1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* X86 Mnemonic tables *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_X86_MNEMONIC_TABLES_H
10#undef GET_X86_MNEMONIC_TABLES_H
11
12namespace llvm::X86 {
13
14bool isFSUBRP(unsigned Opcode);
15bool isVPDPBUSDS(unsigned Opcode);
16bool isPUNPCKLWD(unsigned Opcode);
17bool isVREDUCEBF16(unsigned Opcode);
18bool isPUNPCKLQDQ(unsigned Opcode);
19bool isRDFSBASE(unsigned Opcode);
20bool isVPCMOV(unsigned Opcode);
21bool isVDIVSD(unsigned Opcode);
22bool isVCVTTPS2IBS(unsigned Opcode);
23bool isVPEXTRW(unsigned Opcode);
24bool isLODSD(unsigned Opcode);
25bool isVPTESTNMQ(unsigned Opcode);
26bool isCVTSS2SD(unsigned Opcode);
27bool isVGETMANTPD(unsigned Opcode);
28bool isVMOVDQA64(unsigned Opcode);
29bool isINVLPG(unsigned Opcode);
30bool isVGETEXPBF16(unsigned Opcode);
31bool isVBROADCASTF64X4(unsigned Opcode);
32bool isVPERMI2Q(unsigned Opcode);
33bool isVPMOVSXBD(unsigned Opcode);
34bool isVFMSUB132SS(unsigned Opcode);
35bool isVPMOVUSDW(unsigned Opcode);
36bool isAAD(unsigned Opcode);
37bool isIDIV(unsigned Opcode);
38bool isCVTTPS2DQ(unsigned Opcode);
39bool isVBROADCASTF32X8(unsigned Opcode);
40bool isVFMSUBSS(unsigned Opcode);
41bool isEMMS(unsigned Opcode);
42bool isVPDPBSUD(unsigned Opcode);
43bool isPMOVSXWQ(unsigned Opcode);
44bool isPSRLW(unsigned Opcode);
45bool isMOVNTDQA(unsigned Opcode);
46bool isFUCOMPI(unsigned Opcode);
47bool isANDNPS(unsigned Opcode);
48bool isVINSERTF64X2(unsigned Opcode);
49bool isCLTS(unsigned Opcode);
50bool isSETSSBSY(unsigned Opcode);
51bool isVMULPD(unsigned Opcode);
52bool isVFMADDSUB132PS(unsigned Opcode);
53bool isVPMADCSWD(unsigned Opcode);
54bool isVSCATTERPF0DPS(unsigned Opcode);
55bool isXCHG(unsigned Opcode);
56bool isVGATHERPF1QPS(unsigned Opcode);
57bool isVCVTNEPS2BF16(unsigned Opcode);
58bool isVFMADDSS(unsigned Opcode);
59bool isINTO(unsigned Opcode);
60bool isANDPD(unsigned Opcode);
61bool isSEAMCALL(unsigned Opcode);
62bool isSHLD(unsigned Opcode);
63bool isUNPCKHPS(unsigned Opcode);
64bool isVPDPBSSDS(unsigned Opcode);
65bool isSETZUCC(unsigned Opcode);
66bool isSHUFPD(unsigned Opcode);
67bool isFCMOVNB(unsigned Opcode);
68bool isCVTTSS2SI(unsigned Opcode);
69bool isEXTRQ(unsigned Opcode);
70bool isVBROADCASTSS(unsigned Opcode);
71bool isCLUI(unsigned Opcode);
72bool isVINSERTI128(unsigned Opcode);
73bool isVPSHLDW(unsigned Opcode);
74bool isVBLENDPD(unsigned Opcode);
75bool isVSM4KEY4(unsigned Opcode);
76bool isVCVTNEEPH2PS(unsigned Opcode);
77bool isVCVTTSD2SI(unsigned Opcode);
78bool isWRMSRNS(unsigned Opcode);
79bool isCMPSB(unsigned Opcode);
80bool isVRCPBF16(unsigned Opcode);
81bool isMULSS(unsigned Opcode);
82bool isVMRUN(unsigned Opcode);
83bool isVPSRLVD(unsigned Opcode);
84bool isLEAVE(unsigned Opcode);
85bool isVGETMANTPS(unsigned Opcode);
86bool isXSHA256(unsigned Opcode);
87bool isBOUND(unsigned Opcode);
88bool isSFENCE(unsigned Opcode);
89bool isVPHADDD(unsigned Opcode);
90bool isADOX(unsigned Opcode);
91bool isVPSLLQ(unsigned Opcode);
92bool isVCVTPH2HF8(unsigned Opcode);
93bool isPFRSQIT1(unsigned Opcode);
94bool isCLAC(unsigned Opcode);
95bool isKNOTW(unsigned Opcode);
96bool isVCVTPH2PD(unsigned Opcode);
97bool isVAESENC(unsigned Opcode);
98bool isMOVNTI(unsigned Opcode);
99bool isFXCH(unsigned Opcode);
100bool isPOPP(unsigned Opcode);
101bool isVPBLENDMD(unsigned Opcode);
102bool isFSINCOS(unsigned Opcode);
103bool isVPMOVSXBW(unsigned Opcode);
104bool isVPMULLW(unsigned Opcode);
105bool isSTC(unsigned Opcode);
106bool isVPINSRB(unsigned Opcode);
107bool isLWPVAL(unsigned Opcode);
108bool isKXORB(unsigned Opcode);
109bool isRSTORSSP(unsigned Opcode);
110bool isVPRORQ(unsigned Opcode);
111bool isVSM3MSG1(unsigned Opcode);
112bool isFICOM(unsigned Opcode);
113bool isMAXPS(unsigned Opcode);
114bool isFNCLEX(unsigned Opcode);
115bool isVMOVMSKPS(unsigned Opcode);
116bool isVPMOVDB(unsigned Opcode);
117bool isLLWPCB(unsigned Opcode);
118bool isVMULSS(unsigned Opcode);
119bool isAESENCLAST(unsigned Opcode);
120bool isTILEMOVROW(unsigned Opcode);
121bool isVMINMAXPH(unsigned Opcode);
122bool isVPMAXUB(unsigned Opcode);
123bool isAAS(unsigned Opcode);
124bool isFADD(unsigned Opcode);
125bool isJMP(unsigned Opcode);
126bool isXCRYPTECB(unsigned Opcode);
127bool isPFRCPIT1(unsigned Opcode);
128bool isPMULHRW(unsigned Opcode);
129bool isVCVTPH2PS(unsigned Opcode);
130bool isVPBLENDVB(unsigned Opcode);
131bool isPCMPESTRI(unsigned Opcode);
132bool isSENDUIPI(unsigned Opcode);
133bool isFLDLN2(unsigned Opcode);
134bool isVPMACSWD(unsigned Opcode);
135bool isSHA1MSG1(unsigned Opcode);
136bool isVADDPS(unsigned Opcode);
137bool isVCVTPS2DQ(unsigned Opcode);
138bool isPFPNACC(unsigned Opcode);
139bool isFMUL(unsigned Opcode);
140bool isFNSAVE(unsigned Opcode);
141bool isCDQE(unsigned Opcode);
142bool isVPMACSDD(unsigned Opcode);
143bool isVSQRTPS(unsigned Opcode);
144bool isCMPSQ(unsigned Opcode);
145bool isVPSCATTERDD(unsigned Opcode);
146bool isVCVTTSD2USIS(unsigned Opcode);
147bool isVRNDSCALESD(unsigned Opcode);
148bool isSUBPS(unsigned Opcode);
149bool isVMAXSH(unsigned Opcode);
150bool isFLDZ(unsigned Opcode);
151bool isVFNMADD132SS(unsigned Opcode);
152bool isLGDTW(unsigned Opcode);
153bool isTCVTROWPS2PHH(unsigned Opcode);
154bool isINC(unsigned Opcode);
155bool isPABSB(unsigned Opcode);
156bool isVPANDN(unsigned Opcode);
157bool isVPMAXUD(unsigned Opcode);
158bool isVSHA512RNDS2(unsigned Opcode);
159bool isPHADDSW(unsigned Opcode);
160bool isVPMOVSQW(unsigned Opcode);
161bool isADDSUBPS(unsigned Opcode);
162bool isVPMACSSDQL(unsigned Opcode);
163bool isPXOR(unsigned Opcode);
164bool isVPSRAD(unsigned Opcode);
165bool isVPSHAB(unsigned Opcode);
166bool isBTR(unsigned Opcode);
167bool isKORW(unsigned Opcode);
168bool isVRANGESS(unsigned Opcode);
169bool isVCMPPS(unsigned Opcode);
170bool isVPLZCNTD(unsigned Opcode);
171bool isTDPBUUD(unsigned Opcode);
172bool isROUNDPS(unsigned Opcode);
173bool isFABS(unsigned Opcode);
174bool isSUBPD(unsigned Opcode);
175bool isGF2P8MULB(unsigned Opcode);
176bool isTZMSK(unsigned Opcode);
177bool isVMINMAXSD(unsigned Opcode);
178bool isANDPS(unsigned Opcode);
179bool isVEXTRACTF32X8(unsigned Opcode);
180bool isSEAMRET(unsigned Opcode);
181bool isVPCOMW(unsigned Opcode);
182bool isVFIXUPIMMPD(unsigned Opcode);
183bool isKANDND(unsigned Opcode);
184bool isVMRESUME(unsigned Opcode);
185bool isCVTPD2DQ(unsigned Opcode);
186bool isVFNMADD213PS(unsigned Opcode);
187bool isVPEXTRD(unsigned Opcode);
188bool isPACKUSWB(unsigned Opcode);
189bool isVEXTRACTI32X8(unsigned Opcode);
190bool isVHADDPD(unsigned Opcode);
191bool isVPSADBW(unsigned Opcode);
192bool isMOVDQ2Q(unsigned Opcode);
193bool isPUNPCKHBW(unsigned Opcode);
194bool isXOR(unsigned Opcode);
195bool isPSIGNB(unsigned Opcode);
196bool isVPHADDSW(unsigned Opcode);
197bool isFADDP(unsigned Opcode);
198bool isNEG(unsigned Opcode);
199bool isFLDLG2(unsigned Opcode);
200bool isFNOP(unsigned Opcode);
201bool isVMINSS(unsigned Opcode);
202bool isPCMPISTRM(unsigned Opcode);
203bool isVFMADD132SS(unsigned Opcode);
204bool isFDIVRP(unsigned Opcode);
205bool isPUSHAL(unsigned Opcode);
206bool isSUBSD(unsigned Opcode);
207bool isVPBLENDMQ(unsigned Opcode);
208bool isVPMACSDQL(unsigned Opcode);
209bool isVGATHERDPS(unsigned Opcode);
210bool isSYSRET(unsigned Opcode);
211bool isVPADDB(unsigned Opcode);
212bool isXEND(unsigned Opcode);
213bool isWRSSD(unsigned Opcode);
214bool isVMINMAXSS(unsigned Opcode);
215bool isVCVTDQ2PH(unsigned Opcode);
216bool isCVTPD2PS(unsigned Opcode);
217bool isMAXPD(unsigned Opcode);
218bool isRCPSS(unsigned Opcode);
219bool isVMOVAPD(unsigned Opcode);
220bool isVPSUBSB(unsigned Opcode);
221bool isRDTSC(unsigned Opcode);
222bool isVCVTTPS2UDQS(unsigned Opcode);
223bool isVPMADCSSWD(unsigned Opcode);
224bool isVFNMADD213PH(unsigned Opcode);
225bool isVGF2P8AFFINEQB(unsigned Opcode);
226bool isPMOVZXWD(unsigned Opcode);
227bool isPMINUD(unsigned Opcode);
228bool isXSUSLDTRK(unsigned Opcode);
229bool isVCVTPH2UW(unsigned Opcode);
230bool isPADDSW(unsigned Opcode);
231bool isLFENCE(unsigned Opcode);
232bool isCRC32(unsigned Opcode);
233bool isAESENCWIDE256KL(unsigned Opcode);
234bool isMOVAPD(unsigned Opcode);
235bool isVFMADD213PS(unsigned Opcode);
236bool isVPDPWUUDS(unsigned Opcode);
237bool isMOVSLDUP(unsigned Opcode);
238bool isCLDEMOTE(unsigned Opcode);
239bool isVFNMADD231PS(unsigned Opcode);
240bool isVMOVMSKPD(unsigned Opcode);
241bool isPREFETCHT0(unsigned Opcode);
242bool isVCVTNEOBF162PS(unsigned Opcode);
243bool isVPCMPUD(unsigned Opcode);
244bool isVMAXSD(unsigned Opcode);
245bool isVRCP28SD(unsigned Opcode);
246bool isVMAXPS(unsigned Opcode);
247bool isVPMOVD2M(unsigned Opcode);
248bool isVPMACSSWD(unsigned Opcode);
249bool isVUCOMISD(unsigned Opcode);
250bool isLTR(unsigned Opcode);
251bool isVCVTUSI2SH(unsigned Opcode);
252bool isVSCATTERPF1QPS(unsigned Opcode);
253bool isWRGSBASE(unsigned Opcode);
254bool isSTOSQ(unsigned Opcode);
255bool isVSQRTSD(unsigned Opcode);
256bool isVPERMIL2PD(unsigned Opcode);
257bool isVFCMADDCSH(unsigned Opcode);
258bool isVFMADDSUB213PS(unsigned Opcode);
259bool isPFSUB(unsigned Opcode);
260bool isVSQRTSS(unsigned Opcode);
261bool isVEXPANDPS(unsigned Opcode);
262bool isVPCOMPRESSW(unsigned Opcode);
263bool isPEXTRD(unsigned Opcode);
264bool isVCVTTPS2UQQS(unsigned Opcode);
265bool isSYSEXITQ(unsigned Opcode);
266bool isROUNDSD(unsigned Opcode);
267bool isVFMADD132BF16(unsigned Opcode);
268bool isFCOM(unsigned Opcode);
269bool isVFNMSUBSS(unsigned Opcode);
270bool isKSHIFTLW(unsigned Opcode);
271bool isVMPTRLD(unsigned Opcode);
272bool isSCASD(unsigned Opcode);
273bool isVAESDECLAST(unsigned Opcode);
274bool isVFMADDSUBPS(unsigned Opcode);
275bool isVCVTUQQ2PS(unsigned Opcode);
276bool isVPMOVUSDB(unsigned Opcode);
277bool isVPROTW(unsigned Opcode);
278bool isVDPPS(unsigned Opcode);
279bool isVRSQRT14PD(unsigned Opcode);
280bool isVTESTPD(unsigned Opcode);
281bool isVFNMADD231SH(unsigned Opcode);
282bool isENDBR64(unsigned Opcode);
283bool isMULSD(unsigned Opcode);
284bool isXRSTORS(unsigned Opcode);
285bool isPREFETCHNTA(unsigned Opcode);
286bool isVPCOMD(unsigned Opcode);
287bool isVPCOMUB(unsigned Opcode);
288bool isVPDPBSSD(unsigned Opcode);
289bool isVPHSUBD(unsigned Opcode);
290bool isVBROADCASTI64X2(unsigned Opcode);
291bool isFPATAN(unsigned Opcode);
292bool isLOOPE(unsigned Opcode);
293bool isPCMPEQW(unsigned Opcode);
294bool isVFMADDCSH(unsigned Opcode);
295bool isMOVRS(unsigned Opcode);
296bool isVFMSUBADD132PH(unsigned Opcode);
297bool isKADDW(unsigned Opcode);
298bool isPTEST(unsigned Opcode);
299bool isVPADDSB(unsigned Opcode);
300bool isVRSQRT28PS(unsigned Opcode);
301bool isVGF2P8AFFINEINVQB(unsigned Opcode);
302bool isSERIALIZE(unsigned Opcode);
303bool isVPHADDWQ(unsigned Opcode);
304bool isVRNDSCALESH(unsigned Opcode);
305bool isAAA(unsigned Opcode);
306bool isVADDBF16(unsigned Opcode);
307bool isWRMSRLIST(unsigned Opcode);
308bool isVCVTPH2PSX(unsigned Opcode);
309bool isVFMSUB231PH(unsigned Opcode);
310bool isVGATHERQPD(unsigned Opcode);
311bool isKADDB(unsigned Opcode);
312bool isCVTPD2PI(unsigned Opcode);
313bool isVFNMSUB213PH(unsigned Opcode);
314bool isVPCMPESTRI(unsigned Opcode);
315bool isVPSHRDW(unsigned Opcode);
316bool isXORPS(unsigned Opcode);
317bool isPOP2(unsigned Opcode);
318bool isRDMSRLIST(unsigned Opcode);
319bool isVPDPBUSD(unsigned Opcode);
320bool isVCMPPH(unsigned Opcode);
321bool isVANDNPD(unsigned Opcode);
322bool isSUB(unsigned Opcode);
323bool isVRSQRT28PD(unsigned Opcode);
324bool isVFNMADD132PH(unsigned Opcode);
325bool isVPMACSSWW(unsigned Opcode);
326bool isXSTORE(unsigned Opcode);
327bool isVPROTQ(unsigned Opcode);
328bool isVPHADDBD(unsigned Opcode);
329bool isVPMAXSB(unsigned Opcode);
330bool isVMOVDQU8(unsigned Opcode);
331bool isVPMOVSXWD(unsigned Opcode);
332bool isVMINMAXPD(unsigned Opcode);
333bool isSHA256RNDS2(unsigned Opcode);
334bool isKANDB(unsigned Opcode);
335bool isTPAUSE(unsigned Opcode);
336bool isPUSH(unsigned Opcode);
337bool isVRNDSCALESS(unsigned Opcode);
338bool isVRNDSCALEBF16(unsigned Opcode);
339bool isVPCMPISTRI(unsigned Opcode);
340bool isSTGI(unsigned Opcode);
341bool isSBB(unsigned Opcode);
342bool isBLCS(unsigned Opcode);
343bool isVCVTSD2SH(unsigned Opcode);
344bool isVPERMW(unsigned Opcode);
345bool isXRESLDTRK(unsigned Opcode);
346bool isAESENC256KL(unsigned Opcode);
347bool isVGATHERDPD(unsigned Opcode);
348bool isHRESET(unsigned Opcode);
349bool isVFMSUBADD231PD(unsigned Opcode);
350bool isVFRCZSS(unsigned Opcode);
351bool isMINPS(unsigned Opcode);
352bool isFPREM1(unsigned Opcode);
353bool isVPCMPUB(unsigned Opcode);
354bool isVSQRTPD(unsigned Opcode);
355bool isVFRCZPS(unsigned Opcode);
356bool isVFNMADD213SS(unsigned Opcode);
357bool isVPSHRDVQ(unsigned Opcode);
358bool isVPMOVDW(unsigned Opcode);
359bool isVCVTPH2HF8S(unsigned Opcode);
360bool isVBROADCASTSD(unsigned Opcode);
361bool isVSHUFPD(unsigned Opcode);
362bool isVPSUBSW(unsigned Opcode);
363bool isKUNPCKBW(unsigned Opcode);
364bool isVPBLENDD(unsigned Opcode);
365bool isUNPCKHPD(unsigned Opcode);
366bool isVFNMADD231SD(unsigned Opcode);
367bool isVPBROADCASTMW2D(unsigned Opcode);
368bool isVPMULTISHIFTQB(unsigned Opcode);
369bool isVP2INTERSECTQ(unsigned Opcode);
370bool isVFNMSUB132BF16(unsigned Opcode);
371bool isVFMADD213BF16(unsigned Opcode);
372bool isVPUNPCKHWD(unsigned Opcode);
373bool isVPERM2F128(unsigned Opcode);
374bool isINSD(unsigned Opcode);
375bool isLFS(unsigned Opcode);
376bool isFMULP(unsigned Opcode);
377bool isCWD(unsigned Opcode);
378bool isVDIVSS(unsigned Opcode);
379bool isVPSRLQ(unsigned Opcode);
380bool isFSQRT(unsigned Opcode);
381bool isJRCXZ(unsigned Opcode);
382bool isVPMOVMSKB(unsigned Opcode);
383bool isAESDEC256KL(unsigned Opcode);
384bool isFLDENV(unsigned Opcode);
385bool isVPHSUBWD(unsigned Opcode);
386bool isWBNOINVD(unsigned Opcode);
387bool isVEXPANDPD(unsigned Opcode);
388bool isFYL2XP1(unsigned Opcode);
389bool isPREFETCHT2(unsigned Opcode);
390bool isVPDPBSUDS(unsigned Opcode);
391bool isVSHA512MSG2(unsigned Opcode);
392bool isPMULHUW(unsigned Opcode);
393bool isKANDNB(unsigned Opcode);
394bool isVCVTUW2PH(unsigned Opcode);
395bool isAESDECWIDE256KL(unsigned Opcode);
396bool isVPGATHERDD(unsigned Opcode);
397bool isVREDUCESH(unsigned Opcode);
398bool isPOPFQ(unsigned Opcode);
399bool isPAVGUSB(unsigned Opcode);
400bool isVALIGND(unsigned Opcode);
401bool isVPHMINPOSUW(unsigned Opcode);
402bool isLIDTD(unsigned Opcode);
403bool isVPERMT2PD(unsigned Opcode);
404bool isVMLAUNCH(unsigned Opcode);
405bool isVPXORQ(unsigned Opcode);
406bool isMOVNTDQ(unsigned Opcode);
407bool isPOP2P(unsigned Opcode);
408bool isVADDPD(unsigned Opcode);
409bool isSMSW(unsigned Opcode);
410bool isVEXP2PD(unsigned Opcode);
411bool isPMULUDQ(unsigned Opcode);
412bool isIRET(unsigned Opcode);
413bool isMULPS(unsigned Opcode);
414bool isTDPBF8PS(unsigned Opcode);
415bool isVFNMSUBPD(unsigned Opcode);
416bool isPHADDW(unsigned Opcode);
417bool isRDSEED(unsigned Opcode);
418bool isVPSHLW(unsigned Opcode);
419bool isRMPUPDATE(unsigned Opcode);
420bool isVFMADD231PH(unsigned Opcode);
421bool isVPSHAD(unsigned Opcode);
422bool isCLWB(unsigned Opcode);
423bool isPSUBUSB(unsigned Opcode);
424bool isVCVTTSD2USI(unsigned Opcode);
425bool isVEXTRACTPS(unsigned Opcode);
426bool isMOVLPD(unsigned Opcode);
427bool isLGDTD(unsigned Opcode);
428bool isVPBROADCASTMB2Q(unsigned Opcode);
429bool isOUT(unsigned Opcode);
430bool isVMSAVE(unsigned Opcode);
431bool isVCVTQQ2PD(unsigned Opcode);
432bool isVFMADD213PH(unsigned Opcode);
433bool isFCMOVBE(unsigned Opcode);
434bool isMOVSHDUP(unsigned Opcode);
435bool isVPMOVUSQB(unsigned Opcode);
436bool isFIST(unsigned Opcode);
437bool isHADDPD(unsigned Opcode);
438bool isPACKSSWB(unsigned Opcode);
439bool isVPMACSSDQH(unsigned Opcode);
440bool isVFNMSUB132SD(unsigned Opcode);
441bool isVPMASKMOVQ(unsigned Opcode);
442bool isVCOMPRESSPD(unsigned Opcode);
443bool isVFMADD213SS(unsigned Opcode);
444bool isVPCMPQ(unsigned Opcode);
445bool isVADDSH(unsigned Opcode);
446bool isVFNMADDSD(unsigned Opcode);
447bool isUMWAIT(unsigned Opcode);
448bool isVPUNPCKHDQ(unsigned Opcode);
449bool isLCALL(unsigned Opcode);
450bool isAESDEC128KL(unsigned Opcode);
451bool isVSUBPS(unsigned Opcode);
452bool isFSTP(unsigned Opcode);
453bool isVCVTUDQ2PD(unsigned Opcode);
454bool isVPMOVSWB(unsigned Opcode);
455bool isVPANDNQ(unsigned Opcode);
456bool isSYSENTER(unsigned Opcode);
457bool isVPHADDWD(unsigned Opcode);
458bool isVMOVHPD(unsigned Opcode);
459bool isMOVHPD(unsigned Opcode);
460bool isVDIVPH(unsigned Opcode);
461bool isFFREE(unsigned Opcode);
462bool isVGATHERPF1DPS(unsigned Opcode);
463bool isVPCMPESTRIQ(unsigned Opcode);
464bool isVFNMADD231PD(unsigned Opcode);
465bool isVFCMULCPH(unsigned Opcode);
466bool isVPADDD(unsigned Opcode);
467bool isVPCOMUQ(unsigned Opcode);
468bool isVSM3MSG2(unsigned Opcode);
469bool isVERR(unsigned Opcode);
470bool isKORTESTQ(unsigned Opcode);
471bool isVFMSUB132SD(unsigned Opcode);
472bool isTILEZERO(unsigned Opcode);
473bool isPFADD(unsigned Opcode);
474bool isVCVTSI2SD(unsigned Opcode);
475bool isTILELOADDRS(unsigned Opcode);
476bool isVSTMXCSR(unsigned Opcode);
477bool isVCVTTSH2SI(unsigned Opcode);
478bool isRET(unsigned Opcode);
479bool isLZCNT(unsigned Opcode);
480bool isMULPD(unsigned Opcode);
481bool isVBROADCASTI32X2(unsigned Opcode);
482bool isVCVTPH2W(unsigned Opcode);
483bool isCQO(unsigned Opcode);
484bool isFSUBR(unsigned Opcode);
485bool isDPPD(unsigned Opcode);
486bool isFCOS(unsigned Opcode);
487bool isXSAVES(unsigned Opcode);
488bool isTZCNT(unsigned Opcode);
489bool isLJMP(unsigned Opcode);
490bool isCMOVCC(unsigned Opcode);
491bool isVCVTBIASPH2HF8(unsigned Opcode);
492bool isINVEPT(unsigned Opcode);
493bool isADDSUBPD(unsigned Opcode);
494bool isVCVTSS2SD(unsigned Opcode);
495bool isVMOVSHDUP(unsigned Opcode);
496bool isKSHIFTRD(unsigned Opcode);
497bool isVPTERNLOGD(unsigned Opcode);
498bool isPADDQ(unsigned Opcode);
499bool isVEXTRACTI64X4(unsigned Opcode);
500bool isVFMSUB231SS(unsigned Opcode);
501bool isVPCMPEQB(unsigned Opcode);
502bool isLEA(unsigned Opcode);
503bool isPSUBB(unsigned Opcode);
504bool isKADDQ(unsigned Opcode);
505bool isMOVSX(unsigned Opcode);
506bool isVALIGNQ(unsigned Opcode);
507bool isVCVTNE2PS2BF16(unsigned Opcode);
508bool isVPSRAW(unsigned Opcode);
509bool isVFMSUBADD231PH(unsigned Opcode);
510bool isCVTDQ2PS(unsigned Opcode);
511bool isFBLD(unsigned Opcode);
512bool isLMSW(unsigned Opcode);
513bool isVRNDSCALEPH(unsigned Opcode);
514bool isMINSS(unsigned Opcode);
515bool isWRMSR(unsigned Opcode);
516bool isFSCALE(unsigned Opcode);
517bool isVFNMADD213SH(unsigned Opcode);
518bool isIMULZU(unsigned Opcode);
519bool isVPHADDUBD(unsigned Opcode);
520bool isRDSSPQ(unsigned Opcode);
521bool isVCVTBF162IBS(unsigned Opcode);
522bool isLGDT(unsigned Opcode);
523bool isVPSHLDVD(unsigned Opcode);
524bool isPFCMPGT(unsigned Opcode);
525bool isJCXZ(unsigned Opcode);
526bool isVPMOVZXBW(unsigned Opcode);
527bool isVFMADDSUB231PD(unsigned Opcode);
528bool isVBLENDMPD(unsigned Opcode);
529bool isHSUBPS(unsigned Opcode);
530bool isPREFETCHIT0(unsigned Opcode);
531bool isKTESTD(unsigned Opcode);
532bool isVCVTNEOPH2PS(unsigned Opcode);
533bool isVBLENDVPD(unsigned Opcode);
534bool isVCVTSS2USI(unsigned Opcode);
535bool isVCVTTPS2DQS(unsigned Opcode);
536bool isVPANDD(unsigned Opcode);
537bool isPMINSW(unsigned Opcode);
538bool isSTAC(unsigned Opcode);
539bool isVFMSUB213PS(unsigned Opcode);
540bool isPOPAL(unsigned Opcode);
541bool isVCVTPS2UQQ(unsigned Opcode);
542bool isRDRAND(unsigned Opcode);
543bool isJCC(unsigned Opcode);
544bool isVPMINSQ(unsigned Opcode);
545bool isVADDSD(unsigned Opcode);
546bool isDPPS(unsigned Opcode);
547bool isPINSRQ(unsigned Opcode);
548bool isVUCOMISS(unsigned Opcode);
549bool isVPDPWSUD(unsigned Opcode);
550bool isKANDNW(unsigned Opcode);
551bool isAOR(unsigned Opcode);
552bool isPMAXUB(unsigned Opcode);
553bool isANDNPD(unsigned Opcode);
554bool isINVPCID(unsigned Opcode);
555bool isRDGSBASE(unsigned Opcode);
556bool isVPMOVSQD(unsigned Opcode);
557bool isBT(unsigned Opcode);
558bool isVPROLVQ(unsigned Opcode);
559bool isVFMADDSUB132PD(unsigned Opcode);
560bool isRORX(unsigned Opcode);
561bool isPADDUSW(unsigned Opcode);
562bool isPFNACC(unsigned Opcode);
563bool isAND(unsigned Opcode);
564bool isPSLLQ(unsigned Opcode);
565bool isVFMSUB132PH(unsigned Opcode);
566bool isXSAVE(unsigned Opcode);
567bool isKNOTQ(unsigned Opcode);
568bool isXTEST(unsigned Opcode);
569bool isVINSERTPS(unsigned Opcode);
570bool isXSAVEOPT(unsigned Opcode);
571bool isLDS(unsigned Opcode);
572bool isVFMADDSUB213PD(unsigned Opcode);
573bool isVINSERTF32X4(unsigned Opcode);
574bool isVRSQRTPS(unsigned Opcode);
575bool isVSUBPH(unsigned Opcode);
576bool isPMOVSXBW(unsigned Opcode);
577bool isVPSRLDQ(unsigned Opcode);
578bool isADC(unsigned Opcode);
579bool isPHADDD(unsigned Opcode);
580bool isVDPPHPS(unsigned Opcode);
581bool isVMINPH(unsigned Opcode);
582bool isVMINSD(unsigned Opcode);
583bool isVROUNDPD(unsigned Opcode);
584bool isVFCMADDCPH(unsigned Opcode);
585bool isINCSSPQ(unsigned Opcode);
586bool isVPUNPCKLDQ(unsigned Opcode);
587bool isVMINSH(unsigned Opcode);
588bool isINSERTQ(unsigned Opcode);
589bool isBLCI(unsigned Opcode);
590bool isHLT(unsigned Opcode);
591bool isVPCOMUW(unsigned Opcode);
592bool isVPMOVSXDQ(unsigned Opcode);
593bool isVFNMSUB231PS(unsigned Opcode);
594bool isVFNMSUB213SH(unsigned Opcode);
595bool isVCVTTPD2UQQ(unsigned Opcode);
596bool isSQRTSS(unsigned Opcode);
597bool isIMUL(unsigned Opcode);
598bool isVCVTSS2SI(unsigned Opcode);
599bool isPUSHAW(unsigned Opcode);
600bool isSTOSD(unsigned Opcode);
601bool isPSRLDQ(unsigned Opcode);
602bool isVSCATTERQPS(unsigned Opcode);
603bool isFIDIV(unsigned Opcode);
604bool isVFMSUB213PD(unsigned Opcode);
605bool isVFMADDSUB231PH(unsigned Opcode);
606bool isTDCALL(unsigned Opcode);
607bool isPVALIDATE(unsigned Opcode);
608bool isVPSHUFLW(unsigned Opcode);
609bool isPCLMULQDQ(unsigned Opcode);
610bool isCMPXCHG8B(unsigned Opcode);
611bool isVPMOVM2B(unsigned Opcode);
612bool isVCVTUDQ2PH(unsigned Opcode);
613bool isPEXTRQ(unsigned Opcode);
614bool isXCRYPTCTR(unsigned Opcode);
615bool isVREDUCEPH(unsigned Opcode);
616bool isUCOMISD(unsigned Opcode);
617bool isOUTSD(unsigned Opcode);
618bool isSUBSS(unsigned Opcode);
619bool isVFMSUBPS(unsigned Opcode);
620bool isVPBLENDW(unsigned Opcode);
621bool isVPEXPANDB(unsigned Opcode);
622bool isBZHI(unsigned Opcode);
623bool isVPRORVD(unsigned Opcode);
624bool isRMPQUERY(unsigned Opcode);
625bool isVPSCATTERDQ(unsigned Opcode);
626bool isPSMASH(unsigned Opcode);
627bool isVPSHLDQ(unsigned Opcode);
628bool isVSCATTERPF1DPD(unsigned Opcode);
629bool isMONTMUL(unsigned Opcode);
630bool isVCVTPH2UQQ(unsigned Opcode);
631bool isPSLLD(unsigned Opcode);
632bool isSAR(unsigned Opcode);
633bool isLDTILECFG(unsigned Opcode);
634bool isPMINUB(unsigned Opcode);
635bool isVCVTNEEBF162PS(unsigned Opcode);
636bool isMOVDIR64B(unsigned Opcode);
637bool isSQRTPS(unsigned Opcode);
638bool isSTR(unsigned Opcode);
639bool isKANDNQ(unsigned Opcode);
640bool isBSF(unsigned Opcode);
641bool isINCSSPD(unsigned Opcode);
642bool isVPDPBUUDS(unsigned Opcode);
643bool isCMPXCHG(unsigned Opcode);
644bool isVPSIGNW(unsigned Opcode);
645bool isVCOMISBF16(unsigned Opcode);
646bool isLES(unsigned Opcode);
647bool isCVTSS2SI(unsigned Opcode);
648bool isPFACC(unsigned Opcode);
649bool isFCOMPI(unsigned Opcode);
650bool isPUNPCKHWD(unsigned Opcode);
651bool isVPMOVUSWB(unsigned Opcode);
652bool isVPTESTNMW(unsigned Opcode);
653bool isVPMULDQ(unsigned Opcode);
654bool isSHRX(unsigned Opcode);
655bool isKXORQ(unsigned Opcode);
656bool isVGETEXPSD(unsigned Opcode);
657bool isV4FNMADDPS(unsigned Opcode);
658bool isVFNMSUB231SD(unsigned Opcode);
659bool isVPSHLD(unsigned Opcode);
660bool isPAVGB(unsigned Opcode);
661bool isPMOVZXBD(unsigned Opcode);
662bool isKORTESTW(unsigned Opcode);
663bool isVSHUFPS(unsigned Opcode);
664bool isAESENCWIDE128KL(unsigned Opcode);
665bool isVPXORD(unsigned Opcode);
666bool isVPSHAW(unsigned Opcode);
667bool isVFMSUB132BF16(unsigned Opcode);
668bool isVPERMT2B(unsigned Opcode);
669bool isVFMADD213PD(unsigned Opcode);
670bool isVPGATHERQD(unsigned Opcode);
671bool isVFNMSUB213BF16(unsigned Opcode);
672bool isVCVTPS2IBS(unsigned Opcode);
673bool isVPCMPGTW(unsigned Opcode);
674bool isVMOVRSB(unsigned Opcode);
675bool isVGETMANTSH(unsigned Opcode);
676bool isVANDPS(unsigned Opcode);
677bool isVDIVPS(unsigned Opcode);
678bool isVANDNPS(unsigned Opcode);
679bool isVPBROADCASTW(unsigned Opcode);
680bool isFLDL2T(unsigned Opcode);
681bool isVPERMB(unsigned Opcode);
682bool isFCMOVNBE(unsigned Opcode);
683bool isVCVTTPH2W(unsigned Opcode);
684bool isPMOVZXBQ(unsigned Opcode);
685bool isPF2ID(unsigned Opcode);
686bool isVFNMADD132PD(unsigned Opcode);
687bool isPMULHRSW(unsigned Opcode);
688bool isKADDD(unsigned Opcode);
689bool isVFNMSUB132SH(unsigned Opcode);
690bool isUIRET(unsigned Opcode);
691bool isBSR(unsigned Opcode);
692bool isPCMPEQQ(unsigned Opcode);
693bool isCDQ(unsigned Opcode);
694bool isPMAXSW(unsigned Opcode);
695bool isSIDTD(unsigned Opcode);
696bool isVCVTPS2PHX(unsigned Opcode);
697bool isVPSLLVQ(unsigned Opcode);
698bool isMOVQ(unsigned Opcode);
699bool isPREFETCH(unsigned Opcode);
700bool isVCMPBF16(unsigned Opcode);
701bool isVBMACOR16X16X16(unsigned Opcode);
702bool isCLRSSBSY(unsigned Opcode);
703bool isTCVTROWPS2PHL(unsigned Opcode);
704bool isPSHUFW(unsigned Opcode);
705bool isVPDPWSUDS(unsigned Opcode);
706bool isVPMOVSXBQ(unsigned Opcode);
707bool isFICOMP(unsigned Opcode);
708bool isVFNMSUB132SS(unsigned Opcode);
709bool isVLDMXCSR(unsigned Opcode);
710bool isVPSUBUSW(unsigned Opcode);
711bool isRETF(unsigned Opcode);
712bool isKMOVQ(unsigned Opcode);
713bool isVPADDUSW(unsigned Opcode);
714bool isPACKSSDW(unsigned Opcode);
715bool isUMONITOR(unsigned Opcode);
716bool isENQCMDS(unsigned Opcode);
717bool isVCOMXSD(unsigned Opcode);
718bool isVPMAXSQ(unsigned Opcode);
719bool isVFMSUB213BF16(unsigned Opcode);
720bool isVPERMT2Q(unsigned Opcode);
721bool isFDECSTP(unsigned Opcode);
722bool isVPTESTMQ(unsigned Opcode);
723bool isVRCP14PD(unsigned Opcode);
724bool isARPL(unsigned Opcode);
725bool isVFMSUB213SD(unsigned Opcode);
726bool isJMPABS(unsigned Opcode);
727bool isVUNPCKHPS(unsigned Opcode);
728bool isVFNMADDSS(unsigned Opcode);
729bool isSIDT(unsigned Opcode);
730bool isVPCMPGTB(unsigned Opcode);
731bool isVPRORD(unsigned Opcode);
732bool isVSUBSS(unsigned Opcode);
733bool isPUSHFQ(unsigned Opcode);
734bool isVCVTHF82PH(unsigned Opcode);
735bool isVPCLMULQDQ(unsigned Opcode);
736bool isVPADDUSB(unsigned Opcode);
737bool isVPCMPD(unsigned Opcode);
738bool isMOVSD(unsigned Opcode);
739bool isPSUBUSW(unsigned Opcode);
740bool isVFMSUBADD132PS(unsigned Opcode);
741bool isMOVMSKPS(unsigned Opcode);
742bool isVFIXUPIMMSS(unsigned Opcode);
743bool isMFENCE(unsigned Opcode);
744bool isFTST(unsigned Opcode);
745bool isVPMADDWD(unsigned Opcode);
746bool isPOP(unsigned Opcode);
747bool isPSUBW(unsigned Opcode);
748bool isBSWAP(unsigned Opcode);
749bool isPFMIN(unsigned Opcode);
750bool isVFPCLASSPD(unsigned Opcode);
751bool isVPSHRDVD(unsigned Opcode);
752bool isPADDW(unsigned Opcode);
753bool isCVTSI2SD(unsigned Opcode);
754bool isENQCMD(unsigned Opcode);
755bool isXSHA1(unsigned Opcode);
756bool isVFNMADD132SD(unsigned Opcode);
757bool isMOVZX(unsigned Opcode);
758bool isVFIXUPIMMSD(unsigned Opcode);
759bool isINVD(unsigned Opcode);
760bool isVFIXUPIMMPS(unsigned Opcode);
761bool isMOVDQU(unsigned Opcode);
762bool isVFPCLASSPS(unsigned Opcode);
763bool isVPERMILPS(unsigned Opcode);
764bool isMOVSQ(unsigned Opcode);
765bool isAESDECWIDE128KL(unsigned Opcode);
766bool isROUNDSS(unsigned Opcode);
767bool isVPMOVW2M(unsigned Opcode);
768bool isVPSHUFB(unsigned Opcode);
769bool isVMULSD(unsigned Opcode);
770bool isVPERMI2W(unsigned Opcode);
771bool isVREDUCESS(unsigned Opcode);
772bool isFST(unsigned Opcode);
773bool isVPHSUBW(unsigned Opcode);
774bool isFRNDINT(unsigned Opcode);
775bool isSHR(unsigned Opcode);
776bool isLOOPNE(unsigned Opcode);
777bool isVCVTTPH2UQQ(unsigned Opcode);
778bool isSHA1NEXTE(unsigned Opcode);
779bool isVFMADD132SD(unsigned Opcode);
780bool isPSRAW(unsigned Opcode);
781bool isVPBROADCASTQ(unsigned Opcode);
782bool isCLC(unsigned Opcode);
783bool isPOPAW(unsigned Opcode);
784bool isTCMMIMFP16PS(unsigned Opcode);
785bool isVCVTQQ2PH(unsigned Opcode);
786bool isVCVTTPS2UQQ(unsigned Opcode);
787bool isVMOVUPD(unsigned Opcode);
788bool isFPTAN(unsigned Opcode);
789bool isVMASKMOVPD(unsigned Opcode);
790bool isVMOVLHPS(unsigned Opcode);
791bool isAESKEYGENASSIST(unsigned Opcode);
792bool isXSAVEOPT64(unsigned Opcode);
793bool isXSAVEC(unsigned Opcode);
794bool isVPLZCNTQ(unsigned Opcode);
795bool isVPSUBW(unsigned Opcode);
796bool isCMPCCXADD(unsigned Opcode);
797bool isVFMSUBADD213PH(unsigned Opcode);
798bool isVFMADDSUBPD(unsigned Opcode);
799bool isVPMINSW(unsigned Opcode);
800bool isVFNMSUB132PS(unsigned Opcode);
801bool isVMOVAPS(unsigned Opcode);
802bool isVPEXTRQ(unsigned Opcode);
803bool isVSCALEFSH(unsigned Opcode);
804bool isVCVTPD2PS(unsigned Opcode);
805bool isCLGI(unsigned Opcode);
806bool isVAESDEC(unsigned Opcode);
807bool isPFMUL(unsigned Opcode);
808bool isVCVTBIASPH2BF8S(unsigned Opcode);
809bool isMOVDIRI(unsigned Opcode);
810bool isSHUFPS(unsigned Opcode);
811bool isVFNMSUB231SS(unsigned Opcode);
812bool isVMWRITE(unsigned Opcode);
813bool isVINSERTF128(unsigned Opcode);
814bool isFISUBR(unsigned Opcode);
815bool isVINSERTI32X4(unsigned Opcode);
816bool isVPSLLDQ(unsigned Opcode);
817bool isPOPCNT(unsigned Opcode);
818bool isVXORPD(unsigned Opcode);
819bool isXLATB(unsigned Opcode);
820bool isDIV(unsigned Opcode);
821bool isVPSHLDVQ(unsigned Opcode);
822bool isMOVDDUP(unsigned Opcode);
823bool isVMOVDQU64(unsigned Opcode);
824bool isVPCOMPRESSQ(unsigned Opcode);
825bool isVFMSUBADD132PD(unsigned Opcode);
826bool isVPERMILPD(unsigned Opcode);
827bool isADDSD(unsigned Opcode);
828bool isBLENDPD(unsigned Opcode);
829bool isVPANDQ(unsigned Opcode);
830bool isPMADDUBSW(unsigned Opcode);
831bool isPOPFD(unsigned Opcode);
832bool isCMPSW(unsigned Opcode);
833bool isLDMXCSR(unsigned Opcode);
834bool isVMULPS(unsigned Opcode);
835bool isVROUNDSD(unsigned Opcode);
836bool isVFMADD132PD(unsigned Opcode);
837bool isVPSRAQ(unsigned Opcode);
838bool isVCOMISD(unsigned Opcode);
839bool isVCVTBIASPH2BF8(unsigned Opcode);
840bool isFFREEP(unsigned Opcode);
841bool isVFNMADD213PD(unsigned Opcode);
842bool isVCMPPD(unsigned Opcode);
843bool isVFNMSUB132PH(unsigned Opcode);
844bool isVPHADDBW(unsigned Opcode);
845bool isVPPERM(unsigned Opcode);
846bool isVCVTPS2PD(unsigned Opcode);
847bool isCBW(unsigned Opcode);
848bool isVMOVUPS(unsigned Opcode);
849bool isVPMAXUQ(unsigned Opcode);
850bool isWRSSQ(unsigned Opcode);
851bool isPACKUSDW(unsigned Opcode);
852bool isVCVTTBF162IBS(unsigned Opcode);
853bool isXBEGIN(unsigned Opcode);
854bool isVCVTPD2UQQ(unsigned Opcode);
855bool isFCMOVB(unsigned Opcode);
856bool isNOP(unsigned Opcode);
857bool isVPABSQ(unsigned Opcode);
858bool isVTESTPS(unsigned Opcode);
859bool isPHSUBW(unsigned Opcode);
860bool isPUSH2P(unsigned Opcode);
861bool isFISTTP(unsigned Opcode);
862bool isCFCMOVCC(unsigned Opcode);
863bool isPCMPESTRM(unsigned Opcode);
864bool isVPINSRD(unsigned Opcode);
865bool isVFNMSUB213PS(unsigned Opcode);
866bool isPHSUBD(unsigned Opcode);
867bool isSLDT(unsigned Opcode);
868bool isVCVTTPD2DQS(unsigned Opcode);
869bool isVPMINSD(unsigned Opcode);
870bool isVHADDPS(unsigned Opcode);
871bool isVMOVNTDQ(unsigned Opcode);
872bool isVFRCZSD(unsigned Opcode);
873bool isIBHF(unsigned Opcode);
874bool isVPTESTMW(unsigned Opcode);
875bool isVPMOVZXWD(unsigned Opcode);
876bool isPSADBW(unsigned Opcode);
877bool isVCVTSD2SI(unsigned Opcode);
878bool isVMAXPH(unsigned Opcode);
879bool isLODSB(unsigned Opcode);
880bool isPHMINPOSUW(unsigned Opcode);
881bool isVPROLVD(unsigned Opcode);
882bool isWRFSBASE(unsigned Opcode);
883bool isVRSQRT14PS(unsigned Opcode);
884bool isVPHSUBDQ(unsigned Opcode);
885bool isIRETD(unsigned Opcode);
886bool isVMOVRSD(unsigned Opcode);
887bool isVPMULHRSW(unsigned Opcode);
888bool isCVTSI2SS(unsigned Opcode);
889bool isPI2FD(unsigned Opcode);
890bool isGF2P8AFFINEQB(unsigned Opcode);
891bool isPAND(unsigned Opcode);
892bool isVFNMSUB231SH(unsigned Opcode);
893bool isVMOVHLPS(unsigned Opcode);
894bool isKNOTD(unsigned Opcode);
895bool isPEXTRB(unsigned Opcode);
896bool isVCVTPH2BF8(unsigned Opcode);
897bool isVMMCALL(unsigned Opcode);
898bool isVCVTSH2SS(unsigned Opcode);
899bool isVPUNPCKLQDQ(unsigned Opcode);
900bool isVPERMIL2PS(unsigned Opcode);
901bool isVPCMPGTD(unsigned Opcode);
902bool isCMPXCHG16B(unsigned Opcode);
903bool isTDPHF8PS(unsigned Opcode);
904bool isVZEROUPPER(unsigned Opcode);
905bool isMOVAPS(unsigned Opcode);
906bool isVPCMPW(unsigned Opcode);
907bool isFUCOMPP(unsigned Opcode);
908bool isXSETBV(unsigned Opcode);
909bool isSLWPCB(unsigned Opcode);
910bool isSCASW(unsigned Opcode);
911bool isFCMOVNE(unsigned Opcode);
912bool isPBNDKB(unsigned Opcode);
913bool isVPMULLD(unsigned Opcode);
914bool isVP4DPWSSDS(unsigned Opcode);
915bool isVCVT2PH2HF8(unsigned Opcode);
916bool isPINSRW(unsigned Opcode);
917bool isVCVTSI2SH(unsigned Opcode);
918bool isVINSERTF32X8(unsigned Opcode);
919bool isKSHIFTLB(unsigned Opcode);
920bool isSEAMOPS(unsigned Opcode);
921bool isVPMOVSQB(unsigned Opcode);
922bool isVPMULUDQ(unsigned Opcode);
923bool isVPTESTMD(unsigned Opcode);
924bool isVPHADDDQ(unsigned Opcode);
925bool isKUNPCKDQ(unsigned Opcode);
926bool isT1MSKC(unsigned Opcode);
927bool isVBLENDPS(unsigned Opcode);
928bool isVPCOMB(unsigned Opcode);
929bool isPTWRITE(unsigned Opcode);
930bool isVCVTPH2BF8S(unsigned Opcode);
931bool isCVTPS2PI(unsigned Opcode);
932bool isVPROTD(unsigned Opcode);
933bool isCALL(unsigned Opcode);
934bool isTILELOADDRST1(unsigned Opcode);
935bool isVPERMPS(unsigned Opcode);
936bool isVPSHUFBITQMB(unsigned Opcode);
937bool isVMOVSLDUP(unsigned Opcode);
938bool isINVLPGA(unsigned Opcode);
939bool isVCVTPH2QQ(unsigned Opcode);
940bool isADD(unsigned Opcode);
941bool isPSUBSW(unsigned Opcode);
942bool isSIDTW(unsigned Opcode);
943bool isVEXTRACTF64X2(unsigned Opcode);
944bool isVFNMADD231PH(unsigned Opcode);
945bool isFCOMI(unsigned Opcode);
946bool isRSM(unsigned Opcode);
947bool isVPCOMUD(unsigned Opcode);
948bool isVPMOVZXBQ(unsigned Opcode);
949bool isUWRMSR(unsigned Opcode);
950bool isLGS(unsigned Opcode);
951bool isVMOVNTPD(unsigned Opcode);
952bool isPCMPESTRMQ(unsigned Opcode);
953bool isRDPRU(unsigned Opcode);
954bool isVPUNPCKHBW(unsigned Opcode);
955bool isVUCOMXSD(unsigned Opcode);
956bool isANDN(unsigned Opcode);
957bool isVCVTTPH2UW(unsigned Opcode);
958bool isVMFUNC(unsigned Opcode);
959bool isFIMUL(unsigned Opcode);
960bool isBLCFILL(unsigned Opcode);
961bool isVGATHERPF0DPS(unsigned Opcode);
962bool isVFMSUBADD231PS(unsigned Opcode);
963bool isVREDUCESD(unsigned Opcode);
964bool isVCOMXSH(unsigned Opcode);
965bool isVXORPS(unsigned Opcode);
966bool isPSWAPD(unsigned Opcode);
967bool isPMAXSD(unsigned Opcode);
968bool isVCMPSS(unsigned Opcode);
969bool isEXTRACTPS(unsigned Opcode);
970bool isVPMOVZXBD(unsigned Opcode);
971bool isOUTSW(unsigned Opcode);
972bool isKORTESTB(unsigned Opcode);
973bool isVREDUCEPS(unsigned Opcode);
974bool isPEXTRW(unsigned Opcode);
975bool isFNINIT(unsigned Opcode);
976bool isVCVTPH2IBS(unsigned Opcode);
977bool isROL(unsigned Opcode);
978bool isVCVTPS2QQ(unsigned Opcode);
979bool isVGETMANTPH(unsigned Opcode);
980bool isPUNPCKLDQ(unsigned Opcode);
981bool isPADDD(unsigned Opcode);
982bool isVPSLLD(unsigned Opcode);
983bool isPFCMPGE(unsigned Opcode);
984bool isVGETMANTBF16(unsigned Opcode);
985bool isVSUBBF16(unsigned Opcode);
986bool isVPMOVM2D(unsigned Opcode);
987bool isVCVTTSS2USIS(unsigned Opcode);
988bool isVHSUBPS(unsigned Opcode);
989bool isENDBR32(unsigned Opcode);
990bool isMOVSXD(unsigned Opcode);
991bool isPSIGND(unsigned Opcode);
992bool isVPTEST(unsigned Opcode);
993bool isVPDPWUSD(unsigned Opcode);
994bool isHSUBPD(unsigned Opcode);
995bool isADCX(unsigned Opcode);
996bool isCVTTPD2PI(unsigned Opcode);
997bool isPDEP(unsigned Opcode);
998bool isTDPBUSD(unsigned Opcode);
999bool isVCVTBIASPH2HF8S(unsigned Opcode);
1000bool isVBROADCASTI32X4(unsigned Opcode);
1001bool isVCVTPH2UDQ(unsigned Opcode);
1002bool isVPHADDW(unsigned Opcode);
1003bool isFLDL2E(unsigned Opcode);
1004bool isCLZERO(unsigned Opcode);
1005bool isPBLENDW(unsigned Opcode);
1006bool isVCVTBF162IUBS(unsigned Opcode);
1007bool isVCVTSH2USI(unsigned Opcode);
1008bool isVANDPD(unsigned Opcode);
1009bool isBEXTR(unsigned Opcode);
1010bool isSTD(unsigned Opcode);
1011bool isVAESKEYGENASSIST(unsigned Opcode);
1012bool isCMPSD(unsigned Opcode);
1013bool isMOVSS(unsigned Opcode);
1014bool isVCVTUQQ2PD(unsigned Opcode);
1015bool isVEXTRACTI32X4(unsigned Opcode);
1016bool isFLDCW(unsigned Opcode);
1017bool isINSW(unsigned Opcode);
1018bool isRDPID(unsigned Opcode);
1019bool isVUCOMXSS(unsigned Opcode);
1020bool isKANDQ(unsigned Opcode);
1021bool isV4FMADDPS(unsigned Opcode);
1022bool isPMOVZXWQ(unsigned Opcode);
1023bool isVFPCLASSSD(unsigned Opcode);
1024bool isBLENDPS(unsigned Opcode);
1025bool isVPACKSSDW(unsigned Opcode);
1026bool isVPHSUBBW(unsigned Opcode);
1027bool isVPINSRW(unsigned Opcode);
1028bool isVMINMAXBF16(unsigned Opcode);
1029bool isVSHUFF64X2(unsigned Opcode);
1030bool isVPACKUSWB(unsigned Opcode);
1031bool isVRSQRT28SS(unsigned Opcode);
1032bool isGETSEC(unsigned Opcode);
1033bool isFXAM(unsigned Opcode);
1034bool isVEXTRACTF64X4(unsigned Opcode);
1035bool isBLSR(unsigned Opcode);
1036bool isFILD(unsigned Opcode);
1037bool isRETFQ(unsigned Opcode);
1038bool isVADDSS(unsigned Opcode);
1039bool isCOMISS(unsigned Opcode);
1040bool isCLI(unsigned Opcode);
1041bool isVERW(unsigned Opcode);
1042bool isBTC(unsigned Opcode);
1043bool isVPHADDUBQ(unsigned Opcode);
1044bool isVPORQ(unsigned Opcode);
1045bool isORPD(unsigned Opcode);
1046bool isVMOVSS(unsigned Opcode);
1047bool isVPSUBD(unsigned Opcode);
1048bool isVGATHERPF1QPD(unsigned Opcode);
1049bool isENCODEKEY256(unsigned Opcode);
1050bool isGF2P8AFFINEINVQB(unsigned Opcode);
1051bool isXRSTOR64(unsigned Opcode);
1052bool isKANDW(unsigned Opcode);
1053bool isLODSQ(unsigned Opcode);
1054bool isVMOVRSW(unsigned Opcode);
1055bool isVSUBSH(unsigned Opcode);
1056bool isLSS(unsigned Opcode);
1057bool isPMOVSXBQ(unsigned Opcode);
1058bool isVCVTTSD2SIS(unsigned Opcode);
1059bool isVCMPSH(unsigned Opcode);
1060bool isVFMADD132PS(unsigned Opcode);
1061bool isVPACKSSWB(unsigned Opcode);
1062bool isPCMPGTQ(unsigned Opcode);
1063bool isVFMADD132SH(unsigned Opcode);
1064bool isVCVTUQQ2PH(unsigned Opcode);
1065bool isVCVTQQ2PS(unsigned Opcode);
1066bool isVCVTTSS2USI(unsigned Opcode);
1067bool isVPMOVM2Q(unsigned Opcode);
1068bool isVMOVD(unsigned Opcode);
1069bool isVCVTTPS2QQS(unsigned Opcode);
1070bool isVSQRTBF16(unsigned Opcode);
1071bool isVFPCLASSPH(unsigned Opcode);
1072bool isVCVTSS2SH(unsigned Opcode);
1073bool isSCASB(unsigned Opcode);
1074bool isPSRLD(unsigned Opcode);
1075bool isVADDPH(unsigned Opcode);
1076bool isFSUB(unsigned Opcode);
1077bool isVCVTTPH2IBS(unsigned Opcode);
1078bool isVEXTRACTI64X2(unsigned Opcode);
1079bool isVPSHLDD(unsigned Opcode);
1080bool isPMINUW(unsigned Opcode);
1081bool isPSUBSB(unsigned Opcode);
1082bool isVCVT2PS2PHX(unsigned Opcode);
1083bool isVPCMPEQD(unsigned Opcode);
1084bool isVPSCATTERQD(unsigned Opcode);
1085bool isKXNORB(unsigned Opcode);
1086bool isLDDQU(unsigned Opcode);
1087bool isMASKMOVQ(unsigned Opcode);
1088bool isPABSW(unsigned Opcode);
1089bool isVPCOMQ(unsigned Opcode);
1090bool isVPROLD(unsigned Opcode);
1091bool isVSCATTERDPD(unsigned Opcode);
1092bool isFXRSTOR(unsigned Opcode);
1093bool isVPCMPUW(unsigned Opcode);
1094bool isWBINVD(unsigned Opcode);
1095bool isVCVTTPD2UDQ(unsigned Opcode);
1096bool isERETU(unsigned Opcode);
1097bool isPFRCPIT2(unsigned Opcode);
1098bool isVPERMT2W(unsigned Opcode);
1099bool isVEXTRACTF32X4(unsigned Opcode);
1100bool isVGATHERPF0DPD(unsigned Opcode);
1101bool isVBROADCASTF32X2(unsigned Opcode);
1102bool isVRCP14SD(unsigned Opcode);
1103bool isLAHF(unsigned Opcode);
1104bool isPABSD(unsigned Opcode);
1105bool isPINSRB(unsigned Opcode);
1106bool isSKINIT(unsigned Opcode);
1107bool isENTER(unsigned Opcode);
1108bool isVCVTSI2SS(unsigned Opcode);
1109bool isVFMADD231PD(unsigned Opcode);
1110bool isLOADIWKEY(unsigned Opcode);
1111bool isVMOVNTDQA(unsigned Opcode);
1112bool isVPERMT2PS(unsigned Opcode);
1113bool isPUSHF(unsigned Opcode);
1114bool isMPSADBW(unsigned Opcode);
1115bool isVMINMAXSH(unsigned Opcode);
1116bool isVRSQRT14SS(unsigned Opcode);
1117bool isVCVTDQ2PD(unsigned Opcode);
1118bool isVORPS(unsigned Opcode);
1119bool isVPEXPANDQ(unsigned Opcode);
1120bool isVPSHRDD(unsigned Opcode);
1121bool isTDPBSSD(unsigned Opcode);
1122bool isTESTUI(unsigned Opcode);
1123bool isVFMADDPD(unsigned Opcode);
1124bool isVPANDND(unsigned Opcode);
1125bool isVPMOVSDB(unsigned Opcode);
1126bool isVPBROADCASTB(unsigned Opcode);
1127bool isCVTPI2PD(unsigned Opcode);
1128bool isVPERMI2B(unsigned Opcode);
1129bool isVPMINSB(unsigned Opcode);
1130bool isLAR(unsigned Opcode);
1131bool isINVLPGB(unsigned Opcode);
1132bool isTLBSYNC(unsigned Opcode);
1133bool isFDIVP(unsigned Opcode);
1134bool isVPSRLW(unsigned Opcode);
1135bool isVRCP28SS(unsigned Opcode);
1136bool isVMOVHPS(unsigned Opcode);
1137bool isVPMACSSDD(unsigned Opcode);
1138bool isPEXT(unsigned Opcode);
1139bool isVMAXBF16(unsigned Opcode);
1140bool isVRSQRT14SD(unsigned Opcode);
1141bool isVPDPWSSD(unsigned Opcode);
1142bool isVFMSUB231SD(unsigned Opcode);
1143bool isVPMOVZXWQ(unsigned Opcode);
1144bool isXORPD(unsigned Opcode);
1145bool isVMOVDQA(unsigned Opcode);
1146bool isVFNMSUB213SD(unsigned Opcode);
1147bool isVMINPS(unsigned Opcode);
1148bool isVFMSUB231PS(unsigned Opcode);
1149bool isVPCOMPRESSB(unsigned Opcode);
1150bool isVPCMPEQQ(unsigned Opcode);
1151bool isVRCPSS(unsigned Opcode);
1152bool isVSCATTERPF1DPS(unsigned Opcode);
1153bool isVPHADDUBW(unsigned Opcode);
1154bool isVSUBPD(unsigned Opcode);
1155bool isVPSCATTERQQ(unsigned Opcode);
1156bool isVCVTW2PH(unsigned Opcode);
1157bool isVFMADDCPH(unsigned Opcode);
1158bool isVPACKUSDW(unsigned Opcode);
1159bool isVSCALEFSS(unsigned Opcode);
1160bool isAESIMC(unsigned Opcode);
1161bool isVRCP28PS(unsigned Opcode);
1162bool isAAND(unsigned Opcode);
1163bool isDAA(unsigned Opcode);
1164bool isKTESTW(unsigned Opcode);
1165bool isVCVTPD2UDQ(unsigned Opcode);
1166bool isVPADDQ(unsigned Opcode);
1167bool isPALIGNR(unsigned Opcode);
1168bool isPMAXUW(unsigned Opcode);
1169bool isVFMADDSD(unsigned Opcode);
1170bool isPFMAX(unsigned Opcode);
1171bool isVPOR(unsigned Opcode);
1172bool isVPSUBB(unsigned Opcode);
1173bool isVPAVGB(unsigned Opcode);
1174bool isINSB(unsigned Opcode);
1175bool isFYL2X(unsigned Opcode);
1176bool isVFNMSUB132PD(unsigned Opcode);
1177bool isVFNMSUBPS(unsigned Opcode);
1178bool isVFMADD231PS(unsigned Opcode);
1179bool isVCVTTSS2SI(unsigned Opcode);
1180bool isTCMMRLFP16PS(unsigned Opcode);
1181bool isFCOMPP(unsigned Opcode);
1182bool isMOVD(unsigned Opcode);
1183bool isMOVBE(unsigned Opcode);
1184bool isVP2INTERSECTD(unsigned Opcode);
1185bool isVPMULLQ(unsigned Opcode);
1186bool isVSCALEFPS(unsigned Opcode);
1187bool isVPMACSDQH(unsigned Opcode);
1188bool isVPTESTNMD(unsigned Opcode);
1189bool isFCOMP(unsigned Opcode);
1190bool isPREFETCHWT1(unsigned Opcode);
1191bool isVCMPSD(unsigned Opcode);
1192bool isSGDTD(unsigned Opcode);
1193bool isWRUSSD(unsigned Opcode);
1194bool isFSUBP(unsigned Opcode);
1195bool isVUNPCKLPS(unsigned Opcode);
1196bool isVBMACXOR16X16X16(unsigned Opcode);
1197bool isVFNMSUB213SS(unsigned Opcode);
1198bool isROUNDPD(unsigned Opcode);
1199bool isVPMAXSW(unsigned Opcode);
1200bool isVCVTTPH2DQ(unsigned Opcode);
1201bool isVPUNPCKLWD(unsigned Opcode);
1202bool isKSHIFTLD(unsigned Opcode);
1203bool isTCVTROWPS2BF16H(unsigned Opcode);
1204bool isVFMADD231SD(unsigned Opcode);
1205bool isADDPS(unsigned Opcode);
1206bool isVPSLLVD(unsigned Opcode);
1207bool isVFNMADD132SH(unsigned Opcode);
1208bool isVMOVNTPS(unsigned Opcode);
1209bool isVCVTPD2DQ(unsigned Opcode);
1210bool isVPXOR(unsigned Opcode);
1211bool isSTMXCSR(unsigned Opcode);
1212bool isVRCP14SS(unsigned Opcode);
1213bool isUD2(unsigned Opcode);
1214bool isVPOPCNTW(unsigned Opcode);
1215bool isVRSQRTSH(unsigned Opcode);
1216bool isVSCATTERPF0DPD(unsigned Opcode);
1217bool isVFMADDPS(unsigned Opcode);
1218bool isXSAVEC64(unsigned Opcode);
1219bool isVPMADDUBSW(unsigned Opcode);
1220bool isVPMOVZXDQ(unsigned Opcode);
1221bool isVRCP14PS(unsigned Opcode);
1222bool isVSQRTSH(unsigned Opcode);
1223bool isTCVTROWD2PS(unsigned Opcode);
1224bool isLOOP(unsigned Opcode);
1225bool isSTUI(unsigned Opcode);
1226bool isVCVTTPS2UDQ(unsigned Opcode);
1227bool isXABORT(unsigned Opcode);
1228bool isVCOMPRESSPS(unsigned Opcode);
1229bool isVCVTTBF162IUBS(unsigned Opcode);
1230bool isVPADDW(unsigned Opcode);
1231bool isVPSIGND(unsigned Opcode);
1232bool isVRNDSCALEPS(unsigned Opcode);
1233bool isVPHADDUWD(unsigned Opcode);
1234bool isVCVT2PH2HF8S(unsigned Opcode);
1235bool isVDBPSADBW(unsigned Opcode);
1236bool isPSLLW(unsigned Opcode);
1237bool isVPMOVQD(unsigned Opcode);
1238bool isVINSERTI64X4(unsigned Opcode);
1239bool isVPERMI2PS(unsigned Opcode);
1240bool isVMULPH(unsigned Opcode);
1241bool isVPCMPUQ(unsigned Opcode);
1242bool isVCVTUSI2SD(unsigned Opcode);
1243bool isKXNORW(unsigned Opcode);
1244bool isBLCIC(unsigned Opcode);
1245bool isVFNMADD213SD(unsigned Opcode);
1246bool isVMOVLPS(unsigned Opcode);
1247bool isVPMACSWW(unsigned Opcode);
1248bool isPCONFIG(unsigned Opcode);
1249bool isPANDN(unsigned Opcode);
1250bool isVGETEXPPD(unsigned Opcode);
1251bool isVPSRLVQ(unsigned Opcode);
1252bool isUD1(unsigned Opcode);
1253bool isPMAXSB(unsigned Opcode);
1254bool isVPROLQ(unsigned Opcode);
1255bool isVPSRLD(unsigned Opcode);
1256bool isVSCATTERPF1QPD(unsigned Opcode);
1257bool isINT3(unsigned Opcode);
1258bool isXRSTORS64(unsigned Opcode);
1259bool isCVTSD2SI(unsigned Opcode);
1260bool isVMAXSS(unsigned Opcode);
1261bool isVPMINUB(unsigned Opcode);
1262bool isKXNORQ(unsigned Opcode);
1263bool isFLD(unsigned Opcode);
1264bool isVSHUFI32X4(unsigned Opcode);
1265bool isSAHF(unsigned Opcode);
1266bool isPFRSQRT(unsigned Opcode);
1267bool isSHRD(unsigned Opcode);
1268bool isSYSEXIT(unsigned Opcode);
1269bool isXSAVE64(unsigned Opcode);
1270bool isVPMAXSD(unsigned Opcode);
1271bool isCVTTSD2SI(unsigned Opcode);
1272bool isVCVTTSS2SIS(unsigned Opcode);
1273bool isPMOVMSKB(unsigned Opcode);
1274bool isVRANGEPS(unsigned Opcode);
1275bool isVADDSUBPS(unsigned Opcode);
1276bool isVBROADCASTI128(unsigned Opcode);
1277bool isPADDUSB(unsigned Opcode);
1278bool isENCODEKEY128(unsigned Opcode);
1279bool isOR(unsigned Opcode);
1280bool isSTOSW(unsigned Opcode);
1281bool isVCVTTPD2UQQS(unsigned Opcode);
1282bool isPAVGW(unsigned Opcode);
1283bool isVCVTPD2PH(unsigned Opcode);
1284bool isSHLX(unsigned Opcode);
1285bool isVCVTSH2SD(unsigned Opcode);
1286bool isVFMADD231SS(unsigned Opcode);
1287bool isMOVNTSD(unsigned Opcode);
1288bool isFLDPI(unsigned Opcode);
1289bool isVCVTUSI2SS(unsigned Opcode);
1290bool isPMOVSXBD(unsigned Opcode);
1291bool isVPRORVQ(unsigned Opcode);
1292bool isVPERMT2D(unsigned Opcode);
1293bool isADDSS(unsigned Opcode);
1294bool isAADD(unsigned Opcode);
1295bool isVPSRLVW(unsigned Opcode);
1296bool isVRSQRTPH(unsigned Opcode);
1297bool isVLDDQU(unsigned Opcode);
1298bool isKMOVD(unsigned Opcode);
1299bool isENCLV(unsigned Opcode);
1300bool isENCLU(unsigned Opcode);
1301bool isPREFETCHT1(unsigned Opcode);
1302bool isRSQRTPS(unsigned Opcode);
1303bool isVCVTTSH2USI(unsigned Opcode);
1304bool isPADDB(unsigned Opcode);
1305bool isVMASKMOVDQU(unsigned Opcode);
1306bool isPUNPCKLBW(unsigned Opcode);
1307bool isMOV(unsigned Opcode);
1308bool isVCVTTPH2IUBS(unsigned Opcode);
1309bool isMUL(unsigned Opcode);
1310bool isRCL(unsigned Opcode);
1311bool isVRCPSH(unsigned Opcode);
1312bool isPFCMPEQ(unsigned Opcode);
1313bool isMONITOR(unsigned Opcode);
1314bool isFDIVR(unsigned Opcode);
1315bool isPFRCP(unsigned Opcode);
1316bool isPMINSD(unsigned Opcode);
1317bool isVSHUFF32X4(unsigned Opcode);
1318bool isKTESTQ(unsigned Opcode);
1319bool isVCVTTPD2DQ(unsigned Opcode);
1320bool isVPSLLVW(unsigned Opcode);
1321bool isTDPBSUD(unsigned Opcode);
1322bool isVPMINUQ(unsigned Opcode);
1323bool isFIADD(unsigned Opcode);
1324bool isFCMOVNU(unsigned Opcode);
1325bool isVHSUBPD(unsigned Opcode);
1326bool isKSHIFTRQ(unsigned Opcode);
1327bool isMOVUPS(unsigned Opcode);
1328bool isVMCALL(unsigned Opcode);
1329bool isXADD(unsigned Opcode);
1330bool isXRSTOR(unsigned Opcode);
1331bool isVGATHERPF1DPD(unsigned Opcode);
1332bool isRCR(unsigned Opcode);
1333bool isFNSTCW(unsigned Opcode);
1334bool isVPMOVSDW(unsigned Opcode);
1335bool isVFMSUB132SH(unsigned Opcode);
1336bool isVPCONFLICTQ(unsigned Opcode);
1337bool isSWAPGS(unsigned Opcode);
1338bool isVPMOVQ2M(unsigned Opcode);
1339bool isVPSRAVW(unsigned Opcode);
1340bool isSHA256MSG2(unsigned Opcode);
1341bool isDIVSD(unsigned Opcode);
1342bool isPCMPGTB(unsigned Opcode);
1343bool isMOVDQA(unsigned Opcode);
1344bool isVAESENCLAST(unsigned Opcode);
1345bool isKXORW(unsigned Opcode);
1346bool isLIDTW(unsigned Opcode);
1347bool isPMULHW(unsigned Opcode);
1348bool isVINSERTI32X8(unsigned Opcode);
1349bool isVRCPPS(unsigned Opcode);
1350bool isVRSQRTBF16(unsigned Opcode);
1351bool isVGATHERQPS(unsigned Opcode);
1352bool isCTESTCC(unsigned Opcode);
1353bool isPMADDWD(unsigned Opcode);
1354bool isUCOMISS(unsigned Opcode);
1355bool isXGETBV(unsigned Opcode);
1356bool isVCVTPD2QQ(unsigned Opcode);
1357bool isVGETEXPPS(unsigned Opcode);
1358bool isFISTP(unsigned Opcode);
1359bool isVINSERTF64X4(unsigned Opcode);
1360bool isVMOVDQU16(unsigned Opcode);
1361bool isVFMADD132PH(unsigned Opcode);
1362bool isVFMSUBADD213PS(unsigned Opcode);
1363bool isVMOVDQU32(unsigned Opcode);
1364bool isFUCOM(unsigned Opcode);
1365bool isVFNMADD213BF16(unsigned Opcode);
1366bool isHADDPS(unsigned Opcode);
1367bool isCMP(unsigned Opcode);
1368bool isCVTTPS2PI(unsigned Opcode);
1369bool isIRETQ(unsigned Opcode);
1370bool isPF2IW(unsigned Opcode);
1371bool isPSHUFD(unsigned Opcode);
1372bool isVDPPD(unsigned Opcode);
1373bool isPSHUFHW(unsigned Opcode);
1374bool isRMPADJUST(unsigned Opcode);
1375bool isPI2FW(unsigned Opcode);
1376bool isVCVTTPH2QQ(unsigned Opcode);
1377bool isDIVPD(unsigned Opcode);
1378bool isCLFLUSH(unsigned Opcode);
1379bool isVPMINUW(unsigned Opcode);
1380bool isIN(unsigned Opcode);
1381bool isWRPKRU(unsigned Opcode);
1382bool isINSERTPS(unsigned Opcode);
1383bool isAAM(unsigned Opcode);
1384bool isVPHADDUDQ(unsigned Opcode);
1385bool isVSHA512MSG1(unsigned Opcode);
1386bool isDIVPS(unsigned Opcode);
1387bool isKNOTB(unsigned Opcode);
1388bool isBLSFILL(unsigned Opcode);
1389bool isVPCMPGTQ(unsigned Opcode);
1390bool isMINSD(unsigned Opcode);
1391bool isFPREM(unsigned Opcode);
1392bool isVPUNPCKHQDQ(unsigned Opcode);
1393bool isMINPD(unsigned Opcode);
1394bool isVCVTTPD2QQ(unsigned Opcode);
1395bool isVFMSUBPD(unsigned Opcode);
1396bool isV4FMADDSS(unsigned Opcode);
1397bool isCPUID(unsigned Opcode);
1398bool isSETCC(unsigned Opcode);
1399bool isVPDPWUUD(unsigned Opcode);
1400bool isVCVTTPS2IUBS(unsigned Opcode);
1401bool isPMOVSXDQ(unsigned Opcode);
1402bool isMWAIT(unsigned Opcode);
1403bool isVPEXTRB(unsigned Opcode);
1404bool isINVVPID(unsigned Opcode);
1405bool isVPSHUFD(unsigned Opcode);
1406bool isVMINBF16(unsigned Opcode);
1407bool isMOVLPS(unsigned Opcode);
1408bool isVBLENDMPS(unsigned Opcode);
1409bool isPMULLW(unsigned Opcode);
1410bool isVCVTSH2SI(unsigned Opcode);
1411bool isVPMOVSXWQ(unsigned Opcode);
1412bool isFNSTENV(unsigned Opcode);
1413bool isVCVT2PH2BF8(unsigned Opcode);
1414bool isVPERMI2PD(unsigned Opcode);
1415bool isMAXSS(unsigned Opcode);
1416bool isCWDE(unsigned Opcode);
1417bool isVBROADCASTI32X8(unsigned Opcode);
1418bool isINT(unsigned Opcode);
1419bool isENCLS(unsigned Opcode);
1420bool isMOVNTQ(unsigned Opcode);
1421bool isVDIVSH(unsigned Opcode);
1422bool isMOVHLPS(unsigned Opcode);
1423bool isVPMASKMOVD(unsigned Opcode);
1424bool isVMOVSD(unsigned Opcode);
1425bool isVPMINUD(unsigned Opcode);
1426bool isVPCMPISTRM(unsigned Opcode);
1427bool isVGETMANTSD(unsigned Opcode);
1428bool isKSHIFTRW(unsigned Opcode);
1429bool isAESDECLAST(unsigned Opcode);
1430bool isVPTESTMB(unsigned Opcode);
1431bool isVFNMSUB231BF16(unsigned Opcode);
1432bool isVMPTRST(unsigned Opcode);
1433bool isLLDT(unsigned Opcode);
1434bool isMOVSB(unsigned Opcode);
1435bool isTILELOADD(unsigned Opcode);
1436bool isKTESTB(unsigned Opcode);
1437bool isMOVUPD(unsigned Opcode);
1438bool isLKGS(unsigned Opcode);
1439bool isSGDTW(unsigned Opcode);
1440bool isDIVSS(unsigned Opcode);
1441bool isPUNPCKHQDQ(unsigned Opcode);
1442bool isVFMADD213SD(unsigned Opcode);
1443bool isKXORD(unsigned Opcode);
1444bool isVPMOVB2M(unsigned Opcode);
1445bool isVMREAD(unsigned Opcode);
1446bool isVPDPWSSDS(unsigned Opcode);
1447bool isTILERELEASE(unsigned Opcode);
1448bool isVUCOMXSH(unsigned Opcode);
1449bool isCLFLUSHOPT(unsigned Opcode);
1450bool isDAS(unsigned Opcode);
1451bool isVSCALEFPH(unsigned Opcode);
1452bool isVSUBSD(unsigned Opcode);
1453bool isVCOMISS(unsigned Opcode);
1454bool isVMULBF16(unsigned Opcode);
1455bool isORPS(unsigned Opcode);
1456bool isTDPFP16PS(unsigned Opcode);
1457bool isVMAXPD(unsigned Opcode);
1458bool isVPMOVWB(unsigned Opcode);
1459bool isVEXP2PS(unsigned Opcode);
1460bool isVPGATHERDQ(unsigned Opcode);
1461bool isVPSRAVQ(unsigned Opcode);
1462bool isPCMPISTRI(unsigned Opcode);
1463bool isVFMSUB231PD(unsigned Opcode);
1464bool isRDMSR(unsigned Opcode);
1465bool isKORTESTD(unsigned Opcode);
1466bool isVPBLENDMW(unsigned Opcode);
1467bool isPSHUFB(unsigned Opcode);
1468bool isVDPBF16PS(unsigned Opcode);
1469bool isTDPBF16PS(unsigned Opcode);
1470bool isFCMOVE(unsigned Opcode);
1471bool isVFMADD231BF16(unsigned Opcode);
1472bool isCMPSS(unsigned Opcode);
1473bool isMASKMOVDQU(unsigned Opcode);
1474bool isSARX(unsigned Opcode);
1475bool isVPDPWUSDS(unsigned Opcode);
1476bool isSGDT(unsigned Opcode);
1477bool isVFMULCPH(unsigned Opcode);
1478bool isURDMSR(unsigned Opcode);
1479bool isKUNPCKWD(unsigned Opcode);
1480bool isVSCALEFBF16(unsigned Opcode);
1481bool isCVTPS2PD(unsigned Opcode);
1482bool isFBSTP(unsigned Opcode);
1483bool isPSUBQ(unsigned Opcode);
1484bool isFXSAVE64(unsigned Opcode);
1485bool isKMOVW(unsigned Opcode);
1486bool isBTS(unsigned Opcode);
1487bool isVPHADDBQ(unsigned Opcode);
1488bool isFRSTOR(unsigned Opcode);
1489bool isVFMSUB132PD(unsigned Opcode);
1490bool isPMULLD(unsigned Opcode);
1491bool isSHA1MSG2(unsigned Opcode);
1492bool isJECXZ(unsigned Opcode);
1493bool isVCVTUDQ2PS(unsigned Opcode);
1494bool isAESENC(unsigned Opcode);
1495bool isVMINMAXPS(unsigned Opcode);
1496bool isPSIGNW(unsigned Opcode);
1497bool isUNPCKLPD(unsigned Opcode);
1498bool isPUSHP(unsigned Opcode);
1499bool isBLSI(unsigned Opcode);
1500bool isVPTESTNMB(unsigned Opcode);
1501bool isWRUSSQ(unsigned Opcode);
1502bool isVGF2P8MULB(unsigned Opcode);
1503bool isVPUNPCKLBW(unsigned Opcode);
1504bool isVRANGESD(unsigned Opcode);
1505bool isCLD(unsigned Opcode);
1506bool isVSCALEFPD(unsigned Opcode);
1507bool isVCOMXSS(unsigned Opcode);
1508bool isVPERMQ(unsigned Opcode);
1509bool isVPSHLDVW(unsigned Opcode);
1510bool isROR(unsigned Opcode);
1511bool isVFMADDSUB132PH(unsigned Opcode);
1512bool isDEC(unsigned Opcode);
1513bool isVGETEXPSH(unsigned Opcode);
1514bool isAESDEC(unsigned Opcode);
1515bool isKORD(unsigned Opcode);
1516bool isTILELOADDT1(unsigned Opcode);
1517bool isVPMULHW(unsigned Opcode);
1518bool isVMASKMOVPS(unsigned Opcode);
1519bool isPMOVZXDQ(unsigned Opcode);
1520bool isVCVTPS2PH(unsigned Opcode);
1521bool isCVTDQ2PD(unsigned Opcode);
1522bool isVCVTSD2SS(unsigned Opcode);
1523bool isVFMSUB213PH(unsigned Opcode);
1524bool isVPROTB(unsigned Opcode);
1525bool isPINSRD(unsigned Opcode);
1526bool isVMXON(unsigned Opcode);
1527bool isVFCMULCSH(unsigned Opcode);
1528bool isVFMULCSH(unsigned Opcode);
1529bool isVRANGEPD(unsigned Opcode);
1530bool isCMC(unsigned Opcode);
1531bool isVFNMADD231BF16(unsigned Opcode);
1532bool isSHA256MSG1(unsigned Opcode);
1533bool isFLD1(unsigned Opcode);
1534bool isCMPPS(unsigned Opcode);
1535bool isVPAVGW(unsigned Opcode);
1536bool isVFMADD213SH(unsigned Opcode);
1537bool isVPCMPESTRMQ(unsigned Opcode);
1538bool isVPINSRQ(unsigned Opcode);
1539bool isMOVABS(unsigned Opcode);
1540bool isVPSHAQ(unsigned Opcode);
1541bool isRDTSCP(unsigned Opcode);
1542bool isVFNMADD231SS(unsigned Opcode);
1543bool isTEST(unsigned Opcode);
1544bool isVPERMD(unsigned Opcode);
1545bool isVBCSTNESH2PS(unsigned Opcode);
1546bool isVGATHERPF0QPD(unsigned Opcode);
1547bool isVPERM2I128(unsigned Opcode);
1548bool isVMPSADBW(unsigned Opcode);
1549bool isVFNMSUB231PD(unsigned Opcode);
1550bool isPADDSB(unsigned Opcode);
1551bool isMWAITX(unsigned Opcode);
1552bool isMONITORX(unsigned Opcode);
1553bool isVPEXPANDD(unsigned Opcode);
1554bool isVFRCZPD(unsigned Opcode);
1555bool isVRCPPH(unsigned Opcode);
1556bool isFEMMS(unsigned Opcode);
1557bool isVSCATTERQPD(unsigned Opcode);
1558bool isVMOVW(unsigned Opcode);
1559bool isVPBROADCASTD(unsigned Opcode);
1560bool isSTOSB(unsigned Opcode);
1561bool isFUCOMI(unsigned Opcode);
1562bool isVBROADCASTI64X4(unsigned Opcode);
1563bool isFCMOVU(unsigned Opcode);
1564bool isPSHUFLW(unsigned Opcode);
1565bool isCVTPI2PS(unsigned Opcode);
1566bool isVCVTTPD2UDQS(unsigned Opcode);
1567bool isSYSCALL(unsigned Opcode);
1568bool isVFMADD231SH(unsigned Opcode);
1569bool isVPOPCNTB(unsigned Opcode);
1570bool isPMOVZXBW(unsigned Opcode);
1571bool isVCVTDQ2PS(unsigned Opcode);
1572bool isPSUBD(unsigned Opcode);
1573bool isVPCMPEQW(unsigned Opcode);
1574bool isMOVSW(unsigned Opcode);
1575bool isVSM3RNDS2(unsigned Opcode);
1576bool isVPMOVUSQD(unsigned Opcode);
1577bool isCVTTPD2DQ(unsigned Opcode);
1578bool isVPEXPANDW(unsigned Opcode);
1579bool isVUCOMISH(unsigned Opcode);
1580bool isVZEROALL(unsigned Opcode);
1581bool isVPAND(unsigned Opcode);
1582bool isPMULDQ(unsigned Opcode);
1583bool isVPSHUFHW(unsigned Opcode);
1584bool isVPALIGNR(unsigned Opcode);
1585bool isSQRTSD(unsigned Opcode);
1586bool isVCVTTPH2UDQ(unsigned Opcode);
1587bool isVGETEXPPH(unsigned Opcode);
1588bool isADDPD(unsigned Opcode);
1589bool isVFNMADDPD(unsigned Opcode);
1590bool isSTTILECFG(unsigned Opcode);
1591bool isVMINPD(unsigned Opcode);
1592bool isSHA1RNDS4(unsigned Opcode);
1593bool isPBLENDVB(unsigned Opcode);
1594bool isVBROADCASTF128(unsigned Opcode);
1595bool isVPSHRDQ(unsigned Opcode);
1596bool isVAESIMC(unsigned Opcode);
1597bool isCOMISD(unsigned Opcode);
1598bool isVMOVSH(unsigned Opcode);
1599bool isPFSUBR(unsigned Opcode);
1600bool isRDSSPD(unsigned Opcode);
1601bool isWAIT(unsigned Opcode);
1602bool isVFPCLASSSS(unsigned Opcode);
1603bool isPCMPGTD(unsigned Opcode);
1604bool isVGATHERPF0QPS(unsigned Opcode);
1605bool isBLENDVPS(unsigned Opcode);
1606bool isVBROADCASTF32X4(unsigned Opcode);
1607bool isVMOVLPD(unsigned Opcode);
1608bool isVMOVQ(unsigned Opcode);
1609bool isVPMADD52LUQ(unsigned Opcode);
1610bool isVMOVDQU(unsigned Opcode);
1611bool isAESENC128KL(unsigned Opcode);
1612bool isVFMADDSUB231PS(unsigned Opcode);
1613bool isVFNMSUB213PD(unsigned Opcode);
1614bool isVPCONFLICTD(unsigned Opcode);
1615bool isVFMADDSUB213PH(unsigned Opcode);
1616bool isVPHSUBSW(unsigned Opcode);
1617bool isPUNPCKHDQ(unsigned Opcode);
1618bool isVSHUFI64X2(unsigned Opcode);
1619bool isVFMSUBSD(unsigned Opcode);
1620bool isVPORD(unsigned Opcode);
1621bool isRCPPS(unsigned Opcode);
1622bool isVEXTRACTI128(unsigned Opcode);
1623bool isVCVT2PH2BF8S(unsigned Opcode);
1624bool isVPSHRDVW(unsigned Opcode);
1625bool isVUNPCKLPD(unsigned Opcode);
1626bool isVPSRAVD(unsigned Opcode);
1627bool isVMULSH(unsigned Opcode);
1628bool isMOVNTSS(unsigned Opcode);
1629bool isSTI(unsigned Opcode);
1630bool isVSM4RNDS4(unsigned Opcode);
1631bool isVMCLEAR(unsigned Opcode);
1632bool isVPMADD52HUQ(unsigned Opcode);
1633bool isLIDT(unsigned Opcode);
1634bool isPUSH2(unsigned Opcode);
1635bool isRDPKRU(unsigned Opcode);
1636bool isVCVTPS2IUBS(unsigned Opcode);
1637bool isXSAVES64(unsigned Opcode);
1638bool isVPCMPB(unsigned Opcode);
1639bool isVFMSUB231BF16(unsigned Opcode);
1640bool isFINCSTP(unsigned Opcode);
1641bool isKORQ(unsigned Opcode);
1642bool isRDPMC(unsigned Opcode);
1643bool isVEXTRACTF128(unsigned Opcode);
1644bool isMOVMSKPD(unsigned Opcode);
1645bool isVFMSUB231SH(unsigned Opcode);
1646bool isVPSHLB(unsigned Opcode);
1647bool isXCRYPTCBC(unsigned Opcode);
1648bool isSHL(unsigned Opcode);
1649bool isAXOR(unsigned Opcode);
1650bool isVINSERTI64X2(unsigned Opcode);
1651bool isSYSRETQ(unsigned Opcode);
1652bool isVSCATTERPF0QPD(unsigned Opcode);
1653bool isVFMSUB213SH(unsigned Opcode);
1654bool isVPMOVQW(unsigned Opcode);
1655bool isVREDUCEPD(unsigned Opcode);
1656bool isNOT(unsigned Opcode);
1657bool isLWPINS(unsigned Opcode);
1658bool isVSCATTERDPS(unsigned Opcode);
1659bool isVPMOVM2W(unsigned Opcode);
1660bool isVFNMADD132PS(unsigned Opcode);
1661bool isMOVNTPS(unsigned Opcode);
1662bool isVRSQRTSS(unsigned Opcode);
1663bool isKMOVB(unsigned Opcode);
1664bool isCVTSD2SS(unsigned Opcode);
1665bool isVBROADCASTF64X2(unsigned Opcode);
1666bool isVDIVBF16(unsigned Opcode);
1667bool isMOVNTPD(unsigned Opcode);
1668bool isMAXSD(unsigned Opcode);
1669bool isCMPPD(unsigned Opcode);
1670bool isVPCMPESTRM(unsigned Opcode);
1671bool isVFMSUB132PS(unsigned Opcode);
1672bool isVCOMISH(unsigned Opcode);
1673bool isF2XM1(unsigned Opcode);
1674bool isSQRTPD(unsigned Opcode);
1675bool isVFMSUBADDPS(unsigned Opcode);
1676bool isFXTRACT(unsigned Opcode);
1677bool isVP4DPWSSD(unsigned Opcode);
1678bool isTDPBHF8PS(unsigned Opcode);
1679bool isVFMSUBADDPD(unsigned Opcode);
1680bool isVBCSTNEBF162PS(unsigned Opcode);
1681bool isVPGATHERQQ(unsigned Opcode);
1682bool isPCMPEQB(unsigned Opcode);
1683bool isTILESTORED(unsigned Opcode);
1684bool isBLSMSK(unsigned Opcode);
1685bool isVCVTTPS2DQ(unsigned Opcode);
1686bool isVFPCLASSBF16(unsigned Opcode);
1687bool isVRNDSCALEPD(unsigned Opcode);
1688bool isVMLOAD(unsigned Opcode);
1689bool isVPTERNLOGQ(unsigned Opcode);
1690bool isKXNORD(unsigned Opcode);
1691bool isFXSAVE(unsigned Opcode);
1692bool isVUNPCKHPD(unsigned Opcode);
1693bool isCVTPS2DQ(unsigned Opcode);
1694bool isVFMSUB213SS(unsigned Opcode);
1695bool isVPOPCNTD(unsigned Opcode);
1696bool isSALC(unsigned Opcode);
1697bool isV4FNMADDSS(unsigned Opcode);
1698bool isXCRYPTOFB(unsigned Opcode);
1699bool isVORPD(unsigned Opcode);
1700bool isLSL(unsigned Opcode);
1701bool isXCRYPTCFB(unsigned Opcode);
1702bool isVGETEXPSS(unsigned Opcode);
1703bool isPSLLDQ(unsigned Opcode);
1704bool isVPDPBUUD(unsigned Opcode);
1705bool isVMXOFF(unsigned Opcode);
1706bool isBLSIC(unsigned Opcode);
1707bool isMOVLHPS(unsigned Opcode);
1708bool isVMOVRSQ(unsigned Opcode);
1709bool isVFNMSUBSD(unsigned Opcode);
1710bool isVCVTPH2IUBS(unsigned Opcode);
1711bool isVFPCLASSSH(unsigned Opcode);
1712bool isVPSHLQ(unsigned Opcode);
1713bool isVROUNDPS(unsigned Opcode);
1714bool isVSCATTERPF0QPS(unsigned Opcode);
1715bool isERETS(unsigned Opcode);
1716bool isVPERMI2D(unsigned Opcode);
1717bool isFUCOMP(unsigned Opcode);
1718bool isVCVTTPS2QQ(unsigned Opcode);
1719bool isPUSHFD(unsigned Opcode);
1720bool isVPABSD(unsigned Opcode);
1721bool isKORB(unsigned Opcode);
1722bool isVRCP28PD(unsigned Opcode);
1723bool isVROUNDSS(unsigned Opcode);
1724bool isVCVTSD2USI(unsigned Opcode);
1725bool isVPABSB(unsigned Opcode);
1726bool isPMAXUD(unsigned Opcode);
1727bool isVPERMPD(unsigned Opcode);
1728bool isVPMULHUW(unsigned Opcode);
1729bool isFCHS(unsigned Opcode);
1730bool isVPBLENDMB(unsigned Opcode);
1731bool isVGETMANTSS(unsigned Opcode);
1732bool isVPSLLW(unsigned Opcode);
1733bool isVDIVPD(unsigned Opcode);
1734bool isBLCMSK(unsigned Opcode);
1735bool isFDIV(unsigned Opcode);
1736bool isRSQRTSS(unsigned Opcode);
1737bool isPOR(unsigned Opcode);
1738bool isVMOVDQA32(unsigned Opcode);
1739bool isVPHADDUWQ(unsigned Opcode);
1740bool isPSRAD(unsigned Opcode);
1741bool isPREFETCHW(unsigned Opcode);
1742bool isFIDIVR(unsigned Opcode);
1743bool isMOVHPS(unsigned Opcode);
1744bool isVFNMSUB231PH(unsigned Opcode);
1745bool isUNPCKLPS(unsigned Opcode);
1746bool isVPSIGNB(unsigned Opcode);
1747bool isSAVEPREVSSP(unsigned Opcode);
1748bool isVSCALEFSD(unsigned Opcode);
1749bool isFSIN(unsigned Opcode);
1750bool isSCASQ(unsigned Opcode);
1751bool isVCVTTPD2QQS(unsigned Opcode);
1752bool isPCMPGTW(unsigned Opcode);
1753bool isMULX(unsigned Opcode);
1754bool isVPMAXUW(unsigned Opcode);
1755bool isPAUSE(unsigned Opcode);
1756bool isMOVQ2DQ(unsigned Opcode);
1757bool isVPABSW(unsigned Opcode);
1758bool isVBITREVB(unsigned Opcode);
1759bool isVPCOMPRESSD(unsigned Opcode);
1760bool isVPSUBQ(unsigned Opcode);
1761bool isVPMOVUSQW(unsigned Opcode);
1762bool isBLENDVPD(unsigned Opcode);
1763bool isVFNMADD132BF16(unsigned Opcode);
1764bool isVPMOVQB(unsigned Opcode);
1765bool isVBLENDVPS(unsigned Opcode);
1766bool isKSHIFTLQ(unsigned Opcode);
1767bool isPMOVSXWD(unsigned Opcode);
1768bool isPHSUBSW(unsigned Opcode);
1769bool isPSRLQ(unsigned Opcode);
1770bool isVCVTPH2DQ(unsigned Opcode);
1771bool isPCMPESTRIQ(unsigned Opcode);
1772bool isFISUB(unsigned Opcode);
1773bool isVCVTPS2UDQ(unsigned Opcode);
1774bool isVMOVDDUP(unsigned Opcode);
1775bool isPCMPEQD(unsigned Opcode);
1776bool isVRSQRT28SD(unsigned Opcode);
1777bool isTDPHBF8PS(unsigned Opcode);
1778bool isVPOPCNTQ(unsigned Opcode);
1779bool isLODSW(unsigned Opcode);
1780bool isKSHIFTRB(unsigned Opcode);
1781bool isVFNMADDPS(unsigned Opcode);
1782bool isCCMPCC(unsigned Opcode);
1783bool isFXRSTOR64(unsigned Opcode);
1784bool isVFMSUBADD213PD(unsigned Opcode);
1785bool isVSQRTPH(unsigned Opcode);
1786bool isPOPF(unsigned Opcode);
1787bool isVPSUBUSB(unsigned Opcode);
1788bool isTCVTROWPS2BF16L(unsigned Opcode);
1789bool isVPADDSW(unsigned Opcode);
1790bool isPREFETCHIT1(unsigned Opcode);
1791bool isVADDSUBPD(unsigned Opcode);
1792bool isKANDD(unsigned Opcode);
1793bool isPREFETCHRST2(unsigned Opcode);
1794bool isOUTSB(unsigned Opcode);
1795bool isFNSTSW(unsigned Opcode);
1796bool isPMINSB(unsigned Opcode);
1797
1798} // namespace llvm::X86
1799
1800#endif // GET_X86_MNEMONIC_TABLES_H
1801
1802#ifdef GET_X86_MNEMONIC_TABLES_CPP
1803#undef GET_X86_MNEMONIC_TABLES_CPP
1804
1805namespace llvm::X86 {
1806
1807bool isFSUBRP(unsigned Opcode) {
1808 return Opcode == SUBR_FPrST0;
1809}
1810
1811bool isVPDPBUSDS(unsigned Opcode) {
1812 switch (Opcode) {
1813 case VPDPBUSDSYrm:
1814 case VPDPBUSDSYrr:
1815 case VPDPBUSDSZ128rm:
1816 case VPDPBUSDSZ128rmb:
1817 case VPDPBUSDSZ128rmbk:
1818 case VPDPBUSDSZ128rmbkz:
1819 case VPDPBUSDSZ128rmk:
1820 case VPDPBUSDSZ128rmkz:
1821 case VPDPBUSDSZ128rr:
1822 case VPDPBUSDSZ128rrk:
1823 case VPDPBUSDSZ128rrkz:
1824 case VPDPBUSDSZ256rm:
1825 case VPDPBUSDSZ256rmb:
1826 case VPDPBUSDSZ256rmbk:
1827 case VPDPBUSDSZ256rmbkz:
1828 case VPDPBUSDSZ256rmk:
1829 case VPDPBUSDSZ256rmkz:
1830 case VPDPBUSDSZ256rr:
1831 case VPDPBUSDSZ256rrk:
1832 case VPDPBUSDSZ256rrkz:
1833 case VPDPBUSDSZrm:
1834 case VPDPBUSDSZrmb:
1835 case VPDPBUSDSZrmbk:
1836 case VPDPBUSDSZrmbkz:
1837 case VPDPBUSDSZrmk:
1838 case VPDPBUSDSZrmkz:
1839 case VPDPBUSDSZrr:
1840 case VPDPBUSDSZrrk:
1841 case VPDPBUSDSZrrkz:
1842 case VPDPBUSDSrm:
1843 case VPDPBUSDSrr:
1844 return true;
1845 }
1846 return false;
1847}
1848
1849bool isPUNPCKLWD(unsigned Opcode) {
1850 switch (Opcode) {
1851 case MMX_PUNPCKLWDrm:
1852 case MMX_PUNPCKLWDrr:
1853 case PUNPCKLWDrm:
1854 case PUNPCKLWDrr:
1855 return true;
1856 }
1857 return false;
1858}
1859
1860bool isVREDUCEBF16(unsigned Opcode) {
1861 switch (Opcode) {
1862 case VREDUCEBF16Z128rmbi:
1863 case VREDUCEBF16Z128rmbik:
1864 case VREDUCEBF16Z128rmbikz:
1865 case VREDUCEBF16Z128rmi:
1866 case VREDUCEBF16Z128rmik:
1867 case VREDUCEBF16Z128rmikz:
1868 case VREDUCEBF16Z128rri:
1869 case VREDUCEBF16Z128rrik:
1870 case VREDUCEBF16Z128rrikz:
1871 case VREDUCEBF16Z256rmbi:
1872 case VREDUCEBF16Z256rmbik:
1873 case VREDUCEBF16Z256rmbikz:
1874 case VREDUCEBF16Z256rmi:
1875 case VREDUCEBF16Z256rmik:
1876 case VREDUCEBF16Z256rmikz:
1877 case VREDUCEBF16Z256rri:
1878 case VREDUCEBF16Z256rrik:
1879 case VREDUCEBF16Z256rrikz:
1880 case VREDUCEBF16Zrmbi:
1881 case VREDUCEBF16Zrmbik:
1882 case VREDUCEBF16Zrmbikz:
1883 case VREDUCEBF16Zrmi:
1884 case VREDUCEBF16Zrmik:
1885 case VREDUCEBF16Zrmikz:
1886 case VREDUCEBF16Zrri:
1887 case VREDUCEBF16Zrrik:
1888 case VREDUCEBF16Zrrikz:
1889 return true;
1890 }
1891 return false;
1892}
1893
1894bool isPUNPCKLQDQ(unsigned Opcode) {
1895 switch (Opcode) {
1896 case PUNPCKLQDQrm:
1897 case PUNPCKLQDQrr:
1898 return true;
1899 }
1900 return false;
1901}
1902
1903bool isRDFSBASE(unsigned Opcode) {
1904 switch (Opcode) {
1905 case RDFSBASE:
1906 case RDFSBASE64:
1907 return true;
1908 }
1909 return false;
1910}
1911
1912bool isVPCMOV(unsigned Opcode) {
1913 switch (Opcode) {
1914 case VPCMOVYrmr:
1915 case VPCMOVYrrm:
1916 case VPCMOVYrrr:
1917 case VPCMOVYrrr_REV:
1918 case VPCMOVrmr:
1919 case VPCMOVrrm:
1920 case VPCMOVrrr:
1921 case VPCMOVrrr_REV:
1922 return true;
1923 }
1924 return false;
1925}
1926
1927bool isVDIVSD(unsigned Opcode) {
1928 switch (Opcode) {
1929 case VDIVSDZrm_Int:
1930 case VDIVSDZrmk_Int:
1931 case VDIVSDZrmkz_Int:
1932 case VDIVSDZrr_Int:
1933 case VDIVSDZrrb_Int:
1934 case VDIVSDZrrbk_Int:
1935 case VDIVSDZrrbkz_Int:
1936 case VDIVSDZrrk_Int:
1937 case VDIVSDZrrkz_Int:
1938 case VDIVSDrm_Int:
1939 case VDIVSDrr_Int:
1940 return true;
1941 }
1942 return false;
1943}
1944
1945bool isVCVTTPS2IBS(unsigned Opcode) {
1946 switch (Opcode) {
1947 case VCVTTPS2IBSZ128rm:
1948 case VCVTTPS2IBSZ128rmb:
1949 case VCVTTPS2IBSZ128rmbk:
1950 case VCVTTPS2IBSZ128rmbkz:
1951 case VCVTTPS2IBSZ128rmk:
1952 case VCVTTPS2IBSZ128rmkz:
1953 case VCVTTPS2IBSZ128rr:
1954 case VCVTTPS2IBSZ128rrk:
1955 case VCVTTPS2IBSZ128rrkz:
1956 case VCVTTPS2IBSZ256rm:
1957 case VCVTTPS2IBSZ256rmb:
1958 case VCVTTPS2IBSZ256rmbk:
1959 case VCVTTPS2IBSZ256rmbkz:
1960 case VCVTTPS2IBSZ256rmk:
1961 case VCVTTPS2IBSZ256rmkz:
1962 case VCVTTPS2IBSZ256rr:
1963 case VCVTTPS2IBSZ256rrk:
1964 case VCVTTPS2IBSZ256rrkz:
1965 case VCVTTPS2IBSZrm:
1966 case VCVTTPS2IBSZrmb:
1967 case VCVTTPS2IBSZrmbk:
1968 case VCVTTPS2IBSZrmbkz:
1969 case VCVTTPS2IBSZrmk:
1970 case VCVTTPS2IBSZrmkz:
1971 case VCVTTPS2IBSZrr:
1972 case VCVTTPS2IBSZrrb:
1973 case VCVTTPS2IBSZrrbk:
1974 case VCVTTPS2IBSZrrbkz:
1975 case VCVTTPS2IBSZrrk:
1976 case VCVTTPS2IBSZrrkz:
1977 return true;
1978 }
1979 return false;
1980}
1981
1982bool isVPEXTRW(unsigned Opcode) {
1983 switch (Opcode) {
1984 case VPEXTRWZmri:
1985 case VPEXTRWZrri:
1986 case VPEXTRWZrri_REV:
1987 case VPEXTRWmri:
1988 case VPEXTRWrri:
1989 case VPEXTRWrri_REV:
1990 return true;
1991 }
1992 return false;
1993}
1994
1995bool isLODSD(unsigned Opcode) {
1996 return Opcode == LODSL;
1997}
1998
1999bool isVPTESTNMQ(unsigned Opcode) {
2000 switch (Opcode) {
2001 case VPTESTNMQZ128rm:
2002 case VPTESTNMQZ128rmb:
2003 case VPTESTNMQZ128rmbk:
2004 case VPTESTNMQZ128rmk:
2005 case VPTESTNMQZ128rr:
2006 case VPTESTNMQZ128rrk:
2007 case VPTESTNMQZ256rm:
2008 case VPTESTNMQZ256rmb:
2009 case VPTESTNMQZ256rmbk:
2010 case VPTESTNMQZ256rmk:
2011 case VPTESTNMQZ256rr:
2012 case VPTESTNMQZ256rrk:
2013 case VPTESTNMQZrm:
2014 case VPTESTNMQZrmb:
2015 case VPTESTNMQZrmbk:
2016 case VPTESTNMQZrmk:
2017 case VPTESTNMQZrr:
2018 case VPTESTNMQZrrk:
2019 return true;
2020 }
2021 return false;
2022}
2023
2024bool isCVTSS2SD(unsigned Opcode) {
2025 switch (Opcode) {
2026 case CVTSS2SDrm_Int:
2027 case CVTSS2SDrr_Int:
2028 return true;
2029 }
2030 return false;
2031}
2032
2033bool isVGETMANTPD(unsigned Opcode) {
2034 switch (Opcode) {
2035 case VGETMANTPDZ128rmbi:
2036 case VGETMANTPDZ128rmbik:
2037 case VGETMANTPDZ128rmbikz:
2038 case VGETMANTPDZ128rmi:
2039 case VGETMANTPDZ128rmik:
2040 case VGETMANTPDZ128rmikz:
2041 case VGETMANTPDZ128rri:
2042 case VGETMANTPDZ128rrik:
2043 case VGETMANTPDZ128rrikz:
2044 case VGETMANTPDZ256rmbi:
2045 case VGETMANTPDZ256rmbik:
2046 case VGETMANTPDZ256rmbikz:
2047 case VGETMANTPDZ256rmi:
2048 case VGETMANTPDZ256rmik:
2049 case VGETMANTPDZ256rmikz:
2050 case VGETMANTPDZ256rri:
2051 case VGETMANTPDZ256rrik:
2052 case VGETMANTPDZ256rrikz:
2053 case VGETMANTPDZrmbi:
2054 case VGETMANTPDZrmbik:
2055 case VGETMANTPDZrmbikz:
2056 case VGETMANTPDZrmi:
2057 case VGETMANTPDZrmik:
2058 case VGETMANTPDZrmikz:
2059 case VGETMANTPDZrri:
2060 case VGETMANTPDZrrib:
2061 case VGETMANTPDZrribk:
2062 case VGETMANTPDZrribkz:
2063 case VGETMANTPDZrrik:
2064 case VGETMANTPDZrrikz:
2065 return true;
2066 }
2067 return false;
2068}
2069
2070bool isVMOVDQA64(unsigned Opcode) {
2071 switch (Opcode) {
2072 case VMOVDQA64Z128mr:
2073 case VMOVDQA64Z128mrk:
2074 case VMOVDQA64Z128rm:
2075 case VMOVDQA64Z128rmk:
2076 case VMOVDQA64Z128rmkz:
2077 case VMOVDQA64Z128rr:
2078 case VMOVDQA64Z128rr_REV:
2079 case VMOVDQA64Z128rrk:
2080 case VMOVDQA64Z128rrk_REV:
2081 case VMOVDQA64Z128rrkz:
2082 case VMOVDQA64Z128rrkz_REV:
2083 case VMOVDQA64Z256mr:
2084 case VMOVDQA64Z256mrk:
2085 case VMOVDQA64Z256rm:
2086 case VMOVDQA64Z256rmk:
2087 case VMOVDQA64Z256rmkz:
2088 case VMOVDQA64Z256rr:
2089 case VMOVDQA64Z256rr_REV:
2090 case VMOVDQA64Z256rrk:
2091 case VMOVDQA64Z256rrk_REV:
2092 case VMOVDQA64Z256rrkz:
2093 case VMOVDQA64Z256rrkz_REV:
2094 case VMOVDQA64Zmr:
2095 case VMOVDQA64Zmrk:
2096 case VMOVDQA64Zrm:
2097 case VMOVDQA64Zrmk:
2098 case VMOVDQA64Zrmkz:
2099 case VMOVDQA64Zrr:
2100 case VMOVDQA64Zrr_REV:
2101 case VMOVDQA64Zrrk:
2102 case VMOVDQA64Zrrk_REV:
2103 case VMOVDQA64Zrrkz:
2104 case VMOVDQA64Zrrkz_REV:
2105 return true;
2106 }
2107 return false;
2108}
2109
2110bool isINVLPG(unsigned Opcode) {
2111 return Opcode == INVLPG;
2112}
2113
2114bool isVGETEXPBF16(unsigned Opcode) {
2115 switch (Opcode) {
2116 case VGETEXPBF16Z128m:
2117 case VGETEXPBF16Z128mb:
2118 case VGETEXPBF16Z128mbk:
2119 case VGETEXPBF16Z128mbkz:
2120 case VGETEXPBF16Z128mk:
2121 case VGETEXPBF16Z128mkz:
2122 case VGETEXPBF16Z128r:
2123 case VGETEXPBF16Z128rk:
2124 case VGETEXPBF16Z128rkz:
2125 case VGETEXPBF16Z256m:
2126 case VGETEXPBF16Z256mb:
2127 case VGETEXPBF16Z256mbk:
2128 case VGETEXPBF16Z256mbkz:
2129 case VGETEXPBF16Z256mk:
2130 case VGETEXPBF16Z256mkz:
2131 case VGETEXPBF16Z256r:
2132 case VGETEXPBF16Z256rk:
2133 case VGETEXPBF16Z256rkz:
2134 case VGETEXPBF16Zm:
2135 case VGETEXPBF16Zmb:
2136 case VGETEXPBF16Zmbk:
2137 case VGETEXPBF16Zmbkz:
2138 case VGETEXPBF16Zmk:
2139 case VGETEXPBF16Zmkz:
2140 case VGETEXPBF16Zr:
2141 case VGETEXPBF16Zrk:
2142 case VGETEXPBF16Zrkz:
2143 return true;
2144 }
2145 return false;
2146}
2147
2148bool isVBROADCASTF64X4(unsigned Opcode) {
2149 switch (Opcode) {
2150 case VBROADCASTF64X4Zrm:
2151 case VBROADCASTF64X4Zrmk:
2152 case VBROADCASTF64X4Zrmkz:
2153 return true;
2154 }
2155 return false;
2156}
2157
2158bool isVPERMI2Q(unsigned Opcode) {
2159 switch (Opcode) {
2160 case VPERMI2QZ128rm:
2161 case VPERMI2QZ128rmb:
2162 case VPERMI2QZ128rmbk:
2163 case VPERMI2QZ128rmbkz:
2164 case VPERMI2QZ128rmk:
2165 case VPERMI2QZ128rmkz:
2166 case VPERMI2QZ128rr:
2167 case VPERMI2QZ128rrk:
2168 case VPERMI2QZ128rrkz:
2169 case VPERMI2QZ256rm:
2170 case VPERMI2QZ256rmb:
2171 case VPERMI2QZ256rmbk:
2172 case VPERMI2QZ256rmbkz:
2173 case VPERMI2QZ256rmk:
2174 case VPERMI2QZ256rmkz:
2175 case VPERMI2QZ256rr:
2176 case VPERMI2QZ256rrk:
2177 case VPERMI2QZ256rrkz:
2178 case VPERMI2QZrm:
2179 case VPERMI2QZrmb:
2180 case VPERMI2QZrmbk:
2181 case VPERMI2QZrmbkz:
2182 case VPERMI2QZrmk:
2183 case VPERMI2QZrmkz:
2184 case VPERMI2QZrr:
2185 case VPERMI2QZrrk:
2186 case VPERMI2QZrrkz:
2187 return true;
2188 }
2189 return false;
2190}
2191
2192bool isVPMOVSXBD(unsigned Opcode) {
2193 switch (Opcode) {
2194 case VPMOVSXBDYrm:
2195 case VPMOVSXBDYrr:
2196 case VPMOVSXBDZ128rm:
2197 case VPMOVSXBDZ128rmk:
2198 case VPMOVSXBDZ128rmkz:
2199 case VPMOVSXBDZ128rr:
2200 case VPMOVSXBDZ128rrk:
2201 case VPMOVSXBDZ128rrkz:
2202 case VPMOVSXBDZ256rm:
2203 case VPMOVSXBDZ256rmk:
2204 case VPMOVSXBDZ256rmkz:
2205 case VPMOVSXBDZ256rr:
2206 case VPMOVSXBDZ256rrk:
2207 case VPMOVSXBDZ256rrkz:
2208 case VPMOVSXBDZrm:
2209 case VPMOVSXBDZrmk:
2210 case VPMOVSXBDZrmkz:
2211 case VPMOVSXBDZrr:
2212 case VPMOVSXBDZrrk:
2213 case VPMOVSXBDZrrkz:
2214 case VPMOVSXBDrm:
2215 case VPMOVSXBDrr:
2216 return true;
2217 }
2218 return false;
2219}
2220
2221bool isVFMSUB132SS(unsigned Opcode) {
2222 switch (Opcode) {
2223 case VFMSUB132SSZm_Int:
2224 case VFMSUB132SSZmk_Int:
2225 case VFMSUB132SSZmkz_Int:
2226 case VFMSUB132SSZr_Int:
2227 case VFMSUB132SSZrb_Int:
2228 case VFMSUB132SSZrbk_Int:
2229 case VFMSUB132SSZrbkz_Int:
2230 case VFMSUB132SSZrk_Int:
2231 case VFMSUB132SSZrkz_Int:
2232 case VFMSUB132SSm_Int:
2233 case VFMSUB132SSr_Int:
2234 return true;
2235 }
2236 return false;
2237}
2238
2239bool isVPMOVUSDW(unsigned Opcode) {
2240 switch (Opcode) {
2241 case VPMOVUSDWZ128mr:
2242 case VPMOVUSDWZ128mrk:
2243 case VPMOVUSDWZ128rr:
2244 case VPMOVUSDWZ128rrk:
2245 case VPMOVUSDWZ128rrkz:
2246 case VPMOVUSDWZ256mr:
2247 case VPMOVUSDWZ256mrk:
2248 case VPMOVUSDWZ256rr:
2249 case VPMOVUSDWZ256rrk:
2250 case VPMOVUSDWZ256rrkz:
2251 case VPMOVUSDWZmr:
2252 case VPMOVUSDWZmrk:
2253 case VPMOVUSDWZrr:
2254 case VPMOVUSDWZrrk:
2255 case VPMOVUSDWZrrkz:
2256 return true;
2257 }
2258 return false;
2259}
2260
2261bool isAAD(unsigned Opcode) {
2262 return Opcode == AAD8i8;
2263}
2264
2265bool isIDIV(unsigned Opcode) {
2266 switch (Opcode) {
2267 case IDIV16m:
2268 case IDIV16m_EVEX:
2269 case IDIV16m_NF:
2270 case IDIV16r:
2271 case IDIV16r_EVEX:
2272 case IDIV16r_NF:
2273 case IDIV32m:
2274 case IDIV32m_EVEX:
2275 case IDIV32m_NF:
2276 case IDIV32r:
2277 case IDIV32r_EVEX:
2278 case IDIV32r_NF:
2279 case IDIV64m:
2280 case IDIV64m_EVEX:
2281 case IDIV64m_NF:
2282 case IDIV64r:
2283 case IDIV64r_EVEX:
2284 case IDIV64r_NF:
2285 case IDIV8m:
2286 case IDIV8m_EVEX:
2287 case IDIV8m_NF:
2288 case IDIV8r:
2289 case IDIV8r_EVEX:
2290 case IDIV8r_NF:
2291 return true;
2292 }
2293 return false;
2294}
2295
2296bool isCVTTPS2DQ(unsigned Opcode) {
2297 switch (Opcode) {
2298 case CVTTPS2DQrm:
2299 case CVTTPS2DQrr:
2300 return true;
2301 }
2302 return false;
2303}
2304
2305bool isVBROADCASTF32X8(unsigned Opcode) {
2306 switch (Opcode) {
2307 case VBROADCASTF32X8Zrm:
2308 case VBROADCASTF32X8Zrmk:
2309 case VBROADCASTF32X8Zrmkz:
2310 return true;
2311 }
2312 return false;
2313}
2314
2315bool isVFMSUBSS(unsigned Opcode) {
2316 switch (Opcode) {
2317 case VFMSUBSS4mr:
2318 case VFMSUBSS4rm:
2319 case VFMSUBSS4rr:
2320 case VFMSUBSS4rr_REV:
2321 return true;
2322 }
2323 return false;
2324}
2325
2326bool isEMMS(unsigned Opcode) {
2327 return Opcode == MMX_EMMS;
2328}
2329
2330bool isVPDPBSUD(unsigned Opcode) {
2331 switch (Opcode) {
2332 case VPDPBSUDYrm:
2333 case VPDPBSUDYrr:
2334 case VPDPBSUDZ128rm:
2335 case VPDPBSUDZ128rmb:
2336 case VPDPBSUDZ128rmbk:
2337 case VPDPBSUDZ128rmbkz:
2338 case VPDPBSUDZ128rmk:
2339 case VPDPBSUDZ128rmkz:
2340 case VPDPBSUDZ128rr:
2341 case VPDPBSUDZ128rrk:
2342 case VPDPBSUDZ128rrkz:
2343 case VPDPBSUDZ256rm:
2344 case VPDPBSUDZ256rmb:
2345 case VPDPBSUDZ256rmbk:
2346 case VPDPBSUDZ256rmbkz:
2347 case VPDPBSUDZ256rmk:
2348 case VPDPBSUDZ256rmkz:
2349 case VPDPBSUDZ256rr:
2350 case VPDPBSUDZ256rrk:
2351 case VPDPBSUDZ256rrkz:
2352 case VPDPBSUDZrm:
2353 case VPDPBSUDZrmb:
2354 case VPDPBSUDZrmbk:
2355 case VPDPBSUDZrmbkz:
2356 case VPDPBSUDZrmk:
2357 case VPDPBSUDZrmkz:
2358 case VPDPBSUDZrr:
2359 case VPDPBSUDZrrk:
2360 case VPDPBSUDZrrkz:
2361 case VPDPBSUDrm:
2362 case VPDPBSUDrr:
2363 return true;
2364 }
2365 return false;
2366}
2367
2368bool isPMOVSXWQ(unsigned Opcode) {
2369 switch (Opcode) {
2370 case PMOVSXWQrm:
2371 case PMOVSXWQrr:
2372 return true;
2373 }
2374 return false;
2375}
2376
2377bool isPSRLW(unsigned Opcode) {
2378 switch (Opcode) {
2379 case MMX_PSRLWri:
2380 case MMX_PSRLWrm:
2381 case MMX_PSRLWrr:
2382 case PSRLWri:
2383 case PSRLWrm:
2384 case PSRLWrr:
2385 return true;
2386 }
2387 return false;
2388}
2389
2390bool isMOVNTDQA(unsigned Opcode) {
2391 return Opcode == MOVNTDQArm;
2392}
2393
2394bool isFUCOMPI(unsigned Opcode) {
2395 return Opcode == UCOM_FIPr;
2396}
2397
2398bool isANDNPS(unsigned Opcode) {
2399 switch (Opcode) {
2400 case ANDNPSrm:
2401 case ANDNPSrr:
2402 return true;
2403 }
2404 return false;
2405}
2406
2407bool isVINSERTF64X2(unsigned Opcode) {
2408 switch (Opcode) {
2409 case VINSERTF64X2Z256rmi:
2410 case VINSERTF64X2Z256rmik:
2411 case VINSERTF64X2Z256rmikz:
2412 case VINSERTF64X2Z256rri:
2413 case VINSERTF64X2Z256rrik:
2414 case VINSERTF64X2Z256rrikz:
2415 case VINSERTF64X2Zrmi:
2416 case VINSERTF64X2Zrmik:
2417 case VINSERTF64X2Zrmikz:
2418 case VINSERTF64X2Zrri:
2419 case VINSERTF64X2Zrrik:
2420 case VINSERTF64X2Zrrikz:
2421 return true;
2422 }
2423 return false;
2424}
2425
2426bool isCLTS(unsigned Opcode) {
2427 return Opcode == CLTS;
2428}
2429
2430bool isSETSSBSY(unsigned Opcode) {
2431 return Opcode == SETSSBSY;
2432}
2433
2434bool isVMULPD(unsigned Opcode) {
2435 switch (Opcode) {
2436 case VMULPDYrm:
2437 case VMULPDYrr:
2438 case VMULPDZ128rm:
2439 case VMULPDZ128rmb:
2440 case VMULPDZ128rmbk:
2441 case VMULPDZ128rmbkz:
2442 case VMULPDZ128rmk:
2443 case VMULPDZ128rmkz:
2444 case VMULPDZ128rr:
2445 case VMULPDZ128rrk:
2446 case VMULPDZ128rrkz:
2447 case VMULPDZ256rm:
2448 case VMULPDZ256rmb:
2449 case VMULPDZ256rmbk:
2450 case VMULPDZ256rmbkz:
2451 case VMULPDZ256rmk:
2452 case VMULPDZ256rmkz:
2453 case VMULPDZ256rr:
2454 case VMULPDZ256rrk:
2455 case VMULPDZ256rrkz:
2456 case VMULPDZrm:
2457 case VMULPDZrmb:
2458 case VMULPDZrmbk:
2459 case VMULPDZrmbkz:
2460 case VMULPDZrmk:
2461 case VMULPDZrmkz:
2462 case VMULPDZrr:
2463 case VMULPDZrrb:
2464 case VMULPDZrrbk:
2465 case VMULPDZrrbkz:
2466 case VMULPDZrrk:
2467 case VMULPDZrrkz:
2468 case VMULPDrm:
2469 case VMULPDrr:
2470 return true;
2471 }
2472 return false;
2473}
2474
2475bool isVFMADDSUB132PS(unsigned Opcode) {
2476 switch (Opcode) {
2477 case VFMADDSUB132PSYm:
2478 case VFMADDSUB132PSYr:
2479 case VFMADDSUB132PSZ128m:
2480 case VFMADDSUB132PSZ128mb:
2481 case VFMADDSUB132PSZ128mbk:
2482 case VFMADDSUB132PSZ128mbkz:
2483 case VFMADDSUB132PSZ128mk:
2484 case VFMADDSUB132PSZ128mkz:
2485 case VFMADDSUB132PSZ128r:
2486 case VFMADDSUB132PSZ128rk:
2487 case VFMADDSUB132PSZ128rkz:
2488 case VFMADDSUB132PSZ256m:
2489 case VFMADDSUB132PSZ256mb:
2490 case VFMADDSUB132PSZ256mbk:
2491 case VFMADDSUB132PSZ256mbkz:
2492 case VFMADDSUB132PSZ256mk:
2493 case VFMADDSUB132PSZ256mkz:
2494 case VFMADDSUB132PSZ256r:
2495 case VFMADDSUB132PSZ256rk:
2496 case VFMADDSUB132PSZ256rkz:
2497 case VFMADDSUB132PSZm:
2498 case VFMADDSUB132PSZmb:
2499 case VFMADDSUB132PSZmbk:
2500 case VFMADDSUB132PSZmbkz:
2501 case VFMADDSUB132PSZmk:
2502 case VFMADDSUB132PSZmkz:
2503 case VFMADDSUB132PSZr:
2504 case VFMADDSUB132PSZrb:
2505 case VFMADDSUB132PSZrbk:
2506 case VFMADDSUB132PSZrbkz:
2507 case VFMADDSUB132PSZrk:
2508 case VFMADDSUB132PSZrkz:
2509 case VFMADDSUB132PSm:
2510 case VFMADDSUB132PSr:
2511 return true;
2512 }
2513 return false;
2514}
2515
2516bool isVPMADCSWD(unsigned Opcode) {
2517 switch (Opcode) {
2518 case VPMADCSWDrm:
2519 case VPMADCSWDrr:
2520 return true;
2521 }
2522 return false;
2523}
2524
2525bool isVSCATTERPF0DPS(unsigned Opcode) {
2526 return Opcode == VSCATTERPF0DPSm;
2527}
2528
2529bool isXCHG(unsigned Opcode) {
2530 switch (Opcode) {
2531 case XCHG16ar:
2532 case XCHG16rm:
2533 case XCHG16rr:
2534 case XCHG32ar:
2535 case XCHG32rm:
2536 case XCHG32rr:
2537 case XCHG64ar:
2538 case XCHG64rm:
2539 case XCHG64rr:
2540 case XCHG8rm:
2541 case XCHG8rr:
2542 return true;
2543 }
2544 return false;
2545}
2546
2547bool isVGATHERPF1QPS(unsigned Opcode) {
2548 return Opcode == VGATHERPF1QPSm;
2549}
2550
2551bool isVCVTNEPS2BF16(unsigned Opcode) {
2552 switch (Opcode) {
2553 case VCVTNEPS2BF16Yrm:
2554 case VCVTNEPS2BF16Yrr:
2555 case VCVTNEPS2BF16Z128rm:
2556 case VCVTNEPS2BF16Z128rmb:
2557 case VCVTNEPS2BF16Z128rmbk:
2558 case VCVTNEPS2BF16Z128rmbkz:
2559 case VCVTNEPS2BF16Z128rmk:
2560 case VCVTNEPS2BF16Z128rmkz:
2561 case VCVTNEPS2BF16Z128rr:
2562 case VCVTNEPS2BF16Z128rrk:
2563 case VCVTNEPS2BF16Z128rrkz:
2564 case VCVTNEPS2BF16Z256rm:
2565 case VCVTNEPS2BF16Z256rmb:
2566 case VCVTNEPS2BF16Z256rmbk:
2567 case VCVTNEPS2BF16Z256rmbkz:
2568 case VCVTNEPS2BF16Z256rmk:
2569 case VCVTNEPS2BF16Z256rmkz:
2570 case VCVTNEPS2BF16Z256rr:
2571 case VCVTNEPS2BF16Z256rrk:
2572 case VCVTNEPS2BF16Z256rrkz:
2573 case VCVTNEPS2BF16Zrm:
2574 case VCVTNEPS2BF16Zrmb:
2575 case VCVTNEPS2BF16Zrmbk:
2576 case VCVTNEPS2BF16Zrmbkz:
2577 case VCVTNEPS2BF16Zrmk:
2578 case VCVTNEPS2BF16Zrmkz:
2579 case VCVTNEPS2BF16Zrr:
2580 case VCVTNEPS2BF16Zrrk:
2581 case VCVTNEPS2BF16Zrrkz:
2582 case VCVTNEPS2BF16rm:
2583 case VCVTNEPS2BF16rr:
2584 return true;
2585 }
2586 return false;
2587}
2588
2589bool isVFMADDSS(unsigned Opcode) {
2590 switch (Opcode) {
2591 case VFMADDSS4mr:
2592 case VFMADDSS4rm:
2593 case VFMADDSS4rr:
2594 case VFMADDSS4rr_REV:
2595 return true;
2596 }
2597 return false;
2598}
2599
2600bool isINTO(unsigned Opcode) {
2601 return Opcode == INTO;
2602}
2603
2604bool isANDPD(unsigned Opcode) {
2605 switch (Opcode) {
2606 case ANDPDrm:
2607 case ANDPDrr:
2608 return true;
2609 }
2610 return false;
2611}
2612
2613bool isSEAMCALL(unsigned Opcode) {
2614 return Opcode == SEAMCALL;
2615}
2616
2617bool isSHLD(unsigned Opcode) {
2618 switch (Opcode) {
2619 case SHLD16mrCL:
2620 case SHLD16mrCL_EVEX:
2621 case SHLD16mrCL_ND:
2622 case SHLD16mrCL_NF:
2623 case SHLD16mrCL_NF_ND:
2624 case SHLD16mri8:
2625 case SHLD16mri8_EVEX:
2626 case SHLD16mri8_ND:
2627 case SHLD16mri8_NF:
2628 case SHLD16mri8_NF_ND:
2629 case SHLD16rrCL:
2630 case SHLD16rrCL_EVEX:
2631 case SHLD16rrCL_ND:
2632 case SHLD16rrCL_NF:
2633 case SHLD16rrCL_NF_ND:
2634 case SHLD16rri8:
2635 case SHLD16rri8_EVEX:
2636 case SHLD16rri8_ND:
2637 case SHLD16rri8_NF:
2638 case SHLD16rri8_NF_ND:
2639 case SHLD32mrCL:
2640 case SHLD32mrCL_EVEX:
2641 case SHLD32mrCL_ND:
2642 case SHLD32mrCL_NF:
2643 case SHLD32mrCL_NF_ND:
2644 case SHLD32mri8:
2645 case SHLD32mri8_EVEX:
2646 case SHLD32mri8_ND:
2647 case SHLD32mri8_NF:
2648 case SHLD32mri8_NF_ND:
2649 case SHLD32rrCL:
2650 case SHLD32rrCL_EVEX:
2651 case SHLD32rrCL_ND:
2652 case SHLD32rrCL_NF:
2653 case SHLD32rrCL_NF_ND:
2654 case SHLD32rri8:
2655 case SHLD32rri8_EVEX:
2656 case SHLD32rri8_ND:
2657 case SHLD32rri8_NF:
2658 case SHLD32rri8_NF_ND:
2659 case SHLD64mrCL:
2660 case SHLD64mrCL_EVEX:
2661 case SHLD64mrCL_ND:
2662 case SHLD64mrCL_NF:
2663 case SHLD64mrCL_NF_ND:
2664 case SHLD64mri8:
2665 case SHLD64mri8_EVEX:
2666 case SHLD64mri8_ND:
2667 case SHLD64mri8_NF:
2668 case SHLD64mri8_NF_ND:
2669 case SHLD64rrCL:
2670 case SHLD64rrCL_EVEX:
2671 case SHLD64rrCL_ND:
2672 case SHLD64rrCL_NF:
2673 case SHLD64rrCL_NF_ND:
2674 case SHLD64rri8:
2675 case SHLD64rri8_EVEX:
2676 case SHLD64rri8_ND:
2677 case SHLD64rri8_NF:
2678 case SHLD64rri8_NF_ND:
2679 return true;
2680 }
2681 return false;
2682}
2683
2684bool isUNPCKHPS(unsigned Opcode) {
2685 switch (Opcode) {
2686 case UNPCKHPSrm:
2687 case UNPCKHPSrr:
2688 return true;
2689 }
2690 return false;
2691}
2692
2693bool isVPDPBSSDS(unsigned Opcode) {
2694 switch (Opcode) {
2695 case VPDPBSSDSYrm:
2696 case VPDPBSSDSYrr:
2697 case VPDPBSSDSZ128rm:
2698 case VPDPBSSDSZ128rmb:
2699 case VPDPBSSDSZ128rmbk:
2700 case VPDPBSSDSZ128rmbkz:
2701 case VPDPBSSDSZ128rmk:
2702 case VPDPBSSDSZ128rmkz:
2703 case VPDPBSSDSZ128rr:
2704 case VPDPBSSDSZ128rrk:
2705 case VPDPBSSDSZ128rrkz:
2706 case VPDPBSSDSZ256rm:
2707 case VPDPBSSDSZ256rmb:
2708 case VPDPBSSDSZ256rmbk:
2709 case VPDPBSSDSZ256rmbkz:
2710 case VPDPBSSDSZ256rmk:
2711 case VPDPBSSDSZ256rmkz:
2712 case VPDPBSSDSZ256rr:
2713 case VPDPBSSDSZ256rrk:
2714 case VPDPBSSDSZ256rrkz:
2715 case VPDPBSSDSZrm:
2716 case VPDPBSSDSZrmb:
2717 case VPDPBSSDSZrmbk:
2718 case VPDPBSSDSZrmbkz:
2719 case VPDPBSSDSZrmk:
2720 case VPDPBSSDSZrmkz:
2721 case VPDPBSSDSZrr:
2722 case VPDPBSSDSZrrk:
2723 case VPDPBSSDSZrrkz:
2724 case VPDPBSSDSrm:
2725 case VPDPBSSDSrr:
2726 return true;
2727 }
2728 return false;
2729}
2730
2731bool isSETZUCC(unsigned Opcode) {
2732 switch (Opcode) {
2733 case SETZUCCm:
2734 case SETZUCCr:
2735 return true;
2736 }
2737 return false;
2738}
2739
2740bool isSHUFPD(unsigned Opcode) {
2741 switch (Opcode) {
2742 case SHUFPDrmi:
2743 case SHUFPDrri:
2744 return true;
2745 }
2746 return false;
2747}
2748
2749bool isFCMOVNB(unsigned Opcode) {
2750 return Opcode == CMOVNB_F;
2751}
2752
2753bool isCVTTSS2SI(unsigned Opcode) {
2754 switch (Opcode) {
2755 case CVTTSS2SI64rm_Int:
2756 case CVTTSS2SI64rr_Int:
2757 case CVTTSS2SIrm_Int:
2758 case CVTTSS2SIrr_Int:
2759 return true;
2760 }
2761 return false;
2762}
2763
2764bool isEXTRQ(unsigned Opcode) {
2765 switch (Opcode) {
2766 case EXTRQ:
2767 case EXTRQI:
2768 return true;
2769 }
2770 return false;
2771}
2772
2773bool isVBROADCASTSS(unsigned Opcode) {
2774 switch (Opcode) {
2775 case VBROADCASTSSYrm:
2776 case VBROADCASTSSYrr:
2777 case VBROADCASTSSZ128rm:
2778 case VBROADCASTSSZ128rmk:
2779 case VBROADCASTSSZ128rmkz:
2780 case VBROADCASTSSZ128rr:
2781 case VBROADCASTSSZ128rrk:
2782 case VBROADCASTSSZ128rrkz:
2783 case VBROADCASTSSZ256rm:
2784 case VBROADCASTSSZ256rmk:
2785 case VBROADCASTSSZ256rmkz:
2786 case VBROADCASTSSZ256rr:
2787 case VBROADCASTSSZ256rrk:
2788 case VBROADCASTSSZ256rrkz:
2789 case VBROADCASTSSZrm:
2790 case VBROADCASTSSZrmk:
2791 case VBROADCASTSSZrmkz:
2792 case VBROADCASTSSZrr:
2793 case VBROADCASTSSZrrk:
2794 case VBROADCASTSSZrrkz:
2795 case VBROADCASTSSrm:
2796 case VBROADCASTSSrr:
2797 return true;
2798 }
2799 return false;
2800}
2801
2802bool isCLUI(unsigned Opcode) {
2803 return Opcode == CLUI;
2804}
2805
2806bool isVINSERTI128(unsigned Opcode) {
2807 switch (Opcode) {
2808 case VINSERTI128rmi:
2809 case VINSERTI128rri:
2810 return true;
2811 }
2812 return false;
2813}
2814
2815bool isVPSHLDW(unsigned Opcode) {
2816 switch (Opcode) {
2817 case VPSHLDWZ128rmi:
2818 case VPSHLDWZ128rmik:
2819 case VPSHLDWZ128rmikz:
2820 case VPSHLDWZ128rri:
2821 case VPSHLDWZ128rrik:
2822 case VPSHLDWZ128rrikz:
2823 case VPSHLDWZ256rmi:
2824 case VPSHLDWZ256rmik:
2825 case VPSHLDWZ256rmikz:
2826 case VPSHLDWZ256rri:
2827 case VPSHLDWZ256rrik:
2828 case VPSHLDWZ256rrikz:
2829 case VPSHLDWZrmi:
2830 case VPSHLDWZrmik:
2831 case VPSHLDWZrmikz:
2832 case VPSHLDWZrri:
2833 case VPSHLDWZrrik:
2834 case VPSHLDWZrrikz:
2835 return true;
2836 }
2837 return false;
2838}
2839
2840bool isVBLENDPD(unsigned Opcode) {
2841 switch (Opcode) {
2842 case VBLENDPDYrmi:
2843 case VBLENDPDYrri:
2844 case VBLENDPDrmi:
2845 case VBLENDPDrri:
2846 return true;
2847 }
2848 return false;
2849}
2850
2851bool isVSM4KEY4(unsigned Opcode) {
2852 switch (Opcode) {
2853 case VSM4KEY4Yrm:
2854 case VSM4KEY4Yrr:
2855 case VSM4KEY4Z128rm:
2856 case VSM4KEY4Z128rr:
2857 case VSM4KEY4Z256rm:
2858 case VSM4KEY4Z256rr:
2859 case VSM4KEY4Zrm:
2860 case VSM4KEY4Zrr:
2861 case VSM4KEY4rm:
2862 case VSM4KEY4rr:
2863 return true;
2864 }
2865 return false;
2866}
2867
2868bool isVCVTNEEPH2PS(unsigned Opcode) {
2869 switch (Opcode) {
2870 case VCVTNEEPH2PSYrm:
2871 case VCVTNEEPH2PSrm:
2872 return true;
2873 }
2874 return false;
2875}
2876
2877bool isVCVTTSD2SI(unsigned Opcode) {
2878 switch (Opcode) {
2879 case VCVTTSD2SI64Zrm_Int:
2880 case VCVTTSD2SI64Zrr_Int:
2881 case VCVTTSD2SI64Zrrb_Int:
2882 case VCVTTSD2SI64rm_Int:
2883 case VCVTTSD2SI64rr_Int:
2884 case VCVTTSD2SIZrm_Int:
2885 case VCVTTSD2SIZrr_Int:
2886 case VCVTTSD2SIZrrb_Int:
2887 case VCVTTSD2SIrm_Int:
2888 case VCVTTSD2SIrr_Int:
2889 return true;
2890 }
2891 return false;
2892}
2893
2894bool isWRMSRNS(unsigned Opcode) {
2895 switch (Opcode) {
2896 case WRMSRNS:
2897 case WRMSRNSir:
2898 case WRMSRNSir_EVEX:
2899 return true;
2900 }
2901 return false;
2902}
2903
2904bool isCMPSB(unsigned Opcode) {
2905 return Opcode == CMPSB;
2906}
2907
2908bool isVRCPBF16(unsigned Opcode) {
2909 switch (Opcode) {
2910 case VRCPBF16Z128m:
2911 case VRCPBF16Z128mb:
2912 case VRCPBF16Z128mbk:
2913 case VRCPBF16Z128mbkz:
2914 case VRCPBF16Z128mk:
2915 case VRCPBF16Z128mkz:
2916 case VRCPBF16Z128r:
2917 case VRCPBF16Z128rk:
2918 case VRCPBF16Z128rkz:
2919 case VRCPBF16Z256m:
2920 case VRCPBF16Z256mb:
2921 case VRCPBF16Z256mbk:
2922 case VRCPBF16Z256mbkz:
2923 case VRCPBF16Z256mk:
2924 case VRCPBF16Z256mkz:
2925 case VRCPBF16Z256r:
2926 case VRCPBF16Z256rk:
2927 case VRCPBF16Z256rkz:
2928 case VRCPBF16Zm:
2929 case VRCPBF16Zmb:
2930 case VRCPBF16Zmbk:
2931 case VRCPBF16Zmbkz:
2932 case VRCPBF16Zmk:
2933 case VRCPBF16Zmkz:
2934 case VRCPBF16Zr:
2935 case VRCPBF16Zrk:
2936 case VRCPBF16Zrkz:
2937 return true;
2938 }
2939 return false;
2940}
2941
2942bool isMULSS(unsigned Opcode) {
2943 switch (Opcode) {
2944 case MULSSrm_Int:
2945 case MULSSrr_Int:
2946 return true;
2947 }
2948 return false;
2949}
2950
2951bool isVMRUN(unsigned Opcode) {
2952 switch (Opcode) {
2953 case VMRUN32:
2954 case VMRUN64:
2955 return true;
2956 }
2957 return false;
2958}
2959
2960bool isVPSRLVD(unsigned Opcode) {
2961 switch (Opcode) {
2962 case VPSRLVDYrm:
2963 case VPSRLVDYrr:
2964 case VPSRLVDZ128rm:
2965 case VPSRLVDZ128rmb:
2966 case VPSRLVDZ128rmbk:
2967 case VPSRLVDZ128rmbkz:
2968 case VPSRLVDZ128rmk:
2969 case VPSRLVDZ128rmkz:
2970 case VPSRLVDZ128rr:
2971 case VPSRLVDZ128rrk:
2972 case VPSRLVDZ128rrkz:
2973 case VPSRLVDZ256rm:
2974 case VPSRLVDZ256rmb:
2975 case VPSRLVDZ256rmbk:
2976 case VPSRLVDZ256rmbkz:
2977 case VPSRLVDZ256rmk:
2978 case VPSRLVDZ256rmkz:
2979 case VPSRLVDZ256rr:
2980 case VPSRLVDZ256rrk:
2981 case VPSRLVDZ256rrkz:
2982 case VPSRLVDZrm:
2983 case VPSRLVDZrmb:
2984 case VPSRLVDZrmbk:
2985 case VPSRLVDZrmbkz:
2986 case VPSRLVDZrmk:
2987 case VPSRLVDZrmkz:
2988 case VPSRLVDZrr:
2989 case VPSRLVDZrrk:
2990 case VPSRLVDZrrkz:
2991 case VPSRLVDrm:
2992 case VPSRLVDrr:
2993 return true;
2994 }
2995 return false;
2996}
2997
2998bool isLEAVE(unsigned Opcode) {
2999 switch (Opcode) {
3000 case LEAVE:
3001 case LEAVE64:
3002 return true;
3003 }
3004 return false;
3005}
3006
3007bool isVGETMANTPS(unsigned Opcode) {
3008 switch (Opcode) {
3009 case VGETMANTPSZ128rmbi:
3010 case VGETMANTPSZ128rmbik:
3011 case VGETMANTPSZ128rmbikz:
3012 case VGETMANTPSZ128rmi:
3013 case VGETMANTPSZ128rmik:
3014 case VGETMANTPSZ128rmikz:
3015 case VGETMANTPSZ128rri:
3016 case VGETMANTPSZ128rrik:
3017 case VGETMANTPSZ128rrikz:
3018 case VGETMANTPSZ256rmbi:
3019 case VGETMANTPSZ256rmbik:
3020 case VGETMANTPSZ256rmbikz:
3021 case VGETMANTPSZ256rmi:
3022 case VGETMANTPSZ256rmik:
3023 case VGETMANTPSZ256rmikz:
3024 case VGETMANTPSZ256rri:
3025 case VGETMANTPSZ256rrik:
3026 case VGETMANTPSZ256rrikz:
3027 case VGETMANTPSZrmbi:
3028 case VGETMANTPSZrmbik:
3029 case VGETMANTPSZrmbikz:
3030 case VGETMANTPSZrmi:
3031 case VGETMANTPSZrmik:
3032 case VGETMANTPSZrmikz:
3033 case VGETMANTPSZrri:
3034 case VGETMANTPSZrrib:
3035 case VGETMANTPSZrribk:
3036 case VGETMANTPSZrribkz:
3037 case VGETMANTPSZrrik:
3038 case VGETMANTPSZrrikz:
3039 return true;
3040 }
3041 return false;
3042}
3043
3044bool isXSHA256(unsigned Opcode) {
3045 return Opcode == XSHA256;
3046}
3047
3048bool isBOUND(unsigned Opcode) {
3049 switch (Opcode) {
3050 case BOUNDS16rm:
3051 case BOUNDS32rm:
3052 return true;
3053 }
3054 return false;
3055}
3056
3057bool isSFENCE(unsigned Opcode) {
3058 return Opcode == SFENCE;
3059}
3060
3061bool isVPHADDD(unsigned Opcode) {
3062 switch (Opcode) {
3063 case VPHADDDYrm:
3064 case VPHADDDYrr:
3065 case VPHADDDrm:
3066 case VPHADDDrr:
3067 return true;
3068 }
3069 return false;
3070}
3071
3072bool isADOX(unsigned Opcode) {
3073 switch (Opcode) {
3074 case ADOX32rm:
3075 case ADOX32rm_EVEX:
3076 case ADOX32rm_ND:
3077 case ADOX32rr:
3078 case ADOX32rr_EVEX:
3079 case ADOX32rr_ND:
3080 case ADOX64rm:
3081 case ADOX64rm_EVEX:
3082 case ADOX64rm_ND:
3083 case ADOX64rr:
3084 case ADOX64rr_EVEX:
3085 case ADOX64rr_ND:
3086 return true;
3087 }
3088 return false;
3089}
3090
3091bool isVPSLLQ(unsigned Opcode) {
3092 switch (Opcode) {
3093 case VPSLLQYri:
3094 case VPSLLQYrm:
3095 case VPSLLQYrr:
3096 case VPSLLQZ128mbi:
3097 case VPSLLQZ128mbik:
3098 case VPSLLQZ128mbikz:
3099 case VPSLLQZ128mi:
3100 case VPSLLQZ128mik:
3101 case VPSLLQZ128mikz:
3102 case VPSLLQZ128ri:
3103 case VPSLLQZ128rik:
3104 case VPSLLQZ128rikz:
3105 case VPSLLQZ128rm:
3106 case VPSLLQZ128rmk:
3107 case VPSLLQZ128rmkz:
3108 case VPSLLQZ128rr:
3109 case VPSLLQZ128rrk:
3110 case VPSLLQZ128rrkz:
3111 case VPSLLQZ256mbi:
3112 case VPSLLQZ256mbik:
3113 case VPSLLQZ256mbikz:
3114 case VPSLLQZ256mi:
3115 case VPSLLQZ256mik:
3116 case VPSLLQZ256mikz:
3117 case VPSLLQZ256ri:
3118 case VPSLLQZ256rik:
3119 case VPSLLQZ256rikz:
3120 case VPSLLQZ256rm:
3121 case VPSLLQZ256rmk:
3122 case VPSLLQZ256rmkz:
3123 case VPSLLQZ256rr:
3124 case VPSLLQZ256rrk:
3125 case VPSLLQZ256rrkz:
3126 case VPSLLQZmbi:
3127 case VPSLLQZmbik:
3128 case VPSLLQZmbikz:
3129 case VPSLLQZmi:
3130 case VPSLLQZmik:
3131 case VPSLLQZmikz:
3132 case VPSLLQZri:
3133 case VPSLLQZrik:
3134 case VPSLLQZrikz:
3135 case VPSLLQZrm:
3136 case VPSLLQZrmk:
3137 case VPSLLQZrmkz:
3138 case VPSLLQZrr:
3139 case VPSLLQZrrk:
3140 case VPSLLQZrrkz:
3141 case VPSLLQri:
3142 case VPSLLQrm:
3143 case VPSLLQrr:
3144 return true;
3145 }
3146 return false;
3147}
3148
3149bool isVCVTPH2HF8(unsigned Opcode) {
3150 switch (Opcode) {
3151 case VCVTPH2HF8Z128rm:
3152 case VCVTPH2HF8Z128rmb:
3153 case VCVTPH2HF8Z128rmbk:
3154 case VCVTPH2HF8Z128rmbkz:
3155 case VCVTPH2HF8Z128rmk:
3156 case VCVTPH2HF8Z128rmkz:
3157 case VCVTPH2HF8Z128rr:
3158 case VCVTPH2HF8Z128rrk:
3159 case VCVTPH2HF8Z128rrkz:
3160 case VCVTPH2HF8Z256rm:
3161 case VCVTPH2HF8Z256rmb:
3162 case VCVTPH2HF8Z256rmbk:
3163 case VCVTPH2HF8Z256rmbkz:
3164 case VCVTPH2HF8Z256rmk:
3165 case VCVTPH2HF8Z256rmkz:
3166 case VCVTPH2HF8Z256rr:
3167 case VCVTPH2HF8Z256rrk:
3168 case VCVTPH2HF8Z256rrkz:
3169 case VCVTPH2HF8Zrm:
3170 case VCVTPH2HF8Zrmb:
3171 case VCVTPH2HF8Zrmbk:
3172 case VCVTPH2HF8Zrmbkz:
3173 case VCVTPH2HF8Zrmk:
3174 case VCVTPH2HF8Zrmkz:
3175 case VCVTPH2HF8Zrr:
3176 case VCVTPH2HF8Zrrk:
3177 case VCVTPH2HF8Zrrkz:
3178 return true;
3179 }
3180 return false;
3181}
3182
3183bool isPFRSQIT1(unsigned Opcode) {
3184 switch (Opcode) {
3185 case PFRSQIT1rm:
3186 case PFRSQIT1rr:
3187 return true;
3188 }
3189 return false;
3190}
3191
3192bool isCLAC(unsigned Opcode) {
3193 return Opcode == CLAC;
3194}
3195
3196bool isKNOTW(unsigned Opcode) {
3197 return Opcode == KNOTWkk;
3198}
3199
3200bool isVCVTPH2PD(unsigned Opcode) {
3201 switch (Opcode) {
3202 case VCVTPH2PDZ128rm:
3203 case VCVTPH2PDZ128rmb:
3204 case VCVTPH2PDZ128rmbk:
3205 case VCVTPH2PDZ128rmbkz:
3206 case VCVTPH2PDZ128rmk:
3207 case VCVTPH2PDZ128rmkz:
3208 case VCVTPH2PDZ128rr:
3209 case VCVTPH2PDZ128rrk:
3210 case VCVTPH2PDZ128rrkz:
3211 case VCVTPH2PDZ256rm:
3212 case VCVTPH2PDZ256rmb:
3213 case VCVTPH2PDZ256rmbk:
3214 case VCVTPH2PDZ256rmbkz:
3215 case VCVTPH2PDZ256rmk:
3216 case VCVTPH2PDZ256rmkz:
3217 case VCVTPH2PDZ256rr:
3218 case VCVTPH2PDZ256rrk:
3219 case VCVTPH2PDZ256rrkz:
3220 case VCVTPH2PDZrm:
3221 case VCVTPH2PDZrmb:
3222 case VCVTPH2PDZrmbk:
3223 case VCVTPH2PDZrmbkz:
3224 case VCVTPH2PDZrmk:
3225 case VCVTPH2PDZrmkz:
3226 case VCVTPH2PDZrr:
3227 case VCVTPH2PDZrrb:
3228 case VCVTPH2PDZrrbk:
3229 case VCVTPH2PDZrrbkz:
3230 case VCVTPH2PDZrrk:
3231 case VCVTPH2PDZrrkz:
3232 return true;
3233 }
3234 return false;
3235}
3236
3237bool isVAESENC(unsigned Opcode) {
3238 switch (Opcode) {
3239 case VAESENCYrm:
3240 case VAESENCYrr:
3241 case VAESENCZ128rm:
3242 case VAESENCZ128rr:
3243 case VAESENCZ256rm:
3244 case VAESENCZ256rr:
3245 case VAESENCZrm:
3246 case VAESENCZrr:
3247 case VAESENCrm:
3248 case VAESENCrr:
3249 return true;
3250 }
3251 return false;
3252}
3253
3254bool isMOVNTI(unsigned Opcode) {
3255 switch (Opcode) {
3256 case MOVNTI_64mr:
3257 case MOVNTImr:
3258 return true;
3259 }
3260 return false;
3261}
3262
3263bool isFXCH(unsigned Opcode) {
3264 return Opcode == XCH_F;
3265}
3266
3267bool isPOPP(unsigned Opcode) {
3268 return Opcode == POPP64r;
3269}
3270
3271bool isVPBLENDMD(unsigned Opcode) {
3272 switch (Opcode) {
3273 case VPBLENDMDZ128rm:
3274 case VPBLENDMDZ128rmb:
3275 case VPBLENDMDZ128rmbk:
3276 case VPBLENDMDZ128rmbkz:
3277 case VPBLENDMDZ128rmk:
3278 case VPBLENDMDZ128rmkz:
3279 case VPBLENDMDZ128rr:
3280 case VPBLENDMDZ128rrk:
3281 case VPBLENDMDZ128rrkz:
3282 case VPBLENDMDZ256rm:
3283 case VPBLENDMDZ256rmb:
3284 case VPBLENDMDZ256rmbk:
3285 case VPBLENDMDZ256rmbkz:
3286 case VPBLENDMDZ256rmk:
3287 case VPBLENDMDZ256rmkz:
3288 case VPBLENDMDZ256rr:
3289 case VPBLENDMDZ256rrk:
3290 case VPBLENDMDZ256rrkz:
3291 case VPBLENDMDZrm:
3292 case VPBLENDMDZrmb:
3293 case VPBLENDMDZrmbk:
3294 case VPBLENDMDZrmbkz:
3295 case VPBLENDMDZrmk:
3296 case VPBLENDMDZrmkz:
3297 case VPBLENDMDZrr:
3298 case VPBLENDMDZrrk:
3299 case VPBLENDMDZrrkz:
3300 return true;
3301 }
3302 return false;
3303}
3304
3305bool isFSINCOS(unsigned Opcode) {
3306 return Opcode == FSINCOS;
3307}
3308
3309bool isVPMOVSXBW(unsigned Opcode) {
3310 switch (Opcode) {
3311 case VPMOVSXBWYrm:
3312 case VPMOVSXBWYrr:
3313 case VPMOVSXBWZ128rm:
3314 case VPMOVSXBWZ128rmk:
3315 case VPMOVSXBWZ128rmkz:
3316 case VPMOVSXBWZ128rr:
3317 case VPMOVSXBWZ128rrk:
3318 case VPMOVSXBWZ128rrkz:
3319 case VPMOVSXBWZ256rm:
3320 case VPMOVSXBWZ256rmk:
3321 case VPMOVSXBWZ256rmkz:
3322 case VPMOVSXBWZ256rr:
3323 case VPMOVSXBWZ256rrk:
3324 case VPMOVSXBWZ256rrkz:
3325 case VPMOVSXBWZrm:
3326 case VPMOVSXBWZrmk:
3327 case VPMOVSXBWZrmkz:
3328 case VPMOVSXBWZrr:
3329 case VPMOVSXBWZrrk:
3330 case VPMOVSXBWZrrkz:
3331 case VPMOVSXBWrm:
3332 case VPMOVSXBWrr:
3333 return true;
3334 }
3335 return false;
3336}
3337
3338bool isVPMULLW(unsigned Opcode) {
3339 switch (Opcode) {
3340 case VPMULLWYrm:
3341 case VPMULLWYrr:
3342 case VPMULLWZ128rm:
3343 case VPMULLWZ128rmk:
3344 case VPMULLWZ128rmkz:
3345 case VPMULLWZ128rr:
3346 case VPMULLWZ128rrk:
3347 case VPMULLWZ128rrkz:
3348 case VPMULLWZ256rm:
3349 case VPMULLWZ256rmk:
3350 case VPMULLWZ256rmkz:
3351 case VPMULLWZ256rr:
3352 case VPMULLWZ256rrk:
3353 case VPMULLWZ256rrkz:
3354 case VPMULLWZrm:
3355 case VPMULLWZrmk:
3356 case VPMULLWZrmkz:
3357 case VPMULLWZrr:
3358 case VPMULLWZrrk:
3359 case VPMULLWZrrkz:
3360 case VPMULLWrm:
3361 case VPMULLWrr:
3362 return true;
3363 }
3364 return false;
3365}
3366
3367bool isSTC(unsigned Opcode) {
3368 return Opcode == STC;
3369}
3370
3371bool isVPINSRB(unsigned Opcode) {
3372 switch (Opcode) {
3373 case VPINSRBZrmi:
3374 case VPINSRBZrri:
3375 case VPINSRBrmi:
3376 case VPINSRBrri:
3377 return true;
3378 }
3379 return false;
3380}
3381
3382bool isLWPVAL(unsigned Opcode) {
3383 switch (Opcode) {
3384 case LWPVAL32rmi:
3385 case LWPVAL32rri:
3386 case LWPVAL64rmi:
3387 case LWPVAL64rri:
3388 return true;
3389 }
3390 return false;
3391}
3392
3393bool isKXORB(unsigned Opcode) {
3394 return Opcode == KXORBkk;
3395}
3396
3397bool isRSTORSSP(unsigned Opcode) {
3398 return Opcode == RSTORSSP;
3399}
3400
3401bool isVPRORQ(unsigned Opcode) {
3402 switch (Opcode) {
3403 case VPRORQZ128mbi:
3404 case VPRORQZ128mbik:
3405 case VPRORQZ128mbikz:
3406 case VPRORQZ128mi:
3407 case VPRORQZ128mik:
3408 case VPRORQZ128mikz:
3409 case VPRORQZ128ri:
3410 case VPRORQZ128rik:
3411 case VPRORQZ128rikz:
3412 case VPRORQZ256mbi:
3413 case VPRORQZ256mbik:
3414 case VPRORQZ256mbikz:
3415 case VPRORQZ256mi:
3416 case VPRORQZ256mik:
3417 case VPRORQZ256mikz:
3418 case VPRORQZ256ri:
3419 case VPRORQZ256rik:
3420 case VPRORQZ256rikz:
3421 case VPRORQZmbi:
3422 case VPRORQZmbik:
3423 case VPRORQZmbikz:
3424 case VPRORQZmi:
3425 case VPRORQZmik:
3426 case VPRORQZmikz:
3427 case VPRORQZri:
3428 case VPRORQZrik:
3429 case VPRORQZrikz:
3430 return true;
3431 }
3432 return false;
3433}
3434
3435bool isVSM3MSG1(unsigned Opcode) {
3436 switch (Opcode) {
3437 case VSM3MSG1rm:
3438 case VSM3MSG1rr:
3439 return true;
3440 }
3441 return false;
3442}
3443
3444bool isFICOM(unsigned Opcode) {
3445 switch (Opcode) {
3446 case FICOM16m:
3447 case FICOM32m:
3448 return true;
3449 }
3450 return false;
3451}
3452
3453bool isMAXPS(unsigned Opcode) {
3454 switch (Opcode) {
3455 case MAXPSrm:
3456 case MAXPSrr:
3457 return true;
3458 }
3459 return false;
3460}
3461
3462bool isFNCLEX(unsigned Opcode) {
3463 return Opcode == FNCLEX;
3464}
3465
3466bool isVMOVMSKPS(unsigned Opcode) {
3467 switch (Opcode) {
3468 case VMOVMSKPSYrr:
3469 case VMOVMSKPSrr:
3470 return true;
3471 }
3472 return false;
3473}
3474
3475bool isVPMOVDB(unsigned Opcode) {
3476 switch (Opcode) {
3477 case VPMOVDBZ128mr:
3478 case VPMOVDBZ128mrk:
3479 case VPMOVDBZ128rr:
3480 case VPMOVDBZ128rrk:
3481 case VPMOVDBZ128rrkz:
3482 case VPMOVDBZ256mr:
3483 case VPMOVDBZ256mrk:
3484 case VPMOVDBZ256rr:
3485 case VPMOVDBZ256rrk:
3486 case VPMOVDBZ256rrkz:
3487 case VPMOVDBZmr:
3488 case VPMOVDBZmrk:
3489 case VPMOVDBZrr:
3490 case VPMOVDBZrrk:
3491 case VPMOVDBZrrkz:
3492 return true;
3493 }
3494 return false;
3495}
3496
3497bool isLLWPCB(unsigned Opcode) {
3498 switch (Opcode) {
3499 case LLWPCB:
3500 case LLWPCB64:
3501 return true;
3502 }
3503 return false;
3504}
3505
3506bool isVMULSS(unsigned Opcode) {
3507 switch (Opcode) {
3508 case VMULSSZrm_Int:
3509 case VMULSSZrmk_Int:
3510 case VMULSSZrmkz_Int:
3511 case VMULSSZrr_Int:
3512 case VMULSSZrrb_Int:
3513 case VMULSSZrrbk_Int:
3514 case VMULSSZrrbkz_Int:
3515 case VMULSSZrrk_Int:
3516 case VMULSSZrrkz_Int:
3517 case VMULSSrm_Int:
3518 case VMULSSrr_Int:
3519 return true;
3520 }
3521 return false;
3522}
3523
3524bool isAESENCLAST(unsigned Opcode) {
3525 switch (Opcode) {
3526 case AESENCLASTrm:
3527 case AESENCLASTrr:
3528 return true;
3529 }
3530 return false;
3531}
3532
3533bool isTILEMOVROW(unsigned Opcode) {
3534 switch (Opcode) {
3535 case TILEMOVROWrte:
3536 case TILEMOVROWrti:
3537 return true;
3538 }
3539 return false;
3540}
3541
3542bool isVMINMAXPH(unsigned Opcode) {
3543 switch (Opcode) {
3544 case VMINMAXPHZ128rmbi:
3545 case VMINMAXPHZ128rmbik:
3546 case VMINMAXPHZ128rmbikz:
3547 case VMINMAXPHZ128rmi:
3548 case VMINMAXPHZ128rmik:
3549 case VMINMAXPHZ128rmikz:
3550 case VMINMAXPHZ128rri:
3551 case VMINMAXPHZ128rrik:
3552 case VMINMAXPHZ128rrikz:
3553 case VMINMAXPHZ256rmbi:
3554 case VMINMAXPHZ256rmbik:
3555 case VMINMAXPHZ256rmbikz:
3556 case VMINMAXPHZ256rmi:
3557 case VMINMAXPHZ256rmik:
3558 case VMINMAXPHZ256rmikz:
3559 case VMINMAXPHZ256rri:
3560 case VMINMAXPHZ256rrik:
3561 case VMINMAXPHZ256rrikz:
3562 case VMINMAXPHZrmbi:
3563 case VMINMAXPHZrmbik:
3564 case VMINMAXPHZrmbikz:
3565 case VMINMAXPHZrmi:
3566 case VMINMAXPHZrmik:
3567 case VMINMAXPHZrmikz:
3568 case VMINMAXPHZrri:
3569 case VMINMAXPHZrrib:
3570 case VMINMAXPHZrribk:
3571 case VMINMAXPHZrribkz:
3572 case VMINMAXPHZrrik:
3573 case VMINMAXPHZrrikz:
3574 return true;
3575 }
3576 return false;
3577}
3578
3579bool isVPMAXUB(unsigned Opcode) {
3580 switch (Opcode) {
3581 case VPMAXUBYrm:
3582 case VPMAXUBYrr:
3583 case VPMAXUBZ128rm:
3584 case VPMAXUBZ128rmk:
3585 case VPMAXUBZ128rmkz:
3586 case VPMAXUBZ128rr:
3587 case VPMAXUBZ128rrk:
3588 case VPMAXUBZ128rrkz:
3589 case VPMAXUBZ256rm:
3590 case VPMAXUBZ256rmk:
3591 case VPMAXUBZ256rmkz:
3592 case VPMAXUBZ256rr:
3593 case VPMAXUBZ256rrk:
3594 case VPMAXUBZ256rrkz:
3595 case VPMAXUBZrm:
3596 case VPMAXUBZrmk:
3597 case VPMAXUBZrmkz:
3598 case VPMAXUBZrr:
3599 case VPMAXUBZrrk:
3600 case VPMAXUBZrrkz:
3601 case VPMAXUBrm:
3602 case VPMAXUBrr:
3603 return true;
3604 }
3605 return false;
3606}
3607
3608bool isAAS(unsigned Opcode) {
3609 return Opcode == AAS;
3610}
3611
3612bool isFADD(unsigned Opcode) {
3613 switch (Opcode) {
3614 case ADD_F32m:
3615 case ADD_F64m:
3616 case ADD_FST0r:
3617 case ADD_FrST0:
3618 return true;
3619 }
3620 return false;
3621}
3622
3623bool isJMP(unsigned Opcode) {
3624 switch (Opcode) {
3625 case FARJMP32m:
3626 case JMP16m:
3627 case JMP16r:
3628 case JMP32m:
3629 case JMP32r:
3630 case JMP64m:
3631 case JMP64r:
3632 case JMP_1:
3633 case JMP_2:
3634 case JMP_4:
3635 return true;
3636 }
3637 return false;
3638}
3639
3640bool isXCRYPTECB(unsigned Opcode) {
3641 return Opcode == XCRYPTECB;
3642}
3643
3644bool isPFRCPIT1(unsigned Opcode) {
3645 switch (Opcode) {
3646 case PFRCPIT1rm:
3647 case PFRCPIT1rr:
3648 return true;
3649 }
3650 return false;
3651}
3652
3653bool isPMULHRW(unsigned Opcode) {
3654 switch (Opcode) {
3655 case PMULHRWrm:
3656 case PMULHRWrr:
3657 return true;
3658 }
3659 return false;
3660}
3661
3662bool isVCVTPH2PS(unsigned Opcode) {
3663 switch (Opcode) {
3664 case VCVTPH2PSYrm:
3665 case VCVTPH2PSYrr:
3666 case VCVTPH2PSZ128rm:
3667 case VCVTPH2PSZ128rmk:
3668 case VCVTPH2PSZ128rmkz:
3669 case VCVTPH2PSZ128rr:
3670 case VCVTPH2PSZ128rrk:
3671 case VCVTPH2PSZ128rrkz:
3672 case VCVTPH2PSZ256rm:
3673 case VCVTPH2PSZ256rmk:
3674 case VCVTPH2PSZ256rmkz:
3675 case VCVTPH2PSZ256rr:
3676 case VCVTPH2PSZ256rrk:
3677 case VCVTPH2PSZ256rrkz:
3678 case VCVTPH2PSZrm:
3679 case VCVTPH2PSZrmk:
3680 case VCVTPH2PSZrmkz:
3681 case VCVTPH2PSZrr:
3682 case VCVTPH2PSZrrb:
3683 case VCVTPH2PSZrrbk:
3684 case VCVTPH2PSZrrbkz:
3685 case VCVTPH2PSZrrk:
3686 case VCVTPH2PSZrrkz:
3687 case VCVTPH2PSrm:
3688 case VCVTPH2PSrr:
3689 return true;
3690 }
3691 return false;
3692}
3693
3694bool isVPBLENDVB(unsigned Opcode) {
3695 switch (Opcode) {
3696 case VPBLENDVBYrmr:
3697 case VPBLENDVBYrrr:
3698 case VPBLENDVBrmr:
3699 case VPBLENDVBrrr:
3700 return true;
3701 }
3702 return false;
3703}
3704
3705bool isPCMPESTRI(unsigned Opcode) {
3706 switch (Opcode) {
3707 case PCMPESTRIrmi:
3708 case PCMPESTRIrri:
3709 return true;
3710 }
3711 return false;
3712}
3713
3714bool isSENDUIPI(unsigned Opcode) {
3715 return Opcode == SENDUIPI;
3716}
3717
3718bool isFLDLN2(unsigned Opcode) {
3719 return Opcode == FLDLN2;
3720}
3721
3722bool isVPMACSWD(unsigned Opcode) {
3723 switch (Opcode) {
3724 case VPMACSWDrm:
3725 case VPMACSWDrr:
3726 return true;
3727 }
3728 return false;
3729}
3730
3731bool isSHA1MSG1(unsigned Opcode) {
3732 switch (Opcode) {
3733 case SHA1MSG1rm:
3734 case SHA1MSG1rr:
3735 return true;
3736 }
3737 return false;
3738}
3739
3740bool isVADDPS(unsigned Opcode) {
3741 switch (Opcode) {
3742 case VADDPSYrm:
3743 case VADDPSYrr:
3744 case VADDPSZ128rm:
3745 case VADDPSZ128rmb:
3746 case VADDPSZ128rmbk:
3747 case VADDPSZ128rmbkz:
3748 case VADDPSZ128rmk:
3749 case VADDPSZ128rmkz:
3750 case VADDPSZ128rr:
3751 case VADDPSZ128rrk:
3752 case VADDPSZ128rrkz:
3753 case VADDPSZ256rm:
3754 case VADDPSZ256rmb:
3755 case VADDPSZ256rmbk:
3756 case VADDPSZ256rmbkz:
3757 case VADDPSZ256rmk:
3758 case VADDPSZ256rmkz:
3759 case VADDPSZ256rr:
3760 case VADDPSZ256rrk:
3761 case VADDPSZ256rrkz:
3762 case VADDPSZrm:
3763 case VADDPSZrmb:
3764 case VADDPSZrmbk:
3765 case VADDPSZrmbkz:
3766 case VADDPSZrmk:
3767 case VADDPSZrmkz:
3768 case VADDPSZrr:
3769 case VADDPSZrrb:
3770 case VADDPSZrrbk:
3771 case VADDPSZrrbkz:
3772 case VADDPSZrrk:
3773 case VADDPSZrrkz:
3774 case VADDPSrm:
3775 case VADDPSrr:
3776 return true;
3777 }
3778 return false;
3779}
3780
3781bool isVCVTPS2DQ(unsigned Opcode) {
3782 switch (Opcode) {
3783 case VCVTPS2DQYrm:
3784 case VCVTPS2DQYrr:
3785 case VCVTPS2DQZ128rm:
3786 case VCVTPS2DQZ128rmb:
3787 case VCVTPS2DQZ128rmbk:
3788 case VCVTPS2DQZ128rmbkz:
3789 case VCVTPS2DQZ128rmk:
3790 case VCVTPS2DQZ128rmkz:
3791 case VCVTPS2DQZ128rr:
3792 case VCVTPS2DQZ128rrk:
3793 case VCVTPS2DQZ128rrkz:
3794 case VCVTPS2DQZ256rm:
3795 case VCVTPS2DQZ256rmb:
3796 case VCVTPS2DQZ256rmbk:
3797 case VCVTPS2DQZ256rmbkz:
3798 case VCVTPS2DQZ256rmk:
3799 case VCVTPS2DQZ256rmkz:
3800 case VCVTPS2DQZ256rr:
3801 case VCVTPS2DQZ256rrk:
3802 case VCVTPS2DQZ256rrkz:
3803 case VCVTPS2DQZrm:
3804 case VCVTPS2DQZrmb:
3805 case VCVTPS2DQZrmbk:
3806 case VCVTPS2DQZrmbkz:
3807 case VCVTPS2DQZrmk:
3808 case VCVTPS2DQZrmkz:
3809 case VCVTPS2DQZrr:
3810 case VCVTPS2DQZrrb:
3811 case VCVTPS2DQZrrbk:
3812 case VCVTPS2DQZrrbkz:
3813 case VCVTPS2DQZrrk:
3814 case VCVTPS2DQZrrkz:
3815 case VCVTPS2DQrm:
3816 case VCVTPS2DQrr:
3817 return true;
3818 }
3819 return false;
3820}
3821
3822bool isPFPNACC(unsigned Opcode) {
3823 switch (Opcode) {
3824 case PFPNACCrm:
3825 case PFPNACCrr:
3826 return true;
3827 }
3828 return false;
3829}
3830
3831bool isFMUL(unsigned Opcode) {
3832 switch (Opcode) {
3833 case MUL_F32m:
3834 case MUL_F64m:
3835 case MUL_FST0r:
3836 case MUL_FrST0:
3837 return true;
3838 }
3839 return false;
3840}
3841
3842bool isFNSAVE(unsigned Opcode) {
3843 return Opcode == FSAVEm;
3844}
3845
3846bool isCDQE(unsigned Opcode) {
3847 return Opcode == CDQE;
3848}
3849
3850bool isVPMACSDD(unsigned Opcode) {
3851 switch (Opcode) {
3852 case VPMACSDDrm:
3853 case VPMACSDDrr:
3854 return true;
3855 }
3856 return false;
3857}
3858
3859bool isVSQRTPS(unsigned Opcode) {
3860 switch (Opcode) {
3861 case VSQRTPSYm:
3862 case VSQRTPSYr:
3863 case VSQRTPSZ128m:
3864 case VSQRTPSZ128mb:
3865 case VSQRTPSZ128mbk:
3866 case VSQRTPSZ128mbkz:
3867 case VSQRTPSZ128mk:
3868 case VSQRTPSZ128mkz:
3869 case VSQRTPSZ128r:
3870 case VSQRTPSZ128rk:
3871 case VSQRTPSZ128rkz:
3872 case VSQRTPSZ256m:
3873 case VSQRTPSZ256mb:
3874 case VSQRTPSZ256mbk:
3875 case VSQRTPSZ256mbkz:
3876 case VSQRTPSZ256mk:
3877 case VSQRTPSZ256mkz:
3878 case VSQRTPSZ256r:
3879 case VSQRTPSZ256rk:
3880 case VSQRTPSZ256rkz:
3881 case VSQRTPSZm:
3882 case VSQRTPSZmb:
3883 case VSQRTPSZmbk:
3884 case VSQRTPSZmbkz:
3885 case VSQRTPSZmk:
3886 case VSQRTPSZmkz:
3887 case VSQRTPSZr:
3888 case VSQRTPSZrb:
3889 case VSQRTPSZrbk:
3890 case VSQRTPSZrbkz:
3891 case VSQRTPSZrk:
3892 case VSQRTPSZrkz:
3893 case VSQRTPSm:
3894 case VSQRTPSr:
3895 return true;
3896 }
3897 return false;
3898}
3899
3900bool isCMPSQ(unsigned Opcode) {
3901 return Opcode == CMPSQ;
3902}
3903
3904bool isVPSCATTERDD(unsigned Opcode) {
3905 switch (Opcode) {
3906 case VPSCATTERDDZ128mr:
3907 case VPSCATTERDDZ256mr:
3908 case VPSCATTERDDZmr:
3909 return true;
3910 }
3911 return false;
3912}
3913
3914bool isVCVTTSD2USIS(unsigned Opcode) {
3915 switch (Opcode) {
3916 case VCVTTSD2USI64Srm_Int:
3917 case VCVTTSD2USI64Srr_Int:
3918 case VCVTTSD2USI64Srrb_Int:
3919 case VCVTTSD2USISrm_Int:
3920 case VCVTTSD2USISrr_Int:
3921 case VCVTTSD2USISrrb_Int:
3922 return true;
3923 }
3924 return false;
3925}
3926
3927bool isVRNDSCALESD(unsigned Opcode) {
3928 switch (Opcode) {
3929 case VRNDSCALESDZrmi_Int:
3930 case VRNDSCALESDZrmik_Int:
3931 case VRNDSCALESDZrmikz_Int:
3932 case VRNDSCALESDZrri_Int:
3933 case VRNDSCALESDZrrib_Int:
3934 case VRNDSCALESDZrribk_Int:
3935 case VRNDSCALESDZrribkz_Int:
3936 case VRNDSCALESDZrrik_Int:
3937 case VRNDSCALESDZrrikz_Int:
3938 return true;
3939 }
3940 return false;
3941}
3942
3943bool isSUBPS(unsigned Opcode) {
3944 switch (Opcode) {
3945 case SUBPSrm:
3946 case SUBPSrr:
3947 return true;
3948 }
3949 return false;
3950}
3951
3952bool isVMAXSH(unsigned Opcode) {
3953 switch (Opcode) {
3954 case VMAXSHZrm_Int:
3955 case VMAXSHZrmk_Int:
3956 case VMAXSHZrmkz_Int:
3957 case VMAXSHZrr_Int:
3958 case VMAXSHZrrb_Int:
3959 case VMAXSHZrrbk_Int:
3960 case VMAXSHZrrbkz_Int:
3961 case VMAXSHZrrk_Int:
3962 case VMAXSHZrrkz_Int:
3963 return true;
3964 }
3965 return false;
3966}
3967
3968bool isFLDZ(unsigned Opcode) {
3969 return Opcode == LD_F0;
3970}
3971
3972bool isVFNMADD132SS(unsigned Opcode) {
3973 switch (Opcode) {
3974 case VFNMADD132SSZm_Int:
3975 case VFNMADD132SSZmk_Int:
3976 case VFNMADD132SSZmkz_Int:
3977 case VFNMADD132SSZr_Int:
3978 case VFNMADD132SSZrb_Int:
3979 case VFNMADD132SSZrbk_Int:
3980 case VFNMADD132SSZrbkz_Int:
3981 case VFNMADD132SSZrk_Int:
3982 case VFNMADD132SSZrkz_Int:
3983 case VFNMADD132SSm_Int:
3984 case VFNMADD132SSr_Int:
3985 return true;
3986 }
3987 return false;
3988}
3989
3990bool isLGDTW(unsigned Opcode) {
3991 return Opcode == LGDT16m;
3992}
3993
3994bool isTCVTROWPS2PHH(unsigned Opcode) {
3995 switch (Opcode) {
3996 case TCVTROWPS2PHHrte:
3997 case TCVTROWPS2PHHrti:
3998 return true;
3999 }
4000 return false;
4001}
4002
4003bool isINC(unsigned Opcode) {
4004 switch (Opcode) {
4005 case INC16m:
4006 case INC16m_EVEX:
4007 case INC16m_ND:
4008 case INC16m_NF:
4009 case INC16m_NF_ND:
4010 case INC16r:
4011 case INC16r_EVEX:
4012 case INC16r_ND:
4013 case INC16r_NF:
4014 case INC16r_NF_ND:
4015 case INC16r_alt:
4016 case INC32m:
4017 case INC32m_EVEX:
4018 case INC32m_ND:
4019 case INC32m_NF:
4020 case INC32m_NF_ND:
4021 case INC32r:
4022 case INC32r_EVEX:
4023 case INC32r_ND:
4024 case INC32r_NF:
4025 case INC32r_NF_ND:
4026 case INC32r_alt:
4027 case INC64m:
4028 case INC64m_EVEX:
4029 case INC64m_ND:
4030 case INC64m_NF:
4031 case INC64m_NF_ND:
4032 case INC64r:
4033 case INC64r_EVEX:
4034 case INC64r_ND:
4035 case INC64r_NF:
4036 case INC64r_NF_ND:
4037 case INC8m:
4038 case INC8m_EVEX:
4039 case INC8m_ND:
4040 case INC8m_NF:
4041 case INC8m_NF_ND:
4042 case INC8r:
4043 case INC8r_EVEX:
4044 case INC8r_ND:
4045 case INC8r_NF:
4046 case INC8r_NF_ND:
4047 return true;
4048 }
4049 return false;
4050}
4051
4052bool isPABSB(unsigned Opcode) {
4053 switch (Opcode) {
4054 case MMX_PABSBrm:
4055 case MMX_PABSBrr:
4056 case PABSBrm:
4057 case PABSBrr:
4058 return true;
4059 }
4060 return false;
4061}
4062
4063bool isVPANDN(unsigned Opcode) {
4064 switch (Opcode) {
4065 case VPANDNYrm:
4066 case VPANDNYrr:
4067 case VPANDNrm:
4068 case VPANDNrr:
4069 return true;
4070 }
4071 return false;
4072}
4073
4074bool isVPMAXUD(unsigned Opcode) {
4075 switch (Opcode) {
4076 case VPMAXUDYrm:
4077 case VPMAXUDYrr:
4078 case VPMAXUDZ128rm:
4079 case VPMAXUDZ128rmb:
4080 case VPMAXUDZ128rmbk:
4081 case VPMAXUDZ128rmbkz:
4082 case VPMAXUDZ128rmk:
4083 case VPMAXUDZ128rmkz:
4084 case VPMAXUDZ128rr:
4085 case VPMAXUDZ128rrk:
4086 case VPMAXUDZ128rrkz:
4087 case VPMAXUDZ256rm:
4088 case VPMAXUDZ256rmb:
4089 case VPMAXUDZ256rmbk:
4090 case VPMAXUDZ256rmbkz:
4091 case VPMAXUDZ256rmk:
4092 case VPMAXUDZ256rmkz:
4093 case VPMAXUDZ256rr:
4094 case VPMAXUDZ256rrk:
4095 case VPMAXUDZ256rrkz:
4096 case VPMAXUDZrm:
4097 case VPMAXUDZrmb:
4098 case VPMAXUDZrmbk:
4099 case VPMAXUDZrmbkz:
4100 case VPMAXUDZrmk:
4101 case VPMAXUDZrmkz:
4102 case VPMAXUDZrr:
4103 case VPMAXUDZrrk:
4104 case VPMAXUDZrrkz:
4105 case VPMAXUDrm:
4106 case VPMAXUDrr:
4107 return true;
4108 }
4109 return false;
4110}
4111
4112bool isVSHA512RNDS2(unsigned Opcode) {
4113 return Opcode == VSHA512RNDS2rr;
4114}
4115
4116bool isPHADDSW(unsigned Opcode) {
4117 switch (Opcode) {
4118 case MMX_PHADDSWrm:
4119 case MMX_PHADDSWrr:
4120 case PHADDSWrm:
4121 case PHADDSWrr:
4122 return true;
4123 }
4124 return false;
4125}
4126
4127bool isVPMOVSQW(unsigned Opcode) {
4128 switch (Opcode) {
4129 case VPMOVSQWZ128mr:
4130 case VPMOVSQWZ128mrk:
4131 case VPMOVSQWZ128rr:
4132 case VPMOVSQWZ128rrk:
4133 case VPMOVSQWZ128rrkz:
4134 case VPMOVSQWZ256mr:
4135 case VPMOVSQWZ256mrk:
4136 case VPMOVSQWZ256rr:
4137 case VPMOVSQWZ256rrk:
4138 case VPMOVSQWZ256rrkz:
4139 case VPMOVSQWZmr:
4140 case VPMOVSQWZmrk:
4141 case VPMOVSQWZrr:
4142 case VPMOVSQWZrrk:
4143 case VPMOVSQWZrrkz:
4144 return true;
4145 }
4146 return false;
4147}
4148
4149bool isADDSUBPS(unsigned Opcode) {
4150 switch (Opcode) {
4151 case ADDSUBPSrm:
4152 case ADDSUBPSrr:
4153 return true;
4154 }
4155 return false;
4156}
4157
4158bool isVPMACSSDQL(unsigned Opcode) {
4159 switch (Opcode) {
4160 case VPMACSSDQLrm:
4161 case VPMACSSDQLrr:
4162 return true;
4163 }
4164 return false;
4165}
4166
4167bool isPXOR(unsigned Opcode) {
4168 switch (Opcode) {
4169 case MMX_PXORrm:
4170 case MMX_PXORrr:
4171 case PXORrm:
4172 case PXORrr:
4173 return true;
4174 }
4175 return false;
4176}
4177
4178bool isVPSRAD(unsigned Opcode) {
4179 switch (Opcode) {
4180 case VPSRADYri:
4181 case VPSRADYrm:
4182 case VPSRADYrr:
4183 case VPSRADZ128mbi:
4184 case VPSRADZ128mbik:
4185 case VPSRADZ128mbikz:
4186 case VPSRADZ128mi:
4187 case VPSRADZ128mik:
4188 case VPSRADZ128mikz:
4189 case VPSRADZ128ri:
4190 case VPSRADZ128rik:
4191 case VPSRADZ128rikz:
4192 case VPSRADZ128rm:
4193 case VPSRADZ128rmk:
4194 case VPSRADZ128rmkz:
4195 case VPSRADZ128rr:
4196 case VPSRADZ128rrk:
4197 case VPSRADZ128rrkz:
4198 case VPSRADZ256mbi:
4199 case VPSRADZ256mbik:
4200 case VPSRADZ256mbikz:
4201 case VPSRADZ256mi:
4202 case VPSRADZ256mik:
4203 case VPSRADZ256mikz:
4204 case VPSRADZ256ri:
4205 case VPSRADZ256rik:
4206 case VPSRADZ256rikz:
4207 case VPSRADZ256rm:
4208 case VPSRADZ256rmk:
4209 case VPSRADZ256rmkz:
4210 case VPSRADZ256rr:
4211 case VPSRADZ256rrk:
4212 case VPSRADZ256rrkz:
4213 case VPSRADZmbi:
4214 case VPSRADZmbik:
4215 case VPSRADZmbikz:
4216 case VPSRADZmi:
4217 case VPSRADZmik:
4218 case VPSRADZmikz:
4219 case VPSRADZri:
4220 case VPSRADZrik:
4221 case VPSRADZrikz:
4222 case VPSRADZrm:
4223 case VPSRADZrmk:
4224 case VPSRADZrmkz:
4225 case VPSRADZrr:
4226 case VPSRADZrrk:
4227 case VPSRADZrrkz:
4228 case VPSRADri:
4229 case VPSRADrm:
4230 case VPSRADrr:
4231 return true;
4232 }
4233 return false;
4234}
4235
4236bool isVPSHAB(unsigned Opcode) {
4237 switch (Opcode) {
4238 case VPSHABmr:
4239 case VPSHABrm:
4240 case VPSHABrr:
4241 case VPSHABrr_REV:
4242 return true;
4243 }
4244 return false;
4245}
4246
4247bool isBTR(unsigned Opcode) {
4248 switch (Opcode) {
4249 case BTR16mi8:
4250 case BTR16mr:
4251 case BTR16ri8:
4252 case BTR16rr:
4253 case BTR32mi8:
4254 case BTR32mr:
4255 case BTR32ri8:
4256 case BTR32rr:
4257 case BTR64mi8:
4258 case BTR64mr:
4259 case BTR64ri8:
4260 case BTR64rr:
4261 return true;
4262 }
4263 return false;
4264}
4265
4266bool isKORW(unsigned Opcode) {
4267 return Opcode == KORWkk;
4268}
4269
4270bool isVRANGESS(unsigned Opcode) {
4271 switch (Opcode) {
4272 case VRANGESSZrmi:
4273 case VRANGESSZrmik:
4274 case VRANGESSZrmikz:
4275 case VRANGESSZrri:
4276 case VRANGESSZrrib:
4277 case VRANGESSZrribk:
4278 case VRANGESSZrribkz:
4279 case VRANGESSZrrik:
4280 case VRANGESSZrrikz:
4281 return true;
4282 }
4283 return false;
4284}
4285
4286bool isVCMPPS(unsigned Opcode) {
4287 switch (Opcode) {
4288 case VCMPPSYrmi:
4289 case VCMPPSYrri:
4290 case VCMPPSZ128rmbi:
4291 case VCMPPSZ128rmbik:
4292 case VCMPPSZ128rmi:
4293 case VCMPPSZ128rmik:
4294 case VCMPPSZ128rri:
4295 case VCMPPSZ128rrik:
4296 case VCMPPSZ256rmbi:
4297 case VCMPPSZ256rmbik:
4298 case VCMPPSZ256rmi:
4299 case VCMPPSZ256rmik:
4300 case VCMPPSZ256rri:
4301 case VCMPPSZ256rrik:
4302 case VCMPPSZrmbi:
4303 case VCMPPSZrmbik:
4304 case VCMPPSZrmi:
4305 case VCMPPSZrmik:
4306 case VCMPPSZrri:
4307 case VCMPPSZrrib:
4308 case VCMPPSZrribk:
4309 case VCMPPSZrrik:
4310 case VCMPPSrmi:
4311 case VCMPPSrri:
4312 return true;
4313 }
4314 return false;
4315}
4316
4317bool isVPLZCNTD(unsigned Opcode) {
4318 switch (Opcode) {
4319 case VPLZCNTDZ128rm:
4320 case VPLZCNTDZ128rmb:
4321 case VPLZCNTDZ128rmbk:
4322 case VPLZCNTDZ128rmbkz:
4323 case VPLZCNTDZ128rmk:
4324 case VPLZCNTDZ128rmkz:
4325 case VPLZCNTDZ128rr:
4326 case VPLZCNTDZ128rrk:
4327 case VPLZCNTDZ128rrkz:
4328 case VPLZCNTDZ256rm:
4329 case VPLZCNTDZ256rmb:
4330 case VPLZCNTDZ256rmbk:
4331 case VPLZCNTDZ256rmbkz:
4332 case VPLZCNTDZ256rmk:
4333 case VPLZCNTDZ256rmkz:
4334 case VPLZCNTDZ256rr:
4335 case VPLZCNTDZ256rrk:
4336 case VPLZCNTDZ256rrkz:
4337 case VPLZCNTDZrm:
4338 case VPLZCNTDZrmb:
4339 case VPLZCNTDZrmbk:
4340 case VPLZCNTDZrmbkz:
4341 case VPLZCNTDZrmk:
4342 case VPLZCNTDZrmkz:
4343 case VPLZCNTDZrr:
4344 case VPLZCNTDZrrk:
4345 case VPLZCNTDZrrkz:
4346 return true;
4347 }
4348 return false;
4349}
4350
4351bool isTDPBUUD(unsigned Opcode) {
4352 return Opcode == TDPBUUD;
4353}
4354
4355bool isROUNDPS(unsigned Opcode) {
4356 switch (Opcode) {
4357 case ROUNDPSmi:
4358 case ROUNDPSri:
4359 return true;
4360 }
4361 return false;
4362}
4363
4364bool isFABS(unsigned Opcode) {
4365 return Opcode == ABS_F;
4366}
4367
4368bool isSUBPD(unsigned Opcode) {
4369 switch (Opcode) {
4370 case SUBPDrm:
4371 case SUBPDrr:
4372 return true;
4373 }
4374 return false;
4375}
4376
4377bool isGF2P8MULB(unsigned Opcode) {
4378 switch (Opcode) {
4379 case GF2P8MULBrm:
4380 case GF2P8MULBrr:
4381 return true;
4382 }
4383 return false;
4384}
4385
4386bool isTZMSK(unsigned Opcode) {
4387 switch (Opcode) {
4388 case TZMSK32rm:
4389 case TZMSK32rr:
4390 case TZMSK64rm:
4391 case TZMSK64rr:
4392 return true;
4393 }
4394 return false;
4395}
4396
4397bool isVMINMAXSD(unsigned Opcode) {
4398 switch (Opcode) {
4399 case VMINMAXSDrmi_Int:
4400 case VMINMAXSDrmik_Int:
4401 case VMINMAXSDrmikz_Int:
4402 case VMINMAXSDrri_Int:
4403 case VMINMAXSDrrib_Int:
4404 case VMINMAXSDrribk_Int:
4405 case VMINMAXSDrribkz_Int:
4406 case VMINMAXSDrrik_Int:
4407 case VMINMAXSDrrikz_Int:
4408 return true;
4409 }
4410 return false;
4411}
4412
4413bool isANDPS(unsigned Opcode) {
4414 switch (Opcode) {
4415 case ANDPSrm:
4416 case ANDPSrr:
4417 return true;
4418 }
4419 return false;
4420}
4421
4422bool isVEXTRACTF32X8(unsigned Opcode) {
4423 switch (Opcode) {
4424 case VEXTRACTF32X8Zmri:
4425 case VEXTRACTF32X8Zmrik:
4426 case VEXTRACTF32X8Zrri:
4427 case VEXTRACTF32X8Zrrik:
4428 case VEXTRACTF32X8Zrrikz:
4429 return true;
4430 }
4431 return false;
4432}
4433
4434bool isSEAMRET(unsigned Opcode) {
4435 return Opcode == SEAMRET;
4436}
4437
4438bool isVPCOMW(unsigned Opcode) {
4439 switch (Opcode) {
4440 case VPCOMWmi:
4441 case VPCOMWri:
4442 return true;
4443 }
4444 return false;
4445}
4446
4447bool isVFIXUPIMMPD(unsigned Opcode) {
4448 switch (Opcode) {
4449 case VFIXUPIMMPDZ128rmbi:
4450 case VFIXUPIMMPDZ128rmbik:
4451 case VFIXUPIMMPDZ128rmbikz:
4452 case VFIXUPIMMPDZ128rmi:
4453 case VFIXUPIMMPDZ128rmik:
4454 case VFIXUPIMMPDZ128rmikz:
4455 case VFIXUPIMMPDZ128rri:
4456 case VFIXUPIMMPDZ128rrik:
4457 case VFIXUPIMMPDZ128rrikz:
4458 case VFIXUPIMMPDZ256rmbi:
4459 case VFIXUPIMMPDZ256rmbik:
4460 case VFIXUPIMMPDZ256rmbikz:
4461 case VFIXUPIMMPDZ256rmi:
4462 case VFIXUPIMMPDZ256rmik:
4463 case VFIXUPIMMPDZ256rmikz:
4464 case VFIXUPIMMPDZ256rri:
4465 case VFIXUPIMMPDZ256rrik:
4466 case VFIXUPIMMPDZ256rrikz:
4467 case VFIXUPIMMPDZrmbi:
4468 case VFIXUPIMMPDZrmbik:
4469 case VFIXUPIMMPDZrmbikz:
4470 case VFIXUPIMMPDZrmi:
4471 case VFIXUPIMMPDZrmik:
4472 case VFIXUPIMMPDZrmikz:
4473 case VFIXUPIMMPDZrri:
4474 case VFIXUPIMMPDZrrib:
4475 case VFIXUPIMMPDZrribk:
4476 case VFIXUPIMMPDZrribkz:
4477 case VFIXUPIMMPDZrrik:
4478 case VFIXUPIMMPDZrrikz:
4479 return true;
4480 }
4481 return false;
4482}
4483
4484bool isKANDND(unsigned Opcode) {
4485 return Opcode == KANDNDkk;
4486}
4487
4488bool isVMRESUME(unsigned Opcode) {
4489 return Opcode == VMRESUME;
4490}
4491
4492bool isCVTPD2DQ(unsigned Opcode) {
4493 switch (Opcode) {
4494 case CVTPD2DQrm:
4495 case CVTPD2DQrr:
4496 return true;
4497 }
4498 return false;
4499}
4500
4501bool isVFNMADD213PS(unsigned Opcode) {
4502 switch (Opcode) {
4503 case VFNMADD213PSYm:
4504 case VFNMADD213PSYr:
4505 case VFNMADD213PSZ128m:
4506 case VFNMADD213PSZ128mb:
4507 case VFNMADD213PSZ128mbk:
4508 case VFNMADD213PSZ128mbkz:
4509 case VFNMADD213PSZ128mk:
4510 case VFNMADD213PSZ128mkz:
4511 case VFNMADD213PSZ128r:
4512 case VFNMADD213PSZ128rk:
4513 case VFNMADD213PSZ128rkz:
4514 case VFNMADD213PSZ256m:
4515 case VFNMADD213PSZ256mb:
4516 case VFNMADD213PSZ256mbk:
4517 case VFNMADD213PSZ256mbkz:
4518 case VFNMADD213PSZ256mk:
4519 case VFNMADD213PSZ256mkz:
4520 case VFNMADD213PSZ256r:
4521 case VFNMADD213PSZ256rk:
4522 case VFNMADD213PSZ256rkz:
4523 case VFNMADD213PSZm:
4524 case VFNMADD213PSZmb:
4525 case VFNMADD213PSZmbk:
4526 case VFNMADD213PSZmbkz:
4527 case VFNMADD213PSZmk:
4528 case VFNMADD213PSZmkz:
4529 case VFNMADD213PSZr:
4530 case VFNMADD213PSZrb:
4531 case VFNMADD213PSZrbk:
4532 case VFNMADD213PSZrbkz:
4533 case VFNMADD213PSZrk:
4534 case VFNMADD213PSZrkz:
4535 case VFNMADD213PSm:
4536 case VFNMADD213PSr:
4537 return true;
4538 }
4539 return false;
4540}
4541
4542bool isVPEXTRD(unsigned Opcode) {
4543 switch (Opcode) {
4544 case VPEXTRDZmri:
4545 case VPEXTRDZrri:
4546 case VPEXTRDmri:
4547 case VPEXTRDrri:
4548 return true;
4549 }
4550 return false;
4551}
4552
4553bool isPACKUSWB(unsigned Opcode) {
4554 switch (Opcode) {
4555 case MMX_PACKUSWBrm:
4556 case MMX_PACKUSWBrr:
4557 case PACKUSWBrm:
4558 case PACKUSWBrr:
4559 return true;
4560 }
4561 return false;
4562}
4563
4564bool isVEXTRACTI32X8(unsigned Opcode) {
4565 switch (Opcode) {
4566 case VEXTRACTI32X8Zmri:
4567 case VEXTRACTI32X8Zmrik:
4568 case VEXTRACTI32X8Zrri:
4569 case VEXTRACTI32X8Zrrik:
4570 case VEXTRACTI32X8Zrrikz:
4571 return true;
4572 }
4573 return false;
4574}
4575
4576bool isVHADDPD(unsigned Opcode) {
4577 switch (Opcode) {
4578 case VHADDPDYrm:
4579 case VHADDPDYrr:
4580 case VHADDPDrm:
4581 case VHADDPDrr:
4582 return true;
4583 }
4584 return false;
4585}
4586
4587bool isVPSADBW(unsigned Opcode) {
4588 switch (Opcode) {
4589 case VPSADBWYrm:
4590 case VPSADBWYrr:
4591 case VPSADBWZ128rm:
4592 case VPSADBWZ128rr:
4593 case VPSADBWZ256rm:
4594 case VPSADBWZ256rr:
4595 case VPSADBWZrm:
4596 case VPSADBWZrr:
4597 case VPSADBWrm:
4598 case VPSADBWrr:
4599 return true;
4600 }
4601 return false;
4602}
4603
4604bool isMOVDQ2Q(unsigned Opcode) {
4605 return Opcode == MMX_MOVDQ2Qrr;
4606}
4607
4608bool isPUNPCKHBW(unsigned Opcode) {
4609 switch (Opcode) {
4610 case MMX_PUNPCKHBWrm:
4611 case MMX_PUNPCKHBWrr:
4612 case PUNPCKHBWrm:
4613 case PUNPCKHBWrr:
4614 return true;
4615 }
4616 return false;
4617}
4618
4619bool isXOR(unsigned Opcode) {
4620 switch (Opcode) {
4621 case XOR16i16:
4622 case XOR16mi:
4623 case XOR16mi8:
4624 case XOR16mi8_EVEX:
4625 case XOR16mi8_ND:
4626 case XOR16mi8_NF:
4627 case XOR16mi8_NF_ND:
4628 case XOR16mi_EVEX:
4629 case XOR16mi_ND:
4630 case XOR16mi_NF:
4631 case XOR16mi_NF_ND:
4632 case XOR16mr:
4633 case XOR16mr_EVEX:
4634 case XOR16mr_ND:
4635 case XOR16mr_NF:
4636 case XOR16mr_NF_ND:
4637 case XOR16ri:
4638 case XOR16ri8:
4639 case XOR16ri8_EVEX:
4640 case XOR16ri8_ND:
4641 case XOR16ri8_NF:
4642 case XOR16ri8_NF_ND:
4643 case XOR16ri_EVEX:
4644 case XOR16ri_ND:
4645 case XOR16ri_NF:
4646 case XOR16ri_NF_ND:
4647 case XOR16rm:
4648 case XOR16rm_EVEX:
4649 case XOR16rm_ND:
4650 case XOR16rm_NF:
4651 case XOR16rm_NF_ND:
4652 case XOR16rr:
4653 case XOR16rr_EVEX:
4654 case XOR16rr_EVEX_REV:
4655 case XOR16rr_ND:
4656 case XOR16rr_ND_REV:
4657 case XOR16rr_NF:
4658 case XOR16rr_NF_ND:
4659 case XOR16rr_NF_ND_REV:
4660 case XOR16rr_NF_REV:
4661 case XOR16rr_REV:
4662 case XOR32i32:
4663 case XOR32mi:
4664 case XOR32mi8:
4665 case XOR32mi8_EVEX:
4666 case XOR32mi8_ND:
4667 case XOR32mi8_NF:
4668 case XOR32mi8_NF_ND:
4669 case XOR32mi_EVEX:
4670 case XOR32mi_ND:
4671 case XOR32mi_NF:
4672 case XOR32mi_NF_ND:
4673 case XOR32mr:
4674 case XOR32mr_EVEX:
4675 case XOR32mr_ND:
4676 case XOR32mr_NF:
4677 case XOR32mr_NF_ND:
4678 case XOR32ri:
4679 case XOR32ri8:
4680 case XOR32ri8_EVEX:
4681 case XOR32ri8_ND:
4682 case XOR32ri8_NF:
4683 case XOR32ri8_NF_ND:
4684 case XOR32ri_EVEX:
4685 case XOR32ri_ND:
4686 case XOR32ri_NF:
4687 case XOR32ri_NF_ND:
4688 case XOR32rm:
4689 case XOR32rm_EVEX:
4690 case XOR32rm_ND:
4691 case XOR32rm_NF:
4692 case XOR32rm_NF_ND:
4693 case XOR32rr:
4694 case XOR32rr_EVEX:
4695 case XOR32rr_EVEX_REV:
4696 case XOR32rr_ND:
4697 case XOR32rr_ND_REV:
4698 case XOR32rr_NF:
4699 case XOR32rr_NF_ND:
4700 case XOR32rr_NF_ND_REV:
4701 case XOR32rr_NF_REV:
4702 case XOR32rr_REV:
4703 case XOR64i32:
4704 case XOR64mi32:
4705 case XOR64mi32_EVEX:
4706 case XOR64mi32_ND:
4707 case XOR64mi32_NF:
4708 case XOR64mi32_NF_ND:
4709 case XOR64mi8:
4710 case XOR64mi8_EVEX:
4711 case XOR64mi8_ND:
4712 case XOR64mi8_NF:
4713 case XOR64mi8_NF_ND:
4714 case XOR64mr:
4715 case XOR64mr_EVEX:
4716 case XOR64mr_ND:
4717 case XOR64mr_NF:
4718 case XOR64mr_NF_ND:
4719 case XOR64ri32:
4720 case XOR64ri32_EVEX:
4721 case XOR64ri32_ND:
4722 case XOR64ri32_NF:
4723 case XOR64ri32_NF_ND:
4724 case XOR64ri8:
4725 case XOR64ri8_EVEX:
4726 case XOR64ri8_ND:
4727 case XOR64ri8_NF:
4728 case XOR64ri8_NF_ND:
4729 case XOR64rm:
4730 case XOR64rm_EVEX:
4731 case XOR64rm_ND:
4732 case XOR64rm_NF:
4733 case XOR64rm_NF_ND:
4734 case XOR64rr:
4735 case XOR64rr_EVEX:
4736 case XOR64rr_EVEX_REV:
4737 case XOR64rr_ND:
4738 case XOR64rr_ND_REV:
4739 case XOR64rr_NF:
4740 case XOR64rr_NF_ND:
4741 case XOR64rr_NF_ND_REV:
4742 case XOR64rr_NF_REV:
4743 case XOR64rr_REV:
4744 case XOR8i8:
4745 case XOR8mi:
4746 case XOR8mi8:
4747 case XOR8mi_EVEX:
4748 case XOR8mi_ND:
4749 case XOR8mi_NF:
4750 case XOR8mi_NF_ND:
4751 case XOR8mr:
4752 case XOR8mr_EVEX:
4753 case XOR8mr_ND:
4754 case XOR8mr_NF:
4755 case XOR8mr_NF_ND:
4756 case XOR8ri:
4757 case XOR8ri8:
4758 case XOR8ri_EVEX:
4759 case XOR8ri_ND:
4760 case XOR8ri_NF:
4761 case XOR8ri_NF_ND:
4762 case XOR8rm:
4763 case XOR8rm_EVEX:
4764 case XOR8rm_ND:
4765 case XOR8rm_NF:
4766 case XOR8rm_NF_ND:
4767 case XOR8rr:
4768 case XOR8rr_EVEX:
4769 case XOR8rr_EVEX_REV:
4770 case XOR8rr_ND:
4771 case XOR8rr_ND_REV:
4772 case XOR8rr_NF:
4773 case XOR8rr_NF_ND:
4774 case XOR8rr_NF_ND_REV:
4775 case XOR8rr_NF_REV:
4776 case XOR8rr_REV:
4777 return true;
4778 }
4779 return false;
4780}
4781
4782bool isPSIGNB(unsigned Opcode) {
4783 switch (Opcode) {
4784 case MMX_PSIGNBrm:
4785 case MMX_PSIGNBrr:
4786 case PSIGNBrm:
4787 case PSIGNBrr:
4788 return true;
4789 }
4790 return false;
4791}
4792
4793bool isVPHADDSW(unsigned Opcode) {
4794 switch (Opcode) {
4795 case VPHADDSWYrm:
4796 case VPHADDSWYrr:
4797 case VPHADDSWrm:
4798 case VPHADDSWrr:
4799 return true;
4800 }
4801 return false;
4802}
4803
4804bool isFADDP(unsigned Opcode) {
4805 return Opcode == ADD_FPrST0;
4806}
4807
4808bool isNEG(unsigned Opcode) {
4809 switch (Opcode) {
4810 case NEG16m:
4811 case NEG16m_EVEX:
4812 case NEG16m_ND:
4813 case NEG16m_NF:
4814 case NEG16m_NF_ND:
4815 case NEG16r:
4816 case NEG16r_EVEX:
4817 case NEG16r_ND:
4818 case NEG16r_NF:
4819 case NEG16r_NF_ND:
4820 case NEG32m:
4821 case NEG32m_EVEX:
4822 case NEG32m_ND:
4823 case NEG32m_NF:
4824 case NEG32m_NF_ND:
4825 case NEG32r:
4826 case NEG32r_EVEX:
4827 case NEG32r_ND:
4828 case NEG32r_NF:
4829 case NEG32r_NF_ND:
4830 case NEG64m:
4831 case NEG64m_EVEX:
4832 case NEG64m_ND:
4833 case NEG64m_NF:
4834 case NEG64m_NF_ND:
4835 case NEG64r:
4836 case NEG64r_EVEX:
4837 case NEG64r_ND:
4838 case NEG64r_NF:
4839 case NEG64r_NF_ND:
4840 case NEG8m:
4841 case NEG8m_EVEX:
4842 case NEG8m_ND:
4843 case NEG8m_NF:
4844 case NEG8m_NF_ND:
4845 case NEG8r:
4846 case NEG8r_EVEX:
4847 case NEG8r_ND:
4848 case NEG8r_NF:
4849 case NEG8r_NF_ND:
4850 return true;
4851 }
4852 return false;
4853}
4854
4855bool isFLDLG2(unsigned Opcode) {
4856 return Opcode == FLDLG2;
4857}
4858
4859bool isFNOP(unsigned Opcode) {
4860 return Opcode == FNOP;
4861}
4862
4863bool isVMINSS(unsigned Opcode) {
4864 switch (Opcode) {
4865 case VMINSSZrm_Int:
4866 case VMINSSZrmk_Int:
4867 case VMINSSZrmkz_Int:
4868 case VMINSSZrr_Int:
4869 case VMINSSZrrb_Int:
4870 case VMINSSZrrbk_Int:
4871 case VMINSSZrrbkz_Int:
4872 case VMINSSZrrk_Int:
4873 case VMINSSZrrkz_Int:
4874 case VMINSSrm_Int:
4875 case VMINSSrr_Int:
4876 return true;
4877 }
4878 return false;
4879}
4880
4881bool isPCMPISTRM(unsigned Opcode) {
4882 switch (Opcode) {
4883 case PCMPISTRMrmi:
4884 case PCMPISTRMrri:
4885 return true;
4886 }
4887 return false;
4888}
4889
4890bool isVFMADD132SS(unsigned Opcode) {
4891 switch (Opcode) {
4892 case VFMADD132SSZm_Int:
4893 case VFMADD132SSZmk_Int:
4894 case VFMADD132SSZmkz_Int:
4895 case VFMADD132SSZr_Int:
4896 case VFMADD132SSZrb_Int:
4897 case VFMADD132SSZrbk_Int:
4898 case VFMADD132SSZrbkz_Int:
4899 case VFMADD132SSZrk_Int:
4900 case VFMADD132SSZrkz_Int:
4901 case VFMADD132SSm_Int:
4902 case VFMADD132SSr_Int:
4903 return true;
4904 }
4905 return false;
4906}
4907
4908bool isFDIVRP(unsigned Opcode) {
4909 return Opcode == DIVR_FPrST0;
4910}
4911
4912bool isPUSHAL(unsigned Opcode) {
4913 return Opcode == PUSHA32;
4914}
4915
4916bool isSUBSD(unsigned Opcode) {
4917 switch (Opcode) {
4918 case SUBSDrm_Int:
4919 case SUBSDrr_Int:
4920 return true;
4921 }
4922 return false;
4923}
4924
4925bool isVPBLENDMQ(unsigned Opcode) {
4926 switch (Opcode) {
4927 case VPBLENDMQZ128rm:
4928 case VPBLENDMQZ128rmb:
4929 case VPBLENDMQZ128rmbk:
4930 case VPBLENDMQZ128rmbkz:
4931 case VPBLENDMQZ128rmk:
4932 case VPBLENDMQZ128rmkz:
4933 case VPBLENDMQZ128rr:
4934 case VPBLENDMQZ128rrk:
4935 case VPBLENDMQZ128rrkz:
4936 case VPBLENDMQZ256rm:
4937 case VPBLENDMQZ256rmb:
4938 case VPBLENDMQZ256rmbk:
4939 case VPBLENDMQZ256rmbkz:
4940 case VPBLENDMQZ256rmk:
4941 case VPBLENDMQZ256rmkz:
4942 case VPBLENDMQZ256rr:
4943 case VPBLENDMQZ256rrk:
4944 case VPBLENDMQZ256rrkz:
4945 case VPBLENDMQZrm:
4946 case VPBLENDMQZrmb:
4947 case VPBLENDMQZrmbk:
4948 case VPBLENDMQZrmbkz:
4949 case VPBLENDMQZrmk:
4950 case VPBLENDMQZrmkz:
4951 case VPBLENDMQZrr:
4952 case VPBLENDMQZrrk:
4953 case VPBLENDMQZrrkz:
4954 return true;
4955 }
4956 return false;
4957}
4958
4959bool isVPMACSDQL(unsigned Opcode) {
4960 switch (Opcode) {
4961 case VPMACSDQLrm:
4962 case VPMACSDQLrr:
4963 return true;
4964 }
4965 return false;
4966}
4967
4968bool isVGATHERDPS(unsigned Opcode) {
4969 switch (Opcode) {
4970 case VGATHERDPSYrm:
4971 case VGATHERDPSZ128rm:
4972 case VGATHERDPSZ256rm:
4973 case VGATHERDPSZrm:
4974 case VGATHERDPSrm:
4975 return true;
4976 }
4977 return false;
4978}
4979
4980bool isSYSRET(unsigned Opcode) {
4981 return Opcode == SYSRET;
4982}
4983
4984bool isVPADDB(unsigned Opcode) {
4985 switch (Opcode) {
4986 case VPADDBYrm:
4987 case VPADDBYrr:
4988 case VPADDBZ128rm:
4989 case VPADDBZ128rmk:
4990 case VPADDBZ128rmkz:
4991 case VPADDBZ128rr:
4992 case VPADDBZ128rrk:
4993 case VPADDBZ128rrkz:
4994 case VPADDBZ256rm:
4995 case VPADDBZ256rmk:
4996 case VPADDBZ256rmkz:
4997 case VPADDBZ256rr:
4998 case VPADDBZ256rrk:
4999 case VPADDBZ256rrkz:
5000 case VPADDBZrm:
5001 case VPADDBZrmk:
5002 case VPADDBZrmkz:
5003 case VPADDBZrr:
5004 case VPADDBZrrk:
5005 case VPADDBZrrkz:
5006 case VPADDBrm:
5007 case VPADDBrr:
5008 return true;
5009 }
5010 return false;
5011}
5012
5013bool isXEND(unsigned Opcode) {
5014 return Opcode == XEND;
5015}
5016
5017bool isWRSSD(unsigned Opcode) {
5018 switch (Opcode) {
5019 case WRSSD:
5020 case WRSSD_EVEX:
5021 return true;
5022 }
5023 return false;
5024}
5025
5026bool isVMINMAXSS(unsigned Opcode) {
5027 switch (Opcode) {
5028 case VMINMAXSSrmi_Int:
5029 case VMINMAXSSrmik_Int:
5030 case VMINMAXSSrmikz_Int:
5031 case VMINMAXSSrri_Int:
5032 case VMINMAXSSrrib_Int:
5033 case VMINMAXSSrribk_Int:
5034 case VMINMAXSSrribkz_Int:
5035 case VMINMAXSSrrik_Int:
5036 case VMINMAXSSrrikz_Int:
5037 return true;
5038 }
5039 return false;
5040}
5041
5042bool isVCVTDQ2PH(unsigned Opcode) {
5043 switch (Opcode) {
5044 case VCVTDQ2PHZ128rm:
5045 case VCVTDQ2PHZ128rmb:
5046 case VCVTDQ2PHZ128rmbk:
5047 case VCVTDQ2PHZ128rmbkz:
5048 case VCVTDQ2PHZ128rmk:
5049 case VCVTDQ2PHZ128rmkz:
5050 case VCVTDQ2PHZ128rr:
5051 case VCVTDQ2PHZ128rrk:
5052 case VCVTDQ2PHZ128rrkz:
5053 case VCVTDQ2PHZ256rm:
5054 case VCVTDQ2PHZ256rmb:
5055 case VCVTDQ2PHZ256rmbk:
5056 case VCVTDQ2PHZ256rmbkz:
5057 case VCVTDQ2PHZ256rmk:
5058 case VCVTDQ2PHZ256rmkz:
5059 case VCVTDQ2PHZ256rr:
5060 case VCVTDQ2PHZ256rrk:
5061 case VCVTDQ2PHZ256rrkz:
5062 case VCVTDQ2PHZrm:
5063 case VCVTDQ2PHZrmb:
5064 case VCVTDQ2PHZrmbk:
5065 case VCVTDQ2PHZrmbkz:
5066 case VCVTDQ2PHZrmk:
5067 case VCVTDQ2PHZrmkz:
5068 case VCVTDQ2PHZrr:
5069 case VCVTDQ2PHZrrb:
5070 case VCVTDQ2PHZrrbk:
5071 case VCVTDQ2PHZrrbkz:
5072 case VCVTDQ2PHZrrk:
5073 case VCVTDQ2PHZrrkz:
5074 return true;
5075 }
5076 return false;
5077}
5078
5079bool isCVTPD2PS(unsigned Opcode) {
5080 switch (Opcode) {
5081 case CVTPD2PSrm:
5082 case CVTPD2PSrr:
5083 return true;
5084 }
5085 return false;
5086}
5087
5088bool isMAXPD(unsigned Opcode) {
5089 switch (Opcode) {
5090 case MAXPDrm:
5091 case MAXPDrr:
5092 return true;
5093 }
5094 return false;
5095}
5096
5097bool isRCPSS(unsigned Opcode) {
5098 switch (Opcode) {
5099 case RCPSSm_Int:
5100 case RCPSSr_Int:
5101 return true;
5102 }
5103 return false;
5104}
5105
5106bool isVMOVAPD(unsigned Opcode) {
5107 switch (Opcode) {
5108 case VMOVAPDYmr:
5109 case VMOVAPDYrm:
5110 case VMOVAPDYrr:
5111 case VMOVAPDYrr_REV:
5112 case VMOVAPDZ128mr:
5113 case VMOVAPDZ128mrk:
5114 case VMOVAPDZ128rm:
5115 case VMOVAPDZ128rmk:
5116 case VMOVAPDZ128rmkz:
5117 case VMOVAPDZ128rr:
5118 case VMOVAPDZ128rr_REV:
5119 case VMOVAPDZ128rrk:
5120 case VMOVAPDZ128rrk_REV:
5121 case VMOVAPDZ128rrkz:
5122 case VMOVAPDZ128rrkz_REV:
5123 case VMOVAPDZ256mr:
5124 case VMOVAPDZ256mrk:
5125 case VMOVAPDZ256rm:
5126 case VMOVAPDZ256rmk:
5127 case VMOVAPDZ256rmkz:
5128 case VMOVAPDZ256rr:
5129 case VMOVAPDZ256rr_REV:
5130 case VMOVAPDZ256rrk:
5131 case VMOVAPDZ256rrk_REV:
5132 case VMOVAPDZ256rrkz:
5133 case VMOVAPDZ256rrkz_REV:
5134 case VMOVAPDZmr:
5135 case VMOVAPDZmrk:
5136 case VMOVAPDZrm:
5137 case VMOVAPDZrmk:
5138 case VMOVAPDZrmkz:
5139 case VMOVAPDZrr:
5140 case VMOVAPDZrr_REV:
5141 case VMOVAPDZrrk:
5142 case VMOVAPDZrrk_REV:
5143 case VMOVAPDZrrkz:
5144 case VMOVAPDZrrkz_REV:
5145 case VMOVAPDmr:
5146 case VMOVAPDrm:
5147 case VMOVAPDrr:
5148 case VMOVAPDrr_REV:
5149 return true;
5150 }
5151 return false;
5152}
5153
5154bool isVPSUBSB(unsigned Opcode) {
5155 switch (Opcode) {
5156 case VPSUBSBYrm:
5157 case VPSUBSBYrr:
5158 case VPSUBSBZ128rm:
5159 case VPSUBSBZ128rmk:
5160 case VPSUBSBZ128rmkz:
5161 case VPSUBSBZ128rr:
5162 case VPSUBSBZ128rrk:
5163 case VPSUBSBZ128rrkz:
5164 case VPSUBSBZ256rm:
5165 case VPSUBSBZ256rmk:
5166 case VPSUBSBZ256rmkz:
5167 case VPSUBSBZ256rr:
5168 case VPSUBSBZ256rrk:
5169 case VPSUBSBZ256rrkz:
5170 case VPSUBSBZrm:
5171 case VPSUBSBZrmk:
5172 case VPSUBSBZrmkz:
5173 case VPSUBSBZrr:
5174 case VPSUBSBZrrk:
5175 case VPSUBSBZrrkz:
5176 case VPSUBSBrm:
5177 case VPSUBSBrr:
5178 return true;
5179 }
5180 return false;
5181}
5182
5183bool isRDTSC(unsigned Opcode) {
5184 return Opcode == RDTSC;
5185}
5186
5187bool isVCVTTPS2UDQS(unsigned Opcode) {
5188 switch (Opcode) {
5189 case VCVTTPS2UDQSZ128rm:
5190 case VCVTTPS2UDQSZ128rmb:
5191 case VCVTTPS2UDQSZ128rmbk:
5192 case VCVTTPS2UDQSZ128rmbkz:
5193 case VCVTTPS2UDQSZ128rmk:
5194 case VCVTTPS2UDQSZ128rmkz:
5195 case VCVTTPS2UDQSZ128rr:
5196 case VCVTTPS2UDQSZ128rrk:
5197 case VCVTTPS2UDQSZ128rrkz:
5198 case VCVTTPS2UDQSZ256rm:
5199 case VCVTTPS2UDQSZ256rmb:
5200 case VCVTTPS2UDQSZ256rmbk:
5201 case VCVTTPS2UDQSZ256rmbkz:
5202 case VCVTTPS2UDQSZ256rmk:
5203 case VCVTTPS2UDQSZ256rmkz:
5204 case VCVTTPS2UDQSZ256rr:
5205 case VCVTTPS2UDQSZ256rrk:
5206 case VCVTTPS2UDQSZ256rrkz:
5207 case VCVTTPS2UDQSZrm:
5208 case VCVTTPS2UDQSZrmb:
5209 case VCVTTPS2UDQSZrmbk:
5210 case VCVTTPS2UDQSZrmbkz:
5211 case VCVTTPS2UDQSZrmk:
5212 case VCVTTPS2UDQSZrmkz:
5213 case VCVTTPS2UDQSZrr:
5214 case VCVTTPS2UDQSZrrb:
5215 case VCVTTPS2UDQSZrrbk:
5216 case VCVTTPS2UDQSZrrbkz:
5217 case VCVTTPS2UDQSZrrk:
5218 case VCVTTPS2UDQSZrrkz:
5219 return true;
5220 }
5221 return false;
5222}
5223
5224bool isVPMADCSSWD(unsigned Opcode) {
5225 switch (Opcode) {
5226 case VPMADCSSWDrm:
5227 case VPMADCSSWDrr:
5228 return true;
5229 }
5230 return false;
5231}
5232
5233bool isVFNMADD213PH(unsigned Opcode) {
5234 switch (Opcode) {
5235 case VFNMADD213PHZ128m:
5236 case VFNMADD213PHZ128mb:
5237 case VFNMADD213PHZ128mbk:
5238 case VFNMADD213PHZ128mbkz:
5239 case VFNMADD213PHZ128mk:
5240 case VFNMADD213PHZ128mkz:
5241 case VFNMADD213PHZ128r:
5242 case VFNMADD213PHZ128rk:
5243 case VFNMADD213PHZ128rkz:
5244 case VFNMADD213PHZ256m:
5245 case VFNMADD213PHZ256mb:
5246 case VFNMADD213PHZ256mbk:
5247 case VFNMADD213PHZ256mbkz:
5248 case VFNMADD213PHZ256mk:
5249 case VFNMADD213PHZ256mkz:
5250 case VFNMADD213PHZ256r:
5251 case VFNMADD213PHZ256rk:
5252 case VFNMADD213PHZ256rkz:
5253 case VFNMADD213PHZm:
5254 case VFNMADD213PHZmb:
5255 case VFNMADD213PHZmbk:
5256 case VFNMADD213PHZmbkz:
5257 case VFNMADD213PHZmk:
5258 case VFNMADD213PHZmkz:
5259 case VFNMADD213PHZr:
5260 case VFNMADD213PHZrb:
5261 case VFNMADD213PHZrbk:
5262 case VFNMADD213PHZrbkz:
5263 case VFNMADD213PHZrk:
5264 case VFNMADD213PHZrkz:
5265 return true;
5266 }
5267 return false;
5268}
5269
5270bool isVGF2P8AFFINEQB(unsigned Opcode) {
5271 switch (Opcode) {
5272 case VGF2P8AFFINEQBYrmi:
5273 case VGF2P8AFFINEQBYrri:
5274 case VGF2P8AFFINEQBZ128rmbi:
5275 case VGF2P8AFFINEQBZ128rmbik:
5276 case VGF2P8AFFINEQBZ128rmbikz:
5277 case VGF2P8AFFINEQBZ128rmi:
5278 case VGF2P8AFFINEQBZ128rmik:
5279 case VGF2P8AFFINEQBZ128rmikz:
5280 case VGF2P8AFFINEQBZ128rri:
5281 case VGF2P8AFFINEQBZ128rrik:
5282 case VGF2P8AFFINEQBZ128rrikz:
5283 case VGF2P8AFFINEQBZ256rmbi:
5284 case VGF2P8AFFINEQBZ256rmbik:
5285 case VGF2P8AFFINEQBZ256rmbikz:
5286 case VGF2P8AFFINEQBZ256rmi:
5287 case VGF2P8AFFINEQBZ256rmik:
5288 case VGF2P8AFFINEQBZ256rmikz:
5289 case VGF2P8AFFINEQBZ256rri:
5290 case VGF2P8AFFINEQBZ256rrik:
5291 case VGF2P8AFFINEQBZ256rrikz:
5292 case VGF2P8AFFINEQBZrmbi:
5293 case VGF2P8AFFINEQBZrmbik:
5294 case VGF2P8AFFINEQBZrmbikz:
5295 case VGF2P8AFFINEQBZrmi:
5296 case VGF2P8AFFINEQBZrmik:
5297 case VGF2P8AFFINEQBZrmikz:
5298 case VGF2P8AFFINEQBZrri:
5299 case VGF2P8AFFINEQBZrrik:
5300 case VGF2P8AFFINEQBZrrikz:
5301 case VGF2P8AFFINEQBrmi:
5302 case VGF2P8AFFINEQBrri:
5303 return true;
5304 }
5305 return false;
5306}
5307
5308bool isPMOVZXWD(unsigned Opcode) {
5309 switch (Opcode) {
5310 case PMOVZXWDrm:
5311 case PMOVZXWDrr:
5312 return true;
5313 }
5314 return false;
5315}
5316
5317bool isPMINUD(unsigned Opcode) {
5318 switch (Opcode) {
5319 case PMINUDrm:
5320 case PMINUDrr:
5321 return true;
5322 }
5323 return false;
5324}
5325
5326bool isXSUSLDTRK(unsigned Opcode) {
5327 return Opcode == XSUSLDTRK;
5328}
5329
5330bool isVCVTPH2UW(unsigned Opcode) {
5331 switch (Opcode) {
5332 case VCVTPH2UWZ128rm:
5333 case VCVTPH2UWZ128rmb:
5334 case VCVTPH2UWZ128rmbk:
5335 case VCVTPH2UWZ128rmbkz:
5336 case VCVTPH2UWZ128rmk:
5337 case VCVTPH2UWZ128rmkz:
5338 case VCVTPH2UWZ128rr:
5339 case VCVTPH2UWZ128rrk:
5340 case VCVTPH2UWZ128rrkz:
5341 case VCVTPH2UWZ256rm:
5342 case VCVTPH2UWZ256rmb:
5343 case VCVTPH2UWZ256rmbk:
5344 case VCVTPH2UWZ256rmbkz:
5345 case VCVTPH2UWZ256rmk:
5346 case VCVTPH2UWZ256rmkz:
5347 case VCVTPH2UWZ256rr:
5348 case VCVTPH2UWZ256rrk:
5349 case VCVTPH2UWZ256rrkz:
5350 case VCVTPH2UWZrm:
5351 case VCVTPH2UWZrmb:
5352 case VCVTPH2UWZrmbk:
5353 case VCVTPH2UWZrmbkz:
5354 case VCVTPH2UWZrmk:
5355 case VCVTPH2UWZrmkz:
5356 case VCVTPH2UWZrr:
5357 case VCVTPH2UWZrrb:
5358 case VCVTPH2UWZrrbk:
5359 case VCVTPH2UWZrrbkz:
5360 case VCVTPH2UWZrrk:
5361 case VCVTPH2UWZrrkz:
5362 return true;
5363 }
5364 return false;
5365}
5366
5367bool isPADDSW(unsigned Opcode) {
5368 switch (Opcode) {
5369 case MMX_PADDSWrm:
5370 case MMX_PADDSWrr:
5371 case PADDSWrm:
5372 case PADDSWrr:
5373 return true;
5374 }
5375 return false;
5376}
5377
5378bool isLFENCE(unsigned Opcode) {
5379 return Opcode == LFENCE;
5380}
5381
5382bool isCRC32(unsigned Opcode) {
5383 switch (Opcode) {
5384 case CRC32r32m16:
5385 case CRC32r32m16_EVEX:
5386 case CRC32r32m32:
5387 case CRC32r32m32_EVEX:
5388 case CRC32r32m8:
5389 case CRC32r32m8_EVEX:
5390 case CRC32r32r16:
5391 case CRC32r32r16_EVEX:
5392 case CRC32r32r32:
5393 case CRC32r32r32_EVEX:
5394 case CRC32r32r8:
5395 case CRC32r32r8_EVEX:
5396 case CRC32r64m64:
5397 case CRC32r64m64_EVEX:
5398 case CRC32r64m8:
5399 case CRC32r64m8_EVEX:
5400 case CRC32r64r64:
5401 case CRC32r64r64_EVEX:
5402 case CRC32r64r8:
5403 case CRC32r64r8_EVEX:
5404 return true;
5405 }
5406 return false;
5407}
5408
5409bool isAESENCWIDE256KL(unsigned Opcode) {
5410 return Opcode == AESENCWIDE256KL;
5411}
5412
5413bool isMOVAPD(unsigned Opcode) {
5414 switch (Opcode) {
5415 case MOVAPDmr:
5416 case MOVAPDrm:
5417 case MOVAPDrr:
5418 case MOVAPDrr_REV:
5419 return true;
5420 }
5421 return false;
5422}
5423
5424bool isVFMADD213PS(unsigned Opcode) {
5425 switch (Opcode) {
5426 case VFMADD213PSYm:
5427 case VFMADD213PSYr:
5428 case VFMADD213PSZ128m:
5429 case VFMADD213PSZ128mb:
5430 case VFMADD213PSZ128mbk:
5431 case VFMADD213PSZ128mbkz:
5432 case VFMADD213PSZ128mk:
5433 case VFMADD213PSZ128mkz:
5434 case VFMADD213PSZ128r:
5435 case VFMADD213PSZ128rk:
5436 case VFMADD213PSZ128rkz:
5437 case VFMADD213PSZ256m:
5438 case VFMADD213PSZ256mb:
5439 case VFMADD213PSZ256mbk:
5440 case VFMADD213PSZ256mbkz:
5441 case VFMADD213PSZ256mk:
5442 case VFMADD213PSZ256mkz:
5443 case VFMADD213PSZ256r:
5444 case VFMADD213PSZ256rk:
5445 case VFMADD213PSZ256rkz:
5446 case VFMADD213PSZm:
5447 case VFMADD213PSZmb:
5448 case VFMADD213PSZmbk:
5449 case VFMADD213PSZmbkz:
5450 case VFMADD213PSZmk:
5451 case VFMADD213PSZmkz:
5452 case VFMADD213PSZr:
5453 case VFMADD213PSZrb:
5454 case VFMADD213PSZrbk:
5455 case VFMADD213PSZrbkz:
5456 case VFMADD213PSZrk:
5457 case VFMADD213PSZrkz:
5458 case VFMADD213PSm:
5459 case VFMADD213PSr:
5460 return true;
5461 }
5462 return false;
5463}
5464
5465bool isVPDPWUUDS(unsigned Opcode) {
5466 switch (Opcode) {
5467 case VPDPWUUDSYrm:
5468 case VPDPWUUDSYrr:
5469 case VPDPWUUDSZ128rm:
5470 case VPDPWUUDSZ128rmb:
5471 case VPDPWUUDSZ128rmbk:
5472 case VPDPWUUDSZ128rmbkz:
5473 case VPDPWUUDSZ128rmk:
5474 case VPDPWUUDSZ128rmkz:
5475 case VPDPWUUDSZ128rr:
5476 case VPDPWUUDSZ128rrk:
5477 case VPDPWUUDSZ128rrkz:
5478 case VPDPWUUDSZ256rm:
5479 case VPDPWUUDSZ256rmb:
5480 case VPDPWUUDSZ256rmbk:
5481 case VPDPWUUDSZ256rmbkz:
5482 case VPDPWUUDSZ256rmk:
5483 case VPDPWUUDSZ256rmkz:
5484 case VPDPWUUDSZ256rr:
5485 case VPDPWUUDSZ256rrk:
5486 case VPDPWUUDSZ256rrkz:
5487 case VPDPWUUDSZrm:
5488 case VPDPWUUDSZrmb:
5489 case VPDPWUUDSZrmbk:
5490 case VPDPWUUDSZrmbkz:
5491 case VPDPWUUDSZrmk:
5492 case VPDPWUUDSZrmkz:
5493 case VPDPWUUDSZrr:
5494 case VPDPWUUDSZrrk:
5495 case VPDPWUUDSZrrkz:
5496 case VPDPWUUDSrm:
5497 case VPDPWUUDSrr:
5498 return true;
5499 }
5500 return false;
5501}
5502
5503bool isMOVSLDUP(unsigned Opcode) {
5504 switch (Opcode) {
5505 case MOVSLDUPrm:
5506 case MOVSLDUPrr:
5507 return true;
5508 }
5509 return false;
5510}
5511
5512bool isCLDEMOTE(unsigned Opcode) {
5513 return Opcode == CLDEMOTE;
5514}
5515
5516bool isVFNMADD231PS(unsigned Opcode) {
5517 switch (Opcode) {
5518 case VFNMADD231PSYm:
5519 case VFNMADD231PSYr:
5520 case VFNMADD231PSZ128m:
5521 case VFNMADD231PSZ128mb:
5522 case VFNMADD231PSZ128mbk:
5523 case VFNMADD231PSZ128mbkz:
5524 case VFNMADD231PSZ128mk:
5525 case VFNMADD231PSZ128mkz:
5526 case VFNMADD231PSZ128r:
5527 case VFNMADD231PSZ128rk:
5528 case VFNMADD231PSZ128rkz:
5529 case VFNMADD231PSZ256m:
5530 case VFNMADD231PSZ256mb:
5531 case VFNMADD231PSZ256mbk:
5532 case VFNMADD231PSZ256mbkz:
5533 case VFNMADD231PSZ256mk:
5534 case VFNMADD231PSZ256mkz:
5535 case VFNMADD231PSZ256r:
5536 case VFNMADD231PSZ256rk:
5537 case VFNMADD231PSZ256rkz:
5538 case VFNMADD231PSZm:
5539 case VFNMADD231PSZmb:
5540 case VFNMADD231PSZmbk:
5541 case VFNMADD231PSZmbkz:
5542 case VFNMADD231PSZmk:
5543 case VFNMADD231PSZmkz:
5544 case VFNMADD231PSZr:
5545 case VFNMADD231PSZrb:
5546 case VFNMADD231PSZrbk:
5547 case VFNMADD231PSZrbkz:
5548 case VFNMADD231PSZrk:
5549 case VFNMADD231PSZrkz:
5550 case VFNMADD231PSm:
5551 case VFNMADD231PSr:
5552 return true;
5553 }
5554 return false;
5555}
5556
5557bool isVMOVMSKPD(unsigned Opcode) {
5558 switch (Opcode) {
5559 case VMOVMSKPDYrr:
5560 case VMOVMSKPDrr:
5561 return true;
5562 }
5563 return false;
5564}
5565
5566bool isPREFETCHT0(unsigned Opcode) {
5567 return Opcode == PREFETCHT0;
5568}
5569
5570bool isVCVTNEOBF162PS(unsigned Opcode) {
5571 switch (Opcode) {
5572 case VCVTNEOBF162PSYrm:
5573 case VCVTNEOBF162PSrm:
5574 return true;
5575 }
5576 return false;
5577}
5578
5579bool isVPCMPUD(unsigned Opcode) {
5580 switch (Opcode) {
5581 case VPCMPUDZ128rmbi:
5582 case VPCMPUDZ128rmbik:
5583 case VPCMPUDZ128rmi:
5584 case VPCMPUDZ128rmik:
5585 case VPCMPUDZ128rri:
5586 case VPCMPUDZ128rrik:
5587 case VPCMPUDZ256rmbi:
5588 case VPCMPUDZ256rmbik:
5589 case VPCMPUDZ256rmi:
5590 case VPCMPUDZ256rmik:
5591 case VPCMPUDZ256rri:
5592 case VPCMPUDZ256rrik:
5593 case VPCMPUDZrmbi:
5594 case VPCMPUDZrmbik:
5595 case VPCMPUDZrmi:
5596 case VPCMPUDZrmik:
5597 case VPCMPUDZrri:
5598 case VPCMPUDZrrik:
5599 return true;
5600 }
5601 return false;
5602}
5603
5604bool isVMAXSD(unsigned Opcode) {
5605 switch (Opcode) {
5606 case VMAXSDZrm_Int:
5607 case VMAXSDZrmk_Int:
5608 case VMAXSDZrmkz_Int:
5609 case VMAXSDZrr_Int:
5610 case VMAXSDZrrb_Int:
5611 case VMAXSDZrrbk_Int:
5612 case VMAXSDZrrbkz_Int:
5613 case VMAXSDZrrk_Int:
5614 case VMAXSDZrrkz_Int:
5615 case VMAXSDrm_Int:
5616 case VMAXSDrr_Int:
5617 return true;
5618 }
5619 return false;
5620}
5621
5622bool isVRCP28SD(unsigned Opcode) {
5623 switch (Opcode) {
5624 case VRCP28SDZm:
5625 case VRCP28SDZmk:
5626 case VRCP28SDZmkz:
5627 case VRCP28SDZr:
5628 case VRCP28SDZrb:
5629 case VRCP28SDZrbk:
5630 case VRCP28SDZrbkz:
5631 case VRCP28SDZrk:
5632 case VRCP28SDZrkz:
5633 return true;
5634 }
5635 return false;
5636}
5637
5638bool isVMAXPS(unsigned Opcode) {
5639 switch (Opcode) {
5640 case VMAXPSYrm:
5641 case VMAXPSYrr:
5642 case VMAXPSZ128rm:
5643 case VMAXPSZ128rmb:
5644 case VMAXPSZ128rmbk:
5645 case VMAXPSZ128rmbkz:
5646 case VMAXPSZ128rmk:
5647 case VMAXPSZ128rmkz:
5648 case VMAXPSZ128rr:
5649 case VMAXPSZ128rrk:
5650 case VMAXPSZ128rrkz:
5651 case VMAXPSZ256rm:
5652 case VMAXPSZ256rmb:
5653 case VMAXPSZ256rmbk:
5654 case VMAXPSZ256rmbkz:
5655 case VMAXPSZ256rmk:
5656 case VMAXPSZ256rmkz:
5657 case VMAXPSZ256rr:
5658 case VMAXPSZ256rrk:
5659 case VMAXPSZ256rrkz:
5660 case VMAXPSZrm:
5661 case VMAXPSZrmb:
5662 case VMAXPSZrmbk:
5663 case VMAXPSZrmbkz:
5664 case VMAXPSZrmk:
5665 case VMAXPSZrmkz:
5666 case VMAXPSZrr:
5667 case VMAXPSZrrb:
5668 case VMAXPSZrrbk:
5669 case VMAXPSZrrbkz:
5670 case VMAXPSZrrk:
5671 case VMAXPSZrrkz:
5672 case VMAXPSrm:
5673 case VMAXPSrr:
5674 return true;
5675 }
5676 return false;
5677}
5678
5679bool isVPMOVD2M(unsigned Opcode) {
5680 switch (Opcode) {
5681 case VPMOVD2MZ128kr:
5682 case VPMOVD2MZ256kr:
5683 case VPMOVD2MZkr:
5684 return true;
5685 }
5686 return false;
5687}
5688
5689bool isVPMACSSWD(unsigned Opcode) {
5690 switch (Opcode) {
5691 case VPMACSSWDrm:
5692 case VPMACSSWDrr:
5693 return true;
5694 }
5695 return false;
5696}
5697
5698bool isVUCOMISD(unsigned Opcode) {
5699 switch (Opcode) {
5700 case VUCOMISDZrm:
5701 case VUCOMISDZrr:
5702 case VUCOMISDZrrb:
5703 case VUCOMISDrm:
5704 case VUCOMISDrr:
5705 return true;
5706 }
5707 return false;
5708}
5709
5710bool isLTR(unsigned Opcode) {
5711 switch (Opcode) {
5712 case LTRm:
5713 case LTRr:
5714 return true;
5715 }
5716 return false;
5717}
5718
5719bool isVCVTUSI2SH(unsigned Opcode) {
5720 switch (Opcode) {
5721 case VCVTUSI2SHZrm_Int:
5722 case VCVTUSI2SHZrr_Int:
5723 case VCVTUSI2SHZrrb_Int:
5724 case VCVTUSI642SHZrm_Int:
5725 case VCVTUSI642SHZrr_Int:
5726 case VCVTUSI642SHZrrb_Int:
5727 return true;
5728 }
5729 return false;
5730}
5731
5732bool isVSCATTERPF1QPS(unsigned Opcode) {
5733 return Opcode == VSCATTERPF1QPSm;
5734}
5735
5736bool isWRGSBASE(unsigned Opcode) {
5737 switch (Opcode) {
5738 case WRGSBASE:
5739 case WRGSBASE64:
5740 return true;
5741 }
5742 return false;
5743}
5744
5745bool isSTOSQ(unsigned Opcode) {
5746 return Opcode == STOSQ;
5747}
5748
5749bool isVSQRTSD(unsigned Opcode) {
5750 switch (Opcode) {
5751 case VSQRTSDZm_Int:
5752 case VSQRTSDZmk_Int:
5753 case VSQRTSDZmkz_Int:
5754 case VSQRTSDZr_Int:
5755 case VSQRTSDZrb_Int:
5756 case VSQRTSDZrbk_Int:
5757 case VSQRTSDZrbkz_Int:
5758 case VSQRTSDZrk_Int:
5759 case VSQRTSDZrkz_Int:
5760 case VSQRTSDm_Int:
5761 case VSQRTSDr_Int:
5762 return true;
5763 }
5764 return false;
5765}
5766
5767bool isVPERMIL2PD(unsigned Opcode) {
5768 switch (Opcode) {
5769 case VPERMIL2PDYmr:
5770 case VPERMIL2PDYrm:
5771 case VPERMIL2PDYrr:
5772 case VPERMIL2PDYrr_REV:
5773 case VPERMIL2PDmr:
5774 case VPERMIL2PDrm:
5775 case VPERMIL2PDrr:
5776 case VPERMIL2PDrr_REV:
5777 return true;
5778 }
5779 return false;
5780}
5781
5782bool isVFCMADDCSH(unsigned Opcode) {
5783 switch (Opcode) {
5784 case VFCMADDCSHZm:
5785 case VFCMADDCSHZmk:
5786 case VFCMADDCSHZmkz:
5787 case VFCMADDCSHZr:
5788 case VFCMADDCSHZrb:
5789 case VFCMADDCSHZrbk:
5790 case VFCMADDCSHZrbkz:
5791 case VFCMADDCSHZrk:
5792 case VFCMADDCSHZrkz:
5793 return true;
5794 }
5795 return false;
5796}
5797
5798bool isVFMADDSUB213PS(unsigned Opcode) {
5799 switch (Opcode) {
5800 case VFMADDSUB213PSYm:
5801 case VFMADDSUB213PSYr:
5802 case VFMADDSUB213PSZ128m:
5803 case VFMADDSUB213PSZ128mb:
5804 case VFMADDSUB213PSZ128mbk:
5805 case VFMADDSUB213PSZ128mbkz:
5806 case VFMADDSUB213PSZ128mk:
5807 case VFMADDSUB213PSZ128mkz:
5808 case VFMADDSUB213PSZ128r:
5809 case VFMADDSUB213PSZ128rk:
5810 case VFMADDSUB213PSZ128rkz:
5811 case VFMADDSUB213PSZ256m:
5812 case VFMADDSUB213PSZ256mb:
5813 case VFMADDSUB213PSZ256mbk:
5814 case VFMADDSUB213PSZ256mbkz:
5815 case VFMADDSUB213PSZ256mk:
5816 case VFMADDSUB213PSZ256mkz:
5817 case VFMADDSUB213PSZ256r:
5818 case VFMADDSUB213PSZ256rk:
5819 case VFMADDSUB213PSZ256rkz:
5820 case VFMADDSUB213PSZm:
5821 case VFMADDSUB213PSZmb:
5822 case VFMADDSUB213PSZmbk:
5823 case VFMADDSUB213PSZmbkz:
5824 case VFMADDSUB213PSZmk:
5825 case VFMADDSUB213PSZmkz:
5826 case VFMADDSUB213PSZr:
5827 case VFMADDSUB213PSZrb:
5828 case VFMADDSUB213PSZrbk:
5829 case VFMADDSUB213PSZrbkz:
5830 case VFMADDSUB213PSZrk:
5831 case VFMADDSUB213PSZrkz:
5832 case VFMADDSUB213PSm:
5833 case VFMADDSUB213PSr:
5834 return true;
5835 }
5836 return false;
5837}
5838
5839bool isPFSUB(unsigned Opcode) {
5840 switch (Opcode) {
5841 case PFSUBrm:
5842 case PFSUBrr:
5843 return true;
5844 }
5845 return false;
5846}
5847
5848bool isVSQRTSS(unsigned Opcode) {
5849 switch (Opcode) {
5850 case VSQRTSSZm_Int:
5851 case VSQRTSSZmk_Int:
5852 case VSQRTSSZmkz_Int:
5853 case VSQRTSSZr_Int:
5854 case VSQRTSSZrb_Int:
5855 case VSQRTSSZrbk_Int:
5856 case VSQRTSSZrbkz_Int:
5857 case VSQRTSSZrk_Int:
5858 case VSQRTSSZrkz_Int:
5859 case VSQRTSSm_Int:
5860 case VSQRTSSr_Int:
5861 return true;
5862 }
5863 return false;
5864}
5865
5866bool isVEXPANDPS(unsigned Opcode) {
5867 switch (Opcode) {
5868 case VEXPANDPSZ128rm:
5869 case VEXPANDPSZ128rmk:
5870 case VEXPANDPSZ128rmkz:
5871 case VEXPANDPSZ128rr:
5872 case VEXPANDPSZ128rrk:
5873 case VEXPANDPSZ128rrkz:
5874 case VEXPANDPSZ256rm:
5875 case VEXPANDPSZ256rmk:
5876 case VEXPANDPSZ256rmkz:
5877 case VEXPANDPSZ256rr:
5878 case VEXPANDPSZ256rrk:
5879 case VEXPANDPSZ256rrkz:
5880 case VEXPANDPSZrm:
5881 case VEXPANDPSZrmk:
5882 case VEXPANDPSZrmkz:
5883 case VEXPANDPSZrr:
5884 case VEXPANDPSZrrk:
5885 case VEXPANDPSZrrkz:
5886 return true;
5887 }
5888 return false;
5889}
5890
5891bool isVPCOMPRESSW(unsigned Opcode) {
5892 switch (Opcode) {
5893 case VPCOMPRESSWZ128mr:
5894 case VPCOMPRESSWZ128mrk:
5895 case VPCOMPRESSWZ128rr:
5896 case VPCOMPRESSWZ128rrk:
5897 case VPCOMPRESSWZ128rrkz:
5898 case VPCOMPRESSWZ256mr:
5899 case VPCOMPRESSWZ256mrk:
5900 case VPCOMPRESSWZ256rr:
5901 case VPCOMPRESSWZ256rrk:
5902 case VPCOMPRESSWZ256rrkz:
5903 case VPCOMPRESSWZmr:
5904 case VPCOMPRESSWZmrk:
5905 case VPCOMPRESSWZrr:
5906 case VPCOMPRESSWZrrk:
5907 case VPCOMPRESSWZrrkz:
5908 return true;
5909 }
5910 return false;
5911}
5912
5913bool isPEXTRD(unsigned Opcode) {
5914 switch (Opcode) {
5915 case PEXTRDmri:
5916 case PEXTRDrri:
5917 return true;
5918 }
5919 return false;
5920}
5921
5922bool isVCVTTPS2UQQS(unsigned Opcode) {
5923 switch (Opcode) {
5924 case VCVTTPS2UQQSZ128rm:
5925 case VCVTTPS2UQQSZ128rmb:
5926 case VCVTTPS2UQQSZ128rmbk:
5927 case VCVTTPS2UQQSZ128rmbkz:
5928 case VCVTTPS2UQQSZ128rmk:
5929 case VCVTTPS2UQQSZ128rmkz:
5930 case VCVTTPS2UQQSZ128rr:
5931 case VCVTTPS2UQQSZ128rrk:
5932 case VCVTTPS2UQQSZ128rrkz:
5933 case VCVTTPS2UQQSZ256rm:
5934 case VCVTTPS2UQQSZ256rmb:
5935 case VCVTTPS2UQQSZ256rmbk:
5936 case VCVTTPS2UQQSZ256rmbkz:
5937 case VCVTTPS2UQQSZ256rmk:
5938 case VCVTTPS2UQQSZ256rmkz:
5939 case VCVTTPS2UQQSZ256rr:
5940 case VCVTTPS2UQQSZ256rrb:
5941 case VCVTTPS2UQQSZ256rrbk:
5942 case VCVTTPS2UQQSZ256rrbkz:
5943 case VCVTTPS2UQQSZ256rrk:
5944 case VCVTTPS2UQQSZ256rrkz:
5945 case VCVTTPS2UQQSZrm:
5946 case VCVTTPS2UQQSZrmb:
5947 case VCVTTPS2UQQSZrmbk:
5948 case VCVTTPS2UQQSZrmbkz:
5949 case VCVTTPS2UQQSZrmk:
5950 case VCVTTPS2UQQSZrmkz:
5951 case VCVTTPS2UQQSZrr:
5952 case VCVTTPS2UQQSZrrb:
5953 case VCVTTPS2UQQSZrrbk:
5954 case VCVTTPS2UQQSZrrbkz:
5955 case VCVTTPS2UQQSZrrk:
5956 case VCVTTPS2UQQSZrrkz:
5957 return true;
5958 }
5959 return false;
5960}
5961
5962bool isSYSEXITQ(unsigned Opcode) {
5963 return Opcode == SYSEXIT64;
5964}
5965
5966bool isROUNDSD(unsigned Opcode) {
5967 switch (Opcode) {
5968 case ROUNDSDmi_Int:
5969 case ROUNDSDri_Int:
5970 return true;
5971 }
5972 return false;
5973}
5974
5975bool isVFMADD132BF16(unsigned Opcode) {
5976 switch (Opcode) {
5977 case VFMADD132BF16Z128m:
5978 case VFMADD132BF16Z128mb:
5979 case VFMADD132BF16Z128mbk:
5980 case VFMADD132BF16Z128mbkz:
5981 case VFMADD132BF16Z128mk:
5982 case VFMADD132BF16Z128mkz:
5983 case VFMADD132BF16Z128r:
5984 case VFMADD132BF16Z128rk:
5985 case VFMADD132BF16Z128rkz:
5986 case VFMADD132BF16Z256m:
5987 case VFMADD132BF16Z256mb:
5988 case VFMADD132BF16Z256mbk:
5989 case VFMADD132BF16Z256mbkz:
5990 case VFMADD132BF16Z256mk:
5991 case VFMADD132BF16Z256mkz:
5992 case VFMADD132BF16Z256r:
5993 case VFMADD132BF16Z256rk:
5994 case VFMADD132BF16Z256rkz:
5995 case VFMADD132BF16Zm:
5996 case VFMADD132BF16Zmb:
5997 case VFMADD132BF16Zmbk:
5998 case VFMADD132BF16Zmbkz:
5999 case VFMADD132BF16Zmk:
6000 case VFMADD132BF16Zmkz:
6001 case VFMADD132BF16Zr:
6002 case VFMADD132BF16Zrk:
6003 case VFMADD132BF16Zrkz:
6004 return true;
6005 }
6006 return false;
6007}
6008
6009bool isFCOM(unsigned Opcode) {
6010 switch (Opcode) {
6011 case COM_FST0r:
6012 case FCOM32m:
6013 case FCOM64m:
6014 return true;
6015 }
6016 return false;
6017}
6018
6019bool isVFNMSUBSS(unsigned Opcode) {
6020 switch (Opcode) {
6021 case VFNMSUBSS4mr:
6022 case VFNMSUBSS4rm:
6023 case VFNMSUBSS4rr:
6024 case VFNMSUBSS4rr_REV:
6025 return true;
6026 }
6027 return false;
6028}
6029
6030bool isKSHIFTLW(unsigned Opcode) {
6031 return Opcode == KSHIFTLWki;
6032}
6033
6034bool isVMPTRLD(unsigned Opcode) {
6035 return Opcode == VMPTRLDm;
6036}
6037
6038bool isSCASD(unsigned Opcode) {
6039 return Opcode == SCASL;
6040}
6041
6042bool isVAESDECLAST(unsigned Opcode) {
6043 switch (Opcode) {
6044 case VAESDECLASTYrm:
6045 case VAESDECLASTYrr:
6046 case VAESDECLASTZ128rm:
6047 case VAESDECLASTZ128rr:
6048 case VAESDECLASTZ256rm:
6049 case VAESDECLASTZ256rr:
6050 case VAESDECLASTZrm:
6051 case VAESDECLASTZrr:
6052 case VAESDECLASTrm:
6053 case VAESDECLASTrr:
6054 return true;
6055 }
6056 return false;
6057}
6058
6059bool isVFMADDSUBPS(unsigned Opcode) {
6060 switch (Opcode) {
6061 case VFMADDSUBPS4Ymr:
6062 case VFMADDSUBPS4Yrm:
6063 case VFMADDSUBPS4Yrr:
6064 case VFMADDSUBPS4Yrr_REV:
6065 case VFMADDSUBPS4mr:
6066 case VFMADDSUBPS4rm:
6067 case VFMADDSUBPS4rr:
6068 case VFMADDSUBPS4rr_REV:
6069 return true;
6070 }
6071 return false;
6072}
6073
6074bool isVCVTUQQ2PS(unsigned Opcode) {
6075 switch (Opcode) {
6076 case VCVTUQQ2PSZ128rm:
6077 case VCVTUQQ2PSZ128rmb:
6078 case VCVTUQQ2PSZ128rmbk:
6079 case VCVTUQQ2PSZ128rmbkz:
6080 case VCVTUQQ2PSZ128rmk:
6081 case VCVTUQQ2PSZ128rmkz:
6082 case VCVTUQQ2PSZ128rr:
6083 case VCVTUQQ2PSZ128rrk:
6084 case VCVTUQQ2PSZ128rrkz:
6085 case VCVTUQQ2PSZ256rm:
6086 case VCVTUQQ2PSZ256rmb:
6087 case VCVTUQQ2PSZ256rmbk:
6088 case VCVTUQQ2PSZ256rmbkz:
6089 case VCVTUQQ2PSZ256rmk:
6090 case VCVTUQQ2PSZ256rmkz:
6091 case VCVTUQQ2PSZ256rr:
6092 case VCVTUQQ2PSZ256rrk:
6093 case VCVTUQQ2PSZ256rrkz:
6094 case VCVTUQQ2PSZrm:
6095 case VCVTUQQ2PSZrmb:
6096 case VCVTUQQ2PSZrmbk:
6097 case VCVTUQQ2PSZrmbkz:
6098 case VCVTUQQ2PSZrmk:
6099 case VCVTUQQ2PSZrmkz:
6100 case VCVTUQQ2PSZrr:
6101 case VCVTUQQ2PSZrrb:
6102 case VCVTUQQ2PSZrrbk:
6103 case VCVTUQQ2PSZrrbkz:
6104 case VCVTUQQ2PSZrrk:
6105 case VCVTUQQ2PSZrrkz:
6106 return true;
6107 }
6108 return false;
6109}
6110
6111bool isVPMOVUSDB(unsigned Opcode) {
6112 switch (Opcode) {
6113 case VPMOVUSDBZ128mr:
6114 case VPMOVUSDBZ128mrk:
6115 case VPMOVUSDBZ128rr:
6116 case VPMOVUSDBZ128rrk:
6117 case VPMOVUSDBZ128rrkz:
6118 case VPMOVUSDBZ256mr:
6119 case VPMOVUSDBZ256mrk:
6120 case VPMOVUSDBZ256rr:
6121 case VPMOVUSDBZ256rrk:
6122 case VPMOVUSDBZ256rrkz:
6123 case VPMOVUSDBZmr:
6124 case VPMOVUSDBZmrk:
6125 case VPMOVUSDBZrr:
6126 case VPMOVUSDBZrrk:
6127 case VPMOVUSDBZrrkz:
6128 return true;
6129 }
6130 return false;
6131}
6132
6133bool isVPROTW(unsigned Opcode) {
6134 switch (Opcode) {
6135 case VPROTWmi:
6136 case VPROTWmr:
6137 case VPROTWri:
6138 case VPROTWrm:
6139 case VPROTWrr:
6140 case VPROTWrr_REV:
6141 return true;
6142 }
6143 return false;
6144}
6145
6146bool isVDPPS(unsigned Opcode) {
6147 switch (Opcode) {
6148 case VDPPSYrmi:
6149 case VDPPSYrri:
6150 case VDPPSrmi:
6151 case VDPPSrri:
6152 return true;
6153 }
6154 return false;
6155}
6156
6157bool isVRSQRT14PD(unsigned Opcode) {
6158 switch (Opcode) {
6159 case VRSQRT14PDZ128m:
6160 case VRSQRT14PDZ128mb:
6161 case VRSQRT14PDZ128mbk:
6162 case VRSQRT14PDZ128mbkz:
6163 case VRSQRT14PDZ128mk:
6164 case VRSQRT14PDZ128mkz:
6165 case VRSQRT14PDZ128r:
6166 case VRSQRT14PDZ128rk:
6167 case VRSQRT14PDZ128rkz:
6168 case VRSQRT14PDZ256m:
6169 case VRSQRT14PDZ256mb:
6170 case VRSQRT14PDZ256mbk:
6171 case VRSQRT14PDZ256mbkz:
6172 case VRSQRT14PDZ256mk:
6173 case VRSQRT14PDZ256mkz:
6174 case VRSQRT14PDZ256r:
6175 case VRSQRT14PDZ256rk:
6176 case VRSQRT14PDZ256rkz:
6177 case VRSQRT14PDZm:
6178 case VRSQRT14PDZmb:
6179 case VRSQRT14PDZmbk:
6180 case VRSQRT14PDZmbkz:
6181 case VRSQRT14PDZmk:
6182 case VRSQRT14PDZmkz:
6183 case VRSQRT14PDZr:
6184 case VRSQRT14PDZrk:
6185 case VRSQRT14PDZrkz:
6186 return true;
6187 }
6188 return false;
6189}
6190
6191bool isVTESTPD(unsigned Opcode) {
6192 switch (Opcode) {
6193 case VTESTPDYrm:
6194 case VTESTPDYrr:
6195 case VTESTPDrm:
6196 case VTESTPDrr:
6197 return true;
6198 }
6199 return false;
6200}
6201
6202bool isVFNMADD231SH(unsigned Opcode) {
6203 switch (Opcode) {
6204 case VFNMADD231SHZm_Int:
6205 case VFNMADD231SHZmk_Int:
6206 case VFNMADD231SHZmkz_Int:
6207 case VFNMADD231SHZr_Int:
6208 case VFNMADD231SHZrb_Int:
6209 case VFNMADD231SHZrbk_Int:
6210 case VFNMADD231SHZrbkz_Int:
6211 case VFNMADD231SHZrk_Int:
6212 case VFNMADD231SHZrkz_Int:
6213 return true;
6214 }
6215 return false;
6216}
6217
6218bool isENDBR64(unsigned Opcode) {
6219 return Opcode == ENDBR64;
6220}
6221
6222bool isMULSD(unsigned Opcode) {
6223 switch (Opcode) {
6224 case MULSDrm_Int:
6225 case MULSDrr_Int:
6226 return true;
6227 }
6228 return false;
6229}
6230
6231bool isXRSTORS(unsigned Opcode) {
6232 return Opcode == XRSTORS;
6233}
6234
6235bool isPREFETCHNTA(unsigned Opcode) {
6236 return Opcode == PREFETCHNTA;
6237}
6238
6239bool isVPCOMD(unsigned Opcode) {
6240 switch (Opcode) {
6241 case VPCOMDmi:
6242 case VPCOMDri:
6243 return true;
6244 }
6245 return false;
6246}
6247
6248bool isVPCOMUB(unsigned Opcode) {
6249 switch (Opcode) {
6250 case VPCOMUBmi:
6251 case VPCOMUBri:
6252 return true;
6253 }
6254 return false;
6255}
6256
6257bool isVPDPBSSD(unsigned Opcode) {
6258 switch (Opcode) {
6259 case VPDPBSSDYrm:
6260 case VPDPBSSDYrr:
6261 case VPDPBSSDZ128rm:
6262 case VPDPBSSDZ128rmb:
6263 case VPDPBSSDZ128rmbk:
6264 case VPDPBSSDZ128rmbkz:
6265 case VPDPBSSDZ128rmk:
6266 case VPDPBSSDZ128rmkz:
6267 case VPDPBSSDZ128rr:
6268 case VPDPBSSDZ128rrk:
6269 case VPDPBSSDZ128rrkz:
6270 case VPDPBSSDZ256rm:
6271 case VPDPBSSDZ256rmb:
6272 case VPDPBSSDZ256rmbk:
6273 case VPDPBSSDZ256rmbkz:
6274 case VPDPBSSDZ256rmk:
6275 case VPDPBSSDZ256rmkz:
6276 case VPDPBSSDZ256rr:
6277 case VPDPBSSDZ256rrk:
6278 case VPDPBSSDZ256rrkz:
6279 case VPDPBSSDZrm:
6280 case VPDPBSSDZrmb:
6281 case VPDPBSSDZrmbk:
6282 case VPDPBSSDZrmbkz:
6283 case VPDPBSSDZrmk:
6284 case VPDPBSSDZrmkz:
6285 case VPDPBSSDZrr:
6286 case VPDPBSSDZrrk:
6287 case VPDPBSSDZrrkz:
6288 case VPDPBSSDrm:
6289 case VPDPBSSDrr:
6290 return true;
6291 }
6292 return false;
6293}
6294
6295bool isVPHSUBD(unsigned Opcode) {
6296 switch (Opcode) {
6297 case VPHSUBDYrm:
6298 case VPHSUBDYrr:
6299 case VPHSUBDrm:
6300 case VPHSUBDrr:
6301 return true;
6302 }
6303 return false;
6304}
6305
6306bool isVBROADCASTI64X2(unsigned Opcode) {
6307 switch (Opcode) {
6308 case VBROADCASTI64X2Z256rm:
6309 case VBROADCASTI64X2Z256rmk:
6310 case VBROADCASTI64X2Z256rmkz:
6311 case VBROADCASTI64X2Zrm:
6312 case VBROADCASTI64X2Zrmk:
6313 case VBROADCASTI64X2Zrmkz:
6314 return true;
6315 }
6316 return false;
6317}
6318
6319bool isFPATAN(unsigned Opcode) {
6320 return Opcode == FPATAN;
6321}
6322
6323bool isLOOPE(unsigned Opcode) {
6324 return Opcode == LOOPE;
6325}
6326
6327bool isPCMPEQW(unsigned Opcode) {
6328 switch (Opcode) {
6329 case MMX_PCMPEQWrm:
6330 case MMX_PCMPEQWrr:
6331 case PCMPEQWrm:
6332 case PCMPEQWrr:
6333 return true;
6334 }
6335 return false;
6336}
6337
6338bool isVFMADDCSH(unsigned Opcode) {
6339 switch (Opcode) {
6340 case VFMADDCSHZm:
6341 case VFMADDCSHZmk:
6342 case VFMADDCSHZmkz:
6343 case VFMADDCSHZr:
6344 case VFMADDCSHZrb:
6345 case VFMADDCSHZrbk:
6346 case VFMADDCSHZrbkz:
6347 case VFMADDCSHZrk:
6348 case VFMADDCSHZrkz:
6349 return true;
6350 }
6351 return false;
6352}
6353
6354bool isMOVRS(unsigned Opcode) {
6355 switch (Opcode) {
6356 case MOVRS16rm:
6357 case MOVRS16rm_EVEX:
6358 case MOVRS32rm:
6359 case MOVRS32rm_EVEX:
6360 case MOVRS64rm:
6361 case MOVRS64rm_EVEX:
6362 case MOVRS8rm:
6363 case MOVRS8rm_EVEX:
6364 return true;
6365 }
6366 return false;
6367}
6368
6369bool isVFMSUBADD132PH(unsigned Opcode) {
6370 switch (Opcode) {
6371 case VFMSUBADD132PHZ128m:
6372 case VFMSUBADD132PHZ128mb:
6373 case VFMSUBADD132PHZ128mbk:
6374 case VFMSUBADD132PHZ128mbkz:
6375 case VFMSUBADD132PHZ128mk:
6376 case VFMSUBADD132PHZ128mkz:
6377 case VFMSUBADD132PHZ128r:
6378 case VFMSUBADD132PHZ128rk:
6379 case VFMSUBADD132PHZ128rkz:
6380 case VFMSUBADD132PHZ256m:
6381 case VFMSUBADD132PHZ256mb:
6382 case VFMSUBADD132PHZ256mbk:
6383 case VFMSUBADD132PHZ256mbkz:
6384 case VFMSUBADD132PHZ256mk:
6385 case VFMSUBADD132PHZ256mkz:
6386 case VFMSUBADD132PHZ256r:
6387 case VFMSUBADD132PHZ256rk:
6388 case VFMSUBADD132PHZ256rkz:
6389 case VFMSUBADD132PHZm:
6390 case VFMSUBADD132PHZmb:
6391 case VFMSUBADD132PHZmbk:
6392 case VFMSUBADD132PHZmbkz:
6393 case VFMSUBADD132PHZmk:
6394 case VFMSUBADD132PHZmkz:
6395 case VFMSUBADD132PHZr:
6396 case VFMSUBADD132PHZrb:
6397 case VFMSUBADD132PHZrbk:
6398 case VFMSUBADD132PHZrbkz:
6399 case VFMSUBADD132PHZrk:
6400 case VFMSUBADD132PHZrkz:
6401 return true;
6402 }
6403 return false;
6404}
6405
6406bool isKADDW(unsigned Opcode) {
6407 return Opcode == KADDWkk;
6408}
6409
6410bool isPTEST(unsigned Opcode) {
6411 switch (Opcode) {
6412 case PTESTrm:
6413 case PTESTrr:
6414 return true;
6415 }
6416 return false;
6417}
6418
6419bool isVPADDSB(unsigned Opcode) {
6420 switch (Opcode) {
6421 case VPADDSBYrm:
6422 case VPADDSBYrr:
6423 case VPADDSBZ128rm:
6424 case VPADDSBZ128rmk:
6425 case VPADDSBZ128rmkz:
6426 case VPADDSBZ128rr:
6427 case VPADDSBZ128rrk:
6428 case VPADDSBZ128rrkz:
6429 case VPADDSBZ256rm:
6430 case VPADDSBZ256rmk:
6431 case VPADDSBZ256rmkz:
6432 case VPADDSBZ256rr:
6433 case VPADDSBZ256rrk:
6434 case VPADDSBZ256rrkz:
6435 case VPADDSBZrm:
6436 case VPADDSBZrmk:
6437 case VPADDSBZrmkz:
6438 case VPADDSBZrr:
6439 case VPADDSBZrrk:
6440 case VPADDSBZrrkz:
6441 case VPADDSBrm:
6442 case VPADDSBrr:
6443 return true;
6444 }
6445 return false;
6446}
6447
6448bool isVRSQRT28PS(unsigned Opcode) {
6449 switch (Opcode) {
6450 case VRSQRT28PSZm:
6451 case VRSQRT28PSZmb:
6452 case VRSQRT28PSZmbk:
6453 case VRSQRT28PSZmbkz:
6454 case VRSQRT28PSZmk:
6455 case VRSQRT28PSZmkz:
6456 case VRSQRT28PSZr:
6457 case VRSQRT28PSZrb:
6458 case VRSQRT28PSZrbk:
6459 case VRSQRT28PSZrbkz:
6460 case VRSQRT28PSZrk:
6461 case VRSQRT28PSZrkz:
6462 return true;
6463 }
6464 return false;
6465}
6466
6467bool isVGF2P8AFFINEINVQB(unsigned Opcode) {
6468 switch (Opcode) {
6469 case VGF2P8AFFINEINVQBYrmi:
6470 case VGF2P8AFFINEINVQBYrri:
6471 case VGF2P8AFFINEINVQBZ128rmbi:
6472 case VGF2P8AFFINEINVQBZ128rmbik:
6473 case VGF2P8AFFINEINVQBZ128rmbikz:
6474 case VGF2P8AFFINEINVQBZ128rmi:
6475 case VGF2P8AFFINEINVQBZ128rmik:
6476 case VGF2P8AFFINEINVQBZ128rmikz:
6477 case VGF2P8AFFINEINVQBZ128rri:
6478 case VGF2P8AFFINEINVQBZ128rrik:
6479 case VGF2P8AFFINEINVQBZ128rrikz:
6480 case VGF2P8AFFINEINVQBZ256rmbi:
6481 case VGF2P8AFFINEINVQBZ256rmbik:
6482 case VGF2P8AFFINEINVQBZ256rmbikz:
6483 case VGF2P8AFFINEINVQBZ256rmi:
6484 case VGF2P8AFFINEINVQBZ256rmik:
6485 case VGF2P8AFFINEINVQBZ256rmikz:
6486 case VGF2P8AFFINEINVQBZ256rri:
6487 case VGF2P8AFFINEINVQBZ256rrik:
6488 case VGF2P8AFFINEINVQBZ256rrikz:
6489 case VGF2P8AFFINEINVQBZrmbi:
6490 case VGF2P8AFFINEINVQBZrmbik:
6491 case VGF2P8AFFINEINVQBZrmbikz:
6492 case VGF2P8AFFINEINVQBZrmi:
6493 case VGF2P8AFFINEINVQBZrmik:
6494 case VGF2P8AFFINEINVQBZrmikz:
6495 case VGF2P8AFFINEINVQBZrri:
6496 case VGF2P8AFFINEINVQBZrrik:
6497 case VGF2P8AFFINEINVQBZrrikz:
6498 case VGF2P8AFFINEINVQBrmi:
6499 case VGF2P8AFFINEINVQBrri:
6500 return true;
6501 }
6502 return false;
6503}
6504
6505bool isSERIALIZE(unsigned Opcode) {
6506 return Opcode == SERIALIZE;
6507}
6508
6509bool isVPHADDWQ(unsigned Opcode) {
6510 switch (Opcode) {
6511 case VPHADDWQrm:
6512 case VPHADDWQrr:
6513 return true;
6514 }
6515 return false;
6516}
6517
6518bool isVRNDSCALESH(unsigned Opcode) {
6519 switch (Opcode) {
6520 case VRNDSCALESHZrmi_Int:
6521 case VRNDSCALESHZrmik_Int:
6522 case VRNDSCALESHZrmikz_Int:
6523 case VRNDSCALESHZrri_Int:
6524 case VRNDSCALESHZrrib_Int:
6525 case VRNDSCALESHZrribk_Int:
6526 case VRNDSCALESHZrribkz_Int:
6527 case VRNDSCALESHZrrik_Int:
6528 case VRNDSCALESHZrrikz_Int:
6529 return true;
6530 }
6531 return false;
6532}
6533
6534bool isAAA(unsigned Opcode) {
6535 return Opcode == AAA;
6536}
6537
6538bool isVADDBF16(unsigned Opcode) {
6539 switch (Opcode) {
6540 case VADDBF16Z128rm:
6541 case VADDBF16Z128rmb:
6542 case VADDBF16Z128rmbk:
6543 case VADDBF16Z128rmbkz:
6544 case VADDBF16Z128rmk:
6545 case VADDBF16Z128rmkz:
6546 case VADDBF16Z128rr:
6547 case VADDBF16Z128rrk:
6548 case VADDBF16Z128rrkz:
6549 case VADDBF16Z256rm:
6550 case VADDBF16Z256rmb:
6551 case VADDBF16Z256rmbk:
6552 case VADDBF16Z256rmbkz:
6553 case VADDBF16Z256rmk:
6554 case VADDBF16Z256rmkz:
6555 case VADDBF16Z256rr:
6556 case VADDBF16Z256rrk:
6557 case VADDBF16Z256rrkz:
6558 case VADDBF16Zrm:
6559 case VADDBF16Zrmb:
6560 case VADDBF16Zrmbk:
6561 case VADDBF16Zrmbkz:
6562 case VADDBF16Zrmk:
6563 case VADDBF16Zrmkz:
6564 case VADDBF16Zrr:
6565 case VADDBF16Zrrk:
6566 case VADDBF16Zrrkz:
6567 return true;
6568 }
6569 return false;
6570}
6571
6572bool isWRMSRLIST(unsigned Opcode) {
6573 return Opcode == WRMSRLIST;
6574}
6575
6576bool isVCVTPH2PSX(unsigned Opcode) {
6577 switch (Opcode) {
6578 case VCVTPH2PSXZ128rm:
6579 case VCVTPH2PSXZ128rmb:
6580 case VCVTPH2PSXZ128rmbk:
6581 case VCVTPH2PSXZ128rmbkz:
6582 case VCVTPH2PSXZ128rmk:
6583 case VCVTPH2PSXZ128rmkz:
6584 case VCVTPH2PSXZ128rr:
6585 case VCVTPH2PSXZ128rrk:
6586 case VCVTPH2PSXZ128rrkz:
6587 case VCVTPH2PSXZ256rm:
6588 case VCVTPH2PSXZ256rmb:
6589 case VCVTPH2PSXZ256rmbk:
6590 case VCVTPH2PSXZ256rmbkz:
6591 case VCVTPH2PSXZ256rmk:
6592 case VCVTPH2PSXZ256rmkz:
6593 case VCVTPH2PSXZ256rr:
6594 case VCVTPH2PSXZ256rrk:
6595 case VCVTPH2PSXZ256rrkz:
6596 case VCVTPH2PSXZrm:
6597 case VCVTPH2PSXZrmb:
6598 case VCVTPH2PSXZrmbk:
6599 case VCVTPH2PSXZrmbkz:
6600 case VCVTPH2PSXZrmk:
6601 case VCVTPH2PSXZrmkz:
6602 case VCVTPH2PSXZrr:
6603 case VCVTPH2PSXZrrb:
6604 case VCVTPH2PSXZrrbk:
6605 case VCVTPH2PSXZrrbkz:
6606 case VCVTPH2PSXZrrk:
6607 case VCVTPH2PSXZrrkz:
6608 return true;
6609 }
6610 return false;
6611}
6612
6613bool isVFMSUB231PH(unsigned Opcode) {
6614 switch (Opcode) {
6615 case VFMSUB231PHZ128m:
6616 case VFMSUB231PHZ128mb:
6617 case VFMSUB231PHZ128mbk:
6618 case VFMSUB231PHZ128mbkz:
6619 case VFMSUB231PHZ128mk:
6620 case VFMSUB231PHZ128mkz:
6621 case VFMSUB231PHZ128r:
6622 case VFMSUB231PHZ128rk:
6623 case VFMSUB231PHZ128rkz:
6624 case VFMSUB231PHZ256m:
6625 case VFMSUB231PHZ256mb:
6626 case VFMSUB231PHZ256mbk:
6627 case VFMSUB231PHZ256mbkz:
6628 case VFMSUB231PHZ256mk:
6629 case VFMSUB231PHZ256mkz:
6630 case VFMSUB231PHZ256r:
6631 case VFMSUB231PHZ256rk:
6632 case VFMSUB231PHZ256rkz:
6633 case VFMSUB231PHZm:
6634 case VFMSUB231PHZmb:
6635 case VFMSUB231PHZmbk:
6636 case VFMSUB231PHZmbkz:
6637 case VFMSUB231PHZmk:
6638 case VFMSUB231PHZmkz:
6639 case VFMSUB231PHZr:
6640 case VFMSUB231PHZrb:
6641 case VFMSUB231PHZrbk:
6642 case VFMSUB231PHZrbkz:
6643 case VFMSUB231PHZrk:
6644 case VFMSUB231PHZrkz:
6645 return true;
6646 }
6647 return false;
6648}
6649
6650bool isVGATHERQPD(unsigned Opcode) {
6651 switch (Opcode) {
6652 case VGATHERQPDYrm:
6653 case VGATHERQPDZ128rm:
6654 case VGATHERQPDZ256rm:
6655 case VGATHERQPDZrm:
6656 case VGATHERQPDrm:
6657 return true;
6658 }
6659 return false;
6660}
6661
6662bool isKADDB(unsigned Opcode) {
6663 return Opcode == KADDBkk;
6664}
6665
6666bool isCVTPD2PI(unsigned Opcode) {
6667 switch (Opcode) {
6668 case MMX_CVTPD2PIrm:
6669 case MMX_CVTPD2PIrr:
6670 return true;
6671 }
6672 return false;
6673}
6674
6675bool isVFNMSUB213PH(unsigned Opcode) {
6676 switch (Opcode) {
6677 case VFNMSUB213PHZ128m:
6678 case VFNMSUB213PHZ128mb:
6679 case VFNMSUB213PHZ128mbk:
6680 case VFNMSUB213PHZ128mbkz:
6681 case VFNMSUB213PHZ128mk:
6682 case VFNMSUB213PHZ128mkz:
6683 case VFNMSUB213PHZ128r:
6684 case VFNMSUB213PHZ128rk:
6685 case VFNMSUB213PHZ128rkz:
6686 case VFNMSUB213PHZ256m:
6687 case VFNMSUB213PHZ256mb:
6688 case VFNMSUB213PHZ256mbk:
6689 case VFNMSUB213PHZ256mbkz:
6690 case VFNMSUB213PHZ256mk:
6691 case VFNMSUB213PHZ256mkz:
6692 case VFNMSUB213PHZ256r:
6693 case VFNMSUB213PHZ256rk:
6694 case VFNMSUB213PHZ256rkz:
6695 case VFNMSUB213PHZm:
6696 case VFNMSUB213PHZmb:
6697 case VFNMSUB213PHZmbk:
6698 case VFNMSUB213PHZmbkz:
6699 case VFNMSUB213PHZmk:
6700 case VFNMSUB213PHZmkz:
6701 case VFNMSUB213PHZr:
6702 case VFNMSUB213PHZrb:
6703 case VFNMSUB213PHZrbk:
6704 case VFNMSUB213PHZrbkz:
6705 case VFNMSUB213PHZrk:
6706 case VFNMSUB213PHZrkz:
6707 return true;
6708 }
6709 return false;
6710}
6711
6712bool isVPCMPESTRI(unsigned Opcode) {
6713 switch (Opcode) {
6714 case VPCMPESTRIrmi:
6715 case VPCMPESTRIrri:
6716 return true;
6717 }
6718 return false;
6719}
6720
6721bool isVPSHRDW(unsigned Opcode) {
6722 switch (Opcode) {
6723 case VPSHRDWZ128rmi:
6724 case VPSHRDWZ128rmik:
6725 case VPSHRDWZ128rmikz:
6726 case VPSHRDWZ128rri:
6727 case VPSHRDWZ128rrik:
6728 case VPSHRDWZ128rrikz:
6729 case VPSHRDWZ256rmi:
6730 case VPSHRDWZ256rmik:
6731 case VPSHRDWZ256rmikz:
6732 case VPSHRDWZ256rri:
6733 case VPSHRDWZ256rrik:
6734 case VPSHRDWZ256rrikz:
6735 case VPSHRDWZrmi:
6736 case VPSHRDWZrmik:
6737 case VPSHRDWZrmikz:
6738 case VPSHRDWZrri:
6739 case VPSHRDWZrrik:
6740 case VPSHRDWZrrikz:
6741 return true;
6742 }
6743 return false;
6744}
6745
6746bool isXORPS(unsigned Opcode) {
6747 switch (Opcode) {
6748 case XORPSrm:
6749 case XORPSrr:
6750 return true;
6751 }
6752 return false;
6753}
6754
6755bool isPOP2(unsigned Opcode) {
6756 return Opcode == POP2;
6757}
6758
6759bool isRDMSRLIST(unsigned Opcode) {
6760 return Opcode == RDMSRLIST;
6761}
6762
6763bool isVPDPBUSD(unsigned Opcode) {
6764 switch (Opcode) {
6765 case VPDPBUSDYrm:
6766 case VPDPBUSDYrr:
6767 case VPDPBUSDZ128rm:
6768 case VPDPBUSDZ128rmb:
6769 case VPDPBUSDZ128rmbk:
6770 case VPDPBUSDZ128rmbkz:
6771 case VPDPBUSDZ128rmk:
6772 case VPDPBUSDZ128rmkz:
6773 case VPDPBUSDZ128rr:
6774 case VPDPBUSDZ128rrk:
6775 case VPDPBUSDZ128rrkz:
6776 case VPDPBUSDZ256rm:
6777 case VPDPBUSDZ256rmb:
6778 case VPDPBUSDZ256rmbk:
6779 case VPDPBUSDZ256rmbkz:
6780 case VPDPBUSDZ256rmk:
6781 case VPDPBUSDZ256rmkz:
6782 case VPDPBUSDZ256rr:
6783 case VPDPBUSDZ256rrk:
6784 case VPDPBUSDZ256rrkz:
6785 case VPDPBUSDZrm:
6786 case VPDPBUSDZrmb:
6787 case VPDPBUSDZrmbk:
6788 case VPDPBUSDZrmbkz:
6789 case VPDPBUSDZrmk:
6790 case VPDPBUSDZrmkz:
6791 case VPDPBUSDZrr:
6792 case VPDPBUSDZrrk:
6793 case VPDPBUSDZrrkz:
6794 case VPDPBUSDrm:
6795 case VPDPBUSDrr:
6796 return true;
6797 }
6798 return false;
6799}
6800
6801bool isVCMPPH(unsigned Opcode) {
6802 switch (Opcode) {
6803 case VCMPPHZ128rmbi:
6804 case VCMPPHZ128rmbik:
6805 case VCMPPHZ128rmi:
6806 case VCMPPHZ128rmik:
6807 case VCMPPHZ128rri:
6808 case VCMPPHZ128rrik:
6809 case VCMPPHZ256rmbi:
6810 case VCMPPHZ256rmbik:
6811 case VCMPPHZ256rmi:
6812 case VCMPPHZ256rmik:
6813 case VCMPPHZ256rri:
6814 case VCMPPHZ256rrik:
6815 case VCMPPHZrmbi:
6816 case VCMPPHZrmbik:
6817 case VCMPPHZrmi:
6818 case VCMPPHZrmik:
6819 case VCMPPHZrri:
6820 case VCMPPHZrrib:
6821 case VCMPPHZrribk:
6822 case VCMPPHZrrik:
6823 return true;
6824 }
6825 return false;
6826}
6827
6828bool isVANDNPD(unsigned Opcode) {
6829 switch (Opcode) {
6830 case VANDNPDYrm:
6831 case VANDNPDYrr:
6832 case VANDNPDZ128rm:
6833 case VANDNPDZ128rmb:
6834 case VANDNPDZ128rmbk:
6835 case VANDNPDZ128rmbkz:
6836 case VANDNPDZ128rmk:
6837 case VANDNPDZ128rmkz:
6838 case VANDNPDZ128rr:
6839 case VANDNPDZ128rrk:
6840 case VANDNPDZ128rrkz:
6841 case VANDNPDZ256rm:
6842 case VANDNPDZ256rmb:
6843 case VANDNPDZ256rmbk:
6844 case VANDNPDZ256rmbkz:
6845 case VANDNPDZ256rmk:
6846 case VANDNPDZ256rmkz:
6847 case VANDNPDZ256rr:
6848 case VANDNPDZ256rrk:
6849 case VANDNPDZ256rrkz:
6850 case VANDNPDZrm:
6851 case VANDNPDZrmb:
6852 case VANDNPDZrmbk:
6853 case VANDNPDZrmbkz:
6854 case VANDNPDZrmk:
6855 case VANDNPDZrmkz:
6856 case VANDNPDZrr:
6857 case VANDNPDZrrk:
6858 case VANDNPDZrrkz:
6859 case VANDNPDrm:
6860 case VANDNPDrr:
6861 return true;
6862 }
6863 return false;
6864}
6865
6866bool isSUB(unsigned Opcode) {
6867 switch (Opcode) {
6868 case SUB16i16:
6869 case SUB16mi:
6870 case SUB16mi8:
6871 case SUB16mi8_EVEX:
6872 case SUB16mi8_ND:
6873 case SUB16mi8_NF:
6874 case SUB16mi8_NF_ND:
6875 case SUB16mi_EVEX:
6876 case SUB16mi_ND:
6877 case SUB16mi_NF:
6878 case SUB16mi_NF_ND:
6879 case SUB16mr:
6880 case SUB16mr_EVEX:
6881 case SUB16mr_ND:
6882 case SUB16mr_NF:
6883 case SUB16mr_NF_ND:
6884 case SUB16ri:
6885 case SUB16ri8:
6886 case SUB16ri8_EVEX:
6887 case SUB16ri8_ND:
6888 case SUB16ri8_NF:
6889 case SUB16ri8_NF_ND:
6890 case SUB16ri_EVEX:
6891 case SUB16ri_ND:
6892 case SUB16ri_NF:
6893 case SUB16ri_NF_ND:
6894 case SUB16rm:
6895 case SUB16rm_EVEX:
6896 case SUB16rm_ND:
6897 case SUB16rm_NF:
6898 case SUB16rm_NF_ND:
6899 case SUB16rr:
6900 case SUB16rr_EVEX:
6901 case SUB16rr_EVEX_REV:
6902 case SUB16rr_ND:
6903 case SUB16rr_ND_REV:
6904 case SUB16rr_NF:
6905 case SUB16rr_NF_ND:
6906 case SUB16rr_NF_ND_REV:
6907 case SUB16rr_NF_REV:
6908 case SUB16rr_REV:
6909 case SUB32i32:
6910 case SUB32mi:
6911 case SUB32mi8:
6912 case SUB32mi8_EVEX:
6913 case SUB32mi8_ND:
6914 case SUB32mi8_NF:
6915 case SUB32mi8_NF_ND:
6916 case SUB32mi_EVEX:
6917 case SUB32mi_ND:
6918 case SUB32mi_NF:
6919 case SUB32mi_NF_ND:
6920 case SUB32mr:
6921 case SUB32mr_EVEX:
6922 case SUB32mr_ND:
6923 case SUB32mr_NF:
6924 case SUB32mr_NF_ND:
6925 case SUB32ri:
6926 case SUB32ri8:
6927 case SUB32ri8_EVEX:
6928 case SUB32ri8_ND:
6929 case SUB32ri8_NF:
6930 case SUB32ri8_NF_ND:
6931 case SUB32ri_EVEX:
6932 case SUB32ri_ND:
6933 case SUB32ri_NF:
6934 case SUB32ri_NF_ND:
6935 case SUB32rm:
6936 case SUB32rm_EVEX:
6937 case SUB32rm_ND:
6938 case SUB32rm_NF:
6939 case SUB32rm_NF_ND:
6940 case SUB32rr:
6941 case SUB32rr_EVEX:
6942 case SUB32rr_EVEX_REV:
6943 case SUB32rr_ND:
6944 case SUB32rr_ND_REV:
6945 case SUB32rr_NF:
6946 case SUB32rr_NF_ND:
6947 case SUB32rr_NF_ND_REV:
6948 case SUB32rr_NF_REV:
6949 case SUB32rr_REV:
6950 case SUB64i32:
6951 case SUB64mi32:
6952 case SUB64mi32_EVEX:
6953 case SUB64mi32_ND:
6954 case SUB64mi32_NF:
6955 case SUB64mi32_NF_ND:
6956 case SUB64mi8:
6957 case SUB64mi8_EVEX:
6958 case SUB64mi8_ND:
6959 case SUB64mi8_NF:
6960 case SUB64mi8_NF_ND:
6961 case SUB64mr:
6962 case SUB64mr_EVEX:
6963 case SUB64mr_ND:
6964 case SUB64mr_NF:
6965 case SUB64mr_NF_ND:
6966 case SUB64ri32:
6967 case SUB64ri32_EVEX:
6968 case SUB64ri32_ND:
6969 case SUB64ri32_NF:
6970 case SUB64ri32_NF_ND:
6971 case SUB64ri8:
6972 case SUB64ri8_EVEX:
6973 case SUB64ri8_ND:
6974 case SUB64ri8_NF:
6975 case SUB64ri8_NF_ND:
6976 case SUB64rm:
6977 case SUB64rm_EVEX:
6978 case SUB64rm_ND:
6979 case SUB64rm_NF:
6980 case SUB64rm_NF_ND:
6981 case SUB64rr:
6982 case SUB64rr_EVEX:
6983 case SUB64rr_EVEX_REV:
6984 case SUB64rr_ND:
6985 case SUB64rr_ND_REV:
6986 case SUB64rr_NF:
6987 case SUB64rr_NF_ND:
6988 case SUB64rr_NF_ND_REV:
6989 case SUB64rr_NF_REV:
6990 case SUB64rr_REV:
6991 case SUB8i8:
6992 case SUB8mi:
6993 case SUB8mi8:
6994 case SUB8mi_EVEX:
6995 case SUB8mi_ND:
6996 case SUB8mi_NF:
6997 case SUB8mi_NF_ND:
6998 case SUB8mr:
6999 case SUB8mr_EVEX:
7000 case SUB8mr_ND:
7001 case SUB8mr_NF:
7002 case SUB8mr_NF_ND:
7003 case SUB8ri:
7004 case SUB8ri8:
7005 case SUB8ri_EVEX:
7006 case SUB8ri_ND:
7007 case SUB8ri_NF:
7008 case SUB8ri_NF_ND:
7009 case SUB8rm:
7010 case SUB8rm_EVEX:
7011 case SUB8rm_ND:
7012 case SUB8rm_NF:
7013 case SUB8rm_NF_ND:
7014 case SUB8rr:
7015 case SUB8rr_EVEX:
7016 case SUB8rr_EVEX_REV:
7017 case SUB8rr_ND:
7018 case SUB8rr_ND_REV:
7019 case SUB8rr_NF:
7020 case SUB8rr_NF_ND:
7021 case SUB8rr_NF_ND_REV:
7022 case SUB8rr_NF_REV:
7023 case SUB8rr_REV:
7024 return true;
7025 }
7026 return false;
7027}
7028
7029bool isVRSQRT28PD(unsigned Opcode) {
7030 switch (Opcode) {
7031 case VRSQRT28PDZm:
7032 case VRSQRT28PDZmb:
7033 case VRSQRT28PDZmbk:
7034 case VRSQRT28PDZmbkz:
7035 case VRSQRT28PDZmk:
7036 case VRSQRT28PDZmkz:
7037 case VRSQRT28PDZr:
7038 case VRSQRT28PDZrb:
7039 case VRSQRT28PDZrbk:
7040 case VRSQRT28PDZrbkz:
7041 case VRSQRT28PDZrk:
7042 case VRSQRT28PDZrkz:
7043 return true;
7044 }
7045 return false;
7046}
7047
7048bool isVFNMADD132PH(unsigned Opcode) {
7049 switch (Opcode) {
7050 case VFNMADD132PHZ128m:
7051 case VFNMADD132PHZ128mb:
7052 case VFNMADD132PHZ128mbk:
7053 case VFNMADD132PHZ128mbkz:
7054 case VFNMADD132PHZ128mk:
7055 case VFNMADD132PHZ128mkz:
7056 case VFNMADD132PHZ128r:
7057 case VFNMADD132PHZ128rk:
7058 case VFNMADD132PHZ128rkz:
7059 case VFNMADD132PHZ256m:
7060 case VFNMADD132PHZ256mb:
7061 case VFNMADD132PHZ256mbk:
7062 case VFNMADD132PHZ256mbkz:
7063 case VFNMADD132PHZ256mk:
7064 case VFNMADD132PHZ256mkz:
7065 case VFNMADD132PHZ256r:
7066 case VFNMADD132PHZ256rk:
7067 case VFNMADD132PHZ256rkz:
7068 case VFNMADD132PHZm:
7069 case VFNMADD132PHZmb:
7070 case VFNMADD132PHZmbk:
7071 case VFNMADD132PHZmbkz:
7072 case VFNMADD132PHZmk:
7073 case VFNMADD132PHZmkz:
7074 case VFNMADD132PHZr:
7075 case VFNMADD132PHZrb:
7076 case VFNMADD132PHZrbk:
7077 case VFNMADD132PHZrbkz:
7078 case VFNMADD132PHZrk:
7079 case VFNMADD132PHZrkz:
7080 return true;
7081 }
7082 return false;
7083}
7084
7085bool isVPMACSSWW(unsigned Opcode) {
7086 switch (Opcode) {
7087 case VPMACSSWWrm:
7088 case VPMACSSWWrr:
7089 return true;
7090 }
7091 return false;
7092}
7093
7094bool isXSTORE(unsigned Opcode) {
7095 return Opcode == XSTORE;
7096}
7097
7098bool isVPROTQ(unsigned Opcode) {
7099 switch (Opcode) {
7100 case VPROTQmi:
7101 case VPROTQmr:
7102 case VPROTQri:
7103 case VPROTQrm:
7104 case VPROTQrr:
7105 case VPROTQrr_REV:
7106 return true;
7107 }
7108 return false;
7109}
7110
7111bool isVPHADDBD(unsigned Opcode) {
7112 switch (Opcode) {
7113 case VPHADDBDrm:
7114 case VPHADDBDrr:
7115 return true;
7116 }
7117 return false;
7118}
7119
7120bool isVPMAXSB(unsigned Opcode) {
7121 switch (Opcode) {
7122 case VPMAXSBYrm:
7123 case VPMAXSBYrr:
7124 case VPMAXSBZ128rm:
7125 case VPMAXSBZ128rmk:
7126 case VPMAXSBZ128rmkz:
7127 case VPMAXSBZ128rr:
7128 case VPMAXSBZ128rrk:
7129 case VPMAXSBZ128rrkz:
7130 case VPMAXSBZ256rm:
7131 case VPMAXSBZ256rmk:
7132 case VPMAXSBZ256rmkz:
7133 case VPMAXSBZ256rr:
7134 case VPMAXSBZ256rrk:
7135 case VPMAXSBZ256rrkz:
7136 case VPMAXSBZrm:
7137 case VPMAXSBZrmk:
7138 case VPMAXSBZrmkz:
7139 case VPMAXSBZrr:
7140 case VPMAXSBZrrk:
7141 case VPMAXSBZrrkz:
7142 case VPMAXSBrm:
7143 case VPMAXSBrr:
7144 return true;
7145 }
7146 return false;
7147}
7148
7149bool isVMOVDQU8(unsigned Opcode) {
7150 switch (Opcode) {
7151 case VMOVDQU8Z128mr:
7152 case VMOVDQU8Z128mrk:
7153 case VMOVDQU8Z128rm:
7154 case VMOVDQU8Z128rmk:
7155 case VMOVDQU8Z128rmkz:
7156 case VMOVDQU8Z128rr:
7157 case VMOVDQU8Z128rr_REV:
7158 case VMOVDQU8Z128rrk:
7159 case VMOVDQU8Z128rrk_REV:
7160 case VMOVDQU8Z128rrkz:
7161 case VMOVDQU8Z128rrkz_REV:
7162 case VMOVDQU8Z256mr:
7163 case VMOVDQU8Z256mrk:
7164 case VMOVDQU8Z256rm:
7165 case VMOVDQU8Z256rmk:
7166 case VMOVDQU8Z256rmkz:
7167 case VMOVDQU8Z256rr:
7168 case VMOVDQU8Z256rr_REV:
7169 case VMOVDQU8Z256rrk:
7170 case VMOVDQU8Z256rrk_REV:
7171 case VMOVDQU8Z256rrkz:
7172 case VMOVDQU8Z256rrkz_REV:
7173 case VMOVDQU8Zmr:
7174 case VMOVDQU8Zmrk:
7175 case VMOVDQU8Zrm:
7176 case VMOVDQU8Zrmk:
7177 case VMOVDQU8Zrmkz:
7178 case VMOVDQU8Zrr:
7179 case VMOVDQU8Zrr_REV:
7180 case VMOVDQU8Zrrk:
7181 case VMOVDQU8Zrrk_REV:
7182 case VMOVDQU8Zrrkz:
7183 case VMOVDQU8Zrrkz_REV:
7184 return true;
7185 }
7186 return false;
7187}
7188
7189bool isVPMOVSXWD(unsigned Opcode) {
7190 switch (Opcode) {
7191 case VPMOVSXWDYrm:
7192 case VPMOVSXWDYrr:
7193 case VPMOVSXWDZ128rm:
7194 case VPMOVSXWDZ128rmk:
7195 case VPMOVSXWDZ128rmkz:
7196 case VPMOVSXWDZ128rr:
7197 case VPMOVSXWDZ128rrk:
7198 case VPMOVSXWDZ128rrkz:
7199 case VPMOVSXWDZ256rm:
7200 case VPMOVSXWDZ256rmk:
7201 case VPMOVSXWDZ256rmkz:
7202 case VPMOVSXWDZ256rr:
7203 case VPMOVSXWDZ256rrk:
7204 case VPMOVSXWDZ256rrkz:
7205 case VPMOVSXWDZrm:
7206 case VPMOVSXWDZrmk:
7207 case VPMOVSXWDZrmkz:
7208 case VPMOVSXWDZrr:
7209 case VPMOVSXWDZrrk:
7210 case VPMOVSXWDZrrkz:
7211 case VPMOVSXWDrm:
7212 case VPMOVSXWDrr:
7213 return true;
7214 }
7215 return false;
7216}
7217
7218bool isVMINMAXPD(unsigned Opcode) {
7219 switch (Opcode) {
7220 case VMINMAXPDZ128rmbi:
7221 case VMINMAXPDZ128rmbik:
7222 case VMINMAXPDZ128rmbikz:
7223 case VMINMAXPDZ128rmi:
7224 case VMINMAXPDZ128rmik:
7225 case VMINMAXPDZ128rmikz:
7226 case VMINMAXPDZ128rri:
7227 case VMINMAXPDZ128rrik:
7228 case VMINMAXPDZ128rrikz:
7229 case VMINMAXPDZ256rmbi:
7230 case VMINMAXPDZ256rmbik:
7231 case VMINMAXPDZ256rmbikz:
7232 case VMINMAXPDZ256rmi:
7233 case VMINMAXPDZ256rmik:
7234 case VMINMAXPDZ256rmikz:
7235 case VMINMAXPDZ256rri:
7236 case VMINMAXPDZ256rrik:
7237 case VMINMAXPDZ256rrikz:
7238 case VMINMAXPDZrmbi:
7239 case VMINMAXPDZrmbik:
7240 case VMINMAXPDZrmbikz:
7241 case VMINMAXPDZrmi:
7242 case VMINMAXPDZrmik:
7243 case VMINMAXPDZrmikz:
7244 case VMINMAXPDZrri:
7245 case VMINMAXPDZrrib:
7246 case VMINMAXPDZrribk:
7247 case VMINMAXPDZrribkz:
7248 case VMINMAXPDZrrik:
7249 case VMINMAXPDZrrikz:
7250 return true;
7251 }
7252 return false;
7253}
7254
7255bool isSHA256RNDS2(unsigned Opcode) {
7256 switch (Opcode) {
7257 case SHA256RNDS2rm:
7258 case SHA256RNDS2rr:
7259 return true;
7260 }
7261 return false;
7262}
7263
7264bool isKANDB(unsigned Opcode) {
7265 return Opcode == KANDBkk;
7266}
7267
7268bool isTPAUSE(unsigned Opcode) {
7269 return Opcode == TPAUSE;
7270}
7271
7272bool isPUSH(unsigned Opcode) {
7273 switch (Opcode) {
7274 case PUSH16i:
7275 case PUSH16i8:
7276 case PUSH16r:
7277 case PUSH16rmm:
7278 case PUSH16rmr:
7279 case PUSH32i:
7280 case PUSH32i8:
7281 case PUSH32r:
7282 case PUSH32rmm:
7283 case PUSH32rmr:
7284 case PUSH64i32:
7285 case PUSH64i8:
7286 case PUSH64r:
7287 case PUSH64rmm:
7288 case PUSH64rmr:
7289 case PUSHCS16:
7290 case PUSHCS32:
7291 case PUSHDS16:
7292 case PUSHDS32:
7293 case PUSHES16:
7294 case PUSHES32:
7295 case PUSHFS16:
7296 case PUSHFS32:
7297 case PUSHFS64:
7298 case PUSHGS16:
7299 case PUSHGS32:
7300 case PUSHGS64:
7301 case PUSHSS16:
7302 case PUSHSS32:
7303 return true;
7304 }
7305 return false;
7306}
7307
7308bool isVRNDSCALESS(unsigned Opcode) {
7309 switch (Opcode) {
7310 case VRNDSCALESSZrmi_Int:
7311 case VRNDSCALESSZrmik_Int:
7312 case VRNDSCALESSZrmikz_Int:
7313 case VRNDSCALESSZrri_Int:
7314 case VRNDSCALESSZrrib_Int:
7315 case VRNDSCALESSZrribk_Int:
7316 case VRNDSCALESSZrribkz_Int:
7317 case VRNDSCALESSZrrik_Int:
7318 case VRNDSCALESSZrrikz_Int:
7319 return true;
7320 }
7321 return false;
7322}
7323
7324bool isVRNDSCALEBF16(unsigned Opcode) {
7325 switch (Opcode) {
7326 case VRNDSCALEBF16Z128rmbi:
7327 case VRNDSCALEBF16Z128rmbik:
7328 case VRNDSCALEBF16Z128rmbikz:
7329 case VRNDSCALEBF16Z128rmi:
7330 case VRNDSCALEBF16Z128rmik:
7331 case VRNDSCALEBF16Z128rmikz:
7332 case VRNDSCALEBF16Z128rri:
7333 case VRNDSCALEBF16Z128rrik:
7334 case VRNDSCALEBF16Z128rrikz:
7335 case VRNDSCALEBF16Z256rmbi:
7336 case VRNDSCALEBF16Z256rmbik:
7337 case VRNDSCALEBF16Z256rmbikz:
7338 case VRNDSCALEBF16Z256rmi:
7339 case VRNDSCALEBF16Z256rmik:
7340 case VRNDSCALEBF16Z256rmikz:
7341 case VRNDSCALEBF16Z256rri:
7342 case VRNDSCALEBF16Z256rrik:
7343 case VRNDSCALEBF16Z256rrikz:
7344 case VRNDSCALEBF16Zrmbi:
7345 case VRNDSCALEBF16Zrmbik:
7346 case VRNDSCALEBF16Zrmbikz:
7347 case VRNDSCALEBF16Zrmi:
7348 case VRNDSCALEBF16Zrmik:
7349 case VRNDSCALEBF16Zrmikz:
7350 case VRNDSCALEBF16Zrri:
7351 case VRNDSCALEBF16Zrrik:
7352 case VRNDSCALEBF16Zrrikz:
7353 return true;
7354 }
7355 return false;
7356}
7357
7358bool isVPCMPISTRI(unsigned Opcode) {
7359 switch (Opcode) {
7360 case VPCMPISTRIrmi:
7361 case VPCMPISTRIrri:
7362 return true;
7363 }
7364 return false;
7365}
7366
7367bool isSTGI(unsigned Opcode) {
7368 return Opcode == STGI;
7369}
7370
7371bool isSBB(unsigned Opcode) {
7372 switch (Opcode) {
7373 case SBB16i16:
7374 case SBB16mi:
7375 case SBB16mi8:
7376 case SBB16mi8_EVEX:
7377 case SBB16mi8_ND:
7378 case SBB16mi_EVEX:
7379 case SBB16mi_ND:
7380 case SBB16mr:
7381 case SBB16mr_EVEX:
7382 case SBB16mr_ND:
7383 case SBB16ri:
7384 case SBB16ri8:
7385 case SBB16ri8_EVEX:
7386 case SBB16ri8_ND:
7387 case SBB16ri_EVEX:
7388 case SBB16ri_ND:
7389 case SBB16rm:
7390 case SBB16rm_EVEX:
7391 case SBB16rm_ND:
7392 case SBB16rr:
7393 case SBB16rr_EVEX:
7394 case SBB16rr_EVEX_REV:
7395 case SBB16rr_ND:
7396 case SBB16rr_ND_REV:
7397 case SBB16rr_REV:
7398 case SBB32i32:
7399 case SBB32mi:
7400 case SBB32mi8:
7401 case SBB32mi8_EVEX:
7402 case SBB32mi8_ND:
7403 case SBB32mi_EVEX:
7404 case SBB32mi_ND:
7405 case SBB32mr:
7406 case SBB32mr_EVEX:
7407 case SBB32mr_ND:
7408 case SBB32ri:
7409 case SBB32ri8:
7410 case SBB32ri8_EVEX:
7411 case SBB32ri8_ND:
7412 case SBB32ri_EVEX:
7413 case SBB32ri_ND:
7414 case SBB32rm:
7415 case SBB32rm_EVEX:
7416 case SBB32rm_ND:
7417 case SBB32rr:
7418 case SBB32rr_EVEX:
7419 case SBB32rr_EVEX_REV:
7420 case SBB32rr_ND:
7421 case SBB32rr_ND_REV:
7422 case SBB32rr_REV:
7423 case SBB64i32:
7424 case SBB64mi32:
7425 case SBB64mi32_EVEX:
7426 case SBB64mi32_ND:
7427 case SBB64mi8:
7428 case SBB64mi8_EVEX:
7429 case SBB64mi8_ND:
7430 case SBB64mr:
7431 case SBB64mr_EVEX:
7432 case SBB64mr_ND:
7433 case SBB64ri32:
7434 case SBB64ri32_EVEX:
7435 case SBB64ri32_ND:
7436 case SBB64ri8:
7437 case SBB64ri8_EVEX:
7438 case SBB64ri8_ND:
7439 case SBB64rm:
7440 case SBB64rm_EVEX:
7441 case SBB64rm_ND:
7442 case SBB64rr:
7443 case SBB64rr_EVEX:
7444 case SBB64rr_EVEX_REV:
7445 case SBB64rr_ND:
7446 case SBB64rr_ND_REV:
7447 case SBB64rr_REV:
7448 case SBB8i8:
7449 case SBB8mi:
7450 case SBB8mi8:
7451 case SBB8mi_EVEX:
7452 case SBB8mi_ND:
7453 case SBB8mr:
7454 case SBB8mr_EVEX:
7455 case SBB8mr_ND:
7456 case SBB8ri:
7457 case SBB8ri8:
7458 case SBB8ri_EVEX:
7459 case SBB8ri_ND:
7460 case SBB8rm:
7461 case SBB8rm_EVEX:
7462 case SBB8rm_ND:
7463 case SBB8rr:
7464 case SBB8rr_EVEX:
7465 case SBB8rr_EVEX_REV:
7466 case SBB8rr_ND:
7467 case SBB8rr_ND_REV:
7468 case SBB8rr_REV:
7469 return true;
7470 }
7471 return false;
7472}
7473
7474bool isBLCS(unsigned Opcode) {
7475 switch (Opcode) {
7476 case BLCS32rm:
7477 case BLCS32rr:
7478 case BLCS64rm:
7479 case BLCS64rr:
7480 return true;
7481 }
7482 return false;
7483}
7484
7485bool isVCVTSD2SH(unsigned Opcode) {
7486 switch (Opcode) {
7487 case VCVTSD2SHZrm_Int:
7488 case VCVTSD2SHZrmk_Int:
7489 case VCVTSD2SHZrmkz_Int:
7490 case VCVTSD2SHZrr_Int:
7491 case VCVTSD2SHZrrb_Int:
7492 case VCVTSD2SHZrrbk_Int:
7493 case VCVTSD2SHZrrbkz_Int:
7494 case VCVTSD2SHZrrk_Int:
7495 case VCVTSD2SHZrrkz_Int:
7496 return true;
7497 }
7498 return false;
7499}
7500
7501bool isVPERMW(unsigned Opcode) {
7502 switch (Opcode) {
7503 case VPERMWZ128rm:
7504 case VPERMWZ128rmk:
7505 case VPERMWZ128rmkz:
7506 case VPERMWZ128rr:
7507 case VPERMWZ128rrk:
7508 case VPERMWZ128rrkz:
7509 case VPERMWZ256rm:
7510 case VPERMWZ256rmk:
7511 case VPERMWZ256rmkz:
7512 case VPERMWZ256rr:
7513 case VPERMWZ256rrk:
7514 case VPERMWZ256rrkz:
7515 case VPERMWZrm:
7516 case VPERMWZrmk:
7517 case VPERMWZrmkz:
7518 case VPERMWZrr:
7519 case VPERMWZrrk:
7520 case VPERMWZrrkz:
7521 return true;
7522 }
7523 return false;
7524}
7525
7526bool isXRESLDTRK(unsigned Opcode) {
7527 return Opcode == XRESLDTRK;
7528}
7529
7530bool isAESENC256KL(unsigned Opcode) {
7531 return Opcode == AESENC256KL;
7532}
7533
7534bool isVGATHERDPD(unsigned Opcode) {
7535 switch (Opcode) {
7536 case VGATHERDPDYrm:
7537 case VGATHERDPDZ128rm:
7538 case VGATHERDPDZ256rm:
7539 case VGATHERDPDZrm:
7540 case VGATHERDPDrm:
7541 return true;
7542 }
7543 return false;
7544}
7545
7546bool isHRESET(unsigned Opcode) {
7547 return Opcode == HRESET;
7548}
7549
7550bool isVFMSUBADD231PD(unsigned Opcode) {
7551 switch (Opcode) {
7552 case VFMSUBADD231PDYm:
7553 case VFMSUBADD231PDYr:
7554 case VFMSUBADD231PDZ128m:
7555 case VFMSUBADD231PDZ128mb:
7556 case VFMSUBADD231PDZ128mbk:
7557 case VFMSUBADD231PDZ128mbkz:
7558 case VFMSUBADD231PDZ128mk:
7559 case VFMSUBADD231PDZ128mkz:
7560 case VFMSUBADD231PDZ128r:
7561 case VFMSUBADD231PDZ128rk:
7562 case VFMSUBADD231PDZ128rkz:
7563 case VFMSUBADD231PDZ256m:
7564 case VFMSUBADD231PDZ256mb:
7565 case VFMSUBADD231PDZ256mbk:
7566 case VFMSUBADD231PDZ256mbkz:
7567 case VFMSUBADD231PDZ256mk:
7568 case VFMSUBADD231PDZ256mkz:
7569 case VFMSUBADD231PDZ256r:
7570 case VFMSUBADD231PDZ256rk:
7571 case VFMSUBADD231PDZ256rkz:
7572 case VFMSUBADD231PDZm:
7573 case VFMSUBADD231PDZmb:
7574 case VFMSUBADD231PDZmbk:
7575 case VFMSUBADD231PDZmbkz:
7576 case VFMSUBADD231PDZmk:
7577 case VFMSUBADD231PDZmkz:
7578 case VFMSUBADD231PDZr:
7579 case VFMSUBADD231PDZrb:
7580 case VFMSUBADD231PDZrbk:
7581 case VFMSUBADD231PDZrbkz:
7582 case VFMSUBADD231PDZrk:
7583 case VFMSUBADD231PDZrkz:
7584 case VFMSUBADD231PDm:
7585 case VFMSUBADD231PDr:
7586 return true;
7587 }
7588 return false;
7589}
7590
7591bool isVFRCZSS(unsigned Opcode) {
7592 switch (Opcode) {
7593 case VFRCZSSrm:
7594 case VFRCZSSrr:
7595 return true;
7596 }
7597 return false;
7598}
7599
7600bool isMINPS(unsigned Opcode) {
7601 switch (Opcode) {
7602 case MINPSrm:
7603 case MINPSrr:
7604 return true;
7605 }
7606 return false;
7607}
7608
7609bool isFPREM1(unsigned Opcode) {
7610 return Opcode == FPREM1;
7611}
7612
7613bool isVPCMPUB(unsigned Opcode) {
7614 switch (Opcode) {
7615 case VPCMPUBZ128rmi:
7616 case VPCMPUBZ128rmik:
7617 case VPCMPUBZ128rri:
7618 case VPCMPUBZ128rrik:
7619 case VPCMPUBZ256rmi:
7620 case VPCMPUBZ256rmik:
7621 case VPCMPUBZ256rri:
7622 case VPCMPUBZ256rrik:
7623 case VPCMPUBZrmi:
7624 case VPCMPUBZrmik:
7625 case VPCMPUBZrri:
7626 case VPCMPUBZrrik:
7627 return true;
7628 }
7629 return false;
7630}
7631
7632bool isVSQRTPD(unsigned Opcode) {
7633 switch (Opcode) {
7634 case VSQRTPDYm:
7635 case VSQRTPDYr:
7636 case VSQRTPDZ128m:
7637 case VSQRTPDZ128mb:
7638 case VSQRTPDZ128mbk:
7639 case VSQRTPDZ128mbkz:
7640 case VSQRTPDZ128mk:
7641 case VSQRTPDZ128mkz:
7642 case VSQRTPDZ128r:
7643 case VSQRTPDZ128rk:
7644 case VSQRTPDZ128rkz:
7645 case VSQRTPDZ256m:
7646 case VSQRTPDZ256mb:
7647 case VSQRTPDZ256mbk:
7648 case VSQRTPDZ256mbkz:
7649 case VSQRTPDZ256mk:
7650 case VSQRTPDZ256mkz:
7651 case VSQRTPDZ256r:
7652 case VSQRTPDZ256rk:
7653 case VSQRTPDZ256rkz:
7654 case VSQRTPDZm:
7655 case VSQRTPDZmb:
7656 case VSQRTPDZmbk:
7657 case VSQRTPDZmbkz:
7658 case VSQRTPDZmk:
7659 case VSQRTPDZmkz:
7660 case VSQRTPDZr:
7661 case VSQRTPDZrb:
7662 case VSQRTPDZrbk:
7663 case VSQRTPDZrbkz:
7664 case VSQRTPDZrk:
7665 case VSQRTPDZrkz:
7666 case VSQRTPDm:
7667 case VSQRTPDr:
7668 return true;
7669 }
7670 return false;
7671}
7672
7673bool isVFRCZPS(unsigned Opcode) {
7674 switch (Opcode) {
7675 case VFRCZPSYrm:
7676 case VFRCZPSYrr:
7677 case VFRCZPSrm:
7678 case VFRCZPSrr:
7679 return true;
7680 }
7681 return false;
7682}
7683
7684bool isVFNMADD213SS(unsigned Opcode) {
7685 switch (Opcode) {
7686 case VFNMADD213SSZm_Int:
7687 case VFNMADD213SSZmk_Int:
7688 case VFNMADD213SSZmkz_Int:
7689 case VFNMADD213SSZr_Int:
7690 case VFNMADD213SSZrb_Int:
7691 case VFNMADD213SSZrbk_Int:
7692 case VFNMADD213SSZrbkz_Int:
7693 case VFNMADD213SSZrk_Int:
7694 case VFNMADD213SSZrkz_Int:
7695 case VFNMADD213SSm_Int:
7696 case VFNMADD213SSr_Int:
7697 return true;
7698 }
7699 return false;
7700}
7701
7702bool isVPSHRDVQ(unsigned Opcode) {
7703 switch (Opcode) {
7704 case VPSHRDVQZ128m:
7705 case VPSHRDVQZ128mb:
7706 case VPSHRDVQZ128mbk:
7707 case VPSHRDVQZ128mbkz:
7708 case VPSHRDVQZ128mk:
7709 case VPSHRDVQZ128mkz:
7710 case VPSHRDVQZ128r:
7711 case VPSHRDVQZ128rk:
7712 case VPSHRDVQZ128rkz:
7713 case VPSHRDVQZ256m:
7714 case VPSHRDVQZ256mb:
7715 case VPSHRDVQZ256mbk:
7716 case VPSHRDVQZ256mbkz:
7717 case VPSHRDVQZ256mk:
7718 case VPSHRDVQZ256mkz:
7719 case VPSHRDVQZ256r:
7720 case VPSHRDVQZ256rk:
7721 case VPSHRDVQZ256rkz:
7722 case VPSHRDVQZm:
7723 case VPSHRDVQZmb:
7724 case VPSHRDVQZmbk:
7725 case VPSHRDVQZmbkz:
7726 case VPSHRDVQZmk:
7727 case VPSHRDVQZmkz:
7728 case VPSHRDVQZr:
7729 case VPSHRDVQZrk:
7730 case VPSHRDVQZrkz:
7731 return true;
7732 }
7733 return false;
7734}
7735
7736bool isVPMOVDW(unsigned Opcode) {
7737 switch (Opcode) {
7738 case VPMOVDWZ128mr:
7739 case VPMOVDWZ128mrk:
7740 case VPMOVDWZ128rr:
7741 case VPMOVDWZ128rrk:
7742 case VPMOVDWZ128rrkz:
7743 case VPMOVDWZ256mr:
7744 case VPMOVDWZ256mrk:
7745 case VPMOVDWZ256rr:
7746 case VPMOVDWZ256rrk:
7747 case VPMOVDWZ256rrkz:
7748 case VPMOVDWZmr:
7749 case VPMOVDWZmrk:
7750 case VPMOVDWZrr:
7751 case VPMOVDWZrrk:
7752 case VPMOVDWZrrkz:
7753 return true;
7754 }
7755 return false;
7756}
7757
7758bool isVCVTPH2HF8S(unsigned Opcode) {
7759 switch (Opcode) {
7760 case VCVTPH2HF8SZ128rm:
7761 case VCVTPH2HF8SZ128rmb:
7762 case VCVTPH2HF8SZ128rmbk:
7763 case VCVTPH2HF8SZ128rmbkz:
7764 case VCVTPH2HF8SZ128rmk:
7765 case VCVTPH2HF8SZ128rmkz:
7766 case VCVTPH2HF8SZ128rr:
7767 case VCVTPH2HF8SZ128rrk:
7768 case VCVTPH2HF8SZ128rrkz:
7769 case VCVTPH2HF8SZ256rm:
7770 case VCVTPH2HF8SZ256rmb:
7771 case VCVTPH2HF8SZ256rmbk:
7772 case VCVTPH2HF8SZ256rmbkz:
7773 case VCVTPH2HF8SZ256rmk:
7774 case VCVTPH2HF8SZ256rmkz:
7775 case VCVTPH2HF8SZ256rr:
7776 case VCVTPH2HF8SZ256rrk:
7777 case VCVTPH2HF8SZ256rrkz:
7778 case VCVTPH2HF8SZrm:
7779 case VCVTPH2HF8SZrmb:
7780 case VCVTPH2HF8SZrmbk:
7781 case VCVTPH2HF8SZrmbkz:
7782 case VCVTPH2HF8SZrmk:
7783 case VCVTPH2HF8SZrmkz:
7784 case VCVTPH2HF8SZrr:
7785 case VCVTPH2HF8SZrrk:
7786 case VCVTPH2HF8SZrrkz:
7787 return true;
7788 }
7789 return false;
7790}
7791
7792bool isVBROADCASTSD(unsigned Opcode) {
7793 switch (Opcode) {
7794 case VBROADCASTSDYrm:
7795 case VBROADCASTSDYrr:
7796 case VBROADCASTSDZ256rm:
7797 case VBROADCASTSDZ256rmk:
7798 case VBROADCASTSDZ256rmkz:
7799 case VBROADCASTSDZ256rr:
7800 case VBROADCASTSDZ256rrk:
7801 case VBROADCASTSDZ256rrkz:
7802 case VBROADCASTSDZrm:
7803 case VBROADCASTSDZrmk:
7804 case VBROADCASTSDZrmkz:
7805 case VBROADCASTSDZrr:
7806 case VBROADCASTSDZrrk:
7807 case VBROADCASTSDZrrkz:
7808 return true;
7809 }
7810 return false;
7811}
7812
7813bool isVSHUFPD(unsigned Opcode) {
7814 switch (Opcode) {
7815 case VSHUFPDYrmi:
7816 case VSHUFPDYrri:
7817 case VSHUFPDZ128rmbi:
7818 case VSHUFPDZ128rmbik:
7819 case VSHUFPDZ128rmbikz:
7820 case VSHUFPDZ128rmi:
7821 case VSHUFPDZ128rmik:
7822 case VSHUFPDZ128rmikz:
7823 case VSHUFPDZ128rri:
7824 case VSHUFPDZ128rrik:
7825 case VSHUFPDZ128rrikz:
7826 case VSHUFPDZ256rmbi:
7827 case VSHUFPDZ256rmbik:
7828 case VSHUFPDZ256rmbikz:
7829 case VSHUFPDZ256rmi:
7830 case VSHUFPDZ256rmik:
7831 case VSHUFPDZ256rmikz:
7832 case VSHUFPDZ256rri:
7833 case VSHUFPDZ256rrik:
7834 case VSHUFPDZ256rrikz:
7835 case VSHUFPDZrmbi:
7836 case VSHUFPDZrmbik:
7837 case VSHUFPDZrmbikz:
7838 case VSHUFPDZrmi:
7839 case VSHUFPDZrmik:
7840 case VSHUFPDZrmikz:
7841 case VSHUFPDZrri:
7842 case VSHUFPDZrrik:
7843 case VSHUFPDZrrikz:
7844 case VSHUFPDrmi:
7845 case VSHUFPDrri:
7846 return true;
7847 }
7848 return false;
7849}
7850
7851bool isVPSUBSW(unsigned Opcode) {
7852 switch (Opcode) {
7853 case VPSUBSWYrm:
7854 case VPSUBSWYrr:
7855 case VPSUBSWZ128rm:
7856 case VPSUBSWZ128rmk:
7857 case VPSUBSWZ128rmkz:
7858 case VPSUBSWZ128rr:
7859 case VPSUBSWZ128rrk:
7860 case VPSUBSWZ128rrkz:
7861 case VPSUBSWZ256rm:
7862 case VPSUBSWZ256rmk:
7863 case VPSUBSWZ256rmkz:
7864 case VPSUBSWZ256rr:
7865 case VPSUBSWZ256rrk:
7866 case VPSUBSWZ256rrkz:
7867 case VPSUBSWZrm:
7868 case VPSUBSWZrmk:
7869 case VPSUBSWZrmkz:
7870 case VPSUBSWZrr:
7871 case VPSUBSWZrrk:
7872 case VPSUBSWZrrkz:
7873 case VPSUBSWrm:
7874 case VPSUBSWrr:
7875 return true;
7876 }
7877 return false;
7878}
7879
7880bool isKUNPCKBW(unsigned Opcode) {
7881 return Opcode == KUNPCKBWkk;
7882}
7883
7884bool isVPBLENDD(unsigned Opcode) {
7885 switch (Opcode) {
7886 case VPBLENDDYrmi:
7887 case VPBLENDDYrri:
7888 case VPBLENDDrmi:
7889 case VPBLENDDrri:
7890 return true;
7891 }
7892 return false;
7893}
7894
7895bool isUNPCKHPD(unsigned Opcode) {
7896 switch (Opcode) {
7897 case UNPCKHPDrm:
7898 case UNPCKHPDrr:
7899 return true;
7900 }
7901 return false;
7902}
7903
7904bool isVFNMADD231SD(unsigned Opcode) {
7905 switch (Opcode) {
7906 case VFNMADD231SDZm_Int:
7907 case VFNMADD231SDZmk_Int:
7908 case VFNMADD231SDZmkz_Int:
7909 case VFNMADD231SDZr_Int:
7910 case VFNMADD231SDZrb_Int:
7911 case VFNMADD231SDZrbk_Int:
7912 case VFNMADD231SDZrbkz_Int:
7913 case VFNMADD231SDZrk_Int:
7914 case VFNMADD231SDZrkz_Int:
7915 case VFNMADD231SDm_Int:
7916 case VFNMADD231SDr_Int:
7917 return true;
7918 }
7919 return false;
7920}
7921
7922bool isVPBROADCASTMW2D(unsigned Opcode) {
7923 switch (Opcode) {
7924 case VPBROADCASTMW2DZ128rr:
7925 case VPBROADCASTMW2DZ256rr:
7926 case VPBROADCASTMW2DZrr:
7927 return true;
7928 }
7929 return false;
7930}
7931
7932bool isVPMULTISHIFTQB(unsigned Opcode) {
7933 switch (Opcode) {
7934 case VPMULTISHIFTQBZ128rm:
7935 case VPMULTISHIFTQBZ128rmb:
7936 case VPMULTISHIFTQBZ128rmbk:
7937 case VPMULTISHIFTQBZ128rmbkz:
7938 case VPMULTISHIFTQBZ128rmk:
7939 case VPMULTISHIFTQBZ128rmkz:
7940 case VPMULTISHIFTQBZ128rr:
7941 case VPMULTISHIFTQBZ128rrk:
7942 case VPMULTISHIFTQBZ128rrkz:
7943 case VPMULTISHIFTQBZ256rm:
7944 case VPMULTISHIFTQBZ256rmb:
7945 case VPMULTISHIFTQBZ256rmbk:
7946 case VPMULTISHIFTQBZ256rmbkz:
7947 case VPMULTISHIFTQBZ256rmk:
7948 case VPMULTISHIFTQBZ256rmkz:
7949 case VPMULTISHIFTQBZ256rr:
7950 case VPMULTISHIFTQBZ256rrk:
7951 case VPMULTISHIFTQBZ256rrkz:
7952 case VPMULTISHIFTQBZrm:
7953 case VPMULTISHIFTQBZrmb:
7954 case VPMULTISHIFTQBZrmbk:
7955 case VPMULTISHIFTQBZrmbkz:
7956 case VPMULTISHIFTQBZrmk:
7957 case VPMULTISHIFTQBZrmkz:
7958 case VPMULTISHIFTQBZrr:
7959 case VPMULTISHIFTQBZrrk:
7960 case VPMULTISHIFTQBZrrkz:
7961 return true;
7962 }
7963 return false;
7964}
7965
7966bool isVP2INTERSECTQ(unsigned Opcode) {
7967 switch (Opcode) {
7968 case VP2INTERSECTQZ128rm:
7969 case VP2INTERSECTQZ128rmb:
7970 case VP2INTERSECTQZ128rr:
7971 case VP2INTERSECTQZ256rm:
7972 case VP2INTERSECTQZ256rmb:
7973 case VP2INTERSECTQZ256rr:
7974 case VP2INTERSECTQZrm:
7975 case VP2INTERSECTQZrmb:
7976 case VP2INTERSECTQZrr:
7977 return true;
7978 }
7979 return false;
7980}
7981
7982bool isVFNMSUB132BF16(unsigned Opcode) {
7983 switch (Opcode) {
7984 case VFNMSUB132BF16Z128m:
7985 case VFNMSUB132BF16Z128mb:
7986 case VFNMSUB132BF16Z128mbk:
7987 case VFNMSUB132BF16Z128mbkz:
7988 case VFNMSUB132BF16Z128mk:
7989 case VFNMSUB132BF16Z128mkz:
7990 case VFNMSUB132BF16Z128r:
7991 case VFNMSUB132BF16Z128rk:
7992 case VFNMSUB132BF16Z128rkz:
7993 case VFNMSUB132BF16Z256m:
7994 case VFNMSUB132BF16Z256mb:
7995 case VFNMSUB132BF16Z256mbk:
7996 case VFNMSUB132BF16Z256mbkz:
7997 case VFNMSUB132BF16Z256mk:
7998 case VFNMSUB132BF16Z256mkz:
7999 case VFNMSUB132BF16Z256r:
8000 case VFNMSUB132BF16Z256rk:
8001 case VFNMSUB132BF16Z256rkz:
8002 case VFNMSUB132BF16Zm:
8003 case VFNMSUB132BF16Zmb:
8004 case VFNMSUB132BF16Zmbk:
8005 case VFNMSUB132BF16Zmbkz:
8006 case VFNMSUB132BF16Zmk:
8007 case VFNMSUB132BF16Zmkz:
8008 case VFNMSUB132BF16Zr:
8009 case VFNMSUB132BF16Zrk:
8010 case VFNMSUB132BF16Zrkz:
8011 return true;
8012 }
8013 return false;
8014}
8015
8016bool isVFMADD213BF16(unsigned Opcode) {
8017 switch (Opcode) {
8018 case VFMADD213BF16Z128m:
8019 case VFMADD213BF16Z128mb:
8020 case VFMADD213BF16Z128mbk:
8021 case VFMADD213BF16Z128mbkz:
8022 case VFMADD213BF16Z128mk:
8023 case VFMADD213BF16Z128mkz:
8024 case VFMADD213BF16Z128r:
8025 case VFMADD213BF16Z128rk:
8026 case VFMADD213BF16Z128rkz:
8027 case VFMADD213BF16Z256m:
8028 case VFMADD213BF16Z256mb:
8029 case VFMADD213BF16Z256mbk:
8030 case VFMADD213BF16Z256mbkz:
8031 case VFMADD213BF16Z256mk:
8032 case VFMADD213BF16Z256mkz:
8033 case VFMADD213BF16Z256r:
8034 case VFMADD213BF16Z256rk:
8035 case VFMADD213BF16Z256rkz:
8036 case VFMADD213BF16Zm:
8037 case VFMADD213BF16Zmb:
8038 case VFMADD213BF16Zmbk:
8039 case VFMADD213BF16Zmbkz:
8040 case VFMADD213BF16Zmk:
8041 case VFMADD213BF16Zmkz:
8042 case VFMADD213BF16Zr:
8043 case VFMADD213BF16Zrk:
8044 case VFMADD213BF16Zrkz:
8045 return true;
8046 }
8047 return false;
8048}
8049
8050bool isVPUNPCKHWD(unsigned Opcode) {
8051 switch (Opcode) {
8052 case VPUNPCKHWDYrm:
8053 case VPUNPCKHWDYrr:
8054 case VPUNPCKHWDZ128rm:
8055 case VPUNPCKHWDZ128rmk:
8056 case VPUNPCKHWDZ128rmkz:
8057 case VPUNPCKHWDZ128rr:
8058 case VPUNPCKHWDZ128rrk:
8059 case VPUNPCKHWDZ128rrkz:
8060 case VPUNPCKHWDZ256rm:
8061 case VPUNPCKHWDZ256rmk:
8062 case VPUNPCKHWDZ256rmkz:
8063 case VPUNPCKHWDZ256rr:
8064 case VPUNPCKHWDZ256rrk:
8065 case VPUNPCKHWDZ256rrkz:
8066 case VPUNPCKHWDZrm:
8067 case VPUNPCKHWDZrmk:
8068 case VPUNPCKHWDZrmkz:
8069 case VPUNPCKHWDZrr:
8070 case VPUNPCKHWDZrrk:
8071 case VPUNPCKHWDZrrkz:
8072 case VPUNPCKHWDrm:
8073 case VPUNPCKHWDrr:
8074 return true;
8075 }
8076 return false;
8077}
8078
8079bool isVPERM2F128(unsigned Opcode) {
8080 switch (Opcode) {
8081 case VPERM2F128rmi:
8082 case VPERM2F128rri:
8083 return true;
8084 }
8085 return false;
8086}
8087
8088bool isINSD(unsigned Opcode) {
8089 return Opcode == INSL;
8090}
8091
8092bool isLFS(unsigned Opcode) {
8093 switch (Opcode) {
8094 case LFS16rm:
8095 case LFS32rm:
8096 case LFS64rm:
8097 return true;
8098 }
8099 return false;
8100}
8101
8102bool isFMULP(unsigned Opcode) {
8103 return Opcode == MUL_FPrST0;
8104}
8105
8106bool isCWD(unsigned Opcode) {
8107 return Opcode == CWD;
8108}
8109
8110bool isVDIVSS(unsigned Opcode) {
8111 switch (Opcode) {
8112 case VDIVSSZrm_Int:
8113 case VDIVSSZrmk_Int:
8114 case VDIVSSZrmkz_Int:
8115 case VDIVSSZrr_Int:
8116 case VDIVSSZrrb_Int:
8117 case VDIVSSZrrbk_Int:
8118 case VDIVSSZrrbkz_Int:
8119 case VDIVSSZrrk_Int:
8120 case VDIVSSZrrkz_Int:
8121 case VDIVSSrm_Int:
8122 case VDIVSSrr_Int:
8123 return true;
8124 }
8125 return false;
8126}
8127
8128bool isVPSRLQ(unsigned Opcode) {
8129 switch (Opcode) {
8130 case VPSRLQYri:
8131 case VPSRLQYrm:
8132 case VPSRLQYrr:
8133 case VPSRLQZ128mbi:
8134 case VPSRLQZ128mbik:
8135 case VPSRLQZ128mbikz:
8136 case VPSRLQZ128mi:
8137 case VPSRLQZ128mik:
8138 case VPSRLQZ128mikz:
8139 case VPSRLQZ128ri:
8140 case VPSRLQZ128rik:
8141 case VPSRLQZ128rikz:
8142 case VPSRLQZ128rm:
8143 case VPSRLQZ128rmk:
8144 case VPSRLQZ128rmkz:
8145 case VPSRLQZ128rr:
8146 case VPSRLQZ128rrk:
8147 case VPSRLQZ128rrkz:
8148 case VPSRLQZ256mbi:
8149 case VPSRLQZ256mbik:
8150 case VPSRLQZ256mbikz:
8151 case VPSRLQZ256mi:
8152 case VPSRLQZ256mik:
8153 case VPSRLQZ256mikz:
8154 case VPSRLQZ256ri:
8155 case VPSRLQZ256rik:
8156 case VPSRLQZ256rikz:
8157 case VPSRLQZ256rm:
8158 case VPSRLQZ256rmk:
8159 case VPSRLQZ256rmkz:
8160 case VPSRLQZ256rr:
8161 case VPSRLQZ256rrk:
8162 case VPSRLQZ256rrkz:
8163 case VPSRLQZmbi:
8164 case VPSRLQZmbik:
8165 case VPSRLQZmbikz:
8166 case VPSRLQZmi:
8167 case VPSRLQZmik:
8168 case VPSRLQZmikz:
8169 case VPSRLQZri:
8170 case VPSRLQZrik:
8171 case VPSRLQZrikz:
8172 case VPSRLQZrm:
8173 case VPSRLQZrmk:
8174 case VPSRLQZrmkz:
8175 case VPSRLQZrr:
8176 case VPSRLQZrrk:
8177 case VPSRLQZrrkz:
8178 case VPSRLQri:
8179 case VPSRLQrm:
8180 case VPSRLQrr:
8181 return true;
8182 }
8183 return false;
8184}
8185
8186bool isFSQRT(unsigned Opcode) {
8187 return Opcode == SQRT_F;
8188}
8189
8190bool isJRCXZ(unsigned Opcode) {
8191 return Opcode == JRCXZ;
8192}
8193
8194bool isVPMOVMSKB(unsigned Opcode) {
8195 switch (Opcode) {
8196 case VPMOVMSKBYrr:
8197 case VPMOVMSKBrr:
8198 return true;
8199 }
8200 return false;
8201}
8202
8203bool isAESDEC256KL(unsigned Opcode) {
8204 return Opcode == AESDEC256KL;
8205}
8206
8207bool isFLDENV(unsigned Opcode) {
8208 return Opcode == FLDENVm;
8209}
8210
8211bool isVPHSUBWD(unsigned Opcode) {
8212 switch (Opcode) {
8213 case VPHSUBWDrm:
8214 case VPHSUBWDrr:
8215 return true;
8216 }
8217 return false;
8218}
8219
8220bool isWBNOINVD(unsigned Opcode) {
8221 return Opcode == WBNOINVD;
8222}
8223
8224bool isVEXPANDPD(unsigned Opcode) {
8225 switch (Opcode) {
8226 case VEXPANDPDZ128rm:
8227 case VEXPANDPDZ128rmk:
8228 case VEXPANDPDZ128rmkz:
8229 case VEXPANDPDZ128rr:
8230 case VEXPANDPDZ128rrk:
8231 case VEXPANDPDZ128rrkz:
8232 case VEXPANDPDZ256rm:
8233 case VEXPANDPDZ256rmk:
8234 case VEXPANDPDZ256rmkz:
8235 case VEXPANDPDZ256rr:
8236 case VEXPANDPDZ256rrk:
8237 case VEXPANDPDZ256rrkz:
8238 case VEXPANDPDZrm:
8239 case VEXPANDPDZrmk:
8240 case VEXPANDPDZrmkz:
8241 case VEXPANDPDZrr:
8242 case VEXPANDPDZrrk:
8243 case VEXPANDPDZrrkz:
8244 return true;
8245 }
8246 return false;
8247}
8248
8249bool isFYL2XP1(unsigned Opcode) {
8250 return Opcode == FYL2XP1;
8251}
8252
8253bool isPREFETCHT2(unsigned Opcode) {
8254 return Opcode == PREFETCHT2;
8255}
8256
8257bool isVPDPBSUDS(unsigned Opcode) {
8258 switch (Opcode) {
8259 case VPDPBSUDSYrm:
8260 case VPDPBSUDSYrr:
8261 case VPDPBSUDSZ128rm:
8262 case VPDPBSUDSZ128rmb:
8263 case VPDPBSUDSZ128rmbk:
8264 case VPDPBSUDSZ128rmbkz:
8265 case VPDPBSUDSZ128rmk:
8266 case VPDPBSUDSZ128rmkz:
8267 case VPDPBSUDSZ128rr:
8268 case VPDPBSUDSZ128rrk:
8269 case VPDPBSUDSZ128rrkz:
8270 case VPDPBSUDSZ256rm:
8271 case VPDPBSUDSZ256rmb:
8272 case VPDPBSUDSZ256rmbk:
8273 case VPDPBSUDSZ256rmbkz:
8274 case VPDPBSUDSZ256rmk:
8275 case VPDPBSUDSZ256rmkz:
8276 case VPDPBSUDSZ256rr:
8277 case VPDPBSUDSZ256rrk:
8278 case VPDPBSUDSZ256rrkz:
8279 case VPDPBSUDSZrm:
8280 case VPDPBSUDSZrmb:
8281 case VPDPBSUDSZrmbk:
8282 case VPDPBSUDSZrmbkz:
8283 case VPDPBSUDSZrmk:
8284 case VPDPBSUDSZrmkz:
8285 case VPDPBSUDSZrr:
8286 case VPDPBSUDSZrrk:
8287 case VPDPBSUDSZrrkz:
8288 case VPDPBSUDSrm:
8289 case VPDPBSUDSrr:
8290 return true;
8291 }
8292 return false;
8293}
8294
8295bool isVSHA512MSG2(unsigned Opcode) {
8296 return Opcode == VSHA512MSG2rr;
8297}
8298
8299bool isPMULHUW(unsigned Opcode) {
8300 switch (Opcode) {
8301 case MMX_PMULHUWrm:
8302 case MMX_PMULHUWrr:
8303 case PMULHUWrm:
8304 case PMULHUWrr:
8305 return true;
8306 }
8307 return false;
8308}
8309
8310bool isKANDNB(unsigned Opcode) {
8311 return Opcode == KANDNBkk;
8312}
8313
8314bool isVCVTUW2PH(unsigned Opcode) {
8315 switch (Opcode) {
8316 case VCVTUW2PHZ128rm:
8317 case VCVTUW2PHZ128rmb:
8318 case VCVTUW2PHZ128rmbk:
8319 case VCVTUW2PHZ128rmbkz:
8320 case VCVTUW2PHZ128rmk:
8321 case VCVTUW2PHZ128rmkz:
8322 case VCVTUW2PHZ128rr:
8323 case VCVTUW2PHZ128rrk:
8324 case VCVTUW2PHZ128rrkz:
8325 case VCVTUW2PHZ256rm:
8326 case VCVTUW2PHZ256rmb:
8327 case VCVTUW2PHZ256rmbk:
8328 case VCVTUW2PHZ256rmbkz:
8329 case VCVTUW2PHZ256rmk:
8330 case VCVTUW2PHZ256rmkz:
8331 case VCVTUW2PHZ256rr:
8332 case VCVTUW2PHZ256rrk:
8333 case VCVTUW2PHZ256rrkz:
8334 case VCVTUW2PHZrm:
8335 case VCVTUW2PHZrmb:
8336 case VCVTUW2PHZrmbk:
8337 case VCVTUW2PHZrmbkz:
8338 case VCVTUW2PHZrmk:
8339 case VCVTUW2PHZrmkz:
8340 case VCVTUW2PHZrr:
8341 case VCVTUW2PHZrrb:
8342 case VCVTUW2PHZrrbk:
8343 case VCVTUW2PHZrrbkz:
8344 case VCVTUW2PHZrrk:
8345 case VCVTUW2PHZrrkz:
8346 return true;
8347 }
8348 return false;
8349}
8350
8351bool isAESDECWIDE256KL(unsigned Opcode) {
8352 return Opcode == AESDECWIDE256KL;
8353}
8354
8355bool isVPGATHERDD(unsigned Opcode) {
8356 switch (Opcode) {
8357 case VPGATHERDDYrm:
8358 case VPGATHERDDZ128rm:
8359 case VPGATHERDDZ256rm:
8360 case VPGATHERDDZrm:
8361 case VPGATHERDDrm:
8362 return true;
8363 }
8364 return false;
8365}
8366
8367bool isVREDUCESH(unsigned Opcode) {
8368 switch (Opcode) {
8369 case VREDUCESHZrmi:
8370 case VREDUCESHZrmik:
8371 case VREDUCESHZrmikz:
8372 case VREDUCESHZrri:
8373 case VREDUCESHZrrib:
8374 case VREDUCESHZrribk:
8375 case VREDUCESHZrribkz:
8376 case VREDUCESHZrrik:
8377 case VREDUCESHZrrikz:
8378 return true;
8379 }
8380 return false;
8381}
8382
8383bool isPOPFQ(unsigned Opcode) {
8384 return Opcode == POPF64;
8385}
8386
8387bool isPAVGUSB(unsigned Opcode) {
8388 switch (Opcode) {
8389 case PAVGUSBrm:
8390 case PAVGUSBrr:
8391 return true;
8392 }
8393 return false;
8394}
8395
8396bool isVALIGND(unsigned Opcode) {
8397 switch (Opcode) {
8398 case VALIGNDZ128rmbi:
8399 case VALIGNDZ128rmbik:
8400 case VALIGNDZ128rmbikz:
8401 case VALIGNDZ128rmi:
8402 case VALIGNDZ128rmik:
8403 case VALIGNDZ128rmikz:
8404 case VALIGNDZ128rri:
8405 case VALIGNDZ128rrik:
8406 case VALIGNDZ128rrikz:
8407 case VALIGNDZ256rmbi:
8408 case VALIGNDZ256rmbik:
8409 case VALIGNDZ256rmbikz:
8410 case VALIGNDZ256rmi:
8411 case VALIGNDZ256rmik:
8412 case VALIGNDZ256rmikz:
8413 case VALIGNDZ256rri:
8414 case VALIGNDZ256rrik:
8415 case VALIGNDZ256rrikz:
8416 case VALIGNDZrmbi:
8417 case VALIGNDZrmbik:
8418 case VALIGNDZrmbikz:
8419 case VALIGNDZrmi:
8420 case VALIGNDZrmik:
8421 case VALIGNDZrmikz:
8422 case VALIGNDZrri:
8423 case VALIGNDZrrik:
8424 case VALIGNDZrrikz:
8425 return true;
8426 }
8427 return false;
8428}
8429
8430bool isVPHMINPOSUW(unsigned Opcode) {
8431 switch (Opcode) {
8432 case VPHMINPOSUWrm:
8433 case VPHMINPOSUWrr:
8434 return true;
8435 }
8436 return false;
8437}
8438
8439bool isLIDTD(unsigned Opcode) {
8440 return Opcode == LIDT32m;
8441}
8442
8443bool isVPERMT2PD(unsigned Opcode) {
8444 switch (Opcode) {
8445 case VPERMT2PDZ128rm:
8446 case VPERMT2PDZ128rmb:
8447 case VPERMT2PDZ128rmbk:
8448 case VPERMT2PDZ128rmbkz:
8449 case VPERMT2PDZ128rmk:
8450 case VPERMT2PDZ128rmkz:
8451 case VPERMT2PDZ128rr:
8452 case VPERMT2PDZ128rrk:
8453 case VPERMT2PDZ128rrkz:
8454 case VPERMT2PDZ256rm:
8455 case VPERMT2PDZ256rmb:
8456 case VPERMT2PDZ256rmbk:
8457 case VPERMT2PDZ256rmbkz:
8458 case VPERMT2PDZ256rmk:
8459 case VPERMT2PDZ256rmkz:
8460 case VPERMT2PDZ256rr:
8461 case VPERMT2PDZ256rrk:
8462 case VPERMT2PDZ256rrkz:
8463 case VPERMT2PDZrm:
8464 case VPERMT2PDZrmb:
8465 case VPERMT2PDZrmbk:
8466 case VPERMT2PDZrmbkz:
8467 case VPERMT2PDZrmk:
8468 case VPERMT2PDZrmkz:
8469 case VPERMT2PDZrr:
8470 case VPERMT2PDZrrk:
8471 case VPERMT2PDZrrkz:
8472 return true;
8473 }
8474 return false;
8475}
8476
8477bool isVMLAUNCH(unsigned Opcode) {
8478 return Opcode == VMLAUNCH;
8479}
8480
8481bool isVPXORQ(unsigned Opcode) {
8482 switch (Opcode) {
8483 case VPXORQZ128rm:
8484 case VPXORQZ128rmb:
8485 case VPXORQZ128rmbk:
8486 case VPXORQZ128rmbkz:
8487 case VPXORQZ128rmk:
8488 case VPXORQZ128rmkz:
8489 case VPXORQZ128rr:
8490 case VPXORQZ128rrk:
8491 case VPXORQZ128rrkz:
8492 case VPXORQZ256rm:
8493 case VPXORQZ256rmb:
8494 case VPXORQZ256rmbk:
8495 case VPXORQZ256rmbkz:
8496 case VPXORQZ256rmk:
8497 case VPXORQZ256rmkz:
8498 case VPXORQZ256rr:
8499 case VPXORQZ256rrk:
8500 case VPXORQZ256rrkz:
8501 case VPXORQZrm:
8502 case VPXORQZrmb:
8503 case VPXORQZrmbk:
8504 case VPXORQZrmbkz:
8505 case VPXORQZrmk:
8506 case VPXORQZrmkz:
8507 case VPXORQZrr:
8508 case VPXORQZrrk:
8509 case VPXORQZrrkz:
8510 return true;
8511 }
8512 return false;
8513}
8514
8515bool isMOVNTDQ(unsigned Opcode) {
8516 return Opcode == MOVNTDQmr;
8517}
8518
8519bool isPOP2P(unsigned Opcode) {
8520 return Opcode == POP2P;
8521}
8522
8523bool isVADDPD(unsigned Opcode) {
8524 switch (Opcode) {
8525 case VADDPDYrm:
8526 case VADDPDYrr:
8527 case VADDPDZ128rm:
8528 case VADDPDZ128rmb:
8529 case VADDPDZ128rmbk:
8530 case VADDPDZ128rmbkz:
8531 case VADDPDZ128rmk:
8532 case VADDPDZ128rmkz:
8533 case VADDPDZ128rr:
8534 case VADDPDZ128rrk:
8535 case VADDPDZ128rrkz:
8536 case VADDPDZ256rm:
8537 case VADDPDZ256rmb:
8538 case VADDPDZ256rmbk:
8539 case VADDPDZ256rmbkz:
8540 case VADDPDZ256rmk:
8541 case VADDPDZ256rmkz:
8542 case VADDPDZ256rr:
8543 case VADDPDZ256rrk:
8544 case VADDPDZ256rrkz:
8545 case VADDPDZrm:
8546 case VADDPDZrmb:
8547 case VADDPDZrmbk:
8548 case VADDPDZrmbkz:
8549 case VADDPDZrmk:
8550 case VADDPDZrmkz:
8551 case VADDPDZrr:
8552 case VADDPDZrrb:
8553 case VADDPDZrrbk:
8554 case VADDPDZrrbkz:
8555 case VADDPDZrrk:
8556 case VADDPDZrrkz:
8557 case VADDPDrm:
8558 case VADDPDrr:
8559 return true;
8560 }
8561 return false;
8562}
8563
8564bool isSMSW(unsigned Opcode) {
8565 switch (Opcode) {
8566 case SMSW16m:
8567 case SMSW16r:
8568 case SMSW32r:
8569 case SMSW64r:
8570 return true;
8571 }
8572 return false;
8573}
8574
8575bool isVEXP2PD(unsigned Opcode) {
8576 switch (Opcode) {
8577 case VEXP2PDZm:
8578 case VEXP2PDZmb:
8579 case VEXP2PDZmbk:
8580 case VEXP2PDZmbkz:
8581 case VEXP2PDZmk:
8582 case VEXP2PDZmkz:
8583 case VEXP2PDZr:
8584 case VEXP2PDZrb:
8585 case VEXP2PDZrbk:
8586 case VEXP2PDZrbkz:
8587 case VEXP2PDZrk:
8588 case VEXP2PDZrkz:
8589 return true;
8590 }
8591 return false;
8592}
8593
8594bool isPMULUDQ(unsigned Opcode) {
8595 switch (Opcode) {
8596 case MMX_PMULUDQrm:
8597 case MMX_PMULUDQrr:
8598 case PMULUDQrm:
8599 case PMULUDQrr:
8600 return true;
8601 }
8602 return false;
8603}
8604
8605bool isIRET(unsigned Opcode) {
8606 return Opcode == IRET16;
8607}
8608
8609bool isMULPS(unsigned Opcode) {
8610 switch (Opcode) {
8611 case MULPSrm:
8612 case MULPSrr:
8613 return true;
8614 }
8615 return false;
8616}
8617
8618bool isTDPBF8PS(unsigned Opcode) {
8619 return Opcode == TDPBF8PS;
8620}
8621
8622bool isVFNMSUBPD(unsigned Opcode) {
8623 switch (Opcode) {
8624 case VFNMSUBPD4Ymr:
8625 case VFNMSUBPD4Yrm:
8626 case VFNMSUBPD4Yrr:
8627 case VFNMSUBPD4Yrr_REV:
8628 case VFNMSUBPD4mr:
8629 case VFNMSUBPD4rm:
8630 case VFNMSUBPD4rr:
8631 case VFNMSUBPD4rr_REV:
8632 return true;
8633 }
8634 return false;
8635}
8636
8637bool isPHADDW(unsigned Opcode) {
8638 switch (Opcode) {
8639 case MMX_PHADDWrm:
8640 case MMX_PHADDWrr:
8641 case PHADDWrm:
8642 case PHADDWrr:
8643 return true;
8644 }
8645 return false;
8646}
8647
8648bool isRDSEED(unsigned Opcode) {
8649 switch (Opcode) {
8650 case RDSEED16r:
8651 case RDSEED32r:
8652 case RDSEED64r:
8653 return true;
8654 }
8655 return false;
8656}
8657
8658bool isVPSHLW(unsigned Opcode) {
8659 switch (Opcode) {
8660 case VPSHLWmr:
8661 case VPSHLWrm:
8662 case VPSHLWrr:
8663 case VPSHLWrr_REV:
8664 return true;
8665 }
8666 return false;
8667}
8668
8669bool isRMPUPDATE(unsigned Opcode) {
8670 return Opcode == RMPUPDATE;
8671}
8672
8673bool isVFMADD231PH(unsigned Opcode) {
8674 switch (Opcode) {
8675 case VFMADD231PHZ128m:
8676 case VFMADD231PHZ128mb:
8677 case VFMADD231PHZ128mbk:
8678 case VFMADD231PHZ128mbkz:
8679 case VFMADD231PHZ128mk:
8680 case VFMADD231PHZ128mkz:
8681 case VFMADD231PHZ128r:
8682 case VFMADD231PHZ128rk:
8683 case VFMADD231PHZ128rkz:
8684 case VFMADD231PHZ256m:
8685 case VFMADD231PHZ256mb:
8686 case VFMADD231PHZ256mbk:
8687 case VFMADD231PHZ256mbkz:
8688 case VFMADD231PHZ256mk:
8689 case VFMADD231PHZ256mkz:
8690 case VFMADD231PHZ256r:
8691 case VFMADD231PHZ256rk:
8692 case VFMADD231PHZ256rkz:
8693 case VFMADD231PHZm:
8694 case VFMADD231PHZmb:
8695 case VFMADD231PHZmbk:
8696 case VFMADD231PHZmbkz:
8697 case VFMADD231PHZmk:
8698 case VFMADD231PHZmkz:
8699 case VFMADD231PHZr:
8700 case VFMADD231PHZrb:
8701 case VFMADD231PHZrbk:
8702 case VFMADD231PHZrbkz:
8703 case VFMADD231PHZrk:
8704 case VFMADD231PHZrkz:
8705 return true;
8706 }
8707 return false;
8708}
8709
8710bool isVPSHAD(unsigned Opcode) {
8711 switch (Opcode) {
8712 case VPSHADmr:
8713 case VPSHADrm:
8714 case VPSHADrr:
8715 case VPSHADrr_REV:
8716 return true;
8717 }
8718 return false;
8719}
8720
8721bool isCLWB(unsigned Opcode) {
8722 return Opcode == CLWB;
8723}
8724
8725bool isPSUBUSB(unsigned Opcode) {
8726 switch (Opcode) {
8727 case MMX_PSUBUSBrm:
8728 case MMX_PSUBUSBrr:
8729 case PSUBUSBrm:
8730 case PSUBUSBrr:
8731 return true;
8732 }
8733 return false;
8734}
8735
8736bool isVCVTTSD2USI(unsigned Opcode) {
8737 switch (Opcode) {
8738 case VCVTTSD2USI64Zrm_Int:
8739 case VCVTTSD2USI64Zrr_Int:
8740 case VCVTTSD2USI64Zrrb_Int:
8741 case VCVTTSD2USIZrm_Int:
8742 case VCVTTSD2USIZrr_Int:
8743 case VCVTTSD2USIZrrb_Int:
8744 return true;
8745 }
8746 return false;
8747}
8748
8749bool isVEXTRACTPS(unsigned Opcode) {
8750 switch (Opcode) {
8751 case VEXTRACTPSZmri:
8752 case VEXTRACTPSZrri:
8753 case VEXTRACTPSmri:
8754 case VEXTRACTPSrri:
8755 return true;
8756 }
8757 return false;
8758}
8759
8760bool isMOVLPD(unsigned Opcode) {
8761 switch (Opcode) {
8762 case MOVLPDmr:
8763 case MOVLPDrm:
8764 return true;
8765 }
8766 return false;
8767}
8768
8769bool isLGDTD(unsigned Opcode) {
8770 return Opcode == LGDT32m;
8771}
8772
8773bool isVPBROADCASTMB2Q(unsigned Opcode) {
8774 switch (Opcode) {
8775 case VPBROADCASTMB2QZ128rr:
8776 case VPBROADCASTMB2QZ256rr:
8777 case VPBROADCASTMB2QZrr:
8778 return true;
8779 }
8780 return false;
8781}
8782
8783bool isOUT(unsigned Opcode) {
8784 switch (Opcode) {
8785 case OUT16ir:
8786 case OUT16rr:
8787 case OUT32ir:
8788 case OUT32rr:
8789 case OUT8ir:
8790 case OUT8rr:
8791 return true;
8792 }
8793 return false;
8794}
8795
8796bool isVMSAVE(unsigned Opcode) {
8797 switch (Opcode) {
8798 case VMSAVE32:
8799 case VMSAVE64:
8800 return true;
8801 }
8802 return false;
8803}
8804
8805bool isVCVTQQ2PD(unsigned Opcode) {
8806 switch (Opcode) {
8807 case VCVTQQ2PDZ128rm:
8808 case VCVTQQ2PDZ128rmb:
8809 case VCVTQQ2PDZ128rmbk:
8810 case VCVTQQ2PDZ128rmbkz:
8811 case VCVTQQ2PDZ128rmk:
8812 case VCVTQQ2PDZ128rmkz:
8813 case VCVTQQ2PDZ128rr:
8814 case VCVTQQ2PDZ128rrk:
8815 case VCVTQQ2PDZ128rrkz:
8816 case VCVTQQ2PDZ256rm:
8817 case VCVTQQ2PDZ256rmb:
8818 case VCVTQQ2PDZ256rmbk:
8819 case VCVTQQ2PDZ256rmbkz:
8820 case VCVTQQ2PDZ256rmk:
8821 case VCVTQQ2PDZ256rmkz:
8822 case VCVTQQ2PDZ256rr:
8823 case VCVTQQ2PDZ256rrk:
8824 case VCVTQQ2PDZ256rrkz:
8825 case VCVTQQ2PDZrm:
8826 case VCVTQQ2PDZrmb:
8827 case VCVTQQ2PDZrmbk:
8828 case VCVTQQ2PDZrmbkz:
8829 case VCVTQQ2PDZrmk:
8830 case VCVTQQ2PDZrmkz:
8831 case VCVTQQ2PDZrr:
8832 case VCVTQQ2PDZrrb:
8833 case VCVTQQ2PDZrrbk:
8834 case VCVTQQ2PDZrrbkz:
8835 case VCVTQQ2PDZrrk:
8836 case VCVTQQ2PDZrrkz:
8837 return true;
8838 }
8839 return false;
8840}
8841
8842bool isVFMADD213PH(unsigned Opcode) {
8843 switch (Opcode) {
8844 case VFMADD213PHZ128m:
8845 case VFMADD213PHZ128mb:
8846 case VFMADD213PHZ128mbk:
8847 case VFMADD213PHZ128mbkz:
8848 case VFMADD213PHZ128mk:
8849 case VFMADD213PHZ128mkz:
8850 case VFMADD213PHZ128r:
8851 case VFMADD213PHZ128rk:
8852 case VFMADD213PHZ128rkz:
8853 case VFMADD213PHZ256m:
8854 case VFMADD213PHZ256mb:
8855 case VFMADD213PHZ256mbk:
8856 case VFMADD213PHZ256mbkz:
8857 case VFMADD213PHZ256mk:
8858 case VFMADD213PHZ256mkz:
8859 case VFMADD213PHZ256r:
8860 case VFMADD213PHZ256rk:
8861 case VFMADD213PHZ256rkz:
8862 case VFMADD213PHZm:
8863 case VFMADD213PHZmb:
8864 case VFMADD213PHZmbk:
8865 case VFMADD213PHZmbkz:
8866 case VFMADD213PHZmk:
8867 case VFMADD213PHZmkz:
8868 case VFMADD213PHZr:
8869 case VFMADD213PHZrb:
8870 case VFMADD213PHZrbk:
8871 case VFMADD213PHZrbkz:
8872 case VFMADD213PHZrk:
8873 case VFMADD213PHZrkz:
8874 return true;
8875 }
8876 return false;
8877}
8878
8879bool isFCMOVBE(unsigned Opcode) {
8880 return Opcode == CMOVBE_F;
8881}
8882
8883bool isMOVSHDUP(unsigned Opcode) {
8884 switch (Opcode) {
8885 case MOVSHDUPrm:
8886 case MOVSHDUPrr:
8887 return true;
8888 }
8889 return false;
8890}
8891
8892bool isVPMOVUSQB(unsigned Opcode) {
8893 switch (Opcode) {
8894 case VPMOVUSQBZ128mr:
8895 case VPMOVUSQBZ128mrk:
8896 case VPMOVUSQBZ128rr:
8897 case VPMOVUSQBZ128rrk:
8898 case VPMOVUSQBZ128rrkz:
8899 case VPMOVUSQBZ256mr:
8900 case VPMOVUSQBZ256mrk:
8901 case VPMOVUSQBZ256rr:
8902 case VPMOVUSQBZ256rrk:
8903 case VPMOVUSQBZ256rrkz:
8904 case VPMOVUSQBZmr:
8905 case VPMOVUSQBZmrk:
8906 case VPMOVUSQBZrr:
8907 case VPMOVUSQBZrrk:
8908 case VPMOVUSQBZrrkz:
8909 return true;
8910 }
8911 return false;
8912}
8913
8914bool isFIST(unsigned Opcode) {
8915 switch (Opcode) {
8916 case IST_F16m:
8917 case IST_F32m:
8918 return true;
8919 }
8920 return false;
8921}
8922
8923bool isHADDPD(unsigned Opcode) {
8924 switch (Opcode) {
8925 case HADDPDrm:
8926 case HADDPDrr:
8927 return true;
8928 }
8929 return false;
8930}
8931
8932bool isPACKSSWB(unsigned Opcode) {
8933 switch (Opcode) {
8934 case MMX_PACKSSWBrm:
8935 case MMX_PACKSSWBrr:
8936 case PACKSSWBrm:
8937 case PACKSSWBrr:
8938 return true;
8939 }
8940 return false;
8941}
8942
8943bool isVPMACSSDQH(unsigned Opcode) {
8944 switch (Opcode) {
8945 case VPMACSSDQHrm:
8946 case VPMACSSDQHrr:
8947 return true;
8948 }
8949 return false;
8950}
8951
8952bool isVFNMSUB132SD(unsigned Opcode) {
8953 switch (Opcode) {
8954 case VFNMSUB132SDZm_Int:
8955 case VFNMSUB132SDZmk_Int:
8956 case VFNMSUB132SDZmkz_Int:
8957 case VFNMSUB132SDZr_Int:
8958 case VFNMSUB132SDZrb_Int:
8959 case VFNMSUB132SDZrbk_Int:
8960 case VFNMSUB132SDZrbkz_Int:
8961 case VFNMSUB132SDZrk_Int:
8962 case VFNMSUB132SDZrkz_Int:
8963 case VFNMSUB132SDm_Int:
8964 case VFNMSUB132SDr_Int:
8965 return true;
8966 }
8967 return false;
8968}
8969
8970bool isVPMASKMOVQ(unsigned Opcode) {
8971 switch (Opcode) {
8972 case VPMASKMOVQYmr:
8973 case VPMASKMOVQYrm:
8974 case VPMASKMOVQmr:
8975 case VPMASKMOVQrm:
8976 return true;
8977 }
8978 return false;
8979}
8980
8981bool isVCOMPRESSPD(unsigned Opcode) {
8982 switch (Opcode) {
8983 case VCOMPRESSPDZ128mr:
8984 case VCOMPRESSPDZ128mrk:
8985 case VCOMPRESSPDZ128rr:
8986 case VCOMPRESSPDZ128rrk:
8987 case VCOMPRESSPDZ128rrkz:
8988 case VCOMPRESSPDZ256mr:
8989 case VCOMPRESSPDZ256mrk:
8990 case VCOMPRESSPDZ256rr:
8991 case VCOMPRESSPDZ256rrk:
8992 case VCOMPRESSPDZ256rrkz:
8993 case VCOMPRESSPDZmr:
8994 case VCOMPRESSPDZmrk:
8995 case VCOMPRESSPDZrr:
8996 case VCOMPRESSPDZrrk:
8997 case VCOMPRESSPDZrrkz:
8998 return true;
8999 }
9000 return false;
9001}
9002
9003bool isVFMADD213SS(unsigned Opcode) {
9004 switch (Opcode) {
9005 case VFMADD213SSZm_Int:
9006 case VFMADD213SSZmk_Int:
9007 case VFMADD213SSZmkz_Int:
9008 case VFMADD213SSZr_Int:
9009 case VFMADD213SSZrb_Int:
9010 case VFMADD213SSZrbk_Int:
9011 case VFMADD213SSZrbkz_Int:
9012 case VFMADD213SSZrk_Int:
9013 case VFMADD213SSZrkz_Int:
9014 case VFMADD213SSm_Int:
9015 case VFMADD213SSr_Int:
9016 return true;
9017 }
9018 return false;
9019}
9020
9021bool isVPCMPQ(unsigned Opcode) {
9022 switch (Opcode) {
9023 case VPCMPQZ128rmbi:
9024 case VPCMPQZ128rmbik:
9025 case VPCMPQZ128rmi:
9026 case VPCMPQZ128rmik:
9027 case VPCMPQZ128rri:
9028 case VPCMPQZ128rrik:
9029 case VPCMPQZ256rmbi:
9030 case VPCMPQZ256rmbik:
9031 case VPCMPQZ256rmi:
9032 case VPCMPQZ256rmik:
9033 case VPCMPQZ256rri:
9034 case VPCMPQZ256rrik:
9035 case VPCMPQZrmbi:
9036 case VPCMPQZrmbik:
9037 case VPCMPQZrmi:
9038 case VPCMPQZrmik:
9039 case VPCMPQZrri:
9040 case VPCMPQZrrik:
9041 return true;
9042 }
9043 return false;
9044}
9045
9046bool isVADDSH(unsigned Opcode) {
9047 switch (Opcode) {
9048 case VADDSHZrm_Int:
9049 case VADDSHZrmk_Int:
9050 case VADDSHZrmkz_Int:
9051 case VADDSHZrr_Int:
9052 case VADDSHZrrb_Int:
9053 case VADDSHZrrbk_Int:
9054 case VADDSHZrrbkz_Int:
9055 case VADDSHZrrk_Int:
9056 case VADDSHZrrkz_Int:
9057 return true;
9058 }
9059 return false;
9060}
9061
9062bool isVFNMADDSD(unsigned Opcode) {
9063 switch (Opcode) {
9064 case VFNMADDSD4mr:
9065 case VFNMADDSD4rm:
9066 case VFNMADDSD4rr:
9067 case VFNMADDSD4rr_REV:
9068 return true;
9069 }
9070 return false;
9071}
9072
9073bool isUMWAIT(unsigned Opcode) {
9074 return Opcode == UMWAIT;
9075}
9076
9077bool isVPUNPCKHDQ(unsigned Opcode) {
9078 switch (Opcode) {
9079 case VPUNPCKHDQYrm:
9080 case VPUNPCKHDQYrr:
9081 case VPUNPCKHDQZ128rm:
9082 case VPUNPCKHDQZ128rmb:
9083 case VPUNPCKHDQZ128rmbk:
9084 case VPUNPCKHDQZ128rmbkz:
9085 case VPUNPCKHDQZ128rmk:
9086 case VPUNPCKHDQZ128rmkz:
9087 case VPUNPCKHDQZ128rr:
9088 case VPUNPCKHDQZ128rrk:
9089 case VPUNPCKHDQZ128rrkz:
9090 case VPUNPCKHDQZ256rm:
9091 case VPUNPCKHDQZ256rmb:
9092 case VPUNPCKHDQZ256rmbk:
9093 case VPUNPCKHDQZ256rmbkz:
9094 case VPUNPCKHDQZ256rmk:
9095 case VPUNPCKHDQZ256rmkz:
9096 case VPUNPCKHDQZ256rr:
9097 case VPUNPCKHDQZ256rrk:
9098 case VPUNPCKHDQZ256rrkz:
9099 case VPUNPCKHDQZrm:
9100 case VPUNPCKHDQZrmb:
9101 case VPUNPCKHDQZrmbk:
9102 case VPUNPCKHDQZrmbkz:
9103 case VPUNPCKHDQZrmk:
9104 case VPUNPCKHDQZrmkz:
9105 case VPUNPCKHDQZrr:
9106 case VPUNPCKHDQZrrk:
9107 case VPUNPCKHDQZrrkz:
9108 case VPUNPCKHDQrm:
9109 case VPUNPCKHDQrr:
9110 return true;
9111 }
9112 return false;
9113}
9114
9115bool isLCALL(unsigned Opcode) {
9116 switch (Opcode) {
9117 case FARCALL16i:
9118 case FARCALL16m:
9119 case FARCALL32i:
9120 case FARCALL64m:
9121 return true;
9122 }
9123 return false;
9124}
9125
9126bool isAESDEC128KL(unsigned Opcode) {
9127 return Opcode == AESDEC128KL;
9128}
9129
9130bool isVSUBPS(unsigned Opcode) {
9131 switch (Opcode) {
9132 case VSUBPSYrm:
9133 case VSUBPSYrr:
9134 case VSUBPSZ128rm:
9135 case VSUBPSZ128rmb:
9136 case VSUBPSZ128rmbk:
9137 case VSUBPSZ128rmbkz:
9138 case VSUBPSZ128rmk:
9139 case VSUBPSZ128rmkz:
9140 case VSUBPSZ128rr:
9141 case VSUBPSZ128rrk:
9142 case VSUBPSZ128rrkz:
9143 case VSUBPSZ256rm:
9144 case VSUBPSZ256rmb:
9145 case VSUBPSZ256rmbk:
9146 case VSUBPSZ256rmbkz:
9147 case VSUBPSZ256rmk:
9148 case VSUBPSZ256rmkz:
9149 case VSUBPSZ256rr:
9150 case VSUBPSZ256rrk:
9151 case VSUBPSZ256rrkz:
9152 case VSUBPSZrm:
9153 case VSUBPSZrmb:
9154 case VSUBPSZrmbk:
9155 case VSUBPSZrmbkz:
9156 case VSUBPSZrmk:
9157 case VSUBPSZrmkz:
9158 case VSUBPSZrr:
9159 case VSUBPSZrrb:
9160 case VSUBPSZrrbk:
9161 case VSUBPSZrrbkz:
9162 case VSUBPSZrrk:
9163 case VSUBPSZrrkz:
9164 case VSUBPSrm:
9165 case VSUBPSrr:
9166 return true;
9167 }
9168 return false;
9169}
9170
9171bool isFSTP(unsigned Opcode) {
9172 switch (Opcode) {
9173 case ST_FP32m:
9174 case ST_FP64m:
9175 case ST_FP80m:
9176 case ST_FPrr:
9177 return true;
9178 }
9179 return false;
9180}
9181
9182bool isVCVTUDQ2PD(unsigned Opcode) {
9183 switch (Opcode) {
9184 case VCVTUDQ2PDZ128rm:
9185 case VCVTUDQ2PDZ128rmb:
9186 case VCVTUDQ2PDZ128rmbk:
9187 case VCVTUDQ2PDZ128rmbkz:
9188 case VCVTUDQ2PDZ128rmk:
9189 case VCVTUDQ2PDZ128rmkz:
9190 case VCVTUDQ2PDZ128rr:
9191 case VCVTUDQ2PDZ128rrk:
9192 case VCVTUDQ2PDZ128rrkz:
9193 case VCVTUDQ2PDZ256rm:
9194 case VCVTUDQ2PDZ256rmb:
9195 case VCVTUDQ2PDZ256rmbk:
9196 case VCVTUDQ2PDZ256rmbkz:
9197 case VCVTUDQ2PDZ256rmk:
9198 case VCVTUDQ2PDZ256rmkz:
9199 case VCVTUDQ2PDZ256rr:
9200 case VCVTUDQ2PDZ256rrk:
9201 case VCVTUDQ2PDZ256rrkz:
9202 case VCVTUDQ2PDZrm:
9203 case VCVTUDQ2PDZrmb:
9204 case VCVTUDQ2PDZrmbk:
9205 case VCVTUDQ2PDZrmbkz:
9206 case VCVTUDQ2PDZrmk:
9207 case VCVTUDQ2PDZrmkz:
9208 case VCVTUDQ2PDZrr:
9209 case VCVTUDQ2PDZrrk:
9210 case VCVTUDQ2PDZrrkz:
9211 return true;
9212 }
9213 return false;
9214}
9215
9216bool isVPMOVSWB(unsigned Opcode) {
9217 switch (Opcode) {
9218 case VPMOVSWBZ128mr:
9219 case VPMOVSWBZ128mrk:
9220 case VPMOVSWBZ128rr:
9221 case VPMOVSWBZ128rrk:
9222 case VPMOVSWBZ128rrkz:
9223 case VPMOVSWBZ256mr:
9224 case VPMOVSWBZ256mrk:
9225 case VPMOVSWBZ256rr:
9226 case VPMOVSWBZ256rrk:
9227 case VPMOVSWBZ256rrkz:
9228 case VPMOVSWBZmr:
9229 case VPMOVSWBZmrk:
9230 case VPMOVSWBZrr:
9231 case VPMOVSWBZrrk:
9232 case VPMOVSWBZrrkz:
9233 return true;
9234 }
9235 return false;
9236}
9237
9238bool isVPANDNQ(unsigned Opcode) {
9239 switch (Opcode) {
9240 case VPANDNQZ128rm:
9241 case VPANDNQZ128rmb:
9242 case VPANDNQZ128rmbk:
9243 case VPANDNQZ128rmbkz:
9244 case VPANDNQZ128rmk:
9245 case VPANDNQZ128rmkz:
9246 case VPANDNQZ128rr:
9247 case VPANDNQZ128rrk:
9248 case VPANDNQZ128rrkz:
9249 case VPANDNQZ256rm:
9250 case VPANDNQZ256rmb:
9251 case VPANDNQZ256rmbk:
9252 case VPANDNQZ256rmbkz:
9253 case VPANDNQZ256rmk:
9254 case VPANDNQZ256rmkz:
9255 case VPANDNQZ256rr:
9256 case VPANDNQZ256rrk:
9257 case VPANDNQZ256rrkz:
9258 case VPANDNQZrm:
9259 case VPANDNQZrmb:
9260 case VPANDNQZrmbk:
9261 case VPANDNQZrmbkz:
9262 case VPANDNQZrmk:
9263 case VPANDNQZrmkz:
9264 case VPANDNQZrr:
9265 case VPANDNQZrrk:
9266 case VPANDNQZrrkz:
9267 return true;
9268 }
9269 return false;
9270}
9271
9272bool isSYSENTER(unsigned Opcode) {
9273 return Opcode == SYSENTER;
9274}
9275
9276bool isVPHADDWD(unsigned Opcode) {
9277 switch (Opcode) {
9278 case VPHADDWDrm:
9279 case VPHADDWDrr:
9280 return true;
9281 }
9282 return false;
9283}
9284
9285bool isVMOVHPD(unsigned Opcode) {
9286 switch (Opcode) {
9287 case VMOVHPDZ128mr:
9288 case VMOVHPDZ128rm:
9289 case VMOVHPDmr:
9290 case VMOVHPDrm:
9291 return true;
9292 }
9293 return false;
9294}
9295
9296bool isMOVHPD(unsigned Opcode) {
9297 switch (Opcode) {
9298 case MOVHPDmr:
9299 case MOVHPDrm:
9300 return true;
9301 }
9302 return false;
9303}
9304
9305bool isVDIVPH(unsigned Opcode) {
9306 switch (Opcode) {
9307 case VDIVPHZ128rm:
9308 case VDIVPHZ128rmb:
9309 case VDIVPHZ128rmbk:
9310 case VDIVPHZ128rmbkz:
9311 case VDIVPHZ128rmk:
9312 case VDIVPHZ128rmkz:
9313 case VDIVPHZ128rr:
9314 case VDIVPHZ128rrk:
9315 case VDIVPHZ128rrkz:
9316 case VDIVPHZ256rm:
9317 case VDIVPHZ256rmb:
9318 case VDIVPHZ256rmbk:
9319 case VDIVPHZ256rmbkz:
9320 case VDIVPHZ256rmk:
9321 case VDIVPHZ256rmkz:
9322 case VDIVPHZ256rr:
9323 case VDIVPHZ256rrk:
9324 case VDIVPHZ256rrkz:
9325 case VDIVPHZrm:
9326 case VDIVPHZrmb:
9327 case VDIVPHZrmbk:
9328 case VDIVPHZrmbkz:
9329 case VDIVPHZrmk:
9330 case VDIVPHZrmkz:
9331 case VDIVPHZrr:
9332 case VDIVPHZrrb:
9333 case VDIVPHZrrbk:
9334 case VDIVPHZrrbkz:
9335 case VDIVPHZrrk:
9336 case VDIVPHZrrkz:
9337 return true;
9338 }
9339 return false;
9340}
9341
9342bool isFFREE(unsigned Opcode) {
9343 return Opcode == FFREE;
9344}
9345
9346bool isVGATHERPF1DPS(unsigned Opcode) {
9347 return Opcode == VGATHERPF1DPSm;
9348}
9349
9350bool isVPCMPESTRIQ(unsigned Opcode) {
9351 switch (Opcode) {
9352 case VPCMPESTRIQrmi:
9353 case VPCMPESTRIQrri:
9354 return true;
9355 }
9356 return false;
9357}
9358
9359bool isVFNMADD231PD(unsigned Opcode) {
9360 switch (Opcode) {
9361 case VFNMADD231PDYm:
9362 case VFNMADD231PDYr:
9363 case VFNMADD231PDZ128m:
9364 case VFNMADD231PDZ128mb:
9365 case VFNMADD231PDZ128mbk:
9366 case VFNMADD231PDZ128mbkz:
9367 case VFNMADD231PDZ128mk:
9368 case VFNMADD231PDZ128mkz:
9369 case VFNMADD231PDZ128r:
9370 case VFNMADD231PDZ128rk:
9371 case VFNMADD231PDZ128rkz:
9372 case VFNMADD231PDZ256m:
9373 case VFNMADD231PDZ256mb:
9374 case VFNMADD231PDZ256mbk:
9375 case VFNMADD231PDZ256mbkz:
9376 case VFNMADD231PDZ256mk:
9377 case VFNMADD231PDZ256mkz:
9378 case VFNMADD231PDZ256r:
9379 case VFNMADD231PDZ256rk:
9380 case VFNMADD231PDZ256rkz:
9381 case VFNMADD231PDZm:
9382 case VFNMADD231PDZmb:
9383 case VFNMADD231PDZmbk:
9384 case VFNMADD231PDZmbkz:
9385 case VFNMADD231PDZmk:
9386 case VFNMADD231PDZmkz:
9387 case VFNMADD231PDZr:
9388 case VFNMADD231PDZrb:
9389 case VFNMADD231PDZrbk:
9390 case VFNMADD231PDZrbkz:
9391 case VFNMADD231PDZrk:
9392 case VFNMADD231PDZrkz:
9393 case VFNMADD231PDm:
9394 case VFNMADD231PDr:
9395 return true;
9396 }
9397 return false;
9398}
9399
9400bool isVFCMULCPH(unsigned Opcode) {
9401 switch (Opcode) {
9402 case VFCMULCPHZ128rm:
9403 case VFCMULCPHZ128rmb:
9404 case VFCMULCPHZ128rmbk:
9405 case VFCMULCPHZ128rmbkz:
9406 case VFCMULCPHZ128rmk:
9407 case VFCMULCPHZ128rmkz:
9408 case VFCMULCPHZ128rr:
9409 case VFCMULCPHZ128rrk:
9410 case VFCMULCPHZ128rrkz:
9411 case VFCMULCPHZ256rm:
9412 case VFCMULCPHZ256rmb:
9413 case VFCMULCPHZ256rmbk:
9414 case VFCMULCPHZ256rmbkz:
9415 case VFCMULCPHZ256rmk:
9416 case VFCMULCPHZ256rmkz:
9417 case VFCMULCPHZ256rr:
9418 case VFCMULCPHZ256rrk:
9419 case VFCMULCPHZ256rrkz:
9420 case VFCMULCPHZrm:
9421 case VFCMULCPHZrmb:
9422 case VFCMULCPHZrmbk:
9423 case VFCMULCPHZrmbkz:
9424 case VFCMULCPHZrmk:
9425 case VFCMULCPHZrmkz:
9426 case VFCMULCPHZrr:
9427 case VFCMULCPHZrrb:
9428 case VFCMULCPHZrrbk:
9429 case VFCMULCPHZrrbkz:
9430 case VFCMULCPHZrrk:
9431 case VFCMULCPHZrrkz:
9432 return true;
9433 }
9434 return false;
9435}
9436
9437bool isVPADDD(unsigned Opcode) {
9438 switch (Opcode) {
9439 case VPADDDYrm:
9440 case VPADDDYrr:
9441 case VPADDDZ128rm:
9442 case VPADDDZ128rmb:
9443 case VPADDDZ128rmbk:
9444 case VPADDDZ128rmbkz:
9445 case VPADDDZ128rmk:
9446 case VPADDDZ128rmkz:
9447 case VPADDDZ128rr:
9448 case VPADDDZ128rrk:
9449 case VPADDDZ128rrkz:
9450 case VPADDDZ256rm:
9451 case VPADDDZ256rmb:
9452 case VPADDDZ256rmbk:
9453 case VPADDDZ256rmbkz:
9454 case VPADDDZ256rmk:
9455 case VPADDDZ256rmkz:
9456 case VPADDDZ256rr:
9457 case VPADDDZ256rrk:
9458 case VPADDDZ256rrkz:
9459 case VPADDDZrm:
9460 case VPADDDZrmb:
9461 case VPADDDZrmbk:
9462 case VPADDDZrmbkz:
9463 case VPADDDZrmk:
9464 case VPADDDZrmkz:
9465 case VPADDDZrr:
9466 case VPADDDZrrk:
9467 case VPADDDZrrkz:
9468 case VPADDDrm:
9469 case VPADDDrr:
9470 return true;
9471 }
9472 return false;
9473}
9474
9475bool isVPCOMUQ(unsigned Opcode) {
9476 switch (Opcode) {
9477 case VPCOMUQmi:
9478 case VPCOMUQri:
9479 return true;
9480 }
9481 return false;
9482}
9483
9484bool isVSM3MSG2(unsigned Opcode) {
9485 switch (Opcode) {
9486 case VSM3MSG2rm:
9487 case VSM3MSG2rr:
9488 return true;
9489 }
9490 return false;
9491}
9492
9493bool isVERR(unsigned Opcode) {
9494 switch (Opcode) {
9495 case VERRm:
9496 case VERRr:
9497 return true;
9498 }
9499 return false;
9500}
9501
9502bool isKORTESTQ(unsigned Opcode) {
9503 return Opcode == KORTESTQkk;
9504}
9505
9506bool isVFMSUB132SD(unsigned Opcode) {
9507 switch (Opcode) {
9508 case VFMSUB132SDZm_Int:
9509 case VFMSUB132SDZmk_Int:
9510 case VFMSUB132SDZmkz_Int:
9511 case VFMSUB132SDZr_Int:
9512 case VFMSUB132SDZrb_Int:
9513 case VFMSUB132SDZrbk_Int:
9514 case VFMSUB132SDZrbkz_Int:
9515 case VFMSUB132SDZrk_Int:
9516 case VFMSUB132SDZrkz_Int:
9517 case VFMSUB132SDm_Int:
9518 case VFMSUB132SDr_Int:
9519 return true;
9520 }
9521 return false;
9522}
9523
9524bool isTILEZERO(unsigned Opcode) {
9525 return Opcode == TILEZERO;
9526}
9527
9528bool isPFADD(unsigned Opcode) {
9529 switch (Opcode) {
9530 case PFADDrm:
9531 case PFADDrr:
9532 return true;
9533 }
9534 return false;
9535}
9536
9537bool isVCVTSI2SD(unsigned Opcode) {
9538 switch (Opcode) {
9539 case VCVTSI2SDZrm_Int:
9540 case VCVTSI2SDZrr_Int:
9541 case VCVTSI2SDrm_Int:
9542 case VCVTSI2SDrr_Int:
9543 case VCVTSI642SDZrm_Int:
9544 case VCVTSI642SDZrr_Int:
9545 case VCVTSI642SDZrrb_Int:
9546 case VCVTSI642SDrm_Int:
9547 case VCVTSI642SDrr_Int:
9548 return true;
9549 }
9550 return false;
9551}
9552
9553bool isTILELOADDRS(unsigned Opcode) {
9554 switch (Opcode) {
9555 case TILELOADDRS:
9556 case TILELOADDRS_EVEX:
9557 return true;
9558 }
9559 return false;
9560}
9561
9562bool isVSTMXCSR(unsigned Opcode) {
9563 return Opcode == VSTMXCSR;
9564}
9565
9566bool isVCVTTSH2SI(unsigned Opcode) {
9567 switch (Opcode) {
9568 case VCVTTSH2SI64Zrm_Int:
9569 case VCVTTSH2SI64Zrr_Int:
9570 case VCVTTSH2SI64Zrrb_Int:
9571 case VCVTTSH2SIZrm_Int:
9572 case VCVTTSH2SIZrr_Int:
9573 case VCVTTSH2SIZrrb_Int:
9574 return true;
9575 }
9576 return false;
9577}
9578
9579bool isRET(unsigned Opcode) {
9580 switch (Opcode) {
9581 case RET16:
9582 case RET32:
9583 case RET64:
9584 case RETI16:
9585 case RETI32:
9586 case RETI64:
9587 return true;
9588 }
9589 return false;
9590}
9591
9592bool isLZCNT(unsigned Opcode) {
9593 switch (Opcode) {
9594 case LZCNT16rm:
9595 case LZCNT16rm_EVEX:
9596 case LZCNT16rm_NF:
9597 case LZCNT16rr:
9598 case LZCNT16rr_EVEX:
9599 case LZCNT16rr_NF:
9600 case LZCNT32rm:
9601 case LZCNT32rm_EVEX:
9602 case LZCNT32rm_NF:
9603 case LZCNT32rr:
9604 case LZCNT32rr_EVEX:
9605 case LZCNT32rr_NF:
9606 case LZCNT64rm:
9607 case LZCNT64rm_EVEX:
9608 case LZCNT64rm_NF:
9609 case LZCNT64rr:
9610 case LZCNT64rr_EVEX:
9611 case LZCNT64rr_NF:
9612 return true;
9613 }
9614 return false;
9615}
9616
9617bool isMULPD(unsigned Opcode) {
9618 switch (Opcode) {
9619 case MULPDrm:
9620 case MULPDrr:
9621 return true;
9622 }
9623 return false;
9624}
9625
9626bool isVBROADCASTI32X2(unsigned Opcode) {
9627 switch (Opcode) {
9628 case VBROADCASTI32X2Z128rm:
9629 case VBROADCASTI32X2Z128rmk:
9630 case VBROADCASTI32X2Z128rmkz:
9631 case VBROADCASTI32X2Z128rr:
9632 case VBROADCASTI32X2Z128rrk:
9633 case VBROADCASTI32X2Z128rrkz:
9634 case VBROADCASTI32X2Z256rm:
9635 case VBROADCASTI32X2Z256rmk:
9636 case VBROADCASTI32X2Z256rmkz:
9637 case VBROADCASTI32X2Z256rr:
9638 case VBROADCASTI32X2Z256rrk:
9639 case VBROADCASTI32X2Z256rrkz:
9640 case VBROADCASTI32X2Zrm:
9641 case VBROADCASTI32X2Zrmk:
9642 case VBROADCASTI32X2Zrmkz:
9643 case VBROADCASTI32X2Zrr:
9644 case VBROADCASTI32X2Zrrk:
9645 case VBROADCASTI32X2Zrrkz:
9646 return true;
9647 }
9648 return false;
9649}
9650
9651bool isVCVTPH2W(unsigned Opcode) {
9652 switch (Opcode) {
9653 case VCVTPH2WZ128rm:
9654 case VCVTPH2WZ128rmb:
9655 case VCVTPH2WZ128rmbk:
9656 case VCVTPH2WZ128rmbkz:
9657 case VCVTPH2WZ128rmk:
9658 case VCVTPH2WZ128rmkz:
9659 case VCVTPH2WZ128rr:
9660 case VCVTPH2WZ128rrk:
9661 case VCVTPH2WZ128rrkz:
9662 case VCVTPH2WZ256rm:
9663 case VCVTPH2WZ256rmb:
9664 case VCVTPH2WZ256rmbk:
9665 case VCVTPH2WZ256rmbkz:
9666 case VCVTPH2WZ256rmk:
9667 case VCVTPH2WZ256rmkz:
9668 case VCVTPH2WZ256rr:
9669 case VCVTPH2WZ256rrk:
9670 case VCVTPH2WZ256rrkz:
9671 case VCVTPH2WZrm:
9672 case VCVTPH2WZrmb:
9673 case VCVTPH2WZrmbk:
9674 case VCVTPH2WZrmbkz:
9675 case VCVTPH2WZrmk:
9676 case VCVTPH2WZrmkz:
9677 case VCVTPH2WZrr:
9678 case VCVTPH2WZrrb:
9679 case VCVTPH2WZrrbk:
9680 case VCVTPH2WZrrbkz:
9681 case VCVTPH2WZrrk:
9682 case VCVTPH2WZrrkz:
9683 return true;
9684 }
9685 return false;
9686}
9687
9688bool isCQO(unsigned Opcode) {
9689 return Opcode == CQO;
9690}
9691
9692bool isFSUBR(unsigned Opcode) {
9693 switch (Opcode) {
9694 case SUBR_F32m:
9695 case SUBR_F64m:
9696 case SUBR_FST0r:
9697 case SUBR_FrST0:
9698 return true;
9699 }
9700 return false;
9701}
9702
9703bool isDPPD(unsigned Opcode) {
9704 switch (Opcode) {
9705 case DPPDrmi:
9706 case DPPDrri:
9707 return true;
9708 }
9709 return false;
9710}
9711
9712bool isFCOS(unsigned Opcode) {
9713 return Opcode == FCOS;
9714}
9715
9716bool isXSAVES(unsigned Opcode) {
9717 return Opcode == XSAVES;
9718}
9719
9720bool isTZCNT(unsigned Opcode) {
9721 switch (Opcode) {
9722 case TZCNT16rm:
9723 case TZCNT16rm_EVEX:
9724 case TZCNT16rm_NF:
9725 case TZCNT16rr:
9726 case TZCNT16rr_EVEX:
9727 case TZCNT16rr_NF:
9728 case TZCNT32rm:
9729 case TZCNT32rm_EVEX:
9730 case TZCNT32rm_NF:
9731 case TZCNT32rr:
9732 case TZCNT32rr_EVEX:
9733 case TZCNT32rr_NF:
9734 case TZCNT64rm:
9735 case TZCNT64rm_EVEX:
9736 case TZCNT64rm_NF:
9737 case TZCNT64rr:
9738 case TZCNT64rr_EVEX:
9739 case TZCNT64rr_NF:
9740 return true;
9741 }
9742 return false;
9743}
9744
9745bool isLJMP(unsigned Opcode) {
9746 switch (Opcode) {
9747 case FARJMP16i:
9748 case FARJMP16m:
9749 case FARJMP32i:
9750 case FARJMP64m:
9751 return true;
9752 }
9753 return false;
9754}
9755
9756bool isCMOVCC(unsigned Opcode) {
9757 switch (Opcode) {
9758 case CMOV16rm:
9759 case CMOV16rm_ND:
9760 case CMOV16rr:
9761 case CMOV16rr_ND:
9762 case CMOV32rm:
9763 case CMOV32rm_ND:
9764 case CMOV32rr:
9765 case CMOV32rr_ND:
9766 case CMOV64rm:
9767 case CMOV64rm_ND:
9768 case CMOV64rr:
9769 case CMOV64rr_ND:
9770 return true;
9771 }
9772 return false;
9773}
9774
9775bool isVCVTBIASPH2HF8(unsigned Opcode) {
9776 switch (Opcode) {
9777 case VCVTBIASPH2HF8Z128rm:
9778 case VCVTBIASPH2HF8Z128rmb:
9779 case VCVTBIASPH2HF8Z128rmbk:
9780 case VCVTBIASPH2HF8Z128rmbkz:
9781 case VCVTBIASPH2HF8Z128rmk:
9782 case VCVTBIASPH2HF8Z128rmkz:
9783 case VCVTBIASPH2HF8Z128rr:
9784 case VCVTBIASPH2HF8Z128rrk:
9785 case VCVTBIASPH2HF8Z128rrkz:
9786 case VCVTBIASPH2HF8Z256rm:
9787 case VCVTBIASPH2HF8Z256rmb:
9788 case VCVTBIASPH2HF8Z256rmbk:
9789 case VCVTBIASPH2HF8Z256rmbkz:
9790 case VCVTBIASPH2HF8Z256rmk:
9791 case VCVTBIASPH2HF8Z256rmkz:
9792 case VCVTBIASPH2HF8Z256rr:
9793 case VCVTBIASPH2HF8Z256rrk:
9794 case VCVTBIASPH2HF8Z256rrkz:
9795 case VCVTBIASPH2HF8Zrm:
9796 case VCVTBIASPH2HF8Zrmb:
9797 case VCVTBIASPH2HF8Zrmbk:
9798 case VCVTBIASPH2HF8Zrmbkz:
9799 case VCVTBIASPH2HF8Zrmk:
9800 case VCVTBIASPH2HF8Zrmkz:
9801 case VCVTBIASPH2HF8Zrr:
9802 case VCVTBIASPH2HF8Zrrk:
9803 case VCVTBIASPH2HF8Zrrkz:
9804 return true;
9805 }
9806 return false;
9807}
9808
9809bool isINVEPT(unsigned Opcode) {
9810 switch (Opcode) {
9811 case INVEPT32:
9812 case INVEPT64:
9813 case INVEPT64_EVEX:
9814 return true;
9815 }
9816 return false;
9817}
9818
9819bool isADDSUBPD(unsigned Opcode) {
9820 switch (Opcode) {
9821 case ADDSUBPDrm:
9822 case ADDSUBPDrr:
9823 return true;
9824 }
9825 return false;
9826}
9827
9828bool isVCVTSS2SD(unsigned Opcode) {
9829 switch (Opcode) {
9830 case VCVTSS2SDZrm_Int:
9831 case VCVTSS2SDZrmk_Int:
9832 case VCVTSS2SDZrmkz_Int:
9833 case VCVTSS2SDZrr_Int:
9834 case VCVTSS2SDZrrb_Int:
9835 case VCVTSS2SDZrrbk_Int:
9836 case VCVTSS2SDZrrbkz_Int:
9837 case VCVTSS2SDZrrk_Int:
9838 case VCVTSS2SDZrrkz_Int:
9839 case VCVTSS2SDrm_Int:
9840 case VCVTSS2SDrr_Int:
9841 return true;
9842 }
9843 return false;
9844}
9845
9846bool isVMOVSHDUP(unsigned Opcode) {
9847 switch (Opcode) {
9848 case VMOVSHDUPYrm:
9849 case VMOVSHDUPYrr:
9850 case VMOVSHDUPZ128rm:
9851 case VMOVSHDUPZ128rmk:
9852 case VMOVSHDUPZ128rmkz:
9853 case VMOVSHDUPZ128rr:
9854 case VMOVSHDUPZ128rrk:
9855 case VMOVSHDUPZ128rrkz:
9856 case VMOVSHDUPZ256rm:
9857 case VMOVSHDUPZ256rmk:
9858 case VMOVSHDUPZ256rmkz:
9859 case VMOVSHDUPZ256rr:
9860 case VMOVSHDUPZ256rrk:
9861 case VMOVSHDUPZ256rrkz:
9862 case VMOVSHDUPZrm:
9863 case VMOVSHDUPZrmk:
9864 case VMOVSHDUPZrmkz:
9865 case VMOVSHDUPZrr:
9866 case VMOVSHDUPZrrk:
9867 case VMOVSHDUPZrrkz:
9868 case VMOVSHDUPrm:
9869 case VMOVSHDUPrr:
9870 return true;
9871 }
9872 return false;
9873}
9874
9875bool isKSHIFTRD(unsigned Opcode) {
9876 return Opcode == KSHIFTRDki;
9877}
9878
9879bool isVPTERNLOGD(unsigned Opcode) {
9880 switch (Opcode) {
9881 case VPTERNLOGDZ128rmbi:
9882 case VPTERNLOGDZ128rmbik:
9883 case VPTERNLOGDZ128rmbikz:
9884 case VPTERNLOGDZ128rmi:
9885 case VPTERNLOGDZ128rmik:
9886 case VPTERNLOGDZ128rmikz:
9887 case VPTERNLOGDZ128rri:
9888 case VPTERNLOGDZ128rrik:
9889 case VPTERNLOGDZ128rrikz:
9890 case VPTERNLOGDZ256rmbi:
9891 case VPTERNLOGDZ256rmbik:
9892 case VPTERNLOGDZ256rmbikz:
9893 case VPTERNLOGDZ256rmi:
9894 case VPTERNLOGDZ256rmik:
9895 case VPTERNLOGDZ256rmikz:
9896 case VPTERNLOGDZ256rri:
9897 case VPTERNLOGDZ256rrik:
9898 case VPTERNLOGDZ256rrikz:
9899 case VPTERNLOGDZrmbi:
9900 case VPTERNLOGDZrmbik:
9901 case VPTERNLOGDZrmbikz:
9902 case VPTERNLOGDZrmi:
9903 case VPTERNLOGDZrmik:
9904 case VPTERNLOGDZrmikz:
9905 case VPTERNLOGDZrri:
9906 case VPTERNLOGDZrrik:
9907 case VPTERNLOGDZrrikz:
9908 return true;
9909 }
9910 return false;
9911}
9912
9913bool isPADDQ(unsigned Opcode) {
9914 switch (Opcode) {
9915 case MMX_PADDQrm:
9916 case MMX_PADDQrr:
9917 case PADDQrm:
9918 case PADDQrr:
9919 return true;
9920 }
9921 return false;
9922}
9923
9924bool isVEXTRACTI64X4(unsigned Opcode) {
9925 switch (Opcode) {
9926 case VEXTRACTI64X4Zmri:
9927 case VEXTRACTI64X4Zmrik:
9928 case VEXTRACTI64X4Zrri:
9929 case VEXTRACTI64X4Zrrik:
9930 case VEXTRACTI64X4Zrrikz:
9931 return true;
9932 }
9933 return false;
9934}
9935
9936bool isVFMSUB231SS(unsigned Opcode) {
9937 switch (Opcode) {
9938 case VFMSUB231SSZm_Int:
9939 case VFMSUB231SSZmk_Int:
9940 case VFMSUB231SSZmkz_Int:
9941 case VFMSUB231SSZr_Int:
9942 case VFMSUB231SSZrb_Int:
9943 case VFMSUB231SSZrbk_Int:
9944 case VFMSUB231SSZrbkz_Int:
9945 case VFMSUB231SSZrk_Int:
9946 case VFMSUB231SSZrkz_Int:
9947 case VFMSUB231SSm_Int:
9948 case VFMSUB231SSr_Int:
9949 return true;
9950 }
9951 return false;
9952}
9953
9954bool isVPCMPEQB(unsigned Opcode) {
9955 switch (Opcode) {
9956 case VPCMPEQBYrm:
9957 case VPCMPEQBYrr:
9958 case VPCMPEQBZ128rm:
9959 case VPCMPEQBZ128rmk:
9960 case VPCMPEQBZ128rr:
9961 case VPCMPEQBZ128rrk:
9962 case VPCMPEQBZ256rm:
9963 case VPCMPEQBZ256rmk:
9964 case VPCMPEQBZ256rr:
9965 case VPCMPEQBZ256rrk:
9966 case VPCMPEQBZrm:
9967 case VPCMPEQBZrmk:
9968 case VPCMPEQBZrr:
9969 case VPCMPEQBZrrk:
9970 case VPCMPEQBrm:
9971 case VPCMPEQBrr:
9972 return true;
9973 }
9974 return false;
9975}
9976
9977bool isLEA(unsigned Opcode) {
9978 switch (Opcode) {
9979 case LEA16r:
9980 case LEA32r:
9981 case LEA64_32r:
9982 case LEA64r:
9983 return true;
9984 }
9985 return false;
9986}
9987
9988bool isPSUBB(unsigned Opcode) {
9989 switch (Opcode) {
9990 case MMX_PSUBBrm:
9991 case MMX_PSUBBrr:
9992 case PSUBBrm:
9993 case PSUBBrr:
9994 return true;
9995 }
9996 return false;
9997}
9998
9999bool isKADDQ(unsigned Opcode) {
10000 return Opcode == KADDQkk;
10001}
10002
10003bool isMOVSX(unsigned Opcode) {
10004 switch (Opcode) {
10005 case MOVSX16rm16:
10006 case MOVSX16rm8:
10007 case MOVSX16rr16:
10008 case MOVSX16rr8:
10009 case MOVSX32rm16:
10010 case MOVSX32rm8:
10011 case MOVSX32rr16:
10012 case MOVSX32rr8:
10013 case MOVSX64rm16:
10014 case MOVSX64rm8:
10015 case MOVSX64rr16:
10016 case MOVSX64rr8:
10017 return true;
10018 }
10019 return false;
10020}
10021
10022bool isVALIGNQ(unsigned Opcode) {
10023 switch (Opcode) {
10024 case VALIGNQZ128rmbi:
10025 case VALIGNQZ128rmbik:
10026 case VALIGNQZ128rmbikz:
10027 case VALIGNQZ128rmi:
10028 case VALIGNQZ128rmik:
10029 case VALIGNQZ128rmikz:
10030 case VALIGNQZ128rri:
10031 case VALIGNQZ128rrik:
10032 case VALIGNQZ128rrikz:
10033 case VALIGNQZ256rmbi:
10034 case VALIGNQZ256rmbik:
10035 case VALIGNQZ256rmbikz:
10036 case VALIGNQZ256rmi:
10037 case VALIGNQZ256rmik:
10038 case VALIGNQZ256rmikz:
10039 case VALIGNQZ256rri:
10040 case VALIGNQZ256rrik:
10041 case VALIGNQZ256rrikz:
10042 case VALIGNQZrmbi:
10043 case VALIGNQZrmbik:
10044 case VALIGNQZrmbikz:
10045 case VALIGNQZrmi:
10046 case VALIGNQZrmik:
10047 case VALIGNQZrmikz:
10048 case VALIGNQZrri:
10049 case VALIGNQZrrik:
10050 case VALIGNQZrrikz:
10051 return true;
10052 }
10053 return false;
10054}
10055
10056bool isVCVTNE2PS2BF16(unsigned Opcode) {
10057 switch (Opcode) {
10058 case VCVTNE2PS2BF16Z128rm:
10059 case VCVTNE2PS2BF16Z128rmb:
10060 case VCVTNE2PS2BF16Z128rmbk:
10061 case VCVTNE2PS2BF16Z128rmbkz:
10062 case VCVTNE2PS2BF16Z128rmk:
10063 case VCVTNE2PS2BF16Z128rmkz:
10064 case VCVTNE2PS2BF16Z128rr:
10065 case VCVTNE2PS2BF16Z128rrk:
10066 case VCVTNE2PS2BF16Z128rrkz:
10067 case VCVTNE2PS2BF16Z256rm:
10068 case VCVTNE2PS2BF16Z256rmb:
10069 case VCVTNE2PS2BF16Z256rmbk:
10070 case VCVTNE2PS2BF16Z256rmbkz:
10071 case VCVTNE2PS2BF16Z256rmk:
10072 case VCVTNE2PS2BF16Z256rmkz:
10073 case VCVTNE2PS2BF16Z256rr:
10074 case VCVTNE2PS2BF16Z256rrk:
10075 case VCVTNE2PS2BF16Z256rrkz:
10076 case VCVTNE2PS2BF16Zrm:
10077 case VCVTNE2PS2BF16Zrmb:
10078 case VCVTNE2PS2BF16Zrmbk:
10079 case VCVTNE2PS2BF16Zrmbkz:
10080 case VCVTNE2PS2BF16Zrmk:
10081 case VCVTNE2PS2BF16Zrmkz:
10082 case VCVTNE2PS2BF16Zrr:
10083 case VCVTNE2PS2BF16Zrrk:
10084 case VCVTNE2PS2BF16Zrrkz:
10085 return true;
10086 }
10087 return false;
10088}
10089
10090bool isVPSRAW(unsigned Opcode) {
10091 switch (Opcode) {
10092 case VPSRAWYri:
10093 case VPSRAWYrm:
10094 case VPSRAWYrr:
10095 case VPSRAWZ128mi:
10096 case VPSRAWZ128mik:
10097 case VPSRAWZ128mikz:
10098 case VPSRAWZ128ri:
10099 case VPSRAWZ128rik:
10100 case VPSRAWZ128rikz:
10101 case VPSRAWZ128rm:
10102 case VPSRAWZ128rmk:
10103 case VPSRAWZ128rmkz:
10104 case VPSRAWZ128rr:
10105 case VPSRAWZ128rrk:
10106 case VPSRAWZ128rrkz:
10107 case VPSRAWZ256mi:
10108 case VPSRAWZ256mik:
10109 case VPSRAWZ256mikz:
10110 case VPSRAWZ256ri:
10111 case VPSRAWZ256rik:
10112 case VPSRAWZ256rikz:
10113 case VPSRAWZ256rm:
10114 case VPSRAWZ256rmk:
10115 case VPSRAWZ256rmkz:
10116 case VPSRAWZ256rr:
10117 case VPSRAWZ256rrk:
10118 case VPSRAWZ256rrkz:
10119 case VPSRAWZmi:
10120 case VPSRAWZmik:
10121 case VPSRAWZmikz:
10122 case VPSRAWZri:
10123 case VPSRAWZrik:
10124 case VPSRAWZrikz:
10125 case VPSRAWZrm:
10126 case VPSRAWZrmk:
10127 case VPSRAWZrmkz:
10128 case VPSRAWZrr:
10129 case VPSRAWZrrk:
10130 case VPSRAWZrrkz:
10131 case VPSRAWri:
10132 case VPSRAWrm:
10133 case VPSRAWrr:
10134 return true;
10135 }
10136 return false;
10137}
10138
10139bool isVFMSUBADD231PH(unsigned Opcode) {
10140 switch (Opcode) {
10141 case VFMSUBADD231PHZ128m:
10142 case VFMSUBADD231PHZ128mb:
10143 case VFMSUBADD231PHZ128mbk:
10144 case VFMSUBADD231PHZ128mbkz:
10145 case VFMSUBADD231PHZ128mk:
10146 case VFMSUBADD231PHZ128mkz:
10147 case VFMSUBADD231PHZ128r:
10148 case VFMSUBADD231PHZ128rk:
10149 case VFMSUBADD231PHZ128rkz:
10150 case VFMSUBADD231PHZ256m:
10151 case VFMSUBADD231PHZ256mb:
10152 case VFMSUBADD231PHZ256mbk:
10153 case VFMSUBADD231PHZ256mbkz:
10154 case VFMSUBADD231PHZ256mk:
10155 case VFMSUBADD231PHZ256mkz:
10156 case VFMSUBADD231PHZ256r:
10157 case VFMSUBADD231PHZ256rk:
10158 case VFMSUBADD231PHZ256rkz:
10159 case VFMSUBADD231PHZm:
10160 case VFMSUBADD231PHZmb:
10161 case VFMSUBADD231PHZmbk:
10162 case VFMSUBADD231PHZmbkz:
10163 case VFMSUBADD231PHZmk:
10164 case VFMSUBADD231PHZmkz:
10165 case VFMSUBADD231PHZr:
10166 case VFMSUBADD231PHZrb:
10167 case VFMSUBADD231PHZrbk:
10168 case VFMSUBADD231PHZrbkz:
10169 case VFMSUBADD231PHZrk:
10170 case VFMSUBADD231PHZrkz:
10171 return true;
10172 }
10173 return false;
10174}
10175
10176bool isCVTDQ2PS(unsigned Opcode) {
10177 switch (Opcode) {
10178 case CVTDQ2PSrm:
10179 case CVTDQ2PSrr:
10180 return true;
10181 }
10182 return false;
10183}
10184
10185bool isFBLD(unsigned Opcode) {
10186 return Opcode == FBLDm;
10187}
10188
10189bool isLMSW(unsigned Opcode) {
10190 switch (Opcode) {
10191 case LMSW16m:
10192 case LMSW16r:
10193 return true;
10194 }
10195 return false;
10196}
10197
10198bool isVRNDSCALEPH(unsigned Opcode) {
10199 switch (Opcode) {
10200 case VRNDSCALEPHZ128rmbi:
10201 case VRNDSCALEPHZ128rmbik:
10202 case VRNDSCALEPHZ128rmbikz:
10203 case VRNDSCALEPHZ128rmi:
10204 case VRNDSCALEPHZ128rmik:
10205 case VRNDSCALEPHZ128rmikz:
10206 case VRNDSCALEPHZ128rri:
10207 case VRNDSCALEPHZ128rrik:
10208 case VRNDSCALEPHZ128rrikz:
10209 case VRNDSCALEPHZ256rmbi:
10210 case VRNDSCALEPHZ256rmbik:
10211 case VRNDSCALEPHZ256rmbikz:
10212 case VRNDSCALEPHZ256rmi:
10213 case VRNDSCALEPHZ256rmik:
10214 case VRNDSCALEPHZ256rmikz:
10215 case VRNDSCALEPHZ256rri:
10216 case VRNDSCALEPHZ256rrik:
10217 case VRNDSCALEPHZ256rrikz:
10218 case VRNDSCALEPHZrmbi:
10219 case VRNDSCALEPHZrmbik:
10220 case VRNDSCALEPHZrmbikz:
10221 case VRNDSCALEPHZrmi:
10222 case VRNDSCALEPHZrmik:
10223 case VRNDSCALEPHZrmikz:
10224 case VRNDSCALEPHZrri:
10225 case VRNDSCALEPHZrrib:
10226 case VRNDSCALEPHZrribk:
10227 case VRNDSCALEPHZrribkz:
10228 case VRNDSCALEPHZrrik:
10229 case VRNDSCALEPHZrrikz:
10230 return true;
10231 }
10232 return false;
10233}
10234
10235bool isMINSS(unsigned Opcode) {
10236 switch (Opcode) {
10237 case MINSSrm_Int:
10238 case MINSSrr_Int:
10239 return true;
10240 }
10241 return false;
10242}
10243
10244bool isWRMSR(unsigned Opcode) {
10245 return Opcode == WRMSR;
10246}
10247
10248bool isFSCALE(unsigned Opcode) {
10249 return Opcode == FSCALE;
10250}
10251
10252bool isVFNMADD213SH(unsigned Opcode) {
10253 switch (Opcode) {
10254 case VFNMADD213SHZm_Int:
10255 case VFNMADD213SHZmk_Int:
10256 case VFNMADD213SHZmkz_Int:
10257 case VFNMADD213SHZr_Int:
10258 case VFNMADD213SHZrb_Int:
10259 case VFNMADD213SHZrbk_Int:
10260 case VFNMADD213SHZrbkz_Int:
10261 case VFNMADD213SHZrk_Int:
10262 case VFNMADD213SHZrkz_Int:
10263 return true;
10264 }
10265 return false;
10266}
10267
10268bool isIMULZU(unsigned Opcode) {
10269 switch (Opcode) {
10270 case IMULZU16rmi:
10271 case IMULZU16rmi8:
10272 case IMULZU16rri:
10273 case IMULZU16rri8:
10274 case IMULZU32rmi:
10275 case IMULZU32rmi8:
10276 case IMULZU32rri:
10277 case IMULZU32rri8:
10278 case IMULZU64rmi32:
10279 case IMULZU64rmi8:
10280 case IMULZU64rri32:
10281 case IMULZU64rri8:
10282 return true;
10283 }
10284 return false;
10285}
10286
10287bool isVPHADDUBD(unsigned Opcode) {
10288 switch (Opcode) {
10289 case VPHADDUBDrm:
10290 case VPHADDUBDrr:
10291 return true;
10292 }
10293 return false;
10294}
10295
10296bool isRDSSPQ(unsigned Opcode) {
10297 return Opcode == RDSSPQ;
10298}
10299
10300bool isVCVTBF162IBS(unsigned Opcode) {
10301 switch (Opcode) {
10302 case VCVTBF162IBSZ128rm:
10303 case VCVTBF162IBSZ128rmb:
10304 case VCVTBF162IBSZ128rmbk:
10305 case VCVTBF162IBSZ128rmbkz:
10306 case VCVTBF162IBSZ128rmk:
10307 case VCVTBF162IBSZ128rmkz:
10308 case VCVTBF162IBSZ128rr:
10309 case VCVTBF162IBSZ128rrk:
10310 case VCVTBF162IBSZ128rrkz:
10311 case VCVTBF162IBSZ256rm:
10312 case VCVTBF162IBSZ256rmb:
10313 case VCVTBF162IBSZ256rmbk:
10314 case VCVTBF162IBSZ256rmbkz:
10315 case VCVTBF162IBSZ256rmk:
10316 case VCVTBF162IBSZ256rmkz:
10317 case VCVTBF162IBSZ256rr:
10318 case VCVTBF162IBSZ256rrk:
10319 case VCVTBF162IBSZ256rrkz:
10320 case VCVTBF162IBSZrm:
10321 case VCVTBF162IBSZrmb:
10322 case VCVTBF162IBSZrmbk:
10323 case VCVTBF162IBSZrmbkz:
10324 case VCVTBF162IBSZrmk:
10325 case VCVTBF162IBSZrmkz:
10326 case VCVTBF162IBSZrr:
10327 case VCVTBF162IBSZrrk:
10328 case VCVTBF162IBSZrrkz:
10329 return true;
10330 }
10331 return false;
10332}
10333
10334bool isLGDT(unsigned Opcode) {
10335 return Opcode == LGDT64m;
10336}
10337
10338bool isVPSHLDVD(unsigned Opcode) {
10339 switch (Opcode) {
10340 case VPSHLDVDZ128m:
10341 case VPSHLDVDZ128mb:
10342 case VPSHLDVDZ128mbk:
10343 case VPSHLDVDZ128mbkz:
10344 case VPSHLDVDZ128mk:
10345 case VPSHLDVDZ128mkz:
10346 case VPSHLDVDZ128r:
10347 case VPSHLDVDZ128rk:
10348 case VPSHLDVDZ128rkz:
10349 case VPSHLDVDZ256m:
10350 case VPSHLDVDZ256mb:
10351 case VPSHLDVDZ256mbk:
10352 case VPSHLDVDZ256mbkz:
10353 case VPSHLDVDZ256mk:
10354 case VPSHLDVDZ256mkz:
10355 case VPSHLDVDZ256r:
10356 case VPSHLDVDZ256rk:
10357 case VPSHLDVDZ256rkz:
10358 case VPSHLDVDZm:
10359 case VPSHLDVDZmb:
10360 case VPSHLDVDZmbk:
10361 case VPSHLDVDZmbkz:
10362 case VPSHLDVDZmk:
10363 case VPSHLDVDZmkz:
10364 case VPSHLDVDZr:
10365 case VPSHLDVDZrk:
10366 case VPSHLDVDZrkz:
10367 return true;
10368 }
10369 return false;
10370}
10371
10372bool isPFCMPGT(unsigned Opcode) {
10373 switch (Opcode) {
10374 case PFCMPGTrm:
10375 case PFCMPGTrr:
10376 return true;
10377 }
10378 return false;
10379}
10380
10381bool isJCXZ(unsigned Opcode) {
10382 return Opcode == JCXZ;
10383}
10384
10385bool isVPMOVZXBW(unsigned Opcode) {
10386 switch (Opcode) {
10387 case VPMOVZXBWYrm:
10388 case VPMOVZXBWYrr:
10389 case VPMOVZXBWZ128rm:
10390 case VPMOVZXBWZ128rmk:
10391 case VPMOVZXBWZ128rmkz:
10392 case VPMOVZXBWZ128rr:
10393 case VPMOVZXBWZ128rrk:
10394 case VPMOVZXBWZ128rrkz:
10395 case VPMOVZXBWZ256rm:
10396 case VPMOVZXBWZ256rmk:
10397 case VPMOVZXBWZ256rmkz:
10398 case VPMOVZXBWZ256rr:
10399 case VPMOVZXBWZ256rrk:
10400 case VPMOVZXBWZ256rrkz:
10401 case VPMOVZXBWZrm:
10402 case VPMOVZXBWZrmk:
10403 case VPMOVZXBWZrmkz:
10404 case VPMOVZXBWZrr:
10405 case VPMOVZXBWZrrk:
10406 case VPMOVZXBWZrrkz:
10407 case VPMOVZXBWrm:
10408 case VPMOVZXBWrr:
10409 return true;
10410 }
10411 return false;
10412}
10413
10414bool isVFMADDSUB231PD(unsigned Opcode) {
10415 switch (Opcode) {
10416 case VFMADDSUB231PDYm:
10417 case VFMADDSUB231PDYr:
10418 case VFMADDSUB231PDZ128m:
10419 case VFMADDSUB231PDZ128mb:
10420 case VFMADDSUB231PDZ128mbk:
10421 case VFMADDSUB231PDZ128mbkz:
10422 case VFMADDSUB231PDZ128mk:
10423 case VFMADDSUB231PDZ128mkz:
10424 case VFMADDSUB231PDZ128r:
10425 case VFMADDSUB231PDZ128rk:
10426 case VFMADDSUB231PDZ128rkz:
10427 case VFMADDSUB231PDZ256m:
10428 case VFMADDSUB231PDZ256mb:
10429 case VFMADDSUB231PDZ256mbk:
10430 case VFMADDSUB231PDZ256mbkz:
10431 case VFMADDSUB231PDZ256mk:
10432 case VFMADDSUB231PDZ256mkz:
10433 case VFMADDSUB231PDZ256r:
10434 case VFMADDSUB231PDZ256rk:
10435 case VFMADDSUB231PDZ256rkz:
10436 case VFMADDSUB231PDZm:
10437 case VFMADDSUB231PDZmb:
10438 case VFMADDSUB231PDZmbk:
10439 case VFMADDSUB231PDZmbkz:
10440 case VFMADDSUB231PDZmk:
10441 case VFMADDSUB231PDZmkz:
10442 case VFMADDSUB231PDZr:
10443 case VFMADDSUB231PDZrb:
10444 case VFMADDSUB231PDZrbk:
10445 case VFMADDSUB231PDZrbkz:
10446 case VFMADDSUB231PDZrk:
10447 case VFMADDSUB231PDZrkz:
10448 case VFMADDSUB231PDm:
10449 case VFMADDSUB231PDr:
10450 return true;
10451 }
10452 return false;
10453}
10454
10455bool isVBLENDMPD(unsigned Opcode) {
10456 switch (Opcode) {
10457 case VBLENDMPDZ128rm:
10458 case VBLENDMPDZ128rmb:
10459 case VBLENDMPDZ128rmbk:
10460 case VBLENDMPDZ128rmbkz:
10461 case VBLENDMPDZ128rmk:
10462 case VBLENDMPDZ128rmkz:
10463 case VBLENDMPDZ128rr:
10464 case VBLENDMPDZ128rrk:
10465 case VBLENDMPDZ128rrkz:
10466 case VBLENDMPDZ256rm:
10467 case VBLENDMPDZ256rmb:
10468 case VBLENDMPDZ256rmbk:
10469 case VBLENDMPDZ256rmbkz:
10470 case VBLENDMPDZ256rmk:
10471 case VBLENDMPDZ256rmkz:
10472 case VBLENDMPDZ256rr:
10473 case VBLENDMPDZ256rrk:
10474 case VBLENDMPDZ256rrkz:
10475 case VBLENDMPDZrm:
10476 case VBLENDMPDZrmb:
10477 case VBLENDMPDZrmbk:
10478 case VBLENDMPDZrmbkz:
10479 case VBLENDMPDZrmk:
10480 case VBLENDMPDZrmkz:
10481 case VBLENDMPDZrr:
10482 case VBLENDMPDZrrk:
10483 case VBLENDMPDZrrkz:
10484 return true;
10485 }
10486 return false;
10487}
10488
10489bool isHSUBPS(unsigned Opcode) {
10490 switch (Opcode) {
10491 case HSUBPSrm:
10492 case HSUBPSrr:
10493 return true;
10494 }
10495 return false;
10496}
10497
10498bool isPREFETCHIT0(unsigned Opcode) {
10499 return Opcode == PREFETCHIT0;
10500}
10501
10502bool isKTESTD(unsigned Opcode) {
10503 return Opcode == KTESTDkk;
10504}
10505
10506bool isVCVTNEOPH2PS(unsigned Opcode) {
10507 switch (Opcode) {
10508 case VCVTNEOPH2PSYrm:
10509 case VCVTNEOPH2PSrm:
10510 return true;
10511 }
10512 return false;
10513}
10514
10515bool isVBLENDVPD(unsigned Opcode) {
10516 switch (Opcode) {
10517 case VBLENDVPDYrmr:
10518 case VBLENDVPDYrrr:
10519 case VBLENDVPDrmr:
10520 case VBLENDVPDrrr:
10521 return true;
10522 }
10523 return false;
10524}
10525
10526bool isVCVTSS2USI(unsigned Opcode) {
10527 switch (Opcode) {
10528 case VCVTSS2USI64Zrm_Int:
10529 case VCVTSS2USI64Zrr_Int:
10530 case VCVTSS2USI64Zrrb_Int:
10531 case VCVTSS2USIZrm_Int:
10532 case VCVTSS2USIZrr_Int:
10533 case VCVTSS2USIZrrb_Int:
10534 return true;
10535 }
10536 return false;
10537}
10538
10539bool isVCVTTPS2DQS(unsigned Opcode) {
10540 switch (Opcode) {
10541 case VCVTTPS2DQSZ128rm:
10542 case VCVTTPS2DQSZ128rmb:
10543 case VCVTTPS2DQSZ128rmbk:
10544 case VCVTTPS2DQSZ128rmbkz:
10545 case VCVTTPS2DQSZ128rmk:
10546 case VCVTTPS2DQSZ128rmkz:
10547 case VCVTTPS2DQSZ128rr:
10548 case VCVTTPS2DQSZ128rrk:
10549 case VCVTTPS2DQSZ128rrkz:
10550 case VCVTTPS2DQSZ256rm:
10551 case VCVTTPS2DQSZ256rmb:
10552 case VCVTTPS2DQSZ256rmbk:
10553 case VCVTTPS2DQSZ256rmbkz:
10554 case VCVTTPS2DQSZ256rmk:
10555 case VCVTTPS2DQSZ256rmkz:
10556 case VCVTTPS2DQSZ256rr:
10557 case VCVTTPS2DQSZ256rrk:
10558 case VCVTTPS2DQSZ256rrkz:
10559 case VCVTTPS2DQSZrm:
10560 case VCVTTPS2DQSZrmb:
10561 case VCVTTPS2DQSZrmbk:
10562 case VCVTTPS2DQSZrmbkz:
10563 case VCVTTPS2DQSZrmk:
10564 case VCVTTPS2DQSZrmkz:
10565 case VCVTTPS2DQSZrr:
10566 case VCVTTPS2DQSZrrb:
10567 case VCVTTPS2DQSZrrbk:
10568 case VCVTTPS2DQSZrrbkz:
10569 case VCVTTPS2DQSZrrk:
10570 case VCVTTPS2DQSZrrkz:
10571 return true;
10572 }
10573 return false;
10574}
10575
10576bool isVPANDD(unsigned Opcode) {
10577 switch (Opcode) {
10578 case VPANDDZ128rm:
10579 case VPANDDZ128rmb:
10580 case VPANDDZ128rmbk:
10581 case VPANDDZ128rmbkz:
10582 case VPANDDZ128rmk:
10583 case VPANDDZ128rmkz:
10584 case VPANDDZ128rr:
10585 case VPANDDZ128rrk:
10586 case VPANDDZ128rrkz:
10587 case VPANDDZ256rm:
10588 case VPANDDZ256rmb:
10589 case VPANDDZ256rmbk:
10590 case VPANDDZ256rmbkz:
10591 case VPANDDZ256rmk:
10592 case VPANDDZ256rmkz:
10593 case VPANDDZ256rr:
10594 case VPANDDZ256rrk:
10595 case VPANDDZ256rrkz:
10596 case VPANDDZrm:
10597 case VPANDDZrmb:
10598 case VPANDDZrmbk:
10599 case VPANDDZrmbkz:
10600 case VPANDDZrmk:
10601 case VPANDDZrmkz:
10602 case VPANDDZrr:
10603 case VPANDDZrrk:
10604 case VPANDDZrrkz:
10605 return true;
10606 }
10607 return false;
10608}
10609
10610bool isPMINSW(unsigned Opcode) {
10611 switch (Opcode) {
10612 case MMX_PMINSWrm:
10613 case MMX_PMINSWrr:
10614 case PMINSWrm:
10615 case PMINSWrr:
10616 return true;
10617 }
10618 return false;
10619}
10620
10621bool isSTAC(unsigned Opcode) {
10622 return Opcode == STAC;
10623}
10624
10625bool isVFMSUB213PS(unsigned Opcode) {
10626 switch (Opcode) {
10627 case VFMSUB213PSYm:
10628 case VFMSUB213PSYr:
10629 case VFMSUB213PSZ128m:
10630 case VFMSUB213PSZ128mb:
10631 case VFMSUB213PSZ128mbk:
10632 case VFMSUB213PSZ128mbkz:
10633 case VFMSUB213PSZ128mk:
10634 case VFMSUB213PSZ128mkz:
10635 case VFMSUB213PSZ128r:
10636 case VFMSUB213PSZ128rk:
10637 case VFMSUB213PSZ128rkz:
10638 case VFMSUB213PSZ256m:
10639 case VFMSUB213PSZ256mb:
10640 case VFMSUB213PSZ256mbk:
10641 case VFMSUB213PSZ256mbkz:
10642 case VFMSUB213PSZ256mk:
10643 case VFMSUB213PSZ256mkz:
10644 case VFMSUB213PSZ256r:
10645 case VFMSUB213PSZ256rk:
10646 case VFMSUB213PSZ256rkz:
10647 case VFMSUB213PSZm:
10648 case VFMSUB213PSZmb:
10649 case VFMSUB213PSZmbk:
10650 case VFMSUB213PSZmbkz:
10651 case VFMSUB213PSZmk:
10652 case VFMSUB213PSZmkz:
10653 case VFMSUB213PSZr:
10654 case VFMSUB213PSZrb:
10655 case VFMSUB213PSZrbk:
10656 case VFMSUB213PSZrbkz:
10657 case VFMSUB213PSZrk:
10658 case VFMSUB213PSZrkz:
10659 case VFMSUB213PSm:
10660 case VFMSUB213PSr:
10661 return true;
10662 }
10663 return false;
10664}
10665
10666bool isPOPAL(unsigned Opcode) {
10667 return Opcode == POPA32;
10668}
10669
10670bool isVCVTPS2UQQ(unsigned Opcode) {
10671 switch (Opcode) {
10672 case VCVTPS2UQQZ128rm:
10673 case VCVTPS2UQQZ128rmb:
10674 case VCVTPS2UQQZ128rmbk:
10675 case VCVTPS2UQQZ128rmbkz:
10676 case VCVTPS2UQQZ128rmk:
10677 case VCVTPS2UQQZ128rmkz:
10678 case VCVTPS2UQQZ128rr:
10679 case VCVTPS2UQQZ128rrk:
10680 case VCVTPS2UQQZ128rrkz:
10681 case VCVTPS2UQQZ256rm:
10682 case VCVTPS2UQQZ256rmb:
10683 case VCVTPS2UQQZ256rmbk:
10684 case VCVTPS2UQQZ256rmbkz:
10685 case VCVTPS2UQQZ256rmk:
10686 case VCVTPS2UQQZ256rmkz:
10687 case VCVTPS2UQQZ256rr:
10688 case VCVTPS2UQQZ256rrk:
10689 case VCVTPS2UQQZ256rrkz:
10690 case VCVTPS2UQQZrm:
10691 case VCVTPS2UQQZrmb:
10692 case VCVTPS2UQQZrmbk:
10693 case VCVTPS2UQQZrmbkz:
10694 case VCVTPS2UQQZrmk:
10695 case VCVTPS2UQQZrmkz:
10696 case VCVTPS2UQQZrr:
10697 case VCVTPS2UQQZrrb:
10698 case VCVTPS2UQQZrrbk:
10699 case VCVTPS2UQQZrrbkz:
10700 case VCVTPS2UQQZrrk:
10701 case VCVTPS2UQQZrrkz:
10702 return true;
10703 }
10704 return false;
10705}
10706
10707bool isRDRAND(unsigned Opcode) {
10708 switch (Opcode) {
10709 case RDRAND16r:
10710 case RDRAND32r:
10711 case RDRAND64r:
10712 return true;
10713 }
10714 return false;
10715}
10716
10717bool isJCC(unsigned Opcode) {
10718 switch (Opcode) {
10719 case JCC_1:
10720 case JCC_2:
10721 case JCC_4:
10722 return true;
10723 }
10724 return false;
10725}
10726
10727bool isVPMINSQ(unsigned Opcode) {
10728 switch (Opcode) {
10729 case VPMINSQZ128rm:
10730 case VPMINSQZ128rmb:
10731 case VPMINSQZ128rmbk:
10732 case VPMINSQZ128rmbkz:
10733 case VPMINSQZ128rmk:
10734 case VPMINSQZ128rmkz:
10735 case VPMINSQZ128rr:
10736 case VPMINSQZ128rrk:
10737 case VPMINSQZ128rrkz:
10738 case VPMINSQZ256rm:
10739 case VPMINSQZ256rmb:
10740 case VPMINSQZ256rmbk:
10741 case VPMINSQZ256rmbkz:
10742 case VPMINSQZ256rmk:
10743 case VPMINSQZ256rmkz:
10744 case VPMINSQZ256rr:
10745 case VPMINSQZ256rrk:
10746 case VPMINSQZ256rrkz:
10747 case VPMINSQZrm:
10748 case VPMINSQZrmb:
10749 case VPMINSQZrmbk:
10750 case VPMINSQZrmbkz:
10751 case VPMINSQZrmk:
10752 case VPMINSQZrmkz:
10753 case VPMINSQZrr:
10754 case VPMINSQZrrk:
10755 case VPMINSQZrrkz:
10756 return true;
10757 }
10758 return false;
10759}
10760
10761bool isVADDSD(unsigned Opcode) {
10762 switch (Opcode) {
10763 case VADDSDZrm_Int:
10764 case VADDSDZrmk_Int:
10765 case VADDSDZrmkz_Int:
10766 case VADDSDZrr_Int:
10767 case VADDSDZrrb_Int:
10768 case VADDSDZrrbk_Int:
10769 case VADDSDZrrbkz_Int:
10770 case VADDSDZrrk_Int:
10771 case VADDSDZrrkz_Int:
10772 case VADDSDrm_Int:
10773 case VADDSDrr_Int:
10774 return true;
10775 }
10776 return false;
10777}
10778
10779bool isDPPS(unsigned Opcode) {
10780 switch (Opcode) {
10781 case DPPSrmi:
10782 case DPPSrri:
10783 return true;
10784 }
10785 return false;
10786}
10787
10788bool isPINSRQ(unsigned Opcode) {
10789 switch (Opcode) {
10790 case PINSRQrmi:
10791 case PINSRQrri:
10792 return true;
10793 }
10794 return false;
10795}
10796
10797bool isVUCOMISS(unsigned Opcode) {
10798 switch (Opcode) {
10799 case VUCOMISSZrm:
10800 case VUCOMISSZrr:
10801 case VUCOMISSZrrb:
10802 case VUCOMISSrm:
10803 case VUCOMISSrr:
10804 return true;
10805 }
10806 return false;
10807}
10808
10809bool isVPDPWSUD(unsigned Opcode) {
10810 switch (Opcode) {
10811 case VPDPWSUDYrm:
10812 case VPDPWSUDYrr:
10813 case VPDPWSUDZ128rm:
10814 case VPDPWSUDZ128rmb:
10815 case VPDPWSUDZ128rmbk:
10816 case VPDPWSUDZ128rmbkz:
10817 case VPDPWSUDZ128rmk:
10818 case VPDPWSUDZ128rmkz:
10819 case VPDPWSUDZ128rr:
10820 case VPDPWSUDZ128rrk:
10821 case VPDPWSUDZ128rrkz:
10822 case VPDPWSUDZ256rm:
10823 case VPDPWSUDZ256rmb:
10824 case VPDPWSUDZ256rmbk:
10825 case VPDPWSUDZ256rmbkz:
10826 case VPDPWSUDZ256rmk:
10827 case VPDPWSUDZ256rmkz:
10828 case VPDPWSUDZ256rr:
10829 case VPDPWSUDZ256rrk:
10830 case VPDPWSUDZ256rrkz:
10831 case VPDPWSUDZrm:
10832 case VPDPWSUDZrmb:
10833 case VPDPWSUDZrmbk:
10834 case VPDPWSUDZrmbkz:
10835 case VPDPWSUDZrmk:
10836 case VPDPWSUDZrmkz:
10837 case VPDPWSUDZrr:
10838 case VPDPWSUDZrrk:
10839 case VPDPWSUDZrrkz:
10840 case VPDPWSUDrm:
10841 case VPDPWSUDrr:
10842 return true;
10843 }
10844 return false;
10845}
10846
10847bool isKANDNW(unsigned Opcode) {
10848 return Opcode == KANDNWkk;
10849}
10850
10851bool isAOR(unsigned Opcode) {
10852 switch (Opcode) {
10853 case AOR32mr:
10854 case AOR32mr_EVEX:
10855 case AOR64mr:
10856 case AOR64mr_EVEX:
10857 return true;
10858 }
10859 return false;
10860}
10861
10862bool isPMAXUB(unsigned Opcode) {
10863 switch (Opcode) {
10864 case MMX_PMAXUBrm:
10865 case MMX_PMAXUBrr:
10866 case PMAXUBrm:
10867 case PMAXUBrr:
10868 return true;
10869 }
10870 return false;
10871}
10872
10873bool isANDNPD(unsigned Opcode) {
10874 switch (Opcode) {
10875 case ANDNPDrm:
10876 case ANDNPDrr:
10877 return true;
10878 }
10879 return false;
10880}
10881
10882bool isINVPCID(unsigned Opcode) {
10883 switch (Opcode) {
10884 case INVPCID32:
10885 case INVPCID64:
10886 case INVPCID64_EVEX:
10887 return true;
10888 }
10889 return false;
10890}
10891
10892bool isRDGSBASE(unsigned Opcode) {
10893 switch (Opcode) {
10894 case RDGSBASE:
10895 case RDGSBASE64:
10896 return true;
10897 }
10898 return false;
10899}
10900
10901bool isVPMOVSQD(unsigned Opcode) {
10902 switch (Opcode) {
10903 case VPMOVSQDZ128mr:
10904 case VPMOVSQDZ128mrk:
10905 case VPMOVSQDZ128rr:
10906 case VPMOVSQDZ128rrk:
10907 case VPMOVSQDZ128rrkz:
10908 case VPMOVSQDZ256mr:
10909 case VPMOVSQDZ256mrk:
10910 case VPMOVSQDZ256rr:
10911 case VPMOVSQDZ256rrk:
10912 case VPMOVSQDZ256rrkz:
10913 case VPMOVSQDZmr:
10914 case VPMOVSQDZmrk:
10915 case VPMOVSQDZrr:
10916 case VPMOVSQDZrrk:
10917 case VPMOVSQDZrrkz:
10918 return true;
10919 }
10920 return false;
10921}
10922
10923bool isBT(unsigned Opcode) {
10924 switch (Opcode) {
10925 case BT16mi8:
10926 case BT16mr:
10927 case BT16ri8:
10928 case BT16rr:
10929 case BT32mi8:
10930 case BT32mr:
10931 case BT32ri8:
10932 case BT32rr:
10933 case BT64mi8:
10934 case BT64mr:
10935 case BT64ri8:
10936 case BT64rr:
10937 return true;
10938 }
10939 return false;
10940}
10941
10942bool isVPROLVQ(unsigned Opcode) {
10943 switch (Opcode) {
10944 case VPROLVQZ128rm:
10945 case VPROLVQZ128rmb:
10946 case VPROLVQZ128rmbk:
10947 case VPROLVQZ128rmbkz:
10948 case VPROLVQZ128rmk:
10949 case VPROLVQZ128rmkz:
10950 case VPROLVQZ128rr:
10951 case VPROLVQZ128rrk:
10952 case VPROLVQZ128rrkz:
10953 case VPROLVQZ256rm:
10954 case VPROLVQZ256rmb:
10955 case VPROLVQZ256rmbk:
10956 case VPROLVQZ256rmbkz:
10957 case VPROLVQZ256rmk:
10958 case VPROLVQZ256rmkz:
10959 case VPROLVQZ256rr:
10960 case VPROLVQZ256rrk:
10961 case VPROLVQZ256rrkz:
10962 case VPROLVQZrm:
10963 case VPROLVQZrmb:
10964 case VPROLVQZrmbk:
10965 case VPROLVQZrmbkz:
10966 case VPROLVQZrmk:
10967 case VPROLVQZrmkz:
10968 case VPROLVQZrr:
10969 case VPROLVQZrrk:
10970 case VPROLVQZrrkz:
10971 return true;
10972 }
10973 return false;
10974}
10975
10976bool isVFMADDSUB132PD(unsigned Opcode) {
10977 switch (Opcode) {
10978 case VFMADDSUB132PDYm:
10979 case VFMADDSUB132PDYr:
10980 case VFMADDSUB132PDZ128m:
10981 case VFMADDSUB132PDZ128mb:
10982 case VFMADDSUB132PDZ128mbk:
10983 case VFMADDSUB132PDZ128mbkz:
10984 case VFMADDSUB132PDZ128mk:
10985 case VFMADDSUB132PDZ128mkz:
10986 case VFMADDSUB132PDZ128r:
10987 case VFMADDSUB132PDZ128rk:
10988 case VFMADDSUB132PDZ128rkz:
10989 case VFMADDSUB132PDZ256m:
10990 case VFMADDSUB132PDZ256mb:
10991 case VFMADDSUB132PDZ256mbk:
10992 case VFMADDSUB132PDZ256mbkz:
10993 case VFMADDSUB132PDZ256mk:
10994 case VFMADDSUB132PDZ256mkz:
10995 case VFMADDSUB132PDZ256r:
10996 case VFMADDSUB132PDZ256rk:
10997 case VFMADDSUB132PDZ256rkz:
10998 case VFMADDSUB132PDZm:
10999 case VFMADDSUB132PDZmb:
11000 case VFMADDSUB132PDZmbk:
11001 case VFMADDSUB132PDZmbkz:
11002 case VFMADDSUB132PDZmk:
11003 case VFMADDSUB132PDZmkz:
11004 case VFMADDSUB132PDZr:
11005 case VFMADDSUB132PDZrb:
11006 case VFMADDSUB132PDZrbk:
11007 case VFMADDSUB132PDZrbkz:
11008 case VFMADDSUB132PDZrk:
11009 case VFMADDSUB132PDZrkz:
11010 case VFMADDSUB132PDm:
11011 case VFMADDSUB132PDr:
11012 return true;
11013 }
11014 return false;
11015}
11016
11017bool isRORX(unsigned Opcode) {
11018 switch (Opcode) {
11019 case RORX32mi:
11020 case RORX32mi_EVEX:
11021 case RORX32ri:
11022 case RORX32ri_EVEX:
11023 case RORX64mi:
11024 case RORX64mi_EVEX:
11025 case RORX64ri:
11026 case RORX64ri_EVEX:
11027 return true;
11028 }
11029 return false;
11030}
11031
11032bool isPADDUSW(unsigned Opcode) {
11033 switch (Opcode) {
11034 case MMX_PADDUSWrm:
11035 case MMX_PADDUSWrr:
11036 case PADDUSWrm:
11037 case PADDUSWrr:
11038 return true;
11039 }
11040 return false;
11041}
11042
11043bool isPFNACC(unsigned Opcode) {
11044 switch (Opcode) {
11045 case PFNACCrm:
11046 case PFNACCrr:
11047 return true;
11048 }
11049 return false;
11050}
11051
11052bool isAND(unsigned Opcode) {
11053 switch (Opcode) {
11054 case AND16i16:
11055 case AND16mi:
11056 case AND16mi8:
11057 case AND16mi8_EVEX:
11058 case AND16mi8_ND:
11059 case AND16mi8_NF:
11060 case AND16mi8_NF_ND:
11061 case AND16mi_EVEX:
11062 case AND16mi_ND:
11063 case AND16mi_NF:
11064 case AND16mi_NF_ND:
11065 case AND16mr:
11066 case AND16mr_EVEX:
11067 case AND16mr_ND:
11068 case AND16mr_NF:
11069 case AND16mr_NF_ND:
11070 case AND16ri:
11071 case AND16ri8:
11072 case AND16ri8_EVEX:
11073 case AND16ri8_ND:
11074 case AND16ri8_NF:
11075 case AND16ri8_NF_ND:
11076 case AND16ri_EVEX:
11077 case AND16ri_ND:
11078 case AND16ri_NF:
11079 case AND16ri_NF_ND:
11080 case AND16rm:
11081 case AND16rm_EVEX:
11082 case AND16rm_ND:
11083 case AND16rm_NF:
11084 case AND16rm_NF_ND:
11085 case AND16rr:
11086 case AND16rr_EVEX:
11087 case AND16rr_EVEX_REV:
11088 case AND16rr_ND:
11089 case AND16rr_ND_REV:
11090 case AND16rr_NF:
11091 case AND16rr_NF_ND:
11092 case AND16rr_NF_ND_REV:
11093 case AND16rr_NF_REV:
11094 case AND16rr_REV:
11095 case AND32i32:
11096 case AND32mi:
11097 case AND32mi8:
11098 case AND32mi8_EVEX:
11099 case AND32mi8_ND:
11100 case AND32mi8_NF:
11101 case AND32mi8_NF_ND:
11102 case AND32mi_EVEX:
11103 case AND32mi_ND:
11104 case AND32mi_NF:
11105 case AND32mi_NF_ND:
11106 case AND32mr:
11107 case AND32mr_EVEX:
11108 case AND32mr_ND:
11109 case AND32mr_NF:
11110 case AND32mr_NF_ND:
11111 case AND32ri:
11112 case AND32ri8:
11113 case AND32ri8_EVEX:
11114 case AND32ri8_ND:
11115 case AND32ri8_NF:
11116 case AND32ri8_NF_ND:
11117 case AND32ri_EVEX:
11118 case AND32ri_ND:
11119 case AND32ri_NF:
11120 case AND32ri_NF_ND:
11121 case AND32rm:
11122 case AND32rm_EVEX:
11123 case AND32rm_ND:
11124 case AND32rm_NF:
11125 case AND32rm_NF_ND:
11126 case AND32rr:
11127 case AND32rr_EVEX:
11128 case AND32rr_EVEX_REV:
11129 case AND32rr_ND:
11130 case AND32rr_ND_REV:
11131 case AND32rr_NF:
11132 case AND32rr_NF_ND:
11133 case AND32rr_NF_ND_REV:
11134 case AND32rr_NF_REV:
11135 case AND32rr_REV:
11136 case AND64i32:
11137 case AND64mi32:
11138 case AND64mi32_EVEX:
11139 case AND64mi32_ND:
11140 case AND64mi32_NF:
11141 case AND64mi32_NF_ND:
11142 case AND64mi8:
11143 case AND64mi8_EVEX:
11144 case AND64mi8_ND:
11145 case AND64mi8_NF:
11146 case AND64mi8_NF_ND:
11147 case AND64mr:
11148 case AND64mr_EVEX:
11149 case AND64mr_ND:
11150 case AND64mr_NF:
11151 case AND64mr_NF_ND:
11152 case AND64ri32:
11153 case AND64ri32_EVEX:
11154 case AND64ri32_ND:
11155 case AND64ri32_NF:
11156 case AND64ri32_NF_ND:
11157 case AND64ri8:
11158 case AND64ri8_EVEX:
11159 case AND64ri8_ND:
11160 case AND64ri8_NF:
11161 case AND64ri8_NF_ND:
11162 case AND64rm:
11163 case AND64rm_EVEX:
11164 case AND64rm_ND:
11165 case AND64rm_NF:
11166 case AND64rm_NF_ND:
11167 case AND64rr:
11168 case AND64rr_EVEX:
11169 case AND64rr_EVEX_REV:
11170 case AND64rr_ND:
11171 case AND64rr_ND_REV:
11172 case AND64rr_NF:
11173 case AND64rr_NF_ND:
11174 case AND64rr_NF_ND_REV:
11175 case AND64rr_NF_REV:
11176 case AND64rr_REV:
11177 case AND8i8:
11178 case AND8mi:
11179 case AND8mi8:
11180 case AND8mi_EVEX:
11181 case AND8mi_ND:
11182 case AND8mi_NF:
11183 case AND8mi_NF_ND:
11184 case AND8mr:
11185 case AND8mr_EVEX:
11186 case AND8mr_ND:
11187 case AND8mr_NF:
11188 case AND8mr_NF_ND:
11189 case AND8ri:
11190 case AND8ri8:
11191 case AND8ri_EVEX:
11192 case AND8ri_ND:
11193 case AND8ri_NF:
11194 case AND8ri_NF_ND:
11195 case AND8rm:
11196 case AND8rm_EVEX:
11197 case AND8rm_ND:
11198 case AND8rm_NF:
11199 case AND8rm_NF_ND:
11200 case AND8rr:
11201 case AND8rr_EVEX:
11202 case AND8rr_EVEX_REV:
11203 case AND8rr_ND:
11204 case AND8rr_ND_REV:
11205 case AND8rr_NF:
11206 case AND8rr_NF_ND:
11207 case AND8rr_NF_ND_REV:
11208 case AND8rr_NF_REV:
11209 case AND8rr_REV:
11210 return true;
11211 }
11212 return false;
11213}
11214
11215bool isPSLLQ(unsigned Opcode) {
11216 switch (Opcode) {
11217 case MMX_PSLLQri:
11218 case MMX_PSLLQrm:
11219 case MMX_PSLLQrr:
11220 case PSLLQri:
11221 case PSLLQrm:
11222 case PSLLQrr:
11223 return true;
11224 }
11225 return false;
11226}
11227
11228bool isVFMSUB132PH(unsigned Opcode) {
11229 switch (Opcode) {
11230 case VFMSUB132PHZ128m:
11231 case VFMSUB132PHZ128mb:
11232 case VFMSUB132PHZ128mbk:
11233 case VFMSUB132PHZ128mbkz:
11234 case VFMSUB132PHZ128mk:
11235 case VFMSUB132PHZ128mkz:
11236 case VFMSUB132PHZ128r:
11237 case VFMSUB132PHZ128rk:
11238 case VFMSUB132PHZ128rkz:
11239 case VFMSUB132PHZ256m:
11240 case VFMSUB132PHZ256mb:
11241 case VFMSUB132PHZ256mbk:
11242 case VFMSUB132PHZ256mbkz:
11243 case VFMSUB132PHZ256mk:
11244 case VFMSUB132PHZ256mkz:
11245 case VFMSUB132PHZ256r:
11246 case VFMSUB132PHZ256rk:
11247 case VFMSUB132PHZ256rkz:
11248 case VFMSUB132PHZm:
11249 case VFMSUB132PHZmb:
11250 case VFMSUB132PHZmbk:
11251 case VFMSUB132PHZmbkz:
11252 case VFMSUB132PHZmk:
11253 case VFMSUB132PHZmkz:
11254 case VFMSUB132PHZr:
11255 case VFMSUB132PHZrb:
11256 case VFMSUB132PHZrbk:
11257 case VFMSUB132PHZrbkz:
11258 case VFMSUB132PHZrk:
11259 case VFMSUB132PHZrkz:
11260 return true;
11261 }
11262 return false;
11263}
11264
11265bool isXSAVE(unsigned Opcode) {
11266 return Opcode == XSAVE;
11267}
11268
11269bool isKNOTQ(unsigned Opcode) {
11270 return Opcode == KNOTQkk;
11271}
11272
11273bool isXTEST(unsigned Opcode) {
11274 return Opcode == XTEST;
11275}
11276
11277bool isVINSERTPS(unsigned Opcode) {
11278 switch (Opcode) {
11279 case VINSERTPSZrmi:
11280 case VINSERTPSZrri:
11281 case VINSERTPSrmi:
11282 case VINSERTPSrri:
11283 return true;
11284 }
11285 return false;
11286}
11287
11288bool isXSAVEOPT(unsigned Opcode) {
11289 return Opcode == XSAVEOPT;
11290}
11291
11292bool isLDS(unsigned Opcode) {
11293 switch (Opcode) {
11294 case LDS16rm:
11295 case LDS32rm:
11296 return true;
11297 }
11298 return false;
11299}
11300
11301bool isVFMADDSUB213PD(unsigned Opcode) {
11302 switch (Opcode) {
11303 case VFMADDSUB213PDYm:
11304 case VFMADDSUB213PDYr:
11305 case VFMADDSUB213PDZ128m:
11306 case VFMADDSUB213PDZ128mb:
11307 case VFMADDSUB213PDZ128mbk:
11308 case VFMADDSUB213PDZ128mbkz:
11309 case VFMADDSUB213PDZ128mk:
11310 case VFMADDSUB213PDZ128mkz:
11311 case VFMADDSUB213PDZ128r:
11312 case VFMADDSUB213PDZ128rk:
11313 case VFMADDSUB213PDZ128rkz:
11314 case VFMADDSUB213PDZ256m:
11315 case VFMADDSUB213PDZ256mb:
11316 case VFMADDSUB213PDZ256mbk:
11317 case VFMADDSUB213PDZ256mbkz:
11318 case VFMADDSUB213PDZ256mk:
11319 case VFMADDSUB213PDZ256mkz:
11320 case VFMADDSUB213PDZ256r:
11321 case VFMADDSUB213PDZ256rk:
11322 case VFMADDSUB213PDZ256rkz:
11323 case VFMADDSUB213PDZm:
11324 case VFMADDSUB213PDZmb:
11325 case VFMADDSUB213PDZmbk:
11326 case VFMADDSUB213PDZmbkz:
11327 case VFMADDSUB213PDZmk:
11328 case VFMADDSUB213PDZmkz:
11329 case VFMADDSUB213PDZr:
11330 case VFMADDSUB213PDZrb:
11331 case VFMADDSUB213PDZrbk:
11332 case VFMADDSUB213PDZrbkz:
11333 case VFMADDSUB213PDZrk:
11334 case VFMADDSUB213PDZrkz:
11335 case VFMADDSUB213PDm:
11336 case VFMADDSUB213PDr:
11337 return true;
11338 }
11339 return false;
11340}
11341
11342bool isVINSERTF32X4(unsigned Opcode) {
11343 switch (Opcode) {
11344 case VINSERTF32X4Z256rmi:
11345 case VINSERTF32X4Z256rmik:
11346 case VINSERTF32X4Z256rmikz:
11347 case VINSERTF32X4Z256rri:
11348 case VINSERTF32X4Z256rrik:
11349 case VINSERTF32X4Z256rrikz:
11350 case VINSERTF32X4Zrmi:
11351 case VINSERTF32X4Zrmik:
11352 case VINSERTF32X4Zrmikz:
11353 case VINSERTF32X4Zrri:
11354 case VINSERTF32X4Zrrik:
11355 case VINSERTF32X4Zrrikz:
11356 return true;
11357 }
11358 return false;
11359}
11360
11361bool isVRSQRTPS(unsigned Opcode) {
11362 switch (Opcode) {
11363 case VRSQRTPSYm:
11364 case VRSQRTPSYr:
11365 case VRSQRTPSm:
11366 case VRSQRTPSr:
11367 return true;
11368 }
11369 return false;
11370}
11371
11372bool isVSUBPH(unsigned Opcode) {
11373 switch (Opcode) {
11374 case VSUBPHZ128rm:
11375 case VSUBPHZ128rmb:
11376 case VSUBPHZ128rmbk:
11377 case VSUBPHZ128rmbkz:
11378 case VSUBPHZ128rmk:
11379 case VSUBPHZ128rmkz:
11380 case VSUBPHZ128rr:
11381 case VSUBPHZ128rrk:
11382 case VSUBPHZ128rrkz:
11383 case VSUBPHZ256rm:
11384 case VSUBPHZ256rmb:
11385 case VSUBPHZ256rmbk:
11386 case VSUBPHZ256rmbkz:
11387 case VSUBPHZ256rmk:
11388 case VSUBPHZ256rmkz:
11389 case VSUBPHZ256rr:
11390 case VSUBPHZ256rrk:
11391 case VSUBPHZ256rrkz:
11392 case VSUBPHZrm:
11393 case VSUBPHZrmb:
11394 case VSUBPHZrmbk:
11395 case VSUBPHZrmbkz:
11396 case VSUBPHZrmk:
11397 case VSUBPHZrmkz:
11398 case VSUBPHZrr:
11399 case VSUBPHZrrb:
11400 case VSUBPHZrrbk:
11401 case VSUBPHZrrbkz:
11402 case VSUBPHZrrk:
11403 case VSUBPHZrrkz:
11404 return true;
11405 }
11406 return false;
11407}
11408
11409bool isPMOVSXBW(unsigned Opcode) {
11410 switch (Opcode) {
11411 case PMOVSXBWrm:
11412 case PMOVSXBWrr:
11413 return true;
11414 }
11415 return false;
11416}
11417
11418bool isVPSRLDQ(unsigned Opcode) {
11419 switch (Opcode) {
11420 case VPSRLDQYri:
11421 case VPSRLDQZ128mi:
11422 case VPSRLDQZ128ri:
11423 case VPSRLDQZ256mi:
11424 case VPSRLDQZ256ri:
11425 case VPSRLDQZmi:
11426 case VPSRLDQZri:
11427 case VPSRLDQri:
11428 return true;
11429 }
11430 return false;
11431}
11432
11433bool isADC(unsigned Opcode) {
11434 switch (Opcode) {
11435 case ADC16i16:
11436 case ADC16mi:
11437 case ADC16mi8:
11438 case ADC16mi8_EVEX:
11439 case ADC16mi8_ND:
11440 case ADC16mi_EVEX:
11441 case ADC16mi_ND:
11442 case ADC16mr:
11443 case ADC16mr_EVEX:
11444 case ADC16mr_ND:
11445 case ADC16ri:
11446 case ADC16ri8:
11447 case ADC16ri8_EVEX:
11448 case ADC16ri8_ND:
11449 case ADC16ri_EVEX:
11450 case ADC16ri_ND:
11451 case ADC16rm:
11452 case ADC16rm_EVEX:
11453 case ADC16rm_ND:
11454 case ADC16rr:
11455 case ADC16rr_EVEX:
11456 case ADC16rr_EVEX_REV:
11457 case ADC16rr_ND:
11458 case ADC16rr_ND_REV:
11459 case ADC16rr_REV:
11460 case ADC32i32:
11461 case ADC32mi:
11462 case ADC32mi8:
11463 case ADC32mi8_EVEX:
11464 case ADC32mi8_ND:
11465 case ADC32mi_EVEX:
11466 case ADC32mi_ND:
11467 case ADC32mr:
11468 case ADC32mr_EVEX:
11469 case ADC32mr_ND:
11470 case ADC32ri:
11471 case ADC32ri8:
11472 case ADC32ri8_EVEX:
11473 case ADC32ri8_ND:
11474 case ADC32ri_EVEX:
11475 case ADC32ri_ND:
11476 case ADC32rm:
11477 case ADC32rm_EVEX:
11478 case ADC32rm_ND:
11479 case ADC32rr:
11480 case ADC32rr_EVEX:
11481 case ADC32rr_EVEX_REV:
11482 case ADC32rr_ND:
11483 case ADC32rr_ND_REV:
11484 case ADC32rr_REV:
11485 case ADC64i32:
11486 case ADC64mi32:
11487 case ADC64mi32_EVEX:
11488 case ADC64mi32_ND:
11489 case ADC64mi8:
11490 case ADC64mi8_EVEX:
11491 case ADC64mi8_ND:
11492 case ADC64mr:
11493 case ADC64mr_EVEX:
11494 case ADC64mr_ND:
11495 case ADC64ri32:
11496 case ADC64ri32_EVEX:
11497 case ADC64ri32_ND:
11498 case ADC64ri8:
11499 case ADC64ri8_EVEX:
11500 case ADC64ri8_ND:
11501 case ADC64rm:
11502 case ADC64rm_EVEX:
11503 case ADC64rm_ND:
11504 case ADC64rr:
11505 case ADC64rr_EVEX:
11506 case ADC64rr_EVEX_REV:
11507 case ADC64rr_ND:
11508 case ADC64rr_ND_REV:
11509 case ADC64rr_REV:
11510 case ADC8i8:
11511 case ADC8mi:
11512 case ADC8mi8:
11513 case ADC8mi_EVEX:
11514 case ADC8mi_ND:
11515 case ADC8mr:
11516 case ADC8mr_EVEX:
11517 case ADC8mr_ND:
11518 case ADC8ri:
11519 case ADC8ri8:
11520 case ADC8ri_EVEX:
11521 case ADC8ri_ND:
11522 case ADC8rm:
11523 case ADC8rm_EVEX:
11524 case ADC8rm_ND:
11525 case ADC8rr:
11526 case ADC8rr_EVEX:
11527 case ADC8rr_EVEX_REV:
11528 case ADC8rr_ND:
11529 case ADC8rr_ND_REV:
11530 case ADC8rr_REV:
11531 return true;
11532 }
11533 return false;
11534}
11535
11536bool isPHADDD(unsigned Opcode) {
11537 switch (Opcode) {
11538 case MMX_PHADDDrm:
11539 case MMX_PHADDDrr:
11540 case PHADDDrm:
11541 case PHADDDrr:
11542 return true;
11543 }
11544 return false;
11545}
11546
11547bool isVDPPHPS(unsigned Opcode) {
11548 switch (Opcode) {
11549 case VDPPHPSZ128m:
11550 case VDPPHPSZ128mb:
11551 case VDPPHPSZ128mbk:
11552 case VDPPHPSZ128mbkz:
11553 case VDPPHPSZ128mk:
11554 case VDPPHPSZ128mkz:
11555 case VDPPHPSZ128r:
11556 case VDPPHPSZ128rk:
11557 case VDPPHPSZ128rkz:
11558 case VDPPHPSZ256m:
11559 case VDPPHPSZ256mb:
11560 case VDPPHPSZ256mbk:
11561 case VDPPHPSZ256mbkz:
11562 case VDPPHPSZ256mk:
11563 case VDPPHPSZ256mkz:
11564 case VDPPHPSZ256r:
11565 case VDPPHPSZ256rk:
11566 case VDPPHPSZ256rkz:
11567 case VDPPHPSZm:
11568 case VDPPHPSZmb:
11569 case VDPPHPSZmbk:
11570 case VDPPHPSZmbkz:
11571 case VDPPHPSZmk:
11572 case VDPPHPSZmkz:
11573 case VDPPHPSZr:
11574 case VDPPHPSZrk:
11575 case VDPPHPSZrkz:
11576 return true;
11577 }
11578 return false;
11579}
11580
11581bool isVMINPH(unsigned Opcode) {
11582 switch (Opcode) {
11583 case VMINPHZ128rm:
11584 case VMINPHZ128rmb:
11585 case VMINPHZ128rmbk:
11586 case VMINPHZ128rmbkz:
11587 case VMINPHZ128rmk:
11588 case VMINPHZ128rmkz:
11589 case VMINPHZ128rr:
11590 case VMINPHZ128rrk:
11591 case VMINPHZ128rrkz:
11592 case VMINPHZ256rm:
11593 case VMINPHZ256rmb:
11594 case VMINPHZ256rmbk:
11595 case VMINPHZ256rmbkz:
11596 case VMINPHZ256rmk:
11597 case VMINPHZ256rmkz:
11598 case VMINPHZ256rr:
11599 case VMINPHZ256rrk:
11600 case VMINPHZ256rrkz:
11601 case VMINPHZrm:
11602 case VMINPHZrmb:
11603 case VMINPHZrmbk:
11604 case VMINPHZrmbkz:
11605 case VMINPHZrmk:
11606 case VMINPHZrmkz:
11607 case VMINPHZrr:
11608 case VMINPHZrrb:
11609 case VMINPHZrrbk:
11610 case VMINPHZrrbkz:
11611 case VMINPHZrrk:
11612 case VMINPHZrrkz:
11613 return true;
11614 }
11615 return false;
11616}
11617
11618bool isVMINSD(unsigned Opcode) {
11619 switch (Opcode) {
11620 case VMINSDZrm_Int:
11621 case VMINSDZrmk_Int:
11622 case VMINSDZrmkz_Int:
11623 case VMINSDZrr_Int:
11624 case VMINSDZrrb_Int:
11625 case VMINSDZrrbk_Int:
11626 case VMINSDZrrbkz_Int:
11627 case VMINSDZrrk_Int:
11628 case VMINSDZrrkz_Int:
11629 case VMINSDrm_Int:
11630 case VMINSDrr_Int:
11631 return true;
11632 }
11633 return false;
11634}
11635
11636bool isVROUNDPD(unsigned Opcode) {
11637 switch (Opcode) {
11638 case VROUNDPDYmi:
11639 case VROUNDPDYri:
11640 case VROUNDPDmi:
11641 case VROUNDPDri:
11642 return true;
11643 }
11644 return false;
11645}
11646
11647bool isVFCMADDCPH(unsigned Opcode) {
11648 switch (Opcode) {
11649 case VFCMADDCPHZ128m:
11650 case VFCMADDCPHZ128mb:
11651 case VFCMADDCPHZ128mbk:
11652 case VFCMADDCPHZ128mbkz:
11653 case VFCMADDCPHZ128mk:
11654 case VFCMADDCPHZ128mkz:
11655 case VFCMADDCPHZ128r:
11656 case VFCMADDCPHZ128rk:
11657 case VFCMADDCPHZ128rkz:
11658 case VFCMADDCPHZ256m:
11659 case VFCMADDCPHZ256mb:
11660 case VFCMADDCPHZ256mbk:
11661 case VFCMADDCPHZ256mbkz:
11662 case VFCMADDCPHZ256mk:
11663 case VFCMADDCPHZ256mkz:
11664 case VFCMADDCPHZ256r:
11665 case VFCMADDCPHZ256rk:
11666 case VFCMADDCPHZ256rkz:
11667 case VFCMADDCPHZm:
11668 case VFCMADDCPHZmb:
11669 case VFCMADDCPHZmbk:
11670 case VFCMADDCPHZmbkz:
11671 case VFCMADDCPHZmk:
11672 case VFCMADDCPHZmkz:
11673 case VFCMADDCPHZr:
11674 case VFCMADDCPHZrb:
11675 case VFCMADDCPHZrbk:
11676 case VFCMADDCPHZrbkz:
11677 case VFCMADDCPHZrk:
11678 case VFCMADDCPHZrkz:
11679 return true;
11680 }
11681 return false;
11682}
11683
11684bool isINCSSPQ(unsigned Opcode) {
11685 return Opcode == INCSSPQ;
11686}
11687
11688bool isVPUNPCKLDQ(unsigned Opcode) {
11689 switch (Opcode) {
11690 case VPUNPCKLDQYrm:
11691 case VPUNPCKLDQYrr:
11692 case VPUNPCKLDQZ128rm:
11693 case VPUNPCKLDQZ128rmb:
11694 case VPUNPCKLDQZ128rmbk:
11695 case VPUNPCKLDQZ128rmbkz:
11696 case VPUNPCKLDQZ128rmk:
11697 case VPUNPCKLDQZ128rmkz:
11698 case VPUNPCKLDQZ128rr:
11699 case VPUNPCKLDQZ128rrk:
11700 case VPUNPCKLDQZ128rrkz:
11701 case VPUNPCKLDQZ256rm:
11702 case VPUNPCKLDQZ256rmb:
11703 case VPUNPCKLDQZ256rmbk:
11704 case VPUNPCKLDQZ256rmbkz:
11705 case VPUNPCKLDQZ256rmk:
11706 case VPUNPCKLDQZ256rmkz:
11707 case VPUNPCKLDQZ256rr:
11708 case VPUNPCKLDQZ256rrk:
11709 case VPUNPCKLDQZ256rrkz:
11710 case VPUNPCKLDQZrm:
11711 case VPUNPCKLDQZrmb:
11712 case VPUNPCKLDQZrmbk:
11713 case VPUNPCKLDQZrmbkz:
11714 case VPUNPCKLDQZrmk:
11715 case VPUNPCKLDQZrmkz:
11716 case VPUNPCKLDQZrr:
11717 case VPUNPCKLDQZrrk:
11718 case VPUNPCKLDQZrrkz:
11719 case VPUNPCKLDQrm:
11720 case VPUNPCKLDQrr:
11721 return true;
11722 }
11723 return false;
11724}
11725
11726bool isVMINSH(unsigned Opcode) {
11727 switch (Opcode) {
11728 case VMINSHZrm_Int:
11729 case VMINSHZrmk_Int:
11730 case VMINSHZrmkz_Int:
11731 case VMINSHZrr_Int:
11732 case VMINSHZrrb_Int:
11733 case VMINSHZrrbk_Int:
11734 case VMINSHZrrbkz_Int:
11735 case VMINSHZrrk_Int:
11736 case VMINSHZrrkz_Int:
11737 return true;
11738 }
11739 return false;
11740}
11741
11742bool isINSERTQ(unsigned Opcode) {
11743 switch (Opcode) {
11744 case INSERTQ:
11745 case INSERTQI:
11746 return true;
11747 }
11748 return false;
11749}
11750
11751bool isBLCI(unsigned Opcode) {
11752 switch (Opcode) {
11753 case BLCI32rm:
11754 case BLCI32rr:
11755 case BLCI64rm:
11756 case BLCI64rr:
11757 return true;
11758 }
11759 return false;
11760}
11761
11762bool isHLT(unsigned Opcode) {
11763 return Opcode == HLT;
11764}
11765
11766bool isVPCOMUW(unsigned Opcode) {
11767 switch (Opcode) {
11768 case VPCOMUWmi:
11769 case VPCOMUWri:
11770 return true;
11771 }
11772 return false;
11773}
11774
11775bool isVPMOVSXDQ(unsigned Opcode) {
11776 switch (Opcode) {
11777 case VPMOVSXDQYrm:
11778 case VPMOVSXDQYrr:
11779 case VPMOVSXDQZ128rm:
11780 case VPMOVSXDQZ128rmk:
11781 case VPMOVSXDQZ128rmkz:
11782 case VPMOVSXDQZ128rr:
11783 case VPMOVSXDQZ128rrk:
11784 case VPMOVSXDQZ128rrkz:
11785 case VPMOVSXDQZ256rm:
11786 case VPMOVSXDQZ256rmk:
11787 case VPMOVSXDQZ256rmkz:
11788 case VPMOVSXDQZ256rr:
11789 case VPMOVSXDQZ256rrk:
11790 case VPMOVSXDQZ256rrkz:
11791 case VPMOVSXDQZrm:
11792 case VPMOVSXDQZrmk:
11793 case VPMOVSXDQZrmkz:
11794 case VPMOVSXDQZrr:
11795 case VPMOVSXDQZrrk:
11796 case VPMOVSXDQZrrkz:
11797 case VPMOVSXDQrm:
11798 case VPMOVSXDQrr:
11799 return true;
11800 }
11801 return false;
11802}
11803
11804bool isVFNMSUB231PS(unsigned Opcode) {
11805 switch (Opcode) {
11806 case VFNMSUB231PSYm:
11807 case VFNMSUB231PSYr:
11808 case VFNMSUB231PSZ128m:
11809 case VFNMSUB231PSZ128mb:
11810 case VFNMSUB231PSZ128mbk:
11811 case VFNMSUB231PSZ128mbkz:
11812 case VFNMSUB231PSZ128mk:
11813 case VFNMSUB231PSZ128mkz:
11814 case VFNMSUB231PSZ128r:
11815 case VFNMSUB231PSZ128rk:
11816 case VFNMSUB231PSZ128rkz:
11817 case VFNMSUB231PSZ256m:
11818 case VFNMSUB231PSZ256mb:
11819 case VFNMSUB231PSZ256mbk:
11820 case VFNMSUB231PSZ256mbkz:
11821 case VFNMSUB231PSZ256mk:
11822 case VFNMSUB231PSZ256mkz:
11823 case VFNMSUB231PSZ256r:
11824 case VFNMSUB231PSZ256rk:
11825 case VFNMSUB231PSZ256rkz:
11826 case VFNMSUB231PSZm:
11827 case VFNMSUB231PSZmb:
11828 case VFNMSUB231PSZmbk:
11829 case VFNMSUB231PSZmbkz:
11830 case VFNMSUB231PSZmk:
11831 case VFNMSUB231PSZmkz:
11832 case VFNMSUB231PSZr:
11833 case VFNMSUB231PSZrb:
11834 case VFNMSUB231PSZrbk:
11835 case VFNMSUB231PSZrbkz:
11836 case VFNMSUB231PSZrk:
11837 case VFNMSUB231PSZrkz:
11838 case VFNMSUB231PSm:
11839 case VFNMSUB231PSr:
11840 return true;
11841 }
11842 return false;
11843}
11844
11845bool isVFNMSUB213SH(unsigned Opcode) {
11846 switch (Opcode) {
11847 case VFNMSUB213SHZm_Int:
11848 case VFNMSUB213SHZmk_Int:
11849 case VFNMSUB213SHZmkz_Int:
11850 case VFNMSUB213SHZr_Int:
11851 case VFNMSUB213SHZrb_Int:
11852 case VFNMSUB213SHZrbk_Int:
11853 case VFNMSUB213SHZrbkz_Int:
11854 case VFNMSUB213SHZrk_Int:
11855 case VFNMSUB213SHZrkz_Int:
11856 return true;
11857 }
11858 return false;
11859}
11860
11861bool isVCVTTPD2UQQ(unsigned Opcode) {
11862 switch (Opcode) {
11863 case VCVTTPD2UQQZ128rm:
11864 case VCVTTPD2UQQZ128rmb:
11865 case VCVTTPD2UQQZ128rmbk:
11866 case VCVTTPD2UQQZ128rmbkz:
11867 case VCVTTPD2UQQZ128rmk:
11868 case VCVTTPD2UQQZ128rmkz:
11869 case VCVTTPD2UQQZ128rr:
11870 case VCVTTPD2UQQZ128rrk:
11871 case VCVTTPD2UQQZ128rrkz:
11872 case VCVTTPD2UQQZ256rm:
11873 case VCVTTPD2UQQZ256rmb:
11874 case VCVTTPD2UQQZ256rmbk:
11875 case VCVTTPD2UQQZ256rmbkz:
11876 case VCVTTPD2UQQZ256rmk:
11877 case VCVTTPD2UQQZ256rmkz:
11878 case VCVTTPD2UQQZ256rr:
11879 case VCVTTPD2UQQZ256rrk:
11880 case VCVTTPD2UQQZ256rrkz:
11881 case VCVTTPD2UQQZrm:
11882 case VCVTTPD2UQQZrmb:
11883 case VCVTTPD2UQQZrmbk:
11884 case VCVTTPD2UQQZrmbkz:
11885 case VCVTTPD2UQQZrmk:
11886 case VCVTTPD2UQQZrmkz:
11887 case VCVTTPD2UQQZrr:
11888 case VCVTTPD2UQQZrrb:
11889 case VCVTTPD2UQQZrrbk:
11890 case VCVTTPD2UQQZrrbkz:
11891 case VCVTTPD2UQQZrrk:
11892 case VCVTTPD2UQQZrrkz:
11893 return true;
11894 }
11895 return false;
11896}
11897
11898bool isSQRTSS(unsigned Opcode) {
11899 switch (Opcode) {
11900 case SQRTSSm_Int:
11901 case SQRTSSr_Int:
11902 return true;
11903 }
11904 return false;
11905}
11906
11907bool isIMUL(unsigned Opcode) {
11908 switch (Opcode) {
11909 case IMUL16m:
11910 case IMUL16m_EVEX:
11911 case IMUL16m_NF:
11912 case IMUL16r:
11913 case IMUL16r_EVEX:
11914 case IMUL16r_NF:
11915 case IMUL16rm:
11916 case IMUL16rm_EVEX:
11917 case IMUL16rm_ND:
11918 case IMUL16rm_NF:
11919 case IMUL16rm_NF_ND:
11920 case IMUL16rmi:
11921 case IMUL16rmi8:
11922 case IMUL16rmi8_EVEX:
11923 case IMUL16rmi8_NF:
11924 case IMUL16rmi_EVEX:
11925 case IMUL16rmi_NF:
11926 case IMUL16rr:
11927 case IMUL16rr_EVEX:
11928 case IMUL16rr_ND:
11929 case IMUL16rr_NF:
11930 case IMUL16rr_NF_ND:
11931 case IMUL16rri:
11932 case IMUL16rri8:
11933 case IMUL16rri8_EVEX:
11934 case IMUL16rri8_NF:
11935 case IMUL16rri_EVEX:
11936 case IMUL16rri_NF:
11937 case IMUL32m:
11938 case IMUL32m_EVEX:
11939 case IMUL32m_NF:
11940 case IMUL32r:
11941 case IMUL32r_EVEX:
11942 case IMUL32r_NF:
11943 case IMUL32rm:
11944 case IMUL32rm_EVEX:
11945 case IMUL32rm_ND:
11946 case IMUL32rm_NF:
11947 case IMUL32rm_NF_ND:
11948 case IMUL32rmi:
11949 case IMUL32rmi8:
11950 case IMUL32rmi8_EVEX:
11951 case IMUL32rmi8_NF:
11952 case IMUL32rmi_EVEX:
11953 case IMUL32rmi_NF:
11954 case IMUL32rr:
11955 case IMUL32rr_EVEX:
11956 case IMUL32rr_ND:
11957 case IMUL32rr_NF:
11958 case IMUL32rr_NF_ND:
11959 case IMUL32rri:
11960 case IMUL32rri8:
11961 case IMUL32rri8_EVEX:
11962 case IMUL32rri8_NF:
11963 case IMUL32rri_EVEX:
11964 case IMUL32rri_NF:
11965 case IMUL64m:
11966 case IMUL64m_EVEX:
11967 case IMUL64m_NF:
11968 case IMUL64r:
11969 case IMUL64r_EVEX:
11970 case IMUL64r_NF:
11971 case IMUL64rm:
11972 case IMUL64rm_EVEX:
11973 case IMUL64rm_ND:
11974 case IMUL64rm_NF:
11975 case IMUL64rm_NF_ND:
11976 case IMUL64rmi32:
11977 case IMUL64rmi32_EVEX:
11978 case IMUL64rmi32_NF:
11979 case IMUL64rmi8:
11980 case IMUL64rmi8_EVEX:
11981 case IMUL64rmi8_NF:
11982 case IMUL64rr:
11983 case IMUL64rr_EVEX:
11984 case IMUL64rr_ND:
11985 case IMUL64rr_NF:
11986 case IMUL64rr_NF_ND:
11987 case IMUL64rri32:
11988 case IMUL64rri32_EVEX:
11989 case IMUL64rri32_NF:
11990 case IMUL64rri8:
11991 case IMUL64rri8_EVEX:
11992 case IMUL64rri8_NF:
11993 case IMUL8m:
11994 case IMUL8m_EVEX:
11995 case IMUL8m_NF:
11996 case IMUL8r:
11997 case IMUL8r_EVEX:
11998 case IMUL8r_NF:
11999 return true;
12000 }
12001 return false;
12002}
12003
12004bool isVCVTSS2SI(unsigned Opcode) {
12005 switch (Opcode) {
12006 case VCVTSS2SI64Zrm_Int:
12007 case VCVTSS2SI64Zrr_Int:
12008 case VCVTSS2SI64Zrrb_Int:
12009 case VCVTSS2SI64rm_Int:
12010 case VCVTSS2SI64rr_Int:
12011 case VCVTSS2SIZrm_Int:
12012 case VCVTSS2SIZrr_Int:
12013 case VCVTSS2SIZrrb_Int:
12014 case VCVTSS2SIrm_Int:
12015 case VCVTSS2SIrr_Int:
12016 return true;
12017 }
12018 return false;
12019}
12020
12021bool isPUSHAW(unsigned Opcode) {
12022 return Opcode == PUSHA16;
12023}
12024
12025bool isSTOSD(unsigned Opcode) {
12026 return Opcode == STOSL;
12027}
12028
12029bool isPSRLDQ(unsigned Opcode) {
12030 return Opcode == PSRLDQri;
12031}
12032
12033bool isVSCATTERQPS(unsigned Opcode) {
12034 switch (Opcode) {
12035 case VSCATTERQPSZ128mr:
12036 case VSCATTERQPSZ256mr:
12037 case VSCATTERQPSZmr:
12038 return true;
12039 }
12040 return false;
12041}
12042
12043bool isFIDIV(unsigned Opcode) {
12044 switch (Opcode) {
12045 case DIV_FI16m:
12046 case DIV_FI32m:
12047 return true;
12048 }
12049 return false;
12050}
12051
12052bool isVFMSUB213PD(unsigned Opcode) {
12053 switch (Opcode) {
12054 case VFMSUB213PDYm:
12055 case VFMSUB213PDYr:
12056 case VFMSUB213PDZ128m:
12057 case VFMSUB213PDZ128mb:
12058 case VFMSUB213PDZ128mbk:
12059 case VFMSUB213PDZ128mbkz:
12060 case VFMSUB213PDZ128mk:
12061 case VFMSUB213PDZ128mkz:
12062 case VFMSUB213PDZ128r:
12063 case VFMSUB213PDZ128rk:
12064 case VFMSUB213PDZ128rkz:
12065 case VFMSUB213PDZ256m:
12066 case VFMSUB213PDZ256mb:
12067 case VFMSUB213PDZ256mbk:
12068 case VFMSUB213PDZ256mbkz:
12069 case VFMSUB213PDZ256mk:
12070 case VFMSUB213PDZ256mkz:
12071 case VFMSUB213PDZ256r:
12072 case VFMSUB213PDZ256rk:
12073 case VFMSUB213PDZ256rkz:
12074 case VFMSUB213PDZm:
12075 case VFMSUB213PDZmb:
12076 case VFMSUB213PDZmbk:
12077 case VFMSUB213PDZmbkz:
12078 case VFMSUB213PDZmk:
12079 case VFMSUB213PDZmkz:
12080 case VFMSUB213PDZr:
12081 case VFMSUB213PDZrb:
12082 case VFMSUB213PDZrbk:
12083 case VFMSUB213PDZrbkz:
12084 case VFMSUB213PDZrk:
12085 case VFMSUB213PDZrkz:
12086 case VFMSUB213PDm:
12087 case VFMSUB213PDr:
12088 return true;
12089 }
12090 return false;
12091}
12092
12093bool isVFMADDSUB231PH(unsigned Opcode) {
12094 switch (Opcode) {
12095 case VFMADDSUB231PHZ128m:
12096 case VFMADDSUB231PHZ128mb:
12097 case VFMADDSUB231PHZ128mbk:
12098 case VFMADDSUB231PHZ128mbkz:
12099 case VFMADDSUB231PHZ128mk:
12100 case VFMADDSUB231PHZ128mkz:
12101 case VFMADDSUB231PHZ128r:
12102 case VFMADDSUB231PHZ128rk:
12103 case VFMADDSUB231PHZ128rkz:
12104 case VFMADDSUB231PHZ256m:
12105 case VFMADDSUB231PHZ256mb:
12106 case VFMADDSUB231PHZ256mbk:
12107 case VFMADDSUB231PHZ256mbkz:
12108 case VFMADDSUB231PHZ256mk:
12109 case VFMADDSUB231PHZ256mkz:
12110 case VFMADDSUB231PHZ256r:
12111 case VFMADDSUB231PHZ256rk:
12112 case VFMADDSUB231PHZ256rkz:
12113 case VFMADDSUB231PHZm:
12114 case VFMADDSUB231PHZmb:
12115 case VFMADDSUB231PHZmbk:
12116 case VFMADDSUB231PHZmbkz:
12117 case VFMADDSUB231PHZmk:
12118 case VFMADDSUB231PHZmkz:
12119 case VFMADDSUB231PHZr:
12120 case VFMADDSUB231PHZrb:
12121 case VFMADDSUB231PHZrbk:
12122 case VFMADDSUB231PHZrbkz:
12123 case VFMADDSUB231PHZrk:
12124 case VFMADDSUB231PHZrkz:
12125 return true;
12126 }
12127 return false;
12128}
12129
12130bool isTDCALL(unsigned Opcode) {
12131 return Opcode == TDCALL;
12132}
12133
12134bool isPVALIDATE(unsigned Opcode) {
12135 switch (Opcode) {
12136 case PVALIDATE32:
12137 case PVALIDATE64:
12138 return true;
12139 }
12140 return false;
12141}
12142
12143bool isVPSHUFLW(unsigned Opcode) {
12144 switch (Opcode) {
12145 case VPSHUFLWYmi:
12146 case VPSHUFLWYri:
12147 case VPSHUFLWZ128mi:
12148 case VPSHUFLWZ128mik:
12149 case VPSHUFLWZ128mikz:
12150 case VPSHUFLWZ128ri:
12151 case VPSHUFLWZ128rik:
12152 case VPSHUFLWZ128rikz:
12153 case VPSHUFLWZ256mi:
12154 case VPSHUFLWZ256mik:
12155 case VPSHUFLWZ256mikz:
12156 case VPSHUFLWZ256ri:
12157 case VPSHUFLWZ256rik:
12158 case VPSHUFLWZ256rikz:
12159 case VPSHUFLWZmi:
12160 case VPSHUFLWZmik:
12161 case VPSHUFLWZmikz:
12162 case VPSHUFLWZri:
12163 case VPSHUFLWZrik:
12164 case VPSHUFLWZrikz:
12165 case VPSHUFLWmi:
12166 case VPSHUFLWri:
12167 return true;
12168 }
12169 return false;
12170}
12171
12172bool isPCLMULQDQ(unsigned Opcode) {
12173 switch (Opcode) {
12174 case PCLMULQDQrmi:
12175 case PCLMULQDQrri:
12176 return true;
12177 }
12178 return false;
12179}
12180
12181bool isCMPXCHG8B(unsigned Opcode) {
12182 return Opcode == CMPXCHG8B;
12183}
12184
12185bool isVPMOVM2B(unsigned Opcode) {
12186 switch (Opcode) {
12187 case VPMOVM2BZ128rk:
12188 case VPMOVM2BZ256rk:
12189 case VPMOVM2BZrk:
12190 return true;
12191 }
12192 return false;
12193}
12194
12195bool isVCVTUDQ2PH(unsigned Opcode) {
12196 switch (Opcode) {
12197 case VCVTUDQ2PHZ128rm:
12198 case VCVTUDQ2PHZ128rmb:
12199 case VCVTUDQ2PHZ128rmbk:
12200 case VCVTUDQ2PHZ128rmbkz:
12201 case VCVTUDQ2PHZ128rmk:
12202 case VCVTUDQ2PHZ128rmkz:
12203 case VCVTUDQ2PHZ128rr:
12204 case VCVTUDQ2PHZ128rrk:
12205 case VCVTUDQ2PHZ128rrkz:
12206 case VCVTUDQ2PHZ256rm:
12207 case VCVTUDQ2PHZ256rmb:
12208 case VCVTUDQ2PHZ256rmbk:
12209 case VCVTUDQ2PHZ256rmbkz:
12210 case VCVTUDQ2PHZ256rmk:
12211 case VCVTUDQ2PHZ256rmkz:
12212 case VCVTUDQ2PHZ256rr:
12213 case VCVTUDQ2PHZ256rrk:
12214 case VCVTUDQ2PHZ256rrkz:
12215 case VCVTUDQ2PHZrm:
12216 case VCVTUDQ2PHZrmb:
12217 case VCVTUDQ2PHZrmbk:
12218 case VCVTUDQ2PHZrmbkz:
12219 case VCVTUDQ2PHZrmk:
12220 case VCVTUDQ2PHZrmkz:
12221 case VCVTUDQ2PHZrr:
12222 case VCVTUDQ2PHZrrb:
12223 case VCVTUDQ2PHZrrbk:
12224 case VCVTUDQ2PHZrrbkz:
12225 case VCVTUDQ2PHZrrk:
12226 case VCVTUDQ2PHZrrkz:
12227 return true;
12228 }
12229 return false;
12230}
12231
12232bool isPEXTRQ(unsigned Opcode) {
12233 switch (Opcode) {
12234 case PEXTRQmri:
12235 case PEXTRQrri:
12236 return true;
12237 }
12238 return false;
12239}
12240
12241bool isXCRYPTCTR(unsigned Opcode) {
12242 return Opcode == XCRYPTCTR;
12243}
12244
12245bool isVREDUCEPH(unsigned Opcode) {
12246 switch (Opcode) {
12247 case VREDUCEPHZ128rmbi:
12248 case VREDUCEPHZ128rmbik:
12249 case VREDUCEPHZ128rmbikz:
12250 case VREDUCEPHZ128rmi:
12251 case VREDUCEPHZ128rmik:
12252 case VREDUCEPHZ128rmikz:
12253 case VREDUCEPHZ128rri:
12254 case VREDUCEPHZ128rrik:
12255 case VREDUCEPHZ128rrikz:
12256 case VREDUCEPHZ256rmbi:
12257 case VREDUCEPHZ256rmbik:
12258 case VREDUCEPHZ256rmbikz:
12259 case VREDUCEPHZ256rmi:
12260 case VREDUCEPHZ256rmik:
12261 case VREDUCEPHZ256rmikz:
12262 case VREDUCEPHZ256rri:
12263 case VREDUCEPHZ256rrik:
12264 case VREDUCEPHZ256rrikz:
12265 case VREDUCEPHZrmbi:
12266 case VREDUCEPHZrmbik:
12267 case VREDUCEPHZrmbikz:
12268 case VREDUCEPHZrmi:
12269 case VREDUCEPHZrmik:
12270 case VREDUCEPHZrmikz:
12271 case VREDUCEPHZrri:
12272 case VREDUCEPHZrrib:
12273 case VREDUCEPHZrribk:
12274 case VREDUCEPHZrribkz:
12275 case VREDUCEPHZrrik:
12276 case VREDUCEPHZrrikz:
12277 return true;
12278 }
12279 return false;
12280}
12281
12282bool isUCOMISD(unsigned Opcode) {
12283 switch (Opcode) {
12284 case UCOMISDrm:
12285 case UCOMISDrr:
12286 return true;
12287 }
12288 return false;
12289}
12290
12291bool isOUTSD(unsigned Opcode) {
12292 return Opcode == OUTSL;
12293}
12294
12295bool isSUBSS(unsigned Opcode) {
12296 switch (Opcode) {
12297 case SUBSSrm_Int:
12298 case SUBSSrr_Int:
12299 return true;
12300 }
12301 return false;
12302}
12303
12304bool isVFMSUBPS(unsigned Opcode) {
12305 switch (Opcode) {
12306 case VFMSUBPS4Ymr:
12307 case VFMSUBPS4Yrm:
12308 case VFMSUBPS4Yrr:
12309 case VFMSUBPS4Yrr_REV:
12310 case VFMSUBPS4mr:
12311 case VFMSUBPS4rm:
12312 case VFMSUBPS4rr:
12313 case VFMSUBPS4rr_REV:
12314 return true;
12315 }
12316 return false;
12317}
12318
12319bool isVPBLENDW(unsigned Opcode) {
12320 switch (Opcode) {
12321 case VPBLENDWYrmi:
12322 case VPBLENDWYrri:
12323 case VPBLENDWrmi:
12324 case VPBLENDWrri:
12325 return true;
12326 }
12327 return false;
12328}
12329
12330bool isVPEXPANDB(unsigned Opcode) {
12331 switch (Opcode) {
12332 case VPEXPANDBZ128rm:
12333 case VPEXPANDBZ128rmk:
12334 case VPEXPANDBZ128rmkz:
12335 case VPEXPANDBZ128rr:
12336 case VPEXPANDBZ128rrk:
12337 case VPEXPANDBZ128rrkz:
12338 case VPEXPANDBZ256rm:
12339 case VPEXPANDBZ256rmk:
12340 case VPEXPANDBZ256rmkz:
12341 case VPEXPANDBZ256rr:
12342 case VPEXPANDBZ256rrk:
12343 case VPEXPANDBZ256rrkz:
12344 case VPEXPANDBZrm:
12345 case VPEXPANDBZrmk:
12346 case VPEXPANDBZrmkz:
12347 case VPEXPANDBZrr:
12348 case VPEXPANDBZrrk:
12349 case VPEXPANDBZrrkz:
12350 return true;
12351 }
12352 return false;
12353}
12354
12355bool isBZHI(unsigned Opcode) {
12356 switch (Opcode) {
12357 case BZHI32rm:
12358 case BZHI32rm_EVEX:
12359 case BZHI32rm_NF:
12360 case BZHI32rr:
12361 case BZHI32rr_EVEX:
12362 case BZHI32rr_NF:
12363 case BZHI64rm:
12364 case BZHI64rm_EVEX:
12365 case BZHI64rm_NF:
12366 case BZHI64rr:
12367 case BZHI64rr_EVEX:
12368 case BZHI64rr_NF:
12369 return true;
12370 }
12371 return false;
12372}
12373
12374bool isVPRORVD(unsigned Opcode) {
12375 switch (Opcode) {
12376 case VPRORVDZ128rm:
12377 case VPRORVDZ128rmb:
12378 case VPRORVDZ128rmbk:
12379 case VPRORVDZ128rmbkz:
12380 case VPRORVDZ128rmk:
12381 case VPRORVDZ128rmkz:
12382 case VPRORVDZ128rr:
12383 case VPRORVDZ128rrk:
12384 case VPRORVDZ128rrkz:
12385 case VPRORVDZ256rm:
12386 case VPRORVDZ256rmb:
12387 case VPRORVDZ256rmbk:
12388 case VPRORVDZ256rmbkz:
12389 case VPRORVDZ256rmk:
12390 case VPRORVDZ256rmkz:
12391 case VPRORVDZ256rr:
12392 case VPRORVDZ256rrk:
12393 case VPRORVDZ256rrkz:
12394 case VPRORVDZrm:
12395 case VPRORVDZrmb:
12396 case VPRORVDZrmbk:
12397 case VPRORVDZrmbkz:
12398 case VPRORVDZrmk:
12399 case VPRORVDZrmkz:
12400 case VPRORVDZrr:
12401 case VPRORVDZrrk:
12402 case VPRORVDZrrkz:
12403 return true;
12404 }
12405 return false;
12406}
12407
12408bool isRMPQUERY(unsigned Opcode) {
12409 return Opcode == RMPQUERY;
12410}
12411
12412bool isVPSCATTERDQ(unsigned Opcode) {
12413 switch (Opcode) {
12414 case VPSCATTERDQZ128mr:
12415 case VPSCATTERDQZ256mr:
12416 case VPSCATTERDQZmr:
12417 return true;
12418 }
12419 return false;
12420}
12421
12422bool isPSMASH(unsigned Opcode) {
12423 return Opcode == PSMASH;
12424}
12425
12426bool isVPSHLDQ(unsigned Opcode) {
12427 switch (Opcode) {
12428 case VPSHLDQZ128rmbi:
12429 case VPSHLDQZ128rmbik:
12430 case VPSHLDQZ128rmbikz:
12431 case VPSHLDQZ128rmi:
12432 case VPSHLDQZ128rmik:
12433 case VPSHLDQZ128rmikz:
12434 case VPSHLDQZ128rri:
12435 case VPSHLDQZ128rrik:
12436 case VPSHLDQZ128rrikz:
12437 case VPSHLDQZ256rmbi:
12438 case VPSHLDQZ256rmbik:
12439 case VPSHLDQZ256rmbikz:
12440 case VPSHLDQZ256rmi:
12441 case VPSHLDQZ256rmik:
12442 case VPSHLDQZ256rmikz:
12443 case VPSHLDQZ256rri:
12444 case VPSHLDQZ256rrik:
12445 case VPSHLDQZ256rrikz:
12446 case VPSHLDQZrmbi:
12447 case VPSHLDQZrmbik:
12448 case VPSHLDQZrmbikz:
12449 case VPSHLDQZrmi:
12450 case VPSHLDQZrmik:
12451 case VPSHLDQZrmikz:
12452 case VPSHLDQZrri:
12453 case VPSHLDQZrrik:
12454 case VPSHLDQZrrikz:
12455 return true;
12456 }
12457 return false;
12458}
12459
12460bool isVSCATTERPF1DPD(unsigned Opcode) {
12461 return Opcode == VSCATTERPF1DPDm;
12462}
12463
12464bool isMONTMUL(unsigned Opcode) {
12465 return Opcode == MONTMUL;
12466}
12467
12468bool isVCVTPH2UQQ(unsigned Opcode) {
12469 switch (Opcode) {
12470 case VCVTPH2UQQZ128rm:
12471 case VCVTPH2UQQZ128rmb:
12472 case VCVTPH2UQQZ128rmbk:
12473 case VCVTPH2UQQZ128rmbkz:
12474 case VCVTPH2UQQZ128rmk:
12475 case VCVTPH2UQQZ128rmkz:
12476 case VCVTPH2UQQZ128rr:
12477 case VCVTPH2UQQZ128rrk:
12478 case VCVTPH2UQQZ128rrkz:
12479 case VCVTPH2UQQZ256rm:
12480 case VCVTPH2UQQZ256rmb:
12481 case VCVTPH2UQQZ256rmbk:
12482 case VCVTPH2UQQZ256rmbkz:
12483 case VCVTPH2UQQZ256rmk:
12484 case VCVTPH2UQQZ256rmkz:
12485 case VCVTPH2UQQZ256rr:
12486 case VCVTPH2UQQZ256rrk:
12487 case VCVTPH2UQQZ256rrkz:
12488 case VCVTPH2UQQZrm:
12489 case VCVTPH2UQQZrmb:
12490 case VCVTPH2UQQZrmbk:
12491 case VCVTPH2UQQZrmbkz:
12492 case VCVTPH2UQQZrmk:
12493 case VCVTPH2UQQZrmkz:
12494 case VCVTPH2UQQZrr:
12495 case VCVTPH2UQQZrrb:
12496 case VCVTPH2UQQZrrbk:
12497 case VCVTPH2UQQZrrbkz:
12498 case VCVTPH2UQQZrrk:
12499 case VCVTPH2UQQZrrkz:
12500 return true;
12501 }
12502 return false;
12503}
12504
12505bool isPSLLD(unsigned Opcode) {
12506 switch (Opcode) {
12507 case MMX_PSLLDri:
12508 case MMX_PSLLDrm:
12509 case MMX_PSLLDrr:
12510 case PSLLDri:
12511 case PSLLDrm:
12512 case PSLLDrr:
12513 return true;
12514 }
12515 return false;
12516}
12517
12518bool isSAR(unsigned Opcode) {
12519 switch (Opcode) {
12520 case SAR16m1:
12521 case SAR16m1_EVEX:
12522 case SAR16m1_ND:
12523 case SAR16m1_NF:
12524 case SAR16m1_NF_ND:
12525 case SAR16mCL:
12526 case SAR16mCL_EVEX:
12527 case SAR16mCL_ND:
12528 case SAR16mCL_NF:
12529 case SAR16mCL_NF_ND:
12530 case SAR16mi:
12531 case SAR16mi_EVEX:
12532 case SAR16mi_ND:
12533 case SAR16mi_NF:
12534 case SAR16mi_NF_ND:
12535 case SAR16r1:
12536 case SAR16r1_EVEX:
12537 case SAR16r1_ND:
12538 case SAR16r1_NF:
12539 case SAR16r1_NF_ND:
12540 case SAR16rCL:
12541 case SAR16rCL_EVEX:
12542 case SAR16rCL_ND:
12543 case SAR16rCL_NF:
12544 case SAR16rCL_NF_ND:
12545 case SAR16ri:
12546 case SAR16ri_EVEX:
12547 case SAR16ri_ND:
12548 case SAR16ri_NF:
12549 case SAR16ri_NF_ND:
12550 case SAR32m1:
12551 case SAR32m1_EVEX:
12552 case SAR32m1_ND:
12553 case SAR32m1_NF:
12554 case SAR32m1_NF_ND:
12555 case SAR32mCL:
12556 case SAR32mCL_EVEX:
12557 case SAR32mCL_ND:
12558 case SAR32mCL_NF:
12559 case SAR32mCL_NF_ND:
12560 case SAR32mi:
12561 case SAR32mi_EVEX:
12562 case SAR32mi_ND:
12563 case SAR32mi_NF:
12564 case SAR32mi_NF_ND:
12565 case SAR32r1:
12566 case SAR32r1_EVEX:
12567 case SAR32r1_ND:
12568 case SAR32r1_NF:
12569 case SAR32r1_NF_ND:
12570 case SAR32rCL:
12571 case SAR32rCL_EVEX:
12572 case SAR32rCL_ND:
12573 case SAR32rCL_NF:
12574 case SAR32rCL_NF_ND:
12575 case SAR32ri:
12576 case SAR32ri_EVEX:
12577 case SAR32ri_ND:
12578 case SAR32ri_NF:
12579 case SAR32ri_NF_ND:
12580 case SAR64m1:
12581 case SAR64m1_EVEX:
12582 case SAR64m1_ND:
12583 case SAR64m1_NF:
12584 case SAR64m1_NF_ND:
12585 case SAR64mCL:
12586 case SAR64mCL_EVEX:
12587 case SAR64mCL_ND:
12588 case SAR64mCL_NF:
12589 case SAR64mCL_NF_ND:
12590 case SAR64mi:
12591 case SAR64mi_EVEX:
12592 case SAR64mi_ND:
12593 case SAR64mi_NF:
12594 case SAR64mi_NF_ND:
12595 case SAR64r1:
12596 case SAR64r1_EVEX:
12597 case SAR64r1_ND:
12598 case SAR64r1_NF:
12599 case SAR64r1_NF_ND:
12600 case SAR64rCL:
12601 case SAR64rCL_EVEX:
12602 case SAR64rCL_ND:
12603 case SAR64rCL_NF:
12604 case SAR64rCL_NF_ND:
12605 case SAR64ri:
12606 case SAR64ri_EVEX:
12607 case SAR64ri_ND:
12608 case SAR64ri_NF:
12609 case SAR64ri_NF_ND:
12610 case SAR8m1:
12611 case SAR8m1_EVEX:
12612 case SAR8m1_ND:
12613 case SAR8m1_NF:
12614 case SAR8m1_NF_ND:
12615 case SAR8mCL:
12616 case SAR8mCL_EVEX:
12617 case SAR8mCL_ND:
12618 case SAR8mCL_NF:
12619 case SAR8mCL_NF_ND:
12620 case SAR8mi:
12621 case SAR8mi_EVEX:
12622 case SAR8mi_ND:
12623 case SAR8mi_NF:
12624 case SAR8mi_NF_ND:
12625 case SAR8r1:
12626 case SAR8r1_EVEX:
12627 case SAR8r1_ND:
12628 case SAR8r1_NF:
12629 case SAR8r1_NF_ND:
12630 case SAR8rCL:
12631 case SAR8rCL_EVEX:
12632 case SAR8rCL_ND:
12633 case SAR8rCL_NF:
12634 case SAR8rCL_NF_ND:
12635 case SAR8ri:
12636 case SAR8ri_EVEX:
12637 case SAR8ri_ND:
12638 case SAR8ri_NF:
12639 case SAR8ri_NF_ND:
12640 return true;
12641 }
12642 return false;
12643}
12644
12645bool isLDTILECFG(unsigned Opcode) {
12646 switch (Opcode) {
12647 case LDTILECFG:
12648 case LDTILECFG_EVEX:
12649 return true;
12650 }
12651 return false;
12652}
12653
12654bool isPMINUB(unsigned Opcode) {
12655 switch (Opcode) {
12656 case MMX_PMINUBrm:
12657 case MMX_PMINUBrr:
12658 case PMINUBrm:
12659 case PMINUBrr:
12660 return true;
12661 }
12662 return false;
12663}
12664
12665bool isVCVTNEEBF162PS(unsigned Opcode) {
12666 switch (Opcode) {
12667 case VCVTNEEBF162PSYrm:
12668 case VCVTNEEBF162PSrm:
12669 return true;
12670 }
12671 return false;
12672}
12673
12674bool isMOVDIR64B(unsigned Opcode) {
12675 switch (Opcode) {
12676 case MOVDIR64B16:
12677 case MOVDIR64B32:
12678 case MOVDIR64B32_EVEX:
12679 case MOVDIR64B64:
12680 case MOVDIR64B64_EVEX:
12681 return true;
12682 }
12683 return false;
12684}
12685
12686bool isSQRTPS(unsigned Opcode) {
12687 switch (Opcode) {
12688 case SQRTPSm:
12689 case SQRTPSr:
12690 return true;
12691 }
12692 return false;
12693}
12694
12695bool isSTR(unsigned Opcode) {
12696 switch (Opcode) {
12697 case STR16r:
12698 case STR32r:
12699 case STR64r:
12700 case STRm:
12701 return true;
12702 }
12703 return false;
12704}
12705
12706bool isKANDNQ(unsigned Opcode) {
12707 return Opcode == KANDNQkk;
12708}
12709
12710bool isBSF(unsigned Opcode) {
12711 switch (Opcode) {
12712 case BSF16rm:
12713 case BSF16rr:
12714 case BSF32rm:
12715 case BSF32rr:
12716 case BSF64rm:
12717 case BSF64rr:
12718 return true;
12719 }
12720 return false;
12721}
12722
12723bool isINCSSPD(unsigned Opcode) {
12724 return Opcode == INCSSPD;
12725}
12726
12727bool isVPDPBUUDS(unsigned Opcode) {
12728 switch (Opcode) {
12729 case VPDPBUUDSYrm:
12730 case VPDPBUUDSYrr:
12731 case VPDPBUUDSZ128rm:
12732 case VPDPBUUDSZ128rmb:
12733 case VPDPBUUDSZ128rmbk:
12734 case VPDPBUUDSZ128rmbkz:
12735 case VPDPBUUDSZ128rmk:
12736 case VPDPBUUDSZ128rmkz:
12737 case VPDPBUUDSZ128rr:
12738 case VPDPBUUDSZ128rrk:
12739 case VPDPBUUDSZ128rrkz:
12740 case VPDPBUUDSZ256rm:
12741 case VPDPBUUDSZ256rmb:
12742 case VPDPBUUDSZ256rmbk:
12743 case VPDPBUUDSZ256rmbkz:
12744 case VPDPBUUDSZ256rmk:
12745 case VPDPBUUDSZ256rmkz:
12746 case VPDPBUUDSZ256rr:
12747 case VPDPBUUDSZ256rrk:
12748 case VPDPBUUDSZ256rrkz:
12749 case VPDPBUUDSZrm:
12750 case VPDPBUUDSZrmb:
12751 case VPDPBUUDSZrmbk:
12752 case VPDPBUUDSZrmbkz:
12753 case VPDPBUUDSZrmk:
12754 case VPDPBUUDSZrmkz:
12755 case VPDPBUUDSZrr:
12756 case VPDPBUUDSZrrk:
12757 case VPDPBUUDSZrrkz:
12758 case VPDPBUUDSrm:
12759 case VPDPBUUDSrr:
12760 return true;
12761 }
12762 return false;
12763}
12764
12765bool isCMPXCHG(unsigned Opcode) {
12766 switch (Opcode) {
12767 case CMPXCHG16rm:
12768 case CMPXCHG16rr:
12769 case CMPXCHG32rm:
12770 case CMPXCHG32rr:
12771 case CMPXCHG64rm:
12772 case CMPXCHG64rr:
12773 case CMPXCHG8rm:
12774 case CMPXCHG8rr:
12775 return true;
12776 }
12777 return false;
12778}
12779
12780bool isVPSIGNW(unsigned Opcode) {
12781 switch (Opcode) {
12782 case VPSIGNWYrm:
12783 case VPSIGNWYrr:
12784 case VPSIGNWrm:
12785 case VPSIGNWrr:
12786 return true;
12787 }
12788 return false;
12789}
12790
12791bool isVCOMISBF16(unsigned Opcode) {
12792 switch (Opcode) {
12793 case VCOMISBF16Zrm:
12794 case VCOMISBF16Zrr:
12795 return true;
12796 }
12797 return false;
12798}
12799
12800bool isLES(unsigned Opcode) {
12801 switch (Opcode) {
12802 case LES16rm:
12803 case LES32rm:
12804 return true;
12805 }
12806 return false;
12807}
12808
12809bool isCVTSS2SI(unsigned Opcode) {
12810 switch (Opcode) {
12811 case CVTSS2SI64rm_Int:
12812 case CVTSS2SI64rr_Int:
12813 case CVTSS2SIrm_Int:
12814 case CVTSS2SIrr_Int:
12815 return true;
12816 }
12817 return false;
12818}
12819
12820bool isPFACC(unsigned Opcode) {
12821 switch (Opcode) {
12822 case PFACCrm:
12823 case PFACCrr:
12824 return true;
12825 }
12826 return false;
12827}
12828
12829bool isFCOMPI(unsigned Opcode) {
12830 return Opcode == COM_FIPr;
12831}
12832
12833bool isPUNPCKHWD(unsigned Opcode) {
12834 switch (Opcode) {
12835 case MMX_PUNPCKHWDrm:
12836 case MMX_PUNPCKHWDrr:
12837 case PUNPCKHWDrm:
12838 case PUNPCKHWDrr:
12839 return true;
12840 }
12841 return false;
12842}
12843
12844bool isVPMOVUSWB(unsigned Opcode) {
12845 switch (Opcode) {
12846 case VPMOVUSWBZ128mr:
12847 case VPMOVUSWBZ128mrk:
12848 case VPMOVUSWBZ128rr:
12849 case VPMOVUSWBZ128rrk:
12850 case VPMOVUSWBZ128rrkz:
12851 case VPMOVUSWBZ256mr:
12852 case VPMOVUSWBZ256mrk:
12853 case VPMOVUSWBZ256rr:
12854 case VPMOVUSWBZ256rrk:
12855 case VPMOVUSWBZ256rrkz:
12856 case VPMOVUSWBZmr:
12857 case VPMOVUSWBZmrk:
12858 case VPMOVUSWBZrr:
12859 case VPMOVUSWBZrrk:
12860 case VPMOVUSWBZrrkz:
12861 return true;
12862 }
12863 return false;
12864}
12865
12866bool isVPTESTNMW(unsigned Opcode) {
12867 switch (Opcode) {
12868 case VPTESTNMWZ128rm:
12869 case VPTESTNMWZ128rmk:
12870 case VPTESTNMWZ128rr:
12871 case VPTESTNMWZ128rrk:
12872 case VPTESTNMWZ256rm:
12873 case VPTESTNMWZ256rmk:
12874 case VPTESTNMWZ256rr:
12875 case VPTESTNMWZ256rrk:
12876 case VPTESTNMWZrm:
12877 case VPTESTNMWZrmk:
12878 case VPTESTNMWZrr:
12879 case VPTESTNMWZrrk:
12880 return true;
12881 }
12882 return false;
12883}
12884
12885bool isVPMULDQ(unsigned Opcode) {
12886 switch (Opcode) {
12887 case VPMULDQYrm:
12888 case VPMULDQYrr:
12889 case VPMULDQZ128rm:
12890 case VPMULDQZ128rmb:
12891 case VPMULDQZ128rmbk:
12892 case VPMULDQZ128rmbkz:
12893 case VPMULDQZ128rmk:
12894 case VPMULDQZ128rmkz:
12895 case VPMULDQZ128rr:
12896 case VPMULDQZ128rrk:
12897 case VPMULDQZ128rrkz:
12898 case VPMULDQZ256rm:
12899 case VPMULDQZ256rmb:
12900 case VPMULDQZ256rmbk:
12901 case VPMULDQZ256rmbkz:
12902 case VPMULDQZ256rmk:
12903 case VPMULDQZ256rmkz:
12904 case VPMULDQZ256rr:
12905 case VPMULDQZ256rrk:
12906 case VPMULDQZ256rrkz:
12907 case VPMULDQZrm:
12908 case VPMULDQZrmb:
12909 case VPMULDQZrmbk:
12910 case VPMULDQZrmbkz:
12911 case VPMULDQZrmk:
12912 case VPMULDQZrmkz:
12913 case VPMULDQZrr:
12914 case VPMULDQZrrk:
12915 case VPMULDQZrrkz:
12916 case VPMULDQrm:
12917 case VPMULDQrr:
12918 return true;
12919 }
12920 return false;
12921}
12922
12923bool isSHRX(unsigned Opcode) {
12924 switch (Opcode) {
12925 case SHRX32rm:
12926 case SHRX32rm_EVEX:
12927 case SHRX32rr:
12928 case SHRX32rr_EVEX:
12929 case SHRX64rm:
12930 case SHRX64rm_EVEX:
12931 case SHRX64rr:
12932 case SHRX64rr_EVEX:
12933 return true;
12934 }
12935 return false;
12936}
12937
12938bool isKXORQ(unsigned Opcode) {
12939 return Opcode == KXORQkk;
12940}
12941
12942bool isVGETEXPSD(unsigned Opcode) {
12943 switch (Opcode) {
12944 case VGETEXPSDZm:
12945 case VGETEXPSDZmk:
12946 case VGETEXPSDZmkz:
12947 case VGETEXPSDZr:
12948 case VGETEXPSDZrb:
12949 case VGETEXPSDZrbk:
12950 case VGETEXPSDZrbkz:
12951 case VGETEXPSDZrk:
12952 case VGETEXPSDZrkz:
12953 return true;
12954 }
12955 return false;
12956}
12957
12958bool isV4FNMADDPS(unsigned Opcode) {
12959 switch (Opcode) {
12960 case V4FNMADDPSrm:
12961 case V4FNMADDPSrmk:
12962 case V4FNMADDPSrmkz:
12963 return true;
12964 }
12965 return false;
12966}
12967
12968bool isVFNMSUB231SD(unsigned Opcode) {
12969 switch (Opcode) {
12970 case VFNMSUB231SDZm_Int:
12971 case VFNMSUB231SDZmk_Int:
12972 case VFNMSUB231SDZmkz_Int:
12973 case VFNMSUB231SDZr_Int:
12974 case VFNMSUB231SDZrb_Int:
12975 case VFNMSUB231SDZrbk_Int:
12976 case VFNMSUB231SDZrbkz_Int:
12977 case VFNMSUB231SDZrk_Int:
12978 case VFNMSUB231SDZrkz_Int:
12979 case VFNMSUB231SDm_Int:
12980 case VFNMSUB231SDr_Int:
12981 return true;
12982 }
12983 return false;
12984}
12985
12986bool isVPSHLD(unsigned Opcode) {
12987 switch (Opcode) {
12988 case VPSHLDmr:
12989 case VPSHLDrm:
12990 case VPSHLDrr:
12991 case VPSHLDrr_REV:
12992 return true;
12993 }
12994 return false;
12995}
12996
12997bool isPAVGB(unsigned Opcode) {
12998 switch (Opcode) {
12999 case MMX_PAVGBrm:
13000 case MMX_PAVGBrr:
13001 case PAVGBrm:
13002 case PAVGBrr:
13003 return true;
13004 }
13005 return false;
13006}
13007
13008bool isPMOVZXBD(unsigned Opcode) {
13009 switch (Opcode) {
13010 case PMOVZXBDrm:
13011 case PMOVZXBDrr:
13012 return true;
13013 }
13014 return false;
13015}
13016
13017bool isKORTESTW(unsigned Opcode) {
13018 return Opcode == KORTESTWkk;
13019}
13020
13021bool isVSHUFPS(unsigned Opcode) {
13022 switch (Opcode) {
13023 case VSHUFPSYrmi:
13024 case VSHUFPSYrri:
13025 case VSHUFPSZ128rmbi:
13026 case VSHUFPSZ128rmbik:
13027 case VSHUFPSZ128rmbikz:
13028 case VSHUFPSZ128rmi:
13029 case VSHUFPSZ128rmik:
13030 case VSHUFPSZ128rmikz:
13031 case VSHUFPSZ128rri:
13032 case VSHUFPSZ128rrik:
13033 case VSHUFPSZ128rrikz:
13034 case VSHUFPSZ256rmbi:
13035 case VSHUFPSZ256rmbik:
13036 case VSHUFPSZ256rmbikz:
13037 case VSHUFPSZ256rmi:
13038 case VSHUFPSZ256rmik:
13039 case VSHUFPSZ256rmikz:
13040 case VSHUFPSZ256rri:
13041 case VSHUFPSZ256rrik:
13042 case VSHUFPSZ256rrikz:
13043 case VSHUFPSZrmbi:
13044 case VSHUFPSZrmbik:
13045 case VSHUFPSZrmbikz:
13046 case VSHUFPSZrmi:
13047 case VSHUFPSZrmik:
13048 case VSHUFPSZrmikz:
13049 case VSHUFPSZrri:
13050 case VSHUFPSZrrik:
13051 case VSHUFPSZrrikz:
13052 case VSHUFPSrmi:
13053 case VSHUFPSrri:
13054 return true;
13055 }
13056 return false;
13057}
13058
13059bool isAESENCWIDE128KL(unsigned Opcode) {
13060 return Opcode == AESENCWIDE128KL;
13061}
13062
13063bool isVPXORD(unsigned Opcode) {
13064 switch (Opcode) {
13065 case VPXORDZ128rm:
13066 case VPXORDZ128rmb:
13067 case VPXORDZ128rmbk:
13068 case VPXORDZ128rmbkz:
13069 case VPXORDZ128rmk:
13070 case VPXORDZ128rmkz:
13071 case VPXORDZ128rr:
13072 case VPXORDZ128rrk:
13073 case VPXORDZ128rrkz:
13074 case VPXORDZ256rm:
13075 case VPXORDZ256rmb:
13076 case VPXORDZ256rmbk:
13077 case VPXORDZ256rmbkz:
13078 case VPXORDZ256rmk:
13079 case VPXORDZ256rmkz:
13080 case VPXORDZ256rr:
13081 case VPXORDZ256rrk:
13082 case VPXORDZ256rrkz:
13083 case VPXORDZrm:
13084 case VPXORDZrmb:
13085 case VPXORDZrmbk:
13086 case VPXORDZrmbkz:
13087 case VPXORDZrmk:
13088 case VPXORDZrmkz:
13089 case VPXORDZrr:
13090 case VPXORDZrrk:
13091 case VPXORDZrrkz:
13092 return true;
13093 }
13094 return false;
13095}
13096
13097bool isVPSHAW(unsigned Opcode) {
13098 switch (Opcode) {
13099 case VPSHAWmr:
13100 case VPSHAWrm:
13101 case VPSHAWrr:
13102 case VPSHAWrr_REV:
13103 return true;
13104 }
13105 return false;
13106}
13107
13108bool isVFMSUB132BF16(unsigned Opcode) {
13109 switch (Opcode) {
13110 case VFMSUB132BF16Z128m:
13111 case VFMSUB132BF16Z128mb:
13112 case VFMSUB132BF16Z128mbk:
13113 case VFMSUB132BF16Z128mbkz:
13114 case VFMSUB132BF16Z128mk:
13115 case VFMSUB132BF16Z128mkz:
13116 case VFMSUB132BF16Z128r:
13117 case VFMSUB132BF16Z128rk:
13118 case VFMSUB132BF16Z128rkz:
13119 case VFMSUB132BF16Z256m:
13120 case VFMSUB132BF16Z256mb:
13121 case VFMSUB132BF16Z256mbk:
13122 case VFMSUB132BF16Z256mbkz:
13123 case VFMSUB132BF16Z256mk:
13124 case VFMSUB132BF16Z256mkz:
13125 case VFMSUB132BF16Z256r:
13126 case VFMSUB132BF16Z256rk:
13127 case VFMSUB132BF16Z256rkz:
13128 case VFMSUB132BF16Zm:
13129 case VFMSUB132BF16Zmb:
13130 case VFMSUB132BF16Zmbk:
13131 case VFMSUB132BF16Zmbkz:
13132 case VFMSUB132BF16Zmk:
13133 case VFMSUB132BF16Zmkz:
13134 case VFMSUB132BF16Zr:
13135 case VFMSUB132BF16Zrk:
13136 case VFMSUB132BF16Zrkz:
13137 return true;
13138 }
13139 return false;
13140}
13141
13142bool isVPERMT2B(unsigned Opcode) {
13143 switch (Opcode) {
13144 case VPERMT2BZ128rm:
13145 case VPERMT2BZ128rmk:
13146 case VPERMT2BZ128rmkz:
13147 case VPERMT2BZ128rr:
13148 case VPERMT2BZ128rrk:
13149 case VPERMT2BZ128rrkz:
13150 case VPERMT2BZ256rm:
13151 case VPERMT2BZ256rmk:
13152 case VPERMT2BZ256rmkz:
13153 case VPERMT2BZ256rr:
13154 case VPERMT2BZ256rrk:
13155 case VPERMT2BZ256rrkz:
13156 case VPERMT2BZrm:
13157 case VPERMT2BZrmk:
13158 case VPERMT2BZrmkz:
13159 case VPERMT2BZrr:
13160 case VPERMT2BZrrk:
13161 case VPERMT2BZrrkz:
13162 return true;
13163 }
13164 return false;
13165}
13166
13167bool isVFMADD213PD(unsigned Opcode) {
13168 switch (Opcode) {
13169 case VFMADD213PDYm:
13170 case VFMADD213PDYr:
13171 case VFMADD213PDZ128m:
13172 case VFMADD213PDZ128mb:
13173 case VFMADD213PDZ128mbk:
13174 case VFMADD213PDZ128mbkz:
13175 case VFMADD213PDZ128mk:
13176 case VFMADD213PDZ128mkz:
13177 case VFMADD213PDZ128r:
13178 case VFMADD213PDZ128rk:
13179 case VFMADD213PDZ128rkz:
13180 case VFMADD213PDZ256m:
13181 case VFMADD213PDZ256mb:
13182 case VFMADD213PDZ256mbk:
13183 case VFMADD213PDZ256mbkz:
13184 case VFMADD213PDZ256mk:
13185 case VFMADD213PDZ256mkz:
13186 case VFMADD213PDZ256r:
13187 case VFMADD213PDZ256rk:
13188 case VFMADD213PDZ256rkz:
13189 case VFMADD213PDZm:
13190 case VFMADD213PDZmb:
13191 case VFMADD213PDZmbk:
13192 case VFMADD213PDZmbkz:
13193 case VFMADD213PDZmk:
13194 case VFMADD213PDZmkz:
13195 case VFMADD213PDZr:
13196 case VFMADD213PDZrb:
13197 case VFMADD213PDZrbk:
13198 case VFMADD213PDZrbkz:
13199 case VFMADD213PDZrk:
13200 case VFMADD213PDZrkz:
13201 case VFMADD213PDm:
13202 case VFMADD213PDr:
13203 return true;
13204 }
13205 return false;
13206}
13207
13208bool isVPGATHERQD(unsigned Opcode) {
13209 switch (Opcode) {
13210 case VPGATHERQDYrm:
13211 case VPGATHERQDZ128rm:
13212 case VPGATHERQDZ256rm:
13213 case VPGATHERQDZrm:
13214 case VPGATHERQDrm:
13215 return true;
13216 }
13217 return false;
13218}
13219
13220bool isVFNMSUB213BF16(unsigned Opcode) {
13221 switch (Opcode) {
13222 case VFNMSUB213BF16Z128m:
13223 case VFNMSUB213BF16Z128mb:
13224 case VFNMSUB213BF16Z128mbk:
13225 case VFNMSUB213BF16Z128mbkz:
13226 case VFNMSUB213BF16Z128mk:
13227 case VFNMSUB213BF16Z128mkz:
13228 case VFNMSUB213BF16Z128r:
13229 case VFNMSUB213BF16Z128rk:
13230 case VFNMSUB213BF16Z128rkz:
13231 case VFNMSUB213BF16Z256m:
13232 case VFNMSUB213BF16Z256mb:
13233 case VFNMSUB213BF16Z256mbk:
13234 case VFNMSUB213BF16Z256mbkz:
13235 case VFNMSUB213BF16Z256mk:
13236 case VFNMSUB213BF16Z256mkz:
13237 case VFNMSUB213BF16Z256r:
13238 case VFNMSUB213BF16Z256rk:
13239 case VFNMSUB213BF16Z256rkz:
13240 case VFNMSUB213BF16Zm:
13241 case VFNMSUB213BF16Zmb:
13242 case VFNMSUB213BF16Zmbk:
13243 case VFNMSUB213BF16Zmbkz:
13244 case VFNMSUB213BF16Zmk:
13245 case VFNMSUB213BF16Zmkz:
13246 case VFNMSUB213BF16Zr:
13247 case VFNMSUB213BF16Zrk:
13248 case VFNMSUB213BF16Zrkz:
13249 return true;
13250 }
13251 return false;
13252}
13253
13254bool isVCVTPS2IBS(unsigned Opcode) {
13255 switch (Opcode) {
13256 case VCVTPS2IBSZ128rm:
13257 case VCVTPS2IBSZ128rmb:
13258 case VCVTPS2IBSZ128rmbk:
13259 case VCVTPS2IBSZ128rmbkz:
13260 case VCVTPS2IBSZ128rmk:
13261 case VCVTPS2IBSZ128rmkz:
13262 case VCVTPS2IBSZ128rr:
13263 case VCVTPS2IBSZ128rrk:
13264 case VCVTPS2IBSZ128rrkz:
13265 case VCVTPS2IBSZ256rm:
13266 case VCVTPS2IBSZ256rmb:
13267 case VCVTPS2IBSZ256rmbk:
13268 case VCVTPS2IBSZ256rmbkz:
13269 case VCVTPS2IBSZ256rmk:
13270 case VCVTPS2IBSZ256rmkz:
13271 case VCVTPS2IBSZ256rr:
13272 case VCVTPS2IBSZ256rrk:
13273 case VCVTPS2IBSZ256rrkz:
13274 case VCVTPS2IBSZrm:
13275 case VCVTPS2IBSZrmb:
13276 case VCVTPS2IBSZrmbk:
13277 case VCVTPS2IBSZrmbkz:
13278 case VCVTPS2IBSZrmk:
13279 case VCVTPS2IBSZrmkz:
13280 case VCVTPS2IBSZrr:
13281 case VCVTPS2IBSZrrb:
13282 case VCVTPS2IBSZrrbk:
13283 case VCVTPS2IBSZrrbkz:
13284 case VCVTPS2IBSZrrk:
13285 case VCVTPS2IBSZrrkz:
13286 return true;
13287 }
13288 return false;
13289}
13290
13291bool isVPCMPGTW(unsigned Opcode) {
13292 switch (Opcode) {
13293 case VPCMPGTWYrm:
13294 case VPCMPGTWYrr:
13295 case VPCMPGTWZ128rm:
13296 case VPCMPGTWZ128rmk:
13297 case VPCMPGTWZ128rr:
13298 case VPCMPGTWZ128rrk:
13299 case VPCMPGTWZ256rm:
13300 case VPCMPGTWZ256rmk:
13301 case VPCMPGTWZ256rr:
13302 case VPCMPGTWZ256rrk:
13303 case VPCMPGTWZrm:
13304 case VPCMPGTWZrmk:
13305 case VPCMPGTWZrr:
13306 case VPCMPGTWZrrk:
13307 case VPCMPGTWrm:
13308 case VPCMPGTWrr:
13309 return true;
13310 }
13311 return false;
13312}
13313
13314bool isVMOVRSB(unsigned Opcode) {
13315 switch (Opcode) {
13316 case VMOVRSBZ128m:
13317 case VMOVRSBZ128mk:
13318 case VMOVRSBZ128mkz:
13319 case VMOVRSBZ256m:
13320 case VMOVRSBZ256mk:
13321 case VMOVRSBZ256mkz:
13322 case VMOVRSBZm:
13323 case VMOVRSBZmk:
13324 case VMOVRSBZmkz:
13325 return true;
13326 }
13327 return false;
13328}
13329
13330bool isVGETMANTSH(unsigned Opcode) {
13331 switch (Opcode) {
13332 case VGETMANTSHZrmi:
13333 case VGETMANTSHZrmik:
13334 case VGETMANTSHZrmikz:
13335 case VGETMANTSHZrri:
13336 case VGETMANTSHZrrib:
13337 case VGETMANTSHZrribk:
13338 case VGETMANTSHZrribkz:
13339 case VGETMANTSHZrrik:
13340 case VGETMANTSHZrrikz:
13341 return true;
13342 }
13343 return false;
13344}
13345
13346bool isVANDPS(unsigned Opcode) {
13347 switch (Opcode) {
13348 case VANDPSYrm:
13349 case VANDPSYrr:
13350 case VANDPSZ128rm:
13351 case VANDPSZ128rmb:
13352 case VANDPSZ128rmbk:
13353 case VANDPSZ128rmbkz:
13354 case VANDPSZ128rmk:
13355 case VANDPSZ128rmkz:
13356 case VANDPSZ128rr:
13357 case VANDPSZ128rrk:
13358 case VANDPSZ128rrkz:
13359 case VANDPSZ256rm:
13360 case VANDPSZ256rmb:
13361 case VANDPSZ256rmbk:
13362 case VANDPSZ256rmbkz:
13363 case VANDPSZ256rmk:
13364 case VANDPSZ256rmkz:
13365 case VANDPSZ256rr:
13366 case VANDPSZ256rrk:
13367 case VANDPSZ256rrkz:
13368 case VANDPSZrm:
13369 case VANDPSZrmb:
13370 case VANDPSZrmbk:
13371 case VANDPSZrmbkz:
13372 case VANDPSZrmk:
13373 case VANDPSZrmkz:
13374 case VANDPSZrr:
13375 case VANDPSZrrk:
13376 case VANDPSZrrkz:
13377 case VANDPSrm:
13378 case VANDPSrr:
13379 return true;
13380 }
13381 return false;
13382}
13383
13384bool isVDIVPS(unsigned Opcode) {
13385 switch (Opcode) {
13386 case VDIVPSYrm:
13387 case VDIVPSYrr:
13388 case VDIVPSZ128rm:
13389 case VDIVPSZ128rmb:
13390 case VDIVPSZ128rmbk:
13391 case VDIVPSZ128rmbkz:
13392 case VDIVPSZ128rmk:
13393 case VDIVPSZ128rmkz:
13394 case VDIVPSZ128rr:
13395 case VDIVPSZ128rrk:
13396 case VDIVPSZ128rrkz:
13397 case VDIVPSZ256rm:
13398 case VDIVPSZ256rmb:
13399 case VDIVPSZ256rmbk:
13400 case VDIVPSZ256rmbkz:
13401 case VDIVPSZ256rmk:
13402 case VDIVPSZ256rmkz:
13403 case VDIVPSZ256rr:
13404 case VDIVPSZ256rrk:
13405 case VDIVPSZ256rrkz:
13406 case VDIVPSZrm:
13407 case VDIVPSZrmb:
13408 case VDIVPSZrmbk:
13409 case VDIVPSZrmbkz:
13410 case VDIVPSZrmk:
13411 case VDIVPSZrmkz:
13412 case VDIVPSZrr:
13413 case VDIVPSZrrb:
13414 case VDIVPSZrrbk:
13415 case VDIVPSZrrbkz:
13416 case VDIVPSZrrk:
13417 case VDIVPSZrrkz:
13418 case VDIVPSrm:
13419 case VDIVPSrr:
13420 return true;
13421 }
13422 return false;
13423}
13424
13425bool isVANDNPS(unsigned Opcode) {
13426 switch (Opcode) {
13427 case VANDNPSYrm:
13428 case VANDNPSYrr:
13429 case VANDNPSZ128rm:
13430 case VANDNPSZ128rmb:
13431 case VANDNPSZ128rmbk:
13432 case VANDNPSZ128rmbkz:
13433 case VANDNPSZ128rmk:
13434 case VANDNPSZ128rmkz:
13435 case VANDNPSZ128rr:
13436 case VANDNPSZ128rrk:
13437 case VANDNPSZ128rrkz:
13438 case VANDNPSZ256rm:
13439 case VANDNPSZ256rmb:
13440 case VANDNPSZ256rmbk:
13441 case VANDNPSZ256rmbkz:
13442 case VANDNPSZ256rmk:
13443 case VANDNPSZ256rmkz:
13444 case VANDNPSZ256rr:
13445 case VANDNPSZ256rrk:
13446 case VANDNPSZ256rrkz:
13447 case VANDNPSZrm:
13448 case VANDNPSZrmb:
13449 case VANDNPSZrmbk:
13450 case VANDNPSZrmbkz:
13451 case VANDNPSZrmk:
13452 case VANDNPSZrmkz:
13453 case VANDNPSZrr:
13454 case VANDNPSZrrk:
13455 case VANDNPSZrrkz:
13456 case VANDNPSrm:
13457 case VANDNPSrr:
13458 return true;
13459 }
13460 return false;
13461}
13462
13463bool isVPBROADCASTW(unsigned Opcode) {
13464 switch (Opcode) {
13465 case VPBROADCASTWYrm:
13466 case VPBROADCASTWYrr:
13467 case VPBROADCASTWZ128rm:
13468 case VPBROADCASTWZ128rmk:
13469 case VPBROADCASTWZ128rmkz:
13470 case VPBROADCASTWZ128rr:
13471 case VPBROADCASTWZ128rrk:
13472 case VPBROADCASTWZ128rrkz:
13473 case VPBROADCASTWZ256rm:
13474 case VPBROADCASTWZ256rmk:
13475 case VPBROADCASTWZ256rmkz:
13476 case VPBROADCASTWZ256rr:
13477 case VPBROADCASTWZ256rrk:
13478 case VPBROADCASTWZ256rrkz:
13479 case VPBROADCASTWZrm:
13480 case VPBROADCASTWZrmk:
13481 case VPBROADCASTWZrmkz:
13482 case VPBROADCASTWZrr:
13483 case VPBROADCASTWZrrk:
13484 case VPBROADCASTWZrrkz:
13485 case VPBROADCASTWrZ128rr:
13486 case VPBROADCASTWrZ128rrk:
13487 case VPBROADCASTWrZ128rrkz:
13488 case VPBROADCASTWrZ256rr:
13489 case VPBROADCASTWrZ256rrk:
13490 case VPBROADCASTWrZ256rrkz:
13491 case VPBROADCASTWrZrr:
13492 case VPBROADCASTWrZrrk:
13493 case VPBROADCASTWrZrrkz:
13494 case VPBROADCASTWrm:
13495 case VPBROADCASTWrr:
13496 return true;
13497 }
13498 return false;
13499}
13500
13501bool isFLDL2T(unsigned Opcode) {
13502 return Opcode == FLDL2T;
13503}
13504
13505bool isVPERMB(unsigned Opcode) {
13506 switch (Opcode) {
13507 case VPERMBZ128rm:
13508 case VPERMBZ128rmk:
13509 case VPERMBZ128rmkz:
13510 case VPERMBZ128rr:
13511 case VPERMBZ128rrk:
13512 case VPERMBZ128rrkz:
13513 case VPERMBZ256rm:
13514 case VPERMBZ256rmk:
13515 case VPERMBZ256rmkz:
13516 case VPERMBZ256rr:
13517 case VPERMBZ256rrk:
13518 case VPERMBZ256rrkz:
13519 case VPERMBZrm:
13520 case VPERMBZrmk:
13521 case VPERMBZrmkz:
13522 case VPERMBZrr:
13523 case VPERMBZrrk:
13524 case VPERMBZrrkz:
13525 return true;
13526 }
13527 return false;
13528}
13529
13530bool isFCMOVNBE(unsigned Opcode) {
13531 return Opcode == CMOVNBE_F;
13532}
13533
13534bool isVCVTTPH2W(unsigned Opcode) {
13535 switch (Opcode) {
13536 case VCVTTPH2WZ128rm:
13537 case VCVTTPH2WZ128rmb:
13538 case VCVTTPH2WZ128rmbk:
13539 case VCVTTPH2WZ128rmbkz:
13540 case VCVTTPH2WZ128rmk:
13541 case VCVTTPH2WZ128rmkz:
13542 case VCVTTPH2WZ128rr:
13543 case VCVTTPH2WZ128rrk:
13544 case VCVTTPH2WZ128rrkz:
13545 case VCVTTPH2WZ256rm:
13546 case VCVTTPH2WZ256rmb:
13547 case VCVTTPH2WZ256rmbk:
13548 case VCVTTPH2WZ256rmbkz:
13549 case VCVTTPH2WZ256rmk:
13550 case VCVTTPH2WZ256rmkz:
13551 case VCVTTPH2WZ256rr:
13552 case VCVTTPH2WZ256rrk:
13553 case VCVTTPH2WZ256rrkz:
13554 case VCVTTPH2WZrm:
13555 case VCVTTPH2WZrmb:
13556 case VCVTTPH2WZrmbk:
13557 case VCVTTPH2WZrmbkz:
13558 case VCVTTPH2WZrmk:
13559 case VCVTTPH2WZrmkz:
13560 case VCVTTPH2WZrr:
13561 case VCVTTPH2WZrrb:
13562 case VCVTTPH2WZrrbk:
13563 case VCVTTPH2WZrrbkz:
13564 case VCVTTPH2WZrrk:
13565 case VCVTTPH2WZrrkz:
13566 return true;
13567 }
13568 return false;
13569}
13570
13571bool isPMOVZXBQ(unsigned Opcode) {
13572 switch (Opcode) {
13573 case PMOVZXBQrm:
13574 case PMOVZXBQrr:
13575 return true;
13576 }
13577 return false;
13578}
13579
13580bool isPF2ID(unsigned Opcode) {
13581 switch (Opcode) {
13582 case PF2IDrm:
13583 case PF2IDrr:
13584 return true;
13585 }
13586 return false;
13587}
13588
13589bool isVFNMADD132PD(unsigned Opcode) {
13590 switch (Opcode) {
13591 case VFNMADD132PDYm:
13592 case VFNMADD132PDYr:
13593 case VFNMADD132PDZ128m:
13594 case VFNMADD132PDZ128mb:
13595 case VFNMADD132PDZ128mbk:
13596 case VFNMADD132PDZ128mbkz:
13597 case VFNMADD132PDZ128mk:
13598 case VFNMADD132PDZ128mkz:
13599 case VFNMADD132PDZ128r:
13600 case VFNMADD132PDZ128rk:
13601 case VFNMADD132PDZ128rkz:
13602 case VFNMADD132PDZ256m:
13603 case VFNMADD132PDZ256mb:
13604 case VFNMADD132PDZ256mbk:
13605 case VFNMADD132PDZ256mbkz:
13606 case VFNMADD132PDZ256mk:
13607 case VFNMADD132PDZ256mkz:
13608 case VFNMADD132PDZ256r:
13609 case VFNMADD132PDZ256rk:
13610 case VFNMADD132PDZ256rkz:
13611 case VFNMADD132PDZm:
13612 case VFNMADD132PDZmb:
13613 case VFNMADD132PDZmbk:
13614 case VFNMADD132PDZmbkz:
13615 case VFNMADD132PDZmk:
13616 case VFNMADD132PDZmkz:
13617 case VFNMADD132PDZr:
13618 case VFNMADD132PDZrb:
13619 case VFNMADD132PDZrbk:
13620 case VFNMADD132PDZrbkz:
13621 case VFNMADD132PDZrk:
13622 case VFNMADD132PDZrkz:
13623 case VFNMADD132PDm:
13624 case VFNMADD132PDr:
13625 return true;
13626 }
13627 return false;
13628}
13629
13630bool isPMULHRSW(unsigned Opcode) {
13631 switch (Opcode) {
13632 case MMX_PMULHRSWrm:
13633 case MMX_PMULHRSWrr:
13634 case PMULHRSWrm:
13635 case PMULHRSWrr:
13636 return true;
13637 }
13638 return false;
13639}
13640
13641bool isKADDD(unsigned Opcode) {
13642 return Opcode == KADDDkk;
13643}
13644
13645bool isVFNMSUB132SH(unsigned Opcode) {
13646 switch (Opcode) {
13647 case VFNMSUB132SHZm_Int:
13648 case VFNMSUB132SHZmk_Int:
13649 case VFNMSUB132SHZmkz_Int:
13650 case VFNMSUB132SHZr_Int:
13651 case VFNMSUB132SHZrb_Int:
13652 case VFNMSUB132SHZrbk_Int:
13653 case VFNMSUB132SHZrbkz_Int:
13654 case VFNMSUB132SHZrk_Int:
13655 case VFNMSUB132SHZrkz_Int:
13656 return true;
13657 }
13658 return false;
13659}
13660
13661bool isUIRET(unsigned Opcode) {
13662 return Opcode == UIRET;
13663}
13664
13665bool isBSR(unsigned Opcode) {
13666 switch (Opcode) {
13667 case BSR16rm:
13668 case BSR16rr:
13669 case BSR32rm:
13670 case BSR32rr:
13671 case BSR64rm:
13672 case BSR64rr:
13673 return true;
13674 }
13675 return false;
13676}
13677
13678bool isPCMPEQQ(unsigned Opcode) {
13679 switch (Opcode) {
13680 case PCMPEQQrm:
13681 case PCMPEQQrr:
13682 return true;
13683 }
13684 return false;
13685}
13686
13687bool isCDQ(unsigned Opcode) {
13688 return Opcode == CDQ;
13689}
13690
13691bool isPMAXSW(unsigned Opcode) {
13692 switch (Opcode) {
13693 case MMX_PMAXSWrm:
13694 case MMX_PMAXSWrr:
13695 case PMAXSWrm:
13696 case PMAXSWrr:
13697 return true;
13698 }
13699 return false;
13700}
13701
13702bool isSIDTD(unsigned Opcode) {
13703 return Opcode == SIDT32m;
13704}
13705
13706bool isVCVTPS2PHX(unsigned Opcode) {
13707 switch (Opcode) {
13708 case VCVTPS2PHXZ128rm:
13709 case VCVTPS2PHXZ128rmb:
13710 case VCVTPS2PHXZ128rmbk:
13711 case VCVTPS2PHXZ128rmbkz:
13712 case VCVTPS2PHXZ128rmk:
13713 case VCVTPS2PHXZ128rmkz:
13714 case VCVTPS2PHXZ128rr:
13715 case VCVTPS2PHXZ128rrk:
13716 case VCVTPS2PHXZ128rrkz:
13717 case VCVTPS2PHXZ256rm:
13718 case VCVTPS2PHXZ256rmb:
13719 case VCVTPS2PHXZ256rmbk:
13720 case VCVTPS2PHXZ256rmbkz:
13721 case VCVTPS2PHXZ256rmk:
13722 case VCVTPS2PHXZ256rmkz:
13723 case VCVTPS2PHXZ256rr:
13724 case VCVTPS2PHXZ256rrk:
13725 case VCVTPS2PHXZ256rrkz:
13726 case VCVTPS2PHXZrm:
13727 case VCVTPS2PHXZrmb:
13728 case VCVTPS2PHXZrmbk:
13729 case VCVTPS2PHXZrmbkz:
13730 case VCVTPS2PHXZrmk:
13731 case VCVTPS2PHXZrmkz:
13732 case VCVTPS2PHXZrr:
13733 case VCVTPS2PHXZrrb:
13734 case VCVTPS2PHXZrrbk:
13735 case VCVTPS2PHXZrrbkz:
13736 case VCVTPS2PHXZrrk:
13737 case VCVTPS2PHXZrrkz:
13738 return true;
13739 }
13740 return false;
13741}
13742
13743bool isVPSLLVQ(unsigned Opcode) {
13744 switch (Opcode) {
13745 case VPSLLVQYrm:
13746 case VPSLLVQYrr:
13747 case VPSLLVQZ128rm:
13748 case VPSLLVQZ128rmb:
13749 case VPSLLVQZ128rmbk:
13750 case VPSLLVQZ128rmbkz:
13751 case VPSLLVQZ128rmk:
13752 case VPSLLVQZ128rmkz:
13753 case VPSLLVQZ128rr:
13754 case VPSLLVQZ128rrk:
13755 case VPSLLVQZ128rrkz:
13756 case VPSLLVQZ256rm:
13757 case VPSLLVQZ256rmb:
13758 case VPSLLVQZ256rmbk:
13759 case VPSLLVQZ256rmbkz:
13760 case VPSLLVQZ256rmk:
13761 case VPSLLVQZ256rmkz:
13762 case VPSLLVQZ256rr:
13763 case VPSLLVQZ256rrk:
13764 case VPSLLVQZ256rrkz:
13765 case VPSLLVQZrm:
13766 case VPSLLVQZrmb:
13767 case VPSLLVQZrmbk:
13768 case VPSLLVQZrmbkz:
13769 case VPSLLVQZrmk:
13770 case VPSLLVQZrmkz:
13771 case VPSLLVQZrr:
13772 case VPSLLVQZrrk:
13773 case VPSLLVQZrrkz:
13774 case VPSLLVQrm:
13775 case VPSLLVQrr:
13776 return true;
13777 }
13778 return false;
13779}
13780
13781bool isMOVQ(unsigned Opcode) {
13782 switch (Opcode) {
13783 case MMX_MOVD64from64mr:
13784 case MMX_MOVD64from64rr:
13785 case MMX_MOVD64to64rm:
13786 case MMX_MOVD64to64rr:
13787 case MMX_MOVQ64mr:
13788 case MMX_MOVQ64rm:
13789 case MMX_MOVQ64rr:
13790 case MMX_MOVQ64rr_REV:
13791 case MOV64toPQIrm:
13792 case MOV64toPQIrr:
13793 case MOVPQI2QImr:
13794 case MOVPQI2QIrr:
13795 case MOVPQIto64mr:
13796 case MOVPQIto64rr:
13797 case MOVQI2PQIrm:
13798 case MOVZPQILo2PQIrr:
13799 return true;
13800 }
13801 return false;
13802}
13803
13804bool isPREFETCH(unsigned Opcode) {
13805 return Opcode == PREFETCH;
13806}
13807
13808bool isVCMPBF16(unsigned Opcode) {
13809 switch (Opcode) {
13810 case VCMPBF16Z128rmbi:
13811 case VCMPBF16Z128rmbik:
13812 case VCMPBF16Z128rmi:
13813 case VCMPBF16Z128rmik:
13814 case VCMPBF16Z128rri:
13815 case VCMPBF16Z128rrik:
13816 case VCMPBF16Z256rmbi:
13817 case VCMPBF16Z256rmbik:
13818 case VCMPBF16Z256rmi:
13819 case VCMPBF16Z256rmik:
13820 case VCMPBF16Z256rri:
13821 case VCMPBF16Z256rrik:
13822 case VCMPBF16Zrmbi:
13823 case VCMPBF16Zrmbik:
13824 case VCMPBF16Zrmi:
13825 case VCMPBF16Zrmik:
13826 case VCMPBF16Zrri:
13827 case VCMPBF16Zrrik:
13828 return true;
13829 }
13830 return false;
13831}
13832
13833bool isVBMACOR16X16X16(unsigned Opcode) {
13834 switch (Opcode) {
13835 case VBMACORZ256rm:
13836 case VBMACORZ256rmb:
13837 case VBMACORZ256rmbk:
13838 case VBMACORZ256rmbkz:
13839 case VBMACORZ256rmk:
13840 case VBMACORZ256rmkz:
13841 case VBMACORZ256rr:
13842 case VBMACORZ256rrk:
13843 case VBMACORZ256rrkz:
13844 case VBMACORZrm:
13845 case VBMACORZrmb:
13846 case VBMACORZrmbk:
13847 case VBMACORZrmbkz:
13848 case VBMACORZrmk:
13849 case VBMACORZrmkz:
13850 case VBMACORZrr:
13851 case VBMACORZrrk:
13852 case VBMACORZrrkz:
13853 return true;
13854 }
13855 return false;
13856}
13857
13858bool isCLRSSBSY(unsigned Opcode) {
13859 return Opcode == CLRSSBSY;
13860}
13861
13862bool isTCVTROWPS2PHL(unsigned Opcode) {
13863 switch (Opcode) {
13864 case TCVTROWPS2PHLrte:
13865 case TCVTROWPS2PHLrti:
13866 return true;
13867 }
13868 return false;
13869}
13870
13871bool isPSHUFW(unsigned Opcode) {
13872 switch (Opcode) {
13873 case MMX_PSHUFWmi:
13874 case MMX_PSHUFWri:
13875 return true;
13876 }
13877 return false;
13878}
13879
13880bool isVPDPWSUDS(unsigned Opcode) {
13881 switch (Opcode) {
13882 case VPDPWSUDSYrm:
13883 case VPDPWSUDSYrr:
13884 case VPDPWSUDSZ128rm:
13885 case VPDPWSUDSZ128rmb:
13886 case VPDPWSUDSZ128rmbk:
13887 case VPDPWSUDSZ128rmbkz:
13888 case VPDPWSUDSZ128rmk:
13889 case VPDPWSUDSZ128rmkz:
13890 case VPDPWSUDSZ128rr:
13891 case VPDPWSUDSZ128rrk:
13892 case VPDPWSUDSZ128rrkz:
13893 case VPDPWSUDSZ256rm:
13894 case VPDPWSUDSZ256rmb:
13895 case VPDPWSUDSZ256rmbk:
13896 case VPDPWSUDSZ256rmbkz:
13897 case VPDPWSUDSZ256rmk:
13898 case VPDPWSUDSZ256rmkz:
13899 case VPDPWSUDSZ256rr:
13900 case VPDPWSUDSZ256rrk:
13901 case VPDPWSUDSZ256rrkz:
13902 case VPDPWSUDSZrm:
13903 case VPDPWSUDSZrmb:
13904 case VPDPWSUDSZrmbk:
13905 case VPDPWSUDSZrmbkz:
13906 case VPDPWSUDSZrmk:
13907 case VPDPWSUDSZrmkz:
13908 case VPDPWSUDSZrr:
13909 case VPDPWSUDSZrrk:
13910 case VPDPWSUDSZrrkz:
13911 case VPDPWSUDSrm:
13912 case VPDPWSUDSrr:
13913 return true;
13914 }
13915 return false;
13916}
13917
13918bool isVPMOVSXBQ(unsigned Opcode) {
13919 switch (Opcode) {
13920 case VPMOVSXBQYrm:
13921 case VPMOVSXBQYrr:
13922 case VPMOVSXBQZ128rm:
13923 case VPMOVSXBQZ128rmk:
13924 case VPMOVSXBQZ128rmkz:
13925 case VPMOVSXBQZ128rr:
13926 case VPMOVSXBQZ128rrk:
13927 case VPMOVSXBQZ128rrkz:
13928 case VPMOVSXBQZ256rm:
13929 case VPMOVSXBQZ256rmk:
13930 case VPMOVSXBQZ256rmkz:
13931 case VPMOVSXBQZ256rr:
13932 case VPMOVSXBQZ256rrk:
13933 case VPMOVSXBQZ256rrkz:
13934 case VPMOVSXBQZrm:
13935 case VPMOVSXBQZrmk:
13936 case VPMOVSXBQZrmkz:
13937 case VPMOVSXBQZrr:
13938 case VPMOVSXBQZrrk:
13939 case VPMOVSXBQZrrkz:
13940 case VPMOVSXBQrm:
13941 case VPMOVSXBQrr:
13942 return true;
13943 }
13944 return false;
13945}
13946
13947bool isFICOMP(unsigned Opcode) {
13948 switch (Opcode) {
13949 case FICOMP16m:
13950 case FICOMP32m:
13951 return true;
13952 }
13953 return false;
13954}
13955
13956bool isVFNMSUB132SS(unsigned Opcode) {
13957 switch (Opcode) {
13958 case VFNMSUB132SSZm_Int:
13959 case VFNMSUB132SSZmk_Int:
13960 case VFNMSUB132SSZmkz_Int:
13961 case VFNMSUB132SSZr_Int:
13962 case VFNMSUB132SSZrb_Int:
13963 case VFNMSUB132SSZrbk_Int:
13964 case VFNMSUB132SSZrbkz_Int:
13965 case VFNMSUB132SSZrk_Int:
13966 case VFNMSUB132SSZrkz_Int:
13967 case VFNMSUB132SSm_Int:
13968 case VFNMSUB132SSr_Int:
13969 return true;
13970 }
13971 return false;
13972}
13973
13974bool isVLDMXCSR(unsigned Opcode) {
13975 return Opcode == VLDMXCSR;
13976}
13977
13978bool isVPSUBUSW(unsigned Opcode) {
13979 switch (Opcode) {
13980 case VPSUBUSWYrm:
13981 case VPSUBUSWYrr:
13982 case VPSUBUSWZ128rm:
13983 case VPSUBUSWZ128rmk:
13984 case VPSUBUSWZ128rmkz:
13985 case VPSUBUSWZ128rr:
13986 case VPSUBUSWZ128rrk:
13987 case VPSUBUSWZ128rrkz:
13988 case VPSUBUSWZ256rm:
13989 case VPSUBUSWZ256rmk:
13990 case VPSUBUSWZ256rmkz:
13991 case VPSUBUSWZ256rr:
13992 case VPSUBUSWZ256rrk:
13993 case VPSUBUSWZ256rrkz:
13994 case VPSUBUSWZrm:
13995 case VPSUBUSWZrmk:
13996 case VPSUBUSWZrmkz:
13997 case VPSUBUSWZrr:
13998 case VPSUBUSWZrrk:
13999 case VPSUBUSWZrrkz:
14000 case VPSUBUSWrm:
14001 case VPSUBUSWrr:
14002 return true;
14003 }
14004 return false;
14005}
14006
14007bool isRETF(unsigned Opcode) {
14008 switch (Opcode) {
14009 case LRET16:
14010 case LRET32:
14011 case LRETI16:
14012 case LRETI32:
14013 return true;
14014 }
14015 return false;
14016}
14017
14018bool isKMOVQ(unsigned Opcode) {
14019 switch (Opcode) {
14020 case KMOVQkk:
14021 case KMOVQkk_EVEX:
14022 case KMOVQkm:
14023 case KMOVQkm_EVEX:
14024 case KMOVQkr:
14025 case KMOVQkr_EVEX:
14026 case KMOVQmk:
14027 case KMOVQmk_EVEX:
14028 case KMOVQrk:
14029 case KMOVQrk_EVEX:
14030 return true;
14031 }
14032 return false;
14033}
14034
14035bool isVPADDUSW(unsigned Opcode) {
14036 switch (Opcode) {
14037 case VPADDUSWYrm:
14038 case VPADDUSWYrr:
14039 case VPADDUSWZ128rm:
14040 case VPADDUSWZ128rmk:
14041 case VPADDUSWZ128rmkz:
14042 case VPADDUSWZ128rr:
14043 case VPADDUSWZ128rrk:
14044 case VPADDUSWZ128rrkz:
14045 case VPADDUSWZ256rm:
14046 case VPADDUSWZ256rmk:
14047 case VPADDUSWZ256rmkz:
14048 case VPADDUSWZ256rr:
14049 case VPADDUSWZ256rrk:
14050 case VPADDUSWZ256rrkz:
14051 case VPADDUSWZrm:
14052 case VPADDUSWZrmk:
14053 case VPADDUSWZrmkz:
14054 case VPADDUSWZrr:
14055 case VPADDUSWZrrk:
14056 case VPADDUSWZrrkz:
14057 case VPADDUSWrm:
14058 case VPADDUSWrr:
14059 return true;
14060 }
14061 return false;
14062}
14063
14064bool isPACKSSDW(unsigned Opcode) {
14065 switch (Opcode) {
14066 case MMX_PACKSSDWrm:
14067 case MMX_PACKSSDWrr:
14068 case PACKSSDWrm:
14069 case PACKSSDWrr:
14070 return true;
14071 }
14072 return false;
14073}
14074
14075bool isUMONITOR(unsigned Opcode) {
14076 switch (Opcode) {
14077 case UMONITOR16:
14078 case UMONITOR32:
14079 case UMONITOR64:
14080 return true;
14081 }
14082 return false;
14083}
14084
14085bool isENQCMDS(unsigned Opcode) {
14086 switch (Opcode) {
14087 case ENQCMDS16:
14088 case ENQCMDS32:
14089 case ENQCMDS32_EVEX:
14090 case ENQCMDS64:
14091 case ENQCMDS64_EVEX:
14092 return true;
14093 }
14094 return false;
14095}
14096
14097bool isVCOMXSD(unsigned Opcode) {
14098 switch (Opcode) {
14099 case VCOMXSDZrm_Int:
14100 case VCOMXSDZrr_Int:
14101 case VCOMXSDZrrb_Int:
14102 return true;
14103 }
14104 return false;
14105}
14106
14107bool isVPMAXSQ(unsigned Opcode) {
14108 switch (Opcode) {
14109 case VPMAXSQZ128rm:
14110 case VPMAXSQZ128rmb:
14111 case VPMAXSQZ128rmbk:
14112 case VPMAXSQZ128rmbkz:
14113 case VPMAXSQZ128rmk:
14114 case VPMAXSQZ128rmkz:
14115 case VPMAXSQZ128rr:
14116 case VPMAXSQZ128rrk:
14117 case VPMAXSQZ128rrkz:
14118 case VPMAXSQZ256rm:
14119 case VPMAXSQZ256rmb:
14120 case VPMAXSQZ256rmbk:
14121 case VPMAXSQZ256rmbkz:
14122 case VPMAXSQZ256rmk:
14123 case VPMAXSQZ256rmkz:
14124 case VPMAXSQZ256rr:
14125 case VPMAXSQZ256rrk:
14126 case VPMAXSQZ256rrkz:
14127 case VPMAXSQZrm:
14128 case VPMAXSQZrmb:
14129 case VPMAXSQZrmbk:
14130 case VPMAXSQZrmbkz:
14131 case VPMAXSQZrmk:
14132 case VPMAXSQZrmkz:
14133 case VPMAXSQZrr:
14134 case VPMAXSQZrrk:
14135 case VPMAXSQZrrkz:
14136 return true;
14137 }
14138 return false;
14139}
14140
14141bool isVFMSUB213BF16(unsigned Opcode) {
14142 switch (Opcode) {
14143 case VFMSUB213BF16Z128m:
14144 case VFMSUB213BF16Z128mb:
14145 case VFMSUB213BF16Z128mbk:
14146 case VFMSUB213BF16Z128mbkz:
14147 case VFMSUB213BF16Z128mk:
14148 case VFMSUB213BF16Z128mkz:
14149 case VFMSUB213BF16Z128r:
14150 case VFMSUB213BF16Z128rk:
14151 case VFMSUB213BF16Z128rkz:
14152 case VFMSUB213BF16Z256m:
14153 case VFMSUB213BF16Z256mb:
14154 case VFMSUB213BF16Z256mbk:
14155 case VFMSUB213BF16Z256mbkz:
14156 case VFMSUB213BF16Z256mk:
14157 case VFMSUB213BF16Z256mkz:
14158 case VFMSUB213BF16Z256r:
14159 case VFMSUB213BF16Z256rk:
14160 case VFMSUB213BF16Z256rkz:
14161 case VFMSUB213BF16Zm:
14162 case VFMSUB213BF16Zmb:
14163 case VFMSUB213BF16Zmbk:
14164 case VFMSUB213BF16Zmbkz:
14165 case VFMSUB213BF16Zmk:
14166 case VFMSUB213BF16Zmkz:
14167 case VFMSUB213BF16Zr:
14168 case VFMSUB213BF16Zrk:
14169 case VFMSUB213BF16Zrkz:
14170 return true;
14171 }
14172 return false;
14173}
14174
14175bool isVPERMT2Q(unsigned Opcode) {
14176 switch (Opcode) {
14177 case VPERMT2QZ128rm:
14178 case VPERMT2QZ128rmb:
14179 case VPERMT2QZ128rmbk:
14180 case VPERMT2QZ128rmbkz:
14181 case VPERMT2QZ128rmk:
14182 case VPERMT2QZ128rmkz:
14183 case VPERMT2QZ128rr:
14184 case VPERMT2QZ128rrk:
14185 case VPERMT2QZ128rrkz:
14186 case VPERMT2QZ256rm:
14187 case VPERMT2QZ256rmb:
14188 case VPERMT2QZ256rmbk:
14189 case VPERMT2QZ256rmbkz:
14190 case VPERMT2QZ256rmk:
14191 case VPERMT2QZ256rmkz:
14192 case VPERMT2QZ256rr:
14193 case VPERMT2QZ256rrk:
14194 case VPERMT2QZ256rrkz:
14195 case VPERMT2QZrm:
14196 case VPERMT2QZrmb:
14197 case VPERMT2QZrmbk:
14198 case VPERMT2QZrmbkz:
14199 case VPERMT2QZrmk:
14200 case VPERMT2QZrmkz:
14201 case VPERMT2QZrr:
14202 case VPERMT2QZrrk:
14203 case VPERMT2QZrrkz:
14204 return true;
14205 }
14206 return false;
14207}
14208
14209bool isFDECSTP(unsigned Opcode) {
14210 return Opcode == FDECSTP;
14211}
14212
14213bool isVPTESTMQ(unsigned Opcode) {
14214 switch (Opcode) {
14215 case VPTESTMQZ128rm:
14216 case VPTESTMQZ128rmb:
14217 case VPTESTMQZ128rmbk:
14218 case VPTESTMQZ128rmk:
14219 case VPTESTMQZ128rr:
14220 case VPTESTMQZ128rrk:
14221 case VPTESTMQZ256rm:
14222 case VPTESTMQZ256rmb:
14223 case VPTESTMQZ256rmbk:
14224 case VPTESTMQZ256rmk:
14225 case VPTESTMQZ256rr:
14226 case VPTESTMQZ256rrk:
14227 case VPTESTMQZrm:
14228 case VPTESTMQZrmb:
14229 case VPTESTMQZrmbk:
14230 case VPTESTMQZrmk:
14231 case VPTESTMQZrr:
14232 case VPTESTMQZrrk:
14233 return true;
14234 }
14235 return false;
14236}
14237
14238bool isVRCP14PD(unsigned Opcode) {
14239 switch (Opcode) {
14240 case VRCP14PDZ128m:
14241 case VRCP14PDZ128mb:
14242 case VRCP14PDZ128mbk:
14243 case VRCP14PDZ128mbkz:
14244 case VRCP14PDZ128mk:
14245 case VRCP14PDZ128mkz:
14246 case VRCP14PDZ128r:
14247 case VRCP14PDZ128rk:
14248 case VRCP14PDZ128rkz:
14249 case VRCP14PDZ256m:
14250 case VRCP14PDZ256mb:
14251 case VRCP14PDZ256mbk:
14252 case VRCP14PDZ256mbkz:
14253 case VRCP14PDZ256mk:
14254 case VRCP14PDZ256mkz:
14255 case VRCP14PDZ256r:
14256 case VRCP14PDZ256rk:
14257 case VRCP14PDZ256rkz:
14258 case VRCP14PDZm:
14259 case VRCP14PDZmb:
14260 case VRCP14PDZmbk:
14261 case VRCP14PDZmbkz:
14262 case VRCP14PDZmk:
14263 case VRCP14PDZmkz:
14264 case VRCP14PDZr:
14265 case VRCP14PDZrk:
14266 case VRCP14PDZrkz:
14267 return true;
14268 }
14269 return false;
14270}
14271
14272bool isARPL(unsigned Opcode) {
14273 switch (Opcode) {
14274 case ARPL16mr:
14275 case ARPL16rr:
14276 return true;
14277 }
14278 return false;
14279}
14280
14281bool isVFMSUB213SD(unsigned Opcode) {
14282 switch (Opcode) {
14283 case VFMSUB213SDZm_Int:
14284 case VFMSUB213SDZmk_Int:
14285 case VFMSUB213SDZmkz_Int:
14286 case VFMSUB213SDZr_Int:
14287 case VFMSUB213SDZrb_Int:
14288 case VFMSUB213SDZrbk_Int:
14289 case VFMSUB213SDZrbkz_Int:
14290 case VFMSUB213SDZrk_Int:
14291 case VFMSUB213SDZrkz_Int:
14292 case VFMSUB213SDm_Int:
14293 case VFMSUB213SDr_Int:
14294 return true;
14295 }
14296 return false;
14297}
14298
14299bool isJMPABS(unsigned Opcode) {
14300 return Opcode == JMPABS64i;
14301}
14302
14303bool isVUNPCKHPS(unsigned Opcode) {
14304 switch (Opcode) {
14305 case VUNPCKHPSYrm:
14306 case VUNPCKHPSYrr:
14307 case VUNPCKHPSZ128rm:
14308 case VUNPCKHPSZ128rmb:
14309 case VUNPCKHPSZ128rmbk:
14310 case VUNPCKHPSZ128rmbkz:
14311 case VUNPCKHPSZ128rmk:
14312 case VUNPCKHPSZ128rmkz:
14313 case VUNPCKHPSZ128rr:
14314 case VUNPCKHPSZ128rrk:
14315 case VUNPCKHPSZ128rrkz:
14316 case VUNPCKHPSZ256rm:
14317 case VUNPCKHPSZ256rmb:
14318 case VUNPCKHPSZ256rmbk:
14319 case VUNPCKHPSZ256rmbkz:
14320 case VUNPCKHPSZ256rmk:
14321 case VUNPCKHPSZ256rmkz:
14322 case VUNPCKHPSZ256rr:
14323 case VUNPCKHPSZ256rrk:
14324 case VUNPCKHPSZ256rrkz:
14325 case VUNPCKHPSZrm:
14326 case VUNPCKHPSZrmb:
14327 case VUNPCKHPSZrmbk:
14328 case VUNPCKHPSZrmbkz:
14329 case VUNPCKHPSZrmk:
14330 case VUNPCKHPSZrmkz:
14331 case VUNPCKHPSZrr:
14332 case VUNPCKHPSZrrk:
14333 case VUNPCKHPSZrrkz:
14334 case VUNPCKHPSrm:
14335 case VUNPCKHPSrr:
14336 return true;
14337 }
14338 return false;
14339}
14340
14341bool isVFNMADDSS(unsigned Opcode) {
14342 switch (Opcode) {
14343 case VFNMADDSS4mr:
14344 case VFNMADDSS4rm:
14345 case VFNMADDSS4rr:
14346 case VFNMADDSS4rr_REV:
14347 return true;
14348 }
14349 return false;
14350}
14351
14352bool isSIDT(unsigned Opcode) {
14353 return Opcode == SIDT64m;
14354}
14355
14356bool isVPCMPGTB(unsigned Opcode) {
14357 switch (Opcode) {
14358 case VPCMPGTBYrm:
14359 case VPCMPGTBYrr:
14360 case VPCMPGTBZ128rm:
14361 case VPCMPGTBZ128rmk:
14362 case VPCMPGTBZ128rr:
14363 case VPCMPGTBZ128rrk:
14364 case VPCMPGTBZ256rm:
14365 case VPCMPGTBZ256rmk:
14366 case VPCMPGTBZ256rr:
14367 case VPCMPGTBZ256rrk:
14368 case VPCMPGTBZrm:
14369 case VPCMPGTBZrmk:
14370 case VPCMPGTBZrr:
14371 case VPCMPGTBZrrk:
14372 case VPCMPGTBrm:
14373 case VPCMPGTBrr:
14374 return true;
14375 }
14376 return false;
14377}
14378
14379bool isVPRORD(unsigned Opcode) {
14380 switch (Opcode) {
14381 case VPRORDZ128mbi:
14382 case VPRORDZ128mbik:
14383 case VPRORDZ128mbikz:
14384 case VPRORDZ128mi:
14385 case VPRORDZ128mik:
14386 case VPRORDZ128mikz:
14387 case VPRORDZ128ri:
14388 case VPRORDZ128rik:
14389 case VPRORDZ128rikz:
14390 case VPRORDZ256mbi:
14391 case VPRORDZ256mbik:
14392 case VPRORDZ256mbikz:
14393 case VPRORDZ256mi:
14394 case VPRORDZ256mik:
14395 case VPRORDZ256mikz:
14396 case VPRORDZ256ri:
14397 case VPRORDZ256rik:
14398 case VPRORDZ256rikz:
14399 case VPRORDZmbi:
14400 case VPRORDZmbik:
14401 case VPRORDZmbikz:
14402 case VPRORDZmi:
14403 case VPRORDZmik:
14404 case VPRORDZmikz:
14405 case VPRORDZri:
14406 case VPRORDZrik:
14407 case VPRORDZrikz:
14408 return true;
14409 }
14410 return false;
14411}
14412
14413bool isVSUBSS(unsigned Opcode) {
14414 switch (Opcode) {
14415 case VSUBSSZrm_Int:
14416 case VSUBSSZrmk_Int:
14417 case VSUBSSZrmkz_Int:
14418 case VSUBSSZrr_Int:
14419 case VSUBSSZrrb_Int:
14420 case VSUBSSZrrbk_Int:
14421 case VSUBSSZrrbkz_Int:
14422 case VSUBSSZrrk_Int:
14423 case VSUBSSZrrkz_Int:
14424 case VSUBSSrm_Int:
14425 case VSUBSSrr_Int:
14426 return true;
14427 }
14428 return false;
14429}
14430
14431bool isPUSHFQ(unsigned Opcode) {
14432 return Opcode == PUSHF64;
14433}
14434
14435bool isVCVTHF82PH(unsigned Opcode) {
14436 switch (Opcode) {
14437 case VCVTHF82PHZ128rm:
14438 case VCVTHF82PHZ128rmk:
14439 case VCVTHF82PHZ128rmkz:
14440 case VCVTHF82PHZ128rr:
14441 case VCVTHF82PHZ128rrk:
14442 case VCVTHF82PHZ128rrkz:
14443 case VCVTHF82PHZ256rm:
14444 case VCVTHF82PHZ256rmk:
14445 case VCVTHF82PHZ256rmkz:
14446 case VCVTHF82PHZ256rr:
14447 case VCVTHF82PHZ256rrk:
14448 case VCVTHF82PHZ256rrkz:
14449 case VCVTHF82PHZrm:
14450 case VCVTHF82PHZrmk:
14451 case VCVTHF82PHZrmkz:
14452 case VCVTHF82PHZrr:
14453 case VCVTHF82PHZrrk:
14454 case VCVTHF82PHZrrkz:
14455 return true;
14456 }
14457 return false;
14458}
14459
14460bool isVPCLMULQDQ(unsigned Opcode) {
14461 switch (Opcode) {
14462 case VPCLMULQDQYrmi:
14463 case VPCLMULQDQYrri:
14464 case VPCLMULQDQZ128rmi:
14465 case VPCLMULQDQZ128rri:
14466 case VPCLMULQDQZ256rmi:
14467 case VPCLMULQDQZ256rri:
14468 case VPCLMULQDQZrmi:
14469 case VPCLMULQDQZrri:
14470 case VPCLMULQDQrmi:
14471 case VPCLMULQDQrri:
14472 return true;
14473 }
14474 return false;
14475}
14476
14477bool isVPADDUSB(unsigned Opcode) {
14478 switch (Opcode) {
14479 case VPADDUSBYrm:
14480 case VPADDUSBYrr:
14481 case VPADDUSBZ128rm:
14482 case VPADDUSBZ128rmk:
14483 case VPADDUSBZ128rmkz:
14484 case VPADDUSBZ128rr:
14485 case VPADDUSBZ128rrk:
14486 case VPADDUSBZ128rrkz:
14487 case VPADDUSBZ256rm:
14488 case VPADDUSBZ256rmk:
14489 case VPADDUSBZ256rmkz:
14490 case VPADDUSBZ256rr:
14491 case VPADDUSBZ256rrk:
14492 case VPADDUSBZ256rrkz:
14493 case VPADDUSBZrm:
14494 case VPADDUSBZrmk:
14495 case VPADDUSBZrmkz:
14496 case VPADDUSBZrr:
14497 case VPADDUSBZrrk:
14498 case VPADDUSBZrrkz:
14499 case VPADDUSBrm:
14500 case VPADDUSBrr:
14501 return true;
14502 }
14503 return false;
14504}
14505
14506bool isVPCMPD(unsigned Opcode) {
14507 switch (Opcode) {
14508 case VPCMPDZ128rmbi:
14509 case VPCMPDZ128rmbik:
14510 case VPCMPDZ128rmi:
14511 case VPCMPDZ128rmik:
14512 case VPCMPDZ128rri:
14513 case VPCMPDZ128rrik:
14514 case VPCMPDZ256rmbi:
14515 case VPCMPDZ256rmbik:
14516 case VPCMPDZ256rmi:
14517 case VPCMPDZ256rmik:
14518 case VPCMPDZ256rri:
14519 case VPCMPDZ256rrik:
14520 case VPCMPDZrmbi:
14521 case VPCMPDZrmbik:
14522 case VPCMPDZrmi:
14523 case VPCMPDZrmik:
14524 case VPCMPDZrri:
14525 case VPCMPDZrrik:
14526 return true;
14527 }
14528 return false;
14529}
14530
14531bool isMOVSD(unsigned Opcode) {
14532 switch (Opcode) {
14533 case MOVSDmr:
14534 case MOVSDrm:
14535 case MOVSDrr:
14536 case MOVSDrr_REV:
14537 case MOVSL:
14538 return true;
14539 }
14540 return false;
14541}
14542
14543bool isPSUBUSW(unsigned Opcode) {
14544 switch (Opcode) {
14545 case MMX_PSUBUSWrm:
14546 case MMX_PSUBUSWrr:
14547 case PSUBUSWrm:
14548 case PSUBUSWrr:
14549 return true;
14550 }
14551 return false;
14552}
14553
14554bool isVFMSUBADD132PS(unsigned Opcode) {
14555 switch (Opcode) {
14556 case VFMSUBADD132PSYm:
14557 case VFMSUBADD132PSYr:
14558 case VFMSUBADD132PSZ128m:
14559 case VFMSUBADD132PSZ128mb:
14560 case VFMSUBADD132PSZ128mbk:
14561 case VFMSUBADD132PSZ128mbkz:
14562 case VFMSUBADD132PSZ128mk:
14563 case VFMSUBADD132PSZ128mkz:
14564 case VFMSUBADD132PSZ128r:
14565 case VFMSUBADD132PSZ128rk:
14566 case VFMSUBADD132PSZ128rkz:
14567 case VFMSUBADD132PSZ256m:
14568 case VFMSUBADD132PSZ256mb:
14569 case VFMSUBADD132PSZ256mbk:
14570 case VFMSUBADD132PSZ256mbkz:
14571 case VFMSUBADD132PSZ256mk:
14572 case VFMSUBADD132PSZ256mkz:
14573 case VFMSUBADD132PSZ256r:
14574 case VFMSUBADD132PSZ256rk:
14575 case VFMSUBADD132PSZ256rkz:
14576 case VFMSUBADD132PSZm:
14577 case VFMSUBADD132PSZmb:
14578 case VFMSUBADD132PSZmbk:
14579 case VFMSUBADD132PSZmbkz:
14580 case VFMSUBADD132PSZmk:
14581 case VFMSUBADD132PSZmkz:
14582 case VFMSUBADD132PSZr:
14583 case VFMSUBADD132PSZrb:
14584 case VFMSUBADD132PSZrbk:
14585 case VFMSUBADD132PSZrbkz:
14586 case VFMSUBADD132PSZrk:
14587 case VFMSUBADD132PSZrkz:
14588 case VFMSUBADD132PSm:
14589 case VFMSUBADD132PSr:
14590 return true;
14591 }
14592 return false;
14593}
14594
14595bool isMOVMSKPS(unsigned Opcode) {
14596 return Opcode == MOVMSKPSrr;
14597}
14598
14599bool isVFIXUPIMMSS(unsigned Opcode) {
14600 switch (Opcode) {
14601 case VFIXUPIMMSSZrmi:
14602 case VFIXUPIMMSSZrmik:
14603 case VFIXUPIMMSSZrmikz:
14604 case VFIXUPIMMSSZrri:
14605 case VFIXUPIMMSSZrrib:
14606 case VFIXUPIMMSSZrribk:
14607 case VFIXUPIMMSSZrribkz:
14608 case VFIXUPIMMSSZrrik:
14609 case VFIXUPIMMSSZrrikz:
14610 return true;
14611 }
14612 return false;
14613}
14614
14615bool isMFENCE(unsigned Opcode) {
14616 return Opcode == MFENCE;
14617}
14618
14619bool isFTST(unsigned Opcode) {
14620 return Opcode == TST_F;
14621}
14622
14623bool isVPMADDWD(unsigned Opcode) {
14624 switch (Opcode) {
14625 case VPMADDWDYrm:
14626 case VPMADDWDYrr:
14627 case VPMADDWDZ128rm:
14628 case VPMADDWDZ128rmk:
14629 case VPMADDWDZ128rmkz:
14630 case VPMADDWDZ128rr:
14631 case VPMADDWDZ128rrk:
14632 case VPMADDWDZ128rrkz:
14633 case VPMADDWDZ256rm:
14634 case VPMADDWDZ256rmk:
14635 case VPMADDWDZ256rmkz:
14636 case VPMADDWDZ256rr:
14637 case VPMADDWDZ256rrk:
14638 case VPMADDWDZ256rrkz:
14639 case VPMADDWDZrm:
14640 case VPMADDWDZrmk:
14641 case VPMADDWDZrmkz:
14642 case VPMADDWDZrr:
14643 case VPMADDWDZrrk:
14644 case VPMADDWDZrrkz:
14645 case VPMADDWDrm:
14646 case VPMADDWDrr:
14647 return true;
14648 }
14649 return false;
14650}
14651
14652bool isPOP(unsigned Opcode) {
14653 switch (Opcode) {
14654 case POP16r:
14655 case POP16rmm:
14656 case POP16rmr:
14657 case POP32r:
14658 case POP32rmm:
14659 case POP32rmr:
14660 case POP64r:
14661 case POP64rmm:
14662 case POP64rmr:
14663 case POPDS16:
14664 case POPDS32:
14665 case POPES16:
14666 case POPES32:
14667 case POPFS16:
14668 case POPFS32:
14669 case POPFS64:
14670 case POPGS16:
14671 case POPGS32:
14672 case POPGS64:
14673 case POPSS16:
14674 case POPSS32:
14675 return true;
14676 }
14677 return false;
14678}
14679
14680bool isPSUBW(unsigned Opcode) {
14681 switch (Opcode) {
14682 case MMX_PSUBWrm:
14683 case MMX_PSUBWrr:
14684 case PSUBWrm:
14685 case PSUBWrr:
14686 return true;
14687 }
14688 return false;
14689}
14690
14691bool isBSWAP(unsigned Opcode) {
14692 switch (Opcode) {
14693 case BSWAP16r_BAD:
14694 case BSWAP32r:
14695 case BSWAP64r:
14696 return true;
14697 }
14698 return false;
14699}
14700
14701bool isPFMIN(unsigned Opcode) {
14702 switch (Opcode) {
14703 case PFMINrm:
14704 case PFMINrr:
14705 return true;
14706 }
14707 return false;
14708}
14709
14710bool isVFPCLASSPD(unsigned Opcode) {
14711 switch (Opcode) {
14712 case VFPCLASSPDZ128mbi:
14713 case VFPCLASSPDZ128mbik:
14714 case VFPCLASSPDZ128mi:
14715 case VFPCLASSPDZ128mik:
14716 case VFPCLASSPDZ128ri:
14717 case VFPCLASSPDZ128rik:
14718 case VFPCLASSPDZ256mbi:
14719 case VFPCLASSPDZ256mbik:
14720 case VFPCLASSPDZ256mi:
14721 case VFPCLASSPDZ256mik:
14722 case VFPCLASSPDZ256ri:
14723 case VFPCLASSPDZ256rik:
14724 case VFPCLASSPDZmbi:
14725 case VFPCLASSPDZmbik:
14726 case VFPCLASSPDZmi:
14727 case VFPCLASSPDZmik:
14728 case VFPCLASSPDZri:
14729 case VFPCLASSPDZrik:
14730 return true;
14731 }
14732 return false;
14733}
14734
14735bool isVPSHRDVD(unsigned Opcode) {
14736 switch (Opcode) {
14737 case VPSHRDVDZ128m:
14738 case VPSHRDVDZ128mb:
14739 case VPSHRDVDZ128mbk:
14740 case VPSHRDVDZ128mbkz:
14741 case VPSHRDVDZ128mk:
14742 case VPSHRDVDZ128mkz:
14743 case VPSHRDVDZ128r:
14744 case VPSHRDVDZ128rk:
14745 case VPSHRDVDZ128rkz:
14746 case VPSHRDVDZ256m:
14747 case VPSHRDVDZ256mb:
14748 case VPSHRDVDZ256mbk:
14749 case VPSHRDVDZ256mbkz:
14750 case VPSHRDVDZ256mk:
14751 case VPSHRDVDZ256mkz:
14752 case VPSHRDVDZ256r:
14753 case VPSHRDVDZ256rk:
14754 case VPSHRDVDZ256rkz:
14755 case VPSHRDVDZm:
14756 case VPSHRDVDZmb:
14757 case VPSHRDVDZmbk:
14758 case VPSHRDVDZmbkz:
14759 case VPSHRDVDZmk:
14760 case VPSHRDVDZmkz:
14761 case VPSHRDVDZr:
14762 case VPSHRDVDZrk:
14763 case VPSHRDVDZrkz:
14764 return true;
14765 }
14766 return false;
14767}
14768
14769bool isPADDW(unsigned Opcode) {
14770 switch (Opcode) {
14771 case MMX_PADDWrm:
14772 case MMX_PADDWrr:
14773 case PADDWrm:
14774 case PADDWrr:
14775 return true;
14776 }
14777 return false;
14778}
14779
14780bool isCVTSI2SD(unsigned Opcode) {
14781 switch (Opcode) {
14782 case CVTSI2SDrm_Int:
14783 case CVTSI2SDrr_Int:
14784 case CVTSI642SDrm_Int:
14785 case CVTSI642SDrr_Int:
14786 return true;
14787 }
14788 return false;
14789}
14790
14791bool isENQCMD(unsigned Opcode) {
14792 switch (Opcode) {
14793 case ENQCMD16:
14794 case ENQCMD32:
14795 case ENQCMD32_EVEX:
14796 case ENQCMD64:
14797 case ENQCMD64_EVEX:
14798 return true;
14799 }
14800 return false;
14801}
14802
14803bool isXSHA1(unsigned Opcode) {
14804 return Opcode == XSHA1;
14805}
14806
14807bool isVFNMADD132SD(unsigned Opcode) {
14808 switch (Opcode) {
14809 case VFNMADD132SDZm_Int:
14810 case VFNMADD132SDZmk_Int:
14811 case VFNMADD132SDZmkz_Int:
14812 case VFNMADD132SDZr_Int:
14813 case VFNMADD132SDZrb_Int:
14814 case VFNMADD132SDZrbk_Int:
14815 case VFNMADD132SDZrbkz_Int:
14816 case VFNMADD132SDZrk_Int:
14817 case VFNMADD132SDZrkz_Int:
14818 case VFNMADD132SDm_Int:
14819 case VFNMADD132SDr_Int:
14820 return true;
14821 }
14822 return false;
14823}
14824
14825bool isMOVZX(unsigned Opcode) {
14826 switch (Opcode) {
14827 case MOVZX16rm16:
14828 case MOVZX16rm8:
14829 case MOVZX16rr16:
14830 case MOVZX16rr8:
14831 case MOVZX32rm16:
14832 case MOVZX32rm8:
14833 case MOVZX32rr16:
14834 case MOVZX32rr8:
14835 case MOVZX64rm16:
14836 case MOVZX64rm8:
14837 case MOVZX64rr16:
14838 case MOVZX64rr8:
14839 return true;
14840 }
14841 return false;
14842}
14843
14844bool isVFIXUPIMMSD(unsigned Opcode) {
14845 switch (Opcode) {
14846 case VFIXUPIMMSDZrmi:
14847 case VFIXUPIMMSDZrmik:
14848 case VFIXUPIMMSDZrmikz:
14849 case VFIXUPIMMSDZrri:
14850 case VFIXUPIMMSDZrrib:
14851 case VFIXUPIMMSDZrribk:
14852 case VFIXUPIMMSDZrribkz:
14853 case VFIXUPIMMSDZrrik:
14854 case VFIXUPIMMSDZrrikz:
14855 return true;
14856 }
14857 return false;
14858}
14859
14860bool isINVD(unsigned Opcode) {
14861 return Opcode == INVD;
14862}
14863
14864bool isVFIXUPIMMPS(unsigned Opcode) {
14865 switch (Opcode) {
14866 case VFIXUPIMMPSZ128rmbi:
14867 case VFIXUPIMMPSZ128rmbik:
14868 case VFIXUPIMMPSZ128rmbikz:
14869 case VFIXUPIMMPSZ128rmi:
14870 case VFIXUPIMMPSZ128rmik:
14871 case VFIXUPIMMPSZ128rmikz:
14872 case VFIXUPIMMPSZ128rri:
14873 case VFIXUPIMMPSZ128rrik:
14874 case VFIXUPIMMPSZ128rrikz:
14875 case VFIXUPIMMPSZ256rmbi:
14876 case VFIXUPIMMPSZ256rmbik:
14877 case VFIXUPIMMPSZ256rmbikz:
14878 case VFIXUPIMMPSZ256rmi:
14879 case VFIXUPIMMPSZ256rmik:
14880 case VFIXUPIMMPSZ256rmikz:
14881 case VFIXUPIMMPSZ256rri:
14882 case VFIXUPIMMPSZ256rrik:
14883 case VFIXUPIMMPSZ256rrikz:
14884 case VFIXUPIMMPSZrmbi:
14885 case VFIXUPIMMPSZrmbik:
14886 case VFIXUPIMMPSZrmbikz:
14887 case VFIXUPIMMPSZrmi:
14888 case VFIXUPIMMPSZrmik:
14889 case VFIXUPIMMPSZrmikz:
14890 case VFIXUPIMMPSZrri:
14891 case VFIXUPIMMPSZrrib:
14892 case VFIXUPIMMPSZrribk:
14893 case VFIXUPIMMPSZrribkz:
14894 case VFIXUPIMMPSZrrik:
14895 case VFIXUPIMMPSZrrikz:
14896 return true;
14897 }
14898 return false;
14899}
14900
14901bool isMOVDQU(unsigned Opcode) {
14902 switch (Opcode) {
14903 case MOVDQUmr:
14904 case MOVDQUrm:
14905 case MOVDQUrr:
14906 case MOVDQUrr_REV:
14907 return true;
14908 }
14909 return false;
14910}
14911
14912bool isVFPCLASSPS(unsigned Opcode) {
14913 switch (Opcode) {
14914 case VFPCLASSPSZ128mbi:
14915 case VFPCLASSPSZ128mbik:
14916 case VFPCLASSPSZ128mi:
14917 case VFPCLASSPSZ128mik:
14918 case VFPCLASSPSZ128ri:
14919 case VFPCLASSPSZ128rik:
14920 case VFPCLASSPSZ256mbi:
14921 case VFPCLASSPSZ256mbik:
14922 case VFPCLASSPSZ256mi:
14923 case VFPCLASSPSZ256mik:
14924 case VFPCLASSPSZ256ri:
14925 case VFPCLASSPSZ256rik:
14926 case VFPCLASSPSZmbi:
14927 case VFPCLASSPSZmbik:
14928 case VFPCLASSPSZmi:
14929 case VFPCLASSPSZmik:
14930 case VFPCLASSPSZri:
14931 case VFPCLASSPSZrik:
14932 return true;
14933 }
14934 return false;
14935}
14936
14937bool isVPERMILPS(unsigned Opcode) {
14938 switch (Opcode) {
14939 case VPERMILPSYmi:
14940 case VPERMILPSYri:
14941 case VPERMILPSYrm:
14942 case VPERMILPSYrr:
14943 case VPERMILPSZ128mbi:
14944 case VPERMILPSZ128mbik:
14945 case VPERMILPSZ128mbikz:
14946 case VPERMILPSZ128mi:
14947 case VPERMILPSZ128mik:
14948 case VPERMILPSZ128mikz:
14949 case VPERMILPSZ128ri:
14950 case VPERMILPSZ128rik:
14951 case VPERMILPSZ128rikz:
14952 case VPERMILPSZ128rm:
14953 case VPERMILPSZ128rmb:
14954 case VPERMILPSZ128rmbk:
14955 case VPERMILPSZ128rmbkz:
14956 case VPERMILPSZ128rmk:
14957 case VPERMILPSZ128rmkz:
14958 case VPERMILPSZ128rr:
14959 case VPERMILPSZ128rrk:
14960 case VPERMILPSZ128rrkz:
14961 case VPERMILPSZ256mbi:
14962 case VPERMILPSZ256mbik:
14963 case VPERMILPSZ256mbikz:
14964 case VPERMILPSZ256mi:
14965 case VPERMILPSZ256mik:
14966 case VPERMILPSZ256mikz:
14967 case VPERMILPSZ256ri:
14968 case VPERMILPSZ256rik:
14969 case VPERMILPSZ256rikz:
14970 case VPERMILPSZ256rm:
14971 case VPERMILPSZ256rmb:
14972 case VPERMILPSZ256rmbk:
14973 case VPERMILPSZ256rmbkz:
14974 case VPERMILPSZ256rmk:
14975 case VPERMILPSZ256rmkz:
14976 case VPERMILPSZ256rr:
14977 case VPERMILPSZ256rrk:
14978 case VPERMILPSZ256rrkz:
14979 case VPERMILPSZmbi:
14980 case VPERMILPSZmbik:
14981 case VPERMILPSZmbikz:
14982 case VPERMILPSZmi:
14983 case VPERMILPSZmik:
14984 case VPERMILPSZmikz:
14985 case VPERMILPSZri:
14986 case VPERMILPSZrik:
14987 case VPERMILPSZrikz:
14988 case VPERMILPSZrm:
14989 case VPERMILPSZrmb:
14990 case VPERMILPSZrmbk:
14991 case VPERMILPSZrmbkz:
14992 case VPERMILPSZrmk:
14993 case VPERMILPSZrmkz:
14994 case VPERMILPSZrr:
14995 case VPERMILPSZrrk:
14996 case VPERMILPSZrrkz:
14997 case VPERMILPSmi:
14998 case VPERMILPSri:
14999 case VPERMILPSrm:
15000 case VPERMILPSrr:
15001 return true;
15002 }
15003 return false;
15004}
15005
15006bool isMOVSQ(unsigned Opcode) {
15007 return Opcode == MOVSQ;
15008}
15009
15010bool isAESDECWIDE128KL(unsigned Opcode) {
15011 return Opcode == AESDECWIDE128KL;
15012}
15013
15014bool isROUNDSS(unsigned Opcode) {
15015 switch (Opcode) {
15016 case ROUNDSSmi_Int:
15017 case ROUNDSSri_Int:
15018 return true;
15019 }
15020 return false;
15021}
15022
15023bool isVPMOVW2M(unsigned Opcode) {
15024 switch (Opcode) {
15025 case VPMOVW2MZ128kr:
15026 case VPMOVW2MZ256kr:
15027 case VPMOVW2MZkr:
15028 return true;
15029 }
15030 return false;
15031}
15032
15033bool isVPSHUFB(unsigned Opcode) {
15034 switch (Opcode) {
15035 case VPSHUFBYrm:
15036 case VPSHUFBYrr:
15037 case VPSHUFBZ128rm:
15038 case VPSHUFBZ128rmk:
15039 case VPSHUFBZ128rmkz:
15040 case VPSHUFBZ128rr:
15041 case VPSHUFBZ128rrk:
15042 case VPSHUFBZ128rrkz:
15043 case VPSHUFBZ256rm:
15044 case VPSHUFBZ256rmk:
15045 case VPSHUFBZ256rmkz:
15046 case VPSHUFBZ256rr:
15047 case VPSHUFBZ256rrk:
15048 case VPSHUFBZ256rrkz:
15049 case VPSHUFBZrm:
15050 case VPSHUFBZrmk:
15051 case VPSHUFBZrmkz:
15052 case VPSHUFBZrr:
15053 case VPSHUFBZrrk:
15054 case VPSHUFBZrrkz:
15055 case VPSHUFBrm:
15056 case VPSHUFBrr:
15057 return true;
15058 }
15059 return false;
15060}
15061
15062bool isVMULSD(unsigned Opcode) {
15063 switch (Opcode) {
15064 case VMULSDZrm_Int:
15065 case VMULSDZrmk_Int:
15066 case VMULSDZrmkz_Int:
15067 case VMULSDZrr_Int:
15068 case VMULSDZrrb_Int:
15069 case VMULSDZrrbk_Int:
15070 case VMULSDZrrbkz_Int:
15071 case VMULSDZrrk_Int:
15072 case VMULSDZrrkz_Int:
15073 case VMULSDrm_Int:
15074 case VMULSDrr_Int:
15075 return true;
15076 }
15077 return false;
15078}
15079
15080bool isVPERMI2W(unsigned Opcode) {
15081 switch (Opcode) {
15082 case VPERMI2WZ128rm:
15083 case VPERMI2WZ128rmk:
15084 case VPERMI2WZ128rmkz:
15085 case VPERMI2WZ128rr:
15086 case VPERMI2WZ128rrk:
15087 case VPERMI2WZ128rrkz:
15088 case VPERMI2WZ256rm:
15089 case VPERMI2WZ256rmk:
15090 case VPERMI2WZ256rmkz:
15091 case VPERMI2WZ256rr:
15092 case VPERMI2WZ256rrk:
15093 case VPERMI2WZ256rrkz:
15094 case VPERMI2WZrm:
15095 case VPERMI2WZrmk:
15096 case VPERMI2WZrmkz:
15097 case VPERMI2WZrr:
15098 case VPERMI2WZrrk:
15099 case VPERMI2WZrrkz:
15100 return true;
15101 }
15102 return false;
15103}
15104
15105bool isVREDUCESS(unsigned Opcode) {
15106 switch (Opcode) {
15107 case VREDUCESSZrmi:
15108 case VREDUCESSZrmik:
15109 case VREDUCESSZrmikz:
15110 case VREDUCESSZrri:
15111 case VREDUCESSZrrib:
15112 case VREDUCESSZrribk:
15113 case VREDUCESSZrribkz:
15114 case VREDUCESSZrrik:
15115 case VREDUCESSZrrikz:
15116 return true;
15117 }
15118 return false;
15119}
15120
15121bool isFST(unsigned Opcode) {
15122 switch (Opcode) {
15123 case ST_F32m:
15124 case ST_F64m:
15125 case ST_Frr:
15126 return true;
15127 }
15128 return false;
15129}
15130
15131bool isVPHSUBW(unsigned Opcode) {
15132 switch (Opcode) {
15133 case VPHSUBWYrm:
15134 case VPHSUBWYrr:
15135 case VPHSUBWrm:
15136 case VPHSUBWrr:
15137 return true;
15138 }
15139 return false;
15140}
15141
15142bool isFRNDINT(unsigned Opcode) {
15143 return Opcode == FRNDINT;
15144}
15145
15146bool isSHR(unsigned Opcode) {
15147 switch (Opcode) {
15148 case SHR16m1:
15149 case SHR16m1_EVEX:
15150 case SHR16m1_ND:
15151 case SHR16m1_NF:
15152 case SHR16m1_NF_ND:
15153 case SHR16mCL:
15154 case SHR16mCL_EVEX:
15155 case SHR16mCL_ND:
15156 case SHR16mCL_NF:
15157 case SHR16mCL_NF_ND:
15158 case SHR16mi:
15159 case SHR16mi_EVEX:
15160 case SHR16mi_ND:
15161 case SHR16mi_NF:
15162 case SHR16mi_NF_ND:
15163 case SHR16r1:
15164 case SHR16r1_EVEX:
15165 case SHR16r1_ND:
15166 case SHR16r1_NF:
15167 case SHR16r1_NF_ND:
15168 case SHR16rCL:
15169 case SHR16rCL_EVEX:
15170 case SHR16rCL_ND:
15171 case SHR16rCL_NF:
15172 case SHR16rCL_NF_ND:
15173 case SHR16ri:
15174 case SHR16ri_EVEX:
15175 case SHR16ri_ND:
15176 case SHR16ri_NF:
15177 case SHR16ri_NF_ND:
15178 case SHR32m1:
15179 case SHR32m1_EVEX:
15180 case SHR32m1_ND:
15181 case SHR32m1_NF:
15182 case SHR32m1_NF_ND:
15183 case SHR32mCL:
15184 case SHR32mCL_EVEX:
15185 case SHR32mCL_ND:
15186 case SHR32mCL_NF:
15187 case SHR32mCL_NF_ND:
15188 case SHR32mi:
15189 case SHR32mi_EVEX:
15190 case SHR32mi_ND:
15191 case SHR32mi_NF:
15192 case SHR32mi_NF_ND:
15193 case SHR32r1:
15194 case SHR32r1_EVEX:
15195 case SHR32r1_ND:
15196 case SHR32r1_NF:
15197 case SHR32r1_NF_ND:
15198 case SHR32rCL:
15199 case SHR32rCL_EVEX:
15200 case SHR32rCL_ND:
15201 case SHR32rCL_NF:
15202 case SHR32rCL_NF_ND:
15203 case SHR32ri:
15204 case SHR32ri_EVEX:
15205 case SHR32ri_ND:
15206 case SHR32ri_NF:
15207 case SHR32ri_NF_ND:
15208 case SHR64m1:
15209 case SHR64m1_EVEX:
15210 case SHR64m1_ND:
15211 case SHR64m1_NF:
15212 case SHR64m1_NF_ND:
15213 case SHR64mCL:
15214 case SHR64mCL_EVEX:
15215 case SHR64mCL_ND:
15216 case SHR64mCL_NF:
15217 case SHR64mCL_NF_ND:
15218 case SHR64mi:
15219 case SHR64mi_EVEX:
15220 case SHR64mi_ND:
15221 case SHR64mi_NF:
15222 case SHR64mi_NF_ND:
15223 case SHR64r1:
15224 case SHR64r1_EVEX:
15225 case SHR64r1_ND:
15226 case SHR64r1_NF:
15227 case SHR64r1_NF_ND:
15228 case SHR64rCL:
15229 case SHR64rCL_EVEX:
15230 case SHR64rCL_ND:
15231 case SHR64rCL_NF:
15232 case SHR64rCL_NF_ND:
15233 case SHR64ri:
15234 case SHR64ri_EVEX:
15235 case SHR64ri_ND:
15236 case SHR64ri_NF:
15237 case SHR64ri_NF_ND:
15238 case SHR8m1:
15239 case SHR8m1_EVEX:
15240 case SHR8m1_ND:
15241 case SHR8m1_NF:
15242 case SHR8m1_NF_ND:
15243 case SHR8mCL:
15244 case SHR8mCL_EVEX:
15245 case SHR8mCL_ND:
15246 case SHR8mCL_NF:
15247 case SHR8mCL_NF_ND:
15248 case SHR8mi:
15249 case SHR8mi_EVEX:
15250 case SHR8mi_ND:
15251 case SHR8mi_NF:
15252 case SHR8mi_NF_ND:
15253 case SHR8r1:
15254 case SHR8r1_EVEX:
15255 case SHR8r1_ND:
15256 case SHR8r1_NF:
15257 case SHR8r1_NF_ND:
15258 case SHR8rCL:
15259 case SHR8rCL_EVEX:
15260 case SHR8rCL_ND:
15261 case SHR8rCL_NF:
15262 case SHR8rCL_NF_ND:
15263 case SHR8ri:
15264 case SHR8ri_EVEX:
15265 case SHR8ri_ND:
15266 case SHR8ri_NF:
15267 case SHR8ri_NF_ND:
15268 return true;
15269 }
15270 return false;
15271}
15272
15273bool isLOOPNE(unsigned Opcode) {
15274 return Opcode == LOOPNE;
15275}
15276
15277bool isVCVTTPH2UQQ(unsigned Opcode) {
15278 switch (Opcode) {
15279 case VCVTTPH2UQQZ128rm:
15280 case VCVTTPH2UQQZ128rmb:
15281 case VCVTTPH2UQQZ128rmbk:
15282 case VCVTTPH2UQQZ128rmbkz:
15283 case VCVTTPH2UQQZ128rmk:
15284 case VCVTTPH2UQQZ128rmkz:
15285 case VCVTTPH2UQQZ128rr:
15286 case VCVTTPH2UQQZ128rrk:
15287 case VCVTTPH2UQQZ128rrkz:
15288 case VCVTTPH2UQQZ256rm:
15289 case VCVTTPH2UQQZ256rmb:
15290 case VCVTTPH2UQQZ256rmbk:
15291 case VCVTTPH2UQQZ256rmbkz:
15292 case VCVTTPH2UQQZ256rmk:
15293 case VCVTTPH2UQQZ256rmkz:
15294 case VCVTTPH2UQQZ256rr:
15295 case VCVTTPH2UQQZ256rrk:
15296 case VCVTTPH2UQQZ256rrkz:
15297 case VCVTTPH2UQQZrm:
15298 case VCVTTPH2UQQZrmb:
15299 case VCVTTPH2UQQZrmbk:
15300 case VCVTTPH2UQQZrmbkz:
15301 case VCVTTPH2UQQZrmk:
15302 case VCVTTPH2UQQZrmkz:
15303 case VCVTTPH2UQQZrr:
15304 case VCVTTPH2UQQZrrb:
15305 case VCVTTPH2UQQZrrbk:
15306 case VCVTTPH2UQQZrrbkz:
15307 case VCVTTPH2UQQZrrk:
15308 case VCVTTPH2UQQZrrkz:
15309 return true;
15310 }
15311 return false;
15312}
15313
15314bool isSHA1NEXTE(unsigned Opcode) {
15315 switch (Opcode) {
15316 case SHA1NEXTErm:
15317 case SHA1NEXTErr:
15318 return true;
15319 }
15320 return false;
15321}
15322
15323bool isVFMADD132SD(unsigned Opcode) {
15324 switch (Opcode) {
15325 case VFMADD132SDZm_Int:
15326 case VFMADD132SDZmk_Int:
15327 case VFMADD132SDZmkz_Int:
15328 case VFMADD132SDZr_Int:
15329 case VFMADD132SDZrb_Int:
15330 case VFMADD132SDZrbk_Int:
15331 case VFMADD132SDZrbkz_Int:
15332 case VFMADD132SDZrk_Int:
15333 case VFMADD132SDZrkz_Int:
15334 case VFMADD132SDm_Int:
15335 case VFMADD132SDr_Int:
15336 return true;
15337 }
15338 return false;
15339}
15340
15341bool isPSRAW(unsigned Opcode) {
15342 switch (Opcode) {
15343 case MMX_PSRAWri:
15344 case MMX_PSRAWrm:
15345 case MMX_PSRAWrr:
15346 case PSRAWri:
15347 case PSRAWrm:
15348 case PSRAWrr:
15349 return true;
15350 }
15351 return false;
15352}
15353
15354bool isVPBROADCASTQ(unsigned Opcode) {
15355 switch (Opcode) {
15356 case VPBROADCASTQYrm:
15357 case VPBROADCASTQYrr:
15358 case VPBROADCASTQZ128rm:
15359 case VPBROADCASTQZ128rmk:
15360 case VPBROADCASTQZ128rmkz:
15361 case VPBROADCASTQZ128rr:
15362 case VPBROADCASTQZ128rrk:
15363 case VPBROADCASTQZ128rrkz:
15364 case VPBROADCASTQZ256rm:
15365 case VPBROADCASTQZ256rmk:
15366 case VPBROADCASTQZ256rmkz:
15367 case VPBROADCASTQZ256rr:
15368 case VPBROADCASTQZ256rrk:
15369 case VPBROADCASTQZ256rrkz:
15370 case VPBROADCASTQZrm:
15371 case VPBROADCASTQZrmk:
15372 case VPBROADCASTQZrmkz:
15373 case VPBROADCASTQZrr:
15374 case VPBROADCASTQZrrk:
15375 case VPBROADCASTQZrrkz:
15376 case VPBROADCASTQrZ128rr:
15377 case VPBROADCASTQrZ128rrk:
15378 case VPBROADCASTQrZ128rrkz:
15379 case VPBROADCASTQrZ256rr:
15380 case VPBROADCASTQrZ256rrk:
15381 case VPBROADCASTQrZ256rrkz:
15382 case VPBROADCASTQrZrr:
15383 case VPBROADCASTQrZrrk:
15384 case VPBROADCASTQrZrrkz:
15385 case VPBROADCASTQrm:
15386 case VPBROADCASTQrr:
15387 return true;
15388 }
15389 return false;
15390}
15391
15392bool isCLC(unsigned Opcode) {
15393 return Opcode == CLC;
15394}
15395
15396bool isPOPAW(unsigned Opcode) {
15397 return Opcode == POPA16;
15398}
15399
15400bool isTCMMIMFP16PS(unsigned Opcode) {
15401 return Opcode == TCMMIMFP16PS;
15402}
15403
15404bool isVCVTQQ2PH(unsigned Opcode) {
15405 switch (Opcode) {
15406 case VCVTQQ2PHZ128rm:
15407 case VCVTQQ2PHZ128rmb:
15408 case VCVTQQ2PHZ128rmbk:
15409 case VCVTQQ2PHZ128rmbkz:
15410 case VCVTQQ2PHZ128rmk:
15411 case VCVTQQ2PHZ128rmkz:
15412 case VCVTQQ2PHZ128rr:
15413 case VCVTQQ2PHZ128rrk:
15414 case VCVTQQ2PHZ128rrkz:
15415 case VCVTQQ2PHZ256rm:
15416 case VCVTQQ2PHZ256rmb:
15417 case VCVTQQ2PHZ256rmbk:
15418 case VCVTQQ2PHZ256rmbkz:
15419 case VCVTQQ2PHZ256rmk:
15420 case VCVTQQ2PHZ256rmkz:
15421 case VCVTQQ2PHZ256rr:
15422 case VCVTQQ2PHZ256rrk:
15423 case VCVTQQ2PHZ256rrkz:
15424 case VCVTQQ2PHZrm:
15425 case VCVTQQ2PHZrmb:
15426 case VCVTQQ2PHZrmbk:
15427 case VCVTQQ2PHZrmbkz:
15428 case VCVTQQ2PHZrmk:
15429 case VCVTQQ2PHZrmkz:
15430 case VCVTQQ2PHZrr:
15431 case VCVTQQ2PHZrrb:
15432 case VCVTQQ2PHZrrbk:
15433 case VCVTQQ2PHZrrbkz:
15434 case VCVTQQ2PHZrrk:
15435 case VCVTQQ2PHZrrkz:
15436 return true;
15437 }
15438 return false;
15439}
15440
15441bool isVCVTTPS2UQQ(unsigned Opcode) {
15442 switch (Opcode) {
15443 case VCVTTPS2UQQZ128rm:
15444 case VCVTTPS2UQQZ128rmb:
15445 case VCVTTPS2UQQZ128rmbk:
15446 case VCVTTPS2UQQZ128rmbkz:
15447 case VCVTTPS2UQQZ128rmk:
15448 case VCVTTPS2UQQZ128rmkz:
15449 case VCVTTPS2UQQZ128rr:
15450 case VCVTTPS2UQQZ128rrk:
15451 case VCVTTPS2UQQZ128rrkz:
15452 case VCVTTPS2UQQZ256rm:
15453 case VCVTTPS2UQQZ256rmb:
15454 case VCVTTPS2UQQZ256rmbk:
15455 case VCVTTPS2UQQZ256rmbkz:
15456 case VCVTTPS2UQQZ256rmk:
15457 case VCVTTPS2UQQZ256rmkz:
15458 case VCVTTPS2UQQZ256rr:
15459 case VCVTTPS2UQQZ256rrk:
15460 case VCVTTPS2UQQZ256rrkz:
15461 case VCVTTPS2UQQZrm:
15462 case VCVTTPS2UQQZrmb:
15463 case VCVTTPS2UQQZrmbk:
15464 case VCVTTPS2UQQZrmbkz:
15465 case VCVTTPS2UQQZrmk:
15466 case VCVTTPS2UQQZrmkz:
15467 case VCVTTPS2UQQZrr:
15468 case VCVTTPS2UQQZrrb:
15469 case VCVTTPS2UQQZrrbk:
15470 case VCVTTPS2UQQZrrbkz:
15471 case VCVTTPS2UQQZrrk:
15472 case VCVTTPS2UQQZrrkz:
15473 return true;
15474 }
15475 return false;
15476}
15477
15478bool isVMOVUPD(unsigned Opcode) {
15479 switch (Opcode) {
15480 case VMOVUPDYmr:
15481 case VMOVUPDYrm:
15482 case VMOVUPDYrr:
15483 case VMOVUPDYrr_REV:
15484 case VMOVUPDZ128mr:
15485 case VMOVUPDZ128mrk:
15486 case VMOVUPDZ128rm:
15487 case VMOVUPDZ128rmk:
15488 case VMOVUPDZ128rmkz:
15489 case VMOVUPDZ128rr:
15490 case VMOVUPDZ128rr_REV:
15491 case VMOVUPDZ128rrk:
15492 case VMOVUPDZ128rrk_REV:
15493 case VMOVUPDZ128rrkz:
15494 case VMOVUPDZ128rrkz_REV:
15495 case VMOVUPDZ256mr:
15496 case VMOVUPDZ256mrk:
15497 case VMOVUPDZ256rm:
15498 case VMOVUPDZ256rmk:
15499 case VMOVUPDZ256rmkz:
15500 case VMOVUPDZ256rr:
15501 case VMOVUPDZ256rr_REV:
15502 case VMOVUPDZ256rrk:
15503 case VMOVUPDZ256rrk_REV:
15504 case VMOVUPDZ256rrkz:
15505 case VMOVUPDZ256rrkz_REV:
15506 case VMOVUPDZmr:
15507 case VMOVUPDZmrk:
15508 case VMOVUPDZrm:
15509 case VMOVUPDZrmk:
15510 case VMOVUPDZrmkz:
15511 case VMOVUPDZrr:
15512 case VMOVUPDZrr_REV:
15513 case VMOVUPDZrrk:
15514 case VMOVUPDZrrk_REV:
15515 case VMOVUPDZrrkz:
15516 case VMOVUPDZrrkz_REV:
15517 case VMOVUPDmr:
15518 case VMOVUPDrm:
15519 case VMOVUPDrr:
15520 case VMOVUPDrr_REV:
15521 return true;
15522 }
15523 return false;
15524}
15525
15526bool isFPTAN(unsigned Opcode) {
15527 return Opcode == FPTAN;
15528}
15529
15530bool isVMASKMOVPD(unsigned Opcode) {
15531 switch (Opcode) {
15532 case VMASKMOVPDYmr:
15533 case VMASKMOVPDYrm:
15534 case VMASKMOVPDmr:
15535 case VMASKMOVPDrm:
15536 return true;
15537 }
15538 return false;
15539}
15540
15541bool isVMOVLHPS(unsigned Opcode) {
15542 switch (Opcode) {
15543 case VMOVLHPSZrr:
15544 case VMOVLHPSrr:
15545 return true;
15546 }
15547 return false;
15548}
15549
15550bool isAESKEYGENASSIST(unsigned Opcode) {
15551 switch (Opcode) {
15552 case AESKEYGENASSISTrmi:
15553 case AESKEYGENASSISTrri:
15554 return true;
15555 }
15556 return false;
15557}
15558
15559bool isXSAVEOPT64(unsigned Opcode) {
15560 return Opcode == XSAVEOPT64;
15561}
15562
15563bool isXSAVEC(unsigned Opcode) {
15564 return Opcode == XSAVEC;
15565}
15566
15567bool isVPLZCNTQ(unsigned Opcode) {
15568 switch (Opcode) {
15569 case VPLZCNTQZ128rm:
15570 case VPLZCNTQZ128rmb:
15571 case VPLZCNTQZ128rmbk:
15572 case VPLZCNTQZ128rmbkz:
15573 case VPLZCNTQZ128rmk:
15574 case VPLZCNTQZ128rmkz:
15575 case VPLZCNTQZ128rr:
15576 case VPLZCNTQZ128rrk:
15577 case VPLZCNTQZ128rrkz:
15578 case VPLZCNTQZ256rm:
15579 case VPLZCNTQZ256rmb:
15580 case VPLZCNTQZ256rmbk:
15581 case VPLZCNTQZ256rmbkz:
15582 case VPLZCNTQZ256rmk:
15583 case VPLZCNTQZ256rmkz:
15584 case VPLZCNTQZ256rr:
15585 case VPLZCNTQZ256rrk:
15586 case VPLZCNTQZ256rrkz:
15587 case VPLZCNTQZrm:
15588 case VPLZCNTQZrmb:
15589 case VPLZCNTQZrmbk:
15590 case VPLZCNTQZrmbkz:
15591 case VPLZCNTQZrmk:
15592 case VPLZCNTQZrmkz:
15593 case VPLZCNTQZrr:
15594 case VPLZCNTQZrrk:
15595 case VPLZCNTQZrrkz:
15596 return true;
15597 }
15598 return false;
15599}
15600
15601bool isVPSUBW(unsigned Opcode) {
15602 switch (Opcode) {
15603 case VPSUBWYrm:
15604 case VPSUBWYrr:
15605 case VPSUBWZ128rm:
15606 case VPSUBWZ128rmk:
15607 case VPSUBWZ128rmkz:
15608 case VPSUBWZ128rr:
15609 case VPSUBWZ128rrk:
15610 case VPSUBWZ128rrkz:
15611 case VPSUBWZ256rm:
15612 case VPSUBWZ256rmk:
15613 case VPSUBWZ256rmkz:
15614 case VPSUBWZ256rr:
15615 case VPSUBWZ256rrk:
15616 case VPSUBWZ256rrkz:
15617 case VPSUBWZrm:
15618 case VPSUBWZrmk:
15619 case VPSUBWZrmkz:
15620 case VPSUBWZrr:
15621 case VPSUBWZrrk:
15622 case VPSUBWZrrkz:
15623 case VPSUBWrm:
15624 case VPSUBWrr:
15625 return true;
15626 }
15627 return false;
15628}
15629
15630bool isCMPCCXADD(unsigned Opcode) {
15631 switch (Opcode) {
15632 case CMPCCXADDmr32:
15633 case CMPCCXADDmr32_EVEX:
15634 case CMPCCXADDmr64:
15635 case CMPCCXADDmr64_EVEX:
15636 return true;
15637 }
15638 return false;
15639}
15640
15641bool isVFMSUBADD213PH(unsigned Opcode) {
15642 switch (Opcode) {
15643 case VFMSUBADD213PHZ128m:
15644 case VFMSUBADD213PHZ128mb:
15645 case VFMSUBADD213PHZ128mbk:
15646 case VFMSUBADD213PHZ128mbkz:
15647 case VFMSUBADD213PHZ128mk:
15648 case VFMSUBADD213PHZ128mkz:
15649 case VFMSUBADD213PHZ128r:
15650 case VFMSUBADD213PHZ128rk:
15651 case VFMSUBADD213PHZ128rkz:
15652 case VFMSUBADD213PHZ256m:
15653 case VFMSUBADD213PHZ256mb:
15654 case VFMSUBADD213PHZ256mbk:
15655 case VFMSUBADD213PHZ256mbkz:
15656 case VFMSUBADD213PHZ256mk:
15657 case VFMSUBADD213PHZ256mkz:
15658 case VFMSUBADD213PHZ256r:
15659 case VFMSUBADD213PHZ256rk:
15660 case VFMSUBADD213PHZ256rkz:
15661 case VFMSUBADD213PHZm:
15662 case VFMSUBADD213PHZmb:
15663 case VFMSUBADD213PHZmbk:
15664 case VFMSUBADD213PHZmbkz:
15665 case VFMSUBADD213PHZmk:
15666 case VFMSUBADD213PHZmkz:
15667 case VFMSUBADD213PHZr:
15668 case VFMSUBADD213PHZrb:
15669 case VFMSUBADD213PHZrbk:
15670 case VFMSUBADD213PHZrbkz:
15671 case VFMSUBADD213PHZrk:
15672 case VFMSUBADD213PHZrkz:
15673 return true;
15674 }
15675 return false;
15676}
15677
15678bool isVFMADDSUBPD(unsigned Opcode) {
15679 switch (Opcode) {
15680 case VFMADDSUBPD4Ymr:
15681 case VFMADDSUBPD4Yrm:
15682 case VFMADDSUBPD4Yrr:
15683 case VFMADDSUBPD4Yrr_REV:
15684 case VFMADDSUBPD4mr:
15685 case VFMADDSUBPD4rm:
15686 case VFMADDSUBPD4rr:
15687 case VFMADDSUBPD4rr_REV:
15688 return true;
15689 }
15690 return false;
15691}
15692
15693bool isVPMINSW(unsigned Opcode) {
15694 switch (Opcode) {
15695 case VPMINSWYrm:
15696 case VPMINSWYrr:
15697 case VPMINSWZ128rm:
15698 case VPMINSWZ128rmk:
15699 case VPMINSWZ128rmkz:
15700 case VPMINSWZ128rr:
15701 case VPMINSWZ128rrk:
15702 case VPMINSWZ128rrkz:
15703 case VPMINSWZ256rm:
15704 case VPMINSWZ256rmk:
15705 case VPMINSWZ256rmkz:
15706 case VPMINSWZ256rr:
15707 case VPMINSWZ256rrk:
15708 case VPMINSWZ256rrkz:
15709 case VPMINSWZrm:
15710 case VPMINSWZrmk:
15711 case VPMINSWZrmkz:
15712 case VPMINSWZrr:
15713 case VPMINSWZrrk:
15714 case VPMINSWZrrkz:
15715 case VPMINSWrm:
15716 case VPMINSWrr:
15717 return true;
15718 }
15719 return false;
15720}
15721
15722bool isVFNMSUB132PS(unsigned Opcode) {
15723 switch (Opcode) {
15724 case VFNMSUB132PSYm:
15725 case VFNMSUB132PSYr:
15726 case VFNMSUB132PSZ128m:
15727 case VFNMSUB132PSZ128mb:
15728 case VFNMSUB132PSZ128mbk:
15729 case VFNMSUB132PSZ128mbkz:
15730 case VFNMSUB132PSZ128mk:
15731 case VFNMSUB132PSZ128mkz:
15732 case VFNMSUB132PSZ128r:
15733 case VFNMSUB132PSZ128rk:
15734 case VFNMSUB132PSZ128rkz:
15735 case VFNMSUB132PSZ256m:
15736 case VFNMSUB132PSZ256mb:
15737 case VFNMSUB132PSZ256mbk:
15738 case VFNMSUB132PSZ256mbkz:
15739 case VFNMSUB132PSZ256mk:
15740 case VFNMSUB132PSZ256mkz:
15741 case VFNMSUB132PSZ256r:
15742 case VFNMSUB132PSZ256rk:
15743 case VFNMSUB132PSZ256rkz:
15744 case VFNMSUB132PSZm:
15745 case VFNMSUB132PSZmb:
15746 case VFNMSUB132PSZmbk:
15747 case VFNMSUB132PSZmbkz:
15748 case VFNMSUB132PSZmk:
15749 case VFNMSUB132PSZmkz:
15750 case VFNMSUB132PSZr:
15751 case VFNMSUB132PSZrb:
15752 case VFNMSUB132PSZrbk:
15753 case VFNMSUB132PSZrbkz:
15754 case VFNMSUB132PSZrk:
15755 case VFNMSUB132PSZrkz:
15756 case VFNMSUB132PSm:
15757 case VFNMSUB132PSr:
15758 return true;
15759 }
15760 return false;
15761}
15762
15763bool isVMOVAPS(unsigned Opcode) {
15764 switch (Opcode) {
15765 case VMOVAPSYmr:
15766 case VMOVAPSYrm:
15767 case VMOVAPSYrr:
15768 case VMOVAPSYrr_REV:
15769 case VMOVAPSZ128mr:
15770 case VMOVAPSZ128mrk:
15771 case VMOVAPSZ128rm:
15772 case VMOVAPSZ128rmk:
15773 case VMOVAPSZ128rmkz:
15774 case VMOVAPSZ128rr:
15775 case VMOVAPSZ128rr_REV:
15776 case VMOVAPSZ128rrk:
15777 case VMOVAPSZ128rrk_REV:
15778 case VMOVAPSZ128rrkz:
15779 case VMOVAPSZ128rrkz_REV:
15780 case VMOVAPSZ256mr:
15781 case VMOVAPSZ256mrk:
15782 case VMOVAPSZ256rm:
15783 case VMOVAPSZ256rmk:
15784 case VMOVAPSZ256rmkz:
15785 case VMOVAPSZ256rr:
15786 case VMOVAPSZ256rr_REV:
15787 case VMOVAPSZ256rrk:
15788 case VMOVAPSZ256rrk_REV:
15789 case VMOVAPSZ256rrkz:
15790 case VMOVAPSZ256rrkz_REV:
15791 case VMOVAPSZmr:
15792 case VMOVAPSZmrk:
15793 case VMOVAPSZrm:
15794 case VMOVAPSZrmk:
15795 case VMOVAPSZrmkz:
15796 case VMOVAPSZrr:
15797 case VMOVAPSZrr_REV:
15798 case VMOVAPSZrrk:
15799 case VMOVAPSZrrk_REV:
15800 case VMOVAPSZrrkz:
15801 case VMOVAPSZrrkz_REV:
15802 case VMOVAPSmr:
15803 case VMOVAPSrm:
15804 case VMOVAPSrr:
15805 case VMOVAPSrr_REV:
15806 return true;
15807 }
15808 return false;
15809}
15810
15811bool isVPEXTRQ(unsigned Opcode) {
15812 switch (Opcode) {
15813 case VPEXTRQZmri:
15814 case VPEXTRQZrri:
15815 case VPEXTRQmri:
15816 case VPEXTRQrri:
15817 return true;
15818 }
15819 return false;
15820}
15821
15822bool isVSCALEFSH(unsigned Opcode) {
15823 switch (Opcode) {
15824 case VSCALEFSHZrm:
15825 case VSCALEFSHZrmk:
15826 case VSCALEFSHZrmkz:
15827 case VSCALEFSHZrr:
15828 case VSCALEFSHZrrb_Int:
15829 case VSCALEFSHZrrbk_Int:
15830 case VSCALEFSHZrrbkz_Int:
15831 case VSCALEFSHZrrk:
15832 case VSCALEFSHZrrkz:
15833 return true;
15834 }
15835 return false;
15836}
15837
15838bool isVCVTPD2PS(unsigned Opcode) {
15839 switch (Opcode) {
15840 case VCVTPD2PSYrm:
15841 case VCVTPD2PSYrr:
15842 case VCVTPD2PSZ128rm:
15843 case VCVTPD2PSZ128rmb:
15844 case VCVTPD2PSZ128rmbk:
15845 case VCVTPD2PSZ128rmbkz:
15846 case VCVTPD2PSZ128rmk:
15847 case VCVTPD2PSZ128rmkz:
15848 case VCVTPD2PSZ128rr:
15849 case VCVTPD2PSZ128rrk:
15850 case VCVTPD2PSZ128rrkz:
15851 case VCVTPD2PSZ256rm:
15852 case VCVTPD2PSZ256rmb:
15853 case VCVTPD2PSZ256rmbk:
15854 case VCVTPD2PSZ256rmbkz:
15855 case VCVTPD2PSZ256rmk:
15856 case VCVTPD2PSZ256rmkz:
15857 case VCVTPD2PSZ256rr:
15858 case VCVTPD2PSZ256rrk:
15859 case VCVTPD2PSZ256rrkz:
15860 case VCVTPD2PSZrm:
15861 case VCVTPD2PSZrmb:
15862 case VCVTPD2PSZrmbk:
15863 case VCVTPD2PSZrmbkz:
15864 case VCVTPD2PSZrmk:
15865 case VCVTPD2PSZrmkz:
15866 case VCVTPD2PSZrr:
15867 case VCVTPD2PSZrrb:
15868 case VCVTPD2PSZrrbk:
15869 case VCVTPD2PSZrrbkz:
15870 case VCVTPD2PSZrrk:
15871 case VCVTPD2PSZrrkz:
15872 case VCVTPD2PSrm:
15873 case VCVTPD2PSrr:
15874 return true;
15875 }
15876 return false;
15877}
15878
15879bool isCLGI(unsigned Opcode) {
15880 return Opcode == CLGI;
15881}
15882
15883bool isVAESDEC(unsigned Opcode) {
15884 switch (Opcode) {
15885 case VAESDECYrm:
15886 case VAESDECYrr:
15887 case VAESDECZ128rm:
15888 case VAESDECZ128rr:
15889 case VAESDECZ256rm:
15890 case VAESDECZ256rr:
15891 case VAESDECZrm:
15892 case VAESDECZrr:
15893 case VAESDECrm:
15894 case VAESDECrr:
15895 return true;
15896 }
15897 return false;
15898}
15899
15900bool isPFMUL(unsigned Opcode) {
15901 switch (Opcode) {
15902 case PFMULrm:
15903 case PFMULrr:
15904 return true;
15905 }
15906 return false;
15907}
15908
15909bool isVCVTBIASPH2BF8S(unsigned Opcode) {
15910 switch (Opcode) {
15911 case VCVTBIASPH2BF8SZ128rm:
15912 case VCVTBIASPH2BF8SZ128rmb:
15913 case VCVTBIASPH2BF8SZ128rmbk:
15914 case VCVTBIASPH2BF8SZ128rmbkz:
15915 case VCVTBIASPH2BF8SZ128rmk:
15916 case VCVTBIASPH2BF8SZ128rmkz:
15917 case VCVTBIASPH2BF8SZ128rr:
15918 case VCVTBIASPH2BF8SZ128rrk:
15919 case VCVTBIASPH2BF8SZ128rrkz:
15920 case VCVTBIASPH2BF8SZ256rm:
15921 case VCVTBIASPH2BF8SZ256rmb:
15922 case VCVTBIASPH2BF8SZ256rmbk:
15923 case VCVTBIASPH2BF8SZ256rmbkz:
15924 case VCVTBIASPH2BF8SZ256rmk:
15925 case VCVTBIASPH2BF8SZ256rmkz:
15926 case VCVTBIASPH2BF8SZ256rr:
15927 case VCVTBIASPH2BF8SZ256rrk:
15928 case VCVTBIASPH2BF8SZ256rrkz:
15929 case VCVTBIASPH2BF8SZrm:
15930 case VCVTBIASPH2BF8SZrmb:
15931 case VCVTBIASPH2BF8SZrmbk:
15932 case VCVTBIASPH2BF8SZrmbkz:
15933 case VCVTBIASPH2BF8SZrmk:
15934 case VCVTBIASPH2BF8SZrmkz:
15935 case VCVTBIASPH2BF8SZrr:
15936 case VCVTBIASPH2BF8SZrrk:
15937 case VCVTBIASPH2BF8SZrrkz:
15938 return true;
15939 }
15940 return false;
15941}
15942
15943bool isMOVDIRI(unsigned Opcode) {
15944 switch (Opcode) {
15945 case MOVDIRI32:
15946 case MOVDIRI32_EVEX:
15947 case MOVDIRI64:
15948 case MOVDIRI64_EVEX:
15949 return true;
15950 }
15951 return false;
15952}
15953
15954bool isSHUFPS(unsigned Opcode) {
15955 switch (Opcode) {
15956 case SHUFPSrmi:
15957 case SHUFPSrri:
15958 return true;
15959 }
15960 return false;
15961}
15962
15963bool isVFNMSUB231SS(unsigned Opcode) {
15964 switch (Opcode) {
15965 case VFNMSUB231SSZm_Int:
15966 case VFNMSUB231SSZmk_Int:
15967 case VFNMSUB231SSZmkz_Int:
15968 case VFNMSUB231SSZr_Int:
15969 case VFNMSUB231SSZrb_Int:
15970 case VFNMSUB231SSZrbk_Int:
15971 case VFNMSUB231SSZrbkz_Int:
15972 case VFNMSUB231SSZrk_Int:
15973 case VFNMSUB231SSZrkz_Int:
15974 case VFNMSUB231SSm_Int:
15975 case VFNMSUB231SSr_Int:
15976 return true;
15977 }
15978 return false;
15979}
15980
15981bool isVMWRITE(unsigned Opcode) {
15982 switch (Opcode) {
15983 case VMWRITE32rm:
15984 case VMWRITE32rr:
15985 case VMWRITE64rm:
15986 case VMWRITE64rr:
15987 return true;
15988 }
15989 return false;
15990}
15991
15992bool isVINSERTF128(unsigned Opcode) {
15993 switch (Opcode) {
15994 case VINSERTF128rmi:
15995 case VINSERTF128rri:
15996 return true;
15997 }
15998 return false;
15999}
16000
16001bool isFISUBR(unsigned Opcode) {
16002 switch (Opcode) {
16003 case SUBR_FI16m:
16004 case SUBR_FI32m:
16005 return true;
16006 }
16007 return false;
16008}
16009
16010bool isVINSERTI32X4(unsigned Opcode) {
16011 switch (Opcode) {
16012 case VINSERTI32X4Z256rmi:
16013 case VINSERTI32X4Z256rmik:
16014 case VINSERTI32X4Z256rmikz:
16015 case VINSERTI32X4Z256rri:
16016 case VINSERTI32X4Z256rrik:
16017 case VINSERTI32X4Z256rrikz:
16018 case VINSERTI32X4Zrmi:
16019 case VINSERTI32X4Zrmik:
16020 case VINSERTI32X4Zrmikz:
16021 case VINSERTI32X4Zrri:
16022 case VINSERTI32X4Zrrik:
16023 case VINSERTI32X4Zrrikz:
16024 return true;
16025 }
16026 return false;
16027}
16028
16029bool isVPSLLDQ(unsigned Opcode) {
16030 switch (Opcode) {
16031 case VPSLLDQYri:
16032 case VPSLLDQZ128mi:
16033 case VPSLLDQZ128ri:
16034 case VPSLLDQZ256mi:
16035 case VPSLLDQZ256ri:
16036 case VPSLLDQZmi:
16037 case VPSLLDQZri:
16038 case VPSLLDQri:
16039 return true;
16040 }
16041 return false;
16042}
16043
16044bool isPOPCNT(unsigned Opcode) {
16045 switch (Opcode) {
16046 case POPCNT16rm:
16047 case POPCNT16rm_EVEX:
16048 case POPCNT16rm_NF:
16049 case POPCNT16rr:
16050 case POPCNT16rr_EVEX:
16051 case POPCNT16rr_NF:
16052 case POPCNT32rm:
16053 case POPCNT32rm_EVEX:
16054 case POPCNT32rm_NF:
16055 case POPCNT32rr:
16056 case POPCNT32rr_EVEX:
16057 case POPCNT32rr_NF:
16058 case POPCNT64rm:
16059 case POPCNT64rm_EVEX:
16060 case POPCNT64rm_NF:
16061 case POPCNT64rr:
16062 case POPCNT64rr_EVEX:
16063 case POPCNT64rr_NF:
16064 return true;
16065 }
16066 return false;
16067}
16068
16069bool isVXORPD(unsigned Opcode) {
16070 switch (Opcode) {
16071 case VXORPDYrm:
16072 case VXORPDYrr:
16073 case VXORPDZ128rm:
16074 case VXORPDZ128rmb:
16075 case VXORPDZ128rmbk:
16076 case VXORPDZ128rmbkz:
16077 case VXORPDZ128rmk:
16078 case VXORPDZ128rmkz:
16079 case VXORPDZ128rr:
16080 case VXORPDZ128rrk:
16081 case VXORPDZ128rrkz:
16082 case VXORPDZ256rm:
16083 case VXORPDZ256rmb:
16084 case VXORPDZ256rmbk:
16085 case VXORPDZ256rmbkz:
16086 case VXORPDZ256rmk:
16087 case VXORPDZ256rmkz:
16088 case VXORPDZ256rr:
16089 case VXORPDZ256rrk:
16090 case VXORPDZ256rrkz:
16091 case VXORPDZrm:
16092 case VXORPDZrmb:
16093 case VXORPDZrmbk:
16094 case VXORPDZrmbkz:
16095 case VXORPDZrmk:
16096 case VXORPDZrmkz:
16097 case VXORPDZrr:
16098 case VXORPDZrrk:
16099 case VXORPDZrrkz:
16100 case VXORPDrm:
16101 case VXORPDrr:
16102 return true;
16103 }
16104 return false;
16105}
16106
16107bool isXLATB(unsigned Opcode) {
16108 return Opcode == XLAT;
16109}
16110
16111bool isDIV(unsigned Opcode) {
16112 switch (Opcode) {
16113 case DIV16m:
16114 case DIV16m_EVEX:
16115 case DIV16m_NF:
16116 case DIV16r:
16117 case DIV16r_EVEX:
16118 case DIV16r_NF:
16119 case DIV32m:
16120 case DIV32m_EVEX:
16121 case DIV32m_NF:
16122 case DIV32r:
16123 case DIV32r_EVEX:
16124 case DIV32r_NF:
16125 case DIV64m:
16126 case DIV64m_EVEX:
16127 case DIV64m_NF:
16128 case DIV64r:
16129 case DIV64r_EVEX:
16130 case DIV64r_NF:
16131 case DIV8m:
16132 case DIV8m_EVEX:
16133 case DIV8m_NF:
16134 case DIV8r:
16135 case DIV8r_EVEX:
16136 case DIV8r_NF:
16137 return true;
16138 }
16139 return false;
16140}
16141
16142bool isVPSHLDVQ(unsigned Opcode) {
16143 switch (Opcode) {
16144 case VPSHLDVQZ128m:
16145 case VPSHLDVQZ128mb:
16146 case VPSHLDVQZ128mbk:
16147 case VPSHLDVQZ128mbkz:
16148 case VPSHLDVQZ128mk:
16149 case VPSHLDVQZ128mkz:
16150 case VPSHLDVQZ128r:
16151 case VPSHLDVQZ128rk:
16152 case VPSHLDVQZ128rkz:
16153 case VPSHLDVQZ256m:
16154 case VPSHLDVQZ256mb:
16155 case VPSHLDVQZ256mbk:
16156 case VPSHLDVQZ256mbkz:
16157 case VPSHLDVQZ256mk:
16158 case VPSHLDVQZ256mkz:
16159 case VPSHLDVQZ256r:
16160 case VPSHLDVQZ256rk:
16161 case VPSHLDVQZ256rkz:
16162 case VPSHLDVQZm:
16163 case VPSHLDVQZmb:
16164 case VPSHLDVQZmbk:
16165 case VPSHLDVQZmbkz:
16166 case VPSHLDVQZmk:
16167 case VPSHLDVQZmkz:
16168 case VPSHLDVQZr:
16169 case VPSHLDVQZrk:
16170 case VPSHLDVQZrkz:
16171 return true;
16172 }
16173 return false;
16174}
16175
16176bool isMOVDDUP(unsigned Opcode) {
16177 switch (Opcode) {
16178 case MOVDDUPrm:
16179 case MOVDDUPrr:
16180 return true;
16181 }
16182 return false;
16183}
16184
16185bool isVMOVDQU64(unsigned Opcode) {
16186 switch (Opcode) {
16187 case VMOVDQU64Z128mr:
16188 case VMOVDQU64Z128mrk:
16189 case VMOVDQU64Z128rm:
16190 case VMOVDQU64Z128rmk:
16191 case VMOVDQU64Z128rmkz:
16192 case VMOVDQU64Z128rr:
16193 case VMOVDQU64Z128rr_REV:
16194 case VMOVDQU64Z128rrk:
16195 case VMOVDQU64Z128rrk_REV:
16196 case VMOVDQU64Z128rrkz:
16197 case VMOVDQU64Z128rrkz_REV:
16198 case VMOVDQU64Z256mr:
16199 case VMOVDQU64Z256mrk:
16200 case VMOVDQU64Z256rm:
16201 case VMOVDQU64Z256rmk:
16202 case VMOVDQU64Z256rmkz:
16203 case VMOVDQU64Z256rr:
16204 case VMOVDQU64Z256rr_REV:
16205 case VMOVDQU64Z256rrk:
16206 case VMOVDQU64Z256rrk_REV:
16207 case VMOVDQU64Z256rrkz:
16208 case VMOVDQU64Z256rrkz_REV:
16209 case VMOVDQU64Zmr:
16210 case VMOVDQU64Zmrk:
16211 case VMOVDQU64Zrm:
16212 case VMOVDQU64Zrmk:
16213 case VMOVDQU64Zrmkz:
16214 case VMOVDQU64Zrr:
16215 case VMOVDQU64Zrr_REV:
16216 case VMOVDQU64Zrrk:
16217 case VMOVDQU64Zrrk_REV:
16218 case VMOVDQU64Zrrkz:
16219 case VMOVDQU64Zrrkz_REV:
16220 return true;
16221 }
16222 return false;
16223}
16224
16225bool isVPCOMPRESSQ(unsigned Opcode) {
16226 switch (Opcode) {
16227 case VPCOMPRESSQZ128mr:
16228 case VPCOMPRESSQZ128mrk:
16229 case VPCOMPRESSQZ128rr:
16230 case VPCOMPRESSQZ128rrk:
16231 case VPCOMPRESSQZ128rrkz:
16232 case VPCOMPRESSQZ256mr:
16233 case VPCOMPRESSQZ256mrk:
16234 case VPCOMPRESSQZ256rr:
16235 case VPCOMPRESSQZ256rrk:
16236 case VPCOMPRESSQZ256rrkz:
16237 case VPCOMPRESSQZmr:
16238 case VPCOMPRESSQZmrk:
16239 case VPCOMPRESSQZrr:
16240 case VPCOMPRESSQZrrk:
16241 case VPCOMPRESSQZrrkz:
16242 return true;
16243 }
16244 return false;
16245}
16246
16247bool isVFMSUBADD132PD(unsigned Opcode) {
16248 switch (Opcode) {
16249 case VFMSUBADD132PDYm:
16250 case VFMSUBADD132PDYr:
16251 case VFMSUBADD132PDZ128m:
16252 case VFMSUBADD132PDZ128mb:
16253 case VFMSUBADD132PDZ128mbk:
16254 case VFMSUBADD132PDZ128mbkz:
16255 case VFMSUBADD132PDZ128mk:
16256 case VFMSUBADD132PDZ128mkz:
16257 case VFMSUBADD132PDZ128r:
16258 case VFMSUBADD132PDZ128rk:
16259 case VFMSUBADD132PDZ128rkz:
16260 case VFMSUBADD132PDZ256m:
16261 case VFMSUBADD132PDZ256mb:
16262 case VFMSUBADD132PDZ256mbk:
16263 case VFMSUBADD132PDZ256mbkz:
16264 case VFMSUBADD132PDZ256mk:
16265 case VFMSUBADD132PDZ256mkz:
16266 case VFMSUBADD132PDZ256r:
16267 case VFMSUBADD132PDZ256rk:
16268 case VFMSUBADD132PDZ256rkz:
16269 case VFMSUBADD132PDZm:
16270 case VFMSUBADD132PDZmb:
16271 case VFMSUBADD132PDZmbk:
16272 case VFMSUBADD132PDZmbkz:
16273 case VFMSUBADD132PDZmk:
16274 case VFMSUBADD132PDZmkz:
16275 case VFMSUBADD132PDZr:
16276 case VFMSUBADD132PDZrb:
16277 case VFMSUBADD132PDZrbk:
16278 case VFMSUBADD132PDZrbkz:
16279 case VFMSUBADD132PDZrk:
16280 case VFMSUBADD132PDZrkz:
16281 case VFMSUBADD132PDm:
16282 case VFMSUBADD132PDr:
16283 return true;
16284 }
16285 return false;
16286}
16287
16288bool isVPERMILPD(unsigned Opcode) {
16289 switch (Opcode) {
16290 case VPERMILPDYmi:
16291 case VPERMILPDYri:
16292 case VPERMILPDYrm:
16293 case VPERMILPDYrr:
16294 case VPERMILPDZ128mbi:
16295 case VPERMILPDZ128mbik:
16296 case VPERMILPDZ128mbikz:
16297 case VPERMILPDZ128mi:
16298 case VPERMILPDZ128mik:
16299 case VPERMILPDZ128mikz:
16300 case VPERMILPDZ128ri:
16301 case VPERMILPDZ128rik:
16302 case VPERMILPDZ128rikz:
16303 case VPERMILPDZ128rm:
16304 case VPERMILPDZ128rmb:
16305 case VPERMILPDZ128rmbk:
16306 case VPERMILPDZ128rmbkz:
16307 case VPERMILPDZ128rmk:
16308 case VPERMILPDZ128rmkz:
16309 case VPERMILPDZ128rr:
16310 case VPERMILPDZ128rrk:
16311 case VPERMILPDZ128rrkz:
16312 case VPERMILPDZ256mbi:
16313 case VPERMILPDZ256mbik:
16314 case VPERMILPDZ256mbikz:
16315 case VPERMILPDZ256mi:
16316 case VPERMILPDZ256mik:
16317 case VPERMILPDZ256mikz:
16318 case VPERMILPDZ256ri:
16319 case VPERMILPDZ256rik:
16320 case VPERMILPDZ256rikz:
16321 case VPERMILPDZ256rm:
16322 case VPERMILPDZ256rmb:
16323 case VPERMILPDZ256rmbk:
16324 case VPERMILPDZ256rmbkz:
16325 case VPERMILPDZ256rmk:
16326 case VPERMILPDZ256rmkz:
16327 case VPERMILPDZ256rr:
16328 case VPERMILPDZ256rrk:
16329 case VPERMILPDZ256rrkz:
16330 case VPERMILPDZmbi:
16331 case VPERMILPDZmbik:
16332 case VPERMILPDZmbikz:
16333 case VPERMILPDZmi:
16334 case VPERMILPDZmik:
16335 case VPERMILPDZmikz:
16336 case VPERMILPDZri:
16337 case VPERMILPDZrik:
16338 case VPERMILPDZrikz:
16339 case VPERMILPDZrm:
16340 case VPERMILPDZrmb:
16341 case VPERMILPDZrmbk:
16342 case VPERMILPDZrmbkz:
16343 case VPERMILPDZrmk:
16344 case VPERMILPDZrmkz:
16345 case VPERMILPDZrr:
16346 case VPERMILPDZrrk:
16347 case VPERMILPDZrrkz:
16348 case VPERMILPDmi:
16349 case VPERMILPDri:
16350 case VPERMILPDrm:
16351 case VPERMILPDrr:
16352 return true;
16353 }
16354 return false;
16355}
16356
16357bool isADDSD(unsigned Opcode) {
16358 switch (Opcode) {
16359 case ADDSDrm_Int:
16360 case ADDSDrr_Int:
16361 return true;
16362 }
16363 return false;
16364}
16365
16366bool isBLENDPD(unsigned Opcode) {
16367 switch (Opcode) {
16368 case BLENDPDrmi:
16369 case BLENDPDrri:
16370 return true;
16371 }
16372 return false;
16373}
16374
16375bool isVPANDQ(unsigned Opcode) {
16376 switch (Opcode) {
16377 case VPANDQZ128rm:
16378 case VPANDQZ128rmb:
16379 case VPANDQZ128rmbk:
16380 case VPANDQZ128rmbkz:
16381 case VPANDQZ128rmk:
16382 case VPANDQZ128rmkz:
16383 case VPANDQZ128rr:
16384 case VPANDQZ128rrk:
16385 case VPANDQZ128rrkz:
16386 case VPANDQZ256rm:
16387 case VPANDQZ256rmb:
16388 case VPANDQZ256rmbk:
16389 case VPANDQZ256rmbkz:
16390 case VPANDQZ256rmk:
16391 case VPANDQZ256rmkz:
16392 case VPANDQZ256rr:
16393 case VPANDQZ256rrk:
16394 case VPANDQZ256rrkz:
16395 case VPANDQZrm:
16396 case VPANDQZrmb:
16397 case VPANDQZrmbk:
16398 case VPANDQZrmbkz:
16399 case VPANDQZrmk:
16400 case VPANDQZrmkz:
16401 case VPANDQZrr:
16402 case VPANDQZrrk:
16403 case VPANDQZrrkz:
16404 return true;
16405 }
16406 return false;
16407}
16408
16409bool isPMADDUBSW(unsigned Opcode) {
16410 switch (Opcode) {
16411 case MMX_PMADDUBSWrm:
16412 case MMX_PMADDUBSWrr:
16413 case PMADDUBSWrm:
16414 case PMADDUBSWrr:
16415 return true;
16416 }
16417 return false;
16418}
16419
16420bool isPOPFD(unsigned Opcode) {
16421 return Opcode == POPF32;
16422}
16423
16424bool isCMPSW(unsigned Opcode) {
16425 return Opcode == CMPSW;
16426}
16427
16428bool isLDMXCSR(unsigned Opcode) {
16429 return Opcode == LDMXCSR;
16430}
16431
16432bool isVMULPS(unsigned Opcode) {
16433 switch (Opcode) {
16434 case VMULPSYrm:
16435 case VMULPSYrr:
16436 case VMULPSZ128rm:
16437 case VMULPSZ128rmb:
16438 case VMULPSZ128rmbk:
16439 case VMULPSZ128rmbkz:
16440 case VMULPSZ128rmk:
16441 case VMULPSZ128rmkz:
16442 case VMULPSZ128rr:
16443 case VMULPSZ128rrk:
16444 case VMULPSZ128rrkz:
16445 case VMULPSZ256rm:
16446 case VMULPSZ256rmb:
16447 case VMULPSZ256rmbk:
16448 case VMULPSZ256rmbkz:
16449 case VMULPSZ256rmk:
16450 case VMULPSZ256rmkz:
16451 case VMULPSZ256rr:
16452 case VMULPSZ256rrk:
16453 case VMULPSZ256rrkz:
16454 case VMULPSZrm:
16455 case VMULPSZrmb:
16456 case VMULPSZrmbk:
16457 case VMULPSZrmbkz:
16458 case VMULPSZrmk:
16459 case VMULPSZrmkz:
16460 case VMULPSZrr:
16461 case VMULPSZrrb:
16462 case VMULPSZrrbk:
16463 case VMULPSZrrbkz:
16464 case VMULPSZrrk:
16465 case VMULPSZrrkz:
16466 case VMULPSrm:
16467 case VMULPSrr:
16468 return true;
16469 }
16470 return false;
16471}
16472
16473bool isVROUNDSD(unsigned Opcode) {
16474 switch (Opcode) {
16475 case VROUNDSDmi_Int:
16476 case VROUNDSDri_Int:
16477 return true;
16478 }
16479 return false;
16480}
16481
16482bool isVFMADD132PD(unsigned Opcode) {
16483 switch (Opcode) {
16484 case VFMADD132PDYm:
16485 case VFMADD132PDYr:
16486 case VFMADD132PDZ128m:
16487 case VFMADD132PDZ128mb:
16488 case VFMADD132PDZ128mbk:
16489 case VFMADD132PDZ128mbkz:
16490 case VFMADD132PDZ128mk:
16491 case VFMADD132PDZ128mkz:
16492 case VFMADD132PDZ128r:
16493 case VFMADD132PDZ128rk:
16494 case VFMADD132PDZ128rkz:
16495 case VFMADD132PDZ256m:
16496 case VFMADD132PDZ256mb:
16497 case VFMADD132PDZ256mbk:
16498 case VFMADD132PDZ256mbkz:
16499 case VFMADD132PDZ256mk:
16500 case VFMADD132PDZ256mkz:
16501 case VFMADD132PDZ256r:
16502 case VFMADD132PDZ256rk:
16503 case VFMADD132PDZ256rkz:
16504 case VFMADD132PDZm:
16505 case VFMADD132PDZmb:
16506 case VFMADD132PDZmbk:
16507 case VFMADD132PDZmbkz:
16508 case VFMADD132PDZmk:
16509 case VFMADD132PDZmkz:
16510 case VFMADD132PDZr:
16511 case VFMADD132PDZrb:
16512 case VFMADD132PDZrbk:
16513 case VFMADD132PDZrbkz:
16514 case VFMADD132PDZrk:
16515 case VFMADD132PDZrkz:
16516 case VFMADD132PDm:
16517 case VFMADD132PDr:
16518 return true;
16519 }
16520 return false;
16521}
16522
16523bool isVPSRAQ(unsigned Opcode) {
16524 switch (Opcode) {
16525 case VPSRAQZ128mbi:
16526 case VPSRAQZ128mbik:
16527 case VPSRAQZ128mbikz:
16528 case VPSRAQZ128mi:
16529 case VPSRAQZ128mik:
16530 case VPSRAQZ128mikz:
16531 case VPSRAQZ128ri:
16532 case VPSRAQZ128rik:
16533 case VPSRAQZ128rikz:
16534 case VPSRAQZ128rm:
16535 case VPSRAQZ128rmk:
16536 case VPSRAQZ128rmkz:
16537 case VPSRAQZ128rr:
16538 case VPSRAQZ128rrk:
16539 case VPSRAQZ128rrkz:
16540 case VPSRAQZ256mbi:
16541 case VPSRAQZ256mbik:
16542 case VPSRAQZ256mbikz:
16543 case VPSRAQZ256mi:
16544 case VPSRAQZ256mik:
16545 case VPSRAQZ256mikz:
16546 case VPSRAQZ256ri:
16547 case VPSRAQZ256rik:
16548 case VPSRAQZ256rikz:
16549 case VPSRAQZ256rm:
16550 case VPSRAQZ256rmk:
16551 case VPSRAQZ256rmkz:
16552 case VPSRAQZ256rr:
16553 case VPSRAQZ256rrk:
16554 case VPSRAQZ256rrkz:
16555 case VPSRAQZmbi:
16556 case VPSRAQZmbik:
16557 case VPSRAQZmbikz:
16558 case VPSRAQZmi:
16559 case VPSRAQZmik:
16560 case VPSRAQZmikz:
16561 case VPSRAQZri:
16562 case VPSRAQZrik:
16563 case VPSRAQZrikz:
16564 case VPSRAQZrm:
16565 case VPSRAQZrmk:
16566 case VPSRAQZrmkz:
16567 case VPSRAQZrr:
16568 case VPSRAQZrrk:
16569 case VPSRAQZrrkz:
16570 return true;
16571 }
16572 return false;
16573}
16574
16575bool isVCOMISD(unsigned Opcode) {
16576 switch (Opcode) {
16577 case VCOMISDZrm:
16578 case VCOMISDZrr:
16579 case VCOMISDZrrb:
16580 case VCOMISDrm:
16581 case VCOMISDrr:
16582 return true;
16583 }
16584 return false;
16585}
16586
16587bool isVCVTBIASPH2BF8(unsigned Opcode) {
16588 switch (Opcode) {
16589 case VCVTBIASPH2BF8Z128rm:
16590 case VCVTBIASPH2BF8Z128rmb:
16591 case VCVTBIASPH2BF8Z128rmbk:
16592 case VCVTBIASPH2BF8Z128rmbkz:
16593 case VCVTBIASPH2BF8Z128rmk:
16594 case VCVTBIASPH2BF8Z128rmkz:
16595 case VCVTBIASPH2BF8Z128rr:
16596 case VCVTBIASPH2BF8Z128rrk:
16597 case VCVTBIASPH2BF8Z128rrkz:
16598 case VCVTBIASPH2BF8Z256rm:
16599 case VCVTBIASPH2BF8Z256rmb:
16600 case VCVTBIASPH2BF8Z256rmbk:
16601 case VCVTBIASPH2BF8Z256rmbkz:
16602 case VCVTBIASPH2BF8Z256rmk:
16603 case VCVTBIASPH2BF8Z256rmkz:
16604 case VCVTBIASPH2BF8Z256rr:
16605 case VCVTBIASPH2BF8Z256rrk:
16606 case VCVTBIASPH2BF8Z256rrkz:
16607 case VCVTBIASPH2BF8Zrm:
16608 case VCVTBIASPH2BF8Zrmb:
16609 case VCVTBIASPH2BF8Zrmbk:
16610 case VCVTBIASPH2BF8Zrmbkz:
16611 case VCVTBIASPH2BF8Zrmk:
16612 case VCVTBIASPH2BF8Zrmkz:
16613 case VCVTBIASPH2BF8Zrr:
16614 case VCVTBIASPH2BF8Zrrk:
16615 case VCVTBIASPH2BF8Zrrkz:
16616 return true;
16617 }
16618 return false;
16619}
16620
16621bool isFFREEP(unsigned Opcode) {
16622 return Opcode == FFREEP;
16623}
16624
16625bool isVFNMADD213PD(unsigned Opcode) {
16626 switch (Opcode) {
16627 case VFNMADD213PDYm:
16628 case VFNMADD213PDYr:
16629 case VFNMADD213PDZ128m:
16630 case VFNMADD213PDZ128mb:
16631 case VFNMADD213PDZ128mbk:
16632 case VFNMADD213PDZ128mbkz:
16633 case VFNMADD213PDZ128mk:
16634 case VFNMADD213PDZ128mkz:
16635 case VFNMADD213PDZ128r:
16636 case VFNMADD213PDZ128rk:
16637 case VFNMADD213PDZ128rkz:
16638 case VFNMADD213PDZ256m:
16639 case VFNMADD213PDZ256mb:
16640 case VFNMADD213PDZ256mbk:
16641 case VFNMADD213PDZ256mbkz:
16642 case VFNMADD213PDZ256mk:
16643 case VFNMADD213PDZ256mkz:
16644 case VFNMADD213PDZ256r:
16645 case VFNMADD213PDZ256rk:
16646 case VFNMADD213PDZ256rkz:
16647 case VFNMADD213PDZm:
16648 case VFNMADD213PDZmb:
16649 case VFNMADD213PDZmbk:
16650 case VFNMADD213PDZmbkz:
16651 case VFNMADD213PDZmk:
16652 case VFNMADD213PDZmkz:
16653 case VFNMADD213PDZr:
16654 case VFNMADD213PDZrb:
16655 case VFNMADD213PDZrbk:
16656 case VFNMADD213PDZrbkz:
16657 case VFNMADD213PDZrk:
16658 case VFNMADD213PDZrkz:
16659 case VFNMADD213PDm:
16660 case VFNMADD213PDr:
16661 return true;
16662 }
16663 return false;
16664}
16665
16666bool isVCMPPD(unsigned Opcode) {
16667 switch (Opcode) {
16668 case VCMPPDYrmi:
16669 case VCMPPDYrri:
16670 case VCMPPDZ128rmbi:
16671 case VCMPPDZ128rmbik:
16672 case VCMPPDZ128rmi:
16673 case VCMPPDZ128rmik:
16674 case VCMPPDZ128rri:
16675 case VCMPPDZ128rrik:
16676 case VCMPPDZ256rmbi:
16677 case VCMPPDZ256rmbik:
16678 case VCMPPDZ256rmi:
16679 case VCMPPDZ256rmik:
16680 case VCMPPDZ256rri:
16681 case VCMPPDZ256rrik:
16682 case VCMPPDZrmbi:
16683 case VCMPPDZrmbik:
16684 case VCMPPDZrmi:
16685 case VCMPPDZrmik:
16686 case VCMPPDZrri:
16687 case VCMPPDZrrib:
16688 case VCMPPDZrribk:
16689 case VCMPPDZrrik:
16690 case VCMPPDrmi:
16691 case VCMPPDrri:
16692 return true;
16693 }
16694 return false;
16695}
16696
16697bool isVFNMSUB132PH(unsigned Opcode) {
16698 switch (Opcode) {
16699 case VFNMSUB132PHZ128m:
16700 case VFNMSUB132PHZ128mb:
16701 case VFNMSUB132PHZ128mbk:
16702 case VFNMSUB132PHZ128mbkz:
16703 case VFNMSUB132PHZ128mk:
16704 case VFNMSUB132PHZ128mkz:
16705 case VFNMSUB132PHZ128r:
16706 case VFNMSUB132PHZ128rk:
16707 case VFNMSUB132PHZ128rkz:
16708 case VFNMSUB132PHZ256m:
16709 case VFNMSUB132PHZ256mb:
16710 case VFNMSUB132PHZ256mbk:
16711 case VFNMSUB132PHZ256mbkz:
16712 case VFNMSUB132PHZ256mk:
16713 case VFNMSUB132PHZ256mkz:
16714 case VFNMSUB132PHZ256r:
16715 case VFNMSUB132PHZ256rk:
16716 case VFNMSUB132PHZ256rkz:
16717 case VFNMSUB132PHZm:
16718 case VFNMSUB132PHZmb:
16719 case VFNMSUB132PHZmbk:
16720 case VFNMSUB132PHZmbkz:
16721 case VFNMSUB132PHZmk:
16722 case VFNMSUB132PHZmkz:
16723 case VFNMSUB132PHZr:
16724 case VFNMSUB132PHZrb:
16725 case VFNMSUB132PHZrbk:
16726 case VFNMSUB132PHZrbkz:
16727 case VFNMSUB132PHZrk:
16728 case VFNMSUB132PHZrkz:
16729 return true;
16730 }
16731 return false;
16732}
16733
16734bool isVPHADDBW(unsigned Opcode) {
16735 switch (Opcode) {
16736 case VPHADDBWrm:
16737 case VPHADDBWrr:
16738 return true;
16739 }
16740 return false;
16741}
16742
16743bool isVPPERM(unsigned Opcode) {
16744 switch (Opcode) {
16745 case VPPERMrmr:
16746 case VPPERMrrm:
16747 case VPPERMrrr:
16748 case VPPERMrrr_REV:
16749 return true;
16750 }
16751 return false;
16752}
16753
16754bool isVCVTPS2PD(unsigned Opcode) {
16755 switch (Opcode) {
16756 case VCVTPS2PDYrm:
16757 case VCVTPS2PDYrr:
16758 case VCVTPS2PDZ128rm:
16759 case VCVTPS2PDZ128rmb:
16760 case VCVTPS2PDZ128rmbk:
16761 case VCVTPS2PDZ128rmbkz:
16762 case VCVTPS2PDZ128rmk:
16763 case VCVTPS2PDZ128rmkz:
16764 case VCVTPS2PDZ128rr:
16765 case VCVTPS2PDZ128rrk:
16766 case VCVTPS2PDZ128rrkz:
16767 case VCVTPS2PDZ256rm:
16768 case VCVTPS2PDZ256rmb:
16769 case VCVTPS2PDZ256rmbk:
16770 case VCVTPS2PDZ256rmbkz:
16771 case VCVTPS2PDZ256rmk:
16772 case VCVTPS2PDZ256rmkz:
16773 case VCVTPS2PDZ256rr:
16774 case VCVTPS2PDZ256rrk:
16775 case VCVTPS2PDZ256rrkz:
16776 case VCVTPS2PDZrm:
16777 case VCVTPS2PDZrmb:
16778 case VCVTPS2PDZrmbk:
16779 case VCVTPS2PDZrmbkz:
16780 case VCVTPS2PDZrmk:
16781 case VCVTPS2PDZrmkz:
16782 case VCVTPS2PDZrr:
16783 case VCVTPS2PDZrrb:
16784 case VCVTPS2PDZrrbk:
16785 case VCVTPS2PDZrrbkz:
16786 case VCVTPS2PDZrrk:
16787 case VCVTPS2PDZrrkz:
16788 case VCVTPS2PDrm:
16789 case VCVTPS2PDrr:
16790 return true;
16791 }
16792 return false;
16793}
16794
16795bool isCBW(unsigned Opcode) {
16796 return Opcode == CBW;
16797}
16798
16799bool isVMOVUPS(unsigned Opcode) {
16800 switch (Opcode) {
16801 case VMOVUPSYmr:
16802 case VMOVUPSYrm:
16803 case VMOVUPSYrr:
16804 case VMOVUPSYrr_REV:
16805 case VMOVUPSZ128mr:
16806 case VMOVUPSZ128mrk:
16807 case VMOVUPSZ128rm:
16808 case VMOVUPSZ128rmk:
16809 case VMOVUPSZ128rmkz:
16810 case VMOVUPSZ128rr:
16811 case VMOVUPSZ128rr_REV:
16812 case VMOVUPSZ128rrk:
16813 case VMOVUPSZ128rrk_REV:
16814 case VMOVUPSZ128rrkz:
16815 case VMOVUPSZ128rrkz_REV:
16816 case VMOVUPSZ256mr:
16817 case VMOVUPSZ256mrk:
16818 case VMOVUPSZ256rm:
16819 case VMOVUPSZ256rmk:
16820 case VMOVUPSZ256rmkz:
16821 case VMOVUPSZ256rr:
16822 case VMOVUPSZ256rr_REV:
16823 case VMOVUPSZ256rrk:
16824 case VMOVUPSZ256rrk_REV:
16825 case VMOVUPSZ256rrkz:
16826 case VMOVUPSZ256rrkz_REV:
16827 case VMOVUPSZmr:
16828 case VMOVUPSZmrk:
16829 case VMOVUPSZrm:
16830 case VMOVUPSZrmk:
16831 case VMOVUPSZrmkz:
16832 case VMOVUPSZrr:
16833 case VMOVUPSZrr_REV:
16834 case VMOVUPSZrrk:
16835 case VMOVUPSZrrk_REV:
16836 case VMOVUPSZrrkz:
16837 case VMOVUPSZrrkz_REV:
16838 case VMOVUPSmr:
16839 case VMOVUPSrm:
16840 case VMOVUPSrr:
16841 case VMOVUPSrr_REV:
16842 return true;
16843 }
16844 return false;
16845}
16846
16847bool isVPMAXUQ(unsigned Opcode) {
16848 switch (Opcode) {
16849 case VPMAXUQZ128rm:
16850 case VPMAXUQZ128rmb:
16851 case VPMAXUQZ128rmbk:
16852 case VPMAXUQZ128rmbkz:
16853 case VPMAXUQZ128rmk:
16854 case VPMAXUQZ128rmkz:
16855 case VPMAXUQZ128rr:
16856 case VPMAXUQZ128rrk:
16857 case VPMAXUQZ128rrkz:
16858 case VPMAXUQZ256rm:
16859 case VPMAXUQZ256rmb:
16860 case VPMAXUQZ256rmbk:
16861 case VPMAXUQZ256rmbkz:
16862 case VPMAXUQZ256rmk:
16863 case VPMAXUQZ256rmkz:
16864 case VPMAXUQZ256rr:
16865 case VPMAXUQZ256rrk:
16866 case VPMAXUQZ256rrkz:
16867 case VPMAXUQZrm:
16868 case VPMAXUQZrmb:
16869 case VPMAXUQZrmbk:
16870 case VPMAXUQZrmbkz:
16871 case VPMAXUQZrmk:
16872 case VPMAXUQZrmkz:
16873 case VPMAXUQZrr:
16874 case VPMAXUQZrrk:
16875 case VPMAXUQZrrkz:
16876 return true;
16877 }
16878 return false;
16879}
16880
16881bool isWRSSQ(unsigned Opcode) {
16882 switch (Opcode) {
16883 case WRSSQ:
16884 case WRSSQ_EVEX:
16885 return true;
16886 }
16887 return false;
16888}
16889
16890bool isPACKUSDW(unsigned Opcode) {
16891 switch (Opcode) {
16892 case PACKUSDWrm:
16893 case PACKUSDWrr:
16894 return true;
16895 }
16896 return false;
16897}
16898
16899bool isVCVTTBF162IBS(unsigned Opcode) {
16900 switch (Opcode) {
16901 case VCVTTBF162IBSZ128rm:
16902 case VCVTTBF162IBSZ128rmb:
16903 case VCVTTBF162IBSZ128rmbk:
16904 case VCVTTBF162IBSZ128rmbkz:
16905 case VCVTTBF162IBSZ128rmk:
16906 case VCVTTBF162IBSZ128rmkz:
16907 case VCVTTBF162IBSZ128rr:
16908 case VCVTTBF162IBSZ128rrk:
16909 case VCVTTBF162IBSZ128rrkz:
16910 case VCVTTBF162IBSZ256rm:
16911 case VCVTTBF162IBSZ256rmb:
16912 case VCVTTBF162IBSZ256rmbk:
16913 case VCVTTBF162IBSZ256rmbkz:
16914 case VCVTTBF162IBSZ256rmk:
16915 case VCVTTBF162IBSZ256rmkz:
16916 case VCVTTBF162IBSZ256rr:
16917 case VCVTTBF162IBSZ256rrk:
16918 case VCVTTBF162IBSZ256rrkz:
16919 case VCVTTBF162IBSZrm:
16920 case VCVTTBF162IBSZrmb:
16921 case VCVTTBF162IBSZrmbk:
16922 case VCVTTBF162IBSZrmbkz:
16923 case VCVTTBF162IBSZrmk:
16924 case VCVTTBF162IBSZrmkz:
16925 case VCVTTBF162IBSZrr:
16926 case VCVTTBF162IBSZrrk:
16927 case VCVTTBF162IBSZrrkz:
16928 return true;
16929 }
16930 return false;
16931}
16932
16933bool isXBEGIN(unsigned Opcode) {
16934 switch (Opcode) {
16935 case XBEGIN_2:
16936 case XBEGIN_4:
16937 return true;
16938 }
16939 return false;
16940}
16941
16942bool isVCVTPD2UQQ(unsigned Opcode) {
16943 switch (Opcode) {
16944 case VCVTPD2UQQZ128rm:
16945 case VCVTPD2UQQZ128rmb:
16946 case VCVTPD2UQQZ128rmbk:
16947 case VCVTPD2UQQZ128rmbkz:
16948 case VCVTPD2UQQZ128rmk:
16949 case VCVTPD2UQQZ128rmkz:
16950 case VCVTPD2UQQZ128rr:
16951 case VCVTPD2UQQZ128rrk:
16952 case VCVTPD2UQQZ128rrkz:
16953 case VCVTPD2UQQZ256rm:
16954 case VCVTPD2UQQZ256rmb:
16955 case VCVTPD2UQQZ256rmbk:
16956 case VCVTPD2UQQZ256rmbkz:
16957 case VCVTPD2UQQZ256rmk:
16958 case VCVTPD2UQQZ256rmkz:
16959 case VCVTPD2UQQZ256rr:
16960 case VCVTPD2UQQZ256rrk:
16961 case VCVTPD2UQQZ256rrkz:
16962 case VCVTPD2UQQZrm:
16963 case VCVTPD2UQQZrmb:
16964 case VCVTPD2UQQZrmbk:
16965 case VCVTPD2UQQZrmbkz:
16966 case VCVTPD2UQQZrmk:
16967 case VCVTPD2UQQZrmkz:
16968 case VCVTPD2UQQZrr:
16969 case VCVTPD2UQQZrrb:
16970 case VCVTPD2UQQZrrbk:
16971 case VCVTPD2UQQZrrbkz:
16972 case VCVTPD2UQQZrrk:
16973 case VCVTPD2UQQZrrkz:
16974 return true;
16975 }
16976 return false;
16977}
16978
16979bool isFCMOVB(unsigned Opcode) {
16980 return Opcode == CMOVB_F;
16981}
16982
16983bool isNOP(unsigned Opcode) {
16984 switch (Opcode) {
16985 case NOOP:
16986 case NOOPL:
16987 case NOOPLr:
16988 case NOOPQ:
16989 case NOOPQr:
16990 case NOOPW:
16991 case NOOPWr:
16992 return true;
16993 }
16994 return false;
16995}
16996
16997bool isVPABSQ(unsigned Opcode) {
16998 switch (Opcode) {
16999 case VPABSQZ128rm:
17000 case VPABSQZ128rmb:
17001 case VPABSQZ128rmbk:
17002 case VPABSQZ128rmbkz:
17003 case VPABSQZ128rmk:
17004 case VPABSQZ128rmkz:
17005 case VPABSQZ128rr:
17006 case VPABSQZ128rrk:
17007 case VPABSQZ128rrkz:
17008 case VPABSQZ256rm:
17009 case VPABSQZ256rmb:
17010 case VPABSQZ256rmbk:
17011 case VPABSQZ256rmbkz:
17012 case VPABSQZ256rmk:
17013 case VPABSQZ256rmkz:
17014 case VPABSQZ256rr:
17015 case VPABSQZ256rrk:
17016 case VPABSQZ256rrkz:
17017 case VPABSQZrm:
17018 case VPABSQZrmb:
17019 case VPABSQZrmbk:
17020 case VPABSQZrmbkz:
17021 case VPABSQZrmk:
17022 case VPABSQZrmkz:
17023 case VPABSQZrr:
17024 case VPABSQZrrk:
17025 case VPABSQZrrkz:
17026 return true;
17027 }
17028 return false;
17029}
17030
17031bool isVTESTPS(unsigned Opcode) {
17032 switch (Opcode) {
17033 case VTESTPSYrm:
17034 case VTESTPSYrr:
17035 case VTESTPSrm:
17036 case VTESTPSrr:
17037 return true;
17038 }
17039 return false;
17040}
17041
17042bool isPHSUBW(unsigned Opcode) {
17043 switch (Opcode) {
17044 case MMX_PHSUBWrm:
17045 case MMX_PHSUBWrr:
17046 case PHSUBWrm:
17047 case PHSUBWrr:
17048 return true;
17049 }
17050 return false;
17051}
17052
17053bool isPUSH2P(unsigned Opcode) {
17054 return Opcode == PUSH2P;
17055}
17056
17057bool isFISTTP(unsigned Opcode) {
17058 switch (Opcode) {
17059 case ISTT_FP16m:
17060 case ISTT_FP32m:
17061 case ISTT_FP64m:
17062 return true;
17063 }
17064 return false;
17065}
17066
17067bool isCFCMOVCC(unsigned Opcode) {
17068 switch (Opcode) {
17069 case CFCMOV16mr:
17070 case CFCMOV16rm:
17071 case CFCMOV16rm_ND:
17072 case CFCMOV16rr:
17073 case CFCMOV16rr_ND:
17074 case CFCMOV16rr_REV:
17075 case CFCMOV32mr:
17076 case CFCMOV32rm:
17077 case CFCMOV32rm_ND:
17078 case CFCMOV32rr:
17079 case CFCMOV32rr_ND:
17080 case CFCMOV32rr_REV:
17081 case CFCMOV64mr:
17082 case CFCMOV64rm:
17083 case CFCMOV64rm_ND:
17084 case CFCMOV64rr:
17085 case CFCMOV64rr_ND:
17086 case CFCMOV64rr_REV:
17087 return true;
17088 }
17089 return false;
17090}
17091
17092bool isPCMPESTRM(unsigned Opcode) {
17093 switch (Opcode) {
17094 case PCMPESTRMrmi:
17095 case PCMPESTRMrri:
17096 return true;
17097 }
17098 return false;
17099}
17100
17101bool isVPINSRD(unsigned Opcode) {
17102 switch (Opcode) {
17103 case VPINSRDZrmi:
17104 case VPINSRDZrri:
17105 case VPINSRDrmi:
17106 case VPINSRDrri:
17107 return true;
17108 }
17109 return false;
17110}
17111
17112bool isVFNMSUB213PS(unsigned Opcode) {
17113 switch (Opcode) {
17114 case VFNMSUB213PSYm:
17115 case VFNMSUB213PSYr:
17116 case VFNMSUB213PSZ128m:
17117 case VFNMSUB213PSZ128mb:
17118 case VFNMSUB213PSZ128mbk:
17119 case VFNMSUB213PSZ128mbkz:
17120 case VFNMSUB213PSZ128mk:
17121 case VFNMSUB213PSZ128mkz:
17122 case VFNMSUB213PSZ128r:
17123 case VFNMSUB213PSZ128rk:
17124 case VFNMSUB213PSZ128rkz:
17125 case VFNMSUB213PSZ256m:
17126 case VFNMSUB213PSZ256mb:
17127 case VFNMSUB213PSZ256mbk:
17128 case VFNMSUB213PSZ256mbkz:
17129 case VFNMSUB213PSZ256mk:
17130 case VFNMSUB213PSZ256mkz:
17131 case VFNMSUB213PSZ256r:
17132 case VFNMSUB213PSZ256rk:
17133 case VFNMSUB213PSZ256rkz:
17134 case VFNMSUB213PSZm:
17135 case VFNMSUB213PSZmb:
17136 case VFNMSUB213PSZmbk:
17137 case VFNMSUB213PSZmbkz:
17138 case VFNMSUB213PSZmk:
17139 case VFNMSUB213PSZmkz:
17140 case VFNMSUB213PSZr:
17141 case VFNMSUB213PSZrb:
17142 case VFNMSUB213PSZrbk:
17143 case VFNMSUB213PSZrbkz:
17144 case VFNMSUB213PSZrk:
17145 case VFNMSUB213PSZrkz:
17146 case VFNMSUB213PSm:
17147 case VFNMSUB213PSr:
17148 return true;
17149 }
17150 return false;
17151}
17152
17153bool isPHSUBD(unsigned Opcode) {
17154 switch (Opcode) {
17155 case MMX_PHSUBDrm:
17156 case MMX_PHSUBDrr:
17157 case PHSUBDrm:
17158 case PHSUBDrr:
17159 return true;
17160 }
17161 return false;
17162}
17163
17164bool isSLDT(unsigned Opcode) {
17165 switch (Opcode) {
17166 case SLDT16m:
17167 case SLDT16r:
17168 case SLDT32r:
17169 case SLDT64r:
17170 return true;
17171 }
17172 return false;
17173}
17174
17175bool isVCVTTPD2DQS(unsigned Opcode) {
17176 switch (Opcode) {
17177 case VCVTTPD2DQSZ128rm:
17178 case VCVTTPD2DQSZ128rmb:
17179 case VCVTTPD2DQSZ128rmbk:
17180 case VCVTTPD2DQSZ128rmbkz:
17181 case VCVTTPD2DQSZ128rmk:
17182 case VCVTTPD2DQSZ128rmkz:
17183 case VCVTTPD2DQSZ128rr:
17184 case VCVTTPD2DQSZ128rrk:
17185 case VCVTTPD2DQSZ128rrkz:
17186 case VCVTTPD2DQSZ256rm:
17187 case VCVTTPD2DQSZ256rmb:
17188 case VCVTTPD2DQSZ256rmbk:
17189 case VCVTTPD2DQSZ256rmbkz:
17190 case VCVTTPD2DQSZ256rmk:
17191 case VCVTTPD2DQSZ256rmkz:
17192 case VCVTTPD2DQSZ256rr:
17193 case VCVTTPD2DQSZ256rrb:
17194 case VCVTTPD2DQSZ256rrbk:
17195 case VCVTTPD2DQSZ256rrbkz:
17196 case VCVTTPD2DQSZ256rrk:
17197 case VCVTTPD2DQSZ256rrkz:
17198 case VCVTTPD2DQSZrm:
17199 case VCVTTPD2DQSZrmb:
17200 case VCVTTPD2DQSZrmbk:
17201 case VCVTTPD2DQSZrmbkz:
17202 case VCVTTPD2DQSZrmk:
17203 case VCVTTPD2DQSZrmkz:
17204 case VCVTTPD2DQSZrr:
17205 case VCVTTPD2DQSZrrb:
17206 case VCVTTPD2DQSZrrbk:
17207 case VCVTTPD2DQSZrrbkz:
17208 case VCVTTPD2DQSZrrk:
17209 case VCVTTPD2DQSZrrkz:
17210 return true;
17211 }
17212 return false;
17213}
17214
17215bool isVPMINSD(unsigned Opcode) {
17216 switch (Opcode) {
17217 case VPMINSDYrm:
17218 case VPMINSDYrr:
17219 case VPMINSDZ128rm:
17220 case VPMINSDZ128rmb:
17221 case VPMINSDZ128rmbk:
17222 case VPMINSDZ128rmbkz:
17223 case VPMINSDZ128rmk:
17224 case VPMINSDZ128rmkz:
17225 case VPMINSDZ128rr:
17226 case VPMINSDZ128rrk:
17227 case VPMINSDZ128rrkz:
17228 case VPMINSDZ256rm:
17229 case VPMINSDZ256rmb:
17230 case VPMINSDZ256rmbk:
17231 case VPMINSDZ256rmbkz:
17232 case VPMINSDZ256rmk:
17233 case VPMINSDZ256rmkz:
17234 case VPMINSDZ256rr:
17235 case VPMINSDZ256rrk:
17236 case VPMINSDZ256rrkz:
17237 case VPMINSDZrm:
17238 case VPMINSDZrmb:
17239 case VPMINSDZrmbk:
17240 case VPMINSDZrmbkz:
17241 case VPMINSDZrmk:
17242 case VPMINSDZrmkz:
17243 case VPMINSDZrr:
17244 case VPMINSDZrrk:
17245 case VPMINSDZrrkz:
17246 case VPMINSDrm:
17247 case VPMINSDrr:
17248 return true;
17249 }
17250 return false;
17251}
17252
17253bool isVHADDPS(unsigned Opcode) {
17254 switch (Opcode) {
17255 case VHADDPSYrm:
17256 case VHADDPSYrr:
17257 case VHADDPSrm:
17258 case VHADDPSrr:
17259 return true;
17260 }
17261 return false;
17262}
17263
17264bool isVMOVNTDQ(unsigned Opcode) {
17265 switch (Opcode) {
17266 case VMOVNTDQYmr:
17267 case VMOVNTDQZ128mr:
17268 case VMOVNTDQZ256mr:
17269 case VMOVNTDQZmr:
17270 case VMOVNTDQmr:
17271 return true;
17272 }
17273 return false;
17274}
17275
17276bool isVFRCZSD(unsigned Opcode) {
17277 switch (Opcode) {
17278 case VFRCZSDrm:
17279 case VFRCZSDrr:
17280 return true;
17281 }
17282 return false;
17283}
17284
17285bool isIBHF(unsigned Opcode) {
17286 return Opcode == IBHF;
17287}
17288
17289bool isVPTESTMW(unsigned Opcode) {
17290 switch (Opcode) {
17291 case VPTESTMWZ128rm:
17292 case VPTESTMWZ128rmk:
17293 case VPTESTMWZ128rr:
17294 case VPTESTMWZ128rrk:
17295 case VPTESTMWZ256rm:
17296 case VPTESTMWZ256rmk:
17297 case VPTESTMWZ256rr:
17298 case VPTESTMWZ256rrk:
17299 case VPTESTMWZrm:
17300 case VPTESTMWZrmk:
17301 case VPTESTMWZrr:
17302 case VPTESTMWZrrk:
17303 return true;
17304 }
17305 return false;
17306}
17307
17308bool isVPMOVZXWD(unsigned Opcode) {
17309 switch (Opcode) {
17310 case VPMOVZXWDYrm:
17311 case VPMOVZXWDYrr:
17312 case VPMOVZXWDZ128rm:
17313 case VPMOVZXWDZ128rmk:
17314 case VPMOVZXWDZ128rmkz:
17315 case VPMOVZXWDZ128rr:
17316 case VPMOVZXWDZ128rrk:
17317 case VPMOVZXWDZ128rrkz:
17318 case VPMOVZXWDZ256rm:
17319 case VPMOVZXWDZ256rmk:
17320 case VPMOVZXWDZ256rmkz:
17321 case VPMOVZXWDZ256rr:
17322 case VPMOVZXWDZ256rrk:
17323 case VPMOVZXWDZ256rrkz:
17324 case VPMOVZXWDZrm:
17325 case VPMOVZXWDZrmk:
17326 case VPMOVZXWDZrmkz:
17327 case VPMOVZXWDZrr:
17328 case VPMOVZXWDZrrk:
17329 case VPMOVZXWDZrrkz:
17330 case VPMOVZXWDrm:
17331 case VPMOVZXWDrr:
17332 return true;
17333 }
17334 return false;
17335}
17336
17337bool isPSADBW(unsigned Opcode) {
17338 switch (Opcode) {
17339 case MMX_PSADBWrm:
17340 case MMX_PSADBWrr:
17341 case PSADBWrm:
17342 case PSADBWrr:
17343 return true;
17344 }
17345 return false;
17346}
17347
17348bool isVCVTSD2SI(unsigned Opcode) {
17349 switch (Opcode) {
17350 case VCVTSD2SI64Zrm_Int:
17351 case VCVTSD2SI64Zrr_Int:
17352 case VCVTSD2SI64Zrrb_Int:
17353 case VCVTSD2SI64rm_Int:
17354 case VCVTSD2SI64rr_Int:
17355 case VCVTSD2SIZrm_Int:
17356 case VCVTSD2SIZrr_Int:
17357 case VCVTSD2SIZrrb_Int:
17358 case VCVTSD2SIrm_Int:
17359 case VCVTSD2SIrr_Int:
17360 return true;
17361 }
17362 return false;
17363}
17364
17365bool isVMAXPH(unsigned Opcode) {
17366 switch (Opcode) {
17367 case VMAXPHZ128rm:
17368 case VMAXPHZ128rmb:
17369 case VMAXPHZ128rmbk:
17370 case VMAXPHZ128rmbkz:
17371 case VMAXPHZ128rmk:
17372 case VMAXPHZ128rmkz:
17373 case VMAXPHZ128rr:
17374 case VMAXPHZ128rrk:
17375 case VMAXPHZ128rrkz:
17376 case VMAXPHZ256rm:
17377 case VMAXPHZ256rmb:
17378 case VMAXPHZ256rmbk:
17379 case VMAXPHZ256rmbkz:
17380 case VMAXPHZ256rmk:
17381 case VMAXPHZ256rmkz:
17382 case VMAXPHZ256rr:
17383 case VMAXPHZ256rrk:
17384 case VMAXPHZ256rrkz:
17385 case VMAXPHZrm:
17386 case VMAXPHZrmb:
17387 case VMAXPHZrmbk:
17388 case VMAXPHZrmbkz:
17389 case VMAXPHZrmk:
17390 case VMAXPHZrmkz:
17391 case VMAXPHZrr:
17392 case VMAXPHZrrb:
17393 case VMAXPHZrrbk:
17394 case VMAXPHZrrbkz:
17395 case VMAXPHZrrk:
17396 case VMAXPHZrrkz:
17397 return true;
17398 }
17399 return false;
17400}
17401
17402bool isLODSB(unsigned Opcode) {
17403 return Opcode == LODSB;
17404}
17405
17406bool isPHMINPOSUW(unsigned Opcode) {
17407 switch (Opcode) {
17408 case PHMINPOSUWrm:
17409 case PHMINPOSUWrr:
17410 return true;
17411 }
17412 return false;
17413}
17414
17415bool isVPROLVD(unsigned Opcode) {
17416 switch (Opcode) {
17417 case VPROLVDZ128rm:
17418 case VPROLVDZ128rmb:
17419 case VPROLVDZ128rmbk:
17420 case VPROLVDZ128rmbkz:
17421 case VPROLVDZ128rmk:
17422 case VPROLVDZ128rmkz:
17423 case VPROLVDZ128rr:
17424 case VPROLVDZ128rrk:
17425 case VPROLVDZ128rrkz:
17426 case VPROLVDZ256rm:
17427 case VPROLVDZ256rmb:
17428 case VPROLVDZ256rmbk:
17429 case VPROLVDZ256rmbkz:
17430 case VPROLVDZ256rmk:
17431 case VPROLVDZ256rmkz:
17432 case VPROLVDZ256rr:
17433 case VPROLVDZ256rrk:
17434 case VPROLVDZ256rrkz:
17435 case VPROLVDZrm:
17436 case VPROLVDZrmb:
17437 case VPROLVDZrmbk:
17438 case VPROLVDZrmbkz:
17439 case VPROLVDZrmk:
17440 case VPROLVDZrmkz:
17441 case VPROLVDZrr:
17442 case VPROLVDZrrk:
17443 case VPROLVDZrrkz:
17444 return true;
17445 }
17446 return false;
17447}
17448
17449bool isWRFSBASE(unsigned Opcode) {
17450 switch (Opcode) {
17451 case WRFSBASE:
17452 case WRFSBASE64:
17453 return true;
17454 }
17455 return false;
17456}
17457
17458bool isVRSQRT14PS(unsigned Opcode) {
17459 switch (Opcode) {
17460 case VRSQRT14PSZ128m:
17461 case VRSQRT14PSZ128mb:
17462 case VRSQRT14PSZ128mbk:
17463 case VRSQRT14PSZ128mbkz:
17464 case VRSQRT14PSZ128mk:
17465 case VRSQRT14PSZ128mkz:
17466 case VRSQRT14PSZ128r:
17467 case VRSQRT14PSZ128rk:
17468 case VRSQRT14PSZ128rkz:
17469 case VRSQRT14PSZ256m:
17470 case VRSQRT14PSZ256mb:
17471 case VRSQRT14PSZ256mbk:
17472 case VRSQRT14PSZ256mbkz:
17473 case VRSQRT14PSZ256mk:
17474 case VRSQRT14PSZ256mkz:
17475 case VRSQRT14PSZ256r:
17476 case VRSQRT14PSZ256rk:
17477 case VRSQRT14PSZ256rkz:
17478 case VRSQRT14PSZm:
17479 case VRSQRT14PSZmb:
17480 case VRSQRT14PSZmbk:
17481 case VRSQRT14PSZmbkz:
17482 case VRSQRT14PSZmk:
17483 case VRSQRT14PSZmkz:
17484 case VRSQRT14PSZr:
17485 case VRSQRT14PSZrk:
17486 case VRSQRT14PSZrkz:
17487 return true;
17488 }
17489 return false;
17490}
17491
17492bool isVPHSUBDQ(unsigned Opcode) {
17493 switch (Opcode) {
17494 case VPHSUBDQrm:
17495 case VPHSUBDQrr:
17496 return true;
17497 }
17498 return false;
17499}
17500
17501bool isIRETD(unsigned Opcode) {
17502 return Opcode == IRET32;
17503}
17504
17505bool isVMOVRSD(unsigned Opcode) {
17506 switch (Opcode) {
17507 case VMOVRSDZ128m:
17508 case VMOVRSDZ128mk:
17509 case VMOVRSDZ128mkz:
17510 case VMOVRSDZ256m:
17511 case VMOVRSDZ256mk:
17512 case VMOVRSDZ256mkz:
17513 case VMOVRSDZm:
17514 case VMOVRSDZmk:
17515 case VMOVRSDZmkz:
17516 return true;
17517 }
17518 return false;
17519}
17520
17521bool isVPMULHRSW(unsigned Opcode) {
17522 switch (Opcode) {
17523 case VPMULHRSWYrm:
17524 case VPMULHRSWYrr:
17525 case VPMULHRSWZ128rm:
17526 case VPMULHRSWZ128rmk:
17527 case VPMULHRSWZ128rmkz:
17528 case VPMULHRSWZ128rr:
17529 case VPMULHRSWZ128rrk:
17530 case VPMULHRSWZ128rrkz:
17531 case VPMULHRSWZ256rm:
17532 case VPMULHRSWZ256rmk:
17533 case VPMULHRSWZ256rmkz:
17534 case VPMULHRSWZ256rr:
17535 case VPMULHRSWZ256rrk:
17536 case VPMULHRSWZ256rrkz:
17537 case VPMULHRSWZrm:
17538 case VPMULHRSWZrmk:
17539 case VPMULHRSWZrmkz:
17540 case VPMULHRSWZrr:
17541 case VPMULHRSWZrrk:
17542 case VPMULHRSWZrrkz:
17543 case VPMULHRSWrm:
17544 case VPMULHRSWrr:
17545 return true;
17546 }
17547 return false;
17548}
17549
17550bool isCVTSI2SS(unsigned Opcode) {
17551 switch (Opcode) {
17552 case CVTSI2SSrm_Int:
17553 case CVTSI2SSrr_Int:
17554 case CVTSI642SSrm_Int:
17555 case CVTSI642SSrr_Int:
17556 return true;
17557 }
17558 return false;
17559}
17560
17561bool isPI2FD(unsigned Opcode) {
17562 switch (Opcode) {
17563 case PI2FDrm:
17564 case PI2FDrr:
17565 return true;
17566 }
17567 return false;
17568}
17569
17570bool isGF2P8AFFINEQB(unsigned Opcode) {
17571 switch (Opcode) {
17572 case GF2P8AFFINEQBrmi:
17573 case GF2P8AFFINEQBrri:
17574 return true;
17575 }
17576 return false;
17577}
17578
17579bool isPAND(unsigned Opcode) {
17580 switch (Opcode) {
17581 case MMX_PANDrm:
17582 case MMX_PANDrr:
17583 case PANDrm:
17584 case PANDrr:
17585 return true;
17586 }
17587 return false;
17588}
17589
17590bool isVFNMSUB231SH(unsigned Opcode) {
17591 switch (Opcode) {
17592 case VFNMSUB231SHZm_Int:
17593 case VFNMSUB231SHZmk_Int:
17594 case VFNMSUB231SHZmkz_Int:
17595 case VFNMSUB231SHZr_Int:
17596 case VFNMSUB231SHZrb_Int:
17597 case VFNMSUB231SHZrbk_Int:
17598 case VFNMSUB231SHZrbkz_Int:
17599 case VFNMSUB231SHZrk_Int:
17600 case VFNMSUB231SHZrkz_Int:
17601 return true;
17602 }
17603 return false;
17604}
17605
17606bool isVMOVHLPS(unsigned Opcode) {
17607 switch (Opcode) {
17608 case VMOVHLPSZrr:
17609 case VMOVHLPSrr:
17610 return true;
17611 }
17612 return false;
17613}
17614
17615bool isKNOTD(unsigned Opcode) {
17616 return Opcode == KNOTDkk;
17617}
17618
17619bool isPEXTRB(unsigned Opcode) {
17620 switch (Opcode) {
17621 case PEXTRBmri:
17622 case PEXTRBrri:
17623 return true;
17624 }
17625 return false;
17626}
17627
17628bool isVCVTPH2BF8(unsigned Opcode) {
17629 switch (Opcode) {
17630 case VCVTPH2BF8Z128rm:
17631 case VCVTPH2BF8Z128rmb:
17632 case VCVTPH2BF8Z128rmbk:
17633 case VCVTPH2BF8Z128rmbkz:
17634 case VCVTPH2BF8Z128rmk:
17635 case VCVTPH2BF8Z128rmkz:
17636 case VCVTPH2BF8Z128rr:
17637 case VCVTPH2BF8Z128rrk:
17638 case VCVTPH2BF8Z128rrkz:
17639 case VCVTPH2BF8Z256rm:
17640 case VCVTPH2BF8Z256rmb:
17641 case VCVTPH2BF8Z256rmbk:
17642 case VCVTPH2BF8Z256rmbkz:
17643 case VCVTPH2BF8Z256rmk:
17644 case VCVTPH2BF8Z256rmkz:
17645 case VCVTPH2BF8Z256rr:
17646 case VCVTPH2BF8Z256rrk:
17647 case VCVTPH2BF8Z256rrkz:
17648 case VCVTPH2BF8Zrm:
17649 case VCVTPH2BF8Zrmb:
17650 case VCVTPH2BF8Zrmbk:
17651 case VCVTPH2BF8Zrmbkz:
17652 case VCVTPH2BF8Zrmk:
17653 case VCVTPH2BF8Zrmkz:
17654 case VCVTPH2BF8Zrr:
17655 case VCVTPH2BF8Zrrk:
17656 case VCVTPH2BF8Zrrkz:
17657 return true;
17658 }
17659 return false;
17660}
17661
17662bool isVMMCALL(unsigned Opcode) {
17663 return Opcode == VMMCALL;
17664}
17665
17666bool isVCVTSH2SS(unsigned Opcode) {
17667 switch (Opcode) {
17668 case VCVTSH2SSZrm_Int:
17669 case VCVTSH2SSZrmk_Int:
17670 case VCVTSH2SSZrmkz_Int:
17671 case VCVTSH2SSZrr_Int:
17672 case VCVTSH2SSZrrb_Int:
17673 case VCVTSH2SSZrrbk_Int:
17674 case VCVTSH2SSZrrbkz_Int:
17675 case VCVTSH2SSZrrk_Int:
17676 case VCVTSH2SSZrrkz_Int:
17677 return true;
17678 }
17679 return false;
17680}
17681
17682bool isVPUNPCKLQDQ(unsigned Opcode) {
17683 switch (Opcode) {
17684 case VPUNPCKLQDQYrm:
17685 case VPUNPCKLQDQYrr:
17686 case VPUNPCKLQDQZ128rm:
17687 case VPUNPCKLQDQZ128rmb:
17688 case VPUNPCKLQDQZ128rmbk:
17689 case VPUNPCKLQDQZ128rmbkz:
17690 case VPUNPCKLQDQZ128rmk:
17691 case VPUNPCKLQDQZ128rmkz:
17692 case VPUNPCKLQDQZ128rr:
17693 case VPUNPCKLQDQZ128rrk:
17694 case VPUNPCKLQDQZ128rrkz:
17695 case VPUNPCKLQDQZ256rm:
17696 case VPUNPCKLQDQZ256rmb:
17697 case VPUNPCKLQDQZ256rmbk:
17698 case VPUNPCKLQDQZ256rmbkz:
17699 case VPUNPCKLQDQZ256rmk:
17700 case VPUNPCKLQDQZ256rmkz:
17701 case VPUNPCKLQDQZ256rr:
17702 case VPUNPCKLQDQZ256rrk:
17703 case VPUNPCKLQDQZ256rrkz:
17704 case VPUNPCKLQDQZrm:
17705 case VPUNPCKLQDQZrmb:
17706 case VPUNPCKLQDQZrmbk:
17707 case VPUNPCKLQDQZrmbkz:
17708 case VPUNPCKLQDQZrmk:
17709 case VPUNPCKLQDQZrmkz:
17710 case VPUNPCKLQDQZrr:
17711 case VPUNPCKLQDQZrrk:
17712 case VPUNPCKLQDQZrrkz:
17713 case VPUNPCKLQDQrm:
17714 case VPUNPCKLQDQrr:
17715 return true;
17716 }
17717 return false;
17718}
17719
17720bool isVPERMIL2PS(unsigned Opcode) {
17721 switch (Opcode) {
17722 case VPERMIL2PSYmr:
17723 case VPERMIL2PSYrm:
17724 case VPERMIL2PSYrr:
17725 case VPERMIL2PSYrr_REV:
17726 case VPERMIL2PSmr:
17727 case VPERMIL2PSrm:
17728 case VPERMIL2PSrr:
17729 case VPERMIL2PSrr_REV:
17730 return true;
17731 }
17732 return false;
17733}
17734
17735bool isVPCMPGTD(unsigned Opcode) {
17736 switch (Opcode) {
17737 case VPCMPGTDYrm:
17738 case VPCMPGTDYrr:
17739 case VPCMPGTDZ128rm:
17740 case VPCMPGTDZ128rmb:
17741 case VPCMPGTDZ128rmbk:
17742 case VPCMPGTDZ128rmk:
17743 case VPCMPGTDZ128rr:
17744 case VPCMPGTDZ128rrk:
17745 case VPCMPGTDZ256rm:
17746 case VPCMPGTDZ256rmb:
17747 case VPCMPGTDZ256rmbk:
17748 case VPCMPGTDZ256rmk:
17749 case VPCMPGTDZ256rr:
17750 case VPCMPGTDZ256rrk:
17751 case VPCMPGTDZrm:
17752 case VPCMPGTDZrmb:
17753 case VPCMPGTDZrmbk:
17754 case VPCMPGTDZrmk:
17755 case VPCMPGTDZrr:
17756 case VPCMPGTDZrrk:
17757 case VPCMPGTDrm:
17758 case VPCMPGTDrr:
17759 return true;
17760 }
17761 return false;
17762}
17763
17764bool isCMPXCHG16B(unsigned Opcode) {
17765 return Opcode == CMPXCHG16B;
17766}
17767
17768bool isTDPHF8PS(unsigned Opcode) {
17769 return Opcode == TDPHF8PS;
17770}
17771
17772bool isVZEROUPPER(unsigned Opcode) {
17773 return Opcode == VZEROUPPER;
17774}
17775
17776bool isMOVAPS(unsigned Opcode) {
17777 switch (Opcode) {
17778 case MOVAPSmr:
17779 case MOVAPSrm:
17780 case MOVAPSrr:
17781 case MOVAPSrr_REV:
17782 return true;
17783 }
17784 return false;
17785}
17786
17787bool isVPCMPW(unsigned Opcode) {
17788 switch (Opcode) {
17789 case VPCMPWZ128rmi:
17790 case VPCMPWZ128rmik:
17791 case VPCMPWZ128rri:
17792 case VPCMPWZ128rrik:
17793 case VPCMPWZ256rmi:
17794 case VPCMPWZ256rmik:
17795 case VPCMPWZ256rri:
17796 case VPCMPWZ256rrik:
17797 case VPCMPWZrmi:
17798 case VPCMPWZrmik:
17799 case VPCMPWZrri:
17800 case VPCMPWZrrik:
17801 return true;
17802 }
17803 return false;
17804}
17805
17806bool isFUCOMPP(unsigned Opcode) {
17807 return Opcode == UCOM_FPPr;
17808}
17809
17810bool isXSETBV(unsigned Opcode) {
17811 return Opcode == XSETBV;
17812}
17813
17814bool isSLWPCB(unsigned Opcode) {
17815 switch (Opcode) {
17816 case SLWPCB:
17817 case SLWPCB64:
17818 return true;
17819 }
17820 return false;
17821}
17822
17823bool isSCASW(unsigned Opcode) {
17824 return Opcode == SCASW;
17825}
17826
17827bool isFCMOVNE(unsigned Opcode) {
17828 return Opcode == CMOVNE_F;
17829}
17830
17831bool isPBNDKB(unsigned Opcode) {
17832 return Opcode == PBNDKB;
17833}
17834
17835bool isVPMULLD(unsigned Opcode) {
17836 switch (Opcode) {
17837 case VPMULLDYrm:
17838 case VPMULLDYrr:
17839 case VPMULLDZ128rm:
17840 case VPMULLDZ128rmb:
17841 case VPMULLDZ128rmbk:
17842 case VPMULLDZ128rmbkz:
17843 case VPMULLDZ128rmk:
17844 case VPMULLDZ128rmkz:
17845 case VPMULLDZ128rr:
17846 case VPMULLDZ128rrk:
17847 case VPMULLDZ128rrkz:
17848 case VPMULLDZ256rm:
17849 case VPMULLDZ256rmb:
17850 case VPMULLDZ256rmbk:
17851 case VPMULLDZ256rmbkz:
17852 case VPMULLDZ256rmk:
17853 case VPMULLDZ256rmkz:
17854 case VPMULLDZ256rr:
17855 case VPMULLDZ256rrk:
17856 case VPMULLDZ256rrkz:
17857 case VPMULLDZrm:
17858 case VPMULLDZrmb:
17859 case VPMULLDZrmbk:
17860 case VPMULLDZrmbkz:
17861 case VPMULLDZrmk:
17862 case VPMULLDZrmkz:
17863 case VPMULLDZrr:
17864 case VPMULLDZrrk:
17865 case VPMULLDZrrkz:
17866 case VPMULLDrm:
17867 case VPMULLDrr:
17868 return true;
17869 }
17870 return false;
17871}
17872
17873bool isVP4DPWSSDS(unsigned Opcode) {
17874 switch (Opcode) {
17875 case VP4DPWSSDSrm:
17876 case VP4DPWSSDSrmk:
17877 case VP4DPWSSDSrmkz:
17878 return true;
17879 }
17880 return false;
17881}
17882
17883bool isVCVT2PH2HF8(unsigned Opcode) {
17884 switch (Opcode) {
17885 case VCVT2PH2HF8Z128rm:
17886 case VCVT2PH2HF8Z128rmb:
17887 case VCVT2PH2HF8Z128rmbk:
17888 case VCVT2PH2HF8Z128rmbkz:
17889 case VCVT2PH2HF8Z128rmk:
17890 case VCVT2PH2HF8Z128rmkz:
17891 case VCVT2PH2HF8Z128rr:
17892 case VCVT2PH2HF8Z128rrk:
17893 case VCVT2PH2HF8Z128rrkz:
17894 case VCVT2PH2HF8Z256rm:
17895 case VCVT2PH2HF8Z256rmb:
17896 case VCVT2PH2HF8Z256rmbk:
17897 case VCVT2PH2HF8Z256rmbkz:
17898 case VCVT2PH2HF8Z256rmk:
17899 case VCVT2PH2HF8Z256rmkz:
17900 case VCVT2PH2HF8Z256rr:
17901 case VCVT2PH2HF8Z256rrk:
17902 case VCVT2PH2HF8Z256rrkz:
17903 case VCVT2PH2HF8Zrm:
17904 case VCVT2PH2HF8Zrmb:
17905 case VCVT2PH2HF8Zrmbk:
17906 case VCVT2PH2HF8Zrmbkz:
17907 case VCVT2PH2HF8Zrmk:
17908 case VCVT2PH2HF8Zrmkz:
17909 case VCVT2PH2HF8Zrr:
17910 case VCVT2PH2HF8Zrrk:
17911 case VCVT2PH2HF8Zrrkz:
17912 return true;
17913 }
17914 return false;
17915}
17916
17917bool isPINSRW(unsigned Opcode) {
17918 switch (Opcode) {
17919 case MMX_PINSRWrmi:
17920 case MMX_PINSRWrri:
17921 case PINSRWrmi:
17922 case PINSRWrri:
17923 return true;
17924 }
17925 return false;
17926}
17927
17928bool isVCVTSI2SH(unsigned Opcode) {
17929 switch (Opcode) {
17930 case VCVTSI2SHZrm_Int:
17931 case VCVTSI2SHZrr_Int:
17932 case VCVTSI2SHZrrb_Int:
17933 case VCVTSI642SHZrm_Int:
17934 case VCVTSI642SHZrr_Int:
17935 case VCVTSI642SHZrrb_Int:
17936 return true;
17937 }
17938 return false;
17939}
17940
17941bool isVINSERTF32X8(unsigned Opcode) {
17942 switch (Opcode) {
17943 case VINSERTF32X8Zrmi:
17944 case VINSERTF32X8Zrmik:
17945 case VINSERTF32X8Zrmikz:
17946 case VINSERTF32X8Zrri:
17947 case VINSERTF32X8Zrrik:
17948 case VINSERTF32X8Zrrikz:
17949 return true;
17950 }
17951 return false;
17952}
17953
17954bool isKSHIFTLB(unsigned Opcode) {
17955 return Opcode == KSHIFTLBki;
17956}
17957
17958bool isSEAMOPS(unsigned Opcode) {
17959 return Opcode == SEAMOPS;
17960}
17961
17962bool isVPMOVSQB(unsigned Opcode) {
17963 switch (Opcode) {
17964 case VPMOVSQBZ128mr:
17965 case VPMOVSQBZ128mrk:
17966 case VPMOVSQBZ128rr:
17967 case VPMOVSQBZ128rrk:
17968 case VPMOVSQBZ128rrkz:
17969 case VPMOVSQBZ256mr:
17970 case VPMOVSQBZ256mrk:
17971 case VPMOVSQBZ256rr:
17972 case VPMOVSQBZ256rrk:
17973 case VPMOVSQBZ256rrkz:
17974 case VPMOVSQBZmr:
17975 case VPMOVSQBZmrk:
17976 case VPMOVSQBZrr:
17977 case VPMOVSQBZrrk:
17978 case VPMOVSQBZrrkz:
17979 return true;
17980 }
17981 return false;
17982}
17983
17984bool isVPMULUDQ(unsigned Opcode) {
17985 switch (Opcode) {
17986 case VPMULUDQYrm:
17987 case VPMULUDQYrr:
17988 case VPMULUDQZ128rm:
17989 case VPMULUDQZ128rmb:
17990 case VPMULUDQZ128rmbk:
17991 case VPMULUDQZ128rmbkz:
17992 case VPMULUDQZ128rmk:
17993 case VPMULUDQZ128rmkz:
17994 case VPMULUDQZ128rr:
17995 case VPMULUDQZ128rrk:
17996 case VPMULUDQZ128rrkz:
17997 case VPMULUDQZ256rm:
17998 case VPMULUDQZ256rmb:
17999 case VPMULUDQZ256rmbk:
18000 case VPMULUDQZ256rmbkz:
18001 case VPMULUDQZ256rmk:
18002 case VPMULUDQZ256rmkz:
18003 case VPMULUDQZ256rr:
18004 case VPMULUDQZ256rrk:
18005 case VPMULUDQZ256rrkz:
18006 case VPMULUDQZrm:
18007 case VPMULUDQZrmb:
18008 case VPMULUDQZrmbk:
18009 case VPMULUDQZrmbkz:
18010 case VPMULUDQZrmk:
18011 case VPMULUDQZrmkz:
18012 case VPMULUDQZrr:
18013 case VPMULUDQZrrk:
18014 case VPMULUDQZrrkz:
18015 case VPMULUDQrm:
18016 case VPMULUDQrr:
18017 return true;
18018 }
18019 return false;
18020}
18021
18022bool isVPTESTMD(unsigned Opcode) {
18023 switch (Opcode) {
18024 case VPTESTMDZ128rm:
18025 case VPTESTMDZ128rmb:
18026 case VPTESTMDZ128rmbk:
18027 case VPTESTMDZ128rmk:
18028 case VPTESTMDZ128rr:
18029 case VPTESTMDZ128rrk:
18030 case VPTESTMDZ256rm:
18031 case VPTESTMDZ256rmb:
18032 case VPTESTMDZ256rmbk:
18033 case VPTESTMDZ256rmk:
18034 case VPTESTMDZ256rr:
18035 case VPTESTMDZ256rrk:
18036 case VPTESTMDZrm:
18037 case VPTESTMDZrmb:
18038 case VPTESTMDZrmbk:
18039 case VPTESTMDZrmk:
18040 case VPTESTMDZrr:
18041 case VPTESTMDZrrk:
18042 return true;
18043 }
18044 return false;
18045}
18046
18047bool isVPHADDDQ(unsigned Opcode) {
18048 switch (Opcode) {
18049 case VPHADDDQrm:
18050 case VPHADDDQrr:
18051 return true;
18052 }
18053 return false;
18054}
18055
18056bool isKUNPCKDQ(unsigned Opcode) {
18057 return Opcode == KUNPCKDQkk;
18058}
18059
18060bool isT1MSKC(unsigned Opcode) {
18061 switch (Opcode) {
18062 case T1MSKC32rm:
18063 case T1MSKC32rr:
18064 case T1MSKC64rm:
18065 case T1MSKC64rr:
18066 return true;
18067 }
18068 return false;
18069}
18070
18071bool isVBLENDPS(unsigned Opcode) {
18072 switch (Opcode) {
18073 case VBLENDPSYrmi:
18074 case VBLENDPSYrri:
18075 case VBLENDPSrmi:
18076 case VBLENDPSrri:
18077 return true;
18078 }
18079 return false;
18080}
18081
18082bool isVPCOMB(unsigned Opcode) {
18083 switch (Opcode) {
18084 case VPCOMBmi:
18085 case VPCOMBri:
18086 return true;
18087 }
18088 return false;
18089}
18090
18091bool isPTWRITE(unsigned Opcode) {
18092 switch (Opcode) {
18093 case PTWRITE64m:
18094 case PTWRITE64r:
18095 case PTWRITEm:
18096 case PTWRITEr:
18097 return true;
18098 }
18099 return false;
18100}
18101
18102bool isVCVTPH2BF8S(unsigned Opcode) {
18103 switch (Opcode) {
18104 case VCVTPH2BF8SZ128rm:
18105 case VCVTPH2BF8SZ128rmb:
18106 case VCVTPH2BF8SZ128rmbk:
18107 case VCVTPH2BF8SZ128rmbkz:
18108 case VCVTPH2BF8SZ128rmk:
18109 case VCVTPH2BF8SZ128rmkz:
18110 case VCVTPH2BF8SZ128rr:
18111 case VCVTPH2BF8SZ128rrk:
18112 case VCVTPH2BF8SZ128rrkz:
18113 case VCVTPH2BF8SZ256rm:
18114 case VCVTPH2BF8SZ256rmb:
18115 case VCVTPH2BF8SZ256rmbk:
18116 case VCVTPH2BF8SZ256rmbkz:
18117 case VCVTPH2BF8SZ256rmk:
18118 case VCVTPH2BF8SZ256rmkz:
18119 case VCVTPH2BF8SZ256rr:
18120 case VCVTPH2BF8SZ256rrk:
18121 case VCVTPH2BF8SZ256rrkz:
18122 case VCVTPH2BF8SZrm:
18123 case VCVTPH2BF8SZrmb:
18124 case VCVTPH2BF8SZrmbk:
18125 case VCVTPH2BF8SZrmbkz:
18126 case VCVTPH2BF8SZrmk:
18127 case VCVTPH2BF8SZrmkz:
18128 case VCVTPH2BF8SZrr:
18129 case VCVTPH2BF8SZrrk:
18130 case VCVTPH2BF8SZrrkz:
18131 return true;
18132 }
18133 return false;
18134}
18135
18136bool isCVTPS2PI(unsigned Opcode) {
18137 switch (Opcode) {
18138 case MMX_CVTPS2PIrm:
18139 case MMX_CVTPS2PIrr:
18140 return true;
18141 }
18142 return false;
18143}
18144
18145bool isVPROTD(unsigned Opcode) {
18146 switch (Opcode) {
18147 case VPROTDmi:
18148 case VPROTDmr:
18149 case VPROTDri:
18150 case VPROTDrm:
18151 case VPROTDrr:
18152 case VPROTDrr_REV:
18153 return true;
18154 }
18155 return false;
18156}
18157
18158bool isCALL(unsigned Opcode) {
18159 switch (Opcode) {
18160 case CALL16m:
18161 case CALL16r:
18162 case CALL32m:
18163 case CALL32r:
18164 case CALL64m:
18165 case CALL64pcrel32:
18166 case CALL64r:
18167 case CALLpcrel16:
18168 case CALLpcrel32:
18169 case FARCALL32m:
18170 return true;
18171 }
18172 return false;
18173}
18174
18175bool isTILELOADDRST1(unsigned Opcode) {
18176 switch (Opcode) {
18177 case TILELOADDRST1:
18178 case TILELOADDRST1_EVEX:
18179 return true;
18180 }
18181 return false;
18182}
18183
18184bool isVPERMPS(unsigned Opcode) {
18185 switch (Opcode) {
18186 case VPERMPSYrm:
18187 case VPERMPSYrr:
18188 case VPERMPSZ256rm:
18189 case VPERMPSZ256rmb:
18190 case VPERMPSZ256rmbk:
18191 case VPERMPSZ256rmbkz:
18192 case VPERMPSZ256rmk:
18193 case VPERMPSZ256rmkz:
18194 case VPERMPSZ256rr:
18195 case VPERMPSZ256rrk:
18196 case VPERMPSZ256rrkz:
18197 case VPERMPSZrm:
18198 case VPERMPSZrmb:
18199 case VPERMPSZrmbk:
18200 case VPERMPSZrmbkz:
18201 case VPERMPSZrmk:
18202 case VPERMPSZrmkz:
18203 case VPERMPSZrr:
18204 case VPERMPSZrrk:
18205 case VPERMPSZrrkz:
18206 return true;
18207 }
18208 return false;
18209}
18210
18211bool isVPSHUFBITQMB(unsigned Opcode) {
18212 switch (Opcode) {
18213 case VPSHUFBITQMBZ128rm:
18214 case VPSHUFBITQMBZ128rmk:
18215 case VPSHUFBITQMBZ128rr:
18216 case VPSHUFBITQMBZ128rrk:
18217 case VPSHUFBITQMBZ256rm:
18218 case VPSHUFBITQMBZ256rmk:
18219 case VPSHUFBITQMBZ256rr:
18220 case VPSHUFBITQMBZ256rrk:
18221 case VPSHUFBITQMBZrm:
18222 case VPSHUFBITQMBZrmk:
18223 case VPSHUFBITQMBZrr:
18224 case VPSHUFBITQMBZrrk:
18225 return true;
18226 }
18227 return false;
18228}
18229
18230bool isVMOVSLDUP(unsigned Opcode) {
18231 switch (Opcode) {
18232 case VMOVSLDUPYrm:
18233 case VMOVSLDUPYrr:
18234 case VMOVSLDUPZ128rm:
18235 case VMOVSLDUPZ128rmk:
18236 case VMOVSLDUPZ128rmkz:
18237 case VMOVSLDUPZ128rr:
18238 case VMOVSLDUPZ128rrk:
18239 case VMOVSLDUPZ128rrkz:
18240 case VMOVSLDUPZ256rm:
18241 case VMOVSLDUPZ256rmk:
18242 case VMOVSLDUPZ256rmkz:
18243 case VMOVSLDUPZ256rr:
18244 case VMOVSLDUPZ256rrk:
18245 case VMOVSLDUPZ256rrkz:
18246 case VMOVSLDUPZrm:
18247 case VMOVSLDUPZrmk:
18248 case VMOVSLDUPZrmkz:
18249 case VMOVSLDUPZrr:
18250 case VMOVSLDUPZrrk:
18251 case VMOVSLDUPZrrkz:
18252 case VMOVSLDUPrm:
18253 case VMOVSLDUPrr:
18254 return true;
18255 }
18256 return false;
18257}
18258
18259bool isINVLPGA(unsigned Opcode) {
18260 switch (Opcode) {
18261 case INVLPGA32:
18262 case INVLPGA64:
18263 return true;
18264 }
18265 return false;
18266}
18267
18268bool isVCVTPH2QQ(unsigned Opcode) {
18269 switch (Opcode) {
18270 case VCVTPH2QQZ128rm:
18271 case VCVTPH2QQZ128rmb:
18272 case VCVTPH2QQZ128rmbk:
18273 case VCVTPH2QQZ128rmbkz:
18274 case VCVTPH2QQZ128rmk:
18275 case VCVTPH2QQZ128rmkz:
18276 case VCVTPH2QQZ128rr:
18277 case VCVTPH2QQZ128rrk:
18278 case VCVTPH2QQZ128rrkz:
18279 case VCVTPH2QQZ256rm:
18280 case VCVTPH2QQZ256rmb:
18281 case VCVTPH2QQZ256rmbk:
18282 case VCVTPH2QQZ256rmbkz:
18283 case VCVTPH2QQZ256rmk:
18284 case VCVTPH2QQZ256rmkz:
18285 case VCVTPH2QQZ256rr:
18286 case VCVTPH2QQZ256rrk:
18287 case VCVTPH2QQZ256rrkz:
18288 case VCVTPH2QQZrm:
18289 case VCVTPH2QQZrmb:
18290 case VCVTPH2QQZrmbk:
18291 case VCVTPH2QQZrmbkz:
18292 case VCVTPH2QQZrmk:
18293 case VCVTPH2QQZrmkz:
18294 case VCVTPH2QQZrr:
18295 case VCVTPH2QQZrrb:
18296 case VCVTPH2QQZrrbk:
18297 case VCVTPH2QQZrrbkz:
18298 case VCVTPH2QQZrrk:
18299 case VCVTPH2QQZrrkz:
18300 return true;
18301 }
18302 return false;
18303}
18304
18305bool isADD(unsigned Opcode) {
18306 switch (Opcode) {
18307 case ADD16i16:
18308 case ADD16mi:
18309 case ADD16mi8:
18310 case ADD16mi8_EVEX:
18311 case ADD16mi8_ND:
18312 case ADD16mi8_NF:
18313 case ADD16mi8_NF_ND:
18314 case ADD16mi_EVEX:
18315 case ADD16mi_ND:
18316 case ADD16mi_NF:
18317 case ADD16mi_NF_ND:
18318 case ADD16mr:
18319 case ADD16mr_EVEX:
18320 case ADD16mr_ND:
18321 case ADD16mr_NF:
18322 case ADD16mr_NF_ND:
18323 case ADD16ri:
18324 case ADD16ri8:
18325 case ADD16ri8_EVEX:
18326 case ADD16ri8_ND:
18327 case ADD16ri8_NF:
18328 case ADD16ri8_NF_ND:
18329 case ADD16ri_EVEX:
18330 case ADD16ri_ND:
18331 case ADD16ri_NF:
18332 case ADD16ri_NF_ND:
18333 case ADD16rm:
18334 case ADD16rm_EVEX:
18335 case ADD16rm_ND:
18336 case ADD16rm_NF:
18337 case ADD16rm_NF_ND:
18338 case ADD16rr:
18339 case ADD16rr_EVEX:
18340 case ADD16rr_EVEX_REV:
18341 case ADD16rr_ND:
18342 case ADD16rr_ND_REV:
18343 case ADD16rr_NF:
18344 case ADD16rr_NF_ND:
18345 case ADD16rr_NF_ND_REV:
18346 case ADD16rr_NF_REV:
18347 case ADD16rr_REV:
18348 case ADD32i32:
18349 case ADD32mi:
18350 case ADD32mi8:
18351 case ADD32mi8_EVEX:
18352 case ADD32mi8_ND:
18353 case ADD32mi8_NF:
18354 case ADD32mi8_NF_ND:
18355 case ADD32mi_EVEX:
18356 case ADD32mi_ND:
18357 case ADD32mi_NF:
18358 case ADD32mi_NF_ND:
18359 case ADD32mr:
18360 case ADD32mr_EVEX:
18361 case ADD32mr_ND:
18362 case ADD32mr_NF:
18363 case ADD32mr_NF_ND:
18364 case ADD32ri:
18365 case ADD32ri8:
18366 case ADD32ri8_EVEX:
18367 case ADD32ri8_ND:
18368 case ADD32ri8_NF:
18369 case ADD32ri8_NF_ND:
18370 case ADD32ri_EVEX:
18371 case ADD32ri_ND:
18372 case ADD32ri_NF:
18373 case ADD32ri_NF_ND:
18374 case ADD32rm:
18375 case ADD32rm_EVEX:
18376 case ADD32rm_ND:
18377 case ADD32rm_NF:
18378 case ADD32rm_NF_ND:
18379 case ADD32rr:
18380 case ADD32rr_EVEX:
18381 case ADD32rr_EVEX_REV:
18382 case ADD32rr_ND:
18383 case ADD32rr_ND_REV:
18384 case ADD32rr_NF:
18385 case ADD32rr_NF_ND:
18386 case ADD32rr_NF_ND_REV:
18387 case ADD32rr_NF_REV:
18388 case ADD32rr_REV:
18389 case ADD64i32:
18390 case ADD64mi32:
18391 case ADD64mi32_EVEX:
18392 case ADD64mi32_ND:
18393 case ADD64mi32_NF:
18394 case ADD64mi32_NF_ND:
18395 case ADD64mi8:
18396 case ADD64mi8_EVEX:
18397 case ADD64mi8_ND:
18398 case ADD64mi8_NF:
18399 case ADD64mi8_NF_ND:
18400 case ADD64mr:
18401 case ADD64mr_EVEX:
18402 case ADD64mr_ND:
18403 case ADD64mr_NF:
18404 case ADD64mr_NF_ND:
18405 case ADD64ri32:
18406 case ADD64ri32_EVEX:
18407 case ADD64ri32_ND:
18408 case ADD64ri32_NF:
18409 case ADD64ri32_NF_ND:
18410 case ADD64ri8:
18411 case ADD64ri8_EVEX:
18412 case ADD64ri8_ND:
18413 case ADD64ri8_NF:
18414 case ADD64ri8_NF_ND:
18415 case ADD64rm:
18416 case ADD64rm_EVEX:
18417 case ADD64rm_ND:
18418 case ADD64rm_NF:
18419 case ADD64rm_NF_ND:
18420 case ADD64rr:
18421 case ADD64rr_EVEX:
18422 case ADD64rr_EVEX_REV:
18423 case ADD64rr_ND:
18424 case ADD64rr_ND_REV:
18425 case ADD64rr_NF:
18426 case ADD64rr_NF_ND:
18427 case ADD64rr_NF_ND_REV:
18428 case ADD64rr_NF_REV:
18429 case ADD64rr_REV:
18430 case ADD8i8:
18431 case ADD8mi:
18432 case ADD8mi8:
18433 case ADD8mi_EVEX:
18434 case ADD8mi_ND:
18435 case ADD8mi_NF:
18436 case ADD8mi_NF_ND:
18437 case ADD8mr:
18438 case ADD8mr_EVEX:
18439 case ADD8mr_ND:
18440 case ADD8mr_NF:
18441 case ADD8mr_NF_ND:
18442 case ADD8ri:
18443 case ADD8ri8:
18444 case ADD8ri_EVEX:
18445 case ADD8ri_ND:
18446 case ADD8ri_NF:
18447 case ADD8ri_NF_ND:
18448 case ADD8rm:
18449 case ADD8rm_EVEX:
18450 case ADD8rm_ND:
18451 case ADD8rm_NF:
18452 case ADD8rm_NF_ND:
18453 case ADD8rr:
18454 case ADD8rr_EVEX:
18455 case ADD8rr_EVEX_REV:
18456 case ADD8rr_ND:
18457 case ADD8rr_ND_REV:
18458 case ADD8rr_NF:
18459 case ADD8rr_NF_ND:
18460 case ADD8rr_NF_ND_REV:
18461 case ADD8rr_NF_REV:
18462 case ADD8rr_REV:
18463 return true;
18464 }
18465 return false;
18466}
18467
18468bool isPSUBSW(unsigned Opcode) {
18469 switch (Opcode) {
18470 case MMX_PSUBSWrm:
18471 case MMX_PSUBSWrr:
18472 case PSUBSWrm:
18473 case PSUBSWrr:
18474 return true;
18475 }
18476 return false;
18477}
18478
18479bool isSIDTW(unsigned Opcode) {
18480 return Opcode == SIDT16m;
18481}
18482
18483bool isVEXTRACTF64X2(unsigned Opcode) {
18484 switch (Opcode) {
18485 case VEXTRACTF64X2Z256mri:
18486 case VEXTRACTF64X2Z256mrik:
18487 case VEXTRACTF64X2Z256rri:
18488 case VEXTRACTF64X2Z256rrik:
18489 case VEXTRACTF64X2Z256rrikz:
18490 case VEXTRACTF64X2Zmri:
18491 case VEXTRACTF64X2Zmrik:
18492 case VEXTRACTF64X2Zrri:
18493 case VEXTRACTF64X2Zrrik:
18494 case VEXTRACTF64X2Zrrikz:
18495 return true;
18496 }
18497 return false;
18498}
18499
18500bool isVFNMADD231PH(unsigned Opcode) {
18501 switch (Opcode) {
18502 case VFNMADD231PHZ128m:
18503 case VFNMADD231PHZ128mb:
18504 case VFNMADD231PHZ128mbk:
18505 case VFNMADD231PHZ128mbkz:
18506 case VFNMADD231PHZ128mk:
18507 case VFNMADD231PHZ128mkz:
18508 case VFNMADD231PHZ128r:
18509 case VFNMADD231PHZ128rk:
18510 case VFNMADD231PHZ128rkz:
18511 case VFNMADD231PHZ256m:
18512 case VFNMADD231PHZ256mb:
18513 case VFNMADD231PHZ256mbk:
18514 case VFNMADD231PHZ256mbkz:
18515 case VFNMADD231PHZ256mk:
18516 case VFNMADD231PHZ256mkz:
18517 case VFNMADD231PHZ256r:
18518 case VFNMADD231PHZ256rk:
18519 case VFNMADD231PHZ256rkz:
18520 case VFNMADD231PHZm:
18521 case VFNMADD231PHZmb:
18522 case VFNMADD231PHZmbk:
18523 case VFNMADD231PHZmbkz:
18524 case VFNMADD231PHZmk:
18525 case VFNMADD231PHZmkz:
18526 case VFNMADD231PHZr:
18527 case VFNMADD231PHZrb:
18528 case VFNMADD231PHZrbk:
18529 case VFNMADD231PHZrbkz:
18530 case VFNMADD231PHZrk:
18531 case VFNMADD231PHZrkz:
18532 return true;
18533 }
18534 return false;
18535}
18536
18537bool isFCOMI(unsigned Opcode) {
18538 return Opcode == COM_FIr;
18539}
18540
18541bool isRSM(unsigned Opcode) {
18542 return Opcode == RSM;
18543}
18544
18545bool isVPCOMUD(unsigned Opcode) {
18546 switch (Opcode) {
18547 case VPCOMUDmi:
18548 case VPCOMUDri:
18549 return true;
18550 }
18551 return false;
18552}
18553
18554bool isVPMOVZXBQ(unsigned Opcode) {
18555 switch (Opcode) {
18556 case VPMOVZXBQYrm:
18557 case VPMOVZXBQYrr:
18558 case VPMOVZXBQZ128rm:
18559 case VPMOVZXBQZ128rmk:
18560 case VPMOVZXBQZ128rmkz:
18561 case VPMOVZXBQZ128rr:
18562 case VPMOVZXBQZ128rrk:
18563 case VPMOVZXBQZ128rrkz:
18564 case VPMOVZXBQZ256rm:
18565 case VPMOVZXBQZ256rmk:
18566 case VPMOVZXBQZ256rmkz:
18567 case VPMOVZXBQZ256rr:
18568 case VPMOVZXBQZ256rrk:
18569 case VPMOVZXBQZ256rrkz:
18570 case VPMOVZXBQZrm:
18571 case VPMOVZXBQZrmk:
18572 case VPMOVZXBQZrmkz:
18573 case VPMOVZXBQZrr:
18574 case VPMOVZXBQZrrk:
18575 case VPMOVZXBQZrrkz:
18576 case VPMOVZXBQrm:
18577 case VPMOVZXBQrr:
18578 return true;
18579 }
18580 return false;
18581}
18582
18583bool isUWRMSR(unsigned Opcode) {
18584 switch (Opcode) {
18585 case UWRMSRir:
18586 case UWRMSRir_EVEX:
18587 case UWRMSRrr:
18588 case UWRMSRrr_EVEX:
18589 return true;
18590 }
18591 return false;
18592}
18593
18594bool isLGS(unsigned Opcode) {
18595 switch (Opcode) {
18596 case LGS16rm:
18597 case LGS32rm:
18598 case LGS64rm:
18599 return true;
18600 }
18601 return false;
18602}
18603
18604bool isVMOVNTPD(unsigned Opcode) {
18605 switch (Opcode) {
18606 case VMOVNTPDYmr:
18607 case VMOVNTPDZ128mr:
18608 case VMOVNTPDZ256mr:
18609 case VMOVNTPDZmr:
18610 case VMOVNTPDmr:
18611 return true;
18612 }
18613 return false;
18614}
18615
18616bool isPCMPESTRMQ(unsigned Opcode) {
18617 switch (Opcode) {
18618 case PCMPESTRMQrmi:
18619 case PCMPESTRMQrri:
18620 return true;
18621 }
18622 return false;
18623}
18624
18625bool isRDPRU(unsigned Opcode) {
18626 return Opcode == RDPRU;
18627}
18628
18629bool isVPUNPCKHBW(unsigned Opcode) {
18630 switch (Opcode) {
18631 case VPUNPCKHBWYrm:
18632 case VPUNPCKHBWYrr:
18633 case VPUNPCKHBWZ128rm:
18634 case VPUNPCKHBWZ128rmk:
18635 case VPUNPCKHBWZ128rmkz:
18636 case VPUNPCKHBWZ128rr:
18637 case VPUNPCKHBWZ128rrk:
18638 case VPUNPCKHBWZ128rrkz:
18639 case VPUNPCKHBWZ256rm:
18640 case VPUNPCKHBWZ256rmk:
18641 case VPUNPCKHBWZ256rmkz:
18642 case VPUNPCKHBWZ256rr:
18643 case VPUNPCKHBWZ256rrk:
18644 case VPUNPCKHBWZ256rrkz:
18645 case VPUNPCKHBWZrm:
18646 case VPUNPCKHBWZrmk:
18647 case VPUNPCKHBWZrmkz:
18648 case VPUNPCKHBWZrr:
18649 case VPUNPCKHBWZrrk:
18650 case VPUNPCKHBWZrrkz:
18651 case VPUNPCKHBWrm:
18652 case VPUNPCKHBWrr:
18653 return true;
18654 }
18655 return false;
18656}
18657
18658bool isVUCOMXSD(unsigned Opcode) {
18659 switch (Opcode) {
18660 case VUCOMXSDZrm_Int:
18661 case VUCOMXSDZrr_Int:
18662 case VUCOMXSDZrrb_Int:
18663 return true;
18664 }
18665 return false;
18666}
18667
18668bool isANDN(unsigned Opcode) {
18669 switch (Opcode) {
18670 case ANDN32rm:
18671 case ANDN32rm_EVEX:
18672 case ANDN32rm_NF:
18673 case ANDN32rr:
18674 case ANDN32rr_EVEX:
18675 case ANDN32rr_NF:
18676 case ANDN64rm:
18677 case ANDN64rm_EVEX:
18678 case ANDN64rm_NF:
18679 case ANDN64rr:
18680 case ANDN64rr_EVEX:
18681 case ANDN64rr_NF:
18682 return true;
18683 }
18684 return false;
18685}
18686
18687bool isVCVTTPH2UW(unsigned Opcode) {
18688 switch (Opcode) {
18689 case VCVTTPH2UWZ128rm:
18690 case VCVTTPH2UWZ128rmb:
18691 case VCVTTPH2UWZ128rmbk:
18692 case VCVTTPH2UWZ128rmbkz:
18693 case VCVTTPH2UWZ128rmk:
18694 case VCVTTPH2UWZ128rmkz:
18695 case VCVTTPH2UWZ128rr:
18696 case VCVTTPH2UWZ128rrk:
18697 case VCVTTPH2UWZ128rrkz:
18698 case VCVTTPH2UWZ256rm:
18699 case VCVTTPH2UWZ256rmb:
18700 case VCVTTPH2UWZ256rmbk:
18701 case VCVTTPH2UWZ256rmbkz:
18702 case VCVTTPH2UWZ256rmk:
18703 case VCVTTPH2UWZ256rmkz:
18704 case VCVTTPH2UWZ256rr:
18705 case VCVTTPH2UWZ256rrk:
18706 case VCVTTPH2UWZ256rrkz:
18707 case VCVTTPH2UWZrm:
18708 case VCVTTPH2UWZrmb:
18709 case VCVTTPH2UWZrmbk:
18710 case VCVTTPH2UWZrmbkz:
18711 case VCVTTPH2UWZrmk:
18712 case VCVTTPH2UWZrmkz:
18713 case VCVTTPH2UWZrr:
18714 case VCVTTPH2UWZrrb:
18715 case VCVTTPH2UWZrrbk:
18716 case VCVTTPH2UWZrrbkz:
18717 case VCVTTPH2UWZrrk:
18718 case VCVTTPH2UWZrrkz:
18719 return true;
18720 }
18721 return false;
18722}
18723
18724bool isVMFUNC(unsigned Opcode) {
18725 return Opcode == VMFUNC;
18726}
18727
18728bool isFIMUL(unsigned Opcode) {
18729 switch (Opcode) {
18730 case MUL_FI16m:
18731 case MUL_FI32m:
18732 return true;
18733 }
18734 return false;
18735}
18736
18737bool isBLCFILL(unsigned Opcode) {
18738 switch (Opcode) {
18739 case BLCFILL32rm:
18740 case BLCFILL32rr:
18741 case BLCFILL64rm:
18742 case BLCFILL64rr:
18743 return true;
18744 }
18745 return false;
18746}
18747
18748bool isVGATHERPF0DPS(unsigned Opcode) {
18749 return Opcode == VGATHERPF0DPSm;
18750}
18751
18752bool isVFMSUBADD231PS(unsigned Opcode) {
18753 switch (Opcode) {
18754 case VFMSUBADD231PSYm:
18755 case VFMSUBADD231PSYr:
18756 case VFMSUBADD231PSZ128m:
18757 case VFMSUBADD231PSZ128mb:
18758 case VFMSUBADD231PSZ128mbk:
18759 case VFMSUBADD231PSZ128mbkz:
18760 case VFMSUBADD231PSZ128mk:
18761 case VFMSUBADD231PSZ128mkz:
18762 case VFMSUBADD231PSZ128r:
18763 case VFMSUBADD231PSZ128rk:
18764 case VFMSUBADD231PSZ128rkz:
18765 case VFMSUBADD231PSZ256m:
18766 case VFMSUBADD231PSZ256mb:
18767 case VFMSUBADD231PSZ256mbk:
18768 case VFMSUBADD231PSZ256mbkz:
18769 case VFMSUBADD231PSZ256mk:
18770 case VFMSUBADD231PSZ256mkz:
18771 case VFMSUBADD231PSZ256r:
18772 case VFMSUBADD231PSZ256rk:
18773 case VFMSUBADD231PSZ256rkz:
18774 case VFMSUBADD231PSZm:
18775 case VFMSUBADD231PSZmb:
18776 case VFMSUBADD231PSZmbk:
18777 case VFMSUBADD231PSZmbkz:
18778 case VFMSUBADD231PSZmk:
18779 case VFMSUBADD231PSZmkz:
18780 case VFMSUBADD231PSZr:
18781 case VFMSUBADD231PSZrb:
18782 case VFMSUBADD231PSZrbk:
18783 case VFMSUBADD231PSZrbkz:
18784 case VFMSUBADD231PSZrk:
18785 case VFMSUBADD231PSZrkz:
18786 case VFMSUBADD231PSm:
18787 case VFMSUBADD231PSr:
18788 return true;
18789 }
18790 return false;
18791}
18792
18793bool isVREDUCESD(unsigned Opcode) {
18794 switch (Opcode) {
18795 case VREDUCESDZrmi:
18796 case VREDUCESDZrmik:
18797 case VREDUCESDZrmikz:
18798 case VREDUCESDZrri:
18799 case VREDUCESDZrrib:
18800 case VREDUCESDZrribk:
18801 case VREDUCESDZrribkz:
18802 case VREDUCESDZrrik:
18803 case VREDUCESDZrrikz:
18804 return true;
18805 }
18806 return false;
18807}
18808
18809bool isVCOMXSH(unsigned Opcode) {
18810 switch (Opcode) {
18811 case VCOMXSHZrm_Int:
18812 case VCOMXSHZrr_Int:
18813 case VCOMXSHZrrb_Int:
18814 return true;
18815 }
18816 return false;
18817}
18818
18819bool isVXORPS(unsigned Opcode) {
18820 switch (Opcode) {
18821 case VXORPSYrm:
18822 case VXORPSYrr:
18823 case VXORPSZ128rm:
18824 case VXORPSZ128rmb:
18825 case VXORPSZ128rmbk:
18826 case VXORPSZ128rmbkz:
18827 case VXORPSZ128rmk:
18828 case VXORPSZ128rmkz:
18829 case VXORPSZ128rr:
18830 case VXORPSZ128rrk:
18831 case VXORPSZ128rrkz:
18832 case VXORPSZ256rm:
18833 case VXORPSZ256rmb:
18834 case VXORPSZ256rmbk:
18835 case VXORPSZ256rmbkz:
18836 case VXORPSZ256rmk:
18837 case VXORPSZ256rmkz:
18838 case VXORPSZ256rr:
18839 case VXORPSZ256rrk:
18840 case VXORPSZ256rrkz:
18841 case VXORPSZrm:
18842 case VXORPSZrmb:
18843 case VXORPSZrmbk:
18844 case VXORPSZrmbkz:
18845 case VXORPSZrmk:
18846 case VXORPSZrmkz:
18847 case VXORPSZrr:
18848 case VXORPSZrrk:
18849 case VXORPSZrrkz:
18850 case VXORPSrm:
18851 case VXORPSrr:
18852 return true;
18853 }
18854 return false;
18855}
18856
18857bool isPSWAPD(unsigned Opcode) {
18858 switch (Opcode) {
18859 case PSWAPDrm:
18860 case PSWAPDrr:
18861 return true;
18862 }
18863 return false;
18864}
18865
18866bool isPMAXSD(unsigned Opcode) {
18867 switch (Opcode) {
18868 case PMAXSDrm:
18869 case PMAXSDrr:
18870 return true;
18871 }
18872 return false;
18873}
18874
18875bool isVCMPSS(unsigned Opcode) {
18876 switch (Opcode) {
18877 case VCMPSSZrmi_Int:
18878 case VCMPSSZrmik_Int:
18879 case VCMPSSZrri_Int:
18880 case VCMPSSZrrib_Int:
18881 case VCMPSSZrribk_Int:
18882 case VCMPSSZrrik_Int:
18883 case VCMPSSrmi_Int:
18884 case VCMPSSrri_Int:
18885 return true;
18886 }
18887 return false;
18888}
18889
18890bool isEXTRACTPS(unsigned Opcode) {
18891 switch (Opcode) {
18892 case EXTRACTPSmri:
18893 case EXTRACTPSrri:
18894 return true;
18895 }
18896 return false;
18897}
18898
18899bool isVPMOVZXBD(unsigned Opcode) {
18900 switch (Opcode) {
18901 case VPMOVZXBDYrm:
18902 case VPMOVZXBDYrr:
18903 case VPMOVZXBDZ128rm:
18904 case VPMOVZXBDZ128rmk:
18905 case VPMOVZXBDZ128rmkz:
18906 case VPMOVZXBDZ128rr:
18907 case VPMOVZXBDZ128rrk:
18908 case VPMOVZXBDZ128rrkz:
18909 case VPMOVZXBDZ256rm:
18910 case VPMOVZXBDZ256rmk:
18911 case VPMOVZXBDZ256rmkz:
18912 case VPMOVZXBDZ256rr:
18913 case VPMOVZXBDZ256rrk:
18914 case VPMOVZXBDZ256rrkz:
18915 case VPMOVZXBDZrm:
18916 case VPMOVZXBDZrmk:
18917 case VPMOVZXBDZrmkz:
18918 case VPMOVZXBDZrr:
18919 case VPMOVZXBDZrrk:
18920 case VPMOVZXBDZrrkz:
18921 case VPMOVZXBDrm:
18922 case VPMOVZXBDrr:
18923 return true;
18924 }
18925 return false;
18926}
18927
18928bool isOUTSW(unsigned Opcode) {
18929 return Opcode == OUTSW;
18930}
18931
18932bool isKORTESTB(unsigned Opcode) {
18933 return Opcode == KORTESTBkk;
18934}
18935
18936bool isVREDUCEPS(unsigned Opcode) {
18937 switch (Opcode) {
18938 case VREDUCEPSZ128rmbi:
18939 case VREDUCEPSZ128rmbik:
18940 case VREDUCEPSZ128rmbikz:
18941 case VREDUCEPSZ128rmi:
18942 case VREDUCEPSZ128rmik:
18943 case VREDUCEPSZ128rmikz:
18944 case VREDUCEPSZ128rri:
18945 case VREDUCEPSZ128rrik:
18946 case VREDUCEPSZ128rrikz:
18947 case VREDUCEPSZ256rmbi:
18948 case VREDUCEPSZ256rmbik:
18949 case VREDUCEPSZ256rmbikz:
18950 case VREDUCEPSZ256rmi:
18951 case VREDUCEPSZ256rmik:
18952 case VREDUCEPSZ256rmikz:
18953 case VREDUCEPSZ256rri:
18954 case VREDUCEPSZ256rrik:
18955 case VREDUCEPSZ256rrikz:
18956 case VREDUCEPSZrmbi:
18957 case VREDUCEPSZrmbik:
18958 case VREDUCEPSZrmbikz:
18959 case VREDUCEPSZrmi:
18960 case VREDUCEPSZrmik:
18961 case VREDUCEPSZrmikz:
18962 case VREDUCEPSZrri:
18963 case VREDUCEPSZrrib:
18964 case VREDUCEPSZrribk:
18965 case VREDUCEPSZrribkz:
18966 case VREDUCEPSZrrik:
18967 case VREDUCEPSZrrikz:
18968 return true;
18969 }
18970 return false;
18971}
18972
18973bool isPEXTRW(unsigned Opcode) {
18974 switch (Opcode) {
18975 case MMX_PEXTRWrri:
18976 case PEXTRWmri:
18977 case PEXTRWrri:
18978 case PEXTRWrri_REV:
18979 return true;
18980 }
18981 return false;
18982}
18983
18984bool isFNINIT(unsigned Opcode) {
18985 return Opcode == FNINIT;
18986}
18987
18988bool isVCVTPH2IBS(unsigned Opcode) {
18989 switch (Opcode) {
18990 case VCVTPH2IBSZ128rm:
18991 case VCVTPH2IBSZ128rmb:
18992 case VCVTPH2IBSZ128rmbk:
18993 case VCVTPH2IBSZ128rmbkz:
18994 case VCVTPH2IBSZ128rmk:
18995 case VCVTPH2IBSZ128rmkz:
18996 case VCVTPH2IBSZ128rr:
18997 case VCVTPH2IBSZ128rrk:
18998 case VCVTPH2IBSZ128rrkz:
18999 case VCVTPH2IBSZ256rm:
19000 case VCVTPH2IBSZ256rmb:
19001 case VCVTPH2IBSZ256rmbk:
19002 case VCVTPH2IBSZ256rmbkz:
19003 case VCVTPH2IBSZ256rmk:
19004 case VCVTPH2IBSZ256rmkz:
19005 case VCVTPH2IBSZ256rr:
19006 case VCVTPH2IBSZ256rrk:
19007 case VCVTPH2IBSZ256rrkz:
19008 case VCVTPH2IBSZrm:
19009 case VCVTPH2IBSZrmb:
19010 case VCVTPH2IBSZrmbk:
19011 case VCVTPH2IBSZrmbkz:
19012 case VCVTPH2IBSZrmk:
19013 case VCVTPH2IBSZrmkz:
19014 case VCVTPH2IBSZrr:
19015 case VCVTPH2IBSZrrb:
19016 case VCVTPH2IBSZrrbk:
19017 case VCVTPH2IBSZrrbkz:
19018 case VCVTPH2IBSZrrk:
19019 case VCVTPH2IBSZrrkz:
19020 return true;
19021 }
19022 return false;
19023}
19024
19025bool isROL(unsigned Opcode) {
19026 switch (Opcode) {
19027 case ROL16m1:
19028 case ROL16m1_EVEX:
19029 case ROL16m1_ND:
19030 case ROL16m1_NF:
19031 case ROL16m1_NF_ND:
19032 case ROL16mCL:
19033 case ROL16mCL_EVEX:
19034 case ROL16mCL_ND:
19035 case ROL16mCL_NF:
19036 case ROL16mCL_NF_ND:
19037 case ROL16mi:
19038 case ROL16mi_EVEX:
19039 case ROL16mi_ND:
19040 case ROL16mi_NF:
19041 case ROL16mi_NF_ND:
19042 case ROL16r1:
19043 case ROL16r1_EVEX:
19044 case ROL16r1_ND:
19045 case ROL16r1_NF:
19046 case ROL16r1_NF_ND:
19047 case ROL16rCL:
19048 case ROL16rCL_EVEX:
19049 case ROL16rCL_ND:
19050 case ROL16rCL_NF:
19051 case ROL16rCL_NF_ND:
19052 case ROL16ri:
19053 case ROL16ri_EVEX:
19054 case ROL16ri_ND:
19055 case ROL16ri_NF:
19056 case ROL16ri_NF_ND:
19057 case ROL32m1:
19058 case ROL32m1_EVEX:
19059 case ROL32m1_ND:
19060 case ROL32m1_NF:
19061 case ROL32m1_NF_ND:
19062 case ROL32mCL:
19063 case ROL32mCL_EVEX:
19064 case ROL32mCL_ND:
19065 case ROL32mCL_NF:
19066 case ROL32mCL_NF_ND:
19067 case ROL32mi:
19068 case ROL32mi_EVEX:
19069 case ROL32mi_ND:
19070 case ROL32mi_NF:
19071 case ROL32mi_NF_ND:
19072 case ROL32r1:
19073 case ROL32r1_EVEX:
19074 case ROL32r1_ND:
19075 case ROL32r1_NF:
19076 case ROL32r1_NF_ND:
19077 case ROL32rCL:
19078 case ROL32rCL_EVEX:
19079 case ROL32rCL_ND:
19080 case ROL32rCL_NF:
19081 case ROL32rCL_NF_ND:
19082 case ROL32ri:
19083 case ROL32ri_EVEX:
19084 case ROL32ri_ND:
19085 case ROL32ri_NF:
19086 case ROL32ri_NF_ND:
19087 case ROL64m1:
19088 case ROL64m1_EVEX:
19089 case ROL64m1_ND:
19090 case ROL64m1_NF:
19091 case ROL64m1_NF_ND:
19092 case ROL64mCL:
19093 case ROL64mCL_EVEX:
19094 case ROL64mCL_ND:
19095 case ROL64mCL_NF:
19096 case ROL64mCL_NF_ND:
19097 case ROL64mi:
19098 case ROL64mi_EVEX:
19099 case ROL64mi_ND:
19100 case ROL64mi_NF:
19101 case ROL64mi_NF_ND:
19102 case ROL64r1:
19103 case ROL64r1_EVEX:
19104 case ROL64r1_ND:
19105 case ROL64r1_NF:
19106 case ROL64r1_NF_ND:
19107 case ROL64rCL:
19108 case ROL64rCL_EVEX:
19109 case ROL64rCL_ND:
19110 case ROL64rCL_NF:
19111 case ROL64rCL_NF_ND:
19112 case ROL64ri:
19113 case ROL64ri_EVEX:
19114 case ROL64ri_ND:
19115 case ROL64ri_NF:
19116 case ROL64ri_NF_ND:
19117 case ROL8m1:
19118 case ROL8m1_EVEX:
19119 case ROL8m1_ND:
19120 case ROL8m1_NF:
19121 case ROL8m1_NF_ND:
19122 case ROL8mCL:
19123 case ROL8mCL_EVEX:
19124 case ROL8mCL_ND:
19125 case ROL8mCL_NF:
19126 case ROL8mCL_NF_ND:
19127 case ROL8mi:
19128 case ROL8mi_EVEX:
19129 case ROL8mi_ND:
19130 case ROL8mi_NF:
19131 case ROL8mi_NF_ND:
19132 case ROL8r1:
19133 case ROL8r1_EVEX:
19134 case ROL8r1_ND:
19135 case ROL8r1_NF:
19136 case ROL8r1_NF_ND:
19137 case ROL8rCL:
19138 case ROL8rCL_EVEX:
19139 case ROL8rCL_ND:
19140 case ROL8rCL_NF:
19141 case ROL8rCL_NF_ND:
19142 case ROL8ri:
19143 case ROL8ri_EVEX:
19144 case ROL8ri_ND:
19145 case ROL8ri_NF:
19146 case ROL8ri_NF_ND:
19147 return true;
19148 }
19149 return false;
19150}
19151
19152bool isVCVTPS2QQ(unsigned Opcode) {
19153 switch (Opcode) {
19154 case VCVTPS2QQZ128rm:
19155 case VCVTPS2QQZ128rmb:
19156 case VCVTPS2QQZ128rmbk:
19157 case VCVTPS2QQZ128rmbkz:
19158 case VCVTPS2QQZ128rmk:
19159 case VCVTPS2QQZ128rmkz:
19160 case VCVTPS2QQZ128rr:
19161 case VCVTPS2QQZ128rrk:
19162 case VCVTPS2QQZ128rrkz:
19163 case VCVTPS2QQZ256rm:
19164 case VCVTPS2QQZ256rmb:
19165 case VCVTPS2QQZ256rmbk:
19166 case VCVTPS2QQZ256rmbkz:
19167 case VCVTPS2QQZ256rmk:
19168 case VCVTPS2QQZ256rmkz:
19169 case VCVTPS2QQZ256rr:
19170 case VCVTPS2QQZ256rrk:
19171 case VCVTPS2QQZ256rrkz:
19172 case VCVTPS2QQZrm:
19173 case VCVTPS2QQZrmb:
19174 case VCVTPS2QQZrmbk:
19175 case VCVTPS2QQZrmbkz:
19176 case VCVTPS2QQZrmk:
19177 case VCVTPS2QQZrmkz:
19178 case VCVTPS2QQZrr:
19179 case VCVTPS2QQZrrb:
19180 case VCVTPS2QQZrrbk:
19181 case VCVTPS2QQZrrbkz:
19182 case VCVTPS2QQZrrk:
19183 case VCVTPS2QQZrrkz:
19184 return true;
19185 }
19186 return false;
19187}
19188
19189bool isVGETMANTPH(unsigned Opcode) {
19190 switch (Opcode) {
19191 case VGETMANTPHZ128rmbi:
19192 case VGETMANTPHZ128rmbik:
19193 case VGETMANTPHZ128rmbikz:
19194 case VGETMANTPHZ128rmi:
19195 case VGETMANTPHZ128rmik:
19196 case VGETMANTPHZ128rmikz:
19197 case VGETMANTPHZ128rri:
19198 case VGETMANTPHZ128rrik:
19199 case VGETMANTPHZ128rrikz:
19200 case VGETMANTPHZ256rmbi:
19201 case VGETMANTPHZ256rmbik:
19202 case VGETMANTPHZ256rmbikz:
19203 case VGETMANTPHZ256rmi:
19204 case VGETMANTPHZ256rmik:
19205 case VGETMANTPHZ256rmikz:
19206 case VGETMANTPHZ256rri:
19207 case VGETMANTPHZ256rrik:
19208 case VGETMANTPHZ256rrikz:
19209 case VGETMANTPHZrmbi:
19210 case VGETMANTPHZrmbik:
19211 case VGETMANTPHZrmbikz:
19212 case VGETMANTPHZrmi:
19213 case VGETMANTPHZrmik:
19214 case VGETMANTPHZrmikz:
19215 case VGETMANTPHZrri:
19216 case VGETMANTPHZrrib:
19217 case VGETMANTPHZrribk:
19218 case VGETMANTPHZrribkz:
19219 case VGETMANTPHZrrik:
19220 case VGETMANTPHZrrikz:
19221 return true;
19222 }
19223 return false;
19224}
19225
19226bool isPUNPCKLDQ(unsigned Opcode) {
19227 switch (Opcode) {
19228 case MMX_PUNPCKLDQrm:
19229 case MMX_PUNPCKLDQrr:
19230 case PUNPCKLDQrm:
19231 case PUNPCKLDQrr:
19232 return true;
19233 }
19234 return false;
19235}
19236
19237bool isPADDD(unsigned Opcode) {
19238 switch (Opcode) {
19239 case MMX_PADDDrm:
19240 case MMX_PADDDrr:
19241 case PADDDrm:
19242 case PADDDrr:
19243 return true;
19244 }
19245 return false;
19246}
19247
19248bool isVPSLLD(unsigned Opcode) {
19249 switch (Opcode) {
19250 case VPSLLDYri:
19251 case VPSLLDYrm:
19252 case VPSLLDYrr:
19253 case VPSLLDZ128mbi:
19254 case VPSLLDZ128mbik:
19255 case VPSLLDZ128mbikz:
19256 case VPSLLDZ128mi:
19257 case VPSLLDZ128mik:
19258 case VPSLLDZ128mikz:
19259 case VPSLLDZ128ri:
19260 case VPSLLDZ128rik:
19261 case VPSLLDZ128rikz:
19262 case VPSLLDZ128rm:
19263 case VPSLLDZ128rmk:
19264 case VPSLLDZ128rmkz:
19265 case VPSLLDZ128rr:
19266 case VPSLLDZ128rrk:
19267 case VPSLLDZ128rrkz:
19268 case VPSLLDZ256mbi:
19269 case VPSLLDZ256mbik:
19270 case VPSLLDZ256mbikz:
19271 case VPSLLDZ256mi:
19272 case VPSLLDZ256mik:
19273 case VPSLLDZ256mikz:
19274 case VPSLLDZ256ri:
19275 case VPSLLDZ256rik:
19276 case VPSLLDZ256rikz:
19277 case VPSLLDZ256rm:
19278 case VPSLLDZ256rmk:
19279 case VPSLLDZ256rmkz:
19280 case VPSLLDZ256rr:
19281 case VPSLLDZ256rrk:
19282 case VPSLLDZ256rrkz:
19283 case VPSLLDZmbi:
19284 case VPSLLDZmbik:
19285 case VPSLLDZmbikz:
19286 case VPSLLDZmi:
19287 case VPSLLDZmik:
19288 case VPSLLDZmikz:
19289 case VPSLLDZri:
19290 case VPSLLDZrik:
19291 case VPSLLDZrikz:
19292 case VPSLLDZrm:
19293 case VPSLLDZrmk:
19294 case VPSLLDZrmkz:
19295 case VPSLLDZrr:
19296 case VPSLLDZrrk:
19297 case VPSLLDZrrkz:
19298 case VPSLLDri:
19299 case VPSLLDrm:
19300 case VPSLLDrr:
19301 return true;
19302 }
19303 return false;
19304}
19305
19306bool isPFCMPGE(unsigned Opcode) {
19307 switch (Opcode) {
19308 case PFCMPGErm:
19309 case PFCMPGErr:
19310 return true;
19311 }
19312 return false;
19313}
19314
19315bool isVGETMANTBF16(unsigned Opcode) {
19316 switch (Opcode) {
19317 case VGETMANTBF16Z128rmbi:
19318 case VGETMANTBF16Z128rmbik:
19319 case VGETMANTBF16Z128rmbikz:
19320 case VGETMANTBF16Z128rmi:
19321 case VGETMANTBF16Z128rmik:
19322 case VGETMANTBF16Z128rmikz:
19323 case VGETMANTBF16Z128rri:
19324 case VGETMANTBF16Z128rrik:
19325 case VGETMANTBF16Z128rrikz:
19326 case VGETMANTBF16Z256rmbi:
19327 case VGETMANTBF16Z256rmbik:
19328 case VGETMANTBF16Z256rmbikz:
19329 case VGETMANTBF16Z256rmi:
19330 case VGETMANTBF16Z256rmik:
19331 case VGETMANTBF16Z256rmikz:
19332 case VGETMANTBF16Z256rri:
19333 case VGETMANTBF16Z256rrik:
19334 case VGETMANTBF16Z256rrikz:
19335 case VGETMANTBF16Zrmbi:
19336 case VGETMANTBF16Zrmbik:
19337 case VGETMANTBF16Zrmbikz:
19338 case VGETMANTBF16Zrmi:
19339 case VGETMANTBF16Zrmik:
19340 case VGETMANTBF16Zrmikz:
19341 case VGETMANTBF16Zrri:
19342 case VGETMANTBF16Zrrik:
19343 case VGETMANTBF16Zrrikz:
19344 return true;
19345 }
19346 return false;
19347}
19348
19349bool isVSUBBF16(unsigned Opcode) {
19350 switch (Opcode) {
19351 case VSUBBF16Z128rm:
19352 case VSUBBF16Z128rmb:
19353 case VSUBBF16Z128rmbk:
19354 case VSUBBF16Z128rmbkz:
19355 case VSUBBF16Z128rmk:
19356 case VSUBBF16Z128rmkz:
19357 case VSUBBF16Z128rr:
19358 case VSUBBF16Z128rrk:
19359 case VSUBBF16Z128rrkz:
19360 case VSUBBF16Z256rm:
19361 case VSUBBF16Z256rmb:
19362 case VSUBBF16Z256rmbk:
19363 case VSUBBF16Z256rmbkz:
19364 case VSUBBF16Z256rmk:
19365 case VSUBBF16Z256rmkz:
19366 case VSUBBF16Z256rr:
19367 case VSUBBF16Z256rrk:
19368 case VSUBBF16Z256rrkz:
19369 case VSUBBF16Zrm:
19370 case VSUBBF16Zrmb:
19371 case VSUBBF16Zrmbk:
19372 case VSUBBF16Zrmbkz:
19373 case VSUBBF16Zrmk:
19374 case VSUBBF16Zrmkz:
19375 case VSUBBF16Zrr:
19376 case VSUBBF16Zrrk:
19377 case VSUBBF16Zrrkz:
19378 return true;
19379 }
19380 return false;
19381}
19382
19383bool isVPMOVM2D(unsigned Opcode) {
19384 switch (Opcode) {
19385 case VPMOVM2DZ128rk:
19386 case VPMOVM2DZ256rk:
19387 case VPMOVM2DZrk:
19388 return true;
19389 }
19390 return false;
19391}
19392
19393bool isVCVTTSS2USIS(unsigned Opcode) {
19394 switch (Opcode) {
19395 case VCVTTSS2USI64Srm_Int:
19396 case VCVTTSS2USI64Srr_Int:
19397 case VCVTTSS2USI64Srrb_Int:
19398 case VCVTTSS2USISrm_Int:
19399 case VCVTTSS2USISrr_Int:
19400 case VCVTTSS2USISrrb_Int:
19401 return true;
19402 }
19403 return false;
19404}
19405
19406bool isVHSUBPS(unsigned Opcode) {
19407 switch (Opcode) {
19408 case VHSUBPSYrm:
19409 case VHSUBPSYrr:
19410 case VHSUBPSrm:
19411 case VHSUBPSrr:
19412 return true;
19413 }
19414 return false;
19415}
19416
19417bool isENDBR32(unsigned Opcode) {
19418 return Opcode == ENDBR32;
19419}
19420
19421bool isMOVSXD(unsigned Opcode) {
19422 switch (Opcode) {
19423 case MOVSX16rm32:
19424 case MOVSX16rr32:
19425 case MOVSX32rm32:
19426 case MOVSX32rr32:
19427 case MOVSX64rm32:
19428 case MOVSX64rr32:
19429 return true;
19430 }
19431 return false;
19432}
19433
19434bool isPSIGND(unsigned Opcode) {
19435 switch (Opcode) {
19436 case MMX_PSIGNDrm:
19437 case MMX_PSIGNDrr:
19438 case PSIGNDrm:
19439 case PSIGNDrr:
19440 return true;
19441 }
19442 return false;
19443}
19444
19445bool isVPTEST(unsigned Opcode) {
19446 switch (Opcode) {
19447 case VPTESTYrm:
19448 case VPTESTYrr:
19449 case VPTESTrm:
19450 case VPTESTrr:
19451 return true;
19452 }
19453 return false;
19454}
19455
19456bool isVPDPWUSD(unsigned Opcode) {
19457 switch (Opcode) {
19458 case VPDPWUSDYrm:
19459 case VPDPWUSDYrr:
19460 case VPDPWUSDZ128rm:
19461 case VPDPWUSDZ128rmb:
19462 case VPDPWUSDZ128rmbk:
19463 case VPDPWUSDZ128rmbkz:
19464 case VPDPWUSDZ128rmk:
19465 case VPDPWUSDZ128rmkz:
19466 case VPDPWUSDZ128rr:
19467 case VPDPWUSDZ128rrk:
19468 case VPDPWUSDZ128rrkz:
19469 case VPDPWUSDZ256rm:
19470 case VPDPWUSDZ256rmb:
19471 case VPDPWUSDZ256rmbk:
19472 case VPDPWUSDZ256rmbkz:
19473 case VPDPWUSDZ256rmk:
19474 case VPDPWUSDZ256rmkz:
19475 case VPDPWUSDZ256rr:
19476 case VPDPWUSDZ256rrk:
19477 case VPDPWUSDZ256rrkz:
19478 case VPDPWUSDZrm:
19479 case VPDPWUSDZrmb:
19480 case VPDPWUSDZrmbk:
19481 case VPDPWUSDZrmbkz:
19482 case VPDPWUSDZrmk:
19483 case VPDPWUSDZrmkz:
19484 case VPDPWUSDZrr:
19485 case VPDPWUSDZrrk:
19486 case VPDPWUSDZrrkz:
19487 case VPDPWUSDrm:
19488 case VPDPWUSDrr:
19489 return true;
19490 }
19491 return false;
19492}
19493
19494bool isHSUBPD(unsigned Opcode) {
19495 switch (Opcode) {
19496 case HSUBPDrm:
19497 case HSUBPDrr:
19498 return true;
19499 }
19500 return false;
19501}
19502
19503bool isADCX(unsigned Opcode) {
19504 switch (Opcode) {
19505 case ADCX32rm:
19506 case ADCX32rm_EVEX:
19507 case ADCX32rm_ND:
19508 case ADCX32rr:
19509 case ADCX32rr_EVEX:
19510 case ADCX32rr_ND:
19511 case ADCX64rm:
19512 case ADCX64rm_EVEX:
19513 case ADCX64rm_ND:
19514 case ADCX64rr:
19515 case ADCX64rr_EVEX:
19516 case ADCX64rr_ND:
19517 return true;
19518 }
19519 return false;
19520}
19521
19522bool isCVTTPD2PI(unsigned Opcode) {
19523 switch (Opcode) {
19524 case MMX_CVTTPD2PIrm:
19525 case MMX_CVTTPD2PIrr:
19526 return true;
19527 }
19528 return false;
19529}
19530
19531bool isPDEP(unsigned Opcode) {
19532 switch (Opcode) {
19533 case PDEP32rm:
19534 case PDEP32rm_EVEX:
19535 case PDEP32rr:
19536 case PDEP32rr_EVEX:
19537 case PDEP64rm:
19538 case PDEP64rm_EVEX:
19539 case PDEP64rr:
19540 case PDEP64rr_EVEX:
19541 return true;
19542 }
19543 return false;
19544}
19545
19546bool isTDPBUSD(unsigned Opcode) {
19547 return Opcode == TDPBUSD;
19548}
19549
19550bool isVCVTBIASPH2HF8S(unsigned Opcode) {
19551 switch (Opcode) {
19552 case VCVTBIASPH2HF8SZ128rm:
19553 case VCVTBIASPH2HF8SZ128rmb:
19554 case VCVTBIASPH2HF8SZ128rmbk:
19555 case VCVTBIASPH2HF8SZ128rmbkz:
19556 case VCVTBIASPH2HF8SZ128rmk:
19557 case VCVTBIASPH2HF8SZ128rmkz:
19558 case VCVTBIASPH2HF8SZ128rr:
19559 case VCVTBIASPH2HF8SZ128rrk:
19560 case VCVTBIASPH2HF8SZ128rrkz:
19561 case VCVTBIASPH2HF8SZ256rm:
19562 case VCVTBIASPH2HF8SZ256rmb:
19563 case VCVTBIASPH2HF8SZ256rmbk:
19564 case VCVTBIASPH2HF8SZ256rmbkz:
19565 case VCVTBIASPH2HF8SZ256rmk:
19566 case VCVTBIASPH2HF8SZ256rmkz:
19567 case VCVTBIASPH2HF8SZ256rr:
19568 case VCVTBIASPH2HF8SZ256rrk:
19569 case VCVTBIASPH2HF8SZ256rrkz:
19570 case VCVTBIASPH2HF8SZrm:
19571 case VCVTBIASPH2HF8SZrmb:
19572 case VCVTBIASPH2HF8SZrmbk:
19573 case VCVTBIASPH2HF8SZrmbkz:
19574 case VCVTBIASPH2HF8SZrmk:
19575 case VCVTBIASPH2HF8SZrmkz:
19576 case VCVTBIASPH2HF8SZrr:
19577 case VCVTBIASPH2HF8SZrrk:
19578 case VCVTBIASPH2HF8SZrrkz:
19579 return true;
19580 }
19581 return false;
19582}
19583
19584bool isVBROADCASTI32X4(unsigned Opcode) {
19585 switch (Opcode) {
19586 case VBROADCASTI32X4Z256rm:
19587 case VBROADCASTI32X4Z256rmk:
19588 case VBROADCASTI32X4Z256rmkz:
19589 case VBROADCASTI32X4Zrm:
19590 case VBROADCASTI32X4Zrmk:
19591 case VBROADCASTI32X4Zrmkz:
19592 return true;
19593 }
19594 return false;
19595}
19596
19597bool isVCVTPH2UDQ(unsigned Opcode) {
19598 switch (Opcode) {
19599 case VCVTPH2UDQZ128rm:
19600 case VCVTPH2UDQZ128rmb:
19601 case VCVTPH2UDQZ128rmbk:
19602 case VCVTPH2UDQZ128rmbkz:
19603 case VCVTPH2UDQZ128rmk:
19604 case VCVTPH2UDQZ128rmkz:
19605 case VCVTPH2UDQZ128rr:
19606 case VCVTPH2UDQZ128rrk:
19607 case VCVTPH2UDQZ128rrkz:
19608 case VCVTPH2UDQZ256rm:
19609 case VCVTPH2UDQZ256rmb:
19610 case VCVTPH2UDQZ256rmbk:
19611 case VCVTPH2UDQZ256rmbkz:
19612 case VCVTPH2UDQZ256rmk:
19613 case VCVTPH2UDQZ256rmkz:
19614 case VCVTPH2UDQZ256rr:
19615 case VCVTPH2UDQZ256rrk:
19616 case VCVTPH2UDQZ256rrkz:
19617 case VCVTPH2UDQZrm:
19618 case VCVTPH2UDQZrmb:
19619 case VCVTPH2UDQZrmbk:
19620 case VCVTPH2UDQZrmbkz:
19621 case VCVTPH2UDQZrmk:
19622 case VCVTPH2UDQZrmkz:
19623 case VCVTPH2UDQZrr:
19624 case VCVTPH2UDQZrrb:
19625 case VCVTPH2UDQZrrbk:
19626 case VCVTPH2UDQZrrbkz:
19627 case VCVTPH2UDQZrrk:
19628 case VCVTPH2UDQZrrkz:
19629 return true;
19630 }
19631 return false;
19632}
19633
19634bool isVPHADDW(unsigned Opcode) {
19635 switch (Opcode) {
19636 case VPHADDWYrm:
19637 case VPHADDWYrr:
19638 case VPHADDWrm:
19639 case VPHADDWrr:
19640 return true;
19641 }
19642 return false;
19643}
19644
19645bool isFLDL2E(unsigned Opcode) {
19646 return Opcode == FLDL2E;
19647}
19648
19649bool isCLZERO(unsigned Opcode) {
19650 switch (Opcode) {
19651 case CLZERO32r:
19652 case CLZERO64r:
19653 return true;
19654 }
19655 return false;
19656}
19657
19658bool isPBLENDW(unsigned Opcode) {
19659 switch (Opcode) {
19660 case PBLENDWrmi:
19661 case PBLENDWrri:
19662 return true;
19663 }
19664 return false;
19665}
19666
19667bool isVCVTBF162IUBS(unsigned Opcode) {
19668 switch (Opcode) {
19669 case VCVTBF162IUBSZ128rm:
19670 case VCVTBF162IUBSZ128rmb:
19671 case VCVTBF162IUBSZ128rmbk:
19672 case VCVTBF162IUBSZ128rmbkz:
19673 case VCVTBF162IUBSZ128rmk:
19674 case VCVTBF162IUBSZ128rmkz:
19675 case VCVTBF162IUBSZ128rr:
19676 case VCVTBF162IUBSZ128rrk:
19677 case VCVTBF162IUBSZ128rrkz:
19678 case VCVTBF162IUBSZ256rm:
19679 case VCVTBF162IUBSZ256rmb:
19680 case VCVTBF162IUBSZ256rmbk:
19681 case VCVTBF162IUBSZ256rmbkz:
19682 case VCVTBF162IUBSZ256rmk:
19683 case VCVTBF162IUBSZ256rmkz:
19684 case VCVTBF162IUBSZ256rr:
19685 case VCVTBF162IUBSZ256rrk:
19686 case VCVTBF162IUBSZ256rrkz:
19687 case VCVTBF162IUBSZrm:
19688 case VCVTBF162IUBSZrmb:
19689 case VCVTBF162IUBSZrmbk:
19690 case VCVTBF162IUBSZrmbkz:
19691 case VCVTBF162IUBSZrmk:
19692 case VCVTBF162IUBSZrmkz:
19693 case VCVTBF162IUBSZrr:
19694 case VCVTBF162IUBSZrrk:
19695 case VCVTBF162IUBSZrrkz:
19696 return true;
19697 }
19698 return false;
19699}
19700
19701bool isVCVTSH2USI(unsigned Opcode) {
19702 switch (Opcode) {
19703 case VCVTSH2USI64Zrm_Int:
19704 case VCVTSH2USI64Zrr_Int:
19705 case VCVTSH2USI64Zrrb_Int:
19706 case VCVTSH2USIZrm_Int:
19707 case VCVTSH2USIZrr_Int:
19708 case VCVTSH2USIZrrb_Int:
19709 return true;
19710 }
19711 return false;
19712}
19713
19714bool isVANDPD(unsigned Opcode) {
19715 switch (Opcode) {
19716 case VANDPDYrm:
19717 case VANDPDYrr:
19718 case VANDPDZ128rm:
19719 case VANDPDZ128rmb:
19720 case VANDPDZ128rmbk:
19721 case VANDPDZ128rmbkz:
19722 case VANDPDZ128rmk:
19723 case VANDPDZ128rmkz:
19724 case VANDPDZ128rr:
19725 case VANDPDZ128rrk:
19726 case VANDPDZ128rrkz:
19727 case VANDPDZ256rm:
19728 case VANDPDZ256rmb:
19729 case VANDPDZ256rmbk:
19730 case VANDPDZ256rmbkz:
19731 case VANDPDZ256rmk:
19732 case VANDPDZ256rmkz:
19733 case VANDPDZ256rr:
19734 case VANDPDZ256rrk:
19735 case VANDPDZ256rrkz:
19736 case VANDPDZrm:
19737 case VANDPDZrmb:
19738 case VANDPDZrmbk:
19739 case VANDPDZrmbkz:
19740 case VANDPDZrmk:
19741 case VANDPDZrmkz:
19742 case VANDPDZrr:
19743 case VANDPDZrrk:
19744 case VANDPDZrrkz:
19745 case VANDPDrm:
19746 case VANDPDrr:
19747 return true;
19748 }
19749 return false;
19750}
19751
19752bool isBEXTR(unsigned Opcode) {
19753 switch (Opcode) {
19754 case BEXTR32rm:
19755 case BEXTR32rm_EVEX:
19756 case BEXTR32rm_NF:
19757 case BEXTR32rr:
19758 case BEXTR32rr_EVEX:
19759 case BEXTR32rr_NF:
19760 case BEXTR64rm:
19761 case BEXTR64rm_EVEX:
19762 case BEXTR64rm_NF:
19763 case BEXTR64rr:
19764 case BEXTR64rr_EVEX:
19765 case BEXTR64rr_NF:
19766 case BEXTRI32mi:
19767 case BEXTRI32ri:
19768 case BEXTRI64mi:
19769 case BEXTRI64ri:
19770 return true;
19771 }
19772 return false;
19773}
19774
19775bool isSTD(unsigned Opcode) {
19776 return Opcode == STD;
19777}
19778
19779bool isVAESKEYGENASSIST(unsigned Opcode) {
19780 switch (Opcode) {
19781 case VAESKEYGENASSISTrmi:
19782 case VAESKEYGENASSISTrri:
19783 return true;
19784 }
19785 return false;
19786}
19787
19788bool isCMPSD(unsigned Opcode) {
19789 switch (Opcode) {
19790 case CMPSDrmi_Int:
19791 case CMPSDrri_Int:
19792 case CMPSL:
19793 return true;
19794 }
19795 return false;
19796}
19797
19798bool isMOVSS(unsigned Opcode) {
19799 switch (Opcode) {
19800 case MOVSSmr:
19801 case MOVSSrm:
19802 case MOVSSrr:
19803 case MOVSSrr_REV:
19804 return true;
19805 }
19806 return false;
19807}
19808
19809bool isVCVTUQQ2PD(unsigned Opcode) {
19810 switch (Opcode) {
19811 case VCVTUQQ2PDZ128rm:
19812 case VCVTUQQ2PDZ128rmb:
19813 case VCVTUQQ2PDZ128rmbk:
19814 case VCVTUQQ2PDZ128rmbkz:
19815 case VCVTUQQ2PDZ128rmk:
19816 case VCVTUQQ2PDZ128rmkz:
19817 case VCVTUQQ2PDZ128rr:
19818 case VCVTUQQ2PDZ128rrk:
19819 case VCVTUQQ2PDZ128rrkz:
19820 case VCVTUQQ2PDZ256rm:
19821 case VCVTUQQ2PDZ256rmb:
19822 case VCVTUQQ2PDZ256rmbk:
19823 case VCVTUQQ2PDZ256rmbkz:
19824 case VCVTUQQ2PDZ256rmk:
19825 case VCVTUQQ2PDZ256rmkz:
19826 case VCVTUQQ2PDZ256rr:
19827 case VCVTUQQ2PDZ256rrk:
19828 case VCVTUQQ2PDZ256rrkz:
19829 case VCVTUQQ2PDZrm:
19830 case VCVTUQQ2PDZrmb:
19831 case VCVTUQQ2PDZrmbk:
19832 case VCVTUQQ2PDZrmbkz:
19833 case VCVTUQQ2PDZrmk:
19834 case VCVTUQQ2PDZrmkz:
19835 case VCVTUQQ2PDZrr:
19836 case VCVTUQQ2PDZrrb:
19837 case VCVTUQQ2PDZrrbk:
19838 case VCVTUQQ2PDZrrbkz:
19839 case VCVTUQQ2PDZrrk:
19840 case VCVTUQQ2PDZrrkz:
19841 return true;
19842 }
19843 return false;
19844}
19845
19846bool isVEXTRACTI32X4(unsigned Opcode) {
19847 switch (Opcode) {
19848 case VEXTRACTI32X4Z256mri:
19849 case VEXTRACTI32X4Z256mrik:
19850 case VEXTRACTI32X4Z256rri:
19851 case VEXTRACTI32X4Z256rrik:
19852 case VEXTRACTI32X4Z256rrikz:
19853 case VEXTRACTI32X4Zmri:
19854 case VEXTRACTI32X4Zmrik:
19855 case VEXTRACTI32X4Zrri:
19856 case VEXTRACTI32X4Zrrik:
19857 case VEXTRACTI32X4Zrrikz:
19858 return true;
19859 }
19860 return false;
19861}
19862
19863bool isFLDCW(unsigned Opcode) {
19864 return Opcode == FLDCW16m;
19865}
19866
19867bool isINSW(unsigned Opcode) {
19868 return Opcode == INSW;
19869}
19870
19871bool isRDPID(unsigned Opcode) {
19872 switch (Opcode) {
19873 case RDPID32:
19874 case RDPID64:
19875 return true;
19876 }
19877 return false;
19878}
19879
19880bool isVUCOMXSS(unsigned Opcode) {
19881 switch (Opcode) {
19882 case VUCOMXSSZrm_Int:
19883 case VUCOMXSSZrr_Int:
19884 case VUCOMXSSZrrb_Int:
19885 return true;
19886 }
19887 return false;
19888}
19889
19890bool isKANDQ(unsigned Opcode) {
19891 return Opcode == KANDQkk;
19892}
19893
19894bool isV4FMADDPS(unsigned Opcode) {
19895 switch (Opcode) {
19896 case V4FMADDPSrm:
19897 case V4FMADDPSrmk:
19898 case V4FMADDPSrmkz:
19899 return true;
19900 }
19901 return false;
19902}
19903
19904bool isPMOVZXWQ(unsigned Opcode) {
19905 switch (Opcode) {
19906 case PMOVZXWQrm:
19907 case PMOVZXWQrr:
19908 return true;
19909 }
19910 return false;
19911}
19912
19913bool isVFPCLASSSD(unsigned Opcode) {
19914 switch (Opcode) {
19915 case VFPCLASSSDZmi:
19916 case VFPCLASSSDZmik:
19917 case VFPCLASSSDZri:
19918 case VFPCLASSSDZrik:
19919 return true;
19920 }
19921 return false;
19922}
19923
19924bool isBLENDPS(unsigned Opcode) {
19925 switch (Opcode) {
19926 case BLENDPSrmi:
19927 case BLENDPSrri:
19928 return true;
19929 }
19930 return false;
19931}
19932
19933bool isVPACKSSDW(unsigned Opcode) {
19934 switch (Opcode) {
19935 case VPACKSSDWYrm:
19936 case VPACKSSDWYrr:
19937 case VPACKSSDWZ128rm:
19938 case VPACKSSDWZ128rmb:
19939 case VPACKSSDWZ128rmbk:
19940 case VPACKSSDWZ128rmbkz:
19941 case VPACKSSDWZ128rmk:
19942 case VPACKSSDWZ128rmkz:
19943 case VPACKSSDWZ128rr:
19944 case VPACKSSDWZ128rrk:
19945 case VPACKSSDWZ128rrkz:
19946 case VPACKSSDWZ256rm:
19947 case VPACKSSDWZ256rmb:
19948 case VPACKSSDWZ256rmbk:
19949 case VPACKSSDWZ256rmbkz:
19950 case VPACKSSDWZ256rmk:
19951 case VPACKSSDWZ256rmkz:
19952 case VPACKSSDWZ256rr:
19953 case VPACKSSDWZ256rrk:
19954 case VPACKSSDWZ256rrkz:
19955 case VPACKSSDWZrm:
19956 case VPACKSSDWZrmb:
19957 case VPACKSSDWZrmbk:
19958 case VPACKSSDWZrmbkz:
19959 case VPACKSSDWZrmk:
19960 case VPACKSSDWZrmkz:
19961 case VPACKSSDWZrr:
19962 case VPACKSSDWZrrk:
19963 case VPACKSSDWZrrkz:
19964 case VPACKSSDWrm:
19965 case VPACKSSDWrr:
19966 return true;
19967 }
19968 return false;
19969}
19970
19971bool isVPHSUBBW(unsigned Opcode) {
19972 switch (Opcode) {
19973 case VPHSUBBWrm:
19974 case VPHSUBBWrr:
19975 return true;
19976 }
19977 return false;
19978}
19979
19980bool isVPINSRW(unsigned Opcode) {
19981 switch (Opcode) {
19982 case VPINSRWZrmi:
19983 case VPINSRWZrri:
19984 case VPINSRWrmi:
19985 case VPINSRWrri:
19986 return true;
19987 }
19988 return false;
19989}
19990
19991bool isVMINMAXBF16(unsigned Opcode) {
19992 switch (Opcode) {
19993 case VMINMAXBF16Z128rmbi:
19994 case VMINMAXBF16Z128rmbik:
19995 case VMINMAXBF16Z128rmbikz:
19996 case VMINMAXBF16Z128rmi:
19997 case VMINMAXBF16Z128rmik:
19998 case VMINMAXBF16Z128rmikz:
19999 case VMINMAXBF16Z128rri:
20000 case VMINMAXBF16Z128rrik:
20001 case VMINMAXBF16Z128rrikz:
20002 case VMINMAXBF16Z256rmbi:
20003 case VMINMAXBF16Z256rmbik:
20004 case VMINMAXBF16Z256rmbikz:
20005 case VMINMAXBF16Z256rmi:
20006 case VMINMAXBF16Z256rmik:
20007 case VMINMAXBF16Z256rmikz:
20008 case VMINMAXBF16Z256rri:
20009 case VMINMAXBF16Z256rrik:
20010 case VMINMAXBF16Z256rrikz:
20011 case VMINMAXBF16Zrmbi:
20012 case VMINMAXBF16Zrmbik:
20013 case VMINMAXBF16Zrmbikz:
20014 case VMINMAXBF16Zrmi:
20015 case VMINMAXBF16Zrmik:
20016 case VMINMAXBF16Zrmikz:
20017 case VMINMAXBF16Zrri:
20018 case VMINMAXBF16Zrrik:
20019 case VMINMAXBF16Zrrikz:
20020 return true;
20021 }
20022 return false;
20023}
20024
20025bool isVSHUFF64X2(unsigned Opcode) {
20026 switch (Opcode) {
20027 case VSHUFF64X2Z256rmbi:
20028 case VSHUFF64X2Z256rmbik:
20029 case VSHUFF64X2Z256rmbikz:
20030 case VSHUFF64X2Z256rmi:
20031 case VSHUFF64X2Z256rmik:
20032 case VSHUFF64X2Z256rmikz:
20033 case VSHUFF64X2Z256rri:
20034 case VSHUFF64X2Z256rrik:
20035 case VSHUFF64X2Z256rrikz:
20036 case VSHUFF64X2Zrmbi:
20037 case VSHUFF64X2Zrmbik:
20038 case VSHUFF64X2Zrmbikz:
20039 case VSHUFF64X2Zrmi:
20040 case VSHUFF64X2Zrmik:
20041 case VSHUFF64X2Zrmikz:
20042 case VSHUFF64X2Zrri:
20043 case VSHUFF64X2Zrrik:
20044 case VSHUFF64X2Zrrikz:
20045 return true;
20046 }
20047 return false;
20048}
20049
20050bool isVPACKUSWB(unsigned Opcode) {
20051 switch (Opcode) {
20052 case VPACKUSWBYrm:
20053 case VPACKUSWBYrr:
20054 case VPACKUSWBZ128rm:
20055 case VPACKUSWBZ128rmk:
20056 case VPACKUSWBZ128rmkz:
20057 case VPACKUSWBZ128rr:
20058 case VPACKUSWBZ128rrk:
20059 case VPACKUSWBZ128rrkz:
20060 case VPACKUSWBZ256rm:
20061 case VPACKUSWBZ256rmk:
20062 case VPACKUSWBZ256rmkz:
20063 case VPACKUSWBZ256rr:
20064 case VPACKUSWBZ256rrk:
20065 case VPACKUSWBZ256rrkz:
20066 case VPACKUSWBZrm:
20067 case VPACKUSWBZrmk:
20068 case VPACKUSWBZrmkz:
20069 case VPACKUSWBZrr:
20070 case VPACKUSWBZrrk:
20071 case VPACKUSWBZrrkz:
20072 case VPACKUSWBrm:
20073 case VPACKUSWBrr:
20074 return true;
20075 }
20076 return false;
20077}
20078
20079bool isVRSQRT28SS(unsigned Opcode) {
20080 switch (Opcode) {
20081 case VRSQRT28SSZm:
20082 case VRSQRT28SSZmk:
20083 case VRSQRT28SSZmkz:
20084 case VRSQRT28SSZr:
20085 case VRSQRT28SSZrb:
20086 case VRSQRT28SSZrbk:
20087 case VRSQRT28SSZrbkz:
20088 case VRSQRT28SSZrk:
20089 case VRSQRT28SSZrkz:
20090 return true;
20091 }
20092 return false;
20093}
20094
20095bool isGETSEC(unsigned Opcode) {
20096 return Opcode == GETSEC;
20097}
20098
20099bool isFXAM(unsigned Opcode) {
20100 return Opcode == XAM_F;
20101}
20102
20103bool isVEXTRACTF64X4(unsigned Opcode) {
20104 switch (Opcode) {
20105 case VEXTRACTF64X4Zmri:
20106 case VEXTRACTF64X4Zmrik:
20107 case VEXTRACTF64X4Zrri:
20108 case VEXTRACTF64X4Zrrik:
20109 case VEXTRACTF64X4Zrrikz:
20110 return true;
20111 }
20112 return false;
20113}
20114
20115bool isBLSR(unsigned Opcode) {
20116 switch (Opcode) {
20117 case BLSR32rm:
20118 case BLSR32rm_EVEX:
20119 case BLSR32rm_NF:
20120 case BLSR32rr:
20121 case BLSR32rr_EVEX:
20122 case BLSR32rr_NF:
20123 case BLSR64rm:
20124 case BLSR64rm_EVEX:
20125 case BLSR64rm_NF:
20126 case BLSR64rr:
20127 case BLSR64rr_EVEX:
20128 case BLSR64rr_NF:
20129 return true;
20130 }
20131 return false;
20132}
20133
20134bool isFILD(unsigned Opcode) {
20135 switch (Opcode) {
20136 case ILD_F16m:
20137 case ILD_F32m:
20138 case ILD_F64m:
20139 return true;
20140 }
20141 return false;
20142}
20143
20144bool isRETFQ(unsigned Opcode) {
20145 switch (Opcode) {
20146 case LRET64:
20147 case LRETI64:
20148 return true;
20149 }
20150 return false;
20151}
20152
20153bool isVADDSS(unsigned Opcode) {
20154 switch (Opcode) {
20155 case VADDSSZrm_Int:
20156 case VADDSSZrmk_Int:
20157 case VADDSSZrmkz_Int:
20158 case VADDSSZrr_Int:
20159 case VADDSSZrrb_Int:
20160 case VADDSSZrrbk_Int:
20161 case VADDSSZrrbkz_Int:
20162 case VADDSSZrrk_Int:
20163 case VADDSSZrrkz_Int:
20164 case VADDSSrm_Int:
20165 case VADDSSrr_Int:
20166 return true;
20167 }
20168 return false;
20169}
20170
20171bool isCOMISS(unsigned Opcode) {
20172 switch (Opcode) {
20173 case COMISSrm:
20174 case COMISSrr:
20175 return true;
20176 }
20177 return false;
20178}
20179
20180bool isCLI(unsigned Opcode) {
20181 return Opcode == CLI;
20182}
20183
20184bool isVERW(unsigned Opcode) {
20185 switch (Opcode) {
20186 case VERWm:
20187 case VERWr:
20188 return true;
20189 }
20190 return false;
20191}
20192
20193bool isBTC(unsigned Opcode) {
20194 switch (Opcode) {
20195 case BTC16mi8:
20196 case BTC16mr:
20197 case BTC16ri8:
20198 case BTC16rr:
20199 case BTC32mi8:
20200 case BTC32mr:
20201 case BTC32ri8:
20202 case BTC32rr:
20203 case BTC64mi8:
20204 case BTC64mr:
20205 case BTC64ri8:
20206 case BTC64rr:
20207 return true;
20208 }
20209 return false;
20210}
20211
20212bool isVPHADDUBQ(unsigned Opcode) {
20213 switch (Opcode) {
20214 case VPHADDUBQrm:
20215 case VPHADDUBQrr:
20216 return true;
20217 }
20218 return false;
20219}
20220
20221bool isVPORQ(unsigned Opcode) {
20222 switch (Opcode) {
20223 case VPORQZ128rm:
20224 case VPORQZ128rmb:
20225 case VPORQZ128rmbk:
20226 case VPORQZ128rmbkz:
20227 case VPORQZ128rmk:
20228 case VPORQZ128rmkz:
20229 case VPORQZ128rr:
20230 case VPORQZ128rrk:
20231 case VPORQZ128rrkz:
20232 case VPORQZ256rm:
20233 case VPORQZ256rmb:
20234 case VPORQZ256rmbk:
20235 case VPORQZ256rmbkz:
20236 case VPORQZ256rmk:
20237 case VPORQZ256rmkz:
20238 case VPORQZ256rr:
20239 case VPORQZ256rrk:
20240 case VPORQZ256rrkz:
20241 case VPORQZrm:
20242 case VPORQZrmb:
20243 case VPORQZrmbk:
20244 case VPORQZrmbkz:
20245 case VPORQZrmk:
20246 case VPORQZrmkz:
20247 case VPORQZrr:
20248 case VPORQZrrk:
20249 case VPORQZrrkz:
20250 return true;
20251 }
20252 return false;
20253}
20254
20255bool isORPD(unsigned Opcode) {
20256 switch (Opcode) {
20257 case ORPDrm:
20258 case ORPDrr:
20259 return true;
20260 }
20261 return false;
20262}
20263
20264bool isVMOVSS(unsigned Opcode) {
20265 switch (Opcode) {
20266 case VMOVSSZmr:
20267 case VMOVSSZmrk:
20268 case VMOVSSZrm:
20269 case VMOVSSZrmk:
20270 case VMOVSSZrmkz:
20271 case VMOVSSZrr:
20272 case VMOVSSZrr_REV:
20273 case VMOVSSZrrk:
20274 case VMOVSSZrrk_REV:
20275 case VMOVSSZrrkz:
20276 case VMOVSSZrrkz_REV:
20277 case VMOVSSmr:
20278 case VMOVSSrm:
20279 case VMOVSSrr:
20280 case VMOVSSrr_REV:
20281 return true;
20282 }
20283 return false;
20284}
20285
20286bool isVPSUBD(unsigned Opcode) {
20287 switch (Opcode) {
20288 case VPSUBDYrm:
20289 case VPSUBDYrr:
20290 case VPSUBDZ128rm:
20291 case VPSUBDZ128rmb:
20292 case VPSUBDZ128rmbk:
20293 case VPSUBDZ128rmbkz:
20294 case VPSUBDZ128rmk:
20295 case VPSUBDZ128rmkz:
20296 case VPSUBDZ128rr:
20297 case VPSUBDZ128rrk:
20298 case VPSUBDZ128rrkz:
20299 case VPSUBDZ256rm:
20300 case VPSUBDZ256rmb:
20301 case VPSUBDZ256rmbk:
20302 case VPSUBDZ256rmbkz:
20303 case VPSUBDZ256rmk:
20304 case VPSUBDZ256rmkz:
20305 case VPSUBDZ256rr:
20306 case VPSUBDZ256rrk:
20307 case VPSUBDZ256rrkz:
20308 case VPSUBDZrm:
20309 case VPSUBDZrmb:
20310 case VPSUBDZrmbk:
20311 case VPSUBDZrmbkz:
20312 case VPSUBDZrmk:
20313 case VPSUBDZrmkz:
20314 case VPSUBDZrr:
20315 case VPSUBDZrrk:
20316 case VPSUBDZrrkz:
20317 case VPSUBDrm:
20318 case VPSUBDrr:
20319 return true;
20320 }
20321 return false;
20322}
20323
20324bool isVGATHERPF1QPD(unsigned Opcode) {
20325 return Opcode == VGATHERPF1QPDm;
20326}
20327
20328bool isENCODEKEY256(unsigned Opcode) {
20329 return Opcode == ENCODEKEY256;
20330}
20331
20332bool isGF2P8AFFINEINVQB(unsigned Opcode) {
20333 switch (Opcode) {
20334 case GF2P8AFFINEINVQBrmi:
20335 case GF2P8AFFINEINVQBrri:
20336 return true;
20337 }
20338 return false;
20339}
20340
20341bool isXRSTOR64(unsigned Opcode) {
20342 return Opcode == XRSTOR64;
20343}
20344
20345bool isKANDW(unsigned Opcode) {
20346 return Opcode == KANDWkk;
20347}
20348
20349bool isLODSQ(unsigned Opcode) {
20350 return Opcode == LODSQ;
20351}
20352
20353bool isVMOVRSW(unsigned Opcode) {
20354 switch (Opcode) {
20355 case VMOVRSWZ128m:
20356 case VMOVRSWZ128mk:
20357 case VMOVRSWZ128mkz:
20358 case VMOVRSWZ256m:
20359 case VMOVRSWZ256mk:
20360 case VMOVRSWZ256mkz:
20361 case VMOVRSWZm:
20362 case VMOVRSWZmk:
20363 case VMOVRSWZmkz:
20364 return true;
20365 }
20366 return false;
20367}
20368
20369bool isVSUBSH(unsigned Opcode) {
20370 switch (Opcode) {
20371 case VSUBSHZrm_Int:
20372 case VSUBSHZrmk_Int:
20373 case VSUBSHZrmkz_Int:
20374 case VSUBSHZrr_Int:
20375 case VSUBSHZrrb_Int:
20376 case VSUBSHZrrbk_Int:
20377 case VSUBSHZrrbkz_Int:
20378 case VSUBSHZrrk_Int:
20379 case VSUBSHZrrkz_Int:
20380 return true;
20381 }
20382 return false;
20383}
20384
20385bool isLSS(unsigned Opcode) {
20386 switch (Opcode) {
20387 case LSS16rm:
20388 case LSS32rm:
20389 case LSS64rm:
20390 return true;
20391 }
20392 return false;
20393}
20394
20395bool isPMOVSXBQ(unsigned Opcode) {
20396 switch (Opcode) {
20397 case PMOVSXBQrm:
20398 case PMOVSXBQrr:
20399 return true;
20400 }
20401 return false;
20402}
20403
20404bool isVCVTTSD2SIS(unsigned Opcode) {
20405 switch (Opcode) {
20406 case VCVTTSD2SI64Srm_Int:
20407 case VCVTTSD2SI64Srr_Int:
20408 case VCVTTSD2SI64Srrb_Int:
20409 case VCVTTSD2SISrm_Int:
20410 case VCVTTSD2SISrr_Int:
20411 case VCVTTSD2SISrrb_Int:
20412 return true;
20413 }
20414 return false;
20415}
20416
20417bool isVCMPSH(unsigned Opcode) {
20418 switch (Opcode) {
20419 case VCMPSHZrmi_Int:
20420 case VCMPSHZrmik_Int:
20421 case VCMPSHZrri_Int:
20422 case VCMPSHZrrib_Int:
20423 case VCMPSHZrribk_Int:
20424 case VCMPSHZrrik_Int:
20425 return true;
20426 }
20427 return false;
20428}
20429
20430bool isVFMADD132PS(unsigned Opcode) {
20431 switch (Opcode) {
20432 case VFMADD132PSYm:
20433 case VFMADD132PSYr:
20434 case VFMADD132PSZ128m:
20435 case VFMADD132PSZ128mb:
20436 case VFMADD132PSZ128mbk:
20437 case VFMADD132PSZ128mbkz:
20438 case VFMADD132PSZ128mk:
20439 case VFMADD132PSZ128mkz:
20440 case VFMADD132PSZ128r:
20441 case VFMADD132PSZ128rk:
20442 case VFMADD132PSZ128rkz:
20443 case VFMADD132PSZ256m:
20444 case VFMADD132PSZ256mb:
20445 case VFMADD132PSZ256mbk:
20446 case VFMADD132PSZ256mbkz:
20447 case VFMADD132PSZ256mk:
20448 case VFMADD132PSZ256mkz:
20449 case VFMADD132PSZ256r:
20450 case VFMADD132PSZ256rk:
20451 case VFMADD132PSZ256rkz:
20452 case VFMADD132PSZm:
20453 case VFMADD132PSZmb:
20454 case VFMADD132PSZmbk:
20455 case VFMADD132PSZmbkz:
20456 case VFMADD132PSZmk:
20457 case VFMADD132PSZmkz:
20458 case VFMADD132PSZr:
20459 case VFMADD132PSZrb:
20460 case VFMADD132PSZrbk:
20461 case VFMADD132PSZrbkz:
20462 case VFMADD132PSZrk:
20463 case VFMADD132PSZrkz:
20464 case VFMADD132PSm:
20465 case VFMADD132PSr:
20466 return true;
20467 }
20468 return false;
20469}
20470
20471bool isVPACKSSWB(unsigned Opcode) {
20472 switch (Opcode) {
20473 case VPACKSSWBYrm:
20474 case VPACKSSWBYrr:
20475 case VPACKSSWBZ128rm:
20476 case VPACKSSWBZ128rmk:
20477 case VPACKSSWBZ128rmkz:
20478 case VPACKSSWBZ128rr:
20479 case VPACKSSWBZ128rrk:
20480 case VPACKSSWBZ128rrkz:
20481 case VPACKSSWBZ256rm:
20482 case VPACKSSWBZ256rmk:
20483 case VPACKSSWBZ256rmkz:
20484 case VPACKSSWBZ256rr:
20485 case VPACKSSWBZ256rrk:
20486 case VPACKSSWBZ256rrkz:
20487 case VPACKSSWBZrm:
20488 case VPACKSSWBZrmk:
20489 case VPACKSSWBZrmkz:
20490 case VPACKSSWBZrr:
20491 case VPACKSSWBZrrk:
20492 case VPACKSSWBZrrkz:
20493 case VPACKSSWBrm:
20494 case VPACKSSWBrr:
20495 return true;
20496 }
20497 return false;
20498}
20499
20500bool isPCMPGTQ(unsigned Opcode) {
20501 switch (Opcode) {
20502 case PCMPGTQrm:
20503 case PCMPGTQrr:
20504 return true;
20505 }
20506 return false;
20507}
20508
20509bool isVFMADD132SH(unsigned Opcode) {
20510 switch (Opcode) {
20511 case VFMADD132SHZm_Int:
20512 case VFMADD132SHZmk_Int:
20513 case VFMADD132SHZmkz_Int:
20514 case VFMADD132SHZr_Int:
20515 case VFMADD132SHZrb_Int:
20516 case VFMADD132SHZrbk_Int:
20517 case VFMADD132SHZrbkz_Int:
20518 case VFMADD132SHZrk_Int:
20519 case VFMADD132SHZrkz_Int:
20520 return true;
20521 }
20522 return false;
20523}
20524
20525bool isVCVTUQQ2PH(unsigned Opcode) {
20526 switch (Opcode) {
20527 case VCVTUQQ2PHZ128rm:
20528 case VCVTUQQ2PHZ128rmb:
20529 case VCVTUQQ2PHZ128rmbk:
20530 case VCVTUQQ2PHZ128rmbkz:
20531 case VCVTUQQ2PHZ128rmk:
20532 case VCVTUQQ2PHZ128rmkz:
20533 case VCVTUQQ2PHZ128rr:
20534 case VCVTUQQ2PHZ128rrk:
20535 case VCVTUQQ2PHZ128rrkz:
20536 case VCVTUQQ2PHZ256rm:
20537 case VCVTUQQ2PHZ256rmb:
20538 case VCVTUQQ2PHZ256rmbk:
20539 case VCVTUQQ2PHZ256rmbkz:
20540 case VCVTUQQ2PHZ256rmk:
20541 case VCVTUQQ2PHZ256rmkz:
20542 case VCVTUQQ2PHZ256rr:
20543 case VCVTUQQ2PHZ256rrk:
20544 case VCVTUQQ2PHZ256rrkz:
20545 case VCVTUQQ2PHZrm:
20546 case VCVTUQQ2PHZrmb:
20547 case VCVTUQQ2PHZrmbk:
20548 case VCVTUQQ2PHZrmbkz:
20549 case VCVTUQQ2PHZrmk:
20550 case VCVTUQQ2PHZrmkz:
20551 case VCVTUQQ2PHZrr:
20552 case VCVTUQQ2PHZrrb:
20553 case VCVTUQQ2PHZrrbk:
20554 case VCVTUQQ2PHZrrbkz:
20555 case VCVTUQQ2PHZrrk:
20556 case VCVTUQQ2PHZrrkz:
20557 return true;
20558 }
20559 return false;
20560}
20561
20562bool isVCVTQQ2PS(unsigned Opcode) {
20563 switch (Opcode) {
20564 case VCVTQQ2PSZ128rm:
20565 case VCVTQQ2PSZ128rmb:
20566 case VCVTQQ2PSZ128rmbk:
20567 case VCVTQQ2PSZ128rmbkz:
20568 case VCVTQQ2PSZ128rmk:
20569 case VCVTQQ2PSZ128rmkz:
20570 case VCVTQQ2PSZ128rr:
20571 case VCVTQQ2PSZ128rrk:
20572 case VCVTQQ2PSZ128rrkz:
20573 case VCVTQQ2PSZ256rm:
20574 case VCVTQQ2PSZ256rmb:
20575 case VCVTQQ2PSZ256rmbk:
20576 case VCVTQQ2PSZ256rmbkz:
20577 case VCVTQQ2PSZ256rmk:
20578 case VCVTQQ2PSZ256rmkz:
20579 case VCVTQQ2PSZ256rr:
20580 case VCVTQQ2PSZ256rrk:
20581 case VCVTQQ2PSZ256rrkz:
20582 case VCVTQQ2PSZrm:
20583 case VCVTQQ2PSZrmb:
20584 case VCVTQQ2PSZrmbk:
20585 case VCVTQQ2PSZrmbkz:
20586 case VCVTQQ2PSZrmk:
20587 case VCVTQQ2PSZrmkz:
20588 case VCVTQQ2PSZrr:
20589 case VCVTQQ2PSZrrb:
20590 case VCVTQQ2PSZrrbk:
20591 case VCVTQQ2PSZrrbkz:
20592 case VCVTQQ2PSZrrk:
20593 case VCVTQQ2PSZrrkz:
20594 return true;
20595 }
20596 return false;
20597}
20598
20599bool isVCVTTSS2USI(unsigned Opcode) {
20600 switch (Opcode) {
20601 case VCVTTSS2USI64Zrm_Int:
20602 case VCVTTSS2USI64Zrr_Int:
20603 case VCVTTSS2USI64Zrrb_Int:
20604 case VCVTTSS2USIZrm_Int:
20605 case VCVTTSS2USIZrr_Int:
20606 case VCVTTSS2USIZrrb_Int:
20607 return true;
20608 }
20609 return false;
20610}
20611
20612bool isVPMOVM2Q(unsigned Opcode) {
20613 switch (Opcode) {
20614 case VPMOVM2QZ128rk:
20615 case VPMOVM2QZ256rk:
20616 case VPMOVM2QZrk:
20617 return true;
20618 }
20619 return false;
20620}
20621
20622bool isVMOVD(unsigned Opcode) {
20623 switch (Opcode) {
20624 case VMOVDI2PDIZrm:
20625 case VMOVDI2PDIZrr:
20626 case VMOVDI2PDIrm:
20627 case VMOVDI2PDIrr:
20628 case VMOVPDI2DIZmr:
20629 case VMOVPDI2DIZrr:
20630 case VMOVPDI2DImr:
20631 case VMOVPDI2DIrr:
20632 case VMOVZPDILo2PDIZmr:
20633 case VMOVZPDILo2PDIZrm:
20634 case VMOVZPDILo2PDIZrr:
20635 case VMOVZPDILo2PDIZrr2:
20636 return true;
20637 }
20638 return false;
20639}
20640
20641bool isVCVTTPS2QQS(unsigned Opcode) {
20642 switch (Opcode) {
20643 case VCVTTPS2QQSZ128rm:
20644 case VCVTTPS2QQSZ128rmb:
20645 case VCVTTPS2QQSZ128rmbk:
20646 case VCVTTPS2QQSZ128rmbkz:
20647 case VCVTTPS2QQSZ128rmk:
20648 case VCVTTPS2QQSZ128rmkz:
20649 case VCVTTPS2QQSZ128rr:
20650 case VCVTTPS2QQSZ128rrk:
20651 case VCVTTPS2QQSZ128rrkz:
20652 case VCVTTPS2QQSZ256rm:
20653 case VCVTTPS2QQSZ256rmb:
20654 case VCVTTPS2QQSZ256rmbk:
20655 case VCVTTPS2QQSZ256rmbkz:
20656 case VCVTTPS2QQSZ256rmk:
20657 case VCVTTPS2QQSZ256rmkz:
20658 case VCVTTPS2QQSZ256rr:
20659 case VCVTTPS2QQSZ256rrb:
20660 case VCVTTPS2QQSZ256rrbk:
20661 case VCVTTPS2QQSZ256rrbkz:
20662 case VCVTTPS2QQSZ256rrk:
20663 case VCVTTPS2QQSZ256rrkz:
20664 case VCVTTPS2QQSZrm:
20665 case VCVTTPS2QQSZrmb:
20666 case VCVTTPS2QQSZrmbk:
20667 case VCVTTPS2QQSZrmbkz:
20668 case VCVTTPS2QQSZrmk:
20669 case VCVTTPS2QQSZrmkz:
20670 case VCVTTPS2QQSZrr:
20671 case VCVTTPS2QQSZrrb:
20672 case VCVTTPS2QQSZrrbk:
20673 case VCVTTPS2QQSZrrbkz:
20674 case VCVTTPS2QQSZrrk:
20675 case VCVTTPS2QQSZrrkz:
20676 return true;
20677 }
20678 return false;
20679}
20680
20681bool isVSQRTBF16(unsigned Opcode) {
20682 switch (Opcode) {
20683 case VSQRTBF16Z128m:
20684 case VSQRTBF16Z128mb:
20685 case VSQRTBF16Z128mbk:
20686 case VSQRTBF16Z128mbkz:
20687 case VSQRTBF16Z128mk:
20688 case VSQRTBF16Z128mkz:
20689 case VSQRTBF16Z128r:
20690 case VSQRTBF16Z128rk:
20691 case VSQRTBF16Z128rkz:
20692 case VSQRTBF16Z256m:
20693 case VSQRTBF16Z256mb:
20694 case VSQRTBF16Z256mbk:
20695 case VSQRTBF16Z256mbkz:
20696 case VSQRTBF16Z256mk:
20697 case VSQRTBF16Z256mkz:
20698 case VSQRTBF16Z256r:
20699 case VSQRTBF16Z256rk:
20700 case VSQRTBF16Z256rkz:
20701 case VSQRTBF16Zm:
20702 case VSQRTBF16Zmb:
20703 case VSQRTBF16Zmbk:
20704 case VSQRTBF16Zmbkz:
20705 case VSQRTBF16Zmk:
20706 case VSQRTBF16Zmkz:
20707 case VSQRTBF16Zr:
20708 case VSQRTBF16Zrk:
20709 case VSQRTBF16Zrkz:
20710 return true;
20711 }
20712 return false;
20713}
20714
20715bool isVFPCLASSPH(unsigned Opcode) {
20716 switch (Opcode) {
20717 case VFPCLASSPHZ128mbi:
20718 case VFPCLASSPHZ128mbik:
20719 case VFPCLASSPHZ128mi:
20720 case VFPCLASSPHZ128mik:
20721 case VFPCLASSPHZ128ri:
20722 case VFPCLASSPHZ128rik:
20723 case VFPCLASSPHZ256mbi:
20724 case VFPCLASSPHZ256mbik:
20725 case VFPCLASSPHZ256mi:
20726 case VFPCLASSPHZ256mik:
20727 case VFPCLASSPHZ256ri:
20728 case VFPCLASSPHZ256rik:
20729 case VFPCLASSPHZmbi:
20730 case VFPCLASSPHZmbik:
20731 case VFPCLASSPHZmi:
20732 case VFPCLASSPHZmik:
20733 case VFPCLASSPHZri:
20734 case VFPCLASSPHZrik:
20735 return true;
20736 }
20737 return false;
20738}
20739
20740bool isVCVTSS2SH(unsigned Opcode) {
20741 switch (Opcode) {
20742 case VCVTSS2SHZrm_Int:
20743 case VCVTSS2SHZrmk_Int:
20744 case VCVTSS2SHZrmkz_Int:
20745 case VCVTSS2SHZrr_Int:
20746 case VCVTSS2SHZrrb_Int:
20747 case VCVTSS2SHZrrbk_Int:
20748 case VCVTSS2SHZrrbkz_Int:
20749 case VCVTSS2SHZrrk_Int:
20750 case VCVTSS2SHZrrkz_Int:
20751 return true;
20752 }
20753 return false;
20754}
20755
20756bool isSCASB(unsigned Opcode) {
20757 return Opcode == SCASB;
20758}
20759
20760bool isPSRLD(unsigned Opcode) {
20761 switch (Opcode) {
20762 case MMX_PSRLDri:
20763 case MMX_PSRLDrm:
20764 case MMX_PSRLDrr:
20765 case PSRLDri:
20766 case PSRLDrm:
20767 case PSRLDrr:
20768 return true;
20769 }
20770 return false;
20771}
20772
20773bool isVADDPH(unsigned Opcode) {
20774 switch (Opcode) {
20775 case VADDPHZ128rm:
20776 case VADDPHZ128rmb:
20777 case VADDPHZ128rmbk:
20778 case VADDPHZ128rmbkz:
20779 case VADDPHZ128rmk:
20780 case VADDPHZ128rmkz:
20781 case VADDPHZ128rr:
20782 case VADDPHZ128rrk:
20783 case VADDPHZ128rrkz:
20784 case VADDPHZ256rm:
20785 case VADDPHZ256rmb:
20786 case VADDPHZ256rmbk:
20787 case VADDPHZ256rmbkz:
20788 case VADDPHZ256rmk:
20789 case VADDPHZ256rmkz:
20790 case VADDPHZ256rr:
20791 case VADDPHZ256rrk:
20792 case VADDPHZ256rrkz:
20793 case VADDPHZrm:
20794 case VADDPHZrmb:
20795 case VADDPHZrmbk:
20796 case VADDPHZrmbkz:
20797 case VADDPHZrmk:
20798 case VADDPHZrmkz:
20799 case VADDPHZrr:
20800 case VADDPHZrrb:
20801 case VADDPHZrrbk:
20802 case VADDPHZrrbkz:
20803 case VADDPHZrrk:
20804 case VADDPHZrrkz:
20805 return true;
20806 }
20807 return false;
20808}
20809
20810bool isFSUB(unsigned Opcode) {
20811 switch (Opcode) {
20812 case SUB_F32m:
20813 case SUB_F64m:
20814 case SUB_FST0r:
20815 case SUB_FrST0:
20816 return true;
20817 }
20818 return false;
20819}
20820
20821bool isVCVTTPH2IBS(unsigned Opcode) {
20822 switch (Opcode) {
20823 case VCVTTPH2IBSZ128rm:
20824 case VCVTTPH2IBSZ128rmb:
20825 case VCVTTPH2IBSZ128rmbk:
20826 case VCVTTPH2IBSZ128rmbkz:
20827 case VCVTTPH2IBSZ128rmk:
20828 case VCVTTPH2IBSZ128rmkz:
20829 case VCVTTPH2IBSZ128rr:
20830 case VCVTTPH2IBSZ128rrk:
20831 case VCVTTPH2IBSZ128rrkz:
20832 case VCVTTPH2IBSZ256rm:
20833 case VCVTTPH2IBSZ256rmb:
20834 case VCVTTPH2IBSZ256rmbk:
20835 case VCVTTPH2IBSZ256rmbkz:
20836 case VCVTTPH2IBSZ256rmk:
20837 case VCVTTPH2IBSZ256rmkz:
20838 case VCVTTPH2IBSZ256rr:
20839 case VCVTTPH2IBSZ256rrk:
20840 case VCVTTPH2IBSZ256rrkz:
20841 case VCVTTPH2IBSZrm:
20842 case VCVTTPH2IBSZrmb:
20843 case VCVTTPH2IBSZrmbk:
20844 case VCVTTPH2IBSZrmbkz:
20845 case VCVTTPH2IBSZrmk:
20846 case VCVTTPH2IBSZrmkz:
20847 case VCVTTPH2IBSZrr:
20848 case VCVTTPH2IBSZrrb:
20849 case VCVTTPH2IBSZrrbk:
20850 case VCVTTPH2IBSZrrbkz:
20851 case VCVTTPH2IBSZrrk:
20852 case VCVTTPH2IBSZrrkz:
20853 return true;
20854 }
20855 return false;
20856}
20857
20858bool isVEXTRACTI64X2(unsigned Opcode) {
20859 switch (Opcode) {
20860 case VEXTRACTI64X2Z256mri:
20861 case VEXTRACTI64X2Z256mrik:
20862 case VEXTRACTI64X2Z256rri:
20863 case VEXTRACTI64X2Z256rrik:
20864 case VEXTRACTI64X2Z256rrikz:
20865 case VEXTRACTI64X2Zmri:
20866 case VEXTRACTI64X2Zmrik:
20867 case VEXTRACTI64X2Zrri:
20868 case VEXTRACTI64X2Zrrik:
20869 case VEXTRACTI64X2Zrrikz:
20870 return true;
20871 }
20872 return false;
20873}
20874
20875bool isVPSHLDD(unsigned Opcode) {
20876 switch (Opcode) {
20877 case VPSHLDDZ128rmbi:
20878 case VPSHLDDZ128rmbik:
20879 case VPSHLDDZ128rmbikz:
20880 case VPSHLDDZ128rmi:
20881 case VPSHLDDZ128rmik:
20882 case VPSHLDDZ128rmikz:
20883 case VPSHLDDZ128rri:
20884 case VPSHLDDZ128rrik:
20885 case VPSHLDDZ128rrikz:
20886 case VPSHLDDZ256rmbi:
20887 case VPSHLDDZ256rmbik:
20888 case VPSHLDDZ256rmbikz:
20889 case VPSHLDDZ256rmi:
20890 case VPSHLDDZ256rmik:
20891 case VPSHLDDZ256rmikz:
20892 case VPSHLDDZ256rri:
20893 case VPSHLDDZ256rrik:
20894 case VPSHLDDZ256rrikz:
20895 case VPSHLDDZrmbi:
20896 case VPSHLDDZrmbik:
20897 case VPSHLDDZrmbikz:
20898 case VPSHLDDZrmi:
20899 case VPSHLDDZrmik:
20900 case VPSHLDDZrmikz:
20901 case VPSHLDDZrri:
20902 case VPSHLDDZrrik:
20903 case VPSHLDDZrrikz:
20904 return true;
20905 }
20906 return false;
20907}
20908
20909bool isPMINUW(unsigned Opcode) {
20910 switch (Opcode) {
20911 case PMINUWrm:
20912 case PMINUWrr:
20913 return true;
20914 }
20915 return false;
20916}
20917
20918bool isPSUBSB(unsigned Opcode) {
20919 switch (Opcode) {
20920 case MMX_PSUBSBrm:
20921 case MMX_PSUBSBrr:
20922 case PSUBSBrm:
20923 case PSUBSBrr:
20924 return true;
20925 }
20926 return false;
20927}
20928
20929bool isVCVT2PS2PHX(unsigned Opcode) {
20930 switch (Opcode) {
20931 case VCVT2PS2PHXZ128rm:
20932 case VCVT2PS2PHXZ128rmb:
20933 case VCVT2PS2PHXZ128rmbk:
20934 case VCVT2PS2PHXZ128rmbkz:
20935 case VCVT2PS2PHXZ128rmk:
20936 case VCVT2PS2PHXZ128rmkz:
20937 case VCVT2PS2PHXZ128rr:
20938 case VCVT2PS2PHXZ128rrk:
20939 case VCVT2PS2PHXZ128rrkz:
20940 case VCVT2PS2PHXZ256rm:
20941 case VCVT2PS2PHXZ256rmb:
20942 case VCVT2PS2PHXZ256rmbk:
20943 case VCVT2PS2PHXZ256rmbkz:
20944 case VCVT2PS2PHXZ256rmk:
20945 case VCVT2PS2PHXZ256rmkz:
20946 case VCVT2PS2PHXZ256rr:
20947 case VCVT2PS2PHXZ256rrk:
20948 case VCVT2PS2PHXZ256rrkz:
20949 case VCVT2PS2PHXZrm:
20950 case VCVT2PS2PHXZrmb:
20951 case VCVT2PS2PHXZrmbk:
20952 case VCVT2PS2PHXZrmbkz:
20953 case VCVT2PS2PHXZrmk:
20954 case VCVT2PS2PHXZrmkz:
20955 case VCVT2PS2PHXZrr:
20956 case VCVT2PS2PHXZrrb:
20957 case VCVT2PS2PHXZrrbk:
20958 case VCVT2PS2PHXZrrbkz:
20959 case VCVT2PS2PHXZrrk:
20960 case VCVT2PS2PHXZrrkz:
20961 return true;
20962 }
20963 return false;
20964}
20965
20966bool isVPCMPEQD(unsigned Opcode) {
20967 switch (Opcode) {
20968 case VPCMPEQDYrm:
20969 case VPCMPEQDYrr:
20970 case VPCMPEQDZ128rm:
20971 case VPCMPEQDZ128rmb:
20972 case VPCMPEQDZ128rmbk:
20973 case VPCMPEQDZ128rmk:
20974 case VPCMPEQDZ128rr:
20975 case VPCMPEQDZ128rrk:
20976 case VPCMPEQDZ256rm:
20977 case VPCMPEQDZ256rmb:
20978 case VPCMPEQDZ256rmbk:
20979 case VPCMPEQDZ256rmk:
20980 case VPCMPEQDZ256rr:
20981 case VPCMPEQDZ256rrk:
20982 case VPCMPEQDZrm:
20983 case VPCMPEQDZrmb:
20984 case VPCMPEQDZrmbk:
20985 case VPCMPEQDZrmk:
20986 case VPCMPEQDZrr:
20987 case VPCMPEQDZrrk:
20988 case VPCMPEQDrm:
20989 case VPCMPEQDrr:
20990 return true;
20991 }
20992 return false;
20993}
20994
20995bool isVPSCATTERQD(unsigned Opcode) {
20996 switch (Opcode) {
20997 case VPSCATTERQDZ128mr:
20998 case VPSCATTERQDZ256mr:
20999 case VPSCATTERQDZmr:
21000 return true;
21001 }
21002 return false;
21003}
21004
21005bool isKXNORB(unsigned Opcode) {
21006 return Opcode == KXNORBkk;
21007}
21008
21009bool isLDDQU(unsigned Opcode) {
21010 return Opcode == LDDQUrm;
21011}
21012
21013bool isMASKMOVQ(unsigned Opcode) {
21014 switch (Opcode) {
21015 case MMX_MASKMOVQ:
21016 case MMX_MASKMOVQ64:
21017 return true;
21018 }
21019 return false;
21020}
21021
21022bool isPABSW(unsigned Opcode) {
21023 switch (Opcode) {
21024 case MMX_PABSWrm:
21025 case MMX_PABSWrr:
21026 case PABSWrm:
21027 case PABSWrr:
21028 return true;
21029 }
21030 return false;
21031}
21032
21033bool isVPCOMQ(unsigned Opcode) {
21034 switch (Opcode) {
21035 case VPCOMQmi:
21036 case VPCOMQri:
21037 return true;
21038 }
21039 return false;
21040}
21041
21042bool isVPROLD(unsigned Opcode) {
21043 switch (Opcode) {
21044 case VPROLDZ128mbi:
21045 case VPROLDZ128mbik:
21046 case VPROLDZ128mbikz:
21047 case VPROLDZ128mi:
21048 case VPROLDZ128mik:
21049 case VPROLDZ128mikz:
21050 case VPROLDZ128ri:
21051 case VPROLDZ128rik:
21052 case VPROLDZ128rikz:
21053 case VPROLDZ256mbi:
21054 case VPROLDZ256mbik:
21055 case VPROLDZ256mbikz:
21056 case VPROLDZ256mi:
21057 case VPROLDZ256mik:
21058 case VPROLDZ256mikz:
21059 case VPROLDZ256ri:
21060 case VPROLDZ256rik:
21061 case VPROLDZ256rikz:
21062 case VPROLDZmbi:
21063 case VPROLDZmbik:
21064 case VPROLDZmbikz:
21065 case VPROLDZmi:
21066 case VPROLDZmik:
21067 case VPROLDZmikz:
21068 case VPROLDZri:
21069 case VPROLDZrik:
21070 case VPROLDZrikz:
21071 return true;
21072 }
21073 return false;
21074}
21075
21076bool isVSCATTERDPD(unsigned Opcode) {
21077 switch (Opcode) {
21078 case VSCATTERDPDZ128mr:
21079 case VSCATTERDPDZ256mr:
21080 case VSCATTERDPDZmr:
21081 return true;
21082 }
21083 return false;
21084}
21085
21086bool isFXRSTOR(unsigned Opcode) {
21087 return Opcode == FXRSTOR;
21088}
21089
21090bool isVPCMPUW(unsigned Opcode) {
21091 switch (Opcode) {
21092 case VPCMPUWZ128rmi:
21093 case VPCMPUWZ128rmik:
21094 case VPCMPUWZ128rri:
21095 case VPCMPUWZ128rrik:
21096 case VPCMPUWZ256rmi:
21097 case VPCMPUWZ256rmik:
21098 case VPCMPUWZ256rri:
21099 case VPCMPUWZ256rrik:
21100 case VPCMPUWZrmi:
21101 case VPCMPUWZrmik:
21102 case VPCMPUWZrri:
21103 case VPCMPUWZrrik:
21104 return true;
21105 }
21106 return false;
21107}
21108
21109bool isWBINVD(unsigned Opcode) {
21110 return Opcode == WBINVD;
21111}
21112
21113bool isVCVTTPD2UDQ(unsigned Opcode) {
21114 switch (Opcode) {
21115 case VCVTTPD2UDQZ128rm:
21116 case VCVTTPD2UDQZ128rmb:
21117 case VCVTTPD2UDQZ128rmbk:
21118 case VCVTTPD2UDQZ128rmbkz:
21119 case VCVTTPD2UDQZ128rmk:
21120 case VCVTTPD2UDQZ128rmkz:
21121 case VCVTTPD2UDQZ128rr:
21122 case VCVTTPD2UDQZ128rrk:
21123 case VCVTTPD2UDQZ128rrkz:
21124 case VCVTTPD2UDQZ256rm:
21125 case VCVTTPD2UDQZ256rmb:
21126 case VCVTTPD2UDQZ256rmbk:
21127 case VCVTTPD2UDQZ256rmbkz:
21128 case VCVTTPD2UDQZ256rmk:
21129 case VCVTTPD2UDQZ256rmkz:
21130 case VCVTTPD2UDQZ256rr:
21131 case VCVTTPD2UDQZ256rrk:
21132 case VCVTTPD2UDQZ256rrkz:
21133 case VCVTTPD2UDQZrm:
21134 case VCVTTPD2UDQZrmb:
21135 case VCVTTPD2UDQZrmbk:
21136 case VCVTTPD2UDQZrmbkz:
21137 case VCVTTPD2UDQZrmk:
21138 case VCVTTPD2UDQZrmkz:
21139 case VCVTTPD2UDQZrr:
21140 case VCVTTPD2UDQZrrb:
21141 case VCVTTPD2UDQZrrbk:
21142 case VCVTTPD2UDQZrrbkz:
21143 case VCVTTPD2UDQZrrk:
21144 case VCVTTPD2UDQZrrkz:
21145 return true;
21146 }
21147 return false;
21148}
21149
21150bool isERETU(unsigned Opcode) {
21151 return Opcode == ERETU;
21152}
21153
21154bool isPFRCPIT2(unsigned Opcode) {
21155 switch (Opcode) {
21156 case PFRCPIT2rm:
21157 case PFRCPIT2rr:
21158 return true;
21159 }
21160 return false;
21161}
21162
21163bool isVPERMT2W(unsigned Opcode) {
21164 switch (Opcode) {
21165 case VPERMT2WZ128rm:
21166 case VPERMT2WZ128rmk:
21167 case VPERMT2WZ128rmkz:
21168 case VPERMT2WZ128rr:
21169 case VPERMT2WZ128rrk:
21170 case VPERMT2WZ128rrkz:
21171 case VPERMT2WZ256rm:
21172 case VPERMT2WZ256rmk:
21173 case VPERMT2WZ256rmkz:
21174 case VPERMT2WZ256rr:
21175 case VPERMT2WZ256rrk:
21176 case VPERMT2WZ256rrkz:
21177 case VPERMT2WZrm:
21178 case VPERMT2WZrmk:
21179 case VPERMT2WZrmkz:
21180 case VPERMT2WZrr:
21181 case VPERMT2WZrrk:
21182 case VPERMT2WZrrkz:
21183 return true;
21184 }
21185 return false;
21186}
21187
21188bool isVEXTRACTF32X4(unsigned Opcode) {
21189 switch (Opcode) {
21190 case VEXTRACTF32X4Z256mri:
21191 case VEXTRACTF32X4Z256mrik:
21192 case VEXTRACTF32X4Z256rri:
21193 case VEXTRACTF32X4Z256rrik:
21194 case VEXTRACTF32X4Z256rrikz:
21195 case VEXTRACTF32X4Zmri:
21196 case VEXTRACTF32X4Zmrik:
21197 case VEXTRACTF32X4Zrri:
21198 case VEXTRACTF32X4Zrrik:
21199 case VEXTRACTF32X4Zrrikz:
21200 return true;
21201 }
21202 return false;
21203}
21204
21205bool isVGATHERPF0DPD(unsigned Opcode) {
21206 return Opcode == VGATHERPF0DPDm;
21207}
21208
21209bool isVBROADCASTF32X2(unsigned Opcode) {
21210 switch (Opcode) {
21211 case VBROADCASTF32X2Z256rm:
21212 case VBROADCASTF32X2Z256rmk:
21213 case VBROADCASTF32X2Z256rmkz:
21214 case VBROADCASTF32X2Z256rr:
21215 case VBROADCASTF32X2Z256rrk:
21216 case VBROADCASTF32X2Z256rrkz:
21217 case VBROADCASTF32X2Zrm:
21218 case VBROADCASTF32X2Zrmk:
21219 case VBROADCASTF32X2Zrmkz:
21220 case VBROADCASTF32X2Zrr:
21221 case VBROADCASTF32X2Zrrk:
21222 case VBROADCASTF32X2Zrrkz:
21223 return true;
21224 }
21225 return false;
21226}
21227
21228bool isVRCP14SD(unsigned Opcode) {
21229 switch (Opcode) {
21230 case VRCP14SDZrm:
21231 case VRCP14SDZrmk:
21232 case VRCP14SDZrmkz:
21233 case VRCP14SDZrr:
21234 case VRCP14SDZrrk:
21235 case VRCP14SDZrrkz:
21236 return true;
21237 }
21238 return false;
21239}
21240
21241bool isLAHF(unsigned Opcode) {
21242 return Opcode == LAHF;
21243}
21244
21245bool isPABSD(unsigned Opcode) {
21246 switch (Opcode) {
21247 case MMX_PABSDrm:
21248 case MMX_PABSDrr:
21249 case PABSDrm:
21250 case PABSDrr:
21251 return true;
21252 }
21253 return false;
21254}
21255
21256bool isPINSRB(unsigned Opcode) {
21257 switch (Opcode) {
21258 case PINSRBrmi:
21259 case PINSRBrri:
21260 return true;
21261 }
21262 return false;
21263}
21264
21265bool isSKINIT(unsigned Opcode) {
21266 return Opcode == SKINIT;
21267}
21268
21269bool isENTER(unsigned Opcode) {
21270 return Opcode == ENTER;
21271}
21272
21273bool isVCVTSI2SS(unsigned Opcode) {
21274 switch (Opcode) {
21275 case VCVTSI2SSZrm_Int:
21276 case VCVTSI2SSZrr_Int:
21277 case VCVTSI2SSZrrb_Int:
21278 case VCVTSI2SSrm_Int:
21279 case VCVTSI2SSrr_Int:
21280 case VCVTSI642SSZrm_Int:
21281 case VCVTSI642SSZrr_Int:
21282 case VCVTSI642SSZrrb_Int:
21283 case VCVTSI642SSrm_Int:
21284 case VCVTSI642SSrr_Int:
21285 return true;
21286 }
21287 return false;
21288}
21289
21290bool isVFMADD231PD(unsigned Opcode) {
21291 switch (Opcode) {
21292 case VFMADD231PDYm:
21293 case VFMADD231PDYr:
21294 case VFMADD231PDZ128m:
21295 case VFMADD231PDZ128mb:
21296 case VFMADD231PDZ128mbk:
21297 case VFMADD231PDZ128mbkz:
21298 case VFMADD231PDZ128mk:
21299 case VFMADD231PDZ128mkz:
21300 case VFMADD231PDZ128r:
21301 case VFMADD231PDZ128rk:
21302 case VFMADD231PDZ128rkz:
21303 case VFMADD231PDZ256m:
21304 case VFMADD231PDZ256mb:
21305 case VFMADD231PDZ256mbk:
21306 case VFMADD231PDZ256mbkz:
21307 case VFMADD231PDZ256mk:
21308 case VFMADD231PDZ256mkz:
21309 case VFMADD231PDZ256r:
21310 case VFMADD231PDZ256rk:
21311 case VFMADD231PDZ256rkz:
21312 case VFMADD231PDZm:
21313 case VFMADD231PDZmb:
21314 case VFMADD231PDZmbk:
21315 case VFMADD231PDZmbkz:
21316 case VFMADD231PDZmk:
21317 case VFMADD231PDZmkz:
21318 case VFMADD231PDZr:
21319 case VFMADD231PDZrb:
21320 case VFMADD231PDZrbk:
21321 case VFMADD231PDZrbkz:
21322 case VFMADD231PDZrk:
21323 case VFMADD231PDZrkz:
21324 case VFMADD231PDm:
21325 case VFMADD231PDr:
21326 return true;
21327 }
21328 return false;
21329}
21330
21331bool isLOADIWKEY(unsigned Opcode) {
21332 return Opcode == LOADIWKEY;
21333}
21334
21335bool isVMOVNTDQA(unsigned Opcode) {
21336 switch (Opcode) {
21337 case VMOVNTDQAYrm:
21338 case VMOVNTDQAZ128rm:
21339 case VMOVNTDQAZ256rm:
21340 case VMOVNTDQAZrm:
21341 case VMOVNTDQArm:
21342 return true;
21343 }
21344 return false;
21345}
21346
21347bool isVPERMT2PS(unsigned Opcode) {
21348 switch (Opcode) {
21349 case VPERMT2PSZ128rm:
21350 case VPERMT2PSZ128rmb:
21351 case VPERMT2PSZ128rmbk:
21352 case VPERMT2PSZ128rmbkz:
21353 case VPERMT2PSZ128rmk:
21354 case VPERMT2PSZ128rmkz:
21355 case VPERMT2PSZ128rr:
21356 case VPERMT2PSZ128rrk:
21357 case VPERMT2PSZ128rrkz:
21358 case VPERMT2PSZ256rm:
21359 case VPERMT2PSZ256rmb:
21360 case VPERMT2PSZ256rmbk:
21361 case VPERMT2PSZ256rmbkz:
21362 case VPERMT2PSZ256rmk:
21363 case VPERMT2PSZ256rmkz:
21364 case VPERMT2PSZ256rr:
21365 case VPERMT2PSZ256rrk:
21366 case VPERMT2PSZ256rrkz:
21367 case VPERMT2PSZrm:
21368 case VPERMT2PSZrmb:
21369 case VPERMT2PSZrmbk:
21370 case VPERMT2PSZrmbkz:
21371 case VPERMT2PSZrmk:
21372 case VPERMT2PSZrmkz:
21373 case VPERMT2PSZrr:
21374 case VPERMT2PSZrrk:
21375 case VPERMT2PSZrrkz:
21376 return true;
21377 }
21378 return false;
21379}
21380
21381bool isPUSHF(unsigned Opcode) {
21382 return Opcode == PUSHF16;
21383}
21384
21385bool isMPSADBW(unsigned Opcode) {
21386 switch (Opcode) {
21387 case MPSADBWrmi:
21388 case MPSADBWrri:
21389 return true;
21390 }
21391 return false;
21392}
21393
21394bool isVMINMAXSH(unsigned Opcode) {
21395 switch (Opcode) {
21396 case VMINMAXSHrmi_Int:
21397 case VMINMAXSHrmik_Int:
21398 case VMINMAXSHrmikz_Int:
21399 case VMINMAXSHrri_Int:
21400 case VMINMAXSHrrib_Int:
21401 case VMINMAXSHrribk_Int:
21402 case VMINMAXSHrribkz_Int:
21403 case VMINMAXSHrrik_Int:
21404 case VMINMAXSHrrikz_Int:
21405 return true;
21406 }
21407 return false;
21408}
21409
21410bool isVRSQRT14SS(unsigned Opcode) {
21411 switch (Opcode) {
21412 case VRSQRT14SSZrm:
21413 case VRSQRT14SSZrmk:
21414 case VRSQRT14SSZrmkz:
21415 case VRSQRT14SSZrr:
21416 case VRSQRT14SSZrrk:
21417 case VRSQRT14SSZrrkz:
21418 return true;
21419 }
21420 return false;
21421}
21422
21423bool isVCVTDQ2PD(unsigned Opcode) {
21424 switch (Opcode) {
21425 case VCVTDQ2PDYrm:
21426 case VCVTDQ2PDYrr:
21427 case VCVTDQ2PDZ128rm:
21428 case VCVTDQ2PDZ128rmb:
21429 case VCVTDQ2PDZ128rmbk:
21430 case VCVTDQ2PDZ128rmbkz:
21431 case VCVTDQ2PDZ128rmk:
21432 case VCVTDQ2PDZ128rmkz:
21433 case VCVTDQ2PDZ128rr:
21434 case VCVTDQ2PDZ128rrk:
21435 case VCVTDQ2PDZ128rrkz:
21436 case VCVTDQ2PDZ256rm:
21437 case VCVTDQ2PDZ256rmb:
21438 case VCVTDQ2PDZ256rmbk:
21439 case VCVTDQ2PDZ256rmbkz:
21440 case VCVTDQ2PDZ256rmk:
21441 case VCVTDQ2PDZ256rmkz:
21442 case VCVTDQ2PDZ256rr:
21443 case VCVTDQ2PDZ256rrk:
21444 case VCVTDQ2PDZ256rrkz:
21445 case VCVTDQ2PDZrm:
21446 case VCVTDQ2PDZrmb:
21447 case VCVTDQ2PDZrmbk:
21448 case VCVTDQ2PDZrmbkz:
21449 case VCVTDQ2PDZrmk:
21450 case VCVTDQ2PDZrmkz:
21451 case VCVTDQ2PDZrr:
21452 case VCVTDQ2PDZrrk:
21453 case VCVTDQ2PDZrrkz:
21454 case VCVTDQ2PDrm:
21455 case VCVTDQ2PDrr:
21456 return true;
21457 }
21458 return false;
21459}
21460
21461bool isVORPS(unsigned Opcode) {
21462 switch (Opcode) {
21463 case VORPSYrm:
21464 case VORPSYrr:
21465 case VORPSZ128rm:
21466 case VORPSZ128rmb:
21467 case VORPSZ128rmbk:
21468 case VORPSZ128rmbkz:
21469 case VORPSZ128rmk:
21470 case VORPSZ128rmkz:
21471 case VORPSZ128rr:
21472 case VORPSZ128rrk:
21473 case VORPSZ128rrkz:
21474 case VORPSZ256rm:
21475 case VORPSZ256rmb:
21476 case VORPSZ256rmbk:
21477 case VORPSZ256rmbkz:
21478 case VORPSZ256rmk:
21479 case VORPSZ256rmkz:
21480 case VORPSZ256rr:
21481 case VORPSZ256rrk:
21482 case VORPSZ256rrkz:
21483 case VORPSZrm:
21484 case VORPSZrmb:
21485 case VORPSZrmbk:
21486 case VORPSZrmbkz:
21487 case VORPSZrmk:
21488 case VORPSZrmkz:
21489 case VORPSZrr:
21490 case VORPSZrrk:
21491 case VORPSZrrkz:
21492 case VORPSrm:
21493 case VORPSrr:
21494 return true;
21495 }
21496 return false;
21497}
21498
21499bool isVPEXPANDQ(unsigned Opcode) {
21500 switch (Opcode) {
21501 case VPEXPANDQZ128rm:
21502 case VPEXPANDQZ128rmk:
21503 case VPEXPANDQZ128rmkz:
21504 case VPEXPANDQZ128rr:
21505 case VPEXPANDQZ128rrk:
21506 case VPEXPANDQZ128rrkz:
21507 case VPEXPANDQZ256rm:
21508 case VPEXPANDQZ256rmk:
21509 case VPEXPANDQZ256rmkz:
21510 case VPEXPANDQZ256rr:
21511 case VPEXPANDQZ256rrk:
21512 case VPEXPANDQZ256rrkz:
21513 case VPEXPANDQZrm:
21514 case VPEXPANDQZrmk:
21515 case VPEXPANDQZrmkz:
21516 case VPEXPANDQZrr:
21517 case VPEXPANDQZrrk:
21518 case VPEXPANDQZrrkz:
21519 return true;
21520 }
21521 return false;
21522}
21523
21524bool isVPSHRDD(unsigned Opcode) {
21525 switch (Opcode) {
21526 case VPSHRDDZ128rmbi:
21527 case VPSHRDDZ128rmbik:
21528 case VPSHRDDZ128rmbikz:
21529 case VPSHRDDZ128rmi:
21530 case VPSHRDDZ128rmik:
21531 case VPSHRDDZ128rmikz:
21532 case VPSHRDDZ128rri:
21533 case VPSHRDDZ128rrik:
21534 case VPSHRDDZ128rrikz:
21535 case VPSHRDDZ256rmbi:
21536 case VPSHRDDZ256rmbik:
21537 case VPSHRDDZ256rmbikz:
21538 case VPSHRDDZ256rmi:
21539 case VPSHRDDZ256rmik:
21540 case VPSHRDDZ256rmikz:
21541 case VPSHRDDZ256rri:
21542 case VPSHRDDZ256rrik:
21543 case VPSHRDDZ256rrikz:
21544 case VPSHRDDZrmbi:
21545 case VPSHRDDZrmbik:
21546 case VPSHRDDZrmbikz:
21547 case VPSHRDDZrmi:
21548 case VPSHRDDZrmik:
21549 case VPSHRDDZrmikz:
21550 case VPSHRDDZrri:
21551 case VPSHRDDZrrik:
21552 case VPSHRDDZrrikz:
21553 return true;
21554 }
21555 return false;
21556}
21557
21558bool isTDPBSSD(unsigned Opcode) {
21559 return Opcode == TDPBSSD;
21560}
21561
21562bool isTESTUI(unsigned Opcode) {
21563 return Opcode == TESTUI;
21564}
21565
21566bool isVFMADDPD(unsigned Opcode) {
21567 switch (Opcode) {
21568 case VFMADDPD4Ymr:
21569 case VFMADDPD4Yrm:
21570 case VFMADDPD4Yrr:
21571 case VFMADDPD4Yrr_REV:
21572 case VFMADDPD4mr:
21573 case VFMADDPD4rm:
21574 case VFMADDPD4rr:
21575 case VFMADDPD4rr_REV:
21576 return true;
21577 }
21578 return false;
21579}
21580
21581bool isVPANDND(unsigned Opcode) {
21582 switch (Opcode) {
21583 case VPANDNDZ128rm:
21584 case VPANDNDZ128rmb:
21585 case VPANDNDZ128rmbk:
21586 case VPANDNDZ128rmbkz:
21587 case VPANDNDZ128rmk:
21588 case VPANDNDZ128rmkz:
21589 case VPANDNDZ128rr:
21590 case VPANDNDZ128rrk:
21591 case VPANDNDZ128rrkz:
21592 case VPANDNDZ256rm:
21593 case VPANDNDZ256rmb:
21594 case VPANDNDZ256rmbk:
21595 case VPANDNDZ256rmbkz:
21596 case VPANDNDZ256rmk:
21597 case VPANDNDZ256rmkz:
21598 case VPANDNDZ256rr:
21599 case VPANDNDZ256rrk:
21600 case VPANDNDZ256rrkz:
21601 case VPANDNDZrm:
21602 case VPANDNDZrmb:
21603 case VPANDNDZrmbk:
21604 case VPANDNDZrmbkz:
21605 case VPANDNDZrmk:
21606 case VPANDNDZrmkz:
21607 case VPANDNDZrr:
21608 case VPANDNDZrrk:
21609 case VPANDNDZrrkz:
21610 return true;
21611 }
21612 return false;
21613}
21614
21615bool isVPMOVSDB(unsigned Opcode) {
21616 switch (Opcode) {
21617 case VPMOVSDBZ128mr:
21618 case VPMOVSDBZ128mrk:
21619 case VPMOVSDBZ128rr:
21620 case VPMOVSDBZ128rrk:
21621 case VPMOVSDBZ128rrkz:
21622 case VPMOVSDBZ256mr:
21623 case VPMOVSDBZ256mrk:
21624 case VPMOVSDBZ256rr:
21625 case VPMOVSDBZ256rrk:
21626 case VPMOVSDBZ256rrkz:
21627 case VPMOVSDBZmr:
21628 case VPMOVSDBZmrk:
21629 case VPMOVSDBZrr:
21630 case VPMOVSDBZrrk:
21631 case VPMOVSDBZrrkz:
21632 return true;
21633 }
21634 return false;
21635}
21636
21637bool isVPBROADCASTB(unsigned Opcode) {
21638 switch (Opcode) {
21639 case VPBROADCASTBYrm:
21640 case VPBROADCASTBYrr:
21641 case VPBROADCASTBZ128rm:
21642 case VPBROADCASTBZ128rmk:
21643 case VPBROADCASTBZ128rmkz:
21644 case VPBROADCASTBZ128rr:
21645 case VPBROADCASTBZ128rrk:
21646 case VPBROADCASTBZ128rrkz:
21647 case VPBROADCASTBZ256rm:
21648 case VPBROADCASTBZ256rmk:
21649 case VPBROADCASTBZ256rmkz:
21650 case VPBROADCASTBZ256rr:
21651 case VPBROADCASTBZ256rrk:
21652 case VPBROADCASTBZ256rrkz:
21653 case VPBROADCASTBZrm:
21654 case VPBROADCASTBZrmk:
21655 case VPBROADCASTBZrmkz:
21656 case VPBROADCASTBZrr:
21657 case VPBROADCASTBZrrk:
21658 case VPBROADCASTBZrrkz:
21659 case VPBROADCASTBrZ128rr:
21660 case VPBROADCASTBrZ128rrk:
21661 case VPBROADCASTBrZ128rrkz:
21662 case VPBROADCASTBrZ256rr:
21663 case VPBROADCASTBrZ256rrk:
21664 case VPBROADCASTBrZ256rrkz:
21665 case VPBROADCASTBrZrr:
21666 case VPBROADCASTBrZrrk:
21667 case VPBROADCASTBrZrrkz:
21668 case VPBROADCASTBrm:
21669 case VPBROADCASTBrr:
21670 return true;
21671 }
21672 return false;
21673}
21674
21675bool isCVTPI2PD(unsigned Opcode) {
21676 switch (Opcode) {
21677 case MMX_CVTPI2PDrm:
21678 case MMX_CVTPI2PDrr:
21679 return true;
21680 }
21681 return false;
21682}
21683
21684bool isVPERMI2B(unsigned Opcode) {
21685 switch (Opcode) {
21686 case VPERMI2BZ128rm:
21687 case VPERMI2BZ128rmk:
21688 case VPERMI2BZ128rmkz:
21689 case VPERMI2BZ128rr:
21690 case VPERMI2BZ128rrk:
21691 case VPERMI2BZ128rrkz:
21692 case VPERMI2BZ256rm:
21693 case VPERMI2BZ256rmk:
21694 case VPERMI2BZ256rmkz:
21695 case VPERMI2BZ256rr:
21696 case VPERMI2BZ256rrk:
21697 case VPERMI2BZ256rrkz:
21698 case VPERMI2BZrm:
21699 case VPERMI2BZrmk:
21700 case VPERMI2BZrmkz:
21701 case VPERMI2BZrr:
21702 case VPERMI2BZrrk:
21703 case VPERMI2BZrrkz:
21704 return true;
21705 }
21706 return false;
21707}
21708
21709bool isVPMINSB(unsigned Opcode) {
21710 switch (Opcode) {
21711 case VPMINSBYrm:
21712 case VPMINSBYrr:
21713 case VPMINSBZ128rm:
21714 case VPMINSBZ128rmk:
21715 case VPMINSBZ128rmkz:
21716 case VPMINSBZ128rr:
21717 case VPMINSBZ128rrk:
21718 case VPMINSBZ128rrkz:
21719 case VPMINSBZ256rm:
21720 case VPMINSBZ256rmk:
21721 case VPMINSBZ256rmkz:
21722 case VPMINSBZ256rr:
21723 case VPMINSBZ256rrk:
21724 case VPMINSBZ256rrkz:
21725 case VPMINSBZrm:
21726 case VPMINSBZrmk:
21727 case VPMINSBZrmkz:
21728 case VPMINSBZrr:
21729 case VPMINSBZrrk:
21730 case VPMINSBZrrkz:
21731 case VPMINSBrm:
21732 case VPMINSBrr:
21733 return true;
21734 }
21735 return false;
21736}
21737
21738bool isLAR(unsigned Opcode) {
21739 switch (Opcode) {
21740 case LAR16rm:
21741 case LAR16rr:
21742 case LAR32rm:
21743 case LAR32rr:
21744 case LAR64rm:
21745 case LAR64rr:
21746 return true;
21747 }
21748 return false;
21749}
21750
21751bool isINVLPGB(unsigned Opcode) {
21752 switch (Opcode) {
21753 case INVLPGB32:
21754 case INVLPGB64:
21755 return true;
21756 }
21757 return false;
21758}
21759
21760bool isTLBSYNC(unsigned Opcode) {
21761 return Opcode == TLBSYNC;
21762}
21763
21764bool isFDIVP(unsigned Opcode) {
21765 return Opcode == DIV_FPrST0;
21766}
21767
21768bool isVPSRLW(unsigned Opcode) {
21769 switch (Opcode) {
21770 case VPSRLWYri:
21771 case VPSRLWYrm:
21772 case VPSRLWYrr:
21773 case VPSRLWZ128mi:
21774 case VPSRLWZ128mik:
21775 case VPSRLWZ128mikz:
21776 case VPSRLWZ128ri:
21777 case VPSRLWZ128rik:
21778 case VPSRLWZ128rikz:
21779 case VPSRLWZ128rm:
21780 case VPSRLWZ128rmk:
21781 case VPSRLWZ128rmkz:
21782 case VPSRLWZ128rr:
21783 case VPSRLWZ128rrk:
21784 case VPSRLWZ128rrkz:
21785 case VPSRLWZ256mi:
21786 case VPSRLWZ256mik:
21787 case VPSRLWZ256mikz:
21788 case VPSRLWZ256ri:
21789 case VPSRLWZ256rik:
21790 case VPSRLWZ256rikz:
21791 case VPSRLWZ256rm:
21792 case VPSRLWZ256rmk:
21793 case VPSRLWZ256rmkz:
21794 case VPSRLWZ256rr:
21795 case VPSRLWZ256rrk:
21796 case VPSRLWZ256rrkz:
21797 case VPSRLWZmi:
21798 case VPSRLWZmik:
21799 case VPSRLWZmikz:
21800 case VPSRLWZri:
21801 case VPSRLWZrik:
21802 case VPSRLWZrikz:
21803 case VPSRLWZrm:
21804 case VPSRLWZrmk:
21805 case VPSRLWZrmkz:
21806 case VPSRLWZrr:
21807 case VPSRLWZrrk:
21808 case VPSRLWZrrkz:
21809 case VPSRLWri:
21810 case VPSRLWrm:
21811 case VPSRLWrr:
21812 return true;
21813 }
21814 return false;
21815}
21816
21817bool isVRCP28SS(unsigned Opcode) {
21818 switch (Opcode) {
21819 case VRCP28SSZm:
21820 case VRCP28SSZmk:
21821 case VRCP28SSZmkz:
21822 case VRCP28SSZr:
21823 case VRCP28SSZrb:
21824 case VRCP28SSZrbk:
21825 case VRCP28SSZrbkz:
21826 case VRCP28SSZrk:
21827 case VRCP28SSZrkz:
21828 return true;
21829 }
21830 return false;
21831}
21832
21833bool isVMOVHPS(unsigned Opcode) {
21834 switch (Opcode) {
21835 case VMOVHPSZ128mr:
21836 case VMOVHPSZ128rm:
21837 case VMOVHPSmr:
21838 case VMOVHPSrm:
21839 return true;
21840 }
21841 return false;
21842}
21843
21844bool isVPMACSSDD(unsigned Opcode) {
21845 switch (Opcode) {
21846 case VPMACSSDDrm:
21847 case VPMACSSDDrr:
21848 return true;
21849 }
21850 return false;
21851}
21852
21853bool isPEXT(unsigned Opcode) {
21854 switch (Opcode) {
21855 case PEXT32rm:
21856 case PEXT32rm_EVEX:
21857 case PEXT32rr:
21858 case PEXT32rr_EVEX:
21859 case PEXT64rm:
21860 case PEXT64rm_EVEX:
21861 case PEXT64rr:
21862 case PEXT64rr_EVEX:
21863 return true;
21864 }
21865 return false;
21866}
21867
21868bool isVMAXBF16(unsigned Opcode) {
21869 switch (Opcode) {
21870 case VMAXBF16Z128rm:
21871 case VMAXBF16Z128rmb:
21872 case VMAXBF16Z128rmbk:
21873 case VMAXBF16Z128rmbkz:
21874 case VMAXBF16Z128rmk:
21875 case VMAXBF16Z128rmkz:
21876 case VMAXBF16Z128rr:
21877 case VMAXBF16Z128rrk:
21878 case VMAXBF16Z128rrkz:
21879 case VMAXBF16Z256rm:
21880 case VMAXBF16Z256rmb:
21881 case VMAXBF16Z256rmbk:
21882 case VMAXBF16Z256rmbkz:
21883 case VMAXBF16Z256rmk:
21884 case VMAXBF16Z256rmkz:
21885 case VMAXBF16Z256rr:
21886 case VMAXBF16Z256rrk:
21887 case VMAXBF16Z256rrkz:
21888 case VMAXBF16Zrm:
21889 case VMAXBF16Zrmb:
21890 case VMAXBF16Zrmbk:
21891 case VMAXBF16Zrmbkz:
21892 case VMAXBF16Zrmk:
21893 case VMAXBF16Zrmkz:
21894 case VMAXBF16Zrr:
21895 case VMAXBF16Zrrk:
21896 case VMAXBF16Zrrkz:
21897 return true;
21898 }
21899 return false;
21900}
21901
21902bool isVRSQRT14SD(unsigned Opcode) {
21903 switch (Opcode) {
21904 case VRSQRT14SDZrm:
21905 case VRSQRT14SDZrmk:
21906 case VRSQRT14SDZrmkz:
21907 case VRSQRT14SDZrr:
21908 case VRSQRT14SDZrrk:
21909 case VRSQRT14SDZrrkz:
21910 return true;
21911 }
21912 return false;
21913}
21914
21915bool isVPDPWSSD(unsigned Opcode) {
21916 switch (Opcode) {
21917 case VPDPWSSDYrm:
21918 case VPDPWSSDYrr:
21919 case VPDPWSSDZ128rm:
21920 case VPDPWSSDZ128rmb:
21921 case VPDPWSSDZ128rmbk:
21922 case VPDPWSSDZ128rmbkz:
21923 case VPDPWSSDZ128rmk:
21924 case VPDPWSSDZ128rmkz:
21925 case VPDPWSSDZ128rr:
21926 case VPDPWSSDZ128rrk:
21927 case VPDPWSSDZ128rrkz:
21928 case VPDPWSSDZ256rm:
21929 case VPDPWSSDZ256rmb:
21930 case VPDPWSSDZ256rmbk:
21931 case VPDPWSSDZ256rmbkz:
21932 case VPDPWSSDZ256rmk:
21933 case VPDPWSSDZ256rmkz:
21934 case VPDPWSSDZ256rr:
21935 case VPDPWSSDZ256rrk:
21936 case VPDPWSSDZ256rrkz:
21937 case VPDPWSSDZrm:
21938 case VPDPWSSDZrmb:
21939 case VPDPWSSDZrmbk:
21940 case VPDPWSSDZrmbkz:
21941 case VPDPWSSDZrmk:
21942 case VPDPWSSDZrmkz:
21943 case VPDPWSSDZrr:
21944 case VPDPWSSDZrrk:
21945 case VPDPWSSDZrrkz:
21946 case VPDPWSSDrm:
21947 case VPDPWSSDrr:
21948 return true;
21949 }
21950 return false;
21951}
21952
21953bool isVFMSUB231SD(unsigned Opcode) {
21954 switch (Opcode) {
21955 case VFMSUB231SDZm_Int:
21956 case VFMSUB231SDZmk_Int:
21957 case VFMSUB231SDZmkz_Int:
21958 case VFMSUB231SDZr_Int:
21959 case VFMSUB231SDZrb_Int:
21960 case VFMSUB231SDZrbk_Int:
21961 case VFMSUB231SDZrbkz_Int:
21962 case VFMSUB231SDZrk_Int:
21963 case VFMSUB231SDZrkz_Int:
21964 case VFMSUB231SDm_Int:
21965 case VFMSUB231SDr_Int:
21966 return true;
21967 }
21968 return false;
21969}
21970
21971bool isVPMOVZXWQ(unsigned Opcode) {
21972 switch (Opcode) {
21973 case VPMOVZXWQYrm:
21974 case VPMOVZXWQYrr:
21975 case VPMOVZXWQZ128rm:
21976 case VPMOVZXWQZ128rmk:
21977 case VPMOVZXWQZ128rmkz:
21978 case VPMOVZXWQZ128rr:
21979 case VPMOVZXWQZ128rrk:
21980 case VPMOVZXWQZ128rrkz:
21981 case VPMOVZXWQZ256rm:
21982 case VPMOVZXWQZ256rmk:
21983 case VPMOVZXWQZ256rmkz:
21984 case VPMOVZXWQZ256rr:
21985 case VPMOVZXWQZ256rrk:
21986 case VPMOVZXWQZ256rrkz:
21987 case VPMOVZXWQZrm:
21988 case VPMOVZXWQZrmk:
21989 case VPMOVZXWQZrmkz:
21990 case VPMOVZXWQZrr:
21991 case VPMOVZXWQZrrk:
21992 case VPMOVZXWQZrrkz:
21993 case VPMOVZXWQrm:
21994 case VPMOVZXWQrr:
21995 return true;
21996 }
21997 return false;
21998}
21999
22000bool isXORPD(unsigned Opcode) {
22001 switch (Opcode) {
22002 case XORPDrm:
22003 case XORPDrr:
22004 return true;
22005 }
22006 return false;
22007}
22008
22009bool isVMOVDQA(unsigned Opcode) {
22010 switch (Opcode) {
22011 case VMOVDQAYmr:
22012 case VMOVDQAYrm:
22013 case VMOVDQAYrr:
22014 case VMOVDQAYrr_REV:
22015 case VMOVDQAmr:
22016 case VMOVDQArm:
22017 case VMOVDQArr:
22018 case VMOVDQArr_REV:
22019 return true;
22020 }
22021 return false;
22022}
22023
22024bool isVFNMSUB213SD(unsigned Opcode) {
22025 switch (Opcode) {
22026 case VFNMSUB213SDZm_Int:
22027 case VFNMSUB213SDZmk_Int:
22028 case VFNMSUB213SDZmkz_Int:
22029 case VFNMSUB213SDZr_Int:
22030 case VFNMSUB213SDZrb_Int:
22031 case VFNMSUB213SDZrbk_Int:
22032 case VFNMSUB213SDZrbkz_Int:
22033 case VFNMSUB213SDZrk_Int:
22034 case VFNMSUB213SDZrkz_Int:
22035 case VFNMSUB213SDm_Int:
22036 case VFNMSUB213SDr_Int:
22037 return true;
22038 }
22039 return false;
22040}
22041
22042bool isVMINPS(unsigned Opcode) {
22043 switch (Opcode) {
22044 case VMINPSYrm:
22045 case VMINPSYrr:
22046 case VMINPSZ128rm:
22047 case VMINPSZ128rmb:
22048 case VMINPSZ128rmbk:
22049 case VMINPSZ128rmbkz:
22050 case VMINPSZ128rmk:
22051 case VMINPSZ128rmkz:
22052 case VMINPSZ128rr:
22053 case VMINPSZ128rrk:
22054 case VMINPSZ128rrkz:
22055 case VMINPSZ256rm:
22056 case VMINPSZ256rmb:
22057 case VMINPSZ256rmbk:
22058 case VMINPSZ256rmbkz:
22059 case VMINPSZ256rmk:
22060 case VMINPSZ256rmkz:
22061 case VMINPSZ256rr:
22062 case VMINPSZ256rrk:
22063 case VMINPSZ256rrkz:
22064 case VMINPSZrm:
22065 case VMINPSZrmb:
22066 case VMINPSZrmbk:
22067 case VMINPSZrmbkz:
22068 case VMINPSZrmk:
22069 case VMINPSZrmkz:
22070 case VMINPSZrr:
22071 case VMINPSZrrb:
22072 case VMINPSZrrbk:
22073 case VMINPSZrrbkz:
22074 case VMINPSZrrk:
22075 case VMINPSZrrkz:
22076 case VMINPSrm:
22077 case VMINPSrr:
22078 return true;
22079 }
22080 return false;
22081}
22082
22083bool isVFMSUB231PS(unsigned Opcode) {
22084 switch (Opcode) {
22085 case VFMSUB231PSYm:
22086 case VFMSUB231PSYr:
22087 case VFMSUB231PSZ128m:
22088 case VFMSUB231PSZ128mb:
22089 case VFMSUB231PSZ128mbk:
22090 case VFMSUB231PSZ128mbkz:
22091 case VFMSUB231PSZ128mk:
22092 case VFMSUB231PSZ128mkz:
22093 case VFMSUB231PSZ128r:
22094 case VFMSUB231PSZ128rk:
22095 case VFMSUB231PSZ128rkz:
22096 case VFMSUB231PSZ256m:
22097 case VFMSUB231PSZ256mb:
22098 case VFMSUB231PSZ256mbk:
22099 case VFMSUB231PSZ256mbkz:
22100 case VFMSUB231PSZ256mk:
22101 case VFMSUB231PSZ256mkz:
22102 case VFMSUB231PSZ256r:
22103 case VFMSUB231PSZ256rk:
22104 case VFMSUB231PSZ256rkz:
22105 case VFMSUB231PSZm:
22106 case VFMSUB231PSZmb:
22107 case VFMSUB231PSZmbk:
22108 case VFMSUB231PSZmbkz:
22109 case VFMSUB231PSZmk:
22110 case VFMSUB231PSZmkz:
22111 case VFMSUB231PSZr:
22112 case VFMSUB231PSZrb:
22113 case VFMSUB231PSZrbk:
22114 case VFMSUB231PSZrbkz:
22115 case VFMSUB231PSZrk:
22116 case VFMSUB231PSZrkz:
22117 case VFMSUB231PSm:
22118 case VFMSUB231PSr:
22119 return true;
22120 }
22121 return false;
22122}
22123
22124bool isVPCOMPRESSB(unsigned Opcode) {
22125 switch (Opcode) {
22126 case VPCOMPRESSBZ128mr:
22127 case VPCOMPRESSBZ128mrk:
22128 case VPCOMPRESSBZ128rr:
22129 case VPCOMPRESSBZ128rrk:
22130 case VPCOMPRESSBZ128rrkz:
22131 case VPCOMPRESSBZ256mr:
22132 case VPCOMPRESSBZ256mrk:
22133 case VPCOMPRESSBZ256rr:
22134 case VPCOMPRESSBZ256rrk:
22135 case VPCOMPRESSBZ256rrkz:
22136 case VPCOMPRESSBZmr:
22137 case VPCOMPRESSBZmrk:
22138 case VPCOMPRESSBZrr:
22139 case VPCOMPRESSBZrrk:
22140 case VPCOMPRESSBZrrkz:
22141 return true;
22142 }
22143 return false;
22144}
22145
22146bool isVPCMPEQQ(unsigned Opcode) {
22147 switch (Opcode) {
22148 case VPCMPEQQYrm:
22149 case VPCMPEQQYrr:
22150 case VPCMPEQQZ128rm:
22151 case VPCMPEQQZ128rmb:
22152 case VPCMPEQQZ128rmbk:
22153 case VPCMPEQQZ128rmk:
22154 case VPCMPEQQZ128rr:
22155 case VPCMPEQQZ128rrk:
22156 case VPCMPEQQZ256rm:
22157 case VPCMPEQQZ256rmb:
22158 case VPCMPEQQZ256rmbk:
22159 case VPCMPEQQZ256rmk:
22160 case VPCMPEQQZ256rr:
22161 case VPCMPEQQZ256rrk:
22162 case VPCMPEQQZrm:
22163 case VPCMPEQQZrmb:
22164 case VPCMPEQQZrmbk:
22165 case VPCMPEQQZrmk:
22166 case VPCMPEQQZrr:
22167 case VPCMPEQQZrrk:
22168 case VPCMPEQQrm:
22169 case VPCMPEQQrr:
22170 return true;
22171 }
22172 return false;
22173}
22174
22175bool isVRCPSS(unsigned Opcode) {
22176 switch (Opcode) {
22177 case VRCPSSm_Int:
22178 case VRCPSSr_Int:
22179 return true;
22180 }
22181 return false;
22182}
22183
22184bool isVSCATTERPF1DPS(unsigned Opcode) {
22185 return Opcode == VSCATTERPF1DPSm;
22186}
22187
22188bool isVPHADDUBW(unsigned Opcode) {
22189 switch (Opcode) {
22190 case VPHADDUBWrm:
22191 case VPHADDUBWrr:
22192 return true;
22193 }
22194 return false;
22195}
22196
22197bool isVSUBPD(unsigned Opcode) {
22198 switch (Opcode) {
22199 case VSUBPDYrm:
22200 case VSUBPDYrr:
22201 case VSUBPDZ128rm:
22202 case VSUBPDZ128rmb:
22203 case VSUBPDZ128rmbk:
22204 case VSUBPDZ128rmbkz:
22205 case VSUBPDZ128rmk:
22206 case VSUBPDZ128rmkz:
22207 case VSUBPDZ128rr:
22208 case VSUBPDZ128rrk:
22209 case VSUBPDZ128rrkz:
22210 case VSUBPDZ256rm:
22211 case VSUBPDZ256rmb:
22212 case VSUBPDZ256rmbk:
22213 case VSUBPDZ256rmbkz:
22214 case VSUBPDZ256rmk:
22215 case VSUBPDZ256rmkz:
22216 case VSUBPDZ256rr:
22217 case VSUBPDZ256rrk:
22218 case VSUBPDZ256rrkz:
22219 case VSUBPDZrm:
22220 case VSUBPDZrmb:
22221 case VSUBPDZrmbk:
22222 case VSUBPDZrmbkz:
22223 case VSUBPDZrmk:
22224 case VSUBPDZrmkz:
22225 case VSUBPDZrr:
22226 case VSUBPDZrrb:
22227 case VSUBPDZrrbk:
22228 case VSUBPDZrrbkz:
22229 case VSUBPDZrrk:
22230 case VSUBPDZrrkz:
22231 case VSUBPDrm:
22232 case VSUBPDrr:
22233 return true;
22234 }
22235 return false;
22236}
22237
22238bool isVPSCATTERQQ(unsigned Opcode) {
22239 switch (Opcode) {
22240 case VPSCATTERQQZ128mr:
22241 case VPSCATTERQQZ256mr:
22242 case VPSCATTERQQZmr:
22243 return true;
22244 }
22245 return false;
22246}
22247
22248bool isVCVTW2PH(unsigned Opcode) {
22249 switch (Opcode) {
22250 case VCVTW2PHZ128rm:
22251 case VCVTW2PHZ128rmb:
22252 case VCVTW2PHZ128rmbk:
22253 case VCVTW2PHZ128rmbkz:
22254 case VCVTW2PHZ128rmk:
22255 case VCVTW2PHZ128rmkz:
22256 case VCVTW2PHZ128rr:
22257 case VCVTW2PHZ128rrk:
22258 case VCVTW2PHZ128rrkz:
22259 case VCVTW2PHZ256rm:
22260 case VCVTW2PHZ256rmb:
22261 case VCVTW2PHZ256rmbk:
22262 case VCVTW2PHZ256rmbkz:
22263 case VCVTW2PHZ256rmk:
22264 case VCVTW2PHZ256rmkz:
22265 case VCVTW2PHZ256rr:
22266 case VCVTW2PHZ256rrk:
22267 case VCVTW2PHZ256rrkz:
22268 case VCVTW2PHZrm:
22269 case VCVTW2PHZrmb:
22270 case VCVTW2PHZrmbk:
22271 case VCVTW2PHZrmbkz:
22272 case VCVTW2PHZrmk:
22273 case VCVTW2PHZrmkz:
22274 case VCVTW2PHZrr:
22275 case VCVTW2PHZrrb:
22276 case VCVTW2PHZrrbk:
22277 case VCVTW2PHZrrbkz:
22278 case VCVTW2PHZrrk:
22279 case VCVTW2PHZrrkz:
22280 return true;
22281 }
22282 return false;
22283}
22284
22285bool isVFMADDCPH(unsigned Opcode) {
22286 switch (Opcode) {
22287 case VFMADDCPHZ128m:
22288 case VFMADDCPHZ128mb:
22289 case VFMADDCPHZ128mbk:
22290 case VFMADDCPHZ128mbkz:
22291 case VFMADDCPHZ128mk:
22292 case VFMADDCPHZ128mkz:
22293 case VFMADDCPHZ128r:
22294 case VFMADDCPHZ128rk:
22295 case VFMADDCPHZ128rkz:
22296 case VFMADDCPHZ256m:
22297 case VFMADDCPHZ256mb:
22298 case VFMADDCPHZ256mbk:
22299 case VFMADDCPHZ256mbkz:
22300 case VFMADDCPHZ256mk:
22301 case VFMADDCPHZ256mkz:
22302 case VFMADDCPHZ256r:
22303 case VFMADDCPHZ256rk:
22304 case VFMADDCPHZ256rkz:
22305 case VFMADDCPHZm:
22306 case VFMADDCPHZmb:
22307 case VFMADDCPHZmbk:
22308 case VFMADDCPHZmbkz:
22309 case VFMADDCPHZmk:
22310 case VFMADDCPHZmkz:
22311 case VFMADDCPHZr:
22312 case VFMADDCPHZrb:
22313 case VFMADDCPHZrbk:
22314 case VFMADDCPHZrbkz:
22315 case VFMADDCPHZrk:
22316 case VFMADDCPHZrkz:
22317 return true;
22318 }
22319 return false;
22320}
22321
22322bool isVPACKUSDW(unsigned Opcode) {
22323 switch (Opcode) {
22324 case VPACKUSDWYrm:
22325 case VPACKUSDWYrr:
22326 case VPACKUSDWZ128rm:
22327 case VPACKUSDWZ128rmb:
22328 case VPACKUSDWZ128rmbk:
22329 case VPACKUSDWZ128rmbkz:
22330 case VPACKUSDWZ128rmk:
22331 case VPACKUSDWZ128rmkz:
22332 case VPACKUSDWZ128rr:
22333 case VPACKUSDWZ128rrk:
22334 case VPACKUSDWZ128rrkz:
22335 case VPACKUSDWZ256rm:
22336 case VPACKUSDWZ256rmb:
22337 case VPACKUSDWZ256rmbk:
22338 case VPACKUSDWZ256rmbkz:
22339 case VPACKUSDWZ256rmk:
22340 case VPACKUSDWZ256rmkz:
22341 case VPACKUSDWZ256rr:
22342 case VPACKUSDWZ256rrk:
22343 case VPACKUSDWZ256rrkz:
22344 case VPACKUSDWZrm:
22345 case VPACKUSDWZrmb:
22346 case VPACKUSDWZrmbk:
22347 case VPACKUSDWZrmbkz:
22348 case VPACKUSDWZrmk:
22349 case VPACKUSDWZrmkz:
22350 case VPACKUSDWZrr:
22351 case VPACKUSDWZrrk:
22352 case VPACKUSDWZrrkz:
22353 case VPACKUSDWrm:
22354 case VPACKUSDWrr:
22355 return true;
22356 }
22357 return false;
22358}
22359
22360bool isVSCALEFSS(unsigned Opcode) {
22361 switch (Opcode) {
22362 case VSCALEFSSZrm:
22363 case VSCALEFSSZrmk:
22364 case VSCALEFSSZrmkz:
22365 case VSCALEFSSZrr:
22366 case VSCALEFSSZrrb_Int:
22367 case VSCALEFSSZrrbk_Int:
22368 case VSCALEFSSZrrbkz_Int:
22369 case VSCALEFSSZrrk:
22370 case VSCALEFSSZrrkz:
22371 return true;
22372 }
22373 return false;
22374}
22375
22376bool isAESIMC(unsigned Opcode) {
22377 switch (Opcode) {
22378 case AESIMCrm:
22379 case AESIMCrr:
22380 return true;
22381 }
22382 return false;
22383}
22384
22385bool isVRCP28PS(unsigned Opcode) {
22386 switch (Opcode) {
22387 case VRCP28PSZm:
22388 case VRCP28PSZmb:
22389 case VRCP28PSZmbk:
22390 case VRCP28PSZmbkz:
22391 case VRCP28PSZmk:
22392 case VRCP28PSZmkz:
22393 case VRCP28PSZr:
22394 case VRCP28PSZrb:
22395 case VRCP28PSZrbk:
22396 case VRCP28PSZrbkz:
22397 case VRCP28PSZrk:
22398 case VRCP28PSZrkz:
22399 return true;
22400 }
22401 return false;
22402}
22403
22404bool isAAND(unsigned Opcode) {
22405 switch (Opcode) {
22406 case AAND32mr:
22407 case AAND32mr_EVEX:
22408 case AAND64mr:
22409 case AAND64mr_EVEX:
22410 return true;
22411 }
22412 return false;
22413}
22414
22415bool isDAA(unsigned Opcode) {
22416 return Opcode == DAA;
22417}
22418
22419bool isKTESTW(unsigned Opcode) {
22420 return Opcode == KTESTWkk;
22421}
22422
22423bool isVCVTPD2UDQ(unsigned Opcode) {
22424 switch (Opcode) {
22425 case VCVTPD2UDQZ128rm:
22426 case VCVTPD2UDQZ128rmb:
22427 case VCVTPD2UDQZ128rmbk:
22428 case VCVTPD2UDQZ128rmbkz:
22429 case VCVTPD2UDQZ128rmk:
22430 case VCVTPD2UDQZ128rmkz:
22431 case VCVTPD2UDQZ128rr:
22432 case VCVTPD2UDQZ128rrk:
22433 case VCVTPD2UDQZ128rrkz:
22434 case VCVTPD2UDQZ256rm:
22435 case VCVTPD2UDQZ256rmb:
22436 case VCVTPD2UDQZ256rmbk:
22437 case VCVTPD2UDQZ256rmbkz:
22438 case VCVTPD2UDQZ256rmk:
22439 case VCVTPD2UDQZ256rmkz:
22440 case VCVTPD2UDQZ256rr:
22441 case VCVTPD2UDQZ256rrk:
22442 case VCVTPD2UDQZ256rrkz:
22443 case VCVTPD2UDQZrm:
22444 case VCVTPD2UDQZrmb:
22445 case VCVTPD2UDQZrmbk:
22446 case VCVTPD2UDQZrmbkz:
22447 case VCVTPD2UDQZrmk:
22448 case VCVTPD2UDQZrmkz:
22449 case VCVTPD2UDQZrr:
22450 case VCVTPD2UDQZrrb:
22451 case VCVTPD2UDQZrrbk:
22452 case VCVTPD2UDQZrrbkz:
22453 case VCVTPD2UDQZrrk:
22454 case VCVTPD2UDQZrrkz:
22455 return true;
22456 }
22457 return false;
22458}
22459
22460bool isVPADDQ(unsigned Opcode) {
22461 switch (Opcode) {
22462 case VPADDQYrm:
22463 case VPADDQYrr:
22464 case VPADDQZ128rm:
22465 case VPADDQZ128rmb:
22466 case VPADDQZ128rmbk:
22467 case VPADDQZ128rmbkz:
22468 case VPADDQZ128rmk:
22469 case VPADDQZ128rmkz:
22470 case VPADDQZ128rr:
22471 case VPADDQZ128rrk:
22472 case VPADDQZ128rrkz:
22473 case VPADDQZ256rm:
22474 case VPADDQZ256rmb:
22475 case VPADDQZ256rmbk:
22476 case VPADDQZ256rmbkz:
22477 case VPADDQZ256rmk:
22478 case VPADDQZ256rmkz:
22479 case VPADDQZ256rr:
22480 case VPADDQZ256rrk:
22481 case VPADDQZ256rrkz:
22482 case VPADDQZrm:
22483 case VPADDQZrmb:
22484 case VPADDQZrmbk:
22485 case VPADDQZrmbkz:
22486 case VPADDQZrmk:
22487 case VPADDQZrmkz:
22488 case VPADDQZrr:
22489 case VPADDQZrrk:
22490 case VPADDQZrrkz:
22491 case VPADDQrm:
22492 case VPADDQrr:
22493 return true;
22494 }
22495 return false;
22496}
22497
22498bool isPALIGNR(unsigned Opcode) {
22499 switch (Opcode) {
22500 case MMX_PALIGNRrmi:
22501 case MMX_PALIGNRrri:
22502 case PALIGNRrmi:
22503 case PALIGNRrri:
22504 return true;
22505 }
22506 return false;
22507}
22508
22509bool isPMAXUW(unsigned Opcode) {
22510 switch (Opcode) {
22511 case PMAXUWrm:
22512 case PMAXUWrr:
22513 return true;
22514 }
22515 return false;
22516}
22517
22518bool isVFMADDSD(unsigned Opcode) {
22519 switch (Opcode) {
22520 case VFMADDSD4mr:
22521 case VFMADDSD4rm:
22522 case VFMADDSD4rr:
22523 case VFMADDSD4rr_REV:
22524 return true;
22525 }
22526 return false;
22527}
22528
22529bool isPFMAX(unsigned Opcode) {
22530 switch (Opcode) {
22531 case PFMAXrm:
22532 case PFMAXrr:
22533 return true;
22534 }
22535 return false;
22536}
22537
22538bool isVPOR(unsigned Opcode) {
22539 switch (Opcode) {
22540 case VPORYrm:
22541 case VPORYrr:
22542 case VPORrm:
22543 case VPORrr:
22544 return true;
22545 }
22546 return false;
22547}
22548
22549bool isVPSUBB(unsigned Opcode) {
22550 switch (Opcode) {
22551 case VPSUBBYrm:
22552 case VPSUBBYrr:
22553 case VPSUBBZ128rm:
22554 case VPSUBBZ128rmk:
22555 case VPSUBBZ128rmkz:
22556 case VPSUBBZ128rr:
22557 case VPSUBBZ128rrk:
22558 case VPSUBBZ128rrkz:
22559 case VPSUBBZ256rm:
22560 case VPSUBBZ256rmk:
22561 case VPSUBBZ256rmkz:
22562 case VPSUBBZ256rr:
22563 case VPSUBBZ256rrk:
22564 case VPSUBBZ256rrkz:
22565 case VPSUBBZrm:
22566 case VPSUBBZrmk:
22567 case VPSUBBZrmkz:
22568 case VPSUBBZrr:
22569 case VPSUBBZrrk:
22570 case VPSUBBZrrkz:
22571 case VPSUBBrm:
22572 case VPSUBBrr:
22573 return true;
22574 }
22575 return false;
22576}
22577
22578bool isVPAVGB(unsigned Opcode) {
22579 switch (Opcode) {
22580 case VPAVGBYrm:
22581 case VPAVGBYrr:
22582 case VPAVGBZ128rm:
22583 case VPAVGBZ128rmk:
22584 case VPAVGBZ128rmkz:
22585 case VPAVGBZ128rr:
22586 case VPAVGBZ128rrk:
22587 case VPAVGBZ128rrkz:
22588 case VPAVGBZ256rm:
22589 case VPAVGBZ256rmk:
22590 case VPAVGBZ256rmkz:
22591 case VPAVGBZ256rr:
22592 case VPAVGBZ256rrk:
22593 case VPAVGBZ256rrkz:
22594 case VPAVGBZrm:
22595 case VPAVGBZrmk:
22596 case VPAVGBZrmkz:
22597 case VPAVGBZrr:
22598 case VPAVGBZrrk:
22599 case VPAVGBZrrkz:
22600 case VPAVGBrm:
22601 case VPAVGBrr:
22602 return true;
22603 }
22604 return false;
22605}
22606
22607bool isINSB(unsigned Opcode) {
22608 return Opcode == INSB;
22609}
22610
22611bool isFYL2X(unsigned Opcode) {
22612 return Opcode == FYL2X;
22613}
22614
22615bool isVFNMSUB132PD(unsigned Opcode) {
22616 switch (Opcode) {
22617 case VFNMSUB132PDYm:
22618 case VFNMSUB132PDYr:
22619 case VFNMSUB132PDZ128m:
22620 case VFNMSUB132PDZ128mb:
22621 case VFNMSUB132PDZ128mbk:
22622 case VFNMSUB132PDZ128mbkz:
22623 case VFNMSUB132PDZ128mk:
22624 case VFNMSUB132PDZ128mkz:
22625 case VFNMSUB132PDZ128r:
22626 case VFNMSUB132PDZ128rk:
22627 case VFNMSUB132PDZ128rkz:
22628 case VFNMSUB132PDZ256m:
22629 case VFNMSUB132PDZ256mb:
22630 case VFNMSUB132PDZ256mbk:
22631 case VFNMSUB132PDZ256mbkz:
22632 case VFNMSUB132PDZ256mk:
22633 case VFNMSUB132PDZ256mkz:
22634 case VFNMSUB132PDZ256r:
22635 case VFNMSUB132PDZ256rk:
22636 case VFNMSUB132PDZ256rkz:
22637 case VFNMSUB132PDZm:
22638 case VFNMSUB132PDZmb:
22639 case VFNMSUB132PDZmbk:
22640 case VFNMSUB132PDZmbkz:
22641 case VFNMSUB132PDZmk:
22642 case VFNMSUB132PDZmkz:
22643 case VFNMSUB132PDZr:
22644 case VFNMSUB132PDZrb:
22645 case VFNMSUB132PDZrbk:
22646 case VFNMSUB132PDZrbkz:
22647 case VFNMSUB132PDZrk:
22648 case VFNMSUB132PDZrkz:
22649 case VFNMSUB132PDm:
22650 case VFNMSUB132PDr:
22651 return true;
22652 }
22653 return false;
22654}
22655
22656bool isVFNMSUBPS(unsigned Opcode) {
22657 switch (Opcode) {
22658 case VFNMSUBPS4Ymr:
22659 case VFNMSUBPS4Yrm:
22660 case VFNMSUBPS4Yrr:
22661 case VFNMSUBPS4Yrr_REV:
22662 case VFNMSUBPS4mr:
22663 case VFNMSUBPS4rm:
22664 case VFNMSUBPS4rr:
22665 case VFNMSUBPS4rr_REV:
22666 return true;
22667 }
22668 return false;
22669}
22670
22671bool isVFMADD231PS(unsigned Opcode) {
22672 switch (Opcode) {
22673 case VFMADD231PSYm:
22674 case VFMADD231PSYr:
22675 case VFMADD231PSZ128m:
22676 case VFMADD231PSZ128mb:
22677 case VFMADD231PSZ128mbk:
22678 case VFMADD231PSZ128mbkz:
22679 case VFMADD231PSZ128mk:
22680 case VFMADD231PSZ128mkz:
22681 case VFMADD231PSZ128r:
22682 case VFMADD231PSZ128rk:
22683 case VFMADD231PSZ128rkz:
22684 case VFMADD231PSZ256m:
22685 case VFMADD231PSZ256mb:
22686 case VFMADD231PSZ256mbk:
22687 case VFMADD231PSZ256mbkz:
22688 case VFMADD231PSZ256mk:
22689 case VFMADD231PSZ256mkz:
22690 case VFMADD231PSZ256r:
22691 case VFMADD231PSZ256rk:
22692 case VFMADD231PSZ256rkz:
22693 case VFMADD231PSZm:
22694 case VFMADD231PSZmb:
22695 case VFMADD231PSZmbk:
22696 case VFMADD231PSZmbkz:
22697 case VFMADD231PSZmk:
22698 case VFMADD231PSZmkz:
22699 case VFMADD231PSZr:
22700 case VFMADD231PSZrb:
22701 case VFMADD231PSZrbk:
22702 case VFMADD231PSZrbkz:
22703 case VFMADD231PSZrk:
22704 case VFMADD231PSZrkz:
22705 case VFMADD231PSm:
22706 case VFMADD231PSr:
22707 return true;
22708 }
22709 return false;
22710}
22711
22712bool isVCVTTSS2SI(unsigned Opcode) {
22713 switch (Opcode) {
22714 case VCVTTSS2SI64Zrm_Int:
22715 case VCVTTSS2SI64Zrr_Int:
22716 case VCVTTSS2SI64Zrrb_Int:
22717 case VCVTTSS2SI64rm_Int:
22718 case VCVTTSS2SI64rr_Int:
22719 case VCVTTSS2SIZrm_Int:
22720 case VCVTTSS2SIZrr_Int:
22721 case VCVTTSS2SIZrrb_Int:
22722 case VCVTTSS2SIrm_Int:
22723 case VCVTTSS2SIrr_Int:
22724 return true;
22725 }
22726 return false;
22727}
22728
22729bool isTCMMRLFP16PS(unsigned Opcode) {
22730 return Opcode == TCMMRLFP16PS;
22731}
22732
22733bool isFCOMPP(unsigned Opcode) {
22734 return Opcode == FCOMPP;
22735}
22736
22737bool isMOVD(unsigned Opcode) {
22738 switch (Opcode) {
22739 case MMX_MOVD64grr:
22740 case MMX_MOVD64mr:
22741 case MMX_MOVD64rm:
22742 case MMX_MOVD64rr:
22743 case MOVDI2PDIrm:
22744 case MOVDI2PDIrr:
22745 case MOVPDI2DImr:
22746 case MOVPDI2DIrr:
22747 return true;
22748 }
22749 return false;
22750}
22751
22752bool isMOVBE(unsigned Opcode) {
22753 switch (Opcode) {
22754 case MOVBE16mr:
22755 case MOVBE16mr_EVEX:
22756 case MOVBE16rm:
22757 case MOVBE16rm_EVEX:
22758 case MOVBE16rr:
22759 case MOVBE16rr_REV:
22760 case MOVBE32mr:
22761 case MOVBE32mr_EVEX:
22762 case MOVBE32rm:
22763 case MOVBE32rm_EVEX:
22764 case MOVBE32rr:
22765 case MOVBE32rr_REV:
22766 case MOVBE64mr:
22767 case MOVBE64mr_EVEX:
22768 case MOVBE64rm:
22769 case MOVBE64rm_EVEX:
22770 case MOVBE64rr:
22771 case MOVBE64rr_REV:
22772 return true;
22773 }
22774 return false;
22775}
22776
22777bool isVP2INTERSECTD(unsigned Opcode) {
22778 switch (Opcode) {
22779 case VP2INTERSECTDZ128rm:
22780 case VP2INTERSECTDZ128rmb:
22781 case VP2INTERSECTDZ128rr:
22782 case VP2INTERSECTDZ256rm:
22783 case VP2INTERSECTDZ256rmb:
22784 case VP2INTERSECTDZ256rr:
22785 case VP2INTERSECTDZrm:
22786 case VP2INTERSECTDZrmb:
22787 case VP2INTERSECTDZrr:
22788 return true;
22789 }
22790 return false;
22791}
22792
22793bool isVPMULLQ(unsigned Opcode) {
22794 switch (Opcode) {
22795 case VPMULLQZ128rm:
22796 case VPMULLQZ128rmb:
22797 case VPMULLQZ128rmbk:
22798 case VPMULLQZ128rmbkz:
22799 case VPMULLQZ128rmk:
22800 case VPMULLQZ128rmkz:
22801 case VPMULLQZ128rr:
22802 case VPMULLQZ128rrk:
22803 case VPMULLQZ128rrkz:
22804 case VPMULLQZ256rm:
22805 case VPMULLQZ256rmb:
22806 case VPMULLQZ256rmbk:
22807 case VPMULLQZ256rmbkz:
22808 case VPMULLQZ256rmk:
22809 case VPMULLQZ256rmkz:
22810 case VPMULLQZ256rr:
22811 case VPMULLQZ256rrk:
22812 case VPMULLQZ256rrkz:
22813 case VPMULLQZrm:
22814 case VPMULLQZrmb:
22815 case VPMULLQZrmbk:
22816 case VPMULLQZrmbkz:
22817 case VPMULLQZrmk:
22818 case VPMULLQZrmkz:
22819 case VPMULLQZrr:
22820 case VPMULLQZrrk:
22821 case VPMULLQZrrkz:
22822 return true;
22823 }
22824 return false;
22825}
22826
22827bool isVSCALEFPS(unsigned Opcode) {
22828 switch (Opcode) {
22829 case VSCALEFPSZ128rm:
22830 case VSCALEFPSZ128rmb:
22831 case VSCALEFPSZ128rmbk:
22832 case VSCALEFPSZ128rmbkz:
22833 case VSCALEFPSZ128rmk:
22834 case VSCALEFPSZ128rmkz:
22835 case VSCALEFPSZ128rr:
22836 case VSCALEFPSZ128rrk:
22837 case VSCALEFPSZ128rrkz:
22838 case VSCALEFPSZ256rm:
22839 case VSCALEFPSZ256rmb:
22840 case VSCALEFPSZ256rmbk:
22841 case VSCALEFPSZ256rmbkz:
22842 case VSCALEFPSZ256rmk:
22843 case VSCALEFPSZ256rmkz:
22844 case VSCALEFPSZ256rr:
22845 case VSCALEFPSZ256rrk:
22846 case VSCALEFPSZ256rrkz:
22847 case VSCALEFPSZrm:
22848 case VSCALEFPSZrmb:
22849 case VSCALEFPSZrmbk:
22850 case VSCALEFPSZrmbkz:
22851 case VSCALEFPSZrmk:
22852 case VSCALEFPSZrmkz:
22853 case VSCALEFPSZrr:
22854 case VSCALEFPSZrrb:
22855 case VSCALEFPSZrrbk:
22856 case VSCALEFPSZrrbkz:
22857 case VSCALEFPSZrrk:
22858 case VSCALEFPSZrrkz:
22859 return true;
22860 }
22861 return false;
22862}
22863
22864bool isVPMACSDQH(unsigned Opcode) {
22865 switch (Opcode) {
22866 case VPMACSDQHrm:
22867 case VPMACSDQHrr:
22868 return true;
22869 }
22870 return false;
22871}
22872
22873bool isVPTESTNMD(unsigned Opcode) {
22874 switch (Opcode) {
22875 case VPTESTNMDZ128rm:
22876 case VPTESTNMDZ128rmb:
22877 case VPTESTNMDZ128rmbk:
22878 case VPTESTNMDZ128rmk:
22879 case VPTESTNMDZ128rr:
22880 case VPTESTNMDZ128rrk:
22881 case VPTESTNMDZ256rm:
22882 case VPTESTNMDZ256rmb:
22883 case VPTESTNMDZ256rmbk:
22884 case VPTESTNMDZ256rmk:
22885 case VPTESTNMDZ256rr:
22886 case VPTESTNMDZ256rrk:
22887 case VPTESTNMDZrm:
22888 case VPTESTNMDZrmb:
22889 case VPTESTNMDZrmbk:
22890 case VPTESTNMDZrmk:
22891 case VPTESTNMDZrr:
22892 case VPTESTNMDZrrk:
22893 return true;
22894 }
22895 return false;
22896}
22897
22898bool isFCOMP(unsigned Opcode) {
22899 switch (Opcode) {
22900 case COMP_FST0r:
22901 case FCOMP32m:
22902 case FCOMP64m:
22903 return true;
22904 }
22905 return false;
22906}
22907
22908bool isPREFETCHWT1(unsigned Opcode) {
22909 return Opcode == PREFETCHWT1;
22910}
22911
22912bool isVCMPSD(unsigned Opcode) {
22913 switch (Opcode) {
22914 case VCMPSDZrmi_Int:
22915 case VCMPSDZrmik_Int:
22916 case VCMPSDZrri_Int:
22917 case VCMPSDZrrib_Int:
22918 case VCMPSDZrribk_Int:
22919 case VCMPSDZrrik_Int:
22920 case VCMPSDrmi_Int:
22921 case VCMPSDrri_Int:
22922 return true;
22923 }
22924 return false;
22925}
22926
22927bool isSGDTD(unsigned Opcode) {
22928 return Opcode == SGDT32m;
22929}
22930
22931bool isWRUSSD(unsigned Opcode) {
22932 switch (Opcode) {
22933 case WRUSSD:
22934 case WRUSSD_EVEX:
22935 return true;
22936 }
22937 return false;
22938}
22939
22940bool isFSUBP(unsigned Opcode) {
22941 return Opcode == SUB_FPrST0;
22942}
22943
22944bool isVUNPCKLPS(unsigned Opcode) {
22945 switch (Opcode) {
22946 case VUNPCKLPSYrm:
22947 case VUNPCKLPSYrr:
22948 case VUNPCKLPSZ128rm:
22949 case VUNPCKLPSZ128rmb:
22950 case VUNPCKLPSZ128rmbk:
22951 case VUNPCKLPSZ128rmbkz:
22952 case VUNPCKLPSZ128rmk:
22953 case VUNPCKLPSZ128rmkz:
22954 case VUNPCKLPSZ128rr:
22955 case VUNPCKLPSZ128rrk:
22956 case VUNPCKLPSZ128rrkz:
22957 case VUNPCKLPSZ256rm:
22958 case VUNPCKLPSZ256rmb:
22959 case VUNPCKLPSZ256rmbk:
22960 case VUNPCKLPSZ256rmbkz:
22961 case VUNPCKLPSZ256rmk:
22962 case VUNPCKLPSZ256rmkz:
22963 case VUNPCKLPSZ256rr:
22964 case VUNPCKLPSZ256rrk:
22965 case VUNPCKLPSZ256rrkz:
22966 case VUNPCKLPSZrm:
22967 case VUNPCKLPSZrmb:
22968 case VUNPCKLPSZrmbk:
22969 case VUNPCKLPSZrmbkz:
22970 case VUNPCKLPSZrmk:
22971 case VUNPCKLPSZrmkz:
22972 case VUNPCKLPSZrr:
22973 case VUNPCKLPSZrrk:
22974 case VUNPCKLPSZrrkz:
22975 case VUNPCKLPSrm:
22976 case VUNPCKLPSrr:
22977 return true;
22978 }
22979 return false;
22980}
22981
22982bool isVBMACXOR16X16X16(unsigned Opcode) {
22983 switch (Opcode) {
22984 case VBMACXORZ256rm:
22985 case VBMACXORZ256rmb:
22986 case VBMACXORZ256rmbk:
22987 case VBMACXORZ256rmbkz:
22988 case VBMACXORZ256rmk:
22989 case VBMACXORZ256rmkz:
22990 case VBMACXORZ256rr:
22991 case VBMACXORZ256rrk:
22992 case VBMACXORZ256rrkz:
22993 case VBMACXORZrm:
22994 case VBMACXORZrmb:
22995 case VBMACXORZrmbk:
22996 case VBMACXORZrmbkz:
22997 case VBMACXORZrmk:
22998 case VBMACXORZrmkz:
22999 case VBMACXORZrr:
23000 case VBMACXORZrrk:
23001 case VBMACXORZrrkz:
23002 return true;
23003 }
23004 return false;
23005}
23006
23007bool isVFNMSUB213SS(unsigned Opcode) {
23008 switch (Opcode) {
23009 case VFNMSUB213SSZm_Int:
23010 case VFNMSUB213SSZmk_Int:
23011 case VFNMSUB213SSZmkz_Int:
23012 case VFNMSUB213SSZr_Int:
23013 case VFNMSUB213SSZrb_Int:
23014 case VFNMSUB213SSZrbk_Int:
23015 case VFNMSUB213SSZrbkz_Int:
23016 case VFNMSUB213SSZrk_Int:
23017 case VFNMSUB213SSZrkz_Int:
23018 case VFNMSUB213SSm_Int:
23019 case VFNMSUB213SSr_Int:
23020 return true;
23021 }
23022 return false;
23023}
23024
23025bool isROUNDPD(unsigned Opcode) {
23026 switch (Opcode) {
23027 case ROUNDPDmi:
23028 case ROUNDPDri:
23029 return true;
23030 }
23031 return false;
23032}
23033
23034bool isVPMAXSW(unsigned Opcode) {
23035 switch (Opcode) {
23036 case VPMAXSWYrm:
23037 case VPMAXSWYrr:
23038 case VPMAXSWZ128rm:
23039 case VPMAXSWZ128rmk:
23040 case VPMAXSWZ128rmkz:
23041 case VPMAXSWZ128rr:
23042 case VPMAXSWZ128rrk:
23043 case VPMAXSWZ128rrkz:
23044 case VPMAXSWZ256rm:
23045 case VPMAXSWZ256rmk:
23046 case VPMAXSWZ256rmkz:
23047 case VPMAXSWZ256rr:
23048 case VPMAXSWZ256rrk:
23049 case VPMAXSWZ256rrkz:
23050 case VPMAXSWZrm:
23051 case VPMAXSWZrmk:
23052 case VPMAXSWZrmkz:
23053 case VPMAXSWZrr:
23054 case VPMAXSWZrrk:
23055 case VPMAXSWZrrkz:
23056 case VPMAXSWrm:
23057 case VPMAXSWrr:
23058 return true;
23059 }
23060 return false;
23061}
23062
23063bool isVCVTTPH2DQ(unsigned Opcode) {
23064 switch (Opcode) {
23065 case VCVTTPH2DQZ128rm:
23066 case VCVTTPH2DQZ128rmb:
23067 case VCVTTPH2DQZ128rmbk:
23068 case VCVTTPH2DQZ128rmbkz:
23069 case VCVTTPH2DQZ128rmk:
23070 case VCVTTPH2DQZ128rmkz:
23071 case VCVTTPH2DQZ128rr:
23072 case VCVTTPH2DQZ128rrk:
23073 case VCVTTPH2DQZ128rrkz:
23074 case VCVTTPH2DQZ256rm:
23075 case VCVTTPH2DQZ256rmb:
23076 case VCVTTPH2DQZ256rmbk:
23077 case VCVTTPH2DQZ256rmbkz:
23078 case VCVTTPH2DQZ256rmk:
23079 case VCVTTPH2DQZ256rmkz:
23080 case VCVTTPH2DQZ256rr:
23081 case VCVTTPH2DQZ256rrk:
23082 case VCVTTPH2DQZ256rrkz:
23083 case VCVTTPH2DQZrm:
23084 case VCVTTPH2DQZrmb:
23085 case VCVTTPH2DQZrmbk:
23086 case VCVTTPH2DQZrmbkz:
23087 case VCVTTPH2DQZrmk:
23088 case VCVTTPH2DQZrmkz:
23089 case VCVTTPH2DQZrr:
23090 case VCVTTPH2DQZrrb:
23091 case VCVTTPH2DQZrrbk:
23092 case VCVTTPH2DQZrrbkz:
23093 case VCVTTPH2DQZrrk:
23094 case VCVTTPH2DQZrrkz:
23095 return true;
23096 }
23097 return false;
23098}
23099
23100bool isVPUNPCKLWD(unsigned Opcode) {
23101 switch (Opcode) {
23102 case VPUNPCKLWDYrm:
23103 case VPUNPCKLWDYrr:
23104 case VPUNPCKLWDZ128rm:
23105 case VPUNPCKLWDZ128rmk:
23106 case VPUNPCKLWDZ128rmkz:
23107 case VPUNPCKLWDZ128rr:
23108 case VPUNPCKLWDZ128rrk:
23109 case VPUNPCKLWDZ128rrkz:
23110 case VPUNPCKLWDZ256rm:
23111 case VPUNPCKLWDZ256rmk:
23112 case VPUNPCKLWDZ256rmkz:
23113 case VPUNPCKLWDZ256rr:
23114 case VPUNPCKLWDZ256rrk:
23115 case VPUNPCKLWDZ256rrkz:
23116 case VPUNPCKLWDZrm:
23117 case VPUNPCKLWDZrmk:
23118 case VPUNPCKLWDZrmkz:
23119 case VPUNPCKLWDZrr:
23120 case VPUNPCKLWDZrrk:
23121 case VPUNPCKLWDZrrkz:
23122 case VPUNPCKLWDrm:
23123 case VPUNPCKLWDrr:
23124 return true;
23125 }
23126 return false;
23127}
23128
23129bool isKSHIFTLD(unsigned Opcode) {
23130 return Opcode == KSHIFTLDki;
23131}
23132
23133bool isTCVTROWPS2BF16H(unsigned Opcode) {
23134 switch (Opcode) {
23135 case TCVTROWPS2BF16Hrte:
23136 case TCVTROWPS2BF16Hrti:
23137 return true;
23138 }
23139 return false;
23140}
23141
23142bool isVFMADD231SD(unsigned Opcode) {
23143 switch (Opcode) {
23144 case VFMADD231SDZm_Int:
23145 case VFMADD231SDZmk_Int:
23146 case VFMADD231SDZmkz_Int:
23147 case VFMADD231SDZr_Int:
23148 case VFMADD231SDZrb_Int:
23149 case VFMADD231SDZrbk_Int:
23150 case VFMADD231SDZrbkz_Int:
23151 case VFMADD231SDZrk_Int:
23152 case VFMADD231SDZrkz_Int:
23153 case VFMADD231SDm_Int:
23154 case VFMADD231SDr_Int:
23155 return true;
23156 }
23157 return false;
23158}
23159
23160bool isADDPS(unsigned Opcode) {
23161 switch (Opcode) {
23162 case ADDPSrm:
23163 case ADDPSrr:
23164 return true;
23165 }
23166 return false;
23167}
23168
23169bool isVPSLLVD(unsigned Opcode) {
23170 switch (Opcode) {
23171 case VPSLLVDYrm:
23172 case VPSLLVDYrr:
23173 case VPSLLVDZ128rm:
23174 case VPSLLVDZ128rmb:
23175 case VPSLLVDZ128rmbk:
23176 case VPSLLVDZ128rmbkz:
23177 case VPSLLVDZ128rmk:
23178 case VPSLLVDZ128rmkz:
23179 case VPSLLVDZ128rr:
23180 case VPSLLVDZ128rrk:
23181 case VPSLLVDZ128rrkz:
23182 case VPSLLVDZ256rm:
23183 case VPSLLVDZ256rmb:
23184 case VPSLLVDZ256rmbk:
23185 case VPSLLVDZ256rmbkz:
23186 case VPSLLVDZ256rmk:
23187 case VPSLLVDZ256rmkz:
23188 case VPSLLVDZ256rr:
23189 case VPSLLVDZ256rrk:
23190 case VPSLLVDZ256rrkz:
23191 case VPSLLVDZrm:
23192 case VPSLLVDZrmb:
23193 case VPSLLVDZrmbk:
23194 case VPSLLVDZrmbkz:
23195 case VPSLLVDZrmk:
23196 case VPSLLVDZrmkz:
23197 case VPSLLVDZrr:
23198 case VPSLLVDZrrk:
23199 case VPSLLVDZrrkz:
23200 case VPSLLVDrm:
23201 case VPSLLVDrr:
23202 return true;
23203 }
23204 return false;
23205}
23206
23207bool isVFNMADD132SH(unsigned Opcode) {
23208 switch (Opcode) {
23209 case VFNMADD132SHZm_Int:
23210 case VFNMADD132SHZmk_Int:
23211 case VFNMADD132SHZmkz_Int:
23212 case VFNMADD132SHZr_Int:
23213 case VFNMADD132SHZrb_Int:
23214 case VFNMADD132SHZrbk_Int:
23215 case VFNMADD132SHZrbkz_Int:
23216 case VFNMADD132SHZrk_Int:
23217 case VFNMADD132SHZrkz_Int:
23218 return true;
23219 }
23220 return false;
23221}
23222
23223bool isVMOVNTPS(unsigned Opcode) {
23224 switch (Opcode) {
23225 case VMOVNTPSYmr:
23226 case VMOVNTPSZ128mr:
23227 case VMOVNTPSZ256mr:
23228 case VMOVNTPSZmr:
23229 case VMOVNTPSmr:
23230 return true;
23231 }
23232 return false;
23233}
23234
23235bool isVCVTPD2DQ(unsigned Opcode) {
23236 switch (Opcode) {
23237 case VCVTPD2DQYrm:
23238 case VCVTPD2DQYrr:
23239 case VCVTPD2DQZ128rm:
23240 case VCVTPD2DQZ128rmb:
23241 case VCVTPD2DQZ128rmbk:
23242 case VCVTPD2DQZ128rmbkz:
23243 case VCVTPD2DQZ128rmk:
23244 case VCVTPD2DQZ128rmkz:
23245 case VCVTPD2DQZ128rr:
23246 case VCVTPD2DQZ128rrk:
23247 case VCVTPD2DQZ128rrkz:
23248 case VCVTPD2DQZ256rm:
23249 case VCVTPD2DQZ256rmb:
23250 case VCVTPD2DQZ256rmbk:
23251 case VCVTPD2DQZ256rmbkz:
23252 case VCVTPD2DQZ256rmk:
23253 case VCVTPD2DQZ256rmkz:
23254 case VCVTPD2DQZ256rr:
23255 case VCVTPD2DQZ256rrk:
23256 case VCVTPD2DQZ256rrkz:
23257 case VCVTPD2DQZrm:
23258 case VCVTPD2DQZrmb:
23259 case VCVTPD2DQZrmbk:
23260 case VCVTPD2DQZrmbkz:
23261 case VCVTPD2DQZrmk:
23262 case VCVTPD2DQZrmkz:
23263 case VCVTPD2DQZrr:
23264 case VCVTPD2DQZrrb:
23265 case VCVTPD2DQZrrbk:
23266 case VCVTPD2DQZrrbkz:
23267 case VCVTPD2DQZrrk:
23268 case VCVTPD2DQZrrkz:
23269 case VCVTPD2DQrm:
23270 case VCVTPD2DQrr:
23271 return true;
23272 }
23273 return false;
23274}
23275
23276bool isVPXOR(unsigned Opcode) {
23277 switch (Opcode) {
23278 case VPXORYrm:
23279 case VPXORYrr:
23280 case VPXORrm:
23281 case VPXORrr:
23282 return true;
23283 }
23284 return false;
23285}
23286
23287bool isSTMXCSR(unsigned Opcode) {
23288 return Opcode == STMXCSR;
23289}
23290
23291bool isVRCP14SS(unsigned Opcode) {
23292 switch (Opcode) {
23293 case VRCP14SSZrm:
23294 case VRCP14SSZrmk:
23295 case VRCP14SSZrmkz:
23296 case VRCP14SSZrr:
23297 case VRCP14SSZrrk:
23298 case VRCP14SSZrrkz:
23299 return true;
23300 }
23301 return false;
23302}
23303
23304bool isUD2(unsigned Opcode) {
23305 return Opcode == TRAP;
23306}
23307
23308bool isVPOPCNTW(unsigned Opcode) {
23309 switch (Opcode) {
23310 case VPOPCNTWZ128rm:
23311 case VPOPCNTWZ128rmk:
23312 case VPOPCNTWZ128rmkz:
23313 case VPOPCNTWZ128rr:
23314 case VPOPCNTWZ128rrk:
23315 case VPOPCNTWZ128rrkz:
23316 case VPOPCNTWZ256rm:
23317 case VPOPCNTWZ256rmk:
23318 case VPOPCNTWZ256rmkz:
23319 case VPOPCNTWZ256rr:
23320 case VPOPCNTWZ256rrk:
23321 case VPOPCNTWZ256rrkz:
23322 case VPOPCNTWZrm:
23323 case VPOPCNTWZrmk:
23324 case VPOPCNTWZrmkz:
23325 case VPOPCNTWZrr:
23326 case VPOPCNTWZrrk:
23327 case VPOPCNTWZrrkz:
23328 return true;
23329 }
23330 return false;
23331}
23332
23333bool isVRSQRTSH(unsigned Opcode) {
23334 switch (Opcode) {
23335 case VRSQRTSHZrm:
23336 case VRSQRTSHZrmk:
23337 case VRSQRTSHZrmkz:
23338 case VRSQRTSHZrr:
23339 case VRSQRTSHZrrk:
23340 case VRSQRTSHZrrkz:
23341 return true;
23342 }
23343 return false;
23344}
23345
23346bool isVSCATTERPF0DPD(unsigned Opcode) {
23347 return Opcode == VSCATTERPF0DPDm;
23348}
23349
23350bool isVFMADDPS(unsigned Opcode) {
23351 switch (Opcode) {
23352 case VFMADDPS4Ymr:
23353 case VFMADDPS4Yrm:
23354 case VFMADDPS4Yrr:
23355 case VFMADDPS4Yrr_REV:
23356 case VFMADDPS4mr:
23357 case VFMADDPS4rm:
23358 case VFMADDPS4rr:
23359 case VFMADDPS4rr_REV:
23360 return true;
23361 }
23362 return false;
23363}
23364
23365bool isXSAVEC64(unsigned Opcode) {
23366 return Opcode == XSAVEC64;
23367}
23368
23369bool isVPMADDUBSW(unsigned Opcode) {
23370 switch (Opcode) {
23371 case VPMADDUBSWYrm:
23372 case VPMADDUBSWYrr:
23373 case VPMADDUBSWZ128rm:
23374 case VPMADDUBSWZ128rmk:
23375 case VPMADDUBSWZ128rmkz:
23376 case VPMADDUBSWZ128rr:
23377 case VPMADDUBSWZ128rrk:
23378 case VPMADDUBSWZ128rrkz:
23379 case VPMADDUBSWZ256rm:
23380 case VPMADDUBSWZ256rmk:
23381 case VPMADDUBSWZ256rmkz:
23382 case VPMADDUBSWZ256rr:
23383 case VPMADDUBSWZ256rrk:
23384 case VPMADDUBSWZ256rrkz:
23385 case VPMADDUBSWZrm:
23386 case VPMADDUBSWZrmk:
23387 case VPMADDUBSWZrmkz:
23388 case VPMADDUBSWZrr:
23389 case VPMADDUBSWZrrk:
23390 case VPMADDUBSWZrrkz:
23391 case VPMADDUBSWrm:
23392 case VPMADDUBSWrr:
23393 return true;
23394 }
23395 return false;
23396}
23397
23398bool isVPMOVZXDQ(unsigned Opcode) {
23399 switch (Opcode) {
23400 case VPMOVZXDQYrm:
23401 case VPMOVZXDQYrr:
23402 case VPMOVZXDQZ128rm:
23403 case VPMOVZXDQZ128rmk:
23404 case VPMOVZXDQZ128rmkz:
23405 case VPMOVZXDQZ128rr:
23406 case VPMOVZXDQZ128rrk:
23407 case VPMOVZXDQZ128rrkz:
23408 case VPMOVZXDQZ256rm:
23409 case VPMOVZXDQZ256rmk:
23410 case VPMOVZXDQZ256rmkz:
23411 case VPMOVZXDQZ256rr:
23412 case VPMOVZXDQZ256rrk:
23413 case VPMOVZXDQZ256rrkz:
23414 case VPMOVZXDQZrm:
23415 case VPMOVZXDQZrmk:
23416 case VPMOVZXDQZrmkz:
23417 case VPMOVZXDQZrr:
23418 case VPMOVZXDQZrrk:
23419 case VPMOVZXDQZrrkz:
23420 case VPMOVZXDQrm:
23421 case VPMOVZXDQrr:
23422 return true;
23423 }
23424 return false;
23425}
23426
23427bool isVRCP14PS(unsigned Opcode) {
23428 switch (Opcode) {
23429 case VRCP14PSZ128m:
23430 case VRCP14PSZ128mb:
23431 case VRCP14PSZ128mbk:
23432 case VRCP14PSZ128mbkz:
23433 case VRCP14PSZ128mk:
23434 case VRCP14PSZ128mkz:
23435 case VRCP14PSZ128r:
23436 case VRCP14PSZ128rk:
23437 case VRCP14PSZ128rkz:
23438 case VRCP14PSZ256m:
23439 case VRCP14PSZ256mb:
23440 case VRCP14PSZ256mbk:
23441 case VRCP14PSZ256mbkz:
23442 case VRCP14PSZ256mk:
23443 case VRCP14PSZ256mkz:
23444 case VRCP14PSZ256r:
23445 case VRCP14PSZ256rk:
23446 case VRCP14PSZ256rkz:
23447 case VRCP14PSZm:
23448 case VRCP14PSZmb:
23449 case VRCP14PSZmbk:
23450 case VRCP14PSZmbkz:
23451 case VRCP14PSZmk:
23452 case VRCP14PSZmkz:
23453 case VRCP14PSZr:
23454 case VRCP14PSZrk:
23455 case VRCP14PSZrkz:
23456 return true;
23457 }
23458 return false;
23459}
23460
23461bool isVSQRTSH(unsigned Opcode) {
23462 switch (Opcode) {
23463 case VSQRTSHZm_Int:
23464 case VSQRTSHZmk_Int:
23465 case VSQRTSHZmkz_Int:
23466 case VSQRTSHZr_Int:
23467 case VSQRTSHZrb_Int:
23468 case VSQRTSHZrbk_Int:
23469 case VSQRTSHZrbkz_Int:
23470 case VSQRTSHZrk_Int:
23471 case VSQRTSHZrkz_Int:
23472 return true;
23473 }
23474 return false;
23475}
23476
23477bool isTCVTROWD2PS(unsigned Opcode) {
23478 switch (Opcode) {
23479 case TCVTROWD2PSrte:
23480 case TCVTROWD2PSrti:
23481 return true;
23482 }
23483 return false;
23484}
23485
23486bool isLOOP(unsigned Opcode) {
23487 return Opcode == LOOP;
23488}
23489
23490bool isSTUI(unsigned Opcode) {
23491 return Opcode == STUI;
23492}
23493
23494bool isVCVTTPS2UDQ(unsigned Opcode) {
23495 switch (Opcode) {
23496 case VCVTTPS2UDQZ128rm:
23497 case VCVTTPS2UDQZ128rmb:
23498 case VCVTTPS2UDQZ128rmbk:
23499 case VCVTTPS2UDQZ128rmbkz:
23500 case VCVTTPS2UDQZ128rmk:
23501 case VCVTTPS2UDQZ128rmkz:
23502 case VCVTTPS2UDQZ128rr:
23503 case VCVTTPS2UDQZ128rrk:
23504 case VCVTTPS2UDQZ128rrkz:
23505 case VCVTTPS2UDQZ256rm:
23506 case VCVTTPS2UDQZ256rmb:
23507 case VCVTTPS2UDQZ256rmbk:
23508 case VCVTTPS2UDQZ256rmbkz:
23509 case VCVTTPS2UDQZ256rmk:
23510 case VCVTTPS2UDQZ256rmkz:
23511 case VCVTTPS2UDQZ256rr:
23512 case VCVTTPS2UDQZ256rrk:
23513 case VCVTTPS2UDQZ256rrkz:
23514 case VCVTTPS2UDQZrm:
23515 case VCVTTPS2UDQZrmb:
23516 case VCVTTPS2UDQZrmbk:
23517 case VCVTTPS2UDQZrmbkz:
23518 case VCVTTPS2UDQZrmk:
23519 case VCVTTPS2UDQZrmkz:
23520 case VCVTTPS2UDQZrr:
23521 case VCVTTPS2UDQZrrb:
23522 case VCVTTPS2UDQZrrbk:
23523 case VCVTTPS2UDQZrrbkz:
23524 case VCVTTPS2UDQZrrk:
23525 case VCVTTPS2UDQZrrkz:
23526 return true;
23527 }
23528 return false;
23529}
23530
23531bool isXABORT(unsigned Opcode) {
23532 return Opcode == XABORT;
23533}
23534
23535bool isVCOMPRESSPS(unsigned Opcode) {
23536 switch (Opcode) {
23537 case VCOMPRESSPSZ128mr:
23538 case VCOMPRESSPSZ128mrk:
23539 case VCOMPRESSPSZ128rr:
23540 case VCOMPRESSPSZ128rrk:
23541 case VCOMPRESSPSZ128rrkz:
23542 case VCOMPRESSPSZ256mr:
23543 case VCOMPRESSPSZ256mrk:
23544 case VCOMPRESSPSZ256rr:
23545 case VCOMPRESSPSZ256rrk:
23546 case VCOMPRESSPSZ256rrkz:
23547 case VCOMPRESSPSZmr:
23548 case VCOMPRESSPSZmrk:
23549 case VCOMPRESSPSZrr:
23550 case VCOMPRESSPSZrrk:
23551 case VCOMPRESSPSZrrkz:
23552 return true;
23553 }
23554 return false;
23555}
23556
23557bool isVCVTTBF162IUBS(unsigned Opcode) {
23558 switch (Opcode) {
23559 case VCVTTBF162IUBSZ128rm:
23560 case VCVTTBF162IUBSZ128rmb:
23561 case VCVTTBF162IUBSZ128rmbk:
23562 case VCVTTBF162IUBSZ128rmbkz:
23563 case VCVTTBF162IUBSZ128rmk:
23564 case VCVTTBF162IUBSZ128rmkz:
23565 case VCVTTBF162IUBSZ128rr:
23566 case VCVTTBF162IUBSZ128rrk:
23567 case VCVTTBF162IUBSZ128rrkz:
23568 case VCVTTBF162IUBSZ256rm:
23569 case VCVTTBF162IUBSZ256rmb:
23570 case VCVTTBF162IUBSZ256rmbk:
23571 case VCVTTBF162IUBSZ256rmbkz:
23572 case VCVTTBF162IUBSZ256rmk:
23573 case VCVTTBF162IUBSZ256rmkz:
23574 case VCVTTBF162IUBSZ256rr:
23575 case VCVTTBF162IUBSZ256rrk:
23576 case VCVTTBF162IUBSZ256rrkz:
23577 case VCVTTBF162IUBSZrm:
23578 case VCVTTBF162IUBSZrmb:
23579 case VCVTTBF162IUBSZrmbk:
23580 case VCVTTBF162IUBSZrmbkz:
23581 case VCVTTBF162IUBSZrmk:
23582 case VCVTTBF162IUBSZrmkz:
23583 case VCVTTBF162IUBSZrr:
23584 case VCVTTBF162IUBSZrrk:
23585 case VCVTTBF162IUBSZrrkz:
23586 return true;
23587 }
23588 return false;
23589}
23590
23591bool isVPADDW(unsigned Opcode) {
23592 switch (Opcode) {
23593 case VPADDWYrm:
23594 case VPADDWYrr:
23595 case VPADDWZ128rm:
23596 case VPADDWZ128rmk:
23597 case VPADDWZ128rmkz:
23598 case VPADDWZ128rr:
23599 case VPADDWZ128rrk:
23600 case VPADDWZ128rrkz:
23601 case VPADDWZ256rm:
23602 case VPADDWZ256rmk:
23603 case VPADDWZ256rmkz:
23604 case VPADDWZ256rr:
23605 case VPADDWZ256rrk:
23606 case VPADDWZ256rrkz:
23607 case VPADDWZrm:
23608 case VPADDWZrmk:
23609 case VPADDWZrmkz:
23610 case VPADDWZrr:
23611 case VPADDWZrrk:
23612 case VPADDWZrrkz:
23613 case VPADDWrm:
23614 case VPADDWrr:
23615 return true;
23616 }
23617 return false;
23618}
23619
23620bool isVPSIGND(unsigned Opcode) {
23621 switch (Opcode) {
23622 case VPSIGNDYrm:
23623 case VPSIGNDYrr:
23624 case VPSIGNDrm:
23625 case VPSIGNDrr:
23626 return true;
23627 }
23628 return false;
23629}
23630
23631bool isVRNDSCALEPS(unsigned Opcode) {
23632 switch (Opcode) {
23633 case VRNDSCALEPSZ128rmbi:
23634 case VRNDSCALEPSZ128rmbik:
23635 case VRNDSCALEPSZ128rmbikz:
23636 case VRNDSCALEPSZ128rmi:
23637 case VRNDSCALEPSZ128rmik:
23638 case VRNDSCALEPSZ128rmikz:
23639 case VRNDSCALEPSZ128rri:
23640 case VRNDSCALEPSZ128rrik:
23641 case VRNDSCALEPSZ128rrikz:
23642 case VRNDSCALEPSZ256rmbi:
23643 case VRNDSCALEPSZ256rmbik:
23644 case VRNDSCALEPSZ256rmbikz:
23645 case VRNDSCALEPSZ256rmi:
23646 case VRNDSCALEPSZ256rmik:
23647 case VRNDSCALEPSZ256rmikz:
23648 case VRNDSCALEPSZ256rri:
23649 case VRNDSCALEPSZ256rrik:
23650 case VRNDSCALEPSZ256rrikz:
23651 case VRNDSCALEPSZrmbi:
23652 case VRNDSCALEPSZrmbik:
23653 case VRNDSCALEPSZrmbikz:
23654 case VRNDSCALEPSZrmi:
23655 case VRNDSCALEPSZrmik:
23656 case VRNDSCALEPSZrmikz:
23657 case VRNDSCALEPSZrri:
23658 case VRNDSCALEPSZrrib:
23659 case VRNDSCALEPSZrribk:
23660 case VRNDSCALEPSZrribkz:
23661 case VRNDSCALEPSZrrik:
23662 case VRNDSCALEPSZrrikz:
23663 return true;
23664 }
23665 return false;
23666}
23667
23668bool isVPHADDUWD(unsigned Opcode) {
23669 switch (Opcode) {
23670 case VPHADDUWDrm:
23671 case VPHADDUWDrr:
23672 return true;
23673 }
23674 return false;
23675}
23676
23677bool isVCVT2PH2HF8S(unsigned Opcode) {
23678 switch (Opcode) {
23679 case VCVT2PH2HF8SZ128rm:
23680 case VCVT2PH2HF8SZ128rmb:
23681 case VCVT2PH2HF8SZ128rmbk:
23682 case VCVT2PH2HF8SZ128rmbkz:
23683 case VCVT2PH2HF8SZ128rmk:
23684 case VCVT2PH2HF8SZ128rmkz:
23685 case VCVT2PH2HF8SZ128rr:
23686 case VCVT2PH2HF8SZ128rrk:
23687 case VCVT2PH2HF8SZ128rrkz:
23688 case VCVT2PH2HF8SZ256rm:
23689 case VCVT2PH2HF8SZ256rmb:
23690 case VCVT2PH2HF8SZ256rmbk:
23691 case VCVT2PH2HF8SZ256rmbkz:
23692 case VCVT2PH2HF8SZ256rmk:
23693 case VCVT2PH2HF8SZ256rmkz:
23694 case VCVT2PH2HF8SZ256rr:
23695 case VCVT2PH2HF8SZ256rrk:
23696 case VCVT2PH2HF8SZ256rrkz:
23697 case VCVT2PH2HF8SZrm:
23698 case VCVT2PH2HF8SZrmb:
23699 case VCVT2PH2HF8SZrmbk:
23700 case VCVT2PH2HF8SZrmbkz:
23701 case VCVT2PH2HF8SZrmk:
23702 case VCVT2PH2HF8SZrmkz:
23703 case VCVT2PH2HF8SZrr:
23704 case VCVT2PH2HF8SZrrk:
23705 case VCVT2PH2HF8SZrrkz:
23706 return true;
23707 }
23708 return false;
23709}
23710
23711bool isVDBPSADBW(unsigned Opcode) {
23712 switch (Opcode) {
23713 case VDBPSADBWZ128rmi:
23714 case VDBPSADBWZ128rmik:
23715 case VDBPSADBWZ128rmikz:
23716 case VDBPSADBWZ128rri:
23717 case VDBPSADBWZ128rrik:
23718 case VDBPSADBWZ128rrikz:
23719 case VDBPSADBWZ256rmi:
23720 case VDBPSADBWZ256rmik:
23721 case VDBPSADBWZ256rmikz:
23722 case VDBPSADBWZ256rri:
23723 case VDBPSADBWZ256rrik:
23724 case VDBPSADBWZ256rrikz:
23725 case VDBPSADBWZrmi:
23726 case VDBPSADBWZrmik:
23727 case VDBPSADBWZrmikz:
23728 case VDBPSADBWZrri:
23729 case VDBPSADBWZrrik:
23730 case VDBPSADBWZrrikz:
23731 return true;
23732 }
23733 return false;
23734}
23735
23736bool isPSLLW(unsigned Opcode) {
23737 switch (Opcode) {
23738 case MMX_PSLLWri:
23739 case MMX_PSLLWrm:
23740 case MMX_PSLLWrr:
23741 case PSLLWri:
23742 case PSLLWrm:
23743 case PSLLWrr:
23744 return true;
23745 }
23746 return false;
23747}
23748
23749bool isVPMOVQD(unsigned Opcode) {
23750 switch (Opcode) {
23751 case VPMOVQDZ128mr:
23752 case VPMOVQDZ128mrk:
23753 case VPMOVQDZ128rr:
23754 case VPMOVQDZ128rrk:
23755 case VPMOVQDZ128rrkz:
23756 case VPMOVQDZ256mr:
23757 case VPMOVQDZ256mrk:
23758 case VPMOVQDZ256rr:
23759 case VPMOVQDZ256rrk:
23760 case VPMOVQDZ256rrkz:
23761 case VPMOVQDZmr:
23762 case VPMOVQDZmrk:
23763 case VPMOVQDZrr:
23764 case VPMOVQDZrrk:
23765 case VPMOVQDZrrkz:
23766 return true;
23767 }
23768 return false;
23769}
23770
23771bool isVINSERTI64X4(unsigned Opcode) {
23772 switch (Opcode) {
23773 case VINSERTI64X4Zrmi:
23774 case VINSERTI64X4Zrmik:
23775 case VINSERTI64X4Zrmikz:
23776 case VINSERTI64X4Zrri:
23777 case VINSERTI64X4Zrrik:
23778 case VINSERTI64X4Zrrikz:
23779 return true;
23780 }
23781 return false;
23782}
23783
23784bool isVPERMI2PS(unsigned Opcode) {
23785 switch (Opcode) {
23786 case VPERMI2PSZ128rm:
23787 case VPERMI2PSZ128rmb:
23788 case VPERMI2PSZ128rmbk:
23789 case VPERMI2PSZ128rmbkz:
23790 case VPERMI2PSZ128rmk:
23791 case VPERMI2PSZ128rmkz:
23792 case VPERMI2PSZ128rr:
23793 case VPERMI2PSZ128rrk:
23794 case VPERMI2PSZ128rrkz:
23795 case VPERMI2PSZ256rm:
23796 case VPERMI2PSZ256rmb:
23797 case VPERMI2PSZ256rmbk:
23798 case VPERMI2PSZ256rmbkz:
23799 case VPERMI2PSZ256rmk:
23800 case VPERMI2PSZ256rmkz:
23801 case VPERMI2PSZ256rr:
23802 case VPERMI2PSZ256rrk:
23803 case VPERMI2PSZ256rrkz:
23804 case VPERMI2PSZrm:
23805 case VPERMI2PSZrmb:
23806 case VPERMI2PSZrmbk:
23807 case VPERMI2PSZrmbkz:
23808 case VPERMI2PSZrmk:
23809 case VPERMI2PSZrmkz:
23810 case VPERMI2PSZrr:
23811 case VPERMI2PSZrrk:
23812 case VPERMI2PSZrrkz:
23813 return true;
23814 }
23815 return false;
23816}
23817
23818bool isVMULPH(unsigned Opcode) {
23819 switch (Opcode) {
23820 case VMULPHZ128rm:
23821 case VMULPHZ128rmb:
23822 case VMULPHZ128rmbk:
23823 case VMULPHZ128rmbkz:
23824 case VMULPHZ128rmk:
23825 case VMULPHZ128rmkz:
23826 case VMULPHZ128rr:
23827 case VMULPHZ128rrk:
23828 case VMULPHZ128rrkz:
23829 case VMULPHZ256rm:
23830 case VMULPHZ256rmb:
23831 case VMULPHZ256rmbk:
23832 case VMULPHZ256rmbkz:
23833 case VMULPHZ256rmk:
23834 case VMULPHZ256rmkz:
23835 case VMULPHZ256rr:
23836 case VMULPHZ256rrk:
23837 case VMULPHZ256rrkz:
23838 case VMULPHZrm:
23839 case VMULPHZrmb:
23840 case VMULPHZrmbk:
23841 case VMULPHZrmbkz:
23842 case VMULPHZrmk:
23843 case VMULPHZrmkz:
23844 case VMULPHZrr:
23845 case VMULPHZrrb:
23846 case VMULPHZrrbk:
23847 case VMULPHZrrbkz:
23848 case VMULPHZrrk:
23849 case VMULPHZrrkz:
23850 return true;
23851 }
23852 return false;
23853}
23854
23855bool isVPCMPUQ(unsigned Opcode) {
23856 switch (Opcode) {
23857 case VPCMPUQZ128rmbi:
23858 case VPCMPUQZ128rmbik:
23859 case VPCMPUQZ128rmi:
23860 case VPCMPUQZ128rmik:
23861 case VPCMPUQZ128rri:
23862 case VPCMPUQZ128rrik:
23863 case VPCMPUQZ256rmbi:
23864 case VPCMPUQZ256rmbik:
23865 case VPCMPUQZ256rmi:
23866 case VPCMPUQZ256rmik:
23867 case VPCMPUQZ256rri:
23868 case VPCMPUQZ256rrik:
23869 case VPCMPUQZrmbi:
23870 case VPCMPUQZrmbik:
23871 case VPCMPUQZrmi:
23872 case VPCMPUQZrmik:
23873 case VPCMPUQZrri:
23874 case VPCMPUQZrrik:
23875 return true;
23876 }
23877 return false;
23878}
23879
23880bool isVCVTUSI2SD(unsigned Opcode) {
23881 switch (Opcode) {
23882 case VCVTUSI2SDZrm_Int:
23883 case VCVTUSI2SDZrr_Int:
23884 case VCVTUSI642SDZrm_Int:
23885 case VCVTUSI642SDZrr_Int:
23886 case VCVTUSI642SDZrrb_Int:
23887 return true;
23888 }
23889 return false;
23890}
23891
23892bool isKXNORW(unsigned Opcode) {
23893 return Opcode == KXNORWkk;
23894}
23895
23896bool isBLCIC(unsigned Opcode) {
23897 switch (Opcode) {
23898 case BLCIC32rm:
23899 case BLCIC32rr:
23900 case BLCIC64rm:
23901 case BLCIC64rr:
23902 return true;
23903 }
23904 return false;
23905}
23906
23907bool isVFNMADD213SD(unsigned Opcode) {
23908 switch (Opcode) {
23909 case VFNMADD213SDZm_Int:
23910 case VFNMADD213SDZmk_Int:
23911 case VFNMADD213SDZmkz_Int:
23912 case VFNMADD213SDZr_Int:
23913 case VFNMADD213SDZrb_Int:
23914 case VFNMADD213SDZrbk_Int:
23915 case VFNMADD213SDZrbkz_Int:
23916 case VFNMADD213SDZrk_Int:
23917 case VFNMADD213SDZrkz_Int:
23918 case VFNMADD213SDm_Int:
23919 case VFNMADD213SDr_Int:
23920 return true;
23921 }
23922 return false;
23923}
23924
23925bool isVMOVLPS(unsigned Opcode) {
23926 switch (Opcode) {
23927 case VMOVLPSZ128mr:
23928 case VMOVLPSZ128rm:
23929 case VMOVLPSmr:
23930 case VMOVLPSrm:
23931 return true;
23932 }
23933 return false;
23934}
23935
23936bool isVPMACSWW(unsigned Opcode) {
23937 switch (Opcode) {
23938 case VPMACSWWrm:
23939 case VPMACSWWrr:
23940 return true;
23941 }
23942 return false;
23943}
23944
23945bool isPCONFIG(unsigned Opcode) {
23946 return Opcode == PCONFIG;
23947}
23948
23949bool isPANDN(unsigned Opcode) {
23950 switch (Opcode) {
23951 case MMX_PANDNrm:
23952 case MMX_PANDNrr:
23953 case PANDNrm:
23954 case PANDNrr:
23955 return true;
23956 }
23957 return false;
23958}
23959
23960bool isVGETEXPPD(unsigned Opcode) {
23961 switch (Opcode) {
23962 case VGETEXPPDZ128m:
23963 case VGETEXPPDZ128mb:
23964 case VGETEXPPDZ128mbk:
23965 case VGETEXPPDZ128mbkz:
23966 case VGETEXPPDZ128mk:
23967 case VGETEXPPDZ128mkz:
23968 case VGETEXPPDZ128r:
23969 case VGETEXPPDZ128rk:
23970 case VGETEXPPDZ128rkz:
23971 case VGETEXPPDZ256m:
23972 case VGETEXPPDZ256mb:
23973 case VGETEXPPDZ256mbk:
23974 case VGETEXPPDZ256mbkz:
23975 case VGETEXPPDZ256mk:
23976 case VGETEXPPDZ256mkz:
23977 case VGETEXPPDZ256r:
23978 case VGETEXPPDZ256rk:
23979 case VGETEXPPDZ256rkz:
23980 case VGETEXPPDZm:
23981 case VGETEXPPDZmb:
23982 case VGETEXPPDZmbk:
23983 case VGETEXPPDZmbkz:
23984 case VGETEXPPDZmk:
23985 case VGETEXPPDZmkz:
23986 case VGETEXPPDZr:
23987 case VGETEXPPDZrb:
23988 case VGETEXPPDZrbk:
23989 case VGETEXPPDZrbkz:
23990 case VGETEXPPDZrk:
23991 case VGETEXPPDZrkz:
23992 return true;
23993 }
23994 return false;
23995}
23996
23997bool isVPSRLVQ(unsigned Opcode) {
23998 switch (Opcode) {
23999 case VPSRLVQYrm:
24000 case VPSRLVQYrr:
24001 case VPSRLVQZ128rm:
24002 case VPSRLVQZ128rmb:
24003 case VPSRLVQZ128rmbk:
24004 case VPSRLVQZ128rmbkz:
24005 case VPSRLVQZ128rmk:
24006 case VPSRLVQZ128rmkz:
24007 case VPSRLVQZ128rr:
24008 case VPSRLVQZ128rrk:
24009 case VPSRLVQZ128rrkz:
24010 case VPSRLVQZ256rm:
24011 case VPSRLVQZ256rmb:
24012 case VPSRLVQZ256rmbk:
24013 case VPSRLVQZ256rmbkz:
24014 case VPSRLVQZ256rmk:
24015 case VPSRLVQZ256rmkz:
24016 case VPSRLVQZ256rr:
24017 case VPSRLVQZ256rrk:
24018 case VPSRLVQZ256rrkz:
24019 case VPSRLVQZrm:
24020 case VPSRLVQZrmb:
24021 case VPSRLVQZrmbk:
24022 case VPSRLVQZrmbkz:
24023 case VPSRLVQZrmk:
24024 case VPSRLVQZrmkz:
24025 case VPSRLVQZrr:
24026 case VPSRLVQZrrk:
24027 case VPSRLVQZrrkz:
24028 case VPSRLVQrm:
24029 case VPSRLVQrr:
24030 return true;
24031 }
24032 return false;
24033}
24034
24035bool isUD1(unsigned Opcode) {
24036 switch (Opcode) {
24037 case UD1Lm:
24038 case UD1Lr:
24039 case UD1Qm:
24040 case UD1Qr:
24041 case UD1Wm:
24042 case UD1Wr:
24043 return true;
24044 }
24045 return false;
24046}
24047
24048bool isPMAXSB(unsigned Opcode) {
24049 switch (Opcode) {
24050 case PMAXSBrm:
24051 case PMAXSBrr:
24052 return true;
24053 }
24054 return false;
24055}
24056
24057bool isVPROLQ(unsigned Opcode) {
24058 switch (Opcode) {
24059 case VPROLQZ128mbi:
24060 case VPROLQZ128mbik:
24061 case VPROLQZ128mbikz:
24062 case VPROLQZ128mi:
24063 case VPROLQZ128mik:
24064 case VPROLQZ128mikz:
24065 case VPROLQZ128ri:
24066 case VPROLQZ128rik:
24067 case VPROLQZ128rikz:
24068 case VPROLQZ256mbi:
24069 case VPROLQZ256mbik:
24070 case VPROLQZ256mbikz:
24071 case VPROLQZ256mi:
24072 case VPROLQZ256mik:
24073 case VPROLQZ256mikz:
24074 case VPROLQZ256ri:
24075 case VPROLQZ256rik:
24076 case VPROLQZ256rikz:
24077 case VPROLQZmbi:
24078 case VPROLQZmbik:
24079 case VPROLQZmbikz:
24080 case VPROLQZmi:
24081 case VPROLQZmik:
24082 case VPROLQZmikz:
24083 case VPROLQZri:
24084 case VPROLQZrik:
24085 case VPROLQZrikz:
24086 return true;
24087 }
24088 return false;
24089}
24090
24091bool isVPSRLD(unsigned Opcode) {
24092 switch (Opcode) {
24093 case VPSRLDYri:
24094 case VPSRLDYrm:
24095 case VPSRLDYrr:
24096 case VPSRLDZ128mbi:
24097 case VPSRLDZ128mbik:
24098 case VPSRLDZ128mbikz:
24099 case VPSRLDZ128mi:
24100 case VPSRLDZ128mik:
24101 case VPSRLDZ128mikz:
24102 case VPSRLDZ128ri:
24103 case VPSRLDZ128rik:
24104 case VPSRLDZ128rikz:
24105 case VPSRLDZ128rm:
24106 case VPSRLDZ128rmk:
24107 case VPSRLDZ128rmkz:
24108 case VPSRLDZ128rr:
24109 case VPSRLDZ128rrk:
24110 case VPSRLDZ128rrkz:
24111 case VPSRLDZ256mbi:
24112 case VPSRLDZ256mbik:
24113 case VPSRLDZ256mbikz:
24114 case VPSRLDZ256mi:
24115 case VPSRLDZ256mik:
24116 case VPSRLDZ256mikz:
24117 case VPSRLDZ256ri:
24118 case VPSRLDZ256rik:
24119 case VPSRLDZ256rikz:
24120 case VPSRLDZ256rm:
24121 case VPSRLDZ256rmk:
24122 case VPSRLDZ256rmkz:
24123 case VPSRLDZ256rr:
24124 case VPSRLDZ256rrk:
24125 case VPSRLDZ256rrkz:
24126 case VPSRLDZmbi:
24127 case VPSRLDZmbik:
24128 case VPSRLDZmbikz:
24129 case VPSRLDZmi:
24130 case VPSRLDZmik:
24131 case VPSRLDZmikz:
24132 case VPSRLDZri:
24133 case VPSRLDZrik:
24134 case VPSRLDZrikz:
24135 case VPSRLDZrm:
24136 case VPSRLDZrmk:
24137 case VPSRLDZrmkz:
24138 case VPSRLDZrr:
24139 case VPSRLDZrrk:
24140 case VPSRLDZrrkz:
24141 case VPSRLDri:
24142 case VPSRLDrm:
24143 case VPSRLDrr:
24144 return true;
24145 }
24146 return false;
24147}
24148
24149bool isVSCATTERPF1QPD(unsigned Opcode) {
24150 return Opcode == VSCATTERPF1QPDm;
24151}
24152
24153bool isINT3(unsigned Opcode) {
24154 return Opcode == INT3;
24155}
24156
24157bool isXRSTORS64(unsigned Opcode) {
24158 return Opcode == XRSTORS64;
24159}
24160
24161bool isCVTSD2SI(unsigned Opcode) {
24162 switch (Opcode) {
24163 case CVTSD2SI64rm_Int:
24164 case CVTSD2SI64rr_Int:
24165 case CVTSD2SIrm_Int:
24166 case CVTSD2SIrr_Int:
24167 return true;
24168 }
24169 return false;
24170}
24171
24172bool isVMAXSS(unsigned Opcode) {
24173 switch (Opcode) {
24174 case VMAXSSZrm_Int:
24175 case VMAXSSZrmk_Int:
24176 case VMAXSSZrmkz_Int:
24177 case VMAXSSZrr_Int:
24178 case VMAXSSZrrb_Int:
24179 case VMAXSSZrrbk_Int:
24180 case VMAXSSZrrbkz_Int:
24181 case VMAXSSZrrk_Int:
24182 case VMAXSSZrrkz_Int:
24183 case VMAXSSrm_Int:
24184 case VMAXSSrr_Int:
24185 return true;
24186 }
24187 return false;
24188}
24189
24190bool isVPMINUB(unsigned Opcode) {
24191 switch (Opcode) {
24192 case VPMINUBYrm:
24193 case VPMINUBYrr:
24194 case VPMINUBZ128rm:
24195 case VPMINUBZ128rmk:
24196 case VPMINUBZ128rmkz:
24197 case VPMINUBZ128rr:
24198 case VPMINUBZ128rrk:
24199 case VPMINUBZ128rrkz:
24200 case VPMINUBZ256rm:
24201 case VPMINUBZ256rmk:
24202 case VPMINUBZ256rmkz:
24203 case VPMINUBZ256rr:
24204 case VPMINUBZ256rrk:
24205 case VPMINUBZ256rrkz:
24206 case VPMINUBZrm:
24207 case VPMINUBZrmk:
24208 case VPMINUBZrmkz:
24209 case VPMINUBZrr:
24210 case VPMINUBZrrk:
24211 case VPMINUBZrrkz:
24212 case VPMINUBrm:
24213 case VPMINUBrr:
24214 return true;
24215 }
24216 return false;
24217}
24218
24219bool isKXNORQ(unsigned Opcode) {
24220 return Opcode == KXNORQkk;
24221}
24222
24223bool isFLD(unsigned Opcode) {
24224 switch (Opcode) {
24225 case LD_F32m:
24226 case LD_F64m:
24227 case LD_F80m:
24228 case LD_Frr:
24229 return true;
24230 }
24231 return false;
24232}
24233
24234bool isVSHUFI32X4(unsigned Opcode) {
24235 switch (Opcode) {
24236 case VSHUFI32X4Z256rmbi:
24237 case VSHUFI32X4Z256rmbik:
24238 case VSHUFI32X4Z256rmbikz:
24239 case VSHUFI32X4Z256rmi:
24240 case VSHUFI32X4Z256rmik:
24241 case VSHUFI32X4Z256rmikz:
24242 case VSHUFI32X4Z256rri:
24243 case VSHUFI32X4Z256rrik:
24244 case VSHUFI32X4Z256rrikz:
24245 case VSHUFI32X4Zrmbi:
24246 case VSHUFI32X4Zrmbik:
24247 case VSHUFI32X4Zrmbikz:
24248 case VSHUFI32X4Zrmi:
24249 case VSHUFI32X4Zrmik:
24250 case VSHUFI32X4Zrmikz:
24251 case VSHUFI32X4Zrri:
24252 case VSHUFI32X4Zrrik:
24253 case VSHUFI32X4Zrrikz:
24254 return true;
24255 }
24256 return false;
24257}
24258
24259bool isSAHF(unsigned Opcode) {
24260 return Opcode == SAHF;
24261}
24262
24263bool isPFRSQRT(unsigned Opcode) {
24264 switch (Opcode) {
24265 case PFRSQRTrm:
24266 case PFRSQRTrr:
24267 return true;
24268 }
24269 return false;
24270}
24271
24272bool isSHRD(unsigned Opcode) {
24273 switch (Opcode) {
24274 case SHRD16mrCL:
24275 case SHRD16mrCL_EVEX:
24276 case SHRD16mrCL_ND:
24277 case SHRD16mrCL_NF:
24278 case SHRD16mrCL_NF_ND:
24279 case SHRD16mri8:
24280 case SHRD16mri8_EVEX:
24281 case SHRD16mri8_ND:
24282 case SHRD16mri8_NF:
24283 case SHRD16mri8_NF_ND:
24284 case SHRD16rrCL:
24285 case SHRD16rrCL_EVEX:
24286 case SHRD16rrCL_ND:
24287 case SHRD16rrCL_NF:
24288 case SHRD16rrCL_NF_ND:
24289 case SHRD16rri8:
24290 case SHRD16rri8_EVEX:
24291 case SHRD16rri8_ND:
24292 case SHRD16rri8_NF:
24293 case SHRD16rri8_NF_ND:
24294 case SHRD32mrCL:
24295 case SHRD32mrCL_EVEX:
24296 case SHRD32mrCL_ND:
24297 case SHRD32mrCL_NF:
24298 case SHRD32mrCL_NF_ND:
24299 case SHRD32mri8:
24300 case SHRD32mri8_EVEX:
24301 case SHRD32mri8_ND:
24302 case SHRD32mri8_NF:
24303 case SHRD32mri8_NF_ND:
24304 case SHRD32rrCL:
24305 case SHRD32rrCL_EVEX:
24306 case SHRD32rrCL_ND:
24307 case SHRD32rrCL_NF:
24308 case SHRD32rrCL_NF_ND:
24309 case SHRD32rri8:
24310 case SHRD32rri8_EVEX:
24311 case SHRD32rri8_ND:
24312 case SHRD32rri8_NF:
24313 case SHRD32rri8_NF_ND:
24314 case SHRD64mrCL:
24315 case SHRD64mrCL_EVEX:
24316 case SHRD64mrCL_ND:
24317 case SHRD64mrCL_NF:
24318 case SHRD64mrCL_NF_ND:
24319 case SHRD64mri8:
24320 case SHRD64mri8_EVEX:
24321 case SHRD64mri8_ND:
24322 case SHRD64mri8_NF:
24323 case SHRD64mri8_NF_ND:
24324 case SHRD64rrCL:
24325 case SHRD64rrCL_EVEX:
24326 case SHRD64rrCL_ND:
24327 case SHRD64rrCL_NF:
24328 case SHRD64rrCL_NF_ND:
24329 case SHRD64rri8:
24330 case SHRD64rri8_EVEX:
24331 case SHRD64rri8_ND:
24332 case SHRD64rri8_NF:
24333 case SHRD64rri8_NF_ND:
24334 return true;
24335 }
24336 return false;
24337}
24338
24339bool isSYSEXIT(unsigned Opcode) {
24340 return Opcode == SYSEXIT;
24341}
24342
24343bool isXSAVE64(unsigned Opcode) {
24344 return Opcode == XSAVE64;
24345}
24346
24347bool isVPMAXSD(unsigned Opcode) {
24348 switch (Opcode) {
24349 case VPMAXSDYrm:
24350 case VPMAXSDYrr:
24351 case VPMAXSDZ128rm:
24352 case VPMAXSDZ128rmb:
24353 case VPMAXSDZ128rmbk:
24354 case VPMAXSDZ128rmbkz:
24355 case VPMAXSDZ128rmk:
24356 case VPMAXSDZ128rmkz:
24357 case VPMAXSDZ128rr:
24358 case VPMAXSDZ128rrk:
24359 case VPMAXSDZ128rrkz:
24360 case VPMAXSDZ256rm:
24361 case VPMAXSDZ256rmb:
24362 case VPMAXSDZ256rmbk:
24363 case VPMAXSDZ256rmbkz:
24364 case VPMAXSDZ256rmk:
24365 case VPMAXSDZ256rmkz:
24366 case VPMAXSDZ256rr:
24367 case VPMAXSDZ256rrk:
24368 case VPMAXSDZ256rrkz:
24369 case VPMAXSDZrm:
24370 case VPMAXSDZrmb:
24371 case VPMAXSDZrmbk:
24372 case VPMAXSDZrmbkz:
24373 case VPMAXSDZrmk:
24374 case VPMAXSDZrmkz:
24375 case VPMAXSDZrr:
24376 case VPMAXSDZrrk:
24377 case VPMAXSDZrrkz:
24378 case VPMAXSDrm:
24379 case VPMAXSDrr:
24380 return true;
24381 }
24382 return false;
24383}
24384
24385bool isCVTTSD2SI(unsigned Opcode) {
24386 switch (Opcode) {
24387 case CVTTSD2SI64rm_Int:
24388 case CVTTSD2SI64rr_Int:
24389 case CVTTSD2SIrm_Int:
24390 case CVTTSD2SIrr_Int:
24391 return true;
24392 }
24393 return false;
24394}
24395
24396bool isVCVTTSS2SIS(unsigned Opcode) {
24397 switch (Opcode) {
24398 case VCVTTSS2SI64Srm_Int:
24399 case VCVTTSS2SI64Srr_Int:
24400 case VCVTTSS2SI64Srrb_Int:
24401 case VCVTTSS2SISrm_Int:
24402 case VCVTTSS2SISrr_Int:
24403 case VCVTTSS2SISrrb_Int:
24404 return true;
24405 }
24406 return false;
24407}
24408
24409bool isPMOVMSKB(unsigned Opcode) {
24410 switch (Opcode) {
24411 case MMX_PMOVMSKBrr:
24412 case PMOVMSKBrr:
24413 return true;
24414 }
24415 return false;
24416}
24417
24418bool isVRANGEPS(unsigned Opcode) {
24419 switch (Opcode) {
24420 case VRANGEPSZ128rmbi:
24421 case VRANGEPSZ128rmbik:
24422 case VRANGEPSZ128rmbikz:
24423 case VRANGEPSZ128rmi:
24424 case VRANGEPSZ128rmik:
24425 case VRANGEPSZ128rmikz:
24426 case VRANGEPSZ128rri:
24427 case VRANGEPSZ128rrik:
24428 case VRANGEPSZ128rrikz:
24429 case VRANGEPSZ256rmbi:
24430 case VRANGEPSZ256rmbik:
24431 case VRANGEPSZ256rmbikz:
24432 case VRANGEPSZ256rmi:
24433 case VRANGEPSZ256rmik:
24434 case VRANGEPSZ256rmikz:
24435 case VRANGEPSZ256rri:
24436 case VRANGEPSZ256rrik:
24437 case VRANGEPSZ256rrikz:
24438 case VRANGEPSZrmbi:
24439 case VRANGEPSZrmbik:
24440 case VRANGEPSZrmbikz:
24441 case VRANGEPSZrmi:
24442 case VRANGEPSZrmik:
24443 case VRANGEPSZrmikz:
24444 case VRANGEPSZrri:
24445 case VRANGEPSZrrib:
24446 case VRANGEPSZrribk:
24447 case VRANGEPSZrribkz:
24448 case VRANGEPSZrrik:
24449 case VRANGEPSZrrikz:
24450 return true;
24451 }
24452 return false;
24453}
24454
24455bool isVADDSUBPS(unsigned Opcode) {
24456 switch (Opcode) {
24457 case VADDSUBPSYrm:
24458 case VADDSUBPSYrr:
24459 case VADDSUBPSrm:
24460 case VADDSUBPSrr:
24461 return true;
24462 }
24463 return false;
24464}
24465
24466bool isVBROADCASTI128(unsigned Opcode) {
24467 return Opcode == VBROADCASTI128rm;
24468}
24469
24470bool isPADDUSB(unsigned Opcode) {
24471 switch (Opcode) {
24472 case MMX_PADDUSBrm:
24473 case MMX_PADDUSBrr:
24474 case PADDUSBrm:
24475 case PADDUSBrr:
24476 return true;
24477 }
24478 return false;
24479}
24480
24481bool isENCODEKEY128(unsigned Opcode) {
24482 return Opcode == ENCODEKEY128;
24483}
24484
24485bool isOR(unsigned Opcode) {
24486 switch (Opcode) {
24487 case OR16i16:
24488 case OR16mi:
24489 case OR16mi8:
24490 case OR16mi8_EVEX:
24491 case OR16mi8_ND:
24492 case OR16mi8_NF:
24493 case OR16mi8_NF_ND:
24494 case OR16mi_EVEX:
24495 case OR16mi_ND:
24496 case OR16mi_NF:
24497 case OR16mi_NF_ND:
24498 case OR16mr:
24499 case OR16mr_EVEX:
24500 case OR16mr_ND:
24501 case OR16mr_NF:
24502 case OR16mr_NF_ND:
24503 case OR16ri:
24504 case OR16ri8:
24505 case OR16ri8_EVEX:
24506 case OR16ri8_ND:
24507 case OR16ri8_NF:
24508 case OR16ri8_NF_ND:
24509 case OR16ri_EVEX:
24510 case OR16ri_ND:
24511 case OR16ri_NF:
24512 case OR16ri_NF_ND:
24513 case OR16rm:
24514 case OR16rm_EVEX:
24515 case OR16rm_ND:
24516 case OR16rm_NF:
24517 case OR16rm_NF_ND:
24518 case OR16rr:
24519 case OR16rr_EVEX:
24520 case OR16rr_EVEX_REV:
24521 case OR16rr_ND:
24522 case OR16rr_ND_REV:
24523 case OR16rr_NF:
24524 case OR16rr_NF_ND:
24525 case OR16rr_NF_ND_REV:
24526 case OR16rr_NF_REV:
24527 case OR16rr_REV:
24528 case OR32i32:
24529 case OR32mi:
24530 case OR32mi8:
24531 case OR32mi8_EVEX:
24532 case OR32mi8_ND:
24533 case OR32mi8_NF:
24534 case OR32mi8_NF_ND:
24535 case OR32mi_EVEX:
24536 case OR32mi_ND:
24537 case OR32mi_NF:
24538 case OR32mi_NF_ND:
24539 case OR32mr:
24540 case OR32mr_EVEX:
24541 case OR32mr_ND:
24542 case OR32mr_NF:
24543 case OR32mr_NF_ND:
24544 case OR32ri:
24545 case OR32ri8:
24546 case OR32ri8_EVEX:
24547 case OR32ri8_ND:
24548 case OR32ri8_NF:
24549 case OR32ri8_NF_ND:
24550 case OR32ri_EVEX:
24551 case OR32ri_ND:
24552 case OR32ri_NF:
24553 case OR32ri_NF_ND:
24554 case OR32rm:
24555 case OR32rm_EVEX:
24556 case OR32rm_ND:
24557 case OR32rm_NF:
24558 case OR32rm_NF_ND:
24559 case OR32rr:
24560 case OR32rr_EVEX:
24561 case OR32rr_EVEX_REV:
24562 case OR32rr_ND:
24563 case OR32rr_ND_REV:
24564 case OR32rr_NF:
24565 case OR32rr_NF_ND:
24566 case OR32rr_NF_ND_REV:
24567 case OR32rr_NF_REV:
24568 case OR32rr_REV:
24569 case OR64i32:
24570 case OR64mi32:
24571 case OR64mi32_EVEX:
24572 case OR64mi32_ND:
24573 case OR64mi32_NF:
24574 case OR64mi32_NF_ND:
24575 case OR64mi8:
24576 case OR64mi8_EVEX:
24577 case OR64mi8_ND:
24578 case OR64mi8_NF:
24579 case OR64mi8_NF_ND:
24580 case OR64mr:
24581 case OR64mr_EVEX:
24582 case OR64mr_ND:
24583 case OR64mr_NF:
24584 case OR64mr_NF_ND:
24585 case OR64ri32:
24586 case OR64ri32_EVEX:
24587 case OR64ri32_ND:
24588 case OR64ri32_NF:
24589 case OR64ri32_NF_ND:
24590 case OR64ri8:
24591 case OR64ri8_EVEX:
24592 case OR64ri8_ND:
24593 case OR64ri8_NF:
24594 case OR64ri8_NF_ND:
24595 case OR64rm:
24596 case OR64rm_EVEX:
24597 case OR64rm_ND:
24598 case OR64rm_NF:
24599 case OR64rm_NF_ND:
24600 case OR64rr:
24601 case OR64rr_EVEX:
24602 case OR64rr_EVEX_REV:
24603 case OR64rr_ND:
24604 case OR64rr_ND_REV:
24605 case OR64rr_NF:
24606 case OR64rr_NF_ND:
24607 case OR64rr_NF_ND_REV:
24608 case OR64rr_NF_REV:
24609 case OR64rr_REV:
24610 case OR8i8:
24611 case OR8mi:
24612 case OR8mi8:
24613 case OR8mi_EVEX:
24614 case OR8mi_ND:
24615 case OR8mi_NF:
24616 case OR8mi_NF_ND:
24617 case OR8mr:
24618 case OR8mr_EVEX:
24619 case OR8mr_ND:
24620 case OR8mr_NF:
24621 case OR8mr_NF_ND:
24622 case OR8ri:
24623 case OR8ri8:
24624 case OR8ri_EVEX:
24625 case OR8ri_ND:
24626 case OR8ri_NF:
24627 case OR8ri_NF_ND:
24628 case OR8rm:
24629 case OR8rm_EVEX:
24630 case OR8rm_ND:
24631 case OR8rm_NF:
24632 case OR8rm_NF_ND:
24633 case OR8rr:
24634 case OR8rr_EVEX:
24635 case OR8rr_EVEX_REV:
24636 case OR8rr_ND:
24637 case OR8rr_ND_REV:
24638 case OR8rr_NF:
24639 case OR8rr_NF_ND:
24640 case OR8rr_NF_ND_REV:
24641 case OR8rr_NF_REV:
24642 case OR8rr_REV:
24643 return true;
24644 }
24645 return false;
24646}
24647
24648bool isSTOSW(unsigned Opcode) {
24649 return Opcode == STOSW;
24650}
24651
24652bool isVCVTTPD2UQQS(unsigned Opcode) {
24653 switch (Opcode) {
24654 case VCVTTPD2UQQSZ128rm:
24655 case VCVTTPD2UQQSZ128rmb:
24656 case VCVTTPD2UQQSZ128rmbk:
24657 case VCVTTPD2UQQSZ128rmbkz:
24658 case VCVTTPD2UQQSZ128rmk:
24659 case VCVTTPD2UQQSZ128rmkz:
24660 case VCVTTPD2UQQSZ128rr:
24661 case VCVTTPD2UQQSZ128rrk:
24662 case VCVTTPD2UQQSZ128rrkz:
24663 case VCVTTPD2UQQSZ256rm:
24664 case VCVTTPD2UQQSZ256rmb:
24665 case VCVTTPD2UQQSZ256rmbk:
24666 case VCVTTPD2UQQSZ256rmbkz:
24667 case VCVTTPD2UQQSZ256rmk:
24668 case VCVTTPD2UQQSZ256rmkz:
24669 case VCVTTPD2UQQSZ256rr:
24670 case VCVTTPD2UQQSZ256rrb:
24671 case VCVTTPD2UQQSZ256rrbk:
24672 case VCVTTPD2UQQSZ256rrbkz:
24673 case VCVTTPD2UQQSZ256rrk:
24674 case VCVTTPD2UQQSZ256rrkz:
24675 case VCVTTPD2UQQSZrm:
24676 case VCVTTPD2UQQSZrmb:
24677 case VCVTTPD2UQQSZrmbk:
24678 case VCVTTPD2UQQSZrmbkz:
24679 case VCVTTPD2UQQSZrmk:
24680 case VCVTTPD2UQQSZrmkz:
24681 case VCVTTPD2UQQSZrr:
24682 case VCVTTPD2UQQSZrrb:
24683 case VCVTTPD2UQQSZrrbk:
24684 case VCVTTPD2UQQSZrrbkz:
24685 case VCVTTPD2UQQSZrrk:
24686 case VCVTTPD2UQQSZrrkz:
24687 return true;
24688 }
24689 return false;
24690}
24691
24692bool isPAVGW(unsigned Opcode) {
24693 switch (Opcode) {
24694 case MMX_PAVGWrm:
24695 case MMX_PAVGWrr:
24696 case PAVGWrm:
24697 case PAVGWrr:
24698 return true;
24699 }
24700 return false;
24701}
24702
24703bool isVCVTPD2PH(unsigned Opcode) {
24704 switch (Opcode) {
24705 case VCVTPD2PHZ128rm:
24706 case VCVTPD2PHZ128rmb:
24707 case VCVTPD2PHZ128rmbk:
24708 case VCVTPD2PHZ128rmbkz:
24709 case VCVTPD2PHZ128rmk:
24710 case VCVTPD2PHZ128rmkz:
24711 case VCVTPD2PHZ128rr:
24712 case VCVTPD2PHZ128rrk:
24713 case VCVTPD2PHZ128rrkz:
24714 case VCVTPD2PHZ256rm:
24715 case VCVTPD2PHZ256rmb:
24716 case VCVTPD2PHZ256rmbk:
24717 case VCVTPD2PHZ256rmbkz:
24718 case VCVTPD2PHZ256rmk:
24719 case VCVTPD2PHZ256rmkz:
24720 case VCVTPD2PHZ256rr:
24721 case VCVTPD2PHZ256rrk:
24722 case VCVTPD2PHZ256rrkz:
24723 case VCVTPD2PHZrm:
24724 case VCVTPD2PHZrmb:
24725 case VCVTPD2PHZrmbk:
24726 case VCVTPD2PHZrmbkz:
24727 case VCVTPD2PHZrmk:
24728 case VCVTPD2PHZrmkz:
24729 case VCVTPD2PHZrr:
24730 case VCVTPD2PHZrrb:
24731 case VCVTPD2PHZrrbk:
24732 case VCVTPD2PHZrrbkz:
24733 case VCVTPD2PHZrrk:
24734 case VCVTPD2PHZrrkz:
24735 return true;
24736 }
24737 return false;
24738}
24739
24740bool isSHLX(unsigned Opcode) {
24741 switch (Opcode) {
24742 case SHLX32rm:
24743 case SHLX32rm_EVEX:
24744 case SHLX32rr:
24745 case SHLX32rr_EVEX:
24746 case SHLX64rm:
24747 case SHLX64rm_EVEX:
24748 case SHLX64rr:
24749 case SHLX64rr_EVEX:
24750 return true;
24751 }
24752 return false;
24753}
24754
24755bool isVCVTSH2SD(unsigned Opcode) {
24756 switch (Opcode) {
24757 case VCVTSH2SDZrm_Int:
24758 case VCVTSH2SDZrmk_Int:
24759 case VCVTSH2SDZrmkz_Int:
24760 case VCVTSH2SDZrr_Int:
24761 case VCVTSH2SDZrrb_Int:
24762 case VCVTSH2SDZrrbk_Int:
24763 case VCVTSH2SDZrrbkz_Int:
24764 case VCVTSH2SDZrrk_Int:
24765 case VCVTSH2SDZrrkz_Int:
24766 return true;
24767 }
24768 return false;
24769}
24770
24771bool isVFMADD231SS(unsigned Opcode) {
24772 switch (Opcode) {
24773 case VFMADD231SSZm_Int:
24774 case VFMADD231SSZmk_Int:
24775 case VFMADD231SSZmkz_Int:
24776 case VFMADD231SSZr_Int:
24777 case VFMADD231SSZrb_Int:
24778 case VFMADD231SSZrbk_Int:
24779 case VFMADD231SSZrbkz_Int:
24780 case VFMADD231SSZrk_Int:
24781 case VFMADD231SSZrkz_Int:
24782 case VFMADD231SSm_Int:
24783 case VFMADD231SSr_Int:
24784 return true;
24785 }
24786 return false;
24787}
24788
24789bool isMOVNTSD(unsigned Opcode) {
24790 return Opcode == MOVNTSD;
24791}
24792
24793bool isFLDPI(unsigned Opcode) {
24794 return Opcode == FLDPI;
24795}
24796
24797bool isVCVTUSI2SS(unsigned Opcode) {
24798 switch (Opcode) {
24799 case VCVTUSI2SSZrm_Int:
24800 case VCVTUSI2SSZrr_Int:
24801 case VCVTUSI2SSZrrb_Int:
24802 case VCVTUSI642SSZrm_Int:
24803 case VCVTUSI642SSZrr_Int:
24804 case VCVTUSI642SSZrrb_Int:
24805 return true;
24806 }
24807 return false;
24808}
24809
24810bool isPMOVSXBD(unsigned Opcode) {
24811 switch (Opcode) {
24812 case PMOVSXBDrm:
24813 case PMOVSXBDrr:
24814 return true;
24815 }
24816 return false;
24817}
24818
24819bool isVPRORVQ(unsigned Opcode) {
24820 switch (Opcode) {
24821 case VPRORVQZ128rm:
24822 case VPRORVQZ128rmb:
24823 case VPRORVQZ128rmbk:
24824 case VPRORVQZ128rmbkz:
24825 case VPRORVQZ128rmk:
24826 case VPRORVQZ128rmkz:
24827 case VPRORVQZ128rr:
24828 case VPRORVQZ128rrk:
24829 case VPRORVQZ128rrkz:
24830 case VPRORVQZ256rm:
24831 case VPRORVQZ256rmb:
24832 case VPRORVQZ256rmbk:
24833 case VPRORVQZ256rmbkz:
24834 case VPRORVQZ256rmk:
24835 case VPRORVQZ256rmkz:
24836 case VPRORVQZ256rr:
24837 case VPRORVQZ256rrk:
24838 case VPRORVQZ256rrkz:
24839 case VPRORVQZrm:
24840 case VPRORVQZrmb:
24841 case VPRORVQZrmbk:
24842 case VPRORVQZrmbkz:
24843 case VPRORVQZrmk:
24844 case VPRORVQZrmkz:
24845 case VPRORVQZrr:
24846 case VPRORVQZrrk:
24847 case VPRORVQZrrkz:
24848 return true;
24849 }
24850 return false;
24851}
24852
24853bool isVPERMT2D(unsigned Opcode) {
24854 switch (Opcode) {
24855 case VPERMT2DZ128rm:
24856 case VPERMT2DZ128rmb:
24857 case VPERMT2DZ128rmbk:
24858 case VPERMT2DZ128rmbkz:
24859 case VPERMT2DZ128rmk:
24860 case VPERMT2DZ128rmkz:
24861 case VPERMT2DZ128rr:
24862 case VPERMT2DZ128rrk:
24863 case VPERMT2DZ128rrkz:
24864 case VPERMT2DZ256rm:
24865 case VPERMT2DZ256rmb:
24866 case VPERMT2DZ256rmbk:
24867 case VPERMT2DZ256rmbkz:
24868 case VPERMT2DZ256rmk:
24869 case VPERMT2DZ256rmkz:
24870 case VPERMT2DZ256rr:
24871 case VPERMT2DZ256rrk:
24872 case VPERMT2DZ256rrkz:
24873 case VPERMT2DZrm:
24874 case VPERMT2DZrmb:
24875 case VPERMT2DZrmbk:
24876 case VPERMT2DZrmbkz:
24877 case VPERMT2DZrmk:
24878 case VPERMT2DZrmkz:
24879 case VPERMT2DZrr:
24880 case VPERMT2DZrrk:
24881 case VPERMT2DZrrkz:
24882 return true;
24883 }
24884 return false;
24885}
24886
24887bool isADDSS(unsigned Opcode) {
24888 switch (Opcode) {
24889 case ADDSSrm_Int:
24890 case ADDSSrr_Int:
24891 return true;
24892 }
24893 return false;
24894}
24895
24896bool isAADD(unsigned Opcode) {
24897 switch (Opcode) {
24898 case AADD32mr:
24899 case AADD32mr_EVEX:
24900 case AADD64mr:
24901 case AADD64mr_EVEX:
24902 return true;
24903 }
24904 return false;
24905}
24906
24907bool isVPSRLVW(unsigned Opcode) {
24908 switch (Opcode) {
24909 case VPSRLVWZ128rm:
24910 case VPSRLVWZ128rmk:
24911 case VPSRLVWZ128rmkz:
24912 case VPSRLVWZ128rr:
24913 case VPSRLVWZ128rrk:
24914 case VPSRLVWZ128rrkz:
24915 case VPSRLVWZ256rm:
24916 case VPSRLVWZ256rmk:
24917 case VPSRLVWZ256rmkz:
24918 case VPSRLVWZ256rr:
24919 case VPSRLVWZ256rrk:
24920 case VPSRLVWZ256rrkz:
24921 case VPSRLVWZrm:
24922 case VPSRLVWZrmk:
24923 case VPSRLVWZrmkz:
24924 case VPSRLVWZrr:
24925 case VPSRLVWZrrk:
24926 case VPSRLVWZrrkz:
24927 return true;
24928 }
24929 return false;
24930}
24931
24932bool isVRSQRTPH(unsigned Opcode) {
24933 switch (Opcode) {
24934 case VRSQRTPHZ128m:
24935 case VRSQRTPHZ128mb:
24936 case VRSQRTPHZ128mbk:
24937 case VRSQRTPHZ128mbkz:
24938 case VRSQRTPHZ128mk:
24939 case VRSQRTPHZ128mkz:
24940 case VRSQRTPHZ128r:
24941 case VRSQRTPHZ128rk:
24942 case VRSQRTPHZ128rkz:
24943 case VRSQRTPHZ256m:
24944 case VRSQRTPHZ256mb:
24945 case VRSQRTPHZ256mbk:
24946 case VRSQRTPHZ256mbkz:
24947 case VRSQRTPHZ256mk:
24948 case VRSQRTPHZ256mkz:
24949 case VRSQRTPHZ256r:
24950 case VRSQRTPHZ256rk:
24951 case VRSQRTPHZ256rkz:
24952 case VRSQRTPHZm:
24953 case VRSQRTPHZmb:
24954 case VRSQRTPHZmbk:
24955 case VRSQRTPHZmbkz:
24956 case VRSQRTPHZmk:
24957 case VRSQRTPHZmkz:
24958 case VRSQRTPHZr:
24959 case VRSQRTPHZrk:
24960 case VRSQRTPHZrkz:
24961 return true;
24962 }
24963 return false;
24964}
24965
24966bool isVLDDQU(unsigned Opcode) {
24967 switch (Opcode) {
24968 case VLDDQUYrm:
24969 case VLDDQUrm:
24970 return true;
24971 }
24972 return false;
24973}
24974
24975bool isKMOVD(unsigned Opcode) {
24976 switch (Opcode) {
24977 case KMOVDkk:
24978 case KMOVDkk_EVEX:
24979 case KMOVDkm:
24980 case KMOVDkm_EVEX:
24981 case KMOVDkr:
24982 case KMOVDkr_EVEX:
24983 case KMOVDmk:
24984 case KMOVDmk_EVEX:
24985 case KMOVDrk:
24986 case KMOVDrk_EVEX:
24987 return true;
24988 }
24989 return false;
24990}
24991
24992bool isENCLV(unsigned Opcode) {
24993 return Opcode == ENCLV;
24994}
24995
24996bool isENCLU(unsigned Opcode) {
24997 return Opcode == ENCLU;
24998}
24999
25000bool isPREFETCHT1(unsigned Opcode) {
25001 return Opcode == PREFETCHT1;
25002}
25003
25004bool isRSQRTPS(unsigned Opcode) {
25005 switch (Opcode) {
25006 case RSQRTPSm:
25007 case RSQRTPSr:
25008 return true;
25009 }
25010 return false;
25011}
25012
25013bool isVCVTTSH2USI(unsigned Opcode) {
25014 switch (Opcode) {
25015 case VCVTTSH2USI64Zrm_Int:
25016 case VCVTTSH2USI64Zrr_Int:
25017 case VCVTTSH2USI64Zrrb_Int:
25018 case VCVTTSH2USIZrm_Int:
25019 case VCVTTSH2USIZrr_Int:
25020 case VCVTTSH2USIZrrb_Int:
25021 return true;
25022 }
25023 return false;
25024}
25025
25026bool isPADDB(unsigned Opcode) {
25027 switch (Opcode) {
25028 case MMX_PADDBrm:
25029 case MMX_PADDBrr:
25030 case PADDBrm:
25031 case PADDBrr:
25032 return true;
25033 }
25034 return false;
25035}
25036
25037bool isVMASKMOVDQU(unsigned Opcode) {
25038 return Opcode == VMASKMOVDQU64;
25039}
25040
25041bool isPUNPCKLBW(unsigned Opcode) {
25042 switch (Opcode) {
25043 case MMX_PUNPCKLBWrm:
25044 case MMX_PUNPCKLBWrr:
25045 case PUNPCKLBWrm:
25046 case PUNPCKLBWrr:
25047 return true;
25048 }
25049 return false;
25050}
25051
25052bool isMOV(unsigned Opcode) {
25053 switch (Opcode) {
25054 case MOV16ao16:
25055 case MOV16ao32:
25056 case MOV16mi:
25057 case MOV16mr:
25058 case MOV16ms:
25059 case MOV16o16a:
25060 case MOV16o32a:
25061 case MOV16ri:
25062 case MOV16ri_alt:
25063 case MOV16rm:
25064 case MOV16rr:
25065 case MOV16rr_REV:
25066 case MOV16rs:
25067 case MOV16sm:
25068 case MOV16sr:
25069 case MOV32ao16:
25070 case MOV32ao32:
25071 case MOV32cr:
25072 case MOV32dr:
25073 case MOV32mi:
25074 case MOV32mr:
25075 case MOV32o16a:
25076 case MOV32o32a:
25077 case MOV32rc:
25078 case MOV32rd:
25079 case MOV32ri:
25080 case MOV32ri_alt:
25081 case MOV32rm:
25082 case MOV32rr:
25083 case MOV32rr_REV:
25084 case MOV32rs:
25085 case MOV32sr:
25086 case MOV64ao32:
25087 case MOV64cr:
25088 case MOV64dr:
25089 case MOV64mi32:
25090 case MOV64mr:
25091 case MOV64o32a:
25092 case MOV64rc:
25093 case MOV64rd:
25094 case MOV64ri32:
25095 case MOV64rm:
25096 case MOV64rr:
25097 case MOV64rr_REV:
25098 case MOV64rs:
25099 case MOV64sr:
25100 case MOV8ao16:
25101 case MOV8ao32:
25102 case MOV8mi:
25103 case MOV8mr:
25104 case MOV8o16a:
25105 case MOV8o32a:
25106 case MOV8ri:
25107 case MOV8ri_alt:
25108 case MOV8rm:
25109 case MOV8rr:
25110 case MOV8rr_REV:
25111 return true;
25112 }
25113 return false;
25114}
25115
25116bool isVCVTTPH2IUBS(unsigned Opcode) {
25117 switch (Opcode) {
25118 case VCVTTPH2IUBSZ128rm:
25119 case VCVTTPH2IUBSZ128rmb:
25120 case VCVTTPH2IUBSZ128rmbk:
25121 case VCVTTPH2IUBSZ128rmbkz:
25122 case VCVTTPH2IUBSZ128rmk:
25123 case VCVTTPH2IUBSZ128rmkz:
25124 case VCVTTPH2IUBSZ128rr:
25125 case VCVTTPH2IUBSZ128rrk:
25126 case VCVTTPH2IUBSZ128rrkz:
25127 case VCVTTPH2IUBSZ256rm:
25128 case VCVTTPH2IUBSZ256rmb:
25129 case VCVTTPH2IUBSZ256rmbk:
25130 case VCVTTPH2IUBSZ256rmbkz:
25131 case VCVTTPH2IUBSZ256rmk:
25132 case VCVTTPH2IUBSZ256rmkz:
25133 case VCVTTPH2IUBSZ256rr:
25134 case VCVTTPH2IUBSZ256rrk:
25135 case VCVTTPH2IUBSZ256rrkz:
25136 case VCVTTPH2IUBSZrm:
25137 case VCVTTPH2IUBSZrmb:
25138 case VCVTTPH2IUBSZrmbk:
25139 case VCVTTPH2IUBSZrmbkz:
25140 case VCVTTPH2IUBSZrmk:
25141 case VCVTTPH2IUBSZrmkz:
25142 case VCVTTPH2IUBSZrr:
25143 case VCVTTPH2IUBSZrrb:
25144 case VCVTTPH2IUBSZrrbk:
25145 case VCVTTPH2IUBSZrrbkz:
25146 case VCVTTPH2IUBSZrrk:
25147 case VCVTTPH2IUBSZrrkz:
25148 return true;
25149 }
25150 return false;
25151}
25152
25153bool isMUL(unsigned Opcode) {
25154 switch (Opcode) {
25155 case MUL16m:
25156 case MUL16m_EVEX:
25157 case MUL16m_NF:
25158 case MUL16r:
25159 case MUL16r_EVEX:
25160 case MUL16r_NF:
25161 case MUL32m:
25162 case MUL32m_EVEX:
25163 case MUL32m_NF:
25164 case MUL32r:
25165 case MUL32r_EVEX:
25166 case MUL32r_NF:
25167 case MUL64m:
25168 case MUL64m_EVEX:
25169 case MUL64m_NF:
25170 case MUL64r:
25171 case MUL64r_EVEX:
25172 case MUL64r_NF:
25173 case MUL8m:
25174 case MUL8m_EVEX:
25175 case MUL8m_NF:
25176 case MUL8r:
25177 case MUL8r_EVEX:
25178 case MUL8r_NF:
25179 return true;
25180 }
25181 return false;
25182}
25183
25184bool isRCL(unsigned Opcode) {
25185 switch (Opcode) {
25186 case RCL16m1:
25187 case RCL16m1_EVEX:
25188 case RCL16m1_ND:
25189 case RCL16mCL:
25190 case RCL16mCL_EVEX:
25191 case RCL16mCL_ND:
25192 case RCL16mi:
25193 case RCL16mi_EVEX:
25194 case RCL16mi_ND:
25195 case RCL16r1:
25196 case RCL16r1_EVEX:
25197 case RCL16r1_ND:
25198 case RCL16rCL:
25199 case RCL16rCL_EVEX:
25200 case RCL16rCL_ND:
25201 case RCL16ri:
25202 case RCL16ri_EVEX:
25203 case RCL16ri_ND:
25204 case RCL32m1:
25205 case RCL32m1_EVEX:
25206 case RCL32m1_ND:
25207 case RCL32mCL:
25208 case RCL32mCL_EVEX:
25209 case RCL32mCL_ND:
25210 case RCL32mi:
25211 case RCL32mi_EVEX:
25212 case RCL32mi_ND:
25213 case RCL32r1:
25214 case RCL32r1_EVEX:
25215 case RCL32r1_ND:
25216 case RCL32rCL:
25217 case RCL32rCL_EVEX:
25218 case RCL32rCL_ND:
25219 case RCL32ri:
25220 case RCL32ri_EVEX:
25221 case RCL32ri_ND:
25222 case RCL64m1:
25223 case RCL64m1_EVEX:
25224 case RCL64m1_ND:
25225 case RCL64mCL:
25226 case RCL64mCL_EVEX:
25227 case RCL64mCL_ND:
25228 case RCL64mi:
25229 case RCL64mi_EVEX:
25230 case RCL64mi_ND:
25231 case RCL64r1:
25232 case RCL64r1_EVEX:
25233 case RCL64r1_ND:
25234 case RCL64rCL:
25235 case RCL64rCL_EVEX:
25236 case RCL64rCL_ND:
25237 case RCL64ri:
25238 case RCL64ri_EVEX:
25239 case RCL64ri_ND:
25240 case RCL8m1:
25241 case RCL8m1_EVEX:
25242 case RCL8m1_ND:
25243 case RCL8mCL:
25244 case RCL8mCL_EVEX:
25245 case RCL8mCL_ND:
25246 case RCL8mi:
25247 case RCL8mi_EVEX:
25248 case RCL8mi_ND:
25249 case RCL8r1:
25250 case RCL8r1_EVEX:
25251 case RCL8r1_ND:
25252 case RCL8rCL:
25253 case RCL8rCL_EVEX:
25254 case RCL8rCL_ND:
25255 case RCL8ri:
25256 case RCL8ri_EVEX:
25257 case RCL8ri_ND:
25258 return true;
25259 }
25260 return false;
25261}
25262
25263bool isVRCPSH(unsigned Opcode) {
25264 switch (Opcode) {
25265 case VRCPSHZrm:
25266 case VRCPSHZrmk:
25267 case VRCPSHZrmkz:
25268 case VRCPSHZrr:
25269 case VRCPSHZrrk:
25270 case VRCPSHZrrkz:
25271 return true;
25272 }
25273 return false;
25274}
25275
25276bool isPFCMPEQ(unsigned Opcode) {
25277 switch (Opcode) {
25278 case PFCMPEQrm:
25279 case PFCMPEQrr:
25280 return true;
25281 }
25282 return false;
25283}
25284
25285bool isMONITOR(unsigned Opcode) {
25286 switch (Opcode) {
25287 case MONITOR32rrr:
25288 case MONITOR64rrr:
25289 return true;
25290 }
25291 return false;
25292}
25293
25294bool isFDIVR(unsigned Opcode) {
25295 switch (Opcode) {
25296 case DIVR_F32m:
25297 case DIVR_F64m:
25298 case DIVR_FST0r:
25299 case DIVR_FrST0:
25300 return true;
25301 }
25302 return false;
25303}
25304
25305bool isPFRCP(unsigned Opcode) {
25306 switch (Opcode) {
25307 case PFRCPrm:
25308 case PFRCPrr:
25309 return true;
25310 }
25311 return false;
25312}
25313
25314bool isPMINSD(unsigned Opcode) {
25315 switch (Opcode) {
25316 case PMINSDrm:
25317 case PMINSDrr:
25318 return true;
25319 }
25320 return false;
25321}
25322
25323bool isVSHUFF32X4(unsigned Opcode) {
25324 switch (Opcode) {
25325 case VSHUFF32X4Z256rmbi:
25326 case VSHUFF32X4Z256rmbik:
25327 case VSHUFF32X4Z256rmbikz:
25328 case VSHUFF32X4Z256rmi:
25329 case VSHUFF32X4Z256rmik:
25330 case VSHUFF32X4Z256rmikz:
25331 case VSHUFF32X4Z256rri:
25332 case VSHUFF32X4Z256rrik:
25333 case VSHUFF32X4Z256rrikz:
25334 case VSHUFF32X4Zrmbi:
25335 case VSHUFF32X4Zrmbik:
25336 case VSHUFF32X4Zrmbikz:
25337 case VSHUFF32X4Zrmi:
25338 case VSHUFF32X4Zrmik:
25339 case VSHUFF32X4Zrmikz:
25340 case VSHUFF32X4Zrri:
25341 case VSHUFF32X4Zrrik:
25342 case VSHUFF32X4Zrrikz:
25343 return true;
25344 }
25345 return false;
25346}
25347
25348bool isKTESTQ(unsigned Opcode) {
25349 return Opcode == KTESTQkk;
25350}
25351
25352bool isVCVTTPD2DQ(unsigned Opcode) {
25353 switch (Opcode) {
25354 case VCVTTPD2DQYrm:
25355 case VCVTTPD2DQYrr:
25356 case VCVTTPD2DQZ128rm:
25357 case VCVTTPD2DQZ128rmb:
25358 case VCVTTPD2DQZ128rmbk:
25359 case VCVTTPD2DQZ128rmbkz:
25360 case VCVTTPD2DQZ128rmk:
25361 case VCVTTPD2DQZ128rmkz:
25362 case VCVTTPD2DQZ128rr:
25363 case VCVTTPD2DQZ128rrk:
25364 case VCVTTPD2DQZ128rrkz:
25365 case VCVTTPD2DQZ256rm:
25366 case VCVTTPD2DQZ256rmb:
25367 case VCVTTPD2DQZ256rmbk:
25368 case VCVTTPD2DQZ256rmbkz:
25369 case VCVTTPD2DQZ256rmk:
25370 case VCVTTPD2DQZ256rmkz:
25371 case VCVTTPD2DQZ256rr:
25372 case VCVTTPD2DQZ256rrk:
25373 case VCVTTPD2DQZ256rrkz:
25374 case VCVTTPD2DQZrm:
25375 case VCVTTPD2DQZrmb:
25376 case VCVTTPD2DQZrmbk:
25377 case VCVTTPD2DQZrmbkz:
25378 case VCVTTPD2DQZrmk:
25379 case VCVTTPD2DQZrmkz:
25380 case VCVTTPD2DQZrr:
25381 case VCVTTPD2DQZrrb:
25382 case VCVTTPD2DQZrrbk:
25383 case VCVTTPD2DQZrrbkz:
25384 case VCVTTPD2DQZrrk:
25385 case VCVTTPD2DQZrrkz:
25386 case VCVTTPD2DQrm:
25387 case VCVTTPD2DQrr:
25388 return true;
25389 }
25390 return false;
25391}
25392
25393bool isVPSLLVW(unsigned Opcode) {
25394 switch (Opcode) {
25395 case VPSLLVWZ128rm:
25396 case VPSLLVWZ128rmk:
25397 case VPSLLVWZ128rmkz:
25398 case VPSLLVWZ128rr:
25399 case VPSLLVWZ128rrk:
25400 case VPSLLVWZ128rrkz:
25401 case VPSLLVWZ256rm:
25402 case VPSLLVWZ256rmk:
25403 case VPSLLVWZ256rmkz:
25404 case VPSLLVWZ256rr:
25405 case VPSLLVWZ256rrk:
25406 case VPSLLVWZ256rrkz:
25407 case VPSLLVWZrm:
25408 case VPSLLVWZrmk:
25409 case VPSLLVWZrmkz:
25410 case VPSLLVWZrr:
25411 case VPSLLVWZrrk:
25412 case VPSLLVWZrrkz:
25413 return true;
25414 }
25415 return false;
25416}
25417
25418bool isTDPBSUD(unsigned Opcode) {
25419 return Opcode == TDPBSUD;
25420}
25421
25422bool isVPMINUQ(unsigned Opcode) {
25423 switch (Opcode) {
25424 case VPMINUQZ128rm:
25425 case VPMINUQZ128rmb:
25426 case VPMINUQZ128rmbk:
25427 case VPMINUQZ128rmbkz:
25428 case VPMINUQZ128rmk:
25429 case VPMINUQZ128rmkz:
25430 case VPMINUQZ128rr:
25431 case VPMINUQZ128rrk:
25432 case VPMINUQZ128rrkz:
25433 case VPMINUQZ256rm:
25434 case VPMINUQZ256rmb:
25435 case VPMINUQZ256rmbk:
25436 case VPMINUQZ256rmbkz:
25437 case VPMINUQZ256rmk:
25438 case VPMINUQZ256rmkz:
25439 case VPMINUQZ256rr:
25440 case VPMINUQZ256rrk:
25441 case VPMINUQZ256rrkz:
25442 case VPMINUQZrm:
25443 case VPMINUQZrmb:
25444 case VPMINUQZrmbk:
25445 case VPMINUQZrmbkz:
25446 case VPMINUQZrmk:
25447 case VPMINUQZrmkz:
25448 case VPMINUQZrr:
25449 case VPMINUQZrrk:
25450 case VPMINUQZrrkz:
25451 return true;
25452 }
25453 return false;
25454}
25455
25456bool isFIADD(unsigned Opcode) {
25457 switch (Opcode) {
25458 case ADD_FI16m:
25459 case ADD_FI32m:
25460 return true;
25461 }
25462 return false;
25463}
25464
25465bool isFCMOVNU(unsigned Opcode) {
25466 return Opcode == CMOVNP_F;
25467}
25468
25469bool isVHSUBPD(unsigned Opcode) {
25470 switch (Opcode) {
25471 case VHSUBPDYrm:
25472 case VHSUBPDYrr:
25473 case VHSUBPDrm:
25474 case VHSUBPDrr:
25475 return true;
25476 }
25477 return false;
25478}
25479
25480bool isKSHIFTRQ(unsigned Opcode) {
25481 return Opcode == KSHIFTRQki;
25482}
25483
25484bool isMOVUPS(unsigned Opcode) {
25485 switch (Opcode) {
25486 case MOVUPSmr:
25487 case MOVUPSrm:
25488 case MOVUPSrr:
25489 case MOVUPSrr_REV:
25490 return true;
25491 }
25492 return false;
25493}
25494
25495bool isVMCALL(unsigned Opcode) {
25496 return Opcode == VMCALL;
25497}
25498
25499bool isXADD(unsigned Opcode) {
25500 switch (Opcode) {
25501 case XADD16rm:
25502 case XADD16rr:
25503 case XADD32rm:
25504 case XADD32rr:
25505 case XADD64rm:
25506 case XADD64rr:
25507 case XADD8rm:
25508 case XADD8rr:
25509 return true;
25510 }
25511 return false;
25512}
25513
25514bool isXRSTOR(unsigned Opcode) {
25515 return Opcode == XRSTOR;
25516}
25517
25518bool isVGATHERPF1DPD(unsigned Opcode) {
25519 return Opcode == VGATHERPF1DPDm;
25520}
25521
25522bool isRCR(unsigned Opcode) {
25523 switch (Opcode) {
25524 case RCR16m1:
25525 case RCR16m1_EVEX:
25526 case RCR16m1_ND:
25527 case RCR16mCL:
25528 case RCR16mCL_EVEX:
25529 case RCR16mCL_ND:
25530 case RCR16mi:
25531 case RCR16mi_EVEX:
25532 case RCR16mi_ND:
25533 case RCR16r1:
25534 case RCR16r1_EVEX:
25535 case RCR16r1_ND:
25536 case RCR16rCL:
25537 case RCR16rCL_EVEX:
25538 case RCR16rCL_ND:
25539 case RCR16ri:
25540 case RCR16ri_EVEX:
25541 case RCR16ri_ND:
25542 case RCR32m1:
25543 case RCR32m1_EVEX:
25544 case RCR32m1_ND:
25545 case RCR32mCL:
25546 case RCR32mCL_EVEX:
25547 case RCR32mCL_ND:
25548 case RCR32mi:
25549 case RCR32mi_EVEX:
25550 case RCR32mi_ND:
25551 case RCR32r1:
25552 case RCR32r1_EVEX:
25553 case RCR32r1_ND:
25554 case RCR32rCL:
25555 case RCR32rCL_EVEX:
25556 case RCR32rCL_ND:
25557 case RCR32ri:
25558 case RCR32ri_EVEX:
25559 case RCR32ri_ND:
25560 case RCR64m1:
25561 case RCR64m1_EVEX:
25562 case RCR64m1_ND:
25563 case RCR64mCL:
25564 case RCR64mCL_EVEX:
25565 case RCR64mCL_ND:
25566 case RCR64mi:
25567 case RCR64mi_EVEX:
25568 case RCR64mi_ND:
25569 case RCR64r1:
25570 case RCR64r1_EVEX:
25571 case RCR64r1_ND:
25572 case RCR64rCL:
25573 case RCR64rCL_EVEX:
25574 case RCR64rCL_ND:
25575 case RCR64ri:
25576 case RCR64ri_EVEX:
25577 case RCR64ri_ND:
25578 case RCR8m1:
25579 case RCR8m1_EVEX:
25580 case RCR8m1_ND:
25581 case RCR8mCL:
25582 case RCR8mCL_EVEX:
25583 case RCR8mCL_ND:
25584 case RCR8mi:
25585 case RCR8mi_EVEX:
25586 case RCR8mi_ND:
25587 case RCR8r1:
25588 case RCR8r1_EVEX:
25589 case RCR8r1_ND:
25590 case RCR8rCL:
25591 case RCR8rCL_EVEX:
25592 case RCR8rCL_ND:
25593 case RCR8ri:
25594 case RCR8ri_EVEX:
25595 case RCR8ri_ND:
25596 return true;
25597 }
25598 return false;
25599}
25600
25601bool isFNSTCW(unsigned Opcode) {
25602 return Opcode == FNSTCW16m;
25603}
25604
25605bool isVPMOVSDW(unsigned Opcode) {
25606 switch (Opcode) {
25607 case VPMOVSDWZ128mr:
25608 case VPMOVSDWZ128mrk:
25609 case VPMOVSDWZ128rr:
25610 case VPMOVSDWZ128rrk:
25611 case VPMOVSDWZ128rrkz:
25612 case VPMOVSDWZ256mr:
25613 case VPMOVSDWZ256mrk:
25614 case VPMOVSDWZ256rr:
25615 case VPMOVSDWZ256rrk:
25616 case VPMOVSDWZ256rrkz:
25617 case VPMOVSDWZmr:
25618 case VPMOVSDWZmrk:
25619 case VPMOVSDWZrr:
25620 case VPMOVSDWZrrk:
25621 case VPMOVSDWZrrkz:
25622 return true;
25623 }
25624 return false;
25625}
25626
25627bool isVFMSUB132SH(unsigned Opcode) {
25628 switch (Opcode) {
25629 case VFMSUB132SHZm_Int:
25630 case VFMSUB132SHZmk_Int:
25631 case VFMSUB132SHZmkz_Int:
25632 case VFMSUB132SHZr_Int:
25633 case VFMSUB132SHZrb_Int:
25634 case VFMSUB132SHZrbk_Int:
25635 case VFMSUB132SHZrbkz_Int:
25636 case VFMSUB132SHZrk_Int:
25637 case VFMSUB132SHZrkz_Int:
25638 return true;
25639 }
25640 return false;
25641}
25642
25643bool isVPCONFLICTQ(unsigned Opcode) {
25644 switch (Opcode) {
25645 case VPCONFLICTQZ128rm:
25646 case VPCONFLICTQZ128rmb:
25647 case VPCONFLICTQZ128rmbk:
25648 case VPCONFLICTQZ128rmbkz:
25649 case VPCONFLICTQZ128rmk:
25650 case VPCONFLICTQZ128rmkz:
25651 case VPCONFLICTQZ128rr:
25652 case VPCONFLICTQZ128rrk:
25653 case VPCONFLICTQZ128rrkz:
25654 case VPCONFLICTQZ256rm:
25655 case VPCONFLICTQZ256rmb:
25656 case VPCONFLICTQZ256rmbk:
25657 case VPCONFLICTQZ256rmbkz:
25658 case VPCONFLICTQZ256rmk:
25659 case VPCONFLICTQZ256rmkz:
25660 case VPCONFLICTQZ256rr:
25661 case VPCONFLICTQZ256rrk:
25662 case VPCONFLICTQZ256rrkz:
25663 case VPCONFLICTQZrm:
25664 case VPCONFLICTQZrmb:
25665 case VPCONFLICTQZrmbk:
25666 case VPCONFLICTQZrmbkz:
25667 case VPCONFLICTQZrmk:
25668 case VPCONFLICTQZrmkz:
25669 case VPCONFLICTQZrr:
25670 case VPCONFLICTQZrrk:
25671 case VPCONFLICTQZrrkz:
25672 return true;
25673 }
25674 return false;
25675}
25676
25677bool isSWAPGS(unsigned Opcode) {
25678 return Opcode == SWAPGS;
25679}
25680
25681bool isVPMOVQ2M(unsigned Opcode) {
25682 switch (Opcode) {
25683 case VPMOVQ2MZ128kr:
25684 case VPMOVQ2MZ256kr:
25685 case VPMOVQ2MZkr:
25686 return true;
25687 }
25688 return false;
25689}
25690
25691bool isVPSRAVW(unsigned Opcode) {
25692 switch (Opcode) {
25693 case VPSRAVWZ128rm:
25694 case VPSRAVWZ128rmk:
25695 case VPSRAVWZ128rmkz:
25696 case VPSRAVWZ128rr:
25697 case VPSRAVWZ128rrk:
25698 case VPSRAVWZ128rrkz:
25699 case VPSRAVWZ256rm:
25700 case VPSRAVWZ256rmk:
25701 case VPSRAVWZ256rmkz:
25702 case VPSRAVWZ256rr:
25703 case VPSRAVWZ256rrk:
25704 case VPSRAVWZ256rrkz:
25705 case VPSRAVWZrm:
25706 case VPSRAVWZrmk:
25707 case VPSRAVWZrmkz:
25708 case VPSRAVWZrr:
25709 case VPSRAVWZrrk:
25710 case VPSRAVWZrrkz:
25711 return true;
25712 }
25713 return false;
25714}
25715
25716bool isSHA256MSG2(unsigned Opcode) {
25717 switch (Opcode) {
25718 case SHA256MSG2rm:
25719 case SHA256MSG2rr:
25720 return true;
25721 }
25722 return false;
25723}
25724
25725bool isDIVSD(unsigned Opcode) {
25726 switch (Opcode) {
25727 case DIVSDrm_Int:
25728 case DIVSDrr_Int:
25729 return true;
25730 }
25731 return false;
25732}
25733
25734bool isPCMPGTB(unsigned Opcode) {
25735 switch (Opcode) {
25736 case MMX_PCMPGTBrm:
25737 case MMX_PCMPGTBrr:
25738 case PCMPGTBrm:
25739 case PCMPGTBrr:
25740 return true;
25741 }
25742 return false;
25743}
25744
25745bool isMOVDQA(unsigned Opcode) {
25746 switch (Opcode) {
25747 case MOVDQAmr:
25748 case MOVDQArm:
25749 case MOVDQArr:
25750 case MOVDQArr_REV:
25751 return true;
25752 }
25753 return false;
25754}
25755
25756bool isVAESENCLAST(unsigned Opcode) {
25757 switch (Opcode) {
25758 case VAESENCLASTYrm:
25759 case VAESENCLASTYrr:
25760 case VAESENCLASTZ128rm:
25761 case VAESENCLASTZ128rr:
25762 case VAESENCLASTZ256rm:
25763 case VAESENCLASTZ256rr:
25764 case VAESENCLASTZrm:
25765 case VAESENCLASTZrr:
25766 case VAESENCLASTrm:
25767 case VAESENCLASTrr:
25768 return true;
25769 }
25770 return false;
25771}
25772
25773bool isKXORW(unsigned Opcode) {
25774 return Opcode == KXORWkk;
25775}
25776
25777bool isLIDTW(unsigned Opcode) {
25778 return Opcode == LIDT16m;
25779}
25780
25781bool isPMULHW(unsigned Opcode) {
25782 switch (Opcode) {
25783 case MMX_PMULHWrm:
25784 case MMX_PMULHWrr:
25785 case PMULHWrm:
25786 case PMULHWrr:
25787 return true;
25788 }
25789 return false;
25790}
25791
25792bool isVINSERTI32X8(unsigned Opcode) {
25793 switch (Opcode) {
25794 case VINSERTI32X8Zrmi:
25795 case VINSERTI32X8Zrmik:
25796 case VINSERTI32X8Zrmikz:
25797 case VINSERTI32X8Zrri:
25798 case VINSERTI32X8Zrrik:
25799 case VINSERTI32X8Zrrikz:
25800 return true;
25801 }
25802 return false;
25803}
25804
25805bool isVRCPPS(unsigned Opcode) {
25806 switch (Opcode) {
25807 case VRCPPSYm:
25808 case VRCPPSYr:
25809 case VRCPPSm:
25810 case VRCPPSr:
25811 return true;
25812 }
25813 return false;
25814}
25815
25816bool isVRSQRTBF16(unsigned Opcode) {
25817 switch (Opcode) {
25818 case VRSQRTBF16Z128m:
25819 case VRSQRTBF16Z128mb:
25820 case VRSQRTBF16Z128mbk:
25821 case VRSQRTBF16Z128mbkz:
25822 case VRSQRTBF16Z128mk:
25823 case VRSQRTBF16Z128mkz:
25824 case VRSQRTBF16Z128r:
25825 case VRSQRTBF16Z128rk:
25826 case VRSQRTBF16Z128rkz:
25827 case VRSQRTBF16Z256m:
25828 case VRSQRTBF16Z256mb:
25829 case VRSQRTBF16Z256mbk:
25830 case VRSQRTBF16Z256mbkz:
25831 case VRSQRTBF16Z256mk:
25832 case VRSQRTBF16Z256mkz:
25833 case VRSQRTBF16Z256r:
25834 case VRSQRTBF16Z256rk:
25835 case VRSQRTBF16Z256rkz:
25836 case VRSQRTBF16Zm:
25837 case VRSQRTBF16Zmb:
25838 case VRSQRTBF16Zmbk:
25839 case VRSQRTBF16Zmbkz:
25840 case VRSQRTBF16Zmk:
25841 case VRSQRTBF16Zmkz:
25842 case VRSQRTBF16Zr:
25843 case VRSQRTBF16Zrk:
25844 case VRSQRTBF16Zrkz:
25845 return true;
25846 }
25847 return false;
25848}
25849
25850bool isVGATHERQPS(unsigned Opcode) {
25851 switch (Opcode) {
25852 case VGATHERQPSYrm:
25853 case VGATHERQPSZ128rm:
25854 case VGATHERQPSZ256rm:
25855 case VGATHERQPSZrm:
25856 case VGATHERQPSrm:
25857 return true;
25858 }
25859 return false;
25860}
25861
25862bool isCTESTCC(unsigned Opcode) {
25863 switch (Opcode) {
25864 case CTEST16mi:
25865 case CTEST16mr:
25866 case CTEST16ri:
25867 case CTEST16rr:
25868 case CTEST32mi:
25869 case CTEST32mr:
25870 case CTEST32ri:
25871 case CTEST32rr:
25872 case CTEST64mi32:
25873 case CTEST64mr:
25874 case CTEST64ri32:
25875 case CTEST64rr:
25876 case CTEST8mi:
25877 case CTEST8mr:
25878 case CTEST8ri:
25879 case CTEST8rr:
25880 return true;
25881 }
25882 return false;
25883}
25884
25885bool isPMADDWD(unsigned Opcode) {
25886 switch (Opcode) {
25887 case MMX_PMADDWDrm:
25888 case MMX_PMADDWDrr:
25889 case PMADDWDrm:
25890 case PMADDWDrr:
25891 return true;
25892 }
25893 return false;
25894}
25895
25896bool isUCOMISS(unsigned Opcode) {
25897 switch (Opcode) {
25898 case UCOMISSrm:
25899 case UCOMISSrr:
25900 return true;
25901 }
25902 return false;
25903}
25904
25905bool isXGETBV(unsigned Opcode) {
25906 return Opcode == XGETBV;
25907}
25908
25909bool isVCVTPD2QQ(unsigned Opcode) {
25910 switch (Opcode) {
25911 case VCVTPD2QQZ128rm:
25912 case VCVTPD2QQZ128rmb:
25913 case VCVTPD2QQZ128rmbk:
25914 case VCVTPD2QQZ128rmbkz:
25915 case VCVTPD2QQZ128rmk:
25916 case VCVTPD2QQZ128rmkz:
25917 case VCVTPD2QQZ128rr:
25918 case VCVTPD2QQZ128rrk:
25919 case VCVTPD2QQZ128rrkz:
25920 case VCVTPD2QQZ256rm:
25921 case VCVTPD2QQZ256rmb:
25922 case VCVTPD2QQZ256rmbk:
25923 case VCVTPD2QQZ256rmbkz:
25924 case VCVTPD2QQZ256rmk:
25925 case VCVTPD2QQZ256rmkz:
25926 case VCVTPD2QQZ256rr:
25927 case VCVTPD2QQZ256rrk:
25928 case VCVTPD2QQZ256rrkz:
25929 case VCVTPD2QQZrm:
25930 case VCVTPD2QQZrmb:
25931 case VCVTPD2QQZrmbk:
25932 case VCVTPD2QQZrmbkz:
25933 case VCVTPD2QQZrmk:
25934 case VCVTPD2QQZrmkz:
25935 case VCVTPD2QQZrr:
25936 case VCVTPD2QQZrrb:
25937 case VCVTPD2QQZrrbk:
25938 case VCVTPD2QQZrrbkz:
25939 case VCVTPD2QQZrrk:
25940 case VCVTPD2QQZrrkz:
25941 return true;
25942 }
25943 return false;
25944}
25945
25946bool isVGETEXPPS(unsigned Opcode) {
25947 switch (Opcode) {
25948 case VGETEXPPSZ128m:
25949 case VGETEXPPSZ128mb:
25950 case VGETEXPPSZ128mbk:
25951 case VGETEXPPSZ128mbkz:
25952 case VGETEXPPSZ128mk:
25953 case VGETEXPPSZ128mkz:
25954 case VGETEXPPSZ128r:
25955 case VGETEXPPSZ128rk:
25956 case VGETEXPPSZ128rkz:
25957 case VGETEXPPSZ256m:
25958 case VGETEXPPSZ256mb:
25959 case VGETEXPPSZ256mbk:
25960 case VGETEXPPSZ256mbkz:
25961 case VGETEXPPSZ256mk:
25962 case VGETEXPPSZ256mkz:
25963 case VGETEXPPSZ256r:
25964 case VGETEXPPSZ256rk:
25965 case VGETEXPPSZ256rkz:
25966 case VGETEXPPSZm:
25967 case VGETEXPPSZmb:
25968 case VGETEXPPSZmbk:
25969 case VGETEXPPSZmbkz:
25970 case VGETEXPPSZmk:
25971 case VGETEXPPSZmkz:
25972 case VGETEXPPSZr:
25973 case VGETEXPPSZrb:
25974 case VGETEXPPSZrbk:
25975 case VGETEXPPSZrbkz:
25976 case VGETEXPPSZrk:
25977 case VGETEXPPSZrkz:
25978 return true;
25979 }
25980 return false;
25981}
25982
25983bool isFISTP(unsigned Opcode) {
25984 switch (Opcode) {
25985 case IST_FP16m:
25986 case IST_FP32m:
25987 case IST_FP64m:
25988 return true;
25989 }
25990 return false;
25991}
25992
25993bool isVINSERTF64X4(unsigned Opcode) {
25994 switch (Opcode) {
25995 case VINSERTF64X4Zrmi:
25996 case VINSERTF64X4Zrmik:
25997 case VINSERTF64X4Zrmikz:
25998 case VINSERTF64X4Zrri:
25999 case VINSERTF64X4Zrrik:
26000 case VINSERTF64X4Zrrikz:
26001 return true;
26002 }
26003 return false;
26004}
26005
26006bool isVMOVDQU16(unsigned Opcode) {
26007 switch (Opcode) {
26008 case VMOVDQU16Z128mr:
26009 case VMOVDQU16Z128mrk:
26010 case VMOVDQU16Z128rm:
26011 case VMOVDQU16Z128rmk:
26012 case VMOVDQU16Z128rmkz:
26013 case VMOVDQU16Z128rr:
26014 case VMOVDQU16Z128rr_REV:
26015 case VMOVDQU16Z128rrk:
26016 case VMOVDQU16Z128rrk_REV:
26017 case VMOVDQU16Z128rrkz:
26018 case VMOVDQU16Z128rrkz_REV:
26019 case VMOVDQU16Z256mr:
26020 case VMOVDQU16Z256mrk:
26021 case VMOVDQU16Z256rm:
26022 case VMOVDQU16Z256rmk:
26023 case VMOVDQU16Z256rmkz:
26024 case VMOVDQU16Z256rr:
26025 case VMOVDQU16Z256rr_REV:
26026 case VMOVDQU16Z256rrk:
26027 case VMOVDQU16Z256rrk_REV:
26028 case VMOVDQU16Z256rrkz:
26029 case VMOVDQU16Z256rrkz_REV:
26030 case VMOVDQU16Zmr:
26031 case VMOVDQU16Zmrk:
26032 case VMOVDQU16Zrm:
26033 case VMOVDQU16Zrmk:
26034 case VMOVDQU16Zrmkz:
26035 case VMOVDQU16Zrr:
26036 case VMOVDQU16Zrr_REV:
26037 case VMOVDQU16Zrrk:
26038 case VMOVDQU16Zrrk_REV:
26039 case VMOVDQU16Zrrkz:
26040 case VMOVDQU16Zrrkz_REV:
26041 return true;
26042 }
26043 return false;
26044}
26045
26046bool isVFMADD132PH(unsigned Opcode) {
26047 switch (Opcode) {
26048 case VFMADD132PHZ128m:
26049 case VFMADD132PHZ128mb:
26050 case VFMADD132PHZ128mbk:
26051 case VFMADD132PHZ128mbkz:
26052 case VFMADD132PHZ128mk:
26053 case VFMADD132PHZ128mkz:
26054 case VFMADD132PHZ128r:
26055 case VFMADD132PHZ128rk:
26056 case VFMADD132PHZ128rkz:
26057 case VFMADD132PHZ256m:
26058 case VFMADD132PHZ256mb:
26059 case VFMADD132PHZ256mbk:
26060 case VFMADD132PHZ256mbkz:
26061 case VFMADD132PHZ256mk:
26062 case VFMADD132PHZ256mkz:
26063 case VFMADD132PHZ256r:
26064 case VFMADD132PHZ256rk:
26065 case VFMADD132PHZ256rkz:
26066 case VFMADD132PHZm:
26067 case VFMADD132PHZmb:
26068 case VFMADD132PHZmbk:
26069 case VFMADD132PHZmbkz:
26070 case VFMADD132PHZmk:
26071 case VFMADD132PHZmkz:
26072 case VFMADD132PHZr:
26073 case VFMADD132PHZrb:
26074 case VFMADD132PHZrbk:
26075 case VFMADD132PHZrbkz:
26076 case VFMADD132PHZrk:
26077 case VFMADD132PHZrkz:
26078 return true;
26079 }
26080 return false;
26081}
26082
26083bool isVFMSUBADD213PS(unsigned Opcode) {
26084 switch (Opcode) {
26085 case VFMSUBADD213PSYm:
26086 case VFMSUBADD213PSYr:
26087 case VFMSUBADD213PSZ128m:
26088 case VFMSUBADD213PSZ128mb:
26089 case VFMSUBADD213PSZ128mbk:
26090 case VFMSUBADD213PSZ128mbkz:
26091 case VFMSUBADD213PSZ128mk:
26092 case VFMSUBADD213PSZ128mkz:
26093 case VFMSUBADD213PSZ128r:
26094 case VFMSUBADD213PSZ128rk:
26095 case VFMSUBADD213PSZ128rkz:
26096 case VFMSUBADD213PSZ256m:
26097 case VFMSUBADD213PSZ256mb:
26098 case VFMSUBADD213PSZ256mbk:
26099 case VFMSUBADD213PSZ256mbkz:
26100 case VFMSUBADD213PSZ256mk:
26101 case VFMSUBADD213PSZ256mkz:
26102 case VFMSUBADD213PSZ256r:
26103 case VFMSUBADD213PSZ256rk:
26104 case VFMSUBADD213PSZ256rkz:
26105 case VFMSUBADD213PSZm:
26106 case VFMSUBADD213PSZmb:
26107 case VFMSUBADD213PSZmbk:
26108 case VFMSUBADD213PSZmbkz:
26109 case VFMSUBADD213PSZmk:
26110 case VFMSUBADD213PSZmkz:
26111 case VFMSUBADD213PSZr:
26112 case VFMSUBADD213PSZrb:
26113 case VFMSUBADD213PSZrbk:
26114 case VFMSUBADD213PSZrbkz:
26115 case VFMSUBADD213PSZrk:
26116 case VFMSUBADD213PSZrkz:
26117 case VFMSUBADD213PSm:
26118 case VFMSUBADD213PSr:
26119 return true;
26120 }
26121 return false;
26122}
26123
26124bool isVMOVDQU32(unsigned Opcode) {
26125 switch (Opcode) {
26126 case VMOVDQU32Z128mr:
26127 case VMOVDQU32Z128mrk:
26128 case VMOVDQU32Z128rm:
26129 case VMOVDQU32Z128rmk:
26130 case VMOVDQU32Z128rmkz:
26131 case VMOVDQU32Z128rr:
26132 case VMOVDQU32Z128rr_REV:
26133 case VMOVDQU32Z128rrk:
26134 case VMOVDQU32Z128rrk_REV:
26135 case VMOVDQU32Z128rrkz:
26136 case VMOVDQU32Z128rrkz_REV:
26137 case VMOVDQU32Z256mr:
26138 case VMOVDQU32Z256mrk:
26139 case VMOVDQU32Z256rm:
26140 case VMOVDQU32Z256rmk:
26141 case VMOVDQU32Z256rmkz:
26142 case VMOVDQU32Z256rr:
26143 case VMOVDQU32Z256rr_REV:
26144 case VMOVDQU32Z256rrk:
26145 case VMOVDQU32Z256rrk_REV:
26146 case VMOVDQU32Z256rrkz:
26147 case VMOVDQU32Z256rrkz_REV:
26148 case VMOVDQU32Zmr:
26149 case VMOVDQU32Zmrk:
26150 case VMOVDQU32Zrm:
26151 case VMOVDQU32Zrmk:
26152 case VMOVDQU32Zrmkz:
26153 case VMOVDQU32Zrr:
26154 case VMOVDQU32Zrr_REV:
26155 case VMOVDQU32Zrrk:
26156 case VMOVDQU32Zrrk_REV:
26157 case VMOVDQU32Zrrkz:
26158 case VMOVDQU32Zrrkz_REV:
26159 return true;
26160 }
26161 return false;
26162}
26163
26164bool isFUCOM(unsigned Opcode) {
26165 return Opcode == UCOM_Fr;
26166}
26167
26168bool isVFNMADD213BF16(unsigned Opcode) {
26169 switch (Opcode) {
26170 case VFNMADD213BF16Z128m:
26171 case VFNMADD213BF16Z128mb:
26172 case VFNMADD213BF16Z128mbk:
26173 case VFNMADD213BF16Z128mbkz:
26174 case VFNMADD213BF16Z128mk:
26175 case VFNMADD213BF16Z128mkz:
26176 case VFNMADD213BF16Z128r:
26177 case VFNMADD213BF16Z128rk:
26178 case VFNMADD213BF16Z128rkz:
26179 case VFNMADD213BF16Z256m:
26180 case VFNMADD213BF16Z256mb:
26181 case VFNMADD213BF16Z256mbk:
26182 case VFNMADD213BF16Z256mbkz:
26183 case VFNMADD213BF16Z256mk:
26184 case VFNMADD213BF16Z256mkz:
26185 case VFNMADD213BF16Z256r:
26186 case VFNMADD213BF16Z256rk:
26187 case VFNMADD213BF16Z256rkz:
26188 case VFNMADD213BF16Zm:
26189 case VFNMADD213BF16Zmb:
26190 case VFNMADD213BF16Zmbk:
26191 case VFNMADD213BF16Zmbkz:
26192 case VFNMADD213BF16Zmk:
26193 case VFNMADD213BF16Zmkz:
26194 case VFNMADD213BF16Zr:
26195 case VFNMADD213BF16Zrk:
26196 case VFNMADD213BF16Zrkz:
26197 return true;
26198 }
26199 return false;
26200}
26201
26202bool isHADDPS(unsigned Opcode) {
26203 switch (Opcode) {
26204 case HADDPSrm:
26205 case HADDPSrr:
26206 return true;
26207 }
26208 return false;
26209}
26210
26211bool isCMP(unsigned Opcode) {
26212 switch (Opcode) {
26213 case CMP16i16:
26214 case CMP16mi:
26215 case CMP16mi8:
26216 case CMP16mr:
26217 case CMP16ri:
26218 case CMP16ri8:
26219 case CMP16rm:
26220 case CMP16rr:
26221 case CMP16rr_REV:
26222 case CMP32i32:
26223 case CMP32mi:
26224 case CMP32mi8:
26225 case CMP32mr:
26226 case CMP32ri:
26227 case CMP32ri8:
26228 case CMP32rm:
26229 case CMP32rr:
26230 case CMP32rr_REV:
26231 case CMP64i32:
26232 case CMP64mi32:
26233 case CMP64mi8:
26234 case CMP64mr:
26235 case CMP64ri32:
26236 case CMP64ri8:
26237 case CMP64rm:
26238 case CMP64rr:
26239 case CMP64rr_REV:
26240 case CMP8i8:
26241 case CMP8mi:
26242 case CMP8mi8:
26243 case CMP8mr:
26244 case CMP8ri:
26245 case CMP8ri8:
26246 case CMP8rm:
26247 case CMP8rr:
26248 case CMP8rr_REV:
26249 return true;
26250 }
26251 return false;
26252}
26253
26254bool isCVTTPS2PI(unsigned Opcode) {
26255 switch (Opcode) {
26256 case MMX_CVTTPS2PIrm:
26257 case MMX_CVTTPS2PIrr:
26258 return true;
26259 }
26260 return false;
26261}
26262
26263bool isIRETQ(unsigned Opcode) {
26264 return Opcode == IRET64;
26265}
26266
26267bool isPF2IW(unsigned Opcode) {
26268 switch (Opcode) {
26269 case PF2IWrm:
26270 case PF2IWrr:
26271 return true;
26272 }
26273 return false;
26274}
26275
26276bool isPSHUFD(unsigned Opcode) {
26277 switch (Opcode) {
26278 case PSHUFDmi:
26279 case PSHUFDri:
26280 return true;
26281 }
26282 return false;
26283}
26284
26285bool isVDPPD(unsigned Opcode) {
26286 switch (Opcode) {
26287 case VDPPDrmi:
26288 case VDPPDrri:
26289 return true;
26290 }
26291 return false;
26292}
26293
26294bool isPSHUFHW(unsigned Opcode) {
26295 switch (Opcode) {
26296 case PSHUFHWmi:
26297 case PSHUFHWri:
26298 return true;
26299 }
26300 return false;
26301}
26302
26303bool isRMPADJUST(unsigned Opcode) {
26304 return Opcode == RMPADJUST;
26305}
26306
26307bool isPI2FW(unsigned Opcode) {
26308 switch (Opcode) {
26309 case PI2FWrm:
26310 case PI2FWrr:
26311 return true;
26312 }
26313 return false;
26314}
26315
26316bool isVCVTTPH2QQ(unsigned Opcode) {
26317 switch (Opcode) {
26318 case VCVTTPH2QQZ128rm:
26319 case VCVTTPH2QQZ128rmb:
26320 case VCVTTPH2QQZ128rmbk:
26321 case VCVTTPH2QQZ128rmbkz:
26322 case VCVTTPH2QQZ128rmk:
26323 case VCVTTPH2QQZ128rmkz:
26324 case VCVTTPH2QQZ128rr:
26325 case VCVTTPH2QQZ128rrk:
26326 case VCVTTPH2QQZ128rrkz:
26327 case VCVTTPH2QQZ256rm:
26328 case VCVTTPH2QQZ256rmb:
26329 case VCVTTPH2QQZ256rmbk:
26330 case VCVTTPH2QQZ256rmbkz:
26331 case VCVTTPH2QQZ256rmk:
26332 case VCVTTPH2QQZ256rmkz:
26333 case VCVTTPH2QQZ256rr:
26334 case VCVTTPH2QQZ256rrk:
26335 case VCVTTPH2QQZ256rrkz:
26336 case VCVTTPH2QQZrm:
26337 case VCVTTPH2QQZrmb:
26338 case VCVTTPH2QQZrmbk:
26339 case VCVTTPH2QQZrmbkz:
26340 case VCVTTPH2QQZrmk:
26341 case VCVTTPH2QQZrmkz:
26342 case VCVTTPH2QQZrr:
26343 case VCVTTPH2QQZrrb:
26344 case VCVTTPH2QQZrrbk:
26345 case VCVTTPH2QQZrrbkz:
26346 case VCVTTPH2QQZrrk:
26347 case VCVTTPH2QQZrrkz:
26348 return true;
26349 }
26350 return false;
26351}
26352
26353bool isDIVPD(unsigned Opcode) {
26354 switch (Opcode) {
26355 case DIVPDrm:
26356 case DIVPDrr:
26357 return true;
26358 }
26359 return false;
26360}
26361
26362bool isCLFLUSH(unsigned Opcode) {
26363 return Opcode == CLFLUSH;
26364}
26365
26366bool isVPMINUW(unsigned Opcode) {
26367 switch (Opcode) {
26368 case VPMINUWYrm:
26369 case VPMINUWYrr:
26370 case VPMINUWZ128rm:
26371 case VPMINUWZ128rmk:
26372 case VPMINUWZ128rmkz:
26373 case VPMINUWZ128rr:
26374 case VPMINUWZ128rrk:
26375 case VPMINUWZ128rrkz:
26376 case VPMINUWZ256rm:
26377 case VPMINUWZ256rmk:
26378 case VPMINUWZ256rmkz:
26379 case VPMINUWZ256rr:
26380 case VPMINUWZ256rrk:
26381 case VPMINUWZ256rrkz:
26382 case VPMINUWZrm:
26383 case VPMINUWZrmk:
26384 case VPMINUWZrmkz:
26385 case VPMINUWZrr:
26386 case VPMINUWZrrk:
26387 case VPMINUWZrrkz:
26388 case VPMINUWrm:
26389 case VPMINUWrr:
26390 return true;
26391 }
26392 return false;
26393}
26394
26395bool isIN(unsigned Opcode) {
26396 switch (Opcode) {
26397 case IN16ri:
26398 case IN16rr:
26399 case IN32ri:
26400 case IN32rr:
26401 case IN8ri:
26402 case IN8rr:
26403 return true;
26404 }
26405 return false;
26406}
26407
26408bool isWRPKRU(unsigned Opcode) {
26409 return Opcode == WRPKRUr;
26410}
26411
26412bool isINSERTPS(unsigned Opcode) {
26413 switch (Opcode) {
26414 case INSERTPSrmi:
26415 case INSERTPSrri:
26416 return true;
26417 }
26418 return false;
26419}
26420
26421bool isAAM(unsigned Opcode) {
26422 return Opcode == AAM8i8;
26423}
26424
26425bool isVPHADDUDQ(unsigned Opcode) {
26426 switch (Opcode) {
26427 case VPHADDUDQrm:
26428 case VPHADDUDQrr:
26429 return true;
26430 }
26431 return false;
26432}
26433
26434bool isVSHA512MSG1(unsigned Opcode) {
26435 return Opcode == VSHA512MSG1rr;
26436}
26437
26438bool isDIVPS(unsigned Opcode) {
26439 switch (Opcode) {
26440 case DIVPSrm:
26441 case DIVPSrr:
26442 return true;
26443 }
26444 return false;
26445}
26446
26447bool isKNOTB(unsigned Opcode) {
26448 return Opcode == KNOTBkk;
26449}
26450
26451bool isBLSFILL(unsigned Opcode) {
26452 switch (Opcode) {
26453 case BLSFILL32rm:
26454 case BLSFILL32rr:
26455 case BLSFILL64rm:
26456 case BLSFILL64rr:
26457 return true;
26458 }
26459 return false;
26460}
26461
26462bool isVPCMPGTQ(unsigned Opcode) {
26463 switch (Opcode) {
26464 case VPCMPGTQYrm:
26465 case VPCMPGTQYrr:
26466 case VPCMPGTQZ128rm:
26467 case VPCMPGTQZ128rmb:
26468 case VPCMPGTQZ128rmbk:
26469 case VPCMPGTQZ128rmk:
26470 case VPCMPGTQZ128rr:
26471 case VPCMPGTQZ128rrk:
26472 case VPCMPGTQZ256rm:
26473 case VPCMPGTQZ256rmb:
26474 case VPCMPGTQZ256rmbk:
26475 case VPCMPGTQZ256rmk:
26476 case VPCMPGTQZ256rr:
26477 case VPCMPGTQZ256rrk:
26478 case VPCMPGTQZrm:
26479 case VPCMPGTQZrmb:
26480 case VPCMPGTQZrmbk:
26481 case VPCMPGTQZrmk:
26482 case VPCMPGTQZrr:
26483 case VPCMPGTQZrrk:
26484 case VPCMPGTQrm:
26485 case VPCMPGTQrr:
26486 return true;
26487 }
26488 return false;
26489}
26490
26491bool isMINSD(unsigned Opcode) {
26492 switch (Opcode) {
26493 case MINSDrm_Int:
26494 case MINSDrr_Int:
26495 return true;
26496 }
26497 return false;
26498}
26499
26500bool isFPREM(unsigned Opcode) {
26501 return Opcode == FPREM;
26502}
26503
26504bool isVPUNPCKHQDQ(unsigned Opcode) {
26505 switch (Opcode) {
26506 case VPUNPCKHQDQYrm:
26507 case VPUNPCKHQDQYrr:
26508 case VPUNPCKHQDQZ128rm:
26509 case VPUNPCKHQDQZ128rmb:
26510 case VPUNPCKHQDQZ128rmbk:
26511 case VPUNPCKHQDQZ128rmbkz:
26512 case VPUNPCKHQDQZ128rmk:
26513 case VPUNPCKHQDQZ128rmkz:
26514 case VPUNPCKHQDQZ128rr:
26515 case VPUNPCKHQDQZ128rrk:
26516 case VPUNPCKHQDQZ128rrkz:
26517 case VPUNPCKHQDQZ256rm:
26518 case VPUNPCKHQDQZ256rmb:
26519 case VPUNPCKHQDQZ256rmbk:
26520 case VPUNPCKHQDQZ256rmbkz:
26521 case VPUNPCKHQDQZ256rmk:
26522 case VPUNPCKHQDQZ256rmkz:
26523 case VPUNPCKHQDQZ256rr:
26524 case VPUNPCKHQDQZ256rrk:
26525 case VPUNPCKHQDQZ256rrkz:
26526 case VPUNPCKHQDQZrm:
26527 case VPUNPCKHQDQZrmb:
26528 case VPUNPCKHQDQZrmbk:
26529 case VPUNPCKHQDQZrmbkz:
26530 case VPUNPCKHQDQZrmk:
26531 case VPUNPCKHQDQZrmkz:
26532 case VPUNPCKHQDQZrr:
26533 case VPUNPCKHQDQZrrk:
26534 case VPUNPCKHQDQZrrkz:
26535 case VPUNPCKHQDQrm:
26536 case VPUNPCKHQDQrr:
26537 return true;
26538 }
26539 return false;
26540}
26541
26542bool isMINPD(unsigned Opcode) {
26543 switch (Opcode) {
26544 case MINPDrm:
26545 case MINPDrr:
26546 return true;
26547 }
26548 return false;
26549}
26550
26551bool isVCVTTPD2QQ(unsigned Opcode) {
26552 switch (Opcode) {
26553 case VCVTTPD2QQZ128rm:
26554 case VCVTTPD2QQZ128rmb:
26555 case VCVTTPD2QQZ128rmbk:
26556 case VCVTTPD2QQZ128rmbkz:
26557 case VCVTTPD2QQZ128rmk:
26558 case VCVTTPD2QQZ128rmkz:
26559 case VCVTTPD2QQZ128rr:
26560 case VCVTTPD2QQZ128rrk:
26561 case VCVTTPD2QQZ128rrkz:
26562 case VCVTTPD2QQZ256rm:
26563 case VCVTTPD2QQZ256rmb:
26564 case VCVTTPD2QQZ256rmbk:
26565 case VCVTTPD2QQZ256rmbkz:
26566 case VCVTTPD2QQZ256rmk:
26567 case VCVTTPD2QQZ256rmkz:
26568 case VCVTTPD2QQZ256rr:
26569 case VCVTTPD2QQZ256rrk:
26570 case VCVTTPD2QQZ256rrkz:
26571 case VCVTTPD2QQZrm:
26572 case VCVTTPD2QQZrmb:
26573 case VCVTTPD2QQZrmbk:
26574 case VCVTTPD2QQZrmbkz:
26575 case VCVTTPD2QQZrmk:
26576 case VCVTTPD2QQZrmkz:
26577 case VCVTTPD2QQZrr:
26578 case VCVTTPD2QQZrrb:
26579 case VCVTTPD2QQZrrbk:
26580 case VCVTTPD2QQZrrbkz:
26581 case VCVTTPD2QQZrrk:
26582 case VCVTTPD2QQZrrkz:
26583 return true;
26584 }
26585 return false;
26586}
26587
26588bool isVFMSUBPD(unsigned Opcode) {
26589 switch (Opcode) {
26590 case VFMSUBPD4Ymr:
26591 case VFMSUBPD4Yrm:
26592 case VFMSUBPD4Yrr:
26593 case VFMSUBPD4Yrr_REV:
26594 case VFMSUBPD4mr:
26595 case VFMSUBPD4rm:
26596 case VFMSUBPD4rr:
26597 case VFMSUBPD4rr_REV:
26598 return true;
26599 }
26600 return false;
26601}
26602
26603bool isV4FMADDSS(unsigned Opcode) {
26604 switch (Opcode) {
26605 case V4FMADDSSrm:
26606 case V4FMADDSSrmk:
26607 case V4FMADDSSrmkz:
26608 return true;
26609 }
26610 return false;
26611}
26612
26613bool isCPUID(unsigned Opcode) {
26614 return Opcode == CPUID;
26615}
26616
26617bool isSETCC(unsigned Opcode) {
26618 switch (Opcode) {
26619 case SETCCm:
26620 case SETCCm_EVEX:
26621 case SETCCr:
26622 case SETCCr_EVEX:
26623 return true;
26624 }
26625 return false;
26626}
26627
26628bool isVPDPWUUD(unsigned Opcode) {
26629 switch (Opcode) {
26630 case VPDPWUUDYrm:
26631 case VPDPWUUDYrr:
26632 case VPDPWUUDZ128rm:
26633 case VPDPWUUDZ128rmb:
26634 case VPDPWUUDZ128rmbk:
26635 case VPDPWUUDZ128rmbkz:
26636 case VPDPWUUDZ128rmk:
26637 case VPDPWUUDZ128rmkz:
26638 case VPDPWUUDZ128rr:
26639 case VPDPWUUDZ128rrk:
26640 case VPDPWUUDZ128rrkz:
26641 case VPDPWUUDZ256rm:
26642 case VPDPWUUDZ256rmb:
26643 case VPDPWUUDZ256rmbk:
26644 case VPDPWUUDZ256rmbkz:
26645 case VPDPWUUDZ256rmk:
26646 case VPDPWUUDZ256rmkz:
26647 case VPDPWUUDZ256rr:
26648 case VPDPWUUDZ256rrk:
26649 case VPDPWUUDZ256rrkz:
26650 case VPDPWUUDZrm:
26651 case VPDPWUUDZrmb:
26652 case VPDPWUUDZrmbk:
26653 case VPDPWUUDZrmbkz:
26654 case VPDPWUUDZrmk:
26655 case VPDPWUUDZrmkz:
26656 case VPDPWUUDZrr:
26657 case VPDPWUUDZrrk:
26658 case VPDPWUUDZrrkz:
26659 case VPDPWUUDrm:
26660 case VPDPWUUDrr:
26661 return true;
26662 }
26663 return false;
26664}
26665
26666bool isVCVTTPS2IUBS(unsigned Opcode) {
26667 switch (Opcode) {
26668 case VCVTTPS2IUBSZ128rm:
26669 case VCVTTPS2IUBSZ128rmb:
26670 case VCVTTPS2IUBSZ128rmbk:
26671 case VCVTTPS2IUBSZ128rmbkz:
26672 case VCVTTPS2IUBSZ128rmk:
26673 case VCVTTPS2IUBSZ128rmkz:
26674 case VCVTTPS2IUBSZ128rr:
26675 case VCVTTPS2IUBSZ128rrk:
26676 case VCVTTPS2IUBSZ128rrkz:
26677 case VCVTTPS2IUBSZ256rm:
26678 case VCVTTPS2IUBSZ256rmb:
26679 case VCVTTPS2IUBSZ256rmbk:
26680 case VCVTTPS2IUBSZ256rmbkz:
26681 case VCVTTPS2IUBSZ256rmk:
26682 case VCVTTPS2IUBSZ256rmkz:
26683 case VCVTTPS2IUBSZ256rr:
26684 case VCVTTPS2IUBSZ256rrk:
26685 case VCVTTPS2IUBSZ256rrkz:
26686 case VCVTTPS2IUBSZrm:
26687 case VCVTTPS2IUBSZrmb:
26688 case VCVTTPS2IUBSZrmbk:
26689 case VCVTTPS2IUBSZrmbkz:
26690 case VCVTTPS2IUBSZrmk:
26691 case VCVTTPS2IUBSZrmkz:
26692 case VCVTTPS2IUBSZrr:
26693 case VCVTTPS2IUBSZrrb:
26694 case VCVTTPS2IUBSZrrbk:
26695 case VCVTTPS2IUBSZrrbkz:
26696 case VCVTTPS2IUBSZrrk:
26697 case VCVTTPS2IUBSZrrkz:
26698 return true;
26699 }
26700 return false;
26701}
26702
26703bool isPMOVSXDQ(unsigned Opcode) {
26704 switch (Opcode) {
26705 case PMOVSXDQrm:
26706 case PMOVSXDQrr:
26707 return true;
26708 }
26709 return false;
26710}
26711
26712bool isMWAIT(unsigned Opcode) {
26713 return Opcode == MWAITrr;
26714}
26715
26716bool isVPEXTRB(unsigned Opcode) {
26717 switch (Opcode) {
26718 case VPEXTRBZmri:
26719 case VPEXTRBZrri:
26720 case VPEXTRBmri:
26721 case VPEXTRBrri:
26722 return true;
26723 }
26724 return false;
26725}
26726
26727bool isINVVPID(unsigned Opcode) {
26728 switch (Opcode) {
26729 case INVVPID32:
26730 case INVVPID64:
26731 case INVVPID64_EVEX:
26732 return true;
26733 }
26734 return false;
26735}
26736
26737bool isVPSHUFD(unsigned Opcode) {
26738 switch (Opcode) {
26739 case VPSHUFDYmi:
26740 case VPSHUFDYri:
26741 case VPSHUFDZ128mbi:
26742 case VPSHUFDZ128mbik:
26743 case VPSHUFDZ128mbikz:
26744 case VPSHUFDZ128mi:
26745 case VPSHUFDZ128mik:
26746 case VPSHUFDZ128mikz:
26747 case VPSHUFDZ128ri:
26748 case VPSHUFDZ128rik:
26749 case VPSHUFDZ128rikz:
26750 case VPSHUFDZ256mbi:
26751 case VPSHUFDZ256mbik:
26752 case VPSHUFDZ256mbikz:
26753 case VPSHUFDZ256mi:
26754 case VPSHUFDZ256mik:
26755 case VPSHUFDZ256mikz:
26756 case VPSHUFDZ256ri:
26757 case VPSHUFDZ256rik:
26758 case VPSHUFDZ256rikz:
26759 case VPSHUFDZmbi:
26760 case VPSHUFDZmbik:
26761 case VPSHUFDZmbikz:
26762 case VPSHUFDZmi:
26763 case VPSHUFDZmik:
26764 case VPSHUFDZmikz:
26765 case VPSHUFDZri:
26766 case VPSHUFDZrik:
26767 case VPSHUFDZrikz:
26768 case VPSHUFDmi:
26769 case VPSHUFDri:
26770 return true;
26771 }
26772 return false;
26773}
26774
26775bool isVMINBF16(unsigned Opcode) {
26776 switch (Opcode) {
26777 case VMINBF16Z128rm:
26778 case VMINBF16Z128rmb:
26779 case VMINBF16Z128rmbk:
26780 case VMINBF16Z128rmbkz:
26781 case VMINBF16Z128rmk:
26782 case VMINBF16Z128rmkz:
26783 case VMINBF16Z128rr:
26784 case VMINBF16Z128rrk:
26785 case VMINBF16Z128rrkz:
26786 case VMINBF16Z256rm:
26787 case VMINBF16Z256rmb:
26788 case VMINBF16Z256rmbk:
26789 case VMINBF16Z256rmbkz:
26790 case VMINBF16Z256rmk:
26791 case VMINBF16Z256rmkz:
26792 case VMINBF16Z256rr:
26793 case VMINBF16Z256rrk:
26794 case VMINBF16Z256rrkz:
26795 case VMINBF16Zrm:
26796 case VMINBF16Zrmb:
26797 case VMINBF16Zrmbk:
26798 case VMINBF16Zrmbkz:
26799 case VMINBF16Zrmk:
26800 case VMINBF16Zrmkz:
26801 case VMINBF16Zrr:
26802 case VMINBF16Zrrk:
26803 case VMINBF16Zrrkz:
26804 return true;
26805 }
26806 return false;
26807}
26808
26809bool isMOVLPS(unsigned Opcode) {
26810 switch (Opcode) {
26811 case MOVLPSmr:
26812 case MOVLPSrm:
26813 return true;
26814 }
26815 return false;
26816}
26817
26818bool isVBLENDMPS(unsigned Opcode) {
26819 switch (Opcode) {
26820 case VBLENDMPSZ128rm:
26821 case VBLENDMPSZ128rmb:
26822 case VBLENDMPSZ128rmbk:
26823 case VBLENDMPSZ128rmbkz:
26824 case VBLENDMPSZ128rmk:
26825 case VBLENDMPSZ128rmkz:
26826 case VBLENDMPSZ128rr:
26827 case VBLENDMPSZ128rrk:
26828 case VBLENDMPSZ128rrkz:
26829 case VBLENDMPSZ256rm:
26830 case VBLENDMPSZ256rmb:
26831 case VBLENDMPSZ256rmbk:
26832 case VBLENDMPSZ256rmbkz:
26833 case VBLENDMPSZ256rmk:
26834 case VBLENDMPSZ256rmkz:
26835 case VBLENDMPSZ256rr:
26836 case VBLENDMPSZ256rrk:
26837 case VBLENDMPSZ256rrkz:
26838 case VBLENDMPSZrm:
26839 case VBLENDMPSZrmb:
26840 case VBLENDMPSZrmbk:
26841 case VBLENDMPSZrmbkz:
26842 case VBLENDMPSZrmk:
26843 case VBLENDMPSZrmkz:
26844 case VBLENDMPSZrr:
26845 case VBLENDMPSZrrk:
26846 case VBLENDMPSZrrkz:
26847 return true;
26848 }
26849 return false;
26850}
26851
26852bool isPMULLW(unsigned Opcode) {
26853 switch (Opcode) {
26854 case MMX_PMULLWrm:
26855 case MMX_PMULLWrr:
26856 case PMULLWrm:
26857 case PMULLWrr:
26858 return true;
26859 }
26860 return false;
26861}
26862
26863bool isVCVTSH2SI(unsigned Opcode) {
26864 switch (Opcode) {
26865 case VCVTSH2SI64Zrm_Int:
26866 case VCVTSH2SI64Zrr_Int:
26867 case VCVTSH2SI64Zrrb_Int:
26868 case VCVTSH2SIZrm_Int:
26869 case VCVTSH2SIZrr_Int:
26870 case VCVTSH2SIZrrb_Int:
26871 return true;
26872 }
26873 return false;
26874}
26875
26876bool isVPMOVSXWQ(unsigned Opcode) {
26877 switch (Opcode) {
26878 case VPMOVSXWQYrm:
26879 case VPMOVSXWQYrr:
26880 case VPMOVSXWQZ128rm:
26881 case VPMOVSXWQZ128rmk:
26882 case VPMOVSXWQZ128rmkz:
26883 case VPMOVSXWQZ128rr:
26884 case VPMOVSXWQZ128rrk:
26885 case VPMOVSXWQZ128rrkz:
26886 case VPMOVSXWQZ256rm:
26887 case VPMOVSXWQZ256rmk:
26888 case VPMOVSXWQZ256rmkz:
26889 case VPMOVSXWQZ256rr:
26890 case VPMOVSXWQZ256rrk:
26891 case VPMOVSXWQZ256rrkz:
26892 case VPMOVSXWQZrm:
26893 case VPMOVSXWQZrmk:
26894 case VPMOVSXWQZrmkz:
26895 case VPMOVSXWQZrr:
26896 case VPMOVSXWQZrrk:
26897 case VPMOVSXWQZrrkz:
26898 case VPMOVSXWQrm:
26899 case VPMOVSXWQrr:
26900 return true;
26901 }
26902 return false;
26903}
26904
26905bool isFNSTENV(unsigned Opcode) {
26906 return Opcode == FSTENVm;
26907}
26908
26909bool isVCVT2PH2BF8(unsigned Opcode) {
26910 switch (Opcode) {
26911 case VCVT2PH2BF8Z128rm:
26912 case VCVT2PH2BF8Z128rmb:
26913 case VCVT2PH2BF8Z128rmbk:
26914 case VCVT2PH2BF8Z128rmbkz:
26915 case VCVT2PH2BF8Z128rmk:
26916 case VCVT2PH2BF8Z128rmkz:
26917 case VCVT2PH2BF8Z128rr:
26918 case VCVT2PH2BF8Z128rrk:
26919 case VCVT2PH2BF8Z128rrkz:
26920 case VCVT2PH2BF8Z256rm:
26921 case VCVT2PH2BF8Z256rmb:
26922 case VCVT2PH2BF8Z256rmbk:
26923 case VCVT2PH2BF8Z256rmbkz:
26924 case VCVT2PH2BF8Z256rmk:
26925 case VCVT2PH2BF8Z256rmkz:
26926 case VCVT2PH2BF8Z256rr:
26927 case VCVT2PH2BF8Z256rrk:
26928 case VCVT2PH2BF8Z256rrkz:
26929 case VCVT2PH2BF8Zrm:
26930 case VCVT2PH2BF8Zrmb:
26931 case VCVT2PH2BF8Zrmbk:
26932 case VCVT2PH2BF8Zrmbkz:
26933 case VCVT2PH2BF8Zrmk:
26934 case VCVT2PH2BF8Zrmkz:
26935 case VCVT2PH2BF8Zrr:
26936 case VCVT2PH2BF8Zrrk:
26937 case VCVT2PH2BF8Zrrkz:
26938 return true;
26939 }
26940 return false;
26941}
26942
26943bool isVPERMI2PD(unsigned Opcode) {
26944 switch (Opcode) {
26945 case VPERMI2PDZ128rm:
26946 case VPERMI2PDZ128rmb:
26947 case VPERMI2PDZ128rmbk:
26948 case VPERMI2PDZ128rmbkz:
26949 case VPERMI2PDZ128rmk:
26950 case VPERMI2PDZ128rmkz:
26951 case VPERMI2PDZ128rr:
26952 case VPERMI2PDZ128rrk:
26953 case VPERMI2PDZ128rrkz:
26954 case VPERMI2PDZ256rm:
26955 case VPERMI2PDZ256rmb:
26956 case VPERMI2PDZ256rmbk:
26957 case VPERMI2PDZ256rmbkz:
26958 case VPERMI2PDZ256rmk:
26959 case VPERMI2PDZ256rmkz:
26960 case VPERMI2PDZ256rr:
26961 case VPERMI2PDZ256rrk:
26962 case VPERMI2PDZ256rrkz:
26963 case VPERMI2PDZrm:
26964 case VPERMI2PDZrmb:
26965 case VPERMI2PDZrmbk:
26966 case VPERMI2PDZrmbkz:
26967 case VPERMI2PDZrmk:
26968 case VPERMI2PDZrmkz:
26969 case VPERMI2PDZrr:
26970 case VPERMI2PDZrrk:
26971 case VPERMI2PDZrrkz:
26972 return true;
26973 }
26974 return false;
26975}
26976
26977bool isMAXSS(unsigned Opcode) {
26978 switch (Opcode) {
26979 case MAXSSrm_Int:
26980 case MAXSSrr_Int:
26981 return true;
26982 }
26983 return false;
26984}
26985
26986bool isCWDE(unsigned Opcode) {
26987 return Opcode == CWDE;
26988}
26989
26990bool isVBROADCASTI32X8(unsigned Opcode) {
26991 switch (Opcode) {
26992 case VBROADCASTI32X8Zrm:
26993 case VBROADCASTI32X8Zrmk:
26994 case VBROADCASTI32X8Zrmkz:
26995 return true;
26996 }
26997 return false;
26998}
26999
27000bool isINT(unsigned Opcode) {
27001 return Opcode == INT;
27002}
27003
27004bool isENCLS(unsigned Opcode) {
27005 return Opcode == ENCLS;
27006}
27007
27008bool isMOVNTQ(unsigned Opcode) {
27009 return Opcode == MMX_MOVNTQmr;
27010}
27011
27012bool isVDIVSH(unsigned Opcode) {
27013 switch (Opcode) {
27014 case VDIVSHZrm_Int:
27015 case VDIVSHZrmk_Int:
27016 case VDIVSHZrmkz_Int:
27017 case VDIVSHZrr_Int:
27018 case VDIVSHZrrb_Int:
27019 case VDIVSHZrrbk_Int:
27020 case VDIVSHZrrbkz_Int:
27021 case VDIVSHZrrk_Int:
27022 case VDIVSHZrrkz_Int:
27023 return true;
27024 }
27025 return false;
27026}
27027
27028bool isMOVHLPS(unsigned Opcode) {
27029 return Opcode == MOVHLPSrr;
27030}
27031
27032bool isVPMASKMOVD(unsigned Opcode) {
27033 switch (Opcode) {
27034 case VPMASKMOVDYmr:
27035 case VPMASKMOVDYrm:
27036 case VPMASKMOVDmr:
27037 case VPMASKMOVDrm:
27038 return true;
27039 }
27040 return false;
27041}
27042
27043bool isVMOVSD(unsigned Opcode) {
27044 switch (Opcode) {
27045 case VMOVSDZmr:
27046 case VMOVSDZmrk:
27047 case VMOVSDZrm:
27048 case VMOVSDZrmk:
27049 case VMOVSDZrmkz:
27050 case VMOVSDZrr:
27051 case VMOVSDZrr_REV:
27052 case VMOVSDZrrk:
27053 case VMOVSDZrrk_REV:
27054 case VMOVSDZrrkz:
27055 case VMOVSDZrrkz_REV:
27056 case VMOVSDmr:
27057 case VMOVSDrm:
27058 case VMOVSDrr:
27059 case VMOVSDrr_REV:
27060 return true;
27061 }
27062 return false;
27063}
27064
27065bool isVPMINUD(unsigned Opcode) {
27066 switch (Opcode) {
27067 case VPMINUDYrm:
27068 case VPMINUDYrr:
27069 case VPMINUDZ128rm:
27070 case VPMINUDZ128rmb:
27071 case VPMINUDZ128rmbk:
27072 case VPMINUDZ128rmbkz:
27073 case VPMINUDZ128rmk:
27074 case VPMINUDZ128rmkz:
27075 case VPMINUDZ128rr:
27076 case VPMINUDZ128rrk:
27077 case VPMINUDZ128rrkz:
27078 case VPMINUDZ256rm:
27079 case VPMINUDZ256rmb:
27080 case VPMINUDZ256rmbk:
27081 case VPMINUDZ256rmbkz:
27082 case VPMINUDZ256rmk:
27083 case VPMINUDZ256rmkz:
27084 case VPMINUDZ256rr:
27085 case VPMINUDZ256rrk:
27086 case VPMINUDZ256rrkz:
27087 case VPMINUDZrm:
27088 case VPMINUDZrmb:
27089 case VPMINUDZrmbk:
27090 case VPMINUDZrmbkz:
27091 case VPMINUDZrmk:
27092 case VPMINUDZrmkz:
27093 case VPMINUDZrr:
27094 case VPMINUDZrrk:
27095 case VPMINUDZrrkz:
27096 case VPMINUDrm:
27097 case VPMINUDrr:
27098 return true;
27099 }
27100 return false;
27101}
27102
27103bool isVPCMPISTRM(unsigned Opcode) {
27104 switch (Opcode) {
27105 case VPCMPISTRMrmi:
27106 case VPCMPISTRMrri:
27107 return true;
27108 }
27109 return false;
27110}
27111
27112bool isVGETMANTSD(unsigned Opcode) {
27113 switch (Opcode) {
27114 case VGETMANTSDZrmi:
27115 case VGETMANTSDZrmik:
27116 case VGETMANTSDZrmikz:
27117 case VGETMANTSDZrri:
27118 case VGETMANTSDZrrib:
27119 case VGETMANTSDZrribk:
27120 case VGETMANTSDZrribkz:
27121 case VGETMANTSDZrrik:
27122 case VGETMANTSDZrrikz:
27123 return true;
27124 }
27125 return false;
27126}
27127
27128bool isKSHIFTRW(unsigned Opcode) {
27129 return Opcode == KSHIFTRWki;
27130}
27131
27132bool isAESDECLAST(unsigned Opcode) {
27133 switch (Opcode) {
27134 case AESDECLASTrm:
27135 case AESDECLASTrr:
27136 return true;
27137 }
27138 return false;
27139}
27140
27141bool isVPTESTMB(unsigned Opcode) {
27142 switch (Opcode) {
27143 case VPTESTMBZ128rm:
27144 case VPTESTMBZ128rmk:
27145 case VPTESTMBZ128rr:
27146 case VPTESTMBZ128rrk:
27147 case VPTESTMBZ256rm:
27148 case VPTESTMBZ256rmk:
27149 case VPTESTMBZ256rr:
27150 case VPTESTMBZ256rrk:
27151 case VPTESTMBZrm:
27152 case VPTESTMBZrmk:
27153 case VPTESTMBZrr:
27154 case VPTESTMBZrrk:
27155 return true;
27156 }
27157 return false;
27158}
27159
27160bool isVFNMSUB231BF16(unsigned Opcode) {
27161 switch (Opcode) {
27162 case VFNMSUB231BF16Z128m:
27163 case VFNMSUB231BF16Z128mb:
27164 case VFNMSUB231BF16Z128mbk:
27165 case VFNMSUB231BF16Z128mbkz:
27166 case VFNMSUB231BF16Z128mk:
27167 case VFNMSUB231BF16Z128mkz:
27168 case VFNMSUB231BF16Z128r:
27169 case VFNMSUB231BF16Z128rk:
27170 case VFNMSUB231BF16Z128rkz:
27171 case VFNMSUB231BF16Z256m:
27172 case VFNMSUB231BF16Z256mb:
27173 case VFNMSUB231BF16Z256mbk:
27174 case VFNMSUB231BF16Z256mbkz:
27175 case VFNMSUB231BF16Z256mk:
27176 case VFNMSUB231BF16Z256mkz:
27177 case VFNMSUB231BF16Z256r:
27178 case VFNMSUB231BF16Z256rk:
27179 case VFNMSUB231BF16Z256rkz:
27180 case VFNMSUB231BF16Zm:
27181 case VFNMSUB231BF16Zmb:
27182 case VFNMSUB231BF16Zmbk:
27183 case VFNMSUB231BF16Zmbkz:
27184 case VFNMSUB231BF16Zmk:
27185 case VFNMSUB231BF16Zmkz:
27186 case VFNMSUB231BF16Zr:
27187 case VFNMSUB231BF16Zrk:
27188 case VFNMSUB231BF16Zrkz:
27189 return true;
27190 }
27191 return false;
27192}
27193
27194bool isVMPTRST(unsigned Opcode) {
27195 return Opcode == VMPTRSTm;
27196}
27197
27198bool isLLDT(unsigned Opcode) {
27199 switch (Opcode) {
27200 case LLDT16m:
27201 case LLDT16r:
27202 return true;
27203 }
27204 return false;
27205}
27206
27207bool isMOVSB(unsigned Opcode) {
27208 return Opcode == MOVSB;
27209}
27210
27211bool isTILELOADD(unsigned Opcode) {
27212 switch (Opcode) {
27213 case TILELOADD:
27214 case TILELOADD_EVEX:
27215 return true;
27216 }
27217 return false;
27218}
27219
27220bool isKTESTB(unsigned Opcode) {
27221 return Opcode == KTESTBkk;
27222}
27223
27224bool isMOVUPD(unsigned Opcode) {
27225 switch (Opcode) {
27226 case MOVUPDmr:
27227 case MOVUPDrm:
27228 case MOVUPDrr:
27229 case MOVUPDrr_REV:
27230 return true;
27231 }
27232 return false;
27233}
27234
27235bool isLKGS(unsigned Opcode) {
27236 switch (Opcode) {
27237 case LKGS16m:
27238 case LKGS16r:
27239 return true;
27240 }
27241 return false;
27242}
27243
27244bool isSGDTW(unsigned Opcode) {
27245 return Opcode == SGDT16m;
27246}
27247
27248bool isDIVSS(unsigned Opcode) {
27249 switch (Opcode) {
27250 case DIVSSrm_Int:
27251 case DIVSSrr_Int:
27252 return true;
27253 }
27254 return false;
27255}
27256
27257bool isPUNPCKHQDQ(unsigned Opcode) {
27258 switch (Opcode) {
27259 case PUNPCKHQDQrm:
27260 case PUNPCKHQDQrr:
27261 return true;
27262 }
27263 return false;
27264}
27265
27266bool isVFMADD213SD(unsigned Opcode) {
27267 switch (Opcode) {
27268 case VFMADD213SDZm_Int:
27269 case VFMADD213SDZmk_Int:
27270 case VFMADD213SDZmkz_Int:
27271 case VFMADD213SDZr_Int:
27272 case VFMADD213SDZrb_Int:
27273 case VFMADD213SDZrbk_Int:
27274 case VFMADD213SDZrbkz_Int:
27275 case VFMADD213SDZrk_Int:
27276 case VFMADD213SDZrkz_Int:
27277 case VFMADD213SDm_Int:
27278 case VFMADD213SDr_Int:
27279 return true;
27280 }
27281 return false;
27282}
27283
27284bool isKXORD(unsigned Opcode) {
27285 return Opcode == KXORDkk;
27286}
27287
27288bool isVPMOVB2M(unsigned Opcode) {
27289 switch (Opcode) {
27290 case VPMOVB2MZ128kr:
27291 case VPMOVB2MZ256kr:
27292 case VPMOVB2MZkr:
27293 return true;
27294 }
27295 return false;
27296}
27297
27298bool isVMREAD(unsigned Opcode) {
27299 switch (Opcode) {
27300 case VMREAD32mr:
27301 case VMREAD32rr:
27302 case VMREAD64mr:
27303 case VMREAD64rr:
27304 return true;
27305 }
27306 return false;
27307}
27308
27309bool isVPDPWSSDS(unsigned Opcode) {
27310 switch (Opcode) {
27311 case VPDPWSSDSYrm:
27312 case VPDPWSSDSYrr:
27313 case VPDPWSSDSZ128rm:
27314 case VPDPWSSDSZ128rmb:
27315 case VPDPWSSDSZ128rmbk:
27316 case VPDPWSSDSZ128rmbkz:
27317 case VPDPWSSDSZ128rmk:
27318 case VPDPWSSDSZ128rmkz:
27319 case VPDPWSSDSZ128rr:
27320 case VPDPWSSDSZ128rrk:
27321 case VPDPWSSDSZ128rrkz:
27322 case VPDPWSSDSZ256rm:
27323 case VPDPWSSDSZ256rmb:
27324 case VPDPWSSDSZ256rmbk:
27325 case VPDPWSSDSZ256rmbkz:
27326 case VPDPWSSDSZ256rmk:
27327 case VPDPWSSDSZ256rmkz:
27328 case VPDPWSSDSZ256rr:
27329 case VPDPWSSDSZ256rrk:
27330 case VPDPWSSDSZ256rrkz:
27331 case VPDPWSSDSZrm:
27332 case VPDPWSSDSZrmb:
27333 case VPDPWSSDSZrmbk:
27334 case VPDPWSSDSZrmbkz:
27335 case VPDPWSSDSZrmk:
27336 case VPDPWSSDSZrmkz:
27337 case VPDPWSSDSZrr:
27338 case VPDPWSSDSZrrk:
27339 case VPDPWSSDSZrrkz:
27340 case VPDPWSSDSrm:
27341 case VPDPWSSDSrr:
27342 return true;
27343 }
27344 return false;
27345}
27346
27347bool isTILERELEASE(unsigned Opcode) {
27348 return Opcode == TILERELEASE;
27349}
27350
27351bool isVUCOMXSH(unsigned Opcode) {
27352 switch (Opcode) {
27353 case VUCOMXSHZrm_Int:
27354 case VUCOMXSHZrr_Int:
27355 case VUCOMXSHZrrb_Int:
27356 return true;
27357 }
27358 return false;
27359}
27360
27361bool isCLFLUSHOPT(unsigned Opcode) {
27362 return Opcode == CLFLUSHOPT;
27363}
27364
27365bool isDAS(unsigned Opcode) {
27366 return Opcode == DAS;
27367}
27368
27369bool isVSCALEFPH(unsigned Opcode) {
27370 switch (Opcode) {
27371 case VSCALEFPHZ128rm:
27372 case VSCALEFPHZ128rmb:
27373 case VSCALEFPHZ128rmbk:
27374 case VSCALEFPHZ128rmbkz:
27375 case VSCALEFPHZ128rmk:
27376 case VSCALEFPHZ128rmkz:
27377 case VSCALEFPHZ128rr:
27378 case VSCALEFPHZ128rrk:
27379 case VSCALEFPHZ128rrkz:
27380 case VSCALEFPHZ256rm:
27381 case VSCALEFPHZ256rmb:
27382 case VSCALEFPHZ256rmbk:
27383 case VSCALEFPHZ256rmbkz:
27384 case VSCALEFPHZ256rmk:
27385 case VSCALEFPHZ256rmkz:
27386 case VSCALEFPHZ256rr:
27387 case VSCALEFPHZ256rrk:
27388 case VSCALEFPHZ256rrkz:
27389 case VSCALEFPHZrm:
27390 case VSCALEFPHZrmb:
27391 case VSCALEFPHZrmbk:
27392 case VSCALEFPHZrmbkz:
27393 case VSCALEFPHZrmk:
27394 case VSCALEFPHZrmkz:
27395 case VSCALEFPHZrr:
27396 case VSCALEFPHZrrb:
27397 case VSCALEFPHZrrbk:
27398 case VSCALEFPHZrrbkz:
27399 case VSCALEFPHZrrk:
27400 case VSCALEFPHZrrkz:
27401 return true;
27402 }
27403 return false;
27404}
27405
27406bool isVSUBSD(unsigned Opcode) {
27407 switch (Opcode) {
27408 case VSUBSDZrm_Int:
27409 case VSUBSDZrmk_Int:
27410 case VSUBSDZrmkz_Int:
27411 case VSUBSDZrr_Int:
27412 case VSUBSDZrrb_Int:
27413 case VSUBSDZrrbk_Int:
27414 case VSUBSDZrrbkz_Int:
27415 case VSUBSDZrrk_Int:
27416 case VSUBSDZrrkz_Int:
27417 case VSUBSDrm_Int:
27418 case VSUBSDrr_Int:
27419 return true;
27420 }
27421 return false;
27422}
27423
27424bool isVCOMISS(unsigned Opcode) {
27425 switch (Opcode) {
27426 case VCOMISSZrm:
27427 case VCOMISSZrr:
27428 case VCOMISSZrrb:
27429 case VCOMISSrm:
27430 case VCOMISSrr:
27431 return true;
27432 }
27433 return false;
27434}
27435
27436bool isVMULBF16(unsigned Opcode) {
27437 switch (Opcode) {
27438 case VMULBF16Z128rm:
27439 case VMULBF16Z128rmb:
27440 case VMULBF16Z128rmbk:
27441 case VMULBF16Z128rmbkz:
27442 case VMULBF16Z128rmk:
27443 case VMULBF16Z128rmkz:
27444 case VMULBF16Z128rr:
27445 case VMULBF16Z128rrk:
27446 case VMULBF16Z128rrkz:
27447 case VMULBF16Z256rm:
27448 case VMULBF16Z256rmb:
27449 case VMULBF16Z256rmbk:
27450 case VMULBF16Z256rmbkz:
27451 case VMULBF16Z256rmk:
27452 case VMULBF16Z256rmkz:
27453 case VMULBF16Z256rr:
27454 case VMULBF16Z256rrk:
27455 case VMULBF16Z256rrkz:
27456 case VMULBF16Zrm:
27457 case VMULBF16Zrmb:
27458 case VMULBF16Zrmbk:
27459 case VMULBF16Zrmbkz:
27460 case VMULBF16Zrmk:
27461 case VMULBF16Zrmkz:
27462 case VMULBF16Zrr:
27463 case VMULBF16Zrrk:
27464 case VMULBF16Zrrkz:
27465 return true;
27466 }
27467 return false;
27468}
27469
27470bool isORPS(unsigned Opcode) {
27471 switch (Opcode) {
27472 case ORPSrm:
27473 case ORPSrr:
27474 return true;
27475 }
27476 return false;
27477}
27478
27479bool isTDPFP16PS(unsigned Opcode) {
27480 return Opcode == TDPFP16PS;
27481}
27482
27483bool isVMAXPD(unsigned Opcode) {
27484 switch (Opcode) {
27485 case VMAXPDYrm:
27486 case VMAXPDYrr:
27487 case VMAXPDZ128rm:
27488 case VMAXPDZ128rmb:
27489 case VMAXPDZ128rmbk:
27490 case VMAXPDZ128rmbkz:
27491 case VMAXPDZ128rmk:
27492 case VMAXPDZ128rmkz:
27493 case VMAXPDZ128rr:
27494 case VMAXPDZ128rrk:
27495 case VMAXPDZ128rrkz:
27496 case VMAXPDZ256rm:
27497 case VMAXPDZ256rmb:
27498 case VMAXPDZ256rmbk:
27499 case VMAXPDZ256rmbkz:
27500 case VMAXPDZ256rmk:
27501 case VMAXPDZ256rmkz:
27502 case VMAXPDZ256rr:
27503 case VMAXPDZ256rrk:
27504 case VMAXPDZ256rrkz:
27505 case VMAXPDZrm:
27506 case VMAXPDZrmb:
27507 case VMAXPDZrmbk:
27508 case VMAXPDZrmbkz:
27509 case VMAXPDZrmk:
27510 case VMAXPDZrmkz:
27511 case VMAXPDZrr:
27512 case VMAXPDZrrb:
27513 case VMAXPDZrrbk:
27514 case VMAXPDZrrbkz:
27515 case VMAXPDZrrk:
27516 case VMAXPDZrrkz:
27517 case VMAXPDrm:
27518 case VMAXPDrr:
27519 return true;
27520 }
27521 return false;
27522}
27523
27524bool isVPMOVWB(unsigned Opcode) {
27525 switch (Opcode) {
27526 case VPMOVWBZ128mr:
27527 case VPMOVWBZ128mrk:
27528 case VPMOVWBZ128rr:
27529 case VPMOVWBZ128rrk:
27530 case VPMOVWBZ128rrkz:
27531 case VPMOVWBZ256mr:
27532 case VPMOVWBZ256mrk:
27533 case VPMOVWBZ256rr:
27534 case VPMOVWBZ256rrk:
27535 case VPMOVWBZ256rrkz:
27536 case VPMOVWBZmr:
27537 case VPMOVWBZmrk:
27538 case VPMOVWBZrr:
27539 case VPMOVWBZrrk:
27540 case VPMOVWBZrrkz:
27541 return true;
27542 }
27543 return false;
27544}
27545
27546bool isVEXP2PS(unsigned Opcode) {
27547 switch (Opcode) {
27548 case VEXP2PSZm:
27549 case VEXP2PSZmb:
27550 case VEXP2PSZmbk:
27551 case VEXP2PSZmbkz:
27552 case VEXP2PSZmk:
27553 case VEXP2PSZmkz:
27554 case VEXP2PSZr:
27555 case VEXP2PSZrb:
27556 case VEXP2PSZrbk:
27557 case VEXP2PSZrbkz:
27558 case VEXP2PSZrk:
27559 case VEXP2PSZrkz:
27560 return true;
27561 }
27562 return false;
27563}
27564
27565bool isVPGATHERDQ(unsigned Opcode) {
27566 switch (Opcode) {
27567 case VPGATHERDQYrm:
27568 case VPGATHERDQZ128rm:
27569 case VPGATHERDQZ256rm:
27570 case VPGATHERDQZrm:
27571 case VPGATHERDQrm:
27572 return true;
27573 }
27574 return false;
27575}
27576
27577bool isVPSRAVQ(unsigned Opcode) {
27578 switch (Opcode) {
27579 case VPSRAVQZ128rm:
27580 case VPSRAVQZ128rmb:
27581 case VPSRAVQZ128rmbk:
27582 case VPSRAVQZ128rmbkz:
27583 case VPSRAVQZ128rmk:
27584 case VPSRAVQZ128rmkz:
27585 case VPSRAVQZ128rr:
27586 case VPSRAVQZ128rrk:
27587 case VPSRAVQZ128rrkz:
27588 case VPSRAVQZ256rm:
27589 case VPSRAVQZ256rmb:
27590 case VPSRAVQZ256rmbk:
27591 case VPSRAVQZ256rmbkz:
27592 case VPSRAVQZ256rmk:
27593 case VPSRAVQZ256rmkz:
27594 case VPSRAVQZ256rr:
27595 case VPSRAVQZ256rrk:
27596 case VPSRAVQZ256rrkz:
27597 case VPSRAVQZrm:
27598 case VPSRAVQZrmb:
27599 case VPSRAVQZrmbk:
27600 case VPSRAVQZrmbkz:
27601 case VPSRAVQZrmk:
27602 case VPSRAVQZrmkz:
27603 case VPSRAVQZrr:
27604 case VPSRAVQZrrk:
27605 case VPSRAVQZrrkz:
27606 return true;
27607 }
27608 return false;
27609}
27610
27611bool isPCMPISTRI(unsigned Opcode) {
27612 switch (Opcode) {
27613 case PCMPISTRIrmi:
27614 case PCMPISTRIrri:
27615 return true;
27616 }
27617 return false;
27618}
27619
27620bool isVFMSUB231PD(unsigned Opcode) {
27621 switch (Opcode) {
27622 case VFMSUB231PDYm:
27623 case VFMSUB231PDYr:
27624 case VFMSUB231PDZ128m:
27625 case VFMSUB231PDZ128mb:
27626 case VFMSUB231PDZ128mbk:
27627 case VFMSUB231PDZ128mbkz:
27628 case VFMSUB231PDZ128mk:
27629 case VFMSUB231PDZ128mkz:
27630 case VFMSUB231PDZ128r:
27631 case VFMSUB231PDZ128rk:
27632 case VFMSUB231PDZ128rkz:
27633 case VFMSUB231PDZ256m:
27634 case VFMSUB231PDZ256mb:
27635 case VFMSUB231PDZ256mbk:
27636 case VFMSUB231PDZ256mbkz:
27637 case VFMSUB231PDZ256mk:
27638 case VFMSUB231PDZ256mkz:
27639 case VFMSUB231PDZ256r:
27640 case VFMSUB231PDZ256rk:
27641 case VFMSUB231PDZ256rkz:
27642 case VFMSUB231PDZm:
27643 case VFMSUB231PDZmb:
27644 case VFMSUB231PDZmbk:
27645 case VFMSUB231PDZmbkz:
27646 case VFMSUB231PDZmk:
27647 case VFMSUB231PDZmkz:
27648 case VFMSUB231PDZr:
27649 case VFMSUB231PDZrb:
27650 case VFMSUB231PDZrbk:
27651 case VFMSUB231PDZrbkz:
27652 case VFMSUB231PDZrk:
27653 case VFMSUB231PDZrkz:
27654 case VFMSUB231PDm:
27655 case VFMSUB231PDr:
27656 return true;
27657 }
27658 return false;
27659}
27660
27661bool isRDMSR(unsigned Opcode) {
27662 switch (Opcode) {
27663 case RDMSR:
27664 case RDMSRri:
27665 case RDMSRri_EVEX:
27666 return true;
27667 }
27668 return false;
27669}
27670
27671bool isKORTESTD(unsigned Opcode) {
27672 return Opcode == KORTESTDkk;
27673}
27674
27675bool isVPBLENDMW(unsigned Opcode) {
27676 switch (Opcode) {
27677 case VPBLENDMWZ128rm:
27678 case VPBLENDMWZ128rmk:
27679 case VPBLENDMWZ128rmkz:
27680 case VPBLENDMWZ128rr:
27681 case VPBLENDMWZ128rrk:
27682 case VPBLENDMWZ128rrkz:
27683 case VPBLENDMWZ256rm:
27684 case VPBLENDMWZ256rmk:
27685 case VPBLENDMWZ256rmkz:
27686 case VPBLENDMWZ256rr:
27687 case VPBLENDMWZ256rrk:
27688 case VPBLENDMWZ256rrkz:
27689 case VPBLENDMWZrm:
27690 case VPBLENDMWZrmk:
27691 case VPBLENDMWZrmkz:
27692 case VPBLENDMWZrr:
27693 case VPBLENDMWZrrk:
27694 case VPBLENDMWZrrkz:
27695 return true;
27696 }
27697 return false;
27698}
27699
27700bool isPSHUFB(unsigned Opcode) {
27701 switch (Opcode) {
27702 case MMX_PSHUFBrm:
27703 case MMX_PSHUFBrr:
27704 case PSHUFBrm:
27705 case PSHUFBrr:
27706 return true;
27707 }
27708 return false;
27709}
27710
27711bool isVDPBF16PS(unsigned Opcode) {
27712 switch (Opcode) {
27713 case VDPBF16PSZ128m:
27714 case VDPBF16PSZ128mb:
27715 case VDPBF16PSZ128mbk:
27716 case VDPBF16PSZ128mbkz:
27717 case VDPBF16PSZ128mk:
27718 case VDPBF16PSZ128mkz:
27719 case VDPBF16PSZ128r:
27720 case VDPBF16PSZ128rk:
27721 case VDPBF16PSZ128rkz:
27722 case VDPBF16PSZ256m:
27723 case VDPBF16PSZ256mb:
27724 case VDPBF16PSZ256mbk:
27725 case VDPBF16PSZ256mbkz:
27726 case VDPBF16PSZ256mk:
27727 case VDPBF16PSZ256mkz:
27728 case VDPBF16PSZ256r:
27729 case VDPBF16PSZ256rk:
27730 case VDPBF16PSZ256rkz:
27731 case VDPBF16PSZm:
27732 case VDPBF16PSZmb:
27733 case VDPBF16PSZmbk:
27734 case VDPBF16PSZmbkz:
27735 case VDPBF16PSZmk:
27736 case VDPBF16PSZmkz:
27737 case VDPBF16PSZr:
27738 case VDPBF16PSZrk:
27739 case VDPBF16PSZrkz:
27740 return true;
27741 }
27742 return false;
27743}
27744
27745bool isTDPBF16PS(unsigned Opcode) {
27746 return Opcode == TDPBF16PS;
27747}
27748
27749bool isFCMOVE(unsigned Opcode) {
27750 return Opcode == CMOVE_F;
27751}
27752
27753bool isVFMADD231BF16(unsigned Opcode) {
27754 switch (Opcode) {
27755 case VFMADD231BF16Z128m:
27756 case VFMADD231BF16Z128mb:
27757 case VFMADD231BF16Z128mbk:
27758 case VFMADD231BF16Z128mbkz:
27759 case VFMADD231BF16Z128mk:
27760 case VFMADD231BF16Z128mkz:
27761 case VFMADD231BF16Z128r:
27762 case VFMADD231BF16Z128rk:
27763 case VFMADD231BF16Z128rkz:
27764 case VFMADD231BF16Z256m:
27765 case VFMADD231BF16Z256mb:
27766 case VFMADD231BF16Z256mbk:
27767 case VFMADD231BF16Z256mbkz:
27768 case VFMADD231BF16Z256mk:
27769 case VFMADD231BF16Z256mkz:
27770 case VFMADD231BF16Z256r:
27771 case VFMADD231BF16Z256rk:
27772 case VFMADD231BF16Z256rkz:
27773 case VFMADD231BF16Zm:
27774 case VFMADD231BF16Zmb:
27775 case VFMADD231BF16Zmbk:
27776 case VFMADD231BF16Zmbkz:
27777 case VFMADD231BF16Zmk:
27778 case VFMADD231BF16Zmkz:
27779 case VFMADD231BF16Zr:
27780 case VFMADD231BF16Zrk:
27781 case VFMADD231BF16Zrkz:
27782 return true;
27783 }
27784 return false;
27785}
27786
27787bool isCMPSS(unsigned Opcode) {
27788 switch (Opcode) {
27789 case CMPSSrmi_Int:
27790 case CMPSSrri_Int:
27791 return true;
27792 }
27793 return false;
27794}
27795
27796bool isMASKMOVDQU(unsigned Opcode) {
27797 switch (Opcode) {
27798 case MASKMOVDQU:
27799 case MASKMOVDQU64:
27800 return true;
27801 }
27802 return false;
27803}
27804
27805bool isSARX(unsigned Opcode) {
27806 switch (Opcode) {
27807 case SARX32rm:
27808 case SARX32rm_EVEX:
27809 case SARX32rr:
27810 case SARX32rr_EVEX:
27811 case SARX64rm:
27812 case SARX64rm_EVEX:
27813 case SARX64rr:
27814 case SARX64rr_EVEX:
27815 return true;
27816 }
27817 return false;
27818}
27819
27820bool isVPDPWUSDS(unsigned Opcode) {
27821 switch (Opcode) {
27822 case VPDPWUSDSYrm:
27823 case VPDPWUSDSYrr:
27824 case VPDPWUSDSZ128rm:
27825 case VPDPWUSDSZ128rmb:
27826 case VPDPWUSDSZ128rmbk:
27827 case VPDPWUSDSZ128rmbkz:
27828 case VPDPWUSDSZ128rmk:
27829 case VPDPWUSDSZ128rmkz:
27830 case VPDPWUSDSZ128rr:
27831 case VPDPWUSDSZ128rrk:
27832 case VPDPWUSDSZ128rrkz:
27833 case VPDPWUSDSZ256rm:
27834 case VPDPWUSDSZ256rmb:
27835 case VPDPWUSDSZ256rmbk:
27836 case VPDPWUSDSZ256rmbkz:
27837 case VPDPWUSDSZ256rmk:
27838 case VPDPWUSDSZ256rmkz:
27839 case VPDPWUSDSZ256rr:
27840 case VPDPWUSDSZ256rrk:
27841 case VPDPWUSDSZ256rrkz:
27842 case VPDPWUSDSZrm:
27843 case VPDPWUSDSZrmb:
27844 case VPDPWUSDSZrmbk:
27845 case VPDPWUSDSZrmbkz:
27846 case VPDPWUSDSZrmk:
27847 case VPDPWUSDSZrmkz:
27848 case VPDPWUSDSZrr:
27849 case VPDPWUSDSZrrk:
27850 case VPDPWUSDSZrrkz:
27851 case VPDPWUSDSrm:
27852 case VPDPWUSDSrr:
27853 return true;
27854 }
27855 return false;
27856}
27857
27858bool isSGDT(unsigned Opcode) {
27859 return Opcode == SGDT64m;
27860}
27861
27862bool isVFMULCPH(unsigned Opcode) {
27863 switch (Opcode) {
27864 case VFMULCPHZ128rm:
27865 case VFMULCPHZ128rmb:
27866 case VFMULCPHZ128rmbk:
27867 case VFMULCPHZ128rmbkz:
27868 case VFMULCPHZ128rmk:
27869 case VFMULCPHZ128rmkz:
27870 case VFMULCPHZ128rr:
27871 case VFMULCPHZ128rrk:
27872 case VFMULCPHZ128rrkz:
27873 case VFMULCPHZ256rm:
27874 case VFMULCPHZ256rmb:
27875 case VFMULCPHZ256rmbk:
27876 case VFMULCPHZ256rmbkz:
27877 case VFMULCPHZ256rmk:
27878 case VFMULCPHZ256rmkz:
27879 case VFMULCPHZ256rr:
27880 case VFMULCPHZ256rrk:
27881 case VFMULCPHZ256rrkz:
27882 case VFMULCPHZrm:
27883 case VFMULCPHZrmb:
27884 case VFMULCPHZrmbk:
27885 case VFMULCPHZrmbkz:
27886 case VFMULCPHZrmk:
27887 case VFMULCPHZrmkz:
27888 case VFMULCPHZrr:
27889 case VFMULCPHZrrb:
27890 case VFMULCPHZrrbk:
27891 case VFMULCPHZrrbkz:
27892 case VFMULCPHZrrk:
27893 case VFMULCPHZrrkz:
27894 return true;
27895 }
27896 return false;
27897}
27898
27899bool isURDMSR(unsigned Opcode) {
27900 switch (Opcode) {
27901 case URDMSRri:
27902 case URDMSRri_EVEX:
27903 case URDMSRrr:
27904 case URDMSRrr_EVEX:
27905 return true;
27906 }
27907 return false;
27908}
27909
27910bool isKUNPCKWD(unsigned Opcode) {
27911 return Opcode == KUNPCKWDkk;
27912}
27913
27914bool isVSCALEFBF16(unsigned Opcode) {
27915 switch (Opcode) {
27916 case VSCALEFBF16Z128rm:
27917 case VSCALEFBF16Z128rmb:
27918 case VSCALEFBF16Z128rmbk:
27919 case VSCALEFBF16Z128rmbkz:
27920 case VSCALEFBF16Z128rmk:
27921 case VSCALEFBF16Z128rmkz:
27922 case VSCALEFBF16Z128rr:
27923 case VSCALEFBF16Z128rrk:
27924 case VSCALEFBF16Z128rrkz:
27925 case VSCALEFBF16Z256rm:
27926 case VSCALEFBF16Z256rmb:
27927 case VSCALEFBF16Z256rmbk:
27928 case VSCALEFBF16Z256rmbkz:
27929 case VSCALEFBF16Z256rmk:
27930 case VSCALEFBF16Z256rmkz:
27931 case VSCALEFBF16Z256rr:
27932 case VSCALEFBF16Z256rrk:
27933 case VSCALEFBF16Z256rrkz:
27934 case VSCALEFBF16Zrm:
27935 case VSCALEFBF16Zrmb:
27936 case VSCALEFBF16Zrmbk:
27937 case VSCALEFBF16Zrmbkz:
27938 case VSCALEFBF16Zrmk:
27939 case VSCALEFBF16Zrmkz:
27940 case VSCALEFBF16Zrr:
27941 case VSCALEFBF16Zrrk:
27942 case VSCALEFBF16Zrrkz:
27943 return true;
27944 }
27945 return false;
27946}
27947
27948bool isCVTPS2PD(unsigned Opcode) {
27949 switch (Opcode) {
27950 case CVTPS2PDrm:
27951 case CVTPS2PDrr:
27952 return true;
27953 }
27954 return false;
27955}
27956
27957bool isFBSTP(unsigned Opcode) {
27958 return Opcode == FBSTPm;
27959}
27960
27961bool isPSUBQ(unsigned Opcode) {
27962 switch (Opcode) {
27963 case MMX_PSUBQrm:
27964 case MMX_PSUBQrr:
27965 case PSUBQrm:
27966 case PSUBQrr:
27967 return true;
27968 }
27969 return false;
27970}
27971
27972bool isFXSAVE64(unsigned Opcode) {
27973 return Opcode == FXSAVE64;
27974}
27975
27976bool isKMOVW(unsigned Opcode) {
27977 switch (Opcode) {
27978 case KMOVWkk:
27979 case KMOVWkk_EVEX:
27980 case KMOVWkm:
27981 case KMOVWkm_EVEX:
27982 case KMOVWkr:
27983 case KMOVWkr_EVEX:
27984 case KMOVWmk:
27985 case KMOVWmk_EVEX:
27986 case KMOVWrk:
27987 case KMOVWrk_EVEX:
27988 return true;
27989 }
27990 return false;
27991}
27992
27993bool isBTS(unsigned Opcode) {
27994 switch (Opcode) {
27995 case BTS16mi8:
27996 case BTS16mr:
27997 case BTS16ri8:
27998 case BTS16rr:
27999 case BTS32mi8:
28000 case BTS32mr:
28001 case BTS32ri8:
28002 case BTS32rr:
28003 case BTS64mi8:
28004 case BTS64mr:
28005 case BTS64ri8:
28006 case BTS64rr:
28007 return true;
28008 }
28009 return false;
28010}
28011
28012bool isVPHADDBQ(unsigned Opcode) {
28013 switch (Opcode) {
28014 case VPHADDBQrm:
28015 case VPHADDBQrr:
28016 return true;
28017 }
28018 return false;
28019}
28020
28021bool isFRSTOR(unsigned Opcode) {
28022 return Opcode == FRSTORm;
28023}
28024
28025bool isVFMSUB132PD(unsigned Opcode) {
28026 switch (Opcode) {
28027 case VFMSUB132PDYm:
28028 case VFMSUB132PDYr:
28029 case VFMSUB132PDZ128m:
28030 case VFMSUB132PDZ128mb:
28031 case VFMSUB132PDZ128mbk:
28032 case VFMSUB132PDZ128mbkz:
28033 case VFMSUB132PDZ128mk:
28034 case VFMSUB132PDZ128mkz:
28035 case VFMSUB132PDZ128r:
28036 case VFMSUB132PDZ128rk:
28037 case VFMSUB132PDZ128rkz:
28038 case VFMSUB132PDZ256m:
28039 case VFMSUB132PDZ256mb:
28040 case VFMSUB132PDZ256mbk:
28041 case VFMSUB132PDZ256mbkz:
28042 case VFMSUB132PDZ256mk:
28043 case VFMSUB132PDZ256mkz:
28044 case VFMSUB132PDZ256r:
28045 case VFMSUB132PDZ256rk:
28046 case VFMSUB132PDZ256rkz:
28047 case VFMSUB132PDZm:
28048 case VFMSUB132PDZmb:
28049 case VFMSUB132PDZmbk:
28050 case VFMSUB132PDZmbkz:
28051 case VFMSUB132PDZmk:
28052 case VFMSUB132PDZmkz:
28053 case VFMSUB132PDZr:
28054 case VFMSUB132PDZrb:
28055 case VFMSUB132PDZrbk:
28056 case VFMSUB132PDZrbkz:
28057 case VFMSUB132PDZrk:
28058 case VFMSUB132PDZrkz:
28059 case VFMSUB132PDm:
28060 case VFMSUB132PDr:
28061 return true;
28062 }
28063 return false;
28064}
28065
28066bool isPMULLD(unsigned Opcode) {
28067 switch (Opcode) {
28068 case PMULLDrm:
28069 case PMULLDrr:
28070 return true;
28071 }
28072 return false;
28073}
28074
28075bool isSHA1MSG2(unsigned Opcode) {
28076 switch (Opcode) {
28077 case SHA1MSG2rm:
28078 case SHA1MSG2rr:
28079 return true;
28080 }
28081 return false;
28082}
28083
28084bool isJECXZ(unsigned Opcode) {
28085 return Opcode == JECXZ;
28086}
28087
28088bool isVCVTUDQ2PS(unsigned Opcode) {
28089 switch (Opcode) {
28090 case VCVTUDQ2PSZ128rm:
28091 case VCVTUDQ2PSZ128rmb:
28092 case VCVTUDQ2PSZ128rmbk:
28093 case VCVTUDQ2PSZ128rmbkz:
28094 case VCVTUDQ2PSZ128rmk:
28095 case VCVTUDQ2PSZ128rmkz:
28096 case VCVTUDQ2PSZ128rr:
28097 case VCVTUDQ2PSZ128rrk:
28098 case VCVTUDQ2PSZ128rrkz:
28099 case VCVTUDQ2PSZ256rm:
28100 case VCVTUDQ2PSZ256rmb:
28101 case VCVTUDQ2PSZ256rmbk:
28102 case VCVTUDQ2PSZ256rmbkz:
28103 case VCVTUDQ2PSZ256rmk:
28104 case VCVTUDQ2PSZ256rmkz:
28105 case VCVTUDQ2PSZ256rr:
28106 case VCVTUDQ2PSZ256rrk:
28107 case VCVTUDQ2PSZ256rrkz:
28108 case VCVTUDQ2PSZrm:
28109 case VCVTUDQ2PSZrmb:
28110 case VCVTUDQ2PSZrmbk:
28111 case VCVTUDQ2PSZrmbkz:
28112 case VCVTUDQ2PSZrmk:
28113 case VCVTUDQ2PSZrmkz:
28114 case VCVTUDQ2PSZrr:
28115 case VCVTUDQ2PSZrrb:
28116 case VCVTUDQ2PSZrrbk:
28117 case VCVTUDQ2PSZrrbkz:
28118 case VCVTUDQ2PSZrrk:
28119 case VCVTUDQ2PSZrrkz:
28120 return true;
28121 }
28122 return false;
28123}
28124
28125bool isAESENC(unsigned Opcode) {
28126 switch (Opcode) {
28127 case AESENCrm:
28128 case AESENCrr:
28129 return true;
28130 }
28131 return false;
28132}
28133
28134bool isVMINMAXPS(unsigned Opcode) {
28135 switch (Opcode) {
28136 case VMINMAXPSZ128rmbi:
28137 case VMINMAXPSZ128rmbik:
28138 case VMINMAXPSZ128rmbikz:
28139 case VMINMAXPSZ128rmi:
28140 case VMINMAXPSZ128rmik:
28141 case VMINMAXPSZ128rmikz:
28142 case VMINMAXPSZ128rri:
28143 case VMINMAXPSZ128rrik:
28144 case VMINMAXPSZ128rrikz:
28145 case VMINMAXPSZ256rmbi:
28146 case VMINMAXPSZ256rmbik:
28147 case VMINMAXPSZ256rmbikz:
28148 case VMINMAXPSZ256rmi:
28149 case VMINMAXPSZ256rmik:
28150 case VMINMAXPSZ256rmikz:
28151 case VMINMAXPSZ256rri:
28152 case VMINMAXPSZ256rrik:
28153 case VMINMAXPSZ256rrikz:
28154 case VMINMAXPSZrmbi:
28155 case VMINMAXPSZrmbik:
28156 case VMINMAXPSZrmbikz:
28157 case VMINMAXPSZrmi:
28158 case VMINMAXPSZrmik:
28159 case VMINMAXPSZrmikz:
28160 case VMINMAXPSZrri:
28161 case VMINMAXPSZrrib:
28162 case VMINMAXPSZrribk:
28163 case VMINMAXPSZrribkz:
28164 case VMINMAXPSZrrik:
28165 case VMINMAXPSZrrikz:
28166 return true;
28167 }
28168 return false;
28169}
28170
28171bool isPSIGNW(unsigned Opcode) {
28172 switch (Opcode) {
28173 case MMX_PSIGNWrm:
28174 case MMX_PSIGNWrr:
28175 case PSIGNWrm:
28176 case PSIGNWrr:
28177 return true;
28178 }
28179 return false;
28180}
28181
28182bool isUNPCKLPD(unsigned Opcode) {
28183 switch (Opcode) {
28184 case UNPCKLPDrm:
28185 case UNPCKLPDrr:
28186 return true;
28187 }
28188 return false;
28189}
28190
28191bool isPUSHP(unsigned Opcode) {
28192 return Opcode == PUSHP64r;
28193}
28194
28195bool isBLSI(unsigned Opcode) {
28196 switch (Opcode) {
28197 case BLSI32rm:
28198 case BLSI32rm_EVEX:
28199 case BLSI32rm_NF:
28200 case BLSI32rr:
28201 case BLSI32rr_EVEX:
28202 case BLSI32rr_NF:
28203 case BLSI64rm:
28204 case BLSI64rm_EVEX:
28205 case BLSI64rm_NF:
28206 case BLSI64rr:
28207 case BLSI64rr_EVEX:
28208 case BLSI64rr_NF:
28209 return true;
28210 }
28211 return false;
28212}
28213
28214bool isVPTESTNMB(unsigned Opcode) {
28215 switch (Opcode) {
28216 case VPTESTNMBZ128rm:
28217 case VPTESTNMBZ128rmk:
28218 case VPTESTNMBZ128rr:
28219 case VPTESTNMBZ128rrk:
28220 case VPTESTNMBZ256rm:
28221 case VPTESTNMBZ256rmk:
28222 case VPTESTNMBZ256rr:
28223 case VPTESTNMBZ256rrk:
28224 case VPTESTNMBZrm:
28225 case VPTESTNMBZrmk:
28226 case VPTESTNMBZrr:
28227 case VPTESTNMBZrrk:
28228 return true;
28229 }
28230 return false;
28231}
28232
28233bool isWRUSSQ(unsigned Opcode) {
28234 switch (Opcode) {
28235 case WRUSSQ:
28236 case WRUSSQ_EVEX:
28237 return true;
28238 }
28239 return false;
28240}
28241
28242bool isVGF2P8MULB(unsigned Opcode) {
28243 switch (Opcode) {
28244 case VGF2P8MULBYrm:
28245 case VGF2P8MULBYrr:
28246 case VGF2P8MULBZ128rm:
28247 case VGF2P8MULBZ128rmk:
28248 case VGF2P8MULBZ128rmkz:
28249 case VGF2P8MULBZ128rr:
28250 case VGF2P8MULBZ128rrk:
28251 case VGF2P8MULBZ128rrkz:
28252 case VGF2P8MULBZ256rm:
28253 case VGF2P8MULBZ256rmk:
28254 case VGF2P8MULBZ256rmkz:
28255 case VGF2P8MULBZ256rr:
28256 case VGF2P8MULBZ256rrk:
28257 case VGF2P8MULBZ256rrkz:
28258 case VGF2P8MULBZrm:
28259 case VGF2P8MULBZrmk:
28260 case VGF2P8MULBZrmkz:
28261 case VGF2P8MULBZrr:
28262 case VGF2P8MULBZrrk:
28263 case VGF2P8MULBZrrkz:
28264 case VGF2P8MULBrm:
28265 case VGF2P8MULBrr:
28266 return true;
28267 }
28268 return false;
28269}
28270
28271bool isVPUNPCKLBW(unsigned Opcode) {
28272 switch (Opcode) {
28273 case VPUNPCKLBWYrm:
28274 case VPUNPCKLBWYrr:
28275 case VPUNPCKLBWZ128rm:
28276 case VPUNPCKLBWZ128rmk:
28277 case VPUNPCKLBWZ128rmkz:
28278 case VPUNPCKLBWZ128rr:
28279 case VPUNPCKLBWZ128rrk:
28280 case VPUNPCKLBWZ128rrkz:
28281 case VPUNPCKLBWZ256rm:
28282 case VPUNPCKLBWZ256rmk:
28283 case VPUNPCKLBWZ256rmkz:
28284 case VPUNPCKLBWZ256rr:
28285 case VPUNPCKLBWZ256rrk:
28286 case VPUNPCKLBWZ256rrkz:
28287 case VPUNPCKLBWZrm:
28288 case VPUNPCKLBWZrmk:
28289 case VPUNPCKLBWZrmkz:
28290 case VPUNPCKLBWZrr:
28291 case VPUNPCKLBWZrrk:
28292 case VPUNPCKLBWZrrkz:
28293 case VPUNPCKLBWrm:
28294 case VPUNPCKLBWrr:
28295 return true;
28296 }
28297 return false;
28298}
28299
28300bool isVRANGESD(unsigned Opcode) {
28301 switch (Opcode) {
28302 case VRANGESDZrmi:
28303 case VRANGESDZrmik:
28304 case VRANGESDZrmikz:
28305 case VRANGESDZrri:
28306 case VRANGESDZrrib:
28307 case VRANGESDZrribk:
28308 case VRANGESDZrribkz:
28309 case VRANGESDZrrik:
28310 case VRANGESDZrrikz:
28311 return true;
28312 }
28313 return false;
28314}
28315
28316bool isCLD(unsigned Opcode) {
28317 return Opcode == CLD;
28318}
28319
28320bool isVSCALEFPD(unsigned Opcode) {
28321 switch (Opcode) {
28322 case VSCALEFPDZ128rm:
28323 case VSCALEFPDZ128rmb:
28324 case VSCALEFPDZ128rmbk:
28325 case VSCALEFPDZ128rmbkz:
28326 case VSCALEFPDZ128rmk:
28327 case VSCALEFPDZ128rmkz:
28328 case VSCALEFPDZ128rr:
28329 case VSCALEFPDZ128rrk:
28330 case VSCALEFPDZ128rrkz:
28331 case VSCALEFPDZ256rm:
28332 case VSCALEFPDZ256rmb:
28333 case VSCALEFPDZ256rmbk:
28334 case VSCALEFPDZ256rmbkz:
28335 case VSCALEFPDZ256rmk:
28336 case VSCALEFPDZ256rmkz:
28337 case VSCALEFPDZ256rr:
28338 case VSCALEFPDZ256rrk:
28339 case VSCALEFPDZ256rrkz:
28340 case VSCALEFPDZrm:
28341 case VSCALEFPDZrmb:
28342 case VSCALEFPDZrmbk:
28343 case VSCALEFPDZrmbkz:
28344 case VSCALEFPDZrmk:
28345 case VSCALEFPDZrmkz:
28346 case VSCALEFPDZrr:
28347 case VSCALEFPDZrrb:
28348 case VSCALEFPDZrrbk:
28349 case VSCALEFPDZrrbkz:
28350 case VSCALEFPDZrrk:
28351 case VSCALEFPDZrrkz:
28352 return true;
28353 }
28354 return false;
28355}
28356
28357bool isVCOMXSS(unsigned Opcode) {
28358 switch (Opcode) {
28359 case VCOMXSSZrm_Int:
28360 case VCOMXSSZrr_Int:
28361 case VCOMXSSZrrb_Int:
28362 return true;
28363 }
28364 return false;
28365}
28366
28367bool isVPERMQ(unsigned Opcode) {
28368 switch (Opcode) {
28369 case VPERMQYmi:
28370 case VPERMQYri:
28371 case VPERMQZ256mbi:
28372 case VPERMQZ256mbik:
28373 case VPERMQZ256mbikz:
28374 case VPERMQZ256mi:
28375 case VPERMQZ256mik:
28376 case VPERMQZ256mikz:
28377 case VPERMQZ256ri:
28378 case VPERMQZ256rik:
28379 case VPERMQZ256rikz:
28380 case VPERMQZ256rm:
28381 case VPERMQZ256rmb:
28382 case VPERMQZ256rmbk:
28383 case VPERMQZ256rmbkz:
28384 case VPERMQZ256rmk:
28385 case VPERMQZ256rmkz:
28386 case VPERMQZ256rr:
28387 case VPERMQZ256rrk:
28388 case VPERMQZ256rrkz:
28389 case VPERMQZmbi:
28390 case VPERMQZmbik:
28391 case VPERMQZmbikz:
28392 case VPERMQZmi:
28393 case VPERMQZmik:
28394 case VPERMQZmikz:
28395 case VPERMQZri:
28396 case VPERMQZrik:
28397 case VPERMQZrikz:
28398 case VPERMQZrm:
28399 case VPERMQZrmb:
28400 case VPERMQZrmbk:
28401 case VPERMQZrmbkz:
28402 case VPERMQZrmk:
28403 case VPERMQZrmkz:
28404 case VPERMQZrr:
28405 case VPERMQZrrk:
28406 case VPERMQZrrkz:
28407 return true;
28408 }
28409 return false;
28410}
28411
28412bool isVPSHLDVW(unsigned Opcode) {
28413 switch (Opcode) {
28414 case VPSHLDVWZ128m:
28415 case VPSHLDVWZ128mk:
28416 case VPSHLDVWZ128mkz:
28417 case VPSHLDVWZ128r:
28418 case VPSHLDVWZ128rk:
28419 case VPSHLDVWZ128rkz:
28420 case VPSHLDVWZ256m:
28421 case VPSHLDVWZ256mk:
28422 case VPSHLDVWZ256mkz:
28423 case VPSHLDVWZ256r:
28424 case VPSHLDVWZ256rk:
28425 case VPSHLDVWZ256rkz:
28426 case VPSHLDVWZm:
28427 case VPSHLDVWZmk:
28428 case VPSHLDVWZmkz:
28429 case VPSHLDVWZr:
28430 case VPSHLDVWZrk:
28431 case VPSHLDVWZrkz:
28432 return true;
28433 }
28434 return false;
28435}
28436
28437bool isROR(unsigned Opcode) {
28438 switch (Opcode) {
28439 case ROR16m1:
28440 case ROR16m1_EVEX:
28441 case ROR16m1_ND:
28442 case ROR16m1_NF:
28443 case ROR16m1_NF_ND:
28444 case ROR16mCL:
28445 case ROR16mCL_EVEX:
28446 case ROR16mCL_ND:
28447 case ROR16mCL_NF:
28448 case ROR16mCL_NF_ND:
28449 case ROR16mi:
28450 case ROR16mi_EVEX:
28451 case ROR16mi_ND:
28452 case ROR16mi_NF:
28453 case ROR16mi_NF_ND:
28454 case ROR16r1:
28455 case ROR16r1_EVEX:
28456 case ROR16r1_ND:
28457 case ROR16r1_NF:
28458 case ROR16r1_NF_ND:
28459 case ROR16rCL:
28460 case ROR16rCL_EVEX:
28461 case ROR16rCL_ND:
28462 case ROR16rCL_NF:
28463 case ROR16rCL_NF_ND:
28464 case ROR16ri:
28465 case ROR16ri_EVEX:
28466 case ROR16ri_ND:
28467 case ROR16ri_NF:
28468 case ROR16ri_NF_ND:
28469 case ROR32m1:
28470 case ROR32m1_EVEX:
28471 case ROR32m1_ND:
28472 case ROR32m1_NF:
28473 case ROR32m1_NF_ND:
28474 case ROR32mCL:
28475 case ROR32mCL_EVEX:
28476 case ROR32mCL_ND:
28477 case ROR32mCL_NF:
28478 case ROR32mCL_NF_ND:
28479 case ROR32mi:
28480 case ROR32mi_EVEX:
28481 case ROR32mi_ND:
28482 case ROR32mi_NF:
28483 case ROR32mi_NF_ND:
28484 case ROR32r1:
28485 case ROR32r1_EVEX:
28486 case ROR32r1_ND:
28487 case ROR32r1_NF:
28488 case ROR32r1_NF_ND:
28489 case ROR32rCL:
28490 case ROR32rCL_EVEX:
28491 case ROR32rCL_ND:
28492 case ROR32rCL_NF:
28493 case ROR32rCL_NF_ND:
28494 case ROR32ri:
28495 case ROR32ri_EVEX:
28496 case ROR32ri_ND:
28497 case ROR32ri_NF:
28498 case ROR32ri_NF_ND:
28499 case ROR64m1:
28500 case ROR64m1_EVEX:
28501 case ROR64m1_ND:
28502 case ROR64m1_NF:
28503 case ROR64m1_NF_ND:
28504 case ROR64mCL:
28505 case ROR64mCL_EVEX:
28506 case ROR64mCL_ND:
28507 case ROR64mCL_NF:
28508 case ROR64mCL_NF_ND:
28509 case ROR64mi:
28510 case ROR64mi_EVEX:
28511 case ROR64mi_ND:
28512 case ROR64mi_NF:
28513 case ROR64mi_NF_ND:
28514 case ROR64r1:
28515 case ROR64r1_EVEX:
28516 case ROR64r1_ND:
28517 case ROR64r1_NF:
28518 case ROR64r1_NF_ND:
28519 case ROR64rCL:
28520 case ROR64rCL_EVEX:
28521 case ROR64rCL_ND:
28522 case ROR64rCL_NF:
28523 case ROR64rCL_NF_ND:
28524 case ROR64ri:
28525 case ROR64ri_EVEX:
28526 case ROR64ri_ND:
28527 case ROR64ri_NF:
28528 case ROR64ri_NF_ND:
28529 case ROR8m1:
28530 case ROR8m1_EVEX:
28531 case ROR8m1_ND:
28532 case ROR8m1_NF:
28533 case ROR8m1_NF_ND:
28534 case ROR8mCL:
28535 case ROR8mCL_EVEX:
28536 case ROR8mCL_ND:
28537 case ROR8mCL_NF:
28538 case ROR8mCL_NF_ND:
28539 case ROR8mi:
28540 case ROR8mi_EVEX:
28541 case ROR8mi_ND:
28542 case ROR8mi_NF:
28543 case ROR8mi_NF_ND:
28544 case ROR8r1:
28545 case ROR8r1_EVEX:
28546 case ROR8r1_ND:
28547 case ROR8r1_NF:
28548 case ROR8r1_NF_ND:
28549 case ROR8rCL:
28550 case ROR8rCL_EVEX:
28551 case ROR8rCL_ND:
28552 case ROR8rCL_NF:
28553 case ROR8rCL_NF_ND:
28554 case ROR8ri:
28555 case ROR8ri_EVEX:
28556 case ROR8ri_ND:
28557 case ROR8ri_NF:
28558 case ROR8ri_NF_ND:
28559 return true;
28560 }
28561 return false;
28562}
28563
28564bool isVFMADDSUB132PH(unsigned Opcode) {
28565 switch (Opcode) {
28566 case VFMADDSUB132PHZ128m:
28567 case VFMADDSUB132PHZ128mb:
28568 case VFMADDSUB132PHZ128mbk:
28569 case VFMADDSUB132PHZ128mbkz:
28570 case VFMADDSUB132PHZ128mk:
28571 case VFMADDSUB132PHZ128mkz:
28572 case VFMADDSUB132PHZ128r:
28573 case VFMADDSUB132PHZ128rk:
28574 case VFMADDSUB132PHZ128rkz:
28575 case VFMADDSUB132PHZ256m:
28576 case VFMADDSUB132PHZ256mb:
28577 case VFMADDSUB132PHZ256mbk:
28578 case VFMADDSUB132PHZ256mbkz:
28579 case VFMADDSUB132PHZ256mk:
28580 case VFMADDSUB132PHZ256mkz:
28581 case VFMADDSUB132PHZ256r:
28582 case VFMADDSUB132PHZ256rk:
28583 case VFMADDSUB132PHZ256rkz:
28584 case VFMADDSUB132PHZm:
28585 case VFMADDSUB132PHZmb:
28586 case VFMADDSUB132PHZmbk:
28587 case VFMADDSUB132PHZmbkz:
28588 case VFMADDSUB132PHZmk:
28589 case VFMADDSUB132PHZmkz:
28590 case VFMADDSUB132PHZr:
28591 case VFMADDSUB132PHZrb:
28592 case VFMADDSUB132PHZrbk:
28593 case VFMADDSUB132PHZrbkz:
28594 case VFMADDSUB132PHZrk:
28595 case VFMADDSUB132PHZrkz:
28596 return true;
28597 }
28598 return false;
28599}
28600
28601bool isDEC(unsigned Opcode) {
28602 switch (Opcode) {
28603 case DEC16m:
28604 case DEC16m_EVEX:
28605 case DEC16m_ND:
28606 case DEC16m_NF:
28607 case DEC16m_NF_ND:
28608 case DEC16r:
28609 case DEC16r_EVEX:
28610 case DEC16r_ND:
28611 case DEC16r_NF:
28612 case DEC16r_NF_ND:
28613 case DEC16r_alt:
28614 case DEC32m:
28615 case DEC32m_EVEX:
28616 case DEC32m_ND:
28617 case DEC32m_NF:
28618 case DEC32m_NF_ND:
28619 case DEC32r:
28620 case DEC32r_EVEX:
28621 case DEC32r_ND:
28622 case DEC32r_NF:
28623 case DEC32r_NF_ND:
28624 case DEC32r_alt:
28625 case DEC64m:
28626 case DEC64m_EVEX:
28627 case DEC64m_ND:
28628 case DEC64m_NF:
28629 case DEC64m_NF_ND:
28630 case DEC64r:
28631 case DEC64r_EVEX:
28632 case DEC64r_ND:
28633 case DEC64r_NF:
28634 case DEC64r_NF_ND:
28635 case DEC8m:
28636 case DEC8m_EVEX:
28637 case DEC8m_ND:
28638 case DEC8m_NF:
28639 case DEC8m_NF_ND:
28640 case DEC8r:
28641 case DEC8r_EVEX:
28642 case DEC8r_ND:
28643 case DEC8r_NF:
28644 case DEC8r_NF_ND:
28645 return true;
28646 }
28647 return false;
28648}
28649
28650bool isVGETEXPSH(unsigned Opcode) {
28651 switch (Opcode) {
28652 case VGETEXPSHZm:
28653 case VGETEXPSHZmk:
28654 case VGETEXPSHZmkz:
28655 case VGETEXPSHZr:
28656 case VGETEXPSHZrb:
28657 case VGETEXPSHZrbk:
28658 case VGETEXPSHZrbkz:
28659 case VGETEXPSHZrk:
28660 case VGETEXPSHZrkz:
28661 return true;
28662 }
28663 return false;
28664}
28665
28666bool isAESDEC(unsigned Opcode) {
28667 switch (Opcode) {
28668 case AESDECrm:
28669 case AESDECrr:
28670 return true;
28671 }
28672 return false;
28673}
28674
28675bool isKORD(unsigned Opcode) {
28676 return Opcode == KORDkk;
28677}
28678
28679bool isTILELOADDT1(unsigned Opcode) {
28680 switch (Opcode) {
28681 case TILELOADDT1:
28682 case TILELOADDT1_EVEX:
28683 return true;
28684 }
28685 return false;
28686}
28687
28688bool isVPMULHW(unsigned Opcode) {
28689 switch (Opcode) {
28690 case VPMULHWYrm:
28691 case VPMULHWYrr:
28692 case VPMULHWZ128rm:
28693 case VPMULHWZ128rmk:
28694 case VPMULHWZ128rmkz:
28695 case VPMULHWZ128rr:
28696 case VPMULHWZ128rrk:
28697 case VPMULHWZ128rrkz:
28698 case VPMULHWZ256rm:
28699 case VPMULHWZ256rmk:
28700 case VPMULHWZ256rmkz:
28701 case VPMULHWZ256rr:
28702 case VPMULHWZ256rrk:
28703 case VPMULHWZ256rrkz:
28704 case VPMULHWZrm:
28705 case VPMULHWZrmk:
28706 case VPMULHWZrmkz:
28707 case VPMULHWZrr:
28708 case VPMULHWZrrk:
28709 case VPMULHWZrrkz:
28710 case VPMULHWrm:
28711 case VPMULHWrr:
28712 return true;
28713 }
28714 return false;
28715}
28716
28717bool isVMASKMOVPS(unsigned Opcode) {
28718 switch (Opcode) {
28719 case VMASKMOVPSYmr:
28720 case VMASKMOVPSYrm:
28721 case VMASKMOVPSmr:
28722 case VMASKMOVPSrm:
28723 return true;
28724 }
28725 return false;
28726}
28727
28728bool isPMOVZXDQ(unsigned Opcode) {
28729 switch (Opcode) {
28730 case PMOVZXDQrm:
28731 case PMOVZXDQrr:
28732 return true;
28733 }
28734 return false;
28735}
28736
28737bool isVCVTPS2PH(unsigned Opcode) {
28738 switch (Opcode) {
28739 case VCVTPS2PHYmr:
28740 case VCVTPS2PHYrr:
28741 case VCVTPS2PHZ128mr:
28742 case VCVTPS2PHZ128mrk:
28743 case VCVTPS2PHZ128rr:
28744 case VCVTPS2PHZ128rrk:
28745 case VCVTPS2PHZ128rrkz:
28746 case VCVTPS2PHZ256mr:
28747 case VCVTPS2PHZ256mrk:
28748 case VCVTPS2PHZ256rr:
28749 case VCVTPS2PHZ256rrk:
28750 case VCVTPS2PHZ256rrkz:
28751 case VCVTPS2PHZmr:
28752 case VCVTPS2PHZmrk:
28753 case VCVTPS2PHZrr:
28754 case VCVTPS2PHZrrb:
28755 case VCVTPS2PHZrrbk:
28756 case VCVTPS2PHZrrbkz:
28757 case VCVTPS2PHZrrk:
28758 case VCVTPS2PHZrrkz:
28759 case VCVTPS2PHmr:
28760 case VCVTPS2PHrr:
28761 return true;
28762 }
28763 return false;
28764}
28765
28766bool isCVTDQ2PD(unsigned Opcode) {
28767 switch (Opcode) {
28768 case CVTDQ2PDrm:
28769 case CVTDQ2PDrr:
28770 return true;
28771 }
28772 return false;
28773}
28774
28775bool isVCVTSD2SS(unsigned Opcode) {
28776 switch (Opcode) {
28777 case VCVTSD2SSZrm_Int:
28778 case VCVTSD2SSZrmk_Int:
28779 case VCVTSD2SSZrmkz_Int:
28780 case VCVTSD2SSZrr_Int:
28781 case VCVTSD2SSZrrb_Int:
28782 case VCVTSD2SSZrrbk_Int:
28783 case VCVTSD2SSZrrbkz_Int:
28784 case VCVTSD2SSZrrk_Int:
28785 case VCVTSD2SSZrrkz_Int:
28786 case VCVTSD2SSrm_Int:
28787 case VCVTSD2SSrr_Int:
28788 return true;
28789 }
28790 return false;
28791}
28792
28793bool isVFMSUB213PH(unsigned Opcode) {
28794 switch (Opcode) {
28795 case VFMSUB213PHZ128m:
28796 case VFMSUB213PHZ128mb:
28797 case VFMSUB213PHZ128mbk:
28798 case VFMSUB213PHZ128mbkz:
28799 case VFMSUB213PHZ128mk:
28800 case VFMSUB213PHZ128mkz:
28801 case VFMSUB213PHZ128r:
28802 case VFMSUB213PHZ128rk:
28803 case VFMSUB213PHZ128rkz:
28804 case VFMSUB213PHZ256m:
28805 case VFMSUB213PHZ256mb:
28806 case VFMSUB213PHZ256mbk:
28807 case VFMSUB213PHZ256mbkz:
28808 case VFMSUB213PHZ256mk:
28809 case VFMSUB213PHZ256mkz:
28810 case VFMSUB213PHZ256r:
28811 case VFMSUB213PHZ256rk:
28812 case VFMSUB213PHZ256rkz:
28813 case VFMSUB213PHZm:
28814 case VFMSUB213PHZmb:
28815 case VFMSUB213PHZmbk:
28816 case VFMSUB213PHZmbkz:
28817 case VFMSUB213PHZmk:
28818 case VFMSUB213PHZmkz:
28819 case VFMSUB213PHZr:
28820 case VFMSUB213PHZrb:
28821 case VFMSUB213PHZrbk:
28822 case VFMSUB213PHZrbkz:
28823 case VFMSUB213PHZrk:
28824 case VFMSUB213PHZrkz:
28825 return true;
28826 }
28827 return false;
28828}
28829
28830bool isVPROTB(unsigned Opcode) {
28831 switch (Opcode) {
28832 case VPROTBmi:
28833 case VPROTBmr:
28834 case VPROTBri:
28835 case VPROTBrm:
28836 case VPROTBrr:
28837 case VPROTBrr_REV:
28838 return true;
28839 }
28840 return false;
28841}
28842
28843bool isPINSRD(unsigned Opcode) {
28844 switch (Opcode) {
28845 case PINSRDrmi:
28846 case PINSRDrri:
28847 return true;
28848 }
28849 return false;
28850}
28851
28852bool isVMXON(unsigned Opcode) {
28853 return Opcode == VMXON;
28854}
28855
28856bool isVFCMULCSH(unsigned Opcode) {
28857 switch (Opcode) {
28858 case VFCMULCSHZrm:
28859 case VFCMULCSHZrmk:
28860 case VFCMULCSHZrmkz:
28861 case VFCMULCSHZrr:
28862 case VFCMULCSHZrrb:
28863 case VFCMULCSHZrrbk:
28864 case VFCMULCSHZrrbkz:
28865 case VFCMULCSHZrrk:
28866 case VFCMULCSHZrrkz:
28867 return true;
28868 }
28869 return false;
28870}
28871
28872bool isVFMULCSH(unsigned Opcode) {
28873 switch (Opcode) {
28874 case VFMULCSHZrm:
28875 case VFMULCSHZrmk:
28876 case VFMULCSHZrmkz:
28877 case VFMULCSHZrr:
28878 case VFMULCSHZrrb:
28879 case VFMULCSHZrrbk:
28880 case VFMULCSHZrrbkz:
28881 case VFMULCSHZrrk:
28882 case VFMULCSHZrrkz:
28883 return true;
28884 }
28885 return false;
28886}
28887
28888bool isVRANGEPD(unsigned Opcode) {
28889 switch (Opcode) {
28890 case VRANGEPDZ128rmbi:
28891 case VRANGEPDZ128rmbik:
28892 case VRANGEPDZ128rmbikz:
28893 case VRANGEPDZ128rmi:
28894 case VRANGEPDZ128rmik:
28895 case VRANGEPDZ128rmikz:
28896 case VRANGEPDZ128rri:
28897 case VRANGEPDZ128rrik:
28898 case VRANGEPDZ128rrikz:
28899 case VRANGEPDZ256rmbi:
28900 case VRANGEPDZ256rmbik:
28901 case VRANGEPDZ256rmbikz:
28902 case VRANGEPDZ256rmi:
28903 case VRANGEPDZ256rmik:
28904 case VRANGEPDZ256rmikz:
28905 case VRANGEPDZ256rri:
28906 case VRANGEPDZ256rrik:
28907 case VRANGEPDZ256rrikz:
28908 case VRANGEPDZrmbi:
28909 case VRANGEPDZrmbik:
28910 case VRANGEPDZrmbikz:
28911 case VRANGEPDZrmi:
28912 case VRANGEPDZrmik:
28913 case VRANGEPDZrmikz:
28914 case VRANGEPDZrri:
28915 case VRANGEPDZrrib:
28916 case VRANGEPDZrribk:
28917 case VRANGEPDZrribkz:
28918 case VRANGEPDZrrik:
28919 case VRANGEPDZrrikz:
28920 return true;
28921 }
28922 return false;
28923}
28924
28925bool isCMC(unsigned Opcode) {
28926 return Opcode == CMC;
28927}
28928
28929bool isVFNMADD231BF16(unsigned Opcode) {
28930 switch (Opcode) {
28931 case VFNMADD231BF16Z128m:
28932 case VFNMADD231BF16Z128mb:
28933 case VFNMADD231BF16Z128mbk:
28934 case VFNMADD231BF16Z128mbkz:
28935 case VFNMADD231BF16Z128mk:
28936 case VFNMADD231BF16Z128mkz:
28937 case VFNMADD231BF16Z128r:
28938 case VFNMADD231BF16Z128rk:
28939 case VFNMADD231BF16Z128rkz:
28940 case VFNMADD231BF16Z256m:
28941 case VFNMADD231BF16Z256mb:
28942 case VFNMADD231BF16Z256mbk:
28943 case VFNMADD231BF16Z256mbkz:
28944 case VFNMADD231BF16Z256mk:
28945 case VFNMADD231BF16Z256mkz:
28946 case VFNMADD231BF16Z256r:
28947 case VFNMADD231BF16Z256rk:
28948 case VFNMADD231BF16Z256rkz:
28949 case VFNMADD231BF16Zm:
28950 case VFNMADD231BF16Zmb:
28951 case VFNMADD231BF16Zmbk:
28952 case VFNMADD231BF16Zmbkz:
28953 case VFNMADD231BF16Zmk:
28954 case VFNMADD231BF16Zmkz:
28955 case VFNMADD231BF16Zr:
28956 case VFNMADD231BF16Zrk:
28957 case VFNMADD231BF16Zrkz:
28958 return true;
28959 }
28960 return false;
28961}
28962
28963bool isSHA256MSG1(unsigned Opcode) {
28964 switch (Opcode) {
28965 case SHA256MSG1rm:
28966 case SHA256MSG1rr:
28967 return true;
28968 }
28969 return false;
28970}
28971
28972bool isFLD1(unsigned Opcode) {
28973 return Opcode == LD_F1;
28974}
28975
28976bool isCMPPS(unsigned Opcode) {
28977 switch (Opcode) {
28978 case CMPPSrmi:
28979 case CMPPSrri:
28980 return true;
28981 }
28982 return false;
28983}
28984
28985bool isVPAVGW(unsigned Opcode) {
28986 switch (Opcode) {
28987 case VPAVGWYrm:
28988 case VPAVGWYrr:
28989 case VPAVGWZ128rm:
28990 case VPAVGWZ128rmk:
28991 case VPAVGWZ128rmkz:
28992 case VPAVGWZ128rr:
28993 case VPAVGWZ128rrk:
28994 case VPAVGWZ128rrkz:
28995 case VPAVGWZ256rm:
28996 case VPAVGWZ256rmk:
28997 case VPAVGWZ256rmkz:
28998 case VPAVGWZ256rr:
28999 case VPAVGWZ256rrk:
29000 case VPAVGWZ256rrkz:
29001 case VPAVGWZrm:
29002 case VPAVGWZrmk:
29003 case VPAVGWZrmkz:
29004 case VPAVGWZrr:
29005 case VPAVGWZrrk:
29006 case VPAVGWZrrkz:
29007 case VPAVGWrm:
29008 case VPAVGWrr:
29009 return true;
29010 }
29011 return false;
29012}
29013
29014bool isVFMADD213SH(unsigned Opcode) {
29015 switch (Opcode) {
29016 case VFMADD213SHZm_Int:
29017 case VFMADD213SHZmk_Int:
29018 case VFMADD213SHZmkz_Int:
29019 case VFMADD213SHZr_Int:
29020 case VFMADD213SHZrb_Int:
29021 case VFMADD213SHZrbk_Int:
29022 case VFMADD213SHZrbkz_Int:
29023 case VFMADD213SHZrk_Int:
29024 case VFMADD213SHZrkz_Int:
29025 return true;
29026 }
29027 return false;
29028}
29029
29030bool isVPCMPESTRMQ(unsigned Opcode) {
29031 switch (Opcode) {
29032 case VPCMPESTRMQrmi:
29033 case VPCMPESTRMQrri:
29034 return true;
29035 }
29036 return false;
29037}
29038
29039bool isVPINSRQ(unsigned Opcode) {
29040 switch (Opcode) {
29041 case VPINSRQZrmi:
29042 case VPINSRQZrri:
29043 case VPINSRQrmi:
29044 case VPINSRQrri:
29045 return true;
29046 }
29047 return false;
29048}
29049
29050bool isMOVABS(unsigned Opcode) {
29051 switch (Opcode) {
29052 case MOV16ao64:
29053 case MOV16o64a:
29054 case MOV32ao64:
29055 case MOV32o64a:
29056 case MOV64ao64:
29057 case MOV64o64a:
29058 case MOV64ri:
29059 case MOV8ao64:
29060 case MOV8o64a:
29061 return true;
29062 }
29063 return false;
29064}
29065
29066bool isVPSHAQ(unsigned Opcode) {
29067 switch (Opcode) {
29068 case VPSHAQmr:
29069 case VPSHAQrm:
29070 case VPSHAQrr:
29071 case VPSHAQrr_REV:
29072 return true;
29073 }
29074 return false;
29075}
29076
29077bool isRDTSCP(unsigned Opcode) {
29078 return Opcode == RDTSCP;
29079}
29080
29081bool isVFNMADD231SS(unsigned Opcode) {
29082 switch (Opcode) {
29083 case VFNMADD231SSZm_Int:
29084 case VFNMADD231SSZmk_Int:
29085 case VFNMADD231SSZmkz_Int:
29086 case VFNMADD231SSZr_Int:
29087 case VFNMADD231SSZrb_Int:
29088 case VFNMADD231SSZrbk_Int:
29089 case VFNMADD231SSZrbkz_Int:
29090 case VFNMADD231SSZrk_Int:
29091 case VFNMADD231SSZrkz_Int:
29092 case VFNMADD231SSm_Int:
29093 case VFNMADD231SSr_Int:
29094 return true;
29095 }
29096 return false;
29097}
29098
29099bool isTEST(unsigned Opcode) {
29100 switch (Opcode) {
29101 case TEST16i16:
29102 case TEST16mi:
29103 case TEST16mr:
29104 case TEST16ri:
29105 case TEST16rr:
29106 case TEST32i32:
29107 case TEST32mi:
29108 case TEST32mr:
29109 case TEST32ri:
29110 case TEST32rr:
29111 case TEST64i32:
29112 case TEST64mi32:
29113 case TEST64mr:
29114 case TEST64ri32:
29115 case TEST64rr:
29116 case TEST8i8:
29117 case TEST8mi:
29118 case TEST8mr:
29119 case TEST8ri:
29120 case TEST8rr:
29121 return true;
29122 }
29123 return false;
29124}
29125
29126bool isVPERMD(unsigned Opcode) {
29127 switch (Opcode) {
29128 case VPERMDYrm:
29129 case VPERMDYrr:
29130 case VPERMDZ256rm:
29131 case VPERMDZ256rmb:
29132 case VPERMDZ256rmbk:
29133 case VPERMDZ256rmbkz:
29134 case VPERMDZ256rmk:
29135 case VPERMDZ256rmkz:
29136 case VPERMDZ256rr:
29137 case VPERMDZ256rrk:
29138 case VPERMDZ256rrkz:
29139 case VPERMDZrm:
29140 case VPERMDZrmb:
29141 case VPERMDZrmbk:
29142 case VPERMDZrmbkz:
29143 case VPERMDZrmk:
29144 case VPERMDZrmkz:
29145 case VPERMDZrr:
29146 case VPERMDZrrk:
29147 case VPERMDZrrkz:
29148 return true;
29149 }
29150 return false;
29151}
29152
29153bool isVBCSTNESH2PS(unsigned Opcode) {
29154 switch (Opcode) {
29155 case VBCSTNESH2PSYrm:
29156 case VBCSTNESH2PSrm:
29157 return true;
29158 }
29159 return false;
29160}
29161
29162bool isVGATHERPF0QPD(unsigned Opcode) {
29163 return Opcode == VGATHERPF0QPDm;
29164}
29165
29166bool isVPERM2I128(unsigned Opcode) {
29167 switch (Opcode) {
29168 case VPERM2I128rmi:
29169 case VPERM2I128rri:
29170 return true;
29171 }
29172 return false;
29173}
29174
29175bool isVMPSADBW(unsigned Opcode) {
29176 switch (Opcode) {
29177 case VMPSADBWYrmi:
29178 case VMPSADBWYrri:
29179 case VMPSADBWZ128rmi:
29180 case VMPSADBWZ128rmik:
29181 case VMPSADBWZ128rmikz:
29182 case VMPSADBWZ128rri:
29183 case VMPSADBWZ128rrik:
29184 case VMPSADBWZ128rrikz:
29185 case VMPSADBWZ256rmi:
29186 case VMPSADBWZ256rmik:
29187 case VMPSADBWZ256rmikz:
29188 case VMPSADBWZ256rri:
29189 case VMPSADBWZ256rrik:
29190 case VMPSADBWZ256rrikz:
29191 case VMPSADBWZrmi:
29192 case VMPSADBWZrmik:
29193 case VMPSADBWZrmikz:
29194 case VMPSADBWZrri:
29195 case VMPSADBWZrrik:
29196 case VMPSADBWZrrikz:
29197 case VMPSADBWrmi:
29198 case VMPSADBWrri:
29199 return true;
29200 }
29201 return false;
29202}
29203
29204bool isVFNMSUB231PD(unsigned Opcode) {
29205 switch (Opcode) {
29206 case VFNMSUB231PDYm:
29207 case VFNMSUB231PDYr:
29208 case VFNMSUB231PDZ128m:
29209 case VFNMSUB231PDZ128mb:
29210 case VFNMSUB231PDZ128mbk:
29211 case VFNMSUB231PDZ128mbkz:
29212 case VFNMSUB231PDZ128mk:
29213 case VFNMSUB231PDZ128mkz:
29214 case VFNMSUB231PDZ128r:
29215 case VFNMSUB231PDZ128rk:
29216 case VFNMSUB231PDZ128rkz:
29217 case VFNMSUB231PDZ256m:
29218 case VFNMSUB231PDZ256mb:
29219 case VFNMSUB231PDZ256mbk:
29220 case VFNMSUB231PDZ256mbkz:
29221 case VFNMSUB231PDZ256mk:
29222 case VFNMSUB231PDZ256mkz:
29223 case VFNMSUB231PDZ256r:
29224 case VFNMSUB231PDZ256rk:
29225 case VFNMSUB231PDZ256rkz:
29226 case VFNMSUB231PDZm:
29227 case VFNMSUB231PDZmb:
29228 case VFNMSUB231PDZmbk:
29229 case VFNMSUB231PDZmbkz:
29230 case VFNMSUB231PDZmk:
29231 case VFNMSUB231PDZmkz:
29232 case VFNMSUB231PDZr:
29233 case VFNMSUB231PDZrb:
29234 case VFNMSUB231PDZrbk:
29235 case VFNMSUB231PDZrbkz:
29236 case VFNMSUB231PDZrk:
29237 case VFNMSUB231PDZrkz:
29238 case VFNMSUB231PDm:
29239 case VFNMSUB231PDr:
29240 return true;
29241 }
29242 return false;
29243}
29244
29245bool isPADDSB(unsigned Opcode) {
29246 switch (Opcode) {
29247 case MMX_PADDSBrm:
29248 case MMX_PADDSBrr:
29249 case PADDSBrm:
29250 case PADDSBrr:
29251 return true;
29252 }
29253 return false;
29254}
29255
29256bool isMWAITX(unsigned Opcode) {
29257 return Opcode == MWAITXrrr;
29258}
29259
29260bool isMONITORX(unsigned Opcode) {
29261 switch (Opcode) {
29262 case MONITORX32rrr:
29263 case MONITORX64rrr:
29264 return true;
29265 }
29266 return false;
29267}
29268
29269bool isVPEXPANDD(unsigned Opcode) {
29270 switch (Opcode) {
29271 case VPEXPANDDZ128rm:
29272 case VPEXPANDDZ128rmk:
29273 case VPEXPANDDZ128rmkz:
29274 case VPEXPANDDZ128rr:
29275 case VPEXPANDDZ128rrk:
29276 case VPEXPANDDZ128rrkz:
29277 case VPEXPANDDZ256rm:
29278 case VPEXPANDDZ256rmk:
29279 case VPEXPANDDZ256rmkz:
29280 case VPEXPANDDZ256rr:
29281 case VPEXPANDDZ256rrk:
29282 case VPEXPANDDZ256rrkz:
29283 case VPEXPANDDZrm:
29284 case VPEXPANDDZrmk:
29285 case VPEXPANDDZrmkz:
29286 case VPEXPANDDZrr:
29287 case VPEXPANDDZrrk:
29288 case VPEXPANDDZrrkz:
29289 return true;
29290 }
29291 return false;
29292}
29293
29294bool isVFRCZPD(unsigned Opcode) {
29295 switch (Opcode) {
29296 case VFRCZPDYrm:
29297 case VFRCZPDYrr:
29298 case VFRCZPDrm:
29299 case VFRCZPDrr:
29300 return true;
29301 }
29302 return false;
29303}
29304
29305bool isVRCPPH(unsigned Opcode) {
29306 switch (Opcode) {
29307 case VRCPPHZ128m:
29308 case VRCPPHZ128mb:
29309 case VRCPPHZ128mbk:
29310 case VRCPPHZ128mbkz:
29311 case VRCPPHZ128mk:
29312 case VRCPPHZ128mkz:
29313 case VRCPPHZ128r:
29314 case VRCPPHZ128rk:
29315 case VRCPPHZ128rkz:
29316 case VRCPPHZ256m:
29317 case VRCPPHZ256mb:
29318 case VRCPPHZ256mbk:
29319 case VRCPPHZ256mbkz:
29320 case VRCPPHZ256mk:
29321 case VRCPPHZ256mkz:
29322 case VRCPPHZ256r:
29323 case VRCPPHZ256rk:
29324 case VRCPPHZ256rkz:
29325 case VRCPPHZm:
29326 case VRCPPHZmb:
29327 case VRCPPHZmbk:
29328 case VRCPPHZmbkz:
29329 case VRCPPHZmk:
29330 case VRCPPHZmkz:
29331 case VRCPPHZr:
29332 case VRCPPHZrk:
29333 case VRCPPHZrkz:
29334 return true;
29335 }
29336 return false;
29337}
29338
29339bool isFEMMS(unsigned Opcode) {
29340 return Opcode == FEMMS;
29341}
29342
29343bool isVSCATTERQPD(unsigned Opcode) {
29344 switch (Opcode) {
29345 case VSCATTERQPDZ128mr:
29346 case VSCATTERQPDZ256mr:
29347 case VSCATTERQPDZmr:
29348 return true;
29349 }
29350 return false;
29351}
29352
29353bool isVMOVW(unsigned Opcode) {
29354 switch (Opcode) {
29355 case VMOVSH2Wrr:
29356 case VMOVSHtoW64rr:
29357 case VMOVW2SHrr:
29358 case VMOVW64toSHrr:
29359 case VMOVWmr:
29360 case VMOVWrm:
29361 case VMOVZPWILo2PWIZmr:
29362 case VMOVZPWILo2PWIZrm:
29363 case VMOVZPWILo2PWIZrr:
29364 case VMOVZPWILo2PWIZrr2:
29365 return true;
29366 }
29367 return false;
29368}
29369
29370bool isVPBROADCASTD(unsigned Opcode) {
29371 switch (Opcode) {
29372 case VPBROADCASTDYrm:
29373 case VPBROADCASTDYrr:
29374 case VPBROADCASTDZ128rm:
29375 case VPBROADCASTDZ128rmk:
29376 case VPBROADCASTDZ128rmkz:
29377 case VPBROADCASTDZ128rr:
29378 case VPBROADCASTDZ128rrk:
29379 case VPBROADCASTDZ128rrkz:
29380 case VPBROADCASTDZ256rm:
29381 case VPBROADCASTDZ256rmk:
29382 case VPBROADCASTDZ256rmkz:
29383 case VPBROADCASTDZ256rr:
29384 case VPBROADCASTDZ256rrk:
29385 case VPBROADCASTDZ256rrkz:
29386 case VPBROADCASTDZrm:
29387 case VPBROADCASTDZrmk:
29388 case VPBROADCASTDZrmkz:
29389 case VPBROADCASTDZrr:
29390 case VPBROADCASTDZrrk:
29391 case VPBROADCASTDZrrkz:
29392 case VPBROADCASTDrZ128rr:
29393 case VPBROADCASTDrZ128rrk:
29394 case VPBROADCASTDrZ128rrkz:
29395 case VPBROADCASTDrZ256rr:
29396 case VPBROADCASTDrZ256rrk:
29397 case VPBROADCASTDrZ256rrkz:
29398 case VPBROADCASTDrZrr:
29399 case VPBROADCASTDrZrrk:
29400 case VPBROADCASTDrZrrkz:
29401 case VPBROADCASTDrm:
29402 case VPBROADCASTDrr:
29403 return true;
29404 }
29405 return false;
29406}
29407
29408bool isSTOSB(unsigned Opcode) {
29409 return Opcode == STOSB;
29410}
29411
29412bool isFUCOMI(unsigned Opcode) {
29413 return Opcode == UCOM_FIr;
29414}
29415
29416bool isVBROADCASTI64X4(unsigned Opcode) {
29417 switch (Opcode) {
29418 case VBROADCASTI64X4Zrm:
29419 case VBROADCASTI64X4Zrmk:
29420 case VBROADCASTI64X4Zrmkz:
29421 return true;
29422 }
29423 return false;
29424}
29425
29426bool isFCMOVU(unsigned Opcode) {
29427 return Opcode == CMOVP_F;
29428}
29429
29430bool isPSHUFLW(unsigned Opcode) {
29431 switch (Opcode) {
29432 case PSHUFLWmi:
29433 case PSHUFLWri:
29434 return true;
29435 }
29436 return false;
29437}
29438
29439bool isCVTPI2PS(unsigned Opcode) {
29440 switch (Opcode) {
29441 case MMX_CVTPI2PSrm:
29442 case MMX_CVTPI2PSrr:
29443 return true;
29444 }
29445 return false;
29446}
29447
29448bool isVCVTTPD2UDQS(unsigned Opcode) {
29449 switch (Opcode) {
29450 case VCVTTPD2UDQSZ128rm:
29451 case VCVTTPD2UDQSZ128rmb:
29452 case VCVTTPD2UDQSZ128rmbk:
29453 case VCVTTPD2UDQSZ128rmbkz:
29454 case VCVTTPD2UDQSZ128rmk:
29455 case VCVTTPD2UDQSZ128rmkz:
29456 case VCVTTPD2UDQSZ128rr:
29457 case VCVTTPD2UDQSZ128rrk:
29458 case VCVTTPD2UDQSZ128rrkz:
29459 case VCVTTPD2UDQSZ256rm:
29460 case VCVTTPD2UDQSZ256rmb:
29461 case VCVTTPD2UDQSZ256rmbk:
29462 case VCVTTPD2UDQSZ256rmbkz:
29463 case VCVTTPD2UDQSZ256rmk:
29464 case VCVTTPD2UDQSZ256rmkz:
29465 case VCVTTPD2UDQSZ256rr:
29466 case VCVTTPD2UDQSZ256rrb:
29467 case VCVTTPD2UDQSZ256rrbk:
29468 case VCVTTPD2UDQSZ256rrbkz:
29469 case VCVTTPD2UDQSZ256rrk:
29470 case VCVTTPD2UDQSZ256rrkz:
29471 case VCVTTPD2UDQSZrm:
29472 case VCVTTPD2UDQSZrmb:
29473 case VCVTTPD2UDQSZrmbk:
29474 case VCVTTPD2UDQSZrmbkz:
29475 case VCVTTPD2UDQSZrmk:
29476 case VCVTTPD2UDQSZrmkz:
29477 case VCVTTPD2UDQSZrr:
29478 case VCVTTPD2UDQSZrrb:
29479 case VCVTTPD2UDQSZrrbk:
29480 case VCVTTPD2UDQSZrrbkz:
29481 case VCVTTPD2UDQSZrrk:
29482 case VCVTTPD2UDQSZrrkz:
29483 return true;
29484 }
29485 return false;
29486}
29487
29488bool isSYSCALL(unsigned Opcode) {
29489 return Opcode == SYSCALL;
29490}
29491
29492bool isVFMADD231SH(unsigned Opcode) {
29493 switch (Opcode) {
29494 case VFMADD231SHZm_Int:
29495 case VFMADD231SHZmk_Int:
29496 case VFMADD231SHZmkz_Int:
29497 case VFMADD231SHZr_Int:
29498 case VFMADD231SHZrb_Int:
29499 case VFMADD231SHZrbk_Int:
29500 case VFMADD231SHZrbkz_Int:
29501 case VFMADD231SHZrk_Int:
29502 case VFMADD231SHZrkz_Int:
29503 return true;
29504 }
29505 return false;
29506}
29507
29508bool isVPOPCNTB(unsigned Opcode) {
29509 switch (Opcode) {
29510 case VPOPCNTBZ128rm:
29511 case VPOPCNTBZ128rmk:
29512 case VPOPCNTBZ128rmkz:
29513 case VPOPCNTBZ128rr:
29514 case VPOPCNTBZ128rrk:
29515 case VPOPCNTBZ128rrkz:
29516 case VPOPCNTBZ256rm:
29517 case VPOPCNTBZ256rmk:
29518 case VPOPCNTBZ256rmkz:
29519 case VPOPCNTBZ256rr:
29520 case VPOPCNTBZ256rrk:
29521 case VPOPCNTBZ256rrkz:
29522 case VPOPCNTBZrm:
29523 case VPOPCNTBZrmk:
29524 case VPOPCNTBZrmkz:
29525 case VPOPCNTBZrr:
29526 case VPOPCNTBZrrk:
29527 case VPOPCNTBZrrkz:
29528 return true;
29529 }
29530 return false;
29531}
29532
29533bool isPMOVZXBW(unsigned Opcode) {
29534 switch (Opcode) {
29535 case PMOVZXBWrm:
29536 case PMOVZXBWrr:
29537 return true;
29538 }
29539 return false;
29540}
29541
29542bool isVCVTDQ2PS(unsigned Opcode) {
29543 switch (Opcode) {
29544 case VCVTDQ2PSYrm:
29545 case VCVTDQ2PSYrr:
29546 case VCVTDQ2PSZ128rm:
29547 case VCVTDQ2PSZ128rmb:
29548 case VCVTDQ2PSZ128rmbk:
29549 case VCVTDQ2PSZ128rmbkz:
29550 case VCVTDQ2PSZ128rmk:
29551 case VCVTDQ2PSZ128rmkz:
29552 case VCVTDQ2PSZ128rr:
29553 case VCVTDQ2PSZ128rrk:
29554 case VCVTDQ2PSZ128rrkz:
29555 case VCVTDQ2PSZ256rm:
29556 case VCVTDQ2PSZ256rmb:
29557 case VCVTDQ2PSZ256rmbk:
29558 case VCVTDQ2PSZ256rmbkz:
29559 case VCVTDQ2PSZ256rmk:
29560 case VCVTDQ2PSZ256rmkz:
29561 case VCVTDQ2PSZ256rr:
29562 case VCVTDQ2PSZ256rrk:
29563 case VCVTDQ2PSZ256rrkz:
29564 case VCVTDQ2PSZrm:
29565 case VCVTDQ2PSZrmb:
29566 case VCVTDQ2PSZrmbk:
29567 case VCVTDQ2PSZrmbkz:
29568 case VCVTDQ2PSZrmk:
29569 case VCVTDQ2PSZrmkz:
29570 case VCVTDQ2PSZrr:
29571 case VCVTDQ2PSZrrb:
29572 case VCVTDQ2PSZrrbk:
29573 case VCVTDQ2PSZrrbkz:
29574 case VCVTDQ2PSZrrk:
29575 case VCVTDQ2PSZrrkz:
29576 case VCVTDQ2PSrm:
29577 case VCVTDQ2PSrr:
29578 return true;
29579 }
29580 return false;
29581}
29582
29583bool isPSUBD(unsigned Opcode) {
29584 switch (Opcode) {
29585 case MMX_PSUBDrm:
29586 case MMX_PSUBDrr:
29587 case PSUBDrm:
29588 case PSUBDrr:
29589 return true;
29590 }
29591 return false;
29592}
29593
29594bool isVPCMPEQW(unsigned Opcode) {
29595 switch (Opcode) {
29596 case VPCMPEQWYrm:
29597 case VPCMPEQWYrr:
29598 case VPCMPEQWZ128rm:
29599 case VPCMPEQWZ128rmk:
29600 case VPCMPEQWZ128rr:
29601 case VPCMPEQWZ128rrk:
29602 case VPCMPEQWZ256rm:
29603 case VPCMPEQWZ256rmk:
29604 case VPCMPEQWZ256rr:
29605 case VPCMPEQWZ256rrk:
29606 case VPCMPEQWZrm:
29607 case VPCMPEQWZrmk:
29608 case VPCMPEQWZrr:
29609 case VPCMPEQWZrrk:
29610 case VPCMPEQWrm:
29611 case VPCMPEQWrr:
29612 return true;
29613 }
29614 return false;
29615}
29616
29617bool isMOVSW(unsigned Opcode) {
29618 return Opcode == MOVSW;
29619}
29620
29621bool isVSM3RNDS2(unsigned Opcode) {
29622 switch (Opcode) {
29623 case VSM3RNDS2rmi:
29624 case VSM3RNDS2rri:
29625 return true;
29626 }
29627 return false;
29628}
29629
29630bool isVPMOVUSQD(unsigned Opcode) {
29631 switch (Opcode) {
29632 case VPMOVUSQDZ128mr:
29633 case VPMOVUSQDZ128mrk:
29634 case VPMOVUSQDZ128rr:
29635 case VPMOVUSQDZ128rrk:
29636 case VPMOVUSQDZ128rrkz:
29637 case VPMOVUSQDZ256mr:
29638 case VPMOVUSQDZ256mrk:
29639 case VPMOVUSQDZ256rr:
29640 case VPMOVUSQDZ256rrk:
29641 case VPMOVUSQDZ256rrkz:
29642 case VPMOVUSQDZmr:
29643 case VPMOVUSQDZmrk:
29644 case VPMOVUSQDZrr:
29645 case VPMOVUSQDZrrk:
29646 case VPMOVUSQDZrrkz:
29647 return true;
29648 }
29649 return false;
29650}
29651
29652bool isCVTTPD2DQ(unsigned Opcode) {
29653 switch (Opcode) {
29654 case CVTTPD2DQrm:
29655 case CVTTPD2DQrr:
29656 return true;
29657 }
29658 return false;
29659}
29660
29661bool isVPEXPANDW(unsigned Opcode) {
29662 switch (Opcode) {
29663 case VPEXPANDWZ128rm:
29664 case VPEXPANDWZ128rmk:
29665 case VPEXPANDWZ128rmkz:
29666 case VPEXPANDWZ128rr:
29667 case VPEXPANDWZ128rrk:
29668 case VPEXPANDWZ128rrkz:
29669 case VPEXPANDWZ256rm:
29670 case VPEXPANDWZ256rmk:
29671 case VPEXPANDWZ256rmkz:
29672 case VPEXPANDWZ256rr:
29673 case VPEXPANDWZ256rrk:
29674 case VPEXPANDWZ256rrkz:
29675 case VPEXPANDWZrm:
29676 case VPEXPANDWZrmk:
29677 case VPEXPANDWZrmkz:
29678 case VPEXPANDWZrr:
29679 case VPEXPANDWZrrk:
29680 case VPEXPANDWZrrkz:
29681 return true;
29682 }
29683 return false;
29684}
29685
29686bool isVUCOMISH(unsigned Opcode) {
29687 switch (Opcode) {
29688 case VUCOMISHZrm:
29689 case VUCOMISHZrr:
29690 case VUCOMISHZrrb:
29691 return true;
29692 }
29693 return false;
29694}
29695
29696bool isVZEROALL(unsigned Opcode) {
29697 return Opcode == VZEROALL;
29698}
29699
29700bool isVPAND(unsigned Opcode) {
29701 switch (Opcode) {
29702 case VPANDYrm:
29703 case VPANDYrr:
29704 case VPANDrm:
29705 case VPANDrr:
29706 return true;
29707 }
29708 return false;
29709}
29710
29711bool isPMULDQ(unsigned Opcode) {
29712 switch (Opcode) {
29713 case PMULDQrm:
29714 case PMULDQrr:
29715 return true;
29716 }
29717 return false;
29718}
29719
29720bool isVPSHUFHW(unsigned Opcode) {
29721 switch (Opcode) {
29722 case VPSHUFHWYmi:
29723 case VPSHUFHWYri:
29724 case VPSHUFHWZ128mi:
29725 case VPSHUFHWZ128mik:
29726 case VPSHUFHWZ128mikz:
29727 case VPSHUFHWZ128ri:
29728 case VPSHUFHWZ128rik:
29729 case VPSHUFHWZ128rikz:
29730 case VPSHUFHWZ256mi:
29731 case VPSHUFHWZ256mik:
29732 case VPSHUFHWZ256mikz:
29733 case VPSHUFHWZ256ri:
29734 case VPSHUFHWZ256rik:
29735 case VPSHUFHWZ256rikz:
29736 case VPSHUFHWZmi:
29737 case VPSHUFHWZmik:
29738 case VPSHUFHWZmikz:
29739 case VPSHUFHWZri:
29740 case VPSHUFHWZrik:
29741 case VPSHUFHWZrikz:
29742 case VPSHUFHWmi:
29743 case VPSHUFHWri:
29744 return true;
29745 }
29746 return false;
29747}
29748
29749bool isVPALIGNR(unsigned Opcode) {
29750 switch (Opcode) {
29751 case VPALIGNRYrmi:
29752 case VPALIGNRYrri:
29753 case VPALIGNRZ128rmi:
29754 case VPALIGNRZ128rmik:
29755 case VPALIGNRZ128rmikz:
29756 case VPALIGNRZ128rri:
29757 case VPALIGNRZ128rrik:
29758 case VPALIGNRZ128rrikz:
29759 case VPALIGNRZ256rmi:
29760 case VPALIGNRZ256rmik:
29761 case VPALIGNRZ256rmikz:
29762 case VPALIGNRZ256rri:
29763 case VPALIGNRZ256rrik:
29764 case VPALIGNRZ256rrikz:
29765 case VPALIGNRZrmi:
29766 case VPALIGNRZrmik:
29767 case VPALIGNRZrmikz:
29768 case VPALIGNRZrri:
29769 case VPALIGNRZrrik:
29770 case VPALIGNRZrrikz:
29771 case VPALIGNRrmi:
29772 case VPALIGNRrri:
29773 return true;
29774 }
29775 return false;
29776}
29777
29778bool isSQRTSD(unsigned Opcode) {
29779 switch (Opcode) {
29780 case SQRTSDm_Int:
29781 case SQRTSDr_Int:
29782 return true;
29783 }
29784 return false;
29785}
29786
29787bool isVCVTTPH2UDQ(unsigned Opcode) {
29788 switch (Opcode) {
29789 case VCVTTPH2UDQZ128rm:
29790 case VCVTTPH2UDQZ128rmb:
29791 case VCVTTPH2UDQZ128rmbk:
29792 case VCVTTPH2UDQZ128rmbkz:
29793 case VCVTTPH2UDQZ128rmk:
29794 case VCVTTPH2UDQZ128rmkz:
29795 case VCVTTPH2UDQZ128rr:
29796 case VCVTTPH2UDQZ128rrk:
29797 case VCVTTPH2UDQZ128rrkz:
29798 case VCVTTPH2UDQZ256rm:
29799 case VCVTTPH2UDQZ256rmb:
29800 case VCVTTPH2UDQZ256rmbk:
29801 case VCVTTPH2UDQZ256rmbkz:
29802 case VCVTTPH2UDQZ256rmk:
29803 case VCVTTPH2UDQZ256rmkz:
29804 case VCVTTPH2UDQZ256rr:
29805 case VCVTTPH2UDQZ256rrk:
29806 case VCVTTPH2UDQZ256rrkz:
29807 case VCVTTPH2UDQZrm:
29808 case VCVTTPH2UDQZrmb:
29809 case VCVTTPH2UDQZrmbk:
29810 case VCVTTPH2UDQZrmbkz:
29811 case VCVTTPH2UDQZrmk:
29812 case VCVTTPH2UDQZrmkz:
29813 case VCVTTPH2UDQZrr:
29814 case VCVTTPH2UDQZrrb:
29815 case VCVTTPH2UDQZrrbk:
29816 case VCVTTPH2UDQZrrbkz:
29817 case VCVTTPH2UDQZrrk:
29818 case VCVTTPH2UDQZrrkz:
29819 return true;
29820 }
29821 return false;
29822}
29823
29824bool isVGETEXPPH(unsigned Opcode) {
29825 switch (Opcode) {
29826 case VGETEXPPHZ128m:
29827 case VGETEXPPHZ128mb:
29828 case VGETEXPPHZ128mbk:
29829 case VGETEXPPHZ128mbkz:
29830 case VGETEXPPHZ128mk:
29831 case VGETEXPPHZ128mkz:
29832 case VGETEXPPHZ128r:
29833 case VGETEXPPHZ128rk:
29834 case VGETEXPPHZ128rkz:
29835 case VGETEXPPHZ256m:
29836 case VGETEXPPHZ256mb:
29837 case VGETEXPPHZ256mbk:
29838 case VGETEXPPHZ256mbkz:
29839 case VGETEXPPHZ256mk:
29840 case VGETEXPPHZ256mkz:
29841 case VGETEXPPHZ256r:
29842 case VGETEXPPHZ256rk:
29843 case VGETEXPPHZ256rkz:
29844 case VGETEXPPHZm:
29845 case VGETEXPPHZmb:
29846 case VGETEXPPHZmbk:
29847 case VGETEXPPHZmbkz:
29848 case VGETEXPPHZmk:
29849 case VGETEXPPHZmkz:
29850 case VGETEXPPHZr:
29851 case VGETEXPPHZrb:
29852 case VGETEXPPHZrbk:
29853 case VGETEXPPHZrbkz:
29854 case VGETEXPPHZrk:
29855 case VGETEXPPHZrkz:
29856 return true;
29857 }
29858 return false;
29859}
29860
29861bool isADDPD(unsigned Opcode) {
29862 switch (Opcode) {
29863 case ADDPDrm:
29864 case ADDPDrr:
29865 return true;
29866 }
29867 return false;
29868}
29869
29870bool isVFNMADDPD(unsigned Opcode) {
29871 switch (Opcode) {
29872 case VFNMADDPD4Ymr:
29873 case VFNMADDPD4Yrm:
29874 case VFNMADDPD4Yrr:
29875 case VFNMADDPD4Yrr_REV:
29876 case VFNMADDPD4mr:
29877 case VFNMADDPD4rm:
29878 case VFNMADDPD4rr:
29879 case VFNMADDPD4rr_REV:
29880 return true;
29881 }
29882 return false;
29883}
29884
29885bool isSTTILECFG(unsigned Opcode) {
29886 switch (Opcode) {
29887 case STTILECFG:
29888 case STTILECFG_EVEX:
29889 return true;
29890 }
29891 return false;
29892}
29893
29894bool isVMINPD(unsigned Opcode) {
29895 switch (Opcode) {
29896 case VMINPDYrm:
29897 case VMINPDYrr:
29898 case VMINPDZ128rm:
29899 case VMINPDZ128rmb:
29900 case VMINPDZ128rmbk:
29901 case VMINPDZ128rmbkz:
29902 case VMINPDZ128rmk:
29903 case VMINPDZ128rmkz:
29904 case VMINPDZ128rr:
29905 case VMINPDZ128rrk:
29906 case VMINPDZ128rrkz:
29907 case VMINPDZ256rm:
29908 case VMINPDZ256rmb:
29909 case VMINPDZ256rmbk:
29910 case VMINPDZ256rmbkz:
29911 case VMINPDZ256rmk:
29912 case VMINPDZ256rmkz:
29913 case VMINPDZ256rr:
29914 case VMINPDZ256rrk:
29915 case VMINPDZ256rrkz:
29916 case VMINPDZrm:
29917 case VMINPDZrmb:
29918 case VMINPDZrmbk:
29919 case VMINPDZrmbkz:
29920 case VMINPDZrmk:
29921 case VMINPDZrmkz:
29922 case VMINPDZrr:
29923 case VMINPDZrrb:
29924 case VMINPDZrrbk:
29925 case VMINPDZrrbkz:
29926 case VMINPDZrrk:
29927 case VMINPDZrrkz:
29928 case VMINPDrm:
29929 case VMINPDrr:
29930 return true;
29931 }
29932 return false;
29933}
29934
29935bool isSHA1RNDS4(unsigned Opcode) {
29936 switch (Opcode) {
29937 case SHA1RNDS4rmi:
29938 case SHA1RNDS4rri:
29939 return true;
29940 }
29941 return false;
29942}
29943
29944bool isPBLENDVB(unsigned Opcode) {
29945 switch (Opcode) {
29946 case PBLENDVBrm0:
29947 case PBLENDVBrr0:
29948 return true;
29949 }
29950 return false;
29951}
29952
29953bool isVBROADCASTF128(unsigned Opcode) {
29954 return Opcode == VBROADCASTF128rm;
29955}
29956
29957bool isVPSHRDQ(unsigned Opcode) {
29958 switch (Opcode) {
29959 case VPSHRDQZ128rmbi:
29960 case VPSHRDQZ128rmbik:
29961 case VPSHRDQZ128rmbikz:
29962 case VPSHRDQZ128rmi:
29963 case VPSHRDQZ128rmik:
29964 case VPSHRDQZ128rmikz:
29965 case VPSHRDQZ128rri:
29966 case VPSHRDQZ128rrik:
29967 case VPSHRDQZ128rrikz:
29968 case VPSHRDQZ256rmbi:
29969 case VPSHRDQZ256rmbik:
29970 case VPSHRDQZ256rmbikz:
29971 case VPSHRDQZ256rmi:
29972 case VPSHRDQZ256rmik:
29973 case VPSHRDQZ256rmikz:
29974 case VPSHRDQZ256rri:
29975 case VPSHRDQZ256rrik:
29976 case VPSHRDQZ256rrikz:
29977 case VPSHRDQZrmbi:
29978 case VPSHRDQZrmbik:
29979 case VPSHRDQZrmbikz:
29980 case VPSHRDQZrmi:
29981 case VPSHRDQZrmik:
29982 case VPSHRDQZrmikz:
29983 case VPSHRDQZrri:
29984 case VPSHRDQZrrik:
29985 case VPSHRDQZrrikz:
29986 return true;
29987 }
29988 return false;
29989}
29990
29991bool isVAESIMC(unsigned Opcode) {
29992 switch (Opcode) {
29993 case VAESIMCrm:
29994 case VAESIMCrr:
29995 return true;
29996 }
29997 return false;
29998}
29999
30000bool isCOMISD(unsigned Opcode) {
30001 switch (Opcode) {
30002 case COMISDrm:
30003 case COMISDrr:
30004 return true;
30005 }
30006 return false;
30007}
30008
30009bool isVMOVSH(unsigned Opcode) {
30010 switch (Opcode) {
30011 case VMOVSHZmr:
30012 case VMOVSHZmrk:
30013 case VMOVSHZrm:
30014 case VMOVSHZrmk:
30015 case VMOVSHZrmkz:
30016 case VMOVSHZrr:
30017 case VMOVSHZrr_REV:
30018 case VMOVSHZrrk:
30019 case VMOVSHZrrk_REV:
30020 case VMOVSHZrrkz:
30021 case VMOVSHZrrkz_REV:
30022 return true;
30023 }
30024 return false;
30025}
30026
30027bool isPFSUBR(unsigned Opcode) {
30028 switch (Opcode) {
30029 case PFSUBRrm:
30030 case PFSUBRrr:
30031 return true;
30032 }
30033 return false;
30034}
30035
30036bool isRDSSPD(unsigned Opcode) {
30037 return Opcode == RDSSPD;
30038}
30039
30040bool isWAIT(unsigned Opcode) {
30041 return Opcode == WAIT;
30042}
30043
30044bool isVFPCLASSSS(unsigned Opcode) {
30045 switch (Opcode) {
30046 case VFPCLASSSSZmi:
30047 case VFPCLASSSSZmik:
30048 case VFPCLASSSSZri:
30049 case VFPCLASSSSZrik:
30050 return true;
30051 }
30052 return false;
30053}
30054
30055bool isPCMPGTD(unsigned Opcode) {
30056 switch (Opcode) {
30057 case MMX_PCMPGTDrm:
30058 case MMX_PCMPGTDrr:
30059 case PCMPGTDrm:
30060 case PCMPGTDrr:
30061 return true;
30062 }
30063 return false;
30064}
30065
30066bool isVGATHERPF0QPS(unsigned Opcode) {
30067 return Opcode == VGATHERPF0QPSm;
30068}
30069
30070bool isBLENDVPS(unsigned Opcode) {
30071 switch (Opcode) {
30072 case BLENDVPSrm0:
30073 case BLENDVPSrr0:
30074 return true;
30075 }
30076 return false;
30077}
30078
30079bool isVBROADCASTF32X4(unsigned Opcode) {
30080 switch (Opcode) {
30081 case VBROADCASTF32X4Z256rm:
30082 case VBROADCASTF32X4Z256rmk:
30083 case VBROADCASTF32X4Z256rmkz:
30084 case VBROADCASTF32X4Zrm:
30085 case VBROADCASTF32X4Zrmk:
30086 case VBROADCASTF32X4Zrmkz:
30087 return true;
30088 }
30089 return false;
30090}
30091
30092bool isVMOVLPD(unsigned Opcode) {
30093 switch (Opcode) {
30094 case VMOVLPDZ128mr:
30095 case VMOVLPDZ128rm:
30096 case VMOVLPDmr:
30097 case VMOVLPDrm:
30098 return true;
30099 }
30100 return false;
30101}
30102
30103bool isVMOVQ(unsigned Opcode) {
30104 switch (Opcode) {
30105 case VMOV64toPQIZrm:
30106 case VMOV64toPQIZrr:
30107 case VMOV64toPQIrm:
30108 case VMOV64toPQIrr:
30109 case VMOVPQI2QIZmr:
30110 case VMOVPQI2QIZrr:
30111 case VMOVPQI2QImr:
30112 case VMOVPQI2QIrr:
30113 case VMOVPQIto64Zmr:
30114 case VMOVPQIto64Zrr:
30115 case VMOVPQIto64mr:
30116 case VMOVPQIto64rr:
30117 case VMOVQI2PQIZrm:
30118 case VMOVQI2PQIrm:
30119 case VMOVZPQILo2PQIZrr:
30120 case VMOVZPQILo2PQIrr:
30121 return true;
30122 }
30123 return false;
30124}
30125
30126bool isVPMADD52LUQ(unsigned Opcode) {
30127 switch (Opcode) {
30128 case VPMADD52LUQYrm:
30129 case VPMADD52LUQYrr:
30130 case VPMADD52LUQZ128m:
30131 case VPMADD52LUQZ128mb:
30132 case VPMADD52LUQZ128mbk:
30133 case VPMADD52LUQZ128mbkz:
30134 case VPMADD52LUQZ128mk:
30135 case VPMADD52LUQZ128mkz:
30136 case VPMADD52LUQZ128r:
30137 case VPMADD52LUQZ128rk:
30138 case VPMADD52LUQZ128rkz:
30139 case VPMADD52LUQZ256m:
30140 case VPMADD52LUQZ256mb:
30141 case VPMADD52LUQZ256mbk:
30142 case VPMADD52LUQZ256mbkz:
30143 case VPMADD52LUQZ256mk:
30144 case VPMADD52LUQZ256mkz:
30145 case VPMADD52LUQZ256r:
30146 case VPMADD52LUQZ256rk:
30147 case VPMADD52LUQZ256rkz:
30148 case VPMADD52LUQZm:
30149 case VPMADD52LUQZmb:
30150 case VPMADD52LUQZmbk:
30151 case VPMADD52LUQZmbkz:
30152 case VPMADD52LUQZmk:
30153 case VPMADD52LUQZmkz:
30154 case VPMADD52LUQZr:
30155 case VPMADD52LUQZrk:
30156 case VPMADD52LUQZrkz:
30157 case VPMADD52LUQrm:
30158 case VPMADD52LUQrr:
30159 return true;
30160 }
30161 return false;
30162}
30163
30164bool isVMOVDQU(unsigned Opcode) {
30165 switch (Opcode) {
30166 case VMOVDQUYmr:
30167 case VMOVDQUYrm:
30168 case VMOVDQUYrr:
30169 case VMOVDQUYrr_REV:
30170 case VMOVDQUmr:
30171 case VMOVDQUrm:
30172 case VMOVDQUrr:
30173 case VMOVDQUrr_REV:
30174 return true;
30175 }
30176 return false;
30177}
30178
30179bool isAESENC128KL(unsigned Opcode) {
30180 return Opcode == AESENC128KL;
30181}
30182
30183bool isVFMADDSUB231PS(unsigned Opcode) {
30184 switch (Opcode) {
30185 case VFMADDSUB231PSYm:
30186 case VFMADDSUB231PSYr:
30187 case VFMADDSUB231PSZ128m:
30188 case VFMADDSUB231PSZ128mb:
30189 case VFMADDSUB231PSZ128mbk:
30190 case VFMADDSUB231PSZ128mbkz:
30191 case VFMADDSUB231PSZ128mk:
30192 case VFMADDSUB231PSZ128mkz:
30193 case VFMADDSUB231PSZ128r:
30194 case VFMADDSUB231PSZ128rk:
30195 case VFMADDSUB231PSZ128rkz:
30196 case VFMADDSUB231PSZ256m:
30197 case VFMADDSUB231PSZ256mb:
30198 case VFMADDSUB231PSZ256mbk:
30199 case VFMADDSUB231PSZ256mbkz:
30200 case VFMADDSUB231PSZ256mk:
30201 case VFMADDSUB231PSZ256mkz:
30202 case VFMADDSUB231PSZ256r:
30203 case VFMADDSUB231PSZ256rk:
30204 case VFMADDSUB231PSZ256rkz:
30205 case VFMADDSUB231PSZm:
30206 case VFMADDSUB231PSZmb:
30207 case VFMADDSUB231PSZmbk:
30208 case VFMADDSUB231PSZmbkz:
30209 case VFMADDSUB231PSZmk:
30210 case VFMADDSUB231PSZmkz:
30211 case VFMADDSUB231PSZr:
30212 case VFMADDSUB231PSZrb:
30213 case VFMADDSUB231PSZrbk:
30214 case VFMADDSUB231PSZrbkz:
30215 case VFMADDSUB231PSZrk:
30216 case VFMADDSUB231PSZrkz:
30217 case VFMADDSUB231PSm:
30218 case VFMADDSUB231PSr:
30219 return true;
30220 }
30221 return false;
30222}
30223
30224bool isVFNMSUB213PD(unsigned Opcode) {
30225 switch (Opcode) {
30226 case VFNMSUB213PDYm:
30227 case VFNMSUB213PDYr:
30228 case VFNMSUB213PDZ128m:
30229 case VFNMSUB213PDZ128mb:
30230 case VFNMSUB213PDZ128mbk:
30231 case VFNMSUB213PDZ128mbkz:
30232 case VFNMSUB213PDZ128mk:
30233 case VFNMSUB213PDZ128mkz:
30234 case VFNMSUB213PDZ128r:
30235 case VFNMSUB213PDZ128rk:
30236 case VFNMSUB213PDZ128rkz:
30237 case VFNMSUB213PDZ256m:
30238 case VFNMSUB213PDZ256mb:
30239 case VFNMSUB213PDZ256mbk:
30240 case VFNMSUB213PDZ256mbkz:
30241 case VFNMSUB213PDZ256mk:
30242 case VFNMSUB213PDZ256mkz:
30243 case VFNMSUB213PDZ256r:
30244 case VFNMSUB213PDZ256rk:
30245 case VFNMSUB213PDZ256rkz:
30246 case VFNMSUB213PDZm:
30247 case VFNMSUB213PDZmb:
30248 case VFNMSUB213PDZmbk:
30249 case VFNMSUB213PDZmbkz:
30250 case VFNMSUB213PDZmk:
30251 case VFNMSUB213PDZmkz:
30252 case VFNMSUB213PDZr:
30253 case VFNMSUB213PDZrb:
30254 case VFNMSUB213PDZrbk:
30255 case VFNMSUB213PDZrbkz:
30256 case VFNMSUB213PDZrk:
30257 case VFNMSUB213PDZrkz:
30258 case VFNMSUB213PDm:
30259 case VFNMSUB213PDr:
30260 return true;
30261 }
30262 return false;
30263}
30264
30265bool isVPCONFLICTD(unsigned Opcode) {
30266 switch (Opcode) {
30267 case VPCONFLICTDZ128rm:
30268 case VPCONFLICTDZ128rmb:
30269 case VPCONFLICTDZ128rmbk:
30270 case VPCONFLICTDZ128rmbkz:
30271 case VPCONFLICTDZ128rmk:
30272 case VPCONFLICTDZ128rmkz:
30273 case VPCONFLICTDZ128rr:
30274 case VPCONFLICTDZ128rrk:
30275 case VPCONFLICTDZ128rrkz:
30276 case VPCONFLICTDZ256rm:
30277 case VPCONFLICTDZ256rmb:
30278 case VPCONFLICTDZ256rmbk:
30279 case VPCONFLICTDZ256rmbkz:
30280 case VPCONFLICTDZ256rmk:
30281 case VPCONFLICTDZ256rmkz:
30282 case VPCONFLICTDZ256rr:
30283 case VPCONFLICTDZ256rrk:
30284 case VPCONFLICTDZ256rrkz:
30285 case VPCONFLICTDZrm:
30286 case VPCONFLICTDZrmb:
30287 case VPCONFLICTDZrmbk:
30288 case VPCONFLICTDZrmbkz:
30289 case VPCONFLICTDZrmk:
30290 case VPCONFLICTDZrmkz:
30291 case VPCONFLICTDZrr:
30292 case VPCONFLICTDZrrk:
30293 case VPCONFLICTDZrrkz:
30294 return true;
30295 }
30296 return false;
30297}
30298
30299bool isVFMADDSUB213PH(unsigned Opcode) {
30300 switch (Opcode) {
30301 case VFMADDSUB213PHZ128m:
30302 case VFMADDSUB213PHZ128mb:
30303 case VFMADDSUB213PHZ128mbk:
30304 case VFMADDSUB213PHZ128mbkz:
30305 case VFMADDSUB213PHZ128mk:
30306 case VFMADDSUB213PHZ128mkz:
30307 case VFMADDSUB213PHZ128r:
30308 case VFMADDSUB213PHZ128rk:
30309 case VFMADDSUB213PHZ128rkz:
30310 case VFMADDSUB213PHZ256m:
30311 case VFMADDSUB213PHZ256mb:
30312 case VFMADDSUB213PHZ256mbk:
30313 case VFMADDSUB213PHZ256mbkz:
30314 case VFMADDSUB213PHZ256mk:
30315 case VFMADDSUB213PHZ256mkz:
30316 case VFMADDSUB213PHZ256r:
30317 case VFMADDSUB213PHZ256rk:
30318 case VFMADDSUB213PHZ256rkz:
30319 case VFMADDSUB213PHZm:
30320 case VFMADDSUB213PHZmb:
30321 case VFMADDSUB213PHZmbk:
30322 case VFMADDSUB213PHZmbkz:
30323 case VFMADDSUB213PHZmk:
30324 case VFMADDSUB213PHZmkz:
30325 case VFMADDSUB213PHZr:
30326 case VFMADDSUB213PHZrb:
30327 case VFMADDSUB213PHZrbk:
30328 case VFMADDSUB213PHZrbkz:
30329 case VFMADDSUB213PHZrk:
30330 case VFMADDSUB213PHZrkz:
30331 return true;
30332 }
30333 return false;
30334}
30335
30336bool isVPHSUBSW(unsigned Opcode) {
30337 switch (Opcode) {
30338 case VPHSUBSWYrm:
30339 case VPHSUBSWYrr:
30340 case VPHSUBSWrm:
30341 case VPHSUBSWrr:
30342 return true;
30343 }
30344 return false;
30345}
30346
30347bool isPUNPCKHDQ(unsigned Opcode) {
30348 switch (Opcode) {
30349 case MMX_PUNPCKHDQrm:
30350 case MMX_PUNPCKHDQrr:
30351 case PUNPCKHDQrm:
30352 case PUNPCKHDQrr:
30353 return true;
30354 }
30355 return false;
30356}
30357
30358bool isVSHUFI64X2(unsigned Opcode) {
30359 switch (Opcode) {
30360 case VSHUFI64X2Z256rmbi:
30361 case VSHUFI64X2Z256rmbik:
30362 case VSHUFI64X2Z256rmbikz:
30363 case VSHUFI64X2Z256rmi:
30364 case VSHUFI64X2Z256rmik:
30365 case VSHUFI64X2Z256rmikz:
30366 case VSHUFI64X2Z256rri:
30367 case VSHUFI64X2Z256rrik:
30368 case VSHUFI64X2Z256rrikz:
30369 case VSHUFI64X2Zrmbi:
30370 case VSHUFI64X2Zrmbik:
30371 case VSHUFI64X2Zrmbikz:
30372 case VSHUFI64X2Zrmi:
30373 case VSHUFI64X2Zrmik:
30374 case VSHUFI64X2Zrmikz:
30375 case VSHUFI64X2Zrri:
30376 case VSHUFI64X2Zrrik:
30377 case VSHUFI64X2Zrrikz:
30378 return true;
30379 }
30380 return false;
30381}
30382
30383bool isVFMSUBSD(unsigned Opcode) {
30384 switch (Opcode) {
30385 case VFMSUBSD4mr:
30386 case VFMSUBSD4rm:
30387 case VFMSUBSD4rr:
30388 case VFMSUBSD4rr_REV:
30389 return true;
30390 }
30391 return false;
30392}
30393
30394bool isVPORD(unsigned Opcode) {
30395 switch (Opcode) {
30396 case VPORDZ128rm:
30397 case VPORDZ128rmb:
30398 case VPORDZ128rmbk:
30399 case VPORDZ128rmbkz:
30400 case VPORDZ128rmk:
30401 case VPORDZ128rmkz:
30402 case VPORDZ128rr:
30403 case VPORDZ128rrk:
30404 case VPORDZ128rrkz:
30405 case VPORDZ256rm:
30406 case VPORDZ256rmb:
30407 case VPORDZ256rmbk:
30408 case VPORDZ256rmbkz:
30409 case VPORDZ256rmk:
30410 case VPORDZ256rmkz:
30411 case VPORDZ256rr:
30412 case VPORDZ256rrk:
30413 case VPORDZ256rrkz:
30414 case VPORDZrm:
30415 case VPORDZrmb:
30416 case VPORDZrmbk:
30417 case VPORDZrmbkz:
30418 case VPORDZrmk:
30419 case VPORDZrmkz:
30420 case VPORDZrr:
30421 case VPORDZrrk:
30422 case VPORDZrrkz:
30423 return true;
30424 }
30425 return false;
30426}
30427
30428bool isRCPPS(unsigned Opcode) {
30429 switch (Opcode) {
30430 case RCPPSm:
30431 case RCPPSr:
30432 return true;
30433 }
30434 return false;
30435}
30436
30437bool isVEXTRACTI128(unsigned Opcode) {
30438 switch (Opcode) {
30439 case VEXTRACTI128mri:
30440 case VEXTRACTI128rri:
30441 return true;
30442 }
30443 return false;
30444}
30445
30446bool isVCVT2PH2BF8S(unsigned Opcode) {
30447 switch (Opcode) {
30448 case VCVT2PH2BF8SZ128rm:
30449 case VCVT2PH2BF8SZ128rmb:
30450 case VCVT2PH2BF8SZ128rmbk:
30451 case VCVT2PH2BF8SZ128rmbkz:
30452 case VCVT2PH2BF8SZ128rmk:
30453 case VCVT2PH2BF8SZ128rmkz:
30454 case VCVT2PH2BF8SZ128rr:
30455 case VCVT2PH2BF8SZ128rrk:
30456 case VCVT2PH2BF8SZ128rrkz:
30457 case VCVT2PH2BF8SZ256rm:
30458 case VCVT2PH2BF8SZ256rmb:
30459 case VCVT2PH2BF8SZ256rmbk:
30460 case VCVT2PH2BF8SZ256rmbkz:
30461 case VCVT2PH2BF8SZ256rmk:
30462 case VCVT2PH2BF8SZ256rmkz:
30463 case VCVT2PH2BF8SZ256rr:
30464 case VCVT2PH2BF8SZ256rrk:
30465 case VCVT2PH2BF8SZ256rrkz:
30466 case VCVT2PH2BF8SZrm:
30467 case VCVT2PH2BF8SZrmb:
30468 case VCVT2PH2BF8SZrmbk:
30469 case VCVT2PH2BF8SZrmbkz:
30470 case VCVT2PH2BF8SZrmk:
30471 case VCVT2PH2BF8SZrmkz:
30472 case VCVT2PH2BF8SZrr:
30473 case VCVT2PH2BF8SZrrk:
30474 case VCVT2PH2BF8SZrrkz:
30475 return true;
30476 }
30477 return false;
30478}
30479
30480bool isVPSHRDVW(unsigned Opcode) {
30481 switch (Opcode) {
30482 case VPSHRDVWZ128m:
30483 case VPSHRDVWZ128mk:
30484 case VPSHRDVWZ128mkz:
30485 case VPSHRDVWZ128r:
30486 case VPSHRDVWZ128rk:
30487 case VPSHRDVWZ128rkz:
30488 case VPSHRDVWZ256m:
30489 case VPSHRDVWZ256mk:
30490 case VPSHRDVWZ256mkz:
30491 case VPSHRDVWZ256r:
30492 case VPSHRDVWZ256rk:
30493 case VPSHRDVWZ256rkz:
30494 case VPSHRDVWZm:
30495 case VPSHRDVWZmk:
30496 case VPSHRDVWZmkz:
30497 case VPSHRDVWZr:
30498 case VPSHRDVWZrk:
30499 case VPSHRDVWZrkz:
30500 return true;
30501 }
30502 return false;
30503}
30504
30505bool isVUNPCKLPD(unsigned Opcode) {
30506 switch (Opcode) {
30507 case VUNPCKLPDYrm:
30508 case VUNPCKLPDYrr:
30509 case VUNPCKLPDZ128rm:
30510 case VUNPCKLPDZ128rmb:
30511 case VUNPCKLPDZ128rmbk:
30512 case VUNPCKLPDZ128rmbkz:
30513 case VUNPCKLPDZ128rmk:
30514 case VUNPCKLPDZ128rmkz:
30515 case VUNPCKLPDZ128rr:
30516 case VUNPCKLPDZ128rrk:
30517 case VUNPCKLPDZ128rrkz:
30518 case VUNPCKLPDZ256rm:
30519 case VUNPCKLPDZ256rmb:
30520 case VUNPCKLPDZ256rmbk:
30521 case VUNPCKLPDZ256rmbkz:
30522 case VUNPCKLPDZ256rmk:
30523 case VUNPCKLPDZ256rmkz:
30524 case VUNPCKLPDZ256rr:
30525 case VUNPCKLPDZ256rrk:
30526 case VUNPCKLPDZ256rrkz:
30527 case VUNPCKLPDZrm:
30528 case VUNPCKLPDZrmb:
30529 case VUNPCKLPDZrmbk:
30530 case VUNPCKLPDZrmbkz:
30531 case VUNPCKLPDZrmk:
30532 case VUNPCKLPDZrmkz:
30533 case VUNPCKLPDZrr:
30534 case VUNPCKLPDZrrk:
30535 case VUNPCKLPDZrrkz:
30536 case VUNPCKLPDrm:
30537 case VUNPCKLPDrr:
30538 return true;
30539 }
30540 return false;
30541}
30542
30543bool isVPSRAVD(unsigned Opcode) {
30544 switch (Opcode) {
30545 case VPSRAVDYrm:
30546 case VPSRAVDYrr:
30547 case VPSRAVDZ128rm:
30548 case VPSRAVDZ128rmb:
30549 case VPSRAVDZ128rmbk:
30550 case VPSRAVDZ128rmbkz:
30551 case VPSRAVDZ128rmk:
30552 case VPSRAVDZ128rmkz:
30553 case VPSRAVDZ128rr:
30554 case VPSRAVDZ128rrk:
30555 case VPSRAVDZ128rrkz:
30556 case VPSRAVDZ256rm:
30557 case VPSRAVDZ256rmb:
30558 case VPSRAVDZ256rmbk:
30559 case VPSRAVDZ256rmbkz:
30560 case VPSRAVDZ256rmk:
30561 case VPSRAVDZ256rmkz:
30562 case VPSRAVDZ256rr:
30563 case VPSRAVDZ256rrk:
30564 case VPSRAVDZ256rrkz:
30565 case VPSRAVDZrm:
30566 case VPSRAVDZrmb:
30567 case VPSRAVDZrmbk:
30568 case VPSRAVDZrmbkz:
30569 case VPSRAVDZrmk:
30570 case VPSRAVDZrmkz:
30571 case VPSRAVDZrr:
30572 case VPSRAVDZrrk:
30573 case VPSRAVDZrrkz:
30574 case VPSRAVDrm:
30575 case VPSRAVDrr:
30576 return true;
30577 }
30578 return false;
30579}
30580
30581bool isVMULSH(unsigned Opcode) {
30582 switch (Opcode) {
30583 case VMULSHZrm_Int:
30584 case VMULSHZrmk_Int:
30585 case VMULSHZrmkz_Int:
30586 case VMULSHZrr_Int:
30587 case VMULSHZrrb_Int:
30588 case VMULSHZrrbk_Int:
30589 case VMULSHZrrbkz_Int:
30590 case VMULSHZrrk_Int:
30591 case VMULSHZrrkz_Int:
30592 return true;
30593 }
30594 return false;
30595}
30596
30597bool isMOVNTSS(unsigned Opcode) {
30598 return Opcode == MOVNTSS;
30599}
30600
30601bool isSTI(unsigned Opcode) {
30602 return Opcode == STI;
30603}
30604
30605bool isVSM4RNDS4(unsigned Opcode) {
30606 switch (Opcode) {
30607 case VSM4RNDS4Yrm:
30608 case VSM4RNDS4Yrr:
30609 case VSM4RNDS4Z128rm:
30610 case VSM4RNDS4Z128rr:
30611 case VSM4RNDS4Z256rm:
30612 case VSM4RNDS4Z256rr:
30613 case VSM4RNDS4Zrm:
30614 case VSM4RNDS4Zrr:
30615 case VSM4RNDS4rm:
30616 case VSM4RNDS4rr:
30617 return true;
30618 }
30619 return false;
30620}
30621
30622bool isVMCLEAR(unsigned Opcode) {
30623 return Opcode == VMCLEARm;
30624}
30625
30626bool isVPMADD52HUQ(unsigned Opcode) {
30627 switch (Opcode) {
30628 case VPMADD52HUQYrm:
30629 case VPMADD52HUQYrr:
30630 case VPMADD52HUQZ128m:
30631 case VPMADD52HUQZ128mb:
30632 case VPMADD52HUQZ128mbk:
30633 case VPMADD52HUQZ128mbkz:
30634 case VPMADD52HUQZ128mk:
30635 case VPMADD52HUQZ128mkz:
30636 case VPMADD52HUQZ128r:
30637 case VPMADD52HUQZ128rk:
30638 case VPMADD52HUQZ128rkz:
30639 case VPMADD52HUQZ256m:
30640 case VPMADD52HUQZ256mb:
30641 case VPMADD52HUQZ256mbk:
30642 case VPMADD52HUQZ256mbkz:
30643 case VPMADD52HUQZ256mk:
30644 case VPMADD52HUQZ256mkz:
30645 case VPMADD52HUQZ256r:
30646 case VPMADD52HUQZ256rk:
30647 case VPMADD52HUQZ256rkz:
30648 case VPMADD52HUQZm:
30649 case VPMADD52HUQZmb:
30650 case VPMADD52HUQZmbk:
30651 case VPMADD52HUQZmbkz:
30652 case VPMADD52HUQZmk:
30653 case VPMADD52HUQZmkz:
30654 case VPMADD52HUQZr:
30655 case VPMADD52HUQZrk:
30656 case VPMADD52HUQZrkz:
30657 case VPMADD52HUQrm:
30658 case VPMADD52HUQrr:
30659 return true;
30660 }
30661 return false;
30662}
30663
30664bool isLIDT(unsigned Opcode) {
30665 return Opcode == LIDT64m;
30666}
30667
30668bool isPUSH2(unsigned Opcode) {
30669 return Opcode == PUSH2;
30670}
30671
30672bool isRDPKRU(unsigned Opcode) {
30673 return Opcode == RDPKRUr;
30674}
30675
30676bool isVCVTPS2IUBS(unsigned Opcode) {
30677 switch (Opcode) {
30678 case VCVTPS2IUBSZ128rm:
30679 case VCVTPS2IUBSZ128rmb:
30680 case VCVTPS2IUBSZ128rmbk:
30681 case VCVTPS2IUBSZ128rmbkz:
30682 case VCVTPS2IUBSZ128rmk:
30683 case VCVTPS2IUBSZ128rmkz:
30684 case VCVTPS2IUBSZ128rr:
30685 case VCVTPS2IUBSZ128rrk:
30686 case VCVTPS2IUBSZ128rrkz:
30687 case VCVTPS2IUBSZ256rm:
30688 case VCVTPS2IUBSZ256rmb:
30689 case VCVTPS2IUBSZ256rmbk:
30690 case VCVTPS2IUBSZ256rmbkz:
30691 case VCVTPS2IUBSZ256rmk:
30692 case VCVTPS2IUBSZ256rmkz:
30693 case VCVTPS2IUBSZ256rr:
30694 case VCVTPS2IUBSZ256rrk:
30695 case VCVTPS2IUBSZ256rrkz:
30696 case VCVTPS2IUBSZrm:
30697 case VCVTPS2IUBSZrmb:
30698 case VCVTPS2IUBSZrmbk:
30699 case VCVTPS2IUBSZrmbkz:
30700 case VCVTPS2IUBSZrmk:
30701 case VCVTPS2IUBSZrmkz:
30702 case VCVTPS2IUBSZrr:
30703 case VCVTPS2IUBSZrrb:
30704 case VCVTPS2IUBSZrrbk:
30705 case VCVTPS2IUBSZrrbkz:
30706 case VCVTPS2IUBSZrrk:
30707 case VCVTPS2IUBSZrrkz:
30708 return true;
30709 }
30710 return false;
30711}
30712
30713bool isXSAVES64(unsigned Opcode) {
30714 return Opcode == XSAVES64;
30715}
30716
30717bool isVPCMPB(unsigned Opcode) {
30718 switch (Opcode) {
30719 case VPCMPBZ128rmi:
30720 case VPCMPBZ128rmik:
30721 case VPCMPBZ128rri:
30722 case VPCMPBZ128rrik:
30723 case VPCMPBZ256rmi:
30724 case VPCMPBZ256rmik:
30725 case VPCMPBZ256rri:
30726 case VPCMPBZ256rrik:
30727 case VPCMPBZrmi:
30728 case VPCMPBZrmik:
30729 case VPCMPBZrri:
30730 case VPCMPBZrrik:
30731 return true;
30732 }
30733 return false;
30734}
30735
30736bool isVFMSUB231BF16(unsigned Opcode) {
30737 switch (Opcode) {
30738 case VFMSUB231BF16Z128m:
30739 case VFMSUB231BF16Z128mb:
30740 case VFMSUB231BF16Z128mbk:
30741 case VFMSUB231BF16Z128mbkz:
30742 case VFMSUB231BF16Z128mk:
30743 case VFMSUB231BF16Z128mkz:
30744 case VFMSUB231BF16Z128r:
30745 case VFMSUB231BF16Z128rk:
30746 case VFMSUB231BF16Z128rkz:
30747 case VFMSUB231BF16Z256m:
30748 case VFMSUB231BF16Z256mb:
30749 case VFMSUB231BF16Z256mbk:
30750 case VFMSUB231BF16Z256mbkz:
30751 case VFMSUB231BF16Z256mk:
30752 case VFMSUB231BF16Z256mkz:
30753 case VFMSUB231BF16Z256r:
30754 case VFMSUB231BF16Z256rk:
30755 case VFMSUB231BF16Z256rkz:
30756 case VFMSUB231BF16Zm:
30757 case VFMSUB231BF16Zmb:
30758 case VFMSUB231BF16Zmbk:
30759 case VFMSUB231BF16Zmbkz:
30760 case VFMSUB231BF16Zmk:
30761 case VFMSUB231BF16Zmkz:
30762 case VFMSUB231BF16Zr:
30763 case VFMSUB231BF16Zrk:
30764 case VFMSUB231BF16Zrkz:
30765 return true;
30766 }
30767 return false;
30768}
30769
30770bool isFINCSTP(unsigned Opcode) {
30771 return Opcode == FINCSTP;
30772}
30773
30774bool isKORQ(unsigned Opcode) {
30775 return Opcode == KORQkk;
30776}
30777
30778bool isRDPMC(unsigned Opcode) {
30779 return Opcode == RDPMC;
30780}
30781
30782bool isVEXTRACTF128(unsigned Opcode) {
30783 switch (Opcode) {
30784 case VEXTRACTF128mri:
30785 case VEXTRACTF128rri:
30786 return true;
30787 }
30788 return false;
30789}
30790
30791bool isMOVMSKPD(unsigned Opcode) {
30792 return Opcode == MOVMSKPDrr;
30793}
30794
30795bool isVFMSUB231SH(unsigned Opcode) {
30796 switch (Opcode) {
30797 case VFMSUB231SHZm_Int:
30798 case VFMSUB231SHZmk_Int:
30799 case VFMSUB231SHZmkz_Int:
30800 case VFMSUB231SHZr_Int:
30801 case VFMSUB231SHZrb_Int:
30802 case VFMSUB231SHZrbk_Int:
30803 case VFMSUB231SHZrbkz_Int:
30804 case VFMSUB231SHZrk_Int:
30805 case VFMSUB231SHZrkz_Int:
30806 return true;
30807 }
30808 return false;
30809}
30810
30811bool isVPSHLB(unsigned Opcode) {
30812 switch (Opcode) {
30813 case VPSHLBmr:
30814 case VPSHLBrm:
30815 case VPSHLBrr:
30816 case VPSHLBrr_REV:
30817 return true;
30818 }
30819 return false;
30820}
30821
30822bool isXCRYPTCBC(unsigned Opcode) {
30823 return Opcode == XCRYPTCBC;
30824}
30825
30826bool isSHL(unsigned Opcode) {
30827 switch (Opcode) {
30828 case SHL16m1:
30829 case SHL16m1_EVEX:
30830 case SHL16m1_ND:
30831 case SHL16m1_NF:
30832 case SHL16m1_NF_ND:
30833 case SHL16mCL:
30834 case SHL16mCL_EVEX:
30835 case SHL16mCL_ND:
30836 case SHL16mCL_NF:
30837 case SHL16mCL_NF_ND:
30838 case SHL16mi:
30839 case SHL16mi_EVEX:
30840 case SHL16mi_ND:
30841 case SHL16mi_NF:
30842 case SHL16mi_NF_ND:
30843 case SHL16r1:
30844 case SHL16r1_EVEX:
30845 case SHL16r1_ND:
30846 case SHL16r1_NF:
30847 case SHL16r1_NF_ND:
30848 case SHL16rCL:
30849 case SHL16rCL_EVEX:
30850 case SHL16rCL_ND:
30851 case SHL16rCL_NF:
30852 case SHL16rCL_NF_ND:
30853 case SHL16ri:
30854 case SHL16ri_EVEX:
30855 case SHL16ri_ND:
30856 case SHL16ri_NF:
30857 case SHL16ri_NF_ND:
30858 case SHL32m1:
30859 case SHL32m1_EVEX:
30860 case SHL32m1_ND:
30861 case SHL32m1_NF:
30862 case SHL32m1_NF_ND:
30863 case SHL32mCL:
30864 case SHL32mCL_EVEX:
30865 case SHL32mCL_ND:
30866 case SHL32mCL_NF:
30867 case SHL32mCL_NF_ND:
30868 case SHL32mi:
30869 case SHL32mi_EVEX:
30870 case SHL32mi_ND:
30871 case SHL32mi_NF:
30872 case SHL32mi_NF_ND:
30873 case SHL32r1:
30874 case SHL32r1_EVEX:
30875 case SHL32r1_ND:
30876 case SHL32r1_NF:
30877 case SHL32r1_NF_ND:
30878 case SHL32rCL:
30879 case SHL32rCL_EVEX:
30880 case SHL32rCL_ND:
30881 case SHL32rCL_NF:
30882 case SHL32rCL_NF_ND:
30883 case SHL32ri:
30884 case SHL32ri_EVEX:
30885 case SHL32ri_ND:
30886 case SHL32ri_NF:
30887 case SHL32ri_NF_ND:
30888 case SHL64m1:
30889 case SHL64m1_EVEX:
30890 case SHL64m1_ND:
30891 case SHL64m1_NF:
30892 case SHL64m1_NF_ND:
30893 case SHL64mCL:
30894 case SHL64mCL_EVEX:
30895 case SHL64mCL_ND:
30896 case SHL64mCL_NF:
30897 case SHL64mCL_NF_ND:
30898 case SHL64mi:
30899 case SHL64mi_EVEX:
30900 case SHL64mi_ND:
30901 case SHL64mi_NF:
30902 case SHL64mi_NF_ND:
30903 case SHL64r1:
30904 case SHL64r1_EVEX:
30905 case SHL64r1_ND:
30906 case SHL64r1_NF:
30907 case SHL64r1_NF_ND:
30908 case SHL64rCL:
30909 case SHL64rCL_EVEX:
30910 case SHL64rCL_ND:
30911 case SHL64rCL_NF:
30912 case SHL64rCL_NF_ND:
30913 case SHL64ri:
30914 case SHL64ri_EVEX:
30915 case SHL64ri_ND:
30916 case SHL64ri_NF:
30917 case SHL64ri_NF_ND:
30918 case SHL8m1:
30919 case SHL8m1_EVEX:
30920 case SHL8m1_ND:
30921 case SHL8m1_NF:
30922 case SHL8m1_NF_ND:
30923 case SHL8mCL:
30924 case SHL8mCL_EVEX:
30925 case SHL8mCL_ND:
30926 case SHL8mCL_NF:
30927 case SHL8mCL_NF_ND:
30928 case SHL8mi:
30929 case SHL8mi_EVEX:
30930 case SHL8mi_ND:
30931 case SHL8mi_NF:
30932 case SHL8mi_NF_ND:
30933 case SHL8r1:
30934 case SHL8r1_EVEX:
30935 case SHL8r1_ND:
30936 case SHL8r1_NF:
30937 case SHL8r1_NF_ND:
30938 case SHL8rCL:
30939 case SHL8rCL_EVEX:
30940 case SHL8rCL_ND:
30941 case SHL8rCL_NF:
30942 case SHL8rCL_NF_ND:
30943 case SHL8ri:
30944 case SHL8ri_EVEX:
30945 case SHL8ri_ND:
30946 case SHL8ri_NF:
30947 case SHL8ri_NF_ND:
30948 return true;
30949 }
30950 return false;
30951}
30952
30953bool isAXOR(unsigned Opcode) {
30954 switch (Opcode) {
30955 case AXOR32mr:
30956 case AXOR32mr_EVEX:
30957 case AXOR64mr:
30958 case AXOR64mr_EVEX:
30959 return true;
30960 }
30961 return false;
30962}
30963
30964bool isVINSERTI64X2(unsigned Opcode) {
30965 switch (Opcode) {
30966 case VINSERTI64X2Z256rmi:
30967 case VINSERTI64X2Z256rmik:
30968 case VINSERTI64X2Z256rmikz:
30969 case VINSERTI64X2Z256rri:
30970 case VINSERTI64X2Z256rrik:
30971 case VINSERTI64X2Z256rrikz:
30972 case VINSERTI64X2Zrmi:
30973 case VINSERTI64X2Zrmik:
30974 case VINSERTI64X2Zrmikz:
30975 case VINSERTI64X2Zrri:
30976 case VINSERTI64X2Zrrik:
30977 case VINSERTI64X2Zrrikz:
30978 return true;
30979 }
30980 return false;
30981}
30982
30983bool isSYSRETQ(unsigned Opcode) {
30984 return Opcode == SYSRET64;
30985}
30986
30987bool isVSCATTERPF0QPD(unsigned Opcode) {
30988 return Opcode == VSCATTERPF0QPDm;
30989}
30990
30991bool isVFMSUB213SH(unsigned Opcode) {
30992 switch (Opcode) {
30993 case VFMSUB213SHZm_Int:
30994 case VFMSUB213SHZmk_Int:
30995 case VFMSUB213SHZmkz_Int:
30996 case VFMSUB213SHZr_Int:
30997 case VFMSUB213SHZrb_Int:
30998 case VFMSUB213SHZrbk_Int:
30999 case VFMSUB213SHZrbkz_Int:
31000 case VFMSUB213SHZrk_Int:
31001 case VFMSUB213SHZrkz_Int:
31002 return true;
31003 }
31004 return false;
31005}
31006
31007bool isVPMOVQW(unsigned Opcode) {
31008 switch (Opcode) {
31009 case VPMOVQWZ128mr:
31010 case VPMOVQWZ128mrk:
31011 case VPMOVQWZ128rr:
31012 case VPMOVQWZ128rrk:
31013 case VPMOVQWZ128rrkz:
31014 case VPMOVQWZ256mr:
31015 case VPMOVQWZ256mrk:
31016 case VPMOVQWZ256rr:
31017 case VPMOVQWZ256rrk:
31018 case VPMOVQWZ256rrkz:
31019 case VPMOVQWZmr:
31020 case VPMOVQWZmrk:
31021 case VPMOVQWZrr:
31022 case VPMOVQWZrrk:
31023 case VPMOVQWZrrkz:
31024 return true;
31025 }
31026 return false;
31027}
31028
31029bool isVREDUCEPD(unsigned Opcode) {
31030 switch (Opcode) {
31031 case VREDUCEPDZ128rmbi:
31032 case VREDUCEPDZ128rmbik:
31033 case VREDUCEPDZ128rmbikz:
31034 case VREDUCEPDZ128rmi:
31035 case VREDUCEPDZ128rmik:
31036 case VREDUCEPDZ128rmikz:
31037 case VREDUCEPDZ128rri:
31038 case VREDUCEPDZ128rrik:
31039 case VREDUCEPDZ128rrikz:
31040 case VREDUCEPDZ256rmbi:
31041 case VREDUCEPDZ256rmbik:
31042 case VREDUCEPDZ256rmbikz:
31043 case VREDUCEPDZ256rmi:
31044 case VREDUCEPDZ256rmik:
31045 case VREDUCEPDZ256rmikz:
31046 case VREDUCEPDZ256rri:
31047 case VREDUCEPDZ256rrik:
31048 case VREDUCEPDZ256rrikz:
31049 case VREDUCEPDZrmbi:
31050 case VREDUCEPDZrmbik:
31051 case VREDUCEPDZrmbikz:
31052 case VREDUCEPDZrmi:
31053 case VREDUCEPDZrmik:
31054 case VREDUCEPDZrmikz:
31055 case VREDUCEPDZrri:
31056 case VREDUCEPDZrrib:
31057 case VREDUCEPDZrribk:
31058 case VREDUCEPDZrribkz:
31059 case VREDUCEPDZrrik:
31060 case VREDUCEPDZrrikz:
31061 return true;
31062 }
31063 return false;
31064}
31065
31066bool isNOT(unsigned Opcode) {
31067 switch (Opcode) {
31068 case NOT16m:
31069 case NOT16m_EVEX:
31070 case NOT16m_ND:
31071 case NOT16r:
31072 case NOT16r_EVEX:
31073 case NOT16r_ND:
31074 case NOT32m:
31075 case NOT32m_EVEX:
31076 case NOT32m_ND:
31077 case NOT32r:
31078 case NOT32r_EVEX:
31079 case NOT32r_ND:
31080 case NOT64m:
31081 case NOT64m_EVEX:
31082 case NOT64m_ND:
31083 case NOT64r:
31084 case NOT64r_EVEX:
31085 case NOT64r_ND:
31086 case NOT8m:
31087 case NOT8m_EVEX:
31088 case NOT8m_ND:
31089 case NOT8r:
31090 case NOT8r_EVEX:
31091 case NOT8r_ND:
31092 return true;
31093 }
31094 return false;
31095}
31096
31097bool isLWPINS(unsigned Opcode) {
31098 switch (Opcode) {
31099 case LWPINS32rmi:
31100 case LWPINS32rri:
31101 case LWPINS64rmi:
31102 case LWPINS64rri:
31103 return true;
31104 }
31105 return false;
31106}
31107
31108bool isVSCATTERDPS(unsigned Opcode) {
31109 switch (Opcode) {
31110 case VSCATTERDPSZ128mr:
31111 case VSCATTERDPSZ256mr:
31112 case VSCATTERDPSZmr:
31113 return true;
31114 }
31115 return false;
31116}
31117
31118bool isVPMOVM2W(unsigned Opcode) {
31119 switch (Opcode) {
31120 case VPMOVM2WZ128rk:
31121 case VPMOVM2WZ256rk:
31122 case VPMOVM2WZrk:
31123 return true;
31124 }
31125 return false;
31126}
31127
31128bool isVFNMADD132PS(unsigned Opcode) {
31129 switch (Opcode) {
31130 case VFNMADD132PSYm:
31131 case VFNMADD132PSYr:
31132 case VFNMADD132PSZ128m:
31133 case VFNMADD132PSZ128mb:
31134 case VFNMADD132PSZ128mbk:
31135 case VFNMADD132PSZ128mbkz:
31136 case VFNMADD132PSZ128mk:
31137 case VFNMADD132PSZ128mkz:
31138 case VFNMADD132PSZ128r:
31139 case VFNMADD132PSZ128rk:
31140 case VFNMADD132PSZ128rkz:
31141 case VFNMADD132PSZ256m:
31142 case VFNMADD132PSZ256mb:
31143 case VFNMADD132PSZ256mbk:
31144 case VFNMADD132PSZ256mbkz:
31145 case VFNMADD132PSZ256mk:
31146 case VFNMADD132PSZ256mkz:
31147 case VFNMADD132PSZ256r:
31148 case VFNMADD132PSZ256rk:
31149 case VFNMADD132PSZ256rkz:
31150 case VFNMADD132PSZm:
31151 case VFNMADD132PSZmb:
31152 case VFNMADD132PSZmbk:
31153 case VFNMADD132PSZmbkz:
31154 case VFNMADD132PSZmk:
31155 case VFNMADD132PSZmkz:
31156 case VFNMADD132PSZr:
31157 case VFNMADD132PSZrb:
31158 case VFNMADD132PSZrbk:
31159 case VFNMADD132PSZrbkz:
31160 case VFNMADD132PSZrk:
31161 case VFNMADD132PSZrkz:
31162 case VFNMADD132PSm:
31163 case VFNMADD132PSr:
31164 return true;
31165 }
31166 return false;
31167}
31168
31169bool isMOVNTPS(unsigned Opcode) {
31170 return Opcode == MOVNTPSmr;
31171}
31172
31173bool isVRSQRTSS(unsigned Opcode) {
31174 switch (Opcode) {
31175 case VRSQRTSSm_Int:
31176 case VRSQRTSSr_Int:
31177 return true;
31178 }
31179 return false;
31180}
31181
31182bool isKMOVB(unsigned Opcode) {
31183 switch (Opcode) {
31184 case KMOVBkk:
31185 case KMOVBkk_EVEX:
31186 case KMOVBkm:
31187 case KMOVBkm_EVEX:
31188 case KMOVBkr:
31189 case KMOVBkr_EVEX:
31190 case KMOVBmk:
31191 case KMOVBmk_EVEX:
31192 case KMOVBrk:
31193 case KMOVBrk_EVEX:
31194 return true;
31195 }
31196 return false;
31197}
31198
31199bool isCVTSD2SS(unsigned Opcode) {
31200 switch (Opcode) {
31201 case CVTSD2SSrm_Int:
31202 case CVTSD2SSrr_Int:
31203 return true;
31204 }
31205 return false;
31206}
31207
31208bool isVBROADCASTF64X2(unsigned Opcode) {
31209 switch (Opcode) {
31210 case VBROADCASTF64X2Z256rm:
31211 case VBROADCASTF64X2Z256rmk:
31212 case VBROADCASTF64X2Z256rmkz:
31213 case VBROADCASTF64X2Zrm:
31214 case VBROADCASTF64X2Zrmk:
31215 case VBROADCASTF64X2Zrmkz:
31216 return true;
31217 }
31218 return false;
31219}
31220
31221bool isVDIVBF16(unsigned Opcode) {
31222 switch (Opcode) {
31223 case VDIVBF16Z128rm:
31224 case VDIVBF16Z128rmb:
31225 case VDIVBF16Z128rmbk:
31226 case VDIVBF16Z128rmbkz:
31227 case VDIVBF16Z128rmk:
31228 case VDIVBF16Z128rmkz:
31229 case VDIVBF16Z128rr:
31230 case VDIVBF16Z128rrk:
31231 case VDIVBF16Z128rrkz:
31232 case VDIVBF16Z256rm:
31233 case VDIVBF16Z256rmb:
31234 case VDIVBF16Z256rmbk:
31235 case VDIVBF16Z256rmbkz:
31236 case VDIVBF16Z256rmk:
31237 case VDIVBF16Z256rmkz:
31238 case VDIVBF16Z256rr:
31239 case VDIVBF16Z256rrk:
31240 case VDIVBF16Z256rrkz:
31241 case VDIVBF16Zrm:
31242 case VDIVBF16Zrmb:
31243 case VDIVBF16Zrmbk:
31244 case VDIVBF16Zrmbkz:
31245 case VDIVBF16Zrmk:
31246 case VDIVBF16Zrmkz:
31247 case VDIVBF16Zrr:
31248 case VDIVBF16Zrrk:
31249 case VDIVBF16Zrrkz:
31250 return true;
31251 }
31252 return false;
31253}
31254
31255bool isMOVNTPD(unsigned Opcode) {
31256 return Opcode == MOVNTPDmr;
31257}
31258
31259bool isMAXSD(unsigned Opcode) {
31260 switch (Opcode) {
31261 case MAXSDrm_Int:
31262 case MAXSDrr_Int:
31263 return true;
31264 }
31265 return false;
31266}
31267
31268bool isCMPPD(unsigned Opcode) {
31269 switch (Opcode) {
31270 case CMPPDrmi:
31271 case CMPPDrri:
31272 return true;
31273 }
31274 return false;
31275}
31276
31277bool isVPCMPESTRM(unsigned Opcode) {
31278 switch (Opcode) {
31279 case VPCMPESTRMrmi:
31280 case VPCMPESTRMrri:
31281 return true;
31282 }
31283 return false;
31284}
31285
31286bool isVFMSUB132PS(unsigned Opcode) {
31287 switch (Opcode) {
31288 case VFMSUB132PSYm:
31289 case VFMSUB132PSYr:
31290 case VFMSUB132PSZ128m:
31291 case VFMSUB132PSZ128mb:
31292 case VFMSUB132PSZ128mbk:
31293 case VFMSUB132PSZ128mbkz:
31294 case VFMSUB132PSZ128mk:
31295 case VFMSUB132PSZ128mkz:
31296 case VFMSUB132PSZ128r:
31297 case VFMSUB132PSZ128rk:
31298 case VFMSUB132PSZ128rkz:
31299 case VFMSUB132PSZ256m:
31300 case VFMSUB132PSZ256mb:
31301 case VFMSUB132PSZ256mbk:
31302 case VFMSUB132PSZ256mbkz:
31303 case VFMSUB132PSZ256mk:
31304 case VFMSUB132PSZ256mkz:
31305 case VFMSUB132PSZ256r:
31306 case VFMSUB132PSZ256rk:
31307 case VFMSUB132PSZ256rkz:
31308 case VFMSUB132PSZm:
31309 case VFMSUB132PSZmb:
31310 case VFMSUB132PSZmbk:
31311 case VFMSUB132PSZmbkz:
31312 case VFMSUB132PSZmk:
31313 case VFMSUB132PSZmkz:
31314 case VFMSUB132PSZr:
31315 case VFMSUB132PSZrb:
31316 case VFMSUB132PSZrbk:
31317 case VFMSUB132PSZrbkz:
31318 case VFMSUB132PSZrk:
31319 case VFMSUB132PSZrkz:
31320 case VFMSUB132PSm:
31321 case VFMSUB132PSr:
31322 return true;
31323 }
31324 return false;
31325}
31326
31327bool isVCOMISH(unsigned Opcode) {
31328 switch (Opcode) {
31329 case VCOMISHZrm:
31330 case VCOMISHZrr:
31331 case VCOMISHZrrb:
31332 return true;
31333 }
31334 return false;
31335}
31336
31337bool isF2XM1(unsigned Opcode) {
31338 return Opcode == F2XM1;
31339}
31340
31341bool isSQRTPD(unsigned Opcode) {
31342 switch (Opcode) {
31343 case SQRTPDm:
31344 case SQRTPDr:
31345 return true;
31346 }
31347 return false;
31348}
31349
31350bool isVFMSUBADDPS(unsigned Opcode) {
31351 switch (Opcode) {
31352 case VFMSUBADDPS4Ymr:
31353 case VFMSUBADDPS4Yrm:
31354 case VFMSUBADDPS4Yrr:
31355 case VFMSUBADDPS4Yrr_REV:
31356 case VFMSUBADDPS4mr:
31357 case VFMSUBADDPS4rm:
31358 case VFMSUBADDPS4rr:
31359 case VFMSUBADDPS4rr_REV:
31360 return true;
31361 }
31362 return false;
31363}
31364
31365bool isFXTRACT(unsigned Opcode) {
31366 return Opcode == FXTRACT;
31367}
31368
31369bool isVP4DPWSSD(unsigned Opcode) {
31370 switch (Opcode) {
31371 case VP4DPWSSDrm:
31372 case VP4DPWSSDrmk:
31373 case VP4DPWSSDrmkz:
31374 return true;
31375 }
31376 return false;
31377}
31378
31379bool isTDPBHF8PS(unsigned Opcode) {
31380 return Opcode == TDPBHF8PS;
31381}
31382
31383bool isVFMSUBADDPD(unsigned Opcode) {
31384 switch (Opcode) {
31385 case VFMSUBADDPD4Ymr:
31386 case VFMSUBADDPD4Yrm:
31387 case VFMSUBADDPD4Yrr:
31388 case VFMSUBADDPD4Yrr_REV:
31389 case VFMSUBADDPD4mr:
31390 case VFMSUBADDPD4rm:
31391 case VFMSUBADDPD4rr:
31392 case VFMSUBADDPD4rr_REV:
31393 return true;
31394 }
31395 return false;
31396}
31397
31398bool isVBCSTNEBF162PS(unsigned Opcode) {
31399 switch (Opcode) {
31400 case VBCSTNEBF162PSYrm:
31401 case VBCSTNEBF162PSrm:
31402 return true;
31403 }
31404 return false;
31405}
31406
31407bool isVPGATHERQQ(unsigned Opcode) {
31408 switch (Opcode) {
31409 case VPGATHERQQYrm:
31410 case VPGATHERQQZ128rm:
31411 case VPGATHERQQZ256rm:
31412 case VPGATHERQQZrm:
31413 case VPGATHERQQrm:
31414 return true;
31415 }
31416 return false;
31417}
31418
31419bool isPCMPEQB(unsigned Opcode) {
31420 switch (Opcode) {
31421 case MMX_PCMPEQBrm:
31422 case MMX_PCMPEQBrr:
31423 case PCMPEQBrm:
31424 case PCMPEQBrr:
31425 return true;
31426 }
31427 return false;
31428}
31429
31430bool isTILESTORED(unsigned Opcode) {
31431 switch (Opcode) {
31432 case TILESTORED:
31433 case TILESTORED_EVEX:
31434 return true;
31435 }
31436 return false;
31437}
31438
31439bool isBLSMSK(unsigned Opcode) {
31440 switch (Opcode) {
31441 case BLSMSK32rm:
31442 case BLSMSK32rm_EVEX:
31443 case BLSMSK32rm_NF:
31444 case BLSMSK32rr:
31445 case BLSMSK32rr_EVEX:
31446 case BLSMSK32rr_NF:
31447 case BLSMSK64rm:
31448 case BLSMSK64rm_EVEX:
31449 case BLSMSK64rm_NF:
31450 case BLSMSK64rr:
31451 case BLSMSK64rr_EVEX:
31452 case BLSMSK64rr_NF:
31453 return true;
31454 }
31455 return false;
31456}
31457
31458bool isVCVTTPS2DQ(unsigned Opcode) {
31459 switch (Opcode) {
31460 case VCVTTPS2DQYrm:
31461 case VCVTTPS2DQYrr:
31462 case VCVTTPS2DQZ128rm:
31463 case VCVTTPS2DQZ128rmb:
31464 case VCVTTPS2DQZ128rmbk:
31465 case VCVTTPS2DQZ128rmbkz:
31466 case VCVTTPS2DQZ128rmk:
31467 case VCVTTPS2DQZ128rmkz:
31468 case VCVTTPS2DQZ128rr:
31469 case VCVTTPS2DQZ128rrk:
31470 case VCVTTPS2DQZ128rrkz:
31471 case VCVTTPS2DQZ256rm:
31472 case VCVTTPS2DQZ256rmb:
31473 case VCVTTPS2DQZ256rmbk:
31474 case VCVTTPS2DQZ256rmbkz:
31475 case VCVTTPS2DQZ256rmk:
31476 case VCVTTPS2DQZ256rmkz:
31477 case VCVTTPS2DQZ256rr:
31478 case VCVTTPS2DQZ256rrk:
31479 case VCVTTPS2DQZ256rrkz:
31480 case VCVTTPS2DQZrm:
31481 case VCVTTPS2DQZrmb:
31482 case VCVTTPS2DQZrmbk:
31483 case VCVTTPS2DQZrmbkz:
31484 case VCVTTPS2DQZrmk:
31485 case VCVTTPS2DQZrmkz:
31486 case VCVTTPS2DQZrr:
31487 case VCVTTPS2DQZrrb:
31488 case VCVTTPS2DQZrrbk:
31489 case VCVTTPS2DQZrrbkz:
31490 case VCVTTPS2DQZrrk:
31491 case VCVTTPS2DQZrrkz:
31492 case VCVTTPS2DQrm:
31493 case VCVTTPS2DQrr:
31494 return true;
31495 }
31496 return false;
31497}
31498
31499bool isVFPCLASSBF16(unsigned Opcode) {
31500 switch (Opcode) {
31501 case VFPCLASSBF16Z128mbi:
31502 case VFPCLASSBF16Z128mbik:
31503 case VFPCLASSBF16Z128mi:
31504 case VFPCLASSBF16Z128mik:
31505 case VFPCLASSBF16Z128ri:
31506 case VFPCLASSBF16Z128rik:
31507 case VFPCLASSBF16Z256mbi:
31508 case VFPCLASSBF16Z256mbik:
31509 case VFPCLASSBF16Z256mi:
31510 case VFPCLASSBF16Z256mik:
31511 case VFPCLASSBF16Z256ri:
31512 case VFPCLASSBF16Z256rik:
31513 case VFPCLASSBF16Zmbi:
31514 case VFPCLASSBF16Zmbik:
31515 case VFPCLASSBF16Zmi:
31516 case VFPCLASSBF16Zmik:
31517 case VFPCLASSBF16Zri:
31518 case VFPCLASSBF16Zrik:
31519 return true;
31520 }
31521 return false;
31522}
31523
31524bool isVRNDSCALEPD(unsigned Opcode) {
31525 switch (Opcode) {
31526 case VRNDSCALEPDZ128rmbi:
31527 case VRNDSCALEPDZ128rmbik:
31528 case VRNDSCALEPDZ128rmbikz:
31529 case VRNDSCALEPDZ128rmi:
31530 case VRNDSCALEPDZ128rmik:
31531 case VRNDSCALEPDZ128rmikz:
31532 case VRNDSCALEPDZ128rri:
31533 case VRNDSCALEPDZ128rrik:
31534 case VRNDSCALEPDZ128rrikz:
31535 case VRNDSCALEPDZ256rmbi:
31536 case VRNDSCALEPDZ256rmbik:
31537 case VRNDSCALEPDZ256rmbikz:
31538 case VRNDSCALEPDZ256rmi:
31539 case VRNDSCALEPDZ256rmik:
31540 case VRNDSCALEPDZ256rmikz:
31541 case VRNDSCALEPDZ256rri:
31542 case VRNDSCALEPDZ256rrik:
31543 case VRNDSCALEPDZ256rrikz:
31544 case VRNDSCALEPDZrmbi:
31545 case VRNDSCALEPDZrmbik:
31546 case VRNDSCALEPDZrmbikz:
31547 case VRNDSCALEPDZrmi:
31548 case VRNDSCALEPDZrmik:
31549 case VRNDSCALEPDZrmikz:
31550 case VRNDSCALEPDZrri:
31551 case VRNDSCALEPDZrrib:
31552 case VRNDSCALEPDZrribk:
31553 case VRNDSCALEPDZrribkz:
31554 case VRNDSCALEPDZrrik:
31555 case VRNDSCALEPDZrrikz:
31556 return true;
31557 }
31558 return false;
31559}
31560
31561bool isVMLOAD(unsigned Opcode) {
31562 switch (Opcode) {
31563 case VMLOAD32:
31564 case VMLOAD64:
31565 return true;
31566 }
31567 return false;
31568}
31569
31570bool isVPTERNLOGQ(unsigned Opcode) {
31571 switch (Opcode) {
31572 case VPTERNLOGQZ128rmbi:
31573 case VPTERNLOGQZ128rmbik:
31574 case VPTERNLOGQZ128rmbikz:
31575 case VPTERNLOGQZ128rmi:
31576 case VPTERNLOGQZ128rmik:
31577 case VPTERNLOGQZ128rmikz:
31578 case VPTERNLOGQZ128rri:
31579 case VPTERNLOGQZ128rrik:
31580 case VPTERNLOGQZ128rrikz:
31581 case VPTERNLOGQZ256rmbi:
31582 case VPTERNLOGQZ256rmbik:
31583 case VPTERNLOGQZ256rmbikz:
31584 case VPTERNLOGQZ256rmi:
31585 case VPTERNLOGQZ256rmik:
31586 case VPTERNLOGQZ256rmikz:
31587 case VPTERNLOGQZ256rri:
31588 case VPTERNLOGQZ256rrik:
31589 case VPTERNLOGQZ256rrikz:
31590 case VPTERNLOGQZrmbi:
31591 case VPTERNLOGQZrmbik:
31592 case VPTERNLOGQZrmbikz:
31593 case VPTERNLOGQZrmi:
31594 case VPTERNLOGQZrmik:
31595 case VPTERNLOGQZrmikz:
31596 case VPTERNLOGQZrri:
31597 case VPTERNLOGQZrrik:
31598 case VPTERNLOGQZrrikz:
31599 return true;
31600 }
31601 return false;
31602}
31603
31604bool isKXNORD(unsigned Opcode) {
31605 return Opcode == KXNORDkk;
31606}
31607
31608bool isFXSAVE(unsigned Opcode) {
31609 return Opcode == FXSAVE;
31610}
31611
31612bool isVUNPCKHPD(unsigned Opcode) {
31613 switch (Opcode) {
31614 case VUNPCKHPDYrm:
31615 case VUNPCKHPDYrr:
31616 case VUNPCKHPDZ128rm:
31617 case VUNPCKHPDZ128rmb:
31618 case VUNPCKHPDZ128rmbk:
31619 case VUNPCKHPDZ128rmbkz:
31620 case VUNPCKHPDZ128rmk:
31621 case VUNPCKHPDZ128rmkz:
31622 case VUNPCKHPDZ128rr:
31623 case VUNPCKHPDZ128rrk:
31624 case VUNPCKHPDZ128rrkz:
31625 case VUNPCKHPDZ256rm:
31626 case VUNPCKHPDZ256rmb:
31627 case VUNPCKHPDZ256rmbk:
31628 case VUNPCKHPDZ256rmbkz:
31629 case VUNPCKHPDZ256rmk:
31630 case VUNPCKHPDZ256rmkz:
31631 case VUNPCKHPDZ256rr:
31632 case VUNPCKHPDZ256rrk:
31633 case VUNPCKHPDZ256rrkz:
31634 case VUNPCKHPDZrm:
31635 case VUNPCKHPDZrmb:
31636 case VUNPCKHPDZrmbk:
31637 case VUNPCKHPDZrmbkz:
31638 case VUNPCKHPDZrmk:
31639 case VUNPCKHPDZrmkz:
31640 case VUNPCKHPDZrr:
31641 case VUNPCKHPDZrrk:
31642 case VUNPCKHPDZrrkz:
31643 case VUNPCKHPDrm:
31644 case VUNPCKHPDrr:
31645 return true;
31646 }
31647 return false;
31648}
31649
31650bool isCVTPS2DQ(unsigned Opcode) {
31651 switch (Opcode) {
31652 case CVTPS2DQrm:
31653 case CVTPS2DQrr:
31654 return true;
31655 }
31656 return false;
31657}
31658
31659bool isVFMSUB213SS(unsigned Opcode) {
31660 switch (Opcode) {
31661 case VFMSUB213SSZm_Int:
31662 case VFMSUB213SSZmk_Int:
31663 case VFMSUB213SSZmkz_Int:
31664 case VFMSUB213SSZr_Int:
31665 case VFMSUB213SSZrb_Int:
31666 case VFMSUB213SSZrbk_Int:
31667 case VFMSUB213SSZrbkz_Int:
31668 case VFMSUB213SSZrk_Int:
31669 case VFMSUB213SSZrkz_Int:
31670 case VFMSUB213SSm_Int:
31671 case VFMSUB213SSr_Int:
31672 return true;
31673 }
31674 return false;
31675}
31676
31677bool isVPOPCNTD(unsigned Opcode) {
31678 switch (Opcode) {
31679 case VPOPCNTDZ128rm:
31680 case VPOPCNTDZ128rmb:
31681 case VPOPCNTDZ128rmbk:
31682 case VPOPCNTDZ128rmbkz:
31683 case VPOPCNTDZ128rmk:
31684 case VPOPCNTDZ128rmkz:
31685 case VPOPCNTDZ128rr:
31686 case VPOPCNTDZ128rrk:
31687 case VPOPCNTDZ128rrkz:
31688 case VPOPCNTDZ256rm:
31689 case VPOPCNTDZ256rmb:
31690 case VPOPCNTDZ256rmbk:
31691 case VPOPCNTDZ256rmbkz:
31692 case VPOPCNTDZ256rmk:
31693 case VPOPCNTDZ256rmkz:
31694 case VPOPCNTDZ256rr:
31695 case VPOPCNTDZ256rrk:
31696 case VPOPCNTDZ256rrkz:
31697 case VPOPCNTDZrm:
31698 case VPOPCNTDZrmb:
31699 case VPOPCNTDZrmbk:
31700 case VPOPCNTDZrmbkz:
31701 case VPOPCNTDZrmk:
31702 case VPOPCNTDZrmkz:
31703 case VPOPCNTDZrr:
31704 case VPOPCNTDZrrk:
31705 case VPOPCNTDZrrkz:
31706 return true;
31707 }
31708 return false;
31709}
31710
31711bool isSALC(unsigned Opcode) {
31712 return Opcode == SALC;
31713}
31714
31715bool isV4FNMADDSS(unsigned Opcode) {
31716 switch (Opcode) {
31717 case V4FNMADDSSrm:
31718 case V4FNMADDSSrmk:
31719 case V4FNMADDSSrmkz:
31720 return true;
31721 }
31722 return false;
31723}
31724
31725bool isXCRYPTOFB(unsigned Opcode) {
31726 return Opcode == XCRYPTOFB;
31727}
31728
31729bool isVORPD(unsigned Opcode) {
31730 switch (Opcode) {
31731 case VORPDYrm:
31732 case VORPDYrr:
31733 case VORPDZ128rm:
31734 case VORPDZ128rmb:
31735 case VORPDZ128rmbk:
31736 case VORPDZ128rmbkz:
31737 case VORPDZ128rmk:
31738 case VORPDZ128rmkz:
31739 case VORPDZ128rr:
31740 case VORPDZ128rrk:
31741 case VORPDZ128rrkz:
31742 case VORPDZ256rm:
31743 case VORPDZ256rmb:
31744 case VORPDZ256rmbk:
31745 case VORPDZ256rmbkz:
31746 case VORPDZ256rmk:
31747 case VORPDZ256rmkz:
31748 case VORPDZ256rr:
31749 case VORPDZ256rrk:
31750 case VORPDZ256rrkz:
31751 case VORPDZrm:
31752 case VORPDZrmb:
31753 case VORPDZrmbk:
31754 case VORPDZrmbkz:
31755 case VORPDZrmk:
31756 case VORPDZrmkz:
31757 case VORPDZrr:
31758 case VORPDZrrk:
31759 case VORPDZrrkz:
31760 case VORPDrm:
31761 case VORPDrr:
31762 return true;
31763 }
31764 return false;
31765}
31766
31767bool isLSL(unsigned Opcode) {
31768 switch (Opcode) {
31769 case LSL16rm:
31770 case LSL16rr:
31771 case LSL32rm:
31772 case LSL32rr:
31773 case LSL64rm:
31774 case LSL64rr:
31775 return true;
31776 }
31777 return false;
31778}
31779
31780bool isXCRYPTCFB(unsigned Opcode) {
31781 return Opcode == XCRYPTCFB;
31782}
31783
31784bool isVGETEXPSS(unsigned Opcode) {
31785 switch (Opcode) {
31786 case VGETEXPSSZm:
31787 case VGETEXPSSZmk:
31788 case VGETEXPSSZmkz:
31789 case VGETEXPSSZr:
31790 case VGETEXPSSZrb:
31791 case VGETEXPSSZrbk:
31792 case VGETEXPSSZrbkz:
31793 case VGETEXPSSZrk:
31794 case VGETEXPSSZrkz:
31795 return true;
31796 }
31797 return false;
31798}
31799
31800bool isPSLLDQ(unsigned Opcode) {
31801 return Opcode == PSLLDQri;
31802}
31803
31804bool isVPDPBUUD(unsigned Opcode) {
31805 switch (Opcode) {
31806 case VPDPBUUDYrm:
31807 case VPDPBUUDYrr:
31808 case VPDPBUUDZ128rm:
31809 case VPDPBUUDZ128rmb:
31810 case VPDPBUUDZ128rmbk:
31811 case VPDPBUUDZ128rmbkz:
31812 case VPDPBUUDZ128rmk:
31813 case VPDPBUUDZ128rmkz:
31814 case VPDPBUUDZ128rr:
31815 case VPDPBUUDZ128rrk:
31816 case VPDPBUUDZ128rrkz:
31817 case VPDPBUUDZ256rm:
31818 case VPDPBUUDZ256rmb:
31819 case VPDPBUUDZ256rmbk:
31820 case VPDPBUUDZ256rmbkz:
31821 case VPDPBUUDZ256rmk:
31822 case VPDPBUUDZ256rmkz:
31823 case VPDPBUUDZ256rr:
31824 case VPDPBUUDZ256rrk:
31825 case VPDPBUUDZ256rrkz:
31826 case VPDPBUUDZrm:
31827 case VPDPBUUDZrmb:
31828 case VPDPBUUDZrmbk:
31829 case VPDPBUUDZrmbkz:
31830 case VPDPBUUDZrmk:
31831 case VPDPBUUDZrmkz:
31832 case VPDPBUUDZrr:
31833 case VPDPBUUDZrrk:
31834 case VPDPBUUDZrrkz:
31835 case VPDPBUUDrm:
31836 case VPDPBUUDrr:
31837 return true;
31838 }
31839 return false;
31840}
31841
31842bool isVMXOFF(unsigned Opcode) {
31843 return Opcode == VMXOFF;
31844}
31845
31846bool isBLSIC(unsigned Opcode) {
31847 switch (Opcode) {
31848 case BLSIC32rm:
31849 case BLSIC32rr:
31850 case BLSIC64rm:
31851 case BLSIC64rr:
31852 return true;
31853 }
31854 return false;
31855}
31856
31857bool isMOVLHPS(unsigned Opcode) {
31858 return Opcode == MOVLHPSrr;
31859}
31860
31861bool isVMOVRSQ(unsigned Opcode) {
31862 switch (Opcode) {
31863 case VMOVRSQZ128m:
31864 case VMOVRSQZ128mk:
31865 case VMOVRSQZ128mkz:
31866 case VMOVRSQZ256m:
31867 case VMOVRSQZ256mk:
31868 case VMOVRSQZ256mkz:
31869 case VMOVRSQZm:
31870 case VMOVRSQZmk:
31871 case VMOVRSQZmkz:
31872 return true;
31873 }
31874 return false;
31875}
31876
31877bool isVFNMSUBSD(unsigned Opcode) {
31878 switch (Opcode) {
31879 case VFNMSUBSD4mr:
31880 case VFNMSUBSD4rm:
31881 case VFNMSUBSD4rr:
31882 case VFNMSUBSD4rr_REV:
31883 return true;
31884 }
31885 return false;
31886}
31887
31888bool isVCVTPH2IUBS(unsigned Opcode) {
31889 switch (Opcode) {
31890 case VCVTPH2IUBSZ128rm:
31891 case VCVTPH2IUBSZ128rmb:
31892 case VCVTPH2IUBSZ128rmbk:
31893 case VCVTPH2IUBSZ128rmbkz:
31894 case VCVTPH2IUBSZ128rmk:
31895 case VCVTPH2IUBSZ128rmkz:
31896 case VCVTPH2IUBSZ128rr:
31897 case VCVTPH2IUBSZ128rrk:
31898 case VCVTPH2IUBSZ128rrkz:
31899 case VCVTPH2IUBSZ256rm:
31900 case VCVTPH2IUBSZ256rmb:
31901 case VCVTPH2IUBSZ256rmbk:
31902 case VCVTPH2IUBSZ256rmbkz:
31903 case VCVTPH2IUBSZ256rmk:
31904 case VCVTPH2IUBSZ256rmkz:
31905 case VCVTPH2IUBSZ256rr:
31906 case VCVTPH2IUBSZ256rrk:
31907 case VCVTPH2IUBSZ256rrkz:
31908 case VCVTPH2IUBSZrm:
31909 case VCVTPH2IUBSZrmb:
31910 case VCVTPH2IUBSZrmbk:
31911 case VCVTPH2IUBSZrmbkz:
31912 case VCVTPH2IUBSZrmk:
31913 case VCVTPH2IUBSZrmkz:
31914 case VCVTPH2IUBSZrr:
31915 case VCVTPH2IUBSZrrb:
31916 case VCVTPH2IUBSZrrbk:
31917 case VCVTPH2IUBSZrrbkz:
31918 case VCVTPH2IUBSZrrk:
31919 case VCVTPH2IUBSZrrkz:
31920 return true;
31921 }
31922 return false;
31923}
31924
31925bool isVFPCLASSSH(unsigned Opcode) {
31926 switch (Opcode) {
31927 case VFPCLASSSHZmi:
31928 case VFPCLASSSHZmik:
31929 case VFPCLASSSHZri:
31930 case VFPCLASSSHZrik:
31931 return true;
31932 }
31933 return false;
31934}
31935
31936bool isVPSHLQ(unsigned Opcode) {
31937 switch (Opcode) {
31938 case VPSHLQmr:
31939 case VPSHLQrm:
31940 case VPSHLQrr:
31941 case VPSHLQrr_REV:
31942 return true;
31943 }
31944 return false;
31945}
31946
31947bool isVROUNDPS(unsigned Opcode) {
31948 switch (Opcode) {
31949 case VROUNDPSYmi:
31950 case VROUNDPSYri:
31951 case VROUNDPSmi:
31952 case VROUNDPSri:
31953 return true;
31954 }
31955 return false;
31956}
31957
31958bool isVSCATTERPF0QPS(unsigned Opcode) {
31959 return Opcode == VSCATTERPF0QPSm;
31960}
31961
31962bool isERETS(unsigned Opcode) {
31963 return Opcode == ERETS;
31964}
31965
31966bool isVPERMI2D(unsigned Opcode) {
31967 switch (Opcode) {
31968 case VPERMI2DZ128rm:
31969 case VPERMI2DZ128rmb:
31970 case VPERMI2DZ128rmbk:
31971 case VPERMI2DZ128rmbkz:
31972 case VPERMI2DZ128rmk:
31973 case VPERMI2DZ128rmkz:
31974 case VPERMI2DZ128rr:
31975 case VPERMI2DZ128rrk:
31976 case VPERMI2DZ128rrkz:
31977 case VPERMI2DZ256rm:
31978 case VPERMI2DZ256rmb:
31979 case VPERMI2DZ256rmbk:
31980 case VPERMI2DZ256rmbkz:
31981 case VPERMI2DZ256rmk:
31982 case VPERMI2DZ256rmkz:
31983 case VPERMI2DZ256rr:
31984 case VPERMI2DZ256rrk:
31985 case VPERMI2DZ256rrkz:
31986 case VPERMI2DZrm:
31987 case VPERMI2DZrmb:
31988 case VPERMI2DZrmbk:
31989 case VPERMI2DZrmbkz:
31990 case VPERMI2DZrmk:
31991 case VPERMI2DZrmkz:
31992 case VPERMI2DZrr:
31993 case VPERMI2DZrrk:
31994 case VPERMI2DZrrkz:
31995 return true;
31996 }
31997 return false;
31998}
31999
32000bool isFUCOMP(unsigned Opcode) {
32001 return Opcode == UCOM_FPr;
32002}
32003
32004bool isVCVTTPS2QQ(unsigned Opcode) {
32005 switch (Opcode) {
32006 case VCVTTPS2QQZ128rm:
32007 case VCVTTPS2QQZ128rmb:
32008 case VCVTTPS2QQZ128rmbk:
32009 case VCVTTPS2QQZ128rmbkz:
32010 case VCVTTPS2QQZ128rmk:
32011 case VCVTTPS2QQZ128rmkz:
32012 case VCVTTPS2QQZ128rr:
32013 case VCVTTPS2QQZ128rrk:
32014 case VCVTTPS2QQZ128rrkz:
32015 case VCVTTPS2QQZ256rm:
32016 case VCVTTPS2QQZ256rmb:
32017 case VCVTTPS2QQZ256rmbk:
32018 case VCVTTPS2QQZ256rmbkz:
32019 case VCVTTPS2QQZ256rmk:
32020 case VCVTTPS2QQZ256rmkz:
32021 case VCVTTPS2QQZ256rr:
32022 case VCVTTPS2QQZ256rrk:
32023 case VCVTTPS2QQZ256rrkz:
32024 case VCVTTPS2QQZrm:
32025 case VCVTTPS2QQZrmb:
32026 case VCVTTPS2QQZrmbk:
32027 case VCVTTPS2QQZrmbkz:
32028 case VCVTTPS2QQZrmk:
32029 case VCVTTPS2QQZrmkz:
32030 case VCVTTPS2QQZrr:
32031 case VCVTTPS2QQZrrb:
32032 case VCVTTPS2QQZrrbk:
32033 case VCVTTPS2QQZrrbkz:
32034 case VCVTTPS2QQZrrk:
32035 case VCVTTPS2QQZrrkz:
32036 return true;
32037 }
32038 return false;
32039}
32040
32041bool isPUSHFD(unsigned Opcode) {
32042 return Opcode == PUSHF32;
32043}
32044
32045bool isVPABSD(unsigned Opcode) {
32046 switch (Opcode) {
32047 case VPABSDYrm:
32048 case VPABSDYrr:
32049 case VPABSDZ128rm:
32050 case VPABSDZ128rmb:
32051 case VPABSDZ128rmbk:
32052 case VPABSDZ128rmbkz:
32053 case VPABSDZ128rmk:
32054 case VPABSDZ128rmkz:
32055 case VPABSDZ128rr:
32056 case VPABSDZ128rrk:
32057 case VPABSDZ128rrkz:
32058 case VPABSDZ256rm:
32059 case VPABSDZ256rmb:
32060 case VPABSDZ256rmbk:
32061 case VPABSDZ256rmbkz:
32062 case VPABSDZ256rmk:
32063 case VPABSDZ256rmkz:
32064 case VPABSDZ256rr:
32065 case VPABSDZ256rrk:
32066 case VPABSDZ256rrkz:
32067 case VPABSDZrm:
32068 case VPABSDZrmb:
32069 case VPABSDZrmbk:
32070 case VPABSDZrmbkz:
32071 case VPABSDZrmk:
32072 case VPABSDZrmkz:
32073 case VPABSDZrr:
32074 case VPABSDZrrk:
32075 case VPABSDZrrkz:
32076 case VPABSDrm:
32077 case VPABSDrr:
32078 return true;
32079 }
32080 return false;
32081}
32082
32083bool isKORB(unsigned Opcode) {
32084 return Opcode == KORBkk;
32085}
32086
32087bool isVRCP28PD(unsigned Opcode) {
32088 switch (Opcode) {
32089 case VRCP28PDZm:
32090 case VRCP28PDZmb:
32091 case VRCP28PDZmbk:
32092 case VRCP28PDZmbkz:
32093 case VRCP28PDZmk:
32094 case VRCP28PDZmkz:
32095 case VRCP28PDZr:
32096 case VRCP28PDZrb:
32097 case VRCP28PDZrbk:
32098 case VRCP28PDZrbkz:
32099 case VRCP28PDZrk:
32100 case VRCP28PDZrkz:
32101 return true;
32102 }
32103 return false;
32104}
32105
32106bool isVROUNDSS(unsigned Opcode) {
32107 switch (Opcode) {
32108 case VROUNDSSmi_Int:
32109 case VROUNDSSri_Int:
32110 return true;
32111 }
32112 return false;
32113}
32114
32115bool isVCVTSD2USI(unsigned Opcode) {
32116 switch (Opcode) {
32117 case VCVTSD2USI64Zrm_Int:
32118 case VCVTSD2USI64Zrr_Int:
32119 case VCVTSD2USI64Zrrb_Int:
32120 case VCVTSD2USIZrm_Int:
32121 case VCVTSD2USIZrr_Int:
32122 case VCVTSD2USIZrrb_Int:
32123 return true;
32124 }
32125 return false;
32126}
32127
32128bool isVPABSB(unsigned Opcode) {
32129 switch (Opcode) {
32130 case VPABSBYrm:
32131 case VPABSBYrr:
32132 case VPABSBZ128rm:
32133 case VPABSBZ128rmk:
32134 case VPABSBZ128rmkz:
32135 case VPABSBZ128rr:
32136 case VPABSBZ128rrk:
32137 case VPABSBZ128rrkz:
32138 case VPABSBZ256rm:
32139 case VPABSBZ256rmk:
32140 case VPABSBZ256rmkz:
32141 case VPABSBZ256rr:
32142 case VPABSBZ256rrk:
32143 case VPABSBZ256rrkz:
32144 case VPABSBZrm:
32145 case VPABSBZrmk:
32146 case VPABSBZrmkz:
32147 case VPABSBZrr:
32148 case VPABSBZrrk:
32149 case VPABSBZrrkz:
32150 case VPABSBrm:
32151 case VPABSBrr:
32152 return true;
32153 }
32154 return false;
32155}
32156
32157bool isPMAXUD(unsigned Opcode) {
32158 switch (Opcode) {
32159 case PMAXUDrm:
32160 case PMAXUDrr:
32161 return true;
32162 }
32163 return false;
32164}
32165
32166bool isVPERMPD(unsigned Opcode) {
32167 switch (Opcode) {
32168 case VPERMPDYmi:
32169 case VPERMPDYri:
32170 case VPERMPDZ256mbi:
32171 case VPERMPDZ256mbik:
32172 case VPERMPDZ256mbikz:
32173 case VPERMPDZ256mi:
32174 case VPERMPDZ256mik:
32175 case VPERMPDZ256mikz:
32176 case VPERMPDZ256ri:
32177 case VPERMPDZ256rik:
32178 case VPERMPDZ256rikz:
32179 case VPERMPDZ256rm:
32180 case VPERMPDZ256rmb:
32181 case VPERMPDZ256rmbk:
32182 case VPERMPDZ256rmbkz:
32183 case VPERMPDZ256rmk:
32184 case VPERMPDZ256rmkz:
32185 case VPERMPDZ256rr:
32186 case VPERMPDZ256rrk:
32187 case VPERMPDZ256rrkz:
32188 case VPERMPDZmbi:
32189 case VPERMPDZmbik:
32190 case VPERMPDZmbikz:
32191 case VPERMPDZmi:
32192 case VPERMPDZmik:
32193 case VPERMPDZmikz:
32194 case VPERMPDZri:
32195 case VPERMPDZrik:
32196 case VPERMPDZrikz:
32197 case VPERMPDZrm:
32198 case VPERMPDZrmb:
32199 case VPERMPDZrmbk:
32200 case VPERMPDZrmbkz:
32201 case VPERMPDZrmk:
32202 case VPERMPDZrmkz:
32203 case VPERMPDZrr:
32204 case VPERMPDZrrk:
32205 case VPERMPDZrrkz:
32206 return true;
32207 }
32208 return false;
32209}
32210
32211bool isVPMULHUW(unsigned Opcode) {
32212 switch (Opcode) {
32213 case VPMULHUWYrm:
32214 case VPMULHUWYrr:
32215 case VPMULHUWZ128rm:
32216 case VPMULHUWZ128rmk:
32217 case VPMULHUWZ128rmkz:
32218 case VPMULHUWZ128rr:
32219 case VPMULHUWZ128rrk:
32220 case VPMULHUWZ128rrkz:
32221 case VPMULHUWZ256rm:
32222 case VPMULHUWZ256rmk:
32223 case VPMULHUWZ256rmkz:
32224 case VPMULHUWZ256rr:
32225 case VPMULHUWZ256rrk:
32226 case VPMULHUWZ256rrkz:
32227 case VPMULHUWZrm:
32228 case VPMULHUWZrmk:
32229 case VPMULHUWZrmkz:
32230 case VPMULHUWZrr:
32231 case VPMULHUWZrrk:
32232 case VPMULHUWZrrkz:
32233 case VPMULHUWrm:
32234 case VPMULHUWrr:
32235 return true;
32236 }
32237 return false;
32238}
32239
32240bool isFCHS(unsigned Opcode) {
32241 return Opcode == CHS_F;
32242}
32243
32244bool isVPBLENDMB(unsigned Opcode) {
32245 switch (Opcode) {
32246 case VPBLENDMBZ128rm:
32247 case VPBLENDMBZ128rmk:
32248 case VPBLENDMBZ128rmkz:
32249 case VPBLENDMBZ128rr:
32250 case VPBLENDMBZ128rrk:
32251 case VPBLENDMBZ128rrkz:
32252 case VPBLENDMBZ256rm:
32253 case VPBLENDMBZ256rmk:
32254 case VPBLENDMBZ256rmkz:
32255 case VPBLENDMBZ256rr:
32256 case VPBLENDMBZ256rrk:
32257 case VPBLENDMBZ256rrkz:
32258 case VPBLENDMBZrm:
32259 case VPBLENDMBZrmk:
32260 case VPBLENDMBZrmkz:
32261 case VPBLENDMBZrr:
32262 case VPBLENDMBZrrk:
32263 case VPBLENDMBZrrkz:
32264 return true;
32265 }
32266 return false;
32267}
32268
32269bool isVGETMANTSS(unsigned Opcode) {
32270 switch (Opcode) {
32271 case VGETMANTSSZrmi:
32272 case VGETMANTSSZrmik:
32273 case VGETMANTSSZrmikz:
32274 case VGETMANTSSZrri:
32275 case VGETMANTSSZrrib:
32276 case VGETMANTSSZrribk:
32277 case VGETMANTSSZrribkz:
32278 case VGETMANTSSZrrik:
32279 case VGETMANTSSZrrikz:
32280 return true;
32281 }
32282 return false;
32283}
32284
32285bool isVPSLLW(unsigned Opcode) {
32286 switch (Opcode) {
32287 case VPSLLWYri:
32288 case VPSLLWYrm:
32289 case VPSLLWYrr:
32290 case VPSLLWZ128mi:
32291 case VPSLLWZ128mik:
32292 case VPSLLWZ128mikz:
32293 case VPSLLWZ128ri:
32294 case VPSLLWZ128rik:
32295 case VPSLLWZ128rikz:
32296 case VPSLLWZ128rm:
32297 case VPSLLWZ128rmk:
32298 case VPSLLWZ128rmkz:
32299 case VPSLLWZ128rr:
32300 case VPSLLWZ128rrk:
32301 case VPSLLWZ128rrkz:
32302 case VPSLLWZ256mi:
32303 case VPSLLWZ256mik:
32304 case VPSLLWZ256mikz:
32305 case VPSLLWZ256ri:
32306 case VPSLLWZ256rik:
32307 case VPSLLWZ256rikz:
32308 case VPSLLWZ256rm:
32309 case VPSLLWZ256rmk:
32310 case VPSLLWZ256rmkz:
32311 case VPSLLWZ256rr:
32312 case VPSLLWZ256rrk:
32313 case VPSLLWZ256rrkz:
32314 case VPSLLWZmi:
32315 case VPSLLWZmik:
32316 case VPSLLWZmikz:
32317 case VPSLLWZri:
32318 case VPSLLWZrik:
32319 case VPSLLWZrikz:
32320 case VPSLLWZrm:
32321 case VPSLLWZrmk:
32322 case VPSLLWZrmkz:
32323 case VPSLLWZrr:
32324 case VPSLLWZrrk:
32325 case VPSLLWZrrkz:
32326 case VPSLLWri:
32327 case VPSLLWrm:
32328 case VPSLLWrr:
32329 return true;
32330 }
32331 return false;
32332}
32333
32334bool isVDIVPD(unsigned Opcode) {
32335 switch (Opcode) {
32336 case VDIVPDYrm:
32337 case VDIVPDYrr:
32338 case VDIVPDZ128rm:
32339 case VDIVPDZ128rmb:
32340 case VDIVPDZ128rmbk:
32341 case VDIVPDZ128rmbkz:
32342 case VDIVPDZ128rmk:
32343 case VDIVPDZ128rmkz:
32344 case VDIVPDZ128rr:
32345 case VDIVPDZ128rrk:
32346 case VDIVPDZ128rrkz:
32347 case VDIVPDZ256rm:
32348 case VDIVPDZ256rmb:
32349 case VDIVPDZ256rmbk:
32350 case VDIVPDZ256rmbkz:
32351 case VDIVPDZ256rmk:
32352 case VDIVPDZ256rmkz:
32353 case VDIVPDZ256rr:
32354 case VDIVPDZ256rrk:
32355 case VDIVPDZ256rrkz:
32356 case VDIVPDZrm:
32357 case VDIVPDZrmb:
32358 case VDIVPDZrmbk:
32359 case VDIVPDZrmbkz:
32360 case VDIVPDZrmk:
32361 case VDIVPDZrmkz:
32362 case VDIVPDZrr:
32363 case VDIVPDZrrb:
32364 case VDIVPDZrrbk:
32365 case VDIVPDZrrbkz:
32366 case VDIVPDZrrk:
32367 case VDIVPDZrrkz:
32368 case VDIVPDrm:
32369 case VDIVPDrr:
32370 return true;
32371 }
32372 return false;
32373}
32374
32375bool isBLCMSK(unsigned Opcode) {
32376 switch (Opcode) {
32377 case BLCMSK32rm:
32378 case BLCMSK32rr:
32379 case BLCMSK64rm:
32380 case BLCMSK64rr:
32381 return true;
32382 }
32383 return false;
32384}
32385
32386bool isFDIV(unsigned Opcode) {
32387 switch (Opcode) {
32388 case DIV_F32m:
32389 case DIV_F64m:
32390 case DIV_FST0r:
32391 case DIV_FrST0:
32392 return true;
32393 }
32394 return false;
32395}
32396
32397bool isRSQRTSS(unsigned Opcode) {
32398 switch (Opcode) {
32399 case RSQRTSSm_Int:
32400 case RSQRTSSr_Int:
32401 return true;
32402 }
32403 return false;
32404}
32405
32406bool isPOR(unsigned Opcode) {
32407 switch (Opcode) {
32408 case MMX_PORrm:
32409 case MMX_PORrr:
32410 case PORrm:
32411 case PORrr:
32412 return true;
32413 }
32414 return false;
32415}
32416
32417bool isVMOVDQA32(unsigned Opcode) {
32418 switch (Opcode) {
32419 case VMOVDQA32Z128mr:
32420 case VMOVDQA32Z128mrk:
32421 case VMOVDQA32Z128rm:
32422 case VMOVDQA32Z128rmk:
32423 case VMOVDQA32Z128rmkz:
32424 case VMOVDQA32Z128rr:
32425 case VMOVDQA32Z128rr_REV:
32426 case VMOVDQA32Z128rrk:
32427 case VMOVDQA32Z128rrk_REV:
32428 case VMOVDQA32Z128rrkz:
32429 case VMOVDQA32Z128rrkz_REV:
32430 case VMOVDQA32Z256mr:
32431 case VMOVDQA32Z256mrk:
32432 case VMOVDQA32Z256rm:
32433 case VMOVDQA32Z256rmk:
32434 case VMOVDQA32Z256rmkz:
32435 case VMOVDQA32Z256rr:
32436 case VMOVDQA32Z256rr_REV:
32437 case VMOVDQA32Z256rrk:
32438 case VMOVDQA32Z256rrk_REV:
32439 case VMOVDQA32Z256rrkz:
32440 case VMOVDQA32Z256rrkz_REV:
32441 case VMOVDQA32Zmr:
32442 case VMOVDQA32Zmrk:
32443 case VMOVDQA32Zrm:
32444 case VMOVDQA32Zrmk:
32445 case VMOVDQA32Zrmkz:
32446 case VMOVDQA32Zrr:
32447 case VMOVDQA32Zrr_REV:
32448 case VMOVDQA32Zrrk:
32449 case VMOVDQA32Zrrk_REV:
32450 case VMOVDQA32Zrrkz:
32451 case VMOVDQA32Zrrkz_REV:
32452 return true;
32453 }
32454 return false;
32455}
32456
32457bool isVPHADDUWQ(unsigned Opcode) {
32458 switch (Opcode) {
32459 case VPHADDUWQrm:
32460 case VPHADDUWQrr:
32461 return true;
32462 }
32463 return false;
32464}
32465
32466bool isPSRAD(unsigned Opcode) {
32467 switch (Opcode) {
32468 case MMX_PSRADri:
32469 case MMX_PSRADrm:
32470 case MMX_PSRADrr:
32471 case PSRADri:
32472 case PSRADrm:
32473 case PSRADrr:
32474 return true;
32475 }
32476 return false;
32477}
32478
32479bool isPREFETCHW(unsigned Opcode) {
32480 return Opcode == PREFETCHW;
32481}
32482
32483bool isFIDIVR(unsigned Opcode) {
32484 switch (Opcode) {
32485 case DIVR_FI16m:
32486 case DIVR_FI32m:
32487 return true;
32488 }
32489 return false;
32490}
32491
32492bool isMOVHPS(unsigned Opcode) {
32493 switch (Opcode) {
32494 case MOVHPSmr:
32495 case MOVHPSrm:
32496 return true;
32497 }
32498 return false;
32499}
32500
32501bool isVFNMSUB231PH(unsigned Opcode) {
32502 switch (Opcode) {
32503 case VFNMSUB231PHZ128m:
32504 case VFNMSUB231PHZ128mb:
32505 case VFNMSUB231PHZ128mbk:
32506 case VFNMSUB231PHZ128mbkz:
32507 case VFNMSUB231PHZ128mk:
32508 case VFNMSUB231PHZ128mkz:
32509 case VFNMSUB231PHZ128r:
32510 case VFNMSUB231PHZ128rk:
32511 case VFNMSUB231PHZ128rkz:
32512 case VFNMSUB231PHZ256m:
32513 case VFNMSUB231PHZ256mb:
32514 case VFNMSUB231PHZ256mbk:
32515 case VFNMSUB231PHZ256mbkz:
32516 case VFNMSUB231PHZ256mk:
32517 case VFNMSUB231PHZ256mkz:
32518 case VFNMSUB231PHZ256r:
32519 case VFNMSUB231PHZ256rk:
32520 case VFNMSUB231PHZ256rkz:
32521 case VFNMSUB231PHZm:
32522 case VFNMSUB231PHZmb:
32523 case VFNMSUB231PHZmbk:
32524 case VFNMSUB231PHZmbkz:
32525 case VFNMSUB231PHZmk:
32526 case VFNMSUB231PHZmkz:
32527 case VFNMSUB231PHZr:
32528 case VFNMSUB231PHZrb:
32529 case VFNMSUB231PHZrbk:
32530 case VFNMSUB231PHZrbkz:
32531 case VFNMSUB231PHZrk:
32532 case VFNMSUB231PHZrkz:
32533 return true;
32534 }
32535 return false;
32536}
32537
32538bool isUNPCKLPS(unsigned Opcode) {
32539 switch (Opcode) {
32540 case UNPCKLPSrm:
32541 case UNPCKLPSrr:
32542 return true;
32543 }
32544 return false;
32545}
32546
32547bool isVPSIGNB(unsigned Opcode) {
32548 switch (Opcode) {
32549 case VPSIGNBYrm:
32550 case VPSIGNBYrr:
32551 case VPSIGNBrm:
32552 case VPSIGNBrr:
32553 return true;
32554 }
32555 return false;
32556}
32557
32558bool isSAVEPREVSSP(unsigned Opcode) {
32559 return Opcode == SAVEPREVSSP;
32560}
32561
32562bool isVSCALEFSD(unsigned Opcode) {
32563 switch (Opcode) {
32564 case VSCALEFSDZrm:
32565 case VSCALEFSDZrmk:
32566 case VSCALEFSDZrmkz:
32567 case VSCALEFSDZrr:
32568 case VSCALEFSDZrrb_Int:
32569 case VSCALEFSDZrrbk_Int:
32570 case VSCALEFSDZrrbkz_Int:
32571 case VSCALEFSDZrrk:
32572 case VSCALEFSDZrrkz:
32573 return true;
32574 }
32575 return false;
32576}
32577
32578bool isFSIN(unsigned Opcode) {
32579 return Opcode == FSIN;
32580}
32581
32582bool isSCASQ(unsigned Opcode) {
32583 return Opcode == SCASQ;
32584}
32585
32586bool isVCVTTPD2QQS(unsigned Opcode) {
32587 switch (Opcode) {
32588 case VCVTTPD2QQSZ128rm:
32589 case VCVTTPD2QQSZ128rmb:
32590 case VCVTTPD2QQSZ128rmbk:
32591 case VCVTTPD2QQSZ128rmbkz:
32592 case VCVTTPD2QQSZ128rmk:
32593 case VCVTTPD2QQSZ128rmkz:
32594 case VCVTTPD2QQSZ128rr:
32595 case VCVTTPD2QQSZ128rrk:
32596 case VCVTTPD2QQSZ128rrkz:
32597 case VCVTTPD2QQSZ256rm:
32598 case VCVTTPD2QQSZ256rmb:
32599 case VCVTTPD2QQSZ256rmbk:
32600 case VCVTTPD2QQSZ256rmbkz:
32601 case VCVTTPD2QQSZ256rmk:
32602 case VCVTTPD2QQSZ256rmkz:
32603 case VCVTTPD2QQSZ256rr:
32604 case VCVTTPD2QQSZ256rrb:
32605 case VCVTTPD2QQSZ256rrbk:
32606 case VCVTTPD2QQSZ256rrbkz:
32607 case VCVTTPD2QQSZ256rrk:
32608 case VCVTTPD2QQSZ256rrkz:
32609 case VCVTTPD2QQSZrm:
32610 case VCVTTPD2QQSZrmb:
32611 case VCVTTPD2QQSZrmbk:
32612 case VCVTTPD2QQSZrmbkz:
32613 case VCVTTPD2QQSZrmk:
32614 case VCVTTPD2QQSZrmkz:
32615 case VCVTTPD2QQSZrr:
32616 case VCVTTPD2QQSZrrb:
32617 case VCVTTPD2QQSZrrbk:
32618 case VCVTTPD2QQSZrrbkz:
32619 case VCVTTPD2QQSZrrk:
32620 case VCVTTPD2QQSZrrkz:
32621 return true;
32622 }
32623 return false;
32624}
32625
32626bool isPCMPGTW(unsigned Opcode) {
32627 switch (Opcode) {
32628 case MMX_PCMPGTWrm:
32629 case MMX_PCMPGTWrr:
32630 case PCMPGTWrm:
32631 case PCMPGTWrr:
32632 return true;
32633 }
32634 return false;
32635}
32636
32637bool isMULX(unsigned Opcode) {
32638 switch (Opcode) {
32639 case MULX32rm:
32640 case MULX32rm_EVEX:
32641 case MULX32rr:
32642 case MULX32rr_EVEX:
32643 case MULX64rm:
32644 case MULX64rm_EVEX:
32645 case MULX64rr:
32646 case MULX64rr_EVEX:
32647 return true;
32648 }
32649 return false;
32650}
32651
32652bool isVPMAXUW(unsigned Opcode) {
32653 switch (Opcode) {
32654 case VPMAXUWYrm:
32655 case VPMAXUWYrr:
32656 case VPMAXUWZ128rm:
32657 case VPMAXUWZ128rmk:
32658 case VPMAXUWZ128rmkz:
32659 case VPMAXUWZ128rr:
32660 case VPMAXUWZ128rrk:
32661 case VPMAXUWZ128rrkz:
32662 case VPMAXUWZ256rm:
32663 case VPMAXUWZ256rmk:
32664 case VPMAXUWZ256rmkz:
32665 case VPMAXUWZ256rr:
32666 case VPMAXUWZ256rrk:
32667 case VPMAXUWZ256rrkz:
32668 case VPMAXUWZrm:
32669 case VPMAXUWZrmk:
32670 case VPMAXUWZrmkz:
32671 case VPMAXUWZrr:
32672 case VPMAXUWZrrk:
32673 case VPMAXUWZrrkz:
32674 case VPMAXUWrm:
32675 case VPMAXUWrr:
32676 return true;
32677 }
32678 return false;
32679}
32680
32681bool isPAUSE(unsigned Opcode) {
32682 return Opcode == PAUSE;
32683}
32684
32685bool isMOVQ2DQ(unsigned Opcode) {
32686 return Opcode == MMX_MOVQ2DQrr;
32687}
32688
32689bool isVPABSW(unsigned Opcode) {
32690 switch (Opcode) {
32691 case VPABSWYrm:
32692 case VPABSWYrr:
32693 case VPABSWZ128rm:
32694 case VPABSWZ128rmk:
32695 case VPABSWZ128rmkz:
32696 case VPABSWZ128rr:
32697 case VPABSWZ128rrk:
32698 case VPABSWZ128rrkz:
32699 case VPABSWZ256rm:
32700 case VPABSWZ256rmk:
32701 case VPABSWZ256rmkz:
32702 case VPABSWZ256rr:
32703 case VPABSWZ256rrk:
32704 case VPABSWZ256rrkz:
32705 case VPABSWZrm:
32706 case VPABSWZrmk:
32707 case VPABSWZrmkz:
32708 case VPABSWZrr:
32709 case VPABSWZrrk:
32710 case VPABSWZrrkz:
32711 case VPABSWrm:
32712 case VPABSWrr:
32713 return true;
32714 }
32715 return false;
32716}
32717
32718bool isVBITREVB(unsigned Opcode) {
32719 switch (Opcode) {
32720 case VPBITREVBZ128rm:
32721 case VPBITREVBZ128rmk:
32722 case VPBITREVBZ128rmkz:
32723 case VPBITREVBZ128rr:
32724 case VPBITREVBZ128rrk:
32725 case VPBITREVBZ128rrkz:
32726 case VPBITREVBZ256rm:
32727 case VPBITREVBZ256rmk:
32728 case VPBITREVBZ256rmkz:
32729 case VPBITREVBZ256rr:
32730 case VPBITREVBZ256rrk:
32731 case VPBITREVBZ256rrkz:
32732 case VPBITREVBZrm:
32733 case VPBITREVBZrmk:
32734 case VPBITREVBZrmkz:
32735 case VPBITREVBZrr:
32736 case VPBITREVBZrrk:
32737 case VPBITREVBZrrkz:
32738 return true;
32739 }
32740 return false;
32741}
32742
32743bool isVPCOMPRESSD(unsigned Opcode) {
32744 switch (Opcode) {
32745 case VPCOMPRESSDZ128mr:
32746 case VPCOMPRESSDZ128mrk:
32747 case VPCOMPRESSDZ128rr:
32748 case VPCOMPRESSDZ128rrk:
32749 case VPCOMPRESSDZ128rrkz:
32750 case VPCOMPRESSDZ256mr:
32751 case VPCOMPRESSDZ256mrk:
32752 case VPCOMPRESSDZ256rr:
32753 case VPCOMPRESSDZ256rrk:
32754 case VPCOMPRESSDZ256rrkz:
32755 case VPCOMPRESSDZmr:
32756 case VPCOMPRESSDZmrk:
32757 case VPCOMPRESSDZrr:
32758 case VPCOMPRESSDZrrk:
32759 case VPCOMPRESSDZrrkz:
32760 return true;
32761 }
32762 return false;
32763}
32764
32765bool isVPSUBQ(unsigned Opcode) {
32766 switch (Opcode) {
32767 case VPSUBQYrm:
32768 case VPSUBQYrr:
32769 case VPSUBQZ128rm:
32770 case VPSUBQZ128rmb:
32771 case VPSUBQZ128rmbk:
32772 case VPSUBQZ128rmbkz:
32773 case VPSUBQZ128rmk:
32774 case VPSUBQZ128rmkz:
32775 case VPSUBQZ128rr:
32776 case VPSUBQZ128rrk:
32777 case VPSUBQZ128rrkz:
32778 case VPSUBQZ256rm:
32779 case VPSUBQZ256rmb:
32780 case VPSUBQZ256rmbk:
32781 case VPSUBQZ256rmbkz:
32782 case VPSUBQZ256rmk:
32783 case VPSUBQZ256rmkz:
32784 case VPSUBQZ256rr:
32785 case VPSUBQZ256rrk:
32786 case VPSUBQZ256rrkz:
32787 case VPSUBQZrm:
32788 case VPSUBQZrmb:
32789 case VPSUBQZrmbk:
32790 case VPSUBQZrmbkz:
32791 case VPSUBQZrmk:
32792 case VPSUBQZrmkz:
32793 case VPSUBQZrr:
32794 case VPSUBQZrrk:
32795 case VPSUBQZrrkz:
32796 case VPSUBQrm:
32797 case VPSUBQrr:
32798 return true;
32799 }
32800 return false;
32801}
32802
32803bool isVPMOVUSQW(unsigned Opcode) {
32804 switch (Opcode) {
32805 case VPMOVUSQWZ128mr:
32806 case VPMOVUSQWZ128mrk:
32807 case VPMOVUSQWZ128rr:
32808 case VPMOVUSQWZ128rrk:
32809 case VPMOVUSQWZ128rrkz:
32810 case VPMOVUSQWZ256mr:
32811 case VPMOVUSQWZ256mrk:
32812 case VPMOVUSQWZ256rr:
32813 case VPMOVUSQWZ256rrk:
32814 case VPMOVUSQWZ256rrkz:
32815 case VPMOVUSQWZmr:
32816 case VPMOVUSQWZmrk:
32817 case VPMOVUSQWZrr:
32818 case VPMOVUSQWZrrk:
32819 case VPMOVUSQWZrrkz:
32820 return true;
32821 }
32822 return false;
32823}
32824
32825bool isBLENDVPD(unsigned Opcode) {
32826 switch (Opcode) {
32827 case BLENDVPDrm0:
32828 case BLENDVPDrr0:
32829 return true;
32830 }
32831 return false;
32832}
32833
32834bool isVFNMADD132BF16(unsigned Opcode) {
32835 switch (Opcode) {
32836 case VFNMADD132BF16Z128m:
32837 case VFNMADD132BF16Z128mb:
32838 case VFNMADD132BF16Z128mbk:
32839 case VFNMADD132BF16Z128mbkz:
32840 case VFNMADD132BF16Z128mk:
32841 case VFNMADD132BF16Z128mkz:
32842 case VFNMADD132BF16Z128r:
32843 case VFNMADD132BF16Z128rk:
32844 case VFNMADD132BF16Z128rkz:
32845 case VFNMADD132BF16Z256m:
32846 case VFNMADD132BF16Z256mb:
32847 case VFNMADD132BF16Z256mbk:
32848 case VFNMADD132BF16Z256mbkz:
32849 case VFNMADD132BF16Z256mk:
32850 case VFNMADD132BF16Z256mkz:
32851 case VFNMADD132BF16Z256r:
32852 case VFNMADD132BF16Z256rk:
32853 case VFNMADD132BF16Z256rkz:
32854 case VFNMADD132BF16Zm:
32855 case VFNMADD132BF16Zmb:
32856 case VFNMADD132BF16Zmbk:
32857 case VFNMADD132BF16Zmbkz:
32858 case VFNMADD132BF16Zmk:
32859 case VFNMADD132BF16Zmkz:
32860 case VFNMADD132BF16Zr:
32861 case VFNMADD132BF16Zrk:
32862 case VFNMADD132BF16Zrkz:
32863 return true;
32864 }
32865 return false;
32866}
32867
32868bool isVPMOVQB(unsigned Opcode) {
32869 switch (Opcode) {
32870 case VPMOVQBZ128mr:
32871 case VPMOVQBZ128mrk:
32872 case VPMOVQBZ128rr:
32873 case VPMOVQBZ128rrk:
32874 case VPMOVQBZ128rrkz:
32875 case VPMOVQBZ256mr:
32876 case VPMOVQBZ256mrk:
32877 case VPMOVQBZ256rr:
32878 case VPMOVQBZ256rrk:
32879 case VPMOVQBZ256rrkz:
32880 case VPMOVQBZmr:
32881 case VPMOVQBZmrk:
32882 case VPMOVQBZrr:
32883 case VPMOVQBZrrk:
32884 case VPMOVQBZrrkz:
32885 return true;
32886 }
32887 return false;
32888}
32889
32890bool isVBLENDVPS(unsigned Opcode) {
32891 switch (Opcode) {
32892 case VBLENDVPSYrmr:
32893 case VBLENDVPSYrrr:
32894 case VBLENDVPSrmr:
32895 case VBLENDVPSrrr:
32896 return true;
32897 }
32898 return false;
32899}
32900
32901bool isKSHIFTLQ(unsigned Opcode) {
32902 return Opcode == KSHIFTLQki;
32903}
32904
32905bool isPMOVSXWD(unsigned Opcode) {
32906 switch (Opcode) {
32907 case PMOVSXWDrm:
32908 case PMOVSXWDrr:
32909 return true;
32910 }
32911 return false;
32912}
32913
32914bool isPHSUBSW(unsigned Opcode) {
32915 switch (Opcode) {
32916 case MMX_PHSUBSWrm:
32917 case MMX_PHSUBSWrr:
32918 case PHSUBSWrm:
32919 case PHSUBSWrr:
32920 return true;
32921 }
32922 return false;
32923}
32924
32925bool isPSRLQ(unsigned Opcode) {
32926 switch (Opcode) {
32927 case MMX_PSRLQri:
32928 case MMX_PSRLQrm:
32929 case MMX_PSRLQrr:
32930 case PSRLQri:
32931 case PSRLQrm:
32932 case PSRLQrr:
32933 return true;
32934 }
32935 return false;
32936}
32937
32938bool isVCVTPH2DQ(unsigned Opcode) {
32939 switch (Opcode) {
32940 case VCVTPH2DQZ128rm:
32941 case VCVTPH2DQZ128rmb:
32942 case VCVTPH2DQZ128rmbk:
32943 case VCVTPH2DQZ128rmbkz:
32944 case VCVTPH2DQZ128rmk:
32945 case VCVTPH2DQZ128rmkz:
32946 case VCVTPH2DQZ128rr:
32947 case VCVTPH2DQZ128rrk:
32948 case VCVTPH2DQZ128rrkz:
32949 case VCVTPH2DQZ256rm:
32950 case VCVTPH2DQZ256rmb:
32951 case VCVTPH2DQZ256rmbk:
32952 case VCVTPH2DQZ256rmbkz:
32953 case VCVTPH2DQZ256rmk:
32954 case VCVTPH2DQZ256rmkz:
32955 case VCVTPH2DQZ256rr:
32956 case VCVTPH2DQZ256rrk:
32957 case VCVTPH2DQZ256rrkz:
32958 case VCVTPH2DQZrm:
32959 case VCVTPH2DQZrmb:
32960 case VCVTPH2DQZrmbk:
32961 case VCVTPH2DQZrmbkz:
32962 case VCVTPH2DQZrmk:
32963 case VCVTPH2DQZrmkz:
32964 case VCVTPH2DQZrr:
32965 case VCVTPH2DQZrrb:
32966 case VCVTPH2DQZrrbk:
32967 case VCVTPH2DQZrrbkz:
32968 case VCVTPH2DQZrrk:
32969 case VCVTPH2DQZrrkz:
32970 return true;
32971 }
32972 return false;
32973}
32974
32975bool isPCMPESTRIQ(unsigned Opcode) {
32976 switch (Opcode) {
32977 case PCMPESTRIQrmi:
32978 case PCMPESTRIQrri:
32979 return true;
32980 }
32981 return false;
32982}
32983
32984bool isFISUB(unsigned Opcode) {
32985 switch (Opcode) {
32986 case SUB_FI16m:
32987 case SUB_FI32m:
32988 return true;
32989 }
32990 return false;
32991}
32992
32993bool isVCVTPS2UDQ(unsigned Opcode) {
32994 switch (Opcode) {
32995 case VCVTPS2UDQZ128rm:
32996 case VCVTPS2UDQZ128rmb:
32997 case VCVTPS2UDQZ128rmbk:
32998 case VCVTPS2UDQZ128rmbkz:
32999 case VCVTPS2UDQZ128rmk:
33000 case VCVTPS2UDQZ128rmkz:
33001 case VCVTPS2UDQZ128rr:
33002 case VCVTPS2UDQZ128rrk:
33003 case VCVTPS2UDQZ128rrkz:
33004 case VCVTPS2UDQZ256rm:
33005 case VCVTPS2UDQZ256rmb:
33006 case VCVTPS2UDQZ256rmbk:
33007 case VCVTPS2UDQZ256rmbkz:
33008 case VCVTPS2UDQZ256rmk:
33009 case VCVTPS2UDQZ256rmkz:
33010 case VCVTPS2UDQZ256rr:
33011 case VCVTPS2UDQZ256rrk:
33012 case VCVTPS2UDQZ256rrkz:
33013 case VCVTPS2UDQZrm:
33014 case VCVTPS2UDQZrmb:
33015 case VCVTPS2UDQZrmbk:
33016 case VCVTPS2UDQZrmbkz:
33017 case VCVTPS2UDQZrmk:
33018 case VCVTPS2UDQZrmkz:
33019 case VCVTPS2UDQZrr:
33020 case VCVTPS2UDQZrrb:
33021 case VCVTPS2UDQZrrbk:
33022 case VCVTPS2UDQZrrbkz:
33023 case VCVTPS2UDQZrrk:
33024 case VCVTPS2UDQZrrkz:
33025 return true;
33026 }
33027 return false;
33028}
33029
33030bool isVMOVDDUP(unsigned Opcode) {
33031 switch (Opcode) {
33032 case VMOVDDUPYrm:
33033 case VMOVDDUPYrr:
33034 case VMOVDDUPZ128rm:
33035 case VMOVDDUPZ128rmk:
33036 case VMOVDDUPZ128rmkz:
33037 case VMOVDDUPZ128rr:
33038 case VMOVDDUPZ128rrk:
33039 case VMOVDDUPZ128rrkz:
33040 case VMOVDDUPZ256rm:
33041 case VMOVDDUPZ256rmk:
33042 case VMOVDDUPZ256rmkz:
33043 case VMOVDDUPZ256rr:
33044 case VMOVDDUPZ256rrk:
33045 case VMOVDDUPZ256rrkz:
33046 case VMOVDDUPZrm:
33047 case VMOVDDUPZrmk:
33048 case VMOVDDUPZrmkz:
33049 case VMOVDDUPZrr:
33050 case VMOVDDUPZrrk:
33051 case VMOVDDUPZrrkz:
33052 case VMOVDDUPrm:
33053 case VMOVDDUPrr:
33054 return true;
33055 }
33056 return false;
33057}
33058
33059bool isPCMPEQD(unsigned Opcode) {
33060 switch (Opcode) {
33061 case MMX_PCMPEQDrm:
33062 case MMX_PCMPEQDrr:
33063 case PCMPEQDrm:
33064 case PCMPEQDrr:
33065 return true;
33066 }
33067 return false;
33068}
33069
33070bool isVRSQRT28SD(unsigned Opcode) {
33071 switch (Opcode) {
33072 case VRSQRT28SDZm:
33073 case VRSQRT28SDZmk:
33074 case VRSQRT28SDZmkz:
33075 case VRSQRT28SDZr:
33076 case VRSQRT28SDZrb:
33077 case VRSQRT28SDZrbk:
33078 case VRSQRT28SDZrbkz:
33079 case VRSQRT28SDZrk:
33080 case VRSQRT28SDZrkz:
33081 return true;
33082 }
33083 return false;
33084}
33085
33086bool isTDPHBF8PS(unsigned Opcode) {
33087 return Opcode == TDPHBF8PS;
33088}
33089
33090bool isVPOPCNTQ(unsigned Opcode) {
33091 switch (Opcode) {
33092 case VPOPCNTQZ128rm:
33093 case VPOPCNTQZ128rmb:
33094 case VPOPCNTQZ128rmbk:
33095 case VPOPCNTQZ128rmbkz:
33096 case VPOPCNTQZ128rmk:
33097 case VPOPCNTQZ128rmkz:
33098 case VPOPCNTQZ128rr:
33099 case VPOPCNTQZ128rrk:
33100 case VPOPCNTQZ128rrkz:
33101 case VPOPCNTQZ256rm:
33102 case VPOPCNTQZ256rmb:
33103 case VPOPCNTQZ256rmbk:
33104 case VPOPCNTQZ256rmbkz:
33105 case VPOPCNTQZ256rmk:
33106 case VPOPCNTQZ256rmkz:
33107 case VPOPCNTQZ256rr:
33108 case VPOPCNTQZ256rrk:
33109 case VPOPCNTQZ256rrkz:
33110 case VPOPCNTQZrm:
33111 case VPOPCNTQZrmb:
33112 case VPOPCNTQZrmbk:
33113 case VPOPCNTQZrmbkz:
33114 case VPOPCNTQZrmk:
33115 case VPOPCNTQZrmkz:
33116 case VPOPCNTQZrr:
33117 case VPOPCNTQZrrk:
33118 case VPOPCNTQZrrkz:
33119 return true;
33120 }
33121 return false;
33122}
33123
33124bool isLODSW(unsigned Opcode) {
33125 return Opcode == LODSW;
33126}
33127
33128bool isKSHIFTRB(unsigned Opcode) {
33129 return Opcode == KSHIFTRBki;
33130}
33131
33132bool isVFNMADDPS(unsigned Opcode) {
33133 switch (Opcode) {
33134 case VFNMADDPS4Ymr:
33135 case VFNMADDPS4Yrm:
33136 case VFNMADDPS4Yrr:
33137 case VFNMADDPS4Yrr_REV:
33138 case VFNMADDPS4mr:
33139 case VFNMADDPS4rm:
33140 case VFNMADDPS4rr:
33141 case VFNMADDPS4rr_REV:
33142 return true;
33143 }
33144 return false;
33145}
33146
33147bool isCCMPCC(unsigned Opcode) {
33148 switch (Opcode) {
33149 case CCMP16mi:
33150 case CCMP16mi8:
33151 case CCMP16mr:
33152 case CCMP16ri:
33153 case CCMP16ri8:
33154 case CCMP16rm:
33155 case CCMP16rr:
33156 case CCMP16rr_REV:
33157 case CCMP32mi:
33158 case CCMP32mi8:
33159 case CCMP32mr:
33160 case CCMP32ri:
33161 case CCMP32ri8:
33162 case CCMP32rm:
33163 case CCMP32rr:
33164 case CCMP32rr_REV:
33165 case CCMP64mi32:
33166 case CCMP64mi8:
33167 case CCMP64mr:
33168 case CCMP64ri32:
33169 case CCMP64ri8:
33170 case CCMP64rm:
33171 case CCMP64rr:
33172 case CCMP64rr_REV:
33173 case CCMP8mi:
33174 case CCMP8mr:
33175 case CCMP8ri:
33176 case CCMP8rm:
33177 case CCMP8rr:
33178 case CCMP8rr_REV:
33179 return true;
33180 }
33181 return false;
33182}
33183
33184bool isFXRSTOR64(unsigned Opcode) {
33185 return Opcode == FXRSTOR64;
33186}
33187
33188bool isVFMSUBADD213PD(unsigned Opcode) {
33189 switch (Opcode) {
33190 case VFMSUBADD213PDYm:
33191 case VFMSUBADD213PDYr:
33192 case VFMSUBADD213PDZ128m:
33193 case VFMSUBADD213PDZ128mb:
33194 case VFMSUBADD213PDZ128mbk:
33195 case VFMSUBADD213PDZ128mbkz:
33196 case VFMSUBADD213PDZ128mk:
33197 case VFMSUBADD213PDZ128mkz:
33198 case VFMSUBADD213PDZ128r:
33199 case VFMSUBADD213PDZ128rk:
33200 case VFMSUBADD213PDZ128rkz:
33201 case VFMSUBADD213PDZ256m:
33202 case VFMSUBADD213PDZ256mb:
33203 case VFMSUBADD213PDZ256mbk:
33204 case VFMSUBADD213PDZ256mbkz:
33205 case VFMSUBADD213PDZ256mk:
33206 case VFMSUBADD213PDZ256mkz:
33207 case VFMSUBADD213PDZ256r:
33208 case VFMSUBADD213PDZ256rk:
33209 case VFMSUBADD213PDZ256rkz:
33210 case VFMSUBADD213PDZm:
33211 case VFMSUBADD213PDZmb:
33212 case VFMSUBADD213PDZmbk:
33213 case VFMSUBADD213PDZmbkz:
33214 case VFMSUBADD213PDZmk:
33215 case VFMSUBADD213PDZmkz:
33216 case VFMSUBADD213PDZr:
33217 case VFMSUBADD213PDZrb:
33218 case VFMSUBADD213PDZrbk:
33219 case VFMSUBADD213PDZrbkz:
33220 case VFMSUBADD213PDZrk:
33221 case VFMSUBADD213PDZrkz:
33222 case VFMSUBADD213PDm:
33223 case VFMSUBADD213PDr:
33224 return true;
33225 }
33226 return false;
33227}
33228
33229bool isVSQRTPH(unsigned Opcode) {
33230 switch (Opcode) {
33231 case VSQRTPHZ128m:
33232 case VSQRTPHZ128mb:
33233 case VSQRTPHZ128mbk:
33234 case VSQRTPHZ128mbkz:
33235 case VSQRTPHZ128mk:
33236 case VSQRTPHZ128mkz:
33237 case VSQRTPHZ128r:
33238 case VSQRTPHZ128rk:
33239 case VSQRTPHZ128rkz:
33240 case VSQRTPHZ256m:
33241 case VSQRTPHZ256mb:
33242 case VSQRTPHZ256mbk:
33243 case VSQRTPHZ256mbkz:
33244 case VSQRTPHZ256mk:
33245 case VSQRTPHZ256mkz:
33246 case VSQRTPHZ256r:
33247 case VSQRTPHZ256rk:
33248 case VSQRTPHZ256rkz:
33249 case VSQRTPHZm:
33250 case VSQRTPHZmb:
33251 case VSQRTPHZmbk:
33252 case VSQRTPHZmbkz:
33253 case VSQRTPHZmk:
33254 case VSQRTPHZmkz:
33255 case VSQRTPHZr:
33256 case VSQRTPHZrb:
33257 case VSQRTPHZrbk:
33258 case VSQRTPHZrbkz:
33259 case VSQRTPHZrk:
33260 case VSQRTPHZrkz:
33261 return true;
33262 }
33263 return false;
33264}
33265
33266bool isPOPF(unsigned Opcode) {
33267 return Opcode == POPF16;
33268}
33269
33270bool isVPSUBUSB(unsigned Opcode) {
33271 switch (Opcode) {
33272 case VPSUBUSBYrm:
33273 case VPSUBUSBYrr:
33274 case VPSUBUSBZ128rm:
33275 case VPSUBUSBZ128rmk:
33276 case VPSUBUSBZ128rmkz:
33277 case VPSUBUSBZ128rr:
33278 case VPSUBUSBZ128rrk:
33279 case VPSUBUSBZ128rrkz:
33280 case VPSUBUSBZ256rm:
33281 case VPSUBUSBZ256rmk:
33282 case VPSUBUSBZ256rmkz:
33283 case VPSUBUSBZ256rr:
33284 case VPSUBUSBZ256rrk:
33285 case VPSUBUSBZ256rrkz:
33286 case VPSUBUSBZrm:
33287 case VPSUBUSBZrmk:
33288 case VPSUBUSBZrmkz:
33289 case VPSUBUSBZrr:
33290 case VPSUBUSBZrrk:
33291 case VPSUBUSBZrrkz:
33292 case VPSUBUSBrm:
33293 case VPSUBUSBrr:
33294 return true;
33295 }
33296 return false;
33297}
33298
33299bool isTCVTROWPS2BF16L(unsigned Opcode) {
33300 switch (Opcode) {
33301 case TCVTROWPS2BF16Lrte:
33302 case TCVTROWPS2BF16Lrti:
33303 return true;
33304 }
33305 return false;
33306}
33307
33308bool isVPADDSW(unsigned Opcode) {
33309 switch (Opcode) {
33310 case VPADDSWYrm:
33311 case VPADDSWYrr:
33312 case VPADDSWZ128rm:
33313 case VPADDSWZ128rmk:
33314 case VPADDSWZ128rmkz:
33315 case VPADDSWZ128rr:
33316 case VPADDSWZ128rrk:
33317 case VPADDSWZ128rrkz:
33318 case VPADDSWZ256rm:
33319 case VPADDSWZ256rmk:
33320 case VPADDSWZ256rmkz:
33321 case VPADDSWZ256rr:
33322 case VPADDSWZ256rrk:
33323 case VPADDSWZ256rrkz:
33324 case VPADDSWZrm:
33325 case VPADDSWZrmk:
33326 case VPADDSWZrmkz:
33327 case VPADDSWZrr:
33328 case VPADDSWZrrk:
33329 case VPADDSWZrrkz:
33330 case VPADDSWrm:
33331 case VPADDSWrr:
33332 return true;
33333 }
33334 return false;
33335}
33336
33337bool isPREFETCHIT1(unsigned Opcode) {
33338 return Opcode == PREFETCHIT1;
33339}
33340
33341bool isVADDSUBPD(unsigned Opcode) {
33342 switch (Opcode) {
33343 case VADDSUBPDYrm:
33344 case VADDSUBPDYrr:
33345 case VADDSUBPDrm:
33346 case VADDSUBPDrr:
33347 return true;
33348 }
33349 return false;
33350}
33351
33352bool isKANDD(unsigned Opcode) {
33353 return Opcode == KANDDkk;
33354}
33355
33356bool isPREFETCHRST2(unsigned Opcode) {
33357 return Opcode == PREFETCHRST2;
33358}
33359
33360bool isOUTSB(unsigned Opcode) {
33361 return Opcode == OUTSB;
33362}
33363
33364bool isFNSTSW(unsigned Opcode) {
33365 switch (Opcode) {
33366 case FNSTSW16r:
33367 case FNSTSWm:
33368 return true;
33369 }
33370 return false;
33371}
33372
33373bool isPMINSB(unsigned Opcode) {
33374 switch (Opcode) {
33375 case PMINSBrm:
33376 case PMINSBrr:
33377 return true;
33378 }
33379 return false;
33380}
33381
33382
33383} // namespace llvm::X86
33384
33385#endif // GET_X86_MNEMONIC_TABLES_CPP
33386
33387