1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* X86 Mnemonic tables *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_X86_MNEMONIC_TABLES_H
10#undef GET_X86_MNEMONIC_TABLES_H
11
12namespace llvm::X86 {
13
14bool isFSUBRP(unsigned Opcode);
15bool isVPDPBUSDS(unsigned Opcode);
16bool isPUNPCKLWD(unsigned Opcode);
17bool isVREDUCEBF16(unsigned Opcode);
18bool isPUNPCKLQDQ(unsigned Opcode);
19bool isRDFSBASE(unsigned Opcode);
20bool isVPCMOV(unsigned Opcode);
21bool isVDIVSD(unsigned Opcode);
22bool isVCVTTPS2IBS(unsigned Opcode);
23bool isVPEXTRW(unsigned Opcode);
24bool isLODSD(unsigned Opcode);
25bool isVPTESTNMQ(unsigned Opcode);
26bool isCVTSS2SD(unsigned Opcode);
27bool isVGETMANTPD(unsigned Opcode);
28bool isVMOVDQA64(unsigned Opcode);
29bool isINVLPG(unsigned Opcode);
30bool isVGETEXPBF16(unsigned Opcode);
31bool isVBROADCASTF64X4(unsigned Opcode);
32bool isVPERMI2Q(unsigned Opcode);
33bool isVPMOVSXBD(unsigned Opcode);
34bool isVFMSUB132SS(unsigned Opcode);
35bool isVPMOVUSDW(unsigned Opcode);
36bool isAAD(unsigned Opcode);
37bool isIDIV(unsigned Opcode);
38bool isCVTTPS2DQ(unsigned Opcode);
39bool isVBROADCASTF32X8(unsigned Opcode);
40bool isVFMSUBSS(unsigned Opcode);
41bool isEMMS(unsigned Opcode);
42bool isVPDPBSUD(unsigned Opcode);
43bool isPMOVSXWQ(unsigned Opcode);
44bool isPSRLW(unsigned Opcode);
45bool isMOVNTDQA(unsigned Opcode);
46bool isFUCOMPI(unsigned Opcode);
47bool isANDNPS(unsigned Opcode);
48bool isVINSERTF64X2(unsigned Opcode);
49bool isCLTS(unsigned Opcode);
50bool isSETSSBSY(unsigned Opcode);
51bool isVMULPD(unsigned Opcode);
52bool isVFMADDSUB132PS(unsigned Opcode);
53bool isVPMADCSWD(unsigned Opcode);
54bool isVSCATTERPF0DPS(unsigned Opcode);
55bool isXCHG(unsigned Opcode);
56bool isVGATHERPF1QPS(unsigned Opcode);
57bool isVCVTNEPS2BF16(unsigned Opcode);
58bool isVFMADDSS(unsigned Opcode);
59bool isINTO(unsigned Opcode);
60bool isANDPD(unsigned Opcode);
61bool isSEAMCALL(unsigned Opcode);
62bool isSHLD(unsigned Opcode);
63bool isUNPCKHPS(unsigned Opcode);
64bool isVPDPBSSDS(unsigned Opcode);
65bool isSETZUCC(unsigned Opcode);
66bool isSHUFPD(unsigned Opcode);
67bool isFCMOVNB(unsigned Opcode);
68bool isCVTTSS2SI(unsigned Opcode);
69bool isEXTRQ(unsigned Opcode);
70bool isVBROADCASTSS(unsigned Opcode);
71bool isCLUI(unsigned Opcode);
72bool isVINSERTI128(unsigned Opcode);
73bool isVPSHLDW(unsigned Opcode);
74bool isVBLENDPD(unsigned Opcode);
75bool isVSM4KEY4(unsigned Opcode);
76bool isVCVTNEEPH2PS(unsigned Opcode);
77bool isVCVTTSD2SI(unsigned Opcode);
78bool isWRMSRNS(unsigned Opcode);
79bool isCMPSB(unsigned Opcode);
80bool isVRCPBF16(unsigned Opcode);
81bool isMULSS(unsigned Opcode);
82bool isVMRUN(unsigned Opcode);
83bool isVPSRLVD(unsigned Opcode);
84bool isLEAVE(unsigned Opcode);
85bool isVGETMANTPS(unsigned Opcode);
86bool isXSHA256(unsigned Opcode);
87bool isBOUND(unsigned Opcode);
88bool isSFENCE(unsigned Opcode);
89bool isVPHADDD(unsigned Opcode);
90bool isADOX(unsigned Opcode);
91bool isVPSLLQ(unsigned Opcode);
92bool isVCVTPH2HF8(unsigned Opcode);
93bool isPFRSQIT1(unsigned Opcode);
94bool isCLAC(unsigned Opcode);
95bool isKNOTW(unsigned Opcode);
96bool isVCVTPH2PD(unsigned Opcode);
97bool isVAESENC(unsigned Opcode);
98bool isMOVNTI(unsigned Opcode);
99bool isFXCH(unsigned Opcode);
100bool isPOPP(unsigned Opcode);
101bool isVPBLENDMD(unsigned Opcode);
102bool isFSINCOS(unsigned Opcode);
103bool isVPMOVSXBW(unsigned Opcode);
104bool isVPMULLW(unsigned Opcode);
105bool isSTC(unsigned Opcode);
106bool isVPINSRB(unsigned Opcode);
107bool isLWPVAL(unsigned Opcode);
108bool isKXORB(unsigned Opcode);
109bool isRSTORSSP(unsigned Opcode);
110bool isVPRORQ(unsigned Opcode);
111bool isVSM3MSG1(unsigned Opcode);
112bool isFICOM(unsigned Opcode);
113bool isMAXPS(unsigned Opcode);
114bool isFNCLEX(unsigned Opcode);
115bool isVMOVMSKPS(unsigned Opcode);
116bool isVPMOVDB(unsigned Opcode);
117bool isLLWPCB(unsigned Opcode);
118bool isVMULSS(unsigned Opcode);
119bool isAESENCLAST(unsigned Opcode);
120bool isTILEMOVROW(unsigned Opcode);
121bool isVMINMAXPH(unsigned Opcode);
122bool isVPMAXUB(unsigned Opcode);
123bool isAAS(unsigned Opcode);
124bool isFADD(unsigned Opcode);
125bool isJMP(unsigned Opcode);
126bool isXCRYPTECB(unsigned Opcode);
127bool isPFRCPIT1(unsigned Opcode);
128bool isPMULHRW(unsigned Opcode);
129bool isVCVTPH2PS(unsigned Opcode);
130bool isVPBLENDVB(unsigned Opcode);
131bool isPCMPESTRI(unsigned Opcode);
132bool isSENDUIPI(unsigned Opcode);
133bool isFLDLN2(unsigned Opcode);
134bool isVPMACSWD(unsigned Opcode);
135bool isSHA1MSG1(unsigned Opcode);
136bool isVADDPS(unsigned Opcode);
137bool isVCVTPS2DQ(unsigned Opcode);
138bool isPFPNACC(unsigned Opcode);
139bool isFMUL(unsigned Opcode);
140bool isFNSAVE(unsigned Opcode);
141bool isCDQE(unsigned Opcode);
142bool isVPMACSDD(unsigned Opcode);
143bool isVSQRTPS(unsigned Opcode);
144bool isCMPSQ(unsigned Opcode);
145bool isVPSCATTERDD(unsigned Opcode);
146bool isVCVTTSD2USIS(unsigned Opcode);
147bool isVRNDSCALESD(unsigned Opcode);
148bool isSUBPS(unsigned Opcode);
149bool isVMAXSH(unsigned Opcode);
150bool isFLDZ(unsigned Opcode);
151bool isVFNMADD132SS(unsigned Opcode);
152bool isLGDTW(unsigned Opcode);
153bool isTCVTROWPS2PHH(unsigned Opcode);
154bool isINC(unsigned Opcode);
155bool isPABSB(unsigned Opcode);
156bool isVPANDN(unsigned Opcode);
157bool isVPMAXUD(unsigned Opcode);
158bool isVSHA512RNDS2(unsigned Opcode);
159bool isPHADDSW(unsigned Opcode);
160bool isVPMOVSQW(unsigned Opcode);
161bool isADDSUBPS(unsigned Opcode);
162bool isVPMACSSDQL(unsigned Opcode);
163bool isPXOR(unsigned Opcode);
164bool isVPSRAD(unsigned Opcode);
165bool isVPSHAB(unsigned Opcode);
166bool isBTR(unsigned Opcode);
167bool isKORW(unsigned Opcode);
168bool isVRANGESS(unsigned Opcode);
169bool isVCMPPS(unsigned Opcode);
170bool isVPLZCNTD(unsigned Opcode);
171bool isTDPBUUD(unsigned Opcode);
172bool isROUNDPS(unsigned Opcode);
173bool isFABS(unsigned Opcode);
174bool isSUBPD(unsigned Opcode);
175bool isGF2P8MULB(unsigned Opcode);
176bool isTZMSK(unsigned Opcode);
177bool isVMINMAXSD(unsigned Opcode);
178bool isANDPS(unsigned Opcode);
179bool isVEXTRACTF32X8(unsigned Opcode);
180bool isSEAMRET(unsigned Opcode);
181bool isVPCOMW(unsigned Opcode);
182bool isVFIXUPIMMPD(unsigned Opcode);
183bool isKANDND(unsigned Opcode);
184bool isVMRESUME(unsigned Opcode);
185bool isCVTPD2DQ(unsigned Opcode);
186bool isVFNMADD213PS(unsigned Opcode);
187bool isVPEXTRD(unsigned Opcode);
188bool isPACKUSWB(unsigned Opcode);
189bool isVEXTRACTI32X8(unsigned Opcode);
190bool isVHADDPD(unsigned Opcode);
191bool isVPSADBW(unsigned Opcode);
192bool isMOVDQ2Q(unsigned Opcode);
193bool isPUNPCKHBW(unsigned Opcode);
194bool isXOR(unsigned Opcode);
195bool isPSIGNB(unsigned Opcode);
196bool isVPHADDSW(unsigned Opcode);
197bool isFADDP(unsigned Opcode);
198bool isNEG(unsigned Opcode);
199bool isFLDLG2(unsigned Opcode);
200bool isFNOP(unsigned Opcode);
201bool isVMINSS(unsigned Opcode);
202bool isPCMPISTRM(unsigned Opcode);
203bool isVFMADD132SS(unsigned Opcode);
204bool isFDIVRP(unsigned Opcode);
205bool isPUSHAL(unsigned Opcode);
206bool isSUBSD(unsigned Opcode);
207bool isVPBLENDMQ(unsigned Opcode);
208bool isVPMACSDQL(unsigned Opcode);
209bool isVGATHERDPS(unsigned Opcode);
210bool isRMPREAD(unsigned Opcode);
211bool isSYSRET(unsigned Opcode);
212bool isVPADDB(unsigned Opcode);
213bool isXEND(unsigned Opcode);
214bool isWRSSD(unsigned Opcode);
215bool isVMINMAXSS(unsigned Opcode);
216bool isVCVTDQ2PH(unsigned Opcode);
217bool isCVTPD2PS(unsigned Opcode);
218bool isMAXPD(unsigned Opcode);
219bool isRCPSS(unsigned Opcode);
220bool isVMOVAPD(unsigned Opcode);
221bool isVPSUBSB(unsigned Opcode);
222bool isRDTSC(unsigned Opcode);
223bool isVCVTTPS2UDQS(unsigned Opcode);
224bool isVPMADCSSWD(unsigned Opcode);
225bool isVFNMADD213PH(unsigned Opcode);
226bool isVGF2P8AFFINEQB(unsigned Opcode);
227bool isPMOVZXWD(unsigned Opcode);
228bool isPMINUD(unsigned Opcode);
229bool isXSUSLDTRK(unsigned Opcode);
230bool isVCVTPH2UW(unsigned Opcode);
231bool isPADDSW(unsigned Opcode);
232bool isLFENCE(unsigned Opcode);
233bool isCRC32(unsigned Opcode);
234bool isAESENCWIDE256KL(unsigned Opcode);
235bool isMOVAPD(unsigned Opcode);
236bool isVFMADD213PS(unsigned Opcode);
237bool isVPDPWUUDS(unsigned Opcode);
238bool isMOVSLDUP(unsigned Opcode);
239bool isCLDEMOTE(unsigned Opcode);
240bool isVFNMADD231PS(unsigned Opcode);
241bool isVMOVMSKPD(unsigned Opcode);
242bool isPREFETCHT0(unsigned Opcode);
243bool isVCVTNEOBF162PS(unsigned Opcode);
244bool isVPCMPUD(unsigned Opcode);
245bool isVMAXSD(unsigned Opcode);
246bool isVRCP28SD(unsigned Opcode);
247bool isVMAXPS(unsigned Opcode);
248bool isVPMOVD2M(unsigned Opcode);
249bool isVPMACSSWD(unsigned Opcode);
250bool isVUCOMISD(unsigned Opcode);
251bool isLTR(unsigned Opcode);
252bool isVCVTUSI2SH(unsigned Opcode);
253bool isVSCATTERPF1QPS(unsigned Opcode);
254bool isWRGSBASE(unsigned Opcode);
255bool isSTOSQ(unsigned Opcode);
256bool isVSQRTSD(unsigned Opcode);
257bool isVPERMIL2PD(unsigned Opcode);
258bool isVFCMADDCSH(unsigned Opcode);
259bool isVFMADDSUB213PS(unsigned Opcode);
260bool isPFSUB(unsigned Opcode);
261bool isVSQRTSS(unsigned Opcode);
262bool isVEXPANDPS(unsigned Opcode);
263bool isVPCOMPRESSW(unsigned Opcode);
264bool isPEXTRD(unsigned Opcode);
265bool isVCVTTPS2UQQS(unsigned Opcode);
266bool isSYSEXITQ(unsigned Opcode);
267bool isROUNDSD(unsigned Opcode);
268bool isVFMADD132BF16(unsigned Opcode);
269bool isFCOM(unsigned Opcode);
270bool isVFNMSUBSS(unsigned Opcode);
271bool isKSHIFTLW(unsigned Opcode);
272bool isVMPTRLD(unsigned Opcode);
273bool isSCASD(unsigned Opcode);
274bool isVAESDECLAST(unsigned Opcode);
275bool isVFMADDSUBPS(unsigned Opcode);
276bool isVCVTUQQ2PS(unsigned Opcode);
277bool isVPMOVUSDB(unsigned Opcode);
278bool isVPROTW(unsigned Opcode);
279bool isVDPPS(unsigned Opcode);
280bool isVRSQRT14PD(unsigned Opcode);
281bool isVTESTPD(unsigned Opcode);
282bool isVFNMADD231SH(unsigned Opcode);
283bool isENDBR64(unsigned Opcode);
284bool isMULSD(unsigned Opcode);
285bool isXRSTORS(unsigned Opcode);
286bool isPREFETCHNTA(unsigned Opcode);
287bool isVPCOMD(unsigned Opcode);
288bool isVPCOMUB(unsigned Opcode);
289bool isVPDPBSSD(unsigned Opcode);
290bool isVPHSUBD(unsigned Opcode);
291bool isVBROADCASTI64X2(unsigned Opcode);
292bool isFPATAN(unsigned Opcode);
293bool isLOOPE(unsigned Opcode);
294bool isPCMPEQW(unsigned Opcode);
295bool isVFMADDCSH(unsigned Opcode);
296bool isMOVRS(unsigned Opcode);
297bool isVFMSUBADD132PH(unsigned Opcode);
298bool isKADDW(unsigned Opcode);
299bool isPTEST(unsigned Opcode);
300bool isVPADDSB(unsigned Opcode);
301bool isVRSQRT28PS(unsigned Opcode);
302bool isVGF2P8AFFINEINVQB(unsigned Opcode);
303bool isSERIALIZE(unsigned Opcode);
304bool isVPHADDWQ(unsigned Opcode);
305bool isVRNDSCALESH(unsigned Opcode);
306bool isAAA(unsigned Opcode);
307bool isVADDBF16(unsigned Opcode);
308bool isWRMSRLIST(unsigned Opcode);
309bool isVCVTPH2PSX(unsigned Opcode);
310bool isVFMSUB231PH(unsigned Opcode);
311bool isVGATHERQPD(unsigned Opcode);
312bool isKADDB(unsigned Opcode);
313bool isCVTPD2PI(unsigned Opcode);
314bool isVFNMSUB213PH(unsigned Opcode);
315bool isVPCMPESTRI(unsigned Opcode);
316bool isVPSHRDW(unsigned Opcode);
317bool isXORPS(unsigned Opcode);
318bool isPOP2(unsigned Opcode);
319bool isRDMSRLIST(unsigned Opcode);
320bool isVPDPBUSD(unsigned Opcode);
321bool isVCMPPH(unsigned Opcode);
322bool isVANDNPD(unsigned Opcode);
323bool isSUB(unsigned Opcode);
324bool isVRSQRT28PD(unsigned Opcode);
325bool isVFNMADD132PH(unsigned Opcode);
326bool isVPMACSSWW(unsigned Opcode);
327bool isXSTORE(unsigned Opcode);
328bool isVPROTQ(unsigned Opcode);
329bool isVPHADDBD(unsigned Opcode);
330bool isVPMAXSB(unsigned Opcode);
331bool isVMOVDQU8(unsigned Opcode);
332bool isVPMOVSXWD(unsigned Opcode);
333bool isVMINMAXPD(unsigned Opcode);
334bool isSHA256RNDS2(unsigned Opcode);
335bool isKANDB(unsigned Opcode);
336bool isTPAUSE(unsigned Opcode);
337bool isPUSH(unsigned Opcode);
338bool isVRNDSCALESS(unsigned Opcode);
339bool isVRNDSCALEBF16(unsigned Opcode);
340bool isVPCMPISTRI(unsigned Opcode);
341bool isSTGI(unsigned Opcode);
342bool isSBB(unsigned Opcode);
343bool isBLCS(unsigned Opcode);
344bool isVCVTSD2SH(unsigned Opcode);
345bool isVPERMW(unsigned Opcode);
346bool isXRESLDTRK(unsigned Opcode);
347bool isAESENC256KL(unsigned Opcode);
348bool isVGATHERDPD(unsigned Opcode);
349bool isHRESET(unsigned Opcode);
350bool isVFMSUBADD231PD(unsigned Opcode);
351bool isVFRCZSS(unsigned Opcode);
352bool isMINPS(unsigned Opcode);
353bool isFPREM1(unsigned Opcode);
354bool isVPCMPUB(unsigned Opcode);
355bool isVSQRTPD(unsigned Opcode);
356bool isVFRCZPS(unsigned Opcode);
357bool isVFNMADD213SS(unsigned Opcode);
358bool isVPSHRDVQ(unsigned Opcode);
359bool isVPMOVDW(unsigned Opcode);
360bool isVCVTPH2HF8S(unsigned Opcode);
361bool isVBROADCASTSD(unsigned Opcode);
362bool isVSHUFPD(unsigned Opcode);
363bool isVPSUBSW(unsigned Opcode);
364bool isKUNPCKBW(unsigned Opcode);
365bool isVPBLENDD(unsigned Opcode);
366bool isUNPCKHPD(unsigned Opcode);
367bool isVFNMADD231SD(unsigned Opcode);
368bool isVPBROADCASTMW2D(unsigned Opcode);
369bool isVPMULTISHIFTQB(unsigned Opcode);
370bool isVP2INTERSECTQ(unsigned Opcode);
371bool isVFNMSUB132BF16(unsigned Opcode);
372bool isVFMADD213BF16(unsigned Opcode);
373bool isVPUNPCKHWD(unsigned Opcode);
374bool isVPERM2F128(unsigned Opcode);
375bool isINSD(unsigned Opcode);
376bool isLFS(unsigned Opcode);
377bool isFMULP(unsigned Opcode);
378bool isCWD(unsigned Opcode);
379bool isVDIVSS(unsigned Opcode);
380bool isVPSRLQ(unsigned Opcode);
381bool isFSQRT(unsigned Opcode);
382bool isJRCXZ(unsigned Opcode);
383bool isVPMOVMSKB(unsigned Opcode);
384bool isAESDEC256KL(unsigned Opcode);
385bool isFLDENV(unsigned Opcode);
386bool isVPHSUBWD(unsigned Opcode);
387bool isWBNOINVD(unsigned Opcode);
388bool isVEXPANDPD(unsigned Opcode);
389bool isFYL2XP1(unsigned Opcode);
390bool isPREFETCHT2(unsigned Opcode);
391bool isVPDPBSUDS(unsigned Opcode);
392bool isVSHA512MSG2(unsigned Opcode);
393bool isPMULHUW(unsigned Opcode);
394bool isKANDNB(unsigned Opcode);
395bool isVCVTUW2PH(unsigned Opcode);
396bool isAESDECWIDE256KL(unsigned Opcode);
397bool isVPGATHERDD(unsigned Opcode);
398bool isVREDUCESH(unsigned Opcode);
399bool isPOPFQ(unsigned Opcode);
400bool isPAVGUSB(unsigned Opcode);
401bool isVALIGND(unsigned Opcode);
402bool isVPHMINPOSUW(unsigned Opcode);
403bool isLIDTD(unsigned Opcode);
404bool isVPERMT2PD(unsigned Opcode);
405bool isVMLAUNCH(unsigned Opcode);
406bool isVPXORQ(unsigned Opcode);
407bool isMOVNTDQ(unsigned Opcode);
408bool isPOP2P(unsigned Opcode);
409bool isVADDPD(unsigned Opcode);
410bool isSMSW(unsigned Opcode);
411bool isVEXP2PD(unsigned Opcode);
412bool isPMULUDQ(unsigned Opcode);
413bool isIRET(unsigned Opcode);
414bool isMULPS(unsigned Opcode);
415bool isTDPBF8PS(unsigned Opcode);
416bool isVFNMSUBPD(unsigned Opcode);
417bool isPHADDW(unsigned Opcode);
418bool isRDSEED(unsigned Opcode);
419bool isVPSHLW(unsigned Opcode);
420bool isRMPUPDATE(unsigned Opcode);
421bool isVFMADD231PH(unsigned Opcode);
422bool isVPSHAD(unsigned Opcode);
423bool isCLWB(unsigned Opcode);
424bool isPSUBUSB(unsigned Opcode);
425bool isVCVTTSD2USI(unsigned Opcode);
426bool isVEXTRACTPS(unsigned Opcode);
427bool isMOVLPD(unsigned Opcode);
428bool isLGDTD(unsigned Opcode);
429bool isVPBROADCASTMB2Q(unsigned Opcode);
430bool isOUT(unsigned Opcode);
431bool isVMSAVE(unsigned Opcode);
432bool isVCVTQQ2PD(unsigned Opcode);
433bool isVFMADD213PH(unsigned Opcode);
434bool isFCMOVBE(unsigned Opcode);
435bool isMOVSHDUP(unsigned Opcode);
436bool isVPMOVUSQB(unsigned Opcode);
437bool isFIST(unsigned Opcode);
438bool isHADDPD(unsigned Opcode);
439bool isPACKSSWB(unsigned Opcode);
440bool isVPMACSSDQH(unsigned Opcode);
441bool isVFNMSUB132SD(unsigned Opcode);
442bool isVPMASKMOVQ(unsigned Opcode);
443bool isVCOMPRESSPD(unsigned Opcode);
444bool isVFMADD213SS(unsigned Opcode);
445bool isVPCMPQ(unsigned Opcode);
446bool isVADDSH(unsigned Opcode);
447bool isVFNMADDSD(unsigned Opcode);
448bool isUMWAIT(unsigned Opcode);
449bool isVPUNPCKHDQ(unsigned Opcode);
450bool isLCALL(unsigned Opcode);
451bool isAESDEC128KL(unsigned Opcode);
452bool isVSUBPS(unsigned Opcode);
453bool isFSTP(unsigned Opcode);
454bool isVCVTUDQ2PD(unsigned Opcode);
455bool isVPMOVSWB(unsigned Opcode);
456bool isVPANDNQ(unsigned Opcode);
457bool isSYSENTER(unsigned Opcode);
458bool isVPHADDWD(unsigned Opcode);
459bool isVMOVHPD(unsigned Opcode);
460bool isMOVHPD(unsigned Opcode);
461bool isVDIVPH(unsigned Opcode);
462bool isFFREE(unsigned Opcode);
463bool isVGATHERPF1DPS(unsigned Opcode);
464bool isVPCMPESTRIQ(unsigned Opcode);
465bool isVFNMADD231PD(unsigned Opcode);
466bool isVFCMULCPH(unsigned Opcode);
467bool isVPADDD(unsigned Opcode);
468bool isVPCOMUQ(unsigned Opcode);
469bool isVSM3MSG2(unsigned Opcode);
470bool isVERR(unsigned Opcode);
471bool isKORTESTQ(unsigned Opcode);
472bool isVFMSUB132SD(unsigned Opcode);
473bool isTILEZERO(unsigned Opcode);
474bool isPFADD(unsigned Opcode);
475bool isVCVTSI2SD(unsigned Opcode);
476bool isTILELOADDRS(unsigned Opcode);
477bool isVSTMXCSR(unsigned Opcode);
478bool isVCVTTSH2SI(unsigned Opcode);
479bool isRET(unsigned Opcode);
480bool isLZCNT(unsigned Opcode);
481bool isMULPD(unsigned Opcode);
482bool isVBROADCASTI32X2(unsigned Opcode);
483bool isVCVTPH2W(unsigned Opcode);
484bool isCQO(unsigned Opcode);
485bool isFSUBR(unsigned Opcode);
486bool isDPPD(unsigned Opcode);
487bool isFCOS(unsigned Opcode);
488bool isXSAVES(unsigned Opcode);
489bool isTZCNT(unsigned Opcode);
490bool isLJMP(unsigned Opcode);
491bool isCMOVCC(unsigned Opcode);
492bool isVCVTBIASPH2HF8(unsigned Opcode);
493bool isINVEPT(unsigned Opcode);
494bool isADDSUBPD(unsigned Opcode);
495bool isVCVTSS2SD(unsigned Opcode);
496bool isVMOVSHDUP(unsigned Opcode);
497bool isKSHIFTRD(unsigned Opcode);
498bool isVPTERNLOGD(unsigned Opcode);
499bool isPADDQ(unsigned Opcode);
500bool isVEXTRACTI64X4(unsigned Opcode);
501bool isVFMSUB231SS(unsigned Opcode);
502bool isVPCMPEQB(unsigned Opcode);
503bool isLEA(unsigned Opcode);
504bool isPSUBB(unsigned Opcode);
505bool isKADDQ(unsigned Opcode);
506bool isMOVSX(unsigned Opcode);
507bool isVALIGNQ(unsigned Opcode);
508bool isVCVTNE2PS2BF16(unsigned Opcode);
509bool isVPSRAW(unsigned Opcode);
510bool isVFMSUBADD231PH(unsigned Opcode);
511bool isCVTDQ2PS(unsigned Opcode);
512bool isFBLD(unsigned Opcode);
513bool isLMSW(unsigned Opcode);
514bool isVRNDSCALEPH(unsigned Opcode);
515bool isMINSS(unsigned Opcode);
516bool isWRMSR(unsigned Opcode);
517bool isFSCALE(unsigned Opcode);
518bool isVFNMADD213SH(unsigned Opcode);
519bool isIMULZU(unsigned Opcode);
520bool isVPHADDUBD(unsigned Opcode);
521bool isRDSSPQ(unsigned Opcode);
522bool isVCVTBF162IBS(unsigned Opcode);
523bool isLGDT(unsigned Opcode);
524bool isVPSHLDVD(unsigned Opcode);
525bool isPFCMPGT(unsigned Opcode);
526bool isJCXZ(unsigned Opcode);
527bool isVPMOVZXBW(unsigned Opcode);
528bool isVFMADDSUB231PD(unsigned Opcode);
529bool isVBLENDMPD(unsigned Opcode);
530bool isHSUBPS(unsigned Opcode);
531bool isPREFETCHIT0(unsigned Opcode);
532bool isKTESTD(unsigned Opcode);
533bool isVCVTNEOPH2PS(unsigned Opcode);
534bool isVBLENDVPD(unsigned Opcode);
535bool isVCVTSS2USI(unsigned Opcode);
536bool isVCVTTPS2DQS(unsigned Opcode);
537bool isVPANDD(unsigned Opcode);
538bool isPMINSW(unsigned Opcode);
539bool isSTAC(unsigned Opcode);
540bool isVFMSUB213PS(unsigned Opcode);
541bool isPOPAL(unsigned Opcode);
542bool isVCVTPS2UQQ(unsigned Opcode);
543bool isRDRAND(unsigned Opcode);
544bool isJCC(unsigned Opcode);
545bool isVPMINSQ(unsigned Opcode);
546bool isVADDSD(unsigned Opcode);
547bool isDPPS(unsigned Opcode);
548bool isPINSRQ(unsigned Opcode);
549bool isVUCOMISS(unsigned Opcode);
550bool isVPDPWSUD(unsigned Opcode);
551bool isKANDNW(unsigned Opcode);
552bool isAOR(unsigned Opcode);
553bool isPMAXUB(unsigned Opcode);
554bool isANDNPD(unsigned Opcode);
555bool isINVPCID(unsigned Opcode);
556bool isRDGSBASE(unsigned Opcode);
557bool isVPMOVSQD(unsigned Opcode);
558bool isBT(unsigned Opcode);
559bool isVPROLVQ(unsigned Opcode);
560bool isVFMADDSUB132PD(unsigned Opcode);
561bool isRORX(unsigned Opcode);
562bool isPADDUSW(unsigned Opcode);
563bool isPFNACC(unsigned Opcode);
564bool isAND(unsigned Opcode);
565bool isPSLLQ(unsigned Opcode);
566bool isVFMSUB132PH(unsigned Opcode);
567bool isXSAVE(unsigned Opcode);
568bool isKNOTQ(unsigned Opcode);
569bool isXTEST(unsigned Opcode);
570bool isVINSERTPS(unsigned Opcode);
571bool isXSAVEOPT(unsigned Opcode);
572bool isLDS(unsigned Opcode);
573bool isVFMADDSUB213PD(unsigned Opcode);
574bool isVINSERTF32X4(unsigned Opcode);
575bool isVRSQRTPS(unsigned Opcode);
576bool isVSUBPH(unsigned Opcode);
577bool isPMOVSXBW(unsigned Opcode);
578bool isVPSRLDQ(unsigned Opcode);
579bool isADC(unsigned Opcode);
580bool isPHADDD(unsigned Opcode);
581bool isVDPPHPS(unsigned Opcode);
582bool isVMINPH(unsigned Opcode);
583bool isVMINSD(unsigned Opcode);
584bool isVROUNDPD(unsigned Opcode);
585bool isVFCMADDCPH(unsigned Opcode);
586bool isINCSSPQ(unsigned Opcode);
587bool isVPUNPCKLDQ(unsigned Opcode);
588bool isVMINSH(unsigned Opcode);
589bool isINSERTQ(unsigned Opcode);
590bool isBLCI(unsigned Opcode);
591bool isHLT(unsigned Opcode);
592bool isVPCOMUW(unsigned Opcode);
593bool isVPMOVSXDQ(unsigned Opcode);
594bool isVFNMSUB231PS(unsigned Opcode);
595bool isVFNMSUB213SH(unsigned Opcode);
596bool isVCVTTPD2UQQ(unsigned Opcode);
597bool isSQRTSS(unsigned Opcode);
598bool isIMUL(unsigned Opcode);
599bool isVCVTSS2SI(unsigned Opcode);
600bool isPUSHAW(unsigned Opcode);
601bool isSTOSD(unsigned Opcode);
602bool isPSRLDQ(unsigned Opcode);
603bool isVSCATTERQPS(unsigned Opcode);
604bool isFIDIV(unsigned Opcode);
605bool isVFMSUB213PD(unsigned Opcode);
606bool isVFMADDSUB231PH(unsigned Opcode);
607bool isTDCALL(unsigned Opcode);
608bool isPVALIDATE(unsigned Opcode);
609bool isVPSHUFLW(unsigned Opcode);
610bool isPCLMULQDQ(unsigned Opcode);
611bool isCMPXCHG8B(unsigned Opcode);
612bool isVPMOVM2B(unsigned Opcode);
613bool isVCVTUDQ2PH(unsigned Opcode);
614bool isPEXTRQ(unsigned Opcode);
615bool isXCRYPTCTR(unsigned Opcode);
616bool isVREDUCEPH(unsigned Opcode);
617bool isUCOMISD(unsigned Opcode);
618bool isOUTSD(unsigned Opcode);
619bool isSUBSS(unsigned Opcode);
620bool isVFMSUBPS(unsigned Opcode);
621bool isVPBLENDW(unsigned Opcode);
622bool isVPEXPANDB(unsigned Opcode);
623bool isBZHI(unsigned Opcode);
624bool isVPRORVD(unsigned Opcode);
625bool isRMPQUERY(unsigned Opcode);
626bool isVPSCATTERDQ(unsigned Opcode);
627bool isPSMASH(unsigned Opcode);
628bool isVPSHLDQ(unsigned Opcode);
629bool isVSCATTERPF1DPD(unsigned Opcode);
630bool isMONTMUL(unsigned Opcode);
631bool isVCVTPH2UQQ(unsigned Opcode);
632bool isPSLLD(unsigned Opcode);
633bool isSAR(unsigned Opcode);
634bool isLDTILECFG(unsigned Opcode);
635bool isPMINUB(unsigned Opcode);
636bool isVCVTNEEBF162PS(unsigned Opcode);
637bool isMOVDIR64B(unsigned Opcode);
638bool isSQRTPS(unsigned Opcode);
639bool isSTR(unsigned Opcode);
640bool isKANDNQ(unsigned Opcode);
641bool isBSF(unsigned Opcode);
642bool isINCSSPD(unsigned Opcode);
643bool isVPDPBUUDS(unsigned Opcode);
644bool isCMPXCHG(unsigned Opcode);
645bool isVPSIGNW(unsigned Opcode);
646bool isVCOMISBF16(unsigned Opcode);
647bool isLES(unsigned Opcode);
648bool isCVTSS2SI(unsigned Opcode);
649bool isPFACC(unsigned Opcode);
650bool isFCOMPI(unsigned Opcode);
651bool isPUNPCKHWD(unsigned Opcode);
652bool isVPMOVUSWB(unsigned Opcode);
653bool isVPTESTNMW(unsigned Opcode);
654bool isVPMULDQ(unsigned Opcode);
655bool isSHRX(unsigned Opcode);
656bool isKXORQ(unsigned Opcode);
657bool isVGETEXPSD(unsigned Opcode);
658bool isV4FNMADDPS(unsigned Opcode);
659bool isVFNMSUB231SD(unsigned Opcode);
660bool isVPSHLD(unsigned Opcode);
661bool isPAVGB(unsigned Opcode);
662bool isPMOVZXBD(unsigned Opcode);
663bool isKORTESTW(unsigned Opcode);
664bool isVSHUFPS(unsigned Opcode);
665bool isAESENCWIDE128KL(unsigned Opcode);
666bool isVPXORD(unsigned Opcode);
667bool isVPSHAW(unsigned Opcode);
668bool isVFMSUB132BF16(unsigned Opcode);
669bool isVPERMT2B(unsigned Opcode);
670bool isVFMADD213PD(unsigned Opcode);
671bool isVPGATHERQD(unsigned Opcode);
672bool isVFNMSUB213BF16(unsigned Opcode);
673bool isVCVTPS2IBS(unsigned Opcode);
674bool isVPCMPGTW(unsigned Opcode);
675bool isVMOVRSB(unsigned Opcode);
676bool isVGETMANTSH(unsigned Opcode);
677bool isVANDPS(unsigned Opcode);
678bool isVDIVPS(unsigned Opcode);
679bool isVANDNPS(unsigned Opcode);
680bool isVPBROADCASTW(unsigned Opcode);
681bool isFLDL2T(unsigned Opcode);
682bool isVPERMB(unsigned Opcode);
683bool isFCMOVNBE(unsigned Opcode);
684bool isVCVTTPH2W(unsigned Opcode);
685bool isPMOVZXBQ(unsigned Opcode);
686bool isPF2ID(unsigned Opcode);
687bool isVFNMADD132PD(unsigned Opcode);
688bool isPMULHRSW(unsigned Opcode);
689bool isKADDD(unsigned Opcode);
690bool isVFNMSUB132SH(unsigned Opcode);
691bool isUIRET(unsigned Opcode);
692bool isBSR(unsigned Opcode);
693bool isPCMPEQQ(unsigned Opcode);
694bool isCDQ(unsigned Opcode);
695bool isPMAXSW(unsigned Opcode);
696bool isSIDTD(unsigned Opcode);
697bool isVCVTPS2PHX(unsigned Opcode);
698bool isVPSLLVQ(unsigned Opcode);
699bool isMOVQ(unsigned Opcode);
700bool isPREFETCH(unsigned Opcode);
701bool isVCMPBF16(unsigned Opcode);
702bool isVBMACOR16X16X16(unsigned Opcode);
703bool isCLRSSBSY(unsigned Opcode);
704bool isTCVTROWPS2PHL(unsigned Opcode);
705bool isPSHUFW(unsigned Opcode);
706bool isVPDPWSUDS(unsigned Opcode);
707bool isVPMOVSXBQ(unsigned Opcode);
708bool isFICOMP(unsigned Opcode);
709bool isVFNMSUB132SS(unsigned Opcode);
710bool isVLDMXCSR(unsigned Opcode);
711bool isVPSUBUSW(unsigned Opcode);
712bool isRETF(unsigned Opcode);
713bool isKMOVQ(unsigned Opcode);
714bool isVPADDUSW(unsigned Opcode);
715bool isPACKSSDW(unsigned Opcode);
716bool isUMONITOR(unsigned Opcode);
717bool isENQCMDS(unsigned Opcode);
718bool isVCOMXSD(unsigned Opcode);
719bool isVPMAXSQ(unsigned Opcode);
720bool isVFMSUB213BF16(unsigned Opcode);
721bool isVPERMT2Q(unsigned Opcode);
722bool isFDECSTP(unsigned Opcode);
723bool isVPTESTMQ(unsigned Opcode);
724bool isVRCP14PD(unsigned Opcode);
725bool isARPL(unsigned Opcode);
726bool isVFMSUB213SD(unsigned Opcode);
727bool isJMPABS(unsigned Opcode);
728bool isVUNPCKHPS(unsigned Opcode);
729bool isVFNMADDSS(unsigned Opcode);
730bool isSIDT(unsigned Opcode);
731bool isVPCMPGTB(unsigned Opcode);
732bool isVPRORD(unsigned Opcode);
733bool isVSUBSS(unsigned Opcode);
734bool isPUSHFQ(unsigned Opcode);
735bool isVCVTHF82PH(unsigned Opcode);
736bool isVPCLMULQDQ(unsigned Opcode);
737bool isVPADDUSB(unsigned Opcode);
738bool isVPCMPD(unsigned Opcode);
739bool isMOVSD(unsigned Opcode);
740bool isPSUBUSW(unsigned Opcode);
741bool isVFMSUBADD132PS(unsigned Opcode);
742bool isMOVMSKPS(unsigned Opcode);
743bool isVFIXUPIMMSS(unsigned Opcode);
744bool isMFENCE(unsigned Opcode);
745bool isFTST(unsigned Opcode);
746bool isVPMADDWD(unsigned Opcode);
747bool isPOP(unsigned Opcode);
748bool isPSUBW(unsigned Opcode);
749bool isBSWAP(unsigned Opcode);
750bool isPFMIN(unsigned Opcode);
751bool isVFPCLASSPD(unsigned Opcode);
752bool isVPSHRDVD(unsigned Opcode);
753bool isPADDW(unsigned Opcode);
754bool isCVTSI2SD(unsigned Opcode);
755bool isENQCMD(unsigned Opcode);
756bool isXSHA1(unsigned Opcode);
757bool isVFNMADD132SD(unsigned Opcode);
758bool isMOVZX(unsigned Opcode);
759bool isVFIXUPIMMSD(unsigned Opcode);
760bool isINVD(unsigned Opcode);
761bool isVFIXUPIMMPS(unsigned Opcode);
762bool isMOVDQU(unsigned Opcode);
763bool isVFPCLASSPS(unsigned Opcode);
764bool isVPERMILPS(unsigned Opcode);
765bool isMOVSQ(unsigned Opcode);
766bool isAESDECWIDE128KL(unsigned Opcode);
767bool isROUNDSS(unsigned Opcode);
768bool isVPMOVW2M(unsigned Opcode);
769bool isVPSHUFB(unsigned Opcode);
770bool isVMULSD(unsigned Opcode);
771bool isVPERMI2W(unsigned Opcode);
772bool isVREDUCESS(unsigned Opcode);
773bool isFST(unsigned Opcode);
774bool isVPHSUBW(unsigned Opcode);
775bool isFRNDINT(unsigned Opcode);
776bool isSHR(unsigned Opcode);
777bool isLOOPNE(unsigned Opcode);
778bool isVCVTTPH2UQQ(unsigned Opcode);
779bool isSHA1NEXTE(unsigned Opcode);
780bool isVFMADD132SD(unsigned Opcode);
781bool isPSRAW(unsigned Opcode);
782bool isVPBROADCASTQ(unsigned Opcode);
783bool isCLC(unsigned Opcode);
784bool isPOPAW(unsigned Opcode);
785bool isTCMMIMFP16PS(unsigned Opcode);
786bool isVCVTQQ2PH(unsigned Opcode);
787bool isVCVTTPS2UQQ(unsigned Opcode);
788bool isVMOVUPD(unsigned Opcode);
789bool isFPTAN(unsigned Opcode);
790bool isVMASKMOVPD(unsigned Opcode);
791bool isVMOVLHPS(unsigned Opcode);
792bool isAESKEYGENASSIST(unsigned Opcode);
793bool isXSAVEOPT64(unsigned Opcode);
794bool isXSAVEC(unsigned Opcode);
795bool isVPLZCNTQ(unsigned Opcode);
796bool isVPSUBW(unsigned Opcode);
797bool isCMPCCXADD(unsigned Opcode);
798bool isVFMSUBADD213PH(unsigned Opcode);
799bool isVFMADDSUBPD(unsigned Opcode);
800bool isVPMINSW(unsigned Opcode);
801bool isVFNMSUB132PS(unsigned Opcode);
802bool isVMOVAPS(unsigned Opcode);
803bool isVPEXTRQ(unsigned Opcode);
804bool isVSCALEFSH(unsigned Opcode);
805bool isVCVTPD2PS(unsigned Opcode);
806bool isCLGI(unsigned Opcode);
807bool isVAESDEC(unsigned Opcode);
808bool isPFMUL(unsigned Opcode);
809bool isVCVTBIASPH2BF8S(unsigned Opcode);
810bool isMOVDIRI(unsigned Opcode);
811bool isSHUFPS(unsigned Opcode);
812bool isVFNMSUB231SS(unsigned Opcode);
813bool isVMWRITE(unsigned Opcode);
814bool isVINSERTF128(unsigned Opcode);
815bool isFISUBR(unsigned Opcode);
816bool isVINSERTI32X4(unsigned Opcode);
817bool isVPSLLDQ(unsigned Opcode);
818bool isPOPCNT(unsigned Opcode);
819bool isVXORPD(unsigned Opcode);
820bool isXLATB(unsigned Opcode);
821bool isDIV(unsigned Opcode);
822bool isVPSHLDVQ(unsigned Opcode);
823bool isMOVDDUP(unsigned Opcode);
824bool isVMOVDQU64(unsigned Opcode);
825bool isVPCOMPRESSQ(unsigned Opcode);
826bool isVFMSUBADD132PD(unsigned Opcode);
827bool isVPERMILPD(unsigned Opcode);
828bool isADDSD(unsigned Opcode);
829bool isBLENDPD(unsigned Opcode);
830bool isVPANDQ(unsigned Opcode);
831bool isPMADDUBSW(unsigned Opcode);
832bool isPOPFD(unsigned Opcode);
833bool isCMPSW(unsigned Opcode);
834bool isLDMXCSR(unsigned Opcode);
835bool isVMULPS(unsigned Opcode);
836bool isVROUNDSD(unsigned Opcode);
837bool isVFMADD132PD(unsigned Opcode);
838bool isVPSRAQ(unsigned Opcode);
839bool isVCOMISD(unsigned Opcode);
840bool isVCVTBIASPH2BF8(unsigned Opcode);
841bool isFFREEP(unsigned Opcode);
842bool isVFNMADD213PD(unsigned Opcode);
843bool isVCMPPD(unsigned Opcode);
844bool isVFNMSUB132PH(unsigned Opcode);
845bool isVPHADDBW(unsigned Opcode);
846bool isVPPERM(unsigned Opcode);
847bool isVCVTPS2PD(unsigned Opcode);
848bool isCBW(unsigned Opcode);
849bool isVMOVUPS(unsigned Opcode);
850bool isVPMAXUQ(unsigned Opcode);
851bool isWRSSQ(unsigned Opcode);
852bool isPACKUSDW(unsigned Opcode);
853bool isVCVTTBF162IBS(unsigned Opcode);
854bool isXBEGIN(unsigned Opcode);
855bool isVCVTPD2UQQ(unsigned Opcode);
856bool isFCMOVB(unsigned Opcode);
857bool isNOP(unsigned Opcode);
858bool isVPABSQ(unsigned Opcode);
859bool isVTESTPS(unsigned Opcode);
860bool isPHSUBW(unsigned Opcode);
861bool isPUSH2P(unsigned Opcode);
862bool isFISTTP(unsigned Opcode);
863bool isCFCMOVCC(unsigned Opcode);
864bool isPCMPESTRM(unsigned Opcode);
865bool isVPINSRD(unsigned Opcode);
866bool isVFNMSUB213PS(unsigned Opcode);
867bool isPHSUBD(unsigned Opcode);
868bool isSLDT(unsigned Opcode);
869bool isVCVTTPD2DQS(unsigned Opcode);
870bool isVPMINSD(unsigned Opcode);
871bool isVHADDPS(unsigned Opcode);
872bool isVMOVNTDQ(unsigned Opcode);
873bool isVFRCZSD(unsigned Opcode);
874bool isIBHF(unsigned Opcode);
875bool isVPTESTMW(unsigned Opcode);
876bool isVPMOVZXWD(unsigned Opcode);
877bool isPSADBW(unsigned Opcode);
878bool isVCVTSD2SI(unsigned Opcode);
879bool isVMAXPH(unsigned Opcode);
880bool isLODSB(unsigned Opcode);
881bool isPHMINPOSUW(unsigned Opcode);
882bool isVPROLVD(unsigned Opcode);
883bool isWRFSBASE(unsigned Opcode);
884bool isVRSQRT14PS(unsigned Opcode);
885bool isVPHSUBDQ(unsigned Opcode);
886bool isIRETD(unsigned Opcode);
887bool isVMOVRSD(unsigned Opcode);
888bool isVPMULHRSW(unsigned Opcode);
889bool isCVTSI2SS(unsigned Opcode);
890bool isPI2FD(unsigned Opcode);
891bool isGF2P8AFFINEQB(unsigned Opcode);
892bool isPAND(unsigned Opcode);
893bool isVFNMSUB231SH(unsigned Opcode);
894bool isVMOVHLPS(unsigned Opcode);
895bool isKNOTD(unsigned Opcode);
896bool isPEXTRB(unsigned Opcode);
897bool isVCVTPH2BF8(unsigned Opcode);
898bool isVMMCALL(unsigned Opcode);
899bool isVCVTSH2SS(unsigned Opcode);
900bool isVPUNPCKLQDQ(unsigned Opcode);
901bool isVPERMIL2PS(unsigned Opcode);
902bool isVPCMPGTD(unsigned Opcode);
903bool isCMPXCHG16B(unsigned Opcode);
904bool isTDPHF8PS(unsigned Opcode);
905bool isVZEROUPPER(unsigned Opcode);
906bool isMOVAPS(unsigned Opcode);
907bool isRMPOPT(unsigned Opcode);
908bool isFUCOMPP(unsigned Opcode);
909bool isVPCMPW(unsigned Opcode);
910bool isXSETBV(unsigned Opcode);
911bool isSLWPCB(unsigned Opcode);
912bool isSCASW(unsigned Opcode);
913bool isFCMOVNE(unsigned Opcode);
914bool isPBNDKB(unsigned Opcode);
915bool isVPMULLD(unsigned Opcode);
916bool isVP4DPWSSDS(unsigned Opcode);
917bool isVCVT2PH2HF8(unsigned Opcode);
918bool isPINSRW(unsigned Opcode);
919bool isVCVTSI2SH(unsigned Opcode);
920bool isVINSERTF32X8(unsigned Opcode);
921bool isKSHIFTLB(unsigned Opcode);
922bool isSEAMOPS(unsigned Opcode);
923bool isVPMOVSQB(unsigned Opcode);
924bool isVPMULUDQ(unsigned Opcode);
925bool isVPTESTMD(unsigned Opcode);
926bool isVPHADDDQ(unsigned Opcode);
927bool isKUNPCKDQ(unsigned Opcode);
928bool isT1MSKC(unsigned Opcode);
929bool isVBLENDPS(unsigned Opcode);
930bool isVPCOMB(unsigned Opcode);
931bool isPTWRITE(unsigned Opcode);
932bool isVCVTPH2BF8S(unsigned Opcode);
933bool isCVTPS2PI(unsigned Opcode);
934bool isVPROTD(unsigned Opcode);
935bool isCALL(unsigned Opcode);
936bool isTILELOADDRST1(unsigned Opcode);
937bool isVPERMPS(unsigned Opcode);
938bool isVPSHUFBITQMB(unsigned Opcode);
939bool isVMOVSLDUP(unsigned Opcode);
940bool isINVLPGA(unsigned Opcode);
941bool isVCVTPH2QQ(unsigned Opcode);
942bool isADD(unsigned Opcode);
943bool isPSUBSW(unsigned Opcode);
944bool isSIDTW(unsigned Opcode);
945bool isVEXTRACTF64X2(unsigned Opcode);
946bool isVFNMADD231PH(unsigned Opcode);
947bool isFCOMI(unsigned Opcode);
948bool isRSM(unsigned Opcode);
949bool isVPCOMUD(unsigned Opcode);
950bool isVPMOVZXBQ(unsigned Opcode);
951bool isUWRMSR(unsigned Opcode);
952bool isLGS(unsigned Opcode);
953bool isVMOVNTPD(unsigned Opcode);
954bool isPCMPESTRMQ(unsigned Opcode);
955bool isRDPRU(unsigned Opcode);
956bool isVPUNPCKHBW(unsigned Opcode);
957bool isVUCOMXSD(unsigned Opcode);
958bool isANDN(unsigned Opcode);
959bool isVCVTTPH2UW(unsigned Opcode);
960bool isVMFUNC(unsigned Opcode);
961bool isFIMUL(unsigned Opcode);
962bool isBLCFILL(unsigned Opcode);
963bool isVGATHERPF0DPS(unsigned Opcode);
964bool isVFMSUBADD231PS(unsigned Opcode);
965bool isVREDUCESD(unsigned Opcode);
966bool isVCOMXSH(unsigned Opcode);
967bool isVXORPS(unsigned Opcode);
968bool isPSWAPD(unsigned Opcode);
969bool isPMAXSD(unsigned Opcode);
970bool isVCMPSS(unsigned Opcode);
971bool isEXTRACTPS(unsigned Opcode);
972bool isVPMOVZXBD(unsigned Opcode);
973bool isOUTSW(unsigned Opcode);
974bool isKORTESTB(unsigned Opcode);
975bool isVREDUCEPS(unsigned Opcode);
976bool isPEXTRW(unsigned Opcode);
977bool isFNINIT(unsigned Opcode);
978bool isVCVTPH2IBS(unsigned Opcode);
979bool isROL(unsigned Opcode);
980bool isVCVTPS2QQ(unsigned Opcode);
981bool isVGETMANTPH(unsigned Opcode);
982bool isPUNPCKLDQ(unsigned Opcode);
983bool isPADDD(unsigned Opcode);
984bool isVPSLLD(unsigned Opcode);
985bool isPFCMPGE(unsigned Opcode);
986bool isVGETMANTBF16(unsigned Opcode);
987bool isVSUBBF16(unsigned Opcode);
988bool isVPMOVM2D(unsigned Opcode);
989bool isVCVTTSS2USIS(unsigned Opcode);
990bool isVHSUBPS(unsigned Opcode);
991bool isENDBR32(unsigned Opcode);
992bool isMOVSXD(unsigned Opcode);
993bool isPSIGND(unsigned Opcode);
994bool isVPTEST(unsigned Opcode);
995bool isVPDPWUSD(unsigned Opcode);
996bool isHSUBPD(unsigned Opcode);
997bool isADCX(unsigned Opcode);
998bool isCVTTPD2PI(unsigned Opcode);
999bool isPDEP(unsigned Opcode);
1000bool isTDPBUSD(unsigned Opcode);
1001bool isVCVTBIASPH2HF8S(unsigned Opcode);
1002bool isVBROADCASTI32X4(unsigned Opcode);
1003bool isVCVTPH2UDQ(unsigned Opcode);
1004bool isVPHADDW(unsigned Opcode);
1005bool isFLDL2E(unsigned Opcode);
1006bool isCLZERO(unsigned Opcode);
1007bool isPBLENDW(unsigned Opcode);
1008bool isVCVTBF162IUBS(unsigned Opcode);
1009bool isVCVTSH2USI(unsigned Opcode);
1010bool isVANDPD(unsigned Opcode);
1011bool isBEXTR(unsigned Opcode);
1012bool isSTD(unsigned Opcode);
1013bool isVAESKEYGENASSIST(unsigned Opcode);
1014bool isCMPSD(unsigned Opcode);
1015bool isMOVSS(unsigned Opcode);
1016bool isVCVTUQQ2PD(unsigned Opcode);
1017bool isVEXTRACTI32X4(unsigned Opcode);
1018bool isFLDCW(unsigned Opcode);
1019bool isINSW(unsigned Opcode);
1020bool isRDPID(unsigned Opcode);
1021bool isVUCOMXSS(unsigned Opcode);
1022bool isKANDQ(unsigned Opcode);
1023bool isV4FMADDPS(unsigned Opcode);
1024bool isPMOVZXWQ(unsigned Opcode);
1025bool isVFPCLASSSD(unsigned Opcode);
1026bool isBLENDPS(unsigned Opcode);
1027bool isVPACKSSDW(unsigned Opcode);
1028bool isVPHSUBBW(unsigned Opcode);
1029bool isVPINSRW(unsigned Opcode);
1030bool isVMINMAXBF16(unsigned Opcode);
1031bool isVSHUFF64X2(unsigned Opcode);
1032bool isVPACKUSWB(unsigned Opcode);
1033bool isVRSQRT28SS(unsigned Opcode);
1034bool isGETSEC(unsigned Opcode);
1035bool isFXAM(unsigned Opcode);
1036bool isVEXTRACTF64X4(unsigned Opcode);
1037bool isBLSR(unsigned Opcode);
1038bool isFILD(unsigned Opcode);
1039bool isRETFQ(unsigned Opcode);
1040bool isVADDSS(unsigned Opcode);
1041bool isCOMISS(unsigned Opcode);
1042bool isCLI(unsigned Opcode);
1043bool isVERW(unsigned Opcode);
1044bool isBTC(unsigned Opcode);
1045bool isVPHADDUBQ(unsigned Opcode);
1046bool isVPORQ(unsigned Opcode);
1047bool isORPD(unsigned Opcode);
1048bool isVMOVSS(unsigned Opcode);
1049bool isVPSUBD(unsigned Opcode);
1050bool isVGATHERPF1QPD(unsigned Opcode);
1051bool isENCODEKEY256(unsigned Opcode);
1052bool isGF2P8AFFINEINVQB(unsigned Opcode);
1053bool isXRSTOR64(unsigned Opcode);
1054bool isKANDW(unsigned Opcode);
1055bool isLODSQ(unsigned Opcode);
1056bool isVMOVRSW(unsigned Opcode);
1057bool isVSUBSH(unsigned Opcode);
1058bool isLSS(unsigned Opcode);
1059bool isPMOVSXBQ(unsigned Opcode);
1060bool isVCVTTSD2SIS(unsigned Opcode);
1061bool isVCMPSH(unsigned Opcode);
1062bool isVFMADD132PS(unsigned Opcode);
1063bool isVPACKSSWB(unsigned Opcode);
1064bool isPCMPGTQ(unsigned Opcode);
1065bool isVFMADD132SH(unsigned Opcode);
1066bool isVCVTUQQ2PH(unsigned Opcode);
1067bool isVCVTQQ2PS(unsigned Opcode);
1068bool isVCVTTSS2USI(unsigned Opcode);
1069bool isVPMOVM2Q(unsigned Opcode);
1070bool isVMOVD(unsigned Opcode);
1071bool isVCVTTPS2QQS(unsigned Opcode);
1072bool isVSQRTBF16(unsigned Opcode);
1073bool isVFPCLASSPH(unsigned Opcode);
1074bool isVCVTSS2SH(unsigned Opcode);
1075bool isSCASB(unsigned Opcode);
1076bool isPSRLD(unsigned Opcode);
1077bool isVADDPH(unsigned Opcode);
1078bool isFSUB(unsigned Opcode);
1079bool isVCVTTPH2IBS(unsigned Opcode);
1080bool isVEXTRACTI64X2(unsigned Opcode);
1081bool isVPSHLDD(unsigned Opcode);
1082bool isPMINUW(unsigned Opcode);
1083bool isPSUBSB(unsigned Opcode);
1084bool isVCVT2PS2PHX(unsigned Opcode);
1085bool isVPCMPEQD(unsigned Opcode);
1086bool isVPSCATTERQD(unsigned Opcode);
1087bool isKXNORB(unsigned Opcode);
1088bool isLDDQU(unsigned Opcode);
1089bool isMASKMOVQ(unsigned Opcode);
1090bool isPABSW(unsigned Opcode);
1091bool isVPCOMQ(unsigned Opcode);
1092bool isVPROLD(unsigned Opcode);
1093bool isVSCATTERDPD(unsigned Opcode);
1094bool isFXRSTOR(unsigned Opcode);
1095bool isVPCMPUW(unsigned Opcode);
1096bool isWBINVD(unsigned Opcode);
1097bool isVCVTTPD2UDQ(unsigned Opcode);
1098bool isERETU(unsigned Opcode);
1099bool isPFRCPIT2(unsigned Opcode);
1100bool isVPERMT2W(unsigned Opcode);
1101bool isVEXTRACTF32X4(unsigned Opcode);
1102bool isVGATHERPF0DPD(unsigned Opcode);
1103bool isVBROADCASTF32X2(unsigned Opcode);
1104bool isVRCP14SD(unsigned Opcode);
1105bool isLAHF(unsigned Opcode);
1106bool isPABSD(unsigned Opcode);
1107bool isPINSRB(unsigned Opcode);
1108bool isSKINIT(unsigned Opcode);
1109bool isENTER(unsigned Opcode);
1110bool isVCVTSI2SS(unsigned Opcode);
1111bool isVFMADD231PD(unsigned Opcode);
1112bool isLOADIWKEY(unsigned Opcode);
1113bool isVMOVNTDQA(unsigned Opcode);
1114bool isVPERMT2PS(unsigned Opcode);
1115bool isPUSHF(unsigned Opcode);
1116bool isMPSADBW(unsigned Opcode);
1117bool isVMINMAXSH(unsigned Opcode);
1118bool isVRSQRT14SS(unsigned Opcode);
1119bool isVCVTDQ2PD(unsigned Opcode);
1120bool isVORPS(unsigned Opcode);
1121bool isVPEXPANDQ(unsigned Opcode);
1122bool isVPSHRDD(unsigned Opcode);
1123bool isTDPBSSD(unsigned Opcode);
1124bool isTESTUI(unsigned Opcode);
1125bool isVFMADDPD(unsigned Opcode);
1126bool isVPANDND(unsigned Opcode);
1127bool isVPMOVSDB(unsigned Opcode);
1128bool isVPBROADCASTB(unsigned Opcode);
1129bool isCVTPI2PD(unsigned Opcode);
1130bool isVPERMI2B(unsigned Opcode);
1131bool isVPMINSB(unsigned Opcode);
1132bool isLAR(unsigned Opcode);
1133bool isINVLPGB(unsigned Opcode);
1134bool isTLBSYNC(unsigned Opcode);
1135bool isFDIVP(unsigned Opcode);
1136bool isVPSRLW(unsigned Opcode);
1137bool isVRCP28SS(unsigned Opcode);
1138bool isVMOVHPS(unsigned Opcode);
1139bool isVPMACSSDD(unsigned Opcode);
1140bool isPEXT(unsigned Opcode);
1141bool isVMAXBF16(unsigned Opcode);
1142bool isVRSQRT14SD(unsigned Opcode);
1143bool isVPDPWSSD(unsigned Opcode);
1144bool isVFMSUB231SD(unsigned Opcode);
1145bool isVPMOVZXWQ(unsigned Opcode);
1146bool isXORPD(unsigned Opcode);
1147bool isVMOVDQA(unsigned Opcode);
1148bool isVFNMSUB213SD(unsigned Opcode);
1149bool isVMINPS(unsigned Opcode);
1150bool isVFMSUB231PS(unsigned Opcode);
1151bool isVPCOMPRESSB(unsigned Opcode);
1152bool isVPCMPEQQ(unsigned Opcode);
1153bool isVRCPSS(unsigned Opcode);
1154bool isVSCATTERPF1DPS(unsigned Opcode);
1155bool isVPHADDUBW(unsigned Opcode);
1156bool isVSUBPD(unsigned Opcode);
1157bool isVPSCATTERQQ(unsigned Opcode);
1158bool isVCVTW2PH(unsigned Opcode);
1159bool isVFMADDCPH(unsigned Opcode);
1160bool isVPACKUSDW(unsigned Opcode);
1161bool isVSCALEFSS(unsigned Opcode);
1162bool isAESIMC(unsigned Opcode);
1163bool isVRCP28PS(unsigned Opcode);
1164bool isAAND(unsigned Opcode);
1165bool isDAA(unsigned Opcode);
1166bool isKTESTW(unsigned Opcode);
1167bool isVCVTPD2UDQ(unsigned Opcode);
1168bool isVPADDQ(unsigned Opcode);
1169bool isPALIGNR(unsigned Opcode);
1170bool isPMAXUW(unsigned Opcode);
1171bool isVFMADDSD(unsigned Opcode);
1172bool isPFMAX(unsigned Opcode);
1173bool isVPOR(unsigned Opcode);
1174bool isVPSUBB(unsigned Opcode);
1175bool isVPAVGB(unsigned Opcode);
1176bool isINSB(unsigned Opcode);
1177bool isFYL2X(unsigned Opcode);
1178bool isVFNMSUB132PD(unsigned Opcode);
1179bool isVFNMSUBPS(unsigned Opcode);
1180bool isVFMADD231PS(unsigned Opcode);
1181bool isVCVTTSS2SI(unsigned Opcode);
1182bool isTCMMRLFP16PS(unsigned Opcode);
1183bool isFCOMPP(unsigned Opcode);
1184bool isMOVD(unsigned Opcode);
1185bool isMOVBE(unsigned Opcode);
1186bool isVP2INTERSECTD(unsigned Opcode);
1187bool isVPMULLQ(unsigned Opcode);
1188bool isVSCALEFPS(unsigned Opcode);
1189bool isVPMACSDQH(unsigned Opcode);
1190bool isVPTESTNMD(unsigned Opcode);
1191bool isFCOMP(unsigned Opcode);
1192bool isPREFETCHWT1(unsigned Opcode);
1193bool isVCMPSD(unsigned Opcode);
1194bool isSGDTD(unsigned Opcode);
1195bool isWRUSSD(unsigned Opcode);
1196bool isFSUBP(unsigned Opcode);
1197bool isVUNPCKLPS(unsigned Opcode);
1198bool isVBMACXOR16X16X16(unsigned Opcode);
1199bool isVFNMSUB213SS(unsigned Opcode);
1200bool isROUNDPD(unsigned Opcode);
1201bool isVPMAXSW(unsigned Opcode);
1202bool isVCVTTPH2DQ(unsigned Opcode);
1203bool isVPUNPCKLWD(unsigned Opcode);
1204bool isKSHIFTLD(unsigned Opcode);
1205bool isTCVTROWPS2BF16H(unsigned Opcode);
1206bool isVFMADD231SD(unsigned Opcode);
1207bool isADDPS(unsigned Opcode);
1208bool isVPSLLVD(unsigned Opcode);
1209bool isVFNMADD132SH(unsigned Opcode);
1210bool isVMOVNTPS(unsigned Opcode);
1211bool isVCVTPD2DQ(unsigned Opcode);
1212bool isVPXOR(unsigned Opcode);
1213bool isSTMXCSR(unsigned Opcode);
1214bool isVRCP14SS(unsigned Opcode);
1215bool isUD2(unsigned Opcode);
1216bool isVPOPCNTW(unsigned Opcode);
1217bool isVRSQRTSH(unsigned Opcode);
1218bool isVSCATTERPF0DPD(unsigned Opcode);
1219bool isVFMADDPS(unsigned Opcode);
1220bool isXSAVEC64(unsigned Opcode);
1221bool isVPMADDUBSW(unsigned Opcode);
1222bool isVPMOVZXDQ(unsigned Opcode);
1223bool isVRCP14PS(unsigned Opcode);
1224bool isVSQRTSH(unsigned Opcode);
1225bool isTCVTROWD2PS(unsigned Opcode);
1226bool isLOOP(unsigned Opcode);
1227bool isSTUI(unsigned Opcode);
1228bool isVCVTTPS2UDQ(unsigned Opcode);
1229bool isXABORT(unsigned Opcode);
1230bool isVCOMPRESSPS(unsigned Opcode);
1231bool isVCVTTBF162IUBS(unsigned Opcode);
1232bool isVPADDW(unsigned Opcode);
1233bool isVPSIGND(unsigned Opcode);
1234bool isVRNDSCALEPS(unsigned Opcode);
1235bool isVPHADDUWD(unsigned Opcode);
1236bool isVCVT2PH2HF8S(unsigned Opcode);
1237bool isVDBPSADBW(unsigned Opcode);
1238bool isPSLLW(unsigned Opcode);
1239bool isVPMOVQD(unsigned Opcode);
1240bool isVINSERTI64X4(unsigned Opcode);
1241bool isVPERMI2PS(unsigned Opcode);
1242bool isVMULPH(unsigned Opcode);
1243bool isVPCMPUQ(unsigned Opcode);
1244bool isVCVTUSI2SD(unsigned Opcode);
1245bool isKXNORW(unsigned Opcode);
1246bool isBLCIC(unsigned Opcode);
1247bool isVFNMADD213SD(unsigned Opcode);
1248bool isVMOVLPS(unsigned Opcode);
1249bool isVPMACSWW(unsigned Opcode);
1250bool isPCONFIG(unsigned Opcode);
1251bool isPANDN(unsigned Opcode);
1252bool isVGETEXPPD(unsigned Opcode);
1253bool isVPSRLVQ(unsigned Opcode);
1254bool isUD1(unsigned Opcode);
1255bool isPMAXSB(unsigned Opcode);
1256bool isVPROLQ(unsigned Opcode);
1257bool isVPSRLD(unsigned Opcode);
1258bool isVSCATTERPF1QPD(unsigned Opcode);
1259bool isINT3(unsigned Opcode);
1260bool isXRSTORS64(unsigned Opcode);
1261bool isCVTSD2SI(unsigned Opcode);
1262bool isVMAXSS(unsigned Opcode);
1263bool isVPMINUB(unsigned Opcode);
1264bool isKXNORQ(unsigned Opcode);
1265bool isFLD(unsigned Opcode);
1266bool isVSHUFI32X4(unsigned Opcode);
1267bool isSAHF(unsigned Opcode);
1268bool isPFRSQRT(unsigned Opcode);
1269bool isSHRD(unsigned Opcode);
1270bool isSYSEXIT(unsigned Opcode);
1271bool isXSAVE64(unsigned Opcode);
1272bool isVPMAXSD(unsigned Opcode);
1273bool isCVTTSD2SI(unsigned Opcode);
1274bool isVCVTTSS2SIS(unsigned Opcode);
1275bool isPMOVMSKB(unsigned Opcode);
1276bool isVRANGEPS(unsigned Opcode);
1277bool isVADDSUBPS(unsigned Opcode);
1278bool isVBROADCASTI128(unsigned Opcode);
1279bool isPADDUSB(unsigned Opcode);
1280bool isENCODEKEY128(unsigned Opcode);
1281bool isOR(unsigned Opcode);
1282bool isSTOSW(unsigned Opcode);
1283bool isVCVTTPD2UQQS(unsigned Opcode);
1284bool isPAVGW(unsigned Opcode);
1285bool isVCVTPD2PH(unsigned Opcode);
1286bool isSHLX(unsigned Opcode);
1287bool isVCVTSH2SD(unsigned Opcode);
1288bool isVFMADD231SS(unsigned Opcode);
1289bool isMOVNTSD(unsigned Opcode);
1290bool isFLDPI(unsigned Opcode);
1291bool isVCVTUSI2SS(unsigned Opcode);
1292bool isPMOVSXBD(unsigned Opcode);
1293bool isVPRORVQ(unsigned Opcode);
1294bool isVPERMT2D(unsigned Opcode);
1295bool isADDSS(unsigned Opcode);
1296bool isAADD(unsigned Opcode);
1297bool isVPSRLVW(unsigned Opcode);
1298bool isVRSQRTPH(unsigned Opcode);
1299bool isVLDDQU(unsigned Opcode);
1300bool isKMOVD(unsigned Opcode);
1301bool isENCLV(unsigned Opcode);
1302bool isENCLU(unsigned Opcode);
1303bool isPREFETCHT1(unsigned Opcode);
1304bool isRSQRTPS(unsigned Opcode);
1305bool isVCVTTSH2USI(unsigned Opcode);
1306bool isPADDB(unsigned Opcode);
1307bool isVMASKMOVDQU(unsigned Opcode);
1308bool isPUNPCKLBW(unsigned Opcode);
1309bool isMOV(unsigned Opcode);
1310bool isVCVTTPH2IUBS(unsigned Opcode);
1311bool isMUL(unsigned Opcode);
1312bool isRCL(unsigned Opcode);
1313bool isVRCPSH(unsigned Opcode);
1314bool isPFCMPEQ(unsigned Opcode);
1315bool isMONITOR(unsigned Opcode);
1316bool isFDIVR(unsigned Opcode);
1317bool isPFRCP(unsigned Opcode);
1318bool isPMINSD(unsigned Opcode);
1319bool isVSHUFF32X4(unsigned Opcode);
1320bool isKTESTQ(unsigned Opcode);
1321bool isVCVTTPD2DQ(unsigned Opcode);
1322bool isVPSLLVW(unsigned Opcode);
1323bool isTDPBSUD(unsigned Opcode);
1324bool isVPMINUQ(unsigned Opcode);
1325bool isFIADD(unsigned Opcode);
1326bool isFCMOVNU(unsigned Opcode);
1327bool isVHSUBPD(unsigned Opcode);
1328bool isKSHIFTRQ(unsigned Opcode);
1329bool isMOVUPS(unsigned Opcode);
1330bool isVMCALL(unsigned Opcode);
1331bool isXADD(unsigned Opcode);
1332bool isXRSTOR(unsigned Opcode);
1333bool isVGATHERPF1DPD(unsigned Opcode);
1334bool isRCR(unsigned Opcode);
1335bool isFNSTCW(unsigned Opcode);
1336bool isVPMOVSDW(unsigned Opcode);
1337bool isVFMSUB132SH(unsigned Opcode);
1338bool isVPCONFLICTQ(unsigned Opcode);
1339bool isSWAPGS(unsigned Opcode);
1340bool isVPMOVQ2M(unsigned Opcode);
1341bool isVPSRAVW(unsigned Opcode);
1342bool isSHA256MSG2(unsigned Opcode);
1343bool isDIVSD(unsigned Opcode);
1344bool isPCMPGTB(unsigned Opcode);
1345bool isMOVDQA(unsigned Opcode);
1346bool isVAESENCLAST(unsigned Opcode);
1347bool isKXORW(unsigned Opcode);
1348bool isLIDTW(unsigned Opcode);
1349bool isPMULHW(unsigned Opcode);
1350bool isVINSERTI32X8(unsigned Opcode);
1351bool isVRCPPS(unsigned Opcode);
1352bool isVRSQRTBF16(unsigned Opcode);
1353bool isVGATHERQPS(unsigned Opcode);
1354bool isCTESTCC(unsigned Opcode);
1355bool isPMADDWD(unsigned Opcode);
1356bool isUCOMISS(unsigned Opcode);
1357bool isXGETBV(unsigned Opcode);
1358bool isVCVTPD2QQ(unsigned Opcode);
1359bool isVGETEXPPS(unsigned Opcode);
1360bool isFISTP(unsigned Opcode);
1361bool isVINSERTF64X4(unsigned Opcode);
1362bool isVMOVDQU16(unsigned Opcode);
1363bool isVFMADD132PH(unsigned Opcode);
1364bool isVFMSUBADD213PS(unsigned Opcode);
1365bool isVMOVDQU32(unsigned Opcode);
1366bool isFUCOM(unsigned Opcode);
1367bool isVFNMADD213BF16(unsigned Opcode);
1368bool isHADDPS(unsigned Opcode);
1369bool isCMP(unsigned Opcode);
1370bool isCVTTPS2PI(unsigned Opcode);
1371bool isIRETQ(unsigned Opcode);
1372bool isPF2IW(unsigned Opcode);
1373bool isPSHUFD(unsigned Opcode);
1374bool isVDPPD(unsigned Opcode);
1375bool isPSHUFHW(unsigned Opcode);
1376bool isRMPADJUST(unsigned Opcode);
1377bool isPI2FW(unsigned Opcode);
1378bool isVCVTTPH2QQ(unsigned Opcode);
1379bool isDIVPD(unsigned Opcode);
1380bool isCLFLUSH(unsigned Opcode);
1381bool isVPMINUW(unsigned Opcode);
1382bool isIN(unsigned Opcode);
1383bool isWRPKRU(unsigned Opcode);
1384bool isINSERTPS(unsigned Opcode);
1385bool isAAM(unsigned Opcode);
1386bool isVPHADDUDQ(unsigned Opcode);
1387bool isVSHA512MSG1(unsigned Opcode);
1388bool isDIVPS(unsigned Opcode);
1389bool isKNOTB(unsigned Opcode);
1390bool isBLSFILL(unsigned Opcode);
1391bool isVPCMPGTQ(unsigned Opcode);
1392bool isMINSD(unsigned Opcode);
1393bool isFPREM(unsigned Opcode);
1394bool isVPUNPCKHQDQ(unsigned Opcode);
1395bool isMINPD(unsigned Opcode);
1396bool isVCVTTPD2QQ(unsigned Opcode);
1397bool isVFMSUBPD(unsigned Opcode);
1398bool isV4FMADDSS(unsigned Opcode);
1399bool isCPUID(unsigned Opcode);
1400bool isSETCC(unsigned Opcode);
1401bool isVPDPWUUD(unsigned Opcode);
1402bool isVCVTTPS2IUBS(unsigned Opcode);
1403bool isPMOVSXDQ(unsigned Opcode);
1404bool isMWAIT(unsigned Opcode);
1405bool isVPEXTRB(unsigned Opcode);
1406bool isRMPCHKD(unsigned Opcode);
1407bool isINVVPID(unsigned Opcode);
1408bool isVPSHUFD(unsigned Opcode);
1409bool isVMINBF16(unsigned Opcode);
1410bool isMOVLPS(unsigned Opcode);
1411bool isVBLENDMPS(unsigned Opcode);
1412bool isPMULLW(unsigned Opcode);
1413bool isVCVTSH2SI(unsigned Opcode);
1414bool isVPMOVSXWQ(unsigned Opcode);
1415bool isFNSTENV(unsigned Opcode);
1416bool isVCVT2PH2BF8(unsigned Opcode);
1417bool isVPERMI2PD(unsigned Opcode);
1418bool isMAXSS(unsigned Opcode);
1419bool isCWDE(unsigned Opcode);
1420bool isVBROADCASTI32X8(unsigned Opcode);
1421bool isINT(unsigned Opcode);
1422bool isENCLS(unsigned Opcode);
1423bool isMOVNTQ(unsigned Opcode);
1424bool isVDIVSH(unsigned Opcode);
1425bool isMOVHLPS(unsigned Opcode);
1426bool isVPMASKMOVD(unsigned Opcode);
1427bool isVMOVSD(unsigned Opcode);
1428bool isVPMINUD(unsigned Opcode);
1429bool isVPCMPISTRM(unsigned Opcode);
1430bool isVGETMANTSD(unsigned Opcode);
1431bool isKSHIFTRW(unsigned Opcode);
1432bool isAESDECLAST(unsigned Opcode);
1433bool isVPTESTMB(unsigned Opcode);
1434bool isVFNMSUB231BF16(unsigned Opcode);
1435bool isVMPTRST(unsigned Opcode);
1436bool isLLDT(unsigned Opcode);
1437bool isMOVSB(unsigned Opcode);
1438bool isTILELOADD(unsigned Opcode);
1439bool isKTESTB(unsigned Opcode);
1440bool isMOVUPD(unsigned Opcode);
1441bool isLKGS(unsigned Opcode);
1442bool isSGDTW(unsigned Opcode);
1443bool isDIVSS(unsigned Opcode);
1444bool isPUNPCKHQDQ(unsigned Opcode);
1445bool isVFMADD213SD(unsigned Opcode);
1446bool isKXORD(unsigned Opcode);
1447bool isVPMOVB2M(unsigned Opcode);
1448bool isVMREAD(unsigned Opcode);
1449bool isVPDPWSSDS(unsigned Opcode);
1450bool isTILERELEASE(unsigned Opcode);
1451bool isVUCOMXSH(unsigned Opcode);
1452bool isCLFLUSHOPT(unsigned Opcode);
1453bool isDAS(unsigned Opcode);
1454bool isVSCALEFPH(unsigned Opcode);
1455bool isVSUBSD(unsigned Opcode);
1456bool isVCOMISS(unsigned Opcode);
1457bool isVMULBF16(unsigned Opcode);
1458bool isORPS(unsigned Opcode);
1459bool isTDPFP16PS(unsigned Opcode);
1460bool isVMAXPD(unsigned Opcode);
1461bool isVPMOVWB(unsigned Opcode);
1462bool isVEXP2PS(unsigned Opcode);
1463bool isVPGATHERDQ(unsigned Opcode);
1464bool isVPSRAVQ(unsigned Opcode);
1465bool isPCMPISTRI(unsigned Opcode);
1466bool isVFMSUB231PD(unsigned Opcode);
1467bool isRDMSR(unsigned Opcode);
1468bool isKORTESTD(unsigned Opcode);
1469bool isVPBLENDMW(unsigned Opcode);
1470bool isPSHUFB(unsigned Opcode);
1471bool isVDPBF16PS(unsigned Opcode);
1472bool isTDPBF16PS(unsigned Opcode);
1473bool isFCMOVE(unsigned Opcode);
1474bool isVFMADD231BF16(unsigned Opcode);
1475bool isCMPSS(unsigned Opcode);
1476bool isMASKMOVDQU(unsigned Opcode);
1477bool isSARX(unsigned Opcode);
1478bool isVPDPWUSDS(unsigned Opcode);
1479bool isSGDT(unsigned Opcode);
1480bool isVFMULCPH(unsigned Opcode);
1481bool isURDMSR(unsigned Opcode);
1482bool isKUNPCKWD(unsigned Opcode);
1483bool isVSCALEFBF16(unsigned Opcode);
1484bool isCVTPS2PD(unsigned Opcode);
1485bool isFBSTP(unsigned Opcode);
1486bool isPSUBQ(unsigned Opcode);
1487bool isFXSAVE64(unsigned Opcode);
1488bool isKMOVW(unsigned Opcode);
1489bool isBTS(unsigned Opcode);
1490bool isVPHADDBQ(unsigned Opcode);
1491bool isFRSTOR(unsigned Opcode);
1492bool isVFMSUB132PD(unsigned Opcode);
1493bool isPMULLD(unsigned Opcode);
1494bool isSHA1MSG2(unsigned Opcode);
1495bool isJECXZ(unsigned Opcode);
1496bool isVCVTUDQ2PS(unsigned Opcode);
1497bool isAESENC(unsigned Opcode);
1498bool isVMINMAXPS(unsigned Opcode);
1499bool isPSIGNW(unsigned Opcode);
1500bool isUNPCKLPD(unsigned Opcode);
1501bool isPUSHP(unsigned Opcode);
1502bool isBLSI(unsigned Opcode);
1503bool isVPTESTNMB(unsigned Opcode);
1504bool isWRUSSQ(unsigned Opcode);
1505bool isVGF2P8MULB(unsigned Opcode);
1506bool isVPUNPCKLBW(unsigned Opcode);
1507bool isVRANGESD(unsigned Opcode);
1508bool isCLD(unsigned Opcode);
1509bool isVSCALEFPD(unsigned Opcode);
1510bool isVCOMXSS(unsigned Opcode);
1511bool isVPERMQ(unsigned Opcode);
1512bool isVPSHLDVW(unsigned Opcode);
1513bool isROR(unsigned Opcode);
1514bool isVFMADDSUB132PH(unsigned Opcode);
1515bool isDEC(unsigned Opcode);
1516bool isVGETEXPSH(unsigned Opcode);
1517bool isAESDEC(unsigned Opcode);
1518bool isKORD(unsigned Opcode);
1519bool isTILELOADDT1(unsigned Opcode);
1520bool isVPMULHW(unsigned Opcode);
1521bool isVMASKMOVPS(unsigned Opcode);
1522bool isPMOVZXDQ(unsigned Opcode);
1523bool isVCVTPS2PH(unsigned Opcode);
1524bool isCVTDQ2PD(unsigned Opcode);
1525bool isVCVTSD2SS(unsigned Opcode);
1526bool isVFMSUB213PH(unsigned Opcode);
1527bool isVPROTB(unsigned Opcode);
1528bool isPINSRD(unsigned Opcode);
1529bool isVMXON(unsigned Opcode);
1530bool isVFCMULCSH(unsigned Opcode);
1531bool isVFMULCSH(unsigned Opcode);
1532bool isVRANGEPD(unsigned Opcode);
1533bool isCMC(unsigned Opcode);
1534bool isVFNMADD231BF16(unsigned Opcode);
1535bool isSHA256MSG1(unsigned Opcode);
1536bool isFLD1(unsigned Opcode);
1537bool isCMPPS(unsigned Opcode);
1538bool isVPAVGW(unsigned Opcode);
1539bool isVFMADD213SH(unsigned Opcode);
1540bool isVPCMPESTRMQ(unsigned Opcode);
1541bool isVPINSRQ(unsigned Opcode);
1542bool isMOVABS(unsigned Opcode);
1543bool isVPSHAQ(unsigned Opcode);
1544bool isRDTSCP(unsigned Opcode);
1545bool isVFNMADD231SS(unsigned Opcode);
1546bool isTEST(unsigned Opcode);
1547bool isVPERMD(unsigned Opcode);
1548bool isVBCSTNESH2PS(unsigned Opcode);
1549bool isVGATHERPF0QPD(unsigned Opcode);
1550bool isVPERM2I128(unsigned Opcode);
1551bool isVMPSADBW(unsigned Opcode);
1552bool isVFNMSUB231PD(unsigned Opcode);
1553bool isPADDSB(unsigned Opcode);
1554bool isMWAITX(unsigned Opcode);
1555bool isMONITORX(unsigned Opcode);
1556bool isVPEXPANDD(unsigned Opcode);
1557bool isVFRCZPD(unsigned Opcode);
1558bool isVRCPPH(unsigned Opcode);
1559bool isFEMMS(unsigned Opcode);
1560bool isVSCATTERQPD(unsigned Opcode);
1561bool isVMOVW(unsigned Opcode);
1562bool isVPBROADCASTD(unsigned Opcode);
1563bool isSTOSB(unsigned Opcode);
1564bool isFUCOMI(unsigned Opcode);
1565bool isVBROADCASTI64X4(unsigned Opcode);
1566bool isFCMOVU(unsigned Opcode);
1567bool isPSHUFLW(unsigned Opcode);
1568bool isCVTPI2PS(unsigned Opcode);
1569bool isVCVTTPD2UDQS(unsigned Opcode);
1570bool isSYSCALL(unsigned Opcode);
1571bool isVFMADD231SH(unsigned Opcode);
1572bool isVPOPCNTB(unsigned Opcode);
1573bool isPMOVZXBW(unsigned Opcode);
1574bool isVCVTDQ2PS(unsigned Opcode);
1575bool isPSUBD(unsigned Opcode);
1576bool isVPCMPEQW(unsigned Opcode);
1577bool isMOVSW(unsigned Opcode);
1578bool isVSM3RNDS2(unsigned Opcode);
1579bool isVPMOVUSQD(unsigned Opcode);
1580bool isCVTTPD2DQ(unsigned Opcode);
1581bool isVPEXPANDW(unsigned Opcode);
1582bool isVUCOMISH(unsigned Opcode);
1583bool isVZEROALL(unsigned Opcode);
1584bool isVPAND(unsigned Opcode);
1585bool isPMULDQ(unsigned Opcode);
1586bool isVPSHUFHW(unsigned Opcode);
1587bool isVPALIGNR(unsigned Opcode);
1588bool isSQRTSD(unsigned Opcode);
1589bool isVCVTTPH2UDQ(unsigned Opcode);
1590bool isVGETEXPPH(unsigned Opcode);
1591bool isADDPD(unsigned Opcode);
1592bool isVFNMADDPD(unsigned Opcode);
1593bool isSTTILECFG(unsigned Opcode);
1594bool isVMINPD(unsigned Opcode);
1595bool isSHA1RNDS4(unsigned Opcode);
1596bool isPBLENDVB(unsigned Opcode);
1597bool isVBROADCASTF128(unsigned Opcode);
1598bool isVPSHRDQ(unsigned Opcode);
1599bool isVAESIMC(unsigned Opcode);
1600bool isCOMISD(unsigned Opcode);
1601bool isVMOVSH(unsigned Opcode);
1602bool isPFSUBR(unsigned Opcode);
1603bool isRDSSPD(unsigned Opcode);
1604bool isWAIT(unsigned Opcode);
1605bool isVFPCLASSSS(unsigned Opcode);
1606bool isPCMPGTD(unsigned Opcode);
1607bool isVGATHERPF0QPS(unsigned Opcode);
1608bool isBLENDVPS(unsigned Opcode);
1609bool isVBROADCASTF32X4(unsigned Opcode);
1610bool isVMOVLPD(unsigned Opcode);
1611bool isVMOVQ(unsigned Opcode);
1612bool isVPMADD52LUQ(unsigned Opcode);
1613bool isVMOVDQU(unsigned Opcode);
1614bool isAESENC128KL(unsigned Opcode);
1615bool isVFMADDSUB231PS(unsigned Opcode);
1616bool isVFNMSUB213PD(unsigned Opcode);
1617bool isVPCONFLICTD(unsigned Opcode);
1618bool isVFMADDSUB213PH(unsigned Opcode);
1619bool isVPHSUBSW(unsigned Opcode);
1620bool isPUNPCKHDQ(unsigned Opcode);
1621bool isVSHUFI64X2(unsigned Opcode);
1622bool isVFMSUBSD(unsigned Opcode);
1623bool isVPORD(unsigned Opcode);
1624bool isRCPPS(unsigned Opcode);
1625bool isVEXTRACTI128(unsigned Opcode);
1626bool isVCVT2PH2BF8S(unsigned Opcode);
1627bool isVPSHRDVW(unsigned Opcode);
1628bool isVUNPCKLPD(unsigned Opcode);
1629bool isVPSRAVD(unsigned Opcode);
1630bool isVMULSH(unsigned Opcode);
1631bool isMOVNTSS(unsigned Opcode);
1632bool isSTI(unsigned Opcode);
1633bool isVSM4RNDS4(unsigned Opcode);
1634bool isVMCLEAR(unsigned Opcode);
1635bool isVPMADD52HUQ(unsigned Opcode);
1636bool isLIDT(unsigned Opcode);
1637bool isPUSH2(unsigned Opcode);
1638bool isRDPKRU(unsigned Opcode);
1639bool isVCVTPS2IUBS(unsigned Opcode);
1640bool isXSAVES64(unsigned Opcode);
1641bool isVPCMPB(unsigned Opcode);
1642bool isVFMSUB231BF16(unsigned Opcode);
1643bool isFINCSTP(unsigned Opcode);
1644bool isKORQ(unsigned Opcode);
1645bool isRDPMC(unsigned Opcode);
1646bool isVEXTRACTF128(unsigned Opcode);
1647bool isMOVMSKPD(unsigned Opcode);
1648bool isVFMSUB231SH(unsigned Opcode);
1649bool isVPSHLB(unsigned Opcode);
1650bool isXCRYPTCBC(unsigned Opcode);
1651bool isSHL(unsigned Opcode);
1652bool isAXOR(unsigned Opcode);
1653bool isVINSERTI64X2(unsigned Opcode);
1654bool isSYSRETQ(unsigned Opcode);
1655bool isVSCATTERPF0QPD(unsigned Opcode);
1656bool isVFMSUB213SH(unsigned Opcode);
1657bool isVPMOVQW(unsigned Opcode);
1658bool isVREDUCEPD(unsigned Opcode);
1659bool isNOT(unsigned Opcode);
1660bool isLWPINS(unsigned Opcode);
1661bool isVSCATTERDPS(unsigned Opcode);
1662bool isVPMOVM2W(unsigned Opcode);
1663bool isVFNMADD132PS(unsigned Opcode);
1664bool isMOVNTPS(unsigned Opcode);
1665bool isVRSQRTSS(unsigned Opcode);
1666bool isKMOVB(unsigned Opcode);
1667bool isCVTSD2SS(unsigned Opcode);
1668bool isVBROADCASTF64X2(unsigned Opcode);
1669bool isVDIVBF16(unsigned Opcode);
1670bool isMOVNTPD(unsigned Opcode);
1671bool isMAXSD(unsigned Opcode);
1672bool isCMPPD(unsigned Opcode);
1673bool isVPCMPESTRM(unsigned Opcode);
1674bool isVFMSUB132PS(unsigned Opcode);
1675bool isVCOMISH(unsigned Opcode);
1676bool isF2XM1(unsigned Opcode);
1677bool isSQRTPD(unsigned Opcode);
1678bool isVFMSUBADDPS(unsigned Opcode);
1679bool isFXTRACT(unsigned Opcode);
1680bool isVP4DPWSSD(unsigned Opcode);
1681bool isTDPBHF8PS(unsigned Opcode);
1682bool isVFMSUBADDPD(unsigned Opcode);
1683bool isVBCSTNEBF162PS(unsigned Opcode);
1684bool isVPGATHERQQ(unsigned Opcode);
1685bool isPCMPEQB(unsigned Opcode);
1686bool isTILESTORED(unsigned Opcode);
1687bool isBLSMSK(unsigned Opcode);
1688bool isVCVTTPS2DQ(unsigned Opcode);
1689bool isVFPCLASSBF16(unsigned Opcode);
1690bool isVRNDSCALEPD(unsigned Opcode);
1691bool isVMLOAD(unsigned Opcode);
1692bool isVPTERNLOGQ(unsigned Opcode);
1693bool isKXNORD(unsigned Opcode);
1694bool isFXSAVE(unsigned Opcode);
1695bool isVUNPCKHPD(unsigned Opcode);
1696bool isCVTPS2DQ(unsigned Opcode);
1697bool isVFMSUB213SS(unsigned Opcode);
1698bool isVPOPCNTD(unsigned Opcode);
1699bool isSALC(unsigned Opcode);
1700bool isV4FNMADDSS(unsigned Opcode);
1701bool isXCRYPTOFB(unsigned Opcode);
1702bool isVORPD(unsigned Opcode);
1703bool isLSL(unsigned Opcode);
1704bool isXCRYPTCFB(unsigned Opcode);
1705bool isVGETEXPSS(unsigned Opcode);
1706bool isPSLLDQ(unsigned Opcode);
1707bool isVPDPBUUD(unsigned Opcode);
1708bool isVMXOFF(unsigned Opcode);
1709bool isBLSIC(unsigned Opcode);
1710bool isMOVLHPS(unsigned Opcode);
1711bool isVMOVRSQ(unsigned Opcode);
1712bool isVFNMSUBSD(unsigned Opcode);
1713bool isVCVTPH2IUBS(unsigned Opcode);
1714bool isVFPCLASSSH(unsigned Opcode);
1715bool isVPSHLQ(unsigned Opcode);
1716bool isVROUNDPS(unsigned Opcode);
1717bool isVSCATTERPF0QPS(unsigned Opcode);
1718bool isERETS(unsigned Opcode);
1719bool isVPERMI2D(unsigned Opcode);
1720bool isFUCOMP(unsigned Opcode);
1721bool isVCVTTPS2QQ(unsigned Opcode);
1722bool isPUSHFD(unsigned Opcode);
1723bool isVPABSD(unsigned Opcode);
1724bool isKORB(unsigned Opcode);
1725bool isVRCP28PD(unsigned Opcode);
1726bool isVROUNDSS(unsigned Opcode);
1727bool isVCVTSD2USI(unsigned Opcode);
1728bool isVPABSB(unsigned Opcode);
1729bool isPMAXUD(unsigned Opcode);
1730bool isVPERMPD(unsigned Opcode);
1731bool isVPMULHUW(unsigned Opcode);
1732bool isFCHS(unsigned Opcode);
1733bool isVPBLENDMB(unsigned Opcode);
1734bool isVGETMANTSS(unsigned Opcode);
1735bool isVPSLLW(unsigned Opcode);
1736bool isVDIVPD(unsigned Opcode);
1737bool isBLCMSK(unsigned Opcode);
1738bool isFDIV(unsigned Opcode);
1739bool isRSQRTSS(unsigned Opcode);
1740bool isPOR(unsigned Opcode);
1741bool isVMOVDQA32(unsigned Opcode);
1742bool isVPHADDUWQ(unsigned Opcode);
1743bool isPSRAD(unsigned Opcode);
1744bool isPREFETCHW(unsigned Opcode);
1745bool isFIDIVR(unsigned Opcode);
1746bool isMOVHPS(unsigned Opcode);
1747bool isVFNMSUB231PH(unsigned Opcode);
1748bool isUNPCKLPS(unsigned Opcode);
1749bool isVPSIGNB(unsigned Opcode);
1750bool isSAVEPREVSSP(unsigned Opcode);
1751bool isVSCALEFSD(unsigned Opcode);
1752bool isFSIN(unsigned Opcode);
1753bool isSCASQ(unsigned Opcode);
1754bool isVCVTTPD2QQS(unsigned Opcode);
1755bool isPCMPGTW(unsigned Opcode);
1756bool isMULX(unsigned Opcode);
1757bool isVPMAXUW(unsigned Opcode);
1758bool isPAUSE(unsigned Opcode);
1759bool isMOVQ2DQ(unsigned Opcode);
1760bool isVPABSW(unsigned Opcode);
1761bool isVBITREVB(unsigned Opcode);
1762bool isVPCOMPRESSD(unsigned Opcode);
1763bool isVPSUBQ(unsigned Opcode);
1764bool isVPMOVUSQW(unsigned Opcode);
1765bool isBLENDVPD(unsigned Opcode);
1766bool isVFNMADD132BF16(unsigned Opcode);
1767bool isVPMOVQB(unsigned Opcode);
1768bool isVBLENDVPS(unsigned Opcode);
1769bool isKSHIFTLQ(unsigned Opcode);
1770bool isPMOVSXWD(unsigned Opcode);
1771bool isPHSUBSW(unsigned Opcode);
1772bool isPSRLQ(unsigned Opcode);
1773bool isVCVTPH2DQ(unsigned Opcode);
1774bool isPCMPESTRIQ(unsigned Opcode);
1775bool isFISUB(unsigned Opcode);
1776bool isVCVTPS2UDQ(unsigned Opcode);
1777bool isVMOVDDUP(unsigned Opcode);
1778bool isPCMPEQD(unsigned Opcode);
1779bool isVRSQRT28SD(unsigned Opcode);
1780bool isTDPHBF8PS(unsigned Opcode);
1781bool isVPOPCNTQ(unsigned Opcode);
1782bool isLODSW(unsigned Opcode);
1783bool isKSHIFTRB(unsigned Opcode);
1784bool isVFNMADDPS(unsigned Opcode);
1785bool isCCMPCC(unsigned Opcode);
1786bool isFXRSTOR64(unsigned Opcode);
1787bool isVFMSUBADD213PD(unsigned Opcode);
1788bool isVSQRTPH(unsigned Opcode);
1789bool isPOPF(unsigned Opcode);
1790bool isVPSUBUSB(unsigned Opcode);
1791bool isTCVTROWPS2BF16L(unsigned Opcode);
1792bool isVPADDSW(unsigned Opcode);
1793bool isPREFETCHIT1(unsigned Opcode);
1794bool isVADDSUBPD(unsigned Opcode);
1795bool isKANDD(unsigned Opcode);
1796bool isPREFETCHRST2(unsigned Opcode);
1797bool isOUTSB(unsigned Opcode);
1798bool isFNSTSW(unsigned Opcode);
1799bool isPMINSB(unsigned Opcode);
1800
1801} // namespace llvm::X86
1802
1803#endif // GET_X86_MNEMONIC_TABLES_H
1804
1805#ifdef GET_X86_MNEMONIC_TABLES_CPP
1806#undef GET_X86_MNEMONIC_TABLES_CPP
1807
1808namespace llvm::X86 {
1809
1810bool isFSUBRP(unsigned Opcode) {
1811 return Opcode == SUBR_FPrST0;
1812}
1813
1814bool isVPDPBUSDS(unsigned Opcode) {
1815 switch (Opcode) {
1816 case VPDPBUSDSYrm:
1817 case VPDPBUSDSYrr:
1818 case VPDPBUSDSZ128rm:
1819 case VPDPBUSDSZ128rmb:
1820 case VPDPBUSDSZ128rmbk:
1821 case VPDPBUSDSZ128rmbkz:
1822 case VPDPBUSDSZ128rmk:
1823 case VPDPBUSDSZ128rmkz:
1824 case VPDPBUSDSZ128rr:
1825 case VPDPBUSDSZ128rrk:
1826 case VPDPBUSDSZ128rrkz:
1827 case VPDPBUSDSZ256rm:
1828 case VPDPBUSDSZ256rmb:
1829 case VPDPBUSDSZ256rmbk:
1830 case VPDPBUSDSZ256rmbkz:
1831 case VPDPBUSDSZ256rmk:
1832 case VPDPBUSDSZ256rmkz:
1833 case VPDPBUSDSZ256rr:
1834 case VPDPBUSDSZ256rrk:
1835 case VPDPBUSDSZ256rrkz:
1836 case VPDPBUSDSZrm:
1837 case VPDPBUSDSZrmb:
1838 case VPDPBUSDSZrmbk:
1839 case VPDPBUSDSZrmbkz:
1840 case VPDPBUSDSZrmk:
1841 case VPDPBUSDSZrmkz:
1842 case VPDPBUSDSZrr:
1843 case VPDPBUSDSZrrk:
1844 case VPDPBUSDSZrrkz:
1845 case VPDPBUSDSrm:
1846 case VPDPBUSDSrr:
1847 return true;
1848 }
1849 return false;
1850}
1851
1852bool isPUNPCKLWD(unsigned Opcode) {
1853 switch (Opcode) {
1854 case MMX_PUNPCKLWDrm:
1855 case MMX_PUNPCKLWDrr:
1856 case PUNPCKLWDrm:
1857 case PUNPCKLWDrr:
1858 return true;
1859 }
1860 return false;
1861}
1862
1863bool isVREDUCEBF16(unsigned Opcode) {
1864 switch (Opcode) {
1865 case VREDUCEBF16Z128rmbi:
1866 case VREDUCEBF16Z128rmbik:
1867 case VREDUCEBF16Z128rmbikz:
1868 case VREDUCEBF16Z128rmi:
1869 case VREDUCEBF16Z128rmik:
1870 case VREDUCEBF16Z128rmikz:
1871 case VREDUCEBF16Z128rri:
1872 case VREDUCEBF16Z128rrik:
1873 case VREDUCEBF16Z128rrikz:
1874 case VREDUCEBF16Z256rmbi:
1875 case VREDUCEBF16Z256rmbik:
1876 case VREDUCEBF16Z256rmbikz:
1877 case VREDUCEBF16Z256rmi:
1878 case VREDUCEBF16Z256rmik:
1879 case VREDUCEBF16Z256rmikz:
1880 case VREDUCEBF16Z256rri:
1881 case VREDUCEBF16Z256rrik:
1882 case VREDUCEBF16Z256rrikz:
1883 case VREDUCEBF16Zrmbi:
1884 case VREDUCEBF16Zrmbik:
1885 case VREDUCEBF16Zrmbikz:
1886 case VREDUCEBF16Zrmi:
1887 case VREDUCEBF16Zrmik:
1888 case VREDUCEBF16Zrmikz:
1889 case VREDUCEBF16Zrri:
1890 case VREDUCEBF16Zrrik:
1891 case VREDUCEBF16Zrrikz:
1892 return true;
1893 }
1894 return false;
1895}
1896
1897bool isPUNPCKLQDQ(unsigned Opcode) {
1898 switch (Opcode) {
1899 case PUNPCKLQDQrm:
1900 case PUNPCKLQDQrr:
1901 return true;
1902 }
1903 return false;
1904}
1905
1906bool isRDFSBASE(unsigned Opcode) {
1907 switch (Opcode) {
1908 case RDFSBASE:
1909 case RDFSBASE64:
1910 return true;
1911 }
1912 return false;
1913}
1914
1915bool isVPCMOV(unsigned Opcode) {
1916 switch (Opcode) {
1917 case VPCMOVYrmr:
1918 case VPCMOVYrrm:
1919 case VPCMOVYrrr:
1920 case VPCMOVYrrr_REV:
1921 case VPCMOVrmr:
1922 case VPCMOVrrm:
1923 case VPCMOVrrr:
1924 case VPCMOVrrr_REV:
1925 return true;
1926 }
1927 return false;
1928}
1929
1930bool isVDIVSD(unsigned Opcode) {
1931 switch (Opcode) {
1932 case VDIVSDZrm_Int:
1933 case VDIVSDZrmk_Int:
1934 case VDIVSDZrmkz_Int:
1935 case VDIVSDZrr_Int:
1936 case VDIVSDZrrb_Int:
1937 case VDIVSDZrrbk_Int:
1938 case VDIVSDZrrbkz_Int:
1939 case VDIVSDZrrk_Int:
1940 case VDIVSDZrrkz_Int:
1941 case VDIVSDrm_Int:
1942 case VDIVSDrr_Int:
1943 return true;
1944 }
1945 return false;
1946}
1947
1948bool isVCVTTPS2IBS(unsigned Opcode) {
1949 switch (Opcode) {
1950 case VCVTTPS2IBSZ128rm:
1951 case VCVTTPS2IBSZ128rmb:
1952 case VCVTTPS2IBSZ128rmbk:
1953 case VCVTTPS2IBSZ128rmbkz:
1954 case VCVTTPS2IBSZ128rmk:
1955 case VCVTTPS2IBSZ128rmkz:
1956 case VCVTTPS2IBSZ128rr:
1957 case VCVTTPS2IBSZ128rrk:
1958 case VCVTTPS2IBSZ128rrkz:
1959 case VCVTTPS2IBSZ256rm:
1960 case VCVTTPS2IBSZ256rmb:
1961 case VCVTTPS2IBSZ256rmbk:
1962 case VCVTTPS2IBSZ256rmbkz:
1963 case VCVTTPS2IBSZ256rmk:
1964 case VCVTTPS2IBSZ256rmkz:
1965 case VCVTTPS2IBSZ256rr:
1966 case VCVTTPS2IBSZ256rrk:
1967 case VCVTTPS2IBSZ256rrkz:
1968 case VCVTTPS2IBSZrm:
1969 case VCVTTPS2IBSZrmb:
1970 case VCVTTPS2IBSZrmbk:
1971 case VCVTTPS2IBSZrmbkz:
1972 case VCVTTPS2IBSZrmk:
1973 case VCVTTPS2IBSZrmkz:
1974 case VCVTTPS2IBSZrr:
1975 case VCVTTPS2IBSZrrb:
1976 case VCVTTPS2IBSZrrbk:
1977 case VCVTTPS2IBSZrrbkz:
1978 case VCVTTPS2IBSZrrk:
1979 case VCVTTPS2IBSZrrkz:
1980 return true;
1981 }
1982 return false;
1983}
1984
1985bool isVPEXTRW(unsigned Opcode) {
1986 switch (Opcode) {
1987 case VPEXTRWZmri:
1988 case VPEXTRWZrri:
1989 case VPEXTRWZrri_REV:
1990 case VPEXTRWmri:
1991 case VPEXTRWrri:
1992 case VPEXTRWrri_REV:
1993 return true;
1994 }
1995 return false;
1996}
1997
1998bool isLODSD(unsigned Opcode) {
1999 return Opcode == LODSL;
2000}
2001
2002bool isVPTESTNMQ(unsigned Opcode) {
2003 switch (Opcode) {
2004 case VPTESTNMQZ128rm:
2005 case VPTESTNMQZ128rmb:
2006 case VPTESTNMQZ128rmbk:
2007 case VPTESTNMQZ128rmk:
2008 case VPTESTNMQZ128rr:
2009 case VPTESTNMQZ128rrk:
2010 case VPTESTNMQZ256rm:
2011 case VPTESTNMQZ256rmb:
2012 case VPTESTNMQZ256rmbk:
2013 case VPTESTNMQZ256rmk:
2014 case VPTESTNMQZ256rr:
2015 case VPTESTNMQZ256rrk:
2016 case VPTESTNMQZrm:
2017 case VPTESTNMQZrmb:
2018 case VPTESTNMQZrmbk:
2019 case VPTESTNMQZrmk:
2020 case VPTESTNMQZrr:
2021 case VPTESTNMQZrrk:
2022 return true;
2023 }
2024 return false;
2025}
2026
2027bool isCVTSS2SD(unsigned Opcode) {
2028 switch (Opcode) {
2029 case CVTSS2SDrm_Int:
2030 case CVTSS2SDrr_Int:
2031 return true;
2032 }
2033 return false;
2034}
2035
2036bool isVGETMANTPD(unsigned Opcode) {
2037 switch (Opcode) {
2038 case VGETMANTPDZ128rmbi:
2039 case VGETMANTPDZ128rmbik:
2040 case VGETMANTPDZ128rmbikz:
2041 case VGETMANTPDZ128rmi:
2042 case VGETMANTPDZ128rmik:
2043 case VGETMANTPDZ128rmikz:
2044 case VGETMANTPDZ128rri:
2045 case VGETMANTPDZ128rrik:
2046 case VGETMANTPDZ128rrikz:
2047 case VGETMANTPDZ256rmbi:
2048 case VGETMANTPDZ256rmbik:
2049 case VGETMANTPDZ256rmbikz:
2050 case VGETMANTPDZ256rmi:
2051 case VGETMANTPDZ256rmik:
2052 case VGETMANTPDZ256rmikz:
2053 case VGETMANTPDZ256rri:
2054 case VGETMANTPDZ256rrik:
2055 case VGETMANTPDZ256rrikz:
2056 case VGETMANTPDZrmbi:
2057 case VGETMANTPDZrmbik:
2058 case VGETMANTPDZrmbikz:
2059 case VGETMANTPDZrmi:
2060 case VGETMANTPDZrmik:
2061 case VGETMANTPDZrmikz:
2062 case VGETMANTPDZrri:
2063 case VGETMANTPDZrrib:
2064 case VGETMANTPDZrribk:
2065 case VGETMANTPDZrribkz:
2066 case VGETMANTPDZrrik:
2067 case VGETMANTPDZrrikz:
2068 return true;
2069 }
2070 return false;
2071}
2072
2073bool isVMOVDQA64(unsigned Opcode) {
2074 switch (Opcode) {
2075 case VMOVDQA64Z128mr:
2076 case VMOVDQA64Z128mrk:
2077 case VMOVDQA64Z128rm:
2078 case VMOVDQA64Z128rmk:
2079 case VMOVDQA64Z128rmkz:
2080 case VMOVDQA64Z128rr:
2081 case VMOVDQA64Z128rr_REV:
2082 case VMOVDQA64Z128rrk:
2083 case VMOVDQA64Z128rrk_REV:
2084 case VMOVDQA64Z128rrkz:
2085 case VMOVDQA64Z128rrkz_REV:
2086 case VMOVDQA64Z256mr:
2087 case VMOVDQA64Z256mrk:
2088 case VMOVDQA64Z256rm:
2089 case VMOVDQA64Z256rmk:
2090 case VMOVDQA64Z256rmkz:
2091 case VMOVDQA64Z256rr:
2092 case VMOVDQA64Z256rr_REV:
2093 case VMOVDQA64Z256rrk:
2094 case VMOVDQA64Z256rrk_REV:
2095 case VMOVDQA64Z256rrkz:
2096 case VMOVDQA64Z256rrkz_REV:
2097 case VMOVDQA64Zmr:
2098 case VMOVDQA64Zmrk:
2099 case VMOVDQA64Zrm:
2100 case VMOVDQA64Zrmk:
2101 case VMOVDQA64Zrmkz:
2102 case VMOVDQA64Zrr:
2103 case VMOVDQA64Zrr_REV:
2104 case VMOVDQA64Zrrk:
2105 case VMOVDQA64Zrrk_REV:
2106 case VMOVDQA64Zrrkz:
2107 case VMOVDQA64Zrrkz_REV:
2108 return true;
2109 }
2110 return false;
2111}
2112
2113bool isINVLPG(unsigned Opcode) {
2114 return Opcode == INVLPG;
2115}
2116
2117bool isVGETEXPBF16(unsigned Opcode) {
2118 switch (Opcode) {
2119 case VGETEXPBF16Z128m:
2120 case VGETEXPBF16Z128mb:
2121 case VGETEXPBF16Z128mbk:
2122 case VGETEXPBF16Z128mbkz:
2123 case VGETEXPBF16Z128mk:
2124 case VGETEXPBF16Z128mkz:
2125 case VGETEXPBF16Z128r:
2126 case VGETEXPBF16Z128rk:
2127 case VGETEXPBF16Z128rkz:
2128 case VGETEXPBF16Z256m:
2129 case VGETEXPBF16Z256mb:
2130 case VGETEXPBF16Z256mbk:
2131 case VGETEXPBF16Z256mbkz:
2132 case VGETEXPBF16Z256mk:
2133 case VGETEXPBF16Z256mkz:
2134 case VGETEXPBF16Z256r:
2135 case VGETEXPBF16Z256rk:
2136 case VGETEXPBF16Z256rkz:
2137 case VGETEXPBF16Zm:
2138 case VGETEXPBF16Zmb:
2139 case VGETEXPBF16Zmbk:
2140 case VGETEXPBF16Zmbkz:
2141 case VGETEXPBF16Zmk:
2142 case VGETEXPBF16Zmkz:
2143 case VGETEXPBF16Zr:
2144 case VGETEXPBF16Zrk:
2145 case VGETEXPBF16Zrkz:
2146 return true;
2147 }
2148 return false;
2149}
2150
2151bool isVBROADCASTF64X4(unsigned Opcode) {
2152 switch (Opcode) {
2153 case VBROADCASTF64X4Zrm:
2154 case VBROADCASTF64X4Zrmk:
2155 case VBROADCASTF64X4Zrmkz:
2156 return true;
2157 }
2158 return false;
2159}
2160
2161bool isVPERMI2Q(unsigned Opcode) {
2162 switch (Opcode) {
2163 case VPERMI2QZ128rm:
2164 case VPERMI2QZ128rmb:
2165 case VPERMI2QZ128rmbk:
2166 case VPERMI2QZ128rmbkz:
2167 case VPERMI2QZ128rmk:
2168 case VPERMI2QZ128rmkz:
2169 case VPERMI2QZ128rr:
2170 case VPERMI2QZ128rrk:
2171 case VPERMI2QZ128rrkz:
2172 case VPERMI2QZ256rm:
2173 case VPERMI2QZ256rmb:
2174 case VPERMI2QZ256rmbk:
2175 case VPERMI2QZ256rmbkz:
2176 case VPERMI2QZ256rmk:
2177 case VPERMI2QZ256rmkz:
2178 case VPERMI2QZ256rr:
2179 case VPERMI2QZ256rrk:
2180 case VPERMI2QZ256rrkz:
2181 case VPERMI2QZrm:
2182 case VPERMI2QZrmb:
2183 case VPERMI2QZrmbk:
2184 case VPERMI2QZrmbkz:
2185 case VPERMI2QZrmk:
2186 case VPERMI2QZrmkz:
2187 case VPERMI2QZrr:
2188 case VPERMI2QZrrk:
2189 case VPERMI2QZrrkz:
2190 return true;
2191 }
2192 return false;
2193}
2194
2195bool isVPMOVSXBD(unsigned Opcode) {
2196 switch (Opcode) {
2197 case VPMOVSXBDYrm:
2198 case VPMOVSXBDYrr:
2199 case VPMOVSXBDZ128rm:
2200 case VPMOVSXBDZ128rmk:
2201 case VPMOVSXBDZ128rmkz:
2202 case VPMOVSXBDZ128rr:
2203 case VPMOVSXBDZ128rrk:
2204 case VPMOVSXBDZ128rrkz:
2205 case VPMOVSXBDZ256rm:
2206 case VPMOVSXBDZ256rmk:
2207 case VPMOVSXBDZ256rmkz:
2208 case VPMOVSXBDZ256rr:
2209 case VPMOVSXBDZ256rrk:
2210 case VPMOVSXBDZ256rrkz:
2211 case VPMOVSXBDZrm:
2212 case VPMOVSXBDZrmk:
2213 case VPMOVSXBDZrmkz:
2214 case VPMOVSXBDZrr:
2215 case VPMOVSXBDZrrk:
2216 case VPMOVSXBDZrrkz:
2217 case VPMOVSXBDrm:
2218 case VPMOVSXBDrr:
2219 return true;
2220 }
2221 return false;
2222}
2223
2224bool isVFMSUB132SS(unsigned Opcode) {
2225 switch (Opcode) {
2226 case VFMSUB132SSZm_Int:
2227 case VFMSUB132SSZmk_Int:
2228 case VFMSUB132SSZmkz_Int:
2229 case VFMSUB132SSZr_Int:
2230 case VFMSUB132SSZrb_Int:
2231 case VFMSUB132SSZrbk_Int:
2232 case VFMSUB132SSZrbkz_Int:
2233 case VFMSUB132SSZrk_Int:
2234 case VFMSUB132SSZrkz_Int:
2235 case VFMSUB132SSm_Int:
2236 case VFMSUB132SSr_Int:
2237 return true;
2238 }
2239 return false;
2240}
2241
2242bool isVPMOVUSDW(unsigned Opcode) {
2243 switch (Opcode) {
2244 case VPMOVUSDWZ128mr:
2245 case VPMOVUSDWZ128mrk:
2246 case VPMOVUSDWZ128rr:
2247 case VPMOVUSDWZ128rrk:
2248 case VPMOVUSDWZ128rrkz:
2249 case VPMOVUSDWZ256mr:
2250 case VPMOVUSDWZ256mrk:
2251 case VPMOVUSDWZ256rr:
2252 case VPMOVUSDWZ256rrk:
2253 case VPMOVUSDWZ256rrkz:
2254 case VPMOVUSDWZmr:
2255 case VPMOVUSDWZmrk:
2256 case VPMOVUSDWZrr:
2257 case VPMOVUSDWZrrk:
2258 case VPMOVUSDWZrrkz:
2259 return true;
2260 }
2261 return false;
2262}
2263
2264bool isAAD(unsigned Opcode) {
2265 return Opcode == AAD8i8;
2266}
2267
2268bool isIDIV(unsigned Opcode) {
2269 switch (Opcode) {
2270 case IDIV16m:
2271 case IDIV16m_EVEX:
2272 case IDIV16m_NF:
2273 case IDIV16r:
2274 case IDIV16r_EVEX:
2275 case IDIV16r_NF:
2276 case IDIV32m:
2277 case IDIV32m_EVEX:
2278 case IDIV32m_NF:
2279 case IDIV32r:
2280 case IDIV32r_EVEX:
2281 case IDIV32r_NF:
2282 case IDIV64m:
2283 case IDIV64m_EVEX:
2284 case IDIV64m_NF:
2285 case IDIV64r:
2286 case IDIV64r_EVEX:
2287 case IDIV64r_NF:
2288 case IDIV8m:
2289 case IDIV8m_EVEX:
2290 case IDIV8m_NF:
2291 case IDIV8r:
2292 case IDIV8r_EVEX:
2293 case IDIV8r_NF:
2294 return true;
2295 }
2296 return false;
2297}
2298
2299bool isCVTTPS2DQ(unsigned Opcode) {
2300 switch (Opcode) {
2301 case CVTTPS2DQrm:
2302 case CVTTPS2DQrr:
2303 return true;
2304 }
2305 return false;
2306}
2307
2308bool isVBROADCASTF32X8(unsigned Opcode) {
2309 switch (Opcode) {
2310 case VBROADCASTF32X8Zrm:
2311 case VBROADCASTF32X8Zrmk:
2312 case VBROADCASTF32X8Zrmkz:
2313 return true;
2314 }
2315 return false;
2316}
2317
2318bool isVFMSUBSS(unsigned Opcode) {
2319 switch (Opcode) {
2320 case VFMSUBSS4mr:
2321 case VFMSUBSS4rm:
2322 case VFMSUBSS4rr:
2323 case VFMSUBSS4rr_REV:
2324 return true;
2325 }
2326 return false;
2327}
2328
2329bool isEMMS(unsigned Opcode) {
2330 return Opcode == MMX_EMMS;
2331}
2332
2333bool isVPDPBSUD(unsigned Opcode) {
2334 switch (Opcode) {
2335 case VPDPBSUDYrm:
2336 case VPDPBSUDYrr:
2337 case VPDPBSUDZ128rm:
2338 case VPDPBSUDZ128rmb:
2339 case VPDPBSUDZ128rmbk:
2340 case VPDPBSUDZ128rmbkz:
2341 case VPDPBSUDZ128rmk:
2342 case VPDPBSUDZ128rmkz:
2343 case VPDPBSUDZ128rr:
2344 case VPDPBSUDZ128rrk:
2345 case VPDPBSUDZ128rrkz:
2346 case VPDPBSUDZ256rm:
2347 case VPDPBSUDZ256rmb:
2348 case VPDPBSUDZ256rmbk:
2349 case VPDPBSUDZ256rmbkz:
2350 case VPDPBSUDZ256rmk:
2351 case VPDPBSUDZ256rmkz:
2352 case VPDPBSUDZ256rr:
2353 case VPDPBSUDZ256rrk:
2354 case VPDPBSUDZ256rrkz:
2355 case VPDPBSUDZrm:
2356 case VPDPBSUDZrmb:
2357 case VPDPBSUDZrmbk:
2358 case VPDPBSUDZrmbkz:
2359 case VPDPBSUDZrmk:
2360 case VPDPBSUDZrmkz:
2361 case VPDPBSUDZrr:
2362 case VPDPBSUDZrrk:
2363 case VPDPBSUDZrrkz:
2364 case VPDPBSUDrm:
2365 case VPDPBSUDrr:
2366 return true;
2367 }
2368 return false;
2369}
2370
2371bool isPMOVSXWQ(unsigned Opcode) {
2372 switch (Opcode) {
2373 case PMOVSXWQrm:
2374 case PMOVSXWQrr:
2375 return true;
2376 }
2377 return false;
2378}
2379
2380bool isPSRLW(unsigned Opcode) {
2381 switch (Opcode) {
2382 case MMX_PSRLWri:
2383 case MMX_PSRLWrm:
2384 case MMX_PSRLWrr:
2385 case PSRLWri:
2386 case PSRLWrm:
2387 case PSRLWrr:
2388 return true;
2389 }
2390 return false;
2391}
2392
2393bool isMOVNTDQA(unsigned Opcode) {
2394 return Opcode == MOVNTDQArm;
2395}
2396
2397bool isFUCOMPI(unsigned Opcode) {
2398 return Opcode == UCOM_FIPr;
2399}
2400
2401bool isANDNPS(unsigned Opcode) {
2402 switch (Opcode) {
2403 case ANDNPSrm:
2404 case ANDNPSrr:
2405 return true;
2406 }
2407 return false;
2408}
2409
2410bool isVINSERTF64X2(unsigned Opcode) {
2411 switch (Opcode) {
2412 case VINSERTF64X2Z256rmi:
2413 case VINSERTF64X2Z256rmik:
2414 case VINSERTF64X2Z256rmikz:
2415 case VINSERTF64X2Z256rri:
2416 case VINSERTF64X2Z256rrik:
2417 case VINSERTF64X2Z256rrikz:
2418 case VINSERTF64X2Zrmi:
2419 case VINSERTF64X2Zrmik:
2420 case VINSERTF64X2Zrmikz:
2421 case VINSERTF64X2Zrri:
2422 case VINSERTF64X2Zrrik:
2423 case VINSERTF64X2Zrrikz:
2424 return true;
2425 }
2426 return false;
2427}
2428
2429bool isCLTS(unsigned Opcode) {
2430 return Opcode == CLTS;
2431}
2432
2433bool isSETSSBSY(unsigned Opcode) {
2434 return Opcode == SETSSBSY;
2435}
2436
2437bool isVMULPD(unsigned Opcode) {
2438 switch (Opcode) {
2439 case VMULPDYrm:
2440 case VMULPDYrr:
2441 case VMULPDZ128rm:
2442 case VMULPDZ128rmb:
2443 case VMULPDZ128rmbk:
2444 case VMULPDZ128rmbkz:
2445 case VMULPDZ128rmk:
2446 case VMULPDZ128rmkz:
2447 case VMULPDZ128rr:
2448 case VMULPDZ128rrk:
2449 case VMULPDZ128rrkz:
2450 case VMULPDZ256rm:
2451 case VMULPDZ256rmb:
2452 case VMULPDZ256rmbk:
2453 case VMULPDZ256rmbkz:
2454 case VMULPDZ256rmk:
2455 case VMULPDZ256rmkz:
2456 case VMULPDZ256rr:
2457 case VMULPDZ256rrk:
2458 case VMULPDZ256rrkz:
2459 case VMULPDZrm:
2460 case VMULPDZrmb:
2461 case VMULPDZrmbk:
2462 case VMULPDZrmbkz:
2463 case VMULPDZrmk:
2464 case VMULPDZrmkz:
2465 case VMULPDZrr:
2466 case VMULPDZrrb:
2467 case VMULPDZrrbk:
2468 case VMULPDZrrbkz:
2469 case VMULPDZrrk:
2470 case VMULPDZrrkz:
2471 case VMULPDrm:
2472 case VMULPDrr:
2473 return true;
2474 }
2475 return false;
2476}
2477
2478bool isVFMADDSUB132PS(unsigned Opcode) {
2479 switch (Opcode) {
2480 case VFMADDSUB132PSYm:
2481 case VFMADDSUB132PSYr:
2482 case VFMADDSUB132PSZ128m:
2483 case VFMADDSUB132PSZ128mb:
2484 case VFMADDSUB132PSZ128mbk:
2485 case VFMADDSUB132PSZ128mbkz:
2486 case VFMADDSUB132PSZ128mk:
2487 case VFMADDSUB132PSZ128mkz:
2488 case VFMADDSUB132PSZ128r:
2489 case VFMADDSUB132PSZ128rk:
2490 case VFMADDSUB132PSZ128rkz:
2491 case VFMADDSUB132PSZ256m:
2492 case VFMADDSUB132PSZ256mb:
2493 case VFMADDSUB132PSZ256mbk:
2494 case VFMADDSUB132PSZ256mbkz:
2495 case VFMADDSUB132PSZ256mk:
2496 case VFMADDSUB132PSZ256mkz:
2497 case VFMADDSUB132PSZ256r:
2498 case VFMADDSUB132PSZ256rk:
2499 case VFMADDSUB132PSZ256rkz:
2500 case VFMADDSUB132PSZm:
2501 case VFMADDSUB132PSZmb:
2502 case VFMADDSUB132PSZmbk:
2503 case VFMADDSUB132PSZmbkz:
2504 case VFMADDSUB132PSZmk:
2505 case VFMADDSUB132PSZmkz:
2506 case VFMADDSUB132PSZr:
2507 case VFMADDSUB132PSZrb:
2508 case VFMADDSUB132PSZrbk:
2509 case VFMADDSUB132PSZrbkz:
2510 case VFMADDSUB132PSZrk:
2511 case VFMADDSUB132PSZrkz:
2512 case VFMADDSUB132PSm:
2513 case VFMADDSUB132PSr:
2514 return true;
2515 }
2516 return false;
2517}
2518
2519bool isVPMADCSWD(unsigned Opcode) {
2520 switch (Opcode) {
2521 case VPMADCSWDrm:
2522 case VPMADCSWDrr:
2523 return true;
2524 }
2525 return false;
2526}
2527
2528bool isVSCATTERPF0DPS(unsigned Opcode) {
2529 return Opcode == VSCATTERPF0DPSm;
2530}
2531
2532bool isXCHG(unsigned Opcode) {
2533 switch (Opcode) {
2534 case XCHG16ar:
2535 case XCHG16rm:
2536 case XCHG16rr:
2537 case XCHG32ar:
2538 case XCHG32rm:
2539 case XCHG32rr:
2540 case XCHG64ar:
2541 case XCHG64rm:
2542 case XCHG64rr:
2543 case XCHG8rm:
2544 case XCHG8rr:
2545 return true;
2546 }
2547 return false;
2548}
2549
2550bool isVGATHERPF1QPS(unsigned Opcode) {
2551 return Opcode == VGATHERPF1QPSm;
2552}
2553
2554bool isVCVTNEPS2BF16(unsigned Opcode) {
2555 switch (Opcode) {
2556 case VCVTNEPS2BF16Yrm:
2557 case VCVTNEPS2BF16Yrr:
2558 case VCVTNEPS2BF16Z128rm:
2559 case VCVTNEPS2BF16Z128rmb:
2560 case VCVTNEPS2BF16Z128rmbk:
2561 case VCVTNEPS2BF16Z128rmbkz:
2562 case VCVTNEPS2BF16Z128rmk:
2563 case VCVTNEPS2BF16Z128rmkz:
2564 case VCVTNEPS2BF16Z128rr:
2565 case VCVTNEPS2BF16Z128rrk:
2566 case VCVTNEPS2BF16Z128rrkz:
2567 case VCVTNEPS2BF16Z256rm:
2568 case VCVTNEPS2BF16Z256rmb:
2569 case VCVTNEPS2BF16Z256rmbk:
2570 case VCVTNEPS2BF16Z256rmbkz:
2571 case VCVTNEPS2BF16Z256rmk:
2572 case VCVTNEPS2BF16Z256rmkz:
2573 case VCVTNEPS2BF16Z256rr:
2574 case VCVTNEPS2BF16Z256rrk:
2575 case VCVTNEPS2BF16Z256rrkz:
2576 case VCVTNEPS2BF16Zrm:
2577 case VCVTNEPS2BF16Zrmb:
2578 case VCVTNEPS2BF16Zrmbk:
2579 case VCVTNEPS2BF16Zrmbkz:
2580 case VCVTNEPS2BF16Zrmk:
2581 case VCVTNEPS2BF16Zrmkz:
2582 case VCVTNEPS2BF16Zrr:
2583 case VCVTNEPS2BF16Zrrk:
2584 case VCVTNEPS2BF16Zrrkz:
2585 case VCVTNEPS2BF16rm:
2586 case VCVTNEPS2BF16rr:
2587 return true;
2588 }
2589 return false;
2590}
2591
2592bool isVFMADDSS(unsigned Opcode) {
2593 switch (Opcode) {
2594 case VFMADDSS4mr:
2595 case VFMADDSS4rm:
2596 case VFMADDSS4rr:
2597 case VFMADDSS4rr_REV:
2598 return true;
2599 }
2600 return false;
2601}
2602
2603bool isINTO(unsigned Opcode) {
2604 return Opcode == INTO;
2605}
2606
2607bool isANDPD(unsigned Opcode) {
2608 switch (Opcode) {
2609 case ANDPDrm:
2610 case ANDPDrr:
2611 return true;
2612 }
2613 return false;
2614}
2615
2616bool isSEAMCALL(unsigned Opcode) {
2617 return Opcode == SEAMCALL;
2618}
2619
2620bool isSHLD(unsigned Opcode) {
2621 switch (Opcode) {
2622 case SHLD16mrCL:
2623 case SHLD16mrCL_EVEX:
2624 case SHLD16mrCL_ND:
2625 case SHLD16mrCL_NF:
2626 case SHLD16mrCL_NF_ND:
2627 case SHLD16mri8:
2628 case SHLD16mri8_EVEX:
2629 case SHLD16mri8_ND:
2630 case SHLD16mri8_NF:
2631 case SHLD16mri8_NF_ND:
2632 case SHLD16rrCL:
2633 case SHLD16rrCL_EVEX:
2634 case SHLD16rrCL_ND:
2635 case SHLD16rrCL_NF:
2636 case SHLD16rrCL_NF_ND:
2637 case SHLD16rri8:
2638 case SHLD16rri8_EVEX:
2639 case SHLD16rri8_ND:
2640 case SHLD16rri8_NF:
2641 case SHLD16rri8_NF_ND:
2642 case SHLD32mrCL:
2643 case SHLD32mrCL_EVEX:
2644 case SHLD32mrCL_ND:
2645 case SHLD32mrCL_NF:
2646 case SHLD32mrCL_NF_ND:
2647 case SHLD32mri8:
2648 case SHLD32mri8_EVEX:
2649 case SHLD32mri8_ND:
2650 case SHLD32mri8_NF:
2651 case SHLD32mri8_NF_ND:
2652 case SHLD32rrCL:
2653 case SHLD32rrCL_EVEX:
2654 case SHLD32rrCL_ND:
2655 case SHLD32rrCL_NF:
2656 case SHLD32rrCL_NF_ND:
2657 case SHLD32rri8:
2658 case SHLD32rri8_EVEX:
2659 case SHLD32rri8_ND:
2660 case SHLD32rri8_NF:
2661 case SHLD32rri8_NF_ND:
2662 case SHLD64mrCL:
2663 case SHLD64mrCL_EVEX:
2664 case SHLD64mrCL_ND:
2665 case SHLD64mrCL_NF:
2666 case SHLD64mrCL_NF_ND:
2667 case SHLD64mri8:
2668 case SHLD64mri8_EVEX:
2669 case SHLD64mri8_ND:
2670 case SHLD64mri8_NF:
2671 case SHLD64mri8_NF_ND:
2672 case SHLD64rrCL:
2673 case SHLD64rrCL_EVEX:
2674 case SHLD64rrCL_ND:
2675 case SHLD64rrCL_NF:
2676 case SHLD64rrCL_NF_ND:
2677 case SHLD64rri8:
2678 case SHLD64rri8_EVEX:
2679 case SHLD64rri8_ND:
2680 case SHLD64rri8_NF:
2681 case SHLD64rri8_NF_ND:
2682 return true;
2683 }
2684 return false;
2685}
2686
2687bool isUNPCKHPS(unsigned Opcode) {
2688 switch (Opcode) {
2689 case UNPCKHPSrm:
2690 case UNPCKHPSrr:
2691 return true;
2692 }
2693 return false;
2694}
2695
2696bool isVPDPBSSDS(unsigned Opcode) {
2697 switch (Opcode) {
2698 case VPDPBSSDSYrm:
2699 case VPDPBSSDSYrr:
2700 case VPDPBSSDSZ128rm:
2701 case VPDPBSSDSZ128rmb:
2702 case VPDPBSSDSZ128rmbk:
2703 case VPDPBSSDSZ128rmbkz:
2704 case VPDPBSSDSZ128rmk:
2705 case VPDPBSSDSZ128rmkz:
2706 case VPDPBSSDSZ128rr:
2707 case VPDPBSSDSZ128rrk:
2708 case VPDPBSSDSZ128rrkz:
2709 case VPDPBSSDSZ256rm:
2710 case VPDPBSSDSZ256rmb:
2711 case VPDPBSSDSZ256rmbk:
2712 case VPDPBSSDSZ256rmbkz:
2713 case VPDPBSSDSZ256rmk:
2714 case VPDPBSSDSZ256rmkz:
2715 case VPDPBSSDSZ256rr:
2716 case VPDPBSSDSZ256rrk:
2717 case VPDPBSSDSZ256rrkz:
2718 case VPDPBSSDSZrm:
2719 case VPDPBSSDSZrmb:
2720 case VPDPBSSDSZrmbk:
2721 case VPDPBSSDSZrmbkz:
2722 case VPDPBSSDSZrmk:
2723 case VPDPBSSDSZrmkz:
2724 case VPDPBSSDSZrr:
2725 case VPDPBSSDSZrrk:
2726 case VPDPBSSDSZrrkz:
2727 case VPDPBSSDSrm:
2728 case VPDPBSSDSrr:
2729 return true;
2730 }
2731 return false;
2732}
2733
2734bool isSETZUCC(unsigned Opcode) {
2735 switch (Opcode) {
2736 case SETZUCCm:
2737 case SETZUCCr:
2738 return true;
2739 }
2740 return false;
2741}
2742
2743bool isSHUFPD(unsigned Opcode) {
2744 switch (Opcode) {
2745 case SHUFPDrmi:
2746 case SHUFPDrri:
2747 return true;
2748 }
2749 return false;
2750}
2751
2752bool isFCMOVNB(unsigned Opcode) {
2753 return Opcode == CMOVNB_F;
2754}
2755
2756bool isCVTTSS2SI(unsigned Opcode) {
2757 switch (Opcode) {
2758 case CVTTSS2SI64rm_Int:
2759 case CVTTSS2SI64rr_Int:
2760 case CVTTSS2SIrm_Int:
2761 case CVTTSS2SIrr_Int:
2762 return true;
2763 }
2764 return false;
2765}
2766
2767bool isEXTRQ(unsigned Opcode) {
2768 switch (Opcode) {
2769 case EXTRQ:
2770 case EXTRQI:
2771 return true;
2772 }
2773 return false;
2774}
2775
2776bool isVBROADCASTSS(unsigned Opcode) {
2777 switch (Opcode) {
2778 case VBROADCASTSSYrm:
2779 case VBROADCASTSSYrr:
2780 case VBROADCASTSSZ128rm:
2781 case VBROADCASTSSZ128rmk:
2782 case VBROADCASTSSZ128rmkz:
2783 case VBROADCASTSSZ128rr:
2784 case VBROADCASTSSZ128rrk:
2785 case VBROADCASTSSZ128rrkz:
2786 case VBROADCASTSSZ256rm:
2787 case VBROADCASTSSZ256rmk:
2788 case VBROADCASTSSZ256rmkz:
2789 case VBROADCASTSSZ256rr:
2790 case VBROADCASTSSZ256rrk:
2791 case VBROADCASTSSZ256rrkz:
2792 case VBROADCASTSSZrm:
2793 case VBROADCASTSSZrmk:
2794 case VBROADCASTSSZrmkz:
2795 case VBROADCASTSSZrr:
2796 case VBROADCASTSSZrrk:
2797 case VBROADCASTSSZrrkz:
2798 case VBROADCASTSSrm:
2799 case VBROADCASTSSrr:
2800 return true;
2801 }
2802 return false;
2803}
2804
2805bool isCLUI(unsigned Opcode) {
2806 return Opcode == CLUI;
2807}
2808
2809bool isVINSERTI128(unsigned Opcode) {
2810 switch (Opcode) {
2811 case VINSERTI128rmi:
2812 case VINSERTI128rri:
2813 return true;
2814 }
2815 return false;
2816}
2817
2818bool isVPSHLDW(unsigned Opcode) {
2819 switch (Opcode) {
2820 case VPSHLDWZ128rmi:
2821 case VPSHLDWZ128rmik:
2822 case VPSHLDWZ128rmikz:
2823 case VPSHLDWZ128rri:
2824 case VPSHLDWZ128rrik:
2825 case VPSHLDWZ128rrikz:
2826 case VPSHLDWZ256rmi:
2827 case VPSHLDWZ256rmik:
2828 case VPSHLDWZ256rmikz:
2829 case VPSHLDWZ256rri:
2830 case VPSHLDWZ256rrik:
2831 case VPSHLDWZ256rrikz:
2832 case VPSHLDWZrmi:
2833 case VPSHLDWZrmik:
2834 case VPSHLDWZrmikz:
2835 case VPSHLDWZrri:
2836 case VPSHLDWZrrik:
2837 case VPSHLDWZrrikz:
2838 return true;
2839 }
2840 return false;
2841}
2842
2843bool isVBLENDPD(unsigned Opcode) {
2844 switch (Opcode) {
2845 case VBLENDPDYrmi:
2846 case VBLENDPDYrri:
2847 case VBLENDPDrmi:
2848 case VBLENDPDrri:
2849 return true;
2850 }
2851 return false;
2852}
2853
2854bool isVSM4KEY4(unsigned Opcode) {
2855 switch (Opcode) {
2856 case VSM4KEY4Yrm:
2857 case VSM4KEY4Yrr:
2858 case VSM4KEY4Z128rm:
2859 case VSM4KEY4Z128rr:
2860 case VSM4KEY4Z256rm:
2861 case VSM4KEY4Z256rr:
2862 case VSM4KEY4Zrm:
2863 case VSM4KEY4Zrr:
2864 case VSM4KEY4rm:
2865 case VSM4KEY4rr:
2866 return true;
2867 }
2868 return false;
2869}
2870
2871bool isVCVTNEEPH2PS(unsigned Opcode) {
2872 switch (Opcode) {
2873 case VCVTNEEPH2PSYrm:
2874 case VCVTNEEPH2PSrm:
2875 return true;
2876 }
2877 return false;
2878}
2879
2880bool isVCVTTSD2SI(unsigned Opcode) {
2881 switch (Opcode) {
2882 case VCVTTSD2SI64Zrm_Int:
2883 case VCVTTSD2SI64Zrr_Int:
2884 case VCVTTSD2SI64Zrrb_Int:
2885 case VCVTTSD2SI64rm_Int:
2886 case VCVTTSD2SI64rr_Int:
2887 case VCVTTSD2SIZrm_Int:
2888 case VCVTTSD2SIZrr_Int:
2889 case VCVTTSD2SIZrrb_Int:
2890 case VCVTTSD2SIrm_Int:
2891 case VCVTTSD2SIrr_Int:
2892 return true;
2893 }
2894 return false;
2895}
2896
2897bool isWRMSRNS(unsigned Opcode) {
2898 switch (Opcode) {
2899 case WRMSRNS:
2900 case WRMSRNSir:
2901 case WRMSRNSir_EVEX:
2902 return true;
2903 }
2904 return false;
2905}
2906
2907bool isCMPSB(unsigned Opcode) {
2908 return Opcode == CMPSB;
2909}
2910
2911bool isVRCPBF16(unsigned Opcode) {
2912 switch (Opcode) {
2913 case VRCPBF16Z128m:
2914 case VRCPBF16Z128mb:
2915 case VRCPBF16Z128mbk:
2916 case VRCPBF16Z128mbkz:
2917 case VRCPBF16Z128mk:
2918 case VRCPBF16Z128mkz:
2919 case VRCPBF16Z128r:
2920 case VRCPBF16Z128rk:
2921 case VRCPBF16Z128rkz:
2922 case VRCPBF16Z256m:
2923 case VRCPBF16Z256mb:
2924 case VRCPBF16Z256mbk:
2925 case VRCPBF16Z256mbkz:
2926 case VRCPBF16Z256mk:
2927 case VRCPBF16Z256mkz:
2928 case VRCPBF16Z256r:
2929 case VRCPBF16Z256rk:
2930 case VRCPBF16Z256rkz:
2931 case VRCPBF16Zm:
2932 case VRCPBF16Zmb:
2933 case VRCPBF16Zmbk:
2934 case VRCPBF16Zmbkz:
2935 case VRCPBF16Zmk:
2936 case VRCPBF16Zmkz:
2937 case VRCPBF16Zr:
2938 case VRCPBF16Zrk:
2939 case VRCPBF16Zrkz:
2940 return true;
2941 }
2942 return false;
2943}
2944
2945bool isMULSS(unsigned Opcode) {
2946 switch (Opcode) {
2947 case MULSSrm_Int:
2948 case MULSSrr_Int:
2949 return true;
2950 }
2951 return false;
2952}
2953
2954bool isVMRUN(unsigned Opcode) {
2955 switch (Opcode) {
2956 case VMRUN32:
2957 case VMRUN64:
2958 return true;
2959 }
2960 return false;
2961}
2962
2963bool isVPSRLVD(unsigned Opcode) {
2964 switch (Opcode) {
2965 case VPSRLVDYrm:
2966 case VPSRLVDYrr:
2967 case VPSRLVDZ128rm:
2968 case VPSRLVDZ128rmb:
2969 case VPSRLVDZ128rmbk:
2970 case VPSRLVDZ128rmbkz:
2971 case VPSRLVDZ128rmk:
2972 case VPSRLVDZ128rmkz:
2973 case VPSRLVDZ128rr:
2974 case VPSRLVDZ128rrk:
2975 case VPSRLVDZ128rrkz:
2976 case VPSRLVDZ256rm:
2977 case VPSRLVDZ256rmb:
2978 case VPSRLVDZ256rmbk:
2979 case VPSRLVDZ256rmbkz:
2980 case VPSRLVDZ256rmk:
2981 case VPSRLVDZ256rmkz:
2982 case VPSRLVDZ256rr:
2983 case VPSRLVDZ256rrk:
2984 case VPSRLVDZ256rrkz:
2985 case VPSRLVDZrm:
2986 case VPSRLVDZrmb:
2987 case VPSRLVDZrmbk:
2988 case VPSRLVDZrmbkz:
2989 case VPSRLVDZrmk:
2990 case VPSRLVDZrmkz:
2991 case VPSRLVDZrr:
2992 case VPSRLVDZrrk:
2993 case VPSRLVDZrrkz:
2994 case VPSRLVDrm:
2995 case VPSRLVDrr:
2996 return true;
2997 }
2998 return false;
2999}
3000
3001bool isLEAVE(unsigned Opcode) {
3002 switch (Opcode) {
3003 case LEAVE:
3004 case LEAVE64:
3005 return true;
3006 }
3007 return false;
3008}
3009
3010bool isVGETMANTPS(unsigned Opcode) {
3011 switch (Opcode) {
3012 case VGETMANTPSZ128rmbi:
3013 case VGETMANTPSZ128rmbik:
3014 case VGETMANTPSZ128rmbikz:
3015 case VGETMANTPSZ128rmi:
3016 case VGETMANTPSZ128rmik:
3017 case VGETMANTPSZ128rmikz:
3018 case VGETMANTPSZ128rri:
3019 case VGETMANTPSZ128rrik:
3020 case VGETMANTPSZ128rrikz:
3021 case VGETMANTPSZ256rmbi:
3022 case VGETMANTPSZ256rmbik:
3023 case VGETMANTPSZ256rmbikz:
3024 case VGETMANTPSZ256rmi:
3025 case VGETMANTPSZ256rmik:
3026 case VGETMANTPSZ256rmikz:
3027 case VGETMANTPSZ256rri:
3028 case VGETMANTPSZ256rrik:
3029 case VGETMANTPSZ256rrikz:
3030 case VGETMANTPSZrmbi:
3031 case VGETMANTPSZrmbik:
3032 case VGETMANTPSZrmbikz:
3033 case VGETMANTPSZrmi:
3034 case VGETMANTPSZrmik:
3035 case VGETMANTPSZrmikz:
3036 case VGETMANTPSZrri:
3037 case VGETMANTPSZrrib:
3038 case VGETMANTPSZrribk:
3039 case VGETMANTPSZrribkz:
3040 case VGETMANTPSZrrik:
3041 case VGETMANTPSZrrikz:
3042 return true;
3043 }
3044 return false;
3045}
3046
3047bool isXSHA256(unsigned Opcode) {
3048 return Opcode == XSHA256;
3049}
3050
3051bool isBOUND(unsigned Opcode) {
3052 switch (Opcode) {
3053 case BOUNDS16rm:
3054 case BOUNDS32rm:
3055 return true;
3056 }
3057 return false;
3058}
3059
3060bool isSFENCE(unsigned Opcode) {
3061 return Opcode == SFENCE;
3062}
3063
3064bool isVPHADDD(unsigned Opcode) {
3065 switch (Opcode) {
3066 case VPHADDDYrm:
3067 case VPHADDDYrr:
3068 case VPHADDDrm:
3069 case VPHADDDrr:
3070 return true;
3071 }
3072 return false;
3073}
3074
3075bool isADOX(unsigned Opcode) {
3076 switch (Opcode) {
3077 case ADOX32rm:
3078 case ADOX32rm_EVEX:
3079 case ADOX32rm_ND:
3080 case ADOX32rr:
3081 case ADOX32rr_EVEX:
3082 case ADOX32rr_ND:
3083 case ADOX64rm:
3084 case ADOX64rm_EVEX:
3085 case ADOX64rm_ND:
3086 case ADOX64rr:
3087 case ADOX64rr_EVEX:
3088 case ADOX64rr_ND:
3089 return true;
3090 }
3091 return false;
3092}
3093
3094bool isVPSLLQ(unsigned Opcode) {
3095 switch (Opcode) {
3096 case VPSLLQYri:
3097 case VPSLLQYrm:
3098 case VPSLLQYrr:
3099 case VPSLLQZ128mbi:
3100 case VPSLLQZ128mbik:
3101 case VPSLLQZ128mbikz:
3102 case VPSLLQZ128mi:
3103 case VPSLLQZ128mik:
3104 case VPSLLQZ128mikz:
3105 case VPSLLQZ128ri:
3106 case VPSLLQZ128rik:
3107 case VPSLLQZ128rikz:
3108 case VPSLLQZ128rm:
3109 case VPSLLQZ128rmk:
3110 case VPSLLQZ128rmkz:
3111 case VPSLLQZ128rr:
3112 case VPSLLQZ128rrk:
3113 case VPSLLQZ128rrkz:
3114 case VPSLLQZ256mbi:
3115 case VPSLLQZ256mbik:
3116 case VPSLLQZ256mbikz:
3117 case VPSLLQZ256mi:
3118 case VPSLLQZ256mik:
3119 case VPSLLQZ256mikz:
3120 case VPSLLQZ256ri:
3121 case VPSLLQZ256rik:
3122 case VPSLLQZ256rikz:
3123 case VPSLLQZ256rm:
3124 case VPSLLQZ256rmk:
3125 case VPSLLQZ256rmkz:
3126 case VPSLLQZ256rr:
3127 case VPSLLQZ256rrk:
3128 case VPSLLQZ256rrkz:
3129 case VPSLLQZmbi:
3130 case VPSLLQZmbik:
3131 case VPSLLQZmbikz:
3132 case VPSLLQZmi:
3133 case VPSLLQZmik:
3134 case VPSLLQZmikz:
3135 case VPSLLQZri:
3136 case VPSLLQZrik:
3137 case VPSLLQZrikz:
3138 case VPSLLQZrm:
3139 case VPSLLQZrmk:
3140 case VPSLLQZrmkz:
3141 case VPSLLQZrr:
3142 case VPSLLQZrrk:
3143 case VPSLLQZrrkz:
3144 case VPSLLQri:
3145 case VPSLLQrm:
3146 case VPSLLQrr:
3147 return true;
3148 }
3149 return false;
3150}
3151
3152bool isVCVTPH2HF8(unsigned Opcode) {
3153 switch (Opcode) {
3154 case VCVTPH2HF8Z128rm:
3155 case VCVTPH2HF8Z128rmb:
3156 case VCVTPH2HF8Z128rmbk:
3157 case VCVTPH2HF8Z128rmbkz:
3158 case VCVTPH2HF8Z128rmk:
3159 case VCVTPH2HF8Z128rmkz:
3160 case VCVTPH2HF8Z128rr:
3161 case VCVTPH2HF8Z128rrk:
3162 case VCVTPH2HF8Z128rrkz:
3163 case VCVTPH2HF8Z256rm:
3164 case VCVTPH2HF8Z256rmb:
3165 case VCVTPH2HF8Z256rmbk:
3166 case VCVTPH2HF8Z256rmbkz:
3167 case VCVTPH2HF8Z256rmk:
3168 case VCVTPH2HF8Z256rmkz:
3169 case VCVTPH2HF8Z256rr:
3170 case VCVTPH2HF8Z256rrk:
3171 case VCVTPH2HF8Z256rrkz:
3172 case VCVTPH2HF8Zrm:
3173 case VCVTPH2HF8Zrmb:
3174 case VCVTPH2HF8Zrmbk:
3175 case VCVTPH2HF8Zrmbkz:
3176 case VCVTPH2HF8Zrmk:
3177 case VCVTPH2HF8Zrmkz:
3178 case VCVTPH2HF8Zrr:
3179 case VCVTPH2HF8Zrrk:
3180 case VCVTPH2HF8Zrrkz:
3181 return true;
3182 }
3183 return false;
3184}
3185
3186bool isPFRSQIT1(unsigned Opcode) {
3187 switch (Opcode) {
3188 case PFRSQIT1rm:
3189 case PFRSQIT1rr:
3190 return true;
3191 }
3192 return false;
3193}
3194
3195bool isCLAC(unsigned Opcode) {
3196 return Opcode == CLAC;
3197}
3198
3199bool isKNOTW(unsigned Opcode) {
3200 return Opcode == KNOTWkk;
3201}
3202
3203bool isVCVTPH2PD(unsigned Opcode) {
3204 switch (Opcode) {
3205 case VCVTPH2PDZ128rm:
3206 case VCVTPH2PDZ128rmb:
3207 case VCVTPH2PDZ128rmbk:
3208 case VCVTPH2PDZ128rmbkz:
3209 case VCVTPH2PDZ128rmk:
3210 case VCVTPH2PDZ128rmkz:
3211 case VCVTPH2PDZ128rr:
3212 case VCVTPH2PDZ128rrk:
3213 case VCVTPH2PDZ128rrkz:
3214 case VCVTPH2PDZ256rm:
3215 case VCVTPH2PDZ256rmb:
3216 case VCVTPH2PDZ256rmbk:
3217 case VCVTPH2PDZ256rmbkz:
3218 case VCVTPH2PDZ256rmk:
3219 case VCVTPH2PDZ256rmkz:
3220 case VCVTPH2PDZ256rr:
3221 case VCVTPH2PDZ256rrk:
3222 case VCVTPH2PDZ256rrkz:
3223 case VCVTPH2PDZrm:
3224 case VCVTPH2PDZrmb:
3225 case VCVTPH2PDZrmbk:
3226 case VCVTPH2PDZrmbkz:
3227 case VCVTPH2PDZrmk:
3228 case VCVTPH2PDZrmkz:
3229 case VCVTPH2PDZrr:
3230 case VCVTPH2PDZrrb:
3231 case VCVTPH2PDZrrbk:
3232 case VCVTPH2PDZrrbkz:
3233 case VCVTPH2PDZrrk:
3234 case VCVTPH2PDZrrkz:
3235 return true;
3236 }
3237 return false;
3238}
3239
3240bool isVAESENC(unsigned Opcode) {
3241 switch (Opcode) {
3242 case VAESENCYrm:
3243 case VAESENCYrr:
3244 case VAESENCZ128rm:
3245 case VAESENCZ128rr:
3246 case VAESENCZ256rm:
3247 case VAESENCZ256rr:
3248 case VAESENCZrm:
3249 case VAESENCZrr:
3250 case VAESENCrm:
3251 case VAESENCrr:
3252 return true;
3253 }
3254 return false;
3255}
3256
3257bool isMOVNTI(unsigned Opcode) {
3258 switch (Opcode) {
3259 case MOVNTI_64mr:
3260 case MOVNTImr:
3261 return true;
3262 }
3263 return false;
3264}
3265
3266bool isFXCH(unsigned Opcode) {
3267 return Opcode == XCH_F;
3268}
3269
3270bool isPOPP(unsigned Opcode) {
3271 return Opcode == POPP64r;
3272}
3273
3274bool isVPBLENDMD(unsigned Opcode) {
3275 switch (Opcode) {
3276 case VPBLENDMDZ128rm:
3277 case VPBLENDMDZ128rmb:
3278 case VPBLENDMDZ128rmbk:
3279 case VPBLENDMDZ128rmbkz:
3280 case VPBLENDMDZ128rmk:
3281 case VPBLENDMDZ128rmkz:
3282 case VPBLENDMDZ128rr:
3283 case VPBLENDMDZ128rrk:
3284 case VPBLENDMDZ128rrkz:
3285 case VPBLENDMDZ256rm:
3286 case VPBLENDMDZ256rmb:
3287 case VPBLENDMDZ256rmbk:
3288 case VPBLENDMDZ256rmbkz:
3289 case VPBLENDMDZ256rmk:
3290 case VPBLENDMDZ256rmkz:
3291 case VPBLENDMDZ256rr:
3292 case VPBLENDMDZ256rrk:
3293 case VPBLENDMDZ256rrkz:
3294 case VPBLENDMDZrm:
3295 case VPBLENDMDZrmb:
3296 case VPBLENDMDZrmbk:
3297 case VPBLENDMDZrmbkz:
3298 case VPBLENDMDZrmk:
3299 case VPBLENDMDZrmkz:
3300 case VPBLENDMDZrr:
3301 case VPBLENDMDZrrk:
3302 case VPBLENDMDZrrkz:
3303 return true;
3304 }
3305 return false;
3306}
3307
3308bool isFSINCOS(unsigned Opcode) {
3309 return Opcode == FSINCOS;
3310}
3311
3312bool isVPMOVSXBW(unsigned Opcode) {
3313 switch (Opcode) {
3314 case VPMOVSXBWYrm:
3315 case VPMOVSXBWYrr:
3316 case VPMOVSXBWZ128rm:
3317 case VPMOVSXBWZ128rmk:
3318 case VPMOVSXBWZ128rmkz:
3319 case VPMOVSXBWZ128rr:
3320 case VPMOVSXBWZ128rrk:
3321 case VPMOVSXBWZ128rrkz:
3322 case VPMOVSXBWZ256rm:
3323 case VPMOVSXBWZ256rmk:
3324 case VPMOVSXBWZ256rmkz:
3325 case VPMOVSXBWZ256rr:
3326 case VPMOVSXBWZ256rrk:
3327 case VPMOVSXBWZ256rrkz:
3328 case VPMOVSXBWZrm:
3329 case VPMOVSXBWZrmk:
3330 case VPMOVSXBWZrmkz:
3331 case VPMOVSXBWZrr:
3332 case VPMOVSXBWZrrk:
3333 case VPMOVSXBWZrrkz:
3334 case VPMOVSXBWrm:
3335 case VPMOVSXBWrr:
3336 return true;
3337 }
3338 return false;
3339}
3340
3341bool isVPMULLW(unsigned Opcode) {
3342 switch (Opcode) {
3343 case VPMULLWYrm:
3344 case VPMULLWYrr:
3345 case VPMULLWZ128rm:
3346 case VPMULLWZ128rmk:
3347 case VPMULLWZ128rmkz:
3348 case VPMULLWZ128rr:
3349 case VPMULLWZ128rrk:
3350 case VPMULLWZ128rrkz:
3351 case VPMULLWZ256rm:
3352 case VPMULLWZ256rmk:
3353 case VPMULLWZ256rmkz:
3354 case VPMULLWZ256rr:
3355 case VPMULLWZ256rrk:
3356 case VPMULLWZ256rrkz:
3357 case VPMULLWZrm:
3358 case VPMULLWZrmk:
3359 case VPMULLWZrmkz:
3360 case VPMULLWZrr:
3361 case VPMULLWZrrk:
3362 case VPMULLWZrrkz:
3363 case VPMULLWrm:
3364 case VPMULLWrr:
3365 return true;
3366 }
3367 return false;
3368}
3369
3370bool isSTC(unsigned Opcode) {
3371 return Opcode == STC;
3372}
3373
3374bool isVPINSRB(unsigned Opcode) {
3375 switch (Opcode) {
3376 case VPINSRBZrmi:
3377 case VPINSRBZrri:
3378 case VPINSRBrmi:
3379 case VPINSRBrri:
3380 return true;
3381 }
3382 return false;
3383}
3384
3385bool isLWPVAL(unsigned Opcode) {
3386 switch (Opcode) {
3387 case LWPVAL32rmi:
3388 case LWPVAL32rri:
3389 case LWPVAL64rmi:
3390 case LWPVAL64rri:
3391 return true;
3392 }
3393 return false;
3394}
3395
3396bool isKXORB(unsigned Opcode) {
3397 return Opcode == KXORBkk;
3398}
3399
3400bool isRSTORSSP(unsigned Opcode) {
3401 return Opcode == RSTORSSP;
3402}
3403
3404bool isVPRORQ(unsigned Opcode) {
3405 switch (Opcode) {
3406 case VPRORQZ128mbi:
3407 case VPRORQZ128mbik:
3408 case VPRORQZ128mbikz:
3409 case VPRORQZ128mi:
3410 case VPRORQZ128mik:
3411 case VPRORQZ128mikz:
3412 case VPRORQZ128ri:
3413 case VPRORQZ128rik:
3414 case VPRORQZ128rikz:
3415 case VPRORQZ256mbi:
3416 case VPRORQZ256mbik:
3417 case VPRORQZ256mbikz:
3418 case VPRORQZ256mi:
3419 case VPRORQZ256mik:
3420 case VPRORQZ256mikz:
3421 case VPRORQZ256ri:
3422 case VPRORQZ256rik:
3423 case VPRORQZ256rikz:
3424 case VPRORQZmbi:
3425 case VPRORQZmbik:
3426 case VPRORQZmbikz:
3427 case VPRORQZmi:
3428 case VPRORQZmik:
3429 case VPRORQZmikz:
3430 case VPRORQZri:
3431 case VPRORQZrik:
3432 case VPRORQZrikz:
3433 return true;
3434 }
3435 return false;
3436}
3437
3438bool isVSM3MSG1(unsigned Opcode) {
3439 switch (Opcode) {
3440 case VSM3MSG1rm:
3441 case VSM3MSG1rr:
3442 return true;
3443 }
3444 return false;
3445}
3446
3447bool isFICOM(unsigned Opcode) {
3448 switch (Opcode) {
3449 case FICOM16m:
3450 case FICOM32m:
3451 return true;
3452 }
3453 return false;
3454}
3455
3456bool isMAXPS(unsigned Opcode) {
3457 switch (Opcode) {
3458 case MAXPSrm:
3459 case MAXPSrr:
3460 return true;
3461 }
3462 return false;
3463}
3464
3465bool isFNCLEX(unsigned Opcode) {
3466 return Opcode == FNCLEX;
3467}
3468
3469bool isVMOVMSKPS(unsigned Opcode) {
3470 switch (Opcode) {
3471 case VMOVMSKPSYrr:
3472 case VMOVMSKPSrr:
3473 return true;
3474 }
3475 return false;
3476}
3477
3478bool isVPMOVDB(unsigned Opcode) {
3479 switch (Opcode) {
3480 case VPMOVDBZ128mr:
3481 case VPMOVDBZ128mrk:
3482 case VPMOVDBZ128rr:
3483 case VPMOVDBZ128rrk:
3484 case VPMOVDBZ128rrkz:
3485 case VPMOVDBZ256mr:
3486 case VPMOVDBZ256mrk:
3487 case VPMOVDBZ256rr:
3488 case VPMOVDBZ256rrk:
3489 case VPMOVDBZ256rrkz:
3490 case VPMOVDBZmr:
3491 case VPMOVDBZmrk:
3492 case VPMOVDBZrr:
3493 case VPMOVDBZrrk:
3494 case VPMOVDBZrrkz:
3495 return true;
3496 }
3497 return false;
3498}
3499
3500bool isLLWPCB(unsigned Opcode) {
3501 switch (Opcode) {
3502 case LLWPCB:
3503 case LLWPCB64:
3504 return true;
3505 }
3506 return false;
3507}
3508
3509bool isVMULSS(unsigned Opcode) {
3510 switch (Opcode) {
3511 case VMULSSZrm_Int:
3512 case VMULSSZrmk_Int:
3513 case VMULSSZrmkz_Int:
3514 case VMULSSZrr_Int:
3515 case VMULSSZrrb_Int:
3516 case VMULSSZrrbk_Int:
3517 case VMULSSZrrbkz_Int:
3518 case VMULSSZrrk_Int:
3519 case VMULSSZrrkz_Int:
3520 case VMULSSrm_Int:
3521 case VMULSSrr_Int:
3522 return true;
3523 }
3524 return false;
3525}
3526
3527bool isAESENCLAST(unsigned Opcode) {
3528 switch (Opcode) {
3529 case AESENCLASTrm:
3530 case AESENCLASTrr:
3531 return true;
3532 }
3533 return false;
3534}
3535
3536bool isTILEMOVROW(unsigned Opcode) {
3537 switch (Opcode) {
3538 case TILEMOVROWrte:
3539 case TILEMOVROWrti:
3540 return true;
3541 }
3542 return false;
3543}
3544
3545bool isVMINMAXPH(unsigned Opcode) {
3546 switch (Opcode) {
3547 case VMINMAXPHZ128rmbi:
3548 case VMINMAXPHZ128rmbik:
3549 case VMINMAXPHZ128rmbikz:
3550 case VMINMAXPHZ128rmi:
3551 case VMINMAXPHZ128rmik:
3552 case VMINMAXPHZ128rmikz:
3553 case VMINMAXPHZ128rri:
3554 case VMINMAXPHZ128rrik:
3555 case VMINMAXPHZ128rrikz:
3556 case VMINMAXPHZ256rmbi:
3557 case VMINMAXPHZ256rmbik:
3558 case VMINMAXPHZ256rmbikz:
3559 case VMINMAXPHZ256rmi:
3560 case VMINMAXPHZ256rmik:
3561 case VMINMAXPHZ256rmikz:
3562 case VMINMAXPHZ256rri:
3563 case VMINMAXPHZ256rrik:
3564 case VMINMAXPHZ256rrikz:
3565 case VMINMAXPHZrmbi:
3566 case VMINMAXPHZrmbik:
3567 case VMINMAXPHZrmbikz:
3568 case VMINMAXPHZrmi:
3569 case VMINMAXPHZrmik:
3570 case VMINMAXPHZrmikz:
3571 case VMINMAXPHZrri:
3572 case VMINMAXPHZrrib:
3573 case VMINMAXPHZrribk:
3574 case VMINMAXPHZrribkz:
3575 case VMINMAXPHZrrik:
3576 case VMINMAXPHZrrikz:
3577 return true;
3578 }
3579 return false;
3580}
3581
3582bool isVPMAXUB(unsigned Opcode) {
3583 switch (Opcode) {
3584 case VPMAXUBYrm:
3585 case VPMAXUBYrr:
3586 case VPMAXUBZ128rm:
3587 case VPMAXUBZ128rmk:
3588 case VPMAXUBZ128rmkz:
3589 case VPMAXUBZ128rr:
3590 case VPMAXUBZ128rrk:
3591 case VPMAXUBZ128rrkz:
3592 case VPMAXUBZ256rm:
3593 case VPMAXUBZ256rmk:
3594 case VPMAXUBZ256rmkz:
3595 case VPMAXUBZ256rr:
3596 case VPMAXUBZ256rrk:
3597 case VPMAXUBZ256rrkz:
3598 case VPMAXUBZrm:
3599 case VPMAXUBZrmk:
3600 case VPMAXUBZrmkz:
3601 case VPMAXUBZrr:
3602 case VPMAXUBZrrk:
3603 case VPMAXUBZrrkz:
3604 case VPMAXUBrm:
3605 case VPMAXUBrr:
3606 return true;
3607 }
3608 return false;
3609}
3610
3611bool isAAS(unsigned Opcode) {
3612 return Opcode == AAS;
3613}
3614
3615bool isFADD(unsigned Opcode) {
3616 switch (Opcode) {
3617 case ADD_F32m:
3618 case ADD_F64m:
3619 case ADD_FST0r:
3620 case ADD_FrST0:
3621 return true;
3622 }
3623 return false;
3624}
3625
3626bool isJMP(unsigned Opcode) {
3627 switch (Opcode) {
3628 case FARJMP32m:
3629 case JMP16m:
3630 case JMP16r:
3631 case JMP32m:
3632 case JMP32r:
3633 case JMP64m:
3634 case JMP64r:
3635 case JMP_1:
3636 case JMP_2:
3637 case JMP_4:
3638 return true;
3639 }
3640 return false;
3641}
3642
3643bool isXCRYPTECB(unsigned Opcode) {
3644 return Opcode == XCRYPTECB;
3645}
3646
3647bool isPFRCPIT1(unsigned Opcode) {
3648 switch (Opcode) {
3649 case PFRCPIT1rm:
3650 case PFRCPIT1rr:
3651 return true;
3652 }
3653 return false;
3654}
3655
3656bool isPMULHRW(unsigned Opcode) {
3657 switch (Opcode) {
3658 case PMULHRWrm:
3659 case PMULHRWrr:
3660 return true;
3661 }
3662 return false;
3663}
3664
3665bool isVCVTPH2PS(unsigned Opcode) {
3666 switch (Opcode) {
3667 case VCVTPH2PSYrm:
3668 case VCVTPH2PSYrr:
3669 case VCVTPH2PSZ128rm:
3670 case VCVTPH2PSZ128rmk:
3671 case VCVTPH2PSZ128rmkz:
3672 case VCVTPH2PSZ128rr:
3673 case VCVTPH2PSZ128rrk:
3674 case VCVTPH2PSZ128rrkz:
3675 case VCVTPH2PSZ256rm:
3676 case VCVTPH2PSZ256rmk:
3677 case VCVTPH2PSZ256rmkz:
3678 case VCVTPH2PSZ256rr:
3679 case VCVTPH2PSZ256rrk:
3680 case VCVTPH2PSZ256rrkz:
3681 case VCVTPH2PSZrm:
3682 case VCVTPH2PSZrmk:
3683 case VCVTPH2PSZrmkz:
3684 case VCVTPH2PSZrr:
3685 case VCVTPH2PSZrrb:
3686 case VCVTPH2PSZrrbk:
3687 case VCVTPH2PSZrrbkz:
3688 case VCVTPH2PSZrrk:
3689 case VCVTPH2PSZrrkz:
3690 case VCVTPH2PSrm:
3691 case VCVTPH2PSrr:
3692 return true;
3693 }
3694 return false;
3695}
3696
3697bool isVPBLENDVB(unsigned Opcode) {
3698 switch (Opcode) {
3699 case VPBLENDVBYrmr:
3700 case VPBLENDVBYrrr:
3701 case VPBLENDVBrmr:
3702 case VPBLENDVBrrr:
3703 return true;
3704 }
3705 return false;
3706}
3707
3708bool isPCMPESTRI(unsigned Opcode) {
3709 switch (Opcode) {
3710 case PCMPESTRIrmi:
3711 case PCMPESTRIrri:
3712 return true;
3713 }
3714 return false;
3715}
3716
3717bool isSENDUIPI(unsigned Opcode) {
3718 return Opcode == SENDUIPI;
3719}
3720
3721bool isFLDLN2(unsigned Opcode) {
3722 return Opcode == FLDLN2;
3723}
3724
3725bool isVPMACSWD(unsigned Opcode) {
3726 switch (Opcode) {
3727 case VPMACSWDrm:
3728 case VPMACSWDrr:
3729 return true;
3730 }
3731 return false;
3732}
3733
3734bool isSHA1MSG1(unsigned Opcode) {
3735 switch (Opcode) {
3736 case SHA1MSG1rm:
3737 case SHA1MSG1rr:
3738 return true;
3739 }
3740 return false;
3741}
3742
3743bool isVADDPS(unsigned Opcode) {
3744 switch (Opcode) {
3745 case VADDPSYrm:
3746 case VADDPSYrr:
3747 case VADDPSZ128rm:
3748 case VADDPSZ128rmb:
3749 case VADDPSZ128rmbk:
3750 case VADDPSZ128rmbkz:
3751 case VADDPSZ128rmk:
3752 case VADDPSZ128rmkz:
3753 case VADDPSZ128rr:
3754 case VADDPSZ128rrk:
3755 case VADDPSZ128rrkz:
3756 case VADDPSZ256rm:
3757 case VADDPSZ256rmb:
3758 case VADDPSZ256rmbk:
3759 case VADDPSZ256rmbkz:
3760 case VADDPSZ256rmk:
3761 case VADDPSZ256rmkz:
3762 case VADDPSZ256rr:
3763 case VADDPSZ256rrk:
3764 case VADDPSZ256rrkz:
3765 case VADDPSZrm:
3766 case VADDPSZrmb:
3767 case VADDPSZrmbk:
3768 case VADDPSZrmbkz:
3769 case VADDPSZrmk:
3770 case VADDPSZrmkz:
3771 case VADDPSZrr:
3772 case VADDPSZrrb:
3773 case VADDPSZrrbk:
3774 case VADDPSZrrbkz:
3775 case VADDPSZrrk:
3776 case VADDPSZrrkz:
3777 case VADDPSrm:
3778 case VADDPSrr:
3779 return true;
3780 }
3781 return false;
3782}
3783
3784bool isVCVTPS2DQ(unsigned Opcode) {
3785 switch (Opcode) {
3786 case VCVTPS2DQYrm:
3787 case VCVTPS2DQYrr:
3788 case VCVTPS2DQZ128rm:
3789 case VCVTPS2DQZ128rmb:
3790 case VCVTPS2DQZ128rmbk:
3791 case VCVTPS2DQZ128rmbkz:
3792 case VCVTPS2DQZ128rmk:
3793 case VCVTPS2DQZ128rmkz:
3794 case VCVTPS2DQZ128rr:
3795 case VCVTPS2DQZ128rrk:
3796 case VCVTPS2DQZ128rrkz:
3797 case VCVTPS2DQZ256rm:
3798 case VCVTPS2DQZ256rmb:
3799 case VCVTPS2DQZ256rmbk:
3800 case VCVTPS2DQZ256rmbkz:
3801 case VCVTPS2DQZ256rmk:
3802 case VCVTPS2DQZ256rmkz:
3803 case VCVTPS2DQZ256rr:
3804 case VCVTPS2DQZ256rrk:
3805 case VCVTPS2DQZ256rrkz:
3806 case VCVTPS2DQZrm:
3807 case VCVTPS2DQZrmb:
3808 case VCVTPS2DQZrmbk:
3809 case VCVTPS2DQZrmbkz:
3810 case VCVTPS2DQZrmk:
3811 case VCVTPS2DQZrmkz:
3812 case VCVTPS2DQZrr:
3813 case VCVTPS2DQZrrb:
3814 case VCVTPS2DQZrrbk:
3815 case VCVTPS2DQZrrbkz:
3816 case VCVTPS2DQZrrk:
3817 case VCVTPS2DQZrrkz:
3818 case VCVTPS2DQrm:
3819 case VCVTPS2DQrr:
3820 return true;
3821 }
3822 return false;
3823}
3824
3825bool isPFPNACC(unsigned Opcode) {
3826 switch (Opcode) {
3827 case PFPNACCrm:
3828 case PFPNACCrr:
3829 return true;
3830 }
3831 return false;
3832}
3833
3834bool isFMUL(unsigned Opcode) {
3835 switch (Opcode) {
3836 case MUL_F32m:
3837 case MUL_F64m:
3838 case MUL_FST0r:
3839 case MUL_FrST0:
3840 return true;
3841 }
3842 return false;
3843}
3844
3845bool isFNSAVE(unsigned Opcode) {
3846 return Opcode == FSAVEm;
3847}
3848
3849bool isCDQE(unsigned Opcode) {
3850 return Opcode == CDQE;
3851}
3852
3853bool isVPMACSDD(unsigned Opcode) {
3854 switch (Opcode) {
3855 case VPMACSDDrm:
3856 case VPMACSDDrr:
3857 return true;
3858 }
3859 return false;
3860}
3861
3862bool isVSQRTPS(unsigned Opcode) {
3863 switch (Opcode) {
3864 case VSQRTPSYm:
3865 case VSQRTPSYr:
3866 case VSQRTPSZ128m:
3867 case VSQRTPSZ128mb:
3868 case VSQRTPSZ128mbk:
3869 case VSQRTPSZ128mbkz:
3870 case VSQRTPSZ128mk:
3871 case VSQRTPSZ128mkz:
3872 case VSQRTPSZ128r:
3873 case VSQRTPSZ128rk:
3874 case VSQRTPSZ128rkz:
3875 case VSQRTPSZ256m:
3876 case VSQRTPSZ256mb:
3877 case VSQRTPSZ256mbk:
3878 case VSQRTPSZ256mbkz:
3879 case VSQRTPSZ256mk:
3880 case VSQRTPSZ256mkz:
3881 case VSQRTPSZ256r:
3882 case VSQRTPSZ256rk:
3883 case VSQRTPSZ256rkz:
3884 case VSQRTPSZm:
3885 case VSQRTPSZmb:
3886 case VSQRTPSZmbk:
3887 case VSQRTPSZmbkz:
3888 case VSQRTPSZmk:
3889 case VSQRTPSZmkz:
3890 case VSQRTPSZr:
3891 case VSQRTPSZrb:
3892 case VSQRTPSZrbk:
3893 case VSQRTPSZrbkz:
3894 case VSQRTPSZrk:
3895 case VSQRTPSZrkz:
3896 case VSQRTPSm:
3897 case VSQRTPSr:
3898 return true;
3899 }
3900 return false;
3901}
3902
3903bool isCMPSQ(unsigned Opcode) {
3904 return Opcode == CMPSQ;
3905}
3906
3907bool isVPSCATTERDD(unsigned Opcode) {
3908 switch (Opcode) {
3909 case VPSCATTERDDZ128mr:
3910 case VPSCATTERDDZ256mr:
3911 case VPSCATTERDDZmr:
3912 return true;
3913 }
3914 return false;
3915}
3916
3917bool isVCVTTSD2USIS(unsigned Opcode) {
3918 switch (Opcode) {
3919 case VCVTTSD2USI64Srm_Int:
3920 case VCVTTSD2USI64Srr_Int:
3921 case VCVTTSD2USI64Srrb_Int:
3922 case VCVTTSD2USISrm_Int:
3923 case VCVTTSD2USISrr_Int:
3924 case VCVTTSD2USISrrb_Int:
3925 return true;
3926 }
3927 return false;
3928}
3929
3930bool isVRNDSCALESD(unsigned Opcode) {
3931 switch (Opcode) {
3932 case VRNDSCALESDZrmi_Int:
3933 case VRNDSCALESDZrmik_Int:
3934 case VRNDSCALESDZrmikz_Int:
3935 case VRNDSCALESDZrri_Int:
3936 case VRNDSCALESDZrrib_Int:
3937 case VRNDSCALESDZrribk_Int:
3938 case VRNDSCALESDZrribkz_Int:
3939 case VRNDSCALESDZrrik_Int:
3940 case VRNDSCALESDZrrikz_Int:
3941 return true;
3942 }
3943 return false;
3944}
3945
3946bool isSUBPS(unsigned Opcode) {
3947 switch (Opcode) {
3948 case SUBPSrm:
3949 case SUBPSrr:
3950 return true;
3951 }
3952 return false;
3953}
3954
3955bool isVMAXSH(unsigned Opcode) {
3956 switch (Opcode) {
3957 case VMAXSHZrm_Int:
3958 case VMAXSHZrmk_Int:
3959 case VMAXSHZrmkz_Int:
3960 case VMAXSHZrr_Int:
3961 case VMAXSHZrrb_Int:
3962 case VMAXSHZrrbk_Int:
3963 case VMAXSHZrrbkz_Int:
3964 case VMAXSHZrrk_Int:
3965 case VMAXSHZrrkz_Int:
3966 return true;
3967 }
3968 return false;
3969}
3970
3971bool isFLDZ(unsigned Opcode) {
3972 return Opcode == LD_F0;
3973}
3974
3975bool isVFNMADD132SS(unsigned Opcode) {
3976 switch (Opcode) {
3977 case VFNMADD132SSZm_Int:
3978 case VFNMADD132SSZmk_Int:
3979 case VFNMADD132SSZmkz_Int:
3980 case VFNMADD132SSZr_Int:
3981 case VFNMADD132SSZrb_Int:
3982 case VFNMADD132SSZrbk_Int:
3983 case VFNMADD132SSZrbkz_Int:
3984 case VFNMADD132SSZrk_Int:
3985 case VFNMADD132SSZrkz_Int:
3986 case VFNMADD132SSm_Int:
3987 case VFNMADD132SSr_Int:
3988 return true;
3989 }
3990 return false;
3991}
3992
3993bool isLGDTW(unsigned Opcode) {
3994 return Opcode == LGDT16m;
3995}
3996
3997bool isTCVTROWPS2PHH(unsigned Opcode) {
3998 switch (Opcode) {
3999 case TCVTROWPS2PHHrte:
4000 case TCVTROWPS2PHHrti:
4001 return true;
4002 }
4003 return false;
4004}
4005
4006bool isINC(unsigned Opcode) {
4007 switch (Opcode) {
4008 case INC16m:
4009 case INC16m_EVEX:
4010 case INC16m_ND:
4011 case INC16m_NF:
4012 case INC16m_NF_ND:
4013 case INC16r:
4014 case INC16r_EVEX:
4015 case INC16r_ND:
4016 case INC16r_NF:
4017 case INC16r_NF_ND:
4018 case INC16r_alt:
4019 case INC32m:
4020 case INC32m_EVEX:
4021 case INC32m_ND:
4022 case INC32m_NF:
4023 case INC32m_NF_ND:
4024 case INC32r:
4025 case INC32r_EVEX:
4026 case INC32r_ND:
4027 case INC32r_NF:
4028 case INC32r_NF_ND:
4029 case INC32r_alt:
4030 case INC64m:
4031 case INC64m_EVEX:
4032 case INC64m_ND:
4033 case INC64m_NF:
4034 case INC64m_NF_ND:
4035 case INC64r:
4036 case INC64r_EVEX:
4037 case INC64r_ND:
4038 case INC64r_NF:
4039 case INC64r_NF_ND:
4040 case INC8m:
4041 case INC8m_EVEX:
4042 case INC8m_ND:
4043 case INC8m_NF:
4044 case INC8m_NF_ND:
4045 case INC8r:
4046 case INC8r_EVEX:
4047 case INC8r_ND:
4048 case INC8r_NF:
4049 case INC8r_NF_ND:
4050 return true;
4051 }
4052 return false;
4053}
4054
4055bool isPABSB(unsigned Opcode) {
4056 switch (Opcode) {
4057 case MMX_PABSBrm:
4058 case MMX_PABSBrr:
4059 case PABSBrm:
4060 case PABSBrr:
4061 return true;
4062 }
4063 return false;
4064}
4065
4066bool isVPANDN(unsigned Opcode) {
4067 switch (Opcode) {
4068 case VPANDNYrm:
4069 case VPANDNYrr:
4070 case VPANDNrm:
4071 case VPANDNrr:
4072 return true;
4073 }
4074 return false;
4075}
4076
4077bool isVPMAXUD(unsigned Opcode) {
4078 switch (Opcode) {
4079 case VPMAXUDYrm:
4080 case VPMAXUDYrr:
4081 case VPMAXUDZ128rm:
4082 case VPMAXUDZ128rmb:
4083 case VPMAXUDZ128rmbk:
4084 case VPMAXUDZ128rmbkz:
4085 case VPMAXUDZ128rmk:
4086 case VPMAXUDZ128rmkz:
4087 case VPMAXUDZ128rr:
4088 case VPMAXUDZ128rrk:
4089 case VPMAXUDZ128rrkz:
4090 case VPMAXUDZ256rm:
4091 case VPMAXUDZ256rmb:
4092 case VPMAXUDZ256rmbk:
4093 case VPMAXUDZ256rmbkz:
4094 case VPMAXUDZ256rmk:
4095 case VPMAXUDZ256rmkz:
4096 case VPMAXUDZ256rr:
4097 case VPMAXUDZ256rrk:
4098 case VPMAXUDZ256rrkz:
4099 case VPMAXUDZrm:
4100 case VPMAXUDZrmb:
4101 case VPMAXUDZrmbk:
4102 case VPMAXUDZrmbkz:
4103 case VPMAXUDZrmk:
4104 case VPMAXUDZrmkz:
4105 case VPMAXUDZrr:
4106 case VPMAXUDZrrk:
4107 case VPMAXUDZrrkz:
4108 case VPMAXUDrm:
4109 case VPMAXUDrr:
4110 return true;
4111 }
4112 return false;
4113}
4114
4115bool isVSHA512RNDS2(unsigned Opcode) {
4116 return Opcode == VSHA512RNDS2rr;
4117}
4118
4119bool isPHADDSW(unsigned Opcode) {
4120 switch (Opcode) {
4121 case MMX_PHADDSWrm:
4122 case MMX_PHADDSWrr:
4123 case PHADDSWrm:
4124 case PHADDSWrr:
4125 return true;
4126 }
4127 return false;
4128}
4129
4130bool isVPMOVSQW(unsigned Opcode) {
4131 switch (Opcode) {
4132 case VPMOVSQWZ128mr:
4133 case VPMOVSQWZ128mrk:
4134 case VPMOVSQWZ128rr:
4135 case VPMOVSQWZ128rrk:
4136 case VPMOVSQWZ128rrkz:
4137 case VPMOVSQWZ256mr:
4138 case VPMOVSQWZ256mrk:
4139 case VPMOVSQWZ256rr:
4140 case VPMOVSQWZ256rrk:
4141 case VPMOVSQWZ256rrkz:
4142 case VPMOVSQWZmr:
4143 case VPMOVSQWZmrk:
4144 case VPMOVSQWZrr:
4145 case VPMOVSQWZrrk:
4146 case VPMOVSQWZrrkz:
4147 return true;
4148 }
4149 return false;
4150}
4151
4152bool isADDSUBPS(unsigned Opcode) {
4153 switch (Opcode) {
4154 case ADDSUBPSrm:
4155 case ADDSUBPSrr:
4156 return true;
4157 }
4158 return false;
4159}
4160
4161bool isVPMACSSDQL(unsigned Opcode) {
4162 switch (Opcode) {
4163 case VPMACSSDQLrm:
4164 case VPMACSSDQLrr:
4165 return true;
4166 }
4167 return false;
4168}
4169
4170bool isPXOR(unsigned Opcode) {
4171 switch (Opcode) {
4172 case MMX_PXORrm:
4173 case MMX_PXORrr:
4174 case PXORrm:
4175 case PXORrr:
4176 return true;
4177 }
4178 return false;
4179}
4180
4181bool isVPSRAD(unsigned Opcode) {
4182 switch (Opcode) {
4183 case VPSRADYri:
4184 case VPSRADYrm:
4185 case VPSRADYrr:
4186 case VPSRADZ128mbi:
4187 case VPSRADZ128mbik:
4188 case VPSRADZ128mbikz:
4189 case VPSRADZ128mi:
4190 case VPSRADZ128mik:
4191 case VPSRADZ128mikz:
4192 case VPSRADZ128ri:
4193 case VPSRADZ128rik:
4194 case VPSRADZ128rikz:
4195 case VPSRADZ128rm:
4196 case VPSRADZ128rmk:
4197 case VPSRADZ128rmkz:
4198 case VPSRADZ128rr:
4199 case VPSRADZ128rrk:
4200 case VPSRADZ128rrkz:
4201 case VPSRADZ256mbi:
4202 case VPSRADZ256mbik:
4203 case VPSRADZ256mbikz:
4204 case VPSRADZ256mi:
4205 case VPSRADZ256mik:
4206 case VPSRADZ256mikz:
4207 case VPSRADZ256ri:
4208 case VPSRADZ256rik:
4209 case VPSRADZ256rikz:
4210 case VPSRADZ256rm:
4211 case VPSRADZ256rmk:
4212 case VPSRADZ256rmkz:
4213 case VPSRADZ256rr:
4214 case VPSRADZ256rrk:
4215 case VPSRADZ256rrkz:
4216 case VPSRADZmbi:
4217 case VPSRADZmbik:
4218 case VPSRADZmbikz:
4219 case VPSRADZmi:
4220 case VPSRADZmik:
4221 case VPSRADZmikz:
4222 case VPSRADZri:
4223 case VPSRADZrik:
4224 case VPSRADZrikz:
4225 case VPSRADZrm:
4226 case VPSRADZrmk:
4227 case VPSRADZrmkz:
4228 case VPSRADZrr:
4229 case VPSRADZrrk:
4230 case VPSRADZrrkz:
4231 case VPSRADri:
4232 case VPSRADrm:
4233 case VPSRADrr:
4234 return true;
4235 }
4236 return false;
4237}
4238
4239bool isVPSHAB(unsigned Opcode) {
4240 switch (Opcode) {
4241 case VPSHABmr:
4242 case VPSHABrm:
4243 case VPSHABrr:
4244 case VPSHABrr_REV:
4245 return true;
4246 }
4247 return false;
4248}
4249
4250bool isBTR(unsigned Opcode) {
4251 switch (Opcode) {
4252 case BTR16mi8:
4253 case BTR16mr:
4254 case BTR16ri8:
4255 case BTR16rr:
4256 case BTR32mi8:
4257 case BTR32mr:
4258 case BTR32ri8:
4259 case BTR32rr:
4260 case BTR64mi8:
4261 case BTR64mr:
4262 case BTR64ri8:
4263 case BTR64rr:
4264 return true;
4265 }
4266 return false;
4267}
4268
4269bool isKORW(unsigned Opcode) {
4270 return Opcode == KORWkk;
4271}
4272
4273bool isVRANGESS(unsigned Opcode) {
4274 switch (Opcode) {
4275 case VRANGESSZrmi:
4276 case VRANGESSZrmik:
4277 case VRANGESSZrmikz:
4278 case VRANGESSZrri:
4279 case VRANGESSZrrib:
4280 case VRANGESSZrribk:
4281 case VRANGESSZrribkz:
4282 case VRANGESSZrrik:
4283 case VRANGESSZrrikz:
4284 return true;
4285 }
4286 return false;
4287}
4288
4289bool isVCMPPS(unsigned Opcode) {
4290 switch (Opcode) {
4291 case VCMPPSYrmi:
4292 case VCMPPSYrri:
4293 case VCMPPSZ128rmbi:
4294 case VCMPPSZ128rmbik:
4295 case VCMPPSZ128rmi:
4296 case VCMPPSZ128rmik:
4297 case VCMPPSZ128rri:
4298 case VCMPPSZ128rrik:
4299 case VCMPPSZ256rmbi:
4300 case VCMPPSZ256rmbik:
4301 case VCMPPSZ256rmi:
4302 case VCMPPSZ256rmik:
4303 case VCMPPSZ256rri:
4304 case VCMPPSZ256rrik:
4305 case VCMPPSZrmbi:
4306 case VCMPPSZrmbik:
4307 case VCMPPSZrmi:
4308 case VCMPPSZrmik:
4309 case VCMPPSZrri:
4310 case VCMPPSZrrib:
4311 case VCMPPSZrribk:
4312 case VCMPPSZrrik:
4313 case VCMPPSrmi:
4314 case VCMPPSrri:
4315 return true;
4316 }
4317 return false;
4318}
4319
4320bool isVPLZCNTD(unsigned Opcode) {
4321 switch (Opcode) {
4322 case VPLZCNTDZ128rm:
4323 case VPLZCNTDZ128rmb:
4324 case VPLZCNTDZ128rmbk:
4325 case VPLZCNTDZ128rmbkz:
4326 case VPLZCNTDZ128rmk:
4327 case VPLZCNTDZ128rmkz:
4328 case VPLZCNTDZ128rr:
4329 case VPLZCNTDZ128rrk:
4330 case VPLZCNTDZ128rrkz:
4331 case VPLZCNTDZ256rm:
4332 case VPLZCNTDZ256rmb:
4333 case VPLZCNTDZ256rmbk:
4334 case VPLZCNTDZ256rmbkz:
4335 case VPLZCNTDZ256rmk:
4336 case VPLZCNTDZ256rmkz:
4337 case VPLZCNTDZ256rr:
4338 case VPLZCNTDZ256rrk:
4339 case VPLZCNTDZ256rrkz:
4340 case VPLZCNTDZrm:
4341 case VPLZCNTDZrmb:
4342 case VPLZCNTDZrmbk:
4343 case VPLZCNTDZrmbkz:
4344 case VPLZCNTDZrmk:
4345 case VPLZCNTDZrmkz:
4346 case VPLZCNTDZrr:
4347 case VPLZCNTDZrrk:
4348 case VPLZCNTDZrrkz:
4349 return true;
4350 }
4351 return false;
4352}
4353
4354bool isTDPBUUD(unsigned Opcode) {
4355 return Opcode == TDPBUUD;
4356}
4357
4358bool isROUNDPS(unsigned Opcode) {
4359 switch (Opcode) {
4360 case ROUNDPSmi:
4361 case ROUNDPSri:
4362 return true;
4363 }
4364 return false;
4365}
4366
4367bool isFABS(unsigned Opcode) {
4368 return Opcode == ABS_F;
4369}
4370
4371bool isSUBPD(unsigned Opcode) {
4372 switch (Opcode) {
4373 case SUBPDrm:
4374 case SUBPDrr:
4375 return true;
4376 }
4377 return false;
4378}
4379
4380bool isGF2P8MULB(unsigned Opcode) {
4381 switch (Opcode) {
4382 case GF2P8MULBrm:
4383 case GF2P8MULBrr:
4384 return true;
4385 }
4386 return false;
4387}
4388
4389bool isTZMSK(unsigned Opcode) {
4390 switch (Opcode) {
4391 case TZMSK32rm:
4392 case TZMSK32rr:
4393 case TZMSK64rm:
4394 case TZMSK64rr:
4395 return true;
4396 }
4397 return false;
4398}
4399
4400bool isVMINMAXSD(unsigned Opcode) {
4401 switch (Opcode) {
4402 case VMINMAXSDrmi_Int:
4403 case VMINMAXSDrmik_Int:
4404 case VMINMAXSDrmikz_Int:
4405 case VMINMAXSDrri_Int:
4406 case VMINMAXSDrrib_Int:
4407 case VMINMAXSDrribk_Int:
4408 case VMINMAXSDrribkz_Int:
4409 case VMINMAXSDrrik_Int:
4410 case VMINMAXSDrrikz_Int:
4411 return true;
4412 }
4413 return false;
4414}
4415
4416bool isANDPS(unsigned Opcode) {
4417 switch (Opcode) {
4418 case ANDPSrm:
4419 case ANDPSrr:
4420 return true;
4421 }
4422 return false;
4423}
4424
4425bool isVEXTRACTF32X8(unsigned Opcode) {
4426 switch (Opcode) {
4427 case VEXTRACTF32X8Zmri:
4428 case VEXTRACTF32X8Zmrik:
4429 case VEXTRACTF32X8Zrri:
4430 case VEXTRACTF32X8Zrrik:
4431 case VEXTRACTF32X8Zrrikz:
4432 return true;
4433 }
4434 return false;
4435}
4436
4437bool isSEAMRET(unsigned Opcode) {
4438 return Opcode == SEAMRET;
4439}
4440
4441bool isVPCOMW(unsigned Opcode) {
4442 switch (Opcode) {
4443 case VPCOMWmi:
4444 case VPCOMWri:
4445 return true;
4446 }
4447 return false;
4448}
4449
4450bool isVFIXUPIMMPD(unsigned Opcode) {
4451 switch (Opcode) {
4452 case VFIXUPIMMPDZ128rmbi:
4453 case VFIXUPIMMPDZ128rmbik:
4454 case VFIXUPIMMPDZ128rmbikz:
4455 case VFIXUPIMMPDZ128rmi:
4456 case VFIXUPIMMPDZ128rmik:
4457 case VFIXUPIMMPDZ128rmikz:
4458 case VFIXUPIMMPDZ128rri:
4459 case VFIXUPIMMPDZ128rrik:
4460 case VFIXUPIMMPDZ128rrikz:
4461 case VFIXUPIMMPDZ256rmbi:
4462 case VFIXUPIMMPDZ256rmbik:
4463 case VFIXUPIMMPDZ256rmbikz:
4464 case VFIXUPIMMPDZ256rmi:
4465 case VFIXUPIMMPDZ256rmik:
4466 case VFIXUPIMMPDZ256rmikz:
4467 case VFIXUPIMMPDZ256rri:
4468 case VFIXUPIMMPDZ256rrik:
4469 case VFIXUPIMMPDZ256rrikz:
4470 case VFIXUPIMMPDZrmbi:
4471 case VFIXUPIMMPDZrmbik:
4472 case VFIXUPIMMPDZrmbikz:
4473 case VFIXUPIMMPDZrmi:
4474 case VFIXUPIMMPDZrmik:
4475 case VFIXUPIMMPDZrmikz:
4476 case VFIXUPIMMPDZrri:
4477 case VFIXUPIMMPDZrrib:
4478 case VFIXUPIMMPDZrribk:
4479 case VFIXUPIMMPDZrribkz:
4480 case VFIXUPIMMPDZrrik:
4481 case VFIXUPIMMPDZrrikz:
4482 return true;
4483 }
4484 return false;
4485}
4486
4487bool isKANDND(unsigned Opcode) {
4488 return Opcode == KANDNDkk;
4489}
4490
4491bool isVMRESUME(unsigned Opcode) {
4492 return Opcode == VMRESUME;
4493}
4494
4495bool isCVTPD2DQ(unsigned Opcode) {
4496 switch (Opcode) {
4497 case CVTPD2DQrm:
4498 case CVTPD2DQrr:
4499 return true;
4500 }
4501 return false;
4502}
4503
4504bool isVFNMADD213PS(unsigned Opcode) {
4505 switch (Opcode) {
4506 case VFNMADD213PSYm:
4507 case VFNMADD213PSYr:
4508 case VFNMADD213PSZ128m:
4509 case VFNMADD213PSZ128mb:
4510 case VFNMADD213PSZ128mbk:
4511 case VFNMADD213PSZ128mbkz:
4512 case VFNMADD213PSZ128mk:
4513 case VFNMADD213PSZ128mkz:
4514 case VFNMADD213PSZ128r:
4515 case VFNMADD213PSZ128rk:
4516 case VFNMADD213PSZ128rkz:
4517 case VFNMADD213PSZ256m:
4518 case VFNMADD213PSZ256mb:
4519 case VFNMADD213PSZ256mbk:
4520 case VFNMADD213PSZ256mbkz:
4521 case VFNMADD213PSZ256mk:
4522 case VFNMADD213PSZ256mkz:
4523 case VFNMADD213PSZ256r:
4524 case VFNMADD213PSZ256rk:
4525 case VFNMADD213PSZ256rkz:
4526 case VFNMADD213PSZm:
4527 case VFNMADD213PSZmb:
4528 case VFNMADD213PSZmbk:
4529 case VFNMADD213PSZmbkz:
4530 case VFNMADD213PSZmk:
4531 case VFNMADD213PSZmkz:
4532 case VFNMADD213PSZr:
4533 case VFNMADD213PSZrb:
4534 case VFNMADD213PSZrbk:
4535 case VFNMADD213PSZrbkz:
4536 case VFNMADD213PSZrk:
4537 case VFNMADD213PSZrkz:
4538 case VFNMADD213PSm:
4539 case VFNMADD213PSr:
4540 return true;
4541 }
4542 return false;
4543}
4544
4545bool isVPEXTRD(unsigned Opcode) {
4546 switch (Opcode) {
4547 case VPEXTRDZmri:
4548 case VPEXTRDZrri:
4549 case VPEXTRDmri:
4550 case VPEXTRDrri:
4551 return true;
4552 }
4553 return false;
4554}
4555
4556bool isPACKUSWB(unsigned Opcode) {
4557 switch (Opcode) {
4558 case MMX_PACKUSWBrm:
4559 case MMX_PACKUSWBrr:
4560 case PACKUSWBrm:
4561 case PACKUSWBrr:
4562 return true;
4563 }
4564 return false;
4565}
4566
4567bool isVEXTRACTI32X8(unsigned Opcode) {
4568 switch (Opcode) {
4569 case VEXTRACTI32X8Zmri:
4570 case VEXTRACTI32X8Zmrik:
4571 case VEXTRACTI32X8Zrri:
4572 case VEXTRACTI32X8Zrrik:
4573 case VEXTRACTI32X8Zrrikz:
4574 return true;
4575 }
4576 return false;
4577}
4578
4579bool isVHADDPD(unsigned Opcode) {
4580 switch (Opcode) {
4581 case VHADDPDYrm:
4582 case VHADDPDYrr:
4583 case VHADDPDrm:
4584 case VHADDPDrr:
4585 return true;
4586 }
4587 return false;
4588}
4589
4590bool isVPSADBW(unsigned Opcode) {
4591 switch (Opcode) {
4592 case VPSADBWYrm:
4593 case VPSADBWYrr:
4594 case VPSADBWZ128rm:
4595 case VPSADBWZ128rr:
4596 case VPSADBWZ256rm:
4597 case VPSADBWZ256rr:
4598 case VPSADBWZrm:
4599 case VPSADBWZrr:
4600 case VPSADBWrm:
4601 case VPSADBWrr:
4602 return true;
4603 }
4604 return false;
4605}
4606
4607bool isMOVDQ2Q(unsigned Opcode) {
4608 return Opcode == MMX_MOVDQ2Qrr;
4609}
4610
4611bool isPUNPCKHBW(unsigned Opcode) {
4612 switch (Opcode) {
4613 case MMX_PUNPCKHBWrm:
4614 case MMX_PUNPCKHBWrr:
4615 case PUNPCKHBWrm:
4616 case PUNPCKHBWrr:
4617 return true;
4618 }
4619 return false;
4620}
4621
4622bool isXOR(unsigned Opcode) {
4623 switch (Opcode) {
4624 case XOR16i16:
4625 case XOR16mi:
4626 case XOR16mi8:
4627 case XOR16mi8_EVEX:
4628 case XOR16mi8_ND:
4629 case XOR16mi8_NF:
4630 case XOR16mi8_NF_ND:
4631 case XOR16mi_EVEX:
4632 case XOR16mi_ND:
4633 case XOR16mi_NF:
4634 case XOR16mi_NF_ND:
4635 case XOR16mr:
4636 case XOR16mr_EVEX:
4637 case XOR16mr_ND:
4638 case XOR16mr_NF:
4639 case XOR16mr_NF_ND:
4640 case XOR16ri:
4641 case XOR16ri8:
4642 case XOR16ri8_EVEX:
4643 case XOR16ri8_ND:
4644 case XOR16ri8_NF:
4645 case XOR16ri8_NF_ND:
4646 case XOR16ri_EVEX:
4647 case XOR16ri_ND:
4648 case XOR16ri_NF:
4649 case XOR16ri_NF_ND:
4650 case XOR16rm:
4651 case XOR16rm_EVEX:
4652 case XOR16rm_ND:
4653 case XOR16rm_NF:
4654 case XOR16rm_NF_ND:
4655 case XOR16rr:
4656 case XOR16rr_EVEX:
4657 case XOR16rr_EVEX_REV:
4658 case XOR16rr_ND:
4659 case XOR16rr_ND_REV:
4660 case XOR16rr_NF:
4661 case XOR16rr_NF_ND:
4662 case XOR16rr_NF_ND_REV:
4663 case XOR16rr_NF_REV:
4664 case XOR16rr_REV:
4665 case XOR32i32:
4666 case XOR32mi:
4667 case XOR32mi8:
4668 case XOR32mi8_EVEX:
4669 case XOR32mi8_ND:
4670 case XOR32mi8_NF:
4671 case XOR32mi8_NF_ND:
4672 case XOR32mi_EVEX:
4673 case XOR32mi_ND:
4674 case XOR32mi_NF:
4675 case XOR32mi_NF_ND:
4676 case XOR32mr:
4677 case XOR32mr_EVEX:
4678 case XOR32mr_ND:
4679 case XOR32mr_NF:
4680 case XOR32mr_NF_ND:
4681 case XOR32ri:
4682 case XOR32ri8:
4683 case XOR32ri8_EVEX:
4684 case XOR32ri8_ND:
4685 case XOR32ri8_NF:
4686 case XOR32ri8_NF_ND:
4687 case XOR32ri_EVEX:
4688 case XOR32ri_ND:
4689 case XOR32ri_NF:
4690 case XOR32ri_NF_ND:
4691 case XOR32rm:
4692 case XOR32rm_EVEX:
4693 case XOR32rm_ND:
4694 case XOR32rm_NF:
4695 case XOR32rm_NF_ND:
4696 case XOR32rr:
4697 case XOR32rr_EVEX:
4698 case XOR32rr_EVEX_REV:
4699 case XOR32rr_ND:
4700 case XOR32rr_ND_REV:
4701 case XOR32rr_NF:
4702 case XOR32rr_NF_ND:
4703 case XOR32rr_NF_ND_REV:
4704 case XOR32rr_NF_REV:
4705 case XOR32rr_REV:
4706 case XOR64i32:
4707 case XOR64mi32:
4708 case XOR64mi32_EVEX:
4709 case XOR64mi32_ND:
4710 case XOR64mi32_NF:
4711 case XOR64mi32_NF_ND:
4712 case XOR64mi8:
4713 case XOR64mi8_EVEX:
4714 case XOR64mi8_ND:
4715 case XOR64mi8_NF:
4716 case XOR64mi8_NF_ND:
4717 case XOR64mr:
4718 case XOR64mr_EVEX:
4719 case XOR64mr_ND:
4720 case XOR64mr_NF:
4721 case XOR64mr_NF_ND:
4722 case XOR64ri32:
4723 case XOR64ri32_EVEX:
4724 case XOR64ri32_ND:
4725 case XOR64ri32_NF:
4726 case XOR64ri32_NF_ND:
4727 case XOR64ri8:
4728 case XOR64ri8_EVEX:
4729 case XOR64ri8_ND:
4730 case XOR64ri8_NF:
4731 case XOR64ri8_NF_ND:
4732 case XOR64rm:
4733 case XOR64rm_EVEX:
4734 case XOR64rm_ND:
4735 case XOR64rm_NF:
4736 case XOR64rm_NF_ND:
4737 case XOR64rr:
4738 case XOR64rr_EVEX:
4739 case XOR64rr_EVEX_REV:
4740 case XOR64rr_ND:
4741 case XOR64rr_ND_REV:
4742 case XOR64rr_NF:
4743 case XOR64rr_NF_ND:
4744 case XOR64rr_NF_ND_REV:
4745 case XOR64rr_NF_REV:
4746 case XOR64rr_REV:
4747 case XOR8i8:
4748 case XOR8mi:
4749 case XOR8mi8:
4750 case XOR8mi_EVEX:
4751 case XOR8mi_ND:
4752 case XOR8mi_NF:
4753 case XOR8mi_NF_ND:
4754 case XOR8mr:
4755 case XOR8mr_EVEX:
4756 case XOR8mr_ND:
4757 case XOR8mr_NF:
4758 case XOR8mr_NF_ND:
4759 case XOR8ri:
4760 case XOR8ri8:
4761 case XOR8ri_EVEX:
4762 case XOR8ri_ND:
4763 case XOR8ri_NF:
4764 case XOR8ri_NF_ND:
4765 case XOR8rm:
4766 case XOR8rm_EVEX:
4767 case XOR8rm_ND:
4768 case XOR8rm_NF:
4769 case XOR8rm_NF_ND:
4770 case XOR8rr:
4771 case XOR8rr_EVEX:
4772 case XOR8rr_EVEX_REV:
4773 case XOR8rr_ND:
4774 case XOR8rr_ND_REV:
4775 case XOR8rr_NF:
4776 case XOR8rr_NF_ND:
4777 case XOR8rr_NF_ND_REV:
4778 case XOR8rr_NF_REV:
4779 case XOR8rr_REV:
4780 return true;
4781 }
4782 return false;
4783}
4784
4785bool isPSIGNB(unsigned Opcode) {
4786 switch (Opcode) {
4787 case MMX_PSIGNBrm:
4788 case MMX_PSIGNBrr:
4789 case PSIGNBrm:
4790 case PSIGNBrr:
4791 return true;
4792 }
4793 return false;
4794}
4795
4796bool isVPHADDSW(unsigned Opcode) {
4797 switch (Opcode) {
4798 case VPHADDSWYrm:
4799 case VPHADDSWYrr:
4800 case VPHADDSWrm:
4801 case VPHADDSWrr:
4802 return true;
4803 }
4804 return false;
4805}
4806
4807bool isFADDP(unsigned Opcode) {
4808 return Opcode == ADD_FPrST0;
4809}
4810
4811bool isNEG(unsigned Opcode) {
4812 switch (Opcode) {
4813 case NEG16m:
4814 case NEG16m_EVEX:
4815 case NEG16m_ND:
4816 case NEG16m_NF:
4817 case NEG16m_NF_ND:
4818 case NEG16r:
4819 case NEG16r_EVEX:
4820 case NEG16r_ND:
4821 case NEG16r_NF:
4822 case NEG16r_NF_ND:
4823 case NEG32m:
4824 case NEG32m_EVEX:
4825 case NEG32m_ND:
4826 case NEG32m_NF:
4827 case NEG32m_NF_ND:
4828 case NEG32r:
4829 case NEG32r_EVEX:
4830 case NEG32r_ND:
4831 case NEG32r_NF:
4832 case NEG32r_NF_ND:
4833 case NEG64m:
4834 case NEG64m_EVEX:
4835 case NEG64m_ND:
4836 case NEG64m_NF:
4837 case NEG64m_NF_ND:
4838 case NEG64r:
4839 case NEG64r_EVEX:
4840 case NEG64r_ND:
4841 case NEG64r_NF:
4842 case NEG64r_NF_ND:
4843 case NEG8m:
4844 case NEG8m_EVEX:
4845 case NEG8m_ND:
4846 case NEG8m_NF:
4847 case NEG8m_NF_ND:
4848 case NEG8r:
4849 case NEG8r_EVEX:
4850 case NEG8r_ND:
4851 case NEG8r_NF:
4852 case NEG8r_NF_ND:
4853 return true;
4854 }
4855 return false;
4856}
4857
4858bool isFLDLG2(unsigned Opcode) {
4859 return Opcode == FLDLG2;
4860}
4861
4862bool isFNOP(unsigned Opcode) {
4863 return Opcode == FNOP;
4864}
4865
4866bool isVMINSS(unsigned Opcode) {
4867 switch (Opcode) {
4868 case VMINSSZrm_Int:
4869 case VMINSSZrmk_Int:
4870 case VMINSSZrmkz_Int:
4871 case VMINSSZrr_Int:
4872 case VMINSSZrrb_Int:
4873 case VMINSSZrrbk_Int:
4874 case VMINSSZrrbkz_Int:
4875 case VMINSSZrrk_Int:
4876 case VMINSSZrrkz_Int:
4877 case VMINSSrm_Int:
4878 case VMINSSrr_Int:
4879 return true;
4880 }
4881 return false;
4882}
4883
4884bool isPCMPISTRM(unsigned Opcode) {
4885 switch (Opcode) {
4886 case PCMPISTRMrmi:
4887 case PCMPISTRMrri:
4888 return true;
4889 }
4890 return false;
4891}
4892
4893bool isVFMADD132SS(unsigned Opcode) {
4894 switch (Opcode) {
4895 case VFMADD132SSZm_Int:
4896 case VFMADD132SSZmk_Int:
4897 case VFMADD132SSZmkz_Int:
4898 case VFMADD132SSZr_Int:
4899 case VFMADD132SSZrb_Int:
4900 case VFMADD132SSZrbk_Int:
4901 case VFMADD132SSZrbkz_Int:
4902 case VFMADD132SSZrk_Int:
4903 case VFMADD132SSZrkz_Int:
4904 case VFMADD132SSm_Int:
4905 case VFMADD132SSr_Int:
4906 return true;
4907 }
4908 return false;
4909}
4910
4911bool isFDIVRP(unsigned Opcode) {
4912 return Opcode == DIVR_FPrST0;
4913}
4914
4915bool isPUSHAL(unsigned Opcode) {
4916 return Opcode == PUSHA32;
4917}
4918
4919bool isSUBSD(unsigned Opcode) {
4920 switch (Opcode) {
4921 case SUBSDrm_Int:
4922 case SUBSDrr_Int:
4923 return true;
4924 }
4925 return false;
4926}
4927
4928bool isVPBLENDMQ(unsigned Opcode) {
4929 switch (Opcode) {
4930 case VPBLENDMQZ128rm:
4931 case VPBLENDMQZ128rmb:
4932 case VPBLENDMQZ128rmbk:
4933 case VPBLENDMQZ128rmbkz:
4934 case VPBLENDMQZ128rmk:
4935 case VPBLENDMQZ128rmkz:
4936 case VPBLENDMQZ128rr:
4937 case VPBLENDMQZ128rrk:
4938 case VPBLENDMQZ128rrkz:
4939 case VPBLENDMQZ256rm:
4940 case VPBLENDMQZ256rmb:
4941 case VPBLENDMQZ256rmbk:
4942 case VPBLENDMQZ256rmbkz:
4943 case VPBLENDMQZ256rmk:
4944 case VPBLENDMQZ256rmkz:
4945 case VPBLENDMQZ256rr:
4946 case VPBLENDMQZ256rrk:
4947 case VPBLENDMQZ256rrkz:
4948 case VPBLENDMQZrm:
4949 case VPBLENDMQZrmb:
4950 case VPBLENDMQZrmbk:
4951 case VPBLENDMQZrmbkz:
4952 case VPBLENDMQZrmk:
4953 case VPBLENDMQZrmkz:
4954 case VPBLENDMQZrr:
4955 case VPBLENDMQZrrk:
4956 case VPBLENDMQZrrkz:
4957 return true;
4958 }
4959 return false;
4960}
4961
4962bool isVPMACSDQL(unsigned Opcode) {
4963 switch (Opcode) {
4964 case VPMACSDQLrm:
4965 case VPMACSDQLrr:
4966 return true;
4967 }
4968 return false;
4969}
4970
4971bool isVGATHERDPS(unsigned Opcode) {
4972 switch (Opcode) {
4973 case VGATHERDPSYrm:
4974 case VGATHERDPSZ128rm:
4975 case VGATHERDPSZ256rm:
4976 case VGATHERDPSZrm:
4977 case VGATHERDPSrm:
4978 return true;
4979 }
4980 return false;
4981}
4982
4983bool isRMPREAD(unsigned Opcode) {
4984 return Opcode == RMPREAD;
4985}
4986
4987bool isSYSRET(unsigned Opcode) {
4988 return Opcode == SYSRET;
4989}
4990
4991bool isVPADDB(unsigned Opcode) {
4992 switch (Opcode) {
4993 case VPADDBYrm:
4994 case VPADDBYrr:
4995 case VPADDBZ128rm:
4996 case VPADDBZ128rmk:
4997 case VPADDBZ128rmkz:
4998 case VPADDBZ128rr:
4999 case VPADDBZ128rrk:
5000 case VPADDBZ128rrkz:
5001 case VPADDBZ256rm:
5002 case VPADDBZ256rmk:
5003 case VPADDBZ256rmkz:
5004 case VPADDBZ256rr:
5005 case VPADDBZ256rrk:
5006 case VPADDBZ256rrkz:
5007 case VPADDBZrm:
5008 case VPADDBZrmk:
5009 case VPADDBZrmkz:
5010 case VPADDBZrr:
5011 case VPADDBZrrk:
5012 case VPADDBZrrkz:
5013 case VPADDBrm:
5014 case VPADDBrr:
5015 return true;
5016 }
5017 return false;
5018}
5019
5020bool isXEND(unsigned Opcode) {
5021 return Opcode == XEND;
5022}
5023
5024bool isWRSSD(unsigned Opcode) {
5025 switch (Opcode) {
5026 case WRSSD:
5027 case WRSSD_EVEX:
5028 return true;
5029 }
5030 return false;
5031}
5032
5033bool isVMINMAXSS(unsigned Opcode) {
5034 switch (Opcode) {
5035 case VMINMAXSSrmi_Int:
5036 case VMINMAXSSrmik_Int:
5037 case VMINMAXSSrmikz_Int:
5038 case VMINMAXSSrri_Int:
5039 case VMINMAXSSrrib_Int:
5040 case VMINMAXSSrribk_Int:
5041 case VMINMAXSSrribkz_Int:
5042 case VMINMAXSSrrik_Int:
5043 case VMINMAXSSrrikz_Int:
5044 return true;
5045 }
5046 return false;
5047}
5048
5049bool isVCVTDQ2PH(unsigned Opcode) {
5050 switch (Opcode) {
5051 case VCVTDQ2PHZ128rm:
5052 case VCVTDQ2PHZ128rmb:
5053 case VCVTDQ2PHZ128rmbk:
5054 case VCVTDQ2PHZ128rmbkz:
5055 case VCVTDQ2PHZ128rmk:
5056 case VCVTDQ2PHZ128rmkz:
5057 case VCVTDQ2PHZ128rr:
5058 case VCVTDQ2PHZ128rrk:
5059 case VCVTDQ2PHZ128rrkz:
5060 case VCVTDQ2PHZ256rm:
5061 case VCVTDQ2PHZ256rmb:
5062 case VCVTDQ2PHZ256rmbk:
5063 case VCVTDQ2PHZ256rmbkz:
5064 case VCVTDQ2PHZ256rmk:
5065 case VCVTDQ2PHZ256rmkz:
5066 case VCVTDQ2PHZ256rr:
5067 case VCVTDQ2PHZ256rrk:
5068 case VCVTDQ2PHZ256rrkz:
5069 case VCVTDQ2PHZrm:
5070 case VCVTDQ2PHZrmb:
5071 case VCVTDQ2PHZrmbk:
5072 case VCVTDQ2PHZrmbkz:
5073 case VCVTDQ2PHZrmk:
5074 case VCVTDQ2PHZrmkz:
5075 case VCVTDQ2PHZrr:
5076 case VCVTDQ2PHZrrb:
5077 case VCVTDQ2PHZrrbk:
5078 case VCVTDQ2PHZrrbkz:
5079 case VCVTDQ2PHZrrk:
5080 case VCVTDQ2PHZrrkz:
5081 return true;
5082 }
5083 return false;
5084}
5085
5086bool isCVTPD2PS(unsigned Opcode) {
5087 switch (Opcode) {
5088 case CVTPD2PSrm:
5089 case CVTPD2PSrr:
5090 return true;
5091 }
5092 return false;
5093}
5094
5095bool isMAXPD(unsigned Opcode) {
5096 switch (Opcode) {
5097 case MAXPDrm:
5098 case MAXPDrr:
5099 return true;
5100 }
5101 return false;
5102}
5103
5104bool isRCPSS(unsigned Opcode) {
5105 switch (Opcode) {
5106 case RCPSSm_Int:
5107 case RCPSSr_Int:
5108 return true;
5109 }
5110 return false;
5111}
5112
5113bool isVMOVAPD(unsigned Opcode) {
5114 switch (Opcode) {
5115 case VMOVAPDYmr:
5116 case VMOVAPDYrm:
5117 case VMOVAPDYrr:
5118 case VMOVAPDYrr_REV:
5119 case VMOVAPDZ128mr:
5120 case VMOVAPDZ128mrk:
5121 case VMOVAPDZ128rm:
5122 case VMOVAPDZ128rmk:
5123 case VMOVAPDZ128rmkz:
5124 case VMOVAPDZ128rr:
5125 case VMOVAPDZ128rr_REV:
5126 case VMOVAPDZ128rrk:
5127 case VMOVAPDZ128rrk_REV:
5128 case VMOVAPDZ128rrkz:
5129 case VMOVAPDZ128rrkz_REV:
5130 case VMOVAPDZ256mr:
5131 case VMOVAPDZ256mrk:
5132 case VMOVAPDZ256rm:
5133 case VMOVAPDZ256rmk:
5134 case VMOVAPDZ256rmkz:
5135 case VMOVAPDZ256rr:
5136 case VMOVAPDZ256rr_REV:
5137 case VMOVAPDZ256rrk:
5138 case VMOVAPDZ256rrk_REV:
5139 case VMOVAPDZ256rrkz:
5140 case VMOVAPDZ256rrkz_REV:
5141 case VMOVAPDZmr:
5142 case VMOVAPDZmrk:
5143 case VMOVAPDZrm:
5144 case VMOVAPDZrmk:
5145 case VMOVAPDZrmkz:
5146 case VMOVAPDZrr:
5147 case VMOVAPDZrr_REV:
5148 case VMOVAPDZrrk:
5149 case VMOVAPDZrrk_REV:
5150 case VMOVAPDZrrkz:
5151 case VMOVAPDZrrkz_REV:
5152 case VMOVAPDmr:
5153 case VMOVAPDrm:
5154 case VMOVAPDrr:
5155 case VMOVAPDrr_REV:
5156 return true;
5157 }
5158 return false;
5159}
5160
5161bool isVPSUBSB(unsigned Opcode) {
5162 switch (Opcode) {
5163 case VPSUBSBYrm:
5164 case VPSUBSBYrr:
5165 case VPSUBSBZ128rm:
5166 case VPSUBSBZ128rmk:
5167 case VPSUBSBZ128rmkz:
5168 case VPSUBSBZ128rr:
5169 case VPSUBSBZ128rrk:
5170 case VPSUBSBZ128rrkz:
5171 case VPSUBSBZ256rm:
5172 case VPSUBSBZ256rmk:
5173 case VPSUBSBZ256rmkz:
5174 case VPSUBSBZ256rr:
5175 case VPSUBSBZ256rrk:
5176 case VPSUBSBZ256rrkz:
5177 case VPSUBSBZrm:
5178 case VPSUBSBZrmk:
5179 case VPSUBSBZrmkz:
5180 case VPSUBSBZrr:
5181 case VPSUBSBZrrk:
5182 case VPSUBSBZrrkz:
5183 case VPSUBSBrm:
5184 case VPSUBSBrr:
5185 return true;
5186 }
5187 return false;
5188}
5189
5190bool isRDTSC(unsigned Opcode) {
5191 return Opcode == RDTSC;
5192}
5193
5194bool isVCVTTPS2UDQS(unsigned Opcode) {
5195 switch (Opcode) {
5196 case VCVTTPS2UDQSZ128rm:
5197 case VCVTTPS2UDQSZ128rmb:
5198 case VCVTTPS2UDQSZ128rmbk:
5199 case VCVTTPS2UDQSZ128rmbkz:
5200 case VCVTTPS2UDQSZ128rmk:
5201 case VCVTTPS2UDQSZ128rmkz:
5202 case VCVTTPS2UDQSZ128rr:
5203 case VCVTTPS2UDQSZ128rrk:
5204 case VCVTTPS2UDQSZ128rrkz:
5205 case VCVTTPS2UDQSZ256rm:
5206 case VCVTTPS2UDQSZ256rmb:
5207 case VCVTTPS2UDQSZ256rmbk:
5208 case VCVTTPS2UDQSZ256rmbkz:
5209 case VCVTTPS2UDQSZ256rmk:
5210 case VCVTTPS2UDQSZ256rmkz:
5211 case VCVTTPS2UDQSZ256rr:
5212 case VCVTTPS2UDQSZ256rrk:
5213 case VCVTTPS2UDQSZ256rrkz:
5214 case VCVTTPS2UDQSZrm:
5215 case VCVTTPS2UDQSZrmb:
5216 case VCVTTPS2UDQSZrmbk:
5217 case VCVTTPS2UDQSZrmbkz:
5218 case VCVTTPS2UDQSZrmk:
5219 case VCVTTPS2UDQSZrmkz:
5220 case VCVTTPS2UDQSZrr:
5221 case VCVTTPS2UDQSZrrb:
5222 case VCVTTPS2UDQSZrrbk:
5223 case VCVTTPS2UDQSZrrbkz:
5224 case VCVTTPS2UDQSZrrk:
5225 case VCVTTPS2UDQSZrrkz:
5226 return true;
5227 }
5228 return false;
5229}
5230
5231bool isVPMADCSSWD(unsigned Opcode) {
5232 switch (Opcode) {
5233 case VPMADCSSWDrm:
5234 case VPMADCSSWDrr:
5235 return true;
5236 }
5237 return false;
5238}
5239
5240bool isVFNMADD213PH(unsigned Opcode) {
5241 switch (Opcode) {
5242 case VFNMADD213PHZ128m:
5243 case VFNMADD213PHZ128mb:
5244 case VFNMADD213PHZ128mbk:
5245 case VFNMADD213PHZ128mbkz:
5246 case VFNMADD213PHZ128mk:
5247 case VFNMADD213PHZ128mkz:
5248 case VFNMADD213PHZ128r:
5249 case VFNMADD213PHZ128rk:
5250 case VFNMADD213PHZ128rkz:
5251 case VFNMADD213PHZ256m:
5252 case VFNMADD213PHZ256mb:
5253 case VFNMADD213PHZ256mbk:
5254 case VFNMADD213PHZ256mbkz:
5255 case VFNMADD213PHZ256mk:
5256 case VFNMADD213PHZ256mkz:
5257 case VFNMADD213PHZ256r:
5258 case VFNMADD213PHZ256rk:
5259 case VFNMADD213PHZ256rkz:
5260 case VFNMADD213PHZm:
5261 case VFNMADD213PHZmb:
5262 case VFNMADD213PHZmbk:
5263 case VFNMADD213PHZmbkz:
5264 case VFNMADD213PHZmk:
5265 case VFNMADD213PHZmkz:
5266 case VFNMADD213PHZr:
5267 case VFNMADD213PHZrb:
5268 case VFNMADD213PHZrbk:
5269 case VFNMADD213PHZrbkz:
5270 case VFNMADD213PHZrk:
5271 case VFNMADD213PHZrkz:
5272 return true;
5273 }
5274 return false;
5275}
5276
5277bool isVGF2P8AFFINEQB(unsigned Opcode) {
5278 switch (Opcode) {
5279 case VGF2P8AFFINEQBYrmi:
5280 case VGF2P8AFFINEQBYrri:
5281 case VGF2P8AFFINEQBZ128rmbi:
5282 case VGF2P8AFFINEQBZ128rmbik:
5283 case VGF2P8AFFINEQBZ128rmbikz:
5284 case VGF2P8AFFINEQBZ128rmi:
5285 case VGF2P8AFFINEQBZ128rmik:
5286 case VGF2P8AFFINEQBZ128rmikz:
5287 case VGF2P8AFFINEQBZ128rri:
5288 case VGF2P8AFFINEQBZ128rrik:
5289 case VGF2P8AFFINEQBZ128rrikz:
5290 case VGF2P8AFFINEQBZ256rmbi:
5291 case VGF2P8AFFINEQBZ256rmbik:
5292 case VGF2P8AFFINEQBZ256rmbikz:
5293 case VGF2P8AFFINEQBZ256rmi:
5294 case VGF2P8AFFINEQBZ256rmik:
5295 case VGF2P8AFFINEQBZ256rmikz:
5296 case VGF2P8AFFINEQBZ256rri:
5297 case VGF2P8AFFINEQBZ256rrik:
5298 case VGF2P8AFFINEQBZ256rrikz:
5299 case VGF2P8AFFINEQBZrmbi:
5300 case VGF2P8AFFINEQBZrmbik:
5301 case VGF2P8AFFINEQBZrmbikz:
5302 case VGF2P8AFFINEQBZrmi:
5303 case VGF2P8AFFINEQBZrmik:
5304 case VGF2P8AFFINEQBZrmikz:
5305 case VGF2P8AFFINEQBZrri:
5306 case VGF2P8AFFINEQBZrrik:
5307 case VGF2P8AFFINEQBZrrikz:
5308 case VGF2P8AFFINEQBrmi:
5309 case VGF2P8AFFINEQBrri:
5310 return true;
5311 }
5312 return false;
5313}
5314
5315bool isPMOVZXWD(unsigned Opcode) {
5316 switch (Opcode) {
5317 case PMOVZXWDrm:
5318 case PMOVZXWDrr:
5319 return true;
5320 }
5321 return false;
5322}
5323
5324bool isPMINUD(unsigned Opcode) {
5325 switch (Opcode) {
5326 case PMINUDrm:
5327 case PMINUDrr:
5328 return true;
5329 }
5330 return false;
5331}
5332
5333bool isXSUSLDTRK(unsigned Opcode) {
5334 return Opcode == XSUSLDTRK;
5335}
5336
5337bool isVCVTPH2UW(unsigned Opcode) {
5338 switch (Opcode) {
5339 case VCVTPH2UWZ128rm:
5340 case VCVTPH2UWZ128rmb:
5341 case VCVTPH2UWZ128rmbk:
5342 case VCVTPH2UWZ128rmbkz:
5343 case VCVTPH2UWZ128rmk:
5344 case VCVTPH2UWZ128rmkz:
5345 case VCVTPH2UWZ128rr:
5346 case VCVTPH2UWZ128rrk:
5347 case VCVTPH2UWZ128rrkz:
5348 case VCVTPH2UWZ256rm:
5349 case VCVTPH2UWZ256rmb:
5350 case VCVTPH2UWZ256rmbk:
5351 case VCVTPH2UWZ256rmbkz:
5352 case VCVTPH2UWZ256rmk:
5353 case VCVTPH2UWZ256rmkz:
5354 case VCVTPH2UWZ256rr:
5355 case VCVTPH2UWZ256rrk:
5356 case VCVTPH2UWZ256rrkz:
5357 case VCVTPH2UWZrm:
5358 case VCVTPH2UWZrmb:
5359 case VCVTPH2UWZrmbk:
5360 case VCVTPH2UWZrmbkz:
5361 case VCVTPH2UWZrmk:
5362 case VCVTPH2UWZrmkz:
5363 case VCVTPH2UWZrr:
5364 case VCVTPH2UWZrrb:
5365 case VCVTPH2UWZrrbk:
5366 case VCVTPH2UWZrrbkz:
5367 case VCVTPH2UWZrrk:
5368 case VCVTPH2UWZrrkz:
5369 return true;
5370 }
5371 return false;
5372}
5373
5374bool isPADDSW(unsigned Opcode) {
5375 switch (Opcode) {
5376 case MMX_PADDSWrm:
5377 case MMX_PADDSWrr:
5378 case PADDSWrm:
5379 case PADDSWrr:
5380 return true;
5381 }
5382 return false;
5383}
5384
5385bool isLFENCE(unsigned Opcode) {
5386 return Opcode == LFENCE;
5387}
5388
5389bool isCRC32(unsigned Opcode) {
5390 switch (Opcode) {
5391 case CRC32r32m16:
5392 case CRC32r32m16_EVEX:
5393 case CRC32r32m32:
5394 case CRC32r32m32_EVEX:
5395 case CRC32r32m8:
5396 case CRC32r32m8_EVEX:
5397 case CRC32r32r16:
5398 case CRC32r32r16_EVEX:
5399 case CRC32r32r32:
5400 case CRC32r32r32_EVEX:
5401 case CRC32r32r8:
5402 case CRC32r32r8_EVEX:
5403 case CRC32r64m64:
5404 case CRC32r64m64_EVEX:
5405 case CRC32r64m8:
5406 case CRC32r64m8_EVEX:
5407 case CRC32r64r64:
5408 case CRC32r64r64_EVEX:
5409 case CRC32r64r8:
5410 case CRC32r64r8_EVEX:
5411 return true;
5412 }
5413 return false;
5414}
5415
5416bool isAESENCWIDE256KL(unsigned Opcode) {
5417 return Opcode == AESENCWIDE256KL;
5418}
5419
5420bool isMOVAPD(unsigned Opcode) {
5421 switch (Opcode) {
5422 case MOVAPDmr:
5423 case MOVAPDrm:
5424 case MOVAPDrr:
5425 case MOVAPDrr_REV:
5426 return true;
5427 }
5428 return false;
5429}
5430
5431bool isVFMADD213PS(unsigned Opcode) {
5432 switch (Opcode) {
5433 case VFMADD213PSYm:
5434 case VFMADD213PSYr:
5435 case VFMADD213PSZ128m:
5436 case VFMADD213PSZ128mb:
5437 case VFMADD213PSZ128mbk:
5438 case VFMADD213PSZ128mbkz:
5439 case VFMADD213PSZ128mk:
5440 case VFMADD213PSZ128mkz:
5441 case VFMADD213PSZ128r:
5442 case VFMADD213PSZ128rk:
5443 case VFMADD213PSZ128rkz:
5444 case VFMADD213PSZ256m:
5445 case VFMADD213PSZ256mb:
5446 case VFMADD213PSZ256mbk:
5447 case VFMADD213PSZ256mbkz:
5448 case VFMADD213PSZ256mk:
5449 case VFMADD213PSZ256mkz:
5450 case VFMADD213PSZ256r:
5451 case VFMADD213PSZ256rk:
5452 case VFMADD213PSZ256rkz:
5453 case VFMADD213PSZm:
5454 case VFMADD213PSZmb:
5455 case VFMADD213PSZmbk:
5456 case VFMADD213PSZmbkz:
5457 case VFMADD213PSZmk:
5458 case VFMADD213PSZmkz:
5459 case VFMADD213PSZr:
5460 case VFMADD213PSZrb:
5461 case VFMADD213PSZrbk:
5462 case VFMADD213PSZrbkz:
5463 case VFMADD213PSZrk:
5464 case VFMADD213PSZrkz:
5465 case VFMADD213PSm:
5466 case VFMADD213PSr:
5467 return true;
5468 }
5469 return false;
5470}
5471
5472bool isVPDPWUUDS(unsigned Opcode) {
5473 switch (Opcode) {
5474 case VPDPWUUDSYrm:
5475 case VPDPWUUDSYrr:
5476 case VPDPWUUDSZ128rm:
5477 case VPDPWUUDSZ128rmb:
5478 case VPDPWUUDSZ128rmbk:
5479 case VPDPWUUDSZ128rmbkz:
5480 case VPDPWUUDSZ128rmk:
5481 case VPDPWUUDSZ128rmkz:
5482 case VPDPWUUDSZ128rr:
5483 case VPDPWUUDSZ128rrk:
5484 case VPDPWUUDSZ128rrkz:
5485 case VPDPWUUDSZ256rm:
5486 case VPDPWUUDSZ256rmb:
5487 case VPDPWUUDSZ256rmbk:
5488 case VPDPWUUDSZ256rmbkz:
5489 case VPDPWUUDSZ256rmk:
5490 case VPDPWUUDSZ256rmkz:
5491 case VPDPWUUDSZ256rr:
5492 case VPDPWUUDSZ256rrk:
5493 case VPDPWUUDSZ256rrkz:
5494 case VPDPWUUDSZrm:
5495 case VPDPWUUDSZrmb:
5496 case VPDPWUUDSZrmbk:
5497 case VPDPWUUDSZrmbkz:
5498 case VPDPWUUDSZrmk:
5499 case VPDPWUUDSZrmkz:
5500 case VPDPWUUDSZrr:
5501 case VPDPWUUDSZrrk:
5502 case VPDPWUUDSZrrkz:
5503 case VPDPWUUDSrm:
5504 case VPDPWUUDSrr:
5505 return true;
5506 }
5507 return false;
5508}
5509
5510bool isMOVSLDUP(unsigned Opcode) {
5511 switch (Opcode) {
5512 case MOVSLDUPrm:
5513 case MOVSLDUPrr:
5514 return true;
5515 }
5516 return false;
5517}
5518
5519bool isCLDEMOTE(unsigned Opcode) {
5520 return Opcode == CLDEMOTE;
5521}
5522
5523bool isVFNMADD231PS(unsigned Opcode) {
5524 switch (Opcode) {
5525 case VFNMADD231PSYm:
5526 case VFNMADD231PSYr:
5527 case VFNMADD231PSZ128m:
5528 case VFNMADD231PSZ128mb:
5529 case VFNMADD231PSZ128mbk:
5530 case VFNMADD231PSZ128mbkz:
5531 case VFNMADD231PSZ128mk:
5532 case VFNMADD231PSZ128mkz:
5533 case VFNMADD231PSZ128r:
5534 case VFNMADD231PSZ128rk:
5535 case VFNMADD231PSZ128rkz:
5536 case VFNMADD231PSZ256m:
5537 case VFNMADD231PSZ256mb:
5538 case VFNMADD231PSZ256mbk:
5539 case VFNMADD231PSZ256mbkz:
5540 case VFNMADD231PSZ256mk:
5541 case VFNMADD231PSZ256mkz:
5542 case VFNMADD231PSZ256r:
5543 case VFNMADD231PSZ256rk:
5544 case VFNMADD231PSZ256rkz:
5545 case VFNMADD231PSZm:
5546 case VFNMADD231PSZmb:
5547 case VFNMADD231PSZmbk:
5548 case VFNMADD231PSZmbkz:
5549 case VFNMADD231PSZmk:
5550 case VFNMADD231PSZmkz:
5551 case VFNMADD231PSZr:
5552 case VFNMADD231PSZrb:
5553 case VFNMADD231PSZrbk:
5554 case VFNMADD231PSZrbkz:
5555 case VFNMADD231PSZrk:
5556 case VFNMADD231PSZrkz:
5557 case VFNMADD231PSm:
5558 case VFNMADD231PSr:
5559 return true;
5560 }
5561 return false;
5562}
5563
5564bool isVMOVMSKPD(unsigned Opcode) {
5565 switch (Opcode) {
5566 case VMOVMSKPDYrr:
5567 case VMOVMSKPDrr:
5568 return true;
5569 }
5570 return false;
5571}
5572
5573bool isPREFETCHT0(unsigned Opcode) {
5574 return Opcode == PREFETCHT0;
5575}
5576
5577bool isVCVTNEOBF162PS(unsigned Opcode) {
5578 switch (Opcode) {
5579 case VCVTNEOBF162PSYrm:
5580 case VCVTNEOBF162PSrm:
5581 return true;
5582 }
5583 return false;
5584}
5585
5586bool isVPCMPUD(unsigned Opcode) {
5587 switch (Opcode) {
5588 case VPCMPUDZ128rmbi:
5589 case VPCMPUDZ128rmbik:
5590 case VPCMPUDZ128rmi:
5591 case VPCMPUDZ128rmik:
5592 case VPCMPUDZ128rri:
5593 case VPCMPUDZ128rrik:
5594 case VPCMPUDZ256rmbi:
5595 case VPCMPUDZ256rmbik:
5596 case VPCMPUDZ256rmi:
5597 case VPCMPUDZ256rmik:
5598 case VPCMPUDZ256rri:
5599 case VPCMPUDZ256rrik:
5600 case VPCMPUDZrmbi:
5601 case VPCMPUDZrmbik:
5602 case VPCMPUDZrmi:
5603 case VPCMPUDZrmik:
5604 case VPCMPUDZrri:
5605 case VPCMPUDZrrik:
5606 return true;
5607 }
5608 return false;
5609}
5610
5611bool isVMAXSD(unsigned Opcode) {
5612 switch (Opcode) {
5613 case VMAXSDZrm_Int:
5614 case VMAXSDZrmk_Int:
5615 case VMAXSDZrmkz_Int:
5616 case VMAXSDZrr_Int:
5617 case VMAXSDZrrb_Int:
5618 case VMAXSDZrrbk_Int:
5619 case VMAXSDZrrbkz_Int:
5620 case VMAXSDZrrk_Int:
5621 case VMAXSDZrrkz_Int:
5622 case VMAXSDrm_Int:
5623 case VMAXSDrr_Int:
5624 return true;
5625 }
5626 return false;
5627}
5628
5629bool isVRCP28SD(unsigned Opcode) {
5630 switch (Opcode) {
5631 case VRCP28SDZm:
5632 case VRCP28SDZmk:
5633 case VRCP28SDZmkz:
5634 case VRCP28SDZr:
5635 case VRCP28SDZrb:
5636 case VRCP28SDZrbk:
5637 case VRCP28SDZrbkz:
5638 case VRCP28SDZrk:
5639 case VRCP28SDZrkz:
5640 return true;
5641 }
5642 return false;
5643}
5644
5645bool isVMAXPS(unsigned Opcode) {
5646 switch (Opcode) {
5647 case VMAXPSYrm:
5648 case VMAXPSYrr:
5649 case VMAXPSZ128rm:
5650 case VMAXPSZ128rmb:
5651 case VMAXPSZ128rmbk:
5652 case VMAXPSZ128rmbkz:
5653 case VMAXPSZ128rmk:
5654 case VMAXPSZ128rmkz:
5655 case VMAXPSZ128rr:
5656 case VMAXPSZ128rrk:
5657 case VMAXPSZ128rrkz:
5658 case VMAXPSZ256rm:
5659 case VMAXPSZ256rmb:
5660 case VMAXPSZ256rmbk:
5661 case VMAXPSZ256rmbkz:
5662 case VMAXPSZ256rmk:
5663 case VMAXPSZ256rmkz:
5664 case VMAXPSZ256rr:
5665 case VMAXPSZ256rrk:
5666 case VMAXPSZ256rrkz:
5667 case VMAXPSZrm:
5668 case VMAXPSZrmb:
5669 case VMAXPSZrmbk:
5670 case VMAXPSZrmbkz:
5671 case VMAXPSZrmk:
5672 case VMAXPSZrmkz:
5673 case VMAXPSZrr:
5674 case VMAXPSZrrb:
5675 case VMAXPSZrrbk:
5676 case VMAXPSZrrbkz:
5677 case VMAXPSZrrk:
5678 case VMAXPSZrrkz:
5679 case VMAXPSrm:
5680 case VMAXPSrr:
5681 return true;
5682 }
5683 return false;
5684}
5685
5686bool isVPMOVD2M(unsigned Opcode) {
5687 switch (Opcode) {
5688 case VPMOVD2MZ128kr:
5689 case VPMOVD2MZ256kr:
5690 case VPMOVD2MZkr:
5691 return true;
5692 }
5693 return false;
5694}
5695
5696bool isVPMACSSWD(unsigned Opcode) {
5697 switch (Opcode) {
5698 case VPMACSSWDrm:
5699 case VPMACSSWDrr:
5700 return true;
5701 }
5702 return false;
5703}
5704
5705bool isVUCOMISD(unsigned Opcode) {
5706 switch (Opcode) {
5707 case VUCOMISDZrm:
5708 case VUCOMISDZrr:
5709 case VUCOMISDZrrb:
5710 case VUCOMISDrm:
5711 case VUCOMISDrr:
5712 return true;
5713 }
5714 return false;
5715}
5716
5717bool isLTR(unsigned Opcode) {
5718 switch (Opcode) {
5719 case LTRm:
5720 case LTRr:
5721 return true;
5722 }
5723 return false;
5724}
5725
5726bool isVCVTUSI2SH(unsigned Opcode) {
5727 switch (Opcode) {
5728 case VCVTUSI2SHZrm_Int:
5729 case VCVTUSI2SHZrr_Int:
5730 case VCVTUSI2SHZrrb_Int:
5731 case VCVTUSI642SHZrm_Int:
5732 case VCVTUSI642SHZrr_Int:
5733 case VCVTUSI642SHZrrb_Int:
5734 return true;
5735 }
5736 return false;
5737}
5738
5739bool isVSCATTERPF1QPS(unsigned Opcode) {
5740 return Opcode == VSCATTERPF1QPSm;
5741}
5742
5743bool isWRGSBASE(unsigned Opcode) {
5744 switch (Opcode) {
5745 case WRGSBASE:
5746 case WRGSBASE64:
5747 return true;
5748 }
5749 return false;
5750}
5751
5752bool isSTOSQ(unsigned Opcode) {
5753 return Opcode == STOSQ;
5754}
5755
5756bool isVSQRTSD(unsigned Opcode) {
5757 switch (Opcode) {
5758 case VSQRTSDZm_Int:
5759 case VSQRTSDZmk_Int:
5760 case VSQRTSDZmkz_Int:
5761 case VSQRTSDZr_Int:
5762 case VSQRTSDZrb_Int:
5763 case VSQRTSDZrbk_Int:
5764 case VSQRTSDZrbkz_Int:
5765 case VSQRTSDZrk_Int:
5766 case VSQRTSDZrkz_Int:
5767 case VSQRTSDm_Int:
5768 case VSQRTSDr_Int:
5769 return true;
5770 }
5771 return false;
5772}
5773
5774bool isVPERMIL2PD(unsigned Opcode) {
5775 switch (Opcode) {
5776 case VPERMIL2PDYmr:
5777 case VPERMIL2PDYrm:
5778 case VPERMIL2PDYrr:
5779 case VPERMIL2PDYrr_REV:
5780 case VPERMIL2PDmr:
5781 case VPERMIL2PDrm:
5782 case VPERMIL2PDrr:
5783 case VPERMIL2PDrr_REV:
5784 return true;
5785 }
5786 return false;
5787}
5788
5789bool isVFCMADDCSH(unsigned Opcode) {
5790 switch (Opcode) {
5791 case VFCMADDCSHZm:
5792 case VFCMADDCSHZmk:
5793 case VFCMADDCSHZmkz:
5794 case VFCMADDCSHZr:
5795 case VFCMADDCSHZrb:
5796 case VFCMADDCSHZrbk:
5797 case VFCMADDCSHZrbkz:
5798 case VFCMADDCSHZrk:
5799 case VFCMADDCSHZrkz:
5800 return true;
5801 }
5802 return false;
5803}
5804
5805bool isVFMADDSUB213PS(unsigned Opcode) {
5806 switch (Opcode) {
5807 case VFMADDSUB213PSYm:
5808 case VFMADDSUB213PSYr:
5809 case VFMADDSUB213PSZ128m:
5810 case VFMADDSUB213PSZ128mb:
5811 case VFMADDSUB213PSZ128mbk:
5812 case VFMADDSUB213PSZ128mbkz:
5813 case VFMADDSUB213PSZ128mk:
5814 case VFMADDSUB213PSZ128mkz:
5815 case VFMADDSUB213PSZ128r:
5816 case VFMADDSUB213PSZ128rk:
5817 case VFMADDSUB213PSZ128rkz:
5818 case VFMADDSUB213PSZ256m:
5819 case VFMADDSUB213PSZ256mb:
5820 case VFMADDSUB213PSZ256mbk:
5821 case VFMADDSUB213PSZ256mbkz:
5822 case VFMADDSUB213PSZ256mk:
5823 case VFMADDSUB213PSZ256mkz:
5824 case VFMADDSUB213PSZ256r:
5825 case VFMADDSUB213PSZ256rk:
5826 case VFMADDSUB213PSZ256rkz:
5827 case VFMADDSUB213PSZm:
5828 case VFMADDSUB213PSZmb:
5829 case VFMADDSUB213PSZmbk:
5830 case VFMADDSUB213PSZmbkz:
5831 case VFMADDSUB213PSZmk:
5832 case VFMADDSUB213PSZmkz:
5833 case VFMADDSUB213PSZr:
5834 case VFMADDSUB213PSZrb:
5835 case VFMADDSUB213PSZrbk:
5836 case VFMADDSUB213PSZrbkz:
5837 case VFMADDSUB213PSZrk:
5838 case VFMADDSUB213PSZrkz:
5839 case VFMADDSUB213PSm:
5840 case VFMADDSUB213PSr:
5841 return true;
5842 }
5843 return false;
5844}
5845
5846bool isPFSUB(unsigned Opcode) {
5847 switch (Opcode) {
5848 case PFSUBrm:
5849 case PFSUBrr:
5850 return true;
5851 }
5852 return false;
5853}
5854
5855bool isVSQRTSS(unsigned Opcode) {
5856 switch (Opcode) {
5857 case VSQRTSSZm_Int:
5858 case VSQRTSSZmk_Int:
5859 case VSQRTSSZmkz_Int:
5860 case VSQRTSSZr_Int:
5861 case VSQRTSSZrb_Int:
5862 case VSQRTSSZrbk_Int:
5863 case VSQRTSSZrbkz_Int:
5864 case VSQRTSSZrk_Int:
5865 case VSQRTSSZrkz_Int:
5866 case VSQRTSSm_Int:
5867 case VSQRTSSr_Int:
5868 return true;
5869 }
5870 return false;
5871}
5872
5873bool isVEXPANDPS(unsigned Opcode) {
5874 switch (Opcode) {
5875 case VEXPANDPSZ128rm:
5876 case VEXPANDPSZ128rmk:
5877 case VEXPANDPSZ128rmkz:
5878 case VEXPANDPSZ128rr:
5879 case VEXPANDPSZ128rrk:
5880 case VEXPANDPSZ128rrkz:
5881 case VEXPANDPSZ256rm:
5882 case VEXPANDPSZ256rmk:
5883 case VEXPANDPSZ256rmkz:
5884 case VEXPANDPSZ256rr:
5885 case VEXPANDPSZ256rrk:
5886 case VEXPANDPSZ256rrkz:
5887 case VEXPANDPSZrm:
5888 case VEXPANDPSZrmk:
5889 case VEXPANDPSZrmkz:
5890 case VEXPANDPSZrr:
5891 case VEXPANDPSZrrk:
5892 case VEXPANDPSZrrkz:
5893 return true;
5894 }
5895 return false;
5896}
5897
5898bool isVPCOMPRESSW(unsigned Opcode) {
5899 switch (Opcode) {
5900 case VPCOMPRESSWZ128mr:
5901 case VPCOMPRESSWZ128mrk:
5902 case VPCOMPRESSWZ128rr:
5903 case VPCOMPRESSWZ128rrk:
5904 case VPCOMPRESSWZ128rrkz:
5905 case VPCOMPRESSWZ256mr:
5906 case VPCOMPRESSWZ256mrk:
5907 case VPCOMPRESSWZ256rr:
5908 case VPCOMPRESSWZ256rrk:
5909 case VPCOMPRESSWZ256rrkz:
5910 case VPCOMPRESSWZmr:
5911 case VPCOMPRESSWZmrk:
5912 case VPCOMPRESSWZrr:
5913 case VPCOMPRESSWZrrk:
5914 case VPCOMPRESSWZrrkz:
5915 return true;
5916 }
5917 return false;
5918}
5919
5920bool isPEXTRD(unsigned Opcode) {
5921 switch (Opcode) {
5922 case PEXTRDmri:
5923 case PEXTRDrri:
5924 return true;
5925 }
5926 return false;
5927}
5928
5929bool isVCVTTPS2UQQS(unsigned Opcode) {
5930 switch (Opcode) {
5931 case VCVTTPS2UQQSZ128rm:
5932 case VCVTTPS2UQQSZ128rmb:
5933 case VCVTTPS2UQQSZ128rmbk:
5934 case VCVTTPS2UQQSZ128rmbkz:
5935 case VCVTTPS2UQQSZ128rmk:
5936 case VCVTTPS2UQQSZ128rmkz:
5937 case VCVTTPS2UQQSZ128rr:
5938 case VCVTTPS2UQQSZ128rrk:
5939 case VCVTTPS2UQQSZ128rrkz:
5940 case VCVTTPS2UQQSZ256rm:
5941 case VCVTTPS2UQQSZ256rmb:
5942 case VCVTTPS2UQQSZ256rmbk:
5943 case VCVTTPS2UQQSZ256rmbkz:
5944 case VCVTTPS2UQQSZ256rmk:
5945 case VCVTTPS2UQQSZ256rmkz:
5946 case VCVTTPS2UQQSZ256rr:
5947 case VCVTTPS2UQQSZ256rrb:
5948 case VCVTTPS2UQQSZ256rrbk:
5949 case VCVTTPS2UQQSZ256rrbkz:
5950 case VCVTTPS2UQQSZ256rrk:
5951 case VCVTTPS2UQQSZ256rrkz:
5952 case VCVTTPS2UQQSZrm:
5953 case VCVTTPS2UQQSZrmb:
5954 case VCVTTPS2UQQSZrmbk:
5955 case VCVTTPS2UQQSZrmbkz:
5956 case VCVTTPS2UQQSZrmk:
5957 case VCVTTPS2UQQSZrmkz:
5958 case VCVTTPS2UQQSZrr:
5959 case VCVTTPS2UQQSZrrb:
5960 case VCVTTPS2UQQSZrrbk:
5961 case VCVTTPS2UQQSZrrbkz:
5962 case VCVTTPS2UQQSZrrk:
5963 case VCVTTPS2UQQSZrrkz:
5964 return true;
5965 }
5966 return false;
5967}
5968
5969bool isSYSEXITQ(unsigned Opcode) {
5970 return Opcode == SYSEXIT64;
5971}
5972
5973bool isROUNDSD(unsigned Opcode) {
5974 switch (Opcode) {
5975 case ROUNDSDmi_Int:
5976 case ROUNDSDri_Int:
5977 return true;
5978 }
5979 return false;
5980}
5981
5982bool isVFMADD132BF16(unsigned Opcode) {
5983 switch (Opcode) {
5984 case VFMADD132BF16Z128m:
5985 case VFMADD132BF16Z128mb:
5986 case VFMADD132BF16Z128mbk:
5987 case VFMADD132BF16Z128mbkz:
5988 case VFMADD132BF16Z128mk:
5989 case VFMADD132BF16Z128mkz:
5990 case VFMADD132BF16Z128r:
5991 case VFMADD132BF16Z128rk:
5992 case VFMADD132BF16Z128rkz:
5993 case VFMADD132BF16Z256m:
5994 case VFMADD132BF16Z256mb:
5995 case VFMADD132BF16Z256mbk:
5996 case VFMADD132BF16Z256mbkz:
5997 case VFMADD132BF16Z256mk:
5998 case VFMADD132BF16Z256mkz:
5999 case VFMADD132BF16Z256r:
6000 case VFMADD132BF16Z256rk:
6001 case VFMADD132BF16Z256rkz:
6002 case VFMADD132BF16Zm:
6003 case VFMADD132BF16Zmb:
6004 case VFMADD132BF16Zmbk:
6005 case VFMADD132BF16Zmbkz:
6006 case VFMADD132BF16Zmk:
6007 case VFMADD132BF16Zmkz:
6008 case VFMADD132BF16Zr:
6009 case VFMADD132BF16Zrk:
6010 case VFMADD132BF16Zrkz:
6011 return true;
6012 }
6013 return false;
6014}
6015
6016bool isFCOM(unsigned Opcode) {
6017 switch (Opcode) {
6018 case COM_FST0r:
6019 case FCOM32m:
6020 case FCOM64m:
6021 return true;
6022 }
6023 return false;
6024}
6025
6026bool isVFNMSUBSS(unsigned Opcode) {
6027 switch (Opcode) {
6028 case VFNMSUBSS4mr:
6029 case VFNMSUBSS4rm:
6030 case VFNMSUBSS4rr:
6031 case VFNMSUBSS4rr_REV:
6032 return true;
6033 }
6034 return false;
6035}
6036
6037bool isKSHIFTLW(unsigned Opcode) {
6038 return Opcode == KSHIFTLWki;
6039}
6040
6041bool isVMPTRLD(unsigned Opcode) {
6042 return Opcode == VMPTRLDm;
6043}
6044
6045bool isSCASD(unsigned Opcode) {
6046 return Opcode == SCASL;
6047}
6048
6049bool isVAESDECLAST(unsigned Opcode) {
6050 switch (Opcode) {
6051 case VAESDECLASTYrm:
6052 case VAESDECLASTYrr:
6053 case VAESDECLASTZ128rm:
6054 case VAESDECLASTZ128rr:
6055 case VAESDECLASTZ256rm:
6056 case VAESDECLASTZ256rr:
6057 case VAESDECLASTZrm:
6058 case VAESDECLASTZrr:
6059 case VAESDECLASTrm:
6060 case VAESDECLASTrr:
6061 return true;
6062 }
6063 return false;
6064}
6065
6066bool isVFMADDSUBPS(unsigned Opcode) {
6067 switch (Opcode) {
6068 case VFMADDSUBPS4Ymr:
6069 case VFMADDSUBPS4Yrm:
6070 case VFMADDSUBPS4Yrr:
6071 case VFMADDSUBPS4Yrr_REV:
6072 case VFMADDSUBPS4mr:
6073 case VFMADDSUBPS4rm:
6074 case VFMADDSUBPS4rr:
6075 case VFMADDSUBPS4rr_REV:
6076 return true;
6077 }
6078 return false;
6079}
6080
6081bool isVCVTUQQ2PS(unsigned Opcode) {
6082 switch (Opcode) {
6083 case VCVTUQQ2PSZ128rm:
6084 case VCVTUQQ2PSZ128rmb:
6085 case VCVTUQQ2PSZ128rmbk:
6086 case VCVTUQQ2PSZ128rmbkz:
6087 case VCVTUQQ2PSZ128rmk:
6088 case VCVTUQQ2PSZ128rmkz:
6089 case VCVTUQQ2PSZ128rr:
6090 case VCVTUQQ2PSZ128rrk:
6091 case VCVTUQQ2PSZ128rrkz:
6092 case VCVTUQQ2PSZ256rm:
6093 case VCVTUQQ2PSZ256rmb:
6094 case VCVTUQQ2PSZ256rmbk:
6095 case VCVTUQQ2PSZ256rmbkz:
6096 case VCVTUQQ2PSZ256rmk:
6097 case VCVTUQQ2PSZ256rmkz:
6098 case VCVTUQQ2PSZ256rr:
6099 case VCVTUQQ2PSZ256rrk:
6100 case VCVTUQQ2PSZ256rrkz:
6101 case VCVTUQQ2PSZrm:
6102 case VCVTUQQ2PSZrmb:
6103 case VCVTUQQ2PSZrmbk:
6104 case VCVTUQQ2PSZrmbkz:
6105 case VCVTUQQ2PSZrmk:
6106 case VCVTUQQ2PSZrmkz:
6107 case VCVTUQQ2PSZrr:
6108 case VCVTUQQ2PSZrrb:
6109 case VCVTUQQ2PSZrrbk:
6110 case VCVTUQQ2PSZrrbkz:
6111 case VCVTUQQ2PSZrrk:
6112 case VCVTUQQ2PSZrrkz:
6113 return true;
6114 }
6115 return false;
6116}
6117
6118bool isVPMOVUSDB(unsigned Opcode) {
6119 switch (Opcode) {
6120 case VPMOVUSDBZ128mr:
6121 case VPMOVUSDBZ128mrk:
6122 case VPMOVUSDBZ128rr:
6123 case VPMOVUSDBZ128rrk:
6124 case VPMOVUSDBZ128rrkz:
6125 case VPMOVUSDBZ256mr:
6126 case VPMOVUSDBZ256mrk:
6127 case VPMOVUSDBZ256rr:
6128 case VPMOVUSDBZ256rrk:
6129 case VPMOVUSDBZ256rrkz:
6130 case VPMOVUSDBZmr:
6131 case VPMOVUSDBZmrk:
6132 case VPMOVUSDBZrr:
6133 case VPMOVUSDBZrrk:
6134 case VPMOVUSDBZrrkz:
6135 return true;
6136 }
6137 return false;
6138}
6139
6140bool isVPROTW(unsigned Opcode) {
6141 switch (Opcode) {
6142 case VPROTWmi:
6143 case VPROTWmr:
6144 case VPROTWri:
6145 case VPROTWrm:
6146 case VPROTWrr:
6147 case VPROTWrr_REV:
6148 return true;
6149 }
6150 return false;
6151}
6152
6153bool isVDPPS(unsigned Opcode) {
6154 switch (Opcode) {
6155 case VDPPSYrmi:
6156 case VDPPSYrri:
6157 case VDPPSrmi:
6158 case VDPPSrri:
6159 return true;
6160 }
6161 return false;
6162}
6163
6164bool isVRSQRT14PD(unsigned Opcode) {
6165 switch (Opcode) {
6166 case VRSQRT14PDZ128m:
6167 case VRSQRT14PDZ128mb:
6168 case VRSQRT14PDZ128mbk:
6169 case VRSQRT14PDZ128mbkz:
6170 case VRSQRT14PDZ128mk:
6171 case VRSQRT14PDZ128mkz:
6172 case VRSQRT14PDZ128r:
6173 case VRSQRT14PDZ128rk:
6174 case VRSQRT14PDZ128rkz:
6175 case VRSQRT14PDZ256m:
6176 case VRSQRT14PDZ256mb:
6177 case VRSQRT14PDZ256mbk:
6178 case VRSQRT14PDZ256mbkz:
6179 case VRSQRT14PDZ256mk:
6180 case VRSQRT14PDZ256mkz:
6181 case VRSQRT14PDZ256r:
6182 case VRSQRT14PDZ256rk:
6183 case VRSQRT14PDZ256rkz:
6184 case VRSQRT14PDZm:
6185 case VRSQRT14PDZmb:
6186 case VRSQRT14PDZmbk:
6187 case VRSQRT14PDZmbkz:
6188 case VRSQRT14PDZmk:
6189 case VRSQRT14PDZmkz:
6190 case VRSQRT14PDZr:
6191 case VRSQRT14PDZrk:
6192 case VRSQRT14PDZrkz:
6193 return true;
6194 }
6195 return false;
6196}
6197
6198bool isVTESTPD(unsigned Opcode) {
6199 switch (Opcode) {
6200 case VTESTPDYrm:
6201 case VTESTPDYrr:
6202 case VTESTPDrm:
6203 case VTESTPDrr:
6204 return true;
6205 }
6206 return false;
6207}
6208
6209bool isVFNMADD231SH(unsigned Opcode) {
6210 switch (Opcode) {
6211 case VFNMADD231SHZm_Int:
6212 case VFNMADD231SHZmk_Int:
6213 case VFNMADD231SHZmkz_Int:
6214 case VFNMADD231SHZr_Int:
6215 case VFNMADD231SHZrb_Int:
6216 case VFNMADD231SHZrbk_Int:
6217 case VFNMADD231SHZrbkz_Int:
6218 case VFNMADD231SHZrk_Int:
6219 case VFNMADD231SHZrkz_Int:
6220 return true;
6221 }
6222 return false;
6223}
6224
6225bool isENDBR64(unsigned Opcode) {
6226 return Opcode == ENDBR64;
6227}
6228
6229bool isMULSD(unsigned Opcode) {
6230 switch (Opcode) {
6231 case MULSDrm_Int:
6232 case MULSDrr_Int:
6233 return true;
6234 }
6235 return false;
6236}
6237
6238bool isXRSTORS(unsigned Opcode) {
6239 return Opcode == XRSTORS;
6240}
6241
6242bool isPREFETCHNTA(unsigned Opcode) {
6243 return Opcode == PREFETCHNTA;
6244}
6245
6246bool isVPCOMD(unsigned Opcode) {
6247 switch (Opcode) {
6248 case VPCOMDmi:
6249 case VPCOMDri:
6250 return true;
6251 }
6252 return false;
6253}
6254
6255bool isVPCOMUB(unsigned Opcode) {
6256 switch (Opcode) {
6257 case VPCOMUBmi:
6258 case VPCOMUBri:
6259 return true;
6260 }
6261 return false;
6262}
6263
6264bool isVPDPBSSD(unsigned Opcode) {
6265 switch (Opcode) {
6266 case VPDPBSSDYrm:
6267 case VPDPBSSDYrr:
6268 case VPDPBSSDZ128rm:
6269 case VPDPBSSDZ128rmb:
6270 case VPDPBSSDZ128rmbk:
6271 case VPDPBSSDZ128rmbkz:
6272 case VPDPBSSDZ128rmk:
6273 case VPDPBSSDZ128rmkz:
6274 case VPDPBSSDZ128rr:
6275 case VPDPBSSDZ128rrk:
6276 case VPDPBSSDZ128rrkz:
6277 case VPDPBSSDZ256rm:
6278 case VPDPBSSDZ256rmb:
6279 case VPDPBSSDZ256rmbk:
6280 case VPDPBSSDZ256rmbkz:
6281 case VPDPBSSDZ256rmk:
6282 case VPDPBSSDZ256rmkz:
6283 case VPDPBSSDZ256rr:
6284 case VPDPBSSDZ256rrk:
6285 case VPDPBSSDZ256rrkz:
6286 case VPDPBSSDZrm:
6287 case VPDPBSSDZrmb:
6288 case VPDPBSSDZrmbk:
6289 case VPDPBSSDZrmbkz:
6290 case VPDPBSSDZrmk:
6291 case VPDPBSSDZrmkz:
6292 case VPDPBSSDZrr:
6293 case VPDPBSSDZrrk:
6294 case VPDPBSSDZrrkz:
6295 case VPDPBSSDrm:
6296 case VPDPBSSDrr:
6297 return true;
6298 }
6299 return false;
6300}
6301
6302bool isVPHSUBD(unsigned Opcode) {
6303 switch (Opcode) {
6304 case VPHSUBDYrm:
6305 case VPHSUBDYrr:
6306 case VPHSUBDrm:
6307 case VPHSUBDrr:
6308 return true;
6309 }
6310 return false;
6311}
6312
6313bool isVBROADCASTI64X2(unsigned Opcode) {
6314 switch (Opcode) {
6315 case VBROADCASTI64X2Z256rm:
6316 case VBROADCASTI64X2Z256rmk:
6317 case VBROADCASTI64X2Z256rmkz:
6318 case VBROADCASTI64X2Zrm:
6319 case VBROADCASTI64X2Zrmk:
6320 case VBROADCASTI64X2Zrmkz:
6321 return true;
6322 }
6323 return false;
6324}
6325
6326bool isFPATAN(unsigned Opcode) {
6327 return Opcode == FPATAN;
6328}
6329
6330bool isLOOPE(unsigned Opcode) {
6331 return Opcode == LOOPE;
6332}
6333
6334bool isPCMPEQW(unsigned Opcode) {
6335 switch (Opcode) {
6336 case MMX_PCMPEQWrm:
6337 case MMX_PCMPEQWrr:
6338 case PCMPEQWrm:
6339 case PCMPEQWrr:
6340 return true;
6341 }
6342 return false;
6343}
6344
6345bool isVFMADDCSH(unsigned Opcode) {
6346 switch (Opcode) {
6347 case VFMADDCSHZm:
6348 case VFMADDCSHZmk:
6349 case VFMADDCSHZmkz:
6350 case VFMADDCSHZr:
6351 case VFMADDCSHZrb:
6352 case VFMADDCSHZrbk:
6353 case VFMADDCSHZrbkz:
6354 case VFMADDCSHZrk:
6355 case VFMADDCSHZrkz:
6356 return true;
6357 }
6358 return false;
6359}
6360
6361bool isMOVRS(unsigned Opcode) {
6362 switch (Opcode) {
6363 case MOVRS16rm:
6364 case MOVRS16rm_EVEX:
6365 case MOVRS32rm:
6366 case MOVRS32rm_EVEX:
6367 case MOVRS64rm:
6368 case MOVRS64rm_EVEX:
6369 case MOVRS8rm:
6370 case MOVRS8rm_EVEX:
6371 return true;
6372 }
6373 return false;
6374}
6375
6376bool isVFMSUBADD132PH(unsigned Opcode) {
6377 switch (Opcode) {
6378 case VFMSUBADD132PHZ128m:
6379 case VFMSUBADD132PHZ128mb:
6380 case VFMSUBADD132PHZ128mbk:
6381 case VFMSUBADD132PHZ128mbkz:
6382 case VFMSUBADD132PHZ128mk:
6383 case VFMSUBADD132PHZ128mkz:
6384 case VFMSUBADD132PHZ128r:
6385 case VFMSUBADD132PHZ128rk:
6386 case VFMSUBADD132PHZ128rkz:
6387 case VFMSUBADD132PHZ256m:
6388 case VFMSUBADD132PHZ256mb:
6389 case VFMSUBADD132PHZ256mbk:
6390 case VFMSUBADD132PHZ256mbkz:
6391 case VFMSUBADD132PHZ256mk:
6392 case VFMSUBADD132PHZ256mkz:
6393 case VFMSUBADD132PHZ256r:
6394 case VFMSUBADD132PHZ256rk:
6395 case VFMSUBADD132PHZ256rkz:
6396 case VFMSUBADD132PHZm:
6397 case VFMSUBADD132PHZmb:
6398 case VFMSUBADD132PHZmbk:
6399 case VFMSUBADD132PHZmbkz:
6400 case VFMSUBADD132PHZmk:
6401 case VFMSUBADD132PHZmkz:
6402 case VFMSUBADD132PHZr:
6403 case VFMSUBADD132PHZrb:
6404 case VFMSUBADD132PHZrbk:
6405 case VFMSUBADD132PHZrbkz:
6406 case VFMSUBADD132PHZrk:
6407 case VFMSUBADD132PHZrkz:
6408 return true;
6409 }
6410 return false;
6411}
6412
6413bool isKADDW(unsigned Opcode) {
6414 return Opcode == KADDWkk;
6415}
6416
6417bool isPTEST(unsigned Opcode) {
6418 switch (Opcode) {
6419 case PTESTrm:
6420 case PTESTrr:
6421 return true;
6422 }
6423 return false;
6424}
6425
6426bool isVPADDSB(unsigned Opcode) {
6427 switch (Opcode) {
6428 case VPADDSBYrm:
6429 case VPADDSBYrr:
6430 case VPADDSBZ128rm:
6431 case VPADDSBZ128rmk:
6432 case VPADDSBZ128rmkz:
6433 case VPADDSBZ128rr:
6434 case VPADDSBZ128rrk:
6435 case VPADDSBZ128rrkz:
6436 case VPADDSBZ256rm:
6437 case VPADDSBZ256rmk:
6438 case VPADDSBZ256rmkz:
6439 case VPADDSBZ256rr:
6440 case VPADDSBZ256rrk:
6441 case VPADDSBZ256rrkz:
6442 case VPADDSBZrm:
6443 case VPADDSBZrmk:
6444 case VPADDSBZrmkz:
6445 case VPADDSBZrr:
6446 case VPADDSBZrrk:
6447 case VPADDSBZrrkz:
6448 case VPADDSBrm:
6449 case VPADDSBrr:
6450 return true;
6451 }
6452 return false;
6453}
6454
6455bool isVRSQRT28PS(unsigned Opcode) {
6456 switch (Opcode) {
6457 case VRSQRT28PSZm:
6458 case VRSQRT28PSZmb:
6459 case VRSQRT28PSZmbk:
6460 case VRSQRT28PSZmbkz:
6461 case VRSQRT28PSZmk:
6462 case VRSQRT28PSZmkz:
6463 case VRSQRT28PSZr:
6464 case VRSQRT28PSZrb:
6465 case VRSQRT28PSZrbk:
6466 case VRSQRT28PSZrbkz:
6467 case VRSQRT28PSZrk:
6468 case VRSQRT28PSZrkz:
6469 return true;
6470 }
6471 return false;
6472}
6473
6474bool isVGF2P8AFFINEINVQB(unsigned Opcode) {
6475 switch (Opcode) {
6476 case VGF2P8AFFINEINVQBYrmi:
6477 case VGF2P8AFFINEINVQBYrri:
6478 case VGF2P8AFFINEINVQBZ128rmbi:
6479 case VGF2P8AFFINEINVQBZ128rmbik:
6480 case VGF2P8AFFINEINVQBZ128rmbikz:
6481 case VGF2P8AFFINEINVQBZ128rmi:
6482 case VGF2P8AFFINEINVQBZ128rmik:
6483 case VGF2P8AFFINEINVQBZ128rmikz:
6484 case VGF2P8AFFINEINVQBZ128rri:
6485 case VGF2P8AFFINEINVQBZ128rrik:
6486 case VGF2P8AFFINEINVQBZ128rrikz:
6487 case VGF2P8AFFINEINVQBZ256rmbi:
6488 case VGF2P8AFFINEINVQBZ256rmbik:
6489 case VGF2P8AFFINEINVQBZ256rmbikz:
6490 case VGF2P8AFFINEINVQBZ256rmi:
6491 case VGF2P8AFFINEINVQBZ256rmik:
6492 case VGF2P8AFFINEINVQBZ256rmikz:
6493 case VGF2P8AFFINEINVQBZ256rri:
6494 case VGF2P8AFFINEINVQBZ256rrik:
6495 case VGF2P8AFFINEINVQBZ256rrikz:
6496 case VGF2P8AFFINEINVQBZrmbi:
6497 case VGF2P8AFFINEINVQBZrmbik:
6498 case VGF2P8AFFINEINVQBZrmbikz:
6499 case VGF2P8AFFINEINVQBZrmi:
6500 case VGF2P8AFFINEINVQBZrmik:
6501 case VGF2P8AFFINEINVQBZrmikz:
6502 case VGF2P8AFFINEINVQBZrri:
6503 case VGF2P8AFFINEINVQBZrrik:
6504 case VGF2P8AFFINEINVQBZrrikz:
6505 case VGF2P8AFFINEINVQBrmi:
6506 case VGF2P8AFFINEINVQBrri:
6507 return true;
6508 }
6509 return false;
6510}
6511
6512bool isSERIALIZE(unsigned Opcode) {
6513 return Opcode == SERIALIZE;
6514}
6515
6516bool isVPHADDWQ(unsigned Opcode) {
6517 switch (Opcode) {
6518 case VPHADDWQrm:
6519 case VPHADDWQrr:
6520 return true;
6521 }
6522 return false;
6523}
6524
6525bool isVRNDSCALESH(unsigned Opcode) {
6526 switch (Opcode) {
6527 case VRNDSCALESHZrmi_Int:
6528 case VRNDSCALESHZrmik_Int:
6529 case VRNDSCALESHZrmikz_Int:
6530 case VRNDSCALESHZrri_Int:
6531 case VRNDSCALESHZrrib_Int:
6532 case VRNDSCALESHZrribk_Int:
6533 case VRNDSCALESHZrribkz_Int:
6534 case VRNDSCALESHZrrik_Int:
6535 case VRNDSCALESHZrrikz_Int:
6536 return true;
6537 }
6538 return false;
6539}
6540
6541bool isAAA(unsigned Opcode) {
6542 return Opcode == AAA;
6543}
6544
6545bool isVADDBF16(unsigned Opcode) {
6546 switch (Opcode) {
6547 case VADDBF16Z128rm:
6548 case VADDBF16Z128rmb:
6549 case VADDBF16Z128rmbk:
6550 case VADDBF16Z128rmbkz:
6551 case VADDBF16Z128rmk:
6552 case VADDBF16Z128rmkz:
6553 case VADDBF16Z128rr:
6554 case VADDBF16Z128rrk:
6555 case VADDBF16Z128rrkz:
6556 case VADDBF16Z256rm:
6557 case VADDBF16Z256rmb:
6558 case VADDBF16Z256rmbk:
6559 case VADDBF16Z256rmbkz:
6560 case VADDBF16Z256rmk:
6561 case VADDBF16Z256rmkz:
6562 case VADDBF16Z256rr:
6563 case VADDBF16Z256rrk:
6564 case VADDBF16Z256rrkz:
6565 case VADDBF16Zrm:
6566 case VADDBF16Zrmb:
6567 case VADDBF16Zrmbk:
6568 case VADDBF16Zrmbkz:
6569 case VADDBF16Zrmk:
6570 case VADDBF16Zrmkz:
6571 case VADDBF16Zrr:
6572 case VADDBF16Zrrk:
6573 case VADDBF16Zrrkz:
6574 return true;
6575 }
6576 return false;
6577}
6578
6579bool isWRMSRLIST(unsigned Opcode) {
6580 return Opcode == WRMSRLIST;
6581}
6582
6583bool isVCVTPH2PSX(unsigned Opcode) {
6584 switch (Opcode) {
6585 case VCVTPH2PSXZ128rm:
6586 case VCVTPH2PSXZ128rmb:
6587 case VCVTPH2PSXZ128rmbk:
6588 case VCVTPH2PSXZ128rmbkz:
6589 case VCVTPH2PSXZ128rmk:
6590 case VCVTPH2PSXZ128rmkz:
6591 case VCVTPH2PSXZ128rr:
6592 case VCVTPH2PSXZ128rrk:
6593 case VCVTPH2PSXZ128rrkz:
6594 case VCVTPH2PSXZ256rm:
6595 case VCVTPH2PSXZ256rmb:
6596 case VCVTPH2PSXZ256rmbk:
6597 case VCVTPH2PSXZ256rmbkz:
6598 case VCVTPH2PSXZ256rmk:
6599 case VCVTPH2PSXZ256rmkz:
6600 case VCVTPH2PSXZ256rr:
6601 case VCVTPH2PSXZ256rrk:
6602 case VCVTPH2PSXZ256rrkz:
6603 case VCVTPH2PSXZrm:
6604 case VCVTPH2PSXZrmb:
6605 case VCVTPH2PSXZrmbk:
6606 case VCVTPH2PSXZrmbkz:
6607 case VCVTPH2PSXZrmk:
6608 case VCVTPH2PSXZrmkz:
6609 case VCVTPH2PSXZrr:
6610 case VCVTPH2PSXZrrb:
6611 case VCVTPH2PSXZrrbk:
6612 case VCVTPH2PSXZrrbkz:
6613 case VCVTPH2PSXZrrk:
6614 case VCVTPH2PSXZrrkz:
6615 return true;
6616 }
6617 return false;
6618}
6619
6620bool isVFMSUB231PH(unsigned Opcode) {
6621 switch (Opcode) {
6622 case VFMSUB231PHZ128m:
6623 case VFMSUB231PHZ128mb:
6624 case VFMSUB231PHZ128mbk:
6625 case VFMSUB231PHZ128mbkz:
6626 case VFMSUB231PHZ128mk:
6627 case VFMSUB231PHZ128mkz:
6628 case VFMSUB231PHZ128r:
6629 case VFMSUB231PHZ128rk:
6630 case VFMSUB231PHZ128rkz:
6631 case VFMSUB231PHZ256m:
6632 case VFMSUB231PHZ256mb:
6633 case VFMSUB231PHZ256mbk:
6634 case VFMSUB231PHZ256mbkz:
6635 case VFMSUB231PHZ256mk:
6636 case VFMSUB231PHZ256mkz:
6637 case VFMSUB231PHZ256r:
6638 case VFMSUB231PHZ256rk:
6639 case VFMSUB231PHZ256rkz:
6640 case VFMSUB231PHZm:
6641 case VFMSUB231PHZmb:
6642 case VFMSUB231PHZmbk:
6643 case VFMSUB231PHZmbkz:
6644 case VFMSUB231PHZmk:
6645 case VFMSUB231PHZmkz:
6646 case VFMSUB231PHZr:
6647 case VFMSUB231PHZrb:
6648 case VFMSUB231PHZrbk:
6649 case VFMSUB231PHZrbkz:
6650 case VFMSUB231PHZrk:
6651 case VFMSUB231PHZrkz:
6652 return true;
6653 }
6654 return false;
6655}
6656
6657bool isVGATHERQPD(unsigned Opcode) {
6658 switch (Opcode) {
6659 case VGATHERQPDYrm:
6660 case VGATHERQPDZ128rm:
6661 case VGATHERQPDZ256rm:
6662 case VGATHERQPDZrm:
6663 case VGATHERQPDrm:
6664 return true;
6665 }
6666 return false;
6667}
6668
6669bool isKADDB(unsigned Opcode) {
6670 return Opcode == KADDBkk;
6671}
6672
6673bool isCVTPD2PI(unsigned Opcode) {
6674 switch (Opcode) {
6675 case MMX_CVTPD2PIrm:
6676 case MMX_CVTPD2PIrr:
6677 return true;
6678 }
6679 return false;
6680}
6681
6682bool isVFNMSUB213PH(unsigned Opcode) {
6683 switch (Opcode) {
6684 case VFNMSUB213PHZ128m:
6685 case VFNMSUB213PHZ128mb:
6686 case VFNMSUB213PHZ128mbk:
6687 case VFNMSUB213PHZ128mbkz:
6688 case VFNMSUB213PHZ128mk:
6689 case VFNMSUB213PHZ128mkz:
6690 case VFNMSUB213PHZ128r:
6691 case VFNMSUB213PHZ128rk:
6692 case VFNMSUB213PHZ128rkz:
6693 case VFNMSUB213PHZ256m:
6694 case VFNMSUB213PHZ256mb:
6695 case VFNMSUB213PHZ256mbk:
6696 case VFNMSUB213PHZ256mbkz:
6697 case VFNMSUB213PHZ256mk:
6698 case VFNMSUB213PHZ256mkz:
6699 case VFNMSUB213PHZ256r:
6700 case VFNMSUB213PHZ256rk:
6701 case VFNMSUB213PHZ256rkz:
6702 case VFNMSUB213PHZm:
6703 case VFNMSUB213PHZmb:
6704 case VFNMSUB213PHZmbk:
6705 case VFNMSUB213PHZmbkz:
6706 case VFNMSUB213PHZmk:
6707 case VFNMSUB213PHZmkz:
6708 case VFNMSUB213PHZr:
6709 case VFNMSUB213PHZrb:
6710 case VFNMSUB213PHZrbk:
6711 case VFNMSUB213PHZrbkz:
6712 case VFNMSUB213PHZrk:
6713 case VFNMSUB213PHZrkz:
6714 return true;
6715 }
6716 return false;
6717}
6718
6719bool isVPCMPESTRI(unsigned Opcode) {
6720 switch (Opcode) {
6721 case VPCMPESTRIrmi:
6722 case VPCMPESTRIrri:
6723 return true;
6724 }
6725 return false;
6726}
6727
6728bool isVPSHRDW(unsigned Opcode) {
6729 switch (Opcode) {
6730 case VPSHRDWZ128rmi:
6731 case VPSHRDWZ128rmik:
6732 case VPSHRDWZ128rmikz:
6733 case VPSHRDWZ128rri:
6734 case VPSHRDWZ128rrik:
6735 case VPSHRDWZ128rrikz:
6736 case VPSHRDWZ256rmi:
6737 case VPSHRDWZ256rmik:
6738 case VPSHRDWZ256rmikz:
6739 case VPSHRDWZ256rri:
6740 case VPSHRDWZ256rrik:
6741 case VPSHRDWZ256rrikz:
6742 case VPSHRDWZrmi:
6743 case VPSHRDWZrmik:
6744 case VPSHRDWZrmikz:
6745 case VPSHRDWZrri:
6746 case VPSHRDWZrrik:
6747 case VPSHRDWZrrikz:
6748 return true;
6749 }
6750 return false;
6751}
6752
6753bool isXORPS(unsigned Opcode) {
6754 switch (Opcode) {
6755 case XORPSrm:
6756 case XORPSrr:
6757 return true;
6758 }
6759 return false;
6760}
6761
6762bool isPOP2(unsigned Opcode) {
6763 return Opcode == POP2;
6764}
6765
6766bool isRDMSRLIST(unsigned Opcode) {
6767 return Opcode == RDMSRLIST;
6768}
6769
6770bool isVPDPBUSD(unsigned Opcode) {
6771 switch (Opcode) {
6772 case VPDPBUSDYrm:
6773 case VPDPBUSDYrr:
6774 case VPDPBUSDZ128rm:
6775 case VPDPBUSDZ128rmb:
6776 case VPDPBUSDZ128rmbk:
6777 case VPDPBUSDZ128rmbkz:
6778 case VPDPBUSDZ128rmk:
6779 case VPDPBUSDZ128rmkz:
6780 case VPDPBUSDZ128rr:
6781 case VPDPBUSDZ128rrk:
6782 case VPDPBUSDZ128rrkz:
6783 case VPDPBUSDZ256rm:
6784 case VPDPBUSDZ256rmb:
6785 case VPDPBUSDZ256rmbk:
6786 case VPDPBUSDZ256rmbkz:
6787 case VPDPBUSDZ256rmk:
6788 case VPDPBUSDZ256rmkz:
6789 case VPDPBUSDZ256rr:
6790 case VPDPBUSDZ256rrk:
6791 case VPDPBUSDZ256rrkz:
6792 case VPDPBUSDZrm:
6793 case VPDPBUSDZrmb:
6794 case VPDPBUSDZrmbk:
6795 case VPDPBUSDZrmbkz:
6796 case VPDPBUSDZrmk:
6797 case VPDPBUSDZrmkz:
6798 case VPDPBUSDZrr:
6799 case VPDPBUSDZrrk:
6800 case VPDPBUSDZrrkz:
6801 case VPDPBUSDrm:
6802 case VPDPBUSDrr:
6803 return true;
6804 }
6805 return false;
6806}
6807
6808bool isVCMPPH(unsigned Opcode) {
6809 switch (Opcode) {
6810 case VCMPPHZ128rmbi:
6811 case VCMPPHZ128rmbik:
6812 case VCMPPHZ128rmi:
6813 case VCMPPHZ128rmik:
6814 case VCMPPHZ128rri:
6815 case VCMPPHZ128rrik:
6816 case VCMPPHZ256rmbi:
6817 case VCMPPHZ256rmbik:
6818 case VCMPPHZ256rmi:
6819 case VCMPPHZ256rmik:
6820 case VCMPPHZ256rri:
6821 case VCMPPHZ256rrik:
6822 case VCMPPHZrmbi:
6823 case VCMPPHZrmbik:
6824 case VCMPPHZrmi:
6825 case VCMPPHZrmik:
6826 case VCMPPHZrri:
6827 case VCMPPHZrrib:
6828 case VCMPPHZrribk:
6829 case VCMPPHZrrik:
6830 return true;
6831 }
6832 return false;
6833}
6834
6835bool isVANDNPD(unsigned Opcode) {
6836 switch (Opcode) {
6837 case VANDNPDYrm:
6838 case VANDNPDYrr:
6839 case VANDNPDZ128rm:
6840 case VANDNPDZ128rmb:
6841 case VANDNPDZ128rmbk:
6842 case VANDNPDZ128rmbkz:
6843 case VANDNPDZ128rmk:
6844 case VANDNPDZ128rmkz:
6845 case VANDNPDZ128rr:
6846 case VANDNPDZ128rrk:
6847 case VANDNPDZ128rrkz:
6848 case VANDNPDZ256rm:
6849 case VANDNPDZ256rmb:
6850 case VANDNPDZ256rmbk:
6851 case VANDNPDZ256rmbkz:
6852 case VANDNPDZ256rmk:
6853 case VANDNPDZ256rmkz:
6854 case VANDNPDZ256rr:
6855 case VANDNPDZ256rrk:
6856 case VANDNPDZ256rrkz:
6857 case VANDNPDZrm:
6858 case VANDNPDZrmb:
6859 case VANDNPDZrmbk:
6860 case VANDNPDZrmbkz:
6861 case VANDNPDZrmk:
6862 case VANDNPDZrmkz:
6863 case VANDNPDZrr:
6864 case VANDNPDZrrk:
6865 case VANDNPDZrrkz:
6866 case VANDNPDrm:
6867 case VANDNPDrr:
6868 return true;
6869 }
6870 return false;
6871}
6872
6873bool isSUB(unsigned Opcode) {
6874 switch (Opcode) {
6875 case SUB16i16:
6876 case SUB16mi:
6877 case SUB16mi8:
6878 case SUB16mi8_EVEX:
6879 case SUB16mi8_ND:
6880 case SUB16mi8_NF:
6881 case SUB16mi8_NF_ND:
6882 case SUB16mi_EVEX:
6883 case SUB16mi_ND:
6884 case SUB16mi_NF:
6885 case SUB16mi_NF_ND:
6886 case SUB16mr:
6887 case SUB16mr_EVEX:
6888 case SUB16mr_ND:
6889 case SUB16mr_NF:
6890 case SUB16mr_NF_ND:
6891 case SUB16ri:
6892 case SUB16ri8:
6893 case SUB16ri8_EVEX:
6894 case SUB16ri8_ND:
6895 case SUB16ri8_NF:
6896 case SUB16ri8_NF_ND:
6897 case SUB16ri_EVEX:
6898 case SUB16ri_ND:
6899 case SUB16ri_NF:
6900 case SUB16ri_NF_ND:
6901 case SUB16rm:
6902 case SUB16rm_EVEX:
6903 case SUB16rm_ND:
6904 case SUB16rm_NF:
6905 case SUB16rm_NF_ND:
6906 case SUB16rr:
6907 case SUB16rr_EVEX:
6908 case SUB16rr_EVEX_REV:
6909 case SUB16rr_ND:
6910 case SUB16rr_ND_REV:
6911 case SUB16rr_NF:
6912 case SUB16rr_NF_ND:
6913 case SUB16rr_NF_ND_REV:
6914 case SUB16rr_NF_REV:
6915 case SUB16rr_REV:
6916 case SUB32i32:
6917 case SUB32mi:
6918 case SUB32mi8:
6919 case SUB32mi8_EVEX:
6920 case SUB32mi8_ND:
6921 case SUB32mi8_NF:
6922 case SUB32mi8_NF_ND:
6923 case SUB32mi_EVEX:
6924 case SUB32mi_ND:
6925 case SUB32mi_NF:
6926 case SUB32mi_NF_ND:
6927 case SUB32mr:
6928 case SUB32mr_EVEX:
6929 case SUB32mr_ND:
6930 case SUB32mr_NF:
6931 case SUB32mr_NF_ND:
6932 case SUB32ri:
6933 case SUB32ri8:
6934 case SUB32ri8_EVEX:
6935 case SUB32ri8_ND:
6936 case SUB32ri8_NF:
6937 case SUB32ri8_NF_ND:
6938 case SUB32ri_EVEX:
6939 case SUB32ri_ND:
6940 case SUB32ri_NF:
6941 case SUB32ri_NF_ND:
6942 case SUB32rm:
6943 case SUB32rm_EVEX:
6944 case SUB32rm_ND:
6945 case SUB32rm_NF:
6946 case SUB32rm_NF_ND:
6947 case SUB32rr:
6948 case SUB32rr_EVEX:
6949 case SUB32rr_EVEX_REV:
6950 case SUB32rr_ND:
6951 case SUB32rr_ND_REV:
6952 case SUB32rr_NF:
6953 case SUB32rr_NF_ND:
6954 case SUB32rr_NF_ND_REV:
6955 case SUB32rr_NF_REV:
6956 case SUB32rr_REV:
6957 case SUB64i32:
6958 case SUB64mi32:
6959 case SUB64mi32_EVEX:
6960 case SUB64mi32_ND:
6961 case SUB64mi32_NF:
6962 case SUB64mi32_NF_ND:
6963 case SUB64mi8:
6964 case SUB64mi8_EVEX:
6965 case SUB64mi8_ND:
6966 case SUB64mi8_NF:
6967 case SUB64mi8_NF_ND:
6968 case SUB64mr:
6969 case SUB64mr_EVEX:
6970 case SUB64mr_ND:
6971 case SUB64mr_NF:
6972 case SUB64mr_NF_ND:
6973 case SUB64ri32:
6974 case SUB64ri32_EVEX:
6975 case SUB64ri32_ND:
6976 case SUB64ri32_NF:
6977 case SUB64ri32_NF_ND:
6978 case SUB64ri8:
6979 case SUB64ri8_EVEX:
6980 case SUB64ri8_ND:
6981 case SUB64ri8_NF:
6982 case SUB64ri8_NF_ND:
6983 case SUB64rm:
6984 case SUB64rm_EVEX:
6985 case SUB64rm_ND:
6986 case SUB64rm_NF:
6987 case SUB64rm_NF_ND:
6988 case SUB64rr:
6989 case SUB64rr_EVEX:
6990 case SUB64rr_EVEX_REV:
6991 case SUB64rr_ND:
6992 case SUB64rr_ND_REV:
6993 case SUB64rr_NF:
6994 case SUB64rr_NF_ND:
6995 case SUB64rr_NF_ND_REV:
6996 case SUB64rr_NF_REV:
6997 case SUB64rr_REV:
6998 case SUB8i8:
6999 case SUB8mi:
7000 case SUB8mi8:
7001 case SUB8mi_EVEX:
7002 case SUB8mi_ND:
7003 case SUB8mi_NF:
7004 case SUB8mi_NF_ND:
7005 case SUB8mr:
7006 case SUB8mr_EVEX:
7007 case SUB8mr_ND:
7008 case SUB8mr_NF:
7009 case SUB8mr_NF_ND:
7010 case SUB8ri:
7011 case SUB8ri8:
7012 case SUB8ri_EVEX:
7013 case SUB8ri_ND:
7014 case SUB8ri_NF:
7015 case SUB8ri_NF_ND:
7016 case SUB8rm:
7017 case SUB8rm_EVEX:
7018 case SUB8rm_ND:
7019 case SUB8rm_NF:
7020 case SUB8rm_NF_ND:
7021 case SUB8rr:
7022 case SUB8rr_EVEX:
7023 case SUB8rr_EVEX_REV:
7024 case SUB8rr_ND:
7025 case SUB8rr_ND_REV:
7026 case SUB8rr_NF:
7027 case SUB8rr_NF_ND:
7028 case SUB8rr_NF_ND_REV:
7029 case SUB8rr_NF_REV:
7030 case SUB8rr_REV:
7031 return true;
7032 }
7033 return false;
7034}
7035
7036bool isVRSQRT28PD(unsigned Opcode) {
7037 switch (Opcode) {
7038 case VRSQRT28PDZm:
7039 case VRSQRT28PDZmb:
7040 case VRSQRT28PDZmbk:
7041 case VRSQRT28PDZmbkz:
7042 case VRSQRT28PDZmk:
7043 case VRSQRT28PDZmkz:
7044 case VRSQRT28PDZr:
7045 case VRSQRT28PDZrb:
7046 case VRSQRT28PDZrbk:
7047 case VRSQRT28PDZrbkz:
7048 case VRSQRT28PDZrk:
7049 case VRSQRT28PDZrkz:
7050 return true;
7051 }
7052 return false;
7053}
7054
7055bool isVFNMADD132PH(unsigned Opcode) {
7056 switch (Opcode) {
7057 case VFNMADD132PHZ128m:
7058 case VFNMADD132PHZ128mb:
7059 case VFNMADD132PHZ128mbk:
7060 case VFNMADD132PHZ128mbkz:
7061 case VFNMADD132PHZ128mk:
7062 case VFNMADD132PHZ128mkz:
7063 case VFNMADD132PHZ128r:
7064 case VFNMADD132PHZ128rk:
7065 case VFNMADD132PHZ128rkz:
7066 case VFNMADD132PHZ256m:
7067 case VFNMADD132PHZ256mb:
7068 case VFNMADD132PHZ256mbk:
7069 case VFNMADD132PHZ256mbkz:
7070 case VFNMADD132PHZ256mk:
7071 case VFNMADD132PHZ256mkz:
7072 case VFNMADD132PHZ256r:
7073 case VFNMADD132PHZ256rk:
7074 case VFNMADD132PHZ256rkz:
7075 case VFNMADD132PHZm:
7076 case VFNMADD132PHZmb:
7077 case VFNMADD132PHZmbk:
7078 case VFNMADD132PHZmbkz:
7079 case VFNMADD132PHZmk:
7080 case VFNMADD132PHZmkz:
7081 case VFNMADD132PHZr:
7082 case VFNMADD132PHZrb:
7083 case VFNMADD132PHZrbk:
7084 case VFNMADD132PHZrbkz:
7085 case VFNMADD132PHZrk:
7086 case VFNMADD132PHZrkz:
7087 return true;
7088 }
7089 return false;
7090}
7091
7092bool isVPMACSSWW(unsigned Opcode) {
7093 switch (Opcode) {
7094 case VPMACSSWWrm:
7095 case VPMACSSWWrr:
7096 return true;
7097 }
7098 return false;
7099}
7100
7101bool isXSTORE(unsigned Opcode) {
7102 return Opcode == XSTORE;
7103}
7104
7105bool isVPROTQ(unsigned Opcode) {
7106 switch (Opcode) {
7107 case VPROTQmi:
7108 case VPROTQmr:
7109 case VPROTQri:
7110 case VPROTQrm:
7111 case VPROTQrr:
7112 case VPROTQrr_REV:
7113 return true;
7114 }
7115 return false;
7116}
7117
7118bool isVPHADDBD(unsigned Opcode) {
7119 switch (Opcode) {
7120 case VPHADDBDrm:
7121 case VPHADDBDrr:
7122 return true;
7123 }
7124 return false;
7125}
7126
7127bool isVPMAXSB(unsigned Opcode) {
7128 switch (Opcode) {
7129 case VPMAXSBYrm:
7130 case VPMAXSBYrr:
7131 case VPMAXSBZ128rm:
7132 case VPMAXSBZ128rmk:
7133 case VPMAXSBZ128rmkz:
7134 case VPMAXSBZ128rr:
7135 case VPMAXSBZ128rrk:
7136 case VPMAXSBZ128rrkz:
7137 case VPMAXSBZ256rm:
7138 case VPMAXSBZ256rmk:
7139 case VPMAXSBZ256rmkz:
7140 case VPMAXSBZ256rr:
7141 case VPMAXSBZ256rrk:
7142 case VPMAXSBZ256rrkz:
7143 case VPMAXSBZrm:
7144 case VPMAXSBZrmk:
7145 case VPMAXSBZrmkz:
7146 case VPMAXSBZrr:
7147 case VPMAXSBZrrk:
7148 case VPMAXSBZrrkz:
7149 case VPMAXSBrm:
7150 case VPMAXSBrr:
7151 return true;
7152 }
7153 return false;
7154}
7155
7156bool isVMOVDQU8(unsigned Opcode) {
7157 switch (Opcode) {
7158 case VMOVDQU8Z128mr:
7159 case VMOVDQU8Z128mrk:
7160 case VMOVDQU8Z128rm:
7161 case VMOVDQU8Z128rmk:
7162 case VMOVDQU8Z128rmkz:
7163 case VMOVDQU8Z128rr:
7164 case VMOVDQU8Z128rr_REV:
7165 case VMOVDQU8Z128rrk:
7166 case VMOVDQU8Z128rrk_REV:
7167 case VMOVDQU8Z128rrkz:
7168 case VMOVDQU8Z128rrkz_REV:
7169 case VMOVDQU8Z256mr:
7170 case VMOVDQU8Z256mrk:
7171 case VMOVDQU8Z256rm:
7172 case VMOVDQU8Z256rmk:
7173 case VMOVDQU8Z256rmkz:
7174 case VMOVDQU8Z256rr:
7175 case VMOVDQU8Z256rr_REV:
7176 case VMOVDQU8Z256rrk:
7177 case VMOVDQU8Z256rrk_REV:
7178 case VMOVDQU8Z256rrkz:
7179 case VMOVDQU8Z256rrkz_REV:
7180 case VMOVDQU8Zmr:
7181 case VMOVDQU8Zmrk:
7182 case VMOVDQU8Zrm:
7183 case VMOVDQU8Zrmk:
7184 case VMOVDQU8Zrmkz:
7185 case VMOVDQU8Zrr:
7186 case VMOVDQU8Zrr_REV:
7187 case VMOVDQU8Zrrk:
7188 case VMOVDQU8Zrrk_REV:
7189 case VMOVDQU8Zrrkz:
7190 case VMOVDQU8Zrrkz_REV:
7191 return true;
7192 }
7193 return false;
7194}
7195
7196bool isVPMOVSXWD(unsigned Opcode) {
7197 switch (Opcode) {
7198 case VPMOVSXWDYrm:
7199 case VPMOVSXWDYrr:
7200 case VPMOVSXWDZ128rm:
7201 case VPMOVSXWDZ128rmk:
7202 case VPMOVSXWDZ128rmkz:
7203 case VPMOVSXWDZ128rr:
7204 case VPMOVSXWDZ128rrk:
7205 case VPMOVSXWDZ128rrkz:
7206 case VPMOVSXWDZ256rm:
7207 case VPMOVSXWDZ256rmk:
7208 case VPMOVSXWDZ256rmkz:
7209 case VPMOVSXWDZ256rr:
7210 case VPMOVSXWDZ256rrk:
7211 case VPMOVSXWDZ256rrkz:
7212 case VPMOVSXWDZrm:
7213 case VPMOVSXWDZrmk:
7214 case VPMOVSXWDZrmkz:
7215 case VPMOVSXWDZrr:
7216 case VPMOVSXWDZrrk:
7217 case VPMOVSXWDZrrkz:
7218 case VPMOVSXWDrm:
7219 case VPMOVSXWDrr:
7220 return true;
7221 }
7222 return false;
7223}
7224
7225bool isVMINMAXPD(unsigned Opcode) {
7226 switch (Opcode) {
7227 case VMINMAXPDZ128rmbi:
7228 case VMINMAXPDZ128rmbik:
7229 case VMINMAXPDZ128rmbikz:
7230 case VMINMAXPDZ128rmi:
7231 case VMINMAXPDZ128rmik:
7232 case VMINMAXPDZ128rmikz:
7233 case VMINMAXPDZ128rri:
7234 case VMINMAXPDZ128rrik:
7235 case VMINMAXPDZ128rrikz:
7236 case VMINMAXPDZ256rmbi:
7237 case VMINMAXPDZ256rmbik:
7238 case VMINMAXPDZ256rmbikz:
7239 case VMINMAXPDZ256rmi:
7240 case VMINMAXPDZ256rmik:
7241 case VMINMAXPDZ256rmikz:
7242 case VMINMAXPDZ256rri:
7243 case VMINMAXPDZ256rrik:
7244 case VMINMAXPDZ256rrikz:
7245 case VMINMAXPDZrmbi:
7246 case VMINMAXPDZrmbik:
7247 case VMINMAXPDZrmbikz:
7248 case VMINMAXPDZrmi:
7249 case VMINMAXPDZrmik:
7250 case VMINMAXPDZrmikz:
7251 case VMINMAXPDZrri:
7252 case VMINMAXPDZrrib:
7253 case VMINMAXPDZrribk:
7254 case VMINMAXPDZrribkz:
7255 case VMINMAXPDZrrik:
7256 case VMINMAXPDZrrikz:
7257 return true;
7258 }
7259 return false;
7260}
7261
7262bool isSHA256RNDS2(unsigned Opcode) {
7263 switch (Opcode) {
7264 case SHA256RNDS2rm:
7265 case SHA256RNDS2rr:
7266 return true;
7267 }
7268 return false;
7269}
7270
7271bool isKANDB(unsigned Opcode) {
7272 return Opcode == KANDBkk;
7273}
7274
7275bool isTPAUSE(unsigned Opcode) {
7276 return Opcode == TPAUSE;
7277}
7278
7279bool isPUSH(unsigned Opcode) {
7280 switch (Opcode) {
7281 case PUSH16i:
7282 case PUSH16i8:
7283 case PUSH16r:
7284 case PUSH16rmm:
7285 case PUSH16rmr:
7286 case PUSH32i:
7287 case PUSH32i8:
7288 case PUSH32r:
7289 case PUSH32rmm:
7290 case PUSH32rmr:
7291 case PUSH64i32:
7292 case PUSH64i8:
7293 case PUSH64r:
7294 case PUSH64rmm:
7295 case PUSH64rmr:
7296 case PUSHCS16:
7297 case PUSHCS32:
7298 case PUSHDS16:
7299 case PUSHDS32:
7300 case PUSHES16:
7301 case PUSHES32:
7302 case PUSHFS16:
7303 case PUSHFS32:
7304 case PUSHFS64:
7305 case PUSHGS16:
7306 case PUSHGS32:
7307 case PUSHGS64:
7308 case PUSHSS16:
7309 case PUSHSS32:
7310 return true;
7311 }
7312 return false;
7313}
7314
7315bool isVRNDSCALESS(unsigned Opcode) {
7316 switch (Opcode) {
7317 case VRNDSCALESSZrmi_Int:
7318 case VRNDSCALESSZrmik_Int:
7319 case VRNDSCALESSZrmikz_Int:
7320 case VRNDSCALESSZrri_Int:
7321 case VRNDSCALESSZrrib_Int:
7322 case VRNDSCALESSZrribk_Int:
7323 case VRNDSCALESSZrribkz_Int:
7324 case VRNDSCALESSZrrik_Int:
7325 case VRNDSCALESSZrrikz_Int:
7326 return true;
7327 }
7328 return false;
7329}
7330
7331bool isVRNDSCALEBF16(unsigned Opcode) {
7332 switch (Opcode) {
7333 case VRNDSCALEBF16Z128rmbi:
7334 case VRNDSCALEBF16Z128rmbik:
7335 case VRNDSCALEBF16Z128rmbikz:
7336 case VRNDSCALEBF16Z128rmi:
7337 case VRNDSCALEBF16Z128rmik:
7338 case VRNDSCALEBF16Z128rmikz:
7339 case VRNDSCALEBF16Z128rri:
7340 case VRNDSCALEBF16Z128rrik:
7341 case VRNDSCALEBF16Z128rrikz:
7342 case VRNDSCALEBF16Z256rmbi:
7343 case VRNDSCALEBF16Z256rmbik:
7344 case VRNDSCALEBF16Z256rmbikz:
7345 case VRNDSCALEBF16Z256rmi:
7346 case VRNDSCALEBF16Z256rmik:
7347 case VRNDSCALEBF16Z256rmikz:
7348 case VRNDSCALEBF16Z256rri:
7349 case VRNDSCALEBF16Z256rrik:
7350 case VRNDSCALEBF16Z256rrikz:
7351 case VRNDSCALEBF16Zrmbi:
7352 case VRNDSCALEBF16Zrmbik:
7353 case VRNDSCALEBF16Zrmbikz:
7354 case VRNDSCALEBF16Zrmi:
7355 case VRNDSCALEBF16Zrmik:
7356 case VRNDSCALEBF16Zrmikz:
7357 case VRNDSCALEBF16Zrri:
7358 case VRNDSCALEBF16Zrrik:
7359 case VRNDSCALEBF16Zrrikz:
7360 return true;
7361 }
7362 return false;
7363}
7364
7365bool isVPCMPISTRI(unsigned Opcode) {
7366 switch (Opcode) {
7367 case VPCMPISTRIrmi:
7368 case VPCMPISTRIrri:
7369 return true;
7370 }
7371 return false;
7372}
7373
7374bool isSTGI(unsigned Opcode) {
7375 return Opcode == STGI;
7376}
7377
7378bool isSBB(unsigned Opcode) {
7379 switch (Opcode) {
7380 case SBB16i16:
7381 case SBB16mi:
7382 case SBB16mi8:
7383 case SBB16mi8_EVEX:
7384 case SBB16mi8_ND:
7385 case SBB16mi_EVEX:
7386 case SBB16mi_ND:
7387 case SBB16mr:
7388 case SBB16mr_EVEX:
7389 case SBB16mr_ND:
7390 case SBB16ri:
7391 case SBB16ri8:
7392 case SBB16ri8_EVEX:
7393 case SBB16ri8_ND:
7394 case SBB16ri_EVEX:
7395 case SBB16ri_ND:
7396 case SBB16rm:
7397 case SBB16rm_EVEX:
7398 case SBB16rm_ND:
7399 case SBB16rr:
7400 case SBB16rr_EVEX:
7401 case SBB16rr_EVEX_REV:
7402 case SBB16rr_ND:
7403 case SBB16rr_ND_REV:
7404 case SBB16rr_REV:
7405 case SBB32i32:
7406 case SBB32mi:
7407 case SBB32mi8:
7408 case SBB32mi8_EVEX:
7409 case SBB32mi8_ND:
7410 case SBB32mi_EVEX:
7411 case SBB32mi_ND:
7412 case SBB32mr:
7413 case SBB32mr_EVEX:
7414 case SBB32mr_ND:
7415 case SBB32ri:
7416 case SBB32ri8:
7417 case SBB32ri8_EVEX:
7418 case SBB32ri8_ND:
7419 case SBB32ri_EVEX:
7420 case SBB32ri_ND:
7421 case SBB32rm:
7422 case SBB32rm_EVEX:
7423 case SBB32rm_ND:
7424 case SBB32rr:
7425 case SBB32rr_EVEX:
7426 case SBB32rr_EVEX_REV:
7427 case SBB32rr_ND:
7428 case SBB32rr_ND_REV:
7429 case SBB32rr_REV:
7430 case SBB64i32:
7431 case SBB64mi32:
7432 case SBB64mi32_EVEX:
7433 case SBB64mi32_ND:
7434 case SBB64mi8:
7435 case SBB64mi8_EVEX:
7436 case SBB64mi8_ND:
7437 case SBB64mr:
7438 case SBB64mr_EVEX:
7439 case SBB64mr_ND:
7440 case SBB64ri32:
7441 case SBB64ri32_EVEX:
7442 case SBB64ri32_ND:
7443 case SBB64ri8:
7444 case SBB64ri8_EVEX:
7445 case SBB64ri8_ND:
7446 case SBB64rm:
7447 case SBB64rm_EVEX:
7448 case SBB64rm_ND:
7449 case SBB64rr:
7450 case SBB64rr_EVEX:
7451 case SBB64rr_EVEX_REV:
7452 case SBB64rr_ND:
7453 case SBB64rr_ND_REV:
7454 case SBB64rr_REV:
7455 case SBB8i8:
7456 case SBB8mi:
7457 case SBB8mi8:
7458 case SBB8mi_EVEX:
7459 case SBB8mi_ND:
7460 case SBB8mr:
7461 case SBB8mr_EVEX:
7462 case SBB8mr_ND:
7463 case SBB8ri:
7464 case SBB8ri8:
7465 case SBB8ri_EVEX:
7466 case SBB8ri_ND:
7467 case SBB8rm:
7468 case SBB8rm_EVEX:
7469 case SBB8rm_ND:
7470 case SBB8rr:
7471 case SBB8rr_EVEX:
7472 case SBB8rr_EVEX_REV:
7473 case SBB8rr_ND:
7474 case SBB8rr_ND_REV:
7475 case SBB8rr_REV:
7476 return true;
7477 }
7478 return false;
7479}
7480
7481bool isBLCS(unsigned Opcode) {
7482 switch (Opcode) {
7483 case BLCS32rm:
7484 case BLCS32rr:
7485 case BLCS64rm:
7486 case BLCS64rr:
7487 return true;
7488 }
7489 return false;
7490}
7491
7492bool isVCVTSD2SH(unsigned Opcode) {
7493 switch (Opcode) {
7494 case VCVTSD2SHZrm_Int:
7495 case VCVTSD2SHZrmk_Int:
7496 case VCVTSD2SHZrmkz_Int:
7497 case VCVTSD2SHZrr_Int:
7498 case VCVTSD2SHZrrb_Int:
7499 case VCVTSD2SHZrrbk_Int:
7500 case VCVTSD2SHZrrbkz_Int:
7501 case VCVTSD2SHZrrk_Int:
7502 case VCVTSD2SHZrrkz_Int:
7503 return true;
7504 }
7505 return false;
7506}
7507
7508bool isVPERMW(unsigned Opcode) {
7509 switch (Opcode) {
7510 case VPERMWZ128rm:
7511 case VPERMWZ128rmk:
7512 case VPERMWZ128rmkz:
7513 case VPERMWZ128rr:
7514 case VPERMWZ128rrk:
7515 case VPERMWZ128rrkz:
7516 case VPERMWZ256rm:
7517 case VPERMWZ256rmk:
7518 case VPERMWZ256rmkz:
7519 case VPERMWZ256rr:
7520 case VPERMWZ256rrk:
7521 case VPERMWZ256rrkz:
7522 case VPERMWZrm:
7523 case VPERMWZrmk:
7524 case VPERMWZrmkz:
7525 case VPERMWZrr:
7526 case VPERMWZrrk:
7527 case VPERMWZrrkz:
7528 return true;
7529 }
7530 return false;
7531}
7532
7533bool isXRESLDTRK(unsigned Opcode) {
7534 return Opcode == XRESLDTRK;
7535}
7536
7537bool isAESENC256KL(unsigned Opcode) {
7538 return Opcode == AESENC256KL;
7539}
7540
7541bool isVGATHERDPD(unsigned Opcode) {
7542 switch (Opcode) {
7543 case VGATHERDPDYrm:
7544 case VGATHERDPDZ128rm:
7545 case VGATHERDPDZ256rm:
7546 case VGATHERDPDZrm:
7547 case VGATHERDPDrm:
7548 return true;
7549 }
7550 return false;
7551}
7552
7553bool isHRESET(unsigned Opcode) {
7554 return Opcode == HRESET;
7555}
7556
7557bool isVFMSUBADD231PD(unsigned Opcode) {
7558 switch (Opcode) {
7559 case VFMSUBADD231PDYm:
7560 case VFMSUBADD231PDYr:
7561 case VFMSUBADD231PDZ128m:
7562 case VFMSUBADD231PDZ128mb:
7563 case VFMSUBADD231PDZ128mbk:
7564 case VFMSUBADD231PDZ128mbkz:
7565 case VFMSUBADD231PDZ128mk:
7566 case VFMSUBADD231PDZ128mkz:
7567 case VFMSUBADD231PDZ128r:
7568 case VFMSUBADD231PDZ128rk:
7569 case VFMSUBADD231PDZ128rkz:
7570 case VFMSUBADD231PDZ256m:
7571 case VFMSUBADD231PDZ256mb:
7572 case VFMSUBADD231PDZ256mbk:
7573 case VFMSUBADD231PDZ256mbkz:
7574 case VFMSUBADD231PDZ256mk:
7575 case VFMSUBADD231PDZ256mkz:
7576 case VFMSUBADD231PDZ256r:
7577 case VFMSUBADD231PDZ256rk:
7578 case VFMSUBADD231PDZ256rkz:
7579 case VFMSUBADD231PDZm:
7580 case VFMSUBADD231PDZmb:
7581 case VFMSUBADD231PDZmbk:
7582 case VFMSUBADD231PDZmbkz:
7583 case VFMSUBADD231PDZmk:
7584 case VFMSUBADD231PDZmkz:
7585 case VFMSUBADD231PDZr:
7586 case VFMSUBADD231PDZrb:
7587 case VFMSUBADD231PDZrbk:
7588 case VFMSUBADD231PDZrbkz:
7589 case VFMSUBADD231PDZrk:
7590 case VFMSUBADD231PDZrkz:
7591 case VFMSUBADD231PDm:
7592 case VFMSUBADD231PDr:
7593 return true;
7594 }
7595 return false;
7596}
7597
7598bool isVFRCZSS(unsigned Opcode) {
7599 switch (Opcode) {
7600 case VFRCZSSrm:
7601 case VFRCZSSrr:
7602 return true;
7603 }
7604 return false;
7605}
7606
7607bool isMINPS(unsigned Opcode) {
7608 switch (Opcode) {
7609 case MINPSrm:
7610 case MINPSrr:
7611 return true;
7612 }
7613 return false;
7614}
7615
7616bool isFPREM1(unsigned Opcode) {
7617 return Opcode == FPREM1;
7618}
7619
7620bool isVPCMPUB(unsigned Opcode) {
7621 switch (Opcode) {
7622 case VPCMPUBZ128rmi:
7623 case VPCMPUBZ128rmik:
7624 case VPCMPUBZ128rri:
7625 case VPCMPUBZ128rrik:
7626 case VPCMPUBZ256rmi:
7627 case VPCMPUBZ256rmik:
7628 case VPCMPUBZ256rri:
7629 case VPCMPUBZ256rrik:
7630 case VPCMPUBZrmi:
7631 case VPCMPUBZrmik:
7632 case VPCMPUBZrri:
7633 case VPCMPUBZrrik:
7634 return true;
7635 }
7636 return false;
7637}
7638
7639bool isVSQRTPD(unsigned Opcode) {
7640 switch (Opcode) {
7641 case VSQRTPDYm:
7642 case VSQRTPDYr:
7643 case VSQRTPDZ128m:
7644 case VSQRTPDZ128mb:
7645 case VSQRTPDZ128mbk:
7646 case VSQRTPDZ128mbkz:
7647 case VSQRTPDZ128mk:
7648 case VSQRTPDZ128mkz:
7649 case VSQRTPDZ128r:
7650 case VSQRTPDZ128rk:
7651 case VSQRTPDZ128rkz:
7652 case VSQRTPDZ256m:
7653 case VSQRTPDZ256mb:
7654 case VSQRTPDZ256mbk:
7655 case VSQRTPDZ256mbkz:
7656 case VSQRTPDZ256mk:
7657 case VSQRTPDZ256mkz:
7658 case VSQRTPDZ256r:
7659 case VSQRTPDZ256rk:
7660 case VSQRTPDZ256rkz:
7661 case VSQRTPDZm:
7662 case VSQRTPDZmb:
7663 case VSQRTPDZmbk:
7664 case VSQRTPDZmbkz:
7665 case VSQRTPDZmk:
7666 case VSQRTPDZmkz:
7667 case VSQRTPDZr:
7668 case VSQRTPDZrb:
7669 case VSQRTPDZrbk:
7670 case VSQRTPDZrbkz:
7671 case VSQRTPDZrk:
7672 case VSQRTPDZrkz:
7673 case VSQRTPDm:
7674 case VSQRTPDr:
7675 return true;
7676 }
7677 return false;
7678}
7679
7680bool isVFRCZPS(unsigned Opcode) {
7681 switch (Opcode) {
7682 case VFRCZPSYrm:
7683 case VFRCZPSYrr:
7684 case VFRCZPSrm:
7685 case VFRCZPSrr:
7686 return true;
7687 }
7688 return false;
7689}
7690
7691bool isVFNMADD213SS(unsigned Opcode) {
7692 switch (Opcode) {
7693 case VFNMADD213SSZm_Int:
7694 case VFNMADD213SSZmk_Int:
7695 case VFNMADD213SSZmkz_Int:
7696 case VFNMADD213SSZr_Int:
7697 case VFNMADD213SSZrb_Int:
7698 case VFNMADD213SSZrbk_Int:
7699 case VFNMADD213SSZrbkz_Int:
7700 case VFNMADD213SSZrk_Int:
7701 case VFNMADD213SSZrkz_Int:
7702 case VFNMADD213SSm_Int:
7703 case VFNMADD213SSr_Int:
7704 return true;
7705 }
7706 return false;
7707}
7708
7709bool isVPSHRDVQ(unsigned Opcode) {
7710 switch (Opcode) {
7711 case VPSHRDVQZ128m:
7712 case VPSHRDVQZ128mb:
7713 case VPSHRDVQZ128mbk:
7714 case VPSHRDVQZ128mbkz:
7715 case VPSHRDVQZ128mk:
7716 case VPSHRDVQZ128mkz:
7717 case VPSHRDVQZ128r:
7718 case VPSHRDVQZ128rk:
7719 case VPSHRDVQZ128rkz:
7720 case VPSHRDVQZ256m:
7721 case VPSHRDVQZ256mb:
7722 case VPSHRDVQZ256mbk:
7723 case VPSHRDVQZ256mbkz:
7724 case VPSHRDVQZ256mk:
7725 case VPSHRDVQZ256mkz:
7726 case VPSHRDVQZ256r:
7727 case VPSHRDVQZ256rk:
7728 case VPSHRDVQZ256rkz:
7729 case VPSHRDVQZm:
7730 case VPSHRDVQZmb:
7731 case VPSHRDVQZmbk:
7732 case VPSHRDVQZmbkz:
7733 case VPSHRDVQZmk:
7734 case VPSHRDVQZmkz:
7735 case VPSHRDVQZr:
7736 case VPSHRDVQZrk:
7737 case VPSHRDVQZrkz:
7738 return true;
7739 }
7740 return false;
7741}
7742
7743bool isVPMOVDW(unsigned Opcode) {
7744 switch (Opcode) {
7745 case VPMOVDWZ128mr:
7746 case VPMOVDWZ128mrk:
7747 case VPMOVDWZ128rr:
7748 case VPMOVDWZ128rrk:
7749 case VPMOVDWZ128rrkz:
7750 case VPMOVDWZ256mr:
7751 case VPMOVDWZ256mrk:
7752 case VPMOVDWZ256rr:
7753 case VPMOVDWZ256rrk:
7754 case VPMOVDWZ256rrkz:
7755 case VPMOVDWZmr:
7756 case VPMOVDWZmrk:
7757 case VPMOVDWZrr:
7758 case VPMOVDWZrrk:
7759 case VPMOVDWZrrkz:
7760 return true;
7761 }
7762 return false;
7763}
7764
7765bool isVCVTPH2HF8S(unsigned Opcode) {
7766 switch (Opcode) {
7767 case VCVTPH2HF8SZ128rm:
7768 case VCVTPH2HF8SZ128rmb:
7769 case VCVTPH2HF8SZ128rmbk:
7770 case VCVTPH2HF8SZ128rmbkz:
7771 case VCVTPH2HF8SZ128rmk:
7772 case VCVTPH2HF8SZ128rmkz:
7773 case VCVTPH2HF8SZ128rr:
7774 case VCVTPH2HF8SZ128rrk:
7775 case VCVTPH2HF8SZ128rrkz:
7776 case VCVTPH2HF8SZ256rm:
7777 case VCVTPH2HF8SZ256rmb:
7778 case VCVTPH2HF8SZ256rmbk:
7779 case VCVTPH2HF8SZ256rmbkz:
7780 case VCVTPH2HF8SZ256rmk:
7781 case VCVTPH2HF8SZ256rmkz:
7782 case VCVTPH2HF8SZ256rr:
7783 case VCVTPH2HF8SZ256rrk:
7784 case VCVTPH2HF8SZ256rrkz:
7785 case VCVTPH2HF8SZrm:
7786 case VCVTPH2HF8SZrmb:
7787 case VCVTPH2HF8SZrmbk:
7788 case VCVTPH2HF8SZrmbkz:
7789 case VCVTPH2HF8SZrmk:
7790 case VCVTPH2HF8SZrmkz:
7791 case VCVTPH2HF8SZrr:
7792 case VCVTPH2HF8SZrrk:
7793 case VCVTPH2HF8SZrrkz:
7794 return true;
7795 }
7796 return false;
7797}
7798
7799bool isVBROADCASTSD(unsigned Opcode) {
7800 switch (Opcode) {
7801 case VBROADCASTSDYrm:
7802 case VBROADCASTSDYrr:
7803 case VBROADCASTSDZ256rm:
7804 case VBROADCASTSDZ256rmk:
7805 case VBROADCASTSDZ256rmkz:
7806 case VBROADCASTSDZ256rr:
7807 case VBROADCASTSDZ256rrk:
7808 case VBROADCASTSDZ256rrkz:
7809 case VBROADCASTSDZrm:
7810 case VBROADCASTSDZrmk:
7811 case VBROADCASTSDZrmkz:
7812 case VBROADCASTSDZrr:
7813 case VBROADCASTSDZrrk:
7814 case VBROADCASTSDZrrkz:
7815 return true;
7816 }
7817 return false;
7818}
7819
7820bool isVSHUFPD(unsigned Opcode) {
7821 switch (Opcode) {
7822 case VSHUFPDYrmi:
7823 case VSHUFPDYrri:
7824 case VSHUFPDZ128rmbi:
7825 case VSHUFPDZ128rmbik:
7826 case VSHUFPDZ128rmbikz:
7827 case VSHUFPDZ128rmi:
7828 case VSHUFPDZ128rmik:
7829 case VSHUFPDZ128rmikz:
7830 case VSHUFPDZ128rri:
7831 case VSHUFPDZ128rrik:
7832 case VSHUFPDZ128rrikz:
7833 case VSHUFPDZ256rmbi:
7834 case VSHUFPDZ256rmbik:
7835 case VSHUFPDZ256rmbikz:
7836 case VSHUFPDZ256rmi:
7837 case VSHUFPDZ256rmik:
7838 case VSHUFPDZ256rmikz:
7839 case VSHUFPDZ256rri:
7840 case VSHUFPDZ256rrik:
7841 case VSHUFPDZ256rrikz:
7842 case VSHUFPDZrmbi:
7843 case VSHUFPDZrmbik:
7844 case VSHUFPDZrmbikz:
7845 case VSHUFPDZrmi:
7846 case VSHUFPDZrmik:
7847 case VSHUFPDZrmikz:
7848 case VSHUFPDZrri:
7849 case VSHUFPDZrrik:
7850 case VSHUFPDZrrikz:
7851 case VSHUFPDrmi:
7852 case VSHUFPDrri:
7853 return true;
7854 }
7855 return false;
7856}
7857
7858bool isVPSUBSW(unsigned Opcode) {
7859 switch (Opcode) {
7860 case VPSUBSWYrm:
7861 case VPSUBSWYrr:
7862 case VPSUBSWZ128rm:
7863 case VPSUBSWZ128rmk:
7864 case VPSUBSWZ128rmkz:
7865 case VPSUBSWZ128rr:
7866 case VPSUBSWZ128rrk:
7867 case VPSUBSWZ128rrkz:
7868 case VPSUBSWZ256rm:
7869 case VPSUBSWZ256rmk:
7870 case VPSUBSWZ256rmkz:
7871 case VPSUBSWZ256rr:
7872 case VPSUBSWZ256rrk:
7873 case VPSUBSWZ256rrkz:
7874 case VPSUBSWZrm:
7875 case VPSUBSWZrmk:
7876 case VPSUBSWZrmkz:
7877 case VPSUBSWZrr:
7878 case VPSUBSWZrrk:
7879 case VPSUBSWZrrkz:
7880 case VPSUBSWrm:
7881 case VPSUBSWrr:
7882 return true;
7883 }
7884 return false;
7885}
7886
7887bool isKUNPCKBW(unsigned Opcode) {
7888 return Opcode == KUNPCKBWkk;
7889}
7890
7891bool isVPBLENDD(unsigned Opcode) {
7892 switch (Opcode) {
7893 case VPBLENDDYrmi:
7894 case VPBLENDDYrri:
7895 case VPBLENDDrmi:
7896 case VPBLENDDrri:
7897 return true;
7898 }
7899 return false;
7900}
7901
7902bool isUNPCKHPD(unsigned Opcode) {
7903 switch (Opcode) {
7904 case UNPCKHPDrm:
7905 case UNPCKHPDrr:
7906 return true;
7907 }
7908 return false;
7909}
7910
7911bool isVFNMADD231SD(unsigned Opcode) {
7912 switch (Opcode) {
7913 case VFNMADD231SDZm_Int:
7914 case VFNMADD231SDZmk_Int:
7915 case VFNMADD231SDZmkz_Int:
7916 case VFNMADD231SDZr_Int:
7917 case VFNMADD231SDZrb_Int:
7918 case VFNMADD231SDZrbk_Int:
7919 case VFNMADD231SDZrbkz_Int:
7920 case VFNMADD231SDZrk_Int:
7921 case VFNMADD231SDZrkz_Int:
7922 case VFNMADD231SDm_Int:
7923 case VFNMADD231SDr_Int:
7924 return true;
7925 }
7926 return false;
7927}
7928
7929bool isVPBROADCASTMW2D(unsigned Opcode) {
7930 switch (Opcode) {
7931 case VPBROADCASTMW2DZ128rr:
7932 case VPBROADCASTMW2DZ256rr:
7933 case VPBROADCASTMW2DZrr:
7934 return true;
7935 }
7936 return false;
7937}
7938
7939bool isVPMULTISHIFTQB(unsigned Opcode) {
7940 switch (Opcode) {
7941 case VPMULTISHIFTQBZ128rm:
7942 case VPMULTISHIFTQBZ128rmb:
7943 case VPMULTISHIFTQBZ128rmbk:
7944 case VPMULTISHIFTQBZ128rmbkz:
7945 case VPMULTISHIFTQBZ128rmk:
7946 case VPMULTISHIFTQBZ128rmkz:
7947 case VPMULTISHIFTQBZ128rr:
7948 case VPMULTISHIFTQBZ128rrk:
7949 case VPMULTISHIFTQBZ128rrkz:
7950 case VPMULTISHIFTQBZ256rm:
7951 case VPMULTISHIFTQBZ256rmb:
7952 case VPMULTISHIFTQBZ256rmbk:
7953 case VPMULTISHIFTQBZ256rmbkz:
7954 case VPMULTISHIFTQBZ256rmk:
7955 case VPMULTISHIFTQBZ256rmkz:
7956 case VPMULTISHIFTQBZ256rr:
7957 case VPMULTISHIFTQBZ256rrk:
7958 case VPMULTISHIFTQBZ256rrkz:
7959 case VPMULTISHIFTQBZrm:
7960 case VPMULTISHIFTQBZrmb:
7961 case VPMULTISHIFTQBZrmbk:
7962 case VPMULTISHIFTQBZrmbkz:
7963 case VPMULTISHIFTQBZrmk:
7964 case VPMULTISHIFTQBZrmkz:
7965 case VPMULTISHIFTQBZrr:
7966 case VPMULTISHIFTQBZrrk:
7967 case VPMULTISHIFTQBZrrkz:
7968 return true;
7969 }
7970 return false;
7971}
7972
7973bool isVP2INTERSECTQ(unsigned Opcode) {
7974 switch (Opcode) {
7975 case VP2INTERSECTQZ128rm:
7976 case VP2INTERSECTQZ128rmb:
7977 case VP2INTERSECTQZ128rr:
7978 case VP2INTERSECTQZ256rm:
7979 case VP2INTERSECTQZ256rmb:
7980 case VP2INTERSECTQZ256rr:
7981 case VP2INTERSECTQZrm:
7982 case VP2INTERSECTQZrmb:
7983 case VP2INTERSECTQZrr:
7984 return true;
7985 }
7986 return false;
7987}
7988
7989bool isVFNMSUB132BF16(unsigned Opcode) {
7990 switch (Opcode) {
7991 case VFNMSUB132BF16Z128m:
7992 case VFNMSUB132BF16Z128mb:
7993 case VFNMSUB132BF16Z128mbk:
7994 case VFNMSUB132BF16Z128mbkz:
7995 case VFNMSUB132BF16Z128mk:
7996 case VFNMSUB132BF16Z128mkz:
7997 case VFNMSUB132BF16Z128r:
7998 case VFNMSUB132BF16Z128rk:
7999 case VFNMSUB132BF16Z128rkz:
8000 case VFNMSUB132BF16Z256m:
8001 case VFNMSUB132BF16Z256mb:
8002 case VFNMSUB132BF16Z256mbk:
8003 case VFNMSUB132BF16Z256mbkz:
8004 case VFNMSUB132BF16Z256mk:
8005 case VFNMSUB132BF16Z256mkz:
8006 case VFNMSUB132BF16Z256r:
8007 case VFNMSUB132BF16Z256rk:
8008 case VFNMSUB132BF16Z256rkz:
8009 case VFNMSUB132BF16Zm:
8010 case VFNMSUB132BF16Zmb:
8011 case VFNMSUB132BF16Zmbk:
8012 case VFNMSUB132BF16Zmbkz:
8013 case VFNMSUB132BF16Zmk:
8014 case VFNMSUB132BF16Zmkz:
8015 case VFNMSUB132BF16Zr:
8016 case VFNMSUB132BF16Zrk:
8017 case VFNMSUB132BF16Zrkz:
8018 return true;
8019 }
8020 return false;
8021}
8022
8023bool isVFMADD213BF16(unsigned Opcode) {
8024 switch (Opcode) {
8025 case VFMADD213BF16Z128m:
8026 case VFMADD213BF16Z128mb:
8027 case VFMADD213BF16Z128mbk:
8028 case VFMADD213BF16Z128mbkz:
8029 case VFMADD213BF16Z128mk:
8030 case VFMADD213BF16Z128mkz:
8031 case VFMADD213BF16Z128r:
8032 case VFMADD213BF16Z128rk:
8033 case VFMADD213BF16Z128rkz:
8034 case VFMADD213BF16Z256m:
8035 case VFMADD213BF16Z256mb:
8036 case VFMADD213BF16Z256mbk:
8037 case VFMADD213BF16Z256mbkz:
8038 case VFMADD213BF16Z256mk:
8039 case VFMADD213BF16Z256mkz:
8040 case VFMADD213BF16Z256r:
8041 case VFMADD213BF16Z256rk:
8042 case VFMADD213BF16Z256rkz:
8043 case VFMADD213BF16Zm:
8044 case VFMADD213BF16Zmb:
8045 case VFMADD213BF16Zmbk:
8046 case VFMADD213BF16Zmbkz:
8047 case VFMADD213BF16Zmk:
8048 case VFMADD213BF16Zmkz:
8049 case VFMADD213BF16Zr:
8050 case VFMADD213BF16Zrk:
8051 case VFMADD213BF16Zrkz:
8052 return true;
8053 }
8054 return false;
8055}
8056
8057bool isVPUNPCKHWD(unsigned Opcode) {
8058 switch (Opcode) {
8059 case VPUNPCKHWDYrm:
8060 case VPUNPCKHWDYrr:
8061 case VPUNPCKHWDZ128rm:
8062 case VPUNPCKHWDZ128rmk:
8063 case VPUNPCKHWDZ128rmkz:
8064 case VPUNPCKHWDZ128rr:
8065 case VPUNPCKHWDZ128rrk:
8066 case VPUNPCKHWDZ128rrkz:
8067 case VPUNPCKHWDZ256rm:
8068 case VPUNPCKHWDZ256rmk:
8069 case VPUNPCKHWDZ256rmkz:
8070 case VPUNPCKHWDZ256rr:
8071 case VPUNPCKHWDZ256rrk:
8072 case VPUNPCKHWDZ256rrkz:
8073 case VPUNPCKHWDZrm:
8074 case VPUNPCKHWDZrmk:
8075 case VPUNPCKHWDZrmkz:
8076 case VPUNPCKHWDZrr:
8077 case VPUNPCKHWDZrrk:
8078 case VPUNPCKHWDZrrkz:
8079 case VPUNPCKHWDrm:
8080 case VPUNPCKHWDrr:
8081 return true;
8082 }
8083 return false;
8084}
8085
8086bool isVPERM2F128(unsigned Opcode) {
8087 switch (Opcode) {
8088 case VPERM2F128rmi:
8089 case VPERM2F128rri:
8090 return true;
8091 }
8092 return false;
8093}
8094
8095bool isINSD(unsigned Opcode) {
8096 return Opcode == INSL;
8097}
8098
8099bool isLFS(unsigned Opcode) {
8100 switch (Opcode) {
8101 case LFS16rm:
8102 case LFS32rm:
8103 case LFS64rm:
8104 return true;
8105 }
8106 return false;
8107}
8108
8109bool isFMULP(unsigned Opcode) {
8110 return Opcode == MUL_FPrST0;
8111}
8112
8113bool isCWD(unsigned Opcode) {
8114 return Opcode == CWD;
8115}
8116
8117bool isVDIVSS(unsigned Opcode) {
8118 switch (Opcode) {
8119 case VDIVSSZrm_Int:
8120 case VDIVSSZrmk_Int:
8121 case VDIVSSZrmkz_Int:
8122 case VDIVSSZrr_Int:
8123 case VDIVSSZrrb_Int:
8124 case VDIVSSZrrbk_Int:
8125 case VDIVSSZrrbkz_Int:
8126 case VDIVSSZrrk_Int:
8127 case VDIVSSZrrkz_Int:
8128 case VDIVSSrm_Int:
8129 case VDIVSSrr_Int:
8130 return true;
8131 }
8132 return false;
8133}
8134
8135bool isVPSRLQ(unsigned Opcode) {
8136 switch (Opcode) {
8137 case VPSRLQYri:
8138 case VPSRLQYrm:
8139 case VPSRLQYrr:
8140 case VPSRLQZ128mbi:
8141 case VPSRLQZ128mbik:
8142 case VPSRLQZ128mbikz:
8143 case VPSRLQZ128mi:
8144 case VPSRLQZ128mik:
8145 case VPSRLQZ128mikz:
8146 case VPSRLQZ128ri:
8147 case VPSRLQZ128rik:
8148 case VPSRLQZ128rikz:
8149 case VPSRLQZ128rm:
8150 case VPSRLQZ128rmk:
8151 case VPSRLQZ128rmkz:
8152 case VPSRLQZ128rr:
8153 case VPSRLQZ128rrk:
8154 case VPSRLQZ128rrkz:
8155 case VPSRLQZ256mbi:
8156 case VPSRLQZ256mbik:
8157 case VPSRLQZ256mbikz:
8158 case VPSRLQZ256mi:
8159 case VPSRLQZ256mik:
8160 case VPSRLQZ256mikz:
8161 case VPSRLQZ256ri:
8162 case VPSRLQZ256rik:
8163 case VPSRLQZ256rikz:
8164 case VPSRLQZ256rm:
8165 case VPSRLQZ256rmk:
8166 case VPSRLQZ256rmkz:
8167 case VPSRLQZ256rr:
8168 case VPSRLQZ256rrk:
8169 case VPSRLQZ256rrkz:
8170 case VPSRLQZmbi:
8171 case VPSRLQZmbik:
8172 case VPSRLQZmbikz:
8173 case VPSRLQZmi:
8174 case VPSRLQZmik:
8175 case VPSRLQZmikz:
8176 case VPSRLQZri:
8177 case VPSRLQZrik:
8178 case VPSRLQZrikz:
8179 case VPSRLQZrm:
8180 case VPSRLQZrmk:
8181 case VPSRLQZrmkz:
8182 case VPSRLQZrr:
8183 case VPSRLQZrrk:
8184 case VPSRLQZrrkz:
8185 case VPSRLQri:
8186 case VPSRLQrm:
8187 case VPSRLQrr:
8188 return true;
8189 }
8190 return false;
8191}
8192
8193bool isFSQRT(unsigned Opcode) {
8194 return Opcode == SQRT_F;
8195}
8196
8197bool isJRCXZ(unsigned Opcode) {
8198 return Opcode == JRCXZ;
8199}
8200
8201bool isVPMOVMSKB(unsigned Opcode) {
8202 switch (Opcode) {
8203 case VPMOVMSKBYrr:
8204 case VPMOVMSKBrr:
8205 return true;
8206 }
8207 return false;
8208}
8209
8210bool isAESDEC256KL(unsigned Opcode) {
8211 return Opcode == AESDEC256KL;
8212}
8213
8214bool isFLDENV(unsigned Opcode) {
8215 return Opcode == FLDENVm;
8216}
8217
8218bool isVPHSUBWD(unsigned Opcode) {
8219 switch (Opcode) {
8220 case VPHSUBWDrm:
8221 case VPHSUBWDrr:
8222 return true;
8223 }
8224 return false;
8225}
8226
8227bool isWBNOINVD(unsigned Opcode) {
8228 return Opcode == WBNOINVD;
8229}
8230
8231bool isVEXPANDPD(unsigned Opcode) {
8232 switch (Opcode) {
8233 case VEXPANDPDZ128rm:
8234 case VEXPANDPDZ128rmk:
8235 case VEXPANDPDZ128rmkz:
8236 case VEXPANDPDZ128rr:
8237 case VEXPANDPDZ128rrk:
8238 case VEXPANDPDZ128rrkz:
8239 case VEXPANDPDZ256rm:
8240 case VEXPANDPDZ256rmk:
8241 case VEXPANDPDZ256rmkz:
8242 case VEXPANDPDZ256rr:
8243 case VEXPANDPDZ256rrk:
8244 case VEXPANDPDZ256rrkz:
8245 case VEXPANDPDZrm:
8246 case VEXPANDPDZrmk:
8247 case VEXPANDPDZrmkz:
8248 case VEXPANDPDZrr:
8249 case VEXPANDPDZrrk:
8250 case VEXPANDPDZrrkz:
8251 return true;
8252 }
8253 return false;
8254}
8255
8256bool isFYL2XP1(unsigned Opcode) {
8257 return Opcode == FYL2XP1;
8258}
8259
8260bool isPREFETCHT2(unsigned Opcode) {
8261 return Opcode == PREFETCHT2;
8262}
8263
8264bool isVPDPBSUDS(unsigned Opcode) {
8265 switch (Opcode) {
8266 case VPDPBSUDSYrm:
8267 case VPDPBSUDSYrr:
8268 case VPDPBSUDSZ128rm:
8269 case VPDPBSUDSZ128rmb:
8270 case VPDPBSUDSZ128rmbk:
8271 case VPDPBSUDSZ128rmbkz:
8272 case VPDPBSUDSZ128rmk:
8273 case VPDPBSUDSZ128rmkz:
8274 case VPDPBSUDSZ128rr:
8275 case VPDPBSUDSZ128rrk:
8276 case VPDPBSUDSZ128rrkz:
8277 case VPDPBSUDSZ256rm:
8278 case VPDPBSUDSZ256rmb:
8279 case VPDPBSUDSZ256rmbk:
8280 case VPDPBSUDSZ256rmbkz:
8281 case VPDPBSUDSZ256rmk:
8282 case VPDPBSUDSZ256rmkz:
8283 case VPDPBSUDSZ256rr:
8284 case VPDPBSUDSZ256rrk:
8285 case VPDPBSUDSZ256rrkz:
8286 case VPDPBSUDSZrm:
8287 case VPDPBSUDSZrmb:
8288 case VPDPBSUDSZrmbk:
8289 case VPDPBSUDSZrmbkz:
8290 case VPDPBSUDSZrmk:
8291 case VPDPBSUDSZrmkz:
8292 case VPDPBSUDSZrr:
8293 case VPDPBSUDSZrrk:
8294 case VPDPBSUDSZrrkz:
8295 case VPDPBSUDSrm:
8296 case VPDPBSUDSrr:
8297 return true;
8298 }
8299 return false;
8300}
8301
8302bool isVSHA512MSG2(unsigned Opcode) {
8303 return Opcode == VSHA512MSG2rr;
8304}
8305
8306bool isPMULHUW(unsigned Opcode) {
8307 switch (Opcode) {
8308 case MMX_PMULHUWrm:
8309 case MMX_PMULHUWrr:
8310 case PMULHUWrm:
8311 case PMULHUWrr:
8312 return true;
8313 }
8314 return false;
8315}
8316
8317bool isKANDNB(unsigned Opcode) {
8318 return Opcode == KANDNBkk;
8319}
8320
8321bool isVCVTUW2PH(unsigned Opcode) {
8322 switch (Opcode) {
8323 case VCVTUW2PHZ128rm:
8324 case VCVTUW2PHZ128rmb:
8325 case VCVTUW2PHZ128rmbk:
8326 case VCVTUW2PHZ128rmbkz:
8327 case VCVTUW2PHZ128rmk:
8328 case VCVTUW2PHZ128rmkz:
8329 case VCVTUW2PHZ128rr:
8330 case VCVTUW2PHZ128rrk:
8331 case VCVTUW2PHZ128rrkz:
8332 case VCVTUW2PHZ256rm:
8333 case VCVTUW2PHZ256rmb:
8334 case VCVTUW2PHZ256rmbk:
8335 case VCVTUW2PHZ256rmbkz:
8336 case VCVTUW2PHZ256rmk:
8337 case VCVTUW2PHZ256rmkz:
8338 case VCVTUW2PHZ256rr:
8339 case VCVTUW2PHZ256rrk:
8340 case VCVTUW2PHZ256rrkz:
8341 case VCVTUW2PHZrm:
8342 case VCVTUW2PHZrmb:
8343 case VCVTUW2PHZrmbk:
8344 case VCVTUW2PHZrmbkz:
8345 case VCVTUW2PHZrmk:
8346 case VCVTUW2PHZrmkz:
8347 case VCVTUW2PHZrr:
8348 case VCVTUW2PHZrrb:
8349 case VCVTUW2PHZrrbk:
8350 case VCVTUW2PHZrrbkz:
8351 case VCVTUW2PHZrrk:
8352 case VCVTUW2PHZrrkz:
8353 return true;
8354 }
8355 return false;
8356}
8357
8358bool isAESDECWIDE256KL(unsigned Opcode) {
8359 return Opcode == AESDECWIDE256KL;
8360}
8361
8362bool isVPGATHERDD(unsigned Opcode) {
8363 switch (Opcode) {
8364 case VPGATHERDDYrm:
8365 case VPGATHERDDZ128rm:
8366 case VPGATHERDDZ256rm:
8367 case VPGATHERDDZrm:
8368 case VPGATHERDDrm:
8369 return true;
8370 }
8371 return false;
8372}
8373
8374bool isVREDUCESH(unsigned Opcode) {
8375 switch (Opcode) {
8376 case VREDUCESHZrmi:
8377 case VREDUCESHZrmik:
8378 case VREDUCESHZrmikz:
8379 case VREDUCESHZrri:
8380 case VREDUCESHZrrib:
8381 case VREDUCESHZrribk:
8382 case VREDUCESHZrribkz:
8383 case VREDUCESHZrrik:
8384 case VREDUCESHZrrikz:
8385 return true;
8386 }
8387 return false;
8388}
8389
8390bool isPOPFQ(unsigned Opcode) {
8391 return Opcode == POPF64;
8392}
8393
8394bool isPAVGUSB(unsigned Opcode) {
8395 switch (Opcode) {
8396 case PAVGUSBrm:
8397 case PAVGUSBrr:
8398 return true;
8399 }
8400 return false;
8401}
8402
8403bool isVALIGND(unsigned Opcode) {
8404 switch (Opcode) {
8405 case VALIGNDZ128rmbi:
8406 case VALIGNDZ128rmbik:
8407 case VALIGNDZ128rmbikz:
8408 case VALIGNDZ128rmi:
8409 case VALIGNDZ128rmik:
8410 case VALIGNDZ128rmikz:
8411 case VALIGNDZ128rri:
8412 case VALIGNDZ128rrik:
8413 case VALIGNDZ128rrikz:
8414 case VALIGNDZ256rmbi:
8415 case VALIGNDZ256rmbik:
8416 case VALIGNDZ256rmbikz:
8417 case VALIGNDZ256rmi:
8418 case VALIGNDZ256rmik:
8419 case VALIGNDZ256rmikz:
8420 case VALIGNDZ256rri:
8421 case VALIGNDZ256rrik:
8422 case VALIGNDZ256rrikz:
8423 case VALIGNDZrmbi:
8424 case VALIGNDZrmbik:
8425 case VALIGNDZrmbikz:
8426 case VALIGNDZrmi:
8427 case VALIGNDZrmik:
8428 case VALIGNDZrmikz:
8429 case VALIGNDZrri:
8430 case VALIGNDZrrik:
8431 case VALIGNDZrrikz:
8432 return true;
8433 }
8434 return false;
8435}
8436
8437bool isVPHMINPOSUW(unsigned Opcode) {
8438 switch (Opcode) {
8439 case VPHMINPOSUWrm:
8440 case VPHMINPOSUWrr:
8441 return true;
8442 }
8443 return false;
8444}
8445
8446bool isLIDTD(unsigned Opcode) {
8447 return Opcode == LIDT32m;
8448}
8449
8450bool isVPERMT2PD(unsigned Opcode) {
8451 switch (Opcode) {
8452 case VPERMT2PDZ128rm:
8453 case VPERMT2PDZ128rmb:
8454 case VPERMT2PDZ128rmbk:
8455 case VPERMT2PDZ128rmbkz:
8456 case VPERMT2PDZ128rmk:
8457 case VPERMT2PDZ128rmkz:
8458 case VPERMT2PDZ128rr:
8459 case VPERMT2PDZ128rrk:
8460 case VPERMT2PDZ128rrkz:
8461 case VPERMT2PDZ256rm:
8462 case VPERMT2PDZ256rmb:
8463 case VPERMT2PDZ256rmbk:
8464 case VPERMT2PDZ256rmbkz:
8465 case VPERMT2PDZ256rmk:
8466 case VPERMT2PDZ256rmkz:
8467 case VPERMT2PDZ256rr:
8468 case VPERMT2PDZ256rrk:
8469 case VPERMT2PDZ256rrkz:
8470 case VPERMT2PDZrm:
8471 case VPERMT2PDZrmb:
8472 case VPERMT2PDZrmbk:
8473 case VPERMT2PDZrmbkz:
8474 case VPERMT2PDZrmk:
8475 case VPERMT2PDZrmkz:
8476 case VPERMT2PDZrr:
8477 case VPERMT2PDZrrk:
8478 case VPERMT2PDZrrkz:
8479 return true;
8480 }
8481 return false;
8482}
8483
8484bool isVMLAUNCH(unsigned Opcode) {
8485 return Opcode == VMLAUNCH;
8486}
8487
8488bool isVPXORQ(unsigned Opcode) {
8489 switch (Opcode) {
8490 case VPXORQZ128rm:
8491 case VPXORQZ128rmb:
8492 case VPXORQZ128rmbk:
8493 case VPXORQZ128rmbkz:
8494 case VPXORQZ128rmk:
8495 case VPXORQZ128rmkz:
8496 case VPXORQZ128rr:
8497 case VPXORQZ128rrk:
8498 case VPXORQZ128rrkz:
8499 case VPXORQZ256rm:
8500 case VPXORQZ256rmb:
8501 case VPXORQZ256rmbk:
8502 case VPXORQZ256rmbkz:
8503 case VPXORQZ256rmk:
8504 case VPXORQZ256rmkz:
8505 case VPXORQZ256rr:
8506 case VPXORQZ256rrk:
8507 case VPXORQZ256rrkz:
8508 case VPXORQZrm:
8509 case VPXORQZrmb:
8510 case VPXORQZrmbk:
8511 case VPXORQZrmbkz:
8512 case VPXORQZrmk:
8513 case VPXORQZrmkz:
8514 case VPXORQZrr:
8515 case VPXORQZrrk:
8516 case VPXORQZrrkz:
8517 return true;
8518 }
8519 return false;
8520}
8521
8522bool isMOVNTDQ(unsigned Opcode) {
8523 return Opcode == MOVNTDQmr;
8524}
8525
8526bool isPOP2P(unsigned Opcode) {
8527 return Opcode == POP2P;
8528}
8529
8530bool isVADDPD(unsigned Opcode) {
8531 switch (Opcode) {
8532 case VADDPDYrm:
8533 case VADDPDYrr:
8534 case VADDPDZ128rm:
8535 case VADDPDZ128rmb:
8536 case VADDPDZ128rmbk:
8537 case VADDPDZ128rmbkz:
8538 case VADDPDZ128rmk:
8539 case VADDPDZ128rmkz:
8540 case VADDPDZ128rr:
8541 case VADDPDZ128rrk:
8542 case VADDPDZ128rrkz:
8543 case VADDPDZ256rm:
8544 case VADDPDZ256rmb:
8545 case VADDPDZ256rmbk:
8546 case VADDPDZ256rmbkz:
8547 case VADDPDZ256rmk:
8548 case VADDPDZ256rmkz:
8549 case VADDPDZ256rr:
8550 case VADDPDZ256rrk:
8551 case VADDPDZ256rrkz:
8552 case VADDPDZrm:
8553 case VADDPDZrmb:
8554 case VADDPDZrmbk:
8555 case VADDPDZrmbkz:
8556 case VADDPDZrmk:
8557 case VADDPDZrmkz:
8558 case VADDPDZrr:
8559 case VADDPDZrrb:
8560 case VADDPDZrrbk:
8561 case VADDPDZrrbkz:
8562 case VADDPDZrrk:
8563 case VADDPDZrrkz:
8564 case VADDPDrm:
8565 case VADDPDrr:
8566 return true;
8567 }
8568 return false;
8569}
8570
8571bool isSMSW(unsigned Opcode) {
8572 switch (Opcode) {
8573 case SMSW16m:
8574 case SMSW16r:
8575 case SMSW32r:
8576 case SMSW64r:
8577 return true;
8578 }
8579 return false;
8580}
8581
8582bool isVEXP2PD(unsigned Opcode) {
8583 switch (Opcode) {
8584 case VEXP2PDZm:
8585 case VEXP2PDZmb:
8586 case VEXP2PDZmbk:
8587 case VEXP2PDZmbkz:
8588 case VEXP2PDZmk:
8589 case VEXP2PDZmkz:
8590 case VEXP2PDZr:
8591 case VEXP2PDZrb:
8592 case VEXP2PDZrbk:
8593 case VEXP2PDZrbkz:
8594 case VEXP2PDZrk:
8595 case VEXP2PDZrkz:
8596 return true;
8597 }
8598 return false;
8599}
8600
8601bool isPMULUDQ(unsigned Opcode) {
8602 switch (Opcode) {
8603 case MMX_PMULUDQrm:
8604 case MMX_PMULUDQrr:
8605 case PMULUDQrm:
8606 case PMULUDQrr:
8607 return true;
8608 }
8609 return false;
8610}
8611
8612bool isIRET(unsigned Opcode) {
8613 return Opcode == IRET16;
8614}
8615
8616bool isMULPS(unsigned Opcode) {
8617 switch (Opcode) {
8618 case MULPSrm:
8619 case MULPSrr:
8620 return true;
8621 }
8622 return false;
8623}
8624
8625bool isTDPBF8PS(unsigned Opcode) {
8626 return Opcode == TDPBF8PS;
8627}
8628
8629bool isVFNMSUBPD(unsigned Opcode) {
8630 switch (Opcode) {
8631 case VFNMSUBPD4Ymr:
8632 case VFNMSUBPD4Yrm:
8633 case VFNMSUBPD4Yrr:
8634 case VFNMSUBPD4Yrr_REV:
8635 case VFNMSUBPD4mr:
8636 case VFNMSUBPD4rm:
8637 case VFNMSUBPD4rr:
8638 case VFNMSUBPD4rr_REV:
8639 return true;
8640 }
8641 return false;
8642}
8643
8644bool isPHADDW(unsigned Opcode) {
8645 switch (Opcode) {
8646 case MMX_PHADDWrm:
8647 case MMX_PHADDWrr:
8648 case PHADDWrm:
8649 case PHADDWrr:
8650 return true;
8651 }
8652 return false;
8653}
8654
8655bool isRDSEED(unsigned Opcode) {
8656 switch (Opcode) {
8657 case RDSEED16r:
8658 case RDSEED32r:
8659 case RDSEED64r:
8660 return true;
8661 }
8662 return false;
8663}
8664
8665bool isVPSHLW(unsigned Opcode) {
8666 switch (Opcode) {
8667 case VPSHLWmr:
8668 case VPSHLWrm:
8669 case VPSHLWrr:
8670 case VPSHLWrr_REV:
8671 return true;
8672 }
8673 return false;
8674}
8675
8676bool isRMPUPDATE(unsigned Opcode) {
8677 return Opcode == RMPUPDATE;
8678}
8679
8680bool isVFMADD231PH(unsigned Opcode) {
8681 switch (Opcode) {
8682 case VFMADD231PHZ128m:
8683 case VFMADD231PHZ128mb:
8684 case VFMADD231PHZ128mbk:
8685 case VFMADD231PHZ128mbkz:
8686 case VFMADD231PHZ128mk:
8687 case VFMADD231PHZ128mkz:
8688 case VFMADD231PHZ128r:
8689 case VFMADD231PHZ128rk:
8690 case VFMADD231PHZ128rkz:
8691 case VFMADD231PHZ256m:
8692 case VFMADD231PHZ256mb:
8693 case VFMADD231PHZ256mbk:
8694 case VFMADD231PHZ256mbkz:
8695 case VFMADD231PHZ256mk:
8696 case VFMADD231PHZ256mkz:
8697 case VFMADD231PHZ256r:
8698 case VFMADD231PHZ256rk:
8699 case VFMADD231PHZ256rkz:
8700 case VFMADD231PHZm:
8701 case VFMADD231PHZmb:
8702 case VFMADD231PHZmbk:
8703 case VFMADD231PHZmbkz:
8704 case VFMADD231PHZmk:
8705 case VFMADD231PHZmkz:
8706 case VFMADD231PHZr:
8707 case VFMADD231PHZrb:
8708 case VFMADD231PHZrbk:
8709 case VFMADD231PHZrbkz:
8710 case VFMADD231PHZrk:
8711 case VFMADD231PHZrkz:
8712 return true;
8713 }
8714 return false;
8715}
8716
8717bool isVPSHAD(unsigned Opcode) {
8718 switch (Opcode) {
8719 case VPSHADmr:
8720 case VPSHADrm:
8721 case VPSHADrr:
8722 case VPSHADrr_REV:
8723 return true;
8724 }
8725 return false;
8726}
8727
8728bool isCLWB(unsigned Opcode) {
8729 return Opcode == CLWB;
8730}
8731
8732bool isPSUBUSB(unsigned Opcode) {
8733 switch (Opcode) {
8734 case MMX_PSUBUSBrm:
8735 case MMX_PSUBUSBrr:
8736 case PSUBUSBrm:
8737 case PSUBUSBrr:
8738 return true;
8739 }
8740 return false;
8741}
8742
8743bool isVCVTTSD2USI(unsigned Opcode) {
8744 switch (Opcode) {
8745 case VCVTTSD2USI64Zrm_Int:
8746 case VCVTTSD2USI64Zrr_Int:
8747 case VCVTTSD2USI64Zrrb_Int:
8748 case VCVTTSD2USIZrm_Int:
8749 case VCVTTSD2USIZrr_Int:
8750 case VCVTTSD2USIZrrb_Int:
8751 return true;
8752 }
8753 return false;
8754}
8755
8756bool isVEXTRACTPS(unsigned Opcode) {
8757 switch (Opcode) {
8758 case VEXTRACTPSZmri:
8759 case VEXTRACTPSZrri:
8760 case VEXTRACTPSmri:
8761 case VEXTRACTPSrri:
8762 return true;
8763 }
8764 return false;
8765}
8766
8767bool isMOVLPD(unsigned Opcode) {
8768 switch (Opcode) {
8769 case MOVLPDmr:
8770 case MOVLPDrm:
8771 return true;
8772 }
8773 return false;
8774}
8775
8776bool isLGDTD(unsigned Opcode) {
8777 return Opcode == LGDT32m;
8778}
8779
8780bool isVPBROADCASTMB2Q(unsigned Opcode) {
8781 switch (Opcode) {
8782 case VPBROADCASTMB2QZ128rr:
8783 case VPBROADCASTMB2QZ256rr:
8784 case VPBROADCASTMB2QZrr:
8785 return true;
8786 }
8787 return false;
8788}
8789
8790bool isOUT(unsigned Opcode) {
8791 switch (Opcode) {
8792 case OUT16ir:
8793 case OUT16rr:
8794 case OUT32ir:
8795 case OUT32rr:
8796 case OUT8ir:
8797 case OUT8rr:
8798 return true;
8799 }
8800 return false;
8801}
8802
8803bool isVMSAVE(unsigned Opcode) {
8804 switch (Opcode) {
8805 case VMSAVE32:
8806 case VMSAVE64:
8807 return true;
8808 }
8809 return false;
8810}
8811
8812bool isVCVTQQ2PD(unsigned Opcode) {
8813 switch (Opcode) {
8814 case VCVTQQ2PDZ128rm:
8815 case VCVTQQ2PDZ128rmb:
8816 case VCVTQQ2PDZ128rmbk:
8817 case VCVTQQ2PDZ128rmbkz:
8818 case VCVTQQ2PDZ128rmk:
8819 case VCVTQQ2PDZ128rmkz:
8820 case VCVTQQ2PDZ128rr:
8821 case VCVTQQ2PDZ128rrk:
8822 case VCVTQQ2PDZ128rrkz:
8823 case VCVTQQ2PDZ256rm:
8824 case VCVTQQ2PDZ256rmb:
8825 case VCVTQQ2PDZ256rmbk:
8826 case VCVTQQ2PDZ256rmbkz:
8827 case VCVTQQ2PDZ256rmk:
8828 case VCVTQQ2PDZ256rmkz:
8829 case VCVTQQ2PDZ256rr:
8830 case VCVTQQ2PDZ256rrk:
8831 case VCVTQQ2PDZ256rrkz:
8832 case VCVTQQ2PDZrm:
8833 case VCVTQQ2PDZrmb:
8834 case VCVTQQ2PDZrmbk:
8835 case VCVTQQ2PDZrmbkz:
8836 case VCVTQQ2PDZrmk:
8837 case VCVTQQ2PDZrmkz:
8838 case VCVTQQ2PDZrr:
8839 case VCVTQQ2PDZrrb:
8840 case VCVTQQ2PDZrrbk:
8841 case VCVTQQ2PDZrrbkz:
8842 case VCVTQQ2PDZrrk:
8843 case VCVTQQ2PDZrrkz:
8844 return true;
8845 }
8846 return false;
8847}
8848
8849bool isVFMADD213PH(unsigned Opcode) {
8850 switch (Opcode) {
8851 case VFMADD213PHZ128m:
8852 case VFMADD213PHZ128mb:
8853 case VFMADD213PHZ128mbk:
8854 case VFMADD213PHZ128mbkz:
8855 case VFMADD213PHZ128mk:
8856 case VFMADD213PHZ128mkz:
8857 case VFMADD213PHZ128r:
8858 case VFMADD213PHZ128rk:
8859 case VFMADD213PHZ128rkz:
8860 case VFMADD213PHZ256m:
8861 case VFMADD213PHZ256mb:
8862 case VFMADD213PHZ256mbk:
8863 case VFMADD213PHZ256mbkz:
8864 case VFMADD213PHZ256mk:
8865 case VFMADD213PHZ256mkz:
8866 case VFMADD213PHZ256r:
8867 case VFMADD213PHZ256rk:
8868 case VFMADD213PHZ256rkz:
8869 case VFMADD213PHZm:
8870 case VFMADD213PHZmb:
8871 case VFMADD213PHZmbk:
8872 case VFMADD213PHZmbkz:
8873 case VFMADD213PHZmk:
8874 case VFMADD213PHZmkz:
8875 case VFMADD213PHZr:
8876 case VFMADD213PHZrb:
8877 case VFMADD213PHZrbk:
8878 case VFMADD213PHZrbkz:
8879 case VFMADD213PHZrk:
8880 case VFMADD213PHZrkz:
8881 return true;
8882 }
8883 return false;
8884}
8885
8886bool isFCMOVBE(unsigned Opcode) {
8887 return Opcode == CMOVBE_F;
8888}
8889
8890bool isMOVSHDUP(unsigned Opcode) {
8891 switch (Opcode) {
8892 case MOVSHDUPrm:
8893 case MOVSHDUPrr:
8894 return true;
8895 }
8896 return false;
8897}
8898
8899bool isVPMOVUSQB(unsigned Opcode) {
8900 switch (Opcode) {
8901 case VPMOVUSQBZ128mr:
8902 case VPMOVUSQBZ128mrk:
8903 case VPMOVUSQBZ128rr:
8904 case VPMOVUSQBZ128rrk:
8905 case VPMOVUSQBZ128rrkz:
8906 case VPMOVUSQBZ256mr:
8907 case VPMOVUSQBZ256mrk:
8908 case VPMOVUSQBZ256rr:
8909 case VPMOVUSQBZ256rrk:
8910 case VPMOVUSQBZ256rrkz:
8911 case VPMOVUSQBZmr:
8912 case VPMOVUSQBZmrk:
8913 case VPMOVUSQBZrr:
8914 case VPMOVUSQBZrrk:
8915 case VPMOVUSQBZrrkz:
8916 return true;
8917 }
8918 return false;
8919}
8920
8921bool isFIST(unsigned Opcode) {
8922 switch (Opcode) {
8923 case IST_F16m:
8924 case IST_F32m:
8925 return true;
8926 }
8927 return false;
8928}
8929
8930bool isHADDPD(unsigned Opcode) {
8931 switch (Opcode) {
8932 case HADDPDrm:
8933 case HADDPDrr:
8934 return true;
8935 }
8936 return false;
8937}
8938
8939bool isPACKSSWB(unsigned Opcode) {
8940 switch (Opcode) {
8941 case MMX_PACKSSWBrm:
8942 case MMX_PACKSSWBrr:
8943 case PACKSSWBrm:
8944 case PACKSSWBrr:
8945 return true;
8946 }
8947 return false;
8948}
8949
8950bool isVPMACSSDQH(unsigned Opcode) {
8951 switch (Opcode) {
8952 case VPMACSSDQHrm:
8953 case VPMACSSDQHrr:
8954 return true;
8955 }
8956 return false;
8957}
8958
8959bool isVFNMSUB132SD(unsigned Opcode) {
8960 switch (Opcode) {
8961 case VFNMSUB132SDZm_Int:
8962 case VFNMSUB132SDZmk_Int:
8963 case VFNMSUB132SDZmkz_Int:
8964 case VFNMSUB132SDZr_Int:
8965 case VFNMSUB132SDZrb_Int:
8966 case VFNMSUB132SDZrbk_Int:
8967 case VFNMSUB132SDZrbkz_Int:
8968 case VFNMSUB132SDZrk_Int:
8969 case VFNMSUB132SDZrkz_Int:
8970 case VFNMSUB132SDm_Int:
8971 case VFNMSUB132SDr_Int:
8972 return true;
8973 }
8974 return false;
8975}
8976
8977bool isVPMASKMOVQ(unsigned Opcode) {
8978 switch (Opcode) {
8979 case VPMASKMOVQYmr:
8980 case VPMASKMOVQYrm:
8981 case VPMASKMOVQmr:
8982 case VPMASKMOVQrm:
8983 return true;
8984 }
8985 return false;
8986}
8987
8988bool isVCOMPRESSPD(unsigned Opcode) {
8989 switch (Opcode) {
8990 case VCOMPRESSPDZ128mr:
8991 case VCOMPRESSPDZ128mrk:
8992 case VCOMPRESSPDZ128rr:
8993 case VCOMPRESSPDZ128rrk:
8994 case VCOMPRESSPDZ128rrkz:
8995 case VCOMPRESSPDZ256mr:
8996 case VCOMPRESSPDZ256mrk:
8997 case VCOMPRESSPDZ256rr:
8998 case VCOMPRESSPDZ256rrk:
8999 case VCOMPRESSPDZ256rrkz:
9000 case VCOMPRESSPDZmr:
9001 case VCOMPRESSPDZmrk:
9002 case VCOMPRESSPDZrr:
9003 case VCOMPRESSPDZrrk:
9004 case VCOMPRESSPDZrrkz:
9005 return true;
9006 }
9007 return false;
9008}
9009
9010bool isVFMADD213SS(unsigned Opcode) {
9011 switch (Opcode) {
9012 case VFMADD213SSZm_Int:
9013 case VFMADD213SSZmk_Int:
9014 case VFMADD213SSZmkz_Int:
9015 case VFMADD213SSZr_Int:
9016 case VFMADD213SSZrb_Int:
9017 case VFMADD213SSZrbk_Int:
9018 case VFMADD213SSZrbkz_Int:
9019 case VFMADD213SSZrk_Int:
9020 case VFMADD213SSZrkz_Int:
9021 case VFMADD213SSm_Int:
9022 case VFMADD213SSr_Int:
9023 return true;
9024 }
9025 return false;
9026}
9027
9028bool isVPCMPQ(unsigned Opcode) {
9029 switch (Opcode) {
9030 case VPCMPQZ128rmbi:
9031 case VPCMPQZ128rmbik:
9032 case VPCMPQZ128rmi:
9033 case VPCMPQZ128rmik:
9034 case VPCMPQZ128rri:
9035 case VPCMPQZ128rrik:
9036 case VPCMPQZ256rmbi:
9037 case VPCMPQZ256rmbik:
9038 case VPCMPQZ256rmi:
9039 case VPCMPQZ256rmik:
9040 case VPCMPQZ256rri:
9041 case VPCMPQZ256rrik:
9042 case VPCMPQZrmbi:
9043 case VPCMPQZrmbik:
9044 case VPCMPQZrmi:
9045 case VPCMPQZrmik:
9046 case VPCMPQZrri:
9047 case VPCMPQZrrik:
9048 return true;
9049 }
9050 return false;
9051}
9052
9053bool isVADDSH(unsigned Opcode) {
9054 switch (Opcode) {
9055 case VADDSHZrm_Int:
9056 case VADDSHZrmk_Int:
9057 case VADDSHZrmkz_Int:
9058 case VADDSHZrr_Int:
9059 case VADDSHZrrb_Int:
9060 case VADDSHZrrbk_Int:
9061 case VADDSHZrrbkz_Int:
9062 case VADDSHZrrk_Int:
9063 case VADDSHZrrkz_Int:
9064 return true;
9065 }
9066 return false;
9067}
9068
9069bool isVFNMADDSD(unsigned Opcode) {
9070 switch (Opcode) {
9071 case VFNMADDSD4mr:
9072 case VFNMADDSD4rm:
9073 case VFNMADDSD4rr:
9074 case VFNMADDSD4rr_REV:
9075 return true;
9076 }
9077 return false;
9078}
9079
9080bool isUMWAIT(unsigned Opcode) {
9081 return Opcode == UMWAIT;
9082}
9083
9084bool isVPUNPCKHDQ(unsigned Opcode) {
9085 switch (Opcode) {
9086 case VPUNPCKHDQYrm:
9087 case VPUNPCKHDQYrr:
9088 case VPUNPCKHDQZ128rm:
9089 case VPUNPCKHDQZ128rmb:
9090 case VPUNPCKHDQZ128rmbk:
9091 case VPUNPCKHDQZ128rmbkz:
9092 case VPUNPCKHDQZ128rmk:
9093 case VPUNPCKHDQZ128rmkz:
9094 case VPUNPCKHDQZ128rr:
9095 case VPUNPCKHDQZ128rrk:
9096 case VPUNPCKHDQZ128rrkz:
9097 case VPUNPCKHDQZ256rm:
9098 case VPUNPCKHDQZ256rmb:
9099 case VPUNPCKHDQZ256rmbk:
9100 case VPUNPCKHDQZ256rmbkz:
9101 case VPUNPCKHDQZ256rmk:
9102 case VPUNPCKHDQZ256rmkz:
9103 case VPUNPCKHDQZ256rr:
9104 case VPUNPCKHDQZ256rrk:
9105 case VPUNPCKHDQZ256rrkz:
9106 case VPUNPCKHDQZrm:
9107 case VPUNPCKHDQZrmb:
9108 case VPUNPCKHDQZrmbk:
9109 case VPUNPCKHDQZrmbkz:
9110 case VPUNPCKHDQZrmk:
9111 case VPUNPCKHDQZrmkz:
9112 case VPUNPCKHDQZrr:
9113 case VPUNPCKHDQZrrk:
9114 case VPUNPCKHDQZrrkz:
9115 case VPUNPCKHDQrm:
9116 case VPUNPCKHDQrr:
9117 return true;
9118 }
9119 return false;
9120}
9121
9122bool isLCALL(unsigned Opcode) {
9123 switch (Opcode) {
9124 case FARCALL16i:
9125 case FARCALL16m:
9126 case FARCALL32i:
9127 case FARCALL64m:
9128 return true;
9129 }
9130 return false;
9131}
9132
9133bool isAESDEC128KL(unsigned Opcode) {
9134 return Opcode == AESDEC128KL;
9135}
9136
9137bool isVSUBPS(unsigned Opcode) {
9138 switch (Opcode) {
9139 case VSUBPSYrm:
9140 case VSUBPSYrr:
9141 case VSUBPSZ128rm:
9142 case VSUBPSZ128rmb:
9143 case VSUBPSZ128rmbk:
9144 case VSUBPSZ128rmbkz:
9145 case VSUBPSZ128rmk:
9146 case VSUBPSZ128rmkz:
9147 case VSUBPSZ128rr:
9148 case VSUBPSZ128rrk:
9149 case VSUBPSZ128rrkz:
9150 case VSUBPSZ256rm:
9151 case VSUBPSZ256rmb:
9152 case VSUBPSZ256rmbk:
9153 case VSUBPSZ256rmbkz:
9154 case VSUBPSZ256rmk:
9155 case VSUBPSZ256rmkz:
9156 case VSUBPSZ256rr:
9157 case VSUBPSZ256rrk:
9158 case VSUBPSZ256rrkz:
9159 case VSUBPSZrm:
9160 case VSUBPSZrmb:
9161 case VSUBPSZrmbk:
9162 case VSUBPSZrmbkz:
9163 case VSUBPSZrmk:
9164 case VSUBPSZrmkz:
9165 case VSUBPSZrr:
9166 case VSUBPSZrrb:
9167 case VSUBPSZrrbk:
9168 case VSUBPSZrrbkz:
9169 case VSUBPSZrrk:
9170 case VSUBPSZrrkz:
9171 case VSUBPSrm:
9172 case VSUBPSrr:
9173 return true;
9174 }
9175 return false;
9176}
9177
9178bool isFSTP(unsigned Opcode) {
9179 switch (Opcode) {
9180 case ST_FP32m:
9181 case ST_FP64m:
9182 case ST_FP80m:
9183 case ST_FPrr:
9184 return true;
9185 }
9186 return false;
9187}
9188
9189bool isVCVTUDQ2PD(unsigned Opcode) {
9190 switch (Opcode) {
9191 case VCVTUDQ2PDZ128rm:
9192 case VCVTUDQ2PDZ128rmb:
9193 case VCVTUDQ2PDZ128rmbk:
9194 case VCVTUDQ2PDZ128rmbkz:
9195 case VCVTUDQ2PDZ128rmk:
9196 case VCVTUDQ2PDZ128rmkz:
9197 case VCVTUDQ2PDZ128rr:
9198 case VCVTUDQ2PDZ128rrk:
9199 case VCVTUDQ2PDZ128rrkz:
9200 case VCVTUDQ2PDZ256rm:
9201 case VCVTUDQ2PDZ256rmb:
9202 case VCVTUDQ2PDZ256rmbk:
9203 case VCVTUDQ2PDZ256rmbkz:
9204 case VCVTUDQ2PDZ256rmk:
9205 case VCVTUDQ2PDZ256rmkz:
9206 case VCVTUDQ2PDZ256rr:
9207 case VCVTUDQ2PDZ256rrk:
9208 case VCVTUDQ2PDZ256rrkz:
9209 case VCVTUDQ2PDZrm:
9210 case VCVTUDQ2PDZrmb:
9211 case VCVTUDQ2PDZrmbk:
9212 case VCVTUDQ2PDZrmbkz:
9213 case VCVTUDQ2PDZrmk:
9214 case VCVTUDQ2PDZrmkz:
9215 case VCVTUDQ2PDZrr:
9216 case VCVTUDQ2PDZrrk:
9217 case VCVTUDQ2PDZrrkz:
9218 return true;
9219 }
9220 return false;
9221}
9222
9223bool isVPMOVSWB(unsigned Opcode) {
9224 switch (Opcode) {
9225 case VPMOVSWBZ128mr:
9226 case VPMOVSWBZ128mrk:
9227 case VPMOVSWBZ128rr:
9228 case VPMOVSWBZ128rrk:
9229 case VPMOVSWBZ128rrkz:
9230 case VPMOVSWBZ256mr:
9231 case VPMOVSWBZ256mrk:
9232 case VPMOVSWBZ256rr:
9233 case VPMOVSWBZ256rrk:
9234 case VPMOVSWBZ256rrkz:
9235 case VPMOVSWBZmr:
9236 case VPMOVSWBZmrk:
9237 case VPMOVSWBZrr:
9238 case VPMOVSWBZrrk:
9239 case VPMOVSWBZrrkz:
9240 return true;
9241 }
9242 return false;
9243}
9244
9245bool isVPANDNQ(unsigned Opcode) {
9246 switch (Opcode) {
9247 case VPANDNQZ128rm:
9248 case VPANDNQZ128rmb:
9249 case VPANDNQZ128rmbk:
9250 case VPANDNQZ128rmbkz:
9251 case VPANDNQZ128rmk:
9252 case VPANDNQZ128rmkz:
9253 case VPANDNQZ128rr:
9254 case VPANDNQZ128rrk:
9255 case VPANDNQZ128rrkz:
9256 case VPANDNQZ256rm:
9257 case VPANDNQZ256rmb:
9258 case VPANDNQZ256rmbk:
9259 case VPANDNQZ256rmbkz:
9260 case VPANDNQZ256rmk:
9261 case VPANDNQZ256rmkz:
9262 case VPANDNQZ256rr:
9263 case VPANDNQZ256rrk:
9264 case VPANDNQZ256rrkz:
9265 case VPANDNQZrm:
9266 case VPANDNQZrmb:
9267 case VPANDNQZrmbk:
9268 case VPANDNQZrmbkz:
9269 case VPANDNQZrmk:
9270 case VPANDNQZrmkz:
9271 case VPANDNQZrr:
9272 case VPANDNQZrrk:
9273 case VPANDNQZrrkz:
9274 return true;
9275 }
9276 return false;
9277}
9278
9279bool isSYSENTER(unsigned Opcode) {
9280 return Opcode == SYSENTER;
9281}
9282
9283bool isVPHADDWD(unsigned Opcode) {
9284 switch (Opcode) {
9285 case VPHADDWDrm:
9286 case VPHADDWDrr:
9287 return true;
9288 }
9289 return false;
9290}
9291
9292bool isVMOVHPD(unsigned Opcode) {
9293 switch (Opcode) {
9294 case VMOVHPDZ128mr:
9295 case VMOVHPDZ128rm:
9296 case VMOVHPDmr:
9297 case VMOVHPDrm:
9298 return true;
9299 }
9300 return false;
9301}
9302
9303bool isMOVHPD(unsigned Opcode) {
9304 switch (Opcode) {
9305 case MOVHPDmr:
9306 case MOVHPDrm:
9307 return true;
9308 }
9309 return false;
9310}
9311
9312bool isVDIVPH(unsigned Opcode) {
9313 switch (Opcode) {
9314 case VDIVPHZ128rm:
9315 case VDIVPHZ128rmb:
9316 case VDIVPHZ128rmbk:
9317 case VDIVPHZ128rmbkz:
9318 case VDIVPHZ128rmk:
9319 case VDIVPHZ128rmkz:
9320 case VDIVPHZ128rr:
9321 case VDIVPHZ128rrk:
9322 case VDIVPHZ128rrkz:
9323 case VDIVPHZ256rm:
9324 case VDIVPHZ256rmb:
9325 case VDIVPHZ256rmbk:
9326 case VDIVPHZ256rmbkz:
9327 case VDIVPHZ256rmk:
9328 case VDIVPHZ256rmkz:
9329 case VDIVPHZ256rr:
9330 case VDIVPHZ256rrk:
9331 case VDIVPHZ256rrkz:
9332 case VDIVPHZrm:
9333 case VDIVPHZrmb:
9334 case VDIVPHZrmbk:
9335 case VDIVPHZrmbkz:
9336 case VDIVPHZrmk:
9337 case VDIVPHZrmkz:
9338 case VDIVPHZrr:
9339 case VDIVPHZrrb:
9340 case VDIVPHZrrbk:
9341 case VDIVPHZrrbkz:
9342 case VDIVPHZrrk:
9343 case VDIVPHZrrkz:
9344 return true;
9345 }
9346 return false;
9347}
9348
9349bool isFFREE(unsigned Opcode) {
9350 return Opcode == FFREE;
9351}
9352
9353bool isVGATHERPF1DPS(unsigned Opcode) {
9354 return Opcode == VGATHERPF1DPSm;
9355}
9356
9357bool isVPCMPESTRIQ(unsigned Opcode) {
9358 switch (Opcode) {
9359 case VPCMPESTRIQrmi:
9360 case VPCMPESTRIQrri:
9361 return true;
9362 }
9363 return false;
9364}
9365
9366bool isVFNMADD231PD(unsigned Opcode) {
9367 switch (Opcode) {
9368 case VFNMADD231PDYm:
9369 case VFNMADD231PDYr:
9370 case VFNMADD231PDZ128m:
9371 case VFNMADD231PDZ128mb:
9372 case VFNMADD231PDZ128mbk:
9373 case VFNMADD231PDZ128mbkz:
9374 case VFNMADD231PDZ128mk:
9375 case VFNMADD231PDZ128mkz:
9376 case VFNMADD231PDZ128r:
9377 case VFNMADD231PDZ128rk:
9378 case VFNMADD231PDZ128rkz:
9379 case VFNMADD231PDZ256m:
9380 case VFNMADD231PDZ256mb:
9381 case VFNMADD231PDZ256mbk:
9382 case VFNMADD231PDZ256mbkz:
9383 case VFNMADD231PDZ256mk:
9384 case VFNMADD231PDZ256mkz:
9385 case VFNMADD231PDZ256r:
9386 case VFNMADD231PDZ256rk:
9387 case VFNMADD231PDZ256rkz:
9388 case VFNMADD231PDZm:
9389 case VFNMADD231PDZmb:
9390 case VFNMADD231PDZmbk:
9391 case VFNMADD231PDZmbkz:
9392 case VFNMADD231PDZmk:
9393 case VFNMADD231PDZmkz:
9394 case VFNMADD231PDZr:
9395 case VFNMADD231PDZrb:
9396 case VFNMADD231PDZrbk:
9397 case VFNMADD231PDZrbkz:
9398 case VFNMADD231PDZrk:
9399 case VFNMADD231PDZrkz:
9400 case VFNMADD231PDm:
9401 case VFNMADD231PDr:
9402 return true;
9403 }
9404 return false;
9405}
9406
9407bool isVFCMULCPH(unsigned Opcode) {
9408 switch (Opcode) {
9409 case VFCMULCPHZ128rm:
9410 case VFCMULCPHZ128rmb:
9411 case VFCMULCPHZ128rmbk:
9412 case VFCMULCPHZ128rmbkz:
9413 case VFCMULCPHZ128rmk:
9414 case VFCMULCPHZ128rmkz:
9415 case VFCMULCPHZ128rr:
9416 case VFCMULCPHZ128rrk:
9417 case VFCMULCPHZ128rrkz:
9418 case VFCMULCPHZ256rm:
9419 case VFCMULCPHZ256rmb:
9420 case VFCMULCPHZ256rmbk:
9421 case VFCMULCPHZ256rmbkz:
9422 case VFCMULCPHZ256rmk:
9423 case VFCMULCPHZ256rmkz:
9424 case VFCMULCPHZ256rr:
9425 case VFCMULCPHZ256rrk:
9426 case VFCMULCPHZ256rrkz:
9427 case VFCMULCPHZrm:
9428 case VFCMULCPHZrmb:
9429 case VFCMULCPHZrmbk:
9430 case VFCMULCPHZrmbkz:
9431 case VFCMULCPHZrmk:
9432 case VFCMULCPHZrmkz:
9433 case VFCMULCPHZrr:
9434 case VFCMULCPHZrrb:
9435 case VFCMULCPHZrrbk:
9436 case VFCMULCPHZrrbkz:
9437 case VFCMULCPHZrrk:
9438 case VFCMULCPHZrrkz:
9439 return true;
9440 }
9441 return false;
9442}
9443
9444bool isVPADDD(unsigned Opcode) {
9445 switch (Opcode) {
9446 case VPADDDYrm:
9447 case VPADDDYrr:
9448 case VPADDDZ128rm:
9449 case VPADDDZ128rmb:
9450 case VPADDDZ128rmbk:
9451 case VPADDDZ128rmbkz:
9452 case VPADDDZ128rmk:
9453 case VPADDDZ128rmkz:
9454 case VPADDDZ128rr:
9455 case VPADDDZ128rrk:
9456 case VPADDDZ128rrkz:
9457 case VPADDDZ256rm:
9458 case VPADDDZ256rmb:
9459 case VPADDDZ256rmbk:
9460 case VPADDDZ256rmbkz:
9461 case VPADDDZ256rmk:
9462 case VPADDDZ256rmkz:
9463 case VPADDDZ256rr:
9464 case VPADDDZ256rrk:
9465 case VPADDDZ256rrkz:
9466 case VPADDDZrm:
9467 case VPADDDZrmb:
9468 case VPADDDZrmbk:
9469 case VPADDDZrmbkz:
9470 case VPADDDZrmk:
9471 case VPADDDZrmkz:
9472 case VPADDDZrr:
9473 case VPADDDZrrk:
9474 case VPADDDZrrkz:
9475 case VPADDDrm:
9476 case VPADDDrr:
9477 return true;
9478 }
9479 return false;
9480}
9481
9482bool isVPCOMUQ(unsigned Opcode) {
9483 switch (Opcode) {
9484 case VPCOMUQmi:
9485 case VPCOMUQri:
9486 return true;
9487 }
9488 return false;
9489}
9490
9491bool isVSM3MSG2(unsigned Opcode) {
9492 switch (Opcode) {
9493 case VSM3MSG2rm:
9494 case VSM3MSG2rr:
9495 return true;
9496 }
9497 return false;
9498}
9499
9500bool isVERR(unsigned Opcode) {
9501 switch (Opcode) {
9502 case VERRm:
9503 case VERRr:
9504 return true;
9505 }
9506 return false;
9507}
9508
9509bool isKORTESTQ(unsigned Opcode) {
9510 return Opcode == KORTESTQkk;
9511}
9512
9513bool isVFMSUB132SD(unsigned Opcode) {
9514 switch (Opcode) {
9515 case VFMSUB132SDZm_Int:
9516 case VFMSUB132SDZmk_Int:
9517 case VFMSUB132SDZmkz_Int:
9518 case VFMSUB132SDZr_Int:
9519 case VFMSUB132SDZrb_Int:
9520 case VFMSUB132SDZrbk_Int:
9521 case VFMSUB132SDZrbkz_Int:
9522 case VFMSUB132SDZrk_Int:
9523 case VFMSUB132SDZrkz_Int:
9524 case VFMSUB132SDm_Int:
9525 case VFMSUB132SDr_Int:
9526 return true;
9527 }
9528 return false;
9529}
9530
9531bool isTILEZERO(unsigned Opcode) {
9532 return Opcode == TILEZERO;
9533}
9534
9535bool isPFADD(unsigned Opcode) {
9536 switch (Opcode) {
9537 case PFADDrm:
9538 case PFADDrr:
9539 return true;
9540 }
9541 return false;
9542}
9543
9544bool isVCVTSI2SD(unsigned Opcode) {
9545 switch (Opcode) {
9546 case VCVTSI2SDZrm_Int:
9547 case VCVTSI2SDZrr_Int:
9548 case VCVTSI2SDrm_Int:
9549 case VCVTSI2SDrr_Int:
9550 case VCVTSI642SDZrm_Int:
9551 case VCVTSI642SDZrr_Int:
9552 case VCVTSI642SDZrrb_Int:
9553 case VCVTSI642SDrm_Int:
9554 case VCVTSI642SDrr_Int:
9555 return true;
9556 }
9557 return false;
9558}
9559
9560bool isTILELOADDRS(unsigned Opcode) {
9561 switch (Opcode) {
9562 case TILELOADDRS:
9563 case TILELOADDRS_EVEX:
9564 return true;
9565 }
9566 return false;
9567}
9568
9569bool isVSTMXCSR(unsigned Opcode) {
9570 return Opcode == VSTMXCSR;
9571}
9572
9573bool isVCVTTSH2SI(unsigned Opcode) {
9574 switch (Opcode) {
9575 case VCVTTSH2SI64Zrm_Int:
9576 case VCVTTSH2SI64Zrr_Int:
9577 case VCVTTSH2SI64Zrrb_Int:
9578 case VCVTTSH2SIZrm_Int:
9579 case VCVTTSH2SIZrr_Int:
9580 case VCVTTSH2SIZrrb_Int:
9581 return true;
9582 }
9583 return false;
9584}
9585
9586bool isRET(unsigned Opcode) {
9587 switch (Opcode) {
9588 case RET16:
9589 case RET32:
9590 case RET64:
9591 case RETI16:
9592 case RETI32:
9593 case RETI64:
9594 return true;
9595 }
9596 return false;
9597}
9598
9599bool isLZCNT(unsigned Opcode) {
9600 switch (Opcode) {
9601 case LZCNT16rm:
9602 case LZCNT16rm_EVEX:
9603 case LZCNT16rm_NF:
9604 case LZCNT16rr:
9605 case LZCNT16rr_EVEX:
9606 case LZCNT16rr_NF:
9607 case LZCNT32rm:
9608 case LZCNT32rm_EVEX:
9609 case LZCNT32rm_NF:
9610 case LZCNT32rr:
9611 case LZCNT32rr_EVEX:
9612 case LZCNT32rr_NF:
9613 case LZCNT64rm:
9614 case LZCNT64rm_EVEX:
9615 case LZCNT64rm_NF:
9616 case LZCNT64rr:
9617 case LZCNT64rr_EVEX:
9618 case LZCNT64rr_NF:
9619 return true;
9620 }
9621 return false;
9622}
9623
9624bool isMULPD(unsigned Opcode) {
9625 switch (Opcode) {
9626 case MULPDrm:
9627 case MULPDrr:
9628 return true;
9629 }
9630 return false;
9631}
9632
9633bool isVBROADCASTI32X2(unsigned Opcode) {
9634 switch (Opcode) {
9635 case VBROADCASTI32X2Z128rm:
9636 case VBROADCASTI32X2Z128rmk:
9637 case VBROADCASTI32X2Z128rmkz:
9638 case VBROADCASTI32X2Z128rr:
9639 case VBROADCASTI32X2Z128rrk:
9640 case VBROADCASTI32X2Z128rrkz:
9641 case VBROADCASTI32X2Z256rm:
9642 case VBROADCASTI32X2Z256rmk:
9643 case VBROADCASTI32X2Z256rmkz:
9644 case VBROADCASTI32X2Z256rr:
9645 case VBROADCASTI32X2Z256rrk:
9646 case VBROADCASTI32X2Z256rrkz:
9647 case VBROADCASTI32X2Zrm:
9648 case VBROADCASTI32X2Zrmk:
9649 case VBROADCASTI32X2Zrmkz:
9650 case VBROADCASTI32X2Zrr:
9651 case VBROADCASTI32X2Zrrk:
9652 case VBROADCASTI32X2Zrrkz:
9653 return true;
9654 }
9655 return false;
9656}
9657
9658bool isVCVTPH2W(unsigned Opcode) {
9659 switch (Opcode) {
9660 case VCVTPH2WZ128rm:
9661 case VCVTPH2WZ128rmb:
9662 case VCVTPH2WZ128rmbk:
9663 case VCVTPH2WZ128rmbkz:
9664 case VCVTPH2WZ128rmk:
9665 case VCVTPH2WZ128rmkz:
9666 case VCVTPH2WZ128rr:
9667 case VCVTPH2WZ128rrk:
9668 case VCVTPH2WZ128rrkz:
9669 case VCVTPH2WZ256rm:
9670 case VCVTPH2WZ256rmb:
9671 case VCVTPH2WZ256rmbk:
9672 case VCVTPH2WZ256rmbkz:
9673 case VCVTPH2WZ256rmk:
9674 case VCVTPH2WZ256rmkz:
9675 case VCVTPH2WZ256rr:
9676 case VCVTPH2WZ256rrk:
9677 case VCVTPH2WZ256rrkz:
9678 case VCVTPH2WZrm:
9679 case VCVTPH2WZrmb:
9680 case VCVTPH2WZrmbk:
9681 case VCVTPH2WZrmbkz:
9682 case VCVTPH2WZrmk:
9683 case VCVTPH2WZrmkz:
9684 case VCVTPH2WZrr:
9685 case VCVTPH2WZrrb:
9686 case VCVTPH2WZrrbk:
9687 case VCVTPH2WZrrbkz:
9688 case VCVTPH2WZrrk:
9689 case VCVTPH2WZrrkz:
9690 return true;
9691 }
9692 return false;
9693}
9694
9695bool isCQO(unsigned Opcode) {
9696 return Opcode == CQO;
9697}
9698
9699bool isFSUBR(unsigned Opcode) {
9700 switch (Opcode) {
9701 case SUBR_F32m:
9702 case SUBR_F64m:
9703 case SUBR_FST0r:
9704 case SUBR_FrST0:
9705 return true;
9706 }
9707 return false;
9708}
9709
9710bool isDPPD(unsigned Opcode) {
9711 switch (Opcode) {
9712 case DPPDrmi:
9713 case DPPDrri:
9714 return true;
9715 }
9716 return false;
9717}
9718
9719bool isFCOS(unsigned Opcode) {
9720 return Opcode == FCOS;
9721}
9722
9723bool isXSAVES(unsigned Opcode) {
9724 return Opcode == XSAVES;
9725}
9726
9727bool isTZCNT(unsigned Opcode) {
9728 switch (Opcode) {
9729 case TZCNT16rm:
9730 case TZCNT16rm_EVEX:
9731 case TZCNT16rm_NF:
9732 case TZCNT16rr:
9733 case TZCNT16rr_EVEX:
9734 case TZCNT16rr_NF:
9735 case TZCNT32rm:
9736 case TZCNT32rm_EVEX:
9737 case TZCNT32rm_NF:
9738 case TZCNT32rr:
9739 case TZCNT32rr_EVEX:
9740 case TZCNT32rr_NF:
9741 case TZCNT64rm:
9742 case TZCNT64rm_EVEX:
9743 case TZCNT64rm_NF:
9744 case TZCNT64rr:
9745 case TZCNT64rr_EVEX:
9746 case TZCNT64rr_NF:
9747 return true;
9748 }
9749 return false;
9750}
9751
9752bool isLJMP(unsigned Opcode) {
9753 switch (Opcode) {
9754 case FARJMP16i:
9755 case FARJMP16m:
9756 case FARJMP32i:
9757 case FARJMP64m:
9758 return true;
9759 }
9760 return false;
9761}
9762
9763bool isCMOVCC(unsigned Opcode) {
9764 switch (Opcode) {
9765 case CMOV16rm:
9766 case CMOV16rm_ND:
9767 case CMOV16rr:
9768 case CMOV16rr_ND:
9769 case CMOV32rm:
9770 case CMOV32rm_ND:
9771 case CMOV32rr:
9772 case CMOV32rr_ND:
9773 case CMOV64rm:
9774 case CMOV64rm_ND:
9775 case CMOV64rr:
9776 case CMOV64rr_ND:
9777 return true;
9778 }
9779 return false;
9780}
9781
9782bool isVCVTBIASPH2HF8(unsigned Opcode) {
9783 switch (Opcode) {
9784 case VCVTBIASPH2HF8Z128rm:
9785 case VCVTBIASPH2HF8Z128rmb:
9786 case VCVTBIASPH2HF8Z128rmbk:
9787 case VCVTBIASPH2HF8Z128rmbkz:
9788 case VCVTBIASPH2HF8Z128rmk:
9789 case VCVTBIASPH2HF8Z128rmkz:
9790 case VCVTBIASPH2HF8Z128rr:
9791 case VCVTBIASPH2HF8Z128rrk:
9792 case VCVTBIASPH2HF8Z128rrkz:
9793 case VCVTBIASPH2HF8Z256rm:
9794 case VCVTBIASPH2HF8Z256rmb:
9795 case VCVTBIASPH2HF8Z256rmbk:
9796 case VCVTBIASPH2HF8Z256rmbkz:
9797 case VCVTBIASPH2HF8Z256rmk:
9798 case VCVTBIASPH2HF8Z256rmkz:
9799 case VCVTBIASPH2HF8Z256rr:
9800 case VCVTBIASPH2HF8Z256rrk:
9801 case VCVTBIASPH2HF8Z256rrkz:
9802 case VCVTBIASPH2HF8Zrm:
9803 case VCVTBIASPH2HF8Zrmb:
9804 case VCVTBIASPH2HF8Zrmbk:
9805 case VCVTBIASPH2HF8Zrmbkz:
9806 case VCVTBIASPH2HF8Zrmk:
9807 case VCVTBIASPH2HF8Zrmkz:
9808 case VCVTBIASPH2HF8Zrr:
9809 case VCVTBIASPH2HF8Zrrk:
9810 case VCVTBIASPH2HF8Zrrkz:
9811 return true;
9812 }
9813 return false;
9814}
9815
9816bool isINVEPT(unsigned Opcode) {
9817 switch (Opcode) {
9818 case INVEPT32:
9819 case INVEPT64:
9820 case INVEPT64_EVEX:
9821 return true;
9822 }
9823 return false;
9824}
9825
9826bool isADDSUBPD(unsigned Opcode) {
9827 switch (Opcode) {
9828 case ADDSUBPDrm:
9829 case ADDSUBPDrr:
9830 return true;
9831 }
9832 return false;
9833}
9834
9835bool isVCVTSS2SD(unsigned Opcode) {
9836 switch (Opcode) {
9837 case VCVTSS2SDZrm_Int:
9838 case VCVTSS2SDZrmk_Int:
9839 case VCVTSS2SDZrmkz_Int:
9840 case VCVTSS2SDZrr_Int:
9841 case VCVTSS2SDZrrb_Int:
9842 case VCVTSS2SDZrrbk_Int:
9843 case VCVTSS2SDZrrbkz_Int:
9844 case VCVTSS2SDZrrk_Int:
9845 case VCVTSS2SDZrrkz_Int:
9846 case VCVTSS2SDrm_Int:
9847 case VCVTSS2SDrr_Int:
9848 return true;
9849 }
9850 return false;
9851}
9852
9853bool isVMOVSHDUP(unsigned Opcode) {
9854 switch (Opcode) {
9855 case VMOVSHDUPYrm:
9856 case VMOVSHDUPYrr:
9857 case VMOVSHDUPZ128rm:
9858 case VMOVSHDUPZ128rmk:
9859 case VMOVSHDUPZ128rmkz:
9860 case VMOVSHDUPZ128rr:
9861 case VMOVSHDUPZ128rrk:
9862 case VMOVSHDUPZ128rrkz:
9863 case VMOVSHDUPZ256rm:
9864 case VMOVSHDUPZ256rmk:
9865 case VMOVSHDUPZ256rmkz:
9866 case VMOVSHDUPZ256rr:
9867 case VMOVSHDUPZ256rrk:
9868 case VMOVSHDUPZ256rrkz:
9869 case VMOVSHDUPZrm:
9870 case VMOVSHDUPZrmk:
9871 case VMOVSHDUPZrmkz:
9872 case VMOVSHDUPZrr:
9873 case VMOVSHDUPZrrk:
9874 case VMOVSHDUPZrrkz:
9875 case VMOVSHDUPrm:
9876 case VMOVSHDUPrr:
9877 return true;
9878 }
9879 return false;
9880}
9881
9882bool isKSHIFTRD(unsigned Opcode) {
9883 return Opcode == KSHIFTRDki;
9884}
9885
9886bool isVPTERNLOGD(unsigned Opcode) {
9887 switch (Opcode) {
9888 case VPTERNLOGDZ128rmbi:
9889 case VPTERNLOGDZ128rmbik:
9890 case VPTERNLOGDZ128rmbikz:
9891 case VPTERNLOGDZ128rmi:
9892 case VPTERNLOGDZ128rmik:
9893 case VPTERNLOGDZ128rmikz:
9894 case VPTERNLOGDZ128rri:
9895 case VPTERNLOGDZ128rrik:
9896 case VPTERNLOGDZ128rrikz:
9897 case VPTERNLOGDZ256rmbi:
9898 case VPTERNLOGDZ256rmbik:
9899 case VPTERNLOGDZ256rmbikz:
9900 case VPTERNLOGDZ256rmi:
9901 case VPTERNLOGDZ256rmik:
9902 case VPTERNLOGDZ256rmikz:
9903 case VPTERNLOGDZ256rri:
9904 case VPTERNLOGDZ256rrik:
9905 case VPTERNLOGDZ256rrikz:
9906 case VPTERNLOGDZrmbi:
9907 case VPTERNLOGDZrmbik:
9908 case VPTERNLOGDZrmbikz:
9909 case VPTERNLOGDZrmi:
9910 case VPTERNLOGDZrmik:
9911 case VPTERNLOGDZrmikz:
9912 case VPTERNLOGDZrri:
9913 case VPTERNLOGDZrrik:
9914 case VPTERNLOGDZrrikz:
9915 return true;
9916 }
9917 return false;
9918}
9919
9920bool isPADDQ(unsigned Opcode) {
9921 switch (Opcode) {
9922 case MMX_PADDQrm:
9923 case MMX_PADDQrr:
9924 case PADDQrm:
9925 case PADDQrr:
9926 return true;
9927 }
9928 return false;
9929}
9930
9931bool isVEXTRACTI64X4(unsigned Opcode) {
9932 switch (Opcode) {
9933 case VEXTRACTI64X4Zmri:
9934 case VEXTRACTI64X4Zmrik:
9935 case VEXTRACTI64X4Zrri:
9936 case VEXTRACTI64X4Zrrik:
9937 case VEXTRACTI64X4Zrrikz:
9938 return true;
9939 }
9940 return false;
9941}
9942
9943bool isVFMSUB231SS(unsigned Opcode) {
9944 switch (Opcode) {
9945 case VFMSUB231SSZm_Int:
9946 case VFMSUB231SSZmk_Int:
9947 case VFMSUB231SSZmkz_Int:
9948 case VFMSUB231SSZr_Int:
9949 case VFMSUB231SSZrb_Int:
9950 case VFMSUB231SSZrbk_Int:
9951 case VFMSUB231SSZrbkz_Int:
9952 case VFMSUB231SSZrk_Int:
9953 case VFMSUB231SSZrkz_Int:
9954 case VFMSUB231SSm_Int:
9955 case VFMSUB231SSr_Int:
9956 return true;
9957 }
9958 return false;
9959}
9960
9961bool isVPCMPEQB(unsigned Opcode) {
9962 switch (Opcode) {
9963 case VPCMPEQBYrm:
9964 case VPCMPEQBYrr:
9965 case VPCMPEQBZ128rm:
9966 case VPCMPEQBZ128rmk:
9967 case VPCMPEQBZ128rr:
9968 case VPCMPEQBZ128rrk:
9969 case VPCMPEQBZ256rm:
9970 case VPCMPEQBZ256rmk:
9971 case VPCMPEQBZ256rr:
9972 case VPCMPEQBZ256rrk:
9973 case VPCMPEQBZrm:
9974 case VPCMPEQBZrmk:
9975 case VPCMPEQBZrr:
9976 case VPCMPEQBZrrk:
9977 case VPCMPEQBrm:
9978 case VPCMPEQBrr:
9979 return true;
9980 }
9981 return false;
9982}
9983
9984bool isLEA(unsigned Opcode) {
9985 switch (Opcode) {
9986 case LEA16r:
9987 case LEA32r:
9988 case LEA64_32r:
9989 case LEA64r:
9990 return true;
9991 }
9992 return false;
9993}
9994
9995bool isPSUBB(unsigned Opcode) {
9996 switch (Opcode) {
9997 case MMX_PSUBBrm:
9998 case MMX_PSUBBrr:
9999 case PSUBBrm:
10000 case PSUBBrr:
10001 return true;
10002 }
10003 return false;
10004}
10005
10006bool isKADDQ(unsigned Opcode) {
10007 return Opcode == KADDQkk;
10008}
10009
10010bool isMOVSX(unsigned Opcode) {
10011 switch (Opcode) {
10012 case MOVSX16rm16:
10013 case MOVSX16rm8:
10014 case MOVSX16rr16:
10015 case MOVSX16rr8:
10016 case MOVSX32rm16:
10017 case MOVSX32rm8:
10018 case MOVSX32rr16:
10019 case MOVSX32rr8:
10020 case MOVSX64rm16:
10021 case MOVSX64rm8:
10022 case MOVSX64rr16:
10023 case MOVSX64rr8:
10024 return true;
10025 }
10026 return false;
10027}
10028
10029bool isVALIGNQ(unsigned Opcode) {
10030 switch (Opcode) {
10031 case VALIGNQZ128rmbi:
10032 case VALIGNQZ128rmbik:
10033 case VALIGNQZ128rmbikz:
10034 case VALIGNQZ128rmi:
10035 case VALIGNQZ128rmik:
10036 case VALIGNQZ128rmikz:
10037 case VALIGNQZ128rri:
10038 case VALIGNQZ128rrik:
10039 case VALIGNQZ128rrikz:
10040 case VALIGNQZ256rmbi:
10041 case VALIGNQZ256rmbik:
10042 case VALIGNQZ256rmbikz:
10043 case VALIGNQZ256rmi:
10044 case VALIGNQZ256rmik:
10045 case VALIGNQZ256rmikz:
10046 case VALIGNQZ256rri:
10047 case VALIGNQZ256rrik:
10048 case VALIGNQZ256rrikz:
10049 case VALIGNQZrmbi:
10050 case VALIGNQZrmbik:
10051 case VALIGNQZrmbikz:
10052 case VALIGNQZrmi:
10053 case VALIGNQZrmik:
10054 case VALIGNQZrmikz:
10055 case VALIGNQZrri:
10056 case VALIGNQZrrik:
10057 case VALIGNQZrrikz:
10058 return true;
10059 }
10060 return false;
10061}
10062
10063bool isVCVTNE2PS2BF16(unsigned Opcode) {
10064 switch (Opcode) {
10065 case VCVTNE2PS2BF16Z128rm:
10066 case VCVTNE2PS2BF16Z128rmb:
10067 case VCVTNE2PS2BF16Z128rmbk:
10068 case VCVTNE2PS2BF16Z128rmbkz:
10069 case VCVTNE2PS2BF16Z128rmk:
10070 case VCVTNE2PS2BF16Z128rmkz:
10071 case VCVTNE2PS2BF16Z128rr:
10072 case VCVTNE2PS2BF16Z128rrk:
10073 case VCVTNE2PS2BF16Z128rrkz:
10074 case VCVTNE2PS2BF16Z256rm:
10075 case VCVTNE2PS2BF16Z256rmb:
10076 case VCVTNE2PS2BF16Z256rmbk:
10077 case VCVTNE2PS2BF16Z256rmbkz:
10078 case VCVTNE2PS2BF16Z256rmk:
10079 case VCVTNE2PS2BF16Z256rmkz:
10080 case VCVTNE2PS2BF16Z256rr:
10081 case VCVTNE2PS2BF16Z256rrk:
10082 case VCVTNE2PS2BF16Z256rrkz:
10083 case VCVTNE2PS2BF16Zrm:
10084 case VCVTNE2PS2BF16Zrmb:
10085 case VCVTNE2PS2BF16Zrmbk:
10086 case VCVTNE2PS2BF16Zrmbkz:
10087 case VCVTNE2PS2BF16Zrmk:
10088 case VCVTNE2PS2BF16Zrmkz:
10089 case VCVTNE2PS2BF16Zrr:
10090 case VCVTNE2PS2BF16Zrrk:
10091 case VCVTNE2PS2BF16Zrrkz:
10092 return true;
10093 }
10094 return false;
10095}
10096
10097bool isVPSRAW(unsigned Opcode) {
10098 switch (Opcode) {
10099 case VPSRAWYri:
10100 case VPSRAWYrm:
10101 case VPSRAWYrr:
10102 case VPSRAWZ128mi:
10103 case VPSRAWZ128mik:
10104 case VPSRAWZ128mikz:
10105 case VPSRAWZ128ri:
10106 case VPSRAWZ128rik:
10107 case VPSRAWZ128rikz:
10108 case VPSRAWZ128rm:
10109 case VPSRAWZ128rmk:
10110 case VPSRAWZ128rmkz:
10111 case VPSRAWZ128rr:
10112 case VPSRAWZ128rrk:
10113 case VPSRAWZ128rrkz:
10114 case VPSRAWZ256mi:
10115 case VPSRAWZ256mik:
10116 case VPSRAWZ256mikz:
10117 case VPSRAWZ256ri:
10118 case VPSRAWZ256rik:
10119 case VPSRAWZ256rikz:
10120 case VPSRAWZ256rm:
10121 case VPSRAWZ256rmk:
10122 case VPSRAWZ256rmkz:
10123 case VPSRAWZ256rr:
10124 case VPSRAWZ256rrk:
10125 case VPSRAWZ256rrkz:
10126 case VPSRAWZmi:
10127 case VPSRAWZmik:
10128 case VPSRAWZmikz:
10129 case VPSRAWZri:
10130 case VPSRAWZrik:
10131 case VPSRAWZrikz:
10132 case VPSRAWZrm:
10133 case VPSRAWZrmk:
10134 case VPSRAWZrmkz:
10135 case VPSRAWZrr:
10136 case VPSRAWZrrk:
10137 case VPSRAWZrrkz:
10138 case VPSRAWri:
10139 case VPSRAWrm:
10140 case VPSRAWrr:
10141 return true;
10142 }
10143 return false;
10144}
10145
10146bool isVFMSUBADD231PH(unsigned Opcode) {
10147 switch (Opcode) {
10148 case VFMSUBADD231PHZ128m:
10149 case VFMSUBADD231PHZ128mb:
10150 case VFMSUBADD231PHZ128mbk:
10151 case VFMSUBADD231PHZ128mbkz:
10152 case VFMSUBADD231PHZ128mk:
10153 case VFMSUBADD231PHZ128mkz:
10154 case VFMSUBADD231PHZ128r:
10155 case VFMSUBADD231PHZ128rk:
10156 case VFMSUBADD231PHZ128rkz:
10157 case VFMSUBADD231PHZ256m:
10158 case VFMSUBADD231PHZ256mb:
10159 case VFMSUBADD231PHZ256mbk:
10160 case VFMSUBADD231PHZ256mbkz:
10161 case VFMSUBADD231PHZ256mk:
10162 case VFMSUBADD231PHZ256mkz:
10163 case VFMSUBADD231PHZ256r:
10164 case VFMSUBADD231PHZ256rk:
10165 case VFMSUBADD231PHZ256rkz:
10166 case VFMSUBADD231PHZm:
10167 case VFMSUBADD231PHZmb:
10168 case VFMSUBADD231PHZmbk:
10169 case VFMSUBADD231PHZmbkz:
10170 case VFMSUBADD231PHZmk:
10171 case VFMSUBADD231PHZmkz:
10172 case VFMSUBADD231PHZr:
10173 case VFMSUBADD231PHZrb:
10174 case VFMSUBADD231PHZrbk:
10175 case VFMSUBADD231PHZrbkz:
10176 case VFMSUBADD231PHZrk:
10177 case VFMSUBADD231PHZrkz:
10178 return true;
10179 }
10180 return false;
10181}
10182
10183bool isCVTDQ2PS(unsigned Opcode) {
10184 switch (Opcode) {
10185 case CVTDQ2PSrm:
10186 case CVTDQ2PSrr:
10187 return true;
10188 }
10189 return false;
10190}
10191
10192bool isFBLD(unsigned Opcode) {
10193 return Opcode == FBLDm;
10194}
10195
10196bool isLMSW(unsigned Opcode) {
10197 switch (Opcode) {
10198 case LMSW16m:
10199 case LMSW16r:
10200 return true;
10201 }
10202 return false;
10203}
10204
10205bool isVRNDSCALEPH(unsigned Opcode) {
10206 switch (Opcode) {
10207 case VRNDSCALEPHZ128rmbi:
10208 case VRNDSCALEPHZ128rmbik:
10209 case VRNDSCALEPHZ128rmbikz:
10210 case VRNDSCALEPHZ128rmi:
10211 case VRNDSCALEPHZ128rmik:
10212 case VRNDSCALEPHZ128rmikz:
10213 case VRNDSCALEPHZ128rri:
10214 case VRNDSCALEPHZ128rrik:
10215 case VRNDSCALEPHZ128rrikz:
10216 case VRNDSCALEPHZ256rmbi:
10217 case VRNDSCALEPHZ256rmbik:
10218 case VRNDSCALEPHZ256rmbikz:
10219 case VRNDSCALEPHZ256rmi:
10220 case VRNDSCALEPHZ256rmik:
10221 case VRNDSCALEPHZ256rmikz:
10222 case VRNDSCALEPHZ256rri:
10223 case VRNDSCALEPHZ256rrik:
10224 case VRNDSCALEPHZ256rrikz:
10225 case VRNDSCALEPHZrmbi:
10226 case VRNDSCALEPHZrmbik:
10227 case VRNDSCALEPHZrmbikz:
10228 case VRNDSCALEPHZrmi:
10229 case VRNDSCALEPHZrmik:
10230 case VRNDSCALEPHZrmikz:
10231 case VRNDSCALEPHZrri:
10232 case VRNDSCALEPHZrrib:
10233 case VRNDSCALEPHZrribk:
10234 case VRNDSCALEPHZrribkz:
10235 case VRNDSCALEPHZrrik:
10236 case VRNDSCALEPHZrrikz:
10237 return true;
10238 }
10239 return false;
10240}
10241
10242bool isMINSS(unsigned Opcode) {
10243 switch (Opcode) {
10244 case MINSSrm_Int:
10245 case MINSSrr_Int:
10246 return true;
10247 }
10248 return false;
10249}
10250
10251bool isWRMSR(unsigned Opcode) {
10252 return Opcode == WRMSR;
10253}
10254
10255bool isFSCALE(unsigned Opcode) {
10256 return Opcode == FSCALE;
10257}
10258
10259bool isVFNMADD213SH(unsigned Opcode) {
10260 switch (Opcode) {
10261 case VFNMADD213SHZm_Int:
10262 case VFNMADD213SHZmk_Int:
10263 case VFNMADD213SHZmkz_Int:
10264 case VFNMADD213SHZr_Int:
10265 case VFNMADD213SHZrb_Int:
10266 case VFNMADD213SHZrbk_Int:
10267 case VFNMADD213SHZrbkz_Int:
10268 case VFNMADD213SHZrk_Int:
10269 case VFNMADD213SHZrkz_Int:
10270 return true;
10271 }
10272 return false;
10273}
10274
10275bool isIMULZU(unsigned Opcode) {
10276 switch (Opcode) {
10277 case IMULZU16rmi:
10278 case IMULZU16rmi8:
10279 case IMULZU16rri:
10280 case IMULZU16rri8:
10281 case IMULZU32rmi:
10282 case IMULZU32rmi8:
10283 case IMULZU32rri:
10284 case IMULZU32rri8:
10285 case IMULZU64rmi32:
10286 case IMULZU64rmi8:
10287 case IMULZU64rri32:
10288 case IMULZU64rri8:
10289 return true;
10290 }
10291 return false;
10292}
10293
10294bool isVPHADDUBD(unsigned Opcode) {
10295 switch (Opcode) {
10296 case VPHADDUBDrm:
10297 case VPHADDUBDrr:
10298 return true;
10299 }
10300 return false;
10301}
10302
10303bool isRDSSPQ(unsigned Opcode) {
10304 return Opcode == RDSSPQ;
10305}
10306
10307bool isVCVTBF162IBS(unsigned Opcode) {
10308 switch (Opcode) {
10309 case VCVTBF162IBSZ128rm:
10310 case VCVTBF162IBSZ128rmb:
10311 case VCVTBF162IBSZ128rmbk:
10312 case VCVTBF162IBSZ128rmbkz:
10313 case VCVTBF162IBSZ128rmk:
10314 case VCVTBF162IBSZ128rmkz:
10315 case VCVTBF162IBSZ128rr:
10316 case VCVTBF162IBSZ128rrk:
10317 case VCVTBF162IBSZ128rrkz:
10318 case VCVTBF162IBSZ256rm:
10319 case VCVTBF162IBSZ256rmb:
10320 case VCVTBF162IBSZ256rmbk:
10321 case VCVTBF162IBSZ256rmbkz:
10322 case VCVTBF162IBSZ256rmk:
10323 case VCVTBF162IBSZ256rmkz:
10324 case VCVTBF162IBSZ256rr:
10325 case VCVTBF162IBSZ256rrk:
10326 case VCVTBF162IBSZ256rrkz:
10327 case VCVTBF162IBSZrm:
10328 case VCVTBF162IBSZrmb:
10329 case VCVTBF162IBSZrmbk:
10330 case VCVTBF162IBSZrmbkz:
10331 case VCVTBF162IBSZrmk:
10332 case VCVTBF162IBSZrmkz:
10333 case VCVTBF162IBSZrr:
10334 case VCVTBF162IBSZrrk:
10335 case VCVTBF162IBSZrrkz:
10336 return true;
10337 }
10338 return false;
10339}
10340
10341bool isLGDT(unsigned Opcode) {
10342 return Opcode == LGDT64m;
10343}
10344
10345bool isVPSHLDVD(unsigned Opcode) {
10346 switch (Opcode) {
10347 case VPSHLDVDZ128m:
10348 case VPSHLDVDZ128mb:
10349 case VPSHLDVDZ128mbk:
10350 case VPSHLDVDZ128mbkz:
10351 case VPSHLDVDZ128mk:
10352 case VPSHLDVDZ128mkz:
10353 case VPSHLDVDZ128r:
10354 case VPSHLDVDZ128rk:
10355 case VPSHLDVDZ128rkz:
10356 case VPSHLDVDZ256m:
10357 case VPSHLDVDZ256mb:
10358 case VPSHLDVDZ256mbk:
10359 case VPSHLDVDZ256mbkz:
10360 case VPSHLDVDZ256mk:
10361 case VPSHLDVDZ256mkz:
10362 case VPSHLDVDZ256r:
10363 case VPSHLDVDZ256rk:
10364 case VPSHLDVDZ256rkz:
10365 case VPSHLDVDZm:
10366 case VPSHLDVDZmb:
10367 case VPSHLDVDZmbk:
10368 case VPSHLDVDZmbkz:
10369 case VPSHLDVDZmk:
10370 case VPSHLDVDZmkz:
10371 case VPSHLDVDZr:
10372 case VPSHLDVDZrk:
10373 case VPSHLDVDZrkz:
10374 return true;
10375 }
10376 return false;
10377}
10378
10379bool isPFCMPGT(unsigned Opcode) {
10380 switch (Opcode) {
10381 case PFCMPGTrm:
10382 case PFCMPGTrr:
10383 return true;
10384 }
10385 return false;
10386}
10387
10388bool isJCXZ(unsigned Opcode) {
10389 return Opcode == JCXZ;
10390}
10391
10392bool isVPMOVZXBW(unsigned Opcode) {
10393 switch (Opcode) {
10394 case VPMOVZXBWYrm:
10395 case VPMOVZXBWYrr:
10396 case VPMOVZXBWZ128rm:
10397 case VPMOVZXBWZ128rmk:
10398 case VPMOVZXBWZ128rmkz:
10399 case VPMOVZXBWZ128rr:
10400 case VPMOVZXBWZ128rrk:
10401 case VPMOVZXBWZ128rrkz:
10402 case VPMOVZXBWZ256rm:
10403 case VPMOVZXBWZ256rmk:
10404 case VPMOVZXBWZ256rmkz:
10405 case VPMOVZXBWZ256rr:
10406 case VPMOVZXBWZ256rrk:
10407 case VPMOVZXBWZ256rrkz:
10408 case VPMOVZXBWZrm:
10409 case VPMOVZXBWZrmk:
10410 case VPMOVZXBWZrmkz:
10411 case VPMOVZXBWZrr:
10412 case VPMOVZXBWZrrk:
10413 case VPMOVZXBWZrrkz:
10414 case VPMOVZXBWrm:
10415 case VPMOVZXBWrr:
10416 return true;
10417 }
10418 return false;
10419}
10420
10421bool isVFMADDSUB231PD(unsigned Opcode) {
10422 switch (Opcode) {
10423 case VFMADDSUB231PDYm:
10424 case VFMADDSUB231PDYr:
10425 case VFMADDSUB231PDZ128m:
10426 case VFMADDSUB231PDZ128mb:
10427 case VFMADDSUB231PDZ128mbk:
10428 case VFMADDSUB231PDZ128mbkz:
10429 case VFMADDSUB231PDZ128mk:
10430 case VFMADDSUB231PDZ128mkz:
10431 case VFMADDSUB231PDZ128r:
10432 case VFMADDSUB231PDZ128rk:
10433 case VFMADDSUB231PDZ128rkz:
10434 case VFMADDSUB231PDZ256m:
10435 case VFMADDSUB231PDZ256mb:
10436 case VFMADDSUB231PDZ256mbk:
10437 case VFMADDSUB231PDZ256mbkz:
10438 case VFMADDSUB231PDZ256mk:
10439 case VFMADDSUB231PDZ256mkz:
10440 case VFMADDSUB231PDZ256r:
10441 case VFMADDSUB231PDZ256rk:
10442 case VFMADDSUB231PDZ256rkz:
10443 case VFMADDSUB231PDZm:
10444 case VFMADDSUB231PDZmb:
10445 case VFMADDSUB231PDZmbk:
10446 case VFMADDSUB231PDZmbkz:
10447 case VFMADDSUB231PDZmk:
10448 case VFMADDSUB231PDZmkz:
10449 case VFMADDSUB231PDZr:
10450 case VFMADDSUB231PDZrb:
10451 case VFMADDSUB231PDZrbk:
10452 case VFMADDSUB231PDZrbkz:
10453 case VFMADDSUB231PDZrk:
10454 case VFMADDSUB231PDZrkz:
10455 case VFMADDSUB231PDm:
10456 case VFMADDSUB231PDr:
10457 return true;
10458 }
10459 return false;
10460}
10461
10462bool isVBLENDMPD(unsigned Opcode) {
10463 switch (Opcode) {
10464 case VBLENDMPDZ128rm:
10465 case VBLENDMPDZ128rmb:
10466 case VBLENDMPDZ128rmbk:
10467 case VBLENDMPDZ128rmbkz:
10468 case VBLENDMPDZ128rmk:
10469 case VBLENDMPDZ128rmkz:
10470 case VBLENDMPDZ128rr:
10471 case VBLENDMPDZ128rrk:
10472 case VBLENDMPDZ128rrkz:
10473 case VBLENDMPDZ256rm:
10474 case VBLENDMPDZ256rmb:
10475 case VBLENDMPDZ256rmbk:
10476 case VBLENDMPDZ256rmbkz:
10477 case VBLENDMPDZ256rmk:
10478 case VBLENDMPDZ256rmkz:
10479 case VBLENDMPDZ256rr:
10480 case VBLENDMPDZ256rrk:
10481 case VBLENDMPDZ256rrkz:
10482 case VBLENDMPDZrm:
10483 case VBLENDMPDZrmb:
10484 case VBLENDMPDZrmbk:
10485 case VBLENDMPDZrmbkz:
10486 case VBLENDMPDZrmk:
10487 case VBLENDMPDZrmkz:
10488 case VBLENDMPDZrr:
10489 case VBLENDMPDZrrk:
10490 case VBLENDMPDZrrkz:
10491 return true;
10492 }
10493 return false;
10494}
10495
10496bool isHSUBPS(unsigned Opcode) {
10497 switch (Opcode) {
10498 case HSUBPSrm:
10499 case HSUBPSrr:
10500 return true;
10501 }
10502 return false;
10503}
10504
10505bool isPREFETCHIT0(unsigned Opcode) {
10506 return Opcode == PREFETCHIT0;
10507}
10508
10509bool isKTESTD(unsigned Opcode) {
10510 return Opcode == KTESTDkk;
10511}
10512
10513bool isVCVTNEOPH2PS(unsigned Opcode) {
10514 switch (Opcode) {
10515 case VCVTNEOPH2PSYrm:
10516 case VCVTNEOPH2PSrm:
10517 return true;
10518 }
10519 return false;
10520}
10521
10522bool isVBLENDVPD(unsigned Opcode) {
10523 switch (Opcode) {
10524 case VBLENDVPDYrmr:
10525 case VBLENDVPDYrrr:
10526 case VBLENDVPDrmr:
10527 case VBLENDVPDrrr:
10528 return true;
10529 }
10530 return false;
10531}
10532
10533bool isVCVTSS2USI(unsigned Opcode) {
10534 switch (Opcode) {
10535 case VCVTSS2USI64Zrm_Int:
10536 case VCVTSS2USI64Zrr_Int:
10537 case VCVTSS2USI64Zrrb_Int:
10538 case VCVTSS2USIZrm_Int:
10539 case VCVTSS2USIZrr_Int:
10540 case VCVTSS2USIZrrb_Int:
10541 return true;
10542 }
10543 return false;
10544}
10545
10546bool isVCVTTPS2DQS(unsigned Opcode) {
10547 switch (Opcode) {
10548 case VCVTTPS2DQSZ128rm:
10549 case VCVTTPS2DQSZ128rmb:
10550 case VCVTTPS2DQSZ128rmbk:
10551 case VCVTTPS2DQSZ128rmbkz:
10552 case VCVTTPS2DQSZ128rmk:
10553 case VCVTTPS2DQSZ128rmkz:
10554 case VCVTTPS2DQSZ128rr:
10555 case VCVTTPS2DQSZ128rrk:
10556 case VCVTTPS2DQSZ128rrkz:
10557 case VCVTTPS2DQSZ256rm:
10558 case VCVTTPS2DQSZ256rmb:
10559 case VCVTTPS2DQSZ256rmbk:
10560 case VCVTTPS2DQSZ256rmbkz:
10561 case VCVTTPS2DQSZ256rmk:
10562 case VCVTTPS2DQSZ256rmkz:
10563 case VCVTTPS2DQSZ256rr:
10564 case VCVTTPS2DQSZ256rrk:
10565 case VCVTTPS2DQSZ256rrkz:
10566 case VCVTTPS2DQSZrm:
10567 case VCVTTPS2DQSZrmb:
10568 case VCVTTPS2DQSZrmbk:
10569 case VCVTTPS2DQSZrmbkz:
10570 case VCVTTPS2DQSZrmk:
10571 case VCVTTPS2DQSZrmkz:
10572 case VCVTTPS2DQSZrr:
10573 case VCVTTPS2DQSZrrb:
10574 case VCVTTPS2DQSZrrbk:
10575 case VCVTTPS2DQSZrrbkz:
10576 case VCVTTPS2DQSZrrk:
10577 case VCVTTPS2DQSZrrkz:
10578 return true;
10579 }
10580 return false;
10581}
10582
10583bool isVPANDD(unsigned Opcode) {
10584 switch (Opcode) {
10585 case VPANDDZ128rm:
10586 case VPANDDZ128rmb:
10587 case VPANDDZ128rmbk:
10588 case VPANDDZ128rmbkz:
10589 case VPANDDZ128rmk:
10590 case VPANDDZ128rmkz:
10591 case VPANDDZ128rr:
10592 case VPANDDZ128rrk:
10593 case VPANDDZ128rrkz:
10594 case VPANDDZ256rm:
10595 case VPANDDZ256rmb:
10596 case VPANDDZ256rmbk:
10597 case VPANDDZ256rmbkz:
10598 case VPANDDZ256rmk:
10599 case VPANDDZ256rmkz:
10600 case VPANDDZ256rr:
10601 case VPANDDZ256rrk:
10602 case VPANDDZ256rrkz:
10603 case VPANDDZrm:
10604 case VPANDDZrmb:
10605 case VPANDDZrmbk:
10606 case VPANDDZrmbkz:
10607 case VPANDDZrmk:
10608 case VPANDDZrmkz:
10609 case VPANDDZrr:
10610 case VPANDDZrrk:
10611 case VPANDDZrrkz:
10612 return true;
10613 }
10614 return false;
10615}
10616
10617bool isPMINSW(unsigned Opcode) {
10618 switch (Opcode) {
10619 case MMX_PMINSWrm:
10620 case MMX_PMINSWrr:
10621 case PMINSWrm:
10622 case PMINSWrr:
10623 return true;
10624 }
10625 return false;
10626}
10627
10628bool isSTAC(unsigned Opcode) {
10629 return Opcode == STAC;
10630}
10631
10632bool isVFMSUB213PS(unsigned Opcode) {
10633 switch (Opcode) {
10634 case VFMSUB213PSYm:
10635 case VFMSUB213PSYr:
10636 case VFMSUB213PSZ128m:
10637 case VFMSUB213PSZ128mb:
10638 case VFMSUB213PSZ128mbk:
10639 case VFMSUB213PSZ128mbkz:
10640 case VFMSUB213PSZ128mk:
10641 case VFMSUB213PSZ128mkz:
10642 case VFMSUB213PSZ128r:
10643 case VFMSUB213PSZ128rk:
10644 case VFMSUB213PSZ128rkz:
10645 case VFMSUB213PSZ256m:
10646 case VFMSUB213PSZ256mb:
10647 case VFMSUB213PSZ256mbk:
10648 case VFMSUB213PSZ256mbkz:
10649 case VFMSUB213PSZ256mk:
10650 case VFMSUB213PSZ256mkz:
10651 case VFMSUB213PSZ256r:
10652 case VFMSUB213PSZ256rk:
10653 case VFMSUB213PSZ256rkz:
10654 case VFMSUB213PSZm:
10655 case VFMSUB213PSZmb:
10656 case VFMSUB213PSZmbk:
10657 case VFMSUB213PSZmbkz:
10658 case VFMSUB213PSZmk:
10659 case VFMSUB213PSZmkz:
10660 case VFMSUB213PSZr:
10661 case VFMSUB213PSZrb:
10662 case VFMSUB213PSZrbk:
10663 case VFMSUB213PSZrbkz:
10664 case VFMSUB213PSZrk:
10665 case VFMSUB213PSZrkz:
10666 case VFMSUB213PSm:
10667 case VFMSUB213PSr:
10668 return true;
10669 }
10670 return false;
10671}
10672
10673bool isPOPAL(unsigned Opcode) {
10674 return Opcode == POPA32;
10675}
10676
10677bool isVCVTPS2UQQ(unsigned Opcode) {
10678 switch (Opcode) {
10679 case VCVTPS2UQQZ128rm:
10680 case VCVTPS2UQQZ128rmb:
10681 case VCVTPS2UQQZ128rmbk:
10682 case VCVTPS2UQQZ128rmbkz:
10683 case VCVTPS2UQQZ128rmk:
10684 case VCVTPS2UQQZ128rmkz:
10685 case VCVTPS2UQQZ128rr:
10686 case VCVTPS2UQQZ128rrk:
10687 case VCVTPS2UQQZ128rrkz:
10688 case VCVTPS2UQQZ256rm:
10689 case VCVTPS2UQQZ256rmb:
10690 case VCVTPS2UQQZ256rmbk:
10691 case VCVTPS2UQQZ256rmbkz:
10692 case VCVTPS2UQQZ256rmk:
10693 case VCVTPS2UQQZ256rmkz:
10694 case VCVTPS2UQQZ256rr:
10695 case VCVTPS2UQQZ256rrk:
10696 case VCVTPS2UQQZ256rrkz:
10697 case VCVTPS2UQQZrm:
10698 case VCVTPS2UQQZrmb:
10699 case VCVTPS2UQQZrmbk:
10700 case VCVTPS2UQQZrmbkz:
10701 case VCVTPS2UQQZrmk:
10702 case VCVTPS2UQQZrmkz:
10703 case VCVTPS2UQQZrr:
10704 case VCVTPS2UQQZrrb:
10705 case VCVTPS2UQQZrrbk:
10706 case VCVTPS2UQQZrrbkz:
10707 case VCVTPS2UQQZrrk:
10708 case VCVTPS2UQQZrrkz:
10709 return true;
10710 }
10711 return false;
10712}
10713
10714bool isRDRAND(unsigned Opcode) {
10715 switch (Opcode) {
10716 case RDRAND16r:
10717 case RDRAND32r:
10718 case RDRAND64r:
10719 return true;
10720 }
10721 return false;
10722}
10723
10724bool isJCC(unsigned Opcode) {
10725 switch (Opcode) {
10726 case JCC_1:
10727 case JCC_2:
10728 case JCC_4:
10729 return true;
10730 }
10731 return false;
10732}
10733
10734bool isVPMINSQ(unsigned Opcode) {
10735 switch (Opcode) {
10736 case VPMINSQZ128rm:
10737 case VPMINSQZ128rmb:
10738 case VPMINSQZ128rmbk:
10739 case VPMINSQZ128rmbkz:
10740 case VPMINSQZ128rmk:
10741 case VPMINSQZ128rmkz:
10742 case VPMINSQZ128rr:
10743 case VPMINSQZ128rrk:
10744 case VPMINSQZ128rrkz:
10745 case VPMINSQZ256rm:
10746 case VPMINSQZ256rmb:
10747 case VPMINSQZ256rmbk:
10748 case VPMINSQZ256rmbkz:
10749 case VPMINSQZ256rmk:
10750 case VPMINSQZ256rmkz:
10751 case VPMINSQZ256rr:
10752 case VPMINSQZ256rrk:
10753 case VPMINSQZ256rrkz:
10754 case VPMINSQZrm:
10755 case VPMINSQZrmb:
10756 case VPMINSQZrmbk:
10757 case VPMINSQZrmbkz:
10758 case VPMINSQZrmk:
10759 case VPMINSQZrmkz:
10760 case VPMINSQZrr:
10761 case VPMINSQZrrk:
10762 case VPMINSQZrrkz:
10763 return true;
10764 }
10765 return false;
10766}
10767
10768bool isVADDSD(unsigned Opcode) {
10769 switch (Opcode) {
10770 case VADDSDZrm_Int:
10771 case VADDSDZrmk_Int:
10772 case VADDSDZrmkz_Int:
10773 case VADDSDZrr_Int:
10774 case VADDSDZrrb_Int:
10775 case VADDSDZrrbk_Int:
10776 case VADDSDZrrbkz_Int:
10777 case VADDSDZrrk_Int:
10778 case VADDSDZrrkz_Int:
10779 case VADDSDrm_Int:
10780 case VADDSDrr_Int:
10781 return true;
10782 }
10783 return false;
10784}
10785
10786bool isDPPS(unsigned Opcode) {
10787 switch (Opcode) {
10788 case DPPSrmi:
10789 case DPPSrri:
10790 return true;
10791 }
10792 return false;
10793}
10794
10795bool isPINSRQ(unsigned Opcode) {
10796 switch (Opcode) {
10797 case PINSRQrmi:
10798 case PINSRQrri:
10799 return true;
10800 }
10801 return false;
10802}
10803
10804bool isVUCOMISS(unsigned Opcode) {
10805 switch (Opcode) {
10806 case VUCOMISSZrm:
10807 case VUCOMISSZrr:
10808 case VUCOMISSZrrb:
10809 case VUCOMISSrm:
10810 case VUCOMISSrr:
10811 return true;
10812 }
10813 return false;
10814}
10815
10816bool isVPDPWSUD(unsigned Opcode) {
10817 switch (Opcode) {
10818 case VPDPWSUDYrm:
10819 case VPDPWSUDYrr:
10820 case VPDPWSUDZ128rm:
10821 case VPDPWSUDZ128rmb:
10822 case VPDPWSUDZ128rmbk:
10823 case VPDPWSUDZ128rmbkz:
10824 case VPDPWSUDZ128rmk:
10825 case VPDPWSUDZ128rmkz:
10826 case VPDPWSUDZ128rr:
10827 case VPDPWSUDZ128rrk:
10828 case VPDPWSUDZ128rrkz:
10829 case VPDPWSUDZ256rm:
10830 case VPDPWSUDZ256rmb:
10831 case VPDPWSUDZ256rmbk:
10832 case VPDPWSUDZ256rmbkz:
10833 case VPDPWSUDZ256rmk:
10834 case VPDPWSUDZ256rmkz:
10835 case VPDPWSUDZ256rr:
10836 case VPDPWSUDZ256rrk:
10837 case VPDPWSUDZ256rrkz:
10838 case VPDPWSUDZrm:
10839 case VPDPWSUDZrmb:
10840 case VPDPWSUDZrmbk:
10841 case VPDPWSUDZrmbkz:
10842 case VPDPWSUDZrmk:
10843 case VPDPWSUDZrmkz:
10844 case VPDPWSUDZrr:
10845 case VPDPWSUDZrrk:
10846 case VPDPWSUDZrrkz:
10847 case VPDPWSUDrm:
10848 case VPDPWSUDrr:
10849 return true;
10850 }
10851 return false;
10852}
10853
10854bool isKANDNW(unsigned Opcode) {
10855 return Opcode == KANDNWkk;
10856}
10857
10858bool isAOR(unsigned Opcode) {
10859 switch (Opcode) {
10860 case AOR32mr:
10861 case AOR32mr_EVEX:
10862 case AOR64mr:
10863 case AOR64mr_EVEX:
10864 return true;
10865 }
10866 return false;
10867}
10868
10869bool isPMAXUB(unsigned Opcode) {
10870 switch (Opcode) {
10871 case MMX_PMAXUBrm:
10872 case MMX_PMAXUBrr:
10873 case PMAXUBrm:
10874 case PMAXUBrr:
10875 return true;
10876 }
10877 return false;
10878}
10879
10880bool isANDNPD(unsigned Opcode) {
10881 switch (Opcode) {
10882 case ANDNPDrm:
10883 case ANDNPDrr:
10884 return true;
10885 }
10886 return false;
10887}
10888
10889bool isINVPCID(unsigned Opcode) {
10890 switch (Opcode) {
10891 case INVPCID32:
10892 case INVPCID64:
10893 case INVPCID64_EVEX:
10894 return true;
10895 }
10896 return false;
10897}
10898
10899bool isRDGSBASE(unsigned Opcode) {
10900 switch (Opcode) {
10901 case RDGSBASE:
10902 case RDGSBASE64:
10903 return true;
10904 }
10905 return false;
10906}
10907
10908bool isVPMOVSQD(unsigned Opcode) {
10909 switch (Opcode) {
10910 case VPMOVSQDZ128mr:
10911 case VPMOVSQDZ128mrk:
10912 case VPMOVSQDZ128rr:
10913 case VPMOVSQDZ128rrk:
10914 case VPMOVSQDZ128rrkz:
10915 case VPMOVSQDZ256mr:
10916 case VPMOVSQDZ256mrk:
10917 case VPMOVSQDZ256rr:
10918 case VPMOVSQDZ256rrk:
10919 case VPMOVSQDZ256rrkz:
10920 case VPMOVSQDZmr:
10921 case VPMOVSQDZmrk:
10922 case VPMOVSQDZrr:
10923 case VPMOVSQDZrrk:
10924 case VPMOVSQDZrrkz:
10925 return true;
10926 }
10927 return false;
10928}
10929
10930bool isBT(unsigned Opcode) {
10931 switch (Opcode) {
10932 case BT16mi8:
10933 case BT16mr:
10934 case BT16ri8:
10935 case BT16rr:
10936 case BT32mi8:
10937 case BT32mr:
10938 case BT32ri8:
10939 case BT32rr:
10940 case BT64mi8:
10941 case BT64mr:
10942 case BT64ri8:
10943 case BT64rr:
10944 return true;
10945 }
10946 return false;
10947}
10948
10949bool isVPROLVQ(unsigned Opcode) {
10950 switch (Opcode) {
10951 case VPROLVQZ128rm:
10952 case VPROLVQZ128rmb:
10953 case VPROLVQZ128rmbk:
10954 case VPROLVQZ128rmbkz:
10955 case VPROLVQZ128rmk:
10956 case VPROLVQZ128rmkz:
10957 case VPROLVQZ128rr:
10958 case VPROLVQZ128rrk:
10959 case VPROLVQZ128rrkz:
10960 case VPROLVQZ256rm:
10961 case VPROLVQZ256rmb:
10962 case VPROLVQZ256rmbk:
10963 case VPROLVQZ256rmbkz:
10964 case VPROLVQZ256rmk:
10965 case VPROLVQZ256rmkz:
10966 case VPROLVQZ256rr:
10967 case VPROLVQZ256rrk:
10968 case VPROLVQZ256rrkz:
10969 case VPROLVQZrm:
10970 case VPROLVQZrmb:
10971 case VPROLVQZrmbk:
10972 case VPROLVQZrmbkz:
10973 case VPROLVQZrmk:
10974 case VPROLVQZrmkz:
10975 case VPROLVQZrr:
10976 case VPROLVQZrrk:
10977 case VPROLVQZrrkz:
10978 return true;
10979 }
10980 return false;
10981}
10982
10983bool isVFMADDSUB132PD(unsigned Opcode) {
10984 switch (Opcode) {
10985 case VFMADDSUB132PDYm:
10986 case VFMADDSUB132PDYr:
10987 case VFMADDSUB132PDZ128m:
10988 case VFMADDSUB132PDZ128mb:
10989 case VFMADDSUB132PDZ128mbk:
10990 case VFMADDSUB132PDZ128mbkz:
10991 case VFMADDSUB132PDZ128mk:
10992 case VFMADDSUB132PDZ128mkz:
10993 case VFMADDSUB132PDZ128r:
10994 case VFMADDSUB132PDZ128rk:
10995 case VFMADDSUB132PDZ128rkz:
10996 case VFMADDSUB132PDZ256m:
10997 case VFMADDSUB132PDZ256mb:
10998 case VFMADDSUB132PDZ256mbk:
10999 case VFMADDSUB132PDZ256mbkz:
11000 case VFMADDSUB132PDZ256mk:
11001 case VFMADDSUB132PDZ256mkz:
11002 case VFMADDSUB132PDZ256r:
11003 case VFMADDSUB132PDZ256rk:
11004 case VFMADDSUB132PDZ256rkz:
11005 case VFMADDSUB132PDZm:
11006 case VFMADDSUB132PDZmb:
11007 case VFMADDSUB132PDZmbk:
11008 case VFMADDSUB132PDZmbkz:
11009 case VFMADDSUB132PDZmk:
11010 case VFMADDSUB132PDZmkz:
11011 case VFMADDSUB132PDZr:
11012 case VFMADDSUB132PDZrb:
11013 case VFMADDSUB132PDZrbk:
11014 case VFMADDSUB132PDZrbkz:
11015 case VFMADDSUB132PDZrk:
11016 case VFMADDSUB132PDZrkz:
11017 case VFMADDSUB132PDm:
11018 case VFMADDSUB132PDr:
11019 return true;
11020 }
11021 return false;
11022}
11023
11024bool isRORX(unsigned Opcode) {
11025 switch (Opcode) {
11026 case RORX32mi:
11027 case RORX32mi_EVEX:
11028 case RORX32ri:
11029 case RORX32ri_EVEX:
11030 case RORX64mi:
11031 case RORX64mi_EVEX:
11032 case RORX64ri:
11033 case RORX64ri_EVEX:
11034 return true;
11035 }
11036 return false;
11037}
11038
11039bool isPADDUSW(unsigned Opcode) {
11040 switch (Opcode) {
11041 case MMX_PADDUSWrm:
11042 case MMX_PADDUSWrr:
11043 case PADDUSWrm:
11044 case PADDUSWrr:
11045 return true;
11046 }
11047 return false;
11048}
11049
11050bool isPFNACC(unsigned Opcode) {
11051 switch (Opcode) {
11052 case PFNACCrm:
11053 case PFNACCrr:
11054 return true;
11055 }
11056 return false;
11057}
11058
11059bool isAND(unsigned Opcode) {
11060 switch (Opcode) {
11061 case AND16i16:
11062 case AND16mi:
11063 case AND16mi8:
11064 case AND16mi8_EVEX:
11065 case AND16mi8_ND:
11066 case AND16mi8_NF:
11067 case AND16mi8_NF_ND:
11068 case AND16mi_EVEX:
11069 case AND16mi_ND:
11070 case AND16mi_NF:
11071 case AND16mi_NF_ND:
11072 case AND16mr:
11073 case AND16mr_EVEX:
11074 case AND16mr_ND:
11075 case AND16mr_NF:
11076 case AND16mr_NF_ND:
11077 case AND16ri:
11078 case AND16ri8:
11079 case AND16ri8_EVEX:
11080 case AND16ri8_ND:
11081 case AND16ri8_NF:
11082 case AND16ri8_NF_ND:
11083 case AND16ri_EVEX:
11084 case AND16ri_ND:
11085 case AND16ri_NF:
11086 case AND16ri_NF_ND:
11087 case AND16rm:
11088 case AND16rm_EVEX:
11089 case AND16rm_ND:
11090 case AND16rm_NF:
11091 case AND16rm_NF_ND:
11092 case AND16rr:
11093 case AND16rr_EVEX:
11094 case AND16rr_EVEX_REV:
11095 case AND16rr_ND:
11096 case AND16rr_ND_REV:
11097 case AND16rr_NF:
11098 case AND16rr_NF_ND:
11099 case AND16rr_NF_ND_REV:
11100 case AND16rr_NF_REV:
11101 case AND16rr_REV:
11102 case AND32i32:
11103 case AND32mi:
11104 case AND32mi8:
11105 case AND32mi8_EVEX:
11106 case AND32mi8_ND:
11107 case AND32mi8_NF:
11108 case AND32mi8_NF_ND:
11109 case AND32mi_EVEX:
11110 case AND32mi_ND:
11111 case AND32mi_NF:
11112 case AND32mi_NF_ND:
11113 case AND32mr:
11114 case AND32mr_EVEX:
11115 case AND32mr_ND:
11116 case AND32mr_NF:
11117 case AND32mr_NF_ND:
11118 case AND32ri:
11119 case AND32ri8:
11120 case AND32ri8_EVEX:
11121 case AND32ri8_ND:
11122 case AND32ri8_NF:
11123 case AND32ri8_NF_ND:
11124 case AND32ri_EVEX:
11125 case AND32ri_ND:
11126 case AND32ri_NF:
11127 case AND32ri_NF_ND:
11128 case AND32rm:
11129 case AND32rm_EVEX:
11130 case AND32rm_ND:
11131 case AND32rm_NF:
11132 case AND32rm_NF_ND:
11133 case AND32rr:
11134 case AND32rr_EVEX:
11135 case AND32rr_EVEX_REV:
11136 case AND32rr_ND:
11137 case AND32rr_ND_REV:
11138 case AND32rr_NF:
11139 case AND32rr_NF_ND:
11140 case AND32rr_NF_ND_REV:
11141 case AND32rr_NF_REV:
11142 case AND32rr_REV:
11143 case AND64i32:
11144 case AND64mi32:
11145 case AND64mi32_EVEX:
11146 case AND64mi32_ND:
11147 case AND64mi32_NF:
11148 case AND64mi32_NF_ND:
11149 case AND64mi8:
11150 case AND64mi8_EVEX:
11151 case AND64mi8_ND:
11152 case AND64mi8_NF:
11153 case AND64mi8_NF_ND:
11154 case AND64mr:
11155 case AND64mr_EVEX:
11156 case AND64mr_ND:
11157 case AND64mr_NF:
11158 case AND64mr_NF_ND:
11159 case AND64ri32:
11160 case AND64ri32_EVEX:
11161 case AND64ri32_ND:
11162 case AND64ri32_NF:
11163 case AND64ri32_NF_ND:
11164 case AND64ri8:
11165 case AND64ri8_EVEX:
11166 case AND64ri8_ND:
11167 case AND64ri8_NF:
11168 case AND64ri8_NF_ND:
11169 case AND64rm:
11170 case AND64rm_EVEX:
11171 case AND64rm_ND:
11172 case AND64rm_NF:
11173 case AND64rm_NF_ND:
11174 case AND64rr:
11175 case AND64rr_EVEX:
11176 case AND64rr_EVEX_REV:
11177 case AND64rr_ND:
11178 case AND64rr_ND_REV:
11179 case AND64rr_NF:
11180 case AND64rr_NF_ND:
11181 case AND64rr_NF_ND_REV:
11182 case AND64rr_NF_REV:
11183 case AND64rr_REV:
11184 case AND8i8:
11185 case AND8mi:
11186 case AND8mi8:
11187 case AND8mi_EVEX:
11188 case AND8mi_ND:
11189 case AND8mi_NF:
11190 case AND8mi_NF_ND:
11191 case AND8mr:
11192 case AND8mr_EVEX:
11193 case AND8mr_ND:
11194 case AND8mr_NF:
11195 case AND8mr_NF_ND:
11196 case AND8ri:
11197 case AND8ri8:
11198 case AND8ri_EVEX:
11199 case AND8ri_ND:
11200 case AND8ri_NF:
11201 case AND8ri_NF_ND:
11202 case AND8rm:
11203 case AND8rm_EVEX:
11204 case AND8rm_ND:
11205 case AND8rm_NF:
11206 case AND8rm_NF_ND:
11207 case AND8rr:
11208 case AND8rr_EVEX:
11209 case AND8rr_EVEX_REV:
11210 case AND8rr_ND:
11211 case AND8rr_ND_REV:
11212 case AND8rr_NF:
11213 case AND8rr_NF_ND:
11214 case AND8rr_NF_ND_REV:
11215 case AND8rr_NF_REV:
11216 case AND8rr_REV:
11217 return true;
11218 }
11219 return false;
11220}
11221
11222bool isPSLLQ(unsigned Opcode) {
11223 switch (Opcode) {
11224 case MMX_PSLLQri:
11225 case MMX_PSLLQrm:
11226 case MMX_PSLLQrr:
11227 case PSLLQri:
11228 case PSLLQrm:
11229 case PSLLQrr:
11230 return true;
11231 }
11232 return false;
11233}
11234
11235bool isVFMSUB132PH(unsigned Opcode) {
11236 switch (Opcode) {
11237 case VFMSUB132PHZ128m:
11238 case VFMSUB132PHZ128mb:
11239 case VFMSUB132PHZ128mbk:
11240 case VFMSUB132PHZ128mbkz:
11241 case VFMSUB132PHZ128mk:
11242 case VFMSUB132PHZ128mkz:
11243 case VFMSUB132PHZ128r:
11244 case VFMSUB132PHZ128rk:
11245 case VFMSUB132PHZ128rkz:
11246 case VFMSUB132PHZ256m:
11247 case VFMSUB132PHZ256mb:
11248 case VFMSUB132PHZ256mbk:
11249 case VFMSUB132PHZ256mbkz:
11250 case VFMSUB132PHZ256mk:
11251 case VFMSUB132PHZ256mkz:
11252 case VFMSUB132PHZ256r:
11253 case VFMSUB132PHZ256rk:
11254 case VFMSUB132PHZ256rkz:
11255 case VFMSUB132PHZm:
11256 case VFMSUB132PHZmb:
11257 case VFMSUB132PHZmbk:
11258 case VFMSUB132PHZmbkz:
11259 case VFMSUB132PHZmk:
11260 case VFMSUB132PHZmkz:
11261 case VFMSUB132PHZr:
11262 case VFMSUB132PHZrb:
11263 case VFMSUB132PHZrbk:
11264 case VFMSUB132PHZrbkz:
11265 case VFMSUB132PHZrk:
11266 case VFMSUB132PHZrkz:
11267 return true;
11268 }
11269 return false;
11270}
11271
11272bool isXSAVE(unsigned Opcode) {
11273 return Opcode == XSAVE;
11274}
11275
11276bool isKNOTQ(unsigned Opcode) {
11277 return Opcode == KNOTQkk;
11278}
11279
11280bool isXTEST(unsigned Opcode) {
11281 return Opcode == XTEST;
11282}
11283
11284bool isVINSERTPS(unsigned Opcode) {
11285 switch (Opcode) {
11286 case VINSERTPSZrmi:
11287 case VINSERTPSZrri:
11288 case VINSERTPSrmi:
11289 case VINSERTPSrri:
11290 return true;
11291 }
11292 return false;
11293}
11294
11295bool isXSAVEOPT(unsigned Opcode) {
11296 return Opcode == XSAVEOPT;
11297}
11298
11299bool isLDS(unsigned Opcode) {
11300 switch (Opcode) {
11301 case LDS16rm:
11302 case LDS32rm:
11303 return true;
11304 }
11305 return false;
11306}
11307
11308bool isVFMADDSUB213PD(unsigned Opcode) {
11309 switch (Opcode) {
11310 case VFMADDSUB213PDYm:
11311 case VFMADDSUB213PDYr:
11312 case VFMADDSUB213PDZ128m:
11313 case VFMADDSUB213PDZ128mb:
11314 case VFMADDSUB213PDZ128mbk:
11315 case VFMADDSUB213PDZ128mbkz:
11316 case VFMADDSUB213PDZ128mk:
11317 case VFMADDSUB213PDZ128mkz:
11318 case VFMADDSUB213PDZ128r:
11319 case VFMADDSUB213PDZ128rk:
11320 case VFMADDSUB213PDZ128rkz:
11321 case VFMADDSUB213PDZ256m:
11322 case VFMADDSUB213PDZ256mb:
11323 case VFMADDSUB213PDZ256mbk:
11324 case VFMADDSUB213PDZ256mbkz:
11325 case VFMADDSUB213PDZ256mk:
11326 case VFMADDSUB213PDZ256mkz:
11327 case VFMADDSUB213PDZ256r:
11328 case VFMADDSUB213PDZ256rk:
11329 case VFMADDSUB213PDZ256rkz:
11330 case VFMADDSUB213PDZm:
11331 case VFMADDSUB213PDZmb:
11332 case VFMADDSUB213PDZmbk:
11333 case VFMADDSUB213PDZmbkz:
11334 case VFMADDSUB213PDZmk:
11335 case VFMADDSUB213PDZmkz:
11336 case VFMADDSUB213PDZr:
11337 case VFMADDSUB213PDZrb:
11338 case VFMADDSUB213PDZrbk:
11339 case VFMADDSUB213PDZrbkz:
11340 case VFMADDSUB213PDZrk:
11341 case VFMADDSUB213PDZrkz:
11342 case VFMADDSUB213PDm:
11343 case VFMADDSUB213PDr:
11344 return true;
11345 }
11346 return false;
11347}
11348
11349bool isVINSERTF32X4(unsigned Opcode) {
11350 switch (Opcode) {
11351 case VINSERTF32X4Z256rmi:
11352 case VINSERTF32X4Z256rmik:
11353 case VINSERTF32X4Z256rmikz:
11354 case VINSERTF32X4Z256rri:
11355 case VINSERTF32X4Z256rrik:
11356 case VINSERTF32X4Z256rrikz:
11357 case VINSERTF32X4Zrmi:
11358 case VINSERTF32X4Zrmik:
11359 case VINSERTF32X4Zrmikz:
11360 case VINSERTF32X4Zrri:
11361 case VINSERTF32X4Zrrik:
11362 case VINSERTF32X4Zrrikz:
11363 return true;
11364 }
11365 return false;
11366}
11367
11368bool isVRSQRTPS(unsigned Opcode) {
11369 switch (Opcode) {
11370 case VRSQRTPSYm:
11371 case VRSQRTPSYr:
11372 case VRSQRTPSm:
11373 case VRSQRTPSr:
11374 return true;
11375 }
11376 return false;
11377}
11378
11379bool isVSUBPH(unsigned Opcode) {
11380 switch (Opcode) {
11381 case VSUBPHZ128rm:
11382 case VSUBPHZ128rmb:
11383 case VSUBPHZ128rmbk:
11384 case VSUBPHZ128rmbkz:
11385 case VSUBPHZ128rmk:
11386 case VSUBPHZ128rmkz:
11387 case VSUBPHZ128rr:
11388 case VSUBPHZ128rrk:
11389 case VSUBPHZ128rrkz:
11390 case VSUBPHZ256rm:
11391 case VSUBPHZ256rmb:
11392 case VSUBPHZ256rmbk:
11393 case VSUBPHZ256rmbkz:
11394 case VSUBPHZ256rmk:
11395 case VSUBPHZ256rmkz:
11396 case VSUBPHZ256rr:
11397 case VSUBPHZ256rrk:
11398 case VSUBPHZ256rrkz:
11399 case VSUBPHZrm:
11400 case VSUBPHZrmb:
11401 case VSUBPHZrmbk:
11402 case VSUBPHZrmbkz:
11403 case VSUBPHZrmk:
11404 case VSUBPHZrmkz:
11405 case VSUBPHZrr:
11406 case VSUBPHZrrb:
11407 case VSUBPHZrrbk:
11408 case VSUBPHZrrbkz:
11409 case VSUBPHZrrk:
11410 case VSUBPHZrrkz:
11411 return true;
11412 }
11413 return false;
11414}
11415
11416bool isPMOVSXBW(unsigned Opcode) {
11417 switch (Opcode) {
11418 case PMOVSXBWrm:
11419 case PMOVSXBWrr:
11420 return true;
11421 }
11422 return false;
11423}
11424
11425bool isVPSRLDQ(unsigned Opcode) {
11426 switch (Opcode) {
11427 case VPSRLDQYri:
11428 case VPSRLDQZ128mi:
11429 case VPSRLDQZ128ri:
11430 case VPSRLDQZ256mi:
11431 case VPSRLDQZ256ri:
11432 case VPSRLDQZmi:
11433 case VPSRLDQZri:
11434 case VPSRLDQri:
11435 return true;
11436 }
11437 return false;
11438}
11439
11440bool isADC(unsigned Opcode) {
11441 switch (Opcode) {
11442 case ADC16i16:
11443 case ADC16mi:
11444 case ADC16mi8:
11445 case ADC16mi8_EVEX:
11446 case ADC16mi8_ND:
11447 case ADC16mi_EVEX:
11448 case ADC16mi_ND:
11449 case ADC16mr:
11450 case ADC16mr_EVEX:
11451 case ADC16mr_ND:
11452 case ADC16ri:
11453 case ADC16ri8:
11454 case ADC16ri8_EVEX:
11455 case ADC16ri8_ND:
11456 case ADC16ri_EVEX:
11457 case ADC16ri_ND:
11458 case ADC16rm:
11459 case ADC16rm_EVEX:
11460 case ADC16rm_ND:
11461 case ADC16rr:
11462 case ADC16rr_EVEX:
11463 case ADC16rr_EVEX_REV:
11464 case ADC16rr_ND:
11465 case ADC16rr_ND_REV:
11466 case ADC16rr_REV:
11467 case ADC32i32:
11468 case ADC32mi:
11469 case ADC32mi8:
11470 case ADC32mi8_EVEX:
11471 case ADC32mi8_ND:
11472 case ADC32mi_EVEX:
11473 case ADC32mi_ND:
11474 case ADC32mr:
11475 case ADC32mr_EVEX:
11476 case ADC32mr_ND:
11477 case ADC32ri:
11478 case ADC32ri8:
11479 case ADC32ri8_EVEX:
11480 case ADC32ri8_ND:
11481 case ADC32ri_EVEX:
11482 case ADC32ri_ND:
11483 case ADC32rm:
11484 case ADC32rm_EVEX:
11485 case ADC32rm_ND:
11486 case ADC32rr:
11487 case ADC32rr_EVEX:
11488 case ADC32rr_EVEX_REV:
11489 case ADC32rr_ND:
11490 case ADC32rr_ND_REV:
11491 case ADC32rr_REV:
11492 case ADC64i32:
11493 case ADC64mi32:
11494 case ADC64mi32_EVEX:
11495 case ADC64mi32_ND:
11496 case ADC64mi8:
11497 case ADC64mi8_EVEX:
11498 case ADC64mi8_ND:
11499 case ADC64mr:
11500 case ADC64mr_EVEX:
11501 case ADC64mr_ND:
11502 case ADC64ri32:
11503 case ADC64ri32_EVEX:
11504 case ADC64ri32_ND:
11505 case ADC64ri8:
11506 case ADC64ri8_EVEX:
11507 case ADC64ri8_ND:
11508 case ADC64rm:
11509 case ADC64rm_EVEX:
11510 case ADC64rm_ND:
11511 case ADC64rr:
11512 case ADC64rr_EVEX:
11513 case ADC64rr_EVEX_REV:
11514 case ADC64rr_ND:
11515 case ADC64rr_ND_REV:
11516 case ADC64rr_REV:
11517 case ADC8i8:
11518 case ADC8mi:
11519 case ADC8mi8:
11520 case ADC8mi_EVEX:
11521 case ADC8mi_ND:
11522 case ADC8mr:
11523 case ADC8mr_EVEX:
11524 case ADC8mr_ND:
11525 case ADC8ri:
11526 case ADC8ri8:
11527 case ADC8ri_EVEX:
11528 case ADC8ri_ND:
11529 case ADC8rm:
11530 case ADC8rm_EVEX:
11531 case ADC8rm_ND:
11532 case ADC8rr:
11533 case ADC8rr_EVEX:
11534 case ADC8rr_EVEX_REV:
11535 case ADC8rr_ND:
11536 case ADC8rr_ND_REV:
11537 case ADC8rr_REV:
11538 return true;
11539 }
11540 return false;
11541}
11542
11543bool isPHADDD(unsigned Opcode) {
11544 switch (Opcode) {
11545 case MMX_PHADDDrm:
11546 case MMX_PHADDDrr:
11547 case PHADDDrm:
11548 case PHADDDrr:
11549 return true;
11550 }
11551 return false;
11552}
11553
11554bool isVDPPHPS(unsigned Opcode) {
11555 switch (Opcode) {
11556 case VDPPHPSZ128m:
11557 case VDPPHPSZ128mb:
11558 case VDPPHPSZ128mbk:
11559 case VDPPHPSZ128mbkz:
11560 case VDPPHPSZ128mk:
11561 case VDPPHPSZ128mkz:
11562 case VDPPHPSZ128r:
11563 case VDPPHPSZ128rk:
11564 case VDPPHPSZ128rkz:
11565 case VDPPHPSZ256m:
11566 case VDPPHPSZ256mb:
11567 case VDPPHPSZ256mbk:
11568 case VDPPHPSZ256mbkz:
11569 case VDPPHPSZ256mk:
11570 case VDPPHPSZ256mkz:
11571 case VDPPHPSZ256r:
11572 case VDPPHPSZ256rk:
11573 case VDPPHPSZ256rkz:
11574 case VDPPHPSZm:
11575 case VDPPHPSZmb:
11576 case VDPPHPSZmbk:
11577 case VDPPHPSZmbkz:
11578 case VDPPHPSZmk:
11579 case VDPPHPSZmkz:
11580 case VDPPHPSZr:
11581 case VDPPHPSZrk:
11582 case VDPPHPSZrkz:
11583 return true;
11584 }
11585 return false;
11586}
11587
11588bool isVMINPH(unsigned Opcode) {
11589 switch (Opcode) {
11590 case VMINPHZ128rm:
11591 case VMINPHZ128rmb:
11592 case VMINPHZ128rmbk:
11593 case VMINPHZ128rmbkz:
11594 case VMINPHZ128rmk:
11595 case VMINPHZ128rmkz:
11596 case VMINPHZ128rr:
11597 case VMINPHZ128rrk:
11598 case VMINPHZ128rrkz:
11599 case VMINPHZ256rm:
11600 case VMINPHZ256rmb:
11601 case VMINPHZ256rmbk:
11602 case VMINPHZ256rmbkz:
11603 case VMINPHZ256rmk:
11604 case VMINPHZ256rmkz:
11605 case VMINPHZ256rr:
11606 case VMINPHZ256rrk:
11607 case VMINPHZ256rrkz:
11608 case VMINPHZrm:
11609 case VMINPHZrmb:
11610 case VMINPHZrmbk:
11611 case VMINPHZrmbkz:
11612 case VMINPHZrmk:
11613 case VMINPHZrmkz:
11614 case VMINPHZrr:
11615 case VMINPHZrrb:
11616 case VMINPHZrrbk:
11617 case VMINPHZrrbkz:
11618 case VMINPHZrrk:
11619 case VMINPHZrrkz:
11620 return true;
11621 }
11622 return false;
11623}
11624
11625bool isVMINSD(unsigned Opcode) {
11626 switch (Opcode) {
11627 case VMINSDZrm_Int:
11628 case VMINSDZrmk_Int:
11629 case VMINSDZrmkz_Int:
11630 case VMINSDZrr_Int:
11631 case VMINSDZrrb_Int:
11632 case VMINSDZrrbk_Int:
11633 case VMINSDZrrbkz_Int:
11634 case VMINSDZrrk_Int:
11635 case VMINSDZrrkz_Int:
11636 case VMINSDrm_Int:
11637 case VMINSDrr_Int:
11638 return true;
11639 }
11640 return false;
11641}
11642
11643bool isVROUNDPD(unsigned Opcode) {
11644 switch (Opcode) {
11645 case VROUNDPDYmi:
11646 case VROUNDPDYri:
11647 case VROUNDPDmi:
11648 case VROUNDPDri:
11649 return true;
11650 }
11651 return false;
11652}
11653
11654bool isVFCMADDCPH(unsigned Opcode) {
11655 switch (Opcode) {
11656 case VFCMADDCPHZ128m:
11657 case VFCMADDCPHZ128mb:
11658 case VFCMADDCPHZ128mbk:
11659 case VFCMADDCPHZ128mbkz:
11660 case VFCMADDCPHZ128mk:
11661 case VFCMADDCPHZ128mkz:
11662 case VFCMADDCPHZ128r:
11663 case VFCMADDCPHZ128rk:
11664 case VFCMADDCPHZ128rkz:
11665 case VFCMADDCPHZ256m:
11666 case VFCMADDCPHZ256mb:
11667 case VFCMADDCPHZ256mbk:
11668 case VFCMADDCPHZ256mbkz:
11669 case VFCMADDCPHZ256mk:
11670 case VFCMADDCPHZ256mkz:
11671 case VFCMADDCPHZ256r:
11672 case VFCMADDCPHZ256rk:
11673 case VFCMADDCPHZ256rkz:
11674 case VFCMADDCPHZm:
11675 case VFCMADDCPHZmb:
11676 case VFCMADDCPHZmbk:
11677 case VFCMADDCPHZmbkz:
11678 case VFCMADDCPHZmk:
11679 case VFCMADDCPHZmkz:
11680 case VFCMADDCPHZr:
11681 case VFCMADDCPHZrb:
11682 case VFCMADDCPHZrbk:
11683 case VFCMADDCPHZrbkz:
11684 case VFCMADDCPHZrk:
11685 case VFCMADDCPHZrkz:
11686 return true;
11687 }
11688 return false;
11689}
11690
11691bool isINCSSPQ(unsigned Opcode) {
11692 return Opcode == INCSSPQ;
11693}
11694
11695bool isVPUNPCKLDQ(unsigned Opcode) {
11696 switch (Opcode) {
11697 case VPUNPCKLDQYrm:
11698 case VPUNPCKLDQYrr:
11699 case VPUNPCKLDQZ128rm:
11700 case VPUNPCKLDQZ128rmb:
11701 case VPUNPCKLDQZ128rmbk:
11702 case VPUNPCKLDQZ128rmbkz:
11703 case VPUNPCKLDQZ128rmk:
11704 case VPUNPCKLDQZ128rmkz:
11705 case VPUNPCKLDQZ128rr:
11706 case VPUNPCKLDQZ128rrk:
11707 case VPUNPCKLDQZ128rrkz:
11708 case VPUNPCKLDQZ256rm:
11709 case VPUNPCKLDQZ256rmb:
11710 case VPUNPCKLDQZ256rmbk:
11711 case VPUNPCKLDQZ256rmbkz:
11712 case VPUNPCKLDQZ256rmk:
11713 case VPUNPCKLDQZ256rmkz:
11714 case VPUNPCKLDQZ256rr:
11715 case VPUNPCKLDQZ256rrk:
11716 case VPUNPCKLDQZ256rrkz:
11717 case VPUNPCKLDQZrm:
11718 case VPUNPCKLDQZrmb:
11719 case VPUNPCKLDQZrmbk:
11720 case VPUNPCKLDQZrmbkz:
11721 case VPUNPCKLDQZrmk:
11722 case VPUNPCKLDQZrmkz:
11723 case VPUNPCKLDQZrr:
11724 case VPUNPCKLDQZrrk:
11725 case VPUNPCKLDQZrrkz:
11726 case VPUNPCKLDQrm:
11727 case VPUNPCKLDQrr:
11728 return true;
11729 }
11730 return false;
11731}
11732
11733bool isVMINSH(unsigned Opcode) {
11734 switch (Opcode) {
11735 case VMINSHZrm_Int:
11736 case VMINSHZrmk_Int:
11737 case VMINSHZrmkz_Int:
11738 case VMINSHZrr_Int:
11739 case VMINSHZrrb_Int:
11740 case VMINSHZrrbk_Int:
11741 case VMINSHZrrbkz_Int:
11742 case VMINSHZrrk_Int:
11743 case VMINSHZrrkz_Int:
11744 return true;
11745 }
11746 return false;
11747}
11748
11749bool isINSERTQ(unsigned Opcode) {
11750 switch (Opcode) {
11751 case INSERTQ:
11752 case INSERTQI:
11753 return true;
11754 }
11755 return false;
11756}
11757
11758bool isBLCI(unsigned Opcode) {
11759 switch (Opcode) {
11760 case BLCI32rm:
11761 case BLCI32rr:
11762 case BLCI64rm:
11763 case BLCI64rr:
11764 return true;
11765 }
11766 return false;
11767}
11768
11769bool isHLT(unsigned Opcode) {
11770 return Opcode == HLT;
11771}
11772
11773bool isVPCOMUW(unsigned Opcode) {
11774 switch (Opcode) {
11775 case VPCOMUWmi:
11776 case VPCOMUWri:
11777 return true;
11778 }
11779 return false;
11780}
11781
11782bool isVPMOVSXDQ(unsigned Opcode) {
11783 switch (Opcode) {
11784 case VPMOVSXDQYrm:
11785 case VPMOVSXDQYrr:
11786 case VPMOVSXDQZ128rm:
11787 case VPMOVSXDQZ128rmk:
11788 case VPMOVSXDQZ128rmkz:
11789 case VPMOVSXDQZ128rr:
11790 case VPMOVSXDQZ128rrk:
11791 case VPMOVSXDQZ128rrkz:
11792 case VPMOVSXDQZ256rm:
11793 case VPMOVSXDQZ256rmk:
11794 case VPMOVSXDQZ256rmkz:
11795 case VPMOVSXDQZ256rr:
11796 case VPMOVSXDQZ256rrk:
11797 case VPMOVSXDQZ256rrkz:
11798 case VPMOVSXDQZrm:
11799 case VPMOVSXDQZrmk:
11800 case VPMOVSXDQZrmkz:
11801 case VPMOVSXDQZrr:
11802 case VPMOVSXDQZrrk:
11803 case VPMOVSXDQZrrkz:
11804 case VPMOVSXDQrm:
11805 case VPMOVSXDQrr:
11806 return true;
11807 }
11808 return false;
11809}
11810
11811bool isVFNMSUB231PS(unsigned Opcode) {
11812 switch (Opcode) {
11813 case VFNMSUB231PSYm:
11814 case VFNMSUB231PSYr:
11815 case VFNMSUB231PSZ128m:
11816 case VFNMSUB231PSZ128mb:
11817 case VFNMSUB231PSZ128mbk:
11818 case VFNMSUB231PSZ128mbkz:
11819 case VFNMSUB231PSZ128mk:
11820 case VFNMSUB231PSZ128mkz:
11821 case VFNMSUB231PSZ128r:
11822 case VFNMSUB231PSZ128rk:
11823 case VFNMSUB231PSZ128rkz:
11824 case VFNMSUB231PSZ256m:
11825 case VFNMSUB231PSZ256mb:
11826 case VFNMSUB231PSZ256mbk:
11827 case VFNMSUB231PSZ256mbkz:
11828 case VFNMSUB231PSZ256mk:
11829 case VFNMSUB231PSZ256mkz:
11830 case VFNMSUB231PSZ256r:
11831 case VFNMSUB231PSZ256rk:
11832 case VFNMSUB231PSZ256rkz:
11833 case VFNMSUB231PSZm:
11834 case VFNMSUB231PSZmb:
11835 case VFNMSUB231PSZmbk:
11836 case VFNMSUB231PSZmbkz:
11837 case VFNMSUB231PSZmk:
11838 case VFNMSUB231PSZmkz:
11839 case VFNMSUB231PSZr:
11840 case VFNMSUB231PSZrb:
11841 case VFNMSUB231PSZrbk:
11842 case VFNMSUB231PSZrbkz:
11843 case VFNMSUB231PSZrk:
11844 case VFNMSUB231PSZrkz:
11845 case VFNMSUB231PSm:
11846 case VFNMSUB231PSr:
11847 return true;
11848 }
11849 return false;
11850}
11851
11852bool isVFNMSUB213SH(unsigned Opcode) {
11853 switch (Opcode) {
11854 case VFNMSUB213SHZm_Int:
11855 case VFNMSUB213SHZmk_Int:
11856 case VFNMSUB213SHZmkz_Int:
11857 case VFNMSUB213SHZr_Int:
11858 case VFNMSUB213SHZrb_Int:
11859 case VFNMSUB213SHZrbk_Int:
11860 case VFNMSUB213SHZrbkz_Int:
11861 case VFNMSUB213SHZrk_Int:
11862 case VFNMSUB213SHZrkz_Int:
11863 return true;
11864 }
11865 return false;
11866}
11867
11868bool isVCVTTPD2UQQ(unsigned Opcode) {
11869 switch (Opcode) {
11870 case VCVTTPD2UQQZ128rm:
11871 case VCVTTPD2UQQZ128rmb:
11872 case VCVTTPD2UQQZ128rmbk:
11873 case VCVTTPD2UQQZ128rmbkz:
11874 case VCVTTPD2UQQZ128rmk:
11875 case VCVTTPD2UQQZ128rmkz:
11876 case VCVTTPD2UQQZ128rr:
11877 case VCVTTPD2UQQZ128rrk:
11878 case VCVTTPD2UQQZ128rrkz:
11879 case VCVTTPD2UQQZ256rm:
11880 case VCVTTPD2UQQZ256rmb:
11881 case VCVTTPD2UQQZ256rmbk:
11882 case VCVTTPD2UQQZ256rmbkz:
11883 case VCVTTPD2UQQZ256rmk:
11884 case VCVTTPD2UQQZ256rmkz:
11885 case VCVTTPD2UQQZ256rr:
11886 case VCVTTPD2UQQZ256rrk:
11887 case VCVTTPD2UQQZ256rrkz:
11888 case VCVTTPD2UQQZrm:
11889 case VCVTTPD2UQQZrmb:
11890 case VCVTTPD2UQQZrmbk:
11891 case VCVTTPD2UQQZrmbkz:
11892 case VCVTTPD2UQQZrmk:
11893 case VCVTTPD2UQQZrmkz:
11894 case VCVTTPD2UQQZrr:
11895 case VCVTTPD2UQQZrrb:
11896 case VCVTTPD2UQQZrrbk:
11897 case VCVTTPD2UQQZrrbkz:
11898 case VCVTTPD2UQQZrrk:
11899 case VCVTTPD2UQQZrrkz:
11900 return true;
11901 }
11902 return false;
11903}
11904
11905bool isSQRTSS(unsigned Opcode) {
11906 switch (Opcode) {
11907 case SQRTSSm_Int:
11908 case SQRTSSr_Int:
11909 return true;
11910 }
11911 return false;
11912}
11913
11914bool isIMUL(unsigned Opcode) {
11915 switch (Opcode) {
11916 case IMUL16m:
11917 case IMUL16m_EVEX:
11918 case IMUL16m_NF:
11919 case IMUL16r:
11920 case IMUL16r_EVEX:
11921 case IMUL16r_NF:
11922 case IMUL16rm:
11923 case IMUL16rm_EVEX:
11924 case IMUL16rm_ND:
11925 case IMUL16rm_NF:
11926 case IMUL16rm_NF_ND:
11927 case IMUL16rmi:
11928 case IMUL16rmi8:
11929 case IMUL16rmi8_EVEX:
11930 case IMUL16rmi8_NF:
11931 case IMUL16rmi_EVEX:
11932 case IMUL16rmi_NF:
11933 case IMUL16rr:
11934 case IMUL16rr_EVEX:
11935 case IMUL16rr_ND:
11936 case IMUL16rr_NF:
11937 case IMUL16rr_NF_ND:
11938 case IMUL16rri:
11939 case IMUL16rri8:
11940 case IMUL16rri8_EVEX:
11941 case IMUL16rri8_NF:
11942 case IMUL16rri_EVEX:
11943 case IMUL16rri_NF:
11944 case IMUL32m:
11945 case IMUL32m_EVEX:
11946 case IMUL32m_NF:
11947 case IMUL32r:
11948 case IMUL32r_EVEX:
11949 case IMUL32r_NF:
11950 case IMUL32rm:
11951 case IMUL32rm_EVEX:
11952 case IMUL32rm_ND:
11953 case IMUL32rm_NF:
11954 case IMUL32rm_NF_ND:
11955 case IMUL32rmi:
11956 case IMUL32rmi8:
11957 case IMUL32rmi8_EVEX:
11958 case IMUL32rmi8_NF:
11959 case IMUL32rmi_EVEX:
11960 case IMUL32rmi_NF:
11961 case IMUL32rr:
11962 case IMUL32rr_EVEX:
11963 case IMUL32rr_ND:
11964 case IMUL32rr_NF:
11965 case IMUL32rr_NF_ND:
11966 case IMUL32rri:
11967 case IMUL32rri8:
11968 case IMUL32rri8_EVEX:
11969 case IMUL32rri8_NF:
11970 case IMUL32rri_EVEX:
11971 case IMUL32rri_NF:
11972 case IMUL64m:
11973 case IMUL64m_EVEX:
11974 case IMUL64m_NF:
11975 case IMUL64r:
11976 case IMUL64r_EVEX:
11977 case IMUL64r_NF:
11978 case IMUL64rm:
11979 case IMUL64rm_EVEX:
11980 case IMUL64rm_ND:
11981 case IMUL64rm_NF:
11982 case IMUL64rm_NF_ND:
11983 case IMUL64rmi32:
11984 case IMUL64rmi32_EVEX:
11985 case IMUL64rmi32_NF:
11986 case IMUL64rmi8:
11987 case IMUL64rmi8_EVEX:
11988 case IMUL64rmi8_NF:
11989 case IMUL64rr:
11990 case IMUL64rr_EVEX:
11991 case IMUL64rr_ND:
11992 case IMUL64rr_NF:
11993 case IMUL64rr_NF_ND:
11994 case IMUL64rri32:
11995 case IMUL64rri32_EVEX:
11996 case IMUL64rri32_NF:
11997 case IMUL64rri8:
11998 case IMUL64rri8_EVEX:
11999 case IMUL64rri8_NF:
12000 case IMUL8m:
12001 case IMUL8m_EVEX:
12002 case IMUL8m_NF:
12003 case IMUL8r:
12004 case IMUL8r_EVEX:
12005 case IMUL8r_NF:
12006 return true;
12007 }
12008 return false;
12009}
12010
12011bool isVCVTSS2SI(unsigned Opcode) {
12012 switch (Opcode) {
12013 case VCVTSS2SI64Zrm_Int:
12014 case VCVTSS2SI64Zrr_Int:
12015 case VCVTSS2SI64Zrrb_Int:
12016 case VCVTSS2SI64rm_Int:
12017 case VCVTSS2SI64rr_Int:
12018 case VCVTSS2SIZrm_Int:
12019 case VCVTSS2SIZrr_Int:
12020 case VCVTSS2SIZrrb_Int:
12021 case VCVTSS2SIrm_Int:
12022 case VCVTSS2SIrr_Int:
12023 return true;
12024 }
12025 return false;
12026}
12027
12028bool isPUSHAW(unsigned Opcode) {
12029 return Opcode == PUSHA16;
12030}
12031
12032bool isSTOSD(unsigned Opcode) {
12033 return Opcode == STOSL;
12034}
12035
12036bool isPSRLDQ(unsigned Opcode) {
12037 return Opcode == PSRLDQri;
12038}
12039
12040bool isVSCATTERQPS(unsigned Opcode) {
12041 switch (Opcode) {
12042 case VSCATTERQPSZ128mr:
12043 case VSCATTERQPSZ256mr:
12044 case VSCATTERQPSZmr:
12045 return true;
12046 }
12047 return false;
12048}
12049
12050bool isFIDIV(unsigned Opcode) {
12051 switch (Opcode) {
12052 case DIV_FI16m:
12053 case DIV_FI32m:
12054 return true;
12055 }
12056 return false;
12057}
12058
12059bool isVFMSUB213PD(unsigned Opcode) {
12060 switch (Opcode) {
12061 case VFMSUB213PDYm:
12062 case VFMSUB213PDYr:
12063 case VFMSUB213PDZ128m:
12064 case VFMSUB213PDZ128mb:
12065 case VFMSUB213PDZ128mbk:
12066 case VFMSUB213PDZ128mbkz:
12067 case VFMSUB213PDZ128mk:
12068 case VFMSUB213PDZ128mkz:
12069 case VFMSUB213PDZ128r:
12070 case VFMSUB213PDZ128rk:
12071 case VFMSUB213PDZ128rkz:
12072 case VFMSUB213PDZ256m:
12073 case VFMSUB213PDZ256mb:
12074 case VFMSUB213PDZ256mbk:
12075 case VFMSUB213PDZ256mbkz:
12076 case VFMSUB213PDZ256mk:
12077 case VFMSUB213PDZ256mkz:
12078 case VFMSUB213PDZ256r:
12079 case VFMSUB213PDZ256rk:
12080 case VFMSUB213PDZ256rkz:
12081 case VFMSUB213PDZm:
12082 case VFMSUB213PDZmb:
12083 case VFMSUB213PDZmbk:
12084 case VFMSUB213PDZmbkz:
12085 case VFMSUB213PDZmk:
12086 case VFMSUB213PDZmkz:
12087 case VFMSUB213PDZr:
12088 case VFMSUB213PDZrb:
12089 case VFMSUB213PDZrbk:
12090 case VFMSUB213PDZrbkz:
12091 case VFMSUB213PDZrk:
12092 case VFMSUB213PDZrkz:
12093 case VFMSUB213PDm:
12094 case VFMSUB213PDr:
12095 return true;
12096 }
12097 return false;
12098}
12099
12100bool isVFMADDSUB231PH(unsigned Opcode) {
12101 switch (Opcode) {
12102 case VFMADDSUB231PHZ128m:
12103 case VFMADDSUB231PHZ128mb:
12104 case VFMADDSUB231PHZ128mbk:
12105 case VFMADDSUB231PHZ128mbkz:
12106 case VFMADDSUB231PHZ128mk:
12107 case VFMADDSUB231PHZ128mkz:
12108 case VFMADDSUB231PHZ128r:
12109 case VFMADDSUB231PHZ128rk:
12110 case VFMADDSUB231PHZ128rkz:
12111 case VFMADDSUB231PHZ256m:
12112 case VFMADDSUB231PHZ256mb:
12113 case VFMADDSUB231PHZ256mbk:
12114 case VFMADDSUB231PHZ256mbkz:
12115 case VFMADDSUB231PHZ256mk:
12116 case VFMADDSUB231PHZ256mkz:
12117 case VFMADDSUB231PHZ256r:
12118 case VFMADDSUB231PHZ256rk:
12119 case VFMADDSUB231PHZ256rkz:
12120 case VFMADDSUB231PHZm:
12121 case VFMADDSUB231PHZmb:
12122 case VFMADDSUB231PHZmbk:
12123 case VFMADDSUB231PHZmbkz:
12124 case VFMADDSUB231PHZmk:
12125 case VFMADDSUB231PHZmkz:
12126 case VFMADDSUB231PHZr:
12127 case VFMADDSUB231PHZrb:
12128 case VFMADDSUB231PHZrbk:
12129 case VFMADDSUB231PHZrbkz:
12130 case VFMADDSUB231PHZrk:
12131 case VFMADDSUB231PHZrkz:
12132 return true;
12133 }
12134 return false;
12135}
12136
12137bool isTDCALL(unsigned Opcode) {
12138 return Opcode == TDCALL;
12139}
12140
12141bool isPVALIDATE(unsigned Opcode) {
12142 switch (Opcode) {
12143 case PVALIDATE32:
12144 case PVALIDATE64:
12145 return true;
12146 }
12147 return false;
12148}
12149
12150bool isVPSHUFLW(unsigned Opcode) {
12151 switch (Opcode) {
12152 case VPSHUFLWYmi:
12153 case VPSHUFLWYri:
12154 case VPSHUFLWZ128mi:
12155 case VPSHUFLWZ128mik:
12156 case VPSHUFLWZ128mikz:
12157 case VPSHUFLWZ128ri:
12158 case VPSHUFLWZ128rik:
12159 case VPSHUFLWZ128rikz:
12160 case VPSHUFLWZ256mi:
12161 case VPSHUFLWZ256mik:
12162 case VPSHUFLWZ256mikz:
12163 case VPSHUFLWZ256ri:
12164 case VPSHUFLWZ256rik:
12165 case VPSHUFLWZ256rikz:
12166 case VPSHUFLWZmi:
12167 case VPSHUFLWZmik:
12168 case VPSHUFLWZmikz:
12169 case VPSHUFLWZri:
12170 case VPSHUFLWZrik:
12171 case VPSHUFLWZrikz:
12172 case VPSHUFLWmi:
12173 case VPSHUFLWri:
12174 return true;
12175 }
12176 return false;
12177}
12178
12179bool isPCLMULQDQ(unsigned Opcode) {
12180 switch (Opcode) {
12181 case PCLMULQDQrmi:
12182 case PCLMULQDQrri:
12183 return true;
12184 }
12185 return false;
12186}
12187
12188bool isCMPXCHG8B(unsigned Opcode) {
12189 return Opcode == CMPXCHG8B;
12190}
12191
12192bool isVPMOVM2B(unsigned Opcode) {
12193 switch (Opcode) {
12194 case VPMOVM2BZ128rk:
12195 case VPMOVM2BZ256rk:
12196 case VPMOVM2BZrk:
12197 return true;
12198 }
12199 return false;
12200}
12201
12202bool isVCVTUDQ2PH(unsigned Opcode) {
12203 switch (Opcode) {
12204 case VCVTUDQ2PHZ128rm:
12205 case VCVTUDQ2PHZ128rmb:
12206 case VCVTUDQ2PHZ128rmbk:
12207 case VCVTUDQ2PHZ128rmbkz:
12208 case VCVTUDQ2PHZ128rmk:
12209 case VCVTUDQ2PHZ128rmkz:
12210 case VCVTUDQ2PHZ128rr:
12211 case VCVTUDQ2PHZ128rrk:
12212 case VCVTUDQ2PHZ128rrkz:
12213 case VCVTUDQ2PHZ256rm:
12214 case VCVTUDQ2PHZ256rmb:
12215 case VCVTUDQ2PHZ256rmbk:
12216 case VCVTUDQ2PHZ256rmbkz:
12217 case VCVTUDQ2PHZ256rmk:
12218 case VCVTUDQ2PHZ256rmkz:
12219 case VCVTUDQ2PHZ256rr:
12220 case VCVTUDQ2PHZ256rrk:
12221 case VCVTUDQ2PHZ256rrkz:
12222 case VCVTUDQ2PHZrm:
12223 case VCVTUDQ2PHZrmb:
12224 case VCVTUDQ2PHZrmbk:
12225 case VCVTUDQ2PHZrmbkz:
12226 case VCVTUDQ2PHZrmk:
12227 case VCVTUDQ2PHZrmkz:
12228 case VCVTUDQ2PHZrr:
12229 case VCVTUDQ2PHZrrb:
12230 case VCVTUDQ2PHZrrbk:
12231 case VCVTUDQ2PHZrrbkz:
12232 case VCVTUDQ2PHZrrk:
12233 case VCVTUDQ2PHZrrkz:
12234 return true;
12235 }
12236 return false;
12237}
12238
12239bool isPEXTRQ(unsigned Opcode) {
12240 switch (Opcode) {
12241 case PEXTRQmri:
12242 case PEXTRQrri:
12243 return true;
12244 }
12245 return false;
12246}
12247
12248bool isXCRYPTCTR(unsigned Opcode) {
12249 return Opcode == XCRYPTCTR;
12250}
12251
12252bool isVREDUCEPH(unsigned Opcode) {
12253 switch (Opcode) {
12254 case VREDUCEPHZ128rmbi:
12255 case VREDUCEPHZ128rmbik:
12256 case VREDUCEPHZ128rmbikz:
12257 case VREDUCEPHZ128rmi:
12258 case VREDUCEPHZ128rmik:
12259 case VREDUCEPHZ128rmikz:
12260 case VREDUCEPHZ128rri:
12261 case VREDUCEPHZ128rrik:
12262 case VREDUCEPHZ128rrikz:
12263 case VREDUCEPHZ256rmbi:
12264 case VREDUCEPHZ256rmbik:
12265 case VREDUCEPHZ256rmbikz:
12266 case VREDUCEPHZ256rmi:
12267 case VREDUCEPHZ256rmik:
12268 case VREDUCEPHZ256rmikz:
12269 case VREDUCEPHZ256rri:
12270 case VREDUCEPHZ256rrik:
12271 case VREDUCEPHZ256rrikz:
12272 case VREDUCEPHZrmbi:
12273 case VREDUCEPHZrmbik:
12274 case VREDUCEPHZrmbikz:
12275 case VREDUCEPHZrmi:
12276 case VREDUCEPHZrmik:
12277 case VREDUCEPHZrmikz:
12278 case VREDUCEPHZrri:
12279 case VREDUCEPHZrrib:
12280 case VREDUCEPHZrribk:
12281 case VREDUCEPHZrribkz:
12282 case VREDUCEPHZrrik:
12283 case VREDUCEPHZrrikz:
12284 return true;
12285 }
12286 return false;
12287}
12288
12289bool isUCOMISD(unsigned Opcode) {
12290 switch (Opcode) {
12291 case UCOMISDrm:
12292 case UCOMISDrr:
12293 return true;
12294 }
12295 return false;
12296}
12297
12298bool isOUTSD(unsigned Opcode) {
12299 return Opcode == OUTSL;
12300}
12301
12302bool isSUBSS(unsigned Opcode) {
12303 switch (Opcode) {
12304 case SUBSSrm_Int:
12305 case SUBSSrr_Int:
12306 return true;
12307 }
12308 return false;
12309}
12310
12311bool isVFMSUBPS(unsigned Opcode) {
12312 switch (Opcode) {
12313 case VFMSUBPS4Ymr:
12314 case VFMSUBPS4Yrm:
12315 case VFMSUBPS4Yrr:
12316 case VFMSUBPS4Yrr_REV:
12317 case VFMSUBPS4mr:
12318 case VFMSUBPS4rm:
12319 case VFMSUBPS4rr:
12320 case VFMSUBPS4rr_REV:
12321 return true;
12322 }
12323 return false;
12324}
12325
12326bool isVPBLENDW(unsigned Opcode) {
12327 switch (Opcode) {
12328 case VPBLENDWYrmi:
12329 case VPBLENDWYrri:
12330 case VPBLENDWrmi:
12331 case VPBLENDWrri:
12332 return true;
12333 }
12334 return false;
12335}
12336
12337bool isVPEXPANDB(unsigned Opcode) {
12338 switch (Opcode) {
12339 case VPEXPANDBZ128rm:
12340 case VPEXPANDBZ128rmk:
12341 case VPEXPANDBZ128rmkz:
12342 case VPEXPANDBZ128rr:
12343 case VPEXPANDBZ128rrk:
12344 case VPEXPANDBZ128rrkz:
12345 case VPEXPANDBZ256rm:
12346 case VPEXPANDBZ256rmk:
12347 case VPEXPANDBZ256rmkz:
12348 case VPEXPANDBZ256rr:
12349 case VPEXPANDBZ256rrk:
12350 case VPEXPANDBZ256rrkz:
12351 case VPEXPANDBZrm:
12352 case VPEXPANDBZrmk:
12353 case VPEXPANDBZrmkz:
12354 case VPEXPANDBZrr:
12355 case VPEXPANDBZrrk:
12356 case VPEXPANDBZrrkz:
12357 return true;
12358 }
12359 return false;
12360}
12361
12362bool isBZHI(unsigned Opcode) {
12363 switch (Opcode) {
12364 case BZHI32rm:
12365 case BZHI32rm_EVEX:
12366 case BZHI32rm_NF:
12367 case BZHI32rr:
12368 case BZHI32rr_EVEX:
12369 case BZHI32rr_NF:
12370 case BZHI64rm:
12371 case BZHI64rm_EVEX:
12372 case BZHI64rm_NF:
12373 case BZHI64rr:
12374 case BZHI64rr_EVEX:
12375 case BZHI64rr_NF:
12376 return true;
12377 }
12378 return false;
12379}
12380
12381bool isVPRORVD(unsigned Opcode) {
12382 switch (Opcode) {
12383 case VPRORVDZ128rm:
12384 case VPRORVDZ128rmb:
12385 case VPRORVDZ128rmbk:
12386 case VPRORVDZ128rmbkz:
12387 case VPRORVDZ128rmk:
12388 case VPRORVDZ128rmkz:
12389 case VPRORVDZ128rr:
12390 case VPRORVDZ128rrk:
12391 case VPRORVDZ128rrkz:
12392 case VPRORVDZ256rm:
12393 case VPRORVDZ256rmb:
12394 case VPRORVDZ256rmbk:
12395 case VPRORVDZ256rmbkz:
12396 case VPRORVDZ256rmk:
12397 case VPRORVDZ256rmkz:
12398 case VPRORVDZ256rr:
12399 case VPRORVDZ256rrk:
12400 case VPRORVDZ256rrkz:
12401 case VPRORVDZrm:
12402 case VPRORVDZrmb:
12403 case VPRORVDZrmbk:
12404 case VPRORVDZrmbkz:
12405 case VPRORVDZrmk:
12406 case VPRORVDZrmkz:
12407 case VPRORVDZrr:
12408 case VPRORVDZrrk:
12409 case VPRORVDZrrkz:
12410 return true;
12411 }
12412 return false;
12413}
12414
12415bool isRMPQUERY(unsigned Opcode) {
12416 return Opcode == RMPQUERY;
12417}
12418
12419bool isVPSCATTERDQ(unsigned Opcode) {
12420 switch (Opcode) {
12421 case VPSCATTERDQZ128mr:
12422 case VPSCATTERDQZ256mr:
12423 case VPSCATTERDQZmr:
12424 return true;
12425 }
12426 return false;
12427}
12428
12429bool isPSMASH(unsigned Opcode) {
12430 return Opcode == PSMASH;
12431}
12432
12433bool isVPSHLDQ(unsigned Opcode) {
12434 switch (Opcode) {
12435 case VPSHLDQZ128rmbi:
12436 case VPSHLDQZ128rmbik:
12437 case VPSHLDQZ128rmbikz:
12438 case VPSHLDQZ128rmi:
12439 case VPSHLDQZ128rmik:
12440 case VPSHLDQZ128rmikz:
12441 case VPSHLDQZ128rri:
12442 case VPSHLDQZ128rrik:
12443 case VPSHLDQZ128rrikz:
12444 case VPSHLDQZ256rmbi:
12445 case VPSHLDQZ256rmbik:
12446 case VPSHLDQZ256rmbikz:
12447 case VPSHLDQZ256rmi:
12448 case VPSHLDQZ256rmik:
12449 case VPSHLDQZ256rmikz:
12450 case VPSHLDQZ256rri:
12451 case VPSHLDQZ256rrik:
12452 case VPSHLDQZ256rrikz:
12453 case VPSHLDQZrmbi:
12454 case VPSHLDQZrmbik:
12455 case VPSHLDQZrmbikz:
12456 case VPSHLDQZrmi:
12457 case VPSHLDQZrmik:
12458 case VPSHLDQZrmikz:
12459 case VPSHLDQZrri:
12460 case VPSHLDQZrrik:
12461 case VPSHLDQZrrikz:
12462 return true;
12463 }
12464 return false;
12465}
12466
12467bool isVSCATTERPF1DPD(unsigned Opcode) {
12468 return Opcode == VSCATTERPF1DPDm;
12469}
12470
12471bool isMONTMUL(unsigned Opcode) {
12472 return Opcode == MONTMUL;
12473}
12474
12475bool isVCVTPH2UQQ(unsigned Opcode) {
12476 switch (Opcode) {
12477 case VCVTPH2UQQZ128rm:
12478 case VCVTPH2UQQZ128rmb:
12479 case VCVTPH2UQQZ128rmbk:
12480 case VCVTPH2UQQZ128rmbkz:
12481 case VCVTPH2UQQZ128rmk:
12482 case VCVTPH2UQQZ128rmkz:
12483 case VCVTPH2UQQZ128rr:
12484 case VCVTPH2UQQZ128rrk:
12485 case VCVTPH2UQQZ128rrkz:
12486 case VCVTPH2UQQZ256rm:
12487 case VCVTPH2UQQZ256rmb:
12488 case VCVTPH2UQQZ256rmbk:
12489 case VCVTPH2UQQZ256rmbkz:
12490 case VCVTPH2UQQZ256rmk:
12491 case VCVTPH2UQQZ256rmkz:
12492 case VCVTPH2UQQZ256rr:
12493 case VCVTPH2UQQZ256rrk:
12494 case VCVTPH2UQQZ256rrkz:
12495 case VCVTPH2UQQZrm:
12496 case VCVTPH2UQQZrmb:
12497 case VCVTPH2UQQZrmbk:
12498 case VCVTPH2UQQZrmbkz:
12499 case VCVTPH2UQQZrmk:
12500 case VCVTPH2UQQZrmkz:
12501 case VCVTPH2UQQZrr:
12502 case VCVTPH2UQQZrrb:
12503 case VCVTPH2UQQZrrbk:
12504 case VCVTPH2UQQZrrbkz:
12505 case VCVTPH2UQQZrrk:
12506 case VCVTPH2UQQZrrkz:
12507 return true;
12508 }
12509 return false;
12510}
12511
12512bool isPSLLD(unsigned Opcode) {
12513 switch (Opcode) {
12514 case MMX_PSLLDri:
12515 case MMX_PSLLDrm:
12516 case MMX_PSLLDrr:
12517 case PSLLDri:
12518 case PSLLDrm:
12519 case PSLLDrr:
12520 return true;
12521 }
12522 return false;
12523}
12524
12525bool isSAR(unsigned Opcode) {
12526 switch (Opcode) {
12527 case SAR16m1:
12528 case SAR16m1_EVEX:
12529 case SAR16m1_ND:
12530 case SAR16m1_NF:
12531 case SAR16m1_NF_ND:
12532 case SAR16mCL:
12533 case SAR16mCL_EVEX:
12534 case SAR16mCL_ND:
12535 case SAR16mCL_NF:
12536 case SAR16mCL_NF_ND:
12537 case SAR16mi:
12538 case SAR16mi_EVEX:
12539 case SAR16mi_ND:
12540 case SAR16mi_NF:
12541 case SAR16mi_NF_ND:
12542 case SAR16r1:
12543 case SAR16r1_EVEX:
12544 case SAR16r1_ND:
12545 case SAR16r1_NF:
12546 case SAR16r1_NF_ND:
12547 case SAR16rCL:
12548 case SAR16rCL_EVEX:
12549 case SAR16rCL_ND:
12550 case SAR16rCL_NF:
12551 case SAR16rCL_NF_ND:
12552 case SAR16ri:
12553 case SAR16ri_EVEX:
12554 case SAR16ri_ND:
12555 case SAR16ri_NF:
12556 case SAR16ri_NF_ND:
12557 case SAR32m1:
12558 case SAR32m1_EVEX:
12559 case SAR32m1_ND:
12560 case SAR32m1_NF:
12561 case SAR32m1_NF_ND:
12562 case SAR32mCL:
12563 case SAR32mCL_EVEX:
12564 case SAR32mCL_ND:
12565 case SAR32mCL_NF:
12566 case SAR32mCL_NF_ND:
12567 case SAR32mi:
12568 case SAR32mi_EVEX:
12569 case SAR32mi_ND:
12570 case SAR32mi_NF:
12571 case SAR32mi_NF_ND:
12572 case SAR32r1:
12573 case SAR32r1_EVEX:
12574 case SAR32r1_ND:
12575 case SAR32r1_NF:
12576 case SAR32r1_NF_ND:
12577 case SAR32rCL:
12578 case SAR32rCL_EVEX:
12579 case SAR32rCL_ND:
12580 case SAR32rCL_NF:
12581 case SAR32rCL_NF_ND:
12582 case SAR32ri:
12583 case SAR32ri_EVEX:
12584 case SAR32ri_ND:
12585 case SAR32ri_NF:
12586 case SAR32ri_NF_ND:
12587 case SAR64m1:
12588 case SAR64m1_EVEX:
12589 case SAR64m1_ND:
12590 case SAR64m1_NF:
12591 case SAR64m1_NF_ND:
12592 case SAR64mCL:
12593 case SAR64mCL_EVEX:
12594 case SAR64mCL_ND:
12595 case SAR64mCL_NF:
12596 case SAR64mCL_NF_ND:
12597 case SAR64mi:
12598 case SAR64mi_EVEX:
12599 case SAR64mi_ND:
12600 case SAR64mi_NF:
12601 case SAR64mi_NF_ND:
12602 case SAR64r1:
12603 case SAR64r1_EVEX:
12604 case SAR64r1_ND:
12605 case SAR64r1_NF:
12606 case SAR64r1_NF_ND:
12607 case SAR64rCL:
12608 case SAR64rCL_EVEX:
12609 case SAR64rCL_ND:
12610 case SAR64rCL_NF:
12611 case SAR64rCL_NF_ND:
12612 case SAR64ri:
12613 case SAR64ri_EVEX:
12614 case SAR64ri_ND:
12615 case SAR64ri_NF:
12616 case SAR64ri_NF_ND:
12617 case SAR8m1:
12618 case SAR8m1_EVEX:
12619 case SAR8m1_ND:
12620 case SAR8m1_NF:
12621 case SAR8m1_NF_ND:
12622 case SAR8mCL:
12623 case SAR8mCL_EVEX:
12624 case SAR8mCL_ND:
12625 case SAR8mCL_NF:
12626 case SAR8mCL_NF_ND:
12627 case SAR8mi:
12628 case SAR8mi_EVEX:
12629 case SAR8mi_ND:
12630 case SAR8mi_NF:
12631 case SAR8mi_NF_ND:
12632 case SAR8r1:
12633 case SAR8r1_EVEX:
12634 case SAR8r1_ND:
12635 case SAR8r1_NF:
12636 case SAR8r1_NF_ND:
12637 case SAR8rCL:
12638 case SAR8rCL_EVEX:
12639 case SAR8rCL_ND:
12640 case SAR8rCL_NF:
12641 case SAR8rCL_NF_ND:
12642 case SAR8ri:
12643 case SAR8ri_EVEX:
12644 case SAR8ri_ND:
12645 case SAR8ri_NF:
12646 case SAR8ri_NF_ND:
12647 return true;
12648 }
12649 return false;
12650}
12651
12652bool isLDTILECFG(unsigned Opcode) {
12653 switch (Opcode) {
12654 case LDTILECFG:
12655 case LDTILECFG_EVEX:
12656 return true;
12657 }
12658 return false;
12659}
12660
12661bool isPMINUB(unsigned Opcode) {
12662 switch (Opcode) {
12663 case MMX_PMINUBrm:
12664 case MMX_PMINUBrr:
12665 case PMINUBrm:
12666 case PMINUBrr:
12667 return true;
12668 }
12669 return false;
12670}
12671
12672bool isVCVTNEEBF162PS(unsigned Opcode) {
12673 switch (Opcode) {
12674 case VCVTNEEBF162PSYrm:
12675 case VCVTNEEBF162PSrm:
12676 return true;
12677 }
12678 return false;
12679}
12680
12681bool isMOVDIR64B(unsigned Opcode) {
12682 switch (Opcode) {
12683 case MOVDIR64B16:
12684 case MOVDIR64B32:
12685 case MOVDIR64B32_EVEX:
12686 case MOVDIR64B64:
12687 case MOVDIR64B64_EVEX:
12688 return true;
12689 }
12690 return false;
12691}
12692
12693bool isSQRTPS(unsigned Opcode) {
12694 switch (Opcode) {
12695 case SQRTPSm:
12696 case SQRTPSr:
12697 return true;
12698 }
12699 return false;
12700}
12701
12702bool isSTR(unsigned Opcode) {
12703 switch (Opcode) {
12704 case STR16r:
12705 case STR32r:
12706 case STR64r:
12707 case STRm:
12708 return true;
12709 }
12710 return false;
12711}
12712
12713bool isKANDNQ(unsigned Opcode) {
12714 return Opcode == KANDNQkk;
12715}
12716
12717bool isBSF(unsigned Opcode) {
12718 switch (Opcode) {
12719 case BSF16rm:
12720 case BSF16rr:
12721 case BSF32rm:
12722 case BSF32rr:
12723 case BSF64rm:
12724 case BSF64rr:
12725 return true;
12726 }
12727 return false;
12728}
12729
12730bool isINCSSPD(unsigned Opcode) {
12731 return Opcode == INCSSPD;
12732}
12733
12734bool isVPDPBUUDS(unsigned Opcode) {
12735 switch (Opcode) {
12736 case VPDPBUUDSYrm:
12737 case VPDPBUUDSYrr:
12738 case VPDPBUUDSZ128rm:
12739 case VPDPBUUDSZ128rmb:
12740 case VPDPBUUDSZ128rmbk:
12741 case VPDPBUUDSZ128rmbkz:
12742 case VPDPBUUDSZ128rmk:
12743 case VPDPBUUDSZ128rmkz:
12744 case VPDPBUUDSZ128rr:
12745 case VPDPBUUDSZ128rrk:
12746 case VPDPBUUDSZ128rrkz:
12747 case VPDPBUUDSZ256rm:
12748 case VPDPBUUDSZ256rmb:
12749 case VPDPBUUDSZ256rmbk:
12750 case VPDPBUUDSZ256rmbkz:
12751 case VPDPBUUDSZ256rmk:
12752 case VPDPBUUDSZ256rmkz:
12753 case VPDPBUUDSZ256rr:
12754 case VPDPBUUDSZ256rrk:
12755 case VPDPBUUDSZ256rrkz:
12756 case VPDPBUUDSZrm:
12757 case VPDPBUUDSZrmb:
12758 case VPDPBUUDSZrmbk:
12759 case VPDPBUUDSZrmbkz:
12760 case VPDPBUUDSZrmk:
12761 case VPDPBUUDSZrmkz:
12762 case VPDPBUUDSZrr:
12763 case VPDPBUUDSZrrk:
12764 case VPDPBUUDSZrrkz:
12765 case VPDPBUUDSrm:
12766 case VPDPBUUDSrr:
12767 return true;
12768 }
12769 return false;
12770}
12771
12772bool isCMPXCHG(unsigned Opcode) {
12773 switch (Opcode) {
12774 case CMPXCHG16rm:
12775 case CMPXCHG16rr:
12776 case CMPXCHG32rm:
12777 case CMPXCHG32rr:
12778 case CMPXCHG64rm:
12779 case CMPXCHG64rr:
12780 case CMPXCHG8rm:
12781 case CMPXCHG8rr:
12782 return true;
12783 }
12784 return false;
12785}
12786
12787bool isVPSIGNW(unsigned Opcode) {
12788 switch (Opcode) {
12789 case VPSIGNWYrm:
12790 case VPSIGNWYrr:
12791 case VPSIGNWrm:
12792 case VPSIGNWrr:
12793 return true;
12794 }
12795 return false;
12796}
12797
12798bool isVCOMISBF16(unsigned Opcode) {
12799 switch (Opcode) {
12800 case VCOMISBF16Zrm:
12801 case VCOMISBF16Zrr:
12802 return true;
12803 }
12804 return false;
12805}
12806
12807bool isLES(unsigned Opcode) {
12808 switch (Opcode) {
12809 case LES16rm:
12810 case LES32rm:
12811 return true;
12812 }
12813 return false;
12814}
12815
12816bool isCVTSS2SI(unsigned Opcode) {
12817 switch (Opcode) {
12818 case CVTSS2SI64rm_Int:
12819 case CVTSS2SI64rr_Int:
12820 case CVTSS2SIrm_Int:
12821 case CVTSS2SIrr_Int:
12822 return true;
12823 }
12824 return false;
12825}
12826
12827bool isPFACC(unsigned Opcode) {
12828 switch (Opcode) {
12829 case PFACCrm:
12830 case PFACCrr:
12831 return true;
12832 }
12833 return false;
12834}
12835
12836bool isFCOMPI(unsigned Opcode) {
12837 return Opcode == COM_FIPr;
12838}
12839
12840bool isPUNPCKHWD(unsigned Opcode) {
12841 switch (Opcode) {
12842 case MMX_PUNPCKHWDrm:
12843 case MMX_PUNPCKHWDrr:
12844 case PUNPCKHWDrm:
12845 case PUNPCKHWDrr:
12846 return true;
12847 }
12848 return false;
12849}
12850
12851bool isVPMOVUSWB(unsigned Opcode) {
12852 switch (Opcode) {
12853 case VPMOVUSWBZ128mr:
12854 case VPMOVUSWBZ128mrk:
12855 case VPMOVUSWBZ128rr:
12856 case VPMOVUSWBZ128rrk:
12857 case VPMOVUSWBZ128rrkz:
12858 case VPMOVUSWBZ256mr:
12859 case VPMOVUSWBZ256mrk:
12860 case VPMOVUSWBZ256rr:
12861 case VPMOVUSWBZ256rrk:
12862 case VPMOVUSWBZ256rrkz:
12863 case VPMOVUSWBZmr:
12864 case VPMOVUSWBZmrk:
12865 case VPMOVUSWBZrr:
12866 case VPMOVUSWBZrrk:
12867 case VPMOVUSWBZrrkz:
12868 return true;
12869 }
12870 return false;
12871}
12872
12873bool isVPTESTNMW(unsigned Opcode) {
12874 switch (Opcode) {
12875 case VPTESTNMWZ128rm:
12876 case VPTESTNMWZ128rmk:
12877 case VPTESTNMWZ128rr:
12878 case VPTESTNMWZ128rrk:
12879 case VPTESTNMWZ256rm:
12880 case VPTESTNMWZ256rmk:
12881 case VPTESTNMWZ256rr:
12882 case VPTESTNMWZ256rrk:
12883 case VPTESTNMWZrm:
12884 case VPTESTNMWZrmk:
12885 case VPTESTNMWZrr:
12886 case VPTESTNMWZrrk:
12887 return true;
12888 }
12889 return false;
12890}
12891
12892bool isVPMULDQ(unsigned Opcode) {
12893 switch (Opcode) {
12894 case VPMULDQYrm:
12895 case VPMULDQYrr:
12896 case VPMULDQZ128rm:
12897 case VPMULDQZ128rmb:
12898 case VPMULDQZ128rmbk:
12899 case VPMULDQZ128rmbkz:
12900 case VPMULDQZ128rmk:
12901 case VPMULDQZ128rmkz:
12902 case VPMULDQZ128rr:
12903 case VPMULDQZ128rrk:
12904 case VPMULDQZ128rrkz:
12905 case VPMULDQZ256rm:
12906 case VPMULDQZ256rmb:
12907 case VPMULDQZ256rmbk:
12908 case VPMULDQZ256rmbkz:
12909 case VPMULDQZ256rmk:
12910 case VPMULDQZ256rmkz:
12911 case VPMULDQZ256rr:
12912 case VPMULDQZ256rrk:
12913 case VPMULDQZ256rrkz:
12914 case VPMULDQZrm:
12915 case VPMULDQZrmb:
12916 case VPMULDQZrmbk:
12917 case VPMULDQZrmbkz:
12918 case VPMULDQZrmk:
12919 case VPMULDQZrmkz:
12920 case VPMULDQZrr:
12921 case VPMULDQZrrk:
12922 case VPMULDQZrrkz:
12923 case VPMULDQrm:
12924 case VPMULDQrr:
12925 return true;
12926 }
12927 return false;
12928}
12929
12930bool isSHRX(unsigned Opcode) {
12931 switch (Opcode) {
12932 case SHRX32rm:
12933 case SHRX32rm_EVEX:
12934 case SHRX32rr:
12935 case SHRX32rr_EVEX:
12936 case SHRX64rm:
12937 case SHRX64rm_EVEX:
12938 case SHRX64rr:
12939 case SHRX64rr_EVEX:
12940 return true;
12941 }
12942 return false;
12943}
12944
12945bool isKXORQ(unsigned Opcode) {
12946 return Opcode == KXORQkk;
12947}
12948
12949bool isVGETEXPSD(unsigned Opcode) {
12950 switch (Opcode) {
12951 case VGETEXPSDZm:
12952 case VGETEXPSDZmk:
12953 case VGETEXPSDZmkz:
12954 case VGETEXPSDZr:
12955 case VGETEXPSDZrb:
12956 case VGETEXPSDZrbk:
12957 case VGETEXPSDZrbkz:
12958 case VGETEXPSDZrk:
12959 case VGETEXPSDZrkz:
12960 return true;
12961 }
12962 return false;
12963}
12964
12965bool isV4FNMADDPS(unsigned Opcode) {
12966 switch (Opcode) {
12967 case V4FNMADDPSrm:
12968 case V4FNMADDPSrmk:
12969 case V4FNMADDPSrmkz:
12970 return true;
12971 }
12972 return false;
12973}
12974
12975bool isVFNMSUB231SD(unsigned Opcode) {
12976 switch (Opcode) {
12977 case VFNMSUB231SDZm_Int:
12978 case VFNMSUB231SDZmk_Int:
12979 case VFNMSUB231SDZmkz_Int:
12980 case VFNMSUB231SDZr_Int:
12981 case VFNMSUB231SDZrb_Int:
12982 case VFNMSUB231SDZrbk_Int:
12983 case VFNMSUB231SDZrbkz_Int:
12984 case VFNMSUB231SDZrk_Int:
12985 case VFNMSUB231SDZrkz_Int:
12986 case VFNMSUB231SDm_Int:
12987 case VFNMSUB231SDr_Int:
12988 return true;
12989 }
12990 return false;
12991}
12992
12993bool isVPSHLD(unsigned Opcode) {
12994 switch (Opcode) {
12995 case VPSHLDmr:
12996 case VPSHLDrm:
12997 case VPSHLDrr:
12998 case VPSHLDrr_REV:
12999 return true;
13000 }
13001 return false;
13002}
13003
13004bool isPAVGB(unsigned Opcode) {
13005 switch (Opcode) {
13006 case MMX_PAVGBrm:
13007 case MMX_PAVGBrr:
13008 case PAVGBrm:
13009 case PAVGBrr:
13010 return true;
13011 }
13012 return false;
13013}
13014
13015bool isPMOVZXBD(unsigned Opcode) {
13016 switch (Opcode) {
13017 case PMOVZXBDrm:
13018 case PMOVZXBDrr:
13019 return true;
13020 }
13021 return false;
13022}
13023
13024bool isKORTESTW(unsigned Opcode) {
13025 return Opcode == KORTESTWkk;
13026}
13027
13028bool isVSHUFPS(unsigned Opcode) {
13029 switch (Opcode) {
13030 case VSHUFPSYrmi:
13031 case VSHUFPSYrri:
13032 case VSHUFPSZ128rmbi:
13033 case VSHUFPSZ128rmbik:
13034 case VSHUFPSZ128rmbikz:
13035 case VSHUFPSZ128rmi:
13036 case VSHUFPSZ128rmik:
13037 case VSHUFPSZ128rmikz:
13038 case VSHUFPSZ128rri:
13039 case VSHUFPSZ128rrik:
13040 case VSHUFPSZ128rrikz:
13041 case VSHUFPSZ256rmbi:
13042 case VSHUFPSZ256rmbik:
13043 case VSHUFPSZ256rmbikz:
13044 case VSHUFPSZ256rmi:
13045 case VSHUFPSZ256rmik:
13046 case VSHUFPSZ256rmikz:
13047 case VSHUFPSZ256rri:
13048 case VSHUFPSZ256rrik:
13049 case VSHUFPSZ256rrikz:
13050 case VSHUFPSZrmbi:
13051 case VSHUFPSZrmbik:
13052 case VSHUFPSZrmbikz:
13053 case VSHUFPSZrmi:
13054 case VSHUFPSZrmik:
13055 case VSHUFPSZrmikz:
13056 case VSHUFPSZrri:
13057 case VSHUFPSZrrik:
13058 case VSHUFPSZrrikz:
13059 case VSHUFPSrmi:
13060 case VSHUFPSrri:
13061 return true;
13062 }
13063 return false;
13064}
13065
13066bool isAESENCWIDE128KL(unsigned Opcode) {
13067 return Opcode == AESENCWIDE128KL;
13068}
13069
13070bool isVPXORD(unsigned Opcode) {
13071 switch (Opcode) {
13072 case VPXORDZ128rm:
13073 case VPXORDZ128rmb:
13074 case VPXORDZ128rmbk:
13075 case VPXORDZ128rmbkz:
13076 case VPXORDZ128rmk:
13077 case VPXORDZ128rmkz:
13078 case VPXORDZ128rr:
13079 case VPXORDZ128rrk:
13080 case VPXORDZ128rrkz:
13081 case VPXORDZ256rm:
13082 case VPXORDZ256rmb:
13083 case VPXORDZ256rmbk:
13084 case VPXORDZ256rmbkz:
13085 case VPXORDZ256rmk:
13086 case VPXORDZ256rmkz:
13087 case VPXORDZ256rr:
13088 case VPXORDZ256rrk:
13089 case VPXORDZ256rrkz:
13090 case VPXORDZrm:
13091 case VPXORDZrmb:
13092 case VPXORDZrmbk:
13093 case VPXORDZrmbkz:
13094 case VPXORDZrmk:
13095 case VPXORDZrmkz:
13096 case VPXORDZrr:
13097 case VPXORDZrrk:
13098 case VPXORDZrrkz:
13099 return true;
13100 }
13101 return false;
13102}
13103
13104bool isVPSHAW(unsigned Opcode) {
13105 switch (Opcode) {
13106 case VPSHAWmr:
13107 case VPSHAWrm:
13108 case VPSHAWrr:
13109 case VPSHAWrr_REV:
13110 return true;
13111 }
13112 return false;
13113}
13114
13115bool isVFMSUB132BF16(unsigned Opcode) {
13116 switch (Opcode) {
13117 case VFMSUB132BF16Z128m:
13118 case VFMSUB132BF16Z128mb:
13119 case VFMSUB132BF16Z128mbk:
13120 case VFMSUB132BF16Z128mbkz:
13121 case VFMSUB132BF16Z128mk:
13122 case VFMSUB132BF16Z128mkz:
13123 case VFMSUB132BF16Z128r:
13124 case VFMSUB132BF16Z128rk:
13125 case VFMSUB132BF16Z128rkz:
13126 case VFMSUB132BF16Z256m:
13127 case VFMSUB132BF16Z256mb:
13128 case VFMSUB132BF16Z256mbk:
13129 case VFMSUB132BF16Z256mbkz:
13130 case VFMSUB132BF16Z256mk:
13131 case VFMSUB132BF16Z256mkz:
13132 case VFMSUB132BF16Z256r:
13133 case VFMSUB132BF16Z256rk:
13134 case VFMSUB132BF16Z256rkz:
13135 case VFMSUB132BF16Zm:
13136 case VFMSUB132BF16Zmb:
13137 case VFMSUB132BF16Zmbk:
13138 case VFMSUB132BF16Zmbkz:
13139 case VFMSUB132BF16Zmk:
13140 case VFMSUB132BF16Zmkz:
13141 case VFMSUB132BF16Zr:
13142 case VFMSUB132BF16Zrk:
13143 case VFMSUB132BF16Zrkz:
13144 return true;
13145 }
13146 return false;
13147}
13148
13149bool isVPERMT2B(unsigned Opcode) {
13150 switch (Opcode) {
13151 case VPERMT2BZ128rm:
13152 case VPERMT2BZ128rmk:
13153 case VPERMT2BZ128rmkz:
13154 case VPERMT2BZ128rr:
13155 case VPERMT2BZ128rrk:
13156 case VPERMT2BZ128rrkz:
13157 case VPERMT2BZ256rm:
13158 case VPERMT2BZ256rmk:
13159 case VPERMT2BZ256rmkz:
13160 case VPERMT2BZ256rr:
13161 case VPERMT2BZ256rrk:
13162 case VPERMT2BZ256rrkz:
13163 case VPERMT2BZrm:
13164 case VPERMT2BZrmk:
13165 case VPERMT2BZrmkz:
13166 case VPERMT2BZrr:
13167 case VPERMT2BZrrk:
13168 case VPERMT2BZrrkz:
13169 return true;
13170 }
13171 return false;
13172}
13173
13174bool isVFMADD213PD(unsigned Opcode) {
13175 switch (Opcode) {
13176 case VFMADD213PDYm:
13177 case VFMADD213PDYr:
13178 case VFMADD213PDZ128m:
13179 case VFMADD213PDZ128mb:
13180 case VFMADD213PDZ128mbk:
13181 case VFMADD213PDZ128mbkz:
13182 case VFMADD213PDZ128mk:
13183 case VFMADD213PDZ128mkz:
13184 case VFMADD213PDZ128r:
13185 case VFMADD213PDZ128rk:
13186 case VFMADD213PDZ128rkz:
13187 case VFMADD213PDZ256m:
13188 case VFMADD213PDZ256mb:
13189 case VFMADD213PDZ256mbk:
13190 case VFMADD213PDZ256mbkz:
13191 case VFMADD213PDZ256mk:
13192 case VFMADD213PDZ256mkz:
13193 case VFMADD213PDZ256r:
13194 case VFMADD213PDZ256rk:
13195 case VFMADD213PDZ256rkz:
13196 case VFMADD213PDZm:
13197 case VFMADD213PDZmb:
13198 case VFMADD213PDZmbk:
13199 case VFMADD213PDZmbkz:
13200 case VFMADD213PDZmk:
13201 case VFMADD213PDZmkz:
13202 case VFMADD213PDZr:
13203 case VFMADD213PDZrb:
13204 case VFMADD213PDZrbk:
13205 case VFMADD213PDZrbkz:
13206 case VFMADD213PDZrk:
13207 case VFMADD213PDZrkz:
13208 case VFMADD213PDm:
13209 case VFMADD213PDr:
13210 return true;
13211 }
13212 return false;
13213}
13214
13215bool isVPGATHERQD(unsigned Opcode) {
13216 switch (Opcode) {
13217 case VPGATHERQDYrm:
13218 case VPGATHERQDZ128rm:
13219 case VPGATHERQDZ256rm:
13220 case VPGATHERQDZrm:
13221 case VPGATHERQDrm:
13222 return true;
13223 }
13224 return false;
13225}
13226
13227bool isVFNMSUB213BF16(unsigned Opcode) {
13228 switch (Opcode) {
13229 case VFNMSUB213BF16Z128m:
13230 case VFNMSUB213BF16Z128mb:
13231 case VFNMSUB213BF16Z128mbk:
13232 case VFNMSUB213BF16Z128mbkz:
13233 case VFNMSUB213BF16Z128mk:
13234 case VFNMSUB213BF16Z128mkz:
13235 case VFNMSUB213BF16Z128r:
13236 case VFNMSUB213BF16Z128rk:
13237 case VFNMSUB213BF16Z128rkz:
13238 case VFNMSUB213BF16Z256m:
13239 case VFNMSUB213BF16Z256mb:
13240 case VFNMSUB213BF16Z256mbk:
13241 case VFNMSUB213BF16Z256mbkz:
13242 case VFNMSUB213BF16Z256mk:
13243 case VFNMSUB213BF16Z256mkz:
13244 case VFNMSUB213BF16Z256r:
13245 case VFNMSUB213BF16Z256rk:
13246 case VFNMSUB213BF16Z256rkz:
13247 case VFNMSUB213BF16Zm:
13248 case VFNMSUB213BF16Zmb:
13249 case VFNMSUB213BF16Zmbk:
13250 case VFNMSUB213BF16Zmbkz:
13251 case VFNMSUB213BF16Zmk:
13252 case VFNMSUB213BF16Zmkz:
13253 case VFNMSUB213BF16Zr:
13254 case VFNMSUB213BF16Zrk:
13255 case VFNMSUB213BF16Zrkz:
13256 return true;
13257 }
13258 return false;
13259}
13260
13261bool isVCVTPS2IBS(unsigned Opcode) {
13262 switch (Opcode) {
13263 case VCVTPS2IBSZ128rm:
13264 case VCVTPS2IBSZ128rmb:
13265 case VCVTPS2IBSZ128rmbk:
13266 case VCVTPS2IBSZ128rmbkz:
13267 case VCVTPS2IBSZ128rmk:
13268 case VCVTPS2IBSZ128rmkz:
13269 case VCVTPS2IBSZ128rr:
13270 case VCVTPS2IBSZ128rrk:
13271 case VCVTPS2IBSZ128rrkz:
13272 case VCVTPS2IBSZ256rm:
13273 case VCVTPS2IBSZ256rmb:
13274 case VCVTPS2IBSZ256rmbk:
13275 case VCVTPS2IBSZ256rmbkz:
13276 case VCVTPS2IBSZ256rmk:
13277 case VCVTPS2IBSZ256rmkz:
13278 case VCVTPS2IBSZ256rr:
13279 case VCVTPS2IBSZ256rrk:
13280 case VCVTPS2IBSZ256rrkz:
13281 case VCVTPS2IBSZrm:
13282 case VCVTPS2IBSZrmb:
13283 case VCVTPS2IBSZrmbk:
13284 case VCVTPS2IBSZrmbkz:
13285 case VCVTPS2IBSZrmk:
13286 case VCVTPS2IBSZrmkz:
13287 case VCVTPS2IBSZrr:
13288 case VCVTPS2IBSZrrb:
13289 case VCVTPS2IBSZrrbk:
13290 case VCVTPS2IBSZrrbkz:
13291 case VCVTPS2IBSZrrk:
13292 case VCVTPS2IBSZrrkz:
13293 return true;
13294 }
13295 return false;
13296}
13297
13298bool isVPCMPGTW(unsigned Opcode) {
13299 switch (Opcode) {
13300 case VPCMPGTWYrm:
13301 case VPCMPGTWYrr:
13302 case VPCMPGTWZ128rm:
13303 case VPCMPGTWZ128rmk:
13304 case VPCMPGTWZ128rr:
13305 case VPCMPGTWZ128rrk:
13306 case VPCMPGTWZ256rm:
13307 case VPCMPGTWZ256rmk:
13308 case VPCMPGTWZ256rr:
13309 case VPCMPGTWZ256rrk:
13310 case VPCMPGTWZrm:
13311 case VPCMPGTWZrmk:
13312 case VPCMPGTWZrr:
13313 case VPCMPGTWZrrk:
13314 case VPCMPGTWrm:
13315 case VPCMPGTWrr:
13316 return true;
13317 }
13318 return false;
13319}
13320
13321bool isVMOVRSB(unsigned Opcode) {
13322 switch (Opcode) {
13323 case VMOVRSBZ128m:
13324 case VMOVRSBZ128mk:
13325 case VMOVRSBZ128mkz:
13326 case VMOVRSBZ256m:
13327 case VMOVRSBZ256mk:
13328 case VMOVRSBZ256mkz:
13329 case VMOVRSBZm:
13330 case VMOVRSBZmk:
13331 case VMOVRSBZmkz:
13332 return true;
13333 }
13334 return false;
13335}
13336
13337bool isVGETMANTSH(unsigned Opcode) {
13338 switch (Opcode) {
13339 case VGETMANTSHZrmi:
13340 case VGETMANTSHZrmik:
13341 case VGETMANTSHZrmikz:
13342 case VGETMANTSHZrri:
13343 case VGETMANTSHZrrib:
13344 case VGETMANTSHZrribk:
13345 case VGETMANTSHZrribkz:
13346 case VGETMANTSHZrrik:
13347 case VGETMANTSHZrrikz:
13348 return true;
13349 }
13350 return false;
13351}
13352
13353bool isVANDPS(unsigned Opcode) {
13354 switch (Opcode) {
13355 case VANDPSYrm:
13356 case VANDPSYrr:
13357 case VANDPSZ128rm:
13358 case VANDPSZ128rmb:
13359 case VANDPSZ128rmbk:
13360 case VANDPSZ128rmbkz:
13361 case VANDPSZ128rmk:
13362 case VANDPSZ128rmkz:
13363 case VANDPSZ128rr:
13364 case VANDPSZ128rrk:
13365 case VANDPSZ128rrkz:
13366 case VANDPSZ256rm:
13367 case VANDPSZ256rmb:
13368 case VANDPSZ256rmbk:
13369 case VANDPSZ256rmbkz:
13370 case VANDPSZ256rmk:
13371 case VANDPSZ256rmkz:
13372 case VANDPSZ256rr:
13373 case VANDPSZ256rrk:
13374 case VANDPSZ256rrkz:
13375 case VANDPSZrm:
13376 case VANDPSZrmb:
13377 case VANDPSZrmbk:
13378 case VANDPSZrmbkz:
13379 case VANDPSZrmk:
13380 case VANDPSZrmkz:
13381 case VANDPSZrr:
13382 case VANDPSZrrk:
13383 case VANDPSZrrkz:
13384 case VANDPSrm:
13385 case VANDPSrr:
13386 return true;
13387 }
13388 return false;
13389}
13390
13391bool isVDIVPS(unsigned Opcode) {
13392 switch (Opcode) {
13393 case VDIVPSYrm:
13394 case VDIVPSYrr:
13395 case VDIVPSZ128rm:
13396 case VDIVPSZ128rmb:
13397 case VDIVPSZ128rmbk:
13398 case VDIVPSZ128rmbkz:
13399 case VDIVPSZ128rmk:
13400 case VDIVPSZ128rmkz:
13401 case VDIVPSZ128rr:
13402 case VDIVPSZ128rrk:
13403 case VDIVPSZ128rrkz:
13404 case VDIVPSZ256rm:
13405 case VDIVPSZ256rmb:
13406 case VDIVPSZ256rmbk:
13407 case VDIVPSZ256rmbkz:
13408 case VDIVPSZ256rmk:
13409 case VDIVPSZ256rmkz:
13410 case VDIVPSZ256rr:
13411 case VDIVPSZ256rrk:
13412 case VDIVPSZ256rrkz:
13413 case VDIVPSZrm:
13414 case VDIVPSZrmb:
13415 case VDIVPSZrmbk:
13416 case VDIVPSZrmbkz:
13417 case VDIVPSZrmk:
13418 case VDIVPSZrmkz:
13419 case VDIVPSZrr:
13420 case VDIVPSZrrb:
13421 case VDIVPSZrrbk:
13422 case VDIVPSZrrbkz:
13423 case VDIVPSZrrk:
13424 case VDIVPSZrrkz:
13425 case VDIVPSrm:
13426 case VDIVPSrr:
13427 return true;
13428 }
13429 return false;
13430}
13431
13432bool isVANDNPS(unsigned Opcode) {
13433 switch (Opcode) {
13434 case VANDNPSYrm:
13435 case VANDNPSYrr:
13436 case VANDNPSZ128rm:
13437 case VANDNPSZ128rmb:
13438 case VANDNPSZ128rmbk:
13439 case VANDNPSZ128rmbkz:
13440 case VANDNPSZ128rmk:
13441 case VANDNPSZ128rmkz:
13442 case VANDNPSZ128rr:
13443 case VANDNPSZ128rrk:
13444 case VANDNPSZ128rrkz:
13445 case VANDNPSZ256rm:
13446 case VANDNPSZ256rmb:
13447 case VANDNPSZ256rmbk:
13448 case VANDNPSZ256rmbkz:
13449 case VANDNPSZ256rmk:
13450 case VANDNPSZ256rmkz:
13451 case VANDNPSZ256rr:
13452 case VANDNPSZ256rrk:
13453 case VANDNPSZ256rrkz:
13454 case VANDNPSZrm:
13455 case VANDNPSZrmb:
13456 case VANDNPSZrmbk:
13457 case VANDNPSZrmbkz:
13458 case VANDNPSZrmk:
13459 case VANDNPSZrmkz:
13460 case VANDNPSZrr:
13461 case VANDNPSZrrk:
13462 case VANDNPSZrrkz:
13463 case VANDNPSrm:
13464 case VANDNPSrr:
13465 return true;
13466 }
13467 return false;
13468}
13469
13470bool isVPBROADCASTW(unsigned Opcode) {
13471 switch (Opcode) {
13472 case VPBROADCASTWYrm:
13473 case VPBROADCASTWYrr:
13474 case VPBROADCASTWZ128rm:
13475 case VPBROADCASTWZ128rmk:
13476 case VPBROADCASTWZ128rmkz:
13477 case VPBROADCASTWZ128rr:
13478 case VPBROADCASTWZ128rrk:
13479 case VPBROADCASTWZ128rrkz:
13480 case VPBROADCASTWZ256rm:
13481 case VPBROADCASTWZ256rmk:
13482 case VPBROADCASTWZ256rmkz:
13483 case VPBROADCASTWZ256rr:
13484 case VPBROADCASTWZ256rrk:
13485 case VPBROADCASTWZ256rrkz:
13486 case VPBROADCASTWZrm:
13487 case VPBROADCASTWZrmk:
13488 case VPBROADCASTWZrmkz:
13489 case VPBROADCASTWZrr:
13490 case VPBROADCASTWZrrk:
13491 case VPBROADCASTWZrrkz:
13492 case VPBROADCASTWrZ128rr:
13493 case VPBROADCASTWrZ128rrk:
13494 case VPBROADCASTWrZ128rrkz:
13495 case VPBROADCASTWrZ256rr:
13496 case VPBROADCASTWrZ256rrk:
13497 case VPBROADCASTWrZ256rrkz:
13498 case VPBROADCASTWrZrr:
13499 case VPBROADCASTWrZrrk:
13500 case VPBROADCASTWrZrrkz:
13501 case VPBROADCASTWrm:
13502 case VPBROADCASTWrr:
13503 return true;
13504 }
13505 return false;
13506}
13507
13508bool isFLDL2T(unsigned Opcode) {
13509 return Opcode == FLDL2T;
13510}
13511
13512bool isVPERMB(unsigned Opcode) {
13513 switch (Opcode) {
13514 case VPERMBZ128rm:
13515 case VPERMBZ128rmk:
13516 case VPERMBZ128rmkz:
13517 case VPERMBZ128rr:
13518 case VPERMBZ128rrk:
13519 case VPERMBZ128rrkz:
13520 case VPERMBZ256rm:
13521 case VPERMBZ256rmk:
13522 case VPERMBZ256rmkz:
13523 case VPERMBZ256rr:
13524 case VPERMBZ256rrk:
13525 case VPERMBZ256rrkz:
13526 case VPERMBZrm:
13527 case VPERMBZrmk:
13528 case VPERMBZrmkz:
13529 case VPERMBZrr:
13530 case VPERMBZrrk:
13531 case VPERMBZrrkz:
13532 return true;
13533 }
13534 return false;
13535}
13536
13537bool isFCMOVNBE(unsigned Opcode) {
13538 return Opcode == CMOVNBE_F;
13539}
13540
13541bool isVCVTTPH2W(unsigned Opcode) {
13542 switch (Opcode) {
13543 case VCVTTPH2WZ128rm:
13544 case VCVTTPH2WZ128rmb:
13545 case VCVTTPH2WZ128rmbk:
13546 case VCVTTPH2WZ128rmbkz:
13547 case VCVTTPH2WZ128rmk:
13548 case VCVTTPH2WZ128rmkz:
13549 case VCVTTPH2WZ128rr:
13550 case VCVTTPH2WZ128rrk:
13551 case VCVTTPH2WZ128rrkz:
13552 case VCVTTPH2WZ256rm:
13553 case VCVTTPH2WZ256rmb:
13554 case VCVTTPH2WZ256rmbk:
13555 case VCVTTPH2WZ256rmbkz:
13556 case VCVTTPH2WZ256rmk:
13557 case VCVTTPH2WZ256rmkz:
13558 case VCVTTPH2WZ256rr:
13559 case VCVTTPH2WZ256rrk:
13560 case VCVTTPH2WZ256rrkz:
13561 case VCVTTPH2WZrm:
13562 case VCVTTPH2WZrmb:
13563 case VCVTTPH2WZrmbk:
13564 case VCVTTPH2WZrmbkz:
13565 case VCVTTPH2WZrmk:
13566 case VCVTTPH2WZrmkz:
13567 case VCVTTPH2WZrr:
13568 case VCVTTPH2WZrrb:
13569 case VCVTTPH2WZrrbk:
13570 case VCVTTPH2WZrrbkz:
13571 case VCVTTPH2WZrrk:
13572 case VCVTTPH2WZrrkz:
13573 return true;
13574 }
13575 return false;
13576}
13577
13578bool isPMOVZXBQ(unsigned Opcode) {
13579 switch (Opcode) {
13580 case PMOVZXBQrm:
13581 case PMOVZXBQrr:
13582 return true;
13583 }
13584 return false;
13585}
13586
13587bool isPF2ID(unsigned Opcode) {
13588 switch (Opcode) {
13589 case PF2IDrm:
13590 case PF2IDrr:
13591 return true;
13592 }
13593 return false;
13594}
13595
13596bool isVFNMADD132PD(unsigned Opcode) {
13597 switch (Opcode) {
13598 case VFNMADD132PDYm:
13599 case VFNMADD132PDYr:
13600 case VFNMADD132PDZ128m:
13601 case VFNMADD132PDZ128mb:
13602 case VFNMADD132PDZ128mbk:
13603 case VFNMADD132PDZ128mbkz:
13604 case VFNMADD132PDZ128mk:
13605 case VFNMADD132PDZ128mkz:
13606 case VFNMADD132PDZ128r:
13607 case VFNMADD132PDZ128rk:
13608 case VFNMADD132PDZ128rkz:
13609 case VFNMADD132PDZ256m:
13610 case VFNMADD132PDZ256mb:
13611 case VFNMADD132PDZ256mbk:
13612 case VFNMADD132PDZ256mbkz:
13613 case VFNMADD132PDZ256mk:
13614 case VFNMADD132PDZ256mkz:
13615 case VFNMADD132PDZ256r:
13616 case VFNMADD132PDZ256rk:
13617 case VFNMADD132PDZ256rkz:
13618 case VFNMADD132PDZm:
13619 case VFNMADD132PDZmb:
13620 case VFNMADD132PDZmbk:
13621 case VFNMADD132PDZmbkz:
13622 case VFNMADD132PDZmk:
13623 case VFNMADD132PDZmkz:
13624 case VFNMADD132PDZr:
13625 case VFNMADD132PDZrb:
13626 case VFNMADD132PDZrbk:
13627 case VFNMADD132PDZrbkz:
13628 case VFNMADD132PDZrk:
13629 case VFNMADD132PDZrkz:
13630 case VFNMADD132PDm:
13631 case VFNMADD132PDr:
13632 return true;
13633 }
13634 return false;
13635}
13636
13637bool isPMULHRSW(unsigned Opcode) {
13638 switch (Opcode) {
13639 case MMX_PMULHRSWrm:
13640 case MMX_PMULHRSWrr:
13641 case PMULHRSWrm:
13642 case PMULHRSWrr:
13643 return true;
13644 }
13645 return false;
13646}
13647
13648bool isKADDD(unsigned Opcode) {
13649 return Opcode == KADDDkk;
13650}
13651
13652bool isVFNMSUB132SH(unsigned Opcode) {
13653 switch (Opcode) {
13654 case VFNMSUB132SHZm_Int:
13655 case VFNMSUB132SHZmk_Int:
13656 case VFNMSUB132SHZmkz_Int:
13657 case VFNMSUB132SHZr_Int:
13658 case VFNMSUB132SHZrb_Int:
13659 case VFNMSUB132SHZrbk_Int:
13660 case VFNMSUB132SHZrbkz_Int:
13661 case VFNMSUB132SHZrk_Int:
13662 case VFNMSUB132SHZrkz_Int:
13663 return true;
13664 }
13665 return false;
13666}
13667
13668bool isUIRET(unsigned Opcode) {
13669 return Opcode == UIRET;
13670}
13671
13672bool isBSR(unsigned Opcode) {
13673 switch (Opcode) {
13674 case BSR16rm:
13675 case BSR16rr:
13676 case BSR32rm:
13677 case BSR32rr:
13678 case BSR64rm:
13679 case BSR64rr:
13680 return true;
13681 }
13682 return false;
13683}
13684
13685bool isPCMPEQQ(unsigned Opcode) {
13686 switch (Opcode) {
13687 case PCMPEQQrm:
13688 case PCMPEQQrr:
13689 return true;
13690 }
13691 return false;
13692}
13693
13694bool isCDQ(unsigned Opcode) {
13695 return Opcode == CDQ;
13696}
13697
13698bool isPMAXSW(unsigned Opcode) {
13699 switch (Opcode) {
13700 case MMX_PMAXSWrm:
13701 case MMX_PMAXSWrr:
13702 case PMAXSWrm:
13703 case PMAXSWrr:
13704 return true;
13705 }
13706 return false;
13707}
13708
13709bool isSIDTD(unsigned Opcode) {
13710 return Opcode == SIDT32m;
13711}
13712
13713bool isVCVTPS2PHX(unsigned Opcode) {
13714 switch (Opcode) {
13715 case VCVTPS2PHXZ128rm:
13716 case VCVTPS2PHXZ128rmb:
13717 case VCVTPS2PHXZ128rmbk:
13718 case VCVTPS2PHXZ128rmbkz:
13719 case VCVTPS2PHXZ128rmk:
13720 case VCVTPS2PHXZ128rmkz:
13721 case VCVTPS2PHXZ128rr:
13722 case VCVTPS2PHXZ128rrk:
13723 case VCVTPS2PHXZ128rrkz:
13724 case VCVTPS2PHXZ256rm:
13725 case VCVTPS2PHXZ256rmb:
13726 case VCVTPS2PHXZ256rmbk:
13727 case VCVTPS2PHXZ256rmbkz:
13728 case VCVTPS2PHXZ256rmk:
13729 case VCVTPS2PHXZ256rmkz:
13730 case VCVTPS2PHXZ256rr:
13731 case VCVTPS2PHXZ256rrk:
13732 case VCVTPS2PHXZ256rrkz:
13733 case VCVTPS2PHXZrm:
13734 case VCVTPS2PHXZrmb:
13735 case VCVTPS2PHXZrmbk:
13736 case VCVTPS2PHXZrmbkz:
13737 case VCVTPS2PHXZrmk:
13738 case VCVTPS2PHXZrmkz:
13739 case VCVTPS2PHXZrr:
13740 case VCVTPS2PHXZrrb:
13741 case VCVTPS2PHXZrrbk:
13742 case VCVTPS2PHXZrrbkz:
13743 case VCVTPS2PHXZrrk:
13744 case VCVTPS2PHXZrrkz:
13745 return true;
13746 }
13747 return false;
13748}
13749
13750bool isVPSLLVQ(unsigned Opcode) {
13751 switch (Opcode) {
13752 case VPSLLVQYrm:
13753 case VPSLLVQYrr:
13754 case VPSLLVQZ128rm:
13755 case VPSLLVQZ128rmb:
13756 case VPSLLVQZ128rmbk:
13757 case VPSLLVQZ128rmbkz:
13758 case VPSLLVQZ128rmk:
13759 case VPSLLVQZ128rmkz:
13760 case VPSLLVQZ128rr:
13761 case VPSLLVQZ128rrk:
13762 case VPSLLVQZ128rrkz:
13763 case VPSLLVQZ256rm:
13764 case VPSLLVQZ256rmb:
13765 case VPSLLVQZ256rmbk:
13766 case VPSLLVQZ256rmbkz:
13767 case VPSLLVQZ256rmk:
13768 case VPSLLVQZ256rmkz:
13769 case VPSLLVQZ256rr:
13770 case VPSLLVQZ256rrk:
13771 case VPSLLVQZ256rrkz:
13772 case VPSLLVQZrm:
13773 case VPSLLVQZrmb:
13774 case VPSLLVQZrmbk:
13775 case VPSLLVQZrmbkz:
13776 case VPSLLVQZrmk:
13777 case VPSLLVQZrmkz:
13778 case VPSLLVQZrr:
13779 case VPSLLVQZrrk:
13780 case VPSLLVQZrrkz:
13781 case VPSLLVQrm:
13782 case VPSLLVQrr:
13783 return true;
13784 }
13785 return false;
13786}
13787
13788bool isMOVQ(unsigned Opcode) {
13789 switch (Opcode) {
13790 case MMX_MOVD64from64mr:
13791 case MMX_MOVD64from64rr:
13792 case MMX_MOVD64to64rm:
13793 case MMX_MOVD64to64rr:
13794 case MMX_MOVQ64mr:
13795 case MMX_MOVQ64rm:
13796 case MMX_MOVQ64rr:
13797 case MMX_MOVQ64rr_REV:
13798 case MOV64toPQIrm:
13799 case MOV64toPQIrr:
13800 case MOVPQI2QImr:
13801 case MOVPQI2QIrr:
13802 case MOVPQIto64mr:
13803 case MOVPQIto64rr:
13804 case MOVQI2PQIrm:
13805 case MOVZPQILo2PQIrr:
13806 return true;
13807 }
13808 return false;
13809}
13810
13811bool isPREFETCH(unsigned Opcode) {
13812 return Opcode == PREFETCH;
13813}
13814
13815bool isVCMPBF16(unsigned Opcode) {
13816 switch (Opcode) {
13817 case VCMPBF16Z128rmbi:
13818 case VCMPBF16Z128rmbik:
13819 case VCMPBF16Z128rmi:
13820 case VCMPBF16Z128rmik:
13821 case VCMPBF16Z128rri:
13822 case VCMPBF16Z128rrik:
13823 case VCMPBF16Z256rmbi:
13824 case VCMPBF16Z256rmbik:
13825 case VCMPBF16Z256rmi:
13826 case VCMPBF16Z256rmik:
13827 case VCMPBF16Z256rri:
13828 case VCMPBF16Z256rrik:
13829 case VCMPBF16Zrmbi:
13830 case VCMPBF16Zrmbik:
13831 case VCMPBF16Zrmi:
13832 case VCMPBF16Zrmik:
13833 case VCMPBF16Zrri:
13834 case VCMPBF16Zrrik:
13835 return true;
13836 }
13837 return false;
13838}
13839
13840bool isVBMACOR16X16X16(unsigned Opcode) {
13841 switch (Opcode) {
13842 case VBMACORZ256rm:
13843 case VBMACORZ256rmb:
13844 case VBMACORZ256rmbk:
13845 case VBMACORZ256rmbkz:
13846 case VBMACORZ256rmk:
13847 case VBMACORZ256rmkz:
13848 case VBMACORZ256rr:
13849 case VBMACORZ256rrk:
13850 case VBMACORZ256rrkz:
13851 case VBMACORZrm:
13852 case VBMACORZrmb:
13853 case VBMACORZrmbk:
13854 case VBMACORZrmbkz:
13855 case VBMACORZrmk:
13856 case VBMACORZrmkz:
13857 case VBMACORZrr:
13858 case VBMACORZrrk:
13859 case VBMACORZrrkz:
13860 return true;
13861 }
13862 return false;
13863}
13864
13865bool isCLRSSBSY(unsigned Opcode) {
13866 return Opcode == CLRSSBSY;
13867}
13868
13869bool isTCVTROWPS2PHL(unsigned Opcode) {
13870 switch (Opcode) {
13871 case TCVTROWPS2PHLrte:
13872 case TCVTROWPS2PHLrti:
13873 return true;
13874 }
13875 return false;
13876}
13877
13878bool isPSHUFW(unsigned Opcode) {
13879 switch (Opcode) {
13880 case MMX_PSHUFWmi:
13881 case MMX_PSHUFWri:
13882 return true;
13883 }
13884 return false;
13885}
13886
13887bool isVPDPWSUDS(unsigned Opcode) {
13888 switch (Opcode) {
13889 case VPDPWSUDSYrm:
13890 case VPDPWSUDSYrr:
13891 case VPDPWSUDSZ128rm:
13892 case VPDPWSUDSZ128rmb:
13893 case VPDPWSUDSZ128rmbk:
13894 case VPDPWSUDSZ128rmbkz:
13895 case VPDPWSUDSZ128rmk:
13896 case VPDPWSUDSZ128rmkz:
13897 case VPDPWSUDSZ128rr:
13898 case VPDPWSUDSZ128rrk:
13899 case VPDPWSUDSZ128rrkz:
13900 case VPDPWSUDSZ256rm:
13901 case VPDPWSUDSZ256rmb:
13902 case VPDPWSUDSZ256rmbk:
13903 case VPDPWSUDSZ256rmbkz:
13904 case VPDPWSUDSZ256rmk:
13905 case VPDPWSUDSZ256rmkz:
13906 case VPDPWSUDSZ256rr:
13907 case VPDPWSUDSZ256rrk:
13908 case VPDPWSUDSZ256rrkz:
13909 case VPDPWSUDSZrm:
13910 case VPDPWSUDSZrmb:
13911 case VPDPWSUDSZrmbk:
13912 case VPDPWSUDSZrmbkz:
13913 case VPDPWSUDSZrmk:
13914 case VPDPWSUDSZrmkz:
13915 case VPDPWSUDSZrr:
13916 case VPDPWSUDSZrrk:
13917 case VPDPWSUDSZrrkz:
13918 case VPDPWSUDSrm:
13919 case VPDPWSUDSrr:
13920 return true;
13921 }
13922 return false;
13923}
13924
13925bool isVPMOVSXBQ(unsigned Opcode) {
13926 switch (Opcode) {
13927 case VPMOVSXBQYrm:
13928 case VPMOVSXBQYrr:
13929 case VPMOVSXBQZ128rm:
13930 case VPMOVSXBQZ128rmk:
13931 case VPMOVSXBQZ128rmkz:
13932 case VPMOVSXBQZ128rr:
13933 case VPMOVSXBQZ128rrk:
13934 case VPMOVSXBQZ128rrkz:
13935 case VPMOVSXBQZ256rm:
13936 case VPMOVSXBQZ256rmk:
13937 case VPMOVSXBQZ256rmkz:
13938 case VPMOVSXBQZ256rr:
13939 case VPMOVSXBQZ256rrk:
13940 case VPMOVSXBQZ256rrkz:
13941 case VPMOVSXBQZrm:
13942 case VPMOVSXBQZrmk:
13943 case VPMOVSXBQZrmkz:
13944 case VPMOVSXBQZrr:
13945 case VPMOVSXBQZrrk:
13946 case VPMOVSXBQZrrkz:
13947 case VPMOVSXBQrm:
13948 case VPMOVSXBQrr:
13949 return true;
13950 }
13951 return false;
13952}
13953
13954bool isFICOMP(unsigned Opcode) {
13955 switch (Opcode) {
13956 case FICOMP16m:
13957 case FICOMP32m:
13958 return true;
13959 }
13960 return false;
13961}
13962
13963bool isVFNMSUB132SS(unsigned Opcode) {
13964 switch (Opcode) {
13965 case VFNMSUB132SSZm_Int:
13966 case VFNMSUB132SSZmk_Int:
13967 case VFNMSUB132SSZmkz_Int:
13968 case VFNMSUB132SSZr_Int:
13969 case VFNMSUB132SSZrb_Int:
13970 case VFNMSUB132SSZrbk_Int:
13971 case VFNMSUB132SSZrbkz_Int:
13972 case VFNMSUB132SSZrk_Int:
13973 case VFNMSUB132SSZrkz_Int:
13974 case VFNMSUB132SSm_Int:
13975 case VFNMSUB132SSr_Int:
13976 return true;
13977 }
13978 return false;
13979}
13980
13981bool isVLDMXCSR(unsigned Opcode) {
13982 return Opcode == VLDMXCSR;
13983}
13984
13985bool isVPSUBUSW(unsigned Opcode) {
13986 switch (Opcode) {
13987 case VPSUBUSWYrm:
13988 case VPSUBUSWYrr:
13989 case VPSUBUSWZ128rm:
13990 case VPSUBUSWZ128rmk:
13991 case VPSUBUSWZ128rmkz:
13992 case VPSUBUSWZ128rr:
13993 case VPSUBUSWZ128rrk:
13994 case VPSUBUSWZ128rrkz:
13995 case VPSUBUSWZ256rm:
13996 case VPSUBUSWZ256rmk:
13997 case VPSUBUSWZ256rmkz:
13998 case VPSUBUSWZ256rr:
13999 case VPSUBUSWZ256rrk:
14000 case VPSUBUSWZ256rrkz:
14001 case VPSUBUSWZrm:
14002 case VPSUBUSWZrmk:
14003 case VPSUBUSWZrmkz:
14004 case VPSUBUSWZrr:
14005 case VPSUBUSWZrrk:
14006 case VPSUBUSWZrrkz:
14007 case VPSUBUSWrm:
14008 case VPSUBUSWrr:
14009 return true;
14010 }
14011 return false;
14012}
14013
14014bool isRETF(unsigned Opcode) {
14015 switch (Opcode) {
14016 case LRET16:
14017 case LRET32:
14018 case LRETI16:
14019 case LRETI32:
14020 return true;
14021 }
14022 return false;
14023}
14024
14025bool isKMOVQ(unsigned Opcode) {
14026 switch (Opcode) {
14027 case KMOVQkk:
14028 case KMOVQkk_EVEX:
14029 case KMOVQkm:
14030 case KMOVQkm_EVEX:
14031 case KMOVQkr:
14032 case KMOVQkr_EVEX:
14033 case KMOVQmk:
14034 case KMOVQmk_EVEX:
14035 case KMOVQrk:
14036 case KMOVQrk_EVEX:
14037 return true;
14038 }
14039 return false;
14040}
14041
14042bool isVPADDUSW(unsigned Opcode) {
14043 switch (Opcode) {
14044 case VPADDUSWYrm:
14045 case VPADDUSWYrr:
14046 case VPADDUSWZ128rm:
14047 case VPADDUSWZ128rmk:
14048 case VPADDUSWZ128rmkz:
14049 case VPADDUSWZ128rr:
14050 case VPADDUSWZ128rrk:
14051 case VPADDUSWZ128rrkz:
14052 case VPADDUSWZ256rm:
14053 case VPADDUSWZ256rmk:
14054 case VPADDUSWZ256rmkz:
14055 case VPADDUSWZ256rr:
14056 case VPADDUSWZ256rrk:
14057 case VPADDUSWZ256rrkz:
14058 case VPADDUSWZrm:
14059 case VPADDUSWZrmk:
14060 case VPADDUSWZrmkz:
14061 case VPADDUSWZrr:
14062 case VPADDUSWZrrk:
14063 case VPADDUSWZrrkz:
14064 case VPADDUSWrm:
14065 case VPADDUSWrr:
14066 return true;
14067 }
14068 return false;
14069}
14070
14071bool isPACKSSDW(unsigned Opcode) {
14072 switch (Opcode) {
14073 case MMX_PACKSSDWrm:
14074 case MMX_PACKSSDWrr:
14075 case PACKSSDWrm:
14076 case PACKSSDWrr:
14077 return true;
14078 }
14079 return false;
14080}
14081
14082bool isUMONITOR(unsigned Opcode) {
14083 switch (Opcode) {
14084 case UMONITOR16:
14085 case UMONITOR32:
14086 case UMONITOR64:
14087 return true;
14088 }
14089 return false;
14090}
14091
14092bool isENQCMDS(unsigned Opcode) {
14093 switch (Opcode) {
14094 case ENQCMDS16:
14095 case ENQCMDS32:
14096 case ENQCMDS32_EVEX:
14097 case ENQCMDS64:
14098 case ENQCMDS64_EVEX:
14099 return true;
14100 }
14101 return false;
14102}
14103
14104bool isVCOMXSD(unsigned Opcode) {
14105 switch (Opcode) {
14106 case VCOMXSDZrm_Int:
14107 case VCOMXSDZrr_Int:
14108 case VCOMXSDZrrb_Int:
14109 return true;
14110 }
14111 return false;
14112}
14113
14114bool isVPMAXSQ(unsigned Opcode) {
14115 switch (Opcode) {
14116 case VPMAXSQZ128rm:
14117 case VPMAXSQZ128rmb:
14118 case VPMAXSQZ128rmbk:
14119 case VPMAXSQZ128rmbkz:
14120 case VPMAXSQZ128rmk:
14121 case VPMAXSQZ128rmkz:
14122 case VPMAXSQZ128rr:
14123 case VPMAXSQZ128rrk:
14124 case VPMAXSQZ128rrkz:
14125 case VPMAXSQZ256rm:
14126 case VPMAXSQZ256rmb:
14127 case VPMAXSQZ256rmbk:
14128 case VPMAXSQZ256rmbkz:
14129 case VPMAXSQZ256rmk:
14130 case VPMAXSQZ256rmkz:
14131 case VPMAXSQZ256rr:
14132 case VPMAXSQZ256rrk:
14133 case VPMAXSQZ256rrkz:
14134 case VPMAXSQZrm:
14135 case VPMAXSQZrmb:
14136 case VPMAXSQZrmbk:
14137 case VPMAXSQZrmbkz:
14138 case VPMAXSQZrmk:
14139 case VPMAXSQZrmkz:
14140 case VPMAXSQZrr:
14141 case VPMAXSQZrrk:
14142 case VPMAXSQZrrkz:
14143 return true;
14144 }
14145 return false;
14146}
14147
14148bool isVFMSUB213BF16(unsigned Opcode) {
14149 switch (Opcode) {
14150 case VFMSUB213BF16Z128m:
14151 case VFMSUB213BF16Z128mb:
14152 case VFMSUB213BF16Z128mbk:
14153 case VFMSUB213BF16Z128mbkz:
14154 case VFMSUB213BF16Z128mk:
14155 case VFMSUB213BF16Z128mkz:
14156 case VFMSUB213BF16Z128r:
14157 case VFMSUB213BF16Z128rk:
14158 case VFMSUB213BF16Z128rkz:
14159 case VFMSUB213BF16Z256m:
14160 case VFMSUB213BF16Z256mb:
14161 case VFMSUB213BF16Z256mbk:
14162 case VFMSUB213BF16Z256mbkz:
14163 case VFMSUB213BF16Z256mk:
14164 case VFMSUB213BF16Z256mkz:
14165 case VFMSUB213BF16Z256r:
14166 case VFMSUB213BF16Z256rk:
14167 case VFMSUB213BF16Z256rkz:
14168 case VFMSUB213BF16Zm:
14169 case VFMSUB213BF16Zmb:
14170 case VFMSUB213BF16Zmbk:
14171 case VFMSUB213BF16Zmbkz:
14172 case VFMSUB213BF16Zmk:
14173 case VFMSUB213BF16Zmkz:
14174 case VFMSUB213BF16Zr:
14175 case VFMSUB213BF16Zrk:
14176 case VFMSUB213BF16Zrkz:
14177 return true;
14178 }
14179 return false;
14180}
14181
14182bool isVPERMT2Q(unsigned Opcode) {
14183 switch (Opcode) {
14184 case VPERMT2QZ128rm:
14185 case VPERMT2QZ128rmb:
14186 case VPERMT2QZ128rmbk:
14187 case VPERMT2QZ128rmbkz:
14188 case VPERMT2QZ128rmk:
14189 case VPERMT2QZ128rmkz:
14190 case VPERMT2QZ128rr:
14191 case VPERMT2QZ128rrk:
14192 case VPERMT2QZ128rrkz:
14193 case VPERMT2QZ256rm:
14194 case VPERMT2QZ256rmb:
14195 case VPERMT2QZ256rmbk:
14196 case VPERMT2QZ256rmbkz:
14197 case VPERMT2QZ256rmk:
14198 case VPERMT2QZ256rmkz:
14199 case VPERMT2QZ256rr:
14200 case VPERMT2QZ256rrk:
14201 case VPERMT2QZ256rrkz:
14202 case VPERMT2QZrm:
14203 case VPERMT2QZrmb:
14204 case VPERMT2QZrmbk:
14205 case VPERMT2QZrmbkz:
14206 case VPERMT2QZrmk:
14207 case VPERMT2QZrmkz:
14208 case VPERMT2QZrr:
14209 case VPERMT2QZrrk:
14210 case VPERMT2QZrrkz:
14211 return true;
14212 }
14213 return false;
14214}
14215
14216bool isFDECSTP(unsigned Opcode) {
14217 return Opcode == FDECSTP;
14218}
14219
14220bool isVPTESTMQ(unsigned Opcode) {
14221 switch (Opcode) {
14222 case VPTESTMQZ128rm:
14223 case VPTESTMQZ128rmb:
14224 case VPTESTMQZ128rmbk:
14225 case VPTESTMQZ128rmk:
14226 case VPTESTMQZ128rr:
14227 case VPTESTMQZ128rrk:
14228 case VPTESTMQZ256rm:
14229 case VPTESTMQZ256rmb:
14230 case VPTESTMQZ256rmbk:
14231 case VPTESTMQZ256rmk:
14232 case VPTESTMQZ256rr:
14233 case VPTESTMQZ256rrk:
14234 case VPTESTMQZrm:
14235 case VPTESTMQZrmb:
14236 case VPTESTMQZrmbk:
14237 case VPTESTMQZrmk:
14238 case VPTESTMQZrr:
14239 case VPTESTMQZrrk:
14240 return true;
14241 }
14242 return false;
14243}
14244
14245bool isVRCP14PD(unsigned Opcode) {
14246 switch (Opcode) {
14247 case VRCP14PDZ128m:
14248 case VRCP14PDZ128mb:
14249 case VRCP14PDZ128mbk:
14250 case VRCP14PDZ128mbkz:
14251 case VRCP14PDZ128mk:
14252 case VRCP14PDZ128mkz:
14253 case VRCP14PDZ128r:
14254 case VRCP14PDZ128rk:
14255 case VRCP14PDZ128rkz:
14256 case VRCP14PDZ256m:
14257 case VRCP14PDZ256mb:
14258 case VRCP14PDZ256mbk:
14259 case VRCP14PDZ256mbkz:
14260 case VRCP14PDZ256mk:
14261 case VRCP14PDZ256mkz:
14262 case VRCP14PDZ256r:
14263 case VRCP14PDZ256rk:
14264 case VRCP14PDZ256rkz:
14265 case VRCP14PDZm:
14266 case VRCP14PDZmb:
14267 case VRCP14PDZmbk:
14268 case VRCP14PDZmbkz:
14269 case VRCP14PDZmk:
14270 case VRCP14PDZmkz:
14271 case VRCP14PDZr:
14272 case VRCP14PDZrk:
14273 case VRCP14PDZrkz:
14274 return true;
14275 }
14276 return false;
14277}
14278
14279bool isARPL(unsigned Opcode) {
14280 switch (Opcode) {
14281 case ARPL16mr:
14282 case ARPL16rr:
14283 return true;
14284 }
14285 return false;
14286}
14287
14288bool isVFMSUB213SD(unsigned Opcode) {
14289 switch (Opcode) {
14290 case VFMSUB213SDZm_Int:
14291 case VFMSUB213SDZmk_Int:
14292 case VFMSUB213SDZmkz_Int:
14293 case VFMSUB213SDZr_Int:
14294 case VFMSUB213SDZrb_Int:
14295 case VFMSUB213SDZrbk_Int:
14296 case VFMSUB213SDZrbkz_Int:
14297 case VFMSUB213SDZrk_Int:
14298 case VFMSUB213SDZrkz_Int:
14299 case VFMSUB213SDm_Int:
14300 case VFMSUB213SDr_Int:
14301 return true;
14302 }
14303 return false;
14304}
14305
14306bool isJMPABS(unsigned Opcode) {
14307 return Opcode == JMPABS64i;
14308}
14309
14310bool isVUNPCKHPS(unsigned Opcode) {
14311 switch (Opcode) {
14312 case VUNPCKHPSYrm:
14313 case VUNPCKHPSYrr:
14314 case VUNPCKHPSZ128rm:
14315 case VUNPCKHPSZ128rmb:
14316 case VUNPCKHPSZ128rmbk:
14317 case VUNPCKHPSZ128rmbkz:
14318 case VUNPCKHPSZ128rmk:
14319 case VUNPCKHPSZ128rmkz:
14320 case VUNPCKHPSZ128rr:
14321 case VUNPCKHPSZ128rrk:
14322 case VUNPCKHPSZ128rrkz:
14323 case VUNPCKHPSZ256rm:
14324 case VUNPCKHPSZ256rmb:
14325 case VUNPCKHPSZ256rmbk:
14326 case VUNPCKHPSZ256rmbkz:
14327 case VUNPCKHPSZ256rmk:
14328 case VUNPCKHPSZ256rmkz:
14329 case VUNPCKHPSZ256rr:
14330 case VUNPCKHPSZ256rrk:
14331 case VUNPCKHPSZ256rrkz:
14332 case VUNPCKHPSZrm:
14333 case VUNPCKHPSZrmb:
14334 case VUNPCKHPSZrmbk:
14335 case VUNPCKHPSZrmbkz:
14336 case VUNPCKHPSZrmk:
14337 case VUNPCKHPSZrmkz:
14338 case VUNPCKHPSZrr:
14339 case VUNPCKHPSZrrk:
14340 case VUNPCKHPSZrrkz:
14341 case VUNPCKHPSrm:
14342 case VUNPCKHPSrr:
14343 return true;
14344 }
14345 return false;
14346}
14347
14348bool isVFNMADDSS(unsigned Opcode) {
14349 switch (Opcode) {
14350 case VFNMADDSS4mr:
14351 case VFNMADDSS4rm:
14352 case VFNMADDSS4rr:
14353 case VFNMADDSS4rr_REV:
14354 return true;
14355 }
14356 return false;
14357}
14358
14359bool isSIDT(unsigned Opcode) {
14360 return Opcode == SIDT64m;
14361}
14362
14363bool isVPCMPGTB(unsigned Opcode) {
14364 switch (Opcode) {
14365 case VPCMPGTBYrm:
14366 case VPCMPGTBYrr:
14367 case VPCMPGTBZ128rm:
14368 case VPCMPGTBZ128rmk:
14369 case VPCMPGTBZ128rr:
14370 case VPCMPGTBZ128rrk:
14371 case VPCMPGTBZ256rm:
14372 case VPCMPGTBZ256rmk:
14373 case VPCMPGTBZ256rr:
14374 case VPCMPGTBZ256rrk:
14375 case VPCMPGTBZrm:
14376 case VPCMPGTBZrmk:
14377 case VPCMPGTBZrr:
14378 case VPCMPGTBZrrk:
14379 case VPCMPGTBrm:
14380 case VPCMPGTBrr:
14381 return true;
14382 }
14383 return false;
14384}
14385
14386bool isVPRORD(unsigned Opcode) {
14387 switch (Opcode) {
14388 case VPRORDZ128mbi:
14389 case VPRORDZ128mbik:
14390 case VPRORDZ128mbikz:
14391 case VPRORDZ128mi:
14392 case VPRORDZ128mik:
14393 case VPRORDZ128mikz:
14394 case VPRORDZ128ri:
14395 case VPRORDZ128rik:
14396 case VPRORDZ128rikz:
14397 case VPRORDZ256mbi:
14398 case VPRORDZ256mbik:
14399 case VPRORDZ256mbikz:
14400 case VPRORDZ256mi:
14401 case VPRORDZ256mik:
14402 case VPRORDZ256mikz:
14403 case VPRORDZ256ri:
14404 case VPRORDZ256rik:
14405 case VPRORDZ256rikz:
14406 case VPRORDZmbi:
14407 case VPRORDZmbik:
14408 case VPRORDZmbikz:
14409 case VPRORDZmi:
14410 case VPRORDZmik:
14411 case VPRORDZmikz:
14412 case VPRORDZri:
14413 case VPRORDZrik:
14414 case VPRORDZrikz:
14415 return true;
14416 }
14417 return false;
14418}
14419
14420bool isVSUBSS(unsigned Opcode) {
14421 switch (Opcode) {
14422 case VSUBSSZrm_Int:
14423 case VSUBSSZrmk_Int:
14424 case VSUBSSZrmkz_Int:
14425 case VSUBSSZrr_Int:
14426 case VSUBSSZrrb_Int:
14427 case VSUBSSZrrbk_Int:
14428 case VSUBSSZrrbkz_Int:
14429 case VSUBSSZrrk_Int:
14430 case VSUBSSZrrkz_Int:
14431 case VSUBSSrm_Int:
14432 case VSUBSSrr_Int:
14433 return true;
14434 }
14435 return false;
14436}
14437
14438bool isPUSHFQ(unsigned Opcode) {
14439 return Opcode == PUSHF64;
14440}
14441
14442bool isVCVTHF82PH(unsigned Opcode) {
14443 switch (Opcode) {
14444 case VCVTHF82PHZ128rm:
14445 case VCVTHF82PHZ128rmk:
14446 case VCVTHF82PHZ128rmkz:
14447 case VCVTHF82PHZ128rr:
14448 case VCVTHF82PHZ128rrk:
14449 case VCVTHF82PHZ128rrkz:
14450 case VCVTHF82PHZ256rm:
14451 case VCVTHF82PHZ256rmk:
14452 case VCVTHF82PHZ256rmkz:
14453 case VCVTHF82PHZ256rr:
14454 case VCVTHF82PHZ256rrk:
14455 case VCVTHF82PHZ256rrkz:
14456 case VCVTHF82PHZrm:
14457 case VCVTHF82PHZrmk:
14458 case VCVTHF82PHZrmkz:
14459 case VCVTHF82PHZrr:
14460 case VCVTHF82PHZrrk:
14461 case VCVTHF82PHZrrkz:
14462 return true;
14463 }
14464 return false;
14465}
14466
14467bool isVPCLMULQDQ(unsigned Opcode) {
14468 switch (Opcode) {
14469 case VPCLMULQDQYrmi:
14470 case VPCLMULQDQYrri:
14471 case VPCLMULQDQZ128rmi:
14472 case VPCLMULQDQZ128rri:
14473 case VPCLMULQDQZ256rmi:
14474 case VPCLMULQDQZ256rri:
14475 case VPCLMULQDQZrmi:
14476 case VPCLMULQDQZrri:
14477 case VPCLMULQDQrmi:
14478 case VPCLMULQDQrri:
14479 return true;
14480 }
14481 return false;
14482}
14483
14484bool isVPADDUSB(unsigned Opcode) {
14485 switch (Opcode) {
14486 case VPADDUSBYrm:
14487 case VPADDUSBYrr:
14488 case VPADDUSBZ128rm:
14489 case VPADDUSBZ128rmk:
14490 case VPADDUSBZ128rmkz:
14491 case VPADDUSBZ128rr:
14492 case VPADDUSBZ128rrk:
14493 case VPADDUSBZ128rrkz:
14494 case VPADDUSBZ256rm:
14495 case VPADDUSBZ256rmk:
14496 case VPADDUSBZ256rmkz:
14497 case VPADDUSBZ256rr:
14498 case VPADDUSBZ256rrk:
14499 case VPADDUSBZ256rrkz:
14500 case VPADDUSBZrm:
14501 case VPADDUSBZrmk:
14502 case VPADDUSBZrmkz:
14503 case VPADDUSBZrr:
14504 case VPADDUSBZrrk:
14505 case VPADDUSBZrrkz:
14506 case VPADDUSBrm:
14507 case VPADDUSBrr:
14508 return true;
14509 }
14510 return false;
14511}
14512
14513bool isVPCMPD(unsigned Opcode) {
14514 switch (Opcode) {
14515 case VPCMPDZ128rmbi:
14516 case VPCMPDZ128rmbik:
14517 case VPCMPDZ128rmi:
14518 case VPCMPDZ128rmik:
14519 case VPCMPDZ128rri:
14520 case VPCMPDZ128rrik:
14521 case VPCMPDZ256rmbi:
14522 case VPCMPDZ256rmbik:
14523 case VPCMPDZ256rmi:
14524 case VPCMPDZ256rmik:
14525 case VPCMPDZ256rri:
14526 case VPCMPDZ256rrik:
14527 case VPCMPDZrmbi:
14528 case VPCMPDZrmbik:
14529 case VPCMPDZrmi:
14530 case VPCMPDZrmik:
14531 case VPCMPDZrri:
14532 case VPCMPDZrrik:
14533 return true;
14534 }
14535 return false;
14536}
14537
14538bool isMOVSD(unsigned Opcode) {
14539 switch (Opcode) {
14540 case MOVSDmr:
14541 case MOVSDrm:
14542 case MOVSDrr:
14543 case MOVSDrr_REV:
14544 case MOVSL:
14545 return true;
14546 }
14547 return false;
14548}
14549
14550bool isPSUBUSW(unsigned Opcode) {
14551 switch (Opcode) {
14552 case MMX_PSUBUSWrm:
14553 case MMX_PSUBUSWrr:
14554 case PSUBUSWrm:
14555 case PSUBUSWrr:
14556 return true;
14557 }
14558 return false;
14559}
14560
14561bool isVFMSUBADD132PS(unsigned Opcode) {
14562 switch (Opcode) {
14563 case VFMSUBADD132PSYm:
14564 case VFMSUBADD132PSYr:
14565 case VFMSUBADD132PSZ128m:
14566 case VFMSUBADD132PSZ128mb:
14567 case VFMSUBADD132PSZ128mbk:
14568 case VFMSUBADD132PSZ128mbkz:
14569 case VFMSUBADD132PSZ128mk:
14570 case VFMSUBADD132PSZ128mkz:
14571 case VFMSUBADD132PSZ128r:
14572 case VFMSUBADD132PSZ128rk:
14573 case VFMSUBADD132PSZ128rkz:
14574 case VFMSUBADD132PSZ256m:
14575 case VFMSUBADD132PSZ256mb:
14576 case VFMSUBADD132PSZ256mbk:
14577 case VFMSUBADD132PSZ256mbkz:
14578 case VFMSUBADD132PSZ256mk:
14579 case VFMSUBADD132PSZ256mkz:
14580 case VFMSUBADD132PSZ256r:
14581 case VFMSUBADD132PSZ256rk:
14582 case VFMSUBADD132PSZ256rkz:
14583 case VFMSUBADD132PSZm:
14584 case VFMSUBADD132PSZmb:
14585 case VFMSUBADD132PSZmbk:
14586 case VFMSUBADD132PSZmbkz:
14587 case VFMSUBADD132PSZmk:
14588 case VFMSUBADD132PSZmkz:
14589 case VFMSUBADD132PSZr:
14590 case VFMSUBADD132PSZrb:
14591 case VFMSUBADD132PSZrbk:
14592 case VFMSUBADD132PSZrbkz:
14593 case VFMSUBADD132PSZrk:
14594 case VFMSUBADD132PSZrkz:
14595 case VFMSUBADD132PSm:
14596 case VFMSUBADD132PSr:
14597 return true;
14598 }
14599 return false;
14600}
14601
14602bool isMOVMSKPS(unsigned Opcode) {
14603 return Opcode == MOVMSKPSrr;
14604}
14605
14606bool isVFIXUPIMMSS(unsigned Opcode) {
14607 switch (Opcode) {
14608 case VFIXUPIMMSSZrmi:
14609 case VFIXUPIMMSSZrmik:
14610 case VFIXUPIMMSSZrmikz:
14611 case VFIXUPIMMSSZrri:
14612 case VFIXUPIMMSSZrrib:
14613 case VFIXUPIMMSSZrribk:
14614 case VFIXUPIMMSSZrribkz:
14615 case VFIXUPIMMSSZrrik:
14616 case VFIXUPIMMSSZrrikz:
14617 return true;
14618 }
14619 return false;
14620}
14621
14622bool isMFENCE(unsigned Opcode) {
14623 return Opcode == MFENCE;
14624}
14625
14626bool isFTST(unsigned Opcode) {
14627 return Opcode == TST_F;
14628}
14629
14630bool isVPMADDWD(unsigned Opcode) {
14631 switch (Opcode) {
14632 case VPMADDWDYrm:
14633 case VPMADDWDYrr:
14634 case VPMADDWDZ128rm:
14635 case VPMADDWDZ128rmk:
14636 case VPMADDWDZ128rmkz:
14637 case VPMADDWDZ128rr:
14638 case VPMADDWDZ128rrk:
14639 case VPMADDWDZ128rrkz:
14640 case VPMADDWDZ256rm:
14641 case VPMADDWDZ256rmk:
14642 case VPMADDWDZ256rmkz:
14643 case VPMADDWDZ256rr:
14644 case VPMADDWDZ256rrk:
14645 case VPMADDWDZ256rrkz:
14646 case VPMADDWDZrm:
14647 case VPMADDWDZrmk:
14648 case VPMADDWDZrmkz:
14649 case VPMADDWDZrr:
14650 case VPMADDWDZrrk:
14651 case VPMADDWDZrrkz:
14652 case VPMADDWDrm:
14653 case VPMADDWDrr:
14654 return true;
14655 }
14656 return false;
14657}
14658
14659bool isPOP(unsigned Opcode) {
14660 switch (Opcode) {
14661 case POP16r:
14662 case POP16rmm:
14663 case POP16rmr:
14664 case POP32r:
14665 case POP32rmm:
14666 case POP32rmr:
14667 case POP64r:
14668 case POP64rmm:
14669 case POP64rmr:
14670 case POPDS16:
14671 case POPDS32:
14672 case POPES16:
14673 case POPES32:
14674 case POPFS16:
14675 case POPFS32:
14676 case POPFS64:
14677 case POPGS16:
14678 case POPGS32:
14679 case POPGS64:
14680 case POPSS16:
14681 case POPSS32:
14682 return true;
14683 }
14684 return false;
14685}
14686
14687bool isPSUBW(unsigned Opcode) {
14688 switch (Opcode) {
14689 case MMX_PSUBWrm:
14690 case MMX_PSUBWrr:
14691 case PSUBWrm:
14692 case PSUBWrr:
14693 return true;
14694 }
14695 return false;
14696}
14697
14698bool isBSWAP(unsigned Opcode) {
14699 switch (Opcode) {
14700 case BSWAP16r_BAD:
14701 case BSWAP32r:
14702 case BSWAP64r:
14703 return true;
14704 }
14705 return false;
14706}
14707
14708bool isPFMIN(unsigned Opcode) {
14709 switch (Opcode) {
14710 case PFMINrm:
14711 case PFMINrr:
14712 return true;
14713 }
14714 return false;
14715}
14716
14717bool isVFPCLASSPD(unsigned Opcode) {
14718 switch (Opcode) {
14719 case VFPCLASSPDZ128mbi:
14720 case VFPCLASSPDZ128mbik:
14721 case VFPCLASSPDZ128mi:
14722 case VFPCLASSPDZ128mik:
14723 case VFPCLASSPDZ128ri:
14724 case VFPCLASSPDZ128rik:
14725 case VFPCLASSPDZ256mbi:
14726 case VFPCLASSPDZ256mbik:
14727 case VFPCLASSPDZ256mi:
14728 case VFPCLASSPDZ256mik:
14729 case VFPCLASSPDZ256ri:
14730 case VFPCLASSPDZ256rik:
14731 case VFPCLASSPDZmbi:
14732 case VFPCLASSPDZmbik:
14733 case VFPCLASSPDZmi:
14734 case VFPCLASSPDZmik:
14735 case VFPCLASSPDZri:
14736 case VFPCLASSPDZrik:
14737 return true;
14738 }
14739 return false;
14740}
14741
14742bool isVPSHRDVD(unsigned Opcode) {
14743 switch (Opcode) {
14744 case VPSHRDVDZ128m:
14745 case VPSHRDVDZ128mb:
14746 case VPSHRDVDZ128mbk:
14747 case VPSHRDVDZ128mbkz:
14748 case VPSHRDVDZ128mk:
14749 case VPSHRDVDZ128mkz:
14750 case VPSHRDVDZ128r:
14751 case VPSHRDVDZ128rk:
14752 case VPSHRDVDZ128rkz:
14753 case VPSHRDVDZ256m:
14754 case VPSHRDVDZ256mb:
14755 case VPSHRDVDZ256mbk:
14756 case VPSHRDVDZ256mbkz:
14757 case VPSHRDVDZ256mk:
14758 case VPSHRDVDZ256mkz:
14759 case VPSHRDVDZ256r:
14760 case VPSHRDVDZ256rk:
14761 case VPSHRDVDZ256rkz:
14762 case VPSHRDVDZm:
14763 case VPSHRDVDZmb:
14764 case VPSHRDVDZmbk:
14765 case VPSHRDVDZmbkz:
14766 case VPSHRDVDZmk:
14767 case VPSHRDVDZmkz:
14768 case VPSHRDVDZr:
14769 case VPSHRDVDZrk:
14770 case VPSHRDVDZrkz:
14771 return true;
14772 }
14773 return false;
14774}
14775
14776bool isPADDW(unsigned Opcode) {
14777 switch (Opcode) {
14778 case MMX_PADDWrm:
14779 case MMX_PADDWrr:
14780 case PADDWrm:
14781 case PADDWrr:
14782 return true;
14783 }
14784 return false;
14785}
14786
14787bool isCVTSI2SD(unsigned Opcode) {
14788 switch (Opcode) {
14789 case CVTSI2SDrm_Int:
14790 case CVTSI2SDrr_Int:
14791 case CVTSI642SDrm_Int:
14792 case CVTSI642SDrr_Int:
14793 return true;
14794 }
14795 return false;
14796}
14797
14798bool isENQCMD(unsigned Opcode) {
14799 switch (Opcode) {
14800 case ENQCMD16:
14801 case ENQCMD32:
14802 case ENQCMD32_EVEX:
14803 case ENQCMD64:
14804 case ENQCMD64_EVEX:
14805 return true;
14806 }
14807 return false;
14808}
14809
14810bool isXSHA1(unsigned Opcode) {
14811 return Opcode == XSHA1;
14812}
14813
14814bool isVFNMADD132SD(unsigned Opcode) {
14815 switch (Opcode) {
14816 case VFNMADD132SDZm_Int:
14817 case VFNMADD132SDZmk_Int:
14818 case VFNMADD132SDZmkz_Int:
14819 case VFNMADD132SDZr_Int:
14820 case VFNMADD132SDZrb_Int:
14821 case VFNMADD132SDZrbk_Int:
14822 case VFNMADD132SDZrbkz_Int:
14823 case VFNMADD132SDZrk_Int:
14824 case VFNMADD132SDZrkz_Int:
14825 case VFNMADD132SDm_Int:
14826 case VFNMADD132SDr_Int:
14827 return true;
14828 }
14829 return false;
14830}
14831
14832bool isMOVZX(unsigned Opcode) {
14833 switch (Opcode) {
14834 case MOVZX16rm16:
14835 case MOVZX16rm8:
14836 case MOVZX16rr16:
14837 case MOVZX16rr8:
14838 case MOVZX32rm16:
14839 case MOVZX32rm8:
14840 case MOVZX32rr16:
14841 case MOVZX32rr8:
14842 case MOVZX64rm16:
14843 case MOVZX64rm8:
14844 case MOVZX64rr16:
14845 case MOVZX64rr8:
14846 return true;
14847 }
14848 return false;
14849}
14850
14851bool isVFIXUPIMMSD(unsigned Opcode) {
14852 switch (Opcode) {
14853 case VFIXUPIMMSDZrmi:
14854 case VFIXUPIMMSDZrmik:
14855 case VFIXUPIMMSDZrmikz:
14856 case VFIXUPIMMSDZrri:
14857 case VFIXUPIMMSDZrrib:
14858 case VFIXUPIMMSDZrribk:
14859 case VFIXUPIMMSDZrribkz:
14860 case VFIXUPIMMSDZrrik:
14861 case VFIXUPIMMSDZrrikz:
14862 return true;
14863 }
14864 return false;
14865}
14866
14867bool isINVD(unsigned Opcode) {
14868 return Opcode == INVD;
14869}
14870
14871bool isVFIXUPIMMPS(unsigned Opcode) {
14872 switch (Opcode) {
14873 case VFIXUPIMMPSZ128rmbi:
14874 case VFIXUPIMMPSZ128rmbik:
14875 case VFIXUPIMMPSZ128rmbikz:
14876 case VFIXUPIMMPSZ128rmi:
14877 case VFIXUPIMMPSZ128rmik:
14878 case VFIXUPIMMPSZ128rmikz:
14879 case VFIXUPIMMPSZ128rri:
14880 case VFIXUPIMMPSZ128rrik:
14881 case VFIXUPIMMPSZ128rrikz:
14882 case VFIXUPIMMPSZ256rmbi:
14883 case VFIXUPIMMPSZ256rmbik:
14884 case VFIXUPIMMPSZ256rmbikz:
14885 case VFIXUPIMMPSZ256rmi:
14886 case VFIXUPIMMPSZ256rmik:
14887 case VFIXUPIMMPSZ256rmikz:
14888 case VFIXUPIMMPSZ256rri:
14889 case VFIXUPIMMPSZ256rrik:
14890 case VFIXUPIMMPSZ256rrikz:
14891 case VFIXUPIMMPSZrmbi:
14892 case VFIXUPIMMPSZrmbik:
14893 case VFIXUPIMMPSZrmbikz:
14894 case VFIXUPIMMPSZrmi:
14895 case VFIXUPIMMPSZrmik:
14896 case VFIXUPIMMPSZrmikz:
14897 case VFIXUPIMMPSZrri:
14898 case VFIXUPIMMPSZrrib:
14899 case VFIXUPIMMPSZrribk:
14900 case VFIXUPIMMPSZrribkz:
14901 case VFIXUPIMMPSZrrik:
14902 case VFIXUPIMMPSZrrikz:
14903 return true;
14904 }
14905 return false;
14906}
14907
14908bool isMOVDQU(unsigned Opcode) {
14909 switch (Opcode) {
14910 case MOVDQUmr:
14911 case MOVDQUrm:
14912 case MOVDQUrr:
14913 case MOVDQUrr_REV:
14914 return true;
14915 }
14916 return false;
14917}
14918
14919bool isVFPCLASSPS(unsigned Opcode) {
14920 switch (Opcode) {
14921 case VFPCLASSPSZ128mbi:
14922 case VFPCLASSPSZ128mbik:
14923 case VFPCLASSPSZ128mi:
14924 case VFPCLASSPSZ128mik:
14925 case VFPCLASSPSZ128ri:
14926 case VFPCLASSPSZ128rik:
14927 case VFPCLASSPSZ256mbi:
14928 case VFPCLASSPSZ256mbik:
14929 case VFPCLASSPSZ256mi:
14930 case VFPCLASSPSZ256mik:
14931 case VFPCLASSPSZ256ri:
14932 case VFPCLASSPSZ256rik:
14933 case VFPCLASSPSZmbi:
14934 case VFPCLASSPSZmbik:
14935 case VFPCLASSPSZmi:
14936 case VFPCLASSPSZmik:
14937 case VFPCLASSPSZri:
14938 case VFPCLASSPSZrik:
14939 return true;
14940 }
14941 return false;
14942}
14943
14944bool isVPERMILPS(unsigned Opcode) {
14945 switch (Opcode) {
14946 case VPERMILPSYmi:
14947 case VPERMILPSYri:
14948 case VPERMILPSYrm:
14949 case VPERMILPSYrr:
14950 case VPERMILPSZ128mbi:
14951 case VPERMILPSZ128mbik:
14952 case VPERMILPSZ128mbikz:
14953 case VPERMILPSZ128mi:
14954 case VPERMILPSZ128mik:
14955 case VPERMILPSZ128mikz:
14956 case VPERMILPSZ128ri:
14957 case VPERMILPSZ128rik:
14958 case VPERMILPSZ128rikz:
14959 case VPERMILPSZ128rm:
14960 case VPERMILPSZ128rmb:
14961 case VPERMILPSZ128rmbk:
14962 case VPERMILPSZ128rmbkz:
14963 case VPERMILPSZ128rmk:
14964 case VPERMILPSZ128rmkz:
14965 case VPERMILPSZ128rr:
14966 case VPERMILPSZ128rrk:
14967 case VPERMILPSZ128rrkz:
14968 case VPERMILPSZ256mbi:
14969 case VPERMILPSZ256mbik:
14970 case VPERMILPSZ256mbikz:
14971 case VPERMILPSZ256mi:
14972 case VPERMILPSZ256mik:
14973 case VPERMILPSZ256mikz:
14974 case VPERMILPSZ256ri:
14975 case VPERMILPSZ256rik:
14976 case VPERMILPSZ256rikz:
14977 case VPERMILPSZ256rm:
14978 case VPERMILPSZ256rmb:
14979 case VPERMILPSZ256rmbk:
14980 case VPERMILPSZ256rmbkz:
14981 case VPERMILPSZ256rmk:
14982 case VPERMILPSZ256rmkz:
14983 case VPERMILPSZ256rr:
14984 case VPERMILPSZ256rrk:
14985 case VPERMILPSZ256rrkz:
14986 case VPERMILPSZmbi:
14987 case VPERMILPSZmbik:
14988 case VPERMILPSZmbikz:
14989 case VPERMILPSZmi:
14990 case VPERMILPSZmik:
14991 case VPERMILPSZmikz:
14992 case VPERMILPSZri:
14993 case VPERMILPSZrik:
14994 case VPERMILPSZrikz:
14995 case VPERMILPSZrm:
14996 case VPERMILPSZrmb:
14997 case VPERMILPSZrmbk:
14998 case VPERMILPSZrmbkz:
14999 case VPERMILPSZrmk:
15000 case VPERMILPSZrmkz:
15001 case VPERMILPSZrr:
15002 case VPERMILPSZrrk:
15003 case VPERMILPSZrrkz:
15004 case VPERMILPSmi:
15005 case VPERMILPSri:
15006 case VPERMILPSrm:
15007 case VPERMILPSrr:
15008 return true;
15009 }
15010 return false;
15011}
15012
15013bool isMOVSQ(unsigned Opcode) {
15014 return Opcode == MOVSQ;
15015}
15016
15017bool isAESDECWIDE128KL(unsigned Opcode) {
15018 return Opcode == AESDECWIDE128KL;
15019}
15020
15021bool isROUNDSS(unsigned Opcode) {
15022 switch (Opcode) {
15023 case ROUNDSSmi_Int:
15024 case ROUNDSSri_Int:
15025 return true;
15026 }
15027 return false;
15028}
15029
15030bool isVPMOVW2M(unsigned Opcode) {
15031 switch (Opcode) {
15032 case VPMOVW2MZ128kr:
15033 case VPMOVW2MZ256kr:
15034 case VPMOVW2MZkr:
15035 return true;
15036 }
15037 return false;
15038}
15039
15040bool isVPSHUFB(unsigned Opcode) {
15041 switch (Opcode) {
15042 case VPSHUFBYrm:
15043 case VPSHUFBYrr:
15044 case VPSHUFBZ128rm:
15045 case VPSHUFBZ128rmk:
15046 case VPSHUFBZ128rmkz:
15047 case VPSHUFBZ128rr:
15048 case VPSHUFBZ128rrk:
15049 case VPSHUFBZ128rrkz:
15050 case VPSHUFBZ256rm:
15051 case VPSHUFBZ256rmk:
15052 case VPSHUFBZ256rmkz:
15053 case VPSHUFBZ256rr:
15054 case VPSHUFBZ256rrk:
15055 case VPSHUFBZ256rrkz:
15056 case VPSHUFBZrm:
15057 case VPSHUFBZrmk:
15058 case VPSHUFBZrmkz:
15059 case VPSHUFBZrr:
15060 case VPSHUFBZrrk:
15061 case VPSHUFBZrrkz:
15062 case VPSHUFBrm:
15063 case VPSHUFBrr:
15064 return true;
15065 }
15066 return false;
15067}
15068
15069bool isVMULSD(unsigned Opcode) {
15070 switch (Opcode) {
15071 case VMULSDZrm_Int:
15072 case VMULSDZrmk_Int:
15073 case VMULSDZrmkz_Int:
15074 case VMULSDZrr_Int:
15075 case VMULSDZrrb_Int:
15076 case VMULSDZrrbk_Int:
15077 case VMULSDZrrbkz_Int:
15078 case VMULSDZrrk_Int:
15079 case VMULSDZrrkz_Int:
15080 case VMULSDrm_Int:
15081 case VMULSDrr_Int:
15082 return true;
15083 }
15084 return false;
15085}
15086
15087bool isVPERMI2W(unsigned Opcode) {
15088 switch (Opcode) {
15089 case VPERMI2WZ128rm:
15090 case VPERMI2WZ128rmk:
15091 case VPERMI2WZ128rmkz:
15092 case VPERMI2WZ128rr:
15093 case VPERMI2WZ128rrk:
15094 case VPERMI2WZ128rrkz:
15095 case VPERMI2WZ256rm:
15096 case VPERMI2WZ256rmk:
15097 case VPERMI2WZ256rmkz:
15098 case VPERMI2WZ256rr:
15099 case VPERMI2WZ256rrk:
15100 case VPERMI2WZ256rrkz:
15101 case VPERMI2WZrm:
15102 case VPERMI2WZrmk:
15103 case VPERMI2WZrmkz:
15104 case VPERMI2WZrr:
15105 case VPERMI2WZrrk:
15106 case VPERMI2WZrrkz:
15107 return true;
15108 }
15109 return false;
15110}
15111
15112bool isVREDUCESS(unsigned Opcode) {
15113 switch (Opcode) {
15114 case VREDUCESSZrmi:
15115 case VREDUCESSZrmik:
15116 case VREDUCESSZrmikz:
15117 case VREDUCESSZrri:
15118 case VREDUCESSZrrib:
15119 case VREDUCESSZrribk:
15120 case VREDUCESSZrribkz:
15121 case VREDUCESSZrrik:
15122 case VREDUCESSZrrikz:
15123 return true;
15124 }
15125 return false;
15126}
15127
15128bool isFST(unsigned Opcode) {
15129 switch (Opcode) {
15130 case ST_F32m:
15131 case ST_F64m:
15132 case ST_Frr:
15133 return true;
15134 }
15135 return false;
15136}
15137
15138bool isVPHSUBW(unsigned Opcode) {
15139 switch (Opcode) {
15140 case VPHSUBWYrm:
15141 case VPHSUBWYrr:
15142 case VPHSUBWrm:
15143 case VPHSUBWrr:
15144 return true;
15145 }
15146 return false;
15147}
15148
15149bool isFRNDINT(unsigned Opcode) {
15150 return Opcode == FRNDINT;
15151}
15152
15153bool isSHR(unsigned Opcode) {
15154 switch (Opcode) {
15155 case SHR16m1:
15156 case SHR16m1_EVEX:
15157 case SHR16m1_ND:
15158 case SHR16m1_NF:
15159 case SHR16m1_NF_ND:
15160 case SHR16mCL:
15161 case SHR16mCL_EVEX:
15162 case SHR16mCL_ND:
15163 case SHR16mCL_NF:
15164 case SHR16mCL_NF_ND:
15165 case SHR16mi:
15166 case SHR16mi_EVEX:
15167 case SHR16mi_ND:
15168 case SHR16mi_NF:
15169 case SHR16mi_NF_ND:
15170 case SHR16r1:
15171 case SHR16r1_EVEX:
15172 case SHR16r1_ND:
15173 case SHR16r1_NF:
15174 case SHR16r1_NF_ND:
15175 case SHR16rCL:
15176 case SHR16rCL_EVEX:
15177 case SHR16rCL_ND:
15178 case SHR16rCL_NF:
15179 case SHR16rCL_NF_ND:
15180 case SHR16ri:
15181 case SHR16ri_EVEX:
15182 case SHR16ri_ND:
15183 case SHR16ri_NF:
15184 case SHR16ri_NF_ND:
15185 case SHR32m1:
15186 case SHR32m1_EVEX:
15187 case SHR32m1_ND:
15188 case SHR32m1_NF:
15189 case SHR32m1_NF_ND:
15190 case SHR32mCL:
15191 case SHR32mCL_EVEX:
15192 case SHR32mCL_ND:
15193 case SHR32mCL_NF:
15194 case SHR32mCL_NF_ND:
15195 case SHR32mi:
15196 case SHR32mi_EVEX:
15197 case SHR32mi_ND:
15198 case SHR32mi_NF:
15199 case SHR32mi_NF_ND:
15200 case SHR32r1:
15201 case SHR32r1_EVEX:
15202 case SHR32r1_ND:
15203 case SHR32r1_NF:
15204 case SHR32r1_NF_ND:
15205 case SHR32rCL:
15206 case SHR32rCL_EVEX:
15207 case SHR32rCL_ND:
15208 case SHR32rCL_NF:
15209 case SHR32rCL_NF_ND:
15210 case SHR32ri:
15211 case SHR32ri_EVEX:
15212 case SHR32ri_ND:
15213 case SHR32ri_NF:
15214 case SHR32ri_NF_ND:
15215 case SHR64m1:
15216 case SHR64m1_EVEX:
15217 case SHR64m1_ND:
15218 case SHR64m1_NF:
15219 case SHR64m1_NF_ND:
15220 case SHR64mCL:
15221 case SHR64mCL_EVEX:
15222 case SHR64mCL_ND:
15223 case SHR64mCL_NF:
15224 case SHR64mCL_NF_ND:
15225 case SHR64mi:
15226 case SHR64mi_EVEX:
15227 case SHR64mi_ND:
15228 case SHR64mi_NF:
15229 case SHR64mi_NF_ND:
15230 case SHR64r1:
15231 case SHR64r1_EVEX:
15232 case SHR64r1_ND:
15233 case SHR64r1_NF:
15234 case SHR64r1_NF_ND:
15235 case SHR64rCL:
15236 case SHR64rCL_EVEX:
15237 case SHR64rCL_ND:
15238 case SHR64rCL_NF:
15239 case SHR64rCL_NF_ND:
15240 case SHR64ri:
15241 case SHR64ri_EVEX:
15242 case SHR64ri_ND:
15243 case SHR64ri_NF:
15244 case SHR64ri_NF_ND:
15245 case SHR8m1:
15246 case SHR8m1_EVEX:
15247 case SHR8m1_ND:
15248 case SHR8m1_NF:
15249 case SHR8m1_NF_ND:
15250 case SHR8mCL:
15251 case SHR8mCL_EVEX:
15252 case SHR8mCL_ND:
15253 case SHR8mCL_NF:
15254 case SHR8mCL_NF_ND:
15255 case SHR8mi:
15256 case SHR8mi_EVEX:
15257 case SHR8mi_ND:
15258 case SHR8mi_NF:
15259 case SHR8mi_NF_ND:
15260 case SHR8r1:
15261 case SHR8r1_EVEX:
15262 case SHR8r1_ND:
15263 case SHR8r1_NF:
15264 case SHR8r1_NF_ND:
15265 case SHR8rCL:
15266 case SHR8rCL_EVEX:
15267 case SHR8rCL_ND:
15268 case SHR8rCL_NF:
15269 case SHR8rCL_NF_ND:
15270 case SHR8ri:
15271 case SHR8ri_EVEX:
15272 case SHR8ri_ND:
15273 case SHR8ri_NF:
15274 case SHR8ri_NF_ND:
15275 return true;
15276 }
15277 return false;
15278}
15279
15280bool isLOOPNE(unsigned Opcode) {
15281 return Opcode == LOOPNE;
15282}
15283
15284bool isVCVTTPH2UQQ(unsigned Opcode) {
15285 switch (Opcode) {
15286 case VCVTTPH2UQQZ128rm:
15287 case VCVTTPH2UQQZ128rmb:
15288 case VCVTTPH2UQQZ128rmbk:
15289 case VCVTTPH2UQQZ128rmbkz:
15290 case VCVTTPH2UQQZ128rmk:
15291 case VCVTTPH2UQQZ128rmkz:
15292 case VCVTTPH2UQQZ128rr:
15293 case VCVTTPH2UQQZ128rrk:
15294 case VCVTTPH2UQQZ128rrkz:
15295 case VCVTTPH2UQQZ256rm:
15296 case VCVTTPH2UQQZ256rmb:
15297 case VCVTTPH2UQQZ256rmbk:
15298 case VCVTTPH2UQQZ256rmbkz:
15299 case VCVTTPH2UQQZ256rmk:
15300 case VCVTTPH2UQQZ256rmkz:
15301 case VCVTTPH2UQQZ256rr:
15302 case VCVTTPH2UQQZ256rrk:
15303 case VCVTTPH2UQQZ256rrkz:
15304 case VCVTTPH2UQQZrm:
15305 case VCVTTPH2UQQZrmb:
15306 case VCVTTPH2UQQZrmbk:
15307 case VCVTTPH2UQQZrmbkz:
15308 case VCVTTPH2UQQZrmk:
15309 case VCVTTPH2UQQZrmkz:
15310 case VCVTTPH2UQQZrr:
15311 case VCVTTPH2UQQZrrb:
15312 case VCVTTPH2UQQZrrbk:
15313 case VCVTTPH2UQQZrrbkz:
15314 case VCVTTPH2UQQZrrk:
15315 case VCVTTPH2UQQZrrkz:
15316 return true;
15317 }
15318 return false;
15319}
15320
15321bool isSHA1NEXTE(unsigned Opcode) {
15322 switch (Opcode) {
15323 case SHA1NEXTErm:
15324 case SHA1NEXTErr:
15325 return true;
15326 }
15327 return false;
15328}
15329
15330bool isVFMADD132SD(unsigned Opcode) {
15331 switch (Opcode) {
15332 case VFMADD132SDZm_Int:
15333 case VFMADD132SDZmk_Int:
15334 case VFMADD132SDZmkz_Int:
15335 case VFMADD132SDZr_Int:
15336 case VFMADD132SDZrb_Int:
15337 case VFMADD132SDZrbk_Int:
15338 case VFMADD132SDZrbkz_Int:
15339 case VFMADD132SDZrk_Int:
15340 case VFMADD132SDZrkz_Int:
15341 case VFMADD132SDm_Int:
15342 case VFMADD132SDr_Int:
15343 return true;
15344 }
15345 return false;
15346}
15347
15348bool isPSRAW(unsigned Opcode) {
15349 switch (Opcode) {
15350 case MMX_PSRAWri:
15351 case MMX_PSRAWrm:
15352 case MMX_PSRAWrr:
15353 case PSRAWri:
15354 case PSRAWrm:
15355 case PSRAWrr:
15356 return true;
15357 }
15358 return false;
15359}
15360
15361bool isVPBROADCASTQ(unsigned Opcode) {
15362 switch (Opcode) {
15363 case VPBROADCASTQYrm:
15364 case VPBROADCASTQYrr:
15365 case VPBROADCASTQZ128rm:
15366 case VPBROADCASTQZ128rmk:
15367 case VPBROADCASTQZ128rmkz:
15368 case VPBROADCASTQZ128rr:
15369 case VPBROADCASTQZ128rrk:
15370 case VPBROADCASTQZ128rrkz:
15371 case VPBROADCASTQZ256rm:
15372 case VPBROADCASTQZ256rmk:
15373 case VPBROADCASTQZ256rmkz:
15374 case VPBROADCASTQZ256rr:
15375 case VPBROADCASTQZ256rrk:
15376 case VPBROADCASTQZ256rrkz:
15377 case VPBROADCASTQZrm:
15378 case VPBROADCASTQZrmk:
15379 case VPBROADCASTQZrmkz:
15380 case VPBROADCASTQZrr:
15381 case VPBROADCASTQZrrk:
15382 case VPBROADCASTQZrrkz:
15383 case VPBROADCASTQrZ128rr:
15384 case VPBROADCASTQrZ128rrk:
15385 case VPBROADCASTQrZ128rrkz:
15386 case VPBROADCASTQrZ256rr:
15387 case VPBROADCASTQrZ256rrk:
15388 case VPBROADCASTQrZ256rrkz:
15389 case VPBROADCASTQrZrr:
15390 case VPBROADCASTQrZrrk:
15391 case VPBROADCASTQrZrrkz:
15392 case VPBROADCASTQrm:
15393 case VPBROADCASTQrr:
15394 return true;
15395 }
15396 return false;
15397}
15398
15399bool isCLC(unsigned Opcode) {
15400 return Opcode == CLC;
15401}
15402
15403bool isPOPAW(unsigned Opcode) {
15404 return Opcode == POPA16;
15405}
15406
15407bool isTCMMIMFP16PS(unsigned Opcode) {
15408 return Opcode == TCMMIMFP16PS;
15409}
15410
15411bool isVCVTQQ2PH(unsigned Opcode) {
15412 switch (Opcode) {
15413 case VCVTQQ2PHZ128rm:
15414 case VCVTQQ2PHZ128rmb:
15415 case VCVTQQ2PHZ128rmbk:
15416 case VCVTQQ2PHZ128rmbkz:
15417 case VCVTQQ2PHZ128rmk:
15418 case VCVTQQ2PHZ128rmkz:
15419 case VCVTQQ2PHZ128rr:
15420 case VCVTQQ2PHZ128rrk:
15421 case VCVTQQ2PHZ128rrkz:
15422 case VCVTQQ2PHZ256rm:
15423 case VCVTQQ2PHZ256rmb:
15424 case VCVTQQ2PHZ256rmbk:
15425 case VCVTQQ2PHZ256rmbkz:
15426 case VCVTQQ2PHZ256rmk:
15427 case VCVTQQ2PHZ256rmkz:
15428 case VCVTQQ2PHZ256rr:
15429 case VCVTQQ2PHZ256rrk:
15430 case VCVTQQ2PHZ256rrkz:
15431 case VCVTQQ2PHZrm:
15432 case VCVTQQ2PHZrmb:
15433 case VCVTQQ2PHZrmbk:
15434 case VCVTQQ2PHZrmbkz:
15435 case VCVTQQ2PHZrmk:
15436 case VCVTQQ2PHZrmkz:
15437 case VCVTQQ2PHZrr:
15438 case VCVTQQ2PHZrrb:
15439 case VCVTQQ2PHZrrbk:
15440 case VCVTQQ2PHZrrbkz:
15441 case VCVTQQ2PHZrrk:
15442 case VCVTQQ2PHZrrkz:
15443 return true;
15444 }
15445 return false;
15446}
15447
15448bool isVCVTTPS2UQQ(unsigned Opcode) {
15449 switch (Opcode) {
15450 case VCVTTPS2UQQZ128rm:
15451 case VCVTTPS2UQQZ128rmb:
15452 case VCVTTPS2UQQZ128rmbk:
15453 case VCVTTPS2UQQZ128rmbkz:
15454 case VCVTTPS2UQQZ128rmk:
15455 case VCVTTPS2UQQZ128rmkz:
15456 case VCVTTPS2UQQZ128rr:
15457 case VCVTTPS2UQQZ128rrk:
15458 case VCVTTPS2UQQZ128rrkz:
15459 case VCVTTPS2UQQZ256rm:
15460 case VCVTTPS2UQQZ256rmb:
15461 case VCVTTPS2UQQZ256rmbk:
15462 case VCVTTPS2UQQZ256rmbkz:
15463 case VCVTTPS2UQQZ256rmk:
15464 case VCVTTPS2UQQZ256rmkz:
15465 case VCVTTPS2UQQZ256rr:
15466 case VCVTTPS2UQQZ256rrk:
15467 case VCVTTPS2UQQZ256rrkz:
15468 case VCVTTPS2UQQZrm:
15469 case VCVTTPS2UQQZrmb:
15470 case VCVTTPS2UQQZrmbk:
15471 case VCVTTPS2UQQZrmbkz:
15472 case VCVTTPS2UQQZrmk:
15473 case VCVTTPS2UQQZrmkz:
15474 case VCVTTPS2UQQZrr:
15475 case VCVTTPS2UQQZrrb:
15476 case VCVTTPS2UQQZrrbk:
15477 case VCVTTPS2UQQZrrbkz:
15478 case VCVTTPS2UQQZrrk:
15479 case VCVTTPS2UQQZrrkz:
15480 return true;
15481 }
15482 return false;
15483}
15484
15485bool isVMOVUPD(unsigned Opcode) {
15486 switch (Opcode) {
15487 case VMOVUPDYmr:
15488 case VMOVUPDYrm:
15489 case VMOVUPDYrr:
15490 case VMOVUPDYrr_REV:
15491 case VMOVUPDZ128mr:
15492 case VMOVUPDZ128mrk:
15493 case VMOVUPDZ128rm:
15494 case VMOVUPDZ128rmk:
15495 case VMOVUPDZ128rmkz:
15496 case VMOVUPDZ128rr:
15497 case VMOVUPDZ128rr_REV:
15498 case VMOVUPDZ128rrk:
15499 case VMOVUPDZ128rrk_REV:
15500 case VMOVUPDZ128rrkz:
15501 case VMOVUPDZ128rrkz_REV:
15502 case VMOVUPDZ256mr:
15503 case VMOVUPDZ256mrk:
15504 case VMOVUPDZ256rm:
15505 case VMOVUPDZ256rmk:
15506 case VMOVUPDZ256rmkz:
15507 case VMOVUPDZ256rr:
15508 case VMOVUPDZ256rr_REV:
15509 case VMOVUPDZ256rrk:
15510 case VMOVUPDZ256rrk_REV:
15511 case VMOVUPDZ256rrkz:
15512 case VMOVUPDZ256rrkz_REV:
15513 case VMOVUPDZmr:
15514 case VMOVUPDZmrk:
15515 case VMOVUPDZrm:
15516 case VMOVUPDZrmk:
15517 case VMOVUPDZrmkz:
15518 case VMOVUPDZrr:
15519 case VMOVUPDZrr_REV:
15520 case VMOVUPDZrrk:
15521 case VMOVUPDZrrk_REV:
15522 case VMOVUPDZrrkz:
15523 case VMOVUPDZrrkz_REV:
15524 case VMOVUPDmr:
15525 case VMOVUPDrm:
15526 case VMOVUPDrr:
15527 case VMOVUPDrr_REV:
15528 return true;
15529 }
15530 return false;
15531}
15532
15533bool isFPTAN(unsigned Opcode) {
15534 return Opcode == FPTAN;
15535}
15536
15537bool isVMASKMOVPD(unsigned Opcode) {
15538 switch (Opcode) {
15539 case VMASKMOVPDYmr:
15540 case VMASKMOVPDYrm:
15541 case VMASKMOVPDmr:
15542 case VMASKMOVPDrm:
15543 return true;
15544 }
15545 return false;
15546}
15547
15548bool isVMOVLHPS(unsigned Opcode) {
15549 switch (Opcode) {
15550 case VMOVLHPSZrr:
15551 case VMOVLHPSrr:
15552 return true;
15553 }
15554 return false;
15555}
15556
15557bool isAESKEYGENASSIST(unsigned Opcode) {
15558 switch (Opcode) {
15559 case AESKEYGENASSISTrmi:
15560 case AESKEYGENASSISTrri:
15561 return true;
15562 }
15563 return false;
15564}
15565
15566bool isXSAVEOPT64(unsigned Opcode) {
15567 return Opcode == XSAVEOPT64;
15568}
15569
15570bool isXSAVEC(unsigned Opcode) {
15571 return Opcode == XSAVEC;
15572}
15573
15574bool isVPLZCNTQ(unsigned Opcode) {
15575 switch (Opcode) {
15576 case VPLZCNTQZ128rm:
15577 case VPLZCNTQZ128rmb:
15578 case VPLZCNTQZ128rmbk:
15579 case VPLZCNTQZ128rmbkz:
15580 case VPLZCNTQZ128rmk:
15581 case VPLZCNTQZ128rmkz:
15582 case VPLZCNTQZ128rr:
15583 case VPLZCNTQZ128rrk:
15584 case VPLZCNTQZ128rrkz:
15585 case VPLZCNTQZ256rm:
15586 case VPLZCNTQZ256rmb:
15587 case VPLZCNTQZ256rmbk:
15588 case VPLZCNTQZ256rmbkz:
15589 case VPLZCNTQZ256rmk:
15590 case VPLZCNTQZ256rmkz:
15591 case VPLZCNTQZ256rr:
15592 case VPLZCNTQZ256rrk:
15593 case VPLZCNTQZ256rrkz:
15594 case VPLZCNTQZrm:
15595 case VPLZCNTQZrmb:
15596 case VPLZCNTQZrmbk:
15597 case VPLZCNTQZrmbkz:
15598 case VPLZCNTQZrmk:
15599 case VPLZCNTQZrmkz:
15600 case VPLZCNTQZrr:
15601 case VPLZCNTQZrrk:
15602 case VPLZCNTQZrrkz:
15603 return true;
15604 }
15605 return false;
15606}
15607
15608bool isVPSUBW(unsigned Opcode) {
15609 switch (Opcode) {
15610 case VPSUBWYrm:
15611 case VPSUBWYrr:
15612 case VPSUBWZ128rm:
15613 case VPSUBWZ128rmk:
15614 case VPSUBWZ128rmkz:
15615 case VPSUBWZ128rr:
15616 case VPSUBWZ128rrk:
15617 case VPSUBWZ128rrkz:
15618 case VPSUBWZ256rm:
15619 case VPSUBWZ256rmk:
15620 case VPSUBWZ256rmkz:
15621 case VPSUBWZ256rr:
15622 case VPSUBWZ256rrk:
15623 case VPSUBWZ256rrkz:
15624 case VPSUBWZrm:
15625 case VPSUBWZrmk:
15626 case VPSUBWZrmkz:
15627 case VPSUBWZrr:
15628 case VPSUBWZrrk:
15629 case VPSUBWZrrkz:
15630 case VPSUBWrm:
15631 case VPSUBWrr:
15632 return true;
15633 }
15634 return false;
15635}
15636
15637bool isCMPCCXADD(unsigned Opcode) {
15638 switch (Opcode) {
15639 case CMPCCXADDmr32:
15640 case CMPCCXADDmr32_EVEX:
15641 case CMPCCXADDmr64:
15642 case CMPCCXADDmr64_EVEX:
15643 return true;
15644 }
15645 return false;
15646}
15647
15648bool isVFMSUBADD213PH(unsigned Opcode) {
15649 switch (Opcode) {
15650 case VFMSUBADD213PHZ128m:
15651 case VFMSUBADD213PHZ128mb:
15652 case VFMSUBADD213PHZ128mbk:
15653 case VFMSUBADD213PHZ128mbkz:
15654 case VFMSUBADD213PHZ128mk:
15655 case VFMSUBADD213PHZ128mkz:
15656 case VFMSUBADD213PHZ128r:
15657 case VFMSUBADD213PHZ128rk:
15658 case VFMSUBADD213PHZ128rkz:
15659 case VFMSUBADD213PHZ256m:
15660 case VFMSUBADD213PHZ256mb:
15661 case VFMSUBADD213PHZ256mbk:
15662 case VFMSUBADD213PHZ256mbkz:
15663 case VFMSUBADD213PHZ256mk:
15664 case VFMSUBADD213PHZ256mkz:
15665 case VFMSUBADD213PHZ256r:
15666 case VFMSUBADD213PHZ256rk:
15667 case VFMSUBADD213PHZ256rkz:
15668 case VFMSUBADD213PHZm:
15669 case VFMSUBADD213PHZmb:
15670 case VFMSUBADD213PHZmbk:
15671 case VFMSUBADD213PHZmbkz:
15672 case VFMSUBADD213PHZmk:
15673 case VFMSUBADD213PHZmkz:
15674 case VFMSUBADD213PHZr:
15675 case VFMSUBADD213PHZrb:
15676 case VFMSUBADD213PHZrbk:
15677 case VFMSUBADD213PHZrbkz:
15678 case VFMSUBADD213PHZrk:
15679 case VFMSUBADD213PHZrkz:
15680 return true;
15681 }
15682 return false;
15683}
15684
15685bool isVFMADDSUBPD(unsigned Opcode) {
15686 switch (Opcode) {
15687 case VFMADDSUBPD4Ymr:
15688 case VFMADDSUBPD4Yrm:
15689 case VFMADDSUBPD4Yrr:
15690 case VFMADDSUBPD4Yrr_REV:
15691 case VFMADDSUBPD4mr:
15692 case VFMADDSUBPD4rm:
15693 case VFMADDSUBPD4rr:
15694 case VFMADDSUBPD4rr_REV:
15695 return true;
15696 }
15697 return false;
15698}
15699
15700bool isVPMINSW(unsigned Opcode) {
15701 switch (Opcode) {
15702 case VPMINSWYrm:
15703 case VPMINSWYrr:
15704 case VPMINSWZ128rm:
15705 case VPMINSWZ128rmk:
15706 case VPMINSWZ128rmkz:
15707 case VPMINSWZ128rr:
15708 case VPMINSWZ128rrk:
15709 case VPMINSWZ128rrkz:
15710 case VPMINSWZ256rm:
15711 case VPMINSWZ256rmk:
15712 case VPMINSWZ256rmkz:
15713 case VPMINSWZ256rr:
15714 case VPMINSWZ256rrk:
15715 case VPMINSWZ256rrkz:
15716 case VPMINSWZrm:
15717 case VPMINSWZrmk:
15718 case VPMINSWZrmkz:
15719 case VPMINSWZrr:
15720 case VPMINSWZrrk:
15721 case VPMINSWZrrkz:
15722 case VPMINSWrm:
15723 case VPMINSWrr:
15724 return true;
15725 }
15726 return false;
15727}
15728
15729bool isVFNMSUB132PS(unsigned Opcode) {
15730 switch (Opcode) {
15731 case VFNMSUB132PSYm:
15732 case VFNMSUB132PSYr:
15733 case VFNMSUB132PSZ128m:
15734 case VFNMSUB132PSZ128mb:
15735 case VFNMSUB132PSZ128mbk:
15736 case VFNMSUB132PSZ128mbkz:
15737 case VFNMSUB132PSZ128mk:
15738 case VFNMSUB132PSZ128mkz:
15739 case VFNMSUB132PSZ128r:
15740 case VFNMSUB132PSZ128rk:
15741 case VFNMSUB132PSZ128rkz:
15742 case VFNMSUB132PSZ256m:
15743 case VFNMSUB132PSZ256mb:
15744 case VFNMSUB132PSZ256mbk:
15745 case VFNMSUB132PSZ256mbkz:
15746 case VFNMSUB132PSZ256mk:
15747 case VFNMSUB132PSZ256mkz:
15748 case VFNMSUB132PSZ256r:
15749 case VFNMSUB132PSZ256rk:
15750 case VFNMSUB132PSZ256rkz:
15751 case VFNMSUB132PSZm:
15752 case VFNMSUB132PSZmb:
15753 case VFNMSUB132PSZmbk:
15754 case VFNMSUB132PSZmbkz:
15755 case VFNMSUB132PSZmk:
15756 case VFNMSUB132PSZmkz:
15757 case VFNMSUB132PSZr:
15758 case VFNMSUB132PSZrb:
15759 case VFNMSUB132PSZrbk:
15760 case VFNMSUB132PSZrbkz:
15761 case VFNMSUB132PSZrk:
15762 case VFNMSUB132PSZrkz:
15763 case VFNMSUB132PSm:
15764 case VFNMSUB132PSr:
15765 return true;
15766 }
15767 return false;
15768}
15769
15770bool isVMOVAPS(unsigned Opcode) {
15771 switch (Opcode) {
15772 case VMOVAPSYmr:
15773 case VMOVAPSYrm:
15774 case VMOVAPSYrr:
15775 case VMOVAPSYrr_REV:
15776 case VMOVAPSZ128mr:
15777 case VMOVAPSZ128mrk:
15778 case VMOVAPSZ128rm:
15779 case VMOVAPSZ128rmk:
15780 case VMOVAPSZ128rmkz:
15781 case VMOVAPSZ128rr:
15782 case VMOVAPSZ128rr_REV:
15783 case VMOVAPSZ128rrk:
15784 case VMOVAPSZ128rrk_REV:
15785 case VMOVAPSZ128rrkz:
15786 case VMOVAPSZ128rrkz_REV:
15787 case VMOVAPSZ256mr:
15788 case VMOVAPSZ256mrk:
15789 case VMOVAPSZ256rm:
15790 case VMOVAPSZ256rmk:
15791 case VMOVAPSZ256rmkz:
15792 case VMOVAPSZ256rr:
15793 case VMOVAPSZ256rr_REV:
15794 case VMOVAPSZ256rrk:
15795 case VMOVAPSZ256rrk_REV:
15796 case VMOVAPSZ256rrkz:
15797 case VMOVAPSZ256rrkz_REV:
15798 case VMOVAPSZmr:
15799 case VMOVAPSZmrk:
15800 case VMOVAPSZrm:
15801 case VMOVAPSZrmk:
15802 case VMOVAPSZrmkz:
15803 case VMOVAPSZrr:
15804 case VMOVAPSZrr_REV:
15805 case VMOVAPSZrrk:
15806 case VMOVAPSZrrk_REV:
15807 case VMOVAPSZrrkz:
15808 case VMOVAPSZrrkz_REV:
15809 case VMOVAPSmr:
15810 case VMOVAPSrm:
15811 case VMOVAPSrr:
15812 case VMOVAPSrr_REV:
15813 return true;
15814 }
15815 return false;
15816}
15817
15818bool isVPEXTRQ(unsigned Opcode) {
15819 switch (Opcode) {
15820 case VPEXTRQZmri:
15821 case VPEXTRQZrri:
15822 case VPEXTRQmri:
15823 case VPEXTRQrri:
15824 return true;
15825 }
15826 return false;
15827}
15828
15829bool isVSCALEFSH(unsigned Opcode) {
15830 switch (Opcode) {
15831 case VSCALEFSHZrm:
15832 case VSCALEFSHZrmk:
15833 case VSCALEFSHZrmkz:
15834 case VSCALEFSHZrr:
15835 case VSCALEFSHZrrb_Int:
15836 case VSCALEFSHZrrbk_Int:
15837 case VSCALEFSHZrrbkz_Int:
15838 case VSCALEFSHZrrk:
15839 case VSCALEFSHZrrkz:
15840 return true;
15841 }
15842 return false;
15843}
15844
15845bool isVCVTPD2PS(unsigned Opcode) {
15846 switch (Opcode) {
15847 case VCVTPD2PSYrm:
15848 case VCVTPD2PSYrr:
15849 case VCVTPD2PSZ128rm:
15850 case VCVTPD2PSZ128rmb:
15851 case VCVTPD2PSZ128rmbk:
15852 case VCVTPD2PSZ128rmbkz:
15853 case VCVTPD2PSZ128rmk:
15854 case VCVTPD2PSZ128rmkz:
15855 case VCVTPD2PSZ128rr:
15856 case VCVTPD2PSZ128rrk:
15857 case VCVTPD2PSZ128rrkz:
15858 case VCVTPD2PSZ256rm:
15859 case VCVTPD2PSZ256rmb:
15860 case VCVTPD2PSZ256rmbk:
15861 case VCVTPD2PSZ256rmbkz:
15862 case VCVTPD2PSZ256rmk:
15863 case VCVTPD2PSZ256rmkz:
15864 case VCVTPD2PSZ256rr:
15865 case VCVTPD2PSZ256rrk:
15866 case VCVTPD2PSZ256rrkz:
15867 case VCVTPD2PSZrm:
15868 case VCVTPD2PSZrmb:
15869 case VCVTPD2PSZrmbk:
15870 case VCVTPD2PSZrmbkz:
15871 case VCVTPD2PSZrmk:
15872 case VCVTPD2PSZrmkz:
15873 case VCVTPD2PSZrr:
15874 case VCVTPD2PSZrrb:
15875 case VCVTPD2PSZrrbk:
15876 case VCVTPD2PSZrrbkz:
15877 case VCVTPD2PSZrrk:
15878 case VCVTPD2PSZrrkz:
15879 case VCVTPD2PSrm:
15880 case VCVTPD2PSrr:
15881 return true;
15882 }
15883 return false;
15884}
15885
15886bool isCLGI(unsigned Opcode) {
15887 return Opcode == CLGI;
15888}
15889
15890bool isVAESDEC(unsigned Opcode) {
15891 switch (Opcode) {
15892 case VAESDECYrm:
15893 case VAESDECYrr:
15894 case VAESDECZ128rm:
15895 case VAESDECZ128rr:
15896 case VAESDECZ256rm:
15897 case VAESDECZ256rr:
15898 case VAESDECZrm:
15899 case VAESDECZrr:
15900 case VAESDECrm:
15901 case VAESDECrr:
15902 return true;
15903 }
15904 return false;
15905}
15906
15907bool isPFMUL(unsigned Opcode) {
15908 switch (Opcode) {
15909 case PFMULrm:
15910 case PFMULrr:
15911 return true;
15912 }
15913 return false;
15914}
15915
15916bool isVCVTBIASPH2BF8S(unsigned Opcode) {
15917 switch (Opcode) {
15918 case VCVTBIASPH2BF8SZ128rm:
15919 case VCVTBIASPH2BF8SZ128rmb:
15920 case VCVTBIASPH2BF8SZ128rmbk:
15921 case VCVTBIASPH2BF8SZ128rmbkz:
15922 case VCVTBIASPH2BF8SZ128rmk:
15923 case VCVTBIASPH2BF8SZ128rmkz:
15924 case VCVTBIASPH2BF8SZ128rr:
15925 case VCVTBIASPH2BF8SZ128rrk:
15926 case VCVTBIASPH2BF8SZ128rrkz:
15927 case VCVTBIASPH2BF8SZ256rm:
15928 case VCVTBIASPH2BF8SZ256rmb:
15929 case VCVTBIASPH2BF8SZ256rmbk:
15930 case VCVTBIASPH2BF8SZ256rmbkz:
15931 case VCVTBIASPH2BF8SZ256rmk:
15932 case VCVTBIASPH2BF8SZ256rmkz:
15933 case VCVTBIASPH2BF8SZ256rr:
15934 case VCVTBIASPH2BF8SZ256rrk:
15935 case VCVTBIASPH2BF8SZ256rrkz:
15936 case VCVTBIASPH2BF8SZrm:
15937 case VCVTBIASPH2BF8SZrmb:
15938 case VCVTBIASPH2BF8SZrmbk:
15939 case VCVTBIASPH2BF8SZrmbkz:
15940 case VCVTBIASPH2BF8SZrmk:
15941 case VCVTBIASPH2BF8SZrmkz:
15942 case VCVTBIASPH2BF8SZrr:
15943 case VCVTBIASPH2BF8SZrrk:
15944 case VCVTBIASPH2BF8SZrrkz:
15945 return true;
15946 }
15947 return false;
15948}
15949
15950bool isMOVDIRI(unsigned Opcode) {
15951 switch (Opcode) {
15952 case MOVDIRI32:
15953 case MOVDIRI32_EVEX:
15954 case MOVDIRI64:
15955 case MOVDIRI64_EVEX:
15956 return true;
15957 }
15958 return false;
15959}
15960
15961bool isSHUFPS(unsigned Opcode) {
15962 switch (Opcode) {
15963 case SHUFPSrmi:
15964 case SHUFPSrri:
15965 return true;
15966 }
15967 return false;
15968}
15969
15970bool isVFNMSUB231SS(unsigned Opcode) {
15971 switch (Opcode) {
15972 case VFNMSUB231SSZm_Int:
15973 case VFNMSUB231SSZmk_Int:
15974 case VFNMSUB231SSZmkz_Int:
15975 case VFNMSUB231SSZr_Int:
15976 case VFNMSUB231SSZrb_Int:
15977 case VFNMSUB231SSZrbk_Int:
15978 case VFNMSUB231SSZrbkz_Int:
15979 case VFNMSUB231SSZrk_Int:
15980 case VFNMSUB231SSZrkz_Int:
15981 case VFNMSUB231SSm_Int:
15982 case VFNMSUB231SSr_Int:
15983 return true;
15984 }
15985 return false;
15986}
15987
15988bool isVMWRITE(unsigned Opcode) {
15989 switch (Opcode) {
15990 case VMWRITE32rm:
15991 case VMWRITE32rr:
15992 case VMWRITE64rm:
15993 case VMWRITE64rr:
15994 return true;
15995 }
15996 return false;
15997}
15998
15999bool isVINSERTF128(unsigned Opcode) {
16000 switch (Opcode) {
16001 case VINSERTF128rmi:
16002 case VINSERTF128rri:
16003 return true;
16004 }
16005 return false;
16006}
16007
16008bool isFISUBR(unsigned Opcode) {
16009 switch (Opcode) {
16010 case SUBR_FI16m:
16011 case SUBR_FI32m:
16012 return true;
16013 }
16014 return false;
16015}
16016
16017bool isVINSERTI32X4(unsigned Opcode) {
16018 switch (Opcode) {
16019 case VINSERTI32X4Z256rmi:
16020 case VINSERTI32X4Z256rmik:
16021 case VINSERTI32X4Z256rmikz:
16022 case VINSERTI32X4Z256rri:
16023 case VINSERTI32X4Z256rrik:
16024 case VINSERTI32X4Z256rrikz:
16025 case VINSERTI32X4Zrmi:
16026 case VINSERTI32X4Zrmik:
16027 case VINSERTI32X4Zrmikz:
16028 case VINSERTI32X4Zrri:
16029 case VINSERTI32X4Zrrik:
16030 case VINSERTI32X4Zrrikz:
16031 return true;
16032 }
16033 return false;
16034}
16035
16036bool isVPSLLDQ(unsigned Opcode) {
16037 switch (Opcode) {
16038 case VPSLLDQYri:
16039 case VPSLLDQZ128mi:
16040 case VPSLLDQZ128ri:
16041 case VPSLLDQZ256mi:
16042 case VPSLLDQZ256ri:
16043 case VPSLLDQZmi:
16044 case VPSLLDQZri:
16045 case VPSLLDQri:
16046 return true;
16047 }
16048 return false;
16049}
16050
16051bool isPOPCNT(unsigned Opcode) {
16052 switch (Opcode) {
16053 case POPCNT16rm:
16054 case POPCNT16rm_EVEX:
16055 case POPCNT16rm_NF:
16056 case POPCNT16rr:
16057 case POPCNT16rr_EVEX:
16058 case POPCNT16rr_NF:
16059 case POPCNT32rm:
16060 case POPCNT32rm_EVEX:
16061 case POPCNT32rm_NF:
16062 case POPCNT32rr:
16063 case POPCNT32rr_EVEX:
16064 case POPCNT32rr_NF:
16065 case POPCNT64rm:
16066 case POPCNT64rm_EVEX:
16067 case POPCNT64rm_NF:
16068 case POPCNT64rr:
16069 case POPCNT64rr_EVEX:
16070 case POPCNT64rr_NF:
16071 return true;
16072 }
16073 return false;
16074}
16075
16076bool isVXORPD(unsigned Opcode) {
16077 switch (Opcode) {
16078 case VXORPDYrm:
16079 case VXORPDYrr:
16080 case VXORPDZ128rm:
16081 case VXORPDZ128rmb:
16082 case VXORPDZ128rmbk:
16083 case VXORPDZ128rmbkz:
16084 case VXORPDZ128rmk:
16085 case VXORPDZ128rmkz:
16086 case VXORPDZ128rr:
16087 case VXORPDZ128rrk:
16088 case VXORPDZ128rrkz:
16089 case VXORPDZ256rm:
16090 case VXORPDZ256rmb:
16091 case VXORPDZ256rmbk:
16092 case VXORPDZ256rmbkz:
16093 case VXORPDZ256rmk:
16094 case VXORPDZ256rmkz:
16095 case VXORPDZ256rr:
16096 case VXORPDZ256rrk:
16097 case VXORPDZ256rrkz:
16098 case VXORPDZrm:
16099 case VXORPDZrmb:
16100 case VXORPDZrmbk:
16101 case VXORPDZrmbkz:
16102 case VXORPDZrmk:
16103 case VXORPDZrmkz:
16104 case VXORPDZrr:
16105 case VXORPDZrrk:
16106 case VXORPDZrrkz:
16107 case VXORPDrm:
16108 case VXORPDrr:
16109 return true;
16110 }
16111 return false;
16112}
16113
16114bool isXLATB(unsigned Opcode) {
16115 return Opcode == XLAT;
16116}
16117
16118bool isDIV(unsigned Opcode) {
16119 switch (Opcode) {
16120 case DIV16m:
16121 case DIV16m_EVEX:
16122 case DIV16m_NF:
16123 case DIV16r:
16124 case DIV16r_EVEX:
16125 case DIV16r_NF:
16126 case DIV32m:
16127 case DIV32m_EVEX:
16128 case DIV32m_NF:
16129 case DIV32r:
16130 case DIV32r_EVEX:
16131 case DIV32r_NF:
16132 case DIV64m:
16133 case DIV64m_EVEX:
16134 case DIV64m_NF:
16135 case DIV64r:
16136 case DIV64r_EVEX:
16137 case DIV64r_NF:
16138 case DIV8m:
16139 case DIV8m_EVEX:
16140 case DIV8m_NF:
16141 case DIV8r:
16142 case DIV8r_EVEX:
16143 case DIV8r_NF:
16144 return true;
16145 }
16146 return false;
16147}
16148
16149bool isVPSHLDVQ(unsigned Opcode) {
16150 switch (Opcode) {
16151 case VPSHLDVQZ128m:
16152 case VPSHLDVQZ128mb:
16153 case VPSHLDVQZ128mbk:
16154 case VPSHLDVQZ128mbkz:
16155 case VPSHLDVQZ128mk:
16156 case VPSHLDVQZ128mkz:
16157 case VPSHLDVQZ128r:
16158 case VPSHLDVQZ128rk:
16159 case VPSHLDVQZ128rkz:
16160 case VPSHLDVQZ256m:
16161 case VPSHLDVQZ256mb:
16162 case VPSHLDVQZ256mbk:
16163 case VPSHLDVQZ256mbkz:
16164 case VPSHLDVQZ256mk:
16165 case VPSHLDVQZ256mkz:
16166 case VPSHLDVQZ256r:
16167 case VPSHLDVQZ256rk:
16168 case VPSHLDVQZ256rkz:
16169 case VPSHLDVQZm:
16170 case VPSHLDVQZmb:
16171 case VPSHLDVQZmbk:
16172 case VPSHLDVQZmbkz:
16173 case VPSHLDVQZmk:
16174 case VPSHLDVQZmkz:
16175 case VPSHLDVQZr:
16176 case VPSHLDVQZrk:
16177 case VPSHLDVQZrkz:
16178 return true;
16179 }
16180 return false;
16181}
16182
16183bool isMOVDDUP(unsigned Opcode) {
16184 switch (Opcode) {
16185 case MOVDDUPrm:
16186 case MOVDDUPrr:
16187 return true;
16188 }
16189 return false;
16190}
16191
16192bool isVMOVDQU64(unsigned Opcode) {
16193 switch (Opcode) {
16194 case VMOVDQU64Z128mr:
16195 case VMOVDQU64Z128mrk:
16196 case VMOVDQU64Z128rm:
16197 case VMOVDQU64Z128rmk:
16198 case VMOVDQU64Z128rmkz:
16199 case VMOVDQU64Z128rr:
16200 case VMOVDQU64Z128rr_REV:
16201 case VMOVDQU64Z128rrk:
16202 case VMOVDQU64Z128rrk_REV:
16203 case VMOVDQU64Z128rrkz:
16204 case VMOVDQU64Z128rrkz_REV:
16205 case VMOVDQU64Z256mr:
16206 case VMOVDQU64Z256mrk:
16207 case VMOVDQU64Z256rm:
16208 case VMOVDQU64Z256rmk:
16209 case VMOVDQU64Z256rmkz:
16210 case VMOVDQU64Z256rr:
16211 case VMOVDQU64Z256rr_REV:
16212 case VMOVDQU64Z256rrk:
16213 case VMOVDQU64Z256rrk_REV:
16214 case VMOVDQU64Z256rrkz:
16215 case VMOVDQU64Z256rrkz_REV:
16216 case VMOVDQU64Zmr:
16217 case VMOVDQU64Zmrk:
16218 case VMOVDQU64Zrm:
16219 case VMOVDQU64Zrmk:
16220 case VMOVDQU64Zrmkz:
16221 case VMOVDQU64Zrr:
16222 case VMOVDQU64Zrr_REV:
16223 case VMOVDQU64Zrrk:
16224 case VMOVDQU64Zrrk_REV:
16225 case VMOVDQU64Zrrkz:
16226 case VMOVDQU64Zrrkz_REV:
16227 return true;
16228 }
16229 return false;
16230}
16231
16232bool isVPCOMPRESSQ(unsigned Opcode) {
16233 switch (Opcode) {
16234 case VPCOMPRESSQZ128mr:
16235 case VPCOMPRESSQZ128mrk:
16236 case VPCOMPRESSQZ128rr:
16237 case VPCOMPRESSQZ128rrk:
16238 case VPCOMPRESSQZ128rrkz:
16239 case VPCOMPRESSQZ256mr:
16240 case VPCOMPRESSQZ256mrk:
16241 case VPCOMPRESSQZ256rr:
16242 case VPCOMPRESSQZ256rrk:
16243 case VPCOMPRESSQZ256rrkz:
16244 case VPCOMPRESSQZmr:
16245 case VPCOMPRESSQZmrk:
16246 case VPCOMPRESSQZrr:
16247 case VPCOMPRESSQZrrk:
16248 case VPCOMPRESSQZrrkz:
16249 return true;
16250 }
16251 return false;
16252}
16253
16254bool isVFMSUBADD132PD(unsigned Opcode) {
16255 switch (Opcode) {
16256 case VFMSUBADD132PDYm:
16257 case VFMSUBADD132PDYr:
16258 case VFMSUBADD132PDZ128m:
16259 case VFMSUBADD132PDZ128mb:
16260 case VFMSUBADD132PDZ128mbk:
16261 case VFMSUBADD132PDZ128mbkz:
16262 case VFMSUBADD132PDZ128mk:
16263 case VFMSUBADD132PDZ128mkz:
16264 case VFMSUBADD132PDZ128r:
16265 case VFMSUBADD132PDZ128rk:
16266 case VFMSUBADD132PDZ128rkz:
16267 case VFMSUBADD132PDZ256m:
16268 case VFMSUBADD132PDZ256mb:
16269 case VFMSUBADD132PDZ256mbk:
16270 case VFMSUBADD132PDZ256mbkz:
16271 case VFMSUBADD132PDZ256mk:
16272 case VFMSUBADD132PDZ256mkz:
16273 case VFMSUBADD132PDZ256r:
16274 case VFMSUBADD132PDZ256rk:
16275 case VFMSUBADD132PDZ256rkz:
16276 case VFMSUBADD132PDZm:
16277 case VFMSUBADD132PDZmb:
16278 case VFMSUBADD132PDZmbk:
16279 case VFMSUBADD132PDZmbkz:
16280 case VFMSUBADD132PDZmk:
16281 case VFMSUBADD132PDZmkz:
16282 case VFMSUBADD132PDZr:
16283 case VFMSUBADD132PDZrb:
16284 case VFMSUBADD132PDZrbk:
16285 case VFMSUBADD132PDZrbkz:
16286 case VFMSUBADD132PDZrk:
16287 case VFMSUBADD132PDZrkz:
16288 case VFMSUBADD132PDm:
16289 case VFMSUBADD132PDr:
16290 return true;
16291 }
16292 return false;
16293}
16294
16295bool isVPERMILPD(unsigned Opcode) {
16296 switch (Opcode) {
16297 case VPERMILPDYmi:
16298 case VPERMILPDYri:
16299 case VPERMILPDYrm:
16300 case VPERMILPDYrr:
16301 case VPERMILPDZ128mbi:
16302 case VPERMILPDZ128mbik:
16303 case VPERMILPDZ128mbikz:
16304 case VPERMILPDZ128mi:
16305 case VPERMILPDZ128mik:
16306 case VPERMILPDZ128mikz:
16307 case VPERMILPDZ128ri:
16308 case VPERMILPDZ128rik:
16309 case VPERMILPDZ128rikz:
16310 case VPERMILPDZ128rm:
16311 case VPERMILPDZ128rmb:
16312 case VPERMILPDZ128rmbk:
16313 case VPERMILPDZ128rmbkz:
16314 case VPERMILPDZ128rmk:
16315 case VPERMILPDZ128rmkz:
16316 case VPERMILPDZ128rr:
16317 case VPERMILPDZ128rrk:
16318 case VPERMILPDZ128rrkz:
16319 case VPERMILPDZ256mbi:
16320 case VPERMILPDZ256mbik:
16321 case VPERMILPDZ256mbikz:
16322 case VPERMILPDZ256mi:
16323 case VPERMILPDZ256mik:
16324 case VPERMILPDZ256mikz:
16325 case VPERMILPDZ256ri:
16326 case VPERMILPDZ256rik:
16327 case VPERMILPDZ256rikz:
16328 case VPERMILPDZ256rm:
16329 case VPERMILPDZ256rmb:
16330 case VPERMILPDZ256rmbk:
16331 case VPERMILPDZ256rmbkz:
16332 case VPERMILPDZ256rmk:
16333 case VPERMILPDZ256rmkz:
16334 case VPERMILPDZ256rr:
16335 case VPERMILPDZ256rrk:
16336 case VPERMILPDZ256rrkz:
16337 case VPERMILPDZmbi:
16338 case VPERMILPDZmbik:
16339 case VPERMILPDZmbikz:
16340 case VPERMILPDZmi:
16341 case VPERMILPDZmik:
16342 case VPERMILPDZmikz:
16343 case VPERMILPDZri:
16344 case VPERMILPDZrik:
16345 case VPERMILPDZrikz:
16346 case VPERMILPDZrm:
16347 case VPERMILPDZrmb:
16348 case VPERMILPDZrmbk:
16349 case VPERMILPDZrmbkz:
16350 case VPERMILPDZrmk:
16351 case VPERMILPDZrmkz:
16352 case VPERMILPDZrr:
16353 case VPERMILPDZrrk:
16354 case VPERMILPDZrrkz:
16355 case VPERMILPDmi:
16356 case VPERMILPDri:
16357 case VPERMILPDrm:
16358 case VPERMILPDrr:
16359 return true;
16360 }
16361 return false;
16362}
16363
16364bool isADDSD(unsigned Opcode) {
16365 switch (Opcode) {
16366 case ADDSDrm_Int:
16367 case ADDSDrr_Int:
16368 return true;
16369 }
16370 return false;
16371}
16372
16373bool isBLENDPD(unsigned Opcode) {
16374 switch (Opcode) {
16375 case BLENDPDrmi:
16376 case BLENDPDrri:
16377 return true;
16378 }
16379 return false;
16380}
16381
16382bool isVPANDQ(unsigned Opcode) {
16383 switch (Opcode) {
16384 case VPANDQZ128rm:
16385 case VPANDQZ128rmb:
16386 case VPANDQZ128rmbk:
16387 case VPANDQZ128rmbkz:
16388 case VPANDQZ128rmk:
16389 case VPANDQZ128rmkz:
16390 case VPANDQZ128rr:
16391 case VPANDQZ128rrk:
16392 case VPANDQZ128rrkz:
16393 case VPANDQZ256rm:
16394 case VPANDQZ256rmb:
16395 case VPANDQZ256rmbk:
16396 case VPANDQZ256rmbkz:
16397 case VPANDQZ256rmk:
16398 case VPANDQZ256rmkz:
16399 case VPANDQZ256rr:
16400 case VPANDQZ256rrk:
16401 case VPANDQZ256rrkz:
16402 case VPANDQZrm:
16403 case VPANDQZrmb:
16404 case VPANDQZrmbk:
16405 case VPANDQZrmbkz:
16406 case VPANDQZrmk:
16407 case VPANDQZrmkz:
16408 case VPANDQZrr:
16409 case VPANDQZrrk:
16410 case VPANDQZrrkz:
16411 return true;
16412 }
16413 return false;
16414}
16415
16416bool isPMADDUBSW(unsigned Opcode) {
16417 switch (Opcode) {
16418 case MMX_PMADDUBSWrm:
16419 case MMX_PMADDUBSWrr:
16420 case PMADDUBSWrm:
16421 case PMADDUBSWrr:
16422 return true;
16423 }
16424 return false;
16425}
16426
16427bool isPOPFD(unsigned Opcode) {
16428 return Opcode == POPF32;
16429}
16430
16431bool isCMPSW(unsigned Opcode) {
16432 return Opcode == CMPSW;
16433}
16434
16435bool isLDMXCSR(unsigned Opcode) {
16436 return Opcode == LDMXCSR;
16437}
16438
16439bool isVMULPS(unsigned Opcode) {
16440 switch (Opcode) {
16441 case VMULPSYrm:
16442 case VMULPSYrr:
16443 case VMULPSZ128rm:
16444 case VMULPSZ128rmb:
16445 case VMULPSZ128rmbk:
16446 case VMULPSZ128rmbkz:
16447 case VMULPSZ128rmk:
16448 case VMULPSZ128rmkz:
16449 case VMULPSZ128rr:
16450 case VMULPSZ128rrk:
16451 case VMULPSZ128rrkz:
16452 case VMULPSZ256rm:
16453 case VMULPSZ256rmb:
16454 case VMULPSZ256rmbk:
16455 case VMULPSZ256rmbkz:
16456 case VMULPSZ256rmk:
16457 case VMULPSZ256rmkz:
16458 case VMULPSZ256rr:
16459 case VMULPSZ256rrk:
16460 case VMULPSZ256rrkz:
16461 case VMULPSZrm:
16462 case VMULPSZrmb:
16463 case VMULPSZrmbk:
16464 case VMULPSZrmbkz:
16465 case VMULPSZrmk:
16466 case VMULPSZrmkz:
16467 case VMULPSZrr:
16468 case VMULPSZrrb:
16469 case VMULPSZrrbk:
16470 case VMULPSZrrbkz:
16471 case VMULPSZrrk:
16472 case VMULPSZrrkz:
16473 case VMULPSrm:
16474 case VMULPSrr:
16475 return true;
16476 }
16477 return false;
16478}
16479
16480bool isVROUNDSD(unsigned Opcode) {
16481 switch (Opcode) {
16482 case VROUNDSDmi_Int:
16483 case VROUNDSDri_Int:
16484 return true;
16485 }
16486 return false;
16487}
16488
16489bool isVFMADD132PD(unsigned Opcode) {
16490 switch (Opcode) {
16491 case VFMADD132PDYm:
16492 case VFMADD132PDYr:
16493 case VFMADD132PDZ128m:
16494 case VFMADD132PDZ128mb:
16495 case VFMADD132PDZ128mbk:
16496 case VFMADD132PDZ128mbkz:
16497 case VFMADD132PDZ128mk:
16498 case VFMADD132PDZ128mkz:
16499 case VFMADD132PDZ128r:
16500 case VFMADD132PDZ128rk:
16501 case VFMADD132PDZ128rkz:
16502 case VFMADD132PDZ256m:
16503 case VFMADD132PDZ256mb:
16504 case VFMADD132PDZ256mbk:
16505 case VFMADD132PDZ256mbkz:
16506 case VFMADD132PDZ256mk:
16507 case VFMADD132PDZ256mkz:
16508 case VFMADD132PDZ256r:
16509 case VFMADD132PDZ256rk:
16510 case VFMADD132PDZ256rkz:
16511 case VFMADD132PDZm:
16512 case VFMADD132PDZmb:
16513 case VFMADD132PDZmbk:
16514 case VFMADD132PDZmbkz:
16515 case VFMADD132PDZmk:
16516 case VFMADD132PDZmkz:
16517 case VFMADD132PDZr:
16518 case VFMADD132PDZrb:
16519 case VFMADD132PDZrbk:
16520 case VFMADD132PDZrbkz:
16521 case VFMADD132PDZrk:
16522 case VFMADD132PDZrkz:
16523 case VFMADD132PDm:
16524 case VFMADD132PDr:
16525 return true;
16526 }
16527 return false;
16528}
16529
16530bool isVPSRAQ(unsigned Opcode) {
16531 switch (Opcode) {
16532 case VPSRAQZ128mbi:
16533 case VPSRAQZ128mbik:
16534 case VPSRAQZ128mbikz:
16535 case VPSRAQZ128mi:
16536 case VPSRAQZ128mik:
16537 case VPSRAQZ128mikz:
16538 case VPSRAQZ128ri:
16539 case VPSRAQZ128rik:
16540 case VPSRAQZ128rikz:
16541 case VPSRAQZ128rm:
16542 case VPSRAQZ128rmk:
16543 case VPSRAQZ128rmkz:
16544 case VPSRAQZ128rr:
16545 case VPSRAQZ128rrk:
16546 case VPSRAQZ128rrkz:
16547 case VPSRAQZ256mbi:
16548 case VPSRAQZ256mbik:
16549 case VPSRAQZ256mbikz:
16550 case VPSRAQZ256mi:
16551 case VPSRAQZ256mik:
16552 case VPSRAQZ256mikz:
16553 case VPSRAQZ256ri:
16554 case VPSRAQZ256rik:
16555 case VPSRAQZ256rikz:
16556 case VPSRAQZ256rm:
16557 case VPSRAQZ256rmk:
16558 case VPSRAQZ256rmkz:
16559 case VPSRAQZ256rr:
16560 case VPSRAQZ256rrk:
16561 case VPSRAQZ256rrkz:
16562 case VPSRAQZmbi:
16563 case VPSRAQZmbik:
16564 case VPSRAQZmbikz:
16565 case VPSRAQZmi:
16566 case VPSRAQZmik:
16567 case VPSRAQZmikz:
16568 case VPSRAQZri:
16569 case VPSRAQZrik:
16570 case VPSRAQZrikz:
16571 case VPSRAQZrm:
16572 case VPSRAQZrmk:
16573 case VPSRAQZrmkz:
16574 case VPSRAQZrr:
16575 case VPSRAQZrrk:
16576 case VPSRAQZrrkz:
16577 return true;
16578 }
16579 return false;
16580}
16581
16582bool isVCOMISD(unsigned Opcode) {
16583 switch (Opcode) {
16584 case VCOMISDZrm:
16585 case VCOMISDZrr:
16586 case VCOMISDZrrb:
16587 case VCOMISDrm:
16588 case VCOMISDrr:
16589 return true;
16590 }
16591 return false;
16592}
16593
16594bool isVCVTBIASPH2BF8(unsigned Opcode) {
16595 switch (Opcode) {
16596 case VCVTBIASPH2BF8Z128rm:
16597 case VCVTBIASPH2BF8Z128rmb:
16598 case VCVTBIASPH2BF8Z128rmbk:
16599 case VCVTBIASPH2BF8Z128rmbkz:
16600 case VCVTBIASPH2BF8Z128rmk:
16601 case VCVTBIASPH2BF8Z128rmkz:
16602 case VCVTBIASPH2BF8Z128rr:
16603 case VCVTBIASPH2BF8Z128rrk:
16604 case VCVTBIASPH2BF8Z128rrkz:
16605 case VCVTBIASPH2BF8Z256rm:
16606 case VCVTBIASPH2BF8Z256rmb:
16607 case VCVTBIASPH2BF8Z256rmbk:
16608 case VCVTBIASPH2BF8Z256rmbkz:
16609 case VCVTBIASPH2BF8Z256rmk:
16610 case VCVTBIASPH2BF8Z256rmkz:
16611 case VCVTBIASPH2BF8Z256rr:
16612 case VCVTBIASPH2BF8Z256rrk:
16613 case VCVTBIASPH2BF8Z256rrkz:
16614 case VCVTBIASPH2BF8Zrm:
16615 case VCVTBIASPH2BF8Zrmb:
16616 case VCVTBIASPH2BF8Zrmbk:
16617 case VCVTBIASPH2BF8Zrmbkz:
16618 case VCVTBIASPH2BF8Zrmk:
16619 case VCVTBIASPH2BF8Zrmkz:
16620 case VCVTBIASPH2BF8Zrr:
16621 case VCVTBIASPH2BF8Zrrk:
16622 case VCVTBIASPH2BF8Zrrkz:
16623 return true;
16624 }
16625 return false;
16626}
16627
16628bool isFFREEP(unsigned Opcode) {
16629 return Opcode == FFREEP;
16630}
16631
16632bool isVFNMADD213PD(unsigned Opcode) {
16633 switch (Opcode) {
16634 case VFNMADD213PDYm:
16635 case VFNMADD213PDYr:
16636 case VFNMADD213PDZ128m:
16637 case VFNMADD213PDZ128mb:
16638 case VFNMADD213PDZ128mbk:
16639 case VFNMADD213PDZ128mbkz:
16640 case VFNMADD213PDZ128mk:
16641 case VFNMADD213PDZ128mkz:
16642 case VFNMADD213PDZ128r:
16643 case VFNMADD213PDZ128rk:
16644 case VFNMADD213PDZ128rkz:
16645 case VFNMADD213PDZ256m:
16646 case VFNMADD213PDZ256mb:
16647 case VFNMADD213PDZ256mbk:
16648 case VFNMADD213PDZ256mbkz:
16649 case VFNMADD213PDZ256mk:
16650 case VFNMADD213PDZ256mkz:
16651 case VFNMADD213PDZ256r:
16652 case VFNMADD213PDZ256rk:
16653 case VFNMADD213PDZ256rkz:
16654 case VFNMADD213PDZm:
16655 case VFNMADD213PDZmb:
16656 case VFNMADD213PDZmbk:
16657 case VFNMADD213PDZmbkz:
16658 case VFNMADD213PDZmk:
16659 case VFNMADD213PDZmkz:
16660 case VFNMADD213PDZr:
16661 case VFNMADD213PDZrb:
16662 case VFNMADD213PDZrbk:
16663 case VFNMADD213PDZrbkz:
16664 case VFNMADD213PDZrk:
16665 case VFNMADD213PDZrkz:
16666 case VFNMADD213PDm:
16667 case VFNMADD213PDr:
16668 return true;
16669 }
16670 return false;
16671}
16672
16673bool isVCMPPD(unsigned Opcode) {
16674 switch (Opcode) {
16675 case VCMPPDYrmi:
16676 case VCMPPDYrri:
16677 case VCMPPDZ128rmbi:
16678 case VCMPPDZ128rmbik:
16679 case VCMPPDZ128rmi:
16680 case VCMPPDZ128rmik:
16681 case VCMPPDZ128rri:
16682 case VCMPPDZ128rrik:
16683 case VCMPPDZ256rmbi:
16684 case VCMPPDZ256rmbik:
16685 case VCMPPDZ256rmi:
16686 case VCMPPDZ256rmik:
16687 case VCMPPDZ256rri:
16688 case VCMPPDZ256rrik:
16689 case VCMPPDZrmbi:
16690 case VCMPPDZrmbik:
16691 case VCMPPDZrmi:
16692 case VCMPPDZrmik:
16693 case VCMPPDZrri:
16694 case VCMPPDZrrib:
16695 case VCMPPDZrribk:
16696 case VCMPPDZrrik:
16697 case VCMPPDrmi:
16698 case VCMPPDrri:
16699 return true;
16700 }
16701 return false;
16702}
16703
16704bool isVFNMSUB132PH(unsigned Opcode) {
16705 switch (Opcode) {
16706 case VFNMSUB132PHZ128m:
16707 case VFNMSUB132PHZ128mb:
16708 case VFNMSUB132PHZ128mbk:
16709 case VFNMSUB132PHZ128mbkz:
16710 case VFNMSUB132PHZ128mk:
16711 case VFNMSUB132PHZ128mkz:
16712 case VFNMSUB132PHZ128r:
16713 case VFNMSUB132PHZ128rk:
16714 case VFNMSUB132PHZ128rkz:
16715 case VFNMSUB132PHZ256m:
16716 case VFNMSUB132PHZ256mb:
16717 case VFNMSUB132PHZ256mbk:
16718 case VFNMSUB132PHZ256mbkz:
16719 case VFNMSUB132PHZ256mk:
16720 case VFNMSUB132PHZ256mkz:
16721 case VFNMSUB132PHZ256r:
16722 case VFNMSUB132PHZ256rk:
16723 case VFNMSUB132PHZ256rkz:
16724 case VFNMSUB132PHZm:
16725 case VFNMSUB132PHZmb:
16726 case VFNMSUB132PHZmbk:
16727 case VFNMSUB132PHZmbkz:
16728 case VFNMSUB132PHZmk:
16729 case VFNMSUB132PHZmkz:
16730 case VFNMSUB132PHZr:
16731 case VFNMSUB132PHZrb:
16732 case VFNMSUB132PHZrbk:
16733 case VFNMSUB132PHZrbkz:
16734 case VFNMSUB132PHZrk:
16735 case VFNMSUB132PHZrkz:
16736 return true;
16737 }
16738 return false;
16739}
16740
16741bool isVPHADDBW(unsigned Opcode) {
16742 switch (Opcode) {
16743 case VPHADDBWrm:
16744 case VPHADDBWrr:
16745 return true;
16746 }
16747 return false;
16748}
16749
16750bool isVPPERM(unsigned Opcode) {
16751 switch (Opcode) {
16752 case VPPERMrmr:
16753 case VPPERMrrm:
16754 case VPPERMrrr:
16755 case VPPERMrrr_REV:
16756 return true;
16757 }
16758 return false;
16759}
16760
16761bool isVCVTPS2PD(unsigned Opcode) {
16762 switch (Opcode) {
16763 case VCVTPS2PDYrm:
16764 case VCVTPS2PDYrr:
16765 case VCVTPS2PDZ128rm:
16766 case VCVTPS2PDZ128rmb:
16767 case VCVTPS2PDZ128rmbk:
16768 case VCVTPS2PDZ128rmbkz:
16769 case VCVTPS2PDZ128rmk:
16770 case VCVTPS2PDZ128rmkz:
16771 case VCVTPS2PDZ128rr:
16772 case VCVTPS2PDZ128rrk:
16773 case VCVTPS2PDZ128rrkz:
16774 case VCVTPS2PDZ256rm:
16775 case VCVTPS2PDZ256rmb:
16776 case VCVTPS2PDZ256rmbk:
16777 case VCVTPS2PDZ256rmbkz:
16778 case VCVTPS2PDZ256rmk:
16779 case VCVTPS2PDZ256rmkz:
16780 case VCVTPS2PDZ256rr:
16781 case VCVTPS2PDZ256rrk:
16782 case VCVTPS2PDZ256rrkz:
16783 case VCVTPS2PDZrm:
16784 case VCVTPS2PDZrmb:
16785 case VCVTPS2PDZrmbk:
16786 case VCVTPS2PDZrmbkz:
16787 case VCVTPS2PDZrmk:
16788 case VCVTPS2PDZrmkz:
16789 case VCVTPS2PDZrr:
16790 case VCVTPS2PDZrrb:
16791 case VCVTPS2PDZrrbk:
16792 case VCVTPS2PDZrrbkz:
16793 case VCVTPS2PDZrrk:
16794 case VCVTPS2PDZrrkz:
16795 case VCVTPS2PDrm:
16796 case VCVTPS2PDrr:
16797 return true;
16798 }
16799 return false;
16800}
16801
16802bool isCBW(unsigned Opcode) {
16803 return Opcode == CBW;
16804}
16805
16806bool isVMOVUPS(unsigned Opcode) {
16807 switch (Opcode) {
16808 case VMOVUPSYmr:
16809 case VMOVUPSYrm:
16810 case VMOVUPSYrr:
16811 case VMOVUPSYrr_REV:
16812 case VMOVUPSZ128mr:
16813 case VMOVUPSZ128mrk:
16814 case VMOVUPSZ128rm:
16815 case VMOVUPSZ128rmk:
16816 case VMOVUPSZ128rmkz:
16817 case VMOVUPSZ128rr:
16818 case VMOVUPSZ128rr_REV:
16819 case VMOVUPSZ128rrk:
16820 case VMOVUPSZ128rrk_REV:
16821 case VMOVUPSZ128rrkz:
16822 case VMOVUPSZ128rrkz_REV:
16823 case VMOVUPSZ256mr:
16824 case VMOVUPSZ256mrk:
16825 case VMOVUPSZ256rm:
16826 case VMOVUPSZ256rmk:
16827 case VMOVUPSZ256rmkz:
16828 case VMOVUPSZ256rr:
16829 case VMOVUPSZ256rr_REV:
16830 case VMOVUPSZ256rrk:
16831 case VMOVUPSZ256rrk_REV:
16832 case VMOVUPSZ256rrkz:
16833 case VMOVUPSZ256rrkz_REV:
16834 case VMOVUPSZmr:
16835 case VMOVUPSZmrk:
16836 case VMOVUPSZrm:
16837 case VMOVUPSZrmk:
16838 case VMOVUPSZrmkz:
16839 case VMOVUPSZrr:
16840 case VMOVUPSZrr_REV:
16841 case VMOVUPSZrrk:
16842 case VMOVUPSZrrk_REV:
16843 case VMOVUPSZrrkz:
16844 case VMOVUPSZrrkz_REV:
16845 case VMOVUPSmr:
16846 case VMOVUPSrm:
16847 case VMOVUPSrr:
16848 case VMOVUPSrr_REV:
16849 return true;
16850 }
16851 return false;
16852}
16853
16854bool isVPMAXUQ(unsigned Opcode) {
16855 switch (Opcode) {
16856 case VPMAXUQZ128rm:
16857 case VPMAXUQZ128rmb:
16858 case VPMAXUQZ128rmbk:
16859 case VPMAXUQZ128rmbkz:
16860 case VPMAXUQZ128rmk:
16861 case VPMAXUQZ128rmkz:
16862 case VPMAXUQZ128rr:
16863 case VPMAXUQZ128rrk:
16864 case VPMAXUQZ128rrkz:
16865 case VPMAXUQZ256rm:
16866 case VPMAXUQZ256rmb:
16867 case VPMAXUQZ256rmbk:
16868 case VPMAXUQZ256rmbkz:
16869 case VPMAXUQZ256rmk:
16870 case VPMAXUQZ256rmkz:
16871 case VPMAXUQZ256rr:
16872 case VPMAXUQZ256rrk:
16873 case VPMAXUQZ256rrkz:
16874 case VPMAXUQZrm:
16875 case VPMAXUQZrmb:
16876 case VPMAXUQZrmbk:
16877 case VPMAXUQZrmbkz:
16878 case VPMAXUQZrmk:
16879 case VPMAXUQZrmkz:
16880 case VPMAXUQZrr:
16881 case VPMAXUQZrrk:
16882 case VPMAXUQZrrkz:
16883 return true;
16884 }
16885 return false;
16886}
16887
16888bool isWRSSQ(unsigned Opcode) {
16889 switch (Opcode) {
16890 case WRSSQ:
16891 case WRSSQ_EVEX:
16892 return true;
16893 }
16894 return false;
16895}
16896
16897bool isPACKUSDW(unsigned Opcode) {
16898 switch (Opcode) {
16899 case PACKUSDWrm:
16900 case PACKUSDWrr:
16901 return true;
16902 }
16903 return false;
16904}
16905
16906bool isVCVTTBF162IBS(unsigned Opcode) {
16907 switch (Opcode) {
16908 case VCVTTBF162IBSZ128rm:
16909 case VCVTTBF162IBSZ128rmb:
16910 case VCVTTBF162IBSZ128rmbk:
16911 case VCVTTBF162IBSZ128rmbkz:
16912 case VCVTTBF162IBSZ128rmk:
16913 case VCVTTBF162IBSZ128rmkz:
16914 case VCVTTBF162IBSZ128rr:
16915 case VCVTTBF162IBSZ128rrk:
16916 case VCVTTBF162IBSZ128rrkz:
16917 case VCVTTBF162IBSZ256rm:
16918 case VCVTTBF162IBSZ256rmb:
16919 case VCVTTBF162IBSZ256rmbk:
16920 case VCVTTBF162IBSZ256rmbkz:
16921 case VCVTTBF162IBSZ256rmk:
16922 case VCVTTBF162IBSZ256rmkz:
16923 case VCVTTBF162IBSZ256rr:
16924 case VCVTTBF162IBSZ256rrk:
16925 case VCVTTBF162IBSZ256rrkz:
16926 case VCVTTBF162IBSZrm:
16927 case VCVTTBF162IBSZrmb:
16928 case VCVTTBF162IBSZrmbk:
16929 case VCVTTBF162IBSZrmbkz:
16930 case VCVTTBF162IBSZrmk:
16931 case VCVTTBF162IBSZrmkz:
16932 case VCVTTBF162IBSZrr:
16933 case VCVTTBF162IBSZrrk:
16934 case VCVTTBF162IBSZrrkz:
16935 return true;
16936 }
16937 return false;
16938}
16939
16940bool isXBEGIN(unsigned Opcode) {
16941 switch (Opcode) {
16942 case XBEGIN_2:
16943 case XBEGIN_4:
16944 return true;
16945 }
16946 return false;
16947}
16948
16949bool isVCVTPD2UQQ(unsigned Opcode) {
16950 switch (Opcode) {
16951 case VCVTPD2UQQZ128rm:
16952 case VCVTPD2UQQZ128rmb:
16953 case VCVTPD2UQQZ128rmbk:
16954 case VCVTPD2UQQZ128rmbkz:
16955 case VCVTPD2UQQZ128rmk:
16956 case VCVTPD2UQQZ128rmkz:
16957 case VCVTPD2UQQZ128rr:
16958 case VCVTPD2UQQZ128rrk:
16959 case VCVTPD2UQQZ128rrkz:
16960 case VCVTPD2UQQZ256rm:
16961 case VCVTPD2UQQZ256rmb:
16962 case VCVTPD2UQQZ256rmbk:
16963 case VCVTPD2UQQZ256rmbkz:
16964 case VCVTPD2UQQZ256rmk:
16965 case VCVTPD2UQQZ256rmkz:
16966 case VCVTPD2UQQZ256rr:
16967 case VCVTPD2UQQZ256rrk:
16968 case VCVTPD2UQQZ256rrkz:
16969 case VCVTPD2UQQZrm:
16970 case VCVTPD2UQQZrmb:
16971 case VCVTPD2UQQZrmbk:
16972 case VCVTPD2UQQZrmbkz:
16973 case VCVTPD2UQQZrmk:
16974 case VCVTPD2UQQZrmkz:
16975 case VCVTPD2UQQZrr:
16976 case VCVTPD2UQQZrrb:
16977 case VCVTPD2UQQZrrbk:
16978 case VCVTPD2UQQZrrbkz:
16979 case VCVTPD2UQQZrrk:
16980 case VCVTPD2UQQZrrkz:
16981 return true;
16982 }
16983 return false;
16984}
16985
16986bool isFCMOVB(unsigned Opcode) {
16987 return Opcode == CMOVB_F;
16988}
16989
16990bool isNOP(unsigned Opcode) {
16991 switch (Opcode) {
16992 case NOOP:
16993 case NOOPL:
16994 case NOOPLr:
16995 case NOOPQ:
16996 case NOOPQr:
16997 case NOOPW:
16998 case NOOPWr:
16999 return true;
17000 }
17001 return false;
17002}
17003
17004bool isVPABSQ(unsigned Opcode) {
17005 switch (Opcode) {
17006 case VPABSQZ128rm:
17007 case VPABSQZ128rmb:
17008 case VPABSQZ128rmbk:
17009 case VPABSQZ128rmbkz:
17010 case VPABSQZ128rmk:
17011 case VPABSQZ128rmkz:
17012 case VPABSQZ128rr:
17013 case VPABSQZ128rrk:
17014 case VPABSQZ128rrkz:
17015 case VPABSQZ256rm:
17016 case VPABSQZ256rmb:
17017 case VPABSQZ256rmbk:
17018 case VPABSQZ256rmbkz:
17019 case VPABSQZ256rmk:
17020 case VPABSQZ256rmkz:
17021 case VPABSQZ256rr:
17022 case VPABSQZ256rrk:
17023 case VPABSQZ256rrkz:
17024 case VPABSQZrm:
17025 case VPABSQZrmb:
17026 case VPABSQZrmbk:
17027 case VPABSQZrmbkz:
17028 case VPABSQZrmk:
17029 case VPABSQZrmkz:
17030 case VPABSQZrr:
17031 case VPABSQZrrk:
17032 case VPABSQZrrkz:
17033 return true;
17034 }
17035 return false;
17036}
17037
17038bool isVTESTPS(unsigned Opcode) {
17039 switch (Opcode) {
17040 case VTESTPSYrm:
17041 case VTESTPSYrr:
17042 case VTESTPSrm:
17043 case VTESTPSrr:
17044 return true;
17045 }
17046 return false;
17047}
17048
17049bool isPHSUBW(unsigned Opcode) {
17050 switch (Opcode) {
17051 case MMX_PHSUBWrm:
17052 case MMX_PHSUBWrr:
17053 case PHSUBWrm:
17054 case PHSUBWrr:
17055 return true;
17056 }
17057 return false;
17058}
17059
17060bool isPUSH2P(unsigned Opcode) {
17061 return Opcode == PUSH2P;
17062}
17063
17064bool isFISTTP(unsigned Opcode) {
17065 switch (Opcode) {
17066 case ISTT_FP16m:
17067 case ISTT_FP32m:
17068 case ISTT_FP64m:
17069 return true;
17070 }
17071 return false;
17072}
17073
17074bool isCFCMOVCC(unsigned Opcode) {
17075 switch (Opcode) {
17076 case CFCMOV16mr:
17077 case CFCMOV16rm:
17078 case CFCMOV16rm_ND:
17079 case CFCMOV16rr:
17080 case CFCMOV16rr_ND:
17081 case CFCMOV16rr_REV:
17082 case CFCMOV32mr:
17083 case CFCMOV32rm:
17084 case CFCMOV32rm_ND:
17085 case CFCMOV32rr:
17086 case CFCMOV32rr_ND:
17087 case CFCMOV32rr_REV:
17088 case CFCMOV64mr:
17089 case CFCMOV64rm:
17090 case CFCMOV64rm_ND:
17091 case CFCMOV64rr:
17092 case CFCMOV64rr_ND:
17093 case CFCMOV64rr_REV:
17094 return true;
17095 }
17096 return false;
17097}
17098
17099bool isPCMPESTRM(unsigned Opcode) {
17100 switch (Opcode) {
17101 case PCMPESTRMrmi:
17102 case PCMPESTRMrri:
17103 return true;
17104 }
17105 return false;
17106}
17107
17108bool isVPINSRD(unsigned Opcode) {
17109 switch (Opcode) {
17110 case VPINSRDZrmi:
17111 case VPINSRDZrri:
17112 case VPINSRDrmi:
17113 case VPINSRDrri:
17114 return true;
17115 }
17116 return false;
17117}
17118
17119bool isVFNMSUB213PS(unsigned Opcode) {
17120 switch (Opcode) {
17121 case VFNMSUB213PSYm:
17122 case VFNMSUB213PSYr:
17123 case VFNMSUB213PSZ128m:
17124 case VFNMSUB213PSZ128mb:
17125 case VFNMSUB213PSZ128mbk:
17126 case VFNMSUB213PSZ128mbkz:
17127 case VFNMSUB213PSZ128mk:
17128 case VFNMSUB213PSZ128mkz:
17129 case VFNMSUB213PSZ128r:
17130 case VFNMSUB213PSZ128rk:
17131 case VFNMSUB213PSZ128rkz:
17132 case VFNMSUB213PSZ256m:
17133 case VFNMSUB213PSZ256mb:
17134 case VFNMSUB213PSZ256mbk:
17135 case VFNMSUB213PSZ256mbkz:
17136 case VFNMSUB213PSZ256mk:
17137 case VFNMSUB213PSZ256mkz:
17138 case VFNMSUB213PSZ256r:
17139 case VFNMSUB213PSZ256rk:
17140 case VFNMSUB213PSZ256rkz:
17141 case VFNMSUB213PSZm:
17142 case VFNMSUB213PSZmb:
17143 case VFNMSUB213PSZmbk:
17144 case VFNMSUB213PSZmbkz:
17145 case VFNMSUB213PSZmk:
17146 case VFNMSUB213PSZmkz:
17147 case VFNMSUB213PSZr:
17148 case VFNMSUB213PSZrb:
17149 case VFNMSUB213PSZrbk:
17150 case VFNMSUB213PSZrbkz:
17151 case VFNMSUB213PSZrk:
17152 case VFNMSUB213PSZrkz:
17153 case VFNMSUB213PSm:
17154 case VFNMSUB213PSr:
17155 return true;
17156 }
17157 return false;
17158}
17159
17160bool isPHSUBD(unsigned Opcode) {
17161 switch (Opcode) {
17162 case MMX_PHSUBDrm:
17163 case MMX_PHSUBDrr:
17164 case PHSUBDrm:
17165 case PHSUBDrr:
17166 return true;
17167 }
17168 return false;
17169}
17170
17171bool isSLDT(unsigned Opcode) {
17172 switch (Opcode) {
17173 case SLDT16m:
17174 case SLDT16r:
17175 case SLDT32r:
17176 case SLDT64r:
17177 return true;
17178 }
17179 return false;
17180}
17181
17182bool isVCVTTPD2DQS(unsigned Opcode) {
17183 switch (Opcode) {
17184 case VCVTTPD2DQSZ128rm:
17185 case VCVTTPD2DQSZ128rmb:
17186 case VCVTTPD2DQSZ128rmbk:
17187 case VCVTTPD2DQSZ128rmbkz:
17188 case VCVTTPD2DQSZ128rmk:
17189 case VCVTTPD2DQSZ128rmkz:
17190 case VCVTTPD2DQSZ128rr:
17191 case VCVTTPD2DQSZ128rrk:
17192 case VCVTTPD2DQSZ128rrkz:
17193 case VCVTTPD2DQSZ256rm:
17194 case VCVTTPD2DQSZ256rmb:
17195 case VCVTTPD2DQSZ256rmbk:
17196 case VCVTTPD2DQSZ256rmbkz:
17197 case VCVTTPD2DQSZ256rmk:
17198 case VCVTTPD2DQSZ256rmkz:
17199 case VCVTTPD2DQSZ256rr:
17200 case VCVTTPD2DQSZ256rrb:
17201 case VCVTTPD2DQSZ256rrbk:
17202 case VCVTTPD2DQSZ256rrbkz:
17203 case VCVTTPD2DQSZ256rrk:
17204 case VCVTTPD2DQSZ256rrkz:
17205 case VCVTTPD2DQSZrm:
17206 case VCVTTPD2DQSZrmb:
17207 case VCVTTPD2DQSZrmbk:
17208 case VCVTTPD2DQSZrmbkz:
17209 case VCVTTPD2DQSZrmk:
17210 case VCVTTPD2DQSZrmkz:
17211 case VCVTTPD2DQSZrr:
17212 case VCVTTPD2DQSZrrb:
17213 case VCVTTPD2DQSZrrbk:
17214 case VCVTTPD2DQSZrrbkz:
17215 case VCVTTPD2DQSZrrk:
17216 case VCVTTPD2DQSZrrkz:
17217 return true;
17218 }
17219 return false;
17220}
17221
17222bool isVPMINSD(unsigned Opcode) {
17223 switch (Opcode) {
17224 case VPMINSDYrm:
17225 case VPMINSDYrr:
17226 case VPMINSDZ128rm:
17227 case VPMINSDZ128rmb:
17228 case VPMINSDZ128rmbk:
17229 case VPMINSDZ128rmbkz:
17230 case VPMINSDZ128rmk:
17231 case VPMINSDZ128rmkz:
17232 case VPMINSDZ128rr:
17233 case VPMINSDZ128rrk:
17234 case VPMINSDZ128rrkz:
17235 case VPMINSDZ256rm:
17236 case VPMINSDZ256rmb:
17237 case VPMINSDZ256rmbk:
17238 case VPMINSDZ256rmbkz:
17239 case VPMINSDZ256rmk:
17240 case VPMINSDZ256rmkz:
17241 case VPMINSDZ256rr:
17242 case VPMINSDZ256rrk:
17243 case VPMINSDZ256rrkz:
17244 case VPMINSDZrm:
17245 case VPMINSDZrmb:
17246 case VPMINSDZrmbk:
17247 case VPMINSDZrmbkz:
17248 case VPMINSDZrmk:
17249 case VPMINSDZrmkz:
17250 case VPMINSDZrr:
17251 case VPMINSDZrrk:
17252 case VPMINSDZrrkz:
17253 case VPMINSDrm:
17254 case VPMINSDrr:
17255 return true;
17256 }
17257 return false;
17258}
17259
17260bool isVHADDPS(unsigned Opcode) {
17261 switch (Opcode) {
17262 case VHADDPSYrm:
17263 case VHADDPSYrr:
17264 case VHADDPSrm:
17265 case VHADDPSrr:
17266 return true;
17267 }
17268 return false;
17269}
17270
17271bool isVMOVNTDQ(unsigned Opcode) {
17272 switch (Opcode) {
17273 case VMOVNTDQYmr:
17274 case VMOVNTDQZ128mr:
17275 case VMOVNTDQZ256mr:
17276 case VMOVNTDQZmr:
17277 case VMOVNTDQmr:
17278 return true;
17279 }
17280 return false;
17281}
17282
17283bool isVFRCZSD(unsigned Opcode) {
17284 switch (Opcode) {
17285 case VFRCZSDrm:
17286 case VFRCZSDrr:
17287 return true;
17288 }
17289 return false;
17290}
17291
17292bool isIBHF(unsigned Opcode) {
17293 return Opcode == IBHF;
17294}
17295
17296bool isVPTESTMW(unsigned Opcode) {
17297 switch (Opcode) {
17298 case VPTESTMWZ128rm:
17299 case VPTESTMWZ128rmk:
17300 case VPTESTMWZ128rr:
17301 case VPTESTMWZ128rrk:
17302 case VPTESTMWZ256rm:
17303 case VPTESTMWZ256rmk:
17304 case VPTESTMWZ256rr:
17305 case VPTESTMWZ256rrk:
17306 case VPTESTMWZrm:
17307 case VPTESTMWZrmk:
17308 case VPTESTMWZrr:
17309 case VPTESTMWZrrk:
17310 return true;
17311 }
17312 return false;
17313}
17314
17315bool isVPMOVZXWD(unsigned Opcode) {
17316 switch (Opcode) {
17317 case VPMOVZXWDYrm:
17318 case VPMOVZXWDYrr:
17319 case VPMOVZXWDZ128rm:
17320 case VPMOVZXWDZ128rmk:
17321 case VPMOVZXWDZ128rmkz:
17322 case VPMOVZXWDZ128rr:
17323 case VPMOVZXWDZ128rrk:
17324 case VPMOVZXWDZ128rrkz:
17325 case VPMOVZXWDZ256rm:
17326 case VPMOVZXWDZ256rmk:
17327 case VPMOVZXWDZ256rmkz:
17328 case VPMOVZXWDZ256rr:
17329 case VPMOVZXWDZ256rrk:
17330 case VPMOVZXWDZ256rrkz:
17331 case VPMOVZXWDZrm:
17332 case VPMOVZXWDZrmk:
17333 case VPMOVZXWDZrmkz:
17334 case VPMOVZXWDZrr:
17335 case VPMOVZXWDZrrk:
17336 case VPMOVZXWDZrrkz:
17337 case VPMOVZXWDrm:
17338 case VPMOVZXWDrr:
17339 return true;
17340 }
17341 return false;
17342}
17343
17344bool isPSADBW(unsigned Opcode) {
17345 switch (Opcode) {
17346 case MMX_PSADBWrm:
17347 case MMX_PSADBWrr:
17348 case PSADBWrm:
17349 case PSADBWrr:
17350 return true;
17351 }
17352 return false;
17353}
17354
17355bool isVCVTSD2SI(unsigned Opcode) {
17356 switch (Opcode) {
17357 case VCVTSD2SI64Zrm_Int:
17358 case VCVTSD2SI64Zrr_Int:
17359 case VCVTSD2SI64Zrrb_Int:
17360 case VCVTSD2SI64rm_Int:
17361 case VCVTSD2SI64rr_Int:
17362 case VCVTSD2SIZrm_Int:
17363 case VCVTSD2SIZrr_Int:
17364 case VCVTSD2SIZrrb_Int:
17365 case VCVTSD2SIrm_Int:
17366 case VCVTSD2SIrr_Int:
17367 return true;
17368 }
17369 return false;
17370}
17371
17372bool isVMAXPH(unsigned Opcode) {
17373 switch (Opcode) {
17374 case VMAXPHZ128rm:
17375 case VMAXPHZ128rmb:
17376 case VMAXPHZ128rmbk:
17377 case VMAXPHZ128rmbkz:
17378 case VMAXPHZ128rmk:
17379 case VMAXPHZ128rmkz:
17380 case VMAXPHZ128rr:
17381 case VMAXPHZ128rrk:
17382 case VMAXPHZ128rrkz:
17383 case VMAXPHZ256rm:
17384 case VMAXPHZ256rmb:
17385 case VMAXPHZ256rmbk:
17386 case VMAXPHZ256rmbkz:
17387 case VMAXPHZ256rmk:
17388 case VMAXPHZ256rmkz:
17389 case VMAXPHZ256rr:
17390 case VMAXPHZ256rrk:
17391 case VMAXPHZ256rrkz:
17392 case VMAXPHZrm:
17393 case VMAXPHZrmb:
17394 case VMAXPHZrmbk:
17395 case VMAXPHZrmbkz:
17396 case VMAXPHZrmk:
17397 case VMAXPHZrmkz:
17398 case VMAXPHZrr:
17399 case VMAXPHZrrb:
17400 case VMAXPHZrrbk:
17401 case VMAXPHZrrbkz:
17402 case VMAXPHZrrk:
17403 case VMAXPHZrrkz:
17404 return true;
17405 }
17406 return false;
17407}
17408
17409bool isLODSB(unsigned Opcode) {
17410 return Opcode == LODSB;
17411}
17412
17413bool isPHMINPOSUW(unsigned Opcode) {
17414 switch (Opcode) {
17415 case PHMINPOSUWrm:
17416 case PHMINPOSUWrr:
17417 return true;
17418 }
17419 return false;
17420}
17421
17422bool isVPROLVD(unsigned Opcode) {
17423 switch (Opcode) {
17424 case VPROLVDZ128rm:
17425 case VPROLVDZ128rmb:
17426 case VPROLVDZ128rmbk:
17427 case VPROLVDZ128rmbkz:
17428 case VPROLVDZ128rmk:
17429 case VPROLVDZ128rmkz:
17430 case VPROLVDZ128rr:
17431 case VPROLVDZ128rrk:
17432 case VPROLVDZ128rrkz:
17433 case VPROLVDZ256rm:
17434 case VPROLVDZ256rmb:
17435 case VPROLVDZ256rmbk:
17436 case VPROLVDZ256rmbkz:
17437 case VPROLVDZ256rmk:
17438 case VPROLVDZ256rmkz:
17439 case VPROLVDZ256rr:
17440 case VPROLVDZ256rrk:
17441 case VPROLVDZ256rrkz:
17442 case VPROLVDZrm:
17443 case VPROLVDZrmb:
17444 case VPROLVDZrmbk:
17445 case VPROLVDZrmbkz:
17446 case VPROLVDZrmk:
17447 case VPROLVDZrmkz:
17448 case VPROLVDZrr:
17449 case VPROLVDZrrk:
17450 case VPROLVDZrrkz:
17451 return true;
17452 }
17453 return false;
17454}
17455
17456bool isWRFSBASE(unsigned Opcode) {
17457 switch (Opcode) {
17458 case WRFSBASE:
17459 case WRFSBASE64:
17460 return true;
17461 }
17462 return false;
17463}
17464
17465bool isVRSQRT14PS(unsigned Opcode) {
17466 switch (Opcode) {
17467 case VRSQRT14PSZ128m:
17468 case VRSQRT14PSZ128mb:
17469 case VRSQRT14PSZ128mbk:
17470 case VRSQRT14PSZ128mbkz:
17471 case VRSQRT14PSZ128mk:
17472 case VRSQRT14PSZ128mkz:
17473 case VRSQRT14PSZ128r:
17474 case VRSQRT14PSZ128rk:
17475 case VRSQRT14PSZ128rkz:
17476 case VRSQRT14PSZ256m:
17477 case VRSQRT14PSZ256mb:
17478 case VRSQRT14PSZ256mbk:
17479 case VRSQRT14PSZ256mbkz:
17480 case VRSQRT14PSZ256mk:
17481 case VRSQRT14PSZ256mkz:
17482 case VRSQRT14PSZ256r:
17483 case VRSQRT14PSZ256rk:
17484 case VRSQRT14PSZ256rkz:
17485 case VRSQRT14PSZm:
17486 case VRSQRT14PSZmb:
17487 case VRSQRT14PSZmbk:
17488 case VRSQRT14PSZmbkz:
17489 case VRSQRT14PSZmk:
17490 case VRSQRT14PSZmkz:
17491 case VRSQRT14PSZr:
17492 case VRSQRT14PSZrk:
17493 case VRSQRT14PSZrkz:
17494 return true;
17495 }
17496 return false;
17497}
17498
17499bool isVPHSUBDQ(unsigned Opcode) {
17500 switch (Opcode) {
17501 case VPHSUBDQrm:
17502 case VPHSUBDQrr:
17503 return true;
17504 }
17505 return false;
17506}
17507
17508bool isIRETD(unsigned Opcode) {
17509 return Opcode == IRET32;
17510}
17511
17512bool isVMOVRSD(unsigned Opcode) {
17513 switch (Opcode) {
17514 case VMOVRSDZ128m:
17515 case VMOVRSDZ128mk:
17516 case VMOVRSDZ128mkz:
17517 case VMOVRSDZ256m:
17518 case VMOVRSDZ256mk:
17519 case VMOVRSDZ256mkz:
17520 case VMOVRSDZm:
17521 case VMOVRSDZmk:
17522 case VMOVRSDZmkz:
17523 return true;
17524 }
17525 return false;
17526}
17527
17528bool isVPMULHRSW(unsigned Opcode) {
17529 switch (Opcode) {
17530 case VPMULHRSWYrm:
17531 case VPMULHRSWYrr:
17532 case VPMULHRSWZ128rm:
17533 case VPMULHRSWZ128rmk:
17534 case VPMULHRSWZ128rmkz:
17535 case VPMULHRSWZ128rr:
17536 case VPMULHRSWZ128rrk:
17537 case VPMULHRSWZ128rrkz:
17538 case VPMULHRSWZ256rm:
17539 case VPMULHRSWZ256rmk:
17540 case VPMULHRSWZ256rmkz:
17541 case VPMULHRSWZ256rr:
17542 case VPMULHRSWZ256rrk:
17543 case VPMULHRSWZ256rrkz:
17544 case VPMULHRSWZrm:
17545 case VPMULHRSWZrmk:
17546 case VPMULHRSWZrmkz:
17547 case VPMULHRSWZrr:
17548 case VPMULHRSWZrrk:
17549 case VPMULHRSWZrrkz:
17550 case VPMULHRSWrm:
17551 case VPMULHRSWrr:
17552 return true;
17553 }
17554 return false;
17555}
17556
17557bool isCVTSI2SS(unsigned Opcode) {
17558 switch (Opcode) {
17559 case CVTSI2SSrm_Int:
17560 case CVTSI2SSrr_Int:
17561 case CVTSI642SSrm_Int:
17562 case CVTSI642SSrr_Int:
17563 return true;
17564 }
17565 return false;
17566}
17567
17568bool isPI2FD(unsigned Opcode) {
17569 switch (Opcode) {
17570 case PI2FDrm:
17571 case PI2FDrr:
17572 return true;
17573 }
17574 return false;
17575}
17576
17577bool isGF2P8AFFINEQB(unsigned Opcode) {
17578 switch (Opcode) {
17579 case GF2P8AFFINEQBrmi:
17580 case GF2P8AFFINEQBrri:
17581 return true;
17582 }
17583 return false;
17584}
17585
17586bool isPAND(unsigned Opcode) {
17587 switch (Opcode) {
17588 case MMX_PANDrm:
17589 case MMX_PANDrr:
17590 case PANDrm:
17591 case PANDrr:
17592 return true;
17593 }
17594 return false;
17595}
17596
17597bool isVFNMSUB231SH(unsigned Opcode) {
17598 switch (Opcode) {
17599 case VFNMSUB231SHZm_Int:
17600 case VFNMSUB231SHZmk_Int:
17601 case VFNMSUB231SHZmkz_Int:
17602 case VFNMSUB231SHZr_Int:
17603 case VFNMSUB231SHZrb_Int:
17604 case VFNMSUB231SHZrbk_Int:
17605 case VFNMSUB231SHZrbkz_Int:
17606 case VFNMSUB231SHZrk_Int:
17607 case VFNMSUB231SHZrkz_Int:
17608 return true;
17609 }
17610 return false;
17611}
17612
17613bool isVMOVHLPS(unsigned Opcode) {
17614 switch (Opcode) {
17615 case VMOVHLPSZrr:
17616 case VMOVHLPSrr:
17617 return true;
17618 }
17619 return false;
17620}
17621
17622bool isKNOTD(unsigned Opcode) {
17623 return Opcode == KNOTDkk;
17624}
17625
17626bool isPEXTRB(unsigned Opcode) {
17627 switch (Opcode) {
17628 case PEXTRBmri:
17629 case PEXTRBrri:
17630 return true;
17631 }
17632 return false;
17633}
17634
17635bool isVCVTPH2BF8(unsigned Opcode) {
17636 switch (Opcode) {
17637 case VCVTPH2BF8Z128rm:
17638 case VCVTPH2BF8Z128rmb:
17639 case VCVTPH2BF8Z128rmbk:
17640 case VCVTPH2BF8Z128rmbkz:
17641 case VCVTPH2BF8Z128rmk:
17642 case VCVTPH2BF8Z128rmkz:
17643 case VCVTPH2BF8Z128rr:
17644 case VCVTPH2BF8Z128rrk:
17645 case VCVTPH2BF8Z128rrkz:
17646 case VCVTPH2BF8Z256rm:
17647 case VCVTPH2BF8Z256rmb:
17648 case VCVTPH2BF8Z256rmbk:
17649 case VCVTPH2BF8Z256rmbkz:
17650 case VCVTPH2BF8Z256rmk:
17651 case VCVTPH2BF8Z256rmkz:
17652 case VCVTPH2BF8Z256rr:
17653 case VCVTPH2BF8Z256rrk:
17654 case VCVTPH2BF8Z256rrkz:
17655 case VCVTPH2BF8Zrm:
17656 case VCVTPH2BF8Zrmb:
17657 case VCVTPH2BF8Zrmbk:
17658 case VCVTPH2BF8Zrmbkz:
17659 case VCVTPH2BF8Zrmk:
17660 case VCVTPH2BF8Zrmkz:
17661 case VCVTPH2BF8Zrr:
17662 case VCVTPH2BF8Zrrk:
17663 case VCVTPH2BF8Zrrkz:
17664 return true;
17665 }
17666 return false;
17667}
17668
17669bool isVMMCALL(unsigned Opcode) {
17670 return Opcode == VMMCALL;
17671}
17672
17673bool isVCVTSH2SS(unsigned Opcode) {
17674 switch (Opcode) {
17675 case VCVTSH2SSZrm_Int:
17676 case VCVTSH2SSZrmk_Int:
17677 case VCVTSH2SSZrmkz_Int:
17678 case VCVTSH2SSZrr_Int:
17679 case VCVTSH2SSZrrb_Int:
17680 case VCVTSH2SSZrrbk_Int:
17681 case VCVTSH2SSZrrbkz_Int:
17682 case VCVTSH2SSZrrk_Int:
17683 case VCVTSH2SSZrrkz_Int:
17684 return true;
17685 }
17686 return false;
17687}
17688
17689bool isVPUNPCKLQDQ(unsigned Opcode) {
17690 switch (Opcode) {
17691 case VPUNPCKLQDQYrm:
17692 case VPUNPCKLQDQYrr:
17693 case VPUNPCKLQDQZ128rm:
17694 case VPUNPCKLQDQZ128rmb:
17695 case VPUNPCKLQDQZ128rmbk:
17696 case VPUNPCKLQDQZ128rmbkz:
17697 case VPUNPCKLQDQZ128rmk:
17698 case VPUNPCKLQDQZ128rmkz:
17699 case VPUNPCKLQDQZ128rr:
17700 case VPUNPCKLQDQZ128rrk:
17701 case VPUNPCKLQDQZ128rrkz:
17702 case VPUNPCKLQDQZ256rm:
17703 case VPUNPCKLQDQZ256rmb:
17704 case VPUNPCKLQDQZ256rmbk:
17705 case VPUNPCKLQDQZ256rmbkz:
17706 case VPUNPCKLQDQZ256rmk:
17707 case VPUNPCKLQDQZ256rmkz:
17708 case VPUNPCKLQDQZ256rr:
17709 case VPUNPCKLQDQZ256rrk:
17710 case VPUNPCKLQDQZ256rrkz:
17711 case VPUNPCKLQDQZrm:
17712 case VPUNPCKLQDQZrmb:
17713 case VPUNPCKLQDQZrmbk:
17714 case VPUNPCKLQDQZrmbkz:
17715 case VPUNPCKLQDQZrmk:
17716 case VPUNPCKLQDQZrmkz:
17717 case VPUNPCKLQDQZrr:
17718 case VPUNPCKLQDQZrrk:
17719 case VPUNPCKLQDQZrrkz:
17720 case VPUNPCKLQDQrm:
17721 case VPUNPCKLQDQrr:
17722 return true;
17723 }
17724 return false;
17725}
17726
17727bool isVPERMIL2PS(unsigned Opcode) {
17728 switch (Opcode) {
17729 case VPERMIL2PSYmr:
17730 case VPERMIL2PSYrm:
17731 case VPERMIL2PSYrr:
17732 case VPERMIL2PSYrr_REV:
17733 case VPERMIL2PSmr:
17734 case VPERMIL2PSrm:
17735 case VPERMIL2PSrr:
17736 case VPERMIL2PSrr_REV:
17737 return true;
17738 }
17739 return false;
17740}
17741
17742bool isVPCMPGTD(unsigned Opcode) {
17743 switch (Opcode) {
17744 case VPCMPGTDYrm:
17745 case VPCMPGTDYrr:
17746 case VPCMPGTDZ128rm:
17747 case VPCMPGTDZ128rmb:
17748 case VPCMPGTDZ128rmbk:
17749 case VPCMPGTDZ128rmk:
17750 case VPCMPGTDZ128rr:
17751 case VPCMPGTDZ128rrk:
17752 case VPCMPGTDZ256rm:
17753 case VPCMPGTDZ256rmb:
17754 case VPCMPGTDZ256rmbk:
17755 case VPCMPGTDZ256rmk:
17756 case VPCMPGTDZ256rr:
17757 case VPCMPGTDZ256rrk:
17758 case VPCMPGTDZrm:
17759 case VPCMPGTDZrmb:
17760 case VPCMPGTDZrmbk:
17761 case VPCMPGTDZrmk:
17762 case VPCMPGTDZrr:
17763 case VPCMPGTDZrrk:
17764 case VPCMPGTDrm:
17765 case VPCMPGTDrr:
17766 return true;
17767 }
17768 return false;
17769}
17770
17771bool isCMPXCHG16B(unsigned Opcode) {
17772 return Opcode == CMPXCHG16B;
17773}
17774
17775bool isTDPHF8PS(unsigned Opcode) {
17776 return Opcode == TDPHF8PS;
17777}
17778
17779bool isVZEROUPPER(unsigned Opcode) {
17780 return Opcode == VZEROUPPER;
17781}
17782
17783bool isMOVAPS(unsigned Opcode) {
17784 switch (Opcode) {
17785 case MOVAPSmr:
17786 case MOVAPSrm:
17787 case MOVAPSrr:
17788 case MOVAPSrr_REV:
17789 return true;
17790 }
17791 return false;
17792}
17793
17794bool isRMPOPT(unsigned Opcode) {
17795 return Opcode == RMPOPT;
17796}
17797
17798bool isFUCOMPP(unsigned Opcode) {
17799 return Opcode == UCOM_FPPr;
17800}
17801
17802bool isVPCMPW(unsigned Opcode) {
17803 switch (Opcode) {
17804 case VPCMPWZ128rmi:
17805 case VPCMPWZ128rmik:
17806 case VPCMPWZ128rri:
17807 case VPCMPWZ128rrik:
17808 case VPCMPWZ256rmi:
17809 case VPCMPWZ256rmik:
17810 case VPCMPWZ256rri:
17811 case VPCMPWZ256rrik:
17812 case VPCMPWZrmi:
17813 case VPCMPWZrmik:
17814 case VPCMPWZrri:
17815 case VPCMPWZrrik:
17816 return true;
17817 }
17818 return false;
17819}
17820
17821bool isXSETBV(unsigned Opcode) {
17822 return Opcode == XSETBV;
17823}
17824
17825bool isSLWPCB(unsigned Opcode) {
17826 switch (Opcode) {
17827 case SLWPCB:
17828 case SLWPCB64:
17829 return true;
17830 }
17831 return false;
17832}
17833
17834bool isSCASW(unsigned Opcode) {
17835 return Opcode == SCASW;
17836}
17837
17838bool isFCMOVNE(unsigned Opcode) {
17839 return Opcode == CMOVNE_F;
17840}
17841
17842bool isPBNDKB(unsigned Opcode) {
17843 return Opcode == PBNDKB;
17844}
17845
17846bool isVPMULLD(unsigned Opcode) {
17847 switch (Opcode) {
17848 case VPMULLDYrm:
17849 case VPMULLDYrr:
17850 case VPMULLDZ128rm:
17851 case VPMULLDZ128rmb:
17852 case VPMULLDZ128rmbk:
17853 case VPMULLDZ128rmbkz:
17854 case VPMULLDZ128rmk:
17855 case VPMULLDZ128rmkz:
17856 case VPMULLDZ128rr:
17857 case VPMULLDZ128rrk:
17858 case VPMULLDZ128rrkz:
17859 case VPMULLDZ256rm:
17860 case VPMULLDZ256rmb:
17861 case VPMULLDZ256rmbk:
17862 case VPMULLDZ256rmbkz:
17863 case VPMULLDZ256rmk:
17864 case VPMULLDZ256rmkz:
17865 case VPMULLDZ256rr:
17866 case VPMULLDZ256rrk:
17867 case VPMULLDZ256rrkz:
17868 case VPMULLDZrm:
17869 case VPMULLDZrmb:
17870 case VPMULLDZrmbk:
17871 case VPMULLDZrmbkz:
17872 case VPMULLDZrmk:
17873 case VPMULLDZrmkz:
17874 case VPMULLDZrr:
17875 case VPMULLDZrrk:
17876 case VPMULLDZrrkz:
17877 case VPMULLDrm:
17878 case VPMULLDrr:
17879 return true;
17880 }
17881 return false;
17882}
17883
17884bool isVP4DPWSSDS(unsigned Opcode) {
17885 switch (Opcode) {
17886 case VP4DPWSSDSrm:
17887 case VP4DPWSSDSrmk:
17888 case VP4DPWSSDSrmkz:
17889 return true;
17890 }
17891 return false;
17892}
17893
17894bool isVCVT2PH2HF8(unsigned Opcode) {
17895 switch (Opcode) {
17896 case VCVT2PH2HF8Z128rm:
17897 case VCVT2PH2HF8Z128rmb:
17898 case VCVT2PH2HF8Z128rmbk:
17899 case VCVT2PH2HF8Z128rmbkz:
17900 case VCVT2PH2HF8Z128rmk:
17901 case VCVT2PH2HF8Z128rmkz:
17902 case VCVT2PH2HF8Z128rr:
17903 case VCVT2PH2HF8Z128rrk:
17904 case VCVT2PH2HF8Z128rrkz:
17905 case VCVT2PH2HF8Z256rm:
17906 case VCVT2PH2HF8Z256rmb:
17907 case VCVT2PH2HF8Z256rmbk:
17908 case VCVT2PH2HF8Z256rmbkz:
17909 case VCVT2PH2HF8Z256rmk:
17910 case VCVT2PH2HF8Z256rmkz:
17911 case VCVT2PH2HF8Z256rr:
17912 case VCVT2PH2HF8Z256rrk:
17913 case VCVT2PH2HF8Z256rrkz:
17914 case VCVT2PH2HF8Zrm:
17915 case VCVT2PH2HF8Zrmb:
17916 case VCVT2PH2HF8Zrmbk:
17917 case VCVT2PH2HF8Zrmbkz:
17918 case VCVT2PH2HF8Zrmk:
17919 case VCVT2PH2HF8Zrmkz:
17920 case VCVT2PH2HF8Zrr:
17921 case VCVT2PH2HF8Zrrk:
17922 case VCVT2PH2HF8Zrrkz:
17923 return true;
17924 }
17925 return false;
17926}
17927
17928bool isPINSRW(unsigned Opcode) {
17929 switch (Opcode) {
17930 case MMX_PINSRWrmi:
17931 case MMX_PINSRWrri:
17932 case PINSRWrmi:
17933 case PINSRWrri:
17934 return true;
17935 }
17936 return false;
17937}
17938
17939bool isVCVTSI2SH(unsigned Opcode) {
17940 switch (Opcode) {
17941 case VCVTSI2SHZrm_Int:
17942 case VCVTSI2SHZrr_Int:
17943 case VCVTSI2SHZrrb_Int:
17944 case VCVTSI642SHZrm_Int:
17945 case VCVTSI642SHZrr_Int:
17946 case VCVTSI642SHZrrb_Int:
17947 return true;
17948 }
17949 return false;
17950}
17951
17952bool isVINSERTF32X8(unsigned Opcode) {
17953 switch (Opcode) {
17954 case VINSERTF32X8Zrmi:
17955 case VINSERTF32X8Zrmik:
17956 case VINSERTF32X8Zrmikz:
17957 case VINSERTF32X8Zrri:
17958 case VINSERTF32X8Zrrik:
17959 case VINSERTF32X8Zrrikz:
17960 return true;
17961 }
17962 return false;
17963}
17964
17965bool isKSHIFTLB(unsigned Opcode) {
17966 return Opcode == KSHIFTLBki;
17967}
17968
17969bool isSEAMOPS(unsigned Opcode) {
17970 return Opcode == SEAMOPS;
17971}
17972
17973bool isVPMOVSQB(unsigned Opcode) {
17974 switch (Opcode) {
17975 case VPMOVSQBZ128mr:
17976 case VPMOVSQBZ128mrk:
17977 case VPMOVSQBZ128rr:
17978 case VPMOVSQBZ128rrk:
17979 case VPMOVSQBZ128rrkz:
17980 case VPMOVSQBZ256mr:
17981 case VPMOVSQBZ256mrk:
17982 case VPMOVSQBZ256rr:
17983 case VPMOVSQBZ256rrk:
17984 case VPMOVSQBZ256rrkz:
17985 case VPMOVSQBZmr:
17986 case VPMOVSQBZmrk:
17987 case VPMOVSQBZrr:
17988 case VPMOVSQBZrrk:
17989 case VPMOVSQBZrrkz:
17990 return true;
17991 }
17992 return false;
17993}
17994
17995bool isVPMULUDQ(unsigned Opcode) {
17996 switch (Opcode) {
17997 case VPMULUDQYrm:
17998 case VPMULUDQYrr:
17999 case VPMULUDQZ128rm:
18000 case VPMULUDQZ128rmb:
18001 case VPMULUDQZ128rmbk:
18002 case VPMULUDQZ128rmbkz:
18003 case VPMULUDQZ128rmk:
18004 case VPMULUDQZ128rmkz:
18005 case VPMULUDQZ128rr:
18006 case VPMULUDQZ128rrk:
18007 case VPMULUDQZ128rrkz:
18008 case VPMULUDQZ256rm:
18009 case VPMULUDQZ256rmb:
18010 case VPMULUDQZ256rmbk:
18011 case VPMULUDQZ256rmbkz:
18012 case VPMULUDQZ256rmk:
18013 case VPMULUDQZ256rmkz:
18014 case VPMULUDQZ256rr:
18015 case VPMULUDQZ256rrk:
18016 case VPMULUDQZ256rrkz:
18017 case VPMULUDQZrm:
18018 case VPMULUDQZrmb:
18019 case VPMULUDQZrmbk:
18020 case VPMULUDQZrmbkz:
18021 case VPMULUDQZrmk:
18022 case VPMULUDQZrmkz:
18023 case VPMULUDQZrr:
18024 case VPMULUDQZrrk:
18025 case VPMULUDQZrrkz:
18026 case VPMULUDQrm:
18027 case VPMULUDQrr:
18028 return true;
18029 }
18030 return false;
18031}
18032
18033bool isVPTESTMD(unsigned Opcode) {
18034 switch (Opcode) {
18035 case VPTESTMDZ128rm:
18036 case VPTESTMDZ128rmb:
18037 case VPTESTMDZ128rmbk:
18038 case VPTESTMDZ128rmk:
18039 case VPTESTMDZ128rr:
18040 case VPTESTMDZ128rrk:
18041 case VPTESTMDZ256rm:
18042 case VPTESTMDZ256rmb:
18043 case VPTESTMDZ256rmbk:
18044 case VPTESTMDZ256rmk:
18045 case VPTESTMDZ256rr:
18046 case VPTESTMDZ256rrk:
18047 case VPTESTMDZrm:
18048 case VPTESTMDZrmb:
18049 case VPTESTMDZrmbk:
18050 case VPTESTMDZrmk:
18051 case VPTESTMDZrr:
18052 case VPTESTMDZrrk:
18053 return true;
18054 }
18055 return false;
18056}
18057
18058bool isVPHADDDQ(unsigned Opcode) {
18059 switch (Opcode) {
18060 case VPHADDDQrm:
18061 case VPHADDDQrr:
18062 return true;
18063 }
18064 return false;
18065}
18066
18067bool isKUNPCKDQ(unsigned Opcode) {
18068 return Opcode == KUNPCKDQkk;
18069}
18070
18071bool isT1MSKC(unsigned Opcode) {
18072 switch (Opcode) {
18073 case T1MSKC32rm:
18074 case T1MSKC32rr:
18075 case T1MSKC64rm:
18076 case T1MSKC64rr:
18077 return true;
18078 }
18079 return false;
18080}
18081
18082bool isVBLENDPS(unsigned Opcode) {
18083 switch (Opcode) {
18084 case VBLENDPSYrmi:
18085 case VBLENDPSYrri:
18086 case VBLENDPSrmi:
18087 case VBLENDPSrri:
18088 return true;
18089 }
18090 return false;
18091}
18092
18093bool isVPCOMB(unsigned Opcode) {
18094 switch (Opcode) {
18095 case VPCOMBmi:
18096 case VPCOMBri:
18097 return true;
18098 }
18099 return false;
18100}
18101
18102bool isPTWRITE(unsigned Opcode) {
18103 switch (Opcode) {
18104 case PTWRITE64m:
18105 case PTWRITE64r:
18106 case PTWRITEm:
18107 case PTWRITEr:
18108 return true;
18109 }
18110 return false;
18111}
18112
18113bool isVCVTPH2BF8S(unsigned Opcode) {
18114 switch (Opcode) {
18115 case VCVTPH2BF8SZ128rm:
18116 case VCVTPH2BF8SZ128rmb:
18117 case VCVTPH2BF8SZ128rmbk:
18118 case VCVTPH2BF8SZ128rmbkz:
18119 case VCVTPH2BF8SZ128rmk:
18120 case VCVTPH2BF8SZ128rmkz:
18121 case VCVTPH2BF8SZ128rr:
18122 case VCVTPH2BF8SZ128rrk:
18123 case VCVTPH2BF8SZ128rrkz:
18124 case VCVTPH2BF8SZ256rm:
18125 case VCVTPH2BF8SZ256rmb:
18126 case VCVTPH2BF8SZ256rmbk:
18127 case VCVTPH2BF8SZ256rmbkz:
18128 case VCVTPH2BF8SZ256rmk:
18129 case VCVTPH2BF8SZ256rmkz:
18130 case VCVTPH2BF8SZ256rr:
18131 case VCVTPH2BF8SZ256rrk:
18132 case VCVTPH2BF8SZ256rrkz:
18133 case VCVTPH2BF8SZrm:
18134 case VCVTPH2BF8SZrmb:
18135 case VCVTPH2BF8SZrmbk:
18136 case VCVTPH2BF8SZrmbkz:
18137 case VCVTPH2BF8SZrmk:
18138 case VCVTPH2BF8SZrmkz:
18139 case VCVTPH2BF8SZrr:
18140 case VCVTPH2BF8SZrrk:
18141 case VCVTPH2BF8SZrrkz:
18142 return true;
18143 }
18144 return false;
18145}
18146
18147bool isCVTPS2PI(unsigned Opcode) {
18148 switch (Opcode) {
18149 case MMX_CVTPS2PIrm:
18150 case MMX_CVTPS2PIrr:
18151 return true;
18152 }
18153 return false;
18154}
18155
18156bool isVPROTD(unsigned Opcode) {
18157 switch (Opcode) {
18158 case VPROTDmi:
18159 case VPROTDmr:
18160 case VPROTDri:
18161 case VPROTDrm:
18162 case VPROTDrr:
18163 case VPROTDrr_REV:
18164 return true;
18165 }
18166 return false;
18167}
18168
18169bool isCALL(unsigned Opcode) {
18170 switch (Opcode) {
18171 case CALL16m:
18172 case CALL16r:
18173 case CALL32m:
18174 case CALL32r:
18175 case CALL64m:
18176 case CALL64pcrel32:
18177 case CALL64r:
18178 case CALLpcrel16:
18179 case CALLpcrel32:
18180 case FARCALL32m:
18181 return true;
18182 }
18183 return false;
18184}
18185
18186bool isTILELOADDRST1(unsigned Opcode) {
18187 switch (Opcode) {
18188 case TILELOADDRST1:
18189 case TILELOADDRST1_EVEX:
18190 return true;
18191 }
18192 return false;
18193}
18194
18195bool isVPERMPS(unsigned Opcode) {
18196 switch (Opcode) {
18197 case VPERMPSYrm:
18198 case VPERMPSYrr:
18199 case VPERMPSZ256rm:
18200 case VPERMPSZ256rmb:
18201 case VPERMPSZ256rmbk:
18202 case VPERMPSZ256rmbkz:
18203 case VPERMPSZ256rmk:
18204 case VPERMPSZ256rmkz:
18205 case VPERMPSZ256rr:
18206 case VPERMPSZ256rrk:
18207 case VPERMPSZ256rrkz:
18208 case VPERMPSZrm:
18209 case VPERMPSZrmb:
18210 case VPERMPSZrmbk:
18211 case VPERMPSZrmbkz:
18212 case VPERMPSZrmk:
18213 case VPERMPSZrmkz:
18214 case VPERMPSZrr:
18215 case VPERMPSZrrk:
18216 case VPERMPSZrrkz:
18217 return true;
18218 }
18219 return false;
18220}
18221
18222bool isVPSHUFBITQMB(unsigned Opcode) {
18223 switch (Opcode) {
18224 case VPSHUFBITQMBZ128rm:
18225 case VPSHUFBITQMBZ128rmk:
18226 case VPSHUFBITQMBZ128rr:
18227 case VPSHUFBITQMBZ128rrk:
18228 case VPSHUFBITQMBZ256rm:
18229 case VPSHUFBITQMBZ256rmk:
18230 case VPSHUFBITQMBZ256rr:
18231 case VPSHUFBITQMBZ256rrk:
18232 case VPSHUFBITQMBZrm:
18233 case VPSHUFBITQMBZrmk:
18234 case VPSHUFBITQMBZrr:
18235 case VPSHUFBITQMBZrrk:
18236 return true;
18237 }
18238 return false;
18239}
18240
18241bool isVMOVSLDUP(unsigned Opcode) {
18242 switch (Opcode) {
18243 case VMOVSLDUPYrm:
18244 case VMOVSLDUPYrr:
18245 case VMOVSLDUPZ128rm:
18246 case VMOVSLDUPZ128rmk:
18247 case VMOVSLDUPZ128rmkz:
18248 case VMOVSLDUPZ128rr:
18249 case VMOVSLDUPZ128rrk:
18250 case VMOVSLDUPZ128rrkz:
18251 case VMOVSLDUPZ256rm:
18252 case VMOVSLDUPZ256rmk:
18253 case VMOVSLDUPZ256rmkz:
18254 case VMOVSLDUPZ256rr:
18255 case VMOVSLDUPZ256rrk:
18256 case VMOVSLDUPZ256rrkz:
18257 case VMOVSLDUPZrm:
18258 case VMOVSLDUPZrmk:
18259 case VMOVSLDUPZrmkz:
18260 case VMOVSLDUPZrr:
18261 case VMOVSLDUPZrrk:
18262 case VMOVSLDUPZrrkz:
18263 case VMOVSLDUPrm:
18264 case VMOVSLDUPrr:
18265 return true;
18266 }
18267 return false;
18268}
18269
18270bool isINVLPGA(unsigned Opcode) {
18271 switch (Opcode) {
18272 case INVLPGA32:
18273 case INVLPGA64:
18274 return true;
18275 }
18276 return false;
18277}
18278
18279bool isVCVTPH2QQ(unsigned Opcode) {
18280 switch (Opcode) {
18281 case VCVTPH2QQZ128rm:
18282 case VCVTPH2QQZ128rmb:
18283 case VCVTPH2QQZ128rmbk:
18284 case VCVTPH2QQZ128rmbkz:
18285 case VCVTPH2QQZ128rmk:
18286 case VCVTPH2QQZ128rmkz:
18287 case VCVTPH2QQZ128rr:
18288 case VCVTPH2QQZ128rrk:
18289 case VCVTPH2QQZ128rrkz:
18290 case VCVTPH2QQZ256rm:
18291 case VCVTPH2QQZ256rmb:
18292 case VCVTPH2QQZ256rmbk:
18293 case VCVTPH2QQZ256rmbkz:
18294 case VCVTPH2QQZ256rmk:
18295 case VCVTPH2QQZ256rmkz:
18296 case VCVTPH2QQZ256rr:
18297 case VCVTPH2QQZ256rrk:
18298 case VCVTPH2QQZ256rrkz:
18299 case VCVTPH2QQZrm:
18300 case VCVTPH2QQZrmb:
18301 case VCVTPH2QQZrmbk:
18302 case VCVTPH2QQZrmbkz:
18303 case VCVTPH2QQZrmk:
18304 case VCVTPH2QQZrmkz:
18305 case VCVTPH2QQZrr:
18306 case VCVTPH2QQZrrb:
18307 case VCVTPH2QQZrrbk:
18308 case VCVTPH2QQZrrbkz:
18309 case VCVTPH2QQZrrk:
18310 case VCVTPH2QQZrrkz:
18311 return true;
18312 }
18313 return false;
18314}
18315
18316bool isADD(unsigned Opcode) {
18317 switch (Opcode) {
18318 case ADD16i16:
18319 case ADD16mi:
18320 case ADD16mi8:
18321 case ADD16mi8_EVEX:
18322 case ADD16mi8_ND:
18323 case ADD16mi8_NF:
18324 case ADD16mi8_NF_ND:
18325 case ADD16mi_EVEX:
18326 case ADD16mi_ND:
18327 case ADD16mi_NF:
18328 case ADD16mi_NF_ND:
18329 case ADD16mr:
18330 case ADD16mr_EVEX:
18331 case ADD16mr_ND:
18332 case ADD16mr_NF:
18333 case ADD16mr_NF_ND:
18334 case ADD16ri:
18335 case ADD16ri8:
18336 case ADD16ri8_EVEX:
18337 case ADD16ri8_ND:
18338 case ADD16ri8_NF:
18339 case ADD16ri8_NF_ND:
18340 case ADD16ri_EVEX:
18341 case ADD16ri_ND:
18342 case ADD16ri_NF:
18343 case ADD16ri_NF_ND:
18344 case ADD16rm:
18345 case ADD16rm_EVEX:
18346 case ADD16rm_ND:
18347 case ADD16rm_NF:
18348 case ADD16rm_NF_ND:
18349 case ADD16rr:
18350 case ADD16rr_EVEX:
18351 case ADD16rr_EVEX_REV:
18352 case ADD16rr_ND:
18353 case ADD16rr_ND_REV:
18354 case ADD16rr_NF:
18355 case ADD16rr_NF_ND:
18356 case ADD16rr_NF_ND_REV:
18357 case ADD16rr_NF_REV:
18358 case ADD16rr_REV:
18359 case ADD32i32:
18360 case ADD32mi:
18361 case ADD32mi8:
18362 case ADD32mi8_EVEX:
18363 case ADD32mi8_ND:
18364 case ADD32mi8_NF:
18365 case ADD32mi8_NF_ND:
18366 case ADD32mi_EVEX:
18367 case ADD32mi_ND:
18368 case ADD32mi_NF:
18369 case ADD32mi_NF_ND:
18370 case ADD32mr:
18371 case ADD32mr_EVEX:
18372 case ADD32mr_ND:
18373 case ADD32mr_NF:
18374 case ADD32mr_NF_ND:
18375 case ADD32ri:
18376 case ADD32ri8:
18377 case ADD32ri8_EVEX:
18378 case ADD32ri8_ND:
18379 case ADD32ri8_NF:
18380 case ADD32ri8_NF_ND:
18381 case ADD32ri_EVEX:
18382 case ADD32ri_ND:
18383 case ADD32ri_NF:
18384 case ADD32ri_NF_ND:
18385 case ADD32rm:
18386 case ADD32rm_EVEX:
18387 case ADD32rm_ND:
18388 case ADD32rm_NF:
18389 case ADD32rm_NF_ND:
18390 case ADD32rr:
18391 case ADD32rr_EVEX:
18392 case ADD32rr_EVEX_REV:
18393 case ADD32rr_ND:
18394 case ADD32rr_ND_REV:
18395 case ADD32rr_NF:
18396 case ADD32rr_NF_ND:
18397 case ADD32rr_NF_ND_REV:
18398 case ADD32rr_NF_REV:
18399 case ADD32rr_REV:
18400 case ADD64i32:
18401 case ADD64mi32:
18402 case ADD64mi32_EVEX:
18403 case ADD64mi32_ND:
18404 case ADD64mi32_NF:
18405 case ADD64mi32_NF_ND:
18406 case ADD64mi8:
18407 case ADD64mi8_EVEX:
18408 case ADD64mi8_ND:
18409 case ADD64mi8_NF:
18410 case ADD64mi8_NF_ND:
18411 case ADD64mr:
18412 case ADD64mr_EVEX:
18413 case ADD64mr_ND:
18414 case ADD64mr_NF:
18415 case ADD64mr_NF_ND:
18416 case ADD64ri32:
18417 case ADD64ri32_EVEX:
18418 case ADD64ri32_ND:
18419 case ADD64ri32_NF:
18420 case ADD64ri32_NF_ND:
18421 case ADD64ri8:
18422 case ADD64ri8_EVEX:
18423 case ADD64ri8_ND:
18424 case ADD64ri8_NF:
18425 case ADD64ri8_NF_ND:
18426 case ADD64rm:
18427 case ADD64rm_EVEX:
18428 case ADD64rm_ND:
18429 case ADD64rm_NF:
18430 case ADD64rm_NF_ND:
18431 case ADD64rr:
18432 case ADD64rr_EVEX:
18433 case ADD64rr_EVEX_REV:
18434 case ADD64rr_ND:
18435 case ADD64rr_ND_REV:
18436 case ADD64rr_NF:
18437 case ADD64rr_NF_ND:
18438 case ADD64rr_NF_ND_REV:
18439 case ADD64rr_NF_REV:
18440 case ADD64rr_REV:
18441 case ADD8i8:
18442 case ADD8mi:
18443 case ADD8mi8:
18444 case ADD8mi_EVEX:
18445 case ADD8mi_ND:
18446 case ADD8mi_NF:
18447 case ADD8mi_NF_ND:
18448 case ADD8mr:
18449 case ADD8mr_EVEX:
18450 case ADD8mr_ND:
18451 case ADD8mr_NF:
18452 case ADD8mr_NF_ND:
18453 case ADD8ri:
18454 case ADD8ri8:
18455 case ADD8ri_EVEX:
18456 case ADD8ri_ND:
18457 case ADD8ri_NF:
18458 case ADD8ri_NF_ND:
18459 case ADD8rm:
18460 case ADD8rm_EVEX:
18461 case ADD8rm_ND:
18462 case ADD8rm_NF:
18463 case ADD8rm_NF_ND:
18464 case ADD8rr:
18465 case ADD8rr_EVEX:
18466 case ADD8rr_EVEX_REV:
18467 case ADD8rr_ND:
18468 case ADD8rr_ND_REV:
18469 case ADD8rr_NF:
18470 case ADD8rr_NF_ND:
18471 case ADD8rr_NF_ND_REV:
18472 case ADD8rr_NF_REV:
18473 case ADD8rr_REV:
18474 return true;
18475 }
18476 return false;
18477}
18478
18479bool isPSUBSW(unsigned Opcode) {
18480 switch (Opcode) {
18481 case MMX_PSUBSWrm:
18482 case MMX_PSUBSWrr:
18483 case PSUBSWrm:
18484 case PSUBSWrr:
18485 return true;
18486 }
18487 return false;
18488}
18489
18490bool isSIDTW(unsigned Opcode) {
18491 return Opcode == SIDT16m;
18492}
18493
18494bool isVEXTRACTF64X2(unsigned Opcode) {
18495 switch (Opcode) {
18496 case VEXTRACTF64X2Z256mri:
18497 case VEXTRACTF64X2Z256mrik:
18498 case VEXTRACTF64X2Z256rri:
18499 case VEXTRACTF64X2Z256rrik:
18500 case VEXTRACTF64X2Z256rrikz:
18501 case VEXTRACTF64X2Zmri:
18502 case VEXTRACTF64X2Zmrik:
18503 case VEXTRACTF64X2Zrri:
18504 case VEXTRACTF64X2Zrrik:
18505 case VEXTRACTF64X2Zrrikz:
18506 return true;
18507 }
18508 return false;
18509}
18510
18511bool isVFNMADD231PH(unsigned Opcode) {
18512 switch (Opcode) {
18513 case VFNMADD231PHZ128m:
18514 case VFNMADD231PHZ128mb:
18515 case VFNMADD231PHZ128mbk:
18516 case VFNMADD231PHZ128mbkz:
18517 case VFNMADD231PHZ128mk:
18518 case VFNMADD231PHZ128mkz:
18519 case VFNMADD231PHZ128r:
18520 case VFNMADD231PHZ128rk:
18521 case VFNMADD231PHZ128rkz:
18522 case VFNMADD231PHZ256m:
18523 case VFNMADD231PHZ256mb:
18524 case VFNMADD231PHZ256mbk:
18525 case VFNMADD231PHZ256mbkz:
18526 case VFNMADD231PHZ256mk:
18527 case VFNMADD231PHZ256mkz:
18528 case VFNMADD231PHZ256r:
18529 case VFNMADD231PHZ256rk:
18530 case VFNMADD231PHZ256rkz:
18531 case VFNMADD231PHZm:
18532 case VFNMADD231PHZmb:
18533 case VFNMADD231PHZmbk:
18534 case VFNMADD231PHZmbkz:
18535 case VFNMADD231PHZmk:
18536 case VFNMADD231PHZmkz:
18537 case VFNMADD231PHZr:
18538 case VFNMADD231PHZrb:
18539 case VFNMADD231PHZrbk:
18540 case VFNMADD231PHZrbkz:
18541 case VFNMADD231PHZrk:
18542 case VFNMADD231PHZrkz:
18543 return true;
18544 }
18545 return false;
18546}
18547
18548bool isFCOMI(unsigned Opcode) {
18549 return Opcode == COM_FIr;
18550}
18551
18552bool isRSM(unsigned Opcode) {
18553 return Opcode == RSM;
18554}
18555
18556bool isVPCOMUD(unsigned Opcode) {
18557 switch (Opcode) {
18558 case VPCOMUDmi:
18559 case VPCOMUDri:
18560 return true;
18561 }
18562 return false;
18563}
18564
18565bool isVPMOVZXBQ(unsigned Opcode) {
18566 switch (Opcode) {
18567 case VPMOVZXBQYrm:
18568 case VPMOVZXBQYrr:
18569 case VPMOVZXBQZ128rm:
18570 case VPMOVZXBQZ128rmk:
18571 case VPMOVZXBQZ128rmkz:
18572 case VPMOVZXBQZ128rr:
18573 case VPMOVZXBQZ128rrk:
18574 case VPMOVZXBQZ128rrkz:
18575 case VPMOVZXBQZ256rm:
18576 case VPMOVZXBQZ256rmk:
18577 case VPMOVZXBQZ256rmkz:
18578 case VPMOVZXBQZ256rr:
18579 case VPMOVZXBQZ256rrk:
18580 case VPMOVZXBQZ256rrkz:
18581 case VPMOVZXBQZrm:
18582 case VPMOVZXBQZrmk:
18583 case VPMOVZXBQZrmkz:
18584 case VPMOVZXBQZrr:
18585 case VPMOVZXBQZrrk:
18586 case VPMOVZXBQZrrkz:
18587 case VPMOVZXBQrm:
18588 case VPMOVZXBQrr:
18589 return true;
18590 }
18591 return false;
18592}
18593
18594bool isUWRMSR(unsigned Opcode) {
18595 switch (Opcode) {
18596 case UWRMSRir:
18597 case UWRMSRir_EVEX:
18598 case UWRMSRrr:
18599 case UWRMSRrr_EVEX:
18600 return true;
18601 }
18602 return false;
18603}
18604
18605bool isLGS(unsigned Opcode) {
18606 switch (Opcode) {
18607 case LGS16rm:
18608 case LGS32rm:
18609 case LGS64rm:
18610 return true;
18611 }
18612 return false;
18613}
18614
18615bool isVMOVNTPD(unsigned Opcode) {
18616 switch (Opcode) {
18617 case VMOVNTPDYmr:
18618 case VMOVNTPDZ128mr:
18619 case VMOVNTPDZ256mr:
18620 case VMOVNTPDZmr:
18621 case VMOVNTPDmr:
18622 return true;
18623 }
18624 return false;
18625}
18626
18627bool isPCMPESTRMQ(unsigned Opcode) {
18628 switch (Opcode) {
18629 case PCMPESTRMQrmi:
18630 case PCMPESTRMQrri:
18631 return true;
18632 }
18633 return false;
18634}
18635
18636bool isRDPRU(unsigned Opcode) {
18637 return Opcode == RDPRU;
18638}
18639
18640bool isVPUNPCKHBW(unsigned Opcode) {
18641 switch (Opcode) {
18642 case VPUNPCKHBWYrm:
18643 case VPUNPCKHBWYrr:
18644 case VPUNPCKHBWZ128rm:
18645 case VPUNPCKHBWZ128rmk:
18646 case VPUNPCKHBWZ128rmkz:
18647 case VPUNPCKHBWZ128rr:
18648 case VPUNPCKHBWZ128rrk:
18649 case VPUNPCKHBWZ128rrkz:
18650 case VPUNPCKHBWZ256rm:
18651 case VPUNPCKHBWZ256rmk:
18652 case VPUNPCKHBWZ256rmkz:
18653 case VPUNPCKHBWZ256rr:
18654 case VPUNPCKHBWZ256rrk:
18655 case VPUNPCKHBWZ256rrkz:
18656 case VPUNPCKHBWZrm:
18657 case VPUNPCKHBWZrmk:
18658 case VPUNPCKHBWZrmkz:
18659 case VPUNPCKHBWZrr:
18660 case VPUNPCKHBWZrrk:
18661 case VPUNPCKHBWZrrkz:
18662 case VPUNPCKHBWrm:
18663 case VPUNPCKHBWrr:
18664 return true;
18665 }
18666 return false;
18667}
18668
18669bool isVUCOMXSD(unsigned Opcode) {
18670 switch (Opcode) {
18671 case VUCOMXSDZrm_Int:
18672 case VUCOMXSDZrr_Int:
18673 case VUCOMXSDZrrb_Int:
18674 return true;
18675 }
18676 return false;
18677}
18678
18679bool isANDN(unsigned Opcode) {
18680 switch (Opcode) {
18681 case ANDN32rm:
18682 case ANDN32rm_EVEX:
18683 case ANDN32rm_NF:
18684 case ANDN32rr:
18685 case ANDN32rr_EVEX:
18686 case ANDN32rr_NF:
18687 case ANDN64rm:
18688 case ANDN64rm_EVEX:
18689 case ANDN64rm_NF:
18690 case ANDN64rr:
18691 case ANDN64rr_EVEX:
18692 case ANDN64rr_NF:
18693 return true;
18694 }
18695 return false;
18696}
18697
18698bool isVCVTTPH2UW(unsigned Opcode) {
18699 switch (Opcode) {
18700 case VCVTTPH2UWZ128rm:
18701 case VCVTTPH2UWZ128rmb:
18702 case VCVTTPH2UWZ128rmbk:
18703 case VCVTTPH2UWZ128rmbkz:
18704 case VCVTTPH2UWZ128rmk:
18705 case VCVTTPH2UWZ128rmkz:
18706 case VCVTTPH2UWZ128rr:
18707 case VCVTTPH2UWZ128rrk:
18708 case VCVTTPH2UWZ128rrkz:
18709 case VCVTTPH2UWZ256rm:
18710 case VCVTTPH2UWZ256rmb:
18711 case VCVTTPH2UWZ256rmbk:
18712 case VCVTTPH2UWZ256rmbkz:
18713 case VCVTTPH2UWZ256rmk:
18714 case VCVTTPH2UWZ256rmkz:
18715 case VCVTTPH2UWZ256rr:
18716 case VCVTTPH2UWZ256rrk:
18717 case VCVTTPH2UWZ256rrkz:
18718 case VCVTTPH2UWZrm:
18719 case VCVTTPH2UWZrmb:
18720 case VCVTTPH2UWZrmbk:
18721 case VCVTTPH2UWZrmbkz:
18722 case VCVTTPH2UWZrmk:
18723 case VCVTTPH2UWZrmkz:
18724 case VCVTTPH2UWZrr:
18725 case VCVTTPH2UWZrrb:
18726 case VCVTTPH2UWZrrbk:
18727 case VCVTTPH2UWZrrbkz:
18728 case VCVTTPH2UWZrrk:
18729 case VCVTTPH2UWZrrkz:
18730 return true;
18731 }
18732 return false;
18733}
18734
18735bool isVMFUNC(unsigned Opcode) {
18736 return Opcode == VMFUNC;
18737}
18738
18739bool isFIMUL(unsigned Opcode) {
18740 switch (Opcode) {
18741 case MUL_FI16m:
18742 case MUL_FI32m:
18743 return true;
18744 }
18745 return false;
18746}
18747
18748bool isBLCFILL(unsigned Opcode) {
18749 switch (Opcode) {
18750 case BLCFILL32rm:
18751 case BLCFILL32rr:
18752 case BLCFILL64rm:
18753 case BLCFILL64rr:
18754 return true;
18755 }
18756 return false;
18757}
18758
18759bool isVGATHERPF0DPS(unsigned Opcode) {
18760 return Opcode == VGATHERPF0DPSm;
18761}
18762
18763bool isVFMSUBADD231PS(unsigned Opcode) {
18764 switch (Opcode) {
18765 case VFMSUBADD231PSYm:
18766 case VFMSUBADD231PSYr:
18767 case VFMSUBADD231PSZ128m:
18768 case VFMSUBADD231PSZ128mb:
18769 case VFMSUBADD231PSZ128mbk:
18770 case VFMSUBADD231PSZ128mbkz:
18771 case VFMSUBADD231PSZ128mk:
18772 case VFMSUBADD231PSZ128mkz:
18773 case VFMSUBADD231PSZ128r:
18774 case VFMSUBADD231PSZ128rk:
18775 case VFMSUBADD231PSZ128rkz:
18776 case VFMSUBADD231PSZ256m:
18777 case VFMSUBADD231PSZ256mb:
18778 case VFMSUBADD231PSZ256mbk:
18779 case VFMSUBADD231PSZ256mbkz:
18780 case VFMSUBADD231PSZ256mk:
18781 case VFMSUBADD231PSZ256mkz:
18782 case VFMSUBADD231PSZ256r:
18783 case VFMSUBADD231PSZ256rk:
18784 case VFMSUBADD231PSZ256rkz:
18785 case VFMSUBADD231PSZm:
18786 case VFMSUBADD231PSZmb:
18787 case VFMSUBADD231PSZmbk:
18788 case VFMSUBADD231PSZmbkz:
18789 case VFMSUBADD231PSZmk:
18790 case VFMSUBADD231PSZmkz:
18791 case VFMSUBADD231PSZr:
18792 case VFMSUBADD231PSZrb:
18793 case VFMSUBADD231PSZrbk:
18794 case VFMSUBADD231PSZrbkz:
18795 case VFMSUBADD231PSZrk:
18796 case VFMSUBADD231PSZrkz:
18797 case VFMSUBADD231PSm:
18798 case VFMSUBADD231PSr:
18799 return true;
18800 }
18801 return false;
18802}
18803
18804bool isVREDUCESD(unsigned Opcode) {
18805 switch (Opcode) {
18806 case VREDUCESDZrmi:
18807 case VREDUCESDZrmik:
18808 case VREDUCESDZrmikz:
18809 case VREDUCESDZrri:
18810 case VREDUCESDZrrib:
18811 case VREDUCESDZrribk:
18812 case VREDUCESDZrribkz:
18813 case VREDUCESDZrrik:
18814 case VREDUCESDZrrikz:
18815 return true;
18816 }
18817 return false;
18818}
18819
18820bool isVCOMXSH(unsigned Opcode) {
18821 switch (Opcode) {
18822 case VCOMXSHZrm_Int:
18823 case VCOMXSHZrr_Int:
18824 case VCOMXSHZrrb_Int:
18825 return true;
18826 }
18827 return false;
18828}
18829
18830bool isVXORPS(unsigned Opcode) {
18831 switch (Opcode) {
18832 case VXORPSYrm:
18833 case VXORPSYrr:
18834 case VXORPSZ128rm:
18835 case VXORPSZ128rmb:
18836 case VXORPSZ128rmbk:
18837 case VXORPSZ128rmbkz:
18838 case VXORPSZ128rmk:
18839 case VXORPSZ128rmkz:
18840 case VXORPSZ128rr:
18841 case VXORPSZ128rrk:
18842 case VXORPSZ128rrkz:
18843 case VXORPSZ256rm:
18844 case VXORPSZ256rmb:
18845 case VXORPSZ256rmbk:
18846 case VXORPSZ256rmbkz:
18847 case VXORPSZ256rmk:
18848 case VXORPSZ256rmkz:
18849 case VXORPSZ256rr:
18850 case VXORPSZ256rrk:
18851 case VXORPSZ256rrkz:
18852 case VXORPSZrm:
18853 case VXORPSZrmb:
18854 case VXORPSZrmbk:
18855 case VXORPSZrmbkz:
18856 case VXORPSZrmk:
18857 case VXORPSZrmkz:
18858 case VXORPSZrr:
18859 case VXORPSZrrk:
18860 case VXORPSZrrkz:
18861 case VXORPSrm:
18862 case VXORPSrr:
18863 return true;
18864 }
18865 return false;
18866}
18867
18868bool isPSWAPD(unsigned Opcode) {
18869 switch (Opcode) {
18870 case PSWAPDrm:
18871 case PSWAPDrr:
18872 return true;
18873 }
18874 return false;
18875}
18876
18877bool isPMAXSD(unsigned Opcode) {
18878 switch (Opcode) {
18879 case PMAXSDrm:
18880 case PMAXSDrr:
18881 return true;
18882 }
18883 return false;
18884}
18885
18886bool isVCMPSS(unsigned Opcode) {
18887 switch (Opcode) {
18888 case VCMPSSZrmi_Int:
18889 case VCMPSSZrmik_Int:
18890 case VCMPSSZrri_Int:
18891 case VCMPSSZrrib_Int:
18892 case VCMPSSZrribk_Int:
18893 case VCMPSSZrrik_Int:
18894 case VCMPSSrmi_Int:
18895 case VCMPSSrri_Int:
18896 return true;
18897 }
18898 return false;
18899}
18900
18901bool isEXTRACTPS(unsigned Opcode) {
18902 switch (Opcode) {
18903 case EXTRACTPSmri:
18904 case EXTRACTPSrri:
18905 return true;
18906 }
18907 return false;
18908}
18909
18910bool isVPMOVZXBD(unsigned Opcode) {
18911 switch (Opcode) {
18912 case VPMOVZXBDYrm:
18913 case VPMOVZXBDYrr:
18914 case VPMOVZXBDZ128rm:
18915 case VPMOVZXBDZ128rmk:
18916 case VPMOVZXBDZ128rmkz:
18917 case VPMOVZXBDZ128rr:
18918 case VPMOVZXBDZ128rrk:
18919 case VPMOVZXBDZ128rrkz:
18920 case VPMOVZXBDZ256rm:
18921 case VPMOVZXBDZ256rmk:
18922 case VPMOVZXBDZ256rmkz:
18923 case VPMOVZXBDZ256rr:
18924 case VPMOVZXBDZ256rrk:
18925 case VPMOVZXBDZ256rrkz:
18926 case VPMOVZXBDZrm:
18927 case VPMOVZXBDZrmk:
18928 case VPMOVZXBDZrmkz:
18929 case VPMOVZXBDZrr:
18930 case VPMOVZXBDZrrk:
18931 case VPMOVZXBDZrrkz:
18932 case VPMOVZXBDrm:
18933 case VPMOVZXBDrr:
18934 return true;
18935 }
18936 return false;
18937}
18938
18939bool isOUTSW(unsigned Opcode) {
18940 return Opcode == OUTSW;
18941}
18942
18943bool isKORTESTB(unsigned Opcode) {
18944 return Opcode == KORTESTBkk;
18945}
18946
18947bool isVREDUCEPS(unsigned Opcode) {
18948 switch (Opcode) {
18949 case VREDUCEPSZ128rmbi:
18950 case VREDUCEPSZ128rmbik:
18951 case VREDUCEPSZ128rmbikz:
18952 case VREDUCEPSZ128rmi:
18953 case VREDUCEPSZ128rmik:
18954 case VREDUCEPSZ128rmikz:
18955 case VREDUCEPSZ128rri:
18956 case VREDUCEPSZ128rrik:
18957 case VREDUCEPSZ128rrikz:
18958 case VREDUCEPSZ256rmbi:
18959 case VREDUCEPSZ256rmbik:
18960 case VREDUCEPSZ256rmbikz:
18961 case VREDUCEPSZ256rmi:
18962 case VREDUCEPSZ256rmik:
18963 case VREDUCEPSZ256rmikz:
18964 case VREDUCEPSZ256rri:
18965 case VREDUCEPSZ256rrik:
18966 case VREDUCEPSZ256rrikz:
18967 case VREDUCEPSZrmbi:
18968 case VREDUCEPSZrmbik:
18969 case VREDUCEPSZrmbikz:
18970 case VREDUCEPSZrmi:
18971 case VREDUCEPSZrmik:
18972 case VREDUCEPSZrmikz:
18973 case VREDUCEPSZrri:
18974 case VREDUCEPSZrrib:
18975 case VREDUCEPSZrribk:
18976 case VREDUCEPSZrribkz:
18977 case VREDUCEPSZrrik:
18978 case VREDUCEPSZrrikz:
18979 return true;
18980 }
18981 return false;
18982}
18983
18984bool isPEXTRW(unsigned Opcode) {
18985 switch (Opcode) {
18986 case MMX_PEXTRWrri:
18987 case PEXTRWmri:
18988 case PEXTRWrri:
18989 case PEXTRWrri_REV:
18990 return true;
18991 }
18992 return false;
18993}
18994
18995bool isFNINIT(unsigned Opcode) {
18996 return Opcode == FNINIT;
18997}
18998
18999bool isVCVTPH2IBS(unsigned Opcode) {
19000 switch (Opcode) {
19001 case VCVTPH2IBSZ128rm:
19002 case VCVTPH2IBSZ128rmb:
19003 case VCVTPH2IBSZ128rmbk:
19004 case VCVTPH2IBSZ128rmbkz:
19005 case VCVTPH2IBSZ128rmk:
19006 case VCVTPH2IBSZ128rmkz:
19007 case VCVTPH2IBSZ128rr:
19008 case VCVTPH2IBSZ128rrk:
19009 case VCVTPH2IBSZ128rrkz:
19010 case VCVTPH2IBSZ256rm:
19011 case VCVTPH2IBSZ256rmb:
19012 case VCVTPH2IBSZ256rmbk:
19013 case VCVTPH2IBSZ256rmbkz:
19014 case VCVTPH2IBSZ256rmk:
19015 case VCVTPH2IBSZ256rmkz:
19016 case VCVTPH2IBSZ256rr:
19017 case VCVTPH2IBSZ256rrk:
19018 case VCVTPH2IBSZ256rrkz:
19019 case VCVTPH2IBSZrm:
19020 case VCVTPH2IBSZrmb:
19021 case VCVTPH2IBSZrmbk:
19022 case VCVTPH2IBSZrmbkz:
19023 case VCVTPH2IBSZrmk:
19024 case VCVTPH2IBSZrmkz:
19025 case VCVTPH2IBSZrr:
19026 case VCVTPH2IBSZrrb:
19027 case VCVTPH2IBSZrrbk:
19028 case VCVTPH2IBSZrrbkz:
19029 case VCVTPH2IBSZrrk:
19030 case VCVTPH2IBSZrrkz:
19031 return true;
19032 }
19033 return false;
19034}
19035
19036bool isROL(unsigned Opcode) {
19037 switch (Opcode) {
19038 case ROL16m1:
19039 case ROL16m1_EVEX:
19040 case ROL16m1_ND:
19041 case ROL16m1_NF:
19042 case ROL16m1_NF_ND:
19043 case ROL16mCL:
19044 case ROL16mCL_EVEX:
19045 case ROL16mCL_ND:
19046 case ROL16mCL_NF:
19047 case ROL16mCL_NF_ND:
19048 case ROL16mi:
19049 case ROL16mi_EVEX:
19050 case ROL16mi_ND:
19051 case ROL16mi_NF:
19052 case ROL16mi_NF_ND:
19053 case ROL16r1:
19054 case ROL16r1_EVEX:
19055 case ROL16r1_ND:
19056 case ROL16r1_NF:
19057 case ROL16r1_NF_ND:
19058 case ROL16rCL:
19059 case ROL16rCL_EVEX:
19060 case ROL16rCL_ND:
19061 case ROL16rCL_NF:
19062 case ROL16rCL_NF_ND:
19063 case ROL16ri:
19064 case ROL16ri_EVEX:
19065 case ROL16ri_ND:
19066 case ROL16ri_NF:
19067 case ROL16ri_NF_ND:
19068 case ROL32m1:
19069 case ROL32m1_EVEX:
19070 case ROL32m1_ND:
19071 case ROL32m1_NF:
19072 case ROL32m1_NF_ND:
19073 case ROL32mCL:
19074 case ROL32mCL_EVEX:
19075 case ROL32mCL_ND:
19076 case ROL32mCL_NF:
19077 case ROL32mCL_NF_ND:
19078 case ROL32mi:
19079 case ROL32mi_EVEX:
19080 case ROL32mi_ND:
19081 case ROL32mi_NF:
19082 case ROL32mi_NF_ND:
19083 case ROL32r1:
19084 case ROL32r1_EVEX:
19085 case ROL32r1_ND:
19086 case ROL32r1_NF:
19087 case ROL32r1_NF_ND:
19088 case ROL32rCL:
19089 case ROL32rCL_EVEX:
19090 case ROL32rCL_ND:
19091 case ROL32rCL_NF:
19092 case ROL32rCL_NF_ND:
19093 case ROL32ri:
19094 case ROL32ri_EVEX:
19095 case ROL32ri_ND:
19096 case ROL32ri_NF:
19097 case ROL32ri_NF_ND:
19098 case ROL64m1:
19099 case ROL64m1_EVEX:
19100 case ROL64m1_ND:
19101 case ROL64m1_NF:
19102 case ROL64m1_NF_ND:
19103 case ROL64mCL:
19104 case ROL64mCL_EVEX:
19105 case ROL64mCL_ND:
19106 case ROL64mCL_NF:
19107 case ROL64mCL_NF_ND:
19108 case ROL64mi:
19109 case ROL64mi_EVEX:
19110 case ROL64mi_ND:
19111 case ROL64mi_NF:
19112 case ROL64mi_NF_ND:
19113 case ROL64r1:
19114 case ROL64r1_EVEX:
19115 case ROL64r1_ND:
19116 case ROL64r1_NF:
19117 case ROL64r1_NF_ND:
19118 case ROL64rCL:
19119 case ROL64rCL_EVEX:
19120 case ROL64rCL_ND:
19121 case ROL64rCL_NF:
19122 case ROL64rCL_NF_ND:
19123 case ROL64ri:
19124 case ROL64ri_EVEX:
19125 case ROL64ri_ND:
19126 case ROL64ri_NF:
19127 case ROL64ri_NF_ND:
19128 case ROL8m1:
19129 case ROL8m1_EVEX:
19130 case ROL8m1_ND:
19131 case ROL8m1_NF:
19132 case ROL8m1_NF_ND:
19133 case ROL8mCL:
19134 case ROL8mCL_EVEX:
19135 case ROL8mCL_ND:
19136 case ROL8mCL_NF:
19137 case ROL8mCL_NF_ND:
19138 case ROL8mi:
19139 case ROL8mi_EVEX:
19140 case ROL8mi_ND:
19141 case ROL8mi_NF:
19142 case ROL8mi_NF_ND:
19143 case ROL8r1:
19144 case ROL8r1_EVEX:
19145 case ROL8r1_ND:
19146 case ROL8r1_NF:
19147 case ROL8r1_NF_ND:
19148 case ROL8rCL:
19149 case ROL8rCL_EVEX:
19150 case ROL8rCL_ND:
19151 case ROL8rCL_NF:
19152 case ROL8rCL_NF_ND:
19153 case ROL8ri:
19154 case ROL8ri_EVEX:
19155 case ROL8ri_ND:
19156 case ROL8ri_NF:
19157 case ROL8ri_NF_ND:
19158 return true;
19159 }
19160 return false;
19161}
19162
19163bool isVCVTPS2QQ(unsigned Opcode) {
19164 switch (Opcode) {
19165 case VCVTPS2QQZ128rm:
19166 case VCVTPS2QQZ128rmb:
19167 case VCVTPS2QQZ128rmbk:
19168 case VCVTPS2QQZ128rmbkz:
19169 case VCVTPS2QQZ128rmk:
19170 case VCVTPS2QQZ128rmkz:
19171 case VCVTPS2QQZ128rr:
19172 case VCVTPS2QQZ128rrk:
19173 case VCVTPS2QQZ128rrkz:
19174 case VCVTPS2QQZ256rm:
19175 case VCVTPS2QQZ256rmb:
19176 case VCVTPS2QQZ256rmbk:
19177 case VCVTPS2QQZ256rmbkz:
19178 case VCVTPS2QQZ256rmk:
19179 case VCVTPS2QQZ256rmkz:
19180 case VCVTPS2QQZ256rr:
19181 case VCVTPS2QQZ256rrk:
19182 case VCVTPS2QQZ256rrkz:
19183 case VCVTPS2QQZrm:
19184 case VCVTPS2QQZrmb:
19185 case VCVTPS2QQZrmbk:
19186 case VCVTPS2QQZrmbkz:
19187 case VCVTPS2QQZrmk:
19188 case VCVTPS2QQZrmkz:
19189 case VCVTPS2QQZrr:
19190 case VCVTPS2QQZrrb:
19191 case VCVTPS2QQZrrbk:
19192 case VCVTPS2QQZrrbkz:
19193 case VCVTPS2QQZrrk:
19194 case VCVTPS2QQZrrkz:
19195 return true;
19196 }
19197 return false;
19198}
19199
19200bool isVGETMANTPH(unsigned Opcode) {
19201 switch (Opcode) {
19202 case VGETMANTPHZ128rmbi:
19203 case VGETMANTPHZ128rmbik:
19204 case VGETMANTPHZ128rmbikz:
19205 case VGETMANTPHZ128rmi:
19206 case VGETMANTPHZ128rmik:
19207 case VGETMANTPHZ128rmikz:
19208 case VGETMANTPHZ128rri:
19209 case VGETMANTPHZ128rrik:
19210 case VGETMANTPHZ128rrikz:
19211 case VGETMANTPHZ256rmbi:
19212 case VGETMANTPHZ256rmbik:
19213 case VGETMANTPHZ256rmbikz:
19214 case VGETMANTPHZ256rmi:
19215 case VGETMANTPHZ256rmik:
19216 case VGETMANTPHZ256rmikz:
19217 case VGETMANTPHZ256rri:
19218 case VGETMANTPHZ256rrik:
19219 case VGETMANTPHZ256rrikz:
19220 case VGETMANTPHZrmbi:
19221 case VGETMANTPHZrmbik:
19222 case VGETMANTPHZrmbikz:
19223 case VGETMANTPHZrmi:
19224 case VGETMANTPHZrmik:
19225 case VGETMANTPHZrmikz:
19226 case VGETMANTPHZrri:
19227 case VGETMANTPHZrrib:
19228 case VGETMANTPHZrribk:
19229 case VGETMANTPHZrribkz:
19230 case VGETMANTPHZrrik:
19231 case VGETMANTPHZrrikz:
19232 return true;
19233 }
19234 return false;
19235}
19236
19237bool isPUNPCKLDQ(unsigned Opcode) {
19238 switch (Opcode) {
19239 case MMX_PUNPCKLDQrm:
19240 case MMX_PUNPCKLDQrr:
19241 case PUNPCKLDQrm:
19242 case PUNPCKLDQrr:
19243 return true;
19244 }
19245 return false;
19246}
19247
19248bool isPADDD(unsigned Opcode) {
19249 switch (Opcode) {
19250 case MMX_PADDDrm:
19251 case MMX_PADDDrr:
19252 case PADDDrm:
19253 case PADDDrr:
19254 return true;
19255 }
19256 return false;
19257}
19258
19259bool isVPSLLD(unsigned Opcode) {
19260 switch (Opcode) {
19261 case VPSLLDYri:
19262 case VPSLLDYrm:
19263 case VPSLLDYrr:
19264 case VPSLLDZ128mbi:
19265 case VPSLLDZ128mbik:
19266 case VPSLLDZ128mbikz:
19267 case VPSLLDZ128mi:
19268 case VPSLLDZ128mik:
19269 case VPSLLDZ128mikz:
19270 case VPSLLDZ128ri:
19271 case VPSLLDZ128rik:
19272 case VPSLLDZ128rikz:
19273 case VPSLLDZ128rm:
19274 case VPSLLDZ128rmk:
19275 case VPSLLDZ128rmkz:
19276 case VPSLLDZ128rr:
19277 case VPSLLDZ128rrk:
19278 case VPSLLDZ128rrkz:
19279 case VPSLLDZ256mbi:
19280 case VPSLLDZ256mbik:
19281 case VPSLLDZ256mbikz:
19282 case VPSLLDZ256mi:
19283 case VPSLLDZ256mik:
19284 case VPSLLDZ256mikz:
19285 case VPSLLDZ256ri:
19286 case VPSLLDZ256rik:
19287 case VPSLLDZ256rikz:
19288 case VPSLLDZ256rm:
19289 case VPSLLDZ256rmk:
19290 case VPSLLDZ256rmkz:
19291 case VPSLLDZ256rr:
19292 case VPSLLDZ256rrk:
19293 case VPSLLDZ256rrkz:
19294 case VPSLLDZmbi:
19295 case VPSLLDZmbik:
19296 case VPSLLDZmbikz:
19297 case VPSLLDZmi:
19298 case VPSLLDZmik:
19299 case VPSLLDZmikz:
19300 case VPSLLDZri:
19301 case VPSLLDZrik:
19302 case VPSLLDZrikz:
19303 case VPSLLDZrm:
19304 case VPSLLDZrmk:
19305 case VPSLLDZrmkz:
19306 case VPSLLDZrr:
19307 case VPSLLDZrrk:
19308 case VPSLLDZrrkz:
19309 case VPSLLDri:
19310 case VPSLLDrm:
19311 case VPSLLDrr:
19312 return true;
19313 }
19314 return false;
19315}
19316
19317bool isPFCMPGE(unsigned Opcode) {
19318 switch (Opcode) {
19319 case PFCMPGErm:
19320 case PFCMPGErr:
19321 return true;
19322 }
19323 return false;
19324}
19325
19326bool isVGETMANTBF16(unsigned Opcode) {
19327 switch (Opcode) {
19328 case VGETMANTBF16Z128rmbi:
19329 case VGETMANTBF16Z128rmbik:
19330 case VGETMANTBF16Z128rmbikz:
19331 case VGETMANTBF16Z128rmi:
19332 case VGETMANTBF16Z128rmik:
19333 case VGETMANTBF16Z128rmikz:
19334 case VGETMANTBF16Z128rri:
19335 case VGETMANTBF16Z128rrik:
19336 case VGETMANTBF16Z128rrikz:
19337 case VGETMANTBF16Z256rmbi:
19338 case VGETMANTBF16Z256rmbik:
19339 case VGETMANTBF16Z256rmbikz:
19340 case VGETMANTBF16Z256rmi:
19341 case VGETMANTBF16Z256rmik:
19342 case VGETMANTBF16Z256rmikz:
19343 case VGETMANTBF16Z256rri:
19344 case VGETMANTBF16Z256rrik:
19345 case VGETMANTBF16Z256rrikz:
19346 case VGETMANTBF16Zrmbi:
19347 case VGETMANTBF16Zrmbik:
19348 case VGETMANTBF16Zrmbikz:
19349 case VGETMANTBF16Zrmi:
19350 case VGETMANTBF16Zrmik:
19351 case VGETMANTBF16Zrmikz:
19352 case VGETMANTBF16Zrri:
19353 case VGETMANTBF16Zrrik:
19354 case VGETMANTBF16Zrrikz:
19355 return true;
19356 }
19357 return false;
19358}
19359
19360bool isVSUBBF16(unsigned Opcode) {
19361 switch (Opcode) {
19362 case VSUBBF16Z128rm:
19363 case VSUBBF16Z128rmb:
19364 case VSUBBF16Z128rmbk:
19365 case VSUBBF16Z128rmbkz:
19366 case VSUBBF16Z128rmk:
19367 case VSUBBF16Z128rmkz:
19368 case VSUBBF16Z128rr:
19369 case VSUBBF16Z128rrk:
19370 case VSUBBF16Z128rrkz:
19371 case VSUBBF16Z256rm:
19372 case VSUBBF16Z256rmb:
19373 case VSUBBF16Z256rmbk:
19374 case VSUBBF16Z256rmbkz:
19375 case VSUBBF16Z256rmk:
19376 case VSUBBF16Z256rmkz:
19377 case VSUBBF16Z256rr:
19378 case VSUBBF16Z256rrk:
19379 case VSUBBF16Z256rrkz:
19380 case VSUBBF16Zrm:
19381 case VSUBBF16Zrmb:
19382 case VSUBBF16Zrmbk:
19383 case VSUBBF16Zrmbkz:
19384 case VSUBBF16Zrmk:
19385 case VSUBBF16Zrmkz:
19386 case VSUBBF16Zrr:
19387 case VSUBBF16Zrrk:
19388 case VSUBBF16Zrrkz:
19389 return true;
19390 }
19391 return false;
19392}
19393
19394bool isVPMOVM2D(unsigned Opcode) {
19395 switch (Opcode) {
19396 case VPMOVM2DZ128rk:
19397 case VPMOVM2DZ256rk:
19398 case VPMOVM2DZrk:
19399 return true;
19400 }
19401 return false;
19402}
19403
19404bool isVCVTTSS2USIS(unsigned Opcode) {
19405 switch (Opcode) {
19406 case VCVTTSS2USI64Srm_Int:
19407 case VCVTTSS2USI64Srr_Int:
19408 case VCVTTSS2USI64Srrb_Int:
19409 case VCVTTSS2USISrm_Int:
19410 case VCVTTSS2USISrr_Int:
19411 case VCVTTSS2USISrrb_Int:
19412 return true;
19413 }
19414 return false;
19415}
19416
19417bool isVHSUBPS(unsigned Opcode) {
19418 switch (Opcode) {
19419 case VHSUBPSYrm:
19420 case VHSUBPSYrr:
19421 case VHSUBPSrm:
19422 case VHSUBPSrr:
19423 return true;
19424 }
19425 return false;
19426}
19427
19428bool isENDBR32(unsigned Opcode) {
19429 return Opcode == ENDBR32;
19430}
19431
19432bool isMOVSXD(unsigned Opcode) {
19433 switch (Opcode) {
19434 case MOVSX16rm32:
19435 case MOVSX16rr32:
19436 case MOVSX32rm32:
19437 case MOVSX32rr32:
19438 case MOVSX64rm32:
19439 case MOVSX64rr32:
19440 return true;
19441 }
19442 return false;
19443}
19444
19445bool isPSIGND(unsigned Opcode) {
19446 switch (Opcode) {
19447 case MMX_PSIGNDrm:
19448 case MMX_PSIGNDrr:
19449 case PSIGNDrm:
19450 case PSIGNDrr:
19451 return true;
19452 }
19453 return false;
19454}
19455
19456bool isVPTEST(unsigned Opcode) {
19457 switch (Opcode) {
19458 case VPTESTYrm:
19459 case VPTESTYrr:
19460 case VPTESTrm:
19461 case VPTESTrr:
19462 return true;
19463 }
19464 return false;
19465}
19466
19467bool isVPDPWUSD(unsigned Opcode) {
19468 switch (Opcode) {
19469 case VPDPWUSDYrm:
19470 case VPDPWUSDYrr:
19471 case VPDPWUSDZ128rm:
19472 case VPDPWUSDZ128rmb:
19473 case VPDPWUSDZ128rmbk:
19474 case VPDPWUSDZ128rmbkz:
19475 case VPDPWUSDZ128rmk:
19476 case VPDPWUSDZ128rmkz:
19477 case VPDPWUSDZ128rr:
19478 case VPDPWUSDZ128rrk:
19479 case VPDPWUSDZ128rrkz:
19480 case VPDPWUSDZ256rm:
19481 case VPDPWUSDZ256rmb:
19482 case VPDPWUSDZ256rmbk:
19483 case VPDPWUSDZ256rmbkz:
19484 case VPDPWUSDZ256rmk:
19485 case VPDPWUSDZ256rmkz:
19486 case VPDPWUSDZ256rr:
19487 case VPDPWUSDZ256rrk:
19488 case VPDPWUSDZ256rrkz:
19489 case VPDPWUSDZrm:
19490 case VPDPWUSDZrmb:
19491 case VPDPWUSDZrmbk:
19492 case VPDPWUSDZrmbkz:
19493 case VPDPWUSDZrmk:
19494 case VPDPWUSDZrmkz:
19495 case VPDPWUSDZrr:
19496 case VPDPWUSDZrrk:
19497 case VPDPWUSDZrrkz:
19498 case VPDPWUSDrm:
19499 case VPDPWUSDrr:
19500 return true;
19501 }
19502 return false;
19503}
19504
19505bool isHSUBPD(unsigned Opcode) {
19506 switch (Opcode) {
19507 case HSUBPDrm:
19508 case HSUBPDrr:
19509 return true;
19510 }
19511 return false;
19512}
19513
19514bool isADCX(unsigned Opcode) {
19515 switch (Opcode) {
19516 case ADCX32rm:
19517 case ADCX32rm_EVEX:
19518 case ADCX32rm_ND:
19519 case ADCX32rr:
19520 case ADCX32rr_EVEX:
19521 case ADCX32rr_ND:
19522 case ADCX64rm:
19523 case ADCX64rm_EVEX:
19524 case ADCX64rm_ND:
19525 case ADCX64rr:
19526 case ADCX64rr_EVEX:
19527 case ADCX64rr_ND:
19528 return true;
19529 }
19530 return false;
19531}
19532
19533bool isCVTTPD2PI(unsigned Opcode) {
19534 switch (Opcode) {
19535 case MMX_CVTTPD2PIrm:
19536 case MMX_CVTTPD2PIrr:
19537 return true;
19538 }
19539 return false;
19540}
19541
19542bool isPDEP(unsigned Opcode) {
19543 switch (Opcode) {
19544 case PDEP32rm:
19545 case PDEP32rm_EVEX:
19546 case PDEP32rr:
19547 case PDEP32rr_EVEX:
19548 case PDEP64rm:
19549 case PDEP64rm_EVEX:
19550 case PDEP64rr:
19551 case PDEP64rr_EVEX:
19552 return true;
19553 }
19554 return false;
19555}
19556
19557bool isTDPBUSD(unsigned Opcode) {
19558 return Opcode == TDPBUSD;
19559}
19560
19561bool isVCVTBIASPH2HF8S(unsigned Opcode) {
19562 switch (Opcode) {
19563 case VCVTBIASPH2HF8SZ128rm:
19564 case VCVTBIASPH2HF8SZ128rmb:
19565 case VCVTBIASPH2HF8SZ128rmbk:
19566 case VCVTBIASPH2HF8SZ128rmbkz:
19567 case VCVTBIASPH2HF8SZ128rmk:
19568 case VCVTBIASPH2HF8SZ128rmkz:
19569 case VCVTBIASPH2HF8SZ128rr:
19570 case VCVTBIASPH2HF8SZ128rrk:
19571 case VCVTBIASPH2HF8SZ128rrkz:
19572 case VCVTBIASPH2HF8SZ256rm:
19573 case VCVTBIASPH2HF8SZ256rmb:
19574 case VCVTBIASPH2HF8SZ256rmbk:
19575 case VCVTBIASPH2HF8SZ256rmbkz:
19576 case VCVTBIASPH2HF8SZ256rmk:
19577 case VCVTBIASPH2HF8SZ256rmkz:
19578 case VCVTBIASPH2HF8SZ256rr:
19579 case VCVTBIASPH2HF8SZ256rrk:
19580 case VCVTBIASPH2HF8SZ256rrkz:
19581 case VCVTBIASPH2HF8SZrm:
19582 case VCVTBIASPH2HF8SZrmb:
19583 case VCVTBIASPH2HF8SZrmbk:
19584 case VCVTBIASPH2HF8SZrmbkz:
19585 case VCVTBIASPH2HF8SZrmk:
19586 case VCVTBIASPH2HF8SZrmkz:
19587 case VCVTBIASPH2HF8SZrr:
19588 case VCVTBIASPH2HF8SZrrk:
19589 case VCVTBIASPH2HF8SZrrkz:
19590 return true;
19591 }
19592 return false;
19593}
19594
19595bool isVBROADCASTI32X4(unsigned Opcode) {
19596 switch (Opcode) {
19597 case VBROADCASTI32X4Z256rm:
19598 case VBROADCASTI32X4Z256rmk:
19599 case VBROADCASTI32X4Z256rmkz:
19600 case VBROADCASTI32X4Zrm:
19601 case VBROADCASTI32X4Zrmk:
19602 case VBROADCASTI32X4Zrmkz:
19603 return true;
19604 }
19605 return false;
19606}
19607
19608bool isVCVTPH2UDQ(unsigned Opcode) {
19609 switch (Opcode) {
19610 case VCVTPH2UDQZ128rm:
19611 case VCVTPH2UDQZ128rmb:
19612 case VCVTPH2UDQZ128rmbk:
19613 case VCVTPH2UDQZ128rmbkz:
19614 case VCVTPH2UDQZ128rmk:
19615 case VCVTPH2UDQZ128rmkz:
19616 case VCVTPH2UDQZ128rr:
19617 case VCVTPH2UDQZ128rrk:
19618 case VCVTPH2UDQZ128rrkz:
19619 case VCVTPH2UDQZ256rm:
19620 case VCVTPH2UDQZ256rmb:
19621 case VCVTPH2UDQZ256rmbk:
19622 case VCVTPH2UDQZ256rmbkz:
19623 case VCVTPH2UDQZ256rmk:
19624 case VCVTPH2UDQZ256rmkz:
19625 case VCVTPH2UDQZ256rr:
19626 case VCVTPH2UDQZ256rrk:
19627 case VCVTPH2UDQZ256rrkz:
19628 case VCVTPH2UDQZrm:
19629 case VCVTPH2UDQZrmb:
19630 case VCVTPH2UDQZrmbk:
19631 case VCVTPH2UDQZrmbkz:
19632 case VCVTPH2UDQZrmk:
19633 case VCVTPH2UDQZrmkz:
19634 case VCVTPH2UDQZrr:
19635 case VCVTPH2UDQZrrb:
19636 case VCVTPH2UDQZrrbk:
19637 case VCVTPH2UDQZrrbkz:
19638 case VCVTPH2UDQZrrk:
19639 case VCVTPH2UDQZrrkz:
19640 return true;
19641 }
19642 return false;
19643}
19644
19645bool isVPHADDW(unsigned Opcode) {
19646 switch (Opcode) {
19647 case VPHADDWYrm:
19648 case VPHADDWYrr:
19649 case VPHADDWrm:
19650 case VPHADDWrr:
19651 return true;
19652 }
19653 return false;
19654}
19655
19656bool isFLDL2E(unsigned Opcode) {
19657 return Opcode == FLDL2E;
19658}
19659
19660bool isCLZERO(unsigned Opcode) {
19661 switch (Opcode) {
19662 case CLZERO32r:
19663 case CLZERO64r:
19664 return true;
19665 }
19666 return false;
19667}
19668
19669bool isPBLENDW(unsigned Opcode) {
19670 switch (Opcode) {
19671 case PBLENDWrmi:
19672 case PBLENDWrri:
19673 return true;
19674 }
19675 return false;
19676}
19677
19678bool isVCVTBF162IUBS(unsigned Opcode) {
19679 switch (Opcode) {
19680 case VCVTBF162IUBSZ128rm:
19681 case VCVTBF162IUBSZ128rmb:
19682 case VCVTBF162IUBSZ128rmbk:
19683 case VCVTBF162IUBSZ128rmbkz:
19684 case VCVTBF162IUBSZ128rmk:
19685 case VCVTBF162IUBSZ128rmkz:
19686 case VCVTBF162IUBSZ128rr:
19687 case VCVTBF162IUBSZ128rrk:
19688 case VCVTBF162IUBSZ128rrkz:
19689 case VCVTBF162IUBSZ256rm:
19690 case VCVTBF162IUBSZ256rmb:
19691 case VCVTBF162IUBSZ256rmbk:
19692 case VCVTBF162IUBSZ256rmbkz:
19693 case VCVTBF162IUBSZ256rmk:
19694 case VCVTBF162IUBSZ256rmkz:
19695 case VCVTBF162IUBSZ256rr:
19696 case VCVTBF162IUBSZ256rrk:
19697 case VCVTBF162IUBSZ256rrkz:
19698 case VCVTBF162IUBSZrm:
19699 case VCVTBF162IUBSZrmb:
19700 case VCVTBF162IUBSZrmbk:
19701 case VCVTBF162IUBSZrmbkz:
19702 case VCVTBF162IUBSZrmk:
19703 case VCVTBF162IUBSZrmkz:
19704 case VCVTBF162IUBSZrr:
19705 case VCVTBF162IUBSZrrk:
19706 case VCVTBF162IUBSZrrkz:
19707 return true;
19708 }
19709 return false;
19710}
19711
19712bool isVCVTSH2USI(unsigned Opcode) {
19713 switch (Opcode) {
19714 case VCVTSH2USI64Zrm_Int:
19715 case VCVTSH2USI64Zrr_Int:
19716 case VCVTSH2USI64Zrrb_Int:
19717 case VCVTSH2USIZrm_Int:
19718 case VCVTSH2USIZrr_Int:
19719 case VCVTSH2USIZrrb_Int:
19720 return true;
19721 }
19722 return false;
19723}
19724
19725bool isVANDPD(unsigned Opcode) {
19726 switch (Opcode) {
19727 case VANDPDYrm:
19728 case VANDPDYrr:
19729 case VANDPDZ128rm:
19730 case VANDPDZ128rmb:
19731 case VANDPDZ128rmbk:
19732 case VANDPDZ128rmbkz:
19733 case VANDPDZ128rmk:
19734 case VANDPDZ128rmkz:
19735 case VANDPDZ128rr:
19736 case VANDPDZ128rrk:
19737 case VANDPDZ128rrkz:
19738 case VANDPDZ256rm:
19739 case VANDPDZ256rmb:
19740 case VANDPDZ256rmbk:
19741 case VANDPDZ256rmbkz:
19742 case VANDPDZ256rmk:
19743 case VANDPDZ256rmkz:
19744 case VANDPDZ256rr:
19745 case VANDPDZ256rrk:
19746 case VANDPDZ256rrkz:
19747 case VANDPDZrm:
19748 case VANDPDZrmb:
19749 case VANDPDZrmbk:
19750 case VANDPDZrmbkz:
19751 case VANDPDZrmk:
19752 case VANDPDZrmkz:
19753 case VANDPDZrr:
19754 case VANDPDZrrk:
19755 case VANDPDZrrkz:
19756 case VANDPDrm:
19757 case VANDPDrr:
19758 return true;
19759 }
19760 return false;
19761}
19762
19763bool isBEXTR(unsigned Opcode) {
19764 switch (Opcode) {
19765 case BEXTR32rm:
19766 case BEXTR32rm_EVEX:
19767 case BEXTR32rm_NF:
19768 case BEXTR32rr:
19769 case BEXTR32rr_EVEX:
19770 case BEXTR32rr_NF:
19771 case BEXTR64rm:
19772 case BEXTR64rm_EVEX:
19773 case BEXTR64rm_NF:
19774 case BEXTR64rr:
19775 case BEXTR64rr_EVEX:
19776 case BEXTR64rr_NF:
19777 case BEXTRI32mi:
19778 case BEXTRI32ri:
19779 case BEXTRI64mi:
19780 case BEXTRI64ri:
19781 return true;
19782 }
19783 return false;
19784}
19785
19786bool isSTD(unsigned Opcode) {
19787 return Opcode == STD;
19788}
19789
19790bool isVAESKEYGENASSIST(unsigned Opcode) {
19791 switch (Opcode) {
19792 case VAESKEYGENASSISTrmi:
19793 case VAESKEYGENASSISTrri:
19794 return true;
19795 }
19796 return false;
19797}
19798
19799bool isCMPSD(unsigned Opcode) {
19800 switch (Opcode) {
19801 case CMPSDrmi_Int:
19802 case CMPSDrri_Int:
19803 case CMPSL:
19804 return true;
19805 }
19806 return false;
19807}
19808
19809bool isMOVSS(unsigned Opcode) {
19810 switch (Opcode) {
19811 case MOVSSmr:
19812 case MOVSSrm:
19813 case MOVSSrr:
19814 case MOVSSrr_REV:
19815 return true;
19816 }
19817 return false;
19818}
19819
19820bool isVCVTUQQ2PD(unsigned Opcode) {
19821 switch (Opcode) {
19822 case VCVTUQQ2PDZ128rm:
19823 case VCVTUQQ2PDZ128rmb:
19824 case VCVTUQQ2PDZ128rmbk:
19825 case VCVTUQQ2PDZ128rmbkz:
19826 case VCVTUQQ2PDZ128rmk:
19827 case VCVTUQQ2PDZ128rmkz:
19828 case VCVTUQQ2PDZ128rr:
19829 case VCVTUQQ2PDZ128rrk:
19830 case VCVTUQQ2PDZ128rrkz:
19831 case VCVTUQQ2PDZ256rm:
19832 case VCVTUQQ2PDZ256rmb:
19833 case VCVTUQQ2PDZ256rmbk:
19834 case VCVTUQQ2PDZ256rmbkz:
19835 case VCVTUQQ2PDZ256rmk:
19836 case VCVTUQQ2PDZ256rmkz:
19837 case VCVTUQQ2PDZ256rr:
19838 case VCVTUQQ2PDZ256rrk:
19839 case VCVTUQQ2PDZ256rrkz:
19840 case VCVTUQQ2PDZrm:
19841 case VCVTUQQ2PDZrmb:
19842 case VCVTUQQ2PDZrmbk:
19843 case VCVTUQQ2PDZrmbkz:
19844 case VCVTUQQ2PDZrmk:
19845 case VCVTUQQ2PDZrmkz:
19846 case VCVTUQQ2PDZrr:
19847 case VCVTUQQ2PDZrrb:
19848 case VCVTUQQ2PDZrrbk:
19849 case VCVTUQQ2PDZrrbkz:
19850 case VCVTUQQ2PDZrrk:
19851 case VCVTUQQ2PDZrrkz:
19852 return true;
19853 }
19854 return false;
19855}
19856
19857bool isVEXTRACTI32X4(unsigned Opcode) {
19858 switch (Opcode) {
19859 case VEXTRACTI32X4Z256mri:
19860 case VEXTRACTI32X4Z256mrik:
19861 case VEXTRACTI32X4Z256rri:
19862 case VEXTRACTI32X4Z256rrik:
19863 case VEXTRACTI32X4Z256rrikz:
19864 case VEXTRACTI32X4Zmri:
19865 case VEXTRACTI32X4Zmrik:
19866 case VEXTRACTI32X4Zrri:
19867 case VEXTRACTI32X4Zrrik:
19868 case VEXTRACTI32X4Zrrikz:
19869 return true;
19870 }
19871 return false;
19872}
19873
19874bool isFLDCW(unsigned Opcode) {
19875 return Opcode == FLDCW16m;
19876}
19877
19878bool isINSW(unsigned Opcode) {
19879 return Opcode == INSW;
19880}
19881
19882bool isRDPID(unsigned Opcode) {
19883 switch (Opcode) {
19884 case RDPID32:
19885 case RDPID64:
19886 return true;
19887 }
19888 return false;
19889}
19890
19891bool isVUCOMXSS(unsigned Opcode) {
19892 switch (Opcode) {
19893 case VUCOMXSSZrm_Int:
19894 case VUCOMXSSZrr_Int:
19895 case VUCOMXSSZrrb_Int:
19896 return true;
19897 }
19898 return false;
19899}
19900
19901bool isKANDQ(unsigned Opcode) {
19902 return Opcode == KANDQkk;
19903}
19904
19905bool isV4FMADDPS(unsigned Opcode) {
19906 switch (Opcode) {
19907 case V4FMADDPSrm:
19908 case V4FMADDPSrmk:
19909 case V4FMADDPSrmkz:
19910 return true;
19911 }
19912 return false;
19913}
19914
19915bool isPMOVZXWQ(unsigned Opcode) {
19916 switch (Opcode) {
19917 case PMOVZXWQrm:
19918 case PMOVZXWQrr:
19919 return true;
19920 }
19921 return false;
19922}
19923
19924bool isVFPCLASSSD(unsigned Opcode) {
19925 switch (Opcode) {
19926 case VFPCLASSSDZmi:
19927 case VFPCLASSSDZmik:
19928 case VFPCLASSSDZri:
19929 case VFPCLASSSDZrik:
19930 return true;
19931 }
19932 return false;
19933}
19934
19935bool isBLENDPS(unsigned Opcode) {
19936 switch (Opcode) {
19937 case BLENDPSrmi:
19938 case BLENDPSrri:
19939 return true;
19940 }
19941 return false;
19942}
19943
19944bool isVPACKSSDW(unsigned Opcode) {
19945 switch (Opcode) {
19946 case VPACKSSDWYrm:
19947 case VPACKSSDWYrr:
19948 case VPACKSSDWZ128rm:
19949 case VPACKSSDWZ128rmb:
19950 case VPACKSSDWZ128rmbk:
19951 case VPACKSSDWZ128rmbkz:
19952 case VPACKSSDWZ128rmk:
19953 case VPACKSSDWZ128rmkz:
19954 case VPACKSSDWZ128rr:
19955 case VPACKSSDWZ128rrk:
19956 case VPACKSSDWZ128rrkz:
19957 case VPACKSSDWZ256rm:
19958 case VPACKSSDWZ256rmb:
19959 case VPACKSSDWZ256rmbk:
19960 case VPACKSSDWZ256rmbkz:
19961 case VPACKSSDWZ256rmk:
19962 case VPACKSSDWZ256rmkz:
19963 case VPACKSSDWZ256rr:
19964 case VPACKSSDWZ256rrk:
19965 case VPACKSSDWZ256rrkz:
19966 case VPACKSSDWZrm:
19967 case VPACKSSDWZrmb:
19968 case VPACKSSDWZrmbk:
19969 case VPACKSSDWZrmbkz:
19970 case VPACKSSDWZrmk:
19971 case VPACKSSDWZrmkz:
19972 case VPACKSSDWZrr:
19973 case VPACKSSDWZrrk:
19974 case VPACKSSDWZrrkz:
19975 case VPACKSSDWrm:
19976 case VPACKSSDWrr:
19977 return true;
19978 }
19979 return false;
19980}
19981
19982bool isVPHSUBBW(unsigned Opcode) {
19983 switch (Opcode) {
19984 case VPHSUBBWrm:
19985 case VPHSUBBWrr:
19986 return true;
19987 }
19988 return false;
19989}
19990
19991bool isVPINSRW(unsigned Opcode) {
19992 switch (Opcode) {
19993 case VPINSRWZrmi:
19994 case VPINSRWZrri:
19995 case VPINSRWrmi:
19996 case VPINSRWrri:
19997 return true;
19998 }
19999 return false;
20000}
20001
20002bool isVMINMAXBF16(unsigned Opcode) {
20003 switch (Opcode) {
20004 case VMINMAXBF16Z128rmbi:
20005 case VMINMAXBF16Z128rmbik:
20006 case VMINMAXBF16Z128rmbikz:
20007 case VMINMAXBF16Z128rmi:
20008 case VMINMAXBF16Z128rmik:
20009 case VMINMAXBF16Z128rmikz:
20010 case VMINMAXBF16Z128rri:
20011 case VMINMAXBF16Z128rrik:
20012 case VMINMAXBF16Z128rrikz:
20013 case VMINMAXBF16Z256rmbi:
20014 case VMINMAXBF16Z256rmbik:
20015 case VMINMAXBF16Z256rmbikz:
20016 case VMINMAXBF16Z256rmi:
20017 case VMINMAXBF16Z256rmik:
20018 case VMINMAXBF16Z256rmikz:
20019 case VMINMAXBF16Z256rri:
20020 case VMINMAXBF16Z256rrik:
20021 case VMINMAXBF16Z256rrikz:
20022 case VMINMAXBF16Zrmbi:
20023 case VMINMAXBF16Zrmbik:
20024 case VMINMAXBF16Zrmbikz:
20025 case VMINMAXBF16Zrmi:
20026 case VMINMAXBF16Zrmik:
20027 case VMINMAXBF16Zrmikz:
20028 case VMINMAXBF16Zrri:
20029 case VMINMAXBF16Zrrik:
20030 case VMINMAXBF16Zrrikz:
20031 return true;
20032 }
20033 return false;
20034}
20035
20036bool isVSHUFF64X2(unsigned Opcode) {
20037 switch (Opcode) {
20038 case VSHUFF64X2Z256rmbi:
20039 case VSHUFF64X2Z256rmbik:
20040 case VSHUFF64X2Z256rmbikz:
20041 case VSHUFF64X2Z256rmi:
20042 case VSHUFF64X2Z256rmik:
20043 case VSHUFF64X2Z256rmikz:
20044 case VSHUFF64X2Z256rri:
20045 case VSHUFF64X2Z256rrik:
20046 case VSHUFF64X2Z256rrikz:
20047 case VSHUFF64X2Zrmbi:
20048 case VSHUFF64X2Zrmbik:
20049 case VSHUFF64X2Zrmbikz:
20050 case VSHUFF64X2Zrmi:
20051 case VSHUFF64X2Zrmik:
20052 case VSHUFF64X2Zrmikz:
20053 case VSHUFF64X2Zrri:
20054 case VSHUFF64X2Zrrik:
20055 case VSHUFF64X2Zrrikz:
20056 return true;
20057 }
20058 return false;
20059}
20060
20061bool isVPACKUSWB(unsigned Opcode) {
20062 switch (Opcode) {
20063 case VPACKUSWBYrm:
20064 case VPACKUSWBYrr:
20065 case VPACKUSWBZ128rm:
20066 case VPACKUSWBZ128rmk:
20067 case VPACKUSWBZ128rmkz:
20068 case VPACKUSWBZ128rr:
20069 case VPACKUSWBZ128rrk:
20070 case VPACKUSWBZ128rrkz:
20071 case VPACKUSWBZ256rm:
20072 case VPACKUSWBZ256rmk:
20073 case VPACKUSWBZ256rmkz:
20074 case VPACKUSWBZ256rr:
20075 case VPACKUSWBZ256rrk:
20076 case VPACKUSWBZ256rrkz:
20077 case VPACKUSWBZrm:
20078 case VPACKUSWBZrmk:
20079 case VPACKUSWBZrmkz:
20080 case VPACKUSWBZrr:
20081 case VPACKUSWBZrrk:
20082 case VPACKUSWBZrrkz:
20083 case VPACKUSWBrm:
20084 case VPACKUSWBrr:
20085 return true;
20086 }
20087 return false;
20088}
20089
20090bool isVRSQRT28SS(unsigned Opcode) {
20091 switch (Opcode) {
20092 case VRSQRT28SSZm:
20093 case VRSQRT28SSZmk:
20094 case VRSQRT28SSZmkz:
20095 case VRSQRT28SSZr:
20096 case VRSQRT28SSZrb:
20097 case VRSQRT28SSZrbk:
20098 case VRSQRT28SSZrbkz:
20099 case VRSQRT28SSZrk:
20100 case VRSQRT28SSZrkz:
20101 return true;
20102 }
20103 return false;
20104}
20105
20106bool isGETSEC(unsigned Opcode) {
20107 return Opcode == GETSEC;
20108}
20109
20110bool isFXAM(unsigned Opcode) {
20111 return Opcode == XAM_F;
20112}
20113
20114bool isVEXTRACTF64X4(unsigned Opcode) {
20115 switch (Opcode) {
20116 case VEXTRACTF64X4Zmri:
20117 case VEXTRACTF64X4Zmrik:
20118 case VEXTRACTF64X4Zrri:
20119 case VEXTRACTF64X4Zrrik:
20120 case VEXTRACTF64X4Zrrikz:
20121 return true;
20122 }
20123 return false;
20124}
20125
20126bool isBLSR(unsigned Opcode) {
20127 switch (Opcode) {
20128 case BLSR32rm:
20129 case BLSR32rm_EVEX:
20130 case BLSR32rm_NF:
20131 case BLSR32rr:
20132 case BLSR32rr_EVEX:
20133 case BLSR32rr_NF:
20134 case BLSR64rm:
20135 case BLSR64rm_EVEX:
20136 case BLSR64rm_NF:
20137 case BLSR64rr:
20138 case BLSR64rr_EVEX:
20139 case BLSR64rr_NF:
20140 return true;
20141 }
20142 return false;
20143}
20144
20145bool isFILD(unsigned Opcode) {
20146 switch (Opcode) {
20147 case ILD_F16m:
20148 case ILD_F32m:
20149 case ILD_F64m:
20150 return true;
20151 }
20152 return false;
20153}
20154
20155bool isRETFQ(unsigned Opcode) {
20156 switch (Opcode) {
20157 case LRET64:
20158 case LRETI64:
20159 return true;
20160 }
20161 return false;
20162}
20163
20164bool isVADDSS(unsigned Opcode) {
20165 switch (Opcode) {
20166 case VADDSSZrm_Int:
20167 case VADDSSZrmk_Int:
20168 case VADDSSZrmkz_Int:
20169 case VADDSSZrr_Int:
20170 case VADDSSZrrb_Int:
20171 case VADDSSZrrbk_Int:
20172 case VADDSSZrrbkz_Int:
20173 case VADDSSZrrk_Int:
20174 case VADDSSZrrkz_Int:
20175 case VADDSSrm_Int:
20176 case VADDSSrr_Int:
20177 return true;
20178 }
20179 return false;
20180}
20181
20182bool isCOMISS(unsigned Opcode) {
20183 switch (Opcode) {
20184 case COMISSrm:
20185 case COMISSrr:
20186 return true;
20187 }
20188 return false;
20189}
20190
20191bool isCLI(unsigned Opcode) {
20192 return Opcode == CLI;
20193}
20194
20195bool isVERW(unsigned Opcode) {
20196 switch (Opcode) {
20197 case VERWm:
20198 case VERWr:
20199 return true;
20200 }
20201 return false;
20202}
20203
20204bool isBTC(unsigned Opcode) {
20205 switch (Opcode) {
20206 case BTC16mi8:
20207 case BTC16mr:
20208 case BTC16ri8:
20209 case BTC16rr:
20210 case BTC32mi8:
20211 case BTC32mr:
20212 case BTC32ri8:
20213 case BTC32rr:
20214 case BTC64mi8:
20215 case BTC64mr:
20216 case BTC64ri8:
20217 case BTC64rr:
20218 return true;
20219 }
20220 return false;
20221}
20222
20223bool isVPHADDUBQ(unsigned Opcode) {
20224 switch (Opcode) {
20225 case VPHADDUBQrm:
20226 case VPHADDUBQrr:
20227 return true;
20228 }
20229 return false;
20230}
20231
20232bool isVPORQ(unsigned Opcode) {
20233 switch (Opcode) {
20234 case VPORQZ128rm:
20235 case VPORQZ128rmb:
20236 case VPORQZ128rmbk:
20237 case VPORQZ128rmbkz:
20238 case VPORQZ128rmk:
20239 case VPORQZ128rmkz:
20240 case VPORQZ128rr:
20241 case VPORQZ128rrk:
20242 case VPORQZ128rrkz:
20243 case VPORQZ256rm:
20244 case VPORQZ256rmb:
20245 case VPORQZ256rmbk:
20246 case VPORQZ256rmbkz:
20247 case VPORQZ256rmk:
20248 case VPORQZ256rmkz:
20249 case VPORQZ256rr:
20250 case VPORQZ256rrk:
20251 case VPORQZ256rrkz:
20252 case VPORQZrm:
20253 case VPORQZrmb:
20254 case VPORQZrmbk:
20255 case VPORQZrmbkz:
20256 case VPORQZrmk:
20257 case VPORQZrmkz:
20258 case VPORQZrr:
20259 case VPORQZrrk:
20260 case VPORQZrrkz:
20261 return true;
20262 }
20263 return false;
20264}
20265
20266bool isORPD(unsigned Opcode) {
20267 switch (Opcode) {
20268 case ORPDrm:
20269 case ORPDrr:
20270 return true;
20271 }
20272 return false;
20273}
20274
20275bool isVMOVSS(unsigned Opcode) {
20276 switch (Opcode) {
20277 case VMOVSSZmr:
20278 case VMOVSSZmrk:
20279 case VMOVSSZrm:
20280 case VMOVSSZrmk:
20281 case VMOVSSZrmkz:
20282 case VMOVSSZrr:
20283 case VMOVSSZrr_REV:
20284 case VMOVSSZrrk:
20285 case VMOVSSZrrk_REV:
20286 case VMOVSSZrrkz:
20287 case VMOVSSZrrkz_REV:
20288 case VMOVSSmr:
20289 case VMOVSSrm:
20290 case VMOVSSrr:
20291 case VMOVSSrr_REV:
20292 return true;
20293 }
20294 return false;
20295}
20296
20297bool isVPSUBD(unsigned Opcode) {
20298 switch (Opcode) {
20299 case VPSUBDYrm:
20300 case VPSUBDYrr:
20301 case VPSUBDZ128rm:
20302 case VPSUBDZ128rmb:
20303 case VPSUBDZ128rmbk:
20304 case VPSUBDZ128rmbkz:
20305 case VPSUBDZ128rmk:
20306 case VPSUBDZ128rmkz:
20307 case VPSUBDZ128rr:
20308 case VPSUBDZ128rrk:
20309 case VPSUBDZ128rrkz:
20310 case VPSUBDZ256rm:
20311 case VPSUBDZ256rmb:
20312 case VPSUBDZ256rmbk:
20313 case VPSUBDZ256rmbkz:
20314 case VPSUBDZ256rmk:
20315 case VPSUBDZ256rmkz:
20316 case VPSUBDZ256rr:
20317 case VPSUBDZ256rrk:
20318 case VPSUBDZ256rrkz:
20319 case VPSUBDZrm:
20320 case VPSUBDZrmb:
20321 case VPSUBDZrmbk:
20322 case VPSUBDZrmbkz:
20323 case VPSUBDZrmk:
20324 case VPSUBDZrmkz:
20325 case VPSUBDZrr:
20326 case VPSUBDZrrk:
20327 case VPSUBDZrrkz:
20328 case VPSUBDrm:
20329 case VPSUBDrr:
20330 return true;
20331 }
20332 return false;
20333}
20334
20335bool isVGATHERPF1QPD(unsigned Opcode) {
20336 return Opcode == VGATHERPF1QPDm;
20337}
20338
20339bool isENCODEKEY256(unsigned Opcode) {
20340 return Opcode == ENCODEKEY256;
20341}
20342
20343bool isGF2P8AFFINEINVQB(unsigned Opcode) {
20344 switch (Opcode) {
20345 case GF2P8AFFINEINVQBrmi:
20346 case GF2P8AFFINEINVQBrri:
20347 return true;
20348 }
20349 return false;
20350}
20351
20352bool isXRSTOR64(unsigned Opcode) {
20353 return Opcode == XRSTOR64;
20354}
20355
20356bool isKANDW(unsigned Opcode) {
20357 return Opcode == KANDWkk;
20358}
20359
20360bool isLODSQ(unsigned Opcode) {
20361 return Opcode == LODSQ;
20362}
20363
20364bool isVMOVRSW(unsigned Opcode) {
20365 switch (Opcode) {
20366 case VMOVRSWZ128m:
20367 case VMOVRSWZ128mk:
20368 case VMOVRSWZ128mkz:
20369 case VMOVRSWZ256m:
20370 case VMOVRSWZ256mk:
20371 case VMOVRSWZ256mkz:
20372 case VMOVRSWZm:
20373 case VMOVRSWZmk:
20374 case VMOVRSWZmkz:
20375 return true;
20376 }
20377 return false;
20378}
20379
20380bool isVSUBSH(unsigned Opcode) {
20381 switch (Opcode) {
20382 case VSUBSHZrm_Int:
20383 case VSUBSHZrmk_Int:
20384 case VSUBSHZrmkz_Int:
20385 case VSUBSHZrr_Int:
20386 case VSUBSHZrrb_Int:
20387 case VSUBSHZrrbk_Int:
20388 case VSUBSHZrrbkz_Int:
20389 case VSUBSHZrrk_Int:
20390 case VSUBSHZrrkz_Int:
20391 return true;
20392 }
20393 return false;
20394}
20395
20396bool isLSS(unsigned Opcode) {
20397 switch (Opcode) {
20398 case LSS16rm:
20399 case LSS32rm:
20400 case LSS64rm:
20401 return true;
20402 }
20403 return false;
20404}
20405
20406bool isPMOVSXBQ(unsigned Opcode) {
20407 switch (Opcode) {
20408 case PMOVSXBQrm:
20409 case PMOVSXBQrr:
20410 return true;
20411 }
20412 return false;
20413}
20414
20415bool isVCVTTSD2SIS(unsigned Opcode) {
20416 switch (Opcode) {
20417 case VCVTTSD2SI64Srm_Int:
20418 case VCVTTSD2SI64Srr_Int:
20419 case VCVTTSD2SI64Srrb_Int:
20420 case VCVTTSD2SISrm_Int:
20421 case VCVTTSD2SISrr_Int:
20422 case VCVTTSD2SISrrb_Int:
20423 return true;
20424 }
20425 return false;
20426}
20427
20428bool isVCMPSH(unsigned Opcode) {
20429 switch (Opcode) {
20430 case VCMPSHZrmi_Int:
20431 case VCMPSHZrmik_Int:
20432 case VCMPSHZrri_Int:
20433 case VCMPSHZrrib_Int:
20434 case VCMPSHZrribk_Int:
20435 case VCMPSHZrrik_Int:
20436 return true;
20437 }
20438 return false;
20439}
20440
20441bool isVFMADD132PS(unsigned Opcode) {
20442 switch (Opcode) {
20443 case VFMADD132PSYm:
20444 case VFMADD132PSYr:
20445 case VFMADD132PSZ128m:
20446 case VFMADD132PSZ128mb:
20447 case VFMADD132PSZ128mbk:
20448 case VFMADD132PSZ128mbkz:
20449 case VFMADD132PSZ128mk:
20450 case VFMADD132PSZ128mkz:
20451 case VFMADD132PSZ128r:
20452 case VFMADD132PSZ128rk:
20453 case VFMADD132PSZ128rkz:
20454 case VFMADD132PSZ256m:
20455 case VFMADD132PSZ256mb:
20456 case VFMADD132PSZ256mbk:
20457 case VFMADD132PSZ256mbkz:
20458 case VFMADD132PSZ256mk:
20459 case VFMADD132PSZ256mkz:
20460 case VFMADD132PSZ256r:
20461 case VFMADD132PSZ256rk:
20462 case VFMADD132PSZ256rkz:
20463 case VFMADD132PSZm:
20464 case VFMADD132PSZmb:
20465 case VFMADD132PSZmbk:
20466 case VFMADD132PSZmbkz:
20467 case VFMADD132PSZmk:
20468 case VFMADD132PSZmkz:
20469 case VFMADD132PSZr:
20470 case VFMADD132PSZrb:
20471 case VFMADD132PSZrbk:
20472 case VFMADD132PSZrbkz:
20473 case VFMADD132PSZrk:
20474 case VFMADD132PSZrkz:
20475 case VFMADD132PSm:
20476 case VFMADD132PSr:
20477 return true;
20478 }
20479 return false;
20480}
20481
20482bool isVPACKSSWB(unsigned Opcode) {
20483 switch (Opcode) {
20484 case VPACKSSWBYrm:
20485 case VPACKSSWBYrr:
20486 case VPACKSSWBZ128rm:
20487 case VPACKSSWBZ128rmk:
20488 case VPACKSSWBZ128rmkz:
20489 case VPACKSSWBZ128rr:
20490 case VPACKSSWBZ128rrk:
20491 case VPACKSSWBZ128rrkz:
20492 case VPACKSSWBZ256rm:
20493 case VPACKSSWBZ256rmk:
20494 case VPACKSSWBZ256rmkz:
20495 case VPACKSSWBZ256rr:
20496 case VPACKSSWBZ256rrk:
20497 case VPACKSSWBZ256rrkz:
20498 case VPACKSSWBZrm:
20499 case VPACKSSWBZrmk:
20500 case VPACKSSWBZrmkz:
20501 case VPACKSSWBZrr:
20502 case VPACKSSWBZrrk:
20503 case VPACKSSWBZrrkz:
20504 case VPACKSSWBrm:
20505 case VPACKSSWBrr:
20506 return true;
20507 }
20508 return false;
20509}
20510
20511bool isPCMPGTQ(unsigned Opcode) {
20512 switch (Opcode) {
20513 case PCMPGTQrm:
20514 case PCMPGTQrr:
20515 return true;
20516 }
20517 return false;
20518}
20519
20520bool isVFMADD132SH(unsigned Opcode) {
20521 switch (Opcode) {
20522 case VFMADD132SHZm_Int:
20523 case VFMADD132SHZmk_Int:
20524 case VFMADD132SHZmkz_Int:
20525 case VFMADD132SHZr_Int:
20526 case VFMADD132SHZrb_Int:
20527 case VFMADD132SHZrbk_Int:
20528 case VFMADD132SHZrbkz_Int:
20529 case VFMADD132SHZrk_Int:
20530 case VFMADD132SHZrkz_Int:
20531 return true;
20532 }
20533 return false;
20534}
20535
20536bool isVCVTUQQ2PH(unsigned Opcode) {
20537 switch (Opcode) {
20538 case VCVTUQQ2PHZ128rm:
20539 case VCVTUQQ2PHZ128rmb:
20540 case VCVTUQQ2PHZ128rmbk:
20541 case VCVTUQQ2PHZ128rmbkz:
20542 case VCVTUQQ2PHZ128rmk:
20543 case VCVTUQQ2PHZ128rmkz:
20544 case VCVTUQQ2PHZ128rr:
20545 case VCVTUQQ2PHZ128rrk:
20546 case VCVTUQQ2PHZ128rrkz:
20547 case VCVTUQQ2PHZ256rm:
20548 case VCVTUQQ2PHZ256rmb:
20549 case VCVTUQQ2PHZ256rmbk:
20550 case VCVTUQQ2PHZ256rmbkz:
20551 case VCVTUQQ2PHZ256rmk:
20552 case VCVTUQQ2PHZ256rmkz:
20553 case VCVTUQQ2PHZ256rr:
20554 case VCVTUQQ2PHZ256rrk:
20555 case VCVTUQQ2PHZ256rrkz:
20556 case VCVTUQQ2PHZrm:
20557 case VCVTUQQ2PHZrmb:
20558 case VCVTUQQ2PHZrmbk:
20559 case VCVTUQQ2PHZrmbkz:
20560 case VCVTUQQ2PHZrmk:
20561 case VCVTUQQ2PHZrmkz:
20562 case VCVTUQQ2PHZrr:
20563 case VCVTUQQ2PHZrrb:
20564 case VCVTUQQ2PHZrrbk:
20565 case VCVTUQQ2PHZrrbkz:
20566 case VCVTUQQ2PHZrrk:
20567 case VCVTUQQ2PHZrrkz:
20568 return true;
20569 }
20570 return false;
20571}
20572
20573bool isVCVTQQ2PS(unsigned Opcode) {
20574 switch (Opcode) {
20575 case VCVTQQ2PSZ128rm:
20576 case VCVTQQ2PSZ128rmb:
20577 case VCVTQQ2PSZ128rmbk:
20578 case VCVTQQ2PSZ128rmbkz:
20579 case VCVTQQ2PSZ128rmk:
20580 case VCVTQQ2PSZ128rmkz:
20581 case VCVTQQ2PSZ128rr:
20582 case VCVTQQ2PSZ128rrk:
20583 case VCVTQQ2PSZ128rrkz:
20584 case VCVTQQ2PSZ256rm:
20585 case VCVTQQ2PSZ256rmb:
20586 case VCVTQQ2PSZ256rmbk:
20587 case VCVTQQ2PSZ256rmbkz:
20588 case VCVTQQ2PSZ256rmk:
20589 case VCVTQQ2PSZ256rmkz:
20590 case VCVTQQ2PSZ256rr:
20591 case VCVTQQ2PSZ256rrk:
20592 case VCVTQQ2PSZ256rrkz:
20593 case VCVTQQ2PSZrm:
20594 case VCVTQQ2PSZrmb:
20595 case VCVTQQ2PSZrmbk:
20596 case VCVTQQ2PSZrmbkz:
20597 case VCVTQQ2PSZrmk:
20598 case VCVTQQ2PSZrmkz:
20599 case VCVTQQ2PSZrr:
20600 case VCVTQQ2PSZrrb:
20601 case VCVTQQ2PSZrrbk:
20602 case VCVTQQ2PSZrrbkz:
20603 case VCVTQQ2PSZrrk:
20604 case VCVTQQ2PSZrrkz:
20605 return true;
20606 }
20607 return false;
20608}
20609
20610bool isVCVTTSS2USI(unsigned Opcode) {
20611 switch (Opcode) {
20612 case VCVTTSS2USI64Zrm_Int:
20613 case VCVTTSS2USI64Zrr_Int:
20614 case VCVTTSS2USI64Zrrb_Int:
20615 case VCVTTSS2USIZrm_Int:
20616 case VCVTTSS2USIZrr_Int:
20617 case VCVTTSS2USIZrrb_Int:
20618 return true;
20619 }
20620 return false;
20621}
20622
20623bool isVPMOVM2Q(unsigned Opcode) {
20624 switch (Opcode) {
20625 case VPMOVM2QZ128rk:
20626 case VPMOVM2QZ256rk:
20627 case VPMOVM2QZrk:
20628 return true;
20629 }
20630 return false;
20631}
20632
20633bool isVMOVD(unsigned Opcode) {
20634 switch (Opcode) {
20635 case VMOVDI2PDIZrm:
20636 case VMOVDI2PDIZrr:
20637 case VMOVDI2PDIrm:
20638 case VMOVDI2PDIrr:
20639 case VMOVPDI2DIZmr:
20640 case VMOVPDI2DIZrr:
20641 case VMOVPDI2DImr:
20642 case VMOVPDI2DIrr:
20643 case VMOVZPDILo2PDIZmr:
20644 case VMOVZPDILo2PDIZrm:
20645 case VMOVZPDILo2PDIZrr:
20646 case VMOVZPDILo2PDIZrr2:
20647 return true;
20648 }
20649 return false;
20650}
20651
20652bool isVCVTTPS2QQS(unsigned Opcode) {
20653 switch (Opcode) {
20654 case VCVTTPS2QQSZ128rm:
20655 case VCVTTPS2QQSZ128rmb:
20656 case VCVTTPS2QQSZ128rmbk:
20657 case VCVTTPS2QQSZ128rmbkz:
20658 case VCVTTPS2QQSZ128rmk:
20659 case VCVTTPS2QQSZ128rmkz:
20660 case VCVTTPS2QQSZ128rr:
20661 case VCVTTPS2QQSZ128rrk:
20662 case VCVTTPS2QQSZ128rrkz:
20663 case VCVTTPS2QQSZ256rm:
20664 case VCVTTPS2QQSZ256rmb:
20665 case VCVTTPS2QQSZ256rmbk:
20666 case VCVTTPS2QQSZ256rmbkz:
20667 case VCVTTPS2QQSZ256rmk:
20668 case VCVTTPS2QQSZ256rmkz:
20669 case VCVTTPS2QQSZ256rr:
20670 case VCVTTPS2QQSZ256rrb:
20671 case VCVTTPS2QQSZ256rrbk:
20672 case VCVTTPS2QQSZ256rrbkz:
20673 case VCVTTPS2QQSZ256rrk:
20674 case VCVTTPS2QQSZ256rrkz:
20675 case VCVTTPS2QQSZrm:
20676 case VCVTTPS2QQSZrmb:
20677 case VCVTTPS2QQSZrmbk:
20678 case VCVTTPS2QQSZrmbkz:
20679 case VCVTTPS2QQSZrmk:
20680 case VCVTTPS2QQSZrmkz:
20681 case VCVTTPS2QQSZrr:
20682 case VCVTTPS2QQSZrrb:
20683 case VCVTTPS2QQSZrrbk:
20684 case VCVTTPS2QQSZrrbkz:
20685 case VCVTTPS2QQSZrrk:
20686 case VCVTTPS2QQSZrrkz:
20687 return true;
20688 }
20689 return false;
20690}
20691
20692bool isVSQRTBF16(unsigned Opcode) {
20693 switch (Opcode) {
20694 case VSQRTBF16Z128m:
20695 case VSQRTBF16Z128mb:
20696 case VSQRTBF16Z128mbk:
20697 case VSQRTBF16Z128mbkz:
20698 case VSQRTBF16Z128mk:
20699 case VSQRTBF16Z128mkz:
20700 case VSQRTBF16Z128r:
20701 case VSQRTBF16Z128rk:
20702 case VSQRTBF16Z128rkz:
20703 case VSQRTBF16Z256m:
20704 case VSQRTBF16Z256mb:
20705 case VSQRTBF16Z256mbk:
20706 case VSQRTBF16Z256mbkz:
20707 case VSQRTBF16Z256mk:
20708 case VSQRTBF16Z256mkz:
20709 case VSQRTBF16Z256r:
20710 case VSQRTBF16Z256rk:
20711 case VSQRTBF16Z256rkz:
20712 case VSQRTBF16Zm:
20713 case VSQRTBF16Zmb:
20714 case VSQRTBF16Zmbk:
20715 case VSQRTBF16Zmbkz:
20716 case VSQRTBF16Zmk:
20717 case VSQRTBF16Zmkz:
20718 case VSQRTBF16Zr:
20719 case VSQRTBF16Zrk:
20720 case VSQRTBF16Zrkz:
20721 return true;
20722 }
20723 return false;
20724}
20725
20726bool isVFPCLASSPH(unsigned Opcode) {
20727 switch (Opcode) {
20728 case VFPCLASSPHZ128mbi:
20729 case VFPCLASSPHZ128mbik:
20730 case VFPCLASSPHZ128mi:
20731 case VFPCLASSPHZ128mik:
20732 case VFPCLASSPHZ128ri:
20733 case VFPCLASSPHZ128rik:
20734 case VFPCLASSPHZ256mbi:
20735 case VFPCLASSPHZ256mbik:
20736 case VFPCLASSPHZ256mi:
20737 case VFPCLASSPHZ256mik:
20738 case VFPCLASSPHZ256ri:
20739 case VFPCLASSPHZ256rik:
20740 case VFPCLASSPHZmbi:
20741 case VFPCLASSPHZmbik:
20742 case VFPCLASSPHZmi:
20743 case VFPCLASSPHZmik:
20744 case VFPCLASSPHZri:
20745 case VFPCLASSPHZrik:
20746 return true;
20747 }
20748 return false;
20749}
20750
20751bool isVCVTSS2SH(unsigned Opcode) {
20752 switch (Opcode) {
20753 case VCVTSS2SHZrm_Int:
20754 case VCVTSS2SHZrmk_Int:
20755 case VCVTSS2SHZrmkz_Int:
20756 case VCVTSS2SHZrr_Int:
20757 case VCVTSS2SHZrrb_Int:
20758 case VCVTSS2SHZrrbk_Int:
20759 case VCVTSS2SHZrrbkz_Int:
20760 case VCVTSS2SHZrrk_Int:
20761 case VCVTSS2SHZrrkz_Int:
20762 return true;
20763 }
20764 return false;
20765}
20766
20767bool isSCASB(unsigned Opcode) {
20768 return Opcode == SCASB;
20769}
20770
20771bool isPSRLD(unsigned Opcode) {
20772 switch (Opcode) {
20773 case MMX_PSRLDri:
20774 case MMX_PSRLDrm:
20775 case MMX_PSRLDrr:
20776 case PSRLDri:
20777 case PSRLDrm:
20778 case PSRLDrr:
20779 return true;
20780 }
20781 return false;
20782}
20783
20784bool isVADDPH(unsigned Opcode) {
20785 switch (Opcode) {
20786 case VADDPHZ128rm:
20787 case VADDPHZ128rmb:
20788 case VADDPHZ128rmbk:
20789 case VADDPHZ128rmbkz:
20790 case VADDPHZ128rmk:
20791 case VADDPHZ128rmkz:
20792 case VADDPHZ128rr:
20793 case VADDPHZ128rrk:
20794 case VADDPHZ128rrkz:
20795 case VADDPHZ256rm:
20796 case VADDPHZ256rmb:
20797 case VADDPHZ256rmbk:
20798 case VADDPHZ256rmbkz:
20799 case VADDPHZ256rmk:
20800 case VADDPHZ256rmkz:
20801 case VADDPHZ256rr:
20802 case VADDPHZ256rrk:
20803 case VADDPHZ256rrkz:
20804 case VADDPHZrm:
20805 case VADDPHZrmb:
20806 case VADDPHZrmbk:
20807 case VADDPHZrmbkz:
20808 case VADDPHZrmk:
20809 case VADDPHZrmkz:
20810 case VADDPHZrr:
20811 case VADDPHZrrb:
20812 case VADDPHZrrbk:
20813 case VADDPHZrrbkz:
20814 case VADDPHZrrk:
20815 case VADDPHZrrkz:
20816 return true;
20817 }
20818 return false;
20819}
20820
20821bool isFSUB(unsigned Opcode) {
20822 switch (Opcode) {
20823 case SUB_F32m:
20824 case SUB_F64m:
20825 case SUB_FST0r:
20826 case SUB_FrST0:
20827 return true;
20828 }
20829 return false;
20830}
20831
20832bool isVCVTTPH2IBS(unsigned Opcode) {
20833 switch (Opcode) {
20834 case VCVTTPH2IBSZ128rm:
20835 case VCVTTPH2IBSZ128rmb:
20836 case VCVTTPH2IBSZ128rmbk:
20837 case VCVTTPH2IBSZ128rmbkz:
20838 case VCVTTPH2IBSZ128rmk:
20839 case VCVTTPH2IBSZ128rmkz:
20840 case VCVTTPH2IBSZ128rr:
20841 case VCVTTPH2IBSZ128rrk:
20842 case VCVTTPH2IBSZ128rrkz:
20843 case VCVTTPH2IBSZ256rm:
20844 case VCVTTPH2IBSZ256rmb:
20845 case VCVTTPH2IBSZ256rmbk:
20846 case VCVTTPH2IBSZ256rmbkz:
20847 case VCVTTPH2IBSZ256rmk:
20848 case VCVTTPH2IBSZ256rmkz:
20849 case VCVTTPH2IBSZ256rr:
20850 case VCVTTPH2IBSZ256rrk:
20851 case VCVTTPH2IBSZ256rrkz:
20852 case VCVTTPH2IBSZrm:
20853 case VCVTTPH2IBSZrmb:
20854 case VCVTTPH2IBSZrmbk:
20855 case VCVTTPH2IBSZrmbkz:
20856 case VCVTTPH2IBSZrmk:
20857 case VCVTTPH2IBSZrmkz:
20858 case VCVTTPH2IBSZrr:
20859 case VCVTTPH2IBSZrrb:
20860 case VCVTTPH2IBSZrrbk:
20861 case VCVTTPH2IBSZrrbkz:
20862 case VCVTTPH2IBSZrrk:
20863 case VCVTTPH2IBSZrrkz:
20864 return true;
20865 }
20866 return false;
20867}
20868
20869bool isVEXTRACTI64X2(unsigned Opcode) {
20870 switch (Opcode) {
20871 case VEXTRACTI64X2Z256mri:
20872 case VEXTRACTI64X2Z256mrik:
20873 case VEXTRACTI64X2Z256rri:
20874 case VEXTRACTI64X2Z256rrik:
20875 case VEXTRACTI64X2Z256rrikz:
20876 case VEXTRACTI64X2Zmri:
20877 case VEXTRACTI64X2Zmrik:
20878 case VEXTRACTI64X2Zrri:
20879 case VEXTRACTI64X2Zrrik:
20880 case VEXTRACTI64X2Zrrikz:
20881 return true;
20882 }
20883 return false;
20884}
20885
20886bool isVPSHLDD(unsigned Opcode) {
20887 switch (Opcode) {
20888 case VPSHLDDZ128rmbi:
20889 case VPSHLDDZ128rmbik:
20890 case VPSHLDDZ128rmbikz:
20891 case VPSHLDDZ128rmi:
20892 case VPSHLDDZ128rmik:
20893 case VPSHLDDZ128rmikz:
20894 case VPSHLDDZ128rri:
20895 case VPSHLDDZ128rrik:
20896 case VPSHLDDZ128rrikz:
20897 case VPSHLDDZ256rmbi:
20898 case VPSHLDDZ256rmbik:
20899 case VPSHLDDZ256rmbikz:
20900 case VPSHLDDZ256rmi:
20901 case VPSHLDDZ256rmik:
20902 case VPSHLDDZ256rmikz:
20903 case VPSHLDDZ256rri:
20904 case VPSHLDDZ256rrik:
20905 case VPSHLDDZ256rrikz:
20906 case VPSHLDDZrmbi:
20907 case VPSHLDDZrmbik:
20908 case VPSHLDDZrmbikz:
20909 case VPSHLDDZrmi:
20910 case VPSHLDDZrmik:
20911 case VPSHLDDZrmikz:
20912 case VPSHLDDZrri:
20913 case VPSHLDDZrrik:
20914 case VPSHLDDZrrikz:
20915 return true;
20916 }
20917 return false;
20918}
20919
20920bool isPMINUW(unsigned Opcode) {
20921 switch (Opcode) {
20922 case PMINUWrm:
20923 case PMINUWrr:
20924 return true;
20925 }
20926 return false;
20927}
20928
20929bool isPSUBSB(unsigned Opcode) {
20930 switch (Opcode) {
20931 case MMX_PSUBSBrm:
20932 case MMX_PSUBSBrr:
20933 case PSUBSBrm:
20934 case PSUBSBrr:
20935 return true;
20936 }
20937 return false;
20938}
20939
20940bool isVCVT2PS2PHX(unsigned Opcode) {
20941 switch (Opcode) {
20942 case VCVT2PS2PHXZ128rm:
20943 case VCVT2PS2PHXZ128rmb:
20944 case VCVT2PS2PHXZ128rmbk:
20945 case VCVT2PS2PHXZ128rmbkz:
20946 case VCVT2PS2PHXZ128rmk:
20947 case VCVT2PS2PHXZ128rmkz:
20948 case VCVT2PS2PHXZ128rr:
20949 case VCVT2PS2PHXZ128rrk:
20950 case VCVT2PS2PHXZ128rrkz:
20951 case VCVT2PS2PHXZ256rm:
20952 case VCVT2PS2PHXZ256rmb:
20953 case VCVT2PS2PHXZ256rmbk:
20954 case VCVT2PS2PHXZ256rmbkz:
20955 case VCVT2PS2PHXZ256rmk:
20956 case VCVT2PS2PHXZ256rmkz:
20957 case VCVT2PS2PHXZ256rr:
20958 case VCVT2PS2PHXZ256rrk:
20959 case VCVT2PS2PHXZ256rrkz:
20960 case VCVT2PS2PHXZrm:
20961 case VCVT2PS2PHXZrmb:
20962 case VCVT2PS2PHXZrmbk:
20963 case VCVT2PS2PHXZrmbkz:
20964 case VCVT2PS2PHXZrmk:
20965 case VCVT2PS2PHXZrmkz:
20966 case VCVT2PS2PHXZrr:
20967 case VCVT2PS2PHXZrrb:
20968 case VCVT2PS2PHXZrrbk:
20969 case VCVT2PS2PHXZrrbkz:
20970 case VCVT2PS2PHXZrrk:
20971 case VCVT2PS2PHXZrrkz:
20972 return true;
20973 }
20974 return false;
20975}
20976
20977bool isVPCMPEQD(unsigned Opcode) {
20978 switch (Opcode) {
20979 case VPCMPEQDYrm:
20980 case VPCMPEQDYrr:
20981 case VPCMPEQDZ128rm:
20982 case VPCMPEQDZ128rmb:
20983 case VPCMPEQDZ128rmbk:
20984 case VPCMPEQDZ128rmk:
20985 case VPCMPEQDZ128rr:
20986 case VPCMPEQDZ128rrk:
20987 case VPCMPEQDZ256rm:
20988 case VPCMPEQDZ256rmb:
20989 case VPCMPEQDZ256rmbk:
20990 case VPCMPEQDZ256rmk:
20991 case VPCMPEQDZ256rr:
20992 case VPCMPEQDZ256rrk:
20993 case VPCMPEQDZrm:
20994 case VPCMPEQDZrmb:
20995 case VPCMPEQDZrmbk:
20996 case VPCMPEQDZrmk:
20997 case VPCMPEQDZrr:
20998 case VPCMPEQDZrrk:
20999 case VPCMPEQDrm:
21000 case VPCMPEQDrr:
21001 return true;
21002 }
21003 return false;
21004}
21005
21006bool isVPSCATTERQD(unsigned Opcode) {
21007 switch (Opcode) {
21008 case VPSCATTERQDZ128mr:
21009 case VPSCATTERQDZ256mr:
21010 case VPSCATTERQDZmr:
21011 return true;
21012 }
21013 return false;
21014}
21015
21016bool isKXNORB(unsigned Opcode) {
21017 return Opcode == KXNORBkk;
21018}
21019
21020bool isLDDQU(unsigned Opcode) {
21021 return Opcode == LDDQUrm;
21022}
21023
21024bool isMASKMOVQ(unsigned Opcode) {
21025 switch (Opcode) {
21026 case MMX_MASKMOVQ:
21027 case MMX_MASKMOVQ64:
21028 return true;
21029 }
21030 return false;
21031}
21032
21033bool isPABSW(unsigned Opcode) {
21034 switch (Opcode) {
21035 case MMX_PABSWrm:
21036 case MMX_PABSWrr:
21037 case PABSWrm:
21038 case PABSWrr:
21039 return true;
21040 }
21041 return false;
21042}
21043
21044bool isVPCOMQ(unsigned Opcode) {
21045 switch (Opcode) {
21046 case VPCOMQmi:
21047 case VPCOMQri:
21048 return true;
21049 }
21050 return false;
21051}
21052
21053bool isVPROLD(unsigned Opcode) {
21054 switch (Opcode) {
21055 case VPROLDZ128mbi:
21056 case VPROLDZ128mbik:
21057 case VPROLDZ128mbikz:
21058 case VPROLDZ128mi:
21059 case VPROLDZ128mik:
21060 case VPROLDZ128mikz:
21061 case VPROLDZ128ri:
21062 case VPROLDZ128rik:
21063 case VPROLDZ128rikz:
21064 case VPROLDZ256mbi:
21065 case VPROLDZ256mbik:
21066 case VPROLDZ256mbikz:
21067 case VPROLDZ256mi:
21068 case VPROLDZ256mik:
21069 case VPROLDZ256mikz:
21070 case VPROLDZ256ri:
21071 case VPROLDZ256rik:
21072 case VPROLDZ256rikz:
21073 case VPROLDZmbi:
21074 case VPROLDZmbik:
21075 case VPROLDZmbikz:
21076 case VPROLDZmi:
21077 case VPROLDZmik:
21078 case VPROLDZmikz:
21079 case VPROLDZri:
21080 case VPROLDZrik:
21081 case VPROLDZrikz:
21082 return true;
21083 }
21084 return false;
21085}
21086
21087bool isVSCATTERDPD(unsigned Opcode) {
21088 switch (Opcode) {
21089 case VSCATTERDPDZ128mr:
21090 case VSCATTERDPDZ256mr:
21091 case VSCATTERDPDZmr:
21092 return true;
21093 }
21094 return false;
21095}
21096
21097bool isFXRSTOR(unsigned Opcode) {
21098 return Opcode == FXRSTOR;
21099}
21100
21101bool isVPCMPUW(unsigned Opcode) {
21102 switch (Opcode) {
21103 case VPCMPUWZ128rmi:
21104 case VPCMPUWZ128rmik:
21105 case VPCMPUWZ128rri:
21106 case VPCMPUWZ128rrik:
21107 case VPCMPUWZ256rmi:
21108 case VPCMPUWZ256rmik:
21109 case VPCMPUWZ256rri:
21110 case VPCMPUWZ256rrik:
21111 case VPCMPUWZrmi:
21112 case VPCMPUWZrmik:
21113 case VPCMPUWZrri:
21114 case VPCMPUWZrrik:
21115 return true;
21116 }
21117 return false;
21118}
21119
21120bool isWBINVD(unsigned Opcode) {
21121 return Opcode == WBINVD;
21122}
21123
21124bool isVCVTTPD2UDQ(unsigned Opcode) {
21125 switch (Opcode) {
21126 case VCVTTPD2UDQZ128rm:
21127 case VCVTTPD2UDQZ128rmb:
21128 case VCVTTPD2UDQZ128rmbk:
21129 case VCVTTPD2UDQZ128rmbkz:
21130 case VCVTTPD2UDQZ128rmk:
21131 case VCVTTPD2UDQZ128rmkz:
21132 case VCVTTPD2UDQZ128rr:
21133 case VCVTTPD2UDQZ128rrk:
21134 case VCVTTPD2UDQZ128rrkz:
21135 case VCVTTPD2UDQZ256rm:
21136 case VCVTTPD2UDQZ256rmb:
21137 case VCVTTPD2UDQZ256rmbk:
21138 case VCVTTPD2UDQZ256rmbkz:
21139 case VCVTTPD2UDQZ256rmk:
21140 case VCVTTPD2UDQZ256rmkz:
21141 case VCVTTPD2UDQZ256rr:
21142 case VCVTTPD2UDQZ256rrk:
21143 case VCVTTPD2UDQZ256rrkz:
21144 case VCVTTPD2UDQZrm:
21145 case VCVTTPD2UDQZrmb:
21146 case VCVTTPD2UDQZrmbk:
21147 case VCVTTPD2UDQZrmbkz:
21148 case VCVTTPD2UDQZrmk:
21149 case VCVTTPD2UDQZrmkz:
21150 case VCVTTPD2UDQZrr:
21151 case VCVTTPD2UDQZrrb:
21152 case VCVTTPD2UDQZrrbk:
21153 case VCVTTPD2UDQZrrbkz:
21154 case VCVTTPD2UDQZrrk:
21155 case VCVTTPD2UDQZrrkz:
21156 return true;
21157 }
21158 return false;
21159}
21160
21161bool isERETU(unsigned Opcode) {
21162 return Opcode == ERETU;
21163}
21164
21165bool isPFRCPIT2(unsigned Opcode) {
21166 switch (Opcode) {
21167 case PFRCPIT2rm:
21168 case PFRCPIT2rr:
21169 return true;
21170 }
21171 return false;
21172}
21173
21174bool isVPERMT2W(unsigned Opcode) {
21175 switch (Opcode) {
21176 case VPERMT2WZ128rm:
21177 case VPERMT2WZ128rmk:
21178 case VPERMT2WZ128rmkz:
21179 case VPERMT2WZ128rr:
21180 case VPERMT2WZ128rrk:
21181 case VPERMT2WZ128rrkz:
21182 case VPERMT2WZ256rm:
21183 case VPERMT2WZ256rmk:
21184 case VPERMT2WZ256rmkz:
21185 case VPERMT2WZ256rr:
21186 case VPERMT2WZ256rrk:
21187 case VPERMT2WZ256rrkz:
21188 case VPERMT2WZrm:
21189 case VPERMT2WZrmk:
21190 case VPERMT2WZrmkz:
21191 case VPERMT2WZrr:
21192 case VPERMT2WZrrk:
21193 case VPERMT2WZrrkz:
21194 return true;
21195 }
21196 return false;
21197}
21198
21199bool isVEXTRACTF32X4(unsigned Opcode) {
21200 switch (Opcode) {
21201 case VEXTRACTF32X4Z256mri:
21202 case VEXTRACTF32X4Z256mrik:
21203 case VEXTRACTF32X4Z256rri:
21204 case VEXTRACTF32X4Z256rrik:
21205 case VEXTRACTF32X4Z256rrikz:
21206 case VEXTRACTF32X4Zmri:
21207 case VEXTRACTF32X4Zmrik:
21208 case VEXTRACTF32X4Zrri:
21209 case VEXTRACTF32X4Zrrik:
21210 case VEXTRACTF32X4Zrrikz:
21211 return true;
21212 }
21213 return false;
21214}
21215
21216bool isVGATHERPF0DPD(unsigned Opcode) {
21217 return Opcode == VGATHERPF0DPDm;
21218}
21219
21220bool isVBROADCASTF32X2(unsigned Opcode) {
21221 switch (Opcode) {
21222 case VBROADCASTF32X2Z256rm:
21223 case VBROADCASTF32X2Z256rmk:
21224 case VBROADCASTF32X2Z256rmkz:
21225 case VBROADCASTF32X2Z256rr:
21226 case VBROADCASTF32X2Z256rrk:
21227 case VBROADCASTF32X2Z256rrkz:
21228 case VBROADCASTF32X2Zrm:
21229 case VBROADCASTF32X2Zrmk:
21230 case VBROADCASTF32X2Zrmkz:
21231 case VBROADCASTF32X2Zrr:
21232 case VBROADCASTF32X2Zrrk:
21233 case VBROADCASTF32X2Zrrkz:
21234 return true;
21235 }
21236 return false;
21237}
21238
21239bool isVRCP14SD(unsigned Opcode) {
21240 switch (Opcode) {
21241 case VRCP14SDZrm:
21242 case VRCP14SDZrmk:
21243 case VRCP14SDZrmkz:
21244 case VRCP14SDZrr:
21245 case VRCP14SDZrrk:
21246 case VRCP14SDZrrkz:
21247 return true;
21248 }
21249 return false;
21250}
21251
21252bool isLAHF(unsigned Opcode) {
21253 return Opcode == LAHF;
21254}
21255
21256bool isPABSD(unsigned Opcode) {
21257 switch (Opcode) {
21258 case MMX_PABSDrm:
21259 case MMX_PABSDrr:
21260 case PABSDrm:
21261 case PABSDrr:
21262 return true;
21263 }
21264 return false;
21265}
21266
21267bool isPINSRB(unsigned Opcode) {
21268 switch (Opcode) {
21269 case PINSRBrmi:
21270 case PINSRBrri:
21271 return true;
21272 }
21273 return false;
21274}
21275
21276bool isSKINIT(unsigned Opcode) {
21277 return Opcode == SKINIT;
21278}
21279
21280bool isENTER(unsigned Opcode) {
21281 return Opcode == ENTER;
21282}
21283
21284bool isVCVTSI2SS(unsigned Opcode) {
21285 switch (Opcode) {
21286 case VCVTSI2SSZrm_Int:
21287 case VCVTSI2SSZrr_Int:
21288 case VCVTSI2SSZrrb_Int:
21289 case VCVTSI2SSrm_Int:
21290 case VCVTSI2SSrr_Int:
21291 case VCVTSI642SSZrm_Int:
21292 case VCVTSI642SSZrr_Int:
21293 case VCVTSI642SSZrrb_Int:
21294 case VCVTSI642SSrm_Int:
21295 case VCVTSI642SSrr_Int:
21296 return true;
21297 }
21298 return false;
21299}
21300
21301bool isVFMADD231PD(unsigned Opcode) {
21302 switch (Opcode) {
21303 case VFMADD231PDYm:
21304 case VFMADD231PDYr:
21305 case VFMADD231PDZ128m:
21306 case VFMADD231PDZ128mb:
21307 case VFMADD231PDZ128mbk:
21308 case VFMADD231PDZ128mbkz:
21309 case VFMADD231PDZ128mk:
21310 case VFMADD231PDZ128mkz:
21311 case VFMADD231PDZ128r:
21312 case VFMADD231PDZ128rk:
21313 case VFMADD231PDZ128rkz:
21314 case VFMADD231PDZ256m:
21315 case VFMADD231PDZ256mb:
21316 case VFMADD231PDZ256mbk:
21317 case VFMADD231PDZ256mbkz:
21318 case VFMADD231PDZ256mk:
21319 case VFMADD231PDZ256mkz:
21320 case VFMADD231PDZ256r:
21321 case VFMADD231PDZ256rk:
21322 case VFMADD231PDZ256rkz:
21323 case VFMADD231PDZm:
21324 case VFMADD231PDZmb:
21325 case VFMADD231PDZmbk:
21326 case VFMADD231PDZmbkz:
21327 case VFMADD231PDZmk:
21328 case VFMADD231PDZmkz:
21329 case VFMADD231PDZr:
21330 case VFMADD231PDZrb:
21331 case VFMADD231PDZrbk:
21332 case VFMADD231PDZrbkz:
21333 case VFMADD231PDZrk:
21334 case VFMADD231PDZrkz:
21335 case VFMADD231PDm:
21336 case VFMADD231PDr:
21337 return true;
21338 }
21339 return false;
21340}
21341
21342bool isLOADIWKEY(unsigned Opcode) {
21343 return Opcode == LOADIWKEY;
21344}
21345
21346bool isVMOVNTDQA(unsigned Opcode) {
21347 switch (Opcode) {
21348 case VMOVNTDQAYrm:
21349 case VMOVNTDQAZ128rm:
21350 case VMOVNTDQAZ256rm:
21351 case VMOVNTDQAZrm:
21352 case VMOVNTDQArm:
21353 return true;
21354 }
21355 return false;
21356}
21357
21358bool isVPERMT2PS(unsigned Opcode) {
21359 switch (Opcode) {
21360 case VPERMT2PSZ128rm:
21361 case VPERMT2PSZ128rmb:
21362 case VPERMT2PSZ128rmbk:
21363 case VPERMT2PSZ128rmbkz:
21364 case VPERMT2PSZ128rmk:
21365 case VPERMT2PSZ128rmkz:
21366 case VPERMT2PSZ128rr:
21367 case VPERMT2PSZ128rrk:
21368 case VPERMT2PSZ128rrkz:
21369 case VPERMT2PSZ256rm:
21370 case VPERMT2PSZ256rmb:
21371 case VPERMT2PSZ256rmbk:
21372 case VPERMT2PSZ256rmbkz:
21373 case VPERMT2PSZ256rmk:
21374 case VPERMT2PSZ256rmkz:
21375 case VPERMT2PSZ256rr:
21376 case VPERMT2PSZ256rrk:
21377 case VPERMT2PSZ256rrkz:
21378 case VPERMT2PSZrm:
21379 case VPERMT2PSZrmb:
21380 case VPERMT2PSZrmbk:
21381 case VPERMT2PSZrmbkz:
21382 case VPERMT2PSZrmk:
21383 case VPERMT2PSZrmkz:
21384 case VPERMT2PSZrr:
21385 case VPERMT2PSZrrk:
21386 case VPERMT2PSZrrkz:
21387 return true;
21388 }
21389 return false;
21390}
21391
21392bool isPUSHF(unsigned Opcode) {
21393 return Opcode == PUSHF16;
21394}
21395
21396bool isMPSADBW(unsigned Opcode) {
21397 switch (Opcode) {
21398 case MPSADBWrmi:
21399 case MPSADBWrri:
21400 return true;
21401 }
21402 return false;
21403}
21404
21405bool isVMINMAXSH(unsigned Opcode) {
21406 switch (Opcode) {
21407 case VMINMAXSHrmi_Int:
21408 case VMINMAXSHrmik_Int:
21409 case VMINMAXSHrmikz_Int:
21410 case VMINMAXSHrri_Int:
21411 case VMINMAXSHrrib_Int:
21412 case VMINMAXSHrribk_Int:
21413 case VMINMAXSHrribkz_Int:
21414 case VMINMAXSHrrik_Int:
21415 case VMINMAXSHrrikz_Int:
21416 return true;
21417 }
21418 return false;
21419}
21420
21421bool isVRSQRT14SS(unsigned Opcode) {
21422 switch (Opcode) {
21423 case VRSQRT14SSZrm:
21424 case VRSQRT14SSZrmk:
21425 case VRSQRT14SSZrmkz:
21426 case VRSQRT14SSZrr:
21427 case VRSQRT14SSZrrk:
21428 case VRSQRT14SSZrrkz:
21429 return true;
21430 }
21431 return false;
21432}
21433
21434bool isVCVTDQ2PD(unsigned Opcode) {
21435 switch (Opcode) {
21436 case VCVTDQ2PDYrm:
21437 case VCVTDQ2PDYrr:
21438 case VCVTDQ2PDZ128rm:
21439 case VCVTDQ2PDZ128rmb:
21440 case VCVTDQ2PDZ128rmbk:
21441 case VCVTDQ2PDZ128rmbkz:
21442 case VCVTDQ2PDZ128rmk:
21443 case VCVTDQ2PDZ128rmkz:
21444 case VCVTDQ2PDZ128rr:
21445 case VCVTDQ2PDZ128rrk:
21446 case VCVTDQ2PDZ128rrkz:
21447 case VCVTDQ2PDZ256rm:
21448 case VCVTDQ2PDZ256rmb:
21449 case VCVTDQ2PDZ256rmbk:
21450 case VCVTDQ2PDZ256rmbkz:
21451 case VCVTDQ2PDZ256rmk:
21452 case VCVTDQ2PDZ256rmkz:
21453 case VCVTDQ2PDZ256rr:
21454 case VCVTDQ2PDZ256rrk:
21455 case VCVTDQ2PDZ256rrkz:
21456 case VCVTDQ2PDZrm:
21457 case VCVTDQ2PDZrmb:
21458 case VCVTDQ2PDZrmbk:
21459 case VCVTDQ2PDZrmbkz:
21460 case VCVTDQ2PDZrmk:
21461 case VCVTDQ2PDZrmkz:
21462 case VCVTDQ2PDZrr:
21463 case VCVTDQ2PDZrrk:
21464 case VCVTDQ2PDZrrkz:
21465 case VCVTDQ2PDrm:
21466 case VCVTDQ2PDrr:
21467 return true;
21468 }
21469 return false;
21470}
21471
21472bool isVORPS(unsigned Opcode) {
21473 switch (Opcode) {
21474 case VORPSYrm:
21475 case VORPSYrr:
21476 case VORPSZ128rm:
21477 case VORPSZ128rmb:
21478 case VORPSZ128rmbk:
21479 case VORPSZ128rmbkz:
21480 case VORPSZ128rmk:
21481 case VORPSZ128rmkz:
21482 case VORPSZ128rr:
21483 case VORPSZ128rrk:
21484 case VORPSZ128rrkz:
21485 case VORPSZ256rm:
21486 case VORPSZ256rmb:
21487 case VORPSZ256rmbk:
21488 case VORPSZ256rmbkz:
21489 case VORPSZ256rmk:
21490 case VORPSZ256rmkz:
21491 case VORPSZ256rr:
21492 case VORPSZ256rrk:
21493 case VORPSZ256rrkz:
21494 case VORPSZrm:
21495 case VORPSZrmb:
21496 case VORPSZrmbk:
21497 case VORPSZrmbkz:
21498 case VORPSZrmk:
21499 case VORPSZrmkz:
21500 case VORPSZrr:
21501 case VORPSZrrk:
21502 case VORPSZrrkz:
21503 case VORPSrm:
21504 case VORPSrr:
21505 return true;
21506 }
21507 return false;
21508}
21509
21510bool isVPEXPANDQ(unsigned Opcode) {
21511 switch (Opcode) {
21512 case VPEXPANDQZ128rm:
21513 case VPEXPANDQZ128rmk:
21514 case VPEXPANDQZ128rmkz:
21515 case VPEXPANDQZ128rr:
21516 case VPEXPANDQZ128rrk:
21517 case VPEXPANDQZ128rrkz:
21518 case VPEXPANDQZ256rm:
21519 case VPEXPANDQZ256rmk:
21520 case VPEXPANDQZ256rmkz:
21521 case VPEXPANDQZ256rr:
21522 case VPEXPANDQZ256rrk:
21523 case VPEXPANDQZ256rrkz:
21524 case VPEXPANDQZrm:
21525 case VPEXPANDQZrmk:
21526 case VPEXPANDQZrmkz:
21527 case VPEXPANDQZrr:
21528 case VPEXPANDQZrrk:
21529 case VPEXPANDQZrrkz:
21530 return true;
21531 }
21532 return false;
21533}
21534
21535bool isVPSHRDD(unsigned Opcode) {
21536 switch (Opcode) {
21537 case VPSHRDDZ128rmbi:
21538 case VPSHRDDZ128rmbik:
21539 case VPSHRDDZ128rmbikz:
21540 case VPSHRDDZ128rmi:
21541 case VPSHRDDZ128rmik:
21542 case VPSHRDDZ128rmikz:
21543 case VPSHRDDZ128rri:
21544 case VPSHRDDZ128rrik:
21545 case VPSHRDDZ128rrikz:
21546 case VPSHRDDZ256rmbi:
21547 case VPSHRDDZ256rmbik:
21548 case VPSHRDDZ256rmbikz:
21549 case VPSHRDDZ256rmi:
21550 case VPSHRDDZ256rmik:
21551 case VPSHRDDZ256rmikz:
21552 case VPSHRDDZ256rri:
21553 case VPSHRDDZ256rrik:
21554 case VPSHRDDZ256rrikz:
21555 case VPSHRDDZrmbi:
21556 case VPSHRDDZrmbik:
21557 case VPSHRDDZrmbikz:
21558 case VPSHRDDZrmi:
21559 case VPSHRDDZrmik:
21560 case VPSHRDDZrmikz:
21561 case VPSHRDDZrri:
21562 case VPSHRDDZrrik:
21563 case VPSHRDDZrrikz:
21564 return true;
21565 }
21566 return false;
21567}
21568
21569bool isTDPBSSD(unsigned Opcode) {
21570 return Opcode == TDPBSSD;
21571}
21572
21573bool isTESTUI(unsigned Opcode) {
21574 return Opcode == TESTUI;
21575}
21576
21577bool isVFMADDPD(unsigned Opcode) {
21578 switch (Opcode) {
21579 case VFMADDPD4Ymr:
21580 case VFMADDPD4Yrm:
21581 case VFMADDPD4Yrr:
21582 case VFMADDPD4Yrr_REV:
21583 case VFMADDPD4mr:
21584 case VFMADDPD4rm:
21585 case VFMADDPD4rr:
21586 case VFMADDPD4rr_REV:
21587 return true;
21588 }
21589 return false;
21590}
21591
21592bool isVPANDND(unsigned Opcode) {
21593 switch (Opcode) {
21594 case VPANDNDZ128rm:
21595 case VPANDNDZ128rmb:
21596 case VPANDNDZ128rmbk:
21597 case VPANDNDZ128rmbkz:
21598 case VPANDNDZ128rmk:
21599 case VPANDNDZ128rmkz:
21600 case VPANDNDZ128rr:
21601 case VPANDNDZ128rrk:
21602 case VPANDNDZ128rrkz:
21603 case VPANDNDZ256rm:
21604 case VPANDNDZ256rmb:
21605 case VPANDNDZ256rmbk:
21606 case VPANDNDZ256rmbkz:
21607 case VPANDNDZ256rmk:
21608 case VPANDNDZ256rmkz:
21609 case VPANDNDZ256rr:
21610 case VPANDNDZ256rrk:
21611 case VPANDNDZ256rrkz:
21612 case VPANDNDZrm:
21613 case VPANDNDZrmb:
21614 case VPANDNDZrmbk:
21615 case VPANDNDZrmbkz:
21616 case VPANDNDZrmk:
21617 case VPANDNDZrmkz:
21618 case VPANDNDZrr:
21619 case VPANDNDZrrk:
21620 case VPANDNDZrrkz:
21621 return true;
21622 }
21623 return false;
21624}
21625
21626bool isVPMOVSDB(unsigned Opcode) {
21627 switch (Opcode) {
21628 case VPMOVSDBZ128mr:
21629 case VPMOVSDBZ128mrk:
21630 case VPMOVSDBZ128rr:
21631 case VPMOVSDBZ128rrk:
21632 case VPMOVSDBZ128rrkz:
21633 case VPMOVSDBZ256mr:
21634 case VPMOVSDBZ256mrk:
21635 case VPMOVSDBZ256rr:
21636 case VPMOVSDBZ256rrk:
21637 case VPMOVSDBZ256rrkz:
21638 case VPMOVSDBZmr:
21639 case VPMOVSDBZmrk:
21640 case VPMOVSDBZrr:
21641 case VPMOVSDBZrrk:
21642 case VPMOVSDBZrrkz:
21643 return true;
21644 }
21645 return false;
21646}
21647
21648bool isVPBROADCASTB(unsigned Opcode) {
21649 switch (Opcode) {
21650 case VPBROADCASTBYrm:
21651 case VPBROADCASTBYrr:
21652 case VPBROADCASTBZ128rm:
21653 case VPBROADCASTBZ128rmk:
21654 case VPBROADCASTBZ128rmkz:
21655 case VPBROADCASTBZ128rr:
21656 case VPBROADCASTBZ128rrk:
21657 case VPBROADCASTBZ128rrkz:
21658 case VPBROADCASTBZ256rm:
21659 case VPBROADCASTBZ256rmk:
21660 case VPBROADCASTBZ256rmkz:
21661 case VPBROADCASTBZ256rr:
21662 case VPBROADCASTBZ256rrk:
21663 case VPBROADCASTBZ256rrkz:
21664 case VPBROADCASTBZrm:
21665 case VPBROADCASTBZrmk:
21666 case VPBROADCASTBZrmkz:
21667 case VPBROADCASTBZrr:
21668 case VPBROADCASTBZrrk:
21669 case VPBROADCASTBZrrkz:
21670 case VPBROADCASTBrZ128rr:
21671 case VPBROADCASTBrZ128rrk:
21672 case VPBROADCASTBrZ128rrkz:
21673 case VPBROADCASTBrZ256rr:
21674 case VPBROADCASTBrZ256rrk:
21675 case VPBROADCASTBrZ256rrkz:
21676 case VPBROADCASTBrZrr:
21677 case VPBROADCASTBrZrrk:
21678 case VPBROADCASTBrZrrkz:
21679 case VPBROADCASTBrm:
21680 case VPBROADCASTBrr:
21681 return true;
21682 }
21683 return false;
21684}
21685
21686bool isCVTPI2PD(unsigned Opcode) {
21687 switch (Opcode) {
21688 case MMX_CVTPI2PDrm:
21689 case MMX_CVTPI2PDrr:
21690 return true;
21691 }
21692 return false;
21693}
21694
21695bool isVPERMI2B(unsigned Opcode) {
21696 switch (Opcode) {
21697 case VPERMI2BZ128rm:
21698 case VPERMI2BZ128rmk:
21699 case VPERMI2BZ128rmkz:
21700 case VPERMI2BZ128rr:
21701 case VPERMI2BZ128rrk:
21702 case VPERMI2BZ128rrkz:
21703 case VPERMI2BZ256rm:
21704 case VPERMI2BZ256rmk:
21705 case VPERMI2BZ256rmkz:
21706 case VPERMI2BZ256rr:
21707 case VPERMI2BZ256rrk:
21708 case VPERMI2BZ256rrkz:
21709 case VPERMI2BZrm:
21710 case VPERMI2BZrmk:
21711 case VPERMI2BZrmkz:
21712 case VPERMI2BZrr:
21713 case VPERMI2BZrrk:
21714 case VPERMI2BZrrkz:
21715 return true;
21716 }
21717 return false;
21718}
21719
21720bool isVPMINSB(unsigned Opcode) {
21721 switch (Opcode) {
21722 case VPMINSBYrm:
21723 case VPMINSBYrr:
21724 case VPMINSBZ128rm:
21725 case VPMINSBZ128rmk:
21726 case VPMINSBZ128rmkz:
21727 case VPMINSBZ128rr:
21728 case VPMINSBZ128rrk:
21729 case VPMINSBZ128rrkz:
21730 case VPMINSBZ256rm:
21731 case VPMINSBZ256rmk:
21732 case VPMINSBZ256rmkz:
21733 case VPMINSBZ256rr:
21734 case VPMINSBZ256rrk:
21735 case VPMINSBZ256rrkz:
21736 case VPMINSBZrm:
21737 case VPMINSBZrmk:
21738 case VPMINSBZrmkz:
21739 case VPMINSBZrr:
21740 case VPMINSBZrrk:
21741 case VPMINSBZrrkz:
21742 case VPMINSBrm:
21743 case VPMINSBrr:
21744 return true;
21745 }
21746 return false;
21747}
21748
21749bool isLAR(unsigned Opcode) {
21750 switch (Opcode) {
21751 case LAR16rm:
21752 case LAR16rr:
21753 case LAR32rm:
21754 case LAR32rr:
21755 case LAR64rm:
21756 case LAR64rr:
21757 return true;
21758 }
21759 return false;
21760}
21761
21762bool isINVLPGB(unsigned Opcode) {
21763 switch (Opcode) {
21764 case INVLPGB32:
21765 case INVLPGB64:
21766 return true;
21767 }
21768 return false;
21769}
21770
21771bool isTLBSYNC(unsigned Opcode) {
21772 return Opcode == TLBSYNC;
21773}
21774
21775bool isFDIVP(unsigned Opcode) {
21776 return Opcode == DIV_FPrST0;
21777}
21778
21779bool isVPSRLW(unsigned Opcode) {
21780 switch (Opcode) {
21781 case VPSRLWYri:
21782 case VPSRLWYrm:
21783 case VPSRLWYrr:
21784 case VPSRLWZ128mi:
21785 case VPSRLWZ128mik:
21786 case VPSRLWZ128mikz:
21787 case VPSRLWZ128ri:
21788 case VPSRLWZ128rik:
21789 case VPSRLWZ128rikz:
21790 case VPSRLWZ128rm:
21791 case VPSRLWZ128rmk:
21792 case VPSRLWZ128rmkz:
21793 case VPSRLWZ128rr:
21794 case VPSRLWZ128rrk:
21795 case VPSRLWZ128rrkz:
21796 case VPSRLWZ256mi:
21797 case VPSRLWZ256mik:
21798 case VPSRLWZ256mikz:
21799 case VPSRLWZ256ri:
21800 case VPSRLWZ256rik:
21801 case VPSRLWZ256rikz:
21802 case VPSRLWZ256rm:
21803 case VPSRLWZ256rmk:
21804 case VPSRLWZ256rmkz:
21805 case VPSRLWZ256rr:
21806 case VPSRLWZ256rrk:
21807 case VPSRLWZ256rrkz:
21808 case VPSRLWZmi:
21809 case VPSRLWZmik:
21810 case VPSRLWZmikz:
21811 case VPSRLWZri:
21812 case VPSRLWZrik:
21813 case VPSRLWZrikz:
21814 case VPSRLWZrm:
21815 case VPSRLWZrmk:
21816 case VPSRLWZrmkz:
21817 case VPSRLWZrr:
21818 case VPSRLWZrrk:
21819 case VPSRLWZrrkz:
21820 case VPSRLWri:
21821 case VPSRLWrm:
21822 case VPSRLWrr:
21823 return true;
21824 }
21825 return false;
21826}
21827
21828bool isVRCP28SS(unsigned Opcode) {
21829 switch (Opcode) {
21830 case VRCP28SSZm:
21831 case VRCP28SSZmk:
21832 case VRCP28SSZmkz:
21833 case VRCP28SSZr:
21834 case VRCP28SSZrb:
21835 case VRCP28SSZrbk:
21836 case VRCP28SSZrbkz:
21837 case VRCP28SSZrk:
21838 case VRCP28SSZrkz:
21839 return true;
21840 }
21841 return false;
21842}
21843
21844bool isVMOVHPS(unsigned Opcode) {
21845 switch (Opcode) {
21846 case VMOVHPSZ128mr:
21847 case VMOVHPSZ128rm:
21848 case VMOVHPSmr:
21849 case VMOVHPSrm:
21850 return true;
21851 }
21852 return false;
21853}
21854
21855bool isVPMACSSDD(unsigned Opcode) {
21856 switch (Opcode) {
21857 case VPMACSSDDrm:
21858 case VPMACSSDDrr:
21859 return true;
21860 }
21861 return false;
21862}
21863
21864bool isPEXT(unsigned Opcode) {
21865 switch (Opcode) {
21866 case PEXT32rm:
21867 case PEXT32rm_EVEX:
21868 case PEXT32rr:
21869 case PEXT32rr_EVEX:
21870 case PEXT64rm:
21871 case PEXT64rm_EVEX:
21872 case PEXT64rr:
21873 case PEXT64rr_EVEX:
21874 return true;
21875 }
21876 return false;
21877}
21878
21879bool isVMAXBF16(unsigned Opcode) {
21880 switch (Opcode) {
21881 case VMAXBF16Z128rm:
21882 case VMAXBF16Z128rmb:
21883 case VMAXBF16Z128rmbk:
21884 case VMAXBF16Z128rmbkz:
21885 case VMAXBF16Z128rmk:
21886 case VMAXBF16Z128rmkz:
21887 case VMAXBF16Z128rr:
21888 case VMAXBF16Z128rrk:
21889 case VMAXBF16Z128rrkz:
21890 case VMAXBF16Z256rm:
21891 case VMAXBF16Z256rmb:
21892 case VMAXBF16Z256rmbk:
21893 case VMAXBF16Z256rmbkz:
21894 case VMAXBF16Z256rmk:
21895 case VMAXBF16Z256rmkz:
21896 case VMAXBF16Z256rr:
21897 case VMAXBF16Z256rrk:
21898 case VMAXBF16Z256rrkz:
21899 case VMAXBF16Zrm:
21900 case VMAXBF16Zrmb:
21901 case VMAXBF16Zrmbk:
21902 case VMAXBF16Zrmbkz:
21903 case VMAXBF16Zrmk:
21904 case VMAXBF16Zrmkz:
21905 case VMAXBF16Zrr:
21906 case VMAXBF16Zrrk:
21907 case VMAXBF16Zrrkz:
21908 return true;
21909 }
21910 return false;
21911}
21912
21913bool isVRSQRT14SD(unsigned Opcode) {
21914 switch (Opcode) {
21915 case VRSQRT14SDZrm:
21916 case VRSQRT14SDZrmk:
21917 case VRSQRT14SDZrmkz:
21918 case VRSQRT14SDZrr:
21919 case VRSQRT14SDZrrk:
21920 case VRSQRT14SDZrrkz:
21921 return true;
21922 }
21923 return false;
21924}
21925
21926bool isVPDPWSSD(unsigned Opcode) {
21927 switch (Opcode) {
21928 case VPDPWSSDYrm:
21929 case VPDPWSSDYrr:
21930 case VPDPWSSDZ128rm:
21931 case VPDPWSSDZ128rmb:
21932 case VPDPWSSDZ128rmbk:
21933 case VPDPWSSDZ128rmbkz:
21934 case VPDPWSSDZ128rmk:
21935 case VPDPWSSDZ128rmkz:
21936 case VPDPWSSDZ128rr:
21937 case VPDPWSSDZ128rrk:
21938 case VPDPWSSDZ128rrkz:
21939 case VPDPWSSDZ256rm:
21940 case VPDPWSSDZ256rmb:
21941 case VPDPWSSDZ256rmbk:
21942 case VPDPWSSDZ256rmbkz:
21943 case VPDPWSSDZ256rmk:
21944 case VPDPWSSDZ256rmkz:
21945 case VPDPWSSDZ256rr:
21946 case VPDPWSSDZ256rrk:
21947 case VPDPWSSDZ256rrkz:
21948 case VPDPWSSDZrm:
21949 case VPDPWSSDZrmb:
21950 case VPDPWSSDZrmbk:
21951 case VPDPWSSDZrmbkz:
21952 case VPDPWSSDZrmk:
21953 case VPDPWSSDZrmkz:
21954 case VPDPWSSDZrr:
21955 case VPDPWSSDZrrk:
21956 case VPDPWSSDZrrkz:
21957 case VPDPWSSDrm:
21958 case VPDPWSSDrr:
21959 return true;
21960 }
21961 return false;
21962}
21963
21964bool isVFMSUB231SD(unsigned Opcode) {
21965 switch (Opcode) {
21966 case VFMSUB231SDZm_Int:
21967 case VFMSUB231SDZmk_Int:
21968 case VFMSUB231SDZmkz_Int:
21969 case VFMSUB231SDZr_Int:
21970 case VFMSUB231SDZrb_Int:
21971 case VFMSUB231SDZrbk_Int:
21972 case VFMSUB231SDZrbkz_Int:
21973 case VFMSUB231SDZrk_Int:
21974 case VFMSUB231SDZrkz_Int:
21975 case VFMSUB231SDm_Int:
21976 case VFMSUB231SDr_Int:
21977 return true;
21978 }
21979 return false;
21980}
21981
21982bool isVPMOVZXWQ(unsigned Opcode) {
21983 switch (Opcode) {
21984 case VPMOVZXWQYrm:
21985 case VPMOVZXWQYrr:
21986 case VPMOVZXWQZ128rm:
21987 case VPMOVZXWQZ128rmk:
21988 case VPMOVZXWQZ128rmkz:
21989 case VPMOVZXWQZ128rr:
21990 case VPMOVZXWQZ128rrk:
21991 case VPMOVZXWQZ128rrkz:
21992 case VPMOVZXWQZ256rm:
21993 case VPMOVZXWQZ256rmk:
21994 case VPMOVZXWQZ256rmkz:
21995 case VPMOVZXWQZ256rr:
21996 case VPMOVZXWQZ256rrk:
21997 case VPMOVZXWQZ256rrkz:
21998 case VPMOVZXWQZrm:
21999 case VPMOVZXWQZrmk:
22000 case VPMOVZXWQZrmkz:
22001 case VPMOVZXWQZrr:
22002 case VPMOVZXWQZrrk:
22003 case VPMOVZXWQZrrkz:
22004 case VPMOVZXWQrm:
22005 case VPMOVZXWQrr:
22006 return true;
22007 }
22008 return false;
22009}
22010
22011bool isXORPD(unsigned Opcode) {
22012 switch (Opcode) {
22013 case XORPDrm:
22014 case XORPDrr:
22015 return true;
22016 }
22017 return false;
22018}
22019
22020bool isVMOVDQA(unsigned Opcode) {
22021 switch (Opcode) {
22022 case VMOVDQAYmr:
22023 case VMOVDQAYrm:
22024 case VMOVDQAYrr:
22025 case VMOVDQAYrr_REV:
22026 case VMOVDQAmr:
22027 case VMOVDQArm:
22028 case VMOVDQArr:
22029 case VMOVDQArr_REV:
22030 return true;
22031 }
22032 return false;
22033}
22034
22035bool isVFNMSUB213SD(unsigned Opcode) {
22036 switch (Opcode) {
22037 case VFNMSUB213SDZm_Int:
22038 case VFNMSUB213SDZmk_Int:
22039 case VFNMSUB213SDZmkz_Int:
22040 case VFNMSUB213SDZr_Int:
22041 case VFNMSUB213SDZrb_Int:
22042 case VFNMSUB213SDZrbk_Int:
22043 case VFNMSUB213SDZrbkz_Int:
22044 case VFNMSUB213SDZrk_Int:
22045 case VFNMSUB213SDZrkz_Int:
22046 case VFNMSUB213SDm_Int:
22047 case VFNMSUB213SDr_Int:
22048 return true;
22049 }
22050 return false;
22051}
22052
22053bool isVMINPS(unsigned Opcode) {
22054 switch (Opcode) {
22055 case VMINPSYrm:
22056 case VMINPSYrr:
22057 case VMINPSZ128rm:
22058 case VMINPSZ128rmb:
22059 case VMINPSZ128rmbk:
22060 case VMINPSZ128rmbkz:
22061 case VMINPSZ128rmk:
22062 case VMINPSZ128rmkz:
22063 case VMINPSZ128rr:
22064 case VMINPSZ128rrk:
22065 case VMINPSZ128rrkz:
22066 case VMINPSZ256rm:
22067 case VMINPSZ256rmb:
22068 case VMINPSZ256rmbk:
22069 case VMINPSZ256rmbkz:
22070 case VMINPSZ256rmk:
22071 case VMINPSZ256rmkz:
22072 case VMINPSZ256rr:
22073 case VMINPSZ256rrk:
22074 case VMINPSZ256rrkz:
22075 case VMINPSZrm:
22076 case VMINPSZrmb:
22077 case VMINPSZrmbk:
22078 case VMINPSZrmbkz:
22079 case VMINPSZrmk:
22080 case VMINPSZrmkz:
22081 case VMINPSZrr:
22082 case VMINPSZrrb:
22083 case VMINPSZrrbk:
22084 case VMINPSZrrbkz:
22085 case VMINPSZrrk:
22086 case VMINPSZrrkz:
22087 case VMINPSrm:
22088 case VMINPSrr:
22089 return true;
22090 }
22091 return false;
22092}
22093
22094bool isVFMSUB231PS(unsigned Opcode) {
22095 switch (Opcode) {
22096 case VFMSUB231PSYm:
22097 case VFMSUB231PSYr:
22098 case VFMSUB231PSZ128m:
22099 case VFMSUB231PSZ128mb:
22100 case VFMSUB231PSZ128mbk:
22101 case VFMSUB231PSZ128mbkz:
22102 case VFMSUB231PSZ128mk:
22103 case VFMSUB231PSZ128mkz:
22104 case VFMSUB231PSZ128r:
22105 case VFMSUB231PSZ128rk:
22106 case VFMSUB231PSZ128rkz:
22107 case VFMSUB231PSZ256m:
22108 case VFMSUB231PSZ256mb:
22109 case VFMSUB231PSZ256mbk:
22110 case VFMSUB231PSZ256mbkz:
22111 case VFMSUB231PSZ256mk:
22112 case VFMSUB231PSZ256mkz:
22113 case VFMSUB231PSZ256r:
22114 case VFMSUB231PSZ256rk:
22115 case VFMSUB231PSZ256rkz:
22116 case VFMSUB231PSZm:
22117 case VFMSUB231PSZmb:
22118 case VFMSUB231PSZmbk:
22119 case VFMSUB231PSZmbkz:
22120 case VFMSUB231PSZmk:
22121 case VFMSUB231PSZmkz:
22122 case VFMSUB231PSZr:
22123 case VFMSUB231PSZrb:
22124 case VFMSUB231PSZrbk:
22125 case VFMSUB231PSZrbkz:
22126 case VFMSUB231PSZrk:
22127 case VFMSUB231PSZrkz:
22128 case VFMSUB231PSm:
22129 case VFMSUB231PSr:
22130 return true;
22131 }
22132 return false;
22133}
22134
22135bool isVPCOMPRESSB(unsigned Opcode) {
22136 switch (Opcode) {
22137 case VPCOMPRESSBZ128mr:
22138 case VPCOMPRESSBZ128mrk:
22139 case VPCOMPRESSBZ128rr:
22140 case VPCOMPRESSBZ128rrk:
22141 case VPCOMPRESSBZ128rrkz:
22142 case VPCOMPRESSBZ256mr:
22143 case VPCOMPRESSBZ256mrk:
22144 case VPCOMPRESSBZ256rr:
22145 case VPCOMPRESSBZ256rrk:
22146 case VPCOMPRESSBZ256rrkz:
22147 case VPCOMPRESSBZmr:
22148 case VPCOMPRESSBZmrk:
22149 case VPCOMPRESSBZrr:
22150 case VPCOMPRESSBZrrk:
22151 case VPCOMPRESSBZrrkz:
22152 return true;
22153 }
22154 return false;
22155}
22156
22157bool isVPCMPEQQ(unsigned Opcode) {
22158 switch (Opcode) {
22159 case VPCMPEQQYrm:
22160 case VPCMPEQQYrr:
22161 case VPCMPEQQZ128rm:
22162 case VPCMPEQQZ128rmb:
22163 case VPCMPEQQZ128rmbk:
22164 case VPCMPEQQZ128rmk:
22165 case VPCMPEQQZ128rr:
22166 case VPCMPEQQZ128rrk:
22167 case VPCMPEQQZ256rm:
22168 case VPCMPEQQZ256rmb:
22169 case VPCMPEQQZ256rmbk:
22170 case VPCMPEQQZ256rmk:
22171 case VPCMPEQQZ256rr:
22172 case VPCMPEQQZ256rrk:
22173 case VPCMPEQQZrm:
22174 case VPCMPEQQZrmb:
22175 case VPCMPEQQZrmbk:
22176 case VPCMPEQQZrmk:
22177 case VPCMPEQQZrr:
22178 case VPCMPEQQZrrk:
22179 case VPCMPEQQrm:
22180 case VPCMPEQQrr:
22181 return true;
22182 }
22183 return false;
22184}
22185
22186bool isVRCPSS(unsigned Opcode) {
22187 switch (Opcode) {
22188 case VRCPSSm_Int:
22189 case VRCPSSr_Int:
22190 return true;
22191 }
22192 return false;
22193}
22194
22195bool isVSCATTERPF1DPS(unsigned Opcode) {
22196 return Opcode == VSCATTERPF1DPSm;
22197}
22198
22199bool isVPHADDUBW(unsigned Opcode) {
22200 switch (Opcode) {
22201 case VPHADDUBWrm:
22202 case VPHADDUBWrr:
22203 return true;
22204 }
22205 return false;
22206}
22207
22208bool isVSUBPD(unsigned Opcode) {
22209 switch (Opcode) {
22210 case VSUBPDYrm:
22211 case VSUBPDYrr:
22212 case VSUBPDZ128rm:
22213 case VSUBPDZ128rmb:
22214 case VSUBPDZ128rmbk:
22215 case VSUBPDZ128rmbkz:
22216 case VSUBPDZ128rmk:
22217 case VSUBPDZ128rmkz:
22218 case VSUBPDZ128rr:
22219 case VSUBPDZ128rrk:
22220 case VSUBPDZ128rrkz:
22221 case VSUBPDZ256rm:
22222 case VSUBPDZ256rmb:
22223 case VSUBPDZ256rmbk:
22224 case VSUBPDZ256rmbkz:
22225 case VSUBPDZ256rmk:
22226 case VSUBPDZ256rmkz:
22227 case VSUBPDZ256rr:
22228 case VSUBPDZ256rrk:
22229 case VSUBPDZ256rrkz:
22230 case VSUBPDZrm:
22231 case VSUBPDZrmb:
22232 case VSUBPDZrmbk:
22233 case VSUBPDZrmbkz:
22234 case VSUBPDZrmk:
22235 case VSUBPDZrmkz:
22236 case VSUBPDZrr:
22237 case VSUBPDZrrb:
22238 case VSUBPDZrrbk:
22239 case VSUBPDZrrbkz:
22240 case VSUBPDZrrk:
22241 case VSUBPDZrrkz:
22242 case VSUBPDrm:
22243 case VSUBPDrr:
22244 return true;
22245 }
22246 return false;
22247}
22248
22249bool isVPSCATTERQQ(unsigned Opcode) {
22250 switch (Opcode) {
22251 case VPSCATTERQQZ128mr:
22252 case VPSCATTERQQZ256mr:
22253 case VPSCATTERQQZmr:
22254 return true;
22255 }
22256 return false;
22257}
22258
22259bool isVCVTW2PH(unsigned Opcode) {
22260 switch (Opcode) {
22261 case VCVTW2PHZ128rm:
22262 case VCVTW2PHZ128rmb:
22263 case VCVTW2PHZ128rmbk:
22264 case VCVTW2PHZ128rmbkz:
22265 case VCVTW2PHZ128rmk:
22266 case VCVTW2PHZ128rmkz:
22267 case VCVTW2PHZ128rr:
22268 case VCVTW2PHZ128rrk:
22269 case VCVTW2PHZ128rrkz:
22270 case VCVTW2PHZ256rm:
22271 case VCVTW2PHZ256rmb:
22272 case VCVTW2PHZ256rmbk:
22273 case VCVTW2PHZ256rmbkz:
22274 case VCVTW2PHZ256rmk:
22275 case VCVTW2PHZ256rmkz:
22276 case VCVTW2PHZ256rr:
22277 case VCVTW2PHZ256rrk:
22278 case VCVTW2PHZ256rrkz:
22279 case VCVTW2PHZrm:
22280 case VCVTW2PHZrmb:
22281 case VCVTW2PHZrmbk:
22282 case VCVTW2PHZrmbkz:
22283 case VCVTW2PHZrmk:
22284 case VCVTW2PHZrmkz:
22285 case VCVTW2PHZrr:
22286 case VCVTW2PHZrrb:
22287 case VCVTW2PHZrrbk:
22288 case VCVTW2PHZrrbkz:
22289 case VCVTW2PHZrrk:
22290 case VCVTW2PHZrrkz:
22291 return true;
22292 }
22293 return false;
22294}
22295
22296bool isVFMADDCPH(unsigned Opcode) {
22297 switch (Opcode) {
22298 case VFMADDCPHZ128m:
22299 case VFMADDCPHZ128mb:
22300 case VFMADDCPHZ128mbk:
22301 case VFMADDCPHZ128mbkz:
22302 case VFMADDCPHZ128mk:
22303 case VFMADDCPHZ128mkz:
22304 case VFMADDCPHZ128r:
22305 case VFMADDCPHZ128rk:
22306 case VFMADDCPHZ128rkz:
22307 case VFMADDCPHZ256m:
22308 case VFMADDCPHZ256mb:
22309 case VFMADDCPHZ256mbk:
22310 case VFMADDCPHZ256mbkz:
22311 case VFMADDCPHZ256mk:
22312 case VFMADDCPHZ256mkz:
22313 case VFMADDCPHZ256r:
22314 case VFMADDCPHZ256rk:
22315 case VFMADDCPHZ256rkz:
22316 case VFMADDCPHZm:
22317 case VFMADDCPHZmb:
22318 case VFMADDCPHZmbk:
22319 case VFMADDCPHZmbkz:
22320 case VFMADDCPHZmk:
22321 case VFMADDCPHZmkz:
22322 case VFMADDCPHZr:
22323 case VFMADDCPHZrb:
22324 case VFMADDCPHZrbk:
22325 case VFMADDCPHZrbkz:
22326 case VFMADDCPHZrk:
22327 case VFMADDCPHZrkz:
22328 return true;
22329 }
22330 return false;
22331}
22332
22333bool isVPACKUSDW(unsigned Opcode) {
22334 switch (Opcode) {
22335 case VPACKUSDWYrm:
22336 case VPACKUSDWYrr:
22337 case VPACKUSDWZ128rm:
22338 case VPACKUSDWZ128rmb:
22339 case VPACKUSDWZ128rmbk:
22340 case VPACKUSDWZ128rmbkz:
22341 case VPACKUSDWZ128rmk:
22342 case VPACKUSDWZ128rmkz:
22343 case VPACKUSDWZ128rr:
22344 case VPACKUSDWZ128rrk:
22345 case VPACKUSDWZ128rrkz:
22346 case VPACKUSDWZ256rm:
22347 case VPACKUSDWZ256rmb:
22348 case VPACKUSDWZ256rmbk:
22349 case VPACKUSDWZ256rmbkz:
22350 case VPACKUSDWZ256rmk:
22351 case VPACKUSDWZ256rmkz:
22352 case VPACKUSDWZ256rr:
22353 case VPACKUSDWZ256rrk:
22354 case VPACKUSDWZ256rrkz:
22355 case VPACKUSDWZrm:
22356 case VPACKUSDWZrmb:
22357 case VPACKUSDWZrmbk:
22358 case VPACKUSDWZrmbkz:
22359 case VPACKUSDWZrmk:
22360 case VPACKUSDWZrmkz:
22361 case VPACKUSDWZrr:
22362 case VPACKUSDWZrrk:
22363 case VPACKUSDWZrrkz:
22364 case VPACKUSDWrm:
22365 case VPACKUSDWrr:
22366 return true;
22367 }
22368 return false;
22369}
22370
22371bool isVSCALEFSS(unsigned Opcode) {
22372 switch (Opcode) {
22373 case VSCALEFSSZrm:
22374 case VSCALEFSSZrmk:
22375 case VSCALEFSSZrmkz:
22376 case VSCALEFSSZrr:
22377 case VSCALEFSSZrrb_Int:
22378 case VSCALEFSSZrrbk_Int:
22379 case VSCALEFSSZrrbkz_Int:
22380 case VSCALEFSSZrrk:
22381 case VSCALEFSSZrrkz:
22382 return true;
22383 }
22384 return false;
22385}
22386
22387bool isAESIMC(unsigned Opcode) {
22388 switch (Opcode) {
22389 case AESIMCrm:
22390 case AESIMCrr:
22391 return true;
22392 }
22393 return false;
22394}
22395
22396bool isVRCP28PS(unsigned Opcode) {
22397 switch (Opcode) {
22398 case VRCP28PSZm:
22399 case VRCP28PSZmb:
22400 case VRCP28PSZmbk:
22401 case VRCP28PSZmbkz:
22402 case VRCP28PSZmk:
22403 case VRCP28PSZmkz:
22404 case VRCP28PSZr:
22405 case VRCP28PSZrb:
22406 case VRCP28PSZrbk:
22407 case VRCP28PSZrbkz:
22408 case VRCP28PSZrk:
22409 case VRCP28PSZrkz:
22410 return true;
22411 }
22412 return false;
22413}
22414
22415bool isAAND(unsigned Opcode) {
22416 switch (Opcode) {
22417 case AAND32mr:
22418 case AAND32mr_EVEX:
22419 case AAND64mr:
22420 case AAND64mr_EVEX:
22421 return true;
22422 }
22423 return false;
22424}
22425
22426bool isDAA(unsigned Opcode) {
22427 return Opcode == DAA;
22428}
22429
22430bool isKTESTW(unsigned Opcode) {
22431 return Opcode == KTESTWkk;
22432}
22433
22434bool isVCVTPD2UDQ(unsigned Opcode) {
22435 switch (Opcode) {
22436 case VCVTPD2UDQZ128rm:
22437 case VCVTPD2UDQZ128rmb:
22438 case VCVTPD2UDQZ128rmbk:
22439 case VCVTPD2UDQZ128rmbkz:
22440 case VCVTPD2UDQZ128rmk:
22441 case VCVTPD2UDQZ128rmkz:
22442 case VCVTPD2UDQZ128rr:
22443 case VCVTPD2UDQZ128rrk:
22444 case VCVTPD2UDQZ128rrkz:
22445 case VCVTPD2UDQZ256rm:
22446 case VCVTPD2UDQZ256rmb:
22447 case VCVTPD2UDQZ256rmbk:
22448 case VCVTPD2UDQZ256rmbkz:
22449 case VCVTPD2UDQZ256rmk:
22450 case VCVTPD2UDQZ256rmkz:
22451 case VCVTPD2UDQZ256rr:
22452 case VCVTPD2UDQZ256rrk:
22453 case VCVTPD2UDQZ256rrkz:
22454 case VCVTPD2UDQZrm:
22455 case VCVTPD2UDQZrmb:
22456 case VCVTPD2UDQZrmbk:
22457 case VCVTPD2UDQZrmbkz:
22458 case VCVTPD2UDQZrmk:
22459 case VCVTPD2UDQZrmkz:
22460 case VCVTPD2UDQZrr:
22461 case VCVTPD2UDQZrrb:
22462 case VCVTPD2UDQZrrbk:
22463 case VCVTPD2UDQZrrbkz:
22464 case VCVTPD2UDQZrrk:
22465 case VCVTPD2UDQZrrkz:
22466 return true;
22467 }
22468 return false;
22469}
22470
22471bool isVPADDQ(unsigned Opcode) {
22472 switch (Opcode) {
22473 case VPADDQYrm:
22474 case VPADDQYrr:
22475 case VPADDQZ128rm:
22476 case VPADDQZ128rmb:
22477 case VPADDQZ128rmbk:
22478 case VPADDQZ128rmbkz:
22479 case VPADDQZ128rmk:
22480 case VPADDQZ128rmkz:
22481 case VPADDQZ128rr:
22482 case VPADDQZ128rrk:
22483 case VPADDQZ128rrkz:
22484 case VPADDQZ256rm:
22485 case VPADDQZ256rmb:
22486 case VPADDQZ256rmbk:
22487 case VPADDQZ256rmbkz:
22488 case VPADDQZ256rmk:
22489 case VPADDQZ256rmkz:
22490 case VPADDQZ256rr:
22491 case VPADDQZ256rrk:
22492 case VPADDQZ256rrkz:
22493 case VPADDQZrm:
22494 case VPADDQZrmb:
22495 case VPADDQZrmbk:
22496 case VPADDQZrmbkz:
22497 case VPADDQZrmk:
22498 case VPADDQZrmkz:
22499 case VPADDQZrr:
22500 case VPADDQZrrk:
22501 case VPADDQZrrkz:
22502 case VPADDQrm:
22503 case VPADDQrr:
22504 return true;
22505 }
22506 return false;
22507}
22508
22509bool isPALIGNR(unsigned Opcode) {
22510 switch (Opcode) {
22511 case MMX_PALIGNRrmi:
22512 case MMX_PALIGNRrri:
22513 case PALIGNRrmi:
22514 case PALIGNRrri:
22515 return true;
22516 }
22517 return false;
22518}
22519
22520bool isPMAXUW(unsigned Opcode) {
22521 switch (Opcode) {
22522 case PMAXUWrm:
22523 case PMAXUWrr:
22524 return true;
22525 }
22526 return false;
22527}
22528
22529bool isVFMADDSD(unsigned Opcode) {
22530 switch (Opcode) {
22531 case VFMADDSD4mr:
22532 case VFMADDSD4rm:
22533 case VFMADDSD4rr:
22534 case VFMADDSD4rr_REV:
22535 return true;
22536 }
22537 return false;
22538}
22539
22540bool isPFMAX(unsigned Opcode) {
22541 switch (Opcode) {
22542 case PFMAXrm:
22543 case PFMAXrr:
22544 return true;
22545 }
22546 return false;
22547}
22548
22549bool isVPOR(unsigned Opcode) {
22550 switch (Opcode) {
22551 case VPORYrm:
22552 case VPORYrr:
22553 case VPORrm:
22554 case VPORrr:
22555 return true;
22556 }
22557 return false;
22558}
22559
22560bool isVPSUBB(unsigned Opcode) {
22561 switch (Opcode) {
22562 case VPSUBBYrm:
22563 case VPSUBBYrr:
22564 case VPSUBBZ128rm:
22565 case VPSUBBZ128rmk:
22566 case VPSUBBZ128rmkz:
22567 case VPSUBBZ128rr:
22568 case VPSUBBZ128rrk:
22569 case VPSUBBZ128rrkz:
22570 case VPSUBBZ256rm:
22571 case VPSUBBZ256rmk:
22572 case VPSUBBZ256rmkz:
22573 case VPSUBBZ256rr:
22574 case VPSUBBZ256rrk:
22575 case VPSUBBZ256rrkz:
22576 case VPSUBBZrm:
22577 case VPSUBBZrmk:
22578 case VPSUBBZrmkz:
22579 case VPSUBBZrr:
22580 case VPSUBBZrrk:
22581 case VPSUBBZrrkz:
22582 case VPSUBBrm:
22583 case VPSUBBrr:
22584 return true;
22585 }
22586 return false;
22587}
22588
22589bool isVPAVGB(unsigned Opcode) {
22590 switch (Opcode) {
22591 case VPAVGBYrm:
22592 case VPAVGBYrr:
22593 case VPAVGBZ128rm:
22594 case VPAVGBZ128rmk:
22595 case VPAVGBZ128rmkz:
22596 case VPAVGBZ128rr:
22597 case VPAVGBZ128rrk:
22598 case VPAVGBZ128rrkz:
22599 case VPAVGBZ256rm:
22600 case VPAVGBZ256rmk:
22601 case VPAVGBZ256rmkz:
22602 case VPAVGBZ256rr:
22603 case VPAVGBZ256rrk:
22604 case VPAVGBZ256rrkz:
22605 case VPAVGBZrm:
22606 case VPAVGBZrmk:
22607 case VPAVGBZrmkz:
22608 case VPAVGBZrr:
22609 case VPAVGBZrrk:
22610 case VPAVGBZrrkz:
22611 case VPAVGBrm:
22612 case VPAVGBrr:
22613 return true;
22614 }
22615 return false;
22616}
22617
22618bool isINSB(unsigned Opcode) {
22619 return Opcode == INSB;
22620}
22621
22622bool isFYL2X(unsigned Opcode) {
22623 return Opcode == FYL2X;
22624}
22625
22626bool isVFNMSUB132PD(unsigned Opcode) {
22627 switch (Opcode) {
22628 case VFNMSUB132PDYm:
22629 case VFNMSUB132PDYr:
22630 case VFNMSUB132PDZ128m:
22631 case VFNMSUB132PDZ128mb:
22632 case VFNMSUB132PDZ128mbk:
22633 case VFNMSUB132PDZ128mbkz:
22634 case VFNMSUB132PDZ128mk:
22635 case VFNMSUB132PDZ128mkz:
22636 case VFNMSUB132PDZ128r:
22637 case VFNMSUB132PDZ128rk:
22638 case VFNMSUB132PDZ128rkz:
22639 case VFNMSUB132PDZ256m:
22640 case VFNMSUB132PDZ256mb:
22641 case VFNMSUB132PDZ256mbk:
22642 case VFNMSUB132PDZ256mbkz:
22643 case VFNMSUB132PDZ256mk:
22644 case VFNMSUB132PDZ256mkz:
22645 case VFNMSUB132PDZ256r:
22646 case VFNMSUB132PDZ256rk:
22647 case VFNMSUB132PDZ256rkz:
22648 case VFNMSUB132PDZm:
22649 case VFNMSUB132PDZmb:
22650 case VFNMSUB132PDZmbk:
22651 case VFNMSUB132PDZmbkz:
22652 case VFNMSUB132PDZmk:
22653 case VFNMSUB132PDZmkz:
22654 case VFNMSUB132PDZr:
22655 case VFNMSUB132PDZrb:
22656 case VFNMSUB132PDZrbk:
22657 case VFNMSUB132PDZrbkz:
22658 case VFNMSUB132PDZrk:
22659 case VFNMSUB132PDZrkz:
22660 case VFNMSUB132PDm:
22661 case VFNMSUB132PDr:
22662 return true;
22663 }
22664 return false;
22665}
22666
22667bool isVFNMSUBPS(unsigned Opcode) {
22668 switch (Opcode) {
22669 case VFNMSUBPS4Ymr:
22670 case VFNMSUBPS4Yrm:
22671 case VFNMSUBPS4Yrr:
22672 case VFNMSUBPS4Yrr_REV:
22673 case VFNMSUBPS4mr:
22674 case VFNMSUBPS4rm:
22675 case VFNMSUBPS4rr:
22676 case VFNMSUBPS4rr_REV:
22677 return true;
22678 }
22679 return false;
22680}
22681
22682bool isVFMADD231PS(unsigned Opcode) {
22683 switch (Opcode) {
22684 case VFMADD231PSYm:
22685 case VFMADD231PSYr:
22686 case VFMADD231PSZ128m:
22687 case VFMADD231PSZ128mb:
22688 case VFMADD231PSZ128mbk:
22689 case VFMADD231PSZ128mbkz:
22690 case VFMADD231PSZ128mk:
22691 case VFMADD231PSZ128mkz:
22692 case VFMADD231PSZ128r:
22693 case VFMADD231PSZ128rk:
22694 case VFMADD231PSZ128rkz:
22695 case VFMADD231PSZ256m:
22696 case VFMADD231PSZ256mb:
22697 case VFMADD231PSZ256mbk:
22698 case VFMADD231PSZ256mbkz:
22699 case VFMADD231PSZ256mk:
22700 case VFMADD231PSZ256mkz:
22701 case VFMADD231PSZ256r:
22702 case VFMADD231PSZ256rk:
22703 case VFMADD231PSZ256rkz:
22704 case VFMADD231PSZm:
22705 case VFMADD231PSZmb:
22706 case VFMADD231PSZmbk:
22707 case VFMADD231PSZmbkz:
22708 case VFMADD231PSZmk:
22709 case VFMADD231PSZmkz:
22710 case VFMADD231PSZr:
22711 case VFMADD231PSZrb:
22712 case VFMADD231PSZrbk:
22713 case VFMADD231PSZrbkz:
22714 case VFMADD231PSZrk:
22715 case VFMADD231PSZrkz:
22716 case VFMADD231PSm:
22717 case VFMADD231PSr:
22718 return true;
22719 }
22720 return false;
22721}
22722
22723bool isVCVTTSS2SI(unsigned Opcode) {
22724 switch (Opcode) {
22725 case VCVTTSS2SI64Zrm_Int:
22726 case VCVTTSS2SI64Zrr_Int:
22727 case VCVTTSS2SI64Zrrb_Int:
22728 case VCVTTSS2SI64rm_Int:
22729 case VCVTTSS2SI64rr_Int:
22730 case VCVTTSS2SIZrm_Int:
22731 case VCVTTSS2SIZrr_Int:
22732 case VCVTTSS2SIZrrb_Int:
22733 case VCVTTSS2SIrm_Int:
22734 case VCVTTSS2SIrr_Int:
22735 return true;
22736 }
22737 return false;
22738}
22739
22740bool isTCMMRLFP16PS(unsigned Opcode) {
22741 return Opcode == TCMMRLFP16PS;
22742}
22743
22744bool isFCOMPP(unsigned Opcode) {
22745 return Opcode == FCOMPP;
22746}
22747
22748bool isMOVD(unsigned Opcode) {
22749 switch (Opcode) {
22750 case MMX_MOVD64grr:
22751 case MMX_MOVD64mr:
22752 case MMX_MOVD64rm:
22753 case MMX_MOVD64rr:
22754 case MOVDI2PDIrm:
22755 case MOVDI2PDIrr:
22756 case MOVPDI2DImr:
22757 case MOVPDI2DIrr:
22758 return true;
22759 }
22760 return false;
22761}
22762
22763bool isMOVBE(unsigned Opcode) {
22764 switch (Opcode) {
22765 case MOVBE16mr:
22766 case MOVBE16mr_EVEX:
22767 case MOVBE16rm:
22768 case MOVBE16rm_EVEX:
22769 case MOVBE16rr:
22770 case MOVBE16rr_REV:
22771 case MOVBE32mr:
22772 case MOVBE32mr_EVEX:
22773 case MOVBE32rm:
22774 case MOVBE32rm_EVEX:
22775 case MOVBE32rr:
22776 case MOVBE32rr_REV:
22777 case MOVBE64mr:
22778 case MOVBE64mr_EVEX:
22779 case MOVBE64rm:
22780 case MOVBE64rm_EVEX:
22781 case MOVBE64rr:
22782 case MOVBE64rr_REV:
22783 return true;
22784 }
22785 return false;
22786}
22787
22788bool isVP2INTERSECTD(unsigned Opcode) {
22789 switch (Opcode) {
22790 case VP2INTERSECTDZ128rm:
22791 case VP2INTERSECTDZ128rmb:
22792 case VP2INTERSECTDZ128rr:
22793 case VP2INTERSECTDZ256rm:
22794 case VP2INTERSECTDZ256rmb:
22795 case VP2INTERSECTDZ256rr:
22796 case VP2INTERSECTDZrm:
22797 case VP2INTERSECTDZrmb:
22798 case VP2INTERSECTDZrr:
22799 return true;
22800 }
22801 return false;
22802}
22803
22804bool isVPMULLQ(unsigned Opcode) {
22805 switch (Opcode) {
22806 case VPMULLQZ128rm:
22807 case VPMULLQZ128rmb:
22808 case VPMULLQZ128rmbk:
22809 case VPMULLQZ128rmbkz:
22810 case VPMULLQZ128rmk:
22811 case VPMULLQZ128rmkz:
22812 case VPMULLQZ128rr:
22813 case VPMULLQZ128rrk:
22814 case VPMULLQZ128rrkz:
22815 case VPMULLQZ256rm:
22816 case VPMULLQZ256rmb:
22817 case VPMULLQZ256rmbk:
22818 case VPMULLQZ256rmbkz:
22819 case VPMULLQZ256rmk:
22820 case VPMULLQZ256rmkz:
22821 case VPMULLQZ256rr:
22822 case VPMULLQZ256rrk:
22823 case VPMULLQZ256rrkz:
22824 case VPMULLQZrm:
22825 case VPMULLQZrmb:
22826 case VPMULLQZrmbk:
22827 case VPMULLQZrmbkz:
22828 case VPMULLQZrmk:
22829 case VPMULLQZrmkz:
22830 case VPMULLQZrr:
22831 case VPMULLQZrrk:
22832 case VPMULLQZrrkz:
22833 return true;
22834 }
22835 return false;
22836}
22837
22838bool isVSCALEFPS(unsigned Opcode) {
22839 switch (Opcode) {
22840 case VSCALEFPSZ128rm:
22841 case VSCALEFPSZ128rmb:
22842 case VSCALEFPSZ128rmbk:
22843 case VSCALEFPSZ128rmbkz:
22844 case VSCALEFPSZ128rmk:
22845 case VSCALEFPSZ128rmkz:
22846 case VSCALEFPSZ128rr:
22847 case VSCALEFPSZ128rrk:
22848 case VSCALEFPSZ128rrkz:
22849 case VSCALEFPSZ256rm:
22850 case VSCALEFPSZ256rmb:
22851 case VSCALEFPSZ256rmbk:
22852 case VSCALEFPSZ256rmbkz:
22853 case VSCALEFPSZ256rmk:
22854 case VSCALEFPSZ256rmkz:
22855 case VSCALEFPSZ256rr:
22856 case VSCALEFPSZ256rrk:
22857 case VSCALEFPSZ256rrkz:
22858 case VSCALEFPSZrm:
22859 case VSCALEFPSZrmb:
22860 case VSCALEFPSZrmbk:
22861 case VSCALEFPSZrmbkz:
22862 case VSCALEFPSZrmk:
22863 case VSCALEFPSZrmkz:
22864 case VSCALEFPSZrr:
22865 case VSCALEFPSZrrb:
22866 case VSCALEFPSZrrbk:
22867 case VSCALEFPSZrrbkz:
22868 case VSCALEFPSZrrk:
22869 case VSCALEFPSZrrkz:
22870 return true;
22871 }
22872 return false;
22873}
22874
22875bool isVPMACSDQH(unsigned Opcode) {
22876 switch (Opcode) {
22877 case VPMACSDQHrm:
22878 case VPMACSDQHrr:
22879 return true;
22880 }
22881 return false;
22882}
22883
22884bool isVPTESTNMD(unsigned Opcode) {
22885 switch (Opcode) {
22886 case VPTESTNMDZ128rm:
22887 case VPTESTNMDZ128rmb:
22888 case VPTESTNMDZ128rmbk:
22889 case VPTESTNMDZ128rmk:
22890 case VPTESTNMDZ128rr:
22891 case VPTESTNMDZ128rrk:
22892 case VPTESTNMDZ256rm:
22893 case VPTESTNMDZ256rmb:
22894 case VPTESTNMDZ256rmbk:
22895 case VPTESTNMDZ256rmk:
22896 case VPTESTNMDZ256rr:
22897 case VPTESTNMDZ256rrk:
22898 case VPTESTNMDZrm:
22899 case VPTESTNMDZrmb:
22900 case VPTESTNMDZrmbk:
22901 case VPTESTNMDZrmk:
22902 case VPTESTNMDZrr:
22903 case VPTESTNMDZrrk:
22904 return true;
22905 }
22906 return false;
22907}
22908
22909bool isFCOMP(unsigned Opcode) {
22910 switch (Opcode) {
22911 case COMP_FST0r:
22912 case FCOMP32m:
22913 case FCOMP64m:
22914 return true;
22915 }
22916 return false;
22917}
22918
22919bool isPREFETCHWT1(unsigned Opcode) {
22920 return Opcode == PREFETCHWT1;
22921}
22922
22923bool isVCMPSD(unsigned Opcode) {
22924 switch (Opcode) {
22925 case VCMPSDZrmi_Int:
22926 case VCMPSDZrmik_Int:
22927 case VCMPSDZrri_Int:
22928 case VCMPSDZrrib_Int:
22929 case VCMPSDZrribk_Int:
22930 case VCMPSDZrrik_Int:
22931 case VCMPSDrmi_Int:
22932 case VCMPSDrri_Int:
22933 return true;
22934 }
22935 return false;
22936}
22937
22938bool isSGDTD(unsigned Opcode) {
22939 return Opcode == SGDT32m;
22940}
22941
22942bool isWRUSSD(unsigned Opcode) {
22943 switch (Opcode) {
22944 case WRUSSD:
22945 case WRUSSD_EVEX:
22946 return true;
22947 }
22948 return false;
22949}
22950
22951bool isFSUBP(unsigned Opcode) {
22952 return Opcode == SUB_FPrST0;
22953}
22954
22955bool isVUNPCKLPS(unsigned Opcode) {
22956 switch (Opcode) {
22957 case VUNPCKLPSYrm:
22958 case VUNPCKLPSYrr:
22959 case VUNPCKLPSZ128rm:
22960 case VUNPCKLPSZ128rmb:
22961 case VUNPCKLPSZ128rmbk:
22962 case VUNPCKLPSZ128rmbkz:
22963 case VUNPCKLPSZ128rmk:
22964 case VUNPCKLPSZ128rmkz:
22965 case VUNPCKLPSZ128rr:
22966 case VUNPCKLPSZ128rrk:
22967 case VUNPCKLPSZ128rrkz:
22968 case VUNPCKLPSZ256rm:
22969 case VUNPCKLPSZ256rmb:
22970 case VUNPCKLPSZ256rmbk:
22971 case VUNPCKLPSZ256rmbkz:
22972 case VUNPCKLPSZ256rmk:
22973 case VUNPCKLPSZ256rmkz:
22974 case VUNPCKLPSZ256rr:
22975 case VUNPCKLPSZ256rrk:
22976 case VUNPCKLPSZ256rrkz:
22977 case VUNPCKLPSZrm:
22978 case VUNPCKLPSZrmb:
22979 case VUNPCKLPSZrmbk:
22980 case VUNPCKLPSZrmbkz:
22981 case VUNPCKLPSZrmk:
22982 case VUNPCKLPSZrmkz:
22983 case VUNPCKLPSZrr:
22984 case VUNPCKLPSZrrk:
22985 case VUNPCKLPSZrrkz:
22986 case VUNPCKLPSrm:
22987 case VUNPCKLPSrr:
22988 return true;
22989 }
22990 return false;
22991}
22992
22993bool isVBMACXOR16X16X16(unsigned Opcode) {
22994 switch (Opcode) {
22995 case VBMACXORZ256rm:
22996 case VBMACXORZ256rmb:
22997 case VBMACXORZ256rmbk:
22998 case VBMACXORZ256rmbkz:
22999 case VBMACXORZ256rmk:
23000 case VBMACXORZ256rmkz:
23001 case VBMACXORZ256rr:
23002 case VBMACXORZ256rrk:
23003 case VBMACXORZ256rrkz:
23004 case VBMACXORZrm:
23005 case VBMACXORZrmb:
23006 case VBMACXORZrmbk:
23007 case VBMACXORZrmbkz:
23008 case VBMACXORZrmk:
23009 case VBMACXORZrmkz:
23010 case VBMACXORZrr:
23011 case VBMACXORZrrk:
23012 case VBMACXORZrrkz:
23013 return true;
23014 }
23015 return false;
23016}
23017
23018bool isVFNMSUB213SS(unsigned Opcode) {
23019 switch (Opcode) {
23020 case VFNMSUB213SSZm_Int:
23021 case VFNMSUB213SSZmk_Int:
23022 case VFNMSUB213SSZmkz_Int:
23023 case VFNMSUB213SSZr_Int:
23024 case VFNMSUB213SSZrb_Int:
23025 case VFNMSUB213SSZrbk_Int:
23026 case VFNMSUB213SSZrbkz_Int:
23027 case VFNMSUB213SSZrk_Int:
23028 case VFNMSUB213SSZrkz_Int:
23029 case VFNMSUB213SSm_Int:
23030 case VFNMSUB213SSr_Int:
23031 return true;
23032 }
23033 return false;
23034}
23035
23036bool isROUNDPD(unsigned Opcode) {
23037 switch (Opcode) {
23038 case ROUNDPDmi:
23039 case ROUNDPDri:
23040 return true;
23041 }
23042 return false;
23043}
23044
23045bool isVPMAXSW(unsigned Opcode) {
23046 switch (Opcode) {
23047 case VPMAXSWYrm:
23048 case VPMAXSWYrr:
23049 case VPMAXSWZ128rm:
23050 case VPMAXSWZ128rmk:
23051 case VPMAXSWZ128rmkz:
23052 case VPMAXSWZ128rr:
23053 case VPMAXSWZ128rrk:
23054 case VPMAXSWZ128rrkz:
23055 case VPMAXSWZ256rm:
23056 case VPMAXSWZ256rmk:
23057 case VPMAXSWZ256rmkz:
23058 case VPMAXSWZ256rr:
23059 case VPMAXSWZ256rrk:
23060 case VPMAXSWZ256rrkz:
23061 case VPMAXSWZrm:
23062 case VPMAXSWZrmk:
23063 case VPMAXSWZrmkz:
23064 case VPMAXSWZrr:
23065 case VPMAXSWZrrk:
23066 case VPMAXSWZrrkz:
23067 case VPMAXSWrm:
23068 case VPMAXSWrr:
23069 return true;
23070 }
23071 return false;
23072}
23073
23074bool isVCVTTPH2DQ(unsigned Opcode) {
23075 switch (Opcode) {
23076 case VCVTTPH2DQZ128rm:
23077 case VCVTTPH2DQZ128rmb:
23078 case VCVTTPH2DQZ128rmbk:
23079 case VCVTTPH2DQZ128rmbkz:
23080 case VCVTTPH2DQZ128rmk:
23081 case VCVTTPH2DQZ128rmkz:
23082 case VCVTTPH2DQZ128rr:
23083 case VCVTTPH2DQZ128rrk:
23084 case VCVTTPH2DQZ128rrkz:
23085 case VCVTTPH2DQZ256rm:
23086 case VCVTTPH2DQZ256rmb:
23087 case VCVTTPH2DQZ256rmbk:
23088 case VCVTTPH2DQZ256rmbkz:
23089 case VCVTTPH2DQZ256rmk:
23090 case VCVTTPH2DQZ256rmkz:
23091 case VCVTTPH2DQZ256rr:
23092 case VCVTTPH2DQZ256rrk:
23093 case VCVTTPH2DQZ256rrkz:
23094 case VCVTTPH2DQZrm:
23095 case VCVTTPH2DQZrmb:
23096 case VCVTTPH2DQZrmbk:
23097 case VCVTTPH2DQZrmbkz:
23098 case VCVTTPH2DQZrmk:
23099 case VCVTTPH2DQZrmkz:
23100 case VCVTTPH2DQZrr:
23101 case VCVTTPH2DQZrrb:
23102 case VCVTTPH2DQZrrbk:
23103 case VCVTTPH2DQZrrbkz:
23104 case VCVTTPH2DQZrrk:
23105 case VCVTTPH2DQZrrkz:
23106 return true;
23107 }
23108 return false;
23109}
23110
23111bool isVPUNPCKLWD(unsigned Opcode) {
23112 switch (Opcode) {
23113 case VPUNPCKLWDYrm:
23114 case VPUNPCKLWDYrr:
23115 case VPUNPCKLWDZ128rm:
23116 case VPUNPCKLWDZ128rmk:
23117 case VPUNPCKLWDZ128rmkz:
23118 case VPUNPCKLWDZ128rr:
23119 case VPUNPCKLWDZ128rrk:
23120 case VPUNPCKLWDZ128rrkz:
23121 case VPUNPCKLWDZ256rm:
23122 case VPUNPCKLWDZ256rmk:
23123 case VPUNPCKLWDZ256rmkz:
23124 case VPUNPCKLWDZ256rr:
23125 case VPUNPCKLWDZ256rrk:
23126 case VPUNPCKLWDZ256rrkz:
23127 case VPUNPCKLWDZrm:
23128 case VPUNPCKLWDZrmk:
23129 case VPUNPCKLWDZrmkz:
23130 case VPUNPCKLWDZrr:
23131 case VPUNPCKLWDZrrk:
23132 case VPUNPCKLWDZrrkz:
23133 case VPUNPCKLWDrm:
23134 case VPUNPCKLWDrr:
23135 return true;
23136 }
23137 return false;
23138}
23139
23140bool isKSHIFTLD(unsigned Opcode) {
23141 return Opcode == KSHIFTLDki;
23142}
23143
23144bool isTCVTROWPS2BF16H(unsigned Opcode) {
23145 switch (Opcode) {
23146 case TCVTROWPS2BF16Hrte:
23147 case TCVTROWPS2BF16Hrti:
23148 return true;
23149 }
23150 return false;
23151}
23152
23153bool isVFMADD231SD(unsigned Opcode) {
23154 switch (Opcode) {
23155 case VFMADD231SDZm_Int:
23156 case VFMADD231SDZmk_Int:
23157 case VFMADD231SDZmkz_Int:
23158 case VFMADD231SDZr_Int:
23159 case VFMADD231SDZrb_Int:
23160 case VFMADD231SDZrbk_Int:
23161 case VFMADD231SDZrbkz_Int:
23162 case VFMADD231SDZrk_Int:
23163 case VFMADD231SDZrkz_Int:
23164 case VFMADD231SDm_Int:
23165 case VFMADD231SDr_Int:
23166 return true;
23167 }
23168 return false;
23169}
23170
23171bool isADDPS(unsigned Opcode) {
23172 switch (Opcode) {
23173 case ADDPSrm:
23174 case ADDPSrr:
23175 return true;
23176 }
23177 return false;
23178}
23179
23180bool isVPSLLVD(unsigned Opcode) {
23181 switch (Opcode) {
23182 case VPSLLVDYrm:
23183 case VPSLLVDYrr:
23184 case VPSLLVDZ128rm:
23185 case VPSLLVDZ128rmb:
23186 case VPSLLVDZ128rmbk:
23187 case VPSLLVDZ128rmbkz:
23188 case VPSLLVDZ128rmk:
23189 case VPSLLVDZ128rmkz:
23190 case VPSLLVDZ128rr:
23191 case VPSLLVDZ128rrk:
23192 case VPSLLVDZ128rrkz:
23193 case VPSLLVDZ256rm:
23194 case VPSLLVDZ256rmb:
23195 case VPSLLVDZ256rmbk:
23196 case VPSLLVDZ256rmbkz:
23197 case VPSLLVDZ256rmk:
23198 case VPSLLVDZ256rmkz:
23199 case VPSLLVDZ256rr:
23200 case VPSLLVDZ256rrk:
23201 case VPSLLVDZ256rrkz:
23202 case VPSLLVDZrm:
23203 case VPSLLVDZrmb:
23204 case VPSLLVDZrmbk:
23205 case VPSLLVDZrmbkz:
23206 case VPSLLVDZrmk:
23207 case VPSLLVDZrmkz:
23208 case VPSLLVDZrr:
23209 case VPSLLVDZrrk:
23210 case VPSLLVDZrrkz:
23211 case VPSLLVDrm:
23212 case VPSLLVDrr:
23213 return true;
23214 }
23215 return false;
23216}
23217
23218bool isVFNMADD132SH(unsigned Opcode) {
23219 switch (Opcode) {
23220 case VFNMADD132SHZm_Int:
23221 case VFNMADD132SHZmk_Int:
23222 case VFNMADD132SHZmkz_Int:
23223 case VFNMADD132SHZr_Int:
23224 case VFNMADD132SHZrb_Int:
23225 case VFNMADD132SHZrbk_Int:
23226 case VFNMADD132SHZrbkz_Int:
23227 case VFNMADD132SHZrk_Int:
23228 case VFNMADD132SHZrkz_Int:
23229 return true;
23230 }
23231 return false;
23232}
23233
23234bool isVMOVNTPS(unsigned Opcode) {
23235 switch (Opcode) {
23236 case VMOVNTPSYmr:
23237 case VMOVNTPSZ128mr:
23238 case VMOVNTPSZ256mr:
23239 case VMOVNTPSZmr:
23240 case VMOVNTPSmr:
23241 return true;
23242 }
23243 return false;
23244}
23245
23246bool isVCVTPD2DQ(unsigned Opcode) {
23247 switch (Opcode) {
23248 case VCVTPD2DQYrm:
23249 case VCVTPD2DQYrr:
23250 case VCVTPD2DQZ128rm:
23251 case VCVTPD2DQZ128rmb:
23252 case VCVTPD2DQZ128rmbk:
23253 case VCVTPD2DQZ128rmbkz:
23254 case VCVTPD2DQZ128rmk:
23255 case VCVTPD2DQZ128rmkz:
23256 case VCVTPD2DQZ128rr:
23257 case VCVTPD2DQZ128rrk:
23258 case VCVTPD2DQZ128rrkz:
23259 case VCVTPD2DQZ256rm:
23260 case VCVTPD2DQZ256rmb:
23261 case VCVTPD2DQZ256rmbk:
23262 case VCVTPD2DQZ256rmbkz:
23263 case VCVTPD2DQZ256rmk:
23264 case VCVTPD2DQZ256rmkz:
23265 case VCVTPD2DQZ256rr:
23266 case VCVTPD2DQZ256rrk:
23267 case VCVTPD2DQZ256rrkz:
23268 case VCVTPD2DQZrm:
23269 case VCVTPD2DQZrmb:
23270 case VCVTPD2DQZrmbk:
23271 case VCVTPD2DQZrmbkz:
23272 case VCVTPD2DQZrmk:
23273 case VCVTPD2DQZrmkz:
23274 case VCVTPD2DQZrr:
23275 case VCVTPD2DQZrrb:
23276 case VCVTPD2DQZrrbk:
23277 case VCVTPD2DQZrrbkz:
23278 case VCVTPD2DQZrrk:
23279 case VCVTPD2DQZrrkz:
23280 case VCVTPD2DQrm:
23281 case VCVTPD2DQrr:
23282 return true;
23283 }
23284 return false;
23285}
23286
23287bool isVPXOR(unsigned Opcode) {
23288 switch (Opcode) {
23289 case VPXORYrm:
23290 case VPXORYrr:
23291 case VPXORrm:
23292 case VPXORrr:
23293 return true;
23294 }
23295 return false;
23296}
23297
23298bool isSTMXCSR(unsigned Opcode) {
23299 return Opcode == STMXCSR;
23300}
23301
23302bool isVRCP14SS(unsigned Opcode) {
23303 switch (Opcode) {
23304 case VRCP14SSZrm:
23305 case VRCP14SSZrmk:
23306 case VRCP14SSZrmkz:
23307 case VRCP14SSZrr:
23308 case VRCP14SSZrrk:
23309 case VRCP14SSZrrkz:
23310 return true;
23311 }
23312 return false;
23313}
23314
23315bool isUD2(unsigned Opcode) {
23316 return Opcode == TRAP;
23317}
23318
23319bool isVPOPCNTW(unsigned Opcode) {
23320 switch (Opcode) {
23321 case VPOPCNTWZ128rm:
23322 case VPOPCNTWZ128rmk:
23323 case VPOPCNTWZ128rmkz:
23324 case VPOPCNTWZ128rr:
23325 case VPOPCNTWZ128rrk:
23326 case VPOPCNTWZ128rrkz:
23327 case VPOPCNTWZ256rm:
23328 case VPOPCNTWZ256rmk:
23329 case VPOPCNTWZ256rmkz:
23330 case VPOPCNTWZ256rr:
23331 case VPOPCNTWZ256rrk:
23332 case VPOPCNTWZ256rrkz:
23333 case VPOPCNTWZrm:
23334 case VPOPCNTWZrmk:
23335 case VPOPCNTWZrmkz:
23336 case VPOPCNTWZrr:
23337 case VPOPCNTWZrrk:
23338 case VPOPCNTWZrrkz:
23339 return true;
23340 }
23341 return false;
23342}
23343
23344bool isVRSQRTSH(unsigned Opcode) {
23345 switch (Opcode) {
23346 case VRSQRTSHZrm:
23347 case VRSQRTSHZrmk:
23348 case VRSQRTSHZrmkz:
23349 case VRSQRTSHZrr:
23350 case VRSQRTSHZrrk:
23351 case VRSQRTSHZrrkz:
23352 return true;
23353 }
23354 return false;
23355}
23356
23357bool isVSCATTERPF0DPD(unsigned Opcode) {
23358 return Opcode == VSCATTERPF0DPDm;
23359}
23360
23361bool isVFMADDPS(unsigned Opcode) {
23362 switch (Opcode) {
23363 case VFMADDPS4Ymr:
23364 case VFMADDPS4Yrm:
23365 case VFMADDPS4Yrr:
23366 case VFMADDPS4Yrr_REV:
23367 case VFMADDPS4mr:
23368 case VFMADDPS4rm:
23369 case VFMADDPS4rr:
23370 case VFMADDPS4rr_REV:
23371 return true;
23372 }
23373 return false;
23374}
23375
23376bool isXSAVEC64(unsigned Opcode) {
23377 return Opcode == XSAVEC64;
23378}
23379
23380bool isVPMADDUBSW(unsigned Opcode) {
23381 switch (Opcode) {
23382 case VPMADDUBSWYrm:
23383 case VPMADDUBSWYrr:
23384 case VPMADDUBSWZ128rm:
23385 case VPMADDUBSWZ128rmk:
23386 case VPMADDUBSWZ128rmkz:
23387 case VPMADDUBSWZ128rr:
23388 case VPMADDUBSWZ128rrk:
23389 case VPMADDUBSWZ128rrkz:
23390 case VPMADDUBSWZ256rm:
23391 case VPMADDUBSWZ256rmk:
23392 case VPMADDUBSWZ256rmkz:
23393 case VPMADDUBSWZ256rr:
23394 case VPMADDUBSWZ256rrk:
23395 case VPMADDUBSWZ256rrkz:
23396 case VPMADDUBSWZrm:
23397 case VPMADDUBSWZrmk:
23398 case VPMADDUBSWZrmkz:
23399 case VPMADDUBSWZrr:
23400 case VPMADDUBSWZrrk:
23401 case VPMADDUBSWZrrkz:
23402 case VPMADDUBSWrm:
23403 case VPMADDUBSWrr:
23404 return true;
23405 }
23406 return false;
23407}
23408
23409bool isVPMOVZXDQ(unsigned Opcode) {
23410 switch (Opcode) {
23411 case VPMOVZXDQYrm:
23412 case VPMOVZXDQYrr:
23413 case VPMOVZXDQZ128rm:
23414 case VPMOVZXDQZ128rmk:
23415 case VPMOVZXDQZ128rmkz:
23416 case VPMOVZXDQZ128rr:
23417 case VPMOVZXDQZ128rrk:
23418 case VPMOVZXDQZ128rrkz:
23419 case VPMOVZXDQZ256rm:
23420 case VPMOVZXDQZ256rmk:
23421 case VPMOVZXDQZ256rmkz:
23422 case VPMOVZXDQZ256rr:
23423 case VPMOVZXDQZ256rrk:
23424 case VPMOVZXDQZ256rrkz:
23425 case VPMOVZXDQZrm:
23426 case VPMOVZXDQZrmk:
23427 case VPMOVZXDQZrmkz:
23428 case VPMOVZXDQZrr:
23429 case VPMOVZXDQZrrk:
23430 case VPMOVZXDQZrrkz:
23431 case VPMOVZXDQrm:
23432 case VPMOVZXDQrr:
23433 return true;
23434 }
23435 return false;
23436}
23437
23438bool isVRCP14PS(unsigned Opcode) {
23439 switch (Opcode) {
23440 case VRCP14PSZ128m:
23441 case VRCP14PSZ128mb:
23442 case VRCP14PSZ128mbk:
23443 case VRCP14PSZ128mbkz:
23444 case VRCP14PSZ128mk:
23445 case VRCP14PSZ128mkz:
23446 case VRCP14PSZ128r:
23447 case VRCP14PSZ128rk:
23448 case VRCP14PSZ128rkz:
23449 case VRCP14PSZ256m:
23450 case VRCP14PSZ256mb:
23451 case VRCP14PSZ256mbk:
23452 case VRCP14PSZ256mbkz:
23453 case VRCP14PSZ256mk:
23454 case VRCP14PSZ256mkz:
23455 case VRCP14PSZ256r:
23456 case VRCP14PSZ256rk:
23457 case VRCP14PSZ256rkz:
23458 case VRCP14PSZm:
23459 case VRCP14PSZmb:
23460 case VRCP14PSZmbk:
23461 case VRCP14PSZmbkz:
23462 case VRCP14PSZmk:
23463 case VRCP14PSZmkz:
23464 case VRCP14PSZr:
23465 case VRCP14PSZrk:
23466 case VRCP14PSZrkz:
23467 return true;
23468 }
23469 return false;
23470}
23471
23472bool isVSQRTSH(unsigned Opcode) {
23473 switch (Opcode) {
23474 case VSQRTSHZm_Int:
23475 case VSQRTSHZmk_Int:
23476 case VSQRTSHZmkz_Int:
23477 case VSQRTSHZr_Int:
23478 case VSQRTSHZrb_Int:
23479 case VSQRTSHZrbk_Int:
23480 case VSQRTSHZrbkz_Int:
23481 case VSQRTSHZrk_Int:
23482 case VSQRTSHZrkz_Int:
23483 return true;
23484 }
23485 return false;
23486}
23487
23488bool isTCVTROWD2PS(unsigned Opcode) {
23489 switch (Opcode) {
23490 case TCVTROWD2PSrte:
23491 case TCVTROWD2PSrti:
23492 return true;
23493 }
23494 return false;
23495}
23496
23497bool isLOOP(unsigned Opcode) {
23498 return Opcode == LOOP;
23499}
23500
23501bool isSTUI(unsigned Opcode) {
23502 return Opcode == STUI;
23503}
23504
23505bool isVCVTTPS2UDQ(unsigned Opcode) {
23506 switch (Opcode) {
23507 case VCVTTPS2UDQZ128rm:
23508 case VCVTTPS2UDQZ128rmb:
23509 case VCVTTPS2UDQZ128rmbk:
23510 case VCVTTPS2UDQZ128rmbkz:
23511 case VCVTTPS2UDQZ128rmk:
23512 case VCVTTPS2UDQZ128rmkz:
23513 case VCVTTPS2UDQZ128rr:
23514 case VCVTTPS2UDQZ128rrk:
23515 case VCVTTPS2UDQZ128rrkz:
23516 case VCVTTPS2UDQZ256rm:
23517 case VCVTTPS2UDQZ256rmb:
23518 case VCVTTPS2UDQZ256rmbk:
23519 case VCVTTPS2UDQZ256rmbkz:
23520 case VCVTTPS2UDQZ256rmk:
23521 case VCVTTPS2UDQZ256rmkz:
23522 case VCVTTPS2UDQZ256rr:
23523 case VCVTTPS2UDQZ256rrk:
23524 case VCVTTPS2UDQZ256rrkz:
23525 case VCVTTPS2UDQZrm:
23526 case VCVTTPS2UDQZrmb:
23527 case VCVTTPS2UDQZrmbk:
23528 case VCVTTPS2UDQZrmbkz:
23529 case VCVTTPS2UDQZrmk:
23530 case VCVTTPS2UDQZrmkz:
23531 case VCVTTPS2UDQZrr:
23532 case VCVTTPS2UDQZrrb:
23533 case VCVTTPS2UDQZrrbk:
23534 case VCVTTPS2UDQZrrbkz:
23535 case VCVTTPS2UDQZrrk:
23536 case VCVTTPS2UDQZrrkz:
23537 return true;
23538 }
23539 return false;
23540}
23541
23542bool isXABORT(unsigned Opcode) {
23543 return Opcode == XABORT;
23544}
23545
23546bool isVCOMPRESSPS(unsigned Opcode) {
23547 switch (Opcode) {
23548 case VCOMPRESSPSZ128mr:
23549 case VCOMPRESSPSZ128mrk:
23550 case VCOMPRESSPSZ128rr:
23551 case VCOMPRESSPSZ128rrk:
23552 case VCOMPRESSPSZ128rrkz:
23553 case VCOMPRESSPSZ256mr:
23554 case VCOMPRESSPSZ256mrk:
23555 case VCOMPRESSPSZ256rr:
23556 case VCOMPRESSPSZ256rrk:
23557 case VCOMPRESSPSZ256rrkz:
23558 case VCOMPRESSPSZmr:
23559 case VCOMPRESSPSZmrk:
23560 case VCOMPRESSPSZrr:
23561 case VCOMPRESSPSZrrk:
23562 case VCOMPRESSPSZrrkz:
23563 return true;
23564 }
23565 return false;
23566}
23567
23568bool isVCVTTBF162IUBS(unsigned Opcode) {
23569 switch (Opcode) {
23570 case VCVTTBF162IUBSZ128rm:
23571 case VCVTTBF162IUBSZ128rmb:
23572 case VCVTTBF162IUBSZ128rmbk:
23573 case VCVTTBF162IUBSZ128rmbkz:
23574 case VCVTTBF162IUBSZ128rmk:
23575 case VCVTTBF162IUBSZ128rmkz:
23576 case VCVTTBF162IUBSZ128rr:
23577 case VCVTTBF162IUBSZ128rrk:
23578 case VCVTTBF162IUBSZ128rrkz:
23579 case VCVTTBF162IUBSZ256rm:
23580 case VCVTTBF162IUBSZ256rmb:
23581 case VCVTTBF162IUBSZ256rmbk:
23582 case VCVTTBF162IUBSZ256rmbkz:
23583 case VCVTTBF162IUBSZ256rmk:
23584 case VCVTTBF162IUBSZ256rmkz:
23585 case VCVTTBF162IUBSZ256rr:
23586 case VCVTTBF162IUBSZ256rrk:
23587 case VCVTTBF162IUBSZ256rrkz:
23588 case VCVTTBF162IUBSZrm:
23589 case VCVTTBF162IUBSZrmb:
23590 case VCVTTBF162IUBSZrmbk:
23591 case VCVTTBF162IUBSZrmbkz:
23592 case VCVTTBF162IUBSZrmk:
23593 case VCVTTBF162IUBSZrmkz:
23594 case VCVTTBF162IUBSZrr:
23595 case VCVTTBF162IUBSZrrk:
23596 case VCVTTBF162IUBSZrrkz:
23597 return true;
23598 }
23599 return false;
23600}
23601
23602bool isVPADDW(unsigned Opcode) {
23603 switch (Opcode) {
23604 case VPADDWYrm:
23605 case VPADDWYrr:
23606 case VPADDWZ128rm:
23607 case VPADDWZ128rmk:
23608 case VPADDWZ128rmkz:
23609 case VPADDWZ128rr:
23610 case VPADDWZ128rrk:
23611 case VPADDWZ128rrkz:
23612 case VPADDWZ256rm:
23613 case VPADDWZ256rmk:
23614 case VPADDWZ256rmkz:
23615 case VPADDWZ256rr:
23616 case VPADDWZ256rrk:
23617 case VPADDWZ256rrkz:
23618 case VPADDWZrm:
23619 case VPADDWZrmk:
23620 case VPADDWZrmkz:
23621 case VPADDWZrr:
23622 case VPADDWZrrk:
23623 case VPADDWZrrkz:
23624 case VPADDWrm:
23625 case VPADDWrr:
23626 return true;
23627 }
23628 return false;
23629}
23630
23631bool isVPSIGND(unsigned Opcode) {
23632 switch (Opcode) {
23633 case VPSIGNDYrm:
23634 case VPSIGNDYrr:
23635 case VPSIGNDrm:
23636 case VPSIGNDrr:
23637 return true;
23638 }
23639 return false;
23640}
23641
23642bool isVRNDSCALEPS(unsigned Opcode) {
23643 switch (Opcode) {
23644 case VRNDSCALEPSZ128rmbi:
23645 case VRNDSCALEPSZ128rmbik:
23646 case VRNDSCALEPSZ128rmbikz:
23647 case VRNDSCALEPSZ128rmi:
23648 case VRNDSCALEPSZ128rmik:
23649 case VRNDSCALEPSZ128rmikz:
23650 case VRNDSCALEPSZ128rri:
23651 case VRNDSCALEPSZ128rrik:
23652 case VRNDSCALEPSZ128rrikz:
23653 case VRNDSCALEPSZ256rmbi:
23654 case VRNDSCALEPSZ256rmbik:
23655 case VRNDSCALEPSZ256rmbikz:
23656 case VRNDSCALEPSZ256rmi:
23657 case VRNDSCALEPSZ256rmik:
23658 case VRNDSCALEPSZ256rmikz:
23659 case VRNDSCALEPSZ256rri:
23660 case VRNDSCALEPSZ256rrik:
23661 case VRNDSCALEPSZ256rrikz:
23662 case VRNDSCALEPSZrmbi:
23663 case VRNDSCALEPSZrmbik:
23664 case VRNDSCALEPSZrmbikz:
23665 case VRNDSCALEPSZrmi:
23666 case VRNDSCALEPSZrmik:
23667 case VRNDSCALEPSZrmikz:
23668 case VRNDSCALEPSZrri:
23669 case VRNDSCALEPSZrrib:
23670 case VRNDSCALEPSZrribk:
23671 case VRNDSCALEPSZrribkz:
23672 case VRNDSCALEPSZrrik:
23673 case VRNDSCALEPSZrrikz:
23674 return true;
23675 }
23676 return false;
23677}
23678
23679bool isVPHADDUWD(unsigned Opcode) {
23680 switch (Opcode) {
23681 case VPHADDUWDrm:
23682 case VPHADDUWDrr:
23683 return true;
23684 }
23685 return false;
23686}
23687
23688bool isVCVT2PH2HF8S(unsigned Opcode) {
23689 switch (Opcode) {
23690 case VCVT2PH2HF8SZ128rm:
23691 case VCVT2PH2HF8SZ128rmb:
23692 case VCVT2PH2HF8SZ128rmbk:
23693 case VCVT2PH2HF8SZ128rmbkz:
23694 case VCVT2PH2HF8SZ128rmk:
23695 case VCVT2PH2HF8SZ128rmkz:
23696 case VCVT2PH2HF8SZ128rr:
23697 case VCVT2PH2HF8SZ128rrk:
23698 case VCVT2PH2HF8SZ128rrkz:
23699 case VCVT2PH2HF8SZ256rm:
23700 case VCVT2PH2HF8SZ256rmb:
23701 case VCVT2PH2HF8SZ256rmbk:
23702 case VCVT2PH2HF8SZ256rmbkz:
23703 case VCVT2PH2HF8SZ256rmk:
23704 case VCVT2PH2HF8SZ256rmkz:
23705 case VCVT2PH2HF8SZ256rr:
23706 case VCVT2PH2HF8SZ256rrk:
23707 case VCVT2PH2HF8SZ256rrkz:
23708 case VCVT2PH2HF8SZrm:
23709 case VCVT2PH2HF8SZrmb:
23710 case VCVT2PH2HF8SZrmbk:
23711 case VCVT2PH2HF8SZrmbkz:
23712 case VCVT2PH2HF8SZrmk:
23713 case VCVT2PH2HF8SZrmkz:
23714 case VCVT2PH2HF8SZrr:
23715 case VCVT2PH2HF8SZrrk:
23716 case VCVT2PH2HF8SZrrkz:
23717 return true;
23718 }
23719 return false;
23720}
23721
23722bool isVDBPSADBW(unsigned Opcode) {
23723 switch (Opcode) {
23724 case VDBPSADBWZ128rmi:
23725 case VDBPSADBWZ128rmik:
23726 case VDBPSADBWZ128rmikz:
23727 case VDBPSADBWZ128rri:
23728 case VDBPSADBWZ128rrik:
23729 case VDBPSADBWZ128rrikz:
23730 case VDBPSADBWZ256rmi:
23731 case VDBPSADBWZ256rmik:
23732 case VDBPSADBWZ256rmikz:
23733 case VDBPSADBWZ256rri:
23734 case VDBPSADBWZ256rrik:
23735 case VDBPSADBWZ256rrikz:
23736 case VDBPSADBWZrmi:
23737 case VDBPSADBWZrmik:
23738 case VDBPSADBWZrmikz:
23739 case VDBPSADBWZrri:
23740 case VDBPSADBWZrrik:
23741 case VDBPSADBWZrrikz:
23742 return true;
23743 }
23744 return false;
23745}
23746
23747bool isPSLLW(unsigned Opcode) {
23748 switch (Opcode) {
23749 case MMX_PSLLWri:
23750 case MMX_PSLLWrm:
23751 case MMX_PSLLWrr:
23752 case PSLLWri:
23753 case PSLLWrm:
23754 case PSLLWrr:
23755 return true;
23756 }
23757 return false;
23758}
23759
23760bool isVPMOVQD(unsigned Opcode) {
23761 switch (Opcode) {
23762 case VPMOVQDZ128mr:
23763 case VPMOVQDZ128mrk:
23764 case VPMOVQDZ128rr:
23765 case VPMOVQDZ128rrk:
23766 case VPMOVQDZ128rrkz:
23767 case VPMOVQDZ256mr:
23768 case VPMOVQDZ256mrk:
23769 case VPMOVQDZ256rr:
23770 case VPMOVQDZ256rrk:
23771 case VPMOVQDZ256rrkz:
23772 case VPMOVQDZmr:
23773 case VPMOVQDZmrk:
23774 case VPMOVQDZrr:
23775 case VPMOVQDZrrk:
23776 case VPMOVQDZrrkz:
23777 return true;
23778 }
23779 return false;
23780}
23781
23782bool isVINSERTI64X4(unsigned Opcode) {
23783 switch (Opcode) {
23784 case VINSERTI64X4Zrmi:
23785 case VINSERTI64X4Zrmik:
23786 case VINSERTI64X4Zrmikz:
23787 case VINSERTI64X4Zrri:
23788 case VINSERTI64X4Zrrik:
23789 case VINSERTI64X4Zrrikz:
23790 return true;
23791 }
23792 return false;
23793}
23794
23795bool isVPERMI2PS(unsigned Opcode) {
23796 switch (Opcode) {
23797 case VPERMI2PSZ128rm:
23798 case VPERMI2PSZ128rmb:
23799 case VPERMI2PSZ128rmbk:
23800 case VPERMI2PSZ128rmbkz:
23801 case VPERMI2PSZ128rmk:
23802 case VPERMI2PSZ128rmkz:
23803 case VPERMI2PSZ128rr:
23804 case VPERMI2PSZ128rrk:
23805 case VPERMI2PSZ128rrkz:
23806 case VPERMI2PSZ256rm:
23807 case VPERMI2PSZ256rmb:
23808 case VPERMI2PSZ256rmbk:
23809 case VPERMI2PSZ256rmbkz:
23810 case VPERMI2PSZ256rmk:
23811 case VPERMI2PSZ256rmkz:
23812 case VPERMI2PSZ256rr:
23813 case VPERMI2PSZ256rrk:
23814 case VPERMI2PSZ256rrkz:
23815 case VPERMI2PSZrm:
23816 case VPERMI2PSZrmb:
23817 case VPERMI2PSZrmbk:
23818 case VPERMI2PSZrmbkz:
23819 case VPERMI2PSZrmk:
23820 case VPERMI2PSZrmkz:
23821 case VPERMI2PSZrr:
23822 case VPERMI2PSZrrk:
23823 case VPERMI2PSZrrkz:
23824 return true;
23825 }
23826 return false;
23827}
23828
23829bool isVMULPH(unsigned Opcode) {
23830 switch (Opcode) {
23831 case VMULPHZ128rm:
23832 case VMULPHZ128rmb:
23833 case VMULPHZ128rmbk:
23834 case VMULPHZ128rmbkz:
23835 case VMULPHZ128rmk:
23836 case VMULPHZ128rmkz:
23837 case VMULPHZ128rr:
23838 case VMULPHZ128rrk:
23839 case VMULPHZ128rrkz:
23840 case VMULPHZ256rm:
23841 case VMULPHZ256rmb:
23842 case VMULPHZ256rmbk:
23843 case VMULPHZ256rmbkz:
23844 case VMULPHZ256rmk:
23845 case VMULPHZ256rmkz:
23846 case VMULPHZ256rr:
23847 case VMULPHZ256rrk:
23848 case VMULPHZ256rrkz:
23849 case VMULPHZrm:
23850 case VMULPHZrmb:
23851 case VMULPHZrmbk:
23852 case VMULPHZrmbkz:
23853 case VMULPHZrmk:
23854 case VMULPHZrmkz:
23855 case VMULPHZrr:
23856 case VMULPHZrrb:
23857 case VMULPHZrrbk:
23858 case VMULPHZrrbkz:
23859 case VMULPHZrrk:
23860 case VMULPHZrrkz:
23861 return true;
23862 }
23863 return false;
23864}
23865
23866bool isVPCMPUQ(unsigned Opcode) {
23867 switch (Opcode) {
23868 case VPCMPUQZ128rmbi:
23869 case VPCMPUQZ128rmbik:
23870 case VPCMPUQZ128rmi:
23871 case VPCMPUQZ128rmik:
23872 case VPCMPUQZ128rri:
23873 case VPCMPUQZ128rrik:
23874 case VPCMPUQZ256rmbi:
23875 case VPCMPUQZ256rmbik:
23876 case VPCMPUQZ256rmi:
23877 case VPCMPUQZ256rmik:
23878 case VPCMPUQZ256rri:
23879 case VPCMPUQZ256rrik:
23880 case VPCMPUQZrmbi:
23881 case VPCMPUQZrmbik:
23882 case VPCMPUQZrmi:
23883 case VPCMPUQZrmik:
23884 case VPCMPUQZrri:
23885 case VPCMPUQZrrik:
23886 return true;
23887 }
23888 return false;
23889}
23890
23891bool isVCVTUSI2SD(unsigned Opcode) {
23892 switch (Opcode) {
23893 case VCVTUSI2SDZrm_Int:
23894 case VCVTUSI2SDZrr_Int:
23895 case VCVTUSI642SDZrm_Int:
23896 case VCVTUSI642SDZrr_Int:
23897 case VCVTUSI642SDZrrb_Int:
23898 return true;
23899 }
23900 return false;
23901}
23902
23903bool isKXNORW(unsigned Opcode) {
23904 return Opcode == KXNORWkk;
23905}
23906
23907bool isBLCIC(unsigned Opcode) {
23908 switch (Opcode) {
23909 case BLCIC32rm:
23910 case BLCIC32rr:
23911 case BLCIC64rm:
23912 case BLCIC64rr:
23913 return true;
23914 }
23915 return false;
23916}
23917
23918bool isVFNMADD213SD(unsigned Opcode) {
23919 switch (Opcode) {
23920 case VFNMADD213SDZm_Int:
23921 case VFNMADD213SDZmk_Int:
23922 case VFNMADD213SDZmkz_Int:
23923 case VFNMADD213SDZr_Int:
23924 case VFNMADD213SDZrb_Int:
23925 case VFNMADD213SDZrbk_Int:
23926 case VFNMADD213SDZrbkz_Int:
23927 case VFNMADD213SDZrk_Int:
23928 case VFNMADD213SDZrkz_Int:
23929 case VFNMADD213SDm_Int:
23930 case VFNMADD213SDr_Int:
23931 return true;
23932 }
23933 return false;
23934}
23935
23936bool isVMOVLPS(unsigned Opcode) {
23937 switch (Opcode) {
23938 case VMOVLPSZ128mr:
23939 case VMOVLPSZ128rm:
23940 case VMOVLPSmr:
23941 case VMOVLPSrm:
23942 return true;
23943 }
23944 return false;
23945}
23946
23947bool isVPMACSWW(unsigned Opcode) {
23948 switch (Opcode) {
23949 case VPMACSWWrm:
23950 case VPMACSWWrr:
23951 return true;
23952 }
23953 return false;
23954}
23955
23956bool isPCONFIG(unsigned Opcode) {
23957 return Opcode == PCONFIG;
23958}
23959
23960bool isPANDN(unsigned Opcode) {
23961 switch (Opcode) {
23962 case MMX_PANDNrm:
23963 case MMX_PANDNrr:
23964 case PANDNrm:
23965 case PANDNrr:
23966 return true;
23967 }
23968 return false;
23969}
23970
23971bool isVGETEXPPD(unsigned Opcode) {
23972 switch (Opcode) {
23973 case VGETEXPPDZ128m:
23974 case VGETEXPPDZ128mb:
23975 case VGETEXPPDZ128mbk:
23976 case VGETEXPPDZ128mbkz:
23977 case VGETEXPPDZ128mk:
23978 case VGETEXPPDZ128mkz:
23979 case VGETEXPPDZ128r:
23980 case VGETEXPPDZ128rk:
23981 case VGETEXPPDZ128rkz:
23982 case VGETEXPPDZ256m:
23983 case VGETEXPPDZ256mb:
23984 case VGETEXPPDZ256mbk:
23985 case VGETEXPPDZ256mbkz:
23986 case VGETEXPPDZ256mk:
23987 case VGETEXPPDZ256mkz:
23988 case VGETEXPPDZ256r:
23989 case VGETEXPPDZ256rk:
23990 case VGETEXPPDZ256rkz:
23991 case VGETEXPPDZm:
23992 case VGETEXPPDZmb:
23993 case VGETEXPPDZmbk:
23994 case VGETEXPPDZmbkz:
23995 case VGETEXPPDZmk:
23996 case VGETEXPPDZmkz:
23997 case VGETEXPPDZr:
23998 case VGETEXPPDZrb:
23999 case VGETEXPPDZrbk:
24000 case VGETEXPPDZrbkz:
24001 case VGETEXPPDZrk:
24002 case VGETEXPPDZrkz:
24003 return true;
24004 }
24005 return false;
24006}
24007
24008bool isVPSRLVQ(unsigned Opcode) {
24009 switch (Opcode) {
24010 case VPSRLVQYrm:
24011 case VPSRLVQYrr:
24012 case VPSRLVQZ128rm:
24013 case VPSRLVQZ128rmb:
24014 case VPSRLVQZ128rmbk:
24015 case VPSRLVQZ128rmbkz:
24016 case VPSRLVQZ128rmk:
24017 case VPSRLVQZ128rmkz:
24018 case VPSRLVQZ128rr:
24019 case VPSRLVQZ128rrk:
24020 case VPSRLVQZ128rrkz:
24021 case VPSRLVQZ256rm:
24022 case VPSRLVQZ256rmb:
24023 case VPSRLVQZ256rmbk:
24024 case VPSRLVQZ256rmbkz:
24025 case VPSRLVQZ256rmk:
24026 case VPSRLVQZ256rmkz:
24027 case VPSRLVQZ256rr:
24028 case VPSRLVQZ256rrk:
24029 case VPSRLVQZ256rrkz:
24030 case VPSRLVQZrm:
24031 case VPSRLVQZrmb:
24032 case VPSRLVQZrmbk:
24033 case VPSRLVQZrmbkz:
24034 case VPSRLVQZrmk:
24035 case VPSRLVQZrmkz:
24036 case VPSRLVQZrr:
24037 case VPSRLVQZrrk:
24038 case VPSRLVQZrrkz:
24039 case VPSRLVQrm:
24040 case VPSRLVQrr:
24041 return true;
24042 }
24043 return false;
24044}
24045
24046bool isUD1(unsigned Opcode) {
24047 switch (Opcode) {
24048 case UD1Lm:
24049 case UD1Lr:
24050 case UD1Qm:
24051 case UD1Qr:
24052 case UD1Wm:
24053 case UD1Wr:
24054 return true;
24055 }
24056 return false;
24057}
24058
24059bool isPMAXSB(unsigned Opcode) {
24060 switch (Opcode) {
24061 case PMAXSBrm:
24062 case PMAXSBrr:
24063 return true;
24064 }
24065 return false;
24066}
24067
24068bool isVPROLQ(unsigned Opcode) {
24069 switch (Opcode) {
24070 case VPROLQZ128mbi:
24071 case VPROLQZ128mbik:
24072 case VPROLQZ128mbikz:
24073 case VPROLQZ128mi:
24074 case VPROLQZ128mik:
24075 case VPROLQZ128mikz:
24076 case VPROLQZ128ri:
24077 case VPROLQZ128rik:
24078 case VPROLQZ128rikz:
24079 case VPROLQZ256mbi:
24080 case VPROLQZ256mbik:
24081 case VPROLQZ256mbikz:
24082 case VPROLQZ256mi:
24083 case VPROLQZ256mik:
24084 case VPROLQZ256mikz:
24085 case VPROLQZ256ri:
24086 case VPROLQZ256rik:
24087 case VPROLQZ256rikz:
24088 case VPROLQZmbi:
24089 case VPROLQZmbik:
24090 case VPROLQZmbikz:
24091 case VPROLQZmi:
24092 case VPROLQZmik:
24093 case VPROLQZmikz:
24094 case VPROLQZri:
24095 case VPROLQZrik:
24096 case VPROLQZrikz:
24097 return true;
24098 }
24099 return false;
24100}
24101
24102bool isVPSRLD(unsigned Opcode) {
24103 switch (Opcode) {
24104 case VPSRLDYri:
24105 case VPSRLDYrm:
24106 case VPSRLDYrr:
24107 case VPSRLDZ128mbi:
24108 case VPSRLDZ128mbik:
24109 case VPSRLDZ128mbikz:
24110 case VPSRLDZ128mi:
24111 case VPSRLDZ128mik:
24112 case VPSRLDZ128mikz:
24113 case VPSRLDZ128ri:
24114 case VPSRLDZ128rik:
24115 case VPSRLDZ128rikz:
24116 case VPSRLDZ128rm:
24117 case VPSRLDZ128rmk:
24118 case VPSRLDZ128rmkz:
24119 case VPSRLDZ128rr:
24120 case VPSRLDZ128rrk:
24121 case VPSRLDZ128rrkz:
24122 case VPSRLDZ256mbi:
24123 case VPSRLDZ256mbik:
24124 case VPSRLDZ256mbikz:
24125 case VPSRLDZ256mi:
24126 case VPSRLDZ256mik:
24127 case VPSRLDZ256mikz:
24128 case VPSRLDZ256ri:
24129 case VPSRLDZ256rik:
24130 case VPSRLDZ256rikz:
24131 case VPSRLDZ256rm:
24132 case VPSRLDZ256rmk:
24133 case VPSRLDZ256rmkz:
24134 case VPSRLDZ256rr:
24135 case VPSRLDZ256rrk:
24136 case VPSRLDZ256rrkz:
24137 case VPSRLDZmbi:
24138 case VPSRLDZmbik:
24139 case VPSRLDZmbikz:
24140 case VPSRLDZmi:
24141 case VPSRLDZmik:
24142 case VPSRLDZmikz:
24143 case VPSRLDZri:
24144 case VPSRLDZrik:
24145 case VPSRLDZrikz:
24146 case VPSRLDZrm:
24147 case VPSRLDZrmk:
24148 case VPSRLDZrmkz:
24149 case VPSRLDZrr:
24150 case VPSRLDZrrk:
24151 case VPSRLDZrrkz:
24152 case VPSRLDri:
24153 case VPSRLDrm:
24154 case VPSRLDrr:
24155 return true;
24156 }
24157 return false;
24158}
24159
24160bool isVSCATTERPF1QPD(unsigned Opcode) {
24161 return Opcode == VSCATTERPF1QPDm;
24162}
24163
24164bool isINT3(unsigned Opcode) {
24165 return Opcode == INT3;
24166}
24167
24168bool isXRSTORS64(unsigned Opcode) {
24169 return Opcode == XRSTORS64;
24170}
24171
24172bool isCVTSD2SI(unsigned Opcode) {
24173 switch (Opcode) {
24174 case CVTSD2SI64rm_Int:
24175 case CVTSD2SI64rr_Int:
24176 case CVTSD2SIrm_Int:
24177 case CVTSD2SIrr_Int:
24178 return true;
24179 }
24180 return false;
24181}
24182
24183bool isVMAXSS(unsigned Opcode) {
24184 switch (Opcode) {
24185 case VMAXSSZrm_Int:
24186 case VMAXSSZrmk_Int:
24187 case VMAXSSZrmkz_Int:
24188 case VMAXSSZrr_Int:
24189 case VMAXSSZrrb_Int:
24190 case VMAXSSZrrbk_Int:
24191 case VMAXSSZrrbkz_Int:
24192 case VMAXSSZrrk_Int:
24193 case VMAXSSZrrkz_Int:
24194 case VMAXSSrm_Int:
24195 case VMAXSSrr_Int:
24196 return true;
24197 }
24198 return false;
24199}
24200
24201bool isVPMINUB(unsigned Opcode) {
24202 switch (Opcode) {
24203 case VPMINUBYrm:
24204 case VPMINUBYrr:
24205 case VPMINUBZ128rm:
24206 case VPMINUBZ128rmk:
24207 case VPMINUBZ128rmkz:
24208 case VPMINUBZ128rr:
24209 case VPMINUBZ128rrk:
24210 case VPMINUBZ128rrkz:
24211 case VPMINUBZ256rm:
24212 case VPMINUBZ256rmk:
24213 case VPMINUBZ256rmkz:
24214 case VPMINUBZ256rr:
24215 case VPMINUBZ256rrk:
24216 case VPMINUBZ256rrkz:
24217 case VPMINUBZrm:
24218 case VPMINUBZrmk:
24219 case VPMINUBZrmkz:
24220 case VPMINUBZrr:
24221 case VPMINUBZrrk:
24222 case VPMINUBZrrkz:
24223 case VPMINUBrm:
24224 case VPMINUBrr:
24225 return true;
24226 }
24227 return false;
24228}
24229
24230bool isKXNORQ(unsigned Opcode) {
24231 return Opcode == KXNORQkk;
24232}
24233
24234bool isFLD(unsigned Opcode) {
24235 switch (Opcode) {
24236 case LD_F32m:
24237 case LD_F64m:
24238 case LD_F80m:
24239 case LD_Frr:
24240 return true;
24241 }
24242 return false;
24243}
24244
24245bool isVSHUFI32X4(unsigned Opcode) {
24246 switch (Opcode) {
24247 case VSHUFI32X4Z256rmbi:
24248 case VSHUFI32X4Z256rmbik:
24249 case VSHUFI32X4Z256rmbikz:
24250 case VSHUFI32X4Z256rmi:
24251 case VSHUFI32X4Z256rmik:
24252 case VSHUFI32X4Z256rmikz:
24253 case VSHUFI32X4Z256rri:
24254 case VSHUFI32X4Z256rrik:
24255 case VSHUFI32X4Z256rrikz:
24256 case VSHUFI32X4Zrmbi:
24257 case VSHUFI32X4Zrmbik:
24258 case VSHUFI32X4Zrmbikz:
24259 case VSHUFI32X4Zrmi:
24260 case VSHUFI32X4Zrmik:
24261 case VSHUFI32X4Zrmikz:
24262 case VSHUFI32X4Zrri:
24263 case VSHUFI32X4Zrrik:
24264 case VSHUFI32X4Zrrikz:
24265 return true;
24266 }
24267 return false;
24268}
24269
24270bool isSAHF(unsigned Opcode) {
24271 return Opcode == SAHF;
24272}
24273
24274bool isPFRSQRT(unsigned Opcode) {
24275 switch (Opcode) {
24276 case PFRSQRTrm:
24277 case PFRSQRTrr:
24278 return true;
24279 }
24280 return false;
24281}
24282
24283bool isSHRD(unsigned Opcode) {
24284 switch (Opcode) {
24285 case SHRD16mrCL:
24286 case SHRD16mrCL_EVEX:
24287 case SHRD16mrCL_ND:
24288 case SHRD16mrCL_NF:
24289 case SHRD16mrCL_NF_ND:
24290 case SHRD16mri8:
24291 case SHRD16mri8_EVEX:
24292 case SHRD16mri8_ND:
24293 case SHRD16mri8_NF:
24294 case SHRD16mri8_NF_ND:
24295 case SHRD16rrCL:
24296 case SHRD16rrCL_EVEX:
24297 case SHRD16rrCL_ND:
24298 case SHRD16rrCL_NF:
24299 case SHRD16rrCL_NF_ND:
24300 case SHRD16rri8:
24301 case SHRD16rri8_EVEX:
24302 case SHRD16rri8_ND:
24303 case SHRD16rri8_NF:
24304 case SHRD16rri8_NF_ND:
24305 case SHRD32mrCL:
24306 case SHRD32mrCL_EVEX:
24307 case SHRD32mrCL_ND:
24308 case SHRD32mrCL_NF:
24309 case SHRD32mrCL_NF_ND:
24310 case SHRD32mri8:
24311 case SHRD32mri8_EVEX:
24312 case SHRD32mri8_ND:
24313 case SHRD32mri8_NF:
24314 case SHRD32mri8_NF_ND:
24315 case SHRD32rrCL:
24316 case SHRD32rrCL_EVEX:
24317 case SHRD32rrCL_ND:
24318 case SHRD32rrCL_NF:
24319 case SHRD32rrCL_NF_ND:
24320 case SHRD32rri8:
24321 case SHRD32rri8_EVEX:
24322 case SHRD32rri8_ND:
24323 case SHRD32rri8_NF:
24324 case SHRD32rri8_NF_ND:
24325 case SHRD64mrCL:
24326 case SHRD64mrCL_EVEX:
24327 case SHRD64mrCL_ND:
24328 case SHRD64mrCL_NF:
24329 case SHRD64mrCL_NF_ND:
24330 case SHRD64mri8:
24331 case SHRD64mri8_EVEX:
24332 case SHRD64mri8_ND:
24333 case SHRD64mri8_NF:
24334 case SHRD64mri8_NF_ND:
24335 case SHRD64rrCL:
24336 case SHRD64rrCL_EVEX:
24337 case SHRD64rrCL_ND:
24338 case SHRD64rrCL_NF:
24339 case SHRD64rrCL_NF_ND:
24340 case SHRD64rri8:
24341 case SHRD64rri8_EVEX:
24342 case SHRD64rri8_ND:
24343 case SHRD64rri8_NF:
24344 case SHRD64rri8_NF_ND:
24345 return true;
24346 }
24347 return false;
24348}
24349
24350bool isSYSEXIT(unsigned Opcode) {
24351 return Opcode == SYSEXIT;
24352}
24353
24354bool isXSAVE64(unsigned Opcode) {
24355 return Opcode == XSAVE64;
24356}
24357
24358bool isVPMAXSD(unsigned Opcode) {
24359 switch (Opcode) {
24360 case VPMAXSDYrm:
24361 case VPMAXSDYrr:
24362 case VPMAXSDZ128rm:
24363 case VPMAXSDZ128rmb:
24364 case VPMAXSDZ128rmbk:
24365 case VPMAXSDZ128rmbkz:
24366 case VPMAXSDZ128rmk:
24367 case VPMAXSDZ128rmkz:
24368 case VPMAXSDZ128rr:
24369 case VPMAXSDZ128rrk:
24370 case VPMAXSDZ128rrkz:
24371 case VPMAXSDZ256rm:
24372 case VPMAXSDZ256rmb:
24373 case VPMAXSDZ256rmbk:
24374 case VPMAXSDZ256rmbkz:
24375 case VPMAXSDZ256rmk:
24376 case VPMAXSDZ256rmkz:
24377 case VPMAXSDZ256rr:
24378 case VPMAXSDZ256rrk:
24379 case VPMAXSDZ256rrkz:
24380 case VPMAXSDZrm:
24381 case VPMAXSDZrmb:
24382 case VPMAXSDZrmbk:
24383 case VPMAXSDZrmbkz:
24384 case VPMAXSDZrmk:
24385 case VPMAXSDZrmkz:
24386 case VPMAXSDZrr:
24387 case VPMAXSDZrrk:
24388 case VPMAXSDZrrkz:
24389 case VPMAXSDrm:
24390 case VPMAXSDrr:
24391 return true;
24392 }
24393 return false;
24394}
24395
24396bool isCVTTSD2SI(unsigned Opcode) {
24397 switch (Opcode) {
24398 case CVTTSD2SI64rm_Int:
24399 case CVTTSD2SI64rr_Int:
24400 case CVTTSD2SIrm_Int:
24401 case CVTTSD2SIrr_Int:
24402 return true;
24403 }
24404 return false;
24405}
24406
24407bool isVCVTTSS2SIS(unsigned Opcode) {
24408 switch (Opcode) {
24409 case VCVTTSS2SI64Srm_Int:
24410 case VCVTTSS2SI64Srr_Int:
24411 case VCVTTSS2SI64Srrb_Int:
24412 case VCVTTSS2SISrm_Int:
24413 case VCVTTSS2SISrr_Int:
24414 case VCVTTSS2SISrrb_Int:
24415 return true;
24416 }
24417 return false;
24418}
24419
24420bool isPMOVMSKB(unsigned Opcode) {
24421 switch (Opcode) {
24422 case MMX_PMOVMSKBrr:
24423 case PMOVMSKBrr:
24424 return true;
24425 }
24426 return false;
24427}
24428
24429bool isVRANGEPS(unsigned Opcode) {
24430 switch (Opcode) {
24431 case VRANGEPSZ128rmbi:
24432 case VRANGEPSZ128rmbik:
24433 case VRANGEPSZ128rmbikz:
24434 case VRANGEPSZ128rmi:
24435 case VRANGEPSZ128rmik:
24436 case VRANGEPSZ128rmikz:
24437 case VRANGEPSZ128rri:
24438 case VRANGEPSZ128rrik:
24439 case VRANGEPSZ128rrikz:
24440 case VRANGEPSZ256rmbi:
24441 case VRANGEPSZ256rmbik:
24442 case VRANGEPSZ256rmbikz:
24443 case VRANGEPSZ256rmi:
24444 case VRANGEPSZ256rmik:
24445 case VRANGEPSZ256rmikz:
24446 case VRANGEPSZ256rri:
24447 case VRANGEPSZ256rrik:
24448 case VRANGEPSZ256rrikz:
24449 case VRANGEPSZrmbi:
24450 case VRANGEPSZrmbik:
24451 case VRANGEPSZrmbikz:
24452 case VRANGEPSZrmi:
24453 case VRANGEPSZrmik:
24454 case VRANGEPSZrmikz:
24455 case VRANGEPSZrri:
24456 case VRANGEPSZrrib:
24457 case VRANGEPSZrribk:
24458 case VRANGEPSZrribkz:
24459 case VRANGEPSZrrik:
24460 case VRANGEPSZrrikz:
24461 return true;
24462 }
24463 return false;
24464}
24465
24466bool isVADDSUBPS(unsigned Opcode) {
24467 switch (Opcode) {
24468 case VADDSUBPSYrm:
24469 case VADDSUBPSYrr:
24470 case VADDSUBPSrm:
24471 case VADDSUBPSrr:
24472 return true;
24473 }
24474 return false;
24475}
24476
24477bool isVBROADCASTI128(unsigned Opcode) {
24478 return Opcode == VBROADCASTI128rm;
24479}
24480
24481bool isPADDUSB(unsigned Opcode) {
24482 switch (Opcode) {
24483 case MMX_PADDUSBrm:
24484 case MMX_PADDUSBrr:
24485 case PADDUSBrm:
24486 case PADDUSBrr:
24487 return true;
24488 }
24489 return false;
24490}
24491
24492bool isENCODEKEY128(unsigned Opcode) {
24493 return Opcode == ENCODEKEY128;
24494}
24495
24496bool isOR(unsigned Opcode) {
24497 switch (Opcode) {
24498 case OR16i16:
24499 case OR16mi:
24500 case OR16mi8:
24501 case OR16mi8_EVEX:
24502 case OR16mi8_ND:
24503 case OR16mi8_NF:
24504 case OR16mi8_NF_ND:
24505 case OR16mi_EVEX:
24506 case OR16mi_ND:
24507 case OR16mi_NF:
24508 case OR16mi_NF_ND:
24509 case OR16mr:
24510 case OR16mr_EVEX:
24511 case OR16mr_ND:
24512 case OR16mr_NF:
24513 case OR16mr_NF_ND:
24514 case OR16ri:
24515 case OR16ri8:
24516 case OR16ri8_EVEX:
24517 case OR16ri8_ND:
24518 case OR16ri8_NF:
24519 case OR16ri8_NF_ND:
24520 case OR16ri_EVEX:
24521 case OR16ri_ND:
24522 case OR16ri_NF:
24523 case OR16ri_NF_ND:
24524 case OR16rm:
24525 case OR16rm_EVEX:
24526 case OR16rm_ND:
24527 case OR16rm_NF:
24528 case OR16rm_NF_ND:
24529 case OR16rr:
24530 case OR16rr_EVEX:
24531 case OR16rr_EVEX_REV:
24532 case OR16rr_ND:
24533 case OR16rr_ND_REV:
24534 case OR16rr_NF:
24535 case OR16rr_NF_ND:
24536 case OR16rr_NF_ND_REV:
24537 case OR16rr_NF_REV:
24538 case OR16rr_REV:
24539 case OR32i32:
24540 case OR32mi:
24541 case OR32mi8:
24542 case OR32mi8_EVEX:
24543 case OR32mi8_ND:
24544 case OR32mi8_NF:
24545 case OR32mi8_NF_ND:
24546 case OR32mi_EVEX:
24547 case OR32mi_ND:
24548 case OR32mi_NF:
24549 case OR32mi_NF_ND:
24550 case OR32mr:
24551 case OR32mr_EVEX:
24552 case OR32mr_ND:
24553 case OR32mr_NF:
24554 case OR32mr_NF_ND:
24555 case OR32ri:
24556 case OR32ri8:
24557 case OR32ri8_EVEX:
24558 case OR32ri8_ND:
24559 case OR32ri8_NF:
24560 case OR32ri8_NF_ND:
24561 case OR32ri_EVEX:
24562 case OR32ri_ND:
24563 case OR32ri_NF:
24564 case OR32ri_NF_ND:
24565 case OR32rm:
24566 case OR32rm_EVEX:
24567 case OR32rm_ND:
24568 case OR32rm_NF:
24569 case OR32rm_NF_ND:
24570 case OR32rr:
24571 case OR32rr_EVEX:
24572 case OR32rr_EVEX_REV:
24573 case OR32rr_ND:
24574 case OR32rr_ND_REV:
24575 case OR32rr_NF:
24576 case OR32rr_NF_ND:
24577 case OR32rr_NF_ND_REV:
24578 case OR32rr_NF_REV:
24579 case OR32rr_REV:
24580 case OR64i32:
24581 case OR64mi32:
24582 case OR64mi32_EVEX:
24583 case OR64mi32_ND:
24584 case OR64mi32_NF:
24585 case OR64mi32_NF_ND:
24586 case OR64mi8:
24587 case OR64mi8_EVEX:
24588 case OR64mi8_ND:
24589 case OR64mi8_NF:
24590 case OR64mi8_NF_ND:
24591 case OR64mr:
24592 case OR64mr_EVEX:
24593 case OR64mr_ND:
24594 case OR64mr_NF:
24595 case OR64mr_NF_ND:
24596 case OR64ri32:
24597 case OR64ri32_EVEX:
24598 case OR64ri32_ND:
24599 case OR64ri32_NF:
24600 case OR64ri32_NF_ND:
24601 case OR64ri8:
24602 case OR64ri8_EVEX:
24603 case OR64ri8_ND:
24604 case OR64ri8_NF:
24605 case OR64ri8_NF_ND:
24606 case OR64rm:
24607 case OR64rm_EVEX:
24608 case OR64rm_ND:
24609 case OR64rm_NF:
24610 case OR64rm_NF_ND:
24611 case OR64rr:
24612 case OR64rr_EVEX:
24613 case OR64rr_EVEX_REV:
24614 case OR64rr_ND:
24615 case OR64rr_ND_REV:
24616 case OR64rr_NF:
24617 case OR64rr_NF_ND:
24618 case OR64rr_NF_ND_REV:
24619 case OR64rr_NF_REV:
24620 case OR64rr_REV:
24621 case OR8i8:
24622 case OR8mi:
24623 case OR8mi8:
24624 case OR8mi_EVEX:
24625 case OR8mi_ND:
24626 case OR8mi_NF:
24627 case OR8mi_NF_ND:
24628 case OR8mr:
24629 case OR8mr_EVEX:
24630 case OR8mr_ND:
24631 case OR8mr_NF:
24632 case OR8mr_NF_ND:
24633 case OR8ri:
24634 case OR8ri8:
24635 case OR8ri_EVEX:
24636 case OR8ri_ND:
24637 case OR8ri_NF:
24638 case OR8ri_NF_ND:
24639 case OR8rm:
24640 case OR8rm_EVEX:
24641 case OR8rm_ND:
24642 case OR8rm_NF:
24643 case OR8rm_NF_ND:
24644 case OR8rr:
24645 case OR8rr_EVEX:
24646 case OR8rr_EVEX_REV:
24647 case OR8rr_ND:
24648 case OR8rr_ND_REV:
24649 case OR8rr_NF:
24650 case OR8rr_NF_ND:
24651 case OR8rr_NF_ND_REV:
24652 case OR8rr_NF_REV:
24653 case OR8rr_REV:
24654 return true;
24655 }
24656 return false;
24657}
24658
24659bool isSTOSW(unsigned Opcode) {
24660 return Opcode == STOSW;
24661}
24662
24663bool isVCVTTPD2UQQS(unsigned Opcode) {
24664 switch (Opcode) {
24665 case VCVTTPD2UQQSZ128rm:
24666 case VCVTTPD2UQQSZ128rmb:
24667 case VCVTTPD2UQQSZ128rmbk:
24668 case VCVTTPD2UQQSZ128rmbkz:
24669 case VCVTTPD2UQQSZ128rmk:
24670 case VCVTTPD2UQQSZ128rmkz:
24671 case VCVTTPD2UQQSZ128rr:
24672 case VCVTTPD2UQQSZ128rrk:
24673 case VCVTTPD2UQQSZ128rrkz:
24674 case VCVTTPD2UQQSZ256rm:
24675 case VCVTTPD2UQQSZ256rmb:
24676 case VCVTTPD2UQQSZ256rmbk:
24677 case VCVTTPD2UQQSZ256rmbkz:
24678 case VCVTTPD2UQQSZ256rmk:
24679 case VCVTTPD2UQQSZ256rmkz:
24680 case VCVTTPD2UQQSZ256rr:
24681 case VCVTTPD2UQQSZ256rrb:
24682 case VCVTTPD2UQQSZ256rrbk:
24683 case VCVTTPD2UQQSZ256rrbkz:
24684 case VCVTTPD2UQQSZ256rrk:
24685 case VCVTTPD2UQQSZ256rrkz:
24686 case VCVTTPD2UQQSZrm:
24687 case VCVTTPD2UQQSZrmb:
24688 case VCVTTPD2UQQSZrmbk:
24689 case VCVTTPD2UQQSZrmbkz:
24690 case VCVTTPD2UQQSZrmk:
24691 case VCVTTPD2UQQSZrmkz:
24692 case VCVTTPD2UQQSZrr:
24693 case VCVTTPD2UQQSZrrb:
24694 case VCVTTPD2UQQSZrrbk:
24695 case VCVTTPD2UQQSZrrbkz:
24696 case VCVTTPD2UQQSZrrk:
24697 case VCVTTPD2UQQSZrrkz:
24698 return true;
24699 }
24700 return false;
24701}
24702
24703bool isPAVGW(unsigned Opcode) {
24704 switch (Opcode) {
24705 case MMX_PAVGWrm:
24706 case MMX_PAVGWrr:
24707 case PAVGWrm:
24708 case PAVGWrr:
24709 return true;
24710 }
24711 return false;
24712}
24713
24714bool isVCVTPD2PH(unsigned Opcode) {
24715 switch (Opcode) {
24716 case VCVTPD2PHZ128rm:
24717 case VCVTPD2PHZ128rmb:
24718 case VCVTPD2PHZ128rmbk:
24719 case VCVTPD2PHZ128rmbkz:
24720 case VCVTPD2PHZ128rmk:
24721 case VCVTPD2PHZ128rmkz:
24722 case VCVTPD2PHZ128rr:
24723 case VCVTPD2PHZ128rrk:
24724 case VCVTPD2PHZ128rrkz:
24725 case VCVTPD2PHZ256rm:
24726 case VCVTPD2PHZ256rmb:
24727 case VCVTPD2PHZ256rmbk:
24728 case VCVTPD2PHZ256rmbkz:
24729 case VCVTPD2PHZ256rmk:
24730 case VCVTPD2PHZ256rmkz:
24731 case VCVTPD2PHZ256rr:
24732 case VCVTPD2PHZ256rrk:
24733 case VCVTPD2PHZ256rrkz:
24734 case VCVTPD2PHZrm:
24735 case VCVTPD2PHZrmb:
24736 case VCVTPD2PHZrmbk:
24737 case VCVTPD2PHZrmbkz:
24738 case VCVTPD2PHZrmk:
24739 case VCVTPD2PHZrmkz:
24740 case VCVTPD2PHZrr:
24741 case VCVTPD2PHZrrb:
24742 case VCVTPD2PHZrrbk:
24743 case VCVTPD2PHZrrbkz:
24744 case VCVTPD2PHZrrk:
24745 case VCVTPD2PHZrrkz:
24746 return true;
24747 }
24748 return false;
24749}
24750
24751bool isSHLX(unsigned Opcode) {
24752 switch (Opcode) {
24753 case SHLX32rm:
24754 case SHLX32rm_EVEX:
24755 case SHLX32rr:
24756 case SHLX32rr_EVEX:
24757 case SHLX64rm:
24758 case SHLX64rm_EVEX:
24759 case SHLX64rr:
24760 case SHLX64rr_EVEX:
24761 return true;
24762 }
24763 return false;
24764}
24765
24766bool isVCVTSH2SD(unsigned Opcode) {
24767 switch (Opcode) {
24768 case VCVTSH2SDZrm_Int:
24769 case VCVTSH2SDZrmk_Int:
24770 case VCVTSH2SDZrmkz_Int:
24771 case VCVTSH2SDZrr_Int:
24772 case VCVTSH2SDZrrb_Int:
24773 case VCVTSH2SDZrrbk_Int:
24774 case VCVTSH2SDZrrbkz_Int:
24775 case VCVTSH2SDZrrk_Int:
24776 case VCVTSH2SDZrrkz_Int:
24777 return true;
24778 }
24779 return false;
24780}
24781
24782bool isVFMADD231SS(unsigned Opcode) {
24783 switch (Opcode) {
24784 case VFMADD231SSZm_Int:
24785 case VFMADD231SSZmk_Int:
24786 case VFMADD231SSZmkz_Int:
24787 case VFMADD231SSZr_Int:
24788 case VFMADD231SSZrb_Int:
24789 case VFMADD231SSZrbk_Int:
24790 case VFMADD231SSZrbkz_Int:
24791 case VFMADD231SSZrk_Int:
24792 case VFMADD231SSZrkz_Int:
24793 case VFMADD231SSm_Int:
24794 case VFMADD231SSr_Int:
24795 return true;
24796 }
24797 return false;
24798}
24799
24800bool isMOVNTSD(unsigned Opcode) {
24801 return Opcode == MOVNTSD;
24802}
24803
24804bool isFLDPI(unsigned Opcode) {
24805 return Opcode == FLDPI;
24806}
24807
24808bool isVCVTUSI2SS(unsigned Opcode) {
24809 switch (Opcode) {
24810 case VCVTUSI2SSZrm_Int:
24811 case VCVTUSI2SSZrr_Int:
24812 case VCVTUSI2SSZrrb_Int:
24813 case VCVTUSI642SSZrm_Int:
24814 case VCVTUSI642SSZrr_Int:
24815 case VCVTUSI642SSZrrb_Int:
24816 return true;
24817 }
24818 return false;
24819}
24820
24821bool isPMOVSXBD(unsigned Opcode) {
24822 switch (Opcode) {
24823 case PMOVSXBDrm:
24824 case PMOVSXBDrr:
24825 return true;
24826 }
24827 return false;
24828}
24829
24830bool isVPRORVQ(unsigned Opcode) {
24831 switch (Opcode) {
24832 case VPRORVQZ128rm:
24833 case VPRORVQZ128rmb:
24834 case VPRORVQZ128rmbk:
24835 case VPRORVQZ128rmbkz:
24836 case VPRORVQZ128rmk:
24837 case VPRORVQZ128rmkz:
24838 case VPRORVQZ128rr:
24839 case VPRORVQZ128rrk:
24840 case VPRORVQZ128rrkz:
24841 case VPRORVQZ256rm:
24842 case VPRORVQZ256rmb:
24843 case VPRORVQZ256rmbk:
24844 case VPRORVQZ256rmbkz:
24845 case VPRORVQZ256rmk:
24846 case VPRORVQZ256rmkz:
24847 case VPRORVQZ256rr:
24848 case VPRORVQZ256rrk:
24849 case VPRORVQZ256rrkz:
24850 case VPRORVQZrm:
24851 case VPRORVQZrmb:
24852 case VPRORVQZrmbk:
24853 case VPRORVQZrmbkz:
24854 case VPRORVQZrmk:
24855 case VPRORVQZrmkz:
24856 case VPRORVQZrr:
24857 case VPRORVQZrrk:
24858 case VPRORVQZrrkz:
24859 return true;
24860 }
24861 return false;
24862}
24863
24864bool isVPERMT2D(unsigned Opcode) {
24865 switch (Opcode) {
24866 case VPERMT2DZ128rm:
24867 case VPERMT2DZ128rmb:
24868 case VPERMT2DZ128rmbk:
24869 case VPERMT2DZ128rmbkz:
24870 case VPERMT2DZ128rmk:
24871 case VPERMT2DZ128rmkz:
24872 case VPERMT2DZ128rr:
24873 case VPERMT2DZ128rrk:
24874 case VPERMT2DZ128rrkz:
24875 case VPERMT2DZ256rm:
24876 case VPERMT2DZ256rmb:
24877 case VPERMT2DZ256rmbk:
24878 case VPERMT2DZ256rmbkz:
24879 case VPERMT2DZ256rmk:
24880 case VPERMT2DZ256rmkz:
24881 case VPERMT2DZ256rr:
24882 case VPERMT2DZ256rrk:
24883 case VPERMT2DZ256rrkz:
24884 case VPERMT2DZrm:
24885 case VPERMT2DZrmb:
24886 case VPERMT2DZrmbk:
24887 case VPERMT2DZrmbkz:
24888 case VPERMT2DZrmk:
24889 case VPERMT2DZrmkz:
24890 case VPERMT2DZrr:
24891 case VPERMT2DZrrk:
24892 case VPERMT2DZrrkz:
24893 return true;
24894 }
24895 return false;
24896}
24897
24898bool isADDSS(unsigned Opcode) {
24899 switch (Opcode) {
24900 case ADDSSrm_Int:
24901 case ADDSSrr_Int:
24902 return true;
24903 }
24904 return false;
24905}
24906
24907bool isAADD(unsigned Opcode) {
24908 switch (Opcode) {
24909 case AADD32mr:
24910 case AADD32mr_EVEX:
24911 case AADD64mr:
24912 case AADD64mr_EVEX:
24913 return true;
24914 }
24915 return false;
24916}
24917
24918bool isVPSRLVW(unsigned Opcode) {
24919 switch (Opcode) {
24920 case VPSRLVWZ128rm:
24921 case VPSRLVWZ128rmk:
24922 case VPSRLVWZ128rmkz:
24923 case VPSRLVWZ128rr:
24924 case VPSRLVWZ128rrk:
24925 case VPSRLVWZ128rrkz:
24926 case VPSRLVWZ256rm:
24927 case VPSRLVWZ256rmk:
24928 case VPSRLVWZ256rmkz:
24929 case VPSRLVWZ256rr:
24930 case VPSRLVWZ256rrk:
24931 case VPSRLVWZ256rrkz:
24932 case VPSRLVWZrm:
24933 case VPSRLVWZrmk:
24934 case VPSRLVWZrmkz:
24935 case VPSRLVWZrr:
24936 case VPSRLVWZrrk:
24937 case VPSRLVWZrrkz:
24938 return true;
24939 }
24940 return false;
24941}
24942
24943bool isVRSQRTPH(unsigned Opcode) {
24944 switch (Opcode) {
24945 case VRSQRTPHZ128m:
24946 case VRSQRTPHZ128mb:
24947 case VRSQRTPHZ128mbk:
24948 case VRSQRTPHZ128mbkz:
24949 case VRSQRTPHZ128mk:
24950 case VRSQRTPHZ128mkz:
24951 case VRSQRTPHZ128r:
24952 case VRSQRTPHZ128rk:
24953 case VRSQRTPHZ128rkz:
24954 case VRSQRTPHZ256m:
24955 case VRSQRTPHZ256mb:
24956 case VRSQRTPHZ256mbk:
24957 case VRSQRTPHZ256mbkz:
24958 case VRSQRTPHZ256mk:
24959 case VRSQRTPHZ256mkz:
24960 case VRSQRTPHZ256r:
24961 case VRSQRTPHZ256rk:
24962 case VRSQRTPHZ256rkz:
24963 case VRSQRTPHZm:
24964 case VRSQRTPHZmb:
24965 case VRSQRTPHZmbk:
24966 case VRSQRTPHZmbkz:
24967 case VRSQRTPHZmk:
24968 case VRSQRTPHZmkz:
24969 case VRSQRTPHZr:
24970 case VRSQRTPHZrk:
24971 case VRSQRTPHZrkz:
24972 return true;
24973 }
24974 return false;
24975}
24976
24977bool isVLDDQU(unsigned Opcode) {
24978 switch (Opcode) {
24979 case VLDDQUYrm:
24980 case VLDDQUrm:
24981 return true;
24982 }
24983 return false;
24984}
24985
24986bool isKMOVD(unsigned Opcode) {
24987 switch (Opcode) {
24988 case KMOVDkk:
24989 case KMOVDkk_EVEX:
24990 case KMOVDkm:
24991 case KMOVDkm_EVEX:
24992 case KMOVDkr:
24993 case KMOVDkr_EVEX:
24994 case KMOVDmk:
24995 case KMOVDmk_EVEX:
24996 case KMOVDrk:
24997 case KMOVDrk_EVEX:
24998 return true;
24999 }
25000 return false;
25001}
25002
25003bool isENCLV(unsigned Opcode) {
25004 return Opcode == ENCLV;
25005}
25006
25007bool isENCLU(unsigned Opcode) {
25008 return Opcode == ENCLU;
25009}
25010
25011bool isPREFETCHT1(unsigned Opcode) {
25012 return Opcode == PREFETCHT1;
25013}
25014
25015bool isRSQRTPS(unsigned Opcode) {
25016 switch (Opcode) {
25017 case RSQRTPSm:
25018 case RSQRTPSr:
25019 return true;
25020 }
25021 return false;
25022}
25023
25024bool isVCVTTSH2USI(unsigned Opcode) {
25025 switch (Opcode) {
25026 case VCVTTSH2USI64Zrm_Int:
25027 case VCVTTSH2USI64Zrr_Int:
25028 case VCVTTSH2USI64Zrrb_Int:
25029 case VCVTTSH2USIZrm_Int:
25030 case VCVTTSH2USIZrr_Int:
25031 case VCVTTSH2USIZrrb_Int:
25032 return true;
25033 }
25034 return false;
25035}
25036
25037bool isPADDB(unsigned Opcode) {
25038 switch (Opcode) {
25039 case MMX_PADDBrm:
25040 case MMX_PADDBrr:
25041 case PADDBrm:
25042 case PADDBrr:
25043 return true;
25044 }
25045 return false;
25046}
25047
25048bool isVMASKMOVDQU(unsigned Opcode) {
25049 return Opcode == VMASKMOVDQU64;
25050}
25051
25052bool isPUNPCKLBW(unsigned Opcode) {
25053 switch (Opcode) {
25054 case MMX_PUNPCKLBWrm:
25055 case MMX_PUNPCKLBWrr:
25056 case PUNPCKLBWrm:
25057 case PUNPCKLBWrr:
25058 return true;
25059 }
25060 return false;
25061}
25062
25063bool isMOV(unsigned Opcode) {
25064 switch (Opcode) {
25065 case MOV16ao16:
25066 case MOV16ao32:
25067 case MOV16mi:
25068 case MOV16mr:
25069 case MOV16ms:
25070 case MOV16o16a:
25071 case MOV16o32a:
25072 case MOV16ri:
25073 case MOV16ri_alt:
25074 case MOV16rm:
25075 case MOV16rr:
25076 case MOV16rr_REV:
25077 case MOV16rs:
25078 case MOV16sm:
25079 case MOV16sr:
25080 case MOV32ao16:
25081 case MOV32ao32:
25082 case MOV32cr:
25083 case MOV32dr:
25084 case MOV32mi:
25085 case MOV32mr:
25086 case MOV32o16a:
25087 case MOV32o32a:
25088 case MOV32rc:
25089 case MOV32rd:
25090 case MOV32ri:
25091 case MOV32ri_alt:
25092 case MOV32rm:
25093 case MOV32rr:
25094 case MOV32rr_REV:
25095 case MOV32rs:
25096 case MOV32sr:
25097 case MOV64ao32:
25098 case MOV64cr:
25099 case MOV64dr:
25100 case MOV64mi32:
25101 case MOV64mr:
25102 case MOV64o32a:
25103 case MOV64rc:
25104 case MOV64rd:
25105 case MOV64ri32:
25106 case MOV64rm:
25107 case MOV64rr:
25108 case MOV64rr_REV:
25109 case MOV64rs:
25110 case MOV64sr:
25111 case MOV8ao16:
25112 case MOV8ao32:
25113 case MOV8mi:
25114 case MOV8mr:
25115 case MOV8o16a:
25116 case MOV8o32a:
25117 case MOV8ri:
25118 case MOV8ri_alt:
25119 case MOV8rm:
25120 case MOV8rr:
25121 case MOV8rr_REV:
25122 return true;
25123 }
25124 return false;
25125}
25126
25127bool isVCVTTPH2IUBS(unsigned Opcode) {
25128 switch (Opcode) {
25129 case VCVTTPH2IUBSZ128rm:
25130 case VCVTTPH2IUBSZ128rmb:
25131 case VCVTTPH2IUBSZ128rmbk:
25132 case VCVTTPH2IUBSZ128rmbkz:
25133 case VCVTTPH2IUBSZ128rmk:
25134 case VCVTTPH2IUBSZ128rmkz:
25135 case VCVTTPH2IUBSZ128rr:
25136 case VCVTTPH2IUBSZ128rrk:
25137 case VCVTTPH2IUBSZ128rrkz:
25138 case VCVTTPH2IUBSZ256rm:
25139 case VCVTTPH2IUBSZ256rmb:
25140 case VCVTTPH2IUBSZ256rmbk:
25141 case VCVTTPH2IUBSZ256rmbkz:
25142 case VCVTTPH2IUBSZ256rmk:
25143 case VCVTTPH2IUBSZ256rmkz:
25144 case VCVTTPH2IUBSZ256rr:
25145 case VCVTTPH2IUBSZ256rrk:
25146 case VCVTTPH2IUBSZ256rrkz:
25147 case VCVTTPH2IUBSZrm:
25148 case VCVTTPH2IUBSZrmb:
25149 case VCVTTPH2IUBSZrmbk:
25150 case VCVTTPH2IUBSZrmbkz:
25151 case VCVTTPH2IUBSZrmk:
25152 case VCVTTPH2IUBSZrmkz:
25153 case VCVTTPH2IUBSZrr:
25154 case VCVTTPH2IUBSZrrb:
25155 case VCVTTPH2IUBSZrrbk:
25156 case VCVTTPH2IUBSZrrbkz:
25157 case VCVTTPH2IUBSZrrk:
25158 case VCVTTPH2IUBSZrrkz:
25159 return true;
25160 }
25161 return false;
25162}
25163
25164bool isMUL(unsigned Opcode) {
25165 switch (Opcode) {
25166 case MUL16m:
25167 case MUL16m_EVEX:
25168 case MUL16m_NF:
25169 case MUL16r:
25170 case MUL16r_EVEX:
25171 case MUL16r_NF:
25172 case MUL32m:
25173 case MUL32m_EVEX:
25174 case MUL32m_NF:
25175 case MUL32r:
25176 case MUL32r_EVEX:
25177 case MUL32r_NF:
25178 case MUL64m:
25179 case MUL64m_EVEX:
25180 case MUL64m_NF:
25181 case MUL64r:
25182 case MUL64r_EVEX:
25183 case MUL64r_NF:
25184 case MUL8m:
25185 case MUL8m_EVEX:
25186 case MUL8m_NF:
25187 case MUL8r:
25188 case MUL8r_EVEX:
25189 case MUL8r_NF:
25190 return true;
25191 }
25192 return false;
25193}
25194
25195bool isRCL(unsigned Opcode) {
25196 switch (Opcode) {
25197 case RCL16m1:
25198 case RCL16m1_EVEX:
25199 case RCL16m1_ND:
25200 case RCL16mCL:
25201 case RCL16mCL_EVEX:
25202 case RCL16mCL_ND:
25203 case RCL16mi:
25204 case RCL16mi_EVEX:
25205 case RCL16mi_ND:
25206 case RCL16r1:
25207 case RCL16r1_EVEX:
25208 case RCL16r1_ND:
25209 case RCL16rCL:
25210 case RCL16rCL_EVEX:
25211 case RCL16rCL_ND:
25212 case RCL16ri:
25213 case RCL16ri_EVEX:
25214 case RCL16ri_ND:
25215 case RCL32m1:
25216 case RCL32m1_EVEX:
25217 case RCL32m1_ND:
25218 case RCL32mCL:
25219 case RCL32mCL_EVEX:
25220 case RCL32mCL_ND:
25221 case RCL32mi:
25222 case RCL32mi_EVEX:
25223 case RCL32mi_ND:
25224 case RCL32r1:
25225 case RCL32r1_EVEX:
25226 case RCL32r1_ND:
25227 case RCL32rCL:
25228 case RCL32rCL_EVEX:
25229 case RCL32rCL_ND:
25230 case RCL32ri:
25231 case RCL32ri_EVEX:
25232 case RCL32ri_ND:
25233 case RCL64m1:
25234 case RCL64m1_EVEX:
25235 case RCL64m1_ND:
25236 case RCL64mCL:
25237 case RCL64mCL_EVEX:
25238 case RCL64mCL_ND:
25239 case RCL64mi:
25240 case RCL64mi_EVEX:
25241 case RCL64mi_ND:
25242 case RCL64r1:
25243 case RCL64r1_EVEX:
25244 case RCL64r1_ND:
25245 case RCL64rCL:
25246 case RCL64rCL_EVEX:
25247 case RCL64rCL_ND:
25248 case RCL64ri:
25249 case RCL64ri_EVEX:
25250 case RCL64ri_ND:
25251 case RCL8m1:
25252 case RCL8m1_EVEX:
25253 case RCL8m1_ND:
25254 case RCL8mCL:
25255 case RCL8mCL_EVEX:
25256 case RCL8mCL_ND:
25257 case RCL8mi:
25258 case RCL8mi_EVEX:
25259 case RCL8mi_ND:
25260 case RCL8r1:
25261 case RCL8r1_EVEX:
25262 case RCL8r1_ND:
25263 case RCL8rCL:
25264 case RCL8rCL_EVEX:
25265 case RCL8rCL_ND:
25266 case RCL8ri:
25267 case RCL8ri_EVEX:
25268 case RCL8ri_ND:
25269 return true;
25270 }
25271 return false;
25272}
25273
25274bool isVRCPSH(unsigned Opcode) {
25275 switch (Opcode) {
25276 case VRCPSHZrm:
25277 case VRCPSHZrmk:
25278 case VRCPSHZrmkz:
25279 case VRCPSHZrr:
25280 case VRCPSHZrrk:
25281 case VRCPSHZrrkz:
25282 return true;
25283 }
25284 return false;
25285}
25286
25287bool isPFCMPEQ(unsigned Opcode) {
25288 switch (Opcode) {
25289 case PFCMPEQrm:
25290 case PFCMPEQrr:
25291 return true;
25292 }
25293 return false;
25294}
25295
25296bool isMONITOR(unsigned Opcode) {
25297 switch (Opcode) {
25298 case MONITOR32rrr:
25299 case MONITOR64rrr:
25300 return true;
25301 }
25302 return false;
25303}
25304
25305bool isFDIVR(unsigned Opcode) {
25306 switch (Opcode) {
25307 case DIVR_F32m:
25308 case DIVR_F64m:
25309 case DIVR_FST0r:
25310 case DIVR_FrST0:
25311 return true;
25312 }
25313 return false;
25314}
25315
25316bool isPFRCP(unsigned Opcode) {
25317 switch (Opcode) {
25318 case PFRCPrm:
25319 case PFRCPrr:
25320 return true;
25321 }
25322 return false;
25323}
25324
25325bool isPMINSD(unsigned Opcode) {
25326 switch (Opcode) {
25327 case PMINSDrm:
25328 case PMINSDrr:
25329 return true;
25330 }
25331 return false;
25332}
25333
25334bool isVSHUFF32X4(unsigned Opcode) {
25335 switch (Opcode) {
25336 case VSHUFF32X4Z256rmbi:
25337 case VSHUFF32X4Z256rmbik:
25338 case VSHUFF32X4Z256rmbikz:
25339 case VSHUFF32X4Z256rmi:
25340 case VSHUFF32X4Z256rmik:
25341 case VSHUFF32X4Z256rmikz:
25342 case VSHUFF32X4Z256rri:
25343 case VSHUFF32X4Z256rrik:
25344 case VSHUFF32X4Z256rrikz:
25345 case VSHUFF32X4Zrmbi:
25346 case VSHUFF32X4Zrmbik:
25347 case VSHUFF32X4Zrmbikz:
25348 case VSHUFF32X4Zrmi:
25349 case VSHUFF32X4Zrmik:
25350 case VSHUFF32X4Zrmikz:
25351 case VSHUFF32X4Zrri:
25352 case VSHUFF32X4Zrrik:
25353 case VSHUFF32X4Zrrikz:
25354 return true;
25355 }
25356 return false;
25357}
25358
25359bool isKTESTQ(unsigned Opcode) {
25360 return Opcode == KTESTQkk;
25361}
25362
25363bool isVCVTTPD2DQ(unsigned Opcode) {
25364 switch (Opcode) {
25365 case VCVTTPD2DQYrm:
25366 case VCVTTPD2DQYrr:
25367 case VCVTTPD2DQZ128rm:
25368 case VCVTTPD2DQZ128rmb:
25369 case VCVTTPD2DQZ128rmbk:
25370 case VCVTTPD2DQZ128rmbkz:
25371 case VCVTTPD2DQZ128rmk:
25372 case VCVTTPD2DQZ128rmkz:
25373 case VCVTTPD2DQZ128rr:
25374 case VCVTTPD2DQZ128rrk:
25375 case VCVTTPD2DQZ128rrkz:
25376 case VCVTTPD2DQZ256rm:
25377 case VCVTTPD2DQZ256rmb:
25378 case VCVTTPD2DQZ256rmbk:
25379 case VCVTTPD2DQZ256rmbkz:
25380 case VCVTTPD2DQZ256rmk:
25381 case VCVTTPD2DQZ256rmkz:
25382 case VCVTTPD2DQZ256rr:
25383 case VCVTTPD2DQZ256rrk:
25384 case VCVTTPD2DQZ256rrkz:
25385 case VCVTTPD2DQZrm:
25386 case VCVTTPD2DQZrmb:
25387 case VCVTTPD2DQZrmbk:
25388 case VCVTTPD2DQZrmbkz:
25389 case VCVTTPD2DQZrmk:
25390 case VCVTTPD2DQZrmkz:
25391 case VCVTTPD2DQZrr:
25392 case VCVTTPD2DQZrrb:
25393 case VCVTTPD2DQZrrbk:
25394 case VCVTTPD2DQZrrbkz:
25395 case VCVTTPD2DQZrrk:
25396 case VCVTTPD2DQZrrkz:
25397 case VCVTTPD2DQrm:
25398 case VCVTTPD2DQrr:
25399 return true;
25400 }
25401 return false;
25402}
25403
25404bool isVPSLLVW(unsigned Opcode) {
25405 switch (Opcode) {
25406 case VPSLLVWZ128rm:
25407 case VPSLLVWZ128rmk:
25408 case VPSLLVWZ128rmkz:
25409 case VPSLLVWZ128rr:
25410 case VPSLLVWZ128rrk:
25411 case VPSLLVWZ128rrkz:
25412 case VPSLLVWZ256rm:
25413 case VPSLLVWZ256rmk:
25414 case VPSLLVWZ256rmkz:
25415 case VPSLLVWZ256rr:
25416 case VPSLLVWZ256rrk:
25417 case VPSLLVWZ256rrkz:
25418 case VPSLLVWZrm:
25419 case VPSLLVWZrmk:
25420 case VPSLLVWZrmkz:
25421 case VPSLLVWZrr:
25422 case VPSLLVWZrrk:
25423 case VPSLLVWZrrkz:
25424 return true;
25425 }
25426 return false;
25427}
25428
25429bool isTDPBSUD(unsigned Opcode) {
25430 return Opcode == TDPBSUD;
25431}
25432
25433bool isVPMINUQ(unsigned Opcode) {
25434 switch (Opcode) {
25435 case VPMINUQZ128rm:
25436 case VPMINUQZ128rmb:
25437 case VPMINUQZ128rmbk:
25438 case VPMINUQZ128rmbkz:
25439 case VPMINUQZ128rmk:
25440 case VPMINUQZ128rmkz:
25441 case VPMINUQZ128rr:
25442 case VPMINUQZ128rrk:
25443 case VPMINUQZ128rrkz:
25444 case VPMINUQZ256rm:
25445 case VPMINUQZ256rmb:
25446 case VPMINUQZ256rmbk:
25447 case VPMINUQZ256rmbkz:
25448 case VPMINUQZ256rmk:
25449 case VPMINUQZ256rmkz:
25450 case VPMINUQZ256rr:
25451 case VPMINUQZ256rrk:
25452 case VPMINUQZ256rrkz:
25453 case VPMINUQZrm:
25454 case VPMINUQZrmb:
25455 case VPMINUQZrmbk:
25456 case VPMINUQZrmbkz:
25457 case VPMINUQZrmk:
25458 case VPMINUQZrmkz:
25459 case VPMINUQZrr:
25460 case VPMINUQZrrk:
25461 case VPMINUQZrrkz:
25462 return true;
25463 }
25464 return false;
25465}
25466
25467bool isFIADD(unsigned Opcode) {
25468 switch (Opcode) {
25469 case ADD_FI16m:
25470 case ADD_FI32m:
25471 return true;
25472 }
25473 return false;
25474}
25475
25476bool isFCMOVNU(unsigned Opcode) {
25477 return Opcode == CMOVNP_F;
25478}
25479
25480bool isVHSUBPD(unsigned Opcode) {
25481 switch (Opcode) {
25482 case VHSUBPDYrm:
25483 case VHSUBPDYrr:
25484 case VHSUBPDrm:
25485 case VHSUBPDrr:
25486 return true;
25487 }
25488 return false;
25489}
25490
25491bool isKSHIFTRQ(unsigned Opcode) {
25492 return Opcode == KSHIFTRQki;
25493}
25494
25495bool isMOVUPS(unsigned Opcode) {
25496 switch (Opcode) {
25497 case MOVUPSmr:
25498 case MOVUPSrm:
25499 case MOVUPSrr:
25500 case MOVUPSrr_REV:
25501 return true;
25502 }
25503 return false;
25504}
25505
25506bool isVMCALL(unsigned Opcode) {
25507 return Opcode == VMCALL;
25508}
25509
25510bool isXADD(unsigned Opcode) {
25511 switch (Opcode) {
25512 case XADD16rm:
25513 case XADD16rr:
25514 case XADD32rm:
25515 case XADD32rr:
25516 case XADD64rm:
25517 case XADD64rr:
25518 case XADD8rm:
25519 case XADD8rr:
25520 return true;
25521 }
25522 return false;
25523}
25524
25525bool isXRSTOR(unsigned Opcode) {
25526 return Opcode == XRSTOR;
25527}
25528
25529bool isVGATHERPF1DPD(unsigned Opcode) {
25530 return Opcode == VGATHERPF1DPDm;
25531}
25532
25533bool isRCR(unsigned Opcode) {
25534 switch (Opcode) {
25535 case RCR16m1:
25536 case RCR16m1_EVEX:
25537 case RCR16m1_ND:
25538 case RCR16mCL:
25539 case RCR16mCL_EVEX:
25540 case RCR16mCL_ND:
25541 case RCR16mi:
25542 case RCR16mi_EVEX:
25543 case RCR16mi_ND:
25544 case RCR16r1:
25545 case RCR16r1_EVEX:
25546 case RCR16r1_ND:
25547 case RCR16rCL:
25548 case RCR16rCL_EVEX:
25549 case RCR16rCL_ND:
25550 case RCR16ri:
25551 case RCR16ri_EVEX:
25552 case RCR16ri_ND:
25553 case RCR32m1:
25554 case RCR32m1_EVEX:
25555 case RCR32m1_ND:
25556 case RCR32mCL:
25557 case RCR32mCL_EVEX:
25558 case RCR32mCL_ND:
25559 case RCR32mi:
25560 case RCR32mi_EVEX:
25561 case RCR32mi_ND:
25562 case RCR32r1:
25563 case RCR32r1_EVEX:
25564 case RCR32r1_ND:
25565 case RCR32rCL:
25566 case RCR32rCL_EVEX:
25567 case RCR32rCL_ND:
25568 case RCR32ri:
25569 case RCR32ri_EVEX:
25570 case RCR32ri_ND:
25571 case RCR64m1:
25572 case RCR64m1_EVEX:
25573 case RCR64m1_ND:
25574 case RCR64mCL:
25575 case RCR64mCL_EVEX:
25576 case RCR64mCL_ND:
25577 case RCR64mi:
25578 case RCR64mi_EVEX:
25579 case RCR64mi_ND:
25580 case RCR64r1:
25581 case RCR64r1_EVEX:
25582 case RCR64r1_ND:
25583 case RCR64rCL:
25584 case RCR64rCL_EVEX:
25585 case RCR64rCL_ND:
25586 case RCR64ri:
25587 case RCR64ri_EVEX:
25588 case RCR64ri_ND:
25589 case RCR8m1:
25590 case RCR8m1_EVEX:
25591 case RCR8m1_ND:
25592 case RCR8mCL:
25593 case RCR8mCL_EVEX:
25594 case RCR8mCL_ND:
25595 case RCR8mi:
25596 case RCR8mi_EVEX:
25597 case RCR8mi_ND:
25598 case RCR8r1:
25599 case RCR8r1_EVEX:
25600 case RCR8r1_ND:
25601 case RCR8rCL:
25602 case RCR8rCL_EVEX:
25603 case RCR8rCL_ND:
25604 case RCR8ri:
25605 case RCR8ri_EVEX:
25606 case RCR8ri_ND:
25607 return true;
25608 }
25609 return false;
25610}
25611
25612bool isFNSTCW(unsigned Opcode) {
25613 return Opcode == FNSTCW16m;
25614}
25615
25616bool isVPMOVSDW(unsigned Opcode) {
25617 switch (Opcode) {
25618 case VPMOVSDWZ128mr:
25619 case VPMOVSDWZ128mrk:
25620 case VPMOVSDWZ128rr:
25621 case VPMOVSDWZ128rrk:
25622 case VPMOVSDWZ128rrkz:
25623 case VPMOVSDWZ256mr:
25624 case VPMOVSDWZ256mrk:
25625 case VPMOVSDWZ256rr:
25626 case VPMOVSDWZ256rrk:
25627 case VPMOVSDWZ256rrkz:
25628 case VPMOVSDWZmr:
25629 case VPMOVSDWZmrk:
25630 case VPMOVSDWZrr:
25631 case VPMOVSDWZrrk:
25632 case VPMOVSDWZrrkz:
25633 return true;
25634 }
25635 return false;
25636}
25637
25638bool isVFMSUB132SH(unsigned Opcode) {
25639 switch (Opcode) {
25640 case VFMSUB132SHZm_Int:
25641 case VFMSUB132SHZmk_Int:
25642 case VFMSUB132SHZmkz_Int:
25643 case VFMSUB132SHZr_Int:
25644 case VFMSUB132SHZrb_Int:
25645 case VFMSUB132SHZrbk_Int:
25646 case VFMSUB132SHZrbkz_Int:
25647 case VFMSUB132SHZrk_Int:
25648 case VFMSUB132SHZrkz_Int:
25649 return true;
25650 }
25651 return false;
25652}
25653
25654bool isVPCONFLICTQ(unsigned Opcode) {
25655 switch (Opcode) {
25656 case VPCONFLICTQZ128rm:
25657 case VPCONFLICTQZ128rmb:
25658 case VPCONFLICTQZ128rmbk:
25659 case VPCONFLICTQZ128rmbkz:
25660 case VPCONFLICTQZ128rmk:
25661 case VPCONFLICTQZ128rmkz:
25662 case VPCONFLICTQZ128rr:
25663 case VPCONFLICTQZ128rrk:
25664 case VPCONFLICTQZ128rrkz:
25665 case VPCONFLICTQZ256rm:
25666 case VPCONFLICTQZ256rmb:
25667 case VPCONFLICTQZ256rmbk:
25668 case VPCONFLICTQZ256rmbkz:
25669 case VPCONFLICTQZ256rmk:
25670 case VPCONFLICTQZ256rmkz:
25671 case VPCONFLICTQZ256rr:
25672 case VPCONFLICTQZ256rrk:
25673 case VPCONFLICTQZ256rrkz:
25674 case VPCONFLICTQZrm:
25675 case VPCONFLICTQZrmb:
25676 case VPCONFLICTQZrmbk:
25677 case VPCONFLICTQZrmbkz:
25678 case VPCONFLICTQZrmk:
25679 case VPCONFLICTQZrmkz:
25680 case VPCONFLICTQZrr:
25681 case VPCONFLICTQZrrk:
25682 case VPCONFLICTQZrrkz:
25683 return true;
25684 }
25685 return false;
25686}
25687
25688bool isSWAPGS(unsigned Opcode) {
25689 return Opcode == SWAPGS;
25690}
25691
25692bool isVPMOVQ2M(unsigned Opcode) {
25693 switch (Opcode) {
25694 case VPMOVQ2MZ128kr:
25695 case VPMOVQ2MZ256kr:
25696 case VPMOVQ2MZkr:
25697 return true;
25698 }
25699 return false;
25700}
25701
25702bool isVPSRAVW(unsigned Opcode) {
25703 switch (Opcode) {
25704 case VPSRAVWZ128rm:
25705 case VPSRAVWZ128rmk:
25706 case VPSRAVWZ128rmkz:
25707 case VPSRAVWZ128rr:
25708 case VPSRAVWZ128rrk:
25709 case VPSRAVWZ128rrkz:
25710 case VPSRAVWZ256rm:
25711 case VPSRAVWZ256rmk:
25712 case VPSRAVWZ256rmkz:
25713 case VPSRAVWZ256rr:
25714 case VPSRAVWZ256rrk:
25715 case VPSRAVWZ256rrkz:
25716 case VPSRAVWZrm:
25717 case VPSRAVWZrmk:
25718 case VPSRAVWZrmkz:
25719 case VPSRAVWZrr:
25720 case VPSRAVWZrrk:
25721 case VPSRAVWZrrkz:
25722 return true;
25723 }
25724 return false;
25725}
25726
25727bool isSHA256MSG2(unsigned Opcode) {
25728 switch (Opcode) {
25729 case SHA256MSG2rm:
25730 case SHA256MSG2rr:
25731 return true;
25732 }
25733 return false;
25734}
25735
25736bool isDIVSD(unsigned Opcode) {
25737 switch (Opcode) {
25738 case DIVSDrm_Int:
25739 case DIVSDrr_Int:
25740 return true;
25741 }
25742 return false;
25743}
25744
25745bool isPCMPGTB(unsigned Opcode) {
25746 switch (Opcode) {
25747 case MMX_PCMPGTBrm:
25748 case MMX_PCMPGTBrr:
25749 case PCMPGTBrm:
25750 case PCMPGTBrr:
25751 return true;
25752 }
25753 return false;
25754}
25755
25756bool isMOVDQA(unsigned Opcode) {
25757 switch (Opcode) {
25758 case MOVDQAmr:
25759 case MOVDQArm:
25760 case MOVDQArr:
25761 case MOVDQArr_REV:
25762 return true;
25763 }
25764 return false;
25765}
25766
25767bool isVAESENCLAST(unsigned Opcode) {
25768 switch (Opcode) {
25769 case VAESENCLASTYrm:
25770 case VAESENCLASTYrr:
25771 case VAESENCLASTZ128rm:
25772 case VAESENCLASTZ128rr:
25773 case VAESENCLASTZ256rm:
25774 case VAESENCLASTZ256rr:
25775 case VAESENCLASTZrm:
25776 case VAESENCLASTZrr:
25777 case VAESENCLASTrm:
25778 case VAESENCLASTrr:
25779 return true;
25780 }
25781 return false;
25782}
25783
25784bool isKXORW(unsigned Opcode) {
25785 return Opcode == KXORWkk;
25786}
25787
25788bool isLIDTW(unsigned Opcode) {
25789 return Opcode == LIDT16m;
25790}
25791
25792bool isPMULHW(unsigned Opcode) {
25793 switch (Opcode) {
25794 case MMX_PMULHWrm:
25795 case MMX_PMULHWrr:
25796 case PMULHWrm:
25797 case PMULHWrr:
25798 return true;
25799 }
25800 return false;
25801}
25802
25803bool isVINSERTI32X8(unsigned Opcode) {
25804 switch (Opcode) {
25805 case VINSERTI32X8Zrmi:
25806 case VINSERTI32X8Zrmik:
25807 case VINSERTI32X8Zrmikz:
25808 case VINSERTI32X8Zrri:
25809 case VINSERTI32X8Zrrik:
25810 case VINSERTI32X8Zrrikz:
25811 return true;
25812 }
25813 return false;
25814}
25815
25816bool isVRCPPS(unsigned Opcode) {
25817 switch (Opcode) {
25818 case VRCPPSYm:
25819 case VRCPPSYr:
25820 case VRCPPSm:
25821 case VRCPPSr:
25822 return true;
25823 }
25824 return false;
25825}
25826
25827bool isVRSQRTBF16(unsigned Opcode) {
25828 switch (Opcode) {
25829 case VRSQRTBF16Z128m:
25830 case VRSQRTBF16Z128mb:
25831 case VRSQRTBF16Z128mbk:
25832 case VRSQRTBF16Z128mbkz:
25833 case VRSQRTBF16Z128mk:
25834 case VRSQRTBF16Z128mkz:
25835 case VRSQRTBF16Z128r:
25836 case VRSQRTBF16Z128rk:
25837 case VRSQRTBF16Z128rkz:
25838 case VRSQRTBF16Z256m:
25839 case VRSQRTBF16Z256mb:
25840 case VRSQRTBF16Z256mbk:
25841 case VRSQRTBF16Z256mbkz:
25842 case VRSQRTBF16Z256mk:
25843 case VRSQRTBF16Z256mkz:
25844 case VRSQRTBF16Z256r:
25845 case VRSQRTBF16Z256rk:
25846 case VRSQRTBF16Z256rkz:
25847 case VRSQRTBF16Zm:
25848 case VRSQRTBF16Zmb:
25849 case VRSQRTBF16Zmbk:
25850 case VRSQRTBF16Zmbkz:
25851 case VRSQRTBF16Zmk:
25852 case VRSQRTBF16Zmkz:
25853 case VRSQRTBF16Zr:
25854 case VRSQRTBF16Zrk:
25855 case VRSQRTBF16Zrkz:
25856 return true;
25857 }
25858 return false;
25859}
25860
25861bool isVGATHERQPS(unsigned Opcode) {
25862 switch (Opcode) {
25863 case VGATHERQPSYrm:
25864 case VGATHERQPSZ128rm:
25865 case VGATHERQPSZ256rm:
25866 case VGATHERQPSZrm:
25867 case VGATHERQPSrm:
25868 return true;
25869 }
25870 return false;
25871}
25872
25873bool isCTESTCC(unsigned Opcode) {
25874 switch (Opcode) {
25875 case CTEST16mi:
25876 case CTEST16mr:
25877 case CTEST16ri:
25878 case CTEST16rr:
25879 case CTEST32mi:
25880 case CTEST32mr:
25881 case CTEST32ri:
25882 case CTEST32rr:
25883 case CTEST64mi32:
25884 case CTEST64mr:
25885 case CTEST64ri32:
25886 case CTEST64rr:
25887 case CTEST8mi:
25888 case CTEST8mr:
25889 case CTEST8ri:
25890 case CTEST8rr:
25891 return true;
25892 }
25893 return false;
25894}
25895
25896bool isPMADDWD(unsigned Opcode) {
25897 switch (Opcode) {
25898 case MMX_PMADDWDrm:
25899 case MMX_PMADDWDrr:
25900 case PMADDWDrm:
25901 case PMADDWDrr:
25902 return true;
25903 }
25904 return false;
25905}
25906
25907bool isUCOMISS(unsigned Opcode) {
25908 switch (Opcode) {
25909 case UCOMISSrm:
25910 case UCOMISSrr:
25911 return true;
25912 }
25913 return false;
25914}
25915
25916bool isXGETBV(unsigned Opcode) {
25917 return Opcode == XGETBV;
25918}
25919
25920bool isVCVTPD2QQ(unsigned Opcode) {
25921 switch (Opcode) {
25922 case VCVTPD2QQZ128rm:
25923 case VCVTPD2QQZ128rmb:
25924 case VCVTPD2QQZ128rmbk:
25925 case VCVTPD2QQZ128rmbkz:
25926 case VCVTPD2QQZ128rmk:
25927 case VCVTPD2QQZ128rmkz:
25928 case VCVTPD2QQZ128rr:
25929 case VCVTPD2QQZ128rrk:
25930 case VCVTPD2QQZ128rrkz:
25931 case VCVTPD2QQZ256rm:
25932 case VCVTPD2QQZ256rmb:
25933 case VCVTPD2QQZ256rmbk:
25934 case VCVTPD2QQZ256rmbkz:
25935 case VCVTPD2QQZ256rmk:
25936 case VCVTPD2QQZ256rmkz:
25937 case VCVTPD2QQZ256rr:
25938 case VCVTPD2QQZ256rrk:
25939 case VCVTPD2QQZ256rrkz:
25940 case VCVTPD2QQZrm:
25941 case VCVTPD2QQZrmb:
25942 case VCVTPD2QQZrmbk:
25943 case VCVTPD2QQZrmbkz:
25944 case VCVTPD2QQZrmk:
25945 case VCVTPD2QQZrmkz:
25946 case VCVTPD2QQZrr:
25947 case VCVTPD2QQZrrb:
25948 case VCVTPD2QQZrrbk:
25949 case VCVTPD2QQZrrbkz:
25950 case VCVTPD2QQZrrk:
25951 case VCVTPD2QQZrrkz:
25952 return true;
25953 }
25954 return false;
25955}
25956
25957bool isVGETEXPPS(unsigned Opcode) {
25958 switch (Opcode) {
25959 case VGETEXPPSZ128m:
25960 case VGETEXPPSZ128mb:
25961 case VGETEXPPSZ128mbk:
25962 case VGETEXPPSZ128mbkz:
25963 case VGETEXPPSZ128mk:
25964 case VGETEXPPSZ128mkz:
25965 case VGETEXPPSZ128r:
25966 case VGETEXPPSZ128rk:
25967 case VGETEXPPSZ128rkz:
25968 case VGETEXPPSZ256m:
25969 case VGETEXPPSZ256mb:
25970 case VGETEXPPSZ256mbk:
25971 case VGETEXPPSZ256mbkz:
25972 case VGETEXPPSZ256mk:
25973 case VGETEXPPSZ256mkz:
25974 case VGETEXPPSZ256r:
25975 case VGETEXPPSZ256rk:
25976 case VGETEXPPSZ256rkz:
25977 case VGETEXPPSZm:
25978 case VGETEXPPSZmb:
25979 case VGETEXPPSZmbk:
25980 case VGETEXPPSZmbkz:
25981 case VGETEXPPSZmk:
25982 case VGETEXPPSZmkz:
25983 case VGETEXPPSZr:
25984 case VGETEXPPSZrb:
25985 case VGETEXPPSZrbk:
25986 case VGETEXPPSZrbkz:
25987 case VGETEXPPSZrk:
25988 case VGETEXPPSZrkz:
25989 return true;
25990 }
25991 return false;
25992}
25993
25994bool isFISTP(unsigned Opcode) {
25995 switch (Opcode) {
25996 case IST_FP16m:
25997 case IST_FP32m:
25998 case IST_FP64m:
25999 return true;
26000 }
26001 return false;
26002}
26003
26004bool isVINSERTF64X4(unsigned Opcode) {
26005 switch (Opcode) {
26006 case VINSERTF64X4Zrmi:
26007 case VINSERTF64X4Zrmik:
26008 case VINSERTF64X4Zrmikz:
26009 case VINSERTF64X4Zrri:
26010 case VINSERTF64X4Zrrik:
26011 case VINSERTF64X4Zrrikz:
26012 return true;
26013 }
26014 return false;
26015}
26016
26017bool isVMOVDQU16(unsigned Opcode) {
26018 switch (Opcode) {
26019 case VMOVDQU16Z128mr:
26020 case VMOVDQU16Z128mrk:
26021 case VMOVDQU16Z128rm:
26022 case VMOVDQU16Z128rmk:
26023 case VMOVDQU16Z128rmkz:
26024 case VMOVDQU16Z128rr:
26025 case VMOVDQU16Z128rr_REV:
26026 case VMOVDQU16Z128rrk:
26027 case VMOVDQU16Z128rrk_REV:
26028 case VMOVDQU16Z128rrkz:
26029 case VMOVDQU16Z128rrkz_REV:
26030 case VMOVDQU16Z256mr:
26031 case VMOVDQU16Z256mrk:
26032 case VMOVDQU16Z256rm:
26033 case VMOVDQU16Z256rmk:
26034 case VMOVDQU16Z256rmkz:
26035 case VMOVDQU16Z256rr:
26036 case VMOVDQU16Z256rr_REV:
26037 case VMOVDQU16Z256rrk:
26038 case VMOVDQU16Z256rrk_REV:
26039 case VMOVDQU16Z256rrkz:
26040 case VMOVDQU16Z256rrkz_REV:
26041 case VMOVDQU16Zmr:
26042 case VMOVDQU16Zmrk:
26043 case VMOVDQU16Zrm:
26044 case VMOVDQU16Zrmk:
26045 case VMOVDQU16Zrmkz:
26046 case VMOVDQU16Zrr:
26047 case VMOVDQU16Zrr_REV:
26048 case VMOVDQU16Zrrk:
26049 case VMOVDQU16Zrrk_REV:
26050 case VMOVDQU16Zrrkz:
26051 case VMOVDQU16Zrrkz_REV:
26052 return true;
26053 }
26054 return false;
26055}
26056
26057bool isVFMADD132PH(unsigned Opcode) {
26058 switch (Opcode) {
26059 case VFMADD132PHZ128m:
26060 case VFMADD132PHZ128mb:
26061 case VFMADD132PHZ128mbk:
26062 case VFMADD132PHZ128mbkz:
26063 case VFMADD132PHZ128mk:
26064 case VFMADD132PHZ128mkz:
26065 case VFMADD132PHZ128r:
26066 case VFMADD132PHZ128rk:
26067 case VFMADD132PHZ128rkz:
26068 case VFMADD132PHZ256m:
26069 case VFMADD132PHZ256mb:
26070 case VFMADD132PHZ256mbk:
26071 case VFMADD132PHZ256mbkz:
26072 case VFMADD132PHZ256mk:
26073 case VFMADD132PHZ256mkz:
26074 case VFMADD132PHZ256r:
26075 case VFMADD132PHZ256rk:
26076 case VFMADD132PHZ256rkz:
26077 case VFMADD132PHZm:
26078 case VFMADD132PHZmb:
26079 case VFMADD132PHZmbk:
26080 case VFMADD132PHZmbkz:
26081 case VFMADD132PHZmk:
26082 case VFMADD132PHZmkz:
26083 case VFMADD132PHZr:
26084 case VFMADD132PHZrb:
26085 case VFMADD132PHZrbk:
26086 case VFMADD132PHZrbkz:
26087 case VFMADD132PHZrk:
26088 case VFMADD132PHZrkz:
26089 return true;
26090 }
26091 return false;
26092}
26093
26094bool isVFMSUBADD213PS(unsigned Opcode) {
26095 switch (Opcode) {
26096 case VFMSUBADD213PSYm:
26097 case VFMSUBADD213PSYr:
26098 case VFMSUBADD213PSZ128m:
26099 case VFMSUBADD213PSZ128mb:
26100 case VFMSUBADD213PSZ128mbk:
26101 case VFMSUBADD213PSZ128mbkz:
26102 case VFMSUBADD213PSZ128mk:
26103 case VFMSUBADD213PSZ128mkz:
26104 case VFMSUBADD213PSZ128r:
26105 case VFMSUBADD213PSZ128rk:
26106 case VFMSUBADD213PSZ128rkz:
26107 case VFMSUBADD213PSZ256m:
26108 case VFMSUBADD213PSZ256mb:
26109 case VFMSUBADD213PSZ256mbk:
26110 case VFMSUBADD213PSZ256mbkz:
26111 case VFMSUBADD213PSZ256mk:
26112 case VFMSUBADD213PSZ256mkz:
26113 case VFMSUBADD213PSZ256r:
26114 case VFMSUBADD213PSZ256rk:
26115 case VFMSUBADD213PSZ256rkz:
26116 case VFMSUBADD213PSZm:
26117 case VFMSUBADD213PSZmb:
26118 case VFMSUBADD213PSZmbk:
26119 case VFMSUBADD213PSZmbkz:
26120 case VFMSUBADD213PSZmk:
26121 case VFMSUBADD213PSZmkz:
26122 case VFMSUBADD213PSZr:
26123 case VFMSUBADD213PSZrb:
26124 case VFMSUBADD213PSZrbk:
26125 case VFMSUBADD213PSZrbkz:
26126 case VFMSUBADD213PSZrk:
26127 case VFMSUBADD213PSZrkz:
26128 case VFMSUBADD213PSm:
26129 case VFMSUBADD213PSr:
26130 return true;
26131 }
26132 return false;
26133}
26134
26135bool isVMOVDQU32(unsigned Opcode) {
26136 switch (Opcode) {
26137 case VMOVDQU32Z128mr:
26138 case VMOVDQU32Z128mrk:
26139 case VMOVDQU32Z128rm:
26140 case VMOVDQU32Z128rmk:
26141 case VMOVDQU32Z128rmkz:
26142 case VMOVDQU32Z128rr:
26143 case VMOVDQU32Z128rr_REV:
26144 case VMOVDQU32Z128rrk:
26145 case VMOVDQU32Z128rrk_REV:
26146 case VMOVDQU32Z128rrkz:
26147 case VMOVDQU32Z128rrkz_REV:
26148 case VMOVDQU32Z256mr:
26149 case VMOVDQU32Z256mrk:
26150 case VMOVDQU32Z256rm:
26151 case VMOVDQU32Z256rmk:
26152 case VMOVDQU32Z256rmkz:
26153 case VMOVDQU32Z256rr:
26154 case VMOVDQU32Z256rr_REV:
26155 case VMOVDQU32Z256rrk:
26156 case VMOVDQU32Z256rrk_REV:
26157 case VMOVDQU32Z256rrkz:
26158 case VMOVDQU32Z256rrkz_REV:
26159 case VMOVDQU32Zmr:
26160 case VMOVDQU32Zmrk:
26161 case VMOVDQU32Zrm:
26162 case VMOVDQU32Zrmk:
26163 case VMOVDQU32Zrmkz:
26164 case VMOVDQU32Zrr:
26165 case VMOVDQU32Zrr_REV:
26166 case VMOVDQU32Zrrk:
26167 case VMOVDQU32Zrrk_REV:
26168 case VMOVDQU32Zrrkz:
26169 case VMOVDQU32Zrrkz_REV:
26170 return true;
26171 }
26172 return false;
26173}
26174
26175bool isFUCOM(unsigned Opcode) {
26176 return Opcode == UCOM_Fr;
26177}
26178
26179bool isVFNMADD213BF16(unsigned Opcode) {
26180 switch (Opcode) {
26181 case VFNMADD213BF16Z128m:
26182 case VFNMADD213BF16Z128mb:
26183 case VFNMADD213BF16Z128mbk:
26184 case VFNMADD213BF16Z128mbkz:
26185 case VFNMADD213BF16Z128mk:
26186 case VFNMADD213BF16Z128mkz:
26187 case VFNMADD213BF16Z128r:
26188 case VFNMADD213BF16Z128rk:
26189 case VFNMADD213BF16Z128rkz:
26190 case VFNMADD213BF16Z256m:
26191 case VFNMADD213BF16Z256mb:
26192 case VFNMADD213BF16Z256mbk:
26193 case VFNMADD213BF16Z256mbkz:
26194 case VFNMADD213BF16Z256mk:
26195 case VFNMADD213BF16Z256mkz:
26196 case VFNMADD213BF16Z256r:
26197 case VFNMADD213BF16Z256rk:
26198 case VFNMADD213BF16Z256rkz:
26199 case VFNMADD213BF16Zm:
26200 case VFNMADD213BF16Zmb:
26201 case VFNMADD213BF16Zmbk:
26202 case VFNMADD213BF16Zmbkz:
26203 case VFNMADD213BF16Zmk:
26204 case VFNMADD213BF16Zmkz:
26205 case VFNMADD213BF16Zr:
26206 case VFNMADD213BF16Zrk:
26207 case VFNMADD213BF16Zrkz:
26208 return true;
26209 }
26210 return false;
26211}
26212
26213bool isHADDPS(unsigned Opcode) {
26214 switch (Opcode) {
26215 case HADDPSrm:
26216 case HADDPSrr:
26217 return true;
26218 }
26219 return false;
26220}
26221
26222bool isCMP(unsigned Opcode) {
26223 switch (Opcode) {
26224 case CMP16i16:
26225 case CMP16mi:
26226 case CMP16mi8:
26227 case CMP16mr:
26228 case CMP16ri:
26229 case CMP16ri8:
26230 case CMP16rm:
26231 case CMP16rr:
26232 case CMP16rr_REV:
26233 case CMP32i32:
26234 case CMP32mi:
26235 case CMP32mi8:
26236 case CMP32mr:
26237 case CMP32ri:
26238 case CMP32ri8:
26239 case CMP32rm:
26240 case CMP32rr:
26241 case CMP32rr_REV:
26242 case CMP64i32:
26243 case CMP64mi32:
26244 case CMP64mi8:
26245 case CMP64mr:
26246 case CMP64ri32:
26247 case CMP64ri8:
26248 case CMP64rm:
26249 case CMP64rr:
26250 case CMP64rr_REV:
26251 case CMP8i8:
26252 case CMP8mi:
26253 case CMP8mi8:
26254 case CMP8mr:
26255 case CMP8ri:
26256 case CMP8ri8:
26257 case CMP8rm:
26258 case CMP8rr:
26259 case CMP8rr_REV:
26260 return true;
26261 }
26262 return false;
26263}
26264
26265bool isCVTTPS2PI(unsigned Opcode) {
26266 switch (Opcode) {
26267 case MMX_CVTTPS2PIrm:
26268 case MMX_CVTTPS2PIrr:
26269 return true;
26270 }
26271 return false;
26272}
26273
26274bool isIRETQ(unsigned Opcode) {
26275 return Opcode == IRET64;
26276}
26277
26278bool isPF2IW(unsigned Opcode) {
26279 switch (Opcode) {
26280 case PF2IWrm:
26281 case PF2IWrr:
26282 return true;
26283 }
26284 return false;
26285}
26286
26287bool isPSHUFD(unsigned Opcode) {
26288 switch (Opcode) {
26289 case PSHUFDmi:
26290 case PSHUFDri:
26291 return true;
26292 }
26293 return false;
26294}
26295
26296bool isVDPPD(unsigned Opcode) {
26297 switch (Opcode) {
26298 case VDPPDrmi:
26299 case VDPPDrri:
26300 return true;
26301 }
26302 return false;
26303}
26304
26305bool isPSHUFHW(unsigned Opcode) {
26306 switch (Opcode) {
26307 case PSHUFHWmi:
26308 case PSHUFHWri:
26309 return true;
26310 }
26311 return false;
26312}
26313
26314bool isRMPADJUST(unsigned Opcode) {
26315 return Opcode == RMPADJUST;
26316}
26317
26318bool isPI2FW(unsigned Opcode) {
26319 switch (Opcode) {
26320 case PI2FWrm:
26321 case PI2FWrr:
26322 return true;
26323 }
26324 return false;
26325}
26326
26327bool isVCVTTPH2QQ(unsigned Opcode) {
26328 switch (Opcode) {
26329 case VCVTTPH2QQZ128rm:
26330 case VCVTTPH2QQZ128rmb:
26331 case VCVTTPH2QQZ128rmbk:
26332 case VCVTTPH2QQZ128rmbkz:
26333 case VCVTTPH2QQZ128rmk:
26334 case VCVTTPH2QQZ128rmkz:
26335 case VCVTTPH2QQZ128rr:
26336 case VCVTTPH2QQZ128rrk:
26337 case VCVTTPH2QQZ128rrkz:
26338 case VCVTTPH2QQZ256rm:
26339 case VCVTTPH2QQZ256rmb:
26340 case VCVTTPH2QQZ256rmbk:
26341 case VCVTTPH2QQZ256rmbkz:
26342 case VCVTTPH2QQZ256rmk:
26343 case VCVTTPH2QQZ256rmkz:
26344 case VCVTTPH2QQZ256rr:
26345 case VCVTTPH2QQZ256rrk:
26346 case VCVTTPH2QQZ256rrkz:
26347 case VCVTTPH2QQZrm:
26348 case VCVTTPH2QQZrmb:
26349 case VCVTTPH2QQZrmbk:
26350 case VCVTTPH2QQZrmbkz:
26351 case VCVTTPH2QQZrmk:
26352 case VCVTTPH2QQZrmkz:
26353 case VCVTTPH2QQZrr:
26354 case VCVTTPH2QQZrrb:
26355 case VCVTTPH2QQZrrbk:
26356 case VCVTTPH2QQZrrbkz:
26357 case VCVTTPH2QQZrrk:
26358 case VCVTTPH2QQZrrkz:
26359 return true;
26360 }
26361 return false;
26362}
26363
26364bool isDIVPD(unsigned Opcode) {
26365 switch (Opcode) {
26366 case DIVPDrm:
26367 case DIVPDrr:
26368 return true;
26369 }
26370 return false;
26371}
26372
26373bool isCLFLUSH(unsigned Opcode) {
26374 return Opcode == CLFLUSH;
26375}
26376
26377bool isVPMINUW(unsigned Opcode) {
26378 switch (Opcode) {
26379 case VPMINUWYrm:
26380 case VPMINUWYrr:
26381 case VPMINUWZ128rm:
26382 case VPMINUWZ128rmk:
26383 case VPMINUWZ128rmkz:
26384 case VPMINUWZ128rr:
26385 case VPMINUWZ128rrk:
26386 case VPMINUWZ128rrkz:
26387 case VPMINUWZ256rm:
26388 case VPMINUWZ256rmk:
26389 case VPMINUWZ256rmkz:
26390 case VPMINUWZ256rr:
26391 case VPMINUWZ256rrk:
26392 case VPMINUWZ256rrkz:
26393 case VPMINUWZrm:
26394 case VPMINUWZrmk:
26395 case VPMINUWZrmkz:
26396 case VPMINUWZrr:
26397 case VPMINUWZrrk:
26398 case VPMINUWZrrkz:
26399 case VPMINUWrm:
26400 case VPMINUWrr:
26401 return true;
26402 }
26403 return false;
26404}
26405
26406bool isIN(unsigned Opcode) {
26407 switch (Opcode) {
26408 case IN16ri:
26409 case IN16rr:
26410 case IN32ri:
26411 case IN32rr:
26412 case IN8ri:
26413 case IN8rr:
26414 return true;
26415 }
26416 return false;
26417}
26418
26419bool isWRPKRU(unsigned Opcode) {
26420 return Opcode == WRPKRUr;
26421}
26422
26423bool isINSERTPS(unsigned Opcode) {
26424 switch (Opcode) {
26425 case INSERTPSrmi:
26426 case INSERTPSrri:
26427 return true;
26428 }
26429 return false;
26430}
26431
26432bool isAAM(unsigned Opcode) {
26433 return Opcode == AAM8i8;
26434}
26435
26436bool isVPHADDUDQ(unsigned Opcode) {
26437 switch (Opcode) {
26438 case VPHADDUDQrm:
26439 case VPHADDUDQrr:
26440 return true;
26441 }
26442 return false;
26443}
26444
26445bool isVSHA512MSG1(unsigned Opcode) {
26446 return Opcode == VSHA512MSG1rr;
26447}
26448
26449bool isDIVPS(unsigned Opcode) {
26450 switch (Opcode) {
26451 case DIVPSrm:
26452 case DIVPSrr:
26453 return true;
26454 }
26455 return false;
26456}
26457
26458bool isKNOTB(unsigned Opcode) {
26459 return Opcode == KNOTBkk;
26460}
26461
26462bool isBLSFILL(unsigned Opcode) {
26463 switch (Opcode) {
26464 case BLSFILL32rm:
26465 case BLSFILL32rr:
26466 case BLSFILL64rm:
26467 case BLSFILL64rr:
26468 return true;
26469 }
26470 return false;
26471}
26472
26473bool isVPCMPGTQ(unsigned Opcode) {
26474 switch (Opcode) {
26475 case VPCMPGTQYrm:
26476 case VPCMPGTQYrr:
26477 case VPCMPGTQZ128rm:
26478 case VPCMPGTQZ128rmb:
26479 case VPCMPGTQZ128rmbk:
26480 case VPCMPGTQZ128rmk:
26481 case VPCMPGTQZ128rr:
26482 case VPCMPGTQZ128rrk:
26483 case VPCMPGTQZ256rm:
26484 case VPCMPGTQZ256rmb:
26485 case VPCMPGTQZ256rmbk:
26486 case VPCMPGTQZ256rmk:
26487 case VPCMPGTQZ256rr:
26488 case VPCMPGTQZ256rrk:
26489 case VPCMPGTQZrm:
26490 case VPCMPGTQZrmb:
26491 case VPCMPGTQZrmbk:
26492 case VPCMPGTQZrmk:
26493 case VPCMPGTQZrr:
26494 case VPCMPGTQZrrk:
26495 case VPCMPGTQrm:
26496 case VPCMPGTQrr:
26497 return true;
26498 }
26499 return false;
26500}
26501
26502bool isMINSD(unsigned Opcode) {
26503 switch (Opcode) {
26504 case MINSDrm_Int:
26505 case MINSDrr_Int:
26506 return true;
26507 }
26508 return false;
26509}
26510
26511bool isFPREM(unsigned Opcode) {
26512 return Opcode == FPREM;
26513}
26514
26515bool isVPUNPCKHQDQ(unsigned Opcode) {
26516 switch (Opcode) {
26517 case VPUNPCKHQDQYrm:
26518 case VPUNPCKHQDQYrr:
26519 case VPUNPCKHQDQZ128rm:
26520 case VPUNPCKHQDQZ128rmb:
26521 case VPUNPCKHQDQZ128rmbk:
26522 case VPUNPCKHQDQZ128rmbkz:
26523 case VPUNPCKHQDQZ128rmk:
26524 case VPUNPCKHQDQZ128rmkz:
26525 case VPUNPCKHQDQZ128rr:
26526 case VPUNPCKHQDQZ128rrk:
26527 case VPUNPCKHQDQZ128rrkz:
26528 case VPUNPCKHQDQZ256rm:
26529 case VPUNPCKHQDQZ256rmb:
26530 case VPUNPCKHQDQZ256rmbk:
26531 case VPUNPCKHQDQZ256rmbkz:
26532 case VPUNPCKHQDQZ256rmk:
26533 case VPUNPCKHQDQZ256rmkz:
26534 case VPUNPCKHQDQZ256rr:
26535 case VPUNPCKHQDQZ256rrk:
26536 case VPUNPCKHQDQZ256rrkz:
26537 case VPUNPCKHQDQZrm:
26538 case VPUNPCKHQDQZrmb:
26539 case VPUNPCKHQDQZrmbk:
26540 case VPUNPCKHQDQZrmbkz:
26541 case VPUNPCKHQDQZrmk:
26542 case VPUNPCKHQDQZrmkz:
26543 case VPUNPCKHQDQZrr:
26544 case VPUNPCKHQDQZrrk:
26545 case VPUNPCKHQDQZrrkz:
26546 case VPUNPCKHQDQrm:
26547 case VPUNPCKHQDQrr:
26548 return true;
26549 }
26550 return false;
26551}
26552
26553bool isMINPD(unsigned Opcode) {
26554 switch (Opcode) {
26555 case MINPDrm:
26556 case MINPDrr:
26557 return true;
26558 }
26559 return false;
26560}
26561
26562bool isVCVTTPD2QQ(unsigned Opcode) {
26563 switch (Opcode) {
26564 case VCVTTPD2QQZ128rm:
26565 case VCVTTPD2QQZ128rmb:
26566 case VCVTTPD2QQZ128rmbk:
26567 case VCVTTPD2QQZ128rmbkz:
26568 case VCVTTPD2QQZ128rmk:
26569 case VCVTTPD2QQZ128rmkz:
26570 case VCVTTPD2QQZ128rr:
26571 case VCVTTPD2QQZ128rrk:
26572 case VCVTTPD2QQZ128rrkz:
26573 case VCVTTPD2QQZ256rm:
26574 case VCVTTPD2QQZ256rmb:
26575 case VCVTTPD2QQZ256rmbk:
26576 case VCVTTPD2QQZ256rmbkz:
26577 case VCVTTPD2QQZ256rmk:
26578 case VCVTTPD2QQZ256rmkz:
26579 case VCVTTPD2QQZ256rr:
26580 case VCVTTPD2QQZ256rrk:
26581 case VCVTTPD2QQZ256rrkz:
26582 case VCVTTPD2QQZrm:
26583 case VCVTTPD2QQZrmb:
26584 case VCVTTPD2QQZrmbk:
26585 case VCVTTPD2QQZrmbkz:
26586 case VCVTTPD2QQZrmk:
26587 case VCVTTPD2QQZrmkz:
26588 case VCVTTPD2QQZrr:
26589 case VCVTTPD2QQZrrb:
26590 case VCVTTPD2QQZrrbk:
26591 case VCVTTPD2QQZrrbkz:
26592 case VCVTTPD2QQZrrk:
26593 case VCVTTPD2QQZrrkz:
26594 return true;
26595 }
26596 return false;
26597}
26598
26599bool isVFMSUBPD(unsigned Opcode) {
26600 switch (Opcode) {
26601 case VFMSUBPD4Ymr:
26602 case VFMSUBPD4Yrm:
26603 case VFMSUBPD4Yrr:
26604 case VFMSUBPD4Yrr_REV:
26605 case VFMSUBPD4mr:
26606 case VFMSUBPD4rm:
26607 case VFMSUBPD4rr:
26608 case VFMSUBPD4rr_REV:
26609 return true;
26610 }
26611 return false;
26612}
26613
26614bool isV4FMADDSS(unsigned Opcode) {
26615 switch (Opcode) {
26616 case V4FMADDSSrm:
26617 case V4FMADDSSrmk:
26618 case V4FMADDSSrmkz:
26619 return true;
26620 }
26621 return false;
26622}
26623
26624bool isCPUID(unsigned Opcode) {
26625 return Opcode == CPUID;
26626}
26627
26628bool isSETCC(unsigned Opcode) {
26629 switch (Opcode) {
26630 case SETCCm:
26631 case SETCCm_EVEX:
26632 case SETCCr:
26633 case SETCCr_EVEX:
26634 return true;
26635 }
26636 return false;
26637}
26638
26639bool isVPDPWUUD(unsigned Opcode) {
26640 switch (Opcode) {
26641 case VPDPWUUDYrm:
26642 case VPDPWUUDYrr:
26643 case VPDPWUUDZ128rm:
26644 case VPDPWUUDZ128rmb:
26645 case VPDPWUUDZ128rmbk:
26646 case VPDPWUUDZ128rmbkz:
26647 case VPDPWUUDZ128rmk:
26648 case VPDPWUUDZ128rmkz:
26649 case VPDPWUUDZ128rr:
26650 case VPDPWUUDZ128rrk:
26651 case VPDPWUUDZ128rrkz:
26652 case VPDPWUUDZ256rm:
26653 case VPDPWUUDZ256rmb:
26654 case VPDPWUUDZ256rmbk:
26655 case VPDPWUUDZ256rmbkz:
26656 case VPDPWUUDZ256rmk:
26657 case VPDPWUUDZ256rmkz:
26658 case VPDPWUUDZ256rr:
26659 case VPDPWUUDZ256rrk:
26660 case VPDPWUUDZ256rrkz:
26661 case VPDPWUUDZrm:
26662 case VPDPWUUDZrmb:
26663 case VPDPWUUDZrmbk:
26664 case VPDPWUUDZrmbkz:
26665 case VPDPWUUDZrmk:
26666 case VPDPWUUDZrmkz:
26667 case VPDPWUUDZrr:
26668 case VPDPWUUDZrrk:
26669 case VPDPWUUDZrrkz:
26670 case VPDPWUUDrm:
26671 case VPDPWUUDrr:
26672 return true;
26673 }
26674 return false;
26675}
26676
26677bool isVCVTTPS2IUBS(unsigned Opcode) {
26678 switch (Opcode) {
26679 case VCVTTPS2IUBSZ128rm:
26680 case VCVTTPS2IUBSZ128rmb:
26681 case VCVTTPS2IUBSZ128rmbk:
26682 case VCVTTPS2IUBSZ128rmbkz:
26683 case VCVTTPS2IUBSZ128rmk:
26684 case VCVTTPS2IUBSZ128rmkz:
26685 case VCVTTPS2IUBSZ128rr:
26686 case VCVTTPS2IUBSZ128rrk:
26687 case VCVTTPS2IUBSZ128rrkz:
26688 case VCVTTPS2IUBSZ256rm:
26689 case VCVTTPS2IUBSZ256rmb:
26690 case VCVTTPS2IUBSZ256rmbk:
26691 case VCVTTPS2IUBSZ256rmbkz:
26692 case VCVTTPS2IUBSZ256rmk:
26693 case VCVTTPS2IUBSZ256rmkz:
26694 case VCVTTPS2IUBSZ256rr:
26695 case VCVTTPS2IUBSZ256rrk:
26696 case VCVTTPS2IUBSZ256rrkz:
26697 case VCVTTPS2IUBSZrm:
26698 case VCVTTPS2IUBSZrmb:
26699 case VCVTTPS2IUBSZrmbk:
26700 case VCVTTPS2IUBSZrmbkz:
26701 case VCVTTPS2IUBSZrmk:
26702 case VCVTTPS2IUBSZrmkz:
26703 case VCVTTPS2IUBSZrr:
26704 case VCVTTPS2IUBSZrrb:
26705 case VCVTTPS2IUBSZrrbk:
26706 case VCVTTPS2IUBSZrrbkz:
26707 case VCVTTPS2IUBSZrrk:
26708 case VCVTTPS2IUBSZrrkz:
26709 return true;
26710 }
26711 return false;
26712}
26713
26714bool isPMOVSXDQ(unsigned Opcode) {
26715 switch (Opcode) {
26716 case PMOVSXDQrm:
26717 case PMOVSXDQrr:
26718 return true;
26719 }
26720 return false;
26721}
26722
26723bool isMWAIT(unsigned Opcode) {
26724 return Opcode == MWAITrr;
26725}
26726
26727bool isVPEXTRB(unsigned Opcode) {
26728 switch (Opcode) {
26729 case VPEXTRBZmri:
26730 case VPEXTRBZrri:
26731 case VPEXTRBmri:
26732 case VPEXTRBrri:
26733 return true;
26734 }
26735 return false;
26736}
26737
26738bool isRMPCHKD(unsigned Opcode) {
26739 return Opcode == RMPCHKD;
26740}
26741
26742bool isINVVPID(unsigned Opcode) {
26743 switch (Opcode) {
26744 case INVVPID32:
26745 case INVVPID64:
26746 case INVVPID64_EVEX:
26747 return true;
26748 }
26749 return false;
26750}
26751
26752bool isVPSHUFD(unsigned Opcode) {
26753 switch (Opcode) {
26754 case VPSHUFDYmi:
26755 case VPSHUFDYri:
26756 case VPSHUFDZ128mbi:
26757 case VPSHUFDZ128mbik:
26758 case VPSHUFDZ128mbikz:
26759 case VPSHUFDZ128mi:
26760 case VPSHUFDZ128mik:
26761 case VPSHUFDZ128mikz:
26762 case VPSHUFDZ128ri:
26763 case VPSHUFDZ128rik:
26764 case VPSHUFDZ128rikz:
26765 case VPSHUFDZ256mbi:
26766 case VPSHUFDZ256mbik:
26767 case VPSHUFDZ256mbikz:
26768 case VPSHUFDZ256mi:
26769 case VPSHUFDZ256mik:
26770 case VPSHUFDZ256mikz:
26771 case VPSHUFDZ256ri:
26772 case VPSHUFDZ256rik:
26773 case VPSHUFDZ256rikz:
26774 case VPSHUFDZmbi:
26775 case VPSHUFDZmbik:
26776 case VPSHUFDZmbikz:
26777 case VPSHUFDZmi:
26778 case VPSHUFDZmik:
26779 case VPSHUFDZmikz:
26780 case VPSHUFDZri:
26781 case VPSHUFDZrik:
26782 case VPSHUFDZrikz:
26783 case VPSHUFDmi:
26784 case VPSHUFDri:
26785 return true;
26786 }
26787 return false;
26788}
26789
26790bool isVMINBF16(unsigned Opcode) {
26791 switch (Opcode) {
26792 case VMINBF16Z128rm:
26793 case VMINBF16Z128rmb:
26794 case VMINBF16Z128rmbk:
26795 case VMINBF16Z128rmbkz:
26796 case VMINBF16Z128rmk:
26797 case VMINBF16Z128rmkz:
26798 case VMINBF16Z128rr:
26799 case VMINBF16Z128rrk:
26800 case VMINBF16Z128rrkz:
26801 case VMINBF16Z256rm:
26802 case VMINBF16Z256rmb:
26803 case VMINBF16Z256rmbk:
26804 case VMINBF16Z256rmbkz:
26805 case VMINBF16Z256rmk:
26806 case VMINBF16Z256rmkz:
26807 case VMINBF16Z256rr:
26808 case VMINBF16Z256rrk:
26809 case VMINBF16Z256rrkz:
26810 case VMINBF16Zrm:
26811 case VMINBF16Zrmb:
26812 case VMINBF16Zrmbk:
26813 case VMINBF16Zrmbkz:
26814 case VMINBF16Zrmk:
26815 case VMINBF16Zrmkz:
26816 case VMINBF16Zrr:
26817 case VMINBF16Zrrk:
26818 case VMINBF16Zrrkz:
26819 return true;
26820 }
26821 return false;
26822}
26823
26824bool isMOVLPS(unsigned Opcode) {
26825 switch (Opcode) {
26826 case MOVLPSmr:
26827 case MOVLPSrm:
26828 return true;
26829 }
26830 return false;
26831}
26832
26833bool isVBLENDMPS(unsigned Opcode) {
26834 switch (Opcode) {
26835 case VBLENDMPSZ128rm:
26836 case VBLENDMPSZ128rmb:
26837 case VBLENDMPSZ128rmbk:
26838 case VBLENDMPSZ128rmbkz:
26839 case VBLENDMPSZ128rmk:
26840 case VBLENDMPSZ128rmkz:
26841 case VBLENDMPSZ128rr:
26842 case VBLENDMPSZ128rrk:
26843 case VBLENDMPSZ128rrkz:
26844 case VBLENDMPSZ256rm:
26845 case VBLENDMPSZ256rmb:
26846 case VBLENDMPSZ256rmbk:
26847 case VBLENDMPSZ256rmbkz:
26848 case VBLENDMPSZ256rmk:
26849 case VBLENDMPSZ256rmkz:
26850 case VBLENDMPSZ256rr:
26851 case VBLENDMPSZ256rrk:
26852 case VBLENDMPSZ256rrkz:
26853 case VBLENDMPSZrm:
26854 case VBLENDMPSZrmb:
26855 case VBLENDMPSZrmbk:
26856 case VBLENDMPSZrmbkz:
26857 case VBLENDMPSZrmk:
26858 case VBLENDMPSZrmkz:
26859 case VBLENDMPSZrr:
26860 case VBLENDMPSZrrk:
26861 case VBLENDMPSZrrkz:
26862 return true;
26863 }
26864 return false;
26865}
26866
26867bool isPMULLW(unsigned Opcode) {
26868 switch (Opcode) {
26869 case MMX_PMULLWrm:
26870 case MMX_PMULLWrr:
26871 case PMULLWrm:
26872 case PMULLWrr:
26873 return true;
26874 }
26875 return false;
26876}
26877
26878bool isVCVTSH2SI(unsigned Opcode) {
26879 switch (Opcode) {
26880 case VCVTSH2SI64Zrm_Int:
26881 case VCVTSH2SI64Zrr_Int:
26882 case VCVTSH2SI64Zrrb_Int:
26883 case VCVTSH2SIZrm_Int:
26884 case VCVTSH2SIZrr_Int:
26885 case VCVTSH2SIZrrb_Int:
26886 return true;
26887 }
26888 return false;
26889}
26890
26891bool isVPMOVSXWQ(unsigned Opcode) {
26892 switch (Opcode) {
26893 case VPMOVSXWQYrm:
26894 case VPMOVSXWQYrr:
26895 case VPMOVSXWQZ128rm:
26896 case VPMOVSXWQZ128rmk:
26897 case VPMOVSXWQZ128rmkz:
26898 case VPMOVSXWQZ128rr:
26899 case VPMOVSXWQZ128rrk:
26900 case VPMOVSXWQZ128rrkz:
26901 case VPMOVSXWQZ256rm:
26902 case VPMOVSXWQZ256rmk:
26903 case VPMOVSXWQZ256rmkz:
26904 case VPMOVSXWQZ256rr:
26905 case VPMOVSXWQZ256rrk:
26906 case VPMOVSXWQZ256rrkz:
26907 case VPMOVSXWQZrm:
26908 case VPMOVSXWQZrmk:
26909 case VPMOVSXWQZrmkz:
26910 case VPMOVSXWQZrr:
26911 case VPMOVSXWQZrrk:
26912 case VPMOVSXWQZrrkz:
26913 case VPMOVSXWQrm:
26914 case VPMOVSXWQrr:
26915 return true;
26916 }
26917 return false;
26918}
26919
26920bool isFNSTENV(unsigned Opcode) {
26921 return Opcode == FSTENVm;
26922}
26923
26924bool isVCVT2PH2BF8(unsigned Opcode) {
26925 switch (Opcode) {
26926 case VCVT2PH2BF8Z128rm:
26927 case VCVT2PH2BF8Z128rmb:
26928 case VCVT2PH2BF8Z128rmbk:
26929 case VCVT2PH2BF8Z128rmbkz:
26930 case VCVT2PH2BF8Z128rmk:
26931 case VCVT2PH2BF8Z128rmkz:
26932 case VCVT2PH2BF8Z128rr:
26933 case VCVT2PH2BF8Z128rrk:
26934 case VCVT2PH2BF8Z128rrkz:
26935 case VCVT2PH2BF8Z256rm:
26936 case VCVT2PH2BF8Z256rmb:
26937 case VCVT2PH2BF8Z256rmbk:
26938 case VCVT2PH2BF8Z256rmbkz:
26939 case VCVT2PH2BF8Z256rmk:
26940 case VCVT2PH2BF8Z256rmkz:
26941 case VCVT2PH2BF8Z256rr:
26942 case VCVT2PH2BF8Z256rrk:
26943 case VCVT2PH2BF8Z256rrkz:
26944 case VCVT2PH2BF8Zrm:
26945 case VCVT2PH2BF8Zrmb:
26946 case VCVT2PH2BF8Zrmbk:
26947 case VCVT2PH2BF8Zrmbkz:
26948 case VCVT2PH2BF8Zrmk:
26949 case VCVT2PH2BF8Zrmkz:
26950 case VCVT2PH2BF8Zrr:
26951 case VCVT2PH2BF8Zrrk:
26952 case VCVT2PH2BF8Zrrkz:
26953 return true;
26954 }
26955 return false;
26956}
26957
26958bool isVPERMI2PD(unsigned Opcode) {
26959 switch (Opcode) {
26960 case VPERMI2PDZ128rm:
26961 case VPERMI2PDZ128rmb:
26962 case VPERMI2PDZ128rmbk:
26963 case VPERMI2PDZ128rmbkz:
26964 case VPERMI2PDZ128rmk:
26965 case VPERMI2PDZ128rmkz:
26966 case VPERMI2PDZ128rr:
26967 case VPERMI2PDZ128rrk:
26968 case VPERMI2PDZ128rrkz:
26969 case VPERMI2PDZ256rm:
26970 case VPERMI2PDZ256rmb:
26971 case VPERMI2PDZ256rmbk:
26972 case VPERMI2PDZ256rmbkz:
26973 case VPERMI2PDZ256rmk:
26974 case VPERMI2PDZ256rmkz:
26975 case VPERMI2PDZ256rr:
26976 case VPERMI2PDZ256rrk:
26977 case VPERMI2PDZ256rrkz:
26978 case VPERMI2PDZrm:
26979 case VPERMI2PDZrmb:
26980 case VPERMI2PDZrmbk:
26981 case VPERMI2PDZrmbkz:
26982 case VPERMI2PDZrmk:
26983 case VPERMI2PDZrmkz:
26984 case VPERMI2PDZrr:
26985 case VPERMI2PDZrrk:
26986 case VPERMI2PDZrrkz:
26987 return true;
26988 }
26989 return false;
26990}
26991
26992bool isMAXSS(unsigned Opcode) {
26993 switch (Opcode) {
26994 case MAXSSrm_Int:
26995 case MAXSSrr_Int:
26996 return true;
26997 }
26998 return false;
26999}
27000
27001bool isCWDE(unsigned Opcode) {
27002 return Opcode == CWDE;
27003}
27004
27005bool isVBROADCASTI32X8(unsigned Opcode) {
27006 switch (Opcode) {
27007 case VBROADCASTI32X8Zrm:
27008 case VBROADCASTI32X8Zrmk:
27009 case VBROADCASTI32X8Zrmkz:
27010 return true;
27011 }
27012 return false;
27013}
27014
27015bool isINT(unsigned Opcode) {
27016 return Opcode == INT;
27017}
27018
27019bool isENCLS(unsigned Opcode) {
27020 return Opcode == ENCLS;
27021}
27022
27023bool isMOVNTQ(unsigned Opcode) {
27024 return Opcode == MMX_MOVNTQmr;
27025}
27026
27027bool isVDIVSH(unsigned Opcode) {
27028 switch (Opcode) {
27029 case VDIVSHZrm_Int:
27030 case VDIVSHZrmk_Int:
27031 case VDIVSHZrmkz_Int:
27032 case VDIVSHZrr_Int:
27033 case VDIVSHZrrb_Int:
27034 case VDIVSHZrrbk_Int:
27035 case VDIVSHZrrbkz_Int:
27036 case VDIVSHZrrk_Int:
27037 case VDIVSHZrrkz_Int:
27038 return true;
27039 }
27040 return false;
27041}
27042
27043bool isMOVHLPS(unsigned Opcode) {
27044 return Opcode == MOVHLPSrr;
27045}
27046
27047bool isVPMASKMOVD(unsigned Opcode) {
27048 switch (Opcode) {
27049 case VPMASKMOVDYmr:
27050 case VPMASKMOVDYrm:
27051 case VPMASKMOVDmr:
27052 case VPMASKMOVDrm:
27053 return true;
27054 }
27055 return false;
27056}
27057
27058bool isVMOVSD(unsigned Opcode) {
27059 switch (Opcode) {
27060 case VMOVSDZmr:
27061 case VMOVSDZmrk:
27062 case VMOVSDZrm:
27063 case VMOVSDZrmk:
27064 case VMOVSDZrmkz:
27065 case VMOVSDZrr:
27066 case VMOVSDZrr_REV:
27067 case VMOVSDZrrk:
27068 case VMOVSDZrrk_REV:
27069 case VMOVSDZrrkz:
27070 case VMOVSDZrrkz_REV:
27071 case VMOVSDmr:
27072 case VMOVSDrm:
27073 case VMOVSDrr:
27074 case VMOVSDrr_REV:
27075 return true;
27076 }
27077 return false;
27078}
27079
27080bool isVPMINUD(unsigned Opcode) {
27081 switch (Opcode) {
27082 case VPMINUDYrm:
27083 case VPMINUDYrr:
27084 case VPMINUDZ128rm:
27085 case VPMINUDZ128rmb:
27086 case VPMINUDZ128rmbk:
27087 case VPMINUDZ128rmbkz:
27088 case VPMINUDZ128rmk:
27089 case VPMINUDZ128rmkz:
27090 case VPMINUDZ128rr:
27091 case VPMINUDZ128rrk:
27092 case VPMINUDZ128rrkz:
27093 case VPMINUDZ256rm:
27094 case VPMINUDZ256rmb:
27095 case VPMINUDZ256rmbk:
27096 case VPMINUDZ256rmbkz:
27097 case VPMINUDZ256rmk:
27098 case VPMINUDZ256rmkz:
27099 case VPMINUDZ256rr:
27100 case VPMINUDZ256rrk:
27101 case VPMINUDZ256rrkz:
27102 case VPMINUDZrm:
27103 case VPMINUDZrmb:
27104 case VPMINUDZrmbk:
27105 case VPMINUDZrmbkz:
27106 case VPMINUDZrmk:
27107 case VPMINUDZrmkz:
27108 case VPMINUDZrr:
27109 case VPMINUDZrrk:
27110 case VPMINUDZrrkz:
27111 case VPMINUDrm:
27112 case VPMINUDrr:
27113 return true;
27114 }
27115 return false;
27116}
27117
27118bool isVPCMPISTRM(unsigned Opcode) {
27119 switch (Opcode) {
27120 case VPCMPISTRMrmi:
27121 case VPCMPISTRMrri:
27122 return true;
27123 }
27124 return false;
27125}
27126
27127bool isVGETMANTSD(unsigned Opcode) {
27128 switch (Opcode) {
27129 case VGETMANTSDZrmi:
27130 case VGETMANTSDZrmik:
27131 case VGETMANTSDZrmikz:
27132 case VGETMANTSDZrri:
27133 case VGETMANTSDZrrib:
27134 case VGETMANTSDZrribk:
27135 case VGETMANTSDZrribkz:
27136 case VGETMANTSDZrrik:
27137 case VGETMANTSDZrrikz:
27138 return true;
27139 }
27140 return false;
27141}
27142
27143bool isKSHIFTRW(unsigned Opcode) {
27144 return Opcode == KSHIFTRWki;
27145}
27146
27147bool isAESDECLAST(unsigned Opcode) {
27148 switch (Opcode) {
27149 case AESDECLASTrm:
27150 case AESDECLASTrr:
27151 return true;
27152 }
27153 return false;
27154}
27155
27156bool isVPTESTMB(unsigned Opcode) {
27157 switch (Opcode) {
27158 case VPTESTMBZ128rm:
27159 case VPTESTMBZ128rmk:
27160 case VPTESTMBZ128rr:
27161 case VPTESTMBZ128rrk:
27162 case VPTESTMBZ256rm:
27163 case VPTESTMBZ256rmk:
27164 case VPTESTMBZ256rr:
27165 case VPTESTMBZ256rrk:
27166 case VPTESTMBZrm:
27167 case VPTESTMBZrmk:
27168 case VPTESTMBZrr:
27169 case VPTESTMBZrrk:
27170 return true;
27171 }
27172 return false;
27173}
27174
27175bool isVFNMSUB231BF16(unsigned Opcode) {
27176 switch (Opcode) {
27177 case VFNMSUB231BF16Z128m:
27178 case VFNMSUB231BF16Z128mb:
27179 case VFNMSUB231BF16Z128mbk:
27180 case VFNMSUB231BF16Z128mbkz:
27181 case VFNMSUB231BF16Z128mk:
27182 case VFNMSUB231BF16Z128mkz:
27183 case VFNMSUB231BF16Z128r:
27184 case VFNMSUB231BF16Z128rk:
27185 case VFNMSUB231BF16Z128rkz:
27186 case VFNMSUB231BF16Z256m:
27187 case VFNMSUB231BF16Z256mb:
27188 case VFNMSUB231BF16Z256mbk:
27189 case VFNMSUB231BF16Z256mbkz:
27190 case VFNMSUB231BF16Z256mk:
27191 case VFNMSUB231BF16Z256mkz:
27192 case VFNMSUB231BF16Z256r:
27193 case VFNMSUB231BF16Z256rk:
27194 case VFNMSUB231BF16Z256rkz:
27195 case VFNMSUB231BF16Zm:
27196 case VFNMSUB231BF16Zmb:
27197 case VFNMSUB231BF16Zmbk:
27198 case VFNMSUB231BF16Zmbkz:
27199 case VFNMSUB231BF16Zmk:
27200 case VFNMSUB231BF16Zmkz:
27201 case VFNMSUB231BF16Zr:
27202 case VFNMSUB231BF16Zrk:
27203 case VFNMSUB231BF16Zrkz:
27204 return true;
27205 }
27206 return false;
27207}
27208
27209bool isVMPTRST(unsigned Opcode) {
27210 return Opcode == VMPTRSTm;
27211}
27212
27213bool isLLDT(unsigned Opcode) {
27214 switch (Opcode) {
27215 case LLDT16m:
27216 case LLDT16r:
27217 return true;
27218 }
27219 return false;
27220}
27221
27222bool isMOVSB(unsigned Opcode) {
27223 return Opcode == MOVSB;
27224}
27225
27226bool isTILELOADD(unsigned Opcode) {
27227 switch (Opcode) {
27228 case TILELOADD:
27229 case TILELOADD_EVEX:
27230 return true;
27231 }
27232 return false;
27233}
27234
27235bool isKTESTB(unsigned Opcode) {
27236 return Opcode == KTESTBkk;
27237}
27238
27239bool isMOVUPD(unsigned Opcode) {
27240 switch (Opcode) {
27241 case MOVUPDmr:
27242 case MOVUPDrm:
27243 case MOVUPDrr:
27244 case MOVUPDrr_REV:
27245 return true;
27246 }
27247 return false;
27248}
27249
27250bool isLKGS(unsigned Opcode) {
27251 switch (Opcode) {
27252 case LKGS16m:
27253 case LKGS16r:
27254 return true;
27255 }
27256 return false;
27257}
27258
27259bool isSGDTW(unsigned Opcode) {
27260 return Opcode == SGDT16m;
27261}
27262
27263bool isDIVSS(unsigned Opcode) {
27264 switch (Opcode) {
27265 case DIVSSrm_Int:
27266 case DIVSSrr_Int:
27267 return true;
27268 }
27269 return false;
27270}
27271
27272bool isPUNPCKHQDQ(unsigned Opcode) {
27273 switch (Opcode) {
27274 case PUNPCKHQDQrm:
27275 case PUNPCKHQDQrr:
27276 return true;
27277 }
27278 return false;
27279}
27280
27281bool isVFMADD213SD(unsigned Opcode) {
27282 switch (Opcode) {
27283 case VFMADD213SDZm_Int:
27284 case VFMADD213SDZmk_Int:
27285 case VFMADD213SDZmkz_Int:
27286 case VFMADD213SDZr_Int:
27287 case VFMADD213SDZrb_Int:
27288 case VFMADD213SDZrbk_Int:
27289 case VFMADD213SDZrbkz_Int:
27290 case VFMADD213SDZrk_Int:
27291 case VFMADD213SDZrkz_Int:
27292 case VFMADD213SDm_Int:
27293 case VFMADD213SDr_Int:
27294 return true;
27295 }
27296 return false;
27297}
27298
27299bool isKXORD(unsigned Opcode) {
27300 return Opcode == KXORDkk;
27301}
27302
27303bool isVPMOVB2M(unsigned Opcode) {
27304 switch (Opcode) {
27305 case VPMOVB2MZ128kr:
27306 case VPMOVB2MZ256kr:
27307 case VPMOVB2MZkr:
27308 return true;
27309 }
27310 return false;
27311}
27312
27313bool isVMREAD(unsigned Opcode) {
27314 switch (Opcode) {
27315 case VMREAD32mr:
27316 case VMREAD32rr:
27317 case VMREAD64mr:
27318 case VMREAD64rr:
27319 return true;
27320 }
27321 return false;
27322}
27323
27324bool isVPDPWSSDS(unsigned Opcode) {
27325 switch (Opcode) {
27326 case VPDPWSSDSYrm:
27327 case VPDPWSSDSYrr:
27328 case VPDPWSSDSZ128rm:
27329 case VPDPWSSDSZ128rmb:
27330 case VPDPWSSDSZ128rmbk:
27331 case VPDPWSSDSZ128rmbkz:
27332 case VPDPWSSDSZ128rmk:
27333 case VPDPWSSDSZ128rmkz:
27334 case VPDPWSSDSZ128rr:
27335 case VPDPWSSDSZ128rrk:
27336 case VPDPWSSDSZ128rrkz:
27337 case VPDPWSSDSZ256rm:
27338 case VPDPWSSDSZ256rmb:
27339 case VPDPWSSDSZ256rmbk:
27340 case VPDPWSSDSZ256rmbkz:
27341 case VPDPWSSDSZ256rmk:
27342 case VPDPWSSDSZ256rmkz:
27343 case VPDPWSSDSZ256rr:
27344 case VPDPWSSDSZ256rrk:
27345 case VPDPWSSDSZ256rrkz:
27346 case VPDPWSSDSZrm:
27347 case VPDPWSSDSZrmb:
27348 case VPDPWSSDSZrmbk:
27349 case VPDPWSSDSZrmbkz:
27350 case VPDPWSSDSZrmk:
27351 case VPDPWSSDSZrmkz:
27352 case VPDPWSSDSZrr:
27353 case VPDPWSSDSZrrk:
27354 case VPDPWSSDSZrrkz:
27355 case VPDPWSSDSrm:
27356 case VPDPWSSDSrr:
27357 return true;
27358 }
27359 return false;
27360}
27361
27362bool isTILERELEASE(unsigned Opcode) {
27363 return Opcode == TILERELEASE;
27364}
27365
27366bool isVUCOMXSH(unsigned Opcode) {
27367 switch (Opcode) {
27368 case VUCOMXSHZrm_Int:
27369 case VUCOMXSHZrr_Int:
27370 case VUCOMXSHZrrb_Int:
27371 return true;
27372 }
27373 return false;
27374}
27375
27376bool isCLFLUSHOPT(unsigned Opcode) {
27377 return Opcode == CLFLUSHOPT;
27378}
27379
27380bool isDAS(unsigned Opcode) {
27381 return Opcode == DAS;
27382}
27383
27384bool isVSCALEFPH(unsigned Opcode) {
27385 switch (Opcode) {
27386 case VSCALEFPHZ128rm:
27387 case VSCALEFPHZ128rmb:
27388 case VSCALEFPHZ128rmbk:
27389 case VSCALEFPHZ128rmbkz:
27390 case VSCALEFPHZ128rmk:
27391 case VSCALEFPHZ128rmkz:
27392 case VSCALEFPHZ128rr:
27393 case VSCALEFPHZ128rrk:
27394 case VSCALEFPHZ128rrkz:
27395 case VSCALEFPHZ256rm:
27396 case VSCALEFPHZ256rmb:
27397 case VSCALEFPHZ256rmbk:
27398 case VSCALEFPHZ256rmbkz:
27399 case VSCALEFPHZ256rmk:
27400 case VSCALEFPHZ256rmkz:
27401 case VSCALEFPHZ256rr:
27402 case VSCALEFPHZ256rrk:
27403 case VSCALEFPHZ256rrkz:
27404 case VSCALEFPHZrm:
27405 case VSCALEFPHZrmb:
27406 case VSCALEFPHZrmbk:
27407 case VSCALEFPHZrmbkz:
27408 case VSCALEFPHZrmk:
27409 case VSCALEFPHZrmkz:
27410 case VSCALEFPHZrr:
27411 case VSCALEFPHZrrb:
27412 case VSCALEFPHZrrbk:
27413 case VSCALEFPHZrrbkz:
27414 case VSCALEFPHZrrk:
27415 case VSCALEFPHZrrkz:
27416 return true;
27417 }
27418 return false;
27419}
27420
27421bool isVSUBSD(unsigned Opcode) {
27422 switch (Opcode) {
27423 case VSUBSDZrm_Int:
27424 case VSUBSDZrmk_Int:
27425 case VSUBSDZrmkz_Int:
27426 case VSUBSDZrr_Int:
27427 case VSUBSDZrrb_Int:
27428 case VSUBSDZrrbk_Int:
27429 case VSUBSDZrrbkz_Int:
27430 case VSUBSDZrrk_Int:
27431 case VSUBSDZrrkz_Int:
27432 case VSUBSDrm_Int:
27433 case VSUBSDrr_Int:
27434 return true;
27435 }
27436 return false;
27437}
27438
27439bool isVCOMISS(unsigned Opcode) {
27440 switch (Opcode) {
27441 case VCOMISSZrm:
27442 case VCOMISSZrr:
27443 case VCOMISSZrrb:
27444 case VCOMISSrm:
27445 case VCOMISSrr:
27446 return true;
27447 }
27448 return false;
27449}
27450
27451bool isVMULBF16(unsigned Opcode) {
27452 switch (Opcode) {
27453 case VMULBF16Z128rm:
27454 case VMULBF16Z128rmb:
27455 case VMULBF16Z128rmbk:
27456 case VMULBF16Z128rmbkz:
27457 case VMULBF16Z128rmk:
27458 case VMULBF16Z128rmkz:
27459 case VMULBF16Z128rr:
27460 case VMULBF16Z128rrk:
27461 case VMULBF16Z128rrkz:
27462 case VMULBF16Z256rm:
27463 case VMULBF16Z256rmb:
27464 case VMULBF16Z256rmbk:
27465 case VMULBF16Z256rmbkz:
27466 case VMULBF16Z256rmk:
27467 case VMULBF16Z256rmkz:
27468 case VMULBF16Z256rr:
27469 case VMULBF16Z256rrk:
27470 case VMULBF16Z256rrkz:
27471 case VMULBF16Zrm:
27472 case VMULBF16Zrmb:
27473 case VMULBF16Zrmbk:
27474 case VMULBF16Zrmbkz:
27475 case VMULBF16Zrmk:
27476 case VMULBF16Zrmkz:
27477 case VMULBF16Zrr:
27478 case VMULBF16Zrrk:
27479 case VMULBF16Zrrkz:
27480 return true;
27481 }
27482 return false;
27483}
27484
27485bool isORPS(unsigned Opcode) {
27486 switch (Opcode) {
27487 case ORPSrm:
27488 case ORPSrr:
27489 return true;
27490 }
27491 return false;
27492}
27493
27494bool isTDPFP16PS(unsigned Opcode) {
27495 return Opcode == TDPFP16PS;
27496}
27497
27498bool isVMAXPD(unsigned Opcode) {
27499 switch (Opcode) {
27500 case VMAXPDYrm:
27501 case VMAXPDYrr:
27502 case VMAXPDZ128rm:
27503 case VMAXPDZ128rmb:
27504 case VMAXPDZ128rmbk:
27505 case VMAXPDZ128rmbkz:
27506 case VMAXPDZ128rmk:
27507 case VMAXPDZ128rmkz:
27508 case VMAXPDZ128rr:
27509 case VMAXPDZ128rrk:
27510 case VMAXPDZ128rrkz:
27511 case VMAXPDZ256rm:
27512 case VMAXPDZ256rmb:
27513 case VMAXPDZ256rmbk:
27514 case VMAXPDZ256rmbkz:
27515 case VMAXPDZ256rmk:
27516 case VMAXPDZ256rmkz:
27517 case VMAXPDZ256rr:
27518 case VMAXPDZ256rrk:
27519 case VMAXPDZ256rrkz:
27520 case VMAXPDZrm:
27521 case VMAXPDZrmb:
27522 case VMAXPDZrmbk:
27523 case VMAXPDZrmbkz:
27524 case VMAXPDZrmk:
27525 case VMAXPDZrmkz:
27526 case VMAXPDZrr:
27527 case VMAXPDZrrb:
27528 case VMAXPDZrrbk:
27529 case VMAXPDZrrbkz:
27530 case VMAXPDZrrk:
27531 case VMAXPDZrrkz:
27532 case VMAXPDrm:
27533 case VMAXPDrr:
27534 return true;
27535 }
27536 return false;
27537}
27538
27539bool isVPMOVWB(unsigned Opcode) {
27540 switch (Opcode) {
27541 case VPMOVWBZ128mr:
27542 case VPMOVWBZ128mrk:
27543 case VPMOVWBZ128rr:
27544 case VPMOVWBZ128rrk:
27545 case VPMOVWBZ128rrkz:
27546 case VPMOVWBZ256mr:
27547 case VPMOVWBZ256mrk:
27548 case VPMOVWBZ256rr:
27549 case VPMOVWBZ256rrk:
27550 case VPMOVWBZ256rrkz:
27551 case VPMOVWBZmr:
27552 case VPMOVWBZmrk:
27553 case VPMOVWBZrr:
27554 case VPMOVWBZrrk:
27555 case VPMOVWBZrrkz:
27556 return true;
27557 }
27558 return false;
27559}
27560
27561bool isVEXP2PS(unsigned Opcode) {
27562 switch (Opcode) {
27563 case VEXP2PSZm:
27564 case VEXP2PSZmb:
27565 case VEXP2PSZmbk:
27566 case VEXP2PSZmbkz:
27567 case VEXP2PSZmk:
27568 case VEXP2PSZmkz:
27569 case VEXP2PSZr:
27570 case VEXP2PSZrb:
27571 case VEXP2PSZrbk:
27572 case VEXP2PSZrbkz:
27573 case VEXP2PSZrk:
27574 case VEXP2PSZrkz:
27575 return true;
27576 }
27577 return false;
27578}
27579
27580bool isVPGATHERDQ(unsigned Opcode) {
27581 switch (Opcode) {
27582 case VPGATHERDQYrm:
27583 case VPGATHERDQZ128rm:
27584 case VPGATHERDQZ256rm:
27585 case VPGATHERDQZrm:
27586 case VPGATHERDQrm:
27587 return true;
27588 }
27589 return false;
27590}
27591
27592bool isVPSRAVQ(unsigned Opcode) {
27593 switch (Opcode) {
27594 case VPSRAVQZ128rm:
27595 case VPSRAVQZ128rmb:
27596 case VPSRAVQZ128rmbk:
27597 case VPSRAVQZ128rmbkz:
27598 case VPSRAVQZ128rmk:
27599 case VPSRAVQZ128rmkz:
27600 case VPSRAVQZ128rr:
27601 case VPSRAVQZ128rrk:
27602 case VPSRAVQZ128rrkz:
27603 case VPSRAVQZ256rm:
27604 case VPSRAVQZ256rmb:
27605 case VPSRAVQZ256rmbk:
27606 case VPSRAVQZ256rmbkz:
27607 case VPSRAVQZ256rmk:
27608 case VPSRAVQZ256rmkz:
27609 case VPSRAVQZ256rr:
27610 case VPSRAVQZ256rrk:
27611 case VPSRAVQZ256rrkz:
27612 case VPSRAVQZrm:
27613 case VPSRAVQZrmb:
27614 case VPSRAVQZrmbk:
27615 case VPSRAVQZrmbkz:
27616 case VPSRAVQZrmk:
27617 case VPSRAVQZrmkz:
27618 case VPSRAVQZrr:
27619 case VPSRAVQZrrk:
27620 case VPSRAVQZrrkz:
27621 return true;
27622 }
27623 return false;
27624}
27625
27626bool isPCMPISTRI(unsigned Opcode) {
27627 switch (Opcode) {
27628 case PCMPISTRIrmi:
27629 case PCMPISTRIrri:
27630 return true;
27631 }
27632 return false;
27633}
27634
27635bool isVFMSUB231PD(unsigned Opcode) {
27636 switch (Opcode) {
27637 case VFMSUB231PDYm:
27638 case VFMSUB231PDYr:
27639 case VFMSUB231PDZ128m:
27640 case VFMSUB231PDZ128mb:
27641 case VFMSUB231PDZ128mbk:
27642 case VFMSUB231PDZ128mbkz:
27643 case VFMSUB231PDZ128mk:
27644 case VFMSUB231PDZ128mkz:
27645 case VFMSUB231PDZ128r:
27646 case VFMSUB231PDZ128rk:
27647 case VFMSUB231PDZ128rkz:
27648 case VFMSUB231PDZ256m:
27649 case VFMSUB231PDZ256mb:
27650 case VFMSUB231PDZ256mbk:
27651 case VFMSUB231PDZ256mbkz:
27652 case VFMSUB231PDZ256mk:
27653 case VFMSUB231PDZ256mkz:
27654 case VFMSUB231PDZ256r:
27655 case VFMSUB231PDZ256rk:
27656 case VFMSUB231PDZ256rkz:
27657 case VFMSUB231PDZm:
27658 case VFMSUB231PDZmb:
27659 case VFMSUB231PDZmbk:
27660 case VFMSUB231PDZmbkz:
27661 case VFMSUB231PDZmk:
27662 case VFMSUB231PDZmkz:
27663 case VFMSUB231PDZr:
27664 case VFMSUB231PDZrb:
27665 case VFMSUB231PDZrbk:
27666 case VFMSUB231PDZrbkz:
27667 case VFMSUB231PDZrk:
27668 case VFMSUB231PDZrkz:
27669 case VFMSUB231PDm:
27670 case VFMSUB231PDr:
27671 return true;
27672 }
27673 return false;
27674}
27675
27676bool isRDMSR(unsigned Opcode) {
27677 switch (Opcode) {
27678 case RDMSR:
27679 case RDMSRri:
27680 case RDMSRri_EVEX:
27681 return true;
27682 }
27683 return false;
27684}
27685
27686bool isKORTESTD(unsigned Opcode) {
27687 return Opcode == KORTESTDkk;
27688}
27689
27690bool isVPBLENDMW(unsigned Opcode) {
27691 switch (Opcode) {
27692 case VPBLENDMWZ128rm:
27693 case VPBLENDMWZ128rmk:
27694 case VPBLENDMWZ128rmkz:
27695 case VPBLENDMWZ128rr:
27696 case VPBLENDMWZ128rrk:
27697 case VPBLENDMWZ128rrkz:
27698 case VPBLENDMWZ256rm:
27699 case VPBLENDMWZ256rmk:
27700 case VPBLENDMWZ256rmkz:
27701 case VPBLENDMWZ256rr:
27702 case VPBLENDMWZ256rrk:
27703 case VPBLENDMWZ256rrkz:
27704 case VPBLENDMWZrm:
27705 case VPBLENDMWZrmk:
27706 case VPBLENDMWZrmkz:
27707 case VPBLENDMWZrr:
27708 case VPBLENDMWZrrk:
27709 case VPBLENDMWZrrkz:
27710 return true;
27711 }
27712 return false;
27713}
27714
27715bool isPSHUFB(unsigned Opcode) {
27716 switch (Opcode) {
27717 case MMX_PSHUFBrm:
27718 case MMX_PSHUFBrr:
27719 case PSHUFBrm:
27720 case PSHUFBrr:
27721 return true;
27722 }
27723 return false;
27724}
27725
27726bool isVDPBF16PS(unsigned Opcode) {
27727 switch (Opcode) {
27728 case VDPBF16PSZ128m:
27729 case VDPBF16PSZ128mb:
27730 case VDPBF16PSZ128mbk:
27731 case VDPBF16PSZ128mbkz:
27732 case VDPBF16PSZ128mk:
27733 case VDPBF16PSZ128mkz:
27734 case VDPBF16PSZ128r:
27735 case VDPBF16PSZ128rk:
27736 case VDPBF16PSZ128rkz:
27737 case VDPBF16PSZ256m:
27738 case VDPBF16PSZ256mb:
27739 case VDPBF16PSZ256mbk:
27740 case VDPBF16PSZ256mbkz:
27741 case VDPBF16PSZ256mk:
27742 case VDPBF16PSZ256mkz:
27743 case VDPBF16PSZ256r:
27744 case VDPBF16PSZ256rk:
27745 case VDPBF16PSZ256rkz:
27746 case VDPBF16PSZm:
27747 case VDPBF16PSZmb:
27748 case VDPBF16PSZmbk:
27749 case VDPBF16PSZmbkz:
27750 case VDPBF16PSZmk:
27751 case VDPBF16PSZmkz:
27752 case VDPBF16PSZr:
27753 case VDPBF16PSZrk:
27754 case VDPBF16PSZrkz:
27755 return true;
27756 }
27757 return false;
27758}
27759
27760bool isTDPBF16PS(unsigned Opcode) {
27761 return Opcode == TDPBF16PS;
27762}
27763
27764bool isFCMOVE(unsigned Opcode) {
27765 return Opcode == CMOVE_F;
27766}
27767
27768bool isVFMADD231BF16(unsigned Opcode) {
27769 switch (Opcode) {
27770 case VFMADD231BF16Z128m:
27771 case VFMADD231BF16Z128mb:
27772 case VFMADD231BF16Z128mbk:
27773 case VFMADD231BF16Z128mbkz:
27774 case VFMADD231BF16Z128mk:
27775 case VFMADD231BF16Z128mkz:
27776 case VFMADD231BF16Z128r:
27777 case VFMADD231BF16Z128rk:
27778 case VFMADD231BF16Z128rkz:
27779 case VFMADD231BF16Z256m:
27780 case VFMADD231BF16Z256mb:
27781 case VFMADD231BF16Z256mbk:
27782 case VFMADD231BF16Z256mbkz:
27783 case VFMADD231BF16Z256mk:
27784 case VFMADD231BF16Z256mkz:
27785 case VFMADD231BF16Z256r:
27786 case VFMADD231BF16Z256rk:
27787 case VFMADD231BF16Z256rkz:
27788 case VFMADD231BF16Zm:
27789 case VFMADD231BF16Zmb:
27790 case VFMADD231BF16Zmbk:
27791 case VFMADD231BF16Zmbkz:
27792 case VFMADD231BF16Zmk:
27793 case VFMADD231BF16Zmkz:
27794 case VFMADD231BF16Zr:
27795 case VFMADD231BF16Zrk:
27796 case VFMADD231BF16Zrkz:
27797 return true;
27798 }
27799 return false;
27800}
27801
27802bool isCMPSS(unsigned Opcode) {
27803 switch (Opcode) {
27804 case CMPSSrmi_Int:
27805 case CMPSSrri_Int:
27806 return true;
27807 }
27808 return false;
27809}
27810
27811bool isMASKMOVDQU(unsigned Opcode) {
27812 switch (Opcode) {
27813 case MASKMOVDQU:
27814 case MASKMOVDQU64:
27815 return true;
27816 }
27817 return false;
27818}
27819
27820bool isSARX(unsigned Opcode) {
27821 switch (Opcode) {
27822 case SARX32rm:
27823 case SARX32rm_EVEX:
27824 case SARX32rr:
27825 case SARX32rr_EVEX:
27826 case SARX64rm:
27827 case SARX64rm_EVEX:
27828 case SARX64rr:
27829 case SARX64rr_EVEX:
27830 return true;
27831 }
27832 return false;
27833}
27834
27835bool isVPDPWUSDS(unsigned Opcode) {
27836 switch (Opcode) {
27837 case VPDPWUSDSYrm:
27838 case VPDPWUSDSYrr:
27839 case VPDPWUSDSZ128rm:
27840 case VPDPWUSDSZ128rmb:
27841 case VPDPWUSDSZ128rmbk:
27842 case VPDPWUSDSZ128rmbkz:
27843 case VPDPWUSDSZ128rmk:
27844 case VPDPWUSDSZ128rmkz:
27845 case VPDPWUSDSZ128rr:
27846 case VPDPWUSDSZ128rrk:
27847 case VPDPWUSDSZ128rrkz:
27848 case VPDPWUSDSZ256rm:
27849 case VPDPWUSDSZ256rmb:
27850 case VPDPWUSDSZ256rmbk:
27851 case VPDPWUSDSZ256rmbkz:
27852 case VPDPWUSDSZ256rmk:
27853 case VPDPWUSDSZ256rmkz:
27854 case VPDPWUSDSZ256rr:
27855 case VPDPWUSDSZ256rrk:
27856 case VPDPWUSDSZ256rrkz:
27857 case VPDPWUSDSZrm:
27858 case VPDPWUSDSZrmb:
27859 case VPDPWUSDSZrmbk:
27860 case VPDPWUSDSZrmbkz:
27861 case VPDPWUSDSZrmk:
27862 case VPDPWUSDSZrmkz:
27863 case VPDPWUSDSZrr:
27864 case VPDPWUSDSZrrk:
27865 case VPDPWUSDSZrrkz:
27866 case VPDPWUSDSrm:
27867 case VPDPWUSDSrr:
27868 return true;
27869 }
27870 return false;
27871}
27872
27873bool isSGDT(unsigned Opcode) {
27874 return Opcode == SGDT64m;
27875}
27876
27877bool isVFMULCPH(unsigned Opcode) {
27878 switch (Opcode) {
27879 case VFMULCPHZ128rm:
27880 case VFMULCPHZ128rmb:
27881 case VFMULCPHZ128rmbk:
27882 case VFMULCPHZ128rmbkz:
27883 case VFMULCPHZ128rmk:
27884 case VFMULCPHZ128rmkz:
27885 case VFMULCPHZ128rr:
27886 case VFMULCPHZ128rrk:
27887 case VFMULCPHZ128rrkz:
27888 case VFMULCPHZ256rm:
27889 case VFMULCPHZ256rmb:
27890 case VFMULCPHZ256rmbk:
27891 case VFMULCPHZ256rmbkz:
27892 case VFMULCPHZ256rmk:
27893 case VFMULCPHZ256rmkz:
27894 case VFMULCPHZ256rr:
27895 case VFMULCPHZ256rrk:
27896 case VFMULCPHZ256rrkz:
27897 case VFMULCPHZrm:
27898 case VFMULCPHZrmb:
27899 case VFMULCPHZrmbk:
27900 case VFMULCPHZrmbkz:
27901 case VFMULCPHZrmk:
27902 case VFMULCPHZrmkz:
27903 case VFMULCPHZrr:
27904 case VFMULCPHZrrb:
27905 case VFMULCPHZrrbk:
27906 case VFMULCPHZrrbkz:
27907 case VFMULCPHZrrk:
27908 case VFMULCPHZrrkz:
27909 return true;
27910 }
27911 return false;
27912}
27913
27914bool isURDMSR(unsigned Opcode) {
27915 switch (Opcode) {
27916 case URDMSRri:
27917 case URDMSRri_EVEX:
27918 case URDMSRrr:
27919 case URDMSRrr_EVEX:
27920 return true;
27921 }
27922 return false;
27923}
27924
27925bool isKUNPCKWD(unsigned Opcode) {
27926 return Opcode == KUNPCKWDkk;
27927}
27928
27929bool isVSCALEFBF16(unsigned Opcode) {
27930 switch (Opcode) {
27931 case VSCALEFBF16Z128rm:
27932 case VSCALEFBF16Z128rmb:
27933 case VSCALEFBF16Z128rmbk:
27934 case VSCALEFBF16Z128rmbkz:
27935 case VSCALEFBF16Z128rmk:
27936 case VSCALEFBF16Z128rmkz:
27937 case VSCALEFBF16Z128rr:
27938 case VSCALEFBF16Z128rrk:
27939 case VSCALEFBF16Z128rrkz:
27940 case VSCALEFBF16Z256rm:
27941 case VSCALEFBF16Z256rmb:
27942 case VSCALEFBF16Z256rmbk:
27943 case VSCALEFBF16Z256rmbkz:
27944 case VSCALEFBF16Z256rmk:
27945 case VSCALEFBF16Z256rmkz:
27946 case VSCALEFBF16Z256rr:
27947 case VSCALEFBF16Z256rrk:
27948 case VSCALEFBF16Z256rrkz:
27949 case VSCALEFBF16Zrm:
27950 case VSCALEFBF16Zrmb:
27951 case VSCALEFBF16Zrmbk:
27952 case VSCALEFBF16Zrmbkz:
27953 case VSCALEFBF16Zrmk:
27954 case VSCALEFBF16Zrmkz:
27955 case VSCALEFBF16Zrr:
27956 case VSCALEFBF16Zrrk:
27957 case VSCALEFBF16Zrrkz:
27958 return true;
27959 }
27960 return false;
27961}
27962
27963bool isCVTPS2PD(unsigned Opcode) {
27964 switch (Opcode) {
27965 case CVTPS2PDrm:
27966 case CVTPS2PDrr:
27967 return true;
27968 }
27969 return false;
27970}
27971
27972bool isFBSTP(unsigned Opcode) {
27973 return Opcode == FBSTPm;
27974}
27975
27976bool isPSUBQ(unsigned Opcode) {
27977 switch (Opcode) {
27978 case MMX_PSUBQrm:
27979 case MMX_PSUBQrr:
27980 case PSUBQrm:
27981 case PSUBQrr:
27982 return true;
27983 }
27984 return false;
27985}
27986
27987bool isFXSAVE64(unsigned Opcode) {
27988 return Opcode == FXSAVE64;
27989}
27990
27991bool isKMOVW(unsigned Opcode) {
27992 switch (Opcode) {
27993 case KMOVWkk:
27994 case KMOVWkk_EVEX:
27995 case KMOVWkm:
27996 case KMOVWkm_EVEX:
27997 case KMOVWkr:
27998 case KMOVWkr_EVEX:
27999 case KMOVWmk:
28000 case KMOVWmk_EVEX:
28001 case KMOVWrk:
28002 case KMOVWrk_EVEX:
28003 return true;
28004 }
28005 return false;
28006}
28007
28008bool isBTS(unsigned Opcode) {
28009 switch (Opcode) {
28010 case BTS16mi8:
28011 case BTS16mr:
28012 case BTS16ri8:
28013 case BTS16rr:
28014 case BTS32mi8:
28015 case BTS32mr:
28016 case BTS32ri8:
28017 case BTS32rr:
28018 case BTS64mi8:
28019 case BTS64mr:
28020 case BTS64ri8:
28021 case BTS64rr:
28022 return true;
28023 }
28024 return false;
28025}
28026
28027bool isVPHADDBQ(unsigned Opcode) {
28028 switch (Opcode) {
28029 case VPHADDBQrm:
28030 case VPHADDBQrr:
28031 return true;
28032 }
28033 return false;
28034}
28035
28036bool isFRSTOR(unsigned Opcode) {
28037 return Opcode == FRSTORm;
28038}
28039
28040bool isVFMSUB132PD(unsigned Opcode) {
28041 switch (Opcode) {
28042 case VFMSUB132PDYm:
28043 case VFMSUB132PDYr:
28044 case VFMSUB132PDZ128m:
28045 case VFMSUB132PDZ128mb:
28046 case VFMSUB132PDZ128mbk:
28047 case VFMSUB132PDZ128mbkz:
28048 case VFMSUB132PDZ128mk:
28049 case VFMSUB132PDZ128mkz:
28050 case VFMSUB132PDZ128r:
28051 case VFMSUB132PDZ128rk:
28052 case VFMSUB132PDZ128rkz:
28053 case VFMSUB132PDZ256m:
28054 case VFMSUB132PDZ256mb:
28055 case VFMSUB132PDZ256mbk:
28056 case VFMSUB132PDZ256mbkz:
28057 case VFMSUB132PDZ256mk:
28058 case VFMSUB132PDZ256mkz:
28059 case VFMSUB132PDZ256r:
28060 case VFMSUB132PDZ256rk:
28061 case VFMSUB132PDZ256rkz:
28062 case VFMSUB132PDZm:
28063 case VFMSUB132PDZmb:
28064 case VFMSUB132PDZmbk:
28065 case VFMSUB132PDZmbkz:
28066 case VFMSUB132PDZmk:
28067 case VFMSUB132PDZmkz:
28068 case VFMSUB132PDZr:
28069 case VFMSUB132PDZrb:
28070 case VFMSUB132PDZrbk:
28071 case VFMSUB132PDZrbkz:
28072 case VFMSUB132PDZrk:
28073 case VFMSUB132PDZrkz:
28074 case VFMSUB132PDm:
28075 case VFMSUB132PDr:
28076 return true;
28077 }
28078 return false;
28079}
28080
28081bool isPMULLD(unsigned Opcode) {
28082 switch (Opcode) {
28083 case PMULLDrm:
28084 case PMULLDrr:
28085 return true;
28086 }
28087 return false;
28088}
28089
28090bool isSHA1MSG2(unsigned Opcode) {
28091 switch (Opcode) {
28092 case SHA1MSG2rm:
28093 case SHA1MSG2rr:
28094 return true;
28095 }
28096 return false;
28097}
28098
28099bool isJECXZ(unsigned Opcode) {
28100 return Opcode == JECXZ;
28101}
28102
28103bool isVCVTUDQ2PS(unsigned Opcode) {
28104 switch (Opcode) {
28105 case VCVTUDQ2PSZ128rm:
28106 case VCVTUDQ2PSZ128rmb:
28107 case VCVTUDQ2PSZ128rmbk:
28108 case VCVTUDQ2PSZ128rmbkz:
28109 case VCVTUDQ2PSZ128rmk:
28110 case VCVTUDQ2PSZ128rmkz:
28111 case VCVTUDQ2PSZ128rr:
28112 case VCVTUDQ2PSZ128rrk:
28113 case VCVTUDQ2PSZ128rrkz:
28114 case VCVTUDQ2PSZ256rm:
28115 case VCVTUDQ2PSZ256rmb:
28116 case VCVTUDQ2PSZ256rmbk:
28117 case VCVTUDQ2PSZ256rmbkz:
28118 case VCVTUDQ2PSZ256rmk:
28119 case VCVTUDQ2PSZ256rmkz:
28120 case VCVTUDQ2PSZ256rr:
28121 case VCVTUDQ2PSZ256rrk:
28122 case VCVTUDQ2PSZ256rrkz:
28123 case VCVTUDQ2PSZrm:
28124 case VCVTUDQ2PSZrmb:
28125 case VCVTUDQ2PSZrmbk:
28126 case VCVTUDQ2PSZrmbkz:
28127 case VCVTUDQ2PSZrmk:
28128 case VCVTUDQ2PSZrmkz:
28129 case VCVTUDQ2PSZrr:
28130 case VCVTUDQ2PSZrrb:
28131 case VCVTUDQ2PSZrrbk:
28132 case VCVTUDQ2PSZrrbkz:
28133 case VCVTUDQ2PSZrrk:
28134 case VCVTUDQ2PSZrrkz:
28135 return true;
28136 }
28137 return false;
28138}
28139
28140bool isAESENC(unsigned Opcode) {
28141 switch (Opcode) {
28142 case AESENCrm:
28143 case AESENCrr:
28144 return true;
28145 }
28146 return false;
28147}
28148
28149bool isVMINMAXPS(unsigned Opcode) {
28150 switch (Opcode) {
28151 case VMINMAXPSZ128rmbi:
28152 case VMINMAXPSZ128rmbik:
28153 case VMINMAXPSZ128rmbikz:
28154 case VMINMAXPSZ128rmi:
28155 case VMINMAXPSZ128rmik:
28156 case VMINMAXPSZ128rmikz:
28157 case VMINMAXPSZ128rri:
28158 case VMINMAXPSZ128rrik:
28159 case VMINMAXPSZ128rrikz:
28160 case VMINMAXPSZ256rmbi:
28161 case VMINMAXPSZ256rmbik:
28162 case VMINMAXPSZ256rmbikz:
28163 case VMINMAXPSZ256rmi:
28164 case VMINMAXPSZ256rmik:
28165 case VMINMAXPSZ256rmikz:
28166 case VMINMAXPSZ256rri:
28167 case VMINMAXPSZ256rrik:
28168 case VMINMAXPSZ256rrikz:
28169 case VMINMAXPSZrmbi:
28170 case VMINMAXPSZrmbik:
28171 case VMINMAXPSZrmbikz:
28172 case VMINMAXPSZrmi:
28173 case VMINMAXPSZrmik:
28174 case VMINMAXPSZrmikz:
28175 case VMINMAXPSZrri:
28176 case VMINMAXPSZrrib:
28177 case VMINMAXPSZrribk:
28178 case VMINMAXPSZrribkz:
28179 case VMINMAXPSZrrik:
28180 case VMINMAXPSZrrikz:
28181 return true;
28182 }
28183 return false;
28184}
28185
28186bool isPSIGNW(unsigned Opcode) {
28187 switch (Opcode) {
28188 case MMX_PSIGNWrm:
28189 case MMX_PSIGNWrr:
28190 case PSIGNWrm:
28191 case PSIGNWrr:
28192 return true;
28193 }
28194 return false;
28195}
28196
28197bool isUNPCKLPD(unsigned Opcode) {
28198 switch (Opcode) {
28199 case UNPCKLPDrm:
28200 case UNPCKLPDrr:
28201 return true;
28202 }
28203 return false;
28204}
28205
28206bool isPUSHP(unsigned Opcode) {
28207 return Opcode == PUSHP64r;
28208}
28209
28210bool isBLSI(unsigned Opcode) {
28211 switch (Opcode) {
28212 case BLSI32rm:
28213 case BLSI32rm_EVEX:
28214 case BLSI32rm_NF:
28215 case BLSI32rr:
28216 case BLSI32rr_EVEX:
28217 case BLSI32rr_NF:
28218 case BLSI64rm:
28219 case BLSI64rm_EVEX:
28220 case BLSI64rm_NF:
28221 case BLSI64rr:
28222 case BLSI64rr_EVEX:
28223 case BLSI64rr_NF:
28224 return true;
28225 }
28226 return false;
28227}
28228
28229bool isVPTESTNMB(unsigned Opcode) {
28230 switch (Opcode) {
28231 case VPTESTNMBZ128rm:
28232 case VPTESTNMBZ128rmk:
28233 case VPTESTNMBZ128rr:
28234 case VPTESTNMBZ128rrk:
28235 case VPTESTNMBZ256rm:
28236 case VPTESTNMBZ256rmk:
28237 case VPTESTNMBZ256rr:
28238 case VPTESTNMBZ256rrk:
28239 case VPTESTNMBZrm:
28240 case VPTESTNMBZrmk:
28241 case VPTESTNMBZrr:
28242 case VPTESTNMBZrrk:
28243 return true;
28244 }
28245 return false;
28246}
28247
28248bool isWRUSSQ(unsigned Opcode) {
28249 switch (Opcode) {
28250 case WRUSSQ:
28251 case WRUSSQ_EVEX:
28252 return true;
28253 }
28254 return false;
28255}
28256
28257bool isVGF2P8MULB(unsigned Opcode) {
28258 switch (Opcode) {
28259 case VGF2P8MULBYrm:
28260 case VGF2P8MULBYrr:
28261 case VGF2P8MULBZ128rm:
28262 case VGF2P8MULBZ128rmk:
28263 case VGF2P8MULBZ128rmkz:
28264 case VGF2P8MULBZ128rr:
28265 case VGF2P8MULBZ128rrk:
28266 case VGF2P8MULBZ128rrkz:
28267 case VGF2P8MULBZ256rm:
28268 case VGF2P8MULBZ256rmk:
28269 case VGF2P8MULBZ256rmkz:
28270 case VGF2P8MULBZ256rr:
28271 case VGF2P8MULBZ256rrk:
28272 case VGF2P8MULBZ256rrkz:
28273 case VGF2P8MULBZrm:
28274 case VGF2P8MULBZrmk:
28275 case VGF2P8MULBZrmkz:
28276 case VGF2P8MULBZrr:
28277 case VGF2P8MULBZrrk:
28278 case VGF2P8MULBZrrkz:
28279 case VGF2P8MULBrm:
28280 case VGF2P8MULBrr:
28281 return true;
28282 }
28283 return false;
28284}
28285
28286bool isVPUNPCKLBW(unsigned Opcode) {
28287 switch (Opcode) {
28288 case VPUNPCKLBWYrm:
28289 case VPUNPCKLBWYrr:
28290 case VPUNPCKLBWZ128rm:
28291 case VPUNPCKLBWZ128rmk:
28292 case VPUNPCKLBWZ128rmkz:
28293 case VPUNPCKLBWZ128rr:
28294 case VPUNPCKLBWZ128rrk:
28295 case VPUNPCKLBWZ128rrkz:
28296 case VPUNPCKLBWZ256rm:
28297 case VPUNPCKLBWZ256rmk:
28298 case VPUNPCKLBWZ256rmkz:
28299 case VPUNPCKLBWZ256rr:
28300 case VPUNPCKLBWZ256rrk:
28301 case VPUNPCKLBWZ256rrkz:
28302 case VPUNPCKLBWZrm:
28303 case VPUNPCKLBWZrmk:
28304 case VPUNPCKLBWZrmkz:
28305 case VPUNPCKLBWZrr:
28306 case VPUNPCKLBWZrrk:
28307 case VPUNPCKLBWZrrkz:
28308 case VPUNPCKLBWrm:
28309 case VPUNPCKLBWrr:
28310 return true;
28311 }
28312 return false;
28313}
28314
28315bool isVRANGESD(unsigned Opcode) {
28316 switch (Opcode) {
28317 case VRANGESDZrmi:
28318 case VRANGESDZrmik:
28319 case VRANGESDZrmikz:
28320 case VRANGESDZrri:
28321 case VRANGESDZrrib:
28322 case VRANGESDZrribk:
28323 case VRANGESDZrribkz:
28324 case VRANGESDZrrik:
28325 case VRANGESDZrrikz:
28326 return true;
28327 }
28328 return false;
28329}
28330
28331bool isCLD(unsigned Opcode) {
28332 return Opcode == CLD;
28333}
28334
28335bool isVSCALEFPD(unsigned Opcode) {
28336 switch (Opcode) {
28337 case VSCALEFPDZ128rm:
28338 case VSCALEFPDZ128rmb:
28339 case VSCALEFPDZ128rmbk:
28340 case VSCALEFPDZ128rmbkz:
28341 case VSCALEFPDZ128rmk:
28342 case VSCALEFPDZ128rmkz:
28343 case VSCALEFPDZ128rr:
28344 case VSCALEFPDZ128rrk:
28345 case VSCALEFPDZ128rrkz:
28346 case VSCALEFPDZ256rm:
28347 case VSCALEFPDZ256rmb:
28348 case VSCALEFPDZ256rmbk:
28349 case VSCALEFPDZ256rmbkz:
28350 case VSCALEFPDZ256rmk:
28351 case VSCALEFPDZ256rmkz:
28352 case VSCALEFPDZ256rr:
28353 case VSCALEFPDZ256rrk:
28354 case VSCALEFPDZ256rrkz:
28355 case VSCALEFPDZrm:
28356 case VSCALEFPDZrmb:
28357 case VSCALEFPDZrmbk:
28358 case VSCALEFPDZrmbkz:
28359 case VSCALEFPDZrmk:
28360 case VSCALEFPDZrmkz:
28361 case VSCALEFPDZrr:
28362 case VSCALEFPDZrrb:
28363 case VSCALEFPDZrrbk:
28364 case VSCALEFPDZrrbkz:
28365 case VSCALEFPDZrrk:
28366 case VSCALEFPDZrrkz:
28367 return true;
28368 }
28369 return false;
28370}
28371
28372bool isVCOMXSS(unsigned Opcode) {
28373 switch (Opcode) {
28374 case VCOMXSSZrm_Int:
28375 case VCOMXSSZrr_Int:
28376 case VCOMXSSZrrb_Int:
28377 return true;
28378 }
28379 return false;
28380}
28381
28382bool isVPERMQ(unsigned Opcode) {
28383 switch (Opcode) {
28384 case VPERMQYmi:
28385 case VPERMQYri:
28386 case VPERMQZ256mbi:
28387 case VPERMQZ256mbik:
28388 case VPERMQZ256mbikz:
28389 case VPERMQZ256mi:
28390 case VPERMQZ256mik:
28391 case VPERMQZ256mikz:
28392 case VPERMQZ256ri:
28393 case VPERMQZ256rik:
28394 case VPERMQZ256rikz:
28395 case VPERMQZ256rm:
28396 case VPERMQZ256rmb:
28397 case VPERMQZ256rmbk:
28398 case VPERMQZ256rmbkz:
28399 case VPERMQZ256rmk:
28400 case VPERMQZ256rmkz:
28401 case VPERMQZ256rr:
28402 case VPERMQZ256rrk:
28403 case VPERMQZ256rrkz:
28404 case VPERMQZmbi:
28405 case VPERMQZmbik:
28406 case VPERMQZmbikz:
28407 case VPERMQZmi:
28408 case VPERMQZmik:
28409 case VPERMQZmikz:
28410 case VPERMQZri:
28411 case VPERMQZrik:
28412 case VPERMQZrikz:
28413 case VPERMQZrm:
28414 case VPERMQZrmb:
28415 case VPERMQZrmbk:
28416 case VPERMQZrmbkz:
28417 case VPERMQZrmk:
28418 case VPERMQZrmkz:
28419 case VPERMQZrr:
28420 case VPERMQZrrk:
28421 case VPERMQZrrkz:
28422 return true;
28423 }
28424 return false;
28425}
28426
28427bool isVPSHLDVW(unsigned Opcode) {
28428 switch (Opcode) {
28429 case VPSHLDVWZ128m:
28430 case VPSHLDVWZ128mk:
28431 case VPSHLDVWZ128mkz:
28432 case VPSHLDVWZ128r:
28433 case VPSHLDVWZ128rk:
28434 case VPSHLDVWZ128rkz:
28435 case VPSHLDVWZ256m:
28436 case VPSHLDVWZ256mk:
28437 case VPSHLDVWZ256mkz:
28438 case VPSHLDVWZ256r:
28439 case VPSHLDVWZ256rk:
28440 case VPSHLDVWZ256rkz:
28441 case VPSHLDVWZm:
28442 case VPSHLDVWZmk:
28443 case VPSHLDVWZmkz:
28444 case VPSHLDVWZr:
28445 case VPSHLDVWZrk:
28446 case VPSHLDVWZrkz:
28447 return true;
28448 }
28449 return false;
28450}
28451
28452bool isROR(unsigned Opcode) {
28453 switch (Opcode) {
28454 case ROR16m1:
28455 case ROR16m1_EVEX:
28456 case ROR16m1_ND:
28457 case ROR16m1_NF:
28458 case ROR16m1_NF_ND:
28459 case ROR16mCL:
28460 case ROR16mCL_EVEX:
28461 case ROR16mCL_ND:
28462 case ROR16mCL_NF:
28463 case ROR16mCL_NF_ND:
28464 case ROR16mi:
28465 case ROR16mi_EVEX:
28466 case ROR16mi_ND:
28467 case ROR16mi_NF:
28468 case ROR16mi_NF_ND:
28469 case ROR16r1:
28470 case ROR16r1_EVEX:
28471 case ROR16r1_ND:
28472 case ROR16r1_NF:
28473 case ROR16r1_NF_ND:
28474 case ROR16rCL:
28475 case ROR16rCL_EVEX:
28476 case ROR16rCL_ND:
28477 case ROR16rCL_NF:
28478 case ROR16rCL_NF_ND:
28479 case ROR16ri:
28480 case ROR16ri_EVEX:
28481 case ROR16ri_ND:
28482 case ROR16ri_NF:
28483 case ROR16ri_NF_ND:
28484 case ROR32m1:
28485 case ROR32m1_EVEX:
28486 case ROR32m1_ND:
28487 case ROR32m1_NF:
28488 case ROR32m1_NF_ND:
28489 case ROR32mCL:
28490 case ROR32mCL_EVEX:
28491 case ROR32mCL_ND:
28492 case ROR32mCL_NF:
28493 case ROR32mCL_NF_ND:
28494 case ROR32mi:
28495 case ROR32mi_EVEX:
28496 case ROR32mi_ND:
28497 case ROR32mi_NF:
28498 case ROR32mi_NF_ND:
28499 case ROR32r1:
28500 case ROR32r1_EVEX:
28501 case ROR32r1_ND:
28502 case ROR32r1_NF:
28503 case ROR32r1_NF_ND:
28504 case ROR32rCL:
28505 case ROR32rCL_EVEX:
28506 case ROR32rCL_ND:
28507 case ROR32rCL_NF:
28508 case ROR32rCL_NF_ND:
28509 case ROR32ri:
28510 case ROR32ri_EVEX:
28511 case ROR32ri_ND:
28512 case ROR32ri_NF:
28513 case ROR32ri_NF_ND:
28514 case ROR64m1:
28515 case ROR64m1_EVEX:
28516 case ROR64m1_ND:
28517 case ROR64m1_NF:
28518 case ROR64m1_NF_ND:
28519 case ROR64mCL:
28520 case ROR64mCL_EVEX:
28521 case ROR64mCL_ND:
28522 case ROR64mCL_NF:
28523 case ROR64mCL_NF_ND:
28524 case ROR64mi:
28525 case ROR64mi_EVEX:
28526 case ROR64mi_ND:
28527 case ROR64mi_NF:
28528 case ROR64mi_NF_ND:
28529 case ROR64r1:
28530 case ROR64r1_EVEX:
28531 case ROR64r1_ND:
28532 case ROR64r1_NF:
28533 case ROR64r1_NF_ND:
28534 case ROR64rCL:
28535 case ROR64rCL_EVEX:
28536 case ROR64rCL_ND:
28537 case ROR64rCL_NF:
28538 case ROR64rCL_NF_ND:
28539 case ROR64ri:
28540 case ROR64ri_EVEX:
28541 case ROR64ri_ND:
28542 case ROR64ri_NF:
28543 case ROR64ri_NF_ND:
28544 case ROR8m1:
28545 case ROR8m1_EVEX:
28546 case ROR8m1_ND:
28547 case ROR8m1_NF:
28548 case ROR8m1_NF_ND:
28549 case ROR8mCL:
28550 case ROR8mCL_EVEX:
28551 case ROR8mCL_ND:
28552 case ROR8mCL_NF:
28553 case ROR8mCL_NF_ND:
28554 case ROR8mi:
28555 case ROR8mi_EVEX:
28556 case ROR8mi_ND:
28557 case ROR8mi_NF:
28558 case ROR8mi_NF_ND:
28559 case ROR8r1:
28560 case ROR8r1_EVEX:
28561 case ROR8r1_ND:
28562 case ROR8r1_NF:
28563 case ROR8r1_NF_ND:
28564 case ROR8rCL:
28565 case ROR8rCL_EVEX:
28566 case ROR8rCL_ND:
28567 case ROR8rCL_NF:
28568 case ROR8rCL_NF_ND:
28569 case ROR8ri:
28570 case ROR8ri_EVEX:
28571 case ROR8ri_ND:
28572 case ROR8ri_NF:
28573 case ROR8ri_NF_ND:
28574 return true;
28575 }
28576 return false;
28577}
28578
28579bool isVFMADDSUB132PH(unsigned Opcode) {
28580 switch (Opcode) {
28581 case VFMADDSUB132PHZ128m:
28582 case VFMADDSUB132PHZ128mb:
28583 case VFMADDSUB132PHZ128mbk:
28584 case VFMADDSUB132PHZ128mbkz:
28585 case VFMADDSUB132PHZ128mk:
28586 case VFMADDSUB132PHZ128mkz:
28587 case VFMADDSUB132PHZ128r:
28588 case VFMADDSUB132PHZ128rk:
28589 case VFMADDSUB132PHZ128rkz:
28590 case VFMADDSUB132PHZ256m:
28591 case VFMADDSUB132PHZ256mb:
28592 case VFMADDSUB132PHZ256mbk:
28593 case VFMADDSUB132PHZ256mbkz:
28594 case VFMADDSUB132PHZ256mk:
28595 case VFMADDSUB132PHZ256mkz:
28596 case VFMADDSUB132PHZ256r:
28597 case VFMADDSUB132PHZ256rk:
28598 case VFMADDSUB132PHZ256rkz:
28599 case VFMADDSUB132PHZm:
28600 case VFMADDSUB132PHZmb:
28601 case VFMADDSUB132PHZmbk:
28602 case VFMADDSUB132PHZmbkz:
28603 case VFMADDSUB132PHZmk:
28604 case VFMADDSUB132PHZmkz:
28605 case VFMADDSUB132PHZr:
28606 case VFMADDSUB132PHZrb:
28607 case VFMADDSUB132PHZrbk:
28608 case VFMADDSUB132PHZrbkz:
28609 case VFMADDSUB132PHZrk:
28610 case VFMADDSUB132PHZrkz:
28611 return true;
28612 }
28613 return false;
28614}
28615
28616bool isDEC(unsigned Opcode) {
28617 switch (Opcode) {
28618 case DEC16m:
28619 case DEC16m_EVEX:
28620 case DEC16m_ND:
28621 case DEC16m_NF:
28622 case DEC16m_NF_ND:
28623 case DEC16r:
28624 case DEC16r_EVEX:
28625 case DEC16r_ND:
28626 case DEC16r_NF:
28627 case DEC16r_NF_ND:
28628 case DEC16r_alt:
28629 case DEC32m:
28630 case DEC32m_EVEX:
28631 case DEC32m_ND:
28632 case DEC32m_NF:
28633 case DEC32m_NF_ND:
28634 case DEC32r:
28635 case DEC32r_EVEX:
28636 case DEC32r_ND:
28637 case DEC32r_NF:
28638 case DEC32r_NF_ND:
28639 case DEC32r_alt:
28640 case DEC64m:
28641 case DEC64m_EVEX:
28642 case DEC64m_ND:
28643 case DEC64m_NF:
28644 case DEC64m_NF_ND:
28645 case DEC64r:
28646 case DEC64r_EVEX:
28647 case DEC64r_ND:
28648 case DEC64r_NF:
28649 case DEC64r_NF_ND:
28650 case DEC8m:
28651 case DEC8m_EVEX:
28652 case DEC8m_ND:
28653 case DEC8m_NF:
28654 case DEC8m_NF_ND:
28655 case DEC8r:
28656 case DEC8r_EVEX:
28657 case DEC8r_ND:
28658 case DEC8r_NF:
28659 case DEC8r_NF_ND:
28660 return true;
28661 }
28662 return false;
28663}
28664
28665bool isVGETEXPSH(unsigned Opcode) {
28666 switch (Opcode) {
28667 case VGETEXPSHZm:
28668 case VGETEXPSHZmk:
28669 case VGETEXPSHZmkz:
28670 case VGETEXPSHZr:
28671 case VGETEXPSHZrb:
28672 case VGETEXPSHZrbk:
28673 case VGETEXPSHZrbkz:
28674 case VGETEXPSHZrk:
28675 case VGETEXPSHZrkz:
28676 return true;
28677 }
28678 return false;
28679}
28680
28681bool isAESDEC(unsigned Opcode) {
28682 switch (Opcode) {
28683 case AESDECrm:
28684 case AESDECrr:
28685 return true;
28686 }
28687 return false;
28688}
28689
28690bool isKORD(unsigned Opcode) {
28691 return Opcode == KORDkk;
28692}
28693
28694bool isTILELOADDT1(unsigned Opcode) {
28695 switch (Opcode) {
28696 case TILELOADDT1:
28697 case TILELOADDT1_EVEX:
28698 return true;
28699 }
28700 return false;
28701}
28702
28703bool isVPMULHW(unsigned Opcode) {
28704 switch (Opcode) {
28705 case VPMULHWYrm:
28706 case VPMULHWYrr:
28707 case VPMULHWZ128rm:
28708 case VPMULHWZ128rmk:
28709 case VPMULHWZ128rmkz:
28710 case VPMULHWZ128rr:
28711 case VPMULHWZ128rrk:
28712 case VPMULHWZ128rrkz:
28713 case VPMULHWZ256rm:
28714 case VPMULHWZ256rmk:
28715 case VPMULHWZ256rmkz:
28716 case VPMULHWZ256rr:
28717 case VPMULHWZ256rrk:
28718 case VPMULHWZ256rrkz:
28719 case VPMULHWZrm:
28720 case VPMULHWZrmk:
28721 case VPMULHWZrmkz:
28722 case VPMULHWZrr:
28723 case VPMULHWZrrk:
28724 case VPMULHWZrrkz:
28725 case VPMULHWrm:
28726 case VPMULHWrr:
28727 return true;
28728 }
28729 return false;
28730}
28731
28732bool isVMASKMOVPS(unsigned Opcode) {
28733 switch (Opcode) {
28734 case VMASKMOVPSYmr:
28735 case VMASKMOVPSYrm:
28736 case VMASKMOVPSmr:
28737 case VMASKMOVPSrm:
28738 return true;
28739 }
28740 return false;
28741}
28742
28743bool isPMOVZXDQ(unsigned Opcode) {
28744 switch (Opcode) {
28745 case PMOVZXDQrm:
28746 case PMOVZXDQrr:
28747 return true;
28748 }
28749 return false;
28750}
28751
28752bool isVCVTPS2PH(unsigned Opcode) {
28753 switch (Opcode) {
28754 case VCVTPS2PHYmr:
28755 case VCVTPS2PHYrr:
28756 case VCVTPS2PHZ128mr:
28757 case VCVTPS2PHZ128mrk:
28758 case VCVTPS2PHZ128rr:
28759 case VCVTPS2PHZ128rrk:
28760 case VCVTPS2PHZ128rrkz:
28761 case VCVTPS2PHZ256mr:
28762 case VCVTPS2PHZ256mrk:
28763 case VCVTPS2PHZ256rr:
28764 case VCVTPS2PHZ256rrk:
28765 case VCVTPS2PHZ256rrkz:
28766 case VCVTPS2PHZmr:
28767 case VCVTPS2PHZmrk:
28768 case VCVTPS2PHZrr:
28769 case VCVTPS2PHZrrb:
28770 case VCVTPS2PHZrrbk:
28771 case VCVTPS2PHZrrbkz:
28772 case VCVTPS2PHZrrk:
28773 case VCVTPS2PHZrrkz:
28774 case VCVTPS2PHmr:
28775 case VCVTPS2PHrr:
28776 return true;
28777 }
28778 return false;
28779}
28780
28781bool isCVTDQ2PD(unsigned Opcode) {
28782 switch (Opcode) {
28783 case CVTDQ2PDrm:
28784 case CVTDQ2PDrr:
28785 return true;
28786 }
28787 return false;
28788}
28789
28790bool isVCVTSD2SS(unsigned Opcode) {
28791 switch (Opcode) {
28792 case VCVTSD2SSZrm_Int:
28793 case VCVTSD2SSZrmk_Int:
28794 case VCVTSD2SSZrmkz_Int:
28795 case VCVTSD2SSZrr_Int:
28796 case VCVTSD2SSZrrb_Int:
28797 case VCVTSD2SSZrrbk_Int:
28798 case VCVTSD2SSZrrbkz_Int:
28799 case VCVTSD2SSZrrk_Int:
28800 case VCVTSD2SSZrrkz_Int:
28801 case VCVTSD2SSrm_Int:
28802 case VCVTSD2SSrr_Int:
28803 return true;
28804 }
28805 return false;
28806}
28807
28808bool isVFMSUB213PH(unsigned Opcode) {
28809 switch (Opcode) {
28810 case VFMSUB213PHZ128m:
28811 case VFMSUB213PHZ128mb:
28812 case VFMSUB213PHZ128mbk:
28813 case VFMSUB213PHZ128mbkz:
28814 case VFMSUB213PHZ128mk:
28815 case VFMSUB213PHZ128mkz:
28816 case VFMSUB213PHZ128r:
28817 case VFMSUB213PHZ128rk:
28818 case VFMSUB213PHZ128rkz:
28819 case VFMSUB213PHZ256m:
28820 case VFMSUB213PHZ256mb:
28821 case VFMSUB213PHZ256mbk:
28822 case VFMSUB213PHZ256mbkz:
28823 case VFMSUB213PHZ256mk:
28824 case VFMSUB213PHZ256mkz:
28825 case VFMSUB213PHZ256r:
28826 case VFMSUB213PHZ256rk:
28827 case VFMSUB213PHZ256rkz:
28828 case VFMSUB213PHZm:
28829 case VFMSUB213PHZmb:
28830 case VFMSUB213PHZmbk:
28831 case VFMSUB213PHZmbkz:
28832 case VFMSUB213PHZmk:
28833 case VFMSUB213PHZmkz:
28834 case VFMSUB213PHZr:
28835 case VFMSUB213PHZrb:
28836 case VFMSUB213PHZrbk:
28837 case VFMSUB213PHZrbkz:
28838 case VFMSUB213PHZrk:
28839 case VFMSUB213PHZrkz:
28840 return true;
28841 }
28842 return false;
28843}
28844
28845bool isVPROTB(unsigned Opcode) {
28846 switch (Opcode) {
28847 case VPROTBmi:
28848 case VPROTBmr:
28849 case VPROTBri:
28850 case VPROTBrm:
28851 case VPROTBrr:
28852 case VPROTBrr_REV:
28853 return true;
28854 }
28855 return false;
28856}
28857
28858bool isPINSRD(unsigned Opcode) {
28859 switch (Opcode) {
28860 case PINSRDrmi:
28861 case PINSRDrri:
28862 return true;
28863 }
28864 return false;
28865}
28866
28867bool isVMXON(unsigned Opcode) {
28868 return Opcode == VMXON;
28869}
28870
28871bool isVFCMULCSH(unsigned Opcode) {
28872 switch (Opcode) {
28873 case VFCMULCSHZrm:
28874 case VFCMULCSHZrmk:
28875 case VFCMULCSHZrmkz:
28876 case VFCMULCSHZrr:
28877 case VFCMULCSHZrrb:
28878 case VFCMULCSHZrrbk:
28879 case VFCMULCSHZrrbkz:
28880 case VFCMULCSHZrrk:
28881 case VFCMULCSHZrrkz:
28882 return true;
28883 }
28884 return false;
28885}
28886
28887bool isVFMULCSH(unsigned Opcode) {
28888 switch (Opcode) {
28889 case VFMULCSHZrm:
28890 case VFMULCSHZrmk:
28891 case VFMULCSHZrmkz:
28892 case VFMULCSHZrr:
28893 case VFMULCSHZrrb:
28894 case VFMULCSHZrrbk:
28895 case VFMULCSHZrrbkz:
28896 case VFMULCSHZrrk:
28897 case VFMULCSHZrrkz:
28898 return true;
28899 }
28900 return false;
28901}
28902
28903bool isVRANGEPD(unsigned Opcode) {
28904 switch (Opcode) {
28905 case VRANGEPDZ128rmbi:
28906 case VRANGEPDZ128rmbik:
28907 case VRANGEPDZ128rmbikz:
28908 case VRANGEPDZ128rmi:
28909 case VRANGEPDZ128rmik:
28910 case VRANGEPDZ128rmikz:
28911 case VRANGEPDZ128rri:
28912 case VRANGEPDZ128rrik:
28913 case VRANGEPDZ128rrikz:
28914 case VRANGEPDZ256rmbi:
28915 case VRANGEPDZ256rmbik:
28916 case VRANGEPDZ256rmbikz:
28917 case VRANGEPDZ256rmi:
28918 case VRANGEPDZ256rmik:
28919 case VRANGEPDZ256rmikz:
28920 case VRANGEPDZ256rri:
28921 case VRANGEPDZ256rrik:
28922 case VRANGEPDZ256rrikz:
28923 case VRANGEPDZrmbi:
28924 case VRANGEPDZrmbik:
28925 case VRANGEPDZrmbikz:
28926 case VRANGEPDZrmi:
28927 case VRANGEPDZrmik:
28928 case VRANGEPDZrmikz:
28929 case VRANGEPDZrri:
28930 case VRANGEPDZrrib:
28931 case VRANGEPDZrribk:
28932 case VRANGEPDZrribkz:
28933 case VRANGEPDZrrik:
28934 case VRANGEPDZrrikz:
28935 return true;
28936 }
28937 return false;
28938}
28939
28940bool isCMC(unsigned Opcode) {
28941 return Opcode == CMC;
28942}
28943
28944bool isVFNMADD231BF16(unsigned Opcode) {
28945 switch (Opcode) {
28946 case VFNMADD231BF16Z128m:
28947 case VFNMADD231BF16Z128mb:
28948 case VFNMADD231BF16Z128mbk:
28949 case VFNMADD231BF16Z128mbkz:
28950 case VFNMADD231BF16Z128mk:
28951 case VFNMADD231BF16Z128mkz:
28952 case VFNMADD231BF16Z128r:
28953 case VFNMADD231BF16Z128rk:
28954 case VFNMADD231BF16Z128rkz:
28955 case VFNMADD231BF16Z256m:
28956 case VFNMADD231BF16Z256mb:
28957 case VFNMADD231BF16Z256mbk:
28958 case VFNMADD231BF16Z256mbkz:
28959 case VFNMADD231BF16Z256mk:
28960 case VFNMADD231BF16Z256mkz:
28961 case VFNMADD231BF16Z256r:
28962 case VFNMADD231BF16Z256rk:
28963 case VFNMADD231BF16Z256rkz:
28964 case VFNMADD231BF16Zm:
28965 case VFNMADD231BF16Zmb:
28966 case VFNMADD231BF16Zmbk:
28967 case VFNMADD231BF16Zmbkz:
28968 case VFNMADD231BF16Zmk:
28969 case VFNMADD231BF16Zmkz:
28970 case VFNMADD231BF16Zr:
28971 case VFNMADD231BF16Zrk:
28972 case VFNMADD231BF16Zrkz:
28973 return true;
28974 }
28975 return false;
28976}
28977
28978bool isSHA256MSG1(unsigned Opcode) {
28979 switch (Opcode) {
28980 case SHA256MSG1rm:
28981 case SHA256MSG1rr:
28982 return true;
28983 }
28984 return false;
28985}
28986
28987bool isFLD1(unsigned Opcode) {
28988 return Opcode == LD_F1;
28989}
28990
28991bool isCMPPS(unsigned Opcode) {
28992 switch (Opcode) {
28993 case CMPPSrmi:
28994 case CMPPSrri:
28995 return true;
28996 }
28997 return false;
28998}
28999
29000bool isVPAVGW(unsigned Opcode) {
29001 switch (Opcode) {
29002 case VPAVGWYrm:
29003 case VPAVGWYrr:
29004 case VPAVGWZ128rm:
29005 case VPAVGWZ128rmk:
29006 case VPAVGWZ128rmkz:
29007 case VPAVGWZ128rr:
29008 case VPAVGWZ128rrk:
29009 case VPAVGWZ128rrkz:
29010 case VPAVGWZ256rm:
29011 case VPAVGWZ256rmk:
29012 case VPAVGWZ256rmkz:
29013 case VPAVGWZ256rr:
29014 case VPAVGWZ256rrk:
29015 case VPAVGWZ256rrkz:
29016 case VPAVGWZrm:
29017 case VPAVGWZrmk:
29018 case VPAVGWZrmkz:
29019 case VPAVGWZrr:
29020 case VPAVGWZrrk:
29021 case VPAVGWZrrkz:
29022 case VPAVGWrm:
29023 case VPAVGWrr:
29024 return true;
29025 }
29026 return false;
29027}
29028
29029bool isVFMADD213SH(unsigned Opcode) {
29030 switch (Opcode) {
29031 case VFMADD213SHZm_Int:
29032 case VFMADD213SHZmk_Int:
29033 case VFMADD213SHZmkz_Int:
29034 case VFMADD213SHZr_Int:
29035 case VFMADD213SHZrb_Int:
29036 case VFMADD213SHZrbk_Int:
29037 case VFMADD213SHZrbkz_Int:
29038 case VFMADD213SHZrk_Int:
29039 case VFMADD213SHZrkz_Int:
29040 return true;
29041 }
29042 return false;
29043}
29044
29045bool isVPCMPESTRMQ(unsigned Opcode) {
29046 switch (Opcode) {
29047 case VPCMPESTRMQrmi:
29048 case VPCMPESTRMQrri:
29049 return true;
29050 }
29051 return false;
29052}
29053
29054bool isVPINSRQ(unsigned Opcode) {
29055 switch (Opcode) {
29056 case VPINSRQZrmi:
29057 case VPINSRQZrri:
29058 case VPINSRQrmi:
29059 case VPINSRQrri:
29060 return true;
29061 }
29062 return false;
29063}
29064
29065bool isMOVABS(unsigned Opcode) {
29066 switch (Opcode) {
29067 case MOV16ao64:
29068 case MOV16o64a:
29069 case MOV32ao64:
29070 case MOV32o64a:
29071 case MOV64ao64:
29072 case MOV64o64a:
29073 case MOV64ri:
29074 case MOV8ao64:
29075 case MOV8o64a:
29076 return true;
29077 }
29078 return false;
29079}
29080
29081bool isVPSHAQ(unsigned Opcode) {
29082 switch (Opcode) {
29083 case VPSHAQmr:
29084 case VPSHAQrm:
29085 case VPSHAQrr:
29086 case VPSHAQrr_REV:
29087 return true;
29088 }
29089 return false;
29090}
29091
29092bool isRDTSCP(unsigned Opcode) {
29093 return Opcode == RDTSCP;
29094}
29095
29096bool isVFNMADD231SS(unsigned Opcode) {
29097 switch (Opcode) {
29098 case VFNMADD231SSZm_Int:
29099 case VFNMADD231SSZmk_Int:
29100 case VFNMADD231SSZmkz_Int:
29101 case VFNMADD231SSZr_Int:
29102 case VFNMADD231SSZrb_Int:
29103 case VFNMADD231SSZrbk_Int:
29104 case VFNMADD231SSZrbkz_Int:
29105 case VFNMADD231SSZrk_Int:
29106 case VFNMADD231SSZrkz_Int:
29107 case VFNMADD231SSm_Int:
29108 case VFNMADD231SSr_Int:
29109 return true;
29110 }
29111 return false;
29112}
29113
29114bool isTEST(unsigned Opcode) {
29115 switch (Opcode) {
29116 case TEST16i16:
29117 case TEST16mi:
29118 case TEST16mr:
29119 case TEST16ri:
29120 case TEST16rr:
29121 case TEST32i32:
29122 case TEST32mi:
29123 case TEST32mr:
29124 case TEST32ri:
29125 case TEST32rr:
29126 case TEST64i32:
29127 case TEST64mi32:
29128 case TEST64mr:
29129 case TEST64ri32:
29130 case TEST64rr:
29131 case TEST8i8:
29132 case TEST8mi:
29133 case TEST8mr:
29134 case TEST8ri:
29135 case TEST8rr:
29136 return true;
29137 }
29138 return false;
29139}
29140
29141bool isVPERMD(unsigned Opcode) {
29142 switch (Opcode) {
29143 case VPERMDYrm:
29144 case VPERMDYrr:
29145 case VPERMDZ256rm:
29146 case VPERMDZ256rmb:
29147 case VPERMDZ256rmbk:
29148 case VPERMDZ256rmbkz:
29149 case VPERMDZ256rmk:
29150 case VPERMDZ256rmkz:
29151 case VPERMDZ256rr:
29152 case VPERMDZ256rrk:
29153 case VPERMDZ256rrkz:
29154 case VPERMDZrm:
29155 case VPERMDZrmb:
29156 case VPERMDZrmbk:
29157 case VPERMDZrmbkz:
29158 case VPERMDZrmk:
29159 case VPERMDZrmkz:
29160 case VPERMDZrr:
29161 case VPERMDZrrk:
29162 case VPERMDZrrkz:
29163 return true;
29164 }
29165 return false;
29166}
29167
29168bool isVBCSTNESH2PS(unsigned Opcode) {
29169 switch (Opcode) {
29170 case VBCSTNESH2PSYrm:
29171 case VBCSTNESH2PSrm:
29172 return true;
29173 }
29174 return false;
29175}
29176
29177bool isVGATHERPF0QPD(unsigned Opcode) {
29178 return Opcode == VGATHERPF0QPDm;
29179}
29180
29181bool isVPERM2I128(unsigned Opcode) {
29182 switch (Opcode) {
29183 case VPERM2I128rmi:
29184 case VPERM2I128rri:
29185 return true;
29186 }
29187 return false;
29188}
29189
29190bool isVMPSADBW(unsigned Opcode) {
29191 switch (Opcode) {
29192 case VMPSADBWYrmi:
29193 case VMPSADBWYrri:
29194 case VMPSADBWZ128rmi:
29195 case VMPSADBWZ128rmik:
29196 case VMPSADBWZ128rmikz:
29197 case VMPSADBWZ128rri:
29198 case VMPSADBWZ128rrik:
29199 case VMPSADBWZ128rrikz:
29200 case VMPSADBWZ256rmi:
29201 case VMPSADBWZ256rmik:
29202 case VMPSADBWZ256rmikz:
29203 case VMPSADBWZ256rri:
29204 case VMPSADBWZ256rrik:
29205 case VMPSADBWZ256rrikz:
29206 case VMPSADBWZrmi:
29207 case VMPSADBWZrmik:
29208 case VMPSADBWZrmikz:
29209 case VMPSADBWZrri:
29210 case VMPSADBWZrrik:
29211 case VMPSADBWZrrikz:
29212 case VMPSADBWrmi:
29213 case VMPSADBWrri:
29214 return true;
29215 }
29216 return false;
29217}
29218
29219bool isVFNMSUB231PD(unsigned Opcode) {
29220 switch (Opcode) {
29221 case VFNMSUB231PDYm:
29222 case VFNMSUB231PDYr:
29223 case VFNMSUB231PDZ128m:
29224 case VFNMSUB231PDZ128mb:
29225 case VFNMSUB231PDZ128mbk:
29226 case VFNMSUB231PDZ128mbkz:
29227 case VFNMSUB231PDZ128mk:
29228 case VFNMSUB231PDZ128mkz:
29229 case VFNMSUB231PDZ128r:
29230 case VFNMSUB231PDZ128rk:
29231 case VFNMSUB231PDZ128rkz:
29232 case VFNMSUB231PDZ256m:
29233 case VFNMSUB231PDZ256mb:
29234 case VFNMSUB231PDZ256mbk:
29235 case VFNMSUB231PDZ256mbkz:
29236 case VFNMSUB231PDZ256mk:
29237 case VFNMSUB231PDZ256mkz:
29238 case VFNMSUB231PDZ256r:
29239 case VFNMSUB231PDZ256rk:
29240 case VFNMSUB231PDZ256rkz:
29241 case VFNMSUB231PDZm:
29242 case VFNMSUB231PDZmb:
29243 case VFNMSUB231PDZmbk:
29244 case VFNMSUB231PDZmbkz:
29245 case VFNMSUB231PDZmk:
29246 case VFNMSUB231PDZmkz:
29247 case VFNMSUB231PDZr:
29248 case VFNMSUB231PDZrb:
29249 case VFNMSUB231PDZrbk:
29250 case VFNMSUB231PDZrbkz:
29251 case VFNMSUB231PDZrk:
29252 case VFNMSUB231PDZrkz:
29253 case VFNMSUB231PDm:
29254 case VFNMSUB231PDr:
29255 return true;
29256 }
29257 return false;
29258}
29259
29260bool isPADDSB(unsigned Opcode) {
29261 switch (Opcode) {
29262 case MMX_PADDSBrm:
29263 case MMX_PADDSBrr:
29264 case PADDSBrm:
29265 case PADDSBrr:
29266 return true;
29267 }
29268 return false;
29269}
29270
29271bool isMWAITX(unsigned Opcode) {
29272 return Opcode == MWAITXrrr;
29273}
29274
29275bool isMONITORX(unsigned Opcode) {
29276 switch (Opcode) {
29277 case MONITORX32rrr:
29278 case MONITORX64rrr:
29279 return true;
29280 }
29281 return false;
29282}
29283
29284bool isVPEXPANDD(unsigned Opcode) {
29285 switch (Opcode) {
29286 case VPEXPANDDZ128rm:
29287 case VPEXPANDDZ128rmk:
29288 case VPEXPANDDZ128rmkz:
29289 case VPEXPANDDZ128rr:
29290 case VPEXPANDDZ128rrk:
29291 case VPEXPANDDZ128rrkz:
29292 case VPEXPANDDZ256rm:
29293 case VPEXPANDDZ256rmk:
29294 case VPEXPANDDZ256rmkz:
29295 case VPEXPANDDZ256rr:
29296 case VPEXPANDDZ256rrk:
29297 case VPEXPANDDZ256rrkz:
29298 case VPEXPANDDZrm:
29299 case VPEXPANDDZrmk:
29300 case VPEXPANDDZrmkz:
29301 case VPEXPANDDZrr:
29302 case VPEXPANDDZrrk:
29303 case VPEXPANDDZrrkz:
29304 return true;
29305 }
29306 return false;
29307}
29308
29309bool isVFRCZPD(unsigned Opcode) {
29310 switch (Opcode) {
29311 case VFRCZPDYrm:
29312 case VFRCZPDYrr:
29313 case VFRCZPDrm:
29314 case VFRCZPDrr:
29315 return true;
29316 }
29317 return false;
29318}
29319
29320bool isVRCPPH(unsigned Opcode) {
29321 switch (Opcode) {
29322 case VRCPPHZ128m:
29323 case VRCPPHZ128mb:
29324 case VRCPPHZ128mbk:
29325 case VRCPPHZ128mbkz:
29326 case VRCPPHZ128mk:
29327 case VRCPPHZ128mkz:
29328 case VRCPPHZ128r:
29329 case VRCPPHZ128rk:
29330 case VRCPPHZ128rkz:
29331 case VRCPPHZ256m:
29332 case VRCPPHZ256mb:
29333 case VRCPPHZ256mbk:
29334 case VRCPPHZ256mbkz:
29335 case VRCPPHZ256mk:
29336 case VRCPPHZ256mkz:
29337 case VRCPPHZ256r:
29338 case VRCPPHZ256rk:
29339 case VRCPPHZ256rkz:
29340 case VRCPPHZm:
29341 case VRCPPHZmb:
29342 case VRCPPHZmbk:
29343 case VRCPPHZmbkz:
29344 case VRCPPHZmk:
29345 case VRCPPHZmkz:
29346 case VRCPPHZr:
29347 case VRCPPHZrk:
29348 case VRCPPHZrkz:
29349 return true;
29350 }
29351 return false;
29352}
29353
29354bool isFEMMS(unsigned Opcode) {
29355 return Opcode == FEMMS;
29356}
29357
29358bool isVSCATTERQPD(unsigned Opcode) {
29359 switch (Opcode) {
29360 case VSCATTERQPDZ128mr:
29361 case VSCATTERQPDZ256mr:
29362 case VSCATTERQPDZmr:
29363 return true;
29364 }
29365 return false;
29366}
29367
29368bool isVMOVW(unsigned Opcode) {
29369 switch (Opcode) {
29370 case VMOVSH2Wrr:
29371 case VMOVSHtoW64rr:
29372 case VMOVW2SHrr:
29373 case VMOVW64toSHrr:
29374 case VMOVWmr:
29375 case VMOVWrm:
29376 case VMOVZPWILo2PWIZmr:
29377 case VMOVZPWILo2PWIZrm:
29378 case VMOVZPWILo2PWIZrr:
29379 case VMOVZPWILo2PWIZrr2:
29380 return true;
29381 }
29382 return false;
29383}
29384
29385bool isVPBROADCASTD(unsigned Opcode) {
29386 switch (Opcode) {
29387 case VPBROADCASTDYrm:
29388 case VPBROADCASTDYrr:
29389 case VPBROADCASTDZ128rm:
29390 case VPBROADCASTDZ128rmk:
29391 case VPBROADCASTDZ128rmkz:
29392 case VPBROADCASTDZ128rr:
29393 case VPBROADCASTDZ128rrk:
29394 case VPBROADCASTDZ128rrkz:
29395 case VPBROADCASTDZ256rm:
29396 case VPBROADCASTDZ256rmk:
29397 case VPBROADCASTDZ256rmkz:
29398 case VPBROADCASTDZ256rr:
29399 case VPBROADCASTDZ256rrk:
29400 case VPBROADCASTDZ256rrkz:
29401 case VPBROADCASTDZrm:
29402 case VPBROADCASTDZrmk:
29403 case VPBROADCASTDZrmkz:
29404 case VPBROADCASTDZrr:
29405 case VPBROADCASTDZrrk:
29406 case VPBROADCASTDZrrkz:
29407 case VPBROADCASTDrZ128rr:
29408 case VPBROADCASTDrZ128rrk:
29409 case VPBROADCASTDrZ128rrkz:
29410 case VPBROADCASTDrZ256rr:
29411 case VPBROADCASTDrZ256rrk:
29412 case VPBROADCASTDrZ256rrkz:
29413 case VPBROADCASTDrZrr:
29414 case VPBROADCASTDrZrrk:
29415 case VPBROADCASTDrZrrkz:
29416 case VPBROADCASTDrm:
29417 case VPBROADCASTDrr:
29418 return true;
29419 }
29420 return false;
29421}
29422
29423bool isSTOSB(unsigned Opcode) {
29424 return Opcode == STOSB;
29425}
29426
29427bool isFUCOMI(unsigned Opcode) {
29428 return Opcode == UCOM_FIr;
29429}
29430
29431bool isVBROADCASTI64X4(unsigned Opcode) {
29432 switch (Opcode) {
29433 case VBROADCASTI64X4Zrm:
29434 case VBROADCASTI64X4Zrmk:
29435 case VBROADCASTI64X4Zrmkz:
29436 return true;
29437 }
29438 return false;
29439}
29440
29441bool isFCMOVU(unsigned Opcode) {
29442 return Opcode == CMOVP_F;
29443}
29444
29445bool isPSHUFLW(unsigned Opcode) {
29446 switch (Opcode) {
29447 case PSHUFLWmi:
29448 case PSHUFLWri:
29449 return true;
29450 }
29451 return false;
29452}
29453
29454bool isCVTPI2PS(unsigned Opcode) {
29455 switch (Opcode) {
29456 case MMX_CVTPI2PSrm:
29457 case MMX_CVTPI2PSrr:
29458 return true;
29459 }
29460 return false;
29461}
29462
29463bool isVCVTTPD2UDQS(unsigned Opcode) {
29464 switch (Opcode) {
29465 case VCVTTPD2UDQSZ128rm:
29466 case VCVTTPD2UDQSZ128rmb:
29467 case VCVTTPD2UDQSZ128rmbk:
29468 case VCVTTPD2UDQSZ128rmbkz:
29469 case VCVTTPD2UDQSZ128rmk:
29470 case VCVTTPD2UDQSZ128rmkz:
29471 case VCVTTPD2UDQSZ128rr:
29472 case VCVTTPD2UDQSZ128rrk:
29473 case VCVTTPD2UDQSZ128rrkz:
29474 case VCVTTPD2UDQSZ256rm:
29475 case VCVTTPD2UDQSZ256rmb:
29476 case VCVTTPD2UDQSZ256rmbk:
29477 case VCVTTPD2UDQSZ256rmbkz:
29478 case VCVTTPD2UDQSZ256rmk:
29479 case VCVTTPD2UDQSZ256rmkz:
29480 case VCVTTPD2UDQSZ256rr:
29481 case VCVTTPD2UDQSZ256rrb:
29482 case VCVTTPD2UDQSZ256rrbk:
29483 case VCVTTPD2UDQSZ256rrbkz:
29484 case VCVTTPD2UDQSZ256rrk:
29485 case VCVTTPD2UDQSZ256rrkz:
29486 case VCVTTPD2UDQSZrm:
29487 case VCVTTPD2UDQSZrmb:
29488 case VCVTTPD2UDQSZrmbk:
29489 case VCVTTPD2UDQSZrmbkz:
29490 case VCVTTPD2UDQSZrmk:
29491 case VCVTTPD2UDQSZrmkz:
29492 case VCVTTPD2UDQSZrr:
29493 case VCVTTPD2UDQSZrrb:
29494 case VCVTTPD2UDQSZrrbk:
29495 case VCVTTPD2UDQSZrrbkz:
29496 case VCVTTPD2UDQSZrrk:
29497 case VCVTTPD2UDQSZrrkz:
29498 return true;
29499 }
29500 return false;
29501}
29502
29503bool isSYSCALL(unsigned Opcode) {
29504 return Opcode == SYSCALL;
29505}
29506
29507bool isVFMADD231SH(unsigned Opcode) {
29508 switch (Opcode) {
29509 case VFMADD231SHZm_Int:
29510 case VFMADD231SHZmk_Int:
29511 case VFMADD231SHZmkz_Int:
29512 case VFMADD231SHZr_Int:
29513 case VFMADD231SHZrb_Int:
29514 case VFMADD231SHZrbk_Int:
29515 case VFMADD231SHZrbkz_Int:
29516 case VFMADD231SHZrk_Int:
29517 case VFMADD231SHZrkz_Int:
29518 return true;
29519 }
29520 return false;
29521}
29522
29523bool isVPOPCNTB(unsigned Opcode) {
29524 switch (Opcode) {
29525 case VPOPCNTBZ128rm:
29526 case VPOPCNTBZ128rmk:
29527 case VPOPCNTBZ128rmkz:
29528 case VPOPCNTBZ128rr:
29529 case VPOPCNTBZ128rrk:
29530 case VPOPCNTBZ128rrkz:
29531 case VPOPCNTBZ256rm:
29532 case VPOPCNTBZ256rmk:
29533 case VPOPCNTBZ256rmkz:
29534 case VPOPCNTBZ256rr:
29535 case VPOPCNTBZ256rrk:
29536 case VPOPCNTBZ256rrkz:
29537 case VPOPCNTBZrm:
29538 case VPOPCNTBZrmk:
29539 case VPOPCNTBZrmkz:
29540 case VPOPCNTBZrr:
29541 case VPOPCNTBZrrk:
29542 case VPOPCNTBZrrkz:
29543 return true;
29544 }
29545 return false;
29546}
29547
29548bool isPMOVZXBW(unsigned Opcode) {
29549 switch (Opcode) {
29550 case PMOVZXBWrm:
29551 case PMOVZXBWrr:
29552 return true;
29553 }
29554 return false;
29555}
29556
29557bool isVCVTDQ2PS(unsigned Opcode) {
29558 switch (Opcode) {
29559 case VCVTDQ2PSYrm:
29560 case VCVTDQ2PSYrr:
29561 case VCVTDQ2PSZ128rm:
29562 case VCVTDQ2PSZ128rmb:
29563 case VCVTDQ2PSZ128rmbk:
29564 case VCVTDQ2PSZ128rmbkz:
29565 case VCVTDQ2PSZ128rmk:
29566 case VCVTDQ2PSZ128rmkz:
29567 case VCVTDQ2PSZ128rr:
29568 case VCVTDQ2PSZ128rrk:
29569 case VCVTDQ2PSZ128rrkz:
29570 case VCVTDQ2PSZ256rm:
29571 case VCVTDQ2PSZ256rmb:
29572 case VCVTDQ2PSZ256rmbk:
29573 case VCVTDQ2PSZ256rmbkz:
29574 case VCVTDQ2PSZ256rmk:
29575 case VCVTDQ2PSZ256rmkz:
29576 case VCVTDQ2PSZ256rr:
29577 case VCVTDQ2PSZ256rrk:
29578 case VCVTDQ2PSZ256rrkz:
29579 case VCVTDQ2PSZrm:
29580 case VCVTDQ2PSZrmb:
29581 case VCVTDQ2PSZrmbk:
29582 case VCVTDQ2PSZrmbkz:
29583 case VCVTDQ2PSZrmk:
29584 case VCVTDQ2PSZrmkz:
29585 case VCVTDQ2PSZrr:
29586 case VCVTDQ2PSZrrb:
29587 case VCVTDQ2PSZrrbk:
29588 case VCVTDQ2PSZrrbkz:
29589 case VCVTDQ2PSZrrk:
29590 case VCVTDQ2PSZrrkz:
29591 case VCVTDQ2PSrm:
29592 case VCVTDQ2PSrr:
29593 return true;
29594 }
29595 return false;
29596}
29597
29598bool isPSUBD(unsigned Opcode) {
29599 switch (Opcode) {
29600 case MMX_PSUBDrm:
29601 case MMX_PSUBDrr:
29602 case PSUBDrm:
29603 case PSUBDrr:
29604 return true;
29605 }
29606 return false;
29607}
29608
29609bool isVPCMPEQW(unsigned Opcode) {
29610 switch (Opcode) {
29611 case VPCMPEQWYrm:
29612 case VPCMPEQWYrr:
29613 case VPCMPEQWZ128rm:
29614 case VPCMPEQWZ128rmk:
29615 case VPCMPEQWZ128rr:
29616 case VPCMPEQWZ128rrk:
29617 case VPCMPEQWZ256rm:
29618 case VPCMPEQWZ256rmk:
29619 case VPCMPEQWZ256rr:
29620 case VPCMPEQWZ256rrk:
29621 case VPCMPEQWZrm:
29622 case VPCMPEQWZrmk:
29623 case VPCMPEQWZrr:
29624 case VPCMPEQWZrrk:
29625 case VPCMPEQWrm:
29626 case VPCMPEQWrr:
29627 return true;
29628 }
29629 return false;
29630}
29631
29632bool isMOVSW(unsigned Opcode) {
29633 return Opcode == MOVSW;
29634}
29635
29636bool isVSM3RNDS2(unsigned Opcode) {
29637 switch (Opcode) {
29638 case VSM3RNDS2rmi:
29639 case VSM3RNDS2rri:
29640 return true;
29641 }
29642 return false;
29643}
29644
29645bool isVPMOVUSQD(unsigned Opcode) {
29646 switch (Opcode) {
29647 case VPMOVUSQDZ128mr:
29648 case VPMOVUSQDZ128mrk:
29649 case VPMOVUSQDZ128rr:
29650 case VPMOVUSQDZ128rrk:
29651 case VPMOVUSQDZ128rrkz:
29652 case VPMOVUSQDZ256mr:
29653 case VPMOVUSQDZ256mrk:
29654 case VPMOVUSQDZ256rr:
29655 case VPMOVUSQDZ256rrk:
29656 case VPMOVUSQDZ256rrkz:
29657 case VPMOVUSQDZmr:
29658 case VPMOVUSQDZmrk:
29659 case VPMOVUSQDZrr:
29660 case VPMOVUSQDZrrk:
29661 case VPMOVUSQDZrrkz:
29662 return true;
29663 }
29664 return false;
29665}
29666
29667bool isCVTTPD2DQ(unsigned Opcode) {
29668 switch (Opcode) {
29669 case CVTTPD2DQrm:
29670 case CVTTPD2DQrr:
29671 return true;
29672 }
29673 return false;
29674}
29675
29676bool isVPEXPANDW(unsigned Opcode) {
29677 switch (Opcode) {
29678 case VPEXPANDWZ128rm:
29679 case VPEXPANDWZ128rmk:
29680 case VPEXPANDWZ128rmkz:
29681 case VPEXPANDWZ128rr:
29682 case VPEXPANDWZ128rrk:
29683 case VPEXPANDWZ128rrkz:
29684 case VPEXPANDWZ256rm:
29685 case VPEXPANDWZ256rmk:
29686 case VPEXPANDWZ256rmkz:
29687 case VPEXPANDWZ256rr:
29688 case VPEXPANDWZ256rrk:
29689 case VPEXPANDWZ256rrkz:
29690 case VPEXPANDWZrm:
29691 case VPEXPANDWZrmk:
29692 case VPEXPANDWZrmkz:
29693 case VPEXPANDWZrr:
29694 case VPEXPANDWZrrk:
29695 case VPEXPANDWZrrkz:
29696 return true;
29697 }
29698 return false;
29699}
29700
29701bool isVUCOMISH(unsigned Opcode) {
29702 switch (Opcode) {
29703 case VUCOMISHZrm:
29704 case VUCOMISHZrr:
29705 case VUCOMISHZrrb:
29706 return true;
29707 }
29708 return false;
29709}
29710
29711bool isVZEROALL(unsigned Opcode) {
29712 return Opcode == VZEROALL;
29713}
29714
29715bool isVPAND(unsigned Opcode) {
29716 switch (Opcode) {
29717 case VPANDYrm:
29718 case VPANDYrr:
29719 case VPANDrm:
29720 case VPANDrr:
29721 return true;
29722 }
29723 return false;
29724}
29725
29726bool isPMULDQ(unsigned Opcode) {
29727 switch (Opcode) {
29728 case PMULDQrm:
29729 case PMULDQrr:
29730 return true;
29731 }
29732 return false;
29733}
29734
29735bool isVPSHUFHW(unsigned Opcode) {
29736 switch (Opcode) {
29737 case VPSHUFHWYmi:
29738 case VPSHUFHWYri:
29739 case VPSHUFHWZ128mi:
29740 case VPSHUFHWZ128mik:
29741 case VPSHUFHWZ128mikz:
29742 case VPSHUFHWZ128ri:
29743 case VPSHUFHWZ128rik:
29744 case VPSHUFHWZ128rikz:
29745 case VPSHUFHWZ256mi:
29746 case VPSHUFHWZ256mik:
29747 case VPSHUFHWZ256mikz:
29748 case VPSHUFHWZ256ri:
29749 case VPSHUFHWZ256rik:
29750 case VPSHUFHWZ256rikz:
29751 case VPSHUFHWZmi:
29752 case VPSHUFHWZmik:
29753 case VPSHUFHWZmikz:
29754 case VPSHUFHWZri:
29755 case VPSHUFHWZrik:
29756 case VPSHUFHWZrikz:
29757 case VPSHUFHWmi:
29758 case VPSHUFHWri:
29759 return true;
29760 }
29761 return false;
29762}
29763
29764bool isVPALIGNR(unsigned Opcode) {
29765 switch (Opcode) {
29766 case VPALIGNRYrmi:
29767 case VPALIGNRYrri:
29768 case VPALIGNRZ128rmi:
29769 case VPALIGNRZ128rmik:
29770 case VPALIGNRZ128rmikz:
29771 case VPALIGNRZ128rri:
29772 case VPALIGNRZ128rrik:
29773 case VPALIGNRZ128rrikz:
29774 case VPALIGNRZ256rmi:
29775 case VPALIGNRZ256rmik:
29776 case VPALIGNRZ256rmikz:
29777 case VPALIGNRZ256rri:
29778 case VPALIGNRZ256rrik:
29779 case VPALIGNRZ256rrikz:
29780 case VPALIGNRZrmi:
29781 case VPALIGNRZrmik:
29782 case VPALIGNRZrmikz:
29783 case VPALIGNRZrri:
29784 case VPALIGNRZrrik:
29785 case VPALIGNRZrrikz:
29786 case VPALIGNRrmi:
29787 case VPALIGNRrri:
29788 return true;
29789 }
29790 return false;
29791}
29792
29793bool isSQRTSD(unsigned Opcode) {
29794 switch (Opcode) {
29795 case SQRTSDm_Int:
29796 case SQRTSDr_Int:
29797 return true;
29798 }
29799 return false;
29800}
29801
29802bool isVCVTTPH2UDQ(unsigned Opcode) {
29803 switch (Opcode) {
29804 case VCVTTPH2UDQZ128rm:
29805 case VCVTTPH2UDQZ128rmb:
29806 case VCVTTPH2UDQZ128rmbk:
29807 case VCVTTPH2UDQZ128rmbkz:
29808 case VCVTTPH2UDQZ128rmk:
29809 case VCVTTPH2UDQZ128rmkz:
29810 case VCVTTPH2UDQZ128rr:
29811 case VCVTTPH2UDQZ128rrk:
29812 case VCVTTPH2UDQZ128rrkz:
29813 case VCVTTPH2UDQZ256rm:
29814 case VCVTTPH2UDQZ256rmb:
29815 case VCVTTPH2UDQZ256rmbk:
29816 case VCVTTPH2UDQZ256rmbkz:
29817 case VCVTTPH2UDQZ256rmk:
29818 case VCVTTPH2UDQZ256rmkz:
29819 case VCVTTPH2UDQZ256rr:
29820 case VCVTTPH2UDQZ256rrk:
29821 case VCVTTPH2UDQZ256rrkz:
29822 case VCVTTPH2UDQZrm:
29823 case VCVTTPH2UDQZrmb:
29824 case VCVTTPH2UDQZrmbk:
29825 case VCVTTPH2UDQZrmbkz:
29826 case VCVTTPH2UDQZrmk:
29827 case VCVTTPH2UDQZrmkz:
29828 case VCVTTPH2UDQZrr:
29829 case VCVTTPH2UDQZrrb:
29830 case VCVTTPH2UDQZrrbk:
29831 case VCVTTPH2UDQZrrbkz:
29832 case VCVTTPH2UDQZrrk:
29833 case VCVTTPH2UDQZrrkz:
29834 return true;
29835 }
29836 return false;
29837}
29838
29839bool isVGETEXPPH(unsigned Opcode) {
29840 switch (Opcode) {
29841 case VGETEXPPHZ128m:
29842 case VGETEXPPHZ128mb:
29843 case VGETEXPPHZ128mbk:
29844 case VGETEXPPHZ128mbkz:
29845 case VGETEXPPHZ128mk:
29846 case VGETEXPPHZ128mkz:
29847 case VGETEXPPHZ128r:
29848 case VGETEXPPHZ128rk:
29849 case VGETEXPPHZ128rkz:
29850 case VGETEXPPHZ256m:
29851 case VGETEXPPHZ256mb:
29852 case VGETEXPPHZ256mbk:
29853 case VGETEXPPHZ256mbkz:
29854 case VGETEXPPHZ256mk:
29855 case VGETEXPPHZ256mkz:
29856 case VGETEXPPHZ256r:
29857 case VGETEXPPHZ256rk:
29858 case VGETEXPPHZ256rkz:
29859 case VGETEXPPHZm:
29860 case VGETEXPPHZmb:
29861 case VGETEXPPHZmbk:
29862 case VGETEXPPHZmbkz:
29863 case VGETEXPPHZmk:
29864 case VGETEXPPHZmkz:
29865 case VGETEXPPHZr:
29866 case VGETEXPPHZrb:
29867 case VGETEXPPHZrbk:
29868 case VGETEXPPHZrbkz:
29869 case VGETEXPPHZrk:
29870 case VGETEXPPHZrkz:
29871 return true;
29872 }
29873 return false;
29874}
29875
29876bool isADDPD(unsigned Opcode) {
29877 switch (Opcode) {
29878 case ADDPDrm:
29879 case ADDPDrr:
29880 return true;
29881 }
29882 return false;
29883}
29884
29885bool isVFNMADDPD(unsigned Opcode) {
29886 switch (Opcode) {
29887 case VFNMADDPD4Ymr:
29888 case VFNMADDPD4Yrm:
29889 case VFNMADDPD4Yrr:
29890 case VFNMADDPD4Yrr_REV:
29891 case VFNMADDPD4mr:
29892 case VFNMADDPD4rm:
29893 case VFNMADDPD4rr:
29894 case VFNMADDPD4rr_REV:
29895 return true;
29896 }
29897 return false;
29898}
29899
29900bool isSTTILECFG(unsigned Opcode) {
29901 switch (Opcode) {
29902 case STTILECFG:
29903 case STTILECFG_EVEX:
29904 return true;
29905 }
29906 return false;
29907}
29908
29909bool isVMINPD(unsigned Opcode) {
29910 switch (Opcode) {
29911 case VMINPDYrm:
29912 case VMINPDYrr:
29913 case VMINPDZ128rm:
29914 case VMINPDZ128rmb:
29915 case VMINPDZ128rmbk:
29916 case VMINPDZ128rmbkz:
29917 case VMINPDZ128rmk:
29918 case VMINPDZ128rmkz:
29919 case VMINPDZ128rr:
29920 case VMINPDZ128rrk:
29921 case VMINPDZ128rrkz:
29922 case VMINPDZ256rm:
29923 case VMINPDZ256rmb:
29924 case VMINPDZ256rmbk:
29925 case VMINPDZ256rmbkz:
29926 case VMINPDZ256rmk:
29927 case VMINPDZ256rmkz:
29928 case VMINPDZ256rr:
29929 case VMINPDZ256rrk:
29930 case VMINPDZ256rrkz:
29931 case VMINPDZrm:
29932 case VMINPDZrmb:
29933 case VMINPDZrmbk:
29934 case VMINPDZrmbkz:
29935 case VMINPDZrmk:
29936 case VMINPDZrmkz:
29937 case VMINPDZrr:
29938 case VMINPDZrrb:
29939 case VMINPDZrrbk:
29940 case VMINPDZrrbkz:
29941 case VMINPDZrrk:
29942 case VMINPDZrrkz:
29943 case VMINPDrm:
29944 case VMINPDrr:
29945 return true;
29946 }
29947 return false;
29948}
29949
29950bool isSHA1RNDS4(unsigned Opcode) {
29951 switch (Opcode) {
29952 case SHA1RNDS4rmi:
29953 case SHA1RNDS4rri:
29954 return true;
29955 }
29956 return false;
29957}
29958
29959bool isPBLENDVB(unsigned Opcode) {
29960 switch (Opcode) {
29961 case PBLENDVBrm0:
29962 case PBLENDVBrr0:
29963 return true;
29964 }
29965 return false;
29966}
29967
29968bool isVBROADCASTF128(unsigned Opcode) {
29969 return Opcode == VBROADCASTF128rm;
29970}
29971
29972bool isVPSHRDQ(unsigned Opcode) {
29973 switch (Opcode) {
29974 case VPSHRDQZ128rmbi:
29975 case VPSHRDQZ128rmbik:
29976 case VPSHRDQZ128rmbikz:
29977 case VPSHRDQZ128rmi:
29978 case VPSHRDQZ128rmik:
29979 case VPSHRDQZ128rmikz:
29980 case VPSHRDQZ128rri:
29981 case VPSHRDQZ128rrik:
29982 case VPSHRDQZ128rrikz:
29983 case VPSHRDQZ256rmbi:
29984 case VPSHRDQZ256rmbik:
29985 case VPSHRDQZ256rmbikz:
29986 case VPSHRDQZ256rmi:
29987 case VPSHRDQZ256rmik:
29988 case VPSHRDQZ256rmikz:
29989 case VPSHRDQZ256rri:
29990 case VPSHRDQZ256rrik:
29991 case VPSHRDQZ256rrikz:
29992 case VPSHRDQZrmbi:
29993 case VPSHRDQZrmbik:
29994 case VPSHRDQZrmbikz:
29995 case VPSHRDQZrmi:
29996 case VPSHRDQZrmik:
29997 case VPSHRDQZrmikz:
29998 case VPSHRDQZrri:
29999 case VPSHRDQZrrik:
30000 case VPSHRDQZrrikz:
30001 return true;
30002 }
30003 return false;
30004}
30005
30006bool isVAESIMC(unsigned Opcode) {
30007 switch (Opcode) {
30008 case VAESIMCrm:
30009 case VAESIMCrr:
30010 return true;
30011 }
30012 return false;
30013}
30014
30015bool isCOMISD(unsigned Opcode) {
30016 switch (Opcode) {
30017 case COMISDrm:
30018 case COMISDrr:
30019 return true;
30020 }
30021 return false;
30022}
30023
30024bool isVMOVSH(unsigned Opcode) {
30025 switch (Opcode) {
30026 case VMOVSHZmr:
30027 case VMOVSHZmrk:
30028 case VMOVSHZrm:
30029 case VMOVSHZrmk:
30030 case VMOVSHZrmkz:
30031 case VMOVSHZrr:
30032 case VMOVSHZrr_REV:
30033 case VMOVSHZrrk:
30034 case VMOVSHZrrk_REV:
30035 case VMOVSHZrrkz:
30036 case VMOVSHZrrkz_REV:
30037 return true;
30038 }
30039 return false;
30040}
30041
30042bool isPFSUBR(unsigned Opcode) {
30043 switch (Opcode) {
30044 case PFSUBRrm:
30045 case PFSUBRrr:
30046 return true;
30047 }
30048 return false;
30049}
30050
30051bool isRDSSPD(unsigned Opcode) {
30052 return Opcode == RDSSPD;
30053}
30054
30055bool isWAIT(unsigned Opcode) {
30056 return Opcode == WAIT;
30057}
30058
30059bool isVFPCLASSSS(unsigned Opcode) {
30060 switch (Opcode) {
30061 case VFPCLASSSSZmi:
30062 case VFPCLASSSSZmik:
30063 case VFPCLASSSSZri:
30064 case VFPCLASSSSZrik:
30065 return true;
30066 }
30067 return false;
30068}
30069
30070bool isPCMPGTD(unsigned Opcode) {
30071 switch (Opcode) {
30072 case MMX_PCMPGTDrm:
30073 case MMX_PCMPGTDrr:
30074 case PCMPGTDrm:
30075 case PCMPGTDrr:
30076 return true;
30077 }
30078 return false;
30079}
30080
30081bool isVGATHERPF0QPS(unsigned Opcode) {
30082 return Opcode == VGATHERPF0QPSm;
30083}
30084
30085bool isBLENDVPS(unsigned Opcode) {
30086 switch (Opcode) {
30087 case BLENDVPSrm0:
30088 case BLENDVPSrr0:
30089 return true;
30090 }
30091 return false;
30092}
30093
30094bool isVBROADCASTF32X4(unsigned Opcode) {
30095 switch (Opcode) {
30096 case VBROADCASTF32X4Z256rm:
30097 case VBROADCASTF32X4Z256rmk:
30098 case VBROADCASTF32X4Z256rmkz:
30099 case VBROADCASTF32X4Zrm:
30100 case VBROADCASTF32X4Zrmk:
30101 case VBROADCASTF32X4Zrmkz:
30102 return true;
30103 }
30104 return false;
30105}
30106
30107bool isVMOVLPD(unsigned Opcode) {
30108 switch (Opcode) {
30109 case VMOVLPDZ128mr:
30110 case VMOVLPDZ128rm:
30111 case VMOVLPDmr:
30112 case VMOVLPDrm:
30113 return true;
30114 }
30115 return false;
30116}
30117
30118bool isVMOVQ(unsigned Opcode) {
30119 switch (Opcode) {
30120 case VMOV64toPQIZrm:
30121 case VMOV64toPQIZrr:
30122 case VMOV64toPQIrm:
30123 case VMOV64toPQIrr:
30124 case VMOVPQI2QIZmr:
30125 case VMOVPQI2QIZrr:
30126 case VMOVPQI2QImr:
30127 case VMOVPQI2QIrr:
30128 case VMOVPQIto64Zmr:
30129 case VMOVPQIto64Zrr:
30130 case VMOVPQIto64mr:
30131 case VMOVPQIto64rr:
30132 case VMOVQI2PQIZrm:
30133 case VMOVQI2PQIrm:
30134 case VMOVZPQILo2PQIZrr:
30135 case VMOVZPQILo2PQIrr:
30136 return true;
30137 }
30138 return false;
30139}
30140
30141bool isVPMADD52LUQ(unsigned Opcode) {
30142 switch (Opcode) {
30143 case VPMADD52LUQYrm:
30144 case VPMADD52LUQYrr:
30145 case VPMADD52LUQZ128m:
30146 case VPMADD52LUQZ128mb:
30147 case VPMADD52LUQZ128mbk:
30148 case VPMADD52LUQZ128mbkz:
30149 case VPMADD52LUQZ128mk:
30150 case VPMADD52LUQZ128mkz:
30151 case VPMADD52LUQZ128r:
30152 case VPMADD52LUQZ128rk:
30153 case VPMADD52LUQZ128rkz:
30154 case VPMADD52LUQZ256m:
30155 case VPMADD52LUQZ256mb:
30156 case VPMADD52LUQZ256mbk:
30157 case VPMADD52LUQZ256mbkz:
30158 case VPMADD52LUQZ256mk:
30159 case VPMADD52LUQZ256mkz:
30160 case VPMADD52LUQZ256r:
30161 case VPMADD52LUQZ256rk:
30162 case VPMADD52LUQZ256rkz:
30163 case VPMADD52LUQZm:
30164 case VPMADD52LUQZmb:
30165 case VPMADD52LUQZmbk:
30166 case VPMADD52LUQZmbkz:
30167 case VPMADD52LUQZmk:
30168 case VPMADD52LUQZmkz:
30169 case VPMADD52LUQZr:
30170 case VPMADD52LUQZrk:
30171 case VPMADD52LUQZrkz:
30172 case VPMADD52LUQrm:
30173 case VPMADD52LUQrr:
30174 return true;
30175 }
30176 return false;
30177}
30178
30179bool isVMOVDQU(unsigned Opcode) {
30180 switch (Opcode) {
30181 case VMOVDQUYmr:
30182 case VMOVDQUYrm:
30183 case VMOVDQUYrr:
30184 case VMOVDQUYrr_REV:
30185 case VMOVDQUmr:
30186 case VMOVDQUrm:
30187 case VMOVDQUrr:
30188 case VMOVDQUrr_REV:
30189 return true;
30190 }
30191 return false;
30192}
30193
30194bool isAESENC128KL(unsigned Opcode) {
30195 return Opcode == AESENC128KL;
30196}
30197
30198bool isVFMADDSUB231PS(unsigned Opcode) {
30199 switch (Opcode) {
30200 case VFMADDSUB231PSYm:
30201 case VFMADDSUB231PSYr:
30202 case VFMADDSUB231PSZ128m:
30203 case VFMADDSUB231PSZ128mb:
30204 case VFMADDSUB231PSZ128mbk:
30205 case VFMADDSUB231PSZ128mbkz:
30206 case VFMADDSUB231PSZ128mk:
30207 case VFMADDSUB231PSZ128mkz:
30208 case VFMADDSUB231PSZ128r:
30209 case VFMADDSUB231PSZ128rk:
30210 case VFMADDSUB231PSZ128rkz:
30211 case VFMADDSUB231PSZ256m:
30212 case VFMADDSUB231PSZ256mb:
30213 case VFMADDSUB231PSZ256mbk:
30214 case VFMADDSUB231PSZ256mbkz:
30215 case VFMADDSUB231PSZ256mk:
30216 case VFMADDSUB231PSZ256mkz:
30217 case VFMADDSUB231PSZ256r:
30218 case VFMADDSUB231PSZ256rk:
30219 case VFMADDSUB231PSZ256rkz:
30220 case VFMADDSUB231PSZm:
30221 case VFMADDSUB231PSZmb:
30222 case VFMADDSUB231PSZmbk:
30223 case VFMADDSUB231PSZmbkz:
30224 case VFMADDSUB231PSZmk:
30225 case VFMADDSUB231PSZmkz:
30226 case VFMADDSUB231PSZr:
30227 case VFMADDSUB231PSZrb:
30228 case VFMADDSUB231PSZrbk:
30229 case VFMADDSUB231PSZrbkz:
30230 case VFMADDSUB231PSZrk:
30231 case VFMADDSUB231PSZrkz:
30232 case VFMADDSUB231PSm:
30233 case VFMADDSUB231PSr:
30234 return true;
30235 }
30236 return false;
30237}
30238
30239bool isVFNMSUB213PD(unsigned Opcode) {
30240 switch (Opcode) {
30241 case VFNMSUB213PDYm:
30242 case VFNMSUB213PDYr:
30243 case VFNMSUB213PDZ128m:
30244 case VFNMSUB213PDZ128mb:
30245 case VFNMSUB213PDZ128mbk:
30246 case VFNMSUB213PDZ128mbkz:
30247 case VFNMSUB213PDZ128mk:
30248 case VFNMSUB213PDZ128mkz:
30249 case VFNMSUB213PDZ128r:
30250 case VFNMSUB213PDZ128rk:
30251 case VFNMSUB213PDZ128rkz:
30252 case VFNMSUB213PDZ256m:
30253 case VFNMSUB213PDZ256mb:
30254 case VFNMSUB213PDZ256mbk:
30255 case VFNMSUB213PDZ256mbkz:
30256 case VFNMSUB213PDZ256mk:
30257 case VFNMSUB213PDZ256mkz:
30258 case VFNMSUB213PDZ256r:
30259 case VFNMSUB213PDZ256rk:
30260 case VFNMSUB213PDZ256rkz:
30261 case VFNMSUB213PDZm:
30262 case VFNMSUB213PDZmb:
30263 case VFNMSUB213PDZmbk:
30264 case VFNMSUB213PDZmbkz:
30265 case VFNMSUB213PDZmk:
30266 case VFNMSUB213PDZmkz:
30267 case VFNMSUB213PDZr:
30268 case VFNMSUB213PDZrb:
30269 case VFNMSUB213PDZrbk:
30270 case VFNMSUB213PDZrbkz:
30271 case VFNMSUB213PDZrk:
30272 case VFNMSUB213PDZrkz:
30273 case VFNMSUB213PDm:
30274 case VFNMSUB213PDr:
30275 return true;
30276 }
30277 return false;
30278}
30279
30280bool isVPCONFLICTD(unsigned Opcode) {
30281 switch (Opcode) {
30282 case VPCONFLICTDZ128rm:
30283 case VPCONFLICTDZ128rmb:
30284 case VPCONFLICTDZ128rmbk:
30285 case VPCONFLICTDZ128rmbkz:
30286 case VPCONFLICTDZ128rmk:
30287 case VPCONFLICTDZ128rmkz:
30288 case VPCONFLICTDZ128rr:
30289 case VPCONFLICTDZ128rrk:
30290 case VPCONFLICTDZ128rrkz:
30291 case VPCONFLICTDZ256rm:
30292 case VPCONFLICTDZ256rmb:
30293 case VPCONFLICTDZ256rmbk:
30294 case VPCONFLICTDZ256rmbkz:
30295 case VPCONFLICTDZ256rmk:
30296 case VPCONFLICTDZ256rmkz:
30297 case VPCONFLICTDZ256rr:
30298 case VPCONFLICTDZ256rrk:
30299 case VPCONFLICTDZ256rrkz:
30300 case VPCONFLICTDZrm:
30301 case VPCONFLICTDZrmb:
30302 case VPCONFLICTDZrmbk:
30303 case VPCONFLICTDZrmbkz:
30304 case VPCONFLICTDZrmk:
30305 case VPCONFLICTDZrmkz:
30306 case VPCONFLICTDZrr:
30307 case VPCONFLICTDZrrk:
30308 case VPCONFLICTDZrrkz:
30309 return true;
30310 }
30311 return false;
30312}
30313
30314bool isVFMADDSUB213PH(unsigned Opcode) {
30315 switch (Opcode) {
30316 case VFMADDSUB213PHZ128m:
30317 case VFMADDSUB213PHZ128mb:
30318 case VFMADDSUB213PHZ128mbk:
30319 case VFMADDSUB213PHZ128mbkz:
30320 case VFMADDSUB213PHZ128mk:
30321 case VFMADDSUB213PHZ128mkz:
30322 case VFMADDSUB213PHZ128r:
30323 case VFMADDSUB213PHZ128rk:
30324 case VFMADDSUB213PHZ128rkz:
30325 case VFMADDSUB213PHZ256m:
30326 case VFMADDSUB213PHZ256mb:
30327 case VFMADDSUB213PHZ256mbk:
30328 case VFMADDSUB213PHZ256mbkz:
30329 case VFMADDSUB213PHZ256mk:
30330 case VFMADDSUB213PHZ256mkz:
30331 case VFMADDSUB213PHZ256r:
30332 case VFMADDSUB213PHZ256rk:
30333 case VFMADDSUB213PHZ256rkz:
30334 case VFMADDSUB213PHZm:
30335 case VFMADDSUB213PHZmb:
30336 case VFMADDSUB213PHZmbk:
30337 case VFMADDSUB213PHZmbkz:
30338 case VFMADDSUB213PHZmk:
30339 case VFMADDSUB213PHZmkz:
30340 case VFMADDSUB213PHZr:
30341 case VFMADDSUB213PHZrb:
30342 case VFMADDSUB213PHZrbk:
30343 case VFMADDSUB213PHZrbkz:
30344 case VFMADDSUB213PHZrk:
30345 case VFMADDSUB213PHZrkz:
30346 return true;
30347 }
30348 return false;
30349}
30350
30351bool isVPHSUBSW(unsigned Opcode) {
30352 switch (Opcode) {
30353 case VPHSUBSWYrm:
30354 case VPHSUBSWYrr:
30355 case VPHSUBSWrm:
30356 case VPHSUBSWrr:
30357 return true;
30358 }
30359 return false;
30360}
30361
30362bool isPUNPCKHDQ(unsigned Opcode) {
30363 switch (Opcode) {
30364 case MMX_PUNPCKHDQrm:
30365 case MMX_PUNPCKHDQrr:
30366 case PUNPCKHDQrm:
30367 case PUNPCKHDQrr:
30368 return true;
30369 }
30370 return false;
30371}
30372
30373bool isVSHUFI64X2(unsigned Opcode) {
30374 switch (Opcode) {
30375 case VSHUFI64X2Z256rmbi:
30376 case VSHUFI64X2Z256rmbik:
30377 case VSHUFI64X2Z256rmbikz:
30378 case VSHUFI64X2Z256rmi:
30379 case VSHUFI64X2Z256rmik:
30380 case VSHUFI64X2Z256rmikz:
30381 case VSHUFI64X2Z256rri:
30382 case VSHUFI64X2Z256rrik:
30383 case VSHUFI64X2Z256rrikz:
30384 case VSHUFI64X2Zrmbi:
30385 case VSHUFI64X2Zrmbik:
30386 case VSHUFI64X2Zrmbikz:
30387 case VSHUFI64X2Zrmi:
30388 case VSHUFI64X2Zrmik:
30389 case VSHUFI64X2Zrmikz:
30390 case VSHUFI64X2Zrri:
30391 case VSHUFI64X2Zrrik:
30392 case VSHUFI64X2Zrrikz:
30393 return true;
30394 }
30395 return false;
30396}
30397
30398bool isVFMSUBSD(unsigned Opcode) {
30399 switch (Opcode) {
30400 case VFMSUBSD4mr:
30401 case VFMSUBSD4rm:
30402 case VFMSUBSD4rr:
30403 case VFMSUBSD4rr_REV:
30404 return true;
30405 }
30406 return false;
30407}
30408
30409bool isVPORD(unsigned Opcode) {
30410 switch (Opcode) {
30411 case VPORDZ128rm:
30412 case VPORDZ128rmb:
30413 case VPORDZ128rmbk:
30414 case VPORDZ128rmbkz:
30415 case VPORDZ128rmk:
30416 case VPORDZ128rmkz:
30417 case VPORDZ128rr:
30418 case VPORDZ128rrk:
30419 case VPORDZ128rrkz:
30420 case VPORDZ256rm:
30421 case VPORDZ256rmb:
30422 case VPORDZ256rmbk:
30423 case VPORDZ256rmbkz:
30424 case VPORDZ256rmk:
30425 case VPORDZ256rmkz:
30426 case VPORDZ256rr:
30427 case VPORDZ256rrk:
30428 case VPORDZ256rrkz:
30429 case VPORDZrm:
30430 case VPORDZrmb:
30431 case VPORDZrmbk:
30432 case VPORDZrmbkz:
30433 case VPORDZrmk:
30434 case VPORDZrmkz:
30435 case VPORDZrr:
30436 case VPORDZrrk:
30437 case VPORDZrrkz:
30438 return true;
30439 }
30440 return false;
30441}
30442
30443bool isRCPPS(unsigned Opcode) {
30444 switch (Opcode) {
30445 case RCPPSm:
30446 case RCPPSr:
30447 return true;
30448 }
30449 return false;
30450}
30451
30452bool isVEXTRACTI128(unsigned Opcode) {
30453 switch (Opcode) {
30454 case VEXTRACTI128mri:
30455 case VEXTRACTI128rri:
30456 return true;
30457 }
30458 return false;
30459}
30460
30461bool isVCVT2PH2BF8S(unsigned Opcode) {
30462 switch (Opcode) {
30463 case VCVT2PH2BF8SZ128rm:
30464 case VCVT2PH2BF8SZ128rmb:
30465 case VCVT2PH2BF8SZ128rmbk:
30466 case VCVT2PH2BF8SZ128rmbkz:
30467 case VCVT2PH2BF8SZ128rmk:
30468 case VCVT2PH2BF8SZ128rmkz:
30469 case VCVT2PH2BF8SZ128rr:
30470 case VCVT2PH2BF8SZ128rrk:
30471 case VCVT2PH2BF8SZ128rrkz:
30472 case VCVT2PH2BF8SZ256rm:
30473 case VCVT2PH2BF8SZ256rmb:
30474 case VCVT2PH2BF8SZ256rmbk:
30475 case VCVT2PH2BF8SZ256rmbkz:
30476 case VCVT2PH2BF8SZ256rmk:
30477 case VCVT2PH2BF8SZ256rmkz:
30478 case VCVT2PH2BF8SZ256rr:
30479 case VCVT2PH2BF8SZ256rrk:
30480 case VCVT2PH2BF8SZ256rrkz:
30481 case VCVT2PH2BF8SZrm:
30482 case VCVT2PH2BF8SZrmb:
30483 case VCVT2PH2BF8SZrmbk:
30484 case VCVT2PH2BF8SZrmbkz:
30485 case VCVT2PH2BF8SZrmk:
30486 case VCVT2PH2BF8SZrmkz:
30487 case VCVT2PH2BF8SZrr:
30488 case VCVT2PH2BF8SZrrk:
30489 case VCVT2PH2BF8SZrrkz:
30490 return true;
30491 }
30492 return false;
30493}
30494
30495bool isVPSHRDVW(unsigned Opcode) {
30496 switch (Opcode) {
30497 case VPSHRDVWZ128m:
30498 case VPSHRDVWZ128mk:
30499 case VPSHRDVWZ128mkz:
30500 case VPSHRDVWZ128r:
30501 case VPSHRDVWZ128rk:
30502 case VPSHRDVWZ128rkz:
30503 case VPSHRDVWZ256m:
30504 case VPSHRDVWZ256mk:
30505 case VPSHRDVWZ256mkz:
30506 case VPSHRDVWZ256r:
30507 case VPSHRDVWZ256rk:
30508 case VPSHRDVWZ256rkz:
30509 case VPSHRDVWZm:
30510 case VPSHRDVWZmk:
30511 case VPSHRDVWZmkz:
30512 case VPSHRDVWZr:
30513 case VPSHRDVWZrk:
30514 case VPSHRDVWZrkz:
30515 return true;
30516 }
30517 return false;
30518}
30519
30520bool isVUNPCKLPD(unsigned Opcode) {
30521 switch (Opcode) {
30522 case VUNPCKLPDYrm:
30523 case VUNPCKLPDYrr:
30524 case VUNPCKLPDZ128rm:
30525 case VUNPCKLPDZ128rmb:
30526 case VUNPCKLPDZ128rmbk:
30527 case VUNPCKLPDZ128rmbkz:
30528 case VUNPCKLPDZ128rmk:
30529 case VUNPCKLPDZ128rmkz:
30530 case VUNPCKLPDZ128rr:
30531 case VUNPCKLPDZ128rrk:
30532 case VUNPCKLPDZ128rrkz:
30533 case VUNPCKLPDZ256rm:
30534 case VUNPCKLPDZ256rmb:
30535 case VUNPCKLPDZ256rmbk:
30536 case VUNPCKLPDZ256rmbkz:
30537 case VUNPCKLPDZ256rmk:
30538 case VUNPCKLPDZ256rmkz:
30539 case VUNPCKLPDZ256rr:
30540 case VUNPCKLPDZ256rrk:
30541 case VUNPCKLPDZ256rrkz:
30542 case VUNPCKLPDZrm:
30543 case VUNPCKLPDZrmb:
30544 case VUNPCKLPDZrmbk:
30545 case VUNPCKLPDZrmbkz:
30546 case VUNPCKLPDZrmk:
30547 case VUNPCKLPDZrmkz:
30548 case VUNPCKLPDZrr:
30549 case VUNPCKLPDZrrk:
30550 case VUNPCKLPDZrrkz:
30551 case VUNPCKLPDrm:
30552 case VUNPCKLPDrr:
30553 return true;
30554 }
30555 return false;
30556}
30557
30558bool isVPSRAVD(unsigned Opcode) {
30559 switch (Opcode) {
30560 case VPSRAVDYrm:
30561 case VPSRAVDYrr:
30562 case VPSRAVDZ128rm:
30563 case VPSRAVDZ128rmb:
30564 case VPSRAVDZ128rmbk:
30565 case VPSRAVDZ128rmbkz:
30566 case VPSRAVDZ128rmk:
30567 case VPSRAVDZ128rmkz:
30568 case VPSRAVDZ128rr:
30569 case VPSRAVDZ128rrk:
30570 case VPSRAVDZ128rrkz:
30571 case VPSRAVDZ256rm:
30572 case VPSRAVDZ256rmb:
30573 case VPSRAVDZ256rmbk:
30574 case VPSRAVDZ256rmbkz:
30575 case VPSRAVDZ256rmk:
30576 case VPSRAVDZ256rmkz:
30577 case VPSRAVDZ256rr:
30578 case VPSRAVDZ256rrk:
30579 case VPSRAVDZ256rrkz:
30580 case VPSRAVDZrm:
30581 case VPSRAVDZrmb:
30582 case VPSRAVDZrmbk:
30583 case VPSRAVDZrmbkz:
30584 case VPSRAVDZrmk:
30585 case VPSRAVDZrmkz:
30586 case VPSRAVDZrr:
30587 case VPSRAVDZrrk:
30588 case VPSRAVDZrrkz:
30589 case VPSRAVDrm:
30590 case VPSRAVDrr:
30591 return true;
30592 }
30593 return false;
30594}
30595
30596bool isVMULSH(unsigned Opcode) {
30597 switch (Opcode) {
30598 case VMULSHZrm_Int:
30599 case VMULSHZrmk_Int:
30600 case VMULSHZrmkz_Int:
30601 case VMULSHZrr_Int:
30602 case VMULSHZrrb_Int:
30603 case VMULSHZrrbk_Int:
30604 case VMULSHZrrbkz_Int:
30605 case VMULSHZrrk_Int:
30606 case VMULSHZrrkz_Int:
30607 return true;
30608 }
30609 return false;
30610}
30611
30612bool isMOVNTSS(unsigned Opcode) {
30613 return Opcode == MOVNTSS;
30614}
30615
30616bool isSTI(unsigned Opcode) {
30617 return Opcode == STI;
30618}
30619
30620bool isVSM4RNDS4(unsigned Opcode) {
30621 switch (Opcode) {
30622 case VSM4RNDS4Yrm:
30623 case VSM4RNDS4Yrr:
30624 case VSM4RNDS4Z128rm:
30625 case VSM4RNDS4Z128rr:
30626 case VSM4RNDS4Z256rm:
30627 case VSM4RNDS4Z256rr:
30628 case VSM4RNDS4Zrm:
30629 case VSM4RNDS4Zrr:
30630 case VSM4RNDS4rm:
30631 case VSM4RNDS4rr:
30632 return true;
30633 }
30634 return false;
30635}
30636
30637bool isVMCLEAR(unsigned Opcode) {
30638 return Opcode == VMCLEARm;
30639}
30640
30641bool isVPMADD52HUQ(unsigned Opcode) {
30642 switch (Opcode) {
30643 case VPMADD52HUQYrm:
30644 case VPMADD52HUQYrr:
30645 case VPMADD52HUQZ128m:
30646 case VPMADD52HUQZ128mb:
30647 case VPMADD52HUQZ128mbk:
30648 case VPMADD52HUQZ128mbkz:
30649 case VPMADD52HUQZ128mk:
30650 case VPMADD52HUQZ128mkz:
30651 case VPMADD52HUQZ128r:
30652 case VPMADD52HUQZ128rk:
30653 case VPMADD52HUQZ128rkz:
30654 case VPMADD52HUQZ256m:
30655 case VPMADD52HUQZ256mb:
30656 case VPMADD52HUQZ256mbk:
30657 case VPMADD52HUQZ256mbkz:
30658 case VPMADD52HUQZ256mk:
30659 case VPMADD52HUQZ256mkz:
30660 case VPMADD52HUQZ256r:
30661 case VPMADD52HUQZ256rk:
30662 case VPMADD52HUQZ256rkz:
30663 case VPMADD52HUQZm:
30664 case VPMADD52HUQZmb:
30665 case VPMADD52HUQZmbk:
30666 case VPMADD52HUQZmbkz:
30667 case VPMADD52HUQZmk:
30668 case VPMADD52HUQZmkz:
30669 case VPMADD52HUQZr:
30670 case VPMADD52HUQZrk:
30671 case VPMADD52HUQZrkz:
30672 case VPMADD52HUQrm:
30673 case VPMADD52HUQrr:
30674 return true;
30675 }
30676 return false;
30677}
30678
30679bool isLIDT(unsigned Opcode) {
30680 return Opcode == LIDT64m;
30681}
30682
30683bool isPUSH2(unsigned Opcode) {
30684 return Opcode == PUSH2;
30685}
30686
30687bool isRDPKRU(unsigned Opcode) {
30688 return Opcode == RDPKRUr;
30689}
30690
30691bool isVCVTPS2IUBS(unsigned Opcode) {
30692 switch (Opcode) {
30693 case VCVTPS2IUBSZ128rm:
30694 case VCVTPS2IUBSZ128rmb:
30695 case VCVTPS2IUBSZ128rmbk:
30696 case VCVTPS2IUBSZ128rmbkz:
30697 case VCVTPS2IUBSZ128rmk:
30698 case VCVTPS2IUBSZ128rmkz:
30699 case VCVTPS2IUBSZ128rr:
30700 case VCVTPS2IUBSZ128rrk:
30701 case VCVTPS2IUBSZ128rrkz:
30702 case VCVTPS2IUBSZ256rm:
30703 case VCVTPS2IUBSZ256rmb:
30704 case VCVTPS2IUBSZ256rmbk:
30705 case VCVTPS2IUBSZ256rmbkz:
30706 case VCVTPS2IUBSZ256rmk:
30707 case VCVTPS2IUBSZ256rmkz:
30708 case VCVTPS2IUBSZ256rr:
30709 case VCVTPS2IUBSZ256rrk:
30710 case VCVTPS2IUBSZ256rrkz:
30711 case VCVTPS2IUBSZrm:
30712 case VCVTPS2IUBSZrmb:
30713 case VCVTPS2IUBSZrmbk:
30714 case VCVTPS2IUBSZrmbkz:
30715 case VCVTPS2IUBSZrmk:
30716 case VCVTPS2IUBSZrmkz:
30717 case VCVTPS2IUBSZrr:
30718 case VCVTPS2IUBSZrrb:
30719 case VCVTPS2IUBSZrrbk:
30720 case VCVTPS2IUBSZrrbkz:
30721 case VCVTPS2IUBSZrrk:
30722 case VCVTPS2IUBSZrrkz:
30723 return true;
30724 }
30725 return false;
30726}
30727
30728bool isXSAVES64(unsigned Opcode) {
30729 return Opcode == XSAVES64;
30730}
30731
30732bool isVPCMPB(unsigned Opcode) {
30733 switch (Opcode) {
30734 case VPCMPBZ128rmi:
30735 case VPCMPBZ128rmik:
30736 case VPCMPBZ128rri:
30737 case VPCMPBZ128rrik:
30738 case VPCMPBZ256rmi:
30739 case VPCMPBZ256rmik:
30740 case VPCMPBZ256rri:
30741 case VPCMPBZ256rrik:
30742 case VPCMPBZrmi:
30743 case VPCMPBZrmik:
30744 case VPCMPBZrri:
30745 case VPCMPBZrrik:
30746 return true;
30747 }
30748 return false;
30749}
30750
30751bool isVFMSUB231BF16(unsigned Opcode) {
30752 switch (Opcode) {
30753 case VFMSUB231BF16Z128m:
30754 case VFMSUB231BF16Z128mb:
30755 case VFMSUB231BF16Z128mbk:
30756 case VFMSUB231BF16Z128mbkz:
30757 case VFMSUB231BF16Z128mk:
30758 case VFMSUB231BF16Z128mkz:
30759 case VFMSUB231BF16Z128r:
30760 case VFMSUB231BF16Z128rk:
30761 case VFMSUB231BF16Z128rkz:
30762 case VFMSUB231BF16Z256m:
30763 case VFMSUB231BF16Z256mb:
30764 case VFMSUB231BF16Z256mbk:
30765 case VFMSUB231BF16Z256mbkz:
30766 case VFMSUB231BF16Z256mk:
30767 case VFMSUB231BF16Z256mkz:
30768 case VFMSUB231BF16Z256r:
30769 case VFMSUB231BF16Z256rk:
30770 case VFMSUB231BF16Z256rkz:
30771 case VFMSUB231BF16Zm:
30772 case VFMSUB231BF16Zmb:
30773 case VFMSUB231BF16Zmbk:
30774 case VFMSUB231BF16Zmbkz:
30775 case VFMSUB231BF16Zmk:
30776 case VFMSUB231BF16Zmkz:
30777 case VFMSUB231BF16Zr:
30778 case VFMSUB231BF16Zrk:
30779 case VFMSUB231BF16Zrkz:
30780 return true;
30781 }
30782 return false;
30783}
30784
30785bool isFINCSTP(unsigned Opcode) {
30786 return Opcode == FINCSTP;
30787}
30788
30789bool isKORQ(unsigned Opcode) {
30790 return Opcode == KORQkk;
30791}
30792
30793bool isRDPMC(unsigned Opcode) {
30794 return Opcode == RDPMC;
30795}
30796
30797bool isVEXTRACTF128(unsigned Opcode) {
30798 switch (Opcode) {
30799 case VEXTRACTF128mri:
30800 case VEXTRACTF128rri:
30801 return true;
30802 }
30803 return false;
30804}
30805
30806bool isMOVMSKPD(unsigned Opcode) {
30807 return Opcode == MOVMSKPDrr;
30808}
30809
30810bool isVFMSUB231SH(unsigned Opcode) {
30811 switch (Opcode) {
30812 case VFMSUB231SHZm_Int:
30813 case VFMSUB231SHZmk_Int:
30814 case VFMSUB231SHZmkz_Int:
30815 case VFMSUB231SHZr_Int:
30816 case VFMSUB231SHZrb_Int:
30817 case VFMSUB231SHZrbk_Int:
30818 case VFMSUB231SHZrbkz_Int:
30819 case VFMSUB231SHZrk_Int:
30820 case VFMSUB231SHZrkz_Int:
30821 return true;
30822 }
30823 return false;
30824}
30825
30826bool isVPSHLB(unsigned Opcode) {
30827 switch (Opcode) {
30828 case VPSHLBmr:
30829 case VPSHLBrm:
30830 case VPSHLBrr:
30831 case VPSHLBrr_REV:
30832 return true;
30833 }
30834 return false;
30835}
30836
30837bool isXCRYPTCBC(unsigned Opcode) {
30838 return Opcode == XCRYPTCBC;
30839}
30840
30841bool isSHL(unsigned Opcode) {
30842 switch (Opcode) {
30843 case SHL16m1:
30844 case SHL16m1_EVEX:
30845 case SHL16m1_ND:
30846 case SHL16m1_NF:
30847 case SHL16m1_NF_ND:
30848 case SHL16mCL:
30849 case SHL16mCL_EVEX:
30850 case SHL16mCL_ND:
30851 case SHL16mCL_NF:
30852 case SHL16mCL_NF_ND:
30853 case SHL16mi:
30854 case SHL16mi_EVEX:
30855 case SHL16mi_ND:
30856 case SHL16mi_NF:
30857 case SHL16mi_NF_ND:
30858 case SHL16r1:
30859 case SHL16r1_EVEX:
30860 case SHL16r1_ND:
30861 case SHL16r1_NF:
30862 case SHL16r1_NF_ND:
30863 case SHL16rCL:
30864 case SHL16rCL_EVEX:
30865 case SHL16rCL_ND:
30866 case SHL16rCL_NF:
30867 case SHL16rCL_NF_ND:
30868 case SHL16ri:
30869 case SHL16ri_EVEX:
30870 case SHL16ri_ND:
30871 case SHL16ri_NF:
30872 case SHL16ri_NF_ND:
30873 case SHL32m1:
30874 case SHL32m1_EVEX:
30875 case SHL32m1_ND:
30876 case SHL32m1_NF:
30877 case SHL32m1_NF_ND:
30878 case SHL32mCL:
30879 case SHL32mCL_EVEX:
30880 case SHL32mCL_ND:
30881 case SHL32mCL_NF:
30882 case SHL32mCL_NF_ND:
30883 case SHL32mi:
30884 case SHL32mi_EVEX:
30885 case SHL32mi_ND:
30886 case SHL32mi_NF:
30887 case SHL32mi_NF_ND:
30888 case SHL32r1:
30889 case SHL32r1_EVEX:
30890 case SHL32r1_ND:
30891 case SHL32r1_NF:
30892 case SHL32r1_NF_ND:
30893 case SHL32rCL:
30894 case SHL32rCL_EVEX:
30895 case SHL32rCL_ND:
30896 case SHL32rCL_NF:
30897 case SHL32rCL_NF_ND:
30898 case SHL32ri:
30899 case SHL32ri_EVEX:
30900 case SHL32ri_ND:
30901 case SHL32ri_NF:
30902 case SHL32ri_NF_ND:
30903 case SHL64m1:
30904 case SHL64m1_EVEX:
30905 case SHL64m1_ND:
30906 case SHL64m1_NF:
30907 case SHL64m1_NF_ND:
30908 case SHL64mCL:
30909 case SHL64mCL_EVEX:
30910 case SHL64mCL_ND:
30911 case SHL64mCL_NF:
30912 case SHL64mCL_NF_ND:
30913 case SHL64mi:
30914 case SHL64mi_EVEX:
30915 case SHL64mi_ND:
30916 case SHL64mi_NF:
30917 case SHL64mi_NF_ND:
30918 case SHL64r1:
30919 case SHL64r1_EVEX:
30920 case SHL64r1_ND:
30921 case SHL64r1_NF:
30922 case SHL64r1_NF_ND:
30923 case SHL64rCL:
30924 case SHL64rCL_EVEX:
30925 case SHL64rCL_ND:
30926 case SHL64rCL_NF:
30927 case SHL64rCL_NF_ND:
30928 case SHL64ri:
30929 case SHL64ri_EVEX:
30930 case SHL64ri_ND:
30931 case SHL64ri_NF:
30932 case SHL64ri_NF_ND:
30933 case SHL8m1:
30934 case SHL8m1_EVEX:
30935 case SHL8m1_ND:
30936 case SHL8m1_NF:
30937 case SHL8m1_NF_ND:
30938 case SHL8mCL:
30939 case SHL8mCL_EVEX:
30940 case SHL8mCL_ND:
30941 case SHL8mCL_NF:
30942 case SHL8mCL_NF_ND:
30943 case SHL8mi:
30944 case SHL8mi_EVEX:
30945 case SHL8mi_ND:
30946 case SHL8mi_NF:
30947 case SHL8mi_NF_ND:
30948 case SHL8r1:
30949 case SHL8r1_EVEX:
30950 case SHL8r1_ND:
30951 case SHL8r1_NF:
30952 case SHL8r1_NF_ND:
30953 case SHL8rCL:
30954 case SHL8rCL_EVEX:
30955 case SHL8rCL_ND:
30956 case SHL8rCL_NF:
30957 case SHL8rCL_NF_ND:
30958 case SHL8ri:
30959 case SHL8ri_EVEX:
30960 case SHL8ri_ND:
30961 case SHL8ri_NF:
30962 case SHL8ri_NF_ND:
30963 return true;
30964 }
30965 return false;
30966}
30967
30968bool isAXOR(unsigned Opcode) {
30969 switch (Opcode) {
30970 case AXOR32mr:
30971 case AXOR32mr_EVEX:
30972 case AXOR64mr:
30973 case AXOR64mr_EVEX:
30974 return true;
30975 }
30976 return false;
30977}
30978
30979bool isVINSERTI64X2(unsigned Opcode) {
30980 switch (Opcode) {
30981 case VINSERTI64X2Z256rmi:
30982 case VINSERTI64X2Z256rmik:
30983 case VINSERTI64X2Z256rmikz:
30984 case VINSERTI64X2Z256rri:
30985 case VINSERTI64X2Z256rrik:
30986 case VINSERTI64X2Z256rrikz:
30987 case VINSERTI64X2Zrmi:
30988 case VINSERTI64X2Zrmik:
30989 case VINSERTI64X2Zrmikz:
30990 case VINSERTI64X2Zrri:
30991 case VINSERTI64X2Zrrik:
30992 case VINSERTI64X2Zrrikz:
30993 return true;
30994 }
30995 return false;
30996}
30997
30998bool isSYSRETQ(unsigned Opcode) {
30999 return Opcode == SYSRET64;
31000}
31001
31002bool isVSCATTERPF0QPD(unsigned Opcode) {
31003 return Opcode == VSCATTERPF0QPDm;
31004}
31005
31006bool isVFMSUB213SH(unsigned Opcode) {
31007 switch (Opcode) {
31008 case VFMSUB213SHZm_Int:
31009 case VFMSUB213SHZmk_Int:
31010 case VFMSUB213SHZmkz_Int:
31011 case VFMSUB213SHZr_Int:
31012 case VFMSUB213SHZrb_Int:
31013 case VFMSUB213SHZrbk_Int:
31014 case VFMSUB213SHZrbkz_Int:
31015 case VFMSUB213SHZrk_Int:
31016 case VFMSUB213SHZrkz_Int:
31017 return true;
31018 }
31019 return false;
31020}
31021
31022bool isVPMOVQW(unsigned Opcode) {
31023 switch (Opcode) {
31024 case VPMOVQWZ128mr:
31025 case VPMOVQWZ128mrk:
31026 case VPMOVQWZ128rr:
31027 case VPMOVQWZ128rrk:
31028 case VPMOVQWZ128rrkz:
31029 case VPMOVQWZ256mr:
31030 case VPMOVQWZ256mrk:
31031 case VPMOVQWZ256rr:
31032 case VPMOVQWZ256rrk:
31033 case VPMOVQWZ256rrkz:
31034 case VPMOVQWZmr:
31035 case VPMOVQWZmrk:
31036 case VPMOVQWZrr:
31037 case VPMOVQWZrrk:
31038 case VPMOVQWZrrkz:
31039 return true;
31040 }
31041 return false;
31042}
31043
31044bool isVREDUCEPD(unsigned Opcode) {
31045 switch (Opcode) {
31046 case VREDUCEPDZ128rmbi:
31047 case VREDUCEPDZ128rmbik:
31048 case VREDUCEPDZ128rmbikz:
31049 case VREDUCEPDZ128rmi:
31050 case VREDUCEPDZ128rmik:
31051 case VREDUCEPDZ128rmikz:
31052 case VREDUCEPDZ128rri:
31053 case VREDUCEPDZ128rrik:
31054 case VREDUCEPDZ128rrikz:
31055 case VREDUCEPDZ256rmbi:
31056 case VREDUCEPDZ256rmbik:
31057 case VREDUCEPDZ256rmbikz:
31058 case VREDUCEPDZ256rmi:
31059 case VREDUCEPDZ256rmik:
31060 case VREDUCEPDZ256rmikz:
31061 case VREDUCEPDZ256rri:
31062 case VREDUCEPDZ256rrik:
31063 case VREDUCEPDZ256rrikz:
31064 case VREDUCEPDZrmbi:
31065 case VREDUCEPDZrmbik:
31066 case VREDUCEPDZrmbikz:
31067 case VREDUCEPDZrmi:
31068 case VREDUCEPDZrmik:
31069 case VREDUCEPDZrmikz:
31070 case VREDUCEPDZrri:
31071 case VREDUCEPDZrrib:
31072 case VREDUCEPDZrribk:
31073 case VREDUCEPDZrribkz:
31074 case VREDUCEPDZrrik:
31075 case VREDUCEPDZrrikz:
31076 return true;
31077 }
31078 return false;
31079}
31080
31081bool isNOT(unsigned Opcode) {
31082 switch (Opcode) {
31083 case NOT16m:
31084 case NOT16m_EVEX:
31085 case NOT16m_ND:
31086 case NOT16r:
31087 case NOT16r_EVEX:
31088 case NOT16r_ND:
31089 case NOT32m:
31090 case NOT32m_EVEX:
31091 case NOT32m_ND:
31092 case NOT32r:
31093 case NOT32r_EVEX:
31094 case NOT32r_ND:
31095 case NOT64m:
31096 case NOT64m_EVEX:
31097 case NOT64m_ND:
31098 case NOT64r:
31099 case NOT64r_EVEX:
31100 case NOT64r_ND:
31101 case NOT8m:
31102 case NOT8m_EVEX:
31103 case NOT8m_ND:
31104 case NOT8r:
31105 case NOT8r_EVEX:
31106 case NOT8r_ND:
31107 return true;
31108 }
31109 return false;
31110}
31111
31112bool isLWPINS(unsigned Opcode) {
31113 switch (Opcode) {
31114 case LWPINS32rmi:
31115 case LWPINS32rri:
31116 case LWPINS64rmi:
31117 case LWPINS64rri:
31118 return true;
31119 }
31120 return false;
31121}
31122
31123bool isVSCATTERDPS(unsigned Opcode) {
31124 switch (Opcode) {
31125 case VSCATTERDPSZ128mr:
31126 case VSCATTERDPSZ256mr:
31127 case VSCATTERDPSZmr:
31128 return true;
31129 }
31130 return false;
31131}
31132
31133bool isVPMOVM2W(unsigned Opcode) {
31134 switch (Opcode) {
31135 case VPMOVM2WZ128rk:
31136 case VPMOVM2WZ256rk:
31137 case VPMOVM2WZrk:
31138 return true;
31139 }
31140 return false;
31141}
31142
31143bool isVFNMADD132PS(unsigned Opcode) {
31144 switch (Opcode) {
31145 case VFNMADD132PSYm:
31146 case VFNMADD132PSYr:
31147 case VFNMADD132PSZ128m:
31148 case VFNMADD132PSZ128mb:
31149 case VFNMADD132PSZ128mbk:
31150 case VFNMADD132PSZ128mbkz:
31151 case VFNMADD132PSZ128mk:
31152 case VFNMADD132PSZ128mkz:
31153 case VFNMADD132PSZ128r:
31154 case VFNMADD132PSZ128rk:
31155 case VFNMADD132PSZ128rkz:
31156 case VFNMADD132PSZ256m:
31157 case VFNMADD132PSZ256mb:
31158 case VFNMADD132PSZ256mbk:
31159 case VFNMADD132PSZ256mbkz:
31160 case VFNMADD132PSZ256mk:
31161 case VFNMADD132PSZ256mkz:
31162 case VFNMADD132PSZ256r:
31163 case VFNMADD132PSZ256rk:
31164 case VFNMADD132PSZ256rkz:
31165 case VFNMADD132PSZm:
31166 case VFNMADD132PSZmb:
31167 case VFNMADD132PSZmbk:
31168 case VFNMADD132PSZmbkz:
31169 case VFNMADD132PSZmk:
31170 case VFNMADD132PSZmkz:
31171 case VFNMADD132PSZr:
31172 case VFNMADD132PSZrb:
31173 case VFNMADD132PSZrbk:
31174 case VFNMADD132PSZrbkz:
31175 case VFNMADD132PSZrk:
31176 case VFNMADD132PSZrkz:
31177 case VFNMADD132PSm:
31178 case VFNMADD132PSr:
31179 return true;
31180 }
31181 return false;
31182}
31183
31184bool isMOVNTPS(unsigned Opcode) {
31185 return Opcode == MOVNTPSmr;
31186}
31187
31188bool isVRSQRTSS(unsigned Opcode) {
31189 switch (Opcode) {
31190 case VRSQRTSSm_Int:
31191 case VRSQRTSSr_Int:
31192 return true;
31193 }
31194 return false;
31195}
31196
31197bool isKMOVB(unsigned Opcode) {
31198 switch (Opcode) {
31199 case KMOVBkk:
31200 case KMOVBkk_EVEX:
31201 case KMOVBkm:
31202 case KMOVBkm_EVEX:
31203 case KMOVBkr:
31204 case KMOVBkr_EVEX:
31205 case KMOVBmk:
31206 case KMOVBmk_EVEX:
31207 case KMOVBrk:
31208 case KMOVBrk_EVEX:
31209 return true;
31210 }
31211 return false;
31212}
31213
31214bool isCVTSD2SS(unsigned Opcode) {
31215 switch (Opcode) {
31216 case CVTSD2SSrm_Int:
31217 case CVTSD2SSrr_Int:
31218 return true;
31219 }
31220 return false;
31221}
31222
31223bool isVBROADCASTF64X2(unsigned Opcode) {
31224 switch (Opcode) {
31225 case VBROADCASTF64X2Z256rm:
31226 case VBROADCASTF64X2Z256rmk:
31227 case VBROADCASTF64X2Z256rmkz:
31228 case VBROADCASTF64X2Zrm:
31229 case VBROADCASTF64X2Zrmk:
31230 case VBROADCASTF64X2Zrmkz:
31231 return true;
31232 }
31233 return false;
31234}
31235
31236bool isVDIVBF16(unsigned Opcode) {
31237 switch (Opcode) {
31238 case VDIVBF16Z128rm:
31239 case VDIVBF16Z128rmb:
31240 case VDIVBF16Z128rmbk:
31241 case VDIVBF16Z128rmbkz:
31242 case VDIVBF16Z128rmk:
31243 case VDIVBF16Z128rmkz:
31244 case VDIVBF16Z128rr:
31245 case VDIVBF16Z128rrk:
31246 case VDIVBF16Z128rrkz:
31247 case VDIVBF16Z256rm:
31248 case VDIVBF16Z256rmb:
31249 case VDIVBF16Z256rmbk:
31250 case VDIVBF16Z256rmbkz:
31251 case VDIVBF16Z256rmk:
31252 case VDIVBF16Z256rmkz:
31253 case VDIVBF16Z256rr:
31254 case VDIVBF16Z256rrk:
31255 case VDIVBF16Z256rrkz:
31256 case VDIVBF16Zrm:
31257 case VDIVBF16Zrmb:
31258 case VDIVBF16Zrmbk:
31259 case VDIVBF16Zrmbkz:
31260 case VDIVBF16Zrmk:
31261 case VDIVBF16Zrmkz:
31262 case VDIVBF16Zrr:
31263 case VDIVBF16Zrrk:
31264 case VDIVBF16Zrrkz:
31265 return true;
31266 }
31267 return false;
31268}
31269
31270bool isMOVNTPD(unsigned Opcode) {
31271 return Opcode == MOVNTPDmr;
31272}
31273
31274bool isMAXSD(unsigned Opcode) {
31275 switch (Opcode) {
31276 case MAXSDrm_Int:
31277 case MAXSDrr_Int:
31278 return true;
31279 }
31280 return false;
31281}
31282
31283bool isCMPPD(unsigned Opcode) {
31284 switch (Opcode) {
31285 case CMPPDrmi:
31286 case CMPPDrri:
31287 return true;
31288 }
31289 return false;
31290}
31291
31292bool isVPCMPESTRM(unsigned Opcode) {
31293 switch (Opcode) {
31294 case VPCMPESTRMrmi:
31295 case VPCMPESTRMrri:
31296 return true;
31297 }
31298 return false;
31299}
31300
31301bool isVFMSUB132PS(unsigned Opcode) {
31302 switch (Opcode) {
31303 case VFMSUB132PSYm:
31304 case VFMSUB132PSYr:
31305 case VFMSUB132PSZ128m:
31306 case VFMSUB132PSZ128mb:
31307 case VFMSUB132PSZ128mbk:
31308 case VFMSUB132PSZ128mbkz:
31309 case VFMSUB132PSZ128mk:
31310 case VFMSUB132PSZ128mkz:
31311 case VFMSUB132PSZ128r:
31312 case VFMSUB132PSZ128rk:
31313 case VFMSUB132PSZ128rkz:
31314 case VFMSUB132PSZ256m:
31315 case VFMSUB132PSZ256mb:
31316 case VFMSUB132PSZ256mbk:
31317 case VFMSUB132PSZ256mbkz:
31318 case VFMSUB132PSZ256mk:
31319 case VFMSUB132PSZ256mkz:
31320 case VFMSUB132PSZ256r:
31321 case VFMSUB132PSZ256rk:
31322 case VFMSUB132PSZ256rkz:
31323 case VFMSUB132PSZm:
31324 case VFMSUB132PSZmb:
31325 case VFMSUB132PSZmbk:
31326 case VFMSUB132PSZmbkz:
31327 case VFMSUB132PSZmk:
31328 case VFMSUB132PSZmkz:
31329 case VFMSUB132PSZr:
31330 case VFMSUB132PSZrb:
31331 case VFMSUB132PSZrbk:
31332 case VFMSUB132PSZrbkz:
31333 case VFMSUB132PSZrk:
31334 case VFMSUB132PSZrkz:
31335 case VFMSUB132PSm:
31336 case VFMSUB132PSr:
31337 return true;
31338 }
31339 return false;
31340}
31341
31342bool isVCOMISH(unsigned Opcode) {
31343 switch (Opcode) {
31344 case VCOMISHZrm:
31345 case VCOMISHZrr:
31346 case VCOMISHZrrb:
31347 return true;
31348 }
31349 return false;
31350}
31351
31352bool isF2XM1(unsigned Opcode) {
31353 return Opcode == F2XM1;
31354}
31355
31356bool isSQRTPD(unsigned Opcode) {
31357 switch (Opcode) {
31358 case SQRTPDm:
31359 case SQRTPDr:
31360 return true;
31361 }
31362 return false;
31363}
31364
31365bool isVFMSUBADDPS(unsigned Opcode) {
31366 switch (Opcode) {
31367 case VFMSUBADDPS4Ymr:
31368 case VFMSUBADDPS4Yrm:
31369 case VFMSUBADDPS4Yrr:
31370 case VFMSUBADDPS4Yrr_REV:
31371 case VFMSUBADDPS4mr:
31372 case VFMSUBADDPS4rm:
31373 case VFMSUBADDPS4rr:
31374 case VFMSUBADDPS4rr_REV:
31375 return true;
31376 }
31377 return false;
31378}
31379
31380bool isFXTRACT(unsigned Opcode) {
31381 return Opcode == FXTRACT;
31382}
31383
31384bool isVP4DPWSSD(unsigned Opcode) {
31385 switch (Opcode) {
31386 case VP4DPWSSDrm:
31387 case VP4DPWSSDrmk:
31388 case VP4DPWSSDrmkz:
31389 return true;
31390 }
31391 return false;
31392}
31393
31394bool isTDPBHF8PS(unsigned Opcode) {
31395 return Opcode == TDPBHF8PS;
31396}
31397
31398bool isVFMSUBADDPD(unsigned Opcode) {
31399 switch (Opcode) {
31400 case VFMSUBADDPD4Ymr:
31401 case VFMSUBADDPD4Yrm:
31402 case VFMSUBADDPD4Yrr:
31403 case VFMSUBADDPD4Yrr_REV:
31404 case VFMSUBADDPD4mr:
31405 case VFMSUBADDPD4rm:
31406 case VFMSUBADDPD4rr:
31407 case VFMSUBADDPD4rr_REV:
31408 return true;
31409 }
31410 return false;
31411}
31412
31413bool isVBCSTNEBF162PS(unsigned Opcode) {
31414 switch (Opcode) {
31415 case VBCSTNEBF162PSYrm:
31416 case VBCSTNEBF162PSrm:
31417 return true;
31418 }
31419 return false;
31420}
31421
31422bool isVPGATHERQQ(unsigned Opcode) {
31423 switch (Opcode) {
31424 case VPGATHERQQYrm:
31425 case VPGATHERQQZ128rm:
31426 case VPGATHERQQZ256rm:
31427 case VPGATHERQQZrm:
31428 case VPGATHERQQrm:
31429 return true;
31430 }
31431 return false;
31432}
31433
31434bool isPCMPEQB(unsigned Opcode) {
31435 switch (Opcode) {
31436 case MMX_PCMPEQBrm:
31437 case MMX_PCMPEQBrr:
31438 case PCMPEQBrm:
31439 case PCMPEQBrr:
31440 return true;
31441 }
31442 return false;
31443}
31444
31445bool isTILESTORED(unsigned Opcode) {
31446 switch (Opcode) {
31447 case TILESTORED:
31448 case TILESTORED_EVEX:
31449 return true;
31450 }
31451 return false;
31452}
31453
31454bool isBLSMSK(unsigned Opcode) {
31455 switch (Opcode) {
31456 case BLSMSK32rm:
31457 case BLSMSK32rm_EVEX:
31458 case BLSMSK32rm_NF:
31459 case BLSMSK32rr:
31460 case BLSMSK32rr_EVEX:
31461 case BLSMSK32rr_NF:
31462 case BLSMSK64rm:
31463 case BLSMSK64rm_EVEX:
31464 case BLSMSK64rm_NF:
31465 case BLSMSK64rr:
31466 case BLSMSK64rr_EVEX:
31467 case BLSMSK64rr_NF:
31468 return true;
31469 }
31470 return false;
31471}
31472
31473bool isVCVTTPS2DQ(unsigned Opcode) {
31474 switch (Opcode) {
31475 case VCVTTPS2DQYrm:
31476 case VCVTTPS2DQYrr:
31477 case VCVTTPS2DQZ128rm:
31478 case VCVTTPS2DQZ128rmb:
31479 case VCVTTPS2DQZ128rmbk:
31480 case VCVTTPS2DQZ128rmbkz:
31481 case VCVTTPS2DQZ128rmk:
31482 case VCVTTPS2DQZ128rmkz:
31483 case VCVTTPS2DQZ128rr:
31484 case VCVTTPS2DQZ128rrk:
31485 case VCVTTPS2DQZ128rrkz:
31486 case VCVTTPS2DQZ256rm:
31487 case VCVTTPS2DQZ256rmb:
31488 case VCVTTPS2DQZ256rmbk:
31489 case VCVTTPS2DQZ256rmbkz:
31490 case VCVTTPS2DQZ256rmk:
31491 case VCVTTPS2DQZ256rmkz:
31492 case VCVTTPS2DQZ256rr:
31493 case VCVTTPS2DQZ256rrk:
31494 case VCVTTPS2DQZ256rrkz:
31495 case VCVTTPS2DQZrm:
31496 case VCVTTPS2DQZrmb:
31497 case VCVTTPS2DQZrmbk:
31498 case VCVTTPS2DQZrmbkz:
31499 case VCVTTPS2DQZrmk:
31500 case VCVTTPS2DQZrmkz:
31501 case VCVTTPS2DQZrr:
31502 case VCVTTPS2DQZrrb:
31503 case VCVTTPS2DQZrrbk:
31504 case VCVTTPS2DQZrrbkz:
31505 case VCVTTPS2DQZrrk:
31506 case VCVTTPS2DQZrrkz:
31507 case VCVTTPS2DQrm:
31508 case VCVTTPS2DQrr:
31509 return true;
31510 }
31511 return false;
31512}
31513
31514bool isVFPCLASSBF16(unsigned Opcode) {
31515 switch (Opcode) {
31516 case VFPCLASSBF16Z128mbi:
31517 case VFPCLASSBF16Z128mbik:
31518 case VFPCLASSBF16Z128mi:
31519 case VFPCLASSBF16Z128mik:
31520 case VFPCLASSBF16Z128ri:
31521 case VFPCLASSBF16Z128rik:
31522 case VFPCLASSBF16Z256mbi:
31523 case VFPCLASSBF16Z256mbik:
31524 case VFPCLASSBF16Z256mi:
31525 case VFPCLASSBF16Z256mik:
31526 case VFPCLASSBF16Z256ri:
31527 case VFPCLASSBF16Z256rik:
31528 case VFPCLASSBF16Zmbi:
31529 case VFPCLASSBF16Zmbik:
31530 case VFPCLASSBF16Zmi:
31531 case VFPCLASSBF16Zmik:
31532 case VFPCLASSBF16Zri:
31533 case VFPCLASSBF16Zrik:
31534 return true;
31535 }
31536 return false;
31537}
31538
31539bool isVRNDSCALEPD(unsigned Opcode) {
31540 switch (Opcode) {
31541 case VRNDSCALEPDZ128rmbi:
31542 case VRNDSCALEPDZ128rmbik:
31543 case VRNDSCALEPDZ128rmbikz:
31544 case VRNDSCALEPDZ128rmi:
31545 case VRNDSCALEPDZ128rmik:
31546 case VRNDSCALEPDZ128rmikz:
31547 case VRNDSCALEPDZ128rri:
31548 case VRNDSCALEPDZ128rrik:
31549 case VRNDSCALEPDZ128rrikz:
31550 case VRNDSCALEPDZ256rmbi:
31551 case VRNDSCALEPDZ256rmbik:
31552 case VRNDSCALEPDZ256rmbikz:
31553 case VRNDSCALEPDZ256rmi:
31554 case VRNDSCALEPDZ256rmik:
31555 case VRNDSCALEPDZ256rmikz:
31556 case VRNDSCALEPDZ256rri:
31557 case VRNDSCALEPDZ256rrik:
31558 case VRNDSCALEPDZ256rrikz:
31559 case VRNDSCALEPDZrmbi:
31560 case VRNDSCALEPDZrmbik:
31561 case VRNDSCALEPDZrmbikz:
31562 case VRNDSCALEPDZrmi:
31563 case VRNDSCALEPDZrmik:
31564 case VRNDSCALEPDZrmikz:
31565 case VRNDSCALEPDZrri:
31566 case VRNDSCALEPDZrrib:
31567 case VRNDSCALEPDZrribk:
31568 case VRNDSCALEPDZrribkz:
31569 case VRNDSCALEPDZrrik:
31570 case VRNDSCALEPDZrrikz:
31571 return true;
31572 }
31573 return false;
31574}
31575
31576bool isVMLOAD(unsigned Opcode) {
31577 switch (Opcode) {
31578 case VMLOAD32:
31579 case VMLOAD64:
31580 return true;
31581 }
31582 return false;
31583}
31584
31585bool isVPTERNLOGQ(unsigned Opcode) {
31586 switch (Opcode) {
31587 case VPTERNLOGQZ128rmbi:
31588 case VPTERNLOGQZ128rmbik:
31589 case VPTERNLOGQZ128rmbikz:
31590 case VPTERNLOGQZ128rmi:
31591 case VPTERNLOGQZ128rmik:
31592 case VPTERNLOGQZ128rmikz:
31593 case VPTERNLOGQZ128rri:
31594 case VPTERNLOGQZ128rrik:
31595 case VPTERNLOGQZ128rrikz:
31596 case VPTERNLOGQZ256rmbi:
31597 case VPTERNLOGQZ256rmbik:
31598 case VPTERNLOGQZ256rmbikz:
31599 case VPTERNLOGQZ256rmi:
31600 case VPTERNLOGQZ256rmik:
31601 case VPTERNLOGQZ256rmikz:
31602 case VPTERNLOGQZ256rri:
31603 case VPTERNLOGQZ256rrik:
31604 case VPTERNLOGQZ256rrikz:
31605 case VPTERNLOGQZrmbi:
31606 case VPTERNLOGQZrmbik:
31607 case VPTERNLOGQZrmbikz:
31608 case VPTERNLOGQZrmi:
31609 case VPTERNLOGQZrmik:
31610 case VPTERNLOGQZrmikz:
31611 case VPTERNLOGQZrri:
31612 case VPTERNLOGQZrrik:
31613 case VPTERNLOGQZrrikz:
31614 return true;
31615 }
31616 return false;
31617}
31618
31619bool isKXNORD(unsigned Opcode) {
31620 return Opcode == KXNORDkk;
31621}
31622
31623bool isFXSAVE(unsigned Opcode) {
31624 return Opcode == FXSAVE;
31625}
31626
31627bool isVUNPCKHPD(unsigned Opcode) {
31628 switch (Opcode) {
31629 case VUNPCKHPDYrm:
31630 case VUNPCKHPDYrr:
31631 case VUNPCKHPDZ128rm:
31632 case VUNPCKHPDZ128rmb:
31633 case VUNPCKHPDZ128rmbk:
31634 case VUNPCKHPDZ128rmbkz:
31635 case VUNPCKHPDZ128rmk:
31636 case VUNPCKHPDZ128rmkz:
31637 case VUNPCKHPDZ128rr:
31638 case VUNPCKHPDZ128rrk:
31639 case VUNPCKHPDZ128rrkz:
31640 case VUNPCKHPDZ256rm:
31641 case VUNPCKHPDZ256rmb:
31642 case VUNPCKHPDZ256rmbk:
31643 case VUNPCKHPDZ256rmbkz:
31644 case VUNPCKHPDZ256rmk:
31645 case VUNPCKHPDZ256rmkz:
31646 case VUNPCKHPDZ256rr:
31647 case VUNPCKHPDZ256rrk:
31648 case VUNPCKHPDZ256rrkz:
31649 case VUNPCKHPDZrm:
31650 case VUNPCKHPDZrmb:
31651 case VUNPCKHPDZrmbk:
31652 case VUNPCKHPDZrmbkz:
31653 case VUNPCKHPDZrmk:
31654 case VUNPCKHPDZrmkz:
31655 case VUNPCKHPDZrr:
31656 case VUNPCKHPDZrrk:
31657 case VUNPCKHPDZrrkz:
31658 case VUNPCKHPDrm:
31659 case VUNPCKHPDrr:
31660 return true;
31661 }
31662 return false;
31663}
31664
31665bool isCVTPS2DQ(unsigned Opcode) {
31666 switch (Opcode) {
31667 case CVTPS2DQrm:
31668 case CVTPS2DQrr:
31669 return true;
31670 }
31671 return false;
31672}
31673
31674bool isVFMSUB213SS(unsigned Opcode) {
31675 switch (Opcode) {
31676 case VFMSUB213SSZm_Int:
31677 case VFMSUB213SSZmk_Int:
31678 case VFMSUB213SSZmkz_Int:
31679 case VFMSUB213SSZr_Int:
31680 case VFMSUB213SSZrb_Int:
31681 case VFMSUB213SSZrbk_Int:
31682 case VFMSUB213SSZrbkz_Int:
31683 case VFMSUB213SSZrk_Int:
31684 case VFMSUB213SSZrkz_Int:
31685 case VFMSUB213SSm_Int:
31686 case VFMSUB213SSr_Int:
31687 return true;
31688 }
31689 return false;
31690}
31691
31692bool isVPOPCNTD(unsigned Opcode) {
31693 switch (Opcode) {
31694 case VPOPCNTDZ128rm:
31695 case VPOPCNTDZ128rmb:
31696 case VPOPCNTDZ128rmbk:
31697 case VPOPCNTDZ128rmbkz:
31698 case VPOPCNTDZ128rmk:
31699 case VPOPCNTDZ128rmkz:
31700 case VPOPCNTDZ128rr:
31701 case VPOPCNTDZ128rrk:
31702 case VPOPCNTDZ128rrkz:
31703 case VPOPCNTDZ256rm:
31704 case VPOPCNTDZ256rmb:
31705 case VPOPCNTDZ256rmbk:
31706 case VPOPCNTDZ256rmbkz:
31707 case VPOPCNTDZ256rmk:
31708 case VPOPCNTDZ256rmkz:
31709 case VPOPCNTDZ256rr:
31710 case VPOPCNTDZ256rrk:
31711 case VPOPCNTDZ256rrkz:
31712 case VPOPCNTDZrm:
31713 case VPOPCNTDZrmb:
31714 case VPOPCNTDZrmbk:
31715 case VPOPCNTDZrmbkz:
31716 case VPOPCNTDZrmk:
31717 case VPOPCNTDZrmkz:
31718 case VPOPCNTDZrr:
31719 case VPOPCNTDZrrk:
31720 case VPOPCNTDZrrkz:
31721 return true;
31722 }
31723 return false;
31724}
31725
31726bool isSALC(unsigned Opcode) {
31727 return Opcode == SALC;
31728}
31729
31730bool isV4FNMADDSS(unsigned Opcode) {
31731 switch (Opcode) {
31732 case V4FNMADDSSrm:
31733 case V4FNMADDSSrmk:
31734 case V4FNMADDSSrmkz:
31735 return true;
31736 }
31737 return false;
31738}
31739
31740bool isXCRYPTOFB(unsigned Opcode) {
31741 return Opcode == XCRYPTOFB;
31742}
31743
31744bool isVORPD(unsigned Opcode) {
31745 switch (Opcode) {
31746 case VORPDYrm:
31747 case VORPDYrr:
31748 case VORPDZ128rm:
31749 case VORPDZ128rmb:
31750 case VORPDZ128rmbk:
31751 case VORPDZ128rmbkz:
31752 case VORPDZ128rmk:
31753 case VORPDZ128rmkz:
31754 case VORPDZ128rr:
31755 case VORPDZ128rrk:
31756 case VORPDZ128rrkz:
31757 case VORPDZ256rm:
31758 case VORPDZ256rmb:
31759 case VORPDZ256rmbk:
31760 case VORPDZ256rmbkz:
31761 case VORPDZ256rmk:
31762 case VORPDZ256rmkz:
31763 case VORPDZ256rr:
31764 case VORPDZ256rrk:
31765 case VORPDZ256rrkz:
31766 case VORPDZrm:
31767 case VORPDZrmb:
31768 case VORPDZrmbk:
31769 case VORPDZrmbkz:
31770 case VORPDZrmk:
31771 case VORPDZrmkz:
31772 case VORPDZrr:
31773 case VORPDZrrk:
31774 case VORPDZrrkz:
31775 case VORPDrm:
31776 case VORPDrr:
31777 return true;
31778 }
31779 return false;
31780}
31781
31782bool isLSL(unsigned Opcode) {
31783 switch (Opcode) {
31784 case LSL16rm:
31785 case LSL16rr:
31786 case LSL32rm:
31787 case LSL32rr:
31788 case LSL64rm:
31789 case LSL64rr:
31790 return true;
31791 }
31792 return false;
31793}
31794
31795bool isXCRYPTCFB(unsigned Opcode) {
31796 return Opcode == XCRYPTCFB;
31797}
31798
31799bool isVGETEXPSS(unsigned Opcode) {
31800 switch (Opcode) {
31801 case VGETEXPSSZm:
31802 case VGETEXPSSZmk:
31803 case VGETEXPSSZmkz:
31804 case VGETEXPSSZr:
31805 case VGETEXPSSZrb:
31806 case VGETEXPSSZrbk:
31807 case VGETEXPSSZrbkz:
31808 case VGETEXPSSZrk:
31809 case VGETEXPSSZrkz:
31810 return true;
31811 }
31812 return false;
31813}
31814
31815bool isPSLLDQ(unsigned Opcode) {
31816 return Opcode == PSLLDQri;
31817}
31818
31819bool isVPDPBUUD(unsigned Opcode) {
31820 switch (Opcode) {
31821 case VPDPBUUDYrm:
31822 case VPDPBUUDYrr:
31823 case VPDPBUUDZ128rm:
31824 case VPDPBUUDZ128rmb:
31825 case VPDPBUUDZ128rmbk:
31826 case VPDPBUUDZ128rmbkz:
31827 case VPDPBUUDZ128rmk:
31828 case VPDPBUUDZ128rmkz:
31829 case VPDPBUUDZ128rr:
31830 case VPDPBUUDZ128rrk:
31831 case VPDPBUUDZ128rrkz:
31832 case VPDPBUUDZ256rm:
31833 case VPDPBUUDZ256rmb:
31834 case VPDPBUUDZ256rmbk:
31835 case VPDPBUUDZ256rmbkz:
31836 case VPDPBUUDZ256rmk:
31837 case VPDPBUUDZ256rmkz:
31838 case VPDPBUUDZ256rr:
31839 case VPDPBUUDZ256rrk:
31840 case VPDPBUUDZ256rrkz:
31841 case VPDPBUUDZrm:
31842 case VPDPBUUDZrmb:
31843 case VPDPBUUDZrmbk:
31844 case VPDPBUUDZrmbkz:
31845 case VPDPBUUDZrmk:
31846 case VPDPBUUDZrmkz:
31847 case VPDPBUUDZrr:
31848 case VPDPBUUDZrrk:
31849 case VPDPBUUDZrrkz:
31850 case VPDPBUUDrm:
31851 case VPDPBUUDrr:
31852 return true;
31853 }
31854 return false;
31855}
31856
31857bool isVMXOFF(unsigned Opcode) {
31858 return Opcode == VMXOFF;
31859}
31860
31861bool isBLSIC(unsigned Opcode) {
31862 switch (Opcode) {
31863 case BLSIC32rm:
31864 case BLSIC32rr:
31865 case BLSIC64rm:
31866 case BLSIC64rr:
31867 return true;
31868 }
31869 return false;
31870}
31871
31872bool isMOVLHPS(unsigned Opcode) {
31873 return Opcode == MOVLHPSrr;
31874}
31875
31876bool isVMOVRSQ(unsigned Opcode) {
31877 switch (Opcode) {
31878 case VMOVRSQZ128m:
31879 case VMOVRSQZ128mk:
31880 case VMOVRSQZ128mkz:
31881 case VMOVRSQZ256m:
31882 case VMOVRSQZ256mk:
31883 case VMOVRSQZ256mkz:
31884 case VMOVRSQZm:
31885 case VMOVRSQZmk:
31886 case VMOVRSQZmkz:
31887 return true;
31888 }
31889 return false;
31890}
31891
31892bool isVFNMSUBSD(unsigned Opcode) {
31893 switch (Opcode) {
31894 case VFNMSUBSD4mr:
31895 case VFNMSUBSD4rm:
31896 case VFNMSUBSD4rr:
31897 case VFNMSUBSD4rr_REV:
31898 return true;
31899 }
31900 return false;
31901}
31902
31903bool isVCVTPH2IUBS(unsigned Opcode) {
31904 switch (Opcode) {
31905 case VCVTPH2IUBSZ128rm:
31906 case VCVTPH2IUBSZ128rmb:
31907 case VCVTPH2IUBSZ128rmbk:
31908 case VCVTPH2IUBSZ128rmbkz:
31909 case VCVTPH2IUBSZ128rmk:
31910 case VCVTPH2IUBSZ128rmkz:
31911 case VCVTPH2IUBSZ128rr:
31912 case VCVTPH2IUBSZ128rrk:
31913 case VCVTPH2IUBSZ128rrkz:
31914 case VCVTPH2IUBSZ256rm:
31915 case VCVTPH2IUBSZ256rmb:
31916 case VCVTPH2IUBSZ256rmbk:
31917 case VCVTPH2IUBSZ256rmbkz:
31918 case VCVTPH2IUBSZ256rmk:
31919 case VCVTPH2IUBSZ256rmkz:
31920 case VCVTPH2IUBSZ256rr:
31921 case VCVTPH2IUBSZ256rrk:
31922 case VCVTPH2IUBSZ256rrkz:
31923 case VCVTPH2IUBSZrm:
31924 case VCVTPH2IUBSZrmb:
31925 case VCVTPH2IUBSZrmbk:
31926 case VCVTPH2IUBSZrmbkz:
31927 case VCVTPH2IUBSZrmk:
31928 case VCVTPH2IUBSZrmkz:
31929 case VCVTPH2IUBSZrr:
31930 case VCVTPH2IUBSZrrb:
31931 case VCVTPH2IUBSZrrbk:
31932 case VCVTPH2IUBSZrrbkz:
31933 case VCVTPH2IUBSZrrk:
31934 case VCVTPH2IUBSZrrkz:
31935 return true;
31936 }
31937 return false;
31938}
31939
31940bool isVFPCLASSSH(unsigned Opcode) {
31941 switch (Opcode) {
31942 case VFPCLASSSHZmi:
31943 case VFPCLASSSHZmik:
31944 case VFPCLASSSHZri:
31945 case VFPCLASSSHZrik:
31946 return true;
31947 }
31948 return false;
31949}
31950
31951bool isVPSHLQ(unsigned Opcode) {
31952 switch (Opcode) {
31953 case VPSHLQmr:
31954 case VPSHLQrm:
31955 case VPSHLQrr:
31956 case VPSHLQrr_REV:
31957 return true;
31958 }
31959 return false;
31960}
31961
31962bool isVROUNDPS(unsigned Opcode) {
31963 switch (Opcode) {
31964 case VROUNDPSYmi:
31965 case VROUNDPSYri:
31966 case VROUNDPSmi:
31967 case VROUNDPSri:
31968 return true;
31969 }
31970 return false;
31971}
31972
31973bool isVSCATTERPF0QPS(unsigned Opcode) {
31974 return Opcode == VSCATTERPF0QPSm;
31975}
31976
31977bool isERETS(unsigned Opcode) {
31978 return Opcode == ERETS;
31979}
31980
31981bool isVPERMI2D(unsigned Opcode) {
31982 switch (Opcode) {
31983 case VPERMI2DZ128rm:
31984 case VPERMI2DZ128rmb:
31985 case VPERMI2DZ128rmbk:
31986 case VPERMI2DZ128rmbkz:
31987 case VPERMI2DZ128rmk:
31988 case VPERMI2DZ128rmkz:
31989 case VPERMI2DZ128rr:
31990 case VPERMI2DZ128rrk:
31991 case VPERMI2DZ128rrkz:
31992 case VPERMI2DZ256rm:
31993 case VPERMI2DZ256rmb:
31994 case VPERMI2DZ256rmbk:
31995 case VPERMI2DZ256rmbkz:
31996 case VPERMI2DZ256rmk:
31997 case VPERMI2DZ256rmkz:
31998 case VPERMI2DZ256rr:
31999 case VPERMI2DZ256rrk:
32000 case VPERMI2DZ256rrkz:
32001 case VPERMI2DZrm:
32002 case VPERMI2DZrmb:
32003 case VPERMI2DZrmbk:
32004 case VPERMI2DZrmbkz:
32005 case VPERMI2DZrmk:
32006 case VPERMI2DZrmkz:
32007 case VPERMI2DZrr:
32008 case VPERMI2DZrrk:
32009 case VPERMI2DZrrkz:
32010 return true;
32011 }
32012 return false;
32013}
32014
32015bool isFUCOMP(unsigned Opcode) {
32016 return Opcode == UCOM_FPr;
32017}
32018
32019bool isVCVTTPS2QQ(unsigned Opcode) {
32020 switch (Opcode) {
32021 case VCVTTPS2QQZ128rm:
32022 case VCVTTPS2QQZ128rmb:
32023 case VCVTTPS2QQZ128rmbk:
32024 case VCVTTPS2QQZ128rmbkz:
32025 case VCVTTPS2QQZ128rmk:
32026 case VCVTTPS2QQZ128rmkz:
32027 case VCVTTPS2QQZ128rr:
32028 case VCVTTPS2QQZ128rrk:
32029 case VCVTTPS2QQZ128rrkz:
32030 case VCVTTPS2QQZ256rm:
32031 case VCVTTPS2QQZ256rmb:
32032 case VCVTTPS2QQZ256rmbk:
32033 case VCVTTPS2QQZ256rmbkz:
32034 case VCVTTPS2QQZ256rmk:
32035 case VCVTTPS2QQZ256rmkz:
32036 case VCVTTPS2QQZ256rr:
32037 case VCVTTPS2QQZ256rrk:
32038 case VCVTTPS2QQZ256rrkz:
32039 case VCVTTPS2QQZrm:
32040 case VCVTTPS2QQZrmb:
32041 case VCVTTPS2QQZrmbk:
32042 case VCVTTPS2QQZrmbkz:
32043 case VCVTTPS2QQZrmk:
32044 case VCVTTPS2QQZrmkz:
32045 case VCVTTPS2QQZrr:
32046 case VCVTTPS2QQZrrb:
32047 case VCVTTPS2QQZrrbk:
32048 case VCVTTPS2QQZrrbkz:
32049 case VCVTTPS2QQZrrk:
32050 case VCVTTPS2QQZrrkz:
32051 return true;
32052 }
32053 return false;
32054}
32055
32056bool isPUSHFD(unsigned Opcode) {
32057 return Opcode == PUSHF32;
32058}
32059
32060bool isVPABSD(unsigned Opcode) {
32061 switch (Opcode) {
32062 case VPABSDYrm:
32063 case VPABSDYrr:
32064 case VPABSDZ128rm:
32065 case VPABSDZ128rmb:
32066 case VPABSDZ128rmbk:
32067 case VPABSDZ128rmbkz:
32068 case VPABSDZ128rmk:
32069 case VPABSDZ128rmkz:
32070 case VPABSDZ128rr:
32071 case VPABSDZ128rrk:
32072 case VPABSDZ128rrkz:
32073 case VPABSDZ256rm:
32074 case VPABSDZ256rmb:
32075 case VPABSDZ256rmbk:
32076 case VPABSDZ256rmbkz:
32077 case VPABSDZ256rmk:
32078 case VPABSDZ256rmkz:
32079 case VPABSDZ256rr:
32080 case VPABSDZ256rrk:
32081 case VPABSDZ256rrkz:
32082 case VPABSDZrm:
32083 case VPABSDZrmb:
32084 case VPABSDZrmbk:
32085 case VPABSDZrmbkz:
32086 case VPABSDZrmk:
32087 case VPABSDZrmkz:
32088 case VPABSDZrr:
32089 case VPABSDZrrk:
32090 case VPABSDZrrkz:
32091 case VPABSDrm:
32092 case VPABSDrr:
32093 return true;
32094 }
32095 return false;
32096}
32097
32098bool isKORB(unsigned Opcode) {
32099 return Opcode == KORBkk;
32100}
32101
32102bool isVRCP28PD(unsigned Opcode) {
32103 switch (Opcode) {
32104 case VRCP28PDZm:
32105 case VRCP28PDZmb:
32106 case VRCP28PDZmbk:
32107 case VRCP28PDZmbkz:
32108 case VRCP28PDZmk:
32109 case VRCP28PDZmkz:
32110 case VRCP28PDZr:
32111 case VRCP28PDZrb:
32112 case VRCP28PDZrbk:
32113 case VRCP28PDZrbkz:
32114 case VRCP28PDZrk:
32115 case VRCP28PDZrkz:
32116 return true;
32117 }
32118 return false;
32119}
32120
32121bool isVROUNDSS(unsigned Opcode) {
32122 switch (Opcode) {
32123 case VROUNDSSmi_Int:
32124 case VROUNDSSri_Int:
32125 return true;
32126 }
32127 return false;
32128}
32129
32130bool isVCVTSD2USI(unsigned Opcode) {
32131 switch (Opcode) {
32132 case VCVTSD2USI64Zrm_Int:
32133 case VCVTSD2USI64Zrr_Int:
32134 case VCVTSD2USI64Zrrb_Int:
32135 case VCVTSD2USIZrm_Int:
32136 case VCVTSD2USIZrr_Int:
32137 case VCVTSD2USIZrrb_Int:
32138 return true;
32139 }
32140 return false;
32141}
32142
32143bool isVPABSB(unsigned Opcode) {
32144 switch (Opcode) {
32145 case VPABSBYrm:
32146 case VPABSBYrr:
32147 case VPABSBZ128rm:
32148 case VPABSBZ128rmk:
32149 case VPABSBZ128rmkz:
32150 case VPABSBZ128rr:
32151 case VPABSBZ128rrk:
32152 case VPABSBZ128rrkz:
32153 case VPABSBZ256rm:
32154 case VPABSBZ256rmk:
32155 case VPABSBZ256rmkz:
32156 case VPABSBZ256rr:
32157 case VPABSBZ256rrk:
32158 case VPABSBZ256rrkz:
32159 case VPABSBZrm:
32160 case VPABSBZrmk:
32161 case VPABSBZrmkz:
32162 case VPABSBZrr:
32163 case VPABSBZrrk:
32164 case VPABSBZrrkz:
32165 case VPABSBrm:
32166 case VPABSBrr:
32167 return true;
32168 }
32169 return false;
32170}
32171
32172bool isPMAXUD(unsigned Opcode) {
32173 switch (Opcode) {
32174 case PMAXUDrm:
32175 case PMAXUDrr:
32176 return true;
32177 }
32178 return false;
32179}
32180
32181bool isVPERMPD(unsigned Opcode) {
32182 switch (Opcode) {
32183 case VPERMPDYmi:
32184 case VPERMPDYri:
32185 case VPERMPDZ256mbi:
32186 case VPERMPDZ256mbik:
32187 case VPERMPDZ256mbikz:
32188 case VPERMPDZ256mi:
32189 case VPERMPDZ256mik:
32190 case VPERMPDZ256mikz:
32191 case VPERMPDZ256ri:
32192 case VPERMPDZ256rik:
32193 case VPERMPDZ256rikz:
32194 case VPERMPDZ256rm:
32195 case VPERMPDZ256rmb:
32196 case VPERMPDZ256rmbk:
32197 case VPERMPDZ256rmbkz:
32198 case VPERMPDZ256rmk:
32199 case VPERMPDZ256rmkz:
32200 case VPERMPDZ256rr:
32201 case VPERMPDZ256rrk:
32202 case VPERMPDZ256rrkz:
32203 case VPERMPDZmbi:
32204 case VPERMPDZmbik:
32205 case VPERMPDZmbikz:
32206 case VPERMPDZmi:
32207 case VPERMPDZmik:
32208 case VPERMPDZmikz:
32209 case VPERMPDZri:
32210 case VPERMPDZrik:
32211 case VPERMPDZrikz:
32212 case VPERMPDZrm:
32213 case VPERMPDZrmb:
32214 case VPERMPDZrmbk:
32215 case VPERMPDZrmbkz:
32216 case VPERMPDZrmk:
32217 case VPERMPDZrmkz:
32218 case VPERMPDZrr:
32219 case VPERMPDZrrk:
32220 case VPERMPDZrrkz:
32221 return true;
32222 }
32223 return false;
32224}
32225
32226bool isVPMULHUW(unsigned Opcode) {
32227 switch (Opcode) {
32228 case VPMULHUWYrm:
32229 case VPMULHUWYrr:
32230 case VPMULHUWZ128rm:
32231 case VPMULHUWZ128rmk:
32232 case VPMULHUWZ128rmkz:
32233 case VPMULHUWZ128rr:
32234 case VPMULHUWZ128rrk:
32235 case VPMULHUWZ128rrkz:
32236 case VPMULHUWZ256rm:
32237 case VPMULHUWZ256rmk:
32238 case VPMULHUWZ256rmkz:
32239 case VPMULHUWZ256rr:
32240 case VPMULHUWZ256rrk:
32241 case VPMULHUWZ256rrkz:
32242 case VPMULHUWZrm:
32243 case VPMULHUWZrmk:
32244 case VPMULHUWZrmkz:
32245 case VPMULHUWZrr:
32246 case VPMULHUWZrrk:
32247 case VPMULHUWZrrkz:
32248 case VPMULHUWrm:
32249 case VPMULHUWrr:
32250 return true;
32251 }
32252 return false;
32253}
32254
32255bool isFCHS(unsigned Opcode) {
32256 return Opcode == CHS_F;
32257}
32258
32259bool isVPBLENDMB(unsigned Opcode) {
32260 switch (Opcode) {
32261 case VPBLENDMBZ128rm:
32262 case VPBLENDMBZ128rmk:
32263 case VPBLENDMBZ128rmkz:
32264 case VPBLENDMBZ128rr:
32265 case VPBLENDMBZ128rrk:
32266 case VPBLENDMBZ128rrkz:
32267 case VPBLENDMBZ256rm:
32268 case VPBLENDMBZ256rmk:
32269 case VPBLENDMBZ256rmkz:
32270 case VPBLENDMBZ256rr:
32271 case VPBLENDMBZ256rrk:
32272 case VPBLENDMBZ256rrkz:
32273 case VPBLENDMBZrm:
32274 case VPBLENDMBZrmk:
32275 case VPBLENDMBZrmkz:
32276 case VPBLENDMBZrr:
32277 case VPBLENDMBZrrk:
32278 case VPBLENDMBZrrkz:
32279 return true;
32280 }
32281 return false;
32282}
32283
32284bool isVGETMANTSS(unsigned Opcode) {
32285 switch (Opcode) {
32286 case VGETMANTSSZrmi:
32287 case VGETMANTSSZrmik:
32288 case VGETMANTSSZrmikz:
32289 case VGETMANTSSZrri:
32290 case VGETMANTSSZrrib:
32291 case VGETMANTSSZrribk:
32292 case VGETMANTSSZrribkz:
32293 case VGETMANTSSZrrik:
32294 case VGETMANTSSZrrikz:
32295 return true;
32296 }
32297 return false;
32298}
32299
32300bool isVPSLLW(unsigned Opcode) {
32301 switch (Opcode) {
32302 case VPSLLWYri:
32303 case VPSLLWYrm:
32304 case VPSLLWYrr:
32305 case VPSLLWZ128mi:
32306 case VPSLLWZ128mik:
32307 case VPSLLWZ128mikz:
32308 case VPSLLWZ128ri:
32309 case VPSLLWZ128rik:
32310 case VPSLLWZ128rikz:
32311 case VPSLLWZ128rm:
32312 case VPSLLWZ128rmk:
32313 case VPSLLWZ128rmkz:
32314 case VPSLLWZ128rr:
32315 case VPSLLWZ128rrk:
32316 case VPSLLWZ128rrkz:
32317 case VPSLLWZ256mi:
32318 case VPSLLWZ256mik:
32319 case VPSLLWZ256mikz:
32320 case VPSLLWZ256ri:
32321 case VPSLLWZ256rik:
32322 case VPSLLWZ256rikz:
32323 case VPSLLWZ256rm:
32324 case VPSLLWZ256rmk:
32325 case VPSLLWZ256rmkz:
32326 case VPSLLWZ256rr:
32327 case VPSLLWZ256rrk:
32328 case VPSLLWZ256rrkz:
32329 case VPSLLWZmi:
32330 case VPSLLWZmik:
32331 case VPSLLWZmikz:
32332 case VPSLLWZri:
32333 case VPSLLWZrik:
32334 case VPSLLWZrikz:
32335 case VPSLLWZrm:
32336 case VPSLLWZrmk:
32337 case VPSLLWZrmkz:
32338 case VPSLLWZrr:
32339 case VPSLLWZrrk:
32340 case VPSLLWZrrkz:
32341 case VPSLLWri:
32342 case VPSLLWrm:
32343 case VPSLLWrr:
32344 return true;
32345 }
32346 return false;
32347}
32348
32349bool isVDIVPD(unsigned Opcode) {
32350 switch (Opcode) {
32351 case VDIVPDYrm:
32352 case VDIVPDYrr:
32353 case VDIVPDZ128rm:
32354 case VDIVPDZ128rmb:
32355 case VDIVPDZ128rmbk:
32356 case VDIVPDZ128rmbkz:
32357 case VDIVPDZ128rmk:
32358 case VDIVPDZ128rmkz:
32359 case VDIVPDZ128rr:
32360 case VDIVPDZ128rrk:
32361 case VDIVPDZ128rrkz:
32362 case VDIVPDZ256rm:
32363 case VDIVPDZ256rmb:
32364 case VDIVPDZ256rmbk:
32365 case VDIVPDZ256rmbkz:
32366 case VDIVPDZ256rmk:
32367 case VDIVPDZ256rmkz:
32368 case VDIVPDZ256rr:
32369 case VDIVPDZ256rrk:
32370 case VDIVPDZ256rrkz:
32371 case VDIVPDZrm:
32372 case VDIVPDZrmb:
32373 case VDIVPDZrmbk:
32374 case VDIVPDZrmbkz:
32375 case VDIVPDZrmk:
32376 case VDIVPDZrmkz:
32377 case VDIVPDZrr:
32378 case VDIVPDZrrb:
32379 case VDIVPDZrrbk:
32380 case VDIVPDZrrbkz:
32381 case VDIVPDZrrk:
32382 case VDIVPDZrrkz:
32383 case VDIVPDrm:
32384 case VDIVPDrr:
32385 return true;
32386 }
32387 return false;
32388}
32389
32390bool isBLCMSK(unsigned Opcode) {
32391 switch (Opcode) {
32392 case BLCMSK32rm:
32393 case BLCMSK32rr:
32394 case BLCMSK64rm:
32395 case BLCMSK64rr:
32396 return true;
32397 }
32398 return false;
32399}
32400
32401bool isFDIV(unsigned Opcode) {
32402 switch (Opcode) {
32403 case DIV_F32m:
32404 case DIV_F64m:
32405 case DIV_FST0r:
32406 case DIV_FrST0:
32407 return true;
32408 }
32409 return false;
32410}
32411
32412bool isRSQRTSS(unsigned Opcode) {
32413 switch (Opcode) {
32414 case RSQRTSSm_Int:
32415 case RSQRTSSr_Int:
32416 return true;
32417 }
32418 return false;
32419}
32420
32421bool isPOR(unsigned Opcode) {
32422 switch (Opcode) {
32423 case MMX_PORrm:
32424 case MMX_PORrr:
32425 case PORrm:
32426 case PORrr:
32427 return true;
32428 }
32429 return false;
32430}
32431
32432bool isVMOVDQA32(unsigned Opcode) {
32433 switch (Opcode) {
32434 case VMOVDQA32Z128mr:
32435 case VMOVDQA32Z128mrk:
32436 case VMOVDQA32Z128rm:
32437 case VMOVDQA32Z128rmk:
32438 case VMOVDQA32Z128rmkz:
32439 case VMOVDQA32Z128rr:
32440 case VMOVDQA32Z128rr_REV:
32441 case VMOVDQA32Z128rrk:
32442 case VMOVDQA32Z128rrk_REV:
32443 case VMOVDQA32Z128rrkz:
32444 case VMOVDQA32Z128rrkz_REV:
32445 case VMOVDQA32Z256mr:
32446 case VMOVDQA32Z256mrk:
32447 case VMOVDQA32Z256rm:
32448 case VMOVDQA32Z256rmk:
32449 case VMOVDQA32Z256rmkz:
32450 case VMOVDQA32Z256rr:
32451 case VMOVDQA32Z256rr_REV:
32452 case VMOVDQA32Z256rrk:
32453 case VMOVDQA32Z256rrk_REV:
32454 case VMOVDQA32Z256rrkz:
32455 case VMOVDQA32Z256rrkz_REV:
32456 case VMOVDQA32Zmr:
32457 case VMOVDQA32Zmrk:
32458 case VMOVDQA32Zrm:
32459 case VMOVDQA32Zrmk:
32460 case VMOVDQA32Zrmkz:
32461 case VMOVDQA32Zrr:
32462 case VMOVDQA32Zrr_REV:
32463 case VMOVDQA32Zrrk:
32464 case VMOVDQA32Zrrk_REV:
32465 case VMOVDQA32Zrrkz:
32466 case VMOVDQA32Zrrkz_REV:
32467 return true;
32468 }
32469 return false;
32470}
32471
32472bool isVPHADDUWQ(unsigned Opcode) {
32473 switch (Opcode) {
32474 case VPHADDUWQrm:
32475 case VPHADDUWQrr:
32476 return true;
32477 }
32478 return false;
32479}
32480
32481bool isPSRAD(unsigned Opcode) {
32482 switch (Opcode) {
32483 case MMX_PSRADri:
32484 case MMX_PSRADrm:
32485 case MMX_PSRADrr:
32486 case PSRADri:
32487 case PSRADrm:
32488 case PSRADrr:
32489 return true;
32490 }
32491 return false;
32492}
32493
32494bool isPREFETCHW(unsigned Opcode) {
32495 return Opcode == PREFETCHW;
32496}
32497
32498bool isFIDIVR(unsigned Opcode) {
32499 switch (Opcode) {
32500 case DIVR_FI16m:
32501 case DIVR_FI32m:
32502 return true;
32503 }
32504 return false;
32505}
32506
32507bool isMOVHPS(unsigned Opcode) {
32508 switch (Opcode) {
32509 case MOVHPSmr:
32510 case MOVHPSrm:
32511 return true;
32512 }
32513 return false;
32514}
32515
32516bool isVFNMSUB231PH(unsigned Opcode) {
32517 switch (Opcode) {
32518 case VFNMSUB231PHZ128m:
32519 case VFNMSUB231PHZ128mb:
32520 case VFNMSUB231PHZ128mbk:
32521 case VFNMSUB231PHZ128mbkz:
32522 case VFNMSUB231PHZ128mk:
32523 case VFNMSUB231PHZ128mkz:
32524 case VFNMSUB231PHZ128r:
32525 case VFNMSUB231PHZ128rk:
32526 case VFNMSUB231PHZ128rkz:
32527 case VFNMSUB231PHZ256m:
32528 case VFNMSUB231PHZ256mb:
32529 case VFNMSUB231PHZ256mbk:
32530 case VFNMSUB231PHZ256mbkz:
32531 case VFNMSUB231PHZ256mk:
32532 case VFNMSUB231PHZ256mkz:
32533 case VFNMSUB231PHZ256r:
32534 case VFNMSUB231PHZ256rk:
32535 case VFNMSUB231PHZ256rkz:
32536 case VFNMSUB231PHZm:
32537 case VFNMSUB231PHZmb:
32538 case VFNMSUB231PHZmbk:
32539 case VFNMSUB231PHZmbkz:
32540 case VFNMSUB231PHZmk:
32541 case VFNMSUB231PHZmkz:
32542 case VFNMSUB231PHZr:
32543 case VFNMSUB231PHZrb:
32544 case VFNMSUB231PHZrbk:
32545 case VFNMSUB231PHZrbkz:
32546 case VFNMSUB231PHZrk:
32547 case VFNMSUB231PHZrkz:
32548 return true;
32549 }
32550 return false;
32551}
32552
32553bool isUNPCKLPS(unsigned Opcode) {
32554 switch (Opcode) {
32555 case UNPCKLPSrm:
32556 case UNPCKLPSrr:
32557 return true;
32558 }
32559 return false;
32560}
32561
32562bool isVPSIGNB(unsigned Opcode) {
32563 switch (Opcode) {
32564 case VPSIGNBYrm:
32565 case VPSIGNBYrr:
32566 case VPSIGNBrm:
32567 case VPSIGNBrr:
32568 return true;
32569 }
32570 return false;
32571}
32572
32573bool isSAVEPREVSSP(unsigned Opcode) {
32574 return Opcode == SAVEPREVSSP;
32575}
32576
32577bool isVSCALEFSD(unsigned Opcode) {
32578 switch (Opcode) {
32579 case VSCALEFSDZrm:
32580 case VSCALEFSDZrmk:
32581 case VSCALEFSDZrmkz:
32582 case VSCALEFSDZrr:
32583 case VSCALEFSDZrrb_Int:
32584 case VSCALEFSDZrrbk_Int:
32585 case VSCALEFSDZrrbkz_Int:
32586 case VSCALEFSDZrrk:
32587 case VSCALEFSDZrrkz:
32588 return true;
32589 }
32590 return false;
32591}
32592
32593bool isFSIN(unsigned Opcode) {
32594 return Opcode == FSIN;
32595}
32596
32597bool isSCASQ(unsigned Opcode) {
32598 return Opcode == SCASQ;
32599}
32600
32601bool isVCVTTPD2QQS(unsigned Opcode) {
32602 switch (Opcode) {
32603 case VCVTTPD2QQSZ128rm:
32604 case VCVTTPD2QQSZ128rmb:
32605 case VCVTTPD2QQSZ128rmbk:
32606 case VCVTTPD2QQSZ128rmbkz:
32607 case VCVTTPD2QQSZ128rmk:
32608 case VCVTTPD2QQSZ128rmkz:
32609 case VCVTTPD2QQSZ128rr:
32610 case VCVTTPD2QQSZ128rrk:
32611 case VCVTTPD2QQSZ128rrkz:
32612 case VCVTTPD2QQSZ256rm:
32613 case VCVTTPD2QQSZ256rmb:
32614 case VCVTTPD2QQSZ256rmbk:
32615 case VCVTTPD2QQSZ256rmbkz:
32616 case VCVTTPD2QQSZ256rmk:
32617 case VCVTTPD2QQSZ256rmkz:
32618 case VCVTTPD2QQSZ256rr:
32619 case VCVTTPD2QQSZ256rrb:
32620 case VCVTTPD2QQSZ256rrbk:
32621 case VCVTTPD2QQSZ256rrbkz:
32622 case VCVTTPD2QQSZ256rrk:
32623 case VCVTTPD2QQSZ256rrkz:
32624 case VCVTTPD2QQSZrm:
32625 case VCVTTPD2QQSZrmb:
32626 case VCVTTPD2QQSZrmbk:
32627 case VCVTTPD2QQSZrmbkz:
32628 case VCVTTPD2QQSZrmk:
32629 case VCVTTPD2QQSZrmkz:
32630 case VCVTTPD2QQSZrr:
32631 case VCVTTPD2QQSZrrb:
32632 case VCVTTPD2QQSZrrbk:
32633 case VCVTTPD2QQSZrrbkz:
32634 case VCVTTPD2QQSZrrk:
32635 case VCVTTPD2QQSZrrkz:
32636 return true;
32637 }
32638 return false;
32639}
32640
32641bool isPCMPGTW(unsigned Opcode) {
32642 switch (Opcode) {
32643 case MMX_PCMPGTWrm:
32644 case MMX_PCMPGTWrr:
32645 case PCMPGTWrm:
32646 case PCMPGTWrr:
32647 return true;
32648 }
32649 return false;
32650}
32651
32652bool isMULX(unsigned Opcode) {
32653 switch (Opcode) {
32654 case MULX32rm:
32655 case MULX32rm_EVEX:
32656 case MULX32rr:
32657 case MULX32rr_EVEX:
32658 case MULX64rm:
32659 case MULX64rm_EVEX:
32660 case MULX64rr:
32661 case MULX64rr_EVEX:
32662 return true;
32663 }
32664 return false;
32665}
32666
32667bool isVPMAXUW(unsigned Opcode) {
32668 switch (Opcode) {
32669 case VPMAXUWYrm:
32670 case VPMAXUWYrr:
32671 case VPMAXUWZ128rm:
32672 case VPMAXUWZ128rmk:
32673 case VPMAXUWZ128rmkz:
32674 case VPMAXUWZ128rr:
32675 case VPMAXUWZ128rrk:
32676 case VPMAXUWZ128rrkz:
32677 case VPMAXUWZ256rm:
32678 case VPMAXUWZ256rmk:
32679 case VPMAXUWZ256rmkz:
32680 case VPMAXUWZ256rr:
32681 case VPMAXUWZ256rrk:
32682 case VPMAXUWZ256rrkz:
32683 case VPMAXUWZrm:
32684 case VPMAXUWZrmk:
32685 case VPMAXUWZrmkz:
32686 case VPMAXUWZrr:
32687 case VPMAXUWZrrk:
32688 case VPMAXUWZrrkz:
32689 case VPMAXUWrm:
32690 case VPMAXUWrr:
32691 return true;
32692 }
32693 return false;
32694}
32695
32696bool isPAUSE(unsigned Opcode) {
32697 return Opcode == PAUSE;
32698}
32699
32700bool isMOVQ2DQ(unsigned Opcode) {
32701 return Opcode == MMX_MOVQ2DQrr;
32702}
32703
32704bool isVPABSW(unsigned Opcode) {
32705 switch (Opcode) {
32706 case VPABSWYrm:
32707 case VPABSWYrr:
32708 case VPABSWZ128rm:
32709 case VPABSWZ128rmk:
32710 case VPABSWZ128rmkz:
32711 case VPABSWZ128rr:
32712 case VPABSWZ128rrk:
32713 case VPABSWZ128rrkz:
32714 case VPABSWZ256rm:
32715 case VPABSWZ256rmk:
32716 case VPABSWZ256rmkz:
32717 case VPABSWZ256rr:
32718 case VPABSWZ256rrk:
32719 case VPABSWZ256rrkz:
32720 case VPABSWZrm:
32721 case VPABSWZrmk:
32722 case VPABSWZrmkz:
32723 case VPABSWZrr:
32724 case VPABSWZrrk:
32725 case VPABSWZrrkz:
32726 case VPABSWrm:
32727 case VPABSWrr:
32728 return true;
32729 }
32730 return false;
32731}
32732
32733bool isVBITREVB(unsigned Opcode) {
32734 switch (Opcode) {
32735 case VPBITREVBZ128rm:
32736 case VPBITREVBZ128rmk:
32737 case VPBITREVBZ128rmkz:
32738 case VPBITREVBZ128rr:
32739 case VPBITREVBZ128rrk:
32740 case VPBITREVBZ128rrkz:
32741 case VPBITREVBZ256rm:
32742 case VPBITREVBZ256rmk:
32743 case VPBITREVBZ256rmkz:
32744 case VPBITREVBZ256rr:
32745 case VPBITREVBZ256rrk:
32746 case VPBITREVBZ256rrkz:
32747 case VPBITREVBZrm:
32748 case VPBITREVBZrmk:
32749 case VPBITREVBZrmkz:
32750 case VPBITREVBZrr:
32751 case VPBITREVBZrrk:
32752 case VPBITREVBZrrkz:
32753 return true;
32754 }
32755 return false;
32756}
32757
32758bool isVPCOMPRESSD(unsigned Opcode) {
32759 switch (Opcode) {
32760 case VPCOMPRESSDZ128mr:
32761 case VPCOMPRESSDZ128mrk:
32762 case VPCOMPRESSDZ128rr:
32763 case VPCOMPRESSDZ128rrk:
32764 case VPCOMPRESSDZ128rrkz:
32765 case VPCOMPRESSDZ256mr:
32766 case VPCOMPRESSDZ256mrk:
32767 case VPCOMPRESSDZ256rr:
32768 case VPCOMPRESSDZ256rrk:
32769 case VPCOMPRESSDZ256rrkz:
32770 case VPCOMPRESSDZmr:
32771 case VPCOMPRESSDZmrk:
32772 case VPCOMPRESSDZrr:
32773 case VPCOMPRESSDZrrk:
32774 case VPCOMPRESSDZrrkz:
32775 return true;
32776 }
32777 return false;
32778}
32779
32780bool isVPSUBQ(unsigned Opcode) {
32781 switch (Opcode) {
32782 case VPSUBQYrm:
32783 case VPSUBQYrr:
32784 case VPSUBQZ128rm:
32785 case VPSUBQZ128rmb:
32786 case VPSUBQZ128rmbk:
32787 case VPSUBQZ128rmbkz:
32788 case VPSUBQZ128rmk:
32789 case VPSUBQZ128rmkz:
32790 case VPSUBQZ128rr:
32791 case VPSUBQZ128rrk:
32792 case VPSUBQZ128rrkz:
32793 case VPSUBQZ256rm:
32794 case VPSUBQZ256rmb:
32795 case VPSUBQZ256rmbk:
32796 case VPSUBQZ256rmbkz:
32797 case VPSUBQZ256rmk:
32798 case VPSUBQZ256rmkz:
32799 case VPSUBQZ256rr:
32800 case VPSUBQZ256rrk:
32801 case VPSUBQZ256rrkz:
32802 case VPSUBQZrm:
32803 case VPSUBQZrmb:
32804 case VPSUBQZrmbk:
32805 case VPSUBQZrmbkz:
32806 case VPSUBQZrmk:
32807 case VPSUBQZrmkz:
32808 case VPSUBQZrr:
32809 case VPSUBQZrrk:
32810 case VPSUBQZrrkz:
32811 case VPSUBQrm:
32812 case VPSUBQrr:
32813 return true;
32814 }
32815 return false;
32816}
32817
32818bool isVPMOVUSQW(unsigned Opcode) {
32819 switch (Opcode) {
32820 case VPMOVUSQWZ128mr:
32821 case VPMOVUSQWZ128mrk:
32822 case VPMOVUSQWZ128rr:
32823 case VPMOVUSQWZ128rrk:
32824 case VPMOVUSQWZ128rrkz:
32825 case VPMOVUSQWZ256mr:
32826 case VPMOVUSQWZ256mrk:
32827 case VPMOVUSQWZ256rr:
32828 case VPMOVUSQWZ256rrk:
32829 case VPMOVUSQWZ256rrkz:
32830 case VPMOVUSQWZmr:
32831 case VPMOVUSQWZmrk:
32832 case VPMOVUSQWZrr:
32833 case VPMOVUSQWZrrk:
32834 case VPMOVUSQWZrrkz:
32835 return true;
32836 }
32837 return false;
32838}
32839
32840bool isBLENDVPD(unsigned Opcode) {
32841 switch (Opcode) {
32842 case BLENDVPDrm0:
32843 case BLENDVPDrr0:
32844 return true;
32845 }
32846 return false;
32847}
32848
32849bool isVFNMADD132BF16(unsigned Opcode) {
32850 switch (Opcode) {
32851 case VFNMADD132BF16Z128m:
32852 case VFNMADD132BF16Z128mb:
32853 case VFNMADD132BF16Z128mbk:
32854 case VFNMADD132BF16Z128mbkz:
32855 case VFNMADD132BF16Z128mk:
32856 case VFNMADD132BF16Z128mkz:
32857 case VFNMADD132BF16Z128r:
32858 case VFNMADD132BF16Z128rk:
32859 case VFNMADD132BF16Z128rkz:
32860 case VFNMADD132BF16Z256m:
32861 case VFNMADD132BF16Z256mb:
32862 case VFNMADD132BF16Z256mbk:
32863 case VFNMADD132BF16Z256mbkz:
32864 case VFNMADD132BF16Z256mk:
32865 case VFNMADD132BF16Z256mkz:
32866 case VFNMADD132BF16Z256r:
32867 case VFNMADD132BF16Z256rk:
32868 case VFNMADD132BF16Z256rkz:
32869 case VFNMADD132BF16Zm:
32870 case VFNMADD132BF16Zmb:
32871 case VFNMADD132BF16Zmbk:
32872 case VFNMADD132BF16Zmbkz:
32873 case VFNMADD132BF16Zmk:
32874 case VFNMADD132BF16Zmkz:
32875 case VFNMADD132BF16Zr:
32876 case VFNMADD132BF16Zrk:
32877 case VFNMADD132BF16Zrkz:
32878 return true;
32879 }
32880 return false;
32881}
32882
32883bool isVPMOVQB(unsigned Opcode) {
32884 switch (Opcode) {
32885 case VPMOVQBZ128mr:
32886 case VPMOVQBZ128mrk:
32887 case VPMOVQBZ128rr:
32888 case VPMOVQBZ128rrk:
32889 case VPMOVQBZ128rrkz:
32890 case VPMOVQBZ256mr:
32891 case VPMOVQBZ256mrk:
32892 case VPMOVQBZ256rr:
32893 case VPMOVQBZ256rrk:
32894 case VPMOVQBZ256rrkz:
32895 case VPMOVQBZmr:
32896 case VPMOVQBZmrk:
32897 case VPMOVQBZrr:
32898 case VPMOVQBZrrk:
32899 case VPMOVQBZrrkz:
32900 return true;
32901 }
32902 return false;
32903}
32904
32905bool isVBLENDVPS(unsigned Opcode) {
32906 switch (Opcode) {
32907 case VBLENDVPSYrmr:
32908 case VBLENDVPSYrrr:
32909 case VBLENDVPSrmr:
32910 case VBLENDVPSrrr:
32911 return true;
32912 }
32913 return false;
32914}
32915
32916bool isKSHIFTLQ(unsigned Opcode) {
32917 return Opcode == KSHIFTLQki;
32918}
32919
32920bool isPMOVSXWD(unsigned Opcode) {
32921 switch (Opcode) {
32922 case PMOVSXWDrm:
32923 case PMOVSXWDrr:
32924 return true;
32925 }
32926 return false;
32927}
32928
32929bool isPHSUBSW(unsigned Opcode) {
32930 switch (Opcode) {
32931 case MMX_PHSUBSWrm:
32932 case MMX_PHSUBSWrr:
32933 case PHSUBSWrm:
32934 case PHSUBSWrr:
32935 return true;
32936 }
32937 return false;
32938}
32939
32940bool isPSRLQ(unsigned Opcode) {
32941 switch (Opcode) {
32942 case MMX_PSRLQri:
32943 case MMX_PSRLQrm:
32944 case MMX_PSRLQrr:
32945 case PSRLQri:
32946 case PSRLQrm:
32947 case PSRLQrr:
32948 return true;
32949 }
32950 return false;
32951}
32952
32953bool isVCVTPH2DQ(unsigned Opcode) {
32954 switch (Opcode) {
32955 case VCVTPH2DQZ128rm:
32956 case VCVTPH2DQZ128rmb:
32957 case VCVTPH2DQZ128rmbk:
32958 case VCVTPH2DQZ128rmbkz:
32959 case VCVTPH2DQZ128rmk:
32960 case VCVTPH2DQZ128rmkz:
32961 case VCVTPH2DQZ128rr:
32962 case VCVTPH2DQZ128rrk:
32963 case VCVTPH2DQZ128rrkz:
32964 case VCVTPH2DQZ256rm:
32965 case VCVTPH2DQZ256rmb:
32966 case VCVTPH2DQZ256rmbk:
32967 case VCVTPH2DQZ256rmbkz:
32968 case VCVTPH2DQZ256rmk:
32969 case VCVTPH2DQZ256rmkz:
32970 case VCVTPH2DQZ256rr:
32971 case VCVTPH2DQZ256rrk:
32972 case VCVTPH2DQZ256rrkz:
32973 case VCVTPH2DQZrm:
32974 case VCVTPH2DQZrmb:
32975 case VCVTPH2DQZrmbk:
32976 case VCVTPH2DQZrmbkz:
32977 case VCVTPH2DQZrmk:
32978 case VCVTPH2DQZrmkz:
32979 case VCVTPH2DQZrr:
32980 case VCVTPH2DQZrrb:
32981 case VCVTPH2DQZrrbk:
32982 case VCVTPH2DQZrrbkz:
32983 case VCVTPH2DQZrrk:
32984 case VCVTPH2DQZrrkz:
32985 return true;
32986 }
32987 return false;
32988}
32989
32990bool isPCMPESTRIQ(unsigned Opcode) {
32991 switch (Opcode) {
32992 case PCMPESTRIQrmi:
32993 case PCMPESTRIQrri:
32994 return true;
32995 }
32996 return false;
32997}
32998
32999bool isFISUB(unsigned Opcode) {
33000 switch (Opcode) {
33001 case SUB_FI16m:
33002 case SUB_FI32m:
33003 return true;
33004 }
33005 return false;
33006}
33007
33008bool isVCVTPS2UDQ(unsigned Opcode) {
33009 switch (Opcode) {
33010 case VCVTPS2UDQZ128rm:
33011 case VCVTPS2UDQZ128rmb:
33012 case VCVTPS2UDQZ128rmbk:
33013 case VCVTPS2UDQZ128rmbkz:
33014 case VCVTPS2UDQZ128rmk:
33015 case VCVTPS2UDQZ128rmkz:
33016 case VCVTPS2UDQZ128rr:
33017 case VCVTPS2UDQZ128rrk:
33018 case VCVTPS2UDQZ128rrkz:
33019 case VCVTPS2UDQZ256rm:
33020 case VCVTPS2UDQZ256rmb:
33021 case VCVTPS2UDQZ256rmbk:
33022 case VCVTPS2UDQZ256rmbkz:
33023 case VCVTPS2UDQZ256rmk:
33024 case VCVTPS2UDQZ256rmkz:
33025 case VCVTPS2UDQZ256rr:
33026 case VCVTPS2UDQZ256rrk:
33027 case VCVTPS2UDQZ256rrkz:
33028 case VCVTPS2UDQZrm:
33029 case VCVTPS2UDQZrmb:
33030 case VCVTPS2UDQZrmbk:
33031 case VCVTPS2UDQZrmbkz:
33032 case VCVTPS2UDQZrmk:
33033 case VCVTPS2UDQZrmkz:
33034 case VCVTPS2UDQZrr:
33035 case VCVTPS2UDQZrrb:
33036 case VCVTPS2UDQZrrbk:
33037 case VCVTPS2UDQZrrbkz:
33038 case VCVTPS2UDQZrrk:
33039 case VCVTPS2UDQZrrkz:
33040 return true;
33041 }
33042 return false;
33043}
33044
33045bool isVMOVDDUP(unsigned Opcode) {
33046 switch (Opcode) {
33047 case VMOVDDUPYrm:
33048 case VMOVDDUPYrr:
33049 case VMOVDDUPZ128rm:
33050 case VMOVDDUPZ128rmk:
33051 case VMOVDDUPZ128rmkz:
33052 case VMOVDDUPZ128rr:
33053 case VMOVDDUPZ128rrk:
33054 case VMOVDDUPZ128rrkz:
33055 case VMOVDDUPZ256rm:
33056 case VMOVDDUPZ256rmk:
33057 case VMOVDDUPZ256rmkz:
33058 case VMOVDDUPZ256rr:
33059 case VMOVDDUPZ256rrk:
33060 case VMOVDDUPZ256rrkz:
33061 case VMOVDDUPZrm:
33062 case VMOVDDUPZrmk:
33063 case VMOVDDUPZrmkz:
33064 case VMOVDDUPZrr:
33065 case VMOVDDUPZrrk:
33066 case VMOVDDUPZrrkz:
33067 case VMOVDDUPrm:
33068 case VMOVDDUPrr:
33069 return true;
33070 }
33071 return false;
33072}
33073
33074bool isPCMPEQD(unsigned Opcode) {
33075 switch (Opcode) {
33076 case MMX_PCMPEQDrm:
33077 case MMX_PCMPEQDrr:
33078 case PCMPEQDrm:
33079 case PCMPEQDrr:
33080 return true;
33081 }
33082 return false;
33083}
33084
33085bool isVRSQRT28SD(unsigned Opcode) {
33086 switch (Opcode) {
33087 case VRSQRT28SDZm:
33088 case VRSQRT28SDZmk:
33089 case VRSQRT28SDZmkz:
33090 case VRSQRT28SDZr:
33091 case VRSQRT28SDZrb:
33092 case VRSQRT28SDZrbk:
33093 case VRSQRT28SDZrbkz:
33094 case VRSQRT28SDZrk:
33095 case VRSQRT28SDZrkz:
33096 return true;
33097 }
33098 return false;
33099}
33100
33101bool isTDPHBF8PS(unsigned Opcode) {
33102 return Opcode == TDPHBF8PS;
33103}
33104
33105bool isVPOPCNTQ(unsigned Opcode) {
33106 switch (Opcode) {
33107 case VPOPCNTQZ128rm:
33108 case VPOPCNTQZ128rmb:
33109 case VPOPCNTQZ128rmbk:
33110 case VPOPCNTQZ128rmbkz:
33111 case VPOPCNTQZ128rmk:
33112 case VPOPCNTQZ128rmkz:
33113 case VPOPCNTQZ128rr:
33114 case VPOPCNTQZ128rrk:
33115 case VPOPCNTQZ128rrkz:
33116 case VPOPCNTQZ256rm:
33117 case VPOPCNTQZ256rmb:
33118 case VPOPCNTQZ256rmbk:
33119 case VPOPCNTQZ256rmbkz:
33120 case VPOPCNTQZ256rmk:
33121 case VPOPCNTQZ256rmkz:
33122 case VPOPCNTQZ256rr:
33123 case VPOPCNTQZ256rrk:
33124 case VPOPCNTQZ256rrkz:
33125 case VPOPCNTQZrm:
33126 case VPOPCNTQZrmb:
33127 case VPOPCNTQZrmbk:
33128 case VPOPCNTQZrmbkz:
33129 case VPOPCNTQZrmk:
33130 case VPOPCNTQZrmkz:
33131 case VPOPCNTQZrr:
33132 case VPOPCNTQZrrk:
33133 case VPOPCNTQZrrkz:
33134 return true;
33135 }
33136 return false;
33137}
33138
33139bool isLODSW(unsigned Opcode) {
33140 return Opcode == LODSW;
33141}
33142
33143bool isKSHIFTRB(unsigned Opcode) {
33144 return Opcode == KSHIFTRBki;
33145}
33146
33147bool isVFNMADDPS(unsigned Opcode) {
33148 switch (Opcode) {
33149 case VFNMADDPS4Ymr:
33150 case VFNMADDPS4Yrm:
33151 case VFNMADDPS4Yrr:
33152 case VFNMADDPS4Yrr_REV:
33153 case VFNMADDPS4mr:
33154 case VFNMADDPS4rm:
33155 case VFNMADDPS4rr:
33156 case VFNMADDPS4rr_REV:
33157 return true;
33158 }
33159 return false;
33160}
33161
33162bool isCCMPCC(unsigned Opcode) {
33163 switch (Opcode) {
33164 case CCMP16mi:
33165 case CCMP16mi8:
33166 case CCMP16mr:
33167 case CCMP16ri:
33168 case CCMP16ri8:
33169 case CCMP16rm:
33170 case CCMP16rr:
33171 case CCMP16rr_REV:
33172 case CCMP32mi:
33173 case CCMP32mi8:
33174 case CCMP32mr:
33175 case CCMP32ri:
33176 case CCMP32ri8:
33177 case CCMP32rm:
33178 case CCMP32rr:
33179 case CCMP32rr_REV:
33180 case CCMP64mi32:
33181 case CCMP64mi8:
33182 case CCMP64mr:
33183 case CCMP64ri32:
33184 case CCMP64ri8:
33185 case CCMP64rm:
33186 case CCMP64rr:
33187 case CCMP64rr_REV:
33188 case CCMP8mi:
33189 case CCMP8mr:
33190 case CCMP8ri:
33191 case CCMP8rm:
33192 case CCMP8rr:
33193 case CCMP8rr_REV:
33194 return true;
33195 }
33196 return false;
33197}
33198
33199bool isFXRSTOR64(unsigned Opcode) {
33200 return Opcode == FXRSTOR64;
33201}
33202
33203bool isVFMSUBADD213PD(unsigned Opcode) {
33204 switch (Opcode) {
33205 case VFMSUBADD213PDYm:
33206 case VFMSUBADD213PDYr:
33207 case VFMSUBADD213PDZ128m:
33208 case VFMSUBADD213PDZ128mb:
33209 case VFMSUBADD213PDZ128mbk:
33210 case VFMSUBADD213PDZ128mbkz:
33211 case VFMSUBADD213PDZ128mk:
33212 case VFMSUBADD213PDZ128mkz:
33213 case VFMSUBADD213PDZ128r:
33214 case VFMSUBADD213PDZ128rk:
33215 case VFMSUBADD213PDZ128rkz:
33216 case VFMSUBADD213PDZ256m:
33217 case VFMSUBADD213PDZ256mb:
33218 case VFMSUBADD213PDZ256mbk:
33219 case VFMSUBADD213PDZ256mbkz:
33220 case VFMSUBADD213PDZ256mk:
33221 case VFMSUBADD213PDZ256mkz:
33222 case VFMSUBADD213PDZ256r:
33223 case VFMSUBADD213PDZ256rk:
33224 case VFMSUBADD213PDZ256rkz:
33225 case VFMSUBADD213PDZm:
33226 case VFMSUBADD213PDZmb:
33227 case VFMSUBADD213PDZmbk:
33228 case VFMSUBADD213PDZmbkz:
33229 case VFMSUBADD213PDZmk:
33230 case VFMSUBADD213PDZmkz:
33231 case VFMSUBADD213PDZr:
33232 case VFMSUBADD213PDZrb:
33233 case VFMSUBADD213PDZrbk:
33234 case VFMSUBADD213PDZrbkz:
33235 case VFMSUBADD213PDZrk:
33236 case VFMSUBADD213PDZrkz:
33237 case VFMSUBADD213PDm:
33238 case VFMSUBADD213PDr:
33239 return true;
33240 }
33241 return false;
33242}
33243
33244bool isVSQRTPH(unsigned Opcode) {
33245 switch (Opcode) {
33246 case VSQRTPHZ128m:
33247 case VSQRTPHZ128mb:
33248 case VSQRTPHZ128mbk:
33249 case VSQRTPHZ128mbkz:
33250 case VSQRTPHZ128mk:
33251 case VSQRTPHZ128mkz:
33252 case VSQRTPHZ128r:
33253 case VSQRTPHZ128rk:
33254 case VSQRTPHZ128rkz:
33255 case VSQRTPHZ256m:
33256 case VSQRTPHZ256mb:
33257 case VSQRTPHZ256mbk:
33258 case VSQRTPHZ256mbkz:
33259 case VSQRTPHZ256mk:
33260 case VSQRTPHZ256mkz:
33261 case VSQRTPHZ256r:
33262 case VSQRTPHZ256rk:
33263 case VSQRTPHZ256rkz:
33264 case VSQRTPHZm:
33265 case VSQRTPHZmb:
33266 case VSQRTPHZmbk:
33267 case VSQRTPHZmbkz:
33268 case VSQRTPHZmk:
33269 case VSQRTPHZmkz:
33270 case VSQRTPHZr:
33271 case VSQRTPHZrb:
33272 case VSQRTPHZrbk:
33273 case VSQRTPHZrbkz:
33274 case VSQRTPHZrk:
33275 case VSQRTPHZrkz:
33276 return true;
33277 }
33278 return false;
33279}
33280
33281bool isPOPF(unsigned Opcode) {
33282 return Opcode == POPF16;
33283}
33284
33285bool isVPSUBUSB(unsigned Opcode) {
33286 switch (Opcode) {
33287 case VPSUBUSBYrm:
33288 case VPSUBUSBYrr:
33289 case VPSUBUSBZ128rm:
33290 case VPSUBUSBZ128rmk:
33291 case VPSUBUSBZ128rmkz:
33292 case VPSUBUSBZ128rr:
33293 case VPSUBUSBZ128rrk:
33294 case VPSUBUSBZ128rrkz:
33295 case VPSUBUSBZ256rm:
33296 case VPSUBUSBZ256rmk:
33297 case VPSUBUSBZ256rmkz:
33298 case VPSUBUSBZ256rr:
33299 case VPSUBUSBZ256rrk:
33300 case VPSUBUSBZ256rrkz:
33301 case VPSUBUSBZrm:
33302 case VPSUBUSBZrmk:
33303 case VPSUBUSBZrmkz:
33304 case VPSUBUSBZrr:
33305 case VPSUBUSBZrrk:
33306 case VPSUBUSBZrrkz:
33307 case VPSUBUSBrm:
33308 case VPSUBUSBrr:
33309 return true;
33310 }
33311 return false;
33312}
33313
33314bool isTCVTROWPS2BF16L(unsigned Opcode) {
33315 switch (Opcode) {
33316 case TCVTROWPS2BF16Lrte:
33317 case TCVTROWPS2BF16Lrti:
33318 return true;
33319 }
33320 return false;
33321}
33322
33323bool isVPADDSW(unsigned Opcode) {
33324 switch (Opcode) {
33325 case VPADDSWYrm:
33326 case VPADDSWYrr:
33327 case VPADDSWZ128rm:
33328 case VPADDSWZ128rmk:
33329 case VPADDSWZ128rmkz:
33330 case VPADDSWZ128rr:
33331 case VPADDSWZ128rrk:
33332 case VPADDSWZ128rrkz:
33333 case VPADDSWZ256rm:
33334 case VPADDSWZ256rmk:
33335 case VPADDSWZ256rmkz:
33336 case VPADDSWZ256rr:
33337 case VPADDSWZ256rrk:
33338 case VPADDSWZ256rrkz:
33339 case VPADDSWZrm:
33340 case VPADDSWZrmk:
33341 case VPADDSWZrmkz:
33342 case VPADDSWZrr:
33343 case VPADDSWZrrk:
33344 case VPADDSWZrrkz:
33345 case VPADDSWrm:
33346 case VPADDSWrr:
33347 return true;
33348 }
33349 return false;
33350}
33351
33352bool isPREFETCHIT1(unsigned Opcode) {
33353 return Opcode == PREFETCHIT1;
33354}
33355
33356bool isVADDSUBPD(unsigned Opcode) {
33357 switch (Opcode) {
33358 case VADDSUBPDYrm:
33359 case VADDSUBPDYrr:
33360 case VADDSUBPDrm:
33361 case VADDSUBPDrr:
33362 return true;
33363 }
33364 return false;
33365}
33366
33367bool isKANDD(unsigned Opcode) {
33368 return Opcode == KANDDkk;
33369}
33370
33371bool isPREFETCHRST2(unsigned Opcode) {
33372 return Opcode == PREFETCHRST2;
33373}
33374
33375bool isOUTSB(unsigned Opcode) {
33376 return Opcode == OUTSB;
33377}
33378
33379bool isFNSTSW(unsigned Opcode) {
33380 switch (Opcode) {
33381 case FNSTSW16r:
33382 case FNSTSWm:
33383 return true;
33384 }
33385 return false;
33386}
33387
33388bool isPMINSB(unsigned Opcode) {
33389 switch (Opcode) {
33390 case PMINSBrm:
33391 case PMINSBrr:
33392 return true;
33393 }
33394 return false;
33395}
33396
33397
33398} // namespace llvm::X86
33399
33400#endif // GET_X86_MNEMONIC_TABLES_CPP
33401
33402