1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* X86 Mnemonic tables *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_X86_MNEMONIC_TABLES_H
10#undef GET_X86_MNEMONIC_TABLES_H
11
12namespace llvm::X86 {
13
14bool isFSUBRP(unsigned Opcode);
15bool isVPDPBUSDS(unsigned Opcode);
16bool isPUNPCKLWD(unsigned Opcode);
17bool isVREDUCEBF16(unsigned Opcode);
18bool isPUNPCKLQDQ(unsigned Opcode);
19bool isRDFSBASE(unsigned Opcode);
20bool isVPCMOV(unsigned Opcode);
21bool isVDIVSD(unsigned Opcode);
22bool isVCVTTPS2IBS(unsigned Opcode);
23bool isVPEXTRW(unsigned Opcode);
24bool isLODSD(unsigned Opcode);
25bool isVPTESTNMQ(unsigned Opcode);
26bool isCVTSS2SD(unsigned Opcode);
27bool isVGETMANTPD(unsigned Opcode);
28bool isVMOVDQA64(unsigned Opcode);
29bool isINVLPG(unsigned Opcode);
30bool isVGETEXPBF16(unsigned Opcode);
31bool isVBROADCASTF64X4(unsigned Opcode);
32bool isVPERMI2Q(unsigned Opcode);
33bool isVPMOVSXBD(unsigned Opcode);
34bool isVFMSUB132SS(unsigned Opcode);
35bool isVPMOVUSDW(unsigned Opcode);
36bool isAAD(unsigned Opcode);
37bool isIDIV(unsigned Opcode);
38bool isCVTTPS2DQ(unsigned Opcode);
39bool isVBROADCASTF32X8(unsigned Opcode);
40bool isVFMSUBSS(unsigned Opcode);
41bool isEMMS(unsigned Opcode);
42bool isVPDPBSUD(unsigned Opcode);
43bool isPMOVSXWQ(unsigned Opcode);
44bool isPSRLW(unsigned Opcode);
45bool isMOVNTDQA(unsigned Opcode);
46bool isFUCOMPI(unsigned Opcode);
47bool isANDNPS(unsigned Opcode);
48bool isVINSERTF64X2(unsigned Opcode);
49bool isCLTS(unsigned Opcode);
50bool isSETSSBSY(unsigned Opcode);
51bool isVMULPD(unsigned Opcode);
52bool isVFMADDSUB132PS(unsigned Opcode);
53bool isVPMADCSWD(unsigned Opcode);
54bool isVSCATTERPF0DPS(unsigned Opcode);
55bool isXCHG(unsigned Opcode);
56bool isVGATHERPF1QPS(unsigned Opcode);
57bool isVCVTNEPS2BF16(unsigned Opcode);
58bool isVFMADDSS(unsigned Opcode);
59bool isINTO(unsigned Opcode);
60bool isANDPD(unsigned Opcode);
61bool isSEAMCALL(unsigned Opcode);
62bool isSHLD(unsigned Opcode);
63bool isUNPCKHPS(unsigned Opcode);
64bool isVPDPBSSDS(unsigned Opcode);
65bool isSETZUCC(unsigned Opcode);
66bool isSHUFPD(unsigned Opcode);
67bool isFCMOVNB(unsigned Opcode);
68bool isCVTTSS2SI(unsigned Opcode);
69bool isEXTRQ(unsigned Opcode);
70bool isVBROADCASTSS(unsigned Opcode);
71bool isCLUI(unsigned Opcode);
72bool isVINSERTI128(unsigned Opcode);
73bool isVPSHLDW(unsigned Opcode);
74bool isVBLENDPD(unsigned Opcode);
75bool isVSM4KEY4(unsigned Opcode);
76bool isVCVTNEEPH2PS(unsigned Opcode);
77bool isVCVTTSD2SI(unsigned Opcode);
78bool isWRMSRNS(unsigned Opcode);
79bool isCMPSB(unsigned Opcode);
80bool isVRCPBF16(unsigned Opcode);
81bool isMULSS(unsigned Opcode);
82bool isVMRUN(unsigned Opcode);
83bool isVPSRLVD(unsigned Opcode);
84bool isLEAVE(unsigned Opcode);
85bool isVGETMANTPS(unsigned Opcode);
86bool isXSHA256(unsigned Opcode);
87bool isBOUND(unsigned Opcode);
88bool isSFENCE(unsigned Opcode);
89bool isVPHADDD(unsigned Opcode);
90bool isADOX(unsigned Opcode);
91bool isVPSLLQ(unsigned Opcode);
92bool isVCVTPH2HF8(unsigned Opcode);
93bool isPFRSQIT1(unsigned Opcode);
94bool isCLAC(unsigned Opcode);
95bool isKNOTW(unsigned Opcode);
96bool isVCVTPH2PD(unsigned Opcode);
97bool isVAESENC(unsigned Opcode);
98bool isMOVNTI(unsigned Opcode);
99bool isFXCH(unsigned Opcode);
100bool isPOPP(unsigned Opcode);
101bool isVPBLENDMD(unsigned Opcode);
102bool isFSINCOS(unsigned Opcode);
103bool isVPMOVSXBW(unsigned Opcode);
104bool isVPMULLW(unsigned Opcode);
105bool isSTC(unsigned Opcode);
106bool isVPINSRB(unsigned Opcode);
107bool isLWPVAL(unsigned Opcode);
108bool isKXORB(unsigned Opcode);
109bool isRSTORSSP(unsigned Opcode);
110bool isVPRORQ(unsigned Opcode);
111bool isVSM3MSG1(unsigned Opcode);
112bool isFICOM(unsigned Opcode);
113bool isMAXPS(unsigned Opcode);
114bool isFNCLEX(unsigned Opcode);
115bool isVMOVMSKPS(unsigned Opcode);
116bool isVPMOVDB(unsigned Opcode);
117bool isLLWPCB(unsigned Opcode);
118bool isVMULSS(unsigned Opcode);
119bool isAESENCLAST(unsigned Opcode);
120bool isTILEMOVROW(unsigned Opcode);
121bool isVMINMAXPH(unsigned Opcode);
122bool isVPMAXUB(unsigned Opcode);
123bool isAAS(unsigned Opcode);
124bool isFADD(unsigned Opcode);
125bool isJMP(unsigned Opcode);
126bool isXCRYPTECB(unsigned Opcode);
127bool isPFRCPIT1(unsigned Opcode);
128bool isPMULHRW(unsigned Opcode);
129bool isVCVTPH2PS(unsigned Opcode);
130bool isVPBLENDVB(unsigned Opcode);
131bool isPCMPESTRI(unsigned Opcode);
132bool isSENDUIPI(unsigned Opcode);
133bool isFLDLN2(unsigned Opcode);
134bool isVPMACSWD(unsigned Opcode);
135bool isSHA1MSG1(unsigned Opcode);
136bool isVADDPS(unsigned Opcode);
137bool isVCVTPS2DQ(unsigned Opcode);
138bool isPFPNACC(unsigned Opcode);
139bool isFMUL(unsigned Opcode);
140bool isFNSAVE(unsigned Opcode);
141bool isCDQE(unsigned Opcode);
142bool isVPMACSDD(unsigned Opcode);
143bool isVSQRTPS(unsigned Opcode);
144bool isCMPSQ(unsigned Opcode);
145bool isVPSCATTERDD(unsigned Opcode);
146bool isVCVTTSD2USIS(unsigned Opcode);
147bool isVRNDSCALESD(unsigned Opcode);
148bool isSUBPS(unsigned Opcode);
149bool isVMAXSH(unsigned Opcode);
150bool isFLDZ(unsigned Opcode);
151bool isVFNMADD132SS(unsigned Opcode);
152bool isLGDTW(unsigned Opcode);
153bool isTCVTROWPS2PHH(unsigned Opcode);
154bool isINC(unsigned Opcode);
155bool isPABSB(unsigned Opcode);
156bool isVPANDN(unsigned Opcode);
157bool isVPMAXUD(unsigned Opcode);
158bool isVSHA512RNDS2(unsigned Opcode);
159bool isPHADDSW(unsigned Opcode);
160bool isVPMOVSQW(unsigned Opcode);
161bool isADDSUBPS(unsigned Opcode);
162bool isVPMACSSDQL(unsigned Opcode);
163bool isPXOR(unsigned Opcode);
164bool isVPSRAD(unsigned Opcode);
165bool isVPSHAB(unsigned Opcode);
166bool isBTR(unsigned Opcode);
167bool isKORW(unsigned Opcode);
168bool isVRANGESS(unsigned Opcode);
169bool isVCMPPS(unsigned Opcode);
170bool isVPLZCNTD(unsigned Opcode);
171bool isTDPBUUD(unsigned Opcode);
172bool isROUNDPS(unsigned Opcode);
173bool isFABS(unsigned Opcode);
174bool isSUBPD(unsigned Opcode);
175bool isGF2P8MULB(unsigned Opcode);
176bool isTZMSK(unsigned Opcode);
177bool isVMINMAXSD(unsigned Opcode);
178bool isANDPS(unsigned Opcode);
179bool isVEXTRACTF32X8(unsigned Opcode);
180bool isSEAMRET(unsigned Opcode);
181bool isVPCOMW(unsigned Opcode);
182bool isVFIXUPIMMPD(unsigned Opcode);
183bool isKANDND(unsigned Opcode);
184bool isVMRESUME(unsigned Opcode);
185bool isCVTPD2DQ(unsigned Opcode);
186bool isVFNMADD213PS(unsigned Opcode);
187bool isVPEXTRD(unsigned Opcode);
188bool isPACKUSWB(unsigned Opcode);
189bool isVEXTRACTI32X8(unsigned Opcode);
190bool isVHADDPD(unsigned Opcode);
191bool isVPSADBW(unsigned Opcode);
192bool isMOVDQ2Q(unsigned Opcode);
193bool isPUNPCKHBW(unsigned Opcode);
194bool isXOR(unsigned Opcode);
195bool isPSIGNB(unsigned Opcode);
196bool isVPHADDSW(unsigned Opcode);
197bool isFADDP(unsigned Opcode);
198bool isNEG(unsigned Opcode);
199bool isFLDLG2(unsigned Opcode);
200bool isFNOP(unsigned Opcode);
201bool isVMINSS(unsigned Opcode);
202bool isPCMPISTRM(unsigned Opcode);
203bool isVFMADD132SS(unsigned Opcode);
204bool isFDIVRP(unsigned Opcode);
205bool isPUSHAL(unsigned Opcode);
206bool isSUBSD(unsigned Opcode);
207bool isVPBLENDMQ(unsigned Opcode);
208bool isVPMACSDQL(unsigned Opcode);
209bool isVGATHERDPS(unsigned Opcode);
210bool isSYSRET(unsigned Opcode);
211bool isVPADDB(unsigned Opcode);
212bool isXEND(unsigned Opcode);
213bool isWRSSD(unsigned Opcode);
214bool isVMINMAXSS(unsigned Opcode);
215bool isVCVTDQ2PH(unsigned Opcode);
216bool isCVTPD2PS(unsigned Opcode);
217bool isMAXPD(unsigned Opcode);
218bool isRCPSS(unsigned Opcode);
219bool isVMOVAPD(unsigned Opcode);
220bool isVPSUBSB(unsigned Opcode);
221bool isRDTSC(unsigned Opcode);
222bool isVCVTTPS2UDQS(unsigned Opcode);
223bool isVPMADCSSWD(unsigned Opcode);
224bool isVFNMADD213PH(unsigned Opcode);
225bool isVGF2P8AFFINEQB(unsigned Opcode);
226bool isPMOVZXWD(unsigned Opcode);
227bool isPMINUD(unsigned Opcode);
228bool isXSUSLDTRK(unsigned Opcode);
229bool isVCVTPH2UW(unsigned Opcode);
230bool isPADDSW(unsigned Opcode);
231bool isLFENCE(unsigned Opcode);
232bool isCRC32(unsigned Opcode);
233bool isAESENCWIDE256KL(unsigned Opcode);
234bool isMOVAPD(unsigned Opcode);
235bool isVFMADD213PS(unsigned Opcode);
236bool isVPDPWUUDS(unsigned Opcode);
237bool isMOVSLDUP(unsigned Opcode);
238bool isCLDEMOTE(unsigned Opcode);
239bool isVFNMADD231PS(unsigned Opcode);
240bool isVMOVMSKPD(unsigned Opcode);
241bool isPREFETCHT0(unsigned Opcode);
242bool isVCVTNEOBF162PS(unsigned Opcode);
243bool isVPCMPUD(unsigned Opcode);
244bool isVMAXSD(unsigned Opcode);
245bool isVRCP28SD(unsigned Opcode);
246bool isVMAXPS(unsigned Opcode);
247bool isVPMOVD2M(unsigned Opcode);
248bool isVPMACSSWD(unsigned Opcode);
249bool isVUCOMISD(unsigned Opcode);
250bool isLTR(unsigned Opcode);
251bool isVCVTUSI2SH(unsigned Opcode);
252bool isVSCATTERPF1QPS(unsigned Opcode);
253bool isWRGSBASE(unsigned Opcode);
254bool isSTOSQ(unsigned Opcode);
255bool isVSQRTSD(unsigned Opcode);
256bool isVPERMIL2PD(unsigned Opcode);
257bool isVFCMADDCSH(unsigned Opcode);
258bool isVFMADDSUB213PS(unsigned Opcode);
259bool isPFSUB(unsigned Opcode);
260bool isVSQRTSS(unsigned Opcode);
261bool isVEXPANDPS(unsigned Opcode);
262bool isVPCOMPRESSW(unsigned Opcode);
263bool isPEXTRD(unsigned Opcode);
264bool isVCVTTPS2UQQS(unsigned Opcode);
265bool isSYSEXITQ(unsigned Opcode);
266bool isROUNDSD(unsigned Opcode);
267bool isVFMADD132BF16(unsigned Opcode);
268bool isFCOM(unsigned Opcode);
269bool isVFNMSUBSS(unsigned Opcode);
270bool isKSHIFTLW(unsigned Opcode);
271bool isVMPTRLD(unsigned Opcode);
272bool isSCASD(unsigned Opcode);
273bool isVAESDECLAST(unsigned Opcode);
274bool isVFMADDSUBPS(unsigned Opcode);
275bool isVCVTUQQ2PS(unsigned Opcode);
276bool isVPMOVUSDB(unsigned Opcode);
277bool isVPROTW(unsigned Opcode);
278bool isVDPPS(unsigned Opcode);
279bool isVRSQRT14PD(unsigned Opcode);
280bool isVTESTPD(unsigned Opcode);
281bool isVFNMADD231SH(unsigned Opcode);
282bool isENDBR64(unsigned Opcode);
283bool isMULSD(unsigned Opcode);
284bool isXRSTORS(unsigned Opcode);
285bool isPREFETCHNTA(unsigned Opcode);
286bool isVPCOMD(unsigned Opcode);
287bool isVPCOMUB(unsigned Opcode);
288bool isVPDPBSSD(unsigned Opcode);
289bool isVPHSUBD(unsigned Opcode);
290bool isVBROADCASTI64X2(unsigned Opcode);
291bool isFPATAN(unsigned Opcode);
292bool isLOOPE(unsigned Opcode);
293bool isPCMPEQW(unsigned Opcode);
294bool isVFMADDCSH(unsigned Opcode);
295bool isMOVRS(unsigned Opcode);
296bool isVFMSUBADD132PH(unsigned Opcode);
297bool isKADDW(unsigned Opcode);
298bool isPTEST(unsigned Opcode);
299bool isVPADDSB(unsigned Opcode);
300bool isVRSQRT28PS(unsigned Opcode);
301bool isVGF2P8AFFINEINVQB(unsigned Opcode);
302bool isSERIALIZE(unsigned Opcode);
303bool isVPHADDWQ(unsigned Opcode);
304bool isVRNDSCALESH(unsigned Opcode);
305bool isAAA(unsigned Opcode);
306bool isVADDBF16(unsigned Opcode);
307bool isWRMSRLIST(unsigned Opcode);
308bool isVCVTPH2PSX(unsigned Opcode);
309bool isVFMSUB231PH(unsigned Opcode);
310bool isVGATHERQPD(unsigned Opcode);
311bool isKADDB(unsigned Opcode);
312bool isCVTPD2PI(unsigned Opcode);
313bool isVFNMSUB213PH(unsigned Opcode);
314bool isVPCMPESTRI(unsigned Opcode);
315bool isVPSHRDW(unsigned Opcode);
316bool isXORPS(unsigned Opcode);
317bool isPOP2(unsigned Opcode);
318bool isRDMSRLIST(unsigned Opcode);
319bool isVPDPBUSD(unsigned Opcode);
320bool isVCMPPH(unsigned Opcode);
321bool isVANDNPD(unsigned Opcode);
322bool isSUB(unsigned Opcode);
323bool isVRSQRT28PD(unsigned Opcode);
324bool isVFNMADD132PH(unsigned Opcode);
325bool isVPMACSSWW(unsigned Opcode);
326bool isXSTORE(unsigned Opcode);
327bool isVPROTQ(unsigned Opcode);
328bool isVPHADDBD(unsigned Opcode);
329bool isVPMAXSB(unsigned Opcode);
330bool isVMOVDQU8(unsigned Opcode);
331bool isVPMOVSXWD(unsigned Opcode);
332bool isVMINMAXPD(unsigned Opcode);
333bool isSHA256RNDS2(unsigned Opcode);
334bool isKANDB(unsigned Opcode);
335bool isTPAUSE(unsigned Opcode);
336bool isPUSH(unsigned Opcode);
337bool isVRNDSCALESS(unsigned Opcode);
338bool isVRNDSCALEBF16(unsigned Opcode);
339bool isVPCMPISTRI(unsigned Opcode);
340bool isSTGI(unsigned Opcode);
341bool isSBB(unsigned Opcode);
342bool isBLCS(unsigned Opcode);
343bool isVCVTSD2SH(unsigned Opcode);
344bool isVPERMW(unsigned Opcode);
345bool isXRESLDTRK(unsigned Opcode);
346bool isAESENC256KL(unsigned Opcode);
347bool isVGATHERDPD(unsigned Opcode);
348bool isHRESET(unsigned Opcode);
349bool isVFMSUBADD231PD(unsigned Opcode);
350bool isVFRCZSS(unsigned Opcode);
351bool isMINPS(unsigned Opcode);
352bool isFPREM1(unsigned Opcode);
353bool isVPCMPUB(unsigned Opcode);
354bool isVSQRTPD(unsigned Opcode);
355bool isVFRCZPS(unsigned Opcode);
356bool isVFNMADD213SS(unsigned Opcode);
357bool isVPSHRDVQ(unsigned Opcode);
358bool isVPMOVDW(unsigned Opcode);
359bool isVCVTPH2HF8S(unsigned Opcode);
360bool isVBROADCASTSD(unsigned Opcode);
361bool isVSHUFPD(unsigned Opcode);
362bool isVPSUBSW(unsigned Opcode);
363bool isKUNPCKBW(unsigned Opcode);
364bool isVPBLENDD(unsigned Opcode);
365bool isUNPCKHPD(unsigned Opcode);
366bool isVFNMADD231SD(unsigned Opcode);
367bool isVPBROADCASTMW2D(unsigned Opcode);
368bool isVPMULTISHIFTQB(unsigned Opcode);
369bool isVP2INTERSECTQ(unsigned Opcode);
370bool isVFNMSUB132BF16(unsigned Opcode);
371bool isVFMADD213BF16(unsigned Opcode);
372bool isVPUNPCKHWD(unsigned Opcode);
373bool isVPERM2F128(unsigned Opcode);
374bool isINSD(unsigned Opcode);
375bool isLFS(unsigned Opcode);
376bool isFMULP(unsigned Opcode);
377bool isCWD(unsigned Opcode);
378bool isVDIVSS(unsigned Opcode);
379bool isVPSRLQ(unsigned Opcode);
380bool isFSQRT(unsigned Opcode);
381bool isJRCXZ(unsigned Opcode);
382bool isVPMOVMSKB(unsigned Opcode);
383bool isAESDEC256KL(unsigned Opcode);
384bool isFLDENV(unsigned Opcode);
385bool isVPHSUBWD(unsigned Opcode);
386bool isWBNOINVD(unsigned Opcode);
387bool isVEXPANDPD(unsigned Opcode);
388bool isFYL2XP1(unsigned Opcode);
389bool isPREFETCHT2(unsigned Opcode);
390bool isVPDPBSUDS(unsigned Opcode);
391bool isVSHA512MSG2(unsigned Opcode);
392bool isPMULHUW(unsigned Opcode);
393bool isKANDNB(unsigned Opcode);
394bool isVCVTUW2PH(unsigned Opcode);
395bool isAESDECWIDE256KL(unsigned Opcode);
396bool isVPGATHERDD(unsigned Opcode);
397bool isVREDUCESH(unsigned Opcode);
398bool isPOPFQ(unsigned Opcode);
399bool isPAVGUSB(unsigned Opcode);
400bool isVALIGND(unsigned Opcode);
401bool isVPHMINPOSUW(unsigned Opcode);
402bool isLIDTD(unsigned Opcode);
403bool isVPERMT2PD(unsigned Opcode);
404bool isVMLAUNCH(unsigned Opcode);
405bool isVPXORQ(unsigned Opcode);
406bool isMOVNTDQ(unsigned Opcode);
407bool isPOP2P(unsigned Opcode);
408bool isVADDPD(unsigned Opcode);
409bool isSMSW(unsigned Opcode);
410bool isVEXP2PD(unsigned Opcode);
411bool isPMULUDQ(unsigned Opcode);
412bool isIRET(unsigned Opcode);
413bool isMULPS(unsigned Opcode);
414bool isTDPBF8PS(unsigned Opcode);
415bool isVFNMSUBPD(unsigned Opcode);
416bool isPHADDW(unsigned Opcode);
417bool isRDSEED(unsigned Opcode);
418bool isVPSHLW(unsigned Opcode);
419bool isRMPUPDATE(unsigned Opcode);
420bool isVFMADD231PH(unsigned Opcode);
421bool isVPSHAD(unsigned Opcode);
422bool isCLWB(unsigned Opcode);
423bool isPSUBUSB(unsigned Opcode);
424bool isVCVTTSD2USI(unsigned Opcode);
425bool isVEXTRACTPS(unsigned Opcode);
426bool isMOVLPD(unsigned Opcode);
427bool isLGDTD(unsigned Opcode);
428bool isVPBROADCASTMB2Q(unsigned Opcode);
429bool isOUT(unsigned Opcode);
430bool isVMSAVE(unsigned Opcode);
431bool isVCVTQQ2PD(unsigned Opcode);
432bool isVFMADD213PH(unsigned Opcode);
433bool isFCMOVBE(unsigned Opcode);
434bool isMOVSHDUP(unsigned Opcode);
435bool isVPMOVUSQB(unsigned Opcode);
436bool isFIST(unsigned Opcode);
437bool isHADDPD(unsigned Opcode);
438bool isPACKSSWB(unsigned Opcode);
439bool isVPMACSSDQH(unsigned Opcode);
440bool isVFNMSUB132SD(unsigned Opcode);
441bool isVPMASKMOVQ(unsigned Opcode);
442bool isVCOMPRESSPD(unsigned Opcode);
443bool isVFMADD213SS(unsigned Opcode);
444bool isVPCMPQ(unsigned Opcode);
445bool isVADDSH(unsigned Opcode);
446bool isVFNMADDSD(unsigned Opcode);
447bool isUMWAIT(unsigned Opcode);
448bool isVPUNPCKHDQ(unsigned Opcode);
449bool isLCALL(unsigned Opcode);
450bool isAESDEC128KL(unsigned Opcode);
451bool isVSUBPS(unsigned Opcode);
452bool isFSTP(unsigned Opcode);
453bool isVCVTUDQ2PD(unsigned Opcode);
454bool isVPMOVSWB(unsigned Opcode);
455bool isVPANDNQ(unsigned Opcode);
456bool isSYSENTER(unsigned Opcode);
457bool isVPHADDWD(unsigned Opcode);
458bool isVMOVHPD(unsigned Opcode);
459bool isMOVHPD(unsigned Opcode);
460bool isVDIVPH(unsigned Opcode);
461bool isFFREE(unsigned Opcode);
462bool isVGATHERPF1DPS(unsigned Opcode);
463bool isVPCMPESTRIQ(unsigned Opcode);
464bool isVFNMADD231PD(unsigned Opcode);
465bool isVFCMULCPH(unsigned Opcode);
466bool isVPADDD(unsigned Opcode);
467bool isVPCOMUQ(unsigned Opcode);
468bool isVSM3MSG2(unsigned Opcode);
469bool isVERR(unsigned Opcode);
470bool isKORTESTQ(unsigned Opcode);
471bool isVFMSUB132SD(unsigned Opcode);
472bool isTILEZERO(unsigned Opcode);
473bool isPFADD(unsigned Opcode);
474bool isVCVTSI2SD(unsigned Opcode);
475bool isTILELOADDRS(unsigned Opcode);
476bool isVSTMXCSR(unsigned Opcode);
477bool isVCVTTSH2SI(unsigned Opcode);
478bool isRET(unsigned Opcode);
479bool isLZCNT(unsigned Opcode);
480bool isMULPD(unsigned Opcode);
481bool isVBROADCASTI32X2(unsigned Opcode);
482bool isVCVTPH2W(unsigned Opcode);
483bool isCQO(unsigned Opcode);
484bool isFSUBR(unsigned Opcode);
485bool isDPPD(unsigned Opcode);
486bool isFCOS(unsigned Opcode);
487bool isXSAVES(unsigned Opcode);
488bool isTZCNT(unsigned Opcode);
489bool isLJMP(unsigned Opcode);
490bool isCMOVCC(unsigned Opcode);
491bool isVCVTBIASPH2HF8(unsigned Opcode);
492bool isINVEPT(unsigned Opcode);
493bool isADDSUBPD(unsigned Opcode);
494bool isVCVTSS2SD(unsigned Opcode);
495bool isVMOVSHDUP(unsigned Opcode);
496bool isKSHIFTRD(unsigned Opcode);
497bool isVPTERNLOGD(unsigned Opcode);
498bool isPADDQ(unsigned Opcode);
499bool isVEXTRACTI64X4(unsigned Opcode);
500bool isVFMSUB231SS(unsigned Opcode);
501bool isVPCMPEQB(unsigned Opcode);
502bool isLEA(unsigned Opcode);
503bool isPSUBB(unsigned Opcode);
504bool isKADDQ(unsigned Opcode);
505bool isMOVSX(unsigned Opcode);
506bool isVALIGNQ(unsigned Opcode);
507bool isVCVTNE2PS2BF16(unsigned Opcode);
508bool isVPSRAW(unsigned Opcode);
509bool isVFMSUBADD231PH(unsigned Opcode);
510bool isCVTDQ2PS(unsigned Opcode);
511bool isFBLD(unsigned Opcode);
512bool isLMSW(unsigned Opcode);
513bool isVRNDSCALEPH(unsigned Opcode);
514bool isMINSS(unsigned Opcode);
515bool isWRMSR(unsigned Opcode);
516bool isFSCALE(unsigned Opcode);
517bool isVFNMADD213SH(unsigned Opcode);
518bool isIMULZU(unsigned Opcode);
519bool isVPHADDUBD(unsigned Opcode);
520bool isRDSSPQ(unsigned Opcode);
521bool isVCVTBF162IBS(unsigned Opcode);
522bool isLGDT(unsigned Opcode);
523bool isVPSHLDVD(unsigned Opcode);
524bool isPFCMPGT(unsigned Opcode);
525bool isJCXZ(unsigned Opcode);
526bool isVPMOVZXBW(unsigned Opcode);
527bool isVFMADDSUB231PD(unsigned Opcode);
528bool isVBLENDMPD(unsigned Opcode);
529bool isHSUBPS(unsigned Opcode);
530bool isPREFETCHIT0(unsigned Opcode);
531bool isKTESTD(unsigned Opcode);
532bool isVCVTNEOPH2PS(unsigned Opcode);
533bool isVBLENDVPD(unsigned Opcode);
534bool isVCVTSS2USI(unsigned Opcode);
535bool isVCVTTPS2DQS(unsigned Opcode);
536bool isVPANDD(unsigned Opcode);
537bool isPMINSW(unsigned Opcode);
538bool isSTAC(unsigned Opcode);
539bool isVFMSUB213PS(unsigned Opcode);
540bool isPOPAL(unsigned Opcode);
541bool isVCVTPS2UQQ(unsigned Opcode);
542bool isRDRAND(unsigned Opcode);
543bool isJCC(unsigned Opcode);
544bool isVPMINSQ(unsigned Opcode);
545bool isVADDSD(unsigned Opcode);
546bool isDPPS(unsigned Opcode);
547bool isPINSRQ(unsigned Opcode);
548bool isVUCOMISS(unsigned Opcode);
549bool isVPDPWSUD(unsigned Opcode);
550bool isKANDNW(unsigned Opcode);
551bool isAOR(unsigned Opcode);
552bool isPMAXUB(unsigned Opcode);
553bool isANDNPD(unsigned Opcode);
554bool isINVPCID(unsigned Opcode);
555bool isRDGSBASE(unsigned Opcode);
556bool isVPMOVSQD(unsigned Opcode);
557bool isBT(unsigned Opcode);
558bool isVPROLVQ(unsigned Opcode);
559bool isVFMADDSUB132PD(unsigned Opcode);
560bool isRORX(unsigned Opcode);
561bool isPADDUSW(unsigned Opcode);
562bool isPFNACC(unsigned Opcode);
563bool isAND(unsigned Opcode);
564bool isPSLLQ(unsigned Opcode);
565bool isVFMSUB132PH(unsigned Opcode);
566bool isXSAVE(unsigned Opcode);
567bool isKNOTQ(unsigned Opcode);
568bool isXTEST(unsigned Opcode);
569bool isVINSERTPS(unsigned Opcode);
570bool isXSAVEOPT(unsigned Opcode);
571bool isLDS(unsigned Opcode);
572bool isVFMADDSUB213PD(unsigned Opcode);
573bool isVINSERTF32X4(unsigned Opcode);
574bool isVRSQRTPS(unsigned Opcode);
575bool isVSUBPH(unsigned Opcode);
576bool isPMOVSXBW(unsigned Opcode);
577bool isVPSRLDQ(unsigned Opcode);
578bool isADC(unsigned Opcode);
579bool isPHADDD(unsigned Opcode);
580bool isVDPPHPS(unsigned Opcode);
581bool isVMINPH(unsigned Opcode);
582bool isVMINSD(unsigned Opcode);
583bool isVROUNDPD(unsigned Opcode);
584bool isVFCMADDCPH(unsigned Opcode);
585bool isINCSSPQ(unsigned Opcode);
586bool isVPUNPCKLDQ(unsigned Opcode);
587bool isVMINSH(unsigned Opcode);
588bool isINSERTQ(unsigned Opcode);
589bool isBLCI(unsigned Opcode);
590bool isHLT(unsigned Opcode);
591bool isVPCOMUW(unsigned Opcode);
592bool isVPMOVSXDQ(unsigned Opcode);
593bool isVFNMSUB231PS(unsigned Opcode);
594bool isVFNMSUB213SH(unsigned Opcode);
595bool isVCVTTPD2UQQ(unsigned Opcode);
596bool isSQRTSS(unsigned Opcode);
597bool isIMUL(unsigned Opcode);
598bool isVCVTSS2SI(unsigned Opcode);
599bool isPUSHAW(unsigned Opcode);
600bool isSTOSD(unsigned Opcode);
601bool isPSRLDQ(unsigned Opcode);
602bool isVSCATTERQPS(unsigned Opcode);
603bool isFIDIV(unsigned Opcode);
604bool isVFMSUB213PD(unsigned Opcode);
605bool isVFMADDSUB231PH(unsigned Opcode);
606bool isTDCALL(unsigned Opcode);
607bool isPVALIDATE(unsigned Opcode);
608bool isVPSHUFLW(unsigned Opcode);
609bool isPCLMULQDQ(unsigned Opcode);
610bool isCMPXCHG8B(unsigned Opcode);
611bool isVPMOVM2B(unsigned Opcode);
612bool isVCVTUDQ2PH(unsigned Opcode);
613bool isPEXTRQ(unsigned Opcode);
614bool isXCRYPTCTR(unsigned Opcode);
615bool isVREDUCEPH(unsigned Opcode);
616bool isUCOMISD(unsigned Opcode);
617bool isOUTSD(unsigned Opcode);
618bool isSUBSS(unsigned Opcode);
619bool isVFMSUBPS(unsigned Opcode);
620bool isVPBLENDW(unsigned Opcode);
621bool isVPEXPANDB(unsigned Opcode);
622bool isBZHI(unsigned Opcode);
623bool isVPRORVD(unsigned Opcode);
624bool isRMPQUERY(unsigned Opcode);
625bool isVPSCATTERDQ(unsigned Opcode);
626bool isPSMASH(unsigned Opcode);
627bool isVPSHLDQ(unsigned Opcode);
628bool isVSCATTERPF1DPD(unsigned Opcode);
629bool isMONTMUL(unsigned Opcode);
630bool isVCVTPH2UQQ(unsigned Opcode);
631bool isPSLLD(unsigned Opcode);
632bool isSAR(unsigned Opcode);
633bool isLDTILECFG(unsigned Opcode);
634bool isPMINUB(unsigned Opcode);
635bool isVCVTNEEBF162PS(unsigned Opcode);
636bool isMOVDIR64B(unsigned Opcode);
637bool isSQRTPS(unsigned Opcode);
638bool isSTR(unsigned Opcode);
639bool isKANDNQ(unsigned Opcode);
640bool isBSF(unsigned Opcode);
641bool isINCSSPD(unsigned Opcode);
642bool isVPDPBUUDS(unsigned Opcode);
643bool isCMPXCHG(unsigned Opcode);
644bool isVPSIGNW(unsigned Opcode);
645bool isVCOMISBF16(unsigned Opcode);
646bool isLES(unsigned Opcode);
647bool isCVTSS2SI(unsigned Opcode);
648bool isPFACC(unsigned Opcode);
649bool isFCOMPI(unsigned Opcode);
650bool isPUNPCKHWD(unsigned Opcode);
651bool isVPMOVUSWB(unsigned Opcode);
652bool isVPTESTNMW(unsigned Opcode);
653bool isVPMULDQ(unsigned Opcode);
654bool isSHRX(unsigned Opcode);
655bool isKXORQ(unsigned Opcode);
656bool isVGETEXPSD(unsigned Opcode);
657bool isV4FNMADDPS(unsigned Opcode);
658bool isVFNMSUB231SD(unsigned Opcode);
659bool isVPSHLD(unsigned Opcode);
660bool isPAVGB(unsigned Opcode);
661bool isPMOVZXBD(unsigned Opcode);
662bool isKORTESTW(unsigned Opcode);
663bool isVSHUFPS(unsigned Opcode);
664bool isAESENCWIDE128KL(unsigned Opcode);
665bool isVPXORD(unsigned Opcode);
666bool isVPSHAW(unsigned Opcode);
667bool isVFMSUB132BF16(unsigned Opcode);
668bool isVPERMT2B(unsigned Opcode);
669bool isVFMADD213PD(unsigned Opcode);
670bool isVPGATHERQD(unsigned Opcode);
671bool isVFNMSUB213BF16(unsigned Opcode);
672bool isVCVTPS2IBS(unsigned Opcode);
673bool isVPCMPGTW(unsigned Opcode);
674bool isVMOVRSB(unsigned Opcode);
675bool isVGETMANTSH(unsigned Opcode);
676bool isVANDPS(unsigned Opcode);
677bool isVDIVPS(unsigned Opcode);
678bool isVANDNPS(unsigned Opcode);
679bool isVPBROADCASTW(unsigned Opcode);
680bool isFLDL2T(unsigned Opcode);
681bool isVPERMB(unsigned Opcode);
682bool isFCMOVNBE(unsigned Opcode);
683bool isVCVTTPH2W(unsigned Opcode);
684bool isPMOVZXBQ(unsigned Opcode);
685bool isPF2ID(unsigned Opcode);
686bool isVFNMADD132PD(unsigned Opcode);
687bool isPMULHRSW(unsigned Opcode);
688bool isKADDD(unsigned Opcode);
689bool isVFNMSUB132SH(unsigned Opcode);
690bool isUIRET(unsigned Opcode);
691bool isBSR(unsigned Opcode);
692bool isPCMPEQQ(unsigned Opcode);
693bool isCDQ(unsigned Opcode);
694bool isPMAXSW(unsigned Opcode);
695bool isSIDTD(unsigned Opcode);
696bool isVCVTPS2PHX(unsigned Opcode);
697bool isVPSLLVQ(unsigned Opcode);
698bool isMOVQ(unsigned Opcode);
699bool isPREFETCH(unsigned Opcode);
700bool isVCMPBF16(unsigned Opcode);
701bool isCLRSSBSY(unsigned Opcode);
702bool isTCVTROWPS2PHL(unsigned Opcode);
703bool isPSHUFW(unsigned Opcode);
704bool isVPDPWSUDS(unsigned Opcode);
705bool isVPMOVSXBQ(unsigned Opcode);
706bool isFICOMP(unsigned Opcode);
707bool isVFNMSUB132SS(unsigned Opcode);
708bool isVLDMXCSR(unsigned Opcode);
709bool isVPSUBUSW(unsigned Opcode);
710bool isRETF(unsigned Opcode);
711bool isKMOVQ(unsigned Opcode);
712bool isVPADDUSW(unsigned Opcode);
713bool isPACKSSDW(unsigned Opcode);
714bool isUMONITOR(unsigned Opcode);
715bool isENQCMDS(unsigned Opcode);
716bool isVCOMXSD(unsigned Opcode);
717bool isVPMAXSQ(unsigned Opcode);
718bool isVFMSUB213BF16(unsigned Opcode);
719bool isVPERMT2Q(unsigned Opcode);
720bool isFDECSTP(unsigned Opcode);
721bool isVPTESTMQ(unsigned Opcode);
722bool isVRCP14PD(unsigned Opcode);
723bool isARPL(unsigned Opcode);
724bool isVFMSUB213SD(unsigned Opcode);
725bool isJMPABS(unsigned Opcode);
726bool isVUNPCKHPS(unsigned Opcode);
727bool isVFNMADDSS(unsigned Opcode);
728bool isSIDT(unsigned Opcode);
729bool isVPCMPGTB(unsigned Opcode);
730bool isVPRORD(unsigned Opcode);
731bool isVSUBSS(unsigned Opcode);
732bool isPUSHFQ(unsigned Opcode);
733bool isVCVTHF82PH(unsigned Opcode);
734bool isVPCLMULQDQ(unsigned Opcode);
735bool isVPADDUSB(unsigned Opcode);
736bool isVPCMPD(unsigned Opcode);
737bool isMOVSD(unsigned Opcode);
738bool isPSUBUSW(unsigned Opcode);
739bool isVFMSUBADD132PS(unsigned Opcode);
740bool isMOVMSKPS(unsigned Opcode);
741bool isVFIXUPIMMSS(unsigned Opcode);
742bool isMFENCE(unsigned Opcode);
743bool isFTST(unsigned Opcode);
744bool isVPMADDWD(unsigned Opcode);
745bool isPOP(unsigned Opcode);
746bool isPSUBW(unsigned Opcode);
747bool isBSWAP(unsigned Opcode);
748bool isPFMIN(unsigned Opcode);
749bool isVFPCLASSPD(unsigned Opcode);
750bool isVPSHRDVD(unsigned Opcode);
751bool isPADDW(unsigned Opcode);
752bool isCVTSI2SD(unsigned Opcode);
753bool isENQCMD(unsigned Opcode);
754bool isXSHA1(unsigned Opcode);
755bool isVFNMADD132SD(unsigned Opcode);
756bool isMOVZX(unsigned Opcode);
757bool isVFIXUPIMMSD(unsigned Opcode);
758bool isINVD(unsigned Opcode);
759bool isVFIXUPIMMPS(unsigned Opcode);
760bool isMOVDQU(unsigned Opcode);
761bool isVFPCLASSPS(unsigned Opcode);
762bool isVPERMILPS(unsigned Opcode);
763bool isMOVSQ(unsigned Opcode);
764bool isAESDECWIDE128KL(unsigned Opcode);
765bool isROUNDSS(unsigned Opcode);
766bool isVPMOVW2M(unsigned Opcode);
767bool isVPSHUFB(unsigned Opcode);
768bool isVMULSD(unsigned Opcode);
769bool isVPERMI2W(unsigned Opcode);
770bool isVREDUCESS(unsigned Opcode);
771bool isFST(unsigned Opcode);
772bool isVPHSUBW(unsigned Opcode);
773bool isFRNDINT(unsigned Opcode);
774bool isSHR(unsigned Opcode);
775bool isLOOPNE(unsigned Opcode);
776bool isVCVTTPH2UQQ(unsigned Opcode);
777bool isSHA1NEXTE(unsigned Opcode);
778bool isVFMADD132SD(unsigned Opcode);
779bool isPSRAW(unsigned Opcode);
780bool isVPBROADCASTQ(unsigned Opcode);
781bool isCLC(unsigned Opcode);
782bool isPOPAW(unsigned Opcode);
783bool isTCMMIMFP16PS(unsigned Opcode);
784bool isVCVTQQ2PH(unsigned Opcode);
785bool isVCVTTPS2UQQ(unsigned Opcode);
786bool isVMOVUPD(unsigned Opcode);
787bool isFPTAN(unsigned Opcode);
788bool isVMASKMOVPD(unsigned Opcode);
789bool isVMOVLHPS(unsigned Opcode);
790bool isAESKEYGENASSIST(unsigned Opcode);
791bool isXSAVEOPT64(unsigned Opcode);
792bool isXSAVEC(unsigned Opcode);
793bool isVPLZCNTQ(unsigned Opcode);
794bool isVPSUBW(unsigned Opcode);
795bool isCMPCCXADD(unsigned Opcode);
796bool isVFMSUBADD213PH(unsigned Opcode);
797bool isVFMADDSUBPD(unsigned Opcode);
798bool isVPMINSW(unsigned Opcode);
799bool isVFNMSUB132PS(unsigned Opcode);
800bool isVMOVAPS(unsigned Opcode);
801bool isVPEXTRQ(unsigned Opcode);
802bool isVSCALEFSH(unsigned Opcode);
803bool isVCVTPD2PS(unsigned Opcode);
804bool isCLGI(unsigned Opcode);
805bool isVAESDEC(unsigned Opcode);
806bool isPFMUL(unsigned Opcode);
807bool isVCVTBIASPH2BF8S(unsigned Opcode);
808bool isMOVDIRI(unsigned Opcode);
809bool isSHUFPS(unsigned Opcode);
810bool isVFNMSUB231SS(unsigned Opcode);
811bool isVMWRITE(unsigned Opcode);
812bool isVINSERTF128(unsigned Opcode);
813bool isFISUBR(unsigned Opcode);
814bool isVINSERTI32X4(unsigned Opcode);
815bool isVPSLLDQ(unsigned Opcode);
816bool isPOPCNT(unsigned Opcode);
817bool isVXORPD(unsigned Opcode);
818bool isXLATB(unsigned Opcode);
819bool isDIV(unsigned Opcode);
820bool isVPSHLDVQ(unsigned Opcode);
821bool isMOVDDUP(unsigned Opcode);
822bool isVMOVDQU64(unsigned Opcode);
823bool isVPCOMPRESSQ(unsigned Opcode);
824bool isVFMSUBADD132PD(unsigned Opcode);
825bool isVPERMILPD(unsigned Opcode);
826bool isADDSD(unsigned Opcode);
827bool isBLENDPD(unsigned Opcode);
828bool isVPANDQ(unsigned Opcode);
829bool isPMADDUBSW(unsigned Opcode);
830bool isPOPFD(unsigned Opcode);
831bool isCMPSW(unsigned Opcode);
832bool isLDMXCSR(unsigned Opcode);
833bool isVMULPS(unsigned Opcode);
834bool isVROUNDSD(unsigned Opcode);
835bool isVFMADD132PD(unsigned Opcode);
836bool isVPSRAQ(unsigned Opcode);
837bool isVCOMISD(unsigned Opcode);
838bool isVCVTBIASPH2BF8(unsigned Opcode);
839bool isFFREEP(unsigned Opcode);
840bool isVFNMADD213PD(unsigned Opcode);
841bool isVCMPPD(unsigned Opcode);
842bool isVFNMSUB132PH(unsigned Opcode);
843bool isVPHADDBW(unsigned Opcode);
844bool isVPPERM(unsigned Opcode);
845bool isVCVTPS2PD(unsigned Opcode);
846bool isCBW(unsigned Opcode);
847bool isVMOVUPS(unsigned Opcode);
848bool isVPMAXUQ(unsigned Opcode);
849bool isWRSSQ(unsigned Opcode);
850bool isPACKUSDW(unsigned Opcode);
851bool isVCVTTBF162IBS(unsigned Opcode);
852bool isXBEGIN(unsigned Opcode);
853bool isVCVTPD2UQQ(unsigned Opcode);
854bool isFCMOVB(unsigned Opcode);
855bool isNOP(unsigned Opcode);
856bool isVPABSQ(unsigned Opcode);
857bool isVTESTPS(unsigned Opcode);
858bool isPHSUBW(unsigned Opcode);
859bool isPUSH2P(unsigned Opcode);
860bool isFISTTP(unsigned Opcode);
861bool isCFCMOVCC(unsigned Opcode);
862bool isPCMPESTRM(unsigned Opcode);
863bool isVPINSRD(unsigned Opcode);
864bool isVFNMSUB213PS(unsigned Opcode);
865bool isPHSUBD(unsigned Opcode);
866bool isSLDT(unsigned Opcode);
867bool isVCVTTPD2DQS(unsigned Opcode);
868bool isVPMINSD(unsigned Opcode);
869bool isVHADDPS(unsigned Opcode);
870bool isVMOVNTDQ(unsigned Opcode);
871bool isVFRCZSD(unsigned Opcode);
872bool isIBHF(unsigned Opcode);
873bool isVPTESTMW(unsigned Opcode);
874bool isVPMOVZXWD(unsigned Opcode);
875bool isPSADBW(unsigned Opcode);
876bool isVCVTSD2SI(unsigned Opcode);
877bool isVMAXPH(unsigned Opcode);
878bool isLODSB(unsigned Opcode);
879bool isPHMINPOSUW(unsigned Opcode);
880bool isVPROLVD(unsigned Opcode);
881bool isWRFSBASE(unsigned Opcode);
882bool isVRSQRT14PS(unsigned Opcode);
883bool isVPHSUBDQ(unsigned Opcode);
884bool isIRETD(unsigned Opcode);
885bool isVMOVRSD(unsigned Opcode);
886bool isVPMULHRSW(unsigned Opcode);
887bool isCVTSI2SS(unsigned Opcode);
888bool isPI2FD(unsigned Opcode);
889bool isGF2P8AFFINEQB(unsigned Opcode);
890bool isPAND(unsigned Opcode);
891bool isVFNMSUB231SH(unsigned Opcode);
892bool isVMOVHLPS(unsigned Opcode);
893bool isKNOTD(unsigned Opcode);
894bool isPEXTRB(unsigned Opcode);
895bool isVCVTPH2BF8(unsigned Opcode);
896bool isVMMCALL(unsigned Opcode);
897bool isVCVTSH2SS(unsigned Opcode);
898bool isVPUNPCKLQDQ(unsigned Opcode);
899bool isVPERMIL2PS(unsigned Opcode);
900bool isVPCMPGTD(unsigned Opcode);
901bool isCMPXCHG16B(unsigned Opcode);
902bool isTDPHF8PS(unsigned Opcode);
903bool isVZEROUPPER(unsigned Opcode);
904bool isMOVAPS(unsigned Opcode);
905bool isVPCMPW(unsigned Opcode);
906bool isFUCOMPP(unsigned Opcode);
907bool isXSETBV(unsigned Opcode);
908bool isSLWPCB(unsigned Opcode);
909bool isSCASW(unsigned Opcode);
910bool isFCMOVNE(unsigned Opcode);
911bool isPBNDKB(unsigned Opcode);
912bool isVPMULLD(unsigned Opcode);
913bool isVP4DPWSSDS(unsigned Opcode);
914bool isVCVT2PH2HF8(unsigned Opcode);
915bool isPINSRW(unsigned Opcode);
916bool isVCVTSI2SH(unsigned Opcode);
917bool isVINSERTF32X8(unsigned Opcode);
918bool isKSHIFTLB(unsigned Opcode);
919bool isSEAMOPS(unsigned Opcode);
920bool isVPMOVSQB(unsigned Opcode);
921bool isVPMULUDQ(unsigned Opcode);
922bool isVPTESTMD(unsigned Opcode);
923bool isVPHADDDQ(unsigned Opcode);
924bool isKUNPCKDQ(unsigned Opcode);
925bool isT1MSKC(unsigned Opcode);
926bool isVBLENDPS(unsigned Opcode);
927bool isVPCOMB(unsigned Opcode);
928bool isPTWRITE(unsigned Opcode);
929bool isVCVTPH2BF8S(unsigned Opcode);
930bool isCVTPS2PI(unsigned Opcode);
931bool isVPROTD(unsigned Opcode);
932bool isCALL(unsigned Opcode);
933bool isTILELOADDRST1(unsigned Opcode);
934bool isVPERMPS(unsigned Opcode);
935bool isVPSHUFBITQMB(unsigned Opcode);
936bool isVMOVSLDUP(unsigned Opcode);
937bool isINVLPGA(unsigned Opcode);
938bool isVCVTPH2QQ(unsigned Opcode);
939bool isADD(unsigned Opcode);
940bool isPSUBSW(unsigned Opcode);
941bool isSIDTW(unsigned Opcode);
942bool isVEXTRACTF64X2(unsigned Opcode);
943bool isVFNMADD231PH(unsigned Opcode);
944bool isFCOMI(unsigned Opcode);
945bool isRSM(unsigned Opcode);
946bool isVPCOMUD(unsigned Opcode);
947bool isVPMOVZXBQ(unsigned Opcode);
948bool isUWRMSR(unsigned Opcode);
949bool isLGS(unsigned Opcode);
950bool isVMOVNTPD(unsigned Opcode);
951bool isPCMPESTRMQ(unsigned Opcode);
952bool isRDPRU(unsigned Opcode);
953bool isVPUNPCKHBW(unsigned Opcode);
954bool isVUCOMXSD(unsigned Opcode);
955bool isANDN(unsigned Opcode);
956bool isVCVTTPH2UW(unsigned Opcode);
957bool isVMFUNC(unsigned Opcode);
958bool isFIMUL(unsigned Opcode);
959bool isBLCFILL(unsigned Opcode);
960bool isVGATHERPF0DPS(unsigned Opcode);
961bool isVFMSUBADD231PS(unsigned Opcode);
962bool isVREDUCESD(unsigned Opcode);
963bool isVCOMXSH(unsigned Opcode);
964bool isVXORPS(unsigned Opcode);
965bool isPSWAPD(unsigned Opcode);
966bool isPMAXSD(unsigned Opcode);
967bool isVCMPSS(unsigned Opcode);
968bool isEXTRACTPS(unsigned Opcode);
969bool isVPMOVZXBD(unsigned Opcode);
970bool isOUTSW(unsigned Opcode);
971bool isKORTESTB(unsigned Opcode);
972bool isVREDUCEPS(unsigned Opcode);
973bool isPEXTRW(unsigned Opcode);
974bool isFNINIT(unsigned Opcode);
975bool isVCVTPH2IBS(unsigned Opcode);
976bool isROL(unsigned Opcode);
977bool isVCVTPS2QQ(unsigned Opcode);
978bool isVGETMANTPH(unsigned Opcode);
979bool isPUNPCKLDQ(unsigned Opcode);
980bool isPADDD(unsigned Opcode);
981bool isVPSLLD(unsigned Opcode);
982bool isPFCMPGE(unsigned Opcode);
983bool isVGETMANTBF16(unsigned Opcode);
984bool isVSUBBF16(unsigned Opcode);
985bool isVPMOVM2D(unsigned Opcode);
986bool isVCVTTSS2USIS(unsigned Opcode);
987bool isVHSUBPS(unsigned Opcode);
988bool isENDBR32(unsigned Opcode);
989bool isMOVSXD(unsigned Opcode);
990bool isPSIGND(unsigned Opcode);
991bool isVPTEST(unsigned Opcode);
992bool isVPDPWUSD(unsigned Opcode);
993bool isHSUBPD(unsigned Opcode);
994bool isADCX(unsigned Opcode);
995bool isCVTTPD2PI(unsigned Opcode);
996bool isPDEP(unsigned Opcode);
997bool isTDPBUSD(unsigned Opcode);
998bool isVCVTBIASPH2HF8S(unsigned Opcode);
999bool isVBROADCASTI32X4(unsigned Opcode);
1000bool isVCVTPH2UDQ(unsigned Opcode);
1001bool isVPHADDW(unsigned Opcode);
1002bool isFLDL2E(unsigned Opcode);
1003bool isCLZERO(unsigned Opcode);
1004bool isPBLENDW(unsigned Opcode);
1005bool isVCVTBF162IUBS(unsigned Opcode);
1006bool isVCVTSH2USI(unsigned Opcode);
1007bool isVANDPD(unsigned Opcode);
1008bool isBEXTR(unsigned Opcode);
1009bool isSTD(unsigned Opcode);
1010bool isVAESKEYGENASSIST(unsigned Opcode);
1011bool isCMPSD(unsigned Opcode);
1012bool isMOVSS(unsigned Opcode);
1013bool isVCVTUQQ2PD(unsigned Opcode);
1014bool isVEXTRACTI32X4(unsigned Opcode);
1015bool isFLDCW(unsigned Opcode);
1016bool isINSW(unsigned Opcode);
1017bool isRDPID(unsigned Opcode);
1018bool isVUCOMXSS(unsigned Opcode);
1019bool isKANDQ(unsigned Opcode);
1020bool isV4FMADDPS(unsigned Opcode);
1021bool isPMOVZXWQ(unsigned Opcode);
1022bool isVFPCLASSSD(unsigned Opcode);
1023bool isBLENDPS(unsigned Opcode);
1024bool isVPACKSSDW(unsigned Opcode);
1025bool isVPHSUBBW(unsigned Opcode);
1026bool isVPINSRW(unsigned Opcode);
1027bool isVMINMAXBF16(unsigned Opcode);
1028bool isVSHUFF64X2(unsigned Opcode);
1029bool isVPACKUSWB(unsigned Opcode);
1030bool isVRSQRT28SS(unsigned Opcode);
1031bool isGETSEC(unsigned Opcode);
1032bool isFXAM(unsigned Opcode);
1033bool isVEXTRACTF64X4(unsigned Opcode);
1034bool isBLSR(unsigned Opcode);
1035bool isFILD(unsigned Opcode);
1036bool isRETFQ(unsigned Opcode);
1037bool isVADDSS(unsigned Opcode);
1038bool isCOMISS(unsigned Opcode);
1039bool isCLI(unsigned Opcode);
1040bool isVERW(unsigned Opcode);
1041bool isBTC(unsigned Opcode);
1042bool isVPHADDUBQ(unsigned Opcode);
1043bool isVPORQ(unsigned Opcode);
1044bool isORPD(unsigned Opcode);
1045bool isVMOVSS(unsigned Opcode);
1046bool isVPSUBD(unsigned Opcode);
1047bool isVGATHERPF1QPD(unsigned Opcode);
1048bool isENCODEKEY256(unsigned Opcode);
1049bool isGF2P8AFFINEINVQB(unsigned Opcode);
1050bool isXRSTOR64(unsigned Opcode);
1051bool isKANDW(unsigned Opcode);
1052bool isLODSQ(unsigned Opcode);
1053bool isVMOVRSW(unsigned Opcode);
1054bool isVSUBSH(unsigned Opcode);
1055bool isLSS(unsigned Opcode);
1056bool isPMOVSXBQ(unsigned Opcode);
1057bool isVCVTTSD2SIS(unsigned Opcode);
1058bool isVCMPSH(unsigned Opcode);
1059bool isVFMADD132PS(unsigned Opcode);
1060bool isVPACKSSWB(unsigned Opcode);
1061bool isPCMPGTQ(unsigned Opcode);
1062bool isVFMADD132SH(unsigned Opcode);
1063bool isVCVTUQQ2PH(unsigned Opcode);
1064bool isVCVTQQ2PS(unsigned Opcode);
1065bool isVCVTTSS2USI(unsigned Opcode);
1066bool isVPMOVM2Q(unsigned Opcode);
1067bool isVMOVD(unsigned Opcode);
1068bool isVCVTTPS2QQS(unsigned Opcode);
1069bool isVSQRTBF16(unsigned Opcode);
1070bool isVFPCLASSPH(unsigned Opcode);
1071bool isVCVTSS2SH(unsigned Opcode);
1072bool isSCASB(unsigned Opcode);
1073bool isPSRLD(unsigned Opcode);
1074bool isVADDPH(unsigned Opcode);
1075bool isFSUB(unsigned Opcode);
1076bool isVCVTTPH2IBS(unsigned Opcode);
1077bool isVEXTRACTI64X2(unsigned Opcode);
1078bool isVPSHLDD(unsigned Opcode);
1079bool isPMINUW(unsigned Opcode);
1080bool isPSUBSB(unsigned Opcode);
1081bool isVCVT2PS2PHX(unsigned Opcode);
1082bool isVPCMPEQD(unsigned Opcode);
1083bool isVPSCATTERQD(unsigned Opcode);
1084bool isKXNORB(unsigned Opcode);
1085bool isLDDQU(unsigned Opcode);
1086bool isMASKMOVQ(unsigned Opcode);
1087bool isPABSW(unsigned Opcode);
1088bool isVPCOMQ(unsigned Opcode);
1089bool isVPROLD(unsigned Opcode);
1090bool isVSCATTERDPD(unsigned Opcode);
1091bool isFXRSTOR(unsigned Opcode);
1092bool isVPCMPUW(unsigned Opcode);
1093bool isWBINVD(unsigned Opcode);
1094bool isVCVTTPD2UDQ(unsigned Opcode);
1095bool isERETU(unsigned Opcode);
1096bool isPFRCPIT2(unsigned Opcode);
1097bool isVPERMT2W(unsigned Opcode);
1098bool isVEXTRACTF32X4(unsigned Opcode);
1099bool isVGATHERPF0DPD(unsigned Opcode);
1100bool isVBROADCASTF32X2(unsigned Opcode);
1101bool isVRCP14SD(unsigned Opcode);
1102bool isLAHF(unsigned Opcode);
1103bool isPABSD(unsigned Opcode);
1104bool isPINSRB(unsigned Opcode);
1105bool isSKINIT(unsigned Opcode);
1106bool isENTER(unsigned Opcode);
1107bool isVCVTSI2SS(unsigned Opcode);
1108bool isVFMADD231PD(unsigned Opcode);
1109bool isLOADIWKEY(unsigned Opcode);
1110bool isVMOVNTDQA(unsigned Opcode);
1111bool isVPERMT2PS(unsigned Opcode);
1112bool isPUSHF(unsigned Opcode);
1113bool isMPSADBW(unsigned Opcode);
1114bool isVMINMAXSH(unsigned Opcode);
1115bool isVRSQRT14SS(unsigned Opcode);
1116bool isVCVTDQ2PD(unsigned Opcode);
1117bool isVORPS(unsigned Opcode);
1118bool isVPEXPANDQ(unsigned Opcode);
1119bool isVPSHRDD(unsigned Opcode);
1120bool isTDPBSSD(unsigned Opcode);
1121bool isTESTUI(unsigned Opcode);
1122bool isVFMADDPD(unsigned Opcode);
1123bool isVPANDND(unsigned Opcode);
1124bool isVPMOVSDB(unsigned Opcode);
1125bool isVPBROADCASTB(unsigned Opcode);
1126bool isCVTPI2PD(unsigned Opcode);
1127bool isVPERMI2B(unsigned Opcode);
1128bool isVPMINSB(unsigned Opcode);
1129bool isLAR(unsigned Opcode);
1130bool isINVLPGB(unsigned Opcode);
1131bool isTLBSYNC(unsigned Opcode);
1132bool isFDIVP(unsigned Opcode);
1133bool isVPSRLW(unsigned Opcode);
1134bool isVRCP28SS(unsigned Opcode);
1135bool isVMOVHPS(unsigned Opcode);
1136bool isVPMACSSDD(unsigned Opcode);
1137bool isPEXT(unsigned Opcode);
1138bool isVMAXBF16(unsigned Opcode);
1139bool isVRSQRT14SD(unsigned Opcode);
1140bool isVPDPWSSD(unsigned Opcode);
1141bool isVFMSUB231SD(unsigned Opcode);
1142bool isVPMOVZXWQ(unsigned Opcode);
1143bool isXORPD(unsigned Opcode);
1144bool isVMOVDQA(unsigned Opcode);
1145bool isVFNMSUB213SD(unsigned Opcode);
1146bool isVMINPS(unsigned Opcode);
1147bool isVFMSUB231PS(unsigned Opcode);
1148bool isVPCOMPRESSB(unsigned Opcode);
1149bool isVPCMPEQQ(unsigned Opcode);
1150bool isVRCPSS(unsigned Opcode);
1151bool isVSCATTERPF1DPS(unsigned Opcode);
1152bool isVPHADDUBW(unsigned Opcode);
1153bool isVSUBPD(unsigned Opcode);
1154bool isVPSCATTERQQ(unsigned Opcode);
1155bool isVCVTW2PH(unsigned Opcode);
1156bool isVFMADDCPH(unsigned Opcode);
1157bool isVPACKUSDW(unsigned Opcode);
1158bool isVSCALEFSS(unsigned Opcode);
1159bool isAESIMC(unsigned Opcode);
1160bool isVRCP28PS(unsigned Opcode);
1161bool isAAND(unsigned Opcode);
1162bool isDAA(unsigned Opcode);
1163bool isKTESTW(unsigned Opcode);
1164bool isVCVTPD2UDQ(unsigned Opcode);
1165bool isVPADDQ(unsigned Opcode);
1166bool isPALIGNR(unsigned Opcode);
1167bool isPMAXUW(unsigned Opcode);
1168bool isVFMADDSD(unsigned Opcode);
1169bool isPFMAX(unsigned Opcode);
1170bool isVPOR(unsigned Opcode);
1171bool isVPSUBB(unsigned Opcode);
1172bool isVPAVGB(unsigned Opcode);
1173bool isINSB(unsigned Opcode);
1174bool isFYL2X(unsigned Opcode);
1175bool isVFNMSUB132PD(unsigned Opcode);
1176bool isVFNMSUBPS(unsigned Opcode);
1177bool isVFMADD231PS(unsigned Opcode);
1178bool isVCVTTSS2SI(unsigned Opcode);
1179bool isTCMMRLFP16PS(unsigned Opcode);
1180bool isFCOMPP(unsigned Opcode);
1181bool isMOVD(unsigned Opcode);
1182bool isMOVBE(unsigned Opcode);
1183bool isVP2INTERSECTD(unsigned Opcode);
1184bool isVPMULLQ(unsigned Opcode);
1185bool isVSCALEFPS(unsigned Opcode);
1186bool isVPMACSDQH(unsigned Opcode);
1187bool isVPTESTNMD(unsigned Opcode);
1188bool isFCOMP(unsigned Opcode);
1189bool isPREFETCHWT1(unsigned Opcode);
1190bool isVCMPSD(unsigned Opcode);
1191bool isSGDTD(unsigned Opcode);
1192bool isWRUSSD(unsigned Opcode);
1193bool isFSUBP(unsigned Opcode);
1194bool isVUNPCKLPS(unsigned Opcode);
1195bool isVFNMSUB213SS(unsigned Opcode);
1196bool isROUNDPD(unsigned Opcode);
1197bool isVPMAXSW(unsigned Opcode);
1198bool isVCVTTPH2DQ(unsigned Opcode);
1199bool isVPUNPCKLWD(unsigned Opcode);
1200bool isKSHIFTLD(unsigned Opcode);
1201bool isTCVTROWPS2BF16H(unsigned Opcode);
1202bool isVFMADD231SD(unsigned Opcode);
1203bool isADDPS(unsigned Opcode);
1204bool isVPSLLVD(unsigned Opcode);
1205bool isVFNMADD132SH(unsigned Opcode);
1206bool isVMOVNTPS(unsigned Opcode);
1207bool isVCVTPD2DQ(unsigned Opcode);
1208bool isVPXOR(unsigned Opcode);
1209bool isSTMXCSR(unsigned Opcode);
1210bool isVRCP14SS(unsigned Opcode);
1211bool isUD2(unsigned Opcode);
1212bool isVPOPCNTW(unsigned Opcode);
1213bool isVRSQRTSH(unsigned Opcode);
1214bool isVSCATTERPF0DPD(unsigned Opcode);
1215bool isVFMADDPS(unsigned Opcode);
1216bool isXSAVEC64(unsigned Opcode);
1217bool isVPMADDUBSW(unsigned Opcode);
1218bool isVPMOVZXDQ(unsigned Opcode);
1219bool isVRCP14PS(unsigned Opcode);
1220bool isVSQRTSH(unsigned Opcode);
1221bool isTCVTROWD2PS(unsigned Opcode);
1222bool isLOOP(unsigned Opcode);
1223bool isSTUI(unsigned Opcode);
1224bool isVCVTTPS2UDQ(unsigned Opcode);
1225bool isXABORT(unsigned Opcode);
1226bool isVCOMPRESSPS(unsigned Opcode);
1227bool isVCVTTBF162IUBS(unsigned Opcode);
1228bool isVPADDW(unsigned Opcode);
1229bool isVPSIGND(unsigned Opcode);
1230bool isVRNDSCALEPS(unsigned Opcode);
1231bool isVPHADDUWD(unsigned Opcode);
1232bool isVCVT2PH2HF8S(unsigned Opcode);
1233bool isVDBPSADBW(unsigned Opcode);
1234bool isPSLLW(unsigned Opcode);
1235bool isVPMOVQD(unsigned Opcode);
1236bool isVINSERTI64X4(unsigned Opcode);
1237bool isVPERMI2PS(unsigned Opcode);
1238bool isVMULPH(unsigned Opcode);
1239bool isVPCMPUQ(unsigned Opcode);
1240bool isVCVTUSI2SD(unsigned Opcode);
1241bool isKXNORW(unsigned Opcode);
1242bool isBLCIC(unsigned Opcode);
1243bool isVFNMADD213SD(unsigned Opcode);
1244bool isVMOVLPS(unsigned Opcode);
1245bool isVPMACSWW(unsigned Opcode);
1246bool isPCONFIG(unsigned Opcode);
1247bool isPANDN(unsigned Opcode);
1248bool isVGETEXPPD(unsigned Opcode);
1249bool isVPSRLVQ(unsigned Opcode);
1250bool isUD1(unsigned Opcode);
1251bool isPMAXSB(unsigned Opcode);
1252bool isVPROLQ(unsigned Opcode);
1253bool isVPSRLD(unsigned Opcode);
1254bool isVSCATTERPF1QPD(unsigned Opcode);
1255bool isINT3(unsigned Opcode);
1256bool isXRSTORS64(unsigned Opcode);
1257bool isCVTSD2SI(unsigned Opcode);
1258bool isVMAXSS(unsigned Opcode);
1259bool isVPMINUB(unsigned Opcode);
1260bool isKXNORQ(unsigned Opcode);
1261bool isFLD(unsigned Opcode);
1262bool isVSHUFI32X4(unsigned Opcode);
1263bool isSAHF(unsigned Opcode);
1264bool isPFRSQRT(unsigned Opcode);
1265bool isSHRD(unsigned Opcode);
1266bool isSYSEXIT(unsigned Opcode);
1267bool isXSAVE64(unsigned Opcode);
1268bool isVPMAXSD(unsigned Opcode);
1269bool isCVTTSD2SI(unsigned Opcode);
1270bool isVCVTTSS2SIS(unsigned Opcode);
1271bool isPMOVMSKB(unsigned Opcode);
1272bool isVRANGEPS(unsigned Opcode);
1273bool isVADDSUBPS(unsigned Opcode);
1274bool isVBROADCASTI128(unsigned Opcode);
1275bool isPADDUSB(unsigned Opcode);
1276bool isENCODEKEY128(unsigned Opcode);
1277bool isOR(unsigned Opcode);
1278bool isSTOSW(unsigned Opcode);
1279bool isVCVTTPD2UQQS(unsigned Opcode);
1280bool isPAVGW(unsigned Opcode);
1281bool isVCVTPD2PH(unsigned Opcode);
1282bool isSHLX(unsigned Opcode);
1283bool isVCVTSH2SD(unsigned Opcode);
1284bool isVFMADD231SS(unsigned Opcode);
1285bool isMOVNTSD(unsigned Opcode);
1286bool isFLDPI(unsigned Opcode);
1287bool isVCVTUSI2SS(unsigned Opcode);
1288bool isPMOVSXBD(unsigned Opcode);
1289bool isVPRORVQ(unsigned Opcode);
1290bool isVPERMT2D(unsigned Opcode);
1291bool isADDSS(unsigned Opcode);
1292bool isAADD(unsigned Opcode);
1293bool isVPSRLVW(unsigned Opcode);
1294bool isVRSQRTPH(unsigned Opcode);
1295bool isVLDDQU(unsigned Opcode);
1296bool isKMOVD(unsigned Opcode);
1297bool isENCLV(unsigned Opcode);
1298bool isENCLU(unsigned Opcode);
1299bool isPREFETCHT1(unsigned Opcode);
1300bool isRSQRTPS(unsigned Opcode);
1301bool isVCVTTSH2USI(unsigned Opcode);
1302bool isPADDB(unsigned Opcode);
1303bool isVMASKMOVDQU(unsigned Opcode);
1304bool isPUNPCKLBW(unsigned Opcode);
1305bool isMOV(unsigned Opcode);
1306bool isVCVTTPH2IUBS(unsigned Opcode);
1307bool isMUL(unsigned Opcode);
1308bool isRCL(unsigned Opcode);
1309bool isVRCPSH(unsigned Opcode);
1310bool isPFCMPEQ(unsigned Opcode);
1311bool isMONITOR(unsigned Opcode);
1312bool isFDIVR(unsigned Opcode);
1313bool isPFRCP(unsigned Opcode);
1314bool isPMINSD(unsigned Opcode);
1315bool isVSHUFF32X4(unsigned Opcode);
1316bool isKTESTQ(unsigned Opcode);
1317bool isVCVTTPD2DQ(unsigned Opcode);
1318bool isVPSLLVW(unsigned Opcode);
1319bool isTDPBSUD(unsigned Opcode);
1320bool isVPMINUQ(unsigned Opcode);
1321bool isFIADD(unsigned Opcode);
1322bool isFCMOVNU(unsigned Opcode);
1323bool isVHSUBPD(unsigned Opcode);
1324bool isKSHIFTRQ(unsigned Opcode);
1325bool isMOVUPS(unsigned Opcode);
1326bool isVMCALL(unsigned Opcode);
1327bool isXADD(unsigned Opcode);
1328bool isXRSTOR(unsigned Opcode);
1329bool isVGATHERPF1DPD(unsigned Opcode);
1330bool isRCR(unsigned Opcode);
1331bool isFNSTCW(unsigned Opcode);
1332bool isVPMOVSDW(unsigned Opcode);
1333bool isVFMSUB132SH(unsigned Opcode);
1334bool isVPCONFLICTQ(unsigned Opcode);
1335bool isSWAPGS(unsigned Opcode);
1336bool isVPMOVQ2M(unsigned Opcode);
1337bool isVPSRAVW(unsigned Opcode);
1338bool isSHA256MSG2(unsigned Opcode);
1339bool isDIVSD(unsigned Opcode);
1340bool isPCMPGTB(unsigned Opcode);
1341bool isMOVDQA(unsigned Opcode);
1342bool isVAESENCLAST(unsigned Opcode);
1343bool isKXORW(unsigned Opcode);
1344bool isLIDTW(unsigned Opcode);
1345bool isPMULHW(unsigned Opcode);
1346bool isVINSERTI32X8(unsigned Opcode);
1347bool isVRCPPS(unsigned Opcode);
1348bool isVRSQRTBF16(unsigned Opcode);
1349bool isVGATHERQPS(unsigned Opcode);
1350bool isCTESTCC(unsigned Opcode);
1351bool isPMADDWD(unsigned Opcode);
1352bool isUCOMISS(unsigned Opcode);
1353bool isXGETBV(unsigned Opcode);
1354bool isVCVTPD2QQ(unsigned Opcode);
1355bool isVGETEXPPS(unsigned Opcode);
1356bool isFISTP(unsigned Opcode);
1357bool isVINSERTF64X4(unsigned Opcode);
1358bool isVMOVDQU16(unsigned Opcode);
1359bool isVFMADD132PH(unsigned Opcode);
1360bool isVFMSUBADD213PS(unsigned Opcode);
1361bool isVMOVDQU32(unsigned Opcode);
1362bool isFUCOM(unsigned Opcode);
1363bool isVFNMADD213BF16(unsigned Opcode);
1364bool isHADDPS(unsigned Opcode);
1365bool isCMP(unsigned Opcode);
1366bool isCVTTPS2PI(unsigned Opcode);
1367bool isIRETQ(unsigned Opcode);
1368bool isPF2IW(unsigned Opcode);
1369bool isPSHUFD(unsigned Opcode);
1370bool isVDPPD(unsigned Opcode);
1371bool isPSHUFHW(unsigned Opcode);
1372bool isRMPADJUST(unsigned Opcode);
1373bool isPI2FW(unsigned Opcode);
1374bool isVCVTTPH2QQ(unsigned Opcode);
1375bool isDIVPD(unsigned Opcode);
1376bool isCLFLUSH(unsigned Opcode);
1377bool isVPMINUW(unsigned Opcode);
1378bool isIN(unsigned Opcode);
1379bool isWRPKRU(unsigned Opcode);
1380bool isINSERTPS(unsigned Opcode);
1381bool isAAM(unsigned Opcode);
1382bool isVPHADDUDQ(unsigned Opcode);
1383bool isVSHA512MSG1(unsigned Opcode);
1384bool isDIVPS(unsigned Opcode);
1385bool isKNOTB(unsigned Opcode);
1386bool isBLSFILL(unsigned Opcode);
1387bool isVPCMPGTQ(unsigned Opcode);
1388bool isMINSD(unsigned Opcode);
1389bool isFPREM(unsigned Opcode);
1390bool isVPUNPCKHQDQ(unsigned Opcode);
1391bool isMINPD(unsigned Opcode);
1392bool isVCVTTPD2QQ(unsigned Opcode);
1393bool isVFMSUBPD(unsigned Opcode);
1394bool isV4FMADDSS(unsigned Opcode);
1395bool isCPUID(unsigned Opcode);
1396bool isSETCC(unsigned Opcode);
1397bool isVPDPWUUD(unsigned Opcode);
1398bool isVCVTTPS2IUBS(unsigned Opcode);
1399bool isPMOVSXDQ(unsigned Opcode);
1400bool isMWAIT(unsigned Opcode);
1401bool isVPEXTRB(unsigned Opcode);
1402bool isINVVPID(unsigned Opcode);
1403bool isVPSHUFD(unsigned Opcode);
1404bool isVMINBF16(unsigned Opcode);
1405bool isMOVLPS(unsigned Opcode);
1406bool isVBLENDMPS(unsigned Opcode);
1407bool isPMULLW(unsigned Opcode);
1408bool isVCVTSH2SI(unsigned Opcode);
1409bool isVPMOVSXWQ(unsigned Opcode);
1410bool isFNSTENV(unsigned Opcode);
1411bool isVCVT2PH2BF8(unsigned Opcode);
1412bool isVPERMI2PD(unsigned Opcode);
1413bool isMAXSS(unsigned Opcode);
1414bool isCWDE(unsigned Opcode);
1415bool isVBROADCASTI32X8(unsigned Opcode);
1416bool isINT(unsigned Opcode);
1417bool isENCLS(unsigned Opcode);
1418bool isMOVNTQ(unsigned Opcode);
1419bool isVDIVSH(unsigned Opcode);
1420bool isMOVHLPS(unsigned Opcode);
1421bool isVPMASKMOVD(unsigned Opcode);
1422bool isVMOVSD(unsigned Opcode);
1423bool isVPMINUD(unsigned Opcode);
1424bool isVPCMPISTRM(unsigned Opcode);
1425bool isVGETMANTSD(unsigned Opcode);
1426bool isKSHIFTRW(unsigned Opcode);
1427bool isAESDECLAST(unsigned Opcode);
1428bool isVPTESTMB(unsigned Opcode);
1429bool isVFNMSUB231BF16(unsigned Opcode);
1430bool isVMPTRST(unsigned Opcode);
1431bool isLLDT(unsigned Opcode);
1432bool isMOVSB(unsigned Opcode);
1433bool isTILELOADD(unsigned Opcode);
1434bool isKTESTB(unsigned Opcode);
1435bool isMOVUPD(unsigned Opcode);
1436bool isLKGS(unsigned Opcode);
1437bool isSGDTW(unsigned Opcode);
1438bool isDIVSS(unsigned Opcode);
1439bool isPUNPCKHQDQ(unsigned Opcode);
1440bool isVFMADD213SD(unsigned Opcode);
1441bool isKXORD(unsigned Opcode);
1442bool isVPMOVB2M(unsigned Opcode);
1443bool isVMREAD(unsigned Opcode);
1444bool isVPDPWSSDS(unsigned Opcode);
1445bool isTILERELEASE(unsigned Opcode);
1446bool isVUCOMXSH(unsigned Opcode);
1447bool isCLFLUSHOPT(unsigned Opcode);
1448bool isDAS(unsigned Opcode);
1449bool isVSCALEFPH(unsigned Opcode);
1450bool isVSUBSD(unsigned Opcode);
1451bool isVCOMISS(unsigned Opcode);
1452bool isVMULBF16(unsigned Opcode);
1453bool isORPS(unsigned Opcode);
1454bool isTDPFP16PS(unsigned Opcode);
1455bool isVMAXPD(unsigned Opcode);
1456bool isVPMOVWB(unsigned Opcode);
1457bool isVEXP2PS(unsigned Opcode);
1458bool isVPGATHERDQ(unsigned Opcode);
1459bool isVPSRAVQ(unsigned Opcode);
1460bool isPCMPISTRI(unsigned Opcode);
1461bool isVFMSUB231PD(unsigned Opcode);
1462bool isRDMSR(unsigned Opcode);
1463bool isKORTESTD(unsigned Opcode);
1464bool isVPBLENDMW(unsigned Opcode);
1465bool isPSHUFB(unsigned Opcode);
1466bool isVDPBF16PS(unsigned Opcode);
1467bool isTDPBF16PS(unsigned Opcode);
1468bool isFCMOVE(unsigned Opcode);
1469bool isVFMADD231BF16(unsigned Opcode);
1470bool isCMPSS(unsigned Opcode);
1471bool isMASKMOVDQU(unsigned Opcode);
1472bool isSARX(unsigned Opcode);
1473bool isVPDPWUSDS(unsigned Opcode);
1474bool isSGDT(unsigned Opcode);
1475bool isVFMULCPH(unsigned Opcode);
1476bool isURDMSR(unsigned Opcode);
1477bool isKUNPCKWD(unsigned Opcode);
1478bool isVSCALEFBF16(unsigned Opcode);
1479bool isCVTPS2PD(unsigned Opcode);
1480bool isFBSTP(unsigned Opcode);
1481bool isPSUBQ(unsigned Opcode);
1482bool isFXSAVE64(unsigned Opcode);
1483bool isKMOVW(unsigned Opcode);
1484bool isBTS(unsigned Opcode);
1485bool isVPHADDBQ(unsigned Opcode);
1486bool isFRSTOR(unsigned Opcode);
1487bool isVFMSUB132PD(unsigned Opcode);
1488bool isPMULLD(unsigned Opcode);
1489bool isSHA1MSG2(unsigned Opcode);
1490bool isJECXZ(unsigned Opcode);
1491bool isVCVTUDQ2PS(unsigned Opcode);
1492bool isAESENC(unsigned Opcode);
1493bool isVMINMAXPS(unsigned Opcode);
1494bool isPSIGNW(unsigned Opcode);
1495bool isUNPCKLPD(unsigned Opcode);
1496bool isPUSHP(unsigned Opcode);
1497bool isBLSI(unsigned Opcode);
1498bool isVPTESTNMB(unsigned Opcode);
1499bool isWRUSSQ(unsigned Opcode);
1500bool isVGF2P8MULB(unsigned Opcode);
1501bool isVPUNPCKLBW(unsigned Opcode);
1502bool isVRANGESD(unsigned Opcode);
1503bool isCLD(unsigned Opcode);
1504bool isVSCALEFPD(unsigned Opcode);
1505bool isVCOMXSS(unsigned Opcode);
1506bool isVPERMQ(unsigned Opcode);
1507bool isVPSHLDVW(unsigned Opcode);
1508bool isROR(unsigned Opcode);
1509bool isVFMADDSUB132PH(unsigned Opcode);
1510bool isDEC(unsigned Opcode);
1511bool isVGETEXPSH(unsigned Opcode);
1512bool isAESDEC(unsigned Opcode);
1513bool isKORD(unsigned Opcode);
1514bool isTILELOADDT1(unsigned Opcode);
1515bool isVPMULHW(unsigned Opcode);
1516bool isVMASKMOVPS(unsigned Opcode);
1517bool isPMOVZXDQ(unsigned Opcode);
1518bool isVCVTPS2PH(unsigned Opcode);
1519bool isCVTDQ2PD(unsigned Opcode);
1520bool isVCVTSD2SS(unsigned Opcode);
1521bool isVFMSUB213PH(unsigned Opcode);
1522bool isVPROTB(unsigned Opcode);
1523bool isPINSRD(unsigned Opcode);
1524bool isVMXON(unsigned Opcode);
1525bool isVFCMULCSH(unsigned Opcode);
1526bool isVFMULCSH(unsigned Opcode);
1527bool isVRANGEPD(unsigned Opcode);
1528bool isCMC(unsigned Opcode);
1529bool isVFNMADD231BF16(unsigned Opcode);
1530bool isSHA256MSG1(unsigned Opcode);
1531bool isFLD1(unsigned Opcode);
1532bool isCMPPS(unsigned Opcode);
1533bool isVPAVGW(unsigned Opcode);
1534bool isVFMADD213SH(unsigned Opcode);
1535bool isVPCMPESTRMQ(unsigned Opcode);
1536bool isVPINSRQ(unsigned Opcode);
1537bool isMOVABS(unsigned Opcode);
1538bool isVPSHAQ(unsigned Opcode);
1539bool isRDTSCP(unsigned Opcode);
1540bool isVFNMADD231SS(unsigned Opcode);
1541bool isTEST(unsigned Opcode);
1542bool isVPERMD(unsigned Opcode);
1543bool isVBCSTNESH2PS(unsigned Opcode);
1544bool isVGATHERPF0QPD(unsigned Opcode);
1545bool isVPERM2I128(unsigned Opcode);
1546bool isVMPSADBW(unsigned Opcode);
1547bool isVFNMSUB231PD(unsigned Opcode);
1548bool isPADDSB(unsigned Opcode);
1549bool isMWAITX(unsigned Opcode);
1550bool isMONITORX(unsigned Opcode);
1551bool isVPEXPANDD(unsigned Opcode);
1552bool isVFRCZPD(unsigned Opcode);
1553bool isVRCPPH(unsigned Opcode);
1554bool isFEMMS(unsigned Opcode);
1555bool isVSCATTERQPD(unsigned Opcode);
1556bool isVMOVW(unsigned Opcode);
1557bool isVPBROADCASTD(unsigned Opcode);
1558bool isSTOSB(unsigned Opcode);
1559bool isFUCOMI(unsigned Opcode);
1560bool isVBROADCASTI64X4(unsigned Opcode);
1561bool isFCMOVU(unsigned Opcode);
1562bool isPSHUFLW(unsigned Opcode);
1563bool isCVTPI2PS(unsigned Opcode);
1564bool isVCVTTPD2UDQS(unsigned Opcode);
1565bool isSYSCALL(unsigned Opcode);
1566bool isVFMADD231SH(unsigned Opcode);
1567bool isVPOPCNTB(unsigned Opcode);
1568bool isPMOVZXBW(unsigned Opcode);
1569bool isVCVTDQ2PS(unsigned Opcode);
1570bool isPSUBD(unsigned Opcode);
1571bool isVPCMPEQW(unsigned Opcode);
1572bool isMOVSW(unsigned Opcode);
1573bool isVSM3RNDS2(unsigned Opcode);
1574bool isVPMOVUSQD(unsigned Opcode);
1575bool isCVTTPD2DQ(unsigned Opcode);
1576bool isVPEXPANDW(unsigned Opcode);
1577bool isVUCOMISH(unsigned Opcode);
1578bool isVZEROALL(unsigned Opcode);
1579bool isVPAND(unsigned Opcode);
1580bool isPMULDQ(unsigned Opcode);
1581bool isVPSHUFHW(unsigned Opcode);
1582bool isVPALIGNR(unsigned Opcode);
1583bool isSQRTSD(unsigned Opcode);
1584bool isVCVTTPH2UDQ(unsigned Opcode);
1585bool isVGETEXPPH(unsigned Opcode);
1586bool isADDPD(unsigned Opcode);
1587bool isVFNMADDPD(unsigned Opcode);
1588bool isSTTILECFG(unsigned Opcode);
1589bool isVMINPD(unsigned Opcode);
1590bool isSHA1RNDS4(unsigned Opcode);
1591bool isPBLENDVB(unsigned Opcode);
1592bool isVBROADCASTF128(unsigned Opcode);
1593bool isVPSHRDQ(unsigned Opcode);
1594bool isVAESIMC(unsigned Opcode);
1595bool isCOMISD(unsigned Opcode);
1596bool isVMOVSH(unsigned Opcode);
1597bool isPFSUBR(unsigned Opcode);
1598bool isRDSSPD(unsigned Opcode);
1599bool isWAIT(unsigned Opcode);
1600bool isVFPCLASSSS(unsigned Opcode);
1601bool isPCMPGTD(unsigned Opcode);
1602bool isVGATHERPF0QPS(unsigned Opcode);
1603bool isBLENDVPS(unsigned Opcode);
1604bool isVBROADCASTF32X4(unsigned Opcode);
1605bool isVMOVLPD(unsigned Opcode);
1606bool isVMOVQ(unsigned Opcode);
1607bool isVPMADD52LUQ(unsigned Opcode);
1608bool isVMOVDQU(unsigned Opcode);
1609bool isAESENC128KL(unsigned Opcode);
1610bool isVFMADDSUB231PS(unsigned Opcode);
1611bool isVFNMSUB213PD(unsigned Opcode);
1612bool isVPCONFLICTD(unsigned Opcode);
1613bool isVFMADDSUB213PH(unsigned Opcode);
1614bool isVPHSUBSW(unsigned Opcode);
1615bool isPUNPCKHDQ(unsigned Opcode);
1616bool isVSHUFI64X2(unsigned Opcode);
1617bool isVFMSUBSD(unsigned Opcode);
1618bool isVPORD(unsigned Opcode);
1619bool isRCPPS(unsigned Opcode);
1620bool isVEXTRACTI128(unsigned Opcode);
1621bool isVCVT2PH2BF8S(unsigned Opcode);
1622bool isVPSHRDVW(unsigned Opcode);
1623bool isVUNPCKLPD(unsigned Opcode);
1624bool isVPSRAVD(unsigned Opcode);
1625bool isVMULSH(unsigned Opcode);
1626bool isMOVNTSS(unsigned Opcode);
1627bool isSTI(unsigned Opcode);
1628bool isVSM4RNDS4(unsigned Opcode);
1629bool isVMCLEAR(unsigned Opcode);
1630bool isVPMADD52HUQ(unsigned Opcode);
1631bool isLIDT(unsigned Opcode);
1632bool isPUSH2(unsigned Opcode);
1633bool isRDPKRU(unsigned Opcode);
1634bool isVCVTPS2IUBS(unsigned Opcode);
1635bool isXSAVES64(unsigned Opcode);
1636bool isVPCMPB(unsigned Opcode);
1637bool isVFMSUB231BF16(unsigned Opcode);
1638bool isFINCSTP(unsigned Opcode);
1639bool isKORQ(unsigned Opcode);
1640bool isRDPMC(unsigned Opcode);
1641bool isVEXTRACTF128(unsigned Opcode);
1642bool isMOVMSKPD(unsigned Opcode);
1643bool isVFMSUB231SH(unsigned Opcode);
1644bool isVPSHLB(unsigned Opcode);
1645bool isXCRYPTCBC(unsigned Opcode);
1646bool isSHL(unsigned Opcode);
1647bool isAXOR(unsigned Opcode);
1648bool isVINSERTI64X2(unsigned Opcode);
1649bool isSYSRETQ(unsigned Opcode);
1650bool isVSCATTERPF0QPD(unsigned Opcode);
1651bool isVFMSUB213SH(unsigned Opcode);
1652bool isVPMOVQW(unsigned Opcode);
1653bool isVREDUCEPD(unsigned Opcode);
1654bool isNOT(unsigned Opcode);
1655bool isLWPINS(unsigned Opcode);
1656bool isVSCATTERDPS(unsigned Opcode);
1657bool isVPMOVM2W(unsigned Opcode);
1658bool isVFNMADD132PS(unsigned Opcode);
1659bool isMOVNTPS(unsigned Opcode);
1660bool isVRSQRTSS(unsigned Opcode);
1661bool isKMOVB(unsigned Opcode);
1662bool isCVTSD2SS(unsigned Opcode);
1663bool isVBROADCASTF64X2(unsigned Opcode);
1664bool isVDIVBF16(unsigned Opcode);
1665bool isMOVNTPD(unsigned Opcode);
1666bool isMAXSD(unsigned Opcode);
1667bool isCMPPD(unsigned Opcode);
1668bool isVPCMPESTRM(unsigned Opcode);
1669bool isVFMSUB132PS(unsigned Opcode);
1670bool isVCOMISH(unsigned Opcode);
1671bool isF2XM1(unsigned Opcode);
1672bool isSQRTPD(unsigned Opcode);
1673bool isVFMSUBADDPS(unsigned Opcode);
1674bool isFXTRACT(unsigned Opcode);
1675bool isVP4DPWSSD(unsigned Opcode);
1676bool isTDPBHF8PS(unsigned Opcode);
1677bool isVFMSUBADDPD(unsigned Opcode);
1678bool isVBCSTNEBF162PS(unsigned Opcode);
1679bool isVPGATHERQQ(unsigned Opcode);
1680bool isPCMPEQB(unsigned Opcode);
1681bool isTILESTORED(unsigned Opcode);
1682bool isBLSMSK(unsigned Opcode);
1683bool isVCVTTPS2DQ(unsigned Opcode);
1684bool isVFPCLASSBF16(unsigned Opcode);
1685bool isVRNDSCALEPD(unsigned Opcode);
1686bool isVMLOAD(unsigned Opcode);
1687bool isVPTERNLOGQ(unsigned Opcode);
1688bool isKXNORD(unsigned Opcode);
1689bool isFXSAVE(unsigned Opcode);
1690bool isVUNPCKHPD(unsigned Opcode);
1691bool isCVTPS2DQ(unsigned Opcode);
1692bool isTMMULTF32PS(unsigned Opcode);
1693bool isVFMSUB213SS(unsigned Opcode);
1694bool isVPOPCNTD(unsigned Opcode);
1695bool isSALC(unsigned Opcode);
1696bool isV4FNMADDSS(unsigned Opcode);
1697bool isXCRYPTOFB(unsigned Opcode);
1698bool isVORPD(unsigned Opcode);
1699bool isLSL(unsigned Opcode);
1700bool isXCRYPTCFB(unsigned Opcode);
1701bool isVGETEXPSS(unsigned Opcode);
1702bool isPSLLDQ(unsigned Opcode);
1703bool isVPDPBUUD(unsigned Opcode);
1704bool isVMXOFF(unsigned Opcode);
1705bool isBLSIC(unsigned Opcode);
1706bool isMOVLHPS(unsigned Opcode);
1707bool isVMOVRSQ(unsigned Opcode);
1708bool isVFNMSUBSD(unsigned Opcode);
1709bool isVCVTPH2IUBS(unsigned Opcode);
1710bool isVFPCLASSSH(unsigned Opcode);
1711bool isVPSHLQ(unsigned Opcode);
1712bool isVROUNDPS(unsigned Opcode);
1713bool isVSCATTERPF0QPS(unsigned Opcode);
1714bool isERETS(unsigned Opcode);
1715bool isVPERMI2D(unsigned Opcode);
1716bool isFUCOMP(unsigned Opcode);
1717bool isVCVTTPS2QQ(unsigned Opcode);
1718bool isPUSHFD(unsigned Opcode);
1719bool isVPABSD(unsigned Opcode);
1720bool isKORB(unsigned Opcode);
1721bool isVRCP28PD(unsigned Opcode);
1722bool isVROUNDSS(unsigned Opcode);
1723bool isVCVTSD2USI(unsigned Opcode);
1724bool isVPABSB(unsigned Opcode);
1725bool isPMAXUD(unsigned Opcode);
1726bool isVPERMPD(unsigned Opcode);
1727bool isVPMULHUW(unsigned Opcode);
1728bool isFCHS(unsigned Opcode);
1729bool isVPBLENDMB(unsigned Opcode);
1730bool isVGETMANTSS(unsigned Opcode);
1731bool isVPSLLW(unsigned Opcode);
1732bool isVDIVPD(unsigned Opcode);
1733bool isBLCMSK(unsigned Opcode);
1734bool isFDIV(unsigned Opcode);
1735bool isRSQRTSS(unsigned Opcode);
1736bool isPOR(unsigned Opcode);
1737bool isVMOVDQA32(unsigned Opcode);
1738bool isVPHADDUWQ(unsigned Opcode);
1739bool isPSRAD(unsigned Opcode);
1740bool isPREFETCHW(unsigned Opcode);
1741bool isFIDIVR(unsigned Opcode);
1742bool isMOVHPS(unsigned Opcode);
1743bool isVFNMSUB231PH(unsigned Opcode);
1744bool isUNPCKLPS(unsigned Opcode);
1745bool isVPSIGNB(unsigned Opcode);
1746bool isSAVEPREVSSP(unsigned Opcode);
1747bool isVSCALEFSD(unsigned Opcode);
1748bool isFSIN(unsigned Opcode);
1749bool isSCASQ(unsigned Opcode);
1750bool isVCVTTPD2QQS(unsigned Opcode);
1751bool isPCMPGTW(unsigned Opcode);
1752bool isMULX(unsigned Opcode);
1753bool isVPMAXUW(unsigned Opcode);
1754bool isPAUSE(unsigned Opcode);
1755bool isMOVQ2DQ(unsigned Opcode);
1756bool isVPABSW(unsigned Opcode);
1757bool isVPSUBQ(unsigned Opcode);
1758bool isVPCOMPRESSD(unsigned Opcode);
1759bool isVPMOVUSQW(unsigned Opcode);
1760bool isBLENDVPD(unsigned Opcode);
1761bool isVFNMADD132BF16(unsigned Opcode);
1762bool isVPMOVQB(unsigned Opcode);
1763bool isVBLENDVPS(unsigned Opcode);
1764bool isKSHIFTLQ(unsigned Opcode);
1765bool isPMOVSXWD(unsigned Opcode);
1766bool isPHSUBSW(unsigned Opcode);
1767bool isPSRLQ(unsigned Opcode);
1768bool isVCVTPH2DQ(unsigned Opcode);
1769bool isPCMPESTRIQ(unsigned Opcode);
1770bool isFISUB(unsigned Opcode);
1771bool isVCVTPS2UDQ(unsigned Opcode);
1772bool isVMOVDDUP(unsigned Opcode);
1773bool isPCMPEQD(unsigned Opcode);
1774bool isVRSQRT28SD(unsigned Opcode);
1775bool isTDPHBF8PS(unsigned Opcode);
1776bool isVPOPCNTQ(unsigned Opcode);
1777bool isLODSW(unsigned Opcode);
1778bool isKSHIFTRB(unsigned Opcode);
1779bool isVFNMADDPS(unsigned Opcode);
1780bool isCCMPCC(unsigned Opcode);
1781bool isFXRSTOR64(unsigned Opcode);
1782bool isVFMSUBADD213PD(unsigned Opcode);
1783bool isVSQRTPH(unsigned Opcode);
1784bool isPOPF(unsigned Opcode);
1785bool isVPSUBUSB(unsigned Opcode);
1786bool isTCVTROWPS2BF16L(unsigned Opcode);
1787bool isVPADDSW(unsigned Opcode);
1788bool isPREFETCHIT1(unsigned Opcode);
1789bool isVADDSUBPD(unsigned Opcode);
1790bool isKANDD(unsigned Opcode);
1791bool isPREFETCHRST2(unsigned Opcode);
1792bool isOUTSB(unsigned Opcode);
1793bool isFNSTSW(unsigned Opcode);
1794bool isPMINSB(unsigned Opcode);
1795
1796} // namespace llvm::X86
1797
1798#endif // GET_X86_MNEMONIC_TABLES_H
1799
1800#ifdef GET_X86_MNEMONIC_TABLES_CPP
1801#undef GET_X86_MNEMONIC_TABLES_CPP
1802
1803namespace llvm::X86 {
1804
1805bool isFSUBRP(unsigned Opcode) {
1806 return Opcode == SUBR_FPrST0;
1807}
1808
1809bool isVPDPBUSDS(unsigned Opcode) {
1810 switch (Opcode) {
1811 case VPDPBUSDSYrm:
1812 case VPDPBUSDSYrr:
1813 case VPDPBUSDSZ128rm:
1814 case VPDPBUSDSZ128rmb:
1815 case VPDPBUSDSZ128rmbk:
1816 case VPDPBUSDSZ128rmbkz:
1817 case VPDPBUSDSZ128rmk:
1818 case VPDPBUSDSZ128rmkz:
1819 case VPDPBUSDSZ128rr:
1820 case VPDPBUSDSZ128rrk:
1821 case VPDPBUSDSZ128rrkz:
1822 case VPDPBUSDSZ256rm:
1823 case VPDPBUSDSZ256rmb:
1824 case VPDPBUSDSZ256rmbk:
1825 case VPDPBUSDSZ256rmbkz:
1826 case VPDPBUSDSZ256rmk:
1827 case VPDPBUSDSZ256rmkz:
1828 case VPDPBUSDSZ256rr:
1829 case VPDPBUSDSZ256rrk:
1830 case VPDPBUSDSZ256rrkz:
1831 case VPDPBUSDSZrm:
1832 case VPDPBUSDSZrmb:
1833 case VPDPBUSDSZrmbk:
1834 case VPDPBUSDSZrmbkz:
1835 case VPDPBUSDSZrmk:
1836 case VPDPBUSDSZrmkz:
1837 case VPDPBUSDSZrr:
1838 case VPDPBUSDSZrrk:
1839 case VPDPBUSDSZrrkz:
1840 case VPDPBUSDSrm:
1841 case VPDPBUSDSrr:
1842 return true;
1843 }
1844 return false;
1845}
1846
1847bool isPUNPCKLWD(unsigned Opcode) {
1848 switch (Opcode) {
1849 case MMX_PUNPCKLWDrm:
1850 case MMX_PUNPCKLWDrr:
1851 case PUNPCKLWDrm:
1852 case PUNPCKLWDrr:
1853 return true;
1854 }
1855 return false;
1856}
1857
1858bool isVREDUCEBF16(unsigned Opcode) {
1859 switch (Opcode) {
1860 case VREDUCEBF16Z128rmbi:
1861 case VREDUCEBF16Z128rmbik:
1862 case VREDUCEBF16Z128rmbikz:
1863 case VREDUCEBF16Z128rmi:
1864 case VREDUCEBF16Z128rmik:
1865 case VREDUCEBF16Z128rmikz:
1866 case VREDUCEBF16Z128rri:
1867 case VREDUCEBF16Z128rrik:
1868 case VREDUCEBF16Z128rrikz:
1869 case VREDUCEBF16Z256rmbi:
1870 case VREDUCEBF16Z256rmbik:
1871 case VREDUCEBF16Z256rmbikz:
1872 case VREDUCEBF16Z256rmi:
1873 case VREDUCEBF16Z256rmik:
1874 case VREDUCEBF16Z256rmikz:
1875 case VREDUCEBF16Z256rri:
1876 case VREDUCEBF16Z256rrik:
1877 case VREDUCEBF16Z256rrikz:
1878 case VREDUCEBF16Zrmbi:
1879 case VREDUCEBF16Zrmbik:
1880 case VREDUCEBF16Zrmbikz:
1881 case VREDUCEBF16Zrmi:
1882 case VREDUCEBF16Zrmik:
1883 case VREDUCEBF16Zrmikz:
1884 case VREDUCEBF16Zrri:
1885 case VREDUCEBF16Zrrik:
1886 case VREDUCEBF16Zrrikz:
1887 return true;
1888 }
1889 return false;
1890}
1891
1892bool isPUNPCKLQDQ(unsigned Opcode) {
1893 switch (Opcode) {
1894 case PUNPCKLQDQrm:
1895 case PUNPCKLQDQrr:
1896 return true;
1897 }
1898 return false;
1899}
1900
1901bool isRDFSBASE(unsigned Opcode) {
1902 switch (Opcode) {
1903 case RDFSBASE:
1904 case RDFSBASE64:
1905 return true;
1906 }
1907 return false;
1908}
1909
1910bool isVPCMOV(unsigned Opcode) {
1911 switch (Opcode) {
1912 case VPCMOVYrmr:
1913 case VPCMOVYrrm:
1914 case VPCMOVYrrr:
1915 case VPCMOVYrrr_REV:
1916 case VPCMOVrmr:
1917 case VPCMOVrrm:
1918 case VPCMOVrrr:
1919 case VPCMOVrrr_REV:
1920 return true;
1921 }
1922 return false;
1923}
1924
1925bool isVDIVSD(unsigned Opcode) {
1926 switch (Opcode) {
1927 case VDIVSDZrm_Int:
1928 case VDIVSDZrmk_Int:
1929 case VDIVSDZrmkz_Int:
1930 case VDIVSDZrr_Int:
1931 case VDIVSDZrrb_Int:
1932 case VDIVSDZrrbk_Int:
1933 case VDIVSDZrrbkz_Int:
1934 case VDIVSDZrrk_Int:
1935 case VDIVSDZrrkz_Int:
1936 case VDIVSDrm_Int:
1937 case VDIVSDrr_Int:
1938 return true;
1939 }
1940 return false;
1941}
1942
1943bool isVCVTTPS2IBS(unsigned Opcode) {
1944 switch (Opcode) {
1945 case VCVTTPS2IBSZ128rm:
1946 case VCVTTPS2IBSZ128rmb:
1947 case VCVTTPS2IBSZ128rmbk:
1948 case VCVTTPS2IBSZ128rmbkz:
1949 case VCVTTPS2IBSZ128rmk:
1950 case VCVTTPS2IBSZ128rmkz:
1951 case VCVTTPS2IBSZ128rr:
1952 case VCVTTPS2IBSZ128rrk:
1953 case VCVTTPS2IBSZ128rrkz:
1954 case VCVTTPS2IBSZ256rm:
1955 case VCVTTPS2IBSZ256rmb:
1956 case VCVTTPS2IBSZ256rmbk:
1957 case VCVTTPS2IBSZ256rmbkz:
1958 case VCVTTPS2IBSZ256rmk:
1959 case VCVTTPS2IBSZ256rmkz:
1960 case VCVTTPS2IBSZ256rr:
1961 case VCVTTPS2IBSZ256rrk:
1962 case VCVTTPS2IBSZ256rrkz:
1963 case VCVTTPS2IBSZrm:
1964 case VCVTTPS2IBSZrmb:
1965 case VCVTTPS2IBSZrmbk:
1966 case VCVTTPS2IBSZrmbkz:
1967 case VCVTTPS2IBSZrmk:
1968 case VCVTTPS2IBSZrmkz:
1969 case VCVTTPS2IBSZrr:
1970 case VCVTTPS2IBSZrrb:
1971 case VCVTTPS2IBSZrrbk:
1972 case VCVTTPS2IBSZrrbkz:
1973 case VCVTTPS2IBSZrrk:
1974 case VCVTTPS2IBSZrrkz:
1975 return true;
1976 }
1977 return false;
1978}
1979
1980bool isVPEXTRW(unsigned Opcode) {
1981 switch (Opcode) {
1982 case VPEXTRWZmri:
1983 case VPEXTRWZrri:
1984 case VPEXTRWZrri_REV:
1985 case VPEXTRWmri:
1986 case VPEXTRWrri:
1987 case VPEXTRWrri_REV:
1988 return true;
1989 }
1990 return false;
1991}
1992
1993bool isLODSD(unsigned Opcode) {
1994 return Opcode == LODSL;
1995}
1996
1997bool isVPTESTNMQ(unsigned Opcode) {
1998 switch (Opcode) {
1999 case VPTESTNMQZ128rm:
2000 case VPTESTNMQZ128rmb:
2001 case VPTESTNMQZ128rmbk:
2002 case VPTESTNMQZ128rmk:
2003 case VPTESTNMQZ128rr:
2004 case VPTESTNMQZ128rrk:
2005 case VPTESTNMQZ256rm:
2006 case VPTESTNMQZ256rmb:
2007 case VPTESTNMQZ256rmbk:
2008 case VPTESTNMQZ256rmk:
2009 case VPTESTNMQZ256rr:
2010 case VPTESTNMQZ256rrk:
2011 case VPTESTNMQZrm:
2012 case VPTESTNMQZrmb:
2013 case VPTESTNMQZrmbk:
2014 case VPTESTNMQZrmk:
2015 case VPTESTNMQZrr:
2016 case VPTESTNMQZrrk:
2017 return true;
2018 }
2019 return false;
2020}
2021
2022bool isCVTSS2SD(unsigned Opcode) {
2023 switch (Opcode) {
2024 case CVTSS2SDrm_Int:
2025 case CVTSS2SDrr_Int:
2026 return true;
2027 }
2028 return false;
2029}
2030
2031bool isVGETMANTPD(unsigned Opcode) {
2032 switch (Opcode) {
2033 case VGETMANTPDZ128rmbi:
2034 case VGETMANTPDZ128rmbik:
2035 case VGETMANTPDZ128rmbikz:
2036 case VGETMANTPDZ128rmi:
2037 case VGETMANTPDZ128rmik:
2038 case VGETMANTPDZ128rmikz:
2039 case VGETMANTPDZ128rri:
2040 case VGETMANTPDZ128rrik:
2041 case VGETMANTPDZ128rrikz:
2042 case VGETMANTPDZ256rmbi:
2043 case VGETMANTPDZ256rmbik:
2044 case VGETMANTPDZ256rmbikz:
2045 case VGETMANTPDZ256rmi:
2046 case VGETMANTPDZ256rmik:
2047 case VGETMANTPDZ256rmikz:
2048 case VGETMANTPDZ256rri:
2049 case VGETMANTPDZ256rrik:
2050 case VGETMANTPDZ256rrikz:
2051 case VGETMANTPDZrmbi:
2052 case VGETMANTPDZrmbik:
2053 case VGETMANTPDZrmbikz:
2054 case VGETMANTPDZrmi:
2055 case VGETMANTPDZrmik:
2056 case VGETMANTPDZrmikz:
2057 case VGETMANTPDZrri:
2058 case VGETMANTPDZrrib:
2059 case VGETMANTPDZrribk:
2060 case VGETMANTPDZrribkz:
2061 case VGETMANTPDZrrik:
2062 case VGETMANTPDZrrikz:
2063 return true;
2064 }
2065 return false;
2066}
2067
2068bool isVMOVDQA64(unsigned Opcode) {
2069 switch (Opcode) {
2070 case VMOVDQA64Z128mr:
2071 case VMOVDQA64Z128mrk:
2072 case VMOVDQA64Z128rm:
2073 case VMOVDQA64Z128rmk:
2074 case VMOVDQA64Z128rmkz:
2075 case VMOVDQA64Z128rr:
2076 case VMOVDQA64Z128rr_REV:
2077 case VMOVDQA64Z128rrk:
2078 case VMOVDQA64Z128rrk_REV:
2079 case VMOVDQA64Z128rrkz:
2080 case VMOVDQA64Z128rrkz_REV:
2081 case VMOVDQA64Z256mr:
2082 case VMOVDQA64Z256mrk:
2083 case VMOVDQA64Z256rm:
2084 case VMOVDQA64Z256rmk:
2085 case VMOVDQA64Z256rmkz:
2086 case VMOVDQA64Z256rr:
2087 case VMOVDQA64Z256rr_REV:
2088 case VMOVDQA64Z256rrk:
2089 case VMOVDQA64Z256rrk_REV:
2090 case VMOVDQA64Z256rrkz:
2091 case VMOVDQA64Z256rrkz_REV:
2092 case VMOVDQA64Zmr:
2093 case VMOVDQA64Zmrk:
2094 case VMOVDQA64Zrm:
2095 case VMOVDQA64Zrmk:
2096 case VMOVDQA64Zrmkz:
2097 case VMOVDQA64Zrr:
2098 case VMOVDQA64Zrr_REV:
2099 case VMOVDQA64Zrrk:
2100 case VMOVDQA64Zrrk_REV:
2101 case VMOVDQA64Zrrkz:
2102 case VMOVDQA64Zrrkz_REV:
2103 return true;
2104 }
2105 return false;
2106}
2107
2108bool isINVLPG(unsigned Opcode) {
2109 return Opcode == INVLPG;
2110}
2111
2112bool isVGETEXPBF16(unsigned Opcode) {
2113 switch (Opcode) {
2114 case VGETEXPBF16Z128m:
2115 case VGETEXPBF16Z128mb:
2116 case VGETEXPBF16Z128mbk:
2117 case VGETEXPBF16Z128mbkz:
2118 case VGETEXPBF16Z128mk:
2119 case VGETEXPBF16Z128mkz:
2120 case VGETEXPBF16Z128r:
2121 case VGETEXPBF16Z128rk:
2122 case VGETEXPBF16Z128rkz:
2123 case VGETEXPBF16Z256m:
2124 case VGETEXPBF16Z256mb:
2125 case VGETEXPBF16Z256mbk:
2126 case VGETEXPBF16Z256mbkz:
2127 case VGETEXPBF16Z256mk:
2128 case VGETEXPBF16Z256mkz:
2129 case VGETEXPBF16Z256r:
2130 case VGETEXPBF16Z256rk:
2131 case VGETEXPBF16Z256rkz:
2132 case VGETEXPBF16Zm:
2133 case VGETEXPBF16Zmb:
2134 case VGETEXPBF16Zmbk:
2135 case VGETEXPBF16Zmbkz:
2136 case VGETEXPBF16Zmk:
2137 case VGETEXPBF16Zmkz:
2138 case VGETEXPBF16Zr:
2139 case VGETEXPBF16Zrk:
2140 case VGETEXPBF16Zrkz:
2141 return true;
2142 }
2143 return false;
2144}
2145
2146bool isVBROADCASTF64X4(unsigned Opcode) {
2147 switch (Opcode) {
2148 case VBROADCASTF64X4Zrm:
2149 case VBROADCASTF64X4Zrmk:
2150 case VBROADCASTF64X4Zrmkz:
2151 return true;
2152 }
2153 return false;
2154}
2155
2156bool isVPERMI2Q(unsigned Opcode) {
2157 switch (Opcode) {
2158 case VPERMI2QZ128rm:
2159 case VPERMI2QZ128rmb:
2160 case VPERMI2QZ128rmbk:
2161 case VPERMI2QZ128rmbkz:
2162 case VPERMI2QZ128rmk:
2163 case VPERMI2QZ128rmkz:
2164 case VPERMI2QZ128rr:
2165 case VPERMI2QZ128rrk:
2166 case VPERMI2QZ128rrkz:
2167 case VPERMI2QZ256rm:
2168 case VPERMI2QZ256rmb:
2169 case VPERMI2QZ256rmbk:
2170 case VPERMI2QZ256rmbkz:
2171 case VPERMI2QZ256rmk:
2172 case VPERMI2QZ256rmkz:
2173 case VPERMI2QZ256rr:
2174 case VPERMI2QZ256rrk:
2175 case VPERMI2QZ256rrkz:
2176 case VPERMI2QZrm:
2177 case VPERMI2QZrmb:
2178 case VPERMI2QZrmbk:
2179 case VPERMI2QZrmbkz:
2180 case VPERMI2QZrmk:
2181 case VPERMI2QZrmkz:
2182 case VPERMI2QZrr:
2183 case VPERMI2QZrrk:
2184 case VPERMI2QZrrkz:
2185 return true;
2186 }
2187 return false;
2188}
2189
2190bool isVPMOVSXBD(unsigned Opcode) {
2191 switch (Opcode) {
2192 case VPMOVSXBDYrm:
2193 case VPMOVSXBDYrr:
2194 case VPMOVSXBDZ128rm:
2195 case VPMOVSXBDZ128rmk:
2196 case VPMOVSXBDZ128rmkz:
2197 case VPMOVSXBDZ128rr:
2198 case VPMOVSXBDZ128rrk:
2199 case VPMOVSXBDZ128rrkz:
2200 case VPMOVSXBDZ256rm:
2201 case VPMOVSXBDZ256rmk:
2202 case VPMOVSXBDZ256rmkz:
2203 case VPMOVSXBDZ256rr:
2204 case VPMOVSXBDZ256rrk:
2205 case VPMOVSXBDZ256rrkz:
2206 case VPMOVSXBDZrm:
2207 case VPMOVSXBDZrmk:
2208 case VPMOVSXBDZrmkz:
2209 case VPMOVSXBDZrr:
2210 case VPMOVSXBDZrrk:
2211 case VPMOVSXBDZrrkz:
2212 case VPMOVSXBDrm:
2213 case VPMOVSXBDrr:
2214 return true;
2215 }
2216 return false;
2217}
2218
2219bool isVFMSUB132SS(unsigned Opcode) {
2220 switch (Opcode) {
2221 case VFMSUB132SSZm_Int:
2222 case VFMSUB132SSZmk_Int:
2223 case VFMSUB132SSZmkz_Int:
2224 case VFMSUB132SSZr_Int:
2225 case VFMSUB132SSZrb_Int:
2226 case VFMSUB132SSZrbk_Int:
2227 case VFMSUB132SSZrbkz_Int:
2228 case VFMSUB132SSZrk_Int:
2229 case VFMSUB132SSZrkz_Int:
2230 case VFMSUB132SSm_Int:
2231 case VFMSUB132SSr_Int:
2232 return true;
2233 }
2234 return false;
2235}
2236
2237bool isVPMOVUSDW(unsigned Opcode) {
2238 switch (Opcode) {
2239 case VPMOVUSDWZ128mr:
2240 case VPMOVUSDWZ128mrk:
2241 case VPMOVUSDWZ128rr:
2242 case VPMOVUSDWZ128rrk:
2243 case VPMOVUSDWZ128rrkz:
2244 case VPMOVUSDWZ256mr:
2245 case VPMOVUSDWZ256mrk:
2246 case VPMOVUSDWZ256rr:
2247 case VPMOVUSDWZ256rrk:
2248 case VPMOVUSDWZ256rrkz:
2249 case VPMOVUSDWZmr:
2250 case VPMOVUSDWZmrk:
2251 case VPMOVUSDWZrr:
2252 case VPMOVUSDWZrrk:
2253 case VPMOVUSDWZrrkz:
2254 return true;
2255 }
2256 return false;
2257}
2258
2259bool isAAD(unsigned Opcode) {
2260 return Opcode == AAD8i8;
2261}
2262
2263bool isIDIV(unsigned Opcode) {
2264 switch (Opcode) {
2265 case IDIV16m:
2266 case IDIV16m_EVEX:
2267 case IDIV16m_NF:
2268 case IDIV16r:
2269 case IDIV16r_EVEX:
2270 case IDIV16r_NF:
2271 case IDIV32m:
2272 case IDIV32m_EVEX:
2273 case IDIV32m_NF:
2274 case IDIV32r:
2275 case IDIV32r_EVEX:
2276 case IDIV32r_NF:
2277 case IDIV64m:
2278 case IDIV64m_EVEX:
2279 case IDIV64m_NF:
2280 case IDIV64r:
2281 case IDIV64r_EVEX:
2282 case IDIV64r_NF:
2283 case IDIV8m:
2284 case IDIV8m_EVEX:
2285 case IDIV8m_NF:
2286 case IDIV8r:
2287 case IDIV8r_EVEX:
2288 case IDIV8r_NF:
2289 return true;
2290 }
2291 return false;
2292}
2293
2294bool isCVTTPS2DQ(unsigned Opcode) {
2295 switch (Opcode) {
2296 case CVTTPS2DQrm:
2297 case CVTTPS2DQrr:
2298 return true;
2299 }
2300 return false;
2301}
2302
2303bool isVBROADCASTF32X8(unsigned Opcode) {
2304 switch (Opcode) {
2305 case VBROADCASTF32X8Zrm:
2306 case VBROADCASTF32X8Zrmk:
2307 case VBROADCASTF32X8Zrmkz:
2308 return true;
2309 }
2310 return false;
2311}
2312
2313bool isVFMSUBSS(unsigned Opcode) {
2314 switch (Opcode) {
2315 case VFMSUBSS4mr:
2316 case VFMSUBSS4rm:
2317 case VFMSUBSS4rr:
2318 case VFMSUBSS4rr_REV:
2319 return true;
2320 }
2321 return false;
2322}
2323
2324bool isEMMS(unsigned Opcode) {
2325 return Opcode == MMX_EMMS;
2326}
2327
2328bool isVPDPBSUD(unsigned Opcode) {
2329 switch (Opcode) {
2330 case VPDPBSUDYrm:
2331 case VPDPBSUDYrr:
2332 case VPDPBSUDZ128rm:
2333 case VPDPBSUDZ128rmb:
2334 case VPDPBSUDZ128rmbk:
2335 case VPDPBSUDZ128rmbkz:
2336 case VPDPBSUDZ128rmk:
2337 case VPDPBSUDZ128rmkz:
2338 case VPDPBSUDZ128rr:
2339 case VPDPBSUDZ128rrk:
2340 case VPDPBSUDZ128rrkz:
2341 case VPDPBSUDZ256rm:
2342 case VPDPBSUDZ256rmb:
2343 case VPDPBSUDZ256rmbk:
2344 case VPDPBSUDZ256rmbkz:
2345 case VPDPBSUDZ256rmk:
2346 case VPDPBSUDZ256rmkz:
2347 case VPDPBSUDZ256rr:
2348 case VPDPBSUDZ256rrk:
2349 case VPDPBSUDZ256rrkz:
2350 case VPDPBSUDZrm:
2351 case VPDPBSUDZrmb:
2352 case VPDPBSUDZrmbk:
2353 case VPDPBSUDZrmbkz:
2354 case VPDPBSUDZrmk:
2355 case VPDPBSUDZrmkz:
2356 case VPDPBSUDZrr:
2357 case VPDPBSUDZrrk:
2358 case VPDPBSUDZrrkz:
2359 case VPDPBSUDrm:
2360 case VPDPBSUDrr:
2361 return true;
2362 }
2363 return false;
2364}
2365
2366bool isPMOVSXWQ(unsigned Opcode) {
2367 switch (Opcode) {
2368 case PMOVSXWQrm:
2369 case PMOVSXWQrr:
2370 return true;
2371 }
2372 return false;
2373}
2374
2375bool isPSRLW(unsigned Opcode) {
2376 switch (Opcode) {
2377 case MMX_PSRLWri:
2378 case MMX_PSRLWrm:
2379 case MMX_PSRLWrr:
2380 case PSRLWri:
2381 case PSRLWrm:
2382 case PSRLWrr:
2383 return true;
2384 }
2385 return false;
2386}
2387
2388bool isMOVNTDQA(unsigned Opcode) {
2389 return Opcode == MOVNTDQArm;
2390}
2391
2392bool isFUCOMPI(unsigned Opcode) {
2393 return Opcode == UCOM_FIPr;
2394}
2395
2396bool isANDNPS(unsigned Opcode) {
2397 switch (Opcode) {
2398 case ANDNPSrm:
2399 case ANDNPSrr:
2400 return true;
2401 }
2402 return false;
2403}
2404
2405bool isVINSERTF64X2(unsigned Opcode) {
2406 switch (Opcode) {
2407 case VINSERTF64X2Z256rmi:
2408 case VINSERTF64X2Z256rmik:
2409 case VINSERTF64X2Z256rmikz:
2410 case VINSERTF64X2Z256rri:
2411 case VINSERTF64X2Z256rrik:
2412 case VINSERTF64X2Z256rrikz:
2413 case VINSERTF64X2Zrmi:
2414 case VINSERTF64X2Zrmik:
2415 case VINSERTF64X2Zrmikz:
2416 case VINSERTF64X2Zrri:
2417 case VINSERTF64X2Zrrik:
2418 case VINSERTF64X2Zrrikz:
2419 return true;
2420 }
2421 return false;
2422}
2423
2424bool isCLTS(unsigned Opcode) {
2425 return Opcode == CLTS;
2426}
2427
2428bool isSETSSBSY(unsigned Opcode) {
2429 return Opcode == SETSSBSY;
2430}
2431
2432bool isVMULPD(unsigned Opcode) {
2433 switch (Opcode) {
2434 case VMULPDYrm:
2435 case VMULPDYrr:
2436 case VMULPDZ128rm:
2437 case VMULPDZ128rmb:
2438 case VMULPDZ128rmbk:
2439 case VMULPDZ128rmbkz:
2440 case VMULPDZ128rmk:
2441 case VMULPDZ128rmkz:
2442 case VMULPDZ128rr:
2443 case VMULPDZ128rrk:
2444 case VMULPDZ128rrkz:
2445 case VMULPDZ256rm:
2446 case VMULPDZ256rmb:
2447 case VMULPDZ256rmbk:
2448 case VMULPDZ256rmbkz:
2449 case VMULPDZ256rmk:
2450 case VMULPDZ256rmkz:
2451 case VMULPDZ256rr:
2452 case VMULPDZ256rrk:
2453 case VMULPDZ256rrkz:
2454 case VMULPDZrm:
2455 case VMULPDZrmb:
2456 case VMULPDZrmbk:
2457 case VMULPDZrmbkz:
2458 case VMULPDZrmk:
2459 case VMULPDZrmkz:
2460 case VMULPDZrr:
2461 case VMULPDZrrb:
2462 case VMULPDZrrbk:
2463 case VMULPDZrrbkz:
2464 case VMULPDZrrk:
2465 case VMULPDZrrkz:
2466 case VMULPDrm:
2467 case VMULPDrr:
2468 return true;
2469 }
2470 return false;
2471}
2472
2473bool isVFMADDSUB132PS(unsigned Opcode) {
2474 switch (Opcode) {
2475 case VFMADDSUB132PSYm:
2476 case VFMADDSUB132PSYr:
2477 case VFMADDSUB132PSZ128m:
2478 case VFMADDSUB132PSZ128mb:
2479 case VFMADDSUB132PSZ128mbk:
2480 case VFMADDSUB132PSZ128mbkz:
2481 case VFMADDSUB132PSZ128mk:
2482 case VFMADDSUB132PSZ128mkz:
2483 case VFMADDSUB132PSZ128r:
2484 case VFMADDSUB132PSZ128rk:
2485 case VFMADDSUB132PSZ128rkz:
2486 case VFMADDSUB132PSZ256m:
2487 case VFMADDSUB132PSZ256mb:
2488 case VFMADDSUB132PSZ256mbk:
2489 case VFMADDSUB132PSZ256mbkz:
2490 case VFMADDSUB132PSZ256mk:
2491 case VFMADDSUB132PSZ256mkz:
2492 case VFMADDSUB132PSZ256r:
2493 case VFMADDSUB132PSZ256rk:
2494 case VFMADDSUB132PSZ256rkz:
2495 case VFMADDSUB132PSZm:
2496 case VFMADDSUB132PSZmb:
2497 case VFMADDSUB132PSZmbk:
2498 case VFMADDSUB132PSZmbkz:
2499 case VFMADDSUB132PSZmk:
2500 case VFMADDSUB132PSZmkz:
2501 case VFMADDSUB132PSZr:
2502 case VFMADDSUB132PSZrb:
2503 case VFMADDSUB132PSZrbk:
2504 case VFMADDSUB132PSZrbkz:
2505 case VFMADDSUB132PSZrk:
2506 case VFMADDSUB132PSZrkz:
2507 case VFMADDSUB132PSm:
2508 case VFMADDSUB132PSr:
2509 return true;
2510 }
2511 return false;
2512}
2513
2514bool isVPMADCSWD(unsigned Opcode) {
2515 switch (Opcode) {
2516 case VPMADCSWDrm:
2517 case VPMADCSWDrr:
2518 return true;
2519 }
2520 return false;
2521}
2522
2523bool isVSCATTERPF0DPS(unsigned Opcode) {
2524 return Opcode == VSCATTERPF0DPSm;
2525}
2526
2527bool isXCHG(unsigned Opcode) {
2528 switch (Opcode) {
2529 case XCHG16ar:
2530 case XCHG16rm:
2531 case XCHG16rr:
2532 case XCHG32ar:
2533 case XCHG32rm:
2534 case XCHG32rr:
2535 case XCHG64ar:
2536 case XCHG64rm:
2537 case XCHG64rr:
2538 case XCHG8rm:
2539 case XCHG8rr:
2540 return true;
2541 }
2542 return false;
2543}
2544
2545bool isVGATHERPF1QPS(unsigned Opcode) {
2546 return Opcode == VGATHERPF1QPSm;
2547}
2548
2549bool isVCVTNEPS2BF16(unsigned Opcode) {
2550 switch (Opcode) {
2551 case VCVTNEPS2BF16Yrm:
2552 case VCVTNEPS2BF16Yrr:
2553 case VCVTNEPS2BF16Z128rm:
2554 case VCVTNEPS2BF16Z128rmb:
2555 case VCVTNEPS2BF16Z128rmbk:
2556 case VCVTNEPS2BF16Z128rmbkz:
2557 case VCVTNEPS2BF16Z128rmk:
2558 case VCVTNEPS2BF16Z128rmkz:
2559 case VCVTNEPS2BF16Z128rr:
2560 case VCVTNEPS2BF16Z128rrk:
2561 case VCVTNEPS2BF16Z128rrkz:
2562 case VCVTNEPS2BF16Z256rm:
2563 case VCVTNEPS2BF16Z256rmb:
2564 case VCVTNEPS2BF16Z256rmbk:
2565 case VCVTNEPS2BF16Z256rmbkz:
2566 case VCVTNEPS2BF16Z256rmk:
2567 case VCVTNEPS2BF16Z256rmkz:
2568 case VCVTNEPS2BF16Z256rr:
2569 case VCVTNEPS2BF16Z256rrk:
2570 case VCVTNEPS2BF16Z256rrkz:
2571 case VCVTNEPS2BF16Zrm:
2572 case VCVTNEPS2BF16Zrmb:
2573 case VCVTNEPS2BF16Zrmbk:
2574 case VCVTNEPS2BF16Zrmbkz:
2575 case VCVTNEPS2BF16Zrmk:
2576 case VCVTNEPS2BF16Zrmkz:
2577 case VCVTNEPS2BF16Zrr:
2578 case VCVTNEPS2BF16Zrrk:
2579 case VCVTNEPS2BF16Zrrkz:
2580 case VCVTNEPS2BF16rm:
2581 case VCVTNEPS2BF16rr:
2582 return true;
2583 }
2584 return false;
2585}
2586
2587bool isVFMADDSS(unsigned Opcode) {
2588 switch (Opcode) {
2589 case VFMADDSS4mr:
2590 case VFMADDSS4rm:
2591 case VFMADDSS4rr:
2592 case VFMADDSS4rr_REV:
2593 return true;
2594 }
2595 return false;
2596}
2597
2598bool isINTO(unsigned Opcode) {
2599 return Opcode == INTO;
2600}
2601
2602bool isANDPD(unsigned Opcode) {
2603 switch (Opcode) {
2604 case ANDPDrm:
2605 case ANDPDrr:
2606 return true;
2607 }
2608 return false;
2609}
2610
2611bool isSEAMCALL(unsigned Opcode) {
2612 return Opcode == SEAMCALL;
2613}
2614
2615bool isSHLD(unsigned Opcode) {
2616 switch (Opcode) {
2617 case SHLD16mrCL:
2618 case SHLD16mrCL_EVEX:
2619 case SHLD16mrCL_ND:
2620 case SHLD16mrCL_NF:
2621 case SHLD16mrCL_NF_ND:
2622 case SHLD16mri8:
2623 case SHLD16mri8_EVEX:
2624 case SHLD16mri8_ND:
2625 case SHLD16mri8_NF:
2626 case SHLD16mri8_NF_ND:
2627 case SHLD16rrCL:
2628 case SHLD16rrCL_EVEX:
2629 case SHLD16rrCL_ND:
2630 case SHLD16rrCL_NF:
2631 case SHLD16rrCL_NF_ND:
2632 case SHLD16rri8:
2633 case SHLD16rri8_EVEX:
2634 case SHLD16rri8_ND:
2635 case SHLD16rri8_NF:
2636 case SHLD16rri8_NF_ND:
2637 case SHLD32mrCL:
2638 case SHLD32mrCL_EVEX:
2639 case SHLD32mrCL_ND:
2640 case SHLD32mrCL_NF:
2641 case SHLD32mrCL_NF_ND:
2642 case SHLD32mri8:
2643 case SHLD32mri8_EVEX:
2644 case SHLD32mri8_ND:
2645 case SHLD32mri8_NF:
2646 case SHLD32mri8_NF_ND:
2647 case SHLD32rrCL:
2648 case SHLD32rrCL_EVEX:
2649 case SHLD32rrCL_ND:
2650 case SHLD32rrCL_NF:
2651 case SHLD32rrCL_NF_ND:
2652 case SHLD32rri8:
2653 case SHLD32rri8_EVEX:
2654 case SHLD32rri8_ND:
2655 case SHLD32rri8_NF:
2656 case SHLD32rri8_NF_ND:
2657 case SHLD64mrCL:
2658 case SHLD64mrCL_EVEX:
2659 case SHLD64mrCL_ND:
2660 case SHLD64mrCL_NF:
2661 case SHLD64mrCL_NF_ND:
2662 case SHLD64mri8:
2663 case SHLD64mri8_EVEX:
2664 case SHLD64mri8_ND:
2665 case SHLD64mri8_NF:
2666 case SHLD64mri8_NF_ND:
2667 case SHLD64rrCL:
2668 case SHLD64rrCL_EVEX:
2669 case SHLD64rrCL_ND:
2670 case SHLD64rrCL_NF:
2671 case SHLD64rrCL_NF_ND:
2672 case SHLD64rri8:
2673 case SHLD64rri8_EVEX:
2674 case SHLD64rri8_ND:
2675 case SHLD64rri8_NF:
2676 case SHLD64rri8_NF_ND:
2677 return true;
2678 }
2679 return false;
2680}
2681
2682bool isUNPCKHPS(unsigned Opcode) {
2683 switch (Opcode) {
2684 case UNPCKHPSrm:
2685 case UNPCKHPSrr:
2686 return true;
2687 }
2688 return false;
2689}
2690
2691bool isVPDPBSSDS(unsigned Opcode) {
2692 switch (Opcode) {
2693 case VPDPBSSDSYrm:
2694 case VPDPBSSDSYrr:
2695 case VPDPBSSDSZ128rm:
2696 case VPDPBSSDSZ128rmb:
2697 case VPDPBSSDSZ128rmbk:
2698 case VPDPBSSDSZ128rmbkz:
2699 case VPDPBSSDSZ128rmk:
2700 case VPDPBSSDSZ128rmkz:
2701 case VPDPBSSDSZ128rr:
2702 case VPDPBSSDSZ128rrk:
2703 case VPDPBSSDSZ128rrkz:
2704 case VPDPBSSDSZ256rm:
2705 case VPDPBSSDSZ256rmb:
2706 case VPDPBSSDSZ256rmbk:
2707 case VPDPBSSDSZ256rmbkz:
2708 case VPDPBSSDSZ256rmk:
2709 case VPDPBSSDSZ256rmkz:
2710 case VPDPBSSDSZ256rr:
2711 case VPDPBSSDSZ256rrk:
2712 case VPDPBSSDSZ256rrkz:
2713 case VPDPBSSDSZrm:
2714 case VPDPBSSDSZrmb:
2715 case VPDPBSSDSZrmbk:
2716 case VPDPBSSDSZrmbkz:
2717 case VPDPBSSDSZrmk:
2718 case VPDPBSSDSZrmkz:
2719 case VPDPBSSDSZrr:
2720 case VPDPBSSDSZrrk:
2721 case VPDPBSSDSZrrkz:
2722 case VPDPBSSDSrm:
2723 case VPDPBSSDSrr:
2724 return true;
2725 }
2726 return false;
2727}
2728
2729bool isSETZUCC(unsigned Opcode) {
2730 switch (Opcode) {
2731 case SETZUCCm:
2732 case SETZUCCr:
2733 return true;
2734 }
2735 return false;
2736}
2737
2738bool isSHUFPD(unsigned Opcode) {
2739 switch (Opcode) {
2740 case SHUFPDrmi:
2741 case SHUFPDrri:
2742 return true;
2743 }
2744 return false;
2745}
2746
2747bool isFCMOVNB(unsigned Opcode) {
2748 return Opcode == CMOVNB_F;
2749}
2750
2751bool isCVTTSS2SI(unsigned Opcode) {
2752 switch (Opcode) {
2753 case CVTTSS2SI64rm_Int:
2754 case CVTTSS2SI64rr_Int:
2755 case CVTTSS2SIrm_Int:
2756 case CVTTSS2SIrr_Int:
2757 return true;
2758 }
2759 return false;
2760}
2761
2762bool isEXTRQ(unsigned Opcode) {
2763 switch (Opcode) {
2764 case EXTRQ:
2765 case EXTRQI:
2766 return true;
2767 }
2768 return false;
2769}
2770
2771bool isVBROADCASTSS(unsigned Opcode) {
2772 switch (Opcode) {
2773 case VBROADCASTSSYrm:
2774 case VBROADCASTSSYrr:
2775 case VBROADCASTSSZ128rm:
2776 case VBROADCASTSSZ128rmk:
2777 case VBROADCASTSSZ128rmkz:
2778 case VBROADCASTSSZ128rr:
2779 case VBROADCASTSSZ128rrk:
2780 case VBROADCASTSSZ128rrkz:
2781 case VBROADCASTSSZ256rm:
2782 case VBROADCASTSSZ256rmk:
2783 case VBROADCASTSSZ256rmkz:
2784 case VBROADCASTSSZ256rr:
2785 case VBROADCASTSSZ256rrk:
2786 case VBROADCASTSSZ256rrkz:
2787 case VBROADCASTSSZrm:
2788 case VBROADCASTSSZrmk:
2789 case VBROADCASTSSZrmkz:
2790 case VBROADCASTSSZrr:
2791 case VBROADCASTSSZrrk:
2792 case VBROADCASTSSZrrkz:
2793 case VBROADCASTSSrm:
2794 case VBROADCASTSSrr:
2795 return true;
2796 }
2797 return false;
2798}
2799
2800bool isCLUI(unsigned Opcode) {
2801 return Opcode == CLUI;
2802}
2803
2804bool isVINSERTI128(unsigned Opcode) {
2805 switch (Opcode) {
2806 case VINSERTI128rmi:
2807 case VINSERTI128rri:
2808 return true;
2809 }
2810 return false;
2811}
2812
2813bool isVPSHLDW(unsigned Opcode) {
2814 switch (Opcode) {
2815 case VPSHLDWZ128rmi:
2816 case VPSHLDWZ128rmik:
2817 case VPSHLDWZ128rmikz:
2818 case VPSHLDWZ128rri:
2819 case VPSHLDWZ128rrik:
2820 case VPSHLDWZ128rrikz:
2821 case VPSHLDWZ256rmi:
2822 case VPSHLDWZ256rmik:
2823 case VPSHLDWZ256rmikz:
2824 case VPSHLDWZ256rri:
2825 case VPSHLDWZ256rrik:
2826 case VPSHLDWZ256rrikz:
2827 case VPSHLDWZrmi:
2828 case VPSHLDWZrmik:
2829 case VPSHLDWZrmikz:
2830 case VPSHLDWZrri:
2831 case VPSHLDWZrrik:
2832 case VPSHLDWZrrikz:
2833 return true;
2834 }
2835 return false;
2836}
2837
2838bool isVBLENDPD(unsigned Opcode) {
2839 switch (Opcode) {
2840 case VBLENDPDYrmi:
2841 case VBLENDPDYrri:
2842 case VBLENDPDrmi:
2843 case VBLENDPDrri:
2844 return true;
2845 }
2846 return false;
2847}
2848
2849bool isVSM4KEY4(unsigned Opcode) {
2850 switch (Opcode) {
2851 case VSM4KEY4Yrm:
2852 case VSM4KEY4Yrr:
2853 case VSM4KEY4Z128rm:
2854 case VSM4KEY4Z128rr:
2855 case VSM4KEY4Z256rm:
2856 case VSM4KEY4Z256rr:
2857 case VSM4KEY4Zrm:
2858 case VSM4KEY4Zrr:
2859 case VSM4KEY4rm:
2860 case VSM4KEY4rr:
2861 return true;
2862 }
2863 return false;
2864}
2865
2866bool isVCVTNEEPH2PS(unsigned Opcode) {
2867 switch (Opcode) {
2868 case VCVTNEEPH2PSYrm:
2869 case VCVTNEEPH2PSrm:
2870 return true;
2871 }
2872 return false;
2873}
2874
2875bool isVCVTTSD2SI(unsigned Opcode) {
2876 switch (Opcode) {
2877 case VCVTTSD2SI64Zrm_Int:
2878 case VCVTTSD2SI64Zrr_Int:
2879 case VCVTTSD2SI64Zrrb_Int:
2880 case VCVTTSD2SI64rm_Int:
2881 case VCVTTSD2SI64rr_Int:
2882 case VCVTTSD2SIZrm_Int:
2883 case VCVTTSD2SIZrr_Int:
2884 case VCVTTSD2SIZrrb_Int:
2885 case VCVTTSD2SIrm_Int:
2886 case VCVTTSD2SIrr_Int:
2887 return true;
2888 }
2889 return false;
2890}
2891
2892bool isWRMSRNS(unsigned Opcode) {
2893 switch (Opcode) {
2894 case WRMSRNS:
2895 case WRMSRNSir:
2896 case WRMSRNSir_EVEX:
2897 return true;
2898 }
2899 return false;
2900}
2901
2902bool isCMPSB(unsigned Opcode) {
2903 return Opcode == CMPSB;
2904}
2905
2906bool isVRCPBF16(unsigned Opcode) {
2907 switch (Opcode) {
2908 case VRCPBF16Z128m:
2909 case VRCPBF16Z128mb:
2910 case VRCPBF16Z128mbk:
2911 case VRCPBF16Z128mbkz:
2912 case VRCPBF16Z128mk:
2913 case VRCPBF16Z128mkz:
2914 case VRCPBF16Z128r:
2915 case VRCPBF16Z128rk:
2916 case VRCPBF16Z128rkz:
2917 case VRCPBF16Z256m:
2918 case VRCPBF16Z256mb:
2919 case VRCPBF16Z256mbk:
2920 case VRCPBF16Z256mbkz:
2921 case VRCPBF16Z256mk:
2922 case VRCPBF16Z256mkz:
2923 case VRCPBF16Z256r:
2924 case VRCPBF16Z256rk:
2925 case VRCPBF16Z256rkz:
2926 case VRCPBF16Zm:
2927 case VRCPBF16Zmb:
2928 case VRCPBF16Zmbk:
2929 case VRCPBF16Zmbkz:
2930 case VRCPBF16Zmk:
2931 case VRCPBF16Zmkz:
2932 case VRCPBF16Zr:
2933 case VRCPBF16Zrk:
2934 case VRCPBF16Zrkz:
2935 return true;
2936 }
2937 return false;
2938}
2939
2940bool isMULSS(unsigned Opcode) {
2941 switch (Opcode) {
2942 case MULSSrm_Int:
2943 case MULSSrr_Int:
2944 return true;
2945 }
2946 return false;
2947}
2948
2949bool isVMRUN(unsigned Opcode) {
2950 switch (Opcode) {
2951 case VMRUN32:
2952 case VMRUN64:
2953 return true;
2954 }
2955 return false;
2956}
2957
2958bool isVPSRLVD(unsigned Opcode) {
2959 switch (Opcode) {
2960 case VPSRLVDYrm:
2961 case VPSRLVDYrr:
2962 case VPSRLVDZ128rm:
2963 case VPSRLVDZ128rmb:
2964 case VPSRLVDZ128rmbk:
2965 case VPSRLVDZ128rmbkz:
2966 case VPSRLVDZ128rmk:
2967 case VPSRLVDZ128rmkz:
2968 case VPSRLVDZ128rr:
2969 case VPSRLVDZ128rrk:
2970 case VPSRLVDZ128rrkz:
2971 case VPSRLVDZ256rm:
2972 case VPSRLVDZ256rmb:
2973 case VPSRLVDZ256rmbk:
2974 case VPSRLVDZ256rmbkz:
2975 case VPSRLVDZ256rmk:
2976 case VPSRLVDZ256rmkz:
2977 case VPSRLVDZ256rr:
2978 case VPSRLVDZ256rrk:
2979 case VPSRLVDZ256rrkz:
2980 case VPSRLVDZrm:
2981 case VPSRLVDZrmb:
2982 case VPSRLVDZrmbk:
2983 case VPSRLVDZrmbkz:
2984 case VPSRLVDZrmk:
2985 case VPSRLVDZrmkz:
2986 case VPSRLVDZrr:
2987 case VPSRLVDZrrk:
2988 case VPSRLVDZrrkz:
2989 case VPSRLVDrm:
2990 case VPSRLVDrr:
2991 return true;
2992 }
2993 return false;
2994}
2995
2996bool isLEAVE(unsigned Opcode) {
2997 switch (Opcode) {
2998 case LEAVE:
2999 case LEAVE64:
3000 return true;
3001 }
3002 return false;
3003}
3004
3005bool isVGETMANTPS(unsigned Opcode) {
3006 switch (Opcode) {
3007 case VGETMANTPSZ128rmbi:
3008 case VGETMANTPSZ128rmbik:
3009 case VGETMANTPSZ128rmbikz:
3010 case VGETMANTPSZ128rmi:
3011 case VGETMANTPSZ128rmik:
3012 case VGETMANTPSZ128rmikz:
3013 case VGETMANTPSZ128rri:
3014 case VGETMANTPSZ128rrik:
3015 case VGETMANTPSZ128rrikz:
3016 case VGETMANTPSZ256rmbi:
3017 case VGETMANTPSZ256rmbik:
3018 case VGETMANTPSZ256rmbikz:
3019 case VGETMANTPSZ256rmi:
3020 case VGETMANTPSZ256rmik:
3021 case VGETMANTPSZ256rmikz:
3022 case VGETMANTPSZ256rri:
3023 case VGETMANTPSZ256rrik:
3024 case VGETMANTPSZ256rrikz:
3025 case VGETMANTPSZrmbi:
3026 case VGETMANTPSZrmbik:
3027 case VGETMANTPSZrmbikz:
3028 case VGETMANTPSZrmi:
3029 case VGETMANTPSZrmik:
3030 case VGETMANTPSZrmikz:
3031 case VGETMANTPSZrri:
3032 case VGETMANTPSZrrib:
3033 case VGETMANTPSZrribk:
3034 case VGETMANTPSZrribkz:
3035 case VGETMANTPSZrrik:
3036 case VGETMANTPSZrrikz:
3037 return true;
3038 }
3039 return false;
3040}
3041
3042bool isXSHA256(unsigned Opcode) {
3043 return Opcode == XSHA256;
3044}
3045
3046bool isBOUND(unsigned Opcode) {
3047 switch (Opcode) {
3048 case BOUNDS16rm:
3049 case BOUNDS32rm:
3050 return true;
3051 }
3052 return false;
3053}
3054
3055bool isSFENCE(unsigned Opcode) {
3056 return Opcode == SFENCE;
3057}
3058
3059bool isVPHADDD(unsigned Opcode) {
3060 switch (Opcode) {
3061 case VPHADDDYrm:
3062 case VPHADDDYrr:
3063 case VPHADDDrm:
3064 case VPHADDDrr:
3065 return true;
3066 }
3067 return false;
3068}
3069
3070bool isADOX(unsigned Opcode) {
3071 switch (Opcode) {
3072 case ADOX32rm:
3073 case ADOX32rm_EVEX:
3074 case ADOX32rm_ND:
3075 case ADOX32rr:
3076 case ADOX32rr_EVEX:
3077 case ADOX32rr_ND:
3078 case ADOX64rm:
3079 case ADOX64rm_EVEX:
3080 case ADOX64rm_ND:
3081 case ADOX64rr:
3082 case ADOX64rr_EVEX:
3083 case ADOX64rr_ND:
3084 return true;
3085 }
3086 return false;
3087}
3088
3089bool isVPSLLQ(unsigned Opcode) {
3090 switch (Opcode) {
3091 case VPSLLQYri:
3092 case VPSLLQYrm:
3093 case VPSLLQYrr:
3094 case VPSLLQZ128mbi:
3095 case VPSLLQZ128mbik:
3096 case VPSLLQZ128mbikz:
3097 case VPSLLQZ128mi:
3098 case VPSLLQZ128mik:
3099 case VPSLLQZ128mikz:
3100 case VPSLLQZ128ri:
3101 case VPSLLQZ128rik:
3102 case VPSLLQZ128rikz:
3103 case VPSLLQZ128rm:
3104 case VPSLLQZ128rmk:
3105 case VPSLLQZ128rmkz:
3106 case VPSLLQZ128rr:
3107 case VPSLLQZ128rrk:
3108 case VPSLLQZ128rrkz:
3109 case VPSLLQZ256mbi:
3110 case VPSLLQZ256mbik:
3111 case VPSLLQZ256mbikz:
3112 case VPSLLQZ256mi:
3113 case VPSLLQZ256mik:
3114 case VPSLLQZ256mikz:
3115 case VPSLLQZ256ri:
3116 case VPSLLQZ256rik:
3117 case VPSLLQZ256rikz:
3118 case VPSLLQZ256rm:
3119 case VPSLLQZ256rmk:
3120 case VPSLLQZ256rmkz:
3121 case VPSLLQZ256rr:
3122 case VPSLLQZ256rrk:
3123 case VPSLLQZ256rrkz:
3124 case VPSLLQZmbi:
3125 case VPSLLQZmbik:
3126 case VPSLLQZmbikz:
3127 case VPSLLQZmi:
3128 case VPSLLQZmik:
3129 case VPSLLQZmikz:
3130 case VPSLLQZri:
3131 case VPSLLQZrik:
3132 case VPSLLQZrikz:
3133 case VPSLLQZrm:
3134 case VPSLLQZrmk:
3135 case VPSLLQZrmkz:
3136 case VPSLLQZrr:
3137 case VPSLLQZrrk:
3138 case VPSLLQZrrkz:
3139 case VPSLLQri:
3140 case VPSLLQrm:
3141 case VPSLLQrr:
3142 return true;
3143 }
3144 return false;
3145}
3146
3147bool isVCVTPH2HF8(unsigned Opcode) {
3148 switch (Opcode) {
3149 case VCVTPH2HF8Z128rm:
3150 case VCVTPH2HF8Z128rmb:
3151 case VCVTPH2HF8Z128rmbk:
3152 case VCVTPH2HF8Z128rmbkz:
3153 case VCVTPH2HF8Z128rmk:
3154 case VCVTPH2HF8Z128rmkz:
3155 case VCVTPH2HF8Z128rr:
3156 case VCVTPH2HF8Z128rrk:
3157 case VCVTPH2HF8Z128rrkz:
3158 case VCVTPH2HF8Z256rm:
3159 case VCVTPH2HF8Z256rmb:
3160 case VCVTPH2HF8Z256rmbk:
3161 case VCVTPH2HF8Z256rmbkz:
3162 case VCVTPH2HF8Z256rmk:
3163 case VCVTPH2HF8Z256rmkz:
3164 case VCVTPH2HF8Z256rr:
3165 case VCVTPH2HF8Z256rrk:
3166 case VCVTPH2HF8Z256rrkz:
3167 case VCVTPH2HF8Zrm:
3168 case VCVTPH2HF8Zrmb:
3169 case VCVTPH2HF8Zrmbk:
3170 case VCVTPH2HF8Zrmbkz:
3171 case VCVTPH2HF8Zrmk:
3172 case VCVTPH2HF8Zrmkz:
3173 case VCVTPH2HF8Zrr:
3174 case VCVTPH2HF8Zrrk:
3175 case VCVTPH2HF8Zrrkz:
3176 return true;
3177 }
3178 return false;
3179}
3180
3181bool isPFRSQIT1(unsigned Opcode) {
3182 switch (Opcode) {
3183 case PFRSQIT1rm:
3184 case PFRSQIT1rr:
3185 return true;
3186 }
3187 return false;
3188}
3189
3190bool isCLAC(unsigned Opcode) {
3191 return Opcode == CLAC;
3192}
3193
3194bool isKNOTW(unsigned Opcode) {
3195 return Opcode == KNOTWkk;
3196}
3197
3198bool isVCVTPH2PD(unsigned Opcode) {
3199 switch (Opcode) {
3200 case VCVTPH2PDZ128rm:
3201 case VCVTPH2PDZ128rmb:
3202 case VCVTPH2PDZ128rmbk:
3203 case VCVTPH2PDZ128rmbkz:
3204 case VCVTPH2PDZ128rmk:
3205 case VCVTPH2PDZ128rmkz:
3206 case VCVTPH2PDZ128rr:
3207 case VCVTPH2PDZ128rrk:
3208 case VCVTPH2PDZ128rrkz:
3209 case VCVTPH2PDZ256rm:
3210 case VCVTPH2PDZ256rmb:
3211 case VCVTPH2PDZ256rmbk:
3212 case VCVTPH2PDZ256rmbkz:
3213 case VCVTPH2PDZ256rmk:
3214 case VCVTPH2PDZ256rmkz:
3215 case VCVTPH2PDZ256rr:
3216 case VCVTPH2PDZ256rrk:
3217 case VCVTPH2PDZ256rrkz:
3218 case VCVTPH2PDZrm:
3219 case VCVTPH2PDZrmb:
3220 case VCVTPH2PDZrmbk:
3221 case VCVTPH2PDZrmbkz:
3222 case VCVTPH2PDZrmk:
3223 case VCVTPH2PDZrmkz:
3224 case VCVTPH2PDZrr:
3225 case VCVTPH2PDZrrb:
3226 case VCVTPH2PDZrrbk:
3227 case VCVTPH2PDZrrbkz:
3228 case VCVTPH2PDZrrk:
3229 case VCVTPH2PDZrrkz:
3230 return true;
3231 }
3232 return false;
3233}
3234
3235bool isVAESENC(unsigned Opcode) {
3236 switch (Opcode) {
3237 case VAESENCYrm:
3238 case VAESENCYrr:
3239 case VAESENCZ128rm:
3240 case VAESENCZ128rr:
3241 case VAESENCZ256rm:
3242 case VAESENCZ256rr:
3243 case VAESENCZrm:
3244 case VAESENCZrr:
3245 case VAESENCrm:
3246 case VAESENCrr:
3247 return true;
3248 }
3249 return false;
3250}
3251
3252bool isMOVNTI(unsigned Opcode) {
3253 switch (Opcode) {
3254 case MOVNTI_64mr:
3255 case MOVNTImr:
3256 return true;
3257 }
3258 return false;
3259}
3260
3261bool isFXCH(unsigned Opcode) {
3262 return Opcode == XCH_F;
3263}
3264
3265bool isPOPP(unsigned Opcode) {
3266 return Opcode == POPP64r;
3267}
3268
3269bool isVPBLENDMD(unsigned Opcode) {
3270 switch (Opcode) {
3271 case VPBLENDMDZ128rm:
3272 case VPBLENDMDZ128rmb:
3273 case VPBLENDMDZ128rmbk:
3274 case VPBLENDMDZ128rmbkz:
3275 case VPBLENDMDZ128rmk:
3276 case VPBLENDMDZ128rmkz:
3277 case VPBLENDMDZ128rr:
3278 case VPBLENDMDZ128rrk:
3279 case VPBLENDMDZ128rrkz:
3280 case VPBLENDMDZ256rm:
3281 case VPBLENDMDZ256rmb:
3282 case VPBLENDMDZ256rmbk:
3283 case VPBLENDMDZ256rmbkz:
3284 case VPBLENDMDZ256rmk:
3285 case VPBLENDMDZ256rmkz:
3286 case VPBLENDMDZ256rr:
3287 case VPBLENDMDZ256rrk:
3288 case VPBLENDMDZ256rrkz:
3289 case VPBLENDMDZrm:
3290 case VPBLENDMDZrmb:
3291 case VPBLENDMDZrmbk:
3292 case VPBLENDMDZrmbkz:
3293 case VPBLENDMDZrmk:
3294 case VPBLENDMDZrmkz:
3295 case VPBLENDMDZrr:
3296 case VPBLENDMDZrrk:
3297 case VPBLENDMDZrrkz:
3298 return true;
3299 }
3300 return false;
3301}
3302
3303bool isFSINCOS(unsigned Opcode) {
3304 return Opcode == FSINCOS;
3305}
3306
3307bool isVPMOVSXBW(unsigned Opcode) {
3308 switch (Opcode) {
3309 case VPMOVSXBWYrm:
3310 case VPMOVSXBWYrr:
3311 case VPMOVSXBWZ128rm:
3312 case VPMOVSXBWZ128rmk:
3313 case VPMOVSXBWZ128rmkz:
3314 case VPMOVSXBWZ128rr:
3315 case VPMOVSXBWZ128rrk:
3316 case VPMOVSXBWZ128rrkz:
3317 case VPMOVSXBWZ256rm:
3318 case VPMOVSXBWZ256rmk:
3319 case VPMOVSXBWZ256rmkz:
3320 case VPMOVSXBWZ256rr:
3321 case VPMOVSXBWZ256rrk:
3322 case VPMOVSXBWZ256rrkz:
3323 case VPMOVSXBWZrm:
3324 case VPMOVSXBWZrmk:
3325 case VPMOVSXBWZrmkz:
3326 case VPMOVSXBWZrr:
3327 case VPMOVSXBWZrrk:
3328 case VPMOVSXBWZrrkz:
3329 case VPMOVSXBWrm:
3330 case VPMOVSXBWrr:
3331 return true;
3332 }
3333 return false;
3334}
3335
3336bool isVPMULLW(unsigned Opcode) {
3337 switch (Opcode) {
3338 case VPMULLWYrm:
3339 case VPMULLWYrr:
3340 case VPMULLWZ128rm:
3341 case VPMULLWZ128rmk:
3342 case VPMULLWZ128rmkz:
3343 case VPMULLWZ128rr:
3344 case VPMULLWZ128rrk:
3345 case VPMULLWZ128rrkz:
3346 case VPMULLWZ256rm:
3347 case VPMULLWZ256rmk:
3348 case VPMULLWZ256rmkz:
3349 case VPMULLWZ256rr:
3350 case VPMULLWZ256rrk:
3351 case VPMULLWZ256rrkz:
3352 case VPMULLWZrm:
3353 case VPMULLWZrmk:
3354 case VPMULLWZrmkz:
3355 case VPMULLWZrr:
3356 case VPMULLWZrrk:
3357 case VPMULLWZrrkz:
3358 case VPMULLWrm:
3359 case VPMULLWrr:
3360 return true;
3361 }
3362 return false;
3363}
3364
3365bool isSTC(unsigned Opcode) {
3366 return Opcode == STC;
3367}
3368
3369bool isVPINSRB(unsigned Opcode) {
3370 switch (Opcode) {
3371 case VPINSRBZrmi:
3372 case VPINSRBZrri:
3373 case VPINSRBrmi:
3374 case VPINSRBrri:
3375 return true;
3376 }
3377 return false;
3378}
3379
3380bool isLWPVAL(unsigned Opcode) {
3381 switch (Opcode) {
3382 case LWPVAL32rmi:
3383 case LWPVAL32rri:
3384 case LWPVAL64rmi:
3385 case LWPVAL64rri:
3386 return true;
3387 }
3388 return false;
3389}
3390
3391bool isKXORB(unsigned Opcode) {
3392 return Opcode == KXORBkk;
3393}
3394
3395bool isRSTORSSP(unsigned Opcode) {
3396 return Opcode == RSTORSSP;
3397}
3398
3399bool isVPRORQ(unsigned Opcode) {
3400 switch (Opcode) {
3401 case VPRORQZ128mbi:
3402 case VPRORQZ128mbik:
3403 case VPRORQZ128mbikz:
3404 case VPRORQZ128mi:
3405 case VPRORQZ128mik:
3406 case VPRORQZ128mikz:
3407 case VPRORQZ128ri:
3408 case VPRORQZ128rik:
3409 case VPRORQZ128rikz:
3410 case VPRORQZ256mbi:
3411 case VPRORQZ256mbik:
3412 case VPRORQZ256mbikz:
3413 case VPRORQZ256mi:
3414 case VPRORQZ256mik:
3415 case VPRORQZ256mikz:
3416 case VPRORQZ256ri:
3417 case VPRORQZ256rik:
3418 case VPRORQZ256rikz:
3419 case VPRORQZmbi:
3420 case VPRORQZmbik:
3421 case VPRORQZmbikz:
3422 case VPRORQZmi:
3423 case VPRORQZmik:
3424 case VPRORQZmikz:
3425 case VPRORQZri:
3426 case VPRORQZrik:
3427 case VPRORQZrikz:
3428 return true;
3429 }
3430 return false;
3431}
3432
3433bool isVSM3MSG1(unsigned Opcode) {
3434 switch (Opcode) {
3435 case VSM3MSG1rm:
3436 case VSM3MSG1rr:
3437 return true;
3438 }
3439 return false;
3440}
3441
3442bool isFICOM(unsigned Opcode) {
3443 switch (Opcode) {
3444 case FICOM16m:
3445 case FICOM32m:
3446 return true;
3447 }
3448 return false;
3449}
3450
3451bool isMAXPS(unsigned Opcode) {
3452 switch (Opcode) {
3453 case MAXPSrm:
3454 case MAXPSrr:
3455 return true;
3456 }
3457 return false;
3458}
3459
3460bool isFNCLEX(unsigned Opcode) {
3461 return Opcode == FNCLEX;
3462}
3463
3464bool isVMOVMSKPS(unsigned Opcode) {
3465 switch (Opcode) {
3466 case VMOVMSKPSYrr:
3467 case VMOVMSKPSrr:
3468 return true;
3469 }
3470 return false;
3471}
3472
3473bool isVPMOVDB(unsigned Opcode) {
3474 switch (Opcode) {
3475 case VPMOVDBZ128mr:
3476 case VPMOVDBZ128mrk:
3477 case VPMOVDBZ128rr:
3478 case VPMOVDBZ128rrk:
3479 case VPMOVDBZ128rrkz:
3480 case VPMOVDBZ256mr:
3481 case VPMOVDBZ256mrk:
3482 case VPMOVDBZ256rr:
3483 case VPMOVDBZ256rrk:
3484 case VPMOVDBZ256rrkz:
3485 case VPMOVDBZmr:
3486 case VPMOVDBZmrk:
3487 case VPMOVDBZrr:
3488 case VPMOVDBZrrk:
3489 case VPMOVDBZrrkz:
3490 return true;
3491 }
3492 return false;
3493}
3494
3495bool isLLWPCB(unsigned Opcode) {
3496 switch (Opcode) {
3497 case LLWPCB:
3498 case LLWPCB64:
3499 return true;
3500 }
3501 return false;
3502}
3503
3504bool isVMULSS(unsigned Opcode) {
3505 switch (Opcode) {
3506 case VMULSSZrm_Int:
3507 case VMULSSZrmk_Int:
3508 case VMULSSZrmkz_Int:
3509 case VMULSSZrr_Int:
3510 case VMULSSZrrb_Int:
3511 case VMULSSZrrbk_Int:
3512 case VMULSSZrrbkz_Int:
3513 case VMULSSZrrk_Int:
3514 case VMULSSZrrkz_Int:
3515 case VMULSSrm_Int:
3516 case VMULSSrr_Int:
3517 return true;
3518 }
3519 return false;
3520}
3521
3522bool isAESENCLAST(unsigned Opcode) {
3523 switch (Opcode) {
3524 case AESENCLASTrm:
3525 case AESENCLASTrr:
3526 return true;
3527 }
3528 return false;
3529}
3530
3531bool isTILEMOVROW(unsigned Opcode) {
3532 switch (Opcode) {
3533 case TILEMOVROWrte:
3534 case TILEMOVROWrti:
3535 return true;
3536 }
3537 return false;
3538}
3539
3540bool isVMINMAXPH(unsigned Opcode) {
3541 switch (Opcode) {
3542 case VMINMAXPHZ128rmbi:
3543 case VMINMAXPHZ128rmbik:
3544 case VMINMAXPHZ128rmbikz:
3545 case VMINMAXPHZ128rmi:
3546 case VMINMAXPHZ128rmik:
3547 case VMINMAXPHZ128rmikz:
3548 case VMINMAXPHZ128rri:
3549 case VMINMAXPHZ128rrik:
3550 case VMINMAXPHZ128rrikz:
3551 case VMINMAXPHZ256rmbi:
3552 case VMINMAXPHZ256rmbik:
3553 case VMINMAXPHZ256rmbikz:
3554 case VMINMAXPHZ256rmi:
3555 case VMINMAXPHZ256rmik:
3556 case VMINMAXPHZ256rmikz:
3557 case VMINMAXPHZ256rri:
3558 case VMINMAXPHZ256rrik:
3559 case VMINMAXPHZ256rrikz:
3560 case VMINMAXPHZrmbi:
3561 case VMINMAXPHZrmbik:
3562 case VMINMAXPHZrmbikz:
3563 case VMINMAXPHZrmi:
3564 case VMINMAXPHZrmik:
3565 case VMINMAXPHZrmikz:
3566 case VMINMAXPHZrri:
3567 case VMINMAXPHZrrib:
3568 case VMINMAXPHZrribk:
3569 case VMINMAXPHZrribkz:
3570 case VMINMAXPHZrrik:
3571 case VMINMAXPHZrrikz:
3572 return true;
3573 }
3574 return false;
3575}
3576
3577bool isVPMAXUB(unsigned Opcode) {
3578 switch (Opcode) {
3579 case VPMAXUBYrm:
3580 case VPMAXUBYrr:
3581 case VPMAXUBZ128rm:
3582 case VPMAXUBZ128rmk:
3583 case VPMAXUBZ128rmkz:
3584 case VPMAXUBZ128rr:
3585 case VPMAXUBZ128rrk:
3586 case VPMAXUBZ128rrkz:
3587 case VPMAXUBZ256rm:
3588 case VPMAXUBZ256rmk:
3589 case VPMAXUBZ256rmkz:
3590 case VPMAXUBZ256rr:
3591 case VPMAXUBZ256rrk:
3592 case VPMAXUBZ256rrkz:
3593 case VPMAXUBZrm:
3594 case VPMAXUBZrmk:
3595 case VPMAXUBZrmkz:
3596 case VPMAXUBZrr:
3597 case VPMAXUBZrrk:
3598 case VPMAXUBZrrkz:
3599 case VPMAXUBrm:
3600 case VPMAXUBrr:
3601 return true;
3602 }
3603 return false;
3604}
3605
3606bool isAAS(unsigned Opcode) {
3607 return Opcode == AAS;
3608}
3609
3610bool isFADD(unsigned Opcode) {
3611 switch (Opcode) {
3612 case ADD_F32m:
3613 case ADD_F64m:
3614 case ADD_FST0r:
3615 case ADD_FrST0:
3616 return true;
3617 }
3618 return false;
3619}
3620
3621bool isJMP(unsigned Opcode) {
3622 switch (Opcode) {
3623 case FARJMP32m:
3624 case JMP16m:
3625 case JMP16r:
3626 case JMP32m:
3627 case JMP32r:
3628 case JMP64m:
3629 case JMP64r:
3630 case JMP_1:
3631 case JMP_2:
3632 case JMP_4:
3633 return true;
3634 }
3635 return false;
3636}
3637
3638bool isXCRYPTECB(unsigned Opcode) {
3639 return Opcode == XCRYPTECB;
3640}
3641
3642bool isPFRCPIT1(unsigned Opcode) {
3643 switch (Opcode) {
3644 case PFRCPIT1rm:
3645 case PFRCPIT1rr:
3646 return true;
3647 }
3648 return false;
3649}
3650
3651bool isPMULHRW(unsigned Opcode) {
3652 switch (Opcode) {
3653 case PMULHRWrm:
3654 case PMULHRWrr:
3655 return true;
3656 }
3657 return false;
3658}
3659
3660bool isVCVTPH2PS(unsigned Opcode) {
3661 switch (Opcode) {
3662 case VCVTPH2PSYrm:
3663 case VCVTPH2PSYrr:
3664 case VCVTPH2PSZ128rm:
3665 case VCVTPH2PSZ128rmk:
3666 case VCVTPH2PSZ128rmkz:
3667 case VCVTPH2PSZ128rr:
3668 case VCVTPH2PSZ128rrk:
3669 case VCVTPH2PSZ128rrkz:
3670 case VCVTPH2PSZ256rm:
3671 case VCVTPH2PSZ256rmk:
3672 case VCVTPH2PSZ256rmkz:
3673 case VCVTPH2PSZ256rr:
3674 case VCVTPH2PSZ256rrk:
3675 case VCVTPH2PSZ256rrkz:
3676 case VCVTPH2PSZrm:
3677 case VCVTPH2PSZrmk:
3678 case VCVTPH2PSZrmkz:
3679 case VCVTPH2PSZrr:
3680 case VCVTPH2PSZrrb:
3681 case VCVTPH2PSZrrbk:
3682 case VCVTPH2PSZrrbkz:
3683 case VCVTPH2PSZrrk:
3684 case VCVTPH2PSZrrkz:
3685 case VCVTPH2PSrm:
3686 case VCVTPH2PSrr:
3687 return true;
3688 }
3689 return false;
3690}
3691
3692bool isVPBLENDVB(unsigned Opcode) {
3693 switch (Opcode) {
3694 case VPBLENDVBYrmr:
3695 case VPBLENDVBYrrr:
3696 case VPBLENDVBrmr:
3697 case VPBLENDVBrrr:
3698 return true;
3699 }
3700 return false;
3701}
3702
3703bool isPCMPESTRI(unsigned Opcode) {
3704 switch (Opcode) {
3705 case PCMPESTRIrmi:
3706 case PCMPESTRIrri:
3707 return true;
3708 }
3709 return false;
3710}
3711
3712bool isSENDUIPI(unsigned Opcode) {
3713 return Opcode == SENDUIPI;
3714}
3715
3716bool isFLDLN2(unsigned Opcode) {
3717 return Opcode == FLDLN2;
3718}
3719
3720bool isVPMACSWD(unsigned Opcode) {
3721 switch (Opcode) {
3722 case VPMACSWDrm:
3723 case VPMACSWDrr:
3724 return true;
3725 }
3726 return false;
3727}
3728
3729bool isSHA1MSG1(unsigned Opcode) {
3730 switch (Opcode) {
3731 case SHA1MSG1rm:
3732 case SHA1MSG1rr:
3733 return true;
3734 }
3735 return false;
3736}
3737
3738bool isVADDPS(unsigned Opcode) {
3739 switch (Opcode) {
3740 case VADDPSYrm:
3741 case VADDPSYrr:
3742 case VADDPSZ128rm:
3743 case VADDPSZ128rmb:
3744 case VADDPSZ128rmbk:
3745 case VADDPSZ128rmbkz:
3746 case VADDPSZ128rmk:
3747 case VADDPSZ128rmkz:
3748 case VADDPSZ128rr:
3749 case VADDPSZ128rrk:
3750 case VADDPSZ128rrkz:
3751 case VADDPSZ256rm:
3752 case VADDPSZ256rmb:
3753 case VADDPSZ256rmbk:
3754 case VADDPSZ256rmbkz:
3755 case VADDPSZ256rmk:
3756 case VADDPSZ256rmkz:
3757 case VADDPSZ256rr:
3758 case VADDPSZ256rrk:
3759 case VADDPSZ256rrkz:
3760 case VADDPSZrm:
3761 case VADDPSZrmb:
3762 case VADDPSZrmbk:
3763 case VADDPSZrmbkz:
3764 case VADDPSZrmk:
3765 case VADDPSZrmkz:
3766 case VADDPSZrr:
3767 case VADDPSZrrb:
3768 case VADDPSZrrbk:
3769 case VADDPSZrrbkz:
3770 case VADDPSZrrk:
3771 case VADDPSZrrkz:
3772 case VADDPSrm:
3773 case VADDPSrr:
3774 return true;
3775 }
3776 return false;
3777}
3778
3779bool isVCVTPS2DQ(unsigned Opcode) {
3780 switch (Opcode) {
3781 case VCVTPS2DQYrm:
3782 case VCVTPS2DQYrr:
3783 case VCVTPS2DQZ128rm:
3784 case VCVTPS2DQZ128rmb:
3785 case VCVTPS2DQZ128rmbk:
3786 case VCVTPS2DQZ128rmbkz:
3787 case VCVTPS2DQZ128rmk:
3788 case VCVTPS2DQZ128rmkz:
3789 case VCVTPS2DQZ128rr:
3790 case VCVTPS2DQZ128rrk:
3791 case VCVTPS2DQZ128rrkz:
3792 case VCVTPS2DQZ256rm:
3793 case VCVTPS2DQZ256rmb:
3794 case VCVTPS2DQZ256rmbk:
3795 case VCVTPS2DQZ256rmbkz:
3796 case VCVTPS2DQZ256rmk:
3797 case VCVTPS2DQZ256rmkz:
3798 case VCVTPS2DQZ256rr:
3799 case VCVTPS2DQZ256rrk:
3800 case VCVTPS2DQZ256rrkz:
3801 case VCVTPS2DQZrm:
3802 case VCVTPS2DQZrmb:
3803 case VCVTPS2DQZrmbk:
3804 case VCVTPS2DQZrmbkz:
3805 case VCVTPS2DQZrmk:
3806 case VCVTPS2DQZrmkz:
3807 case VCVTPS2DQZrr:
3808 case VCVTPS2DQZrrb:
3809 case VCVTPS2DQZrrbk:
3810 case VCVTPS2DQZrrbkz:
3811 case VCVTPS2DQZrrk:
3812 case VCVTPS2DQZrrkz:
3813 case VCVTPS2DQrm:
3814 case VCVTPS2DQrr:
3815 return true;
3816 }
3817 return false;
3818}
3819
3820bool isPFPNACC(unsigned Opcode) {
3821 switch (Opcode) {
3822 case PFPNACCrm:
3823 case PFPNACCrr:
3824 return true;
3825 }
3826 return false;
3827}
3828
3829bool isFMUL(unsigned Opcode) {
3830 switch (Opcode) {
3831 case MUL_F32m:
3832 case MUL_F64m:
3833 case MUL_FST0r:
3834 case MUL_FrST0:
3835 return true;
3836 }
3837 return false;
3838}
3839
3840bool isFNSAVE(unsigned Opcode) {
3841 return Opcode == FSAVEm;
3842}
3843
3844bool isCDQE(unsigned Opcode) {
3845 return Opcode == CDQE;
3846}
3847
3848bool isVPMACSDD(unsigned Opcode) {
3849 switch (Opcode) {
3850 case VPMACSDDrm:
3851 case VPMACSDDrr:
3852 return true;
3853 }
3854 return false;
3855}
3856
3857bool isVSQRTPS(unsigned Opcode) {
3858 switch (Opcode) {
3859 case VSQRTPSYm:
3860 case VSQRTPSYr:
3861 case VSQRTPSZ128m:
3862 case VSQRTPSZ128mb:
3863 case VSQRTPSZ128mbk:
3864 case VSQRTPSZ128mbkz:
3865 case VSQRTPSZ128mk:
3866 case VSQRTPSZ128mkz:
3867 case VSQRTPSZ128r:
3868 case VSQRTPSZ128rk:
3869 case VSQRTPSZ128rkz:
3870 case VSQRTPSZ256m:
3871 case VSQRTPSZ256mb:
3872 case VSQRTPSZ256mbk:
3873 case VSQRTPSZ256mbkz:
3874 case VSQRTPSZ256mk:
3875 case VSQRTPSZ256mkz:
3876 case VSQRTPSZ256r:
3877 case VSQRTPSZ256rk:
3878 case VSQRTPSZ256rkz:
3879 case VSQRTPSZm:
3880 case VSQRTPSZmb:
3881 case VSQRTPSZmbk:
3882 case VSQRTPSZmbkz:
3883 case VSQRTPSZmk:
3884 case VSQRTPSZmkz:
3885 case VSQRTPSZr:
3886 case VSQRTPSZrb:
3887 case VSQRTPSZrbk:
3888 case VSQRTPSZrbkz:
3889 case VSQRTPSZrk:
3890 case VSQRTPSZrkz:
3891 case VSQRTPSm:
3892 case VSQRTPSr:
3893 return true;
3894 }
3895 return false;
3896}
3897
3898bool isCMPSQ(unsigned Opcode) {
3899 return Opcode == CMPSQ;
3900}
3901
3902bool isVPSCATTERDD(unsigned Opcode) {
3903 switch (Opcode) {
3904 case VPSCATTERDDZ128mr:
3905 case VPSCATTERDDZ256mr:
3906 case VPSCATTERDDZmr:
3907 return true;
3908 }
3909 return false;
3910}
3911
3912bool isVCVTTSD2USIS(unsigned Opcode) {
3913 switch (Opcode) {
3914 case VCVTTSD2USI64Srm_Int:
3915 case VCVTTSD2USI64Srr_Int:
3916 case VCVTTSD2USI64Srrb_Int:
3917 case VCVTTSD2USISrm_Int:
3918 case VCVTTSD2USISrr_Int:
3919 case VCVTTSD2USISrrb_Int:
3920 return true;
3921 }
3922 return false;
3923}
3924
3925bool isVRNDSCALESD(unsigned Opcode) {
3926 switch (Opcode) {
3927 case VRNDSCALESDZrmi_Int:
3928 case VRNDSCALESDZrmik_Int:
3929 case VRNDSCALESDZrmikz_Int:
3930 case VRNDSCALESDZrri_Int:
3931 case VRNDSCALESDZrrib_Int:
3932 case VRNDSCALESDZrribk_Int:
3933 case VRNDSCALESDZrribkz_Int:
3934 case VRNDSCALESDZrrik_Int:
3935 case VRNDSCALESDZrrikz_Int:
3936 return true;
3937 }
3938 return false;
3939}
3940
3941bool isSUBPS(unsigned Opcode) {
3942 switch (Opcode) {
3943 case SUBPSrm:
3944 case SUBPSrr:
3945 return true;
3946 }
3947 return false;
3948}
3949
3950bool isVMAXSH(unsigned Opcode) {
3951 switch (Opcode) {
3952 case VMAXSHZrm_Int:
3953 case VMAXSHZrmk_Int:
3954 case VMAXSHZrmkz_Int:
3955 case VMAXSHZrr_Int:
3956 case VMAXSHZrrb_Int:
3957 case VMAXSHZrrbk_Int:
3958 case VMAXSHZrrbkz_Int:
3959 case VMAXSHZrrk_Int:
3960 case VMAXSHZrrkz_Int:
3961 return true;
3962 }
3963 return false;
3964}
3965
3966bool isFLDZ(unsigned Opcode) {
3967 return Opcode == LD_F0;
3968}
3969
3970bool isVFNMADD132SS(unsigned Opcode) {
3971 switch (Opcode) {
3972 case VFNMADD132SSZm_Int:
3973 case VFNMADD132SSZmk_Int:
3974 case VFNMADD132SSZmkz_Int:
3975 case VFNMADD132SSZr_Int:
3976 case VFNMADD132SSZrb_Int:
3977 case VFNMADD132SSZrbk_Int:
3978 case VFNMADD132SSZrbkz_Int:
3979 case VFNMADD132SSZrk_Int:
3980 case VFNMADD132SSZrkz_Int:
3981 case VFNMADD132SSm_Int:
3982 case VFNMADD132SSr_Int:
3983 return true;
3984 }
3985 return false;
3986}
3987
3988bool isLGDTW(unsigned Opcode) {
3989 return Opcode == LGDT16m;
3990}
3991
3992bool isTCVTROWPS2PHH(unsigned Opcode) {
3993 switch (Opcode) {
3994 case TCVTROWPS2PHHrte:
3995 case TCVTROWPS2PHHrti:
3996 return true;
3997 }
3998 return false;
3999}
4000
4001bool isINC(unsigned Opcode) {
4002 switch (Opcode) {
4003 case INC16m:
4004 case INC16m_EVEX:
4005 case INC16m_ND:
4006 case INC16m_NF:
4007 case INC16m_NF_ND:
4008 case INC16r:
4009 case INC16r_EVEX:
4010 case INC16r_ND:
4011 case INC16r_NF:
4012 case INC16r_NF_ND:
4013 case INC16r_alt:
4014 case INC32m:
4015 case INC32m_EVEX:
4016 case INC32m_ND:
4017 case INC32m_NF:
4018 case INC32m_NF_ND:
4019 case INC32r:
4020 case INC32r_EVEX:
4021 case INC32r_ND:
4022 case INC32r_NF:
4023 case INC32r_NF_ND:
4024 case INC32r_alt:
4025 case INC64m:
4026 case INC64m_EVEX:
4027 case INC64m_ND:
4028 case INC64m_NF:
4029 case INC64m_NF_ND:
4030 case INC64r:
4031 case INC64r_EVEX:
4032 case INC64r_ND:
4033 case INC64r_NF:
4034 case INC64r_NF_ND:
4035 case INC8m:
4036 case INC8m_EVEX:
4037 case INC8m_ND:
4038 case INC8m_NF:
4039 case INC8m_NF_ND:
4040 case INC8r:
4041 case INC8r_EVEX:
4042 case INC8r_ND:
4043 case INC8r_NF:
4044 case INC8r_NF_ND:
4045 return true;
4046 }
4047 return false;
4048}
4049
4050bool isPABSB(unsigned Opcode) {
4051 switch (Opcode) {
4052 case MMX_PABSBrm:
4053 case MMX_PABSBrr:
4054 case PABSBrm:
4055 case PABSBrr:
4056 return true;
4057 }
4058 return false;
4059}
4060
4061bool isVPANDN(unsigned Opcode) {
4062 switch (Opcode) {
4063 case VPANDNYrm:
4064 case VPANDNYrr:
4065 case VPANDNrm:
4066 case VPANDNrr:
4067 return true;
4068 }
4069 return false;
4070}
4071
4072bool isVPMAXUD(unsigned Opcode) {
4073 switch (Opcode) {
4074 case VPMAXUDYrm:
4075 case VPMAXUDYrr:
4076 case VPMAXUDZ128rm:
4077 case VPMAXUDZ128rmb:
4078 case VPMAXUDZ128rmbk:
4079 case VPMAXUDZ128rmbkz:
4080 case VPMAXUDZ128rmk:
4081 case VPMAXUDZ128rmkz:
4082 case VPMAXUDZ128rr:
4083 case VPMAXUDZ128rrk:
4084 case VPMAXUDZ128rrkz:
4085 case VPMAXUDZ256rm:
4086 case VPMAXUDZ256rmb:
4087 case VPMAXUDZ256rmbk:
4088 case VPMAXUDZ256rmbkz:
4089 case VPMAXUDZ256rmk:
4090 case VPMAXUDZ256rmkz:
4091 case VPMAXUDZ256rr:
4092 case VPMAXUDZ256rrk:
4093 case VPMAXUDZ256rrkz:
4094 case VPMAXUDZrm:
4095 case VPMAXUDZrmb:
4096 case VPMAXUDZrmbk:
4097 case VPMAXUDZrmbkz:
4098 case VPMAXUDZrmk:
4099 case VPMAXUDZrmkz:
4100 case VPMAXUDZrr:
4101 case VPMAXUDZrrk:
4102 case VPMAXUDZrrkz:
4103 case VPMAXUDrm:
4104 case VPMAXUDrr:
4105 return true;
4106 }
4107 return false;
4108}
4109
4110bool isVSHA512RNDS2(unsigned Opcode) {
4111 return Opcode == VSHA512RNDS2rr;
4112}
4113
4114bool isPHADDSW(unsigned Opcode) {
4115 switch (Opcode) {
4116 case MMX_PHADDSWrm:
4117 case MMX_PHADDSWrr:
4118 case PHADDSWrm:
4119 case PHADDSWrr:
4120 return true;
4121 }
4122 return false;
4123}
4124
4125bool isVPMOVSQW(unsigned Opcode) {
4126 switch (Opcode) {
4127 case VPMOVSQWZ128mr:
4128 case VPMOVSQWZ128mrk:
4129 case VPMOVSQWZ128rr:
4130 case VPMOVSQWZ128rrk:
4131 case VPMOVSQWZ128rrkz:
4132 case VPMOVSQWZ256mr:
4133 case VPMOVSQWZ256mrk:
4134 case VPMOVSQWZ256rr:
4135 case VPMOVSQWZ256rrk:
4136 case VPMOVSQWZ256rrkz:
4137 case VPMOVSQWZmr:
4138 case VPMOVSQWZmrk:
4139 case VPMOVSQWZrr:
4140 case VPMOVSQWZrrk:
4141 case VPMOVSQWZrrkz:
4142 return true;
4143 }
4144 return false;
4145}
4146
4147bool isADDSUBPS(unsigned Opcode) {
4148 switch (Opcode) {
4149 case ADDSUBPSrm:
4150 case ADDSUBPSrr:
4151 return true;
4152 }
4153 return false;
4154}
4155
4156bool isVPMACSSDQL(unsigned Opcode) {
4157 switch (Opcode) {
4158 case VPMACSSDQLrm:
4159 case VPMACSSDQLrr:
4160 return true;
4161 }
4162 return false;
4163}
4164
4165bool isPXOR(unsigned Opcode) {
4166 switch (Opcode) {
4167 case MMX_PXORrm:
4168 case MMX_PXORrr:
4169 case PXORrm:
4170 case PXORrr:
4171 return true;
4172 }
4173 return false;
4174}
4175
4176bool isVPSRAD(unsigned Opcode) {
4177 switch (Opcode) {
4178 case VPSRADYri:
4179 case VPSRADYrm:
4180 case VPSRADYrr:
4181 case VPSRADZ128mbi:
4182 case VPSRADZ128mbik:
4183 case VPSRADZ128mbikz:
4184 case VPSRADZ128mi:
4185 case VPSRADZ128mik:
4186 case VPSRADZ128mikz:
4187 case VPSRADZ128ri:
4188 case VPSRADZ128rik:
4189 case VPSRADZ128rikz:
4190 case VPSRADZ128rm:
4191 case VPSRADZ128rmk:
4192 case VPSRADZ128rmkz:
4193 case VPSRADZ128rr:
4194 case VPSRADZ128rrk:
4195 case VPSRADZ128rrkz:
4196 case VPSRADZ256mbi:
4197 case VPSRADZ256mbik:
4198 case VPSRADZ256mbikz:
4199 case VPSRADZ256mi:
4200 case VPSRADZ256mik:
4201 case VPSRADZ256mikz:
4202 case VPSRADZ256ri:
4203 case VPSRADZ256rik:
4204 case VPSRADZ256rikz:
4205 case VPSRADZ256rm:
4206 case VPSRADZ256rmk:
4207 case VPSRADZ256rmkz:
4208 case VPSRADZ256rr:
4209 case VPSRADZ256rrk:
4210 case VPSRADZ256rrkz:
4211 case VPSRADZmbi:
4212 case VPSRADZmbik:
4213 case VPSRADZmbikz:
4214 case VPSRADZmi:
4215 case VPSRADZmik:
4216 case VPSRADZmikz:
4217 case VPSRADZri:
4218 case VPSRADZrik:
4219 case VPSRADZrikz:
4220 case VPSRADZrm:
4221 case VPSRADZrmk:
4222 case VPSRADZrmkz:
4223 case VPSRADZrr:
4224 case VPSRADZrrk:
4225 case VPSRADZrrkz:
4226 case VPSRADri:
4227 case VPSRADrm:
4228 case VPSRADrr:
4229 return true;
4230 }
4231 return false;
4232}
4233
4234bool isVPSHAB(unsigned Opcode) {
4235 switch (Opcode) {
4236 case VPSHABmr:
4237 case VPSHABrm:
4238 case VPSHABrr:
4239 case VPSHABrr_REV:
4240 return true;
4241 }
4242 return false;
4243}
4244
4245bool isBTR(unsigned Opcode) {
4246 switch (Opcode) {
4247 case BTR16mi8:
4248 case BTR16mr:
4249 case BTR16ri8:
4250 case BTR16rr:
4251 case BTR32mi8:
4252 case BTR32mr:
4253 case BTR32ri8:
4254 case BTR32rr:
4255 case BTR64mi8:
4256 case BTR64mr:
4257 case BTR64ri8:
4258 case BTR64rr:
4259 return true;
4260 }
4261 return false;
4262}
4263
4264bool isKORW(unsigned Opcode) {
4265 return Opcode == KORWkk;
4266}
4267
4268bool isVRANGESS(unsigned Opcode) {
4269 switch (Opcode) {
4270 case VRANGESSZrmi:
4271 case VRANGESSZrmik:
4272 case VRANGESSZrmikz:
4273 case VRANGESSZrri:
4274 case VRANGESSZrrib:
4275 case VRANGESSZrribk:
4276 case VRANGESSZrribkz:
4277 case VRANGESSZrrik:
4278 case VRANGESSZrrikz:
4279 return true;
4280 }
4281 return false;
4282}
4283
4284bool isVCMPPS(unsigned Opcode) {
4285 switch (Opcode) {
4286 case VCMPPSYrmi:
4287 case VCMPPSYrri:
4288 case VCMPPSZ128rmbi:
4289 case VCMPPSZ128rmbik:
4290 case VCMPPSZ128rmi:
4291 case VCMPPSZ128rmik:
4292 case VCMPPSZ128rri:
4293 case VCMPPSZ128rrik:
4294 case VCMPPSZ256rmbi:
4295 case VCMPPSZ256rmbik:
4296 case VCMPPSZ256rmi:
4297 case VCMPPSZ256rmik:
4298 case VCMPPSZ256rri:
4299 case VCMPPSZ256rrik:
4300 case VCMPPSZrmbi:
4301 case VCMPPSZrmbik:
4302 case VCMPPSZrmi:
4303 case VCMPPSZrmik:
4304 case VCMPPSZrri:
4305 case VCMPPSZrrib:
4306 case VCMPPSZrribk:
4307 case VCMPPSZrrik:
4308 case VCMPPSrmi:
4309 case VCMPPSrri:
4310 return true;
4311 }
4312 return false;
4313}
4314
4315bool isVPLZCNTD(unsigned Opcode) {
4316 switch (Opcode) {
4317 case VPLZCNTDZ128rm:
4318 case VPLZCNTDZ128rmb:
4319 case VPLZCNTDZ128rmbk:
4320 case VPLZCNTDZ128rmbkz:
4321 case VPLZCNTDZ128rmk:
4322 case VPLZCNTDZ128rmkz:
4323 case VPLZCNTDZ128rr:
4324 case VPLZCNTDZ128rrk:
4325 case VPLZCNTDZ128rrkz:
4326 case VPLZCNTDZ256rm:
4327 case VPLZCNTDZ256rmb:
4328 case VPLZCNTDZ256rmbk:
4329 case VPLZCNTDZ256rmbkz:
4330 case VPLZCNTDZ256rmk:
4331 case VPLZCNTDZ256rmkz:
4332 case VPLZCNTDZ256rr:
4333 case VPLZCNTDZ256rrk:
4334 case VPLZCNTDZ256rrkz:
4335 case VPLZCNTDZrm:
4336 case VPLZCNTDZrmb:
4337 case VPLZCNTDZrmbk:
4338 case VPLZCNTDZrmbkz:
4339 case VPLZCNTDZrmk:
4340 case VPLZCNTDZrmkz:
4341 case VPLZCNTDZrr:
4342 case VPLZCNTDZrrk:
4343 case VPLZCNTDZrrkz:
4344 return true;
4345 }
4346 return false;
4347}
4348
4349bool isTDPBUUD(unsigned Opcode) {
4350 return Opcode == TDPBUUD;
4351}
4352
4353bool isROUNDPS(unsigned Opcode) {
4354 switch (Opcode) {
4355 case ROUNDPSmi:
4356 case ROUNDPSri:
4357 return true;
4358 }
4359 return false;
4360}
4361
4362bool isFABS(unsigned Opcode) {
4363 return Opcode == ABS_F;
4364}
4365
4366bool isSUBPD(unsigned Opcode) {
4367 switch (Opcode) {
4368 case SUBPDrm:
4369 case SUBPDrr:
4370 return true;
4371 }
4372 return false;
4373}
4374
4375bool isGF2P8MULB(unsigned Opcode) {
4376 switch (Opcode) {
4377 case GF2P8MULBrm:
4378 case GF2P8MULBrr:
4379 return true;
4380 }
4381 return false;
4382}
4383
4384bool isTZMSK(unsigned Opcode) {
4385 switch (Opcode) {
4386 case TZMSK32rm:
4387 case TZMSK32rr:
4388 case TZMSK64rm:
4389 case TZMSK64rr:
4390 return true;
4391 }
4392 return false;
4393}
4394
4395bool isVMINMAXSD(unsigned Opcode) {
4396 switch (Opcode) {
4397 case VMINMAXSDrmi_Int:
4398 case VMINMAXSDrmik_Int:
4399 case VMINMAXSDrmikz_Int:
4400 case VMINMAXSDrri_Int:
4401 case VMINMAXSDrrib_Int:
4402 case VMINMAXSDrribk_Int:
4403 case VMINMAXSDrribkz_Int:
4404 case VMINMAXSDrrik_Int:
4405 case VMINMAXSDrrikz_Int:
4406 return true;
4407 }
4408 return false;
4409}
4410
4411bool isANDPS(unsigned Opcode) {
4412 switch (Opcode) {
4413 case ANDPSrm:
4414 case ANDPSrr:
4415 return true;
4416 }
4417 return false;
4418}
4419
4420bool isVEXTRACTF32X8(unsigned Opcode) {
4421 switch (Opcode) {
4422 case VEXTRACTF32X8Zmri:
4423 case VEXTRACTF32X8Zmrik:
4424 case VEXTRACTF32X8Zrri:
4425 case VEXTRACTF32X8Zrrik:
4426 case VEXTRACTF32X8Zrrikz:
4427 return true;
4428 }
4429 return false;
4430}
4431
4432bool isSEAMRET(unsigned Opcode) {
4433 return Opcode == SEAMRET;
4434}
4435
4436bool isVPCOMW(unsigned Opcode) {
4437 switch (Opcode) {
4438 case VPCOMWmi:
4439 case VPCOMWri:
4440 return true;
4441 }
4442 return false;
4443}
4444
4445bool isVFIXUPIMMPD(unsigned Opcode) {
4446 switch (Opcode) {
4447 case VFIXUPIMMPDZ128rmbi:
4448 case VFIXUPIMMPDZ128rmbik:
4449 case VFIXUPIMMPDZ128rmbikz:
4450 case VFIXUPIMMPDZ128rmi:
4451 case VFIXUPIMMPDZ128rmik:
4452 case VFIXUPIMMPDZ128rmikz:
4453 case VFIXUPIMMPDZ128rri:
4454 case VFIXUPIMMPDZ128rrik:
4455 case VFIXUPIMMPDZ128rrikz:
4456 case VFIXUPIMMPDZ256rmbi:
4457 case VFIXUPIMMPDZ256rmbik:
4458 case VFIXUPIMMPDZ256rmbikz:
4459 case VFIXUPIMMPDZ256rmi:
4460 case VFIXUPIMMPDZ256rmik:
4461 case VFIXUPIMMPDZ256rmikz:
4462 case VFIXUPIMMPDZ256rri:
4463 case VFIXUPIMMPDZ256rrik:
4464 case VFIXUPIMMPDZ256rrikz:
4465 case VFIXUPIMMPDZrmbi:
4466 case VFIXUPIMMPDZrmbik:
4467 case VFIXUPIMMPDZrmbikz:
4468 case VFIXUPIMMPDZrmi:
4469 case VFIXUPIMMPDZrmik:
4470 case VFIXUPIMMPDZrmikz:
4471 case VFIXUPIMMPDZrri:
4472 case VFIXUPIMMPDZrrib:
4473 case VFIXUPIMMPDZrribk:
4474 case VFIXUPIMMPDZrribkz:
4475 case VFIXUPIMMPDZrrik:
4476 case VFIXUPIMMPDZrrikz:
4477 return true;
4478 }
4479 return false;
4480}
4481
4482bool isKANDND(unsigned Opcode) {
4483 return Opcode == KANDNDkk;
4484}
4485
4486bool isVMRESUME(unsigned Opcode) {
4487 return Opcode == VMRESUME;
4488}
4489
4490bool isCVTPD2DQ(unsigned Opcode) {
4491 switch (Opcode) {
4492 case CVTPD2DQrm:
4493 case CVTPD2DQrr:
4494 return true;
4495 }
4496 return false;
4497}
4498
4499bool isVFNMADD213PS(unsigned Opcode) {
4500 switch (Opcode) {
4501 case VFNMADD213PSYm:
4502 case VFNMADD213PSYr:
4503 case VFNMADD213PSZ128m:
4504 case VFNMADD213PSZ128mb:
4505 case VFNMADD213PSZ128mbk:
4506 case VFNMADD213PSZ128mbkz:
4507 case VFNMADD213PSZ128mk:
4508 case VFNMADD213PSZ128mkz:
4509 case VFNMADD213PSZ128r:
4510 case VFNMADD213PSZ128rk:
4511 case VFNMADD213PSZ128rkz:
4512 case VFNMADD213PSZ256m:
4513 case VFNMADD213PSZ256mb:
4514 case VFNMADD213PSZ256mbk:
4515 case VFNMADD213PSZ256mbkz:
4516 case VFNMADD213PSZ256mk:
4517 case VFNMADD213PSZ256mkz:
4518 case VFNMADD213PSZ256r:
4519 case VFNMADD213PSZ256rk:
4520 case VFNMADD213PSZ256rkz:
4521 case VFNMADD213PSZm:
4522 case VFNMADD213PSZmb:
4523 case VFNMADD213PSZmbk:
4524 case VFNMADD213PSZmbkz:
4525 case VFNMADD213PSZmk:
4526 case VFNMADD213PSZmkz:
4527 case VFNMADD213PSZr:
4528 case VFNMADD213PSZrb:
4529 case VFNMADD213PSZrbk:
4530 case VFNMADD213PSZrbkz:
4531 case VFNMADD213PSZrk:
4532 case VFNMADD213PSZrkz:
4533 case VFNMADD213PSm:
4534 case VFNMADD213PSr:
4535 return true;
4536 }
4537 return false;
4538}
4539
4540bool isVPEXTRD(unsigned Opcode) {
4541 switch (Opcode) {
4542 case VPEXTRDZmri:
4543 case VPEXTRDZrri:
4544 case VPEXTRDmri:
4545 case VPEXTRDrri:
4546 return true;
4547 }
4548 return false;
4549}
4550
4551bool isPACKUSWB(unsigned Opcode) {
4552 switch (Opcode) {
4553 case MMX_PACKUSWBrm:
4554 case MMX_PACKUSWBrr:
4555 case PACKUSWBrm:
4556 case PACKUSWBrr:
4557 return true;
4558 }
4559 return false;
4560}
4561
4562bool isVEXTRACTI32X8(unsigned Opcode) {
4563 switch (Opcode) {
4564 case VEXTRACTI32X8Zmri:
4565 case VEXTRACTI32X8Zmrik:
4566 case VEXTRACTI32X8Zrri:
4567 case VEXTRACTI32X8Zrrik:
4568 case VEXTRACTI32X8Zrrikz:
4569 return true;
4570 }
4571 return false;
4572}
4573
4574bool isVHADDPD(unsigned Opcode) {
4575 switch (Opcode) {
4576 case VHADDPDYrm:
4577 case VHADDPDYrr:
4578 case VHADDPDrm:
4579 case VHADDPDrr:
4580 return true;
4581 }
4582 return false;
4583}
4584
4585bool isVPSADBW(unsigned Opcode) {
4586 switch (Opcode) {
4587 case VPSADBWYrm:
4588 case VPSADBWYrr:
4589 case VPSADBWZ128rm:
4590 case VPSADBWZ128rr:
4591 case VPSADBWZ256rm:
4592 case VPSADBWZ256rr:
4593 case VPSADBWZrm:
4594 case VPSADBWZrr:
4595 case VPSADBWrm:
4596 case VPSADBWrr:
4597 return true;
4598 }
4599 return false;
4600}
4601
4602bool isMOVDQ2Q(unsigned Opcode) {
4603 return Opcode == MMX_MOVDQ2Qrr;
4604}
4605
4606bool isPUNPCKHBW(unsigned Opcode) {
4607 switch (Opcode) {
4608 case MMX_PUNPCKHBWrm:
4609 case MMX_PUNPCKHBWrr:
4610 case PUNPCKHBWrm:
4611 case PUNPCKHBWrr:
4612 return true;
4613 }
4614 return false;
4615}
4616
4617bool isXOR(unsigned Opcode) {
4618 switch (Opcode) {
4619 case XOR16i16:
4620 case XOR16mi:
4621 case XOR16mi8:
4622 case XOR16mi8_EVEX:
4623 case XOR16mi8_ND:
4624 case XOR16mi8_NF:
4625 case XOR16mi8_NF_ND:
4626 case XOR16mi_EVEX:
4627 case XOR16mi_ND:
4628 case XOR16mi_NF:
4629 case XOR16mi_NF_ND:
4630 case XOR16mr:
4631 case XOR16mr_EVEX:
4632 case XOR16mr_ND:
4633 case XOR16mr_NF:
4634 case XOR16mr_NF_ND:
4635 case XOR16ri:
4636 case XOR16ri8:
4637 case XOR16ri8_EVEX:
4638 case XOR16ri8_ND:
4639 case XOR16ri8_NF:
4640 case XOR16ri8_NF_ND:
4641 case XOR16ri_EVEX:
4642 case XOR16ri_ND:
4643 case XOR16ri_NF:
4644 case XOR16ri_NF_ND:
4645 case XOR16rm:
4646 case XOR16rm_EVEX:
4647 case XOR16rm_ND:
4648 case XOR16rm_NF:
4649 case XOR16rm_NF_ND:
4650 case XOR16rr:
4651 case XOR16rr_EVEX:
4652 case XOR16rr_EVEX_REV:
4653 case XOR16rr_ND:
4654 case XOR16rr_ND_REV:
4655 case XOR16rr_NF:
4656 case XOR16rr_NF_ND:
4657 case XOR16rr_NF_ND_REV:
4658 case XOR16rr_NF_REV:
4659 case XOR16rr_REV:
4660 case XOR32i32:
4661 case XOR32mi:
4662 case XOR32mi8:
4663 case XOR32mi8_EVEX:
4664 case XOR32mi8_ND:
4665 case XOR32mi8_NF:
4666 case XOR32mi8_NF_ND:
4667 case XOR32mi_EVEX:
4668 case XOR32mi_ND:
4669 case XOR32mi_NF:
4670 case XOR32mi_NF_ND:
4671 case XOR32mr:
4672 case XOR32mr_EVEX:
4673 case XOR32mr_ND:
4674 case XOR32mr_NF:
4675 case XOR32mr_NF_ND:
4676 case XOR32ri:
4677 case XOR32ri8:
4678 case XOR32ri8_EVEX:
4679 case XOR32ri8_ND:
4680 case XOR32ri8_NF:
4681 case XOR32ri8_NF_ND:
4682 case XOR32ri_EVEX:
4683 case XOR32ri_ND:
4684 case XOR32ri_NF:
4685 case XOR32ri_NF_ND:
4686 case XOR32rm:
4687 case XOR32rm_EVEX:
4688 case XOR32rm_ND:
4689 case XOR32rm_NF:
4690 case XOR32rm_NF_ND:
4691 case XOR32rr:
4692 case XOR32rr_EVEX:
4693 case XOR32rr_EVEX_REV:
4694 case XOR32rr_ND:
4695 case XOR32rr_ND_REV:
4696 case XOR32rr_NF:
4697 case XOR32rr_NF_ND:
4698 case XOR32rr_NF_ND_REV:
4699 case XOR32rr_NF_REV:
4700 case XOR32rr_REV:
4701 case XOR64i32:
4702 case XOR64mi32:
4703 case XOR64mi32_EVEX:
4704 case XOR64mi32_ND:
4705 case XOR64mi32_NF:
4706 case XOR64mi32_NF_ND:
4707 case XOR64mi8:
4708 case XOR64mi8_EVEX:
4709 case XOR64mi8_ND:
4710 case XOR64mi8_NF:
4711 case XOR64mi8_NF_ND:
4712 case XOR64mr:
4713 case XOR64mr_EVEX:
4714 case XOR64mr_ND:
4715 case XOR64mr_NF:
4716 case XOR64mr_NF_ND:
4717 case XOR64ri32:
4718 case XOR64ri32_EVEX:
4719 case XOR64ri32_ND:
4720 case XOR64ri32_NF:
4721 case XOR64ri32_NF_ND:
4722 case XOR64ri8:
4723 case XOR64ri8_EVEX:
4724 case XOR64ri8_ND:
4725 case XOR64ri8_NF:
4726 case XOR64ri8_NF_ND:
4727 case XOR64rm:
4728 case XOR64rm_EVEX:
4729 case XOR64rm_ND:
4730 case XOR64rm_NF:
4731 case XOR64rm_NF_ND:
4732 case XOR64rr:
4733 case XOR64rr_EVEX:
4734 case XOR64rr_EVEX_REV:
4735 case XOR64rr_ND:
4736 case XOR64rr_ND_REV:
4737 case XOR64rr_NF:
4738 case XOR64rr_NF_ND:
4739 case XOR64rr_NF_ND_REV:
4740 case XOR64rr_NF_REV:
4741 case XOR64rr_REV:
4742 case XOR8i8:
4743 case XOR8mi:
4744 case XOR8mi8:
4745 case XOR8mi_EVEX:
4746 case XOR8mi_ND:
4747 case XOR8mi_NF:
4748 case XOR8mi_NF_ND:
4749 case XOR8mr:
4750 case XOR8mr_EVEX:
4751 case XOR8mr_ND:
4752 case XOR8mr_NF:
4753 case XOR8mr_NF_ND:
4754 case XOR8ri:
4755 case XOR8ri8:
4756 case XOR8ri_EVEX:
4757 case XOR8ri_ND:
4758 case XOR8ri_NF:
4759 case XOR8ri_NF_ND:
4760 case XOR8rm:
4761 case XOR8rm_EVEX:
4762 case XOR8rm_ND:
4763 case XOR8rm_NF:
4764 case XOR8rm_NF_ND:
4765 case XOR8rr:
4766 case XOR8rr_EVEX:
4767 case XOR8rr_EVEX_REV:
4768 case XOR8rr_ND:
4769 case XOR8rr_ND_REV:
4770 case XOR8rr_NF:
4771 case XOR8rr_NF_ND:
4772 case XOR8rr_NF_ND_REV:
4773 case XOR8rr_NF_REV:
4774 case XOR8rr_REV:
4775 return true;
4776 }
4777 return false;
4778}
4779
4780bool isPSIGNB(unsigned Opcode) {
4781 switch (Opcode) {
4782 case MMX_PSIGNBrm:
4783 case MMX_PSIGNBrr:
4784 case PSIGNBrm:
4785 case PSIGNBrr:
4786 return true;
4787 }
4788 return false;
4789}
4790
4791bool isVPHADDSW(unsigned Opcode) {
4792 switch (Opcode) {
4793 case VPHADDSWYrm:
4794 case VPHADDSWYrr:
4795 case VPHADDSWrm:
4796 case VPHADDSWrr:
4797 return true;
4798 }
4799 return false;
4800}
4801
4802bool isFADDP(unsigned Opcode) {
4803 return Opcode == ADD_FPrST0;
4804}
4805
4806bool isNEG(unsigned Opcode) {
4807 switch (Opcode) {
4808 case NEG16m:
4809 case NEG16m_EVEX:
4810 case NEG16m_ND:
4811 case NEG16m_NF:
4812 case NEG16m_NF_ND:
4813 case NEG16r:
4814 case NEG16r_EVEX:
4815 case NEG16r_ND:
4816 case NEG16r_NF:
4817 case NEG16r_NF_ND:
4818 case NEG32m:
4819 case NEG32m_EVEX:
4820 case NEG32m_ND:
4821 case NEG32m_NF:
4822 case NEG32m_NF_ND:
4823 case NEG32r:
4824 case NEG32r_EVEX:
4825 case NEG32r_ND:
4826 case NEG32r_NF:
4827 case NEG32r_NF_ND:
4828 case NEG64m:
4829 case NEG64m_EVEX:
4830 case NEG64m_ND:
4831 case NEG64m_NF:
4832 case NEG64m_NF_ND:
4833 case NEG64r:
4834 case NEG64r_EVEX:
4835 case NEG64r_ND:
4836 case NEG64r_NF:
4837 case NEG64r_NF_ND:
4838 case NEG8m:
4839 case NEG8m_EVEX:
4840 case NEG8m_ND:
4841 case NEG8m_NF:
4842 case NEG8m_NF_ND:
4843 case NEG8r:
4844 case NEG8r_EVEX:
4845 case NEG8r_ND:
4846 case NEG8r_NF:
4847 case NEG8r_NF_ND:
4848 return true;
4849 }
4850 return false;
4851}
4852
4853bool isFLDLG2(unsigned Opcode) {
4854 return Opcode == FLDLG2;
4855}
4856
4857bool isFNOP(unsigned Opcode) {
4858 return Opcode == FNOP;
4859}
4860
4861bool isVMINSS(unsigned Opcode) {
4862 switch (Opcode) {
4863 case VMINSSZrm_Int:
4864 case VMINSSZrmk_Int:
4865 case VMINSSZrmkz_Int:
4866 case VMINSSZrr_Int:
4867 case VMINSSZrrb_Int:
4868 case VMINSSZrrbk_Int:
4869 case VMINSSZrrbkz_Int:
4870 case VMINSSZrrk_Int:
4871 case VMINSSZrrkz_Int:
4872 case VMINSSrm_Int:
4873 case VMINSSrr_Int:
4874 return true;
4875 }
4876 return false;
4877}
4878
4879bool isPCMPISTRM(unsigned Opcode) {
4880 switch (Opcode) {
4881 case PCMPISTRMrmi:
4882 case PCMPISTRMrri:
4883 return true;
4884 }
4885 return false;
4886}
4887
4888bool isVFMADD132SS(unsigned Opcode) {
4889 switch (Opcode) {
4890 case VFMADD132SSZm_Int:
4891 case VFMADD132SSZmk_Int:
4892 case VFMADD132SSZmkz_Int:
4893 case VFMADD132SSZr_Int:
4894 case VFMADD132SSZrb_Int:
4895 case VFMADD132SSZrbk_Int:
4896 case VFMADD132SSZrbkz_Int:
4897 case VFMADD132SSZrk_Int:
4898 case VFMADD132SSZrkz_Int:
4899 case VFMADD132SSm_Int:
4900 case VFMADD132SSr_Int:
4901 return true;
4902 }
4903 return false;
4904}
4905
4906bool isFDIVRP(unsigned Opcode) {
4907 return Opcode == DIVR_FPrST0;
4908}
4909
4910bool isPUSHAL(unsigned Opcode) {
4911 return Opcode == PUSHA32;
4912}
4913
4914bool isSUBSD(unsigned Opcode) {
4915 switch (Opcode) {
4916 case SUBSDrm_Int:
4917 case SUBSDrr_Int:
4918 return true;
4919 }
4920 return false;
4921}
4922
4923bool isVPBLENDMQ(unsigned Opcode) {
4924 switch (Opcode) {
4925 case VPBLENDMQZ128rm:
4926 case VPBLENDMQZ128rmb:
4927 case VPBLENDMQZ128rmbk:
4928 case VPBLENDMQZ128rmbkz:
4929 case VPBLENDMQZ128rmk:
4930 case VPBLENDMQZ128rmkz:
4931 case VPBLENDMQZ128rr:
4932 case VPBLENDMQZ128rrk:
4933 case VPBLENDMQZ128rrkz:
4934 case VPBLENDMQZ256rm:
4935 case VPBLENDMQZ256rmb:
4936 case VPBLENDMQZ256rmbk:
4937 case VPBLENDMQZ256rmbkz:
4938 case VPBLENDMQZ256rmk:
4939 case VPBLENDMQZ256rmkz:
4940 case VPBLENDMQZ256rr:
4941 case VPBLENDMQZ256rrk:
4942 case VPBLENDMQZ256rrkz:
4943 case VPBLENDMQZrm:
4944 case VPBLENDMQZrmb:
4945 case VPBLENDMQZrmbk:
4946 case VPBLENDMQZrmbkz:
4947 case VPBLENDMQZrmk:
4948 case VPBLENDMQZrmkz:
4949 case VPBLENDMQZrr:
4950 case VPBLENDMQZrrk:
4951 case VPBLENDMQZrrkz:
4952 return true;
4953 }
4954 return false;
4955}
4956
4957bool isVPMACSDQL(unsigned Opcode) {
4958 switch (Opcode) {
4959 case VPMACSDQLrm:
4960 case VPMACSDQLrr:
4961 return true;
4962 }
4963 return false;
4964}
4965
4966bool isVGATHERDPS(unsigned Opcode) {
4967 switch (Opcode) {
4968 case VGATHERDPSYrm:
4969 case VGATHERDPSZ128rm:
4970 case VGATHERDPSZ256rm:
4971 case VGATHERDPSZrm:
4972 case VGATHERDPSrm:
4973 return true;
4974 }
4975 return false;
4976}
4977
4978bool isSYSRET(unsigned Opcode) {
4979 return Opcode == SYSRET;
4980}
4981
4982bool isVPADDB(unsigned Opcode) {
4983 switch (Opcode) {
4984 case VPADDBYrm:
4985 case VPADDBYrr:
4986 case VPADDBZ128rm:
4987 case VPADDBZ128rmk:
4988 case VPADDBZ128rmkz:
4989 case VPADDBZ128rr:
4990 case VPADDBZ128rrk:
4991 case VPADDBZ128rrkz:
4992 case VPADDBZ256rm:
4993 case VPADDBZ256rmk:
4994 case VPADDBZ256rmkz:
4995 case VPADDBZ256rr:
4996 case VPADDBZ256rrk:
4997 case VPADDBZ256rrkz:
4998 case VPADDBZrm:
4999 case VPADDBZrmk:
5000 case VPADDBZrmkz:
5001 case VPADDBZrr:
5002 case VPADDBZrrk:
5003 case VPADDBZrrkz:
5004 case VPADDBrm:
5005 case VPADDBrr:
5006 return true;
5007 }
5008 return false;
5009}
5010
5011bool isXEND(unsigned Opcode) {
5012 return Opcode == XEND;
5013}
5014
5015bool isWRSSD(unsigned Opcode) {
5016 switch (Opcode) {
5017 case WRSSD:
5018 case WRSSD_EVEX:
5019 return true;
5020 }
5021 return false;
5022}
5023
5024bool isVMINMAXSS(unsigned Opcode) {
5025 switch (Opcode) {
5026 case VMINMAXSSrmi_Int:
5027 case VMINMAXSSrmik_Int:
5028 case VMINMAXSSrmikz_Int:
5029 case VMINMAXSSrri_Int:
5030 case VMINMAXSSrrib_Int:
5031 case VMINMAXSSrribk_Int:
5032 case VMINMAXSSrribkz_Int:
5033 case VMINMAXSSrrik_Int:
5034 case VMINMAXSSrrikz_Int:
5035 return true;
5036 }
5037 return false;
5038}
5039
5040bool isVCVTDQ2PH(unsigned Opcode) {
5041 switch (Opcode) {
5042 case VCVTDQ2PHZ128rm:
5043 case VCVTDQ2PHZ128rmb:
5044 case VCVTDQ2PHZ128rmbk:
5045 case VCVTDQ2PHZ128rmbkz:
5046 case VCVTDQ2PHZ128rmk:
5047 case VCVTDQ2PHZ128rmkz:
5048 case VCVTDQ2PHZ128rr:
5049 case VCVTDQ2PHZ128rrk:
5050 case VCVTDQ2PHZ128rrkz:
5051 case VCVTDQ2PHZ256rm:
5052 case VCVTDQ2PHZ256rmb:
5053 case VCVTDQ2PHZ256rmbk:
5054 case VCVTDQ2PHZ256rmbkz:
5055 case VCVTDQ2PHZ256rmk:
5056 case VCVTDQ2PHZ256rmkz:
5057 case VCVTDQ2PHZ256rr:
5058 case VCVTDQ2PHZ256rrk:
5059 case VCVTDQ2PHZ256rrkz:
5060 case VCVTDQ2PHZrm:
5061 case VCVTDQ2PHZrmb:
5062 case VCVTDQ2PHZrmbk:
5063 case VCVTDQ2PHZrmbkz:
5064 case VCVTDQ2PHZrmk:
5065 case VCVTDQ2PHZrmkz:
5066 case VCVTDQ2PHZrr:
5067 case VCVTDQ2PHZrrb:
5068 case VCVTDQ2PHZrrbk:
5069 case VCVTDQ2PHZrrbkz:
5070 case VCVTDQ2PHZrrk:
5071 case VCVTDQ2PHZrrkz:
5072 return true;
5073 }
5074 return false;
5075}
5076
5077bool isCVTPD2PS(unsigned Opcode) {
5078 switch (Opcode) {
5079 case CVTPD2PSrm:
5080 case CVTPD2PSrr:
5081 return true;
5082 }
5083 return false;
5084}
5085
5086bool isMAXPD(unsigned Opcode) {
5087 switch (Opcode) {
5088 case MAXPDrm:
5089 case MAXPDrr:
5090 return true;
5091 }
5092 return false;
5093}
5094
5095bool isRCPSS(unsigned Opcode) {
5096 switch (Opcode) {
5097 case RCPSSm_Int:
5098 case RCPSSr_Int:
5099 return true;
5100 }
5101 return false;
5102}
5103
5104bool isVMOVAPD(unsigned Opcode) {
5105 switch (Opcode) {
5106 case VMOVAPDYmr:
5107 case VMOVAPDYrm:
5108 case VMOVAPDYrr:
5109 case VMOVAPDYrr_REV:
5110 case VMOVAPDZ128mr:
5111 case VMOVAPDZ128mrk:
5112 case VMOVAPDZ128rm:
5113 case VMOVAPDZ128rmk:
5114 case VMOVAPDZ128rmkz:
5115 case VMOVAPDZ128rr:
5116 case VMOVAPDZ128rr_REV:
5117 case VMOVAPDZ128rrk:
5118 case VMOVAPDZ128rrk_REV:
5119 case VMOVAPDZ128rrkz:
5120 case VMOVAPDZ128rrkz_REV:
5121 case VMOVAPDZ256mr:
5122 case VMOVAPDZ256mrk:
5123 case VMOVAPDZ256rm:
5124 case VMOVAPDZ256rmk:
5125 case VMOVAPDZ256rmkz:
5126 case VMOVAPDZ256rr:
5127 case VMOVAPDZ256rr_REV:
5128 case VMOVAPDZ256rrk:
5129 case VMOVAPDZ256rrk_REV:
5130 case VMOVAPDZ256rrkz:
5131 case VMOVAPDZ256rrkz_REV:
5132 case VMOVAPDZmr:
5133 case VMOVAPDZmrk:
5134 case VMOVAPDZrm:
5135 case VMOVAPDZrmk:
5136 case VMOVAPDZrmkz:
5137 case VMOVAPDZrr:
5138 case VMOVAPDZrr_REV:
5139 case VMOVAPDZrrk:
5140 case VMOVAPDZrrk_REV:
5141 case VMOVAPDZrrkz:
5142 case VMOVAPDZrrkz_REV:
5143 case VMOVAPDmr:
5144 case VMOVAPDrm:
5145 case VMOVAPDrr:
5146 case VMOVAPDrr_REV:
5147 return true;
5148 }
5149 return false;
5150}
5151
5152bool isVPSUBSB(unsigned Opcode) {
5153 switch (Opcode) {
5154 case VPSUBSBYrm:
5155 case VPSUBSBYrr:
5156 case VPSUBSBZ128rm:
5157 case VPSUBSBZ128rmk:
5158 case VPSUBSBZ128rmkz:
5159 case VPSUBSBZ128rr:
5160 case VPSUBSBZ128rrk:
5161 case VPSUBSBZ128rrkz:
5162 case VPSUBSBZ256rm:
5163 case VPSUBSBZ256rmk:
5164 case VPSUBSBZ256rmkz:
5165 case VPSUBSBZ256rr:
5166 case VPSUBSBZ256rrk:
5167 case VPSUBSBZ256rrkz:
5168 case VPSUBSBZrm:
5169 case VPSUBSBZrmk:
5170 case VPSUBSBZrmkz:
5171 case VPSUBSBZrr:
5172 case VPSUBSBZrrk:
5173 case VPSUBSBZrrkz:
5174 case VPSUBSBrm:
5175 case VPSUBSBrr:
5176 return true;
5177 }
5178 return false;
5179}
5180
5181bool isRDTSC(unsigned Opcode) {
5182 return Opcode == RDTSC;
5183}
5184
5185bool isVCVTTPS2UDQS(unsigned Opcode) {
5186 switch (Opcode) {
5187 case VCVTTPS2UDQSZ128rm:
5188 case VCVTTPS2UDQSZ128rmb:
5189 case VCVTTPS2UDQSZ128rmbk:
5190 case VCVTTPS2UDQSZ128rmbkz:
5191 case VCVTTPS2UDQSZ128rmk:
5192 case VCVTTPS2UDQSZ128rmkz:
5193 case VCVTTPS2UDQSZ128rr:
5194 case VCVTTPS2UDQSZ128rrk:
5195 case VCVTTPS2UDQSZ128rrkz:
5196 case VCVTTPS2UDQSZ256rm:
5197 case VCVTTPS2UDQSZ256rmb:
5198 case VCVTTPS2UDQSZ256rmbk:
5199 case VCVTTPS2UDQSZ256rmbkz:
5200 case VCVTTPS2UDQSZ256rmk:
5201 case VCVTTPS2UDQSZ256rmkz:
5202 case VCVTTPS2UDQSZ256rr:
5203 case VCVTTPS2UDQSZ256rrk:
5204 case VCVTTPS2UDQSZ256rrkz:
5205 case VCVTTPS2UDQSZrm:
5206 case VCVTTPS2UDQSZrmb:
5207 case VCVTTPS2UDQSZrmbk:
5208 case VCVTTPS2UDQSZrmbkz:
5209 case VCVTTPS2UDQSZrmk:
5210 case VCVTTPS2UDQSZrmkz:
5211 case VCVTTPS2UDQSZrr:
5212 case VCVTTPS2UDQSZrrb:
5213 case VCVTTPS2UDQSZrrbk:
5214 case VCVTTPS2UDQSZrrbkz:
5215 case VCVTTPS2UDQSZrrk:
5216 case VCVTTPS2UDQSZrrkz:
5217 return true;
5218 }
5219 return false;
5220}
5221
5222bool isVPMADCSSWD(unsigned Opcode) {
5223 switch (Opcode) {
5224 case VPMADCSSWDrm:
5225 case VPMADCSSWDrr:
5226 return true;
5227 }
5228 return false;
5229}
5230
5231bool isVFNMADD213PH(unsigned Opcode) {
5232 switch (Opcode) {
5233 case VFNMADD213PHZ128m:
5234 case VFNMADD213PHZ128mb:
5235 case VFNMADD213PHZ128mbk:
5236 case VFNMADD213PHZ128mbkz:
5237 case VFNMADD213PHZ128mk:
5238 case VFNMADD213PHZ128mkz:
5239 case VFNMADD213PHZ128r:
5240 case VFNMADD213PHZ128rk:
5241 case VFNMADD213PHZ128rkz:
5242 case VFNMADD213PHZ256m:
5243 case VFNMADD213PHZ256mb:
5244 case VFNMADD213PHZ256mbk:
5245 case VFNMADD213PHZ256mbkz:
5246 case VFNMADD213PHZ256mk:
5247 case VFNMADD213PHZ256mkz:
5248 case VFNMADD213PHZ256r:
5249 case VFNMADD213PHZ256rk:
5250 case VFNMADD213PHZ256rkz:
5251 case VFNMADD213PHZm:
5252 case VFNMADD213PHZmb:
5253 case VFNMADD213PHZmbk:
5254 case VFNMADD213PHZmbkz:
5255 case VFNMADD213PHZmk:
5256 case VFNMADD213PHZmkz:
5257 case VFNMADD213PHZr:
5258 case VFNMADD213PHZrb:
5259 case VFNMADD213PHZrbk:
5260 case VFNMADD213PHZrbkz:
5261 case VFNMADD213PHZrk:
5262 case VFNMADD213PHZrkz:
5263 return true;
5264 }
5265 return false;
5266}
5267
5268bool isVGF2P8AFFINEQB(unsigned Opcode) {
5269 switch (Opcode) {
5270 case VGF2P8AFFINEQBYrmi:
5271 case VGF2P8AFFINEQBYrri:
5272 case VGF2P8AFFINEQBZ128rmbi:
5273 case VGF2P8AFFINEQBZ128rmbik:
5274 case VGF2P8AFFINEQBZ128rmbikz:
5275 case VGF2P8AFFINEQBZ128rmi:
5276 case VGF2P8AFFINEQBZ128rmik:
5277 case VGF2P8AFFINEQBZ128rmikz:
5278 case VGF2P8AFFINEQBZ128rri:
5279 case VGF2P8AFFINEQBZ128rrik:
5280 case VGF2P8AFFINEQBZ128rrikz:
5281 case VGF2P8AFFINEQBZ256rmbi:
5282 case VGF2P8AFFINEQBZ256rmbik:
5283 case VGF2P8AFFINEQBZ256rmbikz:
5284 case VGF2P8AFFINEQBZ256rmi:
5285 case VGF2P8AFFINEQBZ256rmik:
5286 case VGF2P8AFFINEQBZ256rmikz:
5287 case VGF2P8AFFINEQBZ256rri:
5288 case VGF2P8AFFINEQBZ256rrik:
5289 case VGF2P8AFFINEQBZ256rrikz:
5290 case VGF2P8AFFINEQBZrmbi:
5291 case VGF2P8AFFINEQBZrmbik:
5292 case VGF2P8AFFINEQBZrmbikz:
5293 case VGF2P8AFFINEQBZrmi:
5294 case VGF2P8AFFINEQBZrmik:
5295 case VGF2P8AFFINEQBZrmikz:
5296 case VGF2P8AFFINEQBZrri:
5297 case VGF2P8AFFINEQBZrrik:
5298 case VGF2P8AFFINEQBZrrikz:
5299 case VGF2P8AFFINEQBrmi:
5300 case VGF2P8AFFINEQBrri:
5301 return true;
5302 }
5303 return false;
5304}
5305
5306bool isPMOVZXWD(unsigned Opcode) {
5307 switch (Opcode) {
5308 case PMOVZXWDrm:
5309 case PMOVZXWDrr:
5310 return true;
5311 }
5312 return false;
5313}
5314
5315bool isPMINUD(unsigned Opcode) {
5316 switch (Opcode) {
5317 case PMINUDrm:
5318 case PMINUDrr:
5319 return true;
5320 }
5321 return false;
5322}
5323
5324bool isXSUSLDTRK(unsigned Opcode) {
5325 return Opcode == XSUSLDTRK;
5326}
5327
5328bool isVCVTPH2UW(unsigned Opcode) {
5329 switch (Opcode) {
5330 case VCVTPH2UWZ128rm:
5331 case VCVTPH2UWZ128rmb:
5332 case VCVTPH2UWZ128rmbk:
5333 case VCVTPH2UWZ128rmbkz:
5334 case VCVTPH2UWZ128rmk:
5335 case VCVTPH2UWZ128rmkz:
5336 case VCVTPH2UWZ128rr:
5337 case VCVTPH2UWZ128rrk:
5338 case VCVTPH2UWZ128rrkz:
5339 case VCVTPH2UWZ256rm:
5340 case VCVTPH2UWZ256rmb:
5341 case VCVTPH2UWZ256rmbk:
5342 case VCVTPH2UWZ256rmbkz:
5343 case VCVTPH2UWZ256rmk:
5344 case VCVTPH2UWZ256rmkz:
5345 case VCVTPH2UWZ256rr:
5346 case VCVTPH2UWZ256rrk:
5347 case VCVTPH2UWZ256rrkz:
5348 case VCVTPH2UWZrm:
5349 case VCVTPH2UWZrmb:
5350 case VCVTPH2UWZrmbk:
5351 case VCVTPH2UWZrmbkz:
5352 case VCVTPH2UWZrmk:
5353 case VCVTPH2UWZrmkz:
5354 case VCVTPH2UWZrr:
5355 case VCVTPH2UWZrrb:
5356 case VCVTPH2UWZrrbk:
5357 case VCVTPH2UWZrrbkz:
5358 case VCVTPH2UWZrrk:
5359 case VCVTPH2UWZrrkz:
5360 return true;
5361 }
5362 return false;
5363}
5364
5365bool isPADDSW(unsigned Opcode) {
5366 switch (Opcode) {
5367 case MMX_PADDSWrm:
5368 case MMX_PADDSWrr:
5369 case PADDSWrm:
5370 case PADDSWrr:
5371 return true;
5372 }
5373 return false;
5374}
5375
5376bool isLFENCE(unsigned Opcode) {
5377 return Opcode == LFENCE;
5378}
5379
5380bool isCRC32(unsigned Opcode) {
5381 switch (Opcode) {
5382 case CRC32r32m16:
5383 case CRC32r32m16_EVEX:
5384 case CRC32r32m32:
5385 case CRC32r32m32_EVEX:
5386 case CRC32r32m8:
5387 case CRC32r32m8_EVEX:
5388 case CRC32r32r16:
5389 case CRC32r32r16_EVEX:
5390 case CRC32r32r32:
5391 case CRC32r32r32_EVEX:
5392 case CRC32r32r8:
5393 case CRC32r32r8_EVEX:
5394 case CRC32r64m64:
5395 case CRC32r64m64_EVEX:
5396 case CRC32r64m8:
5397 case CRC32r64m8_EVEX:
5398 case CRC32r64r64:
5399 case CRC32r64r64_EVEX:
5400 case CRC32r64r8:
5401 case CRC32r64r8_EVEX:
5402 return true;
5403 }
5404 return false;
5405}
5406
5407bool isAESENCWIDE256KL(unsigned Opcode) {
5408 return Opcode == AESENCWIDE256KL;
5409}
5410
5411bool isMOVAPD(unsigned Opcode) {
5412 switch (Opcode) {
5413 case MOVAPDmr:
5414 case MOVAPDrm:
5415 case MOVAPDrr:
5416 case MOVAPDrr_REV:
5417 return true;
5418 }
5419 return false;
5420}
5421
5422bool isVFMADD213PS(unsigned Opcode) {
5423 switch (Opcode) {
5424 case VFMADD213PSYm:
5425 case VFMADD213PSYr:
5426 case VFMADD213PSZ128m:
5427 case VFMADD213PSZ128mb:
5428 case VFMADD213PSZ128mbk:
5429 case VFMADD213PSZ128mbkz:
5430 case VFMADD213PSZ128mk:
5431 case VFMADD213PSZ128mkz:
5432 case VFMADD213PSZ128r:
5433 case VFMADD213PSZ128rk:
5434 case VFMADD213PSZ128rkz:
5435 case VFMADD213PSZ256m:
5436 case VFMADD213PSZ256mb:
5437 case VFMADD213PSZ256mbk:
5438 case VFMADD213PSZ256mbkz:
5439 case VFMADD213PSZ256mk:
5440 case VFMADD213PSZ256mkz:
5441 case VFMADD213PSZ256r:
5442 case VFMADD213PSZ256rk:
5443 case VFMADD213PSZ256rkz:
5444 case VFMADD213PSZm:
5445 case VFMADD213PSZmb:
5446 case VFMADD213PSZmbk:
5447 case VFMADD213PSZmbkz:
5448 case VFMADD213PSZmk:
5449 case VFMADD213PSZmkz:
5450 case VFMADD213PSZr:
5451 case VFMADD213PSZrb:
5452 case VFMADD213PSZrbk:
5453 case VFMADD213PSZrbkz:
5454 case VFMADD213PSZrk:
5455 case VFMADD213PSZrkz:
5456 case VFMADD213PSm:
5457 case VFMADD213PSr:
5458 return true;
5459 }
5460 return false;
5461}
5462
5463bool isVPDPWUUDS(unsigned Opcode) {
5464 switch (Opcode) {
5465 case VPDPWUUDSYrm:
5466 case VPDPWUUDSYrr:
5467 case VPDPWUUDSZ128rm:
5468 case VPDPWUUDSZ128rmb:
5469 case VPDPWUUDSZ128rmbk:
5470 case VPDPWUUDSZ128rmbkz:
5471 case VPDPWUUDSZ128rmk:
5472 case VPDPWUUDSZ128rmkz:
5473 case VPDPWUUDSZ128rr:
5474 case VPDPWUUDSZ128rrk:
5475 case VPDPWUUDSZ128rrkz:
5476 case VPDPWUUDSZ256rm:
5477 case VPDPWUUDSZ256rmb:
5478 case VPDPWUUDSZ256rmbk:
5479 case VPDPWUUDSZ256rmbkz:
5480 case VPDPWUUDSZ256rmk:
5481 case VPDPWUUDSZ256rmkz:
5482 case VPDPWUUDSZ256rr:
5483 case VPDPWUUDSZ256rrk:
5484 case VPDPWUUDSZ256rrkz:
5485 case VPDPWUUDSZrm:
5486 case VPDPWUUDSZrmb:
5487 case VPDPWUUDSZrmbk:
5488 case VPDPWUUDSZrmbkz:
5489 case VPDPWUUDSZrmk:
5490 case VPDPWUUDSZrmkz:
5491 case VPDPWUUDSZrr:
5492 case VPDPWUUDSZrrk:
5493 case VPDPWUUDSZrrkz:
5494 case VPDPWUUDSrm:
5495 case VPDPWUUDSrr:
5496 return true;
5497 }
5498 return false;
5499}
5500
5501bool isMOVSLDUP(unsigned Opcode) {
5502 switch (Opcode) {
5503 case MOVSLDUPrm:
5504 case MOVSLDUPrr:
5505 return true;
5506 }
5507 return false;
5508}
5509
5510bool isCLDEMOTE(unsigned Opcode) {
5511 return Opcode == CLDEMOTE;
5512}
5513
5514bool isVFNMADD231PS(unsigned Opcode) {
5515 switch (Opcode) {
5516 case VFNMADD231PSYm:
5517 case VFNMADD231PSYr:
5518 case VFNMADD231PSZ128m:
5519 case VFNMADD231PSZ128mb:
5520 case VFNMADD231PSZ128mbk:
5521 case VFNMADD231PSZ128mbkz:
5522 case VFNMADD231PSZ128mk:
5523 case VFNMADD231PSZ128mkz:
5524 case VFNMADD231PSZ128r:
5525 case VFNMADD231PSZ128rk:
5526 case VFNMADD231PSZ128rkz:
5527 case VFNMADD231PSZ256m:
5528 case VFNMADD231PSZ256mb:
5529 case VFNMADD231PSZ256mbk:
5530 case VFNMADD231PSZ256mbkz:
5531 case VFNMADD231PSZ256mk:
5532 case VFNMADD231PSZ256mkz:
5533 case VFNMADD231PSZ256r:
5534 case VFNMADD231PSZ256rk:
5535 case VFNMADD231PSZ256rkz:
5536 case VFNMADD231PSZm:
5537 case VFNMADD231PSZmb:
5538 case VFNMADD231PSZmbk:
5539 case VFNMADD231PSZmbkz:
5540 case VFNMADD231PSZmk:
5541 case VFNMADD231PSZmkz:
5542 case VFNMADD231PSZr:
5543 case VFNMADD231PSZrb:
5544 case VFNMADD231PSZrbk:
5545 case VFNMADD231PSZrbkz:
5546 case VFNMADD231PSZrk:
5547 case VFNMADD231PSZrkz:
5548 case VFNMADD231PSm:
5549 case VFNMADD231PSr:
5550 return true;
5551 }
5552 return false;
5553}
5554
5555bool isVMOVMSKPD(unsigned Opcode) {
5556 switch (Opcode) {
5557 case VMOVMSKPDYrr:
5558 case VMOVMSKPDrr:
5559 return true;
5560 }
5561 return false;
5562}
5563
5564bool isPREFETCHT0(unsigned Opcode) {
5565 return Opcode == PREFETCHT0;
5566}
5567
5568bool isVCVTNEOBF162PS(unsigned Opcode) {
5569 switch (Opcode) {
5570 case VCVTNEOBF162PSYrm:
5571 case VCVTNEOBF162PSrm:
5572 return true;
5573 }
5574 return false;
5575}
5576
5577bool isVPCMPUD(unsigned Opcode) {
5578 switch (Opcode) {
5579 case VPCMPUDZ128rmbi:
5580 case VPCMPUDZ128rmbik:
5581 case VPCMPUDZ128rmi:
5582 case VPCMPUDZ128rmik:
5583 case VPCMPUDZ128rri:
5584 case VPCMPUDZ128rrik:
5585 case VPCMPUDZ256rmbi:
5586 case VPCMPUDZ256rmbik:
5587 case VPCMPUDZ256rmi:
5588 case VPCMPUDZ256rmik:
5589 case VPCMPUDZ256rri:
5590 case VPCMPUDZ256rrik:
5591 case VPCMPUDZrmbi:
5592 case VPCMPUDZrmbik:
5593 case VPCMPUDZrmi:
5594 case VPCMPUDZrmik:
5595 case VPCMPUDZrri:
5596 case VPCMPUDZrrik:
5597 return true;
5598 }
5599 return false;
5600}
5601
5602bool isVMAXSD(unsigned Opcode) {
5603 switch (Opcode) {
5604 case VMAXSDZrm_Int:
5605 case VMAXSDZrmk_Int:
5606 case VMAXSDZrmkz_Int:
5607 case VMAXSDZrr_Int:
5608 case VMAXSDZrrb_Int:
5609 case VMAXSDZrrbk_Int:
5610 case VMAXSDZrrbkz_Int:
5611 case VMAXSDZrrk_Int:
5612 case VMAXSDZrrkz_Int:
5613 case VMAXSDrm_Int:
5614 case VMAXSDrr_Int:
5615 return true;
5616 }
5617 return false;
5618}
5619
5620bool isVRCP28SD(unsigned Opcode) {
5621 switch (Opcode) {
5622 case VRCP28SDZm:
5623 case VRCP28SDZmk:
5624 case VRCP28SDZmkz:
5625 case VRCP28SDZr:
5626 case VRCP28SDZrb:
5627 case VRCP28SDZrbk:
5628 case VRCP28SDZrbkz:
5629 case VRCP28SDZrk:
5630 case VRCP28SDZrkz:
5631 return true;
5632 }
5633 return false;
5634}
5635
5636bool isVMAXPS(unsigned Opcode) {
5637 switch (Opcode) {
5638 case VMAXPSYrm:
5639 case VMAXPSYrr:
5640 case VMAXPSZ128rm:
5641 case VMAXPSZ128rmb:
5642 case VMAXPSZ128rmbk:
5643 case VMAXPSZ128rmbkz:
5644 case VMAXPSZ128rmk:
5645 case VMAXPSZ128rmkz:
5646 case VMAXPSZ128rr:
5647 case VMAXPSZ128rrk:
5648 case VMAXPSZ128rrkz:
5649 case VMAXPSZ256rm:
5650 case VMAXPSZ256rmb:
5651 case VMAXPSZ256rmbk:
5652 case VMAXPSZ256rmbkz:
5653 case VMAXPSZ256rmk:
5654 case VMAXPSZ256rmkz:
5655 case VMAXPSZ256rr:
5656 case VMAXPSZ256rrk:
5657 case VMAXPSZ256rrkz:
5658 case VMAXPSZrm:
5659 case VMAXPSZrmb:
5660 case VMAXPSZrmbk:
5661 case VMAXPSZrmbkz:
5662 case VMAXPSZrmk:
5663 case VMAXPSZrmkz:
5664 case VMAXPSZrr:
5665 case VMAXPSZrrb:
5666 case VMAXPSZrrbk:
5667 case VMAXPSZrrbkz:
5668 case VMAXPSZrrk:
5669 case VMAXPSZrrkz:
5670 case VMAXPSrm:
5671 case VMAXPSrr:
5672 return true;
5673 }
5674 return false;
5675}
5676
5677bool isVPMOVD2M(unsigned Opcode) {
5678 switch (Opcode) {
5679 case VPMOVD2MZ128kr:
5680 case VPMOVD2MZ256kr:
5681 case VPMOVD2MZkr:
5682 return true;
5683 }
5684 return false;
5685}
5686
5687bool isVPMACSSWD(unsigned Opcode) {
5688 switch (Opcode) {
5689 case VPMACSSWDrm:
5690 case VPMACSSWDrr:
5691 return true;
5692 }
5693 return false;
5694}
5695
5696bool isVUCOMISD(unsigned Opcode) {
5697 switch (Opcode) {
5698 case VUCOMISDZrm:
5699 case VUCOMISDZrr:
5700 case VUCOMISDZrrb:
5701 case VUCOMISDrm:
5702 case VUCOMISDrr:
5703 return true;
5704 }
5705 return false;
5706}
5707
5708bool isLTR(unsigned Opcode) {
5709 switch (Opcode) {
5710 case LTRm:
5711 case LTRr:
5712 return true;
5713 }
5714 return false;
5715}
5716
5717bool isVCVTUSI2SH(unsigned Opcode) {
5718 switch (Opcode) {
5719 case VCVTUSI2SHZrm_Int:
5720 case VCVTUSI2SHZrr_Int:
5721 case VCVTUSI2SHZrrb_Int:
5722 case VCVTUSI642SHZrm_Int:
5723 case VCVTUSI642SHZrr_Int:
5724 case VCVTUSI642SHZrrb_Int:
5725 return true;
5726 }
5727 return false;
5728}
5729
5730bool isVSCATTERPF1QPS(unsigned Opcode) {
5731 return Opcode == VSCATTERPF1QPSm;
5732}
5733
5734bool isWRGSBASE(unsigned Opcode) {
5735 switch (Opcode) {
5736 case WRGSBASE:
5737 case WRGSBASE64:
5738 return true;
5739 }
5740 return false;
5741}
5742
5743bool isSTOSQ(unsigned Opcode) {
5744 return Opcode == STOSQ;
5745}
5746
5747bool isVSQRTSD(unsigned Opcode) {
5748 switch (Opcode) {
5749 case VSQRTSDZm_Int:
5750 case VSQRTSDZmk_Int:
5751 case VSQRTSDZmkz_Int:
5752 case VSQRTSDZr_Int:
5753 case VSQRTSDZrb_Int:
5754 case VSQRTSDZrbk_Int:
5755 case VSQRTSDZrbkz_Int:
5756 case VSQRTSDZrk_Int:
5757 case VSQRTSDZrkz_Int:
5758 case VSQRTSDm_Int:
5759 case VSQRTSDr_Int:
5760 return true;
5761 }
5762 return false;
5763}
5764
5765bool isVPERMIL2PD(unsigned Opcode) {
5766 switch (Opcode) {
5767 case VPERMIL2PDYmr:
5768 case VPERMIL2PDYrm:
5769 case VPERMIL2PDYrr:
5770 case VPERMIL2PDYrr_REV:
5771 case VPERMIL2PDmr:
5772 case VPERMIL2PDrm:
5773 case VPERMIL2PDrr:
5774 case VPERMIL2PDrr_REV:
5775 return true;
5776 }
5777 return false;
5778}
5779
5780bool isVFCMADDCSH(unsigned Opcode) {
5781 switch (Opcode) {
5782 case VFCMADDCSHZm:
5783 case VFCMADDCSHZmk:
5784 case VFCMADDCSHZmkz:
5785 case VFCMADDCSHZr:
5786 case VFCMADDCSHZrb:
5787 case VFCMADDCSHZrbk:
5788 case VFCMADDCSHZrbkz:
5789 case VFCMADDCSHZrk:
5790 case VFCMADDCSHZrkz:
5791 return true;
5792 }
5793 return false;
5794}
5795
5796bool isVFMADDSUB213PS(unsigned Opcode) {
5797 switch (Opcode) {
5798 case VFMADDSUB213PSYm:
5799 case VFMADDSUB213PSYr:
5800 case VFMADDSUB213PSZ128m:
5801 case VFMADDSUB213PSZ128mb:
5802 case VFMADDSUB213PSZ128mbk:
5803 case VFMADDSUB213PSZ128mbkz:
5804 case VFMADDSUB213PSZ128mk:
5805 case VFMADDSUB213PSZ128mkz:
5806 case VFMADDSUB213PSZ128r:
5807 case VFMADDSUB213PSZ128rk:
5808 case VFMADDSUB213PSZ128rkz:
5809 case VFMADDSUB213PSZ256m:
5810 case VFMADDSUB213PSZ256mb:
5811 case VFMADDSUB213PSZ256mbk:
5812 case VFMADDSUB213PSZ256mbkz:
5813 case VFMADDSUB213PSZ256mk:
5814 case VFMADDSUB213PSZ256mkz:
5815 case VFMADDSUB213PSZ256r:
5816 case VFMADDSUB213PSZ256rk:
5817 case VFMADDSUB213PSZ256rkz:
5818 case VFMADDSUB213PSZm:
5819 case VFMADDSUB213PSZmb:
5820 case VFMADDSUB213PSZmbk:
5821 case VFMADDSUB213PSZmbkz:
5822 case VFMADDSUB213PSZmk:
5823 case VFMADDSUB213PSZmkz:
5824 case VFMADDSUB213PSZr:
5825 case VFMADDSUB213PSZrb:
5826 case VFMADDSUB213PSZrbk:
5827 case VFMADDSUB213PSZrbkz:
5828 case VFMADDSUB213PSZrk:
5829 case VFMADDSUB213PSZrkz:
5830 case VFMADDSUB213PSm:
5831 case VFMADDSUB213PSr:
5832 return true;
5833 }
5834 return false;
5835}
5836
5837bool isPFSUB(unsigned Opcode) {
5838 switch (Opcode) {
5839 case PFSUBrm:
5840 case PFSUBrr:
5841 return true;
5842 }
5843 return false;
5844}
5845
5846bool isVSQRTSS(unsigned Opcode) {
5847 switch (Opcode) {
5848 case VSQRTSSZm_Int:
5849 case VSQRTSSZmk_Int:
5850 case VSQRTSSZmkz_Int:
5851 case VSQRTSSZr_Int:
5852 case VSQRTSSZrb_Int:
5853 case VSQRTSSZrbk_Int:
5854 case VSQRTSSZrbkz_Int:
5855 case VSQRTSSZrk_Int:
5856 case VSQRTSSZrkz_Int:
5857 case VSQRTSSm_Int:
5858 case VSQRTSSr_Int:
5859 return true;
5860 }
5861 return false;
5862}
5863
5864bool isVEXPANDPS(unsigned Opcode) {
5865 switch (Opcode) {
5866 case VEXPANDPSZ128rm:
5867 case VEXPANDPSZ128rmk:
5868 case VEXPANDPSZ128rmkz:
5869 case VEXPANDPSZ128rr:
5870 case VEXPANDPSZ128rrk:
5871 case VEXPANDPSZ128rrkz:
5872 case VEXPANDPSZ256rm:
5873 case VEXPANDPSZ256rmk:
5874 case VEXPANDPSZ256rmkz:
5875 case VEXPANDPSZ256rr:
5876 case VEXPANDPSZ256rrk:
5877 case VEXPANDPSZ256rrkz:
5878 case VEXPANDPSZrm:
5879 case VEXPANDPSZrmk:
5880 case VEXPANDPSZrmkz:
5881 case VEXPANDPSZrr:
5882 case VEXPANDPSZrrk:
5883 case VEXPANDPSZrrkz:
5884 return true;
5885 }
5886 return false;
5887}
5888
5889bool isVPCOMPRESSW(unsigned Opcode) {
5890 switch (Opcode) {
5891 case VPCOMPRESSWZ128mr:
5892 case VPCOMPRESSWZ128mrk:
5893 case VPCOMPRESSWZ128rr:
5894 case VPCOMPRESSWZ128rrk:
5895 case VPCOMPRESSWZ128rrkz:
5896 case VPCOMPRESSWZ256mr:
5897 case VPCOMPRESSWZ256mrk:
5898 case VPCOMPRESSWZ256rr:
5899 case VPCOMPRESSWZ256rrk:
5900 case VPCOMPRESSWZ256rrkz:
5901 case VPCOMPRESSWZmr:
5902 case VPCOMPRESSWZmrk:
5903 case VPCOMPRESSWZrr:
5904 case VPCOMPRESSWZrrk:
5905 case VPCOMPRESSWZrrkz:
5906 return true;
5907 }
5908 return false;
5909}
5910
5911bool isPEXTRD(unsigned Opcode) {
5912 switch (Opcode) {
5913 case PEXTRDmri:
5914 case PEXTRDrri:
5915 return true;
5916 }
5917 return false;
5918}
5919
5920bool isVCVTTPS2UQQS(unsigned Opcode) {
5921 switch (Opcode) {
5922 case VCVTTPS2UQQSZ128rm:
5923 case VCVTTPS2UQQSZ128rmb:
5924 case VCVTTPS2UQQSZ128rmbk:
5925 case VCVTTPS2UQQSZ128rmbkz:
5926 case VCVTTPS2UQQSZ128rmk:
5927 case VCVTTPS2UQQSZ128rmkz:
5928 case VCVTTPS2UQQSZ128rr:
5929 case VCVTTPS2UQQSZ128rrk:
5930 case VCVTTPS2UQQSZ128rrkz:
5931 case VCVTTPS2UQQSZ256rm:
5932 case VCVTTPS2UQQSZ256rmb:
5933 case VCVTTPS2UQQSZ256rmbk:
5934 case VCVTTPS2UQQSZ256rmbkz:
5935 case VCVTTPS2UQQSZ256rmk:
5936 case VCVTTPS2UQQSZ256rmkz:
5937 case VCVTTPS2UQQSZ256rr:
5938 case VCVTTPS2UQQSZ256rrb:
5939 case VCVTTPS2UQQSZ256rrbk:
5940 case VCVTTPS2UQQSZ256rrbkz:
5941 case VCVTTPS2UQQSZ256rrk:
5942 case VCVTTPS2UQQSZ256rrkz:
5943 case VCVTTPS2UQQSZrm:
5944 case VCVTTPS2UQQSZrmb:
5945 case VCVTTPS2UQQSZrmbk:
5946 case VCVTTPS2UQQSZrmbkz:
5947 case VCVTTPS2UQQSZrmk:
5948 case VCVTTPS2UQQSZrmkz:
5949 case VCVTTPS2UQQSZrr:
5950 case VCVTTPS2UQQSZrrb:
5951 case VCVTTPS2UQQSZrrbk:
5952 case VCVTTPS2UQQSZrrbkz:
5953 case VCVTTPS2UQQSZrrk:
5954 case VCVTTPS2UQQSZrrkz:
5955 return true;
5956 }
5957 return false;
5958}
5959
5960bool isSYSEXITQ(unsigned Opcode) {
5961 return Opcode == SYSEXIT64;
5962}
5963
5964bool isROUNDSD(unsigned Opcode) {
5965 switch (Opcode) {
5966 case ROUNDSDmi_Int:
5967 case ROUNDSDri_Int:
5968 return true;
5969 }
5970 return false;
5971}
5972
5973bool isVFMADD132BF16(unsigned Opcode) {
5974 switch (Opcode) {
5975 case VFMADD132BF16Z128m:
5976 case VFMADD132BF16Z128mb:
5977 case VFMADD132BF16Z128mbk:
5978 case VFMADD132BF16Z128mbkz:
5979 case VFMADD132BF16Z128mk:
5980 case VFMADD132BF16Z128mkz:
5981 case VFMADD132BF16Z128r:
5982 case VFMADD132BF16Z128rk:
5983 case VFMADD132BF16Z128rkz:
5984 case VFMADD132BF16Z256m:
5985 case VFMADD132BF16Z256mb:
5986 case VFMADD132BF16Z256mbk:
5987 case VFMADD132BF16Z256mbkz:
5988 case VFMADD132BF16Z256mk:
5989 case VFMADD132BF16Z256mkz:
5990 case VFMADD132BF16Z256r:
5991 case VFMADD132BF16Z256rk:
5992 case VFMADD132BF16Z256rkz:
5993 case VFMADD132BF16Zm:
5994 case VFMADD132BF16Zmb:
5995 case VFMADD132BF16Zmbk:
5996 case VFMADD132BF16Zmbkz:
5997 case VFMADD132BF16Zmk:
5998 case VFMADD132BF16Zmkz:
5999 case VFMADD132BF16Zr:
6000 case VFMADD132BF16Zrk:
6001 case VFMADD132BF16Zrkz:
6002 return true;
6003 }
6004 return false;
6005}
6006
6007bool isFCOM(unsigned Opcode) {
6008 switch (Opcode) {
6009 case COM_FST0r:
6010 case FCOM32m:
6011 case FCOM64m:
6012 return true;
6013 }
6014 return false;
6015}
6016
6017bool isVFNMSUBSS(unsigned Opcode) {
6018 switch (Opcode) {
6019 case VFNMSUBSS4mr:
6020 case VFNMSUBSS4rm:
6021 case VFNMSUBSS4rr:
6022 case VFNMSUBSS4rr_REV:
6023 return true;
6024 }
6025 return false;
6026}
6027
6028bool isKSHIFTLW(unsigned Opcode) {
6029 return Opcode == KSHIFTLWki;
6030}
6031
6032bool isVMPTRLD(unsigned Opcode) {
6033 return Opcode == VMPTRLDm;
6034}
6035
6036bool isSCASD(unsigned Opcode) {
6037 return Opcode == SCASL;
6038}
6039
6040bool isVAESDECLAST(unsigned Opcode) {
6041 switch (Opcode) {
6042 case VAESDECLASTYrm:
6043 case VAESDECLASTYrr:
6044 case VAESDECLASTZ128rm:
6045 case VAESDECLASTZ128rr:
6046 case VAESDECLASTZ256rm:
6047 case VAESDECLASTZ256rr:
6048 case VAESDECLASTZrm:
6049 case VAESDECLASTZrr:
6050 case VAESDECLASTrm:
6051 case VAESDECLASTrr:
6052 return true;
6053 }
6054 return false;
6055}
6056
6057bool isVFMADDSUBPS(unsigned Opcode) {
6058 switch (Opcode) {
6059 case VFMADDSUBPS4Ymr:
6060 case VFMADDSUBPS4Yrm:
6061 case VFMADDSUBPS4Yrr:
6062 case VFMADDSUBPS4Yrr_REV:
6063 case VFMADDSUBPS4mr:
6064 case VFMADDSUBPS4rm:
6065 case VFMADDSUBPS4rr:
6066 case VFMADDSUBPS4rr_REV:
6067 return true;
6068 }
6069 return false;
6070}
6071
6072bool isVCVTUQQ2PS(unsigned Opcode) {
6073 switch (Opcode) {
6074 case VCVTUQQ2PSZ128rm:
6075 case VCVTUQQ2PSZ128rmb:
6076 case VCVTUQQ2PSZ128rmbk:
6077 case VCVTUQQ2PSZ128rmbkz:
6078 case VCVTUQQ2PSZ128rmk:
6079 case VCVTUQQ2PSZ128rmkz:
6080 case VCVTUQQ2PSZ128rr:
6081 case VCVTUQQ2PSZ128rrk:
6082 case VCVTUQQ2PSZ128rrkz:
6083 case VCVTUQQ2PSZ256rm:
6084 case VCVTUQQ2PSZ256rmb:
6085 case VCVTUQQ2PSZ256rmbk:
6086 case VCVTUQQ2PSZ256rmbkz:
6087 case VCVTUQQ2PSZ256rmk:
6088 case VCVTUQQ2PSZ256rmkz:
6089 case VCVTUQQ2PSZ256rr:
6090 case VCVTUQQ2PSZ256rrk:
6091 case VCVTUQQ2PSZ256rrkz:
6092 case VCVTUQQ2PSZrm:
6093 case VCVTUQQ2PSZrmb:
6094 case VCVTUQQ2PSZrmbk:
6095 case VCVTUQQ2PSZrmbkz:
6096 case VCVTUQQ2PSZrmk:
6097 case VCVTUQQ2PSZrmkz:
6098 case VCVTUQQ2PSZrr:
6099 case VCVTUQQ2PSZrrb:
6100 case VCVTUQQ2PSZrrbk:
6101 case VCVTUQQ2PSZrrbkz:
6102 case VCVTUQQ2PSZrrk:
6103 case VCVTUQQ2PSZrrkz:
6104 return true;
6105 }
6106 return false;
6107}
6108
6109bool isVPMOVUSDB(unsigned Opcode) {
6110 switch (Opcode) {
6111 case VPMOVUSDBZ128mr:
6112 case VPMOVUSDBZ128mrk:
6113 case VPMOVUSDBZ128rr:
6114 case VPMOVUSDBZ128rrk:
6115 case VPMOVUSDBZ128rrkz:
6116 case VPMOVUSDBZ256mr:
6117 case VPMOVUSDBZ256mrk:
6118 case VPMOVUSDBZ256rr:
6119 case VPMOVUSDBZ256rrk:
6120 case VPMOVUSDBZ256rrkz:
6121 case VPMOVUSDBZmr:
6122 case VPMOVUSDBZmrk:
6123 case VPMOVUSDBZrr:
6124 case VPMOVUSDBZrrk:
6125 case VPMOVUSDBZrrkz:
6126 return true;
6127 }
6128 return false;
6129}
6130
6131bool isVPROTW(unsigned Opcode) {
6132 switch (Opcode) {
6133 case VPROTWmi:
6134 case VPROTWmr:
6135 case VPROTWri:
6136 case VPROTWrm:
6137 case VPROTWrr:
6138 case VPROTWrr_REV:
6139 return true;
6140 }
6141 return false;
6142}
6143
6144bool isVDPPS(unsigned Opcode) {
6145 switch (Opcode) {
6146 case VDPPSYrmi:
6147 case VDPPSYrri:
6148 case VDPPSrmi:
6149 case VDPPSrri:
6150 return true;
6151 }
6152 return false;
6153}
6154
6155bool isVRSQRT14PD(unsigned Opcode) {
6156 switch (Opcode) {
6157 case VRSQRT14PDZ128m:
6158 case VRSQRT14PDZ128mb:
6159 case VRSQRT14PDZ128mbk:
6160 case VRSQRT14PDZ128mbkz:
6161 case VRSQRT14PDZ128mk:
6162 case VRSQRT14PDZ128mkz:
6163 case VRSQRT14PDZ128r:
6164 case VRSQRT14PDZ128rk:
6165 case VRSQRT14PDZ128rkz:
6166 case VRSQRT14PDZ256m:
6167 case VRSQRT14PDZ256mb:
6168 case VRSQRT14PDZ256mbk:
6169 case VRSQRT14PDZ256mbkz:
6170 case VRSQRT14PDZ256mk:
6171 case VRSQRT14PDZ256mkz:
6172 case VRSQRT14PDZ256r:
6173 case VRSQRT14PDZ256rk:
6174 case VRSQRT14PDZ256rkz:
6175 case VRSQRT14PDZm:
6176 case VRSQRT14PDZmb:
6177 case VRSQRT14PDZmbk:
6178 case VRSQRT14PDZmbkz:
6179 case VRSQRT14PDZmk:
6180 case VRSQRT14PDZmkz:
6181 case VRSQRT14PDZr:
6182 case VRSQRT14PDZrk:
6183 case VRSQRT14PDZrkz:
6184 return true;
6185 }
6186 return false;
6187}
6188
6189bool isVTESTPD(unsigned Opcode) {
6190 switch (Opcode) {
6191 case VTESTPDYrm:
6192 case VTESTPDYrr:
6193 case VTESTPDrm:
6194 case VTESTPDrr:
6195 return true;
6196 }
6197 return false;
6198}
6199
6200bool isVFNMADD231SH(unsigned Opcode) {
6201 switch (Opcode) {
6202 case VFNMADD231SHZm_Int:
6203 case VFNMADD231SHZmk_Int:
6204 case VFNMADD231SHZmkz_Int:
6205 case VFNMADD231SHZr_Int:
6206 case VFNMADD231SHZrb_Int:
6207 case VFNMADD231SHZrbk_Int:
6208 case VFNMADD231SHZrbkz_Int:
6209 case VFNMADD231SHZrk_Int:
6210 case VFNMADD231SHZrkz_Int:
6211 return true;
6212 }
6213 return false;
6214}
6215
6216bool isENDBR64(unsigned Opcode) {
6217 return Opcode == ENDBR64;
6218}
6219
6220bool isMULSD(unsigned Opcode) {
6221 switch (Opcode) {
6222 case MULSDrm_Int:
6223 case MULSDrr_Int:
6224 return true;
6225 }
6226 return false;
6227}
6228
6229bool isXRSTORS(unsigned Opcode) {
6230 return Opcode == XRSTORS;
6231}
6232
6233bool isPREFETCHNTA(unsigned Opcode) {
6234 return Opcode == PREFETCHNTA;
6235}
6236
6237bool isVPCOMD(unsigned Opcode) {
6238 switch (Opcode) {
6239 case VPCOMDmi:
6240 case VPCOMDri:
6241 return true;
6242 }
6243 return false;
6244}
6245
6246bool isVPCOMUB(unsigned Opcode) {
6247 switch (Opcode) {
6248 case VPCOMUBmi:
6249 case VPCOMUBri:
6250 return true;
6251 }
6252 return false;
6253}
6254
6255bool isVPDPBSSD(unsigned Opcode) {
6256 switch (Opcode) {
6257 case VPDPBSSDYrm:
6258 case VPDPBSSDYrr:
6259 case VPDPBSSDZ128rm:
6260 case VPDPBSSDZ128rmb:
6261 case VPDPBSSDZ128rmbk:
6262 case VPDPBSSDZ128rmbkz:
6263 case VPDPBSSDZ128rmk:
6264 case VPDPBSSDZ128rmkz:
6265 case VPDPBSSDZ128rr:
6266 case VPDPBSSDZ128rrk:
6267 case VPDPBSSDZ128rrkz:
6268 case VPDPBSSDZ256rm:
6269 case VPDPBSSDZ256rmb:
6270 case VPDPBSSDZ256rmbk:
6271 case VPDPBSSDZ256rmbkz:
6272 case VPDPBSSDZ256rmk:
6273 case VPDPBSSDZ256rmkz:
6274 case VPDPBSSDZ256rr:
6275 case VPDPBSSDZ256rrk:
6276 case VPDPBSSDZ256rrkz:
6277 case VPDPBSSDZrm:
6278 case VPDPBSSDZrmb:
6279 case VPDPBSSDZrmbk:
6280 case VPDPBSSDZrmbkz:
6281 case VPDPBSSDZrmk:
6282 case VPDPBSSDZrmkz:
6283 case VPDPBSSDZrr:
6284 case VPDPBSSDZrrk:
6285 case VPDPBSSDZrrkz:
6286 case VPDPBSSDrm:
6287 case VPDPBSSDrr:
6288 return true;
6289 }
6290 return false;
6291}
6292
6293bool isVPHSUBD(unsigned Opcode) {
6294 switch (Opcode) {
6295 case VPHSUBDYrm:
6296 case VPHSUBDYrr:
6297 case VPHSUBDrm:
6298 case VPHSUBDrr:
6299 return true;
6300 }
6301 return false;
6302}
6303
6304bool isVBROADCASTI64X2(unsigned Opcode) {
6305 switch (Opcode) {
6306 case VBROADCASTI64X2Z256rm:
6307 case VBROADCASTI64X2Z256rmk:
6308 case VBROADCASTI64X2Z256rmkz:
6309 case VBROADCASTI64X2Zrm:
6310 case VBROADCASTI64X2Zrmk:
6311 case VBROADCASTI64X2Zrmkz:
6312 return true;
6313 }
6314 return false;
6315}
6316
6317bool isFPATAN(unsigned Opcode) {
6318 return Opcode == FPATAN;
6319}
6320
6321bool isLOOPE(unsigned Opcode) {
6322 return Opcode == LOOPE;
6323}
6324
6325bool isPCMPEQW(unsigned Opcode) {
6326 switch (Opcode) {
6327 case MMX_PCMPEQWrm:
6328 case MMX_PCMPEQWrr:
6329 case PCMPEQWrm:
6330 case PCMPEQWrr:
6331 return true;
6332 }
6333 return false;
6334}
6335
6336bool isVFMADDCSH(unsigned Opcode) {
6337 switch (Opcode) {
6338 case VFMADDCSHZm:
6339 case VFMADDCSHZmk:
6340 case VFMADDCSHZmkz:
6341 case VFMADDCSHZr:
6342 case VFMADDCSHZrb:
6343 case VFMADDCSHZrbk:
6344 case VFMADDCSHZrbkz:
6345 case VFMADDCSHZrk:
6346 case VFMADDCSHZrkz:
6347 return true;
6348 }
6349 return false;
6350}
6351
6352bool isMOVRS(unsigned Opcode) {
6353 switch (Opcode) {
6354 case MOVRS16rm:
6355 case MOVRS16rm_EVEX:
6356 case MOVRS32rm:
6357 case MOVRS32rm_EVEX:
6358 case MOVRS64rm:
6359 case MOVRS64rm_EVEX:
6360 case MOVRS8rm:
6361 case MOVRS8rm_EVEX:
6362 return true;
6363 }
6364 return false;
6365}
6366
6367bool isVFMSUBADD132PH(unsigned Opcode) {
6368 switch (Opcode) {
6369 case VFMSUBADD132PHZ128m:
6370 case VFMSUBADD132PHZ128mb:
6371 case VFMSUBADD132PHZ128mbk:
6372 case VFMSUBADD132PHZ128mbkz:
6373 case VFMSUBADD132PHZ128mk:
6374 case VFMSUBADD132PHZ128mkz:
6375 case VFMSUBADD132PHZ128r:
6376 case VFMSUBADD132PHZ128rk:
6377 case VFMSUBADD132PHZ128rkz:
6378 case VFMSUBADD132PHZ256m:
6379 case VFMSUBADD132PHZ256mb:
6380 case VFMSUBADD132PHZ256mbk:
6381 case VFMSUBADD132PHZ256mbkz:
6382 case VFMSUBADD132PHZ256mk:
6383 case VFMSUBADD132PHZ256mkz:
6384 case VFMSUBADD132PHZ256r:
6385 case VFMSUBADD132PHZ256rk:
6386 case VFMSUBADD132PHZ256rkz:
6387 case VFMSUBADD132PHZm:
6388 case VFMSUBADD132PHZmb:
6389 case VFMSUBADD132PHZmbk:
6390 case VFMSUBADD132PHZmbkz:
6391 case VFMSUBADD132PHZmk:
6392 case VFMSUBADD132PHZmkz:
6393 case VFMSUBADD132PHZr:
6394 case VFMSUBADD132PHZrb:
6395 case VFMSUBADD132PHZrbk:
6396 case VFMSUBADD132PHZrbkz:
6397 case VFMSUBADD132PHZrk:
6398 case VFMSUBADD132PHZrkz:
6399 return true;
6400 }
6401 return false;
6402}
6403
6404bool isKADDW(unsigned Opcode) {
6405 return Opcode == KADDWkk;
6406}
6407
6408bool isPTEST(unsigned Opcode) {
6409 switch (Opcode) {
6410 case PTESTrm:
6411 case PTESTrr:
6412 return true;
6413 }
6414 return false;
6415}
6416
6417bool isVPADDSB(unsigned Opcode) {
6418 switch (Opcode) {
6419 case VPADDSBYrm:
6420 case VPADDSBYrr:
6421 case VPADDSBZ128rm:
6422 case VPADDSBZ128rmk:
6423 case VPADDSBZ128rmkz:
6424 case VPADDSBZ128rr:
6425 case VPADDSBZ128rrk:
6426 case VPADDSBZ128rrkz:
6427 case VPADDSBZ256rm:
6428 case VPADDSBZ256rmk:
6429 case VPADDSBZ256rmkz:
6430 case VPADDSBZ256rr:
6431 case VPADDSBZ256rrk:
6432 case VPADDSBZ256rrkz:
6433 case VPADDSBZrm:
6434 case VPADDSBZrmk:
6435 case VPADDSBZrmkz:
6436 case VPADDSBZrr:
6437 case VPADDSBZrrk:
6438 case VPADDSBZrrkz:
6439 case VPADDSBrm:
6440 case VPADDSBrr:
6441 return true;
6442 }
6443 return false;
6444}
6445
6446bool isVRSQRT28PS(unsigned Opcode) {
6447 switch (Opcode) {
6448 case VRSQRT28PSZm:
6449 case VRSQRT28PSZmb:
6450 case VRSQRT28PSZmbk:
6451 case VRSQRT28PSZmbkz:
6452 case VRSQRT28PSZmk:
6453 case VRSQRT28PSZmkz:
6454 case VRSQRT28PSZr:
6455 case VRSQRT28PSZrb:
6456 case VRSQRT28PSZrbk:
6457 case VRSQRT28PSZrbkz:
6458 case VRSQRT28PSZrk:
6459 case VRSQRT28PSZrkz:
6460 return true;
6461 }
6462 return false;
6463}
6464
6465bool isVGF2P8AFFINEINVQB(unsigned Opcode) {
6466 switch (Opcode) {
6467 case VGF2P8AFFINEINVQBYrmi:
6468 case VGF2P8AFFINEINVQBYrri:
6469 case VGF2P8AFFINEINVQBZ128rmbi:
6470 case VGF2P8AFFINEINVQBZ128rmbik:
6471 case VGF2P8AFFINEINVQBZ128rmbikz:
6472 case VGF2P8AFFINEINVQBZ128rmi:
6473 case VGF2P8AFFINEINVQBZ128rmik:
6474 case VGF2P8AFFINEINVQBZ128rmikz:
6475 case VGF2P8AFFINEINVQBZ128rri:
6476 case VGF2P8AFFINEINVQBZ128rrik:
6477 case VGF2P8AFFINEINVQBZ128rrikz:
6478 case VGF2P8AFFINEINVQBZ256rmbi:
6479 case VGF2P8AFFINEINVQBZ256rmbik:
6480 case VGF2P8AFFINEINVQBZ256rmbikz:
6481 case VGF2P8AFFINEINVQBZ256rmi:
6482 case VGF2P8AFFINEINVQBZ256rmik:
6483 case VGF2P8AFFINEINVQBZ256rmikz:
6484 case VGF2P8AFFINEINVQBZ256rri:
6485 case VGF2P8AFFINEINVQBZ256rrik:
6486 case VGF2P8AFFINEINVQBZ256rrikz:
6487 case VGF2P8AFFINEINVQBZrmbi:
6488 case VGF2P8AFFINEINVQBZrmbik:
6489 case VGF2P8AFFINEINVQBZrmbikz:
6490 case VGF2P8AFFINEINVQBZrmi:
6491 case VGF2P8AFFINEINVQBZrmik:
6492 case VGF2P8AFFINEINVQBZrmikz:
6493 case VGF2P8AFFINEINVQBZrri:
6494 case VGF2P8AFFINEINVQBZrrik:
6495 case VGF2P8AFFINEINVQBZrrikz:
6496 case VGF2P8AFFINEINVQBrmi:
6497 case VGF2P8AFFINEINVQBrri:
6498 return true;
6499 }
6500 return false;
6501}
6502
6503bool isSERIALIZE(unsigned Opcode) {
6504 return Opcode == SERIALIZE;
6505}
6506
6507bool isVPHADDWQ(unsigned Opcode) {
6508 switch (Opcode) {
6509 case VPHADDWQrm:
6510 case VPHADDWQrr:
6511 return true;
6512 }
6513 return false;
6514}
6515
6516bool isVRNDSCALESH(unsigned Opcode) {
6517 switch (Opcode) {
6518 case VRNDSCALESHZrmi_Int:
6519 case VRNDSCALESHZrmik_Int:
6520 case VRNDSCALESHZrmikz_Int:
6521 case VRNDSCALESHZrri_Int:
6522 case VRNDSCALESHZrrib_Int:
6523 case VRNDSCALESHZrribk_Int:
6524 case VRNDSCALESHZrribkz_Int:
6525 case VRNDSCALESHZrrik_Int:
6526 case VRNDSCALESHZrrikz_Int:
6527 return true;
6528 }
6529 return false;
6530}
6531
6532bool isAAA(unsigned Opcode) {
6533 return Opcode == AAA;
6534}
6535
6536bool isVADDBF16(unsigned Opcode) {
6537 switch (Opcode) {
6538 case VADDBF16Z128rm:
6539 case VADDBF16Z128rmb:
6540 case VADDBF16Z128rmbk:
6541 case VADDBF16Z128rmbkz:
6542 case VADDBF16Z128rmk:
6543 case VADDBF16Z128rmkz:
6544 case VADDBF16Z128rr:
6545 case VADDBF16Z128rrk:
6546 case VADDBF16Z128rrkz:
6547 case VADDBF16Z256rm:
6548 case VADDBF16Z256rmb:
6549 case VADDBF16Z256rmbk:
6550 case VADDBF16Z256rmbkz:
6551 case VADDBF16Z256rmk:
6552 case VADDBF16Z256rmkz:
6553 case VADDBF16Z256rr:
6554 case VADDBF16Z256rrk:
6555 case VADDBF16Z256rrkz:
6556 case VADDBF16Zrm:
6557 case VADDBF16Zrmb:
6558 case VADDBF16Zrmbk:
6559 case VADDBF16Zrmbkz:
6560 case VADDBF16Zrmk:
6561 case VADDBF16Zrmkz:
6562 case VADDBF16Zrr:
6563 case VADDBF16Zrrk:
6564 case VADDBF16Zrrkz:
6565 return true;
6566 }
6567 return false;
6568}
6569
6570bool isWRMSRLIST(unsigned Opcode) {
6571 return Opcode == WRMSRLIST;
6572}
6573
6574bool isVCVTPH2PSX(unsigned Opcode) {
6575 switch (Opcode) {
6576 case VCVTPH2PSXZ128rm:
6577 case VCVTPH2PSXZ128rmb:
6578 case VCVTPH2PSXZ128rmbk:
6579 case VCVTPH2PSXZ128rmbkz:
6580 case VCVTPH2PSXZ128rmk:
6581 case VCVTPH2PSXZ128rmkz:
6582 case VCVTPH2PSXZ128rr:
6583 case VCVTPH2PSXZ128rrk:
6584 case VCVTPH2PSXZ128rrkz:
6585 case VCVTPH2PSXZ256rm:
6586 case VCVTPH2PSXZ256rmb:
6587 case VCVTPH2PSXZ256rmbk:
6588 case VCVTPH2PSXZ256rmbkz:
6589 case VCVTPH2PSXZ256rmk:
6590 case VCVTPH2PSXZ256rmkz:
6591 case VCVTPH2PSXZ256rr:
6592 case VCVTPH2PSXZ256rrk:
6593 case VCVTPH2PSXZ256rrkz:
6594 case VCVTPH2PSXZrm:
6595 case VCVTPH2PSXZrmb:
6596 case VCVTPH2PSXZrmbk:
6597 case VCVTPH2PSXZrmbkz:
6598 case VCVTPH2PSXZrmk:
6599 case VCVTPH2PSXZrmkz:
6600 case VCVTPH2PSXZrr:
6601 case VCVTPH2PSXZrrb:
6602 case VCVTPH2PSXZrrbk:
6603 case VCVTPH2PSXZrrbkz:
6604 case VCVTPH2PSXZrrk:
6605 case VCVTPH2PSXZrrkz:
6606 return true;
6607 }
6608 return false;
6609}
6610
6611bool isVFMSUB231PH(unsigned Opcode) {
6612 switch (Opcode) {
6613 case VFMSUB231PHZ128m:
6614 case VFMSUB231PHZ128mb:
6615 case VFMSUB231PHZ128mbk:
6616 case VFMSUB231PHZ128mbkz:
6617 case VFMSUB231PHZ128mk:
6618 case VFMSUB231PHZ128mkz:
6619 case VFMSUB231PHZ128r:
6620 case VFMSUB231PHZ128rk:
6621 case VFMSUB231PHZ128rkz:
6622 case VFMSUB231PHZ256m:
6623 case VFMSUB231PHZ256mb:
6624 case VFMSUB231PHZ256mbk:
6625 case VFMSUB231PHZ256mbkz:
6626 case VFMSUB231PHZ256mk:
6627 case VFMSUB231PHZ256mkz:
6628 case VFMSUB231PHZ256r:
6629 case VFMSUB231PHZ256rk:
6630 case VFMSUB231PHZ256rkz:
6631 case VFMSUB231PHZm:
6632 case VFMSUB231PHZmb:
6633 case VFMSUB231PHZmbk:
6634 case VFMSUB231PHZmbkz:
6635 case VFMSUB231PHZmk:
6636 case VFMSUB231PHZmkz:
6637 case VFMSUB231PHZr:
6638 case VFMSUB231PHZrb:
6639 case VFMSUB231PHZrbk:
6640 case VFMSUB231PHZrbkz:
6641 case VFMSUB231PHZrk:
6642 case VFMSUB231PHZrkz:
6643 return true;
6644 }
6645 return false;
6646}
6647
6648bool isVGATHERQPD(unsigned Opcode) {
6649 switch (Opcode) {
6650 case VGATHERQPDYrm:
6651 case VGATHERQPDZ128rm:
6652 case VGATHERQPDZ256rm:
6653 case VGATHERQPDZrm:
6654 case VGATHERQPDrm:
6655 return true;
6656 }
6657 return false;
6658}
6659
6660bool isKADDB(unsigned Opcode) {
6661 return Opcode == KADDBkk;
6662}
6663
6664bool isCVTPD2PI(unsigned Opcode) {
6665 switch (Opcode) {
6666 case MMX_CVTPD2PIrm:
6667 case MMX_CVTPD2PIrr:
6668 return true;
6669 }
6670 return false;
6671}
6672
6673bool isVFNMSUB213PH(unsigned Opcode) {
6674 switch (Opcode) {
6675 case VFNMSUB213PHZ128m:
6676 case VFNMSUB213PHZ128mb:
6677 case VFNMSUB213PHZ128mbk:
6678 case VFNMSUB213PHZ128mbkz:
6679 case VFNMSUB213PHZ128mk:
6680 case VFNMSUB213PHZ128mkz:
6681 case VFNMSUB213PHZ128r:
6682 case VFNMSUB213PHZ128rk:
6683 case VFNMSUB213PHZ128rkz:
6684 case VFNMSUB213PHZ256m:
6685 case VFNMSUB213PHZ256mb:
6686 case VFNMSUB213PHZ256mbk:
6687 case VFNMSUB213PHZ256mbkz:
6688 case VFNMSUB213PHZ256mk:
6689 case VFNMSUB213PHZ256mkz:
6690 case VFNMSUB213PHZ256r:
6691 case VFNMSUB213PHZ256rk:
6692 case VFNMSUB213PHZ256rkz:
6693 case VFNMSUB213PHZm:
6694 case VFNMSUB213PHZmb:
6695 case VFNMSUB213PHZmbk:
6696 case VFNMSUB213PHZmbkz:
6697 case VFNMSUB213PHZmk:
6698 case VFNMSUB213PHZmkz:
6699 case VFNMSUB213PHZr:
6700 case VFNMSUB213PHZrb:
6701 case VFNMSUB213PHZrbk:
6702 case VFNMSUB213PHZrbkz:
6703 case VFNMSUB213PHZrk:
6704 case VFNMSUB213PHZrkz:
6705 return true;
6706 }
6707 return false;
6708}
6709
6710bool isVPCMPESTRI(unsigned Opcode) {
6711 switch (Opcode) {
6712 case VPCMPESTRIrmi:
6713 case VPCMPESTRIrri:
6714 return true;
6715 }
6716 return false;
6717}
6718
6719bool isVPSHRDW(unsigned Opcode) {
6720 switch (Opcode) {
6721 case VPSHRDWZ128rmi:
6722 case VPSHRDWZ128rmik:
6723 case VPSHRDWZ128rmikz:
6724 case VPSHRDWZ128rri:
6725 case VPSHRDWZ128rrik:
6726 case VPSHRDWZ128rrikz:
6727 case VPSHRDWZ256rmi:
6728 case VPSHRDWZ256rmik:
6729 case VPSHRDWZ256rmikz:
6730 case VPSHRDWZ256rri:
6731 case VPSHRDWZ256rrik:
6732 case VPSHRDWZ256rrikz:
6733 case VPSHRDWZrmi:
6734 case VPSHRDWZrmik:
6735 case VPSHRDWZrmikz:
6736 case VPSHRDWZrri:
6737 case VPSHRDWZrrik:
6738 case VPSHRDWZrrikz:
6739 return true;
6740 }
6741 return false;
6742}
6743
6744bool isXORPS(unsigned Opcode) {
6745 switch (Opcode) {
6746 case XORPSrm:
6747 case XORPSrr:
6748 return true;
6749 }
6750 return false;
6751}
6752
6753bool isPOP2(unsigned Opcode) {
6754 return Opcode == POP2;
6755}
6756
6757bool isRDMSRLIST(unsigned Opcode) {
6758 return Opcode == RDMSRLIST;
6759}
6760
6761bool isVPDPBUSD(unsigned Opcode) {
6762 switch (Opcode) {
6763 case VPDPBUSDYrm:
6764 case VPDPBUSDYrr:
6765 case VPDPBUSDZ128rm:
6766 case VPDPBUSDZ128rmb:
6767 case VPDPBUSDZ128rmbk:
6768 case VPDPBUSDZ128rmbkz:
6769 case VPDPBUSDZ128rmk:
6770 case VPDPBUSDZ128rmkz:
6771 case VPDPBUSDZ128rr:
6772 case VPDPBUSDZ128rrk:
6773 case VPDPBUSDZ128rrkz:
6774 case VPDPBUSDZ256rm:
6775 case VPDPBUSDZ256rmb:
6776 case VPDPBUSDZ256rmbk:
6777 case VPDPBUSDZ256rmbkz:
6778 case VPDPBUSDZ256rmk:
6779 case VPDPBUSDZ256rmkz:
6780 case VPDPBUSDZ256rr:
6781 case VPDPBUSDZ256rrk:
6782 case VPDPBUSDZ256rrkz:
6783 case VPDPBUSDZrm:
6784 case VPDPBUSDZrmb:
6785 case VPDPBUSDZrmbk:
6786 case VPDPBUSDZrmbkz:
6787 case VPDPBUSDZrmk:
6788 case VPDPBUSDZrmkz:
6789 case VPDPBUSDZrr:
6790 case VPDPBUSDZrrk:
6791 case VPDPBUSDZrrkz:
6792 case VPDPBUSDrm:
6793 case VPDPBUSDrr:
6794 return true;
6795 }
6796 return false;
6797}
6798
6799bool isVCMPPH(unsigned Opcode) {
6800 switch (Opcode) {
6801 case VCMPPHZ128rmbi:
6802 case VCMPPHZ128rmbik:
6803 case VCMPPHZ128rmi:
6804 case VCMPPHZ128rmik:
6805 case VCMPPHZ128rri:
6806 case VCMPPHZ128rrik:
6807 case VCMPPHZ256rmbi:
6808 case VCMPPHZ256rmbik:
6809 case VCMPPHZ256rmi:
6810 case VCMPPHZ256rmik:
6811 case VCMPPHZ256rri:
6812 case VCMPPHZ256rrik:
6813 case VCMPPHZrmbi:
6814 case VCMPPHZrmbik:
6815 case VCMPPHZrmi:
6816 case VCMPPHZrmik:
6817 case VCMPPHZrri:
6818 case VCMPPHZrrib:
6819 case VCMPPHZrribk:
6820 case VCMPPHZrrik:
6821 return true;
6822 }
6823 return false;
6824}
6825
6826bool isVANDNPD(unsigned Opcode) {
6827 switch (Opcode) {
6828 case VANDNPDYrm:
6829 case VANDNPDYrr:
6830 case VANDNPDZ128rm:
6831 case VANDNPDZ128rmb:
6832 case VANDNPDZ128rmbk:
6833 case VANDNPDZ128rmbkz:
6834 case VANDNPDZ128rmk:
6835 case VANDNPDZ128rmkz:
6836 case VANDNPDZ128rr:
6837 case VANDNPDZ128rrk:
6838 case VANDNPDZ128rrkz:
6839 case VANDNPDZ256rm:
6840 case VANDNPDZ256rmb:
6841 case VANDNPDZ256rmbk:
6842 case VANDNPDZ256rmbkz:
6843 case VANDNPDZ256rmk:
6844 case VANDNPDZ256rmkz:
6845 case VANDNPDZ256rr:
6846 case VANDNPDZ256rrk:
6847 case VANDNPDZ256rrkz:
6848 case VANDNPDZrm:
6849 case VANDNPDZrmb:
6850 case VANDNPDZrmbk:
6851 case VANDNPDZrmbkz:
6852 case VANDNPDZrmk:
6853 case VANDNPDZrmkz:
6854 case VANDNPDZrr:
6855 case VANDNPDZrrk:
6856 case VANDNPDZrrkz:
6857 case VANDNPDrm:
6858 case VANDNPDrr:
6859 return true;
6860 }
6861 return false;
6862}
6863
6864bool isSUB(unsigned Opcode) {
6865 switch (Opcode) {
6866 case SUB16i16:
6867 case SUB16mi:
6868 case SUB16mi8:
6869 case SUB16mi8_EVEX:
6870 case SUB16mi8_ND:
6871 case SUB16mi8_NF:
6872 case SUB16mi8_NF_ND:
6873 case SUB16mi_EVEX:
6874 case SUB16mi_ND:
6875 case SUB16mi_NF:
6876 case SUB16mi_NF_ND:
6877 case SUB16mr:
6878 case SUB16mr_EVEX:
6879 case SUB16mr_ND:
6880 case SUB16mr_NF:
6881 case SUB16mr_NF_ND:
6882 case SUB16ri:
6883 case SUB16ri8:
6884 case SUB16ri8_EVEX:
6885 case SUB16ri8_ND:
6886 case SUB16ri8_NF:
6887 case SUB16ri8_NF_ND:
6888 case SUB16ri_EVEX:
6889 case SUB16ri_ND:
6890 case SUB16ri_NF:
6891 case SUB16ri_NF_ND:
6892 case SUB16rm:
6893 case SUB16rm_EVEX:
6894 case SUB16rm_ND:
6895 case SUB16rm_NF:
6896 case SUB16rm_NF_ND:
6897 case SUB16rr:
6898 case SUB16rr_EVEX:
6899 case SUB16rr_EVEX_REV:
6900 case SUB16rr_ND:
6901 case SUB16rr_ND_REV:
6902 case SUB16rr_NF:
6903 case SUB16rr_NF_ND:
6904 case SUB16rr_NF_ND_REV:
6905 case SUB16rr_NF_REV:
6906 case SUB16rr_REV:
6907 case SUB32i32:
6908 case SUB32mi:
6909 case SUB32mi8:
6910 case SUB32mi8_EVEX:
6911 case SUB32mi8_ND:
6912 case SUB32mi8_NF:
6913 case SUB32mi8_NF_ND:
6914 case SUB32mi_EVEX:
6915 case SUB32mi_ND:
6916 case SUB32mi_NF:
6917 case SUB32mi_NF_ND:
6918 case SUB32mr:
6919 case SUB32mr_EVEX:
6920 case SUB32mr_ND:
6921 case SUB32mr_NF:
6922 case SUB32mr_NF_ND:
6923 case SUB32ri:
6924 case SUB32ri8:
6925 case SUB32ri8_EVEX:
6926 case SUB32ri8_ND:
6927 case SUB32ri8_NF:
6928 case SUB32ri8_NF_ND:
6929 case SUB32ri_EVEX:
6930 case SUB32ri_ND:
6931 case SUB32ri_NF:
6932 case SUB32ri_NF_ND:
6933 case SUB32rm:
6934 case SUB32rm_EVEX:
6935 case SUB32rm_ND:
6936 case SUB32rm_NF:
6937 case SUB32rm_NF_ND:
6938 case SUB32rr:
6939 case SUB32rr_EVEX:
6940 case SUB32rr_EVEX_REV:
6941 case SUB32rr_ND:
6942 case SUB32rr_ND_REV:
6943 case SUB32rr_NF:
6944 case SUB32rr_NF_ND:
6945 case SUB32rr_NF_ND_REV:
6946 case SUB32rr_NF_REV:
6947 case SUB32rr_REV:
6948 case SUB64i32:
6949 case SUB64mi32:
6950 case SUB64mi32_EVEX:
6951 case SUB64mi32_ND:
6952 case SUB64mi32_NF:
6953 case SUB64mi32_NF_ND:
6954 case SUB64mi8:
6955 case SUB64mi8_EVEX:
6956 case SUB64mi8_ND:
6957 case SUB64mi8_NF:
6958 case SUB64mi8_NF_ND:
6959 case SUB64mr:
6960 case SUB64mr_EVEX:
6961 case SUB64mr_ND:
6962 case SUB64mr_NF:
6963 case SUB64mr_NF_ND:
6964 case SUB64ri32:
6965 case SUB64ri32_EVEX:
6966 case SUB64ri32_ND:
6967 case SUB64ri32_NF:
6968 case SUB64ri32_NF_ND:
6969 case SUB64ri8:
6970 case SUB64ri8_EVEX:
6971 case SUB64ri8_ND:
6972 case SUB64ri8_NF:
6973 case SUB64ri8_NF_ND:
6974 case SUB64rm:
6975 case SUB64rm_EVEX:
6976 case SUB64rm_ND:
6977 case SUB64rm_NF:
6978 case SUB64rm_NF_ND:
6979 case SUB64rr:
6980 case SUB64rr_EVEX:
6981 case SUB64rr_EVEX_REV:
6982 case SUB64rr_ND:
6983 case SUB64rr_ND_REV:
6984 case SUB64rr_NF:
6985 case SUB64rr_NF_ND:
6986 case SUB64rr_NF_ND_REV:
6987 case SUB64rr_NF_REV:
6988 case SUB64rr_REV:
6989 case SUB8i8:
6990 case SUB8mi:
6991 case SUB8mi8:
6992 case SUB8mi_EVEX:
6993 case SUB8mi_ND:
6994 case SUB8mi_NF:
6995 case SUB8mi_NF_ND:
6996 case SUB8mr:
6997 case SUB8mr_EVEX:
6998 case SUB8mr_ND:
6999 case SUB8mr_NF:
7000 case SUB8mr_NF_ND:
7001 case SUB8ri:
7002 case SUB8ri8:
7003 case SUB8ri_EVEX:
7004 case SUB8ri_ND:
7005 case SUB8ri_NF:
7006 case SUB8ri_NF_ND:
7007 case SUB8rm:
7008 case SUB8rm_EVEX:
7009 case SUB8rm_ND:
7010 case SUB8rm_NF:
7011 case SUB8rm_NF_ND:
7012 case SUB8rr:
7013 case SUB8rr_EVEX:
7014 case SUB8rr_EVEX_REV:
7015 case SUB8rr_ND:
7016 case SUB8rr_ND_REV:
7017 case SUB8rr_NF:
7018 case SUB8rr_NF_ND:
7019 case SUB8rr_NF_ND_REV:
7020 case SUB8rr_NF_REV:
7021 case SUB8rr_REV:
7022 return true;
7023 }
7024 return false;
7025}
7026
7027bool isVRSQRT28PD(unsigned Opcode) {
7028 switch (Opcode) {
7029 case VRSQRT28PDZm:
7030 case VRSQRT28PDZmb:
7031 case VRSQRT28PDZmbk:
7032 case VRSQRT28PDZmbkz:
7033 case VRSQRT28PDZmk:
7034 case VRSQRT28PDZmkz:
7035 case VRSQRT28PDZr:
7036 case VRSQRT28PDZrb:
7037 case VRSQRT28PDZrbk:
7038 case VRSQRT28PDZrbkz:
7039 case VRSQRT28PDZrk:
7040 case VRSQRT28PDZrkz:
7041 return true;
7042 }
7043 return false;
7044}
7045
7046bool isVFNMADD132PH(unsigned Opcode) {
7047 switch (Opcode) {
7048 case VFNMADD132PHZ128m:
7049 case VFNMADD132PHZ128mb:
7050 case VFNMADD132PHZ128mbk:
7051 case VFNMADD132PHZ128mbkz:
7052 case VFNMADD132PHZ128mk:
7053 case VFNMADD132PHZ128mkz:
7054 case VFNMADD132PHZ128r:
7055 case VFNMADD132PHZ128rk:
7056 case VFNMADD132PHZ128rkz:
7057 case VFNMADD132PHZ256m:
7058 case VFNMADD132PHZ256mb:
7059 case VFNMADD132PHZ256mbk:
7060 case VFNMADD132PHZ256mbkz:
7061 case VFNMADD132PHZ256mk:
7062 case VFNMADD132PHZ256mkz:
7063 case VFNMADD132PHZ256r:
7064 case VFNMADD132PHZ256rk:
7065 case VFNMADD132PHZ256rkz:
7066 case VFNMADD132PHZm:
7067 case VFNMADD132PHZmb:
7068 case VFNMADD132PHZmbk:
7069 case VFNMADD132PHZmbkz:
7070 case VFNMADD132PHZmk:
7071 case VFNMADD132PHZmkz:
7072 case VFNMADD132PHZr:
7073 case VFNMADD132PHZrb:
7074 case VFNMADD132PHZrbk:
7075 case VFNMADD132PHZrbkz:
7076 case VFNMADD132PHZrk:
7077 case VFNMADD132PHZrkz:
7078 return true;
7079 }
7080 return false;
7081}
7082
7083bool isVPMACSSWW(unsigned Opcode) {
7084 switch (Opcode) {
7085 case VPMACSSWWrm:
7086 case VPMACSSWWrr:
7087 return true;
7088 }
7089 return false;
7090}
7091
7092bool isXSTORE(unsigned Opcode) {
7093 return Opcode == XSTORE;
7094}
7095
7096bool isVPROTQ(unsigned Opcode) {
7097 switch (Opcode) {
7098 case VPROTQmi:
7099 case VPROTQmr:
7100 case VPROTQri:
7101 case VPROTQrm:
7102 case VPROTQrr:
7103 case VPROTQrr_REV:
7104 return true;
7105 }
7106 return false;
7107}
7108
7109bool isVPHADDBD(unsigned Opcode) {
7110 switch (Opcode) {
7111 case VPHADDBDrm:
7112 case VPHADDBDrr:
7113 return true;
7114 }
7115 return false;
7116}
7117
7118bool isVPMAXSB(unsigned Opcode) {
7119 switch (Opcode) {
7120 case VPMAXSBYrm:
7121 case VPMAXSBYrr:
7122 case VPMAXSBZ128rm:
7123 case VPMAXSBZ128rmk:
7124 case VPMAXSBZ128rmkz:
7125 case VPMAXSBZ128rr:
7126 case VPMAXSBZ128rrk:
7127 case VPMAXSBZ128rrkz:
7128 case VPMAXSBZ256rm:
7129 case VPMAXSBZ256rmk:
7130 case VPMAXSBZ256rmkz:
7131 case VPMAXSBZ256rr:
7132 case VPMAXSBZ256rrk:
7133 case VPMAXSBZ256rrkz:
7134 case VPMAXSBZrm:
7135 case VPMAXSBZrmk:
7136 case VPMAXSBZrmkz:
7137 case VPMAXSBZrr:
7138 case VPMAXSBZrrk:
7139 case VPMAXSBZrrkz:
7140 case VPMAXSBrm:
7141 case VPMAXSBrr:
7142 return true;
7143 }
7144 return false;
7145}
7146
7147bool isVMOVDQU8(unsigned Opcode) {
7148 switch (Opcode) {
7149 case VMOVDQU8Z128mr:
7150 case VMOVDQU8Z128mrk:
7151 case VMOVDQU8Z128rm:
7152 case VMOVDQU8Z128rmk:
7153 case VMOVDQU8Z128rmkz:
7154 case VMOVDQU8Z128rr:
7155 case VMOVDQU8Z128rr_REV:
7156 case VMOVDQU8Z128rrk:
7157 case VMOVDQU8Z128rrk_REV:
7158 case VMOVDQU8Z128rrkz:
7159 case VMOVDQU8Z128rrkz_REV:
7160 case VMOVDQU8Z256mr:
7161 case VMOVDQU8Z256mrk:
7162 case VMOVDQU8Z256rm:
7163 case VMOVDQU8Z256rmk:
7164 case VMOVDQU8Z256rmkz:
7165 case VMOVDQU8Z256rr:
7166 case VMOVDQU8Z256rr_REV:
7167 case VMOVDQU8Z256rrk:
7168 case VMOVDQU8Z256rrk_REV:
7169 case VMOVDQU8Z256rrkz:
7170 case VMOVDQU8Z256rrkz_REV:
7171 case VMOVDQU8Zmr:
7172 case VMOVDQU8Zmrk:
7173 case VMOVDQU8Zrm:
7174 case VMOVDQU8Zrmk:
7175 case VMOVDQU8Zrmkz:
7176 case VMOVDQU8Zrr:
7177 case VMOVDQU8Zrr_REV:
7178 case VMOVDQU8Zrrk:
7179 case VMOVDQU8Zrrk_REV:
7180 case VMOVDQU8Zrrkz:
7181 case VMOVDQU8Zrrkz_REV:
7182 return true;
7183 }
7184 return false;
7185}
7186
7187bool isVPMOVSXWD(unsigned Opcode) {
7188 switch (Opcode) {
7189 case VPMOVSXWDYrm:
7190 case VPMOVSXWDYrr:
7191 case VPMOVSXWDZ128rm:
7192 case VPMOVSXWDZ128rmk:
7193 case VPMOVSXWDZ128rmkz:
7194 case VPMOVSXWDZ128rr:
7195 case VPMOVSXWDZ128rrk:
7196 case VPMOVSXWDZ128rrkz:
7197 case VPMOVSXWDZ256rm:
7198 case VPMOVSXWDZ256rmk:
7199 case VPMOVSXWDZ256rmkz:
7200 case VPMOVSXWDZ256rr:
7201 case VPMOVSXWDZ256rrk:
7202 case VPMOVSXWDZ256rrkz:
7203 case VPMOVSXWDZrm:
7204 case VPMOVSXWDZrmk:
7205 case VPMOVSXWDZrmkz:
7206 case VPMOVSXWDZrr:
7207 case VPMOVSXWDZrrk:
7208 case VPMOVSXWDZrrkz:
7209 case VPMOVSXWDrm:
7210 case VPMOVSXWDrr:
7211 return true;
7212 }
7213 return false;
7214}
7215
7216bool isVMINMAXPD(unsigned Opcode) {
7217 switch (Opcode) {
7218 case VMINMAXPDZ128rmbi:
7219 case VMINMAXPDZ128rmbik:
7220 case VMINMAXPDZ128rmbikz:
7221 case VMINMAXPDZ128rmi:
7222 case VMINMAXPDZ128rmik:
7223 case VMINMAXPDZ128rmikz:
7224 case VMINMAXPDZ128rri:
7225 case VMINMAXPDZ128rrik:
7226 case VMINMAXPDZ128rrikz:
7227 case VMINMAXPDZ256rmbi:
7228 case VMINMAXPDZ256rmbik:
7229 case VMINMAXPDZ256rmbikz:
7230 case VMINMAXPDZ256rmi:
7231 case VMINMAXPDZ256rmik:
7232 case VMINMAXPDZ256rmikz:
7233 case VMINMAXPDZ256rri:
7234 case VMINMAXPDZ256rrik:
7235 case VMINMAXPDZ256rrikz:
7236 case VMINMAXPDZrmbi:
7237 case VMINMAXPDZrmbik:
7238 case VMINMAXPDZrmbikz:
7239 case VMINMAXPDZrmi:
7240 case VMINMAXPDZrmik:
7241 case VMINMAXPDZrmikz:
7242 case VMINMAXPDZrri:
7243 case VMINMAXPDZrrib:
7244 case VMINMAXPDZrribk:
7245 case VMINMAXPDZrribkz:
7246 case VMINMAXPDZrrik:
7247 case VMINMAXPDZrrikz:
7248 return true;
7249 }
7250 return false;
7251}
7252
7253bool isSHA256RNDS2(unsigned Opcode) {
7254 switch (Opcode) {
7255 case SHA256RNDS2rm:
7256 case SHA256RNDS2rr:
7257 return true;
7258 }
7259 return false;
7260}
7261
7262bool isKANDB(unsigned Opcode) {
7263 return Opcode == KANDBkk;
7264}
7265
7266bool isTPAUSE(unsigned Opcode) {
7267 return Opcode == TPAUSE;
7268}
7269
7270bool isPUSH(unsigned Opcode) {
7271 switch (Opcode) {
7272 case PUSH16i:
7273 case PUSH16i8:
7274 case PUSH16r:
7275 case PUSH16rmm:
7276 case PUSH16rmr:
7277 case PUSH32i:
7278 case PUSH32i8:
7279 case PUSH32r:
7280 case PUSH32rmm:
7281 case PUSH32rmr:
7282 case PUSH64i32:
7283 case PUSH64i8:
7284 case PUSH64r:
7285 case PUSH64rmm:
7286 case PUSH64rmr:
7287 case PUSHCS16:
7288 case PUSHCS32:
7289 case PUSHDS16:
7290 case PUSHDS32:
7291 case PUSHES16:
7292 case PUSHES32:
7293 case PUSHFS16:
7294 case PUSHFS32:
7295 case PUSHFS64:
7296 case PUSHGS16:
7297 case PUSHGS32:
7298 case PUSHGS64:
7299 case PUSHSS16:
7300 case PUSHSS32:
7301 return true;
7302 }
7303 return false;
7304}
7305
7306bool isVRNDSCALESS(unsigned Opcode) {
7307 switch (Opcode) {
7308 case VRNDSCALESSZrmi_Int:
7309 case VRNDSCALESSZrmik_Int:
7310 case VRNDSCALESSZrmikz_Int:
7311 case VRNDSCALESSZrri_Int:
7312 case VRNDSCALESSZrrib_Int:
7313 case VRNDSCALESSZrribk_Int:
7314 case VRNDSCALESSZrribkz_Int:
7315 case VRNDSCALESSZrrik_Int:
7316 case VRNDSCALESSZrrikz_Int:
7317 return true;
7318 }
7319 return false;
7320}
7321
7322bool isVRNDSCALEBF16(unsigned Opcode) {
7323 switch (Opcode) {
7324 case VRNDSCALEBF16Z128rmbi:
7325 case VRNDSCALEBF16Z128rmbik:
7326 case VRNDSCALEBF16Z128rmbikz:
7327 case VRNDSCALEBF16Z128rmi:
7328 case VRNDSCALEBF16Z128rmik:
7329 case VRNDSCALEBF16Z128rmikz:
7330 case VRNDSCALEBF16Z128rri:
7331 case VRNDSCALEBF16Z128rrik:
7332 case VRNDSCALEBF16Z128rrikz:
7333 case VRNDSCALEBF16Z256rmbi:
7334 case VRNDSCALEBF16Z256rmbik:
7335 case VRNDSCALEBF16Z256rmbikz:
7336 case VRNDSCALEBF16Z256rmi:
7337 case VRNDSCALEBF16Z256rmik:
7338 case VRNDSCALEBF16Z256rmikz:
7339 case VRNDSCALEBF16Z256rri:
7340 case VRNDSCALEBF16Z256rrik:
7341 case VRNDSCALEBF16Z256rrikz:
7342 case VRNDSCALEBF16Zrmbi:
7343 case VRNDSCALEBF16Zrmbik:
7344 case VRNDSCALEBF16Zrmbikz:
7345 case VRNDSCALEBF16Zrmi:
7346 case VRNDSCALEBF16Zrmik:
7347 case VRNDSCALEBF16Zrmikz:
7348 case VRNDSCALEBF16Zrri:
7349 case VRNDSCALEBF16Zrrik:
7350 case VRNDSCALEBF16Zrrikz:
7351 return true;
7352 }
7353 return false;
7354}
7355
7356bool isVPCMPISTRI(unsigned Opcode) {
7357 switch (Opcode) {
7358 case VPCMPISTRIrmi:
7359 case VPCMPISTRIrri:
7360 return true;
7361 }
7362 return false;
7363}
7364
7365bool isSTGI(unsigned Opcode) {
7366 return Opcode == STGI;
7367}
7368
7369bool isSBB(unsigned Opcode) {
7370 switch (Opcode) {
7371 case SBB16i16:
7372 case SBB16mi:
7373 case SBB16mi8:
7374 case SBB16mi8_EVEX:
7375 case SBB16mi8_ND:
7376 case SBB16mi_EVEX:
7377 case SBB16mi_ND:
7378 case SBB16mr:
7379 case SBB16mr_EVEX:
7380 case SBB16mr_ND:
7381 case SBB16ri:
7382 case SBB16ri8:
7383 case SBB16ri8_EVEX:
7384 case SBB16ri8_ND:
7385 case SBB16ri_EVEX:
7386 case SBB16ri_ND:
7387 case SBB16rm:
7388 case SBB16rm_EVEX:
7389 case SBB16rm_ND:
7390 case SBB16rr:
7391 case SBB16rr_EVEX:
7392 case SBB16rr_EVEX_REV:
7393 case SBB16rr_ND:
7394 case SBB16rr_ND_REV:
7395 case SBB16rr_REV:
7396 case SBB32i32:
7397 case SBB32mi:
7398 case SBB32mi8:
7399 case SBB32mi8_EVEX:
7400 case SBB32mi8_ND:
7401 case SBB32mi_EVEX:
7402 case SBB32mi_ND:
7403 case SBB32mr:
7404 case SBB32mr_EVEX:
7405 case SBB32mr_ND:
7406 case SBB32ri:
7407 case SBB32ri8:
7408 case SBB32ri8_EVEX:
7409 case SBB32ri8_ND:
7410 case SBB32ri_EVEX:
7411 case SBB32ri_ND:
7412 case SBB32rm:
7413 case SBB32rm_EVEX:
7414 case SBB32rm_ND:
7415 case SBB32rr:
7416 case SBB32rr_EVEX:
7417 case SBB32rr_EVEX_REV:
7418 case SBB32rr_ND:
7419 case SBB32rr_ND_REV:
7420 case SBB32rr_REV:
7421 case SBB64i32:
7422 case SBB64mi32:
7423 case SBB64mi32_EVEX:
7424 case SBB64mi32_ND:
7425 case SBB64mi8:
7426 case SBB64mi8_EVEX:
7427 case SBB64mi8_ND:
7428 case SBB64mr:
7429 case SBB64mr_EVEX:
7430 case SBB64mr_ND:
7431 case SBB64ri32:
7432 case SBB64ri32_EVEX:
7433 case SBB64ri32_ND:
7434 case SBB64ri8:
7435 case SBB64ri8_EVEX:
7436 case SBB64ri8_ND:
7437 case SBB64rm:
7438 case SBB64rm_EVEX:
7439 case SBB64rm_ND:
7440 case SBB64rr:
7441 case SBB64rr_EVEX:
7442 case SBB64rr_EVEX_REV:
7443 case SBB64rr_ND:
7444 case SBB64rr_ND_REV:
7445 case SBB64rr_REV:
7446 case SBB8i8:
7447 case SBB8mi:
7448 case SBB8mi8:
7449 case SBB8mi_EVEX:
7450 case SBB8mi_ND:
7451 case SBB8mr:
7452 case SBB8mr_EVEX:
7453 case SBB8mr_ND:
7454 case SBB8ri:
7455 case SBB8ri8:
7456 case SBB8ri_EVEX:
7457 case SBB8ri_ND:
7458 case SBB8rm:
7459 case SBB8rm_EVEX:
7460 case SBB8rm_ND:
7461 case SBB8rr:
7462 case SBB8rr_EVEX:
7463 case SBB8rr_EVEX_REV:
7464 case SBB8rr_ND:
7465 case SBB8rr_ND_REV:
7466 case SBB8rr_REV:
7467 return true;
7468 }
7469 return false;
7470}
7471
7472bool isBLCS(unsigned Opcode) {
7473 switch (Opcode) {
7474 case BLCS32rm:
7475 case BLCS32rr:
7476 case BLCS64rm:
7477 case BLCS64rr:
7478 return true;
7479 }
7480 return false;
7481}
7482
7483bool isVCVTSD2SH(unsigned Opcode) {
7484 switch (Opcode) {
7485 case VCVTSD2SHZrm_Int:
7486 case VCVTSD2SHZrmk_Int:
7487 case VCVTSD2SHZrmkz_Int:
7488 case VCVTSD2SHZrr_Int:
7489 case VCVTSD2SHZrrb_Int:
7490 case VCVTSD2SHZrrbk_Int:
7491 case VCVTSD2SHZrrbkz_Int:
7492 case VCVTSD2SHZrrk_Int:
7493 case VCVTSD2SHZrrkz_Int:
7494 return true;
7495 }
7496 return false;
7497}
7498
7499bool isVPERMW(unsigned Opcode) {
7500 switch (Opcode) {
7501 case VPERMWZ128rm:
7502 case VPERMWZ128rmk:
7503 case VPERMWZ128rmkz:
7504 case VPERMWZ128rr:
7505 case VPERMWZ128rrk:
7506 case VPERMWZ128rrkz:
7507 case VPERMWZ256rm:
7508 case VPERMWZ256rmk:
7509 case VPERMWZ256rmkz:
7510 case VPERMWZ256rr:
7511 case VPERMWZ256rrk:
7512 case VPERMWZ256rrkz:
7513 case VPERMWZrm:
7514 case VPERMWZrmk:
7515 case VPERMWZrmkz:
7516 case VPERMWZrr:
7517 case VPERMWZrrk:
7518 case VPERMWZrrkz:
7519 return true;
7520 }
7521 return false;
7522}
7523
7524bool isXRESLDTRK(unsigned Opcode) {
7525 return Opcode == XRESLDTRK;
7526}
7527
7528bool isAESENC256KL(unsigned Opcode) {
7529 return Opcode == AESENC256KL;
7530}
7531
7532bool isVGATHERDPD(unsigned Opcode) {
7533 switch (Opcode) {
7534 case VGATHERDPDYrm:
7535 case VGATHERDPDZ128rm:
7536 case VGATHERDPDZ256rm:
7537 case VGATHERDPDZrm:
7538 case VGATHERDPDrm:
7539 return true;
7540 }
7541 return false;
7542}
7543
7544bool isHRESET(unsigned Opcode) {
7545 return Opcode == HRESET;
7546}
7547
7548bool isVFMSUBADD231PD(unsigned Opcode) {
7549 switch (Opcode) {
7550 case VFMSUBADD231PDYm:
7551 case VFMSUBADD231PDYr:
7552 case VFMSUBADD231PDZ128m:
7553 case VFMSUBADD231PDZ128mb:
7554 case VFMSUBADD231PDZ128mbk:
7555 case VFMSUBADD231PDZ128mbkz:
7556 case VFMSUBADD231PDZ128mk:
7557 case VFMSUBADD231PDZ128mkz:
7558 case VFMSUBADD231PDZ128r:
7559 case VFMSUBADD231PDZ128rk:
7560 case VFMSUBADD231PDZ128rkz:
7561 case VFMSUBADD231PDZ256m:
7562 case VFMSUBADD231PDZ256mb:
7563 case VFMSUBADD231PDZ256mbk:
7564 case VFMSUBADD231PDZ256mbkz:
7565 case VFMSUBADD231PDZ256mk:
7566 case VFMSUBADD231PDZ256mkz:
7567 case VFMSUBADD231PDZ256r:
7568 case VFMSUBADD231PDZ256rk:
7569 case VFMSUBADD231PDZ256rkz:
7570 case VFMSUBADD231PDZm:
7571 case VFMSUBADD231PDZmb:
7572 case VFMSUBADD231PDZmbk:
7573 case VFMSUBADD231PDZmbkz:
7574 case VFMSUBADD231PDZmk:
7575 case VFMSUBADD231PDZmkz:
7576 case VFMSUBADD231PDZr:
7577 case VFMSUBADD231PDZrb:
7578 case VFMSUBADD231PDZrbk:
7579 case VFMSUBADD231PDZrbkz:
7580 case VFMSUBADD231PDZrk:
7581 case VFMSUBADD231PDZrkz:
7582 case VFMSUBADD231PDm:
7583 case VFMSUBADD231PDr:
7584 return true;
7585 }
7586 return false;
7587}
7588
7589bool isVFRCZSS(unsigned Opcode) {
7590 switch (Opcode) {
7591 case VFRCZSSrm:
7592 case VFRCZSSrr:
7593 return true;
7594 }
7595 return false;
7596}
7597
7598bool isMINPS(unsigned Opcode) {
7599 switch (Opcode) {
7600 case MINPSrm:
7601 case MINPSrr:
7602 return true;
7603 }
7604 return false;
7605}
7606
7607bool isFPREM1(unsigned Opcode) {
7608 return Opcode == FPREM1;
7609}
7610
7611bool isVPCMPUB(unsigned Opcode) {
7612 switch (Opcode) {
7613 case VPCMPUBZ128rmi:
7614 case VPCMPUBZ128rmik:
7615 case VPCMPUBZ128rri:
7616 case VPCMPUBZ128rrik:
7617 case VPCMPUBZ256rmi:
7618 case VPCMPUBZ256rmik:
7619 case VPCMPUBZ256rri:
7620 case VPCMPUBZ256rrik:
7621 case VPCMPUBZrmi:
7622 case VPCMPUBZrmik:
7623 case VPCMPUBZrri:
7624 case VPCMPUBZrrik:
7625 return true;
7626 }
7627 return false;
7628}
7629
7630bool isVSQRTPD(unsigned Opcode) {
7631 switch (Opcode) {
7632 case VSQRTPDYm:
7633 case VSQRTPDYr:
7634 case VSQRTPDZ128m:
7635 case VSQRTPDZ128mb:
7636 case VSQRTPDZ128mbk:
7637 case VSQRTPDZ128mbkz:
7638 case VSQRTPDZ128mk:
7639 case VSQRTPDZ128mkz:
7640 case VSQRTPDZ128r:
7641 case VSQRTPDZ128rk:
7642 case VSQRTPDZ128rkz:
7643 case VSQRTPDZ256m:
7644 case VSQRTPDZ256mb:
7645 case VSQRTPDZ256mbk:
7646 case VSQRTPDZ256mbkz:
7647 case VSQRTPDZ256mk:
7648 case VSQRTPDZ256mkz:
7649 case VSQRTPDZ256r:
7650 case VSQRTPDZ256rk:
7651 case VSQRTPDZ256rkz:
7652 case VSQRTPDZm:
7653 case VSQRTPDZmb:
7654 case VSQRTPDZmbk:
7655 case VSQRTPDZmbkz:
7656 case VSQRTPDZmk:
7657 case VSQRTPDZmkz:
7658 case VSQRTPDZr:
7659 case VSQRTPDZrb:
7660 case VSQRTPDZrbk:
7661 case VSQRTPDZrbkz:
7662 case VSQRTPDZrk:
7663 case VSQRTPDZrkz:
7664 case VSQRTPDm:
7665 case VSQRTPDr:
7666 return true;
7667 }
7668 return false;
7669}
7670
7671bool isVFRCZPS(unsigned Opcode) {
7672 switch (Opcode) {
7673 case VFRCZPSYrm:
7674 case VFRCZPSYrr:
7675 case VFRCZPSrm:
7676 case VFRCZPSrr:
7677 return true;
7678 }
7679 return false;
7680}
7681
7682bool isVFNMADD213SS(unsigned Opcode) {
7683 switch (Opcode) {
7684 case VFNMADD213SSZm_Int:
7685 case VFNMADD213SSZmk_Int:
7686 case VFNMADD213SSZmkz_Int:
7687 case VFNMADD213SSZr_Int:
7688 case VFNMADD213SSZrb_Int:
7689 case VFNMADD213SSZrbk_Int:
7690 case VFNMADD213SSZrbkz_Int:
7691 case VFNMADD213SSZrk_Int:
7692 case VFNMADD213SSZrkz_Int:
7693 case VFNMADD213SSm_Int:
7694 case VFNMADD213SSr_Int:
7695 return true;
7696 }
7697 return false;
7698}
7699
7700bool isVPSHRDVQ(unsigned Opcode) {
7701 switch (Opcode) {
7702 case VPSHRDVQZ128m:
7703 case VPSHRDVQZ128mb:
7704 case VPSHRDVQZ128mbk:
7705 case VPSHRDVQZ128mbkz:
7706 case VPSHRDVQZ128mk:
7707 case VPSHRDVQZ128mkz:
7708 case VPSHRDVQZ128r:
7709 case VPSHRDVQZ128rk:
7710 case VPSHRDVQZ128rkz:
7711 case VPSHRDVQZ256m:
7712 case VPSHRDVQZ256mb:
7713 case VPSHRDVQZ256mbk:
7714 case VPSHRDVQZ256mbkz:
7715 case VPSHRDVQZ256mk:
7716 case VPSHRDVQZ256mkz:
7717 case VPSHRDVQZ256r:
7718 case VPSHRDVQZ256rk:
7719 case VPSHRDVQZ256rkz:
7720 case VPSHRDVQZm:
7721 case VPSHRDVQZmb:
7722 case VPSHRDVQZmbk:
7723 case VPSHRDVQZmbkz:
7724 case VPSHRDVQZmk:
7725 case VPSHRDVQZmkz:
7726 case VPSHRDVQZr:
7727 case VPSHRDVQZrk:
7728 case VPSHRDVQZrkz:
7729 return true;
7730 }
7731 return false;
7732}
7733
7734bool isVPMOVDW(unsigned Opcode) {
7735 switch (Opcode) {
7736 case VPMOVDWZ128mr:
7737 case VPMOVDWZ128mrk:
7738 case VPMOVDWZ128rr:
7739 case VPMOVDWZ128rrk:
7740 case VPMOVDWZ128rrkz:
7741 case VPMOVDWZ256mr:
7742 case VPMOVDWZ256mrk:
7743 case VPMOVDWZ256rr:
7744 case VPMOVDWZ256rrk:
7745 case VPMOVDWZ256rrkz:
7746 case VPMOVDWZmr:
7747 case VPMOVDWZmrk:
7748 case VPMOVDWZrr:
7749 case VPMOVDWZrrk:
7750 case VPMOVDWZrrkz:
7751 return true;
7752 }
7753 return false;
7754}
7755
7756bool isVCVTPH2HF8S(unsigned Opcode) {
7757 switch (Opcode) {
7758 case VCVTPH2HF8SZ128rm:
7759 case VCVTPH2HF8SZ128rmb:
7760 case VCVTPH2HF8SZ128rmbk:
7761 case VCVTPH2HF8SZ128rmbkz:
7762 case VCVTPH2HF8SZ128rmk:
7763 case VCVTPH2HF8SZ128rmkz:
7764 case VCVTPH2HF8SZ128rr:
7765 case VCVTPH2HF8SZ128rrk:
7766 case VCVTPH2HF8SZ128rrkz:
7767 case VCVTPH2HF8SZ256rm:
7768 case VCVTPH2HF8SZ256rmb:
7769 case VCVTPH2HF8SZ256rmbk:
7770 case VCVTPH2HF8SZ256rmbkz:
7771 case VCVTPH2HF8SZ256rmk:
7772 case VCVTPH2HF8SZ256rmkz:
7773 case VCVTPH2HF8SZ256rr:
7774 case VCVTPH2HF8SZ256rrk:
7775 case VCVTPH2HF8SZ256rrkz:
7776 case VCVTPH2HF8SZrm:
7777 case VCVTPH2HF8SZrmb:
7778 case VCVTPH2HF8SZrmbk:
7779 case VCVTPH2HF8SZrmbkz:
7780 case VCVTPH2HF8SZrmk:
7781 case VCVTPH2HF8SZrmkz:
7782 case VCVTPH2HF8SZrr:
7783 case VCVTPH2HF8SZrrk:
7784 case VCVTPH2HF8SZrrkz:
7785 return true;
7786 }
7787 return false;
7788}
7789
7790bool isVBROADCASTSD(unsigned Opcode) {
7791 switch (Opcode) {
7792 case VBROADCASTSDYrm:
7793 case VBROADCASTSDYrr:
7794 case VBROADCASTSDZ256rm:
7795 case VBROADCASTSDZ256rmk:
7796 case VBROADCASTSDZ256rmkz:
7797 case VBROADCASTSDZ256rr:
7798 case VBROADCASTSDZ256rrk:
7799 case VBROADCASTSDZ256rrkz:
7800 case VBROADCASTSDZrm:
7801 case VBROADCASTSDZrmk:
7802 case VBROADCASTSDZrmkz:
7803 case VBROADCASTSDZrr:
7804 case VBROADCASTSDZrrk:
7805 case VBROADCASTSDZrrkz:
7806 return true;
7807 }
7808 return false;
7809}
7810
7811bool isVSHUFPD(unsigned Opcode) {
7812 switch (Opcode) {
7813 case VSHUFPDYrmi:
7814 case VSHUFPDYrri:
7815 case VSHUFPDZ128rmbi:
7816 case VSHUFPDZ128rmbik:
7817 case VSHUFPDZ128rmbikz:
7818 case VSHUFPDZ128rmi:
7819 case VSHUFPDZ128rmik:
7820 case VSHUFPDZ128rmikz:
7821 case VSHUFPDZ128rri:
7822 case VSHUFPDZ128rrik:
7823 case VSHUFPDZ128rrikz:
7824 case VSHUFPDZ256rmbi:
7825 case VSHUFPDZ256rmbik:
7826 case VSHUFPDZ256rmbikz:
7827 case VSHUFPDZ256rmi:
7828 case VSHUFPDZ256rmik:
7829 case VSHUFPDZ256rmikz:
7830 case VSHUFPDZ256rri:
7831 case VSHUFPDZ256rrik:
7832 case VSHUFPDZ256rrikz:
7833 case VSHUFPDZrmbi:
7834 case VSHUFPDZrmbik:
7835 case VSHUFPDZrmbikz:
7836 case VSHUFPDZrmi:
7837 case VSHUFPDZrmik:
7838 case VSHUFPDZrmikz:
7839 case VSHUFPDZrri:
7840 case VSHUFPDZrrik:
7841 case VSHUFPDZrrikz:
7842 case VSHUFPDrmi:
7843 case VSHUFPDrri:
7844 return true;
7845 }
7846 return false;
7847}
7848
7849bool isVPSUBSW(unsigned Opcode) {
7850 switch (Opcode) {
7851 case VPSUBSWYrm:
7852 case VPSUBSWYrr:
7853 case VPSUBSWZ128rm:
7854 case VPSUBSWZ128rmk:
7855 case VPSUBSWZ128rmkz:
7856 case VPSUBSWZ128rr:
7857 case VPSUBSWZ128rrk:
7858 case VPSUBSWZ128rrkz:
7859 case VPSUBSWZ256rm:
7860 case VPSUBSWZ256rmk:
7861 case VPSUBSWZ256rmkz:
7862 case VPSUBSWZ256rr:
7863 case VPSUBSWZ256rrk:
7864 case VPSUBSWZ256rrkz:
7865 case VPSUBSWZrm:
7866 case VPSUBSWZrmk:
7867 case VPSUBSWZrmkz:
7868 case VPSUBSWZrr:
7869 case VPSUBSWZrrk:
7870 case VPSUBSWZrrkz:
7871 case VPSUBSWrm:
7872 case VPSUBSWrr:
7873 return true;
7874 }
7875 return false;
7876}
7877
7878bool isKUNPCKBW(unsigned Opcode) {
7879 return Opcode == KUNPCKBWkk;
7880}
7881
7882bool isVPBLENDD(unsigned Opcode) {
7883 switch (Opcode) {
7884 case VPBLENDDYrmi:
7885 case VPBLENDDYrri:
7886 case VPBLENDDrmi:
7887 case VPBLENDDrri:
7888 return true;
7889 }
7890 return false;
7891}
7892
7893bool isUNPCKHPD(unsigned Opcode) {
7894 switch (Opcode) {
7895 case UNPCKHPDrm:
7896 case UNPCKHPDrr:
7897 return true;
7898 }
7899 return false;
7900}
7901
7902bool isVFNMADD231SD(unsigned Opcode) {
7903 switch (Opcode) {
7904 case VFNMADD231SDZm_Int:
7905 case VFNMADD231SDZmk_Int:
7906 case VFNMADD231SDZmkz_Int:
7907 case VFNMADD231SDZr_Int:
7908 case VFNMADD231SDZrb_Int:
7909 case VFNMADD231SDZrbk_Int:
7910 case VFNMADD231SDZrbkz_Int:
7911 case VFNMADD231SDZrk_Int:
7912 case VFNMADD231SDZrkz_Int:
7913 case VFNMADD231SDm_Int:
7914 case VFNMADD231SDr_Int:
7915 return true;
7916 }
7917 return false;
7918}
7919
7920bool isVPBROADCASTMW2D(unsigned Opcode) {
7921 switch (Opcode) {
7922 case VPBROADCASTMW2DZ128rr:
7923 case VPBROADCASTMW2DZ256rr:
7924 case VPBROADCASTMW2DZrr:
7925 return true;
7926 }
7927 return false;
7928}
7929
7930bool isVPMULTISHIFTQB(unsigned Opcode) {
7931 switch (Opcode) {
7932 case VPMULTISHIFTQBZ128rm:
7933 case VPMULTISHIFTQBZ128rmb:
7934 case VPMULTISHIFTQBZ128rmbk:
7935 case VPMULTISHIFTQBZ128rmbkz:
7936 case VPMULTISHIFTQBZ128rmk:
7937 case VPMULTISHIFTQBZ128rmkz:
7938 case VPMULTISHIFTQBZ128rr:
7939 case VPMULTISHIFTQBZ128rrk:
7940 case VPMULTISHIFTQBZ128rrkz:
7941 case VPMULTISHIFTQBZ256rm:
7942 case VPMULTISHIFTQBZ256rmb:
7943 case VPMULTISHIFTQBZ256rmbk:
7944 case VPMULTISHIFTQBZ256rmbkz:
7945 case VPMULTISHIFTQBZ256rmk:
7946 case VPMULTISHIFTQBZ256rmkz:
7947 case VPMULTISHIFTQBZ256rr:
7948 case VPMULTISHIFTQBZ256rrk:
7949 case VPMULTISHIFTQBZ256rrkz:
7950 case VPMULTISHIFTQBZrm:
7951 case VPMULTISHIFTQBZrmb:
7952 case VPMULTISHIFTQBZrmbk:
7953 case VPMULTISHIFTQBZrmbkz:
7954 case VPMULTISHIFTQBZrmk:
7955 case VPMULTISHIFTQBZrmkz:
7956 case VPMULTISHIFTQBZrr:
7957 case VPMULTISHIFTQBZrrk:
7958 case VPMULTISHIFTQBZrrkz:
7959 return true;
7960 }
7961 return false;
7962}
7963
7964bool isVP2INTERSECTQ(unsigned Opcode) {
7965 switch (Opcode) {
7966 case VP2INTERSECTQZ128rm:
7967 case VP2INTERSECTQZ128rmb:
7968 case VP2INTERSECTQZ128rr:
7969 case VP2INTERSECTQZ256rm:
7970 case VP2INTERSECTQZ256rmb:
7971 case VP2INTERSECTQZ256rr:
7972 case VP2INTERSECTQZrm:
7973 case VP2INTERSECTQZrmb:
7974 case VP2INTERSECTQZrr:
7975 return true;
7976 }
7977 return false;
7978}
7979
7980bool isVFNMSUB132BF16(unsigned Opcode) {
7981 switch (Opcode) {
7982 case VFNMSUB132BF16Z128m:
7983 case VFNMSUB132BF16Z128mb:
7984 case VFNMSUB132BF16Z128mbk:
7985 case VFNMSUB132BF16Z128mbkz:
7986 case VFNMSUB132BF16Z128mk:
7987 case VFNMSUB132BF16Z128mkz:
7988 case VFNMSUB132BF16Z128r:
7989 case VFNMSUB132BF16Z128rk:
7990 case VFNMSUB132BF16Z128rkz:
7991 case VFNMSUB132BF16Z256m:
7992 case VFNMSUB132BF16Z256mb:
7993 case VFNMSUB132BF16Z256mbk:
7994 case VFNMSUB132BF16Z256mbkz:
7995 case VFNMSUB132BF16Z256mk:
7996 case VFNMSUB132BF16Z256mkz:
7997 case VFNMSUB132BF16Z256r:
7998 case VFNMSUB132BF16Z256rk:
7999 case VFNMSUB132BF16Z256rkz:
8000 case VFNMSUB132BF16Zm:
8001 case VFNMSUB132BF16Zmb:
8002 case VFNMSUB132BF16Zmbk:
8003 case VFNMSUB132BF16Zmbkz:
8004 case VFNMSUB132BF16Zmk:
8005 case VFNMSUB132BF16Zmkz:
8006 case VFNMSUB132BF16Zr:
8007 case VFNMSUB132BF16Zrk:
8008 case VFNMSUB132BF16Zrkz:
8009 return true;
8010 }
8011 return false;
8012}
8013
8014bool isVFMADD213BF16(unsigned Opcode) {
8015 switch (Opcode) {
8016 case VFMADD213BF16Z128m:
8017 case VFMADD213BF16Z128mb:
8018 case VFMADD213BF16Z128mbk:
8019 case VFMADD213BF16Z128mbkz:
8020 case VFMADD213BF16Z128mk:
8021 case VFMADD213BF16Z128mkz:
8022 case VFMADD213BF16Z128r:
8023 case VFMADD213BF16Z128rk:
8024 case VFMADD213BF16Z128rkz:
8025 case VFMADD213BF16Z256m:
8026 case VFMADD213BF16Z256mb:
8027 case VFMADD213BF16Z256mbk:
8028 case VFMADD213BF16Z256mbkz:
8029 case VFMADD213BF16Z256mk:
8030 case VFMADD213BF16Z256mkz:
8031 case VFMADD213BF16Z256r:
8032 case VFMADD213BF16Z256rk:
8033 case VFMADD213BF16Z256rkz:
8034 case VFMADD213BF16Zm:
8035 case VFMADD213BF16Zmb:
8036 case VFMADD213BF16Zmbk:
8037 case VFMADD213BF16Zmbkz:
8038 case VFMADD213BF16Zmk:
8039 case VFMADD213BF16Zmkz:
8040 case VFMADD213BF16Zr:
8041 case VFMADD213BF16Zrk:
8042 case VFMADD213BF16Zrkz:
8043 return true;
8044 }
8045 return false;
8046}
8047
8048bool isVPUNPCKHWD(unsigned Opcode) {
8049 switch (Opcode) {
8050 case VPUNPCKHWDYrm:
8051 case VPUNPCKHWDYrr:
8052 case VPUNPCKHWDZ128rm:
8053 case VPUNPCKHWDZ128rmk:
8054 case VPUNPCKHWDZ128rmkz:
8055 case VPUNPCKHWDZ128rr:
8056 case VPUNPCKHWDZ128rrk:
8057 case VPUNPCKHWDZ128rrkz:
8058 case VPUNPCKHWDZ256rm:
8059 case VPUNPCKHWDZ256rmk:
8060 case VPUNPCKHWDZ256rmkz:
8061 case VPUNPCKHWDZ256rr:
8062 case VPUNPCKHWDZ256rrk:
8063 case VPUNPCKHWDZ256rrkz:
8064 case VPUNPCKHWDZrm:
8065 case VPUNPCKHWDZrmk:
8066 case VPUNPCKHWDZrmkz:
8067 case VPUNPCKHWDZrr:
8068 case VPUNPCKHWDZrrk:
8069 case VPUNPCKHWDZrrkz:
8070 case VPUNPCKHWDrm:
8071 case VPUNPCKHWDrr:
8072 return true;
8073 }
8074 return false;
8075}
8076
8077bool isVPERM2F128(unsigned Opcode) {
8078 switch (Opcode) {
8079 case VPERM2F128rmi:
8080 case VPERM2F128rri:
8081 return true;
8082 }
8083 return false;
8084}
8085
8086bool isINSD(unsigned Opcode) {
8087 return Opcode == INSL;
8088}
8089
8090bool isLFS(unsigned Opcode) {
8091 switch (Opcode) {
8092 case LFS16rm:
8093 case LFS32rm:
8094 case LFS64rm:
8095 return true;
8096 }
8097 return false;
8098}
8099
8100bool isFMULP(unsigned Opcode) {
8101 return Opcode == MUL_FPrST0;
8102}
8103
8104bool isCWD(unsigned Opcode) {
8105 return Opcode == CWD;
8106}
8107
8108bool isVDIVSS(unsigned Opcode) {
8109 switch (Opcode) {
8110 case VDIVSSZrm_Int:
8111 case VDIVSSZrmk_Int:
8112 case VDIVSSZrmkz_Int:
8113 case VDIVSSZrr_Int:
8114 case VDIVSSZrrb_Int:
8115 case VDIVSSZrrbk_Int:
8116 case VDIVSSZrrbkz_Int:
8117 case VDIVSSZrrk_Int:
8118 case VDIVSSZrrkz_Int:
8119 case VDIVSSrm_Int:
8120 case VDIVSSrr_Int:
8121 return true;
8122 }
8123 return false;
8124}
8125
8126bool isVPSRLQ(unsigned Opcode) {
8127 switch (Opcode) {
8128 case VPSRLQYri:
8129 case VPSRLQYrm:
8130 case VPSRLQYrr:
8131 case VPSRLQZ128mbi:
8132 case VPSRLQZ128mbik:
8133 case VPSRLQZ128mbikz:
8134 case VPSRLQZ128mi:
8135 case VPSRLQZ128mik:
8136 case VPSRLQZ128mikz:
8137 case VPSRLQZ128ri:
8138 case VPSRLQZ128rik:
8139 case VPSRLQZ128rikz:
8140 case VPSRLQZ128rm:
8141 case VPSRLQZ128rmk:
8142 case VPSRLQZ128rmkz:
8143 case VPSRLQZ128rr:
8144 case VPSRLQZ128rrk:
8145 case VPSRLQZ128rrkz:
8146 case VPSRLQZ256mbi:
8147 case VPSRLQZ256mbik:
8148 case VPSRLQZ256mbikz:
8149 case VPSRLQZ256mi:
8150 case VPSRLQZ256mik:
8151 case VPSRLQZ256mikz:
8152 case VPSRLQZ256ri:
8153 case VPSRLQZ256rik:
8154 case VPSRLQZ256rikz:
8155 case VPSRLQZ256rm:
8156 case VPSRLQZ256rmk:
8157 case VPSRLQZ256rmkz:
8158 case VPSRLQZ256rr:
8159 case VPSRLQZ256rrk:
8160 case VPSRLQZ256rrkz:
8161 case VPSRLQZmbi:
8162 case VPSRLQZmbik:
8163 case VPSRLQZmbikz:
8164 case VPSRLQZmi:
8165 case VPSRLQZmik:
8166 case VPSRLQZmikz:
8167 case VPSRLQZri:
8168 case VPSRLQZrik:
8169 case VPSRLQZrikz:
8170 case VPSRLQZrm:
8171 case VPSRLQZrmk:
8172 case VPSRLQZrmkz:
8173 case VPSRLQZrr:
8174 case VPSRLQZrrk:
8175 case VPSRLQZrrkz:
8176 case VPSRLQri:
8177 case VPSRLQrm:
8178 case VPSRLQrr:
8179 return true;
8180 }
8181 return false;
8182}
8183
8184bool isFSQRT(unsigned Opcode) {
8185 return Opcode == SQRT_F;
8186}
8187
8188bool isJRCXZ(unsigned Opcode) {
8189 return Opcode == JRCXZ;
8190}
8191
8192bool isVPMOVMSKB(unsigned Opcode) {
8193 switch (Opcode) {
8194 case VPMOVMSKBYrr:
8195 case VPMOVMSKBrr:
8196 return true;
8197 }
8198 return false;
8199}
8200
8201bool isAESDEC256KL(unsigned Opcode) {
8202 return Opcode == AESDEC256KL;
8203}
8204
8205bool isFLDENV(unsigned Opcode) {
8206 return Opcode == FLDENVm;
8207}
8208
8209bool isVPHSUBWD(unsigned Opcode) {
8210 switch (Opcode) {
8211 case VPHSUBWDrm:
8212 case VPHSUBWDrr:
8213 return true;
8214 }
8215 return false;
8216}
8217
8218bool isWBNOINVD(unsigned Opcode) {
8219 return Opcode == WBNOINVD;
8220}
8221
8222bool isVEXPANDPD(unsigned Opcode) {
8223 switch (Opcode) {
8224 case VEXPANDPDZ128rm:
8225 case VEXPANDPDZ128rmk:
8226 case VEXPANDPDZ128rmkz:
8227 case VEXPANDPDZ128rr:
8228 case VEXPANDPDZ128rrk:
8229 case VEXPANDPDZ128rrkz:
8230 case VEXPANDPDZ256rm:
8231 case VEXPANDPDZ256rmk:
8232 case VEXPANDPDZ256rmkz:
8233 case VEXPANDPDZ256rr:
8234 case VEXPANDPDZ256rrk:
8235 case VEXPANDPDZ256rrkz:
8236 case VEXPANDPDZrm:
8237 case VEXPANDPDZrmk:
8238 case VEXPANDPDZrmkz:
8239 case VEXPANDPDZrr:
8240 case VEXPANDPDZrrk:
8241 case VEXPANDPDZrrkz:
8242 return true;
8243 }
8244 return false;
8245}
8246
8247bool isFYL2XP1(unsigned Opcode) {
8248 return Opcode == FYL2XP1;
8249}
8250
8251bool isPREFETCHT2(unsigned Opcode) {
8252 return Opcode == PREFETCHT2;
8253}
8254
8255bool isVPDPBSUDS(unsigned Opcode) {
8256 switch (Opcode) {
8257 case VPDPBSUDSYrm:
8258 case VPDPBSUDSYrr:
8259 case VPDPBSUDSZ128rm:
8260 case VPDPBSUDSZ128rmb:
8261 case VPDPBSUDSZ128rmbk:
8262 case VPDPBSUDSZ128rmbkz:
8263 case VPDPBSUDSZ128rmk:
8264 case VPDPBSUDSZ128rmkz:
8265 case VPDPBSUDSZ128rr:
8266 case VPDPBSUDSZ128rrk:
8267 case VPDPBSUDSZ128rrkz:
8268 case VPDPBSUDSZ256rm:
8269 case VPDPBSUDSZ256rmb:
8270 case VPDPBSUDSZ256rmbk:
8271 case VPDPBSUDSZ256rmbkz:
8272 case VPDPBSUDSZ256rmk:
8273 case VPDPBSUDSZ256rmkz:
8274 case VPDPBSUDSZ256rr:
8275 case VPDPBSUDSZ256rrk:
8276 case VPDPBSUDSZ256rrkz:
8277 case VPDPBSUDSZrm:
8278 case VPDPBSUDSZrmb:
8279 case VPDPBSUDSZrmbk:
8280 case VPDPBSUDSZrmbkz:
8281 case VPDPBSUDSZrmk:
8282 case VPDPBSUDSZrmkz:
8283 case VPDPBSUDSZrr:
8284 case VPDPBSUDSZrrk:
8285 case VPDPBSUDSZrrkz:
8286 case VPDPBSUDSrm:
8287 case VPDPBSUDSrr:
8288 return true;
8289 }
8290 return false;
8291}
8292
8293bool isVSHA512MSG2(unsigned Opcode) {
8294 return Opcode == VSHA512MSG2rr;
8295}
8296
8297bool isPMULHUW(unsigned Opcode) {
8298 switch (Opcode) {
8299 case MMX_PMULHUWrm:
8300 case MMX_PMULHUWrr:
8301 case PMULHUWrm:
8302 case PMULHUWrr:
8303 return true;
8304 }
8305 return false;
8306}
8307
8308bool isKANDNB(unsigned Opcode) {
8309 return Opcode == KANDNBkk;
8310}
8311
8312bool isVCVTUW2PH(unsigned Opcode) {
8313 switch (Opcode) {
8314 case VCVTUW2PHZ128rm:
8315 case VCVTUW2PHZ128rmb:
8316 case VCVTUW2PHZ128rmbk:
8317 case VCVTUW2PHZ128rmbkz:
8318 case VCVTUW2PHZ128rmk:
8319 case VCVTUW2PHZ128rmkz:
8320 case VCVTUW2PHZ128rr:
8321 case VCVTUW2PHZ128rrk:
8322 case VCVTUW2PHZ128rrkz:
8323 case VCVTUW2PHZ256rm:
8324 case VCVTUW2PHZ256rmb:
8325 case VCVTUW2PHZ256rmbk:
8326 case VCVTUW2PHZ256rmbkz:
8327 case VCVTUW2PHZ256rmk:
8328 case VCVTUW2PHZ256rmkz:
8329 case VCVTUW2PHZ256rr:
8330 case VCVTUW2PHZ256rrk:
8331 case VCVTUW2PHZ256rrkz:
8332 case VCVTUW2PHZrm:
8333 case VCVTUW2PHZrmb:
8334 case VCVTUW2PHZrmbk:
8335 case VCVTUW2PHZrmbkz:
8336 case VCVTUW2PHZrmk:
8337 case VCVTUW2PHZrmkz:
8338 case VCVTUW2PHZrr:
8339 case VCVTUW2PHZrrb:
8340 case VCVTUW2PHZrrbk:
8341 case VCVTUW2PHZrrbkz:
8342 case VCVTUW2PHZrrk:
8343 case VCVTUW2PHZrrkz:
8344 return true;
8345 }
8346 return false;
8347}
8348
8349bool isAESDECWIDE256KL(unsigned Opcode) {
8350 return Opcode == AESDECWIDE256KL;
8351}
8352
8353bool isVPGATHERDD(unsigned Opcode) {
8354 switch (Opcode) {
8355 case VPGATHERDDYrm:
8356 case VPGATHERDDZ128rm:
8357 case VPGATHERDDZ256rm:
8358 case VPGATHERDDZrm:
8359 case VPGATHERDDrm:
8360 return true;
8361 }
8362 return false;
8363}
8364
8365bool isVREDUCESH(unsigned Opcode) {
8366 switch (Opcode) {
8367 case VREDUCESHZrmi:
8368 case VREDUCESHZrmik:
8369 case VREDUCESHZrmikz:
8370 case VREDUCESHZrri:
8371 case VREDUCESHZrrib:
8372 case VREDUCESHZrribk:
8373 case VREDUCESHZrribkz:
8374 case VREDUCESHZrrik:
8375 case VREDUCESHZrrikz:
8376 return true;
8377 }
8378 return false;
8379}
8380
8381bool isPOPFQ(unsigned Opcode) {
8382 return Opcode == POPF64;
8383}
8384
8385bool isPAVGUSB(unsigned Opcode) {
8386 switch (Opcode) {
8387 case PAVGUSBrm:
8388 case PAVGUSBrr:
8389 return true;
8390 }
8391 return false;
8392}
8393
8394bool isVALIGND(unsigned Opcode) {
8395 switch (Opcode) {
8396 case VALIGNDZ128rmbi:
8397 case VALIGNDZ128rmbik:
8398 case VALIGNDZ128rmbikz:
8399 case VALIGNDZ128rmi:
8400 case VALIGNDZ128rmik:
8401 case VALIGNDZ128rmikz:
8402 case VALIGNDZ128rri:
8403 case VALIGNDZ128rrik:
8404 case VALIGNDZ128rrikz:
8405 case VALIGNDZ256rmbi:
8406 case VALIGNDZ256rmbik:
8407 case VALIGNDZ256rmbikz:
8408 case VALIGNDZ256rmi:
8409 case VALIGNDZ256rmik:
8410 case VALIGNDZ256rmikz:
8411 case VALIGNDZ256rri:
8412 case VALIGNDZ256rrik:
8413 case VALIGNDZ256rrikz:
8414 case VALIGNDZrmbi:
8415 case VALIGNDZrmbik:
8416 case VALIGNDZrmbikz:
8417 case VALIGNDZrmi:
8418 case VALIGNDZrmik:
8419 case VALIGNDZrmikz:
8420 case VALIGNDZrri:
8421 case VALIGNDZrrik:
8422 case VALIGNDZrrikz:
8423 return true;
8424 }
8425 return false;
8426}
8427
8428bool isVPHMINPOSUW(unsigned Opcode) {
8429 switch (Opcode) {
8430 case VPHMINPOSUWrm:
8431 case VPHMINPOSUWrr:
8432 return true;
8433 }
8434 return false;
8435}
8436
8437bool isLIDTD(unsigned Opcode) {
8438 return Opcode == LIDT32m;
8439}
8440
8441bool isVPERMT2PD(unsigned Opcode) {
8442 switch (Opcode) {
8443 case VPERMT2PDZ128rm:
8444 case VPERMT2PDZ128rmb:
8445 case VPERMT2PDZ128rmbk:
8446 case VPERMT2PDZ128rmbkz:
8447 case VPERMT2PDZ128rmk:
8448 case VPERMT2PDZ128rmkz:
8449 case VPERMT2PDZ128rr:
8450 case VPERMT2PDZ128rrk:
8451 case VPERMT2PDZ128rrkz:
8452 case VPERMT2PDZ256rm:
8453 case VPERMT2PDZ256rmb:
8454 case VPERMT2PDZ256rmbk:
8455 case VPERMT2PDZ256rmbkz:
8456 case VPERMT2PDZ256rmk:
8457 case VPERMT2PDZ256rmkz:
8458 case VPERMT2PDZ256rr:
8459 case VPERMT2PDZ256rrk:
8460 case VPERMT2PDZ256rrkz:
8461 case VPERMT2PDZrm:
8462 case VPERMT2PDZrmb:
8463 case VPERMT2PDZrmbk:
8464 case VPERMT2PDZrmbkz:
8465 case VPERMT2PDZrmk:
8466 case VPERMT2PDZrmkz:
8467 case VPERMT2PDZrr:
8468 case VPERMT2PDZrrk:
8469 case VPERMT2PDZrrkz:
8470 return true;
8471 }
8472 return false;
8473}
8474
8475bool isVMLAUNCH(unsigned Opcode) {
8476 return Opcode == VMLAUNCH;
8477}
8478
8479bool isVPXORQ(unsigned Opcode) {
8480 switch (Opcode) {
8481 case VPXORQZ128rm:
8482 case VPXORQZ128rmb:
8483 case VPXORQZ128rmbk:
8484 case VPXORQZ128rmbkz:
8485 case VPXORQZ128rmk:
8486 case VPXORQZ128rmkz:
8487 case VPXORQZ128rr:
8488 case VPXORQZ128rrk:
8489 case VPXORQZ128rrkz:
8490 case VPXORQZ256rm:
8491 case VPXORQZ256rmb:
8492 case VPXORQZ256rmbk:
8493 case VPXORQZ256rmbkz:
8494 case VPXORQZ256rmk:
8495 case VPXORQZ256rmkz:
8496 case VPXORQZ256rr:
8497 case VPXORQZ256rrk:
8498 case VPXORQZ256rrkz:
8499 case VPXORQZrm:
8500 case VPXORQZrmb:
8501 case VPXORQZrmbk:
8502 case VPXORQZrmbkz:
8503 case VPXORQZrmk:
8504 case VPXORQZrmkz:
8505 case VPXORQZrr:
8506 case VPXORQZrrk:
8507 case VPXORQZrrkz:
8508 return true;
8509 }
8510 return false;
8511}
8512
8513bool isMOVNTDQ(unsigned Opcode) {
8514 return Opcode == MOVNTDQmr;
8515}
8516
8517bool isPOP2P(unsigned Opcode) {
8518 return Opcode == POP2P;
8519}
8520
8521bool isVADDPD(unsigned Opcode) {
8522 switch (Opcode) {
8523 case VADDPDYrm:
8524 case VADDPDYrr:
8525 case VADDPDZ128rm:
8526 case VADDPDZ128rmb:
8527 case VADDPDZ128rmbk:
8528 case VADDPDZ128rmbkz:
8529 case VADDPDZ128rmk:
8530 case VADDPDZ128rmkz:
8531 case VADDPDZ128rr:
8532 case VADDPDZ128rrk:
8533 case VADDPDZ128rrkz:
8534 case VADDPDZ256rm:
8535 case VADDPDZ256rmb:
8536 case VADDPDZ256rmbk:
8537 case VADDPDZ256rmbkz:
8538 case VADDPDZ256rmk:
8539 case VADDPDZ256rmkz:
8540 case VADDPDZ256rr:
8541 case VADDPDZ256rrk:
8542 case VADDPDZ256rrkz:
8543 case VADDPDZrm:
8544 case VADDPDZrmb:
8545 case VADDPDZrmbk:
8546 case VADDPDZrmbkz:
8547 case VADDPDZrmk:
8548 case VADDPDZrmkz:
8549 case VADDPDZrr:
8550 case VADDPDZrrb:
8551 case VADDPDZrrbk:
8552 case VADDPDZrrbkz:
8553 case VADDPDZrrk:
8554 case VADDPDZrrkz:
8555 case VADDPDrm:
8556 case VADDPDrr:
8557 return true;
8558 }
8559 return false;
8560}
8561
8562bool isSMSW(unsigned Opcode) {
8563 switch (Opcode) {
8564 case SMSW16m:
8565 case SMSW16r:
8566 case SMSW32r:
8567 case SMSW64r:
8568 return true;
8569 }
8570 return false;
8571}
8572
8573bool isVEXP2PD(unsigned Opcode) {
8574 switch (Opcode) {
8575 case VEXP2PDZm:
8576 case VEXP2PDZmb:
8577 case VEXP2PDZmbk:
8578 case VEXP2PDZmbkz:
8579 case VEXP2PDZmk:
8580 case VEXP2PDZmkz:
8581 case VEXP2PDZr:
8582 case VEXP2PDZrb:
8583 case VEXP2PDZrbk:
8584 case VEXP2PDZrbkz:
8585 case VEXP2PDZrk:
8586 case VEXP2PDZrkz:
8587 return true;
8588 }
8589 return false;
8590}
8591
8592bool isPMULUDQ(unsigned Opcode) {
8593 switch (Opcode) {
8594 case MMX_PMULUDQrm:
8595 case MMX_PMULUDQrr:
8596 case PMULUDQrm:
8597 case PMULUDQrr:
8598 return true;
8599 }
8600 return false;
8601}
8602
8603bool isIRET(unsigned Opcode) {
8604 return Opcode == IRET16;
8605}
8606
8607bool isMULPS(unsigned Opcode) {
8608 switch (Opcode) {
8609 case MULPSrm:
8610 case MULPSrr:
8611 return true;
8612 }
8613 return false;
8614}
8615
8616bool isTDPBF8PS(unsigned Opcode) {
8617 return Opcode == TDPBF8PS;
8618}
8619
8620bool isVFNMSUBPD(unsigned Opcode) {
8621 switch (Opcode) {
8622 case VFNMSUBPD4Ymr:
8623 case VFNMSUBPD4Yrm:
8624 case VFNMSUBPD4Yrr:
8625 case VFNMSUBPD4Yrr_REV:
8626 case VFNMSUBPD4mr:
8627 case VFNMSUBPD4rm:
8628 case VFNMSUBPD4rr:
8629 case VFNMSUBPD4rr_REV:
8630 return true;
8631 }
8632 return false;
8633}
8634
8635bool isPHADDW(unsigned Opcode) {
8636 switch (Opcode) {
8637 case MMX_PHADDWrm:
8638 case MMX_PHADDWrr:
8639 case PHADDWrm:
8640 case PHADDWrr:
8641 return true;
8642 }
8643 return false;
8644}
8645
8646bool isRDSEED(unsigned Opcode) {
8647 switch (Opcode) {
8648 case RDSEED16r:
8649 case RDSEED32r:
8650 case RDSEED64r:
8651 return true;
8652 }
8653 return false;
8654}
8655
8656bool isVPSHLW(unsigned Opcode) {
8657 switch (Opcode) {
8658 case VPSHLWmr:
8659 case VPSHLWrm:
8660 case VPSHLWrr:
8661 case VPSHLWrr_REV:
8662 return true;
8663 }
8664 return false;
8665}
8666
8667bool isRMPUPDATE(unsigned Opcode) {
8668 return Opcode == RMPUPDATE;
8669}
8670
8671bool isVFMADD231PH(unsigned Opcode) {
8672 switch (Opcode) {
8673 case VFMADD231PHZ128m:
8674 case VFMADD231PHZ128mb:
8675 case VFMADD231PHZ128mbk:
8676 case VFMADD231PHZ128mbkz:
8677 case VFMADD231PHZ128mk:
8678 case VFMADD231PHZ128mkz:
8679 case VFMADD231PHZ128r:
8680 case VFMADD231PHZ128rk:
8681 case VFMADD231PHZ128rkz:
8682 case VFMADD231PHZ256m:
8683 case VFMADD231PHZ256mb:
8684 case VFMADD231PHZ256mbk:
8685 case VFMADD231PHZ256mbkz:
8686 case VFMADD231PHZ256mk:
8687 case VFMADD231PHZ256mkz:
8688 case VFMADD231PHZ256r:
8689 case VFMADD231PHZ256rk:
8690 case VFMADD231PHZ256rkz:
8691 case VFMADD231PHZm:
8692 case VFMADD231PHZmb:
8693 case VFMADD231PHZmbk:
8694 case VFMADD231PHZmbkz:
8695 case VFMADD231PHZmk:
8696 case VFMADD231PHZmkz:
8697 case VFMADD231PHZr:
8698 case VFMADD231PHZrb:
8699 case VFMADD231PHZrbk:
8700 case VFMADD231PHZrbkz:
8701 case VFMADD231PHZrk:
8702 case VFMADD231PHZrkz:
8703 return true;
8704 }
8705 return false;
8706}
8707
8708bool isVPSHAD(unsigned Opcode) {
8709 switch (Opcode) {
8710 case VPSHADmr:
8711 case VPSHADrm:
8712 case VPSHADrr:
8713 case VPSHADrr_REV:
8714 return true;
8715 }
8716 return false;
8717}
8718
8719bool isCLWB(unsigned Opcode) {
8720 return Opcode == CLWB;
8721}
8722
8723bool isPSUBUSB(unsigned Opcode) {
8724 switch (Opcode) {
8725 case MMX_PSUBUSBrm:
8726 case MMX_PSUBUSBrr:
8727 case PSUBUSBrm:
8728 case PSUBUSBrr:
8729 return true;
8730 }
8731 return false;
8732}
8733
8734bool isVCVTTSD2USI(unsigned Opcode) {
8735 switch (Opcode) {
8736 case VCVTTSD2USI64Zrm_Int:
8737 case VCVTTSD2USI64Zrr_Int:
8738 case VCVTTSD2USI64Zrrb_Int:
8739 case VCVTTSD2USIZrm_Int:
8740 case VCVTTSD2USIZrr_Int:
8741 case VCVTTSD2USIZrrb_Int:
8742 return true;
8743 }
8744 return false;
8745}
8746
8747bool isVEXTRACTPS(unsigned Opcode) {
8748 switch (Opcode) {
8749 case VEXTRACTPSZmri:
8750 case VEXTRACTPSZrri:
8751 case VEXTRACTPSmri:
8752 case VEXTRACTPSrri:
8753 return true;
8754 }
8755 return false;
8756}
8757
8758bool isMOVLPD(unsigned Opcode) {
8759 switch (Opcode) {
8760 case MOVLPDmr:
8761 case MOVLPDrm:
8762 return true;
8763 }
8764 return false;
8765}
8766
8767bool isLGDTD(unsigned Opcode) {
8768 return Opcode == LGDT32m;
8769}
8770
8771bool isVPBROADCASTMB2Q(unsigned Opcode) {
8772 switch (Opcode) {
8773 case VPBROADCASTMB2QZ128rr:
8774 case VPBROADCASTMB2QZ256rr:
8775 case VPBROADCASTMB2QZrr:
8776 return true;
8777 }
8778 return false;
8779}
8780
8781bool isOUT(unsigned Opcode) {
8782 switch (Opcode) {
8783 case OUT16ir:
8784 case OUT16rr:
8785 case OUT32ir:
8786 case OUT32rr:
8787 case OUT8ir:
8788 case OUT8rr:
8789 return true;
8790 }
8791 return false;
8792}
8793
8794bool isVMSAVE(unsigned Opcode) {
8795 switch (Opcode) {
8796 case VMSAVE32:
8797 case VMSAVE64:
8798 return true;
8799 }
8800 return false;
8801}
8802
8803bool isVCVTQQ2PD(unsigned Opcode) {
8804 switch (Opcode) {
8805 case VCVTQQ2PDZ128rm:
8806 case VCVTQQ2PDZ128rmb:
8807 case VCVTQQ2PDZ128rmbk:
8808 case VCVTQQ2PDZ128rmbkz:
8809 case VCVTQQ2PDZ128rmk:
8810 case VCVTQQ2PDZ128rmkz:
8811 case VCVTQQ2PDZ128rr:
8812 case VCVTQQ2PDZ128rrk:
8813 case VCVTQQ2PDZ128rrkz:
8814 case VCVTQQ2PDZ256rm:
8815 case VCVTQQ2PDZ256rmb:
8816 case VCVTQQ2PDZ256rmbk:
8817 case VCVTQQ2PDZ256rmbkz:
8818 case VCVTQQ2PDZ256rmk:
8819 case VCVTQQ2PDZ256rmkz:
8820 case VCVTQQ2PDZ256rr:
8821 case VCVTQQ2PDZ256rrk:
8822 case VCVTQQ2PDZ256rrkz:
8823 case VCVTQQ2PDZrm:
8824 case VCVTQQ2PDZrmb:
8825 case VCVTQQ2PDZrmbk:
8826 case VCVTQQ2PDZrmbkz:
8827 case VCVTQQ2PDZrmk:
8828 case VCVTQQ2PDZrmkz:
8829 case VCVTQQ2PDZrr:
8830 case VCVTQQ2PDZrrb:
8831 case VCVTQQ2PDZrrbk:
8832 case VCVTQQ2PDZrrbkz:
8833 case VCVTQQ2PDZrrk:
8834 case VCVTQQ2PDZrrkz:
8835 return true;
8836 }
8837 return false;
8838}
8839
8840bool isVFMADD213PH(unsigned Opcode) {
8841 switch (Opcode) {
8842 case VFMADD213PHZ128m:
8843 case VFMADD213PHZ128mb:
8844 case VFMADD213PHZ128mbk:
8845 case VFMADD213PHZ128mbkz:
8846 case VFMADD213PHZ128mk:
8847 case VFMADD213PHZ128mkz:
8848 case VFMADD213PHZ128r:
8849 case VFMADD213PHZ128rk:
8850 case VFMADD213PHZ128rkz:
8851 case VFMADD213PHZ256m:
8852 case VFMADD213PHZ256mb:
8853 case VFMADD213PHZ256mbk:
8854 case VFMADD213PHZ256mbkz:
8855 case VFMADD213PHZ256mk:
8856 case VFMADD213PHZ256mkz:
8857 case VFMADD213PHZ256r:
8858 case VFMADD213PHZ256rk:
8859 case VFMADD213PHZ256rkz:
8860 case VFMADD213PHZm:
8861 case VFMADD213PHZmb:
8862 case VFMADD213PHZmbk:
8863 case VFMADD213PHZmbkz:
8864 case VFMADD213PHZmk:
8865 case VFMADD213PHZmkz:
8866 case VFMADD213PHZr:
8867 case VFMADD213PHZrb:
8868 case VFMADD213PHZrbk:
8869 case VFMADD213PHZrbkz:
8870 case VFMADD213PHZrk:
8871 case VFMADD213PHZrkz:
8872 return true;
8873 }
8874 return false;
8875}
8876
8877bool isFCMOVBE(unsigned Opcode) {
8878 return Opcode == CMOVBE_F;
8879}
8880
8881bool isMOVSHDUP(unsigned Opcode) {
8882 switch (Opcode) {
8883 case MOVSHDUPrm:
8884 case MOVSHDUPrr:
8885 return true;
8886 }
8887 return false;
8888}
8889
8890bool isVPMOVUSQB(unsigned Opcode) {
8891 switch (Opcode) {
8892 case VPMOVUSQBZ128mr:
8893 case VPMOVUSQBZ128mrk:
8894 case VPMOVUSQBZ128rr:
8895 case VPMOVUSQBZ128rrk:
8896 case VPMOVUSQBZ128rrkz:
8897 case VPMOVUSQBZ256mr:
8898 case VPMOVUSQBZ256mrk:
8899 case VPMOVUSQBZ256rr:
8900 case VPMOVUSQBZ256rrk:
8901 case VPMOVUSQBZ256rrkz:
8902 case VPMOVUSQBZmr:
8903 case VPMOVUSQBZmrk:
8904 case VPMOVUSQBZrr:
8905 case VPMOVUSQBZrrk:
8906 case VPMOVUSQBZrrkz:
8907 return true;
8908 }
8909 return false;
8910}
8911
8912bool isFIST(unsigned Opcode) {
8913 switch (Opcode) {
8914 case IST_F16m:
8915 case IST_F32m:
8916 return true;
8917 }
8918 return false;
8919}
8920
8921bool isHADDPD(unsigned Opcode) {
8922 switch (Opcode) {
8923 case HADDPDrm:
8924 case HADDPDrr:
8925 return true;
8926 }
8927 return false;
8928}
8929
8930bool isPACKSSWB(unsigned Opcode) {
8931 switch (Opcode) {
8932 case MMX_PACKSSWBrm:
8933 case MMX_PACKSSWBrr:
8934 case PACKSSWBrm:
8935 case PACKSSWBrr:
8936 return true;
8937 }
8938 return false;
8939}
8940
8941bool isVPMACSSDQH(unsigned Opcode) {
8942 switch (Opcode) {
8943 case VPMACSSDQHrm:
8944 case VPMACSSDQHrr:
8945 return true;
8946 }
8947 return false;
8948}
8949
8950bool isVFNMSUB132SD(unsigned Opcode) {
8951 switch (Opcode) {
8952 case VFNMSUB132SDZm_Int:
8953 case VFNMSUB132SDZmk_Int:
8954 case VFNMSUB132SDZmkz_Int:
8955 case VFNMSUB132SDZr_Int:
8956 case VFNMSUB132SDZrb_Int:
8957 case VFNMSUB132SDZrbk_Int:
8958 case VFNMSUB132SDZrbkz_Int:
8959 case VFNMSUB132SDZrk_Int:
8960 case VFNMSUB132SDZrkz_Int:
8961 case VFNMSUB132SDm_Int:
8962 case VFNMSUB132SDr_Int:
8963 return true;
8964 }
8965 return false;
8966}
8967
8968bool isVPMASKMOVQ(unsigned Opcode) {
8969 switch (Opcode) {
8970 case VPMASKMOVQYmr:
8971 case VPMASKMOVQYrm:
8972 case VPMASKMOVQmr:
8973 case VPMASKMOVQrm:
8974 return true;
8975 }
8976 return false;
8977}
8978
8979bool isVCOMPRESSPD(unsigned Opcode) {
8980 switch (Opcode) {
8981 case VCOMPRESSPDZ128mr:
8982 case VCOMPRESSPDZ128mrk:
8983 case VCOMPRESSPDZ128rr:
8984 case VCOMPRESSPDZ128rrk:
8985 case VCOMPRESSPDZ128rrkz:
8986 case VCOMPRESSPDZ256mr:
8987 case VCOMPRESSPDZ256mrk:
8988 case VCOMPRESSPDZ256rr:
8989 case VCOMPRESSPDZ256rrk:
8990 case VCOMPRESSPDZ256rrkz:
8991 case VCOMPRESSPDZmr:
8992 case VCOMPRESSPDZmrk:
8993 case VCOMPRESSPDZrr:
8994 case VCOMPRESSPDZrrk:
8995 case VCOMPRESSPDZrrkz:
8996 return true;
8997 }
8998 return false;
8999}
9000
9001bool isVFMADD213SS(unsigned Opcode) {
9002 switch (Opcode) {
9003 case VFMADD213SSZm_Int:
9004 case VFMADD213SSZmk_Int:
9005 case VFMADD213SSZmkz_Int:
9006 case VFMADD213SSZr_Int:
9007 case VFMADD213SSZrb_Int:
9008 case VFMADD213SSZrbk_Int:
9009 case VFMADD213SSZrbkz_Int:
9010 case VFMADD213SSZrk_Int:
9011 case VFMADD213SSZrkz_Int:
9012 case VFMADD213SSm_Int:
9013 case VFMADD213SSr_Int:
9014 return true;
9015 }
9016 return false;
9017}
9018
9019bool isVPCMPQ(unsigned Opcode) {
9020 switch (Opcode) {
9021 case VPCMPQZ128rmbi:
9022 case VPCMPQZ128rmbik:
9023 case VPCMPQZ128rmi:
9024 case VPCMPQZ128rmik:
9025 case VPCMPQZ128rri:
9026 case VPCMPQZ128rrik:
9027 case VPCMPQZ256rmbi:
9028 case VPCMPQZ256rmbik:
9029 case VPCMPQZ256rmi:
9030 case VPCMPQZ256rmik:
9031 case VPCMPQZ256rri:
9032 case VPCMPQZ256rrik:
9033 case VPCMPQZrmbi:
9034 case VPCMPQZrmbik:
9035 case VPCMPQZrmi:
9036 case VPCMPQZrmik:
9037 case VPCMPQZrri:
9038 case VPCMPQZrrik:
9039 return true;
9040 }
9041 return false;
9042}
9043
9044bool isVADDSH(unsigned Opcode) {
9045 switch (Opcode) {
9046 case VADDSHZrm_Int:
9047 case VADDSHZrmk_Int:
9048 case VADDSHZrmkz_Int:
9049 case VADDSHZrr_Int:
9050 case VADDSHZrrb_Int:
9051 case VADDSHZrrbk_Int:
9052 case VADDSHZrrbkz_Int:
9053 case VADDSHZrrk_Int:
9054 case VADDSHZrrkz_Int:
9055 return true;
9056 }
9057 return false;
9058}
9059
9060bool isVFNMADDSD(unsigned Opcode) {
9061 switch (Opcode) {
9062 case VFNMADDSD4mr:
9063 case VFNMADDSD4rm:
9064 case VFNMADDSD4rr:
9065 case VFNMADDSD4rr_REV:
9066 return true;
9067 }
9068 return false;
9069}
9070
9071bool isUMWAIT(unsigned Opcode) {
9072 return Opcode == UMWAIT;
9073}
9074
9075bool isVPUNPCKHDQ(unsigned Opcode) {
9076 switch (Opcode) {
9077 case VPUNPCKHDQYrm:
9078 case VPUNPCKHDQYrr:
9079 case VPUNPCKHDQZ128rm:
9080 case VPUNPCKHDQZ128rmb:
9081 case VPUNPCKHDQZ128rmbk:
9082 case VPUNPCKHDQZ128rmbkz:
9083 case VPUNPCKHDQZ128rmk:
9084 case VPUNPCKHDQZ128rmkz:
9085 case VPUNPCKHDQZ128rr:
9086 case VPUNPCKHDQZ128rrk:
9087 case VPUNPCKHDQZ128rrkz:
9088 case VPUNPCKHDQZ256rm:
9089 case VPUNPCKHDQZ256rmb:
9090 case VPUNPCKHDQZ256rmbk:
9091 case VPUNPCKHDQZ256rmbkz:
9092 case VPUNPCKHDQZ256rmk:
9093 case VPUNPCKHDQZ256rmkz:
9094 case VPUNPCKHDQZ256rr:
9095 case VPUNPCKHDQZ256rrk:
9096 case VPUNPCKHDQZ256rrkz:
9097 case VPUNPCKHDQZrm:
9098 case VPUNPCKHDQZrmb:
9099 case VPUNPCKHDQZrmbk:
9100 case VPUNPCKHDQZrmbkz:
9101 case VPUNPCKHDQZrmk:
9102 case VPUNPCKHDQZrmkz:
9103 case VPUNPCKHDQZrr:
9104 case VPUNPCKHDQZrrk:
9105 case VPUNPCKHDQZrrkz:
9106 case VPUNPCKHDQrm:
9107 case VPUNPCKHDQrr:
9108 return true;
9109 }
9110 return false;
9111}
9112
9113bool isLCALL(unsigned Opcode) {
9114 switch (Opcode) {
9115 case FARCALL16i:
9116 case FARCALL16m:
9117 case FARCALL32i:
9118 case FARCALL64m:
9119 return true;
9120 }
9121 return false;
9122}
9123
9124bool isAESDEC128KL(unsigned Opcode) {
9125 return Opcode == AESDEC128KL;
9126}
9127
9128bool isVSUBPS(unsigned Opcode) {
9129 switch (Opcode) {
9130 case VSUBPSYrm:
9131 case VSUBPSYrr:
9132 case VSUBPSZ128rm:
9133 case VSUBPSZ128rmb:
9134 case VSUBPSZ128rmbk:
9135 case VSUBPSZ128rmbkz:
9136 case VSUBPSZ128rmk:
9137 case VSUBPSZ128rmkz:
9138 case VSUBPSZ128rr:
9139 case VSUBPSZ128rrk:
9140 case VSUBPSZ128rrkz:
9141 case VSUBPSZ256rm:
9142 case VSUBPSZ256rmb:
9143 case VSUBPSZ256rmbk:
9144 case VSUBPSZ256rmbkz:
9145 case VSUBPSZ256rmk:
9146 case VSUBPSZ256rmkz:
9147 case VSUBPSZ256rr:
9148 case VSUBPSZ256rrk:
9149 case VSUBPSZ256rrkz:
9150 case VSUBPSZrm:
9151 case VSUBPSZrmb:
9152 case VSUBPSZrmbk:
9153 case VSUBPSZrmbkz:
9154 case VSUBPSZrmk:
9155 case VSUBPSZrmkz:
9156 case VSUBPSZrr:
9157 case VSUBPSZrrb:
9158 case VSUBPSZrrbk:
9159 case VSUBPSZrrbkz:
9160 case VSUBPSZrrk:
9161 case VSUBPSZrrkz:
9162 case VSUBPSrm:
9163 case VSUBPSrr:
9164 return true;
9165 }
9166 return false;
9167}
9168
9169bool isFSTP(unsigned Opcode) {
9170 switch (Opcode) {
9171 case ST_FP32m:
9172 case ST_FP64m:
9173 case ST_FP80m:
9174 case ST_FPrr:
9175 return true;
9176 }
9177 return false;
9178}
9179
9180bool isVCVTUDQ2PD(unsigned Opcode) {
9181 switch (Opcode) {
9182 case VCVTUDQ2PDZ128rm:
9183 case VCVTUDQ2PDZ128rmb:
9184 case VCVTUDQ2PDZ128rmbk:
9185 case VCVTUDQ2PDZ128rmbkz:
9186 case VCVTUDQ2PDZ128rmk:
9187 case VCVTUDQ2PDZ128rmkz:
9188 case VCVTUDQ2PDZ128rr:
9189 case VCVTUDQ2PDZ128rrk:
9190 case VCVTUDQ2PDZ128rrkz:
9191 case VCVTUDQ2PDZ256rm:
9192 case VCVTUDQ2PDZ256rmb:
9193 case VCVTUDQ2PDZ256rmbk:
9194 case VCVTUDQ2PDZ256rmbkz:
9195 case VCVTUDQ2PDZ256rmk:
9196 case VCVTUDQ2PDZ256rmkz:
9197 case VCVTUDQ2PDZ256rr:
9198 case VCVTUDQ2PDZ256rrk:
9199 case VCVTUDQ2PDZ256rrkz:
9200 case VCVTUDQ2PDZrm:
9201 case VCVTUDQ2PDZrmb:
9202 case VCVTUDQ2PDZrmbk:
9203 case VCVTUDQ2PDZrmbkz:
9204 case VCVTUDQ2PDZrmk:
9205 case VCVTUDQ2PDZrmkz:
9206 case VCVTUDQ2PDZrr:
9207 case VCVTUDQ2PDZrrk:
9208 case VCVTUDQ2PDZrrkz:
9209 return true;
9210 }
9211 return false;
9212}
9213
9214bool isVPMOVSWB(unsigned Opcode) {
9215 switch (Opcode) {
9216 case VPMOVSWBZ128mr:
9217 case VPMOVSWBZ128mrk:
9218 case VPMOVSWBZ128rr:
9219 case VPMOVSWBZ128rrk:
9220 case VPMOVSWBZ128rrkz:
9221 case VPMOVSWBZ256mr:
9222 case VPMOVSWBZ256mrk:
9223 case VPMOVSWBZ256rr:
9224 case VPMOVSWBZ256rrk:
9225 case VPMOVSWBZ256rrkz:
9226 case VPMOVSWBZmr:
9227 case VPMOVSWBZmrk:
9228 case VPMOVSWBZrr:
9229 case VPMOVSWBZrrk:
9230 case VPMOVSWBZrrkz:
9231 return true;
9232 }
9233 return false;
9234}
9235
9236bool isVPANDNQ(unsigned Opcode) {
9237 switch (Opcode) {
9238 case VPANDNQZ128rm:
9239 case VPANDNQZ128rmb:
9240 case VPANDNQZ128rmbk:
9241 case VPANDNQZ128rmbkz:
9242 case VPANDNQZ128rmk:
9243 case VPANDNQZ128rmkz:
9244 case VPANDNQZ128rr:
9245 case VPANDNQZ128rrk:
9246 case VPANDNQZ128rrkz:
9247 case VPANDNQZ256rm:
9248 case VPANDNQZ256rmb:
9249 case VPANDNQZ256rmbk:
9250 case VPANDNQZ256rmbkz:
9251 case VPANDNQZ256rmk:
9252 case VPANDNQZ256rmkz:
9253 case VPANDNQZ256rr:
9254 case VPANDNQZ256rrk:
9255 case VPANDNQZ256rrkz:
9256 case VPANDNQZrm:
9257 case VPANDNQZrmb:
9258 case VPANDNQZrmbk:
9259 case VPANDNQZrmbkz:
9260 case VPANDNQZrmk:
9261 case VPANDNQZrmkz:
9262 case VPANDNQZrr:
9263 case VPANDNQZrrk:
9264 case VPANDNQZrrkz:
9265 return true;
9266 }
9267 return false;
9268}
9269
9270bool isSYSENTER(unsigned Opcode) {
9271 return Opcode == SYSENTER;
9272}
9273
9274bool isVPHADDWD(unsigned Opcode) {
9275 switch (Opcode) {
9276 case VPHADDWDrm:
9277 case VPHADDWDrr:
9278 return true;
9279 }
9280 return false;
9281}
9282
9283bool isVMOVHPD(unsigned Opcode) {
9284 switch (Opcode) {
9285 case VMOVHPDZ128mr:
9286 case VMOVHPDZ128rm:
9287 case VMOVHPDmr:
9288 case VMOVHPDrm:
9289 return true;
9290 }
9291 return false;
9292}
9293
9294bool isMOVHPD(unsigned Opcode) {
9295 switch (Opcode) {
9296 case MOVHPDmr:
9297 case MOVHPDrm:
9298 return true;
9299 }
9300 return false;
9301}
9302
9303bool isVDIVPH(unsigned Opcode) {
9304 switch (Opcode) {
9305 case VDIVPHZ128rm:
9306 case VDIVPHZ128rmb:
9307 case VDIVPHZ128rmbk:
9308 case VDIVPHZ128rmbkz:
9309 case VDIVPHZ128rmk:
9310 case VDIVPHZ128rmkz:
9311 case VDIVPHZ128rr:
9312 case VDIVPHZ128rrk:
9313 case VDIVPHZ128rrkz:
9314 case VDIVPHZ256rm:
9315 case VDIVPHZ256rmb:
9316 case VDIVPHZ256rmbk:
9317 case VDIVPHZ256rmbkz:
9318 case VDIVPHZ256rmk:
9319 case VDIVPHZ256rmkz:
9320 case VDIVPHZ256rr:
9321 case VDIVPHZ256rrk:
9322 case VDIVPHZ256rrkz:
9323 case VDIVPHZrm:
9324 case VDIVPHZrmb:
9325 case VDIVPHZrmbk:
9326 case VDIVPHZrmbkz:
9327 case VDIVPHZrmk:
9328 case VDIVPHZrmkz:
9329 case VDIVPHZrr:
9330 case VDIVPHZrrb:
9331 case VDIVPHZrrbk:
9332 case VDIVPHZrrbkz:
9333 case VDIVPHZrrk:
9334 case VDIVPHZrrkz:
9335 return true;
9336 }
9337 return false;
9338}
9339
9340bool isFFREE(unsigned Opcode) {
9341 return Opcode == FFREE;
9342}
9343
9344bool isVGATHERPF1DPS(unsigned Opcode) {
9345 return Opcode == VGATHERPF1DPSm;
9346}
9347
9348bool isVPCMPESTRIQ(unsigned Opcode) {
9349 switch (Opcode) {
9350 case VPCMPESTRIQrmi:
9351 case VPCMPESTRIQrri:
9352 return true;
9353 }
9354 return false;
9355}
9356
9357bool isVFNMADD231PD(unsigned Opcode) {
9358 switch (Opcode) {
9359 case VFNMADD231PDYm:
9360 case VFNMADD231PDYr:
9361 case VFNMADD231PDZ128m:
9362 case VFNMADD231PDZ128mb:
9363 case VFNMADD231PDZ128mbk:
9364 case VFNMADD231PDZ128mbkz:
9365 case VFNMADD231PDZ128mk:
9366 case VFNMADD231PDZ128mkz:
9367 case VFNMADD231PDZ128r:
9368 case VFNMADD231PDZ128rk:
9369 case VFNMADD231PDZ128rkz:
9370 case VFNMADD231PDZ256m:
9371 case VFNMADD231PDZ256mb:
9372 case VFNMADD231PDZ256mbk:
9373 case VFNMADD231PDZ256mbkz:
9374 case VFNMADD231PDZ256mk:
9375 case VFNMADD231PDZ256mkz:
9376 case VFNMADD231PDZ256r:
9377 case VFNMADD231PDZ256rk:
9378 case VFNMADD231PDZ256rkz:
9379 case VFNMADD231PDZm:
9380 case VFNMADD231PDZmb:
9381 case VFNMADD231PDZmbk:
9382 case VFNMADD231PDZmbkz:
9383 case VFNMADD231PDZmk:
9384 case VFNMADD231PDZmkz:
9385 case VFNMADD231PDZr:
9386 case VFNMADD231PDZrb:
9387 case VFNMADD231PDZrbk:
9388 case VFNMADD231PDZrbkz:
9389 case VFNMADD231PDZrk:
9390 case VFNMADD231PDZrkz:
9391 case VFNMADD231PDm:
9392 case VFNMADD231PDr:
9393 return true;
9394 }
9395 return false;
9396}
9397
9398bool isVFCMULCPH(unsigned Opcode) {
9399 switch (Opcode) {
9400 case VFCMULCPHZ128rm:
9401 case VFCMULCPHZ128rmb:
9402 case VFCMULCPHZ128rmbk:
9403 case VFCMULCPHZ128rmbkz:
9404 case VFCMULCPHZ128rmk:
9405 case VFCMULCPHZ128rmkz:
9406 case VFCMULCPHZ128rr:
9407 case VFCMULCPHZ128rrk:
9408 case VFCMULCPHZ128rrkz:
9409 case VFCMULCPHZ256rm:
9410 case VFCMULCPHZ256rmb:
9411 case VFCMULCPHZ256rmbk:
9412 case VFCMULCPHZ256rmbkz:
9413 case VFCMULCPHZ256rmk:
9414 case VFCMULCPHZ256rmkz:
9415 case VFCMULCPHZ256rr:
9416 case VFCMULCPHZ256rrk:
9417 case VFCMULCPHZ256rrkz:
9418 case VFCMULCPHZrm:
9419 case VFCMULCPHZrmb:
9420 case VFCMULCPHZrmbk:
9421 case VFCMULCPHZrmbkz:
9422 case VFCMULCPHZrmk:
9423 case VFCMULCPHZrmkz:
9424 case VFCMULCPHZrr:
9425 case VFCMULCPHZrrb:
9426 case VFCMULCPHZrrbk:
9427 case VFCMULCPHZrrbkz:
9428 case VFCMULCPHZrrk:
9429 case VFCMULCPHZrrkz:
9430 return true;
9431 }
9432 return false;
9433}
9434
9435bool isVPADDD(unsigned Opcode) {
9436 switch (Opcode) {
9437 case VPADDDYrm:
9438 case VPADDDYrr:
9439 case VPADDDZ128rm:
9440 case VPADDDZ128rmb:
9441 case VPADDDZ128rmbk:
9442 case VPADDDZ128rmbkz:
9443 case VPADDDZ128rmk:
9444 case VPADDDZ128rmkz:
9445 case VPADDDZ128rr:
9446 case VPADDDZ128rrk:
9447 case VPADDDZ128rrkz:
9448 case VPADDDZ256rm:
9449 case VPADDDZ256rmb:
9450 case VPADDDZ256rmbk:
9451 case VPADDDZ256rmbkz:
9452 case VPADDDZ256rmk:
9453 case VPADDDZ256rmkz:
9454 case VPADDDZ256rr:
9455 case VPADDDZ256rrk:
9456 case VPADDDZ256rrkz:
9457 case VPADDDZrm:
9458 case VPADDDZrmb:
9459 case VPADDDZrmbk:
9460 case VPADDDZrmbkz:
9461 case VPADDDZrmk:
9462 case VPADDDZrmkz:
9463 case VPADDDZrr:
9464 case VPADDDZrrk:
9465 case VPADDDZrrkz:
9466 case VPADDDrm:
9467 case VPADDDrr:
9468 return true;
9469 }
9470 return false;
9471}
9472
9473bool isVPCOMUQ(unsigned Opcode) {
9474 switch (Opcode) {
9475 case VPCOMUQmi:
9476 case VPCOMUQri:
9477 return true;
9478 }
9479 return false;
9480}
9481
9482bool isVSM3MSG2(unsigned Opcode) {
9483 switch (Opcode) {
9484 case VSM3MSG2rm:
9485 case VSM3MSG2rr:
9486 return true;
9487 }
9488 return false;
9489}
9490
9491bool isVERR(unsigned Opcode) {
9492 switch (Opcode) {
9493 case VERRm:
9494 case VERRr:
9495 return true;
9496 }
9497 return false;
9498}
9499
9500bool isKORTESTQ(unsigned Opcode) {
9501 return Opcode == KORTESTQkk;
9502}
9503
9504bool isVFMSUB132SD(unsigned Opcode) {
9505 switch (Opcode) {
9506 case VFMSUB132SDZm_Int:
9507 case VFMSUB132SDZmk_Int:
9508 case VFMSUB132SDZmkz_Int:
9509 case VFMSUB132SDZr_Int:
9510 case VFMSUB132SDZrb_Int:
9511 case VFMSUB132SDZrbk_Int:
9512 case VFMSUB132SDZrbkz_Int:
9513 case VFMSUB132SDZrk_Int:
9514 case VFMSUB132SDZrkz_Int:
9515 case VFMSUB132SDm_Int:
9516 case VFMSUB132SDr_Int:
9517 return true;
9518 }
9519 return false;
9520}
9521
9522bool isTILEZERO(unsigned Opcode) {
9523 return Opcode == TILEZERO;
9524}
9525
9526bool isPFADD(unsigned Opcode) {
9527 switch (Opcode) {
9528 case PFADDrm:
9529 case PFADDrr:
9530 return true;
9531 }
9532 return false;
9533}
9534
9535bool isVCVTSI2SD(unsigned Opcode) {
9536 switch (Opcode) {
9537 case VCVTSI2SDZrm_Int:
9538 case VCVTSI2SDZrr_Int:
9539 case VCVTSI2SDrm_Int:
9540 case VCVTSI2SDrr_Int:
9541 case VCVTSI642SDZrm_Int:
9542 case VCVTSI642SDZrr_Int:
9543 case VCVTSI642SDZrrb_Int:
9544 case VCVTSI642SDrm_Int:
9545 case VCVTSI642SDrr_Int:
9546 return true;
9547 }
9548 return false;
9549}
9550
9551bool isTILELOADDRS(unsigned Opcode) {
9552 switch (Opcode) {
9553 case TILELOADDRS:
9554 case TILELOADDRS_EVEX:
9555 return true;
9556 }
9557 return false;
9558}
9559
9560bool isVSTMXCSR(unsigned Opcode) {
9561 return Opcode == VSTMXCSR;
9562}
9563
9564bool isVCVTTSH2SI(unsigned Opcode) {
9565 switch (Opcode) {
9566 case VCVTTSH2SI64Zrm_Int:
9567 case VCVTTSH2SI64Zrr_Int:
9568 case VCVTTSH2SI64Zrrb_Int:
9569 case VCVTTSH2SIZrm_Int:
9570 case VCVTTSH2SIZrr_Int:
9571 case VCVTTSH2SIZrrb_Int:
9572 return true;
9573 }
9574 return false;
9575}
9576
9577bool isRET(unsigned Opcode) {
9578 switch (Opcode) {
9579 case RET16:
9580 case RET32:
9581 case RET64:
9582 case RETI16:
9583 case RETI32:
9584 case RETI64:
9585 return true;
9586 }
9587 return false;
9588}
9589
9590bool isLZCNT(unsigned Opcode) {
9591 switch (Opcode) {
9592 case LZCNT16rm:
9593 case LZCNT16rm_EVEX:
9594 case LZCNT16rm_NF:
9595 case LZCNT16rr:
9596 case LZCNT16rr_EVEX:
9597 case LZCNT16rr_NF:
9598 case LZCNT32rm:
9599 case LZCNT32rm_EVEX:
9600 case LZCNT32rm_NF:
9601 case LZCNT32rr:
9602 case LZCNT32rr_EVEX:
9603 case LZCNT32rr_NF:
9604 case LZCNT64rm:
9605 case LZCNT64rm_EVEX:
9606 case LZCNT64rm_NF:
9607 case LZCNT64rr:
9608 case LZCNT64rr_EVEX:
9609 case LZCNT64rr_NF:
9610 return true;
9611 }
9612 return false;
9613}
9614
9615bool isMULPD(unsigned Opcode) {
9616 switch (Opcode) {
9617 case MULPDrm:
9618 case MULPDrr:
9619 return true;
9620 }
9621 return false;
9622}
9623
9624bool isVBROADCASTI32X2(unsigned Opcode) {
9625 switch (Opcode) {
9626 case VBROADCASTI32X2Z128rm:
9627 case VBROADCASTI32X2Z128rmk:
9628 case VBROADCASTI32X2Z128rmkz:
9629 case VBROADCASTI32X2Z128rr:
9630 case VBROADCASTI32X2Z128rrk:
9631 case VBROADCASTI32X2Z128rrkz:
9632 case VBROADCASTI32X2Z256rm:
9633 case VBROADCASTI32X2Z256rmk:
9634 case VBROADCASTI32X2Z256rmkz:
9635 case VBROADCASTI32X2Z256rr:
9636 case VBROADCASTI32X2Z256rrk:
9637 case VBROADCASTI32X2Z256rrkz:
9638 case VBROADCASTI32X2Zrm:
9639 case VBROADCASTI32X2Zrmk:
9640 case VBROADCASTI32X2Zrmkz:
9641 case VBROADCASTI32X2Zrr:
9642 case VBROADCASTI32X2Zrrk:
9643 case VBROADCASTI32X2Zrrkz:
9644 return true;
9645 }
9646 return false;
9647}
9648
9649bool isVCVTPH2W(unsigned Opcode) {
9650 switch (Opcode) {
9651 case VCVTPH2WZ128rm:
9652 case VCVTPH2WZ128rmb:
9653 case VCVTPH2WZ128rmbk:
9654 case VCVTPH2WZ128rmbkz:
9655 case VCVTPH2WZ128rmk:
9656 case VCVTPH2WZ128rmkz:
9657 case VCVTPH2WZ128rr:
9658 case VCVTPH2WZ128rrk:
9659 case VCVTPH2WZ128rrkz:
9660 case VCVTPH2WZ256rm:
9661 case VCVTPH2WZ256rmb:
9662 case VCVTPH2WZ256rmbk:
9663 case VCVTPH2WZ256rmbkz:
9664 case VCVTPH2WZ256rmk:
9665 case VCVTPH2WZ256rmkz:
9666 case VCVTPH2WZ256rr:
9667 case VCVTPH2WZ256rrk:
9668 case VCVTPH2WZ256rrkz:
9669 case VCVTPH2WZrm:
9670 case VCVTPH2WZrmb:
9671 case VCVTPH2WZrmbk:
9672 case VCVTPH2WZrmbkz:
9673 case VCVTPH2WZrmk:
9674 case VCVTPH2WZrmkz:
9675 case VCVTPH2WZrr:
9676 case VCVTPH2WZrrb:
9677 case VCVTPH2WZrrbk:
9678 case VCVTPH2WZrrbkz:
9679 case VCVTPH2WZrrk:
9680 case VCVTPH2WZrrkz:
9681 return true;
9682 }
9683 return false;
9684}
9685
9686bool isCQO(unsigned Opcode) {
9687 return Opcode == CQO;
9688}
9689
9690bool isFSUBR(unsigned Opcode) {
9691 switch (Opcode) {
9692 case SUBR_F32m:
9693 case SUBR_F64m:
9694 case SUBR_FST0r:
9695 case SUBR_FrST0:
9696 return true;
9697 }
9698 return false;
9699}
9700
9701bool isDPPD(unsigned Opcode) {
9702 switch (Opcode) {
9703 case DPPDrmi:
9704 case DPPDrri:
9705 return true;
9706 }
9707 return false;
9708}
9709
9710bool isFCOS(unsigned Opcode) {
9711 return Opcode == FCOS;
9712}
9713
9714bool isXSAVES(unsigned Opcode) {
9715 return Opcode == XSAVES;
9716}
9717
9718bool isTZCNT(unsigned Opcode) {
9719 switch (Opcode) {
9720 case TZCNT16rm:
9721 case TZCNT16rm_EVEX:
9722 case TZCNT16rm_NF:
9723 case TZCNT16rr:
9724 case TZCNT16rr_EVEX:
9725 case TZCNT16rr_NF:
9726 case TZCNT32rm:
9727 case TZCNT32rm_EVEX:
9728 case TZCNT32rm_NF:
9729 case TZCNT32rr:
9730 case TZCNT32rr_EVEX:
9731 case TZCNT32rr_NF:
9732 case TZCNT64rm:
9733 case TZCNT64rm_EVEX:
9734 case TZCNT64rm_NF:
9735 case TZCNT64rr:
9736 case TZCNT64rr_EVEX:
9737 case TZCNT64rr_NF:
9738 return true;
9739 }
9740 return false;
9741}
9742
9743bool isLJMP(unsigned Opcode) {
9744 switch (Opcode) {
9745 case FARJMP16i:
9746 case FARJMP16m:
9747 case FARJMP32i:
9748 case FARJMP64m:
9749 return true;
9750 }
9751 return false;
9752}
9753
9754bool isCMOVCC(unsigned Opcode) {
9755 switch (Opcode) {
9756 case CMOV16rm:
9757 case CMOV16rm_ND:
9758 case CMOV16rr:
9759 case CMOV16rr_ND:
9760 case CMOV32rm:
9761 case CMOV32rm_ND:
9762 case CMOV32rr:
9763 case CMOV32rr_ND:
9764 case CMOV64rm:
9765 case CMOV64rm_ND:
9766 case CMOV64rr:
9767 case CMOV64rr_ND:
9768 return true;
9769 }
9770 return false;
9771}
9772
9773bool isVCVTBIASPH2HF8(unsigned Opcode) {
9774 switch (Opcode) {
9775 case VCVTBIASPH2HF8Z128rm:
9776 case VCVTBIASPH2HF8Z128rmb:
9777 case VCVTBIASPH2HF8Z128rmbk:
9778 case VCVTBIASPH2HF8Z128rmbkz:
9779 case VCVTBIASPH2HF8Z128rmk:
9780 case VCVTBIASPH2HF8Z128rmkz:
9781 case VCVTBIASPH2HF8Z128rr:
9782 case VCVTBIASPH2HF8Z128rrk:
9783 case VCVTBIASPH2HF8Z128rrkz:
9784 case VCVTBIASPH2HF8Z256rm:
9785 case VCVTBIASPH2HF8Z256rmb:
9786 case VCVTBIASPH2HF8Z256rmbk:
9787 case VCVTBIASPH2HF8Z256rmbkz:
9788 case VCVTBIASPH2HF8Z256rmk:
9789 case VCVTBIASPH2HF8Z256rmkz:
9790 case VCVTBIASPH2HF8Z256rr:
9791 case VCVTBIASPH2HF8Z256rrk:
9792 case VCVTBIASPH2HF8Z256rrkz:
9793 case VCVTBIASPH2HF8Zrm:
9794 case VCVTBIASPH2HF8Zrmb:
9795 case VCVTBIASPH2HF8Zrmbk:
9796 case VCVTBIASPH2HF8Zrmbkz:
9797 case VCVTBIASPH2HF8Zrmk:
9798 case VCVTBIASPH2HF8Zrmkz:
9799 case VCVTBIASPH2HF8Zrr:
9800 case VCVTBIASPH2HF8Zrrk:
9801 case VCVTBIASPH2HF8Zrrkz:
9802 return true;
9803 }
9804 return false;
9805}
9806
9807bool isINVEPT(unsigned Opcode) {
9808 switch (Opcode) {
9809 case INVEPT32:
9810 case INVEPT64:
9811 case INVEPT64_EVEX:
9812 return true;
9813 }
9814 return false;
9815}
9816
9817bool isADDSUBPD(unsigned Opcode) {
9818 switch (Opcode) {
9819 case ADDSUBPDrm:
9820 case ADDSUBPDrr:
9821 return true;
9822 }
9823 return false;
9824}
9825
9826bool isVCVTSS2SD(unsigned Opcode) {
9827 switch (Opcode) {
9828 case VCVTSS2SDZrm_Int:
9829 case VCVTSS2SDZrmk_Int:
9830 case VCVTSS2SDZrmkz_Int:
9831 case VCVTSS2SDZrr_Int:
9832 case VCVTSS2SDZrrb_Int:
9833 case VCVTSS2SDZrrbk_Int:
9834 case VCVTSS2SDZrrbkz_Int:
9835 case VCVTSS2SDZrrk_Int:
9836 case VCVTSS2SDZrrkz_Int:
9837 case VCVTSS2SDrm_Int:
9838 case VCVTSS2SDrr_Int:
9839 return true;
9840 }
9841 return false;
9842}
9843
9844bool isVMOVSHDUP(unsigned Opcode) {
9845 switch (Opcode) {
9846 case VMOVSHDUPYrm:
9847 case VMOVSHDUPYrr:
9848 case VMOVSHDUPZ128rm:
9849 case VMOVSHDUPZ128rmk:
9850 case VMOVSHDUPZ128rmkz:
9851 case VMOVSHDUPZ128rr:
9852 case VMOVSHDUPZ128rrk:
9853 case VMOVSHDUPZ128rrkz:
9854 case VMOVSHDUPZ256rm:
9855 case VMOVSHDUPZ256rmk:
9856 case VMOVSHDUPZ256rmkz:
9857 case VMOVSHDUPZ256rr:
9858 case VMOVSHDUPZ256rrk:
9859 case VMOVSHDUPZ256rrkz:
9860 case VMOVSHDUPZrm:
9861 case VMOVSHDUPZrmk:
9862 case VMOVSHDUPZrmkz:
9863 case VMOVSHDUPZrr:
9864 case VMOVSHDUPZrrk:
9865 case VMOVSHDUPZrrkz:
9866 case VMOVSHDUPrm:
9867 case VMOVSHDUPrr:
9868 return true;
9869 }
9870 return false;
9871}
9872
9873bool isKSHIFTRD(unsigned Opcode) {
9874 return Opcode == KSHIFTRDki;
9875}
9876
9877bool isVPTERNLOGD(unsigned Opcode) {
9878 switch (Opcode) {
9879 case VPTERNLOGDZ128rmbi:
9880 case VPTERNLOGDZ128rmbik:
9881 case VPTERNLOGDZ128rmbikz:
9882 case VPTERNLOGDZ128rmi:
9883 case VPTERNLOGDZ128rmik:
9884 case VPTERNLOGDZ128rmikz:
9885 case VPTERNLOGDZ128rri:
9886 case VPTERNLOGDZ128rrik:
9887 case VPTERNLOGDZ128rrikz:
9888 case VPTERNLOGDZ256rmbi:
9889 case VPTERNLOGDZ256rmbik:
9890 case VPTERNLOGDZ256rmbikz:
9891 case VPTERNLOGDZ256rmi:
9892 case VPTERNLOGDZ256rmik:
9893 case VPTERNLOGDZ256rmikz:
9894 case VPTERNLOGDZ256rri:
9895 case VPTERNLOGDZ256rrik:
9896 case VPTERNLOGDZ256rrikz:
9897 case VPTERNLOGDZrmbi:
9898 case VPTERNLOGDZrmbik:
9899 case VPTERNLOGDZrmbikz:
9900 case VPTERNLOGDZrmi:
9901 case VPTERNLOGDZrmik:
9902 case VPTERNLOGDZrmikz:
9903 case VPTERNLOGDZrri:
9904 case VPTERNLOGDZrrik:
9905 case VPTERNLOGDZrrikz:
9906 return true;
9907 }
9908 return false;
9909}
9910
9911bool isPADDQ(unsigned Opcode) {
9912 switch (Opcode) {
9913 case MMX_PADDQrm:
9914 case MMX_PADDQrr:
9915 case PADDQrm:
9916 case PADDQrr:
9917 return true;
9918 }
9919 return false;
9920}
9921
9922bool isVEXTRACTI64X4(unsigned Opcode) {
9923 switch (Opcode) {
9924 case VEXTRACTI64X4Zmri:
9925 case VEXTRACTI64X4Zmrik:
9926 case VEXTRACTI64X4Zrri:
9927 case VEXTRACTI64X4Zrrik:
9928 case VEXTRACTI64X4Zrrikz:
9929 return true;
9930 }
9931 return false;
9932}
9933
9934bool isVFMSUB231SS(unsigned Opcode) {
9935 switch (Opcode) {
9936 case VFMSUB231SSZm_Int:
9937 case VFMSUB231SSZmk_Int:
9938 case VFMSUB231SSZmkz_Int:
9939 case VFMSUB231SSZr_Int:
9940 case VFMSUB231SSZrb_Int:
9941 case VFMSUB231SSZrbk_Int:
9942 case VFMSUB231SSZrbkz_Int:
9943 case VFMSUB231SSZrk_Int:
9944 case VFMSUB231SSZrkz_Int:
9945 case VFMSUB231SSm_Int:
9946 case VFMSUB231SSr_Int:
9947 return true;
9948 }
9949 return false;
9950}
9951
9952bool isVPCMPEQB(unsigned Opcode) {
9953 switch (Opcode) {
9954 case VPCMPEQBYrm:
9955 case VPCMPEQBYrr:
9956 case VPCMPEQBZ128rm:
9957 case VPCMPEQBZ128rmk:
9958 case VPCMPEQBZ128rr:
9959 case VPCMPEQBZ128rrk:
9960 case VPCMPEQBZ256rm:
9961 case VPCMPEQBZ256rmk:
9962 case VPCMPEQBZ256rr:
9963 case VPCMPEQBZ256rrk:
9964 case VPCMPEQBZrm:
9965 case VPCMPEQBZrmk:
9966 case VPCMPEQBZrr:
9967 case VPCMPEQBZrrk:
9968 case VPCMPEQBrm:
9969 case VPCMPEQBrr:
9970 return true;
9971 }
9972 return false;
9973}
9974
9975bool isLEA(unsigned Opcode) {
9976 switch (Opcode) {
9977 case LEA16r:
9978 case LEA32r:
9979 case LEA64_32r:
9980 case LEA64r:
9981 return true;
9982 }
9983 return false;
9984}
9985
9986bool isPSUBB(unsigned Opcode) {
9987 switch (Opcode) {
9988 case MMX_PSUBBrm:
9989 case MMX_PSUBBrr:
9990 case PSUBBrm:
9991 case PSUBBrr:
9992 return true;
9993 }
9994 return false;
9995}
9996
9997bool isKADDQ(unsigned Opcode) {
9998 return Opcode == KADDQkk;
9999}
10000
10001bool isMOVSX(unsigned Opcode) {
10002 switch (Opcode) {
10003 case MOVSX16rm16:
10004 case MOVSX16rm8:
10005 case MOVSX16rr16:
10006 case MOVSX16rr8:
10007 case MOVSX32rm16:
10008 case MOVSX32rm8:
10009 case MOVSX32rr16:
10010 case MOVSX32rr8:
10011 case MOVSX64rm16:
10012 case MOVSX64rm8:
10013 case MOVSX64rr16:
10014 case MOVSX64rr8:
10015 return true;
10016 }
10017 return false;
10018}
10019
10020bool isVALIGNQ(unsigned Opcode) {
10021 switch (Opcode) {
10022 case VALIGNQZ128rmbi:
10023 case VALIGNQZ128rmbik:
10024 case VALIGNQZ128rmbikz:
10025 case VALIGNQZ128rmi:
10026 case VALIGNQZ128rmik:
10027 case VALIGNQZ128rmikz:
10028 case VALIGNQZ128rri:
10029 case VALIGNQZ128rrik:
10030 case VALIGNQZ128rrikz:
10031 case VALIGNQZ256rmbi:
10032 case VALIGNQZ256rmbik:
10033 case VALIGNQZ256rmbikz:
10034 case VALIGNQZ256rmi:
10035 case VALIGNQZ256rmik:
10036 case VALIGNQZ256rmikz:
10037 case VALIGNQZ256rri:
10038 case VALIGNQZ256rrik:
10039 case VALIGNQZ256rrikz:
10040 case VALIGNQZrmbi:
10041 case VALIGNQZrmbik:
10042 case VALIGNQZrmbikz:
10043 case VALIGNQZrmi:
10044 case VALIGNQZrmik:
10045 case VALIGNQZrmikz:
10046 case VALIGNQZrri:
10047 case VALIGNQZrrik:
10048 case VALIGNQZrrikz:
10049 return true;
10050 }
10051 return false;
10052}
10053
10054bool isVCVTNE2PS2BF16(unsigned Opcode) {
10055 switch (Opcode) {
10056 case VCVTNE2PS2BF16Z128rm:
10057 case VCVTNE2PS2BF16Z128rmb:
10058 case VCVTNE2PS2BF16Z128rmbk:
10059 case VCVTNE2PS2BF16Z128rmbkz:
10060 case VCVTNE2PS2BF16Z128rmk:
10061 case VCVTNE2PS2BF16Z128rmkz:
10062 case VCVTNE2PS2BF16Z128rr:
10063 case VCVTNE2PS2BF16Z128rrk:
10064 case VCVTNE2PS2BF16Z128rrkz:
10065 case VCVTNE2PS2BF16Z256rm:
10066 case VCVTNE2PS2BF16Z256rmb:
10067 case VCVTNE2PS2BF16Z256rmbk:
10068 case VCVTNE2PS2BF16Z256rmbkz:
10069 case VCVTNE2PS2BF16Z256rmk:
10070 case VCVTNE2PS2BF16Z256rmkz:
10071 case VCVTNE2PS2BF16Z256rr:
10072 case VCVTNE2PS2BF16Z256rrk:
10073 case VCVTNE2PS2BF16Z256rrkz:
10074 case VCVTNE2PS2BF16Zrm:
10075 case VCVTNE2PS2BF16Zrmb:
10076 case VCVTNE2PS2BF16Zrmbk:
10077 case VCVTNE2PS2BF16Zrmbkz:
10078 case VCVTNE2PS2BF16Zrmk:
10079 case VCVTNE2PS2BF16Zrmkz:
10080 case VCVTNE2PS2BF16Zrr:
10081 case VCVTNE2PS2BF16Zrrk:
10082 case VCVTNE2PS2BF16Zrrkz:
10083 return true;
10084 }
10085 return false;
10086}
10087
10088bool isVPSRAW(unsigned Opcode) {
10089 switch (Opcode) {
10090 case VPSRAWYri:
10091 case VPSRAWYrm:
10092 case VPSRAWYrr:
10093 case VPSRAWZ128mi:
10094 case VPSRAWZ128mik:
10095 case VPSRAWZ128mikz:
10096 case VPSRAWZ128ri:
10097 case VPSRAWZ128rik:
10098 case VPSRAWZ128rikz:
10099 case VPSRAWZ128rm:
10100 case VPSRAWZ128rmk:
10101 case VPSRAWZ128rmkz:
10102 case VPSRAWZ128rr:
10103 case VPSRAWZ128rrk:
10104 case VPSRAWZ128rrkz:
10105 case VPSRAWZ256mi:
10106 case VPSRAWZ256mik:
10107 case VPSRAWZ256mikz:
10108 case VPSRAWZ256ri:
10109 case VPSRAWZ256rik:
10110 case VPSRAWZ256rikz:
10111 case VPSRAWZ256rm:
10112 case VPSRAWZ256rmk:
10113 case VPSRAWZ256rmkz:
10114 case VPSRAWZ256rr:
10115 case VPSRAWZ256rrk:
10116 case VPSRAWZ256rrkz:
10117 case VPSRAWZmi:
10118 case VPSRAWZmik:
10119 case VPSRAWZmikz:
10120 case VPSRAWZri:
10121 case VPSRAWZrik:
10122 case VPSRAWZrikz:
10123 case VPSRAWZrm:
10124 case VPSRAWZrmk:
10125 case VPSRAWZrmkz:
10126 case VPSRAWZrr:
10127 case VPSRAWZrrk:
10128 case VPSRAWZrrkz:
10129 case VPSRAWri:
10130 case VPSRAWrm:
10131 case VPSRAWrr:
10132 return true;
10133 }
10134 return false;
10135}
10136
10137bool isVFMSUBADD231PH(unsigned Opcode) {
10138 switch (Opcode) {
10139 case VFMSUBADD231PHZ128m:
10140 case VFMSUBADD231PHZ128mb:
10141 case VFMSUBADD231PHZ128mbk:
10142 case VFMSUBADD231PHZ128mbkz:
10143 case VFMSUBADD231PHZ128mk:
10144 case VFMSUBADD231PHZ128mkz:
10145 case VFMSUBADD231PHZ128r:
10146 case VFMSUBADD231PHZ128rk:
10147 case VFMSUBADD231PHZ128rkz:
10148 case VFMSUBADD231PHZ256m:
10149 case VFMSUBADD231PHZ256mb:
10150 case VFMSUBADD231PHZ256mbk:
10151 case VFMSUBADD231PHZ256mbkz:
10152 case VFMSUBADD231PHZ256mk:
10153 case VFMSUBADD231PHZ256mkz:
10154 case VFMSUBADD231PHZ256r:
10155 case VFMSUBADD231PHZ256rk:
10156 case VFMSUBADD231PHZ256rkz:
10157 case VFMSUBADD231PHZm:
10158 case VFMSUBADD231PHZmb:
10159 case VFMSUBADD231PHZmbk:
10160 case VFMSUBADD231PHZmbkz:
10161 case VFMSUBADD231PHZmk:
10162 case VFMSUBADD231PHZmkz:
10163 case VFMSUBADD231PHZr:
10164 case VFMSUBADD231PHZrb:
10165 case VFMSUBADD231PHZrbk:
10166 case VFMSUBADD231PHZrbkz:
10167 case VFMSUBADD231PHZrk:
10168 case VFMSUBADD231PHZrkz:
10169 return true;
10170 }
10171 return false;
10172}
10173
10174bool isCVTDQ2PS(unsigned Opcode) {
10175 switch (Opcode) {
10176 case CVTDQ2PSrm:
10177 case CVTDQ2PSrr:
10178 return true;
10179 }
10180 return false;
10181}
10182
10183bool isFBLD(unsigned Opcode) {
10184 return Opcode == FBLDm;
10185}
10186
10187bool isLMSW(unsigned Opcode) {
10188 switch (Opcode) {
10189 case LMSW16m:
10190 case LMSW16r:
10191 return true;
10192 }
10193 return false;
10194}
10195
10196bool isVRNDSCALEPH(unsigned Opcode) {
10197 switch (Opcode) {
10198 case VRNDSCALEPHZ128rmbi:
10199 case VRNDSCALEPHZ128rmbik:
10200 case VRNDSCALEPHZ128rmbikz:
10201 case VRNDSCALEPHZ128rmi:
10202 case VRNDSCALEPHZ128rmik:
10203 case VRNDSCALEPHZ128rmikz:
10204 case VRNDSCALEPHZ128rri:
10205 case VRNDSCALEPHZ128rrik:
10206 case VRNDSCALEPHZ128rrikz:
10207 case VRNDSCALEPHZ256rmbi:
10208 case VRNDSCALEPHZ256rmbik:
10209 case VRNDSCALEPHZ256rmbikz:
10210 case VRNDSCALEPHZ256rmi:
10211 case VRNDSCALEPHZ256rmik:
10212 case VRNDSCALEPHZ256rmikz:
10213 case VRNDSCALEPHZ256rri:
10214 case VRNDSCALEPHZ256rrik:
10215 case VRNDSCALEPHZ256rrikz:
10216 case VRNDSCALEPHZrmbi:
10217 case VRNDSCALEPHZrmbik:
10218 case VRNDSCALEPHZrmbikz:
10219 case VRNDSCALEPHZrmi:
10220 case VRNDSCALEPHZrmik:
10221 case VRNDSCALEPHZrmikz:
10222 case VRNDSCALEPHZrri:
10223 case VRNDSCALEPHZrrib:
10224 case VRNDSCALEPHZrribk:
10225 case VRNDSCALEPHZrribkz:
10226 case VRNDSCALEPHZrrik:
10227 case VRNDSCALEPHZrrikz:
10228 return true;
10229 }
10230 return false;
10231}
10232
10233bool isMINSS(unsigned Opcode) {
10234 switch (Opcode) {
10235 case MINSSrm_Int:
10236 case MINSSrr_Int:
10237 return true;
10238 }
10239 return false;
10240}
10241
10242bool isWRMSR(unsigned Opcode) {
10243 return Opcode == WRMSR;
10244}
10245
10246bool isFSCALE(unsigned Opcode) {
10247 return Opcode == FSCALE;
10248}
10249
10250bool isVFNMADD213SH(unsigned Opcode) {
10251 switch (Opcode) {
10252 case VFNMADD213SHZm_Int:
10253 case VFNMADD213SHZmk_Int:
10254 case VFNMADD213SHZmkz_Int:
10255 case VFNMADD213SHZr_Int:
10256 case VFNMADD213SHZrb_Int:
10257 case VFNMADD213SHZrbk_Int:
10258 case VFNMADD213SHZrbkz_Int:
10259 case VFNMADD213SHZrk_Int:
10260 case VFNMADD213SHZrkz_Int:
10261 return true;
10262 }
10263 return false;
10264}
10265
10266bool isIMULZU(unsigned Opcode) {
10267 switch (Opcode) {
10268 case IMULZU16rmi:
10269 case IMULZU16rmi8:
10270 case IMULZU16rri:
10271 case IMULZU16rri8:
10272 case IMULZU32rmi:
10273 case IMULZU32rmi8:
10274 case IMULZU32rri:
10275 case IMULZU32rri8:
10276 case IMULZU64rmi32:
10277 case IMULZU64rmi8:
10278 case IMULZU64rri32:
10279 case IMULZU64rri8:
10280 return true;
10281 }
10282 return false;
10283}
10284
10285bool isVPHADDUBD(unsigned Opcode) {
10286 switch (Opcode) {
10287 case VPHADDUBDrm:
10288 case VPHADDUBDrr:
10289 return true;
10290 }
10291 return false;
10292}
10293
10294bool isRDSSPQ(unsigned Opcode) {
10295 return Opcode == RDSSPQ;
10296}
10297
10298bool isVCVTBF162IBS(unsigned Opcode) {
10299 switch (Opcode) {
10300 case VCVTBF162IBSZ128rm:
10301 case VCVTBF162IBSZ128rmb:
10302 case VCVTBF162IBSZ128rmbk:
10303 case VCVTBF162IBSZ128rmbkz:
10304 case VCVTBF162IBSZ128rmk:
10305 case VCVTBF162IBSZ128rmkz:
10306 case VCVTBF162IBSZ128rr:
10307 case VCVTBF162IBSZ128rrk:
10308 case VCVTBF162IBSZ128rrkz:
10309 case VCVTBF162IBSZ256rm:
10310 case VCVTBF162IBSZ256rmb:
10311 case VCVTBF162IBSZ256rmbk:
10312 case VCVTBF162IBSZ256rmbkz:
10313 case VCVTBF162IBSZ256rmk:
10314 case VCVTBF162IBSZ256rmkz:
10315 case VCVTBF162IBSZ256rr:
10316 case VCVTBF162IBSZ256rrk:
10317 case VCVTBF162IBSZ256rrkz:
10318 case VCVTBF162IBSZrm:
10319 case VCVTBF162IBSZrmb:
10320 case VCVTBF162IBSZrmbk:
10321 case VCVTBF162IBSZrmbkz:
10322 case VCVTBF162IBSZrmk:
10323 case VCVTBF162IBSZrmkz:
10324 case VCVTBF162IBSZrr:
10325 case VCVTBF162IBSZrrk:
10326 case VCVTBF162IBSZrrkz:
10327 return true;
10328 }
10329 return false;
10330}
10331
10332bool isLGDT(unsigned Opcode) {
10333 return Opcode == LGDT64m;
10334}
10335
10336bool isVPSHLDVD(unsigned Opcode) {
10337 switch (Opcode) {
10338 case VPSHLDVDZ128m:
10339 case VPSHLDVDZ128mb:
10340 case VPSHLDVDZ128mbk:
10341 case VPSHLDVDZ128mbkz:
10342 case VPSHLDVDZ128mk:
10343 case VPSHLDVDZ128mkz:
10344 case VPSHLDVDZ128r:
10345 case VPSHLDVDZ128rk:
10346 case VPSHLDVDZ128rkz:
10347 case VPSHLDVDZ256m:
10348 case VPSHLDVDZ256mb:
10349 case VPSHLDVDZ256mbk:
10350 case VPSHLDVDZ256mbkz:
10351 case VPSHLDVDZ256mk:
10352 case VPSHLDVDZ256mkz:
10353 case VPSHLDVDZ256r:
10354 case VPSHLDVDZ256rk:
10355 case VPSHLDVDZ256rkz:
10356 case VPSHLDVDZm:
10357 case VPSHLDVDZmb:
10358 case VPSHLDVDZmbk:
10359 case VPSHLDVDZmbkz:
10360 case VPSHLDVDZmk:
10361 case VPSHLDVDZmkz:
10362 case VPSHLDVDZr:
10363 case VPSHLDVDZrk:
10364 case VPSHLDVDZrkz:
10365 return true;
10366 }
10367 return false;
10368}
10369
10370bool isPFCMPGT(unsigned Opcode) {
10371 switch (Opcode) {
10372 case PFCMPGTrm:
10373 case PFCMPGTrr:
10374 return true;
10375 }
10376 return false;
10377}
10378
10379bool isJCXZ(unsigned Opcode) {
10380 return Opcode == JCXZ;
10381}
10382
10383bool isVPMOVZXBW(unsigned Opcode) {
10384 switch (Opcode) {
10385 case VPMOVZXBWYrm:
10386 case VPMOVZXBWYrr:
10387 case VPMOVZXBWZ128rm:
10388 case VPMOVZXBWZ128rmk:
10389 case VPMOVZXBWZ128rmkz:
10390 case VPMOVZXBWZ128rr:
10391 case VPMOVZXBWZ128rrk:
10392 case VPMOVZXBWZ128rrkz:
10393 case VPMOVZXBWZ256rm:
10394 case VPMOVZXBWZ256rmk:
10395 case VPMOVZXBWZ256rmkz:
10396 case VPMOVZXBWZ256rr:
10397 case VPMOVZXBWZ256rrk:
10398 case VPMOVZXBWZ256rrkz:
10399 case VPMOVZXBWZrm:
10400 case VPMOVZXBWZrmk:
10401 case VPMOVZXBWZrmkz:
10402 case VPMOVZXBWZrr:
10403 case VPMOVZXBWZrrk:
10404 case VPMOVZXBWZrrkz:
10405 case VPMOVZXBWrm:
10406 case VPMOVZXBWrr:
10407 return true;
10408 }
10409 return false;
10410}
10411
10412bool isVFMADDSUB231PD(unsigned Opcode) {
10413 switch (Opcode) {
10414 case VFMADDSUB231PDYm:
10415 case VFMADDSUB231PDYr:
10416 case VFMADDSUB231PDZ128m:
10417 case VFMADDSUB231PDZ128mb:
10418 case VFMADDSUB231PDZ128mbk:
10419 case VFMADDSUB231PDZ128mbkz:
10420 case VFMADDSUB231PDZ128mk:
10421 case VFMADDSUB231PDZ128mkz:
10422 case VFMADDSUB231PDZ128r:
10423 case VFMADDSUB231PDZ128rk:
10424 case VFMADDSUB231PDZ128rkz:
10425 case VFMADDSUB231PDZ256m:
10426 case VFMADDSUB231PDZ256mb:
10427 case VFMADDSUB231PDZ256mbk:
10428 case VFMADDSUB231PDZ256mbkz:
10429 case VFMADDSUB231PDZ256mk:
10430 case VFMADDSUB231PDZ256mkz:
10431 case VFMADDSUB231PDZ256r:
10432 case VFMADDSUB231PDZ256rk:
10433 case VFMADDSUB231PDZ256rkz:
10434 case VFMADDSUB231PDZm:
10435 case VFMADDSUB231PDZmb:
10436 case VFMADDSUB231PDZmbk:
10437 case VFMADDSUB231PDZmbkz:
10438 case VFMADDSUB231PDZmk:
10439 case VFMADDSUB231PDZmkz:
10440 case VFMADDSUB231PDZr:
10441 case VFMADDSUB231PDZrb:
10442 case VFMADDSUB231PDZrbk:
10443 case VFMADDSUB231PDZrbkz:
10444 case VFMADDSUB231PDZrk:
10445 case VFMADDSUB231PDZrkz:
10446 case VFMADDSUB231PDm:
10447 case VFMADDSUB231PDr:
10448 return true;
10449 }
10450 return false;
10451}
10452
10453bool isVBLENDMPD(unsigned Opcode) {
10454 switch (Opcode) {
10455 case VBLENDMPDZ128rm:
10456 case VBLENDMPDZ128rmb:
10457 case VBLENDMPDZ128rmbk:
10458 case VBLENDMPDZ128rmbkz:
10459 case VBLENDMPDZ128rmk:
10460 case VBLENDMPDZ128rmkz:
10461 case VBLENDMPDZ128rr:
10462 case VBLENDMPDZ128rrk:
10463 case VBLENDMPDZ128rrkz:
10464 case VBLENDMPDZ256rm:
10465 case VBLENDMPDZ256rmb:
10466 case VBLENDMPDZ256rmbk:
10467 case VBLENDMPDZ256rmbkz:
10468 case VBLENDMPDZ256rmk:
10469 case VBLENDMPDZ256rmkz:
10470 case VBLENDMPDZ256rr:
10471 case VBLENDMPDZ256rrk:
10472 case VBLENDMPDZ256rrkz:
10473 case VBLENDMPDZrm:
10474 case VBLENDMPDZrmb:
10475 case VBLENDMPDZrmbk:
10476 case VBLENDMPDZrmbkz:
10477 case VBLENDMPDZrmk:
10478 case VBLENDMPDZrmkz:
10479 case VBLENDMPDZrr:
10480 case VBLENDMPDZrrk:
10481 case VBLENDMPDZrrkz:
10482 return true;
10483 }
10484 return false;
10485}
10486
10487bool isHSUBPS(unsigned Opcode) {
10488 switch (Opcode) {
10489 case HSUBPSrm:
10490 case HSUBPSrr:
10491 return true;
10492 }
10493 return false;
10494}
10495
10496bool isPREFETCHIT0(unsigned Opcode) {
10497 return Opcode == PREFETCHIT0;
10498}
10499
10500bool isKTESTD(unsigned Opcode) {
10501 return Opcode == KTESTDkk;
10502}
10503
10504bool isVCVTNEOPH2PS(unsigned Opcode) {
10505 switch (Opcode) {
10506 case VCVTNEOPH2PSYrm:
10507 case VCVTNEOPH2PSrm:
10508 return true;
10509 }
10510 return false;
10511}
10512
10513bool isVBLENDVPD(unsigned Opcode) {
10514 switch (Opcode) {
10515 case VBLENDVPDYrmr:
10516 case VBLENDVPDYrrr:
10517 case VBLENDVPDrmr:
10518 case VBLENDVPDrrr:
10519 return true;
10520 }
10521 return false;
10522}
10523
10524bool isVCVTSS2USI(unsigned Opcode) {
10525 switch (Opcode) {
10526 case VCVTSS2USI64Zrm_Int:
10527 case VCVTSS2USI64Zrr_Int:
10528 case VCVTSS2USI64Zrrb_Int:
10529 case VCVTSS2USIZrm_Int:
10530 case VCVTSS2USIZrr_Int:
10531 case VCVTSS2USIZrrb_Int:
10532 return true;
10533 }
10534 return false;
10535}
10536
10537bool isVCVTTPS2DQS(unsigned Opcode) {
10538 switch (Opcode) {
10539 case VCVTTPS2DQSZ128rm:
10540 case VCVTTPS2DQSZ128rmb:
10541 case VCVTTPS2DQSZ128rmbk:
10542 case VCVTTPS2DQSZ128rmbkz:
10543 case VCVTTPS2DQSZ128rmk:
10544 case VCVTTPS2DQSZ128rmkz:
10545 case VCVTTPS2DQSZ128rr:
10546 case VCVTTPS2DQSZ128rrk:
10547 case VCVTTPS2DQSZ128rrkz:
10548 case VCVTTPS2DQSZ256rm:
10549 case VCVTTPS2DQSZ256rmb:
10550 case VCVTTPS2DQSZ256rmbk:
10551 case VCVTTPS2DQSZ256rmbkz:
10552 case VCVTTPS2DQSZ256rmk:
10553 case VCVTTPS2DQSZ256rmkz:
10554 case VCVTTPS2DQSZ256rr:
10555 case VCVTTPS2DQSZ256rrk:
10556 case VCVTTPS2DQSZ256rrkz:
10557 case VCVTTPS2DQSZrm:
10558 case VCVTTPS2DQSZrmb:
10559 case VCVTTPS2DQSZrmbk:
10560 case VCVTTPS2DQSZrmbkz:
10561 case VCVTTPS2DQSZrmk:
10562 case VCVTTPS2DQSZrmkz:
10563 case VCVTTPS2DQSZrr:
10564 case VCVTTPS2DQSZrrb:
10565 case VCVTTPS2DQSZrrbk:
10566 case VCVTTPS2DQSZrrbkz:
10567 case VCVTTPS2DQSZrrk:
10568 case VCVTTPS2DQSZrrkz:
10569 return true;
10570 }
10571 return false;
10572}
10573
10574bool isVPANDD(unsigned Opcode) {
10575 switch (Opcode) {
10576 case VPANDDZ128rm:
10577 case VPANDDZ128rmb:
10578 case VPANDDZ128rmbk:
10579 case VPANDDZ128rmbkz:
10580 case VPANDDZ128rmk:
10581 case VPANDDZ128rmkz:
10582 case VPANDDZ128rr:
10583 case VPANDDZ128rrk:
10584 case VPANDDZ128rrkz:
10585 case VPANDDZ256rm:
10586 case VPANDDZ256rmb:
10587 case VPANDDZ256rmbk:
10588 case VPANDDZ256rmbkz:
10589 case VPANDDZ256rmk:
10590 case VPANDDZ256rmkz:
10591 case VPANDDZ256rr:
10592 case VPANDDZ256rrk:
10593 case VPANDDZ256rrkz:
10594 case VPANDDZrm:
10595 case VPANDDZrmb:
10596 case VPANDDZrmbk:
10597 case VPANDDZrmbkz:
10598 case VPANDDZrmk:
10599 case VPANDDZrmkz:
10600 case VPANDDZrr:
10601 case VPANDDZrrk:
10602 case VPANDDZrrkz:
10603 return true;
10604 }
10605 return false;
10606}
10607
10608bool isPMINSW(unsigned Opcode) {
10609 switch (Opcode) {
10610 case MMX_PMINSWrm:
10611 case MMX_PMINSWrr:
10612 case PMINSWrm:
10613 case PMINSWrr:
10614 return true;
10615 }
10616 return false;
10617}
10618
10619bool isSTAC(unsigned Opcode) {
10620 return Opcode == STAC;
10621}
10622
10623bool isVFMSUB213PS(unsigned Opcode) {
10624 switch (Opcode) {
10625 case VFMSUB213PSYm:
10626 case VFMSUB213PSYr:
10627 case VFMSUB213PSZ128m:
10628 case VFMSUB213PSZ128mb:
10629 case VFMSUB213PSZ128mbk:
10630 case VFMSUB213PSZ128mbkz:
10631 case VFMSUB213PSZ128mk:
10632 case VFMSUB213PSZ128mkz:
10633 case VFMSUB213PSZ128r:
10634 case VFMSUB213PSZ128rk:
10635 case VFMSUB213PSZ128rkz:
10636 case VFMSUB213PSZ256m:
10637 case VFMSUB213PSZ256mb:
10638 case VFMSUB213PSZ256mbk:
10639 case VFMSUB213PSZ256mbkz:
10640 case VFMSUB213PSZ256mk:
10641 case VFMSUB213PSZ256mkz:
10642 case VFMSUB213PSZ256r:
10643 case VFMSUB213PSZ256rk:
10644 case VFMSUB213PSZ256rkz:
10645 case VFMSUB213PSZm:
10646 case VFMSUB213PSZmb:
10647 case VFMSUB213PSZmbk:
10648 case VFMSUB213PSZmbkz:
10649 case VFMSUB213PSZmk:
10650 case VFMSUB213PSZmkz:
10651 case VFMSUB213PSZr:
10652 case VFMSUB213PSZrb:
10653 case VFMSUB213PSZrbk:
10654 case VFMSUB213PSZrbkz:
10655 case VFMSUB213PSZrk:
10656 case VFMSUB213PSZrkz:
10657 case VFMSUB213PSm:
10658 case VFMSUB213PSr:
10659 return true;
10660 }
10661 return false;
10662}
10663
10664bool isPOPAL(unsigned Opcode) {
10665 return Opcode == POPA32;
10666}
10667
10668bool isVCVTPS2UQQ(unsigned Opcode) {
10669 switch (Opcode) {
10670 case VCVTPS2UQQZ128rm:
10671 case VCVTPS2UQQZ128rmb:
10672 case VCVTPS2UQQZ128rmbk:
10673 case VCVTPS2UQQZ128rmbkz:
10674 case VCVTPS2UQQZ128rmk:
10675 case VCVTPS2UQQZ128rmkz:
10676 case VCVTPS2UQQZ128rr:
10677 case VCVTPS2UQQZ128rrk:
10678 case VCVTPS2UQQZ128rrkz:
10679 case VCVTPS2UQQZ256rm:
10680 case VCVTPS2UQQZ256rmb:
10681 case VCVTPS2UQQZ256rmbk:
10682 case VCVTPS2UQQZ256rmbkz:
10683 case VCVTPS2UQQZ256rmk:
10684 case VCVTPS2UQQZ256rmkz:
10685 case VCVTPS2UQQZ256rr:
10686 case VCVTPS2UQQZ256rrk:
10687 case VCVTPS2UQQZ256rrkz:
10688 case VCVTPS2UQQZrm:
10689 case VCVTPS2UQQZrmb:
10690 case VCVTPS2UQQZrmbk:
10691 case VCVTPS2UQQZrmbkz:
10692 case VCVTPS2UQQZrmk:
10693 case VCVTPS2UQQZrmkz:
10694 case VCVTPS2UQQZrr:
10695 case VCVTPS2UQQZrrb:
10696 case VCVTPS2UQQZrrbk:
10697 case VCVTPS2UQQZrrbkz:
10698 case VCVTPS2UQQZrrk:
10699 case VCVTPS2UQQZrrkz:
10700 return true;
10701 }
10702 return false;
10703}
10704
10705bool isRDRAND(unsigned Opcode) {
10706 switch (Opcode) {
10707 case RDRAND16r:
10708 case RDRAND32r:
10709 case RDRAND64r:
10710 return true;
10711 }
10712 return false;
10713}
10714
10715bool isJCC(unsigned Opcode) {
10716 switch (Opcode) {
10717 case JCC_1:
10718 case JCC_2:
10719 case JCC_4:
10720 return true;
10721 }
10722 return false;
10723}
10724
10725bool isVPMINSQ(unsigned Opcode) {
10726 switch (Opcode) {
10727 case VPMINSQZ128rm:
10728 case VPMINSQZ128rmb:
10729 case VPMINSQZ128rmbk:
10730 case VPMINSQZ128rmbkz:
10731 case VPMINSQZ128rmk:
10732 case VPMINSQZ128rmkz:
10733 case VPMINSQZ128rr:
10734 case VPMINSQZ128rrk:
10735 case VPMINSQZ128rrkz:
10736 case VPMINSQZ256rm:
10737 case VPMINSQZ256rmb:
10738 case VPMINSQZ256rmbk:
10739 case VPMINSQZ256rmbkz:
10740 case VPMINSQZ256rmk:
10741 case VPMINSQZ256rmkz:
10742 case VPMINSQZ256rr:
10743 case VPMINSQZ256rrk:
10744 case VPMINSQZ256rrkz:
10745 case VPMINSQZrm:
10746 case VPMINSQZrmb:
10747 case VPMINSQZrmbk:
10748 case VPMINSQZrmbkz:
10749 case VPMINSQZrmk:
10750 case VPMINSQZrmkz:
10751 case VPMINSQZrr:
10752 case VPMINSQZrrk:
10753 case VPMINSQZrrkz:
10754 return true;
10755 }
10756 return false;
10757}
10758
10759bool isVADDSD(unsigned Opcode) {
10760 switch (Opcode) {
10761 case VADDSDZrm_Int:
10762 case VADDSDZrmk_Int:
10763 case VADDSDZrmkz_Int:
10764 case VADDSDZrr_Int:
10765 case VADDSDZrrb_Int:
10766 case VADDSDZrrbk_Int:
10767 case VADDSDZrrbkz_Int:
10768 case VADDSDZrrk_Int:
10769 case VADDSDZrrkz_Int:
10770 case VADDSDrm_Int:
10771 case VADDSDrr_Int:
10772 return true;
10773 }
10774 return false;
10775}
10776
10777bool isDPPS(unsigned Opcode) {
10778 switch (Opcode) {
10779 case DPPSrmi:
10780 case DPPSrri:
10781 return true;
10782 }
10783 return false;
10784}
10785
10786bool isPINSRQ(unsigned Opcode) {
10787 switch (Opcode) {
10788 case PINSRQrmi:
10789 case PINSRQrri:
10790 return true;
10791 }
10792 return false;
10793}
10794
10795bool isVUCOMISS(unsigned Opcode) {
10796 switch (Opcode) {
10797 case VUCOMISSZrm:
10798 case VUCOMISSZrr:
10799 case VUCOMISSZrrb:
10800 case VUCOMISSrm:
10801 case VUCOMISSrr:
10802 return true;
10803 }
10804 return false;
10805}
10806
10807bool isVPDPWSUD(unsigned Opcode) {
10808 switch (Opcode) {
10809 case VPDPWSUDYrm:
10810 case VPDPWSUDYrr:
10811 case VPDPWSUDZ128rm:
10812 case VPDPWSUDZ128rmb:
10813 case VPDPWSUDZ128rmbk:
10814 case VPDPWSUDZ128rmbkz:
10815 case VPDPWSUDZ128rmk:
10816 case VPDPWSUDZ128rmkz:
10817 case VPDPWSUDZ128rr:
10818 case VPDPWSUDZ128rrk:
10819 case VPDPWSUDZ128rrkz:
10820 case VPDPWSUDZ256rm:
10821 case VPDPWSUDZ256rmb:
10822 case VPDPWSUDZ256rmbk:
10823 case VPDPWSUDZ256rmbkz:
10824 case VPDPWSUDZ256rmk:
10825 case VPDPWSUDZ256rmkz:
10826 case VPDPWSUDZ256rr:
10827 case VPDPWSUDZ256rrk:
10828 case VPDPWSUDZ256rrkz:
10829 case VPDPWSUDZrm:
10830 case VPDPWSUDZrmb:
10831 case VPDPWSUDZrmbk:
10832 case VPDPWSUDZrmbkz:
10833 case VPDPWSUDZrmk:
10834 case VPDPWSUDZrmkz:
10835 case VPDPWSUDZrr:
10836 case VPDPWSUDZrrk:
10837 case VPDPWSUDZrrkz:
10838 case VPDPWSUDrm:
10839 case VPDPWSUDrr:
10840 return true;
10841 }
10842 return false;
10843}
10844
10845bool isKANDNW(unsigned Opcode) {
10846 return Opcode == KANDNWkk;
10847}
10848
10849bool isAOR(unsigned Opcode) {
10850 switch (Opcode) {
10851 case AOR32mr:
10852 case AOR32mr_EVEX:
10853 case AOR64mr:
10854 case AOR64mr_EVEX:
10855 return true;
10856 }
10857 return false;
10858}
10859
10860bool isPMAXUB(unsigned Opcode) {
10861 switch (Opcode) {
10862 case MMX_PMAXUBrm:
10863 case MMX_PMAXUBrr:
10864 case PMAXUBrm:
10865 case PMAXUBrr:
10866 return true;
10867 }
10868 return false;
10869}
10870
10871bool isANDNPD(unsigned Opcode) {
10872 switch (Opcode) {
10873 case ANDNPDrm:
10874 case ANDNPDrr:
10875 return true;
10876 }
10877 return false;
10878}
10879
10880bool isINVPCID(unsigned Opcode) {
10881 switch (Opcode) {
10882 case INVPCID32:
10883 case INVPCID64:
10884 case INVPCID64_EVEX:
10885 return true;
10886 }
10887 return false;
10888}
10889
10890bool isRDGSBASE(unsigned Opcode) {
10891 switch (Opcode) {
10892 case RDGSBASE:
10893 case RDGSBASE64:
10894 return true;
10895 }
10896 return false;
10897}
10898
10899bool isVPMOVSQD(unsigned Opcode) {
10900 switch (Opcode) {
10901 case VPMOVSQDZ128mr:
10902 case VPMOVSQDZ128mrk:
10903 case VPMOVSQDZ128rr:
10904 case VPMOVSQDZ128rrk:
10905 case VPMOVSQDZ128rrkz:
10906 case VPMOVSQDZ256mr:
10907 case VPMOVSQDZ256mrk:
10908 case VPMOVSQDZ256rr:
10909 case VPMOVSQDZ256rrk:
10910 case VPMOVSQDZ256rrkz:
10911 case VPMOVSQDZmr:
10912 case VPMOVSQDZmrk:
10913 case VPMOVSQDZrr:
10914 case VPMOVSQDZrrk:
10915 case VPMOVSQDZrrkz:
10916 return true;
10917 }
10918 return false;
10919}
10920
10921bool isBT(unsigned Opcode) {
10922 switch (Opcode) {
10923 case BT16mi8:
10924 case BT16mr:
10925 case BT16ri8:
10926 case BT16rr:
10927 case BT32mi8:
10928 case BT32mr:
10929 case BT32ri8:
10930 case BT32rr:
10931 case BT64mi8:
10932 case BT64mr:
10933 case BT64ri8:
10934 case BT64rr:
10935 return true;
10936 }
10937 return false;
10938}
10939
10940bool isVPROLVQ(unsigned Opcode) {
10941 switch (Opcode) {
10942 case VPROLVQZ128rm:
10943 case VPROLVQZ128rmb:
10944 case VPROLVQZ128rmbk:
10945 case VPROLVQZ128rmbkz:
10946 case VPROLVQZ128rmk:
10947 case VPROLVQZ128rmkz:
10948 case VPROLVQZ128rr:
10949 case VPROLVQZ128rrk:
10950 case VPROLVQZ128rrkz:
10951 case VPROLVQZ256rm:
10952 case VPROLVQZ256rmb:
10953 case VPROLVQZ256rmbk:
10954 case VPROLVQZ256rmbkz:
10955 case VPROLVQZ256rmk:
10956 case VPROLVQZ256rmkz:
10957 case VPROLVQZ256rr:
10958 case VPROLVQZ256rrk:
10959 case VPROLVQZ256rrkz:
10960 case VPROLVQZrm:
10961 case VPROLVQZrmb:
10962 case VPROLVQZrmbk:
10963 case VPROLVQZrmbkz:
10964 case VPROLVQZrmk:
10965 case VPROLVQZrmkz:
10966 case VPROLVQZrr:
10967 case VPROLVQZrrk:
10968 case VPROLVQZrrkz:
10969 return true;
10970 }
10971 return false;
10972}
10973
10974bool isVFMADDSUB132PD(unsigned Opcode) {
10975 switch (Opcode) {
10976 case VFMADDSUB132PDYm:
10977 case VFMADDSUB132PDYr:
10978 case VFMADDSUB132PDZ128m:
10979 case VFMADDSUB132PDZ128mb:
10980 case VFMADDSUB132PDZ128mbk:
10981 case VFMADDSUB132PDZ128mbkz:
10982 case VFMADDSUB132PDZ128mk:
10983 case VFMADDSUB132PDZ128mkz:
10984 case VFMADDSUB132PDZ128r:
10985 case VFMADDSUB132PDZ128rk:
10986 case VFMADDSUB132PDZ128rkz:
10987 case VFMADDSUB132PDZ256m:
10988 case VFMADDSUB132PDZ256mb:
10989 case VFMADDSUB132PDZ256mbk:
10990 case VFMADDSUB132PDZ256mbkz:
10991 case VFMADDSUB132PDZ256mk:
10992 case VFMADDSUB132PDZ256mkz:
10993 case VFMADDSUB132PDZ256r:
10994 case VFMADDSUB132PDZ256rk:
10995 case VFMADDSUB132PDZ256rkz:
10996 case VFMADDSUB132PDZm:
10997 case VFMADDSUB132PDZmb:
10998 case VFMADDSUB132PDZmbk:
10999 case VFMADDSUB132PDZmbkz:
11000 case VFMADDSUB132PDZmk:
11001 case VFMADDSUB132PDZmkz:
11002 case VFMADDSUB132PDZr:
11003 case VFMADDSUB132PDZrb:
11004 case VFMADDSUB132PDZrbk:
11005 case VFMADDSUB132PDZrbkz:
11006 case VFMADDSUB132PDZrk:
11007 case VFMADDSUB132PDZrkz:
11008 case VFMADDSUB132PDm:
11009 case VFMADDSUB132PDr:
11010 return true;
11011 }
11012 return false;
11013}
11014
11015bool isRORX(unsigned Opcode) {
11016 switch (Opcode) {
11017 case RORX32mi:
11018 case RORX32mi_EVEX:
11019 case RORX32ri:
11020 case RORX32ri_EVEX:
11021 case RORX64mi:
11022 case RORX64mi_EVEX:
11023 case RORX64ri:
11024 case RORX64ri_EVEX:
11025 return true;
11026 }
11027 return false;
11028}
11029
11030bool isPADDUSW(unsigned Opcode) {
11031 switch (Opcode) {
11032 case MMX_PADDUSWrm:
11033 case MMX_PADDUSWrr:
11034 case PADDUSWrm:
11035 case PADDUSWrr:
11036 return true;
11037 }
11038 return false;
11039}
11040
11041bool isPFNACC(unsigned Opcode) {
11042 switch (Opcode) {
11043 case PFNACCrm:
11044 case PFNACCrr:
11045 return true;
11046 }
11047 return false;
11048}
11049
11050bool isAND(unsigned Opcode) {
11051 switch (Opcode) {
11052 case AND16i16:
11053 case AND16mi:
11054 case AND16mi8:
11055 case AND16mi8_EVEX:
11056 case AND16mi8_ND:
11057 case AND16mi8_NF:
11058 case AND16mi8_NF_ND:
11059 case AND16mi_EVEX:
11060 case AND16mi_ND:
11061 case AND16mi_NF:
11062 case AND16mi_NF_ND:
11063 case AND16mr:
11064 case AND16mr_EVEX:
11065 case AND16mr_ND:
11066 case AND16mr_NF:
11067 case AND16mr_NF_ND:
11068 case AND16ri:
11069 case AND16ri8:
11070 case AND16ri8_EVEX:
11071 case AND16ri8_ND:
11072 case AND16ri8_NF:
11073 case AND16ri8_NF_ND:
11074 case AND16ri_EVEX:
11075 case AND16ri_ND:
11076 case AND16ri_NF:
11077 case AND16ri_NF_ND:
11078 case AND16rm:
11079 case AND16rm_EVEX:
11080 case AND16rm_ND:
11081 case AND16rm_NF:
11082 case AND16rm_NF_ND:
11083 case AND16rr:
11084 case AND16rr_EVEX:
11085 case AND16rr_EVEX_REV:
11086 case AND16rr_ND:
11087 case AND16rr_ND_REV:
11088 case AND16rr_NF:
11089 case AND16rr_NF_ND:
11090 case AND16rr_NF_ND_REV:
11091 case AND16rr_NF_REV:
11092 case AND16rr_REV:
11093 case AND32i32:
11094 case AND32mi:
11095 case AND32mi8:
11096 case AND32mi8_EVEX:
11097 case AND32mi8_ND:
11098 case AND32mi8_NF:
11099 case AND32mi8_NF_ND:
11100 case AND32mi_EVEX:
11101 case AND32mi_ND:
11102 case AND32mi_NF:
11103 case AND32mi_NF_ND:
11104 case AND32mr:
11105 case AND32mr_EVEX:
11106 case AND32mr_ND:
11107 case AND32mr_NF:
11108 case AND32mr_NF_ND:
11109 case AND32ri:
11110 case AND32ri8:
11111 case AND32ri8_EVEX:
11112 case AND32ri8_ND:
11113 case AND32ri8_NF:
11114 case AND32ri8_NF_ND:
11115 case AND32ri_EVEX:
11116 case AND32ri_ND:
11117 case AND32ri_NF:
11118 case AND32ri_NF_ND:
11119 case AND32rm:
11120 case AND32rm_EVEX:
11121 case AND32rm_ND:
11122 case AND32rm_NF:
11123 case AND32rm_NF_ND:
11124 case AND32rr:
11125 case AND32rr_EVEX:
11126 case AND32rr_EVEX_REV:
11127 case AND32rr_ND:
11128 case AND32rr_ND_REV:
11129 case AND32rr_NF:
11130 case AND32rr_NF_ND:
11131 case AND32rr_NF_ND_REV:
11132 case AND32rr_NF_REV:
11133 case AND32rr_REV:
11134 case AND64i32:
11135 case AND64mi32:
11136 case AND64mi32_EVEX:
11137 case AND64mi32_ND:
11138 case AND64mi32_NF:
11139 case AND64mi32_NF_ND:
11140 case AND64mi8:
11141 case AND64mi8_EVEX:
11142 case AND64mi8_ND:
11143 case AND64mi8_NF:
11144 case AND64mi8_NF_ND:
11145 case AND64mr:
11146 case AND64mr_EVEX:
11147 case AND64mr_ND:
11148 case AND64mr_NF:
11149 case AND64mr_NF_ND:
11150 case AND64ri32:
11151 case AND64ri32_EVEX:
11152 case AND64ri32_ND:
11153 case AND64ri32_NF:
11154 case AND64ri32_NF_ND:
11155 case AND64ri8:
11156 case AND64ri8_EVEX:
11157 case AND64ri8_ND:
11158 case AND64ri8_NF:
11159 case AND64ri8_NF_ND:
11160 case AND64rm:
11161 case AND64rm_EVEX:
11162 case AND64rm_ND:
11163 case AND64rm_NF:
11164 case AND64rm_NF_ND:
11165 case AND64rr:
11166 case AND64rr_EVEX:
11167 case AND64rr_EVEX_REV:
11168 case AND64rr_ND:
11169 case AND64rr_ND_REV:
11170 case AND64rr_NF:
11171 case AND64rr_NF_ND:
11172 case AND64rr_NF_ND_REV:
11173 case AND64rr_NF_REV:
11174 case AND64rr_REV:
11175 case AND8i8:
11176 case AND8mi:
11177 case AND8mi8:
11178 case AND8mi_EVEX:
11179 case AND8mi_ND:
11180 case AND8mi_NF:
11181 case AND8mi_NF_ND:
11182 case AND8mr:
11183 case AND8mr_EVEX:
11184 case AND8mr_ND:
11185 case AND8mr_NF:
11186 case AND8mr_NF_ND:
11187 case AND8ri:
11188 case AND8ri8:
11189 case AND8ri_EVEX:
11190 case AND8ri_ND:
11191 case AND8ri_NF:
11192 case AND8ri_NF_ND:
11193 case AND8rm:
11194 case AND8rm_EVEX:
11195 case AND8rm_ND:
11196 case AND8rm_NF:
11197 case AND8rm_NF_ND:
11198 case AND8rr:
11199 case AND8rr_EVEX:
11200 case AND8rr_EVEX_REV:
11201 case AND8rr_ND:
11202 case AND8rr_ND_REV:
11203 case AND8rr_NF:
11204 case AND8rr_NF_ND:
11205 case AND8rr_NF_ND_REV:
11206 case AND8rr_NF_REV:
11207 case AND8rr_REV:
11208 return true;
11209 }
11210 return false;
11211}
11212
11213bool isPSLLQ(unsigned Opcode) {
11214 switch (Opcode) {
11215 case MMX_PSLLQri:
11216 case MMX_PSLLQrm:
11217 case MMX_PSLLQrr:
11218 case PSLLQri:
11219 case PSLLQrm:
11220 case PSLLQrr:
11221 return true;
11222 }
11223 return false;
11224}
11225
11226bool isVFMSUB132PH(unsigned Opcode) {
11227 switch (Opcode) {
11228 case VFMSUB132PHZ128m:
11229 case VFMSUB132PHZ128mb:
11230 case VFMSUB132PHZ128mbk:
11231 case VFMSUB132PHZ128mbkz:
11232 case VFMSUB132PHZ128mk:
11233 case VFMSUB132PHZ128mkz:
11234 case VFMSUB132PHZ128r:
11235 case VFMSUB132PHZ128rk:
11236 case VFMSUB132PHZ128rkz:
11237 case VFMSUB132PHZ256m:
11238 case VFMSUB132PHZ256mb:
11239 case VFMSUB132PHZ256mbk:
11240 case VFMSUB132PHZ256mbkz:
11241 case VFMSUB132PHZ256mk:
11242 case VFMSUB132PHZ256mkz:
11243 case VFMSUB132PHZ256r:
11244 case VFMSUB132PHZ256rk:
11245 case VFMSUB132PHZ256rkz:
11246 case VFMSUB132PHZm:
11247 case VFMSUB132PHZmb:
11248 case VFMSUB132PHZmbk:
11249 case VFMSUB132PHZmbkz:
11250 case VFMSUB132PHZmk:
11251 case VFMSUB132PHZmkz:
11252 case VFMSUB132PHZr:
11253 case VFMSUB132PHZrb:
11254 case VFMSUB132PHZrbk:
11255 case VFMSUB132PHZrbkz:
11256 case VFMSUB132PHZrk:
11257 case VFMSUB132PHZrkz:
11258 return true;
11259 }
11260 return false;
11261}
11262
11263bool isXSAVE(unsigned Opcode) {
11264 return Opcode == XSAVE;
11265}
11266
11267bool isKNOTQ(unsigned Opcode) {
11268 return Opcode == KNOTQkk;
11269}
11270
11271bool isXTEST(unsigned Opcode) {
11272 return Opcode == XTEST;
11273}
11274
11275bool isVINSERTPS(unsigned Opcode) {
11276 switch (Opcode) {
11277 case VINSERTPSZrmi:
11278 case VINSERTPSZrri:
11279 case VINSERTPSrmi:
11280 case VINSERTPSrri:
11281 return true;
11282 }
11283 return false;
11284}
11285
11286bool isXSAVEOPT(unsigned Opcode) {
11287 return Opcode == XSAVEOPT;
11288}
11289
11290bool isLDS(unsigned Opcode) {
11291 switch (Opcode) {
11292 case LDS16rm:
11293 case LDS32rm:
11294 return true;
11295 }
11296 return false;
11297}
11298
11299bool isVFMADDSUB213PD(unsigned Opcode) {
11300 switch (Opcode) {
11301 case VFMADDSUB213PDYm:
11302 case VFMADDSUB213PDYr:
11303 case VFMADDSUB213PDZ128m:
11304 case VFMADDSUB213PDZ128mb:
11305 case VFMADDSUB213PDZ128mbk:
11306 case VFMADDSUB213PDZ128mbkz:
11307 case VFMADDSUB213PDZ128mk:
11308 case VFMADDSUB213PDZ128mkz:
11309 case VFMADDSUB213PDZ128r:
11310 case VFMADDSUB213PDZ128rk:
11311 case VFMADDSUB213PDZ128rkz:
11312 case VFMADDSUB213PDZ256m:
11313 case VFMADDSUB213PDZ256mb:
11314 case VFMADDSUB213PDZ256mbk:
11315 case VFMADDSUB213PDZ256mbkz:
11316 case VFMADDSUB213PDZ256mk:
11317 case VFMADDSUB213PDZ256mkz:
11318 case VFMADDSUB213PDZ256r:
11319 case VFMADDSUB213PDZ256rk:
11320 case VFMADDSUB213PDZ256rkz:
11321 case VFMADDSUB213PDZm:
11322 case VFMADDSUB213PDZmb:
11323 case VFMADDSUB213PDZmbk:
11324 case VFMADDSUB213PDZmbkz:
11325 case VFMADDSUB213PDZmk:
11326 case VFMADDSUB213PDZmkz:
11327 case VFMADDSUB213PDZr:
11328 case VFMADDSUB213PDZrb:
11329 case VFMADDSUB213PDZrbk:
11330 case VFMADDSUB213PDZrbkz:
11331 case VFMADDSUB213PDZrk:
11332 case VFMADDSUB213PDZrkz:
11333 case VFMADDSUB213PDm:
11334 case VFMADDSUB213PDr:
11335 return true;
11336 }
11337 return false;
11338}
11339
11340bool isVINSERTF32X4(unsigned Opcode) {
11341 switch (Opcode) {
11342 case VINSERTF32X4Z256rmi:
11343 case VINSERTF32X4Z256rmik:
11344 case VINSERTF32X4Z256rmikz:
11345 case VINSERTF32X4Z256rri:
11346 case VINSERTF32X4Z256rrik:
11347 case VINSERTF32X4Z256rrikz:
11348 case VINSERTF32X4Zrmi:
11349 case VINSERTF32X4Zrmik:
11350 case VINSERTF32X4Zrmikz:
11351 case VINSERTF32X4Zrri:
11352 case VINSERTF32X4Zrrik:
11353 case VINSERTF32X4Zrrikz:
11354 return true;
11355 }
11356 return false;
11357}
11358
11359bool isVRSQRTPS(unsigned Opcode) {
11360 switch (Opcode) {
11361 case VRSQRTPSYm:
11362 case VRSQRTPSYr:
11363 case VRSQRTPSm:
11364 case VRSQRTPSr:
11365 return true;
11366 }
11367 return false;
11368}
11369
11370bool isVSUBPH(unsigned Opcode) {
11371 switch (Opcode) {
11372 case VSUBPHZ128rm:
11373 case VSUBPHZ128rmb:
11374 case VSUBPHZ128rmbk:
11375 case VSUBPHZ128rmbkz:
11376 case VSUBPHZ128rmk:
11377 case VSUBPHZ128rmkz:
11378 case VSUBPHZ128rr:
11379 case VSUBPHZ128rrk:
11380 case VSUBPHZ128rrkz:
11381 case VSUBPHZ256rm:
11382 case VSUBPHZ256rmb:
11383 case VSUBPHZ256rmbk:
11384 case VSUBPHZ256rmbkz:
11385 case VSUBPHZ256rmk:
11386 case VSUBPHZ256rmkz:
11387 case VSUBPHZ256rr:
11388 case VSUBPHZ256rrk:
11389 case VSUBPHZ256rrkz:
11390 case VSUBPHZrm:
11391 case VSUBPHZrmb:
11392 case VSUBPHZrmbk:
11393 case VSUBPHZrmbkz:
11394 case VSUBPHZrmk:
11395 case VSUBPHZrmkz:
11396 case VSUBPHZrr:
11397 case VSUBPHZrrb:
11398 case VSUBPHZrrbk:
11399 case VSUBPHZrrbkz:
11400 case VSUBPHZrrk:
11401 case VSUBPHZrrkz:
11402 return true;
11403 }
11404 return false;
11405}
11406
11407bool isPMOVSXBW(unsigned Opcode) {
11408 switch (Opcode) {
11409 case PMOVSXBWrm:
11410 case PMOVSXBWrr:
11411 return true;
11412 }
11413 return false;
11414}
11415
11416bool isVPSRLDQ(unsigned Opcode) {
11417 switch (Opcode) {
11418 case VPSRLDQYri:
11419 case VPSRLDQZ128mi:
11420 case VPSRLDQZ128ri:
11421 case VPSRLDQZ256mi:
11422 case VPSRLDQZ256ri:
11423 case VPSRLDQZmi:
11424 case VPSRLDQZri:
11425 case VPSRLDQri:
11426 return true;
11427 }
11428 return false;
11429}
11430
11431bool isADC(unsigned Opcode) {
11432 switch (Opcode) {
11433 case ADC16i16:
11434 case ADC16mi:
11435 case ADC16mi8:
11436 case ADC16mi8_EVEX:
11437 case ADC16mi8_ND:
11438 case ADC16mi_EVEX:
11439 case ADC16mi_ND:
11440 case ADC16mr:
11441 case ADC16mr_EVEX:
11442 case ADC16mr_ND:
11443 case ADC16ri:
11444 case ADC16ri8:
11445 case ADC16ri8_EVEX:
11446 case ADC16ri8_ND:
11447 case ADC16ri_EVEX:
11448 case ADC16ri_ND:
11449 case ADC16rm:
11450 case ADC16rm_EVEX:
11451 case ADC16rm_ND:
11452 case ADC16rr:
11453 case ADC16rr_EVEX:
11454 case ADC16rr_EVEX_REV:
11455 case ADC16rr_ND:
11456 case ADC16rr_ND_REV:
11457 case ADC16rr_REV:
11458 case ADC32i32:
11459 case ADC32mi:
11460 case ADC32mi8:
11461 case ADC32mi8_EVEX:
11462 case ADC32mi8_ND:
11463 case ADC32mi_EVEX:
11464 case ADC32mi_ND:
11465 case ADC32mr:
11466 case ADC32mr_EVEX:
11467 case ADC32mr_ND:
11468 case ADC32ri:
11469 case ADC32ri8:
11470 case ADC32ri8_EVEX:
11471 case ADC32ri8_ND:
11472 case ADC32ri_EVEX:
11473 case ADC32ri_ND:
11474 case ADC32rm:
11475 case ADC32rm_EVEX:
11476 case ADC32rm_ND:
11477 case ADC32rr:
11478 case ADC32rr_EVEX:
11479 case ADC32rr_EVEX_REV:
11480 case ADC32rr_ND:
11481 case ADC32rr_ND_REV:
11482 case ADC32rr_REV:
11483 case ADC64i32:
11484 case ADC64mi32:
11485 case ADC64mi32_EVEX:
11486 case ADC64mi32_ND:
11487 case ADC64mi8:
11488 case ADC64mi8_EVEX:
11489 case ADC64mi8_ND:
11490 case ADC64mr:
11491 case ADC64mr_EVEX:
11492 case ADC64mr_ND:
11493 case ADC64ri32:
11494 case ADC64ri32_EVEX:
11495 case ADC64ri32_ND:
11496 case ADC64ri8:
11497 case ADC64ri8_EVEX:
11498 case ADC64ri8_ND:
11499 case ADC64rm:
11500 case ADC64rm_EVEX:
11501 case ADC64rm_ND:
11502 case ADC64rr:
11503 case ADC64rr_EVEX:
11504 case ADC64rr_EVEX_REV:
11505 case ADC64rr_ND:
11506 case ADC64rr_ND_REV:
11507 case ADC64rr_REV:
11508 case ADC8i8:
11509 case ADC8mi:
11510 case ADC8mi8:
11511 case ADC8mi_EVEX:
11512 case ADC8mi_ND:
11513 case ADC8mr:
11514 case ADC8mr_EVEX:
11515 case ADC8mr_ND:
11516 case ADC8ri:
11517 case ADC8ri8:
11518 case ADC8ri_EVEX:
11519 case ADC8ri_ND:
11520 case ADC8rm:
11521 case ADC8rm_EVEX:
11522 case ADC8rm_ND:
11523 case ADC8rr:
11524 case ADC8rr_EVEX:
11525 case ADC8rr_EVEX_REV:
11526 case ADC8rr_ND:
11527 case ADC8rr_ND_REV:
11528 case ADC8rr_REV:
11529 return true;
11530 }
11531 return false;
11532}
11533
11534bool isPHADDD(unsigned Opcode) {
11535 switch (Opcode) {
11536 case MMX_PHADDDrm:
11537 case MMX_PHADDDrr:
11538 case PHADDDrm:
11539 case PHADDDrr:
11540 return true;
11541 }
11542 return false;
11543}
11544
11545bool isVDPPHPS(unsigned Opcode) {
11546 switch (Opcode) {
11547 case VDPPHPSZ128m:
11548 case VDPPHPSZ128mb:
11549 case VDPPHPSZ128mbk:
11550 case VDPPHPSZ128mbkz:
11551 case VDPPHPSZ128mk:
11552 case VDPPHPSZ128mkz:
11553 case VDPPHPSZ128r:
11554 case VDPPHPSZ128rk:
11555 case VDPPHPSZ128rkz:
11556 case VDPPHPSZ256m:
11557 case VDPPHPSZ256mb:
11558 case VDPPHPSZ256mbk:
11559 case VDPPHPSZ256mbkz:
11560 case VDPPHPSZ256mk:
11561 case VDPPHPSZ256mkz:
11562 case VDPPHPSZ256r:
11563 case VDPPHPSZ256rk:
11564 case VDPPHPSZ256rkz:
11565 case VDPPHPSZm:
11566 case VDPPHPSZmb:
11567 case VDPPHPSZmbk:
11568 case VDPPHPSZmbkz:
11569 case VDPPHPSZmk:
11570 case VDPPHPSZmkz:
11571 case VDPPHPSZr:
11572 case VDPPHPSZrk:
11573 case VDPPHPSZrkz:
11574 return true;
11575 }
11576 return false;
11577}
11578
11579bool isVMINPH(unsigned Opcode) {
11580 switch (Opcode) {
11581 case VMINPHZ128rm:
11582 case VMINPHZ128rmb:
11583 case VMINPHZ128rmbk:
11584 case VMINPHZ128rmbkz:
11585 case VMINPHZ128rmk:
11586 case VMINPHZ128rmkz:
11587 case VMINPHZ128rr:
11588 case VMINPHZ128rrk:
11589 case VMINPHZ128rrkz:
11590 case VMINPHZ256rm:
11591 case VMINPHZ256rmb:
11592 case VMINPHZ256rmbk:
11593 case VMINPHZ256rmbkz:
11594 case VMINPHZ256rmk:
11595 case VMINPHZ256rmkz:
11596 case VMINPHZ256rr:
11597 case VMINPHZ256rrk:
11598 case VMINPHZ256rrkz:
11599 case VMINPHZrm:
11600 case VMINPHZrmb:
11601 case VMINPHZrmbk:
11602 case VMINPHZrmbkz:
11603 case VMINPHZrmk:
11604 case VMINPHZrmkz:
11605 case VMINPHZrr:
11606 case VMINPHZrrb:
11607 case VMINPHZrrbk:
11608 case VMINPHZrrbkz:
11609 case VMINPHZrrk:
11610 case VMINPHZrrkz:
11611 return true;
11612 }
11613 return false;
11614}
11615
11616bool isVMINSD(unsigned Opcode) {
11617 switch (Opcode) {
11618 case VMINSDZrm_Int:
11619 case VMINSDZrmk_Int:
11620 case VMINSDZrmkz_Int:
11621 case VMINSDZrr_Int:
11622 case VMINSDZrrb_Int:
11623 case VMINSDZrrbk_Int:
11624 case VMINSDZrrbkz_Int:
11625 case VMINSDZrrk_Int:
11626 case VMINSDZrrkz_Int:
11627 case VMINSDrm_Int:
11628 case VMINSDrr_Int:
11629 return true;
11630 }
11631 return false;
11632}
11633
11634bool isVROUNDPD(unsigned Opcode) {
11635 switch (Opcode) {
11636 case VROUNDPDYmi:
11637 case VROUNDPDYri:
11638 case VROUNDPDmi:
11639 case VROUNDPDri:
11640 return true;
11641 }
11642 return false;
11643}
11644
11645bool isVFCMADDCPH(unsigned Opcode) {
11646 switch (Opcode) {
11647 case VFCMADDCPHZ128m:
11648 case VFCMADDCPHZ128mb:
11649 case VFCMADDCPHZ128mbk:
11650 case VFCMADDCPHZ128mbkz:
11651 case VFCMADDCPHZ128mk:
11652 case VFCMADDCPHZ128mkz:
11653 case VFCMADDCPHZ128r:
11654 case VFCMADDCPHZ128rk:
11655 case VFCMADDCPHZ128rkz:
11656 case VFCMADDCPHZ256m:
11657 case VFCMADDCPHZ256mb:
11658 case VFCMADDCPHZ256mbk:
11659 case VFCMADDCPHZ256mbkz:
11660 case VFCMADDCPHZ256mk:
11661 case VFCMADDCPHZ256mkz:
11662 case VFCMADDCPHZ256r:
11663 case VFCMADDCPHZ256rk:
11664 case VFCMADDCPHZ256rkz:
11665 case VFCMADDCPHZm:
11666 case VFCMADDCPHZmb:
11667 case VFCMADDCPHZmbk:
11668 case VFCMADDCPHZmbkz:
11669 case VFCMADDCPHZmk:
11670 case VFCMADDCPHZmkz:
11671 case VFCMADDCPHZr:
11672 case VFCMADDCPHZrb:
11673 case VFCMADDCPHZrbk:
11674 case VFCMADDCPHZrbkz:
11675 case VFCMADDCPHZrk:
11676 case VFCMADDCPHZrkz:
11677 return true;
11678 }
11679 return false;
11680}
11681
11682bool isINCSSPQ(unsigned Opcode) {
11683 return Opcode == INCSSPQ;
11684}
11685
11686bool isVPUNPCKLDQ(unsigned Opcode) {
11687 switch (Opcode) {
11688 case VPUNPCKLDQYrm:
11689 case VPUNPCKLDQYrr:
11690 case VPUNPCKLDQZ128rm:
11691 case VPUNPCKLDQZ128rmb:
11692 case VPUNPCKLDQZ128rmbk:
11693 case VPUNPCKLDQZ128rmbkz:
11694 case VPUNPCKLDQZ128rmk:
11695 case VPUNPCKLDQZ128rmkz:
11696 case VPUNPCKLDQZ128rr:
11697 case VPUNPCKLDQZ128rrk:
11698 case VPUNPCKLDQZ128rrkz:
11699 case VPUNPCKLDQZ256rm:
11700 case VPUNPCKLDQZ256rmb:
11701 case VPUNPCKLDQZ256rmbk:
11702 case VPUNPCKLDQZ256rmbkz:
11703 case VPUNPCKLDQZ256rmk:
11704 case VPUNPCKLDQZ256rmkz:
11705 case VPUNPCKLDQZ256rr:
11706 case VPUNPCKLDQZ256rrk:
11707 case VPUNPCKLDQZ256rrkz:
11708 case VPUNPCKLDQZrm:
11709 case VPUNPCKLDQZrmb:
11710 case VPUNPCKLDQZrmbk:
11711 case VPUNPCKLDQZrmbkz:
11712 case VPUNPCKLDQZrmk:
11713 case VPUNPCKLDQZrmkz:
11714 case VPUNPCKLDQZrr:
11715 case VPUNPCKLDQZrrk:
11716 case VPUNPCKLDQZrrkz:
11717 case VPUNPCKLDQrm:
11718 case VPUNPCKLDQrr:
11719 return true;
11720 }
11721 return false;
11722}
11723
11724bool isVMINSH(unsigned Opcode) {
11725 switch (Opcode) {
11726 case VMINSHZrm_Int:
11727 case VMINSHZrmk_Int:
11728 case VMINSHZrmkz_Int:
11729 case VMINSHZrr_Int:
11730 case VMINSHZrrb_Int:
11731 case VMINSHZrrbk_Int:
11732 case VMINSHZrrbkz_Int:
11733 case VMINSHZrrk_Int:
11734 case VMINSHZrrkz_Int:
11735 return true;
11736 }
11737 return false;
11738}
11739
11740bool isINSERTQ(unsigned Opcode) {
11741 switch (Opcode) {
11742 case INSERTQ:
11743 case INSERTQI:
11744 return true;
11745 }
11746 return false;
11747}
11748
11749bool isBLCI(unsigned Opcode) {
11750 switch (Opcode) {
11751 case BLCI32rm:
11752 case BLCI32rr:
11753 case BLCI64rm:
11754 case BLCI64rr:
11755 return true;
11756 }
11757 return false;
11758}
11759
11760bool isHLT(unsigned Opcode) {
11761 return Opcode == HLT;
11762}
11763
11764bool isVPCOMUW(unsigned Opcode) {
11765 switch (Opcode) {
11766 case VPCOMUWmi:
11767 case VPCOMUWri:
11768 return true;
11769 }
11770 return false;
11771}
11772
11773bool isVPMOVSXDQ(unsigned Opcode) {
11774 switch (Opcode) {
11775 case VPMOVSXDQYrm:
11776 case VPMOVSXDQYrr:
11777 case VPMOVSXDQZ128rm:
11778 case VPMOVSXDQZ128rmk:
11779 case VPMOVSXDQZ128rmkz:
11780 case VPMOVSXDQZ128rr:
11781 case VPMOVSXDQZ128rrk:
11782 case VPMOVSXDQZ128rrkz:
11783 case VPMOVSXDQZ256rm:
11784 case VPMOVSXDQZ256rmk:
11785 case VPMOVSXDQZ256rmkz:
11786 case VPMOVSXDQZ256rr:
11787 case VPMOVSXDQZ256rrk:
11788 case VPMOVSXDQZ256rrkz:
11789 case VPMOVSXDQZrm:
11790 case VPMOVSXDQZrmk:
11791 case VPMOVSXDQZrmkz:
11792 case VPMOVSXDQZrr:
11793 case VPMOVSXDQZrrk:
11794 case VPMOVSXDQZrrkz:
11795 case VPMOVSXDQrm:
11796 case VPMOVSXDQrr:
11797 return true;
11798 }
11799 return false;
11800}
11801
11802bool isVFNMSUB231PS(unsigned Opcode) {
11803 switch (Opcode) {
11804 case VFNMSUB231PSYm:
11805 case VFNMSUB231PSYr:
11806 case VFNMSUB231PSZ128m:
11807 case VFNMSUB231PSZ128mb:
11808 case VFNMSUB231PSZ128mbk:
11809 case VFNMSUB231PSZ128mbkz:
11810 case VFNMSUB231PSZ128mk:
11811 case VFNMSUB231PSZ128mkz:
11812 case VFNMSUB231PSZ128r:
11813 case VFNMSUB231PSZ128rk:
11814 case VFNMSUB231PSZ128rkz:
11815 case VFNMSUB231PSZ256m:
11816 case VFNMSUB231PSZ256mb:
11817 case VFNMSUB231PSZ256mbk:
11818 case VFNMSUB231PSZ256mbkz:
11819 case VFNMSUB231PSZ256mk:
11820 case VFNMSUB231PSZ256mkz:
11821 case VFNMSUB231PSZ256r:
11822 case VFNMSUB231PSZ256rk:
11823 case VFNMSUB231PSZ256rkz:
11824 case VFNMSUB231PSZm:
11825 case VFNMSUB231PSZmb:
11826 case VFNMSUB231PSZmbk:
11827 case VFNMSUB231PSZmbkz:
11828 case VFNMSUB231PSZmk:
11829 case VFNMSUB231PSZmkz:
11830 case VFNMSUB231PSZr:
11831 case VFNMSUB231PSZrb:
11832 case VFNMSUB231PSZrbk:
11833 case VFNMSUB231PSZrbkz:
11834 case VFNMSUB231PSZrk:
11835 case VFNMSUB231PSZrkz:
11836 case VFNMSUB231PSm:
11837 case VFNMSUB231PSr:
11838 return true;
11839 }
11840 return false;
11841}
11842
11843bool isVFNMSUB213SH(unsigned Opcode) {
11844 switch (Opcode) {
11845 case VFNMSUB213SHZm_Int:
11846 case VFNMSUB213SHZmk_Int:
11847 case VFNMSUB213SHZmkz_Int:
11848 case VFNMSUB213SHZr_Int:
11849 case VFNMSUB213SHZrb_Int:
11850 case VFNMSUB213SHZrbk_Int:
11851 case VFNMSUB213SHZrbkz_Int:
11852 case VFNMSUB213SHZrk_Int:
11853 case VFNMSUB213SHZrkz_Int:
11854 return true;
11855 }
11856 return false;
11857}
11858
11859bool isVCVTTPD2UQQ(unsigned Opcode) {
11860 switch (Opcode) {
11861 case VCVTTPD2UQQZ128rm:
11862 case VCVTTPD2UQQZ128rmb:
11863 case VCVTTPD2UQQZ128rmbk:
11864 case VCVTTPD2UQQZ128rmbkz:
11865 case VCVTTPD2UQQZ128rmk:
11866 case VCVTTPD2UQQZ128rmkz:
11867 case VCVTTPD2UQQZ128rr:
11868 case VCVTTPD2UQQZ128rrk:
11869 case VCVTTPD2UQQZ128rrkz:
11870 case VCVTTPD2UQQZ256rm:
11871 case VCVTTPD2UQQZ256rmb:
11872 case VCVTTPD2UQQZ256rmbk:
11873 case VCVTTPD2UQQZ256rmbkz:
11874 case VCVTTPD2UQQZ256rmk:
11875 case VCVTTPD2UQQZ256rmkz:
11876 case VCVTTPD2UQQZ256rr:
11877 case VCVTTPD2UQQZ256rrk:
11878 case VCVTTPD2UQQZ256rrkz:
11879 case VCVTTPD2UQQZrm:
11880 case VCVTTPD2UQQZrmb:
11881 case VCVTTPD2UQQZrmbk:
11882 case VCVTTPD2UQQZrmbkz:
11883 case VCVTTPD2UQQZrmk:
11884 case VCVTTPD2UQQZrmkz:
11885 case VCVTTPD2UQQZrr:
11886 case VCVTTPD2UQQZrrb:
11887 case VCVTTPD2UQQZrrbk:
11888 case VCVTTPD2UQQZrrbkz:
11889 case VCVTTPD2UQQZrrk:
11890 case VCVTTPD2UQQZrrkz:
11891 return true;
11892 }
11893 return false;
11894}
11895
11896bool isSQRTSS(unsigned Opcode) {
11897 switch (Opcode) {
11898 case SQRTSSm_Int:
11899 case SQRTSSr_Int:
11900 return true;
11901 }
11902 return false;
11903}
11904
11905bool isIMUL(unsigned Opcode) {
11906 switch (Opcode) {
11907 case IMUL16m:
11908 case IMUL16m_EVEX:
11909 case IMUL16m_NF:
11910 case IMUL16r:
11911 case IMUL16r_EVEX:
11912 case IMUL16r_NF:
11913 case IMUL16rm:
11914 case IMUL16rm_EVEX:
11915 case IMUL16rm_ND:
11916 case IMUL16rm_NF:
11917 case IMUL16rm_NF_ND:
11918 case IMUL16rmi:
11919 case IMUL16rmi8:
11920 case IMUL16rmi8_EVEX:
11921 case IMUL16rmi8_NF:
11922 case IMUL16rmi_EVEX:
11923 case IMUL16rmi_NF:
11924 case IMUL16rr:
11925 case IMUL16rr_EVEX:
11926 case IMUL16rr_ND:
11927 case IMUL16rr_NF:
11928 case IMUL16rr_NF_ND:
11929 case IMUL16rri:
11930 case IMUL16rri8:
11931 case IMUL16rri8_EVEX:
11932 case IMUL16rri8_NF:
11933 case IMUL16rri_EVEX:
11934 case IMUL16rri_NF:
11935 case IMUL32m:
11936 case IMUL32m_EVEX:
11937 case IMUL32m_NF:
11938 case IMUL32r:
11939 case IMUL32r_EVEX:
11940 case IMUL32r_NF:
11941 case IMUL32rm:
11942 case IMUL32rm_EVEX:
11943 case IMUL32rm_ND:
11944 case IMUL32rm_NF:
11945 case IMUL32rm_NF_ND:
11946 case IMUL32rmi:
11947 case IMUL32rmi8:
11948 case IMUL32rmi8_EVEX:
11949 case IMUL32rmi8_NF:
11950 case IMUL32rmi_EVEX:
11951 case IMUL32rmi_NF:
11952 case IMUL32rr:
11953 case IMUL32rr_EVEX:
11954 case IMUL32rr_ND:
11955 case IMUL32rr_NF:
11956 case IMUL32rr_NF_ND:
11957 case IMUL32rri:
11958 case IMUL32rri8:
11959 case IMUL32rri8_EVEX:
11960 case IMUL32rri8_NF:
11961 case IMUL32rri_EVEX:
11962 case IMUL32rri_NF:
11963 case IMUL64m:
11964 case IMUL64m_EVEX:
11965 case IMUL64m_NF:
11966 case IMUL64r:
11967 case IMUL64r_EVEX:
11968 case IMUL64r_NF:
11969 case IMUL64rm:
11970 case IMUL64rm_EVEX:
11971 case IMUL64rm_ND:
11972 case IMUL64rm_NF:
11973 case IMUL64rm_NF_ND:
11974 case IMUL64rmi32:
11975 case IMUL64rmi32_EVEX:
11976 case IMUL64rmi32_NF:
11977 case IMUL64rmi8:
11978 case IMUL64rmi8_EVEX:
11979 case IMUL64rmi8_NF:
11980 case IMUL64rr:
11981 case IMUL64rr_EVEX:
11982 case IMUL64rr_ND:
11983 case IMUL64rr_NF:
11984 case IMUL64rr_NF_ND:
11985 case IMUL64rri32:
11986 case IMUL64rri32_EVEX:
11987 case IMUL64rri32_NF:
11988 case IMUL64rri8:
11989 case IMUL64rri8_EVEX:
11990 case IMUL64rri8_NF:
11991 case IMUL8m:
11992 case IMUL8m_EVEX:
11993 case IMUL8m_NF:
11994 case IMUL8r:
11995 case IMUL8r_EVEX:
11996 case IMUL8r_NF:
11997 return true;
11998 }
11999 return false;
12000}
12001
12002bool isVCVTSS2SI(unsigned Opcode) {
12003 switch (Opcode) {
12004 case VCVTSS2SI64Zrm_Int:
12005 case VCVTSS2SI64Zrr_Int:
12006 case VCVTSS2SI64Zrrb_Int:
12007 case VCVTSS2SI64rm_Int:
12008 case VCVTSS2SI64rr_Int:
12009 case VCVTSS2SIZrm_Int:
12010 case VCVTSS2SIZrr_Int:
12011 case VCVTSS2SIZrrb_Int:
12012 case VCVTSS2SIrm_Int:
12013 case VCVTSS2SIrr_Int:
12014 return true;
12015 }
12016 return false;
12017}
12018
12019bool isPUSHAW(unsigned Opcode) {
12020 return Opcode == PUSHA16;
12021}
12022
12023bool isSTOSD(unsigned Opcode) {
12024 return Opcode == STOSL;
12025}
12026
12027bool isPSRLDQ(unsigned Opcode) {
12028 return Opcode == PSRLDQri;
12029}
12030
12031bool isVSCATTERQPS(unsigned Opcode) {
12032 switch (Opcode) {
12033 case VSCATTERQPSZ128mr:
12034 case VSCATTERQPSZ256mr:
12035 case VSCATTERQPSZmr:
12036 return true;
12037 }
12038 return false;
12039}
12040
12041bool isFIDIV(unsigned Opcode) {
12042 switch (Opcode) {
12043 case DIV_FI16m:
12044 case DIV_FI32m:
12045 return true;
12046 }
12047 return false;
12048}
12049
12050bool isVFMSUB213PD(unsigned Opcode) {
12051 switch (Opcode) {
12052 case VFMSUB213PDYm:
12053 case VFMSUB213PDYr:
12054 case VFMSUB213PDZ128m:
12055 case VFMSUB213PDZ128mb:
12056 case VFMSUB213PDZ128mbk:
12057 case VFMSUB213PDZ128mbkz:
12058 case VFMSUB213PDZ128mk:
12059 case VFMSUB213PDZ128mkz:
12060 case VFMSUB213PDZ128r:
12061 case VFMSUB213PDZ128rk:
12062 case VFMSUB213PDZ128rkz:
12063 case VFMSUB213PDZ256m:
12064 case VFMSUB213PDZ256mb:
12065 case VFMSUB213PDZ256mbk:
12066 case VFMSUB213PDZ256mbkz:
12067 case VFMSUB213PDZ256mk:
12068 case VFMSUB213PDZ256mkz:
12069 case VFMSUB213PDZ256r:
12070 case VFMSUB213PDZ256rk:
12071 case VFMSUB213PDZ256rkz:
12072 case VFMSUB213PDZm:
12073 case VFMSUB213PDZmb:
12074 case VFMSUB213PDZmbk:
12075 case VFMSUB213PDZmbkz:
12076 case VFMSUB213PDZmk:
12077 case VFMSUB213PDZmkz:
12078 case VFMSUB213PDZr:
12079 case VFMSUB213PDZrb:
12080 case VFMSUB213PDZrbk:
12081 case VFMSUB213PDZrbkz:
12082 case VFMSUB213PDZrk:
12083 case VFMSUB213PDZrkz:
12084 case VFMSUB213PDm:
12085 case VFMSUB213PDr:
12086 return true;
12087 }
12088 return false;
12089}
12090
12091bool isVFMADDSUB231PH(unsigned Opcode) {
12092 switch (Opcode) {
12093 case VFMADDSUB231PHZ128m:
12094 case VFMADDSUB231PHZ128mb:
12095 case VFMADDSUB231PHZ128mbk:
12096 case VFMADDSUB231PHZ128mbkz:
12097 case VFMADDSUB231PHZ128mk:
12098 case VFMADDSUB231PHZ128mkz:
12099 case VFMADDSUB231PHZ128r:
12100 case VFMADDSUB231PHZ128rk:
12101 case VFMADDSUB231PHZ128rkz:
12102 case VFMADDSUB231PHZ256m:
12103 case VFMADDSUB231PHZ256mb:
12104 case VFMADDSUB231PHZ256mbk:
12105 case VFMADDSUB231PHZ256mbkz:
12106 case VFMADDSUB231PHZ256mk:
12107 case VFMADDSUB231PHZ256mkz:
12108 case VFMADDSUB231PHZ256r:
12109 case VFMADDSUB231PHZ256rk:
12110 case VFMADDSUB231PHZ256rkz:
12111 case VFMADDSUB231PHZm:
12112 case VFMADDSUB231PHZmb:
12113 case VFMADDSUB231PHZmbk:
12114 case VFMADDSUB231PHZmbkz:
12115 case VFMADDSUB231PHZmk:
12116 case VFMADDSUB231PHZmkz:
12117 case VFMADDSUB231PHZr:
12118 case VFMADDSUB231PHZrb:
12119 case VFMADDSUB231PHZrbk:
12120 case VFMADDSUB231PHZrbkz:
12121 case VFMADDSUB231PHZrk:
12122 case VFMADDSUB231PHZrkz:
12123 return true;
12124 }
12125 return false;
12126}
12127
12128bool isTDCALL(unsigned Opcode) {
12129 return Opcode == TDCALL;
12130}
12131
12132bool isPVALIDATE(unsigned Opcode) {
12133 switch (Opcode) {
12134 case PVALIDATE32:
12135 case PVALIDATE64:
12136 return true;
12137 }
12138 return false;
12139}
12140
12141bool isVPSHUFLW(unsigned Opcode) {
12142 switch (Opcode) {
12143 case VPSHUFLWYmi:
12144 case VPSHUFLWYri:
12145 case VPSHUFLWZ128mi:
12146 case VPSHUFLWZ128mik:
12147 case VPSHUFLWZ128mikz:
12148 case VPSHUFLWZ128ri:
12149 case VPSHUFLWZ128rik:
12150 case VPSHUFLWZ128rikz:
12151 case VPSHUFLWZ256mi:
12152 case VPSHUFLWZ256mik:
12153 case VPSHUFLWZ256mikz:
12154 case VPSHUFLWZ256ri:
12155 case VPSHUFLWZ256rik:
12156 case VPSHUFLWZ256rikz:
12157 case VPSHUFLWZmi:
12158 case VPSHUFLWZmik:
12159 case VPSHUFLWZmikz:
12160 case VPSHUFLWZri:
12161 case VPSHUFLWZrik:
12162 case VPSHUFLWZrikz:
12163 case VPSHUFLWmi:
12164 case VPSHUFLWri:
12165 return true;
12166 }
12167 return false;
12168}
12169
12170bool isPCLMULQDQ(unsigned Opcode) {
12171 switch (Opcode) {
12172 case PCLMULQDQrmi:
12173 case PCLMULQDQrri:
12174 return true;
12175 }
12176 return false;
12177}
12178
12179bool isCMPXCHG8B(unsigned Opcode) {
12180 return Opcode == CMPXCHG8B;
12181}
12182
12183bool isVPMOVM2B(unsigned Opcode) {
12184 switch (Opcode) {
12185 case VPMOVM2BZ128rk:
12186 case VPMOVM2BZ256rk:
12187 case VPMOVM2BZrk:
12188 return true;
12189 }
12190 return false;
12191}
12192
12193bool isVCVTUDQ2PH(unsigned Opcode) {
12194 switch (Opcode) {
12195 case VCVTUDQ2PHZ128rm:
12196 case VCVTUDQ2PHZ128rmb:
12197 case VCVTUDQ2PHZ128rmbk:
12198 case VCVTUDQ2PHZ128rmbkz:
12199 case VCVTUDQ2PHZ128rmk:
12200 case VCVTUDQ2PHZ128rmkz:
12201 case VCVTUDQ2PHZ128rr:
12202 case VCVTUDQ2PHZ128rrk:
12203 case VCVTUDQ2PHZ128rrkz:
12204 case VCVTUDQ2PHZ256rm:
12205 case VCVTUDQ2PHZ256rmb:
12206 case VCVTUDQ2PHZ256rmbk:
12207 case VCVTUDQ2PHZ256rmbkz:
12208 case VCVTUDQ2PHZ256rmk:
12209 case VCVTUDQ2PHZ256rmkz:
12210 case VCVTUDQ2PHZ256rr:
12211 case VCVTUDQ2PHZ256rrk:
12212 case VCVTUDQ2PHZ256rrkz:
12213 case VCVTUDQ2PHZrm:
12214 case VCVTUDQ2PHZrmb:
12215 case VCVTUDQ2PHZrmbk:
12216 case VCVTUDQ2PHZrmbkz:
12217 case VCVTUDQ2PHZrmk:
12218 case VCVTUDQ2PHZrmkz:
12219 case VCVTUDQ2PHZrr:
12220 case VCVTUDQ2PHZrrb:
12221 case VCVTUDQ2PHZrrbk:
12222 case VCVTUDQ2PHZrrbkz:
12223 case VCVTUDQ2PHZrrk:
12224 case VCVTUDQ2PHZrrkz:
12225 return true;
12226 }
12227 return false;
12228}
12229
12230bool isPEXTRQ(unsigned Opcode) {
12231 switch (Opcode) {
12232 case PEXTRQmri:
12233 case PEXTRQrri:
12234 return true;
12235 }
12236 return false;
12237}
12238
12239bool isXCRYPTCTR(unsigned Opcode) {
12240 return Opcode == XCRYPTCTR;
12241}
12242
12243bool isVREDUCEPH(unsigned Opcode) {
12244 switch (Opcode) {
12245 case VREDUCEPHZ128rmbi:
12246 case VREDUCEPHZ128rmbik:
12247 case VREDUCEPHZ128rmbikz:
12248 case VREDUCEPHZ128rmi:
12249 case VREDUCEPHZ128rmik:
12250 case VREDUCEPHZ128rmikz:
12251 case VREDUCEPHZ128rri:
12252 case VREDUCEPHZ128rrik:
12253 case VREDUCEPHZ128rrikz:
12254 case VREDUCEPHZ256rmbi:
12255 case VREDUCEPHZ256rmbik:
12256 case VREDUCEPHZ256rmbikz:
12257 case VREDUCEPHZ256rmi:
12258 case VREDUCEPHZ256rmik:
12259 case VREDUCEPHZ256rmikz:
12260 case VREDUCEPHZ256rri:
12261 case VREDUCEPHZ256rrik:
12262 case VREDUCEPHZ256rrikz:
12263 case VREDUCEPHZrmbi:
12264 case VREDUCEPHZrmbik:
12265 case VREDUCEPHZrmbikz:
12266 case VREDUCEPHZrmi:
12267 case VREDUCEPHZrmik:
12268 case VREDUCEPHZrmikz:
12269 case VREDUCEPHZrri:
12270 case VREDUCEPHZrrib:
12271 case VREDUCEPHZrribk:
12272 case VREDUCEPHZrribkz:
12273 case VREDUCEPHZrrik:
12274 case VREDUCEPHZrrikz:
12275 return true;
12276 }
12277 return false;
12278}
12279
12280bool isUCOMISD(unsigned Opcode) {
12281 switch (Opcode) {
12282 case UCOMISDrm:
12283 case UCOMISDrr:
12284 return true;
12285 }
12286 return false;
12287}
12288
12289bool isOUTSD(unsigned Opcode) {
12290 return Opcode == OUTSL;
12291}
12292
12293bool isSUBSS(unsigned Opcode) {
12294 switch (Opcode) {
12295 case SUBSSrm_Int:
12296 case SUBSSrr_Int:
12297 return true;
12298 }
12299 return false;
12300}
12301
12302bool isVFMSUBPS(unsigned Opcode) {
12303 switch (Opcode) {
12304 case VFMSUBPS4Ymr:
12305 case VFMSUBPS4Yrm:
12306 case VFMSUBPS4Yrr:
12307 case VFMSUBPS4Yrr_REV:
12308 case VFMSUBPS4mr:
12309 case VFMSUBPS4rm:
12310 case VFMSUBPS4rr:
12311 case VFMSUBPS4rr_REV:
12312 return true;
12313 }
12314 return false;
12315}
12316
12317bool isVPBLENDW(unsigned Opcode) {
12318 switch (Opcode) {
12319 case VPBLENDWYrmi:
12320 case VPBLENDWYrri:
12321 case VPBLENDWrmi:
12322 case VPBLENDWrri:
12323 return true;
12324 }
12325 return false;
12326}
12327
12328bool isVPEXPANDB(unsigned Opcode) {
12329 switch (Opcode) {
12330 case VPEXPANDBZ128rm:
12331 case VPEXPANDBZ128rmk:
12332 case VPEXPANDBZ128rmkz:
12333 case VPEXPANDBZ128rr:
12334 case VPEXPANDBZ128rrk:
12335 case VPEXPANDBZ128rrkz:
12336 case VPEXPANDBZ256rm:
12337 case VPEXPANDBZ256rmk:
12338 case VPEXPANDBZ256rmkz:
12339 case VPEXPANDBZ256rr:
12340 case VPEXPANDBZ256rrk:
12341 case VPEXPANDBZ256rrkz:
12342 case VPEXPANDBZrm:
12343 case VPEXPANDBZrmk:
12344 case VPEXPANDBZrmkz:
12345 case VPEXPANDBZrr:
12346 case VPEXPANDBZrrk:
12347 case VPEXPANDBZrrkz:
12348 return true;
12349 }
12350 return false;
12351}
12352
12353bool isBZHI(unsigned Opcode) {
12354 switch (Opcode) {
12355 case BZHI32rm:
12356 case BZHI32rm_EVEX:
12357 case BZHI32rm_NF:
12358 case BZHI32rr:
12359 case BZHI32rr_EVEX:
12360 case BZHI32rr_NF:
12361 case BZHI64rm:
12362 case BZHI64rm_EVEX:
12363 case BZHI64rm_NF:
12364 case BZHI64rr:
12365 case BZHI64rr_EVEX:
12366 case BZHI64rr_NF:
12367 return true;
12368 }
12369 return false;
12370}
12371
12372bool isVPRORVD(unsigned Opcode) {
12373 switch (Opcode) {
12374 case VPRORVDZ128rm:
12375 case VPRORVDZ128rmb:
12376 case VPRORVDZ128rmbk:
12377 case VPRORVDZ128rmbkz:
12378 case VPRORVDZ128rmk:
12379 case VPRORVDZ128rmkz:
12380 case VPRORVDZ128rr:
12381 case VPRORVDZ128rrk:
12382 case VPRORVDZ128rrkz:
12383 case VPRORVDZ256rm:
12384 case VPRORVDZ256rmb:
12385 case VPRORVDZ256rmbk:
12386 case VPRORVDZ256rmbkz:
12387 case VPRORVDZ256rmk:
12388 case VPRORVDZ256rmkz:
12389 case VPRORVDZ256rr:
12390 case VPRORVDZ256rrk:
12391 case VPRORVDZ256rrkz:
12392 case VPRORVDZrm:
12393 case VPRORVDZrmb:
12394 case VPRORVDZrmbk:
12395 case VPRORVDZrmbkz:
12396 case VPRORVDZrmk:
12397 case VPRORVDZrmkz:
12398 case VPRORVDZrr:
12399 case VPRORVDZrrk:
12400 case VPRORVDZrrkz:
12401 return true;
12402 }
12403 return false;
12404}
12405
12406bool isRMPQUERY(unsigned Opcode) {
12407 return Opcode == RMPQUERY;
12408}
12409
12410bool isVPSCATTERDQ(unsigned Opcode) {
12411 switch (Opcode) {
12412 case VPSCATTERDQZ128mr:
12413 case VPSCATTERDQZ256mr:
12414 case VPSCATTERDQZmr:
12415 return true;
12416 }
12417 return false;
12418}
12419
12420bool isPSMASH(unsigned Opcode) {
12421 return Opcode == PSMASH;
12422}
12423
12424bool isVPSHLDQ(unsigned Opcode) {
12425 switch (Opcode) {
12426 case VPSHLDQZ128rmbi:
12427 case VPSHLDQZ128rmbik:
12428 case VPSHLDQZ128rmbikz:
12429 case VPSHLDQZ128rmi:
12430 case VPSHLDQZ128rmik:
12431 case VPSHLDQZ128rmikz:
12432 case VPSHLDQZ128rri:
12433 case VPSHLDQZ128rrik:
12434 case VPSHLDQZ128rrikz:
12435 case VPSHLDQZ256rmbi:
12436 case VPSHLDQZ256rmbik:
12437 case VPSHLDQZ256rmbikz:
12438 case VPSHLDQZ256rmi:
12439 case VPSHLDQZ256rmik:
12440 case VPSHLDQZ256rmikz:
12441 case VPSHLDQZ256rri:
12442 case VPSHLDQZ256rrik:
12443 case VPSHLDQZ256rrikz:
12444 case VPSHLDQZrmbi:
12445 case VPSHLDQZrmbik:
12446 case VPSHLDQZrmbikz:
12447 case VPSHLDQZrmi:
12448 case VPSHLDQZrmik:
12449 case VPSHLDQZrmikz:
12450 case VPSHLDQZrri:
12451 case VPSHLDQZrrik:
12452 case VPSHLDQZrrikz:
12453 return true;
12454 }
12455 return false;
12456}
12457
12458bool isVSCATTERPF1DPD(unsigned Opcode) {
12459 return Opcode == VSCATTERPF1DPDm;
12460}
12461
12462bool isMONTMUL(unsigned Opcode) {
12463 return Opcode == MONTMUL;
12464}
12465
12466bool isVCVTPH2UQQ(unsigned Opcode) {
12467 switch (Opcode) {
12468 case VCVTPH2UQQZ128rm:
12469 case VCVTPH2UQQZ128rmb:
12470 case VCVTPH2UQQZ128rmbk:
12471 case VCVTPH2UQQZ128rmbkz:
12472 case VCVTPH2UQQZ128rmk:
12473 case VCVTPH2UQQZ128rmkz:
12474 case VCVTPH2UQQZ128rr:
12475 case VCVTPH2UQQZ128rrk:
12476 case VCVTPH2UQQZ128rrkz:
12477 case VCVTPH2UQQZ256rm:
12478 case VCVTPH2UQQZ256rmb:
12479 case VCVTPH2UQQZ256rmbk:
12480 case VCVTPH2UQQZ256rmbkz:
12481 case VCVTPH2UQQZ256rmk:
12482 case VCVTPH2UQQZ256rmkz:
12483 case VCVTPH2UQQZ256rr:
12484 case VCVTPH2UQQZ256rrk:
12485 case VCVTPH2UQQZ256rrkz:
12486 case VCVTPH2UQQZrm:
12487 case VCVTPH2UQQZrmb:
12488 case VCVTPH2UQQZrmbk:
12489 case VCVTPH2UQQZrmbkz:
12490 case VCVTPH2UQQZrmk:
12491 case VCVTPH2UQQZrmkz:
12492 case VCVTPH2UQQZrr:
12493 case VCVTPH2UQQZrrb:
12494 case VCVTPH2UQQZrrbk:
12495 case VCVTPH2UQQZrrbkz:
12496 case VCVTPH2UQQZrrk:
12497 case VCVTPH2UQQZrrkz:
12498 return true;
12499 }
12500 return false;
12501}
12502
12503bool isPSLLD(unsigned Opcode) {
12504 switch (Opcode) {
12505 case MMX_PSLLDri:
12506 case MMX_PSLLDrm:
12507 case MMX_PSLLDrr:
12508 case PSLLDri:
12509 case PSLLDrm:
12510 case PSLLDrr:
12511 return true;
12512 }
12513 return false;
12514}
12515
12516bool isSAR(unsigned Opcode) {
12517 switch (Opcode) {
12518 case SAR16m1:
12519 case SAR16m1_EVEX:
12520 case SAR16m1_ND:
12521 case SAR16m1_NF:
12522 case SAR16m1_NF_ND:
12523 case SAR16mCL:
12524 case SAR16mCL_EVEX:
12525 case SAR16mCL_ND:
12526 case SAR16mCL_NF:
12527 case SAR16mCL_NF_ND:
12528 case SAR16mi:
12529 case SAR16mi_EVEX:
12530 case SAR16mi_ND:
12531 case SAR16mi_NF:
12532 case SAR16mi_NF_ND:
12533 case SAR16r1:
12534 case SAR16r1_EVEX:
12535 case SAR16r1_ND:
12536 case SAR16r1_NF:
12537 case SAR16r1_NF_ND:
12538 case SAR16rCL:
12539 case SAR16rCL_EVEX:
12540 case SAR16rCL_ND:
12541 case SAR16rCL_NF:
12542 case SAR16rCL_NF_ND:
12543 case SAR16ri:
12544 case SAR16ri_EVEX:
12545 case SAR16ri_ND:
12546 case SAR16ri_NF:
12547 case SAR16ri_NF_ND:
12548 case SAR32m1:
12549 case SAR32m1_EVEX:
12550 case SAR32m1_ND:
12551 case SAR32m1_NF:
12552 case SAR32m1_NF_ND:
12553 case SAR32mCL:
12554 case SAR32mCL_EVEX:
12555 case SAR32mCL_ND:
12556 case SAR32mCL_NF:
12557 case SAR32mCL_NF_ND:
12558 case SAR32mi:
12559 case SAR32mi_EVEX:
12560 case SAR32mi_ND:
12561 case SAR32mi_NF:
12562 case SAR32mi_NF_ND:
12563 case SAR32r1:
12564 case SAR32r1_EVEX:
12565 case SAR32r1_ND:
12566 case SAR32r1_NF:
12567 case SAR32r1_NF_ND:
12568 case SAR32rCL:
12569 case SAR32rCL_EVEX:
12570 case SAR32rCL_ND:
12571 case SAR32rCL_NF:
12572 case SAR32rCL_NF_ND:
12573 case SAR32ri:
12574 case SAR32ri_EVEX:
12575 case SAR32ri_ND:
12576 case SAR32ri_NF:
12577 case SAR32ri_NF_ND:
12578 case SAR64m1:
12579 case SAR64m1_EVEX:
12580 case SAR64m1_ND:
12581 case SAR64m1_NF:
12582 case SAR64m1_NF_ND:
12583 case SAR64mCL:
12584 case SAR64mCL_EVEX:
12585 case SAR64mCL_ND:
12586 case SAR64mCL_NF:
12587 case SAR64mCL_NF_ND:
12588 case SAR64mi:
12589 case SAR64mi_EVEX:
12590 case SAR64mi_ND:
12591 case SAR64mi_NF:
12592 case SAR64mi_NF_ND:
12593 case SAR64r1:
12594 case SAR64r1_EVEX:
12595 case SAR64r1_ND:
12596 case SAR64r1_NF:
12597 case SAR64r1_NF_ND:
12598 case SAR64rCL:
12599 case SAR64rCL_EVEX:
12600 case SAR64rCL_ND:
12601 case SAR64rCL_NF:
12602 case SAR64rCL_NF_ND:
12603 case SAR64ri:
12604 case SAR64ri_EVEX:
12605 case SAR64ri_ND:
12606 case SAR64ri_NF:
12607 case SAR64ri_NF_ND:
12608 case SAR8m1:
12609 case SAR8m1_EVEX:
12610 case SAR8m1_ND:
12611 case SAR8m1_NF:
12612 case SAR8m1_NF_ND:
12613 case SAR8mCL:
12614 case SAR8mCL_EVEX:
12615 case SAR8mCL_ND:
12616 case SAR8mCL_NF:
12617 case SAR8mCL_NF_ND:
12618 case SAR8mi:
12619 case SAR8mi_EVEX:
12620 case SAR8mi_ND:
12621 case SAR8mi_NF:
12622 case SAR8mi_NF_ND:
12623 case SAR8r1:
12624 case SAR8r1_EVEX:
12625 case SAR8r1_ND:
12626 case SAR8r1_NF:
12627 case SAR8r1_NF_ND:
12628 case SAR8rCL:
12629 case SAR8rCL_EVEX:
12630 case SAR8rCL_ND:
12631 case SAR8rCL_NF:
12632 case SAR8rCL_NF_ND:
12633 case SAR8ri:
12634 case SAR8ri_EVEX:
12635 case SAR8ri_ND:
12636 case SAR8ri_NF:
12637 case SAR8ri_NF_ND:
12638 return true;
12639 }
12640 return false;
12641}
12642
12643bool isLDTILECFG(unsigned Opcode) {
12644 switch (Opcode) {
12645 case LDTILECFG:
12646 case LDTILECFG_EVEX:
12647 return true;
12648 }
12649 return false;
12650}
12651
12652bool isPMINUB(unsigned Opcode) {
12653 switch (Opcode) {
12654 case MMX_PMINUBrm:
12655 case MMX_PMINUBrr:
12656 case PMINUBrm:
12657 case PMINUBrr:
12658 return true;
12659 }
12660 return false;
12661}
12662
12663bool isVCVTNEEBF162PS(unsigned Opcode) {
12664 switch (Opcode) {
12665 case VCVTNEEBF162PSYrm:
12666 case VCVTNEEBF162PSrm:
12667 return true;
12668 }
12669 return false;
12670}
12671
12672bool isMOVDIR64B(unsigned Opcode) {
12673 switch (Opcode) {
12674 case MOVDIR64B16:
12675 case MOVDIR64B32:
12676 case MOVDIR64B32_EVEX:
12677 case MOVDIR64B64:
12678 case MOVDIR64B64_EVEX:
12679 return true;
12680 }
12681 return false;
12682}
12683
12684bool isSQRTPS(unsigned Opcode) {
12685 switch (Opcode) {
12686 case SQRTPSm:
12687 case SQRTPSr:
12688 return true;
12689 }
12690 return false;
12691}
12692
12693bool isSTR(unsigned Opcode) {
12694 switch (Opcode) {
12695 case STR16r:
12696 case STR32r:
12697 case STR64r:
12698 case STRm:
12699 return true;
12700 }
12701 return false;
12702}
12703
12704bool isKANDNQ(unsigned Opcode) {
12705 return Opcode == KANDNQkk;
12706}
12707
12708bool isBSF(unsigned Opcode) {
12709 switch (Opcode) {
12710 case BSF16rm:
12711 case BSF16rr:
12712 case BSF32rm:
12713 case BSF32rr:
12714 case BSF64rm:
12715 case BSF64rr:
12716 return true;
12717 }
12718 return false;
12719}
12720
12721bool isINCSSPD(unsigned Opcode) {
12722 return Opcode == INCSSPD;
12723}
12724
12725bool isVPDPBUUDS(unsigned Opcode) {
12726 switch (Opcode) {
12727 case VPDPBUUDSYrm:
12728 case VPDPBUUDSYrr:
12729 case VPDPBUUDSZ128rm:
12730 case VPDPBUUDSZ128rmb:
12731 case VPDPBUUDSZ128rmbk:
12732 case VPDPBUUDSZ128rmbkz:
12733 case VPDPBUUDSZ128rmk:
12734 case VPDPBUUDSZ128rmkz:
12735 case VPDPBUUDSZ128rr:
12736 case VPDPBUUDSZ128rrk:
12737 case VPDPBUUDSZ128rrkz:
12738 case VPDPBUUDSZ256rm:
12739 case VPDPBUUDSZ256rmb:
12740 case VPDPBUUDSZ256rmbk:
12741 case VPDPBUUDSZ256rmbkz:
12742 case VPDPBUUDSZ256rmk:
12743 case VPDPBUUDSZ256rmkz:
12744 case VPDPBUUDSZ256rr:
12745 case VPDPBUUDSZ256rrk:
12746 case VPDPBUUDSZ256rrkz:
12747 case VPDPBUUDSZrm:
12748 case VPDPBUUDSZrmb:
12749 case VPDPBUUDSZrmbk:
12750 case VPDPBUUDSZrmbkz:
12751 case VPDPBUUDSZrmk:
12752 case VPDPBUUDSZrmkz:
12753 case VPDPBUUDSZrr:
12754 case VPDPBUUDSZrrk:
12755 case VPDPBUUDSZrrkz:
12756 case VPDPBUUDSrm:
12757 case VPDPBUUDSrr:
12758 return true;
12759 }
12760 return false;
12761}
12762
12763bool isCMPXCHG(unsigned Opcode) {
12764 switch (Opcode) {
12765 case CMPXCHG16rm:
12766 case CMPXCHG16rr:
12767 case CMPXCHG32rm:
12768 case CMPXCHG32rr:
12769 case CMPXCHG64rm:
12770 case CMPXCHG64rr:
12771 case CMPXCHG8rm:
12772 case CMPXCHG8rr:
12773 return true;
12774 }
12775 return false;
12776}
12777
12778bool isVPSIGNW(unsigned Opcode) {
12779 switch (Opcode) {
12780 case VPSIGNWYrm:
12781 case VPSIGNWYrr:
12782 case VPSIGNWrm:
12783 case VPSIGNWrr:
12784 return true;
12785 }
12786 return false;
12787}
12788
12789bool isVCOMISBF16(unsigned Opcode) {
12790 switch (Opcode) {
12791 case VCOMISBF16Zrm:
12792 case VCOMISBF16Zrr:
12793 return true;
12794 }
12795 return false;
12796}
12797
12798bool isLES(unsigned Opcode) {
12799 switch (Opcode) {
12800 case LES16rm:
12801 case LES32rm:
12802 return true;
12803 }
12804 return false;
12805}
12806
12807bool isCVTSS2SI(unsigned Opcode) {
12808 switch (Opcode) {
12809 case CVTSS2SI64rm_Int:
12810 case CVTSS2SI64rr_Int:
12811 case CVTSS2SIrm_Int:
12812 case CVTSS2SIrr_Int:
12813 return true;
12814 }
12815 return false;
12816}
12817
12818bool isPFACC(unsigned Opcode) {
12819 switch (Opcode) {
12820 case PFACCrm:
12821 case PFACCrr:
12822 return true;
12823 }
12824 return false;
12825}
12826
12827bool isFCOMPI(unsigned Opcode) {
12828 return Opcode == COM_FIPr;
12829}
12830
12831bool isPUNPCKHWD(unsigned Opcode) {
12832 switch (Opcode) {
12833 case MMX_PUNPCKHWDrm:
12834 case MMX_PUNPCKHWDrr:
12835 case PUNPCKHWDrm:
12836 case PUNPCKHWDrr:
12837 return true;
12838 }
12839 return false;
12840}
12841
12842bool isVPMOVUSWB(unsigned Opcode) {
12843 switch (Opcode) {
12844 case VPMOVUSWBZ128mr:
12845 case VPMOVUSWBZ128mrk:
12846 case VPMOVUSWBZ128rr:
12847 case VPMOVUSWBZ128rrk:
12848 case VPMOVUSWBZ128rrkz:
12849 case VPMOVUSWBZ256mr:
12850 case VPMOVUSWBZ256mrk:
12851 case VPMOVUSWBZ256rr:
12852 case VPMOVUSWBZ256rrk:
12853 case VPMOVUSWBZ256rrkz:
12854 case VPMOVUSWBZmr:
12855 case VPMOVUSWBZmrk:
12856 case VPMOVUSWBZrr:
12857 case VPMOVUSWBZrrk:
12858 case VPMOVUSWBZrrkz:
12859 return true;
12860 }
12861 return false;
12862}
12863
12864bool isVPTESTNMW(unsigned Opcode) {
12865 switch (Opcode) {
12866 case VPTESTNMWZ128rm:
12867 case VPTESTNMWZ128rmk:
12868 case VPTESTNMWZ128rr:
12869 case VPTESTNMWZ128rrk:
12870 case VPTESTNMWZ256rm:
12871 case VPTESTNMWZ256rmk:
12872 case VPTESTNMWZ256rr:
12873 case VPTESTNMWZ256rrk:
12874 case VPTESTNMWZrm:
12875 case VPTESTNMWZrmk:
12876 case VPTESTNMWZrr:
12877 case VPTESTNMWZrrk:
12878 return true;
12879 }
12880 return false;
12881}
12882
12883bool isVPMULDQ(unsigned Opcode) {
12884 switch (Opcode) {
12885 case VPMULDQYrm:
12886 case VPMULDQYrr:
12887 case VPMULDQZ128rm:
12888 case VPMULDQZ128rmb:
12889 case VPMULDQZ128rmbk:
12890 case VPMULDQZ128rmbkz:
12891 case VPMULDQZ128rmk:
12892 case VPMULDQZ128rmkz:
12893 case VPMULDQZ128rr:
12894 case VPMULDQZ128rrk:
12895 case VPMULDQZ128rrkz:
12896 case VPMULDQZ256rm:
12897 case VPMULDQZ256rmb:
12898 case VPMULDQZ256rmbk:
12899 case VPMULDQZ256rmbkz:
12900 case VPMULDQZ256rmk:
12901 case VPMULDQZ256rmkz:
12902 case VPMULDQZ256rr:
12903 case VPMULDQZ256rrk:
12904 case VPMULDQZ256rrkz:
12905 case VPMULDQZrm:
12906 case VPMULDQZrmb:
12907 case VPMULDQZrmbk:
12908 case VPMULDQZrmbkz:
12909 case VPMULDQZrmk:
12910 case VPMULDQZrmkz:
12911 case VPMULDQZrr:
12912 case VPMULDQZrrk:
12913 case VPMULDQZrrkz:
12914 case VPMULDQrm:
12915 case VPMULDQrr:
12916 return true;
12917 }
12918 return false;
12919}
12920
12921bool isSHRX(unsigned Opcode) {
12922 switch (Opcode) {
12923 case SHRX32rm:
12924 case SHRX32rm_EVEX:
12925 case SHRX32rr:
12926 case SHRX32rr_EVEX:
12927 case SHRX64rm:
12928 case SHRX64rm_EVEX:
12929 case SHRX64rr:
12930 case SHRX64rr_EVEX:
12931 return true;
12932 }
12933 return false;
12934}
12935
12936bool isKXORQ(unsigned Opcode) {
12937 return Opcode == KXORQkk;
12938}
12939
12940bool isVGETEXPSD(unsigned Opcode) {
12941 switch (Opcode) {
12942 case VGETEXPSDZm:
12943 case VGETEXPSDZmk:
12944 case VGETEXPSDZmkz:
12945 case VGETEXPSDZr:
12946 case VGETEXPSDZrb:
12947 case VGETEXPSDZrbk:
12948 case VGETEXPSDZrbkz:
12949 case VGETEXPSDZrk:
12950 case VGETEXPSDZrkz:
12951 return true;
12952 }
12953 return false;
12954}
12955
12956bool isV4FNMADDPS(unsigned Opcode) {
12957 switch (Opcode) {
12958 case V4FNMADDPSrm:
12959 case V4FNMADDPSrmk:
12960 case V4FNMADDPSrmkz:
12961 return true;
12962 }
12963 return false;
12964}
12965
12966bool isVFNMSUB231SD(unsigned Opcode) {
12967 switch (Opcode) {
12968 case VFNMSUB231SDZm_Int:
12969 case VFNMSUB231SDZmk_Int:
12970 case VFNMSUB231SDZmkz_Int:
12971 case VFNMSUB231SDZr_Int:
12972 case VFNMSUB231SDZrb_Int:
12973 case VFNMSUB231SDZrbk_Int:
12974 case VFNMSUB231SDZrbkz_Int:
12975 case VFNMSUB231SDZrk_Int:
12976 case VFNMSUB231SDZrkz_Int:
12977 case VFNMSUB231SDm_Int:
12978 case VFNMSUB231SDr_Int:
12979 return true;
12980 }
12981 return false;
12982}
12983
12984bool isVPSHLD(unsigned Opcode) {
12985 switch (Opcode) {
12986 case VPSHLDmr:
12987 case VPSHLDrm:
12988 case VPSHLDrr:
12989 case VPSHLDrr_REV:
12990 return true;
12991 }
12992 return false;
12993}
12994
12995bool isPAVGB(unsigned Opcode) {
12996 switch (Opcode) {
12997 case MMX_PAVGBrm:
12998 case MMX_PAVGBrr:
12999 case PAVGBrm:
13000 case PAVGBrr:
13001 return true;
13002 }
13003 return false;
13004}
13005
13006bool isPMOVZXBD(unsigned Opcode) {
13007 switch (Opcode) {
13008 case PMOVZXBDrm:
13009 case PMOVZXBDrr:
13010 return true;
13011 }
13012 return false;
13013}
13014
13015bool isKORTESTW(unsigned Opcode) {
13016 return Opcode == KORTESTWkk;
13017}
13018
13019bool isVSHUFPS(unsigned Opcode) {
13020 switch (Opcode) {
13021 case VSHUFPSYrmi:
13022 case VSHUFPSYrri:
13023 case VSHUFPSZ128rmbi:
13024 case VSHUFPSZ128rmbik:
13025 case VSHUFPSZ128rmbikz:
13026 case VSHUFPSZ128rmi:
13027 case VSHUFPSZ128rmik:
13028 case VSHUFPSZ128rmikz:
13029 case VSHUFPSZ128rri:
13030 case VSHUFPSZ128rrik:
13031 case VSHUFPSZ128rrikz:
13032 case VSHUFPSZ256rmbi:
13033 case VSHUFPSZ256rmbik:
13034 case VSHUFPSZ256rmbikz:
13035 case VSHUFPSZ256rmi:
13036 case VSHUFPSZ256rmik:
13037 case VSHUFPSZ256rmikz:
13038 case VSHUFPSZ256rri:
13039 case VSHUFPSZ256rrik:
13040 case VSHUFPSZ256rrikz:
13041 case VSHUFPSZrmbi:
13042 case VSHUFPSZrmbik:
13043 case VSHUFPSZrmbikz:
13044 case VSHUFPSZrmi:
13045 case VSHUFPSZrmik:
13046 case VSHUFPSZrmikz:
13047 case VSHUFPSZrri:
13048 case VSHUFPSZrrik:
13049 case VSHUFPSZrrikz:
13050 case VSHUFPSrmi:
13051 case VSHUFPSrri:
13052 return true;
13053 }
13054 return false;
13055}
13056
13057bool isAESENCWIDE128KL(unsigned Opcode) {
13058 return Opcode == AESENCWIDE128KL;
13059}
13060
13061bool isVPXORD(unsigned Opcode) {
13062 switch (Opcode) {
13063 case VPXORDZ128rm:
13064 case VPXORDZ128rmb:
13065 case VPXORDZ128rmbk:
13066 case VPXORDZ128rmbkz:
13067 case VPXORDZ128rmk:
13068 case VPXORDZ128rmkz:
13069 case VPXORDZ128rr:
13070 case VPXORDZ128rrk:
13071 case VPXORDZ128rrkz:
13072 case VPXORDZ256rm:
13073 case VPXORDZ256rmb:
13074 case VPXORDZ256rmbk:
13075 case VPXORDZ256rmbkz:
13076 case VPXORDZ256rmk:
13077 case VPXORDZ256rmkz:
13078 case VPXORDZ256rr:
13079 case VPXORDZ256rrk:
13080 case VPXORDZ256rrkz:
13081 case VPXORDZrm:
13082 case VPXORDZrmb:
13083 case VPXORDZrmbk:
13084 case VPXORDZrmbkz:
13085 case VPXORDZrmk:
13086 case VPXORDZrmkz:
13087 case VPXORDZrr:
13088 case VPXORDZrrk:
13089 case VPXORDZrrkz:
13090 return true;
13091 }
13092 return false;
13093}
13094
13095bool isVPSHAW(unsigned Opcode) {
13096 switch (Opcode) {
13097 case VPSHAWmr:
13098 case VPSHAWrm:
13099 case VPSHAWrr:
13100 case VPSHAWrr_REV:
13101 return true;
13102 }
13103 return false;
13104}
13105
13106bool isVFMSUB132BF16(unsigned Opcode) {
13107 switch (Opcode) {
13108 case VFMSUB132BF16Z128m:
13109 case VFMSUB132BF16Z128mb:
13110 case VFMSUB132BF16Z128mbk:
13111 case VFMSUB132BF16Z128mbkz:
13112 case VFMSUB132BF16Z128mk:
13113 case VFMSUB132BF16Z128mkz:
13114 case VFMSUB132BF16Z128r:
13115 case VFMSUB132BF16Z128rk:
13116 case VFMSUB132BF16Z128rkz:
13117 case VFMSUB132BF16Z256m:
13118 case VFMSUB132BF16Z256mb:
13119 case VFMSUB132BF16Z256mbk:
13120 case VFMSUB132BF16Z256mbkz:
13121 case VFMSUB132BF16Z256mk:
13122 case VFMSUB132BF16Z256mkz:
13123 case VFMSUB132BF16Z256r:
13124 case VFMSUB132BF16Z256rk:
13125 case VFMSUB132BF16Z256rkz:
13126 case VFMSUB132BF16Zm:
13127 case VFMSUB132BF16Zmb:
13128 case VFMSUB132BF16Zmbk:
13129 case VFMSUB132BF16Zmbkz:
13130 case VFMSUB132BF16Zmk:
13131 case VFMSUB132BF16Zmkz:
13132 case VFMSUB132BF16Zr:
13133 case VFMSUB132BF16Zrk:
13134 case VFMSUB132BF16Zrkz:
13135 return true;
13136 }
13137 return false;
13138}
13139
13140bool isVPERMT2B(unsigned Opcode) {
13141 switch (Opcode) {
13142 case VPERMT2BZ128rm:
13143 case VPERMT2BZ128rmk:
13144 case VPERMT2BZ128rmkz:
13145 case VPERMT2BZ128rr:
13146 case VPERMT2BZ128rrk:
13147 case VPERMT2BZ128rrkz:
13148 case VPERMT2BZ256rm:
13149 case VPERMT2BZ256rmk:
13150 case VPERMT2BZ256rmkz:
13151 case VPERMT2BZ256rr:
13152 case VPERMT2BZ256rrk:
13153 case VPERMT2BZ256rrkz:
13154 case VPERMT2BZrm:
13155 case VPERMT2BZrmk:
13156 case VPERMT2BZrmkz:
13157 case VPERMT2BZrr:
13158 case VPERMT2BZrrk:
13159 case VPERMT2BZrrkz:
13160 return true;
13161 }
13162 return false;
13163}
13164
13165bool isVFMADD213PD(unsigned Opcode) {
13166 switch (Opcode) {
13167 case VFMADD213PDYm:
13168 case VFMADD213PDYr:
13169 case VFMADD213PDZ128m:
13170 case VFMADD213PDZ128mb:
13171 case VFMADD213PDZ128mbk:
13172 case VFMADD213PDZ128mbkz:
13173 case VFMADD213PDZ128mk:
13174 case VFMADD213PDZ128mkz:
13175 case VFMADD213PDZ128r:
13176 case VFMADD213PDZ128rk:
13177 case VFMADD213PDZ128rkz:
13178 case VFMADD213PDZ256m:
13179 case VFMADD213PDZ256mb:
13180 case VFMADD213PDZ256mbk:
13181 case VFMADD213PDZ256mbkz:
13182 case VFMADD213PDZ256mk:
13183 case VFMADD213PDZ256mkz:
13184 case VFMADD213PDZ256r:
13185 case VFMADD213PDZ256rk:
13186 case VFMADD213PDZ256rkz:
13187 case VFMADD213PDZm:
13188 case VFMADD213PDZmb:
13189 case VFMADD213PDZmbk:
13190 case VFMADD213PDZmbkz:
13191 case VFMADD213PDZmk:
13192 case VFMADD213PDZmkz:
13193 case VFMADD213PDZr:
13194 case VFMADD213PDZrb:
13195 case VFMADD213PDZrbk:
13196 case VFMADD213PDZrbkz:
13197 case VFMADD213PDZrk:
13198 case VFMADD213PDZrkz:
13199 case VFMADD213PDm:
13200 case VFMADD213PDr:
13201 return true;
13202 }
13203 return false;
13204}
13205
13206bool isVPGATHERQD(unsigned Opcode) {
13207 switch (Opcode) {
13208 case VPGATHERQDYrm:
13209 case VPGATHERQDZ128rm:
13210 case VPGATHERQDZ256rm:
13211 case VPGATHERQDZrm:
13212 case VPGATHERQDrm:
13213 return true;
13214 }
13215 return false;
13216}
13217
13218bool isVFNMSUB213BF16(unsigned Opcode) {
13219 switch (Opcode) {
13220 case VFNMSUB213BF16Z128m:
13221 case VFNMSUB213BF16Z128mb:
13222 case VFNMSUB213BF16Z128mbk:
13223 case VFNMSUB213BF16Z128mbkz:
13224 case VFNMSUB213BF16Z128mk:
13225 case VFNMSUB213BF16Z128mkz:
13226 case VFNMSUB213BF16Z128r:
13227 case VFNMSUB213BF16Z128rk:
13228 case VFNMSUB213BF16Z128rkz:
13229 case VFNMSUB213BF16Z256m:
13230 case VFNMSUB213BF16Z256mb:
13231 case VFNMSUB213BF16Z256mbk:
13232 case VFNMSUB213BF16Z256mbkz:
13233 case VFNMSUB213BF16Z256mk:
13234 case VFNMSUB213BF16Z256mkz:
13235 case VFNMSUB213BF16Z256r:
13236 case VFNMSUB213BF16Z256rk:
13237 case VFNMSUB213BF16Z256rkz:
13238 case VFNMSUB213BF16Zm:
13239 case VFNMSUB213BF16Zmb:
13240 case VFNMSUB213BF16Zmbk:
13241 case VFNMSUB213BF16Zmbkz:
13242 case VFNMSUB213BF16Zmk:
13243 case VFNMSUB213BF16Zmkz:
13244 case VFNMSUB213BF16Zr:
13245 case VFNMSUB213BF16Zrk:
13246 case VFNMSUB213BF16Zrkz:
13247 return true;
13248 }
13249 return false;
13250}
13251
13252bool isVCVTPS2IBS(unsigned Opcode) {
13253 switch (Opcode) {
13254 case VCVTPS2IBSZ128rm:
13255 case VCVTPS2IBSZ128rmb:
13256 case VCVTPS2IBSZ128rmbk:
13257 case VCVTPS2IBSZ128rmbkz:
13258 case VCVTPS2IBSZ128rmk:
13259 case VCVTPS2IBSZ128rmkz:
13260 case VCVTPS2IBSZ128rr:
13261 case VCVTPS2IBSZ128rrk:
13262 case VCVTPS2IBSZ128rrkz:
13263 case VCVTPS2IBSZ256rm:
13264 case VCVTPS2IBSZ256rmb:
13265 case VCVTPS2IBSZ256rmbk:
13266 case VCVTPS2IBSZ256rmbkz:
13267 case VCVTPS2IBSZ256rmk:
13268 case VCVTPS2IBSZ256rmkz:
13269 case VCVTPS2IBSZ256rr:
13270 case VCVTPS2IBSZ256rrk:
13271 case VCVTPS2IBSZ256rrkz:
13272 case VCVTPS2IBSZrm:
13273 case VCVTPS2IBSZrmb:
13274 case VCVTPS2IBSZrmbk:
13275 case VCVTPS2IBSZrmbkz:
13276 case VCVTPS2IBSZrmk:
13277 case VCVTPS2IBSZrmkz:
13278 case VCVTPS2IBSZrr:
13279 case VCVTPS2IBSZrrb:
13280 case VCVTPS2IBSZrrbk:
13281 case VCVTPS2IBSZrrbkz:
13282 case VCVTPS2IBSZrrk:
13283 case VCVTPS2IBSZrrkz:
13284 return true;
13285 }
13286 return false;
13287}
13288
13289bool isVPCMPGTW(unsigned Opcode) {
13290 switch (Opcode) {
13291 case VPCMPGTWYrm:
13292 case VPCMPGTWYrr:
13293 case VPCMPGTWZ128rm:
13294 case VPCMPGTWZ128rmk:
13295 case VPCMPGTWZ128rr:
13296 case VPCMPGTWZ128rrk:
13297 case VPCMPGTWZ256rm:
13298 case VPCMPGTWZ256rmk:
13299 case VPCMPGTWZ256rr:
13300 case VPCMPGTWZ256rrk:
13301 case VPCMPGTWZrm:
13302 case VPCMPGTWZrmk:
13303 case VPCMPGTWZrr:
13304 case VPCMPGTWZrrk:
13305 case VPCMPGTWrm:
13306 case VPCMPGTWrr:
13307 return true;
13308 }
13309 return false;
13310}
13311
13312bool isVMOVRSB(unsigned Opcode) {
13313 switch (Opcode) {
13314 case VMOVRSBZ128m:
13315 case VMOVRSBZ128mk:
13316 case VMOVRSBZ128mkz:
13317 case VMOVRSBZ256m:
13318 case VMOVRSBZ256mk:
13319 case VMOVRSBZ256mkz:
13320 case VMOVRSBZm:
13321 case VMOVRSBZmk:
13322 case VMOVRSBZmkz:
13323 return true;
13324 }
13325 return false;
13326}
13327
13328bool isVGETMANTSH(unsigned Opcode) {
13329 switch (Opcode) {
13330 case VGETMANTSHZrmi:
13331 case VGETMANTSHZrmik:
13332 case VGETMANTSHZrmikz:
13333 case VGETMANTSHZrri:
13334 case VGETMANTSHZrrib:
13335 case VGETMANTSHZrribk:
13336 case VGETMANTSHZrribkz:
13337 case VGETMANTSHZrrik:
13338 case VGETMANTSHZrrikz:
13339 return true;
13340 }
13341 return false;
13342}
13343
13344bool isVANDPS(unsigned Opcode) {
13345 switch (Opcode) {
13346 case VANDPSYrm:
13347 case VANDPSYrr:
13348 case VANDPSZ128rm:
13349 case VANDPSZ128rmb:
13350 case VANDPSZ128rmbk:
13351 case VANDPSZ128rmbkz:
13352 case VANDPSZ128rmk:
13353 case VANDPSZ128rmkz:
13354 case VANDPSZ128rr:
13355 case VANDPSZ128rrk:
13356 case VANDPSZ128rrkz:
13357 case VANDPSZ256rm:
13358 case VANDPSZ256rmb:
13359 case VANDPSZ256rmbk:
13360 case VANDPSZ256rmbkz:
13361 case VANDPSZ256rmk:
13362 case VANDPSZ256rmkz:
13363 case VANDPSZ256rr:
13364 case VANDPSZ256rrk:
13365 case VANDPSZ256rrkz:
13366 case VANDPSZrm:
13367 case VANDPSZrmb:
13368 case VANDPSZrmbk:
13369 case VANDPSZrmbkz:
13370 case VANDPSZrmk:
13371 case VANDPSZrmkz:
13372 case VANDPSZrr:
13373 case VANDPSZrrk:
13374 case VANDPSZrrkz:
13375 case VANDPSrm:
13376 case VANDPSrr:
13377 return true;
13378 }
13379 return false;
13380}
13381
13382bool isVDIVPS(unsigned Opcode) {
13383 switch (Opcode) {
13384 case VDIVPSYrm:
13385 case VDIVPSYrr:
13386 case VDIVPSZ128rm:
13387 case VDIVPSZ128rmb:
13388 case VDIVPSZ128rmbk:
13389 case VDIVPSZ128rmbkz:
13390 case VDIVPSZ128rmk:
13391 case VDIVPSZ128rmkz:
13392 case VDIVPSZ128rr:
13393 case VDIVPSZ128rrk:
13394 case VDIVPSZ128rrkz:
13395 case VDIVPSZ256rm:
13396 case VDIVPSZ256rmb:
13397 case VDIVPSZ256rmbk:
13398 case VDIVPSZ256rmbkz:
13399 case VDIVPSZ256rmk:
13400 case VDIVPSZ256rmkz:
13401 case VDIVPSZ256rr:
13402 case VDIVPSZ256rrk:
13403 case VDIVPSZ256rrkz:
13404 case VDIVPSZrm:
13405 case VDIVPSZrmb:
13406 case VDIVPSZrmbk:
13407 case VDIVPSZrmbkz:
13408 case VDIVPSZrmk:
13409 case VDIVPSZrmkz:
13410 case VDIVPSZrr:
13411 case VDIVPSZrrb:
13412 case VDIVPSZrrbk:
13413 case VDIVPSZrrbkz:
13414 case VDIVPSZrrk:
13415 case VDIVPSZrrkz:
13416 case VDIVPSrm:
13417 case VDIVPSrr:
13418 return true;
13419 }
13420 return false;
13421}
13422
13423bool isVANDNPS(unsigned Opcode) {
13424 switch (Opcode) {
13425 case VANDNPSYrm:
13426 case VANDNPSYrr:
13427 case VANDNPSZ128rm:
13428 case VANDNPSZ128rmb:
13429 case VANDNPSZ128rmbk:
13430 case VANDNPSZ128rmbkz:
13431 case VANDNPSZ128rmk:
13432 case VANDNPSZ128rmkz:
13433 case VANDNPSZ128rr:
13434 case VANDNPSZ128rrk:
13435 case VANDNPSZ128rrkz:
13436 case VANDNPSZ256rm:
13437 case VANDNPSZ256rmb:
13438 case VANDNPSZ256rmbk:
13439 case VANDNPSZ256rmbkz:
13440 case VANDNPSZ256rmk:
13441 case VANDNPSZ256rmkz:
13442 case VANDNPSZ256rr:
13443 case VANDNPSZ256rrk:
13444 case VANDNPSZ256rrkz:
13445 case VANDNPSZrm:
13446 case VANDNPSZrmb:
13447 case VANDNPSZrmbk:
13448 case VANDNPSZrmbkz:
13449 case VANDNPSZrmk:
13450 case VANDNPSZrmkz:
13451 case VANDNPSZrr:
13452 case VANDNPSZrrk:
13453 case VANDNPSZrrkz:
13454 case VANDNPSrm:
13455 case VANDNPSrr:
13456 return true;
13457 }
13458 return false;
13459}
13460
13461bool isVPBROADCASTW(unsigned Opcode) {
13462 switch (Opcode) {
13463 case VPBROADCASTWYrm:
13464 case VPBROADCASTWYrr:
13465 case VPBROADCASTWZ128rm:
13466 case VPBROADCASTWZ128rmk:
13467 case VPBROADCASTWZ128rmkz:
13468 case VPBROADCASTWZ128rr:
13469 case VPBROADCASTWZ128rrk:
13470 case VPBROADCASTWZ128rrkz:
13471 case VPBROADCASTWZ256rm:
13472 case VPBROADCASTWZ256rmk:
13473 case VPBROADCASTWZ256rmkz:
13474 case VPBROADCASTWZ256rr:
13475 case VPBROADCASTWZ256rrk:
13476 case VPBROADCASTWZ256rrkz:
13477 case VPBROADCASTWZrm:
13478 case VPBROADCASTWZrmk:
13479 case VPBROADCASTWZrmkz:
13480 case VPBROADCASTWZrr:
13481 case VPBROADCASTWZrrk:
13482 case VPBROADCASTWZrrkz:
13483 case VPBROADCASTWrZ128rr:
13484 case VPBROADCASTWrZ128rrk:
13485 case VPBROADCASTWrZ128rrkz:
13486 case VPBROADCASTWrZ256rr:
13487 case VPBROADCASTWrZ256rrk:
13488 case VPBROADCASTWrZ256rrkz:
13489 case VPBROADCASTWrZrr:
13490 case VPBROADCASTWrZrrk:
13491 case VPBROADCASTWrZrrkz:
13492 case VPBROADCASTWrm:
13493 case VPBROADCASTWrr:
13494 return true;
13495 }
13496 return false;
13497}
13498
13499bool isFLDL2T(unsigned Opcode) {
13500 return Opcode == FLDL2T;
13501}
13502
13503bool isVPERMB(unsigned Opcode) {
13504 switch (Opcode) {
13505 case VPERMBZ128rm:
13506 case VPERMBZ128rmk:
13507 case VPERMBZ128rmkz:
13508 case VPERMBZ128rr:
13509 case VPERMBZ128rrk:
13510 case VPERMBZ128rrkz:
13511 case VPERMBZ256rm:
13512 case VPERMBZ256rmk:
13513 case VPERMBZ256rmkz:
13514 case VPERMBZ256rr:
13515 case VPERMBZ256rrk:
13516 case VPERMBZ256rrkz:
13517 case VPERMBZrm:
13518 case VPERMBZrmk:
13519 case VPERMBZrmkz:
13520 case VPERMBZrr:
13521 case VPERMBZrrk:
13522 case VPERMBZrrkz:
13523 return true;
13524 }
13525 return false;
13526}
13527
13528bool isFCMOVNBE(unsigned Opcode) {
13529 return Opcode == CMOVNBE_F;
13530}
13531
13532bool isVCVTTPH2W(unsigned Opcode) {
13533 switch (Opcode) {
13534 case VCVTTPH2WZ128rm:
13535 case VCVTTPH2WZ128rmb:
13536 case VCVTTPH2WZ128rmbk:
13537 case VCVTTPH2WZ128rmbkz:
13538 case VCVTTPH2WZ128rmk:
13539 case VCVTTPH2WZ128rmkz:
13540 case VCVTTPH2WZ128rr:
13541 case VCVTTPH2WZ128rrk:
13542 case VCVTTPH2WZ128rrkz:
13543 case VCVTTPH2WZ256rm:
13544 case VCVTTPH2WZ256rmb:
13545 case VCVTTPH2WZ256rmbk:
13546 case VCVTTPH2WZ256rmbkz:
13547 case VCVTTPH2WZ256rmk:
13548 case VCVTTPH2WZ256rmkz:
13549 case VCVTTPH2WZ256rr:
13550 case VCVTTPH2WZ256rrk:
13551 case VCVTTPH2WZ256rrkz:
13552 case VCVTTPH2WZrm:
13553 case VCVTTPH2WZrmb:
13554 case VCVTTPH2WZrmbk:
13555 case VCVTTPH2WZrmbkz:
13556 case VCVTTPH2WZrmk:
13557 case VCVTTPH2WZrmkz:
13558 case VCVTTPH2WZrr:
13559 case VCVTTPH2WZrrb:
13560 case VCVTTPH2WZrrbk:
13561 case VCVTTPH2WZrrbkz:
13562 case VCVTTPH2WZrrk:
13563 case VCVTTPH2WZrrkz:
13564 return true;
13565 }
13566 return false;
13567}
13568
13569bool isPMOVZXBQ(unsigned Opcode) {
13570 switch (Opcode) {
13571 case PMOVZXBQrm:
13572 case PMOVZXBQrr:
13573 return true;
13574 }
13575 return false;
13576}
13577
13578bool isPF2ID(unsigned Opcode) {
13579 switch (Opcode) {
13580 case PF2IDrm:
13581 case PF2IDrr:
13582 return true;
13583 }
13584 return false;
13585}
13586
13587bool isVFNMADD132PD(unsigned Opcode) {
13588 switch (Opcode) {
13589 case VFNMADD132PDYm:
13590 case VFNMADD132PDYr:
13591 case VFNMADD132PDZ128m:
13592 case VFNMADD132PDZ128mb:
13593 case VFNMADD132PDZ128mbk:
13594 case VFNMADD132PDZ128mbkz:
13595 case VFNMADD132PDZ128mk:
13596 case VFNMADD132PDZ128mkz:
13597 case VFNMADD132PDZ128r:
13598 case VFNMADD132PDZ128rk:
13599 case VFNMADD132PDZ128rkz:
13600 case VFNMADD132PDZ256m:
13601 case VFNMADD132PDZ256mb:
13602 case VFNMADD132PDZ256mbk:
13603 case VFNMADD132PDZ256mbkz:
13604 case VFNMADD132PDZ256mk:
13605 case VFNMADD132PDZ256mkz:
13606 case VFNMADD132PDZ256r:
13607 case VFNMADD132PDZ256rk:
13608 case VFNMADD132PDZ256rkz:
13609 case VFNMADD132PDZm:
13610 case VFNMADD132PDZmb:
13611 case VFNMADD132PDZmbk:
13612 case VFNMADD132PDZmbkz:
13613 case VFNMADD132PDZmk:
13614 case VFNMADD132PDZmkz:
13615 case VFNMADD132PDZr:
13616 case VFNMADD132PDZrb:
13617 case VFNMADD132PDZrbk:
13618 case VFNMADD132PDZrbkz:
13619 case VFNMADD132PDZrk:
13620 case VFNMADD132PDZrkz:
13621 case VFNMADD132PDm:
13622 case VFNMADD132PDr:
13623 return true;
13624 }
13625 return false;
13626}
13627
13628bool isPMULHRSW(unsigned Opcode) {
13629 switch (Opcode) {
13630 case MMX_PMULHRSWrm:
13631 case MMX_PMULHRSWrr:
13632 case PMULHRSWrm:
13633 case PMULHRSWrr:
13634 return true;
13635 }
13636 return false;
13637}
13638
13639bool isKADDD(unsigned Opcode) {
13640 return Opcode == KADDDkk;
13641}
13642
13643bool isVFNMSUB132SH(unsigned Opcode) {
13644 switch (Opcode) {
13645 case VFNMSUB132SHZm_Int:
13646 case VFNMSUB132SHZmk_Int:
13647 case VFNMSUB132SHZmkz_Int:
13648 case VFNMSUB132SHZr_Int:
13649 case VFNMSUB132SHZrb_Int:
13650 case VFNMSUB132SHZrbk_Int:
13651 case VFNMSUB132SHZrbkz_Int:
13652 case VFNMSUB132SHZrk_Int:
13653 case VFNMSUB132SHZrkz_Int:
13654 return true;
13655 }
13656 return false;
13657}
13658
13659bool isUIRET(unsigned Opcode) {
13660 return Opcode == UIRET;
13661}
13662
13663bool isBSR(unsigned Opcode) {
13664 switch (Opcode) {
13665 case BSR16rm:
13666 case BSR16rr:
13667 case BSR32rm:
13668 case BSR32rr:
13669 case BSR64rm:
13670 case BSR64rr:
13671 return true;
13672 }
13673 return false;
13674}
13675
13676bool isPCMPEQQ(unsigned Opcode) {
13677 switch (Opcode) {
13678 case PCMPEQQrm:
13679 case PCMPEQQrr:
13680 return true;
13681 }
13682 return false;
13683}
13684
13685bool isCDQ(unsigned Opcode) {
13686 return Opcode == CDQ;
13687}
13688
13689bool isPMAXSW(unsigned Opcode) {
13690 switch (Opcode) {
13691 case MMX_PMAXSWrm:
13692 case MMX_PMAXSWrr:
13693 case PMAXSWrm:
13694 case PMAXSWrr:
13695 return true;
13696 }
13697 return false;
13698}
13699
13700bool isSIDTD(unsigned Opcode) {
13701 return Opcode == SIDT32m;
13702}
13703
13704bool isVCVTPS2PHX(unsigned Opcode) {
13705 switch (Opcode) {
13706 case VCVTPS2PHXZ128rm:
13707 case VCVTPS2PHXZ128rmb:
13708 case VCVTPS2PHXZ128rmbk:
13709 case VCVTPS2PHXZ128rmbkz:
13710 case VCVTPS2PHXZ128rmk:
13711 case VCVTPS2PHXZ128rmkz:
13712 case VCVTPS2PHXZ128rr:
13713 case VCVTPS2PHXZ128rrk:
13714 case VCVTPS2PHXZ128rrkz:
13715 case VCVTPS2PHXZ256rm:
13716 case VCVTPS2PHXZ256rmb:
13717 case VCVTPS2PHXZ256rmbk:
13718 case VCVTPS2PHXZ256rmbkz:
13719 case VCVTPS2PHXZ256rmk:
13720 case VCVTPS2PHXZ256rmkz:
13721 case VCVTPS2PHXZ256rr:
13722 case VCVTPS2PHXZ256rrk:
13723 case VCVTPS2PHXZ256rrkz:
13724 case VCVTPS2PHXZrm:
13725 case VCVTPS2PHXZrmb:
13726 case VCVTPS2PHXZrmbk:
13727 case VCVTPS2PHXZrmbkz:
13728 case VCVTPS2PHXZrmk:
13729 case VCVTPS2PHXZrmkz:
13730 case VCVTPS2PHXZrr:
13731 case VCVTPS2PHXZrrb:
13732 case VCVTPS2PHXZrrbk:
13733 case VCVTPS2PHXZrrbkz:
13734 case VCVTPS2PHXZrrk:
13735 case VCVTPS2PHXZrrkz:
13736 return true;
13737 }
13738 return false;
13739}
13740
13741bool isVPSLLVQ(unsigned Opcode) {
13742 switch (Opcode) {
13743 case VPSLLVQYrm:
13744 case VPSLLVQYrr:
13745 case VPSLLVQZ128rm:
13746 case VPSLLVQZ128rmb:
13747 case VPSLLVQZ128rmbk:
13748 case VPSLLVQZ128rmbkz:
13749 case VPSLLVQZ128rmk:
13750 case VPSLLVQZ128rmkz:
13751 case VPSLLVQZ128rr:
13752 case VPSLLVQZ128rrk:
13753 case VPSLLVQZ128rrkz:
13754 case VPSLLVQZ256rm:
13755 case VPSLLVQZ256rmb:
13756 case VPSLLVQZ256rmbk:
13757 case VPSLLVQZ256rmbkz:
13758 case VPSLLVQZ256rmk:
13759 case VPSLLVQZ256rmkz:
13760 case VPSLLVQZ256rr:
13761 case VPSLLVQZ256rrk:
13762 case VPSLLVQZ256rrkz:
13763 case VPSLLVQZrm:
13764 case VPSLLVQZrmb:
13765 case VPSLLVQZrmbk:
13766 case VPSLLVQZrmbkz:
13767 case VPSLLVQZrmk:
13768 case VPSLLVQZrmkz:
13769 case VPSLLVQZrr:
13770 case VPSLLVQZrrk:
13771 case VPSLLVQZrrkz:
13772 case VPSLLVQrm:
13773 case VPSLLVQrr:
13774 return true;
13775 }
13776 return false;
13777}
13778
13779bool isMOVQ(unsigned Opcode) {
13780 switch (Opcode) {
13781 case MMX_MOVD64from64mr:
13782 case MMX_MOVD64from64rr:
13783 case MMX_MOVD64to64rm:
13784 case MMX_MOVD64to64rr:
13785 case MMX_MOVQ64mr:
13786 case MMX_MOVQ64rm:
13787 case MMX_MOVQ64rr:
13788 case MMX_MOVQ64rr_REV:
13789 case MOV64toPQIrm:
13790 case MOV64toPQIrr:
13791 case MOVPQI2QImr:
13792 case MOVPQI2QIrr:
13793 case MOVPQIto64mr:
13794 case MOVPQIto64rr:
13795 case MOVQI2PQIrm:
13796 case MOVZPQILo2PQIrr:
13797 return true;
13798 }
13799 return false;
13800}
13801
13802bool isPREFETCH(unsigned Opcode) {
13803 return Opcode == PREFETCH;
13804}
13805
13806bool isVCMPBF16(unsigned Opcode) {
13807 switch (Opcode) {
13808 case VCMPBF16Z128rmbi:
13809 case VCMPBF16Z128rmbik:
13810 case VCMPBF16Z128rmi:
13811 case VCMPBF16Z128rmik:
13812 case VCMPBF16Z128rri:
13813 case VCMPBF16Z128rrik:
13814 case VCMPBF16Z256rmbi:
13815 case VCMPBF16Z256rmbik:
13816 case VCMPBF16Z256rmi:
13817 case VCMPBF16Z256rmik:
13818 case VCMPBF16Z256rri:
13819 case VCMPBF16Z256rrik:
13820 case VCMPBF16Zrmbi:
13821 case VCMPBF16Zrmbik:
13822 case VCMPBF16Zrmi:
13823 case VCMPBF16Zrmik:
13824 case VCMPBF16Zrri:
13825 case VCMPBF16Zrrik:
13826 return true;
13827 }
13828 return false;
13829}
13830
13831bool isCLRSSBSY(unsigned Opcode) {
13832 return Opcode == CLRSSBSY;
13833}
13834
13835bool isTCVTROWPS2PHL(unsigned Opcode) {
13836 switch (Opcode) {
13837 case TCVTROWPS2PHLrte:
13838 case TCVTROWPS2PHLrti:
13839 return true;
13840 }
13841 return false;
13842}
13843
13844bool isPSHUFW(unsigned Opcode) {
13845 switch (Opcode) {
13846 case MMX_PSHUFWmi:
13847 case MMX_PSHUFWri:
13848 return true;
13849 }
13850 return false;
13851}
13852
13853bool isVPDPWSUDS(unsigned Opcode) {
13854 switch (Opcode) {
13855 case VPDPWSUDSYrm:
13856 case VPDPWSUDSYrr:
13857 case VPDPWSUDSZ128rm:
13858 case VPDPWSUDSZ128rmb:
13859 case VPDPWSUDSZ128rmbk:
13860 case VPDPWSUDSZ128rmbkz:
13861 case VPDPWSUDSZ128rmk:
13862 case VPDPWSUDSZ128rmkz:
13863 case VPDPWSUDSZ128rr:
13864 case VPDPWSUDSZ128rrk:
13865 case VPDPWSUDSZ128rrkz:
13866 case VPDPWSUDSZ256rm:
13867 case VPDPWSUDSZ256rmb:
13868 case VPDPWSUDSZ256rmbk:
13869 case VPDPWSUDSZ256rmbkz:
13870 case VPDPWSUDSZ256rmk:
13871 case VPDPWSUDSZ256rmkz:
13872 case VPDPWSUDSZ256rr:
13873 case VPDPWSUDSZ256rrk:
13874 case VPDPWSUDSZ256rrkz:
13875 case VPDPWSUDSZrm:
13876 case VPDPWSUDSZrmb:
13877 case VPDPWSUDSZrmbk:
13878 case VPDPWSUDSZrmbkz:
13879 case VPDPWSUDSZrmk:
13880 case VPDPWSUDSZrmkz:
13881 case VPDPWSUDSZrr:
13882 case VPDPWSUDSZrrk:
13883 case VPDPWSUDSZrrkz:
13884 case VPDPWSUDSrm:
13885 case VPDPWSUDSrr:
13886 return true;
13887 }
13888 return false;
13889}
13890
13891bool isVPMOVSXBQ(unsigned Opcode) {
13892 switch (Opcode) {
13893 case VPMOVSXBQYrm:
13894 case VPMOVSXBQYrr:
13895 case VPMOVSXBQZ128rm:
13896 case VPMOVSXBQZ128rmk:
13897 case VPMOVSXBQZ128rmkz:
13898 case VPMOVSXBQZ128rr:
13899 case VPMOVSXBQZ128rrk:
13900 case VPMOVSXBQZ128rrkz:
13901 case VPMOVSXBQZ256rm:
13902 case VPMOVSXBQZ256rmk:
13903 case VPMOVSXBQZ256rmkz:
13904 case VPMOVSXBQZ256rr:
13905 case VPMOVSXBQZ256rrk:
13906 case VPMOVSXBQZ256rrkz:
13907 case VPMOVSXBQZrm:
13908 case VPMOVSXBQZrmk:
13909 case VPMOVSXBQZrmkz:
13910 case VPMOVSXBQZrr:
13911 case VPMOVSXBQZrrk:
13912 case VPMOVSXBQZrrkz:
13913 case VPMOVSXBQrm:
13914 case VPMOVSXBQrr:
13915 return true;
13916 }
13917 return false;
13918}
13919
13920bool isFICOMP(unsigned Opcode) {
13921 switch (Opcode) {
13922 case FICOMP16m:
13923 case FICOMP32m:
13924 return true;
13925 }
13926 return false;
13927}
13928
13929bool isVFNMSUB132SS(unsigned Opcode) {
13930 switch (Opcode) {
13931 case VFNMSUB132SSZm_Int:
13932 case VFNMSUB132SSZmk_Int:
13933 case VFNMSUB132SSZmkz_Int:
13934 case VFNMSUB132SSZr_Int:
13935 case VFNMSUB132SSZrb_Int:
13936 case VFNMSUB132SSZrbk_Int:
13937 case VFNMSUB132SSZrbkz_Int:
13938 case VFNMSUB132SSZrk_Int:
13939 case VFNMSUB132SSZrkz_Int:
13940 case VFNMSUB132SSm_Int:
13941 case VFNMSUB132SSr_Int:
13942 return true;
13943 }
13944 return false;
13945}
13946
13947bool isVLDMXCSR(unsigned Opcode) {
13948 return Opcode == VLDMXCSR;
13949}
13950
13951bool isVPSUBUSW(unsigned Opcode) {
13952 switch (Opcode) {
13953 case VPSUBUSWYrm:
13954 case VPSUBUSWYrr:
13955 case VPSUBUSWZ128rm:
13956 case VPSUBUSWZ128rmk:
13957 case VPSUBUSWZ128rmkz:
13958 case VPSUBUSWZ128rr:
13959 case VPSUBUSWZ128rrk:
13960 case VPSUBUSWZ128rrkz:
13961 case VPSUBUSWZ256rm:
13962 case VPSUBUSWZ256rmk:
13963 case VPSUBUSWZ256rmkz:
13964 case VPSUBUSWZ256rr:
13965 case VPSUBUSWZ256rrk:
13966 case VPSUBUSWZ256rrkz:
13967 case VPSUBUSWZrm:
13968 case VPSUBUSWZrmk:
13969 case VPSUBUSWZrmkz:
13970 case VPSUBUSWZrr:
13971 case VPSUBUSWZrrk:
13972 case VPSUBUSWZrrkz:
13973 case VPSUBUSWrm:
13974 case VPSUBUSWrr:
13975 return true;
13976 }
13977 return false;
13978}
13979
13980bool isRETF(unsigned Opcode) {
13981 switch (Opcode) {
13982 case LRET16:
13983 case LRET32:
13984 case LRETI16:
13985 case LRETI32:
13986 return true;
13987 }
13988 return false;
13989}
13990
13991bool isKMOVQ(unsigned Opcode) {
13992 switch (Opcode) {
13993 case KMOVQkk:
13994 case KMOVQkk_EVEX:
13995 case KMOVQkm:
13996 case KMOVQkm_EVEX:
13997 case KMOVQkr:
13998 case KMOVQkr_EVEX:
13999 case KMOVQmk:
14000 case KMOVQmk_EVEX:
14001 case KMOVQrk:
14002 case KMOVQrk_EVEX:
14003 return true;
14004 }
14005 return false;
14006}
14007
14008bool isVPADDUSW(unsigned Opcode) {
14009 switch (Opcode) {
14010 case VPADDUSWYrm:
14011 case VPADDUSWYrr:
14012 case VPADDUSWZ128rm:
14013 case VPADDUSWZ128rmk:
14014 case VPADDUSWZ128rmkz:
14015 case VPADDUSWZ128rr:
14016 case VPADDUSWZ128rrk:
14017 case VPADDUSWZ128rrkz:
14018 case VPADDUSWZ256rm:
14019 case VPADDUSWZ256rmk:
14020 case VPADDUSWZ256rmkz:
14021 case VPADDUSWZ256rr:
14022 case VPADDUSWZ256rrk:
14023 case VPADDUSWZ256rrkz:
14024 case VPADDUSWZrm:
14025 case VPADDUSWZrmk:
14026 case VPADDUSWZrmkz:
14027 case VPADDUSWZrr:
14028 case VPADDUSWZrrk:
14029 case VPADDUSWZrrkz:
14030 case VPADDUSWrm:
14031 case VPADDUSWrr:
14032 return true;
14033 }
14034 return false;
14035}
14036
14037bool isPACKSSDW(unsigned Opcode) {
14038 switch (Opcode) {
14039 case MMX_PACKSSDWrm:
14040 case MMX_PACKSSDWrr:
14041 case PACKSSDWrm:
14042 case PACKSSDWrr:
14043 return true;
14044 }
14045 return false;
14046}
14047
14048bool isUMONITOR(unsigned Opcode) {
14049 switch (Opcode) {
14050 case UMONITOR16:
14051 case UMONITOR32:
14052 case UMONITOR64:
14053 return true;
14054 }
14055 return false;
14056}
14057
14058bool isENQCMDS(unsigned Opcode) {
14059 switch (Opcode) {
14060 case ENQCMDS16:
14061 case ENQCMDS32:
14062 case ENQCMDS32_EVEX:
14063 case ENQCMDS64:
14064 case ENQCMDS64_EVEX:
14065 return true;
14066 }
14067 return false;
14068}
14069
14070bool isVCOMXSD(unsigned Opcode) {
14071 switch (Opcode) {
14072 case VCOMXSDZrm_Int:
14073 case VCOMXSDZrr_Int:
14074 case VCOMXSDZrrb_Int:
14075 return true;
14076 }
14077 return false;
14078}
14079
14080bool isVPMAXSQ(unsigned Opcode) {
14081 switch (Opcode) {
14082 case VPMAXSQZ128rm:
14083 case VPMAXSQZ128rmb:
14084 case VPMAXSQZ128rmbk:
14085 case VPMAXSQZ128rmbkz:
14086 case VPMAXSQZ128rmk:
14087 case VPMAXSQZ128rmkz:
14088 case VPMAXSQZ128rr:
14089 case VPMAXSQZ128rrk:
14090 case VPMAXSQZ128rrkz:
14091 case VPMAXSQZ256rm:
14092 case VPMAXSQZ256rmb:
14093 case VPMAXSQZ256rmbk:
14094 case VPMAXSQZ256rmbkz:
14095 case VPMAXSQZ256rmk:
14096 case VPMAXSQZ256rmkz:
14097 case VPMAXSQZ256rr:
14098 case VPMAXSQZ256rrk:
14099 case VPMAXSQZ256rrkz:
14100 case VPMAXSQZrm:
14101 case VPMAXSQZrmb:
14102 case VPMAXSQZrmbk:
14103 case VPMAXSQZrmbkz:
14104 case VPMAXSQZrmk:
14105 case VPMAXSQZrmkz:
14106 case VPMAXSQZrr:
14107 case VPMAXSQZrrk:
14108 case VPMAXSQZrrkz:
14109 return true;
14110 }
14111 return false;
14112}
14113
14114bool isVFMSUB213BF16(unsigned Opcode) {
14115 switch (Opcode) {
14116 case VFMSUB213BF16Z128m:
14117 case VFMSUB213BF16Z128mb:
14118 case VFMSUB213BF16Z128mbk:
14119 case VFMSUB213BF16Z128mbkz:
14120 case VFMSUB213BF16Z128mk:
14121 case VFMSUB213BF16Z128mkz:
14122 case VFMSUB213BF16Z128r:
14123 case VFMSUB213BF16Z128rk:
14124 case VFMSUB213BF16Z128rkz:
14125 case VFMSUB213BF16Z256m:
14126 case VFMSUB213BF16Z256mb:
14127 case VFMSUB213BF16Z256mbk:
14128 case VFMSUB213BF16Z256mbkz:
14129 case VFMSUB213BF16Z256mk:
14130 case VFMSUB213BF16Z256mkz:
14131 case VFMSUB213BF16Z256r:
14132 case VFMSUB213BF16Z256rk:
14133 case VFMSUB213BF16Z256rkz:
14134 case VFMSUB213BF16Zm:
14135 case VFMSUB213BF16Zmb:
14136 case VFMSUB213BF16Zmbk:
14137 case VFMSUB213BF16Zmbkz:
14138 case VFMSUB213BF16Zmk:
14139 case VFMSUB213BF16Zmkz:
14140 case VFMSUB213BF16Zr:
14141 case VFMSUB213BF16Zrk:
14142 case VFMSUB213BF16Zrkz:
14143 return true;
14144 }
14145 return false;
14146}
14147
14148bool isVPERMT2Q(unsigned Opcode) {
14149 switch (Opcode) {
14150 case VPERMT2QZ128rm:
14151 case VPERMT2QZ128rmb:
14152 case VPERMT2QZ128rmbk:
14153 case VPERMT2QZ128rmbkz:
14154 case VPERMT2QZ128rmk:
14155 case VPERMT2QZ128rmkz:
14156 case VPERMT2QZ128rr:
14157 case VPERMT2QZ128rrk:
14158 case VPERMT2QZ128rrkz:
14159 case VPERMT2QZ256rm:
14160 case VPERMT2QZ256rmb:
14161 case VPERMT2QZ256rmbk:
14162 case VPERMT2QZ256rmbkz:
14163 case VPERMT2QZ256rmk:
14164 case VPERMT2QZ256rmkz:
14165 case VPERMT2QZ256rr:
14166 case VPERMT2QZ256rrk:
14167 case VPERMT2QZ256rrkz:
14168 case VPERMT2QZrm:
14169 case VPERMT2QZrmb:
14170 case VPERMT2QZrmbk:
14171 case VPERMT2QZrmbkz:
14172 case VPERMT2QZrmk:
14173 case VPERMT2QZrmkz:
14174 case VPERMT2QZrr:
14175 case VPERMT2QZrrk:
14176 case VPERMT2QZrrkz:
14177 return true;
14178 }
14179 return false;
14180}
14181
14182bool isFDECSTP(unsigned Opcode) {
14183 return Opcode == FDECSTP;
14184}
14185
14186bool isVPTESTMQ(unsigned Opcode) {
14187 switch (Opcode) {
14188 case VPTESTMQZ128rm:
14189 case VPTESTMQZ128rmb:
14190 case VPTESTMQZ128rmbk:
14191 case VPTESTMQZ128rmk:
14192 case VPTESTMQZ128rr:
14193 case VPTESTMQZ128rrk:
14194 case VPTESTMQZ256rm:
14195 case VPTESTMQZ256rmb:
14196 case VPTESTMQZ256rmbk:
14197 case VPTESTMQZ256rmk:
14198 case VPTESTMQZ256rr:
14199 case VPTESTMQZ256rrk:
14200 case VPTESTMQZrm:
14201 case VPTESTMQZrmb:
14202 case VPTESTMQZrmbk:
14203 case VPTESTMQZrmk:
14204 case VPTESTMQZrr:
14205 case VPTESTMQZrrk:
14206 return true;
14207 }
14208 return false;
14209}
14210
14211bool isVRCP14PD(unsigned Opcode) {
14212 switch (Opcode) {
14213 case VRCP14PDZ128m:
14214 case VRCP14PDZ128mb:
14215 case VRCP14PDZ128mbk:
14216 case VRCP14PDZ128mbkz:
14217 case VRCP14PDZ128mk:
14218 case VRCP14PDZ128mkz:
14219 case VRCP14PDZ128r:
14220 case VRCP14PDZ128rk:
14221 case VRCP14PDZ128rkz:
14222 case VRCP14PDZ256m:
14223 case VRCP14PDZ256mb:
14224 case VRCP14PDZ256mbk:
14225 case VRCP14PDZ256mbkz:
14226 case VRCP14PDZ256mk:
14227 case VRCP14PDZ256mkz:
14228 case VRCP14PDZ256r:
14229 case VRCP14PDZ256rk:
14230 case VRCP14PDZ256rkz:
14231 case VRCP14PDZm:
14232 case VRCP14PDZmb:
14233 case VRCP14PDZmbk:
14234 case VRCP14PDZmbkz:
14235 case VRCP14PDZmk:
14236 case VRCP14PDZmkz:
14237 case VRCP14PDZr:
14238 case VRCP14PDZrk:
14239 case VRCP14PDZrkz:
14240 return true;
14241 }
14242 return false;
14243}
14244
14245bool isARPL(unsigned Opcode) {
14246 switch (Opcode) {
14247 case ARPL16mr:
14248 case ARPL16rr:
14249 return true;
14250 }
14251 return false;
14252}
14253
14254bool isVFMSUB213SD(unsigned Opcode) {
14255 switch (Opcode) {
14256 case VFMSUB213SDZm_Int:
14257 case VFMSUB213SDZmk_Int:
14258 case VFMSUB213SDZmkz_Int:
14259 case VFMSUB213SDZr_Int:
14260 case VFMSUB213SDZrb_Int:
14261 case VFMSUB213SDZrbk_Int:
14262 case VFMSUB213SDZrbkz_Int:
14263 case VFMSUB213SDZrk_Int:
14264 case VFMSUB213SDZrkz_Int:
14265 case VFMSUB213SDm_Int:
14266 case VFMSUB213SDr_Int:
14267 return true;
14268 }
14269 return false;
14270}
14271
14272bool isJMPABS(unsigned Opcode) {
14273 return Opcode == JMPABS64i;
14274}
14275
14276bool isVUNPCKHPS(unsigned Opcode) {
14277 switch (Opcode) {
14278 case VUNPCKHPSYrm:
14279 case VUNPCKHPSYrr:
14280 case VUNPCKHPSZ128rm:
14281 case VUNPCKHPSZ128rmb:
14282 case VUNPCKHPSZ128rmbk:
14283 case VUNPCKHPSZ128rmbkz:
14284 case VUNPCKHPSZ128rmk:
14285 case VUNPCKHPSZ128rmkz:
14286 case VUNPCKHPSZ128rr:
14287 case VUNPCKHPSZ128rrk:
14288 case VUNPCKHPSZ128rrkz:
14289 case VUNPCKHPSZ256rm:
14290 case VUNPCKHPSZ256rmb:
14291 case VUNPCKHPSZ256rmbk:
14292 case VUNPCKHPSZ256rmbkz:
14293 case VUNPCKHPSZ256rmk:
14294 case VUNPCKHPSZ256rmkz:
14295 case VUNPCKHPSZ256rr:
14296 case VUNPCKHPSZ256rrk:
14297 case VUNPCKHPSZ256rrkz:
14298 case VUNPCKHPSZrm:
14299 case VUNPCKHPSZrmb:
14300 case VUNPCKHPSZrmbk:
14301 case VUNPCKHPSZrmbkz:
14302 case VUNPCKHPSZrmk:
14303 case VUNPCKHPSZrmkz:
14304 case VUNPCKHPSZrr:
14305 case VUNPCKHPSZrrk:
14306 case VUNPCKHPSZrrkz:
14307 case VUNPCKHPSrm:
14308 case VUNPCKHPSrr:
14309 return true;
14310 }
14311 return false;
14312}
14313
14314bool isVFNMADDSS(unsigned Opcode) {
14315 switch (Opcode) {
14316 case VFNMADDSS4mr:
14317 case VFNMADDSS4rm:
14318 case VFNMADDSS4rr:
14319 case VFNMADDSS4rr_REV:
14320 return true;
14321 }
14322 return false;
14323}
14324
14325bool isSIDT(unsigned Opcode) {
14326 return Opcode == SIDT64m;
14327}
14328
14329bool isVPCMPGTB(unsigned Opcode) {
14330 switch (Opcode) {
14331 case VPCMPGTBYrm:
14332 case VPCMPGTBYrr:
14333 case VPCMPGTBZ128rm:
14334 case VPCMPGTBZ128rmk:
14335 case VPCMPGTBZ128rr:
14336 case VPCMPGTBZ128rrk:
14337 case VPCMPGTBZ256rm:
14338 case VPCMPGTBZ256rmk:
14339 case VPCMPGTBZ256rr:
14340 case VPCMPGTBZ256rrk:
14341 case VPCMPGTBZrm:
14342 case VPCMPGTBZrmk:
14343 case VPCMPGTBZrr:
14344 case VPCMPGTBZrrk:
14345 case VPCMPGTBrm:
14346 case VPCMPGTBrr:
14347 return true;
14348 }
14349 return false;
14350}
14351
14352bool isVPRORD(unsigned Opcode) {
14353 switch (Opcode) {
14354 case VPRORDZ128mbi:
14355 case VPRORDZ128mbik:
14356 case VPRORDZ128mbikz:
14357 case VPRORDZ128mi:
14358 case VPRORDZ128mik:
14359 case VPRORDZ128mikz:
14360 case VPRORDZ128ri:
14361 case VPRORDZ128rik:
14362 case VPRORDZ128rikz:
14363 case VPRORDZ256mbi:
14364 case VPRORDZ256mbik:
14365 case VPRORDZ256mbikz:
14366 case VPRORDZ256mi:
14367 case VPRORDZ256mik:
14368 case VPRORDZ256mikz:
14369 case VPRORDZ256ri:
14370 case VPRORDZ256rik:
14371 case VPRORDZ256rikz:
14372 case VPRORDZmbi:
14373 case VPRORDZmbik:
14374 case VPRORDZmbikz:
14375 case VPRORDZmi:
14376 case VPRORDZmik:
14377 case VPRORDZmikz:
14378 case VPRORDZri:
14379 case VPRORDZrik:
14380 case VPRORDZrikz:
14381 return true;
14382 }
14383 return false;
14384}
14385
14386bool isVSUBSS(unsigned Opcode) {
14387 switch (Opcode) {
14388 case VSUBSSZrm_Int:
14389 case VSUBSSZrmk_Int:
14390 case VSUBSSZrmkz_Int:
14391 case VSUBSSZrr_Int:
14392 case VSUBSSZrrb_Int:
14393 case VSUBSSZrrbk_Int:
14394 case VSUBSSZrrbkz_Int:
14395 case VSUBSSZrrk_Int:
14396 case VSUBSSZrrkz_Int:
14397 case VSUBSSrm_Int:
14398 case VSUBSSrr_Int:
14399 return true;
14400 }
14401 return false;
14402}
14403
14404bool isPUSHFQ(unsigned Opcode) {
14405 return Opcode == PUSHF64;
14406}
14407
14408bool isVCVTHF82PH(unsigned Opcode) {
14409 switch (Opcode) {
14410 case VCVTHF82PHZ128rm:
14411 case VCVTHF82PHZ128rmk:
14412 case VCVTHF82PHZ128rmkz:
14413 case VCVTHF82PHZ128rr:
14414 case VCVTHF82PHZ128rrk:
14415 case VCVTHF82PHZ128rrkz:
14416 case VCVTHF82PHZ256rm:
14417 case VCVTHF82PHZ256rmk:
14418 case VCVTHF82PHZ256rmkz:
14419 case VCVTHF82PHZ256rr:
14420 case VCVTHF82PHZ256rrk:
14421 case VCVTHF82PHZ256rrkz:
14422 case VCVTHF82PHZrm:
14423 case VCVTHF82PHZrmk:
14424 case VCVTHF82PHZrmkz:
14425 case VCVTHF82PHZrr:
14426 case VCVTHF82PHZrrk:
14427 case VCVTHF82PHZrrkz:
14428 return true;
14429 }
14430 return false;
14431}
14432
14433bool isVPCLMULQDQ(unsigned Opcode) {
14434 switch (Opcode) {
14435 case VPCLMULQDQYrmi:
14436 case VPCLMULQDQYrri:
14437 case VPCLMULQDQZ128rmi:
14438 case VPCLMULQDQZ128rri:
14439 case VPCLMULQDQZ256rmi:
14440 case VPCLMULQDQZ256rri:
14441 case VPCLMULQDQZrmi:
14442 case VPCLMULQDQZrri:
14443 case VPCLMULQDQrmi:
14444 case VPCLMULQDQrri:
14445 return true;
14446 }
14447 return false;
14448}
14449
14450bool isVPADDUSB(unsigned Opcode) {
14451 switch (Opcode) {
14452 case VPADDUSBYrm:
14453 case VPADDUSBYrr:
14454 case VPADDUSBZ128rm:
14455 case VPADDUSBZ128rmk:
14456 case VPADDUSBZ128rmkz:
14457 case VPADDUSBZ128rr:
14458 case VPADDUSBZ128rrk:
14459 case VPADDUSBZ128rrkz:
14460 case VPADDUSBZ256rm:
14461 case VPADDUSBZ256rmk:
14462 case VPADDUSBZ256rmkz:
14463 case VPADDUSBZ256rr:
14464 case VPADDUSBZ256rrk:
14465 case VPADDUSBZ256rrkz:
14466 case VPADDUSBZrm:
14467 case VPADDUSBZrmk:
14468 case VPADDUSBZrmkz:
14469 case VPADDUSBZrr:
14470 case VPADDUSBZrrk:
14471 case VPADDUSBZrrkz:
14472 case VPADDUSBrm:
14473 case VPADDUSBrr:
14474 return true;
14475 }
14476 return false;
14477}
14478
14479bool isVPCMPD(unsigned Opcode) {
14480 switch (Opcode) {
14481 case VPCMPDZ128rmbi:
14482 case VPCMPDZ128rmbik:
14483 case VPCMPDZ128rmi:
14484 case VPCMPDZ128rmik:
14485 case VPCMPDZ128rri:
14486 case VPCMPDZ128rrik:
14487 case VPCMPDZ256rmbi:
14488 case VPCMPDZ256rmbik:
14489 case VPCMPDZ256rmi:
14490 case VPCMPDZ256rmik:
14491 case VPCMPDZ256rri:
14492 case VPCMPDZ256rrik:
14493 case VPCMPDZrmbi:
14494 case VPCMPDZrmbik:
14495 case VPCMPDZrmi:
14496 case VPCMPDZrmik:
14497 case VPCMPDZrri:
14498 case VPCMPDZrrik:
14499 return true;
14500 }
14501 return false;
14502}
14503
14504bool isMOVSD(unsigned Opcode) {
14505 switch (Opcode) {
14506 case MOVSDmr:
14507 case MOVSDrm:
14508 case MOVSDrr:
14509 case MOVSDrr_REV:
14510 case MOVSL:
14511 return true;
14512 }
14513 return false;
14514}
14515
14516bool isPSUBUSW(unsigned Opcode) {
14517 switch (Opcode) {
14518 case MMX_PSUBUSWrm:
14519 case MMX_PSUBUSWrr:
14520 case PSUBUSWrm:
14521 case PSUBUSWrr:
14522 return true;
14523 }
14524 return false;
14525}
14526
14527bool isVFMSUBADD132PS(unsigned Opcode) {
14528 switch (Opcode) {
14529 case VFMSUBADD132PSYm:
14530 case VFMSUBADD132PSYr:
14531 case VFMSUBADD132PSZ128m:
14532 case VFMSUBADD132PSZ128mb:
14533 case VFMSUBADD132PSZ128mbk:
14534 case VFMSUBADD132PSZ128mbkz:
14535 case VFMSUBADD132PSZ128mk:
14536 case VFMSUBADD132PSZ128mkz:
14537 case VFMSUBADD132PSZ128r:
14538 case VFMSUBADD132PSZ128rk:
14539 case VFMSUBADD132PSZ128rkz:
14540 case VFMSUBADD132PSZ256m:
14541 case VFMSUBADD132PSZ256mb:
14542 case VFMSUBADD132PSZ256mbk:
14543 case VFMSUBADD132PSZ256mbkz:
14544 case VFMSUBADD132PSZ256mk:
14545 case VFMSUBADD132PSZ256mkz:
14546 case VFMSUBADD132PSZ256r:
14547 case VFMSUBADD132PSZ256rk:
14548 case VFMSUBADD132PSZ256rkz:
14549 case VFMSUBADD132PSZm:
14550 case VFMSUBADD132PSZmb:
14551 case VFMSUBADD132PSZmbk:
14552 case VFMSUBADD132PSZmbkz:
14553 case VFMSUBADD132PSZmk:
14554 case VFMSUBADD132PSZmkz:
14555 case VFMSUBADD132PSZr:
14556 case VFMSUBADD132PSZrb:
14557 case VFMSUBADD132PSZrbk:
14558 case VFMSUBADD132PSZrbkz:
14559 case VFMSUBADD132PSZrk:
14560 case VFMSUBADD132PSZrkz:
14561 case VFMSUBADD132PSm:
14562 case VFMSUBADD132PSr:
14563 return true;
14564 }
14565 return false;
14566}
14567
14568bool isMOVMSKPS(unsigned Opcode) {
14569 return Opcode == MOVMSKPSrr;
14570}
14571
14572bool isVFIXUPIMMSS(unsigned Opcode) {
14573 switch (Opcode) {
14574 case VFIXUPIMMSSZrmi:
14575 case VFIXUPIMMSSZrmik:
14576 case VFIXUPIMMSSZrmikz:
14577 case VFIXUPIMMSSZrri:
14578 case VFIXUPIMMSSZrrib:
14579 case VFIXUPIMMSSZrribk:
14580 case VFIXUPIMMSSZrribkz:
14581 case VFIXUPIMMSSZrrik:
14582 case VFIXUPIMMSSZrrikz:
14583 return true;
14584 }
14585 return false;
14586}
14587
14588bool isMFENCE(unsigned Opcode) {
14589 return Opcode == MFENCE;
14590}
14591
14592bool isFTST(unsigned Opcode) {
14593 return Opcode == TST_F;
14594}
14595
14596bool isVPMADDWD(unsigned Opcode) {
14597 switch (Opcode) {
14598 case VPMADDWDYrm:
14599 case VPMADDWDYrr:
14600 case VPMADDWDZ128rm:
14601 case VPMADDWDZ128rmk:
14602 case VPMADDWDZ128rmkz:
14603 case VPMADDWDZ128rr:
14604 case VPMADDWDZ128rrk:
14605 case VPMADDWDZ128rrkz:
14606 case VPMADDWDZ256rm:
14607 case VPMADDWDZ256rmk:
14608 case VPMADDWDZ256rmkz:
14609 case VPMADDWDZ256rr:
14610 case VPMADDWDZ256rrk:
14611 case VPMADDWDZ256rrkz:
14612 case VPMADDWDZrm:
14613 case VPMADDWDZrmk:
14614 case VPMADDWDZrmkz:
14615 case VPMADDWDZrr:
14616 case VPMADDWDZrrk:
14617 case VPMADDWDZrrkz:
14618 case VPMADDWDrm:
14619 case VPMADDWDrr:
14620 return true;
14621 }
14622 return false;
14623}
14624
14625bool isPOP(unsigned Opcode) {
14626 switch (Opcode) {
14627 case POP16r:
14628 case POP16rmm:
14629 case POP16rmr:
14630 case POP32r:
14631 case POP32rmm:
14632 case POP32rmr:
14633 case POP64r:
14634 case POP64rmm:
14635 case POP64rmr:
14636 case POPDS16:
14637 case POPDS32:
14638 case POPES16:
14639 case POPES32:
14640 case POPFS16:
14641 case POPFS32:
14642 case POPFS64:
14643 case POPGS16:
14644 case POPGS32:
14645 case POPGS64:
14646 case POPSS16:
14647 case POPSS32:
14648 return true;
14649 }
14650 return false;
14651}
14652
14653bool isPSUBW(unsigned Opcode) {
14654 switch (Opcode) {
14655 case MMX_PSUBWrm:
14656 case MMX_PSUBWrr:
14657 case PSUBWrm:
14658 case PSUBWrr:
14659 return true;
14660 }
14661 return false;
14662}
14663
14664bool isBSWAP(unsigned Opcode) {
14665 switch (Opcode) {
14666 case BSWAP16r_BAD:
14667 case BSWAP32r:
14668 case BSWAP64r:
14669 return true;
14670 }
14671 return false;
14672}
14673
14674bool isPFMIN(unsigned Opcode) {
14675 switch (Opcode) {
14676 case PFMINrm:
14677 case PFMINrr:
14678 return true;
14679 }
14680 return false;
14681}
14682
14683bool isVFPCLASSPD(unsigned Opcode) {
14684 switch (Opcode) {
14685 case VFPCLASSPDZ128mbi:
14686 case VFPCLASSPDZ128mbik:
14687 case VFPCLASSPDZ128mi:
14688 case VFPCLASSPDZ128mik:
14689 case VFPCLASSPDZ128ri:
14690 case VFPCLASSPDZ128rik:
14691 case VFPCLASSPDZ256mbi:
14692 case VFPCLASSPDZ256mbik:
14693 case VFPCLASSPDZ256mi:
14694 case VFPCLASSPDZ256mik:
14695 case VFPCLASSPDZ256ri:
14696 case VFPCLASSPDZ256rik:
14697 case VFPCLASSPDZmbi:
14698 case VFPCLASSPDZmbik:
14699 case VFPCLASSPDZmi:
14700 case VFPCLASSPDZmik:
14701 case VFPCLASSPDZri:
14702 case VFPCLASSPDZrik:
14703 return true;
14704 }
14705 return false;
14706}
14707
14708bool isVPSHRDVD(unsigned Opcode) {
14709 switch (Opcode) {
14710 case VPSHRDVDZ128m:
14711 case VPSHRDVDZ128mb:
14712 case VPSHRDVDZ128mbk:
14713 case VPSHRDVDZ128mbkz:
14714 case VPSHRDVDZ128mk:
14715 case VPSHRDVDZ128mkz:
14716 case VPSHRDVDZ128r:
14717 case VPSHRDVDZ128rk:
14718 case VPSHRDVDZ128rkz:
14719 case VPSHRDVDZ256m:
14720 case VPSHRDVDZ256mb:
14721 case VPSHRDVDZ256mbk:
14722 case VPSHRDVDZ256mbkz:
14723 case VPSHRDVDZ256mk:
14724 case VPSHRDVDZ256mkz:
14725 case VPSHRDVDZ256r:
14726 case VPSHRDVDZ256rk:
14727 case VPSHRDVDZ256rkz:
14728 case VPSHRDVDZm:
14729 case VPSHRDVDZmb:
14730 case VPSHRDVDZmbk:
14731 case VPSHRDVDZmbkz:
14732 case VPSHRDVDZmk:
14733 case VPSHRDVDZmkz:
14734 case VPSHRDVDZr:
14735 case VPSHRDVDZrk:
14736 case VPSHRDVDZrkz:
14737 return true;
14738 }
14739 return false;
14740}
14741
14742bool isPADDW(unsigned Opcode) {
14743 switch (Opcode) {
14744 case MMX_PADDWrm:
14745 case MMX_PADDWrr:
14746 case PADDWrm:
14747 case PADDWrr:
14748 return true;
14749 }
14750 return false;
14751}
14752
14753bool isCVTSI2SD(unsigned Opcode) {
14754 switch (Opcode) {
14755 case CVTSI2SDrm_Int:
14756 case CVTSI2SDrr_Int:
14757 case CVTSI642SDrm_Int:
14758 case CVTSI642SDrr_Int:
14759 return true;
14760 }
14761 return false;
14762}
14763
14764bool isENQCMD(unsigned Opcode) {
14765 switch (Opcode) {
14766 case ENQCMD16:
14767 case ENQCMD32:
14768 case ENQCMD32_EVEX:
14769 case ENQCMD64:
14770 case ENQCMD64_EVEX:
14771 return true;
14772 }
14773 return false;
14774}
14775
14776bool isXSHA1(unsigned Opcode) {
14777 return Opcode == XSHA1;
14778}
14779
14780bool isVFNMADD132SD(unsigned Opcode) {
14781 switch (Opcode) {
14782 case VFNMADD132SDZm_Int:
14783 case VFNMADD132SDZmk_Int:
14784 case VFNMADD132SDZmkz_Int:
14785 case VFNMADD132SDZr_Int:
14786 case VFNMADD132SDZrb_Int:
14787 case VFNMADD132SDZrbk_Int:
14788 case VFNMADD132SDZrbkz_Int:
14789 case VFNMADD132SDZrk_Int:
14790 case VFNMADD132SDZrkz_Int:
14791 case VFNMADD132SDm_Int:
14792 case VFNMADD132SDr_Int:
14793 return true;
14794 }
14795 return false;
14796}
14797
14798bool isMOVZX(unsigned Opcode) {
14799 switch (Opcode) {
14800 case MOVZX16rm16:
14801 case MOVZX16rm8:
14802 case MOVZX16rr16:
14803 case MOVZX16rr8:
14804 case MOVZX32rm16:
14805 case MOVZX32rm8:
14806 case MOVZX32rr16:
14807 case MOVZX32rr8:
14808 case MOVZX64rm16:
14809 case MOVZX64rm8:
14810 case MOVZX64rr16:
14811 case MOVZX64rr8:
14812 return true;
14813 }
14814 return false;
14815}
14816
14817bool isVFIXUPIMMSD(unsigned Opcode) {
14818 switch (Opcode) {
14819 case VFIXUPIMMSDZrmi:
14820 case VFIXUPIMMSDZrmik:
14821 case VFIXUPIMMSDZrmikz:
14822 case VFIXUPIMMSDZrri:
14823 case VFIXUPIMMSDZrrib:
14824 case VFIXUPIMMSDZrribk:
14825 case VFIXUPIMMSDZrribkz:
14826 case VFIXUPIMMSDZrrik:
14827 case VFIXUPIMMSDZrrikz:
14828 return true;
14829 }
14830 return false;
14831}
14832
14833bool isINVD(unsigned Opcode) {
14834 return Opcode == INVD;
14835}
14836
14837bool isVFIXUPIMMPS(unsigned Opcode) {
14838 switch (Opcode) {
14839 case VFIXUPIMMPSZ128rmbi:
14840 case VFIXUPIMMPSZ128rmbik:
14841 case VFIXUPIMMPSZ128rmbikz:
14842 case VFIXUPIMMPSZ128rmi:
14843 case VFIXUPIMMPSZ128rmik:
14844 case VFIXUPIMMPSZ128rmikz:
14845 case VFIXUPIMMPSZ128rri:
14846 case VFIXUPIMMPSZ128rrik:
14847 case VFIXUPIMMPSZ128rrikz:
14848 case VFIXUPIMMPSZ256rmbi:
14849 case VFIXUPIMMPSZ256rmbik:
14850 case VFIXUPIMMPSZ256rmbikz:
14851 case VFIXUPIMMPSZ256rmi:
14852 case VFIXUPIMMPSZ256rmik:
14853 case VFIXUPIMMPSZ256rmikz:
14854 case VFIXUPIMMPSZ256rri:
14855 case VFIXUPIMMPSZ256rrik:
14856 case VFIXUPIMMPSZ256rrikz:
14857 case VFIXUPIMMPSZrmbi:
14858 case VFIXUPIMMPSZrmbik:
14859 case VFIXUPIMMPSZrmbikz:
14860 case VFIXUPIMMPSZrmi:
14861 case VFIXUPIMMPSZrmik:
14862 case VFIXUPIMMPSZrmikz:
14863 case VFIXUPIMMPSZrri:
14864 case VFIXUPIMMPSZrrib:
14865 case VFIXUPIMMPSZrribk:
14866 case VFIXUPIMMPSZrribkz:
14867 case VFIXUPIMMPSZrrik:
14868 case VFIXUPIMMPSZrrikz:
14869 return true;
14870 }
14871 return false;
14872}
14873
14874bool isMOVDQU(unsigned Opcode) {
14875 switch (Opcode) {
14876 case MOVDQUmr:
14877 case MOVDQUrm:
14878 case MOVDQUrr:
14879 case MOVDQUrr_REV:
14880 return true;
14881 }
14882 return false;
14883}
14884
14885bool isVFPCLASSPS(unsigned Opcode) {
14886 switch (Opcode) {
14887 case VFPCLASSPSZ128mbi:
14888 case VFPCLASSPSZ128mbik:
14889 case VFPCLASSPSZ128mi:
14890 case VFPCLASSPSZ128mik:
14891 case VFPCLASSPSZ128ri:
14892 case VFPCLASSPSZ128rik:
14893 case VFPCLASSPSZ256mbi:
14894 case VFPCLASSPSZ256mbik:
14895 case VFPCLASSPSZ256mi:
14896 case VFPCLASSPSZ256mik:
14897 case VFPCLASSPSZ256ri:
14898 case VFPCLASSPSZ256rik:
14899 case VFPCLASSPSZmbi:
14900 case VFPCLASSPSZmbik:
14901 case VFPCLASSPSZmi:
14902 case VFPCLASSPSZmik:
14903 case VFPCLASSPSZri:
14904 case VFPCLASSPSZrik:
14905 return true;
14906 }
14907 return false;
14908}
14909
14910bool isVPERMILPS(unsigned Opcode) {
14911 switch (Opcode) {
14912 case VPERMILPSYmi:
14913 case VPERMILPSYri:
14914 case VPERMILPSYrm:
14915 case VPERMILPSYrr:
14916 case VPERMILPSZ128mbi:
14917 case VPERMILPSZ128mbik:
14918 case VPERMILPSZ128mbikz:
14919 case VPERMILPSZ128mi:
14920 case VPERMILPSZ128mik:
14921 case VPERMILPSZ128mikz:
14922 case VPERMILPSZ128ri:
14923 case VPERMILPSZ128rik:
14924 case VPERMILPSZ128rikz:
14925 case VPERMILPSZ128rm:
14926 case VPERMILPSZ128rmb:
14927 case VPERMILPSZ128rmbk:
14928 case VPERMILPSZ128rmbkz:
14929 case VPERMILPSZ128rmk:
14930 case VPERMILPSZ128rmkz:
14931 case VPERMILPSZ128rr:
14932 case VPERMILPSZ128rrk:
14933 case VPERMILPSZ128rrkz:
14934 case VPERMILPSZ256mbi:
14935 case VPERMILPSZ256mbik:
14936 case VPERMILPSZ256mbikz:
14937 case VPERMILPSZ256mi:
14938 case VPERMILPSZ256mik:
14939 case VPERMILPSZ256mikz:
14940 case VPERMILPSZ256ri:
14941 case VPERMILPSZ256rik:
14942 case VPERMILPSZ256rikz:
14943 case VPERMILPSZ256rm:
14944 case VPERMILPSZ256rmb:
14945 case VPERMILPSZ256rmbk:
14946 case VPERMILPSZ256rmbkz:
14947 case VPERMILPSZ256rmk:
14948 case VPERMILPSZ256rmkz:
14949 case VPERMILPSZ256rr:
14950 case VPERMILPSZ256rrk:
14951 case VPERMILPSZ256rrkz:
14952 case VPERMILPSZmbi:
14953 case VPERMILPSZmbik:
14954 case VPERMILPSZmbikz:
14955 case VPERMILPSZmi:
14956 case VPERMILPSZmik:
14957 case VPERMILPSZmikz:
14958 case VPERMILPSZri:
14959 case VPERMILPSZrik:
14960 case VPERMILPSZrikz:
14961 case VPERMILPSZrm:
14962 case VPERMILPSZrmb:
14963 case VPERMILPSZrmbk:
14964 case VPERMILPSZrmbkz:
14965 case VPERMILPSZrmk:
14966 case VPERMILPSZrmkz:
14967 case VPERMILPSZrr:
14968 case VPERMILPSZrrk:
14969 case VPERMILPSZrrkz:
14970 case VPERMILPSmi:
14971 case VPERMILPSri:
14972 case VPERMILPSrm:
14973 case VPERMILPSrr:
14974 return true;
14975 }
14976 return false;
14977}
14978
14979bool isMOVSQ(unsigned Opcode) {
14980 return Opcode == MOVSQ;
14981}
14982
14983bool isAESDECWIDE128KL(unsigned Opcode) {
14984 return Opcode == AESDECWIDE128KL;
14985}
14986
14987bool isROUNDSS(unsigned Opcode) {
14988 switch (Opcode) {
14989 case ROUNDSSmi_Int:
14990 case ROUNDSSri_Int:
14991 return true;
14992 }
14993 return false;
14994}
14995
14996bool isVPMOVW2M(unsigned Opcode) {
14997 switch (Opcode) {
14998 case VPMOVW2MZ128kr:
14999 case VPMOVW2MZ256kr:
15000 case VPMOVW2MZkr:
15001 return true;
15002 }
15003 return false;
15004}
15005
15006bool isVPSHUFB(unsigned Opcode) {
15007 switch (Opcode) {
15008 case VPSHUFBYrm:
15009 case VPSHUFBYrr:
15010 case VPSHUFBZ128rm:
15011 case VPSHUFBZ128rmk:
15012 case VPSHUFBZ128rmkz:
15013 case VPSHUFBZ128rr:
15014 case VPSHUFBZ128rrk:
15015 case VPSHUFBZ128rrkz:
15016 case VPSHUFBZ256rm:
15017 case VPSHUFBZ256rmk:
15018 case VPSHUFBZ256rmkz:
15019 case VPSHUFBZ256rr:
15020 case VPSHUFBZ256rrk:
15021 case VPSHUFBZ256rrkz:
15022 case VPSHUFBZrm:
15023 case VPSHUFBZrmk:
15024 case VPSHUFBZrmkz:
15025 case VPSHUFBZrr:
15026 case VPSHUFBZrrk:
15027 case VPSHUFBZrrkz:
15028 case VPSHUFBrm:
15029 case VPSHUFBrr:
15030 return true;
15031 }
15032 return false;
15033}
15034
15035bool isVMULSD(unsigned Opcode) {
15036 switch (Opcode) {
15037 case VMULSDZrm_Int:
15038 case VMULSDZrmk_Int:
15039 case VMULSDZrmkz_Int:
15040 case VMULSDZrr_Int:
15041 case VMULSDZrrb_Int:
15042 case VMULSDZrrbk_Int:
15043 case VMULSDZrrbkz_Int:
15044 case VMULSDZrrk_Int:
15045 case VMULSDZrrkz_Int:
15046 case VMULSDrm_Int:
15047 case VMULSDrr_Int:
15048 return true;
15049 }
15050 return false;
15051}
15052
15053bool isVPERMI2W(unsigned Opcode) {
15054 switch (Opcode) {
15055 case VPERMI2WZ128rm:
15056 case VPERMI2WZ128rmk:
15057 case VPERMI2WZ128rmkz:
15058 case VPERMI2WZ128rr:
15059 case VPERMI2WZ128rrk:
15060 case VPERMI2WZ128rrkz:
15061 case VPERMI2WZ256rm:
15062 case VPERMI2WZ256rmk:
15063 case VPERMI2WZ256rmkz:
15064 case VPERMI2WZ256rr:
15065 case VPERMI2WZ256rrk:
15066 case VPERMI2WZ256rrkz:
15067 case VPERMI2WZrm:
15068 case VPERMI2WZrmk:
15069 case VPERMI2WZrmkz:
15070 case VPERMI2WZrr:
15071 case VPERMI2WZrrk:
15072 case VPERMI2WZrrkz:
15073 return true;
15074 }
15075 return false;
15076}
15077
15078bool isVREDUCESS(unsigned Opcode) {
15079 switch (Opcode) {
15080 case VREDUCESSZrmi:
15081 case VREDUCESSZrmik:
15082 case VREDUCESSZrmikz:
15083 case VREDUCESSZrri:
15084 case VREDUCESSZrrib:
15085 case VREDUCESSZrribk:
15086 case VREDUCESSZrribkz:
15087 case VREDUCESSZrrik:
15088 case VREDUCESSZrrikz:
15089 return true;
15090 }
15091 return false;
15092}
15093
15094bool isFST(unsigned Opcode) {
15095 switch (Opcode) {
15096 case ST_F32m:
15097 case ST_F64m:
15098 case ST_Frr:
15099 return true;
15100 }
15101 return false;
15102}
15103
15104bool isVPHSUBW(unsigned Opcode) {
15105 switch (Opcode) {
15106 case VPHSUBWYrm:
15107 case VPHSUBWYrr:
15108 case VPHSUBWrm:
15109 case VPHSUBWrr:
15110 return true;
15111 }
15112 return false;
15113}
15114
15115bool isFRNDINT(unsigned Opcode) {
15116 return Opcode == FRNDINT;
15117}
15118
15119bool isSHR(unsigned Opcode) {
15120 switch (Opcode) {
15121 case SHR16m1:
15122 case SHR16m1_EVEX:
15123 case SHR16m1_ND:
15124 case SHR16m1_NF:
15125 case SHR16m1_NF_ND:
15126 case SHR16mCL:
15127 case SHR16mCL_EVEX:
15128 case SHR16mCL_ND:
15129 case SHR16mCL_NF:
15130 case SHR16mCL_NF_ND:
15131 case SHR16mi:
15132 case SHR16mi_EVEX:
15133 case SHR16mi_ND:
15134 case SHR16mi_NF:
15135 case SHR16mi_NF_ND:
15136 case SHR16r1:
15137 case SHR16r1_EVEX:
15138 case SHR16r1_ND:
15139 case SHR16r1_NF:
15140 case SHR16r1_NF_ND:
15141 case SHR16rCL:
15142 case SHR16rCL_EVEX:
15143 case SHR16rCL_ND:
15144 case SHR16rCL_NF:
15145 case SHR16rCL_NF_ND:
15146 case SHR16ri:
15147 case SHR16ri_EVEX:
15148 case SHR16ri_ND:
15149 case SHR16ri_NF:
15150 case SHR16ri_NF_ND:
15151 case SHR32m1:
15152 case SHR32m1_EVEX:
15153 case SHR32m1_ND:
15154 case SHR32m1_NF:
15155 case SHR32m1_NF_ND:
15156 case SHR32mCL:
15157 case SHR32mCL_EVEX:
15158 case SHR32mCL_ND:
15159 case SHR32mCL_NF:
15160 case SHR32mCL_NF_ND:
15161 case SHR32mi:
15162 case SHR32mi_EVEX:
15163 case SHR32mi_ND:
15164 case SHR32mi_NF:
15165 case SHR32mi_NF_ND:
15166 case SHR32r1:
15167 case SHR32r1_EVEX:
15168 case SHR32r1_ND:
15169 case SHR32r1_NF:
15170 case SHR32r1_NF_ND:
15171 case SHR32rCL:
15172 case SHR32rCL_EVEX:
15173 case SHR32rCL_ND:
15174 case SHR32rCL_NF:
15175 case SHR32rCL_NF_ND:
15176 case SHR32ri:
15177 case SHR32ri_EVEX:
15178 case SHR32ri_ND:
15179 case SHR32ri_NF:
15180 case SHR32ri_NF_ND:
15181 case SHR64m1:
15182 case SHR64m1_EVEX:
15183 case SHR64m1_ND:
15184 case SHR64m1_NF:
15185 case SHR64m1_NF_ND:
15186 case SHR64mCL:
15187 case SHR64mCL_EVEX:
15188 case SHR64mCL_ND:
15189 case SHR64mCL_NF:
15190 case SHR64mCL_NF_ND:
15191 case SHR64mi:
15192 case SHR64mi_EVEX:
15193 case SHR64mi_ND:
15194 case SHR64mi_NF:
15195 case SHR64mi_NF_ND:
15196 case SHR64r1:
15197 case SHR64r1_EVEX:
15198 case SHR64r1_ND:
15199 case SHR64r1_NF:
15200 case SHR64r1_NF_ND:
15201 case SHR64rCL:
15202 case SHR64rCL_EVEX:
15203 case SHR64rCL_ND:
15204 case SHR64rCL_NF:
15205 case SHR64rCL_NF_ND:
15206 case SHR64ri:
15207 case SHR64ri_EVEX:
15208 case SHR64ri_ND:
15209 case SHR64ri_NF:
15210 case SHR64ri_NF_ND:
15211 case SHR8m1:
15212 case SHR8m1_EVEX:
15213 case SHR8m1_ND:
15214 case SHR8m1_NF:
15215 case SHR8m1_NF_ND:
15216 case SHR8mCL:
15217 case SHR8mCL_EVEX:
15218 case SHR8mCL_ND:
15219 case SHR8mCL_NF:
15220 case SHR8mCL_NF_ND:
15221 case SHR8mi:
15222 case SHR8mi_EVEX:
15223 case SHR8mi_ND:
15224 case SHR8mi_NF:
15225 case SHR8mi_NF_ND:
15226 case SHR8r1:
15227 case SHR8r1_EVEX:
15228 case SHR8r1_ND:
15229 case SHR8r1_NF:
15230 case SHR8r1_NF_ND:
15231 case SHR8rCL:
15232 case SHR8rCL_EVEX:
15233 case SHR8rCL_ND:
15234 case SHR8rCL_NF:
15235 case SHR8rCL_NF_ND:
15236 case SHR8ri:
15237 case SHR8ri_EVEX:
15238 case SHR8ri_ND:
15239 case SHR8ri_NF:
15240 case SHR8ri_NF_ND:
15241 return true;
15242 }
15243 return false;
15244}
15245
15246bool isLOOPNE(unsigned Opcode) {
15247 return Opcode == LOOPNE;
15248}
15249
15250bool isVCVTTPH2UQQ(unsigned Opcode) {
15251 switch (Opcode) {
15252 case VCVTTPH2UQQZ128rm:
15253 case VCVTTPH2UQQZ128rmb:
15254 case VCVTTPH2UQQZ128rmbk:
15255 case VCVTTPH2UQQZ128rmbkz:
15256 case VCVTTPH2UQQZ128rmk:
15257 case VCVTTPH2UQQZ128rmkz:
15258 case VCVTTPH2UQQZ128rr:
15259 case VCVTTPH2UQQZ128rrk:
15260 case VCVTTPH2UQQZ128rrkz:
15261 case VCVTTPH2UQQZ256rm:
15262 case VCVTTPH2UQQZ256rmb:
15263 case VCVTTPH2UQQZ256rmbk:
15264 case VCVTTPH2UQQZ256rmbkz:
15265 case VCVTTPH2UQQZ256rmk:
15266 case VCVTTPH2UQQZ256rmkz:
15267 case VCVTTPH2UQQZ256rr:
15268 case VCVTTPH2UQQZ256rrk:
15269 case VCVTTPH2UQQZ256rrkz:
15270 case VCVTTPH2UQQZrm:
15271 case VCVTTPH2UQQZrmb:
15272 case VCVTTPH2UQQZrmbk:
15273 case VCVTTPH2UQQZrmbkz:
15274 case VCVTTPH2UQQZrmk:
15275 case VCVTTPH2UQQZrmkz:
15276 case VCVTTPH2UQQZrr:
15277 case VCVTTPH2UQQZrrb:
15278 case VCVTTPH2UQQZrrbk:
15279 case VCVTTPH2UQQZrrbkz:
15280 case VCVTTPH2UQQZrrk:
15281 case VCVTTPH2UQQZrrkz:
15282 return true;
15283 }
15284 return false;
15285}
15286
15287bool isSHA1NEXTE(unsigned Opcode) {
15288 switch (Opcode) {
15289 case SHA1NEXTErm:
15290 case SHA1NEXTErr:
15291 return true;
15292 }
15293 return false;
15294}
15295
15296bool isVFMADD132SD(unsigned Opcode) {
15297 switch (Opcode) {
15298 case VFMADD132SDZm_Int:
15299 case VFMADD132SDZmk_Int:
15300 case VFMADD132SDZmkz_Int:
15301 case VFMADD132SDZr_Int:
15302 case VFMADD132SDZrb_Int:
15303 case VFMADD132SDZrbk_Int:
15304 case VFMADD132SDZrbkz_Int:
15305 case VFMADD132SDZrk_Int:
15306 case VFMADD132SDZrkz_Int:
15307 case VFMADD132SDm_Int:
15308 case VFMADD132SDr_Int:
15309 return true;
15310 }
15311 return false;
15312}
15313
15314bool isPSRAW(unsigned Opcode) {
15315 switch (Opcode) {
15316 case MMX_PSRAWri:
15317 case MMX_PSRAWrm:
15318 case MMX_PSRAWrr:
15319 case PSRAWri:
15320 case PSRAWrm:
15321 case PSRAWrr:
15322 return true;
15323 }
15324 return false;
15325}
15326
15327bool isVPBROADCASTQ(unsigned Opcode) {
15328 switch (Opcode) {
15329 case VPBROADCASTQYrm:
15330 case VPBROADCASTQYrr:
15331 case VPBROADCASTQZ128rm:
15332 case VPBROADCASTQZ128rmk:
15333 case VPBROADCASTQZ128rmkz:
15334 case VPBROADCASTQZ128rr:
15335 case VPBROADCASTQZ128rrk:
15336 case VPBROADCASTQZ128rrkz:
15337 case VPBROADCASTQZ256rm:
15338 case VPBROADCASTQZ256rmk:
15339 case VPBROADCASTQZ256rmkz:
15340 case VPBROADCASTQZ256rr:
15341 case VPBROADCASTQZ256rrk:
15342 case VPBROADCASTQZ256rrkz:
15343 case VPBROADCASTQZrm:
15344 case VPBROADCASTQZrmk:
15345 case VPBROADCASTQZrmkz:
15346 case VPBROADCASTQZrr:
15347 case VPBROADCASTQZrrk:
15348 case VPBROADCASTQZrrkz:
15349 case VPBROADCASTQrZ128rr:
15350 case VPBROADCASTQrZ128rrk:
15351 case VPBROADCASTQrZ128rrkz:
15352 case VPBROADCASTQrZ256rr:
15353 case VPBROADCASTQrZ256rrk:
15354 case VPBROADCASTQrZ256rrkz:
15355 case VPBROADCASTQrZrr:
15356 case VPBROADCASTQrZrrk:
15357 case VPBROADCASTQrZrrkz:
15358 case VPBROADCASTQrm:
15359 case VPBROADCASTQrr:
15360 return true;
15361 }
15362 return false;
15363}
15364
15365bool isCLC(unsigned Opcode) {
15366 return Opcode == CLC;
15367}
15368
15369bool isPOPAW(unsigned Opcode) {
15370 return Opcode == POPA16;
15371}
15372
15373bool isTCMMIMFP16PS(unsigned Opcode) {
15374 return Opcode == TCMMIMFP16PS;
15375}
15376
15377bool isVCVTQQ2PH(unsigned Opcode) {
15378 switch (Opcode) {
15379 case VCVTQQ2PHZ128rm:
15380 case VCVTQQ2PHZ128rmb:
15381 case VCVTQQ2PHZ128rmbk:
15382 case VCVTQQ2PHZ128rmbkz:
15383 case VCVTQQ2PHZ128rmk:
15384 case VCVTQQ2PHZ128rmkz:
15385 case VCVTQQ2PHZ128rr:
15386 case VCVTQQ2PHZ128rrk:
15387 case VCVTQQ2PHZ128rrkz:
15388 case VCVTQQ2PHZ256rm:
15389 case VCVTQQ2PHZ256rmb:
15390 case VCVTQQ2PHZ256rmbk:
15391 case VCVTQQ2PHZ256rmbkz:
15392 case VCVTQQ2PHZ256rmk:
15393 case VCVTQQ2PHZ256rmkz:
15394 case VCVTQQ2PHZ256rr:
15395 case VCVTQQ2PHZ256rrk:
15396 case VCVTQQ2PHZ256rrkz:
15397 case VCVTQQ2PHZrm:
15398 case VCVTQQ2PHZrmb:
15399 case VCVTQQ2PHZrmbk:
15400 case VCVTQQ2PHZrmbkz:
15401 case VCVTQQ2PHZrmk:
15402 case VCVTQQ2PHZrmkz:
15403 case VCVTQQ2PHZrr:
15404 case VCVTQQ2PHZrrb:
15405 case VCVTQQ2PHZrrbk:
15406 case VCVTQQ2PHZrrbkz:
15407 case VCVTQQ2PHZrrk:
15408 case VCVTQQ2PHZrrkz:
15409 return true;
15410 }
15411 return false;
15412}
15413
15414bool isVCVTTPS2UQQ(unsigned Opcode) {
15415 switch (Opcode) {
15416 case VCVTTPS2UQQZ128rm:
15417 case VCVTTPS2UQQZ128rmb:
15418 case VCVTTPS2UQQZ128rmbk:
15419 case VCVTTPS2UQQZ128rmbkz:
15420 case VCVTTPS2UQQZ128rmk:
15421 case VCVTTPS2UQQZ128rmkz:
15422 case VCVTTPS2UQQZ128rr:
15423 case VCVTTPS2UQQZ128rrk:
15424 case VCVTTPS2UQQZ128rrkz:
15425 case VCVTTPS2UQQZ256rm:
15426 case VCVTTPS2UQQZ256rmb:
15427 case VCVTTPS2UQQZ256rmbk:
15428 case VCVTTPS2UQQZ256rmbkz:
15429 case VCVTTPS2UQQZ256rmk:
15430 case VCVTTPS2UQQZ256rmkz:
15431 case VCVTTPS2UQQZ256rr:
15432 case VCVTTPS2UQQZ256rrk:
15433 case VCVTTPS2UQQZ256rrkz:
15434 case VCVTTPS2UQQZrm:
15435 case VCVTTPS2UQQZrmb:
15436 case VCVTTPS2UQQZrmbk:
15437 case VCVTTPS2UQQZrmbkz:
15438 case VCVTTPS2UQQZrmk:
15439 case VCVTTPS2UQQZrmkz:
15440 case VCVTTPS2UQQZrr:
15441 case VCVTTPS2UQQZrrb:
15442 case VCVTTPS2UQQZrrbk:
15443 case VCVTTPS2UQQZrrbkz:
15444 case VCVTTPS2UQQZrrk:
15445 case VCVTTPS2UQQZrrkz:
15446 return true;
15447 }
15448 return false;
15449}
15450
15451bool isVMOVUPD(unsigned Opcode) {
15452 switch (Opcode) {
15453 case VMOVUPDYmr:
15454 case VMOVUPDYrm:
15455 case VMOVUPDYrr:
15456 case VMOVUPDYrr_REV:
15457 case VMOVUPDZ128mr:
15458 case VMOVUPDZ128mrk:
15459 case VMOVUPDZ128rm:
15460 case VMOVUPDZ128rmk:
15461 case VMOVUPDZ128rmkz:
15462 case VMOVUPDZ128rr:
15463 case VMOVUPDZ128rr_REV:
15464 case VMOVUPDZ128rrk:
15465 case VMOVUPDZ128rrk_REV:
15466 case VMOVUPDZ128rrkz:
15467 case VMOVUPDZ128rrkz_REV:
15468 case VMOVUPDZ256mr:
15469 case VMOVUPDZ256mrk:
15470 case VMOVUPDZ256rm:
15471 case VMOVUPDZ256rmk:
15472 case VMOVUPDZ256rmkz:
15473 case VMOVUPDZ256rr:
15474 case VMOVUPDZ256rr_REV:
15475 case VMOVUPDZ256rrk:
15476 case VMOVUPDZ256rrk_REV:
15477 case VMOVUPDZ256rrkz:
15478 case VMOVUPDZ256rrkz_REV:
15479 case VMOVUPDZmr:
15480 case VMOVUPDZmrk:
15481 case VMOVUPDZrm:
15482 case VMOVUPDZrmk:
15483 case VMOVUPDZrmkz:
15484 case VMOVUPDZrr:
15485 case VMOVUPDZrr_REV:
15486 case VMOVUPDZrrk:
15487 case VMOVUPDZrrk_REV:
15488 case VMOVUPDZrrkz:
15489 case VMOVUPDZrrkz_REV:
15490 case VMOVUPDmr:
15491 case VMOVUPDrm:
15492 case VMOVUPDrr:
15493 case VMOVUPDrr_REV:
15494 return true;
15495 }
15496 return false;
15497}
15498
15499bool isFPTAN(unsigned Opcode) {
15500 return Opcode == FPTAN;
15501}
15502
15503bool isVMASKMOVPD(unsigned Opcode) {
15504 switch (Opcode) {
15505 case VMASKMOVPDYmr:
15506 case VMASKMOVPDYrm:
15507 case VMASKMOVPDmr:
15508 case VMASKMOVPDrm:
15509 return true;
15510 }
15511 return false;
15512}
15513
15514bool isVMOVLHPS(unsigned Opcode) {
15515 switch (Opcode) {
15516 case VMOVLHPSZrr:
15517 case VMOVLHPSrr:
15518 return true;
15519 }
15520 return false;
15521}
15522
15523bool isAESKEYGENASSIST(unsigned Opcode) {
15524 switch (Opcode) {
15525 case AESKEYGENASSISTrmi:
15526 case AESKEYGENASSISTrri:
15527 return true;
15528 }
15529 return false;
15530}
15531
15532bool isXSAVEOPT64(unsigned Opcode) {
15533 return Opcode == XSAVEOPT64;
15534}
15535
15536bool isXSAVEC(unsigned Opcode) {
15537 return Opcode == XSAVEC;
15538}
15539
15540bool isVPLZCNTQ(unsigned Opcode) {
15541 switch (Opcode) {
15542 case VPLZCNTQZ128rm:
15543 case VPLZCNTQZ128rmb:
15544 case VPLZCNTQZ128rmbk:
15545 case VPLZCNTQZ128rmbkz:
15546 case VPLZCNTQZ128rmk:
15547 case VPLZCNTQZ128rmkz:
15548 case VPLZCNTQZ128rr:
15549 case VPLZCNTQZ128rrk:
15550 case VPLZCNTQZ128rrkz:
15551 case VPLZCNTQZ256rm:
15552 case VPLZCNTQZ256rmb:
15553 case VPLZCNTQZ256rmbk:
15554 case VPLZCNTQZ256rmbkz:
15555 case VPLZCNTQZ256rmk:
15556 case VPLZCNTQZ256rmkz:
15557 case VPLZCNTQZ256rr:
15558 case VPLZCNTQZ256rrk:
15559 case VPLZCNTQZ256rrkz:
15560 case VPLZCNTQZrm:
15561 case VPLZCNTQZrmb:
15562 case VPLZCNTQZrmbk:
15563 case VPLZCNTQZrmbkz:
15564 case VPLZCNTQZrmk:
15565 case VPLZCNTQZrmkz:
15566 case VPLZCNTQZrr:
15567 case VPLZCNTQZrrk:
15568 case VPLZCNTQZrrkz:
15569 return true;
15570 }
15571 return false;
15572}
15573
15574bool isVPSUBW(unsigned Opcode) {
15575 switch (Opcode) {
15576 case VPSUBWYrm:
15577 case VPSUBWYrr:
15578 case VPSUBWZ128rm:
15579 case VPSUBWZ128rmk:
15580 case VPSUBWZ128rmkz:
15581 case VPSUBWZ128rr:
15582 case VPSUBWZ128rrk:
15583 case VPSUBWZ128rrkz:
15584 case VPSUBWZ256rm:
15585 case VPSUBWZ256rmk:
15586 case VPSUBWZ256rmkz:
15587 case VPSUBWZ256rr:
15588 case VPSUBWZ256rrk:
15589 case VPSUBWZ256rrkz:
15590 case VPSUBWZrm:
15591 case VPSUBWZrmk:
15592 case VPSUBWZrmkz:
15593 case VPSUBWZrr:
15594 case VPSUBWZrrk:
15595 case VPSUBWZrrkz:
15596 case VPSUBWrm:
15597 case VPSUBWrr:
15598 return true;
15599 }
15600 return false;
15601}
15602
15603bool isCMPCCXADD(unsigned Opcode) {
15604 switch (Opcode) {
15605 case CMPCCXADDmr32:
15606 case CMPCCXADDmr32_EVEX:
15607 case CMPCCXADDmr64:
15608 case CMPCCXADDmr64_EVEX:
15609 return true;
15610 }
15611 return false;
15612}
15613
15614bool isVFMSUBADD213PH(unsigned Opcode) {
15615 switch (Opcode) {
15616 case VFMSUBADD213PHZ128m:
15617 case VFMSUBADD213PHZ128mb:
15618 case VFMSUBADD213PHZ128mbk:
15619 case VFMSUBADD213PHZ128mbkz:
15620 case VFMSUBADD213PHZ128mk:
15621 case VFMSUBADD213PHZ128mkz:
15622 case VFMSUBADD213PHZ128r:
15623 case VFMSUBADD213PHZ128rk:
15624 case VFMSUBADD213PHZ128rkz:
15625 case VFMSUBADD213PHZ256m:
15626 case VFMSUBADD213PHZ256mb:
15627 case VFMSUBADD213PHZ256mbk:
15628 case VFMSUBADD213PHZ256mbkz:
15629 case VFMSUBADD213PHZ256mk:
15630 case VFMSUBADD213PHZ256mkz:
15631 case VFMSUBADD213PHZ256r:
15632 case VFMSUBADD213PHZ256rk:
15633 case VFMSUBADD213PHZ256rkz:
15634 case VFMSUBADD213PHZm:
15635 case VFMSUBADD213PHZmb:
15636 case VFMSUBADD213PHZmbk:
15637 case VFMSUBADD213PHZmbkz:
15638 case VFMSUBADD213PHZmk:
15639 case VFMSUBADD213PHZmkz:
15640 case VFMSUBADD213PHZr:
15641 case VFMSUBADD213PHZrb:
15642 case VFMSUBADD213PHZrbk:
15643 case VFMSUBADD213PHZrbkz:
15644 case VFMSUBADD213PHZrk:
15645 case VFMSUBADD213PHZrkz:
15646 return true;
15647 }
15648 return false;
15649}
15650
15651bool isVFMADDSUBPD(unsigned Opcode) {
15652 switch (Opcode) {
15653 case VFMADDSUBPD4Ymr:
15654 case VFMADDSUBPD4Yrm:
15655 case VFMADDSUBPD4Yrr:
15656 case VFMADDSUBPD4Yrr_REV:
15657 case VFMADDSUBPD4mr:
15658 case VFMADDSUBPD4rm:
15659 case VFMADDSUBPD4rr:
15660 case VFMADDSUBPD4rr_REV:
15661 return true;
15662 }
15663 return false;
15664}
15665
15666bool isVPMINSW(unsigned Opcode) {
15667 switch (Opcode) {
15668 case VPMINSWYrm:
15669 case VPMINSWYrr:
15670 case VPMINSWZ128rm:
15671 case VPMINSWZ128rmk:
15672 case VPMINSWZ128rmkz:
15673 case VPMINSWZ128rr:
15674 case VPMINSWZ128rrk:
15675 case VPMINSWZ128rrkz:
15676 case VPMINSWZ256rm:
15677 case VPMINSWZ256rmk:
15678 case VPMINSWZ256rmkz:
15679 case VPMINSWZ256rr:
15680 case VPMINSWZ256rrk:
15681 case VPMINSWZ256rrkz:
15682 case VPMINSWZrm:
15683 case VPMINSWZrmk:
15684 case VPMINSWZrmkz:
15685 case VPMINSWZrr:
15686 case VPMINSWZrrk:
15687 case VPMINSWZrrkz:
15688 case VPMINSWrm:
15689 case VPMINSWrr:
15690 return true;
15691 }
15692 return false;
15693}
15694
15695bool isVFNMSUB132PS(unsigned Opcode) {
15696 switch (Opcode) {
15697 case VFNMSUB132PSYm:
15698 case VFNMSUB132PSYr:
15699 case VFNMSUB132PSZ128m:
15700 case VFNMSUB132PSZ128mb:
15701 case VFNMSUB132PSZ128mbk:
15702 case VFNMSUB132PSZ128mbkz:
15703 case VFNMSUB132PSZ128mk:
15704 case VFNMSUB132PSZ128mkz:
15705 case VFNMSUB132PSZ128r:
15706 case VFNMSUB132PSZ128rk:
15707 case VFNMSUB132PSZ128rkz:
15708 case VFNMSUB132PSZ256m:
15709 case VFNMSUB132PSZ256mb:
15710 case VFNMSUB132PSZ256mbk:
15711 case VFNMSUB132PSZ256mbkz:
15712 case VFNMSUB132PSZ256mk:
15713 case VFNMSUB132PSZ256mkz:
15714 case VFNMSUB132PSZ256r:
15715 case VFNMSUB132PSZ256rk:
15716 case VFNMSUB132PSZ256rkz:
15717 case VFNMSUB132PSZm:
15718 case VFNMSUB132PSZmb:
15719 case VFNMSUB132PSZmbk:
15720 case VFNMSUB132PSZmbkz:
15721 case VFNMSUB132PSZmk:
15722 case VFNMSUB132PSZmkz:
15723 case VFNMSUB132PSZr:
15724 case VFNMSUB132PSZrb:
15725 case VFNMSUB132PSZrbk:
15726 case VFNMSUB132PSZrbkz:
15727 case VFNMSUB132PSZrk:
15728 case VFNMSUB132PSZrkz:
15729 case VFNMSUB132PSm:
15730 case VFNMSUB132PSr:
15731 return true;
15732 }
15733 return false;
15734}
15735
15736bool isVMOVAPS(unsigned Opcode) {
15737 switch (Opcode) {
15738 case VMOVAPSYmr:
15739 case VMOVAPSYrm:
15740 case VMOVAPSYrr:
15741 case VMOVAPSYrr_REV:
15742 case VMOVAPSZ128mr:
15743 case VMOVAPSZ128mrk:
15744 case VMOVAPSZ128rm:
15745 case VMOVAPSZ128rmk:
15746 case VMOVAPSZ128rmkz:
15747 case VMOVAPSZ128rr:
15748 case VMOVAPSZ128rr_REV:
15749 case VMOVAPSZ128rrk:
15750 case VMOVAPSZ128rrk_REV:
15751 case VMOVAPSZ128rrkz:
15752 case VMOVAPSZ128rrkz_REV:
15753 case VMOVAPSZ256mr:
15754 case VMOVAPSZ256mrk:
15755 case VMOVAPSZ256rm:
15756 case VMOVAPSZ256rmk:
15757 case VMOVAPSZ256rmkz:
15758 case VMOVAPSZ256rr:
15759 case VMOVAPSZ256rr_REV:
15760 case VMOVAPSZ256rrk:
15761 case VMOVAPSZ256rrk_REV:
15762 case VMOVAPSZ256rrkz:
15763 case VMOVAPSZ256rrkz_REV:
15764 case VMOVAPSZmr:
15765 case VMOVAPSZmrk:
15766 case VMOVAPSZrm:
15767 case VMOVAPSZrmk:
15768 case VMOVAPSZrmkz:
15769 case VMOVAPSZrr:
15770 case VMOVAPSZrr_REV:
15771 case VMOVAPSZrrk:
15772 case VMOVAPSZrrk_REV:
15773 case VMOVAPSZrrkz:
15774 case VMOVAPSZrrkz_REV:
15775 case VMOVAPSmr:
15776 case VMOVAPSrm:
15777 case VMOVAPSrr:
15778 case VMOVAPSrr_REV:
15779 return true;
15780 }
15781 return false;
15782}
15783
15784bool isVPEXTRQ(unsigned Opcode) {
15785 switch (Opcode) {
15786 case VPEXTRQZmri:
15787 case VPEXTRQZrri:
15788 case VPEXTRQmri:
15789 case VPEXTRQrri:
15790 return true;
15791 }
15792 return false;
15793}
15794
15795bool isVSCALEFSH(unsigned Opcode) {
15796 switch (Opcode) {
15797 case VSCALEFSHZrm:
15798 case VSCALEFSHZrmk:
15799 case VSCALEFSHZrmkz:
15800 case VSCALEFSHZrr:
15801 case VSCALEFSHZrrb_Int:
15802 case VSCALEFSHZrrbk_Int:
15803 case VSCALEFSHZrrbkz_Int:
15804 case VSCALEFSHZrrk:
15805 case VSCALEFSHZrrkz:
15806 return true;
15807 }
15808 return false;
15809}
15810
15811bool isVCVTPD2PS(unsigned Opcode) {
15812 switch (Opcode) {
15813 case VCVTPD2PSYrm:
15814 case VCVTPD2PSYrr:
15815 case VCVTPD2PSZ128rm:
15816 case VCVTPD2PSZ128rmb:
15817 case VCVTPD2PSZ128rmbk:
15818 case VCVTPD2PSZ128rmbkz:
15819 case VCVTPD2PSZ128rmk:
15820 case VCVTPD2PSZ128rmkz:
15821 case VCVTPD2PSZ128rr:
15822 case VCVTPD2PSZ128rrk:
15823 case VCVTPD2PSZ128rrkz:
15824 case VCVTPD2PSZ256rm:
15825 case VCVTPD2PSZ256rmb:
15826 case VCVTPD2PSZ256rmbk:
15827 case VCVTPD2PSZ256rmbkz:
15828 case VCVTPD2PSZ256rmk:
15829 case VCVTPD2PSZ256rmkz:
15830 case VCVTPD2PSZ256rr:
15831 case VCVTPD2PSZ256rrk:
15832 case VCVTPD2PSZ256rrkz:
15833 case VCVTPD2PSZrm:
15834 case VCVTPD2PSZrmb:
15835 case VCVTPD2PSZrmbk:
15836 case VCVTPD2PSZrmbkz:
15837 case VCVTPD2PSZrmk:
15838 case VCVTPD2PSZrmkz:
15839 case VCVTPD2PSZrr:
15840 case VCVTPD2PSZrrb:
15841 case VCVTPD2PSZrrbk:
15842 case VCVTPD2PSZrrbkz:
15843 case VCVTPD2PSZrrk:
15844 case VCVTPD2PSZrrkz:
15845 case VCVTPD2PSrm:
15846 case VCVTPD2PSrr:
15847 return true;
15848 }
15849 return false;
15850}
15851
15852bool isCLGI(unsigned Opcode) {
15853 return Opcode == CLGI;
15854}
15855
15856bool isVAESDEC(unsigned Opcode) {
15857 switch (Opcode) {
15858 case VAESDECYrm:
15859 case VAESDECYrr:
15860 case VAESDECZ128rm:
15861 case VAESDECZ128rr:
15862 case VAESDECZ256rm:
15863 case VAESDECZ256rr:
15864 case VAESDECZrm:
15865 case VAESDECZrr:
15866 case VAESDECrm:
15867 case VAESDECrr:
15868 return true;
15869 }
15870 return false;
15871}
15872
15873bool isPFMUL(unsigned Opcode) {
15874 switch (Opcode) {
15875 case PFMULrm:
15876 case PFMULrr:
15877 return true;
15878 }
15879 return false;
15880}
15881
15882bool isVCVTBIASPH2BF8S(unsigned Opcode) {
15883 switch (Opcode) {
15884 case VCVTBIASPH2BF8SZ128rm:
15885 case VCVTBIASPH2BF8SZ128rmb:
15886 case VCVTBIASPH2BF8SZ128rmbk:
15887 case VCVTBIASPH2BF8SZ128rmbkz:
15888 case VCVTBIASPH2BF8SZ128rmk:
15889 case VCVTBIASPH2BF8SZ128rmkz:
15890 case VCVTBIASPH2BF8SZ128rr:
15891 case VCVTBIASPH2BF8SZ128rrk:
15892 case VCVTBIASPH2BF8SZ128rrkz:
15893 case VCVTBIASPH2BF8SZ256rm:
15894 case VCVTBIASPH2BF8SZ256rmb:
15895 case VCVTBIASPH2BF8SZ256rmbk:
15896 case VCVTBIASPH2BF8SZ256rmbkz:
15897 case VCVTBIASPH2BF8SZ256rmk:
15898 case VCVTBIASPH2BF8SZ256rmkz:
15899 case VCVTBIASPH2BF8SZ256rr:
15900 case VCVTBIASPH2BF8SZ256rrk:
15901 case VCVTBIASPH2BF8SZ256rrkz:
15902 case VCVTBIASPH2BF8SZrm:
15903 case VCVTBIASPH2BF8SZrmb:
15904 case VCVTBIASPH2BF8SZrmbk:
15905 case VCVTBIASPH2BF8SZrmbkz:
15906 case VCVTBIASPH2BF8SZrmk:
15907 case VCVTBIASPH2BF8SZrmkz:
15908 case VCVTBIASPH2BF8SZrr:
15909 case VCVTBIASPH2BF8SZrrk:
15910 case VCVTBIASPH2BF8SZrrkz:
15911 return true;
15912 }
15913 return false;
15914}
15915
15916bool isMOVDIRI(unsigned Opcode) {
15917 switch (Opcode) {
15918 case MOVDIRI32:
15919 case MOVDIRI32_EVEX:
15920 case MOVDIRI64:
15921 case MOVDIRI64_EVEX:
15922 return true;
15923 }
15924 return false;
15925}
15926
15927bool isSHUFPS(unsigned Opcode) {
15928 switch (Opcode) {
15929 case SHUFPSrmi:
15930 case SHUFPSrri:
15931 return true;
15932 }
15933 return false;
15934}
15935
15936bool isVFNMSUB231SS(unsigned Opcode) {
15937 switch (Opcode) {
15938 case VFNMSUB231SSZm_Int:
15939 case VFNMSUB231SSZmk_Int:
15940 case VFNMSUB231SSZmkz_Int:
15941 case VFNMSUB231SSZr_Int:
15942 case VFNMSUB231SSZrb_Int:
15943 case VFNMSUB231SSZrbk_Int:
15944 case VFNMSUB231SSZrbkz_Int:
15945 case VFNMSUB231SSZrk_Int:
15946 case VFNMSUB231SSZrkz_Int:
15947 case VFNMSUB231SSm_Int:
15948 case VFNMSUB231SSr_Int:
15949 return true;
15950 }
15951 return false;
15952}
15953
15954bool isVMWRITE(unsigned Opcode) {
15955 switch (Opcode) {
15956 case VMWRITE32rm:
15957 case VMWRITE32rr:
15958 case VMWRITE64rm:
15959 case VMWRITE64rr:
15960 return true;
15961 }
15962 return false;
15963}
15964
15965bool isVINSERTF128(unsigned Opcode) {
15966 switch (Opcode) {
15967 case VINSERTF128rmi:
15968 case VINSERTF128rri:
15969 return true;
15970 }
15971 return false;
15972}
15973
15974bool isFISUBR(unsigned Opcode) {
15975 switch (Opcode) {
15976 case SUBR_FI16m:
15977 case SUBR_FI32m:
15978 return true;
15979 }
15980 return false;
15981}
15982
15983bool isVINSERTI32X4(unsigned Opcode) {
15984 switch (Opcode) {
15985 case VINSERTI32X4Z256rmi:
15986 case VINSERTI32X4Z256rmik:
15987 case VINSERTI32X4Z256rmikz:
15988 case VINSERTI32X4Z256rri:
15989 case VINSERTI32X4Z256rrik:
15990 case VINSERTI32X4Z256rrikz:
15991 case VINSERTI32X4Zrmi:
15992 case VINSERTI32X4Zrmik:
15993 case VINSERTI32X4Zrmikz:
15994 case VINSERTI32X4Zrri:
15995 case VINSERTI32X4Zrrik:
15996 case VINSERTI32X4Zrrikz:
15997 return true;
15998 }
15999 return false;
16000}
16001
16002bool isVPSLLDQ(unsigned Opcode) {
16003 switch (Opcode) {
16004 case VPSLLDQYri:
16005 case VPSLLDQZ128mi:
16006 case VPSLLDQZ128ri:
16007 case VPSLLDQZ256mi:
16008 case VPSLLDQZ256ri:
16009 case VPSLLDQZmi:
16010 case VPSLLDQZri:
16011 case VPSLLDQri:
16012 return true;
16013 }
16014 return false;
16015}
16016
16017bool isPOPCNT(unsigned Opcode) {
16018 switch (Opcode) {
16019 case POPCNT16rm:
16020 case POPCNT16rm_EVEX:
16021 case POPCNT16rm_NF:
16022 case POPCNT16rr:
16023 case POPCNT16rr_EVEX:
16024 case POPCNT16rr_NF:
16025 case POPCNT32rm:
16026 case POPCNT32rm_EVEX:
16027 case POPCNT32rm_NF:
16028 case POPCNT32rr:
16029 case POPCNT32rr_EVEX:
16030 case POPCNT32rr_NF:
16031 case POPCNT64rm:
16032 case POPCNT64rm_EVEX:
16033 case POPCNT64rm_NF:
16034 case POPCNT64rr:
16035 case POPCNT64rr_EVEX:
16036 case POPCNT64rr_NF:
16037 return true;
16038 }
16039 return false;
16040}
16041
16042bool isVXORPD(unsigned Opcode) {
16043 switch (Opcode) {
16044 case VXORPDYrm:
16045 case VXORPDYrr:
16046 case VXORPDZ128rm:
16047 case VXORPDZ128rmb:
16048 case VXORPDZ128rmbk:
16049 case VXORPDZ128rmbkz:
16050 case VXORPDZ128rmk:
16051 case VXORPDZ128rmkz:
16052 case VXORPDZ128rr:
16053 case VXORPDZ128rrk:
16054 case VXORPDZ128rrkz:
16055 case VXORPDZ256rm:
16056 case VXORPDZ256rmb:
16057 case VXORPDZ256rmbk:
16058 case VXORPDZ256rmbkz:
16059 case VXORPDZ256rmk:
16060 case VXORPDZ256rmkz:
16061 case VXORPDZ256rr:
16062 case VXORPDZ256rrk:
16063 case VXORPDZ256rrkz:
16064 case VXORPDZrm:
16065 case VXORPDZrmb:
16066 case VXORPDZrmbk:
16067 case VXORPDZrmbkz:
16068 case VXORPDZrmk:
16069 case VXORPDZrmkz:
16070 case VXORPDZrr:
16071 case VXORPDZrrk:
16072 case VXORPDZrrkz:
16073 case VXORPDrm:
16074 case VXORPDrr:
16075 return true;
16076 }
16077 return false;
16078}
16079
16080bool isXLATB(unsigned Opcode) {
16081 return Opcode == XLAT;
16082}
16083
16084bool isDIV(unsigned Opcode) {
16085 switch (Opcode) {
16086 case DIV16m:
16087 case DIV16m_EVEX:
16088 case DIV16m_NF:
16089 case DIV16r:
16090 case DIV16r_EVEX:
16091 case DIV16r_NF:
16092 case DIV32m:
16093 case DIV32m_EVEX:
16094 case DIV32m_NF:
16095 case DIV32r:
16096 case DIV32r_EVEX:
16097 case DIV32r_NF:
16098 case DIV64m:
16099 case DIV64m_EVEX:
16100 case DIV64m_NF:
16101 case DIV64r:
16102 case DIV64r_EVEX:
16103 case DIV64r_NF:
16104 case DIV8m:
16105 case DIV8m_EVEX:
16106 case DIV8m_NF:
16107 case DIV8r:
16108 case DIV8r_EVEX:
16109 case DIV8r_NF:
16110 return true;
16111 }
16112 return false;
16113}
16114
16115bool isVPSHLDVQ(unsigned Opcode) {
16116 switch (Opcode) {
16117 case VPSHLDVQZ128m:
16118 case VPSHLDVQZ128mb:
16119 case VPSHLDVQZ128mbk:
16120 case VPSHLDVQZ128mbkz:
16121 case VPSHLDVQZ128mk:
16122 case VPSHLDVQZ128mkz:
16123 case VPSHLDVQZ128r:
16124 case VPSHLDVQZ128rk:
16125 case VPSHLDVQZ128rkz:
16126 case VPSHLDVQZ256m:
16127 case VPSHLDVQZ256mb:
16128 case VPSHLDVQZ256mbk:
16129 case VPSHLDVQZ256mbkz:
16130 case VPSHLDVQZ256mk:
16131 case VPSHLDVQZ256mkz:
16132 case VPSHLDVQZ256r:
16133 case VPSHLDVQZ256rk:
16134 case VPSHLDVQZ256rkz:
16135 case VPSHLDVQZm:
16136 case VPSHLDVQZmb:
16137 case VPSHLDVQZmbk:
16138 case VPSHLDVQZmbkz:
16139 case VPSHLDVQZmk:
16140 case VPSHLDVQZmkz:
16141 case VPSHLDVQZr:
16142 case VPSHLDVQZrk:
16143 case VPSHLDVQZrkz:
16144 return true;
16145 }
16146 return false;
16147}
16148
16149bool isMOVDDUP(unsigned Opcode) {
16150 switch (Opcode) {
16151 case MOVDDUPrm:
16152 case MOVDDUPrr:
16153 return true;
16154 }
16155 return false;
16156}
16157
16158bool isVMOVDQU64(unsigned Opcode) {
16159 switch (Opcode) {
16160 case VMOVDQU64Z128mr:
16161 case VMOVDQU64Z128mrk:
16162 case VMOVDQU64Z128rm:
16163 case VMOVDQU64Z128rmk:
16164 case VMOVDQU64Z128rmkz:
16165 case VMOVDQU64Z128rr:
16166 case VMOVDQU64Z128rr_REV:
16167 case VMOVDQU64Z128rrk:
16168 case VMOVDQU64Z128rrk_REV:
16169 case VMOVDQU64Z128rrkz:
16170 case VMOVDQU64Z128rrkz_REV:
16171 case VMOVDQU64Z256mr:
16172 case VMOVDQU64Z256mrk:
16173 case VMOVDQU64Z256rm:
16174 case VMOVDQU64Z256rmk:
16175 case VMOVDQU64Z256rmkz:
16176 case VMOVDQU64Z256rr:
16177 case VMOVDQU64Z256rr_REV:
16178 case VMOVDQU64Z256rrk:
16179 case VMOVDQU64Z256rrk_REV:
16180 case VMOVDQU64Z256rrkz:
16181 case VMOVDQU64Z256rrkz_REV:
16182 case VMOVDQU64Zmr:
16183 case VMOVDQU64Zmrk:
16184 case VMOVDQU64Zrm:
16185 case VMOVDQU64Zrmk:
16186 case VMOVDQU64Zrmkz:
16187 case VMOVDQU64Zrr:
16188 case VMOVDQU64Zrr_REV:
16189 case VMOVDQU64Zrrk:
16190 case VMOVDQU64Zrrk_REV:
16191 case VMOVDQU64Zrrkz:
16192 case VMOVDQU64Zrrkz_REV:
16193 return true;
16194 }
16195 return false;
16196}
16197
16198bool isVPCOMPRESSQ(unsigned Opcode) {
16199 switch (Opcode) {
16200 case VPCOMPRESSQZ128mr:
16201 case VPCOMPRESSQZ128mrk:
16202 case VPCOMPRESSQZ128rr:
16203 case VPCOMPRESSQZ128rrk:
16204 case VPCOMPRESSQZ128rrkz:
16205 case VPCOMPRESSQZ256mr:
16206 case VPCOMPRESSQZ256mrk:
16207 case VPCOMPRESSQZ256rr:
16208 case VPCOMPRESSQZ256rrk:
16209 case VPCOMPRESSQZ256rrkz:
16210 case VPCOMPRESSQZmr:
16211 case VPCOMPRESSQZmrk:
16212 case VPCOMPRESSQZrr:
16213 case VPCOMPRESSQZrrk:
16214 case VPCOMPRESSQZrrkz:
16215 return true;
16216 }
16217 return false;
16218}
16219
16220bool isVFMSUBADD132PD(unsigned Opcode) {
16221 switch (Opcode) {
16222 case VFMSUBADD132PDYm:
16223 case VFMSUBADD132PDYr:
16224 case VFMSUBADD132PDZ128m:
16225 case VFMSUBADD132PDZ128mb:
16226 case VFMSUBADD132PDZ128mbk:
16227 case VFMSUBADD132PDZ128mbkz:
16228 case VFMSUBADD132PDZ128mk:
16229 case VFMSUBADD132PDZ128mkz:
16230 case VFMSUBADD132PDZ128r:
16231 case VFMSUBADD132PDZ128rk:
16232 case VFMSUBADD132PDZ128rkz:
16233 case VFMSUBADD132PDZ256m:
16234 case VFMSUBADD132PDZ256mb:
16235 case VFMSUBADD132PDZ256mbk:
16236 case VFMSUBADD132PDZ256mbkz:
16237 case VFMSUBADD132PDZ256mk:
16238 case VFMSUBADD132PDZ256mkz:
16239 case VFMSUBADD132PDZ256r:
16240 case VFMSUBADD132PDZ256rk:
16241 case VFMSUBADD132PDZ256rkz:
16242 case VFMSUBADD132PDZm:
16243 case VFMSUBADD132PDZmb:
16244 case VFMSUBADD132PDZmbk:
16245 case VFMSUBADD132PDZmbkz:
16246 case VFMSUBADD132PDZmk:
16247 case VFMSUBADD132PDZmkz:
16248 case VFMSUBADD132PDZr:
16249 case VFMSUBADD132PDZrb:
16250 case VFMSUBADD132PDZrbk:
16251 case VFMSUBADD132PDZrbkz:
16252 case VFMSUBADD132PDZrk:
16253 case VFMSUBADD132PDZrkz:
16254 case VFMSUBADD132PDm:
16255 case VFMSUBADD132PDr:
16256 return true;
16257 }
16258 return false;
16259}
16260
16261bool isVPERMILPD(unsigned Opcode) {
16262 switch (Opcode) {
16263 case VPERMILPDYmi:
16264 case VPERMILPDYri:
16265 case VPERMILPDYrm:
16266 case VPERMILPDYrr:
16267 case VPERMILPDZ128mbi:
16268 case VPERMILPDZ128mbik:
16269 case VPERMILPDZ128mbikz:
16270 case VPERMILPDZ128mi:
16271 case VPERMILPDZ128mik:
16272 case VPERMILPDZ128mikz:
16273 case VPERMILPDZ128ri:
16274 case VPERMILPDZ128rik:
16275 case VPERMILPDZ128rikz:
16276 case VPERMILPDZ128rm:
16277 case VPERMILPDZ128rmb:
16278 case VPERMILPDZ128rmbk:
16279 case VPERMILPDZ128rmbkz:
16280 case VPERMILPDZ128rmk:
16281 case VPERMILPDZ128rmkz:
16282 case VPERMILPDZ128rr:
16283 case VPERMILPDZ128rrk:
16284 case VPERMILPDZ128rrkz:
16285 case VPERMILPDZ256mbi:
16286 case VPERMILPDZ256mbik:
16287 case VPERMILPDZ256mbikz:
16288 case VPERMILPDZ256mi:
16289 case VPERMILPDZ256mik:
16290 case VPERMILPDZ256mikz:
16291 case VPERMILPDZ256ri:
16292 case VPERMILPDZ256rik:
16293 case VPERMILPDZ256rikz:
16294 case VPERMILPDZ256rm:
16295 case VPERMILPDZ256rmb:
16296 case VPERMILPDZ256rmbk:
16297 case VPERMILPDZ256rmbkz:
16298 case VPERMILPDZ256rmk:
16299 case VPERMILPDZ256rmkz:
16300 case VPERMILPDZ256rr:
16301 case VPERMILPDZ256rrk:
16302 case VPERMILPDZ256rrkz:
16303 case VPERMILPDZmbi:
16304 case VPERMILPDZmbik:
16305 case VPERMILPDZmbikz:
16306 case VPERMILPDZmi:
16307 case VPERMILPDZmik:
16308 case VPERMILPDZmikz:
16309 case VPERMILPDZri:
16310 case VPERMILPDZrik:
16311 case VPERMILPDZrikz:
16312 case VPERMILPDZrm:
16313 case VPERMILPDZrmb:
16314 case VPERMILPDZrmbk:
16315 case VPERMILPDZrmbkz:
16316 case VPERMILPDZrmk:
16317 case VPERMILPDZrmkz:
16318 case VPERMILPDZrr:
16319 case VPERMILPDZrrk:
16320 case VPERMILPDZrrkz:
16321 case VPERMILPDmi:
16322 case VPERMILPDri:
16323 case VPERMILPDrm:
16324 case VPERMILPDrr:
16325 return true;
16326 }
16327 return false;
16328}
16329
16330bool isADDSD(unsigned Opcode) {
16331 switch (Opcode) {
16332 case ADDSDrm_Int:
16333 case ADDSDrr_Int:
16334 return true;
16335 }
16336 return false;
16337}
16338
16339bool isBLENDPD(unsigned Opcode) {
16340 switch (Opcode) {
16341 case BLENDPDrmi:
16342 case BLENDPDrri:
16343 return true;
16344 }
16345 return false;
16346}
16347
16348bool isVPANDQ(unsigned Opcode) {
16349 switch (Opcode) {
16350 case VPANDQZ128rm:
16351 case VPANDQZ128rmb:
16352 case VPANDQZ128rmbk:
16353 case VPANDQZ128rmbkz:
16354 case VPANDQZ128rmk:
16355 case VPANDQZ128rmkz:
16356 case VPANDQZ128rr:
16357 case VPANDQZ128rrk:
16358 case VPANDQZ128rrkz:
16359 case VPANDQZ256rm:
16360 case VPANDQZ256rmb:
16361 case VPANDQZ256rmbk:
16362 case VPANDQZ256rmbkz:
16363 case VPANDQZ256rmk:
16364 case VPANDQZ256rmkz:
16365 case VPANDQZ256rr:
16366 case VPANDQZ256rrk:
16367 case VPANDQZ256rrkz:
16368 case VPANDQZrm:
16369 case VPANDQZrmb:
16370 case VPANDQZrmbk:
16371 case VPANDQZrmbkz:
16372 case VPANDQZrmk:
16373 case VPANDQZrmkz:
16374 case VPANDQZrr:
16375 case VPANDQZrrk:
16376 case VPANDQZrrkz:
16377 return true;
16378 }
16379 return false;
16380}
16381
16382bool isPMADDUBSW(unsigned Opcode) {
16383 switch (Opcode) {
16384 case MMX_PMADDUBSWrm:
16385 case MMX_PMADDUBSWrr:
16386 case PMADDUBSWrm:
16387 case PMADDUBSWrr:
16388 return true;
16389 }
16390 return false;
16391}
16392
16393bool isPOPFD(unsigned Opcode) {
16394 return Opcode == POPF32;
16395}
16396
16397bool isCMPSW(unsigned Opcode) {
16398 return Opcode == CMPSW;
16399}
16400
16401bool isLDMXCSR(unsigned Opcode) {
16402 return Opcode == LDMXCSR;
16403}
16404
16405bool isVMULPS(unsigned Opcode) {
16406 switch (Opcode) {
16407 case VMULPSYrm:
16408 case VMULPSYrr:
16409 case VMULPSZ128rm:
16410 case VMULPSZ128rmb:
16411 case VMULPSZ128rmbk:
16412 case VMULPSZ128rmbkz:
16413 case VMULPSZ128rmk:
16414 case VMULPSZ128rmkz:
16415 case VMULPSZ128rr:
16416 case VMULPSZ128rrk:
16417 case VMULPSZ128rrkz:
16418 case VMULPSZ256rm:
16419 case VMULPSZ256rmb:
16420 case VMULPSZ256rmbk:
16421 case VMULPSZ256rmbkz:
16422 case VMULPSZ256rmk:
16423 case VMULPSZ256rmkz:
16424 case VMULPSZ256rr:
16425 case VMULPSZ256rrk:
16426 case VMULPSZ256rrkz:
16427 case VMULPSZrm:
16428 case VMULPSZrmb:
16429 case VMULPSZrmbk:
16430 case VMULPSZrmbkz:
16431 case VMULPSZrmk:
16432 case VMULPSZrmkz:
16433 case VMULPSZrr:
16434 case VMULPSZrrb:
16435 case VMULPSZrrbk:
16436 case VMULPSZrrbkz:
16437 case VMULPSZrrk:
16438 case VMULPSZrrkz:
16439 case VMULPSrm:
16440 case VMULPSrr:
16441 return true;
16442 }
16443 return false;
16444}
16445
16446bool isVROUNDSD(unsigned Opcode) {
16447 switch (Opcode) {
16448 case VROUNDSDmi_Int:
16449 case VROUNDSDri_Int:
16450 return true;
16451 }
16452 return false;
16453}
16454
16455bool isVFMADD132PD(unsigned Opcode) {
16456 switch (Opcode) {
16457 case VFMADD132PDYm:
16458 case VFMADD132PDYr:
16459 case VFMADD132PDZ128m:
16460 case VFMADD132PDZ128mb:
16461 case VFMADD132PDZ128mbk:
16462 case VFMADD132PDZ128mbkz:
16463 case VFMADD132PDZ128mk:
16464 case VFMADD132PDZ128mkz:
16465 case VFMADD132PDZ128r:
16466 case VFMADD132PDZ128rk:
16467 case VFMADD132PDZ128rkz:
16468 case VFMADD132PDZ256m:
16469 case VFMADD132PDZ256mb:
16470 case VFMADD132PDZ256mbk:
16471 case VFMADD132PDZ256mbkz:
16472 case VFMADD132PDZ256mk:
16473 case VFMADD132PDZ256mkz:
16474 case VFMADD132PDZ256r:
16475 case VFMADD132PDZ256rk:
16476 case VFMADD132PDZ256rkz:
16477 case VFMADD132PDZm:
16478 case VFMADD132PDZmb:
16479 case VFMADD132PDZmbk:
16480 case VFMADD132PDZmbkz:
16481 case VFMADD132PDZmk:
16482 case VFMADD132PDZmkz:
16483 case VFMADD132PDZr:
16484 case VFMADD132PDZrb:
16485 case VFMADD132PDZrbk:
16486 case VFMADD132PDZrbkz:
16487 case VFMADD132PDZrk:
16488 case VFMADD132PDZrkz:
16489 case VFMADD132PDm:
16490 case VFMADD132PDr:
16491 return true;
16492 }
16493 return false;
16494}
16495
16496bool isVPSRAQ(unsigned Opcode) {
16497 switch (Opcode) {
16498 case VPSRAQZ128mbi:
16499 case VPSRAQZ128mbik:
16500 case VPSRAQZ128mbikz:
16501 case VPSRAQZ128mi:
16502 case VPSRAQZ128mik:
16503 case VPSRAQZ128mikz:
16504 case VPSRAQZ128ri:
16505 case VPSRAQZ128rik:
16506 case VPSRAQZ128rikz:
16507 case VPSRAQZ128rm:
16508 case VPSRAQZ128rmk:
16509 case VPSRAQZ128rmkz:
16510 case VPSRAQZ128rr:
16511 case VPSRAQZ128rrk:
16512 case VPSRAQZ128rrkz:
16513 case VPSRAQZ256mbi:
16514 case VPSRAQZ256mbik:
16515 case VPSRAQZ256mbikz:
16516 case VPSRAQZ256mi:
16517 case VPSRAQZ256mik:
16518 case VPSRAQZ256mikz:
16519 case VPSRAQZ256ri:
16520 case VPSRAQZ256rik:
16521 case VPSRAQZ256rikz:
16522 case VPSRAQZ256rm:
16523 case VPSRAQZ256rmk:
16524 case VPSRAQZ256rmkz:
16525 case VPSRAQZ256rr:
16526 case VPSRAQZ256rrk:
16527 case VPSRAQZ256rrkz:
16528 case VPSRAQZmbi:
16529 case VPSRAQZmbik:
16530 case VPSRAQZmbikz:
16531 case VPSRAQZmi:
16532 case VPSRAQZmik:
16533 case VPSRAQZmikz:
16534 case VPSRAQZri:
16535 case VPSRAQZrik:
16536 case VPSRAQZrikz:
16537 case VPSRAQZrm:
16538 case VPSRAQZrmk:
16539 case VPSRAQZrmkz:
16540 case VPSRAQZrr:
16541 case VPSRAQZrrk:
16542 case VPSRAQZrrkz:
16543 return true;
16544 }
16545 return false;
16546}
16547
16548bool isVCOMISD(unsigned Opcode) {
16549 switch (Opcode) {
16550 case VCOMISDZrm:
16551 case VCOMISDZrr:
16552 case VCOMISDZrrb:
16553 case VCOMISDrm:
16554 case VCOMISDrr:
16555 return true;
16556 }
16557 return false;
16558}
16559
16560bool isVCVTBIASPH2BF8(unsigned Opcode) {
16561 switch (Opcode) {
16562 case VCVTBIASPH2BF8Z128rm:
16563 case VCVTBIASPH2BF8Z128rmb:
16564 case VCVTBIASPH2BF8Z128rmbk:
16565 case VCVTBIASPH2BF8Z128rmbkz:
16566 case VCVTBIASPH2BF8Z128rmk:
16567 case VCVTBIASPH2BF8Z128rmkz:
16568 case VCVTBIASPH2BF8Z128rr:
16569 case VCVTBIASPH2BF8Z128rrk:
16570 case VCVTBIASPH2BF8Z128rrkz:
16571 case VCVTBIASPH2BF8Z256rm:
16572 case VCVTBIASPH2BF8Z256rmb:
16573 case VCVTBIASPH2BF8Z256rmbk:
16574 case VCVTBIASPH2BF8Z256rmbkz:
16575 case VCVTBIASPH2BF8Z256rmk:
16576 case VCVTBIASPH2BF8Z256rmkz:
16577 case VCVTBIASPH2BF8Z256rr:
16578 case VCVTBIASPH2BF8Z256rrk:
16579 case VCVTBIASPH2BF8Z256rrkz:
16580 case VCVTBIASPH2BF8Zrm:
16581 case VCVTBIASPH2BF8Zrmb:
16582 case VCVTBIASPH2BF8Zrmbk:
16583 case VCVTBIASPH2BF8Zrmbkz:
16584 case VCVTBIASPH2BF8Zrmk:
16585 case VCVTBIASPH2BF8Zrmkz:
16586 case VCVTBIASPH2BF8Zrr:
16587 case VCVTBIASPH2BF8Zrrk:
16588 case VCVTBIASPH2BF8Zrrkz:
16589 return true;
16590 }
16591 return false;
16592}
16593
16594bool isFFREEP(unsigned Opcode) {
16595 return Opcode == FFREEP;
16596}
16597
16598bool isVFNMADD213PD(unsigned Opcode) {
16599 switch (Opcode) {
16600 case VFNMADD213PDYm:
16601 case VFNMADD213PDYr:
16602 case VFNMADD213PDZ128m:
16603 case VFNMADD213PDZ128mb:
16604 case VFNMADD213PDZ128mbk:
16605 case VFNMADD213PDZ128mbkz:
16606 case VFNMADD213PDZ128mk:
16607 case VFNMADD213PDZ128mkz:
16608 case VFNMADD213PDZ128r:
16609 case VFNMADD213PDZ128rk:
16610 case VFNMADD213PDZ128rkz:
16611 case VFNMADD213PDZ256m:
16612 case VFNMADD213PDZ256mb:
16613 case VFNMADD213PDZ256mbk:
16614 case VFNMADD213PDZ256mbkz:
16615 case VFNMADD213PDZ256mk:
16616 case VFNMADD213PDZ256mkz:
16617 case VFNMADD213PDZ256r:
16618 case VFNMADD213PDZ256rk:
16619 case VFNMADD213PDZ256rkz:
16620 case VFNMADD213PDZm:
16621 case VFNMADD213PDZmb:
16622 case VFNMADD213PDZmbk:
16623 case VFNMADD213PDZmbkz:
16624 case VFNMADD213PDZmk:
16625 case VFNMADD213PDZmkz:
16626 case VFNMADD213PDZr:
16627 case VFNMADD213PDZrb:
16628 case VFNMADD213PDZrbk:
16629 case VFNMADD213PDZrbkz:
16630 case VFNMADD213PDZrk:
16631 case VFNMADD213PDZrkz:
16632 case VFNMADD213PDm:
16633 case VFNMADD213PDr:
16634 return true;
16635 }
16636 return false;
16637}
16638
16639bool isVCMPPD(unsigned Opcode) {
16640 switch (Opcode) {
16641 case VCMPPDYrmi:
16642 case VCMPPDYrri:
16643 case VCMPPDZ128rmbi:
16644 case VCMPPDZ128rmbik:
16645 case VCMPPDZ128rmi:
16646 case VCMPPDZ128rmik:
16647 case VCMPPDZ128rri:
16648 case VCMPPDZ128rrik:
16649 case VCMPPDZ256rmbi:
16650 case VCMPPDZ256rmbik:
16651 case VCMPPDZ256rmi:
16652 case VCMPPDZ256rmik:
16653 case VCMPPDZ256rri:
16654 case VCMPPDZ256rrik:
16655 case VCMPPDZrmbi:
16656 case VCMPPDZrmbik:
16657 case VCMPPDZrmi:
16658 case VCMPPDZrmik:
16659 case VCMPPDZrri:
16660 case VCMPPDZrrib:
16661 case VCMPPDZrribk:
16662 case VCMPPDZrrik:
16663 case VCMPPDrmi:
16664 case VCMPPDrri:
16665 return true;
16666 }
16667 return false;
16668}
16669
16670bool isVFNMSUB132PH(unsigned Opcode) {
16671 switch (Opcode) {
16672 case VFNMSUB132PHZ128m:
16673 case VFNMSUB132PHZ128mb:
16674 case VFNMSUB132PHZ128mbk:
16675 case VFNMSUB132PHZ128mbkz:
16676 case VFNMSUB132PHZ128mk:
16677 case VFNMSUB132PHZ128mkz:
16678 case VFNMSUB132PHZ128r:
16679 case VFNMSUB132PHZ128rk:
16680 case VFNMSUB132PHZ128rkz:
16681 case VFNMSUB132PHZ256m:
16682 case VFNMSUB132PHZ256mb:
16683 case VFNMSUB132PHZ256mbk:
16684 case VFNMSUB132PHZ256mbkz:
16685 case VFNMSUB132PHZ256mk:
16686 case VFNMSUB132PHZ256mkz:
16687 case VFNMSUB132PHZ256r:
16688 case VFNMSUB132PHZ256rk:
16689 case VFNMSUB132PHZ256rkz:
16690 case VFNMSUB132PHZm:
16691 case VFNMSUB132PHZmb:
16692 case VFNMSUB132PHZmbk:
16693 case VFNMSUB132PHZmbkz:
16694 case VFNMSUB132PHZmk:
16695 case VFNMSUB132PHZmkz:
16696 case VFNMSUB132PHZr:
16697 case VFNMSUB132PHZrb:
16698 case VFNMSUB132PHZrbk:
16699 case VFNMSUB132PHZrbkz:
16700 case VFNMSUB132PHZrk:
16701 case VFNMSUB132PHZrkz:
16702 return true;
16703 }
16704 return false;
16705}
16706
16707bool isVPHADDBW(unsigned Opcode) {
16708 switch (Opcode) {
16709 case VPHADDBWrm:
16710 case VPHADDBWrr:
16711 return true;
16712 }
16713 return false;
16714}
16715
16716bool isVPPERM(unsigned Opcode) {
16717 switch (Opcode) {
16718 case VPPERMrmr:
16719 case VPPERMrrm:
16720 case VPPERMrrr:
16721 case VPPERMrrr_REV:
16722 return true;
16723 }
16724 return false;
16725}
16726
16727bool isVCVTPS2PD(unsigned Opcode) {
16728 switch (Opcode) {
16729 case VCVTPS2PDYrm:
16730 case VCVTPS2PDYrr:
16731 case VCVTPS2PDZ128rm:
16732 case VCVTPS2PDZ128rmb:
16733 case VCVTPS2PDZ128rmbk:
16734 case VCVTPS2PDZ128rmbkz:
16735 case VCVTPS2PDZ128rmk:
16736 case VCVTPS2PDZ128rmkz:
16737 case VCVTPS2PDZ128rr:
16738 case VCVTPS2PDZ128rrk:
16739 case VCVTPS2PDZ128rrkz:
16740 case VCVTPS2PDZ256rm:
16741 case VCVTPS2PDZ256rmb:
16742 case VCVTPS2PDZ256rmbk:
16743 case VCVTPS2PDZ256rmbkz:
16744 case VCVTPS2PDZ256rmk:
16745 case VCVTPS2PDZ256rmkz:
16746 case VCVTPS2PDZ256rr:
16747 case VCVTPS2PDZ256rrk:
16748 case VCVTPS2PDZ256rrkz:
16749 case VCVTPS2PDZrm:
16750 case VCVTPS2PDZrmb:
16751 case VCVTPS2PDZrmbk:
16752 case VCVTPS2PDZrmbkz:
16753 case VCVTPS2PDZrmk:
16754 case VCVTPS2PDZrmkz:
16755 case VCVTPS2PDZrr:
16756 case VCVTPS2PDZrrb:
16757 case VCVTPS2PDZrrbk:
16758 case VCVTPS2PDZrrbkz:
16759 case VCVTPS2PDZrrk:
16760 case VCVTPS2PDZrrkz:
16761 case VCVTPS2PDrm:
16762 case VCVTPS2PDrr:
16763 return true;
16764 }
16765 return false;
16766}
16767
16768bool isCBW(unsigned Opcode) {
16769 return Opcode == CBW;
16770}
16771
16772bool isVMOVUPS(unsigned Opcode) {
16773 switch (Opcode) {
16774 case VMOVUPSYmr:
16775 case VMOVUPSYrm:
16776 case VMOVUPSYrr:
16777 case VMOVUPSYrr_REV:
16778 case VMOVUPSZ128mr:
16779 case VMOVUPSZ128mrk:
16780 case VMOVUPSZ128rm:
16781 case VMOVUPSZ128rmk:
16782 case VMOVUPSZ128rmkz:
16783 case VMOVUPSZ128rr:
16784 case VMOVUPSZ128rr_REV:
16785 case VMOVUPSZ128rrk:
16786 case VMOVUPSZ128rrk_REV:
16787 case VMOVUPSZ128rrkz:
16788 case VMOVUPSZ128rrkz_REV:
16789 case VMOVUPSZ256mr:
16790 case VMOVUPSZ256mrk:
16791 case VMOVUPSZ256rm:
16792 case VMOVUPSZ256rmk:
16793 case VMOVUPSZ256rmkz:
16794 case VMOVUPSZ256rr:
16795 case VMOVUPSZ256rr_REV:
16796 case VMOVUPSZ256rrk:
16797 case VMOVUPSZ256rrk_REV:
16798 case VMOVUPSZ256rrkz:
16799 case VMOVUPSZ256rrkz_REV:
16800 case VMOVUPSZmr:
16801 case VMOVUPSZmrk:
16802 case VMOVUPSZrm:
16803 case VMOVUPSZrmk:
16804 case VMOVUPSZrmkz:
16805 case VMOVUPSZrr:
16806 case VMOVUPSZrr_REV:
16807 case VMOVUPSZrrk:
16808 case VMOVUPSZrrk_REV:
16809 case VMOVUPSZrrkz:
16810 case VMOVUPSZrrkz_REV:
16811 case VMOVUPSmr:
16812 case VMOVUPSrm:
16813 case VMOVUPSrr:
16814 case VMOVUPSrr_REV:
16815 return true;
16816 }
16817 return false;
16818}
16819
16820bool isVPMAXUQ(unsigned Opcode) {
16821 switch (Opcode) {
16822 case VPMAXUQZ128rm:
16823 case VPMAXUQZ128rmb:
16824 case VPMAXUQZ128rmbk:
16825 case VPMAXUQZ128rmbkz:
16826 case VPMAXUQZ128rmk:
16827 case VPMAXUQZ128rmkz:
16828 case VPMAXUQZ128rr:
16829 case VPMAXUQZ128rrk:
16830 case VPMAXUQZ128rrkz:
16831 case VPMAXUQZ256rm:
16832 case VPMAXUQZ256rmb:
16833 case VPMAXUQZ256rmbk:
16834 case VPMAXUQZ256rmbkz:
16835 case VPMAXUQZ256rmk:
16836 case VPMAXUQZ256rmkz:
16837 case VPMAXUQZ256rr:
16838 case VPMAXUQZ256rrk:
16839 case VPMAXUQZ256rrkz:
16840 case VPMAXUQZrm:
16841 case VPMAXUQZrmb:
16842 case VPMAXUQZrmbk:
16843 case VPMAXUQZrmbkz:
16844 case VPMAXUQZrmk:
16845 case VPMAXUQZrmkz:
16846 case VPMAXUQZrr:
16847 case VPMAXUQZrrk:
16848 case VPMAXUQZrrkz:
16849 return true;
16850 }
16851 return false;
16852}
16853
16854bool isWRSSQ(unsigned Opcode) {
16855 switch (Opcode) {
16856 case WRSSQ:
16857 case WRSSQ_EVEX:
16858 return true;
16859 }
16860 return false;
16861}
16862
16863bool isPACKUSDW(unsigned Opcode) {
16864 switch (Opcode) {
16865 case PACKUSDWrm:
16866 case PACKUSDWrr:
16867 return true;
16868 }
16869 return false;
16870}
16871
16872bool isVCVTTBF162IBS(unsigned Opcode) {
16873 switch (Opcode) {
16874 case VCVTTBF162IBSZ128rm:
16875 case VCVTTBF162IBSZ128rmb:
16876 case VCVTTBF162IBSZ128rmbk:
16877 case VCVTTBF162IBSZ128rmbkz:
16878 case VCVTTBF162IBSZ128rmk:
16879 case VCVTTBF162IBSZ128rmkz:
16880 case VCVTTBF162IBSZ128rr:
16881 case VCVTTBF162IBSZ128rrk:
16882 case VCVTTBF162IBSZ128rrkz:
16883 case VCVTTBF162IBSZ256rm:
16884 case VCVTTBF162IBSZ256rmb:
16885 case VCVTTBF162IBSZ256rmbk:
16886 case VCVTTBF162IBSZ256rmbkz:
16887 case VCVTTBF162IBSZ256rmk:
16888 case VCVTTBF162IBSZ256rmkz:
16889 case VCVTTBF162IBSZ256rr:
16890 case VCVTTBF162IBSZ256rrk:
16891 case VCVTTBF162IBSZ256rrkz:
16892 case VCVTTBF162IBSZrm:
16893 case VCVTTBF162IBSZrmb:
16894 case VCVTTBF162IBSZrmbk:
16895 case VCVTTBF162IBSZrmbkz:
16896 case VCVTTBF162IBSZrmk:
16897 case VCVTTBF162IBSZrmkz:
16898 case VCVTTBF162IBSZrr:
16899 case VCVTTBF162IBSZrrk:
16900 case VCVTTBF162IBSZrrkz:
16901 return true;
16902 }
16903 return false;
16904}
16905
16906bool isXBEGIN(unsigned Opcode) {
16907 switch (Opcode) {
16908 case XBEGIN_2:
16909 case XBEGIN_4:
16910 return true;
16911 }
16912 return false;
16913}
16914
16915bool isVCVTPD2UQQ(unsigned Opcode) {
16916 switch (Opcode) {
16917 case VCVTPD2UQQZ128rm:
16918 case VCVTPD2UQQZ128rmb:
16919 case VCVTPD2UQQZ128rmbk:
16920 case VCVTPD2UQQZ128rmbkz:
16921 case VCVTPD2UQQZ128rmk:
16922 case VCVTPD2UQQZ128rmkz:
16923 case VCVTPD2UQQZ128rr:
16924 case VCVTPD2UQQZ128rrk:
16925 case VCVTPD2UQQZ128rrkz:
16926 case VCVTPD2UQQZ256rm:
16927 case VCVTPD2UQQZ256rmb:
16928 case VCVTPD2UQQZ256rmbk:
16929 case VCVTPD2UQQZ256rmbkz:
16930 case VCVTPD2UQQZ256rmk:
16931 case VCVTPD2UQQZ256rmkz:
16932 case VCVTPD2UQQZ256rr:
16933 case VCVTPD2UQQZ256rrk:
16934 case VCVTPD2UQQZ256rrkz:
16935 case VCVTPD2UQQZrm:
16936 case VCVTPD2UQQZrmb:
16937 case VCVTPD2UQQZrmbk:
16938 case VCVTPD2UQQZrmbkz:
16939 case VCVTPD2UQQZrmk:
16940 case VCVTPD2UQQZrmkz:
16941 case VCVTPD2UQQZrr:
16942 case VCVTPD2UQQZrrb:
16943 case VCVTPD2UQQZrrbk:
16944 case VCVTPD2UQQZrrbkz:
16945 case VCVTPD2UQQZrrk:
16946 case VCVTPD2UQQZrrkz:
16947 return true;
16948 }
16949 return false;
16950}
16951
16952bool isFCMOVB(unsigned Opcode) {
16953 return Opcode == CMOVB_F;
16954}
16955
16956bool isNOP(unsigned Opcode) {
16957 switch (Opcode) {
16958 case NOOP:
16959 case NOOPL:
16960 case NOOPLr:
16961 case NOOPQ:
16962 case NOOPQr:
16963 case NOOPW:
16964 case NOOPWr:
16965 return true;
16966 }
16967 return false;
16968}
16969
16970bool isVPABSQ(unsigned Opcode) {
16971 switch (Opcode) {
16972 case VPABSQZ128rm:
16973 case VPABSQZ128rmb:
16974 case VPABSQZ128rmbk:
16975 case VPABSQZ128rmbkz:
16976 case VPABSQZ128rmk:
16977 case VPABSQZ128rmkz:
16978 case VPABSQZ128rr:
16979 case VPABSQZ128rrk:
16980 case VPABSQZ128rrkz:
16981 case VPABSQZ256rm:
16982 case VPABSQZ256rmb:
16983 case VPABSQZ256rmbk:
16984 case VPABSQZ256rmbkz:
16985 case VPABSQZ256rmk:
16986 case VPABSQZ256rmkz:
16987 case VPABSQZ256rr:
16988 case VPABSQZ256rrk:
16989 case VPABSQZ256rrkz:
16990 case VPABSQZrm:
16991 case VPABSQZrmb:
16992 case VPABSQZrmbk:
16993 case VPABSQZrmbkz:
16994 case VPABSQZrmk:
16995 case VPABSQZrmkz:
16996 case VPABSQZrr:
16997 case VPABSQZrrk:
16998 case VPABSQZrrkz:
16999 return true;
17000 }
17001 return false;
17002}
17003
17004bool isVTESTPS(unsigned Opcode) {
17005 switch (Opcode) {
17006 case VTESTPSYrm:
17007 case VTESTPSYrr:
17008 case VTESTPSrm:
17009 case VTESTPSrr:
17010 return true;
17011 }
17012 return false;
17013}
17014
17015bool isPHSUBW(unsigned Opcode) {
17016 switch (Opcode) {
17017 case MMX_PHSUBWrm:
17018 case MMX_PHSUBWrr:
17019 case PHSUBWrm:
17020 case PHSUBWrr:
17021 return true;
17022 }
17023 return false;
17024}
17025
17026bool isPUSH2P(unsigned Opcode) {
17027 return Opcode == PUSH2P;
17028}
17029
17030bool isFISTTP(unsigned Opcode) {
17031 switch (Opcode) {
17032 case ISTT_FP16m:
17033 case ISTT_FP32m:
17034 case ISTT_FP64m:
17035 return true;
17036 }
17037 return false;
17038}
17039
17040bool isCFCMOVCC(unsigned Opcode) {
17041 switch (Opcode) {
17042 case CFCMOV16mr:
17043 case CFCMOV16rm:
17044 case CFCMOV16rm_ND:
17045 case CFCMOV16rr:
17046 case CFCMOV16rr_ND:
17047 case CFCMOV16rr_REV:
17048 case CFCMOV32mr:
17049 case CFCMOV32rm:
17050 case CFCMOV32rm_ND:
17051 case CFCMOV32rr:
17052 case CFCMOV32rr_ND:
17053 case CFCMOV32rr_REV:
17054 case CFCMOV64mr:
17055 case CFCMOV64rm:
17056 case CFCMOV64rm_ND:
17057 case CFCMOV64rr:
17058 case CFCMOV64rr_ND:
17059 case CFCMOV64rr_REV:
17060 return true;
17061 }
17062 return false;
17063}
17064
17065bool isPCMPESTRM(unsigned Opcode) {
17066 switch (Opcode) {
17067 case PCMPESTRMrmi:
17068 case PCMPESTRMrri:
17069 return true;
17070 }
17071 return false;
17072}
17073
17074bool isVPINSRD(unsigned Opcode) {
17075 switch (Opcode) {
17076 case VPINSRDZrmi:
17077 case VPINSRDZrri:
17078 case VPINSRDrmi:
17079 case VPINSRDrri:
17080 return true;
17081 }
17082 return false;
17083}
17084
17085bool isVFNMSUB213PS(unsigned Opcode) {
17086 switch (Opcode) {
17087 case VFNMSUB213PSYm:
17088 case VFNMSUB213PSYr:
17089 case VFNMSUB213PSZ128m:
17090 case VFNMSUB213PSZ128mb:
17091 case VFNMSUB213PSZ128mbk:
17092 case VFNMSUB213PSZ128mbkz:
17093 case VFNMSUB213PSZ128mk:
17094 case VFNMSUB213PSZ128mkz:
17095 case VFNMSUB213PSZ128r:
17096 case VFNMSUB213PSZ128rk:
17097 case VFNMSUB213PSZ128rkz:
17098 case VFNMSUB213PSZ256m:
17099 case VFNMSUB213PSZ256mb:
17100 case VFNMSUB213PSZ256mbk:
17101 case VFNMSUB213PSZ256mbkz:
17102 case VFNMSUB213PSZ256mk:
17103 case VFNMSUB213PSZ256mkz:
17104 case VFNMSUB213PSZ256r:
17105 case VFNMSUB213PSZ256rk:
17106 case VFNMSUB213PSZ256rkz:
17107 case VFNMSUB213PSZm:
17108 case VFNMSUB213PSZmb:
17109 case VFNMSUB213PSZmbk:
17110 case VFNMSUB213PSZmbkz:
17111 case VFNMSUB213PSZmk:
17112 case VFNMSUB213PSZmkz:
17113 case VFNMSUB213PSZr:
17114 case VFNMSUB213PSZrb:
17115 case VFNMSUB213PSZrbk:
17116 case VFNMSUB213PSZrbkz:
17117 case VFNMSUB213PSZrk:
17118 case VFNMSUB213PSZrkz:
17119 case VFNMSUB213PSm:
17120 case VFNMSUB213PSr:
17121 return true;
17122 }
17123 return false;
17124}
17125
17126bool isPHSUBD(unsigned Opcode) {
17127 switch (Opcode) {
17128 case MMX_PHSUBDrm:
17129 case MMX_PHSUBDrr:
17130 case PHSUBDrm:
17131 case PHSUBDrr:
17132 return true;
17133 }
17134 return false;
17135}
17136
17137bool isSLDT(unsigned Opcode) {
17138 switch (Opcode) {
17139 case SLDT16m:
17140 case SLDT16r:
17141 case SLDT32r:
17142 case SLDT64r:
17143 return true;
17144 }
17145 return false;
17146}
17147
17148bool isVCVTTPD2DQS(unsigned Opcode) {
17149 switch (Opcode) {
17150 case VCVTTPD2DQSZ128rm:
17151 case VCVTTPD2DQSZ128rmb:
17152 case VCVTTPD2DQSZ128rmbk:
17153 case VCVTTPD2DQSZ128rmbkz:
17154 case VCVTTPD2DQSZ128rmk:
17155 case VCVTTPD2DQSZ128rmkz:
17156 case VCVTTPD2DQSZ128rr:
17157 case VCVTTPD2DQSZ128rrk:
17158 case VCVTTPD2DQSZ128rrkz:
17159 case VCVTTPD2DQSZ256rm:
17160 case VCVTTPD2DQSZ256rmb:
17161 case VCVTTPD2DQSZ256rmbk:
17162 case VCVTTPD2DQSZ256rmbkz:
17163 case VCVTTPD2DQSZ256rmk:
17164 case VCVTTPD2DQSZ256rmkz:
17165 case VCVTTPD2DQSZ256rr:
17166 case VCVTTPD2DQSZ256rrb:
17167 case VCVTTPD2DQSZ256rrbk:
17168 case VCVTTPD2DQSZ256rrbkz:
17169 case VCVTTPD2DQSZ256rrk:
17170 case VCVTTPD2DQSZ256rrkz:
17171 case VCVTTPD2DQSZrm:
17172 case VCVTTPD2DQSZrmb:
17173 case VCVTTPD2DQSZrmbk:
17174 case VCVTTPD2DQSZrmbkz:
17175 case VCVTTPD2DQSZrmk:
17176 case VCVTTPD2DQSZrmkz:
17177 case VCVTTPD2DQSZrr:
17178 case VCVTTPD2DQSZrrb:
17179 case VCVTTPD2DQSZrrbk:
17180 case VCVTTPD2DQSZrrbkz:
17181 case VCVTTPD2DQSZrrk:
17182 case VCVTTPD2DQSZrrkz:
17183 return true;
17184 }
17185 return false;
17186}
17187
17188bool isVPMINSD(unsigned Opcode) {
17189 switch (Opcode) {
17190 case VPMINSDYrm:
17191 case VPMINSDYrr:
17192 case VPMINSDZ128rm:
17193 case VPMINSDZ128rmb:
17194 case VPMINSDZ128rmbk:
17195 case VPMINSDZ128rmbkz:
17196 case VPMINSDZ128rmk:
17197 case VPMINSDZ128rmkz:
17198 case VPMINSDZ128rr:
17199 case VPMINSDZ128rrk:
17200 case VPMINSDZ128rrkz:
17201 case VPMINSDZ256rm:
17202 case VPMINSDZ256rmb:
17203 case VPMINSDZ256rmbk:
17204 case VPMINSDZ256rmbkz:
17205 case VPMINSDZ256rmk:
17206 case VPMINSDZ256rmkz:
17207 case VPMINSDZ256rr:
17208 case VPMINSDZ256rrk:
17209 case VPMINSDZ256rrkz:
17210 case VPMINSDZrm:
17211 case VPMINSDZrmb:
17212 case VPMINSDZrmbk:
17213 case VPMINSDZrmbkz:
17214 case VPMINSDZrmk:
17215 case VPMINSDZrmkz:
17216 case VPMINSDZrr:
17217 case VPMINSDZrrk:
17218 case VPMINSDZrrkz:
17219 case VPMINSDrm:
17220 case VPMINSDrr:
17221 return true;
17222 }
17223 return false;
17224}
17225
17226bool isVHADDPS(unsigned Opcode) {
17227 switch (Opcode) {
17228 case VHADDPSYrm:
17229 case VHADDPSYrr:
17230 case VHADDPSrm:
17231 case VHADDPSrr:
17232 return true;
17233 }
17234 return false;
17235}
17236
17237bool isVMOVNTDQ(unsigned Opcode) {
17238 switch (Opcode) {
17239 case VMOVNTDQYmr:
17240 case VMOVNTDQZ128mr:
17241 case VMOVNTDQZ256mr:
17242 case VMOVNTDQZmr:
17243 case VMOVNTDQmr:
17244 return true;
17245 }
17246 return false;
17247}
17248
17249bool isVFRCZSD(unsigned Opcode) {
17250 switch (Opcode) {
17251 case VFRCZSDrm:
17252 case VFRCZSDrr:
17253 return true;
17254 }
17255 return false;
17256}
17257
17258bool isIBHF(unsigned Opcode) {
17259 return Opcode == IBHF;
17260}
17261
17262bool isVPTESTMW(unsigned Opcode) {
17263 switch (Opcode) {
17264 case VPTESTMWZ128rm:
17265 case VPTESTMWZ128rmk:
17266 case VPTESTMWZ128rr:
17267 case VPTESTMWZ128rrk:
17268 case VPTESTMWZ256rm:
17269 case VPTESTMWZ256rmk:
17270 case VPTESTMWZ256rr:
17271 case VPTESTMWZ256rrk:
17272 case VPTESTMWZrm:
17273 case VPTESTMWZrmk:
17274 case VPTESTMWZrr:
17275 case VPTESTMWZrrk:
17276 return true;
17277 }
17278 return false;
17279}
17280
17281bool isVPMOVZXWD(unsigned Opcode) {
17282 switch (Opcode) {
17283 case VPMOVZXWDYrm:
17284 case VPMOVZXWDYrr:
17285 case VPMOVZXWDZ128rm:
17286 case VPMOVZXWDZ128rmk:
17287 case VPMOVZXWDZ128rmkz:
17288 case VPMOVZXWDZ128rr:
17289 case VPMOVZXWDZ128rrk:
17290 case VPMOVZXWDZ128rrkz:
17291 case VPMOVZXWDZ256rm:
17292 case VPMOVZXWDZ256rmk:
17293 case VPMOVZXWDZ256rmkz:
17294 case VPMOVZXWDZ256rr:
17295 case VPMOVZXWDZ256rrk:
17296 case VPMOVZXWDZ256rrkz:
17297 case VPMOVZXWDZrm:
17298 case VPMOVZXWDZrmk:
17299 case VPMOVZXWDZrmkz:
17300 case VPMOVZXWDZrr:
17301 case VPMOVZXWDZrrk:
17302 case VPMOVZXWDZrrkz:
17303 case VPMOVZXWDrm:
17304 case VPMOVZXWDrr:
17305 return true;
17306 }
17307 return false;
17308}
17309
17310bool isPSADBW(unsigned Opcode) {
17311 switch (Opcode) {
17312 case MMX_PSADBWrm:
17313 case MMX_PSADBWrr:
17314 case PSADBWrm:
17315 case PSADBWrr:
17316 return true;
17317 }
17318 return false;
17319}
17320
17321bool isVCVTSD2SI(unsigned Opcode) {
17322 switch (Opcode) {
17323 case VCVTSD2SI64Zrm_Int:
17324 case VCVTSD2SI64Zrr_Int:
17325 case VCVTSD2SI64Zrrb_Int:
17326 case VCVTSD2SI64rm_Int:
17327 case VCVTSD2SI64rr_Int:
17328 case VCVTSD2SIZrm_Int:
17329 case VCVTSD2SIZrr_Int:
17330 case VCVTSD2SIZrrb_Int:
17331 case VCVTSD2SIrm_Int:
17332 case VCVTSD2SIrr_Int:
17333 return true;
17334 }
17335 return false;
17336}
17337
17338bool isVMAXPH(unsigned Opcode) {
17339 switch (Opcode) {
17340 case VMAXPHZ128rm:
17341 case VMAXPHZ128rmb:
17342 case VMAXPHZ128rmbk:
17343 case VMAXPHZ128rmbkz:
17344 case VMAXPHZ128rmk:
17345 case VMAXPHZ128rmkz:
17346 case VMAXPHZ128rr:
17347 case VMAXPHZ128rrk:
17348 case VMAXPHZ128rrkz:
17349 case VMAXPHZ256rm:
17350 case VMAXPHZ256rmb:
17351 case VMAXPHZ256rmbk:
17352 case VMAXPHZ256rmbkz:
17353 case VMAXPHZ256rmk:
17354 case VMAXPHZ256rmkz:
17355 case VMAXPHZ256rr:
17356 case VMAXPHZ256rrk:
17357 case VMAXPHZ256rrkz:
17358 case VMAXPHZrm:
17359 case VMAXPHZrmb:
17360 case VMAXPHZrmbk:
17361 case VMAXPHZrmbkz:
17362 case VMAXPHZrmk:
17363 case VMAXPHZrmkz:
17364 case VMAXPHZrr:
17365 case VMAXPHZrrb:
17366 case VMAXPHZrrbk:
17367 case VMAXPHZrrbkz:
17368 case VMAXPHZrrk:
17369 case VMAXPHZrrkz:
17370 return true;
17371 }
17372 return false;
17373}
17374
17375bool isLODSB(unsigned Opcode) {
17376 return Opcode == LODSB;
17377}
17378
17379bool isPHMINPOSUW(unsigned Opcode) {
17380 switch (Opcode) {
17381 case PHMINPOSUWrm:
17382 case PHMINPOSUWrr:
17383 return true;
17384 }
17385 return false;
17386}
17387
17388bool isVPROLVD(unsigned Opcode) {
17389 switch (Opcode) {
17390 case VPROLVDZ128rm:
17391 case VPROLVDZ128rmb:
17392 case VPROLVDZ128rmbk:
17393 case VPROLVDZ128rmbkz:
17394 case VPROLVDZ128rmk:
17395 case VPROLVDZ128rmkz:
17396 case VPROLVDZ128rr:
17397 case VPROLVDZ128rrk:
17398 case VPROLVDZ128rrkz:
17399 case VPROLVDZ256rm:
17400 case VPROLVDZ256rmb:
17401 case VPROLVDZ256rmbk:
17402 case VPROLVDZ256rmbkz:
17403 case VPROLVDZ256rmk:
17404 case VPROLVDZ256rmkz:
17405 case VPROLVDZ256rr:
17406 case VPROLVDZ256rrk:
17407 case VPROLVDZ256rrkz:
17408 case VPROLVDZrm:
17409 case VPROLVDZrmb:
17410 case VPROLVDZrmbk:
17411 case VPROLVDZrmbkz:
17412 case VPROLVDZrmk:
17413 case VPROLVDZrmkz:
17414 case VPROLVDZrr:
17415 case VPROLVDZrrk:
17416 case VPROLVDZrrkz:
17417 return true;
17418 }
17419 return false;
17420}
17421
17422bool isWRFSBASE(unsigned Opcode) {
17423 switch (Opcode) {
17424 case WRFSBASE:
17425 case WRFSBASE64:
17426 return true;
17427 }
17428 return false;
17429}
17430
17431bool isVRSQRT14PS(unsigned Opcode) {
17432 switch (Opcode) {
17433 case VRSQRT14PSZ128m:
17434 case VRSQRT14PSZ128mb:
17435 case VRSQRT14PSZ128mbk:
17436 case VRSQRT14PSZ128mbkz:
17437 case VRSQRT14PSZ128mk:
17438 case VRSQRT14PSZ128mkz:
17439 case VRSQRT14PSZ128r:
17440 case VRSQRT14PSZ128rk:
17441 case VRSQRT14PSZ128rkz:
17442 case VRSQRT14PSZ256m:
17443 case VRSQRT14PSZ256mb:
17444 case VRSQRT14PSZ256mbk:
17445 case VRSQRT14PSZ256mbkz:
17446 case VRSQRT14PSZ256mk:
17447 case VRSQRT14PSZ256mkz:
17448 case VRSQRT14PSZ256r:
17449 case VRSQRT14PSZ256rk:
17450 case VRSQRT14PSZ256rkz:
17451 case VRSQRT14PSZm:
17452 case VRSQRT14PSZmb:
17453 case VRSQRT14PSZmbk:
17454 case VRSQRT14PSZmbkz:
17455 case VRSQRT14PSZmk:
17456 case VRSQRT14PSZmkz:
17457 case VRSQRT14PSZr:
17458 case VRSQRT14PSZrk:
17459 case VRSQRT14PSZrkz:
17460 return true;
17461 }
17462 return false;
17463}
17464
17465bool isVPHSUBDQ(unsigned Opcode) {
17466 switch (Opcode) {
17467 case VPHSUBDQrm:
17468 case VPHSUBDQrr:
17469 return true;
17470 }
17471 return false;
17472}
17473
17474bool isIRETD(unsigned Opcode) {
17475 return Opcode == IRET32;
17476}
17477
17478bool isVMOVRSD(unsigned Opcode) {
17479 switch (Opcode) {
17480 case VMOVRSDZ128m:
17481 case VMOVRSDZ128mk:
17482 case VMOVRSDZ128mkz:
17483 case VMOVRSDZ256m:
17484 case VMOVRSDZ256mk:
17485 case VMOVRSDZ256mkz:
17486 case VMOVRSDZm:
17487 case VMOVRSDZmk:
17488 case VMOVRSDZmkz:
17489 return true;
17490 }
17491 return false;
17492}
17493
17494bool isVPMULHRSW(unsigned Opcode) {
17495 switch (Opcode) {
17496 case VPMULHRSWYrm:
17497 case VPMULHRSWYrr:
17498 case VPMULHRSWZ128rm:
17499 case VPMULHRSWZ128rmk:
17500 case VPMULHRSWZ128rmkz:
17501 case VPMULHRSWZ128rr:
17502 case VPMULHRSWZ128rrk:
17503 case VPMULHRSWZ128rrkz:
17504 case VPMULHRSWZ256rm:
17505 case VPMULHRSWZ256rmk:
17506 case VPMULHRSWZ256rmkz:
17507 case VPMULHRSWZ256rr:
17508 case VPMULHRSWZ256rrk:
17509 case VPMULHRSWZ256rrkz:
17510 case VPMULHRSWZrm:
17511 case VPMULHRSWZrmk:
17512 case VPMULHRSWZrmkz:
17513 case VPMULHRSWZrr:
17514 case VPMULHRSWZrrk:
17515 case VPMULHRSWZrrkz:
17516 case VPMULHRSWrm:
17517 case VPMULHRSWrr:
17518 return true;
17519 }
17520 return false;
17521}
17522
17523bool isCVTSI2SS(unsigned Opcode) {
17524 switch (Opcode) {
17525 case CVTSI2SSrm_Int:
17526 case CVTSI2SSrr_Int:
17527 case CVTSI642SSrm_Int:
17528 case CVTSI642SSrr_Int:
17529 return true;
17530 }
17531 return false;
17532}
17533
17534bool isPI2FD(unsigned Opcode) {
17535 switch (Opcode) {
17536 case PI2FDrm:
17537 case PI2FDrr:
17538 return true;
17539 }
17540 return false;
17541}
17542
17543bool isGF2P8AFFINEQB(unsigned Opcode) {
17544 switch (Opcode) {
17545 case GF2P8AFFINEQBrmi:
17546 case GF2P8AFFINEQBrri:
17547 return true;
17548 }
17549 return false;
17550}
17551
17552bool isPAND(unsigned Opcode) {
17553 switch (Opcode) {
17554 case MMX_PANDrm:
17555 case MMX_PANDrr:
17556 case PANDrm:
17557 case PANDrr:
17558 return true;
17559 }
17560 return false;
17561}
17562
17563bool isVFNMSUB231SH(unsigned Opcode) {
17564 switch (Opcode) {
17565 case VFNMSUB231SHZm_Int:
17566 case VFNMSUB231SHZmk_Int:
17567 case VFNMSUB231SHZmkz_Int:
17568 case VFNMSUB231SHZr_Int:
17569 case VFNMSUB231SHZrb_Int:
17570 case VFNMSUB231SHZrbk_Int:
17571 case VFNMSUB231SHZrbkz_Int:
17572 case VFNMSUB231SHZrk_Int:
17573 case VFNMSUB231SHZrkz_Int:
17574 return true;
17575 }
17576 return false;
17577}
17578
17579bool isVMOVHLPS(unsigned Opcode) {
17580 switch (Opcode) {
17581 case VMOVHLPSZrr:
17582 case VMOVHLPSrr:
17583 return true;
17584 }
17585 return false;
17586}
17587
17588bool isKNOTD(unsigned Opcode) {
17589 return Opcode == KNOTDkk;
17590}
17591
17592bool isPEXTRB(unsigned Opcode) {
17593 switch (Opcode) {
17594 case PEXTRBmri:
17595 case PEXTRBrri:
17596 return true;
17597 }
17598 return false;
17599}
17600
17601bool isVCVTPH2BF8(unsigned Opcode) {
17602 switch (Opcode) {
17603 case VCVTPH2BF8Z128rm:
17604 case VCVTPH2BF8Z128rmb:
17605 case VCVTPH2BF8Z128rmbk:
17606 case VCVTPH2BF8Z128rmbkz:
17607 case VCVTPH2BF8Z128rmk:
17608 case VCVTPH2BF8Z128rmkz:
17609 case VCVTPH2BF8Z128rr:
17610 case VCVTPH2BF8Z128rrk:
17611 case VCVTPH2BF8Z128rrkz:
17612 case VCVTPH2BF8Z256rm:
17613 case VCVTPH2BF8Z256rmb:
17614 case VCVTPH2BF8Z256rmbk:
17615 case VCVTPH2BF8Z256rmbkz:
17616 case VCVTPH2BF8Z256rmk:
17617 case VCVTPH2BF8Z256rmkz:
17618 case VCVTPH2BF8Z256rr:
17619 case VCVTPH2BF8Z256rrk:
17620 case VCVTPH2BF8Z256rrkz:
17621 case VCVTPH2BF8Zrm:
17622 case VCVTPH2BF8Zrmb:
17623 case VCVTPH2BF8Zrmbk:
17624 case VCVTPH2BF8Zrmbkz:
17625 case VCVTPH2BF8Zrmk:
17626 case VCVTPH2BF8Zrmkz:
17627 case VCVTPH2BF8Zrr:
17628 case VCVTPH2BF8Zrrk:
17629 case VCVTPH2BF8Zrrkz:
17630 return true;
17631 }
17632 return false;
17633}
17634
17635bool isVMMCALL(unsigned Opcode) {
17636 return Opcode == VMMCALL;
17637}
17638
17639bool isVCVTSH2SS(unsigned Opcode) {
17640 switch (Opcode) {
17641 case VCVTSH2SSZrm_Int:
17642 case VCVTSH2SSZrmk_Int:
17643 case VCVTSH2SSZrmkz_Int:
17644 case VCVTSH2SSZrr_Int:
17645 case VCVTSH2SSZrrb_Int:
17646 case VCVTSH2SSZrrbk_Int:
17647 case VCVTSH2SSZrrbkz_Int:
17648 case VCVTSH2SSZrrk_Int:
17649 case VCVTSH2SSZrrkz_Int:
17650 return true;
17651 }
17652 return false;
17653}
17654
17655bool isVPUNPCKLQDQ(unsigned Opcode) {
17656 switch (Opcode) {
17657 case VPUNPCKLQDQYrm:
17658 case VPUNPCKLQDQYrr:
17659 case VPUNPCKLQDQZ128rm:
17660 case VPUNPCKLQDQZ128rmb:
17661 case VPUNPCKLQDQZ128rmbk:
17662 case VPUNPCKLQDQZ128rmbkz:
17663 case VPUNPCKLQDQZ128rmk:
17664 case VPUNPCKLQDQZ128rmkz:
17665 case VPUNPCKLQDQZ128rr:
17666 case VPUNPCKLQDQZ128rrk:
17667 case VPUNPCKLQDQZ128rrkz:
17668 case VPUNPCKLQDQZ256rm:
17669 case VPUNPCKLQDQZ256rmb:
17670 case VPUNPCKLQDQZ256rmbk:
17671 case VPUNPCKLQDQZ256rmbkz:
17672 case VPUNPCKLQDQZ256rmk:
17673 case VPUNPCKLQDQZ256rmkz:
17674 case VPUNPCKLQDQZ256rr:
17675 case VPUNPCKLQDQZ256rrk:
17676 case VPUNPCKLQDQZ256rrkz:
17677 case VPUNPCKLQDQZrm:
17678 case VPUNPCKLQDQZrmb:
17679 case VPUNPCKLQDQZrmbk:
17680 case VPUNPCKLQDQZrmbkz:
17681 case VPUNPCKLQDQZrmk:
17682 case VPUNPCKLQDQZrmkz:
17683 case VPUNPCKLQDQZrr:
17684 case VPUNPCKLQDQZrrk:
17685 case VPUNPCKLQDQZrrkz:
17686 case VPUNPCKLQDQrm:
17687 case VPUNPCKLQDQrr:
17688 return true;
17689 }
17690 return false;
17691}
17692
17693bool isVPERMIL2PS(unsigned Opcode) {
17694 switch (Opcode) {
17695 case VPERMIL2PSYmr:
17696 case VPERMIL2PSYrm:
17697 case VPERMIL2PSYrr:
17698 case VPERMIL2PSYrr_REV:
17699 case VPERMIL2PSmr:
17700 case VPERMIL2PSrm:
17701 case VPERMIL2PSrr:
17702 case VPERMIL2PSrr_REV:
17703 return true;
17704 }
17705 return false;
17706}
17707
17708bool isVPCMPGTD(unsigned Opcode) {
17709 switch (Opcode) {
17710 case VPCMPGTDYrm:
17711 case VPCMPGTDYrr:
17712 case VPCMPGTDZ128rm:
17713 case VPCMPGTDZ128rmb:
17714 case VPCMPGTDZ128rmbk:
17715 case VPCMPGTDZ128rmk:
17716 case VPCMPGTDZ128rr:
17717 case VPCMPGTDZ128rrk:
17718 case VPCMPGTDZ256rm:
17719 case VPCMPGTDZ256rmb:
17720 case VPCMPGTDZ256rmbk:
17721 case VPCMPGTDZ256rmk:
17722 case VPCMPGTDZ256rr:
17723 case VPCMPGTDZ256rrk:
17724 case VPCMPGTDZrm:
17725 case VPCMPGTDZrmb:
17726 case VPCMPGTDZrmbk:
17727 case VPCMPGTDZrmk:
17728 case VPCMPGTDZrr:
17729 case VPCMPGTDZrrk:
17730 case VPCMPGTDrm:
17731 case VPCMPGTDrr:
17732 return true;
17733 }
17734 return false;
17735}
17736
17737bool isCMPXCHG16B(unsigned Opcode) {
17738 return Opcode == CMPXCHG16B;
17739}
17740
17741bool isTDPHF8PS(unsigned Opcode) {
17742 return Opcode == TDPHF8PS;
17743}
17744
17745bool isVZEROUPPER(unsigned Opcode) {
17746 return Opcode == VZEROUPPER;
17747}
17748
17749bool isMOVAPS(unsigned Opcode) {
17750 switch (Opcode) {
17751 case MOVAPSmr:
17752 case MOVAPSrm:
17753 case MOVAPSrr:
17754 case MOVAPSrr_REV:
17755 return true;
17756 }
17757 return false;
17758}
17759
17760bool isVPCMPW(unsigned Opcode) {
17761 switch (Opcode) {
17762 case VPCMPWZ128rmi:
17763 case VPCMPWZ128rmik:
17764 case VPCMPWZ128rri:
17765 case VPCMPWZ128rrik:
17766 case VPCMPWZ256rmi:
17767 case VPCMPWZ256rmik:
17768 case VPCMPWZ256rri:
17769 case VPCMPWZ256rrik:
17770 case VPCMPWZrmi:
17771 case VPCMPWZrmik:
17772 case VPCMPWZrri:
17773 case VPCMPWZrrik:
17774 return true;
17775 }
17776 return false;
17777}
17778
17779bool isFUCOMPP(unsigned Opcode) {
17780 return Opcode == UCOM_FPPr;
17781}
17782
17783bool isXSETBV(unsigned Opcode) {
17784 return Opcode == XSETBV;
17785}
17786
17787bool isSLWPCB(unsigned Opcode) {
17788 switch (Opcode) {
17789 case SLWPCB:
17790 case SLWPCB64:
17791 return true;
17792 }
17793 return false;
17794}
17795
17796bool isSCASW(unsigned Opcode) {
17797 return Opcode == SCASW;
17798}
17799
17800bool isFCMOVNE(unsigned Opcode) {
17801 return Opcode == CMOVNE_F;
17802}
17803
17804bool isPBNDKB(unsigned Opcode) {
17805 return Opcode == PBNDKB;
17806}
17807
17808bool isVPMULLD(unsigned Opcode) {
17809 switch (Opcode) {
17810 case VPMULLDYrm:
17811 case VPMULLDYrr:
17812 case VPMULLDZ128rm:
17813 case VPMULLDZ128rmb:
17814 case VPMULLDZ128rmbk:
17815 case VPMULLDZ128rmbkz:
17816 case VPMULLDZ128rmk:
17817 case VPMULLDZ128rmkz:
17818 case VPMULLDZ128rr:
17819 case VPMULLDZ128rrk:
17820 case VPMULLDZ128rrkz:
17821 case VPMULLDZ256rm:
17822 case VPMULLDZ256rmb:
17823 case VPMULLDZ256rmbk:
17824 case VPMULLDZ256rmbkz:
17825 case VPMULLDZ256rmk:
17826 case VPMULLDZ256rmkz:
17827 case VPMULLDZ256rr:
17828 case VPMULLDZ256rrk:
17829 case VPMULLDZ256rrkz:
17830 case VPMULLDZrm:
17831 case VPMULLDZrmb:
17832 case VPMULLDZrmbk:
17833 case VPMULLDZrmbkz:
17834 case VPMULLDZrmk:
17835 case VPMULLDZrmkz:
17836 case VPMULLDZrr:
17837 case VPMULLDZrrk:
17838 case VPMULLDZrrkz:
17839 case VPMULLDrm:
17840 case VPMULLDrr:
17841 return true;
17842 }
17843 return false;
17844}
17845
17846bool isVP4DPWSSDS(unsigned Opcode) {
17847 switch (Opcode) {
17848 case VP4DPWSSDSrm:
17849 case VP4DPWSSDSrmk:
17850 case VP4DPWSSDSrmkz:
17851 return true;
17852 }
17853 return false;
17854}
17855
17856bool isVCVT2PH2HF8(unsigned Opcode) {
17857 switch (Opcode) {
17858 case VCVT2PH2HF8Z128rm:
17859 case VCVT2PH2HF8Z128rmb:
17860 case VCVT2PH2HF8Z128rmbk:
17861 case VCVT2PH2HF8Z128rmbkz:
17862 case VCVT2PH2HF8Z128rmk:
17863 case VCVT2PH2HF8Z128rmkz:
17864 case VCVT2PH2HF8Z128rr:
17865 case VCVT2PH2HF8Z128rrk:
17866 case VCVT2PH2HF8Z128rrkz:
17867 case VCVT2PH2HF8Z256rm:
17868 case VCVT2PH2HF8Z256rmb:
17869 case VCVT2PH2HF8Z256rmbk:
17870 case VCVT2PH2HF8Z256rmbkz:
17871 case VCVT2PH2HF8Z256rmk:
17872 case VCVT2PH2HF8Z256rmkz:
17873 case VCVT2PH2HF8Z256rr:
17874 case VCVT2PH2HF8Z256rrk:
17875 case VCVT2PH2HF8Z256rrkz:
17876 case VCVT2PH2HF8Zrm:
17877 case VCVT2PH2HF8Zrmb:
17878 case VCVT2PH2HF8Zrmbk:
17879 case VCVT2PH2HF8Zrmbkz:
17880 case VCVT2PH2HF8Zrmk:
17881 case VCVT2PH2HF8Zrmkz:
17882 case VCVT2PH2HF8Zrr:
17883 case VCVT2PH2HF8Zrrk:
17884 case VCVT2PH2HF8Zrrkz:
17885 return true;
17886 }
17887 return false;
17888}
17889
17890bool isPINSRW(unsigned Opcode) {
17891 switch (Opcode) {
17892 case MMX_PINSRWrmi:
17893 case MMX_PINSRWrri:
17894 case PINSRWrmi:
17895 case PINSRWrri:
17896 return true;
17897 }
17898 return false;
17899}
17900
17901bool isVCVTSI2SH(unsigned Opcode) {
17902 switch (Opcode) {
17903 case VCVTSI2SHZrm_Int:
17904 case VCVTSI2SHZrr_Int:
17905 case VCVTSI2SHZrrb_Int:
17906 case VCVTSI642SHZrm_Int:
17907 case VCVTSI642SHZrr_Int:
17908 case VCVTSI642SHZrrb_Int:
17909 return true;
17910 }
17911 return false;
17912}
17913
17914bool isVINSERTF32X8(unsigned Opcode) {
17915 switch (Opcode) {
17916 case VINSERTF32X8Zrmi:
17917 case VINSERTF32X8Zrmik:
17918 case VINSERTF32X8Zrmikz:
17919 case VINSERTF32X8Zrri:
17920 case VINSERTF32X8Zrrik:
17921 case VINSERTF32X8Zrrikz:
17922 return true;
17923 }
17924 return false;
17925}
17926
17927bool isKSHIFTLB(unsigned Opcode) {
17928 return Opcode == KSHIFTLBki;
17929}
17930
17931bool isSEAMOPS(unsigned Opcode) {
17932 return Opcode == SEAMOPS;
17933}
17934
17935bool isVPMOVSQB(unsigned Opcode) {
17936 switch (Opcode) {
17937 case VPMOVSQBZ128mr:
17938 case VPMOVSQBZ128mrk:
17939 case VPMOVSQBZ128rr:
17940 case VPMOVSQBZ128rrk:
17941 case VPMOVSQBZ128rrkz:
17942 case VPMOVSQBZ256mr:
17943 case VPMOVSQBZ256mrk:
17944 case VPMOVSQBZ256rr:
17945 case VPMOVSQBZ256rrk:
17946 case VPMOVSQBZ256rrkz:
17947 case VPMOVSQBZmr:
17948 case VPMOVSQBZmrk:
17949 case VPMOVSQBZrr:
17950 case VPMOVSQBZrrk:
17951 case VPMOVSQBZrrkz:
17952 return true;
17953 }
17954 return false;
17955}
17956
17957bool isVPMULUDQ(unsigned Opcode) {
17958 switch (Opcode) {
17959 case VPMULUDQYrm:
17960 case VPMULUDQYrr:
17961 case VPMULUDQZ128rm:
17962 case VPMULUDQZ128rmb:
17963 case VPMULUDQZ128rmbk:
17964 case VPMULUDQZ128rmbkz:
17965 case VPMULUDQZ128rmk:
17966 case VPMULUDQZ128rmkz:
17967 case VPMULUDQZ128rr:
17968 case VPMULUDQZ128rrk:
17969 case VPMULUDQZ128rrkz:
17970 case VPMULUDQZ256rm:
17971 case VPMULUDQZ256rmb:
17972 case VPMULUDQZ256rmbk:
17973 case VPMULUDQZ256rmbkz:
17974 case VPMULUDQZ256rmk:
17975 case VPMULUDQZ256rmkz:
17976 case VPMULUDQZ256rr:
17977 case VPMULUDQZ256rrk:
17978 case VPMULUDQZ256rrkz:
17979 case VPMULUDQZrm:
17980 case VPMULUDQZrmb:
17981 case VPMULUDQZrmbk:
17982 case VPMULUDQZrmbkz:
17983 case VPMULUDQZrmk:
17984 case VPMULUDQZrmkz:
17985 case VPMULUDQZrr:
17986 case VPMULUDQZrrk:
17987 case VPMULUDQZrrkz:
17988 case VPMULUDQrm:
17989 case VPMULUDQrr:
17990 return true;
17991 }
17992 return false;
17993}
17994
17995bool isVPTESTMD(unsigned Opcode) {
17996 switch (Opcode) {
17997 case VPTESTMDZ128rm:
17998 case VPTESTMDZ128rmb:
17999 case VPTESTMDZ128rmbk:
18000 case VPTESTMDZ128rmk:
18001 case VPTESTMDZ128rr:
18002 case VPTESTMDZ128rrk:
18003 case VPTESTMDZ256rm:
18004 case VPTESTMDZ256rmb:
18005 case VPTESTMDZ256rmbk:
18006 case VPTESTMDZ256rmk:
18007 case VPTESTMDZ256rr:
18008 case VPTESTMDZ256rrk:
18009 case VPTESTMDZrm:
18010 case VPTESTMDZrmb:
18011 case VPTESTMDZrmbk:
18012 case VPTESTMDZrmk:
18013 case VPTESTMDZrr:
18014 case VPTESTMDZrrk:
18015 return true;
18016 }
18017 return false;
18018}
18019
18020bool isVPHADDDQ(unsigned Opcode) {
18021 switch (Opcode) {
18022 case VPHADDDQrm:
18023 case VPHADDDQrr:
18024 return true;
18025 }
18026 return false;
18027}
18028
18029bool isKUNPCKDQ(unsigned Opcode) {
18030 return Opcode == KUNPCKDQkk;
18031}
18032
18033bool isT1MSKC(unsigned Opcode) {
18034 switch (Opcode) {
18035 case T1MSKC32rm:
18036 case T1MSKC32rr:
18037 case T1MSKC64rm:
18038 case T1MSKC64rr:
18039 return true;
18040 }
18041 return false;
18042}
18043
18044bool isVBLENDPS(unsigned Opcode) {
18045 switch (Opcode) {
18046 case VBLENDPSYrmi:
18047 case VBLENDPSYrri:
18048 case VBLENDPSrmi:
18049 case VBLENDPSrri:
18050 return true;
18051 }
18052 return false;
18053}
18054
18055bool isVPCOMB(unsigned Opcode) {
18056 switch (Opcode) {
18057 case VPCOMBmi:
18058 case VPCOMBri:
18059 return true;
18060 }
18061 return false;
18062}
18063
18064bool isPTWRITE(unsigned Opcode) {
18065 switch (Opcode) {
18066 case PTWRITE64m:
18067 case PTWRITE64r:
18068 case PTWRITEm:
18069 case PTWRITEr:
18070 return true;
18071 }
18072 return false;
18073}
18074
18075bool isVCVTPH2BF8S(unsigned Opcode) {
18076 switch (Opcode) {
18077 case VCVTPH2BF8SZ128rm:
18078 case VCVTPH2BF8SZ128rmb:
18079 case VCVTPH2BF8SZ128rmbk:
18080 case VCVTPH2BF8SZ128rmbkz:
18081 case VCVTPH2BF8SZ128rmk:
18082 case VCVTPH2BF8SZ128rmkz:
18083 case VCVTPH2BF8SZ128rr:
18084 case VCVTPH2BF8SZ128rrk:
18085 case VCVTPH2BF8SZ128rrkz:
18086 case VCVTPH2BF8SZ256rm:
18087 case VCVTPH2BF8SZ256rmb:
18088 case VCVTPH2BF8SZ256rmbk:
18089 case VCVTPH2BF8SZ256rmbkz:
18090 case VCVTPH2BF8SZ256rmk:
18091 case VCVTPH2BF8SZ256rmkz:
18092 case VCVTPH2BF8SZ256rr:
18093 case VCVTPH2BF8SZ256rrk:
18094 case VCVTPH2BF8SZ256rrkz:
18095 case VCVTPH2BF8SZrm:
18096 case VCVTPH2BF8SZrmb:
18097 case VCVTPH2BF8SZrmbk:
18098 case VCVTPH2BF8SZrmbkz:
18099 case VCVTPH2BF8SZrmk:
18100 case VCVTPH2BF8SZrmkz:
18101 case VCVTPH2BF8SZrr:
18102 case VCVTPH2BF8SZrrk:
18103 case VCVTPH2BF8SZrrkz:
18104 return true;
18105 }
18106 return false;
18107}
18108
18109bool isCVTPS2PI(unsigned Opcode) {
18110 switch (Opcode) {
18111 case MMX_CVTPS2PIrm:
18112 case MMX_CVTPS2PIrr:
18113 return true;
18114 }
18115 return false;
18116}
18117
18118bool isVPROTD(unsigned Opcode) {
18119 switch (Opcode) {
18120 case VPROTDmi:
18121 case VPROTDmr:
18122 case VPROTDri:
18123 case VPROTDrm:
18124 case VPROTDrr:
18125 case VPROTDrr_REV:
18126 return true;
18127 }
18128 return false;
18129}
18130
18131bool isCALL(unsigned Opcode) {
18132 switch (Opcode) {
18133 case CALL16m:
18134 case CALL16r:
18135 case CALL32m:
18136 case CALL32r:
18137 case CALL64m:
18138 case CALL64pcrel32:
18139 case CALL64r:
18140 case CALLpcrel16:
18141 case CALLpcrel32:
18142 case FARCALL32m:
18143 return true;
18144 }
18145 return false;
18146}
18147
18148bool isTILELOADDRST1(unsigned Opcode) {
18149 switch (Opcode) {
18150 case TILELOADDRST1:
18151 case TILELOADDRST1_EVEX:
18152 return true;
18153 }
18154 return false;
18155}
18156
18157bool isVPERMPS(unsigned Opcode) {
18158 switch (Opcode) {
18159 case VPERMPSYrm:
18160 case VPERMPSYrr:
18161 case VPERMPSZ256rm:
18162 case VPERMPSZ256rmb:
18163 case VPERMPSZ256rmbk:
18164 case VPERMPSZ256rmbkz:
18165 case VPERMPSZ256rmk:
18166 case VPERMPSZ256rmkz:
18167 case VPERMPSZ256rr:
18168 case VPERMPSZ256rrk:
18169 case VPERMPSZ256rrkz:
18170 case VPERMPSZrm:
18171 case VPERMPSZrmb:
18172 case VPERMPSZrmbk:
18173 case VPERMPSZrmbkz:
18174 case VPERMPSZrmk:
18175 case VPERMPSZrmkz:
18176 case VPERMPSZrr:
18177 case VPERMPSZrrk:
18178 case VPERMPSZrrkz:
18179 return true;
18180 }
18181 return false;
18182}
18183
18184bool isVPSHUFBITQMB(unsigned Opcode) {
18185 switch (Opcode) {
18186 case VPSHUFBITQMBZ128rm:
18187 case VPSHUFBITQMBZ128rmk:
18188 case VPSHUFBITQMBZ128rr:
18189 case VPSHUFBITQMBZ128rrk:
18190 case VPSHUFBITQMBZ256rm:
18191 case VPSHUFBITQMBZ256rmk:
18192 case VPSHUFBITQMBZ256rr:
18193 case VPSHUFBITQMBZ256rrk:
18194 case VPSHUFBITQMBZrm:
18195 case VPSHUFBITQMBZrmk:
18196 case VPSHUFBITQMBZrr:
18197 case VPSHUFBITQMBZrrk:
18198 return true;
18199 }
18200 return false;
18201}
18202
18203bool isVMOVSLDUP(unsigned Opcode) {
18204 switch (Opcode) {
18205 case VMOVSLDUPYrm:
18206 case VMOVSLDUPYrr:
18207 case VMOVSLDUPZ128rm:
18208 case VMOVSLDUPZ128rmk:
18209 case VMOVSLDUPZ128rmkz:
18210 case VMOVSLDUPZ128rr:
18211 case VMOVSLDUPZ128rrk:
18212 case VMOVSLDUPZ128rrkz:
18213 case VMOVSLDUPZ256rm:
18214 case VMOVSLDUPZ256rmk:
18215 case VMOVSLDUPZ256rmkz:
18216 case VMOVSLDUPZ256rr:
18217 case VMOVSLDUPZ256rrk:
18218 case VMOVSLDUPZ256rrkz:
18219 case VMOVSLDUPZrm:
18220 case VMOVSLDUPZrmk:
18221 case VMOVSLDUPZrmkz:
18222 case VMOVSLDUPZrr:
18223 case VMOVSLDUPZrrk:
18224 case VMOVSLDUPZrrkz:
18225 case VMOVSLDUPrm:
18226 case VMOVSLDUPrr:
18227 return true;
18228 }
18229 return false;
18230}
18231
18232bool isINVLPGA(unsigned Opcode) {
18233 switch (Opcode) {
18234 case INVLPGA32:
18235 case INVLPGA64:
18236 return true;
18237 }
18238 return false;
18239}
18240
18241bool isVCVTPH2QQ(unsigned Opcode) {
18242 switch (Opcode) {
18243 case VCVTPH2QQZ128rm:
18244 case VCVTPH2QQZ128rmb:
18245 case VCVTPH2QQZ128rmbk:
18246 case VCVTPH2QQZ128rmbkz:
18247 case VCVTPH2QQZ128rmk:
18248 case VCVTPH2QQZ128rmkz:
18249 case VCVTPH2QQZ128rr:
18250 case VCVTPH2QQZ128rrk:
18251 case VCVTPH2QQZ128rrkz:
18252 case VCVTPH2QQZ256rm:
18253 case VCVTPH2QQZ256rmb:
18254 case VCVTPH2QQZ256rmbk:
18255 case VCVTPH2QQZ256rmbkz:
18256 case VCVTPH2QQZ256rmk:
18257 case VCVTPH2QQZ256rmkz:
18258 case VCVTPH2QQZ256rr:
18259 case VCVTPH2QQZ256rrk:
18260 case VCVTPH2QQZ256rrkz:
18261 case VCVTPH2QQZrm:
18262 case VCVTPH2QQZrmb:
18263 case VCVTPH2QQZrmbk:
18264 case VCVTPH2QQZrmbkz:
18265 case VCVTPH2QQZrmk:
18266 case VCVTPH2QQZrmkz:
18267 case VCVTPH2QQZrr:
18268 case VCVTPH2QQZrrb:
18269 case VCVTPH2QQZrrbk:
18270 case VCVTPH2QQZrrbkz:
18271 case VCVTPH2QQZrrk:
18272 case VCVTPH2QQZrrkz:
18273 return true;
18274 }
18275 return false;
18276}
18277
18278bool isADD(unsigned Opcode) {
18279 switch (Opcode) {
18280 case ADD16i16:
18281 case ADD16mi:
18282 case ADD16mi8:
18283 case ADD16mi8_EVEX:
18284 case ADD16mi8_ND:
18285 case ADD16mi8_NF:
18286 case ADD16mi8_NF_ND:
18287 case ADD16mi_EVEX:
18288 case ADD16mi_ND:
18289 case ADD16mi_NF:
18290 case ADD16mi_NF_ND:
18291 case ADD16mr:
18292 case ADD16mr_EVEX:
18293 case ADD16mr_ND:
18294 case ADD16mr_NF:
18295 case ADD16mr_NF_ND:
18296 case ADD16ri:
18297 case ADD16ri8:
18298 case ADD16ri8_EVEX:
18299 case ADD16ri8_ND:
18300 case ADD16ri8_NF:
18301 case ADD16ri8_NF_ND:
18302 case ADD16ri_EVEX:
18303 case ADD16ri_ND:
18304 case ADD16ri_NF:
18305 case ADD16ri_NF_ND:
18306 case ADD16rm:
18307 case ADD16rm_EVEX:
18308 case ADD16rm_ND:
18309 case ADD16rm_NF:
18310 case ADD16rm_NF_ND:
18311 case ADD16rr:
18312 case ADD16rr_EVEX:
18313 case ADD16rr_EVEX_REV:
18314 case ADD16rr_ND:
18315 case ADD16rr_ND_REV:
18316 case ADD16rr_NF:
18317 case ADD16rr_NF_ND:
18318 case ADD16rr_NF_ND_REV:
18319 case ADD16rr_NF_REV:
18320 case ADD16rr_REV:
18321 case ADD32i32:
18322 case ADD32mi:
18323 case ADD32mi8:
18324 case ADD32mi8_EVEX:
18325 case ADD32mi8_ND:
18326 case ADD32mi8_NF:
18327 case ADD32mi8_NF_ND:
18328 case ADD32mi_EVEX:
18329 case ADD32mi_ND:
18330 case ADD32mi_NF:
18331 case ADD32mi_NF_ND:
18332 case ADD32mr:
18333 case ADD32mr_EVEX:
18334 case ADD32mr_ND:
18335 case ADD32mr_NF:
18336 case ADD32mr_NF_ND:
18337 case ADD32ri:
18338 case ADD32ri8:
18339 case ADD32ri8_EVEX:
18340 case ADD32ri8_ND:
18341 case ADD32ri8_NF:
18342 case ADD32ri8_NF_ND:
18343 case ADD32ri_EVEX:
18344 case ADD32ri_ND:
18345 case ADD32ri_NF:
18346 case ADD32ri_NF_ND:
18347 case ADD32rm:
18348 case ADD32rm_EVEX:
18349 case ADD32rm_ND:
18350 case ADD32rm_NF:
18351 case ADD32rm_NF_ND:
18352 case ADD32rr:
18353 case ADD32rr_EVEX:
18354 case ADD32rr_EVEX_REV:
18355 case ADD32rr_ND:
18356 case ADD32rr_ND_REV:
18357 case ADD32rr_NF:
18358 case ADD32rr_NF_ND:
18359 case ADD32rr_NF_ND_REV:
18360 case ADD32rr_NF_REV:
18361 case ADD32rr_REV:
18362 case ADD64i32:
18363 case ADD64mi32:
18364 case ADD64mi32_EVEX:
18365 case ADD64mi32_ND:
18366 case ADD64mi32_NF:
18367 case ADD64mi32_NF_ND:
18368 case ADD64mi8:
18369 case ADD64mi8_EVEX:
18370 case ADD64mi8_ND:
18371 case ADD64mi8_NF:
18372 case ADD64mi8_NF_ND:
18373 case ADD64mr:
18374 case ADD64mr_EVEX:
18375 case ADD64mr_ND:
18376 case ADD64mr_NF:
18377 case ADD64mr_NF_ND:
18378 case ADD64ri32:
18379 case ADD64ri32_EVEX:
18380 case ADD64ri32_ND:
18381 case ADD64ri32_NF:
18382 case ADD64ri32_NF_ND:
18383 case ADD64ri8:
18384 case ADD64ri8_EVEX:
18385 case ADD64ri8_ND:
18386 case ADD64ri8_NF:
18387 case ADD64ri8_NF_ND:
18388 case ADD64rm:
18389 case ADD64rm_EVEX:
18390 case ADD64rm_ND:
18391 case ADD64rm_NF:
18392 case ADD64rm_NF_ND:
18393 case ADD64rr:
18394 case ADD64rr_EVEX:
18395 case ADD64rr_EVEX_REV:
18396 case ADD64rr_ND:
18397 case ADD64rr_ND_REV:
18398 case ADD64rr_NF:
18399 case ADD64rr_NF_ND:
18400 case ADD64rr_NF_ND_REV:
18401 case ADD64rr_NF_REV:
18402 case ADD64rr_REV:
18403 case ADD8i8:
18404 case ADD8mi:
18405 case ADD8mi8:
18406 case ADD8mi_EVEX:
18407 case ADD8mi_ND:
18408 case ADD8mi_NF:
18409 case ADD8mi_NF_ND:
18410 case ADD8mr:
18411 case ADD8mr_EVEX:
18412 case ADD8mr_ND:
18413 case ADD8mr_NF:
18414 case ADD8mr_NF_ND:
18415 case ADD8ri:
18416 case ADD8ri8:
18417 case ADD8ri_EVEX:
18418 case ADD8ri_ND:
18419 case ADD8ri_NF:
18420 case ADD8ri_NF_ND:
18421 case ADD8rm:
18422 case ADD8rm_EVEX:
18423 case ADD8rm_ND:
18424 case ADD8rm_NF:
18425 case ADD8rm_NF_ND:
18426 case ADD8rr:
18427 case ADD8rr_EVEX:
18428 case ADD8rr_EVEX_REV:
18429 case ADD8rr_ND:
18430 case ADD8rr_ND_REV:
18431 case ADD8rr_NF:
18432 case ADD8rr_NF_ND:
18433 case ADD8rr_NF_ND_REV:
18434 case ADD8rr_NF_REV:
18435 case ADD8rr_REV:
18436 return true;
18437 }
18438 return false;
18439}
18440
18441bool isPSUBSW(unsigned Opcode) {
18442 switch (Opcode) {
18443 case MMX_PSUBSWrm:
18444 case MMX_PSUBSWrr:
18445 case PSUBSWrm:
18446 case PSUBSWrr:
18447 return true;
18448 }
18449 return false;
18450}
18451
18452bool isSIDTW(unsigned Opcode) {
18453 return Opcode == SIDT16m;
18454}
18455
18456bool isVEXTRACTF64X2(unsigned Opcode) {
18457 switch (Opcode) {
18458 case VEXTRACTF64X2Z256mri:
18459 case VEXTRACTF64X2Z256mrik:
18460 case VEXTRACTF64X2Z256rri:
18461 case VEXTRACTF64X2Z256rrik:
18462 case VEXTRACTF64X2Z256rrikz:
18463 case VEXTRACTF64X2Zmri:
18464 case VEXTRACTF64X2Zmrik:
18465 case VEXTRACTF64X2Zrri:
18466 case VEXTRACTF64X2Zrrik:
18467 case VEXTRACTF64X2Zrrikz:
18468 return true;
18469 }
18470 return false;
18471}
18472
18473bool isVFNMADD231PH(unsigned Opcode) {
18474 switch (Opcode) {
18475 case VFNMADD231PHZ128m:
18476 case VFNMADD231PHZ128mb:
18477 case VFNMADD231PHZ128mbk:
18478 case VFNMADD231PHZ128mbkz:
18479 case VFNMADD231PHZ128mk:
18480 case VFNMADD231PHZ128mkz:
18481 case VFNMADD231PHZ128r:
18482 case VFNMADD231PHZ128rk:
18483 case VFNMADD231PHZ128rkz:
18484 case VFNMADD231PHZ256m:
18485 case VFNMADD231PHZ256mb:
18486 case VFNMADD231PHZ256mbk:
18487 case VFNMADD231PHZ256mbkz:
18488 case VFNMADD231PHZ256mk:
18489 case VFNMADD231PHZ256mkz:
18490 case VFNMADD231PHZ256r:
18491 case VFNMADD231PHZ256rk:
18492 case VFNMADD231PHZ256rkz:
18493 case VFNMADD231PHZm:
18494 case VFNMADD231PHZmb:
18495 case VFNMADD231PHZmbk:
18496 case VFNMADD231PHZmbkz:
18497 case VFNMADD231PHZmk:
18498 case VFNMADD231PHZmkz:
18499 case VFNMADD231PHZr:
18500 case VFNMADD231PHZrb:
18501 case VFNMADD231PHZrbk:
18502 case VFNMADD231PHZrbkz:
18503 case VFNMADD231PHZrk:
18504 case VFNMADD231PHZrkz:
18505 return true;
18506 }
18507 return false;
18508}
18509
18510bool isFCOMI(unsigned Opcode) {
18511 return Opcode == COM_FIr;
18512}
18513
18514bool isRSM(unsigned Opcode) {
18515 return Opcode == RSM;
18516}
18517
18518bool isVPCOMUD(unsigned Opcode) {
18519 switch (Opcode) {
18520 case VPCOMUDmi:
18521 case VPCOMUDri:
18522 return true;
18523 }
18524 return false;
18525}
18526
18527bool isVPMOVZXBQ(unsigned Opcode) {
18528 switch (Opcode) {
18529 case VPMOVZXBQYrm:
18530 case VPMOVZXBQYrr:
18531 case VPMOVZXBQZ128rm:
18532 case VPMOVZXBQZ128rmk:
18533 case VPMOVZXBQZ128rmkz:
18534 case VPMOVZXBQZ128rr:
18535 case VPMOVZXBQZ128rrk:
18536 case VPMOVZXBQZ128rrkz:
18537 case VPMOVZXBQZ256rm:
18538 case VPMOVZXBQZ256rmk:
18539 case VPMOVZXBQZ256rmkz:
18540 case VPMOVZXBQZ256rr:
18541 case VPMOVZXBQZ256rrk:
18542 case VPMOVZXBQZ256rrkz:
18543 case VPMOVZXBQZrm:
18544 case VPMOVZXBQZrmk:
18545 case VPMOVZXBQZrmkz:
18546 case VPMOVZXBQZrr:
18547 case VPMOVZXBQZrrk:
18548 case VPMOVZXBQZrrkz:
18549 case VPMOVZXBQrm:
18550 case VPMOVZXBQrr:
18551 return true;
18552 }
18553 return false;
18554}
18555
18556bool isUWRMSR(unsigned Opcode) {
18557 switch (Opcode) {
18558 case UWRMSRir:
18559 case UWRMSRir_EVEX:
18560 case UWRMSRrr:
18561 case UWRMSRrr_EVEX:
18562 return true;
18563 }
18564 return false;
18565}
18566
18567bool isLGS(unsigned Opcode) {
18568 switch (Opcode) {
18569 case LGS16rm:
18570 case LGS32rm:
18571 case LGS64rm:
18572 return true;
18573 }
18574 return false;
18575}
18576
18577bool isVMOVNTPD(unsigned Opcode) {
18578 switch (Opcode) {
18579 case VMOVNTPDYmr:
18580 case VMOVNTPDZ128mr:
18581 case VMOVNTPDZ256mr:
18582 case VMOVNTPDZmr:
18583 case VMOVNTPDmr:
18584 return true;
18585 }
18586 return false;
18587}
18588
18589bool isPCMPESTRMQ(unsigned Opcode) {
18590 switch (Opcode) {
18591 case PCMPESTRMQrmi:
18592 case PCMPESTRMQrri:
18593 return true;
18594 }
18595 return false;
18596}
18597
18598bool isRDPRU(unsigned Opcode) {
18599 return Opcode == RDPRU;
18600}
18601
18602bool isVPUNPCKHBW(unsigned Opcode) {
18603 switch (Opcode) {
18604 case VPUNPCKHBWYrm:
18605 case VPUNPCKHBWYrr:
18606 case VPUNPCKHBWZ128rm:
18607 case VPUNPCKHBWZ128rmk:
18608 case VPUNPCKHBWZ128rmkz:
18609 case VPUNPCKHBWZ128rr:
18610 case VPUNPCKHBWZ128rrk:
18611 case VPUNPCKHBWZ128rrkz:
18612 case VPUNPCKHBWZ256rm:
18613 case VPUNPCKHBWZ256rmk:
18614 case VPUNPCKHBWZ256rmkz:
18615 case VPUNPCKHBWZ256rr:
18616 case VPUNPCKHBWZ256rrk:
18617 case VPUNPCKHBWZ256rrkz:
18618 case VPUNPCKHBWZrm:
18619 case VPUNPCKHBWZrmk:
18620 case VPUNPCKHBWZrmkz:
18621 case VPUNPCKHBWZrr:
18622 case VPUNPCKHBWZrrk:
18623 case VPUNPCKHBWZrrkz:
18624 case VPUNPCKHBWrm:
18625 case VPUNPCKHBWrr:
18626 return true;
18627 }
18628 return false;
18629}
18630
18631bool isVUCOMXSD(unsigned Opcode) {
18632 switch (Opcode) {
18633 case VUCOMXSDZrm_Int:
18634 case VUCOMXSDZrr_Int:
18635 case VUCOMXSDZrrb_Int:
18636 return true;
18637 }
18638 return false;
18639}
18640
18641bool isANDN(unsigned Opcode) {
18642 switch (Opcode) {
18643 case ANDN32rm:
18644 case ANDN32rm_EVEX:
18645 case ANDN32rm_NF:
18646 case ANDN32rr:
18647 case ANDN32rr_EVEX:
18648 case ANDN32rr_NF:
18649 case ANDN64rm:
18650 case ANDN64rm_EVEX:
18651 case ANDN64rm_NF:
18652 case ANDN64rr:
18653 case ANDN64rr_EVEX:
18654 case ANDN64rr_NF:
18655 return true;
18656 }
18657 return false;
18658}
18659
18660bool isVCVTTPH2UW(unsigned Opcode) {
18661 switch (Opcode) {
18662 case VCVTTPH2UWZ128rm:
18663 case VCVTTPH2UWZ128rmb:
18664 case VCVTTPH2UWZ128rmbk:
18665 case VCVTTPH2UWZ128rmbkz:
18666 case VCVTTPH2UWZ128rmk:
18667 case VCVTTPH2UWZ128rmkz:
18668 case VCVTTPH2UWZ128rr:
18669 case VCVTTPH2UWZ128rrk:
18670 case VCVTTPH2UWZ128rrkz:
18671 case VCVTTPH2UWZ256rm:
18672 case VCVTTPH2UWZ256rmb:
18673 case VCVTTPH2UWZ256rmbk:
18674 case VCVTTPH2UWZ256rmbkz:
18675 case VCVTTPH2UWZ256rmk:
18676 case VCVTTPH2UWZ256rmkz:
18677 case VCVTTPH2UWZ256rr:
18678 case VCVTTPH2UWZ256rrk:
18679 case VCVTTPH2UWZ256rrkz:
18680 case VCVTTPH2UWZrm:
18681 case VCVTTPH2UWZrmb:
18682 case VCVTTPH2UWZrmbk:
18683 case VCVTTPH2UWZrmbkz:
18684 case VCVTTPH2UWZrmk:
18685 case VCVTTPH2UWZrmkz:
18686 case VCVTTPH2UWZrr:
18687 case VCVTTPH2UWZrrb:
18688 case VCVTTPH2UWZrrbk:
18689 case VCVTTPH2UWZrrbkz:
18690 case VCVTTPH2UWZrrk:
18691 case VCVTTPH2UWZrrkz:
18692 return true;
18693 }
18694 return false;
18695}
18696
18697bool isVMFUNC(unsigned Opcode) {
18698 return Opcode == VMFUNC;
18699}
18700
18701bool isFIMUL(unsigned Opcode) {
18702 switch (Opcode) {
18703 case MUL_FI16m:
18704 case MUL_FI32m:
18705 return true;
18706 }
18707 return false;
18708}
18709
18710bool isBLCFILL(unsigned Opcode) {
18711 switch (Opcode) {
18712 case BLCFILL32rm:
18713 case BLCFILL32rr:
18714 case BLCFILL64rm:
18715 case BLCFILL64rr:
18716 return true;
18717 }
18718 return false;
18719}
18720
18721bool isVGATHERPF0DPS(unsigned Opcode) {
18722 return Opcode == VGATHERPF0DPSm;
18723}
18724
18725bool isVFMSUBADD231PS(unsigned Opcode) {
18726 switch (Opcode) {
18727 case VFMSUBADD231PSYm:
18728 case VFMSUBADD231PSYr:
18729 case VFMSUBADD231PSZ128m:
18730 case VFMSUBADD231PSZ128mb:
18731 case VFMSUBADD231PSZ128mbk:
18732 case VFMSUBADD231PSZ128mbkz:
18733 case VFMSUBADD231PSZ128mk:
18734 case VFMSUBADD231PSZ128mkz:
18735 case VFMSUBADD231PSZ128r:
18736 case VFMSUBADD231PSZ128rk:
18737 case VFMSUBADD231PSZ128rkz:
18738 case VFMSUBADD231PSZ256m:
18739 case VFMSUBADD231PSZ256mb:
18740 case VFMSUBADD231PSZ256mbk:
18741 case VFMSUBADD231PSZ256mbkz:
18742 case VFMSUBADD231PSZ256mk:
18743 case VFMSUBADD231PSZ256mkz:
18744 case VFMSUBADD231PSZ256r:
18745 case VFMSUBADD231PSZ256rk:
18746 case VFMSUBADD231PSZ256rkz:
18747 case VFMSUBADD231PSZm:
18748 case VFMSUBADD231PSZmb:
18749 case VFMSUBADD231PSZmbk:
18750 case VFMSUBADD231PSZmbkz:
18751 case VFMSUBADD231PSZmk:
18752 case VFMSUBADD231PSZmkz:
18753 case VFMSUBADD231PSZr:
18754 case VFMSUBADD231PSZrb:
18755 case VFMSUBADD231PSZrbk:
18756 case VFMSUBADD231PSZrbkz:
18757 case VFMSUBADD231PSZrk:
18758 case VFMSUBADD231PSZrkz:
18759 case VFMSUBADD231PSm:
18760 case VFMSUBADD231PSr:
18761 return true;
18762 }
18763 return false;
18764}
18765
18766bool isVREDUCESD(unsigned Opcode) {
18767 switch (Opcode) {
18768 case VREDUCESDZrmi:
18769 case VREDUCESDZrmik:
18770 case VREDUCESDZrmikz:
18771 case VREDUCESDZrri:
18772 case VREDUCESDZrrib:
18773 case VREDUCESDZrribk:
18774 case VREDUCESDZrribkz:
18775 case VREDUCESDZrrik:
18776 case VREDUCESDZrrikz:
18777 return true;
18778 }
18779 return false;
18780}
18781
18782bool isVCOMXSH(unsigned Opcode) {
18783 switch (Opcode) {
18784 case VCOMXSHZrm_Int:
18785 case VCOMXSHZrr_Int:
18786 case VCOMXSHZrrb_Int:
18787 return true;
18788 }
18789 return false;
18790}
18791
18792bool isVXORPS(unsigned Opcode) {
18793 switch (Opcode) {
18794 case VXORPSYrm:
18795 case VXORPSYrr:
18796 case VXORPSZ128rm:
18797 case VXORPSZ128rmb:
18798 case VXORPSZ128rmbk:
18799 case VXORPSZ128rmbkz:
18800 case VXORPSZ128rmk:
18801 case VXORPSZ128rmkz:
18802 case VXORPSZ128rr:
18803 case VXORPSZ128rrk:
18804 case VXORPSZ128rrkz:
18805 case VXORPSZ256rm:
18806 case VXORPSZ256rmb:
18807 case VXORPSZ256rmbk:
18808 case VXORPSZ256rmbkz:
18809 case VXORPSZ256rmk:
18810 case VXORPSZ256rmkz:
18811 case VXORPSZ256rr:
18812 case VXORPSZ256rrk:
18813 case VXORPSZ256rrkz:
18814 case VXORPSZrm:
18815 case VXORPSZrmb:
18816 case VXORPSZrmbk:
18817 case VXORPSZrmbkz:
18818 case VXORPSZrmk:
18819 case VXORPSZrmkz:
18820 case VXORPSZrr:
18821 case VXORPSZrrk:
18822 case VXORPSZrrkz:
18823 case VXORPSrm:
18824 case VXORPSrr:
18825 return true;
18826 }
18827 return false;
18828}
18829
18830bool isPSWAPD(unsigned Opcode) {
18831 switch (Opcode) {
18832 case PSWAPDrm:
18833 case PSWAPDrr:
18834 return true;
18835 }
18836 return false;
18837}
18838
18839bool isPMAXSD(unsigned Opcode) {
18840 switch (Opcode) {
18841 case PMAXSDrm:
18842 case PMAXSDrr:
18843 return true;
18844 }
18845 return false;
18846}
18847
18848bool isVCMPSS(unsigned Opcode) {
18849 switch (Opcode) {
18850 case VCMPSSZrmi_Int:
18851 case VCMPSSZrmik_Int:
18852 case VCMPSSZrri_Int:
18853 case VCMPSSZrrib_Int:
18854 case VCMPSSZrribk_Int:
18855 case VCMPSSZrrik_Int:
18856 case VCMPSSrmi_Int:
18857 case VCMPSSrri_Int:
18858 return true;
18859 }
18860 return false;
18861}
18862
18863bool isEXTRACTPS(unsigned Opcode) {
18864 switch (Opcode) {
18865 case EXTRACTPSmri:
18866 case EXTRACTPSrri:
18867 return true;
18868 }
18869 return false;
18870}
18871
18872bool isVPMOVZXBD(unsigned Opcode) {
18873 switch (Opcode) {
18874 case VPMOVZXBDYrm:
18875 case VPMOVZXBDYrr:
18876 case VPMOVZXBDZ128rm:
18877 case VPMOVZXBDZ128rmk:
18878 case VPMOVZXBDZ128rmkz:
18879 case VPMOVZXBDZ128rr:
18880 case VPMOVZXBDZ128rrk:
18881 case VPMOVZXBDZ128rrkz:
18882 case VPMOVZXBDZ256rm:
18883 case VPMOVZXBDZ256rmk:
18884 case VPMOVZXBDZ256rmkz:
18885 case VPMOVZXBDZ256rr:
18886 case VPMOVZXBDZ256rrk:
18887 case VPMOVZXBDZ256rrkz:
18888 case VPMOVZXBDZrm:
18889 case VPMOVZXBDZrmk:
18890 case VPMOVZXBDZrmkz:
18891 case VPMOVZXBDZrr:
18892 case VPMOVZXBDZrrk:
18893 case VPMOVZXBDZrrkz:
18894 case VPMOVZXBDrm:
18895 case VPMOVZXBDrr:
18896 return true;
18897 }
18898 return false;
18899}
18900
18901bool isOUTSW(unsigned Opcode) {
18902 return Opcode == OUTSW;
18903}
18904
18905bool isKORTESTB(unsigned Opcode) {
18906 return Opcode == KORTESTBkk;
18907}
18908
18909bool isVREDUCEPS(unsigned Opcode) {
18910 switch (Opcode) {
18911 case VREDUCEPSZ128rmbi:
18912 case VREDUCEPSZ128rmbik:
18913 case VREDUCEPSZ128rmbikz:
18914 case VREDUCEPSZ128rmi:
18915 case VREDUCEPSZ128rmik:
18916 case VREDUCEPSZ128rmikz:
18917 case VREDUCEPSZ128rri:
18918 case VREDUCEPSZ128rrik:
18919 case VREDUCEPSZ128rrikz:
18920 case VREDUCEPSZ256rmbi:
18921 case VREDUCEPSZ256rmbik:
18922 case VREDUCEPSZ256rmbikz:
18923 case VREDUCEPSZ256rmi:
18924 case VREDUCEPSZ256rmik:
18925 case VREDUCEPSZ256rmikz:
18926 case VREDUCEPSZ256rri:
18927 case VREDUCEPSZ256rrik:
18928 case VREDUCEPSZ256rrikz:
18929 case VREDUCEPSZrmbi:
18930 case VREDUCEPSZrmbik:
18931 case VREDUCEPSZrmbikz:
18932 case VREDUCEPSZrmi:
18933 case VREDUCEPSZrmik:
18934 case VREDUCEPSZrmikz:
18935 case VREDUCEPSZrri:
18936 case VREDUCEPSZrrib:
18937 case VREDUCEPSZrribk:
18938 case VREDUCEPSZrribkz:
18939 case VREDUCEPSZrrik:
18940 case VREDUCEPSZrrikz:
18941 return true;
18942 }
18943 return false;
18944}
18945
18946bool isPEXTRW(unsigned Opcode) {
18947 switch (Opcode) {
18948 case MMX_PEXTRWrri:
18949 case PEXTRWmri:
18950 case PEXTRWrri:
18951 case PEXTRWrri_REV:
18952 return true;
18953 }
18954 return false;
18955}
18956
18957bool isFNINIT(unsigned Opcode) {
18958 return Opcode == FNINIT;
18959}
18960
18961bool isVCVTPH2IBS(unsigned Opcode) {
18962 switch (Opcode) {
18963 case VCVTPH2IBSZ128rm:
18964 case VCVTPH2IBSZ128rmb:
18965 case VCVTPH2IBSZ128rmbk:
18966 case VCVTPH2IBSZ128rmbkz:
18967 case VCVTPH2IBSZ128rmk:
18968 case VCVTPH2IBSZ128rmkz:
18969 case VCVTPH2IBSZ128rr:
18970 case VCVTPH2IBSZ128rrk:
18971 case VCVTPH2IBSZ128rrkz:
18972 case VCVTPH2IBSZ256rm:
18973 case VCVTPH2IBSZ256rmb:
18974 case VCVTPH2IBSZ256rmbk:
18975 case VCVTPH2IBSZ256rmbkz:
18976 case VCVTPH2IBSZ256rmk:
18977 case VCVTPH2IBSZ256rmkz:
18978 case VCVTPH2IBSZ256rr:
18979 case VCVTPH2IBSZ256rrk:
18980 case VCVTPH2IBSZ256rrkz:
18981 case VCVTPH2IBSZrm:
18982 case VCVTPH2IBSZrmb:
18983 case VCVTPH2IBSZrmbk:
18984 case VCVTPH2IBSZrmbkz:
18985 case VCVTPH2IBSZrmk:
18986 case VCVTPH2IBSZrmkz:
18987 case VCVTPH2IBSZrr:
18988 case VCVTPH2IBSZrrb:
18989 case VCVTPH2IBSZrrbk:
18990 case VCVTPH2IBSZrrbkz:
18991 case VCVTPH2IBSZrrk:
18992 case VCVTPH2IBSZrrkz:
18993 return true;
18994 }
18995 return false;
18996}
18997
18998bool isROL(unsigned Opcode) {
18999 switch (Opcode) {
19000 case ROL16m1:
19001 case ROL16m1_EVEX:
19002 case ROL16m1_ND:
19003 case ROL16m1_NF:
19004 case ROL16m1_NF_ND:
19005 case ROL16mCL:
19006 case ROL16mCL_EVEX:
19007 case ROL16mCL_ND:
19008 case ROL16mCL_NF:
19009 case ROL16mCL_NF_ND:
19010 case ROL16mi:
19011 case ROL16mi_EVEX:
19012 case ROL16mi_ND:
19013 case ROL16mi_NF:
19014 case ROL16mi_NF_ND:
19015 case ROL16r1:
19016 case ROL16r1_EVEX:
19017 case ROL16r1_ND:
19018 case ROL16r1_NF:
19019 case ROL16r1_NF_ND:
19020 case ROL16rCL:
19021 case ROL16rCL_EVEX:
19022 case ROL16rCL_ND:
19023 case ROL16rCL_NF:
19024 case ROL16rCL_NF_ND:
19025 case ROL16ri:
19026 case ROL16ri_EVEX:
19027 case ROL16ri_ND:
19028 case ROL16ri_NF:
19029 case ROL16ri_NF_ND:
19030 case ROL32m1:
19031 case ROL32m1_EVEX:
19032 case ROL32m1_ND:
19033 case ROL32m1_NF:
19034 case ROL32m1_NF_ND:
19035 case ROL32mCL:
19036 case ROL32mCL_EVEX:
19037 case ROL32mCL_ND:
19038 case ROL32mCL_NF:
19039 case ROL32mCL_NF_ND:
19040 case ROL32mi:
19041 case ROL32mi_EVEX:
19042 case ROL32mi_ND:
19043 case ROL32mi_NF:
19044 case ROL32mi_NF_ND:
19045 case ROL32r1:
19046 case ROL32r1_EVEX:
19047 case ROL32r1_ND:
19048 case ROL32r1_NF:
19049 case ROL32r1_NF_ND:
19050 case ROL32rCL:
19051 case ROL32rCL_EVEX:
19052 case ROL32rCL_ND:
19053 case ROL32rCL_NF:
19054 case ROL32rCL_NF_ND:
19055 case ROL32ri:
19056 case ROL32ri_EVEX:
19057 case ROL32ri_ND:
19058 case ROL32ri_NF:
19059 case ROL32ri_NF_ND:
19060 case ROL64m1:
19061 case ROL64m1_EVEX:
19062 case ROL64m1_ND:
19063 case ROL64m1_NF:
19064 case ROL64m1_NF_ND:
19065 case ROL64mCL:
19066 case ROL64mCL_EVEX:
19067 case ROL64mCL_ND:
19068 case ROL64mCL_NF:
19069 case ROL64mCL_NF_ND:
19070 case ROL64mi:
19071 case ROL64mi_EVEX:
19072 case ROL64mi_ND:
19073 case ROL64mi_NF:
19074 case ROL64mi_NF_ND:
19075 case ROL64r1:
19076 case ROL64r1_EVEX:
19077 case ROL64r1_ND:
19078 case ROL64r1_NF:
19079 case ROL64r1_NF_ND:
19080 case ROL64rCL:
19081 case ROL64rCL_EVEX:
19082 case ROL64rCL_ND:
19083 case ROL64rCL_NF:
19084 case ROL64rCL_NF_ND:
19085 case ROL64ri:
19086 case ROL64ri_EVEX:
19087 case ROL64ri_ND:
19088 case ROL64ri_NF:
19089 case ROL64ri_NF_ND:
19090 case ROL8m1:
19091 case ROL8m1_EVEX:
19092 case ROL8m1_ND:
19093 case ROL8m1_NF:
19094 case ROL8m1_NF_ND:
19095 case ROL8mCL:
19096 case ROL8mCL_EVEX:
19097 case ROL8mCL_ND:
19098 case ROL8mCL_NF:
19099 case ROL8mCL_NF_ND:
19100 case ROL8mi:
19101 case ROL8mi_EVEX:
19102 case ROL8mi_ND:
19103 case ROL8mi_NF:
19104 case ROL8mi_NF_ND:
19105 case ROL8r1:
19106 case ROL8r1_EVEX:
19107 case ROL8r1_ND:
19108 case ROL8r1_NF:
19109 case ROL8r1_NF_ND:
19110 case ROL8rCL:
19111 case ROL8rCL_EVEX:
19112 case ROL8rCL_ND:
19113 case ROL8rCL_NF:
19114 case ROL8rCL_NF_ND:
19115 case ROL8ri:
19116 case ROL8ri_EVEX:
19117 case ROL8ri_ND:
19118 case ROL8ri_NF:
19119 case ROL8ri_NF_ND:
19120 return true;
19121 }
19122 return false;
19123}
19124
19125bool isVCVTPS2QQ(unsigned Opcode) {
19126 switch (Opcode) {
19127 case VCVTPS2QQZ128rm:
19128 case VCVTPS2QQZ128rmb:
19129 case VCVTPS2QQZ128rmbk:
19130 case VCVTPS2QQZ128rmbkz:
19131 case VCVTPS2QQZ128rmk:
19132 case VCVTPS2QQZ128rmkz:
19133 case VCVTPS2QQZ128rr:
19134 case VCVTPS2QQZ128rrk:
19135 case VCVTPS2QQZ128rrkz:
19136 case VCVTPS2QQZ256rm:
19137 case VCVTPS2QQZ256rmb:
19138 case VCVTPS2QQZ256rmbk:
19139 case VCVTPS2QQZ256rmbkz:
19140 case VCVTPS2QQZ256rmk:
19141 case VCVTPS2QQZ256rmkz:
19142 case VCVTPS2QQZ256rr:
19143 case VCVTPS2QQZ256rrk:
19144 case VCVTPS2QQZ256rrkz:
19145 case VCVTPS2QQZrm:
19146 case VCVTPS2QQZrmb:
19147 case VCVTPS2QQZrmbk:
19148 case VCVTPS2QQZrmbkz:
19149 case VCVTPS2QQZrmk:
19150 case VCVTPS2QQZrmkz:
19151 case VCVTPS2QQZrr:
19152 case VCVTPS2QQZrrb:
19153 case VCVTPS2QQZrrbk:
19154 case VCVTPS2QQZrrbkz:
19155 case VCVTPS2QQZrrk:
19156 case VCVTPS2QQZrrkz:
19157 return true;
19158 }
19159 return false;
19160}
19161
19162bool isVGETMANTPH(unsigned Opcode) {
19163 switch (Opcode) {
19164 case VGETMANTPHZ128rmbi:
19165 case VGETMANTPHZ128rmbik:
19166 case VGETMANTPHZ128rmbikz:
19167 case VGETMANTPHZ128rmi:
19168 case VGETMANTPHZ128rmik:
19169 case VGETMANTPHZ128rmikz:
19170 case VGETMANTPHZ128rri:
19171 case VGETMANTPHZ128rrik:
19172 case VGETMANTPHZ128rrikz:
19173 case VGETMANTPHZ256rmbi:
19174 case VGETMANTPHZ256rmbik:
19175 case VGETMANTPHZ256rmbikz:
19176 case VGETMANTPHZ256rmi:
19177 case VGETMANTPHZ256rmik:
19178 case VGETMANTPHZ256rmikz:
19179 case VGETMANTPHZ256rri:
19180 case VGETMANTPHZ256rrik:
19181 case VGETMANTPHZ256rrikz:
19182 case VGETMANTPHZrmbi:
19183 case VGETMANTPHZrmbik:
19184 case VGETMANTPHZrmbikz:
19185 case VGETMANTPHZrmi:
19186 case VGETMANTPHZrmik:
19187 case VGETMANTPHZrmikz:
19188 case VGETMANTPHZrri:
19189 case VGETMANTPHZrrib:
19190 case VGETMANTPHZrribk:
19191 case VGETMANTPHZrribkz:
19192 case VGETMANTPHZrrik:
19193 case VGETMANTPHZrrikz:
19194 return true;
19195 }
19196 return false;
19197}
19198
19199bool isPUNPCKLDQ(unsigned Opcode) {
19200 switch (Opcode) {
19201 case MMX_PUNPCKLDQrm:
19202 case MMX_PUNPCKLDQrr:
19203 case PUNPCKLDQrm:
19204 case PUNPCKLDQrr:
19205 return true;
19206 }
19207 return false;
19208}
19209
19210bool isPADDD(unsigned Opcode) {
19211 switch (Opcode) {
19212 case MMX_PADDDrm:
19213 case MMX_PADDDrr:
19214 case PADDDrm:
19215 case PADDDrr:
19216 return true;
19217 }
19218 return false;
19219}
19220
19221bool isVPSLLD(unsigned Opcode) {
19222 switch (Opcode) {
19223 case VPSLLDYri:
19224 case VPSLLDYrm:
19225 case VPSLLDYrr:
19226 case VPSLLDZ128mbi:
19227 case VPSLLDZ128mbik:
19228 case VPSLLDZ128mbikz:
19229 case VPSLLDZ128mi:
19230 case VPSLLDZ128mik:
19231 case VPSLLDZ128mikz:
19232 case VPSLLDZ128ri:
19233 case VPSLLDZ128rik:
19234 case VPSLLDZ128rikz:
19235 case VPSLLDZ128rm:
19236 case VPSLLDZ128rmk:
19237 case VPSLLDZ128rmkz:
19238 case VPSLLDZ128rr:
19239 case VPSLLDZ128rrk:
19240 case VPSLLDZ128rrkz:
19241 case VPSLLDZ256mbi:
19242 case VPSLLDZ256mbik:
19243 case VPSLLDZ256mbikz:
19244 case VPSLLDZ256mi:
19245 case VPSLLDZ256mik:
19246 case VPSLLDZ256mikz:
19247 case VPSLLDZ256ri:
19248 case VPSLLDZ256rik:
19249 case VPSLLDZ256rikz:
19250 case VPSLLDZ256rm:
19251 case VPSLLDZ256rmk:
19252 case VPSLLDZ256rmkz:
19253 case VPSLLDZ256rr:
19254 case VPSLLDZ256rrk:
19255 case VPSLLDZ256rrkz:
19256 case VPSLLDZmbi:
19257 case VPSLLDZmbik:
19258 case VPSLLDZmbikz:
19259 case VPSLLDZmi:
19260 case VPSLLDZmik:
19261 case VPSLLDZmikz:
19262 case VPSLLDZri:
19263 case VPSLLDZrik:
19264 case VPSLLDZrikz:
19265 case VPSLLDZrm:
19266 case VPSLLDZrmk:
19267 case VPSLLDZrmkz:
19268 case VPSLLDZrr:
19269 case VPSLLDZrrk:
19270 case VPSLLDZrrkz:
19271 case VPSLLDri:
19272 case VPSLLDrm:
19273 case VPSLLDrr:
19274 return true;
19275 }
19276 return false;
19277}
19278
19279bool isPFCMPGE(unsigned Opcode) {
19280 switch (Opcode) {
19281 case PFCMPGErm:
19282 case PFCMPGErr:
19283 return true;
19284 }
19285 return false;
19286}
19287
19288bool isVGETMANTBF16(unsigned Opcode) {
19289 switch (Opcode) {
19290 case VGETMANTBF16Z128rmbi:
19291 case VGETMANTBF16Z128rmbik:
19292 case VGETMANTBF16Z128rmbikz:
19293 case VGETMANTBF16Z128rmi:
19294 case VGETMANTBF16Z128rmik:
19295 case VGETMANTBF16Z128rmikz:
19296 case VGETMANTBF16Z128rri:
19297 case VGETMANTBF16Z128rrik:
19298 case VGETMANTBF16Z128rrikz:
19299 case VGETMANTBF16Z256rmbi:
19300 case VGETMANTBF16Z256rmbik:
19301 case VGETMANTBF16Z256rmbikz:
19302 case VGETMANTBF16Z256rmi:
19303 case VGETMANTBF16Z256rmik:
19304 case VGETMANTBF16Z256rmikz:
19305 case VGETMANTBF16Z256rri:
19306 case VGETMANTBF16Z256rrik:
19307 case VGETMANTBF16Z256rrikz:
19308 case VGETMANTBF16Zrmbi:
19309 case VGETMANTBF16Zrmbik:
19310 case VGETMANTBF16Zrmbikz:
19311 case VGETMANTBF16Zrmi:
19312 case VGETMANTBF16Zrmik:
19313 case VGETMANTBF16Zrmikz:
19314 case VGETMANTBF16Zrri:
19315 case VGETMANTBF16Zrrik:
19316 case VGETMANTBF16Zrrikz:
19317 return true;
19318 }
19319 return false;
19320}
19321
19322bool isVSUBBF16(unsigned Opcode) {
19323 switch (Opcode) {
19324 case VSUBBF16Z128rm:
19325 case VSUBBF16Z128rmb:
19326 case VSUBBF16Z128rmbk:
19327 case VSUBBF16Z128rmbkz:
19328 case VSUBBF16Z128rmk:
19329 case VSUBBF16Z128rmkz:
19330 case VSUBBF16Z128rr:
19331 case VSUBBF16Z128rrk:
19332 case VSUBBF16Z128rrkz:
19333 case VSUBBF16Z256rm:
19334 case VSUBBF16Z256rmb:
19335 case VSUBBF16Z256rmbk:
19336 case VSUBBF16Z256rmbkz:
19337 case VSUBBF16Z256rmk:
19338 case VSUBBF16Z256rmkz:
19339 case VSUBBF16Z256rr:
19340 case VSUBBF16Z256rrk:
19341 case VSUBBF16Z256rrkz:
19342 case VSUBBF16Zrm:
19343 case VSUBBF16Zrmb:
19344 case VSUBBF16Zrmbk:
19345 case VSUBBF16Zrmbkz:
19346 case VSUBBF16Zrmk:
19347 case VSUBBF16Zrmkz:
19348 case VSUBBF16Zrr:
19349 case VSUBBF16Zrrk:
19350 case VSUBBF16Zrrkz:
19351 return true;
19352 }
19353 return false;
19354}
19355
19356bool isVPMOVM2D(unsigned Opcode) {
19357 switch (Opcode) {
19358 case VPMOVM2DZ128rk:
19359 case VPMOVM2DZ256rk:
19360 case VPMOVM2DZrk:
19361 return true;
19362 }
19363 return false;
19364}
19365
19366bool isVCVTTSS2USIS(unsigned Opcode) {
19367 switch (Opcode) {
19368 case VCVTTSS2USI64Srm_Int:
19369 case VCVTTSS2USI64Srr_Int:
19370 case VCVTTSS2USI64Srrb_Int:
19371 case VCVTTSS2USISrm_Int:
19372 case VCVTTSS2USISrr_Int:
19373 case VCVTTSS2USISrrb_Int:
19374 return true;
19375 }
19376 return false;
19377}
19378
19379bool isVHSUBPS(unsigned Opcode) {
19380 switch (Opcode) {
19381 case VHSUBPSYrm:
19382 case VHSUBPSYrr:
19383 case VHSUBPSrm:
19384 case VHSUBPSrr:
19385 return true;
19386 }
19387 return false;
19388}
19389
19390bool isENDBR32(unsigned Opcode) {
19391 return Opcode == ENDBR32;
19392}
19393
19394bool isMOVSXD(unsigned Opcode) {
19395 switch (Opcode) {
19396 case MOVSX16rm32:
19397 case MOVSX16rr32:
19398 case MOVSX32rm32:
19399 case MOVSX32rr32:
19400 case MOVSX64rm32:
19401 case MOVSX64rr32:
19402 return true;
19403 }
19404 return false;
19405}
19406
19407bool isPSIGND(unsigned Opcode) {
19408 switch (Opcode) {
19409 case MMX_PSIGNDrm:
19410 case MMX_PSIGNDrr:
19411 case PSIGNDrm:
19412 case PSIGNDrr:
19413 return true;
19414 }
19415 return false;
19416}
19417
19418bool isVPTEST(unsigned Opcode) {
19419 switch (Opcode) {
19420 case VPTESTYrm:
19421 case VPTESTYrr:
19422 case VPTESTrm:
19423 case VPTESTrr:
19424 return true;
19425 }
19426 return false;
19427}
19428
19429bool isVPDPWUSD(unsigned Opcode) {
19430 switch (Opcode) {
19431 case VPDPWUSDYrm:
19432 case VPDPWUSDYrr:
19433 case VPDPWUSDZ128rm:
19434 case VPDPWUSDZ128rmb:
19435 case VPDPWUSDZ128rmbk:
19436 case VPDPWUSDZ128rmbkz:
19437 case VPDPWUSDZ128rmk:
19438 case VPDPWUSDZ128rmkz:
19439 case VPDPWUSDZ128rr:
19440 case VPDPWUSDZ128rrk:
19441 case VPDPWUSDZ128rrkz:
19442 case VPDPWUSDZ256rm:
19443 case VPDPWUSDZ256rmb:
19444 case VPDPWUSDZ256rmbk:
19445 case VPDPWUSDZ256rmbkz:
19446 case VPDPWUSDZ256rmk:
19447 case VPDPWUSDZ256rmkz:
19448 case VPDPWUSDZ256rr:
19449 case VPDPWUSDZ256rrk:
19450 case VPDPWUSDZ256rrkz:
19451 case VPDPWUSDZrm:
19452 case VPDPWUSDZrmb:
19453 case VPDPWUSDZrmbk:
19454 case VPDPWUSDZrmbkz:
19455 case VPDPWUSDZrmk:
19456 case VPDPWUSDZrmkz:
19457 case VPDPWUSDZrr:
19458 case VPDPWUSDZrrk:
19459 case VPDPWUSDZrrkz:
19460 case VPDPWUSDrm:
19461 case VPDPWUSDrr:
19462 return true;
19463 }
19464 return false;
19465}
19466
19467bool isHSUBPD(unsigned Opcode) {
19468 switch (Opcode) {
19469 case HSUBPDrm:
19470 case HSUBPDrr:
19471 return true;
19472 }
19473 return false;
19474}
19475
19476bool isADCX(unsigned Opcode) {
19477 switch (Opcode) {
19478 case ADCX32rm:
19479 case ADCX32rm_EVEX:
19480 case ADCX32rm_ND:
19481 case ADCX32rr:
19482 case ADCX32rr_EVEX:
19483 case ADCX32rr_ND:
19484 case ADCX64rm:
19485 case ADCX64rm_EVEX:
19486 case ADCX64rm_ND:
19487 case ADCX64rr:
19488 case ADCX64rr_EVEX:
19489 case ADCX64rr_ND:
19490 return true;
19491 }
19492 return false;
19493}
19494
19495bool isCVTTPD2PI(unsigned Opcode) {
19496 switch (Opcode) {
19497 case MMX_CVTTPD2PIrm:
19498 case MMX_CVTTPD2PIrr:
19499 return true;
19500 }
19501 return false;
19502}
19503
19504bool isPDEP(unsigned Opcode) {
19505 switch (Opcode) {
19506 case PDEP32rm:
19507 case PDEP32rm_EVEX:
19508 case PDEP32rr:
19509 case PDEP32rr_EVEX:
19510 case PDEP64rm:
19511 case PDEP64rm_EVEX:
19512 case PDEP64rr:
19513 case PDEP64rr_EVEX:
19514 return true;
19515 }
19516 return false;
19517}
19518
19519bool isTDPBUSD(unsigned Opcode) {
19520 return Opcode == TDPBUSD;
19521}
19522
19523bool isVCVTBIASPH2HF8S(unsigned Opcode) {
19524 switch (Opcode) {
19525 case VCVTBIASPH2HF8SZ128rm:
19526 case VCVTBIASPH2HF8SZ128rmb:
19527 case VCVTBIASPH2HF8SZ128rmbk:
19528 case VCVTBIASPH2HF8SZ128rmbkz:
19529 case VCVTBIASPH2HF8SZ128rmk:
19530 case VCVTBIASPH2HF8SZ128rmkz:
19531 case VCVTBIASPH2HF8SZ128rr:
19532 case VCVTBIASPH2HF8SZ128rrk:
19533 case VCVTBIASPH2HF8SZ128rrkz:
19534 case VCVTBIASPH2HF8SZ256rm:
19535 case VCVTBIASPH2HF8SZ256rmb:
19536 case VCVTBIASPH2HF8SZ256rmbk:
19537 case VCVTBIASPH2HF8SZ256rmbkz:
19538 case VCVTBIASPH2HF8SZ256rmk:
19539 case VCVTBIASPH2HF8SZ256rmkz:
19540 case VCVTBIASPH2HF8SZ256rr:
19541 case VCVTBIASPH2HF8SZ256rrk:
19542 case VCVTBIASPH2HF8SZ256rrkz:
19543 case VCVTBIASPH2HF8SZrm:
19544 case VCVTBIASPH2HF8SZrmb:
19545 case VCVTBIASPH2HF8SZrmbk:
19546 case VCVTBIASPH2HF8SZrmbkz:
19547 case VCVTBIASPH2HF8SZrmk:
19548 case VCVTBIASPH2HF8SZrmkz:
19549 case VCVTBIASPH2HF8SZrr:
19550 case VCVTBIASPH2HF8SZrrk:
19551 case VCVTBIASPH2HF8SZrrkz:
19552 return true;
19553 }
19554 return false;
19555}
19556
19557bool isVBROADCASTI32X4(unsigned Opcode) {
19558 switch (Opcode) {
19559 case VBROADCASTI32X4Z256rm:
19560 case VBROADCASTI32X4Z256rmk:
19561 case VBROADCASTI32X4Z256rmkz:
19562 case VBROADCASTI32X4Zrm:
19563 case VBROADCASTI32X4Zrmk:
19564 case VBROADCASTI32X4Zrmkz:
19565 return true;
19566 }
19567 return false;
19568}
19569
19570bool isVCVTPH2UDQ(unsigned Opcode) {
19571 switch (Opcode) {
19572 case VCVTPH2UDQZ128rm:
19573 case VCVTPH2UDQZ128rmb:
19574 case VCVTPH2UDQZ128rmbk:
19575 case VCVTPH2UDQZ128rmbkz:
19576 case VCVTPH2UDQZ128rmk:
19577 case VCVTPH2UDQZ128rmkz:
19578 case VCVTPH2UDQZ128rr:
19579 case VCVTPH2UDQZ128rrk:
19580 case VCVTPH2UDQZ128rrkz:
19581 case VCVTPH2UDQZ256rm:
19582 case VCVTPH2UDQZ256rmb:
19583 case VCVTPH2UDQZ256rmbk:
19584 case VCVTPH2UDQZ256rmbkz:
19585 case VCVTPH2UDQZ256rmk:
19586 case VCVTPH2UDQZ256rmkz:
19587 case VCVTPH2UDQZ256rr:
19588 case VCVTPH2UDQZ256rrk:
19589 case VCVTPH2UDQZ256rrkz:
19590 case VCVTPH2UDQZrm:
19591 case VCVTPH2UDQZrmb:
19592 case VCVTPH2UDQZrmbk:
19593 case VCVTPH2UDQZrmbkz:
19594 case VCVTPH2UDQZrmk:
19595 case VCVTPH2UDQZrmkz:
19596 case VCVTPH2UDQZrr:
19597 case VCVTPH2UDQZrrb:
19598 case VCVTPH2UDQZrrbk:
19599 case VCVTPH2UDQZrrbkz:
19600 case VCVTPH2UDQZrrk:
19601 case VCVTPH2UDQZrrkz:
19602 return true;
19603 }
19604 return false;
19605}
19606
19607bool isVPHADDW(unsigned Opcode) {
19608 switch (Opcode) {
19609 case VPHADDWYrm:
19610 case VPHADDWYrr:
19611 case VPHADDWrm:
19612 case VPHADDWrr:
19613 return true;
19614 }
19615 return false;
19616}
19617
19618bool isFLDL2E(unsigned Opcode) {
19619 return Opcode == FLDL2E;
19620}
19621
19622bool isCLZERO(unsigned Opcode) {
19623 switch (Opcode) {
19624 case CLZERO32r:
19625 case CLZERO64r:
19626 return true;
19627 }
19628 return false;
19629}
19630
19631bool isPBLENDW(unsigned Opcode) {
19632 switch (Opcode) {
19633 case PBLENDWrmi:
19634 case PBLENDWrri:
19635 return true;
19636 }
19637 return false;
19638}
19639
19640bool isVCVTBF162IUBS(unsigned Opcode) {
19641 switch (Opcode) {
19642 case VCVTBF162IUBSZ128rm:
19643 case VCVTBF162IUBSZ128rmb:
19644 case VCVTBF162IUBSZ128rmbk:
19645 case VCVTBF162IUBSZ128rmbkz:
19646 case VCVTBF162IUBSZ128rmk:
19647 case VCVTBF162IUBSZ128rmkz:
19648 case VCVTBF162IUBSZ128rr:
19649 case VCVTBF162IUBSZ128rrk:
19650 case VCVTBF162IUBSZ128rrkz:
19651 case VCVTBF162IUBSZ256rm:
19652 case VCVTBF162IUBSZ256rmb:
19653 case VCVTBF162IUBSZ256rmbk:
19654 case VCVTBF162IUBSZ256rmbkz:
19655 case VCVTBF162IUBSZ256rmk:
19656 case VCVTBF162IUBSZ256rmkz:
19657 case VCVTBF162IUBSZ256rr:
19658 case VCVTBF162IUBSZ256rrk:
19659 case VCVTBF162IUBSZ256rrkz:
19660 case VCVTBF162IUBSZrm:
19661 case VCVTBF162IUBSZrmb:
19662 case VCVTBF162IUBSZrmbk:
19663 case VCVTBF162IUBSZrmbkz:
19664 case VCVTBF162IUBSZrmk:
19665 case VCVTBF162IUBSZrmkz:
19666 case VCVTBF162IUBSZrr:
19667 case VCVTBF162IUBSZrrk:
19668 case VCVTBF162IUBSZrrkz:
19669 return true;
19670 }
19671 return false;
19672}
19673
19674bool isVCVTSH2USI(unsigned Opcode) {
19675 switch (Opcode) {
19676 case VCVTSH2USI64Zrm_Int:
19677 case VCVTSH2USI64Zrr_Int:
19678 case VCVTSH2USI64Zrrb_Int:
19679 case VCVTSH2USIZrm_Int:
19680 case VCVTSH2USIZrr_Int:
19681 case VCVTSH2USIZrrb_Int:
19682 return true;
19683 }
19684 return false;
19685}
19686
19687bool isVANDPD(unsigned Opcode) {
19688 switch (Opcode) {
19689 case VANDPDYrm:
19690 case VANDPDYrr:
19691 case VANDPDZ128rm:
19692 case VANDPDZ128rmb:
19693 case VANDPDZ128rmbk:
19694 case VANDPDZ128rmbkz:
19695 case VANDPDZ128rmk:
19696 case VANDPDZ128rmkz:
19697 case VANDPDZ128rr:
19698 case VANDPDZ128rrk:
19699 case VANDPDZ128rrkz:
19700 case VANDPDZ256rm:
19701 case VANDPDZ256rmb:
19702 case VANDPDZ256rmbk:
19703 case VANDPDZ256rmbkz:
19704 case VANDPDZ256rmk:
19705 case VANDPDZ256rmkz:
19706 case VANDPDZ256rr:
19707 case VANDPDZ256rrk:
19708 case VANDPDZ256rrkz:
19709 case VANDPDZrm:
19710 case VANDPDZrmb:
19711 case VANDPDZrmbk:
19712 case VANDPDZrmbkz:
19713 case VANDPDZrmk:
19714 case VANDPDZrmkz:
19715 case VANDPDZrr:
19716 case VANDPDZrrk:
19717 case VANDPDZrrkz:
19718 case VANDPDrm:
19719 case VANDPDrr:
19720 return true;
19721 }
19722 return false;
19723}
19724
19725bool isBEXTR(unsigned Opcode) {
19726 switch (Opcode) {
19727 case BEXTR32rm:
19728 case BEXTR32rm_EVEX:
19729 case BEXTR32rm_NF:
19730 case BEXTR32rr:
19731 case BEXTR32rr_EVEX:
19732 case BEXTR32rr_NF:
19733 case BEXTR64rm:
19734 case BEXTR64rm_EVEX:
19735 case BEXTR64rm_NF:
19736 case BEXTR64rr:
19737 case BEXTR64rr_EVEX:
19738 case BEXTR64rr_NF:
19739 case BEXTRI32mi:
19740 case BEXTRI32ri:
19741 case BEXTRI64mi:
19742 case BEXTRI64ri:
19743 return true;
19744 }
19745 return false;
19746}
19747
19748bool isSTD(unsigned Opcode) {
19749 return Opcode == STD;
19750}
19751
19752bool isVAESKEYGENASSIST(unsigned Opcode) {
19753 switch (Opcode) {
19754 case VAESKEYGENASSISTrmi:
19755 case VAESKEYGENASSISTrri:
19756 return true;
19757 }
19758 return false;
19759}
19760
19761bool isCMPSD(unsigned Opcode) {
19762 switch (Opcode) {
19763 case CMPSDrmi_Int:
19764 case CMPSDrri_Int:
19765 case CMPSL:
19766 return true;
19767 }
19768 return false;
19769}
19770
19771bool isMOVSS(unsigned Opcode) {
19772 switch (Opcode) {
19773 case MOVSSmr:
19774 case MOVSSrm:
19775 case MOVSSrr:
19776 case MOVSSrr_REV:
19777 return true;
19778 }
19779 return false;
19780}
19781
19782bool isVCVTUQQ2PD(unsigned Opcode) {
19783 switch (Opcode) {
19784 case VCVTUQQ2PDZ128rm:
19785 case VCVTUQQ2PDZ128rmb:
19786 case VCVTUQQ2PDZ128rmbk:
19787 case VCVTUQQ2PDZ128rmbkz:
19788 case VCVTUQQ2PDZ128rmk:
19789 case VCVTUQQ2PDZ128rmkz:
19790 case VCVTUQQ2PDZ128rr:
19791 case VCVTUQQ2PDZ128rrk:
19792 case VCVTUQQ2PDZ128rrkz:
19793 case VCVTUQQ2PDZ256rm:
19794 case VCVTUQQ2PDZ256rmb:
19795 case VCVTUQQ2PDZ256rmbk:
19796 case VCVTUQQ2PDZ256rmbkz:
19797 case VCVTUQQ2PDZ256rmk:
19798 case VCVTUQQ2PDZ256rmkz:
19799 case VCVTUQQ2PDZ256rr:
19800 case VCVTUQQ2PDZ256rrk:
19801 case VCVTUQQ2PDZ256rrkz:
19802 case VCVTUQQ2PDZrm:
19803 case VCVTUQQ2PDZrmb:
19804 case VCVTUQQ2PDZrmbk:
19805 case VCVTUQQ2PDZrmbkz:
19806 case VCVTUQQ2PDZrmk:
19807 case VCVTUQQ2PDZrmkz:
19808 case VCVTUQQ2PDZrr:
19809 case VCVTUQQ2PDZrrb:
19810 case VCVTUQQ2PDZrrbk:
19811 case VCVTUQQ2PDZrrbkz:
19812 case VCVTUQQ2PDZrrk:
19813 case VCVTUQQ2PDZrrkz:
19814 return true;
19815 }
19816 return false;
19817}
19818
19819bool isVEXTRACTI32X4(unsigned Opcode) {
19820 switch (Opcode) {
19821 case VEXTRACTI32X4Z256mri:
19822 case VEXTRACTI32X4Z256mrik:
19823 case VEXTRACTI32X4Z256rri:
19824 case VEXTRACTI32X4Z256rrik:
19825 case VEXTRACTI32X4Z256rrikz:
19826 case VEXTRACTI32X4Zmri:
19827 case VEXTRACTI32X4Zmrik:
19828 case VEXTRACTI32X4Zrri:
19829 case VEXTRACTI32X4Zrrik:
19830 case VEXTRACTI32X4Zrrikz:
19831 return true;
19832 }
19833 return false;
19834}
19835
19836bool isFLDCW(unsigned Opcode) {
19837 return Opcode == FLDCW16m;
19838}
19839
19840bool isINSW(unsigned Opcode) {
19841 return Opcode == INSW;
19842}
19843
19844bool isRDPID(unsigned Opcode) {
19845 switch (Opcode) {
19846 case RDPID32:
19847 case RDPID64:
19848 return true;
19849 }
19850 return false;
19851}
19852
19853bool isVUCOMXSS(unsigned Opcode) {
19854 switch (Opcode) {
19855 case VUCOMXSSZrm_Int:
19856 case VUCOMXSSZrr_Int:
19857 case VUCOMXSSZrrb_Int:
19858 return true;
19859 }
19860 return false;
19861}
19862
19863bool isKANDQ(unsigned Opcode) {
19864 return Opcode == KANDQkk;
19865}
19866
19867bool isV4FMADDPS(unsigned Opcode) {
19868 switch (Opcode) {
19869 case V4FMADDPSrm:
19870 case V4FMADDPSrmk:
19871 case V4FMADDPSrmkz:
19872 return true;
19873 }
19874 return false;
19875}
19876
19877bool isPMOVZXWQ(unsigned Opcode) {
19878 switch (Opcode) {
19879 case PMOVZXWQrm:
19880 case PMOVZXWQrr:
19881 return true;
19882 }
19883 return false;
19884}
19885
19886bool isVFPCLASSSD(unsigned Opcode) {
19887 switch (Opcode) {
19888 case VFPCLASSSDZmi:
19889 case VFPCLASSSDZmik:
19890 case VFPCLASSSDZri:
19891 case VFPCLASSSDZrik:
19892 return true;
19893 }
19894 return false;
19895}
19896
19897bool isBLENDPS(unsigned Opcode) {
19898 switch (Opcode) {
19899 case BLENDPSrmi:
19900 case BLENDPSrri:
19901 return true;
19902 }
19903 return false;
19904}
19905
19906bool isVPACKSSDW(unsigned Opcode) {
19907 switch (Opcode) {
19908 case VPACKSSDWYrm:
19909 case VPACKSSDWYrr:
19910 case VPACKSSDWZ128rm:
19911 case VPACKSSDWZ128rmb:
19912 case VPACKSSDWZ128rmbk:
19913 case VPACKSSDWZ128rmbkz:
19914 case VPACKSSDWZ128rmk:
19915 case VPACKSSDWZ128rmkz:
19916 case VPACKSSDWZ128rr:
19917 case VPACKSSDWZ128rrk:
19918 case VPACKSSDWZ128rrkz:
19919 case VPACKSSDWZ256rm:
19920 case VPACKSSDWZ256rmb:
19921 case VPACKSSDWZ256rmbk:
19922 case VPACKSSDWZ256rmbkz:
19923 case VPACKSSDWZ256rmk:
19924 case VPACKSSDWZ256rmkz:
19925 case VPACKSSDWZ256rr:
19926 case VPACKSSDWZ256rrk:
19927 case VPACKSSDWZ256rrkz:
19928 case VPACKSSDWZrm:
19929 case VPACKSSDWZrmb:
19930 case VPACKSSDWZrmbk:
19931 case VPACKSSDWZrmbkz:
19932 case VPACKSSDWZrmk:
19933 case VPACKSSDWZrmkz:
19934 case VPACKSSDWZrr:
19935 case VPACKSSDWZrrk:
19936 case VPACKSSDWZrrkz:
19937 case VPACKSSDWrm:
19938 case VPACKSSDWrr:
19939 return true;
19940 }
19941 return false;
19942}
19943
19944bool isVPHSUBBW(unsigned Opcode) {
19945 switch (Opcode) {
19946 case VPHSUBBWrm:
19947 case VPHSUBBWrr:
19948 return true;
19949 }
19950 return false;
19951}
19952
19953bool isVPINSRW(unsigned Opcode) {
19954 switch (Opcode) {
19955 case VPINSRWZrmi:
19956 case VPINSRWZrri:
19957 case VPINSRWrmi:
19958 case VPINSRWrri:
19959 return true;
19960 }
19961 return false;
19962}
19963
19964bool isVMINMAXBF16(unsigned Opcode) {
19965 switch (Opcode) {
19966 case VMINMAXBF16Z128rmbi:
19967 case VMINMAXBF16Z128rmbik:
19968 case VMINMAXBF16Z128rmbikz:
19969 case VMINMAXBF16Z128rmi:
19970 case VMINMAXBF16Z128rmik:
19971 case VMINMAXBF16Z128rmikz:
19972 case VMINMAXBF16Z128rri:
19973 case VMINMAXBF16Z128rrik:
19974 case VMINMAXBF16Z128rrikz:
19975 case VMINMAXBF16Z256rmbi:
19976 case VMINMAXBF16Z256rmbik:
19977 case VMINMAXBF16Z256rmbikz:
19978 case VMINMAXBF16Z256rmi:
19979 case VMINMAXBF16Z256rmik:
19980 case VMINMAXBF16Z256rmikz:
19981 case VMINMAXBF16Z256rri:
19982 case VMINMAXBF16Z256rrik:
19983 case VMINMAXBF16Z256rrikz:
19984 case VMINMAXBF16Zrmbi:
19985 case VMINMAXBF16Zrmbik:
19986 case VMINMAXBF16Zrmbikz:
19987 case VMINMAXBF16Zrmi:
19988 case VMINMAXBF16Zrmik:
19989 case VMINMAXBF16Zrmikz:
19990 case VMINMAXBF16Zrri:
19991 case VMINMAXBF16Zrrik:
19992 case VMINMAXBF16Zrrikz:
19993 return true;
19994 }
19995 return false;
19996}
19997
19998bool isVSHUFF64X2(unsigned Opcode) {
19999 switch (Opcode) {
20000 case VSHUFF64X2Z256rmbi:
20001 case VSHUFF64X2Z256rmbik:
20002 case VSHUFF64X2Z256rmbikz:
20003 case VSHUFF64X2Z256rmi:
20004 case VSHUFF64X2Z256rmik:
20005 case VSHUFF64X2Z256rmikz:
20006 case VSHUFF64X2Z256rri:
20007 case VSHUFF64X2Z256rrik:
20008 case VSHUFF64X2Z256rrikz:
20009 case VSHUFF64X2Zrmbi:
20010 case VSHUFF64X2Zrmbik:
20011 case VSHUFF64X2Zrmbikz:
20012 case VSHUFF64X2Zrmi:
20013 case VSHUFF64X2Zrmik:
20014 case VSHUFF64X2Zrmikz:
20015 case VSHUFF64X2Zrri:
20016 case VSHUFF64X2Zrrik:
20017 case VSHUFF64X2Zrrikz:
20018 return true;
20019 }
20020 return false;
20021}
20022
20023bool isVPACKUSWB(unsigned Opcode) {
20024 switch (Opcode) {
20025 case VPACKUSWBYrm:
20026 case VPACKUSWBYrr:
20027 case VPACKUSWBZ128rm:
20028 case VPACKUSWBZ128rmk:
20029 case VPACKUSWBZ128rmkz:
20030 case VPACKUSWBZ128rr:
20031 case VPACKUSWBZ128rrk:
20032 case VPACKUSWBZ128rrkz:
20033 case VPACKUSWBZ256rm:
20034 case VPACKUSWBZ256rmk:
20035 case VPACKUSWBZ256rmkz:
20036 case VPACKUSWBZ256rr:
20037 case VPACKUSWBZ256rrk:
20038 case VPACKUSWBZ256rrkz:
20039 case VPACKUSWBZrm:
20040 case VPACKUSWBZrmk:
20041 case VPACKUSWBZrmkz:
20042 case VPACKUSWBZrr:
20043 case VPACKUSWBZrrk:
20044 case VPACKUSWBZrrkz:
20045 case VPACKUSWBrm:
20046 case VPACKUSWBrr:
20047 return true;
20048 }
20049 return false;
20050}
20051
20052bool isVRSQRT28SS(unsigned Opcode) {
20053 switch (Opcode) {
20054 case VRSQRT28SSZm:
20055 case VRSQRT28SSZmk:
20056 case VRSQRT28SSZmkz:
20057 case VRSQRT28SSZr:
20058 case VRSQRT28SSZrb:
20059 case VRSQRT28SSZrbk:
20060 case VRSQRT28SSZrbkz:
20061 case VRSQRT28SSZrk:
20062 case VRSQRT28SSZrkz:
20063 return true;
20064 }
20065 return false;
20066}
20067
20068bool isGETSEC(unsigned Opcode) {
20069 return Opcode == GETSEC;
20070}
20071
20072bool isFXAM(unsigned Opcode) {
20073 return Opcode == XAM_F;
20074}
20075
20076bool isVEXTRACTF64X4(unsigned Opcode) {
20077 switch (Opcode) {
20078 case VEXTRACTF64X4Zmri:
20079 case VEXTRACTF64X4Zmrik:
20080 case VEXTRACTF64X4Zrri:
20081 case VEXTRACTF64X4Zrrik:
20082 case VEXTRACTF64X4Zrrikz:
20083 return true;
20084 }
20085 return false;
20086}
20087
20088bool isBLSR(unsigned Opcode) {
20089 switch (Opcode) {
20090 case BLSR32rm:
20091 case BLSR32rm_EVEX:
20092 case BLSR32rm_NF:
20093 case BLSR32rr:
20094 case BLSR32rr_EVEX:
20095 case BLSR32rr_NF:
20096 case BLSR64rm:
20097 case BLSR64rm_EVEX:
20098 case BLSR64rm_NF:
20099 case BLSR64rr:
20100 case BLSR64rr_EVEX:
20101 case BLSR64rr_NF:
20102 return true;
20103 }
20104 return false;
20105}
20106
20107bool isFILD(unsigned Opcode) {
20108 switch (Opcode) {
20109 case ILD_F16m:
20110 case ILD_F32m:
20111 case ILD_F64m:
20112 return true;
20113 }
20114 return false;
20115}
20116
20117bool isRETFQ(unsigned Opcode) {
20118 switch (Opcode) {
20119 case LRET64:
20120 case LRETI64:
20121 return true;
20122 }
20123 return false;
20124}
20125
20126bool isVADDSS(unsigned Opcode) {
20127 switch (Opcode) {
20128 case VADDSSZrm_Int:
20129 case VADDSSZrmk_Int:
20130 case VADDSSZrmkz_Int:
20131 case VADDSSZrr_Int:
20132 case VADDSSZrrb_Int:
20133 case VADDSSZrrbk_Int:
20134 case VADDSSZrrbkz_Int:
20135 case VADDSSZrrk_Int:
20136 case VADDSSZrrkz_Int:
20137 case VADDSSrm_Int:
20138 case VADDSSrr_Int:
20139 return true;
20140 }
20141 return false;
20142}
20143
20144bool isCOMISS(unsigned Opcode) {
20145 switch (Opcode) {
20146 case COMISSrm:
20147 case COMISSrr:
20148 return true;
20149 }
20150 return false;
20151}
20152
20153bool isCLI(unsigned Opcode) {
20154 return Opcode == CLI;
20155}
20156
20157bool isVERW(unsigned Opcode) {
20158 switch (Opcode) {
20159 case VERWm:
20160 case VERWr:
20161 return true;
20162 }
20163 return false;
20164}
20165
20166bool isBTC(unsigned Opcode) {
20167 switch (Opcode) {
20168 case BTC16mi8:
20169 case BTC16mr:
20170 case BTC16ri8:
20171 case BTC16rr:
20172 case BTC32mi8:
20173 case BTC32mr:
20174 case BTC32ri8:
20175 case BTC32rr:
20176 case BTC64mi8:
20177 case BTC64mr:
20178 case BTC64ri8:
20179 case BTC64rr:
20180 return true;
20181 }
20182 return false;
20183}
20184
20185bool isVPHADDUBQ(unsigned Opcode) {
20186 switch (Opcode) {
20187 case VPHADDUBQrm:
20188 case VPHADDUBQrr:
20189 return true;
20190 }
20191 return false;
20192}
20193
20194bool isVPORQ(unsigned Opcode) {
20195 switch (Opcode) {
20196 case VPORQZ128rm:
20197 case VPORQZ128rmb:
20198 case VPORQZ128rmbk:
20199 case VPORQZ128rmbkz:
20200 case VPORQZ128rmk:
20201 case VPORQZ128rmkz:
20202 case VPORQZ128rr:
20203 case VPORQZ128rrk:
20204 case VPORQZ128rrkz:
20205 case VPORQZ256rm:
20206 case VPORQZ256rmb:
20207 case VPORQZ256rmbk:
20208 case VPORQZ256rmbkz:
20209 case VPORQZ256rmk:
20210 case VPORQZ256rmkz:
20211 case VPORQZ256rr:
20212 case VPORQZ256rrk:
20213 case VPORQZ256rrkz:
20214 case VPORQZrm:
20215 case VPORQZrmb:
20216 case VPORQZrmbk:
20217 case VPORQZrmbkz:
20218 case VPORQZrmk:
20219 case VPORQZrmkz:
20220 case VPORQZrr:
20221 case VPORQZrrk:
20222 case VPORQZrrkz:
20223 return true;
20224 }
20225 return false;
20226}
20227
20228bool isORPD(unsigned Opcode) {
20229 switch (Opcode) {
20230 case ORPDrm:
20231 case ORPDrr:
20232 return true;
20233 }
20234 return false;
20235}
20236
20237bool isVMOVSS(unsigned Opcode) {
20238 switch (Opcode) {
20239 case VMOVSSZmr:
20240 case VMOVSSZmrk:
20241 case VMOVSSZrm:
20242 case VMOVSSZrmk:
20243 case VMOVSSZrmkz:
20244 case VMOVSSZrr:
20245 case VMOVSSZrr_REV:
20246 case VMOVSSZrrk:
20247 case VMOVSSZrrk_REV:
20248 case VMOVSSZrrkz:
20249 case VMOVSSZrrkz_REV:
20250 case VMOVSSmr:
20251 case VMOVSSrm:
20252 case VMOVSSrr:
20253 case VMOVSSrr_REV:
20254 return true;
20255 }
20256 return false;
20257}
20258
20259bool isVPSUBD(unsigned Opcode) {
20260 switch (Opcode) {
20261 case VPSUBDYrm:
20262 case VPSUBDYrr:
20263 case VPSUBDZ128rm:
20264 case VPSUBDZ128rmb:
20265 case VPSUBDZ128rmbk:
20266 case VPSUBDZ128rmbkz:
20267 case VPSUBDZ128rmk:
20268 case VPSUBDZ128rmkz:
20269 case VPSUBDZ128rr:
20270 case VPSUBDZ128rrk:
20271 case VPSUBDZ128rrkz:
20272 case VPSUBDZ256rm:
20273 case VPSUBDZ256rmb:
20274 case VPSUBDZ256rmbk:
20275 case VPSUBDZ256rmbkz:
20276 case VPSUBDZ256rmk:
20277 case VPSUBDZ256rmkz:
20278 case VPSUBDZ256rr:
20279 case VPSUBDZ256rrk:
20280 case VPSUBDZ256rrkz:
20281 case VPSUBDZrm:
20282 case VPSUBDZrmb:
20283 case VPSUBDZrmbk:
20284 case VPSUBDZrmbkz:
20285 case VPSUBDZrmk:
20286 case VPSUBDZrmkz:
20287 case VPSUBDZrr:
20288 case VPSUBDZrrk:
20289 case VPSUBDZrrkz:
20290 case VPSUBDrm:
20291 case VPSUBDrr:
20292 return true;
20293 }
20294 return false;
20295}
20296
20297bool isVGATHERPF1QPD(unsigned Opcode) {
20298 return Opcode == VGATHERPF1QPDm;
20299}
20300
20301bool isENCODEKEY256(unsigned Opcode) {
20302 return Opcode == ENCODEKEY256;
20303}
20304
20305bool isGF2P8AFFINEINVQB(unsigned Opcode) {
20306 switch (Opcode) {
20307 case GF2P8AFFINEINVQBrmi:
20308 case GF2P8AFFINEINVQBrri:
20309 return true;
20310 }
20311 return false;
20312}
20313
20314bool isXRSTOR64(unsigned Opcode) {
20315 return Opcode == XRSTOR64;
20316}
20317
20318bool isKANDW(unsigned Opcode) {
20319 return Opcode == KANDWkk;
20320}
20321
20322bool isLODSQ(unsigned Opcode) {
20323 return Opcode == LODSQ;
20324}
20325
20326bool isVMOVRSW(unsigned Opcode) {
20327 switch (Opcode) {
20328 case VMOVRSWZ128m:
20329 case VMOVRSWZ128mk:
20330 case VMOVRSWZ128mkz:
20331 case VMOVRSWZ256m:
20332 case VMOVRSWZ256mk:
20333 case VMOVRSWZ256mkz:
20334 case VMOVRSWZm:
20335 case VMOVRSWZmk:
20336 case VMOVRSWZmkz:
20337 return true;
20338 }
20339 return false;
20340}
20341
20342bool isVSUBSH(unsigned Opcode) {
20343 switch (Opcode) {
20344 case VSUBSHZrm_Int:
20345 case VSUBSHZrmk_Int:
20346 case VSUBSHZrmkz_Int:
20347 case VSUBSHZrr_Int:
20348 case VSUBSHZrrb_Int:
20349 case VSUBSHZrrbk_Int:
20350 case VSUBSHZrrbkz_Int:
20351 case VSUBSHZrrk_Int:
20352 case VSUBSHZrrkz_Int:
20353 return true;
20354 }
20355 return false;
20356}
20357
20358bool isLSS(unsigned Opcode) {
20359 switch (Opcode) {
20360 case LSS16rm:
20361 case LSS32rm:
20362 case LSS64rm:
20363 return true;
20364 }
20365 return false;
20366}
20367
20368bool isPMOVSXBQ(unsigned Opcode) {
20369 switch (Opcode) {
20370 case PMOVSXBQrm:
20371 case PMOVSXBQrr:
20372 return true;
20373 }
20374 return false;
20375}
20376
20377bool isVCVTTSD2SIS(unsigned Opcode) {
20378 switch (Opcode) {
20379 case VCVTTSD2SI64Srm_Int:
20380 case VCVTTSD2SI64Srr_Int:
20381 case VCVTTSD2SI64Srrb_Int:
20382 case VCVTTSD2SISrm_Int:
20383 case VCVTTSD2SISrr_Int:
20384 case VCVTTSD2SISrrb_Int:
20385 return true;
20386 }
20387 return false;
20388}
20389
20390bool isVCMPSH(unsigned Opcode) {
20391 switch (Opcode) {
20392 case VCMPSHZrmi_Int:
20393 case VCMPSHZrmik_Int:
20394 case VCMPSHZrri_Int:
20395 case VCMPSHZrrib_Int:
20396 case VCMPSHZrribk_Int:
20397 case VCMPSHZrrik_Int:
20398 return true;
20399 }
20400 return false;
20401}
20402
20403bool isVFMADD132PS(unsigned Opcode) {
20404 switch (Opcode) {
20405 case VFMADD132PSYm:
20406 case VFMADD132PSYr:
20407 case VFMADD132PSZ128m:
20408 case VFMADD132PSZ128mb:
20409 case VFMADD132PSZ128mbk:
20410 case VFMADD132PSZ128mbkz:
20411 case VFMADD132PSZ128mk:
20412 case VFMADD132PSZ128mkz:
20413 case VFMADD132PSZ128r:
20414 case VFMADD132PSZ128rk:
20415 case VFMADD132PSZ128rkz:
20416 case VFMADD132PSZ256m:
20417 case VFMADD132PSZ256mb:
20418 case VFMADD132PSZ256mbk:
20419 case VFMADD132PSZ256mbkz:
20420 case VFMADD132PSZ256mk:
20421 case VFMADD132PSZ256mkz:
20422 case VFMADD132PSZ256r:
20423 case VFMADD132PSZ256rk:
20424 case VFMADD132PSZ256rkz:
20425 case VFMADD132PSZm:
20426 case VFMADD132PSZmb:
20427 case VFMADD132PSZmbk:
20428 case VFMADD132PSZmbkz:
20429 case VFMADD132PSZmk:
20430 case VFMADD132PSZmkz:
20431 case VFMADD132PSZr:
20432 case VFMADD132PSZrb:
20433 case VFMADD132PSZrbk:
20434 case VFMADD132PSZrbkz:
20435 case VFMADD132PSZrk:
20436 case VFMADD132PSZrkz:
20437 case VFMADD132PSm:
20438 case VFMADD132PSr:
20439 return true;
20440 }
20441 return false;
20442}
20443
20444bool isVPACKSSWB(unsigned Opcode) {
20445 switch (Opcode) {
20446 case VPACKSSWBYrm:
20447 case VPACKSSWBYrr:
20448 case VPACKSSWBZ128rm:
20449 case VPACKSSWBZ128rmk:
20450 case VPACKSSWBZ128rmkz:
20451 case VPACKSSWBZ128rr:
20452 case VPACKSSWBZ128rrk:
20453 case VPACKSSWBZ128rrkz:
20454 case VPACKSSWBZ256rm:
20455 case VPACKSSWBZ256rmk:
20456 case VPACKSSWBZ256rmkz:
20457 case VPACKSSWBZ256rr:
20458 case VPACKSSWBZ256rrk:
20459 case VPACKSSWBZ256rrkz:
20460 case VPACKSSWBZrm:
20461 case VPACKSSWBZrmk:
20462 case VPACKSSWBZrmkz:
20463 case VPACKSSWBZrr:
20464 case VPACKSSWBZrrk:
20465 case VPACKSSWBZrrkz:
20466 case VPACKSSWBrm:
20467 case VPACKSSWBrr:
20468 return true;
20469 }
20470 return false;
20471}
20472
20473bool isPCMPGTQ(unsigned Opcode) {
20474 switch (Opcode) {
20475 case PCMPGTQrm:
20476 case PCMPGTQrr:
20477 return true;
20478 }
20479 return false;
20480}
20481
20482bool isVFMADD132SH(unsigned Opcode) {
20483 switch (Opcode) {
20484 case VFMADD132SHZm_Int:
20485 case VFMADD132SHZmk_Int:
20486 case VFMADD132SHZmkz_Int:
20487 case VFMADD132SHZr_Int:
20488 case VFMADD132SHZrb_Int:
20489 case VFMADD132SHZrbk_Int:
20490 case VFMADD132SHZrbkz_Int:
20491 case VFMADD132SHZrk_Int:
20492 case VFMADD132SHZrkz_Int:
20493 return true;
20494 }
20495 return false;
20496}
20497
20498bool isVCVTUQQ2PH(unsigned Opcode) {
20499 switch (Opcode) {
20500 case VCVTUQQ2PHZ128rm:
20501 case VCVTUQQ2PHZ128rmb:
20502 case VCVTUQQ2PHZ128rmbk:
20503 case VCVTUQQ2PHZ128rmbkz:
20504 case VCVTUQQ2PHZ128rmk:
20505 case VCVTUQQ2PHZ128rmkz:
20506 case VCVTUQQ2PHZ128rr:
20507 case VCVTUQQ2PHZ128rrk:
20508 case VCVTUQQ2PHZ128rrkz:
20509 case VCVTUQQ2PHZ256rm:
20510 case VCVTUQQ2PHZ256rmb:
20511 case VCVTUQQ2PHZ256rmbk:
20512 case VCVTUQQ2PHZ256rmbkz:
20513 case VCVTUQQ2PHZ256rmk:
20514 case VCVTUQQ2PHZ256rmkz:
20515 case VCVTUQQ2PHZ256rr:
20516 case VCVTUQQ2PHZ256rrk:
20517 case VCVTUQQ2PHZ256rrkz:
20518 case VCVTUQQ2PHZrm:
20519 case VCVTUQQ2PHZrmb:
20520 case VCVTUQQ2PHZrmbk:
20521 case VCVTUQQ2PHZrmbkz:
20522 case VCVTUQQ2PHZrmk:
20523 case VCVTUQQ2PHZrmkz:
20524 case VCVTUQQ2PHZrr:
20525 case VCVTUQQ2PHZrrb:
20526 case VCVTUQQ2PHZrrbk:
20527 case VCVTUQQ2PHZrrbkz:
20528 case VCVTUQQ2PHZrrk:
20529 case VCVTUQQ2PHZrrkz:
20530 return true;
20531 }
20532 return false;
20533}
20534
20535bool isVCVTQQ2PS(unsigned Opcode) {
20536 switch (Opcode) {
20537 case VCVTQQ2PSZ128rm:
20538 case VCVTQQ2PSZ128rmb:
20539 case VCVTQQ2PSZ128rmbk:
20540 case VCVTQQ2PSZ128rmbkz:
20541 case VCVTQQ2PSZ128rmk:
20542 case VCVTQQ2PSZ128rmkz:
20543 case VCVTQQ2PSZ128rr:
20544 case VCVTQQ2PSZ128rrk:
20545 case VCVTQQ2PSZ128rrkz:
20546 case VCVTQQ2PSZ256rm:
20547 case VCVTQQ2PSZ256rmb:
20548 case VCVTQQ2PSZ256rmbk:
20549 case VCVTQQ2PSZ256rmbkz:
20550 case VCVTQQ2PSZ256rmk:
20551 case VCVTQQ2PSZ256rmkz:
20552 case VCVTQQ2PSZ256rr:
20553 case VCVTQQ2PSZ256rrk:
20554 case VCVTQQ2PSZ256rrkz:
20555 case VCVTQQ2PSZrm:
20556 case VCVTQQ2PSZrmb:
20557 case VCVTQQ2PSZrmbk:
20558 case VCVTQQ2PSZrmbkz:
20559 case VCVTQQ2PSZrmk:
20560 case VCVTQQ2PSZrmkz:
20561 case VCVTQQ2PSZrr:
20562 case VCVTQQ2PSZrrb:
20563 case VCVTQQ2PSZrrbk:
20564 case VCVTQQ2PSZrrbkz:
20565 case VCVTQQ2PSZrrk:
20566 case VCVTQQ2PSZrrkz:
20567 return true;
20568 }
20569 return false;
20570}
20571
20572bool isVCVTTSS2USI(unsigned Opcode) {
20573 switch (Opcode) {
20574 case VCVTTSS2USI64Zrm_Int:
20575 case VCVTTSS2USI64Zrr_Int:
20576 case VCVTTSS2USI64Zrrb_Int:
20577 case VCVTTSS2USIZrm_Int:
20578 case VCVTTSS2USIZrr_Int:
20579 case VCVTTSS2USIZrrb_Int:
20580 return true;
20581 }
20582 return false;
20583}
20584
20585bool isVPMOVM2Q(unsigned Opcode) {
20586 switch (Opcode) {
20587 case VPMOVM2QZ128rk:
20588 case VPMOVM2QZ256rk:
20589 case VPMOVM2QZrk:
20590 return true;
20591 }
20592 return false;
20593}
20594
20595bool isVMOVD(unsigned Opcode) {
20596 switch (Opcode) {
20597 case VMOVDI2PDIZrm:
20598 case VMOVDI2PDIZrr:
20599 case VMOVDI2PDIrm:
20600 case VMOVDI2PDIrr:
20601 case VMOVPDI2DIZmr:
20602 case VMOVPDI2DIZrr:
20603 case VMOVPDI2DImr:
20604 case VMOVPDI2DIrr:
20605 case VMOVZPDILo2PDIZmr:
20606 case VMOVZPDILo2PDIZrm:
20607 case VMOVZPDILo2PDIZrr:
20608 case VMOVZPDILo2PDIZrr2:
20609 return true;
20610 }
20611 return false;
20612}
20613
20614bool isVCVTTPS2QQS(unsigned Opcode) {
20615 switch (Opcode) {
20616 case VCVTTPS2QQSZ128rm:
20617 case VCVTTPS2QQSZ128rmb:
20618 case VCVTTPS2QQSZ128rmbk:
20619 case VCVTTPS2QQSZ128rmbkz:
20620 case VCVTTPS2QQSZ128rmk:
20621 case VCVTTPS2QQSZ128rmkz:
20622 case VCVTTPS2QQSZ128rr:
20623 case VCVTTPS2QQSZ128rrk:
20624 case VCVTTPS2QQSZ128rrkz:
20625 case VCVTTPS2QQSZ256rm:
20626 case VCVTTPS2QQSZ256rmb:
20627 case VCVTTPS2QQSZ256rmbk:
20628 case VCVTTPS2QQSZ256rmbkz:
20629 case VCVTTPS2QQSZ256rmk:
20630 case VCVTTPS2QQSZ256rmkz:
20631 case VCVTTPS2QQSZ256rr:
20632 case VCVTTPS2QQSZ256rrb:
20633 case VCVTTPS2QQSZ256rrbk:
20634 case VCVTTPS2QQSZ256rrbkz:
20635 case VCVTTPS2QQSZ256rrk:
20636 case VCVTTPS2QQSZ256rrkz:
20637 case VCVTTPS2QQSZrm:
20638 case VCVTTPS2QQSZrmb:
20639 case VCVTTPS2QQSZrmbk:
20640 case VCVTTPS2QQSZrmbkz:
20641 case VCVTTPS2QQSZrmk:
20642 case VCVTTPS2QQSZrmkz:
20643 case VCVTTPS2QQSZrr:
20644 case VCVTTPS2QQSZrrb:
20645 case VCVTTPS2QQSZrrbk:
20646 case VCVTTPS2QQSZrrbkz:
20647 case VCVTTPS2QQSZrrk:
20648 case VCVTTPS2QQSZrrkz:
20649 return true;
20650 }
20651 return false;
20652}
20653
20654bool isVSQRTBF16(unsigned Opcode) {
20655 switch (Opcode) {
20656 case VSQRTBF16Z128m:
20657 case VSQRTBF16Z128mb:
20658 case VSQRTBF16Z128mbk:
20659 case VSQRTBF16Z128mbkz:
20660 case VSQRTBF16Z128mk:
20661 case VSQRTBF16Z128mkz:
20662 case VSQRTBF16Z128r:
20663 case VSQRTBF16Z128rk:
20664 case VSQRTBF16Z128rkz:
20665 case VSQRTBF16Z256m:
20666 case VSQRTBF16Z256mb:
20667 case VSQRTBF16Z256mbk:
20668 case VSQRTBF16Z256mbkz:
20669 case VSQRTBF16Z256mk:
20670 case VSQRTBF16Z256mkz:
20671 case VSQRTBF16Z256r:
20672 case VSQRTBF16Z256rk:
20673 case VSQRTBF16Z256rkz:
20674 case VSQRTBF16Zm:
20675 case VSQRTBF16Zmb:
20676 case VSQRTBF16Zmbk:
20677 case VSQRTBF16Zmbkz:
20678 case VSQRTBF16Zmk:
20679 case VSQRTBF16Zmkz:
20680 case VSQRTBF16Zr:
20681 case VSQRTBF16Zrk:
20682 case VSQRTBF16Zrkz:
20683 return true;
20684 }
20685 return false;
20686}
20687
20688bool isVFPCLASSPH(unsigned Opcode) {
20689 switch (Opcode) {
20690 case VFPCLASSPHZ128mbi:
20691 case VFPCLASSPHZ128mbik:
20692 case VFPCLASSPHZ128mi:
20693 case VFPCLASSPHZ128mik:
20694 case VFPCLASSPHZ128ri:
20695 case VFPCLASSPHZ128rik:
20696 case VFPCLASSPHZ256mbi:
20697 case VFPCLASSPHZ256mbik:
20698 case VFPCLASSPHZ256mi:
20699 case VFPCLASSPHZ256mik:
20700 case VFPCLASSPHZ256ri:
20701 case VFPCLASSPHZ256rik:
20702 case VFPCLASSPHZmbi:
20703 case VFPCLASSPHZmbik:
20704 case VFPCLASSPHZmi:
20705 case VFPCLASSPHZmik:
20706 case VFPCLASSPHZri:
20707 case VFPCLASSPHZrik:
20708 return true;
20709 }
20710 return false;
20711}
20712
20713bool isVCVTSS2SH(unsigned Opcode) {
20714 switch (Opcode) {
20715 case VCVTSS2SHZrm_Int:
20716 case VCVTSS2SHZrmk_Int:
20717 case VCVTSS2SHZrmkz_Int:
20718 case VCVTSS2SHZrr_Int:
20719 case VCVTSS2SHZrrb_Int:
20720 case VCVTSS2SHZrrbk_Int:
20721 case VCVTSS2SHZrrbkz_Int:
20722 case VCVTSS2SHZrrk_Int:
20723 case VCVTSS2SHZrrkz_Int:
20724 return true;
20725 }
20726 return false;
20727}
20728
20729bool isSCASB(unsigned Opcode) {
20730 return Opcode == SCASB;
20731}
20732
20733bool isPSRLD(unsigned Opcode) {
20734 switch (Opcode) {
20735 case MMX_PSRLDri:
20736 case MMX_PSRLDrm:
20737 case MMX_PSRLDrr:
20738 case PSRLDri:
20739 case PSRLDrm:
20740 case PSRLDrr:
20741 return true;
20742 }
20743 return false;
20744}
20745
20746bool isVADDPH(unsigned Opcode) {
20747 switch (Opcode) {
20748 case VADDPHZ128rm:
20749 case VADDPHZ128rmb:
20750 case VADDPHZ128rmbk:
20751 case VADDPHZ128rmbkz:
20752 case VADDPHZ128rmk:
20753 case VADDPHZ128rmkz:
20754 case VADDPHZ128rr:
20755 case VADDPHZ128rrk:
20756 case VADDPHZ128rrkz:
20757 case VADDPHZ256rm:
20758 case VADDPHZ256rmb:
20759 case VADDPHZ256rmbk:
20760 case VADDPHZ256rmbkz:
20761 case VADDPHZ256rmk:
20762 case VADDPHZ256rmkz:
20763 case VADDPHZ256rr:
20764 case VADDPHZ256rrk:
20765 case VADDPHZ256rrkz:
20766 case VADDPHZrm:
20767 case VADDPHZrmb:
20768 case VADDPHZrmbk:
20769 case VADDPHZrmbkz:
20770 case VADDPHZrmk:
20771 case VADDPHZrmkz:
20772 case VADDPHZrr:
20773 case VADDPHZrrb:
20774 case VADDPHZrrbk:
20775 case VADDPHZrrbkz:
20776 case VADDPHZrrk:
20777 case VADDPHZrrkz:
20778 return true;
20779 }
20780 return false;
20781}
20782
20783bool isFSUB(unsigned Opcode) {
20784 switch (Opcode) {
20785 case SUB_F32m:
20786 case SUB_F64m:
20787 case SUB_FST0r:
20788 case SUB_FrST0:
20789 return true;
20790 }
20791 return false;
20792}
20793
20794bool isVCVTTPH2IBS(unsigned Opcode) {
20795 switch (Opcode) {
20796 case VCVTTPH2IBSZ128rm:
20797 case VCVTTPH2IBSZ128rmb:
20798 case VCVTTPH2IBSZ128rmbk:
20799 case VCVTTPH2IBSZ128rmbkz:
20800 case VCVTTPH2IBSZ128rmk:
20801 case VCVTTPH2IBSZ128rmkz:
20802 case VCVTTPH2IBSZ128rr:
20803 case VCVTTPH2IBSZ128rrk:
20804 case VCVTTPH2IBSZ128rrkz:
20805 case VCVTTPH2IBSZ256rm:
20806 case VCVTTPH2IBSZ256rmb:
20807 case VCVTTPH2IBSZ256rmbk:
20808 case VCVTTPH2IBSZ256rmbkz:
20809 case VCVTTPH2IBSZ256rmk:
20810 case VCVTTPH2IBSZ256rmkz:
20811 case VCVTTPH2IBSZ256rr:
20812 case VCVTTPH2IBSZ256rrk:
20813 case VCVTTPH2IBSZ256rrkz:
20814 case VCVTTPH2IBSZrm:
20815 case VCVTTPH2IBSZrmb:
20816 case VCVTTPH2IBSZrmbk:
20817 case VCVTTPH2IBSZrmbkz:
20818 case VCVTTPH2IBSZrmk:
20819 case VCVTTPH2IBSZrmkz:
20820 case VCVTTPH2IBSZrr:
20821 case VCVTTPH2IBSZrrb:
20822 case VCVTTPH2IBSZrrbk:
20823 case VCVTTPH2IBSZrrbkz:
20824 case VCVTTPH2IBSZrrk:
20825 case VCVTTPH2IBSZrrkz:
20826 return true;
20827 }
20828 return false;
20829}
20830
20831bool isVEXTRACTI64X2(unsigned Opcode) {
20832 switch (Opcode) {
20833 case VEXTRACTI64X2Z256mri:
20834 case VEXTRACTI64X2Z256mrik:
20835 case VEXTRACTI64X2Z256rri:
20836 case VEXTRACTI64X2Z256rrik:
20837 case VEXTRACTI64X2Z256rrikz:
20838 case VEXTRACTI64X2Zmri:
20839 case VEXTRACTI64X2Zmrik:
20840 case VEXTRACTI64X2Zrri:
20841 case VEXTRACTI64X2Zrrik:
20842 case VEXTRACTI64X2Zrrikz:
20843 return true;
20844 }
20845 return false;
20846}
20847
20848bool isVPSHLDD(unsigned Opcode) {
20849 switch (Opcode) {
20850 case VPSHLDDZ128rmbi:
20851 case VPSHLDDZ128rmbik:
20852 case VPSHLDDZ128rmbikz:
20853 case VPSHLDDZ128rmi:
20854 case VPSHLDDZ128rmik:
20855 case VPSHLDDZ128rmikz:
20856 case VPSHLDDZ128rri:
20857 case VPSHLDDZ128rrik:
20858 case VPSHLDDZ128rrikz:
20859 case VPSHLDDZ256rmbi:
20860 case VPSHLDDZ256rmbik:
20861 case VPSHLDDZ256rmbikz:
20862 case VPSHLDDZ256rmi:
20863 case VPSHLDDZ256rmik:
20864 case VPSHLDDZ256rmikz:
20865 case VPSHLDDZ256rri:
20866 case VPSHLDDZ256rrik:
20867 case VPSHLDDZ256rrikz:
20868 case VPSHLDDZrmbi:
20869 case VPSHLDDZrmbik:
20870 case VPSHLDDZrmbikz:
20871 case VPSHLDDZrmi:
20872 case VPSHLDDZrmik:
20873 case VPSHLDDZrmikz:
20874 case VPSHLDDZrri:
20875 case VPSHLDDZrrik:
20876 case VPSHLDDZrrikz:
20877 return true;
20878 }
20879 return false;
20880}
20881
20882bool isPMINUW(unsigned Opcode) {
20883 switch (Opcode) {
20884 case PMINUWrm:
20885 case PMINUWrr:
20886 return true;
20887 }
20888 return false;
20889}
20890
20891bool isPSUBSB(unsigned Opcode) {
20892 switch (Opcode) {
20893 case MMX_PSUBSBrm:
20894 case MMX_PSUBSBrr:
20895 case PSUBSBrm:
20896 case PSUBSBrr:
20897 return true;
20898 }
20899 return false;
20900}
20901
20902bool isVCVT2PS2PHX(unsigned Opcode) {
20903 switch (Opcode) {
20904 case VCVT2PS2PHXZ128rm:
20905 case VCVT2PS2PHXZ128rmb:
20906 case VCVT2PS2PHXZ128rmbk:
20907 case VCVT2PS2PHXZ128rmbkz:
20908 case VCVT2PS2PHXZ128rmk:
20909 case VCVT2PS2PHXZ128rmkz:
20910 case VCVT2PS2PHXZ128rr:
20911 case VCVT2PS2PHXZ128rrk:
20912 case VCVT2PS2PHXZ128rrkz:
20913 case VCVT2PS2PHXZ256rm:
20914 case VCVT2PS2PHXZ256rmb:
20915 case VCVT2PS2PHXZ256rmbk:
20916 case VCVT2PS2PHXZ256rmbkz:
20917 case VCVT2PS2PHXZ256rmk:
20918 case VCVT2PS2PHXZ256rmkz:
20919 case VCVT2PS2PHXZ256rr:
20920 case VCVT2PS2PHXZ256rrk:
20921 case VCVT2PS2PHXZ256rrkz:
20922 case VCVT2PS2PHXZrm:
20923 case VCVT2PS2PHXZrmb:
20924 case VCVT2PS2PHXZrmbk:
20925 case VCVT2PS2PHXZrmbkz:
20926 case VCVT2PS2PHXZrmk:
20927 case VCVT2PS2PHXZrmkz:
20928 case VCVT2PS2PHXZrr:
20929 case VCVT2PS2PHXZrrb:
20930 case VCVT2PS2PHXZrrbk:
20931 case VCVT2PS2PHXZrrbkz:
20932 case VCVT2PS2PHXZrrk:
20933 case VCVT2PS2PHXZrrkz:
20934 return true;
20935 }
20936 return false;
20937}
20938
20939bool isVPCMPEQD(unsigned Opcode) {
20940 switch (Opcode) {
20941 case VPCMPEQDYrm:
20942 case VPCMPEQDYrr:
20943 case VPCMPEQDZ128rm:
20944 case VPCMPEQDZ128rmb:
20945 case VPCMPEQDZ128rmbk:
20946 case VPCMPEQDZ128rmk:
20947 case VPCMPEQDZ128rr:
20948 case VPCMPEQDZ128rrk:
20949 case VPCMPEQDZ256rm:
20950 case VPCMPEQDZ256rmb:
20951 case VPCMPEQDZ256rmbk:
20952 case VPCMPEQDZ256rmk:
20953 case VPCMPEQDZ256rr:
20954 case VPCMPEQDZ256rrk:
20955 case VPCMPEQDZrm:
20956 case VPCMPEQDZrmb:
20957 case VPCMPEQDZrmbk:
20958 case VPCMPEQDZrmk:
20959 case VPCMPEQDZrr:
20960 case VPCMPEQDZrrk:
20961 case VPCMPEQDrm:
20962 case VPCMPEQDrr:
20963 return true;
20964 }
20965 return false;
20966}
20967
20968bool isVPSCATTERQD(unsigned Opcode) {
20969 switch (Opcode) {
20970 case VPSCATTERQDZ128mr:
20971 case VPSCATTERQDZ256mr:
20972 case VPSCATTERQDZmr:
20973 return true;
20974 }
20975 return false;
20976}
20977
20978bool isKXNORB(unsigned Opcode) {
20979 return Opcode == KXNORBkk;
20980}
20981
20982bool isLDDQU(unsigned Opcode) {
20983 return Opcode == LDDQUrm;
20984}
20985
20986bool isMASKMOVQ(unsigned Opcode) {
20987 switch (Opcode) {
20988 case MMX_MASKMOVQ:
20989 case MMX_MASKMOVQ64:
20990 return true;
20991 }
20992 return false;
20993}
20994
20995bool isPABSW(unsigned Opcode) {
20996 switch (Opcode) {
20997 case MMX_PABSWrm:
20998 case MMX_PABSWrr:
20999 case PABSWrm:
21000 case PABSWrr:
21001 return true;
21002 }
21003 return false;
21004}
21005
21006bool isVPCOMQ(unsigned Opcode) {
21007 switch (Opcode) {
21008 case VPCOMQmi:
21009 case VPCOMQri:
21010 return true;
21011 }
21012 return false;
21013}
21014
21015bool isVPROLD(unsigned Opcode) {
21016 switch (Opcode) {
21017 case VPROLDZ128mbi:
21018 case VPROLDZ128mbik:
21019 case VPROLDZ128mbikz:
21020 case VPROLDZ128mi:
21021 case VPROLDZ128mik:
21022 case VPROLDZ128mikz:
21023 case VPROLDZ128ri:
21024 case VPROLDZ128rik:
21025 case VPROLDZ128rikz:
21026 case VPROLDZ256mbi:
21027 case VPROLDZ256mbik:
21028 case VPROLDZ256mbikz:
21029 case VPROLDZ256mi:
21030 case VPROLDZ256mik:
21031 case VPROLDZ256mikz:
21032 case VPROLDZ256ri:
21033 case VPROLDZ256rik:
21034 case VPROLDZ256rikz:
21035 case VPROLDZmbi:
21036 case VPROLDZmbik:
21037 case VPROLDZmbikz:
21038 case VPROLDZmi:
21039 case VPROLDZmik:
21040 case VPROLDZmikz:
21041 case VPROLDZri:
21042 case VPROLDZrik:
21043 case VPROLDZrikz:
21044 return true;
21045 }
21046 return false;
21047}
21048
21049bool isVSCATTERDPD(unsigned Opcode) {
21050 switch (Opcode) {
21051 case VSCATTERDPDZ128mr:
21052 case VSCATTERDPDZ256mr:
21053 case VSCATTERDPDZmr:
21054 return true;
21055 }
21056 return false;
21057}
21058
21059bool isFXRSTOR(unsigned Opcode) {
21060 return Opcode == FXRSTOR;
21061}
21062
21063bool isVPCMPUW(unsigned Opcode) {
21064 switch (Opcode) {
21065 case VPCMPUWZ128rmi:
21066 case VPCMPUWZ128rmik:
21067 case VPCMPUWZ128rri:
21068 case VPCMPUWZ128rrik:
21069 case VPCMPUWZ256rmi:
21070 case VPCMPUWZ256rmik:
21071 case VPCMPUWZ256rri:
21072 case VPCMPUWZ256rrik:
21073 case VPCMPUWZrmi:
21074 case VPCMPUWZrmik:
21075 case VPCMPUWZrri:
21076 case VPCMPUWZrrik:
21077 return true;
21078 }
21079 return false;
21080}
21081
21082bool isWBINVD(unsigned Opcode) {
21083 return Opcode == WBINVD;
21084}
21085
21086bool isVCVTTPD2UDQ(unsigned Opcode) {
21087 switch (Opcode) {
21088 case VCVTTPD2UDQZ128rm:
21089 case VCVTTPD2UDQZ128rmb:
21090 case VCVTTPD2UDQZ128rmbk:
21091 case VCVTTPD2UDQZ128rmbkz:
21092 case VCVTTPD2UDQZ128rmk:
21093 case VCVTTPD2UDQZ128rmkz:
21094 case VCVTTPD2UDQZ128rr:
21095 case VCVTTPD2UDQZ128rrk:
21096 case VCVTTPD2UDQZ128rrkz:
21097 case VCVTTPD2UDQZ256rm:
21098 case VCVTTPD2UDQZ256rmb:
21099 case VCVTTPD2UDQZ256rmbk:
21100 case VCVTTPD2UDQZ256rmbkz:
21101 case VCVTTPD2UDQZ256rmk:
21102 case VCVTTPD2UDQZ256rmkz:
21103 case VCVTTPD2UDQZ256rr:
21104 case VCVTTPD2UDQZ256rrk:
21105 case VCVTTPD2UDQZ256rrkz:
21106 case VCVTTPD2UDQZrm:
21107 case VCVTTPD2UDQZrmb:
21108 case VCVTTPD2UDQZrmbk:
21109 case VCVTTPD2UDQZrmbkz:
21110 case VCVTTPD2UDQZrmk:
21111 case VCVTTPD2UDQZrmkz:
21112 case VCVTTPD2UDQZrr:
21113 case VCVTTPD2UDQZrrb:
21114 case VCVTTPD2UDQZrrbk:
21115 case VCVTTPD2UDQZrrbkz:
21116 case VCVTTPD2UDQZrrk:
21117 case VCVTTPD2UDQZrrkz:
21118 return true;
21119 }
21120 return false;
21121}
21122
21123bool isERETU(unsigned Opcode) {
21124 return Opcode == ERETU;
21125}
21126
21127bool isPFRCPIT2(unsigned Opcode) {
21128 switch (Opcode) {
21129 case PFRCPIT2rm:
21130 case PFRCPIT2rr:
21131 return true;
21132 }
21133 return false;
21134}
21135
21136bool isVPERMT2W(unsigned Opcode) {
21137 switch (Opcode) {
21138 case VPERMT2WZ128rm:
21139 case VPERMT2WZ128rmk:
21140 case VPERMT2WZ128rmkz:
21141 case VPERMT2WZ128rr:
21142 case VPERMT2WZ128rrk:
21143 case VPERMT2WZ128rrkz:
21144 case VPERMT2WZ256rm:
21145 case VPERMT2WZ256rmk:
21146 case VPERMT2WZ256rmkz:
21147 case VPERMT2WZ256rr:
21148 case VPERMT2WZ256rrk:
21149 case VPERMT2WZ256rrkz:
21150 case VPERMT2WZrm:
21151 case VPERMT2WZrmk:
21152 case VPERMT2WZrmkz:
21153 case VPERMT2WZrr:
21154 case VPERMT2WZrrk:
21155 case VPERMT2WZrrkz:
21156 return true;
21157 }
21158 return false;
21159}
21160
21161bool isVEXTRACTF32X4(unsigned Opcode) {
21162 switch (Opcode) {
21163 case VEXTRACTF32X4Z256mri:
21164 case VEXTRACTF32X4Z256mrik:
21165 case VEXTRACTF32X4Z256rri:
21166 case VEXTRACTF32X4Z256rrik:
21167 case VEXTRACTF32X4Z256rrikz:
21168 case VEXTRACTF32X4Zmri:
21169 case VEXTRACTF32X4Zmrik:
21170 case VEXTRACTF32X4Zrri:
21171 case VEXTRACTF32X4Zrrik:
21172 case VEXTRACTF32X4Zrrikz:
21173 return true;
21174 }
21175 return false;
21176}
21177
21178bool isVGATHERPF0DPD(unsigned Opcode) {
21179 return Opcode == VGATHERPF0DPDm;
21180}
21181
21182bool isVBROADCASTF32X2(unsigned Opcode) {
21183 switch (Opcode) {
21184 case VBROADCASTF32X2Z256rm:
21185 case VBROADCASTF32X2Z256rmk:
21186 case VBROADCASTF32X2Z256rmkz:
21187 case VBROADCASTF32X2Z256rr:
21188 case VBROADCASTF32X2Z256rrk:
21189 case VBROADCASTF32X2Z256rrkz:
21190 case VBROADCASTF32X2Zrm:
21191 case VBROADCASTF32X2Zrmk:
21192 case VBROADCASTF32X2Zrmkz:
21193 case VBROADCASTF32X2Zrr:
21194 case VBROADCASTF32X2Zrrk:
21195 case VBROADCASTF32X2Zrrkz:
21196 return true;
21197 }
21198 return false;
21199}
21200
21201bool isVRCP14SD(unsigned Opcode) {
21202 switch (Opcode) {
21203 case VRCP14SDZrm:
21204 case VRCP14SDZrmk:
21205 case VRCP14SDZrmkz:
21206 case VRCP14SDZrr:
21207 case VRCP14SDZrrk:
21208 case VRCP14SDZrrkz:
21209 return true;
21210 }
21211 return false;
21212}
21213
21214bool isLAHF(unsigned Opcode) {
21215 return Opcode == LAHF;
21216}
21217
21218bool isPABSD(unsigned Opcode) {
21219 switch (Opcode) {
21220 case MMX_PABSDrm:
21221 case MMX_PABSDrr:
21222 case PABSDrm:
21223 case PABSDrr:
21224 return true;
21225 }
21226 return false;
21227}
21228
21229bool isPINSRB(unsigned Opcode) {
21230 switch (Opcode) {
21231 case PINSRBrmi:
21232 case PINSRBrri:
21233 return true;
21234 }
21235 return false;
21236}
21237
21238bool isSKINIT(unsigned Opcode) {
21239 return Opcode == SKINIT;
21240}
21241
21242bool isENTER(unsigned Opcode) {
21243 return Opcode == ENTER;
21244}
21245
21246bool isVCVTSI2SS(unsigned Opcode) {
21247 switch (Opcode) {
21248 case VCVTSI2SSZrm_Int:
21249 case VCVTSI2SSZrr_Int:
21250 case VCVTSI2SSZrrb_Int:
21251 case VCVTSI2SSrm_Int:
21252 case VCVTSI2SSrr_Int:
21253 case VCVTSI642SSZrm_Int:
21254 case VCVTSI642SSZrr_Int:
21255 case VCVTSI642SSZrrb_Int:
21256 case VCVTSI642SSrm_Int:
21257 case VCVTSI642SSrr_Int:
21258 return true;
21259 }
21260 return false;
21261}
21262
21263bool isVFMADD231PD(unsigned Opcode) {
21264 switch (Opcode) {
21265 case VFMADD231PDYm:
21266 case VFMADD231PDYr:
21267 case VFMADD231PDZ128m:
21268 case VFMADD231PDZ128mb:
21269 case VFMADD231PDZ128mbk:
21270 case VFMADD231PDZ128mbkz:
21271 case VFMADD231PDZ128mk:
21272 case VFMADD231PDZ128mkz:
21273 case VFMADD231PDZ128r:
21274 case VFMADD231PDZ128rk:
21275 case VFMADD231PDZ128rkz:
21276 case VFMADD231PDZ256m:
21277 case VFMADD231PDZ256mb:
21278 case VFMADD231PDZ256mbk:
21279 case VFMADD231PDZ256mbkz:
21280 case VFMADD231PDZ256mk:
21281 case VFMADD231PDZ256mkz:
21282 case VFMADD231PDZ256r:
21283 case VFMADD231PDZ256rk:
21284 case VFMADD231PDZ256rkz:
21285 case VFMADD231PDZm:
21286 case VFMADD231PDZmb:
21287 case VFMADD231PDZmbk:
21288 case VFMADD231PDZmbkz:
21289 case VFMADD231PDZmk:
21290 case VFMADD231PDZmkz:
21291 case VFMADD231PDZr:
21292 case VFMADD231PDZrb:
21293 case VFMADD231PDZrbk:
21294 case VFMADD231PDZrbkz:
21295 case VFMADD231PDZrk:
21296 case VFMADD231PDZrkz:
21297 case VFMADD231PDm:
21298 case VFMADD231PDr:
21299 return true;
21300 }
21301 return false;
21302}
21303
21304bool isLOADIWKEY(unsigned Opcode) {
21305 return Opcode == LOADIWKEY;
21306}
21307
21308bool isVMOVNTDQA(unsigned Opcode) {
21309 switch (Opcode) {
21310 case VMOVNTDQAYrm:
21311 case VMOVNTDQAZ128rm:
21312 case VMOVNTDQAZ256rm:
21313 case VMOVNTDQAZrm:
21314 case VMOVNTDQArm:
21315 return true;
21316 }
21317 return false;
21318}
21319
21320bool isVPERMT2PS(unsigned Opcode) {
21321 switch (Opcode) {
21322 case VPERMT2PSZ128rm:
21323 case VPERMT2PSZ128rmb:
21324 case VPERMT2PSZ128rmbk:
21325 case VPERMT2PSZ128rmbkz:
21326 case VPERMT2PSZ128rmk:
21327 case VPERMT2PSZ128rmkz:
21328 case VPERMT2PSZ128rr:
21329 case VPERMT2PSZ128rrk:
21330 case VPERMT2PSZ128rrkz:
21331 case VPERMT2PSZ256rm:
21332 case VPERMT2PSZ256rmb:
21333 case VPERMT2PSZ256rmbk:
21334 case VPERMT2PSZ256rmbkz:
21335 case VPERMT2PSZ256rmk:
21336 case VPERMT2PSZ256rmkz:
21337 case VPERMT2PSZ256rr:
21338 case VPERMT2PSZ256rrk:
21339 case VPERMT2PSZ256rrkz:
21340 case VPERMT2PSZrm:
21341 case VPERMT2PSZrmb:
21342 case VPERMT2PSZrmbk:
21343 case VPERMT2PSZrmbkz:
21344 case VPERMT2PSZrmk:
21345 case VPERMT2PSZrmkz:
21346 case VPERMT2PSZrr:
21347 case VPERMT2PSZrrk:
21348 case VPERMT2PSZrrkz:
21349 return true;
21350 }
21351 return false;
21352}
21353
21354bool isPUSHF(unsigned Opcode) {
21355 return Opcode == PUSHF16;
21356}
21357
21358bool isMPSADBW(unsigned Opcode) {
21359 switch (Opcode) {
21360 case MPSADBWrmi:
21361 case MPSADBWrri:
21362 return true;
21363 }
21364 return false;
21365}
21366
21367bool isVMINMAXSH(unsigned Opcode) {
21368 switch (Opcode) {
21369 case VMINMAXSHrmi_Int:
21370 case VMINMAXSHrmik_Int:
21371 case VMINMAXSHrmikz_Int:
21372 case VMINMAXSHrri_Int:
21373 case VMINMAXSHrrib_Int:
21374 case VMINMAXSHrribk_Int:
21375 case VMINMAXSHrribkz_Int:
21376 case VMINMAXSHrrik_Int:
21377 case VMINMAXSHrrikz_Int:
21378 return true;
21379 }
21380 return false;
21381}
21382
21383bool isVRSQRT14SS(unsigned Opcode) {
21384 switch (Opcode) {
21385 case VRSQRT14SSZrm:
21386 case VRSQRT14SSZrmk:
21387 case VRSQRT14SSZrmkz:
21388 case VRSQRT14SSZrr:
21389 case VRSQRT14SSZrrk:
21390 case VRSQRT14SSZrrkz:
21391 return true;
21392 }
21393 return false;
21394}
21395
21396bool isVCVTDQ2PD(unsigned Opcode) {
21397 switch (Opcode) {
21398 case VCVTDQ2PDYrm:
21399 case VCVTDQ2PDYrr:
21400 case VCVTDQ2PDZ128rm:
21401 case VCVTDQ2PDZ128rmb:
21402 case VCVTDQ2PDZ128rmbk:
21403 case VCVTDQ2PDZ128rmbkz:
21404 case VCVTDQ2PDZ128rmk:
21405 case VCVTDQ2PDZ128rmkz:
21406 case VCVTDQ2PDZ128rr:
21407 case VCVTDQ2PDZ128rrk:
21408 case VCVTDQ2PDZ128rrkz:
21409 case VCVTDQ2PDZ256rm:
21410 case VCVTDQ2PDZ256rmb:
21411 case VCVTDQ2PDZ256rmbk:
21412 case VCVTDQ2PDZ256rmbkz:
21413 case VCVTDQ2PDZ256rmk:
21414 case VCVTDQ2PDZ256rmkz:
21415 case VCVTDQ2PDZ256rr:
21416 case VCVTDQ2PDZ256rrk:
21417 case VCVTDQ2PDZ256rrkz:
21418 case VCVTDQ2PDZrm:
21419 case VCVTDQ2PDZrmb:
21420 case VCVTDQ2PDZrmbk:
21421 case VCVTDQ2PDZrmbkz:
21422 case VCVTDQ2PDZrmk:
21423 case VCVTDQ2PDZrmkz:
21424 case VCVTDQ2PDZrr:
21425 case VCVTDQ2PDZrrk:
21426 case VCVTDQ2PDZrrkz:
21427 case VCVTDQ2PDrm:
21428 case VCVTDQ2PDrr:
21429 return true;
21430 }
21431 return false;
21432}
21433
21434bool isVORPS(unsigned Opcode) {
21435 switch (Opcode) {
21436 case VORPSYrm:
21437 case VORPSYrr:
21438 case VORPSZ128rm:
21439 case VORPSZ128rmb:
21440 case VORPSZ128rmbk:
21441 case VORPSZ128rmbkz:
21442 case VORPSZ128rmk:
21443 case VORPSZ128rmkz:
21444 case VORPSZ128rr:
21445 case VORPSZ128rrk:
21446 case VORPSZ128rrkz:
21447 case VORPSZ256rm:
21448 case VORPSZ256rmb:
21449 case VORPSZ256rmbk:
21450 case VORPSZ256rmbkz:
21451 case VORPSZ256rmk:
21452 case VORPSZ256rmkz:
21453 case VORPSZ256rr:
21454 case VORPSZ256rrk:
21455 case VORPSZ256rrkz:
21456 case VORPSZrm:
21457 case VORPSZrmb:
21458 case VORPSZrmbk:
21459 case VORPSZrmbkz:
21460 case VORPSZrmk:
21461 case VORPSZrmkz:
21462 case VORPSZrr:
21463 case VORPSZrrk:
21464 case VORPSZrrkz:
21465 case VORPSrm:
21466 case VORPSrr:
21467 return true;
21468 }
21469 return false;
21470}
21471
21472bool isVPEXPANDQ(unsigned Opcode) {
21473 switch (Opcode) {
21474 case VPEXPANDQZ128rm:
21475 case VPEXPANDQZ128rmk:
21476 case VPEXPANDQZ128rmkz:
21477 case VPEXPANDQZ128rr:
21478 case VPEXPANDQZ128rrk:
21479 case VPEXPANDQZ128rrkz:
21480 case VPEXPANDQZ256rm:
21481 case VPEXPANDQZ256rmk:
21482 case VPEXPANDQZ256rmkz:
21483 case VPEXPANDQZ256rr:
21484 case VPEXPANDQZ256rrk:
21485 case VPEXPANDQZ256rrkz:
21486 case VPEXPANDQZrm:
21487 case VPEXPANDQZrmk:
21488 case VPEXPANDQZrmkz:
21489 case VPEXPANDQZrr:
21490 case VPEXPANDQZrrk:
21491 case VPEXPANDQZrrkz:
21492 return true;
21493 }
21494 return false;
21495}
21496
21497bool isVPSHRDD(unsigned Opcode) {
21498 switch (Opcode) {
21499 case VPSHRDDZ128rmbi:
21500 case VPSHRDDZ128rmbik:
21501 case VPSHRDDZ128rmbikz:
21502 case VPSHRDDZ128rmi:
21503 case VPSHRDDZ128rmik:
21504 case VPSHRDDZ128rmikz:
21505 case VPSHRDDZ128rri:
21506 case VPSHRDDZ128rrik:
21507 case VPSHRDDZ128rrikz:
21508 case VPSHRDDZ256rmbi:
21509 case VPSHRDDZ256rmbik:
21510 case VPSHRDDZ256rmbikz:
21511 case VPSHRDDZ256rmi:
21512 case VPSHRDDZ256rmik:
21513 case VPSHRDDZ256rmikz:
21514 case VPSHRDDZ256rri:
21515 case VPSHRDDZ256rrik:
21516 case VPSHRDDZ256rrikz:
21517 case VPSHRDDZrmbi:
21518 case VPSHRDDZrmbik:
21519 case VPSHRDDZrmbikz:
21520 case VPSHRDDZrmi:
21521 case VPSHRDDZrmik:
21522 case VPSHRDDZrmikz:
21523 case VPSHRDDZrri:
21524 case VPSHRDDZrrik:
21525 case VPSHRDDZrrikz:
21526 return true;
21527 }
21528 return false;
21529}
21530
21531bool isTDPBSSD(unsigned Opcode) {
21532 return Opcode == TDPBSSD;
21533}
21534
21535bool isTESTUI(unsigned Opcode) {
21536 return Opcode == TESTUI;
21537}
21538
21539bool isVFMADDPD(unsigned Opcode) {
21540 switch (Opcode) {
21541 case VFMADDPD4Ymr:
21542 case VFMADDPD4Yrm:
21543 case VFMADDPD4Yrr:
21544 case VFMADDPD4Yrr_REV:
21545 case VFMADDPD4mr:
21546 case VFMADDPD4rm:
21547 case VFMADDPD4rr:
21548 case VFMADDPD4rr_REV:
21549 return true;
21550 }
21551 return false;
21552}
21553
21554bool isVPANDND(unsigned Opcode) {
21555 switch (Opcode) {
21556 case VPANDNDZ128rm:
21557 case VPANDNDZ128rmb:
21558 case VPANDNDZ128rmbk:
21559 case VPANDNDZ128rmbkz:
21560 case VPANDNDZ128rmk:
21561 case VPANDNDZ128rmkz:
21562 case VPANDNDZ128rr:
21563 case VPANDNDZ128rrk:
21564 case VPANDNDZ128rrkz:
21565 case VPANDNDZ256rm:
21566 case VPANDNDZ256rmb:
21567 case VPANDNDZ256rmbk:
21568 case VPANDNDZ256rmbkz:
21569 case VPANDNDZ256rmk:
21570 case VPANDNDZ256rmkz:
21571 case VPANDNDZ256rr:
21572 case VPANDNDZ256rrk:
21573 case VPANDNDZ256rrkz:
21574 case VPANDNDZrm:
21575 case VPANDNDZrmb:
21576 case VPANDNDZrmbk:
21577 case VPANDNDZrmbkz:
21578 case VPANDNDZrmk:
21579 case VPANDNDZrmkz:
21580 case VPANDNDZrr:
21581 case VPANDNDZrrk:
21582 case VPANDNDZrrkz:
21583 return true;
21584 }
21585 return false;
21586}
21587
21588bool isVPMOVSDB(unsigned Opcode) {
21589 switch (Opcode) {
21590 case VPMOVSDBZ128mr:
21591 case VPMOVSDBZ128mrk:
21592 case VPMOVSDBZ128rr:
21593 case VPMOVSDBZ128rrk:
21594 case VPMOVSDBZ128rrkz:
21595 case VPMOVSDBZ256mr:
21596 case VPMOVSDBZ256mrk:
21597 case VPMOVSDBZ256rr:
21598 case VPMOVSDBZ256rrk:
21599 case VPMOVSDBZ256rrkz:
21600 case VPMOVSDBZmr:
21601 case VPMOVSDBZmrk:
21602 case VPMOVSDBZrr:
21603 case VPMOVSDBZrrk:
21604 case VPMOVSDBZrrkz:
21605 return true;
21606 }
21607 return false;
21608}
21609
21610bool isVPBROADCASTB(unsigned Opcode) {
21611 switch (Opcode) {
21612 case VPBROADCASTBYrm:
21613 case VPBROADCASTBYrr:
21614 case VPBROADCASTBZ128rm:
21615 case VPBROADCASTBZ128rmk:
21616 case VPBROADCASTBZ128rmkz:
21617 case VPBROADCASTBZ128rr:
21618 case VPBROADCASTBZ128rrk:
21619 case VPBROADCASTBZ128rrkz:
21620 case VPBROADCASTBZ256rm:
21621 case VPBROADCASTBZ256rmk:
21622 case VPBROADCASTBZ256rmkz:
21623 case VPBROADCASTBZ256rr:
21624 case VPBROADCASTBZ256rrk:
21625 case VPBROADCASTBZ256rrkz:
21626 case VPBROADCASTBZrm:
21627 case VPBROADCASTBZrmk:
21628 case VPBROADCASTBZrmkz:
21629 case VPBROADCASTBZrr:
21630 case VPBROADCASTBZrrk:
21631 case VPBROADCASTBZrrkz:
21632 case VPBROADCASTBrZ128rr:
21633 case VPBROADCASTBrZ128rrk:
21634 case VPBROADCASTBrZ128rrkz:
21635 case VPBROADCASTBrZ256rr:
21636 case VPBROADCASTBrZ256rrk:
21637 case VPBROADCASTBrZ256rrkz:
21638 case VPBROADCASTBrZrr:
21639 case VPBROADCASTBrZrrk:
21640 case VPBROADCASTBrZrrkz:
21641 case VPBROADCASTBrm:
21642 case VPBROADCASTBrr:
21643 return true;
21644 }
21645 return false;
21646}
21647
21648bool isCVTPI2PD(unsigned Opcode) {
21649 switch (Opcode) {
21650 case MMX_CVTPI2PDrm:
21651 case MMX_CVTPI2PDrr:
21652 return true;
21653 }
21654 return false;
21655}
21656
21657bool isVPERMI2B(unsigned Opcode) {
21658 switch (Opcode) {
21659 case VPERMI2BZ128rm:
21660 case VPERMI2BZ128rmk:
21661 case VPERMI2BZ128rmkz:
21662 case VPERMI2BZ128rr:
21663 case VPERMI2BZ128rrk:
21664 case VPERMI2BZ128rrkz:
21665 case VPERMI2BZ256rm:
21666 case VPERMI2BZ256rmk:
21667 case VPERMI2BZ256rmkz:
21668 case VPERMI2BZ256rr:
21669 case VPERMI2BZ256rrk:
21670 case VPERMI2BZ256rrkz:
21671 case VPERMI2BZrm:
21672 case VPERMI2BZrmk:
21673 case VPERMI2BZrmkz:
21674 case VPERMI2BZrr:
21675 case VPERMI2BZrrk:
21676 case VPERMI2BZrrkz:
21677 return true;
21678 }
21679 return false;
21680}
21681
21682bool isVPMINSB(unsigned Opcode) {
21683 switch (Opcode) {
21684 case VPMINSBYrm:
21685 case VPMINSBYrr:
21686 case VPMINSBZ128rm:
21687 case VPMINSBZ128rmk:
21688 case VPMINSBZ128rmkz:
21689 case VPMINSBZ128rr:
21690 case VPMINSBZ128rrk:
21691 case VPMINSBZ128rrkz:
21692 case VPMINSBZ256rm:
21693 case VPMINSBZ256rmk:
21694 case VPMINSBZ256rmkz:
21695 case VPMINSBZ256rr:
21696 case VPMINSBZ256rrk:
21697 case VPMINSBZ256rrkz:
21698 case VPMINSBZrm:
21699 case VPMINSBZrmk:
21700 case VPMINSBZrmkz:
21701 case VPMINSBZrr:
21702 case VPMINSBZrrk:
21703 case VPMINSBZrrkz:
21704 case VPMINSBrm:
21705 case VPMINSBrr:
21706 return true;
21707 }
21708 return false;
21709}
21710
21711bool isLAR(unsigned Opcode) {
21712 switch (Opcode) {
21713 case LAR16rm:
21714 case LAR16rr:
21715 case LAR32rm:
21716 case LAR32rr:
21717 case LAR64rm:
21718 case LAR64rr:
21719 return true;
21720 }
21721 return false;
21722}
21723
21724bool isINVLPGB(unsigned Opcode) {
21725 switch (Opcode) {
21726 case INVLPGB32:
21727 case INVLPGB64:
21728 return true;
21729 }
21730 return false;
21731}
21732
21733bool isTLBSYNC(unsigned Opcode) {
21734 return Opcode == TLBSYNC;
21735}
21736
21737bool isFDIVP(unsigned Opcode) {
21738 return Opcode == DIV_FPrST0;
21739}
21740
21741bool isVPSRLW(unsigned Opcode) {
21742 switch (Opcode) {
21743 case VPSRLWYri:
21744 case VPSRLWYrm:
21745 case VPSRLWYrr:
21746 case VPSRLWZ128mi:
21747 case VPSRLWZ128mik:
21748 case VPSRLWZ128mikz:
21749 case VPSRLWZ128ri:
21750 case VPSRLWZ128rik:
21751 case VPSRLWZ128rikz:
21752 case VPSRLWZ128rm:
21753 case VPSRLWZ128rmk:
21754 case VPSRLWZ128rmkz:
21755 case VPSRLWZ128rr:
21756 case VPSRLWZ128rrk:
21757 case VPSRLWZ128rrkz:
21758 case VPSRLWZ256mi:
21759 case VPSRLWZ256mik:
21760 case VPSRLWZ256mikz:
21761 case VPSRLWZ256ri:
21762 case VPSRLWZ256rik:
21763 case VPSRLWZ256rikz:
21764 case VPSRLWZ256rm:
21765 case VPSRLWZ256rmk:
21766 case VPSRLWZ256rmkz:
21767 case VPSRLWZ256rr:
21768 case VPSRLWZ256rrk:
21769 case VPSRLWZ256rrkz:
21770 case VPSRLWZmi:
21771 case VPSRLWZmik:
21772 case VPSRLWZmikz:
21773 case VPSRLWZri:
21774 case VPSRLWZrik:
21775 case VPSRLWZrikz:
21776 case VPSRLWZrm:
21777 case VPSRLWZrmk:
21778 case VPSRLWZrmkz:
21779 case VPSRLWZrr:
21780 case VPSRLWZrrk:
21781 case VPSRLWZrrkz:
21782 case VPSRLWri:
21783 case VPSRLWrm:
21784 case VPSRLWrr:
21785 return true;
21786 }
21787 return false;
21788}
21789
21790bool isVRCP28SS(unsigned Opcode) {
21791 switch (Opcode) {
21792 case VRCP28SSZm:
21793 case VRCP28SSZmk:
21794 case VRCP28SSZmkz:
21795 case VRCP28SSZr:
21796 case VRCP28SSZrb:
21797 case VRCP28SSZrbk:
21798 case VRCP28SSZrbkz:
21799 case VRCP28SSZrk:
21800 case VRCP28SSZrkz:
21801 return true;
21802 }
21803 return false;
21804}
21805
21806bool isVMOVHPS(unsigned Opcode) {
21807 switch (Opcode) {
21808 case VMOVHPSZ128mr:
21809 case VMOVHPSZ128rm:
21810 case VMOVHPSmr:
21811 case VMOVHPSrm:
21812 return true;
21813 }
21814 return false;
21815}
21816
21817bool isVPMACSSDD(unsigned Opcode) {
21818 switch (Opcode) {
21819 case VPMACSSDDrm:
21820 case VPMACSSDDrr:
21821 return true;
21822 }
21823 return false;
21824}
21825
21826bool isPEXT(unsigned Opcode) {
21827 switch (Opcode) {
21828 case PEXT32rm:
21829 case PEXT32rm_EVEX:
21830 case PEXT32rr:
21831 case PEXT32rr_EVEX:
21832 case PEXT64rm:
21833 case PEXT64rm_EVEX:
21834 case PEXT64rr:
21835 case PEXT64rr_EVEX:
21836 return true;
21837 }
21838 return false;
21839}
21840
21841bool isVMAXBF16(unsigned Opcode) {
21842 switch (Opcode) {
21843 case VMAXBF16Z128rm:
21844 case VMAXBF16Z128rmb:
21845 case VMAXBF16Z128rmbk:
21846 case VMAXBF16Z128rmbkz:
21847 case VMAXBF16Z128rmk:
21848 case VMAXBF16Z128rmkz:
21849 case VMAXBF16Z128rr:
21850 case VMAXBF16Z128rrk:
21851 case VMAXBF16Z128rrkz:
21852 case VMAXBF16Z256rm:
21853 case VMAXBF16Z256rmb:
21854 case VMAXBF16Z256rmbk:
21855 case VMAXBF16Z256rmbkz:
21856 case VMAXBF16Z256rmk:
21857 case VMAXBF16Z256rmkz:
21858 case VMAXBF16Z256rr:
21859 case VMAXBF16Z256rrk:
21860 case VMAXBF16Z256rrkz:
21861 case VMAXBF16Zrm:
21862 case VMAXBF16Zrmb:
21863 case VMAXBF16Zrmbk:
21864 case VMAXBF16Zrmbkz:
21865 case VMAXBF16Zrmk:
21866 case VMAXBF16Zrmkz:
21867 case VMAXBF16Zrr:
21868 case VMAXBF16Zrrk:
21869 case VMAXBF16Zrrkz:
21870 return true;
21871 }
21872 return false;
21873}
21874
21875bool isVRSQRT14SD(unsigned Opcode) {
21876 switch (Opcode) {
21877 case VRSQRT14SDZrm:
21878 case VRSQRT14SDZrmk:
21879 case VRSQRT14SDZrmkz:
21880 case VRSQRT14SDZrr:
21881 case VRSQRT14SDZrrk:
21882 case VRSQRT14SDZrrkz:
21883 return true;
21884 }
21885 return false;
21886}
21887
21888bool isVPDPWSSD(unsigned Opcode) {
21889 switch (Opcode) {
21890 case VPDPWSSDYrm:
21891 case VPDPWSSDYrr:
21892 case VPDPWSSDZ128rm:
21893 case VPDPWSSDZ128rmb:
21894 case VPDPWSSDZ128rmbk:
21895 case VPDPWSSDZ128rmbkz:
21896 case VPDPWSSDZ128rmk:
21897 case VPDPWSSDZ128rmkz:
21898 case VPDPWSSDZ128rr:
21899 case VPDPWSSDZ128rrk:
21900 case VPDPWSSDZ128rrkz:
21901 case VPDPWSSDZ256rm:
21902 case VPDPWSSDZ256rmb:
21903 case VPDPWSSDZ256rmbk:
21904 case VPDPWSSDZ256rmbkz:
21905 case VPDPWSSDZ256rmk:
21906 case VPDPWSSDZ256rmkz:
21907 case VPDPWSSDZ256rr:
21908 case VPDPWSSDZ256rrk:
21909 case VPDPWSSDZ256rrkz:
21910 case VPDPWSSDZrm:
21911 case VPDPWSSDZrmb:
21912 case VPDPWSSDZrmbk:
21913 case VPDPWSSDZrmbkz:
21914 case VPDPWSSDZrmk:
21915 case VPDPWSSDZrmkz:
21916 case VPDPWSSDZrr:
21917 case VPDPWSSDZrrk:
21918 case VPDPWSSDZrrkz:
21919 case VPDPWSSDrm:
21920 case VPDPWSSDrr:
21921 return true;
21922 }
21923 return false;
21924}
21925
21926bool isVFMSUB231SD(unsigned Opcode) {
21927 switch (Opcode) {
21928 case VFMSUB231SDZm_Int:
21929 case VFMSUB231SDZmk_Int:
21930 case VFMSUB231SDZmkz_Int:
21931 case VFMSUB231SDZr_Int:
21932 case VFMSUB231SDZrb_Int:
21933 case VFMSUB231SDZrbk_Int:
21934 case VFMSUB231SDZrbkz_Int:
21935 case VFMSUB231SDZrk_Int:
21936 case VFMSUB231SDZrkz_Int:
21937 case VFMSUB231SDm_Int:
21938 case VFMSUB231SDr_Int:
21939 return true;
21940 }
21941 return false;
21942}
21943
21944bool isVPMOVZXWQ(unsigned Opcode) {
21945 switch (Opcode) {
21946 case VPMOVZXWQYrm:
21947 case VPMOVZXWQYrr:
21948 case VPMOVZXWQZ128rm:
21949 case VPMOVZXWQZ128rmk:
21950 case VPMOVZXWQZ128rmkz:
21951 case VPMOVZXWQZ128rr:
21952 case VPMOVZXWQZ128rrk:
21953 case VPMOVZXWQZ128rrkz:
21954 case VPMOVZXWQZ256rm:
21955 case VPMOVZXWQZ256rmk:
21956 case VPMOVZXWQZ256rmkz:
21957 case VPMOVZXWQZ256rr:
21958 case VPMOVZXWQZ256rrk:
21959 case VPMOVZXWQZ256rrkz:
21960 case VPMOVZXWQZrm:
21961 case VPMOVZXWQZrmk:
21962 case VPMOVZXWQZrmkz:
21963 case VPMOVZXWQZrr:
21964 case VPMOVZXWQZrrk:
21965 case VPMOVZXWQZrrkz:
21966 case VPMOVZXWQrm:
21967 case VPMOVZXWQrr:
21968 return true;
21969 }
21970 return false;
21971}
21972
21973bool isXORPD(unsigned Opcode) {
21974 switch (Opcode) {
21975 case XORPDrm:
21976 case XORPDrr:
21977 return true;
21978 }
21979 return false;
21980}
21981
21982bool isVMOVDQA(unsigned Opcode) {
21983 switch (Opcode) {
21984 case VMOVDQAYmr:
21985 case VMOVDQAYrm:
21986 case VMOVDQAYrr:
21987 case VMOVDQAYrr_REV:
21988 case VMOVDQAmr:
21989 case VMOVDQArm:
21990 case VMOVDQArr:
21991 case VMOVDQArr_REV:
21992 return true;
21993 }
21994 return false;
21995}
21996
21997bool isVFNMSUB213SD(unsigned Opcode) {
21998 switch (Opcode) {
21999 case VFNMSUB213SDZm_Int:
22000 case VFNMSUB213SDZmk_Int:
22001 case VFNMSUB213SDZmkz_Int:
22002 case VFNMSUB213SDZr_Int:
22003 case VFNMSUB213SDZrb_Int:
22004 case VFNMSUB213SDZrbk_Int:
22005 case VFNMSUB213SDZrbkz_Int:
22006 case VFNMSUB213SDZrk_Int:
22007 case VFNMSUB213SDZrkz_Int:
22008 case VFNMSUB213SDm_Int:
22009 case VFNMSUB213SDr_Int:
22010 return true;
22011 }
22012 return false;
22013}
22014
22015bool isVMINPS(unsigned Opcode) {
22016 switch (Opcode) {
22017 case VMINPSYrm:
22018 case VMINPSYrr:
22019 case VMINPSZ128rm:
22020 case VMINPSZ128rmb:
22021 case VMINPSZ128rmbk:
22022 case VMINPSZ128rmbkz:
22023 case VMINPSZ128rmk:
22024 case VMINPSZ128rmkz:
22025 case VMINPSZ128rr:
22026 case VMINPSZ128rrk:
22027 case VMINPSZ128rrkz:
22028 case VMINPSZ256rm:
22029 case VMINPSZ256rmb:
22030 case VMINPSZ256rmbk:
22031 case VMINPSZ256rmbkz:
22032 case VMINPSZ256rmk:
22033 case VMINPSZ256rmkz:
22034 case VMINPSZ256rr:
22035 case VMINPSZ256rrk:
22036 case VMINPSZ256rrkz:
22037 case VMINPSZrm:
22038 case VMINPSZrmb:
22039 case VMINPSZrmbk:
22040 case VMINPSZrmbkz:
22041 case VMINPSZrmk:
22042 case VMINPSZrmkz:
22043 case VMINPSZrr:
22044 case VMINPSZrrb:
22045 case VMINPSZrrbk:
22046 case VMINPSZrrbkz:
22047 case VMINPSZrrk:
22048 case VMINPSZrrkz:
22049 case VMINPSrm:
22050 case VMINPSrr:
22051 return true;
22052 }
22053 return false;
22054}
22055
22056bool isVFMSUB231PS(unsigned Opcode) {
22057 switch (Opcode) {
22058 case VFMSUB231PSYm:
22059 case VFMSUB231PSYr:
22060 case VFMSUB231PSZ128m:
22061 case VFMSUB231PSZ128mb:
22062 case VFMSUB231PSZ128mbk:
22063 case VFMSUB231PSZ128mbkz:
22064 case VFMSUB231PSZ128mk:
22065 case VFMSUB231PSZ128mkz:
22066 case VFMSUB231PSZ128r:
22067 case VFMSUB231PSZ128rk:
22068 case VFMSUB231PSZ128rkz:
22069 case VFMSUB231PSZ256m:
22070 case VFMSUB231PSZ256mb:
22071 case VFMSUB231PSZ256mbk:
22072 case VFMSUB231PSZ256mbkz:
22073 case VFMSUB231PSZ256mk:
22074 case VFMSUB231PSZ256mkz:
22075 case VFMSUB231PSZ256r:
22076 case VFMSUB231PSZ256rk:
22077 case VFMSUB231PSZ256rkz:
22078 case VFMSUB231PSZm:
22079 case VFMSUB231PSZmb:
22080 case VFMSUB231PSZmbk:
22081 case VFMSUB231PSZmbkz:
22082 case VFMSUB231PSZmk:
22083 case VFMSUB231PSZmkz:
22084 case VFMSUB231PSZr:
22085 case VFMSUB231PSZrb:
22086 case VFMSUB231PSZrbk:
22087 case VFMSUB231PSZrbkz:
22088 case VFMSUB231PSZrk:
22089 case VFMSUB231PSZrkz:
22090 case VFMSUB231PSm:
22091 case VFMSUB231PSr:
22092 return true;
22093 }
22094 return false;
22095}
22096
22097bool isVPCOMPRESSB(unsigned Opcode) {
22098 switch (Opcode) {
22099 case VPCOMPRESSBZ128mr:
22100 case VPCOMPRESSBZ128mrk:
22101 case VPCOMPRESSBZ128rr:
22102 case VPCOMPRESSBZ128rrk:
22103 case VPCOMPRESSBZ128rrkz:
22104 case VPCOMPRESSBZ256mr:
22105 case VPCOMPRESSBZ256mrk:
22106 case VPCOMPRESSBZ256rr:
22107 case VPCOMPRESSBZ256rrk:
22108 case VPCOMPRESSBZ256rrkz:
22109 case VPCOMPRESSBZmr:
22110 case VPCOMPRESSBZmrk:
22111 case VPCOMPRESSBZrr:
22112 case VPCOMPRESSBZrrk:
22113 case VPCOMPRESSBZrrkz:
22114 return true;
22115 }
22116 return false;
22117}
22118
22119bool isVPCMPEQQ(unsigned Opcode) {
22120 switch (Opcode) {
22121 case VPCMPEQQYrm:
22122 case VPCMPEQQYrr:
22123 case VPCMPEQQZ128rm:
22124 case VPCMPEQQZ128rmb:
22125 case VPCMPEQQZ128rmbk:
22126 case VPCMPEQQZ128rmk:
22127 case VPCMPEQQZ128rr:
22128 case VPCMPEQQZ128rrk:
22129 case VPCMPEQQZ256rm:
22130 case VPCMPEQQZ256rmb:
22131 case VPCMPEQQZ256rmbk:
22132 case VPCMPEQQZ256rmk:
22133 case VPCMPEQQZ256rr:
22134 case VPCMPEQQZ256rrk:
22135 case VPCMPEQQZrm:
22136 case VPCMPEQQZrmb:
22137 case VPCMPEQQZrmbk:
22138 case VPCMPEQQZrmk:
22139 case VPCMPEQQZrr:
22140 case VPCMPEQQZrrk:
22141 case VPCMPEQQrm:
22142 case VPCMPEQQrr:
22143 return true;
22144 }
22145 return false;
22146}
22147
22148bool isVRCPSS(unsigned Opcode) {
22149 switch (Opcode) {
22150 case VRCPSSm_Int:
22151 case VRCPSSr_Int:
22152 return true;
22153 }
22154 return false;
22155}
22156
22157bool isVSCATTERPF1DPS(unsigned Opcode) {
22158 return Opcode == VSCATTERPF1DPSm;
22159}
22160
22161bool isVPHADDUBW(unsigned Opcode) {
22162 switch (Opcode) {
22163 case VPHADDUBWrm:
22164 case VPHADDUBWrr:
22165 return true;
22166 }
22167 return false;
22168}
22169
22170bool isVSUBPD(unsigned Opcode) {
22171 switch (Opcode) {
22172 case VSUBPDYrm:
22173 case VSUBPDYrr:
22174 case VSUBPDZ128rm:
22175 case VSUBPDZ128rmb:
22176 case VSUBPDZ128rmbk:
22177 case VSUBPDZ128rmbkz:
22178 case VSUBPDZ128rmk:
22179 case VSUBPDZ128rmkz:
22180 case VSUBPDZ128rr:
22181 case VSUBPDZ128rrk:
22182 case VSUBPDZ128rrkz:
22183 case VSUBPDZ256rm:
22184 case VSUBPDZ256rmb:
22185 case VSUBPDZ256rmbk:
22186 case VSUBPDZ256rmbkz:
22187 case VSUBPDZ256rmk:
22188 case VSUBPDZ256rmkz:
22189 case VSUBPDZ256rr:
22190 case VSUBPDZ256rrk:
22191 case VSUBPDZ256rrkz:
22192 case VSUBPDZrm:
22193 case VSUBPDZrmb:
22194 case VSUBPDZrmbk:
22195 case VSUBPDZrmbkz:
22196 case VSUBPDZrmk:
22197 case VSUBPDZrmkz:
22198 case VSUBPDZrr:
22199 case VSUBPDZrrb:
22200 case VSUBPDZrrbk:
22201 case VSUBPDZrrbkz:
22202 case VSUBPDZrrk:
22203 case VSUBPDZrrkz:
22204 case VSUBPDrm:
22205 case VSUBPDrr:
22206 return true;
22207 }
22208 return false;
22209}
22210
22211bool isVPSCATTERQQ(unsigned Opcode) {
22212 switch (Opcode) {
22213 case VPSCATTERQQZ128mr:
22214 case VPSCATTERQQZ256mr:
22215 case VPSCATTERQQZmr:
22216 return true;
22217 }
22218 return false;
22219}
22220
22221bool isVCVTW2PH(unsigned Opcode) {
22222 switch (Opcode) {
22223 case VCVTW2PHZ128rm:
22224 case VCVTW2PHZ128rmb:
22225 case VCVTW2PHZ128rmbk:
22226 case VCVTW2PHZ128rmbkz:
22227 case VCVTW2PHZ128rmk:
22228 case VCVTW2PHZ128rmkz:
22229 case VCVTW2PHZ128rr:
22230 case VCVTW2PHZ128rrk:
22231 case VCVTW2PHZ128rrkz:
22232 case VCVTW2PHZ256rm:
22233 case VCVTW2PHZ256rmb:
22234 case VCVTW2PHZ256rmbk:
22235 case VCVTW2PHZ256rmbkz:
22236 case VCVTW2PHZ256rmk:
22237 case VCVTW2PHZ256rmkz:
22238 case VCVTW2PHZ256rr:
22239 case VCVTW2PHZ256rrk:
22240 case VCVTW2PHZ256rrkz:
22241 case VCVTW2PHZrm:
22242 case VCVTW2PHZrmb:
22243 case VCVTW2PHZrmbk:
22244 case VCVTW2PHZrmbkz:
22245 case VCVTW2PHZrmk:
22246 case VCVTW2PHZrmkz:
22247 case VCVTW2PHZrr:
22248 case VCVTW2PHZrrb:
22249 case VCVTW2PHZrrbk:
22250 case VCVTW2PHZrrbkz:
22251 case VCVTW2PHZrrk:
22252 case VCVTW2PHZrrkz:
22253 return true;
22254 }
22255 return false;
22256}
22257
22258bool isVFMADDCPH(unsigned Opcode) {
22259 switch (Opcode) {
22260 case VFMADDCPHZ128m:
22261 case VFMADDCPHZ128mb:
22262 case VFMADDCPHZ128mbk:
22263 case VFMADDCPHZ128mbkz:
22264 case VFMADDCPHZ128mk:
22265 case VFMADDCPHZ128mkz:
22266 case VFMADDCPHZ128r:
22267 case VFMADDCPHZ128rk:
22268 case VFMADDCPHZ128rkz:
22269 case VFMADDCPHZ256m:
22270 case VFMADDCPHZ256mb:
22271 case VFMADDCPHZ256mbk:
22272 case VFMADDCPHZ256mbkz:
22273 case VFMADDCPHZ256mk:
22274 case VFMADDCPHZ256mkz:
22275 case VFMADDCPHZ256r:
22276 case VFMADDCPHZ256rk:
22277 case VFMADDCPHZ256rkz:
22278 case VFMADDCPHZm:
22279 case VFMADDCPHZmb:
22280 case VFMADDCPHZmbk:
22281 case VFMADDCPHZmbkz:
22282 case VFMADDCPHZmk:
22283 case VFMADDCPHZmkz:
22284 case VFMADDCPHZr:
22285 case VFMADDCPHZrb:
22286 case VFMADDCPHZrbk:
22287 case VFMADDCPHZrbkz:
22288 case VFMADDCPHZrk:
22289 case VFMADDCPHZrkz:
22290 return true;
22291 }
22292 return false;
22293}
22294
22295bool isVPACKUSDW(unsigned Opcode) {
22296 switch (Opcode) {
22297 case VPACKUSDWYrm:
22298 case VPACKUSDWYrr:
22299 case VPACKUSDWZ128rm:
22300 case VPACKUSDWZ128rmb:
22301 case VPACKUSDWZ128rmbk:
22302 case VPACKUSDWZ128rmbkz:
22303 case VPACKUSDWZ128rmk:
22304 case VPACKUSDWZ128rmkz:
22305 case VPACKUSDWZ128rr:
22306 case VPACKUSDWZ128rrk:
22307 case VPACKUSDWZ128rrkz:
22308 case VPACKUSDWZ256rm:
22309 case VPACKUSDWZ256rmb:
22310 case VPACKUSDWZ256rmbk:
22311 case VPACKUSDWZ256rmbkz:
22312 case VPACKUSDWZ256rmk:
22313 case VPACKUSDWZ256rmkz:
22314 case VPACKUSDWZ256rr:
22315 case VPACKUSDWZ256rrk:
22316 case VPACKUSDWZ256rrkz:
22317 case VPACKUSDWZrm:
22318 case VPACKUSDWZrmb:
22319 case VPACKUSDWZrmbk:
22320 case VPACKUSDWZrmbkz:
22321 case VPACKUSDWZrmk:
22322 case VPACKUSDWZrmkz:
22323 case VPACKUSDWZrr:
22324 case VPACKUSDWZrrk:
22325 case VPACKUSDWZrrkz:
22326 case VPACKUSDWrm:
22327 case VPACKUSDWrr:
22328 return true;
22329 }
22330 return false;
22331}
22332
22333bool isVSCALEFSS(unsigned Opcode) {
22334 switch (Opcode) {
22335 case VSCALEFSSZrm:
22336 case VSCALEFSSZrmk:
22337 case VSCALEFSSZrmkz:
22338 case VSCALEFSSZrr:
22339 case VSCALEFSSZrrb_Int:
22340 case VSCALEFSSZrrbk_Int:
22341 case VSCALEFSSZrrbkz_Int:
22342 case VSCALEFSSZrrk:
22343 case VSCALEFSSZrrkz:
22344 return true;
22345 }
22346 return false;
22347}
22348
22349bool isAESIMC(unsigned Opcode) {
22350 switch (Opcode) {
22351 case AESIMCrm:
22352 case AESIMCrr:
22353 return true;
22354 }
22355 return false;
22356}
22357
22358bool isVRCP28PS(unsigned Opcode) {
22359 switch (Opcode) {
22360 case VRCP28PSZm:
22361 case VRCP28PSZmb:
22362 case VRCP28PSZmbk:
22363 case VRCP28PSZmbkz:
22364 case VRCP28PSZmk:
22365 case VRCP28PSZmkz:
22366 case VRCP28PSZr:
22367 case VRCP28PSZrb:
22368 case VRCP28PSZrbk:
22369 case VRCP28PSZrbkz:
22370 case VRCP28PSZrk:
22371 case VRCP28PSZrkz:
22372 return true;
22373 }
22374 return false;
22375}
22376
22377bool isAAND(unsigned Opcode) {
22378 switch (Opcode) {
22379 case AAND32mr:
22380 case AAND32mr_EVEX:
22381 case AAND64mr:
22382 case AAND64mr_EVEX:
22383 return true;
22384 }
22385 return false;
22386}
22387
22388bool isDAA(unsigned Opcode) {
22389 return Opcode == DAA;
22390}
22391
22392bool isKTESTW(unsigned Opcode) {
22393 return Opcode == KTESTWkk;
22394}
22395
22396bool isVCVTPD2UDQ(unsigned Opcode) {
22397 switch (Opcode) {
22398 case VCVTPD2UDQZ128rm:
22399 case VCVTPD2UDQZ128rmb:
22400 case VCVTPD2UDQZ128rmbk:
22401 case VCVTPD2UDQZ128rmbkz:
22402 case VCVTPD2UDQZ128rmk:
22403 case VCVTPD2UDQZ128rmkz:
22404 case VCVTPD2UDQZ128rr:
22405 case VCVTPD2UDQZ128rrk:
22406 case VCVTPD2UDQZ128rrkz:
22407 case VCVTPD2UDQZ256rm:
22408 case VCVTPD2UDQZ256rmb:
22409 case VCVTPD2UDQZ256rmbk:
22410 case VCVTPD2UDQZ256rmbkz:
22411 case VCVTPD2UDQZ256rmk:
22412 case VCVTPD2UDQZ256rmkz:
22413 case VCVTPD2UDQZ256rr:
22414 case VCVTPD2UDQZ256rrk:
22415 case VCVTPD2UDQZ256rrkz:
22416 case VCVTPD2UDQZrm:
22417 case VCVTPD2UDQZrmb:
22418 case VCVTPD2UDQZrmbk:
22419 case VCVTPD2UDQZrmbkz:
22420 case VCVTPD2UDQZrmk:
22421 case VCVTPD2UDQZrmkz:
22422 case VCVTPD2UDQZrr:
22423 case VCVTPD2UDQZrrb:
22424 case VCVTPD2UDQZrrbk:
22425 case VCVTPD2UDQZrrbkz:
22426 case VCVTPD2UDQZrrk:
22427 case VCVTPD2UDQZrrkz:
22428 return true;
22429 }
22430 return false;
22431}
22432
22433bool isVPADDQ(unsigned Opcode) {
22434 switch (Opcode) {
22435 case VPADDQYrm:
22436 case VPADDQYrr:
22437 case VPADDQZ128rm:
22438 case VPADDQZ128rmb:
22439 case VPADDQZ128rmbk:
22440 case VPADDQZ128rmbkz:
22441 case VPADDQZ128rmk:
22442 case VPADDQZ128rmkz:
22443 case VPADDQZ128rr:
22444 case VPADDQZ128rrk:
22445 case VPADDQZ128rrkz:
22446 case VPADDQZ256rm:
22447 case VPADDQZ256rmb:
22448 case VPADDQZ256rmbk:
22449 case VPADDQZ256rmbkz:
22450 case VPADDQZ256rmk:
22451 case VPADDQZ256rmkz:
22452 case VPADDQZ256rr:
22453 case VPADDQZ256rrk:
22454 case VPADDQZ256rrkz:
22455 case VPADDQZrm:
22456 case VPADDQZrmb:
22457 case VPADDQZrmbk:
22458 case VPADDQZrmbkz:
22459 case VPADDQZrmk:
22460 case VPADDQZrmkz:
22461 case VPADDQZrr:
22462 case VPADDQZrrk:
22463 case VPADDQZrrkz:
22464 case VPADDQrm:
22465 case VPADDQrr:
22466 return true;
22467 }
22468 return false;
22469}
22470
22471bool isPALIGNR(unsigned Opcode) {
22472 switch (Opcode) {
22473 case MMX_PALIGNRrmi:
22474 case MMX_PALIGNRrri:
22475 case PALIGNRrmi:
22476 case PALIGNRrri:
22477 return true;
22478 }
22479 return false;
22480}
22481
22482bool isPMAXUW(unsigned Opcode) {
22483 switch (Opcode) {
22484 case PMAXUWrm:
22485 case PMAXUWrr:
22486 return true;
22487 }
22488 return false;
22489}
22490
22491bool isVFMADDSD(unsigned Opcode) {
22492 switch (Opcode) {
22493 case VFMADDSD4mr:
22494 case VFMADDSD4rm:
22495 case VFMADDSD4rr:
22496 case VFMADDSD4rr_REV:
22497 return true;
22498 }
22499 return false;
22500}
22501
22502bool isPFMAX(unsigned Opcode) {
22503 switch (Opcode) {
22504 case PFMAXrm:
22505 case PFMAXrr:
22506 return true;
22507 }
22508 return false;
22509}
22510
22511bool isVPOR(unsigned Opcode) {
22512 switch (Opcode) {
22513 case VPORYrm:
22514 case VPORYrr:
22515 case VPORrm:
22516 case VPORrr:
22517 return true;
22518 }
22519 return false;
22520}
22521
22522bool isVPSUBB(unsigned Opcode) {
22523 switch (Opcode) {
22524 case VPSUBBYrm:
22525 case VPSUBBYrr:
22526 case VPSUBBZ128rm:
22527 case VPSUBBZ128rmk:
22528 case VPSUBBZ128rmkz:
22529 case VPSUBBZ128rr:
22530 case VPSUBBZ128rrk:
22531 case VPSUBBZ128rrkz:
22532 case VPSUBBZ256rm:
22533 case VPSUBBZ256rmk:
22534 case VPSUBBZ256rmkz:
22535 case VPSUBBZ256rr:
22536 case VPSUBBZ256rrk:
22537 case VPSUBBZ256rrkz:
22538 case VPSUBBZrm:
22539 case VPSUBBZrmk:
22540 case VPSUBBZrmkz:
22541 case VPSUBBZrr:
22542 case VPSUBBZrrk:
22543 case VPSUBBZrrkz:
22544 case VPSUBBrm:
22545 case VPSUBBrr:
22546 return true;
22547 }
22548 return false;
22549}
22550
22551bool isVPAVGB(unsigned Opcode) {
22552 switch (Opcode) {
22553 case VPAVGBYrm:
22554 case VPAVGBYrr:
22555 case VPAVGBZ128rm:
22556 case VPAVGBZ128rmk:
22557 case VPAVGBZ128rmkz:
22558 case VPAVGBZ128rr:
22559 case VPAVGBZ128rrk:
22560 case VPAVGBZ128rrkz:
22561 case VPAVGBZ256rm:
22562 case VPAVGBZ256rmk:
22563 case VPAVGBZ256rmkz:
22564 case VPAVGBZ256rr:
22565 case VPAVGBZ256rrk:
22566 case VPAVGBZ256rrkz:
22567 case VPAVGBZrm:
22568 case VPAVGBZrmk:
22569 case VPAVGBZrmkz:
22570 case VPAVGBZrr:
22571 case VPAVGBZrrk:
22572 case VPAVGBZrrkz:
22573 case VPAVGBrm:
22574 case VPAVGBrr:
22575 return true;
22576 }
22577 return false;
22578}
22579
22580bool isINSB(unsigned Opcode) {
22581 return Opcode == INSB;
22582}
22583
22584bool isFYL2X(unsigned Opcode) {
22585 return Opcode == FYL2X;
22586}
22587
22588bool isVFNMSUB132PD(unsigned Opcode) {
22589 switch (Opcode) {
22590 case VFNMSUB132PDYm:
22591 case VFNMSUB132PDYr:
22592 case VFNMSUB132PDZ128m:
22593 case VFNMSUB132PDZ128mb:
22594 case VFNMSUB132PDZ128mbk:
22595 case VFNMSUB132PDZ128mbkz:
22596 case VFNMSUB132PDZ128mk:
22597 case VFNMSUB132PDZ128mkz:
22598 case VFNMSUB132PDZ128r:
22599 case VFNMSUB132PDZ128rk:
22600 case VFNMSUB132PDZ128rkz:
22601 case VFNMSUB132PDZ256m:
22602 case VFNMSUB132PDZ256mb:
22603 case VFNMSUB132PDZ256mbk:
22604 case VFNMSUB132PDZ256mbkz:
22605 case VFNMSUB132PDZ256mk:
22606 case VFNMSUB132PDZ256mkz:
22607 case VFNMSUB132PDZ256r:
22608 case VFNMSUB132PDZ256rk:
22609 case VFNMSUB132PDZ256rkz:
22610 case VFNMSUB132PDZm:
22611 case VFNMSUB132PDZmb:
22612 case VFNMSUB132PDZmbk:
22613 case VFNMSUB132PDZmbkz:
22614 case VFNMSUB132PDZmk:
22615 case VFNMSUB132PDZmkz:
22616 case VFNMSUB132PDZr:
22617 case VFNMSUB132PDZrb:
22618 case VFNMSUB132PDZrbk:
22619 case VFNMSUB132PDZrbkz:
22620 case VFNMSUB132PDZrk:
22621 case VFNMSUB132PDZrkz:
22622 case VFNMSUB132PDm:
22623 case VFNMSUB132PDr:
22624 return true;
22625 }
22626 return false;
22627}
22628
22629bool isVFNMSUBPS(unsigned Opcode) {
22630 switch (Opcode) {
22631 case VFNMSUBPS4Ymr:
22632 case VFNMSUBPS4Yrm:
22633 case VFNMSUBPS4Yrr:
22634 case VFNMSUBPS4Yrr_REV:
22635 case VFNMSUBPS4mr:
22636 case VFNMSUBPS4rm:
22637 case VFNMSUBPS4rr:
22638 case VFNMSUBPS4rr_REV:
22639 return true;
22640 }
22641 return false;
22642}
22643
22644bool isVFMADD231PS(unsigned Opcode) {
22645 switch (Opcode) {
22646 case VFMADD231PSYm:
22647 case VFMADD231PSYr:
22648 case VFMADD231PSZ128m:
22649 case VFMADD231PSZ128mb:
22650 case VFMADD231PSZ128mbk:
22651 case VFMADD231PSZ128mbkz:
22652 case VFMADD231PSZ128mk:
22653 case VFMADD231PSZ128mkz:
22654 case VFMADD231PSZ128r:
22655 case VFMADD231PSZ128rk:
22656 case VFMADD231PSZ128rkz:
22657 case VFMADD231PSZ256m:
22658 case VFMADD231PSZ256mb:
22659 case VFMADD231PSZ256mbk:
22660 case VFMADD231PSZ256mbkz:
22661 case VFMADD231PSZ256mk:
22662 case VFMADD231PSZ256mkz:
22663 case VFMADD231PSZ256r:
22664 case VFMADD231PSZ256rk:
22665 case VFMADD231PSZ256rkz:
22666 case VFMADD231PSZm:
22667 case VFMADD231PSZmb:
22668 case VFMADD231PSZmbk:
22669 case VFMADD231PSZmbkz:
22670 case VFMADD231PSZmk:
22671 case VFMADD231PSZmkz:
22672 case VFMADD231PSZr:
22673 case VFMADD231PSZrb:
22674 case VFMADD231PSZrbk:
22675 case VFMADD231PSZrbkz:
22676 case VFMADD231PSZrk:
22677 case VFMADD231PSZrkz:
22678 case VFMADD231PSm:
22679 case VFMADD231PSr:
22680 return true;
22681 }
22682 return false;
22683}
22684
22685bool isVCVTTSS2SI(unsigned Opcode) {
22686 switch (Opcode) {
22687 case VCVTTSS2SI64Zrm_Int:
22688 case VCVTTSS2SI64Zrr_Int:
22689 case VCVTTSS2SI64Zrrb_Int:
22690 case VCVTTSS2SI64rm_Int:
22691 case VCVTTSS2SI64rr_Int:
22692 case VCVTTSS2SIZrm_Int:
22693 case VCVTTSS2SIZrr_Int:
22694 case VCVTTSS2SIZrrb_Int:
22695 case VCVTTSS2SIrm_Int:
22696 case VCVTTSS2SIrr_Int:
22697 return true;
22698 }
22699 return false;
22700}
22701
22702bool isTCMMRLFP16PS(unsigned Opcode) {
22703 return Opcode == TCMMRLFP16PS;
22704}
22705
22706bool isFCOMPP(unsigned Opcode) {
22707 return Opcode == FCOMPP;
22708}
22709
22710bool isMOVD(unsigned Opcode) {
22711 switch (Opcode) {
22712 case MMX_MOVD64grr:
22713 case MMX_MOVD64mr:
22714 case MMX_MOVD64rm:
22715 case MMX_MOVD64rr:
22716 case MOVDI2PDIrm:
22717 case MOVDI2PDIrr:
22718 case MOVPDI2DImr:
22719 case MOVPDI2DIrr:
22720 return true;
22721 }
22722 return false;
22723}
22724
22725bool isMOVBE(unsigned Opcode) {
22726 switch (Opcode) {
22727 case MOVBE16mr:
22728 case MOVBE16mr_EVEX:
22729 case MOVBE16rm:
22730 case MOVBE16rm_EVEX:
22731 case MOVBE16rr:
22732 case MOVBE16rr_REV:
22733 case MOVBE32mr:
22734 case MOVBE32mr_EVEX:
22735 case MOVBE32rm:
22736 case MOVBE32rm_EVEX:
22737 case MOVBE32rr:
22738 case MOVBE32rr_REV:
22739 case MOVBE64mr:
22740 case MOVBE64mr_EVEX:
22741 case MOVBE64rm:
22742 case MOVBE64rm_EVEX:
22743 case MOVBE64rr:
22744 case MOVBE64rr_REV:
22745 return true;
22746 }
22747 return false;
22748}
22749
22750bool isVP2INTERSECTD(unsigned Opcode) {
22751 switch (Opcode) {
22752 case VP2INTERSECTDZ128rm:
22753 case VP2INTERSECTDZ128rmb:
22754 case VP2INTERSECTDZ128rr:
22755 case VP2INTERSECTDZ256rm:
22756 case VP2INTERSECTDZ256rmb:
22757 case VP2INTERSECTDZ256rr:
22758 case VP2INTERSECTDZrm:
22759 case VP2INTERSECTDZrmb:
22760 case VP2INTERSECTDZrr:
22761 return true;
22762 }
22763 return false;
22764}
22765
22766bool isVPMULLQ(unsigned Opcode) {
22767 switch (Opcode) {
22768 case VPMULLQZ128rm:
22769 case VPMULLQZ128rmb:
22770 case VPMULLQZ128rmbk:
22771 case VPMULLQZ128rmbkz:
22772 case VPMULLQZ128rmk:
22773 case VPMULLQZ128rmkz:
22774 case VPMULLQZ128rr:
22775 case VPMULLQZ128rrk:
22776 case VPMULLQZ128rrkz:
22777 case VPMULLQZ256rm:
22778 case VPMULLQZ256rmb:
22779 case VPMULLQZ256rmbk:
22780 case VPMULLQZ256rmbkz:
22781 case VPMULLQZ256rmk:
22782 case VPMULLQZ256rmkz:
22783 case VPMULLQZ256rr:
22784 case VPMULLQZ256rrk:
22785 case VPMULLQZ256rrkz:
22786 case VPMULLQZrm:
22787 case VPMULLQZrmb:
22788 case VPMULLQZrmbk:
22789 case VPMULLQZrmbkz:
22790 case VPMULLQZrmk:
22791 case VPMULLQZrmkz:
22792 case VPMULLQZrr:
22793 case VPMULLQZrrk:
22794 case VPMULLQZrrkz:
22795 return true;
22796 }
22797 return false;
22798}
22799
22800bool isVSCALEFPS(unsigned Opcode) {
22801 switch (Opcode) {
22802 case VSCALEFPSZ128rm:
22803 case VSCALEFPSZ128rmb:
22804 case VSCALEFPSZ128rmbk:
22805 case VSCALEFPSZ128rmbkz:
22806 case VSCALEFPSZ128rmk:
22807 case VSCALEFPSZ128rmkz:
22808 case VSCALEFPSZ128rr:
22809 case VSCALEFPSZ128rrk:
22810 case VSCALEFPSZ128rrkz:
22811 case VSCALEFPSZ256rm:
22812 case VSCALEFPSZ256rmb:
22813 case VSCALEFPSZ256rmbk:
22814 case VSCALEFPSZ256rmbkz:
22815 case VSCALEFPSZ256rmk:
22816 case VSCALEFPSZ256rmkz:
22817 case VSCALEFPSZ256rr:
22818 case VSCALEFPSZ256rrk:
22819 case VSCALEFPSZ256rrkz:
22820 case VSCALEFPSZrm:
22821 case VSCALEFPSZrmb:
22822 case VSCALEFPSZrmbk:
22823 case VSCALEFPSZrmbkz:
22824 case VSCALEFPSZrmk:
22825 case VSCALEFPSZrmkz:
22826 case VSCALEFPSZrr:
22827 case VSCALEFPSZrrb:
22828 case VSCALEFPSZrrbk:
22829 case VSCALEFPSZrrbkz:
22830 case VSCALEFPSZrrk:
22831 case VSCALEFPSZrrkz:
22832 return true;
22833 }
22834 return false;
22835}
22836
22837bool isVPMACSDQH(unsigned Opcode) {
22838 switch (Opcode) {
22839 case VPMACSDQHrm:
22840 case VPMACSDQHrr:
22841 return true;
22842 }
22843 return false;
22844}
22845
22846bool isVPTESTNMD(unsigned Opcode) {
22847 switch (Opcode) {
22848 case VPTESTNMDZ128rm:
22849 case VPTESTNMDZ128rmb:
22850 case VPTESTNMDZ128rmbk:
22851 case VPTESTNMDZ128rmk:
22852 case VPTESTNMDZ128rr:
22853 case VPTESTNMDZ128rrk:
22854 case VPTESTNMDZ256rm:
22855 case VPTESTNMDZ256rmb:
22856 case VPTESTNMDZ256rmbk:
22857 case VPTESTNMDZ256rmk:
22858 case VPTESTNMDZ256rr:
22859 case VPTESTNMDZ256rrk:
22860 case VPTESTNMDZrm:
22861 case VPTESTNMDZrmb:
22862 case VPTESTNMDZrmbk:
22863 case VPTESTNMDZrmk:
22864 case VPTESTNMDZrr:
22865 case VPTESTNMDZrrk:
22866 return true;
22867 }
22868 return false;
22869}
22870
22871bool isFCOMP(unsigned Opcode) {
22872 switch (Opcode) {
22873 case COMP_FST0r:
22874 case FCOMP32m:
22875 case FCOMP64m:
22876 return true;
22877 }
22878 return false;
22879}
22880
22881bool isPREFETCHWT1(unsigned Opcode) {
22882 return Opcode == PREFETCHWT1;
22883}
22884
22885bool isVCMPSD(unsigned Opcode) {
22886 switch (Opcode) {
22887 case VCMPSDZrmi_Int:
22888 case VCMPSDZrmik_Int:
22889 case VCMPSDZrri_Int:
22890 case VCMPSDZrrib_Int:
22891 case VCMPSDZrribk_Int:
22892 case VCMPSDZrrik_Int:
22893 case VCMPSDrmi_Int:
22894 case VCMPSDrri_Int:
22895 return true;
22896 }
22897 return false;
22898}
22899
22900bool isSGDTD(unsigned Opcode) {
22901 return Opcode == SGDT32m;
22902}
22903
22904bool isWRUSSD(unsigned Opcode) {
22905 switch (Opcode) {
22906 case WRUSSD:
22907 case WRUSSD_EVEX:
22908 return true;
22909 }
22910 return false;
22911}
22912
22913bool isFSUBP(unsigned Opcode) {
22914 return Opcode == SUB_FPrST0;
22915}
22916
22917bool isVUNPCKLPS(unsigned Opcode) {
22918 switch (Opcode) {
22919 case VUNPCKLPSYrm:
22920 case VUNPCKLPSYrr:
22921 case VUNPCKLPSZ128rm:
22922 case VUNPCKLPSZ128rmb:
22923 case VUNPCKLPSZ128rmbk:
22924 case VUNPCKLPSZ128rmbkz:
22925 case VUNPCKLPSZ128rmk:
22926 case VUNPCKLPSZ128rmkz:
22927 case VUNPCKLPSZ128rr:
22928 case VUNPCKLPSZ128rrk:
22929 case VUNPCKLPSZ128rrkz:
22930 case VUNPCKLPSZ256rm:
22931 case VUNPCKLPSZ256rmb:
22932 case VUNPCKLPSZ256rmbk:
22933 case VUNPCKLPSZ256rmbkz:
22934 case VUNPCKLPSZ256rmk:
22935 case VUNPCKLPSZ256rmkz:
22936 case VUNPCKLPSZ256rr:
22937 case VUNPCKLPSZ256rrk:
22938 case VUNPCKLPSZ256rrkz:
22939 case VUNPCKLPSZrm:
22940 case VUNPCKLPSZrmb:
22941 case VUNPCKLPSZrmbk:
22942 case VUNPCKLPSZrmbkz:
22943 case VUNPCKLPSZrmk:
22944 case VUNPCKLPSZrmkz:
22945 case VUNPCKLPSZrr:
22946 case VUNPCKLPSZrrk:
22947 case VUNPCKLPSZrrkz:
22948 case VUNPCKLPSrm:
22949 case VUNPCKLPSrr:
22950 return true;
22951 }
22952 return false;
22953}
22954
22955bool isVFNMSUB213SS(unsigned Opcode) {
22956 switch (Opcode) {
22957 case VFNMSUB213SSZm_Int:
22958 case VFNMSUB213SSZmk_Int:
22959 case VFNMSUB213SSZmkz_Int:
22960 case VFNMSUB213SSZr_Int:
22961 case VFNMSUB213SSZrb_Int:
22962 case VFNMSUB213SSZrbk_Int:
22963 case VFNMSUB213SSZrbkz_Int:
22964 case VFNMSUB213SSZrk_Int:
22965 case VFNMSUB213SSZrkz_Int:
22966 case VFNMSUB213SSm_Int:
22967 case VFNMSUB213SSr_Int:
22968 return true;
22969 }
22970 return false;
22971}
22972
22973bool isROUNDPD(unsigned Opcode) {
22974 switch (Opcode) {
22975 case ROUNDPDmi:
22976 case ROUNDPDri:
22977 return true;
22978 }
22979 return false;
22980}
22981
22982bool isVPMAXSW(unsigned Opcode) {
22983 switch (Opcode) {
22984 case VPMAXSWYrm:
22985 case VPMAXSWYrr:
22986 case VPMAXSWZ128rm:
22987 case VPMAXSWZ128rmk:
22988 case VPMAXSWZ128rmkz:
22989 case VPMAXSWZ128rr:
22990 case VPMAXSWZ128rrk:
22991 case VPMAXSWZ128rrkz:
22992 case VPMAXSWZ256rm:
22993 case VPMAXSWZ256rmk:
22994 case VPMAXSWZ256rmkz:
22995 case VPMAXSWZ256rr:
22996 case VPMAXSWZ256rrk:
22997 case VPMAXSWZ256rrkz:
22998 case VPMAXSWZrm:
22999 case VPMAXSWZrmk:
23000 case VPMAXSWZrmkz:
23001 case VPMAXSWZrr:
23002 case VPMAXSWZrrk:
23003 case VPMAXSWZrrkz:
23004 case VPMAXSWrm:
23005 case VPMAXSWrr:
23006 return true;
23007 }
23008 return false;
23009}
23010
23011bool isVCVTTPH2DQ(unsigned Opcode) {
23012 switch (Opcode) {
23013 case VCVTTPH2DQZ128rm:
23014 case VCVTTPH2DQZ128rmb:
23015 case VCVTTPH2DQZ128rmbk:
23016 case VCVTTPH2DQZ128rmbkz:
23017 case VCVTTPH2DQZ128rmk:
23018 case VCVTTPH2DQZ128rmkz:
23019 case VCVTTPH2DQZ128rr:
23020 case VCVTTPH2DQZ128rrk:
23021 case VCVTTPH2DQZ128rrkz:
23022 case VCVTTPH2DQZ256rm:
23023 case VCVTTPH2DQZ256rmb:
23024 case VCVTTPH2DQZ256rmbk:
23025 case VCVTTPH2DQZ256rmbkz:
23026 case VCVTTPH2DQZ256rmk:
23027 case VCVTTPH2DQZ256rmkz:
23028 case VCVTTPH2DQZ256rr:
23029 case VCVTTPH2DQZ256rrk:
23030 case VCVTTPH2DQZ256rrkz:
23031 case VCVTTPH2DQZrm:
23032 case VCVTTPH2DQZrmb:
23033 case VCVTTPH2DQZrmbk:
23034 case VCVTTPH2DQZrmbkz:
23035 case VCVTTPH2DQZrmk:
23036 case VCVTTPH2DQZrmkz:
23037 case VCVTTPH2DQZrr:
23038 case VCVTTPH2DQZrrb:
23039 case VCVTTPH2DQZrrbk:
23040 case VCVTTPH2DQZrrbkz:
23041 case VCVTTPH2DQZrrk:
23042 case VCVTTPH2DQZrrkz:
23043 return true;
23044 }
23045 return false;
23046}
23047
23048bool isVPUNPCKLWD(unsigned Opcode) {
23049 switch (Opcode) {
23050 case VPUNPCKLWDYrm:
23051 case VPUNPCKLWDYrr:
23052 case VPUNPCKLWDZ128rm:
23053 case VPUNPCKLWDZ128rmk:
23054 case VPUNPCKLWDZ128rmkz:
23055 case VPUNPCKLWDZ128rr:
23056 case VPUNPCKLWDZ128rrk:
23057 case VPUNPCKLWDZ128rrkz:
23058 case VPUNPCKLWDZ256rm:
23059 case VPUNPCKLWDZ256rmk:
23060 case VPUNPCKLWDZ256rmkz:
23061 case VPUNPCKLWDZ256rr:
23062 case VPUNPCKLWDZ256rrk:
23063 case VPUNPCKLWDZ256rrkz:
23064 case VPUNPCKLWDZrm:
23065 case VPUNPCKLWDZrmk:
23066 case VPUNPCKLWDZrmkz:
23067 case VPUNPCKLWDZrr:
23068 case VPUNPCKLWDZrrk:
23069 case VPUNPCKLWDZrrkz:
23070 case VPUNPCKLWDrm:
23071 case VPUNPCKLWDrr:
23072 return true;
23073 }
23074 return false;
23075}
23076
23077bool isKSHIFTLD(unsigned Opcode) {
23078 return Opcode == KSHIFTLDki;
23079}
23080
23081bool isTCVTROWPS2BF16H(unsigned Opcode) {
23082 switch (Opcode) {
23083 case TCVTROWPS2BF16Hrte:
23084 case TCVTROWPS2BF16Hrti:
23085 return true;
23086 }
23087 return false;
23088}
23089
23090bool isVFMADD231SD(unsigned Opcode) {
23091 switch (Opcode) {
23092 case VFMADD231SDZm_Int:
23093 case VFMADD231SDZmk_Int:
23094 case VFMADD231SDZmkz_Int:
23095 case VFMADD231SDZr_Int:
23096 case VFMADD231SDZrb_Int:
23097 case VFMADD231SDZrbk_Int:
23098 case VFMADD231SDZrbkz_Int:
23099 case VFMADD231SDZrk_Int:
23100 case VFMADD231SDZrkz_Int:
23101 case VFMADD231SDm_Int:
23102 case VFMADD231SDr_Int:
23103 return true;
23104 }
23105 return false;
23106}
23107
23108bool isADDPS(unsigned Opcode) {
23109 switch (Opcode) {
23110 case ADDPSrm:
23111 case ADDPSrr:
23112 return true;
23113 }
23114 return false;
23115}
23116
23117bool isVPSLLVD(unsigned Opcode) {
23118 switch (Opcode) {
23119 case VPSLLVDYrm:
23120 case VPSLLVDYrr:
23121 case VPSLLVDZ128rm:
23122 case VPSLLVDZ128rmb:
23123 case VPSLLVDZ128rmbk:
23124 case VPSLLVDZ128rmbkz:
23125 case VPSLLVDZ128rmk:
23126 case VPSLLVDZ128rmkz:
23127 case VPSLLVDZ128rr:
23128 case VPSLLVDZ128rrk:
23129 case VPSLLVDZ128rrkz:
23130 case VPSLLVDZ256rm:
23131 case VPSLLVDZ256rmb:
23132 case VPSLLVDZ256rmbk:
23133 case VPSLLVDZ256rmbkz:
23134 case VPSLLVDZ256rmk:
23135 case VPSLLVDZ256rmkz:
23136 case VPSLLVDZ256rr:
23137 case VPSLLVDZ256rrk:
23138 case VPSLLVDZ256rrkz:
23139 case VPSLLVDZrm:
23140 case VPSLLVDZrmb:
23141 case VPSLLVDZrmbk:
23142 case VPSLLVDZrmbkz:
23143 case VPSLLVDZrmk:
23144 case VPSLLVDZrmkz:
23145 case VPSLLVDZrr:
23146 case VPSLLVDZrrk:
23147 case VPSLLVDZrrkz:
23148 case VPSLLVDrm:
23149 case VPSLLVDrr:
23150 return true;
23151 }
23152 return false;
23153}
23154
23155bool isVFNMADD132SH(unsigned Opcode) {
23156 switch (Opcode) {
23157 case VFNMADD132SHZm_Int:
23158 case VFNMADD132SHZmk_Int:
23159 case VFNMADD132SHZmkz_Int:
23160 case VFNMADD132SHZr_Int:
23161 case VFNMADD132SHZrb_Int:
23162 case VFNMADD132SHZrbk_Int:
23163 case VFNMADD132SHZrbkz_Int:
23164 case VFNMADD132SHZrk_Int:
23165 case VFNMADD132SHZrkz_Int:
23166 return true;
23167 }
23168 return false;
23169}
23170
23171bool isVMOVNTPS(unsigned Opcode) {
23172 switch (Opcode) {
23173 case VMOVNTPSYmr:
23174 case VMOVNTPSZ128mr:
23175 case VMOVNTPSZ256mr:
23176 case VMOVNTPSZmr:
23177 case VMOVNTPSmr:
23178 return true;
23179 }
23180 return false;
23181}
23182
23183bool isVCVTPD2DQ(unsigned Opcode) {
23184 switch (Opcode) {
23185 case VCVTPD2DQYrm:
23186 case VCVTPD2DQYrr:
23187 case VCVTPD2DQZ128rm:
23188 case VCVTPD2DQZ128rmb:
23189 case VCVTPD2DQZ128rmbk:
23190 case VCVTPD2DQZ128rmbkz:
23191 case VCVTPD2DQZ128rmk:
23192 case VCVTPD2DQZ128rmkz:
23193 case VCVTPD2DQZ128rr:
23194 case VCVTPD2DQZ128rrk:
23195 case VCVTPD2DQZ128rrkz:
23196 case VCVTPD2DQZ256rm:
23197 case VCVTPD2DQZ256rmb:
23198 case VCVTPD2DQZ256rmbk:
23199 case VCVTPD2DQZ256rmbkz:
23200 case VCVTPD2DQZ256rmk:
23201 case VCVTPD2DQZ256rmkz:
23202 case VCVTPD2DQZ256rr:
23203 case VCVTPD2DQZ256rrk:
23204 case VCVTPD2DQZ256rrkz:
23205 case VCVTPD2DQZrm:
23206 case VCVTPD2DQZrmb:
23207 case VCVTPD2DQZrmbk:
23208 case VCVTPD2DQZrmbkz:
23209 case VCVTPD2DQZrmk:
23210 case VCVTPD2DQZrmkz:
23211 case VCVTPD2DQZrr:
23212 case VCVTPD2DQZrrb:
23213 case VCVTPD2DQZrrbk:
23214 case VCVTPD2DQZrrbkz:
23215 case VCVTPD2DQZrrk:
23216 case VCVTPD2DQZrrkz:
23217 case VCVTPD2DQrm:
23218 case VCVTPD2DQrr:
23219 return true;
23220 }
23221 return false;
23222}
23223
23224bool isVPXOR(unsigned Opcode) {
23225 switch (Opcode) {
23226 case VPXORYrm:
23227 case VPXORYrr:
23228 case VPXORrm:
23229 case VPXORrr:
23230 return true;
23231 }
23232 return false;
23233}
23234
23235bool isSTMXCSR(unsigned Opcode) {
23236 return Opcode == STMXCSR;
23237}
23238
23239bool isVRCP14SS(unsigned Opcode) {
23240 switch (Opcode) {
23241 case VRCP14SSZrm:
23242 case VRCP14SSZrmk:
23243 case VRCP14SSZrmkz:
23244 case VRCP14SSZrr:
23245 case VRCP14SSZrrk:
23246 case VRCP14SSZrrkz:
23247 return true;
23248 }
23249 return false;
23250}
23251
23252bool isUD2(unsigned Opcode) {
23253 return Opcode == TRAP;
23254}
23255
23256bool isVPOPCNTW(unsigned Opcode) {
23257 switch (Opcode) {
23258 case VPOPCNTWZ128rm:
23259 case VPOPCNTWZ128rmk:
23260 case VPOPCNTWZ128rmkz:
23261 case VPOPCNTWZ128rr:
23262 case VPOPCNTWZ128rrk:
23263 case VPOPCNTWZ128rrkz:
23264 case VPOPCNTWZ256rm:
23265 case VPOPCNTWZ256rmk:
23266 case VPOPCNTWZ256rmkz:
23267 case VPOPCNTWZ256rr:
23268 case VPOPCNTWZ256rrk:
23269 case VPOPCNTWZ256rrkz:
23270 case VPOPCNTWZrm:
23271 case VPOPCNTWZrmk:
23272 case VPOPCNTWZrmkz:
23273 case VPOPCNTWZrr:
23274 case VPOPCNTWZrrk:
23275 case VPOPCNTWZrrkz:
23276 return true;
23277 }
23278 return false;
23279}
23280
23281bool isVRSQRTSH(unsigned Opcode) {
23282 switch (Opcode) {
23283 case VRSQRTSHZrm:
23284 case VRSQRTSHZrmk:
23285 case VRSQRTSHZrmkz:
23286 case VRSQRTSHZrr:
23287 case VRSQRTSHZrrk:
23288 case VRSQRTSHZrrkz:
23289 return true;
23290 }
23291 return false;
23292}
23293
23294bool isVSCATTERPF0DPD(unsigned Opcode) {
23295 return Opcode == VSCATTERPF0DPDm;
23296}
23297
23298bool isVFMADDPS(unsigned Opcode) {
23299 switch (Opcode) {
23300 case VFMADDPS4Ymr:
23301 case VFMADDPS4Yrm:
23302 case VFMADDPS4Yrr:
23303 case VFMADDPS4Yrr_REV:
23304 case VFMADDPS4mr:
23305 case VFMADDPS4rm:
23306 case VFMADDPS4rr:
23307 case VFMADDPS4rr_REV:
23308 return true;
23309 }
23310 return false;
23311}
23312
23313bool isXSAVEC64(unsigned Opcode) {
23314 return Opcode == XSAVEC64;
23315}
23316
23317bool isVPMADDUBSW(unsigned Opcode) {
23318 switch (Opcode) {
23319 case VPMADDUBSWYrm:
23320 case VPMADDUBSWYrr:
23321 case VPMADDUBSWZ128rm:
23322 case VPMADDUBSWZ128rmk:
23323 case VPMADDUBSWZ128rmkz:
23324 case VPMADDUBSWZ128rr:
23325 case VPMADDUBSWZ128rrk:
23326 case VPMADDUBSWZ128rrkz:
23327 case VPMADDUBSWZ256rm:
23328 case VPMADDUBSWZ256rmk:
23329 case VPMADDUBSWZ256rmkz:
23330 case VPMADDUBSWZ256rr:
23331 case VPMADDUBSWZ256rrk:
23332 case VPMADDUBSWZ256rrkz:
23333 case VPMADDUBSWZrm:
23334 case VPMADDUBSWZrmk:
23335 case VPMADDUBSWZrmkz:
23336 case VPMADDUBSWZrr:
23337 case VPMADDUBSWZrrk:
23338 case VPMADDUBSWZrrkz:
23339 case VPMADDUBSWrm:
23340 case VPMADDUBSWrr:
23341 return true;
23342 }
23343 return false;
23344}
23345
23346bool isVPMOVZXDQ(unsigned Opcode) {
23347 switch (Opcode) {
23348 case VPMOVZXDQYrm:
23349 case VPMOVZXDQYrr:
23350 case VPMOVZXDQZ128rm:
23351 case VPMOVZXDQZ128rmk:
23352 case VPMOVZXDQZ128rmkz:
23353 case VPMOVZXDQZ128rr:
23354 case VPMOVZXDQZ128rrk:
23355 case VPMOVZXDQZ128rrkz:
23356 case VPMOVZXDQZ256rm:
23357 case VPMOVZXDQZ256rmk:
23358 case VPMOVZXDQZ256rmkz:
23359 case VPMOVZXDQZ256rr:
23360 case VPMOVZXDQZ256rrk:
23361 case VPMOVZXDQZ256rrkz:
23362 case VPMOVZXDQZrm:
23363 case VPMOVZXDQZrmk:
23364 case VPMOVZXDQZrmkz:
23365 case VPMOVZXDQZrr:
23366 case VPMOVZXDQZrrk:
23367 case VPMOVZXDQZrrkz:
23368 case VPMOVZXDQrm:
23369 case VPMOVZXDQrr:
23370 return true;
23371 }
23372 return false;
23373}
23374
23375bool isVRCP14PS(unsigned Opcode) {
23376 switch (Opcode) {
23377 case VRCP14PSZ128m:
23378 case VRCP14PSZ128mb:
23379 case VRCP14PSZ128mbk:
23380 case VRCP14PSZ128mbkz:
23381 case VRCP14PSZ128mk:
23382 case VRCP14PSZ128mkz:
23383 case VRCP14PSZ128r:
23384 case VRCP14PSZ128rk:
23385 case VRCP14PSZ128rkz:
23386 case VRCP14PSZ256m:
23387 case VRCP14PSZ256mb:
23388 case VRCP14PSZ256mbk:
23389 case VRCP14PSZ256mbkz:
23390 case VRCP14PSZ256mk:
23391 case VRCP14PSZ256mkz:
23392 case VRCP14PSZ256r:
23393 case VRCP14PSZ256rk:
23394 case VRCP14PSZ256rkz:
23395 case VRCP14PSZm:
23396 case VRCP14PSZmb:
23397 case VRCP14PSZmbk:
23398 case VRCP14PSZmbkz:
23399 case VRCP14PSZmk:
23400 case VRCP14PSZmkz:
23401 case VRCP14PSZr:
23402 case VRCP14PSZrk:
23403 case VRCP14PSZrkz:
23404 return true;
23405 }
23406 return false;
23407}
23408
23409bool isVSQRTSH(unsigned Opcode) {
23410 switch (Opcode) {
23411 case VSQRTSHZm_Int:
23412 case VSQRTSHZmk_Int:
23413 case VSQRTSHZmkz_Int:
23414 case VSQRTSHZr_Int:
23415 case VSQRTSHZrb_Int:
23416 case VSQRTSHZrbk_Int:
23417 case VSQRTSHZrbkz_Int:
23418 case VSQRTSHZrk_Int:
23419 case VSQRTSHZrkz_Int:
23420 return true;
23421 }
23422 return false;
23423}
23424
23425bool isTCVTROWD2PS(unsigned Opcode) {
23426 switch (Opcode) {
23427 case TCVTROWD2PSrte:
23428 case TCVTROWD2PSrti:
23429 return true;
23430 }
23431 return false;
23432}
23433
23434bool isLOOP(unsigned Opcode) {
23435 return Opcode == LOOP;
23436}
23437
23438bool isSTUI(unsigned Opcode) {
23439 return Opcode == STUI;
23440}
23441
23442bool isVCVTTPS2UDQ(unsigned Opcode) {
23443 switch (Opcode) {
23444 case VCVTTPS2UDQZ128rm:
23445 case VCVTTPS2UDQZ128rmb:
23446 case VCVTTPS2UDQZ128rmbk:
23447 case VCVTTPS2UDQZ128rmbkz:
23448 case VCVTTPS2UDQZ128rmk:
23449 case VCVTTPS2UDQZ128rmkz:
23450 case VCVTTPS2UDQZ128rr:
23451 case VCVTTPS2UDQZ128rrk:
23452 case VCVTTPS2UDQZ128rrkz:
23453 case VCVTTPS2UDQZ256rm:
23454 case VCVTTPS2UDQZ256rmb:
23455 case VCVTTPS2UDQZ256rmbk:
23456 case VCVTTPS2UDQZ256rmbkz:
23457 case VCVTTPS2UDQZ256rmk:
23458 case VCVTTPS2UDQZ256rmkz:
23459 case VCVTTPS2UDQZ256rr:
23460 case VCVTTPS2UDQZ256rrk:
23461 case VCVTTPS2UDQZ256rrkz:
23462 case VCVTTPS2UDQZrm:
23463 case VCVTTPS2UDQZrmb:
23464 case VCVTTPS2UDQZrmbk:
23465 case VCVTTPS2UDQZrmbkz:
23466 case VCVTTPS2UDQZrmk:
23467 case VCVTTPS2UDQZrmkz:
23468 case VCVTTPS2UDQZrr:
23469 case VCVTTPS2UDQZrrb:
23470 case VCVTTPS2UDQZrrbk:
23471 case VCVTTPS2UDQZrrbkz:
23472 case VCVTTPS2UDQZrrk:
23473 case VCVTTPS2UDQZrrkz:
23474 return true;
23475 }
23476 return false;
23477}
23478
23479bool isXABORT(unsigned Opcode) {
23480 return Opcode == XABORT;
23481}
23482
23483bool isVCOMPRESSPS(unsigned Opcode) {
23484 switch (Opcode) {
23485 case VCOMPRESSPSZ128mr:
23486 case VCOMPRESSPSZ128mrk:
23487 case VCOMPRESSPSZ128rr:
23488 case VCOMPRESSPSZ128rrk:
23489 case VCOMPRESSPSZ128rrkz:
23490 case VCOMPRESSPSZ256mr:
23491 case VCOMPRESSPSZ256mrk:
23492 case VCOMPRESSPSZ256rr:
23493 case VCOMPRESSPSZ256rrk:
23494 case VCOMPRESSPSZ256rrkz:
23495 case VCOMPRESSPSZmr:
23496 case VCOMPRESSPSZmrk:
23497 case VCOMPRESSPSZrr:
23498 case VCOMPRESSPSZrrk:
23499 case VCOMPRESSPSZrrkz:
23500 return true;
23501 }
23502 return false;
23503}
23504
23505bool isVCVTTBF162IUBS(unsigned Opcode) {
23506 switch (Opcode) {
23507 case VCVTTBF162IUBSZ128rm:
23508 case VCVTTBF162IUBSZ128rmb:
23509 case VCVTTBF162IUBSZ128rmbk:
23510 case VCVTTBF162IUBSZ128rmbkz:
23511 case VCVTTBF162IUBSZ128rmk:
23512 case VCVTTBF162IUBSZ128rmkz:
23513 case VCVTTBF162IUBSZ128rr:
23514 case VCVTTBF162IUBSZ128rrk:
23515 case VCVTTBF162IUBSZ128rrkz:
23516 case VCVTTBF162IUBSZ256rm:
23517 case VCVTTBF162IUBSZ256rmb:
23518 case VCVTTBF162IUBSZ256rmbk:
23519 case VCVTTBF162IUBSZ256rmbkz:
23520 case VCVTTBF162IUBSZ256rmk:
23521 case VCVTTBF162IUBSZ256rmkz:
23522 case VCVTTBF162IUBSZ256rr:
23523 case VCVTTBF162IUBSZ256rrk:
23524 case VCVTTBF162IUBSZ256rrkz:
23525 case VCVTTBF162IUBSZrm:
23526 case VCVTTBF162IUBSZrmb:
23527 case VCVTTBF162IUBSZrmbk:
23528 case VCVTTBF162IUBSZrmbkz:
23529 case VCVTTBF162IUBSZrmk:
23530 case VCVTTBF162IUBSZrmkz:
23531 case VCVTTBF162IUBSZrr:
23532 case VCVTTBF162IUBSZrrk:
23533 case VCVTTBF162IUBSZrrkz:
23534 return true;
23535 }
23536 return false;
23537}
23538
23539bool isVPADDW(unsigned Opcode) {
23540 switch (Opcode) {
23541 case VPADDWYrm:
23542 case VPADDWYrr:
23543 case VPADDWZ128rm:
23544 case VPADDWZ128rmk:
23545 case VPADDWZ128rmkz:
23546 case VPADDWZ128rr:
23547 case VPADDWZ128rrk:
23548 case VPADDWZ128rrkz:
23549 case VPADDWZ256rm:
23550 case VPADDWZ256rmk:
23551 case VPADDWZ256rmkz:
23552 case VPADDWZ256rr:
23553 case VPADDWZ256rrk:
23554 case VPADDWZ256rrkz:
23555 case VPADDWZrm:
23556 case VPADDWZrmk:
23557 case VPADDWZrmkz:
23558 case VPADDWZrr:
23559 case VPADDWZrrk:
23560 case VPADDWZrrkz:
23561 case VPADDWrm:
23562 case VPADDWrr:
23563 return true;
23564 }
23565 return false;
23566}
23567
23568bool isVPSIGND(unsigned Opcode) {
23569 switch (Opcode) {
23570 case VPSIGNDYrm:
23571 case VPSIGNDYrr:
23572 case VPSIGNDrm:
23573 case VPSIGNDrr:
23574 return true;
23575 }
23576 return false;
23577}
23578
23579bool isVRNDSCALEPS(unsigned Opcode) {
23580 switch (Opcode) {
23581 case VRNDSCALEPSZ128rmbi:
23582 case VRNDSCALEPSZ128rmbik:
23583 case VRNDSCALEPSZ128rmbikz:
23584 case VRNDSCALEPSZ128rmi:
23585 case VRNDSCALEPSZ128rmik:
23586 case VRNDSCALEPSZ128rmikz:
23587 case VRNDSCALEPSZ128rri:
23588 case VRNDSCALEPSZ128rrik:
23589 case VRNDSCALEPSZ128rrikz:
23590 case VRNDSCALEPSZ256rmbi:
23591 case VRNDSCALEPSZ256rmbik:
23592 case VRNDSCALEPSZ256rmbikz:
23593 case VRNDSCALEPSZ256rmi:
23594 case VRNDSCALEPSZ256rmik:
23595 case VRNDSCALEPSZ256rmikz:
23596 case VRNDSCALEPSZ256rri:
23597 case VRNDSCALEPSZ256rrik:
23598 case VRNDSCALEPSZ256rrikz:
23599 case VRNDSCALEPSZrmbi:
23600 case VRNDSCALEPSZrmbik:
23601 case VRNDSCALEPSZrmbikz:
23602 case VRNDSCALEPSZrmi:
23603 case VRNDSCALEPSZrmik:
23604 case VRNDSCALEPSZrmikz:
23605 case VRNDSCALEPSZrri:
23606 case VRNDSCALEPSZrrib:
23607 case VRNDSCALEPSZrribk:
23608 case VRNDSCALEPSZrribkz:
23609 case VRNDSCALEPSZrrik:
23610 case VRNDSCALEPSZrrikz:
23611 return true;
23612 }
23613 return false;
23614}
23615
23616bool isVPHADDUWD(unsigned Opcode) {
23617 switch (Opcode) {
23618 case VPHADDUWDrm:
23619 case VPHADDUWDrr:
23620 return true;
23621 }
23622 return false;
23623}
23624
23625bool isVCVT2PH2HF8S(unsigned Opcode) {
23626 switch (Opcode) {
23627 case VCVT2PH2HF8SZ128rm:
23628 case VCVT2PH2HF8SZ128rmb:
23629 case VCVT2PH2HF8SZ128rmbk:
23630 case VCVT2PH2HF8SZ128rmbkz:
23631 case VCVT2PH2HF8SZ128rmk:
23632 case VCVT2PH2HF8SZ128rmkz:
23633 case VCVT2PH2HF8SZ128rr:
23634 case VCVT2PH2HF8SZ128rrk:
23635 case VCVT2PH2HF8SZ128rrkz:
23636 case VCVT2PH2HF8SZ256rm:
23637 case VCVT2PH2HF8SZ256rmb:
23638 case VCVT2PH2HF8SZ256rmbk:
23639 case VCVT2PH2HF8SZ256rmbkz:
23640 case VCVT2PH2HF8SZ256rmk:
23641 case VCVT2PH2HF8SZ256rmkz:
23642 case VCVT2PH2HF8SZ256rr:
23643 case VCVT2PH2HF8SZ256rrk:
23644 case VCVT2PH2HF8SZ256rrkz:
23645 case VCVT2PH2HF8SZrm:
23646 case VCVT2PH2HF8SZrmb:
23647 case VCVT2PH2HF8SZrmbk:
23648 case VCVT2PH2HF8SZrmbkz:
23649 case VCVT2PH2HF8SZrmk:
23650 case VCVT2PH2HF8SZrmkz:
23651 case VCVT2PH2HF8SZrr:
23652 case VCVT2PH2HF8SZrrk:
23653 case VCVT2PH2HF8SZrrkz:
23654 return true;
23655 }
23656 return false;
23657}
23658
23659bool isVDBPSADBW(unsigned Opcode) {
23660 switch (Opcode) {
23661 case VDBPSADBWZ128rmi:
23662 case VDBPSADBWZ128rmik:
23663 case VDBPSADBWZ128rmikz:
23664 case VDBPSADBWZ128rri:
23665 case VDBPSADBWZ128rrik:
23666 case VDBPSADBWZ128rrikz:
23667 case VDBPSADBWZ256rmi:
23668 case VDBPSADBWZ256rmik:
23669 case VDBPSADBWZ256rmikz:
23670 case VDBPSADBWZ256rri:
23671 case VDBPSADBWZ256rrik:
23672 case VDBPSADBWZ256rrikz:
23673 case VDBPSADBWZrmi:
23674 case VDBPSADBWZrmik:
23675 case VDBPSADBWZrmikz:
23676 case VDBPSADBWZrri:
23677 case VDBPSADBWZrrik:
23678 case VDBPSADBWZrrikz:
23679 return true;
23680 }
23681 return false;
23682}
23683
23684bool isPSLLW(unsigned Opcode) {
23685 switch (Opcode) {
23686 case MMX_PSLLWri:
23687 case MMX_PSLLWrm:
23688 case MMX_PSLLWrr:
23689 case PSLLWri:
23690 case PSLLWrm:
23691 case PSLLWrr:
23692 return true;
23693 }
23694 return false;
23695}
23696
23697bool isVPMOVQD(unsigned Opcode) {
23698 switch (Opcode) {
23699 case VPMOVQDZ128mr:
23700 case VPMOVQDZ128mrk:
23701 case VPMOVQDZ128rr:
23702 case VPMOVQDZ128rrk:
23703 case VPMOVQDZ128rrkz:
23704 case VPMOVQDZ256mr:
23705 case VPMOVQDZ256mrk:
23706 case VPMOVQDZ256rr:
23707 case VPMOVQDZ256rrk:
23708 case VPMOVQDZ256rrkz:
23709 case VPMOVQDZmr:
23710 case VPMOVQDZmrk:
23711 case VPMOVQDZrr:
23712 case VPMOVQDZrrk:
23713 case VPMOVQDZrrkz:
23714 return true;
23715 }
23716 return false;
23717}
23718
23719bool isVINSERTI64X4(unsigned Opcode) {
23720 switch (Opcode) {
23721 case VINSERTI64X4Zrmi:
23722 case VINSERTI64X4Zrmik:
23723 case VINSERTI64X4Zrmikz:
23724 case VINSERTI64X4Zrri:
23725 case VINSERTI64X4Zrrik:
23726 case VINSERTI64X4Zrrikz:
23727 return true;
23728 }
23729 return false;
23730}
23731
23732bool isVPERMI2PS(unsigned Opcode) {
23733 switch (Opcode) {
23734 case VPERMI2PSZ128rm:
23735 case VPERMI2PSZ128rmb:
23736 case VPERMI2PSZ128rmbk:
23737 case VPERMI2PSZ128rmbkz:
23738 case VPERMI2PSZ128rmk:
23739 case VPERMI2PSZ128rmkz:
23740 case VPERMI2PSZ128rr:
23741 case VPERMI2PSZ128rrk:
23742 case VPERMI2PSZ128rrkz:
23743 case VPERMI2PSZ256rm:
23744 case VPERMI2PSZ256rmb:
23745 case VPERMI2PSZ256rmbk:
23746 case VPERMI2PSZ256rmbkz:
23747 case VPERMI2PSZ256rmk:
23748 case VPERMI2PSZ256rmkz:
23749 case VPERMI2PSZ256rr:
23750 case VPERMI2PSZ256rrk:
23751 case VPERMI2PSZ256rrkz:
23752 case VPERMI2PSZrm:
23753 case VPERMI2PSZrmb:
23754 case VPERMI2PSZrmbk:
23755 case VPERMI2PSZrmbkz:
23756 case VPERMI2PSZrmk:
23757 case VPERMI2PSZrmkz:
23758 case VPERMI2PSZrr:
23759 case VPERMI2PSZrrk:
23760 case VPERMI2PSZrrkz:
23761 return true;
23762 }
23763 return false;
23764}
23765
23766bool isVMULPH(unsigned Opcode) {
23767 switch (Opcode) {
23768 case VMULPHZ128rm:
23769 case VMULPHZ128rmb:
23770 case VMULPHZ128rmbk:
23771 case VMULPHZ128rmbkz:
23772 case VMULPHZ128rmk:
23773 case VMULPHZ128rmkz:
23774 case VMULPHZ128rr:
23775 case VMULPHZ128rrk:
23776 case VMULPHZ128rrkz:
23777 case VMULPHZ256rm:
23778 case VMULPHZ256rmb:
23779 case VMULPHZ256rmbk:
23780 case VMULPHZ256rmbkz:
23781 case VMULPHZ256rmk:
23782 case VMULPHZ256rmkz:
23783 case VMULPHZ256rr:
23784 case VMULPHZ256rrk:
23785 case VMULPHZ256rrkz:
23786 case VMULPHZrm:
23787 case VMULPHZrmb:
23788 case VMULPHZrmbk:
23789 case VMULPHZrmbkz:
23790 case VMULPHZrmk:
23791 case VMULPHZrmkz:
23792 case VMULPHZrr:
23793 case VMULPHZrrb:
23794 case VMULPHZrrbk:
23795 case VMULPHZrrbkz:
23796 case VMULPHZrrk:
23797 case VMULPHZrrkz:
23798 return true;
23799 }
23800 return false;
23801}
23802
23803bool isVPCMPUQ(unsigned Opcode) {
23804 switch (Opcode) {
23805 case VPCMPUQZ128rmbi:
23806 case VPCMPUQZ128rmbik:
23807 case VPCMPUQZ128rmi:
23808 case VPCMPUQZ128rmik:
23809 case VPCMPUQZ128rri:
23810 case VPCMPUQZ128rrik:
23811 case VPCMPUQZ256rmbi:
23812 case VPCMPUQZ256rmbik:
23813 case VPCMPUQZ256rmi:
23814 case VPCMPUQZ256rmik:
23815 case VPCMPUQZ256rri:
23816 case VPCMPUQZ256rrik:
23817 case VPCMPUQZrmbi:
23818 case VPCMPUQZrmbik:
23819 case VPCMPUQZrmi:
23820 case VPCMPUQZrmik:
23821 case VPCMPUQZrri:
23822 case VPCMPUQZrrik:
23823 return true;
23824 }
23825 return false;
23826}
23827
23828bool isVCVTUSI2SD(unsigned Opcode) {
23829 switch (Opcode) {
23830 case VCVTUSI2SDZrm_Int:
23831 case VCVTUSI2SDZrr_Int:
23832 case VCVTUSI642SDZrm_Int:
23833 case VCVTUSI642SDZrr_Int:
23834 case VCVTUSI642SDZrrb_Int:
23835 return true;
23836 }
23837 return false;
23838}
23839
23840bool isKXNORW(unsigned Opcode) {
23841 return Opcode == KXNORWkk;
23842}
23843
23844bool isBLCIC(unsigned Opcode) {
23845 switch (Opcode) {
23846 case BLCIC32rm:
23847 case BLCIC32rr:
23848 case BLCIC64rm:
23849 case BLCIC64rr:
23850 return true;
23851 }
23852 return false;
23853}
23854
23855bool isVFNMADD213SD(unsigned Opcode) {
23856 switch (Opcode) {
23857 case VFNMADD213SDZm_Int:
23858 case VFNMADD213SDZmk_Int:
23859 case VFNMADD213SDZmkz_Int:
23860 case VFNMADD213SDZr_Int:
23861 case VFNMADD213SDZrb_Int:
23862 case VFNMADD213SDZrbk_Int:
23863 case VFNMADD213SDZrbkz_Int:
23864 case VFNMADD213SDZrk_Int:
23865 case VFNMADD213SDZrkz_Int:
23866 case VFNMADD213SDm_Int:
23867 case VFNMADD213SDr_Int:
23868 return true;
23869 }
23870 return false;
23871}
23872
23873bool isVMOVLPS(unsigned Opcode) {
23874 switch (Opcode) {
23875 case VMOVLPSZ128mr:
23876 case VMOVLPSZ128rm:
23877 case VMOVLPSmr:
23878 case VMOVLPSrm:
23879 return true;
23880 }
23881 return false;
23882}
23883
23884bool isVPMACSWW(unsigned Opcode) {
23885 switch (Opcode) {
23886 case VPMACSWWrm:
23887 case VPMACSWWrr:
23888 return true;
23889 }
23890 return false;
23891}
23892
23893bool isPCONFIG(unsigned Opcode) {
23894 return Opcode == PCONFIG;
23895}
23896
23897bool isPANDN(unsigned Opcode) {
23898 switch (Opcode) {
23899 case MMX_PANDNrm:
23900 case MMX_PANDNrr:
23901 case PANDNrm:
23902 case PANDNrr:
23903 return true;
23904 }
23905 return false;
23906}
23907
23908bool isVGETEXPPD(unsigned Opcode) {
23909 switch (Opcode) {
23910 case VGETEXPPDZ128m:
23911 case VGETEXPPDZ128mb:
23912 case VGETEXPPDZ128mbk:
23913 case VGETEXPPDZ128mbkz:
23914 case VGETEXPPDZ128mk:
23915 case VGETEXPPDZ128mkz:
23916 case VGETEXPPDZ128r:
23917 case VGETEXPPDZ128rk:
23918 case VGETEXPPDZ128rkz:
23919 case VGETEXPPDZ256m:
23920 case VGETEXPPDZ256mb:
23921 case VGETEXPPDZ256mbk:
23922 case VGETEXPPDZ256mbkz:
23923 case VGETEXPPDZ256mk:
23924 case VGETEXPPDZ256mkz:
23925 case VGETEXPPDZ256r:
23926 case VGETEXPPDZ256rk:
23927 case VGETEXPPDZ256rkz:
23928 case VGETEXPPDZm:
23929 case VGETEXPPDZmb:
23930 case VGETEXPPDZmbk:
23931 case VGETEXPPDZmbkz:
23932 case VGETEXPPDZmk:
23933 case VGETEXPPDZmkz:
23934 case VGETEXPPDZr:
23935 case VGETEXPPDZrb:
23936 case VGETEXPPDZrbk:
23937 case VGETEXPPDZrbkz:
23938 case VGETEXPPDZrk:
23939 case VGETEXPPDZrkz:
23940 return true;
23941 }
23942 return false;
23943}
23944
23945bool isVPSRLVQ(unsigned Opcode) {
23946 switch (Opcode) {
23947 case VPSRLVQYrm:
23948 case VPSRLVQYrr:
23949 case VPSRLVQZ128rm:
23950 case VPSRLVQZ128rmb:
23951 case VPSRLVQZ128rmbk:
23952 case VPSRLVQZ128rmbkz:
23953 case VPSRLVQZ128rmk:
23954 case VPSRLVQZ128rmkz:
23955 case VPSRLVQZ128rr:
23956 case VPSRLVQZ128rrk:
23957 case VPSRLVQZ128rrkz:
23958 case VPSRLVQZ256rm:
23959 case VPSRLVQZ256rmb:
23960 case VPSRLVQZ256rmbk:
23961 case VPSRLVQZ256rmbkz:
23962 case VPSRLVQZ256rmk:
23963 case VPSRLVQZ256rmkz:
23964 case VPSRLVQZ256rr:
23965 case VPSRLVQZ256rrk:
23966 case VPSRLVQZ256rrkz:
23967 case VPSRLVQZrm:
23968 case VPSRLVQZrmb:
23969 case VPSRLVQZrmbk:
23970 case VPSRLVQZrmbkz:
23971 case VPSRLVQZrmk:
23972 case VPSRLVQZrmkz:
23973 case VPSRLVQZrr:
23974 case VPSRLVQZrrk:
23975 case VPSRLVQZrrkz:
23976 case VPSRLVQrm:
23977 case VPSRLVQrr:
23978 return true;
23979 }
23980 return false;
23981}
23982
23983bool isUD1(unsigned Opcode) {
23984 switch (Opcode) {
23985 case UD1Lm:
23986 case UD1Lr:
23987 case UD1Qm:
23988 case UD1Qr:
23989 case UD1Wm:
23990 case UD1Wr:
23991 return true;
23992 }
23993 return false;
23994}
23995
23996bool isPMAXSB(unsigned Opcode) {
23997 switch (Opcode) {
23998 case PMAXSBrm:
23999 case PMAXSBrr:
24000 return true;
24001 }
24002 return false;
24003}
24004
24005bool isVPROLQ(unsigned Opcode) {
24006 switch (Opcode) {
24007 case VPROLQZ128mbi:
24008 case VPROLQZ128mbik:
24009 case VPROLQZ128mbikz:
24010 case VPROLQZ128mi:
24011 case VPROLQZ128mik:
24012 case VPROLQZ128mikz:
24013 case VPROLQZ128ri:
24014 case VPROLQZ128rik:
24015 case VPROLQZ128rikz:
24016 case VPROLQZ256mbi:
24017 case VPROLQZ256mbik:
24018 case VPROLQZ256mbikz:
24019 case VPROLQZ256mi:
24020 case VPROLQZ256mik:
24021 case VPROLQZ256mikz:
24022 case VPROLQZ256ri:
24023 case VPROLQZ256rik:
24024 case VPROLQZ256rikz:
24025 case VPROLQZmbi:
24026 case VPROLQZmbik:
24027 case VPROLQZmbikz:
24028 case VPROLQZmi:
24029 case VPROLQZmik:
24030 case VPROLQZmikz:
24031 case VPROLQZri:
24032 case VPROLQZrik:
24033 case VPROLQZrikz:
24034 return true;
24035 }
24036 return false;
24037}
24038
24039bool isVPSRLD(unsigned Opcode) {
24040 switch (Opcode) {
24041 case VPSRLDYri:
24042 case VPSRLDYrm:
24043 case VPSRLDYrr:
24044 case VPSRLDZ128mbi:
24045 case VPSRLDZ128mbik:
24046 case VPSRLDZ128mbikz:
24047 case VPSRLDZ128mi:
24048 case VPSRLDZ128mik:
24049 case VPSRLDZ128mikz:
24050 case VPSRLDZ128ri:
24051 case VPSRLDZ128rik:
24052 case VPSRLDZ128rikz:
24053 case VPSRLDZ128rm:
24054 case VPSRLDZ128rmk:
24055 case VPSRLDZ128rmkz:
24056 case VPSRLDZ128rr:
24057 case VPSRLDZ128rrk:
24058 case VPSRLDZ128rrkz:
24059 case VPSRLDZ256mbi:
24060 case VPSRLDZ256mbik:
24061 case VPSRLDZ256mbikz:
24062 case VPSRLDZ256mi:
24063 case VPSRLDZ256mik:
24064 case VPSRLDZ256mikz:
24065 case VPSRLDZ256ri:
24066 case VPSRLDZ256rik:
24067 case VPSRLDZ256rikz:
24068 case VPSRLDZ256rm:
24069 case VPSRLDZ256rmk:
24070 case VPSRLDZ256rmkz:
24071 case VPSRLDZ256rr:
24072 case VPSRLDZ256rrk:
24073 case VPSRLDZ256rrkz:
24074 case VPSRLDZmbi:
24075 case VPSRLDZmbik:
24076 case VPSRLDZmbikz:
24077 case VPSRLDZmi:
24078 case VPSRLDZmik:
24079 case VPSRLDZmikz:
24080 case VPSRLDZri:
24081 case VPSRLDZrik:
24082 case VPSRLDZrikz:
24083 case VPSRLDZrm:
24084 case VPSRLDZrmk:
24085 case VPSRLDZrmkz:
24086 case VPSRLDZrr:
24087 case VPSRLDZrrk:
24088 case VPSRLDZrrkz:
24089 case VPSRLDri:
24090 case VPSRLDrm:
24091 case VPSRLDrr:
24092 return true;
24093 }
24094 return false;
24095}
24096
24097bool isVSCATTERPF1QPD(unsigned Opcode) {
24098 return Opcode == VSCATTERPF1QPDm;
24099}
24100
24101bool isINT3(unsigned Opcode) {
24102 return Opcode == INT3;
24103}
24104
24105bool isXRSTORS64(unsigned Opcode) {
24106 return Opcode == XRSTORS64;
24107}
24108
24109bool isCVTSD2SI(unsigned Opcode) {
24110 switch (Opcode) {
24111 case CVTSD2SI64rm_Int:
24112 case CVTSD2SI64rr_Int:
24113 case CVTSD2SIrm_Int:
24114 case CVTSD2SIrr_Int:
24115 return true;
24116 }
24117 return false;
24118}
24119
24120bool isVMAXSS(unsigned Opcode) {
24121 switch (Opcode) {
24122 case VMAXSSZrm_Int:
24123 case VMAXSSZrmk_Int:
24124 case VMAXSSZrmkz_Int:
24125 case VMAXSSZrr_Int:
24126 case VMAXSSZrrb_Int:
24127 case VMAXSSZrrbk_Int:
24128 case VMAXSSZrrbkz_Int:
24129 case VMAXSSZrrk_Int:
24130 case VMAXSSZrrkz_Int:
24131 case VMAXSSrm_Int:
24132 case VMAXSSrr_Int:
24133 return true;
24134 }
24135 return false;
24136}
24137
24138bool isVPMINUB(unsigned Opcode) {
24139 switch (Opcode) {
24140 case VPMINUBYrm:
24141 case VPMINUBYrr:
24142 case VPMINUBZ128rm:
24143 case VPMINUBZ128rmk:
24144 case VPMINUBZ128rmkz:
24145 case VPMINUBZ128rr:
24146 case VPMINUBZ128rrk:
24147 case VPMINUBZ128rrkz:
24148 case VPMINUBZ256rm:
24149 case VPMINUBZ256rmk:
24150 case VPMINUBZ256rmkz:
24151 case VPMINUBZ256rr:
24152 case VPMINUBZ256rrk:
24153 case VPMINUBZ256rrkz:
24154 case VPMINUBZrm:
24155 case VPMINUBZrmk:
24156 case VPMINUBZrmkz:
24157 case VPMINUBZrr:
24158 case VPMINUBZrrk:
24159 case VPMINUBZrrkz:
24160 case VPMINUBrm:
24161 case VPMINUBrr:
24162 return true;
24163 }
24164 return false;
24165}
24166
24167bool isKXNORQ(unsigned Opcode) {
24168 return Opcode == KXNORQkk;
24169}
24170
24171bool isFLD(unsigned Opcode) {
24172 switch (Opcode) {
24173 case LD_F32m:
24174 case LD_F64m:
24175 case LD_F80m:
24176 case LD_Frr:
24177 return true;
24178 }
24179 return false;
24180}
24181
24182bool isVSHUFI32X4(unsigned Opcode) {
24183 switch (Opcode) {
24184 case VSHUFI32X4Z256rmbi:
24185 case VSHUFI32X4Z256rmbik:
24186 case VSHUFI32X4Z256rmbikz:
24187 case VSHUFI32X4Z256rmi:
24188 case VSHUFI32X4Z256rmik:
24189 case VSHUFI32X4Z256rmikz:
24190 case VSHUFI32X4Z256rri:
24191 case VSHUFI32X4Z256rrik:
24192 case VSHUFI32X4Z256rrikz:
24193 case VSHUFI32X4Zrmbi:
24194 case VSHUFI32X4Zrmbik:
24195 case VSHUFI32X4Zrmbikz:
24196 case VSHUFI32X4Zrmi:
24197 case VSHUFI32X4Zrmik:
24198 case VSHUFI32X4Zrmikz:
24199 case VSHUFI32X4Zrri:
24200 case VSHUFI32X4Zrrik:
24201 case VSHUFI32X4Zrrikz:
24202 return true;
24203 }
24204 return false;
24205}
24206
24207bool isSAHF(unsigned Opcode) {
24208 return Opcode == SAHF;
24209}
24210
24211bool isPFRSQRT(unsigned Opcode) {
24212 switch (Opcode) {
24213 case PFRSQRTrm:
24214 case PFRSQRTrr:
24215 return true;
24216 }
24217 return false;
24218}
24219
24220bool isSHRD(unsigned Opcode) {
24221 switch (Opcode) {
24222 case SHRD16mrCL:
24223 case SHRD16mrCL_EVEX:
24224 case SHRD16mrCL_ND:
24225 case SHRD16mrCL_NF:
24226 case SHRD16mrCL_NF_ND:
24227 case SHRD16mri8:
24228 case SHRD16mri8_EVEX:
24229 case SHRD16mri8_ND:
24230 case SHRD16mri8_NF:
24231 case SHRD16mri8_NF_ND:
24232 case SHRD16rrCL:
24233 case SHRD16rrCL_EVEX:
24234 case SHRD16rrCL_ND:
24235 case SHRD16rrCL_NF:
24236 case SHRD16rrCL_NF_ND:
24237 case SHRD16rri8:
24238 case SHRD16rri8_EVEX:
24239 case SHRD16rri8_ND:
24240 case SHRD16rri8_NF:
24241 case SHRD16rri8_NF_ND:
24242 case SHRD32mrCL:
24243 case SHRD32mrCL_EVEX:
24244 case SHRD32mrCL_ND:
24245 case SHRD32mrCL_NF:
24246 case SHRD32mrCL_NF_ND:
24247 case SHRD32mri8:
24248 case SHRD32mri8_EVEX:
24249 case SHRD32mri8_ND:
24250 case SHRD32mri8_NF:
24251 case SHRD32mri8_NF_ND:
24252 case SHRD32rrCL:
24253 case SHRD32rrCL_EVEX:
24254 case SHRD32rrCL_ND:
24255 case SHRD32rrCL_NF:
24256 case SHRD32rrCL_NF_ND:
24257 case SHRD32rri8:
24258 case SHRD32rri8_EVEX:
24259 case SHRD32rri8_ND:
24260 case SHRD32rri8_NF:
24261 case SHRD32rri8_NF_ND:
24262 case SHRD64mrCL:
24263 case SHRD64mrCL_EVEX:
24264 case SHRD64mrCL_ND:
24265 case SHRD64mrCL_NF:
24266 case SHRD64mrCL_NF_ND:
24267 case SHRD64mri8:
24268 case SHRD64mri8_EVEX:
24269 case SHRD64mri8_ND:
24270 case SHRD64mri8_NF:
24271 case SHRD64mri8_NF_ND:
24272 case SHRD64rrCL:
24273 case SHRD64rrCL_EVEX:
24274 case SHRD64rrCL_ND:
24275 case SHRD64rrCL_NF:
24276 case SHRD64rrCL_NF_ND:
24277 case SHRD64rri8:
24278 case SHRD64rri8_EVEX:
24279 case SHRD64rri8_ND:
24280 case SHRD64rri8_NF:
24281 case SHRD64rri8_NF_ND:
24282 return true;
24283 }
24284 return false;
24285}
24286
24287bool isSYSEXIT(unsigned Opcode) {
24288 return Opcode == SYSEXIT;
24289}
24290
24291bool isXSAVE64(unsigned Opcode) {
24292 return Opcode == XSAVE64;
24293}
24294
24295bool isVPMAXSD(unsigned Opcode) {
24296 switch (Opcode) {
24297 case VPMAXSDYrm:
24298 case VPMAXSDYrr:
24299 case VPMAXSDZ128rm:
24300 case VPMAXSDZ128rmb:
24301 case VPMAXSDZ128rmbk:
24302 case VPMAXSDZ128rmbkz:
24303 case VPMAXSDZ128rmk:
24304 case VPMAXSDZ128rmkz:
24305 case VPMAXSDZ128rr:
24306 case VPMAXSDZ128rrk:
24307 case VPMAXSDZ128rrkz:
24308 case VPMAXSDZ256rm:
24309 case VPMAXSDZ256rmb:
24310 case VPMAXSDZ256rmbk:
24311 case VPMAXSDZ256rmbkz:
24312 case VPMAXSDZ256rmk:
24313 case VPMAXSDZ256rmkz:
24314 case VPMAXSDZ256rr:
24315 case VPMAXSDZ256rrk:
24316 case VPMAXSDZ256rrkz:
24317 case VPMAXSDZrm:
24318 case VPMAXSDZrmb:
24319 case VPMAXSDZrmbk:
24320 case VPMAXSDZrmbkz:
24321 case VPMAXSDZrmk:
24322 case VPMAXSDZrmkz:
24323 case VPMAXSDZrr:
24324 case VPMAXSDZrrk:
24325 case VPMAXSDZrrkz:
24326 case VPMAXSDrm:
24327 case VPMAXSDrr:
24328 return true;
24329 }
24330 return false;
24331}
24332
24333bool isCVTTSD2SI(unsigned Opcode) {
24334 switch (Opcode) {
24335 case CVTTSD2SI64rm_Int:
24336 case CVTTSD2SI64rr_Int:
24337 case CVTTSD2SIrm_Int:
24338 case CVTTSD2SIrr_Int:
24339 return true;
24340 }
24341 return false;
24342}
24343
24344bool isVCVTTSS2SIS(unsigned Opcode) {
24345 switch (Opcode) {
24346 case VCVTTSS2SI64Srm_Int:
24347 case VCVTTSS2SI64Srr_Int:
24348 case VCVTTSS2SI64Srrb_Int:
24349 case VCVTTSS2SISrm_Int:
24350 case VCVTTSS2SISrr_Int:
24351 case VCVTTSS2SISrrb_Int:
24352 return true;
24353 }
24354 return false;
24355}
24356
24357bool isPMOVMSKB(unsigned Opcode) {
24358 switch (Opcode) {
24359 case MMX_PMOVMSKBrr:
24360 case PMOVMSKBrr:
24361 return true;
24362 }
24363 return false;
24364}
24365
24366bool isVRANGEPS(unsigned Opcode) {
24367 switch (Opcode) {
24368 case VRANGEPSZ128rmbi:
24369 case VRANGEPSZ128rmbik:
24370 case VRANGEPSZ128rmbikz:
24371 case VRANGEPSZ128rmi:
24372 case VRANGEPSZ128rmik:
24373 case VRANGEPSZ128rmikz:
24374 case VRANGEPSZ128rri:
24375 case VRANGEPSZ128rrik:
24376 case VRANGEPSZ128rrikz:
24377 case VRANGEPSZ256rmbi:
24378 case VRANGEPSZ256rmbik:
24379 case VRANGEPSZ256rmbikz:
24380 case VRANGEPSZ256rmi:
24381 case VRANGEPSZ256rmik:
24382 case VRANGEPSZ256rmikz:
24383 case VRANGEPSZ256rri:
24384 case VRANGEPSZ256rrik:
24385 case VRANGEPSZ256rrikz:
24386 case VRANGEPSZrmbi:
24387 case VRANGEPSZrmbik:
24388 case VRANGEPSZrmbikz:
24389 case VRANGEPSZrmi:
24390 case VRANGEPSZrmik:
24391 case VRANGEPSZrmikz:
24392 case VRANGEPSZrri:
24393 case VRANGEPSZrrib:
24394 case VRANGEPSZrribk:
24395 case VRANGEPSZrribkz:
24396 case VRANGEPSZrrik:
24397 case VRANGEPSZrrikz:
24398 return true;
24399 }
24400 return false;
24401}
24402
24403bool isVADDSUBPS(unsigned Opcode) {
24404 switch (Opcode) {
24405 case VADDSUBPSYrm:
24406 case VADDSUBPSYrr:
24407 case VADDSUBPSrm:
24408 case VADDSUBPSrr:
24409 return true;
24410 }
24411 return false;
24412}
24413
24414bool isVBROADCASTI128(unsigned Opcode) {
24415 return Opcode == VBROADCASTI128rm;
24416}
24417
24418bool isPADDUSB(unsigned Opcode) {
24419 switch (Opcode) {
24420 case MMX_PADDUSBrm:
24421 case MMX_PADDUSBrr:
24422 case PADDUSBrm:
24423 case PADDUSBrr:
24424 return true;
24425 }
24426 return false;
24427}
24428
24429bool isENCODEKEY128(unsigned Opcode) {
24430 return Opcode == ENCODEKEY128;
24431}
24432
24433bool isOR(unsigned Opcode) {
24434 switch (Opcode) {
24435 case OR16i16:
24436 case OR16mi:
24437 case OR16mi8:
24438 case OR16mi8_EVEX:
24439 case OR16mi8_ND:
24440 case OR16mi8_NF:
24441 case OR16mi8_NF_ND:
24442 case OR16mi_EVEX:
24443 case OR16mi_ND:
24444 case OR16mi_NF:
24445 case OR16mi_NF_ND:
24446 case OR16mr:
24447 case OR16mr_EVEX:
24448 case OR16mr_ND:
24449 case OR16mr_NF:
24450 case OR16mr_NF_ND:
24451 case OR16ri:
24452 case OR16ri8:
24453 case OR16ri8_EVEX:
24454 case OR16ri8_ND:
24455 case OR16ri8_NF:
24456 case OR16ri8_NF_ND:
24457 case OR16ri_EVEX:
24458 case OR16ri_ND:
24459 case OR16ri_NF:
24460 case OR16ri_NF_ND:
24461 case OR16rm:
24462 case OR16rm_EVEX:
24463 case OR16rm_ND:
24464 case OR16rm_NF:
24465 case OR16rm_NF_ND:
24466 case OR16rr:
24467 case OR16rr_EVEX:
24468 case OR16rr_EVEX_REV:
24469 case OR16rr_ND:
24470 case OR16rr_ND_REV:
24471 case OR16rr_NF:
24472 case OR16rr_NF_ND:
24473 case OR16rr_NF_ND_REV:
24474 case OR16rr_NF_REV:
24475 case OR16rr_REV:
24476 case OR32i32:
24477 case OR32mi:
24478 case OR32mi8:
24479 case OR32mi8_EVEX:
24480 case OR32mi8_ND:
24481 case OR32mi8_NF:
24482 case OR32mi8_NF_ND:
24483 case OR32mi_EVEX:
24484 case OR32mi_ND:
24485 case OR32mi_NF:
24486 case OR32mi_NF_ND:
24487 case OR32mr:
24488 case OR32mr_EVEX:
24489 case OR32mr_ND:
24490 case OR32mr_NF:
24491 case OR32mr_NF_ND:
24492 case OR32ri:
24493 case OR32ri8:
24494 case OR32ri8_EVEX:
24495 case OR32ri8_ND:
24496 case OR32ri8_NF:
24497 case OR32ri8_NF_ND:
24498 case OR32ri_EVEX:
24499 case OR32ri_ND:
24500 case OR32ri_NF:
24501 case OR32ri_NF_ND:
24502 case OR32rm:
24503 case OR32rm_EVEX:
24504 case OR32rm_ND:
24505 case OR32rm_NF:
24506 case OR32rm_NF_ND:
24507 case OR32rr:
24508 case OR32rr_EVEX:
24509 case OR32rr_EVEX_REV:
24510 case OR32rr_ND:
24511 case OR32rr_ND_REV:
24512 case OR32rr_NF:
24513 case OR32rr_NF_ND:
24514 case OR32rr_NF_ND_REV:
24515 case OR32rr_NF_REV:
24516 case OR32rr_REV:
24517 case OR64i32:
24518 case OR64mi32:
24519 case OR64mi32_EVEX:
24520 case OR64mi32_ND:
24521 case OR64mi32_NF:
24522 case OR64mi32_NF_ND:
24523 case OR64mi8:
24524 case OR64mi8_EVEX:
24525 case OR64mi8_ND:
24526 case OR64mi8_NF:
24527 case OR64mi8_NF_ND:
24528 case OR64mr:
24529 case OR64mr_EVEX:
24530 case OR64mr_ND:
24531 case OR64mr_NF:
24532 case OR64mr_NF_ND:
24533 case OR64ri32:
24534 case OR64ri32_EVEX:
24535 case OR64ri32_ND:
24536 case OR64ri32_NF:
24537 case OR64ri32_NF_ND:
24538 case OR64ri8:
24539 case OR64ri8_EVEX:
24540 case OR64ri8_ND:
24541 case OR64ri8_NF:
24542 case OR64ri8_NF_ND:
24543 case OR64rm:
24544 case OR64rm_EVEX:
24545 case OR64rm_ND:
24546 case OR64rm_NF:
24547 case OR64rm_NF_ND:
24548 case OR64rr:
24549 case OR64rr_EVEX:
24550 case OR64rr_EVEX_REV:
24551 case OR64rr_ND:
24552 case OR64rr_ND_REV:
24553 case OR64rr_NF:
24554 case OR64rr_NF_ND:
24555 case OR64rr_NF_ND_REV:
24556 case OR64rr_NF_REV:
24557 case OR64rr_REV:
24558 case OR8i8:
24559 case OR8mi:
24560 case OR8mi8:
24561 case OR8mi_EVEX:
24562 case OR8mi_ND:
24563 case OR8mi_NF:
24564 case OR8mi_NF_ND:
24565 case OR8mr:
24566 case OR8mr_EVEX:
24567 case OR8mr_ND:
24568 case OR8mr_NF:
24569 case OR8mr_NF_ND:
24570 case OR8ri:
24571 case OR8ri8:
24572 case OR8ri_EVEX:
24573 case OR8ri_ND:
24574 case OR8ri_NF:
24575 case OR8ri_NF_ND:
24576 case OR8rm:
24577 case OR8rm_EVEX:
24578 case OR8rm_ND:
24579 case OR8rm_NF:
24580 case OR8rm_NF_ND:
24581 case OR8rr:
24582 case OR8rr_EVEX:
24583 case OR8rr_EVEX_REV:
24584 case OR8rr_ND:
24585 case OR8rr_ND_REV:
24586 case OR8rr_NF:
24587 case OR8rr_NF_ND:
24588 case OR8rr_NF_ND_REV:
24589 case OR8rr_NF_REV:
24590 case OR8rr_REV:
24591 return true;
24592 }
24593 return false;
24594}
24595
24596bool isSTOSW(unsigned Opcode) {
24597 return Opcode == STOSW;
24598}
24599
24600bool isVCVTTPD2UQQS(unsigned Opcode) {
24601 switch (Opcode) {
24602 case VCVTTPD2UQQSZ128rm:
24603 case VCVTTPD2UQQSZ128rmb:
24604 case VCVTTPD2UQQSZ128rmbk:
24605 case VCVTTPD2UQQSZ128rmbkz:
24606 case VCVTTPD2UQQSZ128rmk:
24607 case VCVTTPD2UQQSZ128rmkz:
24608 case VCVTTPD2UQQSZ128rr:
24609 case VCVTTPD2UQQSZ128rrk:
24610 case VCVTTPD2UQQSZ128rrkz:
24611 case VCVTTPD2UQQSZ256rm:
24612 case VCVTTPD2UQQSZ256rmb:
24613 case VCVTTPD2UQQSZ256rmbk:
24614 case VCVTTPD2UQQSZ256rmbkz:
24615 case VCVTTPD2UQQSZ256rmk:
24616 case VCVTTPD2UQQSZ256rmkz:
24617 case VCVTTPD2UQQSZ256rr:
24618 case VCVTTPD2UQQSZ256rrb:
24619 case VCVTTPD2UQQSZ256rrbk:
24620 case VCVTTPD2UQQSZ256rrbkz:
24621 case VCVTTPD2UQQSZ256rrk:
24622 case VCVTTPD2UQQSZ256rrkz:
24623 case VCVTTPD2UQQSZrm:
24624 case VCVTTPD2UQQSZrmb:
24625 case VCVTTPD2UQQSZrmbk:
24626 case VCVTTPD2UQQSZrmbkz:
24627 case VCVTTPD2UQQSZrmk:
24628 case VCVTTPD2UQQSZrmkz:
24629 case VCVTTPD2UQQSZrr:
24630 case VCVTTPD2UQQSZrrb:
24631 case VCVTTPD2UQQSZrrbk:
24632 case VCVTTPD2UQQSZrrbkz:
24633 case VCVTTPD2UQQSZrrk:
24634 case VCVTTPD2UQQSZrrkz:
24635 return true;
24636 }
24637 return false;
24638}
24639
24640bool isPAVGW(unsigned Opcode) {
24641 switch (Opcode) {
24642 case MMX_PAVGWrm:
24643 case MMX_PAVGWrr:
24644 case PAVGWrm:
24645 case PAVGWrr:
24646 return true;
24647 }
24648 return false;
24649}
24650
24651bool isVCVTPD2PH(unsigned Opcode) {
24652 switch (Opcode) {
24653 case VCVTPD2PHZ128rm:
24654 case VCVTPD2PHZ128rmb:
24655 case VCVTPD2PHZ128rmbk:
24656 case VCVTPD2PHZ128rmbkz:
24657 case VCVTPD2PHZ128rmk:
24658 case VCVTPD2PHZ128rmkz:
24659 case VCVTPD2PHZ128rr:
24660 case VCVTPD2PHZ128rrk:
24661 case VCVTPD2PHZ128rrkz:
24662 case VCVTPD2PHZ256rm:
24663 case VCVTPD2PHZ256rmb:
24664 case VCVTPD2PHZ256rmbk:
24665 case VCVTPD2PHZ256rmbkz:
24666 case VCVTPD2PHZ256rmk:
24667 case VCVTPD2PHZ256rmkz:
24668 case VCVTPD2PHZ256rr:
24669 case VCVTPD2PHZ256rrk:
24670 case VCVTPD2PHZ256rrkz:
24671 case VCVTPD2PHZrm:
24672 case VCVTPD2PHZrmb:
24673 case VCVTPD2PHZrmbk:
24674 case VCVTPD2PHZrmbkz:
24675 case VCVTPD2PHZrmk:
24676 case VCVTPD2PHZrmkz:
24677 case VCVTPD2PHZrr:
24678 case VCVTPD2PHZrrb:
24679 case VCVTPD2PHZrrbk:
24680 case VCVTPD2PHZrrbkz:
24681 case VCVTPD2PHZrrk:
24682 case VCVTPD2PHZrrkz:
24683 return true;
24684 }
24685 return false;
24686}
24687
24688bool isSHLX(unsigned Opcode) {
24689 switch (Opcode) {
24690 case SHLX32rm:
24691 case SHLX32rm_EVEX:
24692 case SHLX32rr:
24693 case SHLX32rr_EVEX:
24694 case SHLX64rm:
24695 case SHLX64rm_EVEX:
24696 case SHLX64rr:
24697 case SHLX64rr_EVEX:
24698 return true;
24699 }
24700 return false;
24701}
24702
24703bool isVCVTSH2SD(unsigned Opcode) {
24704 switch (Opcode) {
24705 case VCVTSH2SDZrm_Int:
24706 case VCVTSH2SDZrmk_Int:
24707 case VCVTSH2SDZrmkz_Int:
24708 case VCVTSH2SDZrr_Int:
24709 case VCVTSH2SDZrrb_Int:
24710 case VCVTSH2SDZrrbk_Int:
24711 case VCVTSH2SDZrrbkz_Int:
24712 case VCVTSH2SDZrrk_Int:
24713 case VCVTSH2SDZrrkz_Int:
24714 return true;
24715 }
24716 return false;
24717}
24718
24719bool isVFMADD231SS(unsigned Opcode) {
24720 switch (Opcode) {
24721 case VFMADD231SSZm_Int:
24722 case VFMADD231SSZmk_Int:
24723 case VFMADD231SSZmkz_Int:
24724 case VFMADD231SSZr_Int:
24725 case VFMADD231SSZrb_Int:
24726 case VFMADD231SSZrbk_Int:
24727 case VFMADD231SSZrbkz_Int:
24728 case VFMADD231SSZrk_Int:
24729 case VFMADD231SSZrkz_Int:
24730 case VFMADD231SSm_Int:
24731 case VFMADD231SSr_Int:
24732 return true;
24733 }
24734 return false;
24735}
24736
24737bool isMOVNTSD(unsigned Opcode) {
24738 return Opcode == MOVNTSD;
24739}
24740
24741bool isFLDPI(unsigned Opcode) {
24742 return Opcode == FLDPI;
24743}
24744
24745bool isVCVTUSI2SS(unsigned Opcode) {
24746 switch (Opcode) {
24747 case VCVTUSI2SSZrm_Int:
24748 case VCVTUSI2SSZrr_Int:
24749 case VCVTUSI2SSZrrb_Int:
24750 case VCVTUSI642SSZrm_Int:
24751 case VCVTUSI642SSZrr_Int:
24752 case VCVTUSI642SSZrrb_Int:
24753 return true;
24754 }
24755 return false;
24756}
24757
24758bool isPMOVSXBD(unsigned Opcode) {
24759 switch (Opcode) {
24760 case PMOVSXBDrm:
24761 case PMOVSXBDrr:
24762 return true;
24763 }
24764 return false;
24765}
24766
24767bool isVPRORVQ(unsigned Opcode) {
24768 switch (Opcode) {
24769 case VPRORVQZ128rm:
24770 case VPRORVQZ128rmb:
24771 case VPRORVQZ128rmbk:
24772 case VPRORVQZ128rmbkz:
24773 case VPRORVQZ128rmk:
24774 case VPRORVQZ128rmkz:
24775 case VPRORVQZ128rr:
24776 case VPRORVQZ128rrk:
24777 case VPRORVQZ128rrkz:
24778 case VPRORVQZ256rm:
24779 case VPRORVQZ256rmb:
24780 case VPRORVQZ256rmbk:
24781 case VPRORVQZ256rmbkz:
24782 case VPRORVQZ256rmk:
24783 case VPRORVQZ256rmkz:
24784 case VPRORVQZ256rr:
24785 case VPRORVQZ256rrk:
24786 case VPRORVQZ256rrkz:
24787 case VPRORVQZrm:
24788 case VPRORVQZrmb:
24789 case VPRORVQZrmbk:
24790 case VPRORVQZrmbkz:
24791 case VPRORVQZrmk:
24792 case VPRORVQZrmkz:
24793 case VPRORVQZrr:
24794 case VPRORVQZrrk:
24795 case VPRORVQZrrkz:
24796 return true;
24797 }
24798 return false;
24799}
24800
24801bool isVPERMT2D(unsigned Opcode) {
24802 switch (Opcode) {
24803 case VPERMT2DZ128rm:
24804 case VPERMT2DZ128rmb:
24805 case VPERMT2DZ128rmbk:
24806 case VPERMT2DZ128rmbkz:
24807 case VPERMT2DZ128rmk:
24808 case VPERMT2DZ128rmkz:
24809 case VPERMT2DZ128rr:
24810 case VPERMT2DZ128rrk:
24811 case VPERMT2DZ128rrkz:
24812 case VPERMT2DZ256rm:
24813 case VPERMT2DZ256rmb:
24814 case VPERMT2DZ256rmbk:
24815 case VPERMT2DZ256rmbkz:
24816 case VPERMT2DZ256rmk:
24817 case VPERMT2DZ256rmkz:
24818 case VPERMT2DZ256rr:
24819 case VPERMT2DZ256rrk:
24820 case VPERMT2DZ256rrkz:
24821 case VPERMT2DZrm:
24822 case VPERMT2DZrmb:
24823 case VPERMT2DZrmbk:
24824 case VPERMT2DZrmbkz:
24825 case VPERMT2DZrmk:
24826 case VPERMT2DZrmkz:
24827 case VPERMT2DZrr:
24828 case VPERMT2DZrrk:
24829 case VPERMT2DZrrkz:
24830 return true;
24831 }
24832 return false;
24833}
24834
24835bool isADDSS(unsigned Opcode) {
24836 switch (Opcode) {
24837 case ADDSSrm_Int:
24838 case ADDSSrr_Int:
24839 return true;
24840 }
24841 return false;
24842}
24843
24844bool isAADD(unsigned Opcode) {
24845 switch (Opcode) {
24846 case AADD32mr:
24847 case AADD32mr_EVEX:
24848 case AADD64mr:
24849 case AADD64mr_EVEX:
24850 return true;
24851 }
24852 return false;
24853}
24854
24855bool isVPSRLVW(unsigned Opcode) {
24856 switch (Opcode) {
24857 case VPSRLVWZ128rm:
24858 case VPSRLVWZ128rmk:
24859 case VPSRLVWZ128rmkz:
24860 case VPSRLVWZ128rr:
24861 case VPSRLVWZ128rrk:
24862 case VPSRLVWZ128rrkz:
24863 case VPSRLVWZ256rm:
24864 case VPSRLVWZ256rmk:
24865 case VPSRLVWZ256rmkz:
24866 case VPSRLVWZ256rr:
24867 case VPSRLVWZ256rrk:
24868 case VPSRLVWZ256rrkz:
24869 case VPSRLVWZrm:
24870 case VPSRLVWZrmk:
24871 case VPSRLVWZrmkz:
24872 case VPSRLVWZrr:
24873 case VPSRLVWZrrk:
24874 case VPSRLVWZrrkz:
24875 return true;
24876 }
24877 return false;
24878}
24879
24880bool isVRSQRTPH(unsigned Opcode) {
24881 switch (Opcode) {
24882 case VRSQRTPHZ128m:
24883 case VRSQRTPHZ128mb:
24884 case VRSQRTPHZ128mbk:
24885 case VRSQRTPHZ128mbkz:
24886 case VRSQRTPHZ128mk:
24887 case VRSQRTPHZ128mkz:
24888 case VRSQRTPHZ128r:
24889 case VRSQRTPHZ128rk:
24890 case VRSQRTPHZ128rkz:
24891 case VRSQRTPHZ256m:
24892 case VRSQRTPHZ256mb:
24893 case VRSQRTPHZ256mbk:
24894 case VRSQRTPHZ256mbkz:
24895 case VRSQRTPHZ256mk:
24896 case VRSQRTPHZ256mkz:
24897 case VRSQRTPHZ256r:
24898 case VRSQRTPHZ256rk:
24899 case VRSQRTPHZ256rkz:
24900 case VRSQRTPHZm:
24901 case VRSQRTPHZmb:
24902 case VRSQRTPHZmbk:
24903 case VRSQRTPHZmbkz:
24904 case VRSQRTPHZmk:
24905 case VRSQRTPHZmkz:
24906 case VRSQRTPHZr:
24907 case VRSQRTPHZrk:
24908 case VRSQRTPHZrkz:
24909 return true;
24910 }
24911 return false;
24912}
24913
24914bool isVLDDQU(unsigned Opcode) {
24915 switch (Opcode) {
24916 case VLDDQUYrm:
24917 case VLDDQUrm:
24918 return true;
24919 }
24920 return false;
24921}
24922
24923bool isKMOVD(unsigned Opcode) {
24924 switch (Opcode) {
24925 case KMOVDkk:
24926 case KMOVDkk_EVEX:
24927 case KMOVDkm:
24928 case KMOVDkm_EVEX:
24929 case KMOVDkr:
24930 case KMOVDkr_EVEX:
24931 case KMOVDmk:
24932 case KMOVDmk_EVEX:
24933 case KMOVDrk:
24934 case KMOVDrk_EVEX:
24935 return true;
24936 }
24937 return false;
24938}
24939
24940bool isENCLV(unsigned Opcode) {
24941 return Opcode == ENCLV;
24942}
24943
24944bool isENCLU(unsigned Opcode) {
24945 return Opcode == ENCLU;
24946}
24947
24948bool isPREFETCHT1(unsigned Opcode) {
24949 return Opcode == PREFETCHT1;
24950}
24951
24952bool isRSQRTPS(unsigned Opcode) {
24953 switch (Opcode) {
24954 case RSQRTPSm:
24955 case RSQRTPSr:
24956 return true;
24957 }
24958 return false;
24959}
24960
24961bool isVCVTTSH2USI(unsigned Opcode) {
24962 switch (Opcode) {
24963 case VCVTTSH2USI64Zrm_Int:
24964 case VCVTTSH2USI64Zrr_Int:
24965 case VCVTTSH2USI64Zrrb_Int:
24966 case VCVTTSH2USIZrm_Int:
24967 case VCVTTSH2USIZrr_Int:
24968 case VCVTTSH2USIZrrb_Int:
24969 return true;
24970 }
24971 return false;
24972}
24973
24974bool isPADDB(unsigned Opcode) {
24975 switch (Opcode) {
24976 case MMX_PADDBrm:
24977 case MMX_PADDBrr:
24978 case PADDBrm:
24979 case PADDBrr:
24980 return true;
24981 }
24982 return false;
24983}
24984
24985bool isVMASKMOVDQU(unsigned Opcode) {
24986 return Opcode == VMASKMOVDQU64;
24987}
24988
24989bool isPUNPCKLBW(unsigned Opcode) {
24990 switch (Opcode) {
24991 case MMX_PUNPCKLBWrm:
24992 case MMX_PUNPCKLBWrr:
24993 case PUNPCKLBWrm:
24994 case PUNPCKLBWrr:
24995 return true;
24996 }
24997 return false;
24998}
24999
25000bool isMOV(unsigned Opcode) {
25001 switch (Opcode) {
25002 case MOV16ao16:
25003 case MOV16ao32:
25004 case MOV16mi:
25005 case MOV16mr:
25006 case MOV16ms:
25007 case MOV16o16a:
25008 case MOV16o32a:
25009 case MOV16ri:
25010 case MOV16ri_alt:
25011 case MOV16rm:
25012 case MOV16rr:
25013 case MOV16rr_REV:
25014 case MOV16rs:
25015 case MOV16sm:
25016 case MOV16sr:
25017 case MOV32ao16:
25018 case MOV32ao32:
25019 case MOV32cr:
25020 case MOV32dr:
25021 case MOV32mi:
25022 case MOV32mr:
25023 case MOV32o16a:
25024 case MOV32o32a:
25025 case MOV32rc:
25026 case MOV32rd:
25027 case MOV32ri:
25028 case MOV32ri_alt:
25029 case MOV32rm:
25030 case MOV32rr:
25031 case MOV32rr_REV:
25032 case MOV32rs:
25033 case MOV32sr:
25034 case MOV64ao32:
25035 case MOV64cr:
25036 case MOV64dr:
25037 case MOV64mi32:
25038 case MOV64mr:
25039 case MOV64o32a:
25040 case MOV64rc:
25041 case MOV64rd:
25042 case MOV64ri32:
25043 case MOV64rm:
25044 case MOV64rr:
25045 case MOV64rr_REV:
25046 case MOV64rs:
25047 case MOV64sr:
25048 case MOV8ao16:
25049 case MOV8ao32:
25050 case MOV8mi:
25051 case MOV8mr:
25052 case MOV8o16a:
25053 case MOV8o32a:
25054 case MOV8ri:
25055 case MOV8ri_alt:
25056 case MOV8rm:
25057 case MOV8rr:
25058 case MOV8rr_REV:
25059 return true;
25060 }
25061 return false;
25062}
25063
25064bool isVCVTTPH2IUBS(unsigned Opcode) {
25065 switch (Opcode) {
25066 case VCVTTPH2IUBSZ128rm:
25067 case VCVTTPH2IUBSZ128rmb:
25068 case VCVTTPH2IUBSZ128rmbk:
25069 case VCVTTPH2IUBSZ128rmbkz:
25070 case VCVTTPH2IUBSZ128rmk:
25071 case VCVTTPH2IUBSZ128rmkz:
25072 case VCVTTPH2IUBSZ128rr:
25073 case VCVTTPH2IUBSZ128rrk:
25074 case VCVTTPH2IUBSZ128rrkz:
25075 case VCVTTPH2IUBSZ256rm:
25076 case VCVTTPH2IUBSZ256rmb:
25077 case VCVTTPH2IUBSZ256rmbk:
25078 case VCVTTPH2IUBSZ256rmbkz:
25079 case VCVTTPH2IUBSZ256rmk:
25080 case VCVTTPH2IUBSZ256rmkz:
25081 case VCVTTPH2IUBSZ256rr:
25082 case VCVTTPH2IUBSZ256rrk:
25083 case VCVTTPH2IUBSZ256rrkz:
25084 case VCVTTPH2IUBSZrm:
25085 case VCVTTPH2IUBSZrmb:
25086 case VCVTTPH2IUBSZrmbk:
25087 case VCVTTPH2IUBSZrmbkz:
25088 case VCVTTPH2IUBSZrmk:
25089 case VCVTTPH2IUBSZrmkz:
25090 case VCVTTPH2IUBSZrr:
25091 case VCVTTPH2IUBSZrrb:
25092 case VCVTTPH2IUBSZrrbk:
25093 case VCVTTPH2IUBSZrrbkz:
25094 case VCVTTPH2IUBSZrrk:
25095 case VCVTTPH2IUBSZrrkz:
25096 return true;
25097 }
25098 return false;
25099}
25100
25101bool isMUL(unsigned Opcode) {
25102 switch (Opcode) {
25103 case MUL16m:
25104 case MUL16m_EVEX:
25105 case MUL16m_NF:
25106 case MUL16r:
25107 case MUL16r_EVEX:
25108 case MUL16r_NF:
25109 case MUL32m:
25110 case MUL32m_EVEX:
25111 case MUL32m_NF:
25112 case MUL32r:
25113 case MUL32r_EVEX:
25114 case MUL32r_NF:
25115 case MUL64m:
25116 case MUL64m_EVEX:
25117 case MUL64m_NF:
25118 case MUL64r:
25119 case MUL64r_EVEX:
25120 case MUL64r_NF:
25121 case MUL8m:
25122 case MUL8m_EVEX:
25123 case MUL8m_NF:
25124 case MUL8r:
25125 case MUL8r_EVEX:
25126 case MUL8r_NF:
25127 return true;
25128 }
25129 return false;
25130}
25131
25132bool isRCL(unsigned Opcode) {
25133 switch (Opcode) {
25134 case RCL16m1:
25135 case RCL16m1_EVEX:
25136 case RCL16m1_ND:
25137 case RCL16mCL:
25138 case RCL16mCL_EVEX:
25139 case RCL16mCL_ND:
25140 case RCL16mi:
25141 case RCL16mi_EVEX:
25142 case RCL16mi_ND:
25143 case RCL16r1:
25144 case RCL16r1_EVEX:
25145 case RCL16r1_ND:
25146 case RCL16rCL:
25147 case RCL16rCL_EVEX:
25148 case RCL16rCL_ND:
25149 case RCL16ri:
25150 case RCL16ri_EVEX:
25151 case RCL16ri_ND:
25152 case RCL32m1:
25153 case RCL32m1_EVEX:
25154 case RCL32m1_ND:
25155 case RCL32mCL:
25156 case RCL32mCL_EVEX:
25157 case RCL32mCL_ND:
25158 case RCL32mi:
25159 case RCL32mi_EVEX:
25160 case RCL32mi_ND:
25161 case RCL32r1:
25162 case RCL32r1_EVEX:
25163 case RCL32r1_ND:
25164 case RCL32rCL:
25165 case RCL32rCL_EVEX:
25166 case RCL32rCL_ND:
25167 case RCL32ri:
25168 case RCL32ri_EVEX:
25169 case RCL32ri_ND:
25170 case RCL64m1:
25171 case RCL64m1_EVEX:
25172 case RCL64m1_ND:
25173 case RCL64mCL:
25174 case RCL64mCL_EVEX:
25175 case RCL64mCL_ND:
25176 case RCL64mi:
25177 case RCL64mi_EVEX:
25178 case RCL64mi_ND:
25179 case RCL64r1:
25180 case RCL64r1_EVEX:
25181 case RCL64r1_ND:
25182 case RCL64rCL:
25183 case RCL64rCL_EVEX:
25184 case RCL64rCL_ND:
25185 case RCL64ri:
25186 case RCL64ri_EVEX:
25187 case RCL64ri_ND:
25188 case RCL8m1:
25189 case RCL8m1_EVEX:
25190 case RCL8m1_ND:
25191 case RCL8mCL:
25192 case RCL8mCL_EVEX:
25193 case RCL8mCL_ND:
25194 case RCL8mi:
25195 case RCL8mi_EVEX:
25196 case RCL8mi_ND:
25197 case RCL8r1:
25198 case RCL8r1_EVEX:
25199 case RCL8r1_ND:
25200 case RCL8rCL:
25201 case RCL8rCL_EVEX:
25202 case RCL8rCL_ND:
25203 case RCL8ri:
25204 case RCL8ri_EVEX:
25205 case RCL8ri_ND:
25206 return true;
25207 }
25208 return false;
25209}
25210
25211bool isVRCPSH(unsigned Opcode) {
25212 switch (Opcode) {
25213 case VRCPSHZrm:
25214 case VRCPSHZrmk:
25215 case VRCPSHZrmkz:
25216 case VRCPSHZrr:
25217 case VRCPSHZrrk:
25218 case VRCPSHZrrkz:
25219 return true;
25220 }
25221 return false;
25222}
25223
25224bool isPFCMPEQ(unsigned Opcode) {
25225 switch (Opcode) {
25226 case PFCMPEQrm:
25227 case PFCMPEQrr:
25228 return true;
25229 }
25230 return false;
25231}
25232
25233bool isMONITOR(unsigned Opcode) {
25234 switch (Opcode) {
25235 case MONITOR32rrr:
25236 case MONITOR64rrr:
25237 return true;
25238 }
25239 return false;
25240}
25241
25242bool isFDIVR(unsigned Opcode) {
25243 switch (Opcode) {
25244 case DIVR_F32m:
25245 case DIVR_F64m:
25246 case DIVR_FST0r:
25247 case DIVR_FrST0:
25248 return true;
25249 }
25250 return false;
25251}
25252
25253bool isPFRCP(unsigned Opcode) {
25254 switch (Opcode) {
25255 case PFRCPrm:
25256 case PFRCPrr:
25257 return true;
25258 }
25259 return false;
25260}
25261
25262bool isPMINSD(unsigned Opcode) {
25263 switch (Opcode) {
25264 case PMINSDrm:
25265 case PMINSDrr:
25266 return true;
25267 }
25268 return false;
25269}
25270
25271bool isVSHUFF32X4(unsigned Opcode) {
25272 switch (Opcode) {
25273 case VSHUFF32X4Z256rmbi:
25274 case VSHUFF32X4Z256rmbik:
25275 case VSHUFF32X4Z256rmbikz:
25276 case VSHUFF32X4Z256rmi:
25277 case VSHUFF32X4Z256rmik:
25278 case VSHUFF32X4Z256rmikz:
25279 case VSHUFF32X4Z256rri:
25280 case VSHUFF32X4Z256rrik:
25281 case VSHUFF32X4Z256rrikz:
25282 case VSHUFF32X4Zrmbi:
25283 case VSHUFF32X4Zrmbik:
25284 case VSHUFF32X4Zrmbikz:
25285 case VSHUFF32X4Zrmi:
25286 case VSHUFF32X4Zrmik:
25287 case VSHUFF32X4Zrmikz:
25288 case VSHUFF32X4Zrri:
25289 case VSHUFF32X4Zrrik:
25290 case VSHUFF32X4Zrrikz:
25291 return true;
25292 }
25293 return false;
25294}
25295
25296bool isKTESTQ(unsigned Opcode) {
25297 return Opcode == KTESTQkk;
25298}
25299
25300bool isVCVTTPD2DQ(unsigned Opcode) {
25301 switch (Opcode) {
25302 case VCVTTPD2DQYrm:
25303 case VCVTTPD2DQYrr:
25304 case VCVTTPD2DQZ128rm:
25305 case VCVTTPD2DQZ128rmb:
25306 case VCVTTPD2DQZ128rmbk:
25307 case VCVTTPD2DQZ128rmbkz:
25308 case VCVTTPD2DQZ128rmk:
25309 case VCVTTPD2DQZ128rmkz:
25310 case VCVTTPD2DQZ128rr:
25311 case VCVTTPD2DQZ128rrk:
25312 case VCVTTPD2DQZ128rrkz:
25313 case VCVTTPD2DQZ256rm:
25314 case VCVTTPD2DQZ256rmb:
25315 case VCVTTPD2DQZ256rmbk:
25316 case VCVTTPD2DQZ256rmbkz:
25317 case VCVTTPD2DQZ256rmk:
25318 case VCVTTPD2DQZ256rmkz:
25319 case VCVTTPD2DQZ256rr:
25320 case VCVTTPD2DQZ256rrk:
25321 case VCVTTPD2DQZ256rrkz:
25322 case VCVTTPD2DQZrm:
25323 case VCVTTPD2DQZrmb:
25324 case VCVTTPD2DQZrmbk:
25325 case VCVTTPD2DQZrmbkz:
25326 case VCVTTPD2DQZrmk:
25327 case VCVTTPD2DQZrmkz:
25328 case VCVTTPD2DQZrr:
25329 case VCVTTPD2DQZrrb:
25330 case VCVTTPD2DQZrrbk:
25331 case VCVTTPD2DQZrrbkz:
25332 case VCVTTPD2DQZrrk:
25333 case VCVTTPD2DQZrrkz:
25334 case VCVTTPD2DQrm:
25335 case VCVTTPD2DQrr:
25336 return true;
25337 }
25338 return false;
25339}
25340
25341bool isVPSLLVW(unsigned Opcode) {
25342 switch (Opcode) {
25343 case VPSLLVWZ128rm:
25344 case VPSLLVWZ128rmk:
25345 case VPSLLVWZ128rmkz:
25346 case VPSLLVWZ128rr:
25347 case VPSLLVWZ128rrk:
25348 case VPSLLVWZ128rrkz:
25349 case VPSLLVWZ256rm:
25350 case VPSLLVWZ256rmk:
25351 case VPSLLVWZ256rmkz:
25352 case VPSLLVWZ256rr:
25353 case VPSLLVWZ256rrk:
25354 case VPSLLVWZ256rrkz:
25355 case VPSLLVWZrm:
25356 case VPSLLVWZrmk:
25357 case VPSLLVWZrmkz:
25358 case VPSLLVWZrr:
25359 case VPSLLVWZrrk:
25360 case VPSLLVWZrrkz:
25361 return true;
25362 }
25363 return false;
25364}
25365
25366bool isTDPBSUD(unsigned Opcode) {
25367 return Opcode == TDPBSUD;
25368}
25369
25370bool isVPMINUQ(unsigned Opcode) {
25371 switch (Opcode) {
25372 case VPMINUQZ128rm:
25373 case VPMINUQZ128rmb:
25374 case VPMINUQZ128rmbk:
25375 case VPMINUQZ128rmbkz:
25376 case VPMINUQZ128rmk:
25377 case VPMINUQZ128rmkz:
25378 case VPMINUQZ128rr:
25379 case VPMINUQZ128rrk:
25380 case VPMINUQZ128rrkz:
25381 case VPMINUQZ256rm:
25382 case VPMINUQZ256rmb:
25383 case VPMINUQZ256rmbk:
25384 case VPMINUQZ256rmbkz:
25385 case VPMINUQZ256rmk:
25386 case VPMINUQZ256rmkz:
25387 case VPMINUQZ256rr:
25388 case VPMINUQZ256rrk:
25389 case VPMINUQZ256rrkz:
25390 case VPMINUQZrm:
25391 case VPMINUQZrmb:
25392 case VPMINUQZrmbk:
25393 case VPMINUQZrmbkz:
25394 case VPMINUQZrmk:
25395 case VPMINUQZrmkz:
25396 case VPMINUQZrr:
25397 case VPMINUQZrrk:
25398 case VPMINUQZrrkz:
25399 return true;
25400 }
25401 return false;
25402}
25403
25404bool isFIADD(unsigned Opcode) {
25405 switch (Opcode) {
25406 case ADD_FI16m:
25407 case ADD_FI32m:
25408 return true;
25409 }
25410 return false;
25411}
25412
25413bool isFCMOVNU(unsigned Opcode) {
25414 return Opcode == CMOVNP_F;
25415}
25416
25417bool isVHSUBPD(unsigned Opcode) {
25418 switch (Opcode) {
25419 case VHSUBPDYrm:
25420 case VHSUBPDYrr:
25421 case VHSUBPDrm:
25422 case VHSUBPDrr:
25423 return true;
25424 }
25425 return false;
25426}
25427
25428bool isKSHIFTRQ(unsigned Opcode) {
25429 return Opcode == KSHIFTRQki;
25430}
25431
25432bool isMOVUPS(unsigned Opcode) {
25433 switch (Opcode) {
25434 case MOVUPSmr:
25435 case MOVUPSrm:
25436 case MOVUPSrr:
25437 case MOVUPSrr_REV:
25438 return true;
25439 }
25440 return false;
25441}
25442
25443bool isVMCALL(unsigned Opcode) {
25444 return Opcode == VMCALL;
25445}
25446
25447bool isXADD(unsigned Opcode) {
25448 switch (Opcode) {
25449 case XADD16rm:
25450 case XADD16rr:
25451 case XADD32rm:
25452 case XADD32rr:
25453 case XADD64rm:
25454 case XADD64rr:
25455 case XADD8rm:
25456 case XADD8rr:
25457 return true;
25458 }
25459 return false;
25460}
25461
25462bool isXRSTOR(unsigned Opcode) {
25463 return Opcode == XRSTOR;
25464}
25465
25466bool isVGATHERPF1DPD(unsigned Opcode) {
25467 return Opcode == VGATHERPF1DPDm;
25468}
25469
25470bool isRCR(unsigned Opcode) {
25471 switch (Opcode) {
25472 case RCR16m1:
25473 case RCR16m1_EVEX:
25474 case RCR16m1_ND:
25475 case RCR16mCL:
25476 case RCR16mCL_EVEX:
25477 case RCR16mCL_ND:
25478 case RCR16mi:
25479 case RCR16mi_EVEX:
25480 case RCR16mi_ND:
25481 case RCR16r1:
25482 case RCR16r1_EVEX:
25483 case RCR16r1_ND:
25484 case RCR16rCL:
25485 case RCR16rCL_EVEX:
25486 case RCR16rCL_ND:
25487 case RCR16ri:
25488 case RCR16ri_EVEX:
25489 case RCR16ri_ND:
25490 case RCR32m1:
25491 case RCR32m1_EVEX:
25492 case RCR32m1_ND:
25493 case RCR32mCL:
25494 case RCR32mCL_EVEX:
25495 case RCR32mCL_ND:
25496 case RCR32mi:
25497 case RCR32mi_EVEX:
25498 case RCR32mi_ND:
25499 case RCR32r1:
25500 case RCR32r1_EVEX:
25501 case RCR32r1_ND:
25502 case RCR32rCL:
25503 case RCR32rCL_EVEX:
25504 case RCR32rCL_ND:
25505 case RCR32ri:
25506 case RCR32ri_EVEX:
25507 case RCR32ri_ND:
25508 case RCR64m1:
25509 case RCR64m1_EVEX:
25510 case RCR64m1_ND:
25511 case RCR64mCL:
25512 case RCR64mCL_EVEX:
25513 case RCR64mCL_ND:
25514 case RCR64mi:
25515 case RCR64mi_EVEX:
25516 case RCR64mi_ND:
25517 case RCR64r1:
25518 case RCR64r1_EVEX:
25519 case RCR64r1_ND:
25520 case RCR64rCL:
25521 case RCR64rCL_EVEX:
25522 case RCR64rCL_ND:
25523 case RCR64ri:
25524 case RCR64ri_EVEX:
25525 case RCR64ri_ND:
25526 case RCR8m1:
25527 case RCR8m1_EVEX:
25528 case RCR8m1_ND:
25529 case RCR8mCL:
25530 case RCR8mCL_EVEX:
25531 case RCR8mCL_ND:
25532 case RCR8mi:
25533 case RCR8mi_EVEX:
25534 case RCR8mi_ND:
25535 case RCR8r1:
25536 case RCR8r1_EVEX:
25537 case RCR8r1_ND:
25538 case RCR8rCL:
25539 case RCR8rCL_EVEX:
25540 case RCR8rCL_ND:
25541 case RCR8ri:
25542 case RCR8ri_EVEX:
25543 case RCR8ri_ND:
25544 return true;
25545 }
25546 return false;
25547}
25548
25549bool isFNSTCW(unsigned Opcode) {
25550 return Opcode == FNSTCW16m;
25551}
25552
25553bool isVPMOVSDW(unsigned Opcode) {
25554 switch (Opcode) {
25555 case VPMOVSDWZ128mr:
25556 case VPMOVSDWZ128mrk:
25557 case VPMOVSDWZ128rr:
25558 case VPMOVSDWZ128rrk:
25559 case VPMOVSDWZ128rrkz:
25560 case VPMOVSDWZ256mr:
25561 case VPMOVSDWZ256mrk:
25562 case VPMOVSDWZ256rr:
25563 case VPMOVSDWZ256rrk:
25564 case VPMOVSDWZ256rrkz:
25565 case VPMOVSDWZmr:
25566 case VPMOVSDWZmrk:
25567 case VPMOVSDWZrr:
25568 case VPMOVSDWZrrk:
25569 case VPMOVSDWZrrkz:
25570 return true;
25571 }
25572 return false;
25573}
25574
25575bool isVFMSUB132SH(unsigned Opcode) {
25576 switch (Opcode) {
25577 case VFMSUB132SHZm_Int:
25578 case VFMSUB132SHZmk_Int:
25579 case VFMSUB132SHZmkz_Int:
25580 case VFMSUB132SHZr_Int:
25581 case VFMSUB132SHZrb_Int:
25582 case VFMSUB132SHZrbk_Int:
25583 case VFMSUB132SHZrbkz_Int:
25584 case VFMSUB132SHZrk_Int:
25585 case VFMSUB132SHZrkz_Int:
25586 return true;
25587 }
25588 return false;
25589}
25590
25591bool isVPCONFLICTQ(unsigned Opcode) {
25592 switch (Opcode) {
25593 case VPCONFLICTQZ128rm:
25594 case VPCONFLICTQZ128rmb:
25595 case VPCONFLICTQZ128rmbk:
25596 case VPCONFLICTQZ128rmbkz:
25597 case VPCONFLICTQZ128rmk:
25598 case VPCONFLICTQZ128rmkz:
25599 case VPCONFLICTQZ128rr:
25600 case VPCONFLICTQZ128rrk:
25601 case VPCONFLICTQZ128rrkz:
25602 case VPCONFLICTQZ256rm:
25603 case VPCONFLICTQZ256rmb:
25604 case VPCONFLICTQZ256rmbk:
25605 case VPCONFLICTQZ256rmbkz:
25606 case VPCONFLICTQZ256rmk:
25607 case VPCONFLICTQZ256rmkz:
25608 case VPCONFLICTQZ256rr:
25609 case VPCONFLICTQZ256rrk:
25610 case VPCONFLICTQZ256rrkz:
25611 case VPCONFLICTQZrm:
25612 case VPCONFLICTQZrmb:
25613 case VPCONFLICTQZrmbk:
25614 case VPCONFLICTQZrmbkz:
25615 case VPCONFLICTQZrmk:
25616 case VPCONFLICTQZrmkz:
25617 case VPCONFLICTQZrr:
25618 case VPCONFLICTQZrrk:
25619 case VPCONFLICTQZrrkz:
25620 return true;
25621 }
25622 return false;
25623}
25624
25625bool isSWAPGS(unsigned Opcode) {
25626 return Opcode == SWAPGS;
25627}
25628
25629bool isVPMOVQ2M(unsigned Opcode) {
25630 switch (Opcode) {
25631 case VPMOVQ2MZ128kr:
25632 case VPMOVQ2MZ256kr:
25633 case VPMOVQ2MZkr:
25634 return true;
25635 }
25636 return false;
25637}
25638
25639bool isVPSRAVW(unsigned Opcode) {
25640 switch (Opcode) {
25641 case VPSRAVWZ128rm:
25642 case VPSRAVWZ128rmk:
25643 case VPSRAVWZ128rmkz:
25644 case VPSRAVWZ128rr:
25645 case VPSRAVWZ128rrk:
25646 case VPSRAVWZ128rrkz:
25647 case VPSRAVWZ256rm:
25648 case VPSRAVWZ256rmk:
25649 case VPSRAVWZ256rmkz:
25650 case VPSRAVWZ256rr:
25651 case VPSRAVWZ256rrk:
25652 case VPSRAVWZ256rrkz:
25653 case VPSRAVWZrm:
25654 case VPSRAVWZrmk:
25655 case VPSRAVWZrmkz:
25656 case VPSRAVWZrr:
25657 case VPSRAVWZrrk:
25658 case VPSRAVWZrrkz:
25659 return true;
25660 }
25661 return false;
25662}
25663
25664bool isSHA256MSG2(unsigned Opcode) {
25665 switch (Opcode) {
25666 case SHA256MSG2rm:
25667 case SHA256MSG2rr:
25668 return true;
25669 }
25670 return false;
25671}
25672
25673bool isDIVSD(unsigned Opcode) {
25674 switch (Opcode) {
25675 case DIVSDrm_Int:
25676 case DIVSDrr_Int:
25677 return true;
25678 }
25679 return false;
25680}
25681
25682bool isPCMPGTB(unsigned Opcode) {
25683 switch (Opcode) {
25684 case MMX_PCMPGTBrm:
25685 case MMX_PCMPGTBrr:
25686 case PCMPGTBrm:
25687 case PCMPGTBrr:
25688 return true;
25689 }
25690 return false;
25691}
25692
25693bool isMOVDQA(unsigned Opcode) {
25694 switch (Opcode) {
25695 case MOVDQAmr:
25696 case MOVDQArm:
25697 case MOVDQArr:
25698 case MOVDQArr_REV:
25699 return true;
25700 }
25701 return false;
25702}
25703
25704bool isVAESENCLAST(unsigned Opcode) {
25705 switch (Opcode) {
25706 case VAESENCLASTYrm:
25707 case VAESENCLASTYrr:
25708 case VAESENCLASTZ128rm:
25709 case VAESENCLASTZ128rr:
25710 case VAESENCLASTZ256rm:
25711 case VAESENCLASTZ256rr:
25712 case VAESENCLASTZrm:
25713 case VAESENCLASTZrr:
25714 case VAESENCLASTrm:
25715 case VAESENCLASTrr:
25716 return true;
25717 }
25718 return false;
25719}
25720
25721bool isKXORW(unsigned Opcode) {
25722 return Opcode == KXORWkk;
25723}
25724
25725bool isLIDTW(unsigned Opcode) {
25726 return Opcode == LIDT16m;
25727}
25728
25729bool isPMULHW(unsigned Opcode) {
25730 switch (Opcode) {
25731 case MMX_PMULHWrm:
25732 case MMX_PMULHWrr:
25733 case PMULHWrm:
25734 case PMULHWrr:
25735 return true;
25736 }
25737 return false;
25738}
25739
25740bool isVINSERTI32X8(unsigned Opcode) {
25741 switch (Opcode) {
25742 case VINSERTI32X8Zrmi:
25743 case VINSERTI32X8Zrmik:
25744 case VINSERTI32X8Zrmikz:
25745 case VINSERTI32X8Zrri:
25746 case VINSERTI32X8Zrrik:
25747 case VINSERTI32X8Zrrikz:
25748 return true;
25749 }
25750 return false;
25751}
25752
25753bool isVRCPPS(unsigned Opcode) {
25754 switch (Opcode) {
25755 case VRCPPSYm:
25756 case VRCPPSYr:
25757 case VRCPPSm:
25758 case VRCPPSr:
25759 return true;
25760 }
25761 return false;
25762}
25763
25764bool isVRSQRTBF16(unsigned Opcode) {
25765 switch (Opcode) {
25766 case VRSQRTBF16Z128m:
25767 case VRSQRTBF16Z128mb:
25768 case VRSQRTBF16Z128mbk:
25769 case VRSQRTBF16Z128mbkz:
25770 case VRSQRTBF16Z128mk:
25771 case VRSQRTBF16Z128mkz:
25772 case VRSQRTBF16Z128r:
25773 case VRSQRTBF16Z128rk:
25774 case VRSQRTBF16Z128rkz:
25775 case VRSQRTBF16Z256m:
25776 case VRSQRTBF16Z256mb:
25777 case VRSQRTBF16Z256mbk:
25778 case VRSQRTBF16Z256mbkz:
25779 case VRSQRTBF16Z256mk:
25780 case VRSQRTBF16Z256mkz:
25781 case VRSQRTBF16Z256r:
25782 case VRSQRTBF16Z256rk:
25783 case VRSQRTBF16Z256rkz:
25784 case VRSQRTBF16Zm:
25785 case VRSQRTBF16Zmb:
25786 case VRSQRTBF16Zmbk:
25787 case VRSQRTBF16Zmbkz:
25788 case VRSQRTBF16Zmk:
25789 case VRSQRTBF16Zmkz:
25790 case VRSQRTBF16Zr:
25791 case VRSQRTBF16Zrk:
25792 case VRSQRTBF16Zrkz:
25793 return true;
25794 }
25795 return false;
25796}
25797
25798bool isVGATHERQPS(unsigned Opcode) {
25799 switch (Opcode) {
25800 case VGATHERQPSYrm:
25801 case VGATHERQPSZ128rm:
25802 case VGATHERQPSZ256rm:
25803 case VGATHERQPSZrm:
25804 case VGATHERQPSrm:
25805 return true;
25806 }
25807 return false;
25808}
25809
25810bool isCTESTCC(unsigned Opcode) {
25811 switch (Opcode) {
25812 case CTEST16mi:
25813 case CTEST16mr:
25814 case CTEST16ri:
25815 case CTEST16rr:
25816 case CTEST32mi:
25817 case CTEST32mr:
25818 case CTEST32ri:
25819 case CTEST32rr:
25820 case CTEST64mi32:
25821 case CTEST64mr:
25822 case CTEST64ri32:
25823 case CTEST64rr:
25824 case CTEST8mi:
25825 case CTEST8mr:
25826 case CTEST8ri:
25827 case CTEST8rr:
25828 return true;
25829 }
25830 return false;
25831}
25832
25833bool isPMADDWD(unsigned Opcode) {
25834 switch (Opcode) {
25835 case MMX_PMADDWDrm:
25836 case MMX_PMADDWDrr:
25837 case PMADDWDrm:
25838 case PMADDWDrr:
25839 return true;
25840 }
25841 return false;
25842}
25843
25844bool isUCOMISS(unsigned Opcode) {
25845 switch (Opcode) {
25846 case UCOMISSrm:
25847 case UCOMISSrr:
25848 return true;
25849 }
25850 return false;
25851}
25852
25853bool isXGETBV(unsigned Opcode) {
25854 return Opcode == XGETBV;
25855}
25856
25857bool isVCVTPD2QQ(unsigned Opcode) {
25858 switch (Opcode) {
25859 case VCVTPD2QQZ128rm:
25860 case VCVTPD2QQZ128rmb:
25861 case VCVTPD2QQZ128rmbk:
25862 case VCVTPD2QQZ128rmbkz:
25863 case VCVTPD2QQZ128rmk:
25864 case VCVTPD2QQZ128rmkz:
25865 case VCVTPD2QQZ128rr:
25866 case VCVTPD2QQZ128rrk:
25867 case VCVTPD2QQZ128rrkz:
25868 case VCVTPD2QQZ256rm:
25869 case VCVTPD2QQZ256rmb:
25870 case VCVTPD2QQZ256rmbk:
25871 case VCVTPD2QQZ256rmbkz:
25872 case VCVTPD2QQZ256rmk:
25873 case VCVTPD2QQZ256rmkz:
25874 case VCVTPD2QQZ256rr:
25875 case VCVTPD2QQZ256rrk:
25876 case VCVTPD2QQZ256rrkz:
25877 case VCVTPD2QQZrm:
25878 case VCVTPD2QQZrmb:
25879 case VCVTPD2QQZrmbk:
25880 case VCVTPD2QQZrmbkz:
25881 case VCVTPD2QQZrmk:
25882 case VCVTPD2QQZrmkz:
25883 case VCVTPD2QQZrr:
25884 case VCVTPD2QQZrrb:
25885 case VCVTPD2QQZrrbk:
25886 case VCVTPD2QQZrrbkz:
25887 case VCVTPD2QQZrrk:
25888 case VCVTPD2QQZrrkz:
25889 return true;
25890 }
25891 return false;
25892}
25893
25894bool isVGETEXPPS(unsigned Opcode) {
25895 switch (Opcode) {
25896 case VGETEXPPSZ128m:
25897 case VGETEXPPSZ128mb:
25898 case VGETEXPPSZ128mbk:
25899 case VGETEXPPSZ128mbkz:
25900 case VGETEXPPSZ128mk:
25901 case VGETEXPPSZ128mkz:
25902 case VGETEXPPSZ128r:
25903 case VGETEXPPSZ128rk:
25904 case VGETEXPPSZ128rkz:
25905 case VGETEXPPSZ256m:
25906 case VGETEXPPSZ256mb:
25907 case VGETEXPPSZ256mbk:
25908 case VGETEXPPSZ256mbkz:
25909 case VGETEXPPSZ256mk:
25910 case VGETEXPPSZ256mkz:
25911 case VGETEXPPSZ256r:
25912 case VGETEXPPSZ256rk:
25913 case VGETEXPPSZ256rkz:
25914 case VGETEXPPSZm:
25915 case VGETEXPPSZmb:
25916 case VGETEXPPSZmbk:
25917 case VGETEXPPSZmbkz:
25918 case VGETEXPPSZmk:
25919 case VGETEXPPSZmkz:
25920 case VGETEXPPSZr:
25921 case VGETEXPPSZrb:
25922 case VGETEXPPSZrbk:
25923 case VGETEXPPSZrbkz:
25924 case VGETEXPPSZrk:
25925 case VGETEXPPSZrkz:
25926 return true;
25927 }
25928 return false;
25929}
25930
25931bool isFISTP(unsigned Opcode) {
25932 switch (Opcode) {
25933 case IST_FP16m:
25934 case IST_FP32m:
25935 case IST_FP64m:
25936 return true;
25937 }
25938 return false;
25939}
25940
25941bool isVINSERTF64X4(unsigned Opcode) {
25942 switch (Opcode) {
25943 case VINSERTF64X4Zrmi:
25944 case VINSERTF64X4Zrmik:
25945 case VINSERTF64X4Zrmikz:
25946 case VINSERTF64X4Zrri:
25947 case VINSERTF64X4Zrrik:
25948 case VINSERTF64X4Zrrikz:
25949 return true;
25950 }
25951 return false;
25952}
25953
25954bool isVMOVDQU16(unsigned Opcode) {
25955 switch (Opcode) {
25956 case VMOVDQU16Z128mr:
25957 case VMOVDQU16Z128mrk:
25958 case VMOVDQU16Z128rm:
25959 case VMOVDQU16Z128rmk:
25960 case VMOVDQU16Z128rmkz:
25961 case VMOVDQU16Z128rr:
25962 case VMOVDQU16Z128rr_REV:
25963 case VMOVDQU16Z128rrk:
25964 case VMOVDQU16Z128rrk_REV:
25965 case VMOVDQU16Z128rrkz:
25966 case VMOVDQU16Z128rrkz_REV:
25967 case VMOVDQU16Z256mr:
25968 case VMOVDQU16Z256mrk:
25969 case VMOVDQU16Z256rm:
25970 case VMOVDQU16Z256rmk:
25971 case VMOVDQU16Z256rmkz:
25972 case VMOVDQU16Z256rr:
25973 case VMOVDQU16Z256rr_REV:
25974 case VMOVDQU16Z256rrk:
25975 case VMOVDQU16Z256rrk_REV:
25976 case VMOVDQU16Z256rrkz:
25977 case VMOVDQU16Z256rrkz_REV:
25978 case VMOVDQU16Zmr:
25979 case VMOVDQU16Zmrk:
25980 case VMOVDQU16Zrm:
25981 case VMOVDQU16Zrmk:
25982 case VMOVDQU16Zrmkz:
25983 case VMOVDQU16Zrr:
25984 case VMOVDQU16Zrr_REV:
25985 case VMOVDQU16Zrrk:
25986 case VMOVDQU16Zrrk_REV:
25987 case VMOVDQU16Zrrkz:
25988 case VMOVDQU16Zrrkz_REV:
25989 return true;
25990 }
25991 return false;
25992}
25993
25994bool isVFMADD132PH(unsigned Opcode) {
25995 switch (Opcode) {
25996 case VFMADD132PHZ128m:
25997 case VFMADD132PHZ128mb:
25998 case VFMADD132PHZ128mbk:
25999 case VFMADD132PHZ128mbkz:
26000 case VFMADD132PHZ128mk:
26001 case VFMADD132PHZ128mkz:
26002 case VFMADD132PHZ128r:
26003 case VFMADD132PHZ128rk:
26004 case VFMADD132PHZ128rkz:
26005 case VFMADD132PHZ256m:
26006 case VFMADD132PHZ256mb:
26007 case VFMADD132PHZ256mbk:
26008 case VFMADD132PHZ256mbkz:
26009 case VFMADD132PHZ256mk:
26010 case VFMADD132PHZ256mkz:
26011 case VFMADD132PHZ256r:
26012 case VFMADD132PHZ256rk:
26013 case VFMADD132PHZ256rkz:
26014 case VFMADD132PHZm:
26015 case VFMADD132PHZmb:
26016 case VFMADD132PHZmbk:
26017 case VFMADD132PHZmbkz:
26018 case VFMADD132PHZmk:
26019 case VFMADD132PHZmkz:
26020 case VFMADD132PHZr:
26021 case VFMADD132PHZrb:
26022 case VFMADD132PHZrbk:
26023 case VFMADD132PHZrbkz:
26024 case VFMADD132PHZrk:
26025 case VFMADD132PHZrkz:
26026 return true;
26027 }
26028 return false;
26029}
26030
26031bool isVFMSUBADD213PS(unsigned Opcode) {
26032 switch (Opcode) {
26033 case VFMSUBADD213PSYm:
26034 case VFMSUBADD213PSYr:
26035 case VFMSUBADD213PSZ128m:
26036 case VFMSUBADD213PSZ128mb:
26037 case VFMSUBADD213PSZ128mbk:
26038 case VFMSUBADD213PSZ128mbkz:
26039 case VFMSUBADD213PSZ128mk:
26040 case VFMSUBADD213PSZ128mkz:
26041 case VFMSUBADD213PSZ128r:
26042 case VFMSUBADD213PSZ128rk:
26043 case VFMSUBADD213PSZ128rkz:
26044 case VFMSUBADD213PSZ256m:
26045 case VFMSUBADD213PSZ256mb:
26046 case VFMSUBADD213PSZ256mbk:
26047 case VFMSUBADD213PSZ256mbkz:
26048 case VFMSUBADD213PSZ256mk:
26049 case VFMSUBADD213PSZ256mkz:
26050 case VFMSUBADD213PSZ256r:
26051 case VFMSUBADD213PSZ256rk:
26052 case VFMSUBADD213PSZ256rkz:
26053 case VFMSUBADD213PSZm:
26054 case VFMSUBADD213PSZmb:
26055 case VFMSUBADD213PSZmbk:
26056 case VFMSUBADD213PSZmbkz:
26057 case VFMSUBADD213PSZmk:
26058 case VFMSUBADD213PSZmkz:
26059 case VFMSUBADD213PSZr:
26060 case VFMSUBADD213PSZrb:
26061 case VFMSUBADD213PSZrbk:
26062 case VFMSUBADD213PSZrbkz:
26063 case VFMSUBADD213PSZrk:
26064 case VFMSUBADD213PSZrkz:
26065 case VFMSUBADD213PSm:
26066 case VFMSUBADD213PSr:
26067 return true;
26068 }
26069 return false;
26070}
26071
26072bool isVMOVDQU32(unsigned Opcode) {
26073 switch (Opcode) {
26074 case VMOVDQU32Z128mr:
26075 case VMOVDQU32Z128mrk:
26076 case VMOVDQU32Z128rm:
26077 case VMOVDQU32Z128rmk:
26078 case VMOVDQU32Z128rmkz:
26079 case VMOVDQU32Z128rr:
26080 case VMOVDQU32Z128rr_REV:
26081 case VMOVDQU32Z128rrk:
26082 case VMOVDQU32Z128rrk_REV:
26083 case VMOVDQU32Z128rrkz:
26084 case VMOVDQU32Z128rrkz_REV:
26085 case VMOVDQU32Z256mr:
26086 case VMOVDQU32Z256mrk:
26087 case VMOVDQU32Z256rm:
26088 case VMOVDQU32Z256rmk:
26089 case VMOVDQU32Z256rmkz:
26090 case VMOVDQU32Z256rr:
26091 case VMOVDQU32Z256rr_REV:
26092 case VMOVDQU32Z256rrk:
26093 case VMOVDQU32Z256rrk_REV:
26094 case VMOVDQU32Z256rrkz:
26095 case VMOVDQU32Z256rrkz_REV:
26096 case VMOVDQU32Zmr:
26097 case VMOVDQU32Zmrk:
26098 case VMOVDQU32Zrm:
26099 case VMOVDQU32Zrmk:
26100 case VMOVDQU32Zrmkz:
26101 case VMOVDQU32Zrr:
26102 case VMOVDQU32Zrr_REV:
26103 case VMOVDQU32Zrrk:
26104 case VMOVDQU32Zrrk_REV:
26105 case VMOVDQU32Zrrkz:
26106 case VMOVDQU32Zrrkz_REV:
26107 return true;
26108 }
26109 return false;
26110}
26111
26112bool isFUCOM(unsigned Opcode) {
26113 return Opcode == UCOM_Fr;
26114}
26115
26116bool isVFNMADD213BF16(unsigned Opcode) {
26117 switch (Opcode) {
26118 case VFNMADD213BF16Z128m:
26119 case VFNMADD213BF16Z128mb:
26120 case VFNMADD213BF16Z128mbk:
26121 case VFNMADD213BF16Z128mbkz:
26122 case VFNMADD213BF16Z128mk:
26123 case VFNMADD213BF16Z128mkz:
26124 case VFNMADD213BF16Z128r:
26125 case VFNMADD213BF16Z128rk:
26126 case VFNMADD213BF16Z128rkz:
26127 case VFNMADD213BF16Z256m:
26128 case VFNMADD213BF16Z256mb:
26129 case VFNMADD213BF16Z256mbk:
26130 case VFNMADD213BF16Z256mbkz:
26131 case VFNMADD213BF16Z256mk:
26132 case VFNMADD213BF16Z256mkz:
26133 case VFNMADD213BF16Z256r:
26134 case VFNMADD213BF16Z256rk:
26135 case VFNMADD213BF16Z256rkz:
26136 case VFNMADD213BF16Zm:
26137 case VFNMADD213BF16Zmb:
26138 case VFNMADD213BF16Zmbk:
26139 case VFNMADD213BF16Zmbkz:
26140 case VFNMADD213BF16Zmk:
26141 case VFNMADD213BF16Zmkz:
26142 case VFNMADD213BF16Zr:
26143 case VFNMADD213BF16Zrk:
26144 case VFNMADD213BF16Zrkz:
26145 return true;
26146 }
26147 return false;
26148}
26149
26150bool isHADDPS(unsigned Opcode) {
26151 switch (Opcode) {
26152 case HADDPSrm:
26153 case HADDPSrr:
26154 return true;
26155 }
26156 return false;
26157}
26158
26159bool isCMP(unsigned Opcode) {
26160 switch (Opcode) {
26161 case CMP16i16:
26162 case CMP16mi:
26163 case CMP16mi8:
26164 case CMP16mr:
26165 case CMP16ri:
26166 case CMP16ri8:
26167 case CMP16rm:
26168 case CMP16rr:
26169 case CMP16rr_REV:
26170 case CMP32i32:
26171 case CMP32mi:
26172 case CMP32mi8:
26173 case CMP32mr:
26174 case CMP32ri:
26175 case CMP32ri8:
26176 case CMP32rm:
26177 case CMP32rr:
26178 case CMP32rr_REV:
26179 case CMP64i32:
26180 case CMP64mi32:
26181 case CMP64mi8:
26182 case CMP64mr:
26183 case CMP64ri32:
26184 case CMP64ri8:
26185 case CMP64rm:
26186 case CMP64rr:
26187 case CMP64rr_REV:
26188 case CMP8i8:
26189 case CMP8mi:
26190 case CMP8mi8:
26191 case CMP8mr:
26192 case CMP8ri:
26193 case CMP8ri8:
26194 case CMP8rm:
26195 case CMP8rr:
26196 case CMP8rr_REV:
26197 return true;
26198 }
26199 return false;
26200}
26201
26202bool isCVTTPS2PI(unsigned Opcode) {
26203 switch (Opcode) {
26204 case MMX_CVTTPS2PIrm:
26205 case MMX_CVTTPS2PIrr:
26206 return true;
26207 }
26208 return false;
26209}
26210
26211bool isIRETQ(unsigned Opcode) {
26212 return Opcode == IRET64;
26213}
26214
26215bool isPF2IW(unsigned Opcode) {
26216 switch (Opcode) {
26217 case PF2IWrm:
26218 case PF2IWrr:
26219 return true;
26220 }
26221 return false;
26222}
26223
26224bool isPSHUFD(unsigned Opcode) {
26225 switch (Opcode) {
26226 case PSHUFDmi:
26227 case PSHUFDri:
26228 return true;
26229 }
26230 return false;
26231}
26232
26233bool isVDPPD(unsigned Opcode) {
26234 switch (Opcode) {
26235 case VDPPDrmi:
26236 case VDPPDrri:
26237 return true;
26238 }
26239 return false;
26240}
26241
26242bool isPSHUFHW(unsigned Opcode) {
26243 switch (Opcode) {
26244 case PSHUFHWmi:
26245 case PSHUFHWri:
26246 return true;
26247 }
26248 return false;
26249}
26250
26251bool isRMPADJUST(unsigned Opcode) {
26252 return Opcode == RMPADJUST;
26253}
26254
26255bool isPI2FW(unsigned Opcode) {
26256 switch (Opcode) {
26257 case PI2FWrm:
26258 case PI2FWrr:
26259 return true;
26260 }
26261 return false;
26262}
26263
26264bool isVCVTTPH2QQ(unsigned Opcode) {
26265 switch (Opcode) {
26266 case VCVTTPH2QQZ128rm:
26267 case VCVTTPH2QQZ128rmb:
26268 case VCVTTPH2QQZ128rmbk:
26269 case VCVTTPH2QQZ128rmbkz:
26270 case VCVTTPH2QQZ128rmk:
26271 case VCVTTPH2QQZ128rmkz:
26272 case VCVTTPH2QQZ128rr:
26273 case VCVTTPH2QQZ128rrk:
26274 case VCVTTPH2QQZ128rrkz:
26275 case VCVTTPH2QQZ256rm:
26276 case VCVTTPH2QQZ256rmb:
26277 case VCVTTPH2QQZ256rmbk:
26278 case VCVTTPH2QQZ256rmbkz:
26279 case VCVTTPH2QQZ256rmk:
26280 case VCVTTPH2QQZ256rmkz:
26281 case VCVTTPH2QQZ256rr:
26282 case VCVTTPH2QQZ256rrk:
26283 case VCVTTPH2QQZ256rrkz:
26284 case VCVTTPH2QQZrm:
26285 case VCVTTPH2QQZrmb:
26286 case VCVTTPH2QQZrmbk:
26287 case VCVTTPH2QQZrmbkz:
26288 case VCVTTPH2QQZrmk:
26289 case VCVTTPH2QQZrmkz:
26290 case VCVTTPH2QQZrr:
26291 case VCVTTPH2QQZrrb:
26292 case VCVTTPH2QQZrrbk:
26293 case VCVTTPH2QQZrrbkz:
26294 case VCVTTPH2QQZrrk:
26295 case VCVTTPH2QQZrrkz:
26296 return true;
26297 }
26298 return false;
26299}
26300
26301bool isDIVPD(unsigned Opcode) {
26302 switch (Opcode) {
26303 case DIVPDrm:
26304 case DIVPDrr:
26305 return true;
26306 }
26307 return false;
26308}
26309
26310bool isCLFLUSH(unsigned Opcode) {
26311 return Opcode == CLFLUSH;
26312}
26313
26314bool isVPMINUW(unsigned Opcode) {
26315 switch (Opcode) {
26316 case VPMINUWYrm:
26317 case VPMINUWYrr:
26318 case VPMINUWZ128rm:
26319 case VPMINUWZ128rmk:
26320 case VPMINUWZ128rmkz:
26321 case VPMINUWZ128rr:
26322 case VPMINUWZ128rrk:
26323 case VPMINUWZ128rrkz:
26324 case VPMINUWZ256rm:
26325 case VPMINUWZ256rmk:
26326 case VPMINUWZ256rmkz:
26327 case VPMINUWZ256rr:
26328 case VPMINUWZ256rrk:
26329 case VPMINUWZ256rrkz:
26330 case VPMINUWZrm:
26331 case VPMINUWZrmk:
26332 case VPMINUWZrmkz:
26333 case VPMINUWZrr:
26334 case VPMINUWZrrk:
26335 case VPMINUWZrrkz:
26336 case VPMINUWrm:
26337 case VPMINUWrr:
26338 return true;
26339 }
26340 return false;
26341}
26342
26343bool isIN(unsigned Opcode) {
26344 switch (Opcode) {
26345 case IN16ri:
26346 case IN16rr:
26347 case IN32ri:
26348 case IN32rr:
26349 case IN8ri:
26350 case IN8rr:
26351 return true;
26352 }
26353 return false;
26354}
26355
26356bool isWRPKRU(unsigned Opcode) {
26357 return Opcode == WRPKRUr;
26358}
26359
26360bool isINSERTPS(unsigned Opcode) {
26361 switch (Opcode) {
26362 case INSERTPSrmi:
26363 case INSERTPSrri:
26364 return true;
26365 }
26366 return false;
26367}
26368
26369bool isAAM(unsigned Opcode) {
26370 return Opcode == AAM8i8;
26371}
26372
26373bool isVPHADDUDQ(unsigned Opcode) {
26374 switch (Opcode) {
26375 case VPHADDUDQrm:
26376 case VPHADDUDQrr:
26377 return true;
26378 }
26379 return false;
26380}
26381
26382bool isVSHA512MSG1(unsigned Opcode) {
26383 return Opcode == VSHA512MSG1rr;
26384}
26385
26386bool isDIVPS(unsigned Opcode) {
26387 switch (Opcode) {
26388 case DIVPSrm:
26389 case DIVPSrr:
26390 return true;
26391 }
26392 return false;
26393}
26394
26395bool isKNOTB(unsigned Opcode) {
26396 return Opcode == KNOTBkk;
26397}
26398
26399bool isBLSFILL(unsigned Opcode) {
26400 switch (Opcode) {
26401 case BLSFILL32rm:
26402 case BLSFILL32rr:
26403 case BLSFILL64rm:
26404 case BLSFILL64rr:
26405 return true;
26406 }
26407 return false;
26408}
26409
26410bool isVPCMPGTQ(unsigned Opcode) {
26411 switch (Opcode) {
26412 case VPCMPGTQYrm:
26413 case VPCMPGTQYrr:
26414 case VPCMPGTQZ128rm:
26415 case VPCMPGTQZ128rmb:
26416 case VPCMPGTQZ128rmbk:
26417 case VPCMPGTQZ128rmk:
26418 case VPCMPGTQZ128rr:
26419 case VPCMPGTQZ128rrk:
26420 case VPCMPGTQZ256rm:
26421 case VPCMPGTQZ256rmb:
26422 case VPCMPGTQZ256rmbk:
26423 case VPCMPGTQZ256rmk:
26424 case VPCMPGTQZ256rr:
26425 case VPCMPGTQZ256rrk:
26426 case VPCMPGTQZrm:
26427 case VPCMPGTQZrmb:
26428 case VPCMPGTQZrmbk:
26429 case VPCMPGTQZrmk:
26430 case VPCMPGTQZrr:
26431 case VPCMPGTQZrrk:
26432 case VPCMPGTQrm:
26433 case VPCMPGTQrr:
26434 return true;
26435 }
26436 return false;
26437}
26438
26439bool isMINSD(unsigned Opcode) {
26440 switch (Opcode) {
26441 case MINSDrm_Int:
26442 case MINSDrr_Int:
26443 return true;
26444 }
26445 return false;
26446}
26447
26448bool isFPREM(unsigned Opcode) {
26449 return Opcode == FPREM;
26450}
26451
26452bool isVPUNPCKHQDQ(unsigned Opcode) {
26453 switch (Opcode) {
26454 case VPUNPCKHQDQYrm:
26455 case VPUNPCKHQDQYrr:
26456 case VPUNPCKHQDQZ128rm:
26457 case VPUNPCKHQDQZ128rmb:
26458 case VPUNPCKHQDQZ128rmbk:
26459 case VPUNPCKHQDQZ128rmbkz:
26460 case VPUNPCKHQDQZ128rmk:
26461 case VPUNPCKHQDQZ128rmkz:
26462 case VPUNPCKHQDQZ128rr:
26463 case VPUNPCKHQDQZ128rrk:
26464 case VPUNPCKHQDQZ128rrkz:
26465 case VPUNPCKHQDQZ256rm:
26466 case VPUNPCKHQDQZ256rmb:
26467 case VPUNPCKHQDQZ256rmbk:
26468 case VPUNPCKHQDQZ256rmbkz:
26469 case VPUNPCKHQDQZ256rmk:
26470 case VPUNPCKHQDQZ256rmkz:
26471 case VPUNPCKHQDQZ256rr:
26472 case VPUNPCKHQDQZ256rrk:
26473 case VPUNPCKHQDQZ256rrkz:
26474 case VPUNPCKHQDQZrm:
26475 case VPUNPCKHQDQZrmb:
26476 case VPUNPCKHQDQZrmbk:
26477 case VPUNPCKHQDQZrmbkz:
26478 case VPUNPCKHQDQZrmk:
26479 case VPUNPCKHQDQZrmkz:
26480 case VPUNPCKHQDQZrr:
26481 case VPUNPCKHQDQZrrk:
26482 case VPUNPCKHQDQZrrkz:
26483 case VPUNPCKHQDQrm:
26484 case VPUNPCKHQDQrr:
26485 return true;
26486 }
26487 return false;
26488}
26489
26490bool isMINPD(unsigned Opcode) {
26491 switch (Opcode) {
26492 case MINPDrm:
26493 case MINPDrr:
26494 return true;
26495 }
26496 return false;
26497}
26498
26499bool isVCVTTPD2QQ(unsigned Opcode) {
26500 switch (Opcode) {
26501 case VCVTTPD2QQZ128rm:
26502 case VCVTTPD2QQZ128rmb:
26503 case VCVTTPD2QQZ128rmbk:
26504 case VCVTTPD2QQZ128rmbkz:
26505 case VCVTTPD2QQZ128rmk:
26506 case VCVTTPD2QQZ128rmkz:
26507 case VCVTTPD2QQZ128rr:
26508 case VCVTTPD2QQZ128rrk:
26509 case VCVTTPD2QQZ128rrkz:
26510 case VCVTTPD2QQZ256rm:
26511 case VCVTTPD2QQZ256rmb:
26512 case VCVTTPD2QQZ256rmbk:
26513 case VCVTTPD2QQZ256rmbkz:
26514 case VCVTTPD2QQZ256rmk:
26515 case VCVTTPD2QQZ256rmkz:
26516 case VCVTTPD2QQZ256rr:
26517 case VCVTTPD2QQZ256rrk:
26518 case VCVTTPD2QQZ256rrkz:
26519 case VCVTTPD2QQZrm:
26520 case VCVTTPD2QQZrmb:
26521 case VCVTTPD2QQZrmbk:
26522 case VCVTTPD2QQZrmbkz:
26523 case VCVTTPD2QQZrmk:
26524 case VCVTTPD2QQZrmkz:
26525 case VCVTTPD2QQZrr:
26526 case VCVTTPD2QQZrrb:
26527 case VCVTTPD2QQZrrbk:
26528 case VCVTTPD2QQZrrbkz:
26529 case VCVTTPD2QQZrrk:
26530 case VCVTTPD2QQZrrkz:
26531 return true;
26532 }
26533 return false;
26534}
26535
26536bool isVFMSUBPD(unsigned Opcode) {
26537 switch (Opcode) {
26538 case VFMSUBPD4Ymr:
26539 case VFMSUBPD4Yrm:
26540 case VFMSUBPD4Yrr:
26541 case VFMSUBPD4Yrr_REV:
26542 case VFMSUBPD4mr:
26543 case VFMSUBPD4rm:
26544 case VFMSUBPD4rr:
26545 case VFMSUBPD4rr_REV:
26546 return true;
26547 }
26548 return false;
26549}
26550
26551bool isV4FMADDSS(unsigned Opcode) {
26552 switch (Opcode) {
26553 case V4FMADDSSrm:
26554 case V4FMADDSSrmk:
26555 case V4FMADDSSrmkz:
26556 return true;
26557 }
26558 return false;
26559}
26560
26561bool isCPUID(unsigned Opcode) {
26562 return Opcode == CPUID;
26563}
26564
26565bool isSETCC(unsigned Opcode) {
26566 switch (Opcode) {
26567 case SETCCm:
26568 case SETCCm_EVEX:
26569 case SETCCr:
26570 case SETCCr_EVEX:
26571 return true;
26572 }
26573 return false;
26574}
26575
26576bool isVPDPWUUD(unsigned Opcode) {
26577 switch (Opcode) {
26578 case VPDPWUUDYrm:
26579 case VPDPWUUDYrr:
26580 case VPDPWUUDZ128rm:
26581 case VPDPWUUDZ128rmb:
26582 case VPDPWUUDZ128rmbk:
26583 case VPDPWUUDZ128rmbkz:
26584 case VPDPWUUDZ128rmk:
26585 case VPDPWUUDZ128rmkz:
26586 case VPDPWUUDZ128rr:
26587 case VPDPWUUDZ128rrk:
26588 case VPDPWUUDZ128rrkz:
26589 case VPDPWUUDZ256rm:
26590 case VPDPWUUDZ256rmb:
26591 case VPDPWUUDZ256rmbk:
26592 case VPDPWUUDZ256rmbkz:
26593 case VPDPWUUDZ256rmk:
26594 case VPDPWUUDZ256rmkz:
26595 case VPDPWUUDZ256rr:
26596 case VPDPWUUDZ256rrk:
26597 case VPDPWUUDZ256rrkz:
26598 case VPDPWUUDZrm:
26599 case VPDPWUUDZrmb:
26600 case VPDPWUUDZrmbk:
26601 case VPDPWUUDZrmbkz:
26602 case VPDPWUUDZrmk:
26603 case VPDPWUUDZrmkz:
26604 case VPDPWUUDZrr:
26605 case VPDPWUUDZrrk:
26606 case VPDPWUUDZrrkz:
26607 case VPDPWUUDrm:
26608 case VPDPWUUDrr:
26609 return true;
26610 }
26611 return false;
26612}
26613
26614bool isVCVTTPS2IUBS(unsigned Opcode) {
26615 switch (Opcode) {
26616 case VCVTTPS2IUBSZ128rm:
26617 case VCVTTPS2IUBSZ128rmb:
26618 case VCVTTPS2IUBSZ128rmbk:
26619 case VCVTTPS2IUBSZ128rmbkz:
26620 case VCVTTPS2IUBSZ128rmk:
26621 case VCVTTPS2IUBSZ128rmkz:
26622 case VCVTTPS2IUBSZ128rr:
26623 case VCVTTPS2IUBSZ128rrk:
26624 case VCVTTPS2IUBSZ128rrkz:
26625 case VCVTTPS2IUBSZ256rm:
26626 case VCVTTPS2IUBSZ256rmb:
26627 case VCVTTPS2IUBSZ256rmbk:
26628 case VCVTTPS2IUBSZ256rmbkz:
26629 case VCVTTPS2IUBSZ256rmk:
26630 case VCVTTPS2IUBSZ256rmkz:
26631 case VCVTTPS2IUBSZ256rr:
26632 case VCVTTPS2IUBSZ256rrk:
26633 case VCVTTPS2IUBSZ256rrkz:
26634 case VCVTTPS2IUBSZrm:
26635 case VCVTTPS2IUBSZrmb:
26636 case VCVTTPS2IUBSZrmbk:
26637 case VCVTTPS2IUBSZrmbkz:
26638 case VCVTTPS2IUBSZrmk:
26639 case VCVTTPS2IUBSZrmkz:
26640 case VCVTTPS2IUBSZrr:
26641 case VCVTTPS2IUBSZrrb:
26642 case VCVTTPS2IUBSZrrbk:
26643 case VCVTTPS2IUBSZrrbkz:
26644 case VCVTTPS2IUBSZrrk:
26645 case VCVTTPS2IUBSZrrkz:
26646 return true;
26647 }
26648 return false;
26649}
26650
26651bool isPMOVSXDQ(unsigned Opcode) {
26652 switch (Opcode) {
26653 case PMOVSXDQrm:
26654 case PMOVSXDQrr:
26655 return true;
26656 }
26657 return false;
26658}
26659
26660bool isMWAIT(unsigned Opcode) {
26661 return Opcode == MWAITrr;
26662}
26663
26664bool isVPEXTRB(unsigned Opcode) {
26665 switch (Opcode) {
26666 case VPEXTRBZmri:
26667 case VPEXTRBZrri:
26668 case VPEXTRBmri:
26669 case VPEXTRBrri:
26670 return true;
26671 }
26672 return false;
26673}
26674
26675bool isINVVPID(unsigned Opcode) {
26676 switch (Opcode) {
26677 case INVVPID32:
26678 case INVVPID64:
26679 case INVVPID64_EVEX:
26680 return true;
26681 }
26682 return false;
26683}
26684
26685bool isVPSHUFD(unsigned Opcode) {
26686 switch (Opcode) {
26687 case VPSHUFDYmi:
26688 case VPSHUFDYri:
26689 case VPSHUFDZ128mbi:
26690 case VPSHUFDZ128mbik:
26691 case VPSHUFDZ128mbikz:
26692 case VPSHUFDZ128mi:
26693 case VPSHUFDZ128mik:
26694 case VPSHUFDZ128mikz:
26695 case VPSHUFDZ128ri:
26696 case VPSHUFDZ128rik:
26697 case VPSHUFDZ128rikz:
26698 case VPSHUFDZ256mbi:
26699 case VPSHUFDZ256mbik:
26700 case VPSHUFDZ256mbikz:
26701 case VPSHUFDZ256mi:
26702 case VPSHUFDZ256mik:
26703 case VPSHUFDZ256mikz:
26704 case VPSHUFDZ256ri:
26705 case VPSHUFDZ256rik:
26706 case VPSHUFDZ256rikz:
26707 case VPSHUFDZmbi:
26708 case VPSHUFDZmbik:
26709 case VPSHUFDZmbikz:
26710 case VPSHUFDZmi:
26711 case VPSHUFDZmik:
26712 case VPSHUFDZmikz:
26713 case VPSHUFDZri:
26714 case VPSHUFDZrik:
26715 case VPSHUFDZrikz:
26716 case VPSHUFDmi:
26717 case VPSHUFDri:
26718 return true;
26719 }
26720 return false;
26721}
26722
26723bool isVMINBF16(unsigned Opcode) {
26724 switch (Opcode) {
26725 case VMINBF16Z128rm:
26726 case VMINBF16Z128rmb:
26727 case VMINBF16Z128rmbk:
26728 case VMINBF16Z128rmbkz:
26729 case VMINBF16Z128rmk:
26730 case VMINBF16Z128rmkz:
26731 case VMINBF16Z128rr:
26732 case VMINBF16Z128rrk:
26733 case VMINBF16Z128rrkz:
26734 case VMINBF16Z256rm:
26735 case VMINBF16Z256rmb:
26736 case VMINBF16Z256rmbk:
26737 case VMINBF16Z256rmbkz:
26738 case VMINBF16Z256rmk:
26739 case VMINBF16Z256rmkz:
26740 case VMINBF16Z256rr:
26741 case VMINBF16Z256rrk:
26742 case VMINBF16Z256rrkz:
26743 case VMINBF16Zrm:
26744 case VMINBF16Zrmb:
26745 case VMINBF16Zrmbk:
26746 case VMINBF16Zrmbkz:
26747 case VMINBF16Zrmk:
26748 case VMINBF16Zrmkz:
26749 case VMINBF16Zrr:
26750 case VMINBF16Zrrk:
26751 case VMINBF16Zrrkz:
26752 return true;
26753 }
26754 return false;
26755}
26756
26757bool isMOVLPS(unsigned Opcode) {
26758 switch (Opcode) {
26759 case MOVLPSmr:
26760 case MOVLPSrm:
26761 return true;
26762 }
26763 return false;
26764}
26765
26766bool isVBLENDMPS(unsigned Opcode) {
26767 switch (Opcode) {
26768 case VBLENDMPSZ128rm:
26769 case VBLENDMPSZ128rmb:
26770 case VBLENDMPSZ128rmbk:
26771 case VBLENDMPSZ128rmbkz:
26772 case VBLENDMPSZ128rmk:
26773 case VBLENDMPSZ128rmkz:
26774 case VBLENDMPSZ128rr:
26775 case VBLENDMPSZ128rrk:
26776 case VBLENDMPSZ128rrkz:
26777 case VBLENDMPSZ256rm:
26778 case VBLENDMPSZ256rmb:
26779 case VBLENDMPSZ256rmbk:
26780 case VBLENDMPSZ256rmbkz:
26781 case VBLENDMPSZ256rmk:
26782 case VBLENDMPSZ256rmkz:
26783 case VBLENDMPSZ256rr:
26784 case VBLENDMPSZ256rrk:
26785 case VBLENDMPSZ256rrkz:
26786 case VBLENDMPSZrm:
26787 case VBLENDMPSZrmb:
26788 case VBLENDMPSZrmbk:
26789 case VBLENDMPSZrmbkz:
26790 case VBLENDMPSZrmk:
26791 case VBLENDMPSZrmkz:
26792 case VBLENDMPSZrr:
26793 case VBLENDMPSZrrk:
26794 case VBLENDMPSZrrkz:
26795 return true;
26796 }
26797 return false;
26798}
26799
26800bool isPMULLW(unsigned Opcode) {
26801 switch (Opcode) {
26802 case MMX_PMULLWrm:
26803 case MMX_PMULLWrr:
26804 case PMULLWrm:
26805 case PMULLWrr:
26806 return true;
26807 }
26808 return false;
26809}
26810
26811bool isVCVTSH2SI(unsigned Opcode) {
26812 switch (Opcode) {
26813 case VCVTSH2SI64Zrm_Int:
26814 case VCVTSH2SI64Zrr_Int:
26815 case VCVTSH2SI64Zrrb_Int:
26816 case VCVTSH2SIZrm_Int:
26817 case VCVTSH2SIZrr_Int:
26818 case VCVTSH2SIZrrb_Int:
26819 return true;
26820 }
26821 return false;
26822}
26823
26824bool isVPMOVSXWQ(unsigned Opcode) {
26825 switch (Opcode) {
26826 case VPMOVSXWQYrm:
26827 case VPMOVSXWQYrr:
26828 case VPMOVSXWQZ128rm:
26829 case VPMOVSXWQZ128rmk:
26830 case VPMOVSXWQZ128rmkz:
26831 case VPMOVSXWQZ128rr:
26832 case VPMOVSXWQZ128rrk:
26833 case VPMOVSXWQZ128rrkz:
26834 case VPMOVSXWQZ256rm:
26835 case VPMOVSXWQZ256rmk:
26836 case VPMOVSXWQZ256rmkz:
26837 case VPMOVSXWQZ256rr:
26838 case VPMOVSXWQZ256rrk:
26839 case VPMOVSXWQZ256rrkz:
26840 case VPMOVSXWQZrm:
26841 case VPMOVSXWQZrmk:
26842 case VPMOVSXWQZrmkz:
26843 case VPMOVSXWQZrr:
26844 case VPMOVSXWQZrrk:
26845 case VPMOVSXWQZrrkz:
26846 case VPMOVSXWQrm:
26847 case VPMOVSXWQrr:
26848 return true;
26849 }
26850 return false;
26851}
26852
26853bool isFNSTENV(unsigned Opcode) {
26854 return Opcode == FSTENVm;
26855}
26856
26857bool isVCVT2PH2BF8(unsigned Opcode) {
26858 switch (Opcode) {
26859 case VCVT2PH2BF8Z128rm:
26860 case VCVT2PH2BF8Z128rmb:
26861 case VCVT2PH2BF8Z128rmbk:
26862 case VCVT2PH2BF8Z128rmbkz:
26863 case VCVT2PH2BF8Z128rmk:
26864 case VCVT2PH2BF8Z128rmkz:
26865 case VCVT2PH2BF8Z128rr:
26866 case VCVT2PH2BF8Z128rrk:
26867 case VCVT2PH2BF8Z128rrkz:
26868 case VCVT2PH2BF8Z256rm:
26869 case VCVT2PH2BF8Z256rmb:
26870 case VCVT2PH2BF8Z256rmbk:
26871 case VCVT2PH2BF8Z256rmbkz:
26872 case VCVT2PH2BF8Z256rmk:
26873 case VCVT2PH2BF8Z256rmkz:
26874 case VCVT2PH2BF8Z256rr:
26875 case VCVT2PH2BF8Z256rrk:
26876 case VCVT2PH2BF8Z256rrkz:
26877 case VCVT2PH2BF8Zrm:
26878 case VCVT2PH2BF8Zrmb:
26879 case VCVT2PH2BF8Zrmbk:
26880 case VCVT2PH2BF8Zrmbkz:
26881 case VCVT2PH2BF8Zrmk:
26882 case VCVT2PH2BF8Zrmkz:
26883 case VCVT2PH2BF8Zrr:
26884 case VCVT2PH2BF8Zrrk:
26885 case VCVT2PH2BF8Zrrkz:
26886 return true;
26887 }
26888 return false;
26889}
26890
26891bool isVPERMI2PD(unsigned Opcode) {
26892 switch (Opcode) {
26893 case VPERMI2PDZ128rm:
26894 case VPERMI2PDZ128rmb:
26895 case VPERMI2PDZ128rmbk:
26896 case VPERMI2PDZ128rmbkz:
26897 case VPERMI2PDZ128rmk:
26898 case VPERMI2PDZ128rmkz:
26899 case VPERMI2PDZ128rr:
26900 case VPERMI2PDZ128rrk:
26901 case VPERMI2PDZ128rrkz:
26902 case VPERMI2PDZ256rm:
26903 case VPERMI2PDZ256rmb:
26904 case VPERMI2PDZ256rmbk:
26905 case VPERMI2PDZ256rmbkz:
26906 case VPERMI2PDZ256rmk:
26907 case VPERMI2PDZ256rmkz:
26908 case VPERMI2PDZ256rr:
26909 case VPERMI2PDZ256rrk:
26910 case VPERMI2PDZ256rrkz:
26911 case VPERMI2PDZrm:
26912 case VPERMI2PDZrmb:
26913 case VPERMI2PDZrmbk:
26914 case VPERMI2PDZrmbkz:
26915 case VPERMI2PDZrmk:
26916 case VPERMI2PDZrmkz:
26917 case VPERMI2PDZrr:
26918 case VPERMI2PDZrrk:
26919 case VPERMI2PDZrrkz:
26920 return true;
26921 }
26922 return false;
26923}
26924
26925bool isMAXSS(unsigned Opcode) {
26926 switch (Opcode) {
26927 case MAXSSrm_Int:
26928 case MAXSSrr_Int:
26929 return true;
26930 }
26931 return false;
26932}
26933
26934bool isCWDE(unsigned Opcode) {
26935 return Opcode == CWDE;
26936}
26937
26938bool isVBROADCASTI32X8(unsigned Opcode) {
26939 switch (Opcode) {
26940 case VBROADCASTI32X8Zrm:
26941 case VBROADCASTI32X8Zrmk:
26942 case VBROADCASTI32X8Zrmkz:
26943 return true;
26944 }
26945 return false;
26946}
26947
26948bool isINT(unsigned Opcode) {
26949 return Opcode == INT;
26950}
26951
26952bool isENCLS(unsigned Opcode) {
26953 return Opcode == ENCLS;
26954}
26955
26956bool isMOVNTQ(unsigned Opcode) {
26957 return Opcode == MMX_MOVNTQmr;
26958}
26959
26960bool isVDIVSH(unsigned Opcode) {
26961 switch (Opcode) {
26962 case VDIVSHZrm_Int:
26963 case VDIVSHZrmk_Int:
26964 case VDIVSHZrmkz_Int:
26965 case VDIVSHZrr_Int:
26966 case VDIVSHZrrb_Int:
26967 case VDIVSHZrrbk_Int:
26968 case VDIVSHZrrbkz_Int:
26969 case VDIVSHZrrk_Int:
26970 case VDIVSHZrrkz_Int:
26971 return true;
26972 }
26973 return false;
26974}
26975
26976bool isMOVHLPS(unsigned Opcode) {
26977 return Opcode == MOVHLPSrr;
26978}
26979
26980bool isVPMASKMOVD(unsigned Opcode) {
26981 switch (Opcode) {
26982 case VPMASKMOVDYmr:
26983 case VPMASKMOVDYrm:
26984 case VPMASKMOVDmr:
26985 case VPMASKMOVDrm:
26986 return true;
26987 }
26988 return false;
26989}
26990
26991bool isVMOVSD(unsigned Opcode) {
26992 switch (Opcode) {
26993 case VMOVSDZmr:
26994 case VMOVSDZmrk:
26995 case VMOVSDZrm:
26996 case VMOVSDZrmk:
26997 case VMOVSDZrmkz:
26998 case VMOVSDZrr:
26999 case VMOVSDZrr_REV:
27000 case VMOVSDZrrk:
27001 case VMOVSDZrrk_REV:
27002 case VMOVSDZrrkz:
27003 case VMOVSDZrrkz_REV:
27004 case VMOVSDmr:
27005 case VMOVSDrm:
27006 case VMOVSDrr:
27007 case VMOVSDrr_REV:
27008 return true;
27009 }
27010 return false;
27011}
27012
27013bool isVPMINUD(unsigned Opcode) {
27014 switch (Opcode) {
27015 case VPMINUDYrm:
27016 case VPMINUDYrr:
27017 case VPMINUDZ128rm:
27018 case VPMINUDZ128rmb:
27019 case VPMINUDZ128rmbk:
27020 case VPMINUDZ128rmbkz:
27021 case VPMINUDZ128rmk:
27022 case VPMINUDZ128rmkz:
27023 case VPMINUDZ128rr:
27024 case VPMINUDZ128rrk:
27025 case VPMINUDZ128rrkz:
27026 case VPMINUDZ256rm:
27027 case VPMINUDZ256rmb:
27028 case VPMINUDZ256rmbk:
27029 case VPMINUDZ256rmbkz:
27030 case VPMINUDZ256rmk:
27031 case VPMINUDZ256rmkz:
27032 case VPMINUDZ256rr:
27033 case VPMINUDZ256rrk:
27034 case VPMINUDZ256rrkz:
27035 case VPMINUDZrm:
27036 case VPMINUDZrmb:
27037 case VPMINUDZrmbk:
27038 case VPMINUDZrmbkz:
27039 case VPMINUDZrmk:
27040 case VPMINUDZrmkz:
27041 case VPMINUDZrr:
27042 case VPMINUDZrrk:
27043 case VPMINUDZrrkz:
27044 case VPMINUDrm:
27045 case VPMINUDrr:
27046 return true;
27047 }
27048 return false;
27049}
27050
27051bool isVPCMPISTRM(unsigned Opcode) {
27052 switch (Opcode) {
27053 case VPCMPISTRMrmi:
27054 case VPCMPISTRMrri:
27055 return true;
27056 }
27057 return false;
27058}
27059
27060bool isVGETMANTSD(unsigned Opcode) {
27061 switch (Opcode) {
27062 case VGETMANTSDZrmi:
27063 case VGETMANTSDZrmik:
27064 case VGETMANTSDZrmikz:
27065 case VGETMANTSDZrri:
27066 case VGETMANTSDZrrib:
27067 case VGETMANTSDZrribk:
27068 case VGETMANTSDZrribkz:
27069 case VGETMANTSDZrrik:
27070 case VGETMANTSDZrrikz:
27071 return true;
27072 }
27073 return false;
27074}
27075
27076bool isKSHIFTRW(unsigned Opcode) {
27077 return Opcode == KSHIFTRWki;
27078}
27079
27080bool isAESDECLAST(unsigned Opcode) {
27081 switch (Opcode) {
27082 case AESDECLASTrm:
27083 case AESDECLASTrr:
27084 return true;
27085 }
27086 return false;
27087}
27088
27089bool isVPTESTMB(unsigned Opcode) {
27090 switch (Opcode) {
27091 case VPTESTMBZ128rm:
27092 case VPTESTMBZ128rmk:
27093 case VPTESTMBZ128rr:
27094 case VPTESTMBZ128rrk:
27095 case VPTESTMBZ256rm:
27096 case VPTESTMBZ256rmk:
27097 case VPTESTMBZ256rr:
27098 case VPTESTMBZ256rrk:
27099 case VPTESTMBZrm:
27100 case VPTESTMBZrmk:
27101 case VPTESTMBZrr:
27102 case VPTESTMBZrrk:
27103 return true;
27104 }
27105 return false;
27106}
27107
27108bool isVFNMSUB231BF16(unsigned Opcode) {
27109 switch (Opcode) {
27110 case VFNMSUB231BF16Z128m:
27111 case VFNMSUB231BF16Z128mb:
27112 case VFNMSUB231BF16Z128mbk:
27113 case VFNMSUB231BF16Z128mbkz:
27114 case VFNMSUB231BF16Z128mk:
27115 case VFNMSUB231BF16Z128mkz:
27116 case VFNMSUB231BF16Z128r:
27117 case VFNMSUB231BF16Z128rk:
27118 case VFNMSUB231BF16Z128rkz:
27119 case VFNMSUB231BF16Z256m:
27120 case VFNMSUB231BF16Z256mb:
27121 case VFNMSUB231BF16Z256mbk:
27122 case VFNMSUB231BF16Z256mbkz:
27123 case VFNMSUB231BF16Z256mk:
27124 case VFNMSUB231BF16Z256mkz:
27125 case VFNMSUB231BF16Z256r:
27126 case VFNMSUB231BF16Z256rk:
27127 case VFNMSUB231BF16Z256rkz:
27128 case VFNMSUB231BF16Zm:
27129 case VFNMSUB231BF16Zmb:
27130 case VFNMSUB231BF16Zmbk:
27131 case VFNMSUB231BF16Zmbkz:
27132 case VFNMSUB231BF16Zmk:
27133 case VFNMSUB231BF16Zmkz:
27134 case VFNMSUB231BF16Zr:
27135 case VFNMSUB231BF16Zrk:
27136 case VFNMSUB231BF16Zrkz:
27137 return true;
27138 }
27139 return false;
27140}
27141
27142bool isVMPTRST(unsigned Opcode) {
27143 return Opcode == VMPTRSTm;
27144}
27145
27146bool isLLDT(unsigned Opcode) {
27147 switch (Opcode) {
27148 case LLDT16m:
27149 case LLDT16r:
27150 return true;
27151 }
27152 return false;
27153}
27154
27155bool isMOVSB(unsigned Opcode) {
27156 return Opcode == MOVSB;
27157}
27158
27159bool isTILELOADD(unsigned Opcode) {
27160 switch (Opcode) {
27161 case TILELOADD:
27162 case TILELOADD_EVEX:
27163 return true;
27164 }
27165 return false;
27166}
27167
27168bool isKTESTB(unsigned Opcode) {
27169 return Opcode == KTESTBkk;
27170}
27171
27172bool isMOVUPD(unsigned Opcode) {
27173 switch (Opcode) {
27174 case MOVUPDmr:
27175 case MOVUPDrm:
27176 case MOVUPDrr:
27177 case MOVUPDrr_REV:
27178 return true;
27179 }
27180 return false;
27181}
27182
27183bool isLKGS(unsigned Opcode) {
27184 switch (Opcode) {
27185 case LKGS16m:
27186 case LKGS16r:
27187 return true;
27188 }
27189 return false;
27190}
27191
27192bool isSGDTW(unsigned Opcode) {
27193 return Opcode == SGDT16m;
27194}
27195
27196bool isDIVSS(unsigned Opcode) {
27197 switch (Opcode) {
27198 case DIVSSrm_Int:
27199 case DIVSSrr_Int:
27200 return true;
27201 }
27202 return false;
27203}
27204
27205bool isPUNPCKHQDQ(unsigned Opcode) {
27206 switch (Opcode) {
27207 case PUNPCKHQDQrm:
27208 case PUNPCKHQDQrr:
27209 return true;
27210 }
27211 return false;
27212}
27213
27214bool isVFMADD213SD(unsigned Opcode) {
27215 switch (Opcode) {
27216 case VFMADD213SDZm_Int:
27217 case VFMADD213SDZmk_Int:
27218 case VFMADD213SDZmkz_Int:
27219 case VFMADD213SDZr_Int:
27220 case VFMADD213SDZrb_Int:
27221 case VFMADD213SDZrbk_Int:
27222 case VFMADD213SDZrbkz_Int:
27223 case VFMADD213SDZrk_Int:
27224 case VFMADD213SDZrkz_Int:
27225 case VFMADD213SDm_Int:
27226 case VFMADD213SDr_Int:
27227 return true;
27228 }
27229 return false;
27230}
27231
27232bool isKXORD(unsigned Opcode) {
27233 return Opcode == KXORDkk;
27234}
27235
27236bool isVPMOVB2M(unsigned Opcode) {
27237 switch (Opcode) {
27238 case VPMOVB2MZ128kr:
27239 case VPMOVB2MZ256kr:
27240 case VPMOVB2MZkr:
27241 return true;
27242 }
27243 return false;
27244}
27245
27246bool isVMREAD(unsigned Opcode) {
27247 switch (Opcode) {
27248 case VMREAD32mr:
27249 case VMREAD32rr:
27250 case VMREAD64mr:
27251 case VMREAD64rr:
27252 return true;
27253 }
27254 return false;
27255}
27256
27257bool isVPDPWSSDS(unsigned Opcode) {
27258 switch (Opcode) {
27259 case VPDPWSSDSYrm:
27260 case VPDPWSSDSYrr:
27261 case VPDPWSSDSZ128rm:
27262 case VPDPWSSDSZ128rmb:
27263 case VPDPWSSDSZ128rmbk:
27264 case VPDPWSSDSZ128rmbkz:
27265 case VPDPWSSDSZ128rmk:
27266 case VPDPWSSDSZ128rmkz:
27267 case VPDPWSSDSZ128rr:
27268 case VPDPWSSDSZ128rrk:
27269 case VPDPWSSDSZ128rrkz:
27270 case VPDPWSSDSZ256rm:
27271 case VPDPWSSDSZ256rmb:
27272 case VPDPWSSDSZ256rmbk:
27273 case VPDPWSSDSZ256rmbkz:
27274 case VPDPWSSDSZ256rmk:
27275 case VPDPWSSDSZ256rmkz:
27276 case VPDPWSSDSZ256rr:
27277 case VPDPWSSDSZ256rrk:
27278 case VPDPWSSDSZ256rrkz:
27279 case VPDPWSSDSZrm:
27280 case VPDPWSSDSZrmb:
27281 case VPDPWSSDSZrmbk:
27282 case VPDPWSSDSZrmbkz:
27283 case VPDPWSSDSZrmk:
27284 case VPDPWSSDSZrmkz:
27285 case VPDPWSSDSZrr:
27286 case VPDPWSSDSZrrk:
27287 case VPDPWSSDSZrrkz:
27288 case VPDPWSSDSrm:
27289 case VPDPWSSDSrr:
27290 return true;
27291 }
27292 return false;
27293}
27294
27295bool isTILERELEASE(unsigned Opcode) {
27296 return Opcode == TILERELEASE;
27297}
27298
27299bool isVUCOMXSH(unsigned Opcode) {
27300 switch (Opcode) {
27301 case VUCOMXSHZrm_Int:
27302 case VUCOMXSHZrr_Int:
27303 case VUCOMXSHZrrb_Int:
27304 return true;
27305 }
27306 return false;
27307}
27308
27309bool isCLFLUSHOPT(unsigned Opcode) {
27310 return Opcode == CLFLUSHOPT;
27311}
27312
27313bool isDAS(unsigned Opcode) {
27314 return Opcode == DAS;
27315}
27316
27317bool isVSCALEFPH(unsigned Opcode) {
27318 switch (Opcode) {
27319 case VSCALEFPHZ128rm:
27320 case VSCALEFPHZ128rmb:
27321 case VSCALEFPHZ128rmbk:
27322 case VSCALEFPHZ128rmbkz:
27323 case VSCALEFPHZ128rmk:
27324 case VSCALEFPHZ128rmkz:
27325 case VSCALEFPHZ128rr:
27326 case VSCALEFPHZ128rrk:
27327 case VSCALEFPHZ128rrkz:
27328 case VSCALEFPHZ256rm:
27329 case VSCALEFPHZ256rmb:
27330 case VSCALEFPHZ256rmbk:
27331 case VSCALEFPHZ256rmbkz:
27332 case VSCALEFPHZ256rmk:
27333 case VSCALEFPHZ256rmkz:
27334 case VSCALEFPHZ256rr:
27335 case VSCALEFPHZ256rrk:
27336 case VSCALEFPHZ256rrkz:
27337 case VSCALEFPHZrm:
27338 case VSCALEFPHZrmb:
27339 case VSCALEFPHZrmbk:
27340 case VSCALEFPHZrmbkz:
27341 case VSCALEFPHZrmk:
27342 case VSCALEFPHZrmkz:
27343 case VSCALEFPHZrr:
27344 case VSCALEFPHZrrb:
27345 case VSCALEFPHZrrbk:
27346 case VSCALEFPHZrrbkz:
27347 case VSCALEFPHZrrk:
27348 case VSCALEFPHZrrkz:
27349 return true;
27350 }
27351 return false;
27352}
27353
27354bool isVSUBSD(unsigned Opcode) {
27355 switch (Opcode) {
27356 case VSUBSDZrm_Int:
27357 case VSUBSDZrmk_Int:
27358 case VSUBSDZrmkz_Int:
27359 case VSUBSDZrr_Int:
27360 case VSUBSDZrrb_Int:
27361 case VSUBSDZrrbk_Int:
27362 case VSUBSDZrrbkz_Int:
27363 case VSUBSDZrrk_Int:
27364 case VSUBSDZrrkz_Int:
27365 case VSUBSDrm_Int:
27366 case VSUBSDrr_Int:
27367 return true;
27368 }
27369 return false;
27370}
27371
27372bool isVCOMISS(unsigned Opcode) {
27373 switch (Opcode) {
27374 case VCOMISSZrm:
27375 case VCOMISSZrr:
27376 case VCOMISSZrrb:
27377 case VCOMISSrm:
27378 case VCOMISSrr:
27379 return true;
27380 }
27381 return false;
27382}
27383
27384bool isVMULBF16(unsigned Opcode) {
27385 switch (Opcode) {
27386 case VMULBF16Z128rm:
27387 case VMULBF16Z128rmb:
27388 case VMULBF16Z128rmbk:
27389 case VMULBF16Z128rmbkz:
27390 case VMULBF16Z128rmk:
27391 case VMULBF16Z128rmkz:
27392 case VMULBF16Z128rr:
27393 case VMULBF16Z128rrk:
27394 case VMULBF16Z128rrkz:
27395 case VMULBF16Z256rm:
27396 case VMULBF16Z256rmb:
27397 case VMULBF16Z256rmbk:
27398 case VMULBF16Z256rmbkz:
27399 case VMULBF16Z256rmk:
27400 case VMULBF16Z256rmkz:
27401 case VMULBF16Z256rr:
27402 case VMULBF16Z256rrk:
27403 case VMULBF16Z256rrkz:
27404 case VMULBF16Zrm:
27405 case VMULBF16Zrmb:
27406 case VMULBF16Zrmbk:
27407 case VMULBF16Zrmbkz:
27408 case VMULBF16Zrmk:
27409 case VMULBF16Zrmkz:
27410 case VMULBF16Zrr:
27411 case VMULBF16Zrrk:
27412 case VMULBF16Zrrkz:
27413 return true;
27414 }
27415 return false;
27416}
27417
27418bool isORPS(unsigned Opcode) {
27419 switch (Opcode) {
27420 case ORPSrm:
27421 case ORPSrr:
27422 return true;
27423 }
27424 return false;
27425}
27426
27427bool isTDPFP16PS(unsigned Opcode) {
27428 return Opcode == TDPFP16PS;
27429}
27430
27431bool isVMAXPD(unsigned Opcode) {
27432 switch (Opcode) {
27433 case VMAXPDYrm:
27434 case VMAXPDYrr:
27435 case VMAXPDZ128rm:
27436 case VMAXPDZ128rmb:
27437 case VMAXPDZ128rmbk:
27438 case VMAXPDZ128rmbkz:
27439 case VMAXPDZ128rmk:
27440 case VMAXPDZ128rmkz:
27441 case VMAXPDZ128rr:
27442 case VMAXPDZ128rrk:
27443 case VMAXPDZ128rrkz:
27444 case VMAXPDZ256rm:
27445 case VMAXPDZ256rmb:
27446 case VMAXPDZ256rmbk:
27447 case VMAXPDZ256rmbkz:
27448 case VMAXPDZ256rmk:
27449 case VMAXPDZ256rmkz:
27450 case VMAXPDZ256rr:
27451 case VMAXPDZ256rrk:
27452 case VMAXPDZ256rrkz:
27453 case VMAXPDZrm:
27454 case VMAXPDZrmb:
27455 case VMAXPDZrmbk:
27456 case VMAXPDZrmbkz:
27457 case VMAXPDZrmk:
27458 case VMAXPDZrmkz:
27459 case VMAXPDZrr:
27460 case VMAXPDZrrb:
27461 case VMAXPDZrrbk:
27462 case VMAXPDZrrbkz:
27463 case VMAXPDZrrk:
27464 case VMAXPDZrrkz:
27465 case VMAXPDrm:
27466 case VMAXPDrr:
27467 return true;
27468 }
27469 return false;
27470}
27471
27472bool isVPMOVWB(unsigned Opcode) {
27473 switch (Opcode) {
27474 case VPMOVWBZ128mr:
27475 case VPMOVWBZ128mrk:
27476 case VPMOVWBZ128rr:
27477 case VPMOVWBZ128rrk:
27478 case VPMOVWBZ128rrkz:
27479 case VPMOVWBZ256mr:
27480 case VPMOVWBZ256mrk:
27481 case VPMOVWBZ256rr:
27482 case VPMOVWBZ256rrk:
27483 case VPMOVWBZ256rrkz:
27484 case VPMOVWBZmr:
27485 case VPMOVWBZmrk:
27486 case VPMOVWBZrr:
27487 case VPMOVWBZrrk:
27488 case VPMOVWBZrrkz:
27489 return true;
27490 }
27491 return false;
27492}
27493
27494bool isVEXP2PS(unsigned Opcode) {
27495 switch (Opcode) {
27496 case VEXP2PSZm:
27497 case VEXP2PSZmb:
27498 case VEXP2PSZmbk:
27499 case VEXP2PSZmbkz:
27500 case VEXP2PSZmk:
27501 case VEXP2PSZmkz:
27502 case VEXP2PSZr:
27503 case VEXP2PSZrb:
27504 case VEXP2PSZrbk:
27505 case VEXP2PSZrbkz:
27506 case VEXP2PSZrk:
27507 case VEXP2PSZrkz:
27508 return true;
27509 }
27510 return false;
27511}
27512
27513bool isVPGATHERDQ(unsigned Opcode) {
27514 switch (Opcode) {
27515 case VPGATHERDQYrm:
27516 case VPGATHERDQZ128rm:
27517 case VPGATHERDQZ256rm:
27518 case VPGATHERDQZrm:
27519 case VPGATHERDQrm:
27520 return true;
27521 }
27522 return false;
27523}
27524
27525bool isVPSRAVQ(unsigned Opcode) {
27526 switch (Opcode) {
27527 case VPSRAVQZ128rm:
27528 case VPSRAVQZ128rmb:
27529 case VPSRAVQZ128rmbk:
27530 case VPSRAVQZ128rmbkz:
27531 case VPSRAVQZ128rmk:
27532 case VPSRAVQZ128rmkz:
27533 case VPSRAVQZ128rr:
27534 case VPSRAVQZ128rrk:
27535 case VPSRAVQZ128rrkz:
27536 case VPSRAVQZ256rm:
27537 case VPSRAVQZ256rmb:
27538 case VPSRAVQZ256rmbk:
27539 case VPSRAVQZ256rmbkz:
27540 case VPSRAVQZ256rmk:
27541 case VPSRAVQZ256rmkz:
27542 case VPSRAVQZ256rr:
27543 case VPSRAVQZ256rrk:
27544 case VPSRAVQZ256rrkz:
27545 case VPSRAVQZrm:
27546 case VPSRAVQZrmb:
27547 case VPSRAVQZrmbk:
27548 case VPSRAVQZrmbkz:
27549 case VPSRAVQZrmk:
27550 case VPSRAVQZrmkz:
27551 case VPSRAVQZrr:
27552 case VPSRAVQZrrk:
27553 case VPSRAVQZrrkz:
27554 return true;
27555 }
27556 return false;
27557}
27558
27559bool isPCMPISTRI(unsigned Opcode) {
27560 switch (Opcode) {
27561 case PCMPISTRIrmi:
27562 case PCMPISTRIrri:
27563 return true;
27564 }
27565 return false;
27566}
27567
27568bool isVFMSUB231PD(unsigned Opcode) {
27569 switch (Opcode) {
27570 case VFMSUB231PDYm:
27571 case VFMSUB231PDYr:
27572 case VFMSUB231PDZ128m:
27573 case VFMSUB231PDZ128mb:
27574 case VFMSUB231PDZ128mbk:
27575 case VFMSUB231PDZ128mbkz:
27576 case VFMSUB231PDZ128mk:
27577 case VFMSUB231PDZ128mkz:
27578 case VFMSUB231PDZ128r:
27579 case VFMSUB231PDZ128rk:
27580 case VFMSUB231PDZ128rkz:
27581 case VFMSUB231PDZ256m:
27582 case VFMSUB231PDZ256mb:
27583 case VFMSUB231PDZ256mbk:
27584 case VFMSUB231PDZ256mbkz:
27585 case VFMSUB231PDZ256mk:
27586 case VFMSUB231PDZ256mkz:
27587 case VFMSUB231PDZ256r:
27588 case VFMSUB231PDZ256rk:
27589 case VFMSUB231PDZ256rkz:
27590 case VFMSUB231PDZm:
27591 case VFMSUB231PDZmb:
27592 case VFMSUB231PDZmbk:
27593 case VFMSUB231PDZmbkz:
27594 case VFMSUB231PDZmk:
27595 case VFMSUB231PDZmkz:
27596 case VFMSUB231PDZr:
27597 case VFMSUB231PDZrb:
27598 case VFMSUB231PDZrbk:
27599 case VFMSUB231PDZrbkz:
27600 case VFMSUB231PDZrk:
27601 case VFMSUB231PDZrkz:
27602 case VFMSUB231PDm:
27603 case VFMSUB231PDr:
27604 return true;
27605 }
27606 return false;
27607}
27608
27609bool isRDMSR(unsigned Opcode) {
27610 switch (Opcode) {
27611 case RDMSR:
27612 case RDMSRri:
27613 case RDMSRri_EVEX:
27614 return true;
27615 }
27616 return false;
27617}
27618
27619bool isKORTESTD(unsigned Opcode) {
27620 return Opcode == KORTESTDkk;
27621}
27622
27623bool isVPBLENDMW(unsigned Opcode) {
27624 switch (Opcode) {
27625 case VPBLENDMWZ128rm:
27626 case VPBLENDMWZ128rmk:
27627 case VPBLENDMWZ128rmkz:
27628 case VPBLENDMWZ128rr:
27629 case VPBLENDMWZ128rrk:
27630 case VPBLENDMWZ128rrkz:
27631 case VPBLENDMWZ256rm:
27632 case VPBLENDMWZ256rmk:
27633 case VPBLENDMWZ256rmkz:
27634 case VPBLENDMWZ256rr:
27635 case VPBLENDMWZ256rrk:
27636 case VPBLENDMWZ256rrkz:
27637 case VPBLENDMWZrm:
27638 case VPBLENDMWZrmk:
27639 case VPBLENDMWZrmkz:
27640 case VPBLENDMWZrr:
27641 case VPBLENDMWZrrk:
27642 case VPBLENDMWZrrkz:
27643 return true;
27644 }
27645 return false;
27646}
27647
27648bool isPSHUFB(unsigned Opcode) {
27649 switch (Opcode) {
27650 case MMX_PSHUFBrm:
27651 case MMX_PSHUFBrr:
27652 case PSHUFBrm:
27653 case PSHUFBrr:
27654 return true;
27655 }
27656 return false;
27657}
27658
27659bool isVDPBF16PS(unsigned Opcode) {
27660 switch (Opcode) {
27661 case VDPBF16PSZ128m:
27662 case VDPBF16PSZ128mb:
27663 case VDPBF16PSZ128mbk:
27664 case VDPBF16PSZ128mbkz:
27665 case VDPBF16PSZ128mk:
27666 case VDPBF16PSZ128mkz:
27667 case VDPBF16PSZ128r:
27668 case VDPBF16PSZ128rk:
27669 case VDPBF16PSZ128rkz:
27670 case VDPBF16PSZ256m:
27671 case VDPBF16PSZ256mb:
27672 case VDPBF16PSZ256mbk:
27673 case VDPBF16PSZ256mbkz:
27674 case VDPBF16PSZ256mk:
27675 case VDPBF16PSZ256mkz:
27676 case VDPBF16PSZ256r:
27677 case VDPBF16PSZ256rk:
27678 case VDPBF16PSZ256rkz:
27679 case VDPBF16PSZm:
27680 case VDPBF16PSZmb:
27681 case VDPBF16PSZmbk:
27682 case VDPBF16PSZmbkz:
27683 case VDPBF16PSZmk:
27684 case VDPBF16PSZmkz:
27685 case VDPBF16PSZr:
27686 case VDPBF16PSZrk:
27687 case VDPBF16PSZrkz:
27688 return true;
27689 }
27690 return false;
27691}
27692
27693bool isTDPBF16PS(unsigned Opcode) {
27694 return Opcode == TDPBF16PS;
27695}
27696
27697bool isFCMOVE(unsigned Opcode) {
27698 return Opcode == CMOVE_F;
27699}
27700
27701bool isVFMADD231BF16(unsigned Opcode) {
27702 switch (Opcode) {
27703 case VFMADD231BF16Z128m:
27704 case VFMADD231BF16Z128mb:
27705 case VFMADD231BF16Z128mbk:
27706 case VFMADD231BF16Z128mbkz:
27707 case VFMADD231BF16Z128mk:
27708 case VFMADD231BF16Z128mkz:
27709 case VFMADD231BF16Z128r:
27710 case VFMADD231BF16Z128rk:
27711 case VFMADD231BF16Z128rkz:
27712 case VFMADD231BF16Z256m:
27713 case VFMADD231BF16Z256mb:
27714 case VFMADD231BF16Z256mbk:
27715 case VFMADD231BF16Z256mbkz:
27716 case VFMADD231BF16Z256mk:
27717 case VFMADD231BF16Z256mkz:
27718 case VFMADD231BF16Z256r:
27719 case VFMADD231BF16Z256rk:
27720 case VFMADD231BF16Z256rkz:
27721 case VFMADD231BF16Zm:
27722 case VFMADD231BF16Zmb:
27723 case VFMADD231BF16Zmbk:
27724 case VFMADD231BF16Zmbkz:
27725 case VFMADD231BF16Zmk:
27726 case VFMADD231BF16Zmkz:
27727 case VFMADD231BF16Zr:
27728 case VFMADD231BF16Zrk:
27729 case VFMADD231BF16Zrkz:
27730 return true;
27731 }
27732 return false;
27733}
27734
27735bool isCMPSS(unsigned Opcode) {
27736 switch (Opcode) {
27737 case CMPSSrmi_Int:
27738 case CMPSSrri_Int:
27739 return true;
27740 }
27741 return false;
27742}
27743
27744bool isMASKMOVDQU(unsigned Opcode) {
27745 switch (Opcode) {
27746 case MASKMOVDQU:
27747 case MASKMOVDQU64:
27748 return true;
27749 }
27750 return false;
27751}
27752
27753bool isSARX(unsigned Opcode) {
27754 switch (Opcode) {
27755 case SARX32rm:
27756 case SARX32rm_EVEX:
27757 case SARX32rr:
27758 case SARX32rr_EVEX:
27759 case SARX64rm:
27760 case SARX64rm_EVEX:
27761 case SARX64rr:
27762 case SARX64rr_EVEX:
27763 return true;
27764 }
27765 return false;
27766}
27767
27768bool isVPDPWUSDS(unsigned Opcode) {
27769 switch (Opcode) {
27770 case VPDPWUSDSYrm:
27771 case VPDPWUSDSYrr:
27772 case VPDPWUSDSZ128rm:
27773 case VPDPWUSDSZ128rmb:
27774 case VPDPWUSDSZ128rmbk:
27775 case VPDPWUSDSZ128rmbkz:
27776 case VPDPWUSDSZ128rmk:
27777 case VPDPWUSDSZ128rmkz:
27778 case VPDPWUSDSZ128rr:
27779 case VPDPWUSDSZ128rrk:
27780 case VPDPWUSDSZ128rrkz:
27781 case VPDPWUSDSZ256rm:
27782 case VPDPWUSDSZ256rmb:
27783 case VPDPWUSDSZ256rmbk:
27784 case VPDPWUSDSZ256rmbkz:
27785 case VPDPWUSDSZ256rmk:
27786 case VPDPWUSDSZ256rmkz:
27787 case VPDPWUSDSZ256rr:
27788 case VPDPWUSDSZ256rrk:
27789 case VPDPWUSDSZ256rrkz:
27790 case VPDPWUSDSZrm:
27791 case VPDPWUSDSZrmb:
27792 case VPDPWUSDSZrmbk:
27793 case VPDPWUSDSZrmbkz:
27794 case VPDPWUSDSZrmk:
27795 case VPDPWUSDSZrmkz:
27796 case VPDPWUSDSZrr:
27797 case VPDPWUSDSZrrk:
27798 case VPDPWUSDSZrrkz:
27799 case VPDPWUSDSrm:
27800 case VPDPWUSDSrr:
27801 return true;
27802 }
27803 return false;
27804}
27805
27806bool isSGDT(unsigned Opcode) {
27807 return Opcode == SGDT64m;
27808}
27809
27810bool isVFMULCPH(unsigned Opcode) {
27811 switch (Opcode) {
27812 case VFMULCPHZ128rm:
27813 case VFMULCPHZ128rmb:
27814 case VFMULCPHZ128rmbk:
27815 case VFMULCPHZ128rmbkz:
27816 case VFMULCPHZ128rmk:
27817 case VFMULCPHZ128rmkz:
27818 case VFMULCPHZ128rr:
27819 case VFMULCPHZ128rrk:
27820 case VFMULCPHZ128rrkz:
27821 case VFMULCPHZ256rm:
27822 case VFMULCPHZ256rmb:
27823 case VFMULCPHZ256rmbk:
27824 case VFMULCPHZ256rmbkz:
27825 case VFMULCPHZ256rmk:
27826 case VFMULCPHZ256rmkz:
27827 case VFMULCPHZ256rr:
27828 case VFMULCPHZ256rrk:
27829 case VFMULCPHZ256rrkz:
27830 case VFMULCPHZrm:
27831 case VFMULCPHZrmb:
27832 case VFMULCPHZrmbk:
27833 case VFMULCPHZrmbkz:
27834 case VFMULCPHZrmk:
27835 case VFMULCPHZrmkz:
27836 case VFMULCPHZrr:
27837 case VFMULCPHZrrb:
27838 case VFMULCPHZrrbk:
27839 case VFMULCPHZrrbkz:
27840 case VFMULCPHZrrk:
27841 case VFMULCPHZrrkz:
27842 return true;
27843 }
27844 return false;
27845}
27846
27847bool isURDMSR(unsigned Opcode) {
27848 switch (Opcode) {
27849 case URDMSRri:
27850 case URDMSRri_EVEX:
27851 case URDMSRrr:
27852 case URDMSRrr_EVEX:
27853 return true;
27854 }
27855 return false;
27856}
27857
27858bool isKUNPCKWD(unsigned Opcode) {
27859 return Opcode == KUNPCKWDkk;
27860}
27861
27862bool isVSCALEFBF16(unsigned Opcode) {
27863 switch (Opcode) {
27864 case VSCALEFBF16Z128rm:
27865 case VSCALEFBF16Z128rmb:
27866 case VSCALEFBF16Z128rmbk:
27867 case VSCALEFBF16Z128rmbkz:
27868 case VSCALEFBF16Z128rmk:
27869 case VSCALEFBF16Z128rmkz:
27870 case VSCALEFBF16Z128rr:
27871 case VSCALEFBF16Z128rrk:
27872 case VSCALEFBF16Z128rrkz:
27873 case VSCALEFBF16Z256rm:
27874 case VSCALEFBF16Z256rmb:
27875 case VSCALEFBF16Z256rmbk:
27876 case VSCALEFBF16Z256rmbkz:
27877 case VSCALEFBF16Z256rmk:
27878 case VSCALEFBF16Z256rmkz:
27879 case VSCALEFBF16Z256rr:
27880 case VSCALEFBF16Z256rrk:
27881 case VSCALEFBF16Z256rrkz:
27882 case VSCALEFBF16Zrm:
27883 case VSCALEFBF16Zrmb:
27884 case VSCALEFBF16Zrmbk:
27885 case VSCALEFBF16Zrmbkz:
27886 case VSCALEFBF16Zrmk:
27887 case VSCALEFBF16Zrmkz:
27888 case VSCALEFBF16Zrr:
27889 case VSCALEFBF16Zrrk:
27890 case VSCALEFBF16Zrrkz:
27891 return true;
27892 }
27893 return false;
27894}
27895
27896bool isCVTPS2PD(unsigned Opcode) {
27897 switch (Opcode) {
27898 case CVTPS2PDrm:
27899 case CVTPS2PDrr:
27900 return true;
27901 }
27902 return false;
27903}
27904
27905bool isFBSTP(unsigned Opcode) {
27906 return Opcode == FBSTPm;
27907}
27908
27909bool isPSUBQ(unsigned Opcode) {
27910 switch (Opcode) {
27911 case MMX_PSUBQrm:
27912 case MMX_PSUBQrr:
27913 case PSUBQrm:
27914 case PSUBQrr:
27915 return true;
27916 }
27917 return false;
27918}
27919
27920bool isFXSAVE64(unsigned Opcode) {
27921 return Opcode == FXSAVE64;
27922}
27923
27924bool isKMOVW(unsigned Opcode) {
27925 switch (Opcode) {
27926 case KMOVWkk:
27927 case KMOVWkk_EVEX:
27928 case KMOVWkm:
27929 case KMOVWkm_EVEX:
27930 case KMOVWkr:
27931 case KMOVWkr_EVEX:
27932 case KMOVWmk:
27933 case KMOVWmk_EVEX:
27934 case KMOVWrk:
27935 case KMOVWrk_EVEX:
27936 return true;
27937 }
27938 return false;
27939}
27940
27941bool isBTS(unsigned Opcode) {
27942 switch (Opcode) {
27943 case BTS16mi8:
27944 case BTS16mr:
27945 case BTS16ri8:
27946 case BTS16rr:
27947 case BTS32mi8:
27948 case BTS32mr:
27949 case BTS32ri8:
27950 case BTS32rr:
27951 case BTS64mi8:
27952 case BTS64mr:
27953 case BTS64ri8:
27954 case BTS64rr:
27955 return true;
27956 }
27957 return false;
27958}
27959
27960bool isVPHADDBQ(unsigned Opcode) {
27961 switch (Opcode) {
27962 case VPHADDBQrm:
27963 case VPHADDBQrr:
27964 return true;
27965 }
27966 return false;
27967}
27968
27969bool isFRSTOR(unsigned Opcode) {
27970 return Opcode == FRSTORm;
27971}
27972
27973bool isVFMSUB132PD(unsigned Opcode) {
27974 switch (Opcode) {
27975 case VFMSUB132PDYm:
27976 case VFMSUB132PDYr:
27977 case VFMSUB132PDZ128m:
27978 case VFMSUB132PDZ128mb:
27979 case VFMSUB132PDZ128mbk:
27980 case VFMSUB132PDZ128mbkz:
27981 case VFMSUB132PDZ128mk:
27982 case VFMSUB132PDZ128mkz:
27983 case VFMSUB132PDZ128r:
27984 case VFMSUB132PDZ128rk:
27985 case VFMSUB132PDZ128rkz:
27986 case VFMSUB132PDZ256m:
27987 case VFMSUB132PDZ256mb:
27988 case VFMSUB132PDZ256mbk:
27989 case VFMSUB132PDZ256mbkz:
27990 case VFMSUB132PDZ256mk:
27991 case VFMSUB132PDZ256mkz:
27992 case VFMSUB132PDZ256r:
27993 case VFMSUB132PDZ256rk:
27994 case VFMSUB132PDZ256rkz:
27995 case VFMSUB132PDZm:
27996 case VFMSUB132PDZmb:
27997 case VFMSUB132PDZmbk:
27998 case VFMSUB132PDZmbkz:
27999 case VFMSUB132PDZmk:
28000 case VFMSUB132PDZmkz:
28001 case VFMSUB132PDZr:
28002 case VFMSUB132PDZrb:
28003 case VFMSUB132PDZrbk:
28004 case VFMSUB132PDZrbkz:
28005 case VFMSUB132PDZrk:
28006 case VFMSUB132PDZrkz:
28007 case VFMSUB132PDm:
28008 case VFMSUB132PDr:
28009 return true;
28010 }
28011 return false;
28012}
28013
28014bool isPMULLD(unsigned Opcode) {
28015 switch (Opcode) {
28016 case PMULLDrm:
28017 case PMULLDrr:
28018 return true;
28019 }
28020 return false;
28021}
28022
28023bool isSHA1MSG2(unsigned Opcode) {
28024 switch (Opcode) {
28025 case SHA1MSG2rm:
28026 case SHA1MSG2rr:
28027 return true;
28028 }
28029 return false;
28030}
28031
28032bool isJECXZ(unsigned Opcode) {
28033 return Opcode == JECXZ;
28034}
28035
28036bool isVCVTUDQ2PS(unsigned Opcode) {
28037 switch (Opcode) {
28038 case VCVTUDQ2PSZ128rm:
28039 case VCVTUDQ2PSZ128rmb:
28040 case VCVTUDQ2PSZ128rmbk:
28041 case VCVTUDQ2PSZ128rmbkz:
28042 case VCVTUDQ2PSZ128rmk:
28043 case VCVTUDQ2PSZ128rmkz:
28044 case VCVTUDQ2PSZ128rr:
28045 case VCVTUDQ2PSZ128rrk:
28046 case VCVTUDQ2PSZ128rrkz:
28047 case VCVTUDQ2PSZ256rm:
28048 case VCVTUDQ2PSZ256rmb:
28049 case VCVTUDQ2PSZ256rmbk:
28050 case VCVTUDQ2PSZ256rmbkz:
28051 case VCVTUDQ2PSZ256rmk:
28052 case VCVTUDQ2PSZ256rmkz:
28053 case VCVTUDQ2PSZ256rr:
28054 case VCVTUDQ2PSZ256rrk:
28055 case VCVTUDQ2PSZ256rrkz:
28056 case VCVTUDQ2PSZrm:
28057 case VCVTUDQ2PSZrmb:
28058 case VCVTUDQ2PSZrmbk:
28059 case VCVTUDQ2PSZrmbkz:
28060 case VCVTUDQ2PSZrmk:
28061 case VCVTUDQ2PSZrmkz:
28062 case VCVTUDQ2PSZrr:
28063 case VCVTUDQ2PSZrrb:
28064 case VCVTUDQ2PSZrrbk:
28065 case VCVTUDQ2PSZrrbkz:
28066 case VCVTUDQ2PSZrrk:
28067 case VCVTUDQ2PSZrrkz:
28068 return true;
28069 }
28070 return false;
28071}
28072
28073bool isAESENC(unsigned Opcode) {
28074 switch (Opcode) {
28075 case AESENCrm:
28076 case AESENCrr:
28077 return true;
28078 }
28079 return false;
28080}
28081
28082bool isVMINMAXPS(unsigned Opcode) {
28083 switch (Opcode) {
28084 case VMINMAXPSZ128rmbi:
28085 case VMINMAXPSZ128rmbik:
28086 case VMINMAXPSZ128rmbikz:
28087 case VMINMAXPSZ128rmi:
28088 case VMINMAXPSZ128rmik:
28089 case VMINMAXPSZ128rmikz:
28090 case VMINMAXPSZ128rri:
28091 case VMINMAXPSZ128rrik:
28092 case VMINMAXPSZ128rrikz:
28093 case VMINMAXPSZ256rmbi:
28094 case VMINMAXPSZ256rmbik:
28095 case VMINMAXPSZ256rmbikz:
28096 case VMINMAXPSZ256rmi:
28097 case VMINMAXPSZ256rmik:
28098 case VMINMAXPSZ256rmikz:
28099 case VMINMAXPSZ256rri:
28100 case VMINMAXPSZ256rrik:
28101 case VMINMAXPSZ256rrikz:
28102 case VMINMAXPSZrmbi:
28103 case VMINMAXPSZrmbik:
28104 case VMINMAXPSZrmbikz:
28105 case VMINMAXPSZrmi:
28106 case VMINMAXPSZrmik:
28107 case VMINMAXPSZrmikz:
28108 case VMINMAXPSZrri:
28109 case VMINMAXPSZrrib:
28110 case VMINMAXPSZrribk:
28111 case VMINMAXPSZrribkz:
28112 case VMINMAXPSZrrik:
28113 case VMINMAXPSZrrikz:
28114 return true;
28115 }
28116 return false;
28117}
28118
28119bool isPSIGNW(unsigned Opcode) {
28120 switch (Opcode) {
28121 case MMX_PSIGNWrm:
28122 case MMX_PSIGNWrr:
28123 case PSIGNWrm:
28124 case PSIGNWrr:
28125 return true;
28126 }
28127 return false;
28128}
28129
28130bool isUNPCKLPD(unsigned Opcode) {
28131 switch (Opcode) {
28132 case UNPCKLPDrm:
28133 case UNPCKLPDrr:
28134 return true;
28135 }
28136 return false;
28137}
28138
28139bool isPUSHP(unsigned Opcode) {
28140 return Opcode == PUSHP64r;
28141}
28142
28143bool isBLSI(unsigned Opcode) {
28144 switch (Opcode) {
28145 case BLSI32rm:
28146 case BLSI32rm_EVEX:
28147 case BLSI32rm_NF:
28148 case BLSI32rr:
28149 case BLSI32rr_EVEX:
28150 case BLSI32rr_NF:
28151 case BLSI64rm:
28152 case BLSI64rm_EVEX:
28153 case BLSI64rm_NF:
28154 case BLSI64rr:
28155 case BLSI64rr_EVEX:
28156 case BLSI64rr_NF:
28157 return true;
28158 }
28159 return false;
28160}
28161
28162bool isVPTESTNMB(unsigned Opcode) {
28163 switch (Opcode) {
28164 case VPTESTNMBZ128rm:
28165 case VPTESTNMBZ128rmk:
28166 case VPTESTNMBZ128rr:
28167 case VPTESTNMBZ128rrk:
28168 case VPTESTNMBZ256rm:
28169 case VPTESTNMBZ256rmk:
28170 case VPTESTNMBZ256rr:
28171 case VPTESTNMBZ256rrk:
28172 case VPTESTNMBZrm:
28173 case VPTESTNMBZrmk:
28174 case VPTESTNMBZrr:
28175 case VPTESTNMBZrrk:
28176 return true;
28177 }
28178 return false;
28179}
28180
28181bool isWRUSSQ(unsigned Opcode) {
28182 switch (Opcode) {
28183 case WRUSSQ:
28184 case WRUSSQ_EVEX:
28185 return true;
28186 }
28187 return false;
28188}
28189
28190bool isVGF2P8MULB(unsigned Opcode) {
28191 switch (Opcode) {
28192 case VGF2P8MULBYrm:
28193 case VGF2P8MULBYrr:
28194 case VGF2P8MULBZ128rm:
28195 case VGF2P8MULBZ128rmk:
28196 case VGF2P8MULBZ128rmkz:
28197 case VGF2P8MULBZ128rr:
28198 case VGF2P8MULBZ128rrk:
28199 case VGF2P8MULBZ128rrkz:
28200 case VGF2P8MULBZ256rm:
28201 case VGF2P8MULBZ256rmk:
28202 case VGF2P8MULBZ256rmkz:
28203 case VGF2P8MULBZ256rr:
28204 case VGF2P8MULBZ256rrk:
28205 case VGF2P8MULBZ256rrkz:
28206 case VGF2P8MULBZrm:
28207 case VGF2P8MULBZrmk:
28208 case VGF2P8MULBZrmkz:
28209 case VGF2P8MULBZrr:
28210 case VGF2P8MULBZrrk:
28211 case VGF2P8MULBZrrkz:
28212 case VGF2P8MULBrm:
28213 case VGF2P8MULBrr:
28214 return true;
28215 }
28216 return false;
28217}
28218
28219bool isVPUNPCKLBW(unsigned Opcode) {
28220 switch (Opcode) {
28221 case VPUNPCKLBWYrm:
28222 case VPUNPCKLBWYrr:
28223 case VPUNPCKLBWZ128rm:
28224 case VPUNPCKLBWZ128rmk:
28225 case VPUNPCKLBWZ128rmkz:
28226 case VPUNPCKLBWZ128rr:
28227 case VPUNPCKLBWZ128rrk:
28228 case VPUNPCKLBWZ128rrkz:
28229 case VPUNPCKLBWZ256rm:
28230 case VPUNPCKLBWZ256rmk:
28231 case VPUNPCKLBWZ256rmkz:
28232 case VPUNPCKLBWZ256rr:
28233 case VPUNPCKLBWZ256rrk:
28234 case VPUNPCKLBWZ256rrkz:
28235 case VPUNPCKLBWZrm:
28236 case VPUNPCKLBWZrmk:
28237 case VPUNPCKLBWZrmkz:
28238 case VPUNPCKLBWZrr:
28239 case VPUNPCKLBWZrrk:
28240 case VPUNPCKLBWZrrkz:
28241 case VPUNPCKLBWrm:
28242 case VPUNPCKLBWrr:
28243 return true;
28244 }
28245 return false;
28246}
28247
28248bool isVRANGESD(unsigned Opcode) {
28249 switch (Opcode) {
28250 case VRANGESDZrmi:
28251 case VRANGESDZrmik:
28252 case VRANGESDZrmikz:
28253 case VRANGESDZrri:
28254 case VRANGESDZrrib:
28255 case VRANGESDZrribk:
28256 case VRANGESDZrribkz:
28257 case VRANGESDZrrik:
28258 case VRANGESDZrrikz:
28259 return true;
28260 }
28261 return false;
28262}
28263
28264bool isCLD(unsigned Opcode) {
28265 return Opcode == CLD;
28266}
28267
28268bool isVSCALEFPD(unsigned Opcode) {
28269 switch (Opcode) {
28270 case VSCALEFPDZ128rm:
28271 case VSCALEFPDZ128rmb:
28272 case VSCALEFPDZ128rmbk:
28273 case VSCALEFPDZ128rmbkz:
28274 case VSCALEFPDZ128rmk:
28275 case VSCALEFPDZ128rmkz:
28276 case VSCALEFPDZ128rr:
28277 case VSCALEFPDZ128rrk:
28278 case VSCALEFPDZ128rrkz:
28279 case VSCALEFPDZ256rm:
28280 case VSCALEFPDZ256rmb:
28281 case VSCALEFPDZ256rmbk:
28282 case VSCALEFPDZ256rmbkz:
28283 case VSCALEFPDZ256rmk:
28284 case VSCALEFPDZ256rmkz:
28285 case VSCALEFPDZ256rr:
28286 case VSCALEFPDZ256rrk:
28287 case VSCALEFPDZ256rrkz:
28288 case VSCALEFPDZrm:
28289 case VSCALEFPDZrmb:
28290 case VSCALEFPDZrmbk:
28291 case VSCALEFPDZrmbkz:
28292 case VSCALEFPDZrmk:
28293 case VSCALEFPDZrmkz:
28294 case VSCALEFPDZrr:
28295 case VSCALEFPDZrrb:
28296 case VSCALEFPDZrrbk:
28297 case VSCALEFPDZrrbkz:
28298 case VSCALEFPDZrrk:
28299 case VSCALEFPDZrrkz:
28300 return true;
28301 }
28302 return false;
28303}
28304
28305bool isVCOMXSS(unsigned Opcode) {
28306 switch (Opcode) {
28307 case VCOMXSSZrm_Int:
28308 case VCOMXSSZrr_Int:
28309 case VCOMXSSZrrb_Int:
28310 return true;
28311 }
28312 return false;
28313}
28314
28315bool isVPERMQ(unsigned Opcode) {
28316 switch (Opcode) {
28317 case VPERMQYmi:
28318 case VPERMQYri:
28319 case VPERMQZ256mbi:
28320 case VPERMQZ256mbik:
28321 case VPERMQZ256mbikz:
28322 case VPERMQZ256mi:
28323 case VPERMQZ256mik:
28324 case VPERMQZ256mikz:
28325 case VPERMQZ256ri:
28326 case VPERMQZ256rik:
28327 case VPERMQZ256rikz:
28328 case VPERMQZ256rm:
28329 case VPERMQZ256rmb:
28330 case VPERMQZ256rmbk:
28331 case VPERMQZ256rmbkz:
28332 case VPERMQZ256rmk:
28333 case VPERMQZ256rmkz:
28334 case VPERMQZ256rr:
28335 case VPERMQZ256rrk:
28336 case VPERMQZ256rrkz:
28337 case VPERMQZmbi:
28338 case VPERMQZmbik:
28339 case VPERMQZmbikz:
28340 case VPERMQZmi:
28341 case VPERMQZmik:
28342 case VPERMQZmikz:
28343 case VPERMQZri:
28344 case VPERMQZrik:
28345 case VPERMQZrikz:
28346 case VPERMQZrm:
28347 case VPERMQZrmb:
28348 case VPERMQZrmbk:
28349 case VPERMQZrmbkz:
28350 case VPERMQZrmk:
28351 case VPERMQZrmkz:
28352 case VPERMQZrr:
28353 case VPERMQZrrk:
28354 case VPERMQZrrkz:
28355 return true;
28356 }
28357 return false;
28358}
28359
28360bool isVPSHLDVW(unsigned Opcode) {
28361 switch (Opcode) {
28362 case VPSHLDVWZ128m:
28363 case VPSHLDVWZ128mk:
28364 case VPSHLDVWZ128mkz:
28365 case VPSHLDVWZ128r:
28366 case VPSHLDVWZ128rk:
28367 case VPSHLDVWZ128rkz:
28368 case VPSHLDVWZ256m:
28369 case VPSHLDVWZ256mk:
28370 case VPSHLDVWZ256mkz:
28371 case VPSHLDVWZ256r:
28372 case VPSHLDVWZ256rk:
28373 case VPSHLDVWZ256rkz:
28374 case VPSHLDVWZm:
28375 case VPSHLDVWZmk:
28376 case VPSHLDVWZmkz:
28377 case VPSHLDVWZr:
28378 case VPSHLDVWZrk:
28379 case VPSHLDVWZrkz:
28380 return true;
28381 }
28382 return false;
28383}
28384
28385bool isROR(unsigned Opcode) {
28386 switch (Opcode) {
28387 case ROR16m1:
28388 case ROR16m1_EVEX:
28389 case ROR16m1_ND:
28390 case ROR16m1_NF:
28391 case ROR16m1_NF_ND:
28392 case ROR16mCL:
28393 case ROR16mCL_EVEX:
28394 case ROR16mCL_ND:
28395 case ROR16mCL_NF:
28396 case ROR16mCL_NF_ND:
28397 case ROR16mi:
28398 case ROR16mi_EVEX:
28399 case ROR16mi_ND:
28400 case ROR16mi_NF:
28401 case ROR16mi_NF_ND:
28402 case ROR16r1:
28403 case ROR16r1_EVEX:
28404 case ROR16r1_ND:
28405 case ROR16r1_NF:
28406 case ROR16r1_NF_ND:
28407 case ROR16rCL:
28408 case ROR16rCL_EVEX:
28409 case ROR16rCL_ND:
28410 case ROR16rCL_NF:
28411 case ROR16rCL_NF_ND:
28412 case ROR16ri:
28413 case ROR16ri_EVEX:
28414 case ROR16ri_ND:
28415 case ROR16ri_NF:
28416 case ROR16ri_NF_ND:
28417 case ROR32m1:
28418 case ROR32m1_EVEX:
28419 case ROR32m1_ND:
28420 case ROR32m1_NF:
28421 case ROR32m1_NF_ND:
28422 case ROR32mCL:
28423 case ROR32mCL_EVEX:
28424 case ROR32mCL_ND:
28425 case ROR32mCL_NF:
28426 case ROR32mCL_NF_ND:
28427 case ROR32mi:
28428 case ROR32mi_EVEX:
28429 case ROR32mi_ND:
28430 case ROR32mi_NF:
28431 case ROR32mi_NF_ND:
28432 case ROR32r1:
28433 case ROR32r1_EVEX:
28434 case ROR32r1_ND:
28435 case ROR32r1_NF:
28436 case ROR32r1_NF_ND:
28437 case ROR32rCL:
28438 case ROR32rCL_EVEX:
28439 case ROR32rCL_ND:
28440 case ROR32rCL_NF:
28441 case ROR32rCL_NF_ND:
28442 case ROR32ri:
28443 case ROR32ri_EVEX:
28444 case ROR32ri_ND:
28445 case ROR32ri_NF:
28446 case ROR32ri_NF_ND:
28447 case ROR64m1:
28448 case ROR64m1_EVEX:
28449 case ROR64m1_ND:
28450 case ROR64m1_NF:
28451 case ROR64m1_NF_ND:
28452 case ROR64mCL:
28453 case ROR64mCL_EVEX:
28454 case ROR64mCL_ND:
28455 case ROR64mCL_NF:
28456 case ROR64mCL_NF_ND:
28457 case ROR64mi:
28458 case ROR64mi_EVEX:
28459 case ROR64mi_ND:
28460 case ROR64mi_NF:
28461 case ROR64mi_NF_ND:
28462 case ROR64r1:
28463 case ROR64r1_EVEX:
28464 case ROR64r1_ND:
28465 case ROR64r1_NF:
28466 case ROR64r1_NF_ND:
28467 case ROR64rCL:
28468 case ROR64rCL_EVEX:
28469 case ROR64rCL_ND:
28470 case ROR64rCL_NF:
28471 case ROR64rCL_NF_ND:
28472 case ROR64ri:
28473 case ROR64ri_EVEX:
28474 case ROR64ri_ND:
28475 case ROR64ri_NF:
28476 case ROR64ri_NF_ND:
28477 case ROR8m1:
28478 case ROR8m1_EVEX:
28479 case ROR8m1_ND:
28480 case ROR8m1_NF:
28481 case ROR8m1_NF_ND:
28482 case ROR8mCL:
28483 case ROR8mCL_EVEX:
28484 case ROR8mCL_ND:
28485 case ROR8mCL_NF:
28486 case ROR8mCL_NF_ND:
28487 case ROR8mi:
28488 case ROR8mi_EVEX:
28489 case ROR8mi_ND:
28490 case ROR8mi_NF:
28491 case ROR8mi_NF_ND:
28492 case ROR8r1:
28493 case ROR8r1_EVEX:
28494 case ROR8r1_ND:
28495 case ROR8r1_NF:
28496 case ROR8r1_NF_ND:
28497 case ROR8rCL:
28498 case ROR8rCL_EVEX:
28499 case ROR8rCL_ND:
28500 case ROR8rCL_NF:
28501 case ROR8rCL_NF_ND:
28502 case ROR8ri:
28503 case ROR8ri_EVEX:
28504 case ROR8ri_ND:
28505 case ROR8ri_NF:
28506 case ROR8ri_NF_ND:
28507 return true;
28508 }
28509 return false;
28510}
28511
28512bool isVFMADDSUB132PH(unsigned Opcode) {
28513 switch (Opcode) {
28514 case VFMADDSUB132PHZ128m:
28515 case VFMADDSUB132PHZ128mb:
28516 case VFMADDSUB132PHZ128mbk:
28517 case VFMADDSUB132PHZ128mbkz:
28518 case VFMADDSUB132PHZ128mk:
28519 case VFMADDSUB132PHZ128mkz:
28520 case VFMADDSUB132PHZ128r:
28521 case VFMADDSUB132PHZ128rk:
28522 case VFMADDSUB132PHZ128rkz:
28523 case VFMADDSUB132PHZ256m:
28524 case VFMADDSUB132PHZ256mb:
28525 case VFMADDSUB132PHZ256mbk:
28526 case VFMADDSUB132PHZ256mbkz:
28527 case VFMADDSUB132PHZ256mk:
28528 case VFMADDSUB132PHZ256mkz:
28529 case VFMADDSUB132PHZ256r:
28530 case VFMADDSUB132PHZ256rk:
28531 case VFMADDSUB132PHZ256rkz:
28532 case VFMADDSUB132PHZm:
28533 case VFMADDSUB132PHZmb:
28534 case VFMADDSUB132PHZmbk:
28535 case VFMADDSUB132PHZmbkz:
28536 case VFMADDSUB132PHZmk:
28537 case VFMADDSUB132PHZmkz:
28538 case VFMADDSUB132PHZr:
28539 case VFMADDSUB132PHZrb:
28540 case VFMADDSUB132PHZrbk:
28541 case VFMADDSUB132PHZrbkz:
28542 case VFMADDSUB132PHZrk:
28543 case VFMADDSUB132PHZrkz:
28544 return true;
28545 }
28546 return false;
28547}
28548
28549bool isDEC(unsigned Opcode) {
28550 switch (Opcode) {
28551 case DEC16m:
28552 case DEC16m_EVEX:
28553 case DEC16m_ND:
28554 case DEC16m_NF:
28555 case DEC16m_NF_ND:
28556 case DEC16r:
28557 case DEC16r_EVEX:
28558 case DEC16r_ND:
28559 case DEC16r_NF:
28560 case DEC16r_NF_ND:
28561 case DEC16r_alt:
28562 case DEC32m:
28563 case DEC32m_EVEX:
28564 case DEC32m_ND:
28565 case DEC32m_NF:
28566 case DEC32m_NF_ND:
28567 case DEC32r:
28568 case DEC32r_EVEX:
28569 case DEC32r_ND:
28570 case DEC32r_NF:
28571 case DEC32r_NF_ND:
28572 case DEC32r_alt:
28573 case DEC64m:
28574 case DEC64m_EVEX:
28575 case DEC64m_ND:
28576 case DEC64m_NF:
28577 case DEC64m_NF_ND:
28578 case DEC64r:
28579 case DEC64r_EVEX:
28580 case DEC64r_ND:
28581 case DEC64r_NF:
28582 case DEC64r_NF_ND:
28583 case DEC8m:
28584 case DEC8m_EVEX:
28585 case DEC8m_ND:
28586 case DEC8m_NF:
28587 case DEC8m_NF_ND:
28588 case DEC8r:
28589 case DEC8r_EVEX:
28590 case DEC8r_ND:
28591 case DEC8r_NF:
28592 case DEC8r_NF_ND:
28593 return true;
28594 }
28595 return false;
28596}
28597
28598bool isVGETEXPSH(unsigned Opcode) {
28599 switch (Opcode) {
28600 case VGETEXPSHZm:
28601 case VGETEXPSHZmk:
28602 case VGETEXPSHZmkz:
28603 case VGETEXPSHZr:
28604 case VGETEXPSHZrb:
28605 case VGETEXPSHZrbk:
28606 case VGETEXPSHZrbkz:
28607 case VGETEXPSHZrk:
28608 case VGETEXPSHZrkz:
28609 return true;
28610 }
28611 return false;
28612}
28613
28614bool isAESDEC(unsigned Opcode) {
28615 switch (Opcode) {
28616 case AESDECrm:
28617 case AESDECrr:
28618 return true;
28619 }
28620 return false;
28621}
28622
28623bool isKORD(unsigned Opcode) {
28624 return Opcode == KORDkk;
28625}
28626
28627bool isTILELOADDT1(unsigned Opcode) {
28628 switch (Opcode) {
28629 case TILELOADDT1:
28630 case TILELOADDT1_EVEX:
28631 return true;
28632 }
28633 return false;
28634}
28635
28636bool isVPMULHW(unsigned Opcode) {
28637 switch (Opcode) {
28638 case VPMULHWYrm:
28639 case VPMULHWYrr:
28640 case VPMULHWZ128rm:
28641 case VPMULHWZ128rmk:
28642 case VPMULHWZ128rmkz:
28643 case VPMULHWZ128rr:
28644 case VPMULHWZ128rrk:
28645 case VPMULHWZ128rrkz:
28646 case VPMULHWZ256rm:
28647 case VPMULHWZ256rmk:
28648 case VPMULHWZ256rmkz:
28649 case VPMULHWZ256rr:
28650 case VPMULHWZ256rrk:
28651 case VPMULHWZ256rrkz:
28652 case VPMULHWZrm:
28653 case VPMULHWZrmk:
28654 case VPMULHWZrmkz:
28655 case VPMULHWZrr:
28656 case VPMULHWZrrk:
28657 case VPMULHWZrrkz:
28658 case VPMULHWrm:
28659 case VPMULHWrr:
28660 return true;
28661 }
28662 return false;
28663}
28664
28665bool isVMASKMOVPS(unsigned Opcode) {
28666 switch (Opcode) {
28667 case VMASKMOVPSYmr:
28668 case VMASKMOVPSYrm:
28669 case VMASKMOVPSmr:
28670 case VMASKMOVPSrm:
28671 return true;
28672 }
28673 return false;
28674}
28675
28676bool isPMOVZXDQ(unsigned Opcode) {
28677 switch (Opcode) {
28678 case PMOVZXDQrm:
28679 case PMOVZXDQrr:
28680 return true;
28681 }
28682 return false;
28683}
28684
28685bool isVCVTPS2PH(unsigned Opcode) {
28686 switch (Opcode) {
28687 case VCVTPS2PHYmr:
28688 case VCVTPS2PHYrr:
28689 case VCVTPS2PHZ128mr:
28690 case VCVTPS2PHZ128mrk:
28691 case VCVTPS2PHZ128rr:
28692 case VCVTPS2PHZ128rrk:
28693 case VCVTPS2PHZ128rrkz:
28694 case VCVTPS2PHZ256mr:
28695 case VCVTPS2PHZ256mrk:
28696 case VCVTPS2PHZ256rr:
28697 case VCVTPS2PHZ256rrk:
28698 case VCVTPS2PHZ256rrkz:
28699 case VCVTPS2PHZmr:
28700 case VCVTPS2PHZmrk:
28701 case VCVTPS2PHZrr:
28702 case VCVTPS2PHZrrb:
28703 case VCVTPS2PHZrrbk:
28704 case VCVTPS2PHZrrbkz:
28705 case VCVTPS2PHZrrk:
28706 case VCVTPS2PHZrrkz:
28707 case VCVTPS2PHmr:
28708 case VCVTPS2PHrr:
28709 return true;
28710 }
28711 return false;
28712}
28713
28714bool isCVTDQ2PD(unsigned Opcode) {
28715 switch (Opcode) {
28716 case CVTDQ2PDrm:
28717 case CVTDQ2PDrr:
28718 return true;
28719 }
28720 return false;
28721}
28722
28723bool isVCVTSD2SS(unsigned Opcode) {
28724 switch (Opcode) {
28725 case VCVTSD2SSZrm_Int:
28726 case VCVTSD2SSZrmk_Int:
28727 case VCVTSD2SSZrmkz_Int:
28728 case VCVTSD2SSZrr_Int:
28729 case VCVTSD2SSZrrb_Int:
28730 case VCVTSD2SSZrrbk_Int:
28731 case VCVTSD2SSZrrbkz_Int:
28732 case VCVTSD2SSZrrk_Int:
28733 case VCVTSD2SSZrrkz_Int:
28734 case VCVTSD2SSrm_Int:
28735 case VCVTSD2SSrr_Int:
28736 return true;
28737 }
28738 return false;
28739}
28740
28741bool isVFMSUB213PH(unsigned Opcode) {
28742 switch (Opcode) {
28743 case VFMSUB213PHZ128m:
28744 case VFMSUB213PHZ128mb:
28745 case VFMSUB213PHZ128mbk:
28746 case VFMSUB213PHZ128mbkz:
28747 case VFMSUB213PHZ128mk:
28748 case VFMSUB213PHZ128mkz:
28749 case VFMSUB213PHZ128r:
28750 case VFMSUB213PHZ128rk:
28751 case VFMSUB213PHZ128rkz:
28752 case VFMSUB213PHZ256m:
28753 case VFMSUB213PHZ256mb:
28754 case VFMSUB213PHZ256mbk:
28755 case VFMSUB213PHZ256mbkz:
28756 case VFMSUB213PHZ256mk:
28757 case VFMSUB213PHZ256mkz:
28758 case VFMSUB213PHZ256r:
28759 case VFMSUB213PHZ256rk:
28760 case VFMSUB213PHZ256rkz:
28761 case VFMSUB213PHZm:
28762 case VFMSUB213PHZmb:
28763 case VFMSUB213PHZmbk:
28764 case VFMSUB213PHZmbkz:
28765 case VFMSUB213PHZmk:
28766 case VFMSUB213PHZmkz:
28767 case VFMSUB213PHZr:
28768 case VFMSUB213PHZrb:
28769 case VFMSUB213PHZrbk:
28770 case VFMSUB213PHZrbkz:
28771 case VFMSUB213PHZrk:
28772 case VFMSUB213PHZrkz:
28773 return true;
28774 }
28775 return false;
28776}
28777
28778bool isVPROTB(unsigned Opcode) {
28779 switch (Opcode) {
28780 case VPROTBmi:
28781 case VPROTBmr:
28782 case VPROTBri:
28783 case VPROTBrm:
28784 case VPROTBrr:
28785 case VPROTBrr_REV:
28786 return true;
28787 }
28788 return false;
28789}
28790
28791bool isPINSRD(unsigned Opcode) {
28792 switch (Opcode) {
28793 case PINSRDrmi:
28794 case PINSRDrri:
28795 return true;
28796 }
28797 return false;
28798}
28799
28800bool isVMXON(unsigned Opcode) {
28801 return Opcode == VMXON;
28802}
28803
28804bool isVFCMULCSH(unsigned Opcode) {
28805 switch (Opcode) {
28806 case VFCMULCSHZrm:
28807 case VFCMULCSHZrmk:
28808 case VFCMULCSHZrmkz:
28809 case VFCMULCSHZrr:
28810 case VFCMULCSHZrrb:
28811 case VFCMULCSHZrrbk:
28812 case VFCMULCSHZrrbkz:
28813 case VFCMULCSHZrrk:
28814 case VFCMULCSHZrrkz:
28815 return true;
28816 }
28817 return false;
28818}
28819
28820bool isVFMULCSH(unsigned Opcode) {
28821 switch (Opcode) {
28822 case VFMULCSHZrm:
28823 case VFMULCSHZrmk:
28824 case VFMULCSHZrmkz:
28825 case VFMULCSHZrr:
28826 case VFMULCSHZrrb:
28827 case VFMULCSHZrrbk:
28828 case VFMULCSHZrrbkz:
28829 case VFMULCSHZrrk:
28830 case VFMULCSHZrrkz:
28831 return true;
28832 }
28833 return false;
28834}
28835
28836bool isVRANGEPD(unsigned Opcode) {
28837 switch (Opcode) {
28838 case VRANGEPDZ128rmbi:
28839 case VRANGEPDZ128rmbik:
28840 case VRANGEPDZ128rmbikz:
28841 case VRANGEPDZ128rmi:
28842 case VRANGEPDZ128rmik:
28843 case VRANGEPDZ128rmikz:
28844 case VRANGEPDZ128rri:
28845 case VRANGEPDZ128rrik:
28846 case VRANGEPDZ128rrikz:
28847 case VRANGEPDZ256rmbi:
28848 case VRANGEPDZ256rmbik:
28849 case VRANGEPDZ256rmbikz:
28850 case VRANGEPDZ256rmi:
28851 case VRANGEPDZ256rmik:
28852 case VRANGEPDZ256rmikz:
28853 case VRANGEPDZ256rri:
28854 case VRANGEPDZ256rrik:
28855 case VRANGEPDZ256rrikz:
28856 case VRANGEPDZrmbi:
28857 case VRANGEPDZrmbik:
28858 case VRANGEPDZrmbikz:
28859 case VRANGEPDZrmi:
28860 case VRANGEPDZrmik:
28861 case VRANGEPDZrmikz:
28862 case VRANGEPDZrri:
28863 case VRANGEPDZrrib:
28864 case VRANGEPDZrribk:
28865 case VRANGEPDZrribkz:
28866 case VRANGEPDZrrik:
28867 case VRANGEPDZrrikz:
28868 return true;
28869 }
28870 return false;
28871}
28872
28873bool isCMC(unsigned Opcode) {
28874 return Opcode == CMC;
28875}
28876
28877bool isVFNMADD231BF16(unsigned Opcode) {
28878 switch (Opcode) {
28879 case VFNMADD231BF16Z128m:
28880 case VFNMADD231BF16Z128mb:
28881 case VFNMADD231BF16Z128mbk:
28882 case VFNMADD231BF16Z128mbkz:
28883 case VFNMADD231BF16Z128mk:
28884 case VFNMADD231BF16Z128mkz:
28885 case VFNMADD231BF16Z128r:
28886 case VFNMADD231BF16Z128rk:
28887 case VFNMADD231BF16Z128rkz:
28888 case VFNMADD231BF16Z256m:
28889 case VFNMADD231BF16Z256mb:
28890 case VFNMADD231BF16Z256mbk:
28891 case VFNMADD231BF16Z256mbkz:
28892 case VFNMADD231BF16Z256mk:
28893 case VFNMADD231BF16Z256mkz:
28894 case VFNMADD231BF16Z256r:
28895 case VFNMADD231BF16Z256rk:
28896 case VFNMADD231BF16Z256rkz:
28897 case VFNMADD231BF16Zm:
28898 case VFNMADD231BF16Zmb:
28899 case VFNMADD231BF16Zmbk:
28900 case VFNMADD231BF16Zmbkz:
28901 case VFNMADD231BF16Zmk:
28902 case VFNMADD231BF16Zmkz:
28903 case VFNMADD231BF16Zr:
28904 case VFNMADD231BF16Zrk:
28905 case VFNMADD231BF16Zrkz:
28906 return true;
28907 }
28908 return false;
28909}
28910
28911bool isSHA256MSG1(unsigned Opcode) {
28912 switch (Opcode) {
28913 case SHA256MSG1rm:
28914 case SHA256MSG1rr:
28915 return true;
28916 }
28917 return false;
28918}
28919
28920bool isFLD1(unsigned Opcode) {
28921 return Opcode == LD_F1;
28922}
28923
28924bool isCMPPS(unsigned Opcode) {
28925 switch (Opcode) {
28926 case CMPPSrmi:
28927 case CMPPSrri:
28928 return true;
28929 }
28930 return false;
28931}
28932
28933bool isVPAVGW(unsigned Opcode) {
28934 switch (Opcode) {
28935 case VPAVGWYrm:
28936 case VPAVGWYrr:
28937 case VPAVGWZ128rm:
28938 case VPAVGWZ128rmk:
28939 case VPAVGWZ128rmkz:
28940 case VPAVGWZ128rr:
28941 case VPAVGWZ128rrk:
28942 case VPAVGWZ128rrkz:
28943 case VPAVGWZ256rm:
28944 case VPAVGWZ256rmk:
28945 case VPAVGWZ256rmkz:
28946 case VPAVGWZ256rr:
28947 case VPAVGWZ256rrk:
28948 case VPAVGWZ256rrkz:
28949 case VPAVGWZrm:
28950 case VPAVGWZrmk:
28951 case VPAVGWZrmkz:
28952 case VPAVGWZrr:
28953 case VPAVGWZrrk:
28954 case VPAVGWZrrkz:
28955 case VPAVGWrm:
28956 case VPAVGWrr:
28957 return true;
28958 }
28959 return false;
28960}
28961
28962bool isVFMADD213SH(unsigned Opcode) {
28963 switch (Opcode) {
28964 case VFMADD213SHZm_Int:
28965 case VFMADD213SHZmk_Int:
28966 case VFMADD213SHZmkz_Int:
28967 case VFMADD213SHZr_Int:
28968 case VFMADD213SHZrb_Int:
28969 case VFMADD213SHZrbk_Int:
28970 case VFMADD213SHZrbkz_Int:
28971 case VFMADD213SHZrk_Int:
28972 case VFMADD213SHZrkz_Int:
28973 return true;
28974 }
28975 return false;
28976}
28977
28978bool isVPCMPESTRMQ(unsigned Opcode) {
28979 switch (Opcode) {
28980 case VPCMPESTRMQrmi:
28981 case VPCMPESTRMQrri:
28982 return true;
28983 }
28984 return false;
28985}
28986
28987bool isVPINSRQ(unsigned Opcode) {
28988 switch (Opcode) {
28989 case VPINSRQZrmi:
28990 case VPINSRQZrri:
28991 case VPINSRQrmi:
28992 case VPINSRQrri:
28993 return true;
28994 }
28995 return false;
28996}
28997
28998bool isMOVABS(unsigned Opcode) {
28999 switch (Opcode) {
29000 case MOV16ao64:
29001 case MOV16o64a:
29002 case MOV32ao64:
29003 case MOV32o64a:
29004 case MOV64ao64:
29005 case MOV64o64a:
29006 case MOV64ri:
29007 case MOV8ao64:
29008 case MOV8o64a:
29009 return true;
29010 }
29011 return false;
29012}
29013
29014bool isVPSHAQ(unsigned Opcode) {
29015 switch (Opcode) {
29016 case VPSHAQmr:
29017 case VPSHAQrm:
29018 case VPSHAQrr:
29019 case VPSHAQrr_REV:
29020 return true;
29021 }
29022 return false;
29023}
29024
29025bool isRDTSCP(unsigned Opcode) {
29026 return Opcode == RDTSCP;
29027}
29028
29029bool isVFNMADD231SS(unsigned Opcode) {
29030 switch (Opcode) {
29031 case VFNMADD231SSZm_Int:
29032 case VFNMADD231SSZmk_Int:
29033 case VFNMADD231SSZmkz_Int:
29034 case VFNMADD231SSZr_Int:
29035 case VFNMADD231SSZrb_Int:
29036 case VFNMADD231SSZrbk_Int:
29037 case VFNMADD231SSZrbkz_Int:
29038 case VFNMADD231SSZrk_Int:
29039 case VFNMADD231SSZrkz_Int:
29040 case VFNMADD231SSm_Int:
29041 case VFNMADD231SSr_Int:
29042 return true;
29043 }
29044 return false;
29045}
29046
29047bool isTEST(unsigned Opcode) {
29048 switch (Opcode) {
29049 case TEST16i16:
29050 case TEST16mi:
29051 case TEST16mr:
29052 case TEST16ri:
29053 case TEST16rr:
29054 case TEST32i32:
29055 case TEST32mi:
29056 case TEST32mr:
29057 case TEST32ri:
29058 case TEST32rr:
29059 case TEST64i32:
29060 case TEST64mi32:
29061 case TEST64mr:
29062 case TEST64ri32:
29063 case TEST64rr:
29064 case TEST8i8:
29065 case TEST8mi:
29066 case TEST8mr:
29067 case TEST8ri:
29068 case TEST8rr:
29069 return true;
29070 }
29071 return false;
29072}
29073
29074bool isVPERMD(unsigned Opcode) {
29075 switch (Opcode) {
29076 case VPERMDYrm:
29077 case VPERMDYrr:
29078 case VPERMDZ256rm:
29079 case VPERMDZ256rmb:
29080 case VPERMDZ256rmbk:
29081 case VPERMDZ256rmbkz:
29082 case VPERMDZ256rmk:
29083 case VPERMDZ256rmkz:
29084 case VPERMDZ256rr:
29085 case VPERMDZ256rrk:
29086 case VPERMDZ256rrkz:
29087 case VPERMDZrm:
29088 case VPERMDZrmb:
29089 case VPERMDZrmbk:
29090 case VPERMDZrmbkz:
29091 case VPERMDZrmk:
29092 case VPERMDZrmkz:
29093 case VPERMDZrr:
29094 case VPERMDZrrk:
29095 case VPERMDZrrkz:
29096 return true;
29097 }
29098 return false;
29099}
29100
29101bool isVBCSTNESH2PS(unsigned Opcode) {
29102 switch (Opcode) {
29103 case VBCSTNESH2PSYrm:
29104 case VBCSTNESH2PSrm:
29105 return true;
29106 }
29107 return false;
29108}
29109
29110bool isVGATHERPF0QPD(unsigned Opcode) {
29111 return Opcode == VGATHERPF0QPDm;
29112}
29113
29114bool isVPERM2I128(unsigned Opcode) {
29115 switch (Opcode) {
29116 case VPERM2I128rmi:
29117 case VPERM2I128rri:
29118 return true;
29119 }
29120 return false;
29121}
29122
29123bool isVMPSADBW(unsigned Opcode) {
29124 switch (Opcode) {
29125 case VMPSADBWYrmi:
29126 case VMPSADBWYrri:
29127 case VMPSADBWZ128rmi:
29128 case VMPSADBWZ128rmik:
29129 case VMPSADBWZ128rmikz:
29130 case VMPSADBWZ128rri:
29131 case VMPSADBWZ128rrik:
29132 case VMPSADBWZ128rrikz:
29133 case VMPSADBWZ256rmi:
29134 case VMPSADBWZ256rmik:
29135 case VMPSADBWZ256rmikz:
29136 case VMPSADBWZ256rri:
29137 case VMPSADBWZ256rrik:
29138 case VMPSADBWZ256rrikz:
29139 case VMPSADBWZrmi:
29140 case VMPSADBWZrmik:
29141 case VMPSADBWZrmikz:
29142 case VMPSADBWZrri:
29143 case VMPSADBWZrrik:
29144 case VMPSADBWZrrikz:
29145 case VMPSADBWrmi:
29146 case VMPSADBWrri:
29147 return true;
29148 }
29149 return false;
29150}
29151
29152bool isVFNMSUB231PD(unsigned Opcode) {
29153 switch (Opcode) {
29154 case VFNMSUB231PDYm:
29155 case VFNMSUB231PDYr:
29156 case VFNMSUB231PDZ128m:
29157 case VFNMSUB231PDZ128mb:
29158 case VFNMSUB231PDZ128mbk:
29159 case VFNMSUB231PDZ128mbkz:
29160 case VFNMSUB231PDZ128mk:
29161 case VFNMSUB231PDZ128mkz:
29162 case VFNMSUB231PDZ128r:
29163 case VFNMSUB231PDZ128rk:
29164 case VFNMSUB231PDZ128rkz:
29165 case VFNMSUB231PDZ256m:
29166 case VFNMSUB231PDZ256mb:
29167 case VFNMSUB231PDZ256mbk:
29168 case VFNMSUB231PDZ256mbkz:
29169 case VFNMSUB231PDZ256mk:
29170 case VFNMSUB231PDZ256mkz:
29171 case VFNMSUB231PDZ256r:
29172 case VFNMSUB231PDZ256rk:
29173 case VFNMSUB231PDZ256rkz:
29174 case VFNMSUB231PDZm:
29175 case VFNMSUB231PDZmb:
29176 case VFNMSUB231PDZmbk:
29177 case VFNMSUB231PDZmbkz:
29178 case VFNMSUB231PDZmk:
29179 case VFNMSUB231PDZmkz:
29180 case VFNMSUB231PDZr:
29181 case VFNMSUB231PDZrb:
29182 case VFNMSUB231PDZrbk:
29183 case VFNMSUB231PDZrbkz:
29184 case VFNMSUB231PDZrk:
29185 case VFNMSUB231PDZrkz:
29186 case VFNMSUB231PDm:
29187 case VFNMSUB231PDr:
29188 return true;
29189 }
29190 return false;
29191}
29192
29193bool isPADDSB(unsigned Opcode) {
29194 switch (Opcode) {
29195 case MMX_PADDSBrm:
29196 case MMX_PADDSBrr:
29197 case PADDSBrm:
29198 case PADDSBrr:
29199 return true;
29200 }
29201 return false;
29202}
29203
29204bool isMWAITX(unsigned Opcode) {
29205 return Opcode == MWAITXrrr;
29206}
29207
29208bool isMONITORX(unsigned Opcode) {
29209 switch (Opcode) {
29210 case MONITORX32rrr:
29211 case MONITORX64rrr:
29212 return true;
29213 }
29214 return false;
29215}
29216
29217bool isVPEXPANDD(unsigned Opcode) {
29218 switch (Opcode) {
29219 case VPEXPANDDZ128rm:
29220 case VPEXPANDDZ128rmk:
29221 case VPEXPANDDZ128rmkz:
29222 case VPEXPANDDZ128rr:
29223 case VPEXPANDDZ128rrk:
29224 case VPEXPANDDZ128rrkz:
29225 case VPEXPANDDZ256rm:
29226 case VPEXPANDDZ256rmk:
29227 case VPEXPANDDZ256rmkz:
29228 case VPEXPANDDZ256rr:
29229 case VPEXPANDDZ256rrk:
29230 case VPEXPANDDZ256rrkz:
29231 case VPEXPANDDZrm:
29232 case VPEXPANDDZrmk:
29233 case VPEXPANDDZrmkz:
29234 case VPEXPANDDZrr:
29235 case VPEXPANDDZrrk:
29236 case VPEXPANDDZrrkz:
29237 return true;
29238 }
29239 return false;
29240}
29241
29242bool isVFRCZPD(unsigned Opcode) {
29243 switch (Opcode) {
29244 case VFRCZPDYrm:
29245 case VFRCZPDYrr:
29246 case VFRCZPDrm:
29247 case VFRCZPDrr:
29248 return true;
29249 }
29250 return false;
29251}
29252
29253bool isVRCPPH(unsigned Opcode) {
29254 switch (Opcode) {
29255 case VRCPPHZ128m:
29256 case VRCPPHZ128mb:
29257 case VRCPPHZ128mbk:
29258 case VRCPPHZ128mbkz:
29259 case VRCPPHZ128mk:
29260 case VRCPPHZ128mkz:
29261 case VRCPPHZ128r:
29262 case VRCPPHZ128rk:
29263 case VRCPPHZ128rkz:
29264 case VRCPPHZ256m:
29265 case VRCPPHZ256mb:
29266 case VRCPPHZ256mbk:
29267 case VRCPPHZ256mbkz:
29268 case VRCPPHZ256mk:
29269 case VRCPPHZ256mkz:
29270 case VRCPPHZ256r:
29271 case VRCPPHZ256rk:
29272 case VRCPPHZ256rkz:
29273 case VRCPPHZm:
29274 case VRCPPHZmb:
29275 case VRCPPHZmbk:
29276 case VRCPPHZmbkz:
29277 case VRCPPHZmk:
29278 case VRCPPHZmkz:
29279 case VRCPPHZr:
29280 case VRCPPHZrk:
29281 case VRCPPHZrkz:
29282 return true;
29283 }
29284 return false;
29285}
29286
29287bool isFEMMS(unsigned Opcode) {
29288 return Opcode == FEMMS;
29289}
29290
29291bool isVSCATTERQPD(unsigned Opcode) {
29292 switch (Opcode) {
29293 case VSCATTERQPDZ128mr:
29294 case VSCATTERQPDZ256mr:
29295 case VSCATTERQPDZmr:
29296 return true;
29297 }
29298 return false;
29299}
29300
29301bool isVMOVW(unsigned Opcode) {
29302 switch (Opcode) {
29303 case VMOVSH2Wrr:
29304 case VMOVSHtoW64rr:
29305 case VMOVW2SHrr:
29306 case VMOVW64toSHrr:
29307 case VMOVWmr:
29308 case VMOVWrm:
29309 case VMOVZPWILo2PWIZmr:
29310 case VMOVZPWILo2PWIZrm:
29311 case VMOVZPWILo2PWIZrr:
29312 case VMOVZPWILo2PWIZrr2:
29313 return true;
29314 }
29315 return false;
29316}
29317
29318bool isVPBROADCASTD(unsigned Opcode) {
29319 switch (Opcode) {
29320 case VPBROADCASTDYrm:
29321 case VPBROADCASTDYrr:
29322 case VPBROADCASTDZ128rm:
29323 case VPBROADCASTDZ128rmk:
29324 case VPBROADCASTDZ128rmkz:
29325 case VPBROADCASTDZ128rr:
29326 case VPBROADCASTDZ128rrk:
29327 case VPBROADCASTDZ128rrkz:
29328 case VPBROADCASTDZ256rm:
29329 case VPBROADCASTDZ256rmk:
29330 case VPBROADCASTDZ256rmkz:
29331 case VPBROADCASTDZ256rr:
29332 case VPBROADCASTDZ256rrk:
29333 case VPBROADCASTDZ256rrkz:
29334 case VPBROADCASTDZrm:
29335 case VPBROADCASTDZrmk:
29336 case VPBROADCASTDZrmkz:
29337 case VPBROADCASTDZrr:
29338 case VPBROADCASTDZrrk:
29339 case VPBROADCASTDZrrkz:
29340 case VPBROADCASTDrZ128rr:
29341 case VPBROADCASTDrZ128rrk:
29342 case VPBROADCASTDrZ128rrkz:
29343 case VPBROADCASTDrZ256rr:
29344 case VPBROADCASTDrZ256rrk:
29345 case VPBROADCASTDrZ256rrkz:
29346 case VPBROADCASTDrZrr:
29347 case VPBROADCASTDrZrrk:
29348 case VPBROADCASTDrZrrkz:
29349 case VPBROADCASTDrm:
29350 case VPBROADCASTDrr:
29351 return true;
29352 }
29353 return false;
29354}
29355
29356bool isSTOSB(unsigned Opcode) {
29357 return Opcode == STOSB;
29358}
29359
29360bool isFUCOMI(unsigned Opcode) {
29361 return Opcode == UCOM_FIr;
29362}
29363
29364bool isVBROADCASTI64X4(unsigned Opcode) {
29365 switch (Opcode) {
29366 case VBROADCASTI64X4Zrm:
29367 case VBROADCASTI64X4Zrmk:
29368 case VBROADCASTI64X4Zrmkz:
29369 return true;
29370 }
29371 return false;
29372}
29373
29374bool isFCMOVU(unsigned Opcode) {
29375 return Opcode == CMOVP_F;
29376}
29377
29378bool isPSHUFLW(unsigned Opcode) {
29379 switch (Opcode) {
29380 case PSHUFLWmi:
29381 case PSHUFLWri:
29382 return true;
29383 }
29384 return false;
29385}
29386
29387bool isCVTPI2PS(unsigned Opcode) {
29388 switch (Opcode) {
29389 case MMX_CVTPI2PSrm:
29390 case MMX_CVTPI2PSrr:
29391 return true;
29392 }
29393 return false;
29394}
29395
29396bool isVCVTTPD2UDQS(unsigned Opcode) {
29397 switch (Opcode) {
29398 case VCVTTPD2UDQSZ128rm:
29399 case VCVTTPD2UDQSZ128rmb:
29400 case VCVTTPD2UDQSZ128rmbk:
29401 case VCVTTPD2UDQSZ128rmbkz:
29402 case VCVTTPD2UDQSZ128rmk:
29403 case VCVTTPD2UDQSZ128rmkz:
29404 case VCVTTPD2UDQSZ128rr:
29405 case VCVTTPD2UDQSZ128rrk:
29406 case VCVTTPD2UDQSZ128rrkz:
29407 case VCVTTPD2UDQSZ256rm:
29408 case VCVTTPD2UDQSZ256rmb:
29409 case VCVTTPD2UDQSZ256rmbk:
29410 case VCVTTPD2UDQSZ256rmbkz:
29411 case VCVTTPD2UDQSZ256rmk:
29412 case VCVTTPD2UDQSZ256rmkz:
29413 case VCVTTPD2UDQSZ256rr:
29414 case VCVTTPD2UDQSZ256rrb:
29415 case VCVTTPD2UDQSZ256rrbk:
29416 case VCVTTPD2UDQSZ256rrbkz:
29417 case VCVTTPD2UDQSZ256rrk:
29418 case VCVTTPD2UDQSZ256rrkz:
29419 case VCVTTPD2UDQSZrm:
29420 case VCVTTPD2UDQSZrmb:
29421 case VCVTTPD2UDQSZrmbk:
29422 case VCVTTPD2UDQSZrmbkz:
29423 case VCVTTPD2UDQSZrmk:
29424 case VCVTTPD2UDQSZrmkz:
29425 case VCVTTPD2UDQSZrr:
29426 case VCVTTPD2UDQSZrrb:
29427 case VCVTTPD2UDQSZrrbk:
29428 case VCVTTPD2UDQSZrrbkz:
29429 case VCVTTPD2UDQSZrrk:
29430 case VCVTTPD2UDQSZrrkz:
29431 return true;
29432 }
29433 return false;
29434}
29435
29436bool isSYSCALL(unsigned Opcode) {
29437 return Opcode == SYSCALL;
29438}
29439
29440bool isVFMADD231SH(unsigned Opcode) {
29441 switch (Opcode) {
29442 case VFMADD231SHZm_Int:
29443 case VFMADD231SHZmk_Int:
29444 case VFMADD231SHZmkz_Int:
29445 case VFMADD231SHZr_Int:
29446 case VFMADD231SHZrb_Int:
29447 case VFMADD231SHZrbk_Int:
29448 case VFMADD231SHZrbkz_Int:
29449 case VFMADD231SHZrk_Int:
29450 case VFMADD231SHZrkz_Int:
29451 return true;
29452 }
29453 return false;
29454}
29455
29456bool isVPOPCNTB(unsigned Opcode) {
29457 switch (Opcode) {
29458 case VPOPCNTBZ128rm:
29459 case VPOPCNTBZ128rmk:
29460 case VPOPCNTBZ128rmkz:
29461 case VPOPCNTBZ128rr:
29462 case VPOPCNTBZ128rrk:
29463 case VPOPCNTBZ128rrkz:
29464 case VPOPCNTBZ256rm:
29465 case VPOPCNTBZ256rmk:
29466 case VPOPCNTBZ256rmkz:
29467 case VPOPCNTBZ256rr:
29468 case VPOPCNTBZ256rrk:
29469 case VPOPCNTBZ256rrkz:
29470 case VPOPCNTBZrm:
29471 case VPOPCNTBZrmk:
29472 case VPOPCNTBZrmkz:
29473 case VPOPCNTBZrr:
29474 case VPOPCNTBZrrk:
29475 case VPOPCNTBZrrkz:
29476 return true;
29477 }
29478 return false;
29479}
29480
29481bool isPMOVZXBW(unsigned Opcode) {
29482 switch (Opcode) {
29483 case PMOVZXBWrm:
29484 case PMOVZXBWrr:
29485 return true;
29486 }
29487 return false;
29488}
29489
29490bool isVCVTDQ2PS(unsigned Opcode) {
29491 switch (Opcode) {
29492 case VCVTDQ2PSYrm:
29493 case VCVTDQ2PSYrr:
29494 case VCVTDQ2PSZ128rm:
29495 case VCVTDQ2PSZ128rmb:
29496 case VCVTDQ2PSZ128rmbk:
29497 case VCVTDQ2PSZ128rmbkz:
29498 case VCVTDQ2PSZ128rmk:
29499 case VCVTDQ2PSZ128rmkz:
29500 case VCVTDQ2PSZ128rr:
29501 case VCVTDQ2PSZ128rrk:
29502 case VCVTDQ2PSZ128rrkz:
29503 case VCVTDQ2PSZ256rm:
29504 case VCVTDQ2PSZ256rmb:
29505 case VCVTDQ2PSZ256rmbk:
29506 case VCVTDQ2PSZ256rmbkz:
29507 case VCVTDQ2PSZ256rmk:
29508 case VCVTDQ2PSZ256rmkz:
29509 case VCVTDQ2PSZ256rr:
29510 case VCVTDQ2PSZ256rrk:
29511 case VCVTDQ2PSZ256rrkz:
29512 case VCVTDQ2PSZrm:
29513 case VCVTDQ2PSZrmb:
29514 case VCVTDQ2PSZrmbk:
29515 case VCVTDQ2PSZrmbkz:
29516 case VCVTDQ2PSZrmk:
29517 case VCVTDQ2PSZrmkz:
29518 case VCVTDQ2PSZrr:
29519 case VCVTDQ2PSZrrb:
29520 case VCVTDQ2PSZrrbk:
29521 case VCVTDQ2PSZrrbkz:
29522 case VCVTDQ2PSZrrk:
29523 case VCVTDQ2PSZrrkz:
29524 case VCVTDQ2PSrm:
29525 case VCVTDQ2PSrr:
29526 return true;
29527 }
29528 return false;
29529}
29530
29531bool isPSUBD(unsigned Opcode) {
29532 switch (Opcode) {
29533 case MMX_PSUBDrm:
29534 case MMX_PSUBDrr:
29535 case PSUBDrm:
29536 case PSUBDrr:
29537 return true;
29538 }
29539 return false;
29540}
29541
29542bool isVPCMPEQW(unsigned Opcode) {
29543 switch (Opcode) {
29544 case VPCMPEQWYrm:
29545 case VPCMPEQWYrr:
29546 case VPCMPEQWZ128rm:
29547 case VPCMPEQWZ128rmk:
29548 case VPCMPEQWZ128rr:
29549 case VPCMPEQWZ128rrk:
29550 case VPCMPEQWZ256rm:
29551 case VPCMPEQWZ256rmk:
29552 case VPCMPEQWZ256rr:
29553 case VPCMPEQWZ256rrk:
29554 case VPCMPEQWZrm:
29555 case VPCMPEQWZrmk:
29556 case VPCMPEQWZrr:
29557 case VPCMPEQWZrrk:
29558 case VPCMPEQWrm:
29559 case VPCMPEQWrr:
29560 return true;
29561 }
29562 return false;
29563}
29564
29565bool isMOVSW(unsigned Opcode) {
29566 return Opcode == MOVSW;
29567}
29568
29569bool isVSM3RNDS2(unsigned Opcode) {
29570 switch (Opcode) {
29571 case VSM3RNDS2rmi:
29572 case VSM3RNDS2rri:
29573 return true;
29574 }
29575 return false;
29576}
29577
29578bool isVPMOVUSQD(unsigned Opcode) {
29579 switch (Opcode) {
29580 case VPMOVUSQDZ128mr:
29581 case VPMOVUSQDZ128mrk:
29582 case VPMOVUSQDZ128rr:
29583 case VPMOVUSQDZ128rrk:
29584 case VPMOVUSQDZ128rrkz:
29585 case VPMOVUSQDZ256mr:
29586 case VPMOVUSQDZ256mrk:
29587 case VPMOVUSQDZ256rr:
29588 case VPMOVUSQDZ256rrk:
29589 case VPMOVUSQDZ256rrkz:
29590 case VPMOVUSQDZmr:
29591 case VPMOVUSQDZmrk:
29592 case VPMOVUSQDZrr:
29593 case VPMOVUSQDZrrk:
29594 case VPMOVUSQDZrrkz:
29595 return true;
29596 }
29597 return false;
29598}
29599
29600bool isCVTTPD2DQ(unsigned Opcode) {
29601 switch (Opcode) {
29602 case CVTTPD2DQrm:
29603 case CVTTPD2DQrr:
29604 return true;
29605 }
29606 return false;
29607}
29608
29609bool isVPEXPANDW(unsigned Opcode) {
29610 switch (Opcode) {
29611 case VPEXPANDWZ128rm:
29612 case VPEXPANDWZ128rmk:
29613 case VPEXPANDWZ128rmkz:
29614 case VPEXPANDWZ128rr:
29615 case VPEXPANDWZ128rrk:
29616 case VPEXPANDWZ128rrkz:
29617 case VPEXPANDWZ256rm:
29618 case VPEXPANDWZ256rmk:
29619 case VPEXPANDWZ256rmkz:
29620 case VPEXPANDWZ256rr:
29621 case VPEXPANDWZ256rrk:
29622 case VPEXPANDWZ256rrkz:
29623 case VPEXPANDWZrm:
29624 case VPEXPANDWZrmk:
29625 case VPEXPANDWZrmkz:
29626 case VPEXPANDWZrr:
29627 case VPEXPANDWZrrk:
29628 case VPEXPANDWZrrkz:
29629 return true;
29630 }
29631 return false;
29632}
29633
29634bool isVUCOMISH(unsigned Opcode) {
29635 switch (Opcode) {
29636 case VUCOMISHZrm:
29637 case VUCOMISHZrr:
29638 case VUCOMISHZrrb:
29639 return true;
29640 }
29641 return false;
29642}
29643
29644bool isVZEROALL(unsigned Opcode) {
29645 return Opcode == VZEROALL;
29646}
29647
29648bool isVPAND(unsigned Opcode) {
29649 switch (Opcode) {
29650 case VPANDYrm:
29651 case VPANDYrr:
29652 case VPANDrm:
29653 case VPANDrr:
29654 return true;
29655 }
29656 return false;
29657}
29658
29659bool isPMULDQ(unsigned Opcode) {
29660 switch (Opcode) {
29661 case PMULDQrm:
29662 case PMULDQrr:
29663 return true;
29664 }
29665 return false;
29666}
29667
29668bool isVPSHUFHW(unsigned Opcode) {
29669 switch (Opcode) {
29670 case VPSHUFHWYmi:
29671 case VPSHUFHWYri:
29672 case VPSHUFHWZ128mi:
29673 case VPSHUFHWZ128mik:
29674 case VPSHUFHWZ128mikz:
29675 case VPSHUFHWZ128ri:
29676 case VPSHUFHWZ128rik:
29677 case VPSHUFHWZ128rikz:
29678 case VPSHUFHWZ256mi:
29679 case VPSHUFHWZ256mik:
29680 case VPSHUFHWZ256mikz:
29681 case VPSHUFHWZ256ri:
29682 case VPSHUFHWZ256rik:
29683 case VPSHUFHWZ256rikz:
29684 case VPSHUFHWZmi:
29685 case VPSHUFHWZmik:
29686 case VPSHUFHWZmikz:
29687 case VPSHUFHWZri:
29688 case VPSHUFHWZrik:
29689 case VPSHUFHWZrikz:
29690 case VPSHUFHWmi:
29691 case VPSHUFHWri:
29692 return true;
29693 }
29694 return false;
29695}
29696
29697bool isVPALIGNR(unsigned Opcode) {
29698 switch (Opcode) {
29699 case VPALIGNRYrmi:
29700 case VPALIGNRYrri:
29701 case VPALIGNRZ128rmi:
29702 case VPALIGNRZ128rmik:
29703 case VPALIGNRZ128rmikz:
29704 case VPALIGNRZ128rri:
29705 case VPALIGNRZ128rrik:
29706 case VPALIGNRZ128rrikz:
29707 case VPALIGNRZ256rmi:
29708 case VPALIGNRZ256rmik:
29709 case VPALIGNRZ256rmikz:
29710 case VPALIGNRZ256rri:
29711 case VPALIGNRZ256rrik:
29712 case VPALIGNRZ256rrikz:
29713 case VPALIGNRZrmi:
29714 case VPALIGNRZrmik:
29715 case VPALIGNRZrmikz:
29716 case VPALIGNRZrri:
29717 case VPALIGNRZrrik:
29718 case VPALIGNRZrrikz:
29719 case VPALIGNRrmi:
29720 case VPALIGNRrri:
29721 return true;
29722 }
29723 return false;
29724}
29725
29726bool isSQRTSD(unsigned Opcode) {
29727 switch (Opcode) {
29728 case SQRTSDm_Int:
29729 case SQRTSDr_Int:
29730 return true;
29731 }
29732 return false;
29733}
29734
29735bool isVCVTTPH2UDQ(unsigned Opcode) {
29736 switch (Opcode) {
29737 case VCVTTPH2UDQZ128rm:
29738 case VCVTTPH2UDQZ128rmb:
29739 case VCVTTPH2UDQZ128rmbk:
29740 case VCVTTPH2UDQZ128rmbkz:
29741 case VCVTTPH2UDQZ128rmk:
29742 case VCVTTPH2UDQZ128rmkz:
29743 case VCVTTPH2UDQZ128rr:
29744 case VCVTTPH2UDQZ128rrk:
29745 case VCVTTPH2UDQZ128rrkz:
29746 case VCVTTPH2UDQZ256rm:
29747 case VCVTTPH2UDQZ256rmb:
29748 case VCVTTPH2UDQZ256rmbk:
29749 case VCVTTPH2UDQZ256rmbkz:
29750 case VCVTTPH2UDQZ256rmk:
29751 case VCVTTPH2UDQZ256rmkz:
29752 case VCVTTPH2UDQZ256rr:
29753 case VCVTTPH2UDQZ256rrk:
29754 case VCVTTPH2UDQZ256rrkz:
29755 case VCVTTPH2UDQZrm:
29756 case VCVTTPH2UDQZrmb:
29757 case VCVTTPH2UDQZrmbk:
29758 case VCVTTPH2UDQZrmbkz:
29759 case VCVTTPH2UDQZrmk:
29760 case VCVTTPH2UDQZrmkz:
29761 case VCVTTPH2UDQZrr:
29762 case VCVTTPH2UDQZrrb:
29763 case VCVTTPH2UDQZrrbk:
29764 case VCVTTPH2UDQZrrbkz:
29765 case VCVTTPH2UDQZrrk:
29766 case VCVTTPH2UDQZrrkz:
29767 return true;
29768 }
29769 return false;
29770}
29771
29772bool isVGETEXPPH(unsigned Opcode) {
29773 switch (Opcode) {
29774 case VGETEXPPHZ128m:
29775 case VGETEXPPHZ128mb:
29776 case VGETEXPPHZ128mbk:
29777 case VGETEXPPHZ128mbkz:
29778 case VGETEXPPHZ128mk:
29779 case VGETEXPPHZ128mkz:
29780 case VGETEXPPHZ128r:
29781 case VGETEXPPHZ128rk:
29782 case VGETEXPPHZ128rkz:
29783 case VGETEXPPHZ256m:
29784 case VGETEXPPHZ256mb:
29785 case VGETEXPPHZ256mbk:
29786 case VGETEXPPHZ256mbkz:
29787 case VGETEXPPHZ256mk:
29788 case VGETEXPPHZ256mkz:
29789 case VGETEXPPHZ256r:
29790 case VGETEXPPHZ256rk:
29791 case VGETEXPPHZ256rkz:
29792 case VGETEXPPHZm:
29793 case VGETEXPPHZmb:
29794 case VGETEXPPHZmbk:
29795 case VGETEXPPHZmbkz:
29796 case VGETEXPPHZmk:
29797 case VGETEXPPHZmkz:
29798 case VGETEXPPHZr:
29799 case VGETEXPPHZrb:
29800 case VGETEXPPHZrbk:
29801 case VGETEXPPHZrbkz:
29802 case VGETEXPPHZrk:
29803 case VGETEXPPHZrkz:
29804 return true;
29805 }
29806 return false;
29807}
29808
29809bool isADDPD(unsigned Opcode) {
29810 switch (Opcode) {
29811 case ADDPDrm:
29812 case ADDPDrr:
29813 return true;
29814 }
29815 return false;
29816}
29817
29818bool isVFNMADDPD(unsigned Opcode) {
29819 switch (Opcode) {
29820 case VFNMADDPD4Ymr:
29821 case VFNMADDPD4Yrm:
29822 case VFNMADDPD4Yrr:
29823 case VFNMADDPD4Yrr_REV:
29824 case VFNMADDPD4mr:
29825 case VFNMADDPD4rm:
29826 case VFNMADDPD4rr:
29827 case VFNMADDPD4rr_REV:
29828 return true;
29829 }
29830 return false;
29831}
29832
29833bool isSTTILECFG(unsigned Opcode) {
29834 switch (Opcode) {
29835 case STTILECFG:
29836 case STTILECFG_EVEX:
29837 return true;
29838 }
29839 return false;
29840}
29841
29842bool isVMINPD(unsigned Opcode) {
29843 switch (Opcode) {
29844 case VMINPDYrm:
29845 case VMINPDYrr:
29846 case VMINPDZ128rm:
29847 case VMINPDZ128rmb:
29848 case VMINPDZ128rmbk:
29849 case VMINPDZ128rmbkz:
29850 case VMINPDZ128rmk:
29851 case VMINPDZ128rmkz:
29852 case VMINPDZ128rr:
29853 case VMINPDZ128rrk:
29854 case VMINPDZ128rrkz:
29855 case VMINPDZ256rm:
29856 case VMINPDZ256rmb:
29857 case VMINPDZ256rmbk:
29858 case VMINPDZ256rmbkz:
29859 case VMINPDZ256rmk:
29860 case VMINPDZ256rmkz:
29861 case VMINPDZ256rr:
29862 case VMINPDZ256rrk:
29863 case VMINPDZ256rrkz:
29864 case VMINPDZrm:
29865 case VMINPDZrmb:
29866 case VMINPDZrmbk:
29867 case VMINPDZrmbkz:
29868 case VMINPDZrmk:
29869 case VMINPDZrmkz:
29870 case VMINPDZrr:
29871 case VMINPDZrrb:
29872 case VMINPDZrrbk:
29873 case VMINPDZrrbkz:
29874 case VMINPDZrrk:
29875 case VMINPDZrrkz:
29876 case VMINPDrm:
29877 case VMINPDrr:
29878 return true;
29879 }
29880 return false;
29881}
29882
29883bool isSHA1RNDS4(unsigned Opcode) {
29884 switch (Opcode) {
29885 case SHA1RNDS4rmi:
29886 case SHA1RNDS4rri:
29887 return true;
29888 }
29889 return false;
29890}
29891
29892bool isPBLENDVB(unsigned Opcode) {
29893 switch (Opcode) {
29894 case PBLENDVBrm0:
29895 case PBLENDVBrr0:
29896 return true;
29897 }
29898 return false;
29899}
29900
29901bool isVBROADCASTF128(unsigned Opcode) {
29902 return Opcode == VBROADCASTF128rm;
29903}
29904
29905bool isVPSHRDQ(unsigned Opcode) {
29906 switch (Opcode) {
29907 case VPSHRDQZ128rmbi:
29908 case VPSHRDQZ128rmbik:
29909 case VPSHRDQZ128rmbikz:
29910 case VPSHRDQZ128rmi:
29911 case VPSHRDQZ128rmik:
29912 case VPSHRDQZ128rmikz:
29913 case VPSHRDQZ128rri:
29914 case VPSHRDQZ128rrik:
29915 case VPSHRDQZ128rrikz:
29916 case VPSHRDQZ256rmbi:
29917 case VPSHRDQZ256rmbik:
29918 case VPSHRDQZ256rmbikz:
29919 case VPSHRDQZ256rmi:
29920 case VPSHRDQZ256rmik:
29921 case VPSHRDQZ256rmikz:
29922 case VPSHRDQZ256rri:
29923 case VPSHRDQZ256rrik:
29924 case VPSHRDQZ256rrikz:
29925 case VPSHRDQZrmbi:
29926 case VPSHRDQZrmbik:
29927 case VPSHRDQZrmbikz:
29928 case VPSHRDQZrmi:
29929 case VPSHRDQZrmik:
29930 case VPSHRDQZrmikz:
29931 case VPSHRDQZrri:
29932 case VPSHRDQZrrik:
29933 case VPSHRDQZrrikz:
29934 return true;
29935 }
29936 return false;
29937}
29938
29939bool isVAESIMC(unsigned Opcode) {
29940 switch (Opcode) {
29941 case VAESIMCrm:
29942 case VAESIMCrr:
29943 return true;
29944 }
29945 return false;
29946}
29947
29948bool isCOMISD(unsigned Opcode) {
29949 switch (Opcode) {
29950 case COMISDrm:
29951 case COMISDrr:
29952 return true;
29953 }
29954 return false;
29955}
29956
29957bool isVMOVSH(unsigned Opcode) {
29958 switch (Opcode) {
29959 case VMOVSHZmr:
29960 case VMOVSHZmrk:
29961 case VMOVSHZrm:
29962 case VMOVSHZrmk:
29963 case VMOVSHZrmkz:
29964 case VMOVSHZrr:
29965 case VMOVSHZrr_REV:
29966 case VMOVSHZrrk:
29967 case VMOVSHZrrk_REV:
29968 case VMOVSHZrrkz:
29969 case VMOVSHZrrkz_REV:
29970 return true;
29971 }
29972 return false;
29973}
29974
29975bool isPFSUBR(unsigned Opcode) {
29976 switch (Opcode) {
29977 case PFSUBRrm:
29978 case PFSUBRrr:
29979 return true;
29980 }
29981 return false;
29982}
29983
29984bool isRDSSPD(unsigned Opcode) {
29985 return Opcode == RDSSPD;
29986}
29987
29988bool isWAIT(unsigned Opcode) {
29989 return Opcode == WAIT;
29990}
29991
29992bool isVFPCLASSSS(unsigned Opcode) {
29993 switch (Opcode) {
29994 case VFPCLASSSSZmi:
29995 case VFPCLASSSSZmik:
29996 case VFPCLASSSSZri:
29997 case VFPCLASSSSZrik:
29998 return true;
29999 }
30000 return false;
30001}
30002
30003bool isPCMPGTD(unsigned Opcode) {
30004 switch (Opcode) {
30005 case MMX_PCMPGTDrm:
30006 case MMX_PCMPGTDrr:
30007 case PCMPGTDrm:
30008 case PCMPGTDrr:
30009 return true;
30010 }
30011 return false;
30012}
30013
30014bool isVGATHERPF0QPS(unsigned Opcode) {
30015 return Opcode == VGATHERPF0QPSm;
30016}
30017
30018bool isBLENDVPS(unsigned Opcode) {
30019 switch (Opcode) {
30020 case BLENDVPSrm0:
30021 case BLENDVPSrr0:
30022 return true;
30023 }
30024 return false;
30025}
30026
30027bool isVBROADCASTF32X4(unsigned Opcode) {
30028 switch (Opcode) {
30029 case VBROADCASTF32X4Z256rm:
30030 case VBROADCASTF32X4Z256rmk:
30031 case VBROADCASTF32X4Z256rmkz:
30032 case VBROADCASTF32X4Zrm:
30033 case VBROADCASTF32X4Zrmk:
30034 case VBROADCASTF32X4Zrmkz:
30035 return true;
30036 }
30037 return false;
30038}
30039
30040bool isVMOVLPD(unsigned Opcode) {
30041 switch (Opcode) {
30042 case VMOVLPDZ128mr:
30043 case VMOVLPDZ128rm:
30044 case VMOVLPDmr:
30045 case VMOVLPDrm:
30046 return true;
30047 }
30048 return false;
30049}
30050
30051bool isVMOVQ(unsigned Opcode) {
30052 switch (Opcode) {
30053 case VMOV64toPQIZrm:
30054 case VMOV64toPQIZrr:
30055 case VMOV64toPQIrm:
30056 case VMOV64toPQIrr:
30057 case VMOVPQI2QIZmr:
30058 case VMOVPQI2QIZrr:
30059 case VMOVPQI2QImr:
30060 case VMOVPQI2QIrr:
30061 case VMOVPQIto64Zmr:
30062 case VMOVPQIto64Zrr:
30063 case VMOVPQIto64mr:
30064 case VMOVPQIto64rr:
30065 case VMOVQI2PQIZrm:
30066 case VMOVQI2PQIrm:
30067 case VMOVZPQILo2PQIZrr:
30068 case VMOVZPQILo2PQIrr:
30069 return true;
30070 }
30071 return false;
30072}
30073
30074bool isVPMADD52LUQ(unsigned Opcode) {
30075 switch (Opcode) {
30076 case VPMADD52LUQYrm:
30077 case VPMADD52LUQYrr:
30078 case VPMADD52LUQZ128m:
30079 case VPMADD52LUQZ128mb:
30080 case VPMADD52LUQZ128mbk:
30081 case VPMADD52LUQZ128mbkz:
30082 case VPMADD52LUQZ128mk:
30083 case VPMADD52LUQZ128mkz:
30084 case VPMADD52LUQZ128r:
30085 case VPMADD52LUQZ128rk:
30086 case VPMADD52LUQZ128rkz:
30087 case VPMADD52LUQZ256m:
30088 case VPMADD52LUQZ256mb:
30089 case VPMADD52LUQZ256mbk:
30090 case VPMADD52LUQZ256mbkz:
30091 case VPMADD52LUQZ256mk:
30092 case VPMADD52LUQZ256mkz:
30093 case VPMADD52LUQZ256r:
30094 case VPMADD52LUQZ256rk:
30095 case VPMADD52LUQZ256rkz:
30096 case VPMADD52LUQZm:
30097 case VPMADD52LUQZmb:
30098 case VPMADD52LUQZmbk:
30099 case VPMADD52LUQZmbkz:
30100 case VPMADD52LUQZmk:
30101 case VPMADD52LUQZmkz:
30102 case VPMADD52LUQZr:
30103 case VPMADD52LUQZrk:
30104 case VPMADD52LUQZrkz:
30105 case VPMADD52LUQrm:
30106 case VPMADD52LUQrr:
30107 return true;
30108 }
30109 return false;
30110}
30111
30112bool isVMOVDQU(unsigned Opcode) {
30113 switch (Opcode) {
30114 case VMOVDQUYmr:
30115 case VMOVDQUYrm:
30116 case VMOVDQUYrr:
30117 case VMOVDQUYrr_REV:
30118 case VMOVDQUmr:
30119 case VMOVDQUrm:
30120 case VMOVDQUrr:
30121 case VMOVDQUrr_REV:
30122 return true;
30123 }
30124 return false;
30125}
30126
30127bool isAESENC128KL(unsigned Opcode) {
30128 return Opcode == AESENC128KL;
30129}
30130
30131bool isVFMADDSUB231PS(unsigned Opcode) {
30132 switch (Opcode) {
30133 case VFMADDSUB231PSYm:
30134 case VFMADDSUB231PSYr:
30135 case VFMADDSUB231PSZ128m:
30136 case VFMADDSUB231PSZ128mb:
30137 case VFMADDSUB231PSZ128mbk:
30138 case VFMADDSUB231PSZ128mbkz:
30139 case VFMADDSUB231PSZ128mk:
30140 case VFMADDSUB231PSZ128mkz:
30141 case VFMADDSUB231PSZ128r:
30142 case VFMADDSUB231PSZ128rk:
30143 case VFMADDSUB231PSZ128rkz:
30144 case VFMADDSUB231PSZ256m:
30145 case VFMADDSUB231PSZ256mb:
30146 case VFMADDSUB231PSZ256mbk:
30147 case VFMADDSUB231PSZ256mbkz:
30148 case VFMADDSUB231PSZ256mk:
30149 case VFMADDSUB231PSZ256mkz:
30150 case VFMADDSUB231PSZ256r:
30151 case VFMADDSUB231PSZ256rk:
30152 case VFMADDSUB231PSZ256rkz:
30153 case VFMADDSUB231PSZm:
30154 case VFMADDSUB231PSZmb:
30155 case VFMADDSUB231PSZmbk:
30156 case VFMADDSUB231PSZmbkz:
30157 case VFMADDSUB231PSZmk:
30158 case VFMADDSUB231PSZmkz:
30159 case VFMADDSUB231PSZr:
30160 case VFMADDSUB231PSZrb:
30161 case VFMADDSUB231PSZrbk:
30162 case VFMADDSUB231PSZrbkz:
30163 case VFMADDSUB231PSZrk:
30164 case VFMADDSUB231PSZrkz:
30165 case VFMADDSUB231PSm:
30166 case VFMADDSUB231PSr:
30167 return true;
30168 }
30169 return false;
30170}
30171
30172bool isVFNMSUB213PD(unsigned Opcode) {
30173 switch (Opcode) {
30174 case VFNMSUB213PDYm:
30175 case VFNMSUB213PDYr:
30176 case VFNMSUB213PDZ128m:
30177 case VFNMSUB213PDZ128mb:
30178 case VFNMSUB213PDZ128mbk:
30179 case VFNMSUB213PDZ128mbkz:
30180 case VFNMSUB213PDZ128mk:
30181 case VFNMSUB213PDZ128mkz:
30182 case VFNMSUB213PDZ128r:
30183 case VFNMSUB213PDZ128rk:
30184 case VFNMSUB213PDZ128rkz:
30185 case VFNMSUB213PDZ256m:
30186 case VFNMSUB213PDZ256mb:
30187 case VFNMSUB213PDZ256mbk:
30188 case VFNMSUB213PDZ256mbkz:
30189 case VFNMSUB213PDZ256mk:
30190 case VFNMSUB213PDZ256mkz:
30191 case VFNMSUB213PDZ256r:
30192 case VFNMSUB213PDZ256rk:
30193 case VFNMSUB213PDZ256rkz:
30194 case VFNMSUB213PDZm:
30195 case VFNMSUB213PDZmb:
30196 case VFNMSUB213PDZmbk:
30197 case VFNMSUB213PDZmbkz:
30198 case VFNMSUB213PDZmk:
30199 case VFNMSUB213PDZmkz:
30200 case VFNMSUB213PDZr:
30201 case VFNMSUB213PDZrb:
30202 case VFNMSUB213PDZrbk:
30203 case VFNMSUB213PDZrbkz:
30204 case VFNMSUB213PDZrk:
30205 case VFNMSUB213PDZrkz:
30206 case VFNMSUB213PDm:
30207 case VFNMSUB213PDr:
30208 return true;
30209 }
30210 return false;
30211}
30212
30213bool isVPCONFLICTD(unsigned Opcode) {
30214 switch (Opcode) {
30215 case VPCONFLICTDZ128rm:
30216 case VPCONFLICTDZ128rmb:
30217 case VPCONFLICTDZ128rmbk:
30218 case VPCONFLICTDZ128rmbkz:
30219 case VPCONFLICTDZ128rmk:
30220 case VPCONFLICTDZ128rmkz:
30221 case VPCONFLICTDZ128rr:
30222 case VPCONFLICTDZ128rrk:
30223 case VPCONFLICTDZ128rrkz:
30224 case VPCONFLICTDZ256rm:
30225 case VPCONFLICTDZ256rmb:
30226 case VPCONFLICTDZ256rmbk:
30227 case VPCONFLICTDZ256rmbkz:
30228 case VPCONFLICTDZ256rmk:
30229 case VPCONFLICTDZ256rmkz:
30230 case VPCONFLICTDZ256rr:
30231 case VPCONFLICTDZ256rrk:
30232 case VPCONFLICTDZ256rrkz:
30233 case VPCONFLICTDZrm:
30234 case VPCONFLICTDZrmb:
30235 case VPCONFLICTDZrmbk:
30236 case VPCONFLICTDZrmbkz:
30237 case VPCONFLICTDZrmk:
30238 case VPCONFLICTDZrmkz:
30239 case VPCONFLICTDZrr:
30240 case VPCONFLICTDZrrk:
30241 case VPCONFLICTDZrrkz:
30242 return true;
30243 }
30244 return false;
30245}
30246
30247bool isVFMADDSUB213PH(unsigned Opcode) {
30248 switch (Opcode) {
30249 case VFMADDSUB213PHZ128m:
30250 case VFMADDSUB213PHZ128mb:
30251 case VFMADDSUB213PHZ128mbk:
30252 case VFMADDSUB213PHZ128mbkz:
30253 case VFMADDSUB213PHZ128mk:
30254 case VFMADDSUB213PHZ128mkz:
30255 case VFMADDSUB213PHZ128r:
30256 case VFMADDSUB213PHZ128rk:
30257 case VFMADDSUB213PHZ128rkz:
30258 case VFMADDSUB213PHZ256m:
30259 case VFMADDSUB213PHZ256mb:
30260 case VFMADDSUB213PHZ256mbk:
30261 case VFMADDSUB213PHZ256mbkz:
30262 case VFMADDSUB213PHZ256mk:
30263 case VFMADDSUB213PHZ256mkz:
30264 case VFMADDSUB213PHZ256r:
30265 case VFMADDSUB213PHZ256rk:
30266 case VFMADDSUB213PHZ256rkz:
30267 case VFMADDSUB213PHZm:
30268 case VFMADDSUB213PHZmb:
30269 case VFMADDSUB213PHZmbk:
30270 case VFMADDSUB213PHZmbkz:
30271 case VFMADDSUB213PHZmk:
30272 case VFMADDSUB213PHZmkz:
30273 case VFMADDSUB213PHZr:
30274 case VFMADDSUB213PHZrb:
30275 case VFMADDSUB213PHZrbk:
30276 case VFMADDSUB213PHZrbkz:
30277 case VFMADDSUB213PHZrk:
30278 case VFMADDSUB213PHZrkz:
30279 return true;
30280 }
30281 return false;
30282}
30283
30284bool isVPHSUBSW(unsigned Opcode) {
30285 switch (Opcode) {
30286 case VPHSUBSWYrm:
30287 case VPHSUBSWYrr:
30288 case VPHSUBSWrm:
30289 case VPHSUBSWrr:
30290 return true;
30291 }
30292 return false;
30293}
30294
30295bool isPUNPCKHDQ(unsigned Opcode) {
30296 switch (Opcode) {
30297 case MMX_PUNPCKHDQrm:
30298 case MMX_PUNPCKHDQrr:
30299 case PUNPCKHDQrm:
30300 case PUNPCKHDQrr:
30301 return true;
30302 }
30303 return false;
30304}
30305
30306bool isVSHUFI64X2(unsigned Opcode) {
30307 switch (Opcode) {
30308 case VSHUFI64X2Z256rmbi:
30309 case VSHUFI64X2Z256rmbik:
30310 case VSHUFI64X2Z256rmbikz:
30311 case VSHUFI64X2Z256rmi:
30312 case VSHUFI64X2Z256rmik:
30313 case VSHUFI64X2Z256rmikz:
30314 case VSHUFI64X2Z256rri:
30315 case VSHUFI64X2Z256rrik:
30316 case VSHUFI64X2Z256rrikz:
30317 case VSHUFI64X2Zrmbi:
30318 case VSHUFI64X2Zrmbik:
30319 case VSHUFI64X2Zrmbikz:
30320 case VSHUFI64X2Zrmi:
30321 case VSHUFI64X2Zrmik:
30322 case VSHUFI64X2Zrmikz:
30323 case VSHUFI64X2Zrri:
30324 case VSHUFI64X2Zrrik:
30325 case VSHUFI64X2Zrrikz:
30326 return true;
30327 }
30328 return false;
30329}
30330
30331bool isVFMSUBSD(unsigned Opcode) {
30332 switch (Opcode) {
30333 case VFMSUBSD4mr:
30334 case VFMSUBSD4rm:
30335 case VFMSUBSD4rr:
30336 case VFMSUBSD4rr_REV:
30337 return true;
30338 }
30339 return false;
30340}
30341
30342bool isVPORD(unsigned Opcode) {
30343 switch (Opcode) {
30344 case VPORDZ128rm:
30345 case VPORDZ128rmb:
30346 case VPORDZ128rmbk:
30347 case VPORDZ128rmbkz:
30348 case VPORDZ128rmk:
30349 case VPORDZ128rmkz:
30350 case VPORDZ128rr:
30351 case VPORDZ128rrk:
30352 case VPORDZ128rrkz:
30353 case VPORDZ256rm:
30354 case VPORDZ256rmb:
30355 case VPORDZ256rmbk:
30356 case VPORDZ256rmbkz:
30357 case VPORDZ256rmk:
30358 case VPORDZ256rmkz:
30359 case VPORDZ256rr:
30360 case VPORDZ256rrk:
30361 case VPORDZ256rrkz:
30362 case VPORDZrm:
30363 case VPORDZrmb:
30364 case VPORDZrmbk:
30365 case VPORDZrmbkz:
30366 case VPORDZrmk:
30367 case VPORDZrmkz:
30368 case VPORDZrr:
30369 case VPORDZrrk:
30370 case VPORDZrrkz:
30371 return true;
30372 }
30373 return false;
30374}
30375
30376bool isRCPPS(unsigned Opcode) {
30377 switch (Opcode) {
30378 case RCPPSm:
30379 case RCPPSr:
30380 return true;
30381 }
30382 return false;
30383}
30384
30385bool isVEXTRACTI128(unsigned Opcode) {
30386 switch (Opcode) {
30387 case VEXTRACTI128mri:
30388 case VEXTRACTI128rri:
30389 return true;
30390 }
30391 return false;
30392}
30393
30394bool isVCVT2PH2BF8S(unsigned Opcode) {
30395 switch (Opcode) {
30396 case VCVT2PH2BF8SZ128rm:
30397 case VCVT2PH2BF8SZ128rmb:
30398 case VCVT2PH2BF8SZ128rmbk:
30399 case VCVT2PH2BF8SZ128rmbkz:
30400 case VCVT2PH2BF8SZ128rmk:
30401 case VCVT2PH2BF8SZ128rmkz:
30402 case VCVT2PH2BF8SZ128rr:
30403 case VCVT2PH2BF8SZ128rrk:
30404 case VCVT2PH2BF8SZ128rrkz:
30405 case VCVT2PH2BF8SZ256rm:
30406 case VCVT2PH2BF8SZ256rmb:
30407 case VCVT2PH2BF8SZ256rmbk:
30408 case VCVT2PH2BF8SZ256rmbkz:
30409 case VCVT2PH2BF8SZ256rmk:
30410 case VCVT2PH2BF8SZ256rmkz:
30411 case VCVT2PH2BF8SZ256rr:
30412 case VCVT2PH2BF8SZ256rrk:
30413 case VCVT2PH2BF8SZ256rrkz:
30414 case VCVT2PH2BF8SZrm:
30415 case VCVT2PH2BF8SZrmb:
30416 case VCVT2PH2BF8SZrmbk:
30417 case VCVT2PH2BF8SZrmbkz:
30418 case VCVT2PH2BF8SZrmk:
30419 case VCVT2PH2BF8SZrmkz:
30420 case VCVT2PH2BF8SZrr:
30421 case VCVT2PH2BF8SZrrk:
30422 case VCVT2PH2BF8SZrrkz:
30423 return true;
30424 }
30425 return false;
30426}
30427
30428bool isVPSHRDVW(unsigned Opcode) {
30429 switch (Opcode) {
30430 case VPSHRDVWZ128m:
30431 case VPSHRDVWZ128mk:
30432 case VPSHRDVWZ128mkz:
30433 case VPSHRDVWZ128r:
30434 case VPSHRDVWZ128rk:
30435 case VPSHRDVWZ128rkz:
30436 case VPSHRDVWZ256m:
30437 case VPSHRDVWZ256mk:
30438 case VPSHRDVWZ256mkz:
30439 case VPSHRDVWZ256r:
30440 case VPSHRDVWZ256rk:
30441 case VPSHRDVWZ256rkz:
30442 case VPSHRDVWZm:
30443 case VPSHRDVWZmk:
30444 case VPSHRDVWZmkz:
30445 case VPSHRDVWZr:
30446 case VPSHRDVWZrk:
30447 case VPSHRDVWZrkz:
30448 return true;
30449 }
30450 return false;
30451}
30452
30453bool isVUNPCKLPD(unsigned Opcode) {
30454 switch (Opcode) {
30455 case VUNPCKLPDYrm:
30456 case VUNPCKLPDYrr:
30457 case VUNPCKLPDZ128rm:
30458 case VUNPCKLPDZ128rmb:
30459 case VUNPCKLPDZ128rmbk:
30460 case VUNPCKLPDZ128rmbkz:
30461 case VUNPCKLPDZ128rmk:
30462 case VUNPCKLPDZ128rmkz:
30463 case VUNPCKLPDZ128rr:
30464 case VUNPCKLPDZ128rrk:
30465 case VUNPCKLPDZ128rrkz:
30466 case VUNPCKLPDZ256rm:
30467 case VUNPCKLPDZ256rmb:
30468 case VUNPCKLPDZ256rmbk:
30469 case VUNPCKLPDZ256rmbkz:
30470 case VUNPCKLPDZ256rmk:
30471 case VUNPCKLPDZ256rmkz:
30472 case VUNPCKLPDZ256rr:
30473 case VUNPCKLPDZ256rrk:
30474 case VUNPCKLPDZ256rrkz:
30475 case VUNPCKLPDZrm:
30476 case VUNPCKLPDZrmb:
30477 case VUNPCKLPDZrmbk:
30478 case VUNPCKLPDZrmbkz:
30479 case VUNPCKLPDZrmk:
30480 case VUNPCKLPDZrmkz:
30481 case VUNPCKLPDZrr:
30482 case VUNPCKLPDZrrk:
30483 case VUNPCKLPDZrrkz:
30484 case VUNPCKLPDrm:
30485 case VUNPCKLPDrr:
30486 return true;
30487 }
30488 return false;
30489}
30490
30491bool isVPSRAVD(unsigned Opcode) {
30492 switch (Opcode) {
30493 case VPSRAVDYrm:
30494 case VPSRAVDYrr:
30495 case VPSRAVDZ128rm:
30496 case VPSRAVDZ128rmb:
30497 case VPSRAVDZ128rmbk:
30498 case VPSRAVDZ128rmbkz:
30499 case VPSRAVDZ128rmk:
30500 case VPSRAVDZ128rmkz:
30501 case VPSRAVDZ128rr:
30502 case VPSRAVDZ128rrk:
30503 case VPSRAVDZ128rrkz:
30504 case VPSRAVDZ256rm:
30505 case VPSRAVDZ256rmb:
30506 case VPSRAVDZ256rmbk:
30507 case VPSRAVDZ256rmbkz:
30508 case VPSRAVDZ256rmk:
30509 case VPSRAVDZ256rmkz:
30510 case VPSRAVDZ256rr:
30511 case VPSRAVDZ256rrk:
30512 case VPSRAVDZ256rrkz:
30513 case VPSRAVDZrm:
30514 case VPSRAVDZrmb:
30515 case VPSRAVDZrmbk:
30516 case VPSRAVDZrmbkz:
30517 case VPSRAVDZrmk:
30518 case VPSRAVDZrmkz:
30519 case VPSRAVDZrr:
30520 case VPSRAVDZrrk:
30521 case VPSRAVDZrrkz:
30522 case VPSRAVDrm:
30523 case VPSRAVDrr:
30524 return true;
30525 }
30526 return false;
30527}
30528
30529bool isVMULSH(unsigned Opcode) {
30530 switch (Opcode) {
30531 case VMULSHZrm_Int:
30532 case VMULSHZrmk_Int:
30533 case VMULSHZrmkz_Int:
30534 case VMULSHZrr_Int:
30535 case VMULSHZrrb_Int:
30536 case VMULSHZrrbk_Int:
30537 case VMULSHZrrbkz_Int:
30538 case VMULSHZrrk_Int:
30539 case VMULSHZrrkz_Int:
30540 return true;
30541 }
30542 return false;
30543}
30544
30545bool isMOVNTSS(unsigned Opcode) {
30546 return Opcode == MOVNTSS;
30547}
30548
30549bool isSTI(unsigned Opcode) {
30550 return Opcode == STI;
30551}
30552
30553bool isVSM4RNDS4(unsigned Opcode) {
30554 switch (Opcode) {
30555 case VSM4RNDS4Yrm:
30556 case VSM4RNDS4Yrr:
30557 case VSM4RNDS4Z128rm:
30558 case VSM4RNDS4Z128rr:
30559 case VSM4RNDS4Z256rm:
30560 case VSM4RNDS4Z256rr:
30561 case VSM4RNDS4Zrm:
30562 case VSM4RNDS4Zrr:
30563 case VSM4RNDS4rm:
30564 case VSM4RNDS4rr:
30565 return true;
30566 }
30567 return false;
30568}
30569
30570bool isVMCLEAR(unsigned Opcode) {
30571 return Opcode == VMCLEARm;
30572}
30573
30574bool isVPMADD52HUQ(unsigned Opcode) {
30575 switch (Opcode) {
30576 case VPMADD52HUQYrm:
30577 case VPMADD52HUQYrr:
30578 case VPMADD52HUQZ128m:
30579 case VPMADD52HUQZ128mb:
30580 case VPMADD52HUQZ128mbk:
30581 case VPMADD52HUQZ128mbkz:
30582 case VPMADD52HUQZ128mk:
30583 case VPMADD52HUQZ128mkz:
30584 case VPMADD52HUQZ128r:
30585 case VPMADD52HUQZ128rk:
30586 case VPMADD52HUQZ128rkz:
30587 case VPMADD52HUQZ256m:
30588 case VPMADD52HUQZ256mb:
30589 case VPMADD52HUQZ256mbk:
30590 case VPMADD52HUQZ256mbkz:
30591 case VPMADD52HUQZ256mk:
30592 case VPMADD52HUQZ256mkz:
30593 case VPMADD52HUQZ256r:
30594 case VPMADD52HUQZ256rk:
30595 case VPMADD52HUQZ256rkz:
30596 case VPMADD52HUQZm:
30597 case VPMADD52HUQZmb:
30598 case VPMADD52HUQZmbk:
30599 case VPMADD52HUQZmbkz:
30600 case VPMADD52HUQZmk:
30601 case VPMADD52HUQZmkz:
30602 case VPMADD52HUQZr:
30603 case VPMADD52HUQZrk:
30604 case VPMADD52HUQZrkz:
30605 case VPMADD52HUQrm:
30606 case VPMADD52HUQrr:
30607 return true;
30608 }
30609 return false;
30610}
30611
30612bool isLIDT(unsigned Opcode) {
30613 return Opcode == LIDT64m;
30614}
30615
30616bool isPUSH2(unsigned Opcode) {
30617 return Opcode == PUSH2;
30618}
30619
30620bool isRDPKRU(unsigned Opcode) {
30621 return Opcode == RDPKRUr;
30622}
30623
30624bool isVCVTPS2IUBS(unsigned Opcode) {
30625 switch (Opcode) {
30626 case VCVTPS2IUBSZ128rm:
30627 case VCVTPS2IUBSZ128rmb:
30628 case VCVTPS2IUBSZ128rmbk:
30629 case VCVTPS2IUBSZ128rmbkz:
30630 case VCVTPS2IUBSZ128rmk:
30631 case VCVTPS2IUBSZ128rmkz:
30632 case VCVTPS2IUBSZ128rr:
30633 case VCVTPS2IUBSZ128rrk:
30634 case VCVTPS2IUBSZ128rrkz:
30635 case VCVTPS2IUBSZ256rm:
30636 case VCVTPS2IUBSZ256rmb:
30637 case VCVTPS2IUBSZ256rmbk:
30638 case VCVTPS2IUBSZ256rmbkz:
30639 case VCVTPS2IUBSZ256rmk:
30640 case VCVTPS2IUBSZ256rmkz:
30641 case VCVTPS2IUBSZ256rr:
30642 case VCVTPS2IUBSZ256rrk:
30643 case VCVTPS2IUBSZ256rrkz:
30644 case VCVTPS2IUBSZrm:
30645 case VCVTPS2IUBSZrmb:
30646 case VCVTPS2IUBSZrmbk:
30647 case VCVTPS2IUBSZrmbkz:
30648 case VCVTPS2IUBSZrmk:
30649 case VCVTPS2IUBSZrmkz:
30650 case VCVTPS2IUBSZrr:
30651 case VCVTPS2IUBSZrrb:
30652 case VCVTPS2IUBSZrrbk:
30653 case VCVTPS2IUBSZrrbkz:
30654 case VCVTPS2IUBSZrrk:
30655 case VCVTPS2IUBSZrrkz:
30656 return true;
30657 }
30658 return false;
30659}
30660
30661bool isXSAVES64(unsigned Opcode) {
30662 return Opcode == XSAVES64;
30663}
30664
30665bool isVPCMPB(unsigned Opcode) {
30666 switch (Opcode) {
30667 case VPCMPBZ128rmi:
30668 case VPCMPBZ128rmik:
30669 case VPCMPBZ128rri:
30670 case VPCMPBZ128rrik:
30671 case VPCMPBZ256rmi:
30672 case VPCMPBZ256rmik:
30673 case VPCMPBZ256rri:
30674 case VPCMPBZ256rrik:
30675 case VPCMPBZrmi:
30676 case VPCMPBZrmik:
30677 case VPCMPBZrri:
30678 case VPCMPBZrrik:
30679 return true;
30680 }
30681 return false;
30682}
30683
30684bool isVFMSUB231BF16(unsigned Opcode) {
30685 switch (Opcode) {
30686 case VFMSUB231BF16Z128m:
30687 case VFMSUB231BF16Z128mb:
30688 case VFMSUB231BF16Z128mbk:
30689 case VFMSUB231BF16Z128mbkz:
30690 case VFMSUB231BF16Z128mk:
30691 case VFMSUB231BF16Z128mkz:
30692 case VFMSUB231BF16Z128r:
30693 case VFMSUB231BF16Z128rk:
30694 case VFMSUB231BF16Z128rkz:
30695 case VFMSUB231BF16Z256m:
30696 case VFMSUB231BF16Z256mb:
30697 case VFMSUB231BF16Z256mbk:
30698 case VFMSUB231BF16Z256mbkz:
30699 case VFMSUB231BF16Z256mk:
30700 case VFMSUB231BF16Z256mkz:
30701 case VFMSUB231BF16Z256r:
30702 case VFMSUB231BF16Z256rk:
30703 case VFMSUB231BF16Z256rkz:
30704 case VFMSUB231BF16Zm:
30705 case VFMSUB231BF16Zmb:
30706 case VFMSUB231BF16Zmbk:
30707 case VFMSUB231BF16Zmbkz:
30708 case VFMSUB231BF16Zmk:
30709 case VFMSUB231BF16Zmkz:
30710 case VFMSUB231BF16Zr:
30711 case VFMSUB231BF16Zrk:
30712 case VFMSUB231BF16Zrkz:
30713 return true;
30714 }
30715 return false;
30716}
30717
30718bool isFINCSTP(unsigned Opcode) {
30719 return Opcode == FINCSTP;
30720}
30721
30722bool isKORQ(unsigned Opcode) {
30723 return Opcode == KORQkk;
30724}
30725
30726bool isRDPMC(unsigned Opcode) {
30727 return Opcode == RDPMC;
30728}
30729
30730bool isVEXTRACTF128(unsigned Opcode) {
30731 switch (Opcode) {
30732 case VEXTRACTF128mri:
30733 case VEXTRACTF128rri:
30734 return true;
30735 }
30736 return false;
30737}
30738
30739bool isMOVMSKPD(unsigned Opcode) {
30740 return Opcode == MOVMSKPDrr;
30741}
30742
30743bool isVFMSUB231SH(unsigned Opcode) {
30744 switch (Opcode) {
30745 case VFMSUB231SHZm_Int:
30746 case VFMSUB231SHZmk_Int:
30747 case VFMSUB231SHZmkz_Int:
30748 case VFMSUB231SHZr_Int:
30749 case VFMSUB231SHZrb_Int:
30750 case VFMSUB231SHZrbk_Int:
30751 case VFMSUB231SHZrbkz_Int:
30752 case VFMSUB231SHZrk_Int:
30753 case VFMSUB231SHZrkz_Int:
30754 return true;
30755 }
30756 return false;
30757}
30758
30759bool isVPSHLB(unsigned Opcode) {
30760 switch (Opcode) {
30761 case VPSHLBmr:
30762 case VPSHLBrm:
30763 case VPSHLBrr:
30764 case VPSHLBrr_REV:
30765 return true;
30766 }
30767 return false;
30768}
30769
30770bool isXCRYPTCBC(unsigned Opcode) {
30771 return Opcode == XCRYPTCBC;
30772}
30773
30774bool isSHL(unsigned Opcode) {
30775 switch (Opcode) {
30776 case SHL16m1:
30777 case SHL16m1_EVEX:
30778 case SHL16m1_ND:
30779 case SHL16m1_NF:
30780 case SHL16m1_NF_ND:
30781 case SHL16mCL:
30782 case SHL16mCL_EVEX:
30783 case SHL16mCL_ND:
30784 case SHL16mCL_NF:
30785 case SHL16mCL_NF_ND:
30786 case SHL16mi:
30787 case SHL16mi_EVEX:
30788 case SHL16mi_ND:
30789 case SHL16mi_NF:
30790 case SHL16mi_NF_ND:
30791 case SHL16r1:
30792 case SHL16r1_EVEX:
30793 case SHL16r1_ND:
30794 case SHL16r1_NF:
30795 case SHL16r1_NF_ND:
30796 case SHL16rCL:
30797 case SHL16rCL_EVEX:
30798 case SHL16rCL_ND:
30799 case SHL16rCL_NF:
30800 case SHL16rCL_NF_ND:
30801 case SHL16ri:
30802 case SHL16ri_EVEX:
30803 case SHL16ri_ND:
30804 case SHL16ri_NF:
30805 case SHL16ri_NF_ND:
30806 case SHL32m1:
30807 case SHL32m1_EVEX:
30808 case SHL32m1_ND:
30809 case SHL32m1_NF:
30810 case SHL32m1_NF_ND:
30811 case SHL32mCL:
30812 case SHL32mCL_EVEX:
30813 case SHL32mCL_ND:
30814 case SHL32mCL_NF:
30815 case SHL32mCL_NF_ND:
30816 case SHL32mi:
30817 case SHL32mi_EVEX:
30818 case SHL32mi_ND:
30819 case SHL32mi_NF:
30820 case SHL32mi_NF_ND:
30821 case SHL32r1:
30822 case SHL32r1_EVEX:
30823 case SHL32r1_ND:
30824 case SHL32r1_NF:
30825 case SHL32r1_NF_ND:
30826 case SHL32rCL:
30827 case SHL32rCL_EVEX:
30828 case SHL32rCL_ND:
30829 case SHL32rCL_NF:
30830 case SHL32rCL_NF_ND:
30831 case SHL32ri:
30832 case SHL32ri_EVEX:
30833 case SHL32ri_ND:
30834 case SHL32ri_NF:
30835 case SHL32ri_NF_ND:
30836 case SHL64m1:
30837 case SHL64m1_EVEX:
30838 case SHL64m1_ND:
30839 case SHL64m1_NF:
30840 case SHL64m1_NF_ND:
30841 case SHL64mCL:
30842 case SHL64mCL_EVEX:
30843 case SHL64mCL_ND:
30844 case SHL64mCL_NF:
30845 case SHL64mCL_NF_ND:
30846 case SHL64mi:
30847 case SHL64mi_EVEX:
30848 case SHL64mi_ND:
30849 case SHL64mi_NF:
30850 case SHL64mi_NF_ND:
30851 case SHL64r1:
30852 case SHL64r1_EVEX:
30853 case SHL64r1_ND:
30854 case SHL64r1_NF:
30855 case SHL64r1_NF_ND:
30856 case SHL64rCL:
30857 case SHL64rCL_EVEX:
30858 case SHL64rCL_ND:
30859 case SHL64rCL_NF:
30860 case SHL64rCL_NF_ND:
30861 case SHL64ri:
30862 case SHL64ri_EVEX:
30863 case SHL64ri_ND:
30864 case SHL64ri_NF:
30865 case SHL64ri_NF_ND:
30866 case SHL8m1:
30867 case SHL8m1_EVEX:
30868 case SHL8m1_ND:
30869 case SHL8m1_NF:
30870 case SHL8m1_NF_ND:
30871 case SHL8mCL:
30872 case SHL8mCL_EVEX:
30873 case SHL8mCL_ND:
30874 case SHL8mCL_NF:
30875 case SHL8mCL_NF_ND:
30876 case SHL8mi:
30877 case SHL8mi_EVEX:
30878 case SHL8mi_ND:
30879 case SHL8mi_NF:
30880 case SHL8mi_NF_ND:
30881 case SHL8r1:
30882 case SHL8r1_EVEX:
30883 case SHL8r1_ND:
30884 case SHL8r1_NF:
30885 case SHL8r1_NF_ND:
30886 case SHL8rCL:
30887 case SHL8rCL_EVEX:
30888 case SHL8rCL_ND:
30889 case SHL8rCL_NF:
30890 case SHL8rCL_NF_ND:
30891 case SHL8ri:
30892 case SHL8ri_EVEX:
30893 case SHL8ri_ND:
30894 case SHL8ri_NF:
30895 case SHL8ri_NF_ND:
30896 return true;
30897 }
30898 return false;
30899}
30900
30901bool isAXOR(unsigned Opcode) {
30902 switch (Opcode) {
30903 case AXOR32mr:
30904 case AXOR32mr_EVEX:
30905 case AXOR64mr:
30906 case AXOR64mr_EVEX:
30907 return true;
30908 }
30909 return false;
30910}
30911
30912bool isVINSERTI64X2(unsigned Opcode) {
30913 switch (Opcode) {
30914 case VINSERTI64X2Z256rmi:
30915 case VINSERTI64X2Z256rmik:
30916 case VINSERTI64X2Z256rmikz:
30917 case VINSERTI64X2Z256rri:
30918 case VINSERTI64X2Z256rrik:
30919 case VINSERTI64X2Z256rrikz:
30920 case VINSERTI64X2Zrmi:
30921 case VINSERTI64X2Zrmik:
30922 case VINSERTI64X2Zrmikz:
30923 case VINSERTI64X2Zrri:
30924 case VINSERTI64X2Zrrik:
30925 case VINSERTI64X2Zrrikz:
30926 return true;
30927 }
30928 return false;
30929}
30930
30931bool isSYSRETQ(unsigned Opcode) {
30932 return Opcode == SYSRET64;
30933}
30934
30935bool isVSCATTERPF0QPD(unsigned Opcode) {
30936 return Opcode == VSCATTERPF0QPDm;
30937}
30938
30939bool isVFMSUB213SH(unsigned Opcode) {
30940 switch (Opcode) {
30941 case VFMSUB213SHZm_Int:
30942 case VFMSUB213SHZmk_Int:
30943 case VFMSUB213SHZmkz_Int:
30944 case VFMSUB213SHZr_Int:
30945 case VFMSUB213SHZrb_Int:
30946 case VFMSUB213SHZrbk_Int:
30947 case VFMSUB213SHZrbkz_Int:
30948 case VFMSUB213SHZrk_Int:
30949 case VFMSUB213SHZrkz_Int:
30950 return true;
30951 }
30952 return false;
30953}
30954
30955bool isVPMOVQW(unsigned Opcode) {
30956 switch (Opcode) {
30957 case VPMOVQWZ128mr:
30958 case VPMOVQWZ128mrk:
30959 case VPMOVQWZ128rr:
30960 case VPMOVQWZ128rrk:
30961 case VPMOVQWZ128rrkz:
30962 case VPMOVQWZ256mr:
30963 case VPMOVQWZ256mrk:
30964 case VPMOVQWZ256rr:
30965 case VPMOVQWZ256rrk:
30966 case VPMOVQWZ256rrkz:
30967 case VPMOVQWZmr:
30968 case VPMOVQWZmrk:
30969 case VPMOVQWZrr:
30970 case VPMOVQWZrrk:
30971 case VPMOVQWZrrkz:
30972 return true;
30973 }
30974 return false;
30975}
30976
30977bool isVREDUCEPD(unsigned Opcode) {
30978 switch (Opcode) {
30979 case VREDUCEPDZ128rmbi:
30980 case VREDUCEPDZ128rmbik:
30981 case VREDUCEPDZ128rmbikz:
30982 case VREDUCEPDZ128rmi:
30983 case VREDUCEPDZ128rmik:
30984 case VREDUCEPDZ128rmikz:
30985 case VREDUCEPDZ128rri:
30986 case VREDUCEPDZ128rrik:
30987 case VREDUCEPDZ128rrikz:
30988 case VREDUCEPDZ256rmbi:
30989 case VREDUCEPDZ256rmbik:
30990 case VREDUCEPDZ256rmbikz:
30991 case VREDUCEPDZ256rmi:
30992 case VREDUCEPDZ256rmik:
30993 case VREDUCEPDZ256rmikz:
30994 case VREDUCEPDZ256rri:
30995 case VREDUCEPDZ256rrik:
30996 case VREDUCEPDZ256rrikz:
30997 case VREDUCEPDZrmbi:
30998 case VREDUCEPDZrmbik:
30999 case VREDUCEPDZrmbikz:
31000 case VREDUCEPDZrmi:
31001 case VREDUCEPDZrmik:
31002 case VREDUCEPDZrmikz:
31003 case VREDUCEPDZrri:
31004 case VREDUCEPDZrrib:
31005 case VREDUCEPDZrribk:
31006 case VREDUCEPDZrribkz:
31007 case VREDUCEPDZrrik:
31008 case VREDUCEPDZrrikz:
31009 return true;
31010 }
31011 return false;
31012}
31013
31014bool isNOT(unsigned Opcode) {
31015 switch (Opcode) {
31016 case NOT16m:
31017 case NOT16m_EVEX:
31018 case NOT16m_ND:
31019 case NOT16r:
31020 case NOT16r_EVEX:
31021 case NOT16r_ND:
31022 case NOT32m:
31023 case NOT32m_EVEX:
31024 case NOT32m_ND:
31025 case NOT32r:
31026 case NOT32r_EVEX:
31027 case NOT32r_ND:
31028 case NOT64m:
31029 case NOT64m_EVEX:
31030 case NOT64m_ND:
31031 case NOT64r:
31032 case NOT64r_EVEX:
31033 case NOT64r_ND:
31034 case NOT8m:
31035 case NOT8m_EVEX:
31036 case NOT8m_ND:
31037 case NOT8r:
31038 case NOT8r_EVEX:
31039 case NOT8r_ND:
31040 return true;
31041 }
31042 return false;
31043}
31044
31045bool isLWPINS(unsigned Opcode) {
31046 switch (Opcode) {
31047 case LWPINS32rmi:
31048 case LWPINS32rri:
31049 case LWPINS64rmi:
31050 case LWPINS64rri:
31051 return true;
31052 }
31053 return false;
31054}
31055
31056bool isVSCATTERDPS(unsigned Opcode) {
31057 switch (Opcode) {
31058 case VSCATTERDPSZ128mr:
31059 case VSCATTERDPSZ256mr:
31060 case VSCATTERDPSZmr:
31061 return true;
31062 }
31063 return false;
31064}
31065
31066bool isVPMOVM2W(unsigned Opcode) {
31067 switch (Opcode) {
31068 case VPMOVM2WZ128rk:
31069 case VPMOVM2WZ256rk:
31070 case VPMOVM2WZrk:
31071 return true;
31072 }
31073 return false;
31074}
31075
31076bool isVFNMADD132PS(unsigned Opcode) {
31077 switch (Opcode) {
31078 case VFNMADD132PSYm:
31079 case VFNMADD132PSYr:
31080 case VFNMADD132PSZ128m:
31081 case VFNMADD132PSZ128mb:
31082 case VFNMADD132PSZ128mbk:
31083 case VFNMADD132PSZ128mbkz:
31084 case VFNMADD132PSZ128mk:
31085 case VFNMADD132PSZ128mkz:
31086 case VFNMADD132PSZ128r:
31087 case VFNMADD132PSZ128rk:
31088 case VFNMADD132PSZ128rkz:
31089 case VFNMADD132PSZ256m:
31090 case VFNMADD132PSZ256mb:
31091 case VFNMADD132PSZ256mbk:
31092 case VFNMADD132PSZ256mbkz:
31093 case VFNMADD132PSZ256mk:
31094 case VFNMADD132PSZ256mkz:
31095 case VFNMADD132PSZ256r:
31096 case VFNMADD132PSZ256rk:
31097 case VFNMADD132PSZ256rkz:
31098 case VFNMADD132PSZm:
31099 case VFNMADD132PSZmb:
31100 case VFNMADD132PSZmbk:
31101 case VFNMADD132PSZmbkz:
31102 case VFNMADD132PSZmk:
31103 case VFNMADD132PSZmkz:
31104 case VFNMADD132PSZr:
31105 case VFNMADD132PSZrb:
31106 case VFNMADD132PSZrbk:
31107 case VFNMADD132PSZrbkz:
31108 case VFNMADD132PSZrk:
31109 case VFNMADD132PSZrkz:
31110 case VFNMADD132PSm:
31111 case VFNMADD132PSr:
31112 return true;
31113 }
31114 return false;
31115}
31116
31117bool isMOVNTPS(unsigned Opcode) {
31118 return Opcode == MOVNTPSmr;
31119}
31120
31121bool isVRSQRTSS(unsigned Opcode) {
31122 switch (Opcode) {
31123 case VRSQRTSSm_Int:
31124 case VRSQRTSSr_Int:
31125 return true;
31126 }
31127 return false;
31128}
31129
31130bool isKMOVB(unsigned Opcode) {
31131 switch (Opcode) {
31132 case KMOVBkk:
31133 case KMOVBkk_EVEX:
31134 case KMOVBkm:
31135 case KMOVBkm_EVEX:
31136 case KMOVBkr:
31137 case KMOVBkr_EVEX:
31138 case KMOVBmk:
31139 case KMOVBmk_EVEX:
31140 case KMOVBrk:
31141 case KMOVBrk_EVEX:
31142 return true;
31143 }
31144 return false;
31145}
31146
31147bool isCVTSD2SS(unsigned Opcode) {
31148 switch (Opcode) {
31149 case CVTSD2SSrm_Int:
31150 case CVTSD2SSrr_Int:
31151 return true;
31152 }
31153 return false;
31154}
31155
31156bool isVBROADCASTF64X2(unsigned Opcode) {
31157 switch (Opcode) {
31158 case VBROADCASTF64X2Z256rm:
31159 case VBROADCASTF64X2Z256rmk:
31160 case VBROADCASTF64X2Z256rmkz:
31161 case VBROADCASTF64X2Zrm:
31162 case VBROADCASTF64X2Zrmk:
31163 case VBROADCASTF64X2Zrmkz:
31164 return true;
31165 }
31166 return false;
31167}
31168
31169bool isVDIVBF16(unsigned Opcode) {
31170 switch (Opcode) {
31171 case VDIVBF16Z128rm:
31172 case VDIVBF16Z128rmb:
31173 case VDIVBF16Z128rmbk:
31174 case VDIVBF16Z128rmbkz:
31175 case VDIVBF16Z128rmk:
31176 case VDIVBF16Z128rmkz:
31177 case VDIVBF16Z128rr:
31178 case VDIVBF16Z128rrk:
31179 case VDIVBF16Z128rrkz:
31180 case VDIVBF16Z256rm:
31181 case VDIVBF16Z256rmb:
31182 case VDIVBF16Z256rmbk:
31183 case VDIVBF16Z256rmbkz:
31184 case VDIVBF16Z256rmk:
31185 case VDIVBF16Z256rmkz:
31186 case VDIVBF16Z256rr:
31187 case VDIVBF16Z256rrk:
31188 case VDIVBF16Z256rrkz:
31189 case VDIVBF16Zrm:
31190 case VDIVBF16Zrmb:
31191 case VDIVBF16Zrmbk:
31192 case VDIVBF16Zrmbkz:
31193 case VDIVBF16Zrmk:
31194 case VDIVBF16Zrmkz:
31195 case VDIVBF16Zrr:
31196 case VDIVBF16Zrrk:
31197 case VDIVBF16Zrrkz:
31198 return true;
31199 }
31200 return false;
31201}
31202
31203bool isMOVNTPD(unsigned Opcode) {
31204 return Opcode == MOVNTPDmr;
31205}
31206
31207bool isMAXSD(unsigned Opcode) {
31208 switch (Opcode) {
31209 case MAXSDrm_Int:
31210 case MAXSDrr_Int:
31211 return true;
31212 }
31213 return false;
31214}
31215
31216bool isCMPPD(unsigned Opcode) {
31217 switch (Opcode) {
31218 case CMPPDrmi:
31219 case CMPPDrri:
31220 return true;
31221 }
31222 return false;
31223}
31224
31225bool isVPCMPESTRM(unsigned Opcode) {
31226 switch (Opcode) {
31227 case VPCMPESTRMrmi:
31228 case VPCMPESTRMrri:
31229 return true;
31230 }
31231 return false;
31232}
31233
31234bool isVFMSUB132PS(unsigned Opcode) {
31235 switch (Opcode) {
31236 case VFMSUB132PSYm:
31237 case VFMSUB132PSYr:
31238 case VFMSUB132PSZ128m:
31239 case VFMSUB132PSZ128mb:
31240 case VFMSUB132PSZ128mbk:
31241 case VFMSUB132PSZ128mbkz:
31242 case VFMSUB132PSZ128mk:
31243 case VFMSUB132PSZ128mkz:
31244 case VFMSUB132PSZ128r:
31245 case VFMSUB132PSZ128rk:
31246 case VFMSUB132PSZ128rkz:
31247 case VFMSUB132PSZ256m:
31248 case VFMSUB132PSZ256mb:
31249 case VFMSUB132PSZ256mbk:
31250 case VFMSUB132PSZ256mbkz:
31251 case VFMSUB132PSZ256mk:
31252 case VFMSUB132PSZ256mkz:
31253 case VFMSUB132PSZ256r:
31254 case VFMSUB132PSZ256rk:
31255 case VFMSUB132PSZ256rkz:
31256 case VFMSUB132PSZm:
31257 case VFMSUB132PSZmb:
31258 case VFMSUB132PSZmbk:
31259 case VFMSUB132PSZmbkz:
31260 case VFMSUB132PSZmk:
31261 case VFMSUB132PSZmkz:
31262 case VFMSUB132PSZr:
31263 case VFMSUB132PSZrb:
31264 case VFMSUB132PSZrbk:
31265 case VFMSUB132PSZrbkz:
31266 case VFMSUB132PSZrk:
31267 case VFMSUB132PSZrkz:
31268 case VFMSUB132PSm:
31269 case VFMSUB132PSr:
31270 return true;
31271 }
31272 return false;
31273}
31274
31275bool isVCOMISH(unsigned Opcode) {
31276 switch (Opcode) {
31277 case VCOMISHZrm:
31278 case VCOMISHZrr:
31279 case VCOMISHZrrb:
31280 return true;
31281 }
31282 return false;
31283}
31284
31285bool isF2XM1(unsigned Opcode) {
31286 return Opcode == F2XM1;
31287}
31288
31289bool isSQRTPD(unsigned Opcode) {
31290 switch (Opcode) {
31291 case SQRTPDm:
31292 case SQRTPDr:
31293 return true;
31294 }
31295 return false;
31296}
31297
31298bool isVFMSUBADDPS(unsigned Opcode) {
31299 switch (Opcode) {
31300 case VFMSUBADDPS4Ymr:
31301 case VFMSUBADDPS4Yrm:
31302 case VFMSUBADDPS4Yrr:
31303 case VFMSUBADDPS4Yrr_REV:
31304 case VFMSUBADDPS4mr:
31305 case VFMSUBADDPS4rm:
31306 case VFMSUBADDPS4rr:
31307 case VFMSUBADDPS4rr_REV:
31308 return true;
31309 }
31310 return false;
31311}
31312
31313bool isFXTRACT(unsigned Opcode) {
31314 return Opcode == FXTRACT;
31315}
31316
31317bool isVP4DPWSSD(unsigned Opcode) {
31318 switch (Opcode) {
31319 case VP4DPWSSDrm:
31320 case VP4DPWSSDrmk:
31321 case VP4DPWSSDrmkz:
31322 return true;
31323 }
31324 return false;
31325}
31326
31327bool isTDPBHF8PS(unsigned Opcode) {
31328 return Opcode == TDPBHF8PS;
31329}
31330
31331bool isVFMSUBADDPD(unsigned Opcode) {
31332 switch (Opcode) {
31333 case VFMSUBADDPD4Ymr:
31334 case VFMSUBADDPD4Yrm:
31335 case VFMSUBADDPD4Yrr:
31336 case VFMSUBADDPD4Yrr_REV:
31337 case VFMSUBADDPD4mr:
31338 case VFMSUBADDPD4rm:
31339 case VFMSUBADDPD4rr:
31340 case VFMSUBADDPD4rr_REV:
31341 return true;
31342 }
31343 return false;
31344}
31345
31346bool isVBCSTNEBF162PS(unsigned Opcode) {
31347 switch (Opcode) {
31348 case VBCSTNEBF162PSYrm:
31349 case VBCSTNEBF162PSrm:
31350 return true;
31351 }
31352 return false;
31353}
31354
31355bool isVPGATHERQQ(unsigned Opcode) {
31356 switch (Opcode) {
31357 case VPGATHERQQYrm:
31358 case VPGATHERQQZ128rm:
31359 case VPGATHERQQZ256rm:
31360 case VPGATHERQQZrm:
31361 case VPGATHERQQrm:
31362 return true;
31363 }
31364 return false;
31365}
31366
31367bool isPCMPEQB(unsigned Opcode) {
31368 switch (Opcode) {
31369 case MMX_PCMPEQBrm:
31370 case MMX_PCMPEQBrr:
31371 case PCMPEQBrm:
31372 case PCMPEQBrr:
31373 return true;
31374 }
31375 return false;
31376}
31377
31378bool isTILESTORED(unsigned Opcode) {
31379 switch (Opcode) {
31380 case TILESTORED:
31381 case TILESTORED_EVEX:
31382 return true;
31383 }
31384 return false;
31385}
31386
31387bool isBLSMSK(unsigned Opcode) {
31388 switch (Opcode) {
31389 case BLSMSK32rm:
31390 case BLSMSK32rm_EVEX:
31391 case BLSMSK32rm_NF:
31392 case BLSMSK32rr:
31393 case BLSMSK32rr_EVEX:
31394 case BLSMSK32rr_NF:
31395 case BLSMSK64rm:
31396 case BLSMSK64rm_EVEX:
31397 case BLSMSK64rm_NF:
31398 case BLSMSK64rr:
31399 case BLSMSK64rr_EVEX:
31400 case BLSMSK64rr_NF:
31401 return true;
31402 }
31403 return false;
31404}
31405
31406bool isVCVTTPS2DQ(unsigned Opcode) {
31407 switch (Opcode) {
31408 case VCVTTPS2DQYrm:
31409 case VCVTTPS2DQYrr:
31410 case VCVTTPS2DQZ128rm:
31411 case VCVTTPS2DQZ128rmb:
31412 case VCVTTPS2DQZ128rmbk:
31413 case VCVTTPS2DQZ128rmbkz:
31414 case VCVTTPS2DQZ128rmk:
31415 case VCVTTPS2DQZ128rmkz:
31416 case VCVTTPS2DQZ128rr:
31417 case VCVTTPS2DQZ128rrk:
31418 case VCVTTPS2DQZ128rrkz:
31419 case VCVTTPS2DQZ256rm:
31420 case VCVTTPS2DQZ256rmb:
31421 case VCVTTPS2DQZ256rmbk:
31422 case VCVTTPS2DQZ256rmbkz:
31423 case VCVTTPS2DQZ256rmk:
31424 case VCVTTPS2DQZ256rmkz:
31425 case VCVTTPS2DQZ256rr:
31426 case VCVTTPS2DQZ256rrk:
31427 case VCVTTPS2DQZ256rrkz:
31428 case VCVTTPS2DQZrm:
31429 case VCVTTPS2DQZrmb:
31430 case VCVTTPS2DQZrmbk:
31431 case VCVTTPS2DQZrmbkz:
31432 case VCVTTPS2DQZrmk:
31433 case VCVTTPS2DQZrmkz:
31434 case VCVTTPS2DQZrr:
31435 case VCVTTPS2DQZrrb:
31436 case VCVTTPS2DQZrrbk:
31437 case VCVTTPS2DQZrrbkz:
31438 case VCVTTPS2DQZrrk:
31439 case VCVTTPS2DQZrrkz:
31440 case VCVTTPS2DQrm:
31441 case VCVTTPS2DQrr:
31442 return true;
31443 }
31444 return false;
31445}
31446
31447bool isVFPCLASSBF16(unsigned Opcode) {
31448 switch (Opcode) {
31449 case VFPCLASSBF16Z128mbi:
31450 case VFPCLASSBF16Z128mbik:
31451 case VFPCLASSBF16Z128mi:
31452 case VFPCLASSBF16Z128mik:
31453 case VFPCLASSBF16Z128ri:
31454 case VFPCLASSBF16Z128rik:
31455 case VFPCLASSBF16Z256mbi:
31456 case VFPCLASSBF16Z256mbik:
31457 case VFPCLASSBF16Z256mi:
31458 case VFPCLASSBF16Z256mik:
31459 case VFPCLASSBF16Z256ri:
31460 case VFPCLASSBF16Z256rik:
31461 case VFPCLASSBF16Zmbi:
31462 case VFPCLASSBF16Zmbik:
31463 case VFPCLASSBF16Zmi:
31464 case VFPCLASSBF16Zmik:
31465 case VFPCLASSBF16Zri:
31466 case VFPCLASSBF16Zrik:
31467 return true;
31468 }
31469 return false;
31470}
31471
31472bool isVRNDSCALEPD(unsigned Opcode) {
31473 switch (Opcode) {
31474 case VRNDSCALEPDZ128rmbi:
31475 case VRNDSCALEPDZ128rmbik:
31476 case VRNDSCALEPDZ128rmbikz:
31477 case VRNDSCALEPDZ128rmi:
31478 case VRNDSCALEPDZ128rmik:
31479 case VRNDSCALEPDZ128rmikz:
31480 case VRNDSCALEPDZ128rri:
31481 case VRNDSCALEPDZ128rrik:
31482 case VRNDSCALEPDZ128rrikz:
31483 case VRNDSCALEPDZ256rmbi:
31484 case VRNDSCALEPDZ256rmbik:
31485 case VRNDSCALEPDZ256rmbikz:
31486 case VRNDSCALEPDZ256rmi:
31487 case VRNDSCALEPDZ256rmik:
31488 case VRNDSCALEPDZ256rmikz:
31489 case VRNDSCALEPDZ256rri:
31490 case VRNDSCALEPDZ256rrik:
31491 case VRNDSCALEPDZ256rrikz:
31492 case VRNDSCALEPDZrmbi:
31493 case VRNDSCALEPDZrmbik:
31494 case VRNDSCALEPDZrmbikz:
31495 case VRNDSCALEPDZrmi:
31496 case VRNDSCALEPDZrmik:
31497 case VRNDSCALEPDZrmikz:
31498 case VRNDSCALEPDZrri:
31499 case VRNDSCALEPDZrrib:
31500 case VRNDSCALEPDZrribk:
31501 case VRNDSCALEPDZrribkz:
31502 case VRNDSCALEPDZrrik:
31503 case VRNDSCALEPDZrrikz:
31504 return true;
31505 }
31506 return false;
31507}
31508
31509bool isVMLOAD(unsigned Opcode) {
31510 switch (Opcode) {
31511 case VMLOAD32:
31512 case VMLOAD64:
31513 return true;
31514 }
31515 return false;
31516}
31517
31518bool isVPTERNLOGQ(unsigned Opcode) {
31519 switch (Opcode) {
31520 case VPTERNLOGQZ128rmbi:
31521 case VPTERNLOGQZ128rmbik:
31522 case VPTERNLOGQZ128rmbikz:
31523 case VPTERNLOGQZ128rmi:
31524 case VPTERNLOGQZ128rmik:
31525 case VPTERNLOGQZ128rmikz:
31526 case VPTERNLOGQZ128rri:
31527 case VPTERNLOGQZ128rrik:
31528 case VPTERNLOGQZ128rrikz:
31529 case VPTERNLOGQZ256rmbi:
31530 case VPTERNLOGQZ256rmbik:
31531 case VPTERNLOGQZ256rmbikz:
31532 case VPTERNLOGQZ256rmi:
31533 case VPTERNLOGQZ256rmik:
31534 case VPTERNLOGQZ256rmikz:
31535 case VPTERNLOGQZ256rri:
31536 case VPTERNLOGQZ256rrik:
31537 case VPTERNLOGQZ256rrikz:
31538 case VPTERNLOGQZrmbi:
31539 case VPTERNLOGQZrmbik:
31540 case VPTERNLOGQZrmbikz:
31541 case VPTERNLOGQZrmi:
31542 case VPTERNLOGQZrmik:
31543 case VPTERNLOGQZrmikz:
31544 case VPTERNLOGQZrri:
31545 case VPTERNLOGQZrrik:
31546 case VPTERNLOGQZrrikz:
31547 return true;
31548 }
31549 return false;
31550}
31551
31552bool isKXNORD(unsigned Opcode) {
31553 return Opcode == KXNORDkk;
31554}
31555
31556bool isFXSAVE(unsigned Opcode) {
31557 return Opcode == FXSAVE;
31558}
31559
31560bool isVUNPCKHPD(unsigned Opcode) {
31561 switch (Opcode) {
31562 case VUNPCKHPDYrm:
31563 case VUNPCKHPDYrr:
31564 case VUNPCKHPDZ128rm:
31565 case VUNPCKHPDZ128rmb:
31566 case VUNPCKHPDZ128rmbk:
31567 case VUNPCKHPDZ128rmbkz:
31568 case VUNPCKHPDZ128rmk:
31569 case VUNPCKHPDZ128rmkz:
31570 case VUNPCKHPDZ128rr:
31571 case VUNPCKHPDZ128rrk:
31572 case VUNPCKHPDZ128rrkz:
31573 case VUNPCKHPDZ256rm:
31574 case VUNPCKHPDZ256rmb:
31575 case VUNPCKHPDZ256rmbk:
31576 case VUNPCKHPDZ256rmbkz:
31577 case VUNPCKHPDZ256rmk:
31578 case VUNPCKHPDZ256rmkz:
31579 case VUNPCKHPDZ256rr:
31580 case VUNPCKHPDZ256rrk:
31581 case VUNPCKHPDZ256rrkz:
31582 case VUNPCKHPDZrm:
31583 case VUNPCKHPDZrmb:
31584 case VUNPCKHPDZrmbk:
31585 case VUNPCKHPDZrmbkz:
31586 case VUNPCKHPDZrmk:
31587 case VUNPCKHPDZrmkz:
31588 case VUNPCKHPDZrr:
31589 case VUNPCKHPDZrrk:
31590 case VUNPCKHPDZrrkz:
31591 case VUNPCKHPDrm:
31592 case VUNPCKHPDrr:
31593 return true;
31594 }
31595 return false;
31596}
31597
31598bool isCVTPS2DQ(unsigned Opcode) {
31599 switch (Opcode) {
31600 case CVTPS2DQrm:
31601 case CVTPS2DQrr:
31602 return true;
31603 }
31604 return false;
31605}
31606
31607bool isTMMULTF32PS(unsigned Opcode) {
31608 return Opcode == TMMULTF32PS;
31609}
31610
31611bool isVFMSUB213SS(unsigned Opcode) {
31612 switch (Opcode) {
31613 case VFMSUB213SSZm_Int:
31614 case VFMSUB213SSZmk_Int:
31615 case VFMSUB213SSZmkz_Int:
31616 case VFMSUB213SSZr_Int:
31617 case VFMSUB213SSZrb_Int:
31618 case VFMSUB213SSZrbk_Int:
31619 case VFMSUB213SSZrbkz_Int:
31620 case VFMSUB213SSZrk_Int:
31621 case VFMSUB213SSZrkz_Int:
31622 case VFMSUB213SSm_Int:
31623 case VFMSUB213SSr_Int:
31624 return true;
31625 }
31626 return false;
31627}
31628
31629bool isVPOPCNTD(unsigned Opcode) {
31630 switch (Opcode) {
31631 case VPOPCNTDZ128rm:
31632 case VPOPCNTDZ128rmb:
31633 case VPOPCNTDZ128rmbk:
31634 case VPOPCNTDZ128rmbkz:
31635 case VPOPCNTDZ128rmk:
31636 case VPOPCNTDZ128rmkz:
31637 case VPOPCNTDZ128rr:
31638 case VPOPCNTDZ128rrk:
31639 case VPOPCNTDZ128rrkz:
31640 case VPOPCNTDZ256rm:
31641 case VPOPCNTDZ256rmb:
31642 case VPOPCNTDZ256rmbk:
31643 case VPOPCNTDZ256rmbkz:
31644 case VPOPCNTDZ256rmk:
31645 case VPOPCNTDZ256rmkz:
31646 case VPOPCNTDZ256rr:
31647 case VPOPCNTDZ256rrk:
31648 case VPOPCNTDZ256rrkz:
31649 case VPOPCNTDZrm:
31650 case VPOPCNTDZrmb:
31651 case VPOPCNTDZrmbk:
31652 case VPOPCNTDZrmbkz:
31653 case VPOPCNTDZrmk:
31654 case VPOPCNTDZrmkz:
31655 case VPOPCNTDZrr:
31656 case VPOPCNTDZrrk:
31657 case VPOPCNTDZrrkz:
31658 return true;
31659 }
31660 return false;
31661}
31662
31663bool isSALC(unsigned Opcode) {
31664 return Opcode == SALC;
31665}
31666
31667bool isV4FNMADDSS(unsigned Opcode) {
31668 switch (Opcode) {
31669 case V4FNMADDSSrm:
31670 case V4FNMADDSSrmk:
31671 case V4FNMADDSSrmkz:
31672 return true;
31673 }
31674 return false;
31675}
31676
31677bool isXCRYPTOFB(unsigned Opcode) {
31678 return Opcode == XCRYPTOFB;
31679}
31680
31681bool isVORPD(unsigned Opcode) {
31682 switch (Opcode) {
31683 case VORPDYrm:
31684 case VORPDYrr:
31685 case VORPDZ128rm:
31686 case VORPDZ128rmb:
31687 case VORPDZ128rmbk:
31688 case VORPDZ128rmbkz:
31689 case VORPDZ128rmk:
31690 case VORPDZ128rmkz:
31691 case VORPDZ128rr:
31692 case VORPDZ128rrk:
31693 case VORPDZ128rrkz:
31694 case VORPDZ256rm:
31695 case VORPDZ256rmb:
31696 case VORPDZ256rmbk:
31697 case VORPDZ256rmbkz:
31698 case VORPDZ256rmk:
31699 case VORPDZ256rmkz:
31700 case VORPDZ256rr:
31701 case VORPDZ256rrk:
31702 case VORPDZ256rrkz:
31703 case VORPDZrm:
31704 case VORPDZrmb:
31705 case VORPDZrmbk:
31706 case VORPDZrmbkz:
31707 case VORPDZrmk:
31708 case VORPDZrmkz:
31709 case VORPDZrr:
31710 case VORPDZrrk:
31711 case VORPDZrrkz:
31712 case VORPDrm:
31713 case VORPDrr:
31714 return true;
31715 }
31716 return false;
31717}
31718
31719bool isLSL(unsigned Opcode) {
31720 switch (Opcode) {
31721 case LSL16rm:
31722 case LSL16rr:
31723 case LSL32rm:
31724 case LSL32rr:
31725 case LSL64rm:
31726 case LSL64rr:
31727 return true;
31728 }
31729 return false;
31730}
31731
31732bool isXCRYPTCFB(unsigned Opcode) {
31733 return Opcode == XCRYPTCFB;
31734}
31735
31736bool isVGETEXPSS(unsigned Opcode) {
31737 switch (Opcode) {
31738 case VGETEXPSSZm:
31739 case VGETEXPSSZmk:
31740 case VGETEXPSSZmkz:
31741 case VGETEXPSSZr:
31742 case VGETEXPSSZrb:
31743 case VGETEXPSSZrbk:
31744 case VGETEXPSSZrbkz:
31745 case VGETEXPSSZrk:
31746 case VGETEXPSSZrkz:
31747 return true;
31748 }
31749 return false;
31750}
31751
31752bool isPSLLDQ(unsigned Opcode) {
31753 return Opcode == PSLLDQri;
31754}
31755
31756bool isVPDPBUUD(unsigned Opcode) {
31757 switch (Opcode) {
31758 case VPDPBUUDYrm:
31759 case VPDPBUUDYrr:
31760 case VPDPBUUDZ128rm:
31761 case VPDPBUUDZ128rmb:
31762 case VPDPBUUDZ128rmbk:
31763 case VPDPBUUDZ128rmbkz:
31764 case VPDPBUUDZ128rmk:
31765 case VPDPBUUDZ128rmkz:
31766 case VPDPBUUDZ128rr:
31767 case VPDPBUUDZ128rrk:
31768 case VPDPBUUDZ128rrkz:
31769 case VPDPBUUDZ256rm:
31770 case VPDPBUUDZ256rmb:
31771 case VPDPBUUDZ256rmbk:
31772 case VPDPBUUDZ256rmbkz:
31773 case VPDPBUUDZ256rmk:
31774 case VPDPBUUDZ256rmkz:
31775 case VPDPBUUDZ256rr:
31776 case VPDPBUUDZ256rrk:
31777 case VPDPBUUDZ256rrkz:
31778 case VPDPBUUDZrm:
31779 case VPDPBUUDZrmb:
31780 case VPDPBUUDZrmbk:
31781 case VPDPBUUDZrmbkz:
31782 case VPDPBUUDZrmk:
31783 case VPDPBUUDZrmkz:
31784 case VPDPBUUDZrr:
31785 case VPDPBUUDZrrk:
31786 case VPDPBUUDZrrkz:
31787 case VPDPBUUDrm:
31788 case VPDPBUUDrr:
31789 return true;
31790 }
31791 return false;
31792}
31793
31794bool isVMXOFF(unsigned Opcode) {
31795 return Opcode == VMXOFF;
31796}
31797
31798bool isBLSIC(unsigned Opcode) {
31799 switch (Opcode) {
31800 case BLSIC32rm:
31801 case BLSIC32rr:
31802 case BLSIC64rm:
31803 case BLSIC64rr:
31804 return true;
31805 }
31806 return false;
31807}
31808
31809bool isMOVLHPS(unsigned Opcode) {
31810 return Opcode == MOVLHPSrr;
31811}
31812
31813bool isVMOVRSQ(unsigned Opcode) {
31814 switch (Opcode) {
31815 case VMOVRSQZ128m:
31816 case VMOVRSQZ128mk:
31817 case VMOVRSQZ128mkz:
31818 case VMOVRSQZ256m:
31819 case VMOVRSQZ256mk:
31820 case VMOVRSQZ256mkz:
31821 case VMOVRSQZm:
31822 case VMOVRSQZmk:
31823 case VMOVRSQZmkz:
31824 return true;
31825 }
31826 return false;
31827}
31828
31829bool isVFNMSUBSD(unsigned Opcode) {
31830 switch (Opcode) {
31831 case VFNMSUBSD4mr:
31832 case VFNMSUBSD4rm:
31833 case VFNMSUBSD4rr:
31834 case VFNMSUBSD4rr_REV:
31835 return true;
31836 }
31837 return false;
31838}
31839
31840bool isVCVTPH2IUBS(unsigned Opcode) {
31841 switch (Opcode) {
31842 case VCVTPH2IUBSZ128rm:
31843 case VCVTPH2IUBSZ128rmb:
31844 case VCVTPH2IUBSZ128rmbk:
31845 case VCVTPH2IUBSZ128rmbkz:
31846 case VCVTPH2IUBSZ128rmk:
31847 case VCVTPH2IUBSZ128rmkz:
31848 case VCVTPH2IUBSZ128rr:
31849 case VCVTPH2IUBSZ128rrk:
31850 case VCVTPH2IUBSZ128rrkz:
31851 case VCVTPH2IUBSZ256rm:
31852 case VCVTPH2IUBSZ256rmb:
31853 case VCVTPH2IUBSZ256rmbk:
31854 case VCVTPH2IUBSZ256rmbkz:
31855 case VCVTPH2IUBSZ256rmk:
31856 case VCVTPH2IUBSZ256rmkz:
31857 case VCVTPH2IUBSZ256rr:
31858 case VCVTPH2IUBSZ256rrk:
31859 case VCVTPH2IUBSZ256rrkz:
31860 case VCVTPH2IUBSZrm:
31861 case VCVTPH2IUBSZrmb:
31862 case VCVTPH2IUBSZrmbk:
31863 case VCVTPH2IUBSZrmbkz:
31864 case VCVTPH2IUBSZrmk:
31865 case VCVTPH2IUBSZrmkz:
31866 case VCVTPH2IUBSZrr:
31867 case VCVTPH2IUBSZrrb:
31868 case VCVTPH2IUBSZrrbk:
31869 case VCVTPH2IUBSZrrbkz:
31870 case VCVTPH2IUBSZrrk:
31871 case VCVTPH2IUBSZrrkz:
31872 return true;
31873 }
31874 return false;
31875}
31876
31877bool isVFPCLASSSH(unsigned Opcode) {
31878 switch (Opcode) {
31879 case VFPCLASSSHZmi:
31880 case VFPCLASSSHZmik:
31881 case VFPCLASSSHZri:
31882 case VFPCLASSSHZrik:
31883 return true;
31884 }
31885 return false;
31886}
31887
31888bool isVPSHLQ(unsigned Opcode) {
31889 switch (Opcode) {
31890 case VPSHLQmr:
31891 case VPSHLQrm:
31892 case VPSHLQrr:
31893 case VPSHLQrr_REV:
31894 return true;
31895 }
31896 return false;
31897}
31898
31899bool isVROUNDPS(unsigned Opcode) {
31900 switch (Opcode) {
31901 case VROUNDPSYmi:
31902 case VROUNDPSYri:
31903 case VROUNDPSmi:
31904 case VROUNDPSri:
31905 return true;
31906 }
31907 return false;
31908}
31909
31910bool isVSCATTERPF0QPS(unsigned Opcode) {
31911 return Opcode == VSCATTERPF0QPSm;
31912}
31913
31914bool isERETS(unsigned Opcode) {
31915 return Opcode == ERETS;
31916}
31917
31918bool isVPERMI2D(unsigned Opcode) {
31919 switch (Opcode) {
31920 case VPERMI2DZ128rm:
31921 case VPERMI2DZ128rmb:
31922 case VPERMI2DZ128rmbk:
31923 case VPERMI2DZ128rmbkz:
31924 case VPERMI2DZ128rmk:
31925 case VPERMI2DZ128rmkz:
31926 case VPERMI2DZ128rr:
31927 case VPERMI2DZ128rrk:
31928 case VPERMI2DZ128rrkz:
31929 case VPERMI2DZ256rm:
31930 case VPERMI2DZ256rmb:
31931 case VPERMI2DZ256rmbk:
31932 case VPERMI2DZ256rmbkz:
31933 case VPERMI2DZ256rmk:
31934 case VPERMI2DZ256rmkz:
31935 case VPERMI2DZ256rr:
31936 case VPERMI2DZ256rrk:
31937 case VPERMI2DZ256rrkz:
31938 case VPERMI2DZrm:
31939 case VPERMI2DZrmb:
31940 case VPERMI2DZrmbk:
31941 case VPERMI2DZrmbkz:
31942 case VPERMI2DZrmk:
31943 case VPERMI2DZrmkz:
31944 case VPERMI2DZrr:
31945 case VPERMI2DZrrk:
31946 case VPERMI2DZrrkz:
31947 return true;
31948 }
31949 return false;
31950}
31951
31952bool isFUCOMP(unsigned Opcode) {
31953 return Opcode == UCOM_FPr;
31954}
31955
31956bool isVCVTTPS2QQ(unsigned Opcode) {
31957 switch (Opcode) {
31958 case VCVTTPS2QQZ128rm:
31959 case VCVTTPS2QQZ128rmb:
31960 case VCVTTPS2QQZ128rmbk:
31961 case VCVTTPS2QQZ128rmbkz:
31962 case VCVTTPS2QQZ128rmk:
31963 case VCVTTPS2QQZ128rmkz:
31964 case VCVTTPS2QQZ128rr:
31965 case VCVTTPS2QQZ128rrk:
31966 case VCVTTPS2QQZ128rrkz:
31967 case VCVTTPS2QQZ256rm:
31968 case VCVTTPS2QQZ256rmb:
31969 case VCVTTPS2QQZ256rmbk:
31970 case VCVTTPS2QQZ256rmbkz:
31971 case VCVTTPS2QQZ256rmk:
31972 case VCVTTPS2QQZ256rmkz:
31973 case VCVTTPS2QQZ256rr:
31974 case VCVTTPS2QQZ256rrk:
31975 case VCVTTPS2QQZ256rrkz:
31976 case VCVTTPS2QQZrm:
31977 case VCVTTPS2QQZrmb:
31978 case VCVTTPS2QQZrmbk:
31979 case VCVTTPS2QQZrmbkz:
31980 case VCVTTPS2QQZrmk:
31981 case VCVTTPS2QQZrmkz:
31982 case VCVTTPS2QQZrr:
31983 case VCVTTPS2QQZrrb:
31984 case VCVTTPS2QQZrrbk:
31985 case VCVTTPS2QQZrrbkz:
31986 case VCVTTPS2QQZrrk:
31987 case VCVTTPS2QQZrrkz:
31988 return true;
31989 }
31990 return false;
31991}
31992
31993bool isPUSHFD(unsigned Opcode) {
31994 return Opcode == PUSHF32;
31995}
31996
31997bool isVPABSD(unsigned Opcode) {
31998 switch (Opcode) {
31999 case VPABSDYrm:
32000 case VPABSDYrr:
32001 case VPABSDZ128rm:
32002 case VPABSDZ128rmb:
32003 case VPABSDZ128rmbk:
32004 case VPABSDZ128rmbkz:
32005 case VPABSDZ128rmk:
32006 case VPABSDZ128rmkz:
32007 case VPABSDZ128rr:
32008 case VPABSDZ128rrk:
32009 case VPABSDZ128rrkz:
32010 case VPABSDZ256rm:
32011 case VPABSDZ256rmb:
32012 case VPABSDZ256rmbk:
32013 case VPABSDZ256rmbkz:
32014 case VPABSDZ256rmk:
32015 case VPABSDZ256rmkz:
32016 case VPABSDZ256rr:
32017 case VPABSDZ256rrk:
32018 case VPABSDZ256rrkz:
32019 case VPABSDZrm:
32020 case VPABSDZrmb:
32021 case VPABSDZrmbk:
32022 case VPABSDZrmbkz:
32023 case VPABSDZrmk:
32024 case VPABSDZrmkz:
32025 case VPABSDZrr:
32026 case VPABSDZrrk:
32027 case VPABSDZrrkz:
32028 case VPABSDrm:
32029 case VPABSDrr:
32030 return true;
32031 }
32032 return false;
32033}
32034
32035bool isKORB(unsigned Opcode) {
32036 return Opcode == KORBkk;
32037}
32038
32039bool isVRCP28PD(unsigned Opcode) {
32040 switch (Opcode) {
32041 case VRCP28PDZm:
32042 case VRCP28PDZmb:
32043 case VRCP28PDZmbk:
32044 case VRCP28PDZmbkz:
32045 case VRCP28PDZmk:
32046 case VRCP28PDZmkz:
32047 case VRCP28PDZr:
32048 case VRCP28PDZrb:
32049 case VRCP28PDZrbk:
32050 case VRCP28PDZrbkz:
32051 case VRCP28PDZrk:
32052 case VRCP28PDZrkz:
32053 return true;
32054 }
32055 return false;
32056}
32057
32058bool isVROUNDSS(unsigned Opcode) {
32059 switch (Opcode) {
32060 case VROUNDSSmi_Int:
32061 case VROUNDSSri_Int:
32062 return true;
32063 }
32064 return false;
32065}
32066
32067bool isVCVTSD2USI(unsigned Opcode) {
32068 switch (Opcode) {
32069 case VCVTSD2USI64Zrm_Int:
32070 case VCVTSD2USI64Zrr_Int:
32071 case VCVTSD2USI64Zrrb_Int:
32072 case VCVTSD2USIZrm_Int:
32073 case VCVTSD2USIZrr_Int:
32074 case VCVTSD2USIZrrb_Int:
32075 return true;
32076 }
32077 return false;
32078}
32079
32080bool isVPABSB(unsigned Opcode) {
32081 switch (Opcode) {
32082 case VPABSBYrm:
32083 case VPABSBYrr:
32084 case VPABSBZ128rm:
32085 case VPABSBZ128rmk:
32086 case VPABSBZ128rmkz:
32087 case VPABSBZ128rr:
32088 case VPABSBZ128rrk:
32089 case VPABSBZ128rrkz:
32090 case VPABSBZ256rm:
32091 case VPABSBZ256rmk:
32092 case VPABSBZ256rmkz:
32093 case VPABSBZ256rr:
32094 case VPABSBZ256rrk:
32095 case VPABSBZ256rrkz:
32096 case VPABSBZrm:
32097 case VPABSBZrmk:
32098 case VPABSBZrmkz:
32099 case VPABSBZrr:
32100 case VPABSBZrrk:
32101 case VPABSBZrrkz:
32102 case VPABSBrm:
32103 case VPABSBrr:
32104 return true;
32105 }
32106 return false;
32107}
32108
32109bool isPMAXUD(unsigned Opcode) {
32110 switch (Opcode) {
32111 case PMAXUDrm:
32112 case PMAXUDrr:
32113 return true;
32114 }
32115 return false;
32116}
32117
32118bool isVPERMPD(unsigned Opcode) {
32119 switch (Opcode) {
32120 case VPERMPDYmi:
32121 case VPERMPDYri:
32122 case VPERMPDZ256mbi:
32123 case VPERMPDZ256mbik:
32124 case VPERMPDZ256mbikz:
32125 case VPERMPDZ256mi:
32126 case VPERMPDZ256mik:
32127 case VPERMPDZ256mikz:
32128 case VPERMPDZ256ri:
32129 case VPERMPDZ256rik:
32130 case VPERMPDZ256rikz:
32131 case VPERMPDZ256rm:
32132 case VPERMPDZ256rmb:
32133 case VPERMPDZ256rmbk:
32134 case VPERMPDZ256rmbkz:
32135 case VPERMPDZ256rmk:
32136 case VPERMPDZ256rmkz:
32137 case VPERMPDZ256rr:
32138 case VPERMPDZ256rrk:
32139 case VPERMPDZ256rrkz:
32140 case VPERMPDZmbi:
32141 case VPERMPDZmbik:
32142 case VPERMPDZmbikz:
32143 case VPERMPDZmi:
32144 case VPERMPDZmik:
32145 case VPERMPDZmikz:
32146 case VPERMPDZri:
32147 case VPERMPDZrik:
32148 case VPERMPDZrikz:
32149 case VPERMPDZrm:
32150 case VPERMPDZrmb:
32151 case VPERMPDZrmbk:
32152 case VPERMPDZrmbkz:
32153 case VPERMPDZrmk:
32154 case VPERMPDZrmkz:
32155 case VPERMPDZrr:
32156 case VPERMPDZrrk:
32157 case VPERMPDZrrkz:
32158 return true;
32159 }
32160 return false;
32161}
32162
32163bool isVPMULHUW(unsigned Opcode) {
32164 switch (Opcode) {
32165 case VPMULHUWYrm:
32166 case VPMULHUWYrr:
32167 case VPMULHUWZ128rm:
32168 case VPMULHUWZ128rmk:
32169 case VPMULHUWZ128rmkz:
32170 case VPMULHUWZ128rr:
32171 case VPMULHUWZ128rrk:
32172 case VPMULHUWZ128rrkz:
32173 case VPMULHUWZ256rm:
32174 case VPMULHUWZ256rmk:
32175 case VPMULHUWZ256rmkz:
32176 case VPMULHUWZ256rr:
32177 case VPMULHUWZ256rrk:
32178 case VPMULHUWZ256rrkz:
32179 case VPMULHUWZrm:
32180 case VPMULHUWZrmk:
32181 case VPMULHUWZrmkz:
32182 case VPMULHUWZrr:
32183 case VPMULHUWZrrk:
32184 case VPMULHUWZrrkz:
32185 case VPMULHUWrm:
32186 case VPMULHUWrr:
32187 return true;
32188 }
32189 return false;
32190}
32191
32192bool isFCHS(unsigned Opcode) {
32193 return Opcode == CHS_F;
32194}
32195
32196bool isVPBLENDMB(unsigned Opcode) {
32197 switch (Opcode) {
32198 case VPBLENDMBZ128rm:
32199 case VPBLENDMBZ128rmk:
32200 case VPBLENDMBZ128rmkz:
32201 case VPBLENDMBZ128rr:
32202 case VPBLENDMBZ128rrk:
32203 case VPBLENDMBZ128rrkz:
32204 case VPBLENDMBZ256rm:
32205 case VPBLENDMBZ256rmk:
32206 case VPBLENDMBZ256rmkz:
32207 case VPBLENDMBZ256rr:
32208 case VPBLENDMBZ256rrk:
32209 case VPBLENDMBZ256rrkz:
32210 case VPBLENDMBZrm:
32211 case VPBLENDMBZrmk:
32212 case VPBLENDMBZrmkz:
32213 case VPBLENDMBZrr:
32214 case VPBLENDMBZrrk:
32215 case VPBLENDMBZrrkz:
32216 return true;
32217 }
32218 return false;
32219}
32220
32221bool isVGETMANTSS(unsigned Opcode) {
32222 switch (Opcode) {
32223 case VGETMANTSSZrmi:
32224 case VGETMANTSSZrmik:
32225 case VGETMANTSSZrmikz:
32226 case VGETMANTSSZrri:
32227 case VGETMANTSSZrrib:
32228 case VGETMANTSSZrribk:
32229 case VGETMANTSSZrribkz:
32230 case VGETMANTSSZrrik:
32231 case VGETMANTSSZrrikz:
32232 return true;
32233 }
32234 return false;
32235}
32236
32237bool isVPSLLW(unsigned Opcode) {
32238 switch (Opcode) {
32239 case VPSLLWYri:
32240 case VPSLLWYrm:
32241 case VPSLLWYrr:
32242 case VPSLLWZ128mi:
32243 case VPSLLWZ128mik:
32244 case VPSLLWZ128mikz:
32245 case VPSLLWZ128ri:
32246 case VPSLLWZ128rik:
32247 case VPSLLWZ128rikz:
32248 case VPSLLWZ128rm:
32249 case VPSLLWZ128rmk:
32250 case VPSLLWZ128rmkz:
32251 case VPSLLWZ128rr:
32252 case VPSLLWZ128rrk:
32253 case VPSLLWZ128rrkz:
32254 case VPSLLWZ256mi:
32255 case VPSLLWZ256mik:
32256 case VPSLLWZ256mikz:
32257 case VPSLLWZ256ri:
32258 case VPSLLWZ256rik:
32259 case VPSLLWZ256rikz:
32260 case VPSLLWZ256rm:
32261 case VPSLLWZ256rmk:
32262 case VPSLLWZ256rmkz:
32263 case VPSLLWZ256rr:
32264 case VPSLLWZ256rrk:
32265 case VPSLLWZ256rrkz:
32266 case VPSLLWZmi:
32267 case VPSLLWZmik:
32268 case VPSLLWZmikz:
32269 case VPSLLWZri:
32270 case VPSLLWZrik:
32271 case VPSLLWZrikz:
32272 case VPSLLWZrm:
32273 case VPSLLWZrmk:
32274 case VPSLLWZrmkz:
32275 case VPSLLWZrr:
32276 case VPSLLWZrrk:
32277 case VPSLLWZrrkz:
32278 case VPSLLWri:
32279 case VPSLLWrm:
32280 case VPSLLWrr:
32281 return true;
32282 }
32283 return false;
32284}
32285
32286bool isVDIVPD(unsigned Opcode) {
32287 switch (Opcode) {
32288 case VDIVPDYrm:
32289 case VDIVPDYrr:
32290 case VDIVPDZ128rm:
32291 case VDIVPDZ128rmb:
32292 case VDIVPDZ128rmbk:
32293 case VDIVPDZ128rmbkz:
32294 case VDIVPDZ128rmk:
32295 case VDIVPDZ128rmkz:
32296 case VDIVPDZ128rr:
32297 case VDIVPDZ128rrk:
32298 case VDIVPDZ128rrkz:
32299 case VDIVPDZ256rm:
32300 case VDIVPDZ256rmb:
32301 case VDIVPDZ256rmbk:
32302 case VDIVPDZ256rmbkz:
32303 case VDIVPDZ256rmk:
32304 case VDIVPDZ256rmkz:
32305 case VDIVPDZ256rr:
32306 case VDIVPDZ256rrk:
32307 case VDIVPDZ256rrkz:
32308 case VDIVPDZrm:
32309 case VDIVPDZrmb:
32310 case VDIVPDZrmbk:
32311 case VDIVPDZrmbkz:
32312 case VDIVPDZrmk:
32313 case VDIVPDZrmkz:
32314 case VDIVPDZrr:
32315 case VDIVPDZrrb:
32316 case VDIVPDZrrbk:
32317 case VDIVPDZrrbkz:
32318 case VDIVPDZrrk:
32319 case VDIVPDZrrkz:
32320 case VDIVPDrm:
32321 case VDIVPDrr:
32322 return true;
32323 }
32324 return false;
32325}
32326
32327bool isBLCMSK(unsigned Opcode) {
32328 switch (Opcode) {
32329 case BLCMSK32rm:
32330 case BLCMSK32rr:
32331 case BLCMSK64rm:
32332 case BLCMSK64rr:
32333 return true;
32334 }
32335 return false;
32336}
32337
32338bool isFDIV(unsigned Opcode) {
32339 switch (Opcode) {
32340 case DIV_F32m:
32341 case DIV_F64m:
32342 case DIV_FST0r:
32343 case DIV_FrST0:
32344 return true;
32345 }
32346 return false;
32347}
32348
32349bool isRSQRTSS(unsigned Opcode) {
32350 switch (Opcode) {
32351 case RSQRTSSm_Int:
32352 case RSQRTSSr_Int:
32353 return true;
32354 }
32355 return false;
32356}
32357
32358bool isPOR(unsigned Opcode) {
32359 switch (Opcode) {
32360 case MMX_PORrm:
32361 case MMX_PORrr:
32362 case PORrm:
32363 case PORrr:
32364 return true;
32365 }
32366 return false;
32367}
32368
32369bool isVMOVDQA32(unsigned Opcode) {
32370 switch (Opcode) {
32371 case VMOVDQA32Z128mr:
32372 case VMOVDQA32Z128mrk:
32373 case VMOVDQA32Z128rm:
32374 case VMOVDQA32Z128rmk:
32375 case VMOVDQA32Z128rmkz:
32376 case VMOVDQA32Z128rr:
32377 case VMOVDQA32Z128rr_REV:
32378 case VMOVDQA32Z128rrk:
32379 case VMOVDQA32Z128rrk_REV:
32380 case VMOVDQA32Z128rrkz:
32381 case VMOVDQA32Z128rrkz_REV:
32382 case VMOVDQA32Z256mr:
32383 case VMOVDQA32Z256mrk:
32384 case VMOVDQA32Z256rm:
32385 case VMOVDQA32Z256rmk:
32386 case VMOVDQA32Z256rmkz:
32387 case VMOVDQA32Z256rr:
32388 case VMOVDQA32Z256rr_REV:
32389 case VMOVDQA32Z256rrk:
32390 case VMOVDQA32Z256rrk_REV:
32391 case VMOVDQA32Z256rrkz:
32392 case VMOVDQA32Z256rrkz_REV:
32393 case VMOVDQA32Zmr:
32394 case VMOVDQA32Zmrk:
32395 case VMOVDQA32Zrm:
32396 case VMOVDQA32Zrmk:
32397 case VMOVDQA32Zrmkz:
32398 case VMOVDQA32Zrr:
32399 case VMOVDQA32Zrr_REV:
32400 case VMOVDQA32Zrrk:
32401 case VMOVDQA32Zrrk_REV:
32402 case VMOVDQA32Zrrkz:
32403 case VMOVDQA32Zrrkz_REV:
32404 return true;
32405 }
32406 return false;
32407}
32408
32409bool isVPHADDUWQ(unsigned Opcode) {
32410 switch (Opcode) {
32411 case VPHADDUWQrm:
32412 case VPHADDUWQrr:
32413 return true;
32414 }
32415 return false;
32416}
32417
32418bool isPSRAD(unsigned Opcode) {
32419 switch (Opcode) {
32420 case MMX_PSRADri:
32421 case MMX_PSRADrm:
32422 case MMX_PSRADrr:
32423 case PSRADri:
32424 case PSRADrm:
32425 case PSRADrr:
32426 return true;
32427 }
32428 return false;
32429}
32430
32431bool isPREFETCHW(unsigned Opcode) {
32432 return Opcode == PREFETCHW;
32433}
32434
32435bool isFIDIVR(unsigned Opcode) {
32436 switch (Opcode) {
32437 case DIVR_FI16m:
32438 case DIVR_FI32m:
32439 return true;
32440 }
32441 return false;
32442}
32443
32444bool isMOVHPS(unsigned Opcode) {
32445 switch (Opcode) {
32446 case MOVHPSmr:
32447 case MOVHPSrm:
32448 return true;
32449 }
32450 return false;
32451}
32452
32453bool isVFNMSUB231PH(unsigned Opcode) {
32454 switch (Opcode) {
32455 case VFNMSUB231PHZ128m:
32456 case VFNMSUB231PHZ128mb:
32457 case VFNMSUB231PHZ128mbk:
32458 case VFNMSUB231PHZ128mbkz:
32459 case VFNMSUB231PHZ128mk:
32460 case VFNMSUB231PHZ128mkz:
32461 case VFNMSUB231PHZ128r:
32462 case VFNMSUB231PHZ128rk:
32463 case VFNMSUB231PHZ128rkz:
32464 case VFNMSUB231PHZ256m:
32465 case VFNMSUB231PHZ256mb:
32466 case VFNMSUB231PHZ256mbk:
32467 case VFNMSUB231PHZ256mbkz:
32468 case VFNMSUB231PHZ256mk:
32469 case VFNMSUB231PHZ256mkz:
32470 case VFNMSUB231PHZ256r:
32471 case VFNMSUB231PHZ256rk:
32472 case VFNMSUB231PHZ256rkz:
32473 case VFNMSUB231PHZm:
32474 case VFNMSUB231PHZmb:
32475 case VFNMSUB231PHZmbk:
32476 case VFNMSUB231PHZmbkz:
32477 case VFNMSUB231PHZmk:
32478 case VFNMSUB231PHZmkz:
32479 case VFNMSUB231PHZr:
32480 case VFNMSUB231PHZrb:
32481 case VFNMSUB231PHZrbk:
32482 case VFNMSUB231PHZrbkz:
32483 case VFNMSUB231PHZrk:
32484 case VFNMSUB231PHZrkz:
32485 return true;
32486 }
32487 return false;
32488}
32489
32490bool isUNPCKLPS(unsigned Opcode) {
32491 switch (Opcode) {
32492 case UNPCKLPSrm:
32493 case UNPCKLPSrr:
32494 return true;
32495 }
32496 return false;
32497}
32498
32499bool isVPSIGNB(unsigned Opcode) {
32500 switch (Opcode) {
32501 case VPSIGNBYrm:
32502 case VPSIGNBYrr:
32503 case VPSIGNBrm:
32504 case VPSIGNBrr:
32505 return true;
32506 }
32507 return false;
32508}
32509
32510bool isSAVEPREVSSP(unsigned Opcode) {
32511 return Opcode == SAVEPREVSSP;
32512}
32513
32514bool isVSCALEFSD(unsigned Opcode) {
32515 switch (Opcode) {
32516 case VSCALEFSDZrm:
32517 case VSCALEFSDZrmk:
32518 case VSCALEFSDZrmkz:
32519 case VSCALEFSDZrr:
32520 case VSCALEFSDZrrb_Int:
32521 case VSCALEFSDZrrbk_Int:
32522 case VSCALEFSDZrrbkz_Int:
32523 case VSCALEFSDZrrk:
32524 case VSCALEFSDZrrkz:
32525 return true;
32526 }
32527 return false;
32528}
32529
32530bool isFSIN(unsigned Opcode) {
32531 return Opcode == FSIN;
32532}
32533
32534bool isSCASQ(unsigned Opcode) {
32535 return Opcode == SCASQ;
32536}
32537
32538bool isVCVTTPD2QQS(unsigned Opcode) {
32539 switch (Opcode) {
32540 case VCVTTPD2QQSZ128rm:
32541 case VCVTTPD2QQSZ128rmb:
32542 case VCVTTPD2QQSZ128rmbk:
32543 case VCVTTPD2QQSZ128rmbkz:
32544 case VCVTTPD2QQSZ128rmk:
32545 case VCVTTPD2QQSZ128rmkz:
32546 case VCVTTPD2QQSZ128rr:
32547 case VCVTTPD2QQSZ128rrk:
32548 case VCVTTPD2QQSZ128rrkz:
32549 case VCVTTPD2QQSZ256rm:
32550 case VCVTTPD2QQSZ256rmb:
32551 case VCVTTPD2QQSZ256rmbk:
32552 case VCVTTPD2QQSZ256rmbkz:
32553 case VCVTTPD2QQSZ256rmk:
32554 case VCVTTPD2QQSZ256rmkz:
32555 case VCVTTPD2QQSZ256rr:
32556 case VCVTTPD2QQSZ256rrb:
32557 case VCVTTPD2QQSZ256rrbk:
32558 case VCVTTPD2QQSZ256rrbkz:
32559 case VCVTTPD2QQSZ256rrk:
32560 case VCVTTPD2QQSZ256rrkz:
32561 case VCVTTPD2QQSZrm:
32562 case VCVTTPD2QQSZrmb:
32563 case VCVTTPD2QQSZrmbk:
32564 case VCVTTPD2QQSZrmbkz:
32565 case VCVTTPD2QQSZrmk:
32566 case VCVTTPD2QQSZrmkz:
32567 case VCVTTPD2QQSZrr:
32568 case VCVTTPD2QQSZrrb:
32569 case VCVTTPD2QQSZrrbk:
32570 case VCVTTPD2QQSZrrbkz:
32571 case VCVTTPD2QQSZrrk:
32572 case VCVTTPD2QQSZrrkz:
32573 return true;
32574 }
32575 return false;
32576}
32577
32578bool isPCMPGTW(unsigned Opcode) {
32579 switch (Opcode) {
32580 case MMX_PCMPGTWrm:
32581 case MMX_PCMPGTWrr:
32582 case PCMPGTWrm:
32583 case PCMPGTWrr:
32584 return true;
32585 }
32586 return false;
32587}
32588
32589bool isMULX(unsigned Opcode) {
32590 switch (Opcode) {
32591 case MULX32rm:
32592 case MULX32rm_EVEX:
32593 case MULX32rr:
32594 case MULX32rr_EVEX:
32595 case MULX64rm:
32596 case MULX64rm_EVEX:
32597 case MULX64rr:
32598 case MULX64rr_EVEX:
32599 return true;
32600 }
32601 return false;
32602}
32603
32604bool isVPMAXUW(unsigned Opcode) {
32605 switch (Opcode) {
32606 case VPMAXUWYrm:
32607 case VPMAXUWYrr:
32608 case VPMAXUWZ128rm:
32609 case VPMAXUWZ128rmk:
32610 case VPMAXUWZ128rmkz:
32611 case VPMAXUWZ128rr:
32612 case VPMAXUWZ128rrk:
32613 case VPMAXUWZ128rrkz:
32614 case VPMAXUWZ256rm:
32615 case VPMAXUWZ256rmk:
32616 case VPMAXUWZ256rmkz:
32617 case VPMAXUWZ256rr:
32618 case VPMAXUWZ256rrk:
32619 case VPMAXUWZ256rrkz:
32620 case VPMAXUWZrm:
32621 case VPMAXUWZrmk:
32622 case VPMAXUWZrmkz:
32623 case VPMAXUWZrr:
32624 case VPMAXUWZrrk:
32625 case VPMAXUWZrrkz:
32626 case VPMAXUWrm:
32627 case VPMAXUWrr:
32628 return true;
32629 }
32630 return false;
32631}
32632
32633bool isPAUSE(unsigned Opcode) {
32634 return Opcode == PAUSE;
32635}
32636
32637bool isMOVQ2DQ(unsigned Opcode) {
32638 return Opcode == MMX_MOVQ2DQrr;
32639}
32640
32641bool isVPABSW(unsigned Opcode) {
32642 switch (Opcode) {
32643 case VPABSWYrm:
32644 case VPABSWYrr:
32645 case VPABSWZ128rm:
32646 case VPABSWZ128rmk:
32647 case VPABSWZ128rmkz:
32648 case VPABSWZ128rr:
32649 case VPABSWZ128rrk:
32650 case VPABSWZ128rrkz:
32651 case VPABSWZ256rm:
32652 case VPABSWZ256rmk:
32653 case VPABSWZ256rmkz:
32654 case VPABSWZ256rr:
32655 case VPABSWZ256rrk:
32656 case VPABSWZ256rrkz:
32657 case VPABSWZrm:
32658 case VPABSWZrmk:
32659 case VPABSWZrmkz:
32660 case VPABSWZrr:
32661 case VPABSWZrrk:
32662 case VPABSWZrrkz:
32663 case VPABSWrm:
32664 case VPABSWrr:
32665 return true;
32666 }
32667 return false;
32668}
32669
32670bool isVPSUBQ(unsigned Opcode) {
32671 switch (Opcode) {
32672 case VPSUBQYrm:
32673 case VPSUBQYrr:
32674 case VPSUBQZ128rm:
32675 case VPSUBQZ128rmb:
32676 case VPSUBQZ128rmbk:
32677 case VPSUBQZ128rmbkz:
32678 case VPSUBQZ128rmk:
32679 case VPSUBQZ128rmkz:
32680 case VPSUBQZ128rr:
32681 case VPSUBQZ128rrk:
32682 case VPSUBQZ128rrkz:
32683 case VPSUBQZ256rm:
32684 case VPSUBQZ256rmb:
32685 case VPSUBQZ256rmbk:
32686 case VPSUBQZ256rmbkz:
32687 case VPSUBQZ256rmk:
32688 case VPSUBQZ256rmkz:
32689 case VPSUBQZ256rr:
32690 case VPSUBQZ256rrk:
32691 case VPSUBQZ256rrkz:
32692 case VPSUBQZrm:
32693 case VPSUBQZrmb:
32694 case VPSUBQZrmbk:
32695 case VPSUBQZrmbkz:
32696 case VPSUBQZrmk:
32697 case VPSUBQZrmkz:
32698 case VPSUBQZrr:
32699 case VPSUBQZrrk:
32700 case VPSUBQZrrkz:
32701 case VPSUBQrm:
32702 case VPSUBQrr:
32703 return true;
32704 }
32705 return false;
32706}
32707
32708bool isVPCOMPRESSD(unsigned Opcode) {
32709 switch (Opcode) {
32710 case VPCOMPRESSDZ128mr:
32711 case VPCOMPRESSDZ128mrk:
32712 case VPCOMPRESSDZ128rr:
32713 case VPCOMPRESSDZ128rrk:
32714 case VPCOMPRESSDZ128rrkz:
32715 case VPCOMPRESSDZ256mr:
32716 case VPCOMPRESSDZ256mrk:
32717 case VPCOMPRESSDZ256rr:
32718 case VPCOMPRESSDZ256rrk:
32719 case VPCOMPRESSDZ256rrkz:
32720 case VPCOMPRESSDZmr:
32721 case VPCOMPRESSDZmrk:
32722 case VPCOMPRESSDZrr:
32723 case VPCOMPRESSDZrrk:
32724 case VPCOMPRESSDZrrkz:
32725 return true;
32726 }
32727 return false;
32728}
32729
32730bool isVPMOVUSQW(unsigned Opcode) {
32731 switch (Opcode) {
32732 case VPMOVUSQWZ128mr:
32733 case VPMOVUSQWZ128mrk:
32734 case VPMOVUSQWZ128rr:
32735 case VPMOVUSQWZ128rrk:
32736 case VPMOVUSQWZ128rrkz:
32737 case VPMOVUSQWZ256mr:
32738 case VPMOVUSQWZ256mrk:
32739 case VPMOVUSQWZ256rr:
32740 case VPMOVUSQWZ256rrk:
32741 case VPMOVUSQWZ256rrkz:
32742 case VPMOVUSQWZmr:
32743 case VPMOVUSQWZmrk:
32744 case VPMOVUSQWZrr:
32745 case VPMOVUSQWZrrk:
32746 case VPMOVUSQWZrrkz:
32747 return true;
32748 }
32749 return false;
32750}
32751
32752bool isBLENDVPD(unsigned Opcode) {
32753 switch (Opcode) {
32754 case BLENDVPDrm0:
32755 case BLENDVPDrr0:
32756 return true;
32757 }
32758 return false;
32759}
32760
32761bool isVFNMADD132BF16(unsigned Opcode) {
32762 switch (Opcode) {
32763 case VFNMADD132BF16Z128m:
32764 case VFNMADD132BF16Z128mb:
32765 case VFNMADD132BF16Z128mbk:
32766 case VFNMADD132BF16Z128mbkz:
32767 case VFNMADD132BF16Z128mk:
32768 case VFNMADD132BF16Z128mkz:
32769 case VFNMADD132BF16Z128r:
32770 case VFNMADD132BF16Z128rk:
32771 case VFNMADD132BF16Z128rkz:
32772 case VFNMADD132BF16Z256m:
32773 case VFNMADD132BF16Z256mb:
32774 case VFNMADD132BF16Z256mbk:
32775 case VFNMADD132BF16Z256mbkz:
32776 case VFNMADD132BF16Z256mk:
32777 case VFNMADD132BF16Z256mkz:
32778 case VFNMADD132BF16Z256r:
32779 case VFNMADD132BF16Z256rk:
32780 case VFNMADD132BF16Z256rkz:
32781 case VFNMADD132BF16Zm:
32782 case VFNMADD132BF16Zmb:
32783 case VFNMADD132BF16Zmbk:
32784 case VFNMADD132BF16Zmbkz:
32785 case VFNMADD132BF16Zmk:
32786 case VFNMADD132BF16Zmkz:
32787 case VFNMADD132BF16Zr:
32788 case VFNMADD132BF16Zrk:
32789 case VFNMADD132BF16Zrkz:
32790 return true;
32791 }
32792 return false;
32793}
32794
32795bool isVPMOVQB(unsigned Opcode) {
32796 switch (Opcode) {
32797 case VPMOVQBZ128mr:
32798 case VPMOVQBZ128mrk:
32799 case VPMOVQBZ128rr:
32800 case VPMOVQBZ128rrk:
32801 case VPMOVQBZ128rrkz:
32802 case VPMOVQBZ256mr:
32803 case VPMOVQBZ256mrk:
32804 case VPMOVQBZ256rr:
32805 case VPMOVQBZ256rrk:
32806 case VPMOVQBZ256rrkz:
32807 case VPMOVQBZmr:
32808 case VPMOVQBZmrk:
32809 case VPMOVQBZrr:
32810 case VPMOVQBZrrk:
32811 case VPMOVQBZrrkz:
32812 return true;
32813 }
32814 return false;
32815}
32816
32817bool isVBLENDVPS(unsigned Opcode) {
32818 switch (Opcode) {
32819 case VBLENDVPSYrmr:
32820 case VBLENDVPSYrrr:
32821 case VBLENDVPSrmr:
32822 case VBLENDVPSrrr:
32823 return true;
32824 }
32825 return false;
32826}
32827
32828bool isKSHIFTLQ(unsigned Opcode) {
32829 return Opcode == KSHIFTLQki;
32830}
32831
32832bool isPMOVSXWD(unsigned Opcode) {
32833 switch (Opcode) {
32834 case PMOVSXWDrm:
32835 case PMOVSXWDrr:
32836 return true;
32837 }
32838 return false;
32839}
32840
32841bool isPHSUBSW(unsigned Opcode) {
32842 switch (Opcode) {
32843 case MMX_PHSUBSWrm:
32844 case MMX_PHSUBSWrr:
32845 case PHSUBSWrm:
32846 case PHSUBSWrr:
32847 return true;
32848 }
32849 return false;
32850}
32851
32852bool isPSRLQ(unsigned Opcode) {
32853 switch (Opcode) {
32854 case MMX_PSRLQri:
32855 case MMX_PSRLQrm:
32856 case MMX_PSRLQrr:
32857 case PSRLQri:
32858 case PSRLQrm:
32859 case PSRLQrr:
32860 return true;
32861 }
32862 return false;
32863}
32864
32865bool isVCVTPH2DQ(unsigned Opcode) {
32866 switch (Opcode) {
32867 case VCVTPH2DQZ128rm:
32868 case VCVTPH2DQZ128rmb:
32869 case VCVTPH2DQZ128rmbk:
32870 case VCVTPH2DQZ128rmbkz:
32871 case VCVTPH2DQZ128rmk:
32872 case VCVTPH2DQZ128rmkz:
32873 case VCVTPH2DQZ128rr:
32874 case VCVTPH2DQZ128rrk:
32875 case VCVTPH2DQZ128rrkz:
32876 case VCVTPH2DQZ256rm:
32877 case VCVTPH2DQZ256rmb:
32878 case VCVTPH2DQZ256rmbk:
32879 case VCVTPH2DQZ256rmbkz:
32880 case VCVTPH2DQZ256rmk:
32881 case VCVTPH2DQZ256rmkz:
32882 case VCVTPH2DQZ256rr:
32883 case VCVTPH2DQZ256rrk:
32884 case VCVTPH2DQZ256rrkz:
32885 case VCVTPH2DQZrm:
32886 case VCVTPH2DQZrmb:
32887 case VCVTPH2DQZrmbk:
32888 case VCVTPH2DQZrmbkz:
32889 case VCVTPH2DQZrmk:
32890 case VCVTPH2DQZrmkz:
32891 case VCVTPH2DQZrr:
32892 case VCVTPH2DQZrrb:
32893 case VCVTPH2DQZrrbk:
32894 case VCVTPH2DQZrrbkz:
32895 case VCVTPH2DQZrrk:
32896 case VCVTPH2DQZrrkz:
32897 return true;
32898 }
32899 return false;
32900}
32901
32902bool isPCMPESTRIQ(unsigned Opcode) {
32903 switch (Opcode) {
32904 case PCMPESTRIQrmi:
32905 case PCMPESTRIQrri:
32906 return true;
32907 }
32908 return false;
32909}
32910
32911bool isFISUB(unsigned Opcode) {
32912 switch (Opcode) {
32913 case SUB_FI16m:
32914 case SUB_FI32m:
32915 return true;
32916 }
32917 return false;
32918}
32919
32920bool isVCVTPS2UDQ(unsigned Opcode) {
32921 switch (Opcode) {
32922 case VCVTPS2UDQZ128rm:
32923 case VCVTPS2UDQZ128rmb:
32924 case VCVTPS2UDQZ128rmbk:
32925 case VCVTPS2UDQZ128rmbkz:
32926 case VCVTPS2UDQZ128rmk:
32927 case VCVTPS2UDQZ128rmkz:
32928 case VCVTPS2UDQZ128rr:
32929 case VCVTPS2UDQZ128rrk:
32930 case VCVTPS2UDQZ128rrkz:
32931 case VCVTPS2UDQZ256rm:
32932 case VCVTPS2UDQZ256rmb:
32933 case VCVTPS2UDQZ256rmbk:
32934 case VCVTPS2UDQZ256rmbkz:
32935 case VCVTPS2UDQZ256rmk:
32936 case VCVTPS2UDQZ256rmkz:
32937 case VCVTPS2UDQZ256rr:
32938 case VCVTPS2UDQZ256rrk:
32939 case VCVTPS2UDQZ256rrkz:
32940 case VCVTPS2UDQZrm:
32941 case VCVTPS2UDQZrmb:
32942 case VCVTPS2UDQZrmbk:
32943 case VCVTPS2UDQZrmbkz:
32944 case VCVTPS2UDQZrmk:
32945 case VCVTPS2UDQZrmkz:
32946 case VCVTPS2UDQZrr:
32947 case VCVTPS2UDQZrrb:
32948 case VCVTPS2UDQZrrbk:
32949 case VCVTPS2UDQZrrbkz:
32950 case VCVTPS2UDQZrrk:
32951 case VCVTPS2UDQZrrkz:
32952 return true;
32953 }
32954 return false;
32955}
32956
32957bool isVMOVDDUP(unsigned Opcode) {
32958 switch (Opcode) {
32959 case VMOVDDUPYrm:
32960 case VMOVDDUPYrr:
32961 case VMOVDDUPZ128rm:
32962 case VMOVDDUPZ128rmk:
32963 case VMOVDDUPZ128rmkz:
32964 case VMOVDDUPZ128rr:
32965 case VMOVDDUPZ128rrk:
32966 case VMOVDDUPZ128rrkz:
32967 case VMOVDDUPZ256rm:
32968 case VMOVDDUPZ256rmk:
32969 case VMOVDDUPZ256rmkz:
32970 case VMOVDDUPZ256rr:
32971 case VMOVDDUPZ256rrk:
32972 case VMOVDDUPZ256rrkz:
32973 case VMOVDDUPZrm:
32974 case VMOVDDUPZrmk:
32975 case VMOVDDUPZrmkz:
32976 case VMOVDDUPZrr:
32977 case VMOVDDUPZrrk:
32978 case VMOVDDUPZrrkz:
32979 case VMOVDDUPrm:
32980 case VMOVDDUPrr:
32981 return true;
32982 }
32983 return false;
32984}
32985
32986bool isPCMPEQD(unsigned Opcode) {
32987 switch (Opcode) {
32988 case MMX_PCMPEQDrm:
32989 case MMX_PCMPEQDrr:
32990 case PCMPEQDrm:
32991 case PCMPEQDrr:
32992 return true;
32993 }
32994 return false;
32995}
32996
32997bool isVRSQRT28SD(unsigned Opcode) {
32998 switch (Opcode) {
32999 case VRSQRT28SDZm:
33000 case VRSQRT28SDZmk:
33001 case VRSQRT28SDZmkz:
33002 case VRSQRT28SDZr:
33003 case VRSQRT28SDZrb:
33004 case VRSQRT28SDZrbk:
33005 case VRSQRT28SDZrbkz:
33006 case VRSQRT28SDZrk:
33007 case VRSQRT28SDZrkz:
33008 return true;
33009 }
33010 return false;
33011}
33012
33013bool isTDPHBF8PS(unsigned Opcode) {
33014 return Opcode == TDPHBF8PS;
33015}
33016
33017bool isVPOPCNTQ(unsigned Opcode) {
33018 switch (Opcode) {
33019 case VPOPCNTQZ128rm:
33020 case VPOPCNTQZ128rmb:
33021 case VPOPCNTQZ128rmbk:
33022 case VPOPCNTQZ128rmbkz:
33023 case VPOPCNTQZ128rmk:
33024 case VPOPCNTQZ128rmkz:
33025 case VPOPCNTQZ128rr:
33026 case VPOPCNTQZ128rrk:
33027 case VPOPCNTQZ128rrkz:
33028 case VPOPCNTQZ256rm:
33029 case VPOPCNTQZ256rmb:
33030 case VPOPCNTQZ256rmbk:
33031 case VPOPCNTQZ256rmbkz:
33032 case VPOPCNTQZ256rmk:
33033 case VPOPCNTQZ256rmkz:
33034 case VPOPCNTQZ256rr:
33035 case VPOPCNTQZ256rrk:
33036 case VPOPCNTQZ256rrkz:
33037 case VPOPCNTQZrm:
33038 case VPOPCNTQZrmb:
33039 case VPOPCNTQZrmbk:
33040 case VPOPCNTQZrmbkz:
33041 case VPOPCNTQZrmk:
33042 case VPOPCNTQZrmkz:
33043 case VPOPCNTQZrr:
33044 case VPOPCNTQZrrk:
33045 case VPOPCNTQZrrkz:
33046 return true;
33047 }
33048 return false;
33049}
33050
33051bool isLODSW(unsigned Opcode) {
33052 return Opcode == LODSW;
33053}
33054
33055bool isKSHIFTRB(unsigned Opcode) {
33056 return Opcode == KSHIFTRBki;
33057}
33058
33059bool isVFNMADDPS(unsigned Opcode) {
33060 switch (Opcode) {
33061 case VFNMADDPS4Ymr:
33062 case VFNMADDPS4Yrm:
33063 case VFNMADDPS4Yrr:
33064 case VFNMADDPS4Yrr_REV:
33065 case VFNMADDPS4mr:
33066 case VFNMADDPS4rm:
33067 case VFNMADDPS4rr:
33068 case VFNMADDPS4rr_REV:
33069 return true;
33070 }
33071 return false;
33072}
33073
33074bool isCCMPCC(unsigned Opcode) {
33075 switch (Opcode) {
33076 case CCMP16mi:
33077 case CCMP16mi8:
33078 case CCMP16mr:
33079 case CCMP16ri:
33080 case CCMP16ri8:
33081 case CCMP16rm:
33082 case CCMP16rr:
33083 case CCMP16rr_REV:
33084 case CCMP32mi:
33085 case CCMP32mi8:
33086 case CCMP32mr:
33087 case CCMP32ri:
33088 case CCMP32ri8:
33089 case CCMP32rm:
33090 case CCMP32rr:
33091 case CCMP32rr_REV:
33092 case CCMP64mi32:
33093 case CCMP64mi8:
33094 case CCMP64mr:
33095 case CCMP64ri32:
33096 case CCMP64ri8:
33097 case CCMP64rm:
33098 case CCMP64rr:
33099 case CCMP64rr_REV:
33100 case CCMP8mi:
33101 case CCMP8mr:
33102 case CCMP8ri:
33103 case CCMP8rm:
33104 case CCMP8rr:
33105 case CCMP8rr_REV:
33106 return true;
33107 }
33108 return false;
33109}
33110
33111bool isFXRSTOR64(unsigned Opcode) {
33112 return Opcode == FXRSTOR64;
33113}
33114
33115bool isVFMSUBADD213PD(unsigned Opcode) {
33116 switch (Opcode) {
33117 case VFMSUBADD213PDYm:
33118 case VFMSUBADD213PDYr:
33119 case VFMSUBADD213PDZ128m:
33120 case VFMSUBADD213PDZ128mb:
33121 case VFMSUBADD213PDZ128mbk:
33122 case VFMSUBADD213PDZ128mbkz:
33123 case VFMSUBADD213PDZ128mk:
33124 case VFMSUBADD213PDZ128mkz:
33125 case VFMSUBADD213PDZ128r:
33126 case VFMSUBADD213PDZ128rk:
33127 case VFMSUBADD213PDZ128rkz:
33128 case VFMSUBADD213PDZ256m:
33129 case VFMSUBADD213PDZ256mb:
33130 case VFMSUBADD213PDZ256mbk:
33131 case VFMSUBADD213PDZ256mbkz:
33132 case VFMSUBADD213PDZ256mk:
33133 case VFMSUBADD213PDZ256mkz:
33134 case VFMSUBADD213PDZ256r:
33135 case VFMSUBADD213PDZ256rk:
33136 case VFMSUBADD213PDZ256rkz:
33137 case VFMSUBADD213PDZm:
33138 case VFMSUBADD213PDZmb:
33139 case VFMSUBADD213PDZmbk:
33140 case VFMSUBADD213PDZmbkz:
33141 case VFMSUBADD213PDZmk:
33142 case VFMSUBADD213PDZmkz:
33143 case VFMSUBADD213PDZr:
33144 case VFMSUBADD213PDZrb:
33145 case VFMSUBADD213PDZrbk:
33146 case VFMSUBADD213PDZrbkz:
33147 case VFMSUBADD213PDZrk:
33148 case VFMSUBADD213PDZrkz:
33149 case VFMSUBADD213PDm:
33150 case VFMSUBADD213PDr:
33151 return true;
33152 }
33153 return false;
33154}
33155
33156bool isVSQRTPH(unsigned Opcode) {
33157 switch (Opcode) {
33158 case VSQRTPHZ128m:
33159 case VSQRTPHZ128mb:
33160 case VSQRTPHZ128mbk:
33161 case VSQRTPHZ128mbkz:
33162 case VSQRTPHZ128mk:
33163 case VSQRTPHZ128mkz:
33164 case VSQRTPHZ128r:
33165 case VSQRTPHZ128rk:
33166 case VSQRTPHZ128rkz:
33167 case VSQRTPHZ256m:
33168 case VSQRTPHZ256mb:
33169 case VSQRTPHZ256mbk:
33170 case VSQRTPHZ256mbkz:
33171 case VSQRTPHZ256mk:
33172 case VSQRTPHZ256mkz:
33173 case VSQRTPHZ256r:
33174 case VSQRTPHZ256rk:
33175 case VSQRTPHZ256rkz:
33176 case VSQRTPHZm:
33177 case VSQRTPHZmb:
33178 case VSQRTPHZmbk:
33179 case VSQRTPHZmbkz:
33180 case VSQRTPHZmk:
33181 case VSQRTPHZmkz:
33182 case VSQRTPHZr:
33183 case VSQRTPHZrb:
33184 case VSQRTPHZrbk:
33185 case VSQRTPHZrbkz:
33186 case VSQRTPHZrk:
33187 case VSQRTPHZrkz:
33188 return true;
33189 }
33190 return false;
33191}
33192
33193bool isPOPF(unsigned Opcode) {
33194 return Opcode == POPF16;
33195}
33196
33197bool isVPSUBUSB(unsigned Opcode) {
33198 switch (Opcode) {
33199 case VPSUBUSBYrm:
33200 case VPSUBUSBYrr:
33201 case VPSUBUSBZ128rm:
33202 case VPSUBUSBZ128rmk:
33203 case VPSUBUSBZ128rmkz:
33204 case VPSUBUSBZ128rr:
33205 case VPSUBUSBZ128rrk:
33206 case VPSUBUSBZ128rrkz:
33207 case VPSUBUSBZ256rm:
33208 case VPSUBUSBZ256rmk:
33209 case VPSUBUSBZ256rmkz:
33210 case VPSUBUSBZ256rr:
33211 case VPSUBUSBZ256rrk:
33212 case VPSUBUSBZ256rrkz:
33213 case VPSUBUSBZrm:
33214 case VPSUBUSBZrmk:
33215 case VPSUBUSBZrmkz:
33216 case VPSUBUSBZrr:
33217 case VPSUBUSBZrrk:
33218 case VPSUBUSBZrrkz:
33219 case VPSUBUSBrm:
33220 case VPSUBUSBrr:
33221 return true;
33222 }
33223 return false;
33224}
33225
33226bool isTCVTROWPS2BF16L(unsigned Opcode) {
33227 switch (Opcode) {
33228 case TCVTROWPS2BF16Lrte:
33229 case TCVTROWPS2BF16Lrti:
33230 return true;
33231 }
33232 return false;
33233}
33234
33235bool isVPADDSW(unsigned Opcode) {
33236 switch (Opcode) {
33237 case VPADDSWYrm:
33238 case VPADDSWYrr:
33239 case VPADDSWZ128rm:
33240 case VPADDSWZ128rmk:
33241 case VPADDSWZ128rmkz:
33242 case VPADDSWZ128rr:
33243 case VPADDSWZ128rrk:
33244 case VPADDSWZ128rrkz:
33245 case VPADDSWZ256rm:
33246 case VPADDSWZ256rmk:
33247 case VPADDSWZ256rmkz:
33248 case VPADDSWZ256rr:
33249 case VPADDSWZ256rrk:
33250 case VPADDSWZ256rrkz:
33251 case VPADDSWZrm:
33252 case VPADDSWZrmk:
33253 case VPADDSWZrmkz:
33254 case VPADDSWZrr:
33255 case VPADDSWZrrk:
33256 case VPADDSWZrrkz:
33257 case VPADDSWrm:
33258 case VPADDSWrr:
33259 return true;
33260 }
33261 return false;
33262}
33263
33264bool isPREFETCHIT1(unsigned Opcode) {
33265 return Opcode == PREFETCHIT1;
33266}
33267
33268bool isVADDSUBPD(unsigned Opcode) {
33269 switch (Opcode) {
33270 case VADDSUBPDYrm:
33271 case VADDSUBPDYrr:
33272 case VADDSUBPDrm:
33273 case VADDSUBPDrr:
33274 return true;
33275 }
33276 return false;
33277}
33278
33279bool isKANDD(unsigned Opcode) {
33280 return Opcode == KANDDkk;
33281}
33282
33283bool isPREFETCHRST2(unsigned Opcode) {
33284 return Opcode == PREFETCHRST2;
33285}
33286
33287bool isOUTSB(unsigned Opcode) {
33288 return Opcode == OUTSB;
33289}
33290
33291bool isFNSTSW(unsigned Opcode) {
33292 switch (Opcode) {
33293 case FNSTSW16r:
33294 case FNSTSWm:
33295 return true;
33296 }
33297 return false;
33298}
33299
33300bool isPMINSB(unsigned Opcode) {
33301 switch (Opcode) {
33302 case PMINSBrm:
33303 case PMINSBrr:
33304 return true;
33305 }
33306 return false;
33307}
33308
33309
33310} // namespace llvm::X86
33311
33312#endif // GET_X86_MNEMONIC_TABLES_CPP
33313
33314