1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* X86 Mnemonic tables *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_X86_MNEMONIC_TABLES_H
10#undef GET_X86_MNEMONIC_TABLES_H
11
12namespace llvm::X86 {
13
14bool isFSUBRP(unsigned Opcode);
15bool isVPDPBUSDS(unsigned Opcode);
16bool isPUNPCKLWD(unsigned Opcode);
17bool isVREDUCEBF16(unsigned Opcode);
18bool isPUNPCKLQDQ(unsigned Opcode);
19bool isRDFSBASE(unsigned Opcode);
20bool isVPCMOV(unsigned Opcode);
21bool isVDIVSD(unsigned Opcode);
22bool isVCVTTPS2IBS(unsigned Opcode);
23bool isVPEXTRW(unsigned Opcode);
24bool isLODSD(unsigned Opcode);
25bool isVPTESTNMQ(unsigned Opcode);
26bool isCVTSS2SD(unsigned Opcode);
27bool isVGETMANTPD(unsigned Opcode);
28bool isVMOVDQA64(unsigned Opcode);
29bool isINVLPG(unsigned Opcode);
30bool isVGETEXPBF16(unsigned Opcode);
31bool isVBROADCASTF64X4(unsigned Opcode);
32bool isVPERMI2Q(unsigned Opcode);
33bool isVPMOVSXBD(unsigned Opcode);
34bool isVFMSUB132SS(unsigned Opcode);
35bool isVPMOVUSDW(unsigned Opcode);
36bool isAAD(unsigned Opcode);
37bool isIDIV(unsigned Opcode);
38bool isCVTTPS2DQ(unsigned Opcode);
39bool isVBROADCASTF32X8(unsigned Opcode);
40bool isVFMSUBSS(unsigned Opcode);
41bool isEMMS(unsigned Opcode);
42bool isVPDPBSUD(unsigned Opcode);
43bool isPMOVSXWQ(unsigned Opcode);
44bool isPSRLW(unsigned Opcode);
45bool isMOVNTDQA(unsigned Opcode);
46bool isFUCOMPI(unsigned Opcode);
47bool isANDNPS(unsigned Opcode);
48bool isVINSERTF64X2(unsigned Opcode);
49bool isCLTS(unsigned Opcode);
50bool isSETSSBSY(unsigned Opcode);
51bool isVMULPD(unsigned Opcode);
52bool isVFMADDSUB132PS(unsigned Opcode);
53bool isVPMADCSWD(unsigned Opcode);
54bool isVSCATTERPF0DPS(unsigned Opcode);
55bool isXCHG(unsigned Opcode);
56bool isVGATHERPF1QPS(unsigned Opcode);
57bool isVCVTNEPS2BF16(unsigned Opcode);
58bool isVFMADDSS(unsigned Opcode);
59bool isINTO(unsigned Opcode);
60bool isANDPD(unsigned Opcode);
61bool isSEAMCALL(unsigned Opcode);
62bool isSHLD(unsigned Opcode);
63bool isUNPCKHPS(unsigned Opcode);
64bool isVPDPBSSDS(unsigned Opcode);
65bool isSETZUCC(unsigned Opcode);
66bool isSHUFPD(unsigned Opcode);
67bool isFCMOVNB(unsigned Opcode);
68bool isCVTTSS2SI(unsigned Opcode);
69bool isEXTRQ(unsigned Opcode);
70bool isVBROADCASTSS(unsigned Opcode);
71bool isCLUI(unsigned Opcode);
72bool isVINSERTI128(unsigned Opcode);
73bool isVPSHLDW(unsigned Opcode);
74bool isVBLENDPD(unsigned Opcode);
75bool isVSM4KEY4(unsigned Opcode);
76bool isVCVTNEEPH2PS(unsigned Opcode);
77bool isVCVTTSD2SI(unsigned Opcode);
78bool isWRMSRNS(unsigned Opcode);
79bool isCMPSB(unsigned Opcode);
80bool isVRCPBF16(unsigned Opcode);
81bool isMULSS(unsigned Opcode);
82bool isVMRUN(unsigned Opcode);
83bool isVPSRLVD(unsigned Opcode);
84bool isLEAVE(unsigned Opcode);
85bool isVGETMANTPS(unsigned Opcode);
86bool isXSHA256(unsigned Opcode);
87bool isBOUND(unsigned Opcode);
88bool isSFENCE(unsigned Opcode);
89bool isVPHADDD(unsigned Opcode);
90bool isADOX(unsigned Opcode);
91bool isVPSLLQ(unsigned Opcode);
92bool isVCVTPH2HF8(unsigned Opcode);
93bool isPFRSQIT1(unsigned Opcode);
94bool isCLAC(unsigned Opcode);
95bool isKNOTW(unsigned Opcode);
96bool isVCVTPH2PD(unsigned Opcode);
97bool isVAESENC(unsigned Opcode);
98bool isMOVNTI(unsigned Opcode);
99bool isFXCH(unsigned Opcode);
100bool isPOPP(unsigned Opcode);
101bool isVPBLENDMD(unsigned Opcode);
102bool isFSINCOS(unsigned Opcode);
103bool isVPMOVSXBW(unsigned Opcode);
104bool isVPMULLW(unsigned Opcode);
105bool isSTC(unsigned Opcode);
106bool isVPINSRB(unsigned Opcode);
107bool isLWPVAL(unsigned Opcode);
108bool isKXORB(unsigned Opcode);
109bool isRSTORSSP(unsigned Opcode);
110bool isVPRORQ(unsigned Opcode);
111bool isVSM3MSG1(unsigned Opcode);
112bool isFICOM(unsigned Opcode);
113bool isMAXPS(unsigned Opcode);
114bool isFNCLEX(unsigned Opcode);
115bool isVMOVMSKPS(unsigned Opcode);
116bool isVPMOVDB(unsigned Opcode);
117bool isLLWPCB(unsigned Opcode);
118bool isVMULSS(unsigned Opcode);
119bool isAESENCLAST(unsigned Opcode);
120bool isTILEMOVROW(unsigned Opcode);
121bool isVMINMAXPH(unsigned Opcode);
122bool isVPMAXUB(unsigned Opcode);
123bool isAAS(unsigned Opcode);
124bool isFADD(unsigned Opcode);
125bool isJMP(unsigned Opcode);
126bool isXCRYPTECB(unsigned Opcode);
127bool isPFRCPIT1(unsigned Opcode);
128bool isPMULHRW(unsigned Opcode);
129bool isVCVTPH2PS(unsigned Opcode);
130bool isVPBLENDVB(unsigned Opcode);
131bool isPCMPESTRI(unsigned Opcode);
132bool isSENDUIPI(unsigned Opcode);
133bool isFLDLN2(unsigned Opcode);
134bool isVPMACSWD(unsigned Opcode);
135bool isSHA1MSG1(unsigned Opcode);
136bool isVADDPS(unsigned Opcode);
137bool isVCVTPS2DQ(unsigned Opcode);
138bool isPFPNACC(unsigned Opcode);
139bool isFMUL(unsigned Opcode);
140bool isFNSAVE(unsigned Opcode);
141bool isCDQE(unsigned Opcode);
142bool isVPMACSDD(unsigned Opcode);
143bool isVSQRTPS(unsigned Opcode);
144bool isCMPSQ(unsigned Opcode);
145bool isVPSCATTERDD(unsigned Opcode);
146bool isVCVTTSD2USIS(unsigned Opcode);
147bool isVRNDSCALESD(unsigned Opcode);
148bool isSUBPS(unsigned Opcode);
149bool isVMAXSH(unsigned Opcode);
150bool isFLDZ(unsigned Opcode);
151bool isVFNMADD132SS(unsigned Opcode);
152bool isLGDTW(unsigned Opcode);
153bool isTCVTROWPS2PHH(unsigned Opcode);
154bool isINC(unsigned Opcode);
155bool isPABSB(unsigned Opcode);
156bool isVCVTROPS2HF8S(unsigned Opcode);
157bool isVPANDN(unsigned Opcode);
158bool isVCVTHF82HF6S(unsigned Opcode);
159bool isPHADDSW(unsigned Opcode);
160bool isVPMAXUD(unsigned Opcode);
161bool isVPMOVSQW(unsigned Opcode);
162bool isVSHA512RNDS2(unsigned Opcode);
163bool isADDSUBPS(unsigned Opcode);
164bool isVPMACSSDQL(unsigned Opcode);
165bool isPXOR(unsigned Opcode);
166bool isVPSRAD(unsigned Opcode);
167bool isVPSHAB(unsigned Opcode);
168bool isBTR(unsigned Opcode);
169bool isKORW(unsigned Opcode);
170bool isVRANGESS(unsigned Opcode);
171bool isVCMPPS(unsigned Opcode);
172bool isVPLZCNTD(unsigned Opcode);
173bool isTDPBUUD(unsigned Opcode);
174bool isROUNDPS(unsigned Opcode);
175bool isFABS(unsigned Opcode);
176bool isSUBPD(unsigned Opcode);
177bool isGF2P8MULB(unsigned Opcode);
178bool isTZMSK(unsigned Opcode);
179bool isVMINMAXSD(unsigned Opcode);
180bool isANDPS(unsigned Opcode);
181bool isVEXTRACTF32X8(unsigned Opcode);
182bool isSEAMRET(unsigned Opcode);
183bool isVPCOMW(unsigned Opcode);
184bool isVFIXUPIMMPD(unsigned Opcode);
185bool isKANDND(unsigned Opcode);
186bool isVMRESUME(unsigned Opcode);
187bool isCVTPD2DQ(unsigned Opcode);
188bool isVFNMADD213PS(unsigned Opcode);
189bool isVPEXTRD(unsigned Opcode);
190bool isPACKUSWB(unsigned Opcode);
191bool isVEXTRACTI32X8(unsigned Opcode);
192bool isVHADDPD(unsigned Opcode);
193bool isVPSADBW(unsigned Opcode);
194bool isMOVDQ2Q(unsigned Opcode);
195bool isPUNPCKHBW(unsigned Opcode);
196bool isXOR(unsigned Opcode);
197bool isPSIGNB(unsigned Opcode);
198bool isVPHADDSW(unsigned Opcode);
199bool isFADDP(unsigned Opcode);
200bool isNEG(unsigned Opcode);
201bool isFLDLG2(unsigned Opcode);
202bool isFNOP(unsigned Opcode);
203bool isVMINSS(unsigned Opcode);
204bool isPCMPISTRM(unsigned Opcode);
205bool isVFMADD132SS(unsigned Opcode);
206bool isFDIVRP(unsigned Opcode);
207bool isPUSHAL(unsigned Opcode);
208bool isSUBSD(unsigned Opcode);
209bool isVPBLENDMQ(unsigned Opcode);
210bool isVPMACSDQL(unsigned Opcode);
211bool isVGATHERDPS(unsigned Opcode);
212bool isRMPREAD(unsigned Opcode);
213bool isSYSRET(unsigned Opcode);
214bool isVPADDB(unsigned Opcode);
215bool isXEND(unsigned Opcode);
216bool isWRSSD(unsigned Opcode);
217bool isVMINMAXSS(unsigned Opcode);
218bool isVCVTDQ2PH(unsigned Opcode);
219bool isCVTPD2PS(unsigned Opcode);
220bool isMAXPD(unsigned Opcode);
221bool isRCPSS(unsigned Opcode);
222bool isVMOVAPD(unsigned Opcode);
223bool isVPSUBSB(unsigned Opcode);
224bool isRDTSC(unsigned Opcode);
225bool isVCVTTPS2UDQS(unsigned Opcode);
226bool isVPMADCSSWD(unsigned Opcode);
227bool isVFNMADD213PH(unsigned Opcode);
228bool isVGF2P8AFFINEQB(unsigned Opcode);
229bool isPMOVZXWD(unsigned Opcode);
230bool isPMINUD(unsigned Opcode);
231bool isXSUSLDTRK(unsigned Opcode);
232bool isVCVTPH2UW(unsigned Opcode);
233bool isPADDSW(unsigned Opcode);
234bool isLFENCE(unsigned Opcode);
235bool isCRC32(unsigned Opcode);
236bool isAESENCWIDE256KL(unsigned Opcode);
237bool isMOVAPD(unsigned Opcode);
238bool isVFMADD213PS(unsigned Opcode);
239bool isVPDPWUUDS(unsigned Opcode);
240bool isMOVSLDUP(unsigned Opcode);
241bool isCLDEMOTE(unsigned Opcode);
242bool isVCVTBIASPS2HF8S(unsigned Opcode);
243bool isVFNMADD231PS(unsigned Opcode);
244bool isVMOVMSKPD(unsigned Opcode);
245bool isPREFETCHT0(unsigned Opcode);
246bool isVCVTNEOBF162PS(unsigned Opcode);
247bool isVPCMPUD(unsigned Opcode);
248bool isVMAXSD(unsigned Opcode);
249bool isVRCP28SD(unsigned Opcode);
250bool isVMAXPS(unsigned Opcode);
251bool isVPMOVD2M(unsigned Opcode);
252bool isVPMACSSWD(unsigned Opcode);
253bool isVUCOMISD(unsigned Opcode);
254bool isLTR(unsigned Opcode);
255bool isVCVTUSI2SH(unsigned Opcode);
256bool isVSCATTERPF1QPS(unsigned Opcode);
257bool isWRGSBASE(unsigned Opcode);
258bool isSTOSQ(unsigned Opcode);
259bool isVSQRTSD(unsigned Opcode);
260bool isVPERMIL2PD(unsigned Opcode);
261bool isVFCMADDCSH(unsigned Opcode);
262bool isVFMADDSUB213PS(unsigned Opcode);
263bool isPFSUB(unsigned Opcode);
264bool isVSQRTSS(unsigned Opcode);
265bool isVEXPANDPS(unsigned Opcode);
266bool isVPCOMPRESSW(unsigned Opcode);
267bool isPEXTRD(unsigned Opcode);
268bool isVCVTTPS2UQQS(unsigned Opcode);
269bool isSYSEXITQ(unsigned Opcode);
270bool isROUNDSD(unsigned Opcode);
271bool isVFMADD132BF16(unsigned Opcode);
272bool isFCOM(unsigned Opcode);
273bool isVFNMSUBSS(unsigned Opcode);
274bool isKSHIFTLW(unsigned Opcode);
275bool isVMPTRLD(unsigned Opcode);
276bool isSCASD(unsigned Opcode);
277bool isVAESDECLAST(unsigned Opcode);
278bool isVFMADDSUBPS(unsigned Opcode);
279bool isVCVTUQQ2PS(unsigned Opcode);
280bool isVPMOVUSDB(unsigned Opcode);
281bool isVPROTW(unsigned Opcode);
282bool isVDPPS(unsigned Opcode);
283bool isVRSQRT14PD(unsigned Opcode);
284bool isVTESTPD(unsigned Opcode);
285bool isVFNMADD231SH(unsigned Opcode);
286bool isENDBR64(unsigned Opcode);
287bool isMULSD(unsigned Opcode);
288bool isXRSTORS(unsigned Opcode);
289bool isPREFETCHNTA(unsigned Opcode);
290bool isVPCOMD(unsigned Opcode);
291bool isVPCOMUB(unsigned Opcode);
292bool isVPDPBSSD(unsigned Opcode);
293bool isVCVTBIASPS2BF8(unsigned Opcode);
294bool isVPHSUBD(unsigned Opcode);
295bool isVBROADCASTI64X2(unsigned Opcode);
296bool isFPATAN(unsigned Opcode);
297bool isLOOPE(unsigned Opcode);
298bool isPCMPEQW(unsigned Opcode);
299bool isVFMADDCSH(unsigned Opcode);
300bool isMOVRS(unsigned Opcode);
301bool isVFMSUBADD132PH(unsigned Opcode);
302bool isKADDW(unsigned Opcode);
303bool isPTEST(unsigned Opcode);
304bool isVPADDSB(unsigned Opcode);
305bool isVRSQRT28PS(unsigned Opcode);
306bool isVGF2P8AFFINEINVQB(unsigned Opcode);
307bool isSERIALIZE(unsigned Opcode);
308bool isVPHADDWQ(unsigned Opcode);
309bool isVRNDSCALESH(unsigned Opcode);
310bool isAAA(unsigned Opcode);
311bool isVADDBF16(unsigned Opcode);
312bool isWRMSRLIST(unsigned Opcode);
313bool isVCVTPH2PSX(unsigned Opcode);
314bool isVFMSUB231PH(unsigned Opcode);
315bool isVGATHERQPD(unsigned Opcode);
316bool isKADDB(unsigned Opcode);
317bool isCVTPD2PI(unsigned Opcode);
318bool isVFNMSUB213PH(unsigned Opcode);
319bool isVPCMPESTRI(unsigned Opcode);
320bool isVPSHRDW(unsigned Opcode);
321bool isXORPS(unsigned Opcode);
322bool isPOP2(unsigned Opcode);
323bool isRDMSRLIST(unsigned Opcode);
324bool isVPDPBUSD(unsigned Opcode);
325bool isVCMPPH(unsigned Opcode);
326bool isVANDNPD(unsigned Opcode);
327bool isSUB(unsigned Opcode);
328bool isVRSQRT28PD(unsigned Opcode);
329bool isVFNMADD132PH(unsigned Opcode);
330bool isVPMACSSWW(unsigned Opcode);
331bool isXSTORE(unsigned Opcode);
332bool isVPROTQ(unsigned Opcode);
333bool isVPHADDBD(unsigned Opcode);
334bool isVPMAXSB(unsigned Opcode);
335bool isVMOVDQU8(unsigned Opcode);
336bool isVPMOVSXWD(unsigned Opcode);
337bool isVMINMAXPD(unsigned Opcode);
338bool isSHA256RNDS2(unsigned Opcode);
339bool isKANDB(unsigned Opcode);
340bool isTPAUSE(unsigned Opcode);
341bool isPUSH(unsigned Opcode);
342bool isVRNDSCALESS(unsigned Opcode);
343bool isVRNDSCALEBF16(unsigned Opcode);
344bool isVPCMPISTRI(unsigned Opcode);
345bool isSTGI(unsigned Opcode);
346bool isSBB(unsigned Opcode);
347bool isBLCS(unsigned Opcode);
348bool isVCVTSD2SH(unsigned Opcode);
349bool isVPERMW(unsigned Opcode);
350bool isXRESLDTRK(unsigned Opcode);
351bool isAESENC256KL(unsigned Opcode);
352bool isVGATHERDPD(unsigned Opcode);
353bool isHRESET(unsigned Opcode);
354bool isVFMSUBADD231PD(unsigned Opcode);
355bool isVFRCZSS(unsigned Opcode);
356bool isMINPS(unsigned Opcode);
357bool isFPREM1(unsigned Opcode);
358bool isVPCMPUB(unsigned Opcode);
359bool isVSQRTPD(unsigned Opcode);
360bool isVFRCZPS(unsigned Opcode);
361bool isVFNMADD213SS(unsigned Opcode);
362bool isVPSHRDVQ(unsigned Opcode);
363bool isVPMOVDW(unsigned Opcode);
364bool isVCVTPH2HF8S(unsigned Opcode);
365bool isVBROADCASTSD(unsigned Opcode);
366bool isVSHUFPD(unsigned Opcode);
367bool isVPSUBSW(unsigned Opcode);
368bool isKUNPCKBW(unsigned Opcode);
369bool isVPBLENDD(unsigned Opcode);
370bool isUNPCKHPD(unsigned Opcode);
371bool isVFNMADD231SD(unsigned Opcode);
372bool isVPBROADCASTMW2D(unsigned Opcode);
373bool isVCVTBF82PS(unsigned Opcode);
374bool isVPMULTISHIFTQB(unsigned Opcode);
375bool isVP2INTERSECTQ(unsigned Opcode);
376bool isVFNMSUB132BF16(unsigned Opcode);
377bool isVFMADD213BF16(unsigned Opcode);
378bool isVPUNPCKHWD(unsigned Opcode);
379bool isVPERM2F128(unsigned Opcode);
380bool isINSD(unsigned Opcode);
381bool isLFS(unsigned Opcode);
382bool isFMULP(unsigned Opcode);
383bool isCWD(unsigned Opcode);
384bool isVDIVSS(unsigned Opcode);
385bool isVPSRLQ(unsigned Opcode);
386bool isFSQRT(unsigned Opcode);
387bool isJRCXZ(unsigned Opcode);
388bool isVPMOVMSKB(unsigned Opcode);
389bool isAESDEC256KL(unsigned Opcode);
390bool isFLDENV(unsigned Opcode);
391bool isVPHSUBWD(unsigned Opcode);
392bool isWBNOINVD(unsigned Opcode);
393bool isVEXPANDPD(unsigned Opcode);
394bool isFYL2XP1(unsigned Opcode);
395bool isPREFETCHT2(unsigned Opcode);
396bool isVPDPBSUDS(unsigned Opcode);
397bool isVSHA512MSG2(unsigned Opcode);
398bool isVCVTBIASPS2HF8(unsigned Opcode);
399bool isPMULHUW(unsigned Opcode);
400bool isKANDNB(unsigned Opcode);
401bool isVCVTUW2PH(unsigned Opcode);
402bool isAESDECWIDE256KL(unsigned Opcode);
403bool isVPGATHERDD(unsigned Opcode);
404bool isVREDUCESH(unsigned Opcode);
405bool isPOPFQ(unsigned Opcode);
406bool isPAVGUSB(unsigned Opcode);
407bool isVALIGND(unsigned Opcode);
408bool isVPHMINPOSUW(unsigned Opcode);
409bool isLIDTD(unsigned Opcode);
410bool isVPERMT2PD(unsigned Opcode);
411bool isVMLAUNCH(unsigned Opcode);
412bool isVPXORQ(unsigned Opcode);
413bool isMOVNTDQ(unsigned Opcode);
414bool isPOP2P(unsigned Opcode);
415bool isVADDPD(unsigned Opcode);
416bool isSMSW(unsigned Opcode);
417bool isVEXP2PD(unsigned Opcode);
418bool isPMULUDQ(unsigned Opcode);
419bool isIRET(unsigned Opcode);
420bool isMULPS(unsigned Opcode);
421bool isTDPBF8PS(unsigned Opcode);
422bool isVFNMSUBPD(unsigned Opcode);
423bool isPHADDW(unsigned Opcode);
424bool isRDSEED(unsigned Opcode);
425bool isVPSHLW(unsigned Opcode);
426bool isRMPUPDATE(unsigned Opcode);
427bool isVFMADD231PH(unsigned Opcode);
428bool isVPSHAD(unsigned Opcode);
429bool isCLWB(unsigned Opcode);
430bool isPSUBUSB(unsigned Opcode);
431bool isVCVTTSD2USI(unsigned Opcode);
432bool isVEXTRACTPS(unsigned Opcode);
433bool isMOVLPD(unsigned Opcode);
434bool isLGDTD(unsigned Opcode);
435bool isVPBROADCASTMB2Q(unsigned Opcode);
436bool isOUT(unsigned Opcode);
437bool isVMSAVE(unsigned Opcode);
438bool isVCVTQQ2PD(unsigned Opcode);
439bool isVFMADD213PH(unsigned Opcode);
440bool isFCMOVBE(unsigned Opcode);
441bool isMOVSHDUP(unsigned Opcode);
442bool isVPMOVUSQB(unsigned Opcode);
443bool isFIST(unsigned Opcode);
444bool isHADDPD(unsigned Opcode);
445bool isPACKSSWB(unsigned Opcode);
446bool isVPMACSSDQH(unsigned Opcode);
447bool isVFNMSUB132SD(unsigned Opcode);
448bool isVPMASKMOVQ(unsigned Opcode);
449bool isVCOMPRESSPD(unsigned Opcode);
450bool isVFMADD213SS(unsigned Opcode);
451bool isVPCMPQ(unsigned Opcode);
452bool isVADDSH(unsigned Opcode);
453bool isVFNMADDSD(unsigned Opcode);
454bool isUMWAIT(unsigned Opcode);
455bool isVPUNPCKHDQ(unsigned Opcode);
456bool isLCALL(unsigned Opcode);
457bool isAESDEC128KL(unsigned Opcode);
458bool isVSUBPS(unsigned Opcode);
459bool isFSTP(unsigned Opcode);
460bool isVCVTUDQ2PD(unsigned Opcode);
461bool isVPMOVSWB(unsigned Opcode);
462bool isVPANDNQ(unsigned Opcode);
463bool isSYSENTER(unsigned Opcode);
464bool isVPHADDWD(unsigned Opcode);
465bool isVMOVHPD(unsigned Opcode);
466bool isMOVHPD(unsigned Opcode);
467bool isVDIVPH(unsigned Opcode);
468bool isFFREE(unsigned Opcode);
469bool isVGATHERPF1DPS(unsigned Opcode);
470bool isVPCMPESTRIQ(unsigned Opcode);
471bool isVFNMADD231PD(unsigned Opcode);
472bool isVFCMULCPH(unsigned Opcode);
473bool isVPADDD(unsigned Opcode);
474bool isVPCOMUQ(unsigned Opcode);
475bool isVSM3MSG2(unsigned Opcode);
476bool isVERR(unsigned Opcode);
477bool isKORTESTQ(unsigned Opcode);
478bool isVFMSUB132SD(unsigned Opcode);
479bool isTILEZERO(unsigned Opcode);
480bool isPFADD(unsigned Opcode);
481bool isVCVTSI2SD(unsigned Opcode);
482bool isTILELOADDRS(unsigned Opcode);
483bool isVSTMXCSR(unsigned Opcode);
484bool isVCVTTSH2SI(unsigned Opcode);
485bool isRET(unsigned Opcode);
486bool isLZCNT(unsigned Opcode);
487bool isMULPD(unsigned Opcode);
488bool isVBROADCASTI32X2(unsigned Opcode);
489bool isVCVTPH2W(unsigned Opcode);
490bool isCQO(unsigned Opcode);
491bool isFSUBR(unsigned Opcode);
492bool isDPPD(unsigned Opcode);
493bool isFCOS(unsigned Opcode);
494bool isXSAVES(unsigned Opcode);
495bool isTZCNT(unsigned Opcode);
496bool isVCVTHF62HF8(unsigned Opcode);
497bool isLJMP(unsigned Opcode);
498bool isCMOVCC(unsigned Opcode);
499bool isVCVTBIASPH2HF8(unsigned Opcode);
500bool isINVEPT(unsigned Opcode);
501bool isADDSUBPD(unsigned Opcode);
502bool isVCVTSS2SD(unsigned Opcode);
503bool isVMOVSHDUP(unsigned Opcode);
504bool isKSHIFTRD(unsigned Opcode);
505bool isVPTERNLOGD(unsigned Opcode);
506bool isPADDQ(unsigned Opcode);
507bool isVEXTRACTI64X4(unsigned Opcode);
508bool isVFMSUB231SS(unsigned Opcode);
509bool isVPCMPEQB(unsigned Opcode);
510bool isLEA(unsigned Opcode);
511bool isPSUBB(unsigned Opcode);
512bool isKADDQ(unsigned Opcode);
513bool isMOVSX(unsigned Opcode);
514bool isVALIGNQ(unsigned Opcode);
515bool isVCVTNE2PS2BF16(unsigned Opcode);
516bool isVPSRAW(unsigned Opcode);
517bool isVFMSUBADD231PH(unsigned Opcode);
518bool isCVTDQ2PS(unsigned Opcode);
519bool isFBLD(unsigned Opcode);
520bool isLMSW(unsigned Opcode);
521bool isVRNDSCALEPH(unsigned Opcode);
522bool isMINSS(unsigned Opcode);
523bool isWRMSR(unsigned Opcode);
524bool isFSCALE(unsigned Opcode);
525bool isVFNMADD213SH(unsigned Opcode);
526bool isIMULZU(unsigned Opcode);
527bool isVPHADDUBD(unsigned Opcode);
528bool isRDSSPQ(unsigned Opcode);
529bool isVCVTBF162IBS(unsigned Opcode);
530bool isLGDT(unsigned Opcode);
531bool isVPSHLDVD(unsigned Opcode);
532bool isPFCMPGT(unsigned Opcode);
533bool isJCXZ(unsigned Opcode);
534bool isVPMOVZXBW(unsigned Opcode);
535bool isVFMADDSUB231PD(unsigned Opcode);
536bool isVBLENDMPD(unsigned Opcode);
537bool isHSUBPS(unsigned Opcode);
538bool isPREFETCHIT0(unsigned Opcode);
539bool isKTESTD(unsigned Opcode);
540bool isVCVTNEOPH2PS(unsigned Opcode);
541bool isVBLENDVPD(unsigned Opcode);
542bool isVCVTSS2USI(unsigned Opcode);
543bool isVCVTTPS2DQS(unsigned Opcode);
544bool isVPANDD(unsigned Opcode);
545bool isPMINSW(unsigned Opcode);
546bool isSTAC(unsigned Opcode);
547bool isVFMSUB213PS(unsigned Opcode);
548bool isPOPAL(unsigned Opcode);
549bool isVCVTPS2UQQ(unsigned Opcode);
550bool isRDRAND(unsigned Opcode);
551bool isJCC(unsigned Opcode);
552bool isVPMINSQ(unsigned Opcode);
553bool isVADDSD(unsigned Opcode);
554bool isDPPS(unsigned Opcode);
555bool isPINSRQ(unsigned Opcode);
556bool isVUCOMISS(unsigned Opcode);
557bool isVPDPWSUD(unsigned Opcode);
558bool isKANDNW(unsigned Opcode);
559bool isAOR(unsigned Opcode);
560bool isPMAXUB(unsigned Opcode);
561bool isANDNPD(unsigned Opcode);
562bool isINVPCID(unsigned Opcode);
563bool isRDGSBASE(unsigned Opcode);
564bool isVPMOVSQD(unsigned Opcode);
565bool isBT(unsigned Opcode);
566bool isVPROLVQ(unsigned Opcode);
567bool isVFMADDSUB132PD(unsigned Opcode);
568bool isRORX(unsigned Opcode);
569bool isPADDUSW(unsigned Opcode);
570bool isPFNACC(unsigned Opcode);
571bool isAND(unsigned Opcode);
572bool isPSLLQ(unsigned Opcode);
573bool isVFMSUB132PH(unsigned Opcode);
574bool isXSAVE(unsigned Opcode);
575bool isKNOTQ(unsigned Opcode);
576bool isXTEST(unsigned Opcode);
577bool isVINSERTPS(unsigned Opcode);
578bool isXSAVEOPT(unsigned Opcode);
579bool isLDS(unsigned Opcode);
580bool isVFMADDSUB213PD(unsigned Opcode);
581bool isVINSERTF32X4(unsigned Opcode);
582bool isVRSQRTPS(unsigned Opcode);
583bool isVSUBPH(unsigned Opcode);
584bool isPMOVSXBW(unsigned Opcode);
585bool isVPSRLDQ(unsigned Opcode);
586bool isADC(unsigned Opcode);
587bool isPHADDD(unsigned Opcode);
588bool isVDPPHPS(unsigned Opcode);
589bool isVMINPH(unsigned Opcode);
590bool isVMINSD(unsigned Opcode);
591bool isVROUNDPD(unsigned Opcode);
592bool isVFCMADDCPH(unsigned Opcode);
593bool isINCSSPQ(unsigned Opcode);
594bool isVPUNPCKLDQ(unsigned Opcode);
595bool isVMINSH(unsigned Opcode);
596bool isINSERTQ(unsigned Opcode);
597bool isBLCI(unsigned Opcode);
598bool isHLT(unsigned Opcode);
599bool isVPCOMUW(unsigned Opcode);
600bool isVPMOVSXDQ(unsigned Opcode);
601bool isVFNMSUB231PS(unsigned Opcode);
602bool isVFNMSUB213SH(unsigned Opcode);
603bool isVCVTTPD2UQQ(unsigned Opcode);
604bool isSQRTSS(unsigned Opcode);
605bool isIMUL(unsigned Opcode);
606bool isVCVTSS2SI(unsigned Opcode);
607bool isPUSHAW(unsigned Opcode);
608bool isSTOSD(unsigned Opcode);
609bool isPSRLDQ(unsigned Opcode);
610bool isVSCATTERQPS(unsigned Opcode);
611bool isFIDIV(unsigned Opcode);
612bool isVFMSUB213PD(unsigned Opcode);
613bool isVCVTBF62HF8(unsigned Opcode);
614bool isVFMADDSUB231PH(unsigned Opcode);
615bool isTDCALL(unsigned Opcode);
616bool isPVALIDATE(unsigned Opcode);
617bool isVPSHUFLW(unsigned Opcode);
618bool isPCLMULQDQ(unsigned Opcode);
619bool isCMPXCHG8B(unsigned Opcode);
620bool isVPMOVM2B(unsigned Opcode);
621bool isVCVTUDQ2PH(unsigned Opcode);
622bool isPEXTRQ(unsigned Opcode);
623bool isXCRYPTCTR(unsigned Opcode);
624bool isVREDUCEPH(unsigned Opcode);
625bool isUCOMISD(unsigned Opcode);
626bool isOUTSD(unsigned Opcode);
627bool isSUBSS(unsigned Opcode);
628bool isVFMSUBPS(unsigned Opcode);
629bool isVPBLENDW(unsigned Opcode);
630bool isVPEXPANDB(unsigned Opcode);
631bool isBZHI(unsigned Opcode);
632bool isVPRORVD(unsigned Opcode);
633bool isRMPQUERY(unsigned Opcode);
634bool isVPSCATTERDQ(unsigned Opcode);
635bool isPSMASH(unsigned Opcode);
636bool isVPSHLDQ(unsigned Opcode);
637bool isVSCATTERPF1DPD(unsigned Opcode);
638bool isMONTMUL(unsigned Opcode);
639bool isVCVTPH2UQQ(unsigned Opcode);
640bool isPSLLD(unsigned Opcode);
641bool isSAR(unsigned Opcode);
642bool isLDTILECFG(unsigned Opcode);
643bool isPMINUB(unsigned Opcode);
644bool isVCVTNEEBF162PS(unsigned Opcode);
645bool isMOVDIR64B(unsigned Opcode);
646bool isSQRTPS(unsigned Opcode);
647bool isSTR(unsigned Opcode);
648bool isKANDNQ(unsigned Opcode);
649bool isBSF(unsigned Opcode);
650bool isINCSSPD(unsigned Opcode);
651bool isVPDPBUUDS(unsigned Opcode);
652bool isCMPXCHG(unsigned Opcode);
653bool isVPSIGNW(unsigned Opcode);
654bool isVCOMISBF16(unsigned Opcode);
655bool isLES(unsigned Opcode);
656bool isCVTSS2SI(unsigned Opcode);
657bool isPFACC(unsigned Opcode);
658bool isFCOMPI(unsigned Opcode);
659bool isPUNPCKHWD(unsigned Opcode);
660bool isVPMOVUSWB(unsigned Opcode);
661bool isVPTESTNMW(unsigned Opcode);
662bool isVPMULDQ(unsigned Opcode);
663bool isSHRX(unsigned Opcode);
664bool isKXORQ(unsigned Opcode);
665bool isVGETEXPSD(unsigned Opcode);
666bool isV4FNMADDPS(unsigned Opcode);
667bool isVFNMSUB231SD(unsigned Opcode);
668bool isVPSHLD(unsigned Opcode);
669bool isPAVGB(unsigned Opcode);
670bool isPMOVZXBD(unsigned Opcode);
671bool isKORTESTW(unsigned Opcode);
672bool isVSHUFPS(unsigned Opcode);
673bool isVCVTHF82PS(unsigned Opcode);
674bool isAESENCWIDE128KL(unsigned Opcode);
675bool isVPXORD(unsigned Opcode);
676bool isVPSHAW(unsigned Opcode);
677bool isVFMSUB132BF16(unsigned Opcode);
678bool isVPERMT2B(unsigned Opcode);
679bool isVFMADD213PD(unsigned Opcode);
680bool isVPGATHERQD(unsigned Opcode);
681bool isVFNMSUB213BF16(unsigned Opcode);
682bool isVCVTPS2IBS(unsigned Opcode);
683bool isVPCMPGTW(unsigned Opcode);
684bool isVMOVRSB(unsigned Opcode);
685bool isVGETMANTSH(unsigned Opcode);
686bool isVANDPS(unsigned Opcode);
687bool isVDIVPS(unsigned Opcode);
688bool isVANDNPS(unsigned Opcode);
689bool isVPBROADCASTW(unsigned Opcode);
690bool isFLDL2T(unsigned Opcode);
691bool isVPERMB(unsigned Opcode);
692bool isFCMOVNBE(unsigned Opcode);
693bool isVCVTTPH2W(unsigned Opcode);
694bool isPMOVZXBQ(unsigned Opcode);
695bool isPF2ID(unsigned Opcode);
696bool isVFNMADD132PD(unsigned Opcode);
697bool isPMULHRSW(unsigned Opcode);
698bool isKADDD(unsigned Opcode);
699bool isVFNMSUB132SH(unsigned Opcode);
700bool isUIRET(unsigned Opcode);
701bool isBSR(unsigned Opcode);
702bool isPCMPEQQ(unsigned Opcode);
703bool isCDQ(unsigned Opcode);
704bool isPMAXSW(unsigned Opcode);
705bool isSIDTD(unsigned Opcode);
706bool isVCVTPS2PHX(unsigned Opcode);
707bool isVPSLLVQ(unsigned Opcode);
708bool isMOVQ(unsigned Opcode);
709bool isPREFETCH(unsigned Opcode);
710bool isVCMPBF16(unsigned Opcode);
711bool isVBMACOR16X16X16(unsigned Opcode);
712bool isCLRSSBSY(unsigned Opcode);
713bool isTCVTROWPS2PHL(unsigned Opcode);
714bool isPSHUFW(unsigned Opcode);
715bool isVPDPWSUDS(unsigned Opcode);
716bool isVPMOVSXBQ(unsigned Opcode);
717bool isFICOMP(unsigned Opcode);
718bool isVFNMSUB132SS(unsigned Opcode);
719bool isVLDMXCSR(unsigned Opcode);
720bool isVPSUBUSW(unsigned Opcode);
721bool isRETF(unsigned Opcode);
722bool isKMOVQ(unsigned Opcode);
723bool isVPADDUSW(unsigned Opcode);
724bool isPACKSSDW(unsigned Opcode);
725bool isUMONITOR(unsigned Opcode);
726bool isENQCMDS(unsigned Opcode);
727bool isVCOMXSD(unsigned Opcode);
728bool isVPMAXSQ(unsigned Opcode);
729bool isVFMSUB213BF16(unsigned Opcode);
730bool isVPERMT2Q(unsigned Opcode);
731bool isFDECSTP(unsigned Opcode);
732bool isVPTESTMQ(unsigned Opcode);
733bool isVRCP14PD(unsigned Opcode);
734bool isARPL(unsigned Opcode);
735bool isVFMSUB213SD(unsigned Opcode);
736bool isJMPABS(unsigned Opcode);
737bool isVUNPCKHPS(unsigned Opcode);
738bool isVFNMADDSS(unsigned Opcode);
739bool isSIDT(unsigned Opcode);
740bool isVPCMPGTB(unsigned Opcode);
741bool isVPRORD(unsigned Opcode);
742bool isVSUBSS(unsigned Opcode);
743bool isPUSHFQ(unsigned Opcode);
744bool isVCVTHF82PH(unsigned Opcode);
745bool isVPCLMULQDQ(unsigned Opcode);
746bool isVPADDUSB(unsigned Opcode);
747bool isVPCMPD(unsigned Opcode);
748bool isMOVSD(unsigned Opcode);
749bool isPSUBUSW(unsigned Opcode);
750bool isVFMSUBADD132PS(unsigned Opcode);
751bool isMOVMSKPS(unsigned Opcode);
752bool isVFIXUPIMMSS(unsigned Opcode);
753bool isMFENCE(unsigned Opcode);
754bool isFTST(unsigned Opcode);
755bool isVPMADDWD(unsigned Opcode);
756bool isPOP(unsigned Opcode);
757bool isPSUBW(unsigned Opcode);
758bool isBSWAP(unsigned Opcode);
759bool isPFMIN(unsigned Opcode);
760bool isVFPCLASSPD(unsigned Opcode);
761bool isVPSHRDVD(unsigned Opcode);
762bool isPADDW(unsigned Opcode);
763bool isCVTSI2SD(unsigned Opcode);
764bool isENQCMD(unsigned Opcode);
765bool isXSHA1(unsigned Opcode);
766bool isVFNMADD132SD(unsigned Opcode);
767bool isMOVZX(unsigned Opcode);
768bool isVFIXUPIMMSD(unsigned Opcode);
769bool isINVD(unsigned Opcode);
770bool isVFIXUPIMMPS(unsigned Opcode);
771bool isMOVDQU(unsigned Opcode);
772bool isVFPCLASSPS(unsigned Opcode);
773bool isVPERMILPS(unsigned Opcode);
774bool isMOVSQ(unsigned Opcode);
775bool isAESDECWIDE128KL(unsigned Opcode);
776bool isROUNDSS(unsigned Opcode);
777bool isVPMOVW2M(unsigned Opcode);
778bool isVPSHUFB(unsigned Opcode);
779bool isVMULSD(unsigned Opcode);
780bool isVPERMI2W(unsigned Opcode);
781bool isVREDUCESS(unsigned Opcode);
782bool isFST(unsigned Opcode);
783bool isVPHSUBW(unsigned Opcode);
784bool isFRNDINT(unsigned Opcode);
785bool isSHR(unsigned Opcode);
786bool isLOOPNE(unsigned Opcode);
787bool isVCVTTPH2UQQ(unsigned Opcode);
788bool isSHA1NEXTE(unsigned Opcode);
789bool isVFMADD132SD(unsigned Opcode);
790bool isPSRAW(unsigned Opcode);
791bool isVPBROADCASTQ(unsigned Opcode);
792bool isCLC(unsigned Opcode);
793bool isPOPAW(unsigned Opcode);
794bool isTCMMIMFP16PS(unsigned Opcode);
795bool isVCVTQQ2PH(unsigned Opcode);
796bool isVCVTTPS2UQQ(unsigned Opcode);
797bool isVMOVUPD(unsigned Opcode);
798bool isFPTAN(unsigned Opcode);
799bool isVMASKMOVPD(unsigned Opcode);
800bool isVMOVLHPS(unsigned Opcode);
801bool isAESKEYGENASSIST(unsigned Opcode);
802bool isXSAVEOPT64(unsigned Opcode);
803bool isXSAVEC(unsigned Opcode);
804bool isVPLZCNTQ(unsigned Opcode);
805bool isVPSUBW(unsigned Opcode);
806bool isCMPCCXADD(unsigned Opcode);
807bool isVFMSUBADD213PH(unsigned Opcode);
808bool isVFMADDSUBPD(unsigned Opcode);
809bool isVPMINSW(unsigned Opcode);
810bool isVFNMSUB132PS(unsigned Opcode);
811bool isVMOVAPS(unsigned Opcode);
812bool isVPEXTRQ(unsigned Opcode);
813bool isVSCALEFSH(unsigned Opcode);
814bool isVCVTPD2PS(unsigned Opcode);
815bool isCLGI(unsigned Opcode);
816bool isVAESDEC(unsigned Opcode);
817bool isPFMUL(unsigned Opcode);
818bool isVCVTBIASPH2BF8S(unsigned Opcode);
819bool isMOVDIRI(unsigned Opcode);
820bool isSHUFPS(unsigned Opcode);
821bool isVFNMSUB231SS(unsigned Opcode);
822bool isVMWRITE(unsigned Opcode);
823bool isVINSERTF128(unsigned Opcode);
824bool isFISUBR(unsigned Opcode);
825bool isVINSERTI32X4(unsigned Opcode);
826bool isVPSLLDQ(unsigned Opcode);
827bool isPOPCNT(unsigned Opcode);
828bool isVXORPD(unsigned Opcode);
829bool isXLATB(unsigned Opcode);
830bool isDIV(unsigned Opcode);
831bool isVPSHLDVQ(unsigned Opcode);
832bool isMOVDDUP(unsigned Opcode);
833bool isVMOVDQU64(unsigned Opcode);
834bool isVPCOMPRESSQ(unsigned Opcode);
835bool isVFMSUBADD132PD(unsigned Opcode);
836bool isVPERMILPD(unsigned Opcode);
837bool isADDSD(unsigned Opcode);
838bool isBLENDPD(unsigned Opcode);
839bool isVPANDQ(unsigned Opcode);
840bool isPMADDUBSW(unsigned Opcode);
841bool isPOPFD(unsigned Opcode);
842bool isCMPSW(unsigned Opcode);
843bool isLDMXCSR(unsigned Opcode);
844bool isVMULPS(unsigned Opcode);
845bool isVROUNDSD(unsigned Opcode);
846bool isVFMADD132PD(unsigned Opcode);
847bool isVPSRAQ(unsigned Opcode);
848bool isVCOMISD(unsigned Opcode);
849bool isVCVTBIASPH2BF8(unsigned Opcode);
850bool isFFREEP(unsigned Opcode);
851bool isVFNMADD213PD(unsigned Opcode);
852bool isVCMPPD(unsigned Opcode);
853bool isVFNMSUB132PH(unsigned Opcode);
854bool isVPHADDBW(unsigned Opcode);
855bool isVPPERM(unsigned Opcode);
856bool isVCVTPS2PD(unsigned Opcode);
857bool isCBW(unsigned Opcode);
858bool isVMOVUPS(unsigned Opcode);
859bool isVPMAXUQ(unsigned Opcode);
860bool isWRSSQ(unsigned Opcode);
861bool isPACKUSDW(unsigned Opcode);
862bool isVCVTTBF162IBS(unsigned Opcode);
863bool isXBEGIN(unsigned Opcode);
864bool isVCVTPD2UQQ(unsigned Opcode);
865bool isFCMOVB(unsigned Opcode);
866bool isNOP(unsigned Opcode);
867bool isVPABSQ(unsigned Opcode);
868bool isVTESTPS(unsigned Opcode);
869bool isPHSUBW(unsigned Opcode);
870bool isPUSH2P(unsigned Opcode);
871bool isFISTTP(unsigned Opcode);
872bool isCFCMOVCC(unsigned Opcode);
873bool isPCMPESTRM(unsigned Opcode);
874bool isVPINSRD(unsigned Opcode);
875bool isVFNMSUB213PS(unsigned Opcode);
876bool isPHSUBD(unsigned Opcode);
877bool isSLDT(unsigned Opcode);
878bool isVCVTTPD2DQS(unsigned Opcode);
879bool isVPMINSD(unsigned Opcode);
880bool isVHADDPS(unsigned Opcode);
881bool isVMOVNTDQ(unsigned Opcode);
882bool isVFRCZSD(unsigned Opcode);
883bool isIBHF(unsigned Opcode);
884bool isVPTESTMW(unsigned Opcode);
885bool isVPMOVZXWD(unsigned Opcode);
886bool isPSADBW(unsigned Opcode);
887bool isVCVTSD2SI(unsigned Opcode);
888bool isVMAXPH(unsigned Opcode);
889bool isLODSB(unsigned Opcode);
890bool isPHMINPOSUW(unsigned Opcode);
891bool isVPROLVD(unsigned Opcode);
892bool isWRFSBASE(unsigned Opcode);
893bool isVRSQRT14PS(unsigned Opcode);
894bool isVPHSUBDQ(unsigned Opcode);
895bool isIRETD(unsigned Opcode);
896bool isVMOVRSD(unsigned Opcode);
897bool isVPMULHRSW(unsigned Opcode);
898bool isCVTSI2SS(unsigned Opcode);
899bool isPI2FD(unsigned Opcode);
900bool isGF2P8AFFINEQB(unsigned Opcode);
901bool isPAND(unsigned Opcode);
902bool isVFNMSUB231SH(unsigned Opcode);
903bool isVMOVHLPS(unsigned Opcode);
904bool isKNOTD(unsigned Opcode);
905bool isPEXTRB(unsigned Opcode);
906bool isVCVTPH2BF8(unsigned Opcode);
907bool isVMMCALL(unsigned Opcode);
908bool isVCVTSH2SS(unsigned Opcode);
909bool isVPUNPCKLQDQ(unsigned Opcode);
910bool isVPERMIL2PS(unsigned Opcode);
911bool isVPCMPGTD(unsigned Opcode);
912bool isCMPXCHG16B(unsigned Opcode);
913bool isTDPHF8PS(unsigned Opcode);
914bool isVZEROUPPER(unsigned Opcode);
915bool isMOVAPS(unsigned Opcode);
916bool isRMPOPT(unsigned Opcode);
917bool isFUCOMPP(unsigned Opcode);
918bool isVPCMPW(unsigned Opcode);
919bool isXSETBV(unsigned Opcode);
920bool isSLWPCB(unsigned Opcode);
921bool isSCASW(unsigned Opcode);
922bool isFCMOVNE(unsigned Opcode);
923bool isPBNDKB(unsigned Opcode);
924bool isVPMULLD(unsigned Opcode);
925bool isVP4DPWSSDS(unsigned Opcode);
926bool isVCVT2PH2HF8(unsigned Opcode);
927bool isPINSRW(unsigned Opcode);
928bool isVCVTSI2SH(unsigned Opcode);
929bool isVINSERTF32X8(unsigned Opcode);
930bool isKSHIFTLB(unsigned Opcode);
931bool isSEAMOPS(unsigned Opcode);
932bool isVPMOVSQB(unsigned Opcode);
933bool isVPMULUDQ(unsigned Opcode);
934bool isVPTESTMD(unsigned Opcode);
935bool isVPHADDDQ(unsigned Opcode);
936bool isKUNPCKDQ(unsigned Opcode);
937bool isT1MSKC(unsigned Opcode);
938bool isVBLENDPS(unsigned Opcode);
939bool isVPCOMB(unsigned Opcode);
940bool isPTWRITE(unsigned Opcode);
941bool isVCVTPH2BF8S(unsigned Opcode);
942bool isCVTPS2PI(unsigned Opcode);
943bool isVPROTD(unsigned Opcode);
944bool isCALL(unsigned Opcode);
945bool isTILELOADDRST1(unsigned Opcode);
946bool isVPERMPS(unsigned Opcode);
947bool isVPSHUFBITQMB(unsigned Opcode);
948bool isVMOVSLDUP(unsigned Opcode);
949bool isINVLPGA(unsigned Opcode);
950bool isVCVTPH2QQ(unsigned Opcode);
951bool isADD(unsigned Opcode);
952bool isPSUBSW(unsigned Opcode);
953bool isSIDTW(unsigned Opcode);
954bool isVEXTRACTF64X2(unsigned Opcode);
955bool isVFNMADD231PH(unsigned Opcode);
956bool isFCOMI(unsigned Opcode);
957bool isRSM(unsigned Opcode);
958bool isVPCOMUD(unsigned Opcode);
959bool isVPMOVZXBQ(unsigned Opcode);
960bool isUWRMSR(unsigned Opcode);
961bool isLGS(unsigned Opcode);
962bool isVMOVNTPD(unsigned Opcode);
963bool isPCMPESTRMQ(unsigned Opcode);
964bool isRDPRU(unsigned Opcode);
965bool isVPUNPCKHBW(unsigned Opcode);
966bool isVUCOMXSD(unsigned Opcode);
967bool isANDN(unsigned Opcode);
968bool isVCVTTPH2UW(unsigned Opcode);
969bool isVMFUNC(unsigned Opcode);
970bool isFIMUL(unsigned Opcode);
971bool isBLCFILL(unsigned Opcode);
972bool isVGATHERPF0DPS(unsigned Opcode);
973bool isVCVTHF82BF4S(unsigned Opcode);
974bool isVFMSUBADD231PS(unsigned Opcode);
975bool isVREDUCESD(unsigned Opcode);
976bool isVCOMXSH(unsigned Opcode);
977bool isVXORPS(unsigned Opcode);
978bool isPSWAPD(unsigned Opcode);
979bool isPMAXSD(unsigned Opcode);
980bool isVCMPSS(unsigned Opcode);
981bool isEXTRACTPS(unsigned Opcode);
982bool isVPMOVZXBD(unsigned Opcode);
983bool isOUTSW(unsigned Opcode);
984bool isKORTESTB(unsigned Opcode);
985bool isVREDUCEPS(unsigned Opcode);
986bool isPEXTRW(unsigned Opcode);
987bool isFNINIT(unsigned Opcode);
988bool isVCVTPH2IBS(unsigned Opcode);
989bool isROL(unsigned Opcode);
990bool isVCVTPS2QQ(unsigned Opcode);
991bool isVGETMANTPH(unsigned Opcode);
992bool isPUNPCKLDQ(unsigned Opcode);
993bool isPADDD(unsigned Opcode);
994bool isVPSLLD(unsigned Opcode);
995bool isPFCMPGE(unsigned Opcode);
996bool isVGETMANTBF16(unsigned Opcode);
997bool isVSUBBF16(unsigned Opcode);
998bool isVPMOVM2D(unsigned Opcode);
999bool isVCVTTSS2USIS(unsigned Opcode);
1000bool isVHSUBPS(unsigned Opcode);
1001bool isENDBR32(unsigned Opcode);
1002bool isMOVSXD(unsigned Opcode);
1003bool isPSIGND(unsigned Opcode);
1004bool isVPTEST(unsigned Opcode);
1005bool isVPDPWUSD(unsigned Opcode);
1006bool isHSUBPD(unsigned Opcode);
1007bool isADCX(unsigned Opcode);
1008bool isCVTTPD2PI(unsigned Opcode);
1009bool isPDEP(unsigned Opcode);
1010bool isTDPBUSD(unsigned Opcode);
1011bool isVCVTBIASPH2HF8S(unsigned Opcode);
1012bool isVBROADCASTI32X4(unsigned Opcode);
1013bool isVCVTPH2UDQ(unsigned Opcode);
1014bool isVPHADDW(unsigned Opcode);
1015bool isFLDL2E(unsigned Opcode);
1016bool isCLZERO(unsigned Opcode);
1017bool isPBLENDW(unsigned Opcode);
1018bool isVCVTBF162IUBS(unsigned Opcode);
1019bool isVCVTSH2USI(unsigned Opcode);
1020bool isVANDPD(unsigned Opcode);
1021bool isBEXTR(unsigned Opcode);
1022bool isSTD(unsigned Opcode);
1023bool isVAESKEYGENASSIST(unsigned Opcode);
1024bool isCMPSD(unsigned Opcode);
1025bool isMOVSS(unsigned Opcode);
1026bool isVCVTUQQ2PD(unsigned Opcode);
1027bool isVEXTRACTI32X4(unsigned Opcode);
1028bool isFLDCW(unsigned Opcode);
1029bool isINSW(unsigned Opcode);
1030bool isRDPID(unsigned Opcode);
1031bool isVUCOMXSS(unsigned Opcode);
1032bool isKANDQ(unsigned Opcode);
1033bool isV4FMADDPS(unsigned Opcode);
1034bool isPMOVZXWQ(unsigned Opcode);
1035bool isVFPCLASSSD(unsigned Opcode);
1036bool isBLENDPS(unsigned Opcode);
1037bool isVPACKSSDW(unsigned Opcode);
1038bool isVPHSUBBW(unsigned Opcode);
1039bool isVPINSRW(unsigned Opcode);
1040bool isVMINMAXBF16(unsigned Opcode);
1041bool isVSHUFF64X2(unsigned Opcode);
1042bool isVPACKUSWB(unsigned Opcode);
1043bool isVRSQRT28SS(unsigned Opcode);
1044bool isGETSEC(unsigned Opcode);
1045bool isFXAM(unsigned Opcode);
1046bool isVEXTRACTF64X4(unsigned Opcode);
1047bool isBLSR(unsigned Opcode);
1048bool isFILD(unsigned Opcode);
1049bool isRETFQ(unsigned Opcode);
1050bool isVADDSS(unsigned Opcode);
1051bool isCOMISS(unsigned Opcode);
1052bool isCLI(unsigned Opcode);
1053bool isVERW(unsigned Opcode);
1054bool isBTC(unsigned Opcode);
1055bool isVPHADDUBQ(unsigned Opcode);
1056bool isVPORQ(unsigned Opcode);
1057bool isORPD(unsigned Opcode);
1058bool isVMOVSS(unsigned Opcode);
1059bool isVPSUBD(unsigned Opcode);
1060bool isVGATHERPF1QPD(unsigned Opcode);
1061bool isENCODEKEY256(unsigned Opcode);
1062bool isGF2P8AFFINEINVQB(unsigned Opcode);
1063bool isXRSTOR64(unsigned Opcode);
1064bool isKANDW(unsigned Opcode);
1065bool isLODSQ(unsigned Opcode);
1066bool isVMOVRSW(unsigned Opcode);
1067bool isVSUBSH(unsigned Opcode);
1068bool isLSS(unsigned Opcode);
1069bool isPMOVSXBQ(unsigned Opcode);
1070bool isVCVTTSD2SIS(unsigned Opcode);
1071bool isVCMPSH(unsigned Opcode);
1072bool isVFMADD132PS(unsigned Opcode);
1073bool isVPACKSSWB(unsigned Opcode);
1074bool isPCMPGTQ(unsigned Opcode);
1075bool isVFMADD132SH(unsigned Opcode);
1076bool isVCVTUQQ2PH(unsigned Opcode);
1077bool isVCVTQQ2PS(unsigned Opcode);
1078bool isVCVTTSS2USI(unsigned Opcode);
1079bool isVPMOVM2Q(unsigned Opcode);
1080bool isVMOVD(unsigned Opcode);
1081bool isVCVTTPS2QQS(unsigned Opcode);
1082bool isVSQRTBF16(unsigned Opcode);
1083bool isVFPCLASSPH(unsigned Opcode);
1084bool isVCVTSS2SH(unsigned Opcode);
1085bool isSCASB(unsigned Opcode);
1086bool isPSRLD(unsigned Opcode);
1087bool isVADDPH(unsigned Opcode);
1088bool isFSUB(unsigned Opcode);
1089bool isVCVTTPH2IBS(unsigned Opcode);
1090bool isVEXTRACTI64X2(unsigned Opcode);
1091bool isVPSHLDD(unsigned Opcode);
1092bool isPMINUW(unsigned Opcode);
1093bool isPSUBSB(unsigned Opcode);
1094bool isVCVT2PS2PHX(unsigned Opcode);
1095bool isVPCMPEQD(unsigned Opcode);
1096bool isVPSCATTERQD(unsigned Opcode);
1097bool isKXNORB(unsigned Opcode);
1098bool isLDDQU(unsigned Opcode);
1099bool isMASKMOVQ(unsigned Opcode);
1100bool isPABSW(unsigned Opcode);
1101bool isVPCOMQ(unsigned Opcode);
1102bool isVPROLD(unsigned Opcode);
1103bool isVSCATTERDPD(unsigned Opcode);
1104bool isFXRSTOR(unsigned Opcode);
1105bool isVPCMPUW(unsigned Opcode);
1106bool isWBINVD(unsigned Opcode);
1107bool isVCVTTPD2UDQ(unsigned Opcode);
1108bool isERETU(unsigned Opcode);
1109bool isPFRCPIT2(unsigned Opcode);
1110bool isVPERMT2W(unsigned Opcode);
1111bool isVEXTRACTF32X4(unsigned Opcode);
1112bool isVGATHERPF0DPD(unsigned Opcode);
1113bool isVBROADCASTF32X2(unsigned Opcode);
1114bool isVRCP14SD(unsigned Opcode);
1115bool isLAHF(unsigned Opcode);
1116bool isPABSD(unsigned Opcode);
1117bool isPINSRB(unsigned Opcode);
1118bool isSKINIT(unsigned Opcode);
1119bool isENTER(unsigned Opcode);
1120bool isVCVTSI2SS(unsigned Opcode);
1121bool isVFMADD231PD(unsigned Opcode);
1122bool isLOADIWKEY(unsigned Opcode);
1123bool isVMOVNTDQA(unsigned Opcode);
1124bool isVPERMT2PS(unsigned Opcode);
1125bool isPUSHF(unsigned Opcode);
1126bool isMPSADBW(unsigned Opcode);
1127bool isVCVTBIASPS2BF8S(unsigned Opcode);
1128bool isVMINMAXSH(unsigned Opcode);
1129bool isVRSQRT14SS(unsigned Opcode);
1130bool isVCVTDQ2PD(unsigned Opcode);
1131bool isVORPS(unsigned Opcode);
1132bool isVPEXPANDQ(unsigned Opcode);
1133bool isVPSHRDD(unsigned Opcode);
1134bool isTDPBSSD(unsigned Opcode);
1135bool isTESTUI(unsigned Opcode);
1136bool isVCVTBF42HF8(unsigned Opcode);
1137bool isVFMADDPD(unsigned Opcode);
1138bool isVPANDND(unsigned Opcode);
1139bool isVPMOVSDB(unsigned Opcode);
1140bool isVPBROADCASTB(unsigned Opcode);
1141bool isCVTPI2PD(unsigned Opcode);
1142bool isVPERMI2B(unsigned Opcode);
1143bool isVPMINSB(unsigned Opcode);
1144bool isLAR(unsigned Opcode);
1145bool isINVLPGB(unsigned Opcode);
1146bool isTLBSYNC(unsigned Opcode);
1147bool isFDIVP(unsigned Opcode);
1148bool isVPSRLW(unsigned Opcode);
1149bool isVRCP28SS(unsigned Opcode);
1150bool isVMOVHPS(unsigned Opcode);
1151bool isVPMACSSDD(unsigned Opcode);
1152bool isPEXT(unsigned Opcode);
1153bool isVMAXBF16(unsigned Opcode);
1154bool isVRSQRT14SD(unsigned Opcode);
1155bool isVPDPWSSD(unsigned Opcode);
1156bool isVFMSUB231SD(unsigned Opcode);
1157bool isVPMOVZXWQ(unsigned Opcode);
1158bool isXORPD(unsigned Opcode);
1159bool isVMOVDQA(unsigned Opcode);
1160bool isVFNMSUB213SD(unsigned Opcode);
1161bool isVMINPS(unsigned Opcode);
1162bool isVFMSUB231PS(unsigned Opcode);
1163bool isVPCOMPRESSB(unsigned Opcode);
1164bool isVCVTPS2HF8(unsigned Opcode);
1165bool isVPCMPEQQ(unsigned Opcode);
1166bool isVRCPSS(unsigned Opcode);
1167bool isVSCATTERPF1DPS(unsigned Opcode);
1168bool isVPHADDUBW(unsigned Opcode);
1169bool isVSUBPD(unsigned Opcode);
1170bool isVPSCATTERQQ(unsigned Opcode);
1171bool isVCVTW2PH(unsigned Opcode);
1172bool isVFMADDCPH(unsigned Opcode);
1173bool isVPACKUSDW(unsigned Opcode);
1174bool isVSCALEFSS(unsigned Opcode);
1175bool isAESIMC(unsigned Opcode);
1176bool isVRCP28PS(unsigned Opcode);
1177bool isAAND(unsigned Opcode);
1178bool isDAA(unsigned Opcode);
1179bool isKTESTW(unsigned Opcode);
1180bool isVCVTPD2UDQ(unsigned Opcode);
1181bool isVPADDQ(unsigned Opcode);
1182bool isPALIGNR(unsigned Opcode);
1183bool isPMAXUW(unsigned Opcode);
1184bool isVFMADDSD(unsigned Opcode);
1185bool isPFMAX(unsigned Opcode);
1186bool isVPOR(unsigned Opcode);
1187bool isVPSUBB(unsigned Opcode);
1188bool isVPAVGB(unsigned Opcode);
1189bool isINSB(unsigned Opcode);
1190bool isFYL2X(unsigned Opcode);
1191bool isVFNMSUB132PD(unsigned Opcode);
1192bool isVFNMSUBPS(unsigned Opcode);
1193bool isVFMADD231PS(unsigned Opcode);
1194bool isVCVTTSS2SI(unsigned Opcode);
1195bool isTCMMRLFP16PS(unsigned Opcode);
1196bool isFCOMPP(unsigned Opcode);
1197bool isMOVD(unsigned Opcode);
1198bool isMOVBE(unsigned Opcode);
1199bool isVP2INTERSECTD(unsigned Opcode);
1200bool isVPMULLQ(unsigned Opcode);
1201bool isVSCALEFPS(unsigned Opcode);
1202bool isVPMACSDQH(unsigned Opcode);
1203bool isVPTESTNMD(unsigned Opcode);
1204bool isFCOMP(unsigned Opcode);
1205bool isPREFETCHWT1(unsigned Opcode);
1206bool isVCMPSD(unsigned Opcode);
1207bool isSGDTD(unsigned Opcode);
1208bool isWRUSSD(unsigned Opcode);
1209bool isFSUBP(unsigned Opcode);
1210bool isVUNPCKLPS(unsigned Opcode);
1211bool isVBMACXOR16X16X16(unsigned Opcode);
1212bool isVFNMSUB213SS(unsigned Opcode);
1213bool isROUNDPD(unsigned Opcode);
1214bool isVPMAXSW(unsigned Opcode);
1215bool isVCVTTPH2DQ(unsigned Opcode);
1216bool isVPUNPCKLWD(unsigned Opcode);
1217bool isKSHIFTLD(unsigned Opcode);
1218bool isTCVTROWPS2BF16H(unsigned Opcode);
1219bool isVFMADD231SD(unsigned Opcode);
1220bool isADDPS(unsigned Opcode);
1221bool isVPSLLVD(unsigned Opcode);
1222bool isVFNMADD132SH(unsigned Opcode);
1223bool isVMOVNTPS(unsigned Opcode);
1224bool isVCVTBF82BF4S(unsigned Opcode);
1225bool isVCVTPD2DQ(unsigned Opcode);
1226bool isVPXOR(unsigned Opcode);
1227bool isSTMXCSR(unsigned Opcode);
1228bool isVRCP14SS(unsigned Opcode);
1229bool isUD2(unsigned Opcode);
1230bool isVPOPCNTW(unsigned Opcode);
1231bool isVRSQRTSH(unsigned Opcode);
1232bool isVSCATTERPF0DPD(unsigned Opcode);
1233bool isVFMADDPS(unsigned Opcode);
1234bool isXSAVEC64(unsigned Opcode);
1235bool isVPMADDUBSW(unsigned Opcode);
1236bool isVPMOVZXDQ(unsigned Opcode);
1237bool isVRCP14PS(unsigned Opcode);
1238bool isVSQRTSH(unsigned Opcode);
1239bool isTCVTROWD2PS(unsigned Opcode);
1240bool isLOOP(unsigned Opcode);
1241bool isSTUI(unsigned Opcode);
1242bool isVCVTTPS2UDQ(unsigned Opcode);
1243bool isXABORT(unsigned Opcode);
1244bool isVCOMPRESSPS(unsigned Opcode);
1245bool isVCVTPS2BF8S(unsigned Opcode);
1246bool isVCVTTBF162IUBS(unsigned Opcode);
1247bool isVPADDW(unsigned Opcode);
1248bool isVPSIGND(unsigned Opcode);
1249bool isVRNDSCALEPS(unsigned Opcode);
1250bool isVPHADDUWD(unsigned Opcode);
1251bool isVCVT2PH2HF8S(unsigned Opcode);
1252bool isVDBPSADBW(unsigned Opcode);
1253bool isPSLLW(unsigned Opcode);
1254bool isVPMOVQD(unsigned Opcode);
1255bool isVINSERTI64X4(unsigned Opcode);
1256bool isVPERMI2PS(unsigned Opcode);
1257bool isVMULPH(unsigned Opcode);
1258bool isVPCMPUQ(unsigned Opcode);
1259bool isVCVTUSI2SD(unsigned Opcode);
1260bool isKXNORW(unsigned Opcode);
1261bool isBLCIC(unsigned Opcode);
1262bool isVFNMADD213SD(unsigned Opcode);
1263bool isVMOVLPS(unsigned Opcode);
1264bool isVPMACSWW(unsigned Opcode);
1265bool isPCONFIG(unsigned Opcode);
1266bool isPANDN(unsigned Opcode);
1267bool isVCVTPS2BF8(unsigned Opcode);
1268bool isVGETEXPPD(unsigned Opcode);
1269bool isVPSRLVQ(unsigned Opcode);
1270bool isUD1(unsigned Opcode);
1271bool isPMAXSB(unsigned Opcode);
1272bool isVPROLQ(unsigned Opcode);
1273bool isVPSRLD(unsigned Opcode);
1274bool isVSCATTERPF1QPD(unsigned Opcode);
1275bool isINT3(unsigned Opcode);
1276bool isXRSTORS64(unsigned Opcode);
1277bool isCVTSD2SI(unsigned Opcode);
1278bool isVMAXSS(unsigned Opcode);
1279bool isVPMINUB(unsigned Opcode);
1280bool isKXNORQ(unsigned Opcode);
1281bool isFLD(unsigned Opcode);
1282bool isVSHUFI32X4(unsigned Opcode);
1283bool isSAHF(unsigned Opcode);
1284bool isPFRSQRT(unsigned Opcode);
1285bool isSHRD(unsigned Opcode);
1286bool isSYSEXIT(unsigned Opcode);
1287bool isXSAVE64(unsigned Opcode);
1288bool isVPMAXSD(unsigned Opcode);
1289bool isCVTTSD2SI(unsigned Opcode);
1290bool isVCVTTSS2SIS(unsigned Opcode);
1291bool isPMOVMSKB(unsigned Opcode);
1292bool isVPMOVSSDB(unsigned Opcode);
1293bool isVRANGEPS(unsigned Opcode);
1294bool isVADDSUBPS(unsigned Opcode);
1295bool isVBROADCASTI128(unsigned Opcode);
1296bool isPADDUSB(unsigned Opcode);
1297bool isENCODEKEY128(unsigned Opcode);
1298bool isOR(unsigned Opcode);
1299bool isSTOSW(unsigned Opcode);
1300bool isVCVTTPD2UQQS(unsigned Opcode);
1301bool isPAVGW(unsigned Opcode);
1302bool isVCVTPD2PH(unsigned Opcode);
1303bool isSHLX(unsigned Opcode);
1304bool isVCVTSH2SD(unsigned Opcode);
1305bool isVFMADD231SS(unsigned Opcode);
1306bool isMOVNTSD(unsigned Opcode);
1307bool isFLDPI(unsigned Opcode);
1308bool isVCVTUSI2SS(unsigned Opcode);
1309bool isPMOVSXBD(unsigned Opcode);
1310bool isVPRORVQ(unsigned Opcode);
1311bool isVPERMT2D(unsigned Opcode);
1312bool isADDSS(unsigned Opcode);
1313bool isAADD(unsigned Opcode);
1314bool isVPSRLVW(unsigned Opcode);
1315bool isVRSQRTPH(unsigned Opcode);
1316bool isVLDDQU(unsigned Opcode);
1317bool isKMOVD(unsigned Opcode);
1318bool isENCLV(unsigned Opcode);
1319bool isENCLU(unsigned Opcode);
1320bool isPREFETCHT1(unsigned Opcode);
1321bool isRSQRTPS(unsigned Opcode);
1322bool isVCVTTSH2USI(unsigned Opcode);
1323bool isPADDB(unsigned Opcode);
1324bool isVMASKMOVDQU(unsigned Opcode);
1325bool isPUNPCKLBW(unsigned Opcode);
1326bool isMOV(unsigned Opcode);
1327bool isVCVTTPH2IUBS(unsigned Opcode);
1328bool isMUL(unsigned Opcode);
1329bool isRCL(unsigned Opcode);
1330bool isVRCPSH(unsigned Opcode);
1331bool isPFCMPEQ(unsigned Opcode);
1332bool isMONITOR(unsigned Opcode);
1333bool isFDIVR(unsigned Opcode);
1334bool isPFRCP(unsigned Opcode);
1335bool isPMINSD(unsigned Opcode);
1336bool isVSHUFF32X4(unsigned Opcode);
1337bool isKTESTQ(unsigned Opcode);
1338bool isVCVTTPD2DQ(unsigned Opcode);
1339bool isVPSLLVW(unsigned Opcode);
1340bool isTDPBSUD(unsigned Opcode);
1341bool isVPMINUQ(unsigned Opcode);
1342bool isFIADD(unsigned Opcode);
1343bool isFCMOVNU(unsigned Opcode);
1344bool isVHSUBPD(unsigned Opcode);
1345bool isKSHIFTRQ(unsigned Opcode);
1346bool isMOVUPS(unsigned Opcode);
1347bool isVMCALL(unsigned Opcode);
1348bool isXADD(unsigned Opcode);
1349bool isXRSTOR(unsigned Opcode);
1350bool isVGATHERPF1DPD(unsigned Opcode);
1351bool isRCR(unsigned Opcode);
1352bool isFNSTCW(unsigned Opcode);
1353bool isVPMOVSDW(unsigned Opcode);
1354bool isVFMSUB132SH(unsigned Opcode);
1355bool isVPCONFLICTQ(unsigned Opcode);
1356bool isSWAPGS(unsigned Opcode);
1357bool isVPMOVQ2M(unsigned Opcode);
1358bool isVPSRAVW(unsigned Opcode);
1359bool isSHA256MSG2(unsigned Opcode);
1360bool isDIVSD(unsigned Opcode);
1361bool isPCMPGTB(unsigned Opcode);
1362bool isMOVDQA(unsigned Opcode);
1363bool isVAESENCLAST(unsigned Opcode);
1364bool isKXORW(unsigned Opcode);
1365bool isLIDTW(unsigned Opcode);
1366bool isPMULHW(unsigned Opcode);
1367bool isVINSERTI32X8(unsigned Opcode);
1368bool isVRCPPS(unsigned Opcode);
1369bool isVRSQRTBF16(unsigned Opcode);
1370bool isVGATHERQPS(unsigned Opcode);
1371bool isCTESTCC(unsigned Opcode);
1372bool isPMADDWD(unsigned Opcode);
1373bool isUCOMISS(unsigned Opcode);
1374bool isXGETBV(unsigned Opcode);
1375bool isVCVTPD2QQ(unsigned Opcode);
1376bool isVGETEXPPS(unsigned Opcode);
1377bool isFISTP(unsigned Opcode);
1378bool isVINSERTF64X4(unsigned Opcode);
1379bool isVMOVDQU16(unsigned Opcode);
1380bool isVCVTBF82BF6S(unsigned Opcode);
1381bool isVFMADD132PH(unsigned Opcode);
1382bool isVFMSUBADD213PS(unsigned Opcode);
1383bool isVMOVDQU32(unsigned Opcode);
1384bool isFUCOM(unsigned Opcode);
1385bool isVFNMADD213BF16(unsigned Opcode);
1386bool isHADDPS(unsigned Opcode);
1387bool isCMP(unsigned Opcode);
1388bool isCVTTPS2PI(unsigned Opcode);
1389bool isIRETQ(unsigned Opcode);
1390bool isPF2IW(unsigned Opcode);
1391bool isPSHUFD(unsigned Opcode);
1392bool isVDPPD(unsigned Opcode);
1393bool isPSHUFHW(unsigned Opcode);
1394bool isRMPADJUST(unsigned Opcode);
1395bool isPI2FW(unsigned Opcode);
1396bool isVCVTTPH2QQ(unsigned Opcode);
1397bool isDIVPD(unsigned Opcode);
1398bool isCLFLUSH(unsigned Opcode);
1399bool isVPMINUW(unsigned Opcode);
1400bool isIN(unsigned Opcode);
1401bool isWRPKRU(unsigned Opcode);
1402bool isINSERTPS(unsigned Opcode);
1403bool isAAM(unsigned Opcode);
1404bool isVPHADDUDQ(unsigned Opcode);
1405bool isVSHA512MSG1(unsigned Opcode);
1406bool isDIVPS(unsigned Opcode);
1407bool isKNOTB(unsigned Opcode);
1408bool isBLSFILL(unsigned Opcode);
1409bool isVPCMPGTQ(unsigned Opcode);
1410bool isMINSD(unsigned Opcode);
1411bool isFPREM(unsigned Opcode);
1412bool isVPUNPCKHQDQ(unsigned Opcode);
1413bool isMINPD(unsigned Opcode);
1414bool isVCVTTPD2QQ(unsigned Opcode);
1415bool isVFMSUBPD(unsigned Opcode);
1416bool isV4FMADDSS(unsigned Opcode);
1417bool isCPUID(unsigned Opcode);
1418bool isSETCC(unsigned Opcode);
1419bool isVPDPWUUD(unsigned Opcode);
1420bool isVCVTTPS2IUBS(unsigned Opcode);
1421bool isPMOVSXDQ(unsigned Opcode);
1422bool isMWAIT(unsigned Opcode);
1423bool isVPEXTRB(unsigned Opcode);
1424bool isRMPCHKD(unsigned Opcode);
1425bool isINVVPID(unsigned Opcode);
1426bool isVPSHUFD(unsigned Opcode);
1427bool isVMINBF16(unsigned Opcode);
1428bool isMOVLPS(unsigned Opcode);
1429bool isVBLENDMPS(unsigned Opcode);
1430bool isPMULLW(unsigned Opcode);
1431bool isVCVTSH2SI(unsigned Opcode);
1432bool isVPMOVSXWQ(unsigned Opcode);
1433bool isFNSTENV(unsigned Opcode);
1434bool isVCVT2PH2BF8(unsigned Opcode);
1435bool isVPERMI2PD(unsigned Opcode);
1436bool isMAXSS(unsigned Opcode);
1437bool isCWDE(unsigned Opcode);
1438bool isVBROADCASTI32X8(unsigned Opcode);
1439bool isINT(unsigned Opcode);
1440bool isENCLS(unsigned Opcode);
1441bool isMOVNTQ(unsigned Opcode);
1442bool isVDIVSH(unsigned Opcode);
1443bool isMOVHLPS(unsigned Opcode);
1444bool isVPMASKMOVD(unsigned Opcode);
1445bool isVMOVSD(unsigned Opcode);
1446bool isVPMINUD(unsigned Opcode);
1447bool isVPCMPISTRM(unsigned Opcode);
1448bool isVGETMANTSD(unsigned Opcode);
1449bool isKSHIFTRW(unsigned Opcode);
1450bool isAESDECLAST(unsigned Opcode);
1451bool isVPTESTMB(unsigned Opcode);
1452bool isVFNMSUB231BF16(unsigned Opcode);
1453bool isVMPTRST(unsigned Opcode);
1454bool isLLDT(unsigned Opcode);
1455bool isVUNPACKB(unsigned Opcode);
1456bool isMOVSB(unsigned Opcode);
1457bool isTILELOADD(unsigned Opcode);
1458bool isKTESTB(unsigned Opcode);
1459bool isMOVUPD(unsigned Opcode);
1460bool isLKGS(unsigned Opcode);
1461bool isSGDTW(unsigned Opcode);
1462bool isDIVSS(unsigned Opcode);
1463bool isPUNPCKHQDQ(unsigned Opcode);
1464bool isVFMADD213SD(unsigned Opcode);
1465bool isKXORD(unsigned Opcode);
1466bool isVPMOVB2M(unsigned Opcode);
1467bool isVMREAD(unsigned Opcode);
1468bool isVPDPWSSDS(unsigned Opcode);
1469bool isTILERELEASE(unsigned Opcode);
1470bool isVUCOMXSH(unsigned Opcode);
1471bool isCLFLUSHOPT(unsigned Opcode);
1472bool isDAS(unsigned Opcode);
1473bool isVSCALEFPH(unsigned Opcode);
1474bool isVSUBSD(unsigned Opcode);
1475bool isVCVTROPS2HF8(unsigned Opcode);
1476bool isVCOMISS(unsigned Opcode);
1477bool isVMULBF16(unsigned Opcode);
1478bool isORPS(unsigned Opcode);
1479bool isTDPFP16PS(unsigned Opcode);
1480bool isVMAXPD(unsigned Opcode);
1481bool isVPMOVWB(unsigned Opcode);
1482bool isVEXP2PS(unsigned Opcode);
1483bool isVPGATHERDQ(unsigned Opcode);
1484bool isVPSRAVQ(unsigned Opcode);
1485bool isPCMPISTRI(unsigned Opcode);
1486bool isVFMSUB231PD(unsigned Opcode);
1487bool isRDMSR(unsigned Opcode);
1488bool isKORTESTD(unsigned Opcode);
1489bool isVPBLENDMW(unsigned Opcode);
1490bool isPSHUFB(unsigned Opcode);
1491bool isVDPBF16PS(unsigned Opcode);
1492bool isTDPBF16PS(unsigned Opcode);
1493bool isFCMOVE(unsigned Opcode);
1494bool isVFMADD231BF16(unsigned Opcode);
1495bool isCMPSS(unsigned Opcode);
1496bool isMASKMOVDQU(unsigned Opcode);
1497bool isSARX(unsigned Opcode);
1498bool isVPDPWUSDS(unsigned Opcode);
1499bool isSGDT(unsigned Opcode);
1500bool isVFMULCPH(unsigned Opcode);
1501bool isURDMSR(unsigned Opcode);
1502bool isKUNPCKWD(unsigned Opcode);
1503bool isVSCALEFBF16(unsigned Opcode);
1504bool isCVTPS2PD(unsigned Opcode);
1505bool isFBSTP(unsigned Opcode);
1506bool isPSUBQ(unsigned Opcode);
1507bool isFXSAVE64(unsigned Opcode);
1508bool isKMOVW(unsigned Opcode);
1509bool isBTS(unsigned Opcode);
1510bool isVPHADDBQ(unsigned Opcode);
1511bool isFRSTOR(unsigned Opcode);
1512bool isVFMSUB132PD(unsigned Opcode);
1513bool isPMULLD(unsigned Opcode);
1514bool isSHA1MSG2(unsigned Opcode);
1515bool isJECXZ(unsigned Opcode);
1516bool isVCVTUDQ2PS(unsigned Opcode);
1517bool isAESENC(unsigned Opcode);
1518bool isVMINMAXPS(unsigned Opcode);
1519bool isPSIGNW(unsigned Opcode);
1520bool isUNPCKLPD(unsigned Opcode);
1521bool isPUSHP(unsigned Opcode);
1522bool isBLSI(unsigned Opcode);
1523bool isVPTESTNMB(unsigned Opcode);
1524bool isWRUSSQ(unsigned Opcode);
1525bool isVGF2P8MULB(unsigned Opcode);
1526bool isVPUNPCKLBW(unsigned Opcode);
1527bool isVRANGESD(unsigned Opcode);
1528bool isCLD(unsigned Opcode);
1529bool isVSCALEFPD(unsigned Opcode);
1530bool isVCOMXSS(unsigned Opcode);
1531bool isVPERMQ(unsigned Opcode);
1532bool isVPSHLDVW(unsigned Opcode);
1533bool isROR(unsigned Opcode);
1534bool isVFMADDSUB132PH(unsigned Opcode);
1535bool isDEC(unsigned Opcode);
1536bool isVGETEXPSH(unsigned Opcode);
1537bool isAESDEC(unsigned Opcode);
1538bool isKORD(unsigned Opcode);
1539bool isTILELOADDT1(unsigned Opcode);
1540bool isVPMULHW(unsigned Opcode);
1541bool isVMASKMOVPS(unsigned Opcode);
1542bool isPMOVZXDQ(unsigned Opcode);
1543bool isVCVTPS2PH(unsigned Opcode);
1544bool isCVTDQ2PD(unsigned Opcode);
1545bool isVCVTSD2SS(unsigned Opcode);
1546bool isVFMSUB213PH(unsigned Opcode);
1547bool isVPROTB(unsigned Opcode);
1548bool isPINSRD(unsigned Opcode);
1549bool isVMXON(unsigned Opcode);
1550bool isVFCMULCSH(unsigned Opcode);
1551bool isVFMULCSH(unsigned Opcode);
1552bool isVRANGEPD(unsigned Opcode);
1553bool isCMC(unsigned Opcode);
1554bool isVFNMADD231BF16(unsigned Opcode);
1555bool isSHA256MSG1(unsigned Opcode);
1556bool isFLD1(unsigned Opcode);
1557bool isCMPPS(unsigned Opcode);
1558bool isVPAVGW(unsigned Opcode);
1559bool isVFMADD213SH(unsigned Opcode);
1560bool isVPCMPESTRMQ(unsigned Opcode);
1561bool isVPINSRQ(unsigned Opcode);
1562bool isMOVABS(unsigned Opcode);
1563bool isVPSHAQ(unsigned Opcode);
1564bool isRDTSCP(unsigned Opcode);
1565bool isVFNMADD231SS(unsigned Opcode);
1566bool isTEST(unsigned Opcode);
1567bool isVPERMD(unsigned Opcode);
1568bool isVBCSTNESH2PS(unsigned Opcode);
1569bool isVGATHERPF0QPD(unsigned Opcode);
1570bool isVPERM2I128(unsigned Opcode);
1571bool isVMPSADBW(unsigned Opcode);
1572bool isVFNMSUB231PD(unsigned Opcode);
1573bool isPADDSB(unsigned Opcode);
1574bool isMWAITX(unsigned Opcode);
1575bool isMONITORX(unsigned Opcode);
1576bool isVPEXPANDD(unsigned Opcode);
1577bool isVFRCZPD(unsigned Opcode);
1578bool isVRCPPH(unsigned Opcode);
1579bool isFEMMS(unsigned Opcode);
1580bool isVSCATTERQPD(unsigned Opcode);
1581bool isVMOVW(unsigned Opcode);
1582bool isVPBROADCASTD(unsigned Opcode);
1583bool isSTOSB(unsigned Opcode);
1584bool isFUCOMI(unsigned Opcode);
1585bool isVBROADCASTI64X4(unsigned Opcode);
1586bool isFCMOVU(unsigned Opcode);
1587bool isPSHUFLW(unsigned Opcode);
1588bool isCVTPI2PS(unsigned Opcode);
1589bool isVCVTTPD2UDQS(unsigned Opcode);
1590bool isSYSCALL(unsigned Opcode);
1591bool isVFMADD231SH(unsigned Opcode);
1592bool isVPOPCNTB(unsigned Opcode);
1593bool isPMOVZXBW(unsigned Opcode);
1594bool isVCVTDQ2PS(unsigned Opcode);
1595bool isPSUBD(unsigned Opcode);
1596bool isVPCMPEQW(unsigned Opcode);
1597bool isMOVSW(unsigned Opcode);
1598bool isVSM3RNDS2(unsigned Opcode);
1599bool isVPMOVUSQD(unsigned Opcode);
1600bool isCVTTPD2DQ(unsigned Opcode);
1601bool isVPEXPANDW(unsigned Opcode);
1602bool isVUCOMISH(unsigned Opcode);
1603bool isVZEROALL(unsigned Opcode);
1604bool isVPAND(unsigned Opcode);
1605bool isPMULDQ(unsigned Opcode);
1606bool isVPSHUFHW(unsigned Opcode);
1607bool isVPALIGNR(unsigned Opcode);
1608bool isSQRTSD(unsigned Opcode);
1609bool isVCVTTPH2UDQ(unsigned Opcode);
1610bool isVGETEXPPH(unsigned Opcode);
1611bool isADDPD(unsigned Opcode);
1612bool isVFNMADDPD(unsigned Opcode);
1613bool isSTTILECFG(unsigned Opcode);
1614bool isVMINPD(unsigned Opcode);
1615bool isSHA1RNDS4(unsigned Opcode);
1616bool isPBLENDVB(unsigned Opcode);
1617bool isVBROADCASTF128(unsigned Opcode);
1618bool isVPSHRDQ(unsigned Opcode);
1619bool isVAESIMC(unsigned Opcode);
1620bool isCOMISD(unsigned Opcode);
1621bool isVMOVSH(unsigned Opcode);
1622bool isPFSUBR(unsigned Opcode);
1623bool isRDSSPD(unsigned Opcode);
1624bool isWAIT(unsigned Opcode);
1625bool isVFPCLASSSS(unsigned Opcode);
1626bool isPCMPGTD(unsigned Opcode);
1627bool isVGATHERPF0QPS(unsigned Opcode);
1628bool isBLENDVPS(unsigned Opcode);
1629bool isVBROADCASTF32X4(unsigned Opcode);
1630bool isVMOVLPD(unsigned Opcode);
1631bool isVMOVQ(unsigned Opcode);
1632bool isVPMADD52LUQ(unsigned Opcode);
1633bool isVMOVDQU(unsigned Opcode);
1634bool isAESENC128KL(unsigned Opcode);
1635bool isVFMADDSUB231PS(unsigned Opcode);
1636bool isVFNMSUB213PD(unsigned Opcode);
1637bool isVPCONFLICTD(unsigned Opcode);
1638bool isVFMADDSUB213PH(unsigned Opcode);
1639bool isVPHSUBSW(unsigned Opcode);
1640bool isPUNPCKHDQ(unsigned Opcode);
1641bool isVSHUFI64X2(unsigned Opcode);
1642bool isVFMSUBSD(unsigned Opcode);
1643bool isVPORD(unsigned Opcode);
1644bool isRCPPS(unsigned Opcode);
1645bool isVEXTRACTI128(unsigned Opcode);
1646bool isVCVT2PH2BF8S(unsigned Opcode);
1647bool isVPSHRDVW(unsigned Opcode);
1648bool isVUNPCKLPD(unsigned Opcode);
1649bool isVPSRAVD(unsigned Opcode);
1650bool isVMULSH(unsigned Opcode);
1651bool isMOVNTSS(unsigned Opcode);
1652bool isSTI(unsigned Opcode);
1653bool isVSM4RNDS4(unsigned Opcode);
1654bool isVMCLEAR(unsigned Opcode);
1655bool isVPMADD52HUQ(unsigned Opcode);
1656bool isLIDT(unsigned Opcode);
1657bool isPUSH2(unsigned Opcode);
1658bool isRDPKRU(unsigned Opcode);
1659bool isVCVTPS2IUBS(unsigned Opcode);
1660bool isXSAVES64(unsigned Opcode);
1661bool isVPCMPB(unsigned Opcode);
1662bool isVFMSUB231BF16(unsigned Opcode);
1663bool isFINCSTP(unsigned Opcode);
1664bool isKORQ(unsigned Opcode);
1665bool isRDPMC(unsigned Opcode);
1666bool isVEXTRACTF128(unsigned Opcode);
1667bool isMOVMSKPD(unsigned Opcode);
1668bool isVFMSUB231SH(unsigned Opcode);
1669bool isVPSHLB(unsigned Opcode);
1670bool isXCRYPTCBC(unsigned Opcode);
1671bool isSHL(unsigned Opcode);
1672bool isAXOR(unsigned Opcode);
1673bool isVINSERTI64X2(unsigned Opcode);
1674bool isSYSRETQ(unsigned Opcode);
1675bool isVSCATTERPF0QPD(unsigned Opcode);
1676bool isVFMSUB213SH(unsigned Opcode);
1677bool isVPMOVQW(unsigned Opcode);
1678bool isVREDUCEPD(unsigned Opcode);
1679bool isNOT(unsigned Opcode);
1680bool isLWPINS(unsigned Opcode);
1681bool isVSCATTERDPS(unsigned Opcode);
1682bool isVPMOVM2W(unsigned Opcode);
1683bool isVFNMADD132PS(unsigned Opcode);
1684bool isMOVNTPS(unsigned Opcode);
1685bool isVRSQRTSS(unsigned Opcode);
1686bool isKMOVB(unsigned Opcode);
1687bool isCVTSD2SS(unsigned Opcode);
1688bool isVBROADCASTF64X2(unsigned Opcode);
1689bool isVDIVBF16(unsigned Opcode);
1690bool isMOVNTPD(unsigned Opcode);
1691bool isMAXSD(unsigned Opcode);
1692bool isCMPPD(unsigned Opcode);
1693bool isVPCMPESTRM(unsigned Opcode);
1694bool isVFMSUB132PS(unsigned Opcode);
1695bool isVCOMISH(unsigned Opcode);
1696bool isF2XM1(unsigned Opcode);
1697bool isSQRTPD(unsigned Opcode);
1698bool isVFMSUBADDPS(unsigned Opcode);
1699bool isFXTRACT(unsigned Opcode);
1700bool isVP4DPWSSD(unsigned Opcode);
1701bool isTDPBHF8PS(unsigned Opcode);
1702bool isVFMSUBADDPD(unsigned Opcode);
1703bool isVBCSTNEBF162PS(unsigned Opcode);
1704bool isVPGATHERQQ(unsigned Opcode);
1705bool isPCMPEQB(unsigned Opcode);
1706bool isTILESTORED(unsigned Opcode);
1707bool isBLSMSK(unsigned Opcode);
1708bool isVCVTTPS2DQ(unsigned Opcode);
1709bool isVFPCLASSBF16(unsigned Opcode);
1710bool isVRNDSCALEPD(unsigned Opcode);
1711bool isVMLOAD(unsigned Opcode);
1712bool isVPTERNLOGQ(unsigned Opcode);
1713bool isKXNORD(unsigned Opcode);
1714bool isFXSAVE(unsigned Opcode);
1715bool isVUNPCKHPD(unsigned Opcode);
1716bool isCVTPS2DQ(unsigned Opcode);
1717bool isVFMSUB213SS(unsigned Opcode);
1718bool isVPOPCNTD(unsigned Opcode);
1719bool isSALC(unsigned Opcode);
1720bool isV4FNMADDSS(unsigned Opcode);
1721bool isXCRYPTOFB(unsigned Opcode);
1722bool isVORPD(unsigned Opcode);
1723bool isLSL(unsigned Opcode);
1724bool isXCRYPTCFB(unsigned Opcode);
1725bool isVGETEXPSS(unsigned Opcode);
1726bool isPSLLDQ(unsigned Opcode);
1727bool isVPDPBUUD(unsigned Opcode);
1728bool isVMXOFF(unsigned Opcode);
1729bool isBLSIC(unsigned Opcode);
1730bool isMOVLHPS(unsigned Opcode);
1731bool isVMOVRSQ(unsigned Opcode);
1732bool isVFNMSUBSD(unsigned Opcode);
1733bool isVCVTPH2IUBS(unsigned Opcode);
1734bool isVFPCLASSSH(unsigned Opcode);
1735bool isVPSHLQ(unsigned Opcode);
1736bool isVROUNDPS(unsigned Opcode);
1737bool isVCVTPS2HF8S(unsigned Opcode);
1738bool isVSCATTERPF0QPS(unsigned Opcode);
1739bool isERETS(unsigned Opcode);
1740bool isVPERMI2D(unsigned Opcode);
1741bool isFUCOMP(unsigned Opcode);
1742bool isVCVTTPS2QQ(unsigned Opcode);
1743bool isPUSHFD(unsigned Opcode);
1744bool isVPABSD(unsigned Opcode);
1745bool isKORB(unsigned Opcode);
1746bool isVRCP28PD(unsigned Opcode);
1747bool isVROUNDSS(unsigned Opcode);
1748bool isVCVTSD2USI(unsigned Opcode);
1749bool isVPABSB(unsigned Opcode);
1750bool isPMAXUD(unsigned Opcode);
1751bool isVPERMPD(unsigned Opcode);
1752bool isVPMULHUW(unsigned Opcode);
1753bool isFCHS(unsigned Opcode);
1754bool isVPBLENDMB(unsigned Opcode);
1755bool isVGETMANTSS(unsigned Opcode);
1756bool isVPSLLW(unsigned Opcode);
1757bool isVDIVPD(unsigned Opcode);
1758bool isBLCMSK(unsigned Opcode);
1759bool isFDIV(unsigned Opcode);
1760bool isRSQRTSS(unsigned Opcode);
1761bool isPOR(unsigned Opcode);
1762bool isVMOVDQA32(unsigned Opcode);
1763bool isVPHADDUWQ(unsigned Opcode);
1764bool isPSRAD(unsigned Opcode);
1765bool isPREFETCHW(unsigned Opcode);
1766bool isFIDIVR(unsigned Opcode);
1767bool isMOVHPS(unsigned Opcode);
1768bool isVFNMSUB231PH(unsigned Opcode);
1769bool isUNPCKLPS(unsigned Opcode);
1770bool isVPSIGNB(unsigned Opcode);
1771bool isSAVEPREVSSP(unsigned Opcode);
1772bool isVSCALEFSD(unsigned Opcode);
1773bool isFSIN(unsigned Opcode);
1774bool isSCASQ(unsigned Opcode);
1775bool isVCVTTPD2QQS(unsigned Opcode);
1776bool isPCMPGTW(unsigned Opcode);
1777bool isMULX(unsigned Opcode);
1778bool isVPMAXUW(unsigned Opcode);
1779bool isPAUSE(unsigned Opcode);
1780bool isMOVQ2DQ(unsigned Opcode);
1781bool isVPABSW(unsigned Opcode);
1782bool isVBITREVB(unsigned Opcode);
1783bool isVPCOMPRESSD(unsigned Opcode);
1784bool isVPSUBQ(unsigned Opcode);
1785bool isVPMOVUSQW(unsigned Opcode);
1786bool isBLENDVPD(unsigned Opcode);
1787bool isVFNMADD132BF16(unsigned Opcode);
1788bool isVPMOVQB(unsigned Opcode);
1789bool isVBLENDVPS(unsigned Opcode);
1790bool isKSHIFTLQ(unsigned Opcode);
1791bool isPMOVSXWD(unsigned Opcode);
1792bool isPHSUBSW(unsigned Opcode);
1793bool isPSRLQ(unsigned Opcode);
1794bool isVCVTPH2DQ(unsigned Opcode);
1795bool isPCMPESTRIQ(unsigned Opcode);
1796bool isFISUB(unsigned Opcode);
1797bool isVCVTPS2UDQ(unsigned Opcode);
1798bool isVMOVDDUP(unsigned Opcode);
1799bool isPCMPEQD(unsigned Opcode);
1800bool isVRSQRT28SD(unsigned Opcode);
1801bool isTDPHBF8PS(unsigned Opcode);
1802bool isLODSW(unsigned Opcode);
1803bool isVPOPCNTQ(unsigned Opcode);
1804bool isKSHIFTRB(unsigned Opcode);
1805bool isVFNMADDPS(unsigned Opcode);
1806bool isCCMPCC(unsigned Opcode);
1807bool isFXRSTOR64(unsigned Opcode);
1808bool isVFMSUBADD213PD(unsigned Opcode);
1809bool isVSQRTPH(unsigned Opcode);
1810bool isPOPF(unsigned Opcode);
1811bool isVPSUBUSB(unsigned Opcode);
1812bool isTCVTROWPS2BF16L(unsigned Opcode);
1813bool isVPADDSW(unsigned Opcode);
1814bool isPREFETCHIT1(unsigned Opcode);
1815bool isVADDSUBPD(unsigned Opcode);
1816bool isKANDD(unsigned Opcode);
1817bool isPREFETCHRST2(unsigned Opcode);
1818bool isOUTSB(unsigned Opcode);
1819bool isFNSTSW(unsigned Opcode);
1820bool isPMINSB(unsigned Opcode);
1821
1822} // namespace llvm::X86
1823
1824#endif // GET_X86_MNEMONIC_TABLES_H
1825
1826#ifdef GET_X86_MNEMONIC_TABLES_CPP
1827#undef GET_X86_MNEMONIC_TABLES_CPP
1828
1829namespace llvm::X86 {
1830
1831bool isFSUBRP(unsigned Opcode) {
1832 return Opcode == SUBR_FPrST0;
1833}
1834
1835bool isVPDPBUSDS(unsigned Opcode) {
1836 switch (Opcode) {
1837 case VPDPBUSDSYrm:
1838 case VPDPBUSDSYrr:
1839 case VPDPBUSDSZ128rm:
1840 case VPDPBUSDSZ128rmb:
1841 case VPDPBUSDSZ128rmbk:
1842 case VPDPBUSDSZ128rmbkz:
1843 case VPDPBUSDSZ128rmk:
1844 case VPDPBUSDSZ128rmkz:
1845 case VPDPBUSDSZ128rr:
1846 case VPDPBUSDSZ128rrk:
1847 case VPDPBUSDSZ128rrkz:
1848 case VPDPBUSDSZ256rm:
1849 case VPDPBUSDSZ256rmb:
1850 case VPDPBUSDSZ256rmbk:
1851 case VPDPBUSDSZ256rmbkz:
1852 case VPDPBUSDSZ256rmk:
1853 case VPDPBUSDSZ256rmkz:
1854 case VPDPBUSDSZ256rr:
1855 case VPDPBUSDSZ256rrk:
1856 case VPDPBUSDSZ256rrkz:
1857 case VPDPBUSDSZrm:
1858 case VPDPBUSDSZrmb:
1859 case VPDPBUSDSZrmbk:
1860 case VPDPBUSDSZrmbkz:
1861 case VPDPBUSDSZrmk:
1862 case VPDPBUSDSZrmkz:
1863 case VPDPBUSDSZrr:
1864 case VPDPBUSDSZrrk:
1865 case VPDPBUSDSZrrkz:
1866 case VPDPBUSDSrm:
1867 case VPDPBUSDSrr:
1868 return true;
1869 }
1870 return false;
1871}
1872
1873bool isPUNPCKLWD(unsigned Opcode) {
1874 switch (Opcode) {
1875 case MMX_PUNPCKLWDrm:
1876 case MMX_PUNPCKLWDrr:
1877 case PUNPCKLWDrm:
1878 case PUNPCKLWDrr:
1879 return true;
1880 }
1881 return false;
1882}
1883
1884bool isVREDUCEBF16(unsigned Opcode) {
1885 switch (Opcode) {
1886 case VREDUCEBF16Z128rmbi:
1887 case VREDUCEBF16Z128rmbik:
1888 case VREDUCEBF16Z128rmbikz:
1889 case VREDUCEBF16Z128rmi:
1890 case VREDUCEBF16Z128rmik:
1891 case VREDUCEBF16Z128rmikz:
1892 case VREDUCEBF16Z128rri:
1893 case VREDUCEBF16Z128rrik:
1894 case VREDUCEBF16Z128rrikz:
1895 case VREDUCEBF16Z256rmbi:
1896 case VREDUCEBF16Z256rmbik:
1897 case VREDUCEBF16Z256rmbikz:
1898 case VREDUCEBF16Z256rmi:
1899 case VREDUCEBF16Z256rmik:
1900 case VREDUCEBF16Z256rmikz:
1901 case VREDUCEBF16Z256rri:
1902 case VREDUCEBF16Z256rrik:
1903 case VREDUCEBF16Z256rrikz:
1904 case VREDUCEBF16Zrmbi:
1905 case VREDUCEBF16Zrmbik:
1906 case VREDUCEBF16Zrmbikz:
1907 case VREDUCEBF16Zrmi:
1908 case VREDUCEBF16Zrmik:
1909 case VREDUCEBF16Zrmikz:
1910 case VREDUCEBF16Zrri:
1911 case VREDUCEBF16Zrrik:
1912 case VREDUCEBF16Zrrikz:
1913 return true;
1914 }
1915 return false;
1916}
1917
1918bool isPUNPCKLQDQ(unsigned Opcode) {
1919 switch (Opcode) {
1920 case PUNPCKLQDQrm:
1921 case PUNPCKLQDQrr:
1922 return true;
1923 }
1924 return false;
1925}
1926
1927bool isRDFSBASE(unsigned Opcode) {
1928 switch (Opcode) {
1929 case RDFSBASE:
1930 case RDFSBASE64:
1931 return true;
1932 }
1933 return false;
1934}
1935
1936bool isVPCMOV(unsigned Opcode) {
1937 switch (Opcode) {
1938 case VPCMOVYrmr:
1939 case VPCMOVYrrm:
1940 case VPCMOVYrrr:
1941 case VPCMOVYrrr_REV:
1942 case VPCMOVrmr:
1943 case VPCMOVrrm:
1944 case VPCMOVrrr:
1945 case VPCMOVrrr_REV:
1946 return true;
1947 }
1948 return false;
1949}
1950
1951bool isVDIVSD(unsigned Opcode) {
1952 switch (Opcode) {
1953 case VDIVSDZrm_Int:
1954 case VDIVSDZrmk_Int:
1955 case VDIVSDZrmkz_Int:
1956 case VDIVSDZrr_Int:
1957 case VDIVSDZrrb_Int:
1958 case VDIVSDZrrbk_Int:
1959 case VDIVSDZrrbkz_Int:
1960 case VDIVSDZrrk_Int:
1961 case VDIVSDZrrkz_Int:
1962 case VDIVSDrm_Int:
1963 case VDIVSDrr_Int:
1964 return true;
1965 }
1966 return false;
1967}
1968
1969bool isVCVTTPS2IBS(unsigned Opcode) {
1970 switch (Opcode) {
1971 case VCVTTPS2IBSZ128rm:
1972 case VCVTTPS2IBSZ128rmb:
1973 case VCVTTPS2IBSZ128rmbk:
1974 case VCVTTPS2IBSZ128rmbkz:
1975 case VCVTTPS2IBSZ128rmk:
1976 case VCVTTPS2IBSZ128rmkz:
1977 case VCVTTPS2IBSZ128rr:
1978 case VCVTTPS2IBSZ128rrk:
1979 case VCVTTPS2IBSZ128rrkz:
1980 case VCVTTPS2IBSZ256rm:
1981 case VCVTTPS2IBSZ256rmb:
1982 case VCVTTPS2IBSZ256rmbk:
1983 case VCVTTPS2IBSZ256rmbkz:
1984 case VCVTTPS2IBSZ256rmk:
1985 case VCVTTPS2IBSZ256rmkz:
1986 case VCVTTPS2IBSZ256rr:
1987 case VCVTTPS2IBSZ256rrk:
1988 case VCVTTPS2IBSZ256rrkz:
1989 case VCVTTPS2IBSZrm:
1990 case VCVTTPS2IBSZrmb:
1991 case VCVTTPS2IBSZrmbk:
1992 case VCVTTPS2IBSZrmbkz:
1993 case VCVTTPS2IBSZrmk:
1994 case VCVTTPS2IBSZrmkz:
1995 case VCVTTPS2IBSZrr:
1996 case VCVTTPS2IBSZrrb:
1997 case VCVTTPS2IBSZrrbk:
1998 case VCVTTPS2IBSZrrbkz:
1999 case VCVTTPS2IBSZrrk:
2000 case VCVTTPS2IBSZrrkz:
2001 return true;
2002 }
2003 return false;
2004}
2005
2006bool isVPEXTRW(unsigned Opcode) {
2007 switch (Opcode) {
2008 case VPEXTRWZmri:
2009 case VPEXTRWZrri:
2010 case VPEXTRWZrri_REV:
2011 case VPEXTRWmri:
2012 case VPEXTRWrri:
2013 case VPEXTRWrri_REV:
2014 return true;
2015 }
2016 return false;
2017}
2018
2019bool isLODSD(unsigned Opcode) {
2020 return Opcode == LODSL;
2021}
2022
2023bool isVPTESTNMQ(unsigned Opcode) {
2024 switch (Opcode) {
2025 case VPTESTNMQZ128rm:
2026 case VPTESTNMQZ128rmb:
2027 case VPTESTNMQZ128rmbk:
2028 case VPTESTNMQZ128rmk:
2029 case VPTESTNMQZ128rr:
2030 case VPTESTNMQZ128rrk:
2031 case VPTESTNMQZ256rm:
2032 case VPTESTNMQZ256rmb:
2033 case VPTESTNMQZ256rmbk:
2034 case VPTESTNMQZ256rmk:
2035 case VPTESTNMQZ256rr:
2036 case VPTESTNMQZ256rrk:
2037 case VPTESTNMQZrm:
2038 case VPTESTNMQZrmb:
2039 case VPTESTNMQZrmbk:
2040 case VPTESTNMQZrmk:
2041 case VPTESTNMQZrr:
2042 case VPTESTNMQZrrk:
2043 return true;
2044 }
2045 return false;
2046}
2047
2048bool isCVTSS2SD(unsigned Opcode) {
2049 switch (Opcode) {
2050 case CVTSS2SDrm_Int:
2051 case CVTSS2SDrr_Int:
2052 return true;
2053 }
2054 return false;
2055}
2056
2057bool isVGETMANTPD(unsigned Opcode) {
2058 switch (Opcode) {
2059 case VGETMANTPDZ128rmbi:
2060 case VGETMANTPDZ128rmbik:
2061 case VGETMANTPDZ128rmbikz:
2062 case VGETMANTPDZ128rmi:
2063 case VGETMANTPDZ128rmik:
2064 case VGETMANTPDZ128rmikz:
2065 case VGETMANTPDZ128rri:
2066 case VGETMANTPDZ128rrik:
2067 case VGETMANTPDZ128rrikz:
2068 case VGETMANTPDZ256rmbi:
2069 case VGETMANTPDZ256rmbik:
2070 case VGETMANTPDZ256rmbikz:
2071 case VGETMANTPDZ256rmi:
2072 case VGETMANTPDZ256rmik:
2073 case VGETMANTPDZ256rmikz:
2074 case VGETMANTPDZ256rri:
2075 case VGETMANTPDZ256rrik:
2076 case VGETMANTPDZ256rrikz:
2077 case VGETMANTPDZrmbi:
2078 case VGETMANTPDZrmbik:
2079 case VGETMANTPDZrmbikz:
2080 case VGETMANTPDZrmi:
2081 case VGETMANTPDZrmik:
2082 case VGETMANTPDZrmikz:
2083 case VGETMANTPDZrri:
2084 case VGETMANTPDZrrib:
2085 case VGETMANTPDZrribk:
2086 case VGETMANTPDZrribkz:
2087 case VGETMANTPDZrrik:
2088 case VGETMANTPDZrrikz:
2089 return true;
2090 }
2091 return false;
2092}
2093
2094bool isVMOVDQA64(unsigned Opcode) {
2095 switch (Opcode) {
2096 case VMOVDQA64Z128mr:
2097 case VMOVDQA64Z128mrk:
2098 case VMOVDQA64Z128rm:
2099 case VMOVDQA64Z128rmk:
2100 case VMOVDQA64Z128rmkz:
2101 case VMOVDQA64Z128rr:
2102 case VMOVDQA64Z128rr_REV:
2103 case VMOVDQA64Z128rrk:
2104 case VMOVDQA64Z128rrk_REV:
2105 case VMOVDQA64Z128rrkz:
2106 case VMOVDQA64Z128rrkz_REV:
2107 case VMOVDQA64Z256mr:
2108 case VMOVDQA64Z256mrk:
2109 case VMOVDQA64Z256rm:
2110 case VMOVDQA64Z256rmk:
2111 case VMOVDQA64Z256rmkz:
2112 case VMOVDQA64Z256rr:
2113 case VMOVDQA64Z256rr_REV:
2114 case VMOVDQA64Z256rrk:
2115 case VMOVDQA64Z256rrk_REV:
2116 case VMOVDQA64Z256rrkz:
2117 case VMOVDQA64Z256rrkz_REV:
2118 case VMOVDQA64Zmr:
2119 case VMOVDQA64Zmrk:
2120 case VMOVDQA64Zrm:
2121 case VMOVDQA64Zrmk:
2122 case VMOVDQA64Zrmkz:
2123 case VMOVDQA64Zrr:
2124 case VMOVDQA64Zrr_REV:
2125 case VMOVDQA64Zrrk:
2126 case VMOVDQA64Zrrk_REV:
2127 case VMOVDQA64Zrrkz:
2128 case VMOVDQA64Zrrkz_REV:
2129 return true;
2130 }
2131 return false;
2132}
2133
2134bool isINVLPG(unsigned Opcode) {
2135 return Opcode == INVLPG;
2136}
2137
2138bool isVGETEXPBF16(unsigned Opcode) {
2139 switch (Opcode) {
2140 case VGETEXPBF16Z128m:
2141 case VGETEXPBF16Z128mb:
2142 case VGETEXPBF16Z128mbk:
2143 case VGETEXPBF16Z128mbkz:
2144 case VGETEXPBF16Z128mk:
2145 case VGETEXPBF16Z128mkz:
2146 case VGETEXPBF16Z128r:
2147 case VGETEXPBF16Z128rk:
2148 case VGETEXPBF16Z128rkz:
2149 case VGETEXPBF16Z256m:
2150 case VGETEXPBF16Z256mb:
2151 case VGETEXPBF16Z256mbk:
2152 case VGETEXPBF16Z256mbkz:
2153 case VGETEXPBF16Z256mk:
2154 case VGETEXPBF16Z256mkz:
2155 case VGETEXPBF16Z256r:
2156 case VGETEXPBF16Z256rk:
2157 case VGETEXPBF16Z256rkz:
2158 case VGETEXPBF16Zm:
2159 case VGETEXPBF16Zmb:
2160 case VGETEXPBF16Zmbk:
2161 case VGETEXPBF16Zmbkz:
2162 case VGETEXPBF16Zmk:
2163 case VGETEXPBF16Zmkz:
2164 case VGETEXPBF16Zr:
2165 case VGETEXPBF16Zrk:
2166 case VGETEXPBF16Zrkz:
2167 return true;
2168 }
2169 return false;
2170}
2171
2172bool isVBROADCASTF64X4(unsigned Opcode) {
2173 switch (Opcode) {
2174 case VBROADCASTF64X4Zrm:
2175 case VBROADCASTF64X4Zrmk:
2176 case VBROADCASTF64X4Zrmkz:
2177 return true;
2178 }
2179 return false;
2180}
2181
2182bool isVPERMI2Q(unsigned Opcode) {
2183 switch (Opcode) {
2184 case VPERMI2QZ128rm:
2185 case VPERMI2QZ128rmb:
2186 case VPERMI2QZ128rmbk:
2187 case VPERMI2QZ128rmbkz:
2188 case VPERMI2QZ128rmk:
2189 case VPERMI2QZ128rmkz:
2190 case VPERMI2QZ128rr:
2191 case VPERMI2QZ128rrk:
2192 case VPERMI2QZ128rrkz:
2193 case VPERMI2QZ256rm:
2194 case VPERMI2QZ256rmb:
2195 case VPERMI2QZ256rmbk:
2196 case VPERMI2QZ256rmbkz:
2197 case VPERMI2QZ256rmk:
2198 case VPERMI2QZ256rmkz:
2199 case VPERMI2QZ256rr:
2200 case VPERMI2QZ256rrk:
2201 case VPERMI2QZ256rrkz:
2202 case VPERMI2QZrm:
2203 case VPERMI2QZrmb:
2204 case VPERMI2QZrmbk:
2205 case VPERMI2QZrmbkz:
2206 case VPERMI2QZrmk:
2207 case VPERMI2QZrmkz:
2208 case VPERMI2QZrr:
2209 case VPERMI2QZrrk:
2210 case VPERMI2QZrrkz:
2211 return true;
2212 }
2213 return false;
2214}
2215
2216bool isVPMOVSXBD(unsigned Opcode) {
2217 switch (Opcode) {
2218 case VPMOVSXBDYrm:
2219 case VPMOVSXBDYrr:
2220 case VPMOVSXBDZ128rm:
2221 case VPMOVSXBDZ128rmk:
2222 case VPMOVSXBDZ128rmkz:
2223 case VPMOVSXBDZ128rr:
2224 case VPMOVSXBDZ128rrk:
2225 case VPMOVSXBDZ128rrkz:
2226 case VPMOVSXBDZ256rm:
2227 case VPMOVSXBDZ256rmk:
2228 case VPMOVSXBDZ256rmkz:
2229 case VPMOVSXBDZ256rr:
2230 case VPMOVSXBDZ256rrk:
2231 case VPMOVSXBDZ256rrkz:
2232 case VPMOVSXBDZrm:
2233 case VPMOVSXBDZrmk:
2234 case VPMOVSXBDZrmkz:
2235 case VPMOVSXBDZrr:
2236 case VPMOVSXBDZrrk:
2237 case VPMOVSXBDZrrkz:
2238 case VPMOVSXBDrm:
2239 case VPMOVSXBDrr:
2240 return true;
2241 }
2242 return false;
2243}
2244
2245bool isVFMSUB132SS(unsigned Opcode) {
2246 switch (Opcode) {
2247 case VFMSUB132SSZm_Int:
2248 case VFMSUB132SSZmk_Int:
2249 case VFMSUB132SSZmkz_Int:
2250 case VFMSUB132SSZr_Int:
2251 case VFMSUB132SSZrb_Int:
2252 case VFMSUB132SSZrbk_Int:
2253 case VFMSUB132SSZrbkz_Int:
2254 case VFMSUB132SSZrk_Int:
2255 case VFMSUB132SSZrkz_Int:
2256 case VFMSUB132SSm_Int:
2257 case VFMSUB132SSr_Int:
2258 return true;
2259 }
2260 return false;
2261}
2262
2263bool isVPMOVUSDW(unsigned Opcode) {
2264 switch (Opcode) {
2265 case VPMOVUSDWZ128mr:
2266 case VPMOVUSDWZ128mrk:
2267 case VPMOVUSDWZ128rr:
2268 case VPMOVUSDWZ128rrk:
2269 case VPMOVUSDWZ128rrkz:
2270 case VPMOVUSDWZ256mr:
2271 case VPMOVUSDWZ256mrk:
2272 case VPMOVUSDWZ256rr:
2273 case VPMOVUSDWZ256rrk:
2274 case VPMOVUSDWZ256rrkz:
2275 case VPMOVUSDWZmr:
2276 case VPMOVUSDWZmrk:
2277 case VPMOVUSDWZrr:
2278 case VPMOVUSDWZrrk:
2279 case VPMOVUSDWZrrkz:
2280 return true;
2281 }
2282 return false;
2283}
2284
2285bool isAAD(unsigned Opcode) {
2286 return Opcode == AAD8i8;
2287}
2288
2289bool isIDIV(unsigned Opcode) {
2290 switch (Opcode) {
2291 case IDIV16m:
2292 case IDIV16m_EVEX:
2293 case IDIV16m_NF:
2294 case IDIV16r:
2295 case IDIV16r_EVEX:
2296 case IDIV16r_NF:
2297 case IDIV32m:
2298 case IDIV32m_EVEX:
2299 case IDIV32m_NF:
2300 case IDIV32r:
2301 case IDIV32r_EVEX:
2302 case IDIV32r_NF:
2303 case IDIV64m:
2304 case IDIV64m_EVEX:
2305 case IDIV64m_NF:
2306 case IDIV64r:
2307 case IDIV64r_EVEX:
2308 case IDIV64r_NF:
2309 case IDIV8m:
2310 case IDIV8m_EVEX:
2311 case IDIV8m_NF:
2312 case IDIV8r:
2313 case IDIV8r_EVEX:
2314 case IDIV8r_NF:
2315 return true;
2316 }
2317 return false;
2318}
2319
2320bool isCVTTPS2DQ(unsigned Opcode) {
2321 switch (Opcode) {
2322 case CVTTPS2DQrm:
2323 case CVTTPS2DQrr:
2324 return true;
2325 }
2326 return false;
2327}
2328
2329bool isVBROADCASTF32X8(unsigned Opcode) {
2330 switch (Opcode) {
2331 case VBROADCASTF32X8Zrm:
2332 case VBROADCASTF32X8Zrmk:
2333 case VBROADCASTF32X8Zrmkz:
2334 return true;
2335 }
2336 return false;
2337}
2338
2339bool isVFMSUBSS(unsigned Opcode) {
2340 switch (Opcode) {
2341 case VFMSUBSS4mr:
2342 case VFMSUBSS4rm:
2343 case VFMSUBSS4rr:
2344 case VFMSUBSS4rr_REV:
2345 return true;
2346 }
2347 return false;
2348}
2349
2350bool isEMMS(unsigned Opcode) {
2351 return Opcode == MMX_EMMS;
2352}
2353
2354bool isVPDPBSUD(unsigned Opcode) {
2355 switch (Opcode) {
2356 case VPDPBSUDYrm:
2357 case VPDPBSUDYrr:
2358 case VPDPBSUDZ128rm:
2359 case VPDPBSUDZ128rmb:
2360 case VPDPBSUDZ128rmbk:
2361 case VPDPBSUDZ128rmbkz:
2362 case VPDPBSUDZ128rmk:
2363 case VPDPBSUDZ128rmkz:
2364 case VPDPBSUDZ128rr:
2365 case VPDPBSUDZ128rrk:
2366 case VPDPBSUDZ128rrkz:
2367 case VPDPBSUDZ256rm:
2368 case VPDPBSUDZ256rmb:
2369 case VPDPBSUDZ256rmbk:
2370 case VPDPBSUDZ256rmbkz:
2371 case VPDPBSUDZ256rmk:
2372 case VPDPBSUDZ256rmkz:
2373 case VPDPBSUDZ256rr:
2374 case VPDPBSUDZ256rrk:
2375 case VPDPBSUDZ256rrkz:
2376 case VPDPBSUDZrm:
2377 case VPDPBSUDZrmb:
2378 case VPDPBSUDZrmbk:
2379 case VPDPBSUDZrmbkz:
2380 case VPDPBSUDZrmk:
2381 case VPDPBSUDZrmkz:
2382 case VPDPBSUDZrr:
2383 case VPDPBSUDZrrk:
2384 case VPDPBSUDZrrkz:
2385 case VPDPBSUDrm:
2386 case VPDPBSUDrr:
2387 return true;
2388 }
2389 return false;
2390}
2391
2392bool isPMOVSXWQ(unsigned Opcode) {
2393 switch (Opcode) {
2394 case PMOVSXWQrm:
2395 case PMOVSXWQrr:
2396 return true;
2397 }
2398 return false;
2399}
2400
2401bool isPSRLW(unsigned Opcode) {
2402 switch (Opcode) {
2403 case MMX_PSRLWri:
2404 case MMX_PSRLWrm:
2405 case MMX_PSRLWrr:
2406 case PSRLWri:
2407 case PSRLWrm:
2408 case PSRLWrr:
2409 return true;
2410 }
2411 return false;
2412}
2413
2414bool isMOVNTDQA(unsigned Opcode) {
2415 return Opcode == MOVNTDQArm;
2416}
2417
2418bool isFUCOMPI(unsigned Opcode) {
2419 return Opcode == UCOM_FIPr;
2420}
2421
2422bool isANDNPS(unsigned Opcode) {
2423 switch (Opcode) {
2424 case ANDNPSrm:
2425 case ANDNPSrr:
2426 return true;
2427 }
2428 return false;
2429}
2430
2431bool isVINSERTF64X2(unsigned Opcode) {
2432 switch (Opcode) {
2433 case VINSERTF64X2Z256rmi:
2434 case VINSERTF64X2Z256rmik:
2435 case VINSERTF64X2Z256rmikz:
2436 case VINSERTF64X2Z256rri:
2437 case VINSERTF64X2Z256rrik:
2438 case VINSERTF64X2Z256rrikz:
2439 case VINSERTF64X2Zrmi:
2440 case VINSERTF64X2Zrmik:
2441 case VINSERTF64X2Zrmikz:
2442 case VINSERTF64X2Zrri:
2443 case VINSERTF64X2Zrrik:
2444 case VINSERTF64X2Zrrikz:
2445 return true;
2446 }
2447 return false;
2448}
2449
2450bool isCLTS(unsigned Opcode) {
2451 return Opcode == CLTS;
2452}
2453
2454bool isSETSSBSY(unsigned Opcode) {
2455 return Opcode == SETSSBSY;
2456}
2457
2458bool isVMULPD(unsigned Opcode) {
2459 switch (Opcode) {
2460 case VMULPDYrm:
2461 case VMULPDYrr:
2462 case VMULPDZ128rm:
2463 case VMULPDZ128rmb:
2464 case VMULPDZ128rmbk:
2465 case VMULPDZ128rmbkz:
2466 case VMULPDZ128rmk:
2467 case VMULPDZ128rmkz:
2468 case VMULPDZ128rr:
2469 case VMULPDZ128rrk:
2470 case VMULPDZ128rrkz:
2471 case VMULPDZ256rm:
2472 case VMULPDZ256rmb:
2473 case VMULPDZ256rmbk:
2474 case VMULPDZ256rmbkz:
2475 case VMULPDZ256rmk:
2476 case VMULPDZ256rmkz:
2477 case VMULPDZ256rr:
2478 case VMULPDZ256rrk:
2479 case VMULPDZ256rrkz:
2480 case VMULPDZrm:
2481 case VMULPDZrmb:
2482 case VMULPDZrmbk:
2483 case VMULPDZrmbkz:
2484 case VMULPDZrmk:
2485 case VMULPDZrmkz:
2486 case VMULPDZrr:
2487 case VMULPDZrrb:
2488 case VMULPDZrrbk:
2489 case VMULPDZrrbkz:
2490 case VMULPDZrrk:
2491 case VMULPDZrrkz:
2492 case VMULPDrm:
2493 case VMULPDrr:
2494 return true;
2495 }
2496 return false;
2497}
2498
2499bool isVFMADDSUB132PS(unsigned Opcode) {
2500 switch (Opcode) {
2501 case VFMADDSUB132PSYm:
2502 case VFMADDSUB132PSYr:
2503 case VFMADDSUB132PSZ128m:
2504 case VFMADDSUB132PSZ128mb:
2505 case VFMADDSUB132PSZ128mbk:
2506 case VFMADDSUB132PSZ128mbkz:
2507 case VFMADDSUB132PSZ128mk:
2508 case VFMADDSUB132PSZ128mkz:
2509 case VFMADDSUB132PSZ128r:
2510 case VFMADDSUB132PSZ128rk:
2511 case VFMADDSUB132PSZ128rkz:
2512 case VFMADDSUB132PSZ256m:
2513 case VFMADDSUB132PSZ256mb:
2514 case VFMADDSUB132PSZ256mbk:
2515 case VFMADDSUB132PSZ256mbkz:
2516 case VFMADDSUB132PSZ256mk:
2517 case VFMADDSUB132PSZ256mkz:
2518 case VFMADDSUB132PSZ256r:
2519 case VFMADDSUB132PSZ256rk:
2520 case VFMADDSUB132PSZ256rkz:
2521 case VFMADDSUB132PSZm:
2522 case VFMADDSUB132PSZmb:
2523 case VFMADDSUB132PSZmbk:
2524 case VFMADDSUB132PSZmbkz:
2525 case VFMADDSUB132PSZmk:
2526 case VFMADDSUB132PSZmkz:
2527 case VFMADDSUB132PSZr:
2528 case VFMADDSUB132PSZrb:
2529 case VFMADDSUB132PSZrbk:
2530 case VFMADDSUB132PSZrbkz:
2531 case VFMADDSUB132PSZrk:
2532 case VFMADDSUB132PSZrkz:
2533 case VFMADDSUB132PSm:
2534 case VFMADDSUB132PSr:
2535 return true;
2536 }
2537 return false;
2538}
2539
2540bool isVPMADCSWD(unsigned Opcode) {
2541 switch (Opcode) {
2542 case VPMADCSWDrm:
2543 case VPMADCSWDrr:
2544 return true;
2545 }
2546 return false;
2547}
2548
2549bool isVSCATTERPF0DPS(unsigned Opcode) {
2550 return Opcode == VSCATTERPF0DPSm;
2551}
2552
2553bool isXCHG(unsigned Opcode) {
2554 switch (Opcode) {
2555 case XCHG16ar:
2556 case XCHG16rm:
2557 case XCHG16rr:
2558 case XCHG32ar:
2559 case XCHG32rm:
2560 case XCHG32rr:
2561 case XCHG64ar:
2562 case XCHG64rm:
2563 case XCHG64rr:
2564 case XCHG8rm:
2565 case XCHG8rr:
2566 return true;
2567 }
2568 return false;
2569}
2570
2571bool isVGATHERPF1QPS(unsigned Opcode) {
2572 return Opcode == VGATHERPF1QPSm;
2573}
2574
2575bool isVCVTNEPS2BF16(unsigned Opcode) {
2576 switch (Opcode) {
2577 case VCVTNEPS2BF16Yrm:
2578 case VCVTNEPS2BF16Yrr:
2579 case VCVTNEPS2BF16Z128rm:
2580 case VCVTNEPS2BF16Z128rmb:
2581 case VCVTNEPS2BF16Z128rmbk:
2582 case VCVTNEPS2BF16Z128rmbkz:
2583 case VCVTNEPS2BF16Z128rmk:
2584 case VCVTNEPS2BF16Z128rmkz:
2585 case VCVTNEPS2BF16Z128rr:
2586 case VCVTNEPS2BF16Z128rrk:
2587 case VCVTNEPS2BF16Z128rrkz:
2588 case VCVTNEPS2BF16Z256rm:
2589 case VCVTNEPS2BF16Z256rmb:
2590 case VCVTNEPS2BF16Z256rmbk:
2591 case VCVTNEPS2BF16Z256rmbkz:
2592 case VCVTNEPS2BF16Z256rmk:
2593 case VCVTNEPS2BF16Z256rmkz:
2594 case VCVTNEPS2BF16Z256rr:
2595 case VCVTNEPS2BF16Z256rrk:
2596 case VCVTNEPS2BF16Z256rrkz:
2597 case VCVTNEPS2BF16Zrm:
2598 case VCVTNEPS2BF16Zrmb:
2599 case VCVTNEPS2BF16Zrmbk:
2600 case VCVTNEPS2BF16Zrmbkz:
2601 case VCVTNEPS2BF16Zrmk:
2602 case VCVTNEPS2BF16Zrmkz:
2603 case VCVTNEPS2BF16Zrr:
2604 case VCVTNEPS2BF16Zrrk:
2605 case VCVTNEPS2BF16Zrrkz:
2606 case VCVTNEPS2BF16rm:
2607 case VCVTNEPS2BF16rr:
2608 return true;
2609 }
2610 return false;
2611}
2612
2613bool isVFMADDSS(unsigned Opcode) {
2614 switch (Opcode) {
2615 case VFMADDSS4mr:
2616 case VFMADDSS4rm:
2617 case VFMADDSS4rr:
2618 case VFMADDSS4rr_REV:
2619 return true;
2620 }
2621 return false;
2622}
2623
2624bool isINTO(unsigned Opcode) {
2625 return Opcode == INTO;
2626}
2627
2628bool isANDPD(unsigned Opcode) {
2629 switch (Opcode) {
2630 case ANDPDrm:
2631 case ANDPDrr:
2632 return true;
2633 }
2634 return false;
2635}
2636
2637bool isSEAMCALL(unsigned Opcode) {
2638 return Opcode == SEAMCALL;
2639}
2640
2641bool isSHLD(unsigned Opcode) {
2642 switch (Opcode) {
2643 case SHLD16mrCL:
2644 case SHLD16mrCL_EVEX:
2645 case SHLD16mrCL_ND:
2646 case SHLD16mrCL_NF:
2647 case SHLD16mrCL_NF_ND:
2648 case SHLD16mri8:
2649 case SHLD16mri8_EVEX:
2650 case SHLD16mri8_ND:
2651 case SHLD16mri8_NF:
2652 case SHLD16mri8_NF_ND:
2653 case SHLD16rrCL:
2654 case SHLD16rrCL_EVEX:
2655 case SHLD16rrCL_ND:
2656 case SHLD16rrCL_NF:
2657 case SHLD16rrCL_NF_ND:
2658 case SHLD16rri8:
2659 case SHLD16rri8_EVEX:
2660 case SHLD16rri8_ND:
2661 case SHLD16rri8_NF:
2662 case SHLD16rri8_NF_ND:
2663 case SHLD32mrCL:
2664 case SHLD32mrCL_EVEX:
2665 case SHLD32mrCL_ND:
2666 case SHLD32mrCL_NF:
2667 case SHLD32mrCL_NF_ND:
2668 case SHLD32mri8:
2669 case SHLD32mri8_EVEX:
2670 case SHLD32mri8_ND:
2671 case SHLD32mri8_NF:
2672 case SHLD32mri8_NF_ND:
2673 case SHLD32rrCL:
2674 case SHLD32rrCL_EVEX:
2675 case SHLD32rrCL_ND:
2676 case SHLD32rrCL_NF:
2677 case SHLD32rrCL_NF_ND:
2678 case SHLD32rri8:
2679 case SHLD32rri8_EVEX:
2680 case SHLD32rri8_ND:
2681 case SHLD32rri8_NF:
2682 case SHLD32rri8_NF_ND:
2683 case SHLD64mrCL:
2684 case SHLD64mrCL_EVEX:
2685 case SHLD64mrCL_ND:
2686 case SHLD64mrCL_NF:
2687 case SHLD64mrCL_NF_ND:
2688 case SHLD64mri8:
2689 case SHLD64mri8_EVEX:
2690 case SHLD64mri8_ND:
2691 case SHLD64mri8_NF:
2692 case SHLD64mri8_NF_ND:
2693 case SHLD64rrCL:
2694 case SHLD64rrCL_EVEX:
2695 case SHLD64rrCL_ND:
2696 case SHLD64rrCL_NF:
2697 case SHLD64rrCL_NF_ND:
2698 case SHLD64rri8:
2699 case SHLD64rri8_EVEX:
2700 case SHLD64rri8_ND:
2701 case SHLD64rri8_NF:
2702 case SHLD64rri8_NF_ND:
2703 return true;
2704 }
2705 return false;
2706}
2707
2708bool isUNPCKHPS(unsigned Opcode) {
2709 switch (Opcode) {
2710 case UNPCKHPSrm:
2711 case UNPCKHPSrr:
2712 return true;
2713 }
2714 return false;
2715}
2716
2717bool isVPDPBSSDS(unsigned Opcode) {
2718 switch (Opcode) {
2719 case VPDPBSSDSYrm:
2720 case VPDPBSSDSYrr:
2721 case VPDPBSSDSZ128rm:
2722 case VPDPBSSDSZ128rmb:
2723 case VPDPBSSDSZ128rmbk:
2724 case VPDPBSSDSZ128rmbkz:
2725 case VPDPBSSDSZ128rmk:
2726 case VPDPBSSDSZ128rmkz:
2727 case VPDPBSSDSZ128rr:
2728 case VPDPBSSDSZ128rrk:
2729 case VPDPBSSDSZ128rrkz:
2730 case VPDPBSSDSZ256rm:
2731 case VPDPBSSDSZ256rmb:
2732 case VPDPBSSDSZ256rmbk:
2733 case VPDPBSSDSZ256rmbkz:
2734 case VPDPBSSDSZ256rmk:
2735 case VPDPBSSDSZ256rmkz:
2736 case VPDPBSSDSZ256rr:
2737 case VPDPBSSDSZ256rrk:
2738 case VPDPBSSDSZ256rrkz:
2739 case VPDPBSSDSZrm:
2740 case VPDPBSSDSZrmb:
2741 case VPDPBSSDSZrmbk:
2742 case VPDPBSSDSZrmbkz:
2743 case VPDPBSSDSZrmk:
2744 case VPDPBSSDSZrmkz:
2745 case VPDPBSSDSZrr:
2746 case VPDPBSSDSZrrk:
2747 case VPDPBSSDSZrrkz:
2748 case VPDPBSSDSrm:
2749 case VPDPBSSDSrr:
2750 return true;
2751 }
2752 return false;
2753}
2754
2755bool isSETZUCC(unsigned Opcode) {
2756 switch (Opcode) {
2757 case SETZUCCm:
2758 case SETZUCCr:
2759 return true;
2760 }
2761 return false;
2762}
2763
2764bool isSHUFPD(unsigned Opcode) {
2765 switch (Opcode) {
2766 case SHUFPDrmi:
2767 case SHUFPDrri:
2768 return true;
2769 }
2770 return false;
2771}
2772
2773bool isFCMOVNB(unsigned Opcode) {
2774 return Opcode == CMOVNB_F;
2775}
2776
2777bool isCVTTSS2SI(unsigned Opcode) {
2778 switch (Opcode) {
2779 case CVTTSS2SI64rm_Int:
2780 case CVTTSS2SI64rr_Int:
2781 case CVTTSS2SIrm_Int:
2782 case CVTTSS2SIrr_Int:
2783 return true;
2784 }
2785 return false;
2786}
2787
2788bool isEXTRQ(unsigned Opcode) {
2789 switch (Opcode) {
2790 case EXTRQ:
2791 case EXTRQI:
2792 return true;
2793 }
2794 return false;
2795}
2796
2797bool isVBROADCASTSS(unsigned Opcode) {
2798 switch (Opcode) {
2799 case VBROADCASTSSYrm:
2800 case VBROADCASTSSYrr:
2801 case VBROADCASTSSZ128rm:
2802 case VBROADCASTSSZ128rmk:
2803 case VBROADCASTSSZ128rmkz:
2804 case VBROADCASTSSZ128rr:
2805 case VBROADCASTSSZ128rrk:
2806 case VBROADCASTSSZ128rrkz:
2807 case VBROADCASTSSZ256rm:
2808 case VBROADCASTSSZ256rmk:
2809 case VBROADCASTSSZ256rmkz:
2810 case VBROADCASTSSZ256rr:
2811 case VBROADCASTSSZ256rrk:
2812 case VBROADCASTSSZ256rrkz:
2813 case VBROADCASTSSZrm:
2814 case VBROADCASTSSZrmk:
2815 case VBROADCASTSSZrmkz:
2816 case VBROADCASTSSZrr:
2817 case VBROADCASTSSZrrk:
2818 case VBROADCASTSSZrrkz:
2819 case VBROADCASTSSrm:
2820 case VBROADCASTSSrr:
2821 return true;
2822 }
2823 return false;
2824}
2825
2826bool isCLUI(unsigned Opcode) {
2827 return Opcode == CLUI;
2828}
2829
2830bool isVINSERTI128(unsigned Opcode) {
2831 switch (Opcode) {
2832 case VINSERTI128rmi:
2833 case VINSERTI128rri:
2834 return true;
2835 }
2836 return false;
2837}
2838
2839bool isVPSHLDW(unsigned Opcode) {
2840 switch (Opcode) {
2841 case VPSHLDWZ128rmi:
2842 case VPSHLDWZ128rmik:
2843 case VPSHLDWZ128rmikz:
2844 case VPSHLDWZ128rri:
2845 case VPSHLDWZ128rrik:
2846 case VPSHLDWZ128rrikz:
2847 case VPSHLDWZ256rmi:
2848 case VPSHLDWZ256rmik:
2849 case VPSHLDWZ256rmikz:
2850 case VPSHLDWZ256rri:
2851 case VPSHLDWZ256rrik:
2852 case VPSHLDWZ256rrikz:
2853 case VPSHLDWZrmi:
2854 case VPSHLDWZrmik:
2855 case VPSHLDWZrmikz:
2856 case VPSHLDWZrri:
2857 case VPSHLDWZrrik:
2858 case VPSHLDWZrrikz:
2859 return true;
2860 }
2861 return false;
2862}
2863
2864bool isVBLENDPD(unsigned Opcode) {
2865 switch (Opcode) {
2866 case VBLENDPDYrmi:
2867 case VBLENDPDYrri:
2868 case VBLENDPDrmi:
2869 case VBLENDPDrri:
2870 return true;
2871 }
2872 return false;
2873}
2874
2875bool isVSM4KEY4(unsigned Opcode) {
2876 switch (Opcode) {
2877 case VSM4KEY4Yrm:
2878 case VSM4KEY4Yrr:
2879 case VSM4KEY4Z128rm:
2880 case VSM4KEY4Z128rr:
2881 case VSM4KEY4Z256rm:
2882 case VSM4KEY4Z256rr:
2883 case VSM4KEY4Zrm:
2884 case VSM4KEY4Zrr:
2885 case VSM4KEY4rm:
2886 case VSM4KEY4rr:
2887 return true;
2888 }
2889 return false;
2890}
2891
2892bool isVCVTNEEPH2PS(unsigned Opcode) {
2893 switch (Opcode) {
2894 case VCVTNEEPH2PSYrm:
2895 case VCVTNEEPH2PSrm:
2896 return true;
2897 }
2898 return false;
2899}
2900
2901bool isVCVTTSD2SI(unsigned Opcode) {
2902 switch (Opcode) {
2903 case VCVTTSD2SI64Zrm_Int:
2904 case VCVTTSD2SI64Zrr_Int:
2905 case VCVTTSD2SI64Zrrb_Int:
2906 case VCVTTSD2SI64rm_Int:
2907 case VCVTTSD2SI64rr_Int:
2908 case VCVTTSD2SIZrm_Int:
2909 case VCVTTSD2SIZrr_Int:
2910 case VCVTTSD2SIZrrb_Int:
2911 case VCVTTSD2SIrm_Int:
2912 case VCVTTSD2SIrr_Int:
2913 return true;
2914 }
2915 return false;
2916}
2917
2918bool isWRMSRNS(unsigned Opcode) {
2919 switch (Opcode) {
2920 case WRMSRNS:
2921 case WRMSRNSir:
2922 case WRMSRNSir_EVEX:
2923 return true;
2924 }
2925 return false;
2926}
2927
2928bool isCMPSB(unsigned Opcode) {
2929 return Opcode == CMPSB;
2930}
2931
2932bool isVRCPBF16(unsigned Opcode) {
2933 switch (Opcode) {
2934 case VRCPBF16Z128m:
2935 case VRCPBF16Z128mb:
2936 case VRCPBF16Z128mbk:
2937 case VRCPBF16Z128mbkz:
2938 case VRCPBF16Z128mk:
2939 case VRCPBF16Z128mkz:
2940 case VRCPBF16Z128r:
2941 case VRCPBF16Z128rk:
2942 case VRCPBF16Z128rkz:
2943 case VRCPBF16Z256m:
2944 case VRCPBF16Z256mb:
2945 case VRCPBF16Z256mbk:
2946 case VRCPBF16Z256mbkz:
2947 case VRCPBF16Z256mk:
2948 case VRCPBF16Z256mkz:
2949 case VRCPBF16Z256r:
2950 case VRCPBF16Z256rk:
2951 case VRCPBF16Z256rkz:
2952 case VRCPBF16Zm:
2953 case VRCPBF16Zmb:
2954 case VRCPBF16Zmbk:
2955 case VRCPBF16Zmbkz:
2956 case VRCPBF16Zmk:
2957 case VRCPBF16Zmkz:
2958 case VRCPBF16Zr:
2959 case VRCPBF16Zrk:
2960 case VRCPBF16Zrkz:
2961 return true;
2962 }
2963 return false;
2964}
2965
2966bool isMULSS(unsigned Opcode) {
2967 switch (Opcode) {
2968 case MULSSrm_Int:
2969 case MULSSrr_Int:
2970 return true;
2971 }
2972 return false;
2973}
2974
2975bool isVMRUN(unsigned Opcode) {
2976 switch (Opcode) {
2977 case VMRUN32:
2978 case VMRUN64:
2979 return true;
2980 }
2981 return false;
2982}
2983
2984bool isVPSRLVD(unsigned Opcode) {
2985 switch (Opcode) {
2986 case VPSRLVDYrm:
2987 case VPSRLVDYrr:
2988 case VPSRLVDZ128rm:
2989 case VPSRLVDZ128rmb:
2990 case VPSRLVDZ128rmbk:
2991 case VPSRLVDZ128rmbkz:
2992 case VPSRLVDZ128rmk:
2993 case VPSRLVDZ128rmkz:
2994 case VPSRLVDZ128rr:
2995 case VPSRLVDZ128rrk:
2996 case VPSRLVDZ128rrkz:
2997 case VPSRLVDZ256rm:
2998 case VPSRLVDZ256rmb:
2999 case VPSRLVDZ256rmbk:
3000 case VPSRLVDZ256rmbkz:
3001 case VPSRLVDZ256rmk:
3002 case VPSRLVDZ256rmkz:
3003 case VPSRLVDZ256rr:
3004 case VPSRLVDZ256rrk:
3005 case VPSRLVDZ256rrkz:
3006 case VPSRLVDZrm:
3007 case VPSRLVDZrmb:
3008 case VPSRLVDZrmbk:
3009 case VPSRLVDZrmbkz:
3010 case VPSRLVDZrmk:
3011 case VPSRLVDZrmkz:
3012 case VPSRLVDZrr:
3013 case VPSRLVDZrrk:
3014 case VPSRLVDZrrkz:
3015 case VPSRLVDrm:
3016 case VPSRLVDrr:
3017 return true;
3018 }
3019 return false;
3020}
3021
3022bool isLEAVE(unsigned Opcode) {
3023 switch (Opcode) {
3024 case LEAVE:
3025 case LEAVE64:
3026 return true;
3027 }
3028 return false;
3029}
3030
3031bool isVGETMANTPS(unsigned Opcode) {
3032 switch (Opcode) {
3033 case VGETMANTPSZ128rmbi:
3034 case VGETMANTPSZ128rmbik:
3035 case VGETMANTPSZ128rmbikz:
3036 case VGETMANTPSZ128rmi:
3037 case VGETMANTPSZ128rmik:
3038 case VGETMANTPSZ128rmikz:
3039 case VGETMANTPSZ128rri:
3040 case VGETMANTPSZ128rrik:
3041 case VGETMANTPSZ128rrikz:
3042 case VGETMANTPSZ256rmbi:
3043 case VGETMANTPSZ256rmbik:
3044 case VGETMANTPSZ256rmbikz:
3045 case VGETMANTPSZ256rmi:
3046 case VGETMANTPSZ256rmik:
3047 case VGETMANTPSZ256rmikz:
3048 case VGETMANTPSZ256rri:
3049 case VGETMANTPSZ256rrik:
3050 case VGETMANTPSZ256rrikz:
3051 case VGETMANTPSZrmbi:
3052 case VGETMANTPSZrmbik:
3053 case VGETMANTPSZrmbikz:
3054 case VGETMANTPSZrmi:
3055 case VGETMANTPSZrmik:
3056 case VGETMANTPSZrmikz:
3057 case VGETMANTPSZrri:
3058 case VGETMANTPSZrrib:
3059 case VGETMANTPSZrribk:
3060 case VGETMANTPSZrribkz:
3061 case VGETMANTPSZrrik:
3062 case VGETMANTPSZrrikz:
3063 return true;
3064 }
3065 return false;
3066}
3067
3068bool isXSHA256(unsigned Opcode) {
3069 return Opcode == XSHA256;
3070}
3071
3072bool isBOUND(unsigned Opcode) {
3073 switch (Opcode) {
3074 case BOUNDS16rm:
3075 case BOUNDS32rm:
3076 return true;
3077 }
3078 return false;
3079}
3080
3081bool isSFENCE(unsigned Opcode) {
3082 return Opcode == SFENCE;
3083}
3084
3085bool isVPHADDD(unsigned Opcode) {
3086 switch (Opcode) {
3087 case VPHADDDYrm:
3088 case VPHADDDYrr:
3089 case VPHADDDrm:
3090 case VPHADDDrr:
3091 return true;
3092 }
3093 return false;
3094}
3095
3096bool isADOX(unsigned Opcode) {
3097 switch (Opcode) {
3098 case ADOX32rm:
3099 case ADOX32rm_EVEX:
3100 case ADOX32rm_ND:
3101 case ADOX32rr:
3102 case ADOX32rr_EVEX:
3103 case ADOX32rr_ND:
3104 case ADOX64rm:
3105 case ADOX64rm_EVEX:
3106 case ADOX64rm_ND:
3107 case ADOX64rr:
3108 case ADOX64rr_EVEX:
3109 case ADOX64rr_ND:
3110 return true;
3111 }
3112 return false;
3113}
3114
3115bool isVPSLLQ(unsigned Opcode) {
3116 switch (Opcode) {
3117 case VPSLLQYri:
3118 case VPSLLQYrm:
3119 case VPSLLQYrr:
3120 case VPSLLQZ128mbi:
3121 case VPSLLQZ128mbik:
3122 case VPSLLQZ128mbikz:
3123 case VPSLLQZ128mi:
3124 case VPSLLQZ128mik:
3125 case VPSLLQZ128mikz:
3126 case VPSLLQZ128ri:
3127 case VPSLLQZ128rik:
3128 case VPSLLQZ128rikz:
3129 case VPSLLQZ128rm:
3130 case VPSLLQZ128rmk:
3131 case VPSLLQZ128rmkz:
3132 case VPSLLQZ128rr:
3133 case VPSLLQZ128rrk:
3134 case VPSLLQZ128rrkz:
3135 case VPSLLQZ256mbi:
3136 case VPSLLQZ256mbik:
3137 case VPSLLQZ256mbikz:
3138 case VPSLLQZ256mi:
3139 case VPSLLQZ256mik:
3140 case VPSLLQZ256mikz:
3141 case VPSLLQZ256ri:
3142 case VPSLLQZ256rik:
3143 case VPSLLQZ256rikz:
3144 case VPSLLQZ256rm:
3145 case VPSLLQZ256rmk:
3146 case VPSLLQZ256rmkz:
3147 case VPSLLQZ256rr:
3148 case VPSLLQZ256rrk:
3149 case VPSLLQZ256rrkz:
3150 case VPSLLQZmbi:
3151 case VPSLLQZmbik:
3152 case VPSLLQZmbikz:
3153 case VPSLLQZmi:
3154 case VPSLLQZmik:
3155 case VPSLLQZmikz:
3156 case VPSLLQZri:
3157 case VPSLLQZrik:
3158 case VPSLLQZrikz:
3159 case VPSLLQZrm:
3160 case VPSLLQZrmk:
3161 case VPSLLQZrmkz:
3162 case VPSLLQZrr:
3163 case VPSLLQZrrk:
3164 case VPSLLQZrrkz:
3165 case VPSLLQri:
3166 case VPSLLQrm:
3167 case VPSLLQrr:
3168 return true;
3169 }
3170 return false;
3171}
3172
3173bool isVCVTPH2HF8(unsigned Opcode) {
3174 switch (Opcode) {
3175 case VCVTPH2HF8Z128rm:
3176 case VCVTPH2HF8Z128rmb:
3177 case VCVTPH2HF8Z128rmbk:
3178 case VCVTPH2HF8Z128rmbkz:
3179 case VCVTPH2HF8Z128rmk:
3180 case VCVTPH2HF8Z128rmkz:
3181 case VCVTPH2HF8Z128rr:
3182 case VCVTPH2HF8Z128rrk:
3183 case VCVTPH2HF8Z128rrkz:
3184 case VCVTPH2HF8Z256rm:
3185 case VCVTPH2HF8Z256rmb:
3186 case VCVTPH2HF8Z256rmbk:
3187 case VCVTPH2HF8Z256rmbkz:
3188 case VCVTPH2HF8Z256rmk:
3189 case VCVTPH2HF8Z256rmkz:
3190 case VCVTPH2HF8Z256rr:
3191 case VCVTPH2HF8Z256rrk:
3192 case VCVTPH2HF8Z256rrkz:
3193 case VCVTPH2HF8Zrm:
3194 case VCVTPH2HF8Zrmb:
3195 case VCVTPH2HF8Zrmbk:
3196 case VCVTPH2HF8Zrmbkz:
3197 case VCVTPH2HF8Zrmk:
3198 case VCVTPH2HF8Zrmkz:
3199 case VCVTPH2HF8Zrr:
3200 case VCVTPH2HF8Zrrk:
3201 case VCVTPH2HF8Zrrkz:
3202 return true;
3203 }
3204 return false;
3205}
3206
3207bool isPFRSQIT1(unsigned Opcode) {
3208 switch (Opcode) {
3209 case PFRSQIT1rm:
3210 case PFRSQIT1rr:
3211 return true;
3212 }
3213 return false;
3214}
3215
3216bool isCLAC(unsigned Opcode) {
3217 return Opcode == CLAC;
3218}
3219
3220bool isKNOTW(unsigned Opcode) {
3221 return Opcode == KNOTWkk;
3222}
3223
3224bool isVCVTPH2PD(unsigned Opcode) {
3225 switch (Opcode) {
3226 case VCVTPH2PDZ128rm:
3227 case VCVTPH2PDZ128rmb:
3228 case VCVTPH2PDZ128rmbk:
3229 case VCVTPH2PDZ128rmbkz:
3230 case VCVTPH2PDZ128rmk:
3231 case VCVTPH2PDZ128rmkz:
3232 case VCVTPH2PDZ128rr:
3233 case VCVTPH2PDZ128rrk:
3234 case VCVTPH2PDZ128rrkz:
3235 case VCVTPH2PDZ256rm:
3236 case VCVTPH2PDZ256rmb:
3237 case VCVTPH2PDZ256rmbk:
3238 case VCVTPH2PDZ256rmbkz:
3239 case VCVTPH2PDZ256rmk:
3240 case VCVTPH2PDZ256rmkz:
3241 case VCVTPH2PDZ256rr:
3242 case VCVTPH2PDZ256rrk:
3243 case VCVTPH2PDZ256rrkz:
3244 case VCVTPH2PDZrm:
3245 case VCVTPH2PDZrmb:
3246 case VCVTPH2PDZrmbk:
3247 case VCVTPH2PDZrmbkz:
3248 case VCVTPH2PDZrmk:
3249 case VCVTPH2PDZrmkz:
3250 case VCVTPH2PDZrr:
3251 case VCVTPH2PDZrrb:
3252 case VCVTPH2PDZrrbk:
3253 case VCVTPH2PDZrrbkz:
3254 case VCVTPH2PDZrrk:
3255 case VCVTPH2PDZrrkz:
3256 return true;
3257 }
3258 return false;
3259}
3260
3261bool isVAESENC(unsigned Opcode) {
3262 switch (Opcode) {
3263 case VAESENCYrm:
3264 case VAESENCYrr:
3265 case VAESENCZ128rm:
3266 case VAESENCZ128rr:
3267 case VAESENCZ256rm:
3268 case VAESENCZ256rr:
3269 case VAESENCZrm:
3270 case VAESENCZrr:
3271 case VAESENCrm:
3272 case VAESENCrr:
3273 return true;
3274 }
3275 return false;
3276}
3277
3278bool isMOVNTI(unsigned Opcode) {
3279 switch (Opcode) {
3280 case MOVNTI_64mr:
3281 case MOVNTImr:
3282 return true;
3283 }
3284 return false;
3285}
3286
3287bool isFXCH(unsigned Opcode) {
3288 return Opcode == XCH_F;
3289}
3290
3291bool isPOPP(unsigned Opcode) {
3292 return Opcode == POPP64r;
3293}
3294
3295bool isVPBLENDMD(unsigned Opcode) {
3296 switch (Opcode) {
3297 case VPBLENDMDZ128rm:
3298 case VPBLENDMDZ128rmb:
3299 case VPBLENDMDZ128rmbk:
3300 case VPBLENDMDZ128rmbkz:
3301 case VPBLENDMDZ128rmk:
3302 case VPBLENDMDZ128rmkz:
3303 case VPBLENDMDZ128rr:
3304 case VPBLENDMDZ128rrk:
3305 case VPBLENDMDZ128rrkz:
3306 case VPBLENDMDZ256rm:
3307 case VPBLENDMDZ256rmb:
3308 case VPBLENDMDZ256rmbk:
3309 case VPBLENDMDZ256rmbkz:
3310 case VPBLENDMDZ256rmk:
3311 case VPBLENDMDZ256rmkz:
3312 case VPBLENDMDZ256rr:
3313 case VPBLENDMDZ256rrk:
3314 case VPBLENDMDZ256rrkz:
3315 case VPBLENDMDZrm:
3316 case VPBLENDMDZrmb:
3317 case VPBLENDMDZrmbk:
3318 case VPBLENDMDZrmbkz:
3319 case VPBLENDMDZrmk:
3320 case VPBLENDMDZrmkz:
3321 case VPBLENDMDZrr:
3322 case VPBLENDMDZrrk:
3323 case VPBLENDMDZrrkz:
3324 return true;
3325 }
3326 return false;
3327}
3328
3329bool isFSINCOS(unsigned Opcode) {
3330 return Opcode == FSINCOS;
3331}
3332
3333bool isVPMOVSXBW(unsigned Opcode) {
3334 switch (Opcode) {
3335 case VPMOVSXBWYrm:
3336 case VPMOVSXBWYrr:
3337 case VPMOVSXBWZ128rm:
3338 case VPMOVSXBWZ128rmk:
3339 case VPMOVSXBWZ128rmkz:
3340 case VPMOVSXBWZ128rr:
3341 case VPMOVSXBWZ128rrk:
3342 case VPMOVSXBWZ128rrkz:
3343 case VPMOVSXBWZ256rm:
3344 case VPMOVSXBWZ256rmk:
3345 case VPMOVSXBWZ256rmkz:
3346 case VPMOVSXBWZ256rr:
3347 case VPMOVSXBWZ256rrk:
3348 case VPMOVSXBWZ256rrkz:
3349 case VPMOVSXBWZrm:
3350 case VPMOVSXBWZrmk:
3351 case VPMOVSXBWZrmkz:
3352 case VPMOVSXBWZrr:
3353 case VPMOVSXBWZrrk:
3354 case VPMOVSXBWZrrkz:
3355 case VPMOVSXBWrm:
3356 case VPMOVSXBWrr:
3357 return true;
3358 }
3359 return false;
3360}
3361
3362bool isVPMULLW(unsigned Opcode) {
3363 switch (Opcode) {
3364 case VPMULLWYrm:
3365 case VPMULLWYrr:
3366 case VPMULLWZ128rm:
3367 case VPMULLWZ128rmk:
3368 case VPMULLWZ128rmkz:
3369 case VPMULLWZ128rr:
3370 case VPMULLWZ128rrk:
3371 case VPMULLWZ128rrkz:
3372 case VPMULLWZ256rm:
3373 case VPMULLWZ256rmk:
3374 case VPMULLWZ256rmkz:
3375 case VPMULLWZ256rr:
3376 case VPMULLWZ256rrk:
3377 case VPMULLWZ256rrkz:
3378 case VPMULLWZrm:
3379 case VPMULLWZrmk:
3380 case VPMULLWZrmkz:
3381 case VPMULLWZrr:
3382 case VPMULLWZrrk:
3383 case VPMULLWZrrkz:
3384 case VPMULLWrm:
3385 case VPMULLWrr:
3386 return true;
3387 }
3388 return false;
3389}
3390
3391bool isSTC(unsigned Opcode) {
3392 return Opcode == STC;
3393}
3394
3395bool isVPINSRB(unsigned Opcode) {
3396 switch (Opcode) {
3397 case VPINSRBZrmi:
3398 case VPINSRBZrri:
3399 case VPINSRBrmi:
3400 case VPINSRBrri:
3401 return true;
3402 }
3403 return false;
3404}
3405
3406bool isLWPVAL(unsigned Opcode) {
3407 switch (Opcode) {
3408 case LWPVAL32rmi:
3409 case LWPVAL32rri:
3410 case LWPVAL64rmi:
3411 case LWPVAL64rri:
3412 return true;
3413 }
3414 return false;
3415}
3416
3417bool isKXORB(unsigned Opcode) {
3418 return Opcode == KXORBkk;
3419}
3420
3421bool isRSTORSSP(unsigned Opcode) {
3422 return Opcode == RSTORSSP;
3423}
3424
3425bool isVPRORQ(unsigned Opcode) {
3426 switch (Opcode) {
3427 case VPRORQZ128mbi:
3428 case VPRORQZ128mbik:
3429 case VPRORQZ128mbikz:
3430 case VPRORQZ128mi:
3431 case VPRORQZ128mik:
3432 case VPRORQZ128mikz:
3433 case VPRORQZ128ri:
3434 case VPRORQZ128rik:
3435 case VPRORQZ128rikz:
3436 case VPRORQZ256mbi:
3437 case VPRORQZ256mbik:
3438 case VPRORQZ256mbikz:
3439 case VPRORQZ256mi:
3440 case VPRORQZ256mik:
3441 case VPRORQZ256mikz:
3442 case VPRORQZ256ri:
3443 case VPRORQZ256rik:
3444 case VPRORQZ256rikz:
3445 case VPRORQZmbi:
3446 case VPRORQZmbik:
3447 case VPRORQZmbikz:
3448 case VPRORQZmi:
3449 case VPRORQZmik:
3450 case VPRORQZmikz:
3451 case VPRORQZri:
3452 case VPRORQZrik:
3453 case VPRORQZrikz:
3454 return true;
3455 }
3456 return false;
3457}
3458
3459bool isVSM3MSG1(unsigned Opcode) {
3460 switch (Opcode) {
3461 case VSM3MSG1rm:
3462 case VSM3MSG1rr:
3463 return true;
3464 }
3465 return false;
3466}
3467
3468bool isFICOM(unsigned Opcode) {
3469 switch (Opcode) {
3470 case FICOM16m:
3471 case FICOM32m:
3472 return true;
3473 }
3474 return false;
3475}
3476
3477bool isMAXPS(unsigned Opcode) {
3478 switch (Opcode) {
3479 case MAXPSrm:
3480 case MAXPSrr:
3481 return true;
3482 }
3483 return false;
3484}
3485
3486bool isFNCLEX(unsigned Opcode) {
3487 return Opcode == FNCLEX;
3488}
3489
3490bool isVMOVMSKPS(unsigned Opcode) {
3491 switch (Opcode) {
3492 case VMOVMSKPSYrr:
3493 case VMOVMSKPSrr:
3494 return true;
3495 }
3496 return false;
3497}
3498
3499bool isVPMOVDB(unsigned Opcode) {
3500 switch (Opcode) {
3501 case VPMOVDBZ128mr:
3502 case VPMOVDBZ128mrk:
3503 case VPMOVDBZ128rr:
3504 case VPMOVDBZ128rrk:
3505 case VPMOVDBZ128rrkz:
3506 case VPMOVDBZ256mr:
3507 case VPMOVDBZ256mrk:
3508 case VPMOVDBZ256rr:
3509 case VPMOVDBZ256rrk:
3510 case VPMOVDBZ256rrkz:
3511 case VPMOVDBZmr:
3512 case VPMOVDBZmrk:
3513 case VPMOVDBZrr:
3514 case VPMOVDBZrrk:
3515 case VPMOVDBZrrkz:
3516 return true;
3517 }
3518 return false;
3519}
3520
3521bool isLLWPCB(unsigned Opcode) {
3522 switch (Opcode) {
3523 case LLWPCB:
3524 case LLWPCB64:
3525 return true;
3526 }
3527 return false;
3528}
3529
3530bool isVMULSS(unsigned Opcode) {
3531 switch (Opcode) {
3532 case VMULSSZrm_Int:
3533 case VMULSSZrmk_Int:
3534 case VMULSSZrmkz_Int:
3535 case VMULSSZrr_Int:
3536 case VMULSSZrrb_Int:
3537 case VMULSSZrrbk_Int:
3538 case VMULSSZrrbkz_Int:
3539 case VMULSSZrrk_Int:
3540 case VMULSSZrrkz_Int:
3541 case VMULSSrm_Int:
3542 case VMULSSrr_Int:
3543 return true;
3544 }
3545 return false;
3546}
3547
3548bool isAESENCLAST(unsigned Opcode) {
3549 switch (Opcode) {
3550 case AESENCLASTrm:
3551 case AESENCLASTrr:
3552 return true;
3553 }
3554 return false;
3555}
3556
3557bool isTILEMOVROW(unsigned Opcode) {
3558 switch (Opcode) {
3559 case TILEMOVROWrte:
3560 case TILEMOVROWrti:
3561 return true;
3562 }
3563 return false;
3564}
3565
3566bool isVMINMAXPH(unsigned Opcode) {
3567 switch (Opcode) {
3568 case VMINMAXPHZ128rmbi:
3569 case VMINMAXPHZ128rmbik:
3570 case VMINMAXPHZ128rmbikz:
3571 case VMINMAXPHZ128rmi:
3572 case VMINMAXPHZ128rmik:
3573 case VMINMAXPHZ128rmikz:
3574 case VMINMAXPHZ128rri:
3575 case VMINMAXPHZ128rrik:
3576 case VMINMAXPHZ128rrikz:
3577 case VMINMAXPHZ256rmbi:
3578 case VMINMAXPHZ256rmbik:
3579 case VMINMAXPHZ256rmbikz:
3580 case VMINMAXPHZ256rmi:
3581 case VMINMAXPHZ256rmik:
3582 case VMINMAXPHZ256rmikz:
3583 case VMINMAXPHZ256rri:
3584 case VMINMAXPHZ256rrik:
3585 case VMINMAXPHZ256rrikz:
3586 case VMINMAXPHZrmbi:
3587 case VMINMAXPHZrmbik:
3588 case VMINMAXPHZrmbikz:
3589 case VMINMAXPHZrmi:
3590 case VMINMAXPHZrmik:
3591 case VMINMAXPHZrmikz:
3592 case VMINMAXPHZrri:
3593 case VMINMAXPHZrrib:
3594 case VMINMAXPHZrribk:
3595 case VMINMAXPHZrribkz:
3596 case VMINMAXPHZrrik:
3597 case VMINMAXPHZrrikz:
3598 return true;
3599 }
3600 return false;
3601}
3602
3603bool isVPMAXUB(unsigned Opcode) {
3604 switch (Opcode) {
3605 case VPMAXUBYrm:
3606 case VPMAXUBYrr:
3607 case VPMAXUBZ128rm:
3608 case VPMAXUBZ128rmk:
3609 case VPMAXUBZ128rmkz:
3610 case VPMAXUBZ128rr:
3611 case VPMAXUBZ128rrk:
3612 case VPMAXUBZ128rrkz:
3613 case VPMAXUBZ256rm:
3614 case VPMAXUBZ256rmk:
3615 case VPMAXUBZ256rmkz:
3616 case VPMAXUBZ256rr:
3617 case VPMAXUBZ256rrk:
3618 case VPMAXUBZ256rrkz:
3619 case VPMAXUBZrm:
3620 case VPMAXUBZrmk:
3621 case VPMAXUBZrmkz:
3622 case VPMAXUBZrr:
3623 case VPMAXUBZrrk:
3624 case VPMAXUBZrrkz:
3625 case VPMAXUBrm:
3626 case VPMAXUBrr:
3627 return true;
3628 }
3629 return false;
3630}
3631
3632bool isAAS(unsigned Opcode) {
3633 return Opcode == AAS;
3634}
3635
3636bool isFADD(unsigned Opcode) {
3637 switch (Opcode) {
3638 case ADD_F32m:
3639 case ADD_F64m:
3640 case ADD_FST0r:
3641 case ADD_FrST0:
3642 return true;
3643 }
3644 return false;
3645}
3646
3647bool isJMP(unsigned Opcode) {
3648 switch (Opcode) {
3649 case FARJMP32m:
3650 case JMP16m:
3651 case JMP16r:
3652 case JMP32m:
3653 case JMP32r:
3654 case JMP64m:
3655 case JMP64r:
3656 case JMP_1:
3657 case JMP_2:
3658 case JMP_4:
3659 return true;
3660 }
3661 return false;
3662}
3663
3664bool isXCRYPTECB(unsigned Opcode) {
3665 return Opcode == XCRYPTECB;
3666}
3667
3668bool isPFRCPIT1(unsigned Opcode) {
3669 switch (Opcode) {
3670 case PFRCPIT1rm:
3671 case PFRCPIT1rr:
3672 return true;
3673 }
3674 return false;
3675}
3676
3677bool isPMULHRW(unsigned Opcode) {
3678 switch (Opcode) {
3679 case PMULHRWrm:
3680 case PMULHRWrr:
3681 return true;
3682 }
3683 return false;
3684}
3685
3686bool isVCVTPH2PS(unsigned Opcode) {
3687 switch (Opcode) {
3688 case VCVTPH2PSYrm:
3689 case VCVTPH2PSYrr:
3690 case VCVTPH2PSZ128rm:
3691 case VCVTPH2PSZ128rmk:
3692 case VCVTPH2PSZ128rmkz:
3693 case VCVTPH2PSZ128rr:
3694 case VCVTPH2PSZ128rrk:
3695 case VCVTPH2PSZ128rrkz:
3696 case VCVTPH2PSZ256rm:
3697 case VCVTPH2PSZ256rmk:
3698 case VCVTPH2PSZ256rmkz:
3699 case VCVTPH2PSZ256rr:
3700 case VCVTPH2PSZ256rrk:
3701 case VCVTPH2PSZ256rrkz:
3702 case VCVTPH2PSZrm:
3703 case VCVTPH2PSZrmk:
3704 case VCVTPH2PSZrmkz:
3705 case VCVTPH2PSZrr:
3706 case VCVTPH2PSZrrb:
3707 case VCVTPH2PSZrrbk:
3708 case VCVTPH2PSZrrbkz:
3709 case VCVTPH2PSZrrk:
3710 case VCVTPH2PSZrrkz:
3711 case VCVTPH2PSrm:
3712 case VCVTPH2PSrr:
3713 return true;
3714 }
3715 return false;
3716}
3717
3718bool isVPBLENDVB(unsigned Opcode) {
3719 switch (Opcode) {
3720 case VPBLENDVBYrmr:
3721 case VPBLENDVBYrrr:
3722 case VPBLENDVBrmr:
3723 case VPBLENDVBrrr:
3724 return true;
3725 }
3726 return false;
3727}
3728
3729bool isPCMPESTRI(unsigned Opcode) {
3730 switch (Opcode) {
3731 case PCMPESTRIrmi:
3732 case PCMPESTRIrri:
3733 return true;
3734 }
3735 return false;
3736}
3737
3738bool isSENDUIPI(unsigned Opcode) {
3739 return Opcode == SENDUIPI;
3740}
3741
3742bool isFLDLN2(unsigned Opcode) {
3743 return Opcode == FLDLN2;
3744}
3745
3746bool isVPMACSWD(unsigned Opcode) {
3747 switch (Opcode) {
3748 case VPMACSWDrm:
3749 case VPMACSWDrr:
3750 return true;
3751 }
3752 return false;
3753}
3754
3755bool isSHA1MSG1(unsigned Opcode) {
3756 switch (Opcode) {
3757 case SHA1MSG1rm:
3758 case SHA1MSG1rr:
3759 return true;
3760 }
3761 return false;
3762}
3763
3764bool isVADDPS(unsigned Opcode) {
3765 switch (Opcode) {
3766 case VADDPSYrm:
3767 case VADDPSYrr:
3768 case VADDPSZ128rm:
3769 case VADDPSZ128rmb:
3770 case VADDPSZ128rmbk:
3771 case VADDPSZ128rmbkz:
3772 case VADDPSZ128rmk:
3773 case VADDPSZ128rmkz:
3774 case VADDPSZ128rr:
3775 case VADDPSZ128rrk:
3776 case VADDPSZ128rrkz:
3777 case VADDPSZ256rm:
3778 case VADDPSZ256rmb:
3779 case VADDPSZ256rmbk:
3780 case VADDPSZ256rmbkz:
3781 case VADDPSZ256rmk:
3782 case VADDPSZ256rmkz:
3783 case VADDPSZ256rr:
3784 case VADDPSZ256rrk:
3785 case VADDPSZ256rrkz:
3786 case VADDPSZrm:
3787 case VADDPSZrmb:
3788 case VADDPSZrmbk:
3789 case VADDPSZrmbkz:
3790 case VADDPSZrmk:
3791 case VADDPSZrmkz:
3792 case VADDPSZrr:
3793 case VADDPSZrrb:
3794 case VADDPSZrrbk:
3795 case VADDPSZrrbkz:
3796 case VADDPSZrrk:
3797 case VADDPSZrrkz:
3798 case VADDPSrm:
3799 case VADDPSrr:
3800 return true;
3801 }
3802 return false;
3803}
3804
3805bool isVCVTPS2DQ(unsigned Opcode) {
3806 switch (Opcode) {
3807 case VCVTPS2DQYrm:
3808 case VCVTPS2DQYrr:
3809 case VCVTPS2DQZ128rm:
3810 case VCVTPS2DQZ128rmb:
3811 case VCVTPS2DQZ128rmbk:
3812 case VCVTPS2DQZ128rmbkz:
3813 case VCVTPS2DQZ128rmk:
3814 case VCVTPS2DQZ128rmkz:
3815 case VCVTPS2DQZ128rr:
3816 case VCVTPS2DQZ128rrk:
3817 case VCVTPS2DQZ128rrkz:
3818 case VCVTPS2DQZ256rm:
3819 case VCVTPS2DQZ256rmb:
3820 case VCVTPS2DQZ256rmbk:
3821 case VCVTPS2DQZ256rmbkz:
3822 case VCVTPS2DQZ256rmk:
3823 case VCVTPS2DQZ256rmkz:
3824 case VCVTPS2DQZ256rr:
3825 case VCVTPS2DQZ256rrk:
3826 case VCVTPS2DQZ256rrkz:
3827 case VCVTPS2DQZrm:
3828 case VCVTPS2DQZrmb:
3829 case VCVTPS2DQZrmbk:
3830 case VCVTPS2DQZrmbkz:
3831 case VCVTPS2DQZrmk:
3832 case VCVTPS2DQZrmkz:
3833 case VCVTPS2DQZrr:
3834 case VCVTPS2DQZrrb:
3835 case VCVTPS2DQZrrbk:
3836 case VCVTPS2DQZrrbkz:
3837 case VCVTPS2DQZrrk:
3838 case VCVTPS2DQZrrkz:
3839 case VCVTPS2DQrm:
3840 case VCVTPS2DQrr:
3841 return true;
3842 }
3843 return false;
3844}
3845
3846bool isPFPNACC(unsigned Opcode) {
3847 switch (Opcode) {
3848 case PFPNACCrm:
3849 case PFPNACCrr:
3850 return true;
3851 }
3852 return false;
3853}
3854
3855bool isFMUL(unsigned Opcode) {
3856 switch (Opcode) {
3857 case MUL_F32m:
3858 case MUL_F64m:
3859 case MUL_FST0r:
3860 case MUL_FrST0:
3861 return true;
3862 }
3863 return false;
3864}
3865
3866bool isFNSAVE(unsigned Opcode) {
3867 return Opcode == FSAVEm;
3868}
3869
3870bool isCDQE(unsigned Opcode) {
3871 return Opcode == CDQE;
3872}
3873
3874bool isVPMACSDD(unsigned Opcode) {
3875 switch (Opcode) {
3876 case VPMACSDDrm:
3877 case VPMACSDDrr:
3878 return true;
3879 }
3880 return false;
3881}
3882
3883bool isVSQRTPS(unsigned Opcode) {
3884 switch (Opcode) {
3885 case VSQRTPSYm:
3886 case VSQRTPSYr:
3887 case VSQRTPSZ128m:
3888 case VSQRTPSZ128mb:
3889 case VSQRTPSZ128mbk:
3890 case VSQRTPSZ128mbkz:
3891 case VSQRTPSZ128mk:
3892 case VSQRTPSZ128mkz:
3893 case VSQRTPSZ128r:
3894 case VSQRTPSZ128rk:
3895 case VSQRTPSZ128rkz:
3896 case VSQRTPSZ256m:
3897 case VSQRTPSZ256mb:
3898 case VSQRTPSZ256mbk:
3899 case VSQRTPSZ256mbkz:
3900 case VSQRTPSZ256mk:
3901 case VSQRTPSZ256mkz:
3902 case VSQRTPSZ256r:
3903 case VSQRTPSZ256rk:
3904 case VSQRTPSZ256rkz:
3905 case VSQRTPSZm:
3906 case VSQRTPSZmb:
3907 case VSQRTPSZmbk:
3908 case VSQRTPSZmbkz:
3909 case VSQRTPSZmk:
3910 case VSQRTPSZmkz:
3911 case VSQRTPSZr:
3912 case VSQRTPSZrb:
3913 case VSQRTPSZrbk:
3914 case VSQRTPSZrbkz:
3915 case VSQRTPSZrk:
3916 case VSQRTPSZrkz:
3917 case VSQRTPSm:
3918 case VSQRTPSr:
3919 return true;
3920 }
3921 return false;
3922}
3923
3924bool isCMPSQ(unsigned Opcode) {
3925 return Opcode == CMPSQ;
3926}
3927
3928bool isVPSCATTERDD(unsigned Opcode) {
3929 switch (Opcode) {
3930 case VPSCATTERDDZ128mr:
3931 case VPSCATTERDDZ256mr:
3932 case VPSCATTERDDZmr:
3933 return true;
3934 }
3935 return false;
3936}
3937
3938bool isVCVTTSD2USIS(unsigned Opcode) {
3939 switch (Opcode) {
3940 case VCVTTSD2USI64Srm_Int:
3941 case VCVTTSD2USI64Srr_Int:
3942 case VCVTTSD2USI64Srrb_Int:
3943 case VCVTTSD2USISrm_Int:
3944 case VCVTTSD2USISrr_Int:
3945 case VCVTTSD2USISrrb_Int:
3946 return true;
3947 }
3948 return false;
3949}
3950
3951bool isVRNDSCALESD(unsigned Opcode) {
3952 switch (Opcode) {
3953 case VRNDSCALESDZrmi_Int:
3954 case VRNDSCALESDZrmik_Int:
3955 case VRNDSCALESDZrmikz_Int:
3956 case VRNDSCALESDZrri_Int:
3957 case VRNDSCALESDZrrib_Int:
3958 case VRNDSCALESDZrribk_Int:
3959 case VRNDSCALESDZrribkz_Int:
3960 case VRNDSCALESDZrrik_Int:
3961 case VRNDSCALESDZrrikz_Int:
3962 return true;
3963 }
3964 return false;
3965}
3966
3967bool isSUBPS(unsigned Opcode) {
3968 switch (Opcode) {
3969 case SUBPSrm:
3970 case SUBPSrr:
3971 return true;
3972 }
3973 return false;
3974}
3975
3976bool isVMAXSH(unsigned Opcode) {
3977 switch (Opcode) {
3978 case VMAXSHZrm_Int:
3979 case VMAXSHZrmk_Int:
3980 case VMAXSHZrmkz_Int:
3981 case VMAXSHZrr_Int:
3982 case VMAXSHZrrb_Int:
3983 case VMAXSHZrrbk_Int:
3984 case VMAXSHZrrbkz_Int:
3985 case VMAXSHZrrk_Int:
3986 case VMAXSHZrrkz_Int:
3987 return true;
3988 }
3989 return false;
3990}
3991
3992bool isFLDZ(unsigned Opcode) {
3993 return Opcode == LD_F0;
3994}
3995
3996bool isVFNMADD132SS(unsigned Opcode) {
3997 switch (Opcode) {
3998 case VFNMADD132SSZm_Int:
3999 case VFNMADD132SSZmk_Int:
4000 case VFNMADD132SSZmkz_Int:
4001 case VFNMADD132SSZr_Int:
4002 case VFNMADD132SSZrb_Int:
4003 case VFNMADD132SSZrbk_Int:
4004 case VFNMADD132SSZrbkz_Int:
4005 case VFNMADD132SSZrk_Int:
4006 case VFNMADD132SSZrkz_Int:
4007 case VFNMADD132SSm_Int:
4008 case VFNMADD132SSr_Int:
4009 return true;
4010 }
4011 return false;
4012}
4013
4014bool isLGDTW(unsigned Opcode) {
4015 return Opcode == LGDT16m;
4016}
4017
4018bool isTCVTROWPS2PHH(unsigned Opcode) {
4019 switch (Opcode) {
4020 case TCVTROWPS2PHHrte:
4021 case TCVTROWPS2PHHrti:
4022 return true;
4023 }
4024 return false;
4025}
4026
4027bool isINC(unsigned Opcode) {
4028 switch (Opcode) {
4029 case INC16m:
4030 case INC16m_EVEX:
4031 case INC16m_ND:
4032 case INC16m_NF:
4033 case INC16m_NF_ND:
4034 case INC16r:
4035 case INC16r_EVEX:
4036 case INC16r_ND:
4037 case INC16r_NF:
4038 case INC16r_NF_ND:
4039 case INC16r_alt:
4040 case INC32m:
4041 case INC32m_EVEX:
4042 case INC32m_ND:
4043 case INC32m_NF:
4044 case INC32m_NF_ND:
4045 case INC32r:
4046 case INC32r_EVEX:
4047 case INC32r_ND:
4048 case INC32r_NF:
4049 case INC32r_NF_ND:
4050 case INC32r_alt:
4051 case INC64m:
4052 case INC64m_EVEX:
4053 case INC64m_ND:
4054 case INC64m_NF:
4055 case INC64m_NF_ND:
4056 case INC64r:
4057 case INC64r_EVEX:
4058 case INC64r_ND:
4059 case INC64r_NF:
4060 case INC64r_NF_ND:
4061 case INC8m:
4062 case INC8m_EVEX:
4063 case INC8m_ND:
4064 case INC8m_NF:
4065 case INC8m_NF_ND:
4066 case INC8r:
4067 case INC8r_EVEX:
4068 case INC8r_ND:
4069 case INC8r_NF:
4070 case INC8r_NF_ND:
4071 return true;
4072 }
4073 return false;
4074}
4075
4076bool isPABSB(unsigned Opcode) {
4077 switch (Opcode) {
4078 case MMX_PABSBrm:
4079 case MMX_PABSBrr:
4080 case PABSBrm:
4081 case PABSBrr:
4082 return true;
4083 }
4084 return false;
4085}
4086
4087bool isVCVTROPS2HF8S(unsigned Opcode) {
4088 switch (Opcode) {
4089 case VCVTROPS2HF8SZ128rm:
4090 case VCVTROPS2HF8SZ128rmb:
4091 case VCVTROPS2HF8SZ128rmbk:
4092 case VCVTROPS2HF8SZ128rmbkz:
4093 case VCVTROPS2HF8SZ128rmk:
4094 case VCVTROPS2HF8SZ128rmkz:
4095 case VCVTROPS2HF8SZ128rr:
4096 case VCVTROPS2HF8SZ128rrk:
4097 case VCVTROPS2HF8SZ128rrkz:
4098 case VCVTROPS2HF8SZ256rm:
4099 case VCVTROPS2HF8SZ256rmb:
4100 case VCVTROPS2HF8SZ256rmbk:
4101 case VCVTROPS2HF8SZ256rmbkz:
4102 case VCVTROPS2HF8SZ256rmk:
4103 case VCVTROPS2HF8SZ256rmkz:
4104 case VCVTROPS2HF8SZ256rr:
4105 case VCVTROPS2HF8SZ256rrk:
4106 case VCVTROPS2HF8SZ256rrkz:
4107 case VCVTROPS2HF8SZrm:
4108 case VCVTROPS2HF8SZrmb:
4109 case VCVTROPS2HF8SZrmbk:
4110 case VCVTROPS2HF8SZrmbkz:
4111 case VCVTROPS2HF8SZrmk:
4112 case VCVTROPS2HF8SZrmkz:
4113 case VCVTROPS2HF8SZrr:
4114 case VCVTROPS2HF8SZrrk:
4115 case VCVTROPS2HF8SZrrkz:
4116 return true;
4117 }
4118 return false;
4119}
4120
4121bool isVPANDN(unsigned Opcode) {
4122 switch (Opcode) {
4123 case VPANDNYrm:
4124 case VPANDNYrr:
4125 case VPANDNrm:
4126 case VPANDNrr:
4127 return true;
4128 }
4129 return false;
4130}
4131
4132bool isVCVTHF82HF6S(unsigned Opcode) {
4133 switch (Opcode) {
4134 case VCVTHF82HF6SZ128rr:
4135 case VCVTHF82HF6SZ256rr:
4136 case VCVTHF82HF6SZrr:
4137 return true;
4138 }
4139 return false;
4140}
4141
4142bool isPHADDSW(unsigned Opcode) {
4143 switch (Opcode) {
4144 case MMX_PHADDSWrm:
4145 case MMX_PHADDSWrr:
4146 case PHADDSWrm:
4147 case PHADDSWrr:
4148 return true;
4149 }
4150 return false;
4151}
4152
4153bool isVPMAXUD(unsigned Opcode) {
4154 switch (Opcode) {
4155 case VPMAXUDYrm:
4156 case VPMAXUDYrr:
4157 case VPMAXUDZ128rm:
4158 case VPMAXUDZ128rmb:
4159 case VPMAXUDZ128rmbk:
4160 case VPMAXUDZ128rmbkz:
4161 case VPMAXUDZ128rmk:
4162 case VPMAXUDZ128rmkz:
4163 case VPMAXUDZ128rr:
4164 case VPMAXUDZ128rrk:
4165 case VPMAXUDZ128rrkz:
4166 case VPMAXUDZ256rm:
4167 case VPMAXUDZ256rmb:
4168 case VPMAXUDZ256rmbk:
4169 case VPMAXUDZ256rmbkz:
4170 case VPMAXUDZ256rmk:
4171 case VPMAXUDZ256rmkz:
4172 case VPMAXUDZ256rr:
4173 case VPMAXUDZ256rrk:
4174 case VPMAXUDZ256rrkz:
4175 case VPMAXUDZrm:
4176 case VPMAXUDZrmb:
4177 case VPMAXUDZrmbk:
4178 case VPMAXUDZrmbkz:
4179 case VPMAXUDZrmk:
4180 case VPMAXUDZrmkz:
4181 case VPMAXUDZrr:
4182 case VPMAXUDZrrk:
4183 case VPMAXUDZrrkz:
4184 case VPMAXUDrm:
4185 case VPMAXUDrr:
4186 return true;
4187 }
4188 return false;
4189}
4190
4191bool isVPMOVSQW(unsigned Opcode) {
4192 switch (Opcode) {
4193 case VPMOVSQWZ128mr:
4194 case VPMOVSQWZ128mrk:
4195 case VPMOVSQWZ128rr:
4196 case VPMOVSQWZ128rrk:
4197 case VPMOVSQWZ128rrkz:
4198 case VPMOVSQWZ256mr:
4199 case VPMOVSQWZ256mrk:
4200 case VPMOVSQWZ256rr:
4201 case VPMOVSQWZ256rrk:
4202 case VPMOVSQWZ256rrkz:
4203 case VPMOVSQWZmr:
4204 case VPMOVSQWZmrk:
4205 case VPMOVSQWZrr:
4206 case VPMOVSQWZrrk:
4207 case VPMOVSQWZrrkz:
4208 return true;
4209 }
4210 return false;
4211}
4212
4213bool isVSHA512RNDS2(unsigned Opcode) {
4214 return Opcode == VSHA512RNDS2rr;
4215}
4216
4217bool isADDSUBPS(unsigned Opcode) {
4218 switch (Opcode) {
4219 case ADDSUBPSrm:
4220 case ADDSUBPSrr:
4221 return true;
4222 }
4223 return false;
4224}
4225
4226bool isVPMACSSDQL(unsigned Opcode) {
4227 switch (Opcode) {
4228 case VPMACSSDQLrm:
4229 case VPMACSSDQLrr:
4230 return true;
4231 }
4232 return false;
4233}
4234
4235bool isPXOR(unsigned Opcode) {
4236 switch (Opcode) {
4237 case MMX_PXORrm:
4238 case MMX_PXORrr:
4239 case PXORrm:
4240 case PXORrr:
4241 return true;
4242 }
4243 return false;
4244}
4245
4246bool isVPSRAD(unsigned Opcode) {
4247 switch (Opcode) {
4248 case VPSRADYri:
4249 case VPSRADYrm:
4250 case VPSRADYrr:
4251 case VPSRADZ128mbi:
4252 case VPSRADZ128mbik:
4253 case VPSRADZ128mbikz:
4254 case VPSRADZ128mi:
4255 case VPSRADZ128mik:
4256 case VPSRADZ128mikz:
4257 case VPSRADZ128ri:
4258 case VPSRADZ128rik:
4259 case VPSRADZ128rikz:
4260 case VPSRADZ128rm:
4261 case VPSRADZ128rmk:
4262 case VPSRADZ128rmkz:
4263 case VPSRADZ128rr:
4264 case VPSRADZ128rrk:
4265 case VPSRADZ128rrkz:
4266 case VPSRADZ256mbi:
4267 case VPSRADZ256mbik:
4268 case VPSRADZ256mbikz:
4269 case VPSRADZ256mi:
4270 case VPSRADZ256mik:
4271 case VPSRADZ256mikz:
4272 case VPSRADZ256ri:
4273 case VPSRADZ256rik:
4274 case VPSRADZ256rikz:
4275 case VPSRADZ256rm:
4276 case VPSRADZ256rmk:
4277 case VPSRADZ256rmkz:
4278 case VPSRADZ256rr:
4279 case VPSRADZ256rrk:
4280 case VPSRADZ256rrkz:
4281 case VPSRADZmbi:
4282 case VPSRADZmbik:
4283 case VPSRADZmbikz:
4284 case VPSRADZmi:
4285 case VPSRADZmik:
4286 case VPSRADZmikz:
4287 case VPSRADZri:
4288 case VPSRADZrik:
4289 case VPSRADZrikz:
4290 case VPSRADZrm:
4291 case VPSRADZrmk:
4292 case VPSRADZrmkz:
4293 case VPSRADZrr:
4294 case VPSRADZrrk:
4295 case VPSRADZrrkz:
4296 case VPSRADri:
4297 case VPSRADrm:
4298 case VPSRADrr:
4299 return true;
4300 }
4301 return false;
4302}
4303
4304bool isVPSHAB(unsigned Opcode) {
4305 switch (Opcode) {
4306 case VPSHABmr:
4307 case VPSHABrm:
4308 case VPSHABrr:
4309 case VPSHABrr_REV:
4310 return true;
4311 }
4312 return false;
4313}
4314
4315bool isBTR(unsigned Opcode) {
4316 switch (Opcode) {
4317 case BTR16mi8:
4318 case BTR16mr:
4319 case BTR16ri8:
4320 case BTR16rr:
4321 case BTR32mi8:
4322 case BTR32mr:
4323 case BTR32ri8:
4324 case BTR32rr:
4325 case BTR64mi8:
4326 case BTR64mr:
4327 case BTR64ri8:
4328 case BTR64rr:
4329 return true;
4330 }
4331 return false;
4332}
4333
4334bool isKORW(unsigned Opcode) {
4335 return Opcode == KORWkk;
4336}
4337
4338bool isVRANGESS(unsigned Opcode) {
4339 switch (Opcode) {
4340 case VRANGESSZrmi:
4341 case VRANGESSZrmik:
4342 case VRANGESSZrmikz:
4343 case VRANGESSZrri:
4344 case VRANGESSZrrib:
4345 case VRANGESSZrribk:
4346 case VRANGESSZrribkz:
4347 case VRANGESSZrrik:
4348 case VRANGESSZrrikz:
4349 return true;
4350 }
4351 return false;
4352}
4353
4354bool isVCMPPS(unsigned Opcode) {
4355 switch (Opcode) {
4356 case VCMPPSYrmi:
4357 case VCMPPSYrri:
4358 case VCMPPSZ128rmbi:
4359 case VCMPPSZ128rmbik:
4360 case VCMPPSZ128rmi:
4361 case VCMPPSZ128rmik:
4362 case VCMPPSZ128rri:
4363 case VCMPPSZ128rrik:
4364 case VCMPPSZ256rmbi:
4365 case VCMPPSZ256rmbik:
4366 case VCMPPSZ256rmi:
4367 case VCMPPSZ256rmik:
4368 case VCMPPSZ256rri:
4369 case VCMPPSZ256rrik:
4370 case VCMPPSZrmbi:
4371 case VCMPPSZrmbik:
4372 case VCMPPSZrmi:
4373 case VCMPPSZrmik:
4374 case VCMPPSZrri:
4375 case VCMPPSZrrib:
4376 case VCMPPSZrribk:
4377 case VCMPPSZrrik:
4378 case VCMPPSrmi:
4379 case VCMPPSrri:
4380 return true;
4381 }
4382 return false;
4383}
4384
4385bool isVPLZCNTD(unsigned Opcode) {
4386 switch (Opcode) {
4387 case VPLZCNTDZ128rm:
4388 case VPLZCNTDZ128rmb:
4389 case VPLZCNTDZ128rmbk:
4390 case VPLZCNTDZ128rmbkz:
4391 case VPLZCNTDZ128rmk:
4392 case VPLZCNTDZ128rmkz:
4393 case VPLZCNTDZ128rr:
4394 case VPLZCNTDZ128rrk:
4395 case VPLZCNTDZ128rrkz:
4396 case VPLZCNTDZ256rm:
4397 case VPLZCNTDZ256rmb:
4398 case VPLZCNTDZ256rmbk:
4399 case VPLZCNTDZ256rmbkz:
4400 case VPLZCNTDZ256rmk:
4401 case VPLZCNTDZ256rmkz:
4402 case VPLZCNTDZ256rr:
4403 case VPLZCNTDZ256rrk:
4404 case VPLZCNTDZ256rrkz:
4405 case VPLZCNTDZrm:
4406 case VPLZCNTDZrmb:
4407 case VPLZCNTDZrmbk:
4408 case VPLZCNTDZrmbkz:
4409 case VPLZCNTDZrmk:
4410 case VPLZCNTDZrmkz:
4411 case VPLZCNTDZrr:
4412 case VPLZCNTDZrrk:
4413 case VPLZCNTDZrrkz:
4414 return true;
4415 }
4416 return false;
4417}
4418
4419bool isTDPBUUD(unsigned Opcode) {
4420 return Opcode == TDPBUUD;
4421}
4422
4423bool isROUNDPS(unsigned Opcode) {
4424 switch (Opcode) {
4425 case ROUNDPSmi:
4426 case ROUNDPSri:
4427 return true;
4428 }
4429 return false;
4430}
4431
4432bool isFABS(unsigned Opcode) {
4433 return Opcode == ABS_F;
4434}
4435
4436bool isSUBPD(unsigned Opcode) {
4437 switch (Opcode) {
4438 case SUBPDrm:
4439 case SUBPDrr:
4440 return true;
4441 }
4442 return false;
4443}
4444
4445bool isGF2P8MULB(unsigned Opcode) {
4446 switch (Opcode) {
4447 case GF2P8MULBrm:
4448 case GF2P8MULBrr:
4449 return true;
4450 }
4451 return false;
4452}
4453
4454bool isTZMSK(unsigned Opcode) {
4455 switch (Opcode) {
4456 case TZMSK32rm:
4457 case TZMSK32rr:
4458 case TZMSK64rm:
4459 case TZMSK64rr:
4460 return true;
4461 }
4462 return false;
4463}
4464
4465bool isVMINMAXSD(unsigned Opcode) {
4466 switch (Opcode) {
4467 case VMINMAXSDrmi_Int:
4468 case VMINMAXSDrmik_Int:
4469 case VMINMAXSDrmikz_Int:
4470 case VMINMAXSDrri_Int:
4471 case VMINMAXSDrrib_Int:
4472 case VMINMAXSDrribk_Int:
4473 case VMINMAXSDrribkz_Int:
4474 case VMINMAXSDrrik_Int:
4475 case VMINMAXSDrrikz_Int:
4476 return true;
4477 }
4478 return false;
4479}
4480
4481bool isANDPS(unsigned Opcode) {
4482 switch (Opcode) {
4483 case ANDPSrm:
4484 case ANDPSrr:
4485 return true;
4486 }
4487 return false;
4488}
4489
4490bool isVEXTRACTF32X8(unsigned Opcode) {
4491 switch (Opcode) {
4492 case VEXTRACTF32X8Zmri:
4493 case VEXTRACTF32X8Zmrik:
4494 case VEXTRACTF32X8Zrri:
4495 case VEXTRACTF32X8Zrrik:
4496 case VEXTRACTF32X8Zrrikz:
4497 return true;
4498 }
4499 return false;
4500}
4501
4502bool isSEAMRET(unsigned Opcode) {
4503 return Opcode == SEAMRET;
4504}
4505
4506bool isVPCOMW(unsigned Opcode) {
4507 switch (Opcode) {
4508 case VPCOMWmi:
4509 case VPCOMWri:
4510 return true;
4511 }
4512 return false;
4513}
4514
4515bool isVFIXUPIMMPD(unsigned Opcode) {
4516 switch (Opcode) {
4517 case VFIXUPIMMPDZ128rmbi:
4518 case VFIXUPIMMPDZ128rmbik:
4519 case VFIXUPIMMPDZ128rmbikz:
4520 case VFIXUPIMMPDZ128rmi:
4521 case VFIXUPIMMPDZ128rmik:
4522 case VFIXUPIMMPDZ128rmikz:
4523 case VFIXUPIMMPDZ128rri:
4524 case VFIXUPIMMPDZ128rrik:
4525 case VFIXUPIMMPDZ128rrikz:
4526 case VFIXUPIMMPDZ256rmbi:
4527 case VFIXUPIMMPDZ256rmbik:
4528 case VFIXUPIMMPDZ256rmbikz:
4529 case VFIXUPIMMPDZ256rmi:
4530 case VFIXUPIMMPDZ256rmik:
4531 case VFIXUPIMMPDZ256rmikz:
4532 case VFIXUPIMMPDZ256rri:
4533 case VFIXUPIMMPDZ256rrik:
4534 case VFIXUPIMMPDZ256rrikz:
4535 case VFIXUPIMMPDZrmbi:
4536 case VFIXUPIMMPDZrmbik:
4537 case VFIXUPIMMPDZrmbikz:
4538 case VFIXUPIMMPDZrmi:
4539 case VFIXUPIMMPDZrmik:
4540 case VFIXUPIMMPDZrmikz:
4541 case VFIXUPIMMPDZrri:
4542 case VFIXUPIMMPDZrrib:
4543 case VFIXUPIMMPDZrribk:
4544 case VFIXUPIMMPDZrribkz:
4545 case VFIXUPIMMPDZrrik:
4546 case VFIXUPIMMPDZrrikz:
4547 return true;
4548 }
4549 return false;
4550}
4551
4552bool isKANDND(unsigned Opcode) {
4553 return Opcode == KANDNDkk;
4554}
4555
4556bool isVMRESUME(unsigned Opcode) {
4557 return Opcode == VMRESUME;
4558}
4559
4560bool isCVTPD2DQ(unsigned Opcode) {
4561 switch (Opcode) {
4562 case CVTPD2DQrm:
4563 case CVTPD2DQrr:
4564 return true;
4565 }
4566 return false;
4567}
4568
4569bool isVFNMADD213PS(unsigned Opcode) {
4570 switch (Opcode) {
4571 case VFNMADD213PSYm:
4572 case VFNMADD213PSYr:
4573 case VFNMADD213PSZ128m:
4574 case VFNMADD213PSZ128mb:
4575 case VFNMADD213PSZ128mbk:
4576 case VFNMADD213PSZ128mbkz:
4577 case VFNMADD213PSZ128mk:
4578 case VFNMADD213PSZ128mkz:
4579 case VFNMADD213PSZ128r:
4580 case VFNMADD213PSZ128rk:
4581 case VFNMADD213PSZ128rkz:
4582 case VFNMADD213PSZ256m:
4583 case VFNMADD213PSZ256mb:
4584 case VFNMADD213PSZ256mbk:
4585 case VFNMADD213PSZ256mbkz:
4586 case VFNMADD213PSZ256mk:
4587 case VFNMADD213PSZ256mkz:
4588 case VFNMADD213PSZ256r:
4589 case VFNMADD213PSZ256rk:
4590 case VFNMADD213PSZ256rkz:
4591 case VFNMADD213PSZm:
4592 case VFNMADD213PSZmb:
4593 case VFNMADD213PSZmbk:
4594 case VFNMADD213PSZmbkz:
4595 case VFNMADD213PSZmk:
4596 case VFNMADD213PSZmkz:
4597 case VFNMADD213PSZr:
4598 case VFNMADD213PSZrb:
4599 case VFNMADD213PSZrbk:
4600 case VFNMADD213PSZrbkz:
4601 case VFNMADD213PSZrk:
4602 case VFNMADD213PSZrkz:
4603 case VFNMADD213PSm:
4604 case VFNMADD213PSr:
4605 return true;
4606 }
4607 return false;
4608}
4609
4610bool isVPEXTRD(unsigned Opcode) {
4611 switch (Opcode) {
4612 case VPEXTRDZmri:
4613 case VPEXTRDZrri:
4614 case VPEXTRDmri:
4615 case VPEXTRDrri:
4616 return true;
4617 }
4618 return false;
4619}
4620
4621bool isPACKUSWB(unsigned Opcode) {
4622 switch (Opcode) {
4623 case MMX_PACKUSWBrm:
4624 case MMX_PACKUSWBrr:
4625 case PACKUSWBrm:
4626 case PACKUSWBrr:
4627 return true;
4628 }
4629 return false;
4630}
4631
4632bool isVEXTRACTI32X8(unsigned Opcode) {
4633 switch (Opcode) {
4634 case VEXTRACTI32X8Zmri:
4635 case VEXTRACTI32X8Zmrik:
4636 case VEXTRACTI32X8Zrri:
4637 case VEXTRACTI32X8Zrrik:
4638 case VEXTRACTI32X8Zrrikz:
4639 return true;
4640 }
4641 return false;
4642}
4643
4644bool isVHADDPD(unsigned Opcode) {
4645 switch (Opcode) {
4646 case VHADDPDYrm:
4647 case VHADDPDYrr:
4648 case VHADDPDrm:
4649 case VHADDPDrr:
4650 return true;
4651 }
4652 return false;
4653}
4654
4655bool isVPSADBW(unsigned Opcode) {
4656 switch (Opcode) {
4657 case VPSADBWYrm:
4658 case VPSADBWYrr:
4659 case VPSADBWZ128rm:
4660 case VPSADBWZ128rr:
4661 case VPSADBWZ256rm:
4662 case VPSADBWZ256rr:
4663 case VPSADBWZrm:
4664 case VPSADBWZrr:
4665 case VPSADBWrm:
4666 case VPSADBWrr:
4667 return true;
4668 }
4669 return false;
4670}
4671
4672bool isMOVDQ2Q(unsigned Opcode) {
4673 return Opcode == MMX_MOVDQ2Qrr;
4674}
4675
4676bool isPUNPCKHBW(unsigned Opcode) {
4677 switch (Opcode) {
4678 case MMX_PUNPCKHBWrm:
4679 case MMX_PUNPCKHBWrr:
4680 case PUNPCKHBWrm:
4681 case PUNPCKHBWrr:
4682 return true;
4683 }
4684 return false;
4685}
4686
4687bool isXOR(unsigned Opcode) {
4688 switch (Opcode) {
4689 case XOR16i16:
4690 case XOR16mi:
4691 case XOR16mi8:
4692 case XOR16mi8_EVEX:
4693 case XOR16mi8_ND:
4694 case XOR16mi8_NF:
4695 case XOR16mi8_NF_ND:
4696 case XOR16mi_EVEX:
4697 case XOR16mi_ND:
4698 case XOR16mi_NF:
4699 case XOR16mi_NF_ND:
4700 case XOR16mr:
4701 case XOR16mr_EVEX:
4702 case XOR16mr_ND:
4703 case XOR16mr_NF:
4704 case XOR16mr_NF_ND:
4705 case XOR16ri:
4706 case XOR16ri8:
4707 case XOR16ri8_EVEX:
4708 case XOR16ri8_ND:
4709 case XOR16ri8_NF:
4710 case XOR16ri8_NF_ND:
4711 case XOR16ri_EVEX:
4712 case XOR16ri_ND:
4713 case XOR16ri_NF:
4714 case XOR16ri_NF_ND:
4715 case XOR16rm:
4716 case XOR16rm_EVEX:
4717 case XOR16rm_ND:
4718 case XOR16rm_NF:
4719 case XOR16rm_NF_ND:
4720 case XOR16rr:
4721 case XOR16rr_EVEX:
4722 case XOR16rr_EVEX_REV:
4723 case XOR16rr_ND:
4724 case XOR16rr_ND_REV:
4725 case XOR16rr_NF:
4726 case XOR16rr_NF_ND:
4727 case XOR16rr_NF_ND_REV:
4728 case XOR16rr_NF_REV:
4729 case XOR16rr_REV:
4730 case XOR32i32:
4731 case XOR32mi:
4732 case XOR32mi8:
4733 case XOR32mi8_EVEX:
4734 case XOR32mi8_ND:
4735 case XOR32mi8_NF:
4736 case XOR32mi8_NF_ND:
4737 case XOR32mi_EVEX:
4738 case XOR32mi_ND:
4739 case XOR32mi_NF:
4740 case XOR32mi_NF_ND:
4741 case XOR32mr:
4742 case XOR32mr_EVEX:
4743 case XOR32mr_ND:
4744 case XOR32mr_NF:
4745 case XOR32mr_NF_ND:
4746 case XOR32ri:
4747 case XOR32ri8:
4748 case XOR32ri8_EVEX:
4749 case XOR32ri8_ND:
4750 case XOR32ri8_NF:
4751 case XOR32ri8_NF_ND:
4752 case XOR32ri_EVEX:
4753 case XOR32ri_ND:
4754 case XOR32ri_NF:
4755 case XOR32ri_NF_ND:
4756 case XOR32rm:
4757 case XOR32rm_EVEX:
4758 case XOR32rm_ND:
4759 case XOR32rm_NF:
4760 case XOR32rm_NF_ND:
4761 case XOR32rr:
4762 case XOR32rr_EVEX:
4763 case XOR32rr_EVEX_REV:
4764 case XOR32rr_ND:
4765 case XOR32rr_ND_REV:
4766 case XOR32rr_NF:
4767 case XOR32rr_NF_ND:
4768 case XOR32rr_NF_ND_REV:
4769 case XOR32rr_NF_REV:
4770 case XOR32rr_REV:
4771 case XOR64i32:
4772 case XOR64mi32:
4773 case XOR64mi32_EVEX:
4774 case XOR64mi32_ND:
4775 case XOR64mi32_NF:
4776 case XOR64mi32_NF_ND:
4777 case XOR64mi8:
4778 case XOR64mi8_EVEX:
4779 case XOR64mi8_ND:
4780 case XOR64mi8_NF:
4781 case XOR64mi8_NF_ND:
4782 case XOR64mr:
4783 case XOR64mr_EVEX:
4784 case XOR64mr_ND:
4785 case XOR64mr_NF:
4786 case XOR64mr_NF_ND:
4787 case XOR64ri32:
4788 case XOR64ri32_EVEX:
4789 case XOR64ri32_ND:
4790 case XOR64ri32_NF:
4791 case XOR64ri32_NF_ND:
4792 case XOR64ri8:
4793 case XOR64ri8_EVEX:
4794 case XOR64ri8_ND:
4795 case XOR64ri8_NF:
4796 case XOR64ri8_NF_ND:
4797 case XOR64rm:
4798 case XOR64rm_EVEX:
4799 case XOR64rm_ND:
4800 case XOR64rm_NF:
4801 case XOR64rm_NF_ND:
4802 case XOR64rr:
4803 case XOR64rr_EVEX:
4804 case XOR64rr_EVEX_REV:
4805 case XOR64rr_ND:
4806 case XOR64rr_ND_REV:
4807 case XOR64rr_NF:
4808 case XOR64rr_NF_ND:
4809 case XOR64rr_NF_ND_REV:
4810 case XOR64rr_NF_REV:
4811 case XOR64rr_REV:
4812 case XOR8i8:
4813 case XOR8mi:
4814 case XOR8mi8:
4815 case XOR8mi_EVEX:
4816 case XOR8mi_ND:
4817 case XOR8mi_NF:
4818 case XOR8mi_NF_ND:
4819 case XOR8mr:
4820 case XOR8mr_EVEX:
4821 case XOR8mr_ND:
4822 case XOR8mr_NF:
4823 case XOR8mr_NF_ND:
4824 case XOR8ri:
4825 case XOR8ri8:
4826 case XOR8ri_EVEX:
4827 case XOR8ri_ND:
4828 case XOR8ri_NF:
4829 case XOR8ri_NF_ND:
4830 case XOR8rm:
4831 case XOR8rm_EVEX:
4832 case XOR8rm_ND:
4833 case XOR8rm_NF:
4834 case XOR8rm_NF_ND:
4835 case XOR8rr:
4836 case XOR8rr_EVEX:
4837 case XOR8rr_EVEX_REV:
4838 case XOR8rr_ND:
4839 case XOR8rr_ND_REV:
4840 case XOR8rr_NF:
4841 case XOR8rr_NF_ND:
4842 case XOR8rr_NF_ND_REV:
4843 case XOR8rr_NF_REV:
4844 case XOR8rr_REV:
4845 return true;
4846 }
4847 return false;
4848}
4849
4850bool isPSIGNB(unsigned Opcode) {
4851 switch (Opcode) {
4852 case MMX_PSIGNBrm:
4853 case MMX_PSIGNBrr:
4854 case PSIGNBrm:
4855 case PSIGNBrr:
4856 return true;
4857 }
4858 return false;
4859}
4860
4861bool isVPHADDSW(unsigned Opcode) {
4862 switch (Opcode) {
4863 case VPHADDSWYrm:
4864 case VPHADDSWYrr:
4865 case VPHADDSWrm:
4866 case VPHADDSWrr:
4867 return true;
4868 }
4869 return false;
4870}
4871
4872bool isFADDP(unsigned Opcode) {
4873 return Opcode == ADD_FPrST0;
4874}
4875
4876bool isNEG(unsigned Opcode) {
4877 switch (Opcode) {
4878 case NEG16m:
4879 case NEG16m_EVEX:
4880 case NEG16m_ND:
4881 case NEG16m_NF:
4882 case NEG16m_NF_ND:
4883 case NEG16r:
4884 case NEG16r_EVEX:
4885 case NEG16r_ND:
4886 case NEG16r_NF:
4887 case NEG16r_NF_ND:
4888 case NEG32m:
4889 case NEG32m_EVEX:
4890 case NEG32m_ND:
4891 case NEG32m_NF:
4892 case NEG32m_NF_ND:
4893 case NEG32r:
4894 case NEG32r_EVEX:
4895 case NEG32r_ND:
4896 case NEG32r_NF:
4897 case NEG32r_NF_ND:
4898 case NEG64m:
4899 case NEG64m_EVEX:
4900 case NEG64m_ND:
4901 case NEG64m_NF:
4902 case NEG64m_NF_ND:
4903 case NEG64r:
4904 case NEG64r_EVEX:
4905 case NEG64r_ND:
4906 case NEG64r_NF:
4907 case NEG64r_NF_ND:
4908 case NEG8m:
4909 case NEG8m_EVEX:
4910 case NEG8m_ND:
4911 case NEG8m_NF:
4912 case NEG8m_NF_ND:
4913 case NEG8r:
4914 case NEG8r_EVEX:
4915 case NEG8r_ND:
4916 case NEG8r_NF:
4917 case NEG8r_NF_ND:
4918 return true;
4919 }
4920 return false;
4921}
4922
4923bool isFLDLG2(unsigned Opcode) {
4924 return Opcode == FLDLG2;
4925}
4926
4927bool isFNOP(unsigned Opcode) {
4928 return Opcode == FNOP;
4929}
4930
4931bool isVMINSS(unsigned Opcode) {
4932 switch (Opcode) {
4933 case VMINSSZrm_Int:
4934 case VMINSSZrmk_Int:
4935 case VMINSSZrmkz_Int:
4936 case VMINSSZrr_Int:
4937 case VMINSSZrrb_Int:
4938 case VMINSSZrrbk_Int:
4939 case VMINSSZrrbkz_Int:
4940 case VMINSSZrrk_Int:
4941 case VMINSSZrrkz_Int:
4942 case VMINSSrm_Int:
4943 case VMINSSrr_Int:
4944 return true;
4945 }
4946 return false;
4947}
4948
4949bool isPCMPISTRM(unsigned Opcode) {
4950 switch (Opcode) {
4951 case PCMPISTRMrmi:
4952 case PCMPISTRMrri:
4953 return true;
4954 }
4955 return false;
4956}
4957
4958bool isVFMADD132SS(unsigned Opcode) {
4959 switch (Opcode) {
4960 case VFMADD132SSZm_Int:
4961 case VFMADD132SSZmk_Int:
4962 case VFMADD132SSZmkz_Int:
4963 case VFMADD132SSZr_Int:
4964 case VFMADD132SSZrb_Int:
4965 case VFMADD132SSZrbk_Int:
4966 case VFMADD132SSZrbkz_Int:
4967 case VFMADD132SSZrk_Int:
4968 case VFMADD132SSZrkz_Int:
4969 case VFMADD132SSm_Int:
4970 case VFMADD132SSr_Int:
4971 return true;
4972 }
4973 return false;
4974}
4975
4976bool isFDIVRP(unsigned Opcode) {
4977 return Opcode == DIVR_FPrST0;
4978}
4979
4980bool isPUSHAL(unsigned Opcode) {
4981 return Opcode == PUSHA32;
4982}
4983
4984bool isSUBSD(unsigned Opcode) {
4985 switch (Opcode) {
4986 case SUBSDrm_Int:
4987 case SUBSDrr_Int:
4988 return true;
4989 }
4990 return false;
4991}
4992
4993bool isVPBLENDMQ(unsigned Opcode) {
4994 switch (Opcode) {
4995 case VPBLENDMQZ128rm:
4996 case VPBLENDMQZ128rmb:
4997 case VPBLENDMQZ128rmbk:
4998 case VPBLENDMQZ128rmbkz:
4999 case VPBLENDMQZ128rmk:
5000 case VPBLENDMQZ128rmkz:
5001 case VPBLENDMQZ128rr:
5002 case VPBLENDMQZ128rrk:
5003 case VPBLENDMQZ128rrkz:
5004 case VPBLENDMQZ256rm:
5005 case VPBLENDMQZ256rmb:
5006 case VPBLENDMQZ256rmbk:
5007 case VPBLENDMQZ256rmbkz:
5008 case VPBLENDMQZ256rmk:
5009 case VPBLENDMQZ256rmkz:
5010 case VPBLENDMQZ256rr:
5011 case VPBLENDMQZ256rrk:
5012 case VPBLENDMQZ256rrkz:
5013 case VPBLENDMQZrm:
5014 case VPBLENDMQZrmb:
5015 case VPBLENDMQZrmbk:
5016 case VPBLENDMQZrmbkz:
5017 case VPBLENDMQZrmk:
5018 case VPBLENDMQZrmkz:
5019 case VPBLENDMQZrr:
5020 case VPBLENDMQZrrk:
5021 case VPBLENDMQZrrkz:
5022 return true;
5023 }
5024 return false;
5025}
5026
5027bool isVPMACSDQL(unsigned Opcode) {
5028 switch (Opcode) {
5029 case VPMACSDQLrm:
5030 case VPMACSDQLrr:
5031 return true;
5032 }
5033 return false;
5034}
5035
5036bool isVGATHERDPS(unsigned Opcode) {
5037 switch (Opcode) {
5038 case VGATHERDPSYrm:
5039 case VGATHERDPSZ128rm:
5040 case VGATHERDPSZ256rm:
5041 case VGATHERDPSZrm:
5042 case VGATHERDPSrm:
5043 return true;
5044 }
5045 return false;
5046}
5047
5048bool isRMPREAD(unsigned Opcode) {
5049 return Opcode == RMPREAD;
5050}
5051
5052bool isSYSRET(unsigned Opcode) {
5053 return Opcode == SYSRET;
5054}
5055
5056bool isVPADDB(unsigned Opcode) {
5057 switch (Opcode) {
5058 case VPADDBYrm:
5059 case VPADDBYrr:
5060 case VPADDBZ128rm:
5061 case VPADDBZ128rmk:
5062 case VPADDBZ128rmkz:
5063 case VPADDBZ128rr:
5064 case VPADDBZ128rrk:
5065 case VPADDBZ128rrkz:
5066 case VPADDBZ256rm:
5067 case VPADDBZ256rmk:
5068 case VPADDBZ256rmkz:
5069 case VPADDBZ256rr:
5070 case VPADDBZ256rrk:
5071 case VPADDBZ256rrkz:
5072 case VPADDBZrm:
5073 case VPADDBZrmk:
5074 case VPADDBZrmkz:
5075 case VPADDBZrr:
5076 case VPADDBZrrk:
5077 case VPADDBZrrkz:
5078 case VPADDBrm:
5079 case VPADDBrr:
5080 return true;
5081 }
5082 return false;
5083}
5084
5085bool isXEND(unsigned Opcode) {
5086 return Opcode == XEND;
5087}
5088
5089bool isWRSSD(unsigned Opcode) {
5090 switch (Opcode) {
5091 case WRSSD:
5092 case WRSSD_EVEX:
5093 return true;
5094 }
5095 return false;
5096}
5097
5098bool isVMINMAXSS(unsigned Opcode) {
5099 switch (Opcode) {
5100 case VMINMAXSSrmi_Int:
5101 case VMINMAXSSrmik_Int:
5102 case VMINMAXSSrmikz_Int:
5103 case VMINMAXSSrri_Int:
5104 case VMINMAXSSrrib_Int:
5105 case VMINMAXSSrribk_Int:
5106 case VMINMAXSSrribkz_Int:
5107 case VMINMAXSSrrik_Int:
5108 case VMINMAXSSrrikz_Int:
5109 return true;
5110 }
5111 return false;
5112}
5113
5114bool isVCVTDQ2PH(unsigned Opcode) {
5115 switch (Opcode) {
5116 case VCVTDQ2PHZ128rm:
5117 case VCVTDQ2PHZ128rmb:
5118 case VCVTDQ2PHZ128rmbk:
5119 case VCVTDQ2PHZ128rmbkz:
5120 case VCVTDQ2PHZ128rmk:
5121 case VCVTDQ2PHZ128rmkz:
5122 case VCVTDQ2PHZ128rr:
5123 case VCVTDQ2PHZ128rrk:
5124 case VCVTDQ2PHZ128rrkz:
5125 case VCVTDQ2PHZ256rm:
5126 case VCVTDQ2PHZ256rmb:
5127 case VCVTDQ2PHZ256rmbk:
5128 case VCVTDQ2PHZ256rmbkz:
5129 case VCVTDQ2PHZ256rmk:
5130 case VCVTDQ2PHZ256rmkz:
5131 case VCVTDQ2PHZ256rr:
5132 case VCVTDQ2PHZ256rrk:
5133 case VCVTDQ2PHZ256rrkz:
5134 case VCVTDQ2PHZrm:
5135 case VCVTDQ2PHZrmb:
5136 case VCVTDQ2PHZrmbk:
5137 case VCVTDQ2PHZrmbkz:
5138 case VCVTDQ2PHZrmk:
5139 case VCVTDQ2PHZrmkz:
5140 case VCVTDQ2PHZrr:
5141 case VCVTDQ2PHZrrb:
5142 case VCVTDQ2PHZrrbk:
5143 case VCVTDQ2PHZrrbkz:
5144 case VCVTDQ2PHZrrk:
5145 case VCVTDQ2PHZrrkz:
5146 return true;
5147 }
5148 return false;
5149}
5150
5151bool isCVTPD2PS(unsigned Opcode) {
5152 switch (Opcode) {
5153 case CVTPD2PSrm:
5154 case CVTPD2PSrr:
5155 return true;
5156 }
5157 return false;
5158}
5159
5160bool isMAXPD(unsigned Opcode) {
5161 switch (Opcode) {
5162 case MAXPDrm:
5163 case MAXPDrr:
5164 return true;
5165 }
5166 return false;
5167}
5168
5169bool isRCPSS(unsigned Opcode) {
5170 switch (Opcode) {
5171 case RCPSSm_Int:
5172 case RCPSSr_Int:
5173 return true;
5174 }
5175 return false;
5176}
5177
5178bool isVMOVAPD(unsigned Opcode) {
5179 switch (Opcode) {
5180 case VMOVAPDYmr:
5181 case VMOVAPDYrm:
5182 case VMOVAPDYrr:
5183 case VMOVAPDYrr_REV:
5184 case VMOVAPDZ128mr:
5185 case VMOVAPDZ128mrk:
5186 case VMOVAPDZ128rm:
5187 case VMOVAPDZ128rmk:
5188 case VMOVAPDZ128rmkz:
5189 case VMOVAPDZ128rr:
5190 case VMOVAPDZ128rr_REV:
5191 case VMOVAPDZ128rrk:
5192 case VMOVAPDZ128rrk_REV:
5193 case VMOVAPDZ128rrkz:
5194 case VMOVAPDZ128rrkz_REV:
5195 case VMOVAPDZ256mr:
5196 case VMOVAPDZ256mrk:
5197 case VMOVAPDZ256rm:
5198 case VMOVAPDZ256rmk:
5199 case VMOVAPDZ256rmkz:
5200 case VMOVAPDZ256rr:
5201 case VMOVAPDZ256rr_REV:
5202 case VMOVAPDZ256rrk:
5203 case VMOVAPDZ256rrk_REV:
5204 case VMOVAPDZ256rrkz:
5205 case VMOVAPDZ256rrkz_REV:
5206 case VMOVAPDZmr:
5207 case VMOVAPDZmrk:
5208 case VMOVAPDZrm:
5209 case VMOVAPDZrmk:
5210 case VMOVAPDZrmkz:
5211 case VMOVAPDZrr:
5212 case VMOVAPDZrr_REV:
5213 case VMOVAPDZrrk:
5214 case VMOVAPDZrrk_REV:
5215 case VMOVAPDZrrkz:
5216 case VMOVAPDZrrkz_REV:
5217 case VMOVAPDmr:
5218 case VMOVAPDrm:
5219 case VMOVAPDrr:
5220 case VMOVAPDrr_REV:
5221 return true;
5222 }
5223 return false;
5224}
5225
5226bool isVPSUBSB(unsigned Opcode) {
5227 switch (Opcode) {
5228 case VPSUBSBYrm:
5229 case VPSUBSBYrr:
5230 case VPSUBSBZ128rm:
5231 case VPSUBSBZ128rmk:
5232 case VPSUBSBZ128rmkz:
5233 case VPSUBSBZ128rr:
5234 case VPSUBSBZ128rrk:
5235 case VPSUBSBZ128rrkz:
5236 case VPSUBSBZ256rm:
5237 case VPSUBSBZ256rmk:
5238 case VPSUBSBZ256rmkz:
5239 case VPSUBSBZ256rr:
5240 case VPSUBSBZ256rrk:
5241 case VPSUBSBZ256rrkz:
5242 case VPSUBSBZrm:
5243 case VPSUBSBZrmk:
5244 case VPSUBSBZrmkz:
5245 case VPSUBSBZrr:
5246 case VPSUBSBZrrk:
5247 case VPSUBSBZrrkz:
5248 case VPSUBSBrm:
5249 case VPSUBSBrr:
5250 return true;
5251 }
5252 return false;
5253}
5254
5255bool isRDTSC(unsigned Opcode) {
5256 return Opcode == RDTSC;
5257}
5258
5259bool isVCVTTPS2UDQS(unsigned Opcode) {
5260 switch (Opcode) {
5261 case VCVTTPS2UDQSZ128rm:
5262 case VCVTTPS2UDQSZ128rmb:
5263 case VCVTTPS2UDQSZ128rmbk:
5264 case VCVTTPS2UDQSZ128rmbkz:
5265 case VCVTTPS2UDQSZ128rmk:
5266 case VCVTTPS2UDQSZ128rmkz:
5267 case VCVTTPS2UDQSZ128rr:
5268 case VCVTTPS2UDQSZ128rrk:
5269 case VCVTTPS2UDQSZ128rrkz:
5270 case VCVTTPS2UDQSZ256rm:
5271 case VCVTTPS2UDQSZ256rmb:
5272 case VCVTTPS2UDQSZ256rmbk:
5273 case VCVTTPS2UDQSZ256rmbkz:
5274 case VCVTTPS2UDQSZ256rmk:
5275 case VCVTTPS2UDQSZ256rmkz:
5276 case VCVTTPS2UDQSZ256rr:
5277 case VCVTTPS2UDQSZ256rrk:
5278 case VCVTTPS2UDQSZ256rrkz:
5279 case VCVTTPS2UDQSZrm:
5280 case VCVTTPS2UDQSZrmb:
5281 case VCVTTPS2UDQSZrmbk:
5282 case VCVTTPS2UDQSZrmbkz:
5283 case VCVTTPS2UDQSZrmk:
5284 case VCVTTPS2UDQSZrmkz:
5285 case VCVTTPS2UDQSZrr:
5286 case VCVTTPS2UDQSZrrb:
5287 case VCVTTPS2UDQSZrrbk:
5288 case VCVTTPS2UDQSZrrbkz:
5289 case VCVTTPS2UDQSZrrk:
5290 case VCVTTPS2UDQSZrrkz:
5291 return true;
5292 }
5293 return false;
5294}
5295
5296bool isVPMADCSSWD(unsigned Opcode) {
5297 switch (Opcode) {
5298 case VPMADCSSWDrm:
5299 case VPMADCSSWDrr:
5300 return true;
5301 }
5302 return false;
5303}
5304
5305bool isVFNMADD213PH(unsigned Opcode) {
5306 switch (Opcode) {
5307 case VFNMADD213PHZ128m:
5308 case VFNMADD213PHZ128mb:
5309 case VFNMADD213PHZ128mbk:
5310 case VFNMADD213PHZ128mbkz:
5311 case VFNMADD213PHZ128mk:
5312 case VFNMADD213PHZ128mkz:
5313 case VFNMADD213PHZ128r:
5314 case VFNMADD213PHZ128rk:
5315 case VFNMADD213PHZ128rkz:
5316 case VFNMADD213PHZ256m:
5317 case VFNMADD213PHZ256mb:
5318 case VFNMADD213PHZ256mbk:
5319 case VFNMADD213PHZ256mbkz:
5320 case VFNMADD213PHZ256mk:
5321 case VFNMADD213PHZ256mkz:
5322 case VFNMADD213PHZ256r:
5323 case VFNMADD213PHZ256rk:
5324 case VFNMADD213PHZ256rkz:
5325 case VFNMADD213PHZm:
5326 case VFNMADD213PHZmb:
5327 case VFNMADD213PHZmbk:
5328 case VFNMADD213PHZmbkz:
5329 case VFNMADD213PHZmk:
5330 case VFNMADD213PHZmkz:
5331 case VFNMADD213PHZr:
5332 case VFNMADD213PHZrb:
5333 case VFNMADD213PHZrbk:
5334 case VFNMADD213PHZrbkz:
5335 case VFNMADD213PHZrk:
5336 case VFNMADD213PHZrkz:
5337 return true;
5338 }
5339 return false;
5340}
5341
5342bool isVGF2P8AFFINEQB(unsigned Opcode) {
5343 switch (Opcode) {
5344 case VGF2P8AFFINEQBYrmi:
5345 case VGF2P8AFFINEQBYrri:
5346 case VGF2P8AFFINEQBZ128rmbi:
5347 case VGF2P8AFFINEQBZ128rmbik:
5348 case VGF2P8AFFINEQBZ128rmbikz:
5349 case VGF2P8AFFINEQBZ128rmi:
5350 case VGF2P8AFFINEQBZ128rmik:
5351 case VGF2P8AFFINEQBZ128rmikz:
5352 case VGF2P8AFFINEQBZ128rri:
5353 case VGF2P8AFFINEQBZ128rrik:
5354 case VGF2P8AFFINEQBZ128rrikz:
5355 case VGF2P8AFFINEQBZ256rmbi:
5356 case VGF2P8AFFINEQBZ256rmbik:
5357 case VGF2P8AFFINEQBZ256rmbikz:
5358 case VGF2P8AFFINEQBZ256rmi:
5359 case VGF2P8AFFINEQBZ256rmik:
5360 case VGF2P8AFFINEQBZ256rmikz:
5361 case VGF2P8AFFINEQBZ256rri:
5362 case VGF2P8AFFINEQBZ256rrik:
5363 case VGF2P8AFFINEQBZ256rrikz:
5364 case VGF2P8AFFINEQBZrmbi:
5365 case VGF2P8AFFINEQBZrmbik:
5366 case VGF2P8AFFINEQBZrmbikz:
5367 case VGF2P8AFFINEQBZrmi:
5368 case VGF2P8AFFINEQBZrmik:
5369 case VGF2P8AFFINEQBZrmikz:
5370 case VGF2P8AFFINEQBZrri:
5371 case VGF2P8AFFINEQBZrrik:
5372 case VGF2P8AFFINEQBZrrikz:
5373 case VGF2P8AFFINEQBrmi:
5374 case VGF2P8AFFINEQBrri:
5375 return true;
5376 }
5377 return false;
5378}
5379
5380bool isPMOVZXWD(unsigned Opcode) {
5381 switch (Opcode) {
5382 case PMOVZXWDrm:
5383 case PMOVZXWDrr:
5384 return true;
5385 }
5386 return false;
5387}
5388
5389bool isPMINUD(unsigned Opcode) {
5390 switch (Opcode) {
5391 case PMINUDrm:
5392 case PMINUDrr:
5393 return true;
5394 }
5395 return false;
5396}
5397
5398bool isXSUSLDTRK(unsigned Opcode) {
5399 return Opcode == XSUSLDTRK;
5400}
5401
5402bool isVCVTPH2UW(unsigned Opcode) {
5403 switch (Opcode) {
5404 case VCVTPH2UWZ128rm:
5405 case VCVTPH2UWZ128rmb:
5406 case VCVTPH2UWZ128rmbk:
5407 case VCVTPH2UWZ128rmbkz:
5408 case VCVTPH2UWZ128rmk:
5409 case VCVTPH2UWZ128rmkz:
5410 case VCVTPH2UWZ128rr:
5411 case VCVTPH2UWZ128rrk:
5412 case VCVTPH2UWZ128rrkz:
5413 case VCVTPH2UWZ256rm:
5414 case VCVTPH2UWZ256rmb:
5415 case VCVTPH2UWZ256rmbk:
5416 case VCVTPH2UWZ256rmbkz:
5417 case VCVTPH2UWZ256rmk:
5418 case VCVTPH2UWZ256rmkz:
5419 case VCVTPH2UWZ256rr:
5420 case VCVTPH2UWZ256rrk:
5421 case VCVTPH2UWZ256rrkz:
5422 case VCVTPH2UWZrm:
5423 case VCVTPH2UWZrmb:
5424 case VCVTPH2UWZrmbk:
5425 case VCVTPH2UWZrmbkz:
5426 case VCVTPH2UWZrmk:
5427 case VCVTPH2UWZrmkz:
5428 case VCVTPH2UWZrr:
5429 case VCVTPH2UWZrrb:
5430 case VCVTPH2UWZrrbk:
5431 case VCVTPH2UWZrrbkz:
5432 case VCVTPH2UWZrrk:
5433 case VCVTPH2UWZrrkz:
5434 return true;
5435 }
5436 return false;
5437}
5438
5439bool isPADDSW(unsigned Opcode) {
5440 switch (Opcode) {
5441 case MMX_PADDSWrm:
5442 case MMX_PADDSWrr:
5443 case PADDSWrm:
5444 case PADDSWrr:
5445 return true;
5446 }
5447 return false;
5448}
5449
5450bool isLFENCE(unsigned Opcode) {
5451 return Opcode == LFENCE;
5452}
5453
5454bool isCRC32(unsigned Opcode) {
5455 switch (Opcode) {
5456 case CRC32r32m16:
5457 case CRC32r32m16_EVEX:
5458 case CRC32r32m32:
5459 case CRC32r32m32_EVEX:
5460 case CRC32r32m8:
5461 case CRC32r32m8_EVEX:
5462 case CRC32r32r16:
5463 case CRC32r32r16_EVEX:
5464 case CRC32r32r32:
5465 case CRC32r32r32_EVEX:
5466 case CRC32r32r8:
5467 case CRC32r32r8_EVEX:
5468 case CRC32r64m64:
5469 case CRC32r64m64_EVEX:
5470 case CRC32r64m8:
5471 case CRC32r64m8_EVEX:
5472 case CRC32r64r64:
5473 case CRC32r64r64_EVEX:
5474 case CRC32r64r8:
5475 case CRC32r64r8_EVEX:
5476 return true;
5477 }
5478 return false;
5479}
5480
5481bool isAESENCWIDE256KL(unsigned Opcode) {
5482 return Opcode == AESENCWIDE256KL;
5483}
5484
5485bool isMOVAPD(unsigned Opcode) {
5486 switch (Opcode) {
5487 case MOVAPDmr:
5488 case MOVAPDrm:
5489 case MOVAPDrr:
5490 case MOVAPDrr_REV:
5491 return true;
5492 }
5493 return false;
5494}
5495
5496bool isVFMADD213PS(unsigned Opcode) {
5497 switch (Opcode) {
5498 case VFMADD213PSYm:
5499 case VFMADD213PSYr:
5500 case VFMADD213PSZ128m:
5501 case VFMADD213PSZ128mb:
5502 case VFMADD213PSZ128mbk:
5503 case VFMADD213PSZ128mbkz:
5504 case VFMADD213PSZ128mk:
5505 case VFMADD213PSZ128mkz:
5506 case VFMADD213PSZ128r:
5507 case VFMADD213PSZ128rk:
5508 case VFMADD213PSZ128rkz:
5509 case VFMADD213PSZ256m:
5510 case VFMADD213PSZ256mb:
5511 case VFMADD213PSZ256mbk:
5512 case VFMADD213PSZ256mbkz:
5513 case VFMADD213PSZ256mk:
5514 case VFMADD213PSZ256mkz:
5515 case VFMADD213PSZ256r:
5516 case VFMADD213PSZ256rk:
5517 case VFMADD213PSZ256rkz:
5518 case VFMADD213PSZm:
5519 case VFMADD213PSZmb:
5520 case VFMADD213PSZmbk:
5521 case VFMADD213PSZmbkz:
5522 case VFMADD213PSZmk:
5523 case VFMADD213PSZmkz:
5524 case VFMADD213PSZr:
5525 case VFMADD213PSZrb:
5526 case VFMADD213PSZrbk:
5527 case VFMADD213PSZrbkz:
5528 case VFMADD213PSZrk:
5529 case VFMADD213PSZrkz:
5530 case VFMADD213PSm:
5531 case VFMADD213PSr:
5532 return true;
5533 }
5534 return false;
5535}
5536
5537bool isVPDPWUUDS(unsigned Opcode) {
5538 switch (Opcode) {
5539 case VPDPWUUDSYrm:
5540 case VPDPWUUDSYrr:
5541 case VPDPWUUDSZ128rm:
5542 case VPDPWUUDSZ128rmb:
5543 case VPDPWUUDSZ128rmbk:
5544 case VPDPWUUDSZ128rmbkz:
5545 case VPDPWUUDSZ128rmk:
5546 case VPDPWUUDSZ128rmkz:
5547 case VPDPWUUDSZ128rr:
5548 case VPDPWUUDSZ128rrk:
5549 case VPDPWUUDSZ128rrkz:
5550 case VPDPWUUDSZ256rm:
5551 case VPDPWUUDSZ256rmb:
5552 case VPDPWUUDSZ256rmbk:
5553 case VPDPWUUDSZ256rmbkz:
5554 case VPDPWUUDSZ256rmk:
5555 case VPDPWUUDSZ256rmkz:
5556 case VPDPWUUDSZ256rr:
5557 case VPDPWUUDSZ256rrk:
5558 case VPDPWUUDSZ256rrkz:
5559 case VPDPWUUDSZrm:
5560 case VPDPWUUDSZrmb:
5561 case VPDPWUUDSZrmbk:
5562 case VPDPWUUDSZrmbkz:
5563 case VPDPWUUDSZrmk:
5564 case VPDPWUUDSZrmkz:
5565 case VPDPWUUDSZrr:
5566 case VPDPWUUDSZrrk:
5567 case VPDPWUUDSZrrkz:
5568 case VPDPWUUDSrm:
5569 case VPDPWUUDSrr:
5570 return true;
5571 }
5572 return false;
5573}
5574
5575bool isMOVSLDUP(unsigned Opcode) {
5576 switch (Opcode) {
5577 case MOVSLDUPrm:
5578 case MOVSLDUPrr:
5579 return true;
5580 }
5581 return false;
5582}
5583
5584bool isCLDEMOTE(unsigned Opcode) {
5585 return Opcode == CLDEMOTE;
5586}
5587
5588bool isVCVTBIASPS2HF8S(unsigned Opcode) {
5589 switch (Opcode) {
5590 case VCVTBIASPS2HF8SZ128rm:
5591 case VCVTBIASPS2HF8SZ128rmb:
5592 case VCVTBIASPS2HF8SZ128rmbk:
5593 case VCVTBIASPS2HF8SZ128rmbkz:
5594 case VCVTBIASPS2HF8SZ128rmk:
5595 case VCVTBIASPS2HF8SZ128rmkz:
5596 case VCVTBIASPS2HF8SZ128rr:
5597 case VCVTBIASPS2HF8SZ128rrk:
5598 case VCVTBIASPS2HF8SZ128rrkz:
5599 case VCVTBIASPS2HF8SZ256rm:
5600 case VCVTBIASPS2HF8SZ256rmb:
5601 case VCVTBIASPS2HF8SZ256rmbk:
5602 case VCVTBIASPS2HF8SZ256rmbkz:
5603 case VCVTBIASPS2HF8SZ256rmk:
5604 case VCVTBIASPS2HF8SZ256rmkz:
5605 case VCVTBIASPS2HF8SZ256rr:
5606 case VCVTBIASPS2HF8SZ256rrk:
5607 case VCVTBIASPS2HF8SZ256rrkz:
5608 case VCVTBIASPS2HF8SZrm:
5609 case VCVTBIASPS2HF8SZrmb:
5610 case VCVTBIASPS2HF8SZrmbk:
5611 case VCVTBIASPS2HF8SZrmbkz:
5612 case VCVTBIASPS2HF8SZrmk:
5613 case VCVTBIASPS2HF8SZrmkz:
5614 case VCVTBIASPS2HF8SZrr:
5615 case VCVTBIASPS2HF8SZrrk:
5616 case VCVTBIASPS2HF8SZrrkz:
5617 return true;
5618 }
5619 return false;
5620}
5621
5622bool isVFNMADD231PS(unsigned Opcode) {
5623 switch (Opcode) {
5624 case VFNMADD231PSYm:
5625 case VFNMADD231PSYr:
5626 case VFNMADD231PSZ128m:
5627 case VFNMADD231PSZ128mb:
5628 case VFNMADD231PSZ128mbk:
5629 case VFNMADD231PSZ128mbkz:
5630 case VFNMADD231PSZ128mk:
5631 case VFNMADD231PSZ128mkz:
5632 case VFNMADD231PSZ128r:
5633 case VFNMADD231PSZ128rk:
5634 case VFNMADD231PSZ128rkz:
5635 case VFNMADD231PSZ256m:
5636 case VFNMADD231PSZ256mb:
5637 case VFNMADD231PSZ256mbk:
5638 case VFNMADD231PSZ256mbkz:
5639 case VFNMADD231PSZ256mk:
5640 case VFNMADD231PSZ256mkz:
5641 case VFNMADD231PSZ256r:
5642 case VFNMADD231PSZ256rk:
5643 case VFNMADD231PSZ256rkz:
5644 case VFNMADD231PSZm:
5645 case VFNMADD231PSZmb:
5646 case VFNMADD231PSZmbk:
5647 case VFNMADD231PSZmbkz:
5648 case VFNMADD231PSZmk:
5649 case VFNMADD231PSZmkz:
5650 case VFNMADD231PSZr:
5651 case VFNMADD231PSZrb:
5652 case VFNMADD231PSZrbk:
5653 case VFNMADD231PSZrbkz:
5654 case VFNMADD231PSZrk:
5655 case VFNMADD231PSZrkz:
5656 case VFNMADD231PSm:
5657 case VFNMADD231PSr:
5658 return true;
5659 }
5660 return false;
5661}
5662
5663bool isVMOVMSKPD(unsigned Opcode) {
5664 switch (Opcode) {
5665 case VMOVMSKPDYrr:
5666 case VMOVMSKPDrr:
5667 return true;
5668 }
5669 return false;
5670}
5671
5672bool isPREFETCHT0(unsigned Opcode) {
5673 return Opcode == PREFETCHT0;
5674}
5675
5676bool isVCVTNEOBF162PS(unsigned Opcode) {
5677 switch (Opcode) {
5678 case VCVTNEOBF162PSYrm:
5679 case VCVTNEOBF162PSrm:
5680 return true;
5681 }
5682 return false;
5683}
5684
5685bool isVPCMPUD(unsigned Opcode) {
5686 switch (Opcode) {
5687 case VPCMPUDZ128rmbi:
5688 case VPCMPUDZ128rmbik:
5689 case VPCMPUDZ128rmi:
5690 case VPCMPUDZ128rmik:
5691 case VPCMPUDZ128rri:
5692 case VPCMPUDZ128rrik:
5693 case VPCMPUDZ256rmbi:
5694 case VPCMPUDZ256rmbik:
5695 case VPCMPUDZ256rmi:
5696 case VPCMPUDZ256rmik:
5697 case VPCMPUDZ256rri:
5698 case VPCMPUDZ256rrik:
5699 case VPCMPUDZrmbi:
5700 case VPCMPUDZrmbik:
5701 case VPCMPUDZrmi:
5702 case VPCMPUDZrmik:
5703 case VPCMPUDZrri:
5704 case VPCMPUDZrrik:
5705 return true;
5706 }
5707 return false;
5708}
5709
5710bool isVMAXSD(unsigned Opcode) {
5711 switch (Opcode) {
5712 case VMAXSDZrm_Int:
5713 case VMAXSDZrmk_Int:
5714 case VMAXSDZrmkz_Int:
5715 case VMAXSDZrr_Int:
5716 case VMAXSDZrrb_Int:
5717 case VMAXSDZrrbk_Int:
5718 case VMAXSDZrrbkz_Int:
5719 case VMAXSDZrrk_Int:
5720 case VMAXSDZrrkz_Int:
5721 case VMAXSDrm_Int:
5722 case VMAXSDrr_Int:
5723 return true;
5724 }
5725 return false;
5726}
5727
5728bool isVRCP28SD(unsigned Opcode) {
5729 switch (Opcode) {
5730 case VRCP28SDZm:
5731 case VRCP28SDZmk:
5732 case VRCP28SDZmkz:
5733 case VRCP28SDZr:
5734 case VRCP28SDZrb:
5735 case VRCP28SDZrbk:
5736 case VRCP28SDZrbkz:
5737 case VRCP28SDZrk:
5738 case VRCP28SDZrkz:
5739 return true;
5740 }
5741 return false;
5742}
5743
5744bool isVMAXPS(unsigned Opcode) {
5745 switch (Opcode) {
5746 case VMAXPSYrm:
5747 case VMAXPSYrr:
5748 case VMAXPSZ128rm:
5749 case VMAXPSZ128rmb:
5750 case VMAXPSZ128rmbk:
5751 case VMAXPSZ128rmbkz:
5752 case VMAXPSZ128rmk:
5753 case VMAXPSZ128rmkz:
5754 case VMAXPSZ128rr:
5755 case VMAXPSZ128rrk:
5756 case VMAXPSZ128rrkz:
5757 case VMAXPSZ256rm:
5758 case VMAXPSZ256rmb:
5759 case VMAXPSZ256rmbk:
5760 case VMAXPSZ256rmbkz:
5761 case VMAXPSZ256rmk:
5762 case VMAXPSZ256rmkz:
5763 case VMAXPSZ256rr:
5764 case VMAXPSZ256rrk:
5765 case VMAXPSZ256rrkz:
5766 case VMAXPSZrm:
5767 case VMAXPSZrmb:
5768 case VMAXPSZrmbk:
5769 case VMAXPSZrmbkz:
5770 case VMAXPSZrmk:
5771 case VMAXPSZrmkz:
5772 case VMAXPSZrr:
5773 case VMAXPSZrrb:
5774 case VMAXPSZrrbk:
5775 case VMAXPSZrrbkz:
5776 case VMAXPSZrrk:
5777 case VMAXPSZrrkz:
5778 case VMAXPSrm:
5779 case VMAXPSrr:
5780 return true;
5781 }
5782 return false;
5783}
5784
5785bool isVPMOVD2M(unsigned Opcode) {
5786 switch (Opcode) {
5787 case VPMOVD2MZ128kr:
5788 case VPMOVD2MZ256kr:
5789 case VPMOVD2MZkr:
5790 return true;
5791 }
5792 return false;
5793}
5794
5795bool isVPMACSSWD(unsigned Opcode) {
5796 switch (Opcode) {
5797 case VPMACSSWDrm:
5798 case VPMACSSWDrr:
5799 return true;
5800 }
5801 return false;
5802}
5803
5804bool isVUCOMISD(unsigned Opcode) {
5805 switch (Opcode) {
5806 case VUCOMISDZrm:
5807 case VUCOMISDZrr:
5808 case VUCOMISDZrrb:
5809 case VUCOMISDrm:
5810 case VUCOMISDrr:
5811 return true;
5812 }
5813 return false;
5814}
5815
5816bool isLTR(unsigned Opcode) {
5817 switch (Opcode) {
5818 case LTRm:
5819 case LTRr:
5820 return true;
5821 }
5822 return false;
5823}
5824
5825bool isVCVTUSI2SH(unsigned Opcode) {
5826 switch (Opcode) {
5827 case VCVTUSI2SHZrm_Int:
5828 case VCVTUSI2SHZrr_Int:
5829 case VCVTUSI2SHZrrb_Int:
5830 case VCVTUSI642SHZrm_Int:
5831 case VCVTUSI642SHZrr_Int:
5832 case VCVTUSI642SHZrrb_Int:
5833 return true;
5834 }
5835 return false;
5836}
5837
5838bool isVSCATTERPF1QPS(unsigned Opcode) {
5839 return Opcode == VSCATTERPF1QPSm;
5840}
5841
5842bool isWRGSBASE(unsigned Opcode) {
5843 switch (Opcode) {
5844 case WRGSBASE:
5845 case WRGSBASE64:
5846 return true;
5847 }
5848 return false;
5849}
5850
5851bool isSTOSQ(unsigned Opcode) {
5852 return Opcode == STOSQ;
5853}
5854
5855bool isVSQRTSD(unsigned Opcode) {
5856 switch (Opcode) {
5857 case VSQRTSDZm_Int:
5858 case VSQRTSDZmk_Int:
5859 case VSQRTSDZmkz_Int:
5860 case VSQRTSDZr_Int:
5861 case VSQRTSDZrb_Int:
5862 case VSQRTSDZrbk_Int:
5863 case VSQRTSDZrbkz_Int:
5864 case VSQRTSDZrk_Int:
5865 case VSQRTSDZrkz_Int:
5866 case VSQRTSDm_Int:
5867 case VSQRTSDr_Int:
5868 return true;
5869 }
5870 return false;
5871}
5872
5873bool isVPERMIL2PD(unsigned Opcode) {
5874 switch (Opcode) {
5875 case VPERMIL2PDYmr:
5876 case VPERMIL2PDYrm:
5877 case VPERMIL2PDYrr:
5878 case VPERMIL2PDYrr_REV:
5879 case VPERMIL2PDmr:
5880 case VPERMIL2PDrm:
5881 case VPERMIL2PDrr:
5882 case VPERMIL2PDrr_REV:
5883 return true;
5884 }
5885 return false;
5886}
5887
5888bool isVFCMADDCSH(unsigned Opcode) {
5889 switch (Opcode) {
5890 case VFCMADDCSHZm:
5891 case VFCMADDCSHZmk:
5892 case VFCMADDCSHZmkz:
5893 case VFCMADDCSHZr:
5894 case VFCMADDCSHZrb:
5895 case VFCMADDCSHZrbk:
5896 case VFCMADDCSHZrbkz:
5897 case VFCMADDCSHZrk:
5898 case VFCMADDCSHZrkz:
5899 return true;
5900 }
5901 return false;
5902}
5903
5904bool isVFMADDSUB213PS(unsigned Opcode) {
5905 switch (Opcode) {
5906 case VFMADDSUB213PSYm:
5907 case VFMADDSUB213PSYr:
5908 case VFMADDSUB213PSZ128m:
5909 case VFMADDSUB213PSZ128mb:
5910 case VFMADDSUB213PSZ128mbk:
5911 case VFMADDSUB213PSZ128mbkz:
5912 case VFMADDSUB213PSZ128mk:
5913 case VFMADDSUB213PSZ128mkz:
5914 case VFMADDSUB213PSZ128r:
5915 case VFMADDSUB213PSZ128rk:
5916 case VFMADDSUB213PSZ128rkz:
5917 case VFMADDSUB213PSZ256m:
5918 case VFMADDSUB213PSZ256mb:
5919 case VFMADDSUB213PSZ256mbk:
5920 case VFMADDSUB213PSZ256mbkz:
5921 case VFMADDSUB213PSZ256mk:
5922 case VFMADDSUB213PSZ256mkz:
5923 case VFMADDSUB213PSZ256r:
5924 case VFMADDSUB213PSZ256rk:
5925 case VFMADDSUB213PSZ256rkz:
5926 case VFMADDSUB213PSZm:
5927 case VFMADDSUB213PSZmb:
5928 case VFMADDSUB213PSZmbk:
5929 case VFMADDSUB213PSZmbkz:
5930 case VFMADDSUB213PSZmk:
5931 case VFMADDSUB213PSZmkz:
5932 case VFMADDSUB213PSZr:
5933 case VFMADDSUB213PSZrb:
5934 case VFMADDSUB213PSZrbk:
5935 case VFMADDSUB213PSZrbkz:
5936 case VFMADDSUB213PSZrk:
5937 case VFMADDSUB213PSZrkz:
5938 case VFMADDSUB213PSm:
5939 case VFMADDSUB213PSr:
5940 return true;
5941 }
5942 return false;
5943}
5944
5945bool isPFSUB(unsigned Opcode) {
5946 switch (Opcode) {
5947 case PFSUBrm:
5948 case PFSUBrr:
5949 return true;
5950 }
5951 return false;
5952}
5953
5954bool isVSQRTSS(unsigned Opcode) {
5955 switch (Opcode) {
5956 case VSQRTSSZm_Int:
5957 case VSQRTSSZmk_Int:
5958 case VSQRTSSZmkz_Int:
5959 case VSQRTSSZr_Int:
5960 case VSQRTSSZrb_Int:
5961 case VSQRTSSZrbk_Int:
5962 case VSQRTSSZrbkz_Int:
5963 case VSQRTSSZrk_Int:
5964 case VSQRTSSZrkz_Int:
5965 case VSQRTSSm_Int:
5966 case VSQRTSSr_Int:
5967 return true;
5968 }
5969 return false;
5970}
5971
5972bool isVEXPANDPS(unsigned Opcode) {
5973 switch (Opcode) {
5974 case VEXPANDPSZ128rm:
5975 case VEXPANDPSZ128rmk:
5976 case VEXPANDPSZ128rmkz:
5977 case VEXPANDPSZ128rr:
5978 case VEXPANDPSZ128rrk:
5979 case VEXPANDPSZ128rrkz:
5980 case VEXPANDPSZ256rm:
5981 case VEXPANDPSZ256rmk:
5982 case VEXPANDPSZ256rmkz:
5983 case VEXPANDPSZ256rr:
5984 case VEXPANDPSZ256rrk:
5985 case VEXPANDPSZ256rrkz:
5986 case VEXPANDPSZrm:
5987 case VEXPANDPSZrmk:
5988 case VEXPANDPSZrmkz:
5989 case VEXPANDPSZrr:
5990 case VEXPANDPSZrrk:
5991 case VEXPANDPSZrrkz:
5992 return true;
5993 }
5994 return false;
5995}
5996
5997bool isVPCOMPRESSW(unsigned Opcode) {
5998 switch (Opcode) {
5999 case VPCOMPRESSWZ128mr:
6000 case VPCOMPRESSWZ128mrk:
6001 case VPCOMPRESSWZ128rr:
6002 case VPCOMPRESSWZ128rrk:
6003 case VPCOMPRESSWZ128rrkz:
6004 case VPCOMPRESSWZ256mr:
6005 case VPCOMPRESSWZ256mrk:
6006 case VPCOMPRESSWZ256rr:
6007 case VPCOMPRESSWZ256rrk:
6008 case VPCOMPRESSWZ256rrkz:
6009 case VPCOMPRESSWZmr:
6010 case VPCOMPRESSWZmrk:
6011 case VPCOMPRESSWZrr:
6012 case VPCOMPRESSWZrrk:
6013 case VPCOMPRESSWZrrkz:
6014 return true;
6015 }
6016 return false;
6017}
6018
6019bool isPEXTRD(unsigned Opcode) {
6020 switch (Opcode) {
6021 case PEXTRDmri:
6022 case PEXTRDrri:
6023 return true;
6024 }
6025 return false;
6026}
6027
6028bool isVCVTTPS2UQQS(unsigned Opcode) {
6029 switch (Opcode) {
6030 case VCVTTPS2UQQSZ128rm:
6031 case VCVTTPS2UQQSZ128rmb:
6032 case VCVTTPS2UQQSZ128rmbk:
6033 case VCVTTPS2UQQSZ128rmbkz:
6034 case VCVTTPS2UQQSZ128rmk:
6035 case VCVTTPS2UQQSZ128rmkz:
6036 case VCVTTPS2UQQSZ128rr:
6037 case VCVTTPS2UQQSZ128rrk:
6038 case VCVTTPS2UQQSZ128rrkz:
6039 case VCVTTPS2UQQSZ256rm:
6040 case VCVTTPS2UQQSZ256rmb:
6041 case VCVTTPS2UQQSZ256rmbk:
6042 case VCVTTPS2UQQSZ256rmbkz:
6043 case VCVTTPS2UQQSZ256rmk:
6044 case VCVTTPS2UQQSZ256rmkz:
6045 case VCVTTPS2UQQSZ256rr:
6046 case VCVTTPS2UQQSZ256rrb:
6047 case VCVTTPS2UQQSZ256rrbk:
6048 case VCVTTPS2UQQSZ256rrbkz:
6049 case VCVTTPS2UQQSZ256rrk:
6050 case VCVTTPS2UQQSZ256rrkz:
6051 case VCVTTPS2UQQSZrm:
6052 case VCVTTPS2UQQSZrmb:
6053 case VCVTTPS2UQQSZrmbk:
6054 case VCVTTPS2UQQSZrmbkz:
6055 case VCVTTPS2UQQSZrmk:
6056 case VCVTTPS2UQQSZrmkz:
6057 case VCVTTPS2UQQSZrr:
6058 case VCVTTPS2UQQSZrrb:
6059 case VCVTTPS2UQQSZrrbk:
6060 case VCVTTPS2UQQSZrrbkz:
6061 case VCVTTPS2UQQSZrrk:
6062 case VCVTTPS2UQQSZrrkz:
6063 return true;
6064 }
6065 return false;
6066}
6067
6068bool isSYSEXITQ(unsigned Opcode) {
6069 return Opcode == SYSEXIT64;
6070}
6071
6072bool isROUNDSD(unsigned Opcode) {
6073 switch (Opcode) {
6074 case ROUNDSDmi_Int:
6075 case ROUNDSDri_Int:
6076 return true;
6077 }
6078 return false;
6079}
6080
6081bool isVFMADD132BF16(unsigned Opcode) {
6082 switch (Opcode) {
6083 case VFMADD132BF16Z128m:
6084 case VFMADD132BF16Z128mb:
6085 case VFMADD132BF16Z128mbk:
6086 case VFMADD132BF16Z128mbkz:
6087 case VFMADD132BF16Z128mk:
6088 case VFMADD132BF16Z128mkz:
6089 case VFMADD132BF16Z128r:
6090 case VFMADD132BF16Z128rk:
6091 case VFMADD132BF16Z128rkz:
6092 case VFMADD132BF16Z256m:
6093 case VFMADD132BF16Z256mb:
6094 case VFMADD132BF16Z256mbk:
6095 case VFMADD132BF16Z256mbkz:
6096 case VFMADD132BF16Z256mk:
6097 case VFMADD132BF16Z256mkz:
6098 case VFMADD132BF16Z256r:
6099 case VFMADD132BF16Z256rk:
6100 case VFMADD132BF16Z256rkz:
6101 case VFMADD132BF16Zm:
6102 case VFMADD132BF16Zmb:
6103 case VFMADD132BF16Zmbk:
6104 case VFMADD132BF16Zmbkz:
6105 case VFMADD132BF16Zmk:
6106 case VFMADD132BF16Zmkz:
6107 case VFMADD132BF16Zr:
6108 case VFMADD132BF16Zrk:
6109 case VFMADD132BF16Zrkz:
6110 return true;
6111 }
6112 return false;
6113}
6114
6115bool isFCOM(unsigned Opcode) {
6116 switch (Opcode) {
6117 case COM_FST0r:
6118 case FCOM32m:
6119 case FCOM64m:
6120 return true;
6121 }
6122 return false;
6123}
6124
6125bool isVFNMSUBSS(unsigned Opcode) {
6126 switch (Opcode) {
6127 case VFNMSUBSS4mr:
6128 case VFNMSUBSS4rm:
6129 case VFNMSUBSS4rr:
6130 case VFNMSUBSS4rr_REV:
6131 return true;
6132 }
6133 return false;
6134}
6135
6136bool isKSHIFTLW(unsigned Opcode) {
6137 return Opcode == KSHIFTLWki;
6138}
6139
6140bool isVMPTRLD(unsigned Opcode) {
6141 return Opcode == VMPTRLDm;
6142}
6143
6144bool isSCASD(unsigned Opcode) {
6145 return Opcode == SCASL;
6146}
6147
6148bool isVAESDECLAST(unsigned Opcode) {
6149 switch (Opcode) {
6150 case VAESDECLASTYrm:
6151 case VAESDECLASTYrr:
6152 case VAESDECLASTZ128rm:
6153 case VAESDECLASTZ128rr:
6154 case VAESDECLASTZ256rm:
6155 case VAESDECLASTZ256rr:
6156 case VAESDECLASTZrm:
6157 case VAESDECLASTZrr:
6158 case VAESDECLASTrm:
6159 case VAESDECLASTrr:
6160 return true;
6161 }
6162 return false;
6163}
6164
6165bool isVFMADDSUBPS(unsigned Opcode) {
6166 switch (Opcode) {
6167 case VFMADDSUBPS4Ymr:
6168 case VFMADDSUBPS4Yrm:
6169 case VFMADDSUBPS4Yrr:
6170 case VFMADDSUBPS4Yrr_REV:
6171 case VFMADDSUBPS4mr:
6172 case VFMADDSUBPS4rm:
6173 case VFMADDSUBPS4rr:
6174 case VFMADDSUBPS4rr_REV:
6175 return true;
6176 }
6177 return false;
6178}
6179
6180bool isVCVTUQQ2PS(unsigned Opcode) {
6181 switch (Opcode) {
6182 case VCVTUQQ2PSZ128rm:
6183 case VCVTUQQ2PSZ128rmb:
6184 case VCVTUQQ2PSZ128rmbk:
6185 case VCVTUQQ2PSZ128rmbkz:
6186 case VCVTUQQ2PSZ128rmk:
6187 case VCVTUQQ2PSZ128rmkz:
6188 case VCVTUQQ2PSZ128rr:
6189 case VCVTUQQ2PSZ128rrk:
6190 case VCVTUQQ2PSZ128rrkz:
6191 case VCVTUQQ2PSZ256rm:
6192 case VCVTUQQ2PSZ256rmb:
6193 case VCVTUQQ2PSZ256rmbk:
6194 case VCVTUQQ2PSZ256rmbkz:
6195 case VCVTUQQ2PSZ256rmk:
6196 case VCVTUQQ2PSZ256rmkz:
6197 case VCVTUQQ2PSZ256rr:
6198 case VCVTUQQ2PSZ256rrk:
6199 case VCVTUQQ2PSZ256rrkz:
6200 case VCVTUQQ2PSZrm:
6201 case VCVTUQQ2PSZrmb:
6202 case VCVTUQQ2PSZrmbk:
6203 case VCVTUQQ2PSZrmbkz:
6204 case VCVTUQQ2PSZrmk:
6205 case VCVTUQQ2PSZrmkz:
6206 case VCVTUQQ2PSZrr:
6207 case VCVTUQQ2PSZrrb:
6208 case VCVTUQQ2PSZrrbk:
6209 case VCVTUQQ2PSZrrbkz:
6210 case VCVTUQQ2PSZrrk:
6211 case VCVTUQQ2PSZrrkz:
6212 return true;
6213 }
6214 return false;
6215}
6216
6217bool isVPMOVUSDB(unsigned Opcode) {
6218 switch (Opcode) {
6219 case VPMOVUSDBZ128mr:
6220 case VPMOVUSDBZ128mrk:
6221 case VPMOVUSDBZ128rr:
6222 case VPMOVUSDBZ128rrk:
6223 case VPMOVUSDBZ128rrkz:
6224 case VPMOVUSDBZ256mr:
6225 case VPMOVUSDBZ256mrk:
6226 case VPMOVUSDBZ256rr:
6227 case VPMOVUSDBZ256rrk:
6228 case VPMOVUSDBZ256rrkz:
6229 case VPMOVUSDBZmr:
6230 case VPMOVUSDBZmrk:
6231 case VPMOVUSDBZrr:
6232 case VPMOVUSDBZrrk:
6233 case VPMOVUSDBZrrkz:
6234 return true;
6235 }
6236 return false;
6237}
6238
6239bool isVPROTW(unsigned Opcode) {
6240 switch (Opcode) {
6241 case VPROTWmi:
6242 case VPROTWmr:
6243 case VPROTWri:
6244 case VPROTWrm:
6245 case VPROTWrr:
6246 case VPROTWrr_REV:
6247 return true;
6248 }
6249 return false;
6250}
6251
6252bool isVDPPS(unsigned Opcode) {
6253 switch (Opcode) {
6254 case VDPPSYrmi:
6255 case VDPPSYrri:
6256 case VDPPSrmi:
6257 case VDPPSrri:
6258 return true;
6259 }
6260 return false;
6261}
6262
6263bool isVRSQRT14PD(unsigned Opcode) {
6264 switch (Opcode) {
6265 case VRSQRT14PDZ128m:
6266 case VRSQRT14PDZ128mb:
6267 case VRSQRT14PDZ128mbk:
6268 case VRSQRT14PDZ128mbkz:
6269 case VRSQRT14PDZ128mk:
6270 case VRSQRT14PDZ128mkz:
6271 case VRSQRT14PDZ128r:
6272 case VRSQRT14PDZ128rk:
6273 case VRSQRT14PDZ128rkz:
6274 case VRSQRT14PDZ256m:
6275 case VRSQRT14PDZ256mb:
6276 case VRSQRT14PDZ256mbk:
6277 case VRSQRT14PDZ256mbkz:
6278 case VRSQRT14PDZ256mk:
6279 case VRSQRT14PDZ256mkz:
6280 case VRSQRT14PDZ256r:
6281 case VRSQRT14PDZ256rk:
6282 case VRSQRT14PDZ256rkz:
6283 case VRSQRT14PDZm:
6284 case VRSQRT14PDZmb:
6285 case VRSQRT14PDZmbk:
6286 case VRSQRT14PDZmbkz:
6287 case VRSQRT14PDZmk:
6288 case VRSQRT14PDZmkz:
6289 case VRSQRT14PDZr:
6290 case VRSQRT14PDZrk:
6291 case VRSQRT14PDZrkz:
6292 return true;
6293 }
6294 return false;
6295}
6296
6297bool isVTESTPD(unsigned Opcode) {
6298 switch (Opcode) {
6299 case VTESTPDYrm:
6300 case VTESTPDYrr:
6301 case VTESTPDrm:
6302 case VTESTPDrr:
6303 return true;
6304 }
6305 return false;
6306}
6307
6308bool isVFNMADD231SH(unsigned Opcode) {
6309 switch (Opcode) {
6310 case VFNMADD231SHZm_Int:
6311 case VFNMADD231SHZmk_Int:
6312 case VFNMADD231SHZmkz_Int:
6313 case VFNMADD231SHZr_Int:
6314 case VFNMADD231SHZrb_Int:
6315 case VFNMADD231SHZrbk_Int:
6316 case VFNMADD231SHZrbkz_Int:
6317 case VFNMADD231SHZrk_Int:
6318 case VFNMADD231SHZrkz_Int:
6319 return true;
6320 }
6321 return false;
6322}
6323
6324bool isENDBR64(unsigned Opcode) {
6325 return Opcode == ENDBR64;
6326}
6327
6328bool isMULSD(unsigned Opcode) {
6329 switch (Opcode) {
6330 case MULSDrm_Int:
6331 case MULSDrr_Int:
6332 return true;
6333 }
6334 return false;
6335}
6336
6337bool isXRSTORS(unsigned Opcode) {
6338 return Opcode == XRSTORS;
6339}
6340
6341bool isPREFETCHNTA(unsigned Opcode) {
6342 return Opcode == PREFETCHNTA;
6343}
6344
6345bool isVPCOMD(unsigned Opcode) {
6346 switch (Opcode) {
6347 case VPCOMDmi:
6348 case VPCOMDri:
6349 return true;
6350 }
6351 return false;
6352}
6353
6354bool isVPCOMUB(unsigned Opcode) {
6355 switch (Opcode) {
6356 case VPCOMUBmi:
6357 case VPCOMUBri:
6358 return true;
6359 }
6360 return false;
6361}
6362
6363bool isVPDPBSSD(unsigned Opcode) {
6364 switch (Opcode) {
6365 case VPDPBSSDYrm:
6366 case VPDPBSSDYrr:
6367 case VPDPBSSDZ128rm:
6368 case VPDPBSSDZ128rmb:
6369 case VPDPBSSDZ128rmbk:
6370 case VPDPBSSDZ128rmbkz:
6371 case VPDPBSSDZ128rmk:
6372 case VPDPBSSDZ128rmkz:
6373 case VPDPBSSDZ128rr:
6374 case VPDPBSSDZ128rrk:
6375 case VPDPBSSDZ128rrkz:
6376 case VPDPBSSDZ256rm:
6377 case VPDPBSSDZ256rmb:
6378 case VPDPBSSDZ256rmbk:
6379 case VPDPBSSDZ256rmbkz:
6380 case VPDPBSSDZ256rmk:
6381 case VPDPBSSDZ256rmkz:
6382 case VPDPBSSDZ256rr:
6383 case VPDPBSSDZ256rrk:
6384 case VPDPBSSDZ256rrkz:
6385 case VPDPBSSDZrm:
6386 case VPDPBSSDZrmb:
6387 case VPDPBSSDZrmbk:
6388 case VPDPBSSDZrmbkz:
6389 case VPDPBSSDZrmk:
6390 case VPDPBSSDZrmkz:
6391 case VPDPBSSDZrr:
6392 case VPDPBSSDZrrk:
6393 case VPDPBSSDZrrkz:
6394 case VPDPBSSDrm:
6395 case VPDPBSSDrr:
6396 return true;
6397 }
6398 return false;
6399}
6400
6401bool isVCVTBIASPS2BF8(unsigned Opcode) {
6402 switch (Opcode) {
6403 case VCVTBIASPS2BF8Z128rm:
6404 case VCVTBIASPS2BF8Z128rmb:
6405 case VCVTBIASPS2BF8Z128rmbk:
6406 case VCVTBIASPS2BF8Z128rmbkz:
6407 case VCVTBIASPS2BF8Z128rmk:
6408 case VCVTBIASPS2BF8Z128rmkz:
6409 case VCVTBIASPS2BF8Z128rr:
6410 case VCVTBIASPS2BF8Z128rrk:
6411 case VCVTBIASPS2BF8Z128rrkz:
6412 case VCVTBIASPS2BF8Z256rm:
6413 case VCVTBIASPS2BF8Z256rmb:
6414 case VCVTBIASPS2BF8Z256rmbk:
6415 case VCVTBIASPS2BF8Z256rmbkz:
6416 case VCVTBIASPS2BF8Z256rmk:
6417 case VCVTBIASPS2BF8Z256rmkz:
6418 case VCVTBIASPS2BF8Z256rr:
6419 case VCVTBIASPS2BF8Z256rrk:
6420 case VCVTBIASPS2BF8Z256rrkz:
6421 case VCVTBIASPS2BF8Zrm:
6422 case VCVTBIASPS2BF8Zrmb:
6423 case VCVTBIASPS2BF8Zrmbk:
6424 case VCVTBIASPS2BF8Zrmbkz:
6425 case VCVTBIASPS2BF8Zrmk:
6426 case VCVTBIASPS2BF8Zrmkz:
6427 case VCVTBIASPS2BF8Zrr:
6428 case VCVTBIASPS2BF8Zrrk:
6429 case VCVTBIASPS2BF8Zrrkz:
6430 return true;
6431 }
6432 return false;
6433}
6434
6435bool isVPHSUBD(unsigned Opcode) {
6436 switch (Opcode) {
6437 case VPHSUBDYrm:
6438 case VPHSUBDYrr:
6439 case VPHSUBDrm:
6440 case VPHSUBDrr:
6441 return true;
6442 }
6443 return false;
6444}
6445
6446bool isVBROADCASTI64X2(unsigned Opcode) {
6447 switch (Opcode) {
6448 case VBROADCASTI64X2Z256rm:
6449 case VBROADCASTI64X2Z256rmk:
6450 case VBROADCASTI64X2Z256rmkz:
6451 case VBROADCASTI64X2Zrm:
6452 case VBROADCASTI64X2Zrmk:
6453 case VBROADCASTI64X2Zrmkz:
6454 return true;
6455 }
6456 return false;
6457}
6458
6459bool isFPATAN(unsigned Opcode) {
6460 return Opcode == FPATAN;
6461}
6462
6463bool isLOOPE(unsigned Opcode) {
6464 return Opcode == LOOPE;
6465}
6466
6467bool isPCMPEQW(unsigned Opcode) {
6468 switch (Opcode) {
6469 case MMX_PCMPEQWrm:
6470 case MMX_PCMPEQWrr:
6471 case PCMPEQWrm:
6472 case PCMPEQWrr:
6473 return true;
6474 }
6475 return false;
6476}
6477
6478bool isVFMADDCSH(unsigned Opcode) {
6479 switch (Opcode) {
6480 case VFMADDCSHZm:
6481 case VFMADDCSHZmk:
6482 case VFMADDCSHZmkz:
6483 case VFMADDCSHZr:
6484 case VFMADDCSHZrb:
6485 case VFMADDCSHZrbk:
6486 case VFMADDCSHZrbkz:
6487 case VFMADDCSHZrk:
6488 case VFMADDCSHZrkz:
6489 return true;
6490 }
6491 return false;
6492}
6493
6494bool isMOVRS(unsigned Opcode) {
6495 switch (Opcode) {
6496 case MOVRS16rm:
6497 case MOVRS16rm_EVEX:
6498 case MOVRS32rm:
6499 case MOVRS32rm_EVEX:
6500 case MOVRS64rm:
6501 case MOVRS64rm_EVEX:
6502 case MOVRS8rm:
6503 case MOVRS8rm_EVEX:
6504 return true;
6505 }
6506 return false;
6507}
6508
6509bool isVFMSUBADD132PH(unsigned Opcode) {
6510 switch (Opcode) {
6511 case VFMSUBADD132PHZ128m:
6512 case VFMSUBADD132PHZ128mb:
6513 case VFMSUBADD132PHZ128mbk:
6514 case VFMSUBADD132PHZ128mbkz:
6515 case VFMSUBADD132PHZ128mk:
6516 case VFMSUBADD132PHZ128mkz:
6517 case VFMSUBADD132PHZ128r:
6518 case VFMSUBADD132PHZ128rk:
6519 case VFMSUBADD132PHZ128rkz:
6520 case VFMSUBADD132PHZ256m:
6521 case VFMSUBADD132PHZ256mb:
6522 case VFMSUBADD132PHZ256mbk:
6523 case VFMSUBADD132PHZ256mbkz:
6524 case VFMSUBADD132PHZ256mk:
6525 case VFMSUBADD132PHZ256mkz:
6526 case VFMSUBADD132PHZ256r:
6527 case VFMSUBADD132PHZ256rk:
6528 case VFMSUBADD132PHZ256rkz:
6529 case VFMSUBADD132PHZm:
6530 case VFMSUBADD132PHZmb:
6531 case VFMSUBADD132PHZmbk:
6532 case VFMSUBADD132PHZmbkz:
6533 case VFMSUBADD132PHZmk:
6534 case VFMSUBADD132PHZmkz:
6535 case VFMSUBADD132PHZr:
6536 case VFMSUBADD132PHZrb:
6537 case VFMSUBADD132PHZrbk:
6538 case VFMSUBADD132PHZrbkz:
6539 case VFMSUBADD132PHZrk:
6540 case VFMSUBADD132PHZrkz:
6541 return true;
6542 }
6543 return false;
6544}
6545
6546bool isKADDW(unsigned Opcode) {
6547 return Opcode == KADDWkk;
6548}
6549
6550bool isPTEST(unsigned Opcode) {
6551 switch (Opcode) {
6552 case PTESTrm:
6553 case PTESTrr:
6554 return true;
6555 }
6556 return false;
6557}
6558
6559bool isVPADDSB(unsigned Opcode) {
6560 switch (Opcode) {
6561 case VPADDSBYrm:
6562 case VPADDSBYrr:
6563 case VPADDSBZ128rm:
6564 case VPADDSBZ128rmk:
6565 case VPADDSBZ128rmkz:
6566 case VPADDSBZ128rr:
6567 case VPADDSBZ128rrk:
6568 case VPADDSBZ128rrkz:
6569 case VPADDSBZ256rm:
6570 case VPADDSBZ256rmk:
6571 case VPADDSBZ256rmkz:
6572 case VPADDSBZ256rr:
6573 case VPADDSBZ256rrk:
6574 case VPADDSBZ256rrkz:
6575 case VPADDSBZrm:
6576 case VPADDSBZrmk:
6577 case VPADDSBZrmkz:
6578 case VPADDSBZrr:
6579 case VPADDSBZrrk:
6580 case VPADDSBZrrkz:
6581 case VPADDSBrm:
6582 case VPADDSBrr:
6583 return true;
6584 }
6585 return false;
6586}
6587
6588bool isVRSQRT28PS(unsigned Opcode) {
6589 switch (Opcode) {
6590 case VRSQRT28PSZm:
6591 case VRSQRT28PSZmb:
6592 case VRSQRT28PSZmbk:
6593 case VRSQRT28PSZmbkz:
6594 case VRSQRT28PSZmk:
6595 case VRSQRT28PSZmkz:
6596 case VRSQRT28PSZr:
6597 case VRSQRT28PSZrb:
6598 case VRSQRT28PSZrbk:
6599 case VRSQRT28PSZrbkz:
6600 case VRSQRT28PSZrk:
6601 case VRSQRT28PSZrkz:
6602 return true;
6603 }
6604 return false;
6605}
6606
6607bool isVGF2P8AFFINEINVQB(unsigned Opcode) {
6608 switch (Opcode) {
6609 case VGF2P8AFFINEINVQBYrmi:
6610 case VGF2P8AFFINEINVQBYrri:
6611 case VGF2P8AFFINEINVQBZ128rmbi:
6612 case VGF2P8AFFINEINVQBZ128rmbik:
6613 case VGF2P8AFFINEINVQBZ128rmbikz:
6614 case VGF2P8AFFINEINVQBZ128rmi:
6615 case VGF2P8AFFINEINVQBZ128rmik:
6616 case VGF2P8AFFINEINVQBZ128rmikz:
6617 case VGF2P8AFFINEINVQBZ128rri:
6618 case VGF2P8AFFINEINVQBZ128rrik:
6619 case VGF2P8AFFINEINVQBZ128rrikz:
6620 case VGF2P8AFFINEINVQBZ256rmbi:
6621 case VGF2P8AFFINEINVQBZ256rmbik:
6622 case VGF2P8AFFINEINVQBZ256rmbikz:
6623 case VGF2P8AFFINEINVQBZ256rmi:
6624 case VGF2P8AFFINEINVQBZ256rmik:
6625 case VGF2P8AFFINEINVQBZ256rmikz:
6626 case VGF2P8AFFINEINVQBZ256rri:
6627 case VGF2P8AFFINEINVQBZ256rrik:
6628 case VGF2P8AFFINEINVQBZ256rrikz:
6629 case VGF2P8AFFINEINVQBZrmbi:
6630 case VGF2P8AFFINEINVQBZrmbik:
6631 case VGF2P8AFFINEINVQBZrmbikz:
6632 case VGF2P8AFFINEINVQBZrmi:
6633 case VGF2P8AFFINEINVQBZrmik:
6634 case VGF2P8AFFINEINVQBZrmikz:
6635 case VGF2P8AFFINEINVQBZrri:
6636 case VGF2P8AFFINEINVQBZrrik:
6637 case VGF2P8AFFINEINVQBZrrikz:
6638 case VGF2P8AFFINEINVQBrmi:
6639 case VGF2P8AFFINEINVQBrri:
6640 return true;
6641 }
6642 return false;
6643}
6644
6645bool isSERIALIZE(unsigned Opcode) {
6646 return Opcode == SERIALIZE;
6647}
6648
6649bool isVPHADDWQ(unsigned Opcode) {
6650 switch (Opcode) {
6651 case VPHADDWQrm:
6652 case VPHADDWQrr:
6653 return true;
6654 }
6655 return false;
6656}
6657
6658bool isVRNDSCALESH(unsigned Opcode) {
6659 switch (Opcode) {
6660 case VRNDSCALESHZrmi_Int:
6661 case VRNDSCALESHZrmik_Int:
6662 case VRNDSCALESHZrmikz_Int:
6663 case VRNDSCALESHZrri_Int:
6664 case VRNDSCALESHZrrib_Int:
6665 case VRNDSCALESHZrribk_Int:
6666 case VRNDSCALESHZrribkz_Int:
6667 case VRNDSCALESHZrrik_Int:
6668 case VRNDSCALESHZrrikz_Int:
6669 return true;
6670 }
6671 return false;
6672}
6673
6674bool isAAA(unsigned Opcode) {
6675 return Opcode == AAA;
6676}
6677
6678bool isVADDBF16(unsigned Opcode) {
6679 switch (Opcode) {
6680 case VADDBF16Z128rm:
6681 case VADDBF16Z128rmb:
6682 case VADDBF16Z128rmbk:
6683 case VADDBF16Z128rmbkz:
6684 case VADDBF16Z128rmk:
6685 case VADDBF16Z128rmkz:
6686 case VADDBF16Z128rr:
6687 case VADDBF16Z128rrk:
6688 case VADDBF16Z128rrkz:
6689 case VADDBF16Z256rm:
6690 case VADDBF16Z256rmb:
6691 case VADDBF16Z256rmbk:
6692 case VADDBF16Z256rmbkz:
6693 case VADDBF16Z256rmk:
6694 case VADDBF16Z256rmkz:
6695 case VADDBF16Z256rr:
6696 case VADDBF16Z256rrk:
6697 case VADDBF16Z256rrkz:
6698 case VADDBF16Zrm:
6699 case VADDBF16Zrmb:
6700 case VADDBF16Zrmbk:
6701 case VADDBF16Zrmbkz:
6702 case VADDBF16Zrmk:
6703 case VADDBF16Zrmkz:
6704 case VADDBF16Zrr:
6705 case VADDBF16Zrrk:
6706 case VADDBF16Zrrkz:
6707 return true;
6708 }
6709 return false;
6710}
6711
6712bool isWRMSRLIST(unsigned Opcode) {
6713 return Opcode == WRMSRLIST;
6714}
6715
6716bool isVCVTPH2PSX(unsigned Opcode) {
6717 switch (Opcode) {
6718 case VCVTPH2PSXZ128rm:
6719 case VCVTPH2PSXZ128rmb:
6720 case VCVTPH2PSXZ128rmbk:
6721 case VCVTPH2PSXZ128rmbkz:
6722 case VCVTPH2PSXZ128rmk:
6723 case VCVTPH2PSXZ128rmkz:
6724 case VCVTPH2PSXZ128rr:
6725 case VCVTPH2PSXZ128rrk:
6726 case VCVTPH2PSXZ128rrkz:
6727 case VCVTPH2PSXZ256rm:
6728 case VCVTPH2PSXZ256rmb:
6729 case VCVTPH2PSXZ256rmbk:
6730 case VCVTPH2PSXZ256rmbkz:
6731 case VCVTPH2PSXZ256rmk:
6732 case VCVTPH2PSXZ256rmkz:
6733 case VCVTPH2PSXZ256rr:
6734 case VCVTPH2PSXZ256rrk:
6735 case VCVTPH2PSXZ256rrkz:
6736 case VCVTPH2PSXZrm:
6737 case VCVTPH2PSXZrmb:
6738 case VCVTPH2PSXZrmbk:
6739 case VCVTPH2PSXZrmbkz:
6740 case VCVTPH2PSXZrmk:
6741 case VCVTPH2PSXZrmkz:
6742 case VCVTPH2PSXZrr:
6743 case VCVTPH2PSXZrrb:
6744 case VCVTPH2PSXZrrbk:
6745 case VCVTPH2PSXZrrbkz:
6746 case VCVTPH2PSXZrrk:
6747 case VCVTPH2PSXZrrkz:
6748 return true;
6749 }
6750 return false;
6751}
6752
6753bool isVFMSUB231PH(unsigned Opcode) {
6754 switch (Opcode) {
6755 case VFMSUB231PHZ128m:
6756 case VFMSUB231PHZ128mb:
6757 case VFMSUB231PHZ128mbk:
6758 case VFMSUB231PHZ128mbkz:
6759 case VFMSUB231PHZ128mk:
6760 case VFMSUB231PHZ128mkz:
6761 case VFMSUB231PHZ128r:
6762 case VFMSUB231PHZ128rk:
6763 case VFMSUB231PHZ128rkz:
6764 case VFMSUB231PHZ256m:
6765 case VFMSUB231PHZ256mb:
6766 case VFMSUB231PHZ256mbk:
6767 case VFMSUB231PHZ256mbkz:
6768 case VFMSUB231PHZ256mk:
6769 case VFMSUB231PHZ256mkz:
6770 case VFMSUB231PHZ256r:
6771 case VFMSUB231PHZ256rk:
6772 case VFMSUB231PHZ256rkz:
6773 case VFMSUB231PHZm:
6774 case VFMSUB231PHZmb:
6775 case VFMSUB231PHZmbk:
6776 case VFMSUB231PHZmbkz:
6777 case VFMSUB231PHZmk:
6778 case VFMSUB231PHZmkz:
6779 case VFMSUB231PHZr:
6780 case VFMSUB231PHZrb:
6781 case VFMSUB231PHZrbk:
6782 case VFMSUB231PHZrbkz:
6783 case VFMSUB231PHZrk:
6784 case VFMSUB231PHZrkz:
6785 return true;
6786 }
6787 return false;
6788}
6789
6790bool isVGATHERQPD(unsigned Opcode) {
6791 switch (Opcode) {
6792 case VGATHERQPDYrm:
6793 case VGATHERQPDZ128rm:
6794 case VGATHERQPDZ256rm:
6795 case VGATHERQPDZrm:
6796 case VGATHERQPDrm:
6797 return true;
6798 }
6799 return false;
6800}
6801
6802bool isKADDB(unsigned Opcode) {
6803 return Opcode == KADDBkk;
6804}
6805
6806bool isCVTPD2PI(unsigned Opcode) {
6807 switch (Opcode) {
6808 case MMX_CVTPD2PIrm:
6809 case MMX_CVTPD2PIrr:
6810 return true;
6811 }
6812 return false;
6813}
6814
6815bool isVFNMSUB213PH(unsigned Opcode) {
6816 switch (Opcode) {
6817 case VFNMSUB213PHZ128m:
6818 case VFNMSUB213PHZ128mb:
6819 case VFNMSUB213PHZ128mbk:
6820 case VFNMSUB213PHZ128mbkz:
6821 case VFNMSUB213PHZ128mk:
6822 case VFNMSUB213PHZ128mkz:
6823 case VFNMSUB213PHZ128r:
6824 case VFNMSUB213PHZ128rk:
6825 case VFNMSUB213PHZ128rkz:
6826 case VFNMSUB213PHZ256m:
6827 case VFNMSUB213PHZ256mb:
6828 case VFNMSUB213PHZ256mbk:
6829 case VFNMSUB213PHZ256mbkz:
6830 case VFNMSUB213PHZ256mk:
6831 case VFNMSUB213PHZ256mkz:
6832 case VFNMSUB213PHZ256r:
6833 case VFNMSUB213PHZ256rk:
6834 case VFNMSUB213PHZ256rkz:
6835 case VFNMSUB213PHZm:
6836 case VFNMSUB213PHZmb:
6837 case VFNMSUB213PHZmbk:
6838 case VFNMSUB213PHZmbkz:
6839 case VFNMSUB213PHZmk:
6840 case VFNMSUB213PHZmkz:
6841 case VFNMSUB213PHZr:
6842 case VFNMSUB213PHZrb:
6843 case VFNMSUB213PHZrbk:
6844 case VFNMSUB213PHZrbkz:
6845 case VFNMSUB213PHZrk:
6846 case VFNMSUB213PHZrkz:
6847 return true;
6848 }
6849 return false;
6850}
6851
6852bool isVPCMPESTRI(unsigned Opcode) {
6853 switch (Opcode) {
6854 case VPCMPESTRIrmi:
6855 case VPCMPESTRIrri:
6856 return true;
6857 }
6858 return false;
6859}
6860
6861bool isVPSHRDW(unsigned Opcode) {
6862 switch (Opcode) {
6863 case VPSHRDWZ128rmi:
6864 case VPSHRDWZ128rmik:
6865 case VPSHRDWZ128rmikz:
6866 case VPSHRDWZ128rri:
6867 case VPSHRDWZ128rrik:
6868 case VPSHRDWZ128rrikz:
6869 case VPSHRDWZ256rmi:
6870 case VPSHRDWZ256rmik:
6871 case VPSHRDWZ256rmikz:
6872 case VPSHRDWZ256rri:
6873 case VPSHRDWZ256rrik:
6874 case VPSHRDWZ256rrikz:
6875 case VPSHRDWZrmi:
6876 case VPSHRDWZrmik:
6877 case VPSHRDWZrmikz:
6878 case VPSHRDWZrri:
6879 case VPSHRDWZrrik:
6880 case VPSHRDWZrrikz:
6881 return true;
6882 }
6883 return false;
6884}
6885
6886bool isXORPS(unsigned Opcode) {
6887 switch (Opcode) {
6888 case XORPSrm:
6889 case XORPSrr:
6890 return true;
6891 }
6892 return false;
6893}
6894
6895bool isPOP2(unsigned Opcode) {
6896 return Opcode == POP2;
6897}
6898
6899bool isRDMSRLIST(unsigned Opcode) {
6900 return Opcode == RDMSRLIST;
6901}
6902
6903bool isVPDPBUSD(unsigned Opcode) {
6904 switch (Opcode) {
6905 case VPDPBUSDYrm:
6906 case VPDPBUSDYrr:
6907 case VPDPBUSDZ128rm:
6908 case VPDPBUSDZ128rmb:
6909 case VPDPBUSDZ128rmbk:
6910 case VPDPBUSDZ128rmbkz:
6911 case VPDPBUSDZ128rmk:
6912 case VPDPBUSDZ128rmkz:
6913 case VPDPBUSDZ128rr:
6914 case VPDPBUSDZ128rrk:
6915 case VPDPBUSDZ128rrkz:
6916 case VPDPBUSDZ256rm:
6917 case VPDPBUSDZ256rmb:
6918 case VPDPBUSDZ256rmbk:
6919 case VPDPBUSDZ256rmbkz:
6920 case VPDPBUSDZ256rmk:
6921 case VPDPBUSDZ256rmkz:
6922 case VPDPBUSDZ256rr:
6923 case VPDPBUSDZ256rrk:
6924 case VPDPBUSDZ256rrkz:
6925 case VPDPBUSDZrm:
6926 case VPDPBUSDZrmb:
6927 case VPDPBUSDZrmbk:
6928 case VPDPBUSDZrmbkz:
6929 case VPDPBUSDZrmk:
6930 case VPDPBUSDZrmkz:
6931 case VPDPBUSDZrr:
6932 case VPDPBUSDZrrk:
6933 case VPDPBUSDZrrkz:
6934 case VPDPBUSDrm:
6935 case VPDPBUSDrr:
6936 return true;
6937 }
6938 return false;
6939}
6940
6941bool isVCMPPH(unsigned Opcode) {
6942 switch (Opcode) {
6943 case VCMPPHZ128rmbi:
6944 case VCMPPHZ128rmbik:
6945 case VCMPPHZ128rmi:
6946 case VCMPPHZ128rmik:
6947 case VCMPPHZ128rri:
6948 case VCMPPHZ128rrik:
6949 case VCMPPHZ256rmbi:
6950 case VCMPPHZ256rmbik:
6951 case VCMPPHZ256rmi:
6952 case VCMPPHZ256rmik:
6953 case VCMPPHZ256rri:
6954 case VCMPPHZ256rrik:
6955 case VCMPPHZrmbi:
6956 case VCMPPHZrmbik:
6957 case VCMPPHZrmi:
6958 case VCMPPHZrmik:
6959 case VCMPPHZrri:
6960 case VCMPPHZrrib:
6961 case VCMPPHZrribk:
6962 case VCMPPHZrrik:
6963 return true;
6964 }
6965 return false;
6966}
6967
6968bool isVANDNPD(unsigned Opcode) {
6969 switch (Opcode) {
6970 case VANDNPDYrm:
6971 case VANDNPDYrr:
6972 case VANDNPDZ128rm:
6973 case VANDNPDZ128rmb:
6974 case VANDNPDZ128rmbk:
6975 case VANDNPDZ128rmbkz:
6976 case VANDNPDZ128rmk:
6977 case VANDNPDZ128rmkz:
6978 case VANDNPDZ128rr:
6979 case VANDNPDZ128rrk:
6980 case VANDNPDZ128rrkz:
6981 case VANDNPDZ256rm:
6982 case VANDNPDZ256rmb:
6983 case VANDNPDZ256rmbk:
6984 case VANDNPDZ256rmbkz:
6985 case VANDNPDZ256rmk:
6986 case VANDNPDZ256rmkz:
6987 case VANDNPDZ256rr:
6988 case VANDNPDZ256rrk:
6989 case VANDNPDZ256rrkz:
6990 case VANDNPDZrm:
6991 case VANDNPDZrmb:
6992 case VANDNPDZrmbk:
6993 case VANDNPDZrmbkz:
6994 case VANDNPDZrmk:
6995 case VANDNPDZrmkz:
6996 case VANDNPDZrr:
6997 case VANDNPDZrrk:
6998 case VANDNPDZrrkz:
6999 case VANDNPDrm:
7000 case VANDNPDrr:
7001 return true;
7002 }
7003 return false;
7004}
7005
7006bool isSUB(unsigned Opcode) {
7007 switch (Opcode) {
7008 case SUB16i16:
7009 case SUB16mi:
7010 case SUB16mi8:
7011 case SUB16mi8_EVEX:
7012 case SUB16mi8_ND:
7013 case SUB16mi8_NF:
7014 case SUB16mi8_NF_ND:
7015 case SUB16mi_EVEX:
7016 case SUB16mi_ND:
7017 case SUB16mi_NF:
7018 case SUB16mi_NF_ND:
7019 case SUB16mr:
7020 case SUB16mr_EVEX:
7021 case SUB16mr_ND:
7022 case SUB16mr_NF:
7023 case SUB16mr_NF_ND:
7024 case SUB16ri:
7025 case SUB16ri8:
7026 case SUB16ri8_EVEX:
7027 case SUB16ri8_ND:
7028 case SUB16ri8_NF:
7029 case SUB16ri8_NF_ND:
7030 case SUB16ri_EVEX:
7031 case SUB16ri_ND:
7032 case SUB16ri_NF:
7033 case SUB16ri_NF_ND:
7034 case SUB16rm:
7035 case SUB16rm_EVEX:
7036 case SUB16rm_ND:
7037 case SUB16rm_NF:
7038 case SUB16rm_NF_ND:
7039 case SUB16rr:
7040 case SUB16rr_EVEX:
7041 case SUB16rr_EVEX_REV:
7042 case SUB16rr_ND:
7043 case SUB16rr_ND_REV:
7044 case SUB16rr_NF:
7045 case SUB16rr_NF_ND:
7046 case SUB16rr_NF_ND_REV:
7047 case SUB16rr_NF_REV:
7048 case SUB16rr_REV:
7049 case SUB32i32:
7050 case SUB32mi:
7051 case SUB32mi8:
7052 case SUB32mi8_EVEX:
7053 case SUB32mi8_ND:
7054 case SUB32mi8_NF:
7055 case SUB32mi8_NF_ND:
7056 case SUB32mi_EVEX:
7057 case SUB32mi_ND:
7058 case SUB32mi_NF:
7059 case SUB32mi_NF_ND:
7060 case SUB32mr:
7061 case SUB32mr_EVEX:
7062 case SUB32mr_ND:
7063 case SUB32mr_NF:
7064 case SUB32mr_NF_ND:
7065 case SUB32ri:
7066 case SUB32ri8:
7067 case SUB32ri8_EVEX:
7068 case SUB32ri8_ND:
7069 case SUB32ri8_NF:
7070 case SUB32ri8_NF_ND:
7071 case SUB32ri_EVEX:
7072 case SUB32ri_ND:
7073 case SUB32ri_NF:
7074 case SUB32ri_NF_ND:
7075 case SUB32rm:
7076 case SUB32rm_EVEX:
7077 case SUB32rm_ND:
7078 case SUB32rm_NF:
7079 case SUB32rm_NF_ND:
7080 case SUB32rr:
7081 case SUB32rr_EVEX:
7082 case SUB32rr_EVEX_REV:
7083 case SUB32rr_ND:
7084 case SUB32rr_ND_REV:
7085 case SUB32rr_NF:
7086 case SUB32rr_NF_ND:
7087 case SUB32rr_NF_ND_REV:
7088 case SUB32rr_NF_REV:
7089 case SUB32rr_REV:
7090 case SUB64i32:
7091 case SUB64mi32:
7092 case SUB64mi32_EVEX:
7093 case SUB64mi32_ND:
7094 case SUB64mi32_NF:
7095 case SUB64mi32_NF_ND:
7096 case SUB64mi8:
7097 case SUB64mi8_EVEX:
7098 case SUB64mi8_ND:
7099 case SUB64mi8_NF:
7100 case SUB64mi8_NF_ND:
7101 case SUB64mr:
7102 case SUB64mr_EVEX:
7103 case SUB64mr_ND:
7104 case SUB64mr_NF:
7105 case SUB64mr_NF_ND:
7106 case SUB64ri32:
7107 case SUB64ri32_EVEX:
7108 case SUB64ri32_ND:
7109 case SUB64ri32_NF:
7110 case SUB64ri32_NF_ND:
7111 case SUB64ri8:
7112 case SUB64ri8_EVEX:
7113 case SUB64ri8_ND:
7114 case SUB64ri8_NF:
7115 case SUB64ri8_NF_ND:
7116 case SUB64rm:
7117 case SUB64rm_EVEX:
7118 case SUB64rm_ND:
7119 case SUB64rm_NF:
7120 case SUB64rm_NF_ND:
7121 case SUB64rr:
7122 case SUB64rr_EVEX:
7123 case SUB64rr_EVEX_REV:
7124 case SUB64rr_ND:
7125 case SUB64rr_ND_REV:
7126 case SUB64rr_NF:
7127 case SUB64rr_NF_ND:
7128 case SUB64rr_NF_ND_REV:
7129 case SUB64rr_NF_REV:
7130 case SUB64rr_REV:
7131 case SUB8i8:
7132 case SUB8mi:
7133 case SUB8mi8:
7134 case SUB8mi_EVEX:
7135 case SUB8mi_ND:
7136 case SUB8mi_NF:
7137 case SUB8mi_NF_ND:
7138 case SUB8mr:
7139 case SUB8mr_EVEX:
7140 case SUB8mr_ND:
7141 case SUB8mr_NF:
7142 case SUB8mr_NF_ND:
7143 case SUB8ri:
7144 case SUB8ri8:
7145 case SUB8ri_EVEX:
7146 case SUB8ri_ND:
7147 case SUB8ri_NF:
7148 case SUB8ri_NF_ND:
7149 case SUB8rm:
7150 case SUB8rm_EVEX:
7151 case SUB8rm_ND:
7152 case SUB8rm_NF:
7153 case SUB8rm_NF_ND:
7154 case SUB8rr:
7155 case SUB8rr_EVEX:
7156 case SUB8rr_EVEX_REV:
7157 case SUB8rr_ND:
7158 case SUB8rr_ND_REV:
7159 case SUB8rr_NF:
7160 case SUB8rr_NF_ND:
7161 case SUB8rr_NF_ND_REV:
7162 case SUB8rr_NF_REV:
7163 case SUB8rr_REV:
7164 return true;
7165 }
7166 return false;
7167}
7168
7169bool isVRSQRT28PD(unsigned Opcode) {
7170 switch (Opcode) {
7171 case VRSQRT28PDZm:
7172 case VRSQRT28PDZmb:
7173 case VRSQRT28PDZmbk:
7174 case VRSQRT28PDZmbkz:
7175 case VRSQRT28PDZmk:
7176 case VRSQRT28PDZmkz:
7177 case VRSQRT28PDZr:
7178 case VRSQRT28PDZrb:
7179 case VRSQRT28PDZrbk:
7180 case VRSQRT28PDZrbkz:
7181 case VRSQRT28PDZrk:
7182 case VRSQRT28PDZrkz:
7183 return true;
7184 }
7185 return false;
7186}
7187
7188bool isVFNMADD132PH(unsigned Opcode) {
7189 switch (Opcode) {
7190 case VFNMADD132PHZ128m:
7191 case VFNMADD132PHZ128mb:
7192 case VFNMADD132PHZ128mbk:
7193 case VFNMADD132PHZ128mbkz:
7194 case VFNMADD132PHZ128mk:
7195 case VFNMADD132PHZ128mkz:
7196 case VFNMADD132PHZ128r:
7197 case VFNMADD132PHZ128rk:
7198 case VFNMADD132PHZ128rkz:
7199 case VFNMADD132PHZ256m:
7200 case VFNMADD132PHZ256mb:
7201 case VFNMADD132PHZ256mbk:
7202 case VFNMADD132PHZ256mbkz:
7203 case VFNMADD132PHZ256mk:
7204 case VFNMADD132PHZ256mkz:
7205 case VFNMADD132PHZ256r:
7206 case VFNMADD132PHZ256rk:
7207 case VFNMADD132PHZ256rkz:
7208 case VFNMADD132PHZm:
7209 case VFNMADD132PHZmb:
7210 case VFNMADD132PHZmbk:
7211 case VFNMADD132PHZmbkz:
7212 case VFNMADD132PHZmk:
7213 case VFNMADD132PHZmkz:
7214 case VFNMADD132PHZr:
7215 case VFNMADD132PHZrb:
7216 case VFNMADD132PHZrbk:
7217 case VFNMADD132PHZrbkz:
7218 case VFNMADD132PHZrk:
7219 case VFNMADD132PHZrkz:
7220 return true;
7221 }
7222 return false;
7223}
7224
7225bool isVPMACSSWW(unsigned Opcode) {
7226 switch (Opcode) {
7227 case VPMACSSWWrm:
7228 case VPMACSSWWrr:
7229 return true;
7230 }
7231 return false;
7232}
7233
7234bool isXSTORE(unsigned Opcode) {
7235 return Opcode == XSTORE;
7236}
7237
7238bool isVPROTQ(unsigned Opcode) {
7239 switch (Opcode) {
7240 case VPROTQmi:
7241 case VPROTQmr:
7242 case VPROTQri:
7243 case VPROTQrm:
7244 case VPROTQrr:
7245 case VPROTQrr_REV:
7246 return true;
7247 }
7248 return false;
7249}
7250
7251bool isVPHADDBD(unsigned Opcode) {
7252 switch (Opcode) {
7253 case VPHADDBDrm:
7254 case VPHADDBDrr:
7255 return true;
7256 }
7257 return false;
7258}
7259
7260bool isVPMAXSB(unsigned Opcode) {
7261 switch (Opcode) {
7262 case VPMAXSBYrm:
7263 case VPMAXSBYrr:
7264 case VPMAXSBZ128rm:
7265 case VPMAXSBZ128rmk:
7266 case VPMAXSBZ128rmkz:
7267 case VPMAXSBZ128rr:
7268 case VPMAXSBZ128rrk:
7269 case VPMAXSBZ128rrkz:
7270 case VPMAXSBZ256rm:
7271 case VPMAXSBZ256rmk:
7272 case VPMAXSBZ256rmkz:
7273 case VPMAXSBZ256rr:
7274 case VPMAXSBZ256rrk:
7275 case VPMAXSBZ256rrkz:
7276 case VPMAXSBZrm:
7277 case VPMAXSBZrmk:
7278 case VPMAXSBZrmkz:
7279 case VPMAXSBZrr:
7280 case VPMAXSBZrrk:
7281 case VPMAXSBZrrkz:
7282 case VPMAXSBrm:
7283 case VPMAXSBrr:
7284 return true;
7285 }
7286 return false;
7287}
7288
7289bool isVMOVDQU8(unsigned Opcode) {
7290 switch (Opcode) {
7291 case VMOVDQU8Z128mr:
7292 case VMOVDQU8Z128mrk:
7293 case VMOVDQU8Z128rm:
7294 case VMOVDQU8Z128rmk:
7295 case VMOVDQU8Z128rmkz:
7296 case VMOVDQU8Z128rr:
7297 case VMOVDQU8Z128rr_REV:
7298 case VMOVDQU8Z128rrk:
7299 case VMOVDQU8Z128rrk_REV:
7300 case VMOVDQU8Z128rrkz:
7301 case VMOVDQU8Z128rrkz_REV:
7302 case VMOVDQU8Z256mr:
7303 case VMOVDQU8Z256mrk:
7304 case VMOVDQU8Z256rm:
7305 case VMOVDQU8Z256rmk:
7306 case VMOVDQU8Z256rmkz:
7307 case VMOVDQU8Z256rr:
7308 case VMOVDQU8Z256rr_REV:
7309 case VMOVDQU8Z256rrk:
7310 case VMOVDQU8Z256rrk_REV:
7311 case VMOVDQU8Z256rrkz:
7312 case VMOVDQU8Z256rrkz_REV:
7313 case VMOVDQU8Zmr:
7314 case VMOVDQU8Zmrk:
7315 case VMOVDQU8Zrm:
7316 case VMOVDQU8Zrmk:
7317 case VMOVDQU8Zrmkz:
7318 case VMOVDQU8Zrr:
7319 case VMOVDQU8Zrr_REV:
7320 case VMOVDQU8Zrrk:
7321 case VMOVDQU8Zrrk_REV:
7322 case VMOVDQU8Zrrkz:
7323 case VMOVDQU8Zrrkz_REV:
7324 return true;
7325 }
7326 return false;
7327}
7328
7329bool isVPMOVSXWD(unsigned Opcode) {
7330 switch (Opcode) {
7331 case VPMOVSXWDYrm:
7332 case VPMOVSXWDYrr:
7333 case VPMOVSXWDZ128rm:
7334 case VPMOVSXWDZ128rmk:
7335 case VPMOVSXWDZ128rmkz:
7336 case VPMOVSXWDZ128rr:
7337 case VPMOVSXWDZ128rrk:
7338 case VPMOVSXWDZ128rrkz:
7339 case VPMOVSXWDZ256rm:
7340 case VPMOVSXWDZ256rmk:
7341 case VPMOVSXWDZ256rmkz:
7342 case VPMOVSXWDZ256rr:
7343 case VPMOVSXWDZ256rrk:
7344 case VPMOVSXWDZ256rrkz:
7345 case VPMOVSXWDZrm:
7346 case VPMOVSXWDZrmk:
7347 case VPMOVSXWDZrmkz:
7348 case VPMOVSXWDZrr:
7349 case VPMOVSXWDZrrk:
7350 case VPMOVSXWDZrrkz:
7351 case VPMOVSXWDrm:
7352 case VPMOVSXWDrr:
7353 return true;
7354 }
7355 return false;
7356}
7357
7358bool isVMINMAXPD(unsigned Opcode) {
7359 switch (Opcode) {
7360 case VMINMAXPDZ128rmbi:
7361 case VMINMAXPDZ128rmbik:
7362 case VMINMAXPDZ128rmbikz:
7363 case VMINMAXPDZ128rmi:
7364 case VMINMAXPDZ128rmik:
7365 case VMINMAXPDZ128rmikz:
7366 case VMINMAXPDZ128rri:
7367 case VMINMAXPDZ128rrik:
7368 case VMINMAXPDZ128rrikz:
7369 case VMINMAXPDZ256rmbi:
7370 case VMINMAXPDZ256rmbik:
7371 case VMINMAXPDZ256rmbikz:
7372 case VMINMAXPDZ256rmi:
7373 case VMINMAXPDZ256rmik:
7374 case VMINMAXPDZ256rmikz:
7375 case VMINMAXPDZ256rri:
7376 case VMINMAXPDZ256rrik:
7377 case VMINMAXPDZ256rrikz:
7378 case VMINMAXPDZrmbi:
7379 case VMINMAXPDZrmbik:
7380 case VMINMAXPDZrmbikz:
7381 case VMINMAXPDZrmi:
7382 case VMINMAXPDZrmik:
7383 case VMINMAXPDZrmikz:
7384 case VMINMAXPDZrri:
7385 case VMINMAXPDZrrib:
7386 case VMINMAXPDZrribk:
7387 case VMINMAXPDZrribkz:
7388 case VMINMAXPDZrrik:
7389 case VMINMAXPDZrrikz:
7390 return true;
7391 }
7392 return false;
7393}
7394
7395bool isSHA256RNDS2(unsigned Opcode) {
7396 switch (Opcode) {
7397 case SHA256RNDS2rm:
7398 case SHA256RNDS2rr:
7399 return true;
7400 }
7401 return false;
7402}
7403
7404bool isKANDB(unsigned Opcode) {
7405 return Opcode == KANDBkk;
7406}
7407
7408bool isTPAUSE(unsigned Opcode) {
7409 return Opcode == TPAUSE;
7410}
7411
7412bool isPUSH(unsigned Opcode) {
7413 switch (Opcode) {
7414 case PUSH16i:
7415 case PUSH16i8:
7416 case PUSH16r:
7417 case PUSH16rmm:
7418 case PUSH16rmr:
7419 case PUSH32i:
7420 case PUSH32i8:
7421 case PUSH32r:
7422 case PUSH32rmm:
7423 case PUSH32rmr:
7424 case PUSH64i32:
7425 case PUSH64i8:
7426 case PUSH64r:
7427 case PUSH64rmm:
7428 case PUSH64rmr:
7429 case PUSHCS16:
7430 case PUSHCS32:
7431 case PUSHDS16:
7432 case PUSHDS32:
7433 case PUSHES16:
7434 case PUSHES32:
7435 case PUSHFS16:
7436 case PUSHFS32:
7437 case PUSHFS64:
7438 case PUSHGS16:
7439 case PUSHGS32:
7440 case PUSHGS64:
7441 case PUSHSS16:
7442 case PUSHSS32:
7443 return true;
7444 }
7445 return false;
7446}
7447
7448bool isVRNDSCALESS(unsigned Opcode) {
7449 switch (Opcode) {
7450 case VRNDSCALESSZrmi_Int:
7451 case VRNDSCALESSZrmik_Int:
7452 case VRNDSCALESSZrmikz_Int:
7453 case VRNDSCALESSZrri_Int:
7454 case VRNDSCALESSZrrib_Int:
7455 case VRNDSCALESSZrribk_Int:
7456 case VRNDSCALESSZrribkz_Int:
7457 case VRNDSCALESSZrrik_Int:
7458 case VRNDSCALESSZrrikz_Int:
7459 return true;
7460 }
7461 return false;
7462}
7463
7464bool isVRNDSCALEBF16(unsigned Opcode) {
7465 switch (Opcode) {
7466 case VRNDSCALEBF16Z128rmbi:
7467 case VRNDSCALEBF16Z128rmbik:
7468 case VRNDSCALEBF16Z128rmbikz:
7469 case VRNDSCALEBF16Z128rmi:
7470 case VRNDSCALEBF16Z128rmik:
7471 case VRNDSCALEBF16Z128rmikz:
7472 case VRNDSCALEBF16Z128rri:
7473 case VRNDSCALEBF16Z128rrik:
7474 case VRNDSCALEBF16Z128rrikz:
7475 case VRNDSCALEBF16Z256rmbi:
7476 case VRNDSCALEBF16Z256rmbik:
7477 case VRNDSCALEBF16Z256rmbikz:
7478 case VRNDSCALEBF16Z256rmi:
7479 case VRNDSCALEBF16Z256rmik:
7480 case VRNDSCALEBF16Z256rmikz:
7481 case VRNDSCALEBF16Z256rri:
7482 case VRNDSCALEBF16Z256rrik:
7483 case VRNDSCALEBF16Z256rrikz:
7484 case VRNDSCALEBF16Zrmbi:
7485 case VRNDSCALEBF16Zrmbik:
7486 case VRNDSCALEBF16Zrmbikz:
7487 case VRNDSCALEBF16Zrmi:
7488 case VRNDSCALEBF16Zrmik:
7489 case VRNDSCALEBF16Zrmikz:
7490 case VRNDSCALEBF16Zrri:
7491 case VRNDSCALEBF16Zrrik:
7492 case VRNDSCALEBF16Zrrikz:
7493 return true;
7494 }
7495 return false;
7496}
7497
7498bool isVPCMPISTRI(unsigned Opcode) {
7499 switch (Opcode) {
7500 case VPCMPISTRIrmi:
7501 case VPCMPISTRIrri:
7502 return true;
7503 }
7504 return false;
7505}
7506
7507bool isSTGI(unsigned Opcode) {
7508 return Opcode == STGI;
7509}
7510
7511bool isSBB(unsigned Opcode) {
7512 switch (Opcode) {
7513 case SBB16i16:
7514 case SBB16mi:
7515 case SBB16mi8:
7516 case SBB16mi8_EVEX:
7517 case SBB16mi8_ND:
7518 case SBB16mi_EVEX:
7519 case SBB16mi_ND:
7520 case SBB16mr:
7521 case SBB16mr_EVEX:
7522 case SBB16mr_ND:
7523 case SBB16ri:
7524 case SBB16ri8:
7525 case SBB16ri8_EVEX:
7526 case SBB16ri8_ND:
7527 case SBB16ri_EVEX:
7528 case SBB16ri_ND:
7529 case SBB16rm:
7530 case SBB16rm_EVEX:
7531 case SBB16rm_ND:
7532 case SBB16rr:
7533 case SBB16rr_EVEX:
7534 case SBB16rr_EVEX_REV:
7535 case SBB16rr_ND:
7536 case SBB16rr_ND_REV:
7537 case SBB16rr_REV:
7538 case SBB32i32:
7539 case SBB32mi:
7540 case SBB32mi8:
7541 case SBB32mi8_EVEX:
7542 case SBB32mi8_ND:
7543 case SBB32mi_EVEX:
7544 case SBB32mi_ND:
7545 case SBB32mr:
7546 case SBB32mr_EVEX:
7547 case SBB32mr_ND:
7548 case SBB32ri:
7549 case SBB32ri8:
7550 case SBB32ri8_EVEX:
7551 case SBB32ri8_ND:
7552 case SBB32ri_EVEX:
7553 case SBB32ri_ND:
7554 case SBB32rm:
7555 case SBB32rm_EVEX:
7556 case SBB32rm_ND:
7557 case SBB32rr:
7558 case SBB32rr_EVEX:
7559 case SBB32rr_EVEX_REV:
7560 case SBB32rr_ND:
7561 case SBB32rr_ND_REV:
7562 case SBB32rr_REV:
7563 case SBB64i32:
7564 case SBB64mi32:
7565 case SBB64mi32_EVEX:
7566 case SBB64mi32_ND:
7567 case SBB64mi8:
7568 case SBB64mi8_EVEX:
7569 case SBB64mi8_ND:
7570 case SBB64mr:
7571 case SBB64mr_EVEX:
7572 case SBB64mr_ND:
7573 case SBB64ri32:
7574 case SBB64ri32_EVEX:
7575 case SBB64ri32_ND:
7576 case SBB64ri8:
7577 case SBB64ri8_EVEX:
7578 case SBB64ri8_ND:
7579 case SBB64rm:
7580 case SBB64rm_EVEX:
7581 case SBB64rm_ND:
7582 case SBB64rr:
7583 case SBB64rr_EVEX:
7584 case SBB64rr_EVEX_REV:
7585 case SBB64rr_ND:
7586 case SBB64rr_ND_REV:
7587 case SBB64rr_REV:
7588 case SBB8i8:
7589 case SBB8mi:
7590 case SBB8mi8:
7591 case SBB8mi_EVEX:
7592 case SBB8mi_ND:
7593 case SBB8mr:
7594 case SBB8mr_EVEX:
7595 case SBB8mr_ND:
7596 case SBB8ri:
7597 case SBB8ri8:
7598 case SBB8ri_EVEX:
7599 case SBB8ri_ND:
7600 case SBB8rm:
7601 case SBB8rm_EVEX:
7602 case SBB8rm_ND:
7603 case SBB8rr:
7604 case SBB8rr_EVEX:
7605 case SBB8rr_EVEX_REV:
7606 case SBB8rr_ND:
7607 case SBB8rr_ND_REV:
7608 case SBB8rr_REV:
7609 return true;
7610 }
7611 return false;
7612}
7613
7614bool isBLCS(unsigned Opcode) {
7615 switch (Opcode) {
7616 case BLCS32rm:
7617 case BLCS32rr:
7618 case BLCS64rm:
7619 case BLCS64rr:
7620 return true;
7621 }
7622 return false;
7623}
7624
7625bool isVCVTSD2SH(unsigned Opcode) {
7626 switch (Opcode) {
7627 case VCVTSD2SHZrm_Int:
7628 case VCVTSD2SHZrmk_Int:
7629 case VCVTSD2SHZrmkz_Int:
7630 case VCVTSD2SHZrr_Int:
7631 case VCVTSD2SHZrrb_Int:
7632 case VCVTSD2SHZrrbk_Int:
7633 case VCVTSD2SHZrrbkz_Int:
7634 case VCVTSD2SHZrrk_Int:
7635 case VCVTSD2SHZrrkz_Int:
7636 return true;
7637 }
7638 return false;
7639}
7640
7641bool isVPERMW(unsigned Opcode) {
7642 switch (Opcode) {
7643 case VPERMWZ128rm:
7644 case VPERMWZ128rmk:
7645 case VPERMWZ128rmkz:
7646 case VPERMWZ128rr:
7647 case VPERMWZ128rrk:
7648 case VPERMWZ128rrkz:
7649 case VPERMWZ256rm:
7650 case VPERMWZ256rmk:
7651 case VPERMWZ256rmkz:
7652 case VPERMWZ256rr:
7653 case VPERMWZ256rrk:
7654 case VPERMWZ256rrkz:
7655 case VPERMWZrm:
7656 case VPERMWZrmk:
7657 case VPERMWZrmkz:
7658 case VPERMWZrr:
7659 case VPERMWZrrk:
7660 case VPERMWZrrkz:
7661 return true;
7662 }
7663 return false;
7664}
7665
7666bool isXRESLDTRK(unsigned Opcode) {
7667 return Opcode == XRESLDTRK;
7668}
7669
7670bool isAESENC256KL(unsigned Opcode) {
7671 return Opcode == AESENC256KL;
7672}
7673
7674bool isVGATHERDPD(unsigned Opcode) {
7675 switch (Opcode) {
7676 case VGATHERDPDYrm:
7677 case VGATHERDPDZ128rm:
7678 case VGATHERDPDZ256rm:
7679 case VGATHERDPDZrm:
7680 case VGATHERDPDrm:
7681 return true;
7682 }
7683 return false;
7684}
7685
7686bool isHRESET(unsigned Opcode) {
7687 return Opcode == HRESET;
7688}
7689
7690bool isVFMSUBADD231PD(unsigned Opcode) {
7691 switch (Opcode) {
7692 case VFMSUBADD231PDYm:
7693 case VFMSUBADD231PDYr:
7694 case VFMSUBADD231PDZ128m:
7695 case VFMSUBADD231PDZ128mb:
7696 case VFMSUBADD231PDZ128mbk:
7697 case VFMSUBADD231PDZ128mbkz:
7698 case VFMSUBADD231PDZ128mk:
7699 case VFMSUBADD231PDZ128mkz:
7700 case VFMSUBADD231PDZ128r:
7701 case VFMSUBADD231PDZ128rk:
7702 case VFMSUBADD231PDZ128rkz:
7703 case VFMSUBADD231PDZ256m:
7704 case VFMSUBADD231PDZ256mb:
7705 case VFMSUBADD231PDZ256mbk:
7706 case VFMSUBADD231PDZ256mbkz:
7707 case VFMSUBADD231PDZ256mk:
7708 case VFMSUBADD231PDZ256mkz:
7709 case VFMSUBADD231PDZ256r:
7710 case VFMSUBADD231PDZ256rk:
7711 case VFMSUBADD231PDZ256rkz:
7712 case VFMSUBADD231PDZm:
7713 case VFMSUBADD231PDZmb:
7714 case VFMSUBADD231PDZmbk:
7715 case VFMSUBADD231PDZmbkz:
7716 case VFMSUBADD231PDZmk:
7717 case VFMSUBADD231PDZmkz:
7718 case VFMSUBADD231PDZr:
7719 case VFMSUBADD231PDZrb:
7720 case VFMSUBADD231PDZrbk:
7721 case VFMSUBADD231PDZrbkz:
7722 case VFMSUBADD231PDZrk:
7723 case VFMSUBADD231PDZrkz:
7724 case VFMSUBADD231PDm:
7725 case VFMSUBADD231PDr:
7726 return true;
7727 }
7728 return false;
7729}
7730
7731bool isVFRCZSS(unsigned Opcode) {
7732 switch (Opcode) {
7733 case VFRCZSSrm:
7734 case VFRCZSSrr:
7735 return true;
7736 }
7737 return false;
7738}
7739
7740bool isMINPS(unsigned Opcode) {
7741 switch (Opcode) {
7742 case MINPSrm:
7743 case MINPSrr:
7744 return true;
7745 }
7746 return false;
7747}
7748
7749bool isFPREM1(unsigned Opcode) {
7750 return Opcode == FPREM1;
7751}
7752
7753bool isVPCMPUB(unsigned Opcode) {
7754 switch (Opcode) {
7755 case VPCMPUBZ128rmi:
7756 case VPCMPUBZ128rmik:
7757 case VPCMPUBZ128rri:
7758 case VPCMPUBZ128rrik:
7759 case VPCMPUBZ256rmi:
7760 case VPCMPUBZ256rmik:
7761 case VPCMPUBZ256rri:
7762 case VPCMPUBZ256rrik:
7763 case VPCMPUBZrmi:
7764 case VPCMPUBZrmik:
7765 case VPCMPUBZrri:
7766 case VPCMPUBZrrik:
7767 return true;
7768 }
7769 return false;
7770}
7771
7772bool isVSQRTPD(unsigned Opcode) {
7773 switch (Opcode) {
7774 case VSQRTPDYm:
7775 case VSQRTPDYr:
7776 case VSQRTPDZ128m:
7777 case VSQRTPDZ128mb:
7778 case VSQRTPDZ128mbk:
7779 case VSQRTPDZ128mbkz:
7780 case VSQRTPDZ128mk:
7781 case VSQRTPDZ128mkz:
7782 case VSQRTPDZ128r:
7783 case VSQRTPDZ128rk:
7784 case VSQRTPDZ128rkz:
7785 case VSQRTPDZ256m:
7786 case VSQRTPDZ256mb:
7787 case VSQRTPDZ256mbk:
7788 case VSQRTPDZ256mbkz:
7789 case VSQRTPDZ256mk:
7790 case VSQRTPDZ256mkz:
7791 case VSQRTPDZ256r:
7792 case VSQRTPDZ256rk:
7793 case VSQRTPDZ256rkz:
7794 case VSQRTPDZm:
7795 case VSQRTPDZmb:
7796 case VSQRTPDZmbk:
7797 case VSQRTPDZmbkz:
7798 case VSQRTPDZmk:
7799 case VSQRTPDZmkz:
7800 case VSQRTPDZr:
7801 case VSQRTPDZrb:
7802 case VSQRTPDZrbk:
7803 case VSQRTPDZrbkz:
7804 case VSQRTPDZrk:
7805 case VSQRTPDZrkz:
7806 case VSQRTPDm:
7807 case VSQRTPDr:
7808 return true;
7809 }
7810 return false;
7811}
7812
7813bool isVFRCZPS(unsigned Opcode) {
7814 switch (Opcode) {
7815 case VFRCZPSYrm:
7816 case VFRCZPSYrr:
7817 case VFRCZPSrm:
7818 case VFRCZPSrr:
7819 return true;
7820 }
7821 return false;
7822}
7823
7824bool isVFNMADD213SS(unsigned Opcode) {
7825 switch (Opcode) {
7826 case VFNMADD213SSZm_Int:
7827 case VFNMADD213SSZmk_Int:
7828 case VFNMADD213SSZmkz_Int:
7829 case VFNMADD213SSZr_Int:
7830 case VFNMADD213SSZrb_Int:
7831 case VFNMADD213SSZrbk_Int:
7832 case VFNMADD213SSZrbkz_Int:
7833 case VFNMADD213SSZrk_Int:
7834 case VFNMADD213SSZrkz_Int:
7835 case VFNMADD213SSm_Int:
7836 case VFNMADD213SSr_Int:
7837 return true;
7838 }
7839 return false;
7840}
7841
7842bool isVPSHRDVQ(unsigned Opcode) {
7843 switch (Opcode) {
7844 case VPSHRDVQZ128m:
7845 case VPSHRDVQZ128mb:
7846 case VPSHRDVQZ128mbk:
7847 case VPSHRDVQZ128mbkz:
7848 case VPSHRDVQZ128mk:
7849 case VPSHRDVQZ128mkz:
7850 case VPSHRDVQZ128r:
7851 case VPSHRDVQZ128rk:
7852 case VPSHRDVQZ128rkz:
7853 case VPSHRDVQZ256m:
7854 case VPSHRDVQZ256mb:
7855 case VPSHRDVQZ256mbk:
7856 case VPSHRDVQZ256mbkz:
7857 case VPSHRDVQZ256mk:
7858 case VPSHRDVQZ256mkz:
7859 case VPSHRDVQZ256r:
7860 case VPSHRDVQZ256rk:
7861 case VPSHRDVQZ256rkz:
7862 case VPSHRDVQZm:
7863 case VPSHRDVQZmb:
7864 case VPSHRDVQZmbk:
7865 case VPSHRDVQZmbkz:
7866 case VPSHRDVQZmk:
7867 case VPSHRDVQZmkz:
7868 case VPSHRDVQZr:
7869 case VPSHRDVQZrk:
7870 case VPSHRDVQZrkz:
7871 return true;
7872 }
7873 return false;
7874}
7875
7876bool isVPMOVDW(unsigned Opcode) {
7877 switch (Opcode) {
7878 case VPMOVDWZ128mr:
7879 case VPMOVDWZ128mrk:
7880 case VPMOVDWZ128rr:
7881 case VPMOVDWZ128rrk:
7882 case VPMOVDWZ128rrkz:
7883 case VPMOVDWZ256mr:
7884 case VPMOVDWZ256mrk:
7885 case VPMOVDWZ256rr:
7886 case VPMOVDWZ256rrk:
7887 case VPMOVDWZ256rrkz:
7888 case VPMOVDWZmr:
7889 case VPMOVDWZmrk:
7890 case VPMOVDWZrr:
7891 case VPMOVDWZrrk:
7892 case VPMOVDWZrrkz:
7893 return true;
7894 }
7895 return false;
7896}
7897
7898bool isVCVTPH2HF8S(unsigned Opcode) {
7899 switch (Opcode) {
7900 case VCVTPH2HF8SZ128rm:
7901 case VCVTPH2HF8SZ128rmb:
7902 case VCVTPH2HF8SZ128rmbk:
7903 case VCVTPH2HF8SZ128rmbkz:
7904 case VCVTPH2HF8SZ128rmk:
7905 case VCVTPH2HF8SZ128rmkz:
7906 case VCVTPH2HF8SZ128rr:
7907 case VCVTPH2HF8SZ128rrk:
7908 case VCVTPH2HF8SZ128rrkz:
7909 case VCVTPH2HF8SZ256rm:
7910 case VCVTPH2HF8SZ256rmb:
7911 case VCVTPH2HF8SZ256rmbk:
7912 case VCVTPH2HF8SZ256rmbkz:
7913 case VCVTPH2HF8SZ256rmk:
7914 case VCVTPH2HF8SZ256rmkz:
7915 case VCVTPH2HF8SZ256rr:
7916 case VCVTPH2HF8SZ256rrk:
7917 case VCVTPH2HF8SZ256rrkz:
7918 case VCVTPH2HF8SZrm:
7919 case VCVTPH2HF8SZrmb:
7920 case VCVTPH2HF8SZrmbk:
7921 case VCVTPH2HF8SZrmbkz:
7922 case VCVTPH2HF8SZrmk:
7923 case VCVTPH2HF8SZrmkz:
7924 case VCVTPH2HF8SZrr:
7925 case VCVTPH2HF8SZrrk:
7926 case VCVTPH2HF8SZrrkz:
7927 return true;
7928 }
7929 return false;
7930}
7931
7932bool isVBROADCASTSD(unsigned Opcode) {
7933 switch (Opcode) {
7934 case VBROADCASTSDYrm:
7935 case VBROADCASTSDYrr:
7936 case VBROADCASTSDZ256rm:
7937 case VBROADCASTSDZ256rmk:
7938 case VBROADCASTSDZ256rmkz:
7939 case VBROADCASTSDZ256rr:
7940 case VBROADCASTSDZ256rrk:
7941 case VBROADCASTSDZ256rrkz:
7942 case VBROADCASTSDZrm:
7943 case VBROADCASTSDZrmk:
7944 case VBROADCASTSDZrmkz:
7945 case VBROADCASTSDZrr:
7946 case VBROADCASTSDZrrk:
7947 case VBROADCASTSDZrrkz:
7948 return true;
7949 }
7950 return false;
7951}
7952
7953bool isVSHUFPD(unsigned Opcode) {
7954 switch (Opcode) {
7955 case VSHUFPDYrmi:
7956 case VSHUFPDYrri:
7957 case VSHUFPDZ128rmbi:
7958 case VSHUFPDZ128rmbik:
7959 case VSHUFPDZ128rmbikz:
7960 case VSHUFPDZ128rmi:
7961 case VSHUFPDZ128rmik:
7962 case VSHUFPDZ128rmikz:
7963 case VSHUFPDZ128rri:
7964 case VSHUFPDZ128rrik:
7965 case VSHUFPDZ128rrikz:
7966 case VSHUFPDZ256rmbi:
7967 case VSHUFPDZ256rmbik:
7968 case VSHUFPDZ256rmbikz:
7969 case VSHUFPDZ256rmi:
7970 case VSHUFPDZ256rmik:
7971 case VSHUFPDZ256rmikz:
7972 case VSHUFPDZ256rri:
7973 case VSHUFPDZ256rrik:
7974 case VSHUFPDZ256rrikz:
7975 case VSHUFPDZrmbi:
7976 case VSHUFPDZrmbik:
7977 case VSHUFPDZrmbikz:
7978 case VSHUFPDZrmi:
7979 case VSHUFPDZrmik:
7980 case VSHUFPDZrmikz:
7981 case VSHUFPDZrri:
7982 case VSHUFPDZrrik:
7983 case VSHUFPDZrrikz:
7984 case VSHUFPDrmi:
7985 case VSHUFPDrri:
7986 return true;
7987 }
7988 return false;
7989}
7990
7991bool isVPSUBSW(unsigned Opcode) {
7992 switch (Opcode) {
7993 case VPSUBSWYrm:
7994 case VPSUBSWYrr:
7995 case VPSUBSWZ128rm:
7996 case VPSUBSWZ128rmk:
7997 case VPSUBSWZ128rmkz:
7998 case VPSUBSWZ128rr:
7999 case VPSUBSWZ128rrk:
8000 case VPSUBSWZ128rrkz:
8001 case VPSUBSWZ256rm:
8002 case VPSUBSWZ256rmk:
8003 case VPSUBSWZ256rmkz:
8004 case VPSUBSWZ256rr:
8005 case VPSUBSWZ256rrk:
8006 case VPSUBSWZ256rrkz:
8007 case VPSUBSWZrm:
8008 case VPSUBSWZrmk:
8009 case VPSUBSWZrmkz:
8010 case VPSUBSWZrr:
8011 case VPSUBSWZrrk:
8012 case VPSUBSWZrrkz:
8013 case VPSUBSWrm:
8014 case VPSUBSWrr:
8015 return true;
8016 }
8017 return false;
8018}
8019
8020bool isKUNPCKBW(unsigned Opcode) {
8021 return Opcode == KUNPCKBWkk;
8022}
8023
8024bool isVPBLENDD(unsigned Opcode) {
8025 switch (Opcode) {
8026 case VPBLENDDYrmi:
8027 case VPBLENDDYrri:
8028 case VPBLENDDrmi:
8029 case VPBLENDDrri:
8030 return true;
8031 }
8032 return false;
8033}
8034
8035bool isUNPCKHPD(unsigned Opcode) {
8036 switch (Opcode) {
8037 case UNPCKHPDrm:
8038 case UNPCKHPDrr:
8039 return true;
8040 }
8041 return false;
8042}
8043
8044bool isVFNMADD231SD(unsigned Opcode) {
8045 switch (Opcode) {
8046 case VFNMADD231SDZm_Int:
8047 case VFNMADD231SDZmk_Int:
8048 case VFNMADD231SDZmkz_Int:
8049 case VFNMADD231SDZr_Int:
8050 case VFNMADD231SDZrb_Int:
8051 case VFNMADD231SDZrbk_Int:
8052 case VFNMADD231SDZrbkz_Int:
8053 case VFNMADD231SDZrk_Int:
8054 case VFNMADD231SDZrkz_Int:
8055 case VFNMADD231SDm_Int:
8056 case VFNMADD231SDr_Int:
8057 return true;
8058 }
8059 return false;
8060}
8061
8062bool isVPBROADCASTMW2D(unsigned Opcode) {
8063 switch (Opcode) {
8064 case VPBROADCASTMW2DZ128rr:
8065 case VPBROADCASTMW2DZ256rr:
8066 case VPBROADCASTMW2DZrr:
8067 return true;
8068 }
8069 return false;
8070}
8071
8072bool isVCVTBF82PS(unsigned Opcode) {
8073 switch (Opcode) {
8074 case VCVTBF82PSZ128rm:
8075 case VCVTBF82PSZ128rmk:
8076 case VCVTBF82PSZ128rmkz:
8077 case VCVTBF82PSZ128rr:
8078 case VCVTBF82PSZ128rrk:
8079 case VCVTBF82PSZ128rrkz:
8080 case VCVTBF82PSZ256rm:
8081 case VCVTBF82PSZ256rmk:
8082 case VCVTBF82PSZ256rmkz:
8083 case VCVTBF82PSZ256rr:
8084 case VCVTBF82PSZ256rrk:
8085 case VCVTBF82PSZ256rrkz:
8086 case VCVTBF82PSZrm:
8087 case VCVTBF82PSZrmk:
8088 case VCVTBF82PSZrmkz:
8089 case VCVTBF82PSZrr:
8090 case VCVTBF82PSZrrk:
8091 case VCVTBF82PSZrrkz:
8092 return true;
8093 }
8094 return false;
8095}
8096
8097bool isVPMULTISHIFTQB(unsigned Opcode) {
8098 switch (Opcode) {
8099 case VPMULTISHIFTQBZ128rm:
8100 case VPMULTISHIFTQBZ128rmb:
8101 case VPMULTISHIFTQBZ128rmbk:
8102 case VPMULTISHIFTQBZ128rmbkz:
8103 case VPMULTISHIFTQBZ128rmk:
8104 case VPMULTISHIFTQBZ128rmkz:
8105 case VPMULTISHIFTQBZ128rr:
8106 case VPMULTISHIFTQBZ128rrk:
8107 case VPMULTISHIFTQBZ128rrkz:
8108 case VPMULTISHIFTQBZ256rm:
8109 case VPMULTISHIFTQBZ256rmb:
8110 case VPMULTISHIFTQBZ256rmbk:
8111 case VPMULTISHIFTQBZ256rmbkz:
8112 case VPMULTISHIFTQBZ256rmk:
8113 case VPMULTISHIFTQBZ256rmkz:
8114 case VPMULTISHIFTQBZ256rr:
8115 case VPMULTISHIFTQBZ256rrk:
8116 case VPMULTISHIFTQBZ256rrkz:
8117 case VPMULTISHIFTQBZrm:
8118 case VPMULTISHIFTQBZrmb:
8119 case VPMULTISHIFTQBZrmbk:
8120 case VPMULTISHIFTQBZrmbkz:
8121 case VPMULTISHIFTQBZrmk:
8122 case VPMULTISHIFTQBZrmkz:
8123 case VPMULTISHIFTQBZrr:
8124 case VPMULTISHIFTQBZrrk:
8125 case VPMULTISHIFTQBZrrkz:
8126 return true;
8127 }
8128 return false;
8129}
8130
8131bool isVP2INTERSECTQ(unsigned Opcode) {
8132 switch (Opcode) {
8133 case VP2INTERSECTQZ128rm:
8134 case VP2INTERSECTQZ128rmb:
8135 case VP2INTERSECTQZ128rr:
8136 case VP2INTERSECTQZ256rm:
8137 case VP2INTERSECTQZ256rmb:
8138 case VP2INTERSECTQZ256rr:
8139 case VP2INTERSECTQZrm:
8140 case VP2INTERSECTQZrmb:
8141 case VP2INTERSECTQZrr:
8142 return true;
8143 }
8144 return false;
8145}
8146
8147bool isVFNMSUB132BF16(unsigned Opcode) {
8148 switch (Opcode) {
8149 case VFNMSUB132BF16Z128m:
8150 case VFNMSUB132BF16Z128mb:
8151 case VFNMSUB132BF16Z128mbk:
8152 case VFNMSUB132BF16Z128mbkz:
8153 case VFNMSUB132BF16Z128mk:
8154 case VFNMSUB132BF16Z128mkz:
8155 case VFNMSUB132BF16Z128r:
8156 case VFNMSUB132BF16Z128rk:
8157 case VFNMSUB132BF16Z128rkz:
8158 case VFNMSUB132BF16Z256m:
8159 case VFNMSUB132BF16Z256mb:
8160 case VFNMSUB132BF16Z256mbk:
8161 case VFNMSUB132BF16Z256mbkz:
8162 case VFNMSUB132BF16Z256mk:
8163 case VFNMSUB132BF16Z256mkz:
8164 case VFNMSUB132BF16Z256r:
8165 case VFNMSUB132BF16Z256rk:
8166 case VFNMSUB132BF16Z256rkz:
8167 case VFNMSUB132BF16Zm:
8168 case VFNMSUB132BF16Zmb:
8169 case VFNMSUB132BF16Zmbk:
8170 case VFNMSUB132BF16Zmbkz:
8171 case VFNMSUB132BF16Zmk:
8172 case VFNMSUB132BF16Zmkz:
8173 case VFNMSUB132BF16Zr:
8174 case VFNMSUB132BF16Zrk:
8175 case VFNMSUB132BF16Zrkz:
8176 return true;
8177 }
8178 return false;
8179}
8180
8181bool isVFMADD213BF16(unsigned Opcode) {
8182 switch (Opcode) {
8183 case VFMADD213BF16Z128m:
8184 case VFMADD213BF16Z128mb:
8185 case VFMADD213BF16Z128mbk:
8186 case VFMADD213BF16Z128mbkz:
8187 case VFMADD213BF16Z128mk:
8188 case VFMADD213BF16Z128mkz:
8189 case VFMADD213BF16Z128r:
8190 case VFMADD213BF16Z128rk:
8191 case VFMADD213BF16Z128rkz:
8192 case VFMADD213BF16Z256m:
8193 case VFMADD213BF16Z256mb:
8194 case VFMADD213BF16Z256mbk:
8195 case VFMADD213BF16Z256mbkz:
8196 case VFMADD213BF16Z256mk:
8197 case VFMADD213BF16Z256mkz:
8198 case VFMADD213BF16Z256r:
8199 case VFMADD213BF16Z256rk:
8200 case VFMADD213BF16Z256rkz:
8201 case VFMADD213BF16Zm:
8202 case VFMADD213BF16Zmb:
8203 case VFMADD213BF16Zmbk:
8204 case VFMADD213BF16Zmbkz:
8205 case VFMADD213BF16Zmk:
8206 case VFMADD213BF16Zmkz:
8207 case VFMADD213BF16Zr:
8208 case VFMADD213BF16Zrk:
8209 case VFMADD213BF16Zrkz:
8210 return true;
8211 }
8212 return false;
8213}
8214
8215bool isVPUNPCKHWD(unsigned Opcode) {
8216 switch (Opcode) {
8217 case VPUNPCKHWDYrm:
8218 case VPUNPCKHWDYrr:
8219 case VPUNPCKHWDZ128rm:
8220 case VPUNPCKHWDZ128rmk:
8221 case VPUNPCKHWDZ128rmkz:
8222 case VPUNPCKHWDZ128rr:
8223 case VPUNPCKHWDZ128rrk:
8224 case VPUNPCKHWDZ128rrkz:
8225 case VPUNPCKHWDZ256rm:
8226 case VPUNPCKHWDZ256rmk:
8227 case VPUNPCKHWDZ256rmkz:
8228 case VPUNPCKHWDZ256rr:
8229 case VPUNPCKHWDZ256rrk:
8230 case VPUNPCKHWDZ256rrkz:
8231 case VPUNPCKHWDZrm:
8232 case VPUNPCKHWDZrmk:
8233 case VPUNPCKHWDZrmkz:
8234 case VPUNPCKHWDZrr:
8235 case VPUNPCKHWDZrrk:
8236 case VPUNPCKHWDZrrkz:
8237 case VPUNPCKHWDrm:
8238 case VPUNPCKHWDrr:
8239 return true;
8240 }
8241 return false;
8242}
8243
8244bool isVPERM2F128(unsigned Opcode) {
8245 switch (Opcode) {
8246 case VPERM2F128rmi:
8247 case VPERM2F128rri:
8248 return true;
8249 }
8250 return false;
8251}
8252
8253bool isINSD(unsigned Opcode) {
8254 return Opcode == INSL;
8255}
8256
8257bool isLFS(unsigned Opcode) {
8258 switch (Opcode) {
8259 case LFS16rm:
8260 case LFS32rm:
8261 case LFS64rm:
8262 return true;
8263 }
8264 return false;
8265}
8266
8267bool isFMULP(unsigned Opcode) {
8268 return Opcode == MUL_FPrST0;
8269}
8270
8271bool isCWD(unsigned Opcode) {
8272 return Opcode == CWD;
8273}
8274
8275bool isVDIVSS(unsigned Opcode) {
8276 switch (Opcode) {
8277 case VDIVSSZrm_Int:
8278 case VDIVSSZrmk_Int:
8279 case VDIVSSZrmkz_Int:
8280 case VDIVSSZrr_Int:
8281 case VDIVSSZrrb_Int:
8282 case VDIVSSZrrbk_Int:
8283 case VDIVSSZrrbkz_Int:
8284 case VDIVSSZrrk_Int:
8285 case VDIVSSZrrkz_Int:
8286 case VDIVSSrm_Int:
8287 case VDIVSSrr_Int:
8288 return true;
8289 }
8290 return false;
8291}
8292
8293bool isVPSRLQ(unsigned Opcode) {
8294 switch (Opcode) {
8295 case VPSRLQYri:
8296 case VPSRLQYrm:
8297 case VPSRLQYrr:
8298 case VPSRLQZ128mbi:
8299 case VPSRLQZ128mbik:
8300 case VPSRLQZ128mbikz:
8301 case VPSRLQZ128mi:
8302 case VPSRLQZ128mik:
8303 case VPSRLQZ128mikz:
8304 case VPSRLQZ128ri:
8305 case VPSRLQZ128rik:
8306 case VPSRLQZ128rikz:
8307 case VPSRLQZ128rm:
8308 case VPSRLQZ128rmk:
8309 case VPSRLQZ128rmkz:
8310 case VPSRLQZ128rr:
8311 case VPSRLQZ128rrk:
8312 case VPSRLQZ128rrkz:
8313 case VPSRLQZ256mbi:
8314 case VPSRLQZ256mbik:
8315 case VPSRLQZ256mbikz:
8316 case VPSRLQZ256mi:
8317 case VPSRLQZ256mik:
8318 case VPSRLQZ256mikz:
8319 case VPSRLQZ256ri:
8320 case VPSRLQZ256rik:
8321 case VPSRLQZ256rikz:
8322 case VPSRLQZ256rm:
8323 case VPSRLQZ256rmk:
8324 case VPSRLQZ256rmkz:
8325 case VPSRLQZ256rr:
8326 case VPSRLQZ256rrk:
8327 case VPSRLQZ256rrkz:
8328 case VPSRLQZmbi:
8329 case VPSRLQZmbik:
8330 case VPSRLQZmbikz:
8331 case VPSRLQZmi:
8332 case VPSRLQZmik:
8333 case VPSRLQZmikz:
8334 case VPSRLQZri:
8335 case VPSRLQZrik:
8336 case VPSRLQZrikz:
8337 case VPSRLQZrm:
8338 case VPSRLQZrmk:
8339 case VPSRLQZrmkz:
8340 case VPSRLQZrr:
8341 case VPSRLQZrrk:
8342 case VPSRLQZrrkz:
8343 case VPSRLQri:
8344 case VPSRLQrm:
8345 case VPSRLQrr:
8346 return true;
8347 }
8348 return false;
8349}
8350
8351bool isFSQRT(unsigned Opcode) {
8352 return Opcode == SQRT_F;
8353}
8354
8355bool isJRCXZ(unsigned Opcode) {
8356 return Opcode == JRCXZ;
8357}
8358
8359bool isVPMOVMSKB(unsigned Opcode) {
8360 switch (Opcode) {
8361 case VPMOVMSKBYrr:
8362 case VPMOVMSKBrr:
8363 return true;
8364 }
8365 return false;
8366}
8367
8368bool isAESDEC256KL(unsigned Opcode) {
8369 return Opcode == AESDEC256KL;
8370}
8371
8372bool isFLDENV(unsigned Opcode) {
8373 return Opcode == FLDENVm;
8374}
8375
8376bool isVPHSUBWD(unsigned Opcode) {
8377 switch (Opcode) {
8378 case VPHSUBWDrm:
8379 case VPHSUBWDrr:
8380 return true;
8381 }
8382 return false;
8383}
8384
8385bool isWBNOINVD(unsigned Opcode) {
8386 return Opcode == WBNOINVD;
8387}
8388
8389bool isVEXPANDPD(unsigned Opcode) {
8390 switch (Opcode) {
8391 case VEXPANDPDZ128rm:
8392 case VEXPANDPDZ128rmk:
8393 case VEXPANDPDZ128rmkz:
8394 case VEXPANDPDZ128rr:
8395 case VEXPANDPDZ128rrk:
8396 case VEXPANDPDZ128rrkz:
8397 case VEXPANDPDZ256rm:
8398 case VEXPANDPDZ256rmk:
8399 case VEXPANDPDZ256rmkz:
8400 case VEXPANDPDZ256rr:
8401 case VEXPANDPDZ256rrk:
8402 case VEXPANDPDZ256rrkz:
8403 case VEXPANDPDZrm:
8404 case VEXPANDPDZrmk:
8405 case VEXPANDPDZrmkz:
8406 case VEXPANDPDZrr:
8407 case VEXPANDPDZrrk:
8408 case VEXPANDPDZrrkz:
8409 return true;
8410 }
8411 return false;
8412}
8413
8414bool isFYL2XP1(unsigned Opcode) {
8415 return Opcode == FYL2XP1;
8416}
8417
8418bool isPREFETCHT2(unsigned Opcode) {
8419 return Opcode == PREFETCHT2;
8420}
8421
8422bool isVPDPBSUDS(unsigned Opcode) {
8423 switch (Opcode) {
8424 case VPDPBSUDSYrm:
8425 case VPDPBSUDSYrr:
8426 case VPDPBSUDSZ128rm:
8427 case VPDPBSUDSZ128rmb:
8428 case VPDPBSUDSZ128rmbk:
8429 case VPDPBSUDSZ128rmbkz:
8430 case VPDPBSUDSZ128rmk:
8431 case VPDPBSUDSZ128rmkz:
8432 case VPDPBSUDSZ128rr:
8433 case VPDPBSUDSZ128rrk:
8434 case VPDPBSUDSZ128rrkz:
8435 case VPDPBSUDSZ256rm:
8436 case VPDPBSUDSZ256rmb:
8437 case VPDPBSUDSZ256rmbk:
8438 case VPDPBSUDSZ256rmbkz:
8439 case VPDPBSUDSZ256rmk:
8440 case VPDPBSUDSZ256rmkz:
8441 case VPDPBSUDSZ256rr:
8442 case VPDPBSUDSZ256rrk:
8443 case VPDPBSUDSZ256rrkz:
8444 case VPDPBSUDSZrm:
8445 case VPDPBSUDSZrmb:
8446 case VPDPBSUDSZrmbk:
8447 case VPDPBSUDSZrmbkz:
8448 case VPDPBSUDSZrmk:
8449 case VPDPBSUDSZrmkz:
8450 case VPDPBSUDSZrr:
8451 case VPDPBSUDSZrrk:
8452 case VPDPBSUDSZrrkz:
8453 case VPDPBSUDSrm:
8454 case VPDPBSUDSrr:
8455 return true;
8456 }
8457 return false;
8458}
8459
8460bool isVSHA512MSG2(unsigned Opcode) {
8461 return Opcode == VSHA512MSG2rr;
8462}
8463
8464bool isVCVTBIASPS2HF8(unsigned Opcode) {
8465 switch (Opcode) {
8466 case VCVTBIASPS2HF8Z128rm:
8467 case VCVTBIASPS2HF8Z128rmb:
8468 case VCVTBIASPS2HF8Z128rmbk:
8469 case VCVTBIASPS2HF8Z128rmbkz:
8470 case VCVTBIASPS2HF8Z128rmk:
8471 case VCVTBIASPS2HF8Z128rmkz:
8472 case VCVTBIASPS2HF8Z128rr:
8473 case VCVTBIASPS2HF8Z128rrk:
8474 case VCVTBIASPS2HF8Z128rrkz:
8475 case VCVTBIASPS2HF8Z256rm:
8476 case VCVTBIASPS2HF8Z256rmb:
8477 case VCVTBIASPS2HF8Z256rmbk:
8478 case VCVTBIASPS2HF8Z256rmbkz:
8479 case VCVTBIASPS2HF8Z256rmk:
8480 case VCVTBIASPS2HF8Z256rmkz:
8481 case VCVTBIASPS2HF8Z256rr:
8482 case VCVTBIASPS2HF8Z256rrk:
8483 case VCVTBIASPS2HF8Z256rrkz:
8484 case VCVTBIASPS2HF8Zrm:
8485 case VCVTBIASPS2HF8Zrmb:
8486 case VCVTBIASPS2HF8Zrmbk:
8487 case VCVTBIASPS2HF8Zrmbkz:
8488 case VCVTBIASPS2HF8Zrmk:
8489 case VCVTBIASPS2HF8Zrmkz:
8490 case VCVTBIASPS2HF8Zrr:
8491 case VCVTBIASPS2HF8Zrrk:
8492 case VCVTBIASPS2HF8Zrrkz:
8493 return true;
8494 }
8495 return false;
8496}
8497
8498bool isPMULHUW(unsigned Opcode) {
8499 switch (Opcode) {
8500 case MMX_PMULHUWrm:
8501 case MMX_PMULHUWrr:
8502 case PMULHUWrm:
8503 case PMULHUWrr:
8504 return true;
8505 }
8506 return false;
8507}
8508
8509bool isKANDNB(unsigned Opcode) {
8510 return Opcode == KANDNBkk;
8511}
8512
8513bool isVCVTUW2PH(unsigned Opcode) {
8514 switch (Opcode) {
8515 case VCVTUW2PHZ128rm:
8516 case VCVTUW2PHZ128rmb:
8517 case VCVTUW2PHZ128rmbk:
8518 case VCVTUW2PHZ128rmbkz:
8519 case VCVTUW2PHZ128rmk:
8520 case VCVTUW2PHZ128rmkz:
8521 case VCVTUW2PHZ128rr:
8522 case VCVTUW2PHZ128rrk:
8523 case VCVTUW2PHZ128rrkz:
8524 case VCVTUW2PHZ256rm:
8525 case VCVTUW2PHZ256rmb:
8526 case VCVTUW2PHZ256rmbk:
8527 case VCVTUW2PHZ256rmbkz:
8528 case VCVTUW2PHZ256rmk:
8529 case VCVTUW2PHZ256rmkz:
8530 case VCVTUW2PHZ256rr:
8531 case VCVTUW2PHZ256rrk:
8532 case VCVTUW2PHZ256rrkz:
8533 case VCVTUW2PHZrm:
8534 case VCVTUW2PHZrmb:
8535 case VCVTUW2PHZrmbk:
8536 case VCVTUW2PHZrmbkz:
8537 case VCVTUW2PHZrmk:
8538 case VCVTUW2PHZrmkz:
8539 case VCVTUW2PHZrr:
8540 case VCVTUW2PHZrrb:
8541 case VCVTUW2PHZrrbk:
8542 case VCVTUW2PHZrrbkz:
8543 case VCVTUW2PHZrrk:
8544 case VCVTUW2PHZrrkz:
8545 return true;
8546 }
8547 return false;
8548}
8549
8550bool isAESDECWIDE256KL(unsigned Opcode) {
8551 return Opcode == AESDECWIDE256KL;
8552}
8553
8554bool isVPGATHERDD(unsigned Opcode) {
8555 switch (Opcode) {
8556 case VPGATHERDDYrm:
8557 case VPGATHERDDZ128rm:
8558 case VPGATHERDDZ256rm:
8559 case VPGATHERDDZrm:
8560 case VPGATHERDDrm:
8561 return true;
8562 }
8563 return false;
8564}
8565
8566bool isVREDUCESH(unsigned Opcode) {
8567 switch (Opcode) {
8568 case VREDUCESHZrmi:
8569 case VREDUCESHZrmik:
8570 case VREDUCESHZrmikz:
8571 case VREDUCESHZrri:
8572 case VREDUCESHZrrib:
8573 case VREDUCESHZrribk:
8574 case VREDUCESHZrribkz:
8575 case VREDUCESHZrrik:
8576 case VREDUCESHZrrikz:
8577 return true;
8578 }
8579 return false;
8580}
8581
8582bool isPOPFQ(unsigned Opcode) {
8583 return Opcode == POPF64;
8584}
8585
8586bool isPAVGUSB(unsigned Opcode) {
8587 switch (Opcode) {
8588 case PAVGUSBrm:
8589 case PAVGUSBrr:
8590 return true;
8591 }
8592 return false;
8593}
8594
8595bool isVALIGND(unsigned Opcode) {
8596 switch (Opcode) {
8597 case VALIGNDZ128rmbi:
8598 case VALIGNDZ128rmbik:
8599 case VALIGNDZ128rmbikz:
8600 case VALIGNDZ128rmi:
8601 case VALIGNDZ128rmik:
8602 case VALIGNDZ128rmikz:
8603 case VALIGNDZ128rri:
8604 case VALIGNDZ128rrik:
8605 case VALIGNDZ128rrikz:
8606 case VALIGNDZ256rmbi:
8607 case VALIGNDZ256rmbik:
8608 case VALIGNDZ256rmbikz:
8609 case VALIGNDZ256rmi:
8610 case VALIGNDZ256rmik:
8611 case VALIGNDZ256rmikz:
8612 case VALIGNDZ256rri:
8613 case VALIGNDZ256rrik:
8614 case VALIGNDZ256rrikz:
8615 case VALIGNDZrmbi:
8616 case VALIGNDZrmbik:
8617 case VALIGNDZrmbikz:
8618 case VALIGNDZrmi:
8619 case VALIGNDZrmik:
8620 case VALIGNDZrmikz:
8621 case VALIGNDZrri:
8622 case VALIGNDZrrik:
8623 case VALIGNDZrrikz:
8624 return true;
8625 }
8626 return false;
8627}
8628
8629bool isVPHMINPOSUW(unsigned Opcode) {
8630 switch (Opcode) {
8631 case VPHMINPOSUWrm:
8632 case VPHMINPOSUWrr:
8633 return true;
8634 }
8635 return false;
8636}
8637
8638bool isLIDTD(unsigned Opcode) {
8639 return Opcode == LIDT32m;
8640}
8641
8642bool isVPERMT2PD(unsigned Opcode) {
8643 switch (Opcode) {
8644 case VPERMT2PDZ128rm:
8645 case VPERMT2PDZ128rmb:
8646 case VPERMT2PDZ128rmbk:
8647 case VPERMT2PDZ128rmbkz:
8648 case VPERMT2PDZ128rmk:
8649 case VPERMT2PDZ128rmkz:
8650 case VPERMT2PDZ128rr:
8651 case VPERMT2PDZ128rrk:
8652 case VPERMT2PDZ128rrkz:
8653 case VPERMT2PDZ256rm:
8654 case VPERMT2PDZ256rmb:
8655 case VPERMT2PDZ256rmbk:
8656 case VPERMT2PDZ256rmbkz:
8657 case VPERMT2PDZ256rmk:
8658 case VPERMT2PDZ256rmkz:
8659 case VPERMT2PDZ256rr:
8660 case VPERMT2PDZ256rrk:
8661 case VPERMT2PDZ256rrkz:
8662 case VPERMT2PDZrm:
8663 case VPERMT2PDZrmb:
8664 case VPERMT2PDZrmbk:
8665 case VPERMT2PDZrmbkz:
8666 case VPERMT2PDZrmk:
8667 case VPERMT2PDZrmkz:
8668 case VPERMT2PDZrr:
8669 case VPERMT2PDZrrk:
8670 case VPERMT2PDZrrkz:
8671 return true;
8672 }
8673 return false;
8674}
8675
8676bool isVMLAUNCH(unsigned Opcode) {
8677 return Opcode == VMLAUNCH;
8678}
8679
8680bool isVPXORQ(unsigned Opcode) {
8681 switch (Opcode) {
8682 case VPXORQZ128rm:
8683 case VPXORQZ128rmb:
8684 case VPXORQZ128rmbk:
8685 case VPXORQZ128rmbkz:
8686 case VPXORQZ128rmk:
8687 case VPXORQZ128rmkz:
8688 case VPXORQZ128rr:
8689 case VPXORQZ128rrk:
8690 case VPXORQZ128rrkz:
8691 case VPXORQZ256rm:
8692 case VPXORQZ256rmb:
8693 case VPXORQZ256rmbk:
8694 case VPXORQZ256rmbkz:
8695 case VPXORQZ256rmk:
8696 case VPXORQZ256rmkz:
8697 case VPXORQZ256rr:
8698 case VPXORQZ256rrk:
8699 case VPXORQZ256rrkz:
8700 case VPXORQZrm:
8701 case VPXORQZrmb:
8702 case VPXORQZrmbk:
8703 case VPXORQZrmbkz:
8704 case VPXORQZrmk:
8705 case VPXORQZrmkz:
8706 case VPXORQZrr:
8707 case VPXORQZrrk:
8708 case VPXORQZrrkz:
8709 return true;
8710 }
8711 return false;
8712}
8713
8714bool isMOVNTDQ(unsigned Opcode) {
8715 return Opcode == MOVNTDQmr;
8716}
8717
8718bool isPOP2P(unsigned Opcode) {
8719 return Opcode == POP2P;
8720}
8721
8722bool isVADDPD(unsigned Opcode) {
8723 switch (Opcode) {
8724 case VADDPDYrm:
8725 case VADDPDYrr:
8726 case VADDPDZ128rm:
8727 case VADDPDZ128rmb:
8728 case VADDPDZ128rmbk:
8729 case VADDPDZ128rmbkz:
8730 case VADDPDZ128rmk:
8731 case VADDPDZ128rmkz:
8732 case VADDPDZ128rr:
8733 case VADDPDZ128rrk:
8734 case VADDPDZ128rrkz:
8735 case VADDPDZ256rm:
8736 case VADDPDZ256rmb:
8737 case VADDPDZ256rmbk:
8738 case VADDPDZ256rmbkz:
8739 case VADDPDZ256rmk:
8740 case VADDPDZ256rmkz:
8741 case VADDPDZ256rr:
8742 case VADDPDZ256rrk:
8743 case VADDPDZ256rrkz:
8744 case VADDPDZrm:
8745 case VADDPDZrmb:
8746 case VADDPDZrmbk:
8747 case VADDPDZrmbkz:
8748 case VADDPDZrmk:
8749 case VADDPDZrmkz:
8750 case VADDPDZrr:
8751 case VADDPDZrrb:
8752 case VADDPDZrrbk:
8753 case VADDPDZrrbkz:
8754 case VADDPDZrrk:
8755 case VADDPDZrrkz:
8756 case VADDPDrm:
8757 case VADDPDrr:
8758 return true;
8759 }
8760 return false;
8761}
8762
8763bool isSMSW(unsigned Opcode) {
8764 switch (Opcode) {
8765 case SMSW16m:
8766 case SMSW16r:
8767 case SMSW32r:
8768 case SMSW64r:
8769 return true;
8770 }
8771 return false;
8772}
8773
8774bool isVEXP2PD(unsigned Opcode) {
8775 switch (Opcode) {
8776 case VEXP2PDZm:
8777 case VEXP2PDZmb:
8778 case VEXP2PDZmbk:
8779 case VEXP2PDZmbkz:
8780 case VEXP2PDZmk:
8781 case VEXP2PDZmkz:
8782 case VEXP2PDZr:
8783 case VEXP2PDZrb:
8784 case VEXP2PDZrbk:
8785 case VEXP2PDZrbkz:
8786 case VEXP2PDZrk:
8787 case VEXP2PDZrkz:
8788 return true;
8789 }
8790 return false;
8791}
8792
8793bool isPMULUDQ(unsigned Opcode) {
8794 switch (Opcode) {
8795 case MMX_PMULUDQrm:
8796 case MMX_PMULUDQrr:
8797 case PMULUDQrm:
8798 case PMULUDQrr:
8799 return true;
8800 }
8801 return false;
8802}
8803
8804bool isIRET(unsigned Opcode) {
8805 return Opcode == IRET16;
8806}
8807
8808bool isMULPS(unsigned Opcode) {
8809 switch (Opcode) {
8810 case MULPSrm:
8811 case MULPSrr:
8812 return true;
8813 }
8814 return false;
8815}
8816
8817bool isTDPBF8PS(unsigned Opcode) {
8818 return Opcode == TDPBF8PS;
8819}
8820
8821bool isVFNMSUBPD(unsigned Opcode) {
8822 switch (Opcode) {
8823 case VFNMSUBPD4Ymr:
8824 case VFNMSUBPD4Yrm:
8825 case VFNMSUBPD4Yrr:
8826 case VFNMSUBPD4Yrr_REV:
8827 case VFNMSUBPD4mr:
8828 case VFNMSUBPD4rm:
8829 case VFNMSUBPD4rr:
8830 case VFNMSUBPD4rr_REV:
8831 return true;
8832 }
8833 return false;
8834}
8835
8836bool isPHADDW(unsigned Opcode) {
8837 switch (Opcode) {
8838 case MMX_PHADDWrm:
8839 case MMX_PHADDWrr:
8840 case PHADDWrm:
8841 case PHADDWrr:
8842 return true;
8843 }
8844 return false;
8845}
8846
8847bool isRDSEED(unsigned Opcode) {
8848 switch (Opcode) {
8849 case RDSEED16r:
8850 case RDSEED32r:
8851 case RDSEED64r:
8852 return true;
8853 }
8854 return false;
8855}
8856
8857bool isVPSHLW(unsigned Opcode) {
8858 switch (Opcode) {
8859 case VPSHLWmr:
8860 case VPSHLWrm:
8861 case VPSHLWrr:
8862 case VPSHLWrr_REV:
8863 return true;
8864 }
8865 return false;
8866}
8867
8868bool isRMPUPDATE(unsigned Opcode) {
8869 return Opcode == RMPUPDATE;
8870}
8871
8872bool isVFMADD231PH(unsigned Opcode) {
8873 switch (Opcode) {
8874 case VFMADD231PHZ128m:
8875 case VFMADD231PHZ128mb:
8876 case VFMADD231PHZ128mbk:
8877 case VFMADD231PHZ128mbkz:
8878 case VFMADD231PHZ128mk:
8879 case VFMADD231PHZ128mkz:
8880 case VFMADD231PHZ128r:
8881 case VFMADD231PHZ128rk:
8882 case VFMADD231PHZ128rkz:
8883 case VFMADD231PHZ256m:
8884 case VFMADD231PHZ256mb:
8885 case VFMADD231PHZ256mbk:
8886 case VFMADD231PHZ256mbkz:
8887 case VFMADD231PHZ256mk:
8888 case VFMADD231PHZ256mkz:
8889 case VFMADD231PHZ256r:
8890 case VFMADD231PHZ256rk:
8891 case VFMADD231PHZ256rkz:
8892 case VFMADD231PHZm:
8893 case VFMADD231PHZmb:
8894 case VFMADD231PHZmbk:
8895 case VFMADD231PHZmbkz:
8896 case VFMADD231PHZmk:
8897 case VFMADD231PHZmkz:
8898 case VFMADD231PHZr:
8899 case VFMADD231PHZrb:
8900 case VFMADD231PHZrbk:
8901 case VFMADD231PHZrbkz:
8902 case VFMADD231PHZrk:
8903 case VFMADD231PHZrkz:
8904 return true;
8905 }
8906 return false;
8907}
8908
8909bool isVPSHAD(unsigned Opcode) {
8910 switch (Opcode) {
8911 case VPSHADmr:
8912 case VPSHADrm:
8913 case VPSHADrr:
8914 case VPSHADrr_REV:
8915 return true;
8916 }
8917 return false;
8918}
8919
8920bool isCLWB(unsigned Opcode) {
8921 return Opcode == CLWB;
8922}
8923
8924bool isPSUBUSB(unsigned Opcode) {
8925 switch (Opcode) {
8926 case MMX_PSUBUSBrm:
8927 case MMX_PSUBUSBrr:
8928 case PSUBUSBrm:
8929 case PSUBUSBrr:
8930 return true;
8931 }
8932 return false;
8933}
8934
8935bool isVCVTTSD2USI(unsigned Opcode) {
8936 switch (Opcode) {
8937 case VCVTTSD2USI64Zrm_Int:
8938 case VCVTTSD2USI64Zrr_Int:
8939 case VCVTTSD2USI64Zrrb_Int:
8940 case VCVTTSD2USIZrm_Int:
8941 case VCVTTSD2USIZrr_Int:
8942 case VCVTTSD2USIZrrb_Int:
8943 return true;
8944 }
8945 return false;
8946}
8947
8948bool isVEXTRACTPS(unsigned Opcode) {
8949 switch (Opcode) {
8950 case VEXTRACTPSZmri:
8951 case VEXTRACTPSZrri:
8952 case VEXTRACTPSmri:
8953 case VEXTRACTPSrri:
8954 return true;
8955 }
8956 return false;
8957}
8958
8959bool isMOVLPD(unsigned Opcode) {
8960 switch (Opcode) {
8961 case MOVLPDmr:
8962 case MOVLPDrm:
8963 return true;
8964 }
8965 return false;
8966}
8967
8968bool isLGDTD(unsigned Opcode) {
8969 return Opcode == LGDT32m;
8970}
8971
8972bool isVPBROADCASTMB2Q(unsigned Opcode) {
8973 switch (Opcode) {
8974 case VPBROADCASTMB2QZ128rr:
8975 case VPBROADCASTMB2QZ256rr:
8976 case VPBROADCASTMB2QZrr:
8977 return true;
8978 }
8979 return false;
8980}
8981
8982bool isOUT(unsigned Opcode) {
8983 switch (Opcode) {
8984 case OUT16ir:
8985 case OUT16rr:
8986 case OUT32ir:
8987 case OUT32rr:
8988 case OUT8ir:
8989 case OUT8rr:
8990 return true;
8991 }
8992 return false;
8993}
8994
8995bool isVMSAVE(unsigned Opcode) {
8996 switch (Opcode) {
8997 case VMSAVE32:
8998 case VMSAVE64:
8999 return true;
9000 }
9001 return false;
9002}
9003
9004bool isVCVTQQ2PD(unsigned Opcode) {
9005 switch (Opcode) {
9006 case VCVTQQ2PDZ128rm:
9007 case VCVTQQ2PDZ128rmb:
9008 case VCVTQQ2PDZ128rmbk:
9009 case VCVTQQ2PDZ128rmbkz:
9010 case VCVTQQ2PDZ128rmk:
9011 case VCVTQQ2PDZ128rmkz:
9012 case VCVTQQ2PDZ128rr:
9013 case VCVTQQ2PDZ128rrk:
9014 case VCVTQQ2PDZ128rrkz:
9015 case VCVTQQ2PDZ256rm:
9016 case VCVTQQ2PDZ256rmb:
9017 case VCVTQQ2PDZ256rmbk:
9018 case VCVTQQ2PDZ256rmbkz:
9019 case VCVTQQ2PDZ256rmk:
9020 case VCVTQQ2PDZ256rmkz:
9021 case VCVTQQ2PDZ256rr:
9022 case VCVTQQ2PDZ256rrk:
9023 case VCVTQQ2PDZ256rrkz:
9024 case VCVTQQ2PDZrm:
9025 case VCVTQQ2PDZrmb:
9026 case VCVTQQ2PDZrmbk:
9027 case VCVTQQ2PDZrmbkz:
9028 case VCVTQQ2PDZrmk:
9029 case VCVTQQ2PDZrmkz:
9030 case VCVTQQ2PDZrr:
9031 case VCVTQQ2PDZrrb:
9032 case VCVTQQ2PDZrrbk:
9033 case VCVTQQ2PDZrrbkz:
9034 case VCVTQQ2PDZrrk:
9035 case VCVTQQ2PDZrrkz:
9036 return true;
9037 }
9038 return false;
9039}
9040
9041bool isVFMADD213PH(unsigned Opcode) {
9042 switch (Opcode) {
9043 case VFMADD213PHZ128m:
9044 case VFMADD213PHZ128mb:
9045 case VFMADD213PHZ128mbk:
9046 case VFMADD213PHZ128mbkz:
9047 case VFMADD213PHZ128mk:
9048 case VFMADD213PHZ128mkz:
9049 case VFMADD213PHZ128r:
9050 case VFMADD213PHZ128rk:
9051 case VFMADD213PHZ128rkz:
9052 case VFMADD213PHZ256m:
9053 case VFMADD213PHZ256mb:
9054 case VFMADD213PHZ256mbk:
9055 case VFMADD213PHZ256mbkz:
9056 case VFMADD213PHZ256mk:
9057 case VFMADD213PHZ256mkz:
9058 case VFMADD213PHZ256r:
9059 case VFMADD213PHZ256rk:
9060 case VFMADD213PHZ256rkz:
9061 case VFMADD213PHZm:
9062 case VFMADD213PHZmb:
9063 case VFMADD213PHZmbk:
9064 case VFMADD213PHZmbkz:
9065 case VFMADD213PHZmk:
9066 case VFMADD213PHZmkz:
9067 case VFMADD213PHZr:
9068 case VFMADD213PHZrb:
9069 case VFMADD213PHZrbk:
9070 case VFMADD213PHZrbkz:
9071 case VFMADD213PHZrk:
9072 case VFMADD213PHZrkz:
9073 return true;
9074 }
9075 return false;
9076}
9077
9078bool isFCMOVBE(unsigned Opcode) {
9079 return Opcode == CMOVBE_F;
9080}
9081
9082bool isMOVSHDUP(unsigned Opcode) {
9083 switch (Opcode) {
9084 case MOVSHDUPrm:
9085 case MOVSHDUPrr:
9086 return true;
9087 }
9088 return false;
9089}
9090
9091bool isVPMOVUSQB(unsigned Opcode) {
9092 switch (Opcode) {
9093 case VPMOVUSQBZ128mr:
9094 case VPMOVUSQBZ128mrk:
9095 case VPMOVUSQBZ128rr:
9096 case VPMOVUSQBZ128rrk:
9097 case VPMOVUSQBZ128rrkz:
9098 case VPMOVUSQBZ256mr:
9099 case VPMOVUSQBZ256mrk:
9100 case VPMOVUSQBZ256rr:
9101 case VPMOVUSQBZ256rrk:
9102 case VPMOVUSQBZ256rrkz:
9103 case VPMOVUSQBZmr:
9104 case VPMOVUSQBZmrk:
9105 case VPMOVUSQBZrr:
9106 case VPMOVUSQBZrrk:
9107 case VPMOVUSQBZrrkz:
9108 return true;
9109 }
9110 return false;
9111}
9112
9113bool isFIST(unsigned Opcode) {
9114 switch (Opcode) {
9115 case IST_F16m:
9116 case IST_F32m:
9117 return true;
9118 }
9119 return false;
9120}
9121
9122bool isHADDPD(unsigned Opcode) {
9123 switch (Opcode) {
9124 case HADDPDrm:
9125 case HADDPDrr:
9126 return true;
9127 }
9128 return false;
9129}
9130
9131bool isPACKSSWB(unsigned Opcode) {
9132 switch (Opcode) {
9133 case MMX_PACKSSWBrm:
9134 case MMX_PACKSSWBrr:
9135 case PACKSSWBrm:
9136 case PACKSSWBrr:
9137 return true;
9138 }
9139 return false;
9140}
9141
9142bool isVPMACSSDQH(unsigned Opcode) {
9143 switch (Opcode) {
9144 case VPMACSSDQHrm:
9145 case VPMACSSDQHrr:
9146 return true;
9147 }
9148 return false;
9149}
9150
9151bool isVFNMSUB132SD(unsigned Opcode) {
9152 switch (Opcode) {
9153 case VFNMSUB132SDZm_Int:
9154 case VFNMSUB132SDZmk_Int:
9155 case VFNMSUB132SDZmkz_Int:
9156 case VFNMSUB132SDZr_Int:
9157 case VFNMSUB132SDZrb_Int:
9158 case VFNMSUB132SDZrbk_Int:
9159 case VFNMSUB132SDZrbkz_Int:
9160 case VFNMSUB132SDZrk_Int:
9161 case VFNMSUB132SDZrkz_Int:
9162 case VFNMSUB132SDm_Int:
9163 case VFNMSUB132SDr_Int:
9164 return true;
9165 }
9166 return false;
9167}
9168
9169bool isVPMASKMOVQ(unsigned Opcode) {
9170 switch (Opcode) {
9171 case VPMASKMOVQYmr:
9172 case VPMASKMOVQYrm:
9173 case VPMASKMOVQmr:
9174 case VPMASKMOVQrm:
9175 return true;
9176 }
9177 return false;
9178}
9179
9180bool isVCOMPRESSPD(unsigned Opcode) {
9181 switch (Opcode) {
9182 case VCOMPRESSPDZ128mr:
9183 case VCOMPRESSPDZ128mrk:
9184 case VCOMPRESSPDZ128rr:
9185 case VCOMPRESSPDZ128rrk:
9186 case VCOMPRESSPDZ128rrkz:
9187 case VCOMPRESSPDZ256mr:
9188 case VCOMPRESSPDZ256mrk:
9189 case VCOMPRESSPDZ256rr:
9190 case VCOMPRESSPDZ256rrk:
9191 case VCOMPRESSPDZ256rrkz:
9192 case VCOMPRESSPDZmr:
9193 case VCOMPRESSPDZmrk:
9194 case VCOMPRESSPDZrr:
9195 case VCOMPRESSPDZrrk:
9196 case VCOMPRESSPDZrrkz:
9197 return true;
9198 }
9199 return false;
9200}
9201
9202bool isVFMADD213SS(unsigned Opcode) {
9203 switch (Opcode) {
9204 case VFMADD213SSZm_Int:
9205 case VFMADD213SSZmk_Int:
9206 case VFMADD213SSZmkz_Int:
9207 case VFMADD213SSZr_Int:
9208 case VFMADD213SSZrb_Int:
9209 case VFMADD213SSZrbk_Int:
9210 case VFMADD213SSZrbkz_Int:
9211 case VFMADD213SSZrk_Int:
9212 case VFMADD213SSZrkz_Int:
9213 case VFMADD213SSm_Int:
9214 case VFMADD213SSr_Int:
9215 return true;
9216 }
9217 return false;
9218}
9219
9220bool isVPCMPQ(unsigned Opcode) {
9221 switch (Opcode) {
9222 case VPCMPQZ128rmbi:
9223 case VPCMPQZ128rmbik:
9224 case VPCMPQZ128rmi:
9225 case VPCMPQZ128rmik:
9226 case VPCMPQZ128rri:
9227 case VPCMPQZ128rrik:
9228 case VPCMPQZ256rmbi:
9229 case VPCMPQZ256rmbik:
9230 case VPCMPQZ256rmi:
9231 case VPCMPQZ256rmik:
9232 case VPCMPQZ256rri:
9233 case VPCMPQZ256rrik:
9234 case VPCMPQZrmbi:
9235 case VPCMPQZrmbik:
9236 case VPCMPQZrmi:
9237 case VPCMPQZrmik:
9238 case VPCMPQZrri:
9239 case VPCMPQZrrik:
9240 return true;
9241 }
9242 return false;
9243}
9244
9245bool isVADDSH(unsigned Opcode) {
9246 switch (Opcode) {
9247 case VADDSHZrm_Int:
9248 case VADDSHZrmk_Int:
9249 case VADDSHZrmkz_Int:
9250 case VADDSHZrr_Int:
9251 case VADDSHZrrb_Int:
9252 case VADDSHZrrbk_Int:
9253 case VADDSHZrrbkz_Int:
9254 case VADDSHZrrk_Int:
9255 case VADDSHZrrkz_Int:
9256 return true;
9257 }
9258 return false;
9259}
9260
9261bool isVFNMADDSD(unsigned Opcode) {
9262 switch (Opcode) {
9263 case VFNMADDSD4mr:
9264 case VFNMADDSD4rm:
9265 case VFNMADDSD4rr:
9266 case VFNMADDSD4rr_REV:
9267 return true;
9268 }
9269 return false;
9270}
9271
9272bool isUMWAIT(unsigned Opcode) {
9273 return Opcode == UMWAIT;
9274}
9275
9276bool isVPUNPCKHDQ(unsigned Opcode) {
9277 switch (Opcode) {
9278 case VPUNPCKHDQYrm:
9279 case VPUNPCKHDQYrr:
9280 case VPUNPCKHDQZ128rm:
9281 case VPUNPCKHDQZ128rmb:
9282 case VPUNPCKHDQZ128rmbk:
9283 case VPUNPCKHDQZ128rmbkz:
9284 case VPUNPCKHDQZ128rmk:
9285 case VPUNPCKHDQZ128rmkz:
9286 case VPUNPCKHDQZ128rr:
9287 case VPUNPCKHDQZ128rrk:
9288 case VPUNPCKHDQZ128rrkz:
9289 case VPUNPCKHDQZ256rm:
9290 case VPUNPCKHDQZ256rmb:
9291 case VPUNPCKHDQZ256rmbk:
9292 case VPUNPCKHDQZ256rmbkz:
9293 case VPUNPCKHDQZ256rmk:
9294 case VPUNPCKHDQZ256rmkz:
9295 case VPUNPCKHDQZ256rr:
9296 case VPUNPCKHDQZ256rrk:
9297 case VPUNPCKHDQZ256rrkz:
9298 case VPUNPCKHDQZrm:
9299 case VPUNPCKHDQZrmb:
9300 case VPUNPCKHDQZrmbk:
9301 case VPUNPCKHDQZrmbkz:
9302 case VPUNPCKHDQZrmk:
9303 case VPUNPCKHDQZrmkz:
9304 case VPUNPCKHDQZrr:
9305 case VPUNPCKHDQZrrk:
9306 case VPUNPCKHDQZrrkz:
9307 case VPUNPCKHDQrm:
9308 case VPUNPCKHDQrr:
9309 return true;
9310 }
9311 return false;
9312}
9313
9314bool isLCALL(unsigned Opcode) {
9315 switch (Opcode) {
9316 case FARCALL16i:
9317 case FARCALL16m:
9318 case FARCALL32i:
9319 case FARCALL64m:
9320 return true;
9321 }
9322 return false;
9323}
9324
9325bool isAESDEC128KL(unsigned Opcode) {
9326 return Opcode == AESDEC128KL;
9327}
9328
9329bool isVSUBPS(unsigned Opcode) {
9330 switch (Opcode) {
9331 case VSUBPSYrm:
9332 case VSUBPSYrr:
9333 case VSUBPSZ128rm:
9334 case VSUBPSZ128rmb:
9335 case VSUBPSZ128rmbk:
9336 case VSUBPSZ128rmbkz:
9337 case VSUBPSZ128rmk:
9338 case VSUBPSZ128rmkz:
9339 case VSUBPSZ128rr:
9340 case VSUBPSZ128rrk:
9341 case VSUBPSZ128rrkz:
9342 case VSUBPSZ256rm:
9343 case VSUBPSZ256rmb:
9344 case VSUBPSZ256rmbk:
9345 case VSUBPSZ256rmbkz:
9346 case VSUBPSZ256rmk:
9347 case VSUBPSZ256rmkz:
9348 case VSUBPSZ256rr:
9349 case VSUBPSZ256rrk:
9350 case VSUBPSZ256rrkz:
9351 case VSUBPSZrm:
9352 case VSUBPSZrmb:
9353 case VSUBPSZrmbk:
9354 case VSUBPSZrmbkz:
9355 case VSUBPSZrmk:
9356 case VSUBPSZrmkz:
9357 case VSUBPSZrr:
9358 case VSUBPSZrrb:
9359 case VSUBPSZrrbk:
9360 case VSUBPSZrrbkz:
9361 case VSUBPSZrrk:
9362 case VSUBPSZrrkz:
9363 case VSUBPSrm:
9364 case VSUBPSrr:
9365 return true;
9366 }
9367 return false;
9368}
9369
9370bool isFSTP(unsigned Opcode) {
9371 switch (Opcode) {
9372 case ST_FP32m:
9373 case ST_FP64m:
9374 case ST_FP80m:
9375 case ST_FPrr:
9376 return true;
9377 }
9378 return false;
9379}
9380
9381bool isVCVTUDQ2PD(unsigned Opcode) {
9382 switch (Opcode) {
9383 case VCVTUDQ2PDZ128rm:
9384 case VCVTUDQ2PDZ128rmb:
9385 case VCVTUDQ2PDZ128rmbk:
9386 case VCVTUDQ2PDZ128rmbkz:
9387 case VCVTUDQ2PDZ128rmk:
9388 case VCVTUDQ2PDZ128rmkz:
9389 case VCVTUDQ2PDZ128rr:
9390 case VCVTUDQ2PDZ128rrk:
9391 case VCVTUDQ2PDZ128rrkz:
9392 case VCVTUDQ2PDZ256rm:
9393 case VCVTUDQ2PDZ256rmb:
9394 case VCVTUDQ2PDZ256rmbk:
9395 case VCVTUDQ2PDZ256rmbkz:
9396 case VCVTUDQ2PDZ256rmk:
9397 case VCVTUDQ2PDZ256rmkz:
9398 case VCVTUDQ2PDZ256rr:
9399 case VCVTUDQ2PDZ256rrk:
9400 case VCVTUDQ2PDZ256rrkz:
9401 case VCVTUDQ2PDZrm:
9402 case VCVTUDQ2PDZrmb:
9403 case VCVTUDQ2PDZrmbk:
9404 case VCVTUDQ2PDZrmbkz:
9405 case VCVTUDQ2PDZrmk:
9406 case VCVTUDQ2PDZrmkz:
9407 case VCVTUDQ2PDZrr:
9408 case VCVTUDQ2PDZrrk:
9409 case VCVTUDQ2PDZrrkz:
9410 return true;
9411 }
9412 return false;
9413}
9414
9415bool isVPMOVSWB(unsigned Opcode) {
9416 switch (Opcode) {
9417 case VPMOVSWBZ128mr:
9418 case VPMOVSWBZ128mrk:
9419 case VPMOVSWBZ128rr:
9420 case VPMOVSWBZ128rrk:
9421 case VPMOVSWBZ128rrkz:
9422 case VPMOVSWBZ256mr:
9423 case VPMOVSWBZ256mrk:
9424 case VPMOVSWBZ256rr:
9425 case VPMOVSWBZ256rrk:
9426 case VPMOVSWBZ256rrkz:
9427 case VPMOVSWBZmr:
9428 case VPMOVSWBZmrk:
9429 case VPMOVSWBZrr:
9430 case VPMOVSWBZrrk:
9431 case VPMOVSWBZrrkz:
9432 return true;
9433 }
9434 return false;
9435}
9436
9437bool isVPANDNQ(unsigned Opcode) {
9438 switch (Opcode) {
9439 case VPANDNQZ128rm:
9440 case VPANDNQZ128rmb:
9441 case VPANDNQZ128rmbk:
9442 case VPANDNQZ128rmbkz:
9443 case VPANDNQZ128rmk:
9444 case VPANDNQZ128rmkz:
9445 case VPANDNQZ128rr:
9446 case VPANDNQZ128rrk:
9447 case VPANDNQZ128rrkz:
9448 case VPANDNQZ256rm:
9449 case VPANDNQZ256rmb:
9450 case VPANDNQZ256rmbk:
9451 case VPANDNQZ256rmbkz:
9452 case VPANDNQZ256rmk:
9453 case VPANDNQZ256rmkz:
9454 case VPANDNQZ256rr:
9455 case VPANDNQZ256rrk:
9456 case VPANDNQZ256rrkz:
9457 case VPANDNQZrm:
9458 case VPANDNQZrmb:
9459 case VPANDNQZrmbk:
9460 case VPANDNQZrmbkz:
9461 case VPANDNQZrmk:
9462 case VPANDNQZrmkz:
9463 case VPANDNQZrr:
9464 case VPANDNQZrrk:
9465 case VPANDNQZrrkz:
9466 return true;
9467 }
9468 return false;
9469}
9470
9471bool isSYSENTER(unsigned Opcode) {
9472 return Opcode == SYSENTER;
9473}
9474
9475bool isVPHADDWD(unsigned Opcode) {
9476 switch (Opcode) {
9477 case VPHADDWDrm:
9478 case VPHADDWDrr:
9479 return true;
9480 }
9481 return false;
9482}
9483
9484bool isVMOVHPD(unsigned Opcode) {
9485 switch (Opcode) {
9486 case VMOVHPDZ128mr:
9487 case VMOVHPDZ128rm:
9488 case VMOVHPDmr:
9489 case VMOVHPDrm:
9490 return true;
9491 }
9492 return false;
9493}
9494
9495bool isMOVHPD(unsigned Opcode) {
9496 switch (Opcode) {
9497 case MOVHPDmr:
9498 case MOVHPDrm:
9499 return true;
9500 }
9501 return false;
9502}
9503
9504bool isVDIVPH(unsigned Opcode) {
9505 switch (Opcode) {
9506 case VDIVPHZ128rm:
9507 case VDIVPHZ128rmb:
9508 case VDIVPHZ128rmbk:
9509 case VDIVPHZ128rmbkz:
9510 case VDIVPHZ128rmk:
9511 case VDIVPHZ128rmkz:
9512 case VDIVPHZ128rr:
9513 case VDIVPHZ128rrk:
9514 case VDIVPHZ128rrkz:
9515 case VDIVPHZ256rm:
9516 case VDIVPHZ256rmb:
9517 case VDIVPHZ256rmbk:
9518 case VDIVPHZ256rmbkz:
9519 case VDIVPHZ256rmk:
9520 case VDIVPHZ256rmkz:
9521 case VDIVPHZ256rr:
9522 case VDIVPHZ256rrk:
9523 case VDIVPHZ256rrkz:
9524 case VDIVPHZrm:
9525 case VDIVPHZrmb:
9526 case VDIVPHZrmbk:
9527 case VDIVPHZrmbkz:
9528 case VDIVPHZrmk:
9529 case VDIVPHZrmkz:
9530 case VDIVPHZrr:
9531 case VDIVPHZrrb:
9532 case VDIVPHZrrbk:
9533 case VDIVPHZrrbkz:
9534 case VDIVPHZrrk:
9535 case VDIVPHZrrkz:
9536 return true;
9537 }
9538 return false;
9539}
9540
9541bool isFFREE(unsigned Opcode) {
9542 return Opcode == FFREE;
9543}
9544
9545bool isVGATHERPF1DPS(unsigned Opcode) {
9546 return Opcode == VGATHERPF1DPSm;
9547}
9548
9549bool isVPCMPESTRIQ(unsigned Opcode) {
9550 switch (Opcode) {
9551 case VPCMPESTRIQrmi:
9552 case VPCMPESTRIQrri:
9553 return true;
9554 }
9555 return false;
9556}
9557
9558bool isVFNMADD231PD(unsigned Opcode) {
9559 switch (Opcode) {
9560 case VFNMADD231PDYm:
9561 case VFNMADD231PDYr:
9562 case VFNMADD231PDZ128m:
9563 case VFNMADD231PDZ128mb:
9564 case VFNMADD231PDZ128mbk:
9565 case VFNMADD231PDZ128mbkz:
9566 case VFNMADD231PDZ128mk:
9567 case VFNMADD231PDZ128mkz:
9568 case VFNMADD231PDZ128r:
9569 case VFNMADD231PDZ128rk:
9570 case VFNMADD231PDZ128rkz:
9571 case VFNMADD231PDZ256m:
9572 case VFNMADD231PDZ256mb:
9573 case VFNMADD231PDZ256mbk:
9574 case VFNMADD231PDZ256mbkz:
9575 case VFNMADD231PDZ256mk:
9576 case VFNMADD231PDZ256mkz:
9577 case VFNMADD231PDZ256r:
9578 case VFNMADD231PDZ256rk:
9579 case VFNMADD231PDZ256rkz:
9580 case VFNMADD231PDZm:
9581 case VFNMADD231PDZmb:
9582 case VFNMADD231PDZmbk:
9583 case VFNMADD231PDZmbkz:
9584 case VFNMADD231PDZmk:
9585 case VFNMADD231PDZmkz:
9586 case VFNMADD231PDZr:
9587 case VFNMADD231PDZrb:
9588 case VFNMADD231PDZrbk:
9589 case VFNMADD231PDZrbkz:
9590 case VFNMADD231PDZrk:
9591 case VFNMADD231PDZrkz:
9592 case VFNMADD231PDm:
9593 case VFNMADD231PDr:
9594 return true;
9595 }
9596 return false;
9597}
9598
9599bool isVFCMULCPH(unsigned Opcode) {
9600 switch (Opcode) {
9601 case VFCMULCPHZ128rm:
9602 case VFCMULCPHZ128rmb:
9603 case VFCMULCPHZ128rmbk:
9604 case VFCMULCPHZ128rmbkz:
9605 case VFCMULCPHZ128rmk:
9606 case VFCMULCPHZ128rmkz:
9607 case VFCMULCPHZ128rr:
9608 case VFCMULCPHZ128rrk:
9609 case VFCMULCPHZ128rrkz:
9610 case VFCMULCPHZ256rm:
9611 case VFCMULCPHZ256rmb:
9612 case VFCMULCPHZ256rmbk:
9613 case VFCMULCPHZ256rmbkz:
9614 case VFCMULCPHZ256rmk:
9615 case VFCMULCPHZ256rmkz:
9616 case VFCMULCPHZ256rr:
9617 case VFCMULCPHZ256rrk:
9618 case VFCMULCPHZ256rrkz:
9619 case VFCMULCPHZrm:
9620 case VFCMULCPHZrmb:
9621 case VFCMULCPHZrmbk:
9622 case VFCMULCPHZrmbkz:
9623 case VFCMULCPHZrmk:
9624 case VFCMULCPHZrmkz:
9625 case VFCMULCPHZrr:
9626 case VFCMULCPHZrrb:
9627 case VFCMULCPHZrrbk:
9628 case VFCMULCPHZrrbkz:
9629 case VFCMULCPHZrrk:
9630 case VFCMULCPHZrrkz:
9631 return true;
9632 }
9633 return false;
9634}
9635
9636bool isVPADDD(unsigned Opcode) {
9637 switch (Opcode) {
9638 case VPADDDYrm:
9639 case VPADDDYrr:
9640 case VPADDDZ128rm:
9641 case VPADDDZ128rmb:
9642 case VPADDDZ128rmbk:
9643 case VPADDDZ128rmbkz:
9644 case VPADDDZ128rmk:
9645 case VPADDDZ128rmkz:
9646 case VPADDDZ128rr:
9647 case VPADDDZ128rrk:
9648 case VPADDDZ128rrkz:
9649 case VPADDDZ256rm:
9650 case VPADDDZ256rmb:
9651 case VPADDDZ256rmbk:
9652 case VPADDDZ256rmbkz:
9653 case VPADDDZ256rmk:
9654 case VPADDDZ256rmkz:
9655 case VPADDDZ256rr:
9656 case VPADDDZ256rrk:
9657 case VPADDDZ256rrkz:
9658 case VPADDDZrm:
9659 case VPADDDZrmb:
9660 case VPADDDZrmbk:
9661 case VPADDDZrmbkz:
9662 case VPADDDZrmk:
9663 case VPADDDZrmkz:
9664 case VPADDDZrr:
9665 case VPADDDZrrk:
9666 case VPADDDZrrkz:
9667 case VPADDDrm:
9668 case VPADDDrr:
9669 return true;
9670 }
9671 return false;
9672}
9673
9674bool isVPCOMUQ(unsigned Opcode) {
9675 switch (Opcode) {
9676 case VPCOMUQmi:
9677 case VPCOMUQri:
9678 return true;
9679 }
9680 return false;
9681}
9682
9683bool isVSM3MSG2(unsigned Opcode) {
9684 switch (Opcode) {
9685 case VSM3MSG2rm:
9686 case VSM3MSG2rr:
9687 return true;
9688 }
9689 return false;
9690}
9691
9692bool isVERR(unsigned Opcode) {
9693 switch (Opcode) {
9694 case VERRm:
9695 case VERRr:
9696 return true;
9697 }
9698 return false;
9699}
9700
9701bool isKORTESTQ(unsigned Opcode) {
9702 return Opcode == KORTESTQkk;
9703}
9704
9705bool isVFMSUB132SD(unsigned Opcode) {
9706 switch (Opcode) {
9707 case VFMSUB132SDZm_Int:
9708 case VFMSUB132SDZmk_Int:
9709 case VFMSUB132SDZmkz_Int:
9710 case VFMSUB132SDZr_Int:
9711 case VFMSUB132SDZrb_Int:
9712 case VFMSUB132SDZrbk_Int:
9713 case VFMSUB132SDZrbkz_Int:
9714 case VFMSUB132SDZrk_Int:
9715 case VFMSUB132SDZrkz_Int:
9716 case VFMSUB132SDm_Int:
9717 case VFMSUB132SDr_Int:
9718 return true;
9719 }
9720 return false;
9721}
9722
9723bool isTILEZERO(unsigned Opcode) {
9724 return Opcode == TILEZERO;
9725}
9726
9727bool isPFADD(unsigned Opcode) {
9728 switch (Opcode) {
9729 case PFADDrm:
9730 case PFADDrr:
9731 return true;
9732 }
9733 return false;
9734}
9735
9736bool isVCVTSI2SD(unsigned Opcode) {
9737 switch (Opcode) {
9738 case VCVTSI2SDZrm_Int:
9739 case VCVTSI2SDZrr_Int:
9740 case VCVTSI2SDrm_Int:
9741 case VCVTSI2SDrr_Int:
9742 case VCVTSI642SDZrm_Int:
9743 case VCVTSI642SDZrr_Int:
9744 case VCVTSI642SDZrrb_Int:
9745 case VCVTSI642SDrm_Int:
9746 case VCVTSI642SDrr_Int:
9747 return true;
9748 }
9749 return false;
9750}
9751
9752bool isTILELOADDRS(unsigned Opcode) {
9753 switch (Opcode) {
9754 case TILELOADDRS:
9755 case TILELOADDRS_EVEX:
9756 return true;
9757 }
9758 return false;
9759}
9760
9761bool isVSTMXCSR(unsigned Opcode) {
9762 return Opcode == VSTMXCSR;
9763}
9764
9765bool isVCVTTSH2SI(unsigned Opcode) {
9766 switch (Opcode) {
9767 case VCVTTSH2SI64Zrm_Int:
9768 case VCVTTSH2SI64Zrr_Int:
9769 case VCVTTSH2SI64Zrrb_Int:
9770 case VCVTTSH2SIZrm_Int:
9771 case VCVTTSH2SIZrr_Int:
9772 case VCVTTSH2SIZrrb_Int:
9773 return true;
9774 }
9775 return false;
9776}
9777
9778bool isRET(unsigned Opcode) {
9779 switch (Opcode) {
9780 case RET16:
9781 case RET32:
9782 case RET64:
9783 case RETI16:
9784 case RETI32:
9785 case RETI64:
9786 return true;
9787 }
9788 return false;
9789}
9790
9791bool isLZCNT(unsigned Opcode) {
9792 switch (Opcode) {
9793 case LZCNT16rm:
9794 case LZCNT16rm_EVEX:
9795 case LZCNT16rm_NF:
9796 case LZCNT16rr:
9797 case LZCNT16rr_EVEX:
9798 case LZCNT16rr_NF:
9799 case LZCNT32rm:
9800 case LZCNT32rm_EVEX:
9801 case LZCNT32rm_NF:
9802 case LZCNT32rr:
9803 case LZCNT32rr_EVEX:
9804 case LZCNT32rr_NF:
9805 case LZCNT64rm:
9806 case LZCNT64rm_EVEX:
9807 case LZCNT64rm_NF:
9808 case LZCNT64rr:
9809 case LZCNT64rr_EVEX:
9810 case LZCNT64rr_NF:
9811 return true;
9812 }
9813 return false;
9814}
9815
9816bool isMULPD(unsigned Opcode) {
9817 switch (Opcode) {
9818 case MULPDrm:
9819 case MULPDrr:
9820 return true;
9821 }
9822 return false;
9823}
9824
9825bool isVBROADCASTI32X2(unsigned Opcode) {
9826 switch (Opcode) {
9827 case VBROADCASTI32X2Z128rm:
9828 case VBROADCASTI32X2Z128rmk:
9829 case VBROADCASTI32X2Z128rmkz:
9830 case VBROADCASTI32X2Z128rr:
9831 case VBROADCASTI32X2Z128rrk:
9832 case VBROADCASTI32X2Z128rrkz:
9833 case VBROADCASTI32X2Z256rm:
9834 case VBROADCASTI32X2Z256rmk:
9835 case VBROADCASTI32X2Z256rmkz:
9836 case VBROADCASTI32X2Z256rr:
9837 case VBROADCASTI32X2Z256rrk:
9838 case VBROADCASTI32X2Z256rrkz:
9839 case VBROADCASTI32X2Zrm:
9840 case VBROADCASTI32X2Zrmk:
9841 case VBROADCASTI32X2Zrmkz:
9842 case VBROADCASTI32X2Zrr:
9843 case VBROADCASTI32X2Zrrk:
9844 case VBROADCASTI32X2Zrrkz:
9845 return true;
9846 }
9847 return false;
9848}
9849
9850bool isVCVTPH2W(unsigned Opcode) {
9851 switch (Opcode) {
9852 case VCVTPH2WZ128rm:
9853 case VCVTPH2WZ128rmb:
9854 case VCVTPH2WZ128rmbk:
9855 case VCVTPH2WZ128rmbkz:
9856 case VCVTPH2WZ128rmk:
9857 case VCVTPH2WZ128rmkz:
9858 case VCVTPH2WZ128rr:
9859 case VCVTPH2WZ128rrk:
9860 case VCVTPH2WZ128rrkz:
9861 case VCVTPH2WZ256rm:
9862 case VCVTPH2WZ256rmb:
9863 case VCVTPH2WZ256rmbk:
9864 case VCVTPH2WZ256rmbkz:
9865 case VCVTPH2WZ256rmk:
9866 case VCVTPH2WZ256rmkz:
9867 case VCVTPH2WZ256rr:
9868 case VCVTPH2WZ256rrk:
9869 case VCVTPH2WZ256rrkz:
9870 case VCVTPH2WZrm:
9871 case VCVTPH2WZrmb:
9872 case VCVTPH2WZrmbk:
9873 case VCVTPH2WZrmbkz:
9874 case VCVTPH2WZrmk:
9875 case VCVTPH2WZrmkz:
9876 case VCVTPH2WZrr:
9877 case VCVTPH2WZrrb:
9878 case VCVTPH2WZrrbk:
9879 case VCVTPH2WZrrbkz:
9880 case VCVTPH2WZrrk:
9881 case VCVTPH2WZrrkz:
9882 return true;
9883 }
9884 return false;
9885}
9886
9887bool isCQO(unsigned Opcode) {
9888 return Opcode == CQO;
9889}
9890
9891bool isFSUBR(unsigned Opcode) {
9892 switch (Opcode) {
9893 case SUBR_F32m:
9894 case SUBR_F64m:
9895 case SUBR_FST0r:
9896 case SUBR_FrST0:
9897 return true;
9898 }
9899 return false;
9900}
9901
9902bool isDPPD(unsigned Opcode) {
9903 switch (Opcode) {
9904 case DPPDrmi:
9905 case DPPDrri:
9906 return true;
9907 }
9908 return false;
9909}
9910
9911bool isFCOS(unsigned Opcode) {
9912 return Opcode == FCOS;
9913}
9914
9915bool isXSAVES(unsigned Opcode) {
9916 return Opcode == XSAVES;
9917}
9918
9919bool isTZCNT(unsigned Opcode) {
9920 switch (Opcode) {
9921 case TZCNT16rm:
9922 case TZCNT16rm_EVEX:
9923 case TZCNT16rm_NF:
9924 case TZCNT16rr:
9925 case TZCNT16rr_EVEX:
9926 case TZCNT16rr_NF:
9927 case TZCNT32rm:
9928 case TZCNT32rm_EVEX:
9929 case TZCNT32rm_NF:
9930 case TZCNT32rr:
9931 case TZCNT32rr_EVEX:
9932 case TZCNT32rr_NF:
9933 case TZCNT64rm:
9934 case TZCNT64rm_EVEX:
9935 case TZCNT64rm_NF:
9936 case TZCNT64rr:
9937 case TZCNT64rr_EVEX:
9938 case TZCNT64rr_NF:
9939 return true;
9940 }
9941 return false;
9942}
9943
9944bool isVCVTHF62HF8(unsigned Opcode) {
9945 switch (Opcode) {
9946 case VCVTHF62HF8Z128rr:
9947 case VCVTHF62HF8Z128rrk:
9948 case VCVTHF62HF8Z128rrkz:
9949 case VCVTHF62HF8Z256rr:
9950 case VCVTHF62HF8Z256rrk:
9951 case VCVTHF62HF8Z256rrkz:
9952 case VCVTHF62HF8Zrr:
9953 case VCVTHF62HF8Zrrk:
9954 case VCVTHF62HF8Zrrkz:
9955 return true;
9956 }
9957 return false;
9958}
9959
9960bool isLJMP(unsigned Opcode) {
9961 switch (Opcode) {
9962 case FARJMP16i:
9963 case FARJMP16m:
9964 case FARJMP32i:
9965 case FARJMP64m:
9966 return true;
9967 }
9968 return false;
9969}
9970
9971bool isCMOVCC(unsigned Opcode) {
9972 switch (Opcode) {
9973 case CMOV16rm:
9974 case CMOV16rm_ND:
9975 case CMOV16rr:
9976 case CMOV16rr_ND:
9977 case CMOV32rm:
9978 case CMOV32rm_ND:
9979 case CMOV32rr:
9980 case CMOV32rr_ND:
9981 case CMOV64rm:
9982 case CMOV64rm_ND:
9983 case CMOV64rr:
9984 case CMOV64rr_ND:
9985 return true;
9986 }
9987 return false;
9988}
9989
9990bool isVCVTBIASPH2HF8(unsigned Opcode) {
9991 switch (Opcode) {
9992 case VCVTBIASPH2HF8Z128rm:
9993 case VCVTBIASPH2HF8Z128rmb:
9994 case VCVTBIASPH2HF8Z128rmbk:
9995 case VCVTBIASPH2HF8Z128rmbkz:
9996 case VCVTBIASPH2HF8Z128rmk:
9997 case VCVTBIASPH2HF8Z128rmkz:
9998 case VCVTBIASPH2HF8Z128rr:
9999 case VCVTBIASPH2HF8Z128rrk:
10000 case VCVTBIASPH2HF8Z128rrkz:
10001 case VCVTBIASPH2HF8Z256rm:
10002 case VCVTBIASPH2HF8Z256rmb:
10003 case VCVTBIASPH2HF8Z256rmbk:
10004 case VCVTBIASPH2HF8Z256rmbkz:
10005 case VCVTBIASPH2HF8Z256rmk:
10006 case VCVTBIASPH2HF8Z256rmkz:
10007 case VCVTBIASPH2HF8Z256rr:
10008 case VCVTBIASPH2HF8Z256rrk:
10009 case VCVTBIASPH2HF8Z256rrkz:
10010 case VCVTBIASPH2HF8Zrm:
10011 case VCVTBIASPH2HF8Zrmb:
10012 case VCVTBIASPH2HF8Zrmbk:
10013 case VCVTBIASPH2HF8Zrmbkz:
10014 case VCVTBIASPH2HF8Zrmk:
10015 case VCVTBIASPH2HF8Zrmkz:
10016 case VCVTBIASPH2HF8Zrr:
10017 case VCVTBIASPH2HF8Zrrk:
10018 case VCVTBIASPH2HF8Zrrkz:
10019 return true;
10020 }
10021 return false;
10022}
10023
10024bool isINVEPT(unsigned Opcode) {
10025 switch (Opcode) {
10026 case INVEPT32:
10027 case INVEPT64:
10028 case INVEPT64_EVEX:
10029 return true;
10030 }
10031 return false;
10032}
10033
10034bool isADDSUBPD(unsigned Opcode) {
10035 switch (Opcode) {
10036 case ADDSUBPDrm:
10037 case ADDSUBPDrr:
10038 return true;
10039 }
10040 return false;
10041}
10042
10043bool isVCVTSS2SD(unsigned Opcode) {
10044 switch (Opcode) {
10045 case VCVTSS2SDZrm_Int:
10046 case VCVTSS2SDZrmk_Int:
10047 case VCVTSS2SDZrmkz_Int:
10048 case VCVTSS2SDZrr_Int:
10049 case VCVTSS2SDZrrb_Int:
10050 case VCVTSS2SDZrrbk_Int:
10051 case VCVTSS2SDZrrbkz_Int:
10052 case VCVTSS2SDZrrk_Int:
10053 case VCVTSS2SDZrrkz_Int:
10054 case VCVTSS2SDrm_Int:
10055 case VCVTSS2SDrr_Int:
10056 return true;
10057 }
10058 return false;
10059}
10060
10061bool isVMOVSHDUP(unsigned Opcode) {
10062 switch (Opcode) {
10063 case VMOVSHDUPYrm:
10064 case VMOVSHDUPYrr:
10065 case VMOVSHDUPZ128rm:
10066 case VMOVSHDUPZ128rmk:
10067 case VMOVSHDUPZ128rmkz:
10068 case VMOVSHDUPZ128rr:
10069 case VMOVSHDUPZ128rrk:
10070 case VMOVSHDUPZ128rrkz:
10071 case VMOVSHDUPZ256rm:
10072 case VMOVSHDUPZ256rmk:
10073 case VMOVSHDUPZ256rmkz:
10074 case VMOVSHDUPZ256rr:
10075 case VMOVSHDUPZ256rrk:
10076 case VMOVSHDUPZ256rrkz:
10077 case VMOVSHDUPZrm:
10078 case VMOVSHDUPZrmk:
10079 case VMOVSHDUPZrmkz:
10080 case VMOVSHDUPZrr:
10081 case VMOVSHDUPZrrk:
10082 case VMOVSHDUPZrrkz:
10083 case VMOVSHDUPrm:
10084 case VMOVSHDUPrr:
10085 return true;
10086 }
10087 return false;
10088}
10089
10090bool isKSHIFTRD(unsigned Opcode) {
10091 return Opcode == KSHIFTRDki;
10092}
10093
10094bool isVPTERNLOGD(unsigned Opcode) {
10095 switch (Opcode) {
10096 case VPTERNLOGDZ128rmbi:
10097 case VPTERNLOGDZ128rmbik:
10098 case VPTERNLOGDZ128rmbikz:
10099 case VPTERNLOGDZ128rmi:
10100 case VPTERNLOGDZ128rmik:
10101 case VPTERNLOGDZ128rmikz:
10102 case VPTERNLOGDZ128rri:
10103 case VPTERNLOGDZ128rrik:
10104 case VPTERNLOGDZ128rrikz:
10105 case VPTERNLOGDZ256rmbi:
10106 case VPTERNLOGDZ256rmbik:
10107 case VPTERNLOGDZ256rmbikz:
10108 case VPTERNLOGDZ256rmi:
10109 case VPTERNLOGDZ256rmik:
10110 case VPTERNLOGDZ256rmikz:
10111 case VPTERNLOGDZ256rri:
10112 case VPTERNLOGDZ256rrik:
10113 case VPTERNLOGDZ256rrikz:
10114 case VPTERNLOGDZrmbi:
10115 case VPTERNLOGDZrmbik:
10116 case VPTERNLOGDZrmbikz:
10117 case VPTERNLOGDZrmi:
10118 case VPTERNLOGDZrmik:
10119 case VPTERNLOGDZrmikz:
10120 case VPTERNLOGDZrri:
10121 case VPTERNLOGDZrrik:
10122 case VPTERNLOGDZrrikz:
10123 return true;
10124 }
10125 return false;
10126}
10127
10128bool isPADDQ(unsigned Opcode) {
10129 switch (Opcode) {
10130 case MMX_PADDQrm:
10131 case MMX_PADDQrr:
10132 case PADDQrm:
10133 case PADDQrr:
10134 return true;
10135 }
10136 return false;
10137}
10138
10139bool isVEXTRACTI64X4(unsigned Opcode) {
10140 switch (Opcode) {
10141 case VEXTRACTI64X4Zmri:
10142 case VEXTRACTI64X4Zmrik:
10143 case VEXTRACTI64X4Zrri:
10144 case VEXTRACTI64X4Zrrik:
10145 case VEXTRACTI64X4Zrrikz:
10146 return true;
10147 }
10148 return false;
10149}
10150
10151bool isVFMSUB231SS(unsigned Opcode) {
10152 switch (Opcode) {
10153 case VFMSUB231SSZm_Int:
10154 case VFMSUB231SSZmk_Int:
10155 case VFMSUB231SSZmkz_Int:
10156 case VFMSUB231SSZr_Int:
10157 case VFMSUB231SSZrb_Int:
10158 case VFMSUB231SSZrbk_Int:
10159 case VFMSUB231SSZrbkz_Int:
10160 case VFMSUB231SSZrk_Int:
10161 case VFMSUB231SSZrkz_Int:
10162 case VFMSUB231SSm_Int:
10163 case VFMSUB231SSr_Int:
10164 return true;
10165 }
10166 return false;
10167}
10168
10169bool isVPCMPEQB(unsigned Opcode) {
10170 switch (Opcode) {
10171 case VPCMPEQBYrm:
10172 case VPCMPEQBYrr:
10173 case VPCMPEQBZ128rm:
10174 case VPCMPEQBZ128rmk:
10175 case VPCMPEQBZ128rr:
10176 case VPCMPEQBZ128rrk:
10177 case VPCMPEQBZ256rm:
10178 case VPCMPEQBZ256rmk:
10179 case VPCMPEQBZ256rr:
10180 case VPCMPEQBZ256rrk:
10181 case VPCMPEQBZrm:
10182 case VPCMPEQBZrmk:
10183 case VPCMPEQBZrr:
10184 case VPCMPEQBZrrk:
10185 case VPCMPEQBrm:
10186 case VPCMPEQBrr:
10187 return true;
10188 }
10189 return false;
10190}
10191
10192bool isLEA(unsigned Opcode) {
10193 switch (Opcode) {
10194 case LEA16r:
10195 case LEA32r:
10196 case LEA64_32r:
10197 case LEA64r:
10198 return true;
10199 }
10200 return false;
10201}
10202
10203bool isPSUBB(unsigned Opcode) {
10204 switch (Opcode) {
10205 case MMX_PSUBBrm:
10206 case MMX_PSUBBrr:
10207 case PSUBBrm:
10208 case PSUBBrr:
10209 return true;
10210 }
10211 return false;
10212}
10213
10214bool isKADDQ(unsigned Opcode) {
10215 return Opcode == KADDQkk;
10216}
10217
10218bool isMOVSX(unsigned Opcode) {
10219 switch (Opcode) {
10220 case MOVSX16rm16:
10221 case MOVSX16rm8:
10222 case MOVSX16rr16:
10223 case MOVSX16rr8:
10224 case MOVSX32rm16:
10225 case MOVSX32rm8:
10226 case MOVSX32rr16:
10227 case MOVSX32rr8:
10228 case MOVSX64rm16:
10229 case MOVSX64rm8:
10230 case MOVSX64rr16:
10231 case MOVSX64rr8:
10232 return true;
10233 }
10234 return false;
10235}
10236
10237bool isVALIGNQ(unsigned Opcode) {
10238 switch (Opcode) {
10239 case VALIGNQZ128rmbi:
10240 case VALIGNQZ128rmbik:
10241 case VALIGNQZ128rmbikz:
10242 case VALIGNQZ128rmi:
10243 case VALIGNQZ128rmik:
10244 case VALIGNQZ128rmikz:
10245 case VALIGNQZ128rri:
10246 case VALIGNQZ128rrik:
10247 case VALIGNQZ128rrikz:
10248 case VALIGNQZ256rmbi:
10249 case VALIGNQZ256rmbik:
10250 case VALIGNQZ256rmbikz:
10251 case VALIGNQZ256rmi:
10252 case VALIGNQZ256rmik:
10253 case VALIGNQZ256rmikz:
10254 case VALIGNQZ256rri:
10255 case VALIGNQZ256rrik:
10256 case VALIGNQZ256rrikz:
10257 case VALIGNQZrmbi:
10258 case VALIGNQZrmbik:
10259 case VALIGNQZrmbikz:
10260 case VALIGNQZrmi:
10261 case VALIGNQZrmik:
10262 case VALIGNQZrmikz:
10263 case VALIGNQZrri:
10264 case VALIGNQZrrik:
10265 case VALIGNQZrrikz:
10266 return true;
10267 }
10268 return false;
10269}
10270
10271bool isVCVTNE2PS2BF16(unsigned Opcode) {
10272 switch (Opcode) {
10273 case VCVTNE2PS2BF16Z128rm:
10274 case VCVTNE2PS2BF16Z128rmb:
10275 case VCVTNE2PS2BF16Z128rmbk:
10276 case VCVTNE2PS2BF16Z128rmbkz:
10277 case VCVTNE2PS2BF16Z128rmk:
10278 case VCVTNE2PS2BF16Z128rmkz:
10279 case VCVTNE2PS2BF16Z128rr:
10280 case VCVTNE2PS2BF16Z128rrk:
10281 case VCVTNE2PS2BF16Z128rrkz:
10282 case VCVTNE2PS2BF16Z256rm:
10283 case VCVTNE2PS2BF16Z256rmb:
10284 case VCVTNE2PS2BF16Z256rmbk:
10285 case VCVTNE2PS2BF16Z256rmbkz:
10286 case VCVTNE2PS2BF16Z256rmk:
10287 case VCVTNE2PS2BF16Z256rmkz:
10288 case VCVTNE2PS2BF16Z256rr:
10289 case VCVTNE2PS2BF16Z256rrk:
10290 case VCVTNE2PS2BF16Z256rrkz:
10291 case VCVTNE2PS2BF16Zrm:
10292 case VCVTNE2PS2BF16Zrmb:
10293 case VCVTNE2PS2BF16Zrmbk:
10294 case VCVTNE2PS2BF16Zrmbkz:
10295 case VCVTNE2PS2BF16Zrmk:
10296 case VCVTNE2PS2BF16Zrmkz:
10297 case VCVTNE2PS2BF16Zrr:
10298 case VCVTNE2PS2BF16Zrrk:
10299 case VCVTNE2PS2BF16Zrrkz:
10300 return true;
10301 }
10302 return false;
10303}
10304
10305bool isVPSRAW(unsigned Opcode) {
10306 switch (Opcode) {
10307 case VPSRAWYri:
10308 case VPSRAWYrm:
10309 case VPSRAWYrr:
10310 case VPSRAWZ128mi:
10311 case VPSRAWZ128mik:
10312 case VPSRAWZ128mikz:
10313 case VPSRAWZ128ri:
10314 case VPSRAWZ128rik:
10315 case VPSRAWZ128rikz:
10316 case VPSRAWZ128rm:
10317 case VPSRAWZ128rmk:
10318 case VPSRAWZ128rmkz:
10319 case VPSRAWZ128rr:
10320 case VPSRAWZ128rrk:
10321 case VPSRAWZ128rrkz:
10322 case VPSRAWZ256mi:
10323 case VPSRAWZ256mik:
10324 case VPSRAWZ256mikz:
10325 case VPSRAWZ256ri:
10326 case VPSRAWZ256rik:
10327 case VPSRAWZ256rikz:
10328 case VPSRAWZ256rm:
10329 case VPSRAWZ256rmk:
10330 case VPSRAWZ256rmkz:
10331 case VPSRAWZ256rr:
10332 case VPSRAWZ256rrk:
10333 case VPSRAWZ256rrkz:
10334 case VPSRAWZmi:
10335 case VPSRAWZmik:
10336 case VPSRAWZmikz:
10337 case VPSRAWZri:
10338 case VPSRAWZrik:
10339 case VPSRAWZrikz:
10340 case VPSRAWZrm:
10341 case VPSRAWZrmk:
10342 case VPSRAWZrmkz:
10343 case VPSRAWZrr:
10344 case VPSRAWZrrk:
10345 case VPSRAWZrrkz:
10346 case VPSRAWri:
10347 case VPSRAWrm:
10348 case VPSRAWrr:
10349 return true;
10350 }
10351 return false;
10352}
10353
10354bool isVFMSUBADD231PH(unsigned Opcode) {
10355 switch (Opcode) {
10356 case VFMSUBADD231PHZ128m:
10357 case VFMSUBADD231PHZ128mb:
10358 case VFMSUBADD231PHZ128mbk:
10359 case VFMSUBADD231PHZ128mbkz:
10360 case VFMSUBADD231PHZ128mk:
10361 case VFMSUBADD231PHZ128mkz:
10362 case VFMSUBADD231PHZ128r:
10363 case VFMSUBADD231PHZ128rk:
10364 case VFMSUBADD231PHZ128rkz:
10365 case VFMSUBADD231PHZ256m:
10366 case VFMSUBADD231PHZ256mb:
10367 case VFMSUBADD231PHZ256mbk:
10368 case VFMSUBADD231PHZ256mbkz:
10369 case VFMSUBADD231PHZ256mk:
10370 case VFMSUBADD231PHZ256mkz:
10371 case VFMSUBADD231PHZ256r:
10372 case VFMSUBADD231PHZ256rk:
10373 case VFMSUBADD231PHZ256rkz:
10374 case VFMSUBADD231PHZm:
10375 case VFMSUBADD231PHZmb:
10376 case VFMSUBADD231PHZmbk:
10377 case VFMSUBADD231PHZmbkz:
10378 case VFMSUBADD231PHZmk:
10379 case VFMSUBADD231PHZmkz:
10380 case VFMSUBADD231PHZr:
10381 case VFMSUBADD231PHZrb:
10382 case VFMSUBADD231PHZrbk:
10383 case VFMSUBADD231PHZrbkz:
10384 case VFMSUBADD231PHZrk:
10385 case VFMSUBADD231PHZrkz:
10386 return true;
10387 }
10388 return false;
10389}
10390
10391bool isCVTDQ2PS(unsigned Opcode) {
10392 switch (Opcode) {
10393 case CVTDQ2PSrm:
10394 case CVTDQ2PSrr:
10395 return true;
10396 }
10397 return false;
10398}
10399
10400bool isFBLD(unsigned Opcode) {
10401 return Opcode == FBLDm;
10402}
10403
10404bool isLMSW(unsigned Opcode) {
10405 switch (Opcode) {
10406 case LMSW16m:
10407 case LMSW16r:
10408 return true;
10409 }
10410 return false;
10411}
10412
10413bool isVRNDSCALEPH(unsigned Opcode) {
10414 switch (Opcode) {
10415 case VRNDSCALEPHZ128rmbi:
10416 case VRNDSCALEPHZ128rmbik:
10417 case VRNDSCALEPHZ128rmbikz:
10418 case VRNDSCALEPHZ128rmi:
10419 case VRNDSCALEPHZ128rmik:
10420 case VRNDSCALEPHZ128rmikz:
10421 case VRNDSCALEPHZ128rri:
10422 case VRNDSCALEPHZ128rrik:
10423 case VRNDSCALEPHZ128rrikz:
10424 case VRNDSCALEPHZ256rmbi:
10425 case VRNDSCALEPHZ256rmbik:
10426 case VRNDSCALEPHZ256rmbikz:
10427 case VRNDSCALEPHZ256rmi:
10428 case VRNDSCALEPHZ256rmik:
10429 case VRNDSCALEPHZ256rmikz:
10430 case VRNDSCALEPHZ256rri:
10431 case VRNDSCALEPHZ256rrik:
10432 case VRNDSCALEPHZ256rrikz:
10433 case VRNDSCALEPHZrmbi:
10434 case VRNDSCALEPHZrmbik:
10435 case VRNDSCALEPHZrmbikz:
10436 case VRNDSCALEPHZrmi:
10437 case VRNDSCALEPHZrmik:
10438 case VRNDSCALEPHZrmikz:
10439 case VRNDSCALEPHZrri:
10440 case VRNDSCALEPHZrrib:
10441 case VRNDSCALEPHZrribk:
10442 case VRNDSCALEPHZrribkz:
10443 case VRNDSCALEPHZrrik:
10444 case VRNDSCALEPHZrrikz:
10445 return true;
10446 }
10447 return false;
10448}
10449
10450bool isMINSS(unsigned Opcode) {
10451 switch (Opcode) {
10452 case MINSSrm_Int:
10453 case MINSSrr_Int:
10454 return true;
10455 }
10456 return false;
10457}
10458
10459bool isWRMSR(unsigned Opcode) {
10460 return Opcode == WRMSR;
10461}
10462
10463bool isFSCALE(unsigned Opcode) {
10464 return Opcode == FSCALE;
10465}
10466
10467bool isVFNMADD213SH(unsigned Opcode) {
10468 switch (Opcode) {
10469 case VFNMADD213SHZm_Int:
10470 case VFNMADD213SHZmk_Int:
10471 case VFNMADD213SHZmkz_Int:
10472 case VFNMADD213SHZr_Int:
10473 case VFNMADD213SHZrb_Int:
10474 case VFNMADD213SHZrbk_Int:
10475 case VFNMADD213SHZrbkz_Int:
10476 case VFNMADD213SHZrk_Int:
10477 case VFNMADD213SHZrkz_Int:
10478 return true;
10479 }
10480 return false;
10481}
10482
10483bool isIMULZU(unsigned Opcode) {
10484 switch (Opcode) {
10485 case IMULZU16rmi:
10486 case IMULZU16rmi8:
10487 case IMULZU16rri:
10488 case IMULZU16rri8:
10489 case IMULZU32rmi:
10490 case IMULZU32rmi8:
10491 case IMULZU32rri:
10492 case IMULZU32rri8:
10493 case IMULZU64rmi32:
10494 case IMULZU64rmi8:
10495 case IMULZU64rri32:
10496 case IMULZU64rri8:
10497 return true;
10498 }
10499 return false;
10500}
10501
10502bool isVPHADDUBD(unsigned Opcode) {
10503 switch (Opcode) {
10504 case VPHADDUBDrm:
10505 case VPHADDUBDrr:
10506 return true;
10507 }
10508 return false;
10509}
10510
10511bool isRDSSPQ(unsigned Opcode) {
10512 return Opcode == RDSSPQ;
10513}
10514
10515bool isVCVTBF162IBS(unsigned Opcode) {
10516 switch (Opcode) {
10517 case VCVTBF162IBSZ128rm:
10518 case VCVTBF162IBSZ128rmb:
10519 case VCVTBF162IBSZ128rmbk:
10520 case VCVTBF162IBSZ128rmbkz:
10521 case VCVTBF162IBSZ128rmk:
10522 case VCVTBF162IBSZ128rmkz:
10523 case VCVTBF162IBSZ128rr:
10524 case VCVTBF162IBSZ128rrk:
10525 case VCVTBF162IBSZ128rrkz:
10526 case VCVTBF162IBSZ256rm:
10527 case VCVTBF162IBSZ256rmb:
10528 case VCVTBF162IBSZ256rmbk:
10529 case VCVTBF162IBSZ256rmbkz:
10530 case VCVTBF162IBSZ256rmk:
10531 case VCVTBF162IBSZ256rmkz:
10532 case VCVTBF162IBSZ256rr:
10533 case VCVTBF162IBSZ256rrk:
10534 case VCVTBF162IBSZ256rrkz:
10535 case VCVTBF162IBSZrm:
10536 case VCVTBF162IBSZrmb:
10537 case VCVTBF162IBSZrmbk:
10538 case VCVTBF162IBSZrmbkz:
10539 case VCVTBF162IBSZrmk:
10540 case VCVTBF162IBSZrmkz:
10541 case VCVTBF162IBSZrr:
10542 case VCVTBF162IBSZrrk:
10543 case VCVTBF162IBSZrrkz:
10544 return true;
10545 }
10546 return false;
10547}
10548
10549bool isLGDT(unsigned Opcode) {
10550 return Opcode == LGDT64m;
10551}
10552
10553bool isVPSHLDVD(unsigned Opcode) {
10554 switch (Opcode) {
10555 case VPSHLDVDZ128m:
10556 case VPSHLDVDZ128mb:
10557 case VPSHLDVDZ128mbk:
10558 case VPSHLDVDZ128mbkz:
10559 case VPSHLDVDZ128mk:
10560 case VPSHLDVDZ128mkz:
10561 case VPSHLDVDZ128r:
10562 case VPSHLDVDZ128rk:
10563 case VPSHLDVDZ128rkz:
10564 case VPSHLDVDZ256m:
10565 case VPSHLDVDZ256mb:
10566 case VPSHLDVDZ256mbk:
10567 case VPSHLDVDZ256mbkz:
10568 case VPSHLDVDZ256mk:
10569 case VPSHLDVDZ256mkz:
10570 case VPSHLDVDZ256r:
10571 case VPSHLDVDZ256rk:
10572 case VPSHLDVDZ256rkz:
10573 case VPSHLDVDZm:
10574 case VPSHLDVDZmb:
10575 case VPSHLDVDZmbk:
10576 case VPSHLDVDZmbkz:
10577 case VPSHLDVDZmk:
10578 case VPSHLDVDZmkz:
10579 case VPSHLDVDZr:
10580 case VPSHLDVDZrk:
10581 case VPSHLDVDZrkz:
10582 return true;
10583 }
10584 return false;
10585}
10586
10587bool isPFCMPGT(unsigned Opcode) {
10588 switch (Opcode) {
10589 case PFCMPGTrm:
10590 case PFCMPGTrr:
10591 return true;
10592 }
10593 return false;
10594}
10595
10596bool isJCXZ(unsigned Opcode) {
10597 return Opcode == JCXZ;
10598}
10599
10600bool isVPMOVZXBW(unsigned Opcode) {
10601 switch (Opcode) {
10602 case VPMOVZXBWYrm:
10603 case VPMOVZXBWYrr:
10604 case VPMOVZXBWZ128rm:
10605 case VPMOVZXBWZ128rmk:
10606 case VPMOVZXBWZ128rmkz:
10607 case VPMOVZXBWZ128rr:
10608 case VPMOVZXBWZ128rrk:
10609 case VPMOVZXBWZ128rrkz:
10610 case VPMOVZXBWZ256rm:
10611 case VPMOVZXBWZ256rmk:
10612 case VPMOVZXBWZ256rmkz:
10613 case VPMOVZXBWZ256rr:
10614 case VPMOVZXBWZ256rrk:
10615 case VPMOVZXBWZ256rrkz:
10616 case VPMOVZXBWZrm:
10617 case VPMOVZXBWZrmk:
10618 case VPMOVZXBWZrmkz:
10619 case VPMOVZXBWZrr:
10620 case VPMOVZXBWZrrk:
10621 case VPMOVZXBWZrrkz:
10622 case VPMOVZXBWrm:
10623 case VPMOVZXBWrr:
10624 return true;
10625 }
10626 return false;
10627}
10628
10629bool isVFMADDSUB231PD(unsigned Opcode) {
10630 switch (Opcode) {
10631 case VFMADDSUB231PDYm:
10632 case VFMADDSUB231PDYr:
10633 case VFMADDSUB231PDZ128m:
10634 case VFMADDSUB231PDZ128mb:
10635 case VFMADDSUB231PDZ128mbk:
10636 case VFMADDSUB231PDZ128mbkz:
10637 case VFMADDSUB231PDZ128mk:
10638 case VFMADDSUB231PDZ128mkz:
10639 case VFMADDSUB231PDZ128r:
10640 case VFMADDSUB231PDZ128rk:
10641 case VFMADDSUB231PDZ128rkz:
10642 case VFMADDSUB231PDZ256m:
10643 case VFMADDSUB231PDZ256mb:
10644 case VFMADDSUB231PDZ256mbk:
10645 case VFMADDSUB231PDZ256mbkz:
10646 case VFMADDSUB231PDZ256mk:
10647 case VFMADDSUB231PDZ256mkz:
10648 case VFMADDSUB231PDZ256r:
10649 case VFMADDSUB231PDZ256rk:
10650 case VFMADDSUB231PDZ256rkz:
10651 case VFMADDSUB231PDZm:
10652 case VFMADDSUB231PDZmb:
10653 case VFMADDSUB231PDZmbk:
10654 case VFMADDSUB231PDZmbkz:
10655 case VFMADDSUB231PDZmk:
10656 case VFMADDSUB231PDZmkz:
10657 case VFMADDSUB231PDZr:
10658 case VFMADDSUB231PDZrb:
10659 case VFMADDSUB231PDZrbk:
10660 case VFMADDSUB231PDZrbkz:
10661 case VFMADDSUB231PDZrk:
10662 case VFMADDSUB231PDZrkz:
10663 case VFMADDSUB231PDm:
10664 case VFMADDSUB231PDr:
10665 return true;
10666 }
10667 return false;
10668}
10669
10670bool isVBLENDMPD(unsigned Opcode) {
10671 switch (Opcode) {
10672 case VBLENDMPDZ128rm:
10673 case VBLENDMPDZ128rmb:
10674 case VBLENDMPDZ128rmbk:
10675 case VBLENDMPDZ128rmbkz:
10676 case VBLENDMPDZ128rmk:
10677 case VBLENDMPDZ128rmkz:
10678 case VBLENDMPDZ128rr:
10679 case VBLENDMPDZ128rrk:
10680 case VBLENDMPDZ128rrkz:
10681 case VBLENDMPDZ256rm:
10682 case VBLENDMPDZ256rmb:
10683 case VBLENDMPDZ256rmbk:
10684 case VBLENDMPDZ256rmbkz:
10685 case VBLENDMPDZ256rmk:
10686 case VBLENDMPDZ256rmkz:
10687 case VBLENDMPDZ256rr:
10688 case VBLENDMPDZ256rrk:
10689 case VBLENDMPDZ256rrkz:
10690 case VBLENDMPDZrm:
10691 case VBLENDMPDZrmb:
10692 case VBLENDMPDZrmbk:
10693 case VBLENDMPDZrmbkz:
10694 case VBLENDMPDZrmk:
10695 case VBLENDMPDZrmkz:
10696 case VBLENDMPDZrr:
10697 case VBLENDMPDZrrk:
10698 case VBLENDMPDZrrkz:
10699 return true;
10700 }
10701 return false;
10702}
10703
10704bool isHSUBPS(unsigned Opcode) {
10705 switch (Opcode) {
10706 case HSUBPSrm:
10707 case HSUBPSrr:
10708 return true;
10709 }
10710 return false;
10711}
10712
10713bool isPREFETCHIT0(unsigned Opcode) {
10714 return Opcode == PREFETCHIT0;
10715}
10716
10717bool isKTESTD(unsigned Opcode) {
10718 return Opcode == KTESTDkk;
10719}
10720
10721bool isVCVTNEOPH2PS(unsigned Opcode) {
10722 switch (Opcode) {
10723 case VCVTNEOPH2PSYrm:
10724 case VCVTNEOPH2PSrm:
10725 return true;
10726 }
10727 return false;
10728}
10729
10730bool isVBLENDVPD(unsigned Opcode) {
10731 switch (Opcode) {
10732 case VBLENDVPDYrmr:
10733 case VBLENDVPDYrrr:
10734 case VBLENDVPDrmr:
10735 case VBLENDVPDrrr:
10736 return true;
10737 }
10738 return false;
10739}
10740
10741bool isVCVTSS2USI(unsigned Opcode) {
10742 switch (Opcode) {
10743 case VCVTSS2USI64Zrm_Int:
10744 case VCVTSS2USI64Zrr_Int:
10745 case VCVTSS2USI64Zrrb_Int:
10746 case VCVTSS2USIZrm_Int:
10747 case VCVTSS2USIZrr_Int:
10748 case VCVTSS2USIZrrb_Int:
10749 return true;
10750 }
10751 return false;
10752}
10753
10754bool isVCVTTPS2DQS(unsigned Opcode) {
10755 switch (Opcode) {
10756 case VCVTTPS2DQSZ128rm:
10757 case VCVTTPS2DQSZ128rmb:
10758 case VCVTTPS2DQSZ128rmbk:
10759 case VCVTTPS2DQSZ128rmbkz:
10760 case VCVTTPS2DQSZ128rmk:
10761 case VCVTTPS2DQSZ128rmkz:
10762 case VCVTTPS2DQSZ128rr:
10763 case VCVTTPS2DQSZ128rrk:
10764 case VCVTTPS2DQSZ128rrkz:
10765 case VCVTTPS2DQSZ256rm:
10766 case VCVTTPS2DQSZ256rmb:
10767 case VCVTTPS2DQSZ256rmbk:
10768 case VCVTTPS2DQSZ256rmbkz:
10769 case VCVTTPS2DQSZ256rmk:
10770 case VCVTTPS2DQSZ256rmkz:
10771 case VCVTTPS2DQSZ256rr:
10772 case VCVTTPS2DQSZ256rrk:
10773 case VCVTTPS2DQSZ256rrkz:
10774 case VCVTTPS2DQSZrm:
10775 case VCVTTPS2DQSZrmb:
10776 case VCVTTPS2DQSZrmbk:
10777 case VCVTTPS2DQSZrmbkz:
10778 case VCVTTPS2DQSZrmk:
10779 case VCVTTPS2DQSZrmkz:
10780 case VCVTTPS2DQSZrr:
10781 case VCVTTPS2DQSZrrb:
10782 case VCVTTPS2DQSZrrbk:
10783 case VCVTTPS2DQSZrrbkz:
10784 case VCVTTPS2DQSZrrk:
10785 case VCVTTPS2DQSZrrkz:
10786 return true;
10787 }
10788 return false;
10789}
10790
10791bool isVPANDD(unsigned Opcode) {
10792 switch (Opcode) {
10793 case VPANDDZ128rm:
10794 case VPANDDZ128rmb:
10795 case VPANDDZ128rmbk:
10796 case VPANDDZ128rmbkz:
10797 case VPANDDZ128rmk:
10798 case VPANDDZ128rmkz:
10799 case VPANDDZ128rr:
10800 case VPANDDZ128rrk:
10801 case VPANDDZ128rrkz:
10802 case VPANDDZ256rm:
10803 case VPANDDZ256rmb:
10804 case VPANDDZ256rmbk:
10805 case VPANDDZ256rmbkz:
10806 case VPANDDZ256rmk:
10807 case VPANDDZ256rmkz:
10808 case VPANDDZ256rr:
10809 case VPANDDZ256rrk:
10810 case VPANDDZ256rrkz:
10811 case VPANDDZrm:
10812 case VPANDDZrmb:
10813 case VPANDDZrmbk:
10814 case VPANDDZrmbkz:
10815 case VPANDDZrmk:
10816 case VPANDDZrmkz:
10817 case VPANDDZrr:
10818 case VPANDDZrrk:
10819 case VPANDDZrrkz:
10820 return true;
10821 }
10822 return false;
10823}
10824
10825bool isPMINSW(unsigned Opcode) {
10826 switch (Opcode) {
10827 case MMX_PMINSWrm:
10828 case MMX_PMINSWrr:
10829 case PMINSWrm:
10830 case PMINSWrr:
10831 return true;
10832 }
10833 return false;
10834}
10835
10836bool isSTAC(unsigned Opcode) {
10837 return Opcode == STAC;
10838}
10839
10840bool isVFMSUB213PS(unsigned Opcode) {
10841 switch (Opcode) {
10842 case VFMSUB213PSYm:
10843 case VFMSUB213PSYr:
10844 case VFMSUB213PSZ128m:
10845 case VFMSUB213PSZ128mb:
10846 case VFMSUB213PSZ128mbk:
10847 case VFMSUB213PSZ128mbkz:
10848 case VFMSUB213PSZ128mk:
10849 case VFMSUB213PSZ128mkz:
10850 case VFMSUB213PSZ128r:
10851 case VFMSUB213PSZ128rk:
10852 case VFMSUB213PSZ128rkz:
10853 case VFMSUB213PSZ256m:
10854 case VFMSUB213PSZ256mb:
10855 case VFMSUB213PSZ256mbk:
10856 case VFMSUB213PSZ256mbkz:
10857 case VFMSUB213PSZ256mk:
10858 case VFMSUB213PSZ256mkz:
10859 case VFMSUB213PSZ256r:
10860 case VFMSUB213PSZ256rk:
10861 case VFMSUB213PSZ256rkz:
10862 case VFMSUB213PSZm:
10863 case VFMSUB213PSZmb:
10864 case VFMSUB213PSZmbk:
10865 case VFMSUB213PSZmbkz:
10866 case VFMSUB213PSZmk:
10867 case VFMSUB213PSZmkz:
10868 case VFMSUB213PSZr:
10869 case VFMSUB213PSZrb:
10870 case VFMSUB213PSZrbk:
10871 case VFMSUB213PSZrbkz:
10872 case VFMSUB213PSZrk:
10873 case VFMSUB213PSZrkz:
10874 case VFMSUB213PSm:
10875 case VFMSUB213PSr:
10876 return true;
10877 }
10878 return false;
10879}
10880
10881bool isPOPAL(unsigned Opcode) {
10882 return Opcode == POPA32;
10883}
10884
10885bool isVCVTPS2UQQ(unsigned Opcode) {
10886 switch (Opcode) {
10887 case VCVTPS2UQQZ128rm:
10888 case VCVTPS2UQQZ128rmb:
10889 case VCVTPS2UQQZ128rmbk:
10890 case VCVTPS2UQQZ128rmbkz:
10891 case VCVTPS2UQQZ128rmk:
10892 case VCVTPS2UQQZ128rmkz:
10893 case VCVTPS2UQQZ128rr:
10894 case VCVTPS2UQQZ128rrk:
10895 case VCVTPS2UQQZ128rrkz:
10896 case VCVTPS2UQQZ256rm:
10897 case VCVTPS2UQQZ256rmb:
10898 case VCVTPS2UQQZ256rmbk:
10899 case VCVTPS2UQQZ256rmbkz:
10900 case VCVTPS2UQQZ256rmk:
10901 case VCVTPS2UQQZ256rmkz:
10902 case VCVTPS2UQQZ256rr:
10903 case VCVTPS2UQQZ256rrk:
10904 case VCVTPS2UQQZ256rrkz:
10905 case VCVTPS2UQQZrm:
10906 case VCVTPS2UQQZrmb:
10907 case VCVTPS2UQQZrmbk:
10908 case VCVTPS2UQQZrmbkz:
10909 case VCVTPS2UQQZrmk:
10910 case VCVTPS2UQQZrmkz:
10911 case VCVTPS2UQQZrr:
10912 case VCVTPS2UQQZrrb:
10913 case VCVTPS2UQQZrrbk:
10914 case VCVTPS2UQQZrrbkz:
10915 case VCVTPS2UQQZrrk:
10916 case VCVTPS2UQQZrrkz:
10917 return true;
10918 }
10919 return false;
10920}
10921
10922bool isRDRAND(unsigned Opcode) {
10923 switch (Opcode) {
10924 case RDRAND16r:
10925 case RDRAND32r:
10926 case RDRAND64r:
10927 return true;
10928 }
10929 return false;
10930}
10931
10932bool isJCC(unsigned Opcode) {
10933 switch (Opcode) {
10934 case JCC_1:
10935 case JCC_2:
10936 case JCC_4:
10937 return true;
10938 }
10939 return false;
10940}
10941
10942bool isVPMINSQ(unsigned Opcode) {
10943 switch (Opcode) {
10944 case VPMINSQZ128rm:
10945 case VPMINSQZ128rmb:
10946 case VPMINSQZ128rmbk:
10947 case VPMINSQZ128rmbkz:
10948 case VPMINSQZ128rmk:
10949 case VPMINSQZ128rmkz:
10950 case VPMINSQZ128rr:
10951 case VPMINSQZ128rrk:
10952 case VPMINSQZ128rrkz:
10953 case VPMINSQZ256rm:
10954 case VPMINSQZ256rmb:
10955 case VPMINSQZ256rmbk:
10956 case VPMINSQZ256rmbkz:
10957 case VPMINSQZ256rmk:
10958 case VPMINSQZ256rmkz:
10959 case VPMINSQZ256rr:
10960 case VPMINSQZ256rrk:
10961 case VPMINSQZ256rrkz:
10962 case VPMINSQZrm:
10963 case VPMINSQZrmb:
10964 case VPMINSQZrmbk:
10965 case VPMINSQZrmbkz:
10966 case VPMINSQZrmk:
10967 case VPMINSQZrmkz:
10968 case VPMINSQZrr:
10969 case VPMINSQZrrk:
10970 case VPMINSQZrrkz:
10971 return true;
10972 }
10973 return false;
10974}
10975
10976bool isVADDSD(unsigned Opcode) {
10977 switch (Opcode) {
10978 case VADDSDZrm_Int:
10979 case VADDSDZrmk_Int:
10980 case VADDSDZrmkz_Int:
10981 case VADDSDZrr_Int:
10982 case VADDSDZrrb_Int:
10983 case VADDSDZrrbk_Int:
10984 case VADDSDZrrbkz_Int:
10985 case VADDSDZrrk_Int:
10986 case VADDSDZrrkz_Int:
10987 case VADDSDrm_Int:
10988 case VADDSDrr_Int:
10989 return true;
10990 }
10991 return false;
10992}
10993
10994bool isDPPS(unsigned Opcode) {
10995 switch (Opcode) {
10996 case DPPSrmi:
10997 case DPPSrri:
10998 return true;
10999 }
11000 return false;
11001}
11002
11003bool isPINSRQ(unsigned Opcode) {
11004 switch (Opcode) {
11005 case PINSRQrmi:
11006 case PINSRQrri:
11007 return true;
11008 }
11009 return false;
11010}
11011
11012bool isVUCOMISS(unsigned Opcode) {
11013 switch (Opcode) {
11014 case VUCOMISSZrm:
11015 case VUCOMISSZrr:
11016 case VUCOMISSZrrb:
11017 case VUCOMISSrm:
11018 case VUCOMISSrr:
11019 return true;
11020 }
11021 return false;
11022}
11023
11024bool isVPDPWSUD(unsigned Opcode) {
11025 switch (Opcode) {
11026 case VPDPWSUDYrm:
11027 case VPDPWSUDYrr:
11028 case VPDPWSUDZ128rm:
11029 case VPDPWSUDZ128rmb:
11030 case VPDPWSUDZ128rmbk:
11031 case VPDPWSUDZ128rmbkz:
11032 case VPDPWSUDZ128rmk:
11033 case VPDPWSUDZ128rmkz:
11034 case VPDPWSUDZ128rr:
11035 case VPDPWSUDZ128rrk:
11036 case VPDPWSUDZ128rrkz:
11037 case VPDPWSUDZ256rm:
11038 case VPDPWSUDZ256rmb:
11039 case VPDPWSUDZ256rmbk:
11040 case VPDPWSUDZ256rmbkz:
11041 case VPDPWSUDZ256rmk:
11042 case VPDPWSUDZ256rmkz:
11043 case VPDPWSUDZ256rr:
11044 case VPDPWSUDZ256rrk:
11045 case VPDPWSUDZ256rrkz:
11046 case VPDPWSUDZrm:
11047 case VPDPWSUDZrmb:
11048 case VPDPWSUDZrmbk:
11049 case VPDPWSUDZrmbkz:
11050 case VPDPWSUDZrmk:
11051 case VPDPWSUDZrmkz:
11052 case VPDPWSUDZrr:
11053 case VPDPWSUDZrrk:
11054 case VPDPWSUDZrrkz:
11055 case VPDPWSUDrm:
11056 case VPDPWSUDrr:
11057 return true;
11058 }
11059 return false;
11060}
11061
11062bool isKANDNW(unsigned Opcode) {
11063 return Opcode == KANDNWkk;
11064}
11065
11066bool isAOR(unsigned Opcode) {
11067 switch (Opcode) {
11068 case AOR32mr:
11069 case AOR32mr_EVEX:
11070 case AOR64mr:
11071 case AOR64mr_EVEX:
11072 return true;
11073 }
11074 return false;
11075}
11076
11077bool isPMAXUB(unsigned Opcode) {
11078 switch (Opcode) {
11079 case MMX_PMAXUBrm:
11080 case MMX_PMAXUBrr:
11081 case PMAXUBrm:
11082 case PMAXUBrr:
11083 return true;
11084 }
11085 return false;
11086}
11087
11088bool isANDNPD(unsigned Opcode) {
11089 switch (Opcode) {
11090 case ANDNPDrm:
11091 case ANDNPDrr:
11092 return true;
11093 }
11094 return false;
11095}
11096
11097bool isINVPCID(unsigned Opcode) {
11098 switch (Opcode) {
11099 case INVPCID32:
11100 case INVPCID64:
11101 case INVPCID64_EVEX:
11102 return true;
11103 }
11104 return false;
11105}
11106
11107bool isRDGSBASE(unsigned Opcode) {
11108 switch (Opcode) {
11109 case RDGSBASE:
11110 case RDGSBASE64:
11111 return true;
11112 }
11113 return false;
11114}
11115
11116bool isVPMOVSQD(unsigned Opcode) {
11117 switch (Opcode) {
11118 case VPMOVSQDZ128mr:
11119 case VPMOVSQDZ128mrk:
11120 case VPMOVSQDZ128rr:
11121 case VPMOVSQDZ128rrk:
11122 case VPMOVSQDZ128rrkz:
11123 case VPMOVSQDZ256mr:
11124 case VPMOVSQDZ256mrk:
11125 case VPMOVSQDZ256rr:
11126 case VPMOVSQDZ256rrk:
11127 case VPMOVSQDZ256rrkz:
11128 case VPMOVSQDZmr:
11129 case VPMOVSQDZmrk:
11130 case VPMOVSQDZrr:
11131 case VPMOVSQDZrrk:
11132 case VPMOVSQDZrrkz:
11133 return true;
11134 }
11135 return false;
11136}
11137
11138bool isBT(unsigned Opcode) {
11139 switch (Opcode) {
11140 case BT16mi8:
11141 case BT16mr:
11142 case BT16ri8:
11143 case BT16rr:
11144 case BT32mi8:
11145 case BT32mr:
11146 case BT32ri8:
11147 case BT32rr:
11148 case BT64mi8:
11149 case BT64mr:
11150 case BT64ri8:
11151 case BT64rr:
11152 return true;
11153 }
11154 return false;
11155}
11156
11157bool isVPROLVQ(unsigned Opcode) {
11158 switch (Opcode) {
11159 case VPROLVQZ128rm:
11160 case VPROLVQZ128rmb:
11161 case VPROLVQZ128rmbk:
11162 case VPROLVQZ128rmbkz:
11163 case VPROLVQZ128rmk:
11164 case VPROLVQZ128rmkz:
11165 case VPROLVQZ128rr:
11166 case VPROLVQZ128rrk:
11167 case VPROLVQZ128rrkz:
11168 case VPROLVQZ256rm:
11169 case VPROLVQZ256rmb:
11170 case VPROLVQZ256rmbk:
11171 case VPROLVQZ256rmbkz:
11172 case VPROLVQZ256rmk:
11173 case VPROLVQZ256rmkz:
11174 case VPROLVQZ256rr:
11175 case VPROLVQZ256rrk:
11176 case VPROLVQZ256rrkz:
11177 case VPROLVQZrm:
11178 case VPROLVQZrmb:
11179 case VPROLVQZrmbk:
11180 case VPROLVQZrmbkz:
11181 case VPROLVQZrmk:
11182 case VPROLVQZrmkz:
11183 case VPROLVQZrr:
11184 case VPROLVQZrrk:
11185 case VPROLVQZrrkz:
11186 return true;
11187 }
11188 return false;
11189}
11190
11191bool isVFMADDSUB132PD(unsigned Opcode) {
11192 switch (Opcode) {
11193 case VFMADDSUB132PDYm:
11194 case VFMADDSUB132PDYr:
11195 case VFMADDSUB132PDZ128m:
11196 case VFMADDSUB132PDZ128mb:
11197 case VFMADDSUB132PDZ128mbk:
11198 case VFMADDSUB132PDZ128mbkz:
11199 case VFMADDSUB132PDZ128mk:
11200 case VFMADDSUB132PDZ128mkz:
11201 case VFMADDSUB132PDZ128r:
11202 case VFMADDSUB132PDZ128rk:
11203 case VFMADDSUB132PDZ128rkz:
11204 case VFMADDSUB132PDZ256m:
11205 case VFMADDSUB132PDZ256mb:
11206 case VFMADDSUB132PDZ256mbk:
11207 case VFMADDSUB132PDZ256mbkz:
11208 case VFMADDSUB132PDZ256mk:
11209 case VFMADDSUB132PDZ256mkz:
11210 case VFMADDSUB132PDZ256r:
11211 case VFMADDSUB132PDZ256rk:
11212 case VFMADDSUB132PDZ256rkz:
11213 case VFMADDSUB132PDZm:
11214 case VFMADDSUB132PDZmb:
11215 case VFMADDSUB132PDZmbk:
11216 case VFMADDSUB132PDZmbkz:
11217 case VFMADDSUB132PDZmk:
11218 case VFMADDSUB132PDZmkz:
11219 case VFMADDSUB132PDZr:
11220 case VFMADDSUB132PDZrb:
11221 case VFMADDSUB132PDZrbk:
11222 case VFMADDSUB132PDZrbkz:
11223 case VFMADDSUB132PDZrk:
11224 case VFMADDSUB132PDZrkz:
11225 case VFMADDSUB132PDm:
11226 case VFMADDSUB132PDr:
11227 return true;
11228 }
11229 return false;
11230}
11231
11232bool isRORX(unsigned Opcode) {
11233 switch (Opcode) {
11234 case RORX32mi:
11235 case RORX32mi_EVEX:
11236 case RORX32ri:
11237 case RORX32ri_EVEX:
11238 case RORX64mi:
11239 case RORX64mi_EVEX:
11240 case RORX64ri:
11241 case RORX64ri_EVEX:
11242 return true;
11243 }
11244 return false;
11245}
11246
11247bool isPADDUSW(unsigned Opcode) {
11248 switch (Opcode) {
11249 case MMX_PADDUSWrm:
11250 case MMX_PADDUSWrr:
11251 case PADDUSWrm:
11252 case PADDUSWrr:
11253 return true;
11254 }
11255 return false;
11256}
11257
11258bool isPFNACC(unsigned Opcode) {
11259 switch (Opcode) {
11260 case PFNACCrm:
11261 case PFNACCrr:
11262 return true;
11263 }
11264 return false;
11265}
11266
11267bool isAND(unsigned Opcode) {
11268 switch (Opcode) {
11269 case AND16i16:
11270 case AND16mi:
11271 case AND16mi8:
11272 case AND16mi8_EVEX:
11273 case AND16mi8_ND:
11274 case AND16mi8_NF:
11275 case AND16mi8_NF_ND:
11276 case AND16mi_EVEX:
11277 case AND16mi_ND:
11278 case AND16mi_NF:
11279 case AND16mi_NF_ND:
11280 case AND16mr:
11281 case AND16mr_EVEX:
11282 case AND16mr_ND:
11283 case AND16mr_NF:
11284 case AND16mr_NF_ND:
11285 case AND16ri:
11286 case AND16ri8:
11287 case AND16ri8_EVEX:
11288 case AND16ri8_ND:
11289 case AND16ri8_NF:
11290 case AND16ri8_NF_ND:
11291 case AND16ri_EVEX:
11292 case AND16ri_ND:
11293 case AND16ri_NF:
11294 case AND16ri_NF_ND:
11295 case AND16rm:
11296 case AND16rm_EVEX:
11297 case AND16rm_ND:
11298 case AND16rm_NF:
11299 case AND16rm_NF_ND:
11300 case AND16rr:
11301 case AND16rr_EVEX:
11302 case AND16rr_EVEX_REV:
11303 case AND16rr_ND:
11304 case AND16rr_ND_REV:
11305 case AND16rr_NF:
11306 case AND16rr_NF_ND:
11307 case AND16rr_NF_ND_REV:
11308 case AND16rr_NF_REV:
11309 case AND16rr_REV:
11310 case AND32i32:
11311 case AND32mi:
11312 case AND32mi8:
11313 case AND32mi8_EVEX:
11314 case AND32mi8_ND:
11315 case AND32mi8_NF:
11316 case AND32mi8_NF_ND:
11317 case AND32mi_EVEX:
11318 case AND32mi_ND:
11319 case AND32mi_NF:
11320 case AND32mi_NF_ND:
11321 case AND32mr:
11322 case AND32mr_EVEX:
11323 case AND32mr_ND:
11324 case AND32mr_NF:
11325 case AND32mr_NF_ND:
11326 case AND32ri:
11327 case AND32ri8:
11328 case AND32ri8_EVEX:
11329 case AND32ri8_ND:
11330 case AND32ri8_NF:
11331 case AND32ri8_NF_ND:
11332 case AND32ri_EVEX:
11333 case AND32ri_ND:
11334 case AND32ri_NF:
11335 case AND32ri_NF_ND:
11336 case AND32rm:
11337 case AND32rm_EVEX:
11338 case AND32rm_ND:
11339 case AND32rm_NF:
11340 case AND32rm_NF_ND:
11341 case AND32rr:
11342 case AND32rr_EVEX:
11343 case AND32rr_EVEX_REV:
11344 case AND32rr_ND:
11345 case AND32rr_ND_REV:
11346 case AND32rr_NF:
11347 case AND32rr_NF_ND:
11348 case AND32rr_NF_ND_REV:
11349 case AND32rr_NF_REV:
11350 case AND32rr_REV:
11351 case AND64i32:
11352 case AND64mi32:
11353 case AND64mi32_EVEX:
11354 case AND64mi32_ND:
11355 case AND64mi32_NF:
11356 case AND64mi32_NF_ND:
11357 case AND64mi8:
11358 case AND64mi8_EVEX:
11359 case AND64mi8_ND:
11360 case AND64mi8_NF:
11361 case AND64mi8_NF_ND:
11362 case AND64mr:
11363 case AND64mr_EVEX:
11364 case AND64mr_ND:
11365 case AND64mr_NF:
11366 case AND64mr_NF_ND:
11367 case AND64ri32:
11368 case AND64ri32_EVEX:
11369 case AND64ri32_ND:
11370 case AND64ri32_NF:
11371 case AND64ri32_NF_ND:
11372 case AND64ri8:
11373 case AND64ri8_EVEX:
11374 case AND64ri8_ND:
11375 case AND64ri8_NF:
11376 case AND64ri8_NF_ND:
11377 case AND64rm:
11378 case AND64rm_EVEX:
11379 case AND64rm_ND:
11380 case AND64rm_NF:
11381 case AND64rm_NF_ND:
11382 case AND64rr:
11383 case AND64rr_EVEX:
11384 case AND64rr_EVEX_REV:
11385 case AND64rr_ND:
11386 case AND64rr_ND_REV:
11387 case AND64rr_NF:
11388 case AND64rr_NF_ND:
11389 case AND64rr_NF_ND_REV:
11390 case AND64rr_NF_REV:
11391 case AND64rr_REV:
11392 case AND8i8:
11393 case AND8mi:
11394 case AND8mi8:
11395 case AND8mi_EVEX:
11396 case AND8mi_ND:
11397 case AND8mi_NF:
11398 case AND8mi_NF_ND:
11399 case AND8mr:
11400 case AND8mr_EVEX:
11401 case AND8mr_ND:
11402 case AND8mr_NF:
11403 case AND8mr_NF_ND:
11404 case AND8ri:
11405 case AND8ri8:
11406 case AND8ri_EVEX:
11407 case AND8ri_ND:
11408 case AND8ri_NF:
11409 case AND8ri_NF_ND:
11410 case AND8rm:
11411 case AND8rm_EVEX:
11412 case AND8rm_ND:
11413 case AND8rm_NF:
11414 case AND8rm_NF_ND:
11415 case AND8rr:
11416 case AND8rr_EVEX:
11417 case AND8rr_EVEX_REV:
11418 case AND8rr_ND:
11419 case AND8rr_ND_REV:
11420 case AND8rr_NF:
11421 case AND8rr_NF_ND:
11422 case AND8rr_NF_ND_REV:
11423 case AND8rr_NF_REV:
11424 case AND8rr_REV:
11425 return true;
11426 }
11427 return false;
11428}
11429
11430bool isPSLLQ(unsigned Opcode) {
11431 switch (Opcode) {
11432 case MMX_PSLLQri:
11433 case MMX_PSLLQrm:
11434 case MMX_PSLLQrr:
11435 case PSLLQri:
11436 case PSLLQrm:
11437 case PSLLQrr:
11438 return true;
11439 }
11440 return false;
11441}
11442
11443bool isVFMSUB132PH(unsigned Opcode) {
11444 switch (Opcode) {
11445 case VFMSUB132PHZ128m:
11446 case VFMSUB132PHZ128mb:
11447 case VFMSUB132PHZ128mbk:
11448 case VFMSUB132PHZ128mbkz:
11449 case VFMSUB132PHZ128mk:
11450 case VFMSUB132PHZ128mkz:
11451 case VFMSUB132PHZ128r:
11452 case VFMSUB132PHZ128rk:
11453 case VFMSUB132PHZ128rkz:
11454 case VFMSUB132PHZ256m:
11455 case VFMSUB132PHZ256mb:
11456 case VFMSUB132PHZ256mbk:
11457 case VFMSUB132PHZ256mbkz:
11458 case VFMSUB132PHZ256mk:
11459 case VFMSUB132PHZ256mkz:
11460 case VFMSUB132PHZ256r:
11461 case VFMSUB132PHZ256rk:
11462 case VFMSUB132PHZ256rkz:
11463 case VFMSUB132PHZm:
11464 case VFMSUB132PHZmb:
11465 case VFMSUB132PHZmbk:
11466 case VFMSUB132PHZmbkz:
11467 case VFMSUB132PHZmk:
11468 case VFMSUB132PHZmkz:
11469 case VFMSUB132PHZr:
11470 case VFMSUB132PHZrb:
11471 case VFMSUB132PHZrbk:
11472 case VFMSUB132PHZrbkz:
11473 case VFMSUB132PHZrk:
11474 case VFMSUB132PHZrkz:
11475 return true;
11476 }
11477 return false;
11478}
11479
11480bool isXSAVE(unsigned Opcode) {
11481 return Opcode == XSAVE;
11482}
11483
11484bool isKNOTQ(unsigned Opcode) {
11485 return Opcode == KNOTQkk;
11486}
11487
11488bool isXTEST(unsigned Opcode) {
11489 return Opcode == XTEST;
11490}
11491
11492bool isVINSERTPS(unsigned Opcode) {
11493 switch (Opcode) {
11494 case VINSERTPSZrmi:
11495 case VINSERTPSZrri:
11496 case VINSERTPSrmi:
11497 case VINSERTPSrri:
11498 return true;
11499 }
11500 return false;
11501}
11502
11503bool isXSAVEOPT(unsigned Opcode) {
11504 return Opcode == XSAVEOPT;
11505}
11506
11507bool isLDS(unsigned Opcode) {
11508 switch (Opcode) {
11509 case LDS16rm:
11510 case LDS32rm:
11511 return true;
11512 }
11513 return false;
11514}
11515
11516bool isVFMADDSUB213PD(unsigned Opcode) {
11517 switch (Opcode) {
11518 case VFMADDSUB213PDYm:
11519 case VFMADDSUB213PDYr:
11520 case VFMADDSUB213PDZ128m:
11521 case VFMADDSUB213PDZ128mb:
11522 case VFMADDSUB213PDZ128mbk:
11523 case VFMADDSUB213PDZ128mbkz:
11524 case VFMADDSUB213PDZ128mk:
11525 case VFMADDSUB213PDZ128mkz:
11526 case VFMADDSUB213PDZ128r:
11527 case VFMADDSUB213PDZ128rk:
11528 case VFMADDSUB213PDZ128rkz:
11529 case VFMADDSUB213PDZ256m:
11530 case VFMADDSUB213PDZ256mb:
11531 case VFMADDSUB213PDZ256mbk:
11532 case VFMADDSUB213PDZ256mbkz:
11533 case VFMADDSUB213PDZ256mk:
11534 case VFMADDSUB213PDZ256mkz:
11535 case VFMADDSUB213PDZ256r:
11536 case VFMADDSUB213PDZ256rk:
11537 case VFMADDSUB213PDZ256rkz:
11538 case VFMADDSUB213PDZm:
11539 case VFMADDSUB213PDZmb:
11540 case VFMADDSUB213PDZmbk:
11541 case VFMADDSUB213PDZmbkz:
11542 case VFMADDSUB213PDZmk:
11543 case VFMADDSUB213PDZmkz:
11544 case VFMADDSUB213PDZr:
11545 case VFMADDSUB213PDZrb:
11546 case VFMADDSUB213PDZrbk:
11547 case VFMADDSUB213PDZrbkz:
11548 case VFMADDSUB213PDZrk:
11549 case VFMADDSUB213PDZrkz:
11550 case VFMADDSUB213PDm:
11551 case VFMADDSUB213PDr:
11552 return true;
11553 }
11554 return false;
11555}
11556
11557bool isVINSERTF32X4(unsigned Opcode) {
11558 switch (Opcode) {
11559 case VINSERTF32X4Z256rmi:
11560 case VINSERTF32X4Z256rmik:
11561 case VINSERTF32X4Z256rmikz:
11562 case VINSERTF32X4Z256rri:
11563 case VINSERTF32X4Z256rrik:
11564 case VINSERTF32X4Z256rrikz:
11565 case VINSERTF32X4Zrmi:
11566 case VINSERTF32X4Zrmik:
11567 case VINSERTF32X4Zrmikz:
11568 case VINSERTF32X4Zrri:
11569 case VINSERTF32X4Zrrik:
11570 case VINSERTF32X4Zrrikz:
11571 return true;
11572 }
11573 return false;
11574}
11575
11576bool isVRSQRTPS(unsigned Opcode) {
11577 switch (Opcode) {
11578 case VRSQRTPSYm:
11579 case VRSQRTPSYr:
11580 case VRSQRTPSm:
11581 case VRSQRTPSr:
11582 return true;
11583 }
11584 return false;
11585}
11586
11587bool isVSUBPH(unsigned Opcode) {
11588 switch (Opcode) {
11589 case VSUBPHZ128rm:
11590 case VSUBPHZ128rmb:
11591 case VSUBPHZ128rmbk:
11592 case VSUBPHZ128rmbkz:
11593 case VSUBPHZ128rmk:
11594 case VSUBPHZ128rmkz:
11595 case VSUBPHZ128rr:
11596 case VSUBPHZ128rrk:
11597 case VSUBPHZ128rrkz:
11598 case VSUBPHZ256rm:
11599 case VSUBPHZ256rmb:
11600 case VSUBPHZ256rmbk:
11601 case VSUBPHZ256rmbkz:
11602 case VSUBPHZ256rmk:
11603 case VSUBPHZ256rmkz:
11604 case VSUBPHZ256rr:
11605 case VSUBPHZ256rrk:
11606 case VSUBPHZ256rrkz:
11607 case VSUBPHZrm:
11608 case VSUBPHZrmb:
11609 case VSUBPHZrmbk:
11610 case VSUBPHZrmbkz:
11611 case VSUBPHZrmk:
11612 case VSUBPHZrmkz:
11613 case VSUBPHZrr:
11614 case VSUBPHZrrb:
11615 case VSUBPHZrrbk:
11616 case VSUBPHZrrbkz:
11617 case VSUBPHZrrk:
11618 case VSUBPHZrrkz:
11619 return true;
11620 }
11621 return false;
11622}
11623
11624bool isPMOVSXBW(unsigned Opcode) {
11625 switch (Opcode) {
11626 case PMOVSXBWrm:
11627 case PMOVSXBWrr:
11628 return true;
11629 }
11630 return false;
11631}
11632
11633bool isVPSRLDQ(unsigned Opcode) {
11634 switch (Opcode) {
11635 case VPSRLDQYri:
11636 case VPSRLDQZ128mi:
11637 case VPSRLDQZ128ri:
11638 case VPSRLDQZ256mi:
11639 case VPSRLDQZ256ri:
11640 case VPSRLDQZmi:
11641 case VPSRLDQZri:
11642 case VPSRLDQri:
11643 return true;
11644 }
11645 return false;
11646}
11647
11648bool isADC(unsigned Opcode) {
11649 switch (Opcode) {
11650 case ADC16i16:
11651 case ADC16mi:
11652 case ADC16mi8:
11653 case ADC16mi8_EVEX:
11654 case ADC16mi8_ND:
11655 case ADC16mi_EVEX:
11656 case ADC16mi_ND:
11657 case ADC16mr:
11658 case ADC16mr_EVEX:
11659 case ADC16mr_ND:
11660 case ADC16ri:
11661 case ADC16ri8:
11662 case ADC16ri8_EVEX:
11663 case ADC16ri8_ND:
11664 case ADC16ri_EVEX:
11665 case ADC16ri_ND:
11666 case ADC16rm:
11667 case ADC16rm_EVEX:
11668 case ADC16rm_ND:
11669 case ADC16rr:
11670 case ADC16rr_EVEX:
11671 case ADC16rr_EVEX_REV:
11672 case ADC16rr_ND:
11673 case ADC16rr_ND_REV:
11674 case ADC16rr_REV:
11675 case ADC32i32:
11676 case ADC32mi:
11677 case ADC32mi8:
11678 case ADC32mi8_EVEX:
11679 case ADC32mi8_ND:
11680 case ADC32mi_EVEX:
11681 case ADC32mi_ND:
11682 case ADC32mr:
11683 case ADC32mr_EVEX:
11684 case ADC32mr_ND:
11685 case ADC32ri:
11686 case ADC32ri8:
11687 case ADC32ri8_EVEX:
11688 case ADC32ri8_ND:
11689 case ADC32ri_EVEX:
11690 case ADC32ri_ND:
11691 case ADC32rm:
11692 case ADC32rm_EVEX:
11693 case ADC32rm_ND:
11694 case ADC32rr:
11695 case ADC32rr_EVEX:
11696 case ADC32rr_EVEX_REV:
11697 case ADC32rr_ND:
11698 case ADC32rr_ND_REV:
11699 case ADC32rr_REV:
11700 case ADC64i32:
11701 case ADC64mi32:
11702 case ADC64mi32_EVEX:
11703 case ADC64mi32_ND:
11704 case ADC64mi8:
11705 case ADC64mi8_EVEX:
11706 case ADC64mi8_ND:
11707 case ADC64mr:
11708 case ADC64mr_EVEX:
11709 case ADC64mr_ND:
11710 case ADC64ri32:
11711 case ADC64ri32_EVEX:
11712 case ADC64ri32_ND:
11713 case ADC64ri8:
11714 case ADC64ri8_EVEX:
11715 case ADC64ri8_ND:
11716 case ADC64rm:
11717 case ADC64rm_EVEX:
11718 case ADC64rm_ND:
11719 case ADC64rr:
11720 case ADC64rr_EVEX:
11721 case ADC64rr_EVEX_REV:
11722 case ADC64rr_ND:
11723 case ADC64rr_ND_REV:
11724 case ADC64rr_REV:
11725 case ADC8i8:
11726 case ADC8mi:
11727 case ADC8mi8:
11728 case ADC8mi_EVEX:
11729 case ADC8mi_ND:
11730 case ADC8mr:
11731 case ADC8mr_EVEX:
11732 case ADC8mr_ND:
11733 case ADC8ri:
11734 case ADC8ri8:
11735 case ADC8ri_EVEX:
11736 case ADC8ri_ND:
11737 case ADC8rm:
11738 case ADC8rm_EVEX:
11739 case ADC8rm_ND:
11740 case ADC8rr:
11741 case ADC8rr_EVEX:
11742 case ADC8rr_EVEX_REV:
11743 case ADC8rr_ND:
11744 case ADC8rr_ND_REV:
11745 case ADC8rr_REV:
11746 return true;
11747 }
11748 return false;
11749}
11750
11751bool isPHADDD(unsigned Opcode) {
11752 switch (Opcode) {
11753 case MMX_PHADDDrm:
11754 case MMX_PHADDDrr:
11755 case PHADDDrm:
11756 case PHADDDrr:
11757 return true;
11758 }
11759 return false;
11760}
11761
11762bool isVDPPHPS(unsigned Opcode) {
11763 switch (Opcode) {
11764 case VDPPHPSZ128m:
11765 case VDPPHPSZ128mb:
11766 case VDPPHPSZ128mbk:
11767 case VDPPHPSZ128mbkz:
11768 case VDPPHPSZ128mk:
11769 case VDPPHPSZ128mkz:
11770 case VDPPHPSZ128r:
11771 case VDPPHPSZ128rk:
11772 case VDPPHPSZ128rkz:
11773 case VDPPHPSZ256m:
11774 case VDPPHPSZ256mb:
11775 case VDPPHPSZ256mbk:
11776 case VDPPHPSZ256mbkz:
11777 case VDPPHPSZ256mk:
11778 case VDPPHPSZ256mkz:
11779 case VDPPHPSZ256r:
11780 case VDPPHPSZ256rk:
11781 case VDPPHPSZ256rkz:
11782 case VDPPHPSZm:
11783 case VDPPHPSZmb:
11784 case VDPPHPSZmbk:
11785 case VDPPHPSZmbkz:
11786 case VDPPHPSZmk:
11787 case VDPPHPSZmkz:
11788 case VDPPHPSZr:
11789 case VDPPHPSZrk:
11790 case VDPPHPSZrkz:
11791 return true;
11792 }
11793 return false;
11794}
11795
11796bool isVMINPH(unsigned Opcode) {
11797 switch (Opcode) {
11798 case VMINPHZ128rm:
11799 case VMINPHZ128rmb:
11800 case VMINPHZ128rmbk:
11801 case VMINPHZ128rmbkz:
11802 case VMINPHZ128rmk:
11803 case VMINPHZ128rmkz:
11804 case VMINPHZ128rr:
11805 case VMINPHZ128rrk:
11806 case VMINPHZ128rrkz:
11807 case VMINPHZ256rm:
11808 case VMINPHZ256rmb:
11809 case VMINPHZ256rmbk:
11810 case VMINPHZ256rmbkz:
11811 case VMINPHZ256rmk:
11812 case VMINPHZ256rmkz:
11813 case VMINPHZ256rr:
11814 case VMINPHZ256rrk:
11815 case VMINPHZ256rrkz:
11816 case VMINPHZrm:
11817 case VMINPHZrmb:
11818 case VMINPHZrmbk:
11819 case VMINPHZrmbkz:
11820 case VMINPHZrmk:
11821 case VMINPHZrmkz:
11822 case VMINPHZrr:
11823 case VMINPHZrrb:
11824 case VMINPHZrrbk:
11825 case VMINPHZrrbkz:
11826 case VMINPHZrrk:
11827 case VMINPHZrrkz:
11828 return true;
11829 }
11830 return false;
11831}
11832
11833bool isVMINSD(unsigned Opcode) {
11834 switch (Opcode) {
11835 case VMINSDZrm_Int:
11836 case VMINSDZrmk_Int:
11837 case VMINSDZrmkz_Int:
11838 case VMINSDZrr_Int:
11839 case VMINSDZrrb_Int:
11840 case VMINSDZrrbk_Int:
11841 case VMINSDZrrbkz_Int:
11842 case VMINSDZrrk_Int:
11843 case VMINSDZrrkz_Int:
11844 case VMINSDrm_Int:
11845 case VMINSDrr_Int:
11846 return true;
11847 }
11848 return false;
11849}
11850
11851bool isVROUNDPD(unsigned Opcode) {
11852 switch (Opcode) {
11853 case VROUNDPDYmi:
11854 case VROUNDPDYri:
11855 case VROUNDPDmi:
11856 case VROUNDPDri:
11857 return true;
11858 }
11859 return false;
11860}
11861
11862bool isVFCMADDCPH(unsigned Opcode) {
11863 switch (Opcode) {
11864 case VFCMADDCPHZ128m:
11865 case VFCMADDCPHZ128mb:
11866 case VFCMADDCPHZ128mbk:
11867 case VFCMADDCPHZ128mbkz:
11868 case VFCMADDCPHZ128mk:
11869 case VFCMADDCPHZ128mkz:
11870 case VFCMADDCPHZ128r:
11871 case VFCMADDCPHZ128rk:
11872 case VFCMADDCPHZ128rkz:
11873 case VFCMADDCPHZ256m:
11874 case VFCMADDCPHZ256mb:
11875 case VFCMADDCPHZ256mbk:
11876 case VFCMADDCPHZ256mbkz:
11877 case VFCMADDCPHZ256mk:
11878 case VFCMADDCPHZ256mkz:
11879 case VFCMADDCPHZ256r:
11880 case VFCMADDCPHZ256rk:
11881 case VFCMADDCPHZ256rkz:
11882 case VFCMADDCPHZm:
11883 case VFCMADDCPHZmb:
11884 case VFCMADDCPHZmbk:
11885 case VFCMADDCPHZmbkz:
11886 case VFCMADDCPHZmk:
11887 case VFCMADDCPHZmkz:
11888 case VFCMADDCPHZr:
11889 case VFCMADDCPHZrb:
11890 case VFCMADDCPHZrbk:
11891 case VFCMADDCPHZrbkz:
11892 case VFCMADDCPHZrk:
11893 case VFCMADDCPHZrkz:
11894 return true;
11895 }
11896 return false;
11897}
11898
11899bool isINCSSPQ(unsigned Opcode) {
11900 return Opcode == INCSSPQ;
11901}
11902
11903bool isVPUNPCKLDQ(unsigned Opcode) {
11904 switch (Opcode) {
11905 case VPUNPCKLDQYrm:
11906 case VPUNPCKLDQYrr:
11907 case VPUNPCKLDQZ128rm:
11908 case VPUNPCKLDQZ128rmb:
11909 case VPUNPCKLDQZ128rmbk:
11910 case VPUNPCKLDQZ128rmbkz:
11911 case VPUNPCKLDQZ128rmk:
11912 case VPUNPCKLDQZ128rmkz:
11913 case VPUNPCKLDQZ128rr:
11914 case VPUNPCKLDQZ128rrk:
11915 case VPUNPCKLDQZ128rrkz:
11916 case VPUNPCKLDQZ256rm:
11917 case VPUNPCKLDQZ256rmb:
11918 case VPUNPCKLDQZ256rmbk:
11919 case VPUNPCKLDQZ256rmbkz:
11920 case VPUNPCKLDQZ256rmk:
11921 case VPUNPCKLDQZ256rmkz:
11922 case VPUNPCKLDQZ256rr:
11923 case VPUNPCKLDQZ256rrk:
11924 case VPUNPCKLDQZ256rrkz:
11925 case VPUNPCKLDQZrm:
11926 case VPUNPCKLDQZrmb:
11927 case VPUNPCKLDQZrmbk:
11928 case VPUNPCKLDQZrmbkz:
11929 case VPUNPCKLDQZrmk:
11930 case VPUNPCKLDQZrmkz:
11931 case VPUNPCKLDQZrr:
11932 case VPUNPCKLDQZrrk:
11933 case VPUNPCKLDQZrrkz:
11934 case VPUNPCKLDQrm:
11935 case VPUNPCKLDQrr:
11936 return true;
11937 }
11938 return false;
11939}
11940
11941bool isVMINSH(unsigned Opcode) {
11942 switch (Opcode) {
11943 case VMINSHZrm_Int:
11944 case VMINSHZrmk_Int:
11945 case VMINSHZrmkz_Int:
11946 case VMINSHZrr_Int:
11947 case VMINSHZrrb_Int:
11948 case VMINSHZrrbk_Int:
11949 case VMINSHZrrbkz_Int:
11950 case VMINSHZrrk_Int:
11951 case VMINSHZrrkz_Int:
11952 return true;
11953 }
11954 return false;
11955}
11956
11957bool isINSERTQ(unsigned Opcode) {
11958 switch (Opcode) {
11959 case INSERTQ:
11960 case INSERTQI:
11961 return true;
11962 }
11963 return false;
11964}
11965
11966bool isBLCI(unsigned Opcode) {
11967 switch (Opcode) {
11968 case BLCI32rm:
11969 case BLCI32rr:
11970 case BLCI64rm:
11971 case BLCI64rr:
11972 return true;
11973 }
11974 return false;
11975}
11976
11977bool isHLT(unsigned Opcode) {
11978 return Opcode == HLT;
11979}
11980
11981bool isVPCOMUW(unsigned Opcode) {
11982 switch (Opcode) {
11983 case VPCOMUWmi:
11984 case VPCOMUWri:
11985 return true;
11986 }
11987 return false;
11988}
11989
11990bool isVPMOVSXDQ(unsigned Opcode) {
11991 switch (Opcode) {
11992 case VPMOVSXDQYrm:
11993 case VPMOVSXDQYrr:
11994 case VPMOVSXDQZ128rm:
11995 case VPMOVSXDQZ128rmk:
11996 case VPMOVSXDQZ128rmkz:
11997 case VPMOVSXDQZ128rr:
11998 case VPMOVSXDQZ128rrk:
11999 case VPMOVSXDQZ128rrkz:
12000 case VPMOVSXDQZ256rm:
12001 case VPMOVSXDQZ256rmk:
12002 case VPMOVSXDQZ256rmkz:
12003 case VPMOVSXDQZ256rr:
12004 case VPMOVSXDQZ256rrk:
12005 case VPMOVSXDQZ256rrkz:
12006 case VPMOVSXDQZrm:
12007 case VPMOVSXDQZrmk:
12008 case VPMOVSXDQZrmkz:
12009 case VPMOVSXDQZrr:
12010 case VPMOVSXDQZrrk:
12011 case VPMOVSXDQZrrkz:
12012 case VPMOVSXDQrm:
12013 case VPMOVSXDQrr:
12014 return true;
12015 }
12016 return false;
12017}
12018
12019bool isVFNMSUB231PS(unsigned Opcode) {
12020 switch (Opcode) {
12021 case VFNMSUB231PSYm:
12022 case VFNMSUB231PSYr:
12023 case VFNMSUB231PSZ128m:
12024 case VFNMSUB231PSZ128mb:
12025 case VFNMSUB231PSZ128mbk:
12026 case VFNMSUB231PSZ128mbkz:
12027 case VFNMSUB231PSZ128mk:
12028 case VFNMSUB231PSZ128mkz:
12029 case VFNMSUB231PSZ128r:
12030 case VFNMSUB231PSZ128rk:
12031 case VFNMSUB231PSZ128rkz:
12032 case VFNMSUB231PSZ256m:
12033 case VFNMSUB231PSZ256mb:
12034 case VFNMSUB231PSZ256mbk:
12035 case VFNMSUB231PSZ256mbkz:
12036 case VFNMSUB231PSZ256mk:
12037 case VFNMSUB231PSZ256mkz:
12038 case VFNMSUB231PSZ256r:
12039 case VFNMSUB231PSZ256rk:
12040 case VFNMSUB231PSZ256rkz:
12041 case VFNMSUB231PSZm:
12042 case VFNMSUB231PSZmb:
12043 case VFNMSUB231PSZmbk:
12044 case VFNMSUB231PSZmbkz:
12045 case VFNMSUB231PSZmk:
12046 case VFNMSUB231PSZmkz:
12047 case VFNMSUB231PSZr:
12048 case VFNMSUB231PSZrb:
12049 case VFNMSUB231PSZrbk:
12050 case VFNMSUB231PSZrbkz:
12051 case VFNMSUB231PSZrk:
12052 case VFNMSUB231PSZrkz:
12053 case VFNMSUB231PSm:
12054 case VFNMSUB231PSr:
12055 return true;
12056 }
12057 return false;
12058}
12059
12060bool isVFNMSUB213SH(unsigned Opcode) {
12061 switch (Opcode) {
12062 case VFNMSUB213SHZm_Int:
12063 case VFNMSUB213SHZmk_Int:
12064 case VFNMSUB213SHZmkz_Int:
12065 case VFNMSUB213SHZr_Int:
12066 case VFNMSUB213SHZrb_Int:
12067 case VFNMSUB213SHZrbk_Int:
12068 case VFNMSUB213SHZrbkz_Int:
12069 case VFNMSUB213SHZrk_Int:
12070 case VFNMSUB213SHZrkz_Int:
12071 return true;
12072 }
12073 return false;
12074}
12075
12076bool isVCVTTPD2UQQ(unsigned Opcode) {
12077 switch (Opcode) {
12078 case VCVTTPD2UQQZ128rm:
12079 case VCVTTPD2UQQZ128rmb:
12080 case VCVTTPD2UQQZ128rmbk:
12081 case VCVTTPD2UQQZ128rmbkz:
12082 case VCVTTPD2UQQZ128rmk:
12083 case VCVTTPD2UQQZ128rmkz:
12084 case VCVTTPD2UQQZ128rr:
12085 case VCVTTPD2UQQZ128rrk:
12086 case VCVTTPD2UQQZ128rrkz:
12087 case VCVTTPD2UQQZ256rm:
12088 case VCVTTPD2UQQZ256rmb:
12089 case VCVTTPD2UQQZ256rmbk:
12090 case VCVTTPD2UQQZ256rmbkz:
12091 case VCVTTPD2UQQZ256rmk:
12092 case VCVTTPD2UQQZ256rmkz:
12093 case VCVTTPD2UQQZ256rr:
12094 case VCVTTPD2UQQZ256rrk:
12095 case VCVTTPD2UQQZ256rrkz:
12096 case VCVTTPD2UQQZrm:
12097 case VCVTTPD2UQQZrmb:
12098 case VCVTTPD2UQQZrmbk:
12099 case VCVTTPD2UQQZrmbkz:
12100 case VCVTTPD2UQQZrmk:
12101 case VCVTTPD2UQQZrmkz:
12102 case VCVTTPD2UQQZrr:
12103 case VCVTTPD2UQQZrrb:
12104 case VCVTTPD2UQQZrrbk:
12105 case VCVTTPD2UQQZrrbkz:
12106 case VCVTTPD2UQQZrrk:
12107 case VCVTTPD2UQQZrrkz:
12108 return true;
12109 }
12110 return false;
12111}
12112
12113bool isSQRTSS(unsigned Opcode) {
12114 switch (Opcode) {
12115 case SQRTSSm_Int:
12116 case SQRTSSr_Int:
12117 return true;
12118 }
12119 return false;
12120}
12121
12122bool isIMUL(unsigned Opcode) {
12123 switch (Opcode) {
12124 case IMUL16m:
12125 case IMUL16m_EVEX:
12126 case IMUL16m_NF:
12127 case IMUL16r:
12128 case IMUL16r_EVEX:
12129 case IMUL16r_NF:
12130 case IMUL16rm:
12131 case IMUL16rm_EVEX:
12132 case IMUL16rm_ND:
12133 case IMUL16rm_NF:
12134 case IMUL16rm_NF_ND:
12135 case IMUL16rmi:
12136 case IMUL16rmi8:
12137 case IMUL16rmi8_EVEX:
12138 case IMUL16rmi8_NF:
12139 case IMUL16rmi_EVEX:
12140 case IMUL16rmi_NF:
12141 case IMUL16rr:
12142 case IMUL16rr_EVEX:
12143 case IMUL16rr_ND:
12144 case IMUL16rr_NF:
12145 case IMUL16rr_NF_ND:
12146 case IMUL16rri:
12147 case IMUL16rri8:
12148 case IMUL16rri8_EVEX:
12149 case IMUL16rri8_NF:
12150 case IMUL16rri_EVEX:
12151 case IMUL16rri_NF:
12152 case IMUL32m:
12153 case IMUL32m_EVEX:
12154 case IMUL32m_NF:
12155 case IMUL32r:
12156 case IMUL32r_EVEX:
12157 case IMUL32r_NF:
12158 case IMUL32rm:
12159 case IMUL32rm_EVEX:
12160 case IMUL32rm_ND:
12161 case IMUL32rm_NF:
12162 case IMUL32rm_NF_ND:
12163 case IMUL32rmi:
12164 case IMUL32rmi8:
12165 case IMUL32rmi8_EVEX:
12166 case IMUL32rmi8_NF:
12167 case IMUL32rmi_EVEX:
12168 case IMUL32rmi_NF:
12169 case IMUL32rr:
12170 case IMUL32rr_EVEX:
12171 case IMUL32rr_ND:
12172 case IMUL32rr_NF:
12173 case IMUL32rr_NF_ND:
12174 case IMUL32rri:
12175 case IMUL32rri8:
12176 case IMUL32rri8_EVEX:
12177 case IMUL32rri8_NF:
12178 case IMUL32rri_EVEX:
12179 case IMUL32rri_NF:
12180 case IMUL64m:
12181 case IMUL64m_EVEX:
12182 case IMUL64m_NF:
12183 case IMUL64r:
12184 case IMUL64r_EVEX:
12185 case IMUL64r_NF:
12186 case IMUL64rm:
12187 case IMUL64rm_EVEX:
12188 case IMUL64rm_ND:
12189 case IMUL64rm_NF:
12190 case IMUL64rm_NF_ND:
12191 case IMUL64rmi32:
12192 case IMUL64rmi32_EVEX:
12193 case IMUL64rmi32_NF:
12194 case IMUL64rmi8:
12195 case IMUL64rmi8_EVEX:
12196 case IMUL64rmi8_NF:
12197 case IMUL64rr:
12198 case IMUL64rr_EVEX:
12199 case IMUL64rr_ND:
12200 case IMUL64rr_NF:
12201 case IMUL64rr_NF_ND:
12202 case IMUL64rri32:
12203 case IMUL64rri32_EVEX:
12204 case IMUL64rri32_NF:
12205 case IMUL64rri8:
12206 case IMUL64rri8_EVEX:
12207 case IMUL64rri8_NF:
12208 case IMUL8m:
12209 case IMUL8m_EVEX:
12210 case IMUL8m_NF:
12211 case IMUL8r:
12212 case IMUL8r_EVEX:
12213 case IMUL8r_NF:
12214 return true;
12215 }
12216 return false;
12217}
12218
12219bool isVCVTSS2SI(unsigned Opcode) {
12220 switch (Opcode) {
12221 case VCVTSS2SI64Zrm_Int:
12222 case VCVTSS2SI64Zrr_Int:
12223 case VCVTSS2SI64Zrrb_Int:
12224 case VCVTSS2SI64rm_Int:
12225 case VCVTSS2SI64rr_Int:
12226 case VCVTSS2SIZrm_Int:
12227 case VCVTSS2SIZrr_Int:
12228 case VCVTSS2SIZrrb_Int:
12229 case VCVTSS2SIrm_Int:
12230 case VCVTSS2SIrr_Int:
12231 return true;
12232 }
12233 return false;
12234}
12235
12236bool isPUSHAW(unsigned Opcode) {
12237 return Opcode == PUSHA16;
12238}
12239
12240bool isSTOSD(unsigned Opcode) {
12241 return Opcode == STOSL;
12242}
12243
12244bool isPSRLDQ(unsigned Opcode) {
12245 return Opcode == PSRLDQri;
12246}
12247
12248bool isVSCATTERQPS(unsigned Opcode) {
12249 switch (Opcode) {
12250 case VSCATTERQPSZ128mr:
12251 case VSCATTERQPSZ256mr:
12252 case VSCATTERQPSZmr:
12253 return true;
12254 }
12255 return false;
12256}
12257
12258bool isFIDIV(unsigned Opcode) {
12259 switch (Opcode) {
12260 case DIV_FI16m:
12261 case DIV_FI32m:
12262 return true;
12263 }
12264 return false;
12265}
12266
12267bool isVFMSUB213PD(unsigned Opcode) {
12268 switch (Opcode) {
12269 case VFMSUB213PDYm:
12270 case VFMSUB213PDYr:
12271 case VFMSUB213PDZ128m:
12272 case VFMSUB213PDZ128mb:
12273 case VFMSUB213PDZ128mbk:
12274 case VFMSUB213PDZ128mbkz:
12275 case VFMSUB213PDZ128mk:
12276 case VFMSUB213PDZ128mkz:
12277 case VFMSUB213PDZ128r:
12278 case VFMSUB213PDZ128rk:
12279 case VFMSUB213PDZ128rkz:
12280 case VFMSUB213PDZ256m:
12281 case VFMSUB213PDZ256mb:
12282 case VFMSUB213PDZ256mbk:
12283 case VFMSUB213PDZ256mbkz:
12284 case VFMSUB213PDZ256mk:
12285 case VFMSUB213PDZ256mkz:
12286 case VFMSUB213PDZ256r:
12287 case VFMSUB213PDZ256rk:
12288 case VFMSUB213PDZ256rkz:
12289 case VFMSUB213PDZm:
12290 case VFMSUB213PDZmb:
12291 case VFMSUB213PDZmbk:
12292 case VFMSUB213PDZmbkz:
12293 case VFMSUB213PDZmk:
12294 case VFMSUB213PDZmkz:
12295 case VFMSUB213PDZr:
12296 case VFMSUB213PDZrb:
12297 case VFMSUB213PDZrbk:
12298 case VFMSUB213PDZrbkz:
12299 case VFMSUB213PDZrk:
12300 case VFMSUB213PDZrkz:
12301 case VFMSUB213PDm:
12302 case VFMSUB213PDr:
12303 return true;
12304 }
12305 return false;
12306}
12307
12308bool isVCVTBF62HF8(unsigned Opcode) {
12309 switch (Opcode) {
12310 case VCVTBF62HF8Z128rr:
12311 case VCVTBF62HF8Z128rrk:
12312 case VCVTBF62HF8Z128rrkz:
12313 case VCVTBF62HF8Z256rr:
12314 case VCVTBF62HF8Z256rrk:
12315 case VCVTBF62HF8Z256rrkz:
12316 case VCVTBF62HF8Zrr:
12317 case VCVTBF62HF8Zrrk:
12318 case VCVTBF62HF8Zrrkz:
12319 return true;
12320 }
12321 return false;
12322}
12323
12324bool isVFMADDSUB231PH(unsigned Opcode) {
12325 switch (Opcode) {
12326 case VFMADDSUB231PHZ128m:
12327 case VFMADDSUB231PHZ128mb:
12328 case VFMADDSUB231PHZ128mbk:
12329 case VFMADDSUB231PHZ128mbkz:
12330 case VFMADDSUB231PHZ128mk:
12331 case VFMADDSUB231PHZ128mkz:
12332 case VFMADDSUB231PHZ128r:
12333 case VFMADDSUB231PHZ128rk:
12334 case VFMADDSUB231PHZ128rkz:
12335 case VFMADDSUB231PHZ256m:
12336 case VFMADDSUB231PHZ256mb:
12337 case VFMADDSUB231PHZ256mbk:
12338 case VFMADDSUB231PHZ256mbkz:
12339 case VFMADDSUB231PHZ256mk:
12340 case VFMADDSUB231PHZ256mkz:
12341 case VFMADDSUB231PHZ256r:
12342 case VFMADDSUB231PHZ256rk:
12343 case VFMADDSUB231PHZ256rkz:
12344 case VFMADDSUB231PHZm:
12345 case VFMADDSUB231PHZmb:
12346 case VFMADDSUB231PHZmbk:
12347 case VFMADDSUB231PHZmbkz:
12348 case VFMADDSUB231PHZmk:
12349 case VFMADDSUB231PHZmkz:
12350 case VFMADDSUB231PHZr:
12351 case VFMADDSUB231PHZrb:
12352 case VFMADDSUB231PHZrbk:
12353 case VFMADDSUB231PHZrbkz:
12354 case VFMADDSUB231PHZrk:
12355 case VFMADDSUB231PHZrkz:
12356 return true;
12357 }
12358 return false;
12359}
12360
12361bool isTDCALL(unsigned Opcode) {
12362 return Opcode == TDCALL;
12363}
12364
12365bool isPVALIDATE(unsigned Opcode) {
12366 switch (Opcode) {
12367 case PVALIDATE32:
12368 case PVALIDATE64:
12369 return true;
12370 }
12371 return false;
12372}
12373
12374bool isVPSHUFLW(unsigned Opcode) {
12375 switch (Opcode) {
12376 case VPSHUFLWYmi:
12377 case VPSHUFLWYri:
12378 case VPSHUFLWZ128mi:
12379 case VPSHUFLWZ128mik:
12380 case VPSHUFLWZ128mikz:
12381 case VPSHUFLWZ128ri:
12382 case VPSHUFLWZ128rik:
12383 case VPSHUFLWZ128rikz:
12384 case VPSHUFLWZ256mi:
12385 case VPSHUFLWZ256mik:
12386 case VPSHUFLWZ256mikz:
12387 case VPSHUFLWZ256ri:
12388 case VPSHUFLWZ256rik:
12389 case VPSHUFLWZ256rikz:
12390 case VPSHUFLWZmi:
12391 case VPSHUFLWZmik:
12392 case VPSHUFLWZmikz:
12393 case VPSHUFLWZri:
12394 case VPSHUFLWZrik:
12395 case VPSHUFLWZrikz:
12396 case VPSHUFLWmi:
12397 case VPSHUFLWri:
12398 return true;
12399 }
12400 return false;
12401}
12402
12403bool isPCLMULQDQ(unsigned Opcode) {
12404 switch (Opcode) {
12405 case PCLMULQDQrmi:
12406 case PCLMULQDQrri:
12407 return true;
12408 }
12409 return false;
12410}
12411
12412bool isCMPXCHG8B(unsigned Opcode) {
12413 return Opcode == CMPXCHG8B;
12414}
12415
12416bool isVPMOVM2B(unsigned Opcode) {
12417 switch (Opcode) {
12418 case VPMOVM2BZ128rk:
12419 case VPMOVM2BZ256rk:
12420 case VPMOVM2BZrk:
12421 return true;
12422 }
12423 return false;
12424}
12425
12426bool isVCVTUDQ2PH(unsigned Opcode) {
12427 switch (Opcode) {
12428 case VCVTUDQ2PHZ128rm:
12429 case VCVTUDQ2PHZ128rmb:
12430 case VCVTUDQ2PHZ128rmbk:
12431 case VCVTUDQ2PHZ128rmbkz:
12432 case VCVTUDQ2PHZ128rmk:
12433 case VCVTUDQ2PHZ128rmkz:
12434 case VCVTUDQ2PHZ128rr:
12435 case VCVTUDQ2PHZ128rrk:
12436 case VCVTUDQ2PHZ128rrkz:
12437 case VCVTUDQ2PHZ256rm:
12438 case VCVTUDQ2PHZ256rmb:
12439 case VCVTUDQ2PHZ256rmbk:
12440 case VCVTUDQ2PHZ256rmbkz:
12441 case VCVTUDQ2PHZ256rmk:
12442 case VCVTUDQ2PHZ256rmkz:
12443 case VCVTUDQ2PHZ256rr:
12444 case VCVTUDQ2PHZ256rrk:
12445 case VCVTUDQ2PHZ256rrkz:
12446 case VCVTUDQ2PHZrm:
12447 case VCVTUDQ2PHZrmb:
12448 case VCVTUDQ2PHZrmbk:
12449 case VCVTUDQ2PHZrmbkz:
12450 case VCVTUDQ2PHZrmk:
12451 case VCVTUDQ2PHZrmkz:
12452 case VCVTUDQ2PHZrr:
12453 case VCVTUDQ2PHZrrb:
12454 case VCVTUDQ2PHZrrbk:
12455 case VCVTUDQ2PHZrrbkz:
12456 case VCVTUDQ2PHZrrk:
12457 case VCVTUDQ2PHZrrkz:
12458 return true;
12459 }
12460 return false;
12461}
12462
12463bool isPEXTRQ(unsigned Opcode) {
12464 switch (Opcode) {
12465 case PEXTRQmri:
12466 case PEXTRQrri:
12467 return true;
12468 }
12469 return false;
12470}
12471
12472bool isXCRYPTCTR(unsigned Opcode) {
12473 return Opcode == XCRYPTCTR;
12474}
12475
12476bool isVREDUCEPH(unsigned Opcode) {
12477 switch (Opcode) {
12478 case VREDUCEPHZ128rmbi:
12479 case VREDUCEPHZ128rmbik:
12480 case VREDUCEPHZ128rmbikz:
12481 case VREDUCEPHZ128rmi:
12482 case VREDUCEPHZ128rmik:
12483 case VREDUCEPHZ128rmikz:
12484 case VREDUCEPHZ128rri:
12485 case VREDUCEPHZ128rrik:
12486 case VREDUCEPHZ128rrikz:
12487 case VREDUCEPHZ256rmbi:
12488 case VREDUCEPHZ256rmbik:
12489 case VREDUCEPHZ256rmbikz:
12490 case VREDUCEPHZ256rmi:
12491 case VREDUCEPHZ256rmik:
12492 case VREDUCEPHZ256rmikz:
12493 case VREDUCEPHZ256rri:
12494 case VREDUCEPHZ256rrik:
12495 case VREDUCEPHZ256rrikz:
12496 case VREDUCEPHZrmbi:
12497 case VREDUCEPHZrmbik:
12498 case VREDUCEPHZrmbikz:
12499 case VREDUCEPHZrmi:
12500 case VREDUCEPHZrmik:
12501 case VREDUCEPHZrmikz:
12502 case VREDUCEPHZrri:
12503 case VREDUCEPHZrrib:
12504 case VREDUCEPHZrribk:
12505 case VREDUCEPHZrribkz:
12506 case VREDUCEPHZrrik:
12507 case VREDUCEPHZrrikz:
12508 return true;
12509 }
12510 return false;
12511}
12512
12513bool isUCOMISD(unsigned Opcode) {
12514 switch (Opcode) {
12515 case UCOMISDrm:
12516 case UCOMISDrr:
12517 return true;
12518 }
12519 return false;
12520}
12521
12522bool isOUTSD(unsigned Opcode) {
12523 return Opcode == OUTSL;
12524}
12525
12526bool isSUBSS(unsigned Opcode) {
12527 switch (Opcode) {
12528 case SUBSSrm_Int:
12529 case SUBSSrr_Int:
12530 return true;
12531 }
12532 return false;
12533}
12534
12535bool isVFMSUBPS(unsigned Opcode) {
12536 switch (Opcode) {
12537 case VFMSUBPS4Ymr:
12538 case VFMSUBPS4Yrm:
12539 case VFMSUBPS4Yrr:
12540 case VFMSUBPS4Yrr_REV:
12541 case VFMSUBPS4mr:
12542 case VFMSUBPS4rm:
12543 case VFMSUBPS4rr:
12544 case VFMSUBPS4rr_REV:
12545 return true;
12546 }
12547 return false;
12548}
12549
12550bool isVPBLENDW(unsigned Opcode) {
12551 switch (Opcode) {
12552 case VPBLENDWYrmi:
12553 case VPBLENDWYrri:
12554 case VPBLENDWrmi:
12555 case VPBLENDWrri:
12556 return true;
12557 }
12558 return false;
12559}
12560
12561bool isVPEXPANDB(unsigned Opcode) {
12562 switch (Opcode) {
12563 case VPEXPANDBZ128rm:
12564 case VPEXPANDBZ128rmk:
12565 case VPEXPANDBZ128rmkz:
12566 case VPEXPANDBZ128rr:
12567 case VPEXPANDBZ128rrk:
12568 case VPEXPANDBZ128rrkz:
12569 case VPEXPANDBZ256rm:
12570 case VPEXPANDBZ256rmk:
12571 case VPEXPANDBZ256rmkz:
12572 case VPEXPANDBZ256rr:
12573 case VPEXPANDBZ256rrk:
12574 case VPEXPANDBZ256rrkz:
12575 case VPEXPANDBZrm:
12576 case VPEXPANDBZrmk:
12577 case VPEXPANDBZrmkz:
12578 case VPEXPANDBZrr:
12579 case VPEXPANDBZrrk:
12580 case VPEXPANDBZrrkz:
12581 return true;
12582 }
12583 return false;
12584}
12585
12586bool isBZHI(unsigned Opcode) {
12587 switch (Opcode) {
12588 case BZHI32rm:
12589 case BZHI32rm_EVEX:
12590 case BZHI32rm_NF:
12591 case BZHI32rr:
12592 case BZHI32rr_EVEX:
12593 case BZHI32rr_NF:
12594 case BZHI64rm:
12595 case BZHI64rm_EVEX:
12596 case BZHI64rm_NF:
12597 case BZHI64rr:
12598 case BZHI64rr_EVEX:
12599 case BZHI64rr_NF:
12600 return true;
12601 }
12602 return false;
12603}
12604
12605bool isVPRORVD(unsigned Opcode) {
12606 switch (Opcode) {
12607 case VPRORVDZ128rm:
12608 case VPRORVDZ128rmb:
12609 case VPRORVDZ128rmbk:
12610 case VPRORVDZ128rmbkz:
12611 case VPRORVDZ128rmk:
12612 case VPRORVDZ128rmkz:
12613 case VPRORVDZ128rr:
12614 case VPRORVDZ128rrk:
12615 case VPRORVDZ128rrkz:
12616 case VPRORVDZ256rm:
12617 case VPRORVDZ256rmb:
12618 case VPRORVDZ256rmbk:
12619 case VPRORVDZ256rmbkz:
12620 case VPRORVDZ256rmk:
12621 case VPRORVDZ256rmkz:
12622 case VPRORVDZ256rr:
12623 case VPRORVDZ256rrk:
12624 case VPRORVDZ256rrkz:
12625 case VPRORVDZrm:
12626 case VPRORVDZrmb:
12627 case VPRORVDZrmbk:
12628 case VPRORVDZrmbkz:
12629 case VPRORVDZrmk:
12630 case VPRORVDZrmkz:
12631 case VPRORVDZrr:
12632 case VPRORVDZrrk:
12633 case VPRORVDZrrkz:
12634 return true;
12635 }
12636 return false;
12637}
12638
12639bool isRMPQUERY(unsigned Opcode) {
12640 return Opcode == RMPQUERY;
12641}
12642
12643bool isVPSCATTERDQ(unsigned Opcode) {
12644 switch (Opcode) {
12645 case VPSCATTERDQZ128mr:
12646 case VPSCATTERDQZ256mr:
12647 case VPSCATTERDQZmr:
12648 return true;
12649 }
12650 return false;
12651}
12652
12653bool isPSMASH(unsigned Opcode) {
12654 return Opcode == PSMASH;
12655}
12656
12657bool isVPSHLDQ(unsigned Opcode) {
12658 switch (Opcode) {
12659 case VPSHLDQZ128rmbi:
12660 case VPSHLDQZ128rmbik:
12661 case VPSHLDQZ128rmbikz:
12662 case VPSHLDQZ128rmi:
12663 case VPSHLDQZ128rmik:
12664 case VPSHLDQZ128rmikz:
12665 case VPSHLDQZ128rri:
12666 case VPSHLDQZ128rrik:
12667 case VPSHLDQZ128rrikz:
12668 case VPSHLDQZ256rmbi:
12669 case VPSHLDQZ256rmbik:
12670 case VPSHLDQZ256rmbikz:
12671 case VPSHLDQZ256rmi:
12672 case VPSHLDQZ256rmik:
12673 case VPSHLDQZ256rmikz:
12674 case VPSHLDQZ256rri:
12675 case VPSHLDQZ256rrik:
12676 case VPSHLDQZ256rrikz:
12677 case VPSHLDQZrmbi:
12678 case VPSHLDQZrmbik:
12679 case VPSHLDQZrmbikz:
12680 case VPSHLDQZrmi:
12681 case VPSHLDQZrmik:
12682 case VPSHLDQZrmikz:
12683 case VPSHLDQZrri:
12684 case VPSHLDQZrrik:
12685 case VPSHLDQZrrikz:
12686 return true;
12687 }
12688 return false;
12689}
12690
12691bool isVSCATTERPF1DPD(unsigned Opcode) {
12692 return Opcode == VSCATTERPF1DPDm;
12693}
12694
12695bool isMONTMUL(unsigned Opcode) {
12696 return Opcode == MONTMUL;
12697}
12698
12699bool isVCVTPH2UQQ(unsigned Opcode) {
12700 switch (Opcode) {
12701 case VCVTPH2UQQZ128rm:
12702 case VCVTPH2UQQZ128rmb:
12703 case VCVTPH2UQQZ128rmbk:
12704 case VCVTPH2UQQZ128rmbkz:
12705 case VCVTPH2UQQZ128rmk:
12706 case VCVTPH2UQQZ128rmkz:
12707 case VCVTPH2UQQZ128rr:
12708 case VCVTPH2UQQZ128rrk:
12709 case VCVTPH2UQQZ128rrkz:
12710 case VCVTPH2UQQZ256rm:
12711 case VCVTPH2UQQZ256rmb:
12712 case VCVTPH2UQQZ256rmbk:
12713 case VCVTPH2UQQZ256rmbkz:
12714 case VCVTPH2UQQZ256rmk:
12715 case VCVTPH2UQQZ256rmkz:
12716 case VCVTPH2UQQZ256rr:
12717 case VCVTPH2UQQZ256rrk:
12718 case VCVTPH2UQQZ256rrkz:
12719 case VCVTPH2UQQZrm:
12720 case VCVTPH2UQQZrmb:
12721 case VCVTPH2UQQZrmbk:
12722 case VCVTPH2UQQZrmbkz:
12723 case VCVTPH2UQQZrmk:
12724 case VCVTPH2UQQZrmkz:
12725 case VCVTPH2UQQZrr:
12726 case VCVTPH2UQQZrrb:
12727 case VCVTPH2UQQZrrbk:
12728 case VCVTPH2UQQZrrbkz:
12729 case VCVTPH2UQQZrrk:
12730 case VCVTPH2UQQZrrkz:
12731 return true;
12732 }
12733 return false;
12734}
12735
12736bool isPSLLD(unsigned Opcode) {
12737 switch (Opcode) {
12738 case MMX_PSLLDri:
12739 case MMX_PSLLDrm:
12740 case MMX_PSLLDrr:
12741 case PSLLDri:
12742 case PSLLDrm:
12743 case PSLLDrr:
12744 return true;
12745 }
12746 return false;
12747}
12748
12749bool isSAR(unsigned Opcode) {
12750 switch (Opcode) {
12751 case SAR16m1:
12752 case SAR16m1_EVEX:
12753 case SAR16m1_ND:
12754 case SAR16m1_NF:
12755 case SAR16m1_NF_ND:
12756 case SAR16mCL:
12757 case SAR16mCL_EVEX:
12758 case SAR16mCL_ND:
12759 case SAR16mCL_NF:
12760 case SAR16mCL_NF_ND:
12761 case SAR16mi:
12762 case SAR16mi_EVEX:
12763 case SAR16mi_ND:
12764 case SAR16mi_NF:
12765 case SAR16mi_NF_ND:
12766 case SAR16r1:
12767 case SAR16r1_EVEX:
12768 case SAR16r1_ND:
12769 case SAR16r1_NF:
12770 case SAR16r1_NF_ND:
12771 case SAR16rCL:
12772 case SAR16rCL_EVEX:
12773 case SAR16rCL_ND:
12774 case SAR16rCL_NF:
12775 case SAR16rCL_NF_ND:
12776 case SAR16ri:
12777 case SAR16ri_EVEX:
12778 case SAR16ri_ND:
12779 case SAR16ri_NF:
12780 case SAR16ri_NF_ND:
12781 case SAR32m1:
12782 case SAR32m1_EVEX:
12783 case SAR32m1_ND:
12784 case SAR32m1_NF:
12785 case SAR32m1_NF_ND:
12786 case SAR32mCL:
12787 case SAR32mCL_EVEX:
12788 case SAR32mCL_ND:
12789 case SAR32mCL_NF:
12790 case SAR32mCL_NF_ND:
12791 case SAR32mi:
12792 case SAR32mi_EVEX:
12793 case SAR32mi_ND:
12794 case SAR32mi_NF:
12795 case SAR32mi_NF_ND:
12796 case SAR32r1:
12797 case SAR32r1_EVEX:
12798 case SAR32r1_ND:
12799 case SAR32r1_NF:
12800 case SAR32r1_NF_ND:
12801 case SAR32rCL:
12802 case SAR32rCL_EVEX:
12803 case SAR32rCL_ND:
12804 case SAR32rCL_NF:
12805 case SAR32rCL_NF_ND:
12806 case SAR32ri:
12807 case SAR32ri_EVEX:
12808 case SAR32ri_ND:
12809 case SAR32ri_NF:
12810 case SAR32ri_NF_ND:
12811 case SAR64m1:
12812 case SAR64m1_EVEX:
12813 case SAR64m1_ND:
12814 case SAR64m1_NF:
12815 case SAR64m1_NF_ND:
12816 case SAR64mCL:
12817 case SAR64mCL_EVEX:
12818 case SAR64mCL_ND:
12819 case SAR64mCL_NF:
12820 case SAR64mCL_NF_ND:
12821 case SAR64mi:
12822 case SAR64mi_EVEX:
12823 case SAR64mi_ND:
12824 case SAR64mi_NF:
12825 case SAR64mi_NF_ND:
12826 case SAR64r1:
12827 case SAR64r1_EVEX:
12828 case SAR64r1_ND:
12829 case SAR64r1_NF:
12830 case SAR64r1_NF_ND:
12831 case SAR64rCL:
12832 case SAR64rCL_EVEX:
12833 case SAR64rCL_ND:
12834 case SAR64rCL_NF:
12835 case SAR64rCL_NF_ND:
12836 case SAR64ri:
12837 case SAR64ri_EVEX:
12838 case SAR64ri_ND:
12839 case SAR64ri_NF:
12840 case SAR64ri_NF_ND:
12841 case SAR8m1:
12842 case SAR8m1_EVEX:
12843 case SAR8m1_ND:
12844 case SAR8m1_NF:
12845 case SAR8m1_NF_ND:
12846 case SAR8mCL:
12847 case SAR8mCL_EVEX:
12848 case SAR8mCL_ND:
12849 case SAR8mCL_NF:
12850 case SAR8mCL_NF_ND:
12851 case SAR8mi:
12852 case SAR8mi_EVEX:
12853 case SAR8mi_ND:
12854 case SAR8mi_NF:
12855 case SAR8mi_NF_ND:
12856 case SAR8r1:
12857 case SAR8r1_EVEX:
12858 case SAR8r1_ND:
12859 case SAR8r1_NF:
12860 case SAR8r1_NF_ND:
12861 case SAR8rCL:
12862 case SAR8rCL_EVEX:
12863 case SAR8rCL_ND:
12864 case SAR8rCL_NF:
12865 case SAR8rCL_NF_ND:
12866 case SAR8ri:
12867 case SAR8ri_EVEX:
12868 case SAR8ri_ND:
12869 case SAR8ri_NF:
12870 case SAR8ri_NF_ND:
12871 return true;
12872 }
12873 return false;
12874}
12875
12876bool isLDTILECFG(unsigned Opcode) {
12877 switch (Opcode) {
12878 case LDTILECFG:
12879 case LDTILECFG_EVEX:
12880 return true;
12881 }
12882 return false;
12883}
12884
12885bool isPMINUB(unsigned Opcode) {
12886 switch (Opcode) {
12887 case MMX_PMINUBrm:
12888 case MMX_PMINUBrr:
12889 case PMINUBrm:
12890 case PMINUBrr:
12891 return true;
12892 }
12893 return false;
12894}
12895
12896bool isVCVTNEEBF162PS(unsigned Opcode) {
12897 switch (Opcode) {
12898 case VCVTNEEBF162PSYrm:
12899 case VCVTNEEBF162PSrm:
12900 return true;
12901 }
12902 return false;
12903}
12904
12905bool isMOVDIR64B(unsigned Opcode) {
12906 switch (Opcode) {
12907 case MOVDIR64B16:
12908 case MOVDIR64B32:
12909 case MOVDIR64B32_EVEX:
12910 case MOVDIR64B64:
12911 case MOVDIR64B64_EVEX:
12912 return true;
12913 }
12914 return false;
12915}
12916
12917bool isSQRTPS(unsigned Opcode) {
12918 switch (Opcode) {
12919 case SQRTPSm:
12920 case SQRTPSr:
12921 return true;
12922 }
12923 return false;
12924}
12925
12926bool isSTR(unsigned Opcode) {
12927 switch (Opcode) {
12928 case STR16r:
12929 case STR32r:
12930 case STR64r:
12931 case STRm:
12932 return true;
12933 }
12934 return false;
12935}
12936
12937bool isKANDNQ(unsigned Opcode) {
12938 return Opcode == KANDNQkk;
12939}
12940
12941bool isBSF(unsigned Opcode) {
12942 switch (Opcode) {
12943 case BSF16rm:
12944 case BSF16rr:
12945 case BSF32rm:
12946 case BSF32rr:
12947 case BSF64rm:
12948 case BSF64rr:
12949 return true;
12950 }
12951 return false;
12952}
12953
12954bool isINCSSPD(unsigned Opcode) {
12955 return Opcode == INCSSPD;
12956}
12957
12958bool isVPDPBUUDS(unsigned Opcode) {
12959 switch (Opcode) {
12960 case VPDPBUUDSYrm:
12961 case VPDPBUUDSYrr:
12962 case VPDPBUUDSZ128rm:
12963 case VPDPBUUDSZ128rmb:
12964 case VPDPBUUDSZ128rmbk:
12965 case VPDPBUUDSZ128rmbkz:
12966 case VPDPBUUDSZ128rmk:
12967 case VPDPBUUDSZ128rmkz:
12968 case VPDPBUUDSZ128rr:
12969 case VPDPBUUDSZ128rrk:
12970 case VPDPBUUDSZ128rrkz:
12971 case VPDPBUUDSZ256rm:
12972 case VPDPBUUDSZ256rmb:
12973 case VPDPBUUDSZ256rmbk:
12974 case VPDPBUUDSZ256rmbkz:
12975 case VPDPBUUDSZ256rmk:
12976 case VPDPBUUDSZ256rmkz:
12977 case VPDPBUUDSZ256rr:
12978 case VPDPBUUDSZ256rrk:
12979 case VPDPBUUDSZ256rrkz:
12980 case VPDPBUUDSZrm:
12981 case VPDPBUUDSZrmb:
12982 case VPDPBUUDSZrmbk:
12983 case VPDPBUUDSZrmbkz:
12984 case VPDPBUUDSZrmk:
12985 case VPDPBUUDSZrmkz:
12986 case VPDPBUUDSZrr:
12987 case VPDPBUUDSZrrk:
12988 case VPDPBUUDSZrrkz:
12989 case VPDPBUUDSrm:
12990 case VPDPBUUDSrr:
12991 return true;
12992 }
12993 return false;
12994}
12995
12996bool isCMPXCHG(unsigned Opcode) {
12997 switch (Opcode) {
12998 case CMPXCHG16rm:
12999 case CMPXCHG16rr:
13000 case CMPXCHG32rm:
13001 case CMPXCHG32rr:
13002 case CMPXCHG64rm:
13003 case CMPXCHG64rr:
13004 case CMPXCHG8rm:
13005 case CMPXCHG8rr:
13006 return true;
13007 }
13008 return false;
13009}
13010
13011bool isVPSIGNW(unsigned Opcode) {
13012 switch (Opcode) {
13013 case VPSIGNWYrm:
13014 case VPSIGNWYrr:
13015 case VPSIGNWrm:
13016 case VPSIGNWrr:
13017 return true;
13018 }
13019 return false;
13020}
13021
13022bool isVCOMISBF16(unsigned Opcode) {
13023 switch (Opcode) {
13024 case VCOMISBF16Zrm:
13025 case VCOMISBF16Zrr:
13026 return true;
13027 }
13028 return false;
13029}
13030
13031bool isLES(unsigned Opcode) {
13032 switch (Opcode) {
13033 case LES16rm:
13034 case LES32rm:
13035 return true;
13036 }
13037 return false;
13038}
13039
13040bool isCVTSS2SI(unsigned Opcode) {
13041 switch (Opcode) {
13042 case CVTSS2SI64rm_Int:
13043 case CVTSS2SI64rr_Int:
13044 case CVTSS2SIrm_Int:
13045 case CVTSS2SIrr_Int:
13046 return true;
13047 }
13048 return false;
13049}
13050
13051bool isPFACC(unsigned Opcode) {
13052 switch (Opcode) {
13053 case PFACCrm:
13054 case PFACCrr:
13055 return true;
13056 }
13057 return false;
13058}
13059
13060bool isFCOMPI(unsigned Opcode) {
13061 return Opcode == COM_FIPr;
13062}
13063
13064bool isPUNPCKHWD(unsigned Opcode) {
13065 switch (Opcode) {
13066 case MMX_PUNPCKHWDrm:
13067 case MMX_PUNPCKHWDrr:
13068 case PUNPCKHWDrm:
13069 case PUNPCKHWDrr:
13070 return true;
13071 }
13072 return false;
13073}
13074
13075bool isVPMOVUSWB(unsigned Opcode) {
13076 switch (Opcode) {
13077 case VPMOVUSWBZ128mr:
13078 case VPMOVUSWBZ128mrk:
13079 case VPMOVUSWBZ128rr:
13080 case VPMOVUSWBZ128rrk:
13081 case VPMOVUSWBZ128rrkz:
13082 case VPMOVUSWBZ256mr:
13083 case VPMOVUSWBZ256mrk:
13084 case VPMOVUSWBZ256rr:
13085 case VPMOVUSWBZ256rrk:
13086 case VPMOVUSWBZ256rrkz:
13087 case VPMOVUSWBZmr:
13088 case VPMOVUSWBZmrk:
13089 case VPMOVUSWBZrr:
13090 case VPMOVUSWBZrrk:
13091 case VPMOVUSWBZrrkz:
13092 return true;
13093 }
13094 return false;
13095}
13096
13097bool isVPTESTNMW(unsigned Opcode) {
13098 switch (Opcode) {
13099 case VPTESTNMWZ128rm:
13100 case VPTESTNMWZ128rmk:
13101 case VPTESTNMWZ128rr:
13102 case VPTESTNMWZ128rrk:
13103 case VPTESTNMWZ256rm:
13104 case VPTESTNMWZ256rmk:
13105 case VPTESTNMWZ256rr:
13106 case VPTESTNMWZ256rrk:
13107 case VPTESTNMWZrm:
13108 case VPTESTNMWZrmk:
13109 case VPTESTNMWZrr:
13110 case VPTESTNMWZrrk:
13111 return true;
13112 }
13113 return false;
13114}
13115
13116bool isVPMULDQ(unsigned Opcode) {
13117 switch (Opcode) {
13118 case VPMULDQYrm:
13119 case VPMULDQYrr:
13120 case VPMULDQZ128rm:
13121 case VPMULDQZ128rmb:
13122 case VPMULDQZ128rmbk:
13123 case VPMULDQZ128rmbkz:
13124 case VPMULDQZ128rmk:
13125 case VPMULDQZ128rmkz:
13126 case VPMULDQZ128rr:
13127 case VPMULDQZ128rrk:
13128 case VPMULDQZ128rrkz:
13129 case VPMULDQZ256rm:
13130 case VPMULDQZ256rmb:
13131 case VPMULDQZ256rmbk:
13132 case VPMULDQZ256rmbkz:
13133 case VPMULDQZ256rmk:
13134 case VPMULDQZ256rmkz:
13135 case VPMULDQZ256rr:
13136 case VPMULDQZ256rrk:
13137 case VPMULDQZ256rrkz:
13138 case VPMULDQZrm:
13139 case VPMULDQZrmb:
13140 case VPMULDQZrmbk:
13141 case VPMULDQZrmbkz:
13142 case VPMULDQZrmk:
13143 case VPMULDQZrmkz:
13144 case VPMULDQZrr:
13145 case VPMULDQZrrk:
13146 case VPMULDQZrrkz:
13147 case VPMULDQrm:
13148 case VPMULDQrr:
13149 return true;
13150 }
13151 return false;
13152}
13153
13154bool isSHRX(unsigned Opcode) {
13155 switch (Opcode) {
13156 case SHRX32rm:
13157 case SHRX32rm_EVEX:
13158 case SHRX32rr:
13159 case SHRX32rr_EVEX:
13160 case SHRX64rm:
13161 case SHRX64rm_EVEX:
13162 case SHRX64rr:
13163 case SHRX64rr_EVEX:
13164 return true;
13165 }
13166 return false;
13167}
13168
13169bool isKXORQ(unsigned Opcode) {
13170 return Opcode == KXORQkk;
13171}
13172
13173bool isVGETEXPSD(unsigned Opcode) {
13174 switch (Opcode) {
13175 case VGETEXPSDZm:
13176 case VGETEXPSDZmk:
13177 case VGETEXPSDZmkz:
13178 case VGETEXPSDZr:
13179 case VGETEXPSDZrb:
13180 case VGETEXPSDZrbk:
13181 case VGETEXPSDZrbkz:
13182 case VGETEXPSDZrk:
13183 case VGETEXPSDZrkz:
13184 return true;
13185 }
13186 return false;
13187}
13188
13189bool isV4FNMADDPS(unsigned Opcode) {
13190 switch (Opcode) {
13191 case V4FNMADDPSrm:
13192 case V4FNMADDPSrmk:
13193 case V4FNMADDPSrmkz:
13194 return true;
13195 }
13196 return false;
13197}
13198
13199bool isVFNMSUB231SD(unsigned Opcode) {
13200 switch (Opcode) {
13201 case VFNMSUB231SDZm_Int:
13202 case VFNMSUB231SDZmk_Int:
13203 case VFNMSUB231SDZmkz_Int:
13204 case VFNMSUB231SDZr_Int:
13205 case VFNMSUB231SDZrb_Int:
13206 case VFNMSUB231SDZrbk_Int:
13207 case VFNMSUB231SDZrbkz_Int:
13208 case VFNMSUB231SDZrk_Int:
13209 case VFNMSUB231SDZrkz_Int:
13210 case VFNMSUB231SDm_Int:
13211 case VFNMSUB231SDr_Int:
13212 return true;
13213 }
13214 return false;
13215}
13216
13217bool isVPSHLD(unsigned Opcode) {
13218 switch (Opcode) {
13219 case VPSHLDmr:
13220 case VPSHLDrm:
13221 case VPSHLDrr:
13222 case VPSHLDrr_REV:
13223 return true;
13224 }
13225 return false;
13226}
13227
13228bool isPAVGB(unsigned Opcode) {
13229 switch (Opcode) {
13230 case MMX_PAVGBrm:
13231 case MMX_PAVGBrr:
13232 case PAVGBrm:
13233 case PAVGBrr:
13234 return true;
13235 }
13236 return false;
13237}
13238
13239bool isPMOVZXBD(unsigned Opcode) {
13240 switch (Opcode) {
13241 case PMOVZXBDrm:
13242 case PMOVZXBDrr:
13243 return true;
13244 }
13245 return false;
13246}
13247
13248bool isKORTESTW(unsigned Opcode) {
13249 return Opcode == KORTESTWkk;
13250}
13251
13252bool isVSHUFPS(unsigned Opcode) {
13253 switch (Opcode) {
13254 case VSHUFPSYrmi:
13255 case VSHUFPSYrri:
13256 case VSHUFPSZ128rmbi:
13257 case VSHUFPSZ128rmbik:
13258 case VSHUFPSZ128rmbikz:
13259 case VSHUFPSZ128rmi:
13260 case VSHUFPSZ128rmik:
13261 case VSHUFPSZ128rmikz:
13262 case VSHUFPSZ128rri:
13263 case VSHUFPSZ128rrik:
13264 case VSHUFPSZ128rrikz:
13265 case VSHUFPSZ256rmbi:
13266 case VSHUFPSZ256rmbik:
13267 case VSHUFPSZ256rmbikz:
13268 case VSHUFPSZ256rmi:
13269 case VSHUFPSZ256rmik:
13270 case VSHUFPSZ256rmikz:
13271 case VSHUFPSZ256rri:
13272 case VSHUFPSZ256rrik:
13273 case VSHUFPSZ256rrikz:
13274 case VSHUFPSZrmbi:
13275 case VSHUFPSZrmbik:
13276 case VSHUFPSZrmbikz:
13277 case VSHUFPSZrmi:
13278 case VSHUFPSZrmik:
13279 case VSHUFPSZrmikz:
13280 case VSHUFPSZrri:
13281 case VSHUFPSZrrik:
13282 case VSHUFPSZrrikz:
13283 case VSHUFPSrmi:
13284 case VSHUFPSrri:
13285 return true;
13286 }
13287 return false;
13288}
13289
13290bool isVCVTHF82PS(unsigned Opcode) {
13291 switch (Opcode) {
13292 case VCVTHF82PSZ128rm:
13293 case VCVTHF82PSZ128rmk:
13294 case VCVTHF82PSZ128rmkz:
13295 case VCVTHF82PSZ128rr:
13296 case VCVTHF82PSZ128rrk:
13297 case VCVTHF82PSZ128rrkz:
13298 case VCVTHF82PSZ256rm:
13299 case VCVTHF82PSZ256rmk:
13300 case VCVTHF82PSZ256rmkz:
13301 case VCVTHF82PSZ256rr:
13302 case VCVTHF82PSZ256rrk:
13303 case VCVTHF82PSZ256rrkz:
13304 case VCVTHF82PSZrm:
13305 case VCVTHF82PSZrmk:
13306 case VCVTHF82PSZrmkz:
13307 case VCVTHF82PSZrr:
13308 case VCVTHF82PSZrrk:
13309 case VCVTHF82PSZrrkz:
13310 return true;
13311 }
13312 return false;
13313}
13314
13315bool isAESENCWIDE128KL(unsigned Opcode) {
13316 return Opcode == AESENCWIDE128KL;
13317}
13318
13319bool isVPXORD(unsigned Opcode) {
13320 switch (Opcode) {
13321 case VPXORDZ128rm:
13322 case VPXORDZ128rmb:
13323 case VPXORDZ128rmbk:
13324 case VPXORDZ128rmbkz:
13325 case VPXORDZ128rmk:
13326 case VPXORDZ128rmkz:
13327 case VPXORDZ128rr:
13328 case VPXORDZ128rrk:
13329 case VPXORDZ128rrkz:
13330 case VPXORDZ256rm:
13331 case VPXORDZ256rmb:
13332 case VPXORDZ256rmbk:
13333 case VPXORDZ256rmbkz:
13334 case VPXORDZ256rmk:
13335 case VPXORDZ256rmkz:
13336 case VPXORDZ256rr:
13337 case VPXORDZ256rrk:
13338 case VPXORDZ256rrkz:
13339 case VPXORDZrm:
13340 case VPXORDZrmb:
13341 case VPXORDZrmbk:
13342 case VPXORDZrmbkz:
13343 case VPXORDZrmk:
13344 case VPXORDZrmkz:
13345 case VPXORDZrr:
13346 case VPXORDZrrk:
13347 case VPXORDZrrkz:
13348 return true;
13349 }
13350 return false;
13351}
13352
13353bool isVPSHAW(unsigned Opcode) {
13354 switch (Opcode) {
13355 case VPSHAWmr:
13356 case VPSHAWrm:
13357 case VPSHAWrr:
13358 case VPSHAWrr_REV:
13359 return true;
13360 }
13361 return false;
13362}
13363
13364bool isVFMSUB132BF16(unsigned Opcode) {
13365 switch (Opcode) {
13366 case VFMSUB132BF16Z128m:
13367 case VFMSUB132BF16Z128mb:
13368 case VFMSUB132BF16Z128mbk:
13369 case VFMSUB132BF16Z128mbkz:
13370 case VFMSUB132BF16Z128mk:
13371 case VFMSUB132BF16Z128mkz:
13372 case VFMSUB132BF16Z128r:
13373 case VFMSUB132BF16Z128rk:
13374 case VFMSUB132BF16Z128rkz:
13375 case VFMSUB132BF16Z256m:
13376 case VFMSUB132BF16Z256mb:
13377 case VFMSUB132BF16Z256mbk:
13378 case VFMSUB132BF16Z256mbkz:
13379 case VFMSUB132BF16Z256mk:
13380 case VFMSUB132BF16Z256mkz:
13381 case VFMSUB132BF16Z256r:
13382 case VFMSUB132BF16Z256rk:
13383 case VFMSUB132BF16Z256rkz:
13384 case VFMSUB132BF16Zm:
13385 case VFMSUB132BF16Zmb:
13386 case VFMSUB132BF16Zmbk:
13387 case VFMSUB132BF16Zmbkz:
13388 case VFMSUB132BF16Zmk:
13389 case VFMSUB132BF16Zmkz:
13390 case VFMSUB132BF16Zr:
13391 case VFMSUB132BF16Zrk:
13392 case VFMSUB132BF16Zrkz:
13393 return true;
13394 }
13395 return false;
13396}
13397
13398bool isVPERMT2B(unsigned Opcode) {
13399 switch (Opcode) {
13400 case VPERMT2BZ128rm:
13401 case VPERMT2BZ128rmk:
13402 case VPERMT2BZ128rmkz:
13403 case VPERMT2BZ128rr:
13404 case VPERMT2BZ128rrk:
13405 case VPERMT2BZ128rrkz:
13406 case VPERMT2BZ256rm:
13407 case VPERMT2BZ256rmk:
13408 case VPERMT2BZ256rmkz:
13409 case VPERMT2BZ256rr:
13410 case VPERMT2BZ256rrk:
13411 case VPERMT2BZ256rrkz:
13412 case VPERMT2BZrm:
13413 case VPERMT2BZrmk:
13414 case VPERMT2BZrmkz:
13415 case VPERMT2BZrr:
13416 case VPERMT2BZrrk:
13417 case VPERMT2BZrrkz:
13418 return true;
13419 }
13420 return false;
13421}
13422
13423bool isVFMADD213PD(unsigned Opcode) {
13424 switch (Opcode) {
13425 case VFMADD213PDYm:
13426 case VFMADD213PDYr:
13427 case VFMADD213PDZ128m:
13428 case VFMADD213PDZ128mb:
13429 case VFMADD213PDZ128mbk:
13430 case VFMADD213PDZ128mbkz:
13431 case VFMADD213PDZ128mk:
13432 case VFMADD213PDZ128mkz:
13433 case VFMADD213PDZ128r:
13434 case VFMADD213PDZ128rk:
13435 case VFMADD213PDZ128rkz:
13436 case VFMADD213PDZ256m:
13437 case VFMADD213PDZ256mb:
13438 case VFMADD213PDZ256mbk:
13439 case VFMADD213PDZ256mbkz:
13440 case VFMADD213PDZ256mk:
13441 case VFMADD213PDZ256mkz:
13442 case VFMADD213PDZ256r:
13443 case VFMADD213PDZ256rk:
13444 case VFMADD213PDZ256rkz:
13445 case VFMADD213PDZm:
13446 case VFMADD213PDZmb:
13447 case VFMADD213PDZmbk:
13448 case VFMADD213PDZmbkz:
13449 case VFMADD213PDZmk:
13450 case VFMADD213PDZmkz:
13451 case VFMADD213PDZr:
13452 case VFMADD213PDZrb:
13453 case VFMADD213PDZrbk:
13454 case VFMADD213PDZrbkz:
13455 case VFMADD213PDZrk:
13456 case VFMADD213PDZrkz:
13457 case VFMADD213PDm:
13458 case VFMADD213PDr:
13459 return true;
13460 }
13461 return false;
13462}
13463
13464bool isVPGATHERQD(unsigned Opcode) {
13465 switch (Opcode) {
13466 case VPGATHERQDYrm:
13467 case VPGATHERQDZ128rm:
13468 case VPGATHERQDZ256rm:
13469 case VPGATHERQDZrm:
13470 case VPGATHERQDrm:
13471 return true;
13472 }
13473 return false;
13474}
13475
13476bool isVFNMSUB213BF16(unsigned Opcode) {
13477 switch (Opcode) {
13478 case VFNMSUB213BF16Z128m:
13479 case VFNMSUB213BF16Z128mb:
13480 case VFNMSUB213BF16Z128mbk:
13481 case VFNMSUB213BF16Z128mbkz:
13482 case VFNMSUB213BF16Z128mk:
13483 case VFNMSUB213BF16Z128mkz:
13484 case VFNMSUB213BF16Z128r:
13485 case VFNMSUB213BF16Z128rk:
13486 case VFNMSUB213BF16Z128rkz:
13487 case VFNMSUB213BF16Z256m:
13488 case VFNMSUB213BF16Z256mb:
13489 case VFNMSUB213BF16Z256mbk:
13490 case VFNMSUB213BF16Z256mbkz:
13491 case VFNMSUB213BF16Z256mk:
13492 case VFNMSUB213BF16Z256mkz:
13493 case VFNMSUB213BF16Z256r:
13494 case VFNMSUB213BF16Z256rk:
13495 case VFNMSUB213BF16Z256rkz:
13496 case VFNMSUB213BF16Zm:
13497 case VFNMSUB213BF16Zmb:
13498 case VFNMSUB213BF16Zmbk:
13499 case VFNMSUB213BF16Zmbkz:
13500 case VFNMSUB213BF16Zmk:
13501 case VFNMSUB213BF16Zmkz:
13502 case VFNMSUB213BF16Zr:
13503 case VFNMSUB213BF16Zrk:
13504 case VFNMSUB213BF16Zrkz:
13505 return true;
13506 }
13507 return false;
13508}
13509
13510bool isVCVTPS2IBS(unsigned Opcode) {
13511 switch (Opcode) {
13512 case VCVTPS2IBSZ128rm:
13513 case VCVTPS2IBSZ128rmb:
13514 case VCVTPS2IBSZ128rmbk:
13515 case VCVTPS2IBSZ128rmbkz:
13516 case VCVTPS2IBSZ128rmk:
13517 case VCVTPS2IBSZ128rmkz:
13518 case VCVTPS2IBSZ128rr:
13519 case VCVTPS2IBSZ128rrk:
13520 case VCVTPS2IBSZ128rrkz:
13521 case VCVTPS2IBSZ256rm:
13522 case VCVTPS2IBSZ256rmb:
13523 case VCVTPS2IBSZ256rmbk:
13524 case VCVTPS2IBSZ256rmbkz:
13525 case VCVTPS2IBSZ256rmk:
13526 case VCVTPS2IBSZ256rmkz:
13527 case VCVTPS2IBSZ256rr:
13528 case VCVTPS2IBSZ256rrk:
13529 case VCVTPS2IBSZ256rrkz:
13530 case VCVTPS2IBSZrm:
13531 case VCVTPS2IBSZrmb:
13532 case VCVTPS2IBSZrmbk:
13533 case VCVTPS2IBSZrmbkz:
13534 case VCVTPS2IBSZrmk:
13535 case VCVTPS2IBSZrmkz:
13536 case VCVTPS2IBSZrr:
13537 case VCVTPS2IBSZrrb:
13538 case VCVTPS2IBSZrrbk:
13539 case VCVTPS2IBSZrrbkz:
13540 case VCVTPS2IBSZrrk:
13541 case VCVTPS2IBSZrrkz:
13542 return true;
13543 }
13544 return false;
13545}
13546
13547bool isVPCMPGTW(unsigned Opcode) {
13548 switch (Opcode) {
13549 case VPCMPGTWYrm:
13550 case VPCMPGTWYrr:
13551 case VPCMPGTWZ128rm:
13552 case VPCMPGTWZ128rmk:
13553 case VPCMPGTWZ128rr:
13554 case VPCMPGTWZ128rrk:
13555 case VPCMPGTWZ256rm:
13556 case VPCMPGTWZ256rmk:
13557 case VPCMPGTWZ256rr:
13558 case VPCMPGTWZ256rrk:
13559 case VPCMPGTWZrm:
13560 case VPCMPGTWZrmk:
13561 case VPCMPGTWZrr:
13562 case VPCMPGTWZrrk:
13563 case VPCMPGTWrm:
13564 case VPCMPGTWrr:
13565 return true;
13566 }
13567 return false;
13568}
13569
13570bool isVMOVRSB(unsigned Opcode) {
13571 switch (Opcode) {
13572 case VMOVRSBZ128m:
13573 case VMOVRSBZ128mk:
13574 case VMOVRSBZ128mkz:
13575 case VMOVRSBZ256m:
13576 case VMOVRSBZ256mk:
13577 case VMOVRSBZ256mkz:
13578 case VMOVRSBZm:
13579 case VMOVRSBZmk:
13580 case VMOVRSBZmkz:
13581 return true;
13582 }
13583 return false;
13584}
13585
13586bool isVGETMANTSH(unsigned Opcode) {
13587 switch (Opcode) {
13588 case VGETMANTSHZrmi:
13589 case VGETMANTSHZrmik:
13590 case VGETMANTSHZrmikz:
13591 case VGETMANTSHZrri:
13592 case VGETMANTSHZrrib:
13593 case VGETMANTSHZrribk:
13594 case VGETMANTSHZrribkz:
13595 case VGETMANTSHZrrik:
13596 case VGETMANTSHZrrikz:
13597 return true;
13598 }
13599 return false;
13600}
13601
13602bool isVANDPS(unsigned Opcode) {
13603 switch (Opcode) {
13604 case VANDPSYrm:
13605 case VANDPSYrr:
13606 case VANDPSZ128rm:
13607 case VANDPSZ128rmb:
13608 case VANDPSZ128rmbk:
13609 case VANDPSZ128rmbkz:
13610 case VANDPSZ128rmk:
13611 case VANDPSZ128rmkz:
13612 case VANDPSZ128rr:
13613 case VANDPSZ128rrk:
13614 case VANDPSZ128rrkz:
13615 case VANDPSZ256rm:
13616 case VANDPSZ256rmb:
13617 case VANDPSZ256rmbk:
13618 case VANDPSZ256rmbkz:
13619 case VANDPSZ256rmk:
13620 case VANDPSZ256rmkz:
13621 case VANDPSZ256rr:
13622 case VANDPSZ256rrk:
13623 case VANDPSZ256rrkz:
13624 case VANDPSZrm:
13625 case VANDPSZrmb:
13626 case VANDPSZrmbk:
13627 case VANDPSZrmbkz:
13628 case VANDPSZrmk:
13629 case VANDPSZrmkz:
13630 case VANDPSZrr:
13631 case VANDPSZrrk:
13632 case VANDPSZrrkz:
13633 case VANDPSrm:
13634 case VANDPSrr:
13635 return true;
13636 }
13637 return false;
13638}
13639
13640bool isVDIVPS(unsigned Opcode) {
13641 switch (Opcode) {
13642 case VDIVPSYrm:
13643 case VDIVPSYrr:
13644 case VDIVPSZ128rm:
13645 case VDIVPSZ128rmb:
13646 case VDIVPSZ128rmbk:
13647 case VDIVPSZ128rmbkz:
13648 case VDIVPSZ128rmk:
13649 case VDIVPSZ128rmkz:
13650 case VDIVPSZ128rr:
13651 case VDIVPSZ128rrk:
13652 case VDIVPSZ128rrkz:
13653 case VDIVPSZ256rm:
13654 case VDIVPSZ256rmb:
13655 case VDIVPSZ256rmbk:
13656 case VDIVPSZ256rmbkz:
13657 case VDIVPSZ256rmk:
13658 case VDIVPSZ256rmkz:
13659 case VDIVPSZ256rr:
13660 case VDIVPSZ256rrk:
13661 case VDIVPSZ256rrkz:
13662 case VDIVPSZrm:
13663 case VDIVPSZrmb:
13664 case VDIVPSZrmbk:
13665 case VDIVPSZrmbkz:
13666 case VDIVPSZrmk:
13667 case VDIVPSZrmkz:
13668 case VDIVPSZrr:
13669 case VDIVPSZrrb:
13670 case VDIVPSZrrbk:
13671 case VDIVPSZrrbkz:
13672 case VDIVPSZrrk:
13673 case VDIVPSZrrkz:
13674 case VDIVPSrm:
13675 case VDIVPSrr:
13676 return true;
13677 }
13678 return false;
13679}
13680
13681bool isVANDNPS(unsigned Opcode) {
13682 switch (Opcode) {
13683 case VANDNPSYrm:
13684 case VANDNPSYrr:
13685 case VANDNPSZ128rm:
13686 case VANDNPSZ128rmb:
13687 case VANDNPSZ128rmbk:
13688 case VANDNPSZ128rmbkz:
13689 case VANDNPSZ128rmk:
13690 case VANDNPSZ128rmkz:
13691 case VANDNPSZ128rr:
13692 case VANDNPSZ128rrk:
13693 case VANDNPSZ128rrkz:
13694 case VANDNPSZ256rm:
13695 case VANDNPSZ256rmb:
13696 case VANDNPSZ256rmbk:
13697 case VANDNPSZ256rmbkz:
13698 case VANDNPSZ256rmk:
13699 case VANDNPSZ256rmkz:
13700 case VANDNPSZ256rr:
13701 case VANDNPSZ256rrk:
13702 case VANDNPSZ256rrkz:
13703 case VANDNPSZrm:
13704 case VANDNPSZrmb:
13705 case VANDNPSZrmbk:
13706 case VANDNPSZrmbkz:
13707 case VANDNPSZrmk:
13708 case VANDNPSZrmkz:
13709 case VANDNPSZrr:
13710 case VANDNPSZrrk:
13711 case VANDNPSZrrkz:
13712 case VANDNPSrm:
13713 case VANDNPSrr:
13714 return true;
13715 }
13716 return false;
13717}
13718
13719bool isVPBROADCASTW(unsigned Opcode) {
13720 switch (Opcode) {
13721 case VPBROADCASTWYrm:
13722 case VPBROADCASTWYrr:
13723 case VPBROADCASTWZ128rm:
13724 case VPBROADCASTWZ128rmk:
13725 case VPBROADCASTWZ128rmkz:
13726 case VPBROADCASTWZ128rr:
13727 case VPBROADCASTWZ128rrk:
13728 case VPBROADCASTWZ128rrkz:
13729 case VPBROADCASTWZ256rm:
13730 case VPBROADCASTWZ256rmk:
13731 case VPBROADCASTWZ256rmkz:
13732 case VPBROADCASTWZ256rr:
13733 case VPBROADCASTWZ256rrk:
13734 case VPBROADCASTWZ256rrkz:
13735 case VPBROADCASTWZrm:
13736 case VPBROADCASTWZrmk:
13737 case VPBROADCASTWZrmkz:
13738 case VPBROADCASTWZrr:
13739 case VPBROADCASTWZrrk:
13740 case VPBROADCASTWZrrkz:
13741 case VPBROADCASTWrZ128rr:
13742 case VPBROADCASTWrZ128rrk:
13743 case VPBROADCASTWrZ128rrkz:
13744 case VPBROADCASTWrZ256rr:
13745 case VPBROADCASTWrZ256rrk:
13746 case VPBROADCASTWrZ256rrkz:
13747 case VPBROADCASTWrZrr:
13748 case VPBROADCASTWrZrrk:
13749 case VPBROADCASTWrZrrkz:
13750 case VPBROADCASTWrm:
13751 case VPBROADCASTWrr:
13752 return true;
13753 }
13754 return false;
13755}
13756
13757bool isFLDL2T(unsigned Opcode) {
13758 return Opcode == FLDL2T;
13759}
13760
13761bool isVPERMB(unsigned Opcode) {
13762 switch (Opcode) {
13763 case VPERMBZ128rm:
13764 case VPERMBZ128rmk:
13765 case VPERMBZ128rmkz:
13766 case VPERMBZ128rr:
13767 case VPERMBZ128rrk:
13768 case VPERMBZ128rrkz:
13769 case VPERMBZ256rm:
13770 case VPERMBZ256rmk:
13771 case VPERMBZ256rmkz:
13772 case VPERMBZ256rr:
13773 case VPERMBZ256rrk:
13774 case VPERMBZ256rrkz:
13775 case VPERMBZrm:
13776 case VPERMBZrmk:
13777 case VPERMBZrmkz:
13778 case VPERMBZrr:
13779 case VPERMBZrrk:
13780 case VPERMBZrrkz:
13781 return true;
13782 }
13783 return false;
13784}
13785
13786bool isFCMOVNBE(unsigned Opcode) {
13787 return Opcode == CMOVNBE_F;
13788}
13789
13790bool isVCVTTPH2W(unsigned Opcode) {
13791 switch (Opcode) {
13792 case VCVTTPH2WZ128rm:
13793 case VCVTTPH2WZ128rmb:
13794 case VCVTTPH2WZ128rmbk:
13795 case VCVTTPH2WZ128rmbkz:
13796 case VCVTTPH2WZ128rmk:
13797 case VCVTTPH2WZ128rmkz:
13798 case VCVTTPH2WZ128rr:
13799 case VCVTTPH2WZ128rrk:
13800 case VCVTTPH2WZ128rrkz:
13801 case VCVTTPH2WZ256rm:
13802 case VCVTTPH2WZ256rmb:
13803 case VCVTTPH2WZ256rmbk:
13804 case VCVTTPH2WZ256rmbkz:
13805 case VCVTTPH2WZ256rmk:
13806 case VCVTTPH2WZ256rmkz:
13807 case VCVTTPH2WZ256rr:
13808 case VCVTTPH2WZ256rrk:
13809 case VCVTTPH2WZ256rrkz:
13810 case VCVTTPH2WZrm:
13811 case VCVTTPH2WZrmb:
13812 case VCVTTPH2WZrmbk:
13813 case VCVTTPH2WZrmbkz:
13814 case VCVTTPH2WZrmk:
13815 case VCVTTPH2WZrmkz:
13816 case VCVTTPH2WZrr:
13817 case VCVTTPH2WZrrb:
13818 case VCVTTPH2WZrrbk:
13819 case VCVTTPH2WZrrbkz:
13820 case VCVTTPH2WZrrk:
13821 case VCVTTPH2WZrrkz:
13822 return true;
13823 }
13824 return false;
13825}
13826
13827bool isPMOVZXBQ(unsigned Opcode) {
13828 switch (Opcode) {
13829 case PMOVZXBQrm:
13830 case PMOVZXBQrr:
13831 return true;
13832 }
13833 return false;
13834}
13835
13836bool isPF2ID(unsigned Opcode) {
13837 switch (Opcode) {
13838 case PF2IDrm:
13839 case PF2IDrr:
13840 return true;
13841 }
13842 return false;
13843}
13844
13845bool isVFNMADD132PD(unsigned Opcode) {
13846 switch (Opcode) {
13847 case VFNMADD132PDYm:
13848 case VFNMADD132PDYr:
13849 case VFNMADD132PDZ128m:
13850 case VFNMADD132PDZ128mb:
13851 case VFNMADD132PDZ128mbk:
13852 case VFNMADD132PDZ128mbkz:
13853 case VFNMADD132PDZ128mk:
13854 case VFNMADD132PDZ128mkz:
13855 case VFNMADD132PDZ128r:
13856 case VFNMADD132PDZ128rk:
13857 case VFNMADD132PDZ128rkz:
13858 case VFNMADD132PDZ256m:
13859 case VFNMADD132PDZ256mb:
13860 case VFNMADD132PDZ256mbk:
13861 case VFNMADD132PDZ256mbkz:
13862 case VFNMADD132PDZ256mk:
13863 case VFNMADD132PDZ256mkz:
13864 case VFNMADD132PDZ256r:
13865 case VFNMADD132PDZ256rk:
13866 case VFNMADD132PDZ256rkz:
13867 case VFNMADD132PDZm:
13868 case VFNMADD132PDZmb:
13869 case VFNMADD132PDZmbk:
13870 case VFNMADD132PDZmbkz:
13871 case VFNMADD132PDZmk:
13872 case VFNMADD132PDZmkz:
13873 case VFNMADD132PDZr:
13874 case VFNMADD132PDZrb:
13875 case VFNMADD132PDZrbk:
13876 case VFNMADD132PDZrbkz:
13877 case VFNMADD132PDZrk:
13878 case VFNMADD132PDZrkz:
13879 case VFNMADD132PDm:
13880 case VFNMADD132PDr:
13881 return true;
13882 }
13883 return false;
13884}
13885
13886bool isPMULHRSW(unsigned Opcode) {
13887 switch (Opcode) {
13888 case MMX_PMULHRSWrm:
13889 case MMX_PMULHRSWrr:
13890 case PMULHRSWrm:
13891 case PMULHRSWrr:
13892 return true;
13893 }
13894 return false;
13895}
13896
13897bool isKADDD(unsigned Opcode) {
13898 return Opcode == KADDDkk;
13899}
13900
13901bool isVFNMSUB132SH(unsigned Opcode) {
13902 switch (Opcode) {
13903 case VFNMSUB132SHZm_Int:
13904 case VFNMSUB132SHZmk_Int:
13905 case VFNMSUB132SHZmkz_Int:
13906 case VFNMSUB132SHZr_Int:
13907 case VFNMSUB132SHZrb_Int:
13908 case VFNMSUB132SHZrbk_Int:
13909 case VFNMSUB132SHZrbkz_Int:
13910 case VFNMSUB132SHZrk_Int:
13911 case VFNMSUB132SHZrkz_Int:
13912 return true;
13913 }
13914 return false;
13915}
13916
13917bool isUIRET(unsigned Opcode) {
13918 return Opcode == UIRET;
13919}
13920
13921bool isBSR(unsigned Opcode) {
13922 switch (Opcode) {
13923 case BSR16rm:
13924 case BSR16rr:
13925 case BSR32rm:
13926 case BSR32rr:
13927 case BSR64rm:
13928 case BSR64rr:
13929 return true;
13930 }
13931 return false;
13932}
13933
13934bool isPCMPEQQ(unsigned Opcode) {
13935 switch (Opcode) {
13936 case PCMPEQQrm:
13937 case PCMPEQQrr:
13938 return true;
13939 }
13940 return false;
13941}
13942
13943bool isCDQ(unsigned Opcode) {
13944 return Opcode == CDQ;
13945}
13946
13947bool isPMAXSW(unsigned Opcode) {
13948 switch (Opcode) {
13949 case MMX_PMAXSWrm:
13950 case MMX_PMAXSWrr:
13951 case PMAXSWrm:
13952 case PMAXSWrr:
13953 return true;
13954 }
13955 return false;
13956}
13957
13958bool isSIDTD(unsigned Opcode) {
13959 return Opcode == SIDT32m;
13960}
13961
13962bool isVCVTPS2PHX(unsigned Opcode) {
13963 switch (Opcode) {
13964 case VCVTPS2PHXZ128rm:
13965 case VCVTPS2PHXZ128rmb:
13966 case VCVTPS2PHXZ128rmbk:
13967 case VCVTPS2PHXZ128rmbkz:
13968 case VCVTPS2PHXZ128rmk:
13969 case VCVTPS2PHXZ128rmkz:
13970 case VCVTPS2PHXZ128rr:
13971 case VCVTPS2PHXZ128rrk:
13972 case VCVTPS2PHXZ128rrkz:
13973 case VCVTPS2PHXZ256rm:
13974 case VCVTPS2PHXZ256rmb:
13975 case VCVTPS2PHXZ256rmbk:
13976 case VCVTPS2PHXZ256rmbkz:
13977 case VCVTPS2PHXZ256rmk:
13978 case VCVTPS2PHXZ256rmkz:
13979 case VCVTPS2PHXZ256rr:
13980 case VCVTPS2PHXZ256rrk:
13981 case VCVTPS2PHXZ256rrkz:
13982 case VCVTPS2PHXZrm:
13983 case VCVTPS2PHXZrmb:
13984 case VCVTPS2PHXZrmbk:
13985 case VCVTPS2PHXZrmbkz:
13986 case VCVTPS2PHXZrmk:
13987 case VCVTPS2PHXZrmkz:
13988 case VCVTPS2PHXZrr:
13989 case VCVTPS2PHXZrrb:
13990 case VCVTPS2PHXZrrbk:
13991 case VCVTPS2PHXZrrbkz:
13992 case VCVTPS2PHXZrrk:
13993 case VCVTPS2PHXZrrkz:
13994 return true;
13995 }
13996 return false;
13997}
13998
13999bool isVPSLLVQ(unsigned Opcode) {
14000 switch (Opcode) {
14001 case VPSLLVQYrm:
14002 case VPSLLVQYrr:
14003 case VPSLLVQZ128rm:
14004 case VPSLLVQZ128rmb:
14005 case VPSLLVQZ128rmbk:
14006 case VPSLLVQZ128rmbkz:
14007 case VPSLLVQZ128rmk:
14008 case VPSLLVQZ128rmkz:
14009 case VPSLLVQZ128rr:
14010 case VPSLLVQZ128rrk:
14011 case VPSLLVQZ128rrkz:
14012 case VPSLLVQZ256rm:
14013 case VPSLLVQZ256rmb:
14014 case VPSLLVQZ256rmbk:
14015 case VPSLLVQZ256rmbkz:
14016 case VPSLLVQZ256rmk:
14017 case VPSLLVQZ256rmkz:
14018 case VPSLLVQZ256rr:
14019 case VPSLLVQZ256rrk:
14020 case VPSLLVQZ256rrkz:
14021 case VPSLLVQZrm:
14022 case VPSLLVQZrmb:
14023 case VPSLLVQZrmbk:
14024 case VPSLLVQZrmbkz:
14025 case VPSLLVQZrmk:
14026 case VPSLLVQZrmkz:
14027 case VPSLLVQZrr:
14028 case VPSLLVQZrrk:
14029 case VPSLLVQZrrkz:
14030 case VPSLLVQrm:
14031 case VPSLLVQrr:
14032 return true;
14033 }
14034 return false;
14035}
14036
14037bool isMOVQ(unsigned Opcode) {
14038 switch (Opcode) {
14039 case MMX_MOVD64from64mr:
14040 case MMX_MOVD64from64rr:
14041 case MMX_MOVD64to64rm:
14042 case MMX_MOVD64to64rr:
14043 case MMX_MOVQ64mr:
14044 case MMX_MOVQ64rm:
14045 case MMX_MOVQ64rr:
14046 case MMX_MOVQ64rr_REV:
14047 case MOV64toPQIrm:
14048 case MOV64toPQIrr:
14049 case MOVPQI2QImr:
14050 case MOVPQI2QIrr:
14051 case MOVPQIto64mr:
14052 case MOVPQIto64rr:
14053 case MOVQI2PQIrm:
14054 case MOVZPQILo2PQIrr:
14055 return true;
14056 }
14057 return false;
14058}
14059
14060bool isPREFETCH(unsigned Opcode) {
14061 return Opcode == PREFETCH;
14062}
14063
14064bool isVCMPBF16(unsigned Opcode) {
14065 switch (Opcode) {
14066 case VCMPBF16Z128rmbi:
14067 case VCMPBF16Z128rmbik:
14068 case VCMPBF16Z128rmi:
14069 case VCMPBF16Z128rmik:
14070 case VCMPBF16Z128rri:
14071 case VCMPBF16Z128rrik:
14072 case VCMPBF16Z256rmbi:
14073 case VCMPBF16Z256rmbik:
14074 case VCMPBF16Z256rmi:
14075 case VCMPBF16Z256rmik:
14076 case VCMPBF16Z256rri:
14077 case VCMPBF16Z256rrik:
14078 case VCMPBF16Zrmbi:
14079 case VCMPBF16Zrmbik:
14080 case VCMPBF16Zrmi:
14081 case VCMPBF16Zrmik:
14082 case VCMPBF16Zrri:
14083 case VCMPBF16Zrrik:
14084 return true;
14085 }
14086 return false;
14087}
14088
14089bool isVBMACOR16X16X16(unsigned Opcode) {
14090 switch (Opcode) {
14091 case VBMACORZ256rm:
14092 case VBMACORZ256rmb:
14093 case VBMACORZ256rmbk:
14094 case VBMACORZ256rmbkz:
14095 case VBMACORZ256rmk:
14096 case VBMACORZ256rmkz:
14097 case VBMACORZ256rr:
14098 case VBMACORZ256rrk:
14099 case VBMACORZ256rrkz:
14100 case VBMACORZrm:
14101 case VBMACORZrmb:
14102 case VBMACORZrmbk:
14103 case VBMACORZrmbkz:
14104 case VBMACORZrmk:
14105 case VBMACORZrmkz:
14106 case VBMACORZrr:
14107 case VBMACORZrrk:
14108 case VBMACORZrrkz:
14109 return true;
14110 }
14111 return false;
14112}
14113
14114bool isCLRSSBSY(unsigned Opcode) {
14115 return Opcode == CLRSSBSY;
14116}
14117
14118bool isTCVTROWPS2PHL(unsigned Opcode) {
14119 switch (Opcode) {
14120 case TCVTROWPS2PHLrte:
14121 case TCVTROWPS2PHLrti:
14122 return true;
14123 }
14124 return false;
14125}
14126
14127bool isPSHUFW(unsigned Opcode) {
14128 switch (Opcode) {
14129 case MMX_PSHUFWmi:
14130 case MMX_PSHUFWri:
14131 return true;
14132 }
14133 return false;
14134}
14135
14136bool isVPDPWSUDS(unsigned Opcode) {
14137 switch (Opcode) {
14138 case VPDPWSUDSYrm:
14139 case VPDPWSUDSYrr:
14140 case VPDPWSUDSZ128rm:
14141 case VPDPWSUDSZ128rmb:
14142 case VPDPWSUDSZ128rmbk:
14143 case VPDPWSUDSZ128rmbkz:
14144 case VPDPWSUDSZ128rmk:
14145 case VPDPWSUDSZ128rmkz:
14146 case VPDPWSUDSZ128rr:
14147 case VPDPWSUDSZ128rrk:
14148 case VPDPWSUDSZ128rrkz:
14149 case VPDPWSUDSZ256rm:
14150 case VPDPWSUDSZ256rmb:
14151 case VPDPWSUDSZ256rmbk:
14152 case VPDPWSUDSZ256rmbkz:
14153 case VPDPWSUDSZ256rmk:
14154 case VPDPWSUDSZ256rmkz:
14155 case VPDPWSUDSZ256rr:
14156 case VPDPWSUDSZ256rrk:
14157 case VPDPWSUDSZ256rrkz:
14158 case VPDPWSUDSZrm:
14159 case VPDPWSUDSZrmb:
14160 case VPDPWSUDSZrmbk:
14161 case VPDPWSUDSZrmbkz:
14162 case VPDPWSUDSZrmk:
14163 case VPDPWSUDSZrmkz:
14164 case VPDPWSUDSZrr:
14165 case VPDPWSUDSZrrk:
14166 case VPDPWSUDSZrrkz:
14167 case VPDPWSUDSrm:
14168 case VPDPWSUDSrr:
14169 return true;
14170 }
14171 return false;
14172}
14173
14174bool isVPMOVSXBQ(unsigned Opcode) {
14175 switch (Opcode) {
14176 case VPMOVSXBQYrm:
14177 case VPMOVSXBQYrr:
14178 case VPMOVSXBQZ128rm:
14179 case VPMOVSXBQZ128rmk:
14180 case VPMOVSXBQZ128rmkz:
14181 case VPMOVSXBQZ128rr:
14182 case VPMOVSXBQZ128rrk:
14183 case VPMOVSXBQZ128rrkz:
14184 case VPMOVSXBQZ256rm:
14185 case VPMOVSXBQZ256rmk:
14186 case VPMOVSXBQZ256rmkz:
14187 case VPMOVSXBQZ256rr:
14188 case VPMOVSXBQZ256rrk:
14189 case VPMOVSXBQZ256rrkz:
14190 case VPMOVSXBQZrm:
14191 case VPMOVSXBQZrmk:
14192 case VPMOVSXBQZrmkz:
14193 case VPMOVSXBQZrr:
14194 case VPMOVSXBQZrrk:
14195 case VPMOVSXBQZrrkz:
14196 case VPMOVSXBQrm:
14197 case VPMOVSXBQrr:
14198 return true;
14199 }
14200 return false;
14201}
14202
14203bool isFICOMP(unsigned Opcode) {
14204 switch (Opcode) {
14205 case FICOMP16m:
14206 case FICOMP32m:
14207 return true;
14208 }
14209 return false;
14210}
14211
14212bool isVFNMSUB132SS(unsigned Opcode) {
14213 switch (Opcode) {
14214 case VFNMSUB132SSZm_Int:
14215 case VFNMSUB132SSZmk_Int:
14216 case VFNMSUB132SSZmkz_Int:
14217 case VFNMSUB132SSZr_Int:
14218 case VFNMSUB132SSZrb_Int:
14219 case VFNMSUB132SSZrbk_Int:
14220 case VFNMSUB132SSZrbkz_Int:
14221 case VFNMSUB132SSZrk_Int:
14222 case VFNMSUB132SSZrkz_Int:
14223 case VFNMSUB132SSm_Int:
14224 case VFNMSUB132SSr_Int:
14225 return true;
14226 }
14227 return false;
14228}
14229
14230bool isVLDMXCSR(unsigned Opcode) {
14231 return Opcode == VLDMXCSR;
14232}
14233
14234bool isVPSUBUSW(unsigned Opcode) {
14235 switch (Opcode) {
14236 case VPSUBUSWYrm:
14237 case VPSUBUSWYrr:
14238 case VPSUBUSWZ128rm:
14239 case VPSUBUSWZ128rmk:
14240 case VPSUBUSWZ128rmkz:
14241 case VPSUBUSWZ128rr:
14242 case VPSUBUSWZ128rrk:
14243 case VPSUBUSWZ128rrkz:
14244 case VPSUBUSWZ256rm:
14245 case VPSUBUSWZ256rmk:
14246 case VPSUBUSWZ256rmkz:
14247 case VPSUBUSWZ256rr:
14248 case VPSUBUSWZ256rrk:
14249 case VPSUBUSWZ256rrkz:
14250 case VPSUBUSWZrm:
14251 case VPSUBUSWZrmk:
14252 case VPSUBUSWZrmkz:
14253 case VPSUBUSWZrr:
14254 case VPSUBUSWZrrk:
14255 case VPSUBUSWZrrkz:
14256 case VPSUBUSWrm:
14257 case VPSUBUSWrr:
14258 return true;
14259 }
14260 return false;
14261}
14262
14263bool isRETF(unsigned Opcode) {
14264 switch (Opcode) {
14265 case LRET16:
14266 case LRET32:
14267 case LRETI16:
14268 case LRETI32:
14269 return true;
14270 }
14271 return false;
14272}
14273
14274bool isKMOVQ(unsigned Opcode) {
14275 switch (Opcode) {
14276 case KMOVQkk:
14277 case KMOVQkk_EVEX:
14278 case KMOVQkm:
14279 case KMOVQkm_EVEX:
14280 case KMOVQkr:
14281 case KMOVQkr_EVEX:
14282 case KMOVQmk:
14283 case KMOVQmk_EVEX:
14284 case KMOVQrk:
14285 case KMOVQrk_EVEX:
14286 return true;
14287 }
14288 return false;
14289}
14290
14291bool isVPADDUSW(unsigned Opcode) {
14292 switch (Opcode) {
14293 case VPADDUSWYrm:
14294 case VPADDUSWYrr:
14295 case VPADDUSWZ128rm:
14296 case VPADDUSWZ128rmk:
14297 case VPADDUSWZ128rmkz:
14298 case VPADDUSWZ128rr:
14299 case VPADDUSWZ128rrk:
14300 case VPADDUSWZ128rrkz:
14301 case VPADDUSWZ256rm:
14302 case VPADDUSWZ256rmk:
14303 case VPADDUSWZ256rmkz:
14304 case VPADDUSWZ256rr:
14305 case VPADDUSWZ256rrk:
14306 case VPADDUSWZ256rrkz:
14307 case VPADDUSWZrm:
14308 case VPADDUSWZrmk:
14309 case VPADDUSWZrmkz:
14310 case VPADDUSWZrr:
14311 case VPADDUSWZrrk:
14312 case VPADDUSWZrrkz:
14313 case VPADDUSWrm:
14314 case VPADDUSWrr:
14315 return true;
14316 }
14317 return false;
14318}
14319
14320bool isPACKSSDW(unsigned Opcode) {
14321 switch (Opcode) {
14322 case MMX_PACKSSDWrm:
14323 case MMX_PACKSSDWrr:
14324 case PACKSSDWrm:
14325 case PACKSSDWrr:
14326 return true;
14327 }
14328 return false;
14329}
14330
14331bool isUMONITOR(unsigned Opcode) {
14332 switch (Opcode) {
14333 case UMONITOR16:
14334 case UMONITOR32:
14335 case UMONITOR64:
14336 return true;
14337 }
14338 return false;
14339}
14340
14341bool isENQCMDS(unsigned Opcode) {
14342 switch (Opcode) {
14343 case ENQCMDS16:
14344 case ENQCMDS32:
14345 case ENQCMDS32_EVEX:
14346 case ENQCMDS64:
14347 case ENQCMDS64_EVEX:
14348 return true;
14349 }
14350 return false;
14351}
14352
14353bool isVCOMXSD(unsigned Opcode) {
14354 switch (Opcode) {
14355 case VCOMXSDZrm_Int:
14356 case VCOMXSDZrr_Int:
14357 case VCOMXSDZrrb_Int:
14358 return true;
14359 }
14360 return false;
14361}
14362
14363bool isVPMAXSQ(unsigned Opcode) {
14364 switch (Opcode) {
14365 case VPMAXSQZ128rm:
14366 case VPMAXSQZ128rmb:
14367 case VPMAXSQZ128rmbk:
14368 case VPMAXSQZ128rmbkz:
14369 case VPMAXSQZ128rmk:
14370 case VPMAXSQZ128rmkz:
14371 case VPMAXSQZ128rr:
14372 case VPMAXSQZ128rrk:
14373 case VPMAXSQZ128rrkz:
14374 case VPMAXSQZ256rm:
14375 case VPMAXSQZ256rmb:
14376 case VPMAXSQZ256rmbk:
14377 case VPMAXSQZ256rmbkz:
14378 case VPMAXSQZ256rmk:
14379 case VPMAXSQZ256rmkz:
14380 case VPMAXSQZ256rr:
14381 case VPMAXSQZ256rrk:
14382 case VPMAXSQZ256rrkz:
14383 case VPMAXSQZrm:
14384 case VPMAXSQZrmb:
14385 case VPMAXSQZrmbk:
14386 case VPMAXSQZrmbkz:
14387 case VPMAXSQZrmk:
14388 case VPMAXSQZrmkz:
14389 case VPMAXSQZrr:
14390 case VPMAXSQZrrk:
14391 case VPMAXSQZrrkz:
14392 return true;
14393 }
14394 return false;
14395}
14396
14397bool isVFMSUB213BF16(unsigned Opcode) {
14398 switch (Opcode) {
14399 case VFMSUB213BF16Z128m:
14400 case VFMSUB213BF16Z128mb:
14401 case VFMSUB213BF16Z128mbk:
14402 case VFMSUB213BF16Z128mbkz:
14403 case VFMSUB213BF16Z128mk:
14404 case VFMSUB213BF16Z128mkz:
14405 case VFMSUB213BF16Z128r:
14406 case VFMSUB213BF16Z128rk:
14407 case VFMSUB213BF16Z128rkz:
14408 case VFMSUB213BF16Z256m:
14409 case VFMSUB213BF16Z256mb:
14410 case VFMSUB213BF16Z256mbk:
14411 case VFMSUB213BF16Z256mbkz:
14412 case VFMSUB213BF16Z256mk:
14413 case VFMSUB213BF16Z256mkz:
14414 case VFMSUB213BF16Z256r:
14415 case VFMSUB213BF16Z256rk:
14416 case VFMSUB213BF16Z256rkz:
14417 case VFMSUB213BF16Zm:
14418 case VFMSUB213BF16Zmb:
14419 case VFMSUB213BF16Zmbk:
14420 case VFMSUB213BF16Zmbkz:
14421 case VFMSUB213BF16Zmk:
14422 case VFMSUB213BF16Zmkz:
14423 case VFMSUB213BF16Zr:
14424 case VFMSUB213BF16Zrk:
14425 case VFMSUB213BF16Zrkz:
14426 return true;
14427 }
14428 return false;
14429}
14430
14431bool isVPERMT2Q(unsigned Opcode) {
14432 switch (Opcode) {
14433 case VPERMT2QZ128rm:
14434 case VPERMT2QZ128rmb:
14435 case VPERMT2QZ128rmbk:
14436 case VPERMT2QZ128rmbkz:
14437 case VPERMT2QZ128rmk:
14438 case VPERMT2QZ128rmkz:
14439 case VPERMT2QZ128rr:
14440 case VPERMT2QZ128rrk:
14441 case VPERMT2QZ128rrkz:
14442 case VPERMT2QZ256rm:
14443 case VPERMT2QZ256rmb:
14444 case VPERMT2QZ256rmbk:
14445 case VPERMT2QZ256rmbkz:
14446 case VPERMT2QZ256rmk:
14447 case VPERMT2QZ256rmkz:
14448 case VPERMT2QZ256rr:
14449 case VPERMT2QZ256rrk:
14450 case VPERMT2QZ256rrkz:
14451 case VPERMT2QZrm:
14452 case VPERMT2QZrmb:
14453 case VPERMT2QZrmbk:
14454 case VPERMT2QZrmbkz:
14455 case VPERMT2QZrmk:
14456 case VPERMT2QZrmkz:
14457 case VPERMT2QZrr:
14458 case VPERMT2QZrrk:
14459 case VPERMT2QZrrkz:
14460 return true;
14461 }
14462 return false;
14463}
14464
14465bool isFDECSTP(unsigned Opcode) {
14466 return Opcode == FDECSTP;
14467}
14468
14469bool isVPTESTMQ(unsigned Opcode) {
14470 switch (Opcode) {
14471 case VPTESTMQZ128rm:
14472 case VPTESTMQZ128rmb:
14473 case VPTESTMQZ128rmbk:
14474 case VPTESTMQZ128rmk:
14475 case VPTESTMQZ128rr:
14476 case VPTESTMQZ128rrk:
14477 case VPTESTMQZ256rm:
14478 case VPTESTMQZ256rmb:
14479 case VPTESTMQZ256rmbk:
14480 case VPTESTMQZ256rmk:
14481 case VPTESTMQZ256rr:
14482 case VPTESTMQZ256rrk:
14483 case VPTESTMQZrm:
14484 case VPTESTMQZrmb:
14485 case VPTESTMQZrmbk:
14486 case VPTESTMQZrmk:
14487 case VPTESTMQZrr:
14488 case VPTESTMQZrrk:
14489 return true;
14490 }
14491 return false;
14492}
14493
14494bool isVRCP14PD(unsigned Opcode) {
14495 switch (Opcode) {
14496 case VRCP14PDZ128m:
14497 case VRCP14PDZ128mb:
14498 case VRCP14PDZ128mbk:
14499 case VRCP14PDZ128mbkz:
14500 case VRCP14PDZ128mk:
14501 case VRCP14PDZ128mkz:
14502 case VRCP14PDZ128r:
14503 case VRCP14PDZ128rk:
14504 case VRCP14PDZ128rkz:
14505 case VRCP14PDZ256m:
14506 case VRCP14PDZ256mb:
14507 case VRCP14PDZ256mbk:
14508 case VRCP14PDZ256mbkz:
14509 case VRCP14PDZ256mk:
14510 case VRCP14PDZ256mkz:
14511 case VRCP14PDZ256r:
14512 case VRCP14PDZ256rk:
14513 case VRCP14PDZ256rkz:
14514 case VRCP14PDZm:
14515 case VRCP14PDZmb:
14516 case VRCP14PDZmbk:
14517 case VRCP14PDZmbkz:
14518 case VRCP14PDZmk:
14519 case VRCP14PDZmkz:
14520 case VRCP14PDZr:
14521 case VRCP14PDZrk:
14522 case VRCP14PDZrkz:
14523 return true;
14524 }
14525 return false;
14526}
14527
14528bool isARPL(unsigned Opcode) {
14529 switch (Opcode) {
14530 case ARPL16mr:
14531 case ARPL16rr:
14532 return true;
14533 }
14534 return false;
14535}
14536
14537bool isVFMSUB213SD(unsigned Opcode) {
14538 switch (Opcode) {
14539 case VFMSUB213SDZm_Int:
14540 case VFMSUB213SDZmk_Int:
14541 case VFMSUB213SDZmkz_Int:
14542 case VFMSUB213SDZr_Int:
14543 case VFMSUB213SDZrb_Int:
14544 case VFMSUB213SDZrbk_Int:
14545 case VFMSUB213SDZrbkz_Int:
14546 case VFMSUB213SDZrk_Int:
14547 case VFMSUB213SDZrkz_Int:
14548 case VFMSUB213SDm_Int:
14549 case VFMSUB213SDr_Int:
14550 return true;
14551 }
14552 return false;
14553}
14554
14555bool isJMPABS(unsigned Opcode) {
14556 return Opcode == JMPABS64i;
14557}
14558
14559bool isVUNPCKHPS(unsigned Opcode) {
14560 switch (Opcode) {
14561 case VUNPCKHPSYrm:
14562 case VUNPCKHPSYrr:
14563 case VUNPCKHPSZ128rm:
14564 case VUNPCKHPSZ128rmb:
14565 case VUNPCKHPSZ128rmbk:
14566 case VUNPCKHPSZ128rmbkz:
14567 case VUNPCKHPSZ128rmk:
14568 case VUNPCKHPSZ128rmkz:
14569 case VUNPCKHPSZ128rr:
14570 case VUNPCKHPSZ128rrk:
14571 case VUNPCKHPSZ128rrkz:
14572 case VUNPCKHPSZ256rm:
14573 case VUNPCKHPSZ256rmb:
14574 case VUNPCKHPSZ256rmbk:
14575 case VUNPCKHPSZ256rmbkz:
14576 case VUNPCKHPSZ256rmk:
14577 case VUNPCKHPSZ256rmkz:
14578 case VUNPCKHPSZ256rr:
14579 case VUNPCKHPSZ256rrk:
14580 case VUNPCKHPSZ256rrkz:
14581 case VUNPCKHPSZrm:
14582 case VUNPCKHPSZrmb:
14583 case VUNPCKHPSZrmbk:
14584 case VUNPCKHPSZrmbkz:
14585 case VUNPCKHPSZrmk:
14586 case VUNPCKHPSZrmkz:
14587 case VUNPCKHPSZrr:
14588 case VUNPCKHPSZrrk:
14589 case VUNPCKHPSZrrkz:
14590 case VUNPCKHPSrm:
14591 case VUNPCKHPSrr:
14592 return true;
14593 }
14594 return false;
14595}
14596
14597bool isVFNMADDSS(unsigned Opcode) {
14598 switch (Opcode) {
14599 case VFNMADDSS4mr:
14600 case VFNMADDSS4rm:
14601 case VFNMADDSS4rr:
14602 case VFNMADDSS4rr_REV:
14603 return true;
14604 }
14605 return false;
14606}
14607
14608bool isSIDT(unsigned Opcode) {
14609 return Opcode == SIDT64m;
14610}
14611
14612bool isVPCMPGTB(unsigned Opcode) {
14613 switch (Opcode) {
14614 case VPCMPGTBYrm:
14615 case VPCMPGTBYrr:
14616 case VPCMPGTBZ128rm:
14617 case VPCMPGTBZ128rmk:
14618 case VPCMPGTBZ128rr:
14619 case VPCMPGTBZ128rrk:
14620 case VPCMPGTBZ256rm:
14621 case VPCMPGTBZ256rmk:
14622 case VPCMPGTBZ256rr:
14623 case VPCMPGTBZ256rrk:
14624 case VPCMPGTBZrm:
14625 case VPCMPGTBZrmk:
14626 case VPCMPGTBZrr:
14627 case VPCMPGTBZrrk:
14628 case VPCMPGTBrm:
14629 case VPCMPGTBrr:
14630 return true;
14631 }
14632 return false;
14633}
14634
14635bool isVPRORD(unsigned Opcode) {
14636 switch (Opcode) {
14637 case VPRORDZ128mbi:
14638 case VPRORDZ128mbik:
14639 case VPRORDZ128mbikz:
14640 case VPRORDZ128mi:
14641 case VPRORDZ128mik:
14642 case VPRORDZ128mikz:
14643 case VPRORDZ128ri:
14644 case VPRORDZ128rik:
14645 case VPRORDZ128rikz:
14646 case VPRORDZ256mbi:
14647 case VPRORDZ256mbik:
14648 case VPRORDZ256mbikz:
14649 case VPRORDZ256mi:
14650 case VPRORDZ256mik:
14651 case VPRORDZ256mikz:
14652 case VPRORDZ256ri:
14653 case VPRORDZ256rik:
14654 case VPRORDZ256rikz:
14655 case VPRORDZmbi:
14656 case VPRORDZmbik:
14657 case VPRORDZmbikz:
14658 case VPRORDZmi:
14659 case VPRORDZmik:
14660 case VPRORDZmikz:
14661 case VPRORDZri:
14662 case VPRORDZrik:
14663 case VPRORDZrikz:
14664 return true;
14665 }
14666 return false;
14667}
14668
14669bool isVSUBSS(unsigned Opcode) {
14670 switch (Opcode) {
14671 case VSUBSSZrm_Int:
14672 case VSUBSSZrmk_Int:
14673 case VSUBSSZrmkz_Int:
14674 case VSUBSSZrr_Int:
14675 case VSUBSSZrrb_Int:
14676 case VSUBSSZrrbk_Int:
14677 case VSUBSSZrrbkz_Int:
14678 case VSUBSSZrrk_Int:
14679 case VSUBSSZrrkz_Int:
14680 case VSUBSSrm_Int:
14681 case VSUBSSrr_Int:
14682 return true;
14683 }
14684 return false;
14685}
14686
14687bool isPUSHFQ(unsigned Opcode) {
14688 return Opcode == PUSHF64;
14689}
14690
14691bool isVCVTHF82PH(unsigned Opcode) {
14692 switch (Opcode) {
14693 case VCVTHF82PHZ128rm:
14694 case VCVTHF82PHZ128rmk:
14695 case VCVTHF82PHZ128rmkz:
14696 case VCVTHF82PHZ128rr:
14697 case VCVTHF82PHZ128rrk:
14698 case VCVTHF82PHZ128rrkz:
14699 case VCVTHF82PHZ256rm:
14700 case VCVTHF82PHZ256rmk:
14701 case VCVTHF82PHZ256rmkz:
14702 case VCVTHF82PHZ256rr:
14703 case VCVTHF82PHZ256rrk:
14704 case VCVTHF82PHZ256rrkz:
14705 case VCVTHF82PHZrm:
14706 case VCVTHF82PHZrmk:
14707 case VCVTHF82PHZrmkz:
14708 case VCVTHF82PHZrr:
14709 case VCVTHF82PHZrrk:
14710 case VCVTHF82PHZrrkz:
14711 return true;
14712 }
14713 return false;
14714}
14715
14716bool isVPCLMULQDQ(unsigned Opcode) {
14717 switch (Opcode) {
14718 case VPCLMULQDQYrmi:
14719 case VPCLMULQDQYrri:
14720 case VPCLMULQDQZ128rmi:
14721 case VPCLMULQDQZ128rri:
14722 case VPCLMULQDQZ256rmi:
14723 case VPCLMULQDQZ256rri:
14724 case VPCLMULQDQZrmi:
14725 case VPCLMULQDQZrri:
14726 case VPCLMULQDQrmi:
14727 case VPCLMULQDQrri:
14728 return true;
14729 }
14730 return false;
14731}
14732
14733bool isVPADDUSB(unsigned Opcode) {
14734 switch (Opcode) {
14735 case VPADDUSBYrm:
14736 case VPADDUSBYrr:
14737 case VPADDUSBZ128rm:
14738 case VPADDUSBZ128rmk:
14739 case VPADDUSBZ128rmkz:
14740 case VPADDUSBZ128rr:
14741 case VPADDUSBZ128rrk:
14742 case VPADDUSBZ128rrkz:
14743 case VPADDUSBZ256rm:
14744 case VPADDUSBZ256rmk:
14745 case VPADDUSBZ256rmkz:
14746 case VPADDUSBZ256rr:
14747 case VPADDUSBZ256rrk:
14748 case VPADDUSBZ256rrkz:
14749 case VPADDUSBZrm:
14750 case VPADDUSBZrmk:
14751 case VPADDUSBZrmkz:
14752 case VPADDUSBZrr:
14753 case VPADDUSBZrrk:
14754 case VPADDUSBZrrkz:
14755 case VPADDUSBrm:
14756 case VPADDUSBrr:
14757 return true;
14758 }
14759 return false;
14760}
14761
14762bool isVPCMPD(unsigned Opcode) {
14763 switch (Opcode) {
14764 case VPCMPDZ128rmbi:
14765 case VPCMPDZ128rmbik:
14766 case VPCMPDZ128rmi:
14767 case VPCMPDZ128rmik:
14768 case VPCMPDZ128rri:
14769 case VPCMPDZ128rrik:
14770 case VPCMPDZ256rmbi:
14771 case VPCMPDZ256rmbik:
14772 case VPCMPDZ256rmi:
14773 case VPCMPDZ256rmik:
14774 case VPCMPDZ256rri:
14775 case VPCMPDZ256rrik:
14776 case VPCMPDZrmbi:
14777 case VPCMPDZrmbik:
14778 case VPCMPDZrmi:
14779 case VPCMPDZrmik:
14780 case VPCMPDZrri:
14781 case VPCMPDZrrik:
14782 return true;
14783 }
14784 return false;
14785}
14786
14787bool isMOVSD(unsigned Opcode) {
14788 switch (Opcode) {
14789 case MOVSDmr:
14790 case MOVSDrm:
14791 case MOVSDrr:
14792 case MOVSDrr_REV:
14793 case MOVSL:
14794 return true;
14795 }
14796 return false;
14797}
14798
14799bool isPSUBUSW(unsigned Opcode) {
14800 switch (Opcode) {
14801 case MMX_PSUBUSWrm:
14802 case MMX_PSUBUSWrr:
14803 case PSUBUSWrm:
14804 case PSUBUSWrr:
14805 return true;
14806 }
14807 return false;
14808}
14809
14810bool isVFMSUBADD132PS(unsigned Opcode) {
14811 switch (Opcode) {
14812 case VFMSUBADD132PSYm:
14813 case VFMSUBADD132PSYr:
14814 case VFMSUBADD132PSZ128m:
14815 case VFMSUBADD132PSZ128mb:
14816 case VFMSUBADD132PSZ128mbk:
14817 case VFMSUBADD132PSZ128mbkz:
14818 case VFMSUBADD132PSZ128mk:
14819 case VFMSUBADD132PSZ128mkz:
14820 case VFMSUBADD132PSZ128r:
14821 case VFMSUBADD132PSZ128rk:
14822 case VFMSUBADD132PSZ128rkz:
14823 case VFMSUBADD132PSZ256m:
14824 case VFMSUBADD132PSZ256mb:
14825 case VFMSUBADD132PSZ256mbk:
14826 case VFMSUBADD132PSZ256mbkz:
14827 case VFMSUBADD132PSZ256mk:
14828 case VFMSUBADD132PSZ256mkz:
14829 case VFMSUBADD132PSZ256r:
14830 case VFMSUBADD132PSZ256rk:
14831 case VFMSUBADD132PSZ256rkz:
14832 case VFMSUBADD132PSZm:
14833 case VFMSUBADD132PSZmb:
14834 case VFMSUBADD132PSZmbk:
14835 case VFMSUBADD132PSZmbkz:
14836 case VFMSUBADD132PSZmk:
14837 case VFMSUBADD132PSZmkz:
14838 case VFMSUBADD132PSZr:
14839 case VFMSUBADD132PSZrb:
14840 case VFMSUBADD132PSZrbk:
14841 case VFMSUBADD132PSZrbkz:
14842 case VFMSUBADD132PSZrk:
14843 case VFMSUBADD132PSZrkz:
14844 case VFMSUBADD132PSm:
14845 case VFMSUBADD132PSr:
14846 return true;
14847 }
14848 return false;
14849}
14850
14851bool isMOVMSKPS(unsigned Opcode) {
14852 return Opcode == MOVMSKPSrr;
14853}
14854
14855bool isVFIXUPIMMSS(unsigned Opcode) {
14856 switch (Opcode) {
14857 case VFIXUPIMMSSZrmi:
14858 case VFIXUPIMMSSZrmik:
14859 case VFIXUPIMMSSZrmikz:
14860 case VFIXUPIMMSSZrri:
14861 case VFIXUPIMMSSZrrib:
14862 case VFIXUPIMMSSZrribk:
14863 case VFIXUPIMMSSZrribkz:
14864 case VFIXUPIMMSSZrrik:
14865 case VFIXUPIMMSSZrrikz:
14866 return true;
14867 }
14868 return false;
14869}
14870
14871bool isMFENCE(unsigned Opcode) {
14872 return Opcode == MFENCE;
14873}
14874
14875bool isFTST(unsigned Opcode) {
14876 return Opcode == TST_F;
14877}
14878
14879bool isVPMADDWD(unsigned Opcode) {
14880 switch (Opcode) {
14881 case VPMADDWDYrm:
14882 case VPMADDWDYrr:
14883 case VPMADDWDZ128rm:
14884 case VPMADDWDZ128rmk:
14885 case VPMADDWDZ128rmkz:
14886 case VPMADDWDZ128rr:
14887 case VPMADDWDZ128rrk:
14888 case VPMADDWDZ128rrkz:
14889 case VPMADDWDZ256rm:
14890 case VPMADDWDZ256rmk:
14891 case VPMADDWDZ256rmkz:
14892 case VPMADDWDZ256rr:
14893 case VPMADDWDZ256rrk:
14894 case VPMADDWDZ256rrkz:
14895 case VPMADDWDZrm:
14896 case VPMADDWDZrmk:
14897 case VPMADDWDZrmkz:
14898 case VPMADDWDZrr:
14899 case VPMADDWDZrrk:
14900 case VPMADDWDZrrkz:
14901 case VPMADDWDrm:
14902 case VPMADDWDrr:
14903 return true;
14904 }
14905 return false;
14906}
14907
14908bool isPOP(unsigned Opcode) {
14909 switch (Opcode) {
14910 case POP16r:
14911 case POP16rmm:
14912 case POP16rmr:
14913 case POP32r:
14914 case POP32rmm:
14915 case POP32rmr:
14916 case POP64r:
14917 case POP64rmm:
14918 case POP64rmr:
14919 case POPDS16:
14920 case POPDS32:
14921 case POPES16:
14922 case POPES32:
14923 case POPFS16:
14924 case POPFS32:
14925 case POPFS64:
14926 case POPGS16:
14927 case POPGS32:
14928 case POPGS64:
14929 case POPSS16:
14930 case POPSS32:
14931 return true;
14932 }
14933 return false;
14934}
14935
14936bool isPSUBW(unsigned Opcode) {
14937 switch (Opcode) {
14938 case MMX_PSUBWrm:
14939 case MMX_PSUBWrr:
14940 case PSUBWrm:
14941 case PSUBWrr:
14942 return true;
14943 }
14944 return false;
14945}
14946
14947bool isBSWAP(unsigned Opcode) {
14948 switch (Opcode) {
14949 case BSWAP16r_BAD:
14950 case BSWAP32r:
14951 case BSWAP64r:
14952 return true;
14953 }
14954 return false;
14955}
14956
14957bool isPFMIN(unsigned Opcode) {
14958 switch (Opcode) {
14959 case PFMINrm:
14960 case PFMINrr:
14961 return true;
14962 }
14963 return false;
14964}
14965
14966bool isVFPCLASSPD(unsigned Opcode) {
14967 switch (Opcode) {
14968 case VFPCLASSPDZ128mbi:
14969 case VFPCLASSPDZ128mbik:
14970 case VFPCLASSPDZ128mi:
14971 case VFPCLASSPDZ128mik:
14972 case VFPCLASSPDZ128ri:
14973 case VFPCLASSPDZ128rik:
14974 case VFPCLASSPDZ256mbi:
14975 case VFPCLASSPDZ256mbik:
14976 case VFPCLASSPDZ256mi:
14977 case VFPCLASSPDZ256mik:
14978 case VFPCLASSPDZ256ri:
14979 case VFPCLASSPDZ256rik:
14980 case VFPCLASSPDZmbi:
14981 case VFPCLASSPDZmbik:
14982 case VFPCLASSPDZmi:
14983 case VFPCLASSPDZmik:
14984 case VFPCLASSPDZri:
14985 case VFPCLASSPDZrik:
14986 return true;
14987 }
14988 return false;
14989}
14990
14991bool isVPSHRDVD(unsigned Opcode) {
14992 switch (Opcode) {
14993 case VPSHRDVDZ128m:
14994 case VPSHRDVDZ128mb:
14995 case VPSHRDVDZ128mbk:
14996 case VPSHRDVDZ128mbkz:
14997 case VPSHRDVDZ128mk:
14998 case VPSHRDVDZ128mkz:
14999 case VPSHRDVDZ128r:
15000 case VPSHRDVDZ128rk:
15001 case VPSHRDVDZ128rkz:
15002 case VPSHRDVDZ256m:
15003 case VPSHRDVDZ256mb:
15004 case VPSHRDVDZ256mbk:
15005 case VPSHRDVDZ256mbkz:
15006 case VPSHRDVDZ256mk:
15007 case VPSHRDVDZ256mkz:
15008 case VPSHRDVDZ256r:
15009 case VPSHRDVDZ256rk:
15010 case VPSHRDVDZ256rkz:
15011 case VPSHRDVDZm:
15012 case VPSHRDVDZmb:
15013 case VPSHRDVDZmbk:
15014 case VPSHRDVDZmbkz:
15015 case VPSHRDVDZmk:
15016 case VPSHRDVDZmkz:
15017 case VPSHRDVDZr:
15018 case VPSHRDVDZrk:
15019 case VPSHRDVDZrkz:
15020 return true;
15021 }
15022 return false;
15023}
15024
15025bool isPADDW(unsigned Opcode) {
15026 switch (Opcode) {
15027 case MMX_PADDWrm:
15028 case MMX_PADDWrr:
15029 case PADDWrm:
15030 case PADDWrr:
15031 return true;
15032 }
15033 return false;
15034}
15035
15036bool isCVTSI2SD(unsigned Opcode) {
15037 switch (Opcode) {
15038 case CVTSI2SDrm_Int:
15039 case CVTSI2SDrr_Int:
15040 case CVTSI642SDrm_Int:
15041 case CVTSI642SDrr_Int:
15042 return true;
15043 }
15044 return false;
15045}
15046
15047bool isENQCMD(unsigned Opcode) {
15048 switch (Opcode) {
15049 case ENQCMD16:
15050 case ENQCMD32:
15051 case ENQCMD32_EVEX:
15052 case ENQCMD64:
15053 case ENQCMD64_EVEX:
15054 return true;
15055 }
15056 return false;
15057}
15058
15059bool isXSHA1(unsigned Opcode) {
15060 return Opcode == XSHA1;
15061}
15062
15063bool isVFNMADD132SD(unsigned Opcode) {
15064 switch (Opcode) {
15065 case VFNMADD132SDZm_Int:
15066 case VFNMADD132SDZmk_Int:
15067 case VFNMADD132SDZmkz_Int:
15068 case VFNMADD132SDZr_Int:
15069 case VFNMADD132SDZrb_Int:
15070 case VFNMADD132SDZrbk_Int:
15071 case VFNMADD132SDZrbkz_Int:
15072 case VFNMADD132SDZrk_Int:
15073 case VFNMADD132SDZrkz_Int:
15074 case VFNMADD132SDm_Int:
15075 case VFNMADD132SDr_Int:
15076 return true;
15077 }
15078 return false;
15079}
15080
15081bool isMOVZX(unsigned Opcode) {
15082 switch (Opcode) {
15083 case MOVZX16rm16:
15084 case MOVZX16rm8:
15085 case MOVZX16rr16:
15086 case MOVZX16rr8:
15087 case MOVZX32rm16:
15088 case MOVZX32rm8:
15089 case MOVZX32rr16:
15090 case MOVZX32rr8:
15091 case MOVZX64rm16:
15092 case MOVZX64rm8:
15093 case MOVZX64rr16:
15094 case MOVZX64rr8:
15095 return true;
15096 }
15097 return false;
15098}
15099
15100bool isVFIXUPIMMSD(unsigned Opcode) {
15101 switch (Opcode) {
15102 case VFIXUPIMMSDZrmi:
15103 case VFIXUPIMMSDZrmik:
15104 case VFIXUPIMMSDZrmikz:
15105 case VFIXUPIMMSDZrri:
15106 case VFIXUPIMMSDZrrib:
15107 case VFIXUPIMMSDZrribk:
15108 case VFIXUPIMMSDZrribkz:
15109 case VFIXUPIMMSDZrrik:
15110 case VFIXUPIMMSDZrrikz:
15111 return true;
15112 }
15113 return false;
15114}
15115
15116bool isINVD(unsigned Opcode) {
15117 return Opcode == INVD;
15118}
15119
15120bool isVFIXUPIMMPS(unsigned Opcode) {
15121 switch (Opcode) {
15122 case VFIXUPIMMPSZ128rmbi:
15123 case VFIXUPIMMPSZ128rmbik:
15124 case VFIXUPIMMPSZ128rmbikz:
15125 case VFIXUPIMMPSZ128rmi:
15126 case VFIXUPIMMPSZ128rmik:
15127 case VFIXUPIMMPSZ128rmikz:
15128 case VFIXUPIMMPSZ128rri:
15129 case VFIXUPIMMPSZ128rrik:
15130 case VFIXUPIMMPSZ128rrikz:
15131 case VFIXUPIMMPSZ256rmbi:
15132 case VFIXUPIMMPSZ256rmbik:
15133 case VFIXUPIMMPSZ256rmbikz:
15134 case VFIXUPIMMPSZ256rmi:
15135 case VFIXUPIMMPSZ256rmik:
15136 case VFIXUPIMMPSZ256rmikz:
15137 case VFIXUPIMMPSZ256rri:
15138 case VFIXUPIMMPSZ256rrik:
15139 case VFIXUPIMMPSZ256rrikz:
15140 case VFIXUPIMMPSZrmbi:
15141 case VFIXUPIMMPSZrmbik:
15142 case VFIXUPIMMPSZrmbikz:
15143 case VFIXUPIMMPSZrmi:
15144 case VFIXUPIMMPSZrmik:
15145 case VFIXUPIMMPSZrmikz:
15146 case VFIXUPIMMPSZrri:
15147 case VFIXUPIMMPSZrrib:
15148 case VFIXUPIMMPSZrribk:
15149 case VFIXUPIMMPSZrribkz:
15150 case VFIXUPIMMPSZrrik:
15151 case VFIXUPIMMPSZrrikz:
15152 return true;
15153 }
15154 return false;
15155}
15156
15157bool isMOVDQU(unsigned Opcode) {
15158 switch (Opcode) {
15159 case MOVDQUmr:
15160 case MOVDQUrm:
15161 case MOVDQUrr:
15162 case MOVDQUrr_REV:
15163 return true;
15164 }
15165 return false;
15166}
15167
15168bool isVFPCLASSPS(unsigned Opcode) {
15169 switch (Opcode) {
15170 case VFPCLASSPSZ128mbi:
15171 case VFPCLASSPSZ128mbik:
15172 case VFPCLASSPSZ128mi:
15173 case VFPCLASSPSZ128mik:
15174 case VFPCLASSPSZ128ri:
15175 case VFPCLASSPSZ128rik:
15176 case VFPCLASSPSZ256mbi:
15177 case VFPCLASSPSZ256mbik:
15178 case VFPCLASSPSZ256mi:
15179 case VFPCLASSPSZ256mik:
15180 case VFPCLASSPSZ256ri:
15181 case VFPCLASSPSZ256rik:
15182 case VFPCLASSPSZmbi:
15183 case VFPCLASSPSZmbik:
15184 case VFPCLASSPSZmi:
15185 case VFPCLASSPSZmik:
15186 case VFPCLASSPSZri:
15187 case VFPCLASSPSZrik:
15188 return true;
15189 }
15190 return false;
15191}
15192
15193bool isVPERMILPS(unsigned Opcode) {
15194 switch (Opcode) {
15195 case VPERMILPSYmi:
15196 case VPERMILPSYri:
15197 case VPERMILPSYrm:
15198 case VPERMILPSYrr:
15199 case VPERMILPSZ128mbi:
15200 case VPERMILPSZ128mbik:
15201 case VPERMILPSZ128mbikz:
15202 case VPERMILPSZ128mi:
15203 case VPERMILPSZ128mik:
15204 case VPERMILPSZ128mikz:
15205 case VPERMILPSZ128ri:
15206 case VPERMILPSZ128rik:
15207 case VPERMILPSZ128rikz:
15208 case VPERMILPSZ128rm:
15209 case VPERMILPSZ128rmb:
15210 case VPERMILPSZ128rmbk:
15211 case VPERMILPSZ128rmbkz:
15212 case VPERMILPSZ128rmk:
15213 case VPERMILPSZ128rmkz:
15214 case VPERMILPSZ128rr:
15215 case VPERMILPSZ128rrk:
15216 case VPERMILPSZ128rrkz:
15217 case VPERMILPSZ256mbi:
15218 case VPERMILPSZ256mbik:
15219 case VPERMILPSZ256mbikz:
15220 case VPERMILPSZ256mi:
15221 case VPERMILPSZ256mik:
15222 case VPERMILPSZ256mikz:
15223 case VPERMILPSZ256ri:
15224 case VPERMILPSZ256rik:
15225 case VPERMILPSZ256rikz:
15226 case VPERMILPSZ256rm:
15227 case VPERMILPSZ256rmb:
15228 case VPERMILPSZ256rmbk:
15229 case VPERMILPSZ256rmbkz:
15230 case VPERMILPSZ256rmk:
15231 case VPERMILPSZ256rmkz:
15232 case VPERMILPSZ256rr:
15233 case VPERMILPSZ256rrk:
15234 case VPERMILPSZ256rrkz:
15235 case VPERMILPSZmbi:
15236 case VPERMILPSZmbik:
15237 case VPERMILPSZmbikz:
15238 case VPERMILPSZmi:
15239 case VPERMILPSZmik:
15240 case VPERMILPSZmikz:
15241 case VPERMILPSZri:
15242 case VPERMILPSZrik:
15243 case VPERMILPSZrikz:
15244 case VPERMILPSZrm:
15245 case VPERMILPSZrmb:
15246 case VPERMILPSZrmbk:
15247 case VPERMILPSZrmbkz:
15248 case VPERMILPSZrmk:
15249 case VPERMILPSZrmkz:
15250 case VPERMILPSZrr:
15251 case VPERMILPSZrrk:
15252 case VPERMILPSZrrkz:
15253 case VPERMILPSmi:
15254 case VPERMILPSri:
15255 case VPERMILPSrm:
15256 case VPERMILPSrr:
15257 return true;
15258 }
15259 return false;
15260}
15261
15262bool isMOVSQ(unsigned Opcode) {
15263 return Opcode == MOVSQ;
15264}
15265
15266bool isAESDECWIDE128KL(unsigned Opcode) {
15267 return Opcode == AESDECWIDE128KL;
15268}
15269
15270bool isROUNDSS(unsigned Opcode) {
15271 switch (Opcode) {
15272 case ROUNDSSmi_Int:
15273 case ROUNDSSri_Int:
15274 return true;
15275 }
15276 return false;
15277}
15278
15279bool isVPMOVW2M(unsigned Opcode) {
15280 switch (Opcode) {
15281 case VPMOVW2MZ128kr:
15282 case VPMOVW2MZ256kr:
15283 case VPMOVW2MZkr:
15284 return true;
15285 }
15286 return false;
15287}
15288
15289bool isVPSHUFB(unsigned Opcode) {
15290 switch (Opcode) {
15291 case VPSHUFBYrm:
15292 case VPSHUFBYrr:
15293 case VPSHUFBZ128rm:
15294 case VPSHUFBZ128rmk:
15295 case VPSHUFBZ128rmkz:
15296 case VPSHUFBZ128rr:
15297 case VPSHUFBZ128rrk:
15298 case VPSHUFBZ128rrkz:
15299 case VPSHUFBZ256rm:
15300 case VPSHUFBZ256rmk:
15301 case VPSHUFBZ256rmkz:
15302 case VPSHUFBZ256rr:
15303 case VPSHUFBZ256rrk:
15304 case VPSHUFBZ256rrkz:
15305 case VPSHUFBZrm:
15306 case VPSHUFBZrmk:
15307 case VPSHUFBZrmkz:
15308 case VPSHUFBZrr:
15309 case VPSHUFBZrrk:
15310 case VPSHUFBZrrkz:
15311 case VPSHUFBrm:
15312 case VPSHUFBrr:
15313 return true;
15314 }
15315 return false;
15316}
15317
15318bool isVMULSD(unsigned Opcode) {
15319 switch (Opcode) {
15320 case VMULSDZrm_Int:
15321 case VMULSDZrmk_Int:
15322 case VMULSDZrmkz_Int:
15323 case VMULSDZrr_Int:
15324 case VMULSDZrrb_Int:
15325 case VMULSDZrrbk_Int:
15326 case VMULSDZrrbkz_Int:
15327 case VMULSDZrrk_Int:
15328 case VMULSDZrrkz_Int:
15329 case VMULSDrm_Int:
15330 case VMULSDrr_Int:
15331 return true;
15332 }
15333 return false;
15334}
15335
15336bool isVPERMI2W(unsigned Opcode) {
15337 switch (Opcode) {
15338 case VPERMI2WZ128rm:
15339 case VPERMI2WZ128rmk:
15340 case VPERMI2WZ128rmkz:
15341 case VPERMI2WZ128rr:
15342 case VPERMI2WZ128rrk:
15343 case VPERMI2WZ128rrkz:
15344 case VPERMI2WZ256rm:
15345 case VPERMI2WZ256rmk:
15346 case VPERMI2WZ256rmkz:
15347 case VPERMI2WZ256rr:
15348 case VPERMI2WZ256rrk:
15349 case VPERMI2WZ256rrkz:
15350 case VPERMI2WZrm:
15351 case VPERMI2WZrmk:
15352 case VPERMI2WZrmkz:
15353 case VPERMI2WZrr:
15354 case VPERMI2WZrrk:
15355 case VPERMI2WZrrkz:
15356 return true;
15357 }
15358 return false;
15359}
15360
15361bool isVREDUCESS(unsigned Opcode) {
15362 switch (Opcode) {
15363 case VREDUCESSZrmi:
15364 case VREDUCESSZrmik:
15365 case VREDUCESSZrmikz:
15366 case VREDUCESSZrri:
15367 case VREDUCESSZrrib:
15368 case VREDUCESSZrribk:
15369 case VREDUCESSZrribkz:
15370 case VREDUCESSZrrik:
15371 case VREDUCESSZrrikz:
15372 return true;
15373 }
15374 return false;
15375}
15376
15377bool isFST(unsigned Opcode) {
15378 switch (Opcode) {
15379 case ST_F32m:
15380 case ST_F64m:
15381 case ST_Frr:
15382 return true;
15383 }
15384 return false;
15385}
15386
15387bool isVPHSUBW(unsigned Opcode) {
15388 switch (Opcode) {
15389 case VPHSUBWYrm:
15390 case VPHSUBWYrr:
15391 case VPHSUBWrm:
15392 case VPHSUBWrr:
15393 return true;
15394 }
15395 return false;
15396}
15397
15398bool isFRNDINT(unsigned Opcode) {
15399 return Opcode == FRNDINT;
15400}
15401
15402bool isSHR(unsigned Opcode) {
15403 switch (Opcode) {
15404 case SHR16m1:
15405 case SHR16m1_EVEX:
15406 case SHR16m1_ND:
15407 case SHR16m1_NF:
15408 case SHR16m1_NF_ND:
15409 case SHR16mCL:
15410 case SHR16mCL_EVEX:
15411 case SHR16mCL_ND:
15412 case SHR16mCL_NF:
15413 case SHR16mCL_NF_ND:
15414 case SHR16mi:
15415 case SHR16mi_EVEX:
15416 case SHR16mi_ND:
15417 case SHR16mi_NF:
15418 case SHR16mi_NF_ND:
15419 case SHR16r1:
15420 case SHR16r1_EVEX:
15421 case SHR16r1_ND:
15422 case SHR16r1_NF:
15423 case SHR16r1_NF_ND:
15424 case SHR16rCL:
15425 case SHR16rCL_EVEX:
15426 case SHR16rCL_ND:
15427 case SHR16rCL_NF:
15428 case SHR16rCL_NF_ND:
15429 case SHR16ri:
15430 case SHR16ri_EVEX:
15431 case SHR16ri_ND:
15432 case SHR16ri_NF:
15433 case SHR16ri_NF_ND:
15434 case SHR32m1:
15435 case SHR32m1_EVEX:
15436 case SHR32m1_ND:
15437 case SHR32m1_NF:
15438 case SHR32m1_NF_ND:
15439 case SHR32mCL:
15440 case SHR32mCL_EVEX:
15441 case SHR32mCL_ND:
15442 case SHR32mCL_NF:
15443 case SHR32mCL_NF_ND:
15444 case SHR32mi:
15445 case SHR32mi_EVEX:
15446 case SHR32mi_ND:
15447 case SHR32mi_NF:
15448 case SHR32mi_NF_ND:
15449 case SHR32r1:
15450 case SHR32r1_EVEX:
15451 case SHR32r1_ND:
15452 case SHR32r1_NF:
15453 case SHR32r1_NF_ND:
15454 case SHR32rCL:
15455 case SHR32rCL_EVEX:
15456 case SHR32rCL_ND:
15457 case SHR32rCL_NF:
15458 case SHR32rCL_NF_ND:
15459 case SHR32ri:
15460 case SHR32ri_EVEX:
15461 case SHR32ri_ND:
15462 case SHR32ri_NF:
15463 case SHR32ri_NF_ND:
15464 case SHR64m1:
15465 case SHR64m1_EVEX:
15466 case SHR64m1_ND:
15467 case SHR64m1_NF:
15468 case SHR64m1_NF_ND:
15469 case SHR64mCL:
15470 case SHR64mCL_EVEX:
15471 case SHR64mCL_ND:
15472 case SHR64mCL_NF:
15473 case SHR64mCL_NF_ND:
15474 case SHR64mi:
15475 case SHR64mi_EVEX:
15476 case SHR64mi_ND:
15477 case SHR64mi_NF:
15478 case SHR64mi_NF_ND:
15479 case SHR64r1:
15480 case SHR64r1_EVEX:
15481 case SHR64r1_ND:
15482 case SHR64r1_NF:
15483 case SHR64r1_NF_ND:
15484 case SHR64rCL:
15485 case SHR64rCL_EVEX:
15486 case SHR64rCL_ND:
15487 case SHR64rCL_NF:
15488 case SHR64rCL_NF_ND:
15489 case SHR64ri:
15490 case SHR64ri_EVEX:
15491 case SHR64ri_ND:
15492 case SHR64ri_NF:
15493 case SHR64ri_NF_ND:
15494 case SHR8m1:
15495 case SHR8m1_EVEX:
15496 case SHR8m1_ND:
15497 case SHR8m1_NF:
15498 case SHR8m1_NF_ND:
15499 case SHR8mCL:
15500 case SHR8mCL_EVEX:
15501 case SHR8mCL_ND:
15502 case SHR8mCL_NF:
15503 case SHR8mCL_NF_ND:
15504 case SHR8mi:
15505 case SHR8mi_EVEX:
15506 case SHR8mi_ND:
15507 case SHR8mi_NF:
15508 case SHR8mi_NF_ND:
15509 case SHR8r1:
15510 case SHR8r1_EVEX:
15511 case SHR8r1_ND:
15512 case SHR8r1_NF:
15513 case SHR8r1_NF_ND:
15514 case SHR8rCL:
15515 case SHR8rCL_EVEX:
15516 case SHR8rCL_ND:
15517 case SHR8rCL_NF:
15518 case SHR8rCL_NF_ND:
15519 case SHR8ri:
15520 case SHR8ri_EVEX:
15521 case SHR8ri_ND:
15522 case SHR8ri_NF:
15523 case SHR8ri_NF_ND:
15524 return true;
15525 }
15526 return false;
15527}
15528
15529bool isLOOPNE(unsigned Opcode) {
15530 return Opcode == LOOPNE;
15531}
15532
15533bool isVCVTTPH2UQQ(unsigned Opcode) {
15534 switch (Opcode) {
15535 case VCVTTPH2UQQZ128rm:
15536 case VCVTTPH2UQQZ128rmb:
15537 case VCVTTPH2UQQZ128rmbk:
15538 case VCVTTPH2UQQZ128rmbkz:
15539 case VCVTTPH2UQQZ128rmk:
15540 case VCVTTPH2UQQZ128rmkz:
15541 case VCVTTPH2UQQZ128rr:
15542 case VCVTTPH2UQQZ128rrk:
15543 case VCVTTPH2UQQZ128rrkz:
15544 case VCVTTPH2UQQZ256rm:
15545 case VCVTTPH2UQQZ256rmb:
15546 case VCVTTPH2UQQZ256rmbk:
15547 case VCVTTPH2UQQZ256rmbkz:
15548 case VCVTTPH2UQQZ256rmk:
15549 case VCVTTPH2UQQZ256rmkz:
15550 case VCVTTPH2UQQZ256rr:
15551 case VCVTTPH2UQQZ256rrk:
15552 case VCVTTPH2UQQZ256rrkz:
15553 case VCVTTPH2UQQZrm:
15554 case VCVTTPH2UQQZrmb:
15555 case VCVTTPH2UQQZrmbk:
15556 case VCVTTPH2UQQZrmbkz:
15557 case VCVTTPH2UQQZrmk:
15558 case VCVTTPH2UQQZrmkz:
15559 case VCVTTPH2UQQZrr:
15560 case VCVTTPH2UQQZrrb:
15561 case VCVTTPH2UQQZrrbk:
15562 case VCVTTPH2UQQZrrbkz:
15563 case VCVTTPH2UQQZrrk:
15564 case VCVTTPH2UQQZrrkz:
15565 return true;
15566 }
15567 return false;
15568}
15569
15570bool isSHA1NEXTE(unsigned Opcode) {
15571 switch (Opcode) {
15572 case SHA1NEXTErm:
15573 case SHA1NEXTErr:
15574 return true;
15575 }
15576 return false;
15577}
15578
15579bool isVFMADD132SD(unsigned Opcode) {
15580 switch (Opcode) {
15581 case VFMADD132SDZm_Int:
15582 case VFMADD132SDZmk_Int:
15583 case VFMADD132SDZmkz_Int:
15584 case VFMADD132SDZr_Int:
15585 case VFMADD132SDZrb_Int:
15586 case VFMADD132SDZrbk_Int:
15587 case VFMADD132SDZrbkz_Int:
15588 case VFMADD132SDZrk_Int:
15589 case VFMADD132SDZrkz_Int:
15590 case VFMADD132SDm_Int:
15591 case VFMADD132SDr_Int:
15592 return true;
15593 }
15594 return false;
15595}
15596
15597bool isPSRAW(unsigned Opcode) {
15598 switch (Opcode) {
15599 case MMX_PSRAWri:
15600 case MMX_PSRAWrm:
15601 case MMX_PSRAWrr:
15602 case PSRAWri:
15603 case PSRAWrm:
15604 case PSRAWrr:
15605 return true;
15606 }
15607 return false;
15608}
15609
15610bool isVPBROADCASTQ(unsigned Opcode) {
15611 switch (Opcode) {
15612 case VPBROADCASTQYrm:
15613 case VPBROADCASTQYrr:
15614 case VPBROADCASTQZ128rm:
15615 case VPBROADCASTQZ128rmk:
15616 case VPBROADCASTQZ128rmkz:
15617 case VPBROADCASTQZ128rr:
15618 case VPBROADCASTQZ128rrk:
15619 case VPBROADCASTQZ128rrkz:
15620 case VPBROADCASTQZ256rm:
15621 case VPBROADCASTQZ256rmk:
15622 case VPBROADCASTQZ256rmkz:
15623 case VPBROADCASTQZ256rr:
15624 case VPBROADCASTQZ256rrk:
15625 case VPBROADCASTQZ256rrkz:
15626 case VPBROADCASTQZrm:
15627 case VPBROADCASTQZrmk:
15628 case VPBROADCASTQZrmkz:
15629 case VPBROADCASTQZrr:
15630 case VPBROADCASTQZrrk:
15631 case VPBROADCASTQZrrkz:
15632 case VPBROADCASTQrZ128rr:
15633 case VPBROADCASTQrZ128rrk:
15634 case VPBROADCASTQrZ128rrkz:
15635 case VPBROADCASTQrZ256rr:
15636 case VPBROADCASTQrZ256rrk:
15637 case VPBROADCASTQrZ256rrkz:
15638 case VPBROADCASTQrZrr:
15639 case VPBROADCASTQrZrrk:
15640 case VPBROADCASTQrZrrkz:
15641 case VPBROADCASTQrm:
15642 case VPBROADCASTQrr:
15643 return true;
15644 }
15645 return false;
15646}
15647
15648bool isCLC(unsigned Opcode) {
15649 return Opcode == CLC;
15650}
15651
15652bool isPOPAW(unsigned Opcode) {
15653 return Opcode == POPA16;
15654}
15655
15656bool isTCMMIMFP16PS(unsigned Opcode) {
15657 return Opcode == TCMMIMFP16PS;
15658}
15659
15660bool isVCVTQQ2PH(unsigned Opcode) {
15661 switch (Opcode) {
15662 case VCVTQQ2PHZ128rm:
15663 case VCVTQQ2PHZ128rmb:
15664 case VCVTQQ2PHZ128rmbk:
15665 case VCVTQQ2PHZ128rmbkz:
15666 case VCVTQQ2PHZ128rmk:
15667 case VCVTQQ2PHZ128rmkz:
15668 case VCVTQQ2PHZ128rr:
15669 case VCVTQQ2PHZ128rrk:
15670 case VCVTQQ2PHZ128rrkz:
15671 case VCVTQQ2PHZ256rm:
15672 case VCVTQQ2PHZ256rmb:
15673 case VCVTQQ2PHZ256rmbk:
15674 case VCVTQQ2PHZ256rmbkz:
15675 case VCVTQQ2PHZ256rmk:
15676 case VCVTQQ2PHZ256rmkz:
15677 case VCVTQQ2PHZ256rr:
15678 case VCVTQQ2PHZ256rrk:
15679 case VCVTQQ2PHZ256rrkz:
15680 case VCVTQQ2PHZrm:
15681 case VCVTQQ2PHZrmb:
15682 case VCVTQQ2PHZrmbk:
15683 case VCVTQQ2PHZrmbkz:
15684 case VCVTQQ2PHZrmk:
15685 case VCVTQQ2PHZrmkz:
15686 case VCVTQQ2PHZrr:
15687 case VCVTQQ2PHZrrb:
15688 case VCVTQQ2PHZrrbk:
15689 case VCVTQQ2PHZrrbkz:
15690 case VCVTQQ2PHZrrk:
15691 case VCVTQQ2PHZrrkz:
15692 return true;
15693 }
15694 return false;
15695}
15696
15697bool isVCVTTPS2UQQ(unsigned Opcode) {
15698 switch (Opcode) {
15699 case VCVTTPS2UQQZ128rm:
15700 case VCVTTPS2UQQZ128rmb:
15701 case VCVTTPS2UQQZ128rmbk:
15702 case VCVTTPS2UQQZ128rmbkz:
15703 case VCVTTPS2UQQZ128rmk:
15704 case VCVTTPS2UQQZ128rmkz:
15705 case VCVTTPS2UQQZ128rr:
15706 case VCVTTPS2UQQZ128rrk:
15707 case VCVTTPS2UQQZ128rrkz:
15708 case VCVTTPS2UQQZ256rm:
15709 case VCVTTPS2UQQZ256rmb:
15710 case VCVTTPS2UQQZ256rmbk:
15711 case VCVTTPS2UQQZ256rmbkz:
15712 case VCVTTPS2UQQZ256rmk:
15713 case VCVTTPS2UQQZ256rmkz:
15714 case VCVTTPS2UQQZ256rr:
15715 case VCVTTPS2UQQZ256rrk:
15716 case VCVTTPS2UQQZ256rrkz:
15717 case VCVTTPS2UQQZrm:
15718 case VCVTTPS2UQQZrmb:
15719 case VCVTTPS2UQQZrmbk:
15720 case VCVTTPS2UQQZrmbkz:
15721 case VCVTTPS2UQQZrmk:
15722 case VCVTTPS2UQQZrmkz:
15723 case VCVTTPS2UQQZrr:
15724 case VCVTTPS2UQQZrrb:
15725 case VCVTTPS2UQQZrrbk:
15726 case VCVTTPS2UQQZrrbkz:
15727 case VCVTTPS2UQQZrrk:
15728 case VCVTTPS2UQQZrrkz:
15729 return true;
15730 }
15731 return false;
15732}
15733
15734bool isVMOVUPD(unsigned Opcode) {
15735 switch (Opcode) {
15736 case VMOVUPDYmr:
15737 case VMOVUPDYrm:
15738 case VMOVUPDYrr:
15739 case VMOVUPDYrr_REV:
15740 case VMOVUPDZ128mr:
15741 case VMOVUPDZ128mrk:
15742 case VMOVUPDZ128rm:
15743 case VMOVUPDZ128rmk:
15744 case VMOVUPDZ128rmkz:
15745 case VMOVUPDZ128rr:
15746 case VMOVUPDZ128rr_REV:
15747 case VMOVUPDZ128rrk:
15748 case VMOVUPDZ128rrk_REV:
15749 case VMOVUPDZ128rrkz:
15750 case VMOVUPDZ128rrkz_REV:
15751 case VMOVUPDZ256mr:
15752 case VMOVUPDZ256mrk:
15753 case VMOVUPDZ256rm:
15754 case VMOVUPDZ256rmk:
15755 case VMOVUPDZ256rmkz:
15756 case VMOVUPDZ256rr:
15757 case VMOVUPDZ256rr_REV:
15758 case VMOVUPDZ256rrk:
15759 case VMOVUPDZ256rrk_REV:
15760 case VMOVUPDZ256rrkz:
15761 case VMOVUPDZ256rrkz_REV:
15762 case VMOVUPDZmr:
15763 case VMOVUPDZmrk:
15764 case VMOVUPDZrm:
15765 case VMOVUPDZrmk:
15766 case VMOVUPDZrmkz:
15767 case VMOVUPDZrr:
15768 case VMOVUPDZrr_REV:
15769 case VMOVUPDZrrk:
15770 case VMOVUPDZrrk_REV:
15771 case VMOVUPDZrrkz:
15772 case VMOVUPDZrrkz_REV:
15773 case VMOVUPDmr:
15774 case VMOVUPDrm:
15775 case VMOVUPDrr:
15776 case VMOVUPDrr_REV:
15777 return true;
15778 }
15779 return false;
15780}
15781
15782bool isFPTAN(unsigned Opcode) {
15783 return Opcode == FPTAN;
15784}
15785
15786bool isVMASKMOVPD(unsigned Opcode) {
15787 switch (Opcode) {
15788 case VMASKMOVPDYmr:
15789 case VMASKMOVPDYrm:
15790 case VMASKMOVPDmr:
15791 case VMASKMOVPDrm:
15792 return true;
15793 }
15794 return false;
15795}
15796
15797bool isVMOVLHPS(unsigned Opcode) {
15798 switch (Opcode) {
15799 case VMOVLHPSZrr:
15800 case VMOVLHPSrr:
15801 return true;
15802 }
15803 return false;
15804}
15805
15806bool isAESKEYGENASSIST(unsigned Opcode) {
15807 switch (Opcode) {
15808 case AESKEYGENASSISTrmi:
15809 case AESKEYGENASSISTrri:
15810 return true;
15811 }
15812 return false;
15813}
15814
15815bool isXSAVEOPT64(unsigned Opcode) {
15816 return Opcode == XSAVEOPT64;
15817}
15818
15819bool isXSAVEC(unsigned Opcode) {
15820 return Opcode == XSAVEC;
15821}
15822
15823bool isVPLZCNTQ(unsigned Opcode) {
15824 switch (Opcode) {
15825 case VPLZCNTQZ128rm:
15826 case VPLZCNTQZ128rmb:
15827 case VPLZCNTQZ128rmbk:
15828 case VPLZCNTQZ128rmbkz:
15829 case VPLZCNTQZ128rmk:
15830 case VPLZCNTQZ128rmkz:
15831 case VPLZCNTQZ128rr:
15832 case VPLZCNTQZ128rrk:
15833 case VPLZCNTQZ128rrkz:
15834 case VPLZCNTQZ256rm:
15835 case VPLZCNTQZ256rmb:
15836 case VPLZCNTQZ256rmbk:
15837 case VPLZCNTQZ256rmbkz:
15838 case VPLZCNTQZ256rmk:
15839 case VPLZCNTQZ256rmkz:
15840 case VPLZCNTQZ256rr:
15841 case VPLZCNTQZ256rrk:
15842 case VPLZCNTQZ256rrkz:
15843 case VPLZCNTQZrm:
15844 case VPLZCNTQZrmb:
15845 case VPLZCNTQZrmbk:
15846 case VPLZCNTQZrmbkz:
15847 case VPLZCNTQZrmk:
15848 case VPLZCNTQZrmkz:
15849 case VPLZCNTQZrr:
15850 case VPLZCNTQZrrk:
15851 case VPLZCNTQZrrkz:
15852 return true;
15853 }
15854 return false;
15855}
15856
15857bool isVPSUBW(unsigned Opcode) {
15858 switch (Opcode) {
15859 case VPSUBWYrm:
15860 case VPSUBWYrr:
15861 case VPSUBWZ128rm:
15862 case VPSUBWZ128rmk:
15863 case VPSUBWZ128rmkz:
15864 case VPSUBWZ128rr:
15865 case VPSUBWZ128rrk:
15866 case VPSUBWZ128rrkz:
15867 case VPSUBWZ256rm:
15868 case VPSUBWZ256rmk:
15869 case VPSUBWZ256rmkz:
15870 case VPSUBWZ256rr:
15871 case VPSUBWZ256rrk:
15872 case VPSUBWZ256rrkz:
15873 case VPSUBWZrm:
15874 case VPSUBWZrmk:
15875 case VPSUBWZrmkz:
15876 case VPSUBWZrr:
15877 case VPSUBWZrrk:
15878 case VPSUBWZrrkz:
15879 case VPSUBWrm:
15880 case VPSUBWrr:
15881 return true;
15882 }
15883 return false;
15884}
15885
15886bool isCMPCCXADD(unsigned Opcode) {
15887 switch (Opcode) {
15888 case CMPCCXADDmr32:
15889 case CMPCCXADDmr32_EVEX:
15890 case CMPCCXADDmr64:
15891 case CMPCCXADDmr64_EVEX:
15892 return true;
15893 }
15894 return false;
15895}
15896
15897bool isVFMSUBADD213PH(unsigned Opcode) {
15898 switch (Opcode) {
15899 case VFMSUBADD213PHZ128m:
15900 case VFMSUBADD213PHZ128mb:
15901 case VFMSUBADD213PHZ128mbk:
15902 case VFMSUBADD213PHZ128mbkz:
15903 case VFMSUBADD213PHZ128mk:
15904 case VFMSUBADD213PHZ128mkz:
15905 case VFMSUBADD213PHZ128r:
15906 case VFMSUBADD213PHZ128rk:
15907 case VFMSUBADD213PHZ128rkz:
15908 case VFMSUBADD213PHZ256m:
15909 case VFMSUBADD213PHZ256mb:
15910 case VFMSUBADD213PHZ256mbk:
15911 case VFMSUBADD213PHZ256mbkz:
15912 case VFMSUBADD213PHZ256mk:
15913 case VFMSUBADD213PHZ256mkz:
15914 case VFMSUBADD213PHZ256r:
15915 case VFMSUBADD213PHZ256rk:
15916 case VFMSUBADD213PHZ256rkz:
15917 case VFMSUBADD213PHZm:
15918 case VFMSUBADD213PHZmb:
15919 case VFMSUBADD213PHZmbk:
15920 case VFMSUBADD213PHZmbkz:
15921 case VFMSUBADD213PHZmk:
15922 case VFMSUBADD213PHZmkz:
15923 case VFMSUBADD213PHZr:
15924 case VFMSUBADD213PHZrb:
15925 case VFMSUBADD213PHZrbk:
15926 case VFMSUBADD213PHZrbkz:
15927 case VFMSUBADD213PHZrk:
15928 case VFMSUBADD213PHZrkz:
15929 return true;
15930 }
15931 return false;
15932}
15933
15934bool isVFMADDSUBPD(unsigned Opcode) {
15935 switch (Opcode) {
15936 case VFMADDSUBPD4Ymr:
15937 case VFMADDSUBPD4Yrm:
15938 case VFMADDSUBPD4Yrr:
15939 case VFMADDSUBPD4Yrr_REV:
15940 case VFMADDSUBPD4mr:
15941 case VFMADDSUBPD4rm:
15942 case VFMADDSUBPD4rr:
15943 case VFMADDSUBPD4rr_REV:
15944 return true;
15945 }
15946 return false;
15947}
15948
15949bool isVPMINSW(unsigned Opcode) {
15950 switch (Opcode) {
15951 case VPMINSWYrm:
15952 case VPMINSWYrr:
15953 case VPMINSWZ128rm:
15954 case VPMINSWZ128rmk:
15955 case VPMINSWZ128rmkz:
15956 case VPMINSWZ128rr:
15957 case VPMINSWZ128rrk:
15958 case VPMINSWZ128rrkz:
15959 case VPMINSWZ256rm:
15960 case VPMINSWZ256rmk:
15961 case VPMINSWZ256rmkz:
15962 case VPMINSWZ256rr:
15963 case VPMINSWZ256rrk:
15964 case VPMINSWZ256rrkz:
15965 case VPMINSWZrm:
15966 case VPMINSWZrmk:
15967 case VPMINSWZrmkz:
15968 case VPMINSWZrr:
15969 case VPMINSWZrrk:
15970 case VPMINSWZrrkz:
15971 case VPMINSWrm:
15972 case VPMINSWrr:
15973 return true;
15974 }
15975 return false;
15976}
15977
15978bool isVFNMSUB132PS(unsigned Opcode) {
15979 switch (Opcode) {
15980 case VFNMSUB132PSYm:
15981 case VFNMSUB132PSYr:
15982 case VFNMSUB132PSZ128m:
15983 case VFNMSUB132PSZ128mb:
15984 case VFNMSUB132PSZ128mbk:
15985 case VFNMSUB132PSZ128mbkz:
15986 case VFNMSUB132PSZ128mk:
15987 case VFNMSUB132PSZ128mkz:
15988 case VFNMSUB132PSZ128r:
15989 case VFNMSUB132PSZ128rk:
15990 case VFNMSUB132PSZ128rkz:
15991 case VFNMSUB132PSZ256m:
15992 case VFNMSUB132PSZ256mb:
15993 case VFNMSUB132PSZ256mbk:
15994 case VFNMSUB132PSZ256mbkz:
15995 case VFNMSUB132PSZ256mk:
15996 case VFNMSUB132PSZ256mkz:
15997 case VFNMSUB132PSZ256r:
15998 case VFNMSUB132PSZ256rk:
15999 case VFNMSUB132PSZ256rkz:
16000 case VFNMSUB132PSZm:
16001 case VFNMSUB132PSZmb:
16002 case VFNMSUB132PSZmbk:
16003 case VFNMSUB132PSZmbkz:
16004 case VFNMSUB132PSZmk:
16005 case VFNMSUB132PSZmkz:
16006 case VFNMSUB132PSZr:
16007 case VFNMSUB132PSZrb:
16008 case VFNMSUB132PSZrbk:
16009 case VFNMSUB132PSZrbkz:
16010 case VFNMSUB132PSZrk:
16011 case VFNMSUB132PSZrkz:
16012 case VFNMSUB132PSm:
16013 case VFNMSUB132PSr:
16014 return true;
16015 }
16016 return false;
16017}
16018
16019bool isVMOVAPS(unsigned Opcode) {
16020 switch (Opcode) {
16021 case VMOVAPSYmr:
16022 case VMOVAPSYrm:
16023 case VMOVAPSYrr:
16024 case VMOVAPSYrr_REV:
16025 case VMOVAPSZ128mr:
16026 case VMOVAPSZ128mrk:
16027 case VMOVAPSZ128rm:
16028 case VMOVAPSZ128rmk:
16029 case VMOVAPSZ128rmkz:
16030 case VMOVAPSZ128rr:
16031 case VMOVAPSZ128rr_REV:
16032 case VMOVAPSZ128rrk:
16033 case VMOVAPSZ128rrk_REV:
16034 case VMOVAPSZ128rrkz:
16035 case VMOVAPSZ128rrkz_REV:
16036 case VMOVAPSZ256mr:
16037 case VMOVAPSZ256mrk:
16038 case VMOVAPSZ256rm:
16039 case VMOVAPSZ256rmk:
16040 case VMOVAPSZ256rmkz:
16041 case VMOVAPSZ256rr:
16042 case VMOVAPSZ256rr_REV:
16043 case VMOVAPSZ256rrk:
16044 case VMOVAPSZ256rrk_REV:
16045 case VMOVAPSZ256rrkz:
16046 case VMOVAPSZ256rrkz_REV:
16047 case VMOVAPSZmr:
16048 case VMOVAPSZmrk:
16049 case VMOVAPSZrm:
16050 case VMOVAPSZrmk:
16051 case VMOVAPSZrmkz:
16052 case VMOVAPSZrr:
16053 case VMOVAPSZrr_REV:
16054 case VMOVAPSZrrk:
16055 case VMOVAPSZrrk_REV:
16056 case VMOVAPSZrrkz:
16057 case VMOVAPSZrrkz_REV:
16058 case VMOVAPSmr:
16059 case VMOVAPSrm:
16060 case VMOVAPSrr:
16061 case VMOVAPSrr_REV:
16062 return true;
16063 }
16064 return false;
16065}
16066
16067bool isVPEXTRQ(unsigned Opcode) {
16068 switch (Opcode) {
16069 case VPEXTRQZmri:
16070 case VPEXTRQZrri:
16071 case VPEXTRQmri:
16072 case VPEXTRQrri:
16073 return true;
16074 }
16075 return false;
16076}
16077
16078bool isVSCALEFSH(unsigned Opcode) {
16079 switch (Opcode) {
16080 case VSCALEFSHZrm:
16081 case VSCALEFSHZrmk:
16082 case VSCALEFSHZrmkz:
16083 case VSCALEFSHZrr:
16084 case VSCALEFSHZrrb_Int:
16085 case VSCALEFSHZrrbk_Int:
16086 case VSCALEFSHZrrbkz_Int:
16087 case VSCALEFSHZrrk:
16088 case VSCALEFSHZrrkz:
16089 return true;
16090 }
16091 return false;
16092}
16093
16094bool isVCVTPD2PS(unsigned Opcode) {
16095 switch (Opcode) {
16096 case VCVTPD2PSYrm:
16097 case VCVTPD2PSYrr:
16098 case VCVTPD2PSZ128rm:
16099 case VCVTPD2PSZ128rmb:
16100 case VCVTPD2PSZ128rmbk:
16101 case VCVTPD2PSZ128rmbkz:
16102 case VCVTPD2PSZ128rmk:
16103 case VCVTPD2PSZ128rmkz:
16104 case VCVTPD2PSZ128rr:
16105 case VCVTPD2PSZ128rrk:
16106 case VCVTPD2PSZ128rrkz:
16107 case VCVTPD2PSZ256rm:
16108 case VCVTPD2PSZ256rmb:
16109 case VCVTPD2PSZ256rmbk:
16110 case VCVTPD2PSZ256rmbkz:
16111 case VCVTPD2PSZ256rmk:
16112 case VCVTPD2PSZ256rmkz:
16113 case VCVTPD2PSZ256rr:
16114 case VCVTPD2PSZ256rrk:
16115 case VCVTPD2PSZ256rrkz:
16116 case VCVTPD2PSZrm:
16117 case VCVTPD2PSZrmb:
16118 case VCVTPD2PSZrmbk:
16119 case VCVTPD2PSZrmbkz:
16120 case VCVTPD2PSZrmk:
16121 case VCVTPD2PSZrmkz:
16122 case VCVTPD2PSZrr:
16123 case VCVTPD2PSZrrb:
16124 case VCVTPD2PSZrrbk:
16125 case VCVTPD2PSZrrbkz:
16126 case VCVTPD2PSZrrk:
16127 case VCVTPD2PSZrrkz:
16128 case VCVTPD2PSrm:
16129 case VCVTPD2PSrr:
16130 return true;
16131 }
16132 return false;
16133}
16134
16135bool isCLGI(unsigned Opcode) {
16136 return Opcode == CLGI;
16137}
16138
16139bool isVAESDEC(unsigned Opcode) {
16140 switch (Opcode) {
16141 case VAESDECYrm:
16142 case VAESDECYrr:
16143 case VAESDECZ128rm:
16144 case VAESDECZ128rr:
16145 case VAESDECZ256rm:
16146 case VAESDECZ256rr:
16147 case VAESDECZrm:
16148 case VAESDECZrr:
16149 case VAESDECrm:
16150 case VAESDECrr:
16151 return true;
16152 }
16153 return false;
16154}
16155
16156bool isPFMUL(unsigned Opcode) {
16157 switch (Opcode) {
16158 case PFMULrm:
16159 case PFMULrr:
16160 return true;
16161 }
16162 return false;
16163}
16164
16165bool isVCVTBIASPH2BF8S(unsigned Opcode) {
16166 switch (Opcode) {
16167 case VCVTBIASPH2BF8SZ128rm:
16168 case VCVTBIASPH2BF8SZ128rmb:
16169 case VCVTBIASPH2BF8SZ128rmbk:
16170 case VCVTBIASPH2BF8SZ128rmbkz:
16171 case VCVTBIASPH2BF8SZ128rmk:
16172 case VCVTBIASPH2BF8SZ128rmkz:
16173 case VCVTBIASPH2BF8SZ128rr:
16174 case VCVTBIASPH2BF8SZ128rrk:
16175 case VCVTBIASPH2BF8SZ128rrkz:
16176 case VCVTBIASPH2BF8SZ256rm:
16177 case VCVTBIASPH2BF8SZ256rmb:
16178 case VCVTBIASPH2BF8SZ256rmbk:
16179 case VCVTBIASPH2BF8SZ256rmbkz:
16180 case VCVTBIASPH2BF8SZ256rmk:
16181 case VCVTBIASPH2BF8SZ256rmkz:
16182 case VCVTBIASPH2BF8SZ256rr:
16183 case VCVTBIASPH2BF8SZ256rrk:
16184 case VCVTBIASPH2BF8SZ256rrkz:
16185 case VCVTBIASPH2BF8SZrm:
16186 case VCVTBIASPH2BF8SZrmb:
16187 case VCVTBIASPH2BF8SZrmbk:
16188 case VCVTBIASPH2BF8SZrmbkz:
16189 case VCVTBIASPH2BF8SZrmk:
16190 case VCVTBIASPH2BF8SZrmkz:
16191 case VCVTBIASPH2BF8SZrr:
16192 case VCVTBIASPH2BF8SZrrk:
16193 case VCVTBIASPH2BF8SZrrkz:
16194 return true;
16195 }
16196 return false;
16197}
16198
16199bool isMOVDIRI(unsigned Opcode) {
16200 switch (Opcode) {
16201 case MOVDIRI32:
16202 case MOVDIRI32_EVEX:
16203 case MOVDIRI64:
16204 case MOVDIRI64_EVEX:
16205 return true;
16206 }
16207 return false;
16208}
16209
16210bool isSHUFPS(unsigned Opcode) {
16211 switch (Opcode) {
16212 case SHUFPSrmi:
16213 case SHUFPSrri:
16214 return true;
16215 }
16216 return false;
16217}
16218
16219bool isVFNMSUB231SS(unsigned Opcode) {
16220 switch (Opcode) {
16221 case VFNMSUB231SSZm_Int:
16222 case VFNMSUB231SSZmk_Int:
16223 case VFNMSUB231SSZmkz_Int:
16224 case VFNMSUB231SSZr_Int:
16225 case VFNMSUB231SSZrb_Int:
16226 case VFNMSUB231SSZrbk_Int:
16227 case VFNMSUB231SSZrbkz_Int:
16228 case VFNMSUB231SSZrk_Int:
16229 case VFNMSUB231SSZrkz_Int:
16230 case VFNMSUB231SSm_Int:
16231 case VFNMSUB231SSr_Int:
16232 return true;
16233 }
16234 return false;
16235}
16236
16237bool isVMWRITE(unsigned Opcode) {
16238 switch (Opcode) {
16239 case VMWRITE32rm:
16240 case VMWRITE32rr:
16241 case VMWRITE64rm:
16242 case VMWRITE64rr:
16243 return true;
16244 }
16245 return false;
16246}
16247
16248bool isVINSERTF128(unsigned Opcode) {
16249 switch (Opcode) {
16250 case VINSERTF128rmi:
16251 case VINSERTF128rri:
16252 return true;
16253 }
16254 return false;
16255}
16256
16257bool isFISUBR(unsigned Opcode) {
16258 switch (Opcode) {
16259 case SUBR_FI16m:
16260 case SUBR_FI32m:
16261 return true;
16262 }
16263 return false;
16264}
16265
16266bool isVINSERTI32X4(unsigned Opcode) {
16267 switch (Opcode) {
16268 case VINSERTI32X4Z256rmi:
16269 case VINSERTI32X4Z256rmik:
16270 case VINSERTI32X4Z256rmikz:
16271 case VINSERTI32X4Z256rri:
16272 case VINSERTI32X4Z256rrik:
16273 case VINSERTI32X4Z256rrikz:
16274 case VINSERTI32X4Zrmi:
16275 case VINSERTI32X4Zrmik:
16276 case VINSERTI32X4Zrmikz:
16277 case VINSERTI32X4Zrri:
16278 case VINSERTI32X4Zrrik:
16279 case VINSERTI32X4Zrrikz:
16280 return true;
16281 }
16282 return false;
16283}
16284
16285bool isVPSLLDQ(unsigned Opcode) {
16286 switch (Opcode) {
16287 case VPSLLDQYri:
16288 case VPSLLDQZ128mi:
16289 case VPSLLDQZ128ri:
16290 case VPSLLDQZ256mi:
16291 case VPSLLDQZ256ri:
16292 case VPSLLDQZmi:
16293 case VPSLLDQZri:
16294 case VPSLLDQri:
16295 return true;
16296 }
16297 return false;
16298}
16299
16300bool isPOPCNT(unsigned Opcode) {
16301 switch (Opcode) {
16302 case POPCNT16rm:
16303 case POPCNT16rm_EVEX:
16304 case POPCNT16rm_NF:
16305 case POPCNT16rr:
16306 case POPCNT16rr_EVEX:
16307 case POPCNT16rr_NF:
16308 case POPCNT32rm:
16309 case POPCNT32rm_EVEX:
16310 case POPCNT32rm_NF:
16311 case POPCNT32rr:
16312 case POPCNT32rr_EVEX:
16313 case POPCNT32rr_NF:
16314 case POPCNT64rm:
16315 case POPCNT64rm_EVEX:
16316 case POPCNT64rm_NF:
16317 case POPCNT64rr:
16318 case POPCNT64rr_EVEX:
16319 case POPCNT64rr_NF:
16320 return true;
16321 }
16322 return false;
16323}
16324
16325bool isVXORPD(unsigned Opcode) {
16326 switch (Opcode) {
16327 case VXORPDYrm:
16328 case VXORPDYrr:
16329 case VXORPDZ128rm:
16330 case VXORPDZ128rmb:
16331 case VXORPDZ128rmbk:
16332 case VXORPDZ128rmbkz:
16333 case VXORPDZ128rmk:
16334 case VXORPDZ128rmkz:
16335 case VXORPDZ128rr:
16336 case VXORPDZ128rrk:
16337 case VXORPDZ128rrkz:
16338 case VXORPDZ256rm:
16339 case VXORPDZ256rmb:
16340 case VXORPDZ256rmbk:
16341 case VXORPDZ256rmbkz:
16342 case VXORPDZ256rmk:
16343 case VXORPDZ256rmkz:
16344 case VXORPDZ256rr:
16345 case VXORPDZ256rrk:
16346 case VXORPDZ256rrkz:
16347 case VXORPDZrm:
16348 case VXORPDZrmb:
16349 case VXORPDZrmbk:
16350 case VXORPDZrmbkz:
16351 case VXORPDZrmk:
16352 case VXORPDZrmkz:
16353 case VXORPDZrr:
16354 case VXORPDZrrk:
16355 case VXORPDZrrkz:
16356 case VXORPDrm:
16357 case VXORPDrr:
16358 return true;
16359 }
16360 return false;
16361}
16362
16363bool isXLATB(unsigned Opcode) {
16364 return Opcode == XLAT;
16365}
16366
16367bool isDIV(unsigned Opcode) {
16368 switch (Opcode) {
16369 case DIV16m:
16370 case DIV16m_EVEX:
16371 case DIV16m_NF:
16372 case DIV16r:
16373 case DIV16r_EVEX:
16374 case DIV16r_NF:
16375 case DIV32m:
16376 case DIV32m_EVEX:
16377 case DIV32m_NF:
16378 case DIV32r:
16379 case DIV32r_EVEX:
16380 case DIV32r_NF:
16381 case DIV64m:
16382 case DIV64m_EVEX:
16383 case DIV64m_NF:
16384 case DIV64r:
16385 case DIV64r_EVEX:
16386 case DIV64r_NF:
16387 case DIV8m:
16388 case DIV8m_EVEX:
16389 case DIV8m_NF:
16390 case DIV8r:
16391 case DIV8r_EVEX:
16392 case DIV8r_NF:
16393 return true;
16394 }
16395 return false;
16396}
16397
16398bool isVPSHLDVQ(unsigned Opcode) {
16399 switch (Opcode) {
16400 case VPSHLDVQZ128m:
16401 case VPSHLDVQZ128mb:
16402 case VPSHLDVQZ128mbk:
16403 case VPSHLDVQZ128mbkz:
16404 case VPSHLDVQZ128mk:
16405 case VPSHLDVQZ128mkz:
16406 case VPSHLDVQZ128r:
16407 case VPSHLDVQZ128rk:
16408 case VPSHLDVQZ128rkz:
16409 case VPSHLDVQZ256m:
16410 case VPSHLDVQZ256mb:
16411 case VPSHLDVQZ256mbk:
16412 case VPSHLDVQZ256mbkz:
16413 case VPSHLDVQZ256mk:
16414 case VPSHLDVQZ256mkz:
16415 case VPSHLDVQZ256r:
16416 case VPSHLDVQZ256rk:
16417 case VPSHLDVQZ256rkz:
16418 case VPSHLDVQZm:
16419 case VPSHLDVQZmb:
16420 case VPSHLDVQZmbk:
16421 case VPSHLDVQZmbkz:
16422 case VPSHLDVQZmk:
16423 case VPSHLDVQZmkz:
16424 case VPSHLDVQZr:
16425 case VPSHLDVQZrk:
16426 case VPSHLDVQZrkz:
16427 return true;
16428 }
16429 return false;
16430}
16431
16432bool isMOVDDUP(unsigned Opcode) {
16433 switch (Opcode) {
16434 case MOVDDUPrm:
16435 case MOVDDUPrr:
16436 return true;
16437 }
16438 return false;
16439}
16440
16441bool isVMOVDQU64(unsigned Opcode) {
16442 switch (Opcode) {
16443 case VMOVDQU64Z128mr:
16444 case VMOVDQU64Z128mrk:
16445 case VMOVDQU64Z128rm:
16446 case VMOVDQU64Z128rmk:
16447 case VMOVDQU64Z128rmkz:
16448 case VMOVDQU64Z128rr:
16449 case VMOVDQU64Z128rr_REV:
16450 case VMOVDQU64Z128rrk:
16451 case VMOVDQU64Z128rrk_REV:
16452 case VMOVDQU64Z128rrkz:
16453 case VMOVDQU64Z128rrkz_REV:
16454 case VMOVDQU64Z256mr:
16455 case VMOVDQU64Z256mrk:
16456 case VMOVDQU64Z256rm:
16457 case VMOVDQU64Z256rmk:
16458 case VMOVDQU64Z256rmkz:
16459 case VMOVDQU64Z256rr:
16460 case VMOVDQU64Z256rr_REV:
16461 case VMOVDQU64Z256rrk:
16462 case VMOVDQU64Z256rrk_REV:
16463 case VMOVDQU64Z256rrkz:
16464 case VMOVDQU64Z256rrkz_REV:
16465 case VMOVDQU64Zmr:
16466 case VMOVDQU64Zmrk:
16467 case VMOVDQU64Zrm:
16468 case VMOVDQU64Zrmk:
16469 case VMOVDQU64Zrmkz:
16470 case VMOVDQU64Zrr:
16471 case VMOVDQU64Zrr_REV:
16472 case VMOVDQU64Zrrk:
16473 case VMOVDQU64Zrrk_REV:
16474 case VMOVDQU64Zrrkz:
16475 case VMOVDQU64Zrrkz_REV:
16476 return true;
16477 }
16478 return false;
16479}
16480
16481bool isVPCOMPRESSQ(unsigned Opcode) {
16482 switch (Opcode) {
16483 case VPCOMPRESSQZ128mr:
16484 case VPCOMPRESSQZ128mrk:
16485 case VPCOMPRESSQZ128rr:
16486 case VPCOMPRESSQZ128rrk:
16487 case VPCOMPRESSQZ128rrkz:
16488 case VPCOMPRESSQZ256mr:
16489 case VPCOMPRESSQZ256mrk:
16490 case VPCOMPRESSQZ256rr:
16491 case VPCOMPRESSQZ256rrk:
16492 case VPCOMPRESSQZ256rrkz:
16493 case VPCOMPRESSQZmr:
16494 case VPCOMPRESSQZmrk:
16495 case VPCOMPRESSQZrr:
16496 case VPCOMPRESSQZrrk:
16497 case VPCOMPRESSQZrrkz:
16498 return true;
16499 }
16500 return false;
16501}
16502
16503bool isVFMSUBADD132PD(unsigned Opcode) {
16504 switch (Opcode) {
16505 case VFMSUBADD132PDYm:
16506 case VFMSUBADD132PDYr:
16507 case VFMSUBADD132PDZ128m:
16508 case VFMSUBADD132PDZ128mb:
16509 case VFMSUBADD132PDZ128mbk:
16510 case VFMSUBADD132PDZ128mbkz:
16511 case VFMSUBADD132PDZ128mk:
16512 case VFMSUBADD132PDZ128mkz:
16513 case VFMSUBADD132PDZ128r:
16514 case VFMSUBADD132PDZ128rk:
16515 case VFMSUBADD132PDZ128rkz:
16516 case VFMSUBADD132PDZ256m:
16517 case VFMSUBADD132PDZ256mb:
16518 case VFMSUBADD132PDZ256mbk:
16519 case VFMSUBADD132PDZ256mbkz:
16520 case VFMSUBADD132PDZ256mk:
16521 case VFMSUBADD132PDZ256mkz:
16522 case VFMSUBADD132PDZ256r:
16523 case VFMSUBADD132PDZ256rk:
16524 case VFMSUBADD132PDZ256rkz:
16525 case VFMSUBADD132PDZm:
16526 case VFMSUBADD132PDZmb:
16527 case VFMSUBADD132PDZmbk:
16528 case VFMSUBADD132PDZmbkz:
16529 case VFMSUBADD132PDZmk:
16530 case VFMSUBADD132PDZmkz:
16531 case VFMSUBADD132PDZr:
16532 case VFMSUBADD132PDZrb:
16533 case VFMSUBADD132PDZrbk:
16534 case VFMSUBADD132PDZrbkz:
16535 case VFMSUBADD132PDZrk:
16536 case VFMSUBADD132PDZrkz:
16537 case VFMSUBADD132PDm:
16538 case VFMSUBADD132PDr:
16539 return true;
16540 }
16541 return false;
16542}
16543
16544bool isVPERMILPD(unsigned Opcode) {
16545 switch (Opcode) {
16546 case VPERMILPDYmi:
16547 case VPERMILPDYri:
16548 case VPERMILPDYrm:
16549 case VPERMILPDYrr:
16550 case VPERMILPDZ128mbi:
16551 case VPERMILPDZ128mbik:
16552 case VPERMILPDZ128mbikz:
16553 case VPERMILPDZ128mi:
16554 case VPERMILPDZ128mik:
16555 case VPERMILPDZ128mikz:
16556 case VPERMILPDZ128ri:
16557 case VPERMILPDZ128rik:
16558 case VPERMILPDZ128rikz:
16559 case VPERMILPDZ128rm:
16560 case VPERMILPDZ128rmb:
16561 case VPERMILPDZ128rmbk:
16562 case VPERMILPDZ128rmbkz:
16563 case VPERMILPDZ128rmk:
16564 case VPERMILPDZ128rmkz:
16565 case VPERMILPDZ128rr:
16566 case VPERMILPDZ128rrk:
16567 case VPERMILPDZ128rrkz:
16568 case VPERMILPDZ256mbi:
16569 case VPERMILPDZ256mbik:
16570 case VPERMILPDZ256mbikz:
16571 case VPERMILPDZ256mi:
16572 case VPERMILPDZ256mik:
16573 case VPERMILPDZ256mikz:
16574 case VPERMILPDZ256ri:
16575 case VPERMILPDZ256rik:
16576 case VPERMILPDZ256rikz:
16577 case VPERMILPDZ256rm:
16578 case VPERMILPDZ256rmb:
16579 case VPERMILPDZ256rmbk:
16580 case VPERMILPDZ256rmbkz:
16581 case VPERMILPDZ256rmk:
16582 case VPERMILPDZ256rmkz:
16583 case VPERMILPDZ256rr:
16584 case VPERMILPDZ256rrk:
16585 case VPERMILPDZ256rrkz:
16586 case VPERMILPDZmbi:
16587 case VPERMILPDZmbik:
16588 case VPERMILPDZmbikz:
16589 case VPERMILPDZmi:
16590 case VPERMILPDZmik:
16591 case VPERMILPDZmikz:
16592 case VPERMILPDZri:
16593 case VPERMILPDZrik:
16594 case VPERMILPDZrikz:
16595 case VPERMILPDZrm:
16596 case VPERMILPDZrmb:
16597 case VPERMILPDZrmbk:
16598 case VPERMILPDZrmbkz:
16599 case VPERMILPDZrmk:
16600 case VPERMILPDZrmkz:
16601 case VPERMILPDZrr:
16602 case VPERMILPDZrrk:
16603 case VPERMILPDZrrkz:
16604 case VPERMILPDmi:
16605 case VPERMILPDri:
16606 case VPERMILPDrm:
16607 case VPERMILPDrr:
16608 return true;
16609 }
16610 return false;
16611}
16612
16613bool isADDSD(unsigned Opcode) {
16614 switch (Opcode) {
16615 case ADDSDrm_Int:
16616 case ADDSDrr_Int:
16617 return true;
16618 }
16619 return false;
16620}
16621
16622bool isBLENDPD(unsigned Opcode) {
16623 switch (Opcode) {
16624 case BLENDPDrmi:
16625 case BLENDPDrri:
16626 return true;
16627 }
16628 return false;
16629}
16630
16631bool isVPANDQ(unsigned Opcode) {
16632 switch (Opcode) {
16633 case VPANDQZ128rm:
16634 case VPANDQZ128rmb:
16635 case VPANDQZ128rmbk:
16636 case VPANDQZ128rmbkz:
16637 case VPANDQZ128rmk:
16638 case VPANDQZ128rmkz:
16639 case VPANDQZ128rr:
16640 case VPANDQZ128rrk:
16641 case VPANDQZ128rrkz:
16642 case VPANDQZ256rm:
16643 case VPANDQZ256rmb:
16644 case VPANDQZ256rmbk:
16645 case VPANDQZ256rmbkz:
16646 case VPANDQZ256rmk:
16647 case VPANDQZ256rmkz:
16648 case VPANDQZ256rr:
16649 case VPANDQZ256rrk:
16650 case VPANDQZ256rrkz:
16651 case VPANDQZrm:
16652 case VPANDQZrmb:
16653 case VPANDQZrmbk:
16654 case VPANDQZrmbkz:
16655 case VPANDQZrmk:
16656 case VPANDQZrmkz:
16657 case VPANDQZrr:
16658 case VPANDQZrrk:
16659 case VPANDQZrrkz:
16660 return true;
16661 }
16662 return false;
16663}
16664
16665bool isPMADDUBSW(unsigned Opcode) {
16666 switch (Opcode) {
16667 case MMX_PMADDUBSWrm:
16668 case MMX_PMADDUBSWrr:
16669 case PMADDUBSWrm:
16670 case PMADDUBSWrr:
16671 return true;
16672 }
16673 return false;
16674}
16675
16676bool isPOPFD(unsigned Opcode) {
16677 return Opcode == POPF32;
16678}
16679
16680bool isCMPSW(unsigned Opcode) {
16681 return Opcode == CMPSW;
16682}
16683
16684bool isLDMXCSR(unsigned Opcode) {
16685 return Opcode == LDMXCSR;
16686}
16687
16688bool isVMULPS(unsigned Opcode) {
16689 switch (Opcode) {
16690 case VMULPSYrm:
16691 case VMULPSYrr:
16692 case VMULPSZ128rm:
16693 case VMULPSZ128rmb:
16694 case VMULPSZ128rmbk:
16695 case VMULPSZ128rmbkz:
16696 case VMULPSZ128rmk:
16697 case VMULPSZ128rmkz:
16698 case VMULPSZ128rr:
16699 case VMULPSZ128rrk:
16700 case VMULPSZ128rrkz:
16701 case VMULPSZ256rm:
16702 case VMULPSZ256rmb:
16703 case VMULPSZ256rmbk:
16704 case VMULPSZ256rmbkz:
16705 case VMULPSZ256rmk:
16706 case VMULPSZ256rmkz:
16707 case VMULPSZ256rr:
16708 case VMULPSZ256rrk:
16709 case VMULPSZ256rrkz:
16710 case VMULPSZrm:
16711 case VMULPSZrmb:
16712 case VMULPSZrmbk:
16713 case VMULPSZrmbkz:
16714 case VMULPSZrmk:
16715 case VMULPSZrmkz:
16716 case VMULPSZrr:
16717 case VMULPSZrrb:
16718 case VMULPSZrrbk:
16719 case VMULPSZrrbkz:
16720 case VMULPSZrrk:
16721 case VMULPSZrrkz:
16722 case VMULPSrm:
16723 case VMULPSrr:
16724 return true;
16725 }
16726 return false;
16727}
16728
16729bool isVROUNDSD(unsigned Opcode) {
16730 switch (Opcode) {
16731 case VROUNDSDmi_Int:
16732 case VROUNDSDri_Int:
16733 return true;
16734 }
16735 return false;
16736}
16737
16738bool isVFMADD132PD(unsigned Opcode) {
16739 switch (Opcode) {
16740 case VFMADD132PDYm:
16741 case VFMADD132PDYr:
16742 case VFMADD132PDZ128m:
16743 case VFMADD132PDZ128mb:
16744 case VFMADD132PDZ128mbk:
16745 case VFMADD132PDZ128mbkz:
16746 case VFMADD132PDZ128mk:
16747 case VFMADD132PDZ128mkz:
16748 case VFMADD132PDZ128r:
16749 case VFMADD132PDZ128rk:
16750 case VFMADD132PDZ128rkz:
16751 case VFMADD132PDZ256m:
16752 case VFMADD132PDZ256mb:
16753 case VFMADD132PDZ256mbk:
16754 case VFMADD132PDZ256mbkz:
16755 case VFMADD132PDZ256mk:
16756 case VFMADD132PDZ256mkz:
16757 case VFMADD132PDZ256r:
16758 case VFMADD132PDZ256rk:
16759 case VFMADD132PDZ256rkz:
16760 case VFMADD132PDZm:
16761 case VFMADD132PDZmb:
16762 case VFMADD132PDZmbk:
16763 case VFMADD132PDZmbkz:
16764 case VFMADD132PDZmk:
16765 case VFMADD132PDZmkz:
16766 case VFMADD132PDZr:
16767 case VFMADD132PDZrb:
16768 case VFMADD132PDZrbk:
16769 case VFMADD132PDZrbkz:
16770 case VFMADD132PDZrk:
16771 case VFMADD132PDZrkz:
16772 case VFMADD132PDm:
16773 case VFMADD132PDr:
16774 return true;
16775 }
16776 return false;
16777}
16778
16779bool isVPSRAQ(unsigned Opcode) {
16780 switch (Opcode) {
16781 case VPSRAQZ128mbi:
16782 case VPSRAQZ128mbik:
16783 case VPSRAQZ128mbikz:
16784 case VPSRAQZ128mi:
16785 case VPSRAQZ128mik:
16786 case VPSRAQZ128mikz:
16787 case VPSRAQZ128ri:
16788 case VPSRAQZ128rik:
16789 case VPSRAQZ128rikz:
16790 case VPSRAQZ128rm:
16791 case VPSRAQZ128rmk:
16792 case VPSRAQZ128rmkz:
16793 case VPSRAQZ128rr:
16794 case VPSRAQZ128rrk:
16795 case VPSRAQZ128rrkz:
16796 case VPSRAQZ256mbi:
16797 case VPSRAQZ256mbik:
16798 case VPSRAQZ256mbikz:
16799 case VPSRAQZ256mi:
16800 case VPSRAQZ256mik:
16801 case VPSRAQZ256mikz:
16802 case VPSRAQZ256ri:
16803 case VPSRAQZ256rik:
16804 case VPSRAQZ256rikz:
16805 case VPSRAQZ256rm:
16806 case VPSRAQZ256rmk:
16807 case VPSRAQZ256rmkz:
16808 case VPSRAQZ256rr:
16809 case VPSRAQZ256rrk:
16810 case VPSRAQZ256rrkz:
16811 case VPSRAQZmbi:
16812 case VPSRAQZmbik:
16813 case VPSRAQZmbikz:
16814 case VPSRAQZmi:
16815 case VPSRAQZmik:
16816 case VPSRAQZmikz:
16817 case VPSRAQZri:
16818 case VPSRAQZrik:
16819 case VPSRAQZrikz:
16820 case VPSRAQZrm:
16821 case VPSRAQZrmk:
16822 case VPSRAQZrmkz:
16823 case VPSRAQZrr:
16824 case VPSRAQZrrk:
16825 case VPSRAQZrrkz:
16826 return true;
16827 }
16828 return false;
16829}
16830
16831bool isVCOMISD(unsigned Opcode) {
16832 switch (Opcode) {
16833 case VCOMISDZrm:
16834 case VCOMISDZrr:
16835 case VCOMISDZrrb:
16836 case VCOMISDrm:
16837 case VCOMISDrr:
16838 return true;
16839 }
16840 return false;
16841}
16842
16843bool isVCVTBIASPH2BF8(unsigned Opcode) {
16844 switch (Opcode) {
16845 case VCVTBIASPH2BF8Z128rm:
16846 case VCVTBIASPH2BF8Z128rmb:
16847 case VCVTBIASPH2BF8Z128rmbk:
16848 case VCVTBIASPH2BF8Z128rmbkz:
16849 case VCVTBIASPH2BF8Z128rmk:
16850 case VCVTBIASPH2BF8Z128rmkz:
16851 case VCVTBIASPH2BF8Z128rr:
16852 case VCVTBIASPH2BF8Z128rrk:
16853 case VCVTBIASPH2BF8Z128rrkz:
16854 case VCVTBIASPH2BF8Z256rm:
16855 case VCVTBIASPH2BF8Z256rmb:
16856 case VCVTBIASPH2BF8Z256rmbk:
16857 case VCVTBIASPH2BF8Z256rmbkz:
16858 case VCVTBIASPH2BF8Z256rmk:
16859 case VCVTBIASPH2BF8Z256rmkz:
16860 case VCVTBIASPH2BF8Z256rr:
16861 case VCVTBIASPH2BF8Z256rrk:
16862 case VCVTBIASPH2BF8Z256rrkz:
16863 case VCVTBIASPH2BF8Zrm:
16864 case VCVTBIASPH2BF8Zrmb:
16865 case VCVTBIASPH2BF8Zrmbk:
16866 case VCVTBIASPH2BF8Zrmbkz:
16867 case VCVTBIASPH2BF8Zrmk:
16868 case VCVTBIASPH2BF8Zrmkz:
16869 case VCVTBIASPH2BF8Zrr:
16870 case VCVTBIASPH2BF8Zrrk:
16871 case VCVTBIASPH2BF8Zrrkz:
16872 return true;
16873 }
16874 return false;
16875}
16876
16877bool isFFREEP(unsigned Opcode) {
16878 return Opcode == FFREEP;
16879}
16880
16881bool isVFNMADD213PD(unsigned Opcode) {
16882 switch (Opcode) {
16883 case VFNMADD213PDYm:
16884 case VFNMADD213PDYr:
16885 case VFNMADD213PDZ128m:
16886 case VFNMADD213PDZ128mb:
16887 case VFNMADD213PDZ128mbk:
16888 case VFNMADD213PDZ128mbkz:
16889 case VFNMADD213PDZ128mk:
16890 case VFNMADD213PDZ128mkz:
16891 case VFNMADD213PDZ128r:
16892 case VFNMADD213PDZ128rk:
16893 case VFNMADD213PDZ128rkz:
16894 case VFNMADD213PDZ256m:
16895 case VFNMADD213PDZ256mb:
16896 case VFNMADD213PDZ256mbk:
16897 case VFNMADD213PDZ256mbkz:
16898 case VFNMADD213PDZ256mk:
16899 case VFNMADD213PDZ256mkz:
16900 case VFNMADD213PDZ256r:
16901 case VFNMADD213PDZ256rk:
16902 case VFNMADD213PDZ256rkz:
16903 case VFNMADD213PDZm:
16904 case VFNMADD213PDZmb:
16905 case VFNMADD213PDZmbk:
16906 case VFNMADD213PDZmbkz:
16907 case VFNMADD213PDZmk:
16908 case VFNMADD213PDZmkz:
16909 case VFNMADD213PDZr:
16910 case VFNMADD213PDZrb:
16911 case VFNMADD213PDZrbk:
16912 case VFNMADD213PDZrbkz:
16913 case VFNMADD213PDZrk:
16914 case VFNMADD213PDZrkz:
16915 case VFNMADD213PDm:
16916 case VFNMADD213PDr:
16917 return true;
16918 }
16919 return false;
16920}
16921
16922bool isVCMPPD(unsigned Opcode) {
16923 switch (Opcode) {
16924 case VCMPPDYrmi:
16925 case VCMPPDYrri:
16926 case VCMPPDZ128rmbi:
16927 case VCMPPDZ128rmbik:
16928 case VCMPPDZ128rmi:
16929 case VCMPPDZ128rmik:
16930 case VCMPPDZ128rri:
16931 case VCMPPDZ128rrik:
16932 case VCMPPDZ256rmbi:
16933 case VCMPPDZ256rmbik:
16934 case VCMPPDZ256rmi:
16935 case VCMPPDZ256rmik:
16936 case VCMPPDZ256rri:
16937 case VCMPPDZ256rrik:
16938 case VCMPPDZrmbi:
16939 case VCMPPDZrmbik:
16940 case VCMPPDZrmi:
16941 case VCMPPDZrmik:
16942 case VCMPPDZrri:
16943 case VCMPPDZrrib:
16944 case VCMPPDZrribk:
16945 case VCMPPDZrrik:
16946 case VCMPPDrmi:
16947 case VCMPPDrri:
16948 return true;
16949 }
16950 return false;
16951}
16952
16953bool isVFNMSUB132PH(unsigned Opcode) {
16954 switch (Opcode) {
16955 case VFNMSUB132PHZ128m:
16956 case VFNMSUB132PHZ128mb:
16957 case VFNMSUB132PHZ128mbk:
16958 case VFNMSUB132PHZ128mbkz:
16959 case VFNMSUB132PHZ128mk:
16960 case VFNMSUB132PHZ128mkz:
16961 case VFNMSUB132PHZ128r:
16962 case VFNMSUB132PHZ128rk:
16963 case VFNMSUB132PHZ128rkz:
16964 case VFNMSUB132PHZ256m:
16965 case VFNMSUB132PHZ256mb:
16966 case VFNMSUB132PHZ256mbk:
16967 case VFNMSUB132PHZ256mbkz:
16968 case VFNMSUB132PHZ256mk:
16969 case VFNMSUB132PHZ256mkz:
16970 case VFNMSUB132PHZ256r:
16971 case VFNMSUB132PHZ256rk:
16972 case VFNMSUB132PHZ256rkz:
16973 case VFNMSUB132PHZm:
16974 case VFNMSUB132PHZmb:
16975 case VFNMSUB132PHZmbk:
16976 case VFNMSUB132PHZmbkz:
16977 case VFNMSUB132PHZmk:
16978 case VFNMSUB132PHZmkz:
16979 case VFNMSUB132PHZr:
16980 case VFNMSUB132PHZrb:
16981 case VFNMSUB132PHZrbk:
16982 case VFNMSUB132PHZrbkz:
16983 case VFNMSUB132PHZrk:
16984 case VFNMSUB132PHZrkz:
16985 return true;
16986 }
16987 return false;
16988}
16989
16990bool isVPHADDBW(unsigned Opcode) {
16991 switch (Opcode) {
16992 case VPHADDBWrm:
16993 case VPHADDBWrr:
16994 return true;
16995 }
16996 return false;
16997}
16998
16999bool isVPPERM(unsigned Opcode) {
17000 switch (Opcode) {
17001 case VPPERMrmr:
17002 case VPPERMrrm:
17003 case VPPERMrrr:
17004 case VPPERMrrr_REV:
17005 return true;
17006 }
17007 return false;
17008}
17009
17010bool isVCVTPS2PD(unsigned Opcode) {
17011 switch (Opcode) {
17012 case VCVTPS2PDYrm:
17013 case VCVTPS2PDYrr:
17014 case VCVTPS2PDZ128rm:
17015 case VCVTPS2PDZ128rmb:
17016 case VCVTPS2PDZ128rmbk:
17017 case VCVTPS2PDZ128rmbkz:
17018 case VCVTPS2PDZ128rmk:
17019 case VCVTPS2PDZ128rmkz:
17020 case VCVTPS2PDZ128rr:
17021 case VCVTPS2PDZ128rrk:
17022 case VCVTPS2PDZ128rrkz:
17023 case VCVTPS2PDZ256rm:
17024 case VCVTPS2PDZ256rmb:
17025 case VCVTPS2PDZ256rmbk:
17026 case VCVTPS2PDZ256rmbkz:
17027 case VCVTPS2PDZ256rmk:
17028 case VCVTPS2PDZ256rmkz:
17029 case VCVTPS2PDZ256rr:
17030 case VCVTPS2PDZ256rrk:
17031 case VCVTPS2PDZ256rrkz:
17032 case VCVTPS2PDZrm:
17033 case VCVTPS2PDZrmb:
17034 case VCVTPS2PDZrmbk:
17035 case VCVTPS2PDZrmbkz:
17036 case VCVTPS2PDZrmk:
17037 case VCVTPS2PDZrmkz:
17038 case VCVTPS2PDZrr:
17039 case VCVTPS2PDZrrb:
17040 case VCVTPS2PDZrrbk:
17041 case VCVTPS2PDZrrbkz:
17042 case VCVTPS2PDZrrk:
17043 case VCVTPS2PDZrrkz:
17044 case VCVTPS2PDrm:
17045 case VCVTPS2PDrr:
17046 return true;
17047 }
17048 return false;
17049}
17050
17051bool isCBW(unsigned Opcode) {
17052 return Opcode == CBW;
17053}
17054
17055bool isVMOVUPS(unsigned Opcode) {
17056 switch (Opcode) {
17057 case VMOVUPSYmr:
17058 case VMOVUPSYrm:
17059 case VMOVUPSYrr:
17060 case VMOVUPSYrr_REV:
17061 case VMOVUPSZ128mr:
17062 case VMOVUPSZ128mrk:
17063 case VMOVUPSZ128rm:
17064 case VMOVUPSZ128rmk:
17065 case VMOVUPSZ128rmkz:
17066 case VMOVUPSZ128rr:
17067 case VMOVUPSZ128rr_REV:
17068 case VMOVUPSZ128rrk:
17069 case VMOVUPSZ128rrk_REV:
17070 case VMOVUPSZ128rrkz:
17071 case VMOVUPSZ128rrkz_REV:
17072 case VMOVUPSZ256mr:
17073 case VMOVUPSZ256mrk:
17074 case VMOVUPSZ256rm:
17075 case VMOVUPSZ256rmk:
17076 case VMOVUPSZ256rmkz:
17077 case VMOVUPSZ256rr:
17078 case VMOVUPSZ256rr_REV:
17079 case VMOVUPSZ256rrk:
17080 case VMOVUPSZ256rrk_REV:
17081 case VMOVUPSZ256rrkz:
17082 case VMOVUPSZ256rrkz_REV:
17083 case VMOVUPSZmr:
17084 case VMOVUPSZmrk:
17085 case VMOVUPSZrm:
17086 case VMOVUPSZrmk:
17087 case VMOVUPSZrmkz:
17088 case VMOVUPSZrr:
17089 case VMOVUPSZrr_REV:
17090 case VMOVUPSZrrk:
17091 case VMOVUPSZrrk_REV:
17092 case VMOVUPSZrrkz:
17093 case VMOVUPSZrrkz_REV:
17094 case VMOVUPSmr:
17095 case VMOVUPSrm:
17096 case VMOVUPSrr:
17097 case VMOVUPSrr_REV:
17098 return true;
17099 }
17100 return false;
17101}
17102
17103bool isVPMAXUQ(unsigned Opcode) {
17104 switch (Opcode) {
17105 case VPMAXUQZ128rm:
17106 case VPMAXUQZ128rmb:
17107 case VPMAXUQZ128rmbk:
17108 case VPMAXUQZ128rmbkz:
17109 case VPMAXUQZ128rmk:
17110 case VPMAXUQZ128rmkz:
17111 case VPMAXUQZ128rr:
17112 case VPMAXUQZ128rrk:
17113 case VPMAXUQZ128rrkz:
17114 case VPMAXUQZ256rm:
17115 case VPMAXUQZ256rmb:
17116 case VPMAXUQZ256rmbk:
17117 case VPMAXUQZ256rmbkz:
17118 case VPMAXUQZ256rmk:
17119 case VPMAXUQZ256rmkz:
17120 case VPMAXUQZ256rr:
17121 case VPMAXUQZ256rrk:
17122 case VPMAXUQZ256rrkz:
17123 case VPMAXUQZrm:
17124 case VPMAXUQZrmb:
17125 case VPMAXUQZrmbk:
17126 case VPMAXUQZrmbkz:
17127 case VPMAXUQZrmk:
17128 case VPMAXUQZrmkz:
17129 case VPMAXUQZrr:
17130 case VPMAXUQZrrk:
17131 case VPMAXUQZrrkz:
17132 return true;
17133 }
17134 return false;
17135}
17136
17137bool isWRSSQ(unsigned Opcode) {
17138 switch (Opcode) {
17139 case WRSSQ:
17140 case WRSSQ_EVEX:
17141 return true;
17142 }
17143 return false;
17144}
17145
17146bool isPACKUSDW(unsigned Opcode) {
17147 switch (Opcode) {
17148 case PACKUSDWrm:
17149 case PACKUSDWrr:
17150 return true;
17151 }
17152 return false;
17153}
17154
17155bool isVCVTTBF162IBS(unsigned Opcode) {
17156 switch (Opcode) {
17157 case VCVTTBF162IBSZ128rm:
17158 case VCVTTBF162IBSZ128rmb:
17159 case VCVTTBF162IBSZ128rmbk:
17160 case VCVTTBF162IBSZ128rmbkz:
17161 case VCVTTBF162IBSZ128rmk:
17162 case VCVTTBF162IBSZ128rmkz:
17163 case VCVTTBF162IBSZ128rr:
17164 case VCVTTBF162IBSZ128rrk:
17165 case VCVTTBF162IBSZ128rrkz:
17166 case VCVTTBF162IBSZ256rm:
17167 case VCVTTBF162IBSZ256rmb:
17168 case VCVTTBF162IBSZ256rmbk:
17169 case VCVTTBF162IBSZ256rmbkz:
17170 case VCVTTBF162IBSZ256rmk:
17171 case VCVTTBF162IBSZ256rmkz:
17172 case VCVTTBF162IBSZ256rr:
17173 case VCVTTBF162IBSZ256rrk:
17174 case VCVTTBF162IBSZ256rrkz:
17175 case VCVTTBF162IBSZrm:
17176 case VCVTTBF162IBSZrmb:
17177 case VCVTTBF162IBSZrmbk:
17178 case VCVTTBF162IBSZrmbkz:
17179 case VCVTTBF162IBSZrmk:
17180 case VCVTTBF162IBSZrmkz:
17181 case VCVTTBF162IBSZrr:
17182 case VCVTTBF162IBSZrrk:
17183 case VCVTTBF162IBSZrrkz:
17184 return true;
17185 }
17186 return false;
17187}
17188
17189bool isXBEGIN(unsigned Opcode) {
17190 switch (Opcode) {
17191 case XBEGIN_2:
17192 case XBEGIN_4:
17193 return true;
17194 }
17195 return false;
17196}
17197
17198bool isVCVTPD2UQQ(unsigned Opcode) {
17199 switch (Opcode) {
17200 case VCVTPD2UQQZ128rm:
17201 case VCVTPD2UQQZ128rmb:
17202 case VCVTPD2UQQZ128rmbk:
17203 case VCVTPD2UQQZ128rmbkz:
17204 case VCVTPD2UQQZ128rmk:
17205 case VCVTPD2UQQZ128rmkz:
17206 case VCVTPD2UQQZ128rr:
17207 case VCVTPD2UQQZ128rrk:
17208 case VCVTPD2UQQZ128rrkz:
17209 case VCVTPD2UQQZ256rm:
17210 case VCVTPD2UQQZ256rmb:
17211 case VCVTPD2UQQZ256rmbk:
17212 case VCVTPD2UQQZ256rmbkz:
17213 case VCVTPD2UQQZ256rmk:
17214 case VCVTPD2UQQZ256rmkz:
17215 case VCVTPD2UQQZ256rr:
17216 case VCVTPD2UQQZ256rrk:
17217 case VCVTPD2UQQZ256rrkz:
17218 case VCVTPD2UQQZrm:
17219 case VCVTPD2UQQZrmb:
17220 case VCVTPD2UQQZrmbk:
17221 case VCVTPD2UQQZrmbkz:
17222 case VCVTPD2UQQZrmk:
17223 case VCVTPD2UQQZrmkz:
17224 case VCVTPD2UQQZrr:
17225 case VCVTPD2UQQZrrb:
17226 case VCVTPD2UQQZrrbk:
17227 case VCVTPD2UQQZrrbkz:
17228 case VCVTPD2UQQZrrk:
17229 case VCVTPD2UQQZrrkz:
17230 return true;
17231 }
17232 return false;
17233}
17234
17235bool isFCMOVB(unsigned Opcode) {
17236 return Opcode == CMOVB_F;
17237}
17238
17239bool isNOP(unsigned Opcode) {
17240 switch (Opcode) {
17241 case NOOP:
17242 case NOOPL:
17243 case NOOPLr:
17244 case NOOPQ:
17245 case NOOPQr:
17246 case NOOPW:
17247 case NOOPWr:
17248 return true;
17249 }
17250 return false;
17251}
17252
17253bool isVPABSQ(unsigned Opcode) {
17254 switch (Opcode) {
17255 case VPABSQZ128rm:
17256 case VPABSQZ128rmb:
17257 case VPABSQZ128rmbk:
17258 case VPABSQZ128rmbkz:
17259 case VPABSQZ128rmk:
17260 case VPABSQZ128rmkz:
17261 case VPABSQZ128rr:
17262 case VPABSQZ128rrk:
17263 case VPABSQZ128rrkz:
17264 case VPABSQZ256rm:
17265 case VPABSQZ256rmb:
17266 case VPABSQZ256rmbk:
17267 case VPABSQZ256rmbkz:
17268 case VPABSQZ256rmk:
17269 case VPABSQZ256rmkz:
17270 case VPABSQZ256rr:
17271 case VPABSQZ256rrk:
17272 case VPABSQZ256rrkz:
17273 case VPABSQZrm:
17274 case VPABSQZrmb:
17275 case VPABSQZrmbk:
17276 case VPABSQZrmbkz:
17277 case VPABSQZrmk:
17278 case VPABSQZrmkz:
17279 case VPABSQZrr:
17280 case VPABSQZrrk:
17281 case VPABSQZrrkz:
17282 return true;
17283 }
17284 return false;
17285}
17286
17287bool isVTESTPS(unsigned Opcode) {
17288 switch (Opcode) {
17289 case VTESTPSYrm:
17290 case VTESTPSYrr:
17291 case VTESTPSrm:
17292 case VTESTPSrr:
17293 return true;
17294 }
17295 return false;
17296}
17297
17298bool isPHSUBW(unsigned Opcode) {
17299 switch (Opcode) {
17300 case MMX_PHSUBWrm:
17301 case MMX_PHSUBWrr:
17302 case PHSUBWrm:
17303 case PHSUBWrr:
17304 return true;
17305 }
17306 return false;
17307}
17308
17309bool isPUSH2P(unsigned Opcode) {
17310 return Opcode == PUSH2P;
17311}
17312
17313bool isFISTTP(unsigned Opcode) {
17314 switch (Opcode) {
17315 case ISTT_FP16m:
17316 case ISTT_FP32m:
17317 case ISTT_FP64m:
17318 return true;
17319 }
17320 return false;
17321}
17322
17323bool isCFCMOVCC(unsigned Opcode) {
17324 switch (Opcode) {
17325 case CFCMOV16mr:
17326 case CFCMOV16rm:
17327 case CFCMOV16rm_ND:
17328 case CFCMOV16rr:
17329 case CFCMOV16rr_ND:
17330 case CFCMOV16rr_REV:
17331 case CFCMOV32mr:
17332 case CFCMOV32rm:
17333 case CFCMOV32rm_ND:
17334 case CFCMOV32rr:
17335 case CFCMOV32rr_ND:
17336 case CFCMOV32rr_REV:
17337 case CFCMOV64mr:
17338 case CFCMOV64rm:
17339 case CFCMOV64rm_ND:
17340 case CFCMOV64rr:
17341 case CFCMOV64rr_ND:
17342 case CFCMOV64rr_REV:
17343 return true;
17344 }
17345 return false;
17346}
17347
17348bool isPCMPESTRM(unsigned Opcode) {
17349 switch (Opcode) {
17350 case PCMPESTRMrmi:
17351 case PCMPESTRMrri:
17352 return true;
17353 }
17354 return false;
17355}
17356
17357bool isVPINSRD(unsigned Opcode) {
17358 switch (Opcode) {
17359 case VPINSRDZrmi:
17360 case VPINSRDZrri:
17361 case VPINSRDrmi:
17362 case VPINSRDrri:
17363 return true;
17364 }
17365 return false;
17366}
17367
17368bool isVFNMSUB213PS(unsigned Opcode) {
17369 switch (Opcode) {
17370 case VFNMSUB213PSYm:
17371 case VFNMSUB213PSYr:
17372 case VFNMSUB213PSZ128m:
17373 case VFNMSUB213PSZ128mb:
17374 case VFNMSUB213PSZ128mbk:
17375 case VFNMSUB213PSZ128mbkz:
17376 case VFNMSUB213PSZ128mk:
17377 case VFNMSUB213PSZ128mkz:
17378 case VFNMSUB213PSZ128r:
17379 case VFNMSUB213PSZ128rk:
17380 case VFNMSUB213PSZ128rkz:
17381 case VFNMSUB213PSZ256m:
17382 case VFNMSUB213PSZ256mb:
17383 case VFNMSUB213PSZ256mbk:
17384 case VFNMSUB213PSZ256mbkz:
17385 case VFNMSUB213PSZ256mk:
17386 case VFNMSUB213PSZ256mkz:
17387 case VFNMSUB213PSZ256r:
17388 case VFNMSUB213PSZ256rk:
17389 case VFNMSUB213PSZ256rkz:
17390 case VFNMSUB213PSZm:
17391 case VFNMSUB213PSZmb:
17392 case VFNMSUB213PSZmbk:
17393 case VFNMSUB213PSZmbkz:
17394 case VFNMSUB213PSZmk:
17395 case VFNMSUB213PSZmkz:
17396 case VFNMSUB213PSZr:
17397 case VFNMSUB213PSZrb:
17398 case VFNMSUB213PSZrbk:
17399 case VFNMSUB213PSZrbkz:
17400 case VFNMSUB213PSZrk:
17401 case VFNMSUB213PSZrkz:
17402 case VFNMSUB213PSm:
17403 case VFNMSUB213PSr:
17404 return true;
17405 }
17406 return false;
17407}
17408
17409bool isPHSUBD(unsigned Opcode) {
17410 switch (Opcode) {
17411 case MMX_PHSUBDrm:
17412 case MMX_PHSUBDrr:
17413 case PHSUBDrm:
17414 case PHSUBDrr:
17415 return true;
17416 }
17417 return false;
17418}
17419
17420bool isSLDT(unsigned Opcode) {
17421 switch (Opcode) {
17422 case SLDT16m:
17423 case SLDT16r:
17424 case SLDT32r:
17425 case SLDT64r:
17426 return true;
17427 }
17428 return false;
17429}
17430
17431bool isVCVTTPD2DQS(unsigned Opcode) {
17432 switch (Opcode) {
17433 case VCVTTPD2DQSZ128rm:
17434 case VCVTTPD2DQSZ128rmb:
17435 case VCVTTPD2DQSZ128rmbk:
17436 case VCVTTPD2DQSZ128rmbkz:
17437 case VCVTTPD2DQSZ128rmk:
17438 case VCVTTPD2DQSZ128rmkz:
17439 case VCVTTPD2DQSZ128rr:
17440 case VCVTTPD2DQSZ128rrk:
17441 case VCVTTPD2DQSZ128rrkz:
17442 case VCVTTPD2DQSZ256rm:
17443 case VCVTTPD2DQSZ256rmb:
17444 case VCVTTPD2DQSZ256rmbk:
17445 case VCVTTPD2DQSZ256rmbkz:
17446 case VCVTTPD2DQSZ256rmk:
17447 case VCVTTPD2DQSZ256rmkz:
17448 case VCVTTPD2DQSZ256rr:
17449 case VCVTTPD2DQSZ256rrb:
17450 case VCVTTPD2DQSZ256rrbk:
17451 case VCVTTPD2DQSZ256rrbkz:
17452 case VCVTTPD2DQSZ256rrk:
17453 case VCVTTPD2DQSZ256rrkz:
17454 case VCVTTPD2DQSZrm:
17455 case VCVTTPD2DQSZrmb:
17456 case VCVTTPD2DQSZrmbk:
17457 case VCVTTPD2DQSZrmbkz:
17458 case VCVTTPD2DQSZrmk:
17459 case VCVTTPD2DQSZrmkz:
17460 case VCVTTPD2DQSZrr:
17461 case VCVTTPD2DQSZrrb:
17462 case VCVTTPD2DQSZrrbk:
17463 case VCVTTPD2DQSZrrbkz:
17464 case VCVTTPD2DQSZrrk:
17465 case VCVTTPD2DQSZrrkz:
17466 return true;
17467 }
17468 return false;
17469}
17470
17471bool isVPMINSD(unsigned Opcode) {
17472 switch (Opcode) {
17473 case VPMINSDYrm:
17474 case VPMINSDYrr:
17475 case VPMINSDZ128rm:
17476 case VPMINSDZ128rmb:
17477 case VPMINSDZ128rmbk:
17478 case VPMINSDZ128rmbkz:
17479 case VPMINSDZ128rmk:
17480 case VPMINSDZ128rmkz:
17481 case VPMINSDZ128rr:
17482 case VPMINSDZ128rrk:
17483 case VPMINSDZ128rrkz:
17484 case VPMINSDZ256rm:
17485 case VPMINSDZ256rmb:
17486 case VPMINSDZ256rmbk:
17487 case VPMINSDZ256rmbkz:
17488 case VPMINSDZ256rmk:
17489 case VPMINSDZ256rmkz:
17490 case VPMINSDZ256rr:
17491 case VPMINSDZ256rrk:
17492 case VPMINSDZ256rrkz:
17493 case VPMINSDZrm:
17494 case VPMINSDZrmb:
17495 case VPMINSDZrmbk:
17496 case VPMINSDZrmbkz:
17497 case VPMINSDZrmk:
17498 case VPMINSDZrmkz:
17499 case VPMINSDZrr:
17500 case VPMINSDZrrk:
17501 case VPMINSDZrrkz:
17502 case VPMINSDrm:
17503 case VPMINSDrr:
17504 return true;
17505 }
17506 return false;
17507}
17508
17509bool isVHADDPS(unsigned Opcode) {
17510 switch (Opcode) {
17511 case VHADDPSYrm:
17512 case VHADDPSYrr:
17513 case VHADDPSrm:
17514 case VHADDPSrr:
17515 return true;
17516 }
17517 return false;
17518}
17519
17520bool isVMOVNTDQ(unsigned Opcode) {
17521 switch (Opcode) {
17522 case VMOVNTDQYmr:
17523 case VMOVNTDQZ128mr:
17524 case VMOVNTDQZ256mr:
17525 case VMOVNTDQZmr:
17526 case VMOVNTDQmr:
17527 return true;
17528 }
17529 return false;
17530}
17531
17532bool isVFRCZSD(unsigned Opcode) {
17533 switch (Opcode) {
17534 case VFRCZSDrm:
17535 case VFRCZSDrr:
17536 return true;
17537 }
17538 return false;
17539}
17540
17541bool isIBHF(unsigned Opcode) {
17542 return Opcode == IBHF;
17543}
17544
17545bool isVPTESTMW(unsigned Opcode) {
17546 switch (Opcode) {
17547 case VPTESTMWZ128rm:
17548 case VPTESTMWZ128rmk:
17549 case VPTESTMWZ128rr:
17550 case VPTESTMWZ128rrk:
17551 case VPTESTMWZ256rm:
17552 case VPTESTMWZ256rmk:
17553 case VPTESTMWZ256rr:
17554 case VPTESTMWZ256rrk:
17555 case VPTESTMWZrm:
17556 case VPTESTMWZrmk:
17557 case VPTESTMWZrr:
17558 case VPTESTMWZrrk:
17559 return true;
17560 }
17561 return false;
17562}
17563
17564bool isVPMOVZXWD(unsigned Opcode) {
17565 switch (Opcode) {
17566 case VPMOVZXWDYrm:
17567 case VPMOVZXWDYrr:
17568 case VPMOVZXWDZ128rm:
17569 case VPMOVZXWDZ128rmk:
17570 case VPMOVZXWDZ128rmkz:
17571 case VPMOVZXWDZ128rr:
17572 case VPMOVZXWDZ128rrk:
17573 case VPMOVZXWDZ128rrkz:
17574 case VPMOVZXWDZ256rm:
17575 case VPMOVZXWDZ256rmk:
17576 case VPMOVZXWDZ256rmkz:
17577 case VPMOVZXWDZ256rr:
17578 case VPMOVZXWDZ256rrk:
17579 case VPMOVZXWDZ256rrkz:
17580 case VPMOVZXWDZrm:
17581 case VPMOVZXWDZrmk:
17582 case VPMOVZXWDZrmkz:
17583 case VPMOVZXWDZrr:
17584 case VPMOVZXWDZrrk:
17585 case VPMOVZXWDZrrkz:
17586 case VPMOVZXWDrm:
17587 case VPMOVZXWDrr:
17588 return true;
17589 }
17590 return false;
17591}
17592
17593bool isPSADBW(unsigned Opcode) {
17594 switch (Opcode) {
17595 case MMX_PSADBWrm:
17596 case MMX_PSADBWrr:
17597 case PSADBWrm:
17598 case PSADBWrr:
17599 return true;
17600 }
17601 return false;
17602}
17603
17604bool isVCVTSD2SI(unsigned Opcode) {
17605 switch (Opcode) {
17606 case VCVTSD2SI64Zrm_Int:
17607 case VCVTSD2SI64Zrr_Int:
17608 case VCVTSD2SI64Zrrb_Int:
17609 case VCVTSD2SI64rm_Int:
17610 case VCVTSD2SI64rr_Int:
17611 case VCVTSD2SIZrm_Int:
17612 case VCVTSD2SIZrr_Int:
17613 case VCVTSD2SIZrrb_Int:
17614 case VCVTSD2SIrm_Int:
17615 case VCVTSD2SIrr_Int:
17616 return true;
17617 }
17618 return false;
17619}
17620
17621bool isVMAXPH(unsigned Opcode) {
17622 switch (Opcode) {
17623 case VMAXPHZ128rm:
17624 case VMAXPHZ128rmb:
17625 case VMAXPHZ128rmbk:
17626 case VMAXPHZ128rmbkz:
17627 case VMAXPHZ128rmk:
17628 case VMAXPHZ128rmkz:
17629 case VMAXPHZ128rr:
17630 case VMAXPHZ128rrk:
17631 case VMAXPHZ128rrkz:
17632 case VMAXPHZ256rm:
17633 case VMAXPHZ256rmb:
17634 case VMAXPHZ256rmbk:
17635 case VMAXPHZ256rmbkz:
17636 case VMAXPHZ256rmk:
17637 case VMAXPHZ256rmkz:
17638 case VMAXPHZ256rr:
17639 case VMAXPHZ256rrk:
17640 case VMAXPHZ256rrkz:
17641 case VMAXPHZrm:
17642 case VMAXPHZrmb:
17643 case VMAXPHZrmbk:
17644 case VMAXPHZrmbkz:
17645 case VMAXPHZrmk:
17646 case VMAXPHZrmkz:
17647 case VMAXPHZrr:
17648 case VMAXPHZrrb:
17649 case VMAXPHZrrbk:
17650 case VMAXPHZrrbkz:
17651 case VMAXPHZrrk:
17652 case VMAXPHZrrkz:
17653 return true;
17654 }
17655 return false;
17656}
17657
17658bool isLODSB(unsigned Opcode) {
17659 return Opcode == LODSB;
17660}
17661
17662bool isPHMINPOSUW(unsigned Opcode) {
17663 switch (Opcode) {
17664 case PHMINPOSUWrm:
17665 case PHMINPOSUWrr:
17666 return true;
17667 }
17668 return false;
17669}
17670
17671bool isVPROLVD(unsigned Opcode) {
17672 switch (Opcode) {
17673 case VPROLVDZ128rm:
17674 case VPROLVDZ128rmb:
17675 case VPROLVDZ128rmbk:
17676 case VPROLVDZ128rmbkz:
17677 case VPROLVDZ128rmk:
17678 case VPROLVDZ128rmkz:
17679 case VPROLVDZ128rr:
17680 case VPROLVDZ128rrk:
17681 case VPROLVDZ128rrkz:
17682 case VPROLVDZ256rm:
17683 case VPROLVDZ256rmb:
17684 case VPROLVDZ256rmbk:
17685 case VPROLVDZ256rmbkz:
17686 case VPROLVDZ256rmk:
17687 case VPROLVDZ256rmkz:
17688 case VPROLVDZ256rr:
17689 case VPROLVDZ256rrk:
17690 case VPROLVDZ256rrkz:
17691 case VPROLVDZrm:
17692 case VPROLVDZrmb:
17693 case VPROLVDZrmbk:
17694 case VPROLVDZrmbkz:
17695 case VPROLVDZrmk:
17696 case VPROLVDZrmkz:
17697 case VPROLVDZrr:
17698 case VPROLVDZrrk:
17699 case VPROLVDZrrkz:
17700 return true;
17701 }
17702 return false;
17703}
17704
17705bool isWRFSBASE(unsigned Opcode) {
17706 switch (Opcode) {
17707 case WRFSBASE:
17708 case WRFSBASE64:
17709 return true;
17710 }
17711 return false;
17712}
17713
17714bool isVRSQRT14PS(unsigned Opcode) {
17715 switch (Opcode) {
17716 case VRSQRT14PSZ128m:
17717 case VRSQRT14PSZ128mb:
17718 case VRSQRT14PSZ128mbk:
17719 case VRSQRT14PSZ128mbkz:
17720 case VRSQRT14PSZ128mk:
17721 case VRSQRT14PSZ128mkz:
17722 case VRSQRT14PSZ128r:
17723 case VRSQRT14PSZ128rk:
17724 case VRSQRT14PSZ128rkz:
17725 case VRSQRT14PSZ256m:
17726 case VRSQRT14PSZ256mb:
17727 case VRSQRT14PSZ256mbk:
17728 case VRSQRT14PSZ256mbkz:
17729 case VRSQRT14PSZ256mk:
17730 case VRSQRT14PSZ256mkz:
17731 case VRSQRT14PSZ256r:
17732 case VRSQRT14PSZ256rk:
17733 case VRSQRT14PSZ256rkz:
17734 case VRSQRT14PSZm:
17735 case VRSQRT14PSZmb:
17736 case VRSQRT14PSZmbk:
17737 case VRSQRT14PSZmbkz:
17738 case VRSQRT14PSZmk:
17739 case VRSQRT14PSZmkz:
17740 case VRSQRT14PSZr:
17741 case VRSQRT14PSZrk:
17742 case VRSQRT14PSZrkz:
17743 return true;
17744 }
17745 return false;
17746}
17747
17748bool isVPHSUBDQ(unsigned Opcode) {
17749 switch (Opcode) {
17750 case VPHSUBDQrm:
17751 case VPHSUBDQrr:
17752 return true;
17753 }
17754 return false;
17755}
17756
17757bool isIRETD(unsigned Opcode) {
17758 return Opcode == IRET32;
17759}
17760
17761bool isVMOVRSD(unsigned Opcode) {
17762 switch (Opcode) {
17763 case VMOVRSDZ128m:
17764 case VMOVRSDZ128mk:
17765 case VMOVRSDZ128mkz:
17766 case VMOVRSDZ256m:
17767 case VMOVRSDZ256mk:
17768 case VMOVRSDZ256mkz:
17769 case VMOVRSDZm:
17770 case VMOVRSDZmk:
17771 case VMOVRSDZmkz:
17772 return true;
17773 }
17774 return false;
17775}
17776
17777bool isVPMULHRSW(unsigned Opcode) {
17778 switch (Opcode) {
17779 case VPMULHRSWYrm:
17780 case VPMULHRSWYrr:
17781 case VPMULHRSWZ128rm:
17782 case VPMULHRSWZ128rmk:
17783 case VPMULHRSWZ128rmkz:
17784 case VPMULHRSWZ128rr:
17785 case VPMULHRSWZ128rrk:
17786 case VPMULHRSWZ128rrkz:
17787 case VPMULHRSWZ256rm:
17788 case VPMULHRSWZ256rmk:
17789 case VPMULHRSWZ256rmkz:
17790 case VPMULHRSWZ256rr:
17791 case VPMULHRSWZ256rrk:
17792 case VPMULHRSWZ256rrkz:
17793 case VPMULHRSWZrm:
17794 case VPMULHRSWZrmk:
17795 case VPMULHRSWZrmkz:
17796 case VPMULHRSWZrr:
17797 case VPMULHRSWZrrk:
17798 case VPMULHRSWZrrkz:
17799 case VPMULHRSWrm:
17800 case VPMULHRSWrr:
17801 return true;
17802 }
17803 return false;
17804}
17805
17806bool isCVTSI2SS(unsigned Opcode) {
17807 switch (Opcode) {
17808 case CVTSI2SSrm_Int:
17809 case CVTSI2SSrr_Int:
17810 case CVTSI642SSrm_Int:
17811 case CVTSI642SSrr_Int:
17812 return true;
17813 }
17814 return false;
17815}
17816
17817bool isPI2FD(unsigned Opcode) {
17818 switch (Opcode) {
17819 case PI2FDrm:
17820 case PI2FDrr:
17821 return true;
17822 }
17823 return false;
17824}
17825
17826bool isGF2P8AFFINEQB(unsigned Opcode) {
17827 switch (Opcode) {
17828 case GF2P8AFFINEQBrmi:
17829 case GF2P8AFFINEQBrri:
17830 return true;
17831 }
17832 return false;
17833}
17834
17835bool isPAND(unsigned Opcode) {
17836 switch (Opcode) {
17837 case MMX_PANDrm:
17838 case MMX_PANDrr:
17839 case PANDrm:
17840 case PANDrr:
17841 return true;
17842 }
17843 return false;
17844}
17845
17846bool isVFNMSUB231SH(unsigned Opcode) {
17847 switch (Opcode) {
17848 case VFNMSUB231SHZm_Int:
17849 case VFNMSUB231SHZmk_Int:
17850 case VFNMSUB231SHZmkz_Int:
17851 case VFNMSUB231SHZr_Int:
17852 case VFNMSUB231SHZrb_Int:
17853 case VFNMSUB231SHZrbk_Int:
17854 case VFNMSUB231SHZrbkz_Int:
17855 case VFNMSUB231SHZrk_Int:
17856 case VFNMSUB231SHZrkz_Int:
17857 return true;
17858 }
17859 return false;
17860}
17861
17862bool isVMOVHLPS(unsigned Opcode) {
17863 switch (Opcode) {
17864 case VMOVHLPSZrr:
17865 case VMOVHLPSrr:
17866 return true;
17867 }
17868 return false;
17869}
17870
17871bool isKNOTD(unsigned Opcode) {
17872 return Opcode == KNOTDkk;
17873}
17874
17875bool isPEXTRB(unsigned Opcode) {
17876 switch (Opcode) {
17877 case PEXTRBmri:
17878 case PEXTRBrri:
17879 return true;
17880 }
17881 return false;
17882}
17883
17884bool isVCVTPH2BF8(unsigned Opcode) {
17885 switch (Opcode) {
17886 case VCVTPH2BF8Z128rm:
17887 case VCVTPH2BF8Z128rmb:
17888 case VCVTPH2BF8Z128rmbk:
17889 case VCVTPH2BF8Z128rmbkz:
17890 case VCVTPH2BF8Z128rmk:
17891 case VCVTPH2BF8Z128rmkz:
17892 case VCVTPH2BF8Z128rr:
17893 case VCVTPH2BF8Z128rrk:
17894 case VCVTPH2BF8Z128rrkz:
17895 case VCVTPH2BF8Z256rm:
17896 case VCVTPH2BF8Z256rmb:
17897 case VCVTPH2BF8Z256rmbk:
17898 case VCVTPH2BF8Z256rmbkz:
17899 case VCVTPH2BF8Z256rmk:
17900 case VCVTPH2BF8Z256rmkz:
17901 case VCVTPH2BF8Z256rr:
17902 case VCVTPH2BF8Z256rrk:
17903 case VCVTPH2BF8Z256rrkz:
17904 case VCVTPH2BF8Zrm:
17905 case VCVTPH2BF8Zrmb:
17906 case VCVTPH2BF8Zrmbk:
17907 case VCVTPH2BF8Zrmbkz:
17908 case VCVTPH2BF8Zrmk:
17909 case VCVTPH2BF8Zrmkz:
17910 case VCVTPH2BF8Zrr:
17911 case VCVTPH2BF8Zrrk:
17912 case VCVTPH2BF8Zrrkz:
17913 return true;
17914 }
17915 return false;
17916}
17917
17918bool isVMMCALL(unsigned Opcode) {
17919 return Opcode == VMMCALL;
17920}
17921
17922bool isVCVTSH2SS(unsigned Opcode) {
17923 switch (Opcode) {
17924 case VCVTSH2SSZrm_Int:
17925 case VCVTSH2SSZrmk_Int:
17926 case VCVTSH2SSZrmkz_Int:
17927 case VCVTSH2SSZrr_Int:
17928 case VCVTSH2SSZrrb_Int:
17929 case VCVTSH2SSZrrbk_Int:
17930 case VCVTSH2SSZrrbkz_Int:
17931 case VCVTSH2SSZrrk_Int:
17932 case VCVTSH2SSZrrkz_Int:
17933 return true;
17934 }
17935 return false;
17936}
17937
17938bool isVPUNPCKLQDQ(unsigned Opcode) {
17939 switch (Opcode) {
17940 case VPUNPCKLQDQYrm:
17941 case VPUNPCKLQDQYrr:
17942 case VPUNPCKLQDQZ128rm:
17943 case VPUNPCKLQDQZ128rmb:
17944 case VPUNPCKLQDQZ128rmbk:
17945 case VPUNPCKLQDQZ128rmbkz:
17946 case VPUNPCKLQDQZ128rmk:
17947 case VPUNPCKLQDQZ128rmkz:
17948 case VPUNPCKLQDQZ128rr:
17949 case VPUNPCKLQDQZ128rrk:
17950 case VPUNPCKLQDQZ128rrkz:
17951 case VPUNPCKLQDQZ256rm:
17952 case VPUNPCKLQDQZ256rmb:
17953 case VPUNPCKLQDQZ256rmbk:
17954 case VPUNPCKLQDQZ256rmbkz:
17955 case VPUNPCKLQDQZ256rmk:
17956 case VPUNPCKLQDQZ256rmkz:
17957 case VPUNPCKLQDQZ256rr:
17958 case VPUNPCKLQDQZ256rrk:
17959 case VPUNPCKLQDQZ256rrkz:
17960 case VPUNPCKLQDQZrm:
17961 case VPUNPCKLQDQZrmb:
17962 case VPUNPCKLQDQZrmbk:
17963 case VPUNPCKLQDQZrmbkz:
17964 case VPUNPCKLQDQZrmk:
17965 case VPUNPCKLQDQZrmkz:
17966 case VPUNPCKLQDQZrr:
17967 case VPUNPCKLQDQZrrk:
17968 case VPUNPCKLQDQZrrkz:
17969 case VPUNPCKLQDQrm:
17970 case VPUNPCKLQDQrr:
17971 return true;
17972 }
17973 return false;
17974}
17975
17976bool isVPERMIL2PS(unsigned Opcode) {
17977 switch (Opcode) {
17978 case VPERMIL2PSYmr:
17979 case VPERMIL2PSYrm:
17980 case VPERMIL2PSYrr:
17981 case VPERMIL2PSYrr_REV:
17982 case VPERMIL2PSmr:
17983 case VPERMIL2PSrm:
17984 case VPERMIL2PSrr:
17985 case VPERMIL2PSrr_REV:
17986 return true;
17987 }
17988 return false;
17989}
17990
17991bool isVPCMPGTD(unsigned Opcode) {
17992 switch (Opcode) {
17993 case VPCMPGTDYrm:
17994 case VPCMPGTDYrr:
17995 case VPCMPGTDZ128rm:
17996 case VPCMPGTDZ128rmb:
17997 case VPCMPGTDZ128rmbk:
17998 case VPCMPGTDZ128rmk:
17999 case VPCMPGTDZ128rr:
18000 case VPCMPGTDZ128rrk:
18001 case VPCMPGTDZ256rm:
18002 case VPCMPGTDZ256rmb:
18003 case VPCMPGTDZ256rmbk:
18004 case VPCMPGTDZ256rmk:
18005 case VPCMPGTDZ256rr:
18006 case VPCMPGTDZ256rrk:
18007 case VPCMPGTDZrm:
18008 case VPCMPGTDZrmb:
18009 case VPCMPGTDZrmbk:
18010 case VPCMPGTDZrmk:
18011 case VPCMPGTDZrr:
18012 case VPCMPGTDZrrk:
18013 case VPCMPGTDrm:
18014 case VPCMPGTDrr:
18015 return true;
18016 }
18017 return false;
18018}
18019
18020bool isCMPXCHG16B(unsigned Opcode) {
18021 return Opcode == CMPXCHG16B;
18022}
18023
18024bool isTDPHF8PS(unsigned Opcode) {
18025 return Opcode == TDPHF8PS;
18026}
18027
18028bool isVZEROUPPER(unsigned Opcode) {
18029 return Opcode == VZEROUPPER;
18030}
18031
18032bool isMOVAPS(unsigned Opcode) {
18033 switch (Opcode) {
18034 case MOVAPSmr:
18035 case MOVAPSrm:
18036 case MOVAPSrr:
18037 case MOVAPSrr_REV:
18038 return true;
18039 }
18040 return false;
18041}
18042
18043bool isRMPOPT(unsigned Opcode) {
18044 return Opcode == RMPOPT;
18045}
18046
18047bool isFUCOMPP(unsigned Opcode) {
18048 return Opcode == UCOM_FPPr;
18049}
18050
18051bool isVPCMPW(unsigned Opcode) {
18052 switch (Opcode) {
18053 case VPCMPWZ128rmi:
18054 case VPCMPWZ128rmik:
18055 case VPCMPWZ128rri:
18056 case VPCMPWZ128rrik:
18057 case VPCMPWZ256rmi:
18058 case VPCMPWZ256rmik:
18059 case VPCMPWZ256rri:
18060 case VPCMPWZ256rrik:
18061 case VPCMPWZrmi:
18062 case VPCMPWZrmik:
18063 case VPCMPWZrri:
18064 case VPCMPWZrrik:
18065 return true;
18066 }
18067 return false;
18068}
18069
18070bool isXSETBV(unsigned Opcode) {
18071 return Opcode == XSETBV;
18072}
18073
18074bool isSLWPCB(unsigned Opcode) {
18075 switch (Opcode) {
18076 case SLWPCB:
18077 case SLWPCB64:
18078 return true;
18079 }
18080 return false;
18081}
18082
18083bool isSCASW(unsigned Opcode) {
18084 return Opcode == SCASW;
18085}
18086
18087bool isFCMOVNE(unsigned Opcode) {
18088 return Opcode == CMOVNE_F;
18089}
18090
18091bool isPBNDKB(unsigned Opcode) {
18092 return Opcode == PBNDKB;
18093}
18094
18095bool isVPMULLD(unsigned Opcode) {
18096 switch (Opcode) {
18097 case VPMULLDYrm:
18098 case VPMULLDYrr:
18099 case VPMULLDZ128rm:
18100 case VPMULLDZ128rmb:
18101 case VPMULLDZ128rmbk:
18102 case VPMULLDZ128rmbkz:
18103 case VPMULLDZ128rmk:
18104 case VPMULLDZ128rmkz:
18105 case VPMULLDZ128rr:
18106 case VPMULLDZ128rrk:
18107 case VPMULLDZ128rrkz:
18108 case VPMULLDZ256rm:
18109 case VPMULLDZ256rmb:
18110 case VPMULLDZ256rmbk:
18111 case VPMULLDZ256rmbkz:
18112 case VPMULLDZ256rmk:
18113 case VPMULLDZ256rmkz:
18114 case VPMULLDZ256rr:
18115 case VPMULLDZ256rrk:
18116 case VPMULLDZ256rrkz:
18117 case VPMULLDZrm:
18118 case VPMULLDZrmb:
18119 case VPMULLDZrmbk:
18120 case VPMULLDZrmbkz:
18121 case VPMULLDZrmk:
18122 case VPMULLDZrmkz:
18123 case VPMULLDZrr:
18124 case VPMULLDZrrk:
18125 case VPMULLDZrrkz:
18126 case VPMULLDrm:
18127 case VPMULLDrr:
18128 return true;
18129 }
18130 return false;
18131}
18132
18133bool isVP4DPWSSDS(unsigned Opcode) {
18134 switch (Opcode) {
18135 case VP4DPWSSDSrm:
18136 case VP4DPWSSDSrmk:
18137 case VP4DPWSSDSrmkz:
18138 return true;
18139 }
18140 return false;
18141}
18142
18143bool isVCVT2PH2HF8(unsigned Opcode) {
18144 switch (Opcode) {
18145 case VCVT2PH2HF8Z128rm:
18146 case VCVT2PH2HF8Z128rmb:
18147 case VCVT2PH2HF8Z128rmbk:
18148 case VCVT2PH2HF8Z128rmbkz:
18149 case VCVT2PH2HF8Z128rmk:
18150 case VCVT2PH2HF8Z128rmkz:
18151 case VCVT2PH2HF8Z128rr:
18152 case VCVT2PH2HF8Z128rrk:
18153 case VCVT2PH2HF8Z128rrkz:
18154 case VCVT2PH2HF8Z256rm:
18155 case VCVT2PH2HF8Z256rmb:
18156 case VCVT2PH2HF8Z256rmbk:
18157 case VCVT2PH2HF8Z256rmbkz:
18158 case VCVT2PH2HF8Z256rmk:
18159 case VCVT2PH2HF8Z256rmkz:
18160 case VCVT2PH2HF8Z256rr:
18161 case VCVT2PH2HF8Z256rrk:
18162 case VCVT2PH2HF8Z256rrkz:
18163 case VCVT2PH2HF8Zrm:
18164 case VCVT2PH2HF8Zrmb:
18165 case VCVT2PH2HF8Zrmbk:
18166 case VCVT2PH2HF8Zrmbkz:
18167 case VCVT2PH2HF8Zrmk:
18168 case VCVT2PH2HF8Zrmkz:
18169 case VCVT2PH2HF8Zrr:
18170 case VCVT2PH2HF8Zrrk:
18171 case VCVT2PH2HF8Zrrkz:
18172 return true;
18173 }
18174 return false;
18175}
18176
18177bool isPINSRW(unsigned Opcode) {
18178 switch (Opcode) {
18179 case MMX_PINSRWrmi:
18180 case MMX_PINSRWrri:
18181 case PINSRWrmi:
18182 case PINSRWrri:
18183 return true;
18184 }
18185 return false;
18186}
18187
18188bool isVCVTSI2SH(unsigned Opcode) {
18189 switch (Opcode) {
18190 case VCVTSI2SHZrm_Int:
18191 case VCVTSI2SHZrr_Int:
18192 case VCVTSI2SHZrrb_Int:
18193 case VCVTSI642SHZrm_Int:
18194 case VCVTSI642SHZrr_Int:
18195 case VCVTSI642SHZrrb_Int:
18196 return true;
18197 }
18198 return false;
18199}
18200
18201bool isVINSERTF32X8(unsigned Opcode) {
18202 switch (Opcode) {
18203 case VINSERTF32X8Zrmi:
18204 case VINSERTF32X8Zrmik:
18205 case VINSERTF32X8Zrmikz:
18206 case VINSERTF32X8Zrri:
18207 case VINSERTF32X8Zrrik:
18208 case VINSERTF32X8Zrrikz:
18209 return true;
18210 }
18211 return false;
18212}
18213
18214bool isKSHIFTLB(unsigned Opcode) {
18215 return Opcode == KSHIFTLBki;
18216}
18217
18218bool isSEAMOPS(unsigned Opcode) {
18219 return Opcode == SEAMOPS;
18220}
18221
18222bool isVPMOVSQB(unsigned Opcode) {
18223 switch (Opcode) {
18224 case VPMOVSQBZ128mr:
18225 case VPMOVSQBZ128mrk:
18226 case VPMOVSQBZ128rr:
18227 case VPMOVSQBZ128rrk:
18228 case VPMOVSQBZ128rrkz:
18229 case VPMOVSQBZ256mr:
18230 case VPMOVSQBZ256mrk:
18231 case VPMOVSQBZ256rr:
18232 case VPMOVSQBZ256rrk:
18233 case VPMOVSQBZ256rrkz:
18234 case VPMOVSQBZmr:
18235 case VPMOVSQBZmrk:
18236 case VPMOVSQBZrr:
18237 case VPMOVSQBZrrk:
18238 case VPMOVSQBZrrkz:
18239 return true;
18240 }
18241 return false;
18242}
18243
18244bool isVPMULUDQ(unsigned Opcode) {
18245 switch (Opcode) {
18246 case VPMULUDQYrm:
18247 case VPMULUDQYrr:
18248 case VPMULUDQZ128rm:
18249 case VPMULUDQZ128rmb:
18250 case VPMULUDQZ128rmbk:
18251 case VPMULUDQZ128rmbkz:
18252 case VPMULUDQZ128rmk:
18253 case VPMULUDQZ128rmkz:
18254 case VPMULUDQZ128rr:
18255 case VPMULUDQZ128rrk:
18256 case VPMULUDQZ128rrkz:
18257 case VPMULUDQZ256rm:
18258 case VPMULUDQZ256rmb:
18259 case VPMULUDQZ256rmbk:
18260 case VPMULUDQZ256rmbkz:
18261 case VPMULUDQZ256rmk:
18262 case VPMULUDQZ256rmkz:
18263 case VPMULUDQZ256rr:
18264 case VPMULUDQZ256rrk:
18265 case VPMULUDQZ256rrkz:
18266 case VPMULUDQZrm:
18267 case VPMULUDQZrmb:
18268 case VPMULUDQZrmbk:
18269 case VPMULUDQZrmbkz:
18270 case VPMULUDQZrmk:
18271 case VPMULUDQZrmkz:
18272 case VPMULUDQZrr:
18273 case VPMULUDQZrrk:
18274 case VPMULUDQZrrkz:
18275 case VPMULUDQrm:
18276 case VPMULUDQrr:
18277 return true;
18278 }
18279 return false;
18280}
18281
18282bool isVPTESTMD(unsigned Opcode) {
18283 switch (Opcode) {
18284 case VPTESTMDZ128rm:
18285 case VPTESTMDZ128rmb:
18286 case VPTESTMDZ128rmbk:
18287 case VPTESTMDZ128rmk:
18288 case VPTESTMDZ128rr:
18289 case VPTESTMDZ128rrk:
18290 case VPTESTMDZ256rm:
18291 case VPTESTMDZ256rmb:
18292 case VPTESTMDZ256rmbk:
18293 case VPTESTMDZ256rmk:
18294 case VPTESTMDZ256rr:
18295 case VPTESTMDZ256rrk:
18296 case VPTESTMDZrm:
18297 case VPTESTMDZrmb:
18298 case VPTESTMDZrmbk:
18299 case VPTESTMDZrmk:
18300 case VPTESTMDZrr:
18301 case VPTESTMDZrrk:
18302 return true;
18303 }
18304 return false;
18305}
18306
18307bool isVPHADDDQ(unsigned Opcode) {
18308 switch (Opcode) {
18309 case VPHADDDQrm:
18310 case VPHADDDQrr:
18311 return true;
18312 }
18313 return false;
18314}
18315
18316bool isKUNPCKDQ(unsigned Opcode) {
18317 return Opcode == KUNPCKDQkk;
18318}
18319
18320bool isT1MSKC(unsigned Opcode) {
18321 switch (Opcode) {
18322 case T1MSKC32rm:
18323 case T1MSKC32rr:
18324 case T1MSKC64rm:
18325 case T1MSKC64rr:
18326 return true;
18327 }
18328 return false;
18329}
18330
18331bool isVBLENDPS(unsigned Opcode) {
18332 switch (Opcode) {
18333 case VBLENDPSYrmi:
18334 case VBLENDPSYrri:
18335 case VBLENDPSrmi:
18336 case VBLENDPSrri:
18337 return true;
18338 }
18339 return false;
18340}
18341
18342bool isVPCOMB(unsigned Opcode) {
18343 switch (Opcode) {
18344 case VPCOMBmi:
18345 case VPCOMBri:
18346 return true;
18347 }
18348 return false;
18349}
18350
18351bool isPTWRITE(unsigned Opcode) {
18352 switch (Opcode) {
18353 case PTWRITE64m:
18354 case PTWRITE64r:
18355 case PTWRITEm:
18356 case PTWRITEr:
18357 return true;
18358 }
18359 return false;
18360}
18361
18362bool isVCVTPH2BF8S(unsigned Opcode) {
18363 switch (Opcode) {
18364 case VCVTPH2BF8SZ128rm:
18365 case VCVTPH2BF8SZ128rmb:
18366 case VCVTPH2BF8SZ128rmbk:
18367 case VCVTPH2BF8SZ128rmbkz:
18368 case VCVTPH2BF8SZ128rmk:
18369 case VCVTPH2BF8SZ128rmkz:
18370 case VCVTPH2BF8SZ128rr:
18371 case VCVTPH2BF8SZ128rrk:
18372 case VCVTPH2BF8SZ128rrkz:
18373 case VCVTPH2BF8SZ256rm:
18374 case VCVTPH2BF8SZ256rmb:
18375 case VCVTPH2BF8SZ256rmbk:
18376 case VCVTPH2BF8SZ256rmbkz:
18377 case VCVTPH2BF8SZ256rmk:
18378 case VCVTPH2BF8SZ256rmkz:
18379 case VCVTPH2BF8SZ256rr:
18380 case VCVTPH2BF8SZ256rrk:
18381 case VCVTPH2BF8SZ256rrkz:
18382 case VCVTPH2BF8SZrm:
18383 case VCVTPH2BF8SZrmb:
18384 case VCVTPH2BF8SZrmbk:
18385 case VCVTPH2BF8SZrmbkz:
18386 case VCVTPH2BF8SZrmk:
18387 case VCVTPH2BF8SZrmkz:
18388 case VCVTPH2BF8SZrr:
18389 case VCVTPH2BF8SZrrk:
18390 case VCVTPH2BF8SZrrkz:
18391 return true;
18392 }
18393 return false;
18394}
18395
18396bool isCVTPS2PI(unsigned Opcode) {
18397 switch (Opcode) {
18398 case MMX_CVTPS2PIrm:
18399 case MMX_CVTPS2PIrr:
18400 return true;
18401 }
18402 return false;
18403}
18404
18405bool isVPROTD(unsigned Opcode) {
18406 switch (Opcode) {
18407 case VPROTDmi:
18408 case VPROTDmr:
18409 case VPROTDri:
18410 case VPROTDrm:
18411 case VPROTDrr:
18412 case VPROTDrr_REV:
18413 return true;
18414 }
18415 return false;
18416}
18417
18418bool isCALL(unsigned Opcode) {
18419 switch (Opcode) {
18420 case CALL16m:
18421 case CALL16r:
18422 case CALL32m:
18423 case CALL32r:
18424 case CALL64m:
18425 case CALL64pcrel32:
18426 case CALL64r:
18427 case CALLpcrel16:
18428 case CALLpcrel32:
18429 case FARCALL32m:
18430 return true;
18431 }
18432 return false;
18433}
18434
18435bool isTILELOADDRST1(unsigned Opcode) {
18436 switch (Opcode) {
18437 case TILELOADDRST1:
18438 case TILELOADDRST1_EVEX:
18439 return true;
18440 }
18441 return false;
18442}
18443
18444bool isVPERMPS(unsigned Opcode) {
18445 switch (Opcode) {
18446 case VPERMPSYrm:
18447 case VPERMPSYrr:
18448 case VPERMPSZ256rm:
18449 case VPERMPSZ256rmb:
18450 case VPERMPSZ256rmbk:
18451 case VPERMPSZ256rmbkz:
18452 case VPERMPSZ256rmk:
18453 case VPERMPSZ256rmkz:
18454 case VPERMPSZ256rr:
18455 case VPERMPSZ256rrk:
18456 case VPERMPSZ256rrkz:
18457 case VPERMPSZrm:
18458 case VPERMPSZrmb:
18459 case VPERMPSZrmbk:
18460 case VPERMPSZrmbkz:
18461 case VPERMPSZrmk:
18462 case VPERMPSZrmkz:
18463 case VPERMPSZrr:
18464 case VPERMPSZrrk:
18465 case VPERMPSZrrkz:
18466 return true;
18467 }
18468 return false;
18469}
18470
18471bool isVPSHUFBITQMB(unsigned Opcode) {
18472 switch (Opcode) {
18473 case VPSHUFBITQMBZ128rm:
18474 case VPSHUFBITQMBZ128rmk:
18475 case VPSHUFBITQMBZ128rr:
18476 case VPSHUFBITQMBZ128rrk:
18477 case VPSHUFBITQMBZ256rm:
18478 case VPSHUFBITQMBZ256rmk:
18479 case VPSHUFBITQMBZ256rr:
18480 case VPSHUFBITQMBZ256rrk:
18481 case VPSHUFBITQMBZrm:
18482 case VPSHUFBITQMBZrmk:
18483 case VPSHUFBITQMBZrr:
18484 case VPSHUFBITQMBZrrk:
18485 return true;
18486 }
18487 return false;
18488}
18489
18490bool isVMOVSLDUP(unsigned Opcode) {
18491 switch (Opcode) {
18492 case VMOVSLDUPYrm:
18493 case VMOVSLDUPYrr:
18494 case VMOVSLDUPZ128rm:
18495 case VMOVSLDUPZ128rmk:
18496 case VMOVSLDUPZ128rmkz:
18497 case VMOVSLDUPZ128rr:
18498 case VMOVSLDUPZ128rrk:
18499 case VMOVSLDUPZ128rrkz:
18500 case VMOVSLDUPZ256rm:
18501 case VMOVSLDUPZ256rmk:
18502 case VMOVSLDUPZ256rmkz:
18503 case VMOVSLDUPZ256rr:
18504 case VMOVSLDUPZ256rrk:
18505 case VMOVSLDUPZ256rrkz:
18506 case VMOVSLDUPZrm:
18507 case VMOVSLDUPZrmk:
18508 case VMOVSLDUPZrmkz:
18509 case VMOVSLDUPZrr:
18510 case VMOVSLDUPZrrk:
18511 case VMOVSLDUPZrrkz:
18512 case VMOVSLDUPrm:
18513 case VMOVSLDUPrr:
18514 return true;
18515 }
18516 return false;
18517}
18518
18519bool isINVLPGA(unsigned Opcode) {
18520 switch (Opcode) {
18521 case INVLPGA32:
18522 case INVLPGA64:
18523 return true;
18524 }
18525 return false;
18526}
18527
18528bool isVCVTPH2QQ(unsigned Opcode) {
18529 switch (Opcode) {
18530 case VCVTPH2QQZ128rm:
18531 case VCVTPH2QQZ128rmb:
18532 case VCVTPH2QQZ128rmbk:
18533 case VCVTPH2QQZ128rmbkz:
18534 case VCVTPH2QQZ128rmk:
18535 case VCVTPH2QQZ128rmkz:
18536 case VCVTPH2QQZ128rr:
18537 case VCVTPH2QQZ128rrk:
18538 case VCVTPH2QQZ128rrkz:
18539 case VCVTPH2QQZ256rm:
18540 case VCVTPH2QQZ256rmb:
18541 case VCVTPH2QQZ256rmbk:
18542 case VCVTPH2QQZ256rmbkz:
18543 case VCVTPH2QQZ256rmk:
18544 case VCVTPH2QQZ256rmkz:
18545 case VCVTPH2QQZ256rr:
18546 case VCVTPH2QQZ256rrk:
18547 case VCVTPH2QQZ256rrkz:
18548 case VCVTPH2QQZrm:
18549 case VCVTPH2QQZrmb:
18550 case VCVTPH2QQZrmbk:
18551 case VCVTPH2QQZrmbkz:
18552 case VCVTPH2QQZrmk:
18553 case VCVTPH2QQZrmkz:
18554 case VCVTPH2QQZrr:
18555 case VCVTPH2QQZrrb:
18556 case VCVTPH2QQZrrbk:
18557 case VCVTPH2QQZrrbkz:
18558 case VCVTPH2QQZrrk:
18559 case VCVTPH2QQZrrkz:
18560 return true;
18561 }
18562 return false;
18563}
18564
18565bool isADD(unsigned Opcode) {
18566 switch (Opcode) {
18567 case ADD16i16:
18568 case ADD16mi:
18569 case ADD16mi8:
18570 case ADD16mi8_EVEX:
18571 case ADD16mi8_ND:
18572 case ADD16mi8_NF:
18573 case ADD16mi8_NF_ND:
18574 case ADD16mi_EVEX:
18575 case ADD16mi_ND:
18576 case ADD16mi_NF:
18577 case ADD16mi_NF_ND:
18578 case ADD16mr:
18579 case ADD16mr_EVEX:
18580 case ADD16mr_ND:
18581 case ADD16mr_NF:
18582 case ADD16mr_NF_ND:
18583 case ADD16ri:
18584 case ADD16ri8:
18585 case ADD16ri8_EVEX:
18586 case ADD16ri8_ND:
18587 case ADD16ri8_NF:
18588 case ADD16ri8_NF_ND:
18589 case ADD16ri_EVEX:
18590 case ADD16ri_ND:
18591 case ADD16ri_NF:
18592 case ADD16ri_NF_ND:
18593 case ADD16rm:
18594 case ADD16rm_EVEX:
18595 case ADD16rm_ND:
18596 case ADD16rm_NF:
18597 case ADD16rm_NF_ND:
18598 case ADD16rr:
18599 case ADD16rr_EVEX:
18600 case ADD16rr_EVEX_REV:
18601 case ADD16rr_ND:
18602 case ADD16rr_ND_REV:
18603 case ADD16rr_NF:
18604 case ADD16rr_NF_ND:
18605 case ADD16rr_NF_ND_REV:
18606 case ADD16rr_NF_REV:
18607 case ADD16rr_REV:
18608 case ADD32i32:
18609 case ADD32mi:
18610 case ADD32mi8:
18611 case ADD32mi8_EVEX:
18612 case ADD32mi8_ND:
18613 case ADD32mi8_NF:
18614 case ADD32mi8_NF_ND:
18615 case ADD32mi_EVEX:
18616 case ADD32mi_ND:
18617 case ADD32mi_NF:
18618 case ADD32mi_NF_ND:
18619 case ADD32mr:
18620 case ADD32mr_EVEX:
18621 case ADD32mr_ND:
18622 case ADD32mr_NF:
18623 case ADD32mr_NF_ND:
18624 case ADD32ri:
18625 case ADD32ri8:
18626 case ADD32ri8_EVEX:
18627 case ADD32ri8_ND:
18628 case ADD32ri8_NF:
18629 case ADD32ri8_NF_ND:
18630 case ADD32ri_EVEX:
18631 case ADD32ri_ND:
18632 case ADD32ri_NF:
18633 case ADD32ri_NF_ND:
18634 case ADD32rm:
18635 case ADD32rm_EVEX:
18636 case ADD32rm_ND:
18637 case ADD32rm_NF:
18638 case ADD32rm_NF_ND:
18639 case ADD32rr:
18640 case ADD32rr_EVEX:
18641 case ADD32rr_EVEX_REV:
18642 case ADD32rr_ND:
18643 case ADD32rr_ND_REV:
18644 case ADD32rr_NF:
18645 case ADD32rr_NF_ND:
18646 case ADD32rr_NF_ND_REV:
18647 case ADD32rr_NF_REV:
18648 case ADD32rr_REV:
18649 case ADD64i32:
18650 case ADD64mi32:
18651 case ADD64mi32_EVEX:
18652 case ADD64mi32_ND:
18653 case ADD64mi32_NF:
18654 case ADD64mi32_NF_ND:
18655 case ADD64mi8:
18656 case ADD64mi8_EVEX:
18657 case ADD64mi8_ND:
18658 case ADD64mi8_NF:
18659 case ADD64mi8_NF_ND:
18660 case ADD64mr:
18661 case ADD64mr_EVEX:
18662 case ADD64mr_ND:
18663 case ADD64mr_NF:
18664 case ADD64mr_NF_ND:
18665 case ADD64ri32:
18666 case ADD64ri32_EVEX:
18667 case ADD64ri32_ND:
18668 case ADD64ri32_NF:
18669 case ADD64ri32_NF_ND:
18670 case ADD64ri8:
18671 case ADD64ri8_EVEX:
18672 case ADD64ri8_ND:
18673 case ADD64ri8_NF:
18674 case ADD64ri8_NF_ND:
18675 case ADD64rm:
18676 case ADD64rm_EVEX:
18677 case ADD64rm_ND:
18678 case ADD64rm_NF:
18679 case ADD64rm_NF_ND:
18680 case ADD64rr:
18681 case ADD64rr_EVEX:
18682 case ADD64rr_EVEX_REV:
18683 case ADD64rr_ND:
18684 case ADD64rr_ND_REV:
18685 case ADD64rr_NF:
18686 case ADD64rr_NF_ND:
18687 case ADD64rr_NF_ND_REV:
18688 case ADD64rr_NF_REV:
18689 case ADD64rr_REV:
18690 case ADD8i8:
18691 case ADD8mi:
18692 case ADD8mi8:
18693 case ADD8mi_EVEX:
18694 case ADD8mi_ND:
18695 case ADD8mi_NF:
18696 case ADD8mi_NF_ND:
18697 case ADD8mr:
18698 case ADD8mr_EVEX:
18699 case ADD8mr_ND:
18700 case ADD8mr_NF:
18701 case ADD8mr_NF_ND:
18702 case ADD8ri:
18703 case ADD8ri8:
18704 case ADD8ri_EVEX:
18705 case ADD8ri_ND:
18706 case ADD8ri_NF:
18707 case ADD8ri_NF_ND:
18708 case ADD8rm:
18709 case ADD8rm_EVEX:
18710 case ADD8rm_ND:
18711 case ADD8rm_NF:
18712 case ADD8rm_NF_ND:
18713 case ADD8rr:
18714 case ADD8rr_EVEX:
18715 case ADD8rr_EVEX_REV:
18716 case ADD8rr_ND:
18717 case ADD8rr_ND_REV:
18718 case ADD8rr_NF:
18719 case ADD8rr_NF_ND:
18720 case ADD8rr_NF_ND_REV:
18721 case ADD8rr_NF_REV:
18722 case ADD8rr_REV:
18723 return true;
18724 }
18725 return false;
18726}
18727
18728bool isPSUBSW(unsigned Opcode) {
18729 switch (Opcode) {
18730 case MMX_PSUBSWrm:
18731 case MMX_PSUBSWrr:
18732 case PSUBSWrm:
18733 case PSUBSWrr:
18734 return true;
18735 }
18736 return false;
18737}
18738
18739bool isSIDTW(unsigned Opcode) {
18740 return Opcode == SIDT16m;
18741}
18742
18743bool isVEXTRACTF64X2(unsigned Opcode) {
18744 switch (Opcode) {
18745 case VEXTRACTF64X2Z256mri:
18746 case VEXTRACTF64X2Z256mrik:
18747 case VEXTRACTF64X2Z256rri:
18748 case VEXTRACTF64X2Z256rrik:
18749 case VEXTRACTF64X2Z256rrikz:
18750 case VEXTRACTF64X2Zmri:
18751 case VEXTRACTF64X2Zmrik:
18752 case VEXTRACTF64X2Zrri:
18753 case VEXTRACTF64X2Zrrik:
18754 case VEXTRACTF64X2Zrrikz:
18755 return true;
18756 }
18757 return false;
18758}
18759
18760bool isVFNMADD231PH(unsigned Opcode) {
18761 switch (Opcode) {
18762 case VFNMADD231PHZ128m:
18763 case VFNMADD231PHZ128mb:
18764 case VFNMADD231PHZ128mbk:
18765 case VFNMADD231PHZ128mbkz:
18766 case VFNMADD231PHZ128mk:
18767 case VFNMADD231PHZ128mkz:
18768 case VFNMADD231PHZ128r:
18769 case VFNMADD231PHZ128rk:
18770 case VFNMADD231PHZ128rkz:
18771 case VFNMADD231PHZ256m:
18772 case VFNMADD231PHZ256mb:
18773 case VFNMADD231PHZ256mbk:
18774 case VFNMADD231PHZ256mbkz:
18775 case VFNMADD231PHZ256mk:
18776 case VFNMADD231PHZ256mkz:
18777 case VFNMADD231PHZ256r:
18778 case VFNMADD231PHZ256rk:
18779 case VFNMADD231PHZ256rkz:
18780 case VFNMADD231PHZm:
18781 case VFNMADD231PHZmb:
18782 case VFNMADD231PHZmbk:
18783 case VFNMADD231PHZmbkz:
18784 case VFNMADD231PHZmk:
18785 case VFNMADD231PHZmkz:
18786 case VFNMADD231PHZr:
18787 case VFNMADD231PHZrb:
18788 case VFNMADD231PHZrbk:
18789 case VFNMADD231PHZrbkz:
18790 case VFNMADD231PHZrk:
18791 case VFNMADD231PHZrkz:
18792 return true;
18793 }
18794 return false;
18795}
18796
18797bool isFCOMI(unsigned Opcode) {
18798 return Opcode == COM_FIr;
18799}
18800
18801bool isRSM(unsigned Opcode) {
18802 return Opcode == RSM;
18803}
18804
18805bool isVPCOMUD(unsigned Opcode) {
18806 switch (Opcode) {
18807 case VPCOMUDmi:
18808 case VPCOMUDri:
18809 return true;
18810 }
18811 return false;
18812}
18813
18814bool isVPMOVZXBQ(unsigned Opcode) {
18815 switch (Opcode) {
18816 case VPMOVZXBQYrm:
18817 case VPMOVZXBQYrr:
18818 case VPMOVZXBQZ128rm:
18819 case VPMOVZXBQZ128rmk:
18820 case VPMOVZXBQZ128rmkz:
18821 case VPMOVZXBQZ128rr:
18822 case VPMOVZXBQZ128rrk:
18823 case VPMOVZXBQZ128rrkz:
18824 case VPMOVZXBQZ256rm:
18825 case VPMOVZXBQZ256rmk:
18826 case VPMOVZXBQZ256rmkz:
18827 case VPMOVZXBQZ256rr:
18828 case VPMOVZXBQZ256rrk:
18829 case VPMOVZXBQZ256rrkz:
18830 case VPMOVZXBQZrm:
18831 case VPMOVZXBQZrmk:
18832 case VPMOVZXBQZrmkz:
18833 case VPMOVZXBQZrr:
18834 case VPMOVZXBQZrrk:
18835 case VPMOVZXBQZrrkz:
18836 case VPMOVZXBQrm:
18837 case VPMOVZXBQrr:
18838 return true;
18839 }
18840 return false;
18841}
18842
18843bool isUWRMSR(unsigned Opcode) {
18844 switch (Opcode) {
18845 case UWRMSRir:
18846 case UWRMSRir_EVEX:
18847 case UWRMSRrr:
18848 case UWRMSRrr_EVEX:
18849 return true;
18850 }
18851 return false;
18852}
18853
18854bool isLGS(unsigned Opcode) {
18855 switch (Opcode) {
18856 case LGS16rm:
18857 case LGS32rm:
18858 case LGS64rm:
18859 return true;
18860 }
18861 return false;
18862}
18863
18864bool isVMOVNTPD(unsigned Opcode) {
18865 switch (Opcode) {
18866 case VMOVNTPDYmr:
18867 case VMOVNTPDZ128mr:
18868 case VMOVNTPDZ256mr:
18869 case VMOVNTPDZmr:
18870 case VMOVNTPDmr:
18871 return true;
18872 }
18873 return false;
18874}
18875
18876bool isPCMPESTRMQ(unsigned Opcode) {
18877 switch (Opcode) {
18878 case PCMPESTRMQrmi:
18879 case PCMPESTRMQrri:
18880 return true;
18881 }
18882 return false;
18883}
18884
18885bool isRDPRU(unsigned Opcode) {
18886 return Opcode == RDPRU;
18887}
18888
18889bool isVPUNPCKHBW(unsigned Opcode) {
18890 switch (Opcode) {
18891 case VPUNPCKHBWYrm:
18892 case VPUNPCKHBWYrr:
18893 case VPUNPCKHBWZ128rm:
18894 case VPUNPCKHBWZ128rmk:
18895 case VPUNPCKHBWZ128rmkz:
18896 case VPUNPCKHBWZ128rr:
18897 case VPUNPCKHBWZ128rrk:
18898 case VPUNPCKHBWZ128rrkz:
18899 case VPUNPCKHBWZ256rm:
18900 case VPUNPCKHBWZ256rmk:
18901 case VPUNPCKHBWZ256rmkz:
18902 case VPUNPCKHBWZ256rr:
18903 case VPUNPCKHBWZ256rrk:
18904 case VPUNPCKHBWZ256rrkz:
18905 case VPUNPCKHBWZrm:
18906 case VPUNPCKHBWZrmk:
18907 case VPUNPCKHBWZrmkz:
18908 case VPUNPCKHBWZrr:
18909 case VPUNPCKHBWZrrk:
18910 case VPUNPCKHBWZrrkz:
18911 case VPUNPCKHBWrm:
18912 case VPUNPCKHBWrr:
18913 return true;
18914 }
18915 return false;
18916}
18917
18918bool isVUCOMXSD(unsigned Opcode) {
18919 switch (Opcode) {
18920 case VUCOMXSDZrm_Int:
18921 case VUCOMXSDZrr_Int:
18922 case VUCOMXSDZrrb_Int:
18923 return true;
18924 }
18925 return false;
18926}
18927
18928bool isANDN(unsigned Opcode) {
18929 switch (Opcode) {
18930 case ANDN32rm:
18931 case ANDN32rm_EVEX:
18932 case ANDN32rm_NF:
18933 case ANDN32rr:
18934 case ANDN32rr_EVEX:
18935 case ANDN32rr_NF:
18936 case ANDN64rm:
18937 case ANDN64rm_EVEX:
18938 case ANDN64rm_NF:
18939 case ANDN64rr:
18940 case ANDN64rr_EVEX:
18941 case ANDN64rr_NF:
18942 return true;
18943 }
18944 return false;
18945}
18946
18947bool isVCVTTPH2UW(unsigned Opcode) {
18948 switch (Opcode) {
18949 case VCVTTPH2UWZ128rm:
18950 case VCVTTPH2UWZ128rmb:
18951 case VCVTTPH2UWZ128rmbk:
18952 case VCVTTPH2UWZ128rmbkz:
18953 case VCVTTPH2UWZ128rmk:
18954 case VCVTTPH2UWZ128rmkz:
18955 case VCVTTPH2UWZ128rr:
18956 case VCVTTPH2UWZ128rrk:
18957 case VCVTTPH2UWZ128rrkz:
18958 case VCVTTPH2UWZ256rm:
18959 case VCVTTPH2UWZ256rmb:
18960 case VCVTTPH2UWZ256rmbk:
18961 case VCVTTPH2UWZ256rmbkz:
18962 case VCVTTPH2UWZ256rmk:
18963 case VCVTTPH2UWZ256rmkz:
18964 case VCVTTPH2UWZ256rr:
18965 case VCVTTPH2UWZ256rrk:
18966 case VCVTTPH2UWZ256rrkz:
18967 case VCVTTPH2UWZrm:
18968 case VCVTTPH2UWZrmb:
18969 case VCVTTPH2UWZrmbk:
18970 case VCVTTPH2UWZrmbkz:
18971 case VCVTTPH2UWZrmk:
18972 case VCVTTPH2UWZrmkz:
18973 case VCVTTPH2UWZrr:
18974 case VCVTTPH2UWZrrb:
18975 case VCVTTPH2UWZrrbk:
18976 case VCVTTPH2UWZrrbkz:
18977 case VCVTTPH2UWZrrk:
18978 case VCVTTPH2UWZrrkz:
18979 return true;
18980 }
18981 return false;
18982}
18983
18984bool isVMFUNC(unsigned Opcode) {
18985 return Opcode == VMFUNC;
18986}
18987
18988bool isFIMUL(unsigned Opcode) {
18989 switch (Opcode) {
18990 case MUL_FI16m:
18991 case MUL_FI32m:
18992 return true;
18993 }
18994 return false;
18995}
18996
18997bool isBLCFILL(unsigned Opcode) {
18998 switch (Opcode) {
18999 case BLCFILL32rm:
19000 case BLCFILL32rr:
19001 case BLCFILL64rm:
19002 case BLCFILL64rr:
19003 return true;
19004 }
19005 return false;
19006}
19007
19008bool isVGATHERPF0DPS(unsigned Opcode) {
19009 return Opcode == VGATHERPF0DPSm;
19010}
19011
19012bool isVCVTHF82BF4S(unsigned Opcode) {
19013 switch (Opcode) {
19014 case VCVTHF82BF4SZ128mr:
19015 case VCVTHF82BF4SZ128rr:
19016 case VCVTHF82BF4SZ256mr:
19017 case VCVTHF82BF4SZ256rr:
19018 case VCVTHF82BF4SZmr:
19019 case VCVTHF82BF4SZrr:
19020 return true;
19021 }
19022 return false;
19023}
19024
19025bool isVFMSUBADD231PS(unsigned Opcode) {
19026 switch (Opcode) {
19027 case VFMSUBADD231PSYm:
19028 case VFMSUBADD231PSYr:
19029 case VFMSUBADD231PSZ128m:
19030 case VFMSUBADD231PSZ128mb:
19031 case VFMSUBADD231PSZ128mbk:
19032 case VFMSUBADD231PSZ128mbkz:
19033 case VFMSUBADD231PSZ128mk:
19034 case VFMSUBADD231PSZ128mkz:
19035 case VFMSUBADD231PSZ128r:
19036 case VFMSUBADD231PSZ128rk:
19037 case VFMSUBADD231PSZ128rkz:
19038 case VFMSUBADD231PSZ256m:
19039 case VFMSUBADD231PSZ256mb:
19040 case VFMSUBADD231PSZ256mbk:
19041 case VFMSUBADD231PSZ256mbkz:
19042 case VFMSUBADD231PSZ256mk:
19043 case VFMSUBADD231PSZ256mkz:
19044 case VFMSUBADD231PSZ256r:
19045 case VFMSUBADD231PSZ256rk:
19046 case VFMSUBADD231PSZ256rkz:
19047 case VFMSUBADD231PSZm:
19048 case VFMSUBADD231PSZmb:
19049 case VFMSUBADD231PSZmbk:
19050 case VFMSUBADD231PSZmbkz:
19051 case VFMSUBADD231PSZmk:
19052 case VFMSUBADD231PSZmkz:
19053 case VFMSUBADD231PSZr:
19054 case VFMSUBADD231PSZrb:
19055 case VFMSUBADD231PSZrbk:
19056 case VFMSUBADD231PSZrbkz:
19057 case VFMSUBADD231PSZrk:
19058 case VFMSUBADD231PSZrkz:
19059 case VFMSUBADD231PSm:
19060 case VFMSUBADD231PSr:
19061 return true;
19062 }
19063 return false;
19064}
19065
19066bool isVREDUCESD(unsigned Opcode) {
19067 switch (Opcode) {
19068 case VREDUCESDZrmi:
19069 case VREDUCESDZrmik:
19070 case VREDUCESDZrmikz:
19071 case VREDUCESDZrri:
19072 case VREDUCESDZrrib:
19073 case VREDUCESDZrribk:
19074 case VREDUCESDZrribkz:
19075 case VREDUCESDZrrik:
19076 case VREDUCESDZrrikz:
19077 return true;
19078 }
19079 return false;
19080}
19081
19082bool isVCOMXSH(unsigned Opcode) {
19083 switch (Opcode) {
19084 case VCOMXSHZrm_Int:
19085 case VCOMXSHZrr_Int:
19086 case VCOMXSHZrrb_Int:
19087 return true;
19088 }
19089 return false;
19090}
19091
19092bool isVXORPS(unsigned Opcode) {
19093 switch (Opcode) {
19094 case VXORPSYrm:
19095 case VXORPSYrr:
19096 case VXORPSZ128rm:
19097 case VXORPSZ128rmb:
19098 case VXORPSZ128rmbk:
19099 case VXORPSZ128rmbkz:
19100 case VXORPSZ128rmk:
19101 case VXORPSZ128rmkz:
19102 case VXORPSZ128rr:
19103 case VXORPSZ128rrk:
19104 case VXORPSZ128rrkz:
19105 case VXORPSZ256rm:
19106 case VXORPSZ256rmb:
19107 case VXORPSZ256rmbk:
19108 case VXORPSZ256rmbkz:
19109 case VXORPSZ256rmk:
19110 case VXORPSZ256rmkz:
19111 case VXORPSZ256rr:
19112 case VXORPSZ256rrk:
19113 case VXORPSZ256rrkz:
19114 case VXORPSZrm:
19115 case VXORPSZrmb:
19116 case VXORPSZrmbk:
19117 case VXORPSZrmbkz:
19118 case VXORPSZrmk:
19119 case VXORPSZrmkz:
19120 case VXORPSZrr:
19121 case VXORPSZrrk:
19122 case VXORPSZrrkz:
19123 case VXORPSrm:
19124 case VXORPSrr:
19125 return true;
19126 }
19127 return false;
19128}
19129
19130bool isPSWAPD(unsigned Opcode) {
19131 switch (Opcode) {
19132 case PSWAPDrm:
19133 case PSWAPDrr:
19134 return true;
19135 }
19136 return false;
19137}
19138
19139bool isPMAXSD(unsigned Opcode) {
19140 switch (Opcode) {
19141 case PMAXSDrm:
19142 case PMAXSDrr:
19143 return true;
19144 }
19145 return false;
19146}
19147
19148bool isVCMPSS(unsigned Opcode) {
19149 switch (Opcode) {
19150 case VCMPSSZrmi_Int:
19151 case VCMPSSZrmik_Int:
19152 case VCMPSSZrri_Int:
19153 case VCMPSSZrrib_Int:
19154 case VCMPSSZrribk_Int:
19155 case VCMPSSZrrik_Int:
19156 case VCMPSSrmi_Int:
19157 case VCMPSSrri_Int:
19158 return true;
19159 }
19160 return false;
19161}
19162
19163bool isEXTRACTPS(unsigned Opcode) {
19164 switch (Opcode) {
19165 case EXTRACTPSmri:
19166 case EXTRACTPSrri:
19167 return true;
19168 }
19169 return false;
19170}
19171
19172bool isVPMOVZXBD(unsigned Opcode) {
19173 switch (Opcode) {
19174 case VPMOVZXBDYrm:
19175 case VPMOVZXBDYrr:
19176 case VPMOVZXBDZ128rm:
19177 case VPMOVZXBDZ128rmk:
19178 case VPMOVZXBDZ128rmkz:
19179 case VPMOVZXBDZ128rr:
19180 case VPMOVZXBDZ128rrk:
19181 case VPMOVZXBDZ128rrkz:
19182 case VPMOVZXBDZ256rm:
19183 case VPMOVZXBDZ256rmk:
19184 case VPMOVZXBDZ256rmkz:
19185 case VPMOVZXBDZ256rr:
19186 case VPMOVZXBDZ256rrk:
19187 case VPMOVZXBDZ256rrkz:
19188 case VPMOVZXBDZrm:
19189 case VPMOVZXBDZrmk:
19190 case VPMOVZXBDZrmkz:
19191 case VPMOVZXBDZrr:
19192 case VPMOVZXBDZrrk:
19193 case VPMOVZXBDZrrkz:
19194 case VPMOVZXBDrm:
19195 case VPMOVZXBDrr:
19196 return true;
19197 }
19198 return false;
19199}
19200
19201bool isOUTSW(unsigned Opcode) {
19202 return Opcode == OUTSW;
19203}
19204
19205bool isKORTESTB(unsigned Opcode) {
19206 return Opcode == KORTESTBkk;
19207}
19208
19209bool isVREDUCEPS(unsigned Opcode) {
19210 switch (Opcode) {
19211 case VREDUCEPSZ128rmbi:
19212 case VREDUCEPSZ128rmbik:
19213 case VREDUCEPSZ128rmbikz:
19214 case VREDUCEPSZ128rmi:
19215 case VREDUCEPSZ128rmik:
19216 case VREDUCEPSZ128rmikz:
19217 case VREDUCEPSZ128rri:
19218 case VREDUCEPSZ128rrik:
19219 case VREDUCEPSZ128rrikz:
19220 case VREDUCEPSZ256rmbi:
19221 case VREDUCEPSZ256rmbik:
19222 case VREDUCEPSZ256rmbikz:
19223 case VREDUCEPSZ256rmi:
19224 case VREDUCEPSZ256rmik:
19225 case VREDUCEPSZ256rmikz:
19226 case VREDUCEPSZ256rri:
19227 case VREDUCEPSZ256rrik:
19228 case VREDUCEPSZ256rrikz:
19229 case VREDUCEPSZrmbi:
19230 case VREDUCEPSZrmbik:
19231 case VREDUCEPSZrmbikz:
19232 case VREDUCEPSZrmi:
19233 case VREDUCEPSZrmik:
19234 case VREDUCEPSZrmikz:
19235 case VREDUCEPSZrri:
19236 case VREDUCEPSZrrib:
19237 case VREDUCEPSZrribk:
19238 case VREDUCEPSZrribkz:
19239 case VREDUCEPSZrrik:
19240 case VREDUCEPSZrrikz:
19241 return true;
19242 }
19243 return false;
19244}
19245
19246bool isPEXTRW(unsigned Opcode) {
19247 switch (Opcode) {
19248 case MMX_PEXTRWrri:
19249 case PEXTRWmri:
19250 case PEXTRWrri:
19251 case PEXTRWrri_REV:
19252 return true;
19253 }
19254 return false;
19255}
19256
19257bool isFNINIT(unsigned Opcode) {
19258 return Opcode == FNINIT;
19259}
19260
19261bool isVCVTPH2IBS(unsigned Opcode) {
19262 switch (Opcode) {
19263 case VCVTPH2IBSZ128rm:
19264 case VCVTPH2IBSZ128rmb:
19265 case VCVTPH2IBSZ128rmbk:
19266 case VCVTPH2IBSZ128rmbkz:
19267 case VCVTPH2IBSZ128rmk:
19268 case VCVTPH2IBSZ128rmkz:
19269 case VCVTPH2IBSZ128rr:
19270 case VCVTPH2IBSZ128rrk:
19271 case VCVTPH2IBSZ128rrkz:
19272 case VCVTPH2IBSZ256rm:
19273 case VCVTPH2IBSZ256rmb:
19274 case VCVTPH2IBSZ256rmbk:
19275 case VCVTPH2IBSZ256rmbkz:
19276 case VCVTPH2IBSZ256rmk:
19277 case VCVTPH2IBSZ256rmkz:
19278 case VCVTPH2IBSZ256rr:
19279 case VCVTPH2IBSZ256rrk:
19280 case VCVTPH2IBSZ256rrkz:
19281 case VCVTPH2IBSZrm:
19282 case VCVTPH2IBSZrmb:
19283 case VCVTPH2IBSZrmbk:
19284 case VCVTPH2IBSZrmbkz:
19285 case VCVTPH2IBSZrmk:
19286 case VCVTPH2IBSZrmkz:
19287 case VCVTPH2IBSZrr:
19288 case VCVTPH2IBSZrrb:
19289 case VCVTPH2IBSZrrbk:
19290 case VCVTPH2IBSZrrbkz:
19291 case VCVTPH2IBSZrrk:
19292 case VCVTPH2IBSZrrkz:
19293 return true;
19294 }
19295 return false;
19296}
19297
19298bool isROL(unsigned Opcode) {
19299 switch (Opcode) {
19300 case ROL16m1:
19301 case ROL16m1_EVEX:
19302 case ROL16m1_ND:
19303 case ROL16m1_NF:
19304 case ROL16m1_NF_ND:
19305 case ROL16mCL:
19306 case ROL16mCL_EVEX:
19307 case ROL16mCL_ND:
19308 case ROL16mCL_NF:
19309 case ROL16mCL_NF_ND:
19310 case ROL16mi:
19311 case ROL16mi_EVEX:
19312 case ROL16mi_ND:
19313 case ROL16mi_NF:
19314 case ROL16mi_NF_ND:
19315 case ROL16r1:
19316 case ROL16r1_EVEX:
19317 case ROL16r1_ND:
19318 case ROL16r1_NF:
19319 case ROL16r1_NF_ND:
19320 case ROL16rCL:
19321 case ROL16rCL_EVEX:
19322 case ROL16rCL_ND:
19323 case ROL16rCL_NF:
19324 case ROL16rCL_NF_ND:
19325 case ROL16ri:
19326 case ROL16ri_EVEX:
19327 case ROL16ri_ND:
19328 case ROL16ri_NF:
19329 case ROL16ri_NF_ND:
19330 case ROL32m1:
19331 case ROL32m1_EVEX:
19332 case ROL32m1_ND:
19333 case ROL32m1_NF:
19334 case ROL32m1_NF_ND:
19335 case ROL32mCL:
19336 case ROL32mCL_EVEX:
19337 case ROL32mCL_ND:
19338 case ROL32mCL_NF:
19339 case ROL32mCL_NF_ND:
19340 case ROL32mi:
19341 case ROL32mi_EVEX:
19342 case ROL32mi_ND:
19343 case ROL32mi_NF:
19344 case ROL32mi_NF_ND:
19345 case ROL32r1:
19346 case ROL32r1_EVEX:
19347 case ROL32r1_ND:
19348 case ROL32r1_NF:
19349 case ROL32r1_NF_ND:
19350 case ROL32rCL:
19351 case ROL32rCL_EVEX:
19352 case ROL32rCL_ND:
19353 case ROL32rCL_NF:
19354 case ROL32rCL_NF_ND:
19355 case ROL32ri:
19356 case ROL32ri_EVEX:
19357 case ROL32ri_ND:
19358 case ROL32ri_NF:
19359 case ROL32ri_NF_ND:
19360 case ROL64m1:
19361 case ROL64m1_EVEX:
19362 case ROL64m1_ND:
19363 case ROL64m1_NF:
19364 case ROL64m1_NF_ND:
19365 case ROL64mCL:
19366 case ROL64mCL_EVEX:
19367 case ROL64mCL_ND:
19368 case ROL64mCL_NF:
19369 case ROL64mCL_NF_ND:
19370 case ROL64mi:
19371 case ROL64mi_EVEX:
19372 case ROL64mi_ND:
19373 case ROL64mi_NF:
19374 case ROL64mi_NF_ND:
19375 case ROL64r1:
19376 case ROL64r1_EVEX:
19377 case ROL64r1_ND:
19378 case ROL64r1_NF:
19379 case ROL64r1_NF_ND:
19380 case ROL64rCL:
19381 case ROL64rCL_EVEX:
19382 case ROL64rCL_ND:
19383 case ROL64rCL_NF:
19384 case ROL64rCL_NF_ND:
19385 case ROL64ri:
19386 case ROL64ri_EVEX:
19387 case ROL64ri_ND:
19388 case ROL64ri_NF:
19389 case ROL64ri_NF_ND:
19390 case ROL8m1:
19391 case ROL8m1_EVEX:
19392 case ROL8m1_ND:
19393 case ROL8m1_NF:
19394 case ROL8m1_NF_ND:
19395 case ROL8mCL:
19396 case ROL8mCL_EVEX:
19397 case ROL8mCL_ND:
19398 case ROL8mCL_NF:
19399 case ROL8mCL_NF_ND:
19400 case ROL8mi:
19401 case ROL8mi_EVEX:
19402 case ROL8mi_ND:
19403 case ROL8mi_NF:
19404 case ROL8mi_NF_ND:
19405 case ROL8r1:
19406 case ROL8r1_EVEX:
19407 case ROL8r1_ND:
19408 case ROL8r1_NF:
19409 case ROL8r1_NF_ND:
19410 case ROL8rCL:
19411 case ROL8rCL_EVEX:
19412 case ROL8rCL_ND:
19413 case ROL8rCL_NF:
19414 case ROL8rCL_NF_ND:
19415 case ROL8ri:
19416 case ROL8ri_EVEX:
19417 case ROL8ri_ND:
19418 case ROL8ri_NF:
19419 case ROL8ri_NF_ND:
19420 return true;
19421 }
19422 return false;
19423}
19424
19425bool isVCVTPS2QQ(unsigned Opcode) {
19426 switch (Opcode) {
19427 case VCVTPS2QQZ128rm:
19428 case VCVTPS2QQZ128rmb:
19429 case VCVTPS2QQZ128rmbk:
19430 case VCVTPS2QQZ128rmbkz:
19431 case VCVTPS2QQZ128rmk:
19432 case VCVTPS2QQZ128rmkz:
19433 case VCVTPS2QQZ128rr:
19434 case VCVTPS2QQZ128rrk:
19435 case VCVTPS2QQZ128rrkz:
19436 case VCVTPS2QQZ256rm:
19437 case VCVTPS2QQZ256rmb:
19438 case VCVTPS2QQZ256rmbk:
19439 case VCVTPS2QQZ256rmbkz:
19440 case VCVTPS2QQZ256rmk:
19441 case VCVTPS2QQZ256rmkz:
19442 case VCVTPS2QQZ256rr:
19443 case VCVTPS2QQZ256rrk:
19444 case VCVTPS2QQZ256rrkz:
19445 case VCVTPS2QQZrm:
19446 case VCVTPS2QQZrmb:
19447 case VCVTPS2QQZrmbk:
19448 case VCVTPS2QQZrmbkz:
19449 case VCVTPS2QQZrmk:
19450 case VCVTPS2QQZrmkz:
19451 case VCVTPS2QQZrr:
19452 case VCVTPS2QQZrrb:
19453 case VCVTPS2QQZrrbk:
19454 case VCVTPS2QQZrrbkz:
19455 case VCVTPS2QQZrrk:
19456 case VCVTPS2QQZrrkz:
19457 return true;
19458 }
19459 return false;
19460}
19461
19462bool isVGETMANTPH(unsigned Opcode) {
19463 switch (Opcode) {
19464 case VGETMANTPHZ128rmbi:
19465 case VGETMANTPHZ128rmbik:
19466 case VGETMANTPHZ128rmbikz:
19467 case VGETMANTPHZ128rmi:
19468 case VGETMANTPHZ128rmik:
19469 case VGETMANTPHZ128rmikz:
19470 case VGETMANTPHZ128rri:
19471 case VGETMANTPHZ128rrik:
19472 case VGETMANTPHZ128rrikz:
19473 case VGETMANTPHZ256rmbi:
19474 case VGETMANTPHZ256rmbik:
19475 case VGETMANTPHZ256rmbikz:
19476 case VGETMANTPHZ256rmi:
19477 case VGETMANTPHZ256rmik:
19478 case VGETMANTPHZ256rmikz:
19479 case VGETMANTPHZ256rri:
19480 case VGETMANTPHZ256rrik:
19481 case VGETMANTPHZ256rrikz:
19482 case VGETMANTPHZrmbi:
19483 case VGETMANTPHZrmbik:
19484 case VGETMANTPHZrmbikz:
19485 case VGETMANTPHZrmi:
19486 case VGETMANTPHZrmik:
19487 case VGETMANTPHZrmikz:
19488 case VGETMANTPHZrri:
19489 case VGETMANTPHZrrib:
19490 case VGETMANTPHZrribk:
19491 case VGETMANTPHZrribkz:
19492 case VGETMANTPHZrrik:
19493 case VGETMANTPHZrrikz:
19494 return true;
19495 }
19496 return false;
19497}
19498
19499bool isPUNPCKLDQ(unsigned Opcode) {
19500 switch (Opcode) {
19501 case MMX_PUNPCKLDQrm:
19502 case MMX_PUNPCKLDQrr:
19503 case PUNPCKLDQrm:
19504 case PUNPCKLDQrr:
19505 return true;
19506 }
19507 return false;
19508}
19509
19510bool isPADDD(unsigned Opcode) {
19511 switch (Opcode) {
19512 case MMX_PADDDrm:
19513 case MMX_PADDDrr:
19514 case PADDDrm:
19515 case PADDDrr:
19516 return true;
19517 }
19518 return false;
19519}
19520
19521bool isVPSLLD(unsigned Opcode) {
19522 switch (Opcode) {
19523 case VPSLLDYri:
19524 case VPSLLDYrm:
19525 case VPSLLDYrr:
19526 case VPSLLDZ128mbi:
19527 case VPSLLDZ128mbik:
19528 case VPSLLDZ128mbikz:
19529 case VPSLLDZ128mi:
19530 case VPSLLDZ128mik:
19531 case VPSLLDZ128mikz:
19532 case VPSLLDZ128ri:
19533 case VPSLLDZ128rik:
19534 case VPSLLDZ128rikz:
19535 case VPSLLDZ128rm:
19536 case VPSLLDZ128rmk:
19537 case VPSLLDZ128rmkz:
19538 case VPSLLDZ128rr:
19539 case VPSLLDZ128rrk:
19540 case VPSLLDZ128rrkz:
19541 case VPSLLDZ256mbi:
19542 case VPSLLDZ256mbik:
19543 case VPSLLDZ256mbikz:
19544 case VPSLLDZ256mi:
19545 case VPSLLDZ256mik:
19546 case VPSLLDZ256mikz:
19547 case VPSLLDZ256ri:
19548 case VPSLLDZ256rik:
19549 case VPSLLDZ256rikz:
19550 case VPSLLDZ256rm:
19551 case VPSLLDZ256rmk:
19552 case VPSLLDZ256rmkz:
19553 case VPSLLDZ256rr:
19554 case VPSLLDZ256rrk:
19555 case VPSLLDZ256rrkz:
19556 case VPSLLDZmbi:
19557 case VPSLLDZmbik:
19558 case VPSLLDZmbikz:
19559 case VPSLLDZmi:
19560 case VPSLLDZmik:
19561 case VPSLLDZmikz:
19562 case VPSLLDZri:
19563 case VPSLLDZrik:
19564 case VPSLLDZrikz:
19565 case VPSLLDZrm:
19566 case VPSLLDZrmk:
19567 case VPSLLDZrmkz:
19568 case VPSLLDZrr:
19569 case VPSLLDZrrk:
19570 case VPSLLDZrrkz:
19571 case VPSLLDri:
19572 case VPSLLDrm:
19573 case VPSLLDrr:
19574 return true;
19575 }
19576 return false;
19577}
19578
19579bool isPFCMPGE(unsigned Opcode) {
19580 switch (Opcode) {
19581 case PFCMPGErm:
19582 case PFCMPGErr:
19583 return true;
19584 }
19585 return false;
19586}
19587
19588bool isVGETMANTBF16(unsigned Opcode) {
19589 switch (Opcode) {
19590 case VGETMANTBF16Z128rmbi:
19591 case VGETMANTBF16Z128rmbik:
19592 case VGETMANTBF16Z128rmbikz:
19593 case VGETMANTBF16Z128rmi:
19594 case VGETMANTBF16Z128rmik:
19595 case VGETMANTBF16Z128rmikz:
19596 case VGETMANTBF16Z128rri:
19597 case VGETMANTBF16Z128rrik:
19598 case VGETMANTBF16Z128rrikz:
19599 case VGETMANTBF16Z256rmbi:
19600 case VGETMANTBF16Z256rmbik:
19601 case VGETMANTBF16Z256rmbikz:
19602 case VGETMANTBF16Z256rmi:
19603 case VGETMANTBF16Z256rmik:
19604 case VGETMANTBF16Z256rmikz:
19605 case VGETMANTBF16Z256rri:
19606 case VGETMANTBF16Z256rrik:
19607 case VGETMANTBF16Z256rrikz:
19608 case VGETMANTBF16Zrmbi:
19609 case VGETMANTBF16Zrmbik:
19610 case VGETMANTBF16Zrmbikz:
19611 case VGETMANTBF16Zrmi:
19612 case VGETMANTBF16Zrmik:
19613 case VGETMANTBF16Zrmikz:
19614 case VGETMANTBF16Zrri:
19615 case VGETMANTBF16Zrrik:
19616 case VGETMANTBF16Zrrikz:
19617 return true;
19618 }
19619 return false;
19620}
19621
19622bool isVSUBBF16(unsigned Opcode) {
19623 switch (Opcode) {
19624 case VSUBBF16Z128rm:
19625 case VSUBBF16Z128rmb:
19626 case VSUBBF16Z128rmbk:
19627 case VSUBBF16Z128rmbkz:
19628 case VSUBBF16Z128rmk:
19629 case VSUBBF16Z128rmkz:
19630 case VSUBBF16Z128rr:
19631 case VSUBBF16Z128rrk:
19632 case VSUBBF16Z128rrkz:
19633 case VSUBBF16Z256rm:
19634 case VSUBBF16Z256rmb:
19635 case VSUBBF16Z256rmbk:
19636 case VSUBBF16Z256rmbkz:
19637 case VSUBBF16Z256rmk:
19638 case VSUBBF16Z256rmkz:
19639 case VSUBBF16Z256rr:
19640 case VSUBBF16Z256rrk:
19641 case VSUBBF16Z256rrkz:
19642 case VSUBBF16Zrm:
19643 case VSUBBF16Zrmb:
19644 case VSUBBF16Zrmbk:
19645 case VSUBBF16Zrmbkz:
19646 case VSUBBF16Zrmk:
19647 case VSUBBF16Zrmkz:
19648 case VSUBBF16Zrr:
19649 case VSUBBF16Zrrk:
19650 case VSUBBF16Zrrkz:
19651 return true;
19652 }
19653 return false;
19654}
19655
19656bool isVPMOVM2D(unsigned Opcode) {
19657 switch (Opcode) {
19658 case VPMOVM2DZ128rk:
19659 case VPMOVM2DZ256rk:
19660 case VPMOVM2DZrk:
19661 return true;
19662 }
19663 return false;
19664}
19665
19666bool isVCVTTSS2USIS(unsigned Opcode) {
19667 switch (Opcode) {
19668 case VCVTTSS2USI64Srm_Int:
19669 case VCVTTSS2USI64Srr_Int:
19670 case VCVTTSS2USI64Srrb_Int:
19671 case VCVTTSS2USISrm_Int:
19672 case VCVTTSS2USISrr_Int:
19673 case VCVTTSS2USISrrb_Int:
19674 return true;
19675 }
19676 return false;
19677}
19678
19679bool isVHSUBPS(unsigned Opcode) {
19680 switch (Opcode) {
19681 case VHSUBPSYrm:
19682 case VHSUBPSYrr:
19683 case VHSUBPSrm:
19684 case VHSUBPSrr:
19685 return true;
19686 }
19687 return false;
19688}
19689
19690bool isENDBR32(unsigned Opcode) {
19691 return Opcode == ENDBR32;
19692}
19693
19694bool isMOVSXD(unsigned Opcode) {
19695 switch (Opcode) {
19696 case MOVSX16rm32:
19697 case MOVSX16rr32:
19698 case MOVSX32rm32:
19699 case MOVSX32rr32:
19700 case MOVSX64rm32:
19701 case MOVSX64rr32:
19702 return true;
19703 }
19704 return false;
19705}
19706
19707bool isPSIGND(unsigned Opcode) {
19708 switch (Opcode) {
19709 case MMX_PSIGNDrm:
19710 case MMX_PSIGNDrr:
19711 case PSIGNDrm:
19712 case PSIGNDrr:
19713 return true;
19714 }
19715 return false;
19716}
19717
19718bool isVPTEST(unsigned Opcode) {
19719 switch (Opcode) {
19720 case VPTESTYrm:
19721 case VPTESTYrr:
19722 case VPTESTrm:
19723 case VPTESTrr:
19724 return true;
19725 }
19726 return false;
19727}
19728
19729bool isVPDPWUSD(unsigned Opcode) {
19730 switch (Opcode) {
19731 case VPDPWUSDYrm:
19732 case VPDPWUSDYrr:
19733 case VPDPWUSDZ128rm:
19734 case VPDPWUSDZ128rmb:
19735 case VPDPWUSDZ128rmbk:
19736 case VPDPWUSDZ128rmbkz:
19737 case VPDPWUSDZ128rmk:
19738 case VPDPWUSDZ128rmkz:
19739 case VPDPWUSDZ128rr:
19740 case VPDPWUSDZ128rrk:
19741 case VPDPWUSDZ128rrkz:
19742 case VPDPWUSDZ256rm:
19743 case VPDPWUSDZ256rmb:
19744 case VPDPWUSDZ256rmbk:
19745 case VPDPWUSDZ256rmbkz:
19746 case VPDPWUSDZ256rmk:
19747 case VPDPWUSDZ256rmkz:
19748 case VPDPWUSDZ256rr:
19749 case VPDPWUSDZ256rrk:
19750 case VPDPWUSDZ256rrkz:
19751 case VPDPWUSDZrm:
19752 case VPDPWUSDZrmb:
19753 case VPDPWUSDZrmbk:
19754 case VPDPWUSDZrmbkz:
19755 case VPDPWUSDZrmk:
19756 case VPDPWUSDZrmkz:
19757 case VPDPWUSDZrr:
19758 case VPDPWUSDZrrk:
19759 case VPDPWUSDZrrkz:
19760 case VPDPWUSDrm:
19761 case VPDPWUSDrr:
19762 return true;
19763 }
19764 return false;
19765}
19766
19767bool isHSUBPD(unsigned Opcode) {
19768 switch (Opcode) {
19769 case HSUBPDrm:
19770 case HSUBPDrr:
19771 return true;
19772 }
19773 return false;
19774}
19775
19776bool isADCX(unsigned Opcode) {
19777 switch (Opcode) {
19778 case ADCX32rm:
19779 case ADCX32rm_EVEX:
19780 case ADCX32rm_ND:
19781 case ADCX32rr:
19782 case ADCX32rr_EVEX:
19783 case ADCX32rr_ND:
19784 case ADCX64rm:
19785 case ADCX64rm_EVEX:
19786 case ADCX64rm_ND:
19787 case ADCX64rr:
19788 case ADCX64rr_EVEX:
19789 case ADCX64rr_ND:
19790 return true;
19791 }
19792 return false;
19793}
19794
19795bool isCVTTPD2PI(unsigned Opcode) {
19796 switch (Opcode) {
19797 case MMX_CVTTPD2PIrm:
19798 case MMX_CVTTPD2PIrr:
19799 return true;
19800 }
19801 return false;
19802}
19803
19804bool isPDEP(unsigned Opcode) {
19805 switch (Opcode) {
19806 case PDEP32rm:
19807 case PDEP32rm_EVEX:
19808 case PDEP32rr:
19809 case PDEP32rr_EVEX:
19810 case PDEP64rm:
19811 case PDEP64rm_EVEX:
19812 case PDEP64rr:
19813 case PDEP64rr_EVEX:
19814 return true;
19815 }
19816 return false;
19817}
19818
19819bool isTDPBUSD(unsigned Opcode) {
19820 return Opcode == TDPBUSD;
19821}
19822
19823bool isVCVTBIASPH2HF8S(unsigned Opcode) {
19824 switch (Opcode) {
19825 case VCVTBIASPH2HF8SZ128rm:
19826 case VCVTBIASPH2HF8SZ128rmb:
19827 case VCVTBIASPH2HF8SZ128rmbk:
19828 case VCVTBIASPH2HF8SZ128rmbkz:
19829 case VCVTBIASPH2HF8SZ128rmk:
19830 case VCVTBIASPH2HF8SZ128rmkz:
19831 case VCVTBIASPH2HF8SZ128rr:
19832 case VCVTBIASPH2HF8SZ128rrk:
19833 case VCVTBIASPH2HF8SZ128rrkz:
19834 case VCVTBIASPH2HF8SZ256rm:
19835 case VCVTBIASPH2HF8SZ256rmb:
19836 case VCVTBIASPH2HF8SZ256rmbk:
19837 case VCVTBIASPH2HF8SZ256rmbkz:
19838 case VCVTBIASPH2HF8SZ256rmk:
19839 case VCVTBIASPH2HF8SZ256rmkz:
19840 case VCVTBIASPH2HF8SZ256rr:
19841 case VCVTBIASPH2HF8SZ256rrk:
19842 case VCVTBIASPH2HF8SZ256rrkz:
19843 case VCVTBIASPH2HF8SZrm:
19844 case VCVTBIASPH2HF8SZrmb:
19845 case VCVTBIASPH2HF8SZrmbk:
19846 case VCVTBIASPH2HF8SZrmbkz:
19847 case VCVTBIASPH2HF8SZrmk:
19848 case VCVTBIASPH2HF8SZrmkz:
19849 case VCVTBIASPH2HF8SZrr:
19850 case VCVTBIASPH2HF8SZrrk:
19851 case VCVTBIASPH2HF8SZrrkz:
19852 return true;
19853 }
19854 return false;
19855}
19856
19857bool isVBROADCASTI32X4(unsigned Opcode) {
19858 switch (Opcode) {
19859 case VBROADCASTI32X4Z256rm:
19860 case VBROADCASTI32X4Z256rmk:
19861 case VBROADCASTI32X4Z256rmkz:
19862 case VBROADCASTI32X4Zrm:
19863 case VBROADCASTI32X4Zrmk:
19864 case VBROADCASTI32X4Zrmkz:
19865 return true;
19866 }
19867 return false;
19868}
19869
19870bool isVCVTPH2UDQ(unsigned Opcode) {
19871 switch (Opcode) {
19872 case VCVTPH2UDQZ128rm:
19873 case VCVTPH2UDQZ128rmb:
19874 case VCVTPH2UDQZ128rmbk:
19875 case VCVTPH2UDQZ128rmbkz:
19876 case VCVTPH2UDQZ128rmk:
19877 case VCVTPH2UDQZ128rmkz:
19878 case VCVTPH2UDQZ128rr:
19879 case VCVTPH2UDQZ128rrk:
19880 case VCVTPH2UDQZ128rrkz:
19881 case VCVTPH2UDQZ256rm:
19882 case VCVTPH2UDQZ256rmb:
19883 case VCVTPH2UDQZ256rmbk:
19884 case VCVTPH2UDQZ256rmbkz:
19885 case VCVTPH2UDQZ256rmk:
19886 case VCVTPH2UDQZ256rmkz:
19887 case VCVTPH2UDQZ256rr:
19888 case VCVTPH2UDQZ256rrk:
19889 case VCVTPH2UDQZ256rrkz:
19890 case VCVTPH2UDQZrm:
19891 case VCVTPH2UDQZrmb:
19892 case VCVTPH2UDQZrmbk:
19893 case VCVTPH2UDQZrmbkz:
19894 case VCVTPH2UDQZrmk:
19895 case VCVTPH2UDQZrmkz:
19896 case VCVTPH2UDQZrr:
19897 case VCVTPH2UDQZrrb:
19898 case VCVTPH2UDQZrrbk:
19899 case VCVTPH2UDQZrrbkz:
19900 case VCVTPH2UDQZrrk:
19901 case VCVTPH2UDQZrrkz:
19902 return true;
19903 }
19904 return false;
19905}
19906
19907bool isVPHADDW(unsigned Opcode) {
19908 switch (Opcode) {
19909 case VPHADDWYrm:
19910 case VPHADDWYrr:
19911 case VPHADDWrm:
19912 case VPHADDWrr:
19913 return true;
19914 }
19915 return false;
19916}
19917
19918bool isFLDL2E(unsigned Opcode) {
19919 return Opcode == FLDL2E;
19920}
19921
19922bool isCLZERO(unsigned Opcode) {
19923 switch (Opcode) {
19924 case CLZERO32r:
19925 case CLZERO64r:
19926 return true;
19927 }
19928 return false;
19929}
19930
19931bool isPBLENDW(unsigned Opcode) {
19932 switch (Opcode) {
19933 case PBLENDWrmi:
19934 case PBLENDWrri:
19935 return true;
19936 }
19937 return false;
19938}
19939
19940bool isVCVTBF162IUBS(unsigned Opcode) {
19941 switch (Opcode) {
19942 case VCVTBF162IUBSZ128rm:
19943 case VCVTBF162IUBSZ128rmb:
19944 case VCVTBF162IUBSZ128rmbk:
19945 case VCVTBF162IUBSZ128rmbkz:
19946 case VCVTBF162IUBSZ128rmk:
19947 case VCVTBF162IUBSZ128rmkz:
19948 case VCVTBF162IUBSZ128rr:
19949 case VCVTBF162IUBSZ128rrk:
19950 case VCVTBF162IUBSZ128rrkz:
19951 case VCVTBF162IUBSZ256rm:
19952 case VCVTBF162IUBSZ256rmb:
19953 case VCVTBF162IUBSZ256rmbk:
19954 case VCVTBF162IUBSZ256rmbkz:
19955 case VCVTBF162IUBSZ256rmk:
19956 case VCVTBF162IUBSZ256rmkz:
19957 case VCVTBF162IUBSZ256rr:
19958 case VCVTBF162IUBSZ256rrk:
19959 case VCVTBF162IUBSZ256rrkz:
19960 case VCVTBF162IUBSZrm:
19961 case VCVTBF162IUBSZrmb:
19962 case VCVTBF162IUBSZrmbk:
19963 case VCVTBF162IUBSZrmbkz:
19964 case VCVTBF162IUBSZrmk:
19965 case VCVTBF162IUBSZrmkz:
19966 case VCVTBF162IUBSZrr:
19967 case VCVTBF162IUBSZrrk:
19968 case VCVTBF162IUBSZrrkz:
19969 return true;
19970 }
19971 return false;
19972}
19973
19974bool isVCVTSH2USI(unsigned Opcode) {
19975 switch (Opcode) {
19976 case VCVTSH2USI64Zrm_Int:
19977 case VCVTSH2USI64Zrr_Int:
19978 case VCVTSH2USI64Zrrb_Int:
19979 case VCVTSH2USIZrm_Int:
19980 case VCVTSH2USIZrr_Int:
19981 case VCVTSH2USIZrrb_Int:
19982 return true;
19983 }
19984 return false;
19985}
19986
19987bool isVANDPD(unsigned Opcode) {
19988 switch (Opcode) {
19989 case VANDPDYrm:
19990 case VANDPDYrr:
19991 case VANDPDZ128rm:
19992 case VANDPDZ128rmb:
19993 case VANDPDZ128rmbk:
19994 case VANDPDZ128rmbkz:
19995 case VANDPDZ128rmk:
19996 case VANDPDZ128rmkz:
19997 case VANDPDZ128rr:
19998 case VANDPDZ128rrk:
19999 case VANDPDZ128rrkz:
20000 case VANDPDZ256rm:
20001 case VANDPDZ256rmb:
20002 case VANDPDZ256rmbk:
20003 case VANDPDZ256rmbkz:
20004 case VANDPDZ256rmk:
20005 case VANDPDZ256rmkz:
20006 case VANDPDZ256rr:
20007 case VANDPDZ256rrk:
20008 case VANDPDZ256rrkz:
20009 case VANDPDZrm:
20010 case VANDPDZrmb:
20011 case VANDPDZrmbk:
20012 case VANDPDZrmbkz:
20013 case VANDPDZrmk:
20014 case VANDPDZrmkz:
20015 case VANDPDZrr:
20016 case VANDPDZrrk:
20017 case VANDPDZrrkz:
20018 case VANDPDrm:
20019 case VANDPDrr:
20020 return true;
20021 }
20022 return false;
20023}
20024
20025bool isBEXTR(unsigned Opcode) {
20026 switch (Opcode) {
20027 case BEXTR32rm:
20028 case BEXTR32rm_EVEX:
20029 case BEXTR32rm_NF:
20030 case BEXTR32rr:
20031 case BEXTR32rr_EVEX:
20032 case BEXTR32rr_NF:
20033 case BEXTR64rm:
20034 case BEXTR64rm_EVEX:
20035 case BEXTR64rm_NF:
20036 case BEXTR64rr:
20037 case BEXTR64rr_EVEX:
20038 case BEXTR64rr_NF:
20039 case BEXTRI32mi:
20040 case BEXTRI32ri:
20041 case BEXTRI64mi:
20042 case BEXTRI64ri:
20043 return true;
20044 }
20045 return false;
20046}
20047
20048bool isSTD(unsigned Opcode) {
20049 return Opcode == STD;
20050}
20051
20052bool isVAESKEYGENASSIST(unsigned Opcode) {
20053 switch (Opcode) {
20054 case VAESKEYGENASSISTrmi:
20055 case VAESKEYGENASSISTrri:
20056 return true;
20057 }
20058 return false;
20059}
20060
20061bool isCMPSD(unsigned Opcode) {
20062 switch (Opcode) {
20063 case CMPSDrmi_Int:
20064 case CMPSDrri_Int:
20065 case CMPSL:
20066 return true;
20067 }
20068 return false;
20069}
20070
20071bool isMOVSS(unsigned Opcode) {
20072 switch (Opcode) {
20073 case MOVSSmr:
20074 case MOVSSrm:
20075 case MOVSSrr:
20076 case MOVSSrr_REV:
20077 return true;
20078 }
20079 return false;
20080}
20081
20082bool isVCVTUQQ2PD(unsigned Opcode) {
20083 switch (Opcode) {
20084 case VCVTUQQ2PDZ128rm:
20085 case VCVTUQQ2PDZ128rmb:
20086 case VCVTUQQ2PDZ128rmbk:
20087 case VCVTUQQ2PDZ128rmbkz:
20088 case VCVTUQQ2PDZ128rmk:
20089 case VCVTUQQ2PDZ128rmkz:
20090 case VCVTUQQ2PDZ128rr:
20091 case VCVTUQQ2PDZ128rrk:
20092 case VCVTUQQ2PDZ128rrkz:
20093 case VCVTUQQ2PDZ256rm:
20094 case VCVTUQQ2PDZ256rmb:
20095 case VCVTUQQ2PDZ256rmbk:
20096 case VCVTUQQ2PDZ256rmbkz:
20097 case VCVTUQQ2PDZ256rmk:
20098 case VCVTUQQ2PDZ256rmkz:
20099 case VCVTUQQ2PDZ256rr:
20100 case VCVTUQQ2PDZ256rrk:
20101 case VCVTUQQ2PDZ256rrkz:
20102 case VCVTUQQ2PDZrm:
20103 case VCVTUQQ2PDZrmb:
20104 case VCVTUQQ2PDZrmbk:
20105 case VCVTUQQ2PDZrmbkz:
20106 case VCVTUQQ2PDZrmk:
20107 case VCVTUQQ2PDZrmkz:
20108 case VCVTUQQ2PDZrr:
20109 case VCVTUQQ2PDZrrb:
20110 case VCVTUQQ2PDZrrbk:
20111 case VCVTUQQ2PDZrrbkz:
20112 case VCVTUQQ2PDZrrk:
20113 case VCVTUQQ2PDZrrkz:
20114 return true;
20115 }
20116 return false;
20117}
20118
20119bool isVEXTRACTI32X4(unsigned Opcode) {
20120 switch (Opcode) {
20121 case VEXTRACTI32X4Z256mri:
20122 case VEXTRACTI32X4Z256mrik:
20123 case VEXTRACTI32X4Z256rri:
20124 case VEXTRACTI32X4Z256rrik:
20125 case VEXTRACTI32X4Z256rrikz:
20126 case VEXTRACTI32X4Zmri:
20127 case VEXTRACTI32X4Zmrik:
20128 case VEXTRACTI32X4Zrri:
20129 case VEXTRACTI32X4Zrrik:
20130 case VEXTRACTI32X4Zrrikz:
20131 return true;
20132 }
20133 return false;
20134}
20135
20136bool isFLDCW(unsigned Opcode) {
20137 return Opcode == FLDCW16m;
20138}
20139
20140bool isINSW(unsigned Opcode) {
20141 return Opcode == INSW;
20142}
20143
20144bool isRDPID(unsigned Opcode) {
20145 switch (Opcode) {
20146 case RDPID32:
20147 case RDPID64:
20148 return true;
20149 }
20150 return false;
20151}
20152
20153bool isVUCOMXSS(unsigned Opcode) {
20154 switch (Opcode) {
20155 case VUCOMXSSZrm_Int:
20156 case VUCOMXSSZrr_Int:
20157 case VUCOMXSSZrrb_Int:
20158 return true;
20159 }
20160 return false;
20161}
20162
20163bool isKANDQ(unsigned Opcode) {
20164 return Opcode == KANDQkk;
20165}
20166
20167bool isV4FMADDPS(unsigned Opcode) {
20168 switch (Opcode) {
20169 case V4FMADDPSrm:
20170 case V4FMADDPSrmk:
20171 case V4FMADDPSrmkz:
20172 return true;
20173 }
20174 return false;
20175}
20176
20177bool isPMOVZXWQ(unsigned Opcode) {
20178 switch (Opcode) {
20179 case PMOVZXWQrm:
20180 case PMOVZXWQrr:
20181 return true;
20182 }
20183 return false;
20184}
20185
20186bool isVFPCLASSSD(unsigned Opcode) {
20187 switch (Opcode) {
20188 case VFPCLASSSDZmi:
20189 case VFPCLASSSDZmik:
20190 case VFPCLASSSDZri:
20191 case VFPCLASSSDZrik:
20192 return true;
20193 }
20194 return false;
20195}
20196
20197bool isBLENDPS(unsigned Opcode) {
20198 switch (Opcode) {
20199 case BLENDPSrmi:
20200 case BLENDPSrri:
20201 return true;
20202 }
20203 return false;
20204}
20205
20206bool isVPACKSSDW(unsigned Opcode) {
20207 switch (Opcode) {
20208 case VPACKSSDWYrm:
20209 case VPACKSSDWYrr:
20210 case VPACKSSDWZ128rm:
20211 case VPACKSSDWZ128rmb:
20212 case VPACKSSDWZ128rmbk:
20213 case VPACKSSDWZ128rmbkz:
20214 case VPACKSSDWZ128rmk:
20215 case VPACKSSDWZ128rmkz:
20216 case VPACKSSDWZ128rr:
20217 case VPACKSSDWZ128rrk:
20218 case VPACKSSDWZ128rrkz:
20219 case VPACKSSDWZ256rm:
20220 case VPACKSSDWZ256rmb:
20221 case VPACKSSDWZ256rmbk:
20222 case VPACKSSDWZ256rmbkz:
20223 case VPACKSSDWZ256rmk:
20224 case VPACKSSDWZ256rmkz:
20225 case VPACKSSDWZ256rr:
20226 case VPACKSSDWZ256rrk:
20227 case VPACKSSDWZ256rrkz:
20228 case VPACKSSDWZrm:
20229 case VPACKSSDWZrmb:
20230 case VPACKSSDWZrmbk:
20231 case VPACKSSDWZrmbkz:
20232 case VPACKSSDWZrmk:
20233 case VPACKSSDWZrmkz:
20234 case VPACKSSDWZrr:
20235 case VPACKSSDWZrrk:
20236 case VPACKSSDWZrrkz:
20237 case VPACKSSDWrm:
20238 case VPACKSSDWrr:
20239 return true;
20240 }
20241 return false;
20242}
20243
20244bool isVPHSUBBW(unsigned Opcode) {
20245 switch (Opcode) {
20246 case VPHSUBBWrm:
20247 case VPHSUBBWrr:
20248 return true;
20249 }
20250 return false;
20251}
20252
20253bool isVPINSRW(unsigned Opcode) {
20254 switch (Opcode) {
20255 case VPINSRWZrmi:
20256 case VPINSRWZrri:
20257 case VPINSRWrmi:
20258 case VPINSRWrri:
20259 return true;
20260 }
20261 return false;
20262}
20263
20264bool isVMINMAXBF16(unsigned Opcode) {
20265 switch (Opcode) {
20266 case VMINMAXBF16Z128rmbi:
20267 case VMINMAXBF16Z128rmbik:
20268 case VMINMAXBF16Z128rmbikz:
20269 case VMINMAXBF16Z128rmi:
20270 case VMINMAXBF16Z128rmik:
20271 case VMINMAXBF16Z128rmikz:
20272 case VMINMAXBF16Z128rri:
20273 case VMINMAXBF16Z128rrik:
20274 case VMINMAXBF16Z128rrikz:
20275 case VMINMAXBF16Z256rmbi:
20276 case VMINMAXBF16Z256rmbik:
20277 case VMINMAXBF16Z256rmbikz:
20278 case VMINMAXBF16Z256rmi:
20279 case VMINMAXBF16Z256rmik:
20280 case VMINMAXBF16Z256rmikz:
20281 case VMINMAXBF16Z256rri:
20282 case VMINMAXBF16Z256rrik:
20283 case VMINMAXBF16Z256rrikz:
20284 case VMINMAXBF16Zrmbi:
20285 case VMINMAXBF16Zrmbik:
20286 case VMINMAXBF16Zrmbikz:
20287 case VMINMAXBF16Zrmi:
20288 case VMINMAXBF16Zrmik:
20289 case VMINMAXBF16Zrmikz:
20290 case VMINMAXBF16Zrri:
20291 case VMINMAXBF16Zrrik:
20292 case VMINMAXBF16Zrrikz:
20293 return true;
20294 }
20295 return false;
20296}
20297
20298bool isVSHUFF64X2(unsigned Opcode) {
20299 switch (Opcode) {
20300 case VSHUFF64X2Z256rmbi:
20301 case VSHUFF64X2Z256rmbik:
20302 case VSHUFF64X2Z256rmbikz:
20303 case VSHUFF64X2Z256rmi:
20304 case VSHUFF64X2Z256rmik:
20305 case VSHUFF64X2Z256rmikz:
20306 case VSHUFF64X2Z256rri:
20307 case VSHUFF64X2Z256rrik:
20308 case VSHUFF64X2Z256rrikz:
20309 case VSHUFF64X2Zrmbi:
20310 case VSHUFF64X2Zrmbik:
20311 case VSHUFF64X2Zrmbikz:
20312 case VSHUFF64X2Zrmi:
20313 case VSHUFF64X2Zrmik:
20314 case VSHUFF64X2Zrmikz:
20315 case VSHUFF64X2Zrri:
20316 case VSHUFF64X2Zrrik:
20317 case VSHUFF64X2Zrrikz:
20318 return true;
20319 }
20320 return false;
20321}
20322
20323bool isVPACKUSWB(unsigned Opcode) {
20324 switch (Opcode) {
20325 case VPACKUSWBYrm:
20326 case VPACKUSWBYrr:
20327 case VPACKUSWBZ128rm:
20328 case VPACKUSWBZ128rmk:
20329 case VPACKUSWBZ128rmkz:
20330 case VPACKUSWBZ128rr:
20331 case VPACKUSWBZ128rrk:
20332 case VPACKUSWBZ128rrkz:
20333 case VPACKUSWBZ256rm:
20334 case VPACKUSWBZ256rmk:
20335 case VPACKUSWBZ256rmkz:
20336 case VPACKUSWBZ256rr:
20337 case VPACKUSWBZ256rrk:
20338 case VPACKUSWBZ256rrkz:
20339 case VPACKUSWBZrm:
20340 case VPACKUSWBZrmk:
20341 case VPACKUSWBZrmkz:
20342 case VPACKUSWBZrr:
20343 case VPACKUSWBZrrk:
20344 case VPACKUSWBZrrkz:
20345 case VPACKUSWBrm:
20346 case VPACKUSWBrr:
20347 return true;
20348 }
20349 return false;
20350}
20351
20352bool isVRSQRT28SS(unsigned Opcode) {
20353 switch (Opcode) {
20354 case VRSQRT28SSZm:
20355 case VRSQRT28SSZmk:
20356 case VRSQRT28SSZmkz:
20357 case VRSQRT28SSZr:
20358 case VRSQRT28SSZrb:
20359 case VRSQRT28SSZrbk:
20360 case VRSQRT28SSZrbkz:
20361 case VRSQRT28SSZrk:
20362 case VRSQRT28SSZrkz:
20363 return true;
20364 }
20365 return false;
20366}
20367
20368bool isGETSEC(unsigned Opcode) {
20369 return Opcode == GETSEC;
20370}
20371
20372bool isFXAM(unsigned Opcode) {
20373 return Opcode == XAM_F;
20374}
20375
20376bool isVEXTRACTF64X4(unsigned Opcode) {
20377 switch (Opcode) {
20378 case VEXTRACTF64X4Zmri:
20379 case VEXTRACTF64X4Zmrik:
20380 case VEXTRACTF64X4Zrri:
20381 case VEXTRACTF64X4Zrrik:
20382 case VEXTRACTF64X4Zrrikz:
20383 return true;
20384 }
20385 return false;
20386}
20387
20388bool isBLSR(unsigned Opcode) {
20389 switch (Opcode) {
20390 case BLSR32rm:
20391 case BLSR32rm_EVEX:
20392 case BLSR32rm_NF:
20393 case BLSR32rr:
20394 case BLSR32rr_EVEX:
20395 case BLSR32rr_NF:
20396 case BLSR64rm:
20397 case BLSR64rm_EVEX:
20398 case BLSR64rm_NF:
20399 case BLSR64rr:
20400 case BLSR64rr_EVEX:
20401 case BLSR64rr_NF:
20402 return true;
20403 }
20404 return false;
20405}
20406
20407bool isFILD(unsigned Opcode) {
20408 switch (Opcode) {
20409 case ILD_F16m:
20410 case ILD_F32m:
20411 case ILD_F64m:
20412 return true;
20413 }
20414 return false;
20415}
20416
20417bool isRETFQ(unsigned Opcode) {
20418 switch (Opcode) {
20419 case LRET64:
20420 case LRETI64:
20421 return true;
20422 }
20423 return false;
20424}
20425
20426bool isVADDSS(unsigned Opcode) {
20427 switch (Opcode) {
20428 case VADDSSZrm_Int:
20429 case VADDSSZrmk_Int:
20430 case VADDSSZrmkz_Int:
20431 case VADDSSZrr_Int:
20432 case VADDSSZrrb_Int:
20433 case VADDSSZrrbk_Int:
20434 case VADDSSZrrbkz_Int:
20435 case VADDSSZrrk_Int:
20436 case VADDSSZrrkz_Int:
20437 case VADDSSrm_Int:
20438 case VADDSSrr_Int:
20439 return true;
20440 }
20441 return false;
20442}
20443
20444bool isCOMISS(unsigned Opcode) {
20445 switch (Opcode) {
20446 case COMISSrm:
20447 case COMISSrr:
20448 return true;
20449 }
20450 return false;
20451}
20452
20453bool isCLI(unsigned Opcode) {
20454 return Opcode == CLI;
20455}
20456
20457bool isVERW(unsigned Opcode) {
20458 switch (Opcode) {
20459 case VERWm:
20460 case VERWr:
20461 return true;
20462 }
20463 return false;
20464}
20465
20466bool isBTC(unsigned Opcode) {
20467 switch (Opcode) {
20468 case BTC16mi8:
20469 case BTC16mr:
20470 case BTC16ri8:
20471 case BTC16rr:
20472 case BTC32mi8:
20473 case BTC32mr:
20474 case BTC32ri8:
20475 case BTC32rr:
20476 case BTC64mi8:
20477 case BTC64mr:
20478 case BTC64ri8:
20479 case BTC64rr:
20480 return true;
20481 }
20482 return false;
20483}
20484
20485bool isVPHADDUBQ(unsigned Opcode) {
20486 switch (Opcode) {
20487 case VPHADDUBQrm:
20488 case VPHADDUBQrr:
20489 return true;
20490 }
20491 return false;
20492}
20493
20494bool isVPORQ(unsigned Opcode) {
20495 switch (Opcode) {
20496 case VPORQZ128rm:
20497 case VPORQZ128rmb:
20498 case VPORQZ128rmbk:
20499 case VPORQZ128rmbkz:
20500 case VPORQZ128rmk:
20501 case VPORQZ128rmkz:
20502 case VPORQZ128rr:
20503 case VPORQZ128rrk:
20504 case VPORQZ128rrkz:
20505 case VPORQZ256rm:
20506 case VPORQZ256rmb:
20507 case VPORQZ256rmbk:
20508 case VPORQZ256rmbkz:
20509 case VPORQZ256rmk:
20510 case VPORQZ256rmkz:
20511 case VPORQZ256rr:
20512 case VPORQZ256rrk:
20513 case VPORQZ256rrkz:
20514 case VPORQZrm:
20515 case VPORQZrmb:
20516 case VPORQZrmbk:
20517 case VPORQZrmbkz:
20518 case VPORQZrmk:
20519 case VPORQZrmkz:
20520 case VPORQZrr:
20521 case VPORQZrrk:
20522 case VPORQZrrkz:
20523 return true;
20524 }
20525 return false;
20526}
20527
20528bool isORPD(unsigned Opcode) {
20529 switch (Opcode) {
20530 case ORPDrm:
20531 case ORPDrr:
20532 return true;
20533 }
20534 return false;
20535}
20536
20537bool isVMOVSS(unsigned Opcode) {
20538 switch (Opcode) {
20539 case VMOVSSZmr:
20540 case VMOVSSZmrk:
20541 case VMOVSSZrm:
20542 case VMOVSSZrmk:
20543 case VMOVSSZrmkz:
20544 case VMOVSSZrr:
20545 case VMOVSSZrr_REV:
20546 case VMOVSSZrrk:
20547 case VMOVSSZrrk_REV:
20548 case VMOVSSZrrkz:
20549 case VMOVSSZrrkz_REV:
20550 case VMOVSSmr:
20551 case VMOVSSrm:
20552 case VMOVSSrr:
20553 case VMOVSSrr_REV:
20554 return true;
20555 }
20556 return false;
20557}
20558
20559bool isVPSUBD(unsigned Opcode) {
20560 switch (Opcode) {
20561 case VPSUBDYrm:
20562 case VPSUBDYrr:
20563 case VPSUBDZ128rm:
20564 case VPSUBDZ128rmb:
20565 case VPSUBDZ128rmbk:
20566 case VPSUBDZ128rmbkz:
20567 case VPSUBDZ128rmk:
20568 case VPSUBDZ128rmkz:
20569 case VPSUBDZ128rr:
20570 case VPSUBDZ128rrk:
20571 case VPSUBDZ128rrkz:
20572 case VPSUBDZ256rm:
20573 case VPSUBDZ256rmb:
20574 case VPSUBDZ256rmbk:
20575 case VPSUBDZ256rmbkz:
20576 case VPSUBDZ256rmk:
20577 case VPSUBDZ256rmkz:
20578 case VPSUBDZ256rr:
20579 case VPSUBDZ256rrk:
20580 case VPSUBDZ256rrkz:
20581 case VPSUBDZrm:
20582 case VPSUBDZrmb:
20583 case VPSUBDZrmbk:
20584 case VPSUBDZrmbkz:
20585 case VPSUBDZrmk:
20586 case VPSUBDZrmkz:
20587 case VPSUBDZrr:
20588 case VPSUBDZrrk:
20589 case VPSUBDZrrkz:
20590 case VPSUBDrm:
20591 case VPSUBDrr:
20592 return true;
20593 }
20594 return false;
20595}
20596
20597bool isVGATHERPF1QPD(unsigned Opcode) {
20598 return Opcode == VGATHERPF1QPDm;
20599}
20600
20601bool isENCODEKEY256(unsigned Opcode) {
20602 return Opcode == ENCODEKEY256;
20603}
20604
20605bool isGF2P8AFFINEINVQB(unsigned Opcode) {
20606 switch (Opcode) {
20607 case GF2P8AFFINEINVQBrmi:
20608 case GF2P8AFFINEINVQBrri:
20609 return true;
20610 }
20611 return false;
20612}
20613
20614bool isXRSTOR64(unsigned Opcode) {
20615 return Opcode == XRSTOR64;
20616}
20617
20618bool isKANDW(unsigned Opcode) {
20619 return Opcode == KANDWkk;
20620}
20621
20622bool isLODSQ(unsigned Opcode) {
20623 return Opcode == LODSQ;
20624}
20625
20626bool isVMOVRSW(unsigned Opcode) {
20627 switch (Opcode) {
20628 case VMOVRSWZ128m:
20629 case VMOVRSWZ128mk:
20630 case VMOVRSWZ128mkz:
20631 case VMOVRSWZ256m:
20632 case VMOVRSWZ256mk:
20633 case VMOVRSWZ256mkz:
20634 case VMOVRSWZm:
20635 case VMOVRSWZmk:
20636 case VMOVRSWZmkz:
20637 return true;
20638 }
20639 return false;
20640}
20641
20642bool isVSUBSH(unsigned Opcode) {
20643 switch (Opcode) {
20644 case VSUBSHZrm_Int:
20645 case VSUBSHZrmk_Int:
20646 case VSUBSHZrmkz_Int:
20647 case VSUBSHZrr_Int:
20648 case VSUBSHZrrb_Int:
20649 case VSUBSHZrrbk_Int:
20650 case VSUBSHZrrbkz_Int:
20651 case VSUBSHZrrk_Int:
20652 case VSUBSHZrrkz_Int:
20653 return true;
20654 }
20655 return false;
20656}
20657
20658bool isLSS(unsigned Opcode) {
20659 switch (Opcode) {
20660 case LSS16rm:
20661 case LSS32rm:
20662 case LSS64rm:
20663 return true;
20664 }
20665 return false;
20666}
20667
20668bool isPMOVSXBQ(unsigned Opcode) {
20669 switch (Opcode) {
20670 case PMOVSXBQrm:
20671 case PMOVSXBQrr:
20672 return true;
20673 }
20674 return false;
20675}
20676
20677bool isVCVTTSD2SIS(unsigned Opcode) {
20678 switch (Opcode) {
20679 case VCVTTSD2SI64Srm_Int:
20680 case VCVTTSD2SI64Srr_Int:
20681 case VCVTTSD2SI64Srrb_Int:
20682 case VCVTTSD2SISrm_Int:
20683 case VCVTTSD2SISrr_Int:
20684 case VCVTTSD2SISrrb_Int:
20685 return true;
20686 }
20687 return false;
20688}
20689
20690bool isVCMPSH(unsigned Opcode) {
20691 switch (Opcode) {
20692 case VCMPSHZrmi_Int:
20693 case VCMPSHZrmik_Int:
20694 case VCMPSHZrri_Int:
20695 case VCMPSHZrrib_Int:
20696 case VCMPSHZrribk_Int:
20697 case VCMPSHZrrik_Int:
20698 return true;
20699 }
20700 return false;
20701}
20702
20703bool isVFMADD132PS(unsigned Opcode) {
20704 switch (Opcode) {
20705 case VFMADD132PSYm:
20706 case VFMADD132PSYr:
20707 case VFMADD132PSZ128m:
20708 case VFMADD132PSZ128mb:
20709 case VFMADD132PSZ128mbk:
20710 case VFMADD132PSZ128mbkz:
20711 case VFMADD132PSZ128mk:
20712 case VFMADD132PSZ128mkz:
20713 case VFMADD132PSZ128r:
20714 case VFMADD132PSZ128rk:
20715 case VFMADD132PSZ128rkz:
20716 case VFMADD132PSZ256m:
20717 case VFMADD132PSZ256mb:
20718 case VFMADD132PSZ256mbk:
20719 case VFMADD132PSZ256mbkz:
20720 case VFMADD132PSZ256mk:
20721 case VFMADD132PSZ256mkz:
20722 case VFMADD132PSZ256r:
20723 case VFMADD132PSZ256rk:
20724 case VFMADD132PSZ256rkz:
20725 case VFMADD132PSZm:
20726 case VFMADD132PSZmb:
20727 case VFMADD132PSZmbk:
20728 case VFMADD132PSZmbkz:
20729 case VFMADD132PSZmk:
20730 case VFMADD132PSZmkz:
20731 case VFMADD132PSZr:
20732 case VFMADD132PSZrb:
20733 case VFMADD132PSZrbk:
20734 case VFMADD132PSZrbkz:
20735 case VFMADD132PSZrk:
20736 case VFMADD132PSZrkz:
20737 case VFMADD132PSm:
20738 case VFMADD132PSr:
20739 return true;
20740 }
20741 return false;
20742}
20743
20744bool isVPACKSSWB(unsigned Opcode) {
20745 switch (Opcode) {
20746 case VPACKSSWBYrm:
20747 case VPACKSSWBYrr:
20748 case VPACKSSWBZ128rm:
20749 case VPACKSSWBZ128rmk:
20750 case VPACKSSWBZ128rmkz:
20751 case VPACKSSWBZ128rr:
20752 case VPACKSSWBZ128rrk:
20753 case VPACKSSWBZ128rrkz:
20754 case VPACKSSWBZ256rm:
20755 case VPACKSSWBZ256rmk:
20756 case VPACKSSWBZ256rmkz:
20757 case VPACKSSWBZ256rr:
20758 case VPACKSSWBZ256rrk:
20759 case VPACKSSWBZ256rrkz:
20760 case VPACKSSWBZrm:
20761 case VPACKSSWBZrmk:
20762 case VPACKSSWBZrmkz:
20763 case VPACKSSWBZrr:
20764 case VPACKSSWBZrrk:
20765 case VPACKSSWBZrrkz:
20766 case VPACKSSWBrm:
20767 case VPACKSSWBrr:
20768 return true;
20769 }
20770 return false;
20771}
20772
20773bool isPCMPGTQ(unsigned Opcode) {
20774 switch (Opcode) {
20775 case PCMPGTQrm:
20776 case PCMPGTQrr:
20777 return true;
20778 }
20779 return false;
20780}
20781
20782bool isVFMADD132SH(unsigned Opcode) {
20783 switch (Opcode) {
20784 case VFMADD132SHZm_Int:
20785 case VFMADD132SHZmk_Int:
20786 case VFMADD132SHZmkz_Int:
20787 case VFMADD132SHZr_Int:
20788 case VFMADD132SHZrb_Int:
20789 case VFMADD132SHZrbk_Int:
20790 case VFMADD132SHZrbkz_Int:
20791 case VFMADD132SHZrk_Int:
20792 case VFMADD132SHZrkz_Int:
20793 return true;
20794 }
20795 return false;
20796}
20797
20798bool isVCVTUQQ2PH(unsigned Opcode) {
20799 switch (Opcode) {
20800 case VCVTUQQ2PHZ128rm:
20801 case VCVTUQQ2PHZ128rmb:
20802 case VCVTUQQ2PHZ128rmbk:
20803 case VCVTUQQ2PHZ128rmbkz:
20804 case VCVTUQQ2PHZ128rmk:
20805 case VCVTUQQ2PHZ128rmkz:
20806 case VCVTUQQ2PHZ128rr:
20807 case VCVTUQQ2PHZ128rrk:
20808 case VCVTUQQ2PHZ128rrkz:
20809 case VCVTUQQ2PHZ256rm:
20810 case VCVTUQQ2PHZ256rmb:
20811 case VCVTUQQ2PHZ256rmbk:
20812 case VCVTUQQ2PHZ256rmbkz:
20813 case VCVTUQQ2PHZ256rmk:
20814 case VCVTUQQ2PHZ256rmkz:
20815 case VCVTUQQ2PHZ256rr:
20816 case VCVTUQQ2PHZ256rrk:
20817 case VCVTUQQ2PHZ256rrkz:
20818 case VCVTUQQ2PHZrm:
20819 case VCVTUQQ2PHZrmb:
20820 case VCVTUQQ2PHZrmbk:
20821 case VCVTUQQ2PHZrmbkz:
20822 case VCVTUQQ2PHZrmk:
20823 case VCVTUQQ2PHZrmkz:
20824 case VCVTUQQ2PHZrr:
20825 case VCVTUQQ2PHZrrb:
20826 case VCVTUQQ2PHZrrbk:
20827 case VCVTUQQ2PHZrrbkz:
20828 case VCVTUQQ2PHZrrk:
20829 case VCVTUQQ2PHZrrkz:
20830 return true;
20831 }
20832 return false;
20833}
20834
20835bool isVCVTQQ2PS(unsigned Opcode) {
20836 switch (Opcode) {
20837 case VCVTQQ2PSZ128rm:
20838 case VCVTQQ2PSZ128rmb:
20839 case VCVTQQ2PSZ128rmbk:
20840 case VCVTQQ2PSZ128rmbkz:
20841 case VCVTQQ2PSZ128rmk:
20842 case VCVTQQ2PSZ128rmkz:
20843 case VCVTQQ2PSZ128rr:
20844 case VCVTQQ2PSZ128rrk:
20845 case VCVTQQ2PSZ128rrkz:
20846 case VCVTQQ2PSZ256rm:
20847 case VCVTQQ2PSZ256rmb:
20848 case VCVTQQ2PSZ256rmbk:
20849 case VCVTQQ2PSZ256rmbkz:
20850 case VCVTQQ2PSZ256rmk:
20851 case VCVTQQ2PSZ256rmkz:
20852 case VCVTQQ2PSZ256rr:
20853 case VCVTQQ2PSZ256rrk:
20854 case VCVTQQ2PSZ256rrkz:
20855 case VCVTQQ2PSZrm:
20856 case VCVTQQ2PSZrmb:
20857 case VCVTQQ2PSZrmbk:
20858 case VCVTQQ2PSZrmbkz:
20859 case VCVTQQ2PSZrmk:
20860 case VCVTQQ2PSZrmkz:
20861 case VCVTQQ2PSZrr:
20862 case VCVTQQ2PSZrrb:
20863 case VCVTQQ2PSZrrbk:
20864 case VCVTQQ2PSZrrbkz:
20865 case VCVTQQ2PSZrrk:
20866 case VCVTQQ2PSZrrkz:
20867 return true;
20868 }
20869 return false;
20870}
20871
20872bool isVCVTTSS2USI(unsigned Opcode) {
20873 switch (Opcode) {
20874 case VCVTTSS2USI64Zrm_Int:
20875 case VCVTTSS2USI64Zrr_Int:
20876 case VCVTTSS2USI64Zrrb_Int:
20877 case VCVTTSS2USIZrm_Int:
20878 case VCVTTSS2USIZrr_Int:
20879 case VCVTTSS2USIZrrb_Int:
20880 return true;
20881 }
20882 return false;
20883}
20884
20885bool isVPMOVM2Q(unsigned Opcode) {
20886 switch (Opcode) {
20887 case VPMOVM2QZ128rk:
20888 case VPMOVM2QZ256rk:
20889 case VPMOVM2QZrk:
20890 return true;
20891 }
20892 return false;
20893}
20894
20895bool isVMOVD(unsigned Opcode) {
20896 switch (Opcode) {
20897 case VMOVDI2PDIZrm:
20898 case VMOVDI2PDIZrr:
20899 case VMOVDI2PDIrm:
20900 case VMOVDI2PDIrr:
20901 case VMOVPDI2DIZmr:
20902 case VMOVPDI2DIZrr:
20903 case VMOVPDI2DImr:
20904 case VMOVPDI2DIrr:
20905 case VMOVZPDILo2PDIZmr:
20906 case VMOVZPDILo2PDIZrm:
20907 case VMOVZPDILo2PDIZrr:
20908 case VMOVZPDILo2PDIZrr2:
20909 return true;
20910 }
20911 return false;
20912}
20913
20914bool isVCVTTPS2QQS(unsigned Opcode) {
20915 switch (Opcode) {
20916 case VCVTTPS2QQSZ128rm:
20917 case VCVTTPS2QQSZ128rmb:
20918 case VCVTTPS2QQSZ128rmbk:
20919 case VCVTTPS2QQSZ128rmbkz:
20920 case VCVTTPS2QQSZ128rmk:
20921 case VCVTTPS2QQSZ128rmkz:
20922 case VCVTTPS2QQSZ128rr:
20923 case VCVTTPS2QQSZ128rrk:
20924 case VCVTTPS2QQSZ128rrkz:
20925 case VCVTTPS2QQSZ256rm:
20926 case VCVTTPS2QQSZ256rmb:
20927 case VCVTTPS2QQSZ256rmbk:
20928 case VCVTTPS2QQSZ256rmbkz:
20929 case VCVTTPS2QQSZ256rmk:
20930 case VCVTTPS2QQSZ256rmkz:
20931 case VCVTTPS2QQSZ256rr:
20932 case VCVTTPS2QQSZ256rrb:
20933 case VCVTTPS2QQSZ256rrbk:
20934 case VCVTTPS2QQSZ256rrbkz:
20935 case VCVTTPS2QQSZ256rrk:
20936 case VCVTTPS2QQSZ256rrkz:
20937 case VCVTTPS2QQSZrm:
20938 case VCVTTPS2QQSZrmb:
20939 case VCVTTPS2QQSZrmbk:
20940 case VCVTTPS2QQSZrmbkz:
20941 case VCVTTPS2QQSZrmk:
20942 case VCVTTPS2QQSZrmkz:
20943 case VCVTTPS2QQSZrr:
20944 case VCVTTPS2QQSZrrb:
20945 case VCVTTPS2QQSZrrbk:
20946 case VCVTTPS2QQSZrrbkz:
20947 case VCVTTPS2QQSZrrk:
20948 case VCVTTPS2QQSZrrkz:
20949 return true;
20950 }
20951 return false;
20952}
20953
20954bool isVSQRTBF16(unsigned Opcode) {
20955 switch (Opcode) {
20956 case VSQRTBF16Z128m:
20957 case VSQRTBF16Z128mb:
20958 case VSQRTBF16Z128mbk:
20959 case VSQRTBF16Z128mbkz:
20960 case VSQRTBF16Z128mk:
20961 case VSQRTBF16Z128mkz:
20962 case VSQRTBF16Z128r:
20963 case VSQRTBF16Z128rk:
20964 case VSQRTBF16Z128rkz:
20965 case VSQRTBF16Z256m:
20966 case VSQRTBF16Z256mb:
20967 case VSQRTBF16Z256mbk:
20968 case VSQRTBF16Z256mbkz:
20969 case VSQRTBF16Z256mk:
20970 case VSQRTBF16Z256mkz:
20971 case VSQRTBF16Z256r:
20972 case VSQRTBF16Z256rk:
20973 case VSQRTBF16Z256rkz:
20974 case VSQRTBF16Zm:
20975 case VSQRTBF16Zmb:
20976 case VSQRTBF16Zmbk:
20977 case VSQRTBF16Zmbkz:
20978 case VSQRTBF16Zmk:
20979 case VSQRTBF16Zmkz:
20980 case VSQRTBF16Zr:
20981 case VSQRTBF16Zrk:
20982 case VSQRTBF16Zrkz:
20983 return true;
20984 }
20985 return false;
20986}
20987
20988bool isVFPCLASSPH(unsigned Opcode) {
20989 switch (Opcode) {
20990 case VFPCLASSPHZ128mbi:
20991 case VFPCLASSPHZ128mbik:
20992 case VFPCLASSPHZ128mi:
20993 case VFPCLASSPHZ128mik:
20994 case VFPCLASSPHZ128ri:
20995 case VFPCLASSPHZ128rik:
20996 case VFPCLASSPHZ256mbi:
20997 case VFPCLASSPHZ256mbik:
20998 case VFPCLASSPHZ256mi:
20999 case VFPCLASSPHZ256mik:
21000 case VFPCLASSPHZ256ri:
21001 case VFPCLASSPHZ256rik:
21002 case VFPCLASSPHZmbi:
21003 case VFPCLASSPHZmbik:
21004 case VFPCLASSPHZmi:
21005 case VFPCLASSPHZmik:
21006 case VFPCLASSPHZri:
21007 case VFPCLASSPHZrik:
21008 return true;
21009 }
21010 return false;
21011}
21012
21013bool isVCVTSS2SH(unsigned Opcode) {
21014 switch (Opcode) {
21015 case VCVTSS2SHZrm_Int:
21016 case VCVTSS2SHZrmk_Int:
21017 case VCVTSS2SHZrmkz_Int:
21018 case VCVTSS2SHZrr_Int:
21019 case VCVTSS2SHZrrb_Int:
21020 case VCVTSS2SHZrrbk_Int:
21021 case VCVTSS2SHZrrbkz_Int:
21022 case VCVTSS2SHZrrk_Int:
21023 case VCVTSS2SHZrrkz_Int:
21024 return true;
21025 }
21026 return false;
21027}
21028
21029bool isSCASB(unsigned Opcode) {
21030 return Opcode == SCASB;
21031}
21032
21033bool isPSRLD(unsigned Opcode) {
21034 switch (Opcode) {
21035 case MMX_PSRLDri:
21036 case MMX_PSRLDrm:
21037 case MMX_PSRLDrr:
21038 case PSRLDri:
21039 case PSRLDrm:
21040 case PSRLDrr:
21041 return true;
21042 }
21043 return false;
21044}
21045
21046bool isVADDPH(unsigned Opcode) {
21047 switch (Opcode) {
21048 case VADDPHZ128rm:
21049 case VADDPHZ128rmb:
21050 case VADDPHZ128rmbk:
21051 case VADDPHZ128rmbkz:
21052 case VADDPHZ128rmk:
21053 case VADDPHZ128rmkz:
21054 case VADDPHZ128rr:
21055 case VADDPHZ128rrk:
21056 case VADDPHZ128rrkz:
21057 case VADDPHZ256rm:
21058 case VADDPHZ256rmb:
21059 case VADDPHZ256rmbk:
21060 case VADDPHZ256rmbkz:
21061 case VADDPHZ256rmk:
21062 case VADDPHZ256rmkz:
21063 case VADDPHZ256rr:
21064 case VADDPHZ256rrk:
21065 case VADDPHZ256rrkz:
21066 case VADDPHZrm:
21067 case VADDPHZrmb:
21068 case VADDPHZrmbk:
21069 case VADDPHZrmbkz:
21070 case VADDPHZrmk:
21071 case VADDPHZrmkz:
21072 case VADDPHZrr:
21073 case VADDPHZrrb:
21074 case VADDPHZrrbk:
21075 case VADDPHZrrbkz:
21076 case VADDPHZrrk:
21077 case VADDPHZrrkz:
21078 return true;
21079 }
21080 return false;
21081}
21082
21083bool isFSUB(unsigned Opcode) {
21084 switch (Opcode) {
21085 case SUB_F32m:
21086 case SUB_F64m:
21087 case SUB_FST0r:
21088 case SUB_FrST0:
21089 return true;
21090 }
21091 return false;
21092}
21093
21094bool isVCVTTPH2IBS(unsigned Opcode) {
21095 switch (Opcode) {
21096 case VCVTTPH2IBSZ128rm:
21097 case VCVTTPH2IBSZ128rmb:
21098 case VCVTTPH2IBSZ128rmbk:
21099 case VCVTTPH2IBSZ128rmbkz:
21100 case VCVTTPH2IBSZ128rmk:
21101 case VCVTTPH2IBSZ128rmkz:
21102 case VCVTTPH2IBSZ128rr:
21103 case VCVTTPH2IBSZ128rrk:
21104 case VCVTTPH2IBSZ128rrkz:
21105 case VCVTTPH2IBSZ256rm:
21106 case VCVTTPH2IBSZ256rmb:
21107 case VCVTTPH2IBSZ256rmbk:
21108 case VCVTTPH2IBSZ256rmbkz:
21109 case VCVTTPH2IBSZ256rmk:
21110 case VCVTTPH2IBSZ256rmkz:
21111 case VCVTTPH2IBSZ256rr:
21112 case VCVTTPH2IBSZ256rrk:
21113 case VCVTTPH2IBSZ256rrkz:
21114 case VCVTTPH2IBSZrm:
21115 case VCVTTPH2IBSZrmb:
21116 case VCVTTPH2IBSZrmbk:
21117 case VCVTTPH2IBSZrmbkz:
21118 case VCVTTPH2IBSZrmk:
21119 case VCVTTPH2IBSZrmkz:
21120 case VCVTTPH2IBSZrr:
21121 case VCVTTPH2IBSZrrb:
21122 case VCVTTPH2IBSZrrbk:
21123 case VCVTTPH2IBSZrrbkz:
21124 case VCVTTPH2IBSZrrk:
21125 case VCVTTPH2IBSZrrkz:
21126 return true;
21127 }
21128 return false;
21129}
21130
21131bool isVEXTRACTI64X2(unsigned Opcode) {
21132 switch (Opcode) {
21133 case VEXTRACTI64X2Z256mri:
21134 case VEXTRACTI64X2Z256mrik:
21135 case VEXTRACTI64X2Z256rri:
21136 case VEXTRACTI64X2Z256rrik:
21137 case VEXTRACTI64X2Z256rrikz:
21138 case VEXTRACTI64X2Zmri:
21139 case VEXTRACTI64X2Zmrik:
21140 case VEXTRACTI64X2Zrri:
21141 case VEXTRACTI64X2Zrrik:
21142 case VEXTRACTI64X2Zrrikz:
21143 return true;
21144 }
21145 return false;
21146}
21147
21148bool isVPSHLDD(unsigned Opcode) {
21149 switch (Opcode) {
21150 case VPSHLDDZ128rmbi:
21151 case VPSHLDDZ128rmbik:
21152 case VPSHLDDZ128rmbikz:
21153 case VPSHLDDZ128rmi:
21154 case VPSHLDDZ128rmik:
21155 case VPSHLDDZ128rmikz:
21156 case VPSHLDDZ128rri:
21157 case VPSHLDDZ128rrik:
21158 case VPSHLDDZ128rrikz:
21159 case VPSHLDDZ256rmbi:
21160 case VPSHLDDZ256rmbik:
21161 case VPSHLDDZ256rmbikz:
21162 case VPSHLDDZ256rmi:
21163 case VPSHLDDZ256rmik:
21164 case VPSHLDDZ256rmikz:
21165 case VPSHLDDZ256rri:
21166 case VPSHLDDZ256rrik:
21167 case VPSHLDDZ256rrikz:
21168 case VPSHLDDZrmbi:
21169 case VPSHLDDZrmbik:
21170 case VPSHLDDZrmbikz:
21171 case VPSHLDDZrmi:
21172 case VPSHLDDZrmik:
21173 case VPSHLDDZrmikz:
21174 case VPSHLDDZrri:
21175 case VPSHLDDZrrik:
21176 case VPSHLDDZrrikz:
21177 return true;
21178 }
21179 return false;
21180}
21181
21182bool isPMINUW(unsigned Opcode) {
21183 switch (Opcode) {
21184 case PMINUWrm:
21185 case PMINUWrr:
21186 return true;
21187 }
21188 return false;
21189}
21190
21191bool isPSUBSB(unsigned Opcode) {
21192 switch (Opcode) {
21193 case MMX_PSUBSBrm:
21194 case MMX_PSUBSBrr:
21195 case PSUBSBrm:
21196 case PSUBSBrr:
21197 return true;
21198 }
21199 return false;
21200}
21201
21202bool isVCVT2PS2PHX(unsigned Opcode) {
21203 switch (Opcode) {
21204 case VCVT2PS2PHXZ128rm:
21205 case VCVT2PS2PHXZ128rmb:
21206 case VCVT2PS2PHXZ128rmbk:
21207 case VCVT2PS2PHXZ128rmbkz:
21208 case VCVT2PS2PHXZ128rmk:
21209 case VCVT2PS2PHXZ128rmkz:
21210 case VCVT2PS2PHXZ128rr:
21211 case VCVT2PS2PHXZ128rrk:
21212 case VCVT2PS2PHXZ128rrkz:
21213 case VCVT2PS2PHXZ256rm:
21214 case VCVT2PS2PHXZ256rmb:
21215 case VCVT2PS2PHXZ256rmbk:
21216 case VCVT2PS2PHXZ256rmbkz:
21217 case VCVT2PS2PHXZ256rmk:
21218 case VCVT2PS2PHXZ256rmkz:
21219 case VCVT2PS2PHXZ256rr:
21220 case VCVT2PS2PHXZ256rrk:
21221 case VCVT2PS2PHXZ256rrkz:
21222 case VCVT2PS2PHXZrm:
21223 case VCVT2PS2PHXZrmb:
21224 case VCVT2PS2PHXZrmbk:
21225 case VCVT2PS2PHXZrmbkz:
21226 case VCVT2PS2PHXZrmk:
21227 case VCVT2PS2PHXZrmkz:
21228 case VCVT2PS2PHXZrr:
21229 case VCVT2PS2PHXZrrb:
21230 case VCVT2PS2PHXZrrbk:
21231 case VCVT2PS2PHXZrrbkz:
21232 case VCVT2PS2PHXZrrk:
21233 case VCVT2PS2PHXZrrkz:
21234 return true;
21235 }
21236 return false;
21237}
21238
21239bool isVPCMPEQD(unsigned Opcode) {
21240 switch (Opcode) {
21241 case VPCMPEQDYrm:
21242 case VPCMPEQDYrr:
21243 case VPCMPEQDZ128rm:
21244 case VPCMPEQDZ128rmb:
21245 case VPCMPEQDZ128rmbk:
21246 case VPCMPEQDZ128rmk:
21247 case VPCMPEQDZ128rr:
21248 case VPCMPEQDZ128rrk:
21249 case VPCMPEQDZ256rm:
21250 case VPCMPEQDZ256rmb:
21251 case VPCMPEQDZ256rmbk:
21252 case VPCMPEQDZ256rmk:
21253 case VPCMPEQDZ256rr:
21254 case VPCMPEQDZ256rrk:
21255 case VPCMPEQDZrm:
21256 case VPCMPEQDZrmb:
21257 case VPCMPEQDZrmbk:
21258 case VPCMPEQDZrmk:
21259 case VPCMPEQDZrr:
21260 case VPCMPEQDZrrk:
21261 case VPCMPEQDrm:
21262 case VPCMPEQDrr:
21263 return true;
21264 }
21265 return false;
21266}
21267
21268bool isVPSCATTERQD(unsigned Opcode) {
21269 switch (Opcode) {
21270 case VPSCATTERQDZ128mr:
21271 case VPSCATTERQDZ256mr:
21272 case VPSCATTERQDZmr:
21273 return true;
21274 }
21275 return false;
21276}
21277
21278bool isKXNORB(unsigned Opcode) {
21279 return Opcode == KXNORBkk;
21280}
21281
21282bool isLDDQU(unsigned Opcode) {
21283 return Opcode == LDDQUrm;
21284}
21285
21286bool isMASKMOVQ(unsigned Opcode) {
21287 switch (Opcode) {
21288 case MMX_MASKMOVQ:
21289 case MMX_MASKMOVQ64:
21290 return true;
21291 }
21292 return false;
21293}
21294
21295bool isPABSW(unsigned Opcode) {
21296 switch (Opcode) {
21297 case MMX_PABSWrm:
21298 case MMX_PABSWrr:
21299 case PABSWrm:
21300 case PABSWrr:
21301 return true;
21302 }
21303 return false;
21304}
21305
21306bool isVPCOMQ(unsigned Opcode) {
21307 switch (Opcode) {
21308 case VPCOMQmi:
21309 case VPCOMQri:
21310 return true;
21311 }
21312 return false;
21313}
21314
21315bool isVPROLD(unsigned Opcode) {
21316 switch (Opcode) {
21317 case VPROLDZ128mbi:
21318 case VPROLDZ128mbik:
21319 case VPROLDZ128mbikz:
21320 case VPROLDZ128mi:
21321 case VPROLDZ128mik:
21322 case VPROLDZ128mikz:
21323 case VPROLDZ128ri:
21324 case VPROLDZ128rik:
21325 case VPROLDZ128rikz:
21326 case VPROLDZ256mbi:
21327 case VPROLDZ256mbik:
21328 case VPROLDZ256mbikz:
21329 case VPROLDZ256mi:
21330 case VPROLDZ256mik:
21331 case VPROLDZ256mikz:
21332 case VPROLDZ256ri:
21333 case VPROLDZ256rik:
21334 case VPROLDZ256rikz:
21335 case VPROLDZmbi:
21336 case VPROLDZmbik:
21337 case VPROLDZmbikz:
21338 case VPROLDZmi:
21339 case VPROLDZmik:
21340 case VPROLDZmikz:
21341 case VPROLDZri:
21342 case VPROLDZrik:
21343 case VPROLDZrikz:
21344 return true;
21345 }
21346 return false;
21347}
21348
21349bool isVSCATTERDPD(unsigned Opcode) {
21350 switch (Opcode) {
21351 case VSCATTERDPDZ128mr:
21352 case VSCATTERDPDZ256mr:
21353 case VSCATTERDPDZmr:
21354 return true;
21355 }
21356 return false;
21357}
21358
21359bool isFXRSTOR(unsigned Opcode) {
21360 return Opcode == FXRSTOR;
21361}
21362
21363bool isVPCMPUW(unsigned Opcode) {
21364 switch (Opcode) {
21365 case VPCMPUWZ128rmi:
21366 case VPCMPUWZ128rmik:
21367 case VPCMPUWZ128rri:
21368 case VPCMPUWZ128rrik:
21369 case VPCMPUWZ256rmi:
21370 case VPCMPUWZ256rmik:
21371 case VPCMPUWZ256rri:
21372 case VPCMPUWZ256rrik:
21373 case VPCMPUWZrmi:
21374 case VPCMPUWZrmik:
21375 case VPCMPUWZrri:
21376 case VPCMPUWZrrik:
21377 return true;
21378 }
21379 return false;
21380}
21381
21382bool isWBINVD(unsigned Opcode) {
21383 return Opcode == WBINVD;
21384}
21385
21386bool isVCVTTPD2UDQ(unsigned Opcode) {
21387 switch (Opcode) {
21388 case VCVTTPD2UDQZ128rm:
21389 case VCVTTPD2UDQZ128rmb:
21390 case VCVTTPD2UDQZ128rmbk:
21391 case VCVTTPD2UDQZ128rmbkz:
21392 case VCVTTPD2UDQZ128rmk:
21393 case VCVTTPD2UDQZ128rmkz:
21394 case VCVTTPD2UDQZ128rr:
21395 case VCVTTPD2UDQZ128rrk:
21396 case VCVTTPD2UDQZ128rrkz:
21397 case VCVTTPD2UDQZ256rm:
21398 case VCVTTPD2UDQZ256rmb:
21399 case VCVTTPD2UDQZ256rmbk:
21400 case VCVTTPD2UDQZ256rmbkz:
21401 case VCVTTPD2UDQZ256rmk:
21402 case VCVTTPD2UDQZ256rmkz:
21403 case VCVTTPD2UDQZ256rr:
21404 case VCVTTPD2UDQZ256rrk:
21405 case VCVTTPD2UDQZ256rrkz:
21406 case VCVTTPD2UDQZrm:
21407 case VCVTTPD2UDQZrmb:
21408 case VCVTTPD2UDQZrmbk:
21409 case VCVTTPD2UDQZrmbkz:
21410 case VCVTTPD2UDQZrmk:
21411 case VCVTTPD2UDQZrmkz:
21412 case VCVTTPD2UDQZrr:
21413 case VCVTTPD2UDQZrrb:
21414 case VCVTTPD2UDQZrrbk:
21415 case VCVTTPD2UDQZrrbkz:
21416 case VCVTTPD2UDQZrrk:
21417 case VCVTTPD2UDQZrrkz:
21418 return true;
21419 }
21420 return false;
21421}
21422
21423bool isERETU(unsigned Opcode) {
21424 return Opcode == ERETU;
21425}
21426
21427bool isPFRCPIT2(unsigned Opcode) {
21428 switch (Opcode) {
21429 case PFRCPIT2rm:
21430 case PFRCPIT2rr:
21431 return true;
21432 }
21433 return false;
21434}
21435
21436bool isVPERMT2W(unsigned Opcode) {
21437 switch (Opcode) {
21438 case VPERMT2WZ128rm:
21439 case VPERMT2WZ128rmk:
21440 case VPERMT2WZ128rmkz:
21441 case VPERMT2WZ128rr:
21442 case VPERMT2WZ128rrk:
21443 case VPERMT2WZ128rrkz:
21444 case VPERMT2WZ256rm:
21445 case VPERMT2WZ256rmk:
21446 case VPERMT2WZ256rmkz:
21447 case VPERMT2WZ256rr:
21448 case VPERMT2WZ256rrk:
21449 case VPERMT2WZ256rrkz:
21450 case VPERMT2WZrm:
21451 case VPERMT2WZrmk:
21452 case VPERMT2WZrmkz:
21453 case VPERMT2WZrr:
21454 case VPERMT2WZrrk:
21455 case VPERMT2WZrrkz:
21456 return true;
21457 }
21458 return false;
21459}
21460
21461bool isVEXTRACTF32X4(unsigned Opcode) {
21462 switch (Opcode) {
21463 case VEXTRACTF32X4Z256mri:
21464 case VEXTRACTF32X4Z256mrik:
21465 case VEXTRACTF32X4Z256rri:
21466 case VEXTRACTF32X4Z256rrik:
21467 case VEXTRACTF32X4Z256rrikz:
21468 case VEXTRACTF32X4Zmri:
21469 case VEXTRACTF32X4Zmrik:
21470 case VEXTRACTF32X4Zrri:
21471 case VEXTRACTF32X4Zrrik:
21472 case VEXTRACTF32X4Zrrikz:
21473 return true;
21474 }
21475 return false;
21476}
21477
21478bool isVGATHERPF0DPD(unsigned Opcode) {
21479 return Opcode == VGATHERPF0DPDm;
21480}
21481
21482bool isVBROADCASTF32X2(unsigned Opcode) {
21483 switch (Opcode) {
21484 case VBROADCASTF32X2Z256rm:
21485 case VBROADCASTF32X2Z256rmk:
21486 case VBROADCASTF32X2Z256rmkz:
21487 case VBROADCASTF32X2Z256rr:
21488 case VBROADCASTF32X2Z256rrk:
21489 case VBROADCASTF32X2Z256rrkz:
21490 case VBROADCASTF32X2Zrm:
21491 case VBROADCASTF32X2Zrmk:
21492 case VBROADCASTF32X2Zrmkz:
21493 case VBROADCASTF32X2Zrr:
21494 case VBROADCASTF32X2Zrrk:
21495 case VBROADCASTF32X2Zrrkz:
21496 return true;
21497 }
21498 return false;
21499}
21500
21501bool isVRCP14SD(unsigned Opcode) {
21502 switch (Opcode) {
21503 case VRCP14SDZrm:
21504 case VRCP14SDZrmk:
21505 case VRCP14SDZrmkz:
21506 case VRCP14SDZrr:
21507 case VRCP14SDZrrk:
21508 case VRCP14SDZrrkz:
21509 return true;
21510 }
21511 return false;
21512}
21513
21514bool isLAHF(unsigned Opcode) {
21515 return Opcode == LAHF;
21516}
21517
21518bool isPABSD(unsigned Opcode) {
21519 switch (Opcode) {
21520 case MMX_PABSDrm:
21521 case MMX_PABSDrr:
21522 case PABSDrm:
21523 case PABSDrr:
21524 return true;
21525 }
21526 return false;
21527}
21528
21529bool isPINSRB(unsigned Opcode) {
21530 switch (Opcode) {
21531 case PINSRBrmi:
21532 case PINSRBrri:
21533 return true;
21534 }
21535 return false;
21536}
21537
21538bool isSKINIT(unsigned Opcode) {
21539 return Opcode == SKINIT;
21540}
21541
21542bool isENTER(unsigned Opcode) {
21543 return Opcode == ENTER;
21544}
21545
21546bool isVCVTSI2SS(unsigned Opcode) {
21547 switch (Opcode) {
21548 case VCVTSI2SSZrm_Int:
21549 case VCVTSI2SSZrr_Int:
21550 case VCVTSI2SSZrrb_Int:
21551 case VCVTSI2SSrm_Int:
21552 case VCVTSI2SSrr_Int:
21553 case VCVTSI642SSZrm_Int:
21554 case VCVTSI642SSZrr_Int:
21555 case VCVTSI642SSZrrb_Int:
21556 case VCVTSI642SSrm_Int:
21557 case VCVTSI642SSrr_Int:
21558 return true;
21559 }
21560 return false;
21561}
21562
21563bool isVFMADD231PD(unsigned Opcode) {
21564 switch (Opcode) {
21565 case VFMADD231PDYm:
21566 case VFMADD231PDYr:
21567 case VFMADD231PDZ128m:
21568 case VFMADD231PDZ128mb:
21569 case VFMADD231PDZ128mbk:
21570 case VFMADD231PDZ128mbkz:
21571 case VFMADD231PDZ128mk:
21572 case VFMADD231PDZ128mkz:
21573 case VFMADD231PDZ128r:
21574 case VFMADD231PDZ128rk:
21575 case VFMADD231PDZ128rkz:
21576 case VFMADD231PDZ256m:
21577 case VFMADD231PDZ256mb:
21578 case VFMADD231PDZ256mbk:
21579 case VFMADD231PDZ256mbkz:
21580 case VFMADD231PDZ256mk:
21581 case VFMADD231PDZ256mkz:
21582 case VFMADD231PDZ256r:
21583 case VFMADD231PDZ256rk:
21584 case VFMADD231PDZ256rkz:
21585 case VFMADD231PDZm:
21586 case VFMADD231PDZmb:
21587 case VFMADD231PDZmbk:
21588 case VFMADD231PDZmbkz:
21589 case VFMADD231PDZmk:
21590 case VFMADD231PDZmkz:
21591 case VFMADD231PDZr:
21592 case VFMADD231PDZrb:
21593 case VFMADD231PDZrbk:
21594 case VFMADD231PDZrbkz:
21595 case VFMADD231PDZrk:
21596 case VFMADD231PDZrkz:
21597 case VFMADD231PDm:
21598 case VFMADD231PDr:
21599 return true;
21600 }
21601 return false;
21602}
21603
21604bool isLOADIWKEY(unsigned Opcode) {
21605 return Opcode == LOADIWKEY;
21606}
21607
21608bool isVMOVNTDQA(unsigned Opcode) {
21609 switch (Opcode) {
21610 case VMOVNTDQAYrm:
21611 case VMOVNTDQAZ128rm:
21612 case VMOVNTDQAZ256rm:
21613 case VMOVNTDQAZrm:
21614 case VMOVNTDQArm:
21615 return true;
21616 }
21617 return false;
21618}
21619
21620bool isVPERMT2PS(unsigned Opcode) {
21621 switch (Opcode) {
21622 case VPERMT2PSZ128rm:
21623 case VPERMT2PSZ128rmb:
21624 case VPERMT2PSZ128rmbk:
21625 case VPERMT2PSZ128rmbkz:
21626 case VPERMT2PSZ128rmk:
21627 case VPERMT2PSZ128rmkz:
21628 case VPERMT2PSZ128rr:
21629 case VPERMT2PSZ128rrk:
21630 case VPERMT2PSZ128rrkz:
21631 case VPERMT2PSZ256rm:
21632 case VPERMT2PSZ256rmb:
21633 case VPERMT2PSZ256rmbk:
21634 case VPERMT2PSZ256rmbkz:
21635 case VPERMT2PSZ256rmk:
21636 case VPERMT2PSZ256rmkz:
21637 case VPERMT2PSZ256rr:
21638 case VPERMT2PSZ256rrk:
21639 case VPERMT2PSZ256rrkz:
21640 case VPERMT2PSZrm:
21641 case VPERMT2PSZrmb:
21642 case VPERMT2PSZrmbk:
21643 case VPERMT2PSZrmbkz:
21644 case VPERMT2PSZrmk:
21645 case VPERMT2PSZrmkz:
21646 case VPERMT2PSZrr:
21647 case VPERMT2PSZrrk:
21648 case VPERMT2PSZrrkz:
21649 return true;
21650 }
21651 return false;
21652}
21653
21654bool isPUSHF(unsigned Opcode) {
21655 return Opcode == PUSHF16;
21656}
21657
21658bool isMPSADBW(unsigned Opcode) {
21659 switch (Opcode) {
21660 case MPSADBWrmi:
21661 case MPSADBWrri:
21662 return true;
21663 }
21664 return false;
21665}
21666
21667bool isVCVTBIASPS2BF8S(unsigned Opcode) {
21668 switch (Opcode) {
21669 case VCVTBIASPS2BF8SZ128rm:
21670 case VCVTBIASPS2BF8SZ128rmb:
21671 case VCVTBIASPS2BF8SZ128rmbk:
21672 case VCVTBIASPS2BF8SZ128rmbkz:
21673 case VCVTBIASPS2BF8SZ128rmk:
21674 case VCVTBIASPS2BF8SZ128rmkz:
21675 case VCVTBIASPS2BF8SZ128rr:
21676 case VCVTBIASPS2BF8SZ128rrk:
21677 case VCVTBIASPS2BF8SZ128rrkz:
21678 case VCVTBIASPS2BF8SZ256rm:
21679 case VCVTBIASPS2BF8SZ256rmb:
21680 case VCVTBIASPS2BF8SZ256rmbk:
21681 case VCVTBIASPS2BF8SZ256rmbkz:
21682 case VCVTBIASPS2BF8SZ256rmk:
21683 case VCVTBIASPS2BF8SZ256rmkz:
21684 case VCVTBIASPS2BF8SZ256rr:
21685 case VCVTBIASPS2BF8SZ256rrk:
21686 case VCVTBIASPS2BF8SZ256rrkz:
21687 case VCVTBIASPS2BF8SZrm:
21688 case VCVTBIASPS2BF8SZrmb:
21689 case VCVTBIASPS2BF8SZrmbk:
21690 case VCVTBIASPS2BF8SZrmbkz:
21691 case VCVTBIASPS2BF8SZrmk:
21692 case VCVTBIASPS2BF8SZrmkz:
21693 case VCVTBIASPS2BF8SZrr:
21694 case VCVTBIASPS2BF8SZrrk:
21695 case VCVTBIASPS2BF8SZrrkz:
21696 return true;
21697 }
21698 return false;
21699}
21700
21701bool isVMINMAXSH(unsigned Opcode) {
21702 switch (Opcode) {
21703 case VMINMAXSHrmi_Int:
21704 case VMINMAXSHrmik_Int:
21705 case VMINMAXSHrmikz_Int:
21706 case VMINMAXSHrri_Int:
21707 case VMINMAXSHrrib_Int:
21708 case VMINMAXSHrribk_Int:
21709 case VMINMAXSHrribkz_Int:
21710 case VMINMAXSHrrik_Int:
21711 case VMINMAXSHrrikz_Int:
21712 return true;
21713 }
21714 return false;
21715}
21716
21717bool isVRSQRT14SS(unsigned Opcode) {
21718 switch (Opcode) {
21719 case VRSQRT14SSZrm:
21720 case VRSQRT14SSZrmk:
21721 case VRSQRT14SSZrmkz:
21722 case VRSQRT14SSZrr:
21723 case VRSQRT14SSZrrk:
21724 case VRSQRT14SSZrrkz:
21725 return true;
21726 }
21727 return false;
21728}
21729
21730bool isVCVTDQ2PD(unsigned Opcode) {
21731 switch (Opcode) {
21732 case VCVTDQ2PDYrm:
21733 case VCVTDQ2PDYrr:
21734 case VCVTDQ2PDZ128rm:
21735 case VCVTDQ2PDZ128rmb:
21736 case VCVTDQ2PDZ128rmbk:
21737 case VCVTDQ2PDZ128rmbkz:
21738 case VCVTDQ2PDZ128rmk:
21739 case VCVTDQ2PDZ128rmkz:
21740 case VCVTDQ2PDZ128rr:
21741 case VCVTDQ2PDZ128rrk:
21742 case VCVTDQ2PDZ128rrkz:
21743 case VCVTDQ2PDZ256rm:
21744 case VCVTDQ2PDZ256rmb:
21745 case VCVTDQ2PDZ256rmbk:
21746 case VCVTDQ2PDZ256rmbkz:
21747 case VCVTDQ2PDZ256rmk:
21748 case VCVTDQ2PDZ256rmkz:
21749 case VCVTDQ2PDZ256rr:
21750 case VCVTDQ2PDZ256rrk:
21751 case VCVTDQ2PDZ256rrkz:
21752 case VCVTDQ2PDZrm:
21753 case VCVTDQ2PDZrmb:
21754 case VCVTDQ2PDZrmbk:
21755 case VCVTDQ2PDZrmbkz:
21756 case VCVTDQ2PDZrmk:
21757 case VCVTDQ2PDZrmkz:
21758 case VCVTDQ2PDZrr:
21759 case VCVTDQ2PDZrrk:
21760 case VCVTDQ2PDZrrkz:
21761 case VCVTDQ2PDrm:
21762 case VCVTDQ2PDrr:
21763 return true;
21764 }
21765 return false;
21766}
21767
21768bool isVORPS(unsigned Opcode) {
21769 switch (Opcode) {
21770 case VORPSYrm:
21771 case VORPSYrr:
21772 case VORPSZ128rm:
21773 case VORPSZ128rmb:
21774 case VORPSZ128rmbk:
21775 case VORPSZ128rmbkz:
21776 case VORPSZ128rmk:
21777 case VORPSZ128rmkz:
21778 case VORPSZ128rr:
21779 case VORPSZ128rrk:
21780 case VORPSZ128rrkz:
21781 case VORPSZ256rm:
21782 case VORPSZ256rmb:
21783 case VORPSZ256rmbk:
21784 case VORPSZ256rmbkz:
21785 case VORPSZ256rmk:
21786 case VORPSZ256rmkz:
21787 case VORPSZ256rr:
21788 case VORPSZ256rrk:
21789 case VORPSZ256rrkz:
21790 case VORPSZrm:
21791 case VORPSZrmb:
21792 case VORPSZrmbk:
21793 case VORPSZrmbkz:
21794 case VORPSZrmk:
21795 case VORPSZrmkz:
21796 case VORPSZrr:
21797 case VORPSZrrk:
21798 case VORPSZrrkz:
21799 case VORPSrm:
21800 case VORPSrr:
21801 return true;
21802 }
21803 return false;
21804}
21805
21806bool isVPEXPANDQ(unsigned Opcode) {
21807 switch (Opcode) {
21808 case VPEXPANDQZ128rm:
21809 case VPEXPANDQZ128rmk:
21810 case VPEXPANDQZ128rmkz:
21811 case VPEXPANDQZ128rr:
21812 case VPEXPANDQZ128rrk:
21813 case VPEXPANDQZ128rrkz:
21814 case VPEXPANDQZ256rm:
21815 case VPEXPANDQZ256rmk:
21816 case VPEXPANDQZ256rmkz:
21817 case VPEXPANDQZ256rr:
21818 case VPEXPANDQZ256rrk:
21819 case VPEXPANDQZ256rrkz:
21820 case VPEXPANDQZrm:
21821 case VPEXPANDQZrmk:
21822 case VPEXPANDQZrmkz:
21823 case VPEXPANDQZrr:
21824 case VPEXPANDQZrrk:
21825 case VPEXPANDQZrrkz:
21826 return true;
21827 }
21828 return false;
21829}
21830
21831bool isVPSHRDD(unsigned Opcode) {
21832 switch (Opcode) {
21833 case VPSHRDDZ128rmbi:
21834 case VPSHRDDZ128rmbik:
21835 case VPSHRDDZ128rmbikz:
21836 case VPSHRDDZ128rmi:
21837 case VPSHRDDZ128rmik:
21838 case VPSHRDDZ128rmikz:
21839 case VPSHRDDZ128rri:
21840 case VPSHRDDZ128rrik:
21841 case VPSHRDDZ128rrikz:
21842 case VPSHRDDZ256rmbi:
21843 case VPSHRDDZ256rmbik:
21844 case VPSHRDDZ256rmbikz:
21845 case VPSHRDDZ256rmi:
21846 case VPSHRDDZ256rmik:
21847 case VPSHRDDZ256rmikz:
21848 case VPSHRDDZ256rri:
21849 case VPSHRDDZ256rrik:
21850 case VPSHRDDZ256rrikz:
21851 case VPSHRDDZrmbi:
21852 case VPSHRDDZrmbik:
21853 case VPSHRDDZrmbikz:
21854 case VPSHRDDZrmi:
21855 case VPSHRDDZrmik:
21856 case VPSHRDDZrmikz:
21857 case VPSHRDDZrri:
21858 case VPSHRDDZrrik:
21859 case VPSHRDDZrrikz:
21860 return true;
21861 }
21862 return false;
21863}
21864
21865bool isTDPBSSD(unsigned Opcode) {
21866 return Opcode == TDPBSSD;
21867}
21868
21869bool isTESTUI(unsigned Opcode) {
21870 return Opcode == TESTUI;
21871}
21872
21873bool isVCVTBF42HF8(unsigned Opcode) {
21874 switch (Opcode) {
21875 case VCVTBF42HF8Z128rm:
21876 case VCVTBF42HF8Z128rmk:
21877 case VCVTBF42HF8Z128rmkz:
21878 case VCVTBF42HF8Z128rr:
21879 case VCVTBF42HF8Z128rrk:
21880 case VCVTBF42HF8Z128rrkz:
21881 case VCVTBF42HF8Z256rm:
21882 case VCVTBF42HF8Z256rmk:
21883 case VCVTBF42HF8Z256rmkz:
21884 case VCVTBF42HF8Z256rr:
21885 case VCVTBF42HF8Z256rrk:
21886 case VCVTBF42HF8Z256rrkz:
21887 case VCVTBF42HF8Zrm:
21888 case VCVTBF42HF8Zrmk:
21889 case VCVTBF42HF8Zrmkz:
21890 case VCVTBF42HF8Zrr:
21891 case VCVTBF42HF8Zrrk:
21892 case VCVTBF42HF8Zrrkz:
21893 return true;
21894 }
21895 return false;
21896}
21897
21898bool isVFMADDPD(unsigned Opcode) {
21899 switch (Opcode) {
21900 case VFMADDPD4Ymr:
21901 case VFMADDPD4Yrm:
21902 case VFMADDPD4Yrr:
21903 case VFMADDPD4Yrr_REV:
21904 case VFMADDPD4mr:
21905 case VFMADDPD4rm:
21906 case VFMADDPD4rr:
21907 case VFMADDPD4rr_REV:
21908 return true;
21909 }
21910 return false;
21911}
21912
21913bool isVPANDND(unsigned Opcode) {
21914 switch (Opcode) {
21915 case VPANDNDZ128rm:
21916 case VPANDNDZ128rmb:
21917 case VPANDNDZ128rmbk:
21918 case VPANDNDZ128rmbkz:
21919 case VPANDNDZ128rmk:
21920 case VPANDNDZ128rmkz:
21921 case VPANDNDZ128rr:
21922 case VPANDNDZ128rrk:
21923 case VPANDNDZ128rrkz:
21924 case VPANDNDZ256rm:
21925 case VPANDNDZ256rmb:
21926 case VPANDNDZ256rmbk:
21927 case VPANDNDZ256rmbkz:
21928 case VPANDNDZ256rmk:
21929 case VPANDNDZ256rmkz:
21930 case VPANDNDZ256rr:
21931 case VPANDNDZ256rrk:
21932 case VPANDNDZ256rrkz:
21933 case VPANDNDZrm:
21934 case VPANDNDZrmb:
21935 case VPANDNDZrmbk:
21936 case VPANDNDZrmbkz:
21937 case VPANDNDZrmk:
21938 case VPANDNDZrmkz:
21939 case VPANDNDZrr:
21940 case VPANDNDZrrk:
21941 case VPANDNDZrrkz:
21942 return true;
21943 }
21944 return false;
21945}
21946
21947bool isVPMOVSDB(unsigned Opcode) {
21948 switch (Opcode) {
21949 case VPMOVSDBZ128mr:
21950 case VPMOVSDBZ128mrk:
21951 case VPMOVSDBZ128rr:
21952 case VPMOVSDBZ128rrk:
21953 case VPMOVSDBZ128rrkz:
21954 case VPMOVSDBZ256mr:
21955 case VPMOVSDBZ256mrk:
21956 case VPMOVSDBZ256rr:
21957 case VPMOVSDBZ256rrk:
21958 case VPMOVSDBZ256rrkz:
21959 case VPMOVSDBZmr:
21960 case VPMOVSDBZmrk:
21961 case VPMOVSDBZrr:
21962 case VPMOVSDBZrrk:
21963 case VPMOVSDBZrrkz:
21964 return true;
21965 }
21966 return false;
21967}
21968
21969bool isVPBROADCASTB(unsigned Opcode) {
21970 switch (Opcode) {
21971 case VPBROADCASTBYrm:
21972 case VPBROADCASTBYrr:
21973 case VPBROADCASTBZ128rm:
21974 case VPBROADCASTBZ128rmk:
21975 case VPBROADCASTBZ128rmkz:
21976 case VPBROADCASTBZ128rr:
21977 case VPBROADCASTBZ128rrk:
21978 case VPBROADCASTBZ128rrkz:
21979 case VPBROADCASTBZ256rm:
21980 case VPBROADCASTBZ256rmk:
21981 case VPBROADCASTBZ256rmkz:
21982 case VPBROADCASTBZ256rr:
21983 case VPBROADCASTBZ256rrk:
21984 case VPBROADCASTBZ256rrkz:
21985 case VPBROADCASTBZrm:
21986 case VPBROADCASTBZrmk:
21987 case VPBROADCASTBZrmkz:
21988 case VPBROADCASTBZrr:
21989 case VPBROADCASTBZrrk:
21990 case VPBROADCASTBZrrkz:
21991 case VPBROADCASTBrZ128rr:
21992 case VPBROADCASTBrZ128rrk:
21993 case VPBROADCASTBrZ128rrkz:
21994 case VPBROADCASTBrZ256rr:
21995 case VPBROADCASTBrZ256rrk:
21996 case VPBROADCASTBrZ256rrkz:
21997 case VPBROADCASTBrZrr:
21998 case VPBROADCASTBrZrrk:
21999 case VPBROADCASTBrZrrkz:
22000 case VPBROADCASTBrm:
22001 case VPBROADCASTBrr:
22002 return true;
22003 }
22004 return false;
22005}
22006
22007bool isCVTPI2PD(unsigned Opcode) {
22008 switch (Opcode) {
22009 case MMX_CVTPI2PDrm:
22010 case MMX_CVTPI2PDrr:
22011 return true;
22012 }
22013 return false;
22014}
22015
22016bool isVPERMI2B(unsigned Opcode) {
22017 switch (Opcode) {
22018 case VPERMI2BZ128rm:
22019 case VPERMI2BZ128rmk:
22020 case VPERMI2BZ128rmkz:
22021 case VPERMI2BZ128rr:
22022 case VPERMI2BZ128rrk:
22023 case VPERMI2BZ128rrkz:
22024 case VPERMI2BZ256rm:
22025 case VPERMI2BZ256rmk:
22026 case VPERMI2BZ256rmkz:
22027 case VPERMI2BZ256rr:
22028 case VPERMI2BZ256rrk:
22029 case VPERMI2BZ256rrkz:
22030 case VPERMI2BZrm:
22031 case VPERMI2BZrmk:
22032 case VPERMI2BZrmkz:
22033 case VPERMI2BZrr:
22034 case VPERMI2BZrrk:
22035 case VPERMI2BZrrkz:
22036 return true;
22037 }
22038 return false;
22039}
22040
22041bool isVPMINSB(unsigned Opcode) {
22042 switch (Opcode) {
22043 case VPMINSBYrm:
22044 case VPMINSBYrr:
22045 case VPMINSBZ128rm:
22046 case VPMINSBZ128rmk:
22047 case VPMINSBZ128rmkz:
22048 case VPMINSBZ128rr:
22049 case VPMINSBZ128rrk:
22050 case VPMINSBZ128rrkz:
22051 case VPMINSBZ256rm:
22052 case VPMINSBZ256rmk:
22053 case VPMINSBZ256rmkz:
22054 case VPMINSBZ256rr:
22055 case VPMINSBZ256rrk:
22056 case VPMINSBZ256rrkz:
22057 case VPMINSBZrm:
22058 case VPMINSBZrmk:
22059 case VPMINSBZrmkz:
22060 case VPMINSBZrr:
22061 case VPMINSBZrrk:
22062 case VPMINSBZrrkz:
22063 case VPMINSBrm:
22064 case VPMINSBrr:
22065 return true;
22066 }
22067 return false;
22068}
22069
22070bool isLAR(unsigned Opcode) {
22071 switch (Opcode) {
22072 case LAR16rm:
22073 case LAR16rr:
22074 case LAR32rm:
22075 case LAR32rr:
22076 case LAR64rm:
22077 case LAR64rr:
22078 return true;
22079 }
22080 return false;
22081}
22082
22083bool isINVLPGB(unsigned Opcode) {
22084 switch (Opcode) {
22085 case INVLPGB32:
22086 case INVLPGB64:
22087 return true;
22088 }
22089 return false;
22090}
22091
22092bool isTLBSYNC(unsigned Opcode) {
22093 return Opcode == TLBSYNC;
22094}
22095
22096bool isFDIVP(unsigned Opcode) {
22097 return Opcode == DIV_FPrST0;
22098}
22099
22100bool isVPSRLW(unsigned Opcode) {
22101 switch (Opcode) {
22102 case VPSRLWYri:
22103 case VPSRLWYrm:
22104 case VPSRLWYrr:
22105 case VPSRLWZ128mi:
22106 case VPSRLWZ128mik:
22107 case VPSRLWZ128mikz:
22108 case VPSRLWZ128ri:
22109 case VPSRLWZ128rik:
22110 case VPSRLWZ128rikz:
22111 case VPSRLWZ128rm:
22112 case VPSRLWZ128rmk:
22113 case VPSRLWZ128rmkz:
22114 case VPSRLWZ128rr:
22115 case VPSRLWZ128rrk:
22116 case VPSRLWZ128rrkz:
22117 case VPSRLWZ256mi:
22118 case VPSRLWZ256mik:
22119 case VPSRLWZ256mikz:
22120 case VPSRLWZ256ri:
22121 case VPSRLWZ256rik:
22122 case VPSRLWZ256rikz:
22123 case VPSRLWZ256rm:
22124 case VPSRLWZ256rmk:
22125 case VPSRLWZ256rmkz:
22126 case VPSRLWZ256rr:
22127 case VPSRLWZ256rrk:
22128 case VPSRLWZ256rrkz:
22129 case VPSRLWZmi:
22130 case VPSRLWZmik:
22131 case VPSRLWZmikz:
22132 case VPSRLWZri:
22133 case VPSRLWZrik:
22134 case VPSRLWZrikz:
22135 case VPSRLWZrm:
22136 case VPSRLWZrmk:
22137 case VPSRLWZrmkz:
22138 case VPSRLWZrr:
22139 case VPSRLWZrrk:
22140 case VPSRLWZrrkz:
22141 case VPSRLWri:
22142 case VPSRLWrm:
22143 case VPSRLWrr:
22144 return true;
22145 }
22146 return false;
22147}
22148
22149bool isVRCP28SS(unsigned Opcode) {
22150 switch (Opcode) {
22151 case VRCP28SSZm:
22152 case VRCP28SSZmk:
22153 case VRCP28SSZmkz:
22154 case VRCP28SSZr:
22155 case VRCP28SSZrb:
22156 case VRCP28SSZrbk:
22157 case VRCP28SSZrbkz:
22158 case VRCP28SSZrk:
22159 case VRCP28SSZrkz:
22160 return true;
22161 }
22162 return false;
22163}
22164
22165bool isVMOVHPS(unsigned Opcode) {
22166 switch (Opcode) {
22167 case VMOVHPSZ128mr:
22168 case VMOVHPSZ128rm:
22169 case VMOVHPSmr:
22170 case VMOVHPSrm:
22171 return true;
22172 }
22173 return false;
22174}
22175
22176bool isVPMACSSDD(unsigned Opcode) {
22177 switch (Opcode) {
22178 case VPMACSSDDrm:
22179 case VPMACSSDDrr:
22180 return true;
22181 }
22182 return false;
22183}
22184
22185bool isPEXT(unsigned Opcode) {
22186 switch (Opcode) {
22187 case PEXT32rm:
22188 case PEXT32rm_EVEX:
22189 case PEXT32rr:
22190 case PEXT32rr_EVEX:
22191 case PEXT64rm:
22192 case PEXT64rm_EVEX:
22193 case PEXT64rr:
22194 case PEXT64rr_EVEX:
22195 return true;
22196 }
22197 return false;
22198}
22199
22200bool isVMAXBF16(unsigned Opcode) {
22201 switch (Opcode) {
22202 case VMAXBF16Z128rm:
22203 case VMAXBF16Z128rmb:
22204 case VMAXBF16Z128rmbk:
22205 case VMAXBF16Z128rmbkz:
22206 case VMAXBF16Z128rmk:
22207 case VMAXBF16Z128rmkz:
22208 case VMAXBF16Z128rr:
22209 case VMAXBF16Z128rrk:
22210 case VMAXBF16Z128rrkz:
22211 case VMAXBF16Z256rm:
22212 case VMAXBF16Z256rmb:
22213 case VMAXBF16Z256rmbk:
22214 case VMAXBF16Z256rmbkz:
22215 case VMAXBF16Z256rmk:
22216 case VMAXBF16Z256rmkz:
22217 case VMAXBF16Z256rr:
22218 case VMAXBF16Z256rrk:
22219 case VMAXBF16Z256rrkz:
22220 case VMAXBF16Zrm:
22221 case VMAXBF16Zrmb:
22222 case VMAXBF16Zrmbk:
22223 case VMAXBF16Zrmbkz:
22224 case VMAXBF16Zrmk:
22225 case VMAXBF16Zrmkz:
22226 case VMAXBF16Zrr:
22227 case VMAXBF16Zrrk:
22228 case VMAXBF16Zrrkz:
22229 return true;
22230 }
22231 return false;
22232}
22233
22234bool isVRSQRT14SD(unsigned Opcode) {
22235 switch (Opcode) {
22236 case VRSQRT14SDZrm:
22237 case VRSQRT14SDZrmk:
22238 case VRSQRT14SDZrmkz:
22239 case VRSQRT14SDZrr:
22240 case VRSQRT14SDZrrk:
22241 case VRSQRT14SDZrrkz:
22242 return true;
22243 }
22244 return false;
22245}
22246
22247bool isVPDPWSSD(unsigned Opcode) {
22248 switch (Opcode) {
22249 case VPDPWSSDYrm:
22250 case VPDPWSSDYrr:
22251 case VPDPWSSDZ128rm:
22252 case VPDPWSSDZ128rmb:
22253 case VPDPWSSDZ128rmbk:
22254 case VPDPWSSDZ128rmbkz:
22255 case VPDPWSSDZ128rmk:
22256 case VPDPWSSDZ128rmkz:
22257 case VPDPWSSDZ128rr:
22258 case VPDPWSSDZ128rrk:
22259 case VPDPWSSDZ128rrkz:
22260 case VPDPWSSDZ256rm:
22261 case VPDPWSSDZ256rmb:
22262 case VPDPWSSDZ256rmbk:
22263 case VPDPWSSDZ256rmbkz:
22264 case VPDPWSSDZ256rmk:
22265 case VPDPWSSDZ256rmkz:
22266 case VPDPWSSDZ256rr:
22267 case VPDPWSSDZ256rrk:
22268 case VPDPWSSDZ256rrkz:
22269 case VPDPWSSDZrm:
22270 case VPDPWSSDZrmb:
22271 case VPDPWSSDZrmbk:
22272 case VPDPWSSDZrmbkz:
22273 case VPDPWSSDZrmk:
22274 case VPDPWSSDZrmkz:
22275 case VPDPWSSDZrr:
22276 case VPDPWSSDZrrk:
22277 case VPDPWSSDZrrkz:
22278 case VPDPWSSDrm:
22279 case VPDPWSSDrr:
22280 return true;
22281 }
22282 return false;
22283}
22284
22285bool isVFMSUB231SD(unsigned Opcode) {
22286 switch (Opcode) {
22287 case VFMSUB231SDZm_Int:
22288 case VFMSUB231SDZmk_Int:
22289 case VFMSUB231SDZmkz_Int:
22290 case VFMSUB231SDZr_Int:
22291 case VFMSUB231SDZrb_Int:
22292 case VFMSUB231SDZrbk_Int:
22293 case VFMSUB231SDZrbkz_Int:
22294 case VFMSUB231SDZrk_Int:
22295 case VFMSUB231SDZrkz_Int:
22296 case VFMSUB231SDm_Int:
22297 case VFMSUB231SDr_Int:
22298 return true;
22299 }
22300 return false;
22301}
22302
22303bool isVPMOVZXWQ(unsigned Opcode) {
22304 switch (Opcode) {
22305 case VPMOVZXWQYrm:
22306 case VPMOVZXWQYrr:
22307 case VPMOVZXWQZ128rm:
22308 case VPMOVZXWQZ128rmk:
22309 case VPMOVZXWQZ128rmkz:
22310 case VPMOVZXWQZ128rr:
22311 case VPMOVZXWQZ128rrk:
22312 case VPMOVZXWQZ128rrkz:
22313 case VPMOVZXWQZ256rm:
22314 case VPMOVZXWQZ256rmk:
22315 case VPMOVZXWQZ256rmkz:
22316 case VPMOVZXWQZ256rr:
22317 case VPMOVZXWQZ256rrk:
22318 case VPMOVZXWQZ256rrkz:
22319 case VPMOVZXWQZrm:
22320 case VPMOVZXWQZrmk:
22321 case VPMOVZXWQZrmkz:
22322 case VPMOVZXWQZrr:
22323 case VPMOVZXWQZrrk:
22324 case VPMOVZXWQZrrkz:
22325 case VPMOVZXWQrm:
22326 case VPMOVZXWQrr:
22327 return true;
22328 }
22329 return false;
22330}
22331
22332bool isXORPD(unsigned Opcode) {
22333 switch (Opcode) {
22334 case XORPDrm:
22335 case XORPDrr:
22336 return true;
22337 }
22338 return false;
22339}
22340
22341bool isVMOVDQA(unsigned Opcode) {
22342 switch (Opcode) {
22343 case VMOVDQAYmr:
22344 case VMOVDQAYrm:
22345 case VMOVDQAYrr:
22346 case VMOVDQAYrr_REV:
22347 case VMOVDQAmr:
22348 case VMOVDQArm:
22349 case VMOVDQArr:
22350 case VMOVDQArr_REV:
22351 return true;
22352 }
22353 return false;
22354}
22355
22356bool isVFNMSUB213SD(unsigned Opcode) {
22357 switch (Opcode) {
22358 case VFNMSUB213SDZm_Int:
22359 case VFNMSUB213SDZmk_Int:
22360 case VFNMSUB213SDZmkz_Int:
22361 case VFNMSUB213SDZr_Int:
22362 case VFNMSUB213SDZrb_Int:
22363 case VFNMSUB213SDZrbk_Int:
22364 case VFNMSUB213SDZrbkz_Int:
22365 case VFNMSUB213SDZrk_Int:
22366 case VFNMSUB213SDZrkz_Int:
22367 case VFNMSUB213SDm_Int:
22368 case VFNMSUB213SDr_Int:
22369 return true;
22370 }
22371 return false;
22372}
22373
22374bool isVMINPS(unsigned Opcode) {
22375 switch (Opcode) {
22376 case VMINPSYrm:
22377 case VMINPSYrr:
22378 case VMINPSZ128rm:
22379 case VMINPSZ128rmb:
22380 case VMINPSZ128rmbk:
22381 case VMINPSZ128rmbkz:
22382 case VMINPSZ128rmk:
22383 case VMINPSZ128rmkz:
22384 case VMINPSZ128rr:
22385 case VMINPSZ128rrk:
22386 case VMINPSZ128rrkz:
22387 case VMINPSZ256rm:
22388 case VMINPSZ256rmb:
22389 case VMINPSZ256rmbk:
22390 case VMINPSZ256rmbkz:
22391 case VMINPSZ256rmk:
22392 case VMINPSZ256rmkz:
22393 case VMINPSZ256rr:
22394 case VMINPSZ256rrk:
22395 case VMINPSZ256rrkz:
22396 case VMINPSZrm:
22397 case VMINPSZrmb:
22398 case VMINPSZrmbk:
22399 case VMINPSZrmbkz:
22400 case VMINPSZrmk:
22401 case VMINPSZrmkz:
22402 case VMINPSZrr:
22403 case VMINPSZrrb:
22404 case VMINPSZrrbk:
22405 case VMINPSZrrbkz:
22406 case VMINPSZrrk:
22407 case VMINPSZrrkz:
22408 case VMINPSrm:
22409 case VMINPSrr:
22410 return true;
22411 }
22412 return false;
22413}
22414
22415bool isVFMSUB231PS(unsigned Opcode) {
22416 switch (Opcode) {
22417 case VFMSUB231PSYm:
22418 case VFMSUB231PSYr:
22419 case VFMSUB231PSZ128m:
22420 case VFMSUB231PSZ128mb:
22421 case VFMSUB231PSZ128mbk:
22422 case VFMSUB231PSZ128mbkz:
22423 case VFMSUB231PSZ128mk:
22424 case VFMSUB231PSZ128mkz:
22425 case VFMSUB231PSZ128r:
22426 case VFMSUB231PSZ128rk:
22427 case VFMSUB231PSZ128rkz:
22428 case VFMSUB231PSZ256m:
22429 case VFMSUB231PSZ256mb:
22430 case VFMSUB231PSZ256mbk:
22431 case VFMSUB231PSZ256mbkz:
22432 case VFMSUB231PSZ256mk:
22433 case VFMSUB231PSZ256mkz:
22434 case VFMSUB231PSZ256r:
22435 case VFMSUB231PSZ256rk:
22436 case VFMSUB231PSZ256rkz:
22437 case VFMSUB231PSZm:
22438 case VFMSUB231PSZmb:
22439 case VFMSUB231PSZmbk:
22440 case VFMSUB231PSZmbkz:
22441 case VFMSUB231PSZmk:
22442 case VFMSUB231PSZmkz:
22443 case VFMSUB231PSZr:
22444 case VFMSUB231PSZrb:
22445 case VFMSUB231PSZrbk:
22446 case VFMSUB231PSZrbkz:
22447 case VFMSUB231PSZrk:
22448 case VFMSUB231PSZrkz:
22449 case VFMSUB231PSm:
22450 case VFMSUB231PSr:
22451 return true;
22452 }
22453 return false;
22454}
22455
22456bool isVPCOMPRESSB(unsigned Opcode) {
22457 switch (Opcode) {
22458 case VPCOMPRESSBZ128mr:
22459 case VPCOMPRESSBZ128mrk:
22460 case VPCOMPRESSBZ128rr:
22461 case VPCOMPRESSBZ128rrk:
22462 case VPCOMPRESSBZ128rrkz:
22463 case VPCOMPRESSBZ256mr:
22464 case VPCOMPRESSBZ256mrk:
22465 case VPCOMPRESSBZ256rr:
22466 case VPCOMPRESSBZ256rrk:
22467 case VPCOMPRESSBZ256rrkz:
22468 case VPCOMPRESSBZmr:
22469 case VPCOMPRESSBZmrk:
22470 case VPCOMPRESSBZrr:
22471 case VPCOMPRESSBZrrk:
22472 case VPCOMPRESSBZrrkz:
22473 return true;
22474 }
22475 return false;
22476}
22477
22478bool isVCVTPS2HF8(unsigned Opcode) {
22479 switch (Opcode) {
22480 case VCVTPS2HF8Z128rm:
22481 case VCVTPS2HF8Z128rmb:
22482 case VCVTPS2HF8Z128rmbk:
22483 case VCVTPS2HF8Z128rmbkz:
22484 case VCVTPS2HF8Z128rmk:
22485 case VCVTPS2HF8Z128rmkz:
22486 case VCVTPS2HF8Z128rr:
22487 case VCVTPS2HF8Z128rrk:
22488 case VCVTPS2HF8Z128rrkz:
22489 case VCVTPS2HF8Z256rm:
22490 case VCVTPS2HF8Z256rmb:
22491 case VCVTPS2HF8Z256rmbk:
22492 case VCVTPS2HF8Z256rmbkz:
22493 case VCVTPS2HF8Z256rmk:
22494 case VCVTPS2HF8Z256rmkz:
22495 case VCVTPS2HF8Z256rr:
22496 case VCVTPS2HF8Z256rrk:
22497 case VCVTPS2HF8Z256rrkz:
22498 case VCVTPS2HF8Zrm:
22499 case VCVTPS2HF8Zrmb:
22500 case VCVTPS2HF8Zrmbk:
22501 case VCVTPS2HF8Zrmbkz:
22502 case VCVTPS2HF8Zrmk:
22503 case VCVTPS2HF8Zrmkz:
22504 case VCVTPS2HF8Zrr:
22505 case VCVTPS2HF8Zrrk:
22506 case VCVTPS2HF8Zrrkz:
22507 return true;
22508 }
22509 return false;
22510}
22511
22512bool isVPCMPEQQ(unsigned Opcode) {
22513 switch (Opcode) {
22514 case VPCMPEQQYrm:
22515 case VPCMPEQQYrr:
22516 case VPCMPEQQZ128rm:
22517 case VPCMPEQQZ128rmb:
22518 case VPCMPEQQZ128rmbk:
22519 case VPCMPEQQZ128rmk:
22520 case VPCMPEQQZ128rr:
22521 case VPCMPEQQZ128rrk:
22522 case VPCMPEQQZ256rm:
22523 case VPCMPEQQZ256rmb:
22524 case VPCMPEQQZ256rmbk:
22525 case VPCMPEQQZ256rmk:
22526 case VPCMPEQQZ256rr:
22527 case VPCMPEQQZ256rrk:
22528 case VPCMPEQQZrm:
22529 case VPCMPEQQZrmb:
22530 case VPCMPEQQZrmbk:
22531 case VPCMPEQQZrmk:
22532 case VPCMPEQQZrr:
22533 case VPCMPEQQZrrk:
22534 case VPCMPEQQrm:
22535 case VPCMPEQQrr:
22536 return true;
22537 }
22538 return false;
22539}
22540
22541bool isVRCPSS(unsigned Opcode) {
22542 switch (Opcode) {
22543 case VRCPSSm_Int:
22544 case VRCPSSr_Int:
22545 return true;
22546 }
22547 return false;
22548}
22549
22550bool isVSCATTERPF1DPS(unsigned Opcode) {
22551 return Opcode == VSCATTERPF1DPSm;
22552}
22553
22554bool isVPHADDUBW(unsigned Opcode) {
22555 switch (Opcode) {
22556 case VPHADDUBWrm:
22557 case VPHADDUBWrr:
22558 return true;
22559 }
22560 return false;
22561}
22562
22563bool isVSUBPD(unsigned Opcode) {
22564 switch (Opcode) {
22565 case VSUBPDYrm:
22566 case VSUBPDYrr:
22567 case VSUBPDZ128rm:
22568 case VSUBPDZ128rmb:
22569 case VSUBPDZ128rmbk:
22570 case VSUBPDZ128rmbkz:
22571 case VSUBPDZ128rmk:
22572 case VSUBPDZ128rmkz:
22573 case VSUBPDZ128rr:
22574 case VSUBPDZ128rrk:
22575 case VSUBPDZ128rrkz:
22576 case VSUBPDZ256rm:
22577 case VSUBPDZ256rmb:
22578 case VSUBPDZ256rmbk:
22579 case VSUBPDZ256rmbkz:
22580 case VSUBPDZ256rmk:
22581 case VSUBPDZ256rmkz:
22582 case VSUBPDZ256rr:
22583 case VSUBPDZ256rrk:
22584 case VSUBPDZ256rrkz:
22585 case VSUBPDZrm:
22586 case VSUBPDZrmb:
22587 case VSUBPDZrmbk:
22588 case VSUBPDZrmbkz:
22589 case VSUBPDZrmk:
22590 case VSUBPDZrmkz:
22591 case VSUBPDZrr:
22592 case VSUBPDZrrb:
22593 case VSUBPDZrrbk:
22594 case VSUBPDZrrbkz:
22595 case VSUBPDZrrk:
22596 case VSUBPDZrrkz:
22597 case VSUBPDrm:
22598 case VSUBPDrr:
22599 return true;
22600 }
22601 return false;
22602}
22603
22604bool isVPSCATTERQQ(unsigned Opcode) {
22605 switch (Opcode) {
22606 case VPSCATTERQQZ128mr:
22607 case VPSCATTERQQZ256mr:
22608 case VPSCATTERQQZmr:
22609 return true;
22610 }
22611 return false;
22612}
22613
22614bool isVCVTW2PH(unsigned Opcode) {
22615 switch (Opcode) {
22616 case VCVTW2PHZ128rm:
22617 case VCVTW2PHZ128rmb:
22618 case VCVTW2PHZ128rmbk:
22619 case VCVTW2PHZ128rmbkz:
22620 case VCVTW2PHZ128rmk:
22621 case VCVTW2PHZ128rmkz:
22622 case VCVTW2PHZ128rr:
22623 case VCVTW2PHZ128rrk:
22624 case VCVTW2PHZ128rrkz:
22625 case VCVTW2PHZ256rm:
22626 case VCVTW2PHZ256rmb:
22627 case VCVTW2PHZ256rmbk:
22628 case VCVTW2PHZ256rmbkz:
22629 case VCVTW2PHZ256rmk:
22630 case VCVTW2PHZ256rmkz:
22631 case VCVTW2PHZ256rr:
22632 case VCVTW2PHZ256rrk:
22633 case VCVTW2PHZ256rrkz:
22634 case VCVTW2PHZrm:
22635 case VCVTW2PHZrmb:
22636 case VCVTW2PHZrmbk:
22637 case VCVTW2PHZrmbkz:
22638 case VCVTW2PHZrmk:
22639 case VCVTW2PHZrmkz:
22640 case VCVTW2PHZrr:
22641 case VCVTW2PHZrrb:
22642 case VCVTW2PHZrrbk:
22643 case VCVTW2PHZrrbkz:
22644 case VCVTW2PHZrrk:
22645 case VCVTW2PHZrrkz:
22646 return true;
22647 }
22648 return false;
22649}
22650
22651bool isVFMADDCPH(unsigned Opcode) {
22652 switch (Opcode) {
22653 case VFMADDCPHZ128m:
22654 case VFMADDCPHZ128mb:
22655 case VFMADDCPHZ128mbk:
22656 case VFMADDCPHZ128mbkz:
22657 case VFMADDCPHZ128mk:
22658 case VFMADDCPHZ128mkz:
22659 case VFMADDCPHZ128r:
22660 case VFMADDCPHZ128rk:
22661 case VFMADDCPHZ128rkz:
22662 case VFMADDCPHZ256m:
22663 case VFMADDCPHZ256mb:
22664 case VFMADDCPHZ256mbk:
22665 case VFMADDCPHZ256mbkz:
22666 case VFMADDCPHZ256mk:
22667 case VFMADDCPHZ256mkz:
22668 case VFMADDCPHZ256r:
22669 case VFMADDCPHZ256rk:
22670 case VFMADDCPHZ256rkz:
22671 case VFMADDCPHZm:
22672 case VFMADDCPHZmb:
22673 case VFMADDCPHZmbk:
22674 case VFMADDCPHZmbkz:
22675 case VFMADDCPHZmk:
22676 case VFMADDCPHZmkz:
22677 case VFMADDCPHZr:
22678 case VFMADDCPHZrb:
22679 case VFMADDCPHZrbk:
22680 case VFMADDCPHZrbkz:
22681 case VFMADDCPHZrk:
22682 case VFMADDCPHZrkz:
22683 return true;
22684 }
22685 return false;
22686}
22687
22688bool isVPACKUSDW(unsigned Opcode) {
22689 switch (Opcode) {
22690 case VPACKUSDWYrm:
22691 case VPACKUSDWYrr:
22692 case VPACKUSDWZ128rm:
22693 case VPACKUSDWZ128rmb:
22694 case VPACKUSDWZ128rmbk:
22695 case VPACKUSDWZ128rmbkz:
22696 case VPACKUSDWZ128rmk:
22697 case VPACKUSDWZ128rmkz:
22698 case VPACKUSDWZ128rr:
22699 case VPACKUSDWZ128rrk:
22700 case VPACKUSDWZ128rrkz:
22701 case VPACKUSDWZ256rm:
22702 case VPACKUSDWZ256rmb:
22703 case VPACKUSDWZ256rmbk:
22704 case VPACKUSDWZ256rmbkz:
22705 case VPACKUSDWZ256rmk:
22706 case VPACKUSDWZ256rmkz:
22707 case VPACKUSDWZ256rr:
22708 case VPACKUSDWZ256rrk:
22709 case VPACKUSDWZ256rrkz:
22710 case VPACKUSDWZrm:
22711 case VPACKUSDWZrmb:
22712 case VPACKUSDWZrmbk:
22713 case VPACKUSDWZrmbkz:
22714 case VPACKUSDWZrmk:
22715 case VPACKUSDWZrmkz:
22716 case VPACKUSDWZrr:
22717 case VPACKUSDWZrrk:
22718 case VPACKUSDWZrrkz:
22719 case VPACKUSDWrm:
22720 case VPACKUSDWrr:
22721 return true;
22722 }
22723 return false;
22724}
22725
22726bool isVSCALEFSS(unsigned Opcode) {
22727 switch (Opcode) {
22728 case VSCALEFSSZrm:
22729 case VSCALEFSSZrmk:
22730 case VSCALEFSSZrmkz:
22731 case VSCALEFSSZrr:
22732 case VSCALEFSSZrrb_Int:
22733 case VSCALEFSSZrrbk_Int:
22734 case VSCALEFSSZrrbkz_Int:
22735 case VSCALEFSSZrrk:
22736 case VSCALEFSSZrrkz:
22737 return true;
22738 }
22739 return false;
22740}
22741
22742bool isAESIMC(unsigned Opcode) {
22743 switch (Opcode) {
22744 case AESIMCrm:
22745 case AESIMCrr:
22746 return true;
22747 }
22748 return false;
22749}
22750
22751bool isVRCP28PS(unsigned Opcode) {
22752 switch (Opcode) {
22753 case VRCP28PSZm:
22754 case VRCP28PSZmb:
22755 case VRCP28PSZmbk:
22756 case VRCP28PSZmbkz:
22757 case VRCP28PSZmk:
22758 case VRCP28PSZmkz:
22759 case VRCP28PSZr:
22760 case VRCP28PSZrb:
22761 case VRCP28PSZrbk:
22762 case VRCP28PSZrbkz:
22763 case VRCP28PSZrk:
22764 case VRCP28PSZrkz:
22765 return true;
22766 }
22767 return false;
22768}
22769
22770bool isAAND(unsigned Opcode) {
22771 switch (Opcode) {
22772 case AAND32mr:
22773 case AAND32mr_EVEX:
22774 case AAND64mr:
22775 case AAND64mr_EVEX:
22776 return true;
22777 }
22778 return false;
22779}
22780
22781bool isDAA(unsigned Opcode) {
22782 return Opcode == DAA;
22783}
22784
22785bool isKTESTW(unsigned Opcode) {
22786 return Opcode == KTESTWkk;
22787}
22788
22789bool isVCVTPD2UDQ(unsigned Opcode) {
22790 switch (Opcode) {
22791 case VCVTPD2UDQZ128rm:
22792 case VCVTPD2UDQZ128rmb:
22793 case VCVTPD2UDQZ128rmbk:
22794 case VCVTPD2UDQZ128rmbkz:
22795 case VCVTPD2UDQZ128rmk:
22796 case VCVTPD2UDQZ128rmkz:
22797 case VCVTPD2UDQZ128rr:
22798 case VCVTPD2UDQZ128rrk:
22799 case VCVTPD2UDQZ128rrkz:
22800 case VCVTPD2UDQZ256rm:
22801 case VCVTPD2UDQZ256rmb:
22802 case VCVTPD2UDQZ256rmbk:
22803 case VCVTPD2UDQZ256rmbkz:
22804 case VCVTPD2UDQZ256rmk:
22805 case VCVTPD2UDQZ256rmkz:
22806 case VCVTPD2UDQZ256rr:
22807 case VCVTPD2UDQZ256rrk:
22808 case VCVTPD2UDQZ256rrkz:
22809 case VCVTPD2UDQZrm:
22810 case VCVTPD2UDQZrmb:
22811 case VCVTPD2UDQZrmbk:
22812 case VCVTPD2UDQZrmbkz:
22813 case VCVTPD2UDQZrmk:
22814 case VCVTPD2UDQZrmkz:
22815 case VCVTPD2UDQZrr:
22816 case VCVTPD2UDQZrrb:
22817 case VCVTPD2UDQZrrbk:
22818 case VCVTPD2UDQZrrbkz:
22819 case VCVTPD2UDQZrrk:
22820 case VCVTPD2UDQZrrkz:
22821 return true;
22822 }
22823 return false;
22824}
22825
22826bool isVPADDQ(unsigned Opcode) {
22827 switch (Opcode) {
22828 case VPADDQYrm:
22829 case VPADDQYrr:
22830 case VPADDQZ128rm:
22831 case VPADDQZ128rmb:
22832 case VPADDQZ128rmbk:
22833 case VPADDQZ128rmbkz:
22834 case VPADDQZ128rmk:
22835 case VPADDQZ128rmkz:
22836 case VPADDQZ128rr:
22837 case VPADDQZ128rrk:
22838 case VPADDQZ128rrkz:
22839 case VPADDQZ256rm:
22840 case VPADDQZ256rmb:
22841 case VPADDQZ256rmbk:
22842 case VPADDQZ256rmbkz:
22843 case VPADDQZ256rmk:
22844 case VPADDQZ256rmkz:
22845 case VPADDQZ256rr:
22846 case VPADDQZ256rrk:
22847 case VPADDQZ256rrkz:
22848 case VPADDQZrm:
22849 case VPADDQZrmb:
22850 case VPADDQZrmbk:
22851 case VPADDQZrmbkz:
22852 case VPADDQZrmk:
22853 case VPADDQZrmkz:
22854 case VPADDQZrr:
22855 case VPADDQZrrk:
22856 case VPADDQZrrkz:
22857 case VPADDQrm:
22858 case VPADDQrr:
22859 return true;
22860 }
22861 return false;
22862}
22863
22864bool isPALIGNR(unsigned Opcode) {
22865 switch (Opcode) {
22866 case MMX_PALIGNRrmi:
22867 case MMX_PALIGNRrri:
22868 case PALIGNRrmi:
22869 case PALIGNRrri:
22870 return true;
22871 }
22872 return false;
22873}
22874
22875bool isPMAXUW(unsigned Opcode) {
22876 switch (Opcode) {
22877 case PMAXUWrm:
22878 case PMAXUWrr:
22879 return true;
22880 }
22881 return false;
22882}
22883
22884bool isVFMADDSD(unsigned Opcode) {
22885 switch (Opcode) {
22886 case VFMADDSD4mr:
22887 case VFMADDSD4rm:
22888 case VFMADDSD4rr:
22889 case VFMADDSD4rr_REV:
22890 return true;
22891 }
22892 return false;
22893}
22894
22895bool isPFMAX(unsigned Opcode) {
22896 switch (Opcode) {
22897 case PFMAXrm:
22898 case PFMAXrr:
22899 return true;
22900 }
22901 return false;
22902}
22903
22904bool isVPOR(unsigned Opcode) {
22905 switch (Opcode) {
22906 case VPORYrm:
22907 case VPORYrr:
22908 case VPORrm:
22909 case VPORrr:
22910 return true;
22911 }
22912 return false;
22913}
22914
22915bool isVPSUBB(unsigned Opcode) {
22916 switch (Opcode) {
22917 case VPSUBBYrm:
22918 case VPSUBBYrr:
22919 case VPSUBBZ128rm:
22920 case VPSUBBZ128rmk:
22921 case VPSUBBZ128rmkz:
22922 case VPSUBBZ128rr:
22923 case VPSUBBZ128rrk:
22924 case VPSUBBZ128rrkz:
22925 case VPSUBBZ256rm:
22926 case VPSUBBZ256rmk:
22927 case VPSUBBZ256rmkz:
22928 case VPSUBBZ256rr:
22929 case VPSUBBZ256rrk:
22930 case VPSUBBZ256rrkz:
22931 case VPSUBBZrm:
22932 case VPSUBBZrmk:
22933 case VPSUBBZrmkz:
22934 case VPSUBBZrr:
22935 case VPSUBBZrrk:
22936 case VPSUBBZrrkz:
22937 case VPSUBBrm:
22938 case VPSUBBrr:
22939 return true;
22940 }
22941 return false;
22942}
22943
22944bool isVPAVGB(unsigned Opcode) {
22945 switch (Opcode) {
22946 case VPAVGBYrm:
22947 case VPAVGBYrr:
22948 case VPAVGBZ128rm:
22949 case VPAVGBZ128rmk:
22950 case VPAVGBZ128rmkz:
22951 case VPAVGBZ128rr:
22952 case VPAVGBZ128rrk:
22953 case VPAVGBZ128rrkz:
22954 case VPAVGBZ256rm:
22955 case VPAVGBZ256rmk:
22956 case VPAVGBZ256rmkz:
22957 case VPAVGBZ256rr:
22958 case VPAVGBZ256rrk:
22959 case VPAVGBZ256rrkz:
22960 case VPAVGBZrm:
22961 case VPAVGBZrmk:
22962 case VPAVGBZrmkz:
22963 case VPAVGBZrr:
22964 case VPAVGBZrrk:
22965 case VPAVGBZrrkz:
22966 case VPAVGBrm:
22967 case VPAVGBrr:
22968 return true;
22969 }
22970 return false;
22971}
22972
22973bool isINSB(unsigned Opcode) {
22974 return Opcode == INSB;
22975}
22976
22977bool isFYL2X(unsigned Opcode) {
22978 return Opcode == FYL2X;
22979}
22980
22981bool isVFNMSUB132PD(unsigned Opcode) {
22982 switch (Opcode) {
22983 case VFNMSUB132PDYm:
22984 case VFNMSUB132PDYr:
22985 case VFNMSUB132PDZ128m:
22986 case VFNMSUB132PDZ128mb:
22987 case VFNMSUB132PDZ128mbk:
22988 case VFNMSUB132PDZ128mbkz:
22989 case VFNMSUB132PDZ128mk:
22990 case VFNMSUB132PDZ128mkz:
22991 case VFNMSUB132PDZ128r:
22992 case VFNMSUB132PDZ128rk:
22993 case VFNMSUB132PDZ128rkz:
22994 case VFNMSUB132PDZ256m:
22995 case VFNMSUB132PDZ256mb:
22996 case VFNMSUB132PDZ256mbk:
22997 case VFNMSUB132PDZ256mbkz:
22998 case VFNMSUB132PDZ256mk:
22999 case VFNMSUB132PDZ256mkz:
23000 case VFNMSUB132PDZ256r:
23001 case VFNMSUB132PDZ256rk:
23002 case VFNMSUB132PDZ256rkz:
23003 case VFNMSUB132PDZm:
23004 case VFNMSUB132PDZmb:
23005 case VFNMSUB132PDZmbk:
23006 case VFNMSUB132PDZmbkz:
23007 case VFNMSUB132PDZmk:
23008 case VFNMSUB132PDZmkz:
23009 case VFNMSUB132PDZr:
23010 case VFNMSUB132PDZrb:
23011 case VFNMSUB132PDZrbk:
23012 case VFNMSUB132PDZrbkz:
23013 case VFNMSUB132PDZrk:
23014 case VFNMSUB132PDZrkz:
23015 case VFNMSUB132PDm:
23016 case VFNMSUB132PDr:
23017 return true;
23018 }
23019 return false;
23020}
23021
23022bool isVFNMSUBPS(unsigned Opcode) {
23023 switch (Opcode) {
23024 case VFNMSUBPS4Ymr:
23025 case VFNMSUBPS4Yrm:
23026 case VFNMSUBPS4Yrr:
23027 case VFNMSUBPS4Yrr_REV:
23028 case VFNMSUBPS4mr:
23029 case VFNMSUBPS4rm:
23030 case VFNMSUBPS4rr:
23031 case VFNMSUBPS4rr_REV:
23032 return true;
23033 }
23034 return false;
23035}
23036
23037bool isVFMADD231PS(unsigned Opcode) {
23038 switch (Opcode) {
23039 case VFMADD231PSYm:
23040 case VFMADD231PSYr:
23041 case VFMADD231PSZ128m:
23042 case VFMADD231PSZ128mb:
23043 case VFMADD231PSZ128mbk:
23044 case VFMADD231PSZ128mbkz:
23045 case VFMADD231PSZ128mk:
23046 case VFMADD231PSZ128mkz:
23047 case VFMADD231PSZ128r:
23048 case VFMADD231PSZ128rk:
23049 case VFMADD231PSZ128rkz:
23050 case VFMADD231PSZ256m:
23051 case VFMADD231PSZ256mb:
23052 case VFMADD231PSZ256mbk:
23053 case VFMADD231PSZ256mbkz:
23054 case VFMADD231PSZ256mk:
23055 case VFMADD231PSZ256mkz:
23056 case VFMADD231PSZ256r:
23057 case VFMADD231PSZ256rk:
23058 case VFMADD231PSZ256rkz:
23059 case VFMADD231PSZm:
23060 case VFMADD231PSZmb:
23061 case VFMADD231PSZmbk:
23062 case VFMADD231PSZmbkz:
23063 case VFMADD231PSZmk:
23064 case VFMADD231PSZmkz:
23065 case VFMADD231PSZr:
23066 case VFMADD231PSZrb:
23067 case VFMADD231PSZrbk:
23068 case VFMADD231PSZrbkz:
23069 case VFMADD231PSZrk:
23070 case VFMADD231PSZrkz:
23071 case VFMADD231PSm:
23072 case VFMADD231PSr:
23073 return true;
23074 }
23075 return false;
23076}
23077
23078bool isVCVTTSS2SI(unsigned Opcode) {
23079 switch (Opcode) {
23080 case VCVTTSS2SI64Zrm_Int:
23081 case VCVTTSS2SI64Zrr_Int:
23082 case VCVTTSS2SI64Zrrb_Int:
23083 case VCVTTSS2SI64rm_Int:
23084 case VCVTTSS2SI64rr_Int:
23085 case VCVTTSS2SIZrm_Int:
23086 case VCVTTSS2SIZrr_Int:
23087 case VCVTTSS2SIZrrb_Int:
23088 case VCVTTSS2SIrm_Int:
23089 case VCVTTSS2SIrr_Int:
23090 return true;
23091 }
23092 return false;
23093}
23094
23095bool isTCMMRLFP16PS(unsigned Opcode) {
23096 return Opcode == TCMMRLFP16PS;
23097}
23098
23099bool isFCOMPP(unsigned Opcode) {
23100 return Opcode == FCOMPP;
23101}
23102
23103bool isMOVD(unsigned Opcode) {
23104 switch (Opcode) {
23105 case MMX_MOVD64grr:
23106 case MMX_MOVD64mr:
23107 case MMX_MOVD64rm:
23108 case MMX_MOVD64rr:
23109 case MOVDI2PDIrm:
23110 case MOVDI2PDIrr:
23111 case MOVPDI2DImr:
23112 case MOVPDI2DIrr:
23113 return true;
23114 }
23115 return false;
23116}
23117
23118bool isMOVBE(unsigned Opcode) {
23119 switch (Opcode) {
23120 case MOVBE16mr:
23121 case MOVBE16mr_EVEX:
23122 case MOVBE16rm:
23123 case MOVBE16rm_EVEX:
23124 case MOVBE16rr:
23125 case MOVBE16rr_REV:
23126 case MOVBE32mr:
23127 case MOVBE32mr_EVEX:
23128 case MOVBE32rm:
23129 case MOVBE32rm_EVEX:
23130 case MOVBE32rr:
23131 case MOVBE32rr_REV:
23132 case MOVBE64mr:
23133 case MOVBE64mr_EVEX:
23134 case MOVBE64rm:
23135 case MOVBE64rm_EVEX:
23136 case MOVBE64rr:
23137 case MOVBE64rr_REV:
23138 return true;
23139 }
23140 return false;
23141}
23142
23143bool isVP2INTERSECTD(unsigned Opcode) {
23144 switch (Opcode) {
23145 case VP2INTERSECTDZ128rm:
23146 case VP2INTERSECTDZ128rmb:
23147 case VP2INTERSECTDZ128rr:
23148 case VP2INTERSECTDZ256rm:
23149 case VP2INTERSECTDZ256rmb:
23150 case VP2INTERSECTDZ256rr:
23151 case VP2INTERSECTDZrm:
23152 case VP2INTERSECTDZrmb:
23153 case VP2INTERSECTDZrr:
23154 return true;
23155 }
23156 return false;
23157}
23158
23159bool isVPMULLQ(unsigned Opcode) {
23160 switch (Opcode) {
23161 case VPMULLQZ128rm:
23162 case VPMULLQZ128rmb:
23163 case VPMULLQZ128rmbk:
23164 case VPMULLQZ128rmbkz:
23165 case VPMULLQZ128rmk:
23166 case VPMULLQZ128rmkz:
23167 case VPMULLQZ128rr:
23168 case VPMULLQZ128rrk:
23169 case VPMULLQZ128rrkz:
23170 case VPMULLQZ256rm:
23171 case VPMULLQZ256rmb:
23172 case VPMULLQZ256rmbk:
23173 case VPMULLQZ256rmbkz:
23174 case VPMULLQZ256rmk:
23175 case VPMULLQZ256rmkz:
23176 case VPMULLQZ256rr:
23177 case VPMULLQZ256rrk:
23178 case VPMULLQZ256rrkz:
23179 case VPMULLQZrm:
23180 case VPMULLQZrmb:
23181 case VPMULLQZrmbk:
23182 case VPMULLQZrmbkz:
23183 case VPMULLQZrmk:
23184 case VPMULLQZrmkz:
23185 case VPMULLQZrr:
23186 case VPMULLQZrrk:
23187 case VPMULLQZrrkz:
23188 return true;
23189 }
23190 return false;
23191}
23192
23193bool isVSCALEFPS(unsigned Opcode) {
23194 switch (Opcode) {
23195 case VSCALEFPSZ128rm:
23196 case VSCALEFPSZ128rmb:
23197 case VSCALEFPSZ128rmbk:
23198 case VSCALEFPSZ128rmbkz:
23199 case VSCALEFPSZ128rmk:
23200 case VSCALEFPSZ128rmkz:
23201 case VSCALEFPSZ128rr:
23202 case VSCALEFPSZ128rrk:
23203 case VSCALEFPSZ128rrkz:
23204 case VSCALEFPSZ256rm:
23205 case VSCALEFPSZ256rmb:
23206 case VSCALEFPSZ256rmbk:
23207 case VSCALEFPSZ256rmbkz:
23208 case VSCALEFPSZ256rmk:
23209 case VSCALEFPSZ256rmkz:
23210 case VSCALEFPSZ256rr:
23211 case VSCALEFPSZ256rrk:
23212 case VSCALEFPSZ256rrkz:
23213 case VSCALEFPSZrm:
23214 case VSCALEFPSZrmb:
23215 case VSCALEFPSZrmbk:
23216 case VSCALEFPSZrmbkz:
23217 case VSCALEFPSZrmk:
23218 case VSCALEFPSZrmkz:
23219 case VSCALEFPSZrr:
23220 case VSCALEFPSZrrb:
23221 case VSCALEFPSZrrbk:
23222 case VSCALEFPSZrrbkz:
23223 case VSCALEFPSZrrk:
23224 case VSCALEFPSZrrkz:
23225 return true;
23226 }
23227 return false;
23228}
23229
23230bool isVPMACSDQH(unsigned Opcode) {
23231 switch (Opcode) {
23232 case VPMACSDQHrm:
23233 case VPMACSDQHrr:
23234 return true;
23235 }
23236 return false;
23237}
23238
23239bool isVPTESTNMD(unsigned Opcode) {
23240 switch (Opcode) {
23241 case VPTESTNMDZ128rm:
23242 case VPTESTNMDZ128rmb:
23243 case VPTESTNMDZ128rmbk:
23244 case VPTESTNMDZ128rmk:
23245 case VPTESTNMDZ128rr:
23246 case VPTESTNMDZ128rrk:
23247 case VPTESTNMDZ256rm:
23248 case VPTESTNMDZ256rmb:
23249 case VPTESTNMDZ256rmbk:
23250 case VPTESTNMDZ256rmk:
23251 case VPTESTNMDZ256rr:
23252 case VPTESTNMDZ256rrk:
23253 case VPTESTNMDZrm:
23254 case VPTESTNMDZrmb:
23255 case VPTESTNMDZrmbk:
23256 case VPTESTNMDZrmk:
23257 case VPTESTNMDZrr:
23258 case VPTESTNMDZrrk:
23259 return true;
23260 }
23261 return false;
23262}
23263
23264bool isFCOMP(unsigned Opcode) {
23265 switch (Opcode) {
23266 case COMP_FST0r:
23267 case FCOMP32m:
23268 case FCOMP64m:
23269 return true;
23270 }
23271 return false;
23272}
23273
23274bool isPREFETCHWT1(unsigned Opcode) {
23275 return Opcode == PREFETCHWT1;
23276}
23277
23278bool isVCMPSD(unsigned Opcode) {
23279 switch (Opcode) {
23280 case VCMPSDZrmi_Int:
23281 case VCMPSDZrmik_Int:
23282 case VCMPSDZrri_Int:
23283 case VCMPSDZrrib_Int:
23284 case VCMPSDZrribk_Int:
23285 case VCMPSDZrrik_Int:
23286 case VCMPSDrmi_Int:
23287 case VCMPSDrri_Int:
23288 return true;
23289 }
23290 return false;
23291}
23292
23293bool isSGDTD(unsigned Opcode) {
23294 return Opcode == SGDT32m;
23295}
23296
23297bool isWRUSSD(unsigned Opcode) {
23298 switch (Opcode) {
23299 case WRUSSD:
23300 case WRUSSD_EVEX:
23301 return true;
23302 }
23303 return false;
23304}
23305
23306bool isFSUBP(unsigned Opcode) {
23307 return Opcode == SUB_FPrST0;
23308}
23309
23310bool isVUNPCKLPS(unsigned Opcode) {
23311 switch (Opcode) {
23312 case VUNPCKLPSYrm:
23313 case VUNPCKLPSYrr:
23314 case VUNPCKLPSZ128rm:
23315 case VUNPCKLPSZ128rmb:
23316 case VUNPCKLPSZ128rmbk:
23317 case VUNPCKLPSZ128rmbkz:
23318 case VUNPCKLPSZ128rmk:
23319 case VUNPCKLPSZ128rmkz:
23320 case VUNPCKLPSZ128rr:
23321 case VUNPCKLPSZ128rrk:
23322 case VUNPCKLPSZ128rrkz:
23323 case VUNPCKLPSZ256rm:
23324 case VUNPCKLPSZ256rmb:
23325 case VUNPCKLPSZ256rmbk:
23326 case VUNPCKLPSZ256rmbkz:
23327 case VUNPCKLPSZ256rmk:
23328 case VUNPCKLPSZ256rmkz:
23329 case VUNPCKLPSZ256rr:
23330 case VUNPCKLPSZ256rrk:
23331 case VUNPCKLPSZ256rrkz:
23332 case VUNPCKLPSZrm:
23333 case VUNPCKLPSZrmb:
23334 case VUNPCKLPSZrmbk:
23335 case VUNPCKLPSZrmbkz:
23336 case VUNPCKLPSZrmk:
23337 case VUNPCKLPSZrmkz:
23338 case VUNPCKLPSZrr:
23339 case VUNPCKLPSZrrk:
23340 case VUNPCKLPSZrrkz:
23341 case VUNPCKLPSrm:
23342 case VUNPCKLPSrr:
23343 return true;
23344 }
23345 return false;
23346}
23347
23348bool isVBMACXOR16X16X16(unsigned Opcode) {
23349 switch (Opcode) {
23350 case VBMACXORZ256rm:
23351 case VBMACXORZ256rmb:
23352 case VBMACXORZ256rmbk:
23353 case VBMACXORZ256rmbkz:
23354 case VBMACXORZ256rmk:
23355 case VBMACXORZ256rmkz:
23356 case VBMACXORZ256rr:
23357 case VBMACXORZ256rrk:
23358 case VBMACXORZ256rrkz:
23359 case VBMACXORZrm:
23360 case VBMACXORZrmb:
23361 case VBMACXORZrmbk:
23362 case VBMACXORZrmbkz:
23363 case VBMACXORZrmk:
23364 case VBMACXORZrmkz:
23365 case VBMACXORZrr:
23366 case VBMACXORZrrk:
23367 case VBMACXORZrrkz:
23368 return true;
23369 }
23370 return false;
23371}
23372
23373bool isVFNMSUB213SS(unsigned Opcode) {
23374 switch (Opcode) {
23375 case VFNMSUB213SSZm_Int:
23376 case VFNMSUB213SSZmk_Int:
23377 case VFNMSUB213SSZmkz_Int:
23378 case VFNMSUB213SSZr_Int:
23379 case VFNMSUB213SSZrb_Int:
23380 case VFNMSUB213SSZrbk_Int:
23381 case VFNMSUB213SSZrbkz_Int:
23382 case VFNMSUB213SSZrk_Int:
23383 case VFNMSUB213SSZrkz_Int:
23384 case VFNMSUB213SSm_Int:
23385 case VFNMSUB213SSr_Int:
23386 return true;
23387 }
23388 return false;
23389}
23390
23391bool isROUNDPD(unsigned Opcode) {
23392 switch (Opcode) {
23393 case ROUNDPDmi:
23394 case ROUNDPDri:
23395 return true;
23396 }
23397 return false;
23398}
23399
23400bool isVPMAXSW(unsigned Opcode) {
23401 switch (Opcode) {
23402 case VPMAXSWYrm:
23403 case VPMAXSWYrr:
23404 case VPMAXSWZ128rm:
23405 case VPMAXSWZ128rmk:
23406 case VPMAXSWZ128rmkz:
23407 case VPMAXSWZ128rr:
23408 case VPMAXSWZ128rrk:
23409 case VPMAXSWZ128rrkz:
23410 case VPMAXSWZ256rm:
23411 case VPMAXSWZ256rmk:
23412 case VPMAXSWZ256rmkz:
23413 case VPMAXSWZ256rr:
23414 case VPMAXSWZ256rrk:
23415 case VPMAXSWZ256rrkz:
23416 case VPMAXSWZrm:
23417 case VPMAXSWZrmk:
23418 case VPMAXSWZrmkz:
23419 case VPMAXSWZrr:
23420 case VPMAXSWZrrk:
23421 case VPMAXSWZrrkz:
23422 case VPMAXSWrm:
23423 case VPMAXSWrr:
23424 return true;
23425 }
23426 return false;
23427}
23428
23429bool isVCVTTPH2DQ(unsigned Opcode) {
23430 switch (Opcode) {
23431 case VCVTTPH2DQZ128rm:
23432 case VCVTTPH2DQZ128rmb:
23433 case VCVTTPH2DQZ128rmbk:
23434 case VCVTTPH2DQZ128rmbkz:
23435 case VCVTTPH2DQZ128rmk:
23436 case VCVTTPH2DQZ128rmkz:
23437 case VCVTTPH2DQZ128rr:
23438 case VCVTTPH2DQZ128rrk:
23439 case VCVTTPH2DQZ128rrkz:
23440 case VCVTTPH2DQZ256rm:
23441 case VCVTTPH2DQZ256rmb:
23442 case VCVTTPH2DQZ256rmbk:
23443 case VCVTTPH2DQZ256rmbkz:
23444 case VCVTTPH2DQZ256rmk:
23445 case VCVTTPH2DQZ256rmkz:
23446 case VCVTTPH2DQZ256rr:
23447 case VCVTTPH2DQZ256rrk:
23448 case VCVTTPH2DQZ256rrkz:
23449 case VCVTTPH2DQZrm:
23450 case VCVTTPH2DQZrmb:
23451 case VCVTTPH2DQZrmbk:
23452 case VCVTTPH2DQZrmbkz:
23453 case VCVTTPH2DQZrmk:
23454 case VCVTTPH2DQZrmkz:
23455 case VCVTTPH2DQZrr:
23456 case VCVTTPH2DQZrrb:
23457 case VCVTTPH2DQZrrbk:
23458 case VCVTTPH2DQZrrbkz:
23459 case VCVTTPH2DQZrrk:
23460 case VCVTTPH2DQZrrkz:
23461 return true;
23462 }
23463 return false;
23464}
23465
23466bool isVPUNPCKLWD(unsigned Opcode) {
23467 switch (Opcode) {
23468 case VPUNPCKLWDYrm:
23469 case VPUNPCKLWDYrr:
23470 case VPUNPCKLWDZ128rm:
23471 case VPUNPCKLWDZ128rmk:
23472 case VPUNPCKLWDZ128rmkz:
23473 case VPUNPCKLWDZ128rr:
23474 case VPUNPCKLWDZ128rrk:
23475 case VPUNPCKLWDZ128rrkz:
23476 case VPUNPCKLWDZ256rm:
23477 case VPUNPCKLWDZ256rmk:
23478 case VPUNPCKLWDZ256rmkz:
23479 case VPUNPCKLWDZ256rr:
23480 case VPUNPCKLWDZ256rrk:
23481 case VPUNPCKLWDZ256rrkz:
23482 case VPUNPCKLWDZrm:
23483 case VPUNPCKLWDZrmk:
23484 case VPUNPCKLWDZrmkz:
23485 case VPUNPCKLWDZrr:
23486 case VPUNPCKLWDZrrk:
23487 case VPUNPCKLWDZrrkz:
23488 case VPUNPCKLWDrm:
23489 case VPUNPCKLWDrr:
23490 return true;
23491 }
23492 return false;
23493}
23494
23495bool isKSHIFTLD(unsigned Opcode) {
23496 return Opcode == KSHIFTLDki;
23497}
23498
23499bool isTCVTROWPS2BF16H(unsigned Opcode) {
23500 switch (Opcode) {
23501 case TCVTROWPS2BF16Hrte:
23502 case TCVTROWPS2BF16Hrti:
23503 return true;
23504 }
23505 return false;
23506}
23507
23508bool isVFMADD231SD(unsigned Opcode) {
23509 switch (Opcode) {
23510 case VFMADD231SDZm_Int:
23511 case VFMADD231SDZmk_Int:
23512 case VFMADD231SDZmkz_Int:
23513 case VFMADD231SDZr_Int:
23514 case VFMADD231SDZrb_Int:
23515 case VFMADD231SDZrbk_Int:
23516 case VFMADD231SDZrbkz_Int:
23517 case VFMADD231SDZrk_Int:
23518 case VFMADD231SDZrkz_Int:
23519 case VFMADD231SDm_Int:
23520 case VFMADD231SDr_Int:
23521 return true;
23522 }
23523 return false;
23524}
23525
23526bool isADDPS(unsigned Opcode) {
23527 switch (Opcode) {
23528 case ADDPSrm:
23529 case ADDPSrr:
23530 return true;
23531 }
23532 return false;
23533}
23534
23535bool isVPSLLVD(unsigned Opcode) {
23536 switch (Opcode) {
23537 case VPSLLVDYrm:
23538 case VPSLLVDYrr:
23539 case VPSLLVDZ128rm:
23540 case VPSLLVDZ128rmb:
23541 case VPSLLVDZ128rmbk:
23542 case VPSLLVDZ128rmbkz:
23543 case VPSLLVDZ128rmk:
23544 case VPSLLVDZ128rmkz:
23545 case VPSLLVDZ128rr:
23546 case VPSLLVDZ128rrk:
23547 case VPSLLVDZ128rrkz:
23548 case VPSLLVDZ256rm:
23549 case VPSLLVDZ256rmb:
23550 case VPSLLVDZ256rmbk:
23551 case VPSLLVDZ256rmbkz:
23552 case VPSLLVDZ256rmk:
23553 case VPSLLVDZ256rmkz:
23554 case VPSLLVDZ256rr:
23555 case VPSLLVDZ256rrk:
23556 case VPSLLVDZ256rrkz:
23557 case VPSLLVDZrm:
23558 case VPSLLVDZrmb:
23559 case VPSLLVDZrmbk:
23560 case VPSLLVDZrmbkz:
23561 case VPSLLVDZrmk:
23562 case VPSLLVDZrmkz:
23563 case VPSLLVDZrr:
23564 case VPSLLVDZrrk:
23565 case VPSLLVDZrrkz:
23566 case VPSLLVDrm:
23567 case VPSLLVDrr:
23568 return true;
23569 }
23570 return false;
23571}
23572
23573bool isVFNMADD132SH(unsigned Opcode) {
23574 switch (Opcode) {
23575 case VFNMADD132SHZm_Int:
23576 case VFNMADD132SHZmk_Int:
23577 case VFNMADD132SHZmkz_Int:
23578 case VFNMADD132SHZr_Int:
23579 case VFNMADD132SHZrb_Int:
23580 case VFNMADD132SHZrbk_Int:
23581 case VFNMADD132SHZrbkz_Int:
23582 case VFNMADD132SHZrk_Int:
23583 case VFNMADD132SHZrkz_Int:
23584 return true;
23585 }
23586 return false;
23587}
23588
23589bool isVMOVNTPS(unsigned Opcode) {
23590 switch (Opcode) {
23591 case VMOVNTPSYmr:
23592 case VMOVNTPSZ128mr:
23593 case VMOVNTPSZ256mr:
23594 case VMOVNTPSZmr:
23595 case VMOVNTPSmr:
23596 return true;
23597 }
23598 return false;
23599}
23600
23601bool isVCVTBF82BF4S(unsigned Opcode) {
23602 switch (Opcode) {
23603 case VCVTBF82BF4SZ128mr:
23604 case VCVTBF82BF4SZ128rr:
23605 case VCVTBF82BF4SZ256mr:
23606 case VCVTBF82BF4SZ256rr:
23607 case VCVTBF82BF4SZmr:
23608 case VCVTBF82BF4SZrr:
23609 return true;
23610 }
23611 return false;
23612}
23613
23614bool isVCVTPD2DQ(unsigned Opcode) {
23615 switch (Opcode) {
23616 case VCVTPD2DQYrm:
23617 case VCVTPD2DQYrr:
23618 case VCVTPD2DQZ128rm:
23619 case VCVTPD2DQZ128rmb:
23620 case VCVTPD2DQZ128rmbk:
23621 case VCVTPD2DQZ128rmbkz:
23622 case VCVTPD2DQZ128rmk:
23623 case VCVTPD2DQZ128rmkz:
23624 case VCVTPD2DQZ128rr:
23625 case VCVTPD2DQZ128rrk:
23626 case VCVTPD2DQZ128rrkz:
23627 case VCVTPD2DQZ256rm:
23628 case VCVTPD2DQZ256rmb:
23629 case VCVTPD2DQZ256rmbk:
23630 case VCVTPD2DQZ256rmbkz:
23631 case VCVTPD2DQZ256rmk:
23632 case VCVTPD2DQZ256rmkz:
23633 case VCVTPD2DQZ256rr:
23634 case VCVTPD2DQZ256rrk:
23635 case VCVTPD2DQZ256rrkz:
23636 case VCVTPD2DQZrm:
23637 case VCVTPD2DQZrmb:
23638 case VCVTPD2DQZrmbk:
23639 case VCVTPD2DQZrmbkz:
23640 case VCVTPD2DQZrmk:
23641 case VCVTPD2DQZrmkz:
23642 case VCVTPD2DQZrr:
23643 case VCVTPD2DQZrrb:
23644 case VCVTPD2DQZrrbk:
23645 case VCVTPD2DQZrrbkz:
23646 case VCVTPD2DQZrrk:
23647 case VCVTPD2DQZrrkz:
23648 case VCVTPD2DQrm:
23649 case VCVTPD2DQrr:
23650 return true;
23651 }
23652 return false;
23653}
23654
23655bool isVPXOR(unsigned Opcode) {
23656 switch (Opcode) {
23657 case VPXORYrm:
23658 case VPXORYrr:
23659 case VPXORrm:
23660 case VPXORrr:
23661 return true;
23662 }
23663 return false;
23664}
23665
23666bool isSTMXCSR(unsigned Opcode) {
23667 return Opcode == STMXCSR;
23668}
23669
23670bool isVRCP14SS(unsigned Opcode) {
23671 switch (Opcode) {
23672 case VRCP14SSZrm:
23673 case VRCP14SSZrmk:
23674 case VRCP14SSZrmkz:
23675 case VRCP14SSZrr:
23676 case VRCP14SSZrrk:
23677 case VRCP14SSZrrkz:
23678 return true;
23679 }
23680 return false;
23681}
23682
23683bool isUD2(unsigned Opcode) {
23684 return Opcode == TRAP;
23685}
23686
23687bool isVPOPCNTW(unsigned Opcode) {
23688 switch (Opcode) {
23689 case VPOPCNTWZ128rm:
23690 case VPOPCNTWZ128rmk:
23691 case VPOPCNTWZ128rmkz:
23692 case VPOPCNTWZ128rr:
23693 case VPOPCNTWZ128rrk:
23694 case VPOPCNTWZ128rrkz:
23695 case VPOPCNTWZ256rm:
23696 case VPOPCNTWZ256rmk:
23697 case VPOPCNTWZ256rmkz:
23698 case VPOPCNTWZ256rr:
23699 case VPOPCNTWZ256rrk:
23700 case VPOPCNTWZ256rrkz:
23701 case VPOPCNTWZrm:
23702 case VPOPCNTWZrmk:
23703 case VPOPCNTWZrmkz:
23704 case VPOPCNTWZrr:
23705 case VPOPCNTWZrrk:
23706 case VPOPCNTWZrrkz:
23707 return true;
23708 }
23709 return false;
23710}
23711
23712bool isVRSQRTSH(unsigned Opcode) {
23713 switch (Opcode) {
23714 case VRSQRTSHZrm:
23715 case VRSQRTSHZrmk:
23716 case VRSQRTSHZrmkz:
23717 case VRSQRTSHZrr:
23718 case VRSQRTSHZrrk:
23719 case VRSQRTSHZrrkz:
23720 return true;
23721 }
23722 return false;
23723}
23724
23725bool isVSCATTERPF0DPD(unsigned Opcode) {
23726 return Opcode == VSCATTERPF0DPDm;
23727}
23728
23729bool isVFMADDPS(unsigned Opcode) {
23730 switch (Opcode) {
23731 case VFMADDPS4Ymr:
23732 case VFMADDPS4Yrm:
23733 case VFMADDPS4Yrr:
23734 case VFMADDPS4Yrr_REV:
23735 case VFMADDPS4mr:
23736 case VFMADDPS4rm:
23737 case VFMADDPS4rr:
23738 case VFMADDPS4rr_REV:
23739 return true;
23740 }
23741 return false;
23742}
23743
23744bool isXSAVEC64(unsigned Opcode) {
23745 return Opcode == XSAVEC64;
23746}
23747
23748bool isVPMADDUBSW(unsigned Opcode) {
23749 switch (Opcode) {
23750 case VPMADDUBSWYrm:
23751 case VPMADDUBSWYrr:
23752 case VPMADDUBSWZ128rm:
23753 case VPMADDUBSWZ128rmk:
23754 case VPMADDUBSWZ128rmkz:
23755 case VPMADDUBSWZ128rr:
23756 case VPMADDUBSWZ128rrk:
23757 case VPMADDUBSWZ128rrkz:
23758 case VPMADDUBSWZ256rm:
23759 case VPMADDUBSWZ256rmk:
23760 case VPMADDUBSWZ256rmkz:
23761 case VPMADDUBSWZ256rr:
23762 case VPMADDUBSWZ256rrk:
23763 case VPMADDUBSWZ256rrkz:
23764 case VPMADDUBSWZrm:
23765 case VPMADDUBSWZrmk:
23766 case VPMADDUBSWZrmkz:
23767 case VPMADDUBSWZrr:
23768 case VPMADDUBSWZrrk:
23769 case VPMADDUBSWZrrkz:
23770 case VPMADDUBSWrm:
23771 case VPMADDUBSWrr:
23772 return true;
23773 }
23774 return false;
23775}
23776
23777bool isVPMOVZXDQ(unsigned Opcode) {
23778 switch (Opcode) {
23779 case VPMOVZXDQYrm:
23780 case VPMOVZXDQYrr:
23781 case VPMOVZXDQZ128rm:
23782 case VPMOVZXDQZ128rmk:
23783 case VPMOVZXDQZ128rmkz:
23784 case VPMOVZXDQZ128rr:
23785 case VPMOVZXDQZ128rrk:
23786 case VPMOVZXDQZ128rrkz:
23787 case VPMOVZXDQZ256rm:
23788 case VPMOVZXDQZ256rmk:
23789 case VPMOVZXDQZ256rmkz:
23790 case VPMOVZXDQZ256rr:
23791 case VPMOVZXDQZ256rrk:
23792 case VPMOVZXDQZ256rrkz:
23793 case VPMOVZXDQZrm:
23794 case VPMOVZXDQZrmk:
23795 case VPMOVZXDQZrmkz:
23796 case VPMOVZXDQZrr:
23797 case VPMOVZXDQZrrk:
23798 case VPMOVZXDQZrrkz:
23799 case VPMOVZXDQrm:
23800 case VPMOVZXDQrr:
23801 return true;
23802 }
23803 return false;
23804}
23805
23806bool isVRCP14PS(unsigned Opcode) {
23807 switch (Opcode) {
23808 case VRCP14PSZ128m:
23809 case VRCP14PSZ128mb:
23810 case VRCP14PSZ128mbk:
23811 case VRCP14PSZ128mbkz:
23812 case VRCP14PSZ128mk:
23813 case VRCP14PSZ128mkz:
23814 case VRCP14PSZ128r:
23815 case VRCP14PSZ128rk:
23816 case VRCP14PSZ128rkz:
23817 case VRCP14PSZ256m:
23818 case VRCP14PSZ256mb:
23819 case VRCP14PSZ256mbk:
23820 case VRCP14PSZ256mbkz:
23821 case VRCP14PSZ256mk:
23822 case VRCP14PSZ256mkz:
23823 case VRCP14PSZ256r:
23824 case VRCP14PSZ256rk:
23825 case VRCP14PSZ256rkz:
23826 case VRCP14PSZm:
23827 case VRCP14PSZmb:
23828 case VRCP14PSZmbk:
23829 case VRCP14PSZmbkz:
23830 case VRCP14PSZmk:
23831 case VRCP14PSZmkz:
23832 case VRCP14PSZr:
23833 case VRCP14PSZrk:
23834 case VRCP14PSZrkz:
23835 return true;
23836 }
23837 return false;
23838}
23839
23840bool isVSQRTSH(unsigned Opcode) {
23841 switch (Opcode) {
23842 case VSQRTSHZm_Int:
23843 case VSQRTSHZmk_Int:
23844 case VSQRTSHZmkz_Int:
23845 case VSQRTSHZr_Int:
23846 case VSQRTSHZrb_Int:
23847 case VSQRTSHZrbk_Int:
23848 case VSQRTSHZrbkz_Int:
23849 case VSQRTSHZrk_Int:
23850 case VSQRTSHZrkz_Int:
23851 return true;
23852 }
23853 return false;
23854}
23855
23856bool isTCVTROWD2PS(unsigned Opcode) {
23857 switch (Opcode) {
23858 case TCVTROWD2PSrte:
23859 case TCVTROWD2PSrti:
23860 return true;
23861 }
23862 return false;
23863}
23864
23865bool isLOOP(unsigned Opcode) {
23866 return Opcode == LOOP;
23867}
23868
23869bool isSTUI(unsigned Opcode) {
23870 return Opcode == STUI;
23871}
23872
23873bool isVCVTTPS2UDQ(unsigned Opcode) {
23874 switch (Opcode) {
23875 case VCVTTPS2UDQZ128rm:
23876 case VCVTTPS2UDQZ128rmb:
23877 case VCVTTPS2UDQZ128rmbk:
23878 case VCVTTPS2UDQZ128rmbkz:
23879 case VCVTTPS2UDQZ128rmk:
23880 case VCVTTPS2UDQZ128rmkz:
23881 case VCVTTPS2UDQZ128rr:
23882 case VCVTTPS2UDQZ128rrk:
23883 case VCVTTPS2UDQZ128rrkz:
23884 case VCVTTPS2UDQZ256rm:
23885 case VCVTTPS2UDQZ256rmb:
23886 case VCVTTPS2UDQZ256rmbk:
23887 case VCVTTPS2UDQZ256rmbkz:
23888 case VCVTTPS2UDQZ256rmk:
23889 case VCVTTPS2UDQZ256rmkz:
23890 case VCVTTPS2UDQZ256rr:
23891 case VCVTTPS2UDQZ256rrk:
23892 case VCVTTPS2UDQZ256rrkz:
23893 case VCVTTPS2UDQZrm:
23894 case VCVTTPS2UDQZrmb:
23895 case VCVTTPS2UDQZrmbk:
23896 case VCVTTPS2UDQZrmbkz:
23897 case VCVTTPS2UDQZrmk:
23898 case VCVTTPS2UDQZrmkz:
23899 case VCVTTPS2UDQZrr:
23900 case VCVTTPS2UDQZrrb:
23901 case VCVTTPS2UDQZrrbk:
23902 case VCVTTPS2UDQZrrbkz:
23903 case VCVTTPS2UDQZrrk:
23904 case VCVTTPS2UDQZrrkz:
23905 return true;
23906 }
23907 return false;
23908}
23909
23910bool isXABORT(unsigned Opcode) {
23911 return Opcode == XABORT;
23912}
23913
23914bool isVCOMPRESSPS(unsigned Opcode) {
23915 switch (Opcode) {
23916 case VCOMPRESSPSZ128mr:
23917 case VCOMPRESSPSZ128mrk:
23918 case VCOMPRESSPSZ128rr:
23919 case VCOMPRESSPSZ128rrk:
23920 case VCOMPRESSPSZ128rrkz:
23921 case VCOMPRESSPSZ256mr:
23922 case VCOMPRESSPSZ256mrk:
23923 case VCOMPRESSPSZ256rr:
23924 case VCOMPRESSPSZ256rrk:
23925 case VCOMPRESSPSZ256rrkz:
23926 case VCOMPRESSPSZmr:
23927 case VCOMPRESSPSZmrk:
23928 case VCOMPRESSPSZrr:
23929 case VCOMPRESSPSZrrk:
23930 case VCOMPRESSPSZrrkz:
23931 return true;
23932 }
23933 return false;
23934}
23935
23936bool isVCVTPS2BF8S(unsigned Opcode) {
23937 switch (Opcode) {
23938 case VCVTPS2BF8SZ128rm:
23939 case VCVTPS2BF8SZ128rmb:
23940 case VCVTPS2BF8SZ128rmbk:
23941 case VCVTPS2BF8SZ128rmbkz:
23942 case VCVTPS2BF8SZ128rmk:
23943 case VCVTPS2BF8SZ128rmkz:
23944 case VCVTPS2BF8SZ128rr:
23945 case VCVTPS2BF8SZ128rrk:
23946 case VCVTPS2BF8SZ128rrkz:
23947 case VCVTPS2BF8SZ256rm:
23948 case VCVTPS2BF8SZ256rmb:
23949 case VCVTPS2BF8SZ256rmbk:
23950 case VCVTPS2BF8SZ256rmbkz:
23951 case VCVTPS2BF8SZ256rmk:
23952 case VCVTPS2BF8SZ256rmkz:
23953 case VCVTPS2BF8SZ256rr:
23954 case VCVTPS2BF8SZ256rrk:
23955 case VCVTPS2BF8SZ256rrkz:
23956 case VCVTPS2BF8SZrm:
23957 case VCVTPS2BF8SZrmb:
23958 case VCVTPS2BF8SZrmbk:
23959 case VCVTPS2BF8SZrmbkz:
23960 case VCVTPS2BF8SZrmk:
23961 case VCVTPS2BF8SZrmkz:
23962 case VCVTPS2BF8SZrr:
23963 case VCVTPS2BF8SZrrk:
23964 case VCVTPS2BF8SZrrkz:
23965 return true;
23966 }
23967 return false;
23968}
23969
23970bool isVCVTTBF162IUBS(unsigned Opcode) {
23971 switch (Opcode) {
23972 case VCVTTBF162IUBSZ128rm:
23973 case VCVTTBF162IUBSZ128rmb:
23974 case VCVTTBF162IUBSZ128rmbk:
23975 case VCVTTBF162IUBSZ128rmbkz:
23976 case VCVTTBF162IUBSZ128rmk:
23977 case VCVTTBF162IUBSZ128rmkz:
23978 case VCVTTBF162IUBSZ128rr:
23979 case VCVTTBF162IUBSZ128rrk:
23980 case VCVTTBF162IUBSZ128rrkz:
23981 case VCVTTBF162IUBSZ256rm:
23982 case VCVTTBF162IUBSZ256rmb:
23983 case VCVTTBF162IUBSZ256rmbk:
23984 case VCVTTBF162IUBSZ256rmbkz:
23985 case VCVTTBF162IUBSZ256rmk:
23986 case VCVTTBF162IUBSZ256rmkz:
23987 case VCVTTBF162IUBSZ256rr:
23988 case VCVTTBF162IUBSZ256rrk:
23989 case VCVTTBF162IUBSZ256rrkz:
23990 case VCVTTBF162IUBSZrm:
23991 case VCVTTBF162IUBSZrmb:
23992 case VCVTTBF162IUBSZrmbk:
23993 case VCVTTBF162IUBSZrmbkz:
23994 case VCVTTBF162IUBSZrmk:
23995 case VCVTTBF162IUBSZrmkz:
23996 case VCVTTBF162IUBSZrr:
23997 case VCVTTBF162IUBSZrrk:
23998 case VCVTTBF162IUBSZrrkz:
23999 return true;
24000 }
24001 return false;
24002}
24003
24004bool isVPADDW(unsigned Opcode) {
24005 switch (Opcode) {
24006 case VPADDWYrm:
24007 case VPADDWYrr:
24008 case VPADDWZ128rm:
24009 case VPADDWZ128rmk:
24010 case VPADDWZ128rmkz:
24011 case VPADDWZ128rr:
24012 case VPADDWZ128rrk:
24013 case VPADDWZ128rrkz:
24014 case VPADDWZ256rm:
24015 case VPADDWZ256rmk:
24016 case VPADDWZ256rmkz:
24017 case VPADDWZ256rr:
24018 case VPADDWZ256rrk:
24019 case VPADDWZ256rrkz:
24020 case VPADDWZrm:
24021 case VPADDWZrmk:
24022 case VPADDWZrmkz:
24023 case VPADDWZrr:
24024 case VPADDWZrrk:
24025 case VPADDWZrrkz:
24026 case VPADDWrm:
24027 case VPADDWrr:
24028 return true;
24029 }
24030 return false;
24031}
24032
24033bool isVPSIGND(unsigned Opcode) {
24034 switch (Opcode) {
24035 case VPSIGNDYrm:
24036 case VPSIGNDYrr:
24037 case VPSIGNDrm:
24038 case VPSIGNDrr:
24039 return true;
24040 }
24041 return false;
24042}
24043
24044bool isVRNDSCALEPS(unsigned Opcode) {
24045 switch (Opcode) {
24046 case VRNDSCALEPSZ128rmbi:
24047 case VRNDSCALEPSZ128rmbik:
24048 case VRNDSCALEPSZ128rmbikz:
24049 case VRNDSCALEPSZ128rmi:
24050 case VRNDSCALEPSZ128rmik:
24051 case VRNDSCALEPSZ128rmikz:
24052 case VRNDSCALEPSZ128rri:
24053 case VRNDSCALEPSZ128rrik:
24054 case VRNDSCALEPSZ128rrikz:
24055 case VRNDSCALEPSZ256rmbi:
24056 case VRNDSCALEPSZ256rmbik:
24057 case VRNDSCALEPSZ256rmbikz:
24058 case VRNDSCALEPSZ256rmi:
24059 case VRNDSCALEPSZ256rmik:
24060 case VRNDSCALEPSZ256rmikz:
24061 case VRNDSCALEPSZ256rri:
24062 case VRNDSCALEPSZ256rrik:
24063 case VRNDSCALEPSZ256rrikz:
24064 case VRNDSCALEPSZrmbi:
24065 case VRNDSCALEPSZrmbik:
24066 case VRNDSCALEPSZrmbikz:
24067 case VRNDSCALEPSZrmi:
24068 case VRNDSCALEPSZrmik:
24069 case VRNDSCALEPSZrmikz:
24070 case VRNDSCALEPSZrri:
24071 case VRNDSCALEPSZrrib:
24072 case VRNDSCALEPSZrribk:
24073 case VRNDSCALEPSZrribkz:
24074 case VRNDSCALEPSZrrik:
24075 case VRNDSCALEPSZrrikz:
24076 return true;
24077 }
24078 return false;
24079}
24080
24081bool isVPHADDUWD(unsigned Opcode) {
24082 switch (Opcode) {
24083 case VPHADDUWDrm:
24084 case VPHADDUWDrr:
24085 return true;
24086 }
24087 return false;
24088}
24089
24090bool isVCVT2PH2HF8S(unsigned Opcode) {
24091 switch (Opcode) {
24092 case VCVT2PH2HF8SZ128rm:
24093 case VCVT2PH2HF8SZ128rmb:
24094 case VCVT2PH2HF8SZ128rmbk:
24095 case VCVT2PH2HF8SZ128rmbkz:
24096 case VCVT2PH2HF8SZ128rmk:
24097 case VCVT2PH2HF8SZ128rmkz:
24098 case VCVT2PH2HF8SZ128rr:
24099 case VCVT2PH2HF8SZ128rrk:
24100 case VCVT2PH2HF8SZ128rrkz:
24101 case VCVT2PH2HF8SZ256rm:
24102 case VCVT2PH2HF8SZ256rmb:
24103 case VCVT2PH2HF8SZ256rmbk:
24104 case VCVT2PH2HF8SZ256rmbkz:
24105 case VCVT2PH2HF8SZ256rmk:
24106 case VCVT2PH2HF8SZ256rmkz:
24107 case VCVT2PH2HF8SZ256rr:
24108 case VCVT2PH2HF8SZ256rrk:
24109 case VCVT2PH2HF8SZ256rrkz:
24110 case VCVT2PH2HF8SZrm:
24111 case VCVT2PH2HF8SZrmb:
24112 case VCVT2PH2HF8SZrmbk:
24113 case VCVT2PH2HF8SZrmbkz:
24114 case VCVT2PH2HF8SZrmk:
24115 case VCVT2PH2HF8SZrmkz:
24116 case VCVT2PH2HF8SZrr:
24117 case VCVT2PH2HF8SZrrk:
24118 case VCVT2PH2HF8SZrrkz:
24119 return true;
24120 }
24121 return false;
24122}
24123
24124bool isVDBPSADBW(unsigned Opcode) {
24125 switch (Opcode) {
24126 case VDBPSADBWZ128rmi:
24127 case VDBPSADBWZ128rmik:
24128 case VDBPSADBWZ128rmikz:
24129 case VDBPSADBWZ128rri:
24130 case VDBPSADBWZ128rrik:
24131 case VDBPSADBWZ128rrikz:
24132 case VDBPSADBWZ256rmi:
24133 case VDBPSADBWZ256rmik:
24134 case VDBPSADBWZ256rmikz:
24135 case VDBPSADBWZ256rri:
24136 case VDBPSADBWZ256rrik:
24137 case VDBPSADBWZ256rrikz:
24138 case VDBPSADBWZrmi:
24139 case VDBPSADBWZrmik:
24140 case VDBPSADBWZrmikz:
24141 case VDBPSADBWZrri:
24142 case VDBPSADBWZrrik:
24143 case VDBPSADBWZrrikz:
24144 return true;
24145 }
24146 return false;
24147}
24148
24149bool isPSLLW(unsigned Opcode) {
24150 switch (Opcode) {
24151 case MMX_PSLLWri:
24152 case MMX_PSLLWrm:
24153 case MMX_PSLLWrr:
24154 case PSLLWri:
24155 case PSLLWrm:
24156 case PSLLWrr:
24157 return true;
24158 }
24159 return false;
24160}
24161
24162bool isVPMOVQD(unsigned Opcode) {
24163 switch (Opcode) {
24164 case VPMOVQDZ128mr:
24165 case VPMOVQDZ128mrk:
24166 case VPMOVQDZ128rr:
24167 case VPMOVQDZ128rrk:
24168 case VPMOVQDZ128rrkz:
24169 case VPMOVQDZ256mr:
24170 case VPMOVQDZ256mrk:
24171 case VPMOVQDZ256rr:
24172 case VPMOVQDZ256rrk:
24173 case VPMOVQDZ256rrkz:
24174 case VPMOVQDZmr:
24175 case VPMOVQDZmrk:
24176 case VPMOVQDZrr:
24177 case VPMOVQDZrrk:
24178 case VPMOVQDZrrkz:
24179 return true;
24180 }
24181 return false;
24182}
24183
24184bool isVINSERTI64X4(unsigned Opcode) {
24185 switch (Opcode) {
24186 case VINSERTI64X4Zrmi:
24187 case VINSERTI64X4Zrmik:
24188 case VINSERTI64X4Zrmikz:
24189 case VINSERTI64X4Zrri:
24190 case VINSERTI64X4Zrrik:
24191 case VINSERTI64X4Zrrikz:
24192 return true;
24193 }
24194 return false;
24195}
24196
24197bool isVPERMI2PS(unsigned Opcode) {
24198 switch (Opcode) {
24199 case VPERMI2PSZ128rm:
24200 case VPERMI2PSZ128rmb:
24201 case VPERMI2PSZ128rmbk:
24202 case VPERMI2PSZ128rmbkz:
24203 case VPERMI2PSZ128rmk:
24204 case VPERMI2PSZ128rmkz:
24205 case VPERMI2PSZ128rr:
24206 case VPERMI2PSZ128rrk:
24207 case VPERMI2PSZ128rrkz:
24208 case VPERMI2PSZ256rm:
24209 case VPERMI2PSZ256rmb:
24210 case VPERMI2PSZ256rmbk:
24211 case VPERMI2PSZ256rmbkz:
24212 case VPERMI2PSZ256rmk:
24213 case VPERMI2PSZ256rmkz:
24214 case VPERMI2PSZ256rr:
24215 case VPERMI2PSZ256rrk:
24216 case VPERMI2PSZ256rrkz:
24217 case VPERMI2PSZrm:
24218 case VPERMI2PSZrmb:
24219 case VPERMI2PSZrmbk:
24220 case VPERMI2PSZrmbkz:
24221 case VPERMI2PSZrmk:
24222 case VPERMI2PSZrmkz:
24223 case VPERMI2PSZrr:
24224 case VPERMI2PSZrrk:
24225 case VPERMI2PSZrrkz:
24226 return true;
24227 }
24228 return false;
24229}
24230
24231bool isVMULPH(unsigned Opcode) {
24232 switch (Opcode) {
24233 case VMULPHZ128rm:
24234 case VMULPHZ128rmb:
24235 case VMULPHZ128rmbk:
24236 case VMULPHZ128rmbkz:
24237 case VMULPHZ128rmk:
24238 case VMULPHZ128rmkz:
24239 case VMULPHZ128rr:
24240 case VMULPHZ128rrk:
24241 case VMULPHZ128rrkz:
24242 case VMULPHZ256rm:
24243 case VMULPHZ256rmb:
24244 case VMULPHZ256rmbk:
24245 case VMULPHZ256rmbkz:
24246 case VMULPHZ256rmk:
24247 case VMULPHZ256rmkz:
24248 case VMULPHZ256rr:
24249 case VMULPHZ256rrk:
24250 case VMULPHZ256rrkz:
24251 case VMULPHZrm:
24252 case VMULPHZrmb:
24253 case VMULPHZrmbk:
24254 case VMULPHZrmbkz:
24255 case VMULPHZrmk:
24256 case VMULPHZrmkz:
24257 case VMULPHZrr:
24258 case VMULPHZrrb:
24259 case VMULPHZrrbk:
24260 case VMULPHZrrbkz:
24261 case VMULPHZrrk:
24262 case VMULPHZrrkz:
24263 return true;
24264 }
24265 return false;
24266}
24267
24268bool isVPCMPUQ(unsigned Opcode) {
24269 switch (Opcode) {
24270 case VPCMPUQZ128rmbi:
24271 case VPCMPUQZ128rmbik:
24272 case VPCMPUQZ128rmi:
24273 case VPCMPUQZ128rmik:
24274 case VPCMPUQZ128rri:
24275 case VPCMPUQZ128rrik:
24276 case VPCMPUQZ256rmbi:
24277 case VPCMPUQZ256rmbik:
24278 case VPCMPUQZ256rmi:
24279 case VPCMPUQZ256rmik:
24280 case VPCMPUQZ256rri:
24281 case VPCMPUQZ256rrik:
24282 case VPCMPUQZrmbi:
24283 case VPCMPUQZrmbik:
24284 case VPCMPUQZrmi:
24285 case VPCMPUQZrmik:
24286 case VPCMPUQZrri:
24287 case VPCMPUQZrrik:
24288 return true;
24289 }
24290 return false;
24291}
24292
24293bool isVCVTUSI2SD(unsigned Opcode) {
24294 switch (Opcode) {
24295 case VCVTUSI2SDZrm_Int:
24296 case VCVTUSI2SDZrr_Int:
24297 case VCVTUSI642SDZrm_Int:
24298 case VCVTUSI642SDZrr_Int:
24299 case VCVTUSI642SDZrrb_Int:
24300 return true;
24301 }
24302 return false;
24303}
24304
24305bool isKXNORW(unsigned Opcode) {
24306 return Opcode == KXNORWkk;
24307}
24308
24309bool isBLCIC(unsigned Opcode) {
24310 switch (Opcode) {
24311 case BLCIC32rm:
24312 case BLCIC32rr:
24313 case BLCIC64rm:
24314 case BLCIC64rr:
24315 return true;
24316 }
24317 return false;
24318}
24319
24320bool isVFNMADD213SD(unsigned Opcode) {
24321 switch (Opcode) {
24322 case VFNMADD213SDZm_Int:
24323 case VFNMADD213SDZmk_Int:
24324 case VFNMADD213SDZmkz_Int:
24325 case VFNMADD213SDZr_Int:
24326 case VFNMADD213SDZrb_Int:
24327 case VFNMADD213SDZrbk_Int:
24328 case VFNMADD213SDZrbkz_Int:
24329 case VFNMADD213SDZrk_Int:
24330 case VFNMADD213SDZrkz_Int:
24331 case VFNMADD213SDm_Int:
24332 case VFNMADD213SDr_Int:
24333 return true;
24334 }
24335 return false;
24336}
24337
24338bool isVMOVLPS(unsigned Opcode) {
24339 switch (Opcode) {
24340 case VMOVLPSZ128mr:
24341 case VMOVLPSZ128rm:
24342 case VMOVLPSmr:
24343 case VMOVLPSrm:
24344 return true;
24345 }
24346 return false;
24347}
24348
24349bool isVPMACSWW(unsigned Opcode) {
24350 switch (Opcode) {
24351 case VPMACSWWrm:
24352 case VPMACSWWrr:
24353 return true;
24354 }
24355 return false;
24356}
24357
24358bool isPCONFIG(unsigned Opcode) {
24359 return Opcode == PCONFIG;
24360}
24361
24362bool isPANDN(unsigned Opcode) {
24363 switch (Opcode) {
24364 case MMX_PANDNrm:
24365 case MMX_PANDNrr:
24366 case PANDNrm:
24367 case PANDNrr:
24368 return true;
24369 }
24370 return false;
24371}
24372
24373bool isVCVTPS2BF8(unsigned Opcode) {
24374 switch (Opcode) {
24375 case VCVTPS2BF8Z128rm:
24376 case VCVTPS2BF8Z128rmb:
24377 case VCVTPS2BF8Z128rmbk:
24378 case VCVTPS2BF8Z128rmbkz:
24379 case VCVTPS2BF8Z128rmk:
24380 case VCVTPS2BF8Z128rmkz:
24381 case VCVTPS2BF8Z128rr:
24382 case VCVTPS2BF8Z128rrk:
24383 case VCVTPS2BF8Z128rrkz:
24384 case VCVTPS2BF8Z256rm:
24385 case VCVTPS2BF8Z256rmb:
24386 case VCVTPS2BF8Z256rmbk:
24387 case VCVTPS2BF8Z256rmbkz:
24388 case VCVTPS2BF8Z256rmk:
24389 case VCVTPS2BF8Z256rmkz:
24390 case VCVTPS2BF8Z256rr:
24391 case VCVTPS2BF8Z256rrk:
24392 case VCVTPS2BF8Z256rrkz:
24393 case VCVTPS2BF8Zrm:
24394 case VCVTPS2BF8Zrmb:
24395 case VCVTPS2BF8Zrmbk:
24396 case VCVTPS2BF8Zrmbkz:
24397 case VCVTPS2BF8Zrmk:
24398 case VCVTPS2BF8Zrmkz:
24399 case VCVTPS2BF8Zrr:
24400 case VCVTPS2BF8Zrrk:
24401 case VCVTPS2BF8Zrrkz:
24402 return true;
24403 }
24404 return false;
24405}
24406
24407bool isVGETEXPPD(unsigned Opcode) {
24408 switch (Opcode) {
24409 case VGETEXPPDZ128m:
24410 case VGETEXPPDZ128mb:
24411 case VGETEXPPDZ128mbk:
24412 case VGETEXPPDZ128mbkz:
24413 case VGETEXPPDZ128mk:
24414 case VGETEXPPDZ128mkz:
24415 case VGETEXPPDZ128r:
24416 case VGETEXPPDZ128rk:
24417 case VGETEXPPDZ128rkz:
24418 case VGETEXPPDZ256m:
24419 case VGETEXPPDZ256mb:
24420 case VGETEXPPDZ256mbk:
24421 case VGETEXPPDZ256mbkz:
24422 case VGETEXPPDZ256mk:
24423 case VGETEXPPDZ256mkz:
24424 case VGETEXPPDZ256r:
24425 case VGETEXPPDZ256rk:
24426 case VGETEXPPDZ256rkz:
24427 case VGETEXPPDZm:
24428 case VGETEXPPDZmb:
24429 case VGETEXPPDZmbk:
24430 case VGETEXPPDZmbkz:
24431 case VGETEXPPDZmk:
24432 case VGETEXPPDZmkz:
24433 case VGETEXPPDZr:
24434 case VGETEXPPDZrb:
24435 case VGETEXPPDZrbk:
24436 case VGETEXPPDZrbkz:
24437 case VGETEXPPDZrk:
24438 case VGETEXPPDZrkz:
24439 return true;
24440 }
24441 return false;
24442}
24443
24444bool isVPSRLVQ(unsigned Opcode) {
24445 switch (Opcode) {
24446 case VPSRLVQYrm:
24447 case VPSRLVQYrr:
24448 case VPSRLVQZ128rm:
24449 case VPSRLVQZ128rmb:
24450 case VPSRLVQZ128rmbk:
24451 case VPSRLVQZ128rmbkz:
24452 case VPSRLVQZ128rmk:
24453 case VPSRLVQZ128rmkz:
24454 case VPSRLVQZ128rr:
24455 case VPSRLVQZ128rrk:
24456 case VPSRLVQZ128rrkz:
24457 case VPSRLVQZ256rm:
24458 case VPSRLVQZ256rmb:
24459 case VPSRLVQZ256rmbk:
24460 case VPSRLVQZ256rmbkz:
24461 case VPSRLVQZ256rmk:
24462 case VPSRLVQZ256rmkz:
24463 case VPSRLVQZ256rr:
24464 case VPSRLVQZ256rrk:
24465 case VPSRLVQZ256rrkz:
24466 case VPSRLVQZrm:
24467 case VPSRLVQZrmb:
24468 case VPSRLVQZrmbk:
24469 case VPSRLVQZrmbkz:
24470 case VPSRLVQZrmk:
24471 case VPSRLVQZrmkz:
24472 case VPSRLVQZrr:
24473 case VPSRLVQZrrk:
24474 case VPSRLVQZrrkz:
24475 case VPSRLVQrm:
24476 case VPSRLVQrr:
24477 return true;
24478 }
24479 return false;
24480}
24481
24482bool isUD1(unsigned Opcode) {
24483 switch (Opcode) {
24484 case UD1Lm:
24485 case UD1Lr:
24486 case UD1Qm:
24487 case UD1Qr:
24488 case UD1Wm:
24489 case UD1Wr:
24490 return true;
24491 }
24492 return false;
24493}
24494
24495bool isPMAXSB(unsigned Opcode) {
24496 switch (Opcode) {
24497 case PMAXSBrm:
24498 case PMAXSBrr:
24499 return true;
24500 }
24501 return false;
24502}
24503
24504bool isVPROLQ(unsigned Opcode) {
24505 switch (Opcode) {
24506 case VPROLQZ128mbi:
24507 case VPROLQZ128mbik:
24508 case VPROLQZ128mbikz:
24509 case VPROLQZ128mi:
24510 case VPROLQZ128mik:
24511 case VPROLQZ128mikz:
24512 case VPROLQZ128ri:
24513 case VPROLQZ128rik:
24514 case VPROLQZ128rikz:
24515 case VPROLQZ256mbi:
24516 case VPROLQZ256mbik:
24517 case VPROLQZ256mbikz:
24518 case VPROLQZ256mi:
24519 case VPROLQZ256mik:
24520 case VPROLQZ256mikz:
24521 case VPROLQZ256ri:
24522 case VPROLQZ256rik:
24523 case VPROLQZ256rikz:
24524 case VPROLQZmbi:
24525 case VPROLQZmbik:
24526 case VPROLQZmbikz:
24527 case VPROLQZmi:
24528 case VPROLQZmik:
24529 case VPROLQZmikz:
24530 case VPROLQZri:
24531 case VPROLQZrik:
24532 case VPROLQZrikz:
24533 return true;
24534 }
24535 return false;
24536}
24537
24538bool isVPSRLD(unsigned Opcode) {
24539 switch (Opcode) {
24540 case VPSRLDYri:
24541 case VPSRLDYrm:
24542 case VPSRLDYrr:
24543 case VPSRLDZ128mbi:
24544 case VPSRLDZ128mbik:
24545 case VPSRLDZ128mbikz:
24546 case VPSRLDZ128mi:
24547 case VPSRLDZ128mik:
24548 case VPSRLDZ128mikz:
24549 case VPSRLDZ128ri:
24550 case VPSRLDZ128rik:
24551 case VPSRLDZ128rikz:
24552 case VPSRLDZ128rm:
24553 case VPSRLDZ128rmk:
24554 case VPSRLDZ128rmkz:
24555 case VPSRLDZ128rr:
24556 case VPSRLDZ128rrk:
24557 case VPSRLDZ128rrkz:
24558 case VPSRLDZ256mbi:
24559 case VPSRLDZ256mbik:
24560 case VPSRLDZ256mbikz:
24561 case VPSRLDZ256mi:
24562 case VPSRLDZ256mik:
24563 case VPSRLDZ256mikz:
24564 case VPSRLDZ256ri:
24565 case VPSRLDZ256rik:
24566 case VPSRLDZ256rikz:
24567 case VPSRLDZ256rm:
24568 case VPSRLDZ256rmk:
24569 case VPSRLDZ256rmkz:
24570 case VPSRLDZ256rr:
24571 case VPSRLDZ256rrk:
24572 case VPSRLDZ256rrkz:
24573 case VPSRLDZmbi:
24574 case VPSRLDZmbik:
24575 case VPSRLDZmbikz:
24576 case VPSRLDZmi:
24577 case VPSRLDZmik:
24578 case VPSRLDZmikz:
24579 case VPSRLDZri:
24580 case VPSRLDZrik:
24581 case VPSRLDZrikz:
24582 case VPSRLDZrm:
24583 case VPSRLDZrmk:
24584 case VPSRLDZrmkz:
24585 case VPSRLDZrr:
24586 case VPSRLDZrrk:
24587 case VPSRLDZrrkz:
24588 case VPSRLDri:
24589 case VPSRLDrm:
24590 case VPSRLDrr:
24591 return true;
24592 }
24593 return false;
24594}
24595
24596bool isVSCATTERPF1QPD(unsigned Opcode) {
24597 return Opcode == VSCATTERPF1QPDm;
24598}
24599
24600bool isINT3(unsigned Opcode) {
24601 return Opcode == INT3;
24602}
24603
24604bool isXRSTORS64(unsigned Opcode) {
24605 return Opcode == XRSTORS64;
24606}
24607
24608bool isCVTSD2SI(unsigned Opcode) {
24609 switch (Opcode) {
24610 case CVTSD2SI64rm_Int:
24611 case CVTSD2SI64rr_Int:
24612 case CVTSD2SIrm_Int:
24613 case CVTSD2SIrr_Int:
24614 return true;
24615 }
24616 return false;
24617}
24618
24619bool isVMAXSS(unsigned Opcode) {
24620 switch (Opcode) {
24621 case VMAXSSZrm_Int:
24622 case VMAXSSZrmk_Int:
24623 case VMAXSSZrmkz_Int:
24624 case VMAXSSZrr_Int:
24625 case VMAXSSZrrb_Int:
24626 case VMAXSSZrrbk_Int:
24627 case VMAXSSZrrbkz_Int:
24628 case VMAXSSZrrk_Int:
24629 case VMAXSSZrrkz_Int:
24630 case VMAXSSrm_Int:
24631 case VMAXSSrr_Int:
24632 return true;
24633 }
24634 return false;
24635}
24636
24637bool isVPMINUB(unsigned Opcode) {
24638 switch (Opcode) {
24639 case VPMINUBYrm:
24640 case VPMINUBYrr:
24641 case VPMINUBZ128rm:
24642 case VPMINUBZ128rmk:
24643 case VPMINUBZ128rmkz:
24644 case VPMINUBZ128rr:
24645 case VPMINUBZ128rrk:
24646 case VPMINUBZ128rrkz:
24647 case VPMINUBZ256rm:
24648 case VPMINUBZ256rmk:
24649 case VPMINUBZ256rmkz:
24650 case VPMINUBZ256rr:
24651 case VPMINUBZ256rrk:
24652 case VPMINUBZ256rrkz:
24653 case VPMINUBZrm:
24654 case VPMINUBZrmk:
24655 case VPMINUBZrmkz:
24656 case VPMINUBZrr:
24657 case VPMINUBZrrk:
24658 case VPMINUBZrrkz:
24659 case VPMINUBrm:
24660 case VPMINUBrr:
24661 return true;
24662 }
24663 return false;
24664}
24665
24666bool isKXNORQ(unsigned Opcode) {
24667 return Opcode == KXNORQkk;
24668}
24669
24670bool isFLD(unsigned Opcode) {
24671 switch (Opcode) {
24672 case LD_F32m:
24673 case LD_F64m:
24674 case LD_F80m:
24675 case LD_Frr:
24676 return true;
24677 }
24678 return false;
24679}
24680
24681bool isVSHUFI32X4(unsigned Opcode) {
24682 switch (Opcode) {
24683 case VSHUFI32X4Z256rmbi:
24684 case VSHUFI32X4Z256rmbik:
24685 case VSHUFI32X4Z256rmbikz:
24686 case VSHUFI32X4Z256rmi:
24687 case VSHUFI32X4Z256rmik:
24688 case VSHUFI32X4Z256rmikz:
24689 case VSHUFI32X4Z256rri:
24690 case VSHUFI32X4Z256rrik:
24691 case VSHUFI32X4Z256rrikz:
24692 case VSHUFI32X4Zrmbi:
24693 case VSHUFI32X4Zrmbik:
24694 case VSHUFI32X4Zrmbikz:
24695 case VSHUFI32X4Zrmi:
24696 case VSHUFI32X4Zrmik:
24697 case VSHUFI32X4Zrmikz:
24698 case VSHUFI32X4Zrri:
24699 case VSHUFI32X4Zrrik:
24700 case VSHUFI32X4Zrrikz:
24701 return true;
24702 }
24703 return false;
24704}
24705
24706bool isSAHF(unsigned Opcode) {
24707 return Opcode == SAHF;
24708}
24709
24710bool isPFRSQRT(unsigned Opcode) {
24711 switch (Opcode) {
24712 case PFRSQRTrm:
24713 case PFRSQRTrr:
24714 return true;
24715 }
24716 return false;
24717}
24718
24719bool isSHRD(unsigned Opcode) {
24720 switch (Opcode) {
24721 case SHRD16mrCL:
24722 case SHRD16mrCL_EVEX:
24723 case SHRD16mrCL_ND:
24724 case SHRD16mrCL_NF:
24725 case SHRD16mrCL_NF_ND:
24726 case SHRD16mri8:
24727 case SHRD16mri8_EVEX:
24728 case SHRD16mri8_ND:
24729 case SHRD16mri8_NF:
24730 case SHRD16mri8_NF_ND:
24731 case SHRD16rrCL:
24732 case SHRD16rrCL_EVEX:
24733 case SHRD16rrCL_ND:
24734 case SHRD16rrCL_NF:
24735 case SHRD16rrCL_NF_ND:
24736 case SHRD16rri8:
24737 case SHRD16rri8_EVEX:
24738 case SHRD16rri8_ND:
24739 case SHRD16rri8_NF:
24740 case SHRD16rri8_NF_ND:
24741 case SHRD32mrCL:
24742 case SHRD32mrCL_EVEX:
24743 case SHRD32mrCL_ND:
24744 case SHRD32mrCL_NF:
24745 case SHRD32mrCL_NF_ND:
24746 case SHRD32mri8:
24747 case SHRD32mri8_EVEX:
24748 case SHRD32mri8_ND:
24749 case SHRD32mri8_NF:
24750 case SHRD32mri8_NF_ND:
24751 case SHRD32rrCL:
24752 case SHRD32rrCL_EVEX:
24753 case SHRD32rrCL_ND:
24754 case SHRD32rrCL_NF:
24755 case SHRD32rrCL_NF_ND:
24756 case SHRD32rri8:
24757 case SHRD32rri8_EVEX:
24758 case SHRD32rri8_ND:
24759 case SHRD32rri8_NF:
24760 case SHRD32rri8_NF_ND:
24761 case SHRD64mrCL:
24762 case SHRD64mrCL_EVEX:
24763 case SHRD64mrCL_ND:
24764 case SHRD64mrCL_NF:
24765 case SHRD64mrCL_NF_ND:
24766 case SHRD64mri8:
24767 case SHRD64mri8_EVEX:
24768 case SHRD64mri8_ND:
24769 case SHRD64mri8_NF:
24770 case SHRD64mri8_NF_ND:
24771 case SHRD64rrCL:
24772 case SHRD64rrCL_EVEX:
24773 case SHRD64rrCL_ND:
24774 case SHRD64rrCL_NF:
24775 case SHRD64rrCL_NF_ND:
24776 case SHRD64rri8:
24777 case SHRD64rri8_EVEX:
24778 case SHRD64rri8_ND:
24779 case SHRD64rri8_NF:
24780 case SHRD64rri8_NF_ND:
24781 return true;
24782 }
24783 return false;
24784}
24785
24786bool isSYSEXIT(unsigned Opcode) {
24787 return Opcode == SYSEXIT;
24788}
24789
24790bool isXSAVE64(unsigned Opcode) {
24791 return Opcode == XSAVE64;
24792}
24793
24794bool isVPMAXSD(unsigned Opcode) {
24795 switch (Opcode) {
24796 case VPMAXSDYrm:
24797 case VPMAXSDYrr:
24798 case VPMAXSDZ128rm:
24799 case VPMAXSDZ128rmb:
24800 case VPMAXSDZ128rmbk:
24801 case VPMAXSDZ128rmbkz:
24802 case VPMAXSDZ128rmk:
24803 case VPMAXSDZ128rmkz:
24804 case VPMAXSDZ128rr:
24805 case VPMAXSDZ128rrk:
24806 case VPMAXSDZ128rrkz:
24807 case VPMAXSDZ256rm:
24808 case VPMAXSDZ256rmb:
24809 case VPMAXSDZ256rmbk:
24810 case VPMAXSDZ256rmbkz:
24811 case VPMAXSDZ256rmk:
24812 case VPMAXSDZ256rmkz:
24813 case VPMAXSDZ256rr:
24814 case VPMAXSDZ256rrk:
24815 case VPMAXSDZ256rrkz:
24816 case VPMAXSDZrm:
24817 case VPMAXSDZrmb:
24818 case VPMAXSDZrmbk:
24819 case VPMAXSDZrmbkz:
24820 case VPMAXSDZrmk:
24821 case VPMAXSDZrmkz:
24822 case VPMAXSDZrr:
24823 case VPMAXSDZrrk:
24824 case VPMAXSDZrrkz:
24825 case VPMAXSDrm:
24826 case VPMAXSDrr:
24827 return true;
24828 }
24829 return false;
24830}
24831
24832bool isCVTTSD2SI(unsigned Opcode) {
24833 switch (Opcode) {
24834 case CVTTSD2SI64rm_Int:
24835 case CVTTSD2SI64rr_Int:
24836 case CVTTSD2SIrm_Int:
24837 case CVTTSD2SIrr_Int:
24838 return true;
24839 }
24840 return false;
24841}
24842
24843bool isVCVTTSS2SIS(unsigned Opcode) {
24844 switch (Opcode) {
24845 case VCVTTSS2SI64Srm_Int:
24846 case VCVTTSS2SI64Srr_Int:
24847 case VCVTTSS2SI64Srrb_Int:
24848 case VCVTTSS2SISrm_Int:
24849 case VCVTTSS2SISrr_Int:
24850 case VCVTTSS2SISrrb_Int:
24851 return true;
24852 }
24853 return false;
24854}
24855
24856bool isPMOVMSKB(unsigned Opcode) {
24857 switch (Opcode) {
24858 case MMX_PMOVMSKBrr:
24859 case PMOVMSKBrr:
24860 return true;
24861 }
24862 return false;
24863}
24864
24865bool isVPMOVSSDB(unsigned Opcode) {
24866 switch (Opcode) {
24867 case VPMOVSSDBZ128mr:
24868 case VPMOVSSDBZ128mrk:
24869 case VPMOVSSDBZ128rr:
24870 case VPMOVSSDBZ128rrk:
24871 case VPMOVSSDBZ128rrkz:
24872 case VPMOVSSDBZ256mr:
24873 case VPMOVSSDBZ256mrk:
24874 case VPMOVSSDBZ256rr:
24875 case VPMOVSSDBZ256rrk:
24876 case VPMOVSSDBZ256rrkz:
24877 case VPMOVSSDBZmr:
24878 case VPMOVSSDBZmrk:
24879 case VPMOVSSDBZrr:
24880 case VPMOVSSDBZrrk:
24881 case VPMOVSSDBZrrkz:
24882 return true;
24883 }
24884 return false;
24885}
24886
24887bool isVRANGEPS(unsigned Opcode) {
24888 switch (Opcode) {
24889 case VRANGEPSZ128rmbi:
24890 case VRANGEPSZ128rmbik:
24891 case VRANGEPSZ128rmbikz:
24892 case VRANGEPSZ128rmi:
24893 case VRANGEPSZ128rmik:
24894 case VRANGEPSZ128rmikz:
24895 case VRANGEPSZ128rri:
24896 case VRANGEPSZ128rrik:
24897 case VRANGEPSZ128rrikz:
24898 case VRANGEPSZ256rmbi:
24899 case VRANGEPSZ256rmbik:
24900 case VRANGEPSZ256rmbikz:
24901 case VRANGEPSZ256rmi:
24902 case VRANGEPSZ256rmik:
24903 case VRANGEPSZ256rmikz:
24904 case VRANGEPSZ256rri:
24905 case VRANGEPSZ256rrik:
24906 case VRANGEPSZ256rrikz:
24907 case VRANGEPSZrmbi:
24908 case VRANGEPSZrmbik:
24909 case VRANGEPSZrmbikz:
24910 case VRANGEPSZrmi:
24911 case VRANGEPSZrmik:
24912 case VRANGEPSZrmikz:
24913 case VRANGEPSZrri:
24914 case VRANGEPSZrrib:
24915 case VRANGEPSZrribk:
24916 case VRANGEPSZrribkz:
24917 case VRANGEPSZrrik:
24918 case VRANGEPSZrrikz:
24919 return true;
24920 }
24921 return false;
24922}
24923
24924bool isVADDSUBPS(unsigned Opcode) {
24925 switch (Opcode) {
24926 case VADDSUBPSYrm:
24927 case VADDSUBPSYrr:
24928 case VADDSUBPSrm:
24929 case VADDSUBPSrr:
24930 return true;
24931 }
24932 return false;
24933}
24934
24935bool isVBROADCASTI128(unsigned Opcode) {
24936 return Opcode == VBROADCASTI128rm;
24937}
24938
24939bool isPADDUSB(unsigned Opcode) {
24940 switch (Opcode) {
24941 case MMX_PADDUSBrm:
24942 case MMX_PADDUSBrr:
24943 case PADDUSBrm:
24944 case PADDUSBrr:
24945 return true;
24946 }
24947 return false;
24948}
24949
24950bool isENCODEKEY128(unsigned Opcode) {
24951 return Opcode == ENCODEKEY128;
24952}
24953
24954bool isOR(unsigned Opcode) {
24955 switch (Opcode) {
24956 case OR16i16:
24957 case OR16mi:
24958 case OR16mi8:
24959 case OR16mi8_EVEX:
24960 case OR16mi8_ND:
24961 case OR16mi8_NF:
24962 case OR16mi8_NF_ND:
24963 case OR16mi_EVEX:
24964 case OR16mi_ND:
24965 case OR16mi_NF:
24966 case OR16mi_NF_ND:
24967 case OR16mr:
24968 case OR16mr_EVEX:
24969 case OR16mr_ND:
24970 case OR16mr_NF:
24971 case OR16mr_NF_ND:
24972 case OR16ri:
24973 case OR16ri8:
24974 case OR16ri8_EVEX:
24975 case OR16ri8_ND:
24976 case OR16ri8_NF:
24977 case OR16ri8_NF_ND:
24978 case OR16ri_EVEX:
24979 case OR16ri_ND:
24980 case OR16ri_NF:
24981 case OR16ri_NF_ND:
24982 case OR16rm:
24983 case OR16rm_EVEX:
24984 case OR16rm_ND:
24985 case OR16rm_NF:
24986 case OR16rm_NF_ND:
24987 case OR16rr:
24988 case OR16rr_EVEX:
24989 case OR16rr_EVEX_REV:
24990 case OR16rr_ND:
24991 case OR16rr_ND_REV:
24992 case OR16rr_NF:
24993 case OR16rr_NF_ND:
24994 case OR16rr_NF_ND_REV:
24995 case OR16rr_NF_REV:
24996 case OR16rr_REV:
24997 case OR32i32:
24998 case OR32mi:
24999 case OR32mi8:
25000 case OR32mi8_EVEX:
25001 case OR32mi8_ND:
25002 case OR32mi8_NF:
25003 case OR32mi8_NF_ND:
25004 case OR32mi_EVEX:
25005 case OR32mi_ND:
25006 case OR32mi_NF:
25007 case OR32mi_NF_ND:
25008 case OR32mr:
25009 case OR32mr_EVEX:
25010 case OR32mr_ND:
25011 case OR32mr_NF:
25012 case OR32mr_NF_ND:
25013 case OR32ri:
25014 case OR32ri8:
25015 case OR32ri8_EVEX:
25016 case OR32ri8_ND:
25017 case OR32ri8_NF:
25018 case OR32ri8_NF_ND:
25019 case OR32ri_EVEX:
25020 case OR32ri_ND:
25021 case OR32ri_NF:
25022 case OR32ri_NF_ND:
25023 case OR32rm:
25024 case OR32rm_EVEX:
25025 case OR32rm_ND:
25026 case OR32rm_NF:
25027 case OR32rm_NF_ND:
25028 case OR32rr:
25029 case OR32rr_EVEX:
25030 case OR32rr_EVEX_REV:
25031 case OR32rr_ND:
25032 case OR32rr_ND_REV:
25033 case OR32rr_NF:
25034 case OR32rr_NF_ND:
25035 case OR32rr_NF_ND_REV:
25036 case OR32rr_NF_REV:
25037 case OR32rr_REV:
25038 case OR64i32:
25039 case OR64mi32:
25040 case OR64mi32_EVEX:
25041 case OR64mi32_ND:
25042 case OR64mi32_NF:
25043 case OR64mi32_NF_ND:
25044 case OR64mi8:
25045 case OR64mi8_EVEX:
25046 case OR64mi8_ND:
25047 case OR64mi8_NF:
25048 case OR64mi8_NF_ND:
25049 case OR64mr:
25050 case OR64mr_EVEX:
25051 case OR64mr_ND:
25052 case OR64mr_NF:
25053 case OR64mr_NF_ND:
25054 case OR64ri32:
25055 case OR64ri32_EVEX:
25056 case OR64ri32_ND:
25057 case OR64ri32_NF:
25058 case OR64ri32_NF_ND:
25059 case OR64ri8:
25060 case OR64ri8_EVEX:
25061 case OR64ri8_ND:
25062 case OR64ri8_NF:
25063 case OR64ri8_NF_ND:
25064 case OR64rm:
25065 case OR64rm_EVEX:
25066 case OR64rm_ND:
25067 case OR64rm_NF:
25068 case OR64rm_NF_ND:
25069 case OR64rr:
25070 case OR64rr_EVEX:
25071 case OR64rr_EVEX_REV:
25072 case OR64rr_ND:
25073 case OR64rr_ND_REV:
25074 case OR64rr_NF:
25075 case OR64rr_NF_ND:
25076 case OR64rr_NF_ND_REV:
25077 case OR64rr_NF_REV:
25078 case OR64rr_REV:
25079 case OR8i8:
25080 case OR8mi:
25081 case OR8mi8:
25082 case OR8mi_EVEX:
25083 case OR8mi_ND:
25084 case OR8mi_NF:
25085 case OR8mi_NF_ND:
25086 case OR8mr:
25087 case OR8mr_EVEX:
25088 case OR8mr_ND:
25089 case OR8mr_NF:
25090 case OR8mr_NF_ND:
25091 case OR8ri:
25092 case OR8ri8:
25093 case OR8ri_EVEX:
25094 case OR8ri_ND:
25095 case OR8ri_NF:
25096 case OR8ri_NF_ND:
25097 case OR8rm:
25098 case OR8rm_EVEX:
25099 case OR8rm_ND:
25100 case OR8rm_NF:
25101 case OR8rm_NF_ND:
25102 case OR8rr:
25103 case OR8rr_EVEX:
25104 case OR8rr_EVEX_REV:
25105 case OR8rr_ND:
25106 case OR8rr_ND_REV:
25107 case OR8rr_NF:
25108 case OR8rr_NF_ND:
25109 case OR8rr_NF_ND_REV:
25110 case OR8rr_NF_REV:
25111 case OR8rr_REV:
25112 return true;
25113 }
25114 return false;
25115}
25116
25117bool isSTOSW(unsigned Opcode) {
25118 return Opcode == STOSW;
25119}
25120
25121bool isVCVTTPD2UQQS(unsigned Opcode) {
25122 switch (Opcode) {
25123 case VCVTTPD2UQQSZ128rm:
25124 case VCVTTPD2UQQSZ128rmb:
25125 case VCVTTPD2UQQSZ128rmbk:
25126 case VCVTTPD2UQQSZ128rmbkz:
25127 case VCVTTPD2UQQSZ128rmk:
25128 case VCVTTPD2UQQSZ128rmkz:
25129 case VCVTTPD2UQQSZ128rr:
25130 case VCVTTPD2UQQSZ128rrk:
25131 case VCVTTPD2UQQSZ128rrkz:
25132 case VCVTTPD2UQQSZ256rm:
25133 case VCVTTPD2UQQSZ256rmb:
25134 case VCVTTPD2UQQSZ256rmbk:
25135 case VCVTTPD2UQQSZ256rmbkz:
25136 case VCVTTPD2UQQSZ256rmk:
25137 case VCVTTPD2UQQSZ256rmkz:
25138 case VCVTTPD2UQQSZ256rr:
25139 case VCVTTPD2UQQSZ256rrb:
25140 case VCVTTPD2UQQSZ256rrbk:
25141 case VCVTTPD2UQQSZ256rrbkz:
25142 case VCVTTPD2UQQSZ256rrk:
25143 case VCVTTPD2UQQSZ256rrkz:
25144 case VCVTTPD2UQQSZrm:
25145 case VCVTTPD2UQQSZrmb:
25146 case VCVTTPD2UQQSZrmbk:
25147 case VCVTTPD2UQQSZrmbkz:
25148 case VCVTTPD2UQQSZrmk:
25149 case VCVTTPD2UQQSZrmkz:
25150 case VCVTTPD2UQQSZrr:
25151 case VCVTTPD2UQQSZrrb:
25152 case VCVTTPD2UQQSZrrbk:
25153 case VCVTTPD2UQQSZrrbkz:
25154 case VCVTTPD2UQQSZrrk:
25155 case VCVTTPD2UQQSZrrkz:
25156 return true;
25157 }
25158 return false;
25159}
25160
25161bool isPAVGW(unsigned Opcode) {
25162 switch (Opcode) {
25163 case MMX_PAVGWrm:
25164 case MMX_PAVGWrr:
25165 case PAVGWrm:
25166 case PAVGWrr:
25167 return true;
25168 }
25169 return false;
25170}
25171
25172bool isVCVTPD2PH(unsigned Opcode) {
25173 switch (Opcode) {
25174 case VCVTPD2PHZ128rm:
25175 case VCVTPD2PHZ128rmb:
25176 case VCVTPD2PHZ128rmbk:
25177 case VCVTPD2PHZ128rmbkz:
25178 case VCVTPD2PHZ128rmk:
25179 case VCVTPD2PHZ128rmkz:
25180 case VCVTPD2PHZ128rr:
25181 case VCVTPD2PHZ128rrk:
25182 case VCVTPD2PHZ128rrkz:
25183 case VCVTPD2PHZ256rm:
25184 case VCVTPD2PHZ256rmb:
25185 case VCVTPD2PHZ256rmbk:
25186 case VCVTPD2PHZ256rmbkz:
25187 case VCVTPD2PHZ256rmk:
25188 case VCVTPD2PHZ256rmkz:
25189 case VCVTPD2PHZ256rr:
25190 case VCVTPD2PHZ256rrk:
25191 case VCVTPD2PHZ256rrkz:
25192 case VCVTPD2PHZrm:
25193 case VCVTPD2PHZrmb:
25194 case VCVTPD2PHZrmbk:
25195 case VCVTPD2PHZrmbkz:
25196 case VCVTPD2PHZrmk:
25197 case VCVTPD2PHZrmkz:
25198 case VCVTPD2PHZrr:
25199 case VCVTPD2PHZrrb:
25200 case VCVTPD2PHZrrbk:
25201 case VCVTPD2PHZrrbkz:
25202 case VCVTPD2PHZrrk:
25203 case VCVTPD2PHZrrkz:
25204 return true;
25205 }
25206 return false;
25207}
25208
25209bool isSHLX(unsigned Opcode) {
25210 switch (Opcode) {
25211 case SHLX32rm:
25212 case SHLX32rm_EVEX:
25213 case SHLX32rr:
25214 case SHLX32rr_EVEX:
25215 case SHLX64rm:
25216 case SHLX64rm_EVEX:
25217 case SHLX64rr:
25218 case SHLX64rr_EVEX:
25219 return true;
25220 }
25221 return false;
25222}
25223
25224bool isVCVTSH2SD(unsigned Opcode) {
25225 switch (Opcode) {
25226 case VCVTSH2SDZrm_Int:
25227 case VCVTSH2SDZrmk_Int:
25228 case VCVTSH2SDZrmkz_Int:
25229 case VCVTSH2SDZrr_Int:
25230 case VCVTSH2SDZrrb_Int:
25231 case VCVTSH2SDZrrbk_Int:
25232 case VCVTSH2SDZrrbkz_Int:
25233 case VCVTSH2SDZrrk_Int:
25234 case VCVTSH2SDZrrkz_Int:
25235 return true;
25236 }
25237 return false;
25238}
25239
25240bool isVFMADD231SS(unsigned Opcode) {
25241 switch (Opcode) {
25242 case VFMADD231SSZm_Int:
25243 case VFMADD231SSZmk_Int:
25244 case VFMADD231SSZmkz_Int:
25245 case VFMADD231SSZr_Int:
25246 case VFMADD231SSZrb_Int:
25247 case VFMADD231SSZrbk_Int:
25248 case VFMADD231SSZrbkz_Int:
25249 case VFMADD231SSZrk_Int:
25250 case VFMADD231SSZrkz_Int:
25251 case VFMADD231SSm_Int:
25252 case VFMADD231SSr_Int:
25253 return true;
25254 }
25255 return false;
25256}
25257
25258bool isMOVNTSD(unsigned Opcode) {
25259 return Opcode == MOVNTSD;
25260}
25261
25262bool isFLDPI(unsigned Opcode) {
25263 return Opcode == FLDPI;
25264}
25265
25266bool isVCVTUSI2SS(unsigned Opcode) {
25267 switch (Opcode) {
25268 case VCVTUSI2SSZrm_Int:
25269 case VCVTUSI2SSZrr_Int:
25270 case VCVTUSI2SSZrrb_Int:
25271 case VCVTUSI642SSZrm_Int:
25272 case VCVTUSI642SSZrr_Int:
25273 case VCVTUSI642SSZrrb_Int:
25274 return true;
25275 }
25276 return false;
25277}
25278
25279bool isPMOVSXBD(unsigned Opcode) {
25280 switch (Opcode) {
25281 case PMOVSXBDrm:
25282 case PMOVSXBDrr:
25283 return true;
25284 }
25285 return false;
25286}
25287
25288bool isVPRORVQ(unsigned Opcode) {
25289 switch (Opcode) {
25290 case VPRORVQZ128rm:
25291 case VPRORVQZ128rmb:
25292 case VPRORVQZ128rmbk:
25293 case VPRORVQZ128rmbkz:
25294 case VPRORVQZ128rmk:
25295 case VPRORVQZ128rmkz:
25296 case VPRORVQZ128rr:
25297 case VPRORVQZ128rrk:
25298 case VPRORVQZ128rrkz:
25299 case VPRORVQZ256rm:
25300 case VPRORVQZ256rmb:
25301 case VPRORVQZ256rmbk:
25302 case VPRORVQZ256rmbkz:
25303 case VPRORVQZ256rmk:
25304 case VPRORVQZ256rmkz:
25305 case VPRORVQZ256rr:
25306 case VPRORVQZ256rrk:
25307 case VPRORVQZ256rrkz:
25308 case VPRORVQZrm:
25309 case VPRORVQZrmb:
25310 case VPRORVQZrmbk:
25311 case VPRORVQZrmbkz:
25312 case VPRORVQZrmk:
25313 case VPRORVQZrmkz:
25314 case VPRORVQZrr:
25315 case VPRORVQZrrk:
25316 case VPRORVQZrrkz:
25317 return true;
25318 }
25319 return false;
25320}
25321
25322bool isVPERMT2D(unsigned Opcode) {
25323 switch (Opcode) {
25324 case VPERMT2DZ128rm:
25325 case VPERMT2DZ128rmb:
25326 case VPERMT2DZ128rmbk:
25327 case VPERMT2DZ128rmbkz:
25328 case VPERMT2DZ128rmk:
25329 case VPERMT2DZ128rmkz:
25330 case VPERMT2DZ128rr:
25331 case VPERMT2DZ128rrk:
25332 case VPERMT2DZ128rrkz:
25333 case VPERMT2DZ256rm:
25334 case VPERMT2DZ256rmb:
25335 case VPERMT2DZ256rmbk:
25336 case VPERMT2DZ256rmbkz:
25337 case VPERMT2DZ256rmk:
25338 case VPERMT2DZ256rmkz:
25339 case VPERMT2DZ256rr:
25340 case VPERMT2DZ256rrk:
25341 case VPERMT2DZ256rrkz:
25342 case VPERMT2DZrm:
25343 case VPERMT2DZrmb:
25344 case VPERMT2DZrmbk:
25345 case VPERMT2DZrmbkz:
25346 case VPERMT2DZrmk:
25347 case VPERMT2DZrmkz:
25348 case VPERMT2DZrr:
25349 case VPERMT2DZrrk:
25350 case VPERMT2DZrrkz:
25351 return true;
25352 }
25353 return false;
25354}
25355
25356bool isADDSS(unsigned Opcode) {
25357 switch (Opcode) {
25358 case ADDSSrm_Int:
25359 case ADDSSrr_Int:
25360 return true;
25361 }
25362 return false;
25363}
25364
25365bool isAADD(unsigned Opcode) {
25366 switch (Opcode) {
25367 case AADD32mr:
25368 case AADD32mr_EVEX:
25369 case AADD64mr:
25370 case AADD64mr_EVEX:
25371 return true;
25372 }
25373 return false;
25374}
25375
25376bool isVPSRLVW(unsigned Opcode) {
25377 switch (Opcode) {
25378 case VPSRLVWZ128rm:
25379 case VPSRLVWZ128rmk:
25380 case VPSRLVWZ128rmkz:
25381 case VPSRLVWZ128rr:
25382 case VPSRLVWZ128rrk:
25383 case VPSRLVWZ128rrkz:
25384 case VPSRLVWZ256rm:
25385 case VPSRLVWZ256rmk:
25386 case VPSRLVWZ256rmkz:
25387 case VPSRLVWZ256rr:
25388 case VPSRLVWZ256rrk:
25389 case VPSRLVWZ256rrkz:
25390 case VPSRLVWZrm:
25391 case VPSRLVWZrmk:
25392 case VPSRLVWZrmkz:
25393 case VPSRLVWZrr:
25394 case VPSRLVWZrrk:
25395 case VPSRLVWZrrkz:
25396 return true;
25397 }
25398 return false;
25399}
25400
25401bool isVRSQRTPH(unsigned Opcode) {
25402 switch (Opcode) {
25403 case VRSQRTPHZ128m:
25404 case VRSQRTPHZ128mb:
25405 case VRSQRTPHZ128mbk:
25406 case VRSQRTPHZ128mbkz:
25407 case VRSQRTPHZ128mk:
25408 case VRSQRTPHZ128mkz:
25409 case VRSQRTPHZ128r:
25410 case VRSQRTPHZ128rk:
25411 case VRSQRTPHZ128rkz:
25412 case VRSQRTPHZ256m:
25413 case VRSQRTPHZ256mb:
25414 case VRSQRTPHZ256mbk:
25415 case VRSQRTPHZ256mbkz:
25416 case VRSQRTPHZ256mk:
25417 case VRSQRTPHZ256mkz:
25418 case VRSQRTPHZ256r:
25419 case VRSQRTPHZ256rk:
25420 case VRSQRTPHZ256rkz:
25421 case VRSQRTPHZm:
25422 case VRSQRTPHZmb:
25423 case VRSQRTPHZmbk:
25424 case VRSQRTPHZmbkz:
25425 case VRSQRTPHZmk:
25426 case VRSQRTPHZmkz:
25427 case VRSQRTPHZr:
25428 case VRSQRTPHZrk:
25429 case VRSQRTPHZrkz:
25430 return true;
25431 }
25432 return false;
25433}
25434
25435bool isVLDDQU(unsigned Opcode) {
25436 switch (Opcode) {
25437 case VLDDQUYrm:
25438 case VLDDQUrm:
25439 return true;
25440 }
25441 return false;
25442}
25443
25444bool isKMOVD(unsigned Opcode) {
25445 switch (Opcode) {
25446 case KMOVDkk:
25447 case KMOVDkk_EVEX:
25448 case KMOVDkm:
25449 case KMOVDkm_EVEX:
25450 case KMOVDkr:
25451 case KMOVDkr_EVEX:
25452 case KMOVDmk:
25453 case KMOVDmk_EVEX:
25454 case KMOVDrk:
25455 case KMOVDrk_EVEX:
25456 return true;
25457 }
25458 return false;
25459}
25460
25461bool isENCLV(unsigned Opcode) {
25462 return Opcode == ENCLV;
25463}
25464
25465bool isENCLU(unsigned Opcode) {
25466 return Opcode == ENCLU;
25467}
25468
25469bool isPREFETCHT1(unsigned Opcode) {
25470 return Opcode == PREFETCHT1;
25471}
25472
25473bool isRSQRTPS(unsigned Opcode) {
25474 switch (Opcode) {
25475 case RSQRTPSm:
25476 case RSQRTPSr:
25477 return true;
25478 }
25479 return false;
25480}
25481
25482bool isVCVTTSH2USI(unsigned Opcode) {
25483 switch (Opcode) {
25484 case VCVTTSH2USI64Zrm_Int:
25485 case VCVTTSH2USI64Zrr_Int:
25486 case VCVTTSH2USI64Zrrb_Int:
25487 case VCVTTSH2USIZrm_Int:
25488 case VCVTTSH2USIZrr_Int:
25489 case VCVTTSH2USIZrrb_Int:
25490 return true;
25491 }
25492 return false;
25493}
25494
25495bool isPADDB(unsigned Opcode) {
25496 switch (Opcode) {
25497 case MMX_PADDBrm:
25498 case MMX_PADDBrr:
25499 case PADDBrm:
25500 case PADDBrr:
25501 return true;
25502 }
25503 return false;
25504}
25505
25506bool isVMASKMOVDQU(unsigned Opcode) {
25507 return Opcode == VMASKMOVDQU64;
25508}
25509
25510bool isPUNPCKLBW(unsigned Opcode) {
25511 switch (Opcode) {
25512 case MMX_PUNPCKLBWrm:
25513 case MMX_PUNPCKLBWrr:
25514 case PUNPCKLBWrm:
25515 case PUNPCKLBWrr:
25516 return true;
25517 }
25518 return false;
25519}
25520
25521bool isMOV(unsigned Opcode) {
25522 switch (Opcode) {
25523 case MOV16ao16:
25524 case MOV16ao32:
25525 case MOV16mi:
25526 case MOV16mr:
25527 case MOV16ms:
25528 case MOV16o16a:
25529 case MOV16o32a:
25530 case MOV16ri:
25531 case MOV16ri_alt:
25532 case MOV16rm:
25533 case MOV16rr:
25534 case MOV16rr_REV:
25535 case MOV16rs:
25536 case MOV16sm:
25537 case MOV16sr:
25538 case MOV32ao16:
25539 case MOV32ao32:
25540 case MOV32cr:
25541 case MOV32dr:
25542 case MOV32mi:
25543 case MOV32mr:
25544 case MOV32o16a:
25545 case MOV32o32a:
25546 case MOV32rc:
25547 case MOV32rd:
25548 case MOV32ri:
25549 case MOV32ri_alt:
25550 case MOV32rm:
25551 case MOV32rr:
25552 case MOV32rr_REV:
25553 case MOV32rs:
25554 case MOV32sr:
25555 case MOV64ao32:
25556 case MOV64cr:
25557 case MOV64dr:
25558 case MOV64mi32:
25559 case MOV64mr:
25560 case MOV64o32a:
25561 case MOV64rc:
25562 case MOV64rd:
25563 case MOV64ri32:
25564 case MOV64rm:
25565 case MOV64rr:
25566 case MOV64rr_REV:
25567 case MOV64rs:
25568 case MOV64sr:
25569 case MOV8ao16:
25570 case MOV8ao32:
25571 case MOV8mi:
25572 case MOV8mr:
25573 case MOV8o16a:
25574 case MOV8o32a:
25575 case MOV8ri:
25576 case MOV8ri_alt:
25577 case MOV8rm:
25578 case MOV8rr:
25579 case MOV8rr_REV:
25580 return true;
25581 }
25582 return false;
25583}
25584
25585bool isVCVTTPH2IUBS(unsigned Opcode) {
25586 switch (Opcode) {
25587 case VCVTTPH2IUBSZ128rm:
25588 case VCVTTPH2IUBSZ128rmb:
25589 case VCVTTPH2IUBSZ128rmbk:
25590 case VCVTTPH2IUBSZ128rmbkz:
25591 case VCVTTPH2IUBSZ128rmk:
25592 case VCVTTPH2IUBSZ128rmkz:
25593 case VCVTTPH2IUBSZ128rr:
25594 case VCVTTPH2IUBSZ128rrk:
25595 case VCVTTPH2IUBSZ128rrkz:
25596 case VCVTTPH2IUBSZ256rm:
25597 case VCVTTPH2IUBSZ256rmb:
25598 case VCVTTPH2IUBSZ256rmbk:
25599 case VCVTTPH2IUBSZ256rmbkz:
25600 case VCVTTPH2IUBSZ256rmk:
25601 case VCVTTPH2IUBSZ256rmkz:
25602 case VCVTTPH2IUBSZ256rr:
25603 case VCVTTPH2IUBSZ256rrk:
25604 case VCVTTPH2IUBSZ256rrkz:
25605 case VCVTTPH2IUBSZrm:
25606 case VCVTTPH2IUBSZrmb:
25607 case VCVTTPH2IUBSZrmbk:
25608 case VCVTTPH2IUBSZrmbkz:
25609 case VCVTTPH2IUBSZrmk:
25610 case VCVTTPH2IUBSZrmkz:
25611 case VCVTTPH2IUBSZrr:
25612 case VCVTTPH2IUBSZrrb:
25613 case VCVTTPH2IUBSZrrbk:
25614 case VCVTTPH2IUBSZrrbkz:
25615 case VCVTTPH2IUBSZrrk:
25616 case VCVTTPH2IUBSZrrkz:
25617 return true;
25618 }
25619 return false;
25620}
25621
25622bool isMUL(unsigned Opcode) {
25623 switch (Opcode) {
25624 case MUL16m:
25625 case MUL16m_EVEX:
25626 case MUL16m_NF:
25627 case MUL16r:
25628 case MUL16r_EVEX:
25629 case MUL16r_NF:
25630 case MUL32m:
25631 case MUL32m_EVEX:
25632 case MUL32m_NF:
25633 case MUL32r:
25634 case MUL32r_EVEX:
25635 case MUL32r_NF:
25636 case MUL64m:
25637 case MUL64m_EVEX:
25638 case MUL64m_NF:
25639 case MUL64r:
25640 case MUL64r_EVEX:
25641 case MUL64r_NF:
25642 case MUL8m:
25643 case MUL8m_EVEX:
25644 case MUL8m_NF:
25645 case MUL8r:
25646 case MUL8r_EVEX:
25647 case MUL8r_NF:
25648 return true;
25649 }
25650 return false;
25651}
25652
25653bool isRCL(unsigned Opcode) {
25654 switch (Opcode) {
25655 case RCL16m1:
25656 case RCL16m1_EVEX:
25657 case RCL16m1_ND:
25658 case RCL16mCL:
25659 case RCL16mCL_EVEX:
25660 case RCL16mCL_ND:
25661 case RCL16mi:
25662 case RCL16mi_EVEX:
25663 case RCL16mi_ND:
25664 case RCL16r1:
25665 case RCL16r1_EVEX:
25666 case RCL16r1_ND:
25667 case RCL16rCL:
25668 case RCL16rCL_EVEX:
25669 case RCL16rCL_ND:
25670 case RCL16ri:
25671 case RCL16ri_EVEX:
25672 case RCL16ri_ND:
25673 case RCL32m1:
25674 case RCL32m1_EVEX:
25675 case RCL32m1_ND:
25676 case RCL32mCL:
25677 case RCL32mCL_EVEX:
25678 case RCL32mCL_ND:
25679 case RCL32mi:
25680 case RCL32mi_EVEX:
25681 case RCL32mi_ND:
25682 case RCL32r1:
25683 case RCL32r1_EVEX:
25684 case RCL32r1_ND:
25685 case RCL32rCL:
25686 case RCL32rCL_EVEX:
25687 case RCL32rCL_ND:
25688 case RCL32ri:
25689 case RCL32ri_EVEX:
25690 case RCL32ri_ND:
25691 case RCL64m1:
25692 case RCL64m1_EVEX:
25693 case RCL64m1_ND:
25694 case RCL64mCL:
25695 case RCL64mCL_EVEX:
25696 case RCL64mCL_ND:
25697 case RCL64mi:
25698 case RCL64mi_EVEX:
25699 case RCL64mi_ND:
25700 case RCL64r1:
25701 case RCL64r1_EVEX:
25702 case RCL64r1_ND:
25703 case RCL64rCL:
25704 case RCL64rCL_EVEX:
25705 case RCL64rCL_ND:
25706 case RCL64ri:
25707 case RCL64ri_EVEX:
25708 case RCL64ri_ND:
25709 case RCL8m1:
25710 case RCL8m1_EVEX:
25711 case RCL8m1_ND:
25712 case RCL8mCL:
25713 case RCL8mCL_EVEX:
25714 case RCL8mCL_ND:
25715 case RCL8mi:
25716 case RCL8mi_EVEX:
25717 case RCL8mi_ND:
25718 case RCL8r1:
25719 case RCL8r1_EVEX:
25720 case RCL8r1_ND:
25721 case RCL8rCL:
25722 case RCL8rCL_EVEX:
25723 case RCL8rCL_ND:
25724 case RCL8ri:
25725 case RCL8ri_EVEX:
25726 case RCL8ri_ND:
25727 return true;
25728 }
25729 return false;
25730}
25731
25732bool isVRCPSH(unsigned Opcode) {
25733 switch (Opcode) {
25734 case VRCPSHZrm:
25735 case VRCPSHZrmk:
25736 case VRCPSHZrmkz:
25737 case VRCPSHZrr:
25738 case VRCPSHZrrk:
25739 case VRCPSHZrrkz:
25740 return true;
25741 }
25742 return false;
25743}
25744
25745bool isPFCMPEQ(unsigned Opcode) {
25746 switch (Opcode) {
25747 case PFCMPEQrm:
25748 case PFCMPEQrr:
25749 return true;
25750 }
25751 return false;
25752}
25753
25754bool isMONITOR(unsigned Opcode) {
25755 switch (Opcode) {
25756 case MONITOR32rrr:
25757 case MONITOR64rrr:
25758 return true;
25759 }
25760 return false;
25761}
25762
25763bool isFDIVR(unsigned Opcode) {
25764 switch (Opcode) {
25765 case DIVR_F32m:
25766 case DIVR_F64m:
25767 case DIVR_FST0r:
25768 case DIVR_FrST0:
25769 return true;
25770 }
25771 return false;
25772}
25773
25774bool isPFRCP(unsigned Opcode) {
25775 switch (Opcode) {
25776 case PFRCPrm:
25777 case PFRCPrr:
25778 return true;
25779 }
25780 return false;
25781}
25782
25783bool isPMINSD(unsigned Opcode) {
25784 switch (Opcode) {
25785 case PMINSDrm:
25786 case PMINSDrr:
25787 return true;
25788 }
25789 return false;
25790}
25791
25792bool isVSHUFF32X4(unsigned Opcode) {
25793 switch (Opcode) {
25794 case VSHUFF32X4Z256rmbi:
25795 case VSHUFF32X4Z256rmbik:
25796 case VSHUFF32X4Z256rmbikz:
25797 case VSHUFF32X4Z256rmi:
25798 case VSHUFF32X4Z256rmik:
25799 case VSHUFF32X4Z256rmikz:
25800 case VSHUFF32X4Z256rri:
25801 case VSHUFF32X4Z256rrik:
25802 case VSHUFF32X4Z256rrikz:
25803 case VSHUFF32X4Zrmbi:
25804 case VSHUFF32X4Zrmbik:
25805 case VSHUFF32X4Zrmbikz:
25806 case VSHUFF32X4Zrmi:
25807 case VSHUFF32X4Zrmik:
25808 case VSHUFF32X4Zrmikz:
25809 case VSHUFF32X4Zrri:
25810 case VSHUFF32X4Zrrik:
25811 case VSHUFF32X4Zrrikz:
25812 return true;
25813 }
25814 return false;
25815}
25816
25817bool isKTESTQ(unsigned Opcode) {
25818 return Opcode == KTESTQkk;
25819}
25820
25821bool isVCVTTPD2DQ(unsigned Opcode) {
25822 switch (Opcode) {
25823 case VCVTTPD2DQYrm:
25824 case VCVTTPD2DQYrr:
25825 case VCVTTPD2DQZ128rm:
25826 case VCVTTPD2DQZ128rmb:
25827 case VCVTTPD2DQZ128rmbk:
25828 case VCVTTPD2DQZ128rmbkz:
25829 case VCVTTPD2DQZ128rmk:
25830 case VCVTTPD2DQZ128rmkz:
25831 case VCVTTPD2DQZ128rr:
25832 case VCVTTPD2DQZ128rrk:
25833 case VCVTTPD2DQZ128rrkz:
25834 case VCVTTPD2DQZ256rm:
25835 case VCVTTPD2DQZ256rmb:
25836 case VCVTTPD2DQZ256rmbk:
25837 case VCVTTPD2DQZ256rmbkz:
25838 case VCVTTPD2DQZ256rmk:
25839 case VCVTTPD2DQZ256rmkz:
25840 case VCVTTPD2DQZ256rr:
25841 case VCVTTPD2DQZ256rrk:
25842 case VCVTTPD2DQZ256rrkz:
25843 case VCVTTPD2DQZrm:
25844 case VCVTTPD2DQZrmb:
25845 case VCVTTPD2DQZrmbk:
25846 case VCVTTPD2DQZrmbkz:
25847 case VCVTTPD2DQZrmk:
25848 case VCVTTPD2DQZrmkz:
25849 case VCVTTPD2DQZrr:
25850 case VCVTTPD2DQZrrb:
25851 case VCVTTPD2DQZrrbk:
25852 case VCVTTPD2DQZrrbkz:
25853 case VCVTTPD2DQZrrk:
25854 case VCVTTPD2DQZrrkz:
25855 case VCVTTPD2DQrm:
25856 case VCVTTPD2DQrr:
25857 return true;
25858 }
25859 return false;
25860}
25861
25862bool isVPSLLVW(unsigned Opcode) {
25863 switch (Opcode) {
25864 case VPSLLVWZ128rm:
25865 case VPSLLVWZ128rmk:
25866 case VPSLLVWZ128rmkz:
25867 case VPSLLVWZ128rr:
25868 case VPSLLVWZ128rrk:
25869 case VPSLLVWZ128rrkz:
25870 case VPSLLVWZ256rm:
25871 case VPSLLVWZ256rmk:
25872 case VPSLLVWZ256rmkz:
25873 case VPSLLVWZ256rr:
25874 case VPSLLVWZ256rrk:
25875 case VPSLLVWZ256rrkz:
25876 case VPSLLVWZrm:
25877 case VPSLLVWZrmk:
25878 case VPSLLVWZrmkz:
25879 case VPSLLVWZrr:
25880 case VPSLLVWZrrk:
25881 case VPSLLVWZrrkz:
25882 return true;
25883 }
25884 return false;
25885}
25886
25887bool isTDPBSUD(unsigned Opcode) {
25888 return Opcode == TDPBSUD;
25889}
25890
25891bool isVPMINUQ(unsigned Opcode) {
25892 switch (Opcode) {
25893 case VPMINUQZ128rm:
25894 case VPMINUQZ128rmb:
25895 case VPMINUQZ128rmbk:
25896 case VPMINUQZ128rmbkz:
25897 case VPMINUQZ128rmk:
25898 case VPMINUQZ128rmkz:
25899 case VPMINUQZ128rr:
25900 case VPMINUQZ128rrk:
25901 case VPMINUQZ128rrkz:
25902 case VPMINUQZ256rm:
25903 case VPMINUQZ256rmb:
25904 case VPMINUQZ256rmbk:
25905 case VPMINUQZ256rmbkz:
25906 case VPMINUQZ256rmk:
25907 case VPMINUQZ256rmkz:
25908 case VPMINUQZ256rr:
25909 case VPMINUQZ256rrk:
25910 case VPMINUQZ256rrkz:
25911 case VPMINUQZrm:
25912 case VPMINUQZrmb:
25913 case VPMINUQZrmbk:
25914 case VPMINUQZrmbkz:
25915 case VPMINUQZrmk:
25916 case VPMINUQZrmkz:
25917 case VPMINUQZrr:
25918 case VPMINUQZrrk:
25919 case VPMINUQZrrkz:
25920 return true;
25921 }
25922 return false;
25923}
25924
25925bool isFIADD(unsigned Opcode) {
25926 switch (Opcode) {
25927 case ADD_FI16m:
25928 case ADD_FI32m:
25929 return true;
25930 }
25931 return false;
25932}
25933
25934bool isFCMOVNU(unsigned Opcode) {
25935 return Opcode == CMOVNP_F;
25936}
25937
25938bool isVHSUBPD(unsigned Opcode) {
25939 switch (Opcode) {
25940 case VHSUBPDYrm:
25941 case VHSUBPDYrr:
25942 case VHSUBPDrm:
25943 case VHSUBPDrr:
25944 return true;
25945 }
25946 return false;
25947}
25948
25949bool isKSHIFTRQ(unsigned Opcode) {
25950 return Opcode == KSHIFTRQki;
25951}
25952
25953bool isMOVUPS(unsigned Opcode) {
25954 switch (Opcode) {
25955 case MOVUPSmr:
25956 case MOVUPSrm:
25957 case MOVUPSrr:
25958 case MOVUPSrr_REV:
25959 return true;
25960 }
25961 return false;
25962}
25963
25964bool isVMCALL(unsigned Opcode) {
25965 return Opcode == VMCALL;
25966}
25967
25968bool isXADD(unsigned Opcode) {
25969 switch (Opcode) {
25970 case XADD16rm:
25971 case XADD16rr:
25972 case XADD32rm:
25973 case XADD32rr:
25974 case XADD64rm:
25975 case XADD64rr:
25976 case XADD8rm:
25977 case XADD8rr:
25978 return true;
25979 }
25980 return false;
25981}
25982
25983bool isXRSTOR(unsigned Opcode) {
25984 return Opcode == XRSTOR;
25985}
25986
25987bool isVGATHERPF1DPD(unsigned Opcode) {
25988 return Opcode == VGATHERPF1DPDm;
25989}
25990
25991bool isRCR(unsigned Opcode) {
25992 switch (Opcode) {
25993 case RCR16m1:
25994 case RCR16m1_EVEX:
25995 case RCR16m1_ND:
25996 case RCR16mCL:
25997 case RCR16mCL_EVEX:
25998 case RCR16mCL_ND:
25999 case RCR16mi:
26000 case RCR16mi_EVEX:
26001 case RCR16mi_ND:
26002 case RCR16r1:
26003 case RCR16r1_EVEX:
26004 case RCR16r1_ND:
26005 case RCR16rCL:
26006 case RCR16rCL_EVEX:
26007 case RCR16rCL_ND:
26008 case RCR16ri:
26009 case RCR16ri_EVEX:
26010 case RCR16ri_ND:
26011 case RCR32m1:
26012 case RCR32m1_EVEX:
26013 case RCR32m1_ND:
26014 case RCR32mCL:
26015 case RCR32mCL_EVEX:
26016 case RCR32mCL_ND:
26017 case RCR32mi:
26018 case RCR32mi_EVEX:
26019 case RCR32mi_ND:
26020 case RCR32r1:
26021 case RCR32r1_EVEX:
26022 case RCR32r1_ND:
26023 case RCR32rCL:
26024 case RCR32rCL_EVEX:
26025 case RCR32rCL_ND:
26026 case RCR32ri:
26027 case RCR32ri_EVEX:
26028 case RCR32ri_ND:
26029 case RCR64m1:
26030 case RCR64m1_EVEX:
26031 case RCR64m1_ND:
26032 case RCR64mCL:
26033 case RCR64mCL_EVEX:
26034 case RCR64mCL_ND:
26035 case RCR64mi:
26036 case RCR64mi_EVEX:
26037 case RCR64mi_ND:
26038 case RCR64r1:
26039 case RCR64r1_EVEX:
26040 case RCR64r1_ND:
26041 case RCR64rCL:
26042 case RCR64rCL_EVEX:
26043 case RCR64rCL_ND:
26044 case RCR64ri:
26045 case RCR64ri_EVEX:
26046 case RCR64ri_ND:
26047 case RCR8m1:
26048 case RCR8m1_EVEX:
26049 case RCR8m1_ND:
26050 case RCR8mCL:
26051 case RCR8mCL_EVEX:
26052 case RCR8mCL_ND:
26053 case RCR8mi:
26054 case RCR8mi_EVEX:
26055 case RCR8mi_ND:
26056 case RCR8r1:
26057 case RCR8r1_EVEX:
26058 case RCR8r1_ND:
26059 case RCR8rCL:
26060 case RCR8rCL_EVEX:
26061 case RCR8rCL_ND:
26062 case RCR8ri:
26063 case RCR8ri_EVEX:
26064 case RCR8ri_ND:
26065 return true;
26066 }
26067 return false;
26068}
26069
26070bool isFNSTCW(unsigned Opcode) {
26071 return Opcode == FNSTCW16m;
26072}
26073
26074bool isVPMOVSDW(unsigned Opcode) {
26075 switch (Opcode) {
26076 case VPMOVSDWZ128mr:
26077 case VPMOVSDWZ128mrk:
26078 case VPMOVSDWZ128rr:
26079 case VPMOVSDWZ128rrk:
26080 case VPMOVSDWZ128rrkz:
26081 case VPMOVSDWZ256mr:
26082 case VPMOVSDWZ256mrk:
26083 case VPMOVSDWZ256rr:
26084 case VPMOVSDWZ256rrk:
26085 case VPMOVSDWZ256rrkz:
26086 case VPMOVSDWZmr:
26087 case VPMOVSDWZmrk:
26088 case VPMOVSDWZrr:
26089 case VPMOVSDWZrrk:
26090 case VPMOVSDWZrrkz:
26091 return true;
26092 }
26093 return false;
26094}
26095
26096bool isVFMSUB132SH(unsigned Opcode) {
26097 switch (Opcode) {
26098 case VFMSUB132SHZm_Int:
26099 case VFMSUB132SHZmk_Int:
26100 case VFMSUB132SHZmkz_Int:
26101 case VFMSUB132SHZr_Int:
26102 case VFMSUB132SHZrb_Int:
26103 case VFMSUB132SHZrbk_Int:
26104 case VFMSUB132SHZrbkz_Int:
26105 case VFMSUB132SHZrk_Int:
26106 case VFMSUB132SHZrkz_Int:
26107 return true;
26108 }
26109 return false;
26110}
26111
26112bool isVPCONFLICTQ(unsigned Opcode) {
26113 switch (Opcode) {
26114 case VPCONFLICTQZ128rm:
26115 case VPCONFLICTQZ128rmb:
26116 case VPCONFLICTQZ128rmbk:
26117 case VPCONFLICTQZ128rmbkz:
26118 case VPCONFLICTQZ128rmk:
26119 case VPCONFLICTQZ128rmkz:
26120 case VPCONFLICTQZ128rr:
26121 case VPCONFLICTQZ128rrk:
26122 case VPCONFLICTQZ128rrkz:
26123 case VPCONFLICTQZ256rm:
26124 case VPCONFLICTQZ256rmb:
26125 case VPCONFLICTQZ256rmbk:
26126 case VPCONFLICTQZ256rmbkz:
26127 case VPCONFLICTQZ256rmk:
26128 case VPCONFLICTQZ256rmkz:
26129 case VPCONFLICTQZ256rr:
26130 case VPCONFLICTQZ256rrk:
26131 case VPCONFLICTQZ256rrkz:
26132 case VPCONFLICTQZrm:
26133 case VPCONFLICTQZrmb:
26134 case VPCONFLICTQZrmbk:
26135 case VPCONFLICTQZrmbkz:
26136 case VPCONFLICTQZrmk:
26137 case VPCONFLICTQZrmkz:
26138 case VPCONFLICTQZrr:
26139 case VPCONFLICTQZrrk:
26140 case VPCONFLICTQZrrkz:
26141 return true;
26142 }
26143 return false;
26144}
26145
26146bool isSWAPGS(unsigned Opcode) {
26147 return Opcode == SWAPGS;
26148}
26149
26150bool isVPMOVQ2M(unsigned Opcode) {
26151 switch (Opcode) {
26152 case VPMOVQ2MZ128kr:
26153 case VPMOVQ2MZ256kr:
26154 case VPMOVQ2MZkr:
26155 return true;
26156 }
26157 return false;
26158}
26159
26160bool isVPSRAVW(unsigned Opcode) {
26161 switch (Opcode) {
26162 case VPSRAVWZ128rm:
26163 case VPSRAVWZ128rmk:
26164 case VPSRAVWZ128rmkz:
26165 case VPSRAVWZ128rr:
26166 case VPSRAVWZ128rrk:
26167 case VPSRAVWZ128rrkz:
26168 case VPSRAVWZ256rm:
26169 case VPSRAVWZ256rmk:
26170 case VPSRAVWZ256rmkz:
26171 case VPSRAVWZ256rr:
26172 case VPSRAVWZ256rrk:
26173 case VPSRAVWZ256rrkz:
26174 case VPSRAVWZrm:
26175 case VPSRAVWZrmk:
26176 case VPSRAVWZrmkz:
26177 case VPSRAVWZrr:
26178 case VPSRAVWZrrk:
26179 case VPSRAVWZrrkz:
26180 return true;
26181 }
26182 return false;
26183}
26184
26185bool isSHA256MSG2(unsigned Opcode) {
26186 switch (Opcode) {
26187 case SHA256MSG2rm:
26188 case SHA256MSG2rr:
26189 return true;
26190 }
26191 return false;
26192}
26193
26194bool isDIVSD(unsigned Opcode) {
26195 switch (Opcode) {
26196 case DIVSDrm_Int:
26197 case DIVSDrr_Int:
26198 return true;
26199 }
26200 return false;
26201}
26202
26203bool isPCMPGTB(unsigned Opcode) {
26204 switch (Opcode) {
26205 case MMX_PCMPGTBrm:
26206 case MMX_PCMPGTBrr:
26207 case PCMPGTBrm:
26208 case PCMPGTBrr:
26209 return true;
26210 }
26211 return false;
26212}
26213
26214bool isMOVDQA(unsigned Opcode) {
26215 switch (Opcode) {
26216 case MOVDQAmr:
26217 case MOVDQArm:
26218 case MOVDQArr:
26219 case MOVDQArr_REV:
26220 return true;
26221 }
26222 return false;
26223}
26224
26225bool isVAESENCLAST(unsigned Opcode) {
26226 switch (Opcode) {
26227 case VAESENCLASTYrm:
26228 case VAESENCLASTYrr:
26229 case VAESENCLASTZ128rm:
26230 case VAESENCLASTZ128rr:
26231 case VAESENCLASTZ256rm:
26232 case VAESENCLASTZ256rr:
26233 case VAESENCLASTZrm:
26234 case VAESENCLASTZrr:
26235 case VAESENCLASTrm:
26236 case VAESENCLASTrr:
26237 return true;
26238 }
26239 return false;
26240}
26241
26242bool isKXORW(unsigned Opcode) {
26243 return Opcode == KXORWkk;
26244}
26245
26246bool isLIDTW(unsigned Opcode) {
26247 return Opcode == LIDT16m;
26248}
26249
26250bool isPMULHW(unsigned Opcode) {
26251 switch (Opcode) {
26252 case MMX_PMULHWrm:
26253 case MMX_PMULHWrr:
26254 case PMULHWrm:
26255 case PMULHWrr:
26256 return true;
26257 }
26258 return false;
26259}
26260
26261bool isVINSERTI32X8(unsigned Opcode) {
26262 switch (Opcode) {
26263 case VINSERTI32X8Zrmi:
26264 case VINSERTI32X8Zrmik:
26265 case VINSERTI32X8Zrmikz:
26266 case VINSERTI32X8Zrri:
26267 case VINSERTI32X8Zrrik:
26268 case VINSERTI32X8Zrrikz:
26269 return true;
26270 }
26271 return false;
26272}
26273
26274bool isVRCPPS(unsigned Opcode) {
26275 switch (Opcode) {
26276 case VRCPPSYm:
26277 case VRCPPSYr:
26278 case VRCPPSm:
26279 case VRCPPSr:
26280 return true;
26281 }
26282 return false;
26283}
26284
26285bool isVRSQRTBF16(unsigned Opcode) {
26286 switch (Opcode) {
26287 case VRSQRTBF16Z128m:
26288 case VRSQRTBF16Z128mb:
26289 case VRSQRTBF16Z128mbk:
26290 case VRSQRTBF16Z128mbkz:
26291 case VRSQRTBF16Z128mk:
26292 case VRSQRTBF16Z128mkz:
26293 case VRSQRTBF16Z128r:
26294 case VRSQRTBF16Z128rk:
26295 case VRSQRTBF16Z128rkz:
26296 case VRSQRTBF16Z256m:
26297 case VRSQRTBF16Z256mb:
26298 case VRSQRTBF16Z256mbk:
26299 case VRSQRTBF16Z256mbkz:
26300 case VRSQRTBF16Z256mk:
26301 case VRSQRTBF16Z256mkz:
26302 case VRSQRTBF16Z256r:
26303 case VRSQRTBF16Z256rk:
26304 case VRSQRTBF16Z256rkz:
26305 case VRSQRTBF16Zm:
26306 case VRSQRTBF16Zmb:
26307 case VRSQRTBF16Zmbk:
26308 case VRSQRTBF16Zmbkz:
26309 case VRSQRTBF16Zmk:
26310 case VRSQRTBF16Zmkz:
26311 case VRSQRTBF16Zr:
26312 case VRSQRTBF16Zrk:
26313 case VRSQRTBF16Zrkz:
26314 return true;
26315 }
26316 return false;
26317}
26318
26319bool isVGATHERQPS(unsigned Opcode) {
26320 switch (Opcode) {
26321 case VGATHERQPSYrm:
26322 case VGATHERQPSZ128rm:
26323 case VGATHERQPSZ256rm:
26324 case VGATHERQPSZrm:
26325 case VGATHERQPSrm:
26326 return true;
26327 }
26328 return false;
26329}
26330
26331bool isCTESTCC(unsigned Opcode) {
26332 switch (Opcode) {
26333 case CTEST16mi:
26334 case CTEST16mr:
26335 case CTEST16ri:
26336 case CTEST16rr:
26337 case CTEST32mi:
26338 case CTEST32mr:
26339 case CTEST32ri:
26340 case CTEST32rr:
26341 case CTEST64mi32:
26342 case CTEST64mr:
26343 case CTEST64ri32:
26344 case CTEST64rr:
26345 case CTEST8mi:
26346 case CTEST8mr:
26347 case CTEST8ri:
26348 case CTEST8rr:
26349 return true;
26350 }
26351 return false;
26352}
26353
26354bool isPMADDWD(unsigned Opcode) {
26355 switch (Opcode) {
26356 case MMX_PMADDWDrm:
26357 case MMX_PMADDWDrr:
26358 case PMADDWDrm:
26359 case PMADDWDrr:
26360 return true;
26361 }
26362 return false;
26363}
26364
26365bool isUCOMISS(unsigned Opcode) {
26366 switch (Opcode) {
26367 case UCOMISSrm:
26368 case UCOMISSrr:
26369 return true;
26370 }
26371 return false;
26372}
26373
26374bool isXGETBV(unsigned Opcode) {
26375 return Opcode == XGETBV;
26376}
26377
26378bool isVCVTPD2QQ(unsigned Opcode) {
26379 switch (Opcode) {
26380 case VCVTPD2QQZ128rm:
26381 case VCVTPD2QQZ128rmb:
26382 case VCVTPD2QQZ128rmbk:
26383 case VCVTPD2QQZ128rmbkz:
26384 case VCVTPD2QQZ128rmk:
26385 case VCVTPD2QQZ128rmkz:
26386 case VCVTPD2QQZ128rr:
26387 case VCVTPD2QQZ128rrk:
26388 case VCVTPD2QQZ128rrkz:
26389 case VCVTPD2QQZ256rm:
26390 case VCVTPD2QQZ256rmb:
26391 case VCVTPD2QQZ256rmbk:
26392 case VCVTPD2QQZ256rmbkz:
26393 case VCVTPD2QQZ256rmk:
26394 case VCVTPD2QQZ256rmkz:
26395 case VCVTPD2QQZ256rr:
26396 case VCVTPD2QQZ256rrk:
26397 case VCVTPD2QQZ256rrkz:
26398 case VCVTPD2QQZrm:
26399 case VCVTPD2QQZrmb:
26400 case VCVTPD2QQZrmbk:
26401 case VCVTPD2QQZrmbkz:
26402 case VCVTPD2QQZrmk:
26403 case VCVTPD2QQZrmkz:
26404 case VCVTPD2QQZrr:
26405 case VCVTPD2QQZrrb:
26406 case VCVTPD2QQZrrbk:
26407 case VCVTPD2QQZrrbkz:
26408 case VCVTPD2QQZrrk:
26409 case VCVTPD2QQZrrkz:
26410 return true;
26411 }
26412 return false;
26413}
26414
26415bool isVGETEXPPS(unsigned Opcode) {
26416 switch (Opcode) {
26417 case VGETEXPPSZ128m:
26418 case VGETEXPPSZ128mb:
26419 case VGETEXPPSZ128mbk:
26420 case VGETEXPPSZ128mbkz:
26421 case VGETEXPPSZ128mk:
26422 case VGETEXPPSZ128mkz:
26423 case VGETEXPPSZ128r:
26424 case VGETEXPPSZ128rk:
26425 case VGETEXPPSZ128rkz:
26426 case VGETEXPPSZ256m:
26427 case VGETEXPPSZ256mb:
26428 case VGETEXPPSZ256mbk:
26429 case VGETEXPPSZ256mbkz:
26430 case VGETEXPPSZ256mk:
26431 case VGETEXPPSZ256mkz:
26432 case VGETEXPPSZ256r:
26433 case VGETEXPPSZ256rk:
26434 case VGETEXPPSZ256rkz:
26435 case VGETEXPPSZm:
26436 case VGETEXPPSZmb:
26437 case VGETEXPPSZmbk:
26438 case VGETEXPPSZmbkz:
26439 case VGETEXPPSZmk:
26440 case VGETEXPPSZmkz:
26441 case VGETEXPPSZr:
26442 case VGETEXPPSZrb:
26443 case VGETEXPPSZrbk:
26444 case VGETEXPPSZrbkz:
26445 case VGETEXPPSZrk:
26446 case VGETEXPPSZrkz:
26447 return true;
26448 }
26449 return false;
26450}
26451
26452bool isFISTP(unsigned Opcode) {
26453 switch (Opcode) {
26454 case IST_FP16m:
26455 case IST_FP32m:
26456 case IST_FP64m:
26457 return true;
26458 }
26459 return false;
26460}
26461
26462bool isVINSERTF64X4(unsigned Opcode) {
26463 switch (Opcode) {
26464 case VINSERTF64X4Zrmi:
26465 case VINSERTF64X4Zrmik:
26466 case VINSERTF64X4Zrmikz:
26467 case VINSERTF64X4Zrri:
26468 case VINSERTF64X4Zrrik:
26469 case VINSERTF64X4Zrrikz:
26470 return true;
26471 }
26472 return false;
26473}
26474
26475bool isVMOVDQU16(unsigned Opcode) {
26476 switch (Opcode) {
26477 case VMOVDQU16Z128mr:
26478 case VMOVDQU16Z128mrk:
26479 case VMOVDQU16Z128rm:
26480 case VMOVDQU16Z128rmk:
26481 case VMOVDQU16Z128rmkz:
26482 case VMOVDQU16Z128rr:
26483 case VMOVDQU16Z128rr_REV:
26484 case VMOVDQU16Z128rrk:
26485 case VMOVDQU16Z128rrk_REV:
26486 case VMOVDQU16Z128rrkz:
26487 case VMOVDQU16Z128rrkz_REV:
26488 case VMOVDQU16Z256mr:
26489 case VMOVDQU16Z256mrk:
26490 case VMOVDQU16Z256rm:
26491 case VMOVDQU16Z256rmk:
26492 case VMOVDQU16Z256rmkz:
26493 case VMOVDQU16Z256rr:
26494 case VMOVDQU16Z256rr_REV:
26495 case VMOVDQU16Z256rrk:
26496 case VMOVDQU16Z256rrk_REV:
26497 case VMOVDQU16Z256rrkz:
26498 case VMOVDQU16Z256rrkz_REV:
26499 case VMOVDQU16Zmr:
26500 case VMOVDQU16Zmrk:
26501 case VMOVDQU16Zrm:
26502 case VMOVDQU16Zrmk:
26503 case VMOVDQU16Zrmkz:
26504 case VMOVDQU16Zrr:
26505 case VMOVDQU16Zrr_REV:
26506 case VMOVDQU16Zrrk:
26507 case VMOVDQU16Zrrk_REV:
26508 case VMOVDQU16Zrrkz:
26509 case VMOVDQU16Zrrkz_REV:
26510 return true;
26511 }
26512 return false;
26513}
26514
26515bool isVCVTBF82BF6S(unsigned Opcode) {
26516 switch (Opcode) {
26517 case VCVTBF82BF6SZ128rr:
26518 case VCVTBF82BF6SZ256rr:
26519 case VCVTBF82BF6SZrr:
26520 return true;
26521 }
26522 return false;
26523}
26524
26525bool isVFMADD132PH(unsigned Opcode) {
26526 switch (Opcode) {
26527 case VFMADD132PHZ128m:
26528 case VFMADD132PHZ128mb:
26529 case VFMADD132PHZ128mbk:
26530 case VFMADD132PHZ128mbkz:
26531 case VFMADD132PHZ128mk:
26532 case VFMADD132PHZ128mkz:
26533 case VFMADD132PHZ128r:
26534 case VFMADD132PHZ128rk:
26535 case VFMADD132PHZ128rkz:
26536 case VFMADD132PHZ256m:
26537 case VFMADD132PHZ256mb:
26538 case VFMADD132PHZ256mbk:
26539 case VFMADD132PHZ256mbkz:
26540 case VFMADD132PHZ256mk:
26541 case VFMADD132PHZ256mkz:
26542 case VFMADD132PHZ256r:
26543 case VFMADD132PHZ256rk:
26544 case VFMADD132PHZ256rkz:
26545 case VFMADD132PHZm:
26546 case VFMADD132PHZmb:
26547 case VFMADD132PHZmbk:
26548 case VFMADD132PHZmbkz:
26549 case VFMADD132PHZmk:
26550 case VFMADD132PHZmkz:
26551 case VFMADD132PHZr:
26552 case VFMADD132PHZrb:
26553 case VFMADD132PHZrbk:
26554 case VFMADD132PHZrbkz:
26555 case VFMADD132PHZrk:
26556 case VFMADD132PHZrkz:
26557 return true;
26558 }
26559 return false;
26560}
26561
26562bool isVFMSUBADD213PS(unsigned Opcode) {
26563 switch (Opcode) {
26564 case VFMSUBADD213PSYm:
26565 case VFMSUBADD213PSYr:
26566 case VFMSUBADD213PSZ128m:
26567 case VFMSUBADD213PSZ128mb:
26568 case VFMSUBADD213PSZ128mbk:
26569 case VFMSUBADD213PSZ128mbkz:
26570 case VFMSUBADD213PSZ128mk:
26571 case VFMSUBADD213PSZ128mkz:
26572 case VFMSUBADD213PSZ128r:
26573 case VFMSUBADD213PSZ128rk:
26574 case VFMSUBADD213PSZ128rkz:
26575 case VFMSUBADD213PSZ256m:
26576 case VFMSUBADD213PSZ256mb:
26577 case VFMSUBADD213PSZ256mbk:
26578 case VFMSUBADD213PSZ256mbkz:
26579 case VFMSUBADD213PSZ256mk:
26580 case VFMSUBADD213PSZ256mkz:
26581 case VFMSUBADD213PSZ256r:
26582 case VFMSUBADD213PSZ256rk:
26583 case VFMSUBADD213PSZ256rkz:
26584 case VFMSUBADD213PSZm:
26585 case VFMSUBADD213PSZmb:
26586 case VFMSUBADD213PSZmbk:
26587 case VFMSUBADD213PSZmbkz:
26588 case VFMSUBADD213PSZmk:
26589 case VFMSUBADD213PSZmkz:
26590 case VFMSUBADD213PSZr:
26591 case VFMSUBADD213PSZrb:
26592 case VFMSUBADD213PSZrbk:
26593 case VFMSUBADD213PSZrbkz:
26594 case VFMSUBADD213PSZrk:
26595 case VFMSUBADD213PSZrkz:
26596 case VFMSUBADD213PSm:
26597 case VFMSUBADD213PSr:
26598 return true;
26599 }
26600 return false;
26601}
26602
26603bool isVMOVDQU32(unsigned Opcode) {
26604 switch (Opcode) {
26605 case VMOVDQU32Z128mr:
26606 case VMOVDQU32Z128mrk:
26607 case VMOVDQU32Z128rm:
26608 case VMOVDQU32Z128rmk:
26609 case VMOVDQU32Z128rmkz:
26610 case VMOVDQU32Z128rr:
26611 case VMOVDQU32Z128rr_REV:
26612 case VMOVDQU32Z128rrk:
26613 case VMOVDQU32Z128rrk_REV:
26614 case VMOVDQU32Z128rrkz:
26615 case VMOVDQU32Z128rrkz_REV:
26616 case VMOVDQU32Z256mr:
26617 case VMOVDQU32Z256mrk:
26618 case VMOVDQU32Z256rm:
26619 case VMOVDQU32Z256rmk:
26620 case VMOVDQU32Z256rmkz:
26621 case VMOVDQU32Z256rr:
26622 case VMOVDQU32Z256rr_REV:
26623 case VMOVDQU32Z256rrk:
26624 case VMOVDQU32Z256rrk_REV:
26625 case VMOVDQU32Z256rrkz:
26626 case VMOVDQU32Z256rrkz_REV:
26627 case VMOVDQU32Zmr:
26628 case VMOVDQU32Zmrk:
26629 case VMOVDQU32Zrm:
26630 case VMOVDQU32Zrmk:
26631 case VMOVDQU32Zrmkz:
26632 case VMOVDQU32Zrr:
26633 case VMOVDQU32Zrr_REV:
26634 case VMOVDQU32Zrrk:
26635 case VMOVDQU32Zrrk_REV:
26636 case VMOVDQU32Zrrkz:
26637 case VMOVDQU32Zrrkz_REV:
26638 return true;
26639 }
26640 return false;
26641}
26642
26643bool isFUCOM(unsigned Opcode) {
26644 return Opcode == UCOM_Fr;
26645}
26646
26647bool isVFNMADD213BF16(unsigned Opcode) {
26648 switch (Opcode) {
26649 case VFNMADD213BF16Z128m:
26650 case VFNMADD213BF16Z128mb:
26651 case VFNMADD213BF16Z128mbk:
26652 case VFNMADD213BF16Z128mbkz:
26653 case VFNMADD213BF16Z128mk:
26654 case VFNMADD213BF16Z128mkz:
26655 case VFNMADD213BF16Z128r:
26656 case VFNMADD213BF16Z128rk:
26657 case VFNMADD213BF16Z128rkz:
26658 case VFNMADD213BF16Z256m:
26659 case VFNMADD213BF16Z256mb:
26660 case VFNMADD213BF16Z256mbk:
26661 case VFNMADD213BF16Z256mbkz:
26662 case VFNMADD213BF16Z256mk:
26663 case VFNMADD213BF16Z256mkz:
26664 case VFNMADD213BF16Z256r:
26665 case VFNMADD213BF16Z256rk:
26666 case VFNMADD213BF16Z256rkz:
26667 case VFNMADD213BF16Zm:
26668 case VFNMADD213BF16Zmb:
26669 case VFNMADD213BF16Zmbk:
26670 case VFNMADD213BF16Zmbkz:
26671 case VFNMADD213BF16Zmk:
26672 case VFNMADD213BF16Zmkz:
26673 case VFNMADD213BF16Zr:
26674 case VFNMADD213BF16Zrk:
26675 case VFNMADD213BF16Zrkz:
26676 return true;
26677 }
26678 return false;
26679}
26680
26681bool isHADDPS(unsigned Opcode) {
26682 switch (Opcode) {
26683 case HADDPSrm:
26684 case HADDPSrr:
26685 return true;
26686 }
26687 return false;
26688}
26689
26690bool isCMP(unsigned Opcode) {
26691 switch (Opcode) {
26692 case CMP16i16:
26693 case CMP16mi:
26694 case CMP16mi8:
26695 case CMP16mr:
26696 case CMP16ri:
26697 case CMP16ri8:
26698 case CMP16rm:
26699 case CMP16rr:
26700 case CMP16rr_REV:
26701 case CMP32i32:
26702 case CMP32mi:
26703 case CMP32mi8:
26704 case CMP32mr:
26705 case CMP32ri:
26706 case CMP32ri8:
26707 case CMP32rm:
26708 case CMP32rr:
26709 case CMP32rr_REV:
26710 case CMP64i32:
26711 case CMP64mi32:
26712 case CMP64mi8:
26713 case CMP64mr:
26714 case CMP64ri32:
26715 case CMP64ri8:
26716 case CMP64rm:
26717 case CMP64rr:
26718 case CMP64rr_REV:
26719 case CMP8i8:
26720 case CMP8mi:
26721 case CMP8mi8:
26722 case CMP8mr:
26723 case CMP8ri:
26724 case CMP8ri8:
26725 case CMP8rm:
26726 case CMP8rr:
26727 case CMP8rr_REV:
26728 return true;
26729 }
26730 return false;
26731}
26732
26733bool isCVTTPS2PI(unsigned Opcode) {
26734 switch (Opcode) {
26735 case MMX_CVTTPS2PIrm:
26736 case MMX_CVTTPS2PIrr:
26737 return true;
26738 }
26739 return false;
26740}
26741
26742bool isIRETQ(unsigned Opcode) {
26743 return Opcode == IRET64;
26744}
26745
26746bool isPF2IW(unsigned Opcode) {
26747 switch (Opcode) {
26748 case PF2IWrm:
26749 case PF2IWrr:
26750 return true;
26751 }
26752 return false;
26753}
26754
26755bool isPSHUFD(unsigned Opcode) {
26756 switch (Opcode) {
26757 case PSHUFDmi:
26758 case PSHUFDri:
26759 return true;
26760 }
26761 return false;
26762}
26763
26764bool isVDPPD(unsigned Opcode) {
26765 switch (Opcode) {
26766 case VDPPDrmi:
26767 case VDPPDrri:
26768 return true;
26769 }
26770 return false;
26771}
26772
26773bool isPSHUFHW(unsigned Opcode) {
26774 switch (Opcode) {
26775 case PSHUFHWmi:
26776 case PSHUFHWri:
26777 return true;
26778 }
26779 return false;
26780}
26781
26782bool isRMPADJUST(unsigned Opcode) {
26783 return Opcode == RMPADJUST;
26784}
26785
26786bool isPI2FW(unsigned Opcode) {
26787 switch (Opcode) {
26788 case PI2FWrm:
26789 case PI2FWrr:
26790 return true;
26791 }
26792 return false;
26793}
26794
26795bool isVCVTTPH2QQ(unsigned Opcode) {
26796 switch (Opcode) {
26797 case VCVTTPH2QQZ128rm:
26798 case VCVTTPH2QQZ128rmb:
26799 case VCVTTPH2QQZ128rmbk:
26800 case VCVTTPH2QQZ128rmbkz:
26801 case VCVTTPH2QQZ128rmk:
26802 case VCVTTPH2QQZ128rmkz:
26803 case VCVTTPH2QQZ128rr:
26804 case VCVTTPH2QQZ128rrk:
26805 case VCVTTPH2QQZ128rrkz:
26806 case VCVTTPH2QQZ256rm:
26807 case VCVTTPH2QQZ256rmb:
26808 case VCVTTPH2QQZ256rmbk:
26809 case VCVTTPH2QQZ256rmbkz:
26810 case VCVTTPH2QQZ256rmk:
26811 case VCVTTPH2QQZ256rmkz:
26812 case VCVTTPH2QQZ256rr:
26813 case VCVTTPH2QQZ256rrk:
26814 case VCVTTPH2QQZ256rrkz:
26815 case VCVTTPH2QQZrm:
26816 case VCVTTPH2QQZrmb:
26817 case VCVTTPH2QQZrmbk:
26818 case VCVTTPH2QQZrmbkz:
26819 case VCVTTPH2QQZrmk:
26820 case VCVTTPH2QQZrmkz:
26821 case VCVTTPH2QQZrr:
26822 case VCVTTPH2QQZrrb:
26823 case VCVTTPH2QQZrrbk:
26824 case VCVTTPH2QQZrrbkz:
26825 case VCVTTPH2QQZrrk:
26826 case VCVTTPH2QQZrrkz:
26827 return true;
26828 }
26829 return false;
26830}
26831
26832bool isDIVPD(unsigned Opcode) {
26833 switch (Opcode) {
26834 case DIVPDrm:
26835 case DIVPDrr:
26836 return true;
26837 }
26838 return false;
26839}
26840
26841bool isCLFLUSH(unsigned Opcode) {
26842 return Opcode == CLFLUSH;
26843}
26844
26845bool isVPMINUW(unsigned Opcode) {
26846 switch (Opcode) {
26847 case VPMINUWYrm:
26848 case VPMINUWYrr:
26849 case VPMINUWZ128rm:
26850 case VPMINUWZ128rmk:
26851 case VPMINUWZ128rmkz:
26852 case VPMINUWZ128rr:
26853 case VPMINUWZ128rrk:
26854 case VPMINUWZ128rrkz:
26855 case VPMINUWZ256rm:
26856 case VPMINUWZ256rmk:
26857 case VPMINUWZ256rmkz:
26858 case VPMINUWZ256rr:
26859 case VPMINUWZ256rrk:
26860 case VPMINUWZ256rrkz:
26861 case VPMINUWZrm:
26862 case VPMINUWZrmk:
26863 case VPMINUWZrmkz:
26864 case VPMINUWZrr:
26865 case VPMINUWZrrk:
26866 case VPMINUWZrrkz:
26867 case VPMINUWrm:
26868 case VPMINUWrr:
26869 return true;
26870 }
26871 return false;
26872}
26873
26874bool isIN(unsigned Opcode) {
26875 switch (Opcode) {
26876 case IN16ri:
26877 case IN16rr:
26878 case IN32ri:
26879 case IN32rr:
26880 case IN8ri:
26881 case IN8rr:
26882 return true;
26883 }
26884 return false;
26885}
26886
26887bool isWRPKRU(unsigned Opcode) {
26888 return Opcode == WRPKRUr;
26889}
26890
26891bool isINSERTPS(unsigned Opcode) {
26892 switch (Opcode) {
26893 case INSERTPSrmi:
26894 case INSERTPSrri:
26895 return true;
26896 }
26897 return false;
26898}
26899
26900bool isAAM(unsigned Opcode) {
26901 return Opcode == AAM8i8;
26902}
26903
26904bool isVPHADDUDQ(unsigned Opcode) {
26905 switch (Opcode) {
26906 case VPHADDUDQrm:
26907 case VPHADDUDQrr:
26908 return true;
26909 }
26910 return false;
26911}
26912
26913bool isVSHA512MSG1(unsigned Opcode) {
26914 return Opcode == VSHA512MSG1rr;
26915}
26916
26917bool isDIVPS(unsigned Opcode) {
26918 switch (Opcode) {
26919 case DIVPSrm:
26920 case DIVPSrr:
26921 return true;
26922 }
26923 return false;
26924}
26925
26926bool isKNOTB(unsigned Opcode) {
26927 return Opcode == KNOTBkk;
26928}
26929
26930bool isBLSFILL(unsigned Opcode) {
26931 switch (Opcode) {
26932 case BLSFILL32rm:
26933 case BLSFILL32rr:
26934 case BLSFILL64rm:
26935 case BLSFILL64rr:
26936 return true;
26937 }
26938 return false;
26939}
26940
26941bool isVPCMPGTQ(unsigned Opcode) {
26942 switch (Opcode) {
26943 case VPCMPGTQYrm:
26944 case VPCMPGTQYrr:
26945 case VPCMPGTQZ128rm:
26946 case VPCMPGTQZ128rmb:
26947 case VPCMPGTQZ128rmbk:
26948 case VPCMPGTQZ128rmk:
26949 case VPCMPGTQZ128rr:
26950 case VPCMPGTQZ128rrk:
26951 case VPCMPGTQZ256rm:
26952 case VPCMPGTQZ256rmb:
26953 case VPCMPGTQZ256rmbk:
26954 case VPCMPGTQZ256rmk:
26955 case VPCMPGTQZ256rr:
26956 case VPCMPGTQZ256rrk:
26957 case VPCMPGTQZrm:
26958 case VPCMPGTQZrmb:
26959 case VPCMPGTQZrmbk:
26960 case VPCMPGTQZrmk:
26961 case VPCMPGTQZrr:
26962 case VPCMPGTQZrrk:
26963 case VPCMPGTQrm:
26964 case VPCMPGTQrr:
26965 return true;
26966 }
26967 return false;
26968}
26969
26970bool isMINSD(unsigned Opcode) {
26971 switch (Opcode) {
26972 case MINSDrm_Int:
26973 case MINSDrr_Int:
26974 return true;
26975 }
26976 return false;
26977}
26978
26979bool isFPREM(unsigned Opcode) {
26980 return Opcode == FPREM;
26981}
26982
26983bool isVPUNPCKHQDQ(unsigned Opcode) {
26984 switch (Opcode) {
26985 case VPUNPCKHQDQYrm:
26986 case VPUNPCKHQDQYrr:
26987 case VPUNPCKHQDQZ128rm:
26988 case VPUNPCKHQDQZ128rmb:
26989 case VPUNPCKHQDQZ128rmbk:
26990 case VPUNPCKHQDQZ128rmbkz:
26991 case VPUNPCKHQDQZ128rmk:
26992 case VPUNPCKHQDQZ128rmkz:
26993 case VPUNPCKHQDQZ128rr:
26994 case VPUNPCKHQDQZ128rrk:
26995 case VPUNPCKHQDQZ128rrkz:
26996 case VPUNPCKHQDQZ256rm:
26997 case VPUNPCKHQDQZ256rmb:
26998 case VPUNPCKHQDQZ256rmbk:
26999 case VPUNPCKHQDQZ256rmbkz:
27000 case VPUNPCKHQDQZ256rmk:
27001 case VPUNPCKHQDQZ256rmkz:
27002 case VPUNPCKHQDQZ256rr:
27003 case VPUNPCKHQDQZ256rrk:
27004 case VPUNPCKHQDQZ256rrkz:
27005 case VPUNPCKHQDQZrm:
27006 case VPUNPCKHQDQZrmb:
27007 case VPUNPCKHQDQZrmbk:
27008 case VPUNPCKHQDQZrmbkz:
27009 case VPUNPCKHQDQZrmk:
27010 case VPUNPCKHQDQZrmkz:
27011 case VPUNPCKHQDQZrr:
27012 case VPUNPCKHQDQZrrk:
27013 case VPUNPCKHQDQZrrkz:
27014 case VPUNPCKHQDQrm:
27015 case VPUNPCKHQDQrr:
27016 return true;
27017 }
27018 return false;
27019}
27020
27021bool isMINPD(unsigned Opcode) {
27022 switch (Opcode) {
27023 case MINPDrm:
27024 case MINPDrr:
27025 return true;
27026 }
27027 return false;
27028}
27029
27030bool isVCVTTPD2QQ(unsigned Opcode) {
27031 switch (Opcode) {
27032 case VCVTTPD2QQZ128rm:
27033 case VCVTTPD2QQZ128rmb:
27034 case VCVTTPD2QQZ128rmbk:
27035 case VCVTTPD2QQZ128rmbkz:
27036 case VCVTTPD2QQZ128rmk:
27037 case VCVTTPD2QQZ128rmkz:
27038 case VCVTTPD2QQZ128rr:
27039 case VCVTTPD2QQZ128rrk:
27040 case VCVTTPD2QQZ128rrkz:
27041 case VCVTTPD2QQZ256rm:
27042 case VCVTTPD2QQZ256rmb:
27043 case VCVTTPD2QQZ256rmbk:
27044 case VCVTTPD2QQZ256rmbkz:
27045 case VCVTTPD2QQZ256rmk:
27046 case VCVTTPD2QQZ256rmkz:
27047 case VCVTTPD2QQZ256rr:
27048 case VCVTTPD2QQZ256rrk:
27049 case VCVTTPD2QQZ256rrkz:
27050 case VCVTTPD2QQZrm:
27051 case VCVTTPD2QQZrmb:
27052 case VCVTTPD2QQZrmbk:
27053 case VCVTTPD2QQZrmbkz:
27054 case VCVTTPD2QQZrmk:
27055 case VCVTTPD2QQZrmkz:
27056 case VCVTTPD2QQZrr:
27057 case VCVTTPD2QQZrrb:
27058 case VCVTTPD2QQZrrbk:
27059 case VCVTTPD2QQZrrbkz:
27060 case VCVTTPD2QQZrrk:
27061 case VCVTTPD2QQZrrkz:
27062 return true;
27063 }
27064 return false;
27065}
27066
27067bool isVFMSUBPD(unsigned Opcode) {
27068 switch (Opcode) {
27069 case VFMSUBPD4Ymr:
27070 case VFMSUBPD4Yrm:
27071 case VFMSUBPD4Yrr:
27072 case VFMSUBPD4Yrr_REV:
27073 case VFMSUBPD4mr:
27074 case VFMSUBPD4rm:
27075 case VFMSUBPD4rr:
27076 case VFMSUBPD4rr_REV:
27077 return true;
27078 }
27079 return false;
27080}
27081
27082bool isV4FMADDSS(unsigned Opcode) {
27083 switch (Opcode) {
27084 case V4FMADDSSrm:
27085 case V4FMADDSSrmk:
27086 case V4FMADDSSrmkz:
27087 return true;
27088 }
27089 return false;
27090}
27091
27092bool isCPUID(unsigned Opcode) {
27093 return Opcode == CPUID;
27094}
27095
27096bool isSETCC(unsigned Opcode) {
27097 switch (Opcode) {
27098 case SETCCm:
27099 case SETCCm_EVEX:
27100 case SETCCr:
27101 case SETCCr_EVEX:
27102 return true;
27103 }
27104 return false;
27105}
27106
27107bool isVPDPWUUD(unsigned Opcode) {
27108 switch (Opcode) {
27109 case VPDPWUUDYrm:
27110 case VPDPWUUDYrr:
27111 case VPDPWUUDZ128rm:
27112 case VPDPWUUDZ128rmb:
27113 case VPDPWUUDZ128rmbk:
27114 case VPDPWUUDZ128rmbkz:
27115 case VPDPWUUDZ128rmk:
27116 case VPDPWUUDZ128rmkz:
27117 case VPDPWUUDZ128rr:
27118 case VPDPWUUDZ128rrk:
27119 case VPDPWUUDZ128rrkz:
27120 case VPDPWUUDZ256rm:
27121 case VPDPWUUDZ256rmb:
27122 case VPDPWUUDZ256rmbk:
27123 case VPDPWUUDZ256rmbkz:
27124 case VPDPWUUDZ256rmk:
27125 case VPDPWUUDZ256rmkz:
27126 case VPDPWUUDZ256rr:
27127 case VPDPWUUDZ256rrk:
27128 case VPDPWUUDZ256rrkz:
27129 case VPDPWUUDZrm:
27130 case VPDPWUUDZrmb:
27131 case VPDPWUUDZrmbk:
27132 case VPDPWUUDZrmbkz:
27133 case VPDPWUUDZrmk:
27134 case VPDPWUUDZrmkz:
27135 case VPDPWUUDZrr:
27136 case VPDPWUUDZrrk:
27137 case VPDPWUUDZrrkz:
27138 case VPDPWUUDrm:
27139 case VPDPWUUDrr:
27140 return true;
27141 }
27142 return false;
27143}
27144
27145bool isVCVTTPS2IUBS(unsigned Opcode) {
27146 switch (Opcode) {
27147 case VCVTTPS2IUBSZ128rm:
27148 case VCVTTPS2IUBSZ128rmb:
27149 case VCVTTPS2IUBSZ128rmbk:
27150 case VCVTTPS2IUBSZ128rmbkz:
27151 case VCVTTPS2IUBSZ128rmk:
27152 case VCVTTPS2IUBSZ128rmkz:
27153 case VCVTTPS2IUBSZ128rr:
27154 case VCVTTPS2IUBSZ128rrk:
27155 case VCVTTPS2IUBSZ128rrkz:
27156 case VCVTTPS2IUBSZ256rm:
27157 case VCVTTPS2IUBSZ256rmb:
27158 case VCVTTPS2IUBSZ256rmbk:
27159 case VCVTTPS2IUBSZ256rmbkz:
27160 case VCVTTPS2IUBSZ256rmk:
27161 case VCVTTPS2IUBSZ256rmkz:
27162 case VCVTTPS2IUBSZ256rr:
27163 case VCVTTPS2IUBSZ256rrk:
27164 case VCVTTPS2IUBSZ256rrkz:
27165 case VCVTTPS2IUBSZrm:
27166 case VCVTTPS2IUBSZrmb:
27167 case VCVTTPS2IUBSZrmbk:
27168 case VCVTTPS2IUBSZrmbkz:
27169 case VCVTTPS2IUBSZrmk:
27170 case VCVTTPS2IUBSZrmkz:
27171 case VCVTTPS2IUBSZrr:
27172 case VCVTTPS2IUBSZrrb:
27173 case VCVTTPS2IUBSZrrbk:
27174 case VCVTTPS2IUBSZrrbkz:
27175 case VCVTTPS2IUBSZrrk:
27176 case VCVTTPS2IUBSZrrkz:
27177 return true;
27178 }
27179 return false;
27180}
27181
27182bool isPMOVSXDQ(unsigned Opcode) {
27183 switch (Opcode) {
27184 case PMOVSXDQrm:
27185 case PMOVSXDQrr:
27186 return true;
27187 }
27188 return false;
27189}
27190
27191bool isMWAIT(unsigned Opcode) {
27192 return Opcode == MWAITrr;
27193}
27194
27195bool isVPEXTRB(unsigned Opcode) {
27196 switch (Opcode) {
27197 case VPEXTRBZmri:
27198 case VPEXTRBZrri:
27199 case VPEXTRBmri:
27200 case VPEXTRBrri:
27201 return true;
27202 }
27203 return false;
27204}
27205
27206bool isRMPCHKD(unsigned Opcode) {
27207 return Opcode == RMPCHKD;
27208}
27209
27210bool isINVVPID(unsigned Opcode) {
27211 switch (Opcode) {
27212 case INVVPID32:
27213 case INVVPID64:
27214 case INVVPID64_EVEX:
27215 return true;
27216 }
27217 return false;
27218}
27219
27220bool isVPSHUFD(unsigned Opcode) {
27221 switch (Opcode) {
27222 case VPSHUFDYmi:
27223 case VPSHUFDYri:
27224 case VPSHUFDZ128mbi:
27225 case VPSHUFDZ128mbik:
27226 case VPSHUFDZ128mbikz:
27227 case VPSHUFDZ128mi:
27228 case VPSHUFDZ128mik:
27229 case VPSHUFDZ128mikz:
27230 case VPSHUFDZ128ri:
27231 case VPSHUFDZ128rik:
27232 case VPSHUFDZ128rikz:
27233 case VPSHUFDZ256mbi:
27234 case VPSHUFDZ256mbik:
27235 case VPSHUFDZ256mbikz:
27236 case VPSHUFDZ256mi:
27237 case VPSHUFDZ256mik:
27238 case VPSHUFDZ256mikz:
27239 case VPSHUFDZ256ri:
27240 case VPSHUFDZ256rik:
27241 case VPSHUFDZ256rikz:
27242 case VPSHUFDZmbi:
27243 case VPSHUFDZmbik:
27244 case VPSHUFDZmbikz:
27245 case VPSHUFDZmi:
27246 case VPSHUFDZmik:
27247 case VPSHUFDZmikz:
27248 case VPSHUFDZri:
27249 case VPSHUFDZrik:
27250 case VPSHUFDZrikz:
27251 case VPSHUFDmi:
27252 case VPSHUFDri:
27253 return true;
27254 }
27255 return false;
27256}
27257
27258bool isVMINBF16(unsigned Opcode) {
27259 switch (Opcode) {
27260 case VMINBF16Z128rm:
27261 case VMINBF16Z128rmb:
27262 case VMINBF16Z128rmbk:
27263 case VMINBF16Z128rmbkz:
27264 case VMINBF16Z128rmk:
27265 case VMINBF16Z128rmkz:
27266 case VMINBF16Z128rr:
27267 case VMINBF16Z128rrk:
27268 case VMINBF16Z128rrkz:
27269 case VMINBF16Z256rm:
27270 case VMINBF16Z256rmb:
27271 case VMINBF16Z256rmbk:
27272 case VMINBF16Z256rmbkz:
27273 case VMINBF16Z256rmk:
27274 case VMINBF16Z256rmkz:
27275 case VMINBF16Z256rr:
27276 case VMINBF16Z256rrk:
27277 case VMINBF16Z256rrkz:
27278 case VMINBF16Zrm:
27279 case VMINBF16Zrmb:
27280 case VMINBF16Zrmbk:
27281 case VMINBF16Zrmbkz:
27282 case VMINBF16Zrmk:
27283 case VMINBF16Zrmkz:
27284 case VMINBF16Zrr:
27285 case VMINBF16Zrrk:
27286 case VMINBF16Zrrkz:
27287 return true;
27288 }
27289 return false;
27290}
27291
27292bool isMOVLPS(unsigned Opcode) {
27293 switch (Opcode) {
27294 case MOVLPSmr:
27295 case MOVLPSrm:
27296 return true;
27297 }
27298 return false;
27299}
27300
27301bool isVBLENDMPS(unsigned Opcode) {
27302 switch (Opcode) {
27303 case VBLENDMPSZ128rm:
27304 case VBLENDMPSZ128rmb:
27305 case VBLENDMPSZ128rmbk:
27306 case VBLENDMPSZ128rmbkz:
27307 case VBLENDMPSZ128rmk:
27308 case VBLENDMPSZ128rmkz:
27309 case VBLENDMPSZ128rr:
27310 case VBLENDMPSZ128rrk:
27311 case VBLENDMPSZ128rrkz:
27312 case VBLENDMPSZ256rm:
27313 case VBLENDMPSZ256rmb:
27314 case VBLENDMPSZ256rmbk:
27315 case VBLENDMPSZ256rmbkz:
27316 case VBLENDMPSZ256rmk:
27317 case VBLENDMPSZ256rmkz:
27318 case VBLENDMPSZ256rr:
27319 case VBLENDMPSZ256rrk:
27320 case VBLENDMPSZ256rrkz:
27321 case VBLENDMPSZrm:
27322 case VBLENDMPSZrmb:
27323 case VBLENDMPSZrmbk:
27324 case VBLENDMPSZrmbkz:
27325 case VBLENDMPSZrmk:
27326 case VBLENDMPSZrmkz:
27327 case VBLENDMPSZrr:
27328 case VBLENDMPSZrrk:
27329 case VBLENDMPSZrrkz:
27330 return true;
27331 }
27332 return false;
27333}
27334
27335bool isPMULLW(unsigned Opcode) {
27336 switch (Opcode) {
27337 case MMX_PMULLWrm:
27338 case MMX_PMULLWrr:
27339 case PMULLWrm:
27340 case PMULLWrr:
27341 return true;
27342 }
27343 return false;
27344}
27345
27346bool isVCVTSH2SI(unsigned Opcode) {
27347 switch (Opcode) {
27348 case VCVTSH2SI64Zrm_Int:
27349 case VCVTSH2SI64Zrr_Int:
27350 case VCVTSH2SI64Zrrb_Int:
27351 case VCVTSH2SIZrm_Int:
27352 case VCVTSH2SIZrr_Int:
27353 case VCVTSH2SIZrrb_Int:
27354 return true;
27355 }
27356 return false;
27357}
27358
27359bool isVPMOVSXWQ(unsigned Opcode) {
27360 switch (Opcode) {
27361 case VPMOVSXWQYrm:
27362 case VPMOVSXWQYrr:
27363 case VPMOVSXWQZ128rm:
27364 case VPMOVSXWQZ128rmk:
27365 case VPMOVSXWQZ128rmkz:
27366 case VPMOVSXWQZ128rr:
27367 case VPMOVSXWQZ128rrk:
27368 case VPMOVSXWQZ128rrkz:
27369 case VPMOVSXWQZ256rm:
27370 case VPMOVSXWQZ256rmk:
27371 case VPMOVSXWQZ256rmkz:
27372 case VPMOVSXWQZ256rr:
27373 case VPMOVSXWQZ256rrk:
27374 case VPMOVSXWQZ256rrkz:
27375 case VPMOVSXWQZrm:
27376 case VPMOVSXWQZrmk:
27377 case VPMOVSXWQZrmkz:
27378 case VPMOVSXWQZrr:
27379 case VPMOVSXWQZrrk:
27380 case VPMOVSXWQZrrkz:
27381 case VPMOVSXWQrm:
27382 case VPMOVSXWQrr:
27383 return true;
27384 }
27385 return false;
27386}
27387
27388bool isFNSTENV(unsigned Opcode) {
27389 return Opcode == FSTENVm;
27390}
27391
27392bool isVCVT2PH2BF8(unsigned Opcode) {
27393 switch (Opcode) {
27394 case VCVT2PH2BF8Z128rm:
27395 case VCVT2PH2BF8Z128rmb:
27396 case VCVT2PH2BF8Z128rmbk:
27397 case VCVT2PH2BF8Z128rmbkz:
27398 case VCVT2PH2BF8Z128rmk:
27399 case VCVT2PH2BF8Z128rmkz:
27400 case VCVT2PH2BF8Z128rr:
27401 case VCVT2PH2BF8Z128rrk:
27402 case VCVT2PH2BF8Z128rrkz:
27403 case VCVT2PH2BF8Z256rm:
27404 case VCVT2PH2BF8Z256rmb:
27405 case VCVT2PH2BF8Z256rmbk:
27406 case VCVT2PH2BF8Z256rmbkz:
27407 case VCVT2PH2BF8Z256rmk:
27408 case VCVT2PH2BF8Z256rmkz:
27409 case VCVT2PH2BF8Z256rr:
27410 case VCVT2PH2BF8Z256rrk:
27411 case VCVT2PH2BF8Z256rrkz:
27412 case VCVT2PH2BF8Zrm:
27413 case VCVT2PH2BF8Zrmb:
27414 case VCVT2PH2BF8Zrmbk:
27415 case VCVT2PH2BF8Zrmbkz:
27416 case VCVT2PH2BF8Zrmk:
27417 case VCVT2PH2BF8Zrmkz:
27418 case VCVT2PH2BF8Zrr:
27419 case VCVT2PH2BF8Zrrk:
27420 case VCVT2PH2BF8Zrrkz:
27421 return true;
27422 }
27423 return false;
27424}
27425
27426bool isVPERMI2PD(unsigned Opcode) {
27427 switch (Opcode) {
27428 case VPERMI2PDZ128rm:
27429 case VPERMI2PDZ128rmb:
27430 case VPERMI2PDZ128rmbk:
27431 case VPERMI2PDZ128rmbkz:
27432 case VPERMI2PDZ128rmk:
27433 case VPERMI2PDZ128rmkz:
27434 case VPERMI2PDZ128rr:
27435 case VPERMI2PDZ128rrk:
27436 case VPERMI2PDZ128rrkz:
27437 case VPERMI2PDZ256rm:
27438 case VPERMI2PDZ256rmb:
27439 case VPERMI2PDZ256rmbk:
27440 case VPERMI2PDZ256rmbkz:
27441 case VPERMI2PDZ256rmk:
27442 case VPERMI2PDZ256rmkz:
27443 case VPERMI2PDZ256rr:
27444 case VPERMI2PDZ256rrk:
27445 case VPERMI2PDZ256rrkz:
27446 case VPERMI2PDZrm:
27447 case VPERMI2PDZrmb:
27448 case VPERMI2PDZrmbk:
27449 case VPERMI2PDZrmbkz:
27450 case VPERMI2PDZrmk:
27451 case VPERMI2PDZrmkz:
27452 case VPERMI2PDZrr:
27453 case VPERMI2PDZrrk:
27454 case VPERMI2PDZrrkz:
27455 return true;
27456 }
27457 return false;
27458}
27459
27460bool isMAXSS(unsigned Opcode) {
27461 switch (Opcode) {
27462 case MAXSSrm_Int:
27463 case MAXSSrr_Int:
27464 return true;
27465 }
27466 return false;
27467}
27468
27469bool isCWDE(unsigned Opcode) {
27470 return Opcode == CWDE;
27471}
27472
27473bool isVBROADCASTI32X8(unsigned Opcode) {
27474 switch (Opcode) {
27475 case VBROADCASTI32X8Zrm:
27476 case VBROADCASTI32X8Zrmk:
27477 case VBROADCASTI32X8Zrmkz:
27478 return true;
27479 }
27480 return false;
27481}
27482
27483bool isINT(unsigned Opcode) {
27484 return Opcode == INT;
27485}
27486
27487bool isENCLS(unsigned Opcode) {
27488 return Opcode == ENCLS;
27489}
27490
27491bool isMOVNTQ(unsigned Opcode) {
27492 return Opcode == MMX_MOVNTQmr;
27493}
27494
27495bool isVDIVSH(unsigned Opcode) {
27496 switch (Opcode) {
27497 case VDIVSHZrm_Int:
27498 case VDIVSHZrmk_Int:
27499 case VDIVSHZrmkz_Int:
27500 case VDIVSHZrr_Int:
27501 case VDIVSHZrrb_Int:
27502 case VDIVSHZrrbk_Int:
27503 case VDIVSHZrrbkz_Int:
27504 case VDIVSHZrrk_Int:
27505 case VDIVSHZrrkz_Int:
27506 return true;
27507 }
27508 return false;
27509}
27510
27511bool isMOVHLPS(unsigned Opcode) {
27512 return Opcode == MOVHLPSrr;
27513}
27514
27515bool isVPMASKMOVD(unsigned Opcode) {
27516 switch (Opcode) {
27517 case VPMASKMOVDYmr:
27518 case VPMASKMOVDYrm:
27519 case VPMASKMOVDmr:
27520 case VPMASKMOVDrm:
27521 return true;
27522 }
27523 return false;
27524}
27525
27526bool isVMOVSD(unsigned Opcode) {
27527 switch (Opcode) {
27528 case VMOVSDZmr:
27529 case VMOVSDZmrk:
27530 case VMOVSDZrm:
27531 case VMOVSDZrmk:
27532 case VMOVSDZrmkz:
27533 case VMOVSDZrr:
27534 case VMOVSDZrr_REV:
27535 case VMOVSDZrrk:
27536 case VMOVSDZrrk_REV:
27537 case VMOVSDZrrkz:
27538 case VMOVSDZrrkz_REV:
27539 case VMOVSDmr:
27540 case VMOVSDrm:
27541 case VMOVSDrr:
27542 case VMOVSDrr_REV:
27543 return true;
27544 }
27545 return false;
27546}
27547
27548bool isVPMINUD(unsigned Opcode) {
27549 switch (Opcode) {
27550 case VPMINUDYrm:
27551 case VPMINUDYrr:
27552 case VPMINUDZ128rm:
27553 case VPMINUDZ128rmb:
27554 case VPMINUDZ128rmbk:
27555 case VPMINUDZ128rmbkz:
27556 case VPMINUDZ128rmk:
27557 case VPMINUDZ128rmkz:
27558 case VPMINUDZ128rr:
27559 case VPMINUDZ128rrk:
27560 case VPMINUDZ128rrkz:
27561 case VPMINUDZ256rm:
27562 case VPMINUDZ256rmb:
27563 case VPMINUDZ256rmbk:
27564 case VPMINUDZ256rmbkz:
27565 case VPMINUDZ256rmk:
27566 case VPMINUDZ256rmkz:
27567 case VPMINUDZ256rr:
27568 case VPMINUDZ256rrk:
27569 case VPMINUDZ256rrkz:
27570 case VPMINUDZrm:
27571 case VPMINUDZrmb:
27572 case VPMINUDZrmbk:
27573 case VPMINUDZrmbkz:
27574 case VPMINUDZrmk:
27575 case VPMINUDZrmkz:
27576 case VPMINUDZrr:
27577 case VPMINUDZrrk:
27578 case VPMINUDZrrkz:
27579 case VPMINUDrm:
27580 case VPMINUDrr:
27581 return true;
27582 }
27583 return false;
27584}
27585
27586bool isVPCMPISTRM(unsigned Opcode) {
27587 switch (Opcode) {
27588 case VPCMPISTRMrmi:
27589 case VPCMPISTRMrri:
27590 return true;
27591 }
27592 return false;
27593}
27594
27595bool isVGETMANTSD(unsigned Opcode) {
27596 switch (Opcode) {
27597 case VGETMANTSDZrmi:
27598 case VGETMANTSDZrmik:
27599 case VGETMANTSDZrmikz:
27600 case VGETMANTSDZrri:
27601 case VGETMANTSDZrrib:
27602 case VGETMANTSDZrribk:
27603 case VGETMANTSDZrribkz:
27604 case VGETMANTSDZrrik:
27605 case VGETMANTSDZrrikz:
27606 return true;
27607 }
27608 return false;
27609}
27610
27611bool isKSHIFTRW(unsigned Opcode) {
27612 return Opcode == KSHIFTRWki;
27613}
27614
27615bool isAESDECLAST(unsigned Opcode) {
27616 switch (Opcode) {
27617 case AESDECLASTrm:
27618 case AESDECLASTrr:
27619 return true;
27620 }
27621 return false;
27622}
27623
27624bool isVPTESTMB(unsigned Opcode) {
27625 switch (Opcode) {
27626 case VPTESTMBZ128rm:
27627 case VPTESTMBZ128rmk:
27628 case VPTESTMBZ128rr:
27629 case VPTESTMBZ128rrk:
27630 case VPTESTMBZ256rm:
27631 case VPTESTMBZ256rmk:
27632 case VPTESTMBZ256rr:
27633 case VPTESTMBZ256rrk:
27634 case VPTESTMBZrm:
27635 case VPTESTMBZrmk:
27636 case VPTESTMBZrr:
27637 case VPTESTMBZrrk:
27638 return true;
27639 }
27640 return false;
27641}
27642
27643bool isVFNMSUB231BF16(unsigned Opcode) {
27644 switch (Opcode) {
27645 case VFNMSUB231BF16Z128m:
27646 case VFNMSUB231BF16Z128mb:
27647 case VFNMSUB231BF16Z128mbk:
27648 case VFNMSUB231BF16Z128mbkz:
27649 case VFNMSUB231BF16Z128mk:
27650 case VFNMSUB231BF16Z128mkz:
27651 case VFNMSUB231BF16Z128r:
27652 case VFNMSUB231BF16Z128rk:
27653 case VFNMSUB231BF16Z128rkz:
27654 case VFNMSUB231BF16Z256m:
27655 case VFNMSUB231BF16Z256mb:
27656 case VFNMSUB231BF16Z256mbk:
27657 case VFNMSUB231BF16Z256mbkz:
27658 case VFNMSUB231BF16Z256mk:
27659 case VFNMSUB231BF16Z256mkz:
27660 case VFNMSUB231BF16Z256r:
27661 case VFNMSUB231BF16Z256rk:
27662 case VFNMSUB231BF16Z256rkz:
27663 case VFNMSUB231BF16Zm:
27664 case VFNMSUB231BF16Zmb:
27665 case VFNMSUB231BF16Zmbk:
27666 case VFNMSUB231BF16Zmbkz:
27667 case VFNMSUB231BF16Zmk:
27668 case VFNMSUB231BF16Zmkz:
27669 case VFNMSUB231BF16Zr:
27670 case VFNMSUB231BF16Zrk:
27671 case VFNMSUB231BF16Zrkz:
27672 return true;
27673 }
27674 return false;
27675}
27676
27677bool isVMPTRST(unsigned Opcode) {
27678 return Opcode == VMPTRSTm;
27679}
27680
27681bool isLLDT(unsigned Opcode) {
27682 switch (Opcode) {
27683 case LLDT16m:
27684 case LLDT16r:
27685 return true;
27686 }
27687 return false;
27688}
27689
27690bool isVUNPACKB(unsigned Opcode) {
27691 switch (Opcode) {
27692 case VUNPACKBZ128rmi:
27693 case VUNPACKBZ128rmik:
27694 case VUNPACKBZ128rmikz:
27695 case VUNPACKBZ128rri:
27696 case VUNPACKBZ128rrik:
27697 case VUNPACKBZ128rrikz:
27698 case VUNPACKBZ256rmi:
27699 case VUNPACKBZ256rmik:
27700 case VUNPACKBZ256rmikz:
27701 case VUNPACKBZ256rri:
27702 case VUNPACKBZ256rrik:
27703 case VUNPACKBZ256rrikz:
27704 case VUNPACKBZrmi:
27705 case VUNPACKBZrmik:
27706 case VUNPACKBZrmikz:
27707 case VUNPACKBZrri:
27708 case VUNPACKBZrrik:
27709 case VUNPACKBZrrikz:
27710 return true;
27711 }
27712 return false;
27713}
27714
27715bool isMOVSB(unsigned Opcode) {
27716 return Opcode == MOVSB;
27717}
27718
27719bool isTILELOADD(unsigned Opcode) {
27720 switch (Opcode) {
27721 case TILELOADD:
27722 case TILELOADD_EVEX:
27723 return true;
27724 }
27725 return false;
27726}
27727
27728bool isKTESTB(unsigned Opcode) {
27729 return Opcode == KTESTBkk;
27730}
27731
27732bool isMOVUPD(unsigned Opcode) {
27733 switch (Opcode) {
27734 case MOVUPDmr:
27735 case MOVUPDrm:
27736 case MOVUPDrr:
27737 case MOVUPDrr_REV:
27738 return true;
27739 }
27740 return false;
27741}
27742
27743bool isLKGS(unsigned Opcode) {
27744 switch (Opcode) {
27745 case LKGS16m:
27746 case LKGS16r:
27747 return true;
27748 }
27749 return false;
27750}
27751
27752bool isSGDTW(unsigned Opcode) {
27753 return Opcode == SGDT16m;
27754}
27755
27756bool isDIVSS(unsigned Opcode) {
27757 switch (Opcode) {
27758 case DIVSSrm_Int:
27759 case DIVSSrr_Int:
27760 return true;
27761 }
27762 return false;
27763}
27764
27765bool isPUNPCKHQDQ(unsigned Opcode) {
27766 switch (Opcode) {
27767 case PUNPCKHQDQrm:
27768 case PUNPCKHQDQrr:
27769 return true;
27770 }
27771 return false;
27772}
27773
27774bool isVFMADD213SD(unsigned Opcode) {
27775 switch (Opcode) {
27776 case VFMADD213SDZm_Int:
27777 case VFMADD213SDZmk_Int:
27778 case VFMADD213SDZmkz_Int:
27779 case VFMADD213SDZr_Int:
27780 case VFMADD213SDZrb_Int:
27781 case VFMADD213SDZrbk_Int:
27782 case VFMADD213SDZrbkz_Int:
27783 case VFMADD213SDZrk_Int:
27784 case VFMADD213SDZrkz_Int:
27785 case VFMADD213SDm_Int:
27786 case VFMADD213SDr_Int:
27787 return true;
27788 }
27789 return false;
27790}
27791
27792bool isKXORD(unsigned Opcode) {
27793 return Opcode == KXORDkk;
27794}
27795
27796bool isVPMOVB2M(unsigned Opcode) {
27797 switch (Opcode) {
27798 case VPMOVB2MZ128kr:
27799 case VPMOVB2MZ256kr:
27800 case VPMOVB2MZkr:
27801 return true;
27802 }
27803 return false;
27804}
27805
27806bool isVMREAD(unsigned Opcode) {
27807 switch (Opcode) {
27808 case VMREAD32mr:
27809 case VMREAD32rr:
27810 case VMREAD64mr:
27811 case VMREAD64rr:
27812 return true;
27813 }
27814 return false;
27815}
27816
27817bool isVPDPWSSDS(unsigned Opcode) {
27818 switch (Opcode) {
27819 case VPDPWSSDSYrm:
27820 case VPDPWSSDSYrr:
27821 case VPDPWSSDSZ128rm:
27822 case VPDPWSSDSZ128rmb:
27823 case VPDPWSSDSZ128rmbk:
27824 case VPDPWSSDSZ128rmbkz:
27825 case VPDPWSSDSZ128rmk:
27826 case VPDPWSSDSZ128rmkz:
27827 case VPDPWSSDSZ128rr:
27828 case VPDPWSSDSZ128rrk:
27829 case VPDPWSSDSZ128rrkz:
27830 case VPDPWSSDSZ256rm:
27831 case VPDPWSSDSZ256rmb:
27832 case VPDPWSSDSZ256rmbk:
27833 case VPDPWSSDSZ256rmbkz:
27834 case VPDPWSSDSZ256rmk:
27835 case VPDPWSSDSZ256rmkz:
27836 case VPDPWSSDSZ256rr:
27837 case VPDPWSSDSZ256rrk:
27838 case VPDPWSSDSZ256rrkz:
27839 case VPDPWSSDSZrm:
27840 case VPDPWSSDSZrmb:
27841 case VPDPWSSDSZrmbk:
27842 case VPDPWSSDSZrmbkz:
27843 case VPDPWSSDSZrmk:
27844 case VPDPWSSDSZrmkz:
27845 case VPDPWSSDSZrr:
27846 case VPDPWSSDSZrrk:
27847 case VPDPWSSDSZrrkz:
27848 case VPDPWSSDSrm:
27849 case VPDPWSSDSrr:
27850 return true;
27851 }
27852 return false;
27853}
27854
27855bool isTILERELEASE(unsigned Opcode) {
27856 return Opcode == TILERELEASE;
27857}
27858
27859bool isVUCOMXSH(unsigned Opcode) {
27860 switch (Opcode) {
27861 case VUCOMXSHZrm_Int:
27862 case VUCOMXSHZrr_Int:
27863 case VUCOMXSHZrrb_Int:
27864 return true;
27865 }
27866 return false;
27867}
27868
27869bool isCLFLUSHOPT(unsigned Opcode) {
27870 return Opcode == CLFLUSHOPT;
27871}
27872
27873bool isDAS(unsigned Opcode) {
27874 return Opcode == DAS;
27875}
27876
27877bool isVSCALEFPH(unsigned Opcode) {
27878 switch (Opcode) {
27879 case VSCALEFPHZ128rm:
27880 case VSCALEFPHZ128rmb:
27881 case VSCALEFPHZ128rmbk:
27882 case VSCALEFPHZ128rmbkz:
27883 case VSCALEFPHZ128rmk:
27884 case VSCALEFPHZ128rmkz:
27885 case VSCALEFPHZ128rr:
27886 case VSCALEFPHZ128rrk:
27887 case VSCALEFPHZ128rrkz:
27888 case VSCALEFPHZ256rm:
27889 case VSCALEFPHZ256rmb:
27890 case VSCALEFPHZ256rmbk:
27891 case VSCALEFPHZ256rmbkz:
27892 case VSCALEFPHZ256rmk:
27893 case VSCALEFPHZ256rmkz:
27894 case VSCALEFPHZ256rr:
27895 case VSCALEFPHZ256rrk:
27896 case VSCALEFPHZ256rrkz:
27897 case VSCALEFPHZrm:
27898 case VSCALEFPHZrmb:
27899 case VSCALEFPHZrmbk:
27900 case VSCALEFPHZrmbkz:
27901 case VSCALEFPHZrmk:
27902 case VSCALEFPHZrmkz:
27903 case VSCALEFPHZrr:
27904 case VSCALEFPHZrrb:
27905 case VSCALEFPHZrrbk:
27906 case VSCALEFPHZrrbkz:
27907 case VSCALEFPHZrrk:
27908 case VSCALEFPHZrrkz:
27909 return true;
27910 }
27911 return false;
27912}
27913
27914bool isVSUBSD(unsigned Opcode) {
27915 switch (Opcode) {
27916 case VSUBSDZrm_Int:
27917 case VSUBSDZrmk_Int:
27918 case VSUBSDZrmkz_Int:
27919 case VSUBSDZrr_Int:
27920 case VSUBSDZrrb_Int:
27921 case VSUBSDZrrbk_Int:
27922 case VSUBSDZrrbkz_Int:
27923 case VSUBSDZrrk_Int:
27924 case VSUBSDZrrkz_Int:
27925 case VSUBSDrm_Int:
27926 case VSUBSDrr_Int:
27927 return true;
27928 }
27929 return false;
27930}
27931
27932bool isVCVTROPS2HF8(unsigned Opcode) {
27933 switch (Opcode) {
27934 case VCVTROPS2HF8Z128rm:
27935 case VCVTROPS2HF8Z128rmb:
27936 case VCVTROPS2HF8Z128rmbk:
27937 case VCVTROPS2HF8Z128rmbkz:
27938 case VCVTROPS2HF8Z128rmk:
27939 case VCVTROPS2HF8Z128rmkz:
27940 case VCVTROPS2HF8Z128rr:
27941 case VCVTROPS2HF8Z128rrk:
27942 case VCVTROPS2HF8Z128rrkz:
27943 case VCVTROPS2HF8Z256rm:
27944 case VCVTROPS2HF8Z256rmb:
27945 case VCVTROPS2HF8Z256rmbk:
27946 case VCVTROPS2HF8Z256rmbkz:
27947 case VCVTROPS2HF8Z256rmk:
27948 case VCVTROPS2HF8Z256rmkz:
27949 case VCVTROPS2HF8Z256rr:
27950 case VCVTROPS2HF8Z256rrk:
27951 case VCVTROPS2HF8Z256rrkz:
27952 case VCVTROPS2HF8Zrm:
27953 case VCVTROPS2HF8Zrmb:
27954 case VCVTROPS2HF8Zrmbk:
27955 case VCVTROPS2HF8Zrmbkz:
27956 case VCVTROPS2HF8Zrmk:
27957 case VCVTROPS2HF8Zrmkz:
27958 case VCVTROPS2HF8Zrr:
27959 case VCVTROPS2HF8Zrrk:
27960 case VCVTROPS2HF8Zrrkz:
27961 return true;
27962 }
27963 return false;
27964}
27965
27966bool isVCOMISS(unsigned Opcode) {
27967 switch (Opcode) {
27968 case VCOMISSZrm:
27969 case VCOMISSZrr:
27970 case VCOMISSZrrb:
27971 case VCOMISSrm:
27972 case VCOMISSrr:
27973 return true;
27974 }
27975 return false;
27976}
27977
27978bool isVMULBF16(unsigned Opcode) {
27979 switch (Opcode) {
27980 case VMULBF16Z128rm:
27981 case VMULBF16Z128rmb:
27982 case VMULBF16Z128rmbk:
27983 case VMULBF16Z128rmbkz:
27984 case VMULBF16Z128rmk:
27985 case VMULBF16Z128rmkz:
27986 case VMULBF16Z128rr:
27987 case VMULBF16Z128rrk:
27988 case VMULBF16Z128rrkz:
27989 case VMULBF16Z256rm:
27990 case VMULBF16Z256rmb:
27991 case VMULBF16Z256rmbk:
27992 case VMULBF16Z256rmbkz:
27993 case VMULBF16Z256rmk:
27994 case VMULBF16Z256rmkz:
27995 case VMULBF16Z256rr:
27996 case VMULBF16Z256rrk:
27997 case VMULBF16Z256rrkz:
27998 case VMULBF16Zrm:
27999 case VMULBF16Zrmb:
28000 case VMULBF16Zrmbk:
28001 case VMULBF16Zrmbkz:
28002 case VMULBF16Zrmk:
28003 case VMULBF16Zrmkz:
28004 case VMULBF16Zrr:
28005 case VMULBF16Zrrk:
28006 case VMULBF16Zrrkz:
28007 return true;
28008 }
28009 return false;
28010}
28011
28012bool isORPS(unsigned Opcode) {
28013 switch (Opcode) {
28014 case ORPSrm:
28015 case ORPSrr:
28016 return true;
28017 }
28018 return false;
28019}
28020
28021bool isTDPFP16PS(unsigned Opcode) {
28022 return Opcode == TDPFP16PS;
28023}
28024
28025bool isVMAXPD(unsigned Opcode) {
28026 switch (Opcode) {
28027 case VMAXPDYrm:
28028 case VMAXPDYrr:
28029 case VMAXPDZ128rm:
28030 case VMAXPDZ128rmb:
28031 case VMAXPDZ128rmbk:
28032 case VMAXPDZ128rmbkz:
28033 case VMAXPDZ128rmk:
28034 case VMAXPDZ128rmkz:
28035 case VMAXPDZ128rr:
28036 case VMAXPDZ128rrk:
28037 case VMAXPDZ128rrkz:
28038 case VMAXPDZ256rm:
28039 case VMAXPDZ256rmb:
28040 case VMAXPDZ256rmbk:
28041 case VMAXPDZ256rmbkz:
28042 case VMAXPDZ256rmk:
28043 case VMAXPDZ256rmkz:
28044 case VMAXPDZ256rr:
28045 case VMAXPDZ256rrk:
28046 case VMAXPDZ256rrkz:
28047 case VMAXPDZrm:
28048 case VMAXPDZrmb:
28049 case VMAXPDZrmbk:
28050 case VMAXPDZrmbkz:
28051 case VMAXPDZrmk:
28052 case VMAXPDZrmkz:
28053 case VMAXPDZrr:
28054 case VMAXPDZrrb:
28055 case VMAXPDZrrbk:
28056 case VMAXPDZrrbkz:
28057 case VMAXPDZrrk:
28058 case VMAXPDZrrkz:
28059 case VMAXPDrm:
28060 case VMAXPDrr:
28061 return true;
28062 }
28063 return false;
28064}
28065
28066bool isVPMOVWB(unsigned Opcode) {
28067 switch (Opcode) {
28068 case VPMOVWBZ128mr:
28069 case VPMOVWBZ128mrk:
28070 case VPMOVWBZ128rr:
28071 case VPMOVWBZ128rrk:
28072 case VPMOVWBZ128rrkz:
28073 case VPMOVWBZ256mr:
28074 case VPMOVWBZ256mrk:
28075 case VPMOVWBZ256rr:
28076 case VPMOVWBZ256rrk:
28077 case VPMOVWBZ256rrkz:
28078 case VPMOVWBZmr:
28079 case VPMOVWBZmrk:
28080 case VPMOVWBZrr:
28081 case VPMOVWBZrrk:
28082 case VPMOVWBZrrkz:
28083 return true;
28084 }
28085 return false;
28086}
28087
28088bool isVEXP2PS(unsigned Opcode) {
28089 switch (Opcode) {
28090 case VEXP2PSZm:
28091 case VEXP2PSZmb:
28092 case VEXP2PSZmbk:
28093 case VEXP2PSZmbkz:
28094 case VEXP2PSZmk:
28095 case VEXP2PSZmkz:
28096 case VEXP2PSZr:
28097 case VEXP2PSZrb:
28098 case VEXP2PSZrbk:
28099 case VEXP2PSZrbkz:
28100 case VEXP2PSZrk:
28101 case VEXP2PSZrkz:
28102 return true;
28103 }
28104 return false;
28105}
28106
28107bool isVPGATHERDQ(unsigned Opcode) {
28108 switch (Opcode) {
28109 case VPGATHERDQYrm:
28110 case VPGATHERDQZ128rm:
28111 case VPGATHERDQZ256rm:
28112 case VPGATHERDQZrm:
28113 case VPGATHERDQrm:
28114 return true;
28115 }
28116 return false;
28117}
28118
28119bool isVPSRAVQ(unsigned Opcode) {
28120 switch (Opcode) {
28121 case VPSRAVQZ128rm:
28122 case VPSRAVQZ128rmb:
28123 case VPSRAVQZ128rmbk:
28124 case VPSRAVQZ128rmbkz:
28125 case VPSRAVQZ128rmk:
28126 case VPSRAVQZ128rmkz:
28127 case VPSRAVQZ128rr:
28128 case VPSRAVQZ128rrk:
28129 case VPSRAVQZ128rrkz:
28130 case VPSRAVQZ256rm:
28131 case VPSRAVQZ256rmb:
28132 case VPSRAVQZ256rmbk:
28133 case VPSRAVQZ256rmbkz:
28134 case VPSRAVQZ256rmk:
28135 case VPSRAVQZ256rmkz:
28136 case VPSRAVQZ256rr:
28137 case VPSRAVQZ256rrk:
28138 case VPSRAVQZ256rrkz:
28139 case VPSRAVQZrm:
28140 case VPSRAVQZrmb:
28141 case VPSRAVQZrmbk:
28142 case VPSRAVQZrmbkz:
28143 case VPSRAVQZrmk:
28144 case VPSRAVQZrmkz:
28145 case VPSRAVQZrr:
28146 case VPSRAVQZrrk:
28147 case VPSRAVQZrrkz:
28148 return true;
28149 }
28150 return false;
28151}
28152
28153bool isPCMPISTRI(unsigned Opcode) {
28154 switch (Opcode) {
28155 case PCMPISTRIrmi:
28156 case PCMPISTRIrri:
28157 return true;
28158 }
28159 return false;
28160}
28161
28162bool isVFMSUB231PD(unsigned Opcode) {
28163 switch (Opcode) {
28164 case VFMSUB231PDYm:
28165 case VFMSUB231PDYr:
28166 case VFMSUB231PDZ128m:
28167 case VFMSUB231PDZ128mb:
28168 case VFMSUB231PDZ128mbk:
28169 case VFMSUB231PDZ128mbkz:
28170 case VFMSUB231PDZ128mk:
28171 case VFMSUB231PDZ128mkz:
28172 case VFMSUB231PDZ128r:
28173 case VFMSUB231PDZ128rk:
28174 case VFMSUB231PDZ128rkz:
28175 case VFMSUB231PDZ256m:
28176 case VFMSUB231PDZ256mb:
28177 case VFMSUB231PDZ256mbk:
28178 case VFMSUB231PDZ256mbkz:
28179 case VFMSUB231PDZ256mk:
28180 case VFMSUB231PDZ256mkz:
28181 case VFMSUB231PDZ256r:
28182 case VFMSUB231PDZ256rk:
28183 case VFMSUB231PDZ256rkz:
28184 case VFMSUB231PDZm:
28185 case VFMSUB231PDZmb:
28186 case VFMSUB231PDZmbk:
28187 case VFMSUB231PDZmbkz:
28188 case VFMSUB231PDZmk:
28189 case VFMSUB231PDZmkz:
28190 case VFMSUB231PDZr:
28191 case VFMSUB231PDZrb:
28192 case VFMSUB231PDZrbk:
28193 case VFMSUB231PDZrbkz:
28194 case VFMSUB231PDZrk:
28195 case VFMSUB231PDZrkz:
28196 case VFMSUB231PDm:
28197 case VFMSUB231PDr:
28198 return true;
28199 }
28200 return false;
28201}
28202
28203bool isRDMSR(unsigned Opcode) {
28204 switch (Opcode) {
28205 case RDMSR:
28206 case RDMSRri:
28207 case RDMSRri_EVEX:
28208 return true;
28209 }
28210 return false;
28211}
28212
28213bool isKORTESTD(unsigned Opcode) {
28214 return Opcode == KORTESTDkk;
28215}
28216
28217bool isVPBLENDMW(unsigned Opcode) {
28218 switch (Opcode) {
28219 case VPBLENDMWZ128rm:
28220 case VPBLENDMWZ128rmk:
28221 case VPBLENDMWZ128rmkz:
28222 case VPBLENDMWZ128rr:
28223 case VPBLENDMWZ128rrk:
28224 case VPBLENDMWZ128rrkz:
28225 case VPBLENDMWZ256rm:
28226 case VPBLENDMWZ256rmk:
28227 case VPBLENDMWZ256rmkz:
28228 case VPBLENDMWZ256rr:
28229 case VPBLENDMWZ256rrk:
28230 case VPBLENDMWZ256rrkz:
28231 case VPBLENDMWZrm:
28232 case VPBLENDMWZrmk:
28233 case VPBLENDMWZrmkz:
28234 case VPBLENDMWZrr:
28235 case VPBLENDMWZrrk:
28236 case VPBLENDMWZrrkz:
28237 return true;
28238 }
28239 return false;
28240}
28241
28242bool isPSHUFB(unsigned Opcode) {
28243 switch (Opcode) {
28244 case MMX_PSHUFBrm:
28245 case MMX_PSHUFBrr:
28246 case PSHUFBrm:
28247 case PSHUFBrr:
28248 return true;
28249 }
28250 return false;
28251}
28252
28253bool isVDPBF16PS(unsigned Opcode) {
28254 switch (Opcode) {
28255 case VDPBF16PSZ128m:
28256 case VDPBF16PSZ128mb:
28257 case VDPBF16PSZ128mbk:
28258 case VDPBF16PSZ128mbkz:
28259 case VDPBF16PSZ128mk:
28260 case VDPBF16PSZ128mkz:
28261 case VDPBF16PSZ128r:
28262 case VDPBF16PSZ128rk:
28263 case VDPBF16PSZ128rkz:
28264 case VDPBF16PSZ256m:
28265 case VDPBF16PSZ256mb:
28266 case VDPBF16PSZ256mbk:
28267 case VDPBF16PSZ256mbkz:
28268 case VDPBF16PSZ256mk:
28269 case VDPBF16PSZ256mkz:
28270 case VDPBF16PSZ256r:
28271 case VDPBF16PSZ256rk:
28272 case VDPBF16PSZ256rkz:
28273 case VDPBF16PSZm:
28274 case VDPBF16PSZmb:
28275 case VDPBF16PSZmbk:
28276 case VDPBF16PSZmbkz:
28277 case VDPBF16PSZmk:
28278 case VDPBF16PSZmkz:
28279 case VDPBF16PSZr:
28280 case VDPBF16PSZrk:
28281 case VDPBF16PSZrkz:
28282 return true;
28283 }
28284 return false;
28285}
28286
28287bool isTDPBF16PS(unsigned Opcode) {
28288 return Opcode == TDPBF16PS;
28289}
28290
28291bool isFCMOVE(unsigned Opcode) {
28292 return Opcode == CMOVE_F;
28293}
28294
28295bool isVFMADD231BF16(unsigned Opcode) {
28296 switch (Opcode) {
28297 case VFMADD231BF16Z128m:
28298 case VFMADD231BF16Z128mb:
28299 case VFMADD231BF16Z128mbk:
28300 case VFMADD231BF16Z128mbkz:
28301 case VFMADD231BF16Z128mk:
28302 case VFMADD231BF16Z128mkz:
28303 case VFMADD231BF16Z128r:
28304 case VFMADD231BF16Z128rk:
28305 case VFMADD231BF16Z128rkz:
28306 case VFMADD231BF16Z256m:
28307 case VFMADD231BF16Z256mb:
28308 case VFMADD231BF16Z256mbk:
28309 case VFMADD231BF16Z256mbkz:
28310 case VFMADD231BF16Z256mk:
28311 case VFMADD231BF16Z256mkz:
28312 case VFMADD231BF16Z256r:
28313 case VFMADD231BF16Z256rk:
28314 case VFMADD231BF16Z256rkz:
28315 case VFMADD231BF16Zm:
28316 case VFMADD231BF16Zmb:
28317 case VFMADD231BF16Zmbk:
28318 case VFMADD231BF16Zmbkz:
28319 case VFMADD231BF16Zmk:
28320 case VFMADD231BF16Zmkz:
28321 case VFMADD231BF16Zr:
28322 case VFMADD231BF16Zrk:
28323 case VFMADD231BF16Zrkz:
28324 return true;
28325 }
28326 return false;
28327}
28328
28329bool isCMPSS(unsigned Opcode) {
28330 switch (Opcode) {
28331 case CMPSSrmi_Int:
28332 case CMPSSrri_Int:
28333 return true;
28334 }
28335 return false;
28336}
28337
28338bool isMASKMOVDQU(unsigned Opcode) {
28339 switch (Opcode) {
28340 case MASKMOVDQU:
28341 case MASKMOVDQU64:
28342 return true;
28343 }
28344 return false;
28345}
28346
28347bool isSARX(unsigned Opcode) {
28348 switch (Opcode) {
28349 case SARX32rm:
28350 case SARX32rm_EVEX:
28351 case SARX32rr:
28352 case SARX32rr_EVEX:
28353 case SARX64rm:
28354 case SARX64rm_EVEX:
28355 case SARX64rr:
28356 case SARX64rr_EVEX:
28357 return true;
28358 }
28359 return false;
28360}
28361
28362bool isVPDPWUSDS(unsigned Opcode) {
28363 switch (Opcode) {
28364 case VPDPWUSDSYrm:
28365 case VPDPWUSDSYrr:
28366 case VPDPWUSDSZ128rm:
28367 case VPDPWUSDSZ128rmb:
28368 case VPDPWUSDSZ128rmbk:
28369 case VPDPWUSDSZ128rmbkz:
28370 case VPDPWUSDSZ128rmk:
28371 case VPDPWUSDSZ128rmkz:
28372 case VPDPWUSDSZ128rr:
28373 case VPDPWUSDSZ128rrk:
28374 case VPDPWUSDSZ128rrkz:
28375 case VPDPWUSDSZ256rm:
28376 case VPDPWUSDSZ256rmb:
28377 case VPDPWUSDSZ256rmbk:
28378 case VPDPWUSDSZ256rmbkz:
28379 case VPDPWUSDSZ256rmk:
28380 case VPDPWUSDSZ256rmkz:
28381 case VPDPWUSDSZ256rr:
28382 case VPDPWUSDSZ256rrk:
28383 case VPDPWUSDSZ256rrkz:
28384 case VPDPWUSDSZrm:
28385 case VPDPWUSDSZrmb:
28386 case VPDPWUSDSZrmbk:
28387 case VPDPWUSDSZrmbkz:
28388 case VPDPWUSDSZrmk:
28389 case VPDPWUSDSZrmkz:
28390 case VPDPWUSDSZrr:
28391 case VPDPWUSDSZrrk:
28392 case VPDPWUSDSZrrkz:
28393 case VPDPWUSDSrm:
28394 case VPDPWUSDSrr:
28395 return true;
28396 }
28397 return false;
28398}
28399
28400bool isSGDT(unsigned Opcode) {
28401 return Opcode == SGDT64m;
28402}
28403
28404bool isVFMULCPH(unsigned Opcode) {
28405 switch (Opcode) {
28406 case VFMULCPHZ128rm:
28407 case VFMULCPHZ128rmb:
28408 case VFMULCPHZ128rmbk:
28409 case VFMULCPHZ128rmbkz:
28410 case VFMULCPHZ128rmk:
28411 case VFMULCPHZ128rmkz:
28412 case VFMULCPHZ128rr:
28413 case VFMULCPHZ128rrk:
28414 case VFMULCPHZ128rrkz:
28415 case VFMULCPHZ256rm:
28416 case VFMULCPHZ256rmb:
28417 case VFMULCPHZ256rmbk:
28418 case VFMULCPHZ256rmbkz:
28419 case VFMULCPHZ256rmk:
28420 case VFMULCPHZ256rmkz:
28421 case VFMULCPHZ256rr:
28422 case VFMULCPHZ256rrk:
28423 case VFMULCPHZ256rrkz:
28424 case VFMULCPHZrm:
28425 case VFMULCPHZrmb:
28426 case VFMULCPHZrmbk:
28427 case VFMULCPHZrmbkz:
28428 case VFMULCPHZrmk:
28429 case VFMULCPHZrmkz:
28430 case VFMULCPHZrr:
28431 case VFMULCPHZrrb:
28432 case VFMULCPHZrrbk:
28433 case VFMULCPHZrrbkz:
28434 case VFMULCPHZrrk:
28435 case VFMULCPHZrrkz:
28436 return true;
28437 }
28438 return false;
28439}
28440
28441bool isURDMSR(unsigned Opcode) {
28442 switch (Opcode) {
28443 case URDMSRri:
28444 case URDMSRri_EVEX:
28445 case URDMSRrr:
28446 case URDMSRrr_EVEX:
28447 return true;
28448 }
28449 return false;
28450}
28451
28452bool isKUNPCKWD(unsigned Opcode) {
28453 return Opcode == KUNPCKWDkk;
28454}
28455
28456bool isVSCALEFBF16(unsigned Opcode) {
28457 switch (Opcode) {
28458 case VSCALEFBF16Z128rm:
28459 case VSCALEFBF16Z128rmb:
28460 case VSCALEFBF16Z128rmbk:
28461 case VSCALEFBF16Z128rmbkz:
28462 case VSCALEFBF16Z128rmk:
28463 case VSCALEFBF16Z128rmkz:
28464 case VSCALEFBF16Z128rr:
28465 case VSCALEFBF16Z128rrk:
28466 case VSCALEFBF16Z128rrkz:
28467 case VSCALEFBF16Z256rm:
28468 case VSCALEFBF16Z256rmb:
28469 case VSCALEFBF16Z256rmbk:
28470 case VSCALEFBF16Z256rmbkz:
28471 case VSCALEFBF16Z256rmk:
28472 case VSCALEFBF16Z256rmkz:
28473 case VSCALEFBF16Z256rr:
28474 case VSCALEFBF16Z256rrk:
28475 case VSCALEFBF16Z256rrkz:
28476 case VSCALEFBF16Zrm:
28477 case VSCALEFBF16Zrmb:
28478 case VSCALEFBF16Zrmbk:
28479 case VSCALEFBF16Zrmbkz:
28480 case VSCALEFBF16Zrmk:
28481 case VSCALEFBF16Zrmkz:
28482 case VSCALEFBF16Zrr:
28483 case VSCALEFBF16Zrrk:
28484 case VSCALEFBF16Zrrkz:
28485 return true;
28486 }
28487 return false;
28488}
28489
28490bool isCVTPS2PD(unsigned Opcode) {
28491 switch (Opcode) {
28492 case CVTPS2PDrm:
28493 case CVTPS2PDrr:
28494 return true;
28495 }
28496 return false;
28497}
28498
28499bool isFBSTP(unsigned Opcode) {
28500 return Opcode == FBSTPm;
28501}
28502
28503bool isPSUBQ(unsigned Opcode) {
28504 switch (Opcode) {
28505 case MMX_PSUBQrm:
28506 case MMX_PSUBQrr:
28507 case PSUBQrm:
28508 case PSUBQrr:
28509 return true;
28510 }
28511 return false;
28512}
28513
28514bool isFXSAVE64(unsigned Opcode) {
28515 return Opcode == FXSAVE64;
28516}
28517
28518bool isKMOVW(unsigned Opcode) {
28519 switch (Opcode) {
28520 case KMOVWkk:
28521 case KMOVWkk_EVEX:
28522 case KMOVWkm:
28523 case KMOVWkm_EVEX:
28524 case KMOVWkr:
28525 case KMOVWkr_EVEX:
28526 case KMOVWmk:
28527 case KMOVWmk_EVEX:
28528 case KMOVWrk:
28529 case KMOVWrk_EVEX:
28530 return true;
28531 }
28532 return false;
28533}
28534
28535bool isBTS(unsigned Opcode) {
28536 switch (Opcode) {
28537 case BTS16mi8:
28538 case BTS16mr:
28539 case BTS16ri8:
28540 case BTS16rr:
28541 case BTS32mi8:
28542 case BTS32mr:
28543 case BTS32ri8:
28544 case BTS32rr:
28545 case BTS64mi8:
28546 case BTS64mr:
28547 case BTS64ri8:
28548 case BTS64rr:
28549 return true;
28550 }
28551 return false;
28552}
28553
28554bool isVPHADDBQ(unsigned Opcode) {
28555 switch (Opcode) {
28556 case VPHADDBQrm:
28557 case VPHADDBQrr:
28558 return true;
28559 }
28560 return false;
28561}
28562
28563bool isFRSTOR(unsigned Opcode) {
28564 return Opcode == FRSTORm;
28565}
28566
28567bool isVFMSUB132PD(unsigned Opcode) {
28568 switch (Opcode) {
28569 case VFMSUB132PDYm:
28570 case VFMSUB132PDYr:
28571 case VFMSUB132PDZ128m:
28572 case VFMSUB132PDZ128mb:
28573 case VFMSUB132PDZ128mbk:
28574 case VFMSUB132PDZ128mbkz:
28575 case VFMSUB132PDZ128mk:
28576 case VFMSUB132PDZ128mkz:
28577 case VFMSUB132PDZ128r:
28578 case VFMSUB132PDZ128rk:
28579 case VFMSUB132PDZ128rkz:
28580 case VFMSUB132PDZ256m:
28581 case VFMSUB132PDZ256mb:
28582 case VFMSUB132PDZ256mbk:
28583 case VFMSUB132PDZ256mbkz:
28584 case VFMSUB132PDZ256mk:
28585 case VFMSUB132PDZ256mkz:
28586 case VFMSUB132PDZ256r:
28587 case VFMSUB132PDZ256rk:
28588 case VFMSUB132PDZ256rkz:
28589 case VFMSUB132PDZm:
28590 case VFMSUB132PDZmb:
28591 case VFMSUB132PDZmbk:
28592 case VFMSUB132PDZmbkz:
28593 case VFMSUB132PDZmk:
28594 case VFMSUB132PDZmkz:
28595 case VFMSUB132PDZr:
28596 case VFMSUB132PDZrb:
28597 case VFMSUB132PDZrbk:
28598 case VFMSUB132PDZrbkz:
28599 case VFMSUB132PDZrk:
28600 case VFMSUB132PDZrkz:
28601 case VFMSUB132PDm:
28602 case VFMSUB132PDr:
28603 return true;
28604 }
28605 return false;
28606}
28607
28608bool isPMULLD(unsigned Opcode) {
28609 switch (Opcode) {
28610 case PMULLDrm:
28611 case PMULLDrr:
28612 return true;
28613 }
28614 return false;
28615}
28616
28617bool isSHA1MSG2(unsigned Opcode) {
28618 switch (Opcode) {
28619 case SHA1MSG2rm:
28620 case SHA1MSG2rr:
28621 return true;
28622 }
28623 return false;
28624}
28625
28626bool isJECXZ(unsigned Opcode) {
28627 return Opcode == JECXZ;
28628}
28629
28630bool isVCVTUDQ2PS(unsigned Opcode) {
28631 switch (Opcode) {
28632 case VCVTUDQ2PSZ128rm:
28633 case VCVTUDQ2PSZ128rmb:
28634 case VCVTUDQ2PSZ128rmbk:
28635 case VCVTUDQ2PSZ128rmbkz:
28636 case VCVTUDQ2PSZ128rmk:
28637 case VCVTUDQ2PSZ128rmkz:
28638 case VCVTUDQ2PSZ128rr:
28639 case VCVTUDQ2PSZ128rrk:
28640 case VCVTUDQ2PSZ128rrkz:
28641 case VCVTUDQ2PSZ256rm:
28642 case VCVTUDQ2PSZ256rmb:
28643 case VCVTUDQ2PSZ256rmbk:
28644 case VCVTUDQ2PSZ256rmbkz:
28645 case VCVTUDQ2PSZ256rmk:
28646 case VCVTUDQ2PSZ256rmkz:
28647 case VCVTUDQ2PSZ256rr:
28648 case VCVTUDQ2PSZ256rrk:
28649 case VCVTUDQ2PSZ256rrkz:
28650 case VCVTUDQ2PSZrm:
28651 case VCVTUDQ2PSZrmb:
28652 case VCVTUDQ2PSZrmbk:
28653 case VCVTUDQ2PSZrmbkz:
28654 case VCVTUDQ2PSZrmk:
28655 case VCVTUDQ2PSZrmkz:
28656 case VCVTUDQ2PSZrr:
28657 case VCVTUDQ2PSZrrb:
28658 case VCVTUDQ2PSZrrbk:
28659 case VCVTUDQ2PSZrrbkz:
28660 case VCVTUDQ2PSZrrk:
28661 case VCVTUDQ2PSZrrkz:
28662 return true;
28663 }
28664 return false;
28665}
28666
28667bool isAESENC(unsigned Opcode) {
28668 switch (Opcode) {
28669 case AESENCrm:
28670 case AESENCrr:
28671 return true;
28672 }
28673 return false;
28674}
28675
28676bool isVMINMAXPS(unsigned Opcode) {
28677 switch (Opcode) {
28678 case VMINMAXPSZ128rmbi:
28679 case VMINMAXPSZ128rmbik:
28680 case VMINMAXPSZ128rmbikz:
28681 case VMINMAXPSZ128rmi:
28682 case VMINMAXPSZ128rmik:
28683 case VMINMAXPSZ128rmikz:
28684 case VMINMAXPSZ128rri:
28685 case VMINMAXPSZ128rrik:
28686 case VMINMAXPSZ128rrikz:
28687 case VMINMAXPSZ256rmbi:
28688 case VMINMAXPSZ256rmbik:
28689 case VMINMAXPSZ256rmbikz:
28690 case VMINMAXPSZ256rmi:
28691 case VMINMAXPSZ256rmik:
28692 case VMINMAXPSZ256rmikz:
28693 case VMINMAXPSZ256rri:
28694 case VMINMAXPSZ256rrik:
28695 case VMINMAXPSZ256rrikz:
28696 case VMINMAXPSZrmbi:
28697 case VMINMAXPSZrmbik:
28698 case VMINMAXPSZrmbikz:
28699 case VMINMAXPSZrmi:
28700 case VMINMAXPSZrmik:
28701 case VMINMAXPSZrmikz:
28702 case VMINMAXPSZrri:
28703 case VMINMAXPSZrrib:
28704 case VMINMAXPSZrribk:
28705 case VMINMAXPSZrribkz:
28706 case VMINMAXPSZrrik:
28707 case VMINMAXPSZrrikz:
28708 return true;
28709 }
28710 return false;
28711}
28712
28713bool isPSIGNW(unsigned Opcode) {
28714 switch (Opcode) {
28715 case MMX_PSIGNWrm:
28716 case MMX_PSIGNWrr:
28717 case PSIGNWrm:
28718 case PSIGNWrr:
28719 return true;
28720 }
28721 return false;
28722}
28723
28724bool isUNPCKLPD(unsigned Opcode) {
28725 switch (Opcode) {
28726 case UNPCKLPDrm:
28727 case UNPCKLPDrr:
28728 return true;
28729 }
28730 return false;
28731}
28732
28733bool isPUSHP(unsigned Opcode) {
28734 return Opcode == PUSHP64r;
28735}
28736
28737bool isBLSI(unsigned Opcode) {
28738 switch (Opcode) {
28739 case BLSI32rm:
28740 case BLSI32rm_EVEX:
28741 case BLSI32rm_NF:
28742 case BLSI32rr:
28743 case BLSI32rr_EVEX:
28744 case BLSI32rr_NF:
28745 case BLSI64rm:
28746 case BLSI64rm_EVEX:
28747 case BLSI64rm_NF:
28748 case BLSI64rr:
28749 case BLSI64rr_EVEX:
28750 case BLSI64rr_NF:
28751 return true;
28752 }
28753 return false;
28754}
28755
28756bool isVPTESTNMB(unsigned Opcode) {
28757 switch (Opcode) {
28758 case VPTESTNMBZ128rm:
28759 case VPTESTNMBZ128rmk:
28760 case VPTESTNMBZ128rr:
28761 case VPTESTNMBZ128rrk:
28762 case VPTESTNMBZ256rm:
28763 case VPTESTNMBZ256rmk:
28764 case VPTESTNMBZ256rr:
28765 case VPTESTNMBZ256rrk:
28766 case VPTESTNMBZrm:
28767 case VPTESTNMBZrmk:
28768 case VPTESTNMBZrr:
28769 case VPTESTNMBZrrk:
28770 return true;
28771 }
28772 return false;
28773}
28774
28775bool isWRUSSQ(unsigned Opcode) {
28776 switch (Opcode) {
28777 case WRUSSQ:
28778 case WRUSSQ_EVEX:
28779 return true;
28780 }
28781 return false;
28782}
28783
28784bool isVGF2P8MULB(unsigned Opcode) {
28785 switch (Opcode) {
28786 case VGF2P8MULBYrm:
28787 case VGF2P8MULBYrr:
28788 case VGF2P8MULBZ128rm:
28789 case VGF2P8MULBZ128rmk:
28790 case VGF2P8MULBZ128rmkz:
28791 case VGF2P8MULBZ128rr:
28792 case VGF2P8MULBZ128rrk:
28793 case VGF2P8MULBZ128rrkz:
28794 case VGF2P8MULBZ256rm:
28795 case VGF2P8MULBZ256rmk:
28796 case VGF2P8MULBZ256rmkz:
28797 case VGF2P8MULBZ256rr:
28798 case VGF2P8MULBZ256rrk:
28799 case VGF2P8MULBZ256rrkz:
28800 case VGF2P8MULBZrm:
28801 case VGF2P8MULBZrmk:
28802 case VGF2P8MULBZrmkz:
28803 case VGF2P8MULBZrr:
28804 case VGF2P8MULBZrrk:
28805 case VGF2P8MULBZrrkz:
28806 case VGF2P8MULBrm:
28807 case VGF2P8MULBrr:
28808 return true;
28809 }
28810 return false;
28811}
28812
28813bool isVPUNPCKLBW(unsigned Opcode) {
28814 switch (Opcode) {
28815 case VPUNPCKLBWYrm:
28816 case VPUNPCKLBWYrr:
28817 case VPUNPCKLBWZ128rm:
28818 case VPUNPCKLBWZ128rmk:
28819 case VPUNPCKLBWZ128rmkz:
28820 case VPUNPCKLBWZ128rr:
28821 case VPUNPCKLBWZ128rrk:
28822 case VPUNPCKLBWZ128rrkz:
28823 case VPUNPCKLBWZ256rm:
28824 case VPUNPCKLBWZ256rmk:
28825 case VPUNPCKLBWZ256rmkz:
28826 case VPUNPCKLBWZ256rr:
28827 case VPUNPCKLBWZ256rrk:
28828 case VPUNPCKLBWZ256rrkz:
28829 case VPUNPCKLBWZrm:
28830 case VPUNPCKLBWZrmk:
28831 case VPUNPCKLBWZrmkz:
28832 case VPUNPCKLBWZrr:
28833 case VPUNPCKLBWZrrk:
28834 case VPUNPCKLBWZrrkz:
28835 case VPUNPCKLBWrm:
28836 case VPUNPCKLBWrr:
28837 return true;
28838 }
28839 return false;
28840}
28841
28842bool isVRANGESD(unsigned Opcode) {
28843 switch (Opcode) {
28844 case VRANGESDZrmi:
28845 case VRANGESDZrmik:
28846 case VRANGESDZrmikz:
28847 case VRANGESDZrri:
28848 case VRANGESDZrrib:
28849 case VRANGESDZrribk:
28850 case VRANGESDZrribkz:
28851 case VRANGESDZrrik:
28852 case VRANGESDZrrikz:
28853 return true;
28854 }
28855 return false;
28856}
28857
28858bool isCLD(unsigned Opcode) {
28859 return Opcode == CLD;
28860}
28861
28862bool isVSCALEFPD(unsigned Opcode) {
28863 switch (Opcode) {
28864 case VSCALEFPDZ128rm:
28865 case VSCALEFPDZ128rmb:
28866 case VSCALEFPDZ128rmbk:
28867 case VSCALEFPDZ128rmbkz:
28868 case VSCALEFPDZ128rmk:
28869 case VSCALEFPDZ128rmkz:
28870 case VSCALEFPDZ128rr:
28871 case VSCALEFPDZ128rrk:
28872 case VSCALEFPDZ128rrkz:
28873 case VSCALEFPDZ256rm:
28874 case VSCALEFPDZ256rmb:
28875 case VSCALEFPDZ256rmbk:
28876 case VSCALEFPDZ256rmbkz:
28877 case VSCALEFPDZ256rmk:
28878 case VSCALEFPDZ256rmkz:
28879 case VSCALEFPDZ256rr:
28880 case VSCALEFPDZ256rrk:
28881 case VSCALEFPDZ256rrkz:
28882 case VSCALEFPDZrm:
28883 case VSCALEFPDZrmb:
28884 case VSCALEFPDZrmbk:
28885 case VSCALEFPDZrmbkz:
28886 case VSCALEFPDZrmk:
28887 case VSCALEFPDZrmkz:
28888 case VSCALEFPDZrr:
28889 case VSCALEFPDZrrb:
28890 case VSCALEFPDZrrbk:
28891 case VSCALEFPDZrrbkz:
28892 case VSCALEFPDZrrk:
28893 case VSCALEFPDZrrkz:
28894 return true;
28895 }
28896 return false;
28897}
28898
28899bool isVCOMXSS(unsigned Opcode) {
28900 switch (Opcode) {
28901 case VCOMXSSZrm_Int:
28902 case VCOMXSSZrr_Int:
28903 case VCOMXSSZrrb_Int:
28904 return true;
28905 }
28906 return false;
28907}
28908
28909bool isVPERMQ(unsigned Opcode) {
28910 switch (Opcode) {
28911 case VPERMQYmi:
28912 case VPERMQYri:
28913 case VPERMQZ256mbi:
28914 case VPERMQZ256mbik:
28915 case VPERMQZ256mbikz:
28916 case VPERMQZ256mi:
28917 case VPERMQZ256mik:
28918 case VPERMQZ256mikz:
28919 case VPERMQZ256ri:
28920 case VPERMQZ256rik:
28921 case VPERMQZ256rikz:
28922 case VPERMQZ256rm:
28923 case VPERMQZ256rmb:
28924 case VPERMQZ256rmbk:
28925 case VPERMQZ256rmbkz:
28926 case VPERMQZ256rmk:
28927 case VPERMQZ256rmkz:
28928 case VPERMQZ256rr:
28929 case VPERMQZ256rrk:
28930 case VPERMQZ256rrkz:
28931 case VPERMQZmbi:
28932 case VPERMQZmbik:
28933 case VPERMQZmbikz:
28934 case VPERMQZmi:
28935 case VPERMQZmik:
28936 case VPERMQZmikz:
28937 case VPERMQZri:
28938 case VPERMQZrik:
28939 case VPERMQZrikz:
28940 case VPERMQZrm:
28941 case VPERMQZrmb:
28942 case VPERMQZrmbk:
28943 case VPERMQZrmbkz:
28944 case VPERMQZrmk:
28945 case VPERMQZrmkz:
28946 case VPERMQZrr:
28947 case VPERMQZrrk:
28948 case VPERMQZrrkz:
28949 return true;
28950 }
28951 return false;
28952}
28953
28954bool isVPSHLDVW(unsigned Opcode) {
28955 switch (Opcode) {
28956 case VPSHLDVWZ128m:
28957 case VPSHLDVWZ128mk:
28958 case VPSHLDVWZ128mkz:
28959 case VPSHLDVWZ128r:
28960 case VPSHLDVWZ128rk:
28961 case VPSHLDVWZ128rkz:
28962 case VPSHLDVWZ256m:
28963 case VPSHLDVWZ256mk:
28964 case VPSHLDVWZ256mkz:
28965 case VPSHLDVWZ256r:
28966 case VPSHLDVWZ256rk:
28967 case VPSHLDVWZ256rkz:
28968 case VPSHLDVWZm:
28969 case VPSHLDVWZmk:
28970 case VPSHLDVWZmkz:
28971 case VPSHLDVWZr:
28972 case VPSHLDVWZrk:
28973 case VPSHLDVWZrkz:
28974 return true;
28975 }
28976 return false;
28977}
28978
28979bool isROR(unsigned Opcode) {
28980 switch (Opcode) {
28981 case ROR16m1:
28982 case ROR16m1_EVEX:
28983 case ROR16m1_ND:
28984 case ROR16m1_NF:
28985 case ROR16m1_NF_ND:
28986 case ROR16mCL:
28987 case ROR16mCL_EVEX:
28988 case ROR16mCL_ND:
28989 case ROR16mCL_NF:
28990 case ROR16mCL_NF_ND:
28991 case ROR16mi:
28992 case ROR16mi_EVEX:
28993 case ROR16mi_ND:
28994 case ROR16mi_NF:
28995 case ROR16mi_NF_ND:
28996 case ROR16r1:
28997 case ROR16r1_EVEX:
28998 case ROR16r1_ND:
28999 case ROR16r1_NF:
29000 case ROR16r1_NF_ND:
29001 case ROR16rCL:
29002 case ROR16rCL_EVEX:
29003 case ROR16rCL_ND:
29004 case ROR16rCL_NF:
29005 case ROR16rCL_NF_ND:
29006 case ROR16ri:
29007 case ROR16ri_EVEX:
29008 case ROR16ri_ND:
29009 case ROR16ri_NF:
29010 case ROR16ri_NF_ND:
29011 case ROR32m1:
29012 case ROR32m1_EVEX:
29013 case ROR32m1_ND:
29014 case ROR32m1_NF:
29015 case ROR32m1_NF_ND:
29016 case ROR32mCL:
29017 case ROR32mCL_EVEX:
29018 case ROR32mCL_ND:
29019 case ROR32mCL_NF:
29020 case ROR32mCL_NF_ND:
29021 case ROR32mi:
29022 case ROR32mi_EVEX:
29023 case ROR32mi_ND:
29024 case ROR32mi_NF:
29025 case ROR32mi_NF_ND:
29026 case ROR32r1:
29027 case ROR32r1_EVEX:
29028 case ROR32r1_ND:
29029 case ROR32r1_NF:
29030 case ROR32r1_NF_ND:
29031 case ROR32rCL:
29032 case ROR32rCL_EVEX:
29033 case ROR32rCL_ND:
29034 case ROR32rCL_NF:
29035 case ROR32rCL_NF_ND:
29036 case ROR32ri:
29037 case ROR32ri_EVEX:
29038 case ROR32ri_ND:
29039 case ROR32ri_NF:
29040 case ROR32ri_NF_ND:
29041 case ROR64m1:
29042 case ROR64m1_EVEX:
29043 case ROR64m1_ND:
29044 case ROR64m1_NF:
29045 case ROR64m1_NF_ND:
29046 case ROR64mCL:
29047 case ROR64mCL_EVEX:
29048 case ROR64mCL_ND:
29049 case ROR64mCL_NF:
29050 case ROR64mCL_NF_ND:
29051 case ROR64mi:
29052 case ROR64mi_EVEX:
29053 case ROR64mi_ND:
29054 case ROR64mi_NF:
29055 case ROR64mi_NF_ND:
29056 case ROR64r1:
29057 case ROR64r1_EVEX:
29058 case ROR64r1_ND:
29059 case ROR64r1_NF:
29060 case ROR64r1_NF_ND:
29061 case ROR64rCL:
29062 case ROR64rCL_EVEX:
29063 case ROR64rCL_ND:
29064 case ROR64rCL_NF:
29065 case ROR64rCL_NF_ND:
29066 case ROR64ri:
29067 case ROR64ri_EVEX:
29068 case ROR64ri_ND:
29069 case ROR64ri_NF:
29070 case ROR64ri_NF_ND:
29071 case ROR8m1:
29072 case ROR8m1_EVEX:
29073 case ROR8m1_ND:
29074 case ROR8m1_NF:
29075 case ROR8m1_NF_ND:
29076 case ROR8mCL:
29077 case ROR8mCL_EVEX:
29078 case ROR8mCL_ND:
29079 case ROR8mCL_NF:
29080 case ROR8mCL_NF_ND:
29081 case ROR8mi:
29082 case ROR8mi_EVEX:
29083 case ROR8mi_ND:
29084 case ROR8mi_NF:
29085 case ROR8mi_NF_ND:
29086 case ROR8r1:
29087 case ROR8r1_EVEX:
29088 case ROR8r1_ND:
29089 case ROR8r1_NF:
29090 case ROR8r1_NF_ND:
29091 case ROR8rCL:
29092 case ROR8rCL_EVEX:
29093 case ROR8rCL_ND:
29094 case ROR8rCL_NF:
29095 case ROR8rCL_NF_ND:
29096 case ROR8ri:
29097 case ROR8ri_EVEX:
29098 case ROR8ri_ND:
29099 case ROR8ri_NF:
29100 case ROR8ri_NF_ND:
29101 return true;
29102 }
29103 return false;
29104}
29105
29106bool isVFMADDSUB132PH(unsigned Opcode) {
29107 switch (Opcode) {
29108 case VFMADDSUB132PHZ128m:
29109 case VFMADDSUB132PHZ128mb:
29110 case VFMADDSUB132PHZ128mbk:
29111 case VFMADDSUB132PHZ128mbkz:
29112 case VFMADDSUB132PHZ128mk:
29113 case VFMADDSUB132PHZ128mkz:
29114 case VFMADDSUB132PHZ128r:
29115 case VFMADDSUB132PHZ128rk:
29116 case VFMADDSUB132PHZ128rkz:
29117 case VFMADDSUB132PHZ256m:
29118 case VFMADDSUB132PHZ256mb:
29119 case VFMADDSUB132PHZ256mbk:
29120 case VFMADDSUB132PHZ256mbkz:
29121 case VFMADDSUB132PHZ256mk:
29122 case VFMADDSUB132PHZ256mkz:
29123 case VFMADDSUB132PHZ256r:
29124 case VFMADDSUB132PHZ256rk:
29125 case VFMADDSUB132PHZ256rkz:
29126 case VFMADDSUB132PHZm:
29127 case VFMADDSUB132PHZmb:
29128 case VFMADDSUB132PHZmbk:
29129 case VFMADDSUB132PHZmbkz:
29130 case VFMADDSUB132PHZmk:
29131 case VFMADDSUB132PHZmkz:
29132 case VFMADDSUB132PHZr:
29133 case VFMADDSUB132PHZrb:
29134 case VFMADDSUB132PHZrbk:
29135 case VFMADDSUB132PHZrbkz:
29136 case VFMADDSUB132PHZrk:
29137 case VFMADDSUB132PHZrkz:
29138 return true;
29139 }
29140 return false;
29141}
29142
29143bool isDEC(unsigned Opcode) {
29144 switch (Opcode) {
29145 case DEC16m:
29146 case DEC16m_EVEX:
29147 case DEC16m_ND:
29148 case DEC16m_NF:
29149 case DEC16m_NF_ND:
29150 case DEC16r:
29151 case DEC16r_EVEX:
29152 case DEC16r_ND:
29153 case DEC16r_NF:
29154 case DEC16r_NF_ND:
29155 case DEC16r_alt:
29156 case DEC32m:
29157 case DEC32m_EVEX:
29158 case DEC32m_ND:
29159 case DEC32m_NF:
29160 case DEC32m_NF_ND:
29161 case DEC32r:
29162 case DEC32r_EVEX:
29163 case DEC32r_ND:
29164 case DEC32r_NF:
29165 case DEC32r_NF_ND:
29166 case DEC32r_alt:
29167 case DEC64m:
29168 case DEC64m_EVEX:
29169 case DEC64m_ND:
29170 case DEC64m_NF:
29171 case DEC64m_NF_ND:
29172 case DEC64r:
29173 case DEC64r_EVEX:
29174 case DEC64r_ND:
29175 case DEC64r_NF:
29176 case DEC64r_NF_ND:
29177 case DEC8m:
29178 case DEC8m_EVEX:
29179 case DEC8m_ND:
29180 case DEC8m_NF:
29181 case DEC8m_NF_ND:
29182 case DEC8r:
29183 case DEC8r_EVEX:
29184 case DEC8r_ND:
29185 case DEC8r_NF:
29186 case DEC8r_NF_ND:
29187 return true;
29188 }
29189 return false;
29190}
29191
29192bool isVGETEXPSH(unsigned Opcode) {
29193 switch (Opcode) {
29194 case VGETEXPSHZm:
29195 case VGETEXPSHZmk:
29196 case VGETEXPSHZmkz:
29197 case VGETEXPSHZr:
29198 case VGETEXPSHZrb:
29199 case VGETEXPSHZrbk:
29200 case VGETEXPSHZrbkz:
29201 case VGETEXPSHZrk:
29202 case VGETEXPSHZrkz:
29203 return true;
29204 }
29205 return false;
29206}
29207
29208bool isAESDEC(unsigned Opcode) {
29209 switch (Opcode) {
29210 case AESDECrm:
29211 case AESDECrr:
29212 return true;
29213 }
29214 return false;
29215}
29216
29217bool isKORD(unsigned Opcode) {
29218 return Opcode == KORDkk;
29219}
29220
29221bool isTILELOADDT1(unsigned Opcode) {
29222 switch (Opcode) {
29223 case TILELOADDT1:
29224 case TILELOADDT1_EVEX:
29225 return true;
29226 }
29227 return false;
29228}
29229
29230bool isVPMULHW(unsigned Opcode) {
29231 switch (Opcode) {
29232 case VPMULHWYrm:
29233 case VPMULHWYrr:
29234 case VPMULHWZ128rm:
29235 case VPMULHWZ128rmk:
29236 case VPMULHWZ128rmkz:
29237 case VPMULHWZ128rr:
29238 case VPMULHWZ128rrk:
29239 case VPMULHWZ128rrkz:
29240 case VPMULHWZ256rm:
29241 case VPMULHWZ256rmk:
29242 case VPMULHWZ256rmkz:
29243 case VPMULHWZ256rr:
29244 case VPMULHWZ256rrk:
29245 case VPMULHWZ256rrkz:
29246 case VPMULHWZrm:
29247 case VPMULHWZrmk:
29248 case VPMULHWZrmkz:
29249 case VPMULHWZrr:
29250 case VPMULHWZrrk:
29251 case VPMULHWZrrkz:
29252 case VPMULHWrm:
29253 case VPMULHWrr:
29254 return true;
29255 }
29256 return false;
29257}
29258
29259bool isVMASKMOVPS(unsigned Opcode) {
29260 switch (Opcode) {
29261 case VMASKMOVPSYmr:
29262 case VMASKMOVPSYrm:
29263 case VMASKMOVPSmr:
29264 case VMASKMOVPSrm:
29265 return true;
29266 }
29267 return false;
29268}
29269
29270bool isPMOVZXDQ(unsigned Opcode) {
29271 switch (Opcode) {
29272 case PMOVZXDQrm:
29273 case PMOVZXDQrr:
29274 return true;
29275 }
29276 return false;
29277}
29278
29279bool isVCVTPS2PH(unsigned Opcode) {
29280 switch (Opcode) {
29281 case VCVTPS2PHYmr:
29282 case VCVTPS2PHYrr:
29283 case VCVTPS2PHZ128mr:
29284 case VCVTPS2PHZ128mrk:
29285 case VCVTPS2PHZ128rr:
29286 case VCVTPS2PHZ128rrk:
29287 case VCVTPS2PHZ128rrkz:
29288 case VCVTPS2PHZ256mr:
29289 case VCVTPS2PHZ256mrk:
29290 case VCVTPS2PHZ256rr:
29291 case VCVTPS2PHZ256rrk:
29292 case VCVTPS2PHZ256rrkz:
29293 case VCVTPS2PHZmr:
29294 case VCVTPS2PHZmrk:
29295 case VCVTPS2PHZrr:
29296 case VCVTPS2PHZrrb:
29297 case VCVTPS2PHZrrbk:
29298 case VCVTPS2PHZrrbkz:
29299 case VCVTPS2PHZrrk:
29300 case VCVTPS2PHZrrkz:
29301 case VCVTPS2PHmr:
29302 case VCVTPS2PHrr:
29303 return true;
29304 }
29305 return false;
29306}
29307
29308bool isCVTDQ2PD(unsigned Opcode) {
29309 switch (Opcode) {
29310 case CVTDQ2PDrm:
29311 case CVTDQ2PDrr:
29312 return true;
29313 }
29314 return false;
29315}
29316
29317bool isVCVTSD2SS(unsigned Opcode) {
29318 switch (Opcode) {
29319 case VCVTSD2SSZrm_Int:
29320 case VCVTSD2SSZrmk_Int:
29321 case VCVTSD2SSZrmkz_Int:
29322 case VCVTSD2SSZrr_Int:
29323 case VCVTSD2SSZrrb_Int:
29324 case VCVTSD2SSZrrbk_Int:
29325 case VCVTSD2SSZrrbkz_Int:
29326 case VCVTSD2SSZrrk_Int:
29327 case VCVTSD2SSZrrkz_Int:
29328 case VCVTSD2SSrm_Int:
29329 case VCVTSD2SSrr_Int:
29330 return true;
29331 }
29332 return false;
29333}
29334
29335bool isVFMSUB213PH(unsigned Opcode) {
29336 switch (Opcode) {
29337 case VFMSUB213PHZ128m:
29338 case VFMSUB213PHZ128mb:
29339 case VFMSUB213PHZ128mbk:
29340 case VFMSUB213PHZ128mbkz:
29341 case VFMSUB213PHZ128mk:
29342 case VFMSUB213PHZ128mkz:
29343 case VFMSUB213PHZ128r:
29344 case VFMSUB213PHZ128rk:
29345 case VFMSUB213PHZ128rkz:
29346 case VFMSUB213PHZ256m:
29347 case VFMSUB213PHZ256mb:
29348 case VFMSUB213PHZ256mbk:
29349 case VFMSUB213PHZ256mbkz:
29350 case VFMSUB213PHZ256mk:
29351 case VFMSUB213PHZ256mkz:
29352 case VFMSUB213PHZ256r:
29353 case VFMSUB213PHZ256rk:
29354 case VFMSUB213PHZ256rkz:
29355 case VFMSUB213PHZm:
29356 case VFMSUB213PHZmb:
29357 case VFMSUB213PHZmbk:
29358 case VFMSUB213PHZmbkz:
29359 case VFMSUB213PHZmk:
29360 case VFMSUB213PHZmkz:
29361 case VFMSUB213PHZr:
29362 case VFMSUB213PHZrb:
29363 case VFMSUB213PHZrbk:
29364 case VFMSUB213PHZrbkz:
29365 case VFMSUB213PHZrk:
29366 case VFMSUB213PHZrkz:
29367 return true;
29368 }
29369 return false;
29370}
29371
29372bool isVPROTB(unsigned Opcode) {
29373 switch (Opcode) {
29374 case VPROTBmi:
29375 case VPROTBmr:
29376 case VPROTBri:
29377 case VPROTBrm:
29378 case VPROTBrr:
29379 case VPROTBrr_REV:
29380 return true;
29381 }
29382 return false;
29383}
29384
29385bool isPINSRD(unsigned Opcode) {
29386 switch (Opcode) {
29387 case PINSRDrmi:
29388 case PINSRDrri:
29389 return true;
29390 }
29391 return false;
29392}
29393
29394bool isVMXON(unsigned Opcode) {
29395 return Opcode == VMXON;
29396}
29397
29398bool isVFCMULCSH(unsigned Opcode) {
29399 switch (Opcode) {
29400 case VFCMULCSHZrm:
29401 case VFCMULCSHZrmk:
29402 case VFCMULCSHZrmkz:
29403 case VFCMULCSHZrr:
29404 case VFCMULCSHZrrb:
29405 case VFCMULCSHZrrbk:
29406 case VFCMULCSHZrrbkz:
29407 case VFCMULCSHZrrk:
29408 case VFCMULCSHZrrkz:
29409 return true;
29410 }
29411 return false;
29412}
29413
29414bool isVFMULCSH(unsigned Opcode) {
29415 switch (Opcode) {
29416 case VFMULCSHZrm:
29417 case VFMULCSHZrmk:
29418 case VFMULCSHZrmkz:
29419 case VFMULCSHZrr:
29420 case VFMULCSHZrrb:
29421 case VFMULCSHZrrbk:
29422 case VFMULCSHZrrbkz:
29423 case VFMULCSHZrrk:
29424 case VFMULCSHZrrkz:
29425 return true;
29426 }
29427 return false;
29428}
29429
29430bool isVRANGEPD(unsigned Opcode) {
29431 switch (Opcode) {
29432 case VRANGEPDZ128rmbi:
29433 case VRANGEPDZ128rmbik:
29434 case VRANGEPDZ128rmbikz:
29435 case VRANGEPDZ128rmi:
29436 case VRANGEPDZ128rmik:
29437 case VRANGEPDZ128rmikz:
29438 case VRANGEPDZ128rri:
29439 case VRANGEPDZ128rrik:
29440 case VRANGEPDZ128rrikz:
29441 case VRANGEPDZ256rmbi:
29442 case VRANGEPDZ256rmbik:
29443 case VRANGEPDZ256rmbikz:
29444 case VRANGEPDZ256rmi:
29445 case VRANGEPDZ256rmik:
29446 case VRANGEPDZ256rmikz:
29447 case VRANGEPDZ256rri:
29448 case VRANGEPDZ256rrik:
29449 case VRANGEPDZ256rrikz:
29450 case VRANGEPDZrmbi:
29451 case VRANGEPDZrmbik:
29452 case VRANGEPDZrmbikz:
29453 case VRANGEPDZrmi:
29454 case VRANGEPDZrmik:
29455 case VRANGEPDZrmikz:
29456 case VRANGEPDZrri:
29457 case VRANGEPDZrrib:
29458 case VRANGEPDZrribk:
29459 case VRANGEPDZrribkz:
29460 case VRANGEPDZrrik:
29461 case VRANGEPDZrrikz:
29462 return true;
29463 }
29464 return false;
29465}
29466
29467bool isCMC(unsigned Opcode) {
29468 return Opcode == CMC;
29469}
29470
29471bool isVFNMADD231BF16(unsigned Opcode) {
29472 switch (Opcode) {
29473 case VFNMADD231BF16Z128m:
29474 case VFNMADD231BF16Z128mb:
29475 case VFNMADD231BF16Z128mbk:
29476 case VFNMADD231BF16Z128mbkz:
29477 case VFNMADD231BF16Z128mk:
29478 case VFNMADD231BF16Z128mkz:
29479 case VFNMADD231BF16Z128r:
29480 case VFNMADD231BF16Z128rk:
29481 case VFNMADD231BF16Z128rkz:
29482 case VFNMADD231BF16Z256m:
29483 case VFNMADD231BF16Z256mb:
29484 case VFNMADD231BF16Z256mbk:
29485 case VFNMADD231BF16Z256mbkz:
29486 case VFNMADD231BF16Z256mk:
29487 case VFNMADD231BF16Z256mkz:
29488 case VFNMADD231BF16Z256r:
29489 case VFNMADD231BF16Z256rk:
29490 case VFNMADD231BF16Z256rkz:
29491 case VFNMADD231BF16Zm:
29492 case VFNMADD231BF16Zmb:
29493 case VFNMADD231BF16Zmbk:
29494 case VFNMADD231BF16Zmbkz:
29495 case VFNMADD231BF16Zmk:
29496 case VFNMADD231BF16Zmkz:
29497 case VFNMADD231BF16Zr:
29498 case VFNMADD231BF16Zrk:
29499 case VFNMADD231BF16Zrkz:
29500 return true;
29501 }
29502 return false;
29503}
29504
29505bool isSHA256MSG1(unsigned Opcode) {
29506 switch (Opcode) {
29507 case SHA256MSG1rm:
29508 case SHA256MSG1rr:
29509 return true;
29510 }
29511 return false;
29512}
29513
29514bool isFLD1(unsigned Opcode) {
29515 return Opcode == LD_F1;
29516}
29517
29518bool isCMPPS(unsigned Opcode) {
29519 switch (Opcode) {
29520 case CMPPSrmi:
29521 case CMPPSrri:
29522 return true;
29523 }
29524 return false;
29525}
29526
29527bool isVPAVGW(unsigned Opcode) {
29528 switch (Opcode) {
29529 case VPAVGWYrm:
29530 case VPAVGWYrr:
29531 case VPAVGWZ128rm:
29532 case VPAVGWZ128rmk:
29533 case VPAVGWZ128rmkz:
29534 case VPAVGWZ128rr:
29535 case VPAVGWZ128rrk:
29536 case VPAVGWZ128rrkz:
29537 case VPAVGWZ256rm:
29538 case VPAVGWZ256rmk:
29539 case VPAVGWZ256rmkz:
29540 case VPAVGWZ256rr:
29541 case VPAVGWZ256rrk:
29542 case VPAVGWZ256rrkz:
29543 case VPAVGWZrm:
29544 case VPAVGWZrmk:
29545 case VPAVGWZrmkz:
29546 case VPAVGWZrr:
29547 case VPAVGWZrrk:
29548 case VPAVGWZrrkz:
29549 case VPAVGWrm:
29550 case VPAVGWrr:
29551 return true;
29552 }
29553 return false;
29554}
29555
29556bool isVFMADD213SH(unsigned Opcode) {
29557 switch (Opcode) {
29558 case VFMADD213SHZm_Int:
29559 case VFMADD213SHZmk_Int:
29560 case VFMADD213SHZmkz_Int:
29561 case VFMADD213SHZr_Int:
29562 case VFMADD213SHZrb_Int:
29563 case VFMADD213SHZrbk_Int:
29564 case VFMADD213SHZrbkz_Int:
29565 case VFMADD213SHZrk_Int:
29566 case VFMADD213SHZrkz_Int:
29567 return true;
29568 }
29569 return false;
29570}
29571
29572bool isVPCMPESTRMQ(unsigned Opcode) {
29573 switch (Opcode) {
29574 case VPCMPESTRMQrmi:
29575 case VPCMPESTRMQrri:
29576 return true;
29577 }
29578 return false;
29579}
29580
29581bool isVPINSRQ(unsigned Opcode) {
29582 switch (Opcode) {
29583 case VPINSRQZrmi:
29584 case VPINSRQZrri:
29585 case VPINSRQrmi:
29586 case VPINSRQrri:
29587 return true;
29588 }
29589 return false;
29590}
29591
29592bool isMOVABS(unsigned Opcode) {
29593 switch (Opcode) {
29594 case MOV16ao64:
29595 case MOV16o64a:
29596 case MOV32ao64:
29597 case MOV32o64a:
29598 case MOV64ao64:
29599 case MOV64o64a:
29600 case MOV64ri:
29601 case MOV8ao64:
29602 case MOV8o64a:
29603 return true;
29604 }
29605 return false;
29606}
29607
29608bool isVPSHAQ(unsigned Opcode) {
29609 switch (Opcode) {
29610 case VPSHAQmr:
29611 case VPSHAQrm:
29612 case VPSHAQrr:
29613 case VPSHAQrr_REV:
29614 return true;
29615 }
29616 return false;
29617}
29618
29619bool isRDTSCP(unsigned Opcode) {
29620 return Opcode == RDTSCP;
29621}
29622
29623bool isVFNMADD231SS(unsigned Opcode) {
29624 switch (Opcode) {
29625 case VFNMADD231SSZm_Int:
29626 case VFNMADD231SSZmk_Int:
29627 case VFNMADD231SSZmkz_Int:
29628 case VFNMADD231SSZr_Int:
29629 case VFNMADD231SSZrb_Int:
29630 case VFNMADD231SSZrbk_Int:
29631 case VFNMADD231SSZrbkz_Int:
29632 case VFNMADD231SSZrk_Int:
29633 case VFNMADD231SSZrkz_Int:
29634 case VFNMADD231SSm_Int:
29635 case VFNMADD231SSr_Int:
29636 return true;
29637 }
29638 return false;
29639}
29640
29641bool isTEST(unsigned Opcode) {
29642 switch (Opcode) {
29643 case TEST16i16:
29644 case TEST16mi:
29645 case TEST16mr:
29646 case TEST16ri:
29647 case TEST16rr:
29648 case TEST32i32:
29649 case TEST32mi:
29650 case TEST32mr:
29651 case TEST32ri:
29652 case TEST32rr:
29653 case TEST64i32:
29654 case TEST64mi32:
29655 case TEST64mr:
29656 case TEST64ri32:
29657 case TEST64rr:
29658 case TEST8i8:
29659 case TEST8mi:
29660 case TEST8mr:
29661 case TEST8ri:
29662 case TEST8rr:
29663 return true;
29664 }
29665 return false;
29666}
29667
29668bool isVPERMD(unsigned Opcode) {
29669 switch (Opcode) {
29670 case VPERMDYrm:
29671 case VPERMDYrr:
29672 case VPERMDZ256rm:
29673 case VPERMDZ256rmb:
29674 case VPERMDZ256rmbk:
29675 case VPERMDZ256rmbkz:
29676 case VPERMDZ256rmk:
29677 case VPERMDZ256rmkz:
29678 case VPERMDZ256rr:
29679 case VPERMDZ256rrk:
29680 case VPERMDZ256rrkz:
29681 case VPERMDZrm:
29682 case VPERMDZrmb:
29683 case VPERMDZrmbk:
29684 case VPERMDZrmbkz:
29685 case VPERMDZrmk:
29686 case VPERMDZrmkz:
29687 case VPERMDZrr:
29688 case VPERMDZrrk:
29689 case VPERMDZrrkz:
29690 return true;
29691 }
29692 return false;
29693}
29694
29695bool isVBCSTNESH2PS(unsigned Opcode) {
29696 switch (Opcode) {
29697 case VBCSTNESH2PSYrm:
29698 case VBCSTNESH2PSrm:
29699 return true;
29700 }
29701 return false;
29702}
29703
29704bool isVGATHERPF0QPD(unsigned Opcode) {
29705 return Opcode == VGATHERPF0QPDm;
29706}
29707
29708bool isVPERM2I128(unsigned Opcode) {
29709 switch (Opcode) {
29710 case VPERM2I128rmi:
29711 case VPERM2I128rri:
29712 return true;
29713 }
29714 return false;
29715}
29716
29717bool isVMPSADBW(unsigned Opcode) {
29718 switch (Opcode) {
29719 case VMPSADBWYrmi:
29720 case VMPSADBWYrri:
29721 case VMPSADBWZ128rmi:
29722 case VMPSADBWZ128rmik:
29723 case VMPSADBWZ128rmikz:
29724 case VMPSADBWZ128rri:
29725 case VMPSADBWZ128rrik:
29726 case VMPSADBWZ128rrikz:
29727 case VMPSADBWZ256rmi:
29728 case VMPSADBWZ256rmik:
29729 case VMPSADBWZ256rmikz:
29730 case VMPSADBWZ256rri:
29731 case VMPSADBWZ256rrik:
29732 case VMPSADBWZ256rrikz:
29733 case VMPSADBWZrmi:
29734 case VMPSADBWZrmik:
29735 case VMPSADBWZrmikz:
29736 case VMPSADBWZrri:
29737 case VMPSADBWZrrik:
29738 case VMPSADBWZrrikz:
29739 case VMPSADBWrmi:
29740 case VMPSADBWrri:
29741 return true;
29742 }
29743 return false;
29744}
29745
29746bool isVFNMSUB231PD(unsigned Opcode) {
29747 switch (Opcode) {
29748 case VFNMSUB231PDYm:
29749 case VFNMSUB231PDYr:
29750 case VFNMSUB231PDZ128m:
29751 case VFNMSUB231PDZ128mb:
29752 case VFNMSUB231PDZ128mbk:
29753 case VFNMSUB231PDZ128mbkz:
29754 case VFNMSUB231PDZ128mk:
29755 case VFNMSUB231PDZ128mkz:
29756 case VFNMSUB231PDZ128r:
29757 case VFNMSUB231PDZ128rk:
29758 case VFNMSUB231PDZ128rkz:
29759 case VFNMSUB231PDZ256m:
29760 case VFNMSUB231PDZ256mb:
29761 case VFNMSUB231PDZ256mbk:
29762 case VFNMSUB231PDZ256mbkz:
29763 case VFNMSUB231PDZ256mk:
29764 case VFNMSUB231PDZ256mkz:
29765 case VFNMSUB231PDZ256r:
29766 case VFNMSUB231PDZ256rk:
29767 case VFNMSUB231PDZ256rkz:
29768 case VFNMSUB231PDZm:
29769 case VFNMSUB231PDZmb:
29770 case VFNMSUB231PDZmbk:
29771 case VFNMSUB231PDZmbkz:
29772 case VFNMSUB231PDZmk:
29773 case VFNMSUB231PDZmkz:
29774 case VFNMSUB231PDZr:
29775 case VFNMSUB231PDZrb:
29776 case VFNMSUB231PDZrbk:
29777 case VFNMSUB231PDZrbkz:
29778 case VFNMSUB231PDZrk:
29779 case VFNMSUB231PDZrkz:
29780 case VFNMSUB231PDm:
29781 case VFNMSUB231PDr:
29782 return true;
29783 }
29784 return false;
29785}
29786
29787bool isPADDSB(unsigned Opcode) {
29788 switch (Opcode) {
29789 case MMX_PADDSBrm:
29790 case MMX_PADDSBrr:
29791 case PADDSBrm:
29792 case PADDSBrr:
29793 return true;
29794 }
29795 return false;
29796}
29797
29798bool isMWAITX(unsigned Opcode) {
29799 return Opcode == MWAITXrrr;
29800}
29801
29802bool isMONITORX(unsigned Opcode) {
29803 switch (Opcode) {
29804 case MONITORX32rrr:
29805 case MONITORX64rrr:
29806 return true;
29807 }
29808 return false;
29809}
29810
29811bool isVPEXPANDD(unsigned Opcode) {
29812 switch (Opcode) {
29813 case VPEXPANDDZ128rm:
29814 case VPEXPANDDZ128rmk:
29815 case VPEXPANDDZ128rmkz:
29816 case VPEXPANDDZ128rr:
29817 case VPEXPANDDZ128rrk:
29818 case VPEXPANDDZ128rrkz:
29819 case VPEXPANDDZ256rm:
29820 case VPEXPANDDZ256rmk:
29821 case VPEXPANDDZ256rmkz:
29822 case VPEXPANDDZ256rr:
29823 case VPEXPANDDZ256rrk:
29824 case VPEXPANDDZ256rrkz:
29825 case VPEXPANDDZrm:
29826 case VPEXPANDDZrmk:
29827 case VPEXPANDDZrmkz:
29828 case VPEXPANDDZrr:
29829 case VPEXPANDDZrrk:
29830 case VPEXPANDDZrrkz:
29831 return true;
29832 }
29833 return false;
29834}
29835
29836bool isVFRCZPD(unsigned Opcode) {
29837 switch (Opcode) {
29838 case VFRCZPDYrm:
29839 case VFRCZPDYrr:
29840 case VFRCZPDrm:
29841 case VFRCZPDrr:
29842 return true;
29843 }
29844 return false;
29845}
29846
29847bool isVRCPPH(unsigned Opcode) {
29848 switch (Opcode) {
29849 case VRCPPHZ128m:
29850 case VRCPPHZ128mb:
29851 case VRCPPHZ128mbk:
29852 case VRCPPHZ128mbkz:
29853 case VRCPPHZ128mk:
29854 case VRCPPHZ128mkz:
29855 case VRCPPHZ128r:
29856 case VRCPPHZ128rk:
29857 case VRCPPHZ128rkz:
29858 case VRCPPHZ256m:
29859 case VRCPPHZ256mb:
29860 case VRCPPHZ256mbk:
29861 case VRCPPHZ256mbkz:
29862 case VRCPPHZ256mk:
29863 case VRCPPHZ256mkz:
29864 case VRCPPHZ256r:
29865 case VRCPPHZ256rk:
29866 case VRCPPHZ256rkz:
29867 case VRCPPHZm:
29868 case VRCPPHZmb:
29869 case VRCPPHZmbk:
29870 case VRCPPHZmbkz:
29871 case VRCPPHZmk:
29872 case VRCPPHZmkz:
29873 case VRCPPHZr:
29874 case VRCPPHZrk:
29875 case VRCPPHZrkz:
29876 return true;
29877 }
29878 return false;
29879}
29880
29881bool isFEMMS(unsigned Opcode) {
29882 return Opcode == FEMMS;
29883}
29884
29885bool isVSCATTERQPD(unsigned Opcode) {
29886 switch (Opcode) {
29887 case VSCATTERQPDZ128mr:
29888 case VSCATTERQPDZ256mr:
29889 case VSCATTERQPDZmr:
29890 return true;
29891 }
29892 return false;
29893}
29894
29895bool isVMOVW(unsigned Opcode) {
29896 switch (Opcode) {
29897 case VMOVSH2Wrr:
29898 case VMOVSHtoW64rr:
29899 case VMOVW2SHrr:
29900 case VMOVW64toSHrr:
29901 case VMOVWmr:
29902 case VMOVWrm:
29903 case VMOVZPWILo2PWIZmr:
29904 case VMOVZPWILo2PWIZrm:
29905 case VMOVZPWILo2PWIZrr:
29906 case VMOVZPWILo2PWIZrr2:
29907 return true;
29908 }
29909 return false;
29910}
29911
29912bool isVPBROADCASTD(unsigned Opcode) {
29913 switch (Opcode) {
29914 case VPBROADCASTDYrm:
29915 case VPBROADCASTDYrr:
29916 case VPBROADCASTDZ128rm:
29917 case VPBROADCASTDZ128rmk:
29918 case VPBROADCASTDZ128rmkz:
29919 case VPBROADCASTDZ128rr:
29920 case VPBROADCASTDZ128rrk:
29921 case VPBROADCASTDZ128rrkz:
29922 case VPBROADCASTDZ256rm:
29923 case VPBROADCASTDZ256rmk:
29924 case VPBROADCASTDZ256rmkz:
29925 case VPBROADCASTDZ256rr:
29926 case VPBROADCASTDZ256rrk:
29927 case VPBROADCASTDZ256rrkz:
29928 case VPBROADCASTDZrm:
29929 case VPBROADCASTDZrmk:
29930 case VPBROADCASTDZrmkz:
29931 case VPBROADCASTDZrr:
29932 case VPBROADCASTDZrrk:
29933 case VPBROADCASTDZrrkz:
29934 case VPBROADCASTDrZ128rr:
29935 case VPBROADCASTDrZ128rrk:
29936 case VPBROADCASTDrZ128rrkz:
29937 case VPBROADCASTDrZ256rr:
29938 case VPBROADCASTDrZ256rrk:
29939 case VPBROADCASTDrZ256rrkz:
29940 case VPBROADCASTDrZrr:
29941 case VPBROADCASTDrZrrk:
29942 case VPBROADCASTDrZrrkz:
29943 case VPBROADCASTDrm:
29944 case VPBROADCASTDrr:
29945 return true;
29946 }
29947 return false;
29948}
29949
29950bool isSTOSB(unsigned Opcode) {
29951 return Opcode == STOSB;
29952}
29953
29954bool isFUCOMI(unsigned Opcode) {
29955 return Opcode == UCOM_FIr;
29956}
29957
29958bool isVBROADCASTI64X4(unsigned Opcode) {
29959 switch (Opcode) {
29960 case VBROADCASTI64X4Zrm:
29961 case VBROADCASTI64X4Zrmk:
29962 case VBROADCASTI64X4Zrmkz:
29963 return true;
29964 }
29965 return false;
29966}
29967
29968bool isFCMOVU(unsigned Opcode) {
29969 return Opcode == CMOVP_F;
29970}
29971
29972bool isPSHUFLW(unsigned Opcode) {
29973 switch (Opcode) {
29974 case PSHUFLWmi:
29975 case PSHUFLWri:
29976 return true;
29977 }
29978 return false;
29979}
29980
29981bool isCVTPI2PS(unsigned Opcode) {
29982 switch (Opcode) {
29983 case MMX_CVTPI2PSrm:
29984 case MMX_CVTPI2PSrr:
29985 return true;
29986 }
29987 return false;
29988}
29989
29990bool isVCVTTPD2UDQS(unsigned Opcode) {
29991 switch (Opcode) {
29992 case VCVTTPD2UDQSZ128rm:
29993 case VCVTTPD2UDQSZ128rmb:
29994 case VCVTTPD2UDQSZ128rmbk:
29995 case VCVTTPD2UDQSZ128rmbkz:
29996 case VCVTTPD2UDQSZ128rmk:
29997 case VCVTTPD2UDQSZ128rmkz:
29998 case VCVTTPD2UDQSZ128rr:
29999 case VCVTTPD2UDQSZ128rrk:
30000 case VCVTTPD2UDQSZ128rrkz:
30001 case VCVTTPD2UDQSZ256rm:
30002 case VCVTTPD2UDQSZ256rmb:
30003 case VCVTTPD2UDQSZ256rmbk:
30004 case VCVTTPD2UDQSZ256rmbkz:
30005 case VCVTTPD2UDQSZ256rmk:
30006 case VCVTTPD2UDQSZ256rmkz:
30007 case VCVTTPD2UDQSZ256rr:
30008 case VCVTTPD2UDQSZ256rrb:
30009 case VCVTTPD2UDQSZ256rrbk:
30010 case VCVTTPD2UDQSZ256rrbkz:
30011 case VCVTTPD2UDQSZ256rrk:
30012 case VCVTTPD2UDQSZ256rrkz:
30013 case VCVTTPD2UDQSZrm:
30014 case VCVTTPD2UDQSZrmb:
30015 case VCVTTPD2UDQSZrmbk:
30016 case VCVTTPD2UDQSZrmbkz:
30017 case VCVTTPD2UDQSZrmk:
30018 case VCVTTPD2UDQSZrmkz:
30019 case VCVTTPD2UDQSZrr:
30020 case VCVTTPD2UDQSZrrb:
30021 case VCVTTPD2UDQSZrrbk:
30022 case VCVTTPD2UDQSZrrbkz:
30023 case VCVTTPD2UDQSZrrk:
30024 case VCVTTPD2UDQSZrrkz:
30025 return true;
30026 }
30027 return false;
30028}
30029
30030bool isSYSCALL(unsigned Opcode) {
30031 return Opcode == SYSCALL;
30032}
30033
30034bool isVFMADD231SH(unsigned Opcode) {
30035 switch (Opcode) {
30036 case VFMADD231SHZm_Int:
30037 case VFMADD231SHZmk_Int:
30038 case VFMADD231SHZmkz_Int:
30039 case VFMADD231SHZr_Int:
30040 case VFMADD231SHZrb_Int:
30041 case VFMADD231SHZrbk_Int:
30042 case VFMADD231SHZrbkz_Int:
30043 case VFMADD231SHZrk_Int:
30044 case VFMADD231SHZrkz_Int:
30045 return true;
30046 }
30047 return false;
30048}
30049
30050bool isVPOPCNTB(unsigned Opcode) {
30051 switch (Opcode) {
30052 case VPOPCNTBZ128rm:
30053 case VPOPCNTBZ128rmk:
30054 case VPOPCNTBZ128rmkz:
30055 case VPOPCNTBZ128rr:
30056 case VPOPCNTBZ128rrk:
30057 case VPOPCNTBZ128rrkz:
30058 case VPOPCNTBZ256rm:
30059 case VPOPCNTBZ256rmk:
30060 case VPOPCNTBZ256rmkz:
30061 case VPOPCNTBZ256rr:
30062 case VPOPCNTBZ256rrk:
30063 case VPOPCNTBZ256rrkz:
30064 case VPOPCNTBZrm:
30065 case VPOPCNTBZrmk:
30066 case VPOPCNTBZrmkz:
30067 case VPOPCNTBZrr:
30068 case VPOPCNTBZrrk:
30069 case VPOPCNTBZrrkz:
30070 return true;
30071 }
30072 return false;
30073}
30074
30075bool isPMOVZXBW(unsigned Opcode) {
30076 switch (Opcode) {
30077 case PMOVZXBWrm:
30078 case PMOVZXBWrr:
30079 return true;
30080 }
30081 return false;
30082}
30083
30084bool isVCVTDQ2PS(unsigned Opcode) {
30085 switch (Opcode) {
30086 case VCVTDQ2PSYrm:
30087 case VCVTDQ2PSYrr:
30088 case VCVTDQ2PSZ128rm:
30089 case VCVTDQ2PSZ128rmb:
30090 case VCVTDQ2PSZ128rmbk:
30091 case VCVTDQ2PSZ128rmbkz:
30092 case VCVTDQ2PSZ128rmk:
30093 case VCVTDQ2PSZ128rmkz:
30094 case VCVTDQ2PSZ128rr:
30095 case VCVTDQ2PSZ128rrk:
30096 case VCVTDQ2PSZ128rrkz:
30097 case VCVTDQ2PSZ256rm:
30098 case VCVTDQ2PSZ256rmb:
30099 case VCVTDQ2PSZ256rmbk:
30100 case VCVTDQ2PSZ256rmbkz:
30101 case VCVTDQ2PSZ256rmk:
30102 case VCVTDQ2PSZ256rmkz:
30103 case VCVTDQ2PSZ256rr:
30104 case VCVTDQ2PSZ256rrk:
30105 case VCVTDQ2PSZ256rrkz:
30106 case VCVTDQ2PSZrm:
30107 case VCVTDQ2PSZrmb:
30108 case VCVTDQ2PSZrmbk:
30109 case VCVTDQ2PSZrmbkz:
30110 case VCVTDQ2PSZrmk:
30111 case VCVTDQ2PSZrmkz:
30112 case VCVTDQ2PSZrr:
30113 case VCVTDQ2PSZrrb:
30114 case VCVTDQ2PSZrrbk:
30115 case VCVTDQ2PSZrrbkz:
30116 case VCVTDQ2PSZrrk:
30117 case VCVTDQ2PSZrrkz:
30118 case VCVTDQ2PSrm:
30119 case VCVTDQ2PSrr:
30120 return true;
30121 }
30122 return false;
30123}
30124
30125bool isPSUBD(unsigned Opcode) {
30126 switch (Opcode) {
30127 case MMX_PSUBDrm:
30128 case MMX_PSUBDrr:
30129 case PSUBDrm:
30130 case PSUBDrr:
30131 return true;
30132 }
30133 return false;
30134}
30135
30136bool isVPCMPEQW(unsigned Opcode) {
30137 switch (Opcode) {
30138 case VPCMPEQWYrm:
30139 case VPCMPEQWYrr:
30140 case VPCMPEQWZ128rm:
30141 case VPCMPEQWZ128rmk:
30142 case VPCMPEQWZ128rr:
30143 case VPCMPEQWZ128rrk:
30144 case VPCMPEQWZ256rm:
30145 case VPCMPEQWZ256rmk:
30146 case VPCMPEQWZ256rr:
30147 case VPCMPEQWZ256rrk:
30148 case VPCMPEQWZrm:
30149 case VPCMPEQWZrmk:
30150 case VPCMPEQWZrr:
30151 case VPCMPEQWZrrk:
30152 case VPCMPEQWrm:
30153 case VPCMPEQWrr:
30154 return true;
30155 }
30156 return false;
30157}
30158
30159bool isMOVSW(unsigned Opcode) {
30160 return Opcode == MOVSW;
30161}
30162
30163bool isVSM3RNDS2(unsigned Opcode) {
30164 switch (Opcode) {
30165 case VSM3RNDS2rmi:
30166 case VSM3RNDS2rri:
30167 return true;
30168 }
30169 return false;
30170}
30171
30172bool isVPMOVUSQD(unsigned Opcode) {
30173 switch (Opcode) {
30174 case VPMOVUSQDZ128mr:
30175 case VPMOVUSQDZ128mrk:
30176 case VPMOVUSQDZ128rr:
30177 case VPMOVUSQDZ128rrk:
30178 case VPMOVUSQDZ128rrkz:
30179 case VPMOVUSQDZ256mr:
30180 case VPMOVUSQDZ256mrk:
30181 case VPMOVUSQDZ256rr:
30182 case VPMOVUSQDZ256rrk:
30183 case VPMOVUSQDZ256rrkz:
30184 case VPMOVUSQDZmr:
30185 case VPMOVUSQDZmrk:
30186 case VPMOVUSQDZrr:
30187 case VPMOVUSQDZrrk:
30188 case VPMOVUSQDZrrkz:
30189 return true;
30190 }
30191 return false;
30192}
30193
30194bool isCVTTPD2DQ(unsigned Opcode) {
30195 switch (Opcode) {
30196 case CVTTPD2DQrm:
30197 case CVTTPD2DQrr:
30198 return true;
30199 }
30200 return false;
30201}
30202
30203bool isVPEXPANDW(unsigned Opcode) {
30204 switch (Opcode) {
30205 case VPEXPANDWZ128rm:
30206 case VPEXPANDWZ128rmk:
30207 case VPEXPANDWZ128rmkz:
30208 case VPEXPANDWZ128rr:
30209 case VPEXPANDWZ128rrk:
30210 case VPEXPANDWZ128rrkz:
30211 case VPEXPANDWZ256rm:
30212 case VPEXPANDWZ256rmk:
30213 case VPEXPANDWZ256rmkz:
30214 case VPEXPANDWZ256rr:
30215 case VPEXPANDWZ256rrk:
30216 case VPEXPANDWZ256rrkz:
30217 case VPEXPANDWZrm:
30218 case VPEXPANDWZrmk:
30219 case VPEXPANDWZrmkz:
30220 case VPEXPANDWZrr:
30221 case VPEXPANDWZrrk:
30222 case VPEXPANDWZrrkz:
30223 return true;
30224 }
30225 return false;
30226}
30227
30228bool isVUCOMISH(unsigned Opcode) {
30229 switch (Opcode) {
30230 case VUCOMISHZrm:
30231 case VUCOMISHZrr:
30232 case VUCOMISHZrrb:
30233 return true;
30234 }
30235 return false;
30236}
30237
30238bool isVZEROALL(unsigned Opcode) {
30239 return Opcode == VZEROALL;
30240}
30241
30242bool isVPAND(unsigned Opcode) {
30243 switch (Opcode) {
30244 case VPANDYrm:
30245 case VPANDYrr:
30246 case VPANDrm:
30247 case VPANDrr:
30248 return true;
30249 }
30250 return false;
30251}
30252
30253bool isPMULDQ(unsigned Opcode) {
30254 switch (Opcode) {
30255 case PMULDQrm:
30256 case PMULDQrr:
30257 return true;
30258 }
30259 return false;
30260}
30261
30262bool isVPSHUFHW(unsigned Opcode) {
30263 switch (Opcode) {
30264 case VPSHUFHWYmi:
30265 case VPSHUFHWYri:
30266 case VPSHUFHWZ128mi:
30267 case VPSHUFHWZ128mik:
30268 case VPSHUFHWZ128mikz:
30269 case VPSHUFHWZ128ri:
30270 case VPSHUFHWZ128rik:
30271 case VPSHUFHWZ128rikz:
30272 case VPSHUFHWZ256mi:
30273 case VPSHUFHWZ256mik:
30274 case VPSHUFHWZ256mikz:
30275 case VPSHUFHWZ256ri:
30276 case VPSHUFHWZ256rik:
30277 case VPSHUFHWZ256rikz:
30278 case VPSHUFHWZmi:
30279 case VPSHUFHWZmik:
30280 case VPSHUFHWZmikz:
30281 case VPSHUFHWZri:
30282 case VPSHUFHWZrik:
30283 case VPSHUFHWZrikz:
30284 case VPSHUFHWmi:
30285 case VPSHUFHWri:
30286 return true;
30287 }
30288 return false;
30289}
30290
30291bool isVPALIGNR(unsigned Opcode) {
30292 switch (Opcode) {
30293 case VPALIGNRYrmi:
30294 case VPALIGNRYrri:
30295 case VPALIGNRZ128rmi:
30296 case VPALIGNRZ128rmik:
30297 case VPALIGNRZ128rmikz:
30298 case VPALIGNRZ128rri:
30299 case VPALIGNRZ128rrik:
30300 case VPALIGNRZ128rrikz:
30301 case VPALIGNRZ256rmi:
30302 case VPALIGNRZ256rmik:
30303 case VPALIGNRZ256rmikz:
30304 case VPALIGNRZ256rri:
30305 case VPALIGNRZ256rrik:
30306 case VPALIGNRZ256rrikz:
30307 case VPALIGNRZrmi:
30308 case VPALIGNRZrmik:
30309 case VPALIGNRZrmikz:
30310 case VPALIGNRZrri:
30311 case VPALIGNRZrrik:
30312 case VPALIGNRZrrikz:
30313 case VPALIGNRrmi:
30314 case VPALIGNRrri:
30315 return true;
30316 }
30317 return false;
30318}
30319
30320bool isSQRTSD(unsigned Opcode) {
30321 switch (Opcode) {
30322 case SQRTSDm_Int:
30323 case SQRTSDr_Int:
30324 return true;
30325 }
30326 return false;
30327}
30328
30329bool isVCVTTPH2UDQ(unsigned Opcode) {
30330 switch (Opcode) {
30331 case VCVTTPH2UDQZ128rm:
30332 case VCVTTPH2UDQZ128rmb:
30333 case VCVTTPH2UDQZ128rmbk:
30334 case VCVTTPH2UDQZ128rmbkz:
30335 case VCVTTPH2UDQZ128rmk:
30336 case VCVTTPH2UDQZ128rmkz:
30337 case VCVTTPH2UDQZ128rr:
30338 case VCVTTPH2UDQZ128rrk:
30339 case VCVTTPH2UDQZ128rrkz:
30340 case VCVTTPH2UDQZ256rm:
30341 case VCVTTPH2UDQZ256rmb:
30342 case VCVTTPH2UDQZ256rmbk:
30343 case VCVTTPH2UDQZ256rmbkz:
30344 case VCVTTPH2UDQZ256rmk:
30345 case VCVTTPH2UDQZ256rmkz:
30346 case VCVTTPH2UDQZ256rr:
30347 case VCVTTPH2UDQZ256rrk:
30348 case VCVTTPH2UDQZ256rrkz:
30349 case VCVTTPH2UDQZrm:
30350 case VCVTTPH2UDQZrmb:
30351 case VCVTTPH2UDQZrmbk:
30352 case VCVTTPH2UDQZrmbkz:
30353 case VCVTTPH2UDQZrmk:
30354 case VCVTTPH2UDQZrmkz:
30355 case VCVTTPH2UDQZrr:
30356 case VCVTTPH2UDQZrrb:
30357 case VCVTTPH2UDQZrrbk:
30358 case VCVTTPH2UDQZrrbkz:
30359 case VCVTTPH2UDQZrrk:
30360 case VCVTTPH2UDQZrrkz:
30361 return true;
30362 }
30363 return false;
30364}
30365
30366bool isVGETEXPPH(unsigned Opcode) {
30367 switch (Opcode) {
30368 case VGETEXPPHZ128m:
30369 case VGETEXPPHZ128mb:
30370 case VGETEXPPHZ128mbk:
30371 case VGETEXPPHZ128mbkz:
30372 case VGETEXPPHZ128mk:
30373 case VGETEXPPHZ128mkz:
30374 case VGETEXPPHZ128r:
30375 case VGETEXPPHZ128rk:
30376 case VGETEXPPHZ128rkz:
30377 case VGETEXPPHZ256m:
30378 case VGETEXPPHZ256mb:
30379 case VGETEXPPHZ256mbk:
30380 case VGETEXPPHZ256mbkz:
30381 case VGETEXPPHZ256mk:
30382 case VGETEXPPHZ256mkz:
30383 case VGETEXPPHZ256r:
30384 case VGETEXPPHZ256rk:
30385 case VGETEXPPHZ256rkz:
30386 case VGETEXPPHZm:
30387 case VGETEXPPHZmb:
30388 case VGETEXPPHZmbk:
30389 case VGETEXPPHZmbkz:
30390 case VGETEXPPHZmk:
30391 case VGETEXPPHZmkz:
30392 case VGETEXPPHZr:
30393 case VGETEXPPHZrb:
30394 case VGETEXPPHZrbk:
30395 case VGETEXPPHZrbkz:
30396 case VGETEXPPHZrk:
30397 case VGETEXPPHZrkz:
30398 return true;
30399 }
30400 return false;
30401}
30402
30403bool isADDPD(unsigned Opcode) {
30404 switch (Opcode) {
30405 case ADDPDrm:
30406 case ADDPDrr:
30407 return true;
30408 }
30409 return false;
30410}
30411
30412bool isVFNMADDPD(unsigned Opcode) {
30413 switch (Opcode) {
30414 case VFNMADDPD4Ymr:
30415 case VFNMADDPD4Yrm:
30416 case VFNMADDPD4Yrr:
30417 case VFNMADDPD4Yrr_REV:
30418 case VFNMADDPD4mr:
30419 case VFNMADDPD4rm:
30420 case VFNMADDPD4rr:
30421 case VFNMADDPD4rr_REV:
30422 return true;
30423 }
30424 return false;
30425}
30426
30427bool isSTTILECFG(unsigned Opcode) {
30428 switch (Opcode) {
30429 case STTILECFG:
30430 case STTILECFG_EVEX:
30431 return true;
30432 }
30433 return false;
30434}
30435
30436bool isVMINPD(unsigned Opcode) {
30437 switch (Opcode) {
30438 case VMINPDYrm:
30439 case VMINPDYrr:
30440 case VMINPDZ128rm:
30441 case VMINPDZ128rmb:
30442 case VMINPDZ128rmbk:
30443 case VMINPDZ128rmbkz:
30444 case VMINPDZ128rmk:
30445 case VMINPDZ128rmkz:
30446 case VMINPDZ128rr:
30447 case VMINPDZ128rrk:
30448 case VMINPDZ128rrkz:
30449 case VMINPDZ256rm:
30450 case VMINPDZ256rmb:
30451 case VMINPDZ256rmbk:
30452 case VMINPDZ256rmbkz:
30453 case VMINPDZ256rmk:
30454 case VMINPDZ256rmkz:
30455 case VMINPDZ256rr:
30456 case VMINPDZ256rrk:
30457 case VMINPDZ256rrkz:
30458 case VMINPDZrm:
30459 case VMINPDZrmb:
30460 case VMINPDZrmbk:
30461 case VMINPDZrmbkz:
30462 case VMINPDZrmk:
30463 case VMINPDZrmkz:
30464 case VMINPDZrr:
30465 case VMINPDZrrb:
30466 case VMINPDZrrbk:
30467 case VMINPDZrrbkz:
30468 case VMINPDZrrk:
30469 case VMINPDZrrkz:
30470 case VMINPDrm:
30471 case VMINPDrr:
30472 return true;
30473 }
30474 return false;
30475}
30476
30477bool isSHA1RNDS4(unsigned Opcode) {
30478 switch (Opcode) {
30479 case SHA1RNDS4rmi:
30480 case SHA1RNDS4rri:
30481 return true;
30482 }
30483 return false;
30484}
30485
30486bool isPBLENDVB(unsigned Opcode) {
30487 switch (Opcode) {
30488 case PBLENDVBrm0:
30489 case PBLENDVBrr0:
30490 return true;
30491 }
30492 return false;
30493}
30494
30495bool isVBROADCASTF128(unsigned Opcode) {
30496 return Opcode == VBROADCASTF128rm;
30497}
30498
30499bool isVPSHRDQ(unsigned Opcode) {
30500 switch (Opcode) {
30501 case VPSHRDQZ128rmbi:
30502 case VPSHRDQZ128rmbik:
30503 case VPSHRDQZ128rmbikz:
30504 case VPSHRDQZ128rmi:
30505 case VPSHRDQZ128rmik:
30506 case VPSHRDQZ128rmikz:
30507 case VPSHRDQZ128rri:
30508 case VPSHRDQZ128rrik:
30509 case VPSHRDQZ128rrikz:
30510 case VPSHRDQZ256rmbi:
30511 case VPSHRDQZ256rmbik:
30512 case VPSHRDQZ256rmbikz:
30513 case VPSHRDQZ256rmi:
30514 case VPSHRDQZ256rmik:
30515 case VPSHRDQZ256rmikz:
30516 case VPSHRDQZ256rri:
30517 case VPSHRDQZ256rrik:
30518 case VPSHRDQZ256rrikz:
30519 case VPSHRDQZrmbi:
30520 case VPSHRDQZrmbik:
30521 case VPSHRDQZrmbikz:
30522 case VPSHRDQZrmi:
30523 case VPSHRDQZrmik:
30524 case VPSHRDQZrmikz:
30525 case VPSHRDQZrri:
30526 case VPSHRDQZrrik:
30527 case VPSHRDQZrrikz:
30528 return true;
30529 }
30530 return false;
30531}
30532
30533bool isVAESIMC(unsigned Opcode) {
30534 switch (Opcode) {
30535 case VAESIMCrm:
30536 case VAESIMCrr:
30537 return true;
30538 }
30539 return false;
30540}
30541
30542bool isCOMISD(unsigned Opcode) {
30543 switch (Opcode) {
30544 case COMISDrm:
30545 case COMISDrr:
30546 return true;
30547 }
30548 return false;
30549}
30550
30551bool isVMOVSH(unsigned Opcode) {
30552 switch (Opcode) {
30553 case VMOVSHZmr:
30554 case VMOVSHZmrk:
30555 case VMOVSHZrm:
30556 case VMOVSHZrmk:
30557 case VMOVSHZrmkz:
30558 case VMOVSHZrr:
30559 case VMOVSHZrr_REV:
30560 case VMOVSHZrrk:
30561 case VMOVSHZrrk_REV:
30562 case VMOVSHZrrkz:
30563 case VMOVSHZrrkz_REV:
30564 return true;
30565 }
30566 return false;
30567}
30568
30569bool isPFSUBR(unsigned Opcode) {
30570 switch (Opcode) {
30571 case PFSUBRrm:
30572 case PFSUBRrr:
30573 return true;
30574 }
30575 return false;
30576}
30577
30578bool isRDSSPD(unsigned Opcode) {
30579 return Opcode == RDSSPD;
30580}
30581
30582bool isWAIT(unsigned Opcode) {
30583 return Opcode == WAIT;
30584}
30585
30586bool isVFPCLASSSS(unsigned Opcode) {
30587 switch (Opcode) {
30588 case VFPCLASSSSZmi:
30589 case VFPCLASSSSZmik:
30590 case VFPCLASSSSZri:
30591 case VFPCLASSSSZrik:
30592 return true;
30593 }
30594 return false;
30595}
30596
30597bool isPCMPGTD(unsigned Opcode) {
30598 switch (Opcode) {
30599 case MMX_PCMPGTDrm:
30600 case MMX_PCMPGTDrr:
30601 case PCMPGTDrm:
30602 case PCMPGTDrr:
30603 return true;
30604 }
30605 return false;
30606}
30607
30608bool isVGATHERPF0QPS(unsigned Opcode) {
30609 return Opcode == VGATHERPF0QPSm;
30610}
30611
30612bool isBLENDVPS(unsigned Opcode) {
30613 switch (Opcode) {
30614 case BLENDVPSrm0:
30615 case BLENDVPSrr0:
30616 return true;
30617 }
30618 return false;
30619}
30620
30621bool isVBROADCASTF32X4(unsigned Opcode) {
30622 switch (Opcode) {
30623 case VBROADCASTF32X4Z256rm:
30624 case VBROADCASTF32X4Z256rmk:
30625 case VBROADCASTF32X4Z256rmkz:
30626 case VBROADCASTF32X4Zrm:
30627 case VBROADCASTF32X4Zrmk:
30628 case VBROADCASTF32X4Zrmkz:
30629 return true;
30630 }
30631 return false;
30632}
30633
30634bool isVMOVLPD(unsigned Opcode) {
30635 switch (Opcode) {
30636 case VMOVLPDZ128mr:
30637 case VMOVLPDZ128rm:
30638 case VMOVLPDmr:
30639 case VMOVLPDrm:
30640 return true;
30641 }
30642 return false;
30643}
30644
30645bool isVMOVQ(unsigned Opcode) {
30646 switch (Opcode) {
30647 case VMOV64toPQIZrm:
30648 case VMOV64toPQIZrr:
30649 case VMOV64toPQIrm:
30650 case VMOV64toPQIrr:
30651 case VMOVPQI2QIZmr:
30652 case VMOVPQI2QIZrr:
30653 case VMOVPQI2QImr:
30654 case VMOVPQI2QIrr:
30655 case VMOVPQIto64Zmr:
30656 case VMOVPQIto64Zrr:
30657 case VMOVPQIto64mr:
30658 case VMOVPQIto64rr:
30659 case VMOVQI2PQIZrm:
30660 case VMOVQI2PQIrm:
30661 case VMOVZPQILo2PQIZrr:
30662 case VMOVZPQILo2PQIrr:
30663 return true;
30664 }
30665 return false;
30666}
30667
30668bool isVPMADD52LUQ(unsigned Opcode) {
30669 switch (Opcode) {
30670 case VPMADD52LUQYrm:
30671 case VPMADD52LUQYrr:
30672 case VPMADD52LUQZ128m:
30673 case VPMADD52LUQZ128mb:
30674 case VPMADD52LUQZ128mbk:
30675 case VPMADD52LUQZ128mbkz:
30676 case VPMADD52LUQZ128mk:
30677 case VPMADD52LUQZ128mkz:
30678 case VPMADD52LUQZ128r:
30679 case VPMADD52LUQZ128rk:
30680 case VPMADD52LUQZ128rkz:
30681 case VPMADD52LUQZ256m:
30682 case VPMADD52LUQZ256mb:
30683 case VPMADD52LUQZ256mbk:
30684 case VPMADD52LUQZ256mbkz:
30685 case VPMADD52LUQZ256mk:
30686 case VPMADD52LUQZ256mkz:
30687 case VPMADD52LUQZ256r:
30688 case VPMADD52LUQZ256rk:
30689 case VPMADD52LUQZ256rkz:
30690 case VPMADD52LUQZm:
30691 case VPMADD52LUQZmb:
30692 case VPMADD52LUQZmbk:
30693 case VPMADD52LUQZmbkz:
30694 case VPMADD52LUQZmk:
30695 case VPMADD52LUQZmkz:
30696 case VPMADD52LUQZr:
30697 case VPMADD52LUQZrk:
30698 case VPMADD52LUQZrkz:
30699 case VPMADD52LUQrm:
30700 case VPMADD52LUQrr:
30701 return true;
30702 }
30703 return false;
30704}
30705
30706bool isVMOVDQU(unsigned Opcode) {
30707 switch (Opcode) {
30708 case VMOVDQUYmr:
30709 case VMOVDQUYrm:
30710 case VMOVDQUYrr:
30711 case VMOVDQUYrr_REV:
30712 case VMOVDQUmr:
30713 case VMOVDQUrm:
30714 case VMOVDQUrr:
30715 case VMOVDQUrr_REV:
30716 return true;
30717 }
30718 return false;
30719}
30720
30721bool isAESENC128KL(unsigned Opcode) {
30722 return Opcode == AESENC128KL;
30723}
30724
30725bool isVFMADDSUB231PS(unsigned Opcode) {
30726 switch (Opcode) {
30727 case VFMADDSUB231PSYm:
30728 case VFMADDSUB231PSYr:
30729 case VFMADDSUB231PSZ128m:
30730 case VFMADDSUB231PSZ128mb:
30731 case VFMADDSUB231PSZ128mbk:
30732 case VFMADDSUB231PSZ128mbkz:
30733 case VFMADDSUB231PSZ128mk:
30734 case VFMADDSUB231PSZ128mkz:
30735 case VFMADDSUB231PSZ128r:
30736 case VFMADDSUB231PSZ128rk:
30737 case VFMADDSUB231PSZ128rkz:
30738 case VFMADDSUB231PSZ256m:
30739 case VFMADDSUB231PSZ256mb:
30740 case VFMADDSUB231PSZ256mbk:
30741 case VFMADDSUB231PSZ256mbkz:
30742 case VFMADDSUB231PSZ256mk:
30743 case VFMADDSUB231PSZ256mkz:
30744 case VFMADDSUB231PSZ256r:
30745 case VFMADDSUB231PSZ256rk:
30746 case VFMADDSUB231PSZ256rkz:
30747 case VFMADDSUB231PSZm:
30748 case VFMADDSUB231PSZmb:
30749 case VFMADDSUB231PSZmbk:
30750 case VFMADDSUB231PSZmbkz:
30751 case VFMADDSUB231PSZmk:
30752 case VFMADDSUB231PSZmkz:
30753 case VFMADDSUB231PSZr:
30754 case VFMADDSUB231PSZrb:
30755 case VFMADDSUB231PSZrbk:
30756 case VFMADDSUB231PSZrbkz:
30757 case VFMADDSUB231PSZrk:
30758 case VFMADDSUB231PSZrkz:
30759 case VFMADDSUB231PSm:
30760 case VFMADDSUB231PSr:
30761 return true;
30762 }
30763 return false;
30764}
30765
30766bool isVFNMSUB213PD(unsigned Opcode) {
30767 switch (Opcode) {
30768 case VFNMSUB213PDYm:
30769 case VFNMSUB213PDYr:
30770 case VFNMSUB213PDZ128m:
30771 case VFNMSUB213PDZ128mb:
30772 case VFNMSUB213PDZ128mbk:
30773 case VFNMSUB213PDZ128mbkz:
30774 case VFNMSUB213PDZ128mk:
30775 case VFNMSUB213PDZ128mkz:
30776 case VFNMSUB213PDZ128r:
30777 case VFNMSUB213PDZ128rk:
30778 case VFNMSUB213PDZ128rkz:
30779 case VFNMSUB213PDZ256m:
30780 case VFNMSUB213PDZ256mb:
30781 case VFNMSUB213PDZ256mbk:
30782 case VFNMSUB213PDZ256mbkz:
30783 case VFNMSUB213PDZ256mk:
30784 case VFNMSUB213PDZ256mkz:
30785 case VFNMSUB213PDZ256r:
30786 case VFNMSUB213PDZ256rk:
30787 case VFNMSUB213PDZ256rkz:
30788 case VFNMSUB213PDZm:
30789 case VFNMSUB213PDZmb:
30790 case VFNMSUB213PDZmbk:
30791 case VFNMSUB213PDZmbkz:
30792 case VFNMSUB213PDZmk:
30793 case VFNMSUB213PDZmkz:
30794 case VFNMSUB213PDZr:
30795 case VFNMSUB213PDZrb:
30796 case VFNMSUB213PDZrbk:
30797 case VFNMSUB213PDZrbkz:
30798 case VFNMSUB213PDZrk:
30799 case VFNMSUB213PDZrkz:
30800 case VFNMSUB213PDm:
30801 case VFNMSUB213PDr:
30802 return true;
30803 }
30804 return false;
30805}
30806
30807bool isVPCONFLICTD(unsigned Opcode) {
30808 switch (Opcode) {
30809 case VPCONFLICTDZ128rm:
30810 case VPCONFLICTDZ128rmb:
30811 case VPCONFLICTDZ128rmbk:
30812 case VPCONFLICTDZ128rmbkz:
30813 case VPCONFLICTDZ128rmk:
30814 case VPCONFLICTDZ128rmkz:
30815 case VPCONFLICTDZ128rr:
30816 case VPCONFLICTDZ128rrk:
30817 case VPCONFLICTDZ128rrkz:
30818 case VPCONFLICTDZ256rm:
30819 case VPCONFLICTDZ256rmb:
30820 case VPCONFLICTDZ256rmbk:
30821 case VPCONFLICTDZ256rmbkz:
30822 case VPCONFLICTDZ256rmk:
30823 case VPCONFLICTDZ256rmkz:
30824 case VPCONFLICTDZ256rr:
30825 case VPCONFLICTDZ256rrk:
30826 case VPCONFLICTDZ256rrkz:
30827 case VPCONFLICTDZrm:
30828 case VPCONFLICTDZrmb:
30829 case VPCONFLICTDZrmbk:
30830 case VPCONFLICTDZrmbkz:
30831 case VPCONFLICTDZrmk:
30832 case VPCONFLICTDZrmkz:
30833 case VPCONFLICTDZrr:
30834 case VPCONFLICTDZrrk:
30835 case VPCONFLICTDZrrkz:
30836 return true;
30837 }
30838 return false;
30839}
30840
30841bool isVFMADDSUB213PH(unsigned Opcode) {
30842 switch (Opcode) {
30843 case VFMADDSUB213PHZ128m:
30844 case VFMADDSUB213PHZ128mb:
30845 case VFMADDSUB213PHZ128mbk:
30846 case VFMADDSUB213PHZ128mbkz:
30847 case VFMADDSUB213PHZ128mk:
30848 case VFMADDSUB213PHZ128mkz:
30849 case VFMADDSUB213PHZ128r:
30850 case VFMADDSUB213PHZ128rk:
30851 case VFMADDSUB213PHZ128rkz:
30852 case VFMADDSUB213PHZ256m:
30853 case VFMADDSUB213PHZ256mb:
30854 case VFMADDSUB213PHZ256mbk:
30855 case VFMADDSUB213PHZ256mbkz:
30856 case VFMADDSUB213PHZ256mk:
30857 case VFMADDSUB213PHZ256mkz:
30858 case VFMADDSUB213PHZ256r:
30859 case VFMADDSUB213PHZ256rk:
30860 case VFMADDSUB213PHZ256rkz:
30861 case VFMADDSUB213PHZm:
30862 case VFMADDSUB213PHZmb:
30863 case VFMADDSUB213PHZmbk:
30864 case VFMADDSUB213PHZmbkz:
30865 case VFMADDSUB213PHZmk:
30866 case VFMADDSUB213PHZmkz:
30867 case VFMADDSUB213PHZr:
30868 case VFMADDSUB213PHZrb:
30869 case VFMADDSUB213PHZrbk:
30870 case VFMADDSUB213PHZrbkz:
30871 case VFMADDSUB213PHZrk:
30872 case VFMADDSUB213PHZrkz:
30873 return true;
30874 }
30875 return false;
30876}
30877
30878bool isVPHSUBSW(unsigned Opcode) {
30879 switch (Opcode) {
30880 case VPHSUBSWYrm:
30881 case VPHSUBSWYrr:
30882 case VPHSUBSWrm:
30883 case VPHSUBSWrr:
30884 return true;
30885 }
30886 return false;
30887}
30888
30889bool isPUNPCKHDQ(unsigned Opcode) {
30890 switch (Opcode) {
30891 case MMX_PUNPCKHDQrm:
30892 case MMX_PUNPCKHDQrr:
30893 case PUNPCKHDQrm:
30894 case PUNPCKHDQrr:
30895 return true;
30896 }
30897 return false;
30898}
30899
30900bool isVSHUFI64X2(unsigned Opcode) {
30901 switch (Opcode) {
30902 case VSHUFI64X2Z256rmbi:
30903 case VSHUFI64X2Z256rmbik:
30904 case VSHUFI64X2Z256rmbikz:
30905 case VSHUFI64X2Z256rmi:
30906 case VSHUFI64X2Z256rmik:
30907 case VSHUFI64X2Z256rmikz:
30908 case VSHUFI64X2Z256rri:
30909 case VSHUFI64X2Z256rrik:
30910 case VSHUFI64X2Z256rrikz:
30911 case VSHUFI64X2Zrmbi:
30912 case VSHUFI64X2Zrmbik:
30913 case VSHUFI64X2Zrmbikz:
30914 case VSHUFI64X2Zrmi:
30915 case VSHUFI64X2Zrmik:
30916 case VSHUFI64X2Zrmikz:
30917 case VSHUFI64X2Zrri:
30918 case VSHUFI64X2Zrrik:
30919 case VSHUFI64X2Zrrikz:
30920 return true;
30921 }
30922 return false;
30923}
30924
30925bool isVFMSUBSD(unsigned Opcode) {
30926 switch (Opcode) {
30927 case VFMSUBSD4mr:
30928 case VFMSUBSD4rm:
30929 case VFMSUBSD4rr:
30930 case VFMSUBSD4rr_REV:
30931 return true;
30932 }
30933 return false;
30934}
30935
30936bool isVPORD(unsigned Opcode) {
30937 switch (Opcode) {
30938 case VPORDZ128rm:
30939 case VPORDZ128rmb:
30940 case VPORDZ128rmbk:
30941 case VPORDZ128rmbkz:
30942 case VPORDZ128rmk:
30943 case VPORDZ128rmkz:
30944 case VPORDZ128rr:
30945 case VPORDZ128rrk:
30946 case VPORDZ128rrkz:
30947 case VPORDZ256rm:
30948 case VPORDZ256rmb:
30949 case VPORDZ256rmbk:
30950 case VPORDZ256rmbkz:
30951 case VPORDZ256rmk:
30952 case VPORDZ256rmkz:
30953 case VPORDZ256rr:
30954 case VPORDZ256rrk:
30955 case VPORDZ256rrkz:
30956 case VPORDZrm:
30957 case VPORDZrmb:
30958 case VPORDZrmbk:
30959 case VPORDZrmbkz:
30960 case VPORDZrmk:
30961 case VPORDZrmkz:
30962 case VPORDZrr:
30963 case VPORDZrrk:
30964 case VPORDZrrkz:
30965 return true;
30966 }
30967 return false;
30968}
30969
30970bool isRCPPS(unsigned Opcode) {
30971 switch (Opcode) {
30972 case RCPPSm:
30973 case RCPPSr:
30974 return true;
30975 }
30976 return false;
30977}
30978
30979bool isVEXTRACTI128(unsigned Opcode) {
30980 switch (Opcode) {
30981 case VEXTRACTI128mri:
30982 case VEXTRACTI128rri:
30983 return true;
30984 }
30985 return false;
30986}
30987
30988bool isVCVT2PH2BF8S(unsigned Opcode) {
30989 switch (Opcode) {
30990 case VCVT2PH2BF8SZ128rm:
30991 case VCVT2PH2BF8SZ128rmb:
30992 case VCVT2PH2BF8SZ128rmbk:
30993 case VCVT2PH2BF8SZ128rmbkz:
30994 case VCVT2PH2BF8SZ128rmk:
30995 case VCVT2PH2BF8SZ128rmkz:
30996 case VCVT2PH2BF8SZ128rr:
30997 case VCVT2PH2BF8SZ128rrk:
30998 case VCVT2PH2BF8SZ128rrkz:
30999 case VCVT2PH2BF8SZ256rm:
31000 case VCVT2PH2BF8SZ256rmb:
31001 case VCVT2PH2BF8SZ256rmbk:
31002 case VCVT2PH2BF8SZ256rmbkz:
31003 case VCVT2PH2BF8SZ256rmk:
31004 case VCVT2PH2BF8SZ256rmkz:
31005 case VCVT2PH2BF8SZ256rr:
31006 case VCVT2PH2BF8SZ256rrk:
31007 case VCVT2PH2BF8SZ256rrkz:
31008 case VCVT2PH2BF8SZrm:
31009 case VCVT2PH2BF8SZrmb:
31010 case VCVT2PH2BF8SZrmbk:
31011 case VCVT2PH2BF8SZrmbkz:
31012 case VCVT2PH2BF8SZrmk:
31013 case VCVT2PH2BF8SZrmkz:
31014 case VCVT2PH2BF8SZrr:
31015 case VCVT2PH2BF8SZrrk:
31016 case VCVT2PH2BF8SZrrkz:
31017 return true;
31018 }
31019 return false;
31020}
31021
31022bool isVPSHRDVW(unsigned Opcode) {
31023 switch (Opcode) {
31024 case VPSHRDVWZ128m:
31025 case VPSHRDVWZ128mk:
31026 case VPSHRDVWZ128mkz:
31027 case VPSHRDVWZ128r:
31028 case VPSHRDVWZ128rk:
31029 case VPSHRDVWZ128rkz:
31030 case VPSHRDVWZ256m:
31031 case VPSHRDVWZ256mk:
31032 case VPSHRDVWZ256mkz:
31033 case VPSHRDVWZ256r:
31034 case VPSHRDVWZ256rk:
31035 case VPSHRDVWZ256rkz:
31036 case VPSHRDVWZm:
31037 case VPSHRDVWZmk:
31038 case VPSHRDVWZmkz:
31039 case VPSHRDVWZr:
31040 case VPSHRDVWZrk:
31041 case VPSHRDVWZrkz:
31042 return true;
31043 }
31044 return false;
31045}
31046
31047bool isVUNPCKLPD(unsigned Opcode) {
31048 switch (Opcode) {
31049 case VUNPCKLPDYrm:
31050 case VUNPCKLPDYrr:
31051 case VUNPCKLPDZ128rm:
31052 case VUNPCKLPDZ128rmb:
31053 case VUNPCKLPDZ128rmbk:
31054 case VUNPCKLPDZ128rmbkz:
31055 case VUNPCKLPDZ128rmk:
31056 case VUNPCKLPDZ128rmkz:
31057 case VUNPCKLPDZ128rr:
31058 case VUNPCKLPDZ128rrk:
31059 case VUNPCKLPDZ128rrkz:
31060 case VUNPCKLPDZ256rm:
31061 case VUNPCKLPDZ256rmb:
31062 case VUNPCKLPDZ256rmbk:
31063 case VUNPCKLPDZ256rmbkz:
31064 case VUNPCKLPDZ256rmk:
31065 case VUNPCKLPDZ256rmkz:
31066 case VUNPCKLPDZ256rr:
31067 case VUNPCKLPDZ256rrk:
31068 case VUNPCKLPDZ256rrkz:
31069 case VUNPCKLPDZrm:
31070 case VUNPCKLPDZrmb:
31071 case VUNPCKLPDZrmbk:
31072 case VUNPCKLPDZrmbkz:
31073 case VUNPCKLPDZrmk:
31074 case VUNPCKLPDZrmkz:
31075 case VUNPCKLPDZrr:
31076 case VUNPCKLPDZrrk:
31077 case VUNPCKLPDZrrkz:
31078 case VUNPCKLPDrm:
31079 case VUNPCKLPDrr:
31080 return true;
31081 }
31082 return false;
31083}
31084
31085bool isVPSRAVD(unsigned Opcode) {
31086 switch (Opcode) {
31087 case VPSRAVDYrm:
31088 case VPSRAVDYrr:
31089 case VPSRAVDZ128rm:
31090 case VPSRAVDZ128rmb:
31091 case VPSRAVDZ128rmbk:
31092 case VPSRAVDZ128rmbkz:
31093 case VPSRAVDZ128rmk:
31094 case VPSRAVDZ128rmkz:
31095 case VPSRAVDZ128rr:
31096 case VPSRAVDZ128rrk:
31097 case VPSRAVDZ128rrkz:
31098 case VPSRAVDZ256rm:
31099 case VPSRAVDZ256rmb:
31100 case VPSRAVDZ256rmbk:
31101 case VPSRAVDZ256rmbkz:
31102 case VPSRAVDZ256rmk:
31103 case VPSRAVDZ256rmkz:
31104 case VPSRAVDZ256rr:
31105 case VPSRAVDZ256rrk:
31106 case VPSRAVDZ256rrkz:
31107 case VPSRAVDZrm:
31108 case VPSRAVDZrmb:
31109 case VPSRAVDZrmbk:
31110 case VPSRAVDZrmbkz:
31111 case VPSRAVDZrmk:
31112 case VPSRAVDZrmkz:
31113 case VPSRAVDZrr:
31114 case VPSRAVDZrrk:
31115 case VPSRAVDZrrkz:
31116 case VPSRAVDrm:
31117 case VPSRAVDrr:
31118 return true;
31119 }
31120 return false;
31121}
31122
31123bool isVMULSH(unsigned Opcode) {
31124 switch (Opcode) {
31125 case VMULSHZrm_Int:
31126 case VMULSHZrmk_Int:
31127 case VMULSHZrmkz_Int:
31128 case VMULSHZrr_Int:
31129 case VMULSHZrrb_Int:
31130 case VMULSHZrrbk_Int:
31131 case VMULSHZrrbkz_Int:
31132 case VMULSHZrrk_Int:
31133 case VMULSHZrrkz_Int:
31134 return true;
31135 }
31136 return false;
31137}
31138
31139bool isMOVNTSS(unsigned Opcode) {
31140 return Opcode == MOVNTSS;
31141}
31142
31143bool isSTI(unsigned Opcode) {
31144 return Opcode == STI;
31145}
31146
31147bool isVSM4RNDS4(unsigned Opcode) {
31148 switch (Opcode) {
31149 case VSM4RNDS4Yrm:
31150 case VSM4RNDS4Yrr:
31151 case VSM4RNDS4Z128rm:
31152 case VSM4RNDS4Z128rr:
31153 case VSM4RNDS4Z256rm:
31154 case VSM4RNDS4Z256rr:
31155 case VSM4RNDS4Zrm:
31156 case VSM4RNDS4Zrr:
31157 case VSM4RNDS4rm:
31158 case VSM4RNDS4rr:
31159 return true;
31160 }
31161 return false;
31162}
31163
31164bool isVMCLEAR(unsigned Opcode) {
31165 return Opcode == VMCLEARm;
31166}
31167
31168bool isVPMADD52HUQ(unsigned Opcode) {
31169 switch (Opcode) {
31170 case VPMADD52HUQYrm:
31171 case VPMADD52HUQYrr:
31172 case VPMADD52HUQZ128m:
31173 case VPMADD52HUQZ128mb:
31174 case VPMADD52HUQZ128mbk:
31175 case VPMADD52HUQZ128mbkz:
31176 case VPMADD52HUQZ128mk:
31177 case VPMADD52HUQZ128mkz:
31178 case VPMADD52HUQZ128r:
31179 case VPMADD52HUQZ128rk:
31180 case VPMADD52HUQZ128rkz:
31181 case VPMADD52HUQZ256m:
31182 case VPMADD52HUQZ256mb:
31183 case VPMADD52HUQZ256mbk:
31184 case VPMADD52HUQZ256mbkz:
31185 case VPMADD52HUQZ256mk:
31186 case VPMADD52HUQZ256mkz:
31187 case VPMADD52HUQZ256r:
31188 case VPMADD52HUQZ256rk:
31189 case VPMADD52HUQZ256rkz:
31190 case VPMADD52HUQZm:
31191 case VPMADD52HUQZmb:
31192 case VPMADD52HUQZmbk:
31193 case VPMADD52HUQZmbkz:
31194 case VPMADD52HUQZmk:
31195 case VPMADD52HUQZmkz:
31196 case VPMADD52HUQZr:
31197 case VPMADD52HUQZrk:
31198 case VPMADD52HUQZrkz:
31199 case VPMADD52HUQrm:
31200 case VPMADD52HUQrr:
31201 return true;
31202 }
31203 return false;
31204}
31205
31206bool isLIDT(unsigned Opcode) {
31207 return Opcode == LIDT64m;
31208}
31209
31210bool isPUSH2(unsigned Opcode) {
31211 return Opcode == PUSH2;
31212}
31213
31214bool isRDPKRU(unsigned Opcode) {
31215 return Opcode == RDPKRUr;
31216}
31217
31218bool isVCVTPS2IUBS(unsigned Opcode) {
31219 switch (Opcode) {
31220 case VCVTPS2IUBSZ128rm:
31221 case VCVTPS2IUBSZ128rmb:
31222 case VCVTPS2IUBSZ128rmbk:
31223 case VCVTPS2IUBSZ128rmbkz:
31224 case VCVTPS2IUBSZ128rmk:
31225 case VCVTPS2IUBSZ128rmkz:
31226 case VCVTPS2IUBSZ128rr:
31227 case VCVTPS2IUBSZ128rrk:
31228 case VCVTPS2IUBSZ128rrkz:
31229 case VCVTPS2IUBSZ256rm:
31230 case VCVTPS2IUBSZ256rmb:
31231 case VCVTPS2IUBSZ256rmbk:
31232 case VCVTPS2IUBSZ256rmbkz:
31233 case VCVTPS2IUBSZ256rmk:
31234 case VCVTPS2IUBSZ256rmkz:
31235 case VCVTPS2IUBSZ256rr:
31236 case VCVTPS2IUBSZ256rrk:
31237 case VCVTPS2IUBSZ256rrkz:
31238 case VCVTPS2IUBSZrm:
31239 case VCVTPS2IUBSZrmb:
31240 case VCVTPS2IUBSZrmbk:
31241 case VCVTPS2IUBSZrmbkz:
31242 case VCVTPS2IUBSZrmk:
31243 case VCVTPS2IUBSZrmkz:
31244 case VCVTPS2IUBSZrr:
31245 case VCVTPS2IUBSZrrb:
31246 case VCVTPS2IUBSZrrbk:
31247 case VCVTPS2IUBSZrrbkz:
31248 case VCVTPS2IUBSZrrk:
31249 case VCVTPS2IUBSZrrkz:
31250 return true;
31251 }
31252 return false;
31253}
31254
31255bool isXSAVES64(unsigned Opcode) {
31256 return Opcode == XSAVES64;
31257}
31258
31259bool isVPCMPB(unsigned Opcode) {
31260 switch (Opcode) {
31261 case VPCMPBZ128rmi:
31262 case VPCMPBZ128rmik:
31263 case VPCMPBZ128rri:
31264 case VPCMPBZ128rrik:
31265 case VPCMPBZ256rmi:
31266 case VPCMPBZ256rmik:
31267 case VPCMPBZ256rri:
31268 case VPCMPBZ256rrik:
31269 case VPCMPBZrmi:
31270 case VPCMPBZrmik:
31271 case VPCMPBZrri:
31272 case VPCMPBZrrik:
31273 return true;
31274 }
31275 return false;
31276}
31277
31278bool isVFMSUB231BF16(unsigned Opcode) {
31279 switch (Opcode) {
31280 case VFMSUB231BF16Z128m:
31281 case VFMSUB231BF16Z128mb:
31282 case VFMSUB231BF16Z128mbk:
31283 case VFMSUB231BF16Z128mbkz:
31284 case VFMSUB231BF16Z128mk:
31285 case VFMSUB231BF16Z128mkz:
31286 case VFMSUB231BF16Z128r:
31287 case VFMSUB231BF16Z128rk:
31288 case VFMSUB231BF16Z128rkz:
31289 case VFMSUB231BF16Z256m:
31290 case VFMSUB231BF16Z256mb:
31291 case VFMSUB231BF16Z256mbk:
31292 case VFMSUB231BF16Z256mbkz:
31293 case VFMSUB231BF16Z256mk:
31294 case VFMSUB231BF16Z256mkz:
31295 case VFMSUB231BF16Z256r:
31296 case VFMSUB231BF16Z256rk:
31297 case VFMSUB231BF16Z256rkz:
31298 case VFMSUB231BF16Zm:
31299 case VFMSUB231BF16Zmb:
31300 case VFMSUB231BF16Zmbk:
31301 case VFMSUB231BF16Zmbkz:
31302 case VFMSUB231BF16Zmk:
31303 case VFMSUB231BF16Zmkz:
31304 case VFMSUB231BF16Zr:
31305 case VFMSUB231BF16Zrk:
31306 case VFMSUB231BF16Zrkz:
31307 return true;
31308 }
31309 return false;
31310}
31311
31312bool isFINCSTP(unsigned Opcode) {
31313 return Opcode == FINCSTP;
31314}
31315
31316bool isKORQ(unsigned Opcode) {
31317 return Opcode == KORQkk;
31318}
31319
31320bool isRDPMC(unsigned Opcode) {
31321 return Opcode == RDPMC;
31322}
31323
31324bool isVEXTRACTF128(unsigned Opcode) {
31325 switch (Opcode) {
31326 case VEXTRACTF128mri:
31327 case VEXTRACTF128rri:
31328 return true;
31329 }
31330 return false;
31331}
31332
31333bool isMOVMSKPD(unsigned Opcode) {
31334 return Opcode == MOVMSKPDrr;
31335}
31336
31337bool isVFMSUB231SH(unsigned Opcode) {
31338 switch (Opcode) {
31339 case VFMSUB231SHZm_Int:
31340 case VFMSUB231SHZmk_Int:
31341 case VFMSUB231SHZmkz_Int:
31342 case VFMSUB231SHZr_Int:
31343 case VFMSUB231SHZrb_Int:
31344 case VFMSUB231SHZrbk_Int:
31345 case VFMSUB231SHZrbkz_Int:
31346 case VFMSUB231SHZrk_Int:
31347 case VFMSUB231SHZrkz_Int:
31348 return true;
31349 }
31350 return false;
31351}
31352
31353bool isVPSHLB(unsigned Opcode) {
31354 switch (Opcode) {
31355 case VPSHLBmr:
31356 case VPSHLBrm:
31357 case VPSHLBrr:
31358 case VPSHLBrr_REV:
31359 return true;
31360 }
31361 return false;
31362}
31363
31364bool isXCRYPTCBC(unsigned Opcode) {
31365 return Opcode == XCRYPTCBC;
31366}
31367
31368bool isSHL(unsigned Opcode) {
31369 switch (Opcode) {
31370 case SHL16m1:
31371 case SHL16m1_EVEX:
31372 case SHL16m1_ND:
31373 case SHL16m1_NF:
31374 case SHL16m1_NF_ND:
31375 case SHL16mCL:
31376 case SHL16mCL_EVEX:
31377 case SHL16mCL_ND:
31378 case SHL16mCL_NF:
31379 case SHL16mCL_NF_ND:
31380 case SHL16mi:
31381 case SHL16mi_EVEX:
31382 case SHL16mi_ND:
31383 case SHL16mi_NF:
31384 case SHL16mi_NF_ND:
31385 case SHL16r1:
31386 case SHL16r1_EVEX:
31387 case SHL16r1_ND:
31388 case SHL16r1_NF:
31389 case SHL16r1_NF_ND:
31390 case SHL16rCL:
31391 case SHL16rCL_EVEX:
31392 case SHL16rCL_ND:
31393 case SHL16rCL_NF:
31394 case SHL16rCL_NF_ND:
31395 case SHL16ri:
31396 case SHL16ri_EVEX:
31397 case SHL16ri_ND:
31398 case SHL16ri_NF:
31399 case SHL16ri_NF_ND:
31400 case SHL32m1:
31401 case SHL32m1_EVEX:
31402 case SHL32m1_ND:
31403 case SHL32m1_NF:
31404 case SHL32m1_NF_ND:
31405 case SHL32mCL:
31406 case SHL32mCL_EVEX:
31407 case SHL32mCL_ND:
31408 case SHL32mCL_NF:
31409 case SHL32mCL_NF_ND:
31410 case SHL32mi:
31411 case SHL32mi_EVEX:
31412 case SHL32mi_ND:
31413 case SHL32mi_NF:
31414 case SHL32mi_NF_ND:
31415 case SHL32r1:
31416 case SHL32r1_EVEX:
31417 case SHL32r1_ND:
31418 case SHL32r1_NF:
31419 case SHL32r1_NF_ND:
31420 case SHL32rCL:
31421 case SHL32rCL_EVEX:
31422 case SHL32rCL_ND:
31423 case SHL32rCL_NF:
31424 case SHL32rCL_NF_ND:
31425 case SHL32ri:
31426 case SHL32ri_EVEX:
31427 case SHL32ri_ND:
31428 case SHL32ri_NF:
31429 case SHL32ri_NF_ND:
31430 case SHL64m1:
31431 case SHL64m1_EVEX:
31432 case SHL64m1_ND:
31433 case SHL64m1_NF:
31434 case SHL64m1_NF_ND:
31435 case SHL64mCL:
31436 case SHL64mCL_EVEX:
31437 case SHL64mCL_ND:
31438 case SHL64mCL_NF:
31439 case SHL64mCL_NF_ND:
31440 case SHL64mi:
31441 case SHL64mi_EVEX:
31442 case SHL64mi_ND:
31443 case SHL64mi_NF:
31444 case SHL64mi_NF_ND:
31445 case SHL64r1:
31446 case SHL64r1_EVEX:
31447 case SHL64r1_ND:
31448 case SHL64r1_NF:
31449 case SHL64r1_NF_ND:
31450 case SHL64rCL:
31451 case SHL64rCL_EVEX:
31452 case SHL64rCL_ND:
31453 case SHL64rCL_NF:
31454 case SHL64rCL_NF_ND:
31455 case SHL64ri:
31456 case SHL64ri_EVEX:
31457 case SHL64ri_ND:
31458 case SHL64ri_NF:
31459 case SHL64ri_NF_ND:
31460 case SHL8m1:
31461 case SHL8m1_EVEX:
31462 case SHL8m1_ND:
31463 case SHL8m1_NF:
31464 case SHL8m1_NF_ND:
31465 case SHL8mCL:
31466 case SHL8mCL_EVEX:
31467 case SHL8mCL_ND:
31468 case SHL8mCL_NF:
31469 case SHL8mCL_NF_ND:
31470 case SHL8mi:
31471 case SHL8mi_EVEX:
31472 case SHL8mi_ND:
31473 case SHL8mi_NF:
31474 case SHL8mi_NF_ND:
31475 case SHL8r1:
31476 case SHL8r1_EVEX:
31477 case SHL8r1_ND:
31478 case SHL8r1_NF:
31479 case SHL8r1_NF_ND:
31480 case SHL8rCL:
31481 case SHL8rCL_EVEX:
31482 case SHL8rCL_ND:
31483 case SHL8rCL_NF:
31484 case SHL8rCL_NF_ND:
31485 case SHL8ri:
31486 case SHL8ri_EVEX:
31487 case SHL8ri_ND:
31488 case SHL8ri_NF:
31489 case SHL8ri_NF_ND:
31490 return true;
31491 }
31492 return false;
31493}
31494
31495bool isAXOR(unsigned Opcode) {
31496 switch (Opcode) {
31497 case AXOR32mr:
31498 case AXOR32mr_EVEX:
31499 case AXOR64mr:
31500 case AXOR64mr_EVEX:
31501 return true;
31502 }
31503 return false;
31504}
31505
31506bool isVINSERTI64X2(unsigned Opcode) {
31507 switch (Opcode) {
31508 case VINSERTI64X2Z256rmi:
31509 case VINSERTI64X2Z256rmik:
31510 case VINSERTI64X2Z256rmikz:
31511 case VINSERTI64X2Z256rri:
31512 case VINSERTI64X2Z256rrik:
31513 case VINSERTI64X2Z256rrikz:
31514 case VINSERTI64X2Zrmi:
31515 case VINSERTI64X2Zrmik:
31516 case VINSERTI64X2Zrmikz:
31517 case VINSERTI64X2Zrri:
31518 case VINSERTI64X2Zrrik:
31519 case VINSERTI64X2Zrrikz:
31520 return true;
31521 }
31522 return false;
31523}
31524
31525bool isSYSRETQ(unsigned Opcode) {
31526 return Opcode == SYSRET64;
31527}
31528
31529bool isVSCATTERPF0QPD(unsigned Opcode) {
31530 return Opcode == VSCATTERPF0QPDm;
31531}
31532
31533bool isVFMSUB213SH(unsigned Opcode) {
31534 switch (Opcode) {
31535 case VFMSUB213SHZm_Int:
31536 case VFMSUB213SHZmk_Int:
31537 case VFMSUB213SHZmkz_Int:
31538 case VFMSUB213SHZr_Int:
31539 case VFMSUB213SHZrb_Int:
31540 case VFMSUB213SHZrbk_Int:
31541 case VFMSUB213SHZrbkz_Int:
31542 case VFMSUB213SHZrk_Int:
31543 case VFMSUB213SHZrkz_Int:
31544 return true;
31545 }
31546 return false;
31547}
31548
31549bool isVPMOVQW(unsigned Opcode) {
31550 switch (Opcode) {
31551 case VPMOVQWZ128mr:
31552 case VPMOVQWZ128mrk:
31553 case VPMOVQWZ128rr:
31554 case VPMOVQWZ128rrk:
31555 case VPMOVQWZ128rrkz:
31556 case VPMOVQWZ256mr:
31557 case VPMOVQWZ256mrk:
31558 case VPMOVQWZ256rr:
31559 case VPMOVQWZ256rrk:
31560 case VPMOVQWZ256rrkz:
31561 case VPMOVQWZmr:
31562 case VPMOVQWZmrk:
31563 case VPMOVQWZrr:
31564 case VPMOVQWZrrk:
31565 case VPMOVQWZrrkz:
31566 return true;
31567 }
31568 return false;
31569}
31570
31571bool isVREDUCEPD(unsigned Opcode) {
31572 switch (Opcode) {
31573 case VREDUCEPDZ128rmbi:
31574 case VREDUCEPDZ128rmbik:
31575 case VREDUCEPDZ128rmbikz:
31576 case VREDUCEPDZ128rmi:
31577 case VREDUCEPDZ128rmik:
31578 case VREDUCEPDZ128rmikz:
31579 case VREDUCEPDZ128rri:
31580 case VREDUCEPDZ128rrik:
31581 case VREDUCEPDZ128rrikz:
31582 case VREDUCEPDZ256rmbi:
31583 case VREDUCEPDZ256rmbik:
31584 case VREDUCEPDZ256rmbikz:
31585 case VREDUCEPDZ256rmi:
31586 case VREDUCEPDZ256rmik:
31587 case VREDUCEPDZ256rmikz:
31588 case VREDUCEPDZ256rri:
31589 case VREDUCEPDZ256rrik:
31590 case VREDUCEPDZ256rrikz:
31591 case VREDUCEPDZrmbi:
31592 case VREDUCEPDZrmbik:
31593 case VREDUCEPDZrmbikz:
31594 case VREDUCEPDZrmi:
31595 case VREDUCEPDZrmik:
31596 case VREDUCEPDZrmikz:
31597 case VREDUCEPDZrri:
31598 case VREDUCEPDZrrib:
31599 case VREDUCEPDZrribk:
31600 case VREDUCEPDZrribkz:
31601 case VREDUCEPDZrrik:
31602 case VREDUCEPDZrrikz:
31603 return true;
31604 }
31605 return false;
31606}
31607
31608bool isNOT(unsigned Opcode) {
31609 switch (Opcode) {
31610 case NOT16m:
31611 case NOT16m_EVEX:
31612 case NOT16m_ND:
31613 case NOT16r:
31614 case NOT16r_EVEX:
31615 case NOT16r_ND:
31616 case NOT32m:
31617 case NOT32m_EVEX:
31618 case NOT32m_ND:
31619 case NOT32r:
31620 case NOT32r_EVEX:
31621 case NOT32r_ND:
31622 case NOT64m:
31623 case NOT64m_EVEX:
31624 case NOT64m_ND:
31625 case NOT64r:
31626 case NOT64r_EVEX:
31627 case NOT64r_ND:
31628 case NOT8m:
31629 case NOT8m_EVEX:
31630 case NOT8m_ND:
31631 case NOT8r:
31632 case NOT8r_EVEX:
31633 case NOT8r_ND:
31634 return true;
31635 }
31636 return false;
31637}
31638
31639bool isLWPINS(unsigned Opcode) {
31640 switch (Opcode) {
31641 case LWPINS32rmi:
31642 case LWPINS32rri:
31643 case LWPINS64rmi:
31644 case LWPINS64rri:
31645 return true;
31646 }
31647 return false;
31648}
31649
31650bool isVSCATTERDPS(unsigned Opcode) {
31651 switch (Opcode) {
31652 case VSCATTERDPSZ128mr:
31653 case VSCATTERDPSZ256mr:
31654 case VSCATTERDPSZmr:
31655 return true;
31656 }
31657 return false;
31658}
31659
31660bool isVPMOVM2W(unsigned Opcode) {
31661 switch (Opcode) {
31662 case VPMOVM2WZ128rk:
31663 case VPMOVM2WZ256rk:
31664 case VPMOVM2WZrk:
31665 return true;
31666 }
31667 return false;
31668}
31669
31670bool isVFNMADD132PS(unsigned Opcode) {
31671 switch (Opcode) {
31672 case VFNMADD132PSYm:
31673 case VFNMADD132PSYr:
31674 case VFNMADD132PSZ128m:
31675 case VFNMADD132PSZ128mb:
31676 case VFNMADD132PSZ128mbk:
31677 case VFNMADD132PSZ128mbkz:
31678 case VFNMADD132PSZ128mk:
31679 case VFNMADD132PSZ128mkz:
31680 case VFNMADD132PSZ128r:
31681 case VFNMADD132PSZ128rk:
31682 case VFNMADD132PSZ128rkz:
31683 case VFNMADD132PSZ256m:
31684 case VFNMADD132PSZ256mb:
31685 case VFNMADD132PSZ256mbk:
31686 case VFNMADD132PSZ256mbkz:
31687 case VFNMADD132PSZ256mk:
31688 case VFNMADD132PSZ256mkz:
31689 case VFNMADD132PSZ256r:
31690 case VFNMADD132PSZ256rk:
31691 case VFNMADD132PSZ256rkz:
31692 case VFNMADD132PSZm:
31693 case VFNMADD132PSZmb:
31694 case VFNMADD132PSZmbk:
31695 case VFNMADD132PSZmbkz:
31696 case VFNMADD132PSZmk:
31697 case VFNMADD132PSZmkz:
31698 case VFNMADD132PSZr:
31699 case VFNMADD132PSZrb:
31700 case VFNMADD132PSZrbk:
31701 case VFNMADD132PSZrbkz:
31702 case VFNMADD132PSZrk:
31703 case VFNMADD132PSZrkz:
31704 case VFNMADD132PSm:
31705 case VFNMADD132PSr:
31706 return true;
31707 }
31708 return false;
31709}
31710
31711bool isMOVNTPS(unsigned Opcode) {
31712 return Opcode == MOVNTPSmr;
31713}
31714
31715bool isVRSQRTSS(unsigned Opcode) {
31716 switch (Opcode) {
31717 case VRSQRTSSm_Int:
31718 case VRSQRTSSr_Int:
31719 return true;
31720 }
31721 return false;
31722}
31723
31724bool isKMOVB(unsigned Opcode) {
31725 switch (Opcode) {
31726 case KMOVBkk:
31727 case KMOVBkk_EVEX:
31728 case KMOVBkm:
31729 case KMOVBkm_EVEX:
31730 case KMOVBkr:
31731 case KMOVBkr_EVEX:
31732 case KMOVBmk:
31733 case KMOVBmk_EVEX:
31734 case KMOVBrk:
31735 case KMOVBrk_EVEX:
31736 return true;
31737 }
31738 return false;
31739}
31740
31741bool isCVTSD2SS(unsigned Opcode) {
31742 switch (Opcode) {
31743 case CVTSD2SSrm_Int:
31744 case CVTSD2SSrr_Int:
31745 return true;
31746 }
31747 return false;
31748}
31749
31750bool isVBROADCASTF64X2(unsigned Opcode) {
31751 switch (Opcode) {
31752 case VBROADCASTF64X2Z256rm:
31753 case VBROADCASTF64X2Z256rmk:
31754 case VBROADCASTF64X2Z256rmkz:
31755 case VBROADCASTF64X2Zrm:
31756 case VBROADCASTF64X2Zrmk:
31757 case VBROADCASTF64X2Zrmkz:
31758 return true;
31759 }
31760 return false;
31761}
31762
31763bool isVDIVBF16(unsigned Opcode) {
31764 switch (Opcode) {
31765 case VDIVBF16Z128rm:
31766 case VDIVBF16Z128rmb:
31767 case VDIVBF16Z128rmbk:
31768 case VDIVBF16Z128rmbkz:
31769 case VDIVBF16Z128rmk:
31770 case VDIVBF16Z128rmkz:
31771 case VDIVBF16Z128rr:
31772 case VDIVBF16Z128rrk:
31773 case VDIVBF16Z128rrkz:
31774 case VDIVBF16Z256rm:
31775 case VDIVBF16Z256rmb:
31776 case VDIVBF16Z256rmbk:
31777 case VDIVBF16Z256rmbkz:
31778 case VDIVBF16Z256rmk:
31779 case VDIVBF16Z256rmkz:
31780 case VDIVBF16Z256rr:
31781 case VDIVBF16Z256rrk:
31782 case VDIVBF16Z256rrkz:
31783 case VDIVBF16Zrm:
31784 case VDIVBF16Zrmb:
31785 case VDIVBF16Zrmbk:
31786 case VDIVBF16Zrmbkz:
31787 case VDIVBF16Zrmk:
31788 case VDIVBF16Zrmkz:
31789 case VDIVBF16Zrr:
31790 case VDIVBF16Zrrk:
31791 case VDIVBF16Zrrkz:
31792 return true;
31793 }
31794 return false;
31795}
31796
31797bool isMOVNTPD(unsigned Opcode) {
31798 return Opcode == MOVNTPDmr;
31799}
31800
31801bool isMAXSD(unsigned Opcode) {
31802 switch (Opcode) {
31803 case MAXSDrm_Int:
31804 case MAXSDrr_Int:
31805 return true;
31806 }
31807 return false;
31808}
31809
31810bool isCMPPD(unsigned Opcode) {
31811 switch (Opcode) {
31812 case CMPPDrmi:
31813 case CMPPDrri:
31814 return true;
31815 }
31816 return false;
31817}
31818
31819bool isVPCMPESTRM(unsigned Opcode) {
31820 switch (Opcode) {
31821 case VPCMPESTRMrmi:
31822 case VPCMPESTRMrri:
31823 return true;
31824 }
31825 return false;
31826}
31827
31828bool isVFMSUB132PS(unsigned Opcode) {
31829 switch (Opcode) {
31830 case VFMSUB132PSYm:
31831 case VFMSUB132PSYr:
31832 case VFMSUB132PSZ128m:
31833 case VFMSUB132PSZ128mb:
31834 case VFMSUB132PSZ128mbk:
31835 case VFMSUB132PSZ128mbkz:
31836 case VFMSUB132PSZ128mk:
31837 case VFMSUB132PSZ128mkz:
31838 case VFMSUB132PSZ128r:
31839 case VFMSUB132PSZ128rk:
31840 case VFMSUB132PSZ128rkz:
31841 case VFMSUB132PSZ256m:
31842 case VFMSUB132PSZ256mb:
31843 case VFMSUB132PSZ256mbk:
31844 case VFMSUB132PSZ256mbkz:
31845 case VFMSUB132PSZ256mk:
31846 case VFMSUB132PSZ256mkz:
31847 case VFMSUB132PSZ256r:
31848 case VFMSUB132PSZ256rk:
31849 case VFMSUB132PSZ256rkz:
31850 case VFMSUB132PSZm:
31851 case VFMSUB132PSZmb:
31852 case VFMSUB132PSZmbk:
31853 case VFMSUB132PSZmbkz:
31854 case VFMSUB132PSZmk:
31855 case VFMSUB132PSZmkz:
31856 case VFMSUB132PSZr:
31857 case VFMSUB132PSZrb:
31858 case VFMSUB132PSZrbk:
31859 case VFMSUB132PSZrbkz:
31860 case VFMSUB132PSZrk:
31861 case VFMSUB132PSZrkz:
31862 case VFMSUB132PSm:
31863 case VFMSUB132PSr:
31864 return true;
31865 }
31866 return false;
31867}
31868
31869bool isVCOMISH(unsigned Opcode) {
31870 switch (Opcode) {
31871 case VCOMISHZrm:
31872 case VCOMISHZrr:
31873 case VCOMISHZrrb:
31874 return true;
31875 }
31876 return false;
31877}
31878
31879bool isF2XM1(unsigned Opcode) {
31880 return Opcode == F2XM1;
31881}
31882
31883bool isSQRTPD(unsigned Opcode) {
31884 switch (Opcode) {
31885 case SQRTPDm:
31886 case SQRTPDr:
31887 return true;
31888 }
31889 return false;
31890}
31891
31892bool isVFMSUBADDPS(unsigned Opcode) {
31893 switch (Opcode) {
31894 case VFMSUBADDPS4Ymr:
31895 case VFMSUBADDPS4Yrm:
31896 case VFMSUBADDPS4Yrr:
31897 case VFMSUBADDPS4Yrr_REV:
31898 case VFMSUBADDPS4mr:
31899 case VFMSUBADDPS4rm:
31900 case VFMSUBADDPS4rr:
31901 case VFMSUBADDPS4rr_REV:
31902 return true;
31903 }
31904 return false;
31905}
31906
31907bool isFXTRACT(unsigned Opcode) {
31908 return Opcode == FXTRACT;
31909}
31910
31911bool isVP4DPWSSD(unsigned Opcode) {
31912 switch (Opcode) {
31913 case VP4DPWSSDrm:
31914 case VP4DPWSSDrmk:
31915 case VP4DPWSSDrmkz:
31916 return true;
31917 }
31918 return false;
31919}
31920
31921bool isTDPBHF8PS(unsigned Opcode) {
31922 return Opcode == TDPBHF8PS;
31923}
31924
31925bool isVFMSUBADDPD(unsigned Opcode) {
31926 switch (Opcode) {
31927 case VFMSUBADDPD4Ymr:
31928 case VFMSUBADDPD4Yrm:
31929 case VFMSUBADDPD4Yrr:
31930 case VFMSUBADDPD4Yrr_REV:
31931 case VFMSUBADDPD4mr:
31932 case VFMSUBADDPD4rm:
31933 case VFMSUBADDPD4rr:
31934 case VFMSUBADDPD4rr_REV:
31935 return true;
31936 }
31937 return false;
31938}
31939
31940bool isVBCSTNEBF162PS(unsigned Opcode) {
31941 switch (Opcode) {
31942 case VBCSTNEBF162PSYrm:
31943 case VBCSTNEBF162PSrm:
31944 return true;
31945 }
31946 return false;
31947}
31948
31949bool isVPGATHERQQ(unsigned Opcode) {
31950 switch (Opcode) {
31951 case VPGATHERQQYrm:
31952 case VPGATHERQQZ128rm:
31953 case VPGATHERQQZ256rm:
31954 case VPGATHERQQZrm:
31955 case VPGATHERQQrm:
31956 return true;
31957 }
31958 return false;
31959}
31960
31961bool isPCMPEQB(unsigned Opcode) {
31962 switch (Opcode) {
31963 case MMX_PCMPEQBrm:
31964 case MMX_PCMPEQBrr:
31965 case PCMPEQBrm:
31966 case PCMPEQBrr:
31967 return true;
31968 }
31969 return false;
31970}
31971
31972bool isTILESTORED(unsigned Opcode) {
31973 switch (Opcode) {
31974 case TILESTORED:
31975 case TILESTORED_EVEX:
31976 return true;
31977 }
31978 return false;
31979}
31980
31981bool isBLSMSK(unsigned Opcode) {
31982 switch (Opcode) {
31983 case BLSMSK32rm:
31984 case BLSMSK32rm_EVEX:
31985 case BLSMSK32rm_NF:
31986 case BLSMSK32rr:
31987 case BLSMSK32rr_EVEX:
31988 case BLSMSK32rr_NF:
31989 case BLSMSK64rm:
31990 case BLSMSK64rm_EVEX:
31991 case BLSMSK64rm_NF:
31992 case BLSMSK64rr:
31993 case BLSMSK64rr_EVEX:
31994 case BLSMSK64rr_NF:
31995 return true;
31996 }
31997 return false;
31998}
31999
32000bool isVCVTTPS2DQ(unsigned Opcode) {
32001 switch (Opcode) {
32002 case VCVTTPS2DQYrm:
32003 case VCVTTPS2DQYrr:
32004 case VCVTTPS2DQZ128rm:
32005 case VCVTTPS2DQZ128rmb:
32006 case VCVTTPS2DQZ128rmbk:
32007 case VCVTTPS2DQZ128rmbkz:
32008 case VCVTTPS2DQZ128rmk:
32009 case VCVTTPS2DQZ128rmkz:
32010 case VCVTTPS2DQZ128rr:
32011 case VCVTTPS2DQZ128rrk:
32012 case VCVTTPS2DQZ128rrkz:
32013 case VCVTTPS2DQZ256rm:
32014 case VCVTTPS2DQZ256rmb:
32015 case VCVTTPS2DQZ256rmbk:
32016 case VCVTTPS2DQZ256rmbkz:
32017 case VCVTTPS2DQZ256rmk:
32018 case VCVTTPS2DQZ256rmkz:
32019 case VCVTTPS2DQZ256rr:
32020 case VCVTTPS2DQZ256rrk:
32021 case VCVTTPS2DQZ256rrkz:
32022 case VCVTTPS2DQZrm:
32023 case VCVTTPS2DQZrmb:
32024 case VCVTTPS2DQZrmbk:
32025 case VCVTTPS2DQZrmbkz:
32026 case VCVTTPS2DQZrmk:
32027 case VCVTTPS2DQZrmkz:
32028 case VCVTTPS2DQZrr:
32029 case VCVTTPS2DQZrrb:
32030 case VCVTTPS2DQZrrbk:
32031 case VCVTTPS2DQZrrbkz:
32032 case VCVTTPS2DQZrrk:
32033 case VCVTTPS2DQZrrkz:
32034 case VCVTTPS2DQrm:
32035 case VCVTTPS2DQrr:
32036 return true;
32037 }
32038 return false;
32039}
32040
32041bool isVFPCLASSBF16(unsigned Opcode) {
32042 switch (Opcode) {
32043 case VFPCLASSBF16Z128mbi:
32044 case VFPCLASSBF16Z128mbik:
32045 case VFPCLASSBF16Z128mi:
32046 case VFPCLASSBF16Z128mik:
32047 case VFPCLASSBF16Z128ri:
32048 case VFPCLASSBF16Z128rik:
32049 case VFPCLASSBF16Z256mbi:
32050 case VFPCLASSBF16Z256mbik:
32051 case VFPCLASSBF16Z256mi:
32052 case VFPCLASSBF16Z256mik:
32053 case VFPCLASSBF16Z256ri:
32054 case VFPCLASSBF16Z256rik:
32055 case VFPCLASSBF16Zmbi:
32056 case VFPCLASSBF16Zmbik:
32057 case VFPCLASSBF16Zmi:
32058 case VFPCLASSBF16Zmik:
32059 case VFPCLASSBF16Zri:
32060 case VFPCLASSBF16Zrik:
32061 return true;
32062 }
32063 return false;
32064}
32065
32066bool isVRNDSCALEPD(unsigned Opcode) {
32067 switch (Opcode) {
32068 case VRNDSCALEPDZ128rmbi:
32069 case VRNDSCALEPDZ128rmbik:
32070 case VRNDSCALEPDZ128rmbikz:
32071 case VRNDSCALEPDZ128rmi:
32072 case VRNDSCALEPDZ128rmik:
32073 case VRNDSCALEPDZ128rmikz:
32074 case VRNDSCALEPDZ128rri:
32075 case VRNDSCALEPDZ128rrik:
32076 case VRNDSCALEPDZ128rrikz:
32077 case VRNDSCALEPDZ256rmbi:
32078 case VRNDSCALEPDZ256rmbik:
32079 case VRNDSCALEPDZ256rmbikz:
32080 case VRNDSCALEPDZ256rmi:
32081 case VRNDSCALEPDZ256rmik:
32082 case VRNDSCALEPDZ256rmikz:
32083 case VRNDSCALEPDZ256rri:
32084 case VRNDSCALEPDZ256rrik:
32085 case VRNDSCALEPDZ256rrikz:
32086 case VRNDSCALEPDZrmbi:
32087 case VRNDSCALEPDZrmbik:
32088 case VRNDSCALEPDZrmbikz:
32089 case VRNDSCALEPDZrmi:
32090 case VRNDSCALEPDZrmik:
32091 case VRNDSCALEPDZrmikz:
32092 case VRNDSCALEPDZrri:
32093 case VRNDSCALEPDZrrib:
32094 case VRNDSCALEPDZrribk:
32095 case VRNDSCALEPDZrribkz:
32096 case VRNDSCALEPDZrrik:
32097 case VRNDSCALEPDZrrikz:
32098 return true;
32099 }
32100 return false;
32101}
32102
32103bool isVMLOAD(unsigned Opcode) {
32104 switch (Opcode) {
32105 case VMLOAD32:
32106 case VMLOAD64:
32107 return true;
32108 }
32109 return false;
32110}
32111
32112bool isVPTERNLOGQ(unsigned Opcode) {
32113 switch (Opcode) {
32114 case VPTERNLOGQZ128rmbi:
32115 case VPTERNLOGQZ128rmbik:
32116 case VPTERNLOGQZ128rmbikz:
32117 case VPTERNLOGQZ128rmi:
32118 case VPTERNLOGQZ128rmik:
32119 case VPTERNLOGQZ128rmikz:
32120 case VPTERNLOGQZ128rri:
32121 case VPTERNLOGQZ128rrik:
32122 case VPTERNLOGQZ128rrikz:
32123 case VPTERNLOGQZ256rmbi:
32124 case VPTERNLOGQZ256rmbik:
32125 case VPTERNLOGQZ256rmbikz:
32126 case VPTERNLOGQZ256rmi:
32127 case VPTERNLOGQZ256rmik:
32128 case VPTERNLOGQZ256rmikz:
32129 case VPTERNLOGQZ256rri:
32130 case VPTERNLOGQZ256rrik:
32131 case VPTERNLOGQZ256rrikz:
32132 case VPTERNLOGQZrmbi:
32133 case VPTERNLOGQZrmbik:
32134 case VPTERNLOGQZrmbikz:
32135 case VPTERNLOGQZrmi:
32136 case VPTERNLOGQZrmik:
32137 case VPTERNLOGQZrmikz:
32138 case VPTERNLOGQZrri:
32139 case VPTERNLOGQZrrik:
32140 case VPTERNLOGQZrrikz:
32141 return true;
32142 }
32143 return false;
32144}
32145
32146bool isKXNORD(unsigned Opcode) {
32147 return Opcode == KXNORDkk;
32148}
32149
32150bool isFXSAVE(unsigned Opcode) {
32151 return Opcode == FXSAVE;
32152}
32153
32154bool isVUNPCKHPD(unsigned Opcode) {
32155 switch (Opcode) {
32156 case VUNPCKHPDYrm:
32157 case VUNPCKHPDYrr:
32158 case VUNPCKHPDZ128rm:
32159 case VUNPCKHPDZ128rmb:
32160 case VUNPCKHPDZ128rmbk:
32161 case VUNPCKHPDZ128rmbkz:
32162 case VUNPCKHPDZ128rmk:
32163 case VUNPCKHPDZ128rmkz:
32164 case VUNPCKHPDZ128rr:
32165 case VUNPCKHPDZ128rrk:
32166 case VUNPCKHPDZ128rrkz:
32167 case VUNPCKHPDZ256rm:
32168 case VUNPCKHPDZ256rmb:
32169 case VUNPCKHPDZ256rmbk:
32170 case VUNPCKHPDZ256rmbkz:
32171 case VUNPCKHPDZ256rmk:
32172 case VUNPCKHPDZ256rmkz:
32173 case VUNPCKHPDZ256rr:
32174 case VUNPCKHPDZ256rrk:
32175 case VUNPCKHPDZ256rrkz:
32176 case VUNPCKHPDZrm:
32177 case VUNPCKHPDZrmb:
32178 case VUNPCKHPDZrmbk:
32179 case VUNPCKHPDZrmbkz:
32180 case VUNPCKHPDZrmk:
32181 case VUNPCKHPDZrmkz:
32182 case VUNPCKHPDZrr:
32183 case VUNPCKHPDZrrk:
32184 case VUNPCKHPDZrrkz:
32185 case VUNPCKHPDrm:
32186 case VUNPCKHPDrr:
32187 return true;
32188 }
32189 return false;
32190}
32191
32192bool isCVTPS2DQ(unsigned Opcode) {
32193 switch (Opcode) {
32194 case CVTPS2DQrm:
32195 case CVTPS2DQrr:
32196 return true;
32197 }
32198 return false;
32199}
32200
32201bool isVFMSUB213SS(unsigned Opcode) {
32202 switch (Opcode) {
32203 case VFMSUB213SSZm_Int:
32204 case VFMSUB213SSZmk_Int:
32205 case VFMSUB213SSZmkz_Int:
32206 case VFMSUB213SSZr_Int:
32207 case VFMSUB213SSZrb_Int:
32208 case VFMSUB213SSZrbk_Int:
32209 case VFMSUB213SSZrbkz_Int:
32210 case VFMSUB213SSZrk_Int:
32211 case VFMSUB213SSZrkz_Int:
32212 case VFMSUB213SSm_Int:
32213 case VFMSUB213SSr_Int:
32214 return true;
32215 }
32216 return false;
32217}
32218
32219bool isVPOPCNTD(unsigned Opcode) {
32220 switch (Opcode) {
32221 case VPOPCNTDZ128rm:
32222 case VPOPCNTDZ128rmb:
32223 case VPOPCNTDZ128rmbk:
32224 case VPOPCNTDZ128rmbkz:
32225 case VPOPCNTDZ128rmk:
32226 case VPOPCNTDZ128rmkz:
32227 case VPOPCNTDZ128rr:
32228 case VPOPCNTDZ128rrk:
32229 case VPOPCNTDZ128rrkz:
32230 case VPOPCNTDZ256rm:
32231 case VPOPCNTDZ256rmb:
32232 case VPOPCNTDZ256rmbk:
32233 case VPOPCNTDZ256rmbkz:
32234 case VPOPCNTDZ256rmk:
32235 case VPOPCNTDZ256rmkz:
32236 case VPOPCNTDZ256rr:
32237 case VPOPCNTDZ256rrk:
32238 case VPOPCNTDZ256rrkz:
32239 case VPOPCNTDZrm:
32240 case VPOPCNTDZrmb:
32241 case VPOPCNTDZrmbk:
32242 case VPOPCNTDZrmbkz:
32243 case VPOPCNTDZrmk:
32244 case VPOPCNTDZrmkz:
32245 case VPOPCNTDZrr:
32246 case VPOPCNTDZrrk:
32247 case VPOPCNTDZrrkz:
32248 return true;
32249 }
32250 return false;
32251}
32252
32253bool isSALC(unsigned Opcode) {
32254 return Opcode == SALC;
32255}
32256
32257bool isV4FNMADDSS(unsigned Opcode) {
32258 switch (Opcode) {
32259 case V4FNMADDSSrm:
32260 case V4FNMADDSSrmk:
32261 case V4FNMADDSSrmkz:
32262 return true;
32263 }
32264 return false;
32265}
32266
32267bool isXCRYPTOFB(unsigned Opcode) {
32268 return Opcode == XCRYPTOFB;
32269}
32270
32271bool isVORPD(unsigned Opcode) {
32272 switch (Opcode) {
32273 case VORPDYrm:
32274 case VORPDYrr:
32275 case VORPDZ128rm:
32276 case VORPDZ128rmb:
32277 case VORPDZ128rmbk:
32278 case VORPDZ128rmbkz:
32279 case VORPDZ128rmk:
32280 case VORPDZ128rmkz:
32281 case VORPDZ128rr:
32282 case VORPDZ128rrk:
32283 case VORPDZ128rrkz:
32284 case VORPDZ256rm:
32285 case VORPDZ256rmb:
32286 case VORPDZ256rmbk:
32287 case VORPDZ256rmbkz:
32288 case VORPDZ256rmk:
32289 case VORPDZ256rmkz:
32290 case VORPDZ256rr:
32291 case VORPDZ256rrk:
32292 case VORPDZ256rrkz:
32293 case VORPDZrm:
32294 case VORPDZrmb:
32295 case VORPDZrmbk:
32296 case VORPDZrmbkz:
32297 case VORPDZrmk:
32298 case VORPDZrmkz:
32299 case VORPDZrr:
32300 case VORPDZrrk:
32301 case VORPDZrrkz:
32302 case VORPDrm:
32303 case VORPDrr:
32304 return true;
32305 }
32306 return false;
32307}
32308
32309bool isLSL(unsigned Opcode) {
32310 switch (Opcode) {
32311 case LSL16rm:
32312 case LSL16rr:
32313 case LSL32rm:
32314 case LSL32rr:
32315 case LSL64rm:
32316 case LSL64rr:
32317 return true;
32318 }
32319 return false;
32320}
32321
32322bool isXCRYPTCFB(unsigned Opcode) {
32323 return Opcode == XCRYPTCFB;
32324}
32325
32326bool isVGETEXPSS(unsigned Opcode) {
32327 switch (Opcode) {
32328 case VGETEXPSSZm:
32329 case VGETEXPSSZmk:
32330 case VGETEXPSSZmkz:
32331 case VGETEXPSSZr:
32332 case VGETEXPSSZrb:
32333 case VGETEXPSSZrbk:
32334 case VGETEXPSSZrbkz:
32335 case VGETEXPSSZrk:
32336 case VGETEXPSSZrkz:
32337 return true;
32338 }
32339 return false;
32340}
32341
32342bool isPSLLDQ(unsigned Opcode) {
32343 return Opcode == PSLLDQri;
32344}
32345
32346bool isVPDPBUUD(unsigned Opcode) {
32347 switch (Opcode) {
32348 case VPDPBUUDYrm:
32349 case VPDPBUUDYrr:
32350 case VPDPBUUDZ128rm:
32351 case VPDPBUUDZ128rmb:
32352 case VPDPBUUDZ128rmbk:
32353 case VPDPBUUDZ128rmbkz:
32354 case VPDPBUUDZ128rmk:
32355 case VPDPBUUDZ128rmkz:
32356 case VPDPBUUDZ128rr:
32357 case VPDPBUUDZ128rrk:
32358 case VPDPBUUDZ128rrkz:
32359 case VPDPBUUDZ256rm:
32360 case VPDPBUUDZ256rmb:
32361 case VPDPBUUDZ256rmbk:
32362 case VPDPBUUDZ256rmbkz:
32363 case VPDPBUUDZ256rmk:
32364 case VPDPBUUDZ256rmkz:
32365 case VPDPBUUDZ256rr:
32366 case VPDPBUUDZ256rrk:
32367 case VPDPBUUDZ256rrkz:
32368 case VPDPBUUDZrm:
32369 case VPDPBUUDZrmb:
32370 case VPDPBUUDZrmbk:
32371 case VPDPBUUDZrmbkz:
32372 case VPDPBUUDZrmk:
32373 case VPDPBUUDZrmkz:
32374 case VPDPBUUDZrr:
32375 case VPDPBUUDZrrk:
32376 case VPDPBUUDZrrkz:
32377 case VPDPBUUDrm:
32378 case VPDPBUUDrr:
32379 return true;
32380 }
32381 return false;
32382}
32383
32384bool isVMXOFF(unsigned Opcode) {
32385 return Opcode == VMXOFF;
32386}
32387
32388bool isBLSIC(unsigned Opcode) {
32389 switch (Opcode) {
32390 case BLSIC32rm:
32391 case BLSIC32rr:
32392 case BLSIC64rm:
32393 case BLSIC64rr:
32394 return true;
32395 }
32396 return false;
32397}
32398
32399bool isMOVLHPS(unsigned Opcode) {
32400 return Opcode == MOVLHPSrr;
32401}
32402
32403bool isVMOVRSQ(unsigned Opcode) {
32404 switch (Opcode) {
32405 case VMOVRSQZ128m:
32406 case VMOVRSQZ128mk:
32407 case VMOVRSQZ128mkz:
32408 case VMOVRSQZ256m:
32409 case VMOVRSQZ256mk:
32410 case VMOVRSQZ256mkz:
32411 case VMOVRSQZm:
32412 case VMOVRSQZmk:
32413 case VMOVRSQZmkz:
32414 return true;
32415 }
32416 return false;
32417}
32418
32419bool isVFNMSUBSD(unsigned Opcode) {
32420 switch (Opcode) {
32421 case VFNMSUBSD4mr:
32422 case VFNMSUBSD4rm:
32423 case VFNMSUBSD4rr:
32424 case VFNMSUBSD4rr_REV:
32425 return true;
32426 }
32427 return false;
32428}
32429
32430bool isVCVTPH2IUBS(unsigned Opcode) {
32431 switch (Opcode) {
32432 case VCVTPH2IUBSZ128rm:
32433 case VCVTPH2IUBSZ128rmb:
32434 case VCVTPH2IUBSZ128rmbk:
32435 case VCVTPH2IUBSZ128rmbkz:
32436 case VCVTPH2IUBSZ128rmk:
32437 case VCVTPH2IUBSZ128rmkz:
32438 case VCVTPH2IUBSZ128rr:
32439 case VCVTPH2IUBSZ128rrk:
32440 case VCVTPH2IUBSZ128rrkz:
32441 case VCVTPH2IUBSZ256rm:
32442 case VCVTPH2IUBSZ256rmb:
32443 case VCVTPH2IUBSZ256rmbk:
32444 case VCVTPH2IUBSZ256rmbkz:
32445 case VCVTPH2IUBSZ256rmk:
32446 case VCVTPH2IUBSZ256rmkz:
32447 case VCVTPH2IUBSZ256rr:
32448 case VCVTPH2IUBSZ256rrk:
32449 case VCVTPH2IUBSZ256rrkz:
32450 case VCVTPH2IUBSZrm:
32451 case VCVTPH2IUBSZrmb:
32452 case VCVTPH2IUBSZrmbk:
32453 case VCVTPH2IUBSZrmbkz:
32454 case VCVTPH2IUBSZrmk:
32455 case VCVTPH2IUBSZrmkz:
32456 case VCVTPH2IUBSZrr:
32457 case VCVTPH2IUBSZrrb:
32458 case VCVTPH2IUBSZrrbk:
32459 case VCVTPH2IUBSZrrbkz:
32460 case VCVTPH2IUBSZrrk:
32461 case VCVTPH2IUBSZrrkz:
32462 return true;
32463 }
32464 return false;
32465}
32466
32467bool isVFPCLASSSH(unsigned Opcode) {
32468 switch (Opcode) {
32469 case VFPCLASSSHZmi:
32470 case VFPCLASSSHZmik:
32471 case VFPCLASSSHZri:
32472 case VFPCLASSSHZrik:
32473 return true;
32474 }
32475 return false;
32476}
32477
32478bool isVPSHLQ(unsigned Opcode) {
32479 switch (Opcode) {
32480 case VPSHLQmr:
32481 case VPSHLQrm:
32482 case VPSHLQrr:
32483 case VPSHLQrr_REV:
32484 return true;
32485 }
32486 return false;
32487}
32488
32489bool isVROUNDPS(unsigned Opcode) {
32490 switch (Opcode) {
32491 case VROUNDPSYmi:
32492 case VROUNDPSYri:
32493 case VROUNDPSmi:
32494 case VROUNDPSri:
32495 return true;
32496 }
32497 return false;
32498}
32499
32500bool isVCVTPS2HF8S(unsigned Opcode) {
32501 switch (Opcode) {
32502 case VCVTPS2HF8SZ128rm:
32503 case VCVTPS2HF8SZ128rmb:
32504 case VCVTPS2HF8SZ128rmbk:
32505 case VCVTPS2HF8SZ128rmbkz:
32506 case VCVTPS2HF8SZ128rmk:
32507 case VCVTPS2HF8SZ128rmkz:
32508 case VCVTPS2HF8SZ128rr:
32509 case VCVTPS2HF8SZ128rrk:
32510 case VCVTPS2HF8SZ128rrkz:
32511 case VCVTPS2HF8SZ256rm:
32512 case VCVTPS2HF8SZ256rmb:
32513 case VCVTPS2HF8SZ256rmbk:
32514 case VCVTPS2HF8SZ256rmbkz:
32515 case VCVTPS2HF8SZ256rmk:
32516 case VCVTPS2HF8SZ256rmkz:
32517 case VCVTPS2HF8SZ256rr:
32518 case VCVTPS2HF8SZ256rrk:
32519 case VCVTPS2HF8SZ256rrkz:
32520 case VCVTPS2HF8SZrm:
32521 case VCVTPS2HF8SZrmb:
32522 case VCVTPS2HF8SZrmbk:
32523 case VCVTPS2HF8SZrmbkz:
32524 case VCVTPS2HF8SZrmk:
32525 case VCVTPS2HF8SZrmkz:
32526 case VCVTPS2HF8SZrr:
32527 case VCVTPS2HF8SZrrk:
32528 case VCVTPS2HF8SZrrkz:
32529 return true;
32530 }
32531 return false;
32532}
32533
32534bool isVSCATTERPF0QPS(unsigned Opcode) {
32535 return Opcode == VSCATTERPF0QPSm;
32536}
32537
32538bool isERETS(unsigned Opcode) {
32539 return Opcode == ERETS;
32540}
32541
32542bool isVPERMI2D(unsigned Opcode) {
32543 switch (Opcode) {
32544 case VPERMI2DZ128rm:
32545 case VPERMI2DZ128rmb:
32546 case VPERMI2DZ128rmbk:
32547 case VPERMI2DZ128rmbkz:
32548 case VPERMI2DZ128rmk:
32549 case VPERMI2DZ128rmkz:
32550 case VPERMI2DZ128rr:
32551 case VPERMI2DZ128rrk:
32552 case VPERMI2DZ128rrkz:
32553 case VPERMI2DZ256rm:
32554 case VPERMI2DZ256rmb:
32555 case VPERMI2DZ256rmbk:
32556 case VPERMI2DZ256rmbkz:
32557 case VPERMI2DZ256rmk:
32558 case VPERMI2DZ256rmkz:
32559 case VPERMI2DZ256rr:
32560 case VPERMI2DZ256rrk:
32561 case VPERMI2DZ256rrkz:
32562 case VPERMI2DZrm:
32563 case VPERMI2DZrmb:
32564 case VPERMI2DZrmbk:
32565 case VPERMI2DZrmbkz:
32566 case VPERMI2DZrmk:
32567 case VPERMI2DZrmkz:
32568 case VPERMI2DZrr:
32569 case VPERMI2DZrrk:
32570 case VPERMI2DZrrkz:
32571 return true;
32572 }
32573 return false;
32574}
32575
32576bool isFUCOMP(unsigned Opcode) {
32577 return Opcode == UCOM_FPr;
32578}
32579
32580bool isVCVTTPS2QQ(unsigned Opcode) {
32581 switch (Opcode) {
32582 case VCVTTPS2QQZ128rm:
32583 case VCVTTPS2QQZ128rmb:
32584 case VCVTTPS2QQZ128rmbk:
32585 case VCVTTPS2QQZ128rmbkz:
32586 case VCVTTPS2QQZ128rmk:
32587 case VCVTTPS2QQZ128rmkz:
32588 case VCVTTPS2QQZ128rr:
32589 case VCVTTPS2QQZ128rrk:
32590 case VCVTTPS2QQZ128rrkz:
32591 case VCVTTPS2QQZ256rm:
32592 case VCVTTPS2QQZ256rmb:
32593 case VCVTTPS2QQZ256rmbk:
32594 case VCVTTPS2QQZ256rmbkz:
32595 case VCVTTPS2QQZ256rmk:
32596 case VCVTTPS2QQZ256rmkz:
32597 case VCVTTPS2QQZ256rr:
32598 case VCVTTPS2QQZ256rrk:
32599 case VCVTTPS2QQZ256rrkz:
32600 case VCVTTPS2QQZrm:
32601 case VCVTTPS2QQZrmb:
32602 case VCVTTPS2QQZrmbk:
32603 case VCVTTPS2QQZrmbkz:
32604 case VCVTTPS2QQZrmk:
32605 case VCVTTPS2QQZrmkz:
32606 case VCVTTPS2QQZrr:
32607 case VCVTTPS2QQZrrb:
32608 case VCVTTPS2QQZrrbk:
32609 case VCVTTPS2QQZrrbkz:
32610 case VCVTTPS2QQZrrk:
32611 case VCVTTPS2QQZrrkz:
32612 return true;
32613 }
32614 return false;
32615}
32616
32617bool isPUSHFD(unsigned Opcode) {
32618 return Opcode == PUSHF32;
32619}
32620
32621bool isVPABSD(unsigned Opcode) {
32622 switch (Opcode) {
32623 case VPABSDYrm:
32624 case VPABSDYrr:
32625 case VPABSDZ128rm:
32626 case VPABSDZ128rmb:
32627 case VPABSDZ128rmbk:
32628 case VPABSDZ128rmbkz:
32629 case VPABSDZ128rmk:
32630 case VPABSDZ128rmkz:
32631 case VPABSDZ128rr:
32632 case VPABSDZ128rrk:
32633 case VPABSDZ128rrkz:
32634 case VPABSDZ256rm:
32635 case VPABSDZ256rmb:
32636 case VPABSDZ256rmbk:
32637 case VPABSDZ256rmbkz:
32638 case VPABSDZ256rmk:
32639 case VPABSDZ256rmkz:
32640 case VPABSDZ256rr:
32641 case VPABSDZ256rrk:
32642 case VPABSDZ256rrkz:
32643 case VPABSDZrm:
32644 case VPABSDZrmb:
32645 case VPABSDZrmbk:
32646 case VPABSDZrmbkz:
32647 case VPABSDZrmk:
32648 case VPABSDZrmkz:
32649 case VPABSDZrr:
32650 case VPABSDZrrk:
32651 case VPABSDZrrkz:
32652 case VPABSDrm:
32653 case VPABSDrr:
32654 return true;
32655 }
32656 return false;
32657}
32658
32659bool isKORB(unsigned Opcode) {
32660 return Opcode == KORBkk;
32661}
32662
32663bool isVRCP28PD(unsigned Opcode) {
32664 switch (Opcode) {
32665 case VRCP28PDZm:
32666 case VRCP28PDZmb:
32667 case VRCP28PDZmbk:
32668 case VRCP28PDZmbkz:
32669 case VRCP28PDZmk:
32670 case VRCP28PDZmkz:
32671 case VRCP28PDZr:
32672 case VRCP28PDZrb:
32673 case VRCP28PDZrbk:
32674 case VRCP28PDZrbkz:
32675 case VRCP28PDZrk:
32676 case VRCP28PDZrkz:
32677 return true;
32678 }
32679 return false;
32680}
32681
32682bool isVROUNDSS(unsigned Opcode) {
32683 switch (Opcode) {
32684 case VROUNDSSmi_Int:
32685 case VROUNDSSri_Int:
32686 return true;
32687 }
32688 return false;
32689}
32690
32691bool isVCVTSD2USI(unsigned Opcode) {
32692 switch (Opcode) {
32693 case VCVTSD2USI64Zrm_Int:
32694 case VCVTSD2USI64Zrr_Int:
32695 case VCVTSD2USI64Zrrb_Int:
32696 case VCVTSD2USIZrm_Int:
32697 case VCVTSD2USIZrr_Int:
32698 case VCVTSD2USIZrrb_Int:
32699 return true;
32700 }
32701 return false;
32702}
32703
32704bool isVPABSB(unsigned Opcode) {
32705 switch (Opcode) {
32706 case VPABSBYrm:
32707 case VPABSBYrr:
32708 case VPABSBZ128rm:
32709 case VPABSBZ128rmk:
32710 case VPABSBZ128rmkz:
32711 case VPABSBZ128rr:
32712 case VPABSBZ128rrk:
32713 case VPABSBZ128rrkz:
32714 case VPABSBZ256rm:
32715 case VPABSBZ256rmk:
32716 case VPABSBZ256rmkz:
32717 case VPABSBZ256rr:
32718 case VPABSBZ256rrk:
32719 case VPABSBZ256rrkz:
32720 case VPABSBZrm:
32721 case VPABSBZrmk:
32722 case VPABSBZrmkz:
32723 case VPABSBZrr:
32724 case VPABSBZrrk:
32725 case VPABSBZrrkz:
32726 case VPABSBrm:
32727 case VPABSBrr:
32728 return true;
32729 }
32730 return false;
32731}
32732
32733bool isPMAXUD(unsigned Opcode) {
32734 switch (Opcode) {
32735 case PMAXUDrm:
32736 case PMAXUDrr:
32737 return true;
32738 }
32739 return false;
32740}
32741
32742bool isVPERMPD(unsigned Opcode) {
32743 switch (Opcode) {
32744 case VPERMPDYmi:
32745 case VPERMPDYri:
32746 case VPERMPDZ256mbi:
32747 case VPERMPDZ256mbik:
32748 case VPERMPDZ256mbikz:
32749 case VPERMPDZ256mi:
32750 case VPERMPDZ256mik:
32751 case VPERMPDZ256mikz:
32752 case VPERMPDZ256ri:
32753 case VPERMPDZ256rik:
32754 case VPERMPDZ256rikz:
32755 case VPERMPDZ256rm:
32756 case VPERMPDZ256rmb:
32757 case VPERMPDZ256rmbk:
32758 case VPERMPDZ256rmbkz:
32759 case VPERMPDZ256rmk:
32760 case VPERMPDZ256rmkz:
32761 case VPERMPDZ256rr:
32762 case VPERMPDZ256rrk:
32763 case VPERMPDZ256rrkz:
32764 case VPERMPDZmbi:
32765 case VPERMPDZmbik:
32766 case VPERMPDZmbikz:
32767 case VPERMPDZmi:
32768 case VPERMPDZmik:
32769 case VPERMPDZmikz:
32770 case VPERMPDZri:
32771 case VPERMPDZrik:
32772 case VPERMPDZrikz:
32773 case VPERMPDZrm:
32774 case VPERMPDZrmb:
32775 case VPERMPDZrmbk:
32776 case VPERMPDZrmbkz:
32777 case VPERMPDZrmk:
32778 case VPERMPDZrmkz:
32779 case VPERMPDZrr:
32780 case VPERMPDZrrk:
32781 case VPERMPDZrrkz:
32782 return true;
32783 }
32784 return false;
32785}
32786
32787bool isVPMULHUW(unsigned Opcode) {
32788 switch (Opcode) {
32789 case VPMULHUWYrm:
32790 case VPMULHUWYrr:
32791 case VPMULHUWZ128rm:
32792 case VPMULHUWZ128rmk:
32793 case VPMULHUWZ128rmkz:
32794 case VPMULHUWZ128rr:
32795 case VPMULHUWZ128rrk:
32796 case VPMULHUWZ128rrkz:
32797 case VPMULHUWZ256rm:
32798 case VPMULHUWZ256rmk:
32799 case VPMULHUWZ256rmkz:
32800 case VPMULHUWZ256rr:
32801 case VPMULHUWZ256rrk:
32802 case VPMULHUWZ256rrkz:
32803 case VPMULHUWZrm:
32804 case VPMULHUWZrmk:
32805 case VPMULHUWZrmkz:
32806 case VPMULHUWZrr:
32807 case VPMULHUWZrrk:
32808 case VPMULHUWZrrkz:
32809 case VPMULHUWrm:
32810 case VPMULHUWrr:
32811 return true;
32812 }
32813 return false;
32814}
32815
32816bool isFCHS(unsigned Opcode) {
32817 return Opcode == CHS_F;
32818}
32819
32820bool isVPBLENDMB(unsigned Opcode) {
32821 switch (Opcode) {
32822 case VPBLENDMBZ128rm:
32823 case VPBLENDMBZ128rmk:
32824 case VPBLENDMBZ128rmkz:
32825 case VPBLENDMBZ128rr:
32826 case VPBLENDMBZ128rrk:
32827 case VPBLENDMBZ128rrkz:
32828 case VPBLENDMBZ256rm:
32829 case VPBLENDMBZ256rmk:
32830 case VPBLENDMBZ256rmkz:
32831 case VPBLENDMBZ256rr:
32832 case VPBLENDMBZ256rrk:
32833 case VPBLENDMBZ256rrkz:
32834 case VPBLENDMBZrm:
32835 case VPBLENDMBZrmk:
32836 case VPBLENDMBZrmkz:
32837 case VPBLENDMBZrr:
32838 case VPBLENDMBZrrk:
32839 case VPBLENDMBZrrkz:
32840 return true;
32841 }
32842 return false;
32843}
32844
32845bool isVGETMANTSS(unsigned Opcode) {
32846 switch (Opcode) {
32847 case VGETMANTSSZrmi:
32848 case VGETMANTSSZrmik:
32849 case VGETMANTSSZrmikz:
32850 case VGETMANTSSZrri:
32851 case VGETMANTSSZrrib:
32852 case VGETMANTSSZrribk:
32853 case VGETMANTSSZrribkz:
32854 case VGETMANTSSZrrik:
32855 case VGETMANTSSZrrikz:
32856 return true;
32857 }
32858 return false;
32859}
32860
32861bool isVPSLLW(unsigned Opcode) {
32862 switch (Opcode) {
32863 case VPSLLWYri:
32864 case VPSLLWYrm:
32865 case VPSLLWYrr:
32866 case VPSLLWZ128mi:
32867 case VPSLLWZ128mik:
32868 case VPSLLWZ128mikz:
32869 case VPSLLWZ128ri:
32870 case VPSLLWZ128rik:
32871 case VPSLLWZ128rikz:
32872 case VPSLLWZ128rm:
32873 case VPSLLWZ128rmk:
32874 case VPSLLWZ128rmkz:
32875 case VPSLLWZ128rr:
32876 case VPSLLWZ128rrk:
32877 case VPSLLWZ128rrkz:
32878 case VPSLLWZ256mi:
32879 case VPSLLWZ256mik:
32880 case VPSLLWZ256mikz:
32881 case VPSLLWZ256ri:
32882 case VPSLLWZ256rik:
32883 case VPSLLWZ256rikz:
32884 case VPSLLWZ256rm:
32885 case VPSLLWZ256rmk:
32886 case VPSLLWZ256rmkz:
32887 case VPSLLWZ256rr:
32888 case VPSLLWZ256rrk:
32889 case VPSLLWZ256rrkz:
32890 case VPSLLWZmi:
32891 case VPSLLWZmik:
32892 case VPSLLWZmikz:
32893 case VPSLLWZri:
32894 case VPSLLWZrik:
32895 case VPSLLWZrikz:
32896 case VPSLLWZrm:
32897 case VPSLLWZrmk:
32898 case VPSLLWZrmkz:
32899 case VPSLLWZrr:
32900 case VPSLLWZrrk:
32901 case VPSLLWZrrkz:
32902 case VPSLLWri:
32903 case VPSLLWrm:
32904 case VPSLLWrr:
32905 return true;
32906 }
32907 return false;
32908}
32909
32910bool isVDIVPD(unsigned Opcode) {
32911 switch (Opcode) {
32912 case VDIVPDYrm:
32913 case VDIVPDYrr:
32914 case VDIVPDZ128rm:
32915 case VDIVPDZ128rmb:
32916 case VDIVPDZ128rmbk:
32917 case VDIVPDZ128rmbkz:
32918 case VDIVPDZ128rmk:
32919 case VDIVPDZ128rmkz:
32920 case VDIVPDZ128rr:
32921 case VDIVPDZ128rrk:
32922 case VDIVPDZ128rrkz:
32923 case VDIVPDZ256rm:
32924 case VDIVPDZ256rmb:
32925 case VDIVPDZ256rmbk:
32926 case VDIVPDZ256rmbkz:
32927 case VDIVPDZ256rmk:
32928 case VDIVPDZ256rmkz:
32929 case VDIVPDZ256rr:
32930 case VDIVPDZ256rrk:
32931 case VDIVPDZ256rrkz:
32932 case VDIVPDZrm:
32933 case VDIVPDZrmb:
32934 case VDIVPDZrmbk:
32935 case VDIVPDZrmbkz:
32936 case VDIVPDZrmk:
32937 case VDIVPDZrmkz:
32938 case VDIVPDZrr:
32939 case VDIVPDZrrb:
32940 case VDIVPDZrrbk:
32941 case VDIVPDZrrbkz:
32942 case VDIVPDZrrk:
32943 case VDIVPDZrrkz:
32944 case VDIVPDrm:
32945 case VDIVPDrr:
32946 return true;
32947 }
32948 return false;
32949}
32950
32951bool isBLCMSK(unsigned Opcode) {
32952 switch (Opcode) {
32953 case BLCMSK32rm:
32954 case BLCMSK32rr:
32955 case BLCMSK64rm:
32956 case BLCMSK64rr:
32957 return true;
32958 }
32959 return false;
32960}
32961
32962bool isFDIV(unsigned Opcode) {
32963 switch (Opcode) {
32964 case DIV_F32m:
32965 case DIV_F64m:
32966 case DIV_FST0r:
32967 case DIV_FrST0:
32968 return true;
32969 }
32970 return false;
32971}
32972
32973bool isRSQRTSS(unsigned Opcode) {
32974 switch (Opcode) {
32975 case RSQRTSSm_Int:
32976 case RSQRTSSr_Int:
32977 return true;
32978 }
32979 return false;
32980}
32981
32982bool isPOR(unsigned Opcode) {
32983 switch (Opcode) {
32984 case MMX_PORrm:
32985 case MMX_PORrr:
32986 case PORrm:
32987 case PORrr:
32988 return true;
32989 }
32990 return false;
32991}
32992
32993bool isVMOVDQA32(unsigned Opcode) {
32994 switch (Opcode) {
32995 case VMOVDQA32Z128mr:
32996 case VMOVDQA32Z128mrk:
32997 case VMOVDQA32Z128rm:
32998 case VMOVDQA32Z128rmk:
32999 case VMOVDQA32Z128rmkz:
33000 case VMOVDQA32Z128rr:
33001 case VMOVDQA32Z128rr_REV:
33002 case VMOVDQA32Z128rrk:
33003 case VMOVDQA32Z128rrk_REV:
33004 case VMOVDQA32Z128rrkz:
33005 case VMOVDQA32Z128rrkz_REV:
33006 case VMOVDQA32Z256mr:
33007 case VMOVDQA32Z256mrk:
33008 case VMOVDQA32Z256rm:
33009 case VMOVDQA32Z256rmk:
33010 case VMOVDQA32Z256rmkz:
33011 case VMOVDQA32Z256rr:
33012 case VMOVDQA32Z256rr_REV:
33013 case VMOVDQA32Z256rrk:
33014 case VMOVDQA32Z256rrk_REV:
33015 case VMOVDQA32Z256rrkz:
33016 case VMOVDQA32Z256rrkz_REV:
33017 case VMOVDQA32Zmr:
33018 case VMOVDQA32Zmrk:
33019 case VMOVDQA32Zrm:
33020 case VMOVDQA32Zrmk:
33021 case VMOVDQA32Zrmkz:
33022 case VMOVDQA32Zrr:
33023 case VMOVDQA32Zrr_REV:
33024 case VMOVDQA32Zrrk:
33025 case VMOVDQA32Zrrk_REV:
33026 case VMOVDQA32Zrrkz:
33027 case VMOVDQA32Zrrkz_REV:
33028 return true;
33029 }
33030 return false;
33031}
33032
33033bool isVPHADDUWQ(unsigned Opcode) {
33034 switch (Opcode) {
33035 case VPHADDUWQrm:
33036 case VPHADDUWQrr:
33037 return true;
33038 }
33039 return false;
33040}
33041
33042bool isPSRAD(unsigned Opcode) {
33043 switch (Opcode) {
33044 case MMX_PSRADri:
33045 case MMX_PSRADrm:
33046 case MMX_PSRADrr:
33047 case PSRADri:
33048 case PSRADrm:
33049 case PSRADrr:
33050 return true;
33051 }
33052 return false;
33053}
33054
33055bool isPREFETCHW(unsigned Opcode) {
33056 return Opcode == PREFETCHW;
33057}
33058
33059bool isFIDIVR(unsigned Opcode) {
33060 switch (Opcode) {
33061 case DIVR_FI16m:
33062 case DIVR_FI32m:
33063 return true;
33064 }
33065 return false;
33066}
33067
33068bool isMOVHPS(unsigned Opcode) {
33069 switch (Opcode) {
33070 case MOVHPSmr:
33071 case MOVHPSrm:
33072 return true;
33073 }
33074 return false;
33075}
33076
33077bool isVFNMSUB231PH(unsigned Opcode) {
33078 switch (Opcode) {
33079 case VFNMSUB231PHZ128m:
33080 case VFNMSUB231PHZ128mb:
33081 case VFNMSUB231PHZ128mbk:
33082 case VFNMSUB231PHZ128mbkz:
33083 case VFNMSUB231PHZ128mk:
33084 case VFNMSUB231PHZ128mkz:
33085 case VFNMSUB231PHZ128r:
33086 case VFNMSUB231PHZ128rk:
33087 case VFNMSUB231PHZ128rkz:
33088 case VFNMSUB231PHZ256m:
33089 case VFNMSUB231PHZ256mb:
33090 case VFNMSUB231PHZ256mbk:
33091 case VFNMSUB231PHZ256mbkz:
33092 case VFNMSUB231PHZ256mk:
33093 case VFNMSUB231PHZ256mkz:
33094 case VFNMSUB231PHZ256r:
33095 case VFNMSUB231PHZ256rk:
33096 case VFNMSUB231PHZ256rkz:
33097 case VFNMSUB231PHZm:
33098 case VFNMSUB231PHZmb:
33099 case VFNMSUB231PHZmbk:
33100 case VFNMSUB231PHZmbkz:
33101 case VFNMSUB231PHZmk:
33102 case VFNMSUB231PHZmkz:
33103 case VFNMSUB231PHZr:
33104 case VFNMSUB231PHZrb:
33105 case VFNMSUB231PHZrbk:
33106 case VFNMSUB231PHZrbkz:
33107 case VFNMSUB231PHZrk:
33108 case VFNMSUB231PHZrkz:
33109 return true;
33110 }
33111 return false;
33112}
33113
33114bool isUNPCKLPS(unsigned Opcode) {
33115 switch (Opcode) {
33116 case UNPCKLPSrm:
33117 case UNPCKLPSrr:
33118 return true;
33119 }
33120 return false;
33121}
33122
33123bool isVPSIGNB(unsigned Opcode) {
33124 switch (Opcode) {
33125 case VPSIGNBYrm:
33126 case VPSIGNBYrr:
33127 case VPSIGNBrm:
33128 case VPSIGNBrr:
33129 return true;
33130 }
33131 return false;
33132}
33133
33134bool isSAVEPREVSSP(unsigned Opcode) {
33135 return Opcode == SAVEPREVSSP;
33136}
33137
33138bool isVSCALEFSD(unsigned Opcode) {
33139 switch (Opcode) {
33140 case VSCALEFSDZrm:
33141 case VSCALEFSDZrmk:
33142 case VSCALEFSDZrmkz:
33143 case VSCALEFSDZrr:
33144 case VSCALEFSDZrrb_Int:
33145 case VSCALEFSDZrrbk_Int:
33146 case VSCALEFSDZrrbkz_Int:
33147 case VSCALEFSDZrrk:
33148 case VSCALEFSDZrrkz:
33149 return true;
33150 }
33151 return false;
33152}
33153
33154bool isFSIN(unsigned Opcode) {
33155 return Opcode == FSIN;
33156}
33157
33158bool isSCASQ(unsigned Opcode) {
33159 return Opcode == SCASQ;
33160}
33161
33162bool isVCVTTPD2QQS(unsigned Opcode) {
33163 switch (Opcode) {
33164 case VCVTTPD2QQSZ128rm:
33165 case VCVTTPD2QQSZ128rmb:
33166 case VCVTTPD2QQSZ128rmbk:
33167 case VCVTTPD2QQSZ128rmbkz:
33168 case VCVTTPD2QQSZ128rmk:
33169 case VCVTTPD2QQSZ128rmkz:
33170 case VCVTTPD2QQSZ128rr:
33171 case VCVTTPD2QQSZ128rrk:
33172 case VCVTTPD2QQSZ128rrkz:
33173 case VCVTTPD2QQSZ256rm:
33174 case VCVTTPD2QQSZ256rmb:
33175 case VCVTTPD2QQSZ256rmbk:
33176 case VCVTTPD2QQSZ256rmbkz:
33177 case VCVTTPD2QQSZ256rmk:
33178 case VCVTTPD2QQSZ256rmkz:
33179 case VCVTTPD2QQSZ256rr:
33180 case VCVTTPD2QQSZ256rrb:
33181 case VCVTTPD2QQSZ256rrbk:
33182 case VCVTTPD2QQSZ256rrbkz:
33183 case VCVTTPD2QQSZ256rrk:
33184 case VCVTTPD2QQSZ256rrkz:
33185 case VCVTTPD2QQSZrm:
33186 case VCVTTPD2QQSZrmb:
33187 case VCVTTPD2QQSZrmbk:
33188 case VCVTTPD2QQSZrmbkz:
33189 case VCVTTPD2QQSZrmk:
33190 case VCVTTPD2QQSZrmkz:
33191 case VCVTTPD2QQSZrr:
33192 case VCVTTPD2QQSZrrb:
33193 case VCVTTPD2QQSZrrbk:
33194 case VCVTTPD2QQSZrrbkz:
33195 case VCVTTPD2QQSZrrk:
33196 case VCVTTPD2QQSZrrkz:
33197 return true;
33198 }
33199 return false;
33200}
33201
33202bool isPCMPGTW(unsigned Opcode) {
33203 switch (Opcode) {
33204 case MMX_PCMPGTWrm:
33205 case MMX_PCMPGTWrr:
33206 case PCMPGTWrm:
33207 case PCMPGTWrr:
33208 return true;
33209 }
33210 return false;
33211}
33212
33213bool isMULX(unsigned Opcode) {
33214 switch (Opcode) {
33215 case MULX32rm:
33216 case MULX32rm_EVEX:
33217 case MULX32rr:
33218 case MULX32rr_EVEX:
33219 case MULX64rm:
33220 case MULX64rm_EVEX:
33221 case MULX64rr:
33222 case MULX64rr_EVEX:
33223 return true;
33224 }
33225 return false;
33226}
33227
33228bool isVPMAXUW(unsigned Opcode) {
33229 switch (Opcode) {
33230 case VPMAXUWYrm:
33231 case VPMAXUWYrr:
33232 case VPMAXUWZ128rm:
33233 case VPMAXUWZ128rmk:
33234 case VPMAXUWZ128rmkz:
33235 case VPMAXUWZ128rr:
33236 case VPMAXUWZ128rrk:
33237 case VPMAXUWZ128rrkz:
33238 case VPMAXUWZ256rm:
33239 case VPMAXUWZ256rmk:
33240 case VPMAXUWZ256rmkz:
33241 case VPMAXUWZ256rr:
33242 case VPMAXUWZ256rrk:
33243 case VPMAXUWZ256rrkz:
33244 case VPMAXUWZrm:
33245 case VPMAXUWZrmk:
33246 case VPMAXUWZrmkz:
33247 case VPMAXUWZrr:
33248 case VPMAXUWZrrk:
33249 case VPMAXUWZrrkz:
33250 case VPMAXUWrm:
33251 case VPMAXUWrr:
33252 return true;
33253 }
33254 return false;
33255}
33256
33257bool isPAUSE(unsigned Opcode) {
33258 return Opcode == PAUSE;
33259}
33260
33261bool isMOVQ2DQ(unsigned Opcode) {
33262 return Opcode == MMX_MOVQ2DQrr;
33263}
33264
33265bool isVPABSW(unsigned Opcode) {
33266 switch (Opcode) {
33267 case VPABSWYrm:
33268 case VPABSWYrr:
33269 case VPABSWZ128rm:
33270 case VPABSWZ128rmk:
33271 case VPABSWZ128rmkz:
33272 case VPABSWZ128rr:
33273 case VPABSWZ128rrk:
33274 case VPABSWZ128rrkz:
33275 case VPABSWZ256rm:
33276 case VPABSWZ256rmk:
33277 case VPABSWZ256rmkz:
33278 case VPABSWZ256rr:
33279 case VPABSWZ256rrk:
33280 case VPABSWZ256rrkz:
33281 case VPABSWZrm:
33282 case VPABSWZrmk:
33283 case VPABSWZrmkz:
33284 case VPABSWZrr:
33285 case VPABSWZrrk:
33286 case VPABSWZrrkz:
33287 case VPABSWrm:
33288 case VPABSWrr:
33289 return true;
33290 }
33291 return false;
33292}
33293
33294bool isVBITREVB(unsigned Opcode) {
33295 switch (Opcode) {
33296 case VPBITREVBZ128rm:
33297 case VPBITREVBZ128rmk:
33298 case VPBITREVBZ128rmkz:
33299 case VPBITREVBZ128rr:
33300 case VPBITREVBZ128rrk:
33301 case VPBITREVBZ128rrkz:
33302 case VPBITREVBZ256rm:
33303 case VPBITREVBZ256rmk:
33304 case VPBITREVBZ256rmkz:
33305 case VPBITREVBZ256rr:
33306 case VPBITREVBZ256rrk:
33307 case VPBITREVBZ256rrkz:
33308 case VPBITREVBZrm:
33309 case VPBITREVBZrmk:
33310 case VPBITREVBZrmkz:
33311 case VPBITREVBZrr:
33312 case VPBITREVBZrrk:
33313 case VPBITREVBZrrkz:
33314 return true;
33315 }
33316 return false;
33317}
33318
33319bool isVPCOMPRESSD(unsigned Opcode) {
33320 switch (Opcode) {
33321 case VPCOMPRESSDZ128mr:
33322 case VPCOMPRESSDZ128mrk:
33323 case VPCOMPRESSDZ128rr:
33324 case VPCOMPRESSDZ128rrk:
33325 case VPCOMPRESSDZ128rrkz:
33326 case VPCOMPRESSDZ256mr:
33327 case VPCOMPRESSDZ256mrk:
33328 case VPCOMPRESSDZ256rr:
33329 case VPCOMPRESSDZ256rrk:
33330 case VPCOMPRESSDZ256rrkz:
33331 case VPCOMPRESSDZmr:
33332 case VPCOMPRESSDZmrk:
33333 case VPCOMPRESSDZrr:
33334 case VPCOMPRESSDZrrk:
33335 case VPCOMPRESSDZrrkz:
33336 return true;
33337 }
33338 return false;
33339}
33340
33341bool isVPSUBQ(unsigned Opcode) {
33342 switch (Opcode) {
33343 case VPSUBQYrm:
33344 case VPSUBQYrr:
33345 case VPSUBQZ128rm:
33346 case VPSUBQZ128rmb:
33347 case VPSUBQZ128rmbk:
33348 case VPSUBQZ128rmbkz:
33349 case VPSUBQZ128rmk:
33350 case VPSUBQZ128rmkz:
33351 case VPSUBQZ128rr:
33352 case VPSUBQZ128rrk:
33353 case VPSUBQZ128rrkz:
33354 case VPSUBQZ256rm:
33355 case VPSUBQZ256rmb:
33356 case VPSUBQZ256rmbk:
33357 case VPSUBQZ256rmbkz:
33358 case VPSUBQZ256rmk:
33359 case VPSUBQZ256rmkz:
33360 case VPSUBQZ256rr:
33361 case VPSUBQZ256rrk:
33362 case VPSUBQZ256rrkz:
33363 case VPSUBQZrm:
33364 case VPSUBQZrmb:
33365 case VPSUBQZrmbk:
33366 case VPSUBQZrmbkz:
33367 case VPSUBQZrmk:
33368 case VPSUBQZrmkz:
33369 case VPSUBQZrr:
33370 case VPSUBQZrrk:
33371 case VPSUBQZrrkz:
33372 case VPSUBQrm:
33373 case VPSUBQrr:
33374 return true;
33375 }
33376 return false;
33377}
33378
33379bool isVPMOVUSQW(unsigned Opcode) {
33380 switch (Opcode) {
33381 case VPMOVUSQWZ128mr:
33382 case VPMOVUSQWZ128mrk:
33383 case VPMOVUSQWZ128rr:
33384 case VPMOVUSQWZ128rrk:
33385 case VPMOVUSQWZ128rrkz:
33386 case VPMOVUSQWZ256mr:
33387 case VPMOVUSQWZ256mrk:
33388 case VPMOVUSQWZ256rr:
33389 case VPMOVUSQWZ256rrk:
33390 case VPMOVUSQWZ256rrkz:
33391 case VPMOVUSQWZmr:
33392 case VPMOVUSQWZmrk:
33393 case VPMOVUSQWZrr:
33394 case VPMOVUSQWZrrk:
33395 case VPMOVUSQWZrrkz:
33396 return true;
33397 }
33398 return false;
33399}
33400
33401bool isBLENDVPD(unsigned Opcode) {
33402 switch (Opcode) {
33403 case BLENDVPDrm0:
33404 case BLENDVPDrr0:
33405 return true;
33406 }
33407 return false;
33408}
33409
33410bool isVFNMADD132BF16(unsigned Opcode) {
33411 switch (Opcode) {
33412 case VFNMADD132BF16Z128m:
33413 case VFNMADD132BF16Z128mb:
33414 case VFNMADD132BF16Z128mbk:
33415 case VFNMADD132BF16Z128mbkz:
33416 case VFNMADD132BF16Z128mk:
33417 case VFNMADD132BF16Z128mkz:
33418 case VFNMADD132BF16Z128r:
33419 case VFNMADD132BF16Z128rk:
33420 case VFNMADD132BF16Z128rkz:
33421 case VFNMADD132BF16Z256m:
33422 case VFNMADD132BF16Z256mb:
33423 case VFNMADD132BF16Z256mbk:
33424 case VFNMADD132BF16Z256mbkz:
33425 case VFNMADD132BF16Z256mk:
33426 case VFNMADD132BF16Z256mkz:
33427 case VFNMADD132BF16Z256r:
33428 case VFNMADD132BF16Z256rk:
33429 case VFNMADD132BF16Z256rkz:
33430 case VFNMADD132BF16Zm:
33431 case VFNMADD132BF16Zmb:
33432 case VFNMADD132BF16Zmbk:
33433 case VFNMADD132BF16Zmbkz:
33434 case VFNMADD132BF16Zmk:
33435 case VFNMADD132BF16Zmkz:
33436 case VFNMADD132BF16Zr:
33437 case VFNMADD132BF16Zrk:
33438 case VFNMADD132BF16Zrkz:
33439 return true;
33440 }
33441 return false;
33442}
33443
33444bool isVPMOVQB(unsigned Opcode) {
33445 switch (Opcode) {
33446 case VPMOVQBZ128mr:
33447 case VPMOVQBZ128mrk:
33448 case VPMOVQBZ128rr:
33449 case VPMOVQBZ128rrk:
33450 case VPMOVQBZ128rrkz:
33451 case VPMOVQBZ256mr:
33452 case VPMOVQBZ256mrk:
33453 case VPMOVQBZ256rr:
33454 case VPMOVQBZ256rrk:
33455 case VPMOVQBZ256rrkz:
33456 case VPMOVQBZmr:
33457 case VPMOVQBZmrk:
33458 case VPMOVQBZrr:
33459 case VPMOVQBZrrk:
33460 case VPMOVQBZrrkz:
33461 return true;
33462 }
33463 return false;
33464}
33465
33466bool isVBLENDVPS(unsigned Opcode) {
33467 switch (Opcode) {
33468 case VBLENDVPSYrmr:
33469 case VBLENDVPSYrrr:
33470 case VBLENDVPSrmr:
33471 case VBLENDVPSrrr:
33472 return true;
33473 }
33474 return false;
33475}
33476
33477bool isKSHIFTLQ(unsigned Opcode) {
33478 return Opcode == KSHIFTLQki;
33479}
33480
33481bool isPMOVSXWD(unsigned Opcode) {
33482 switch (Opcode) {
33483 case PMOVSXWDrm:
33484 case PMOVSXWDrr:
33485 return true;
33486 }
33487 return false;
33488}
33489
33490bool isPHSUBSW(unsigned Opcode) {
33491 switch (Opcode) {
33492 case MMX_PHSUBSWrm:
33493 case MMX_PHSUBSWrr:
33494 case PHSUBSWrm:
33495 case PHSUBSWrr:
33496 return true;
33497 }
33498 return false;
33499}
33500
33501bool isPSRLQ(unsigned Opcode) {
33502 switch (Opcode) {
33503 case MMX_PSRLQri:
33504 case MMX_PSRLQrm:
33505 case MMX_PSRLQrr:
33506 case PSRLQri:
33507 case PSRLQrm:
33508 case PSRLQrr:
33509 return true;
33510 }
33511 return false;
33512}
33513
33514bool isVCVTPH2DQ(unsigned Opcode) {
33515 switch (Opcode) {
33516 case VCVTPH2DQZ128rm:
33517 case VCVTPH2DQZ128rmb:
33518 case VCVTPH2DQZ128rmbk:
33519 case VCVTPH2DQZ128rmbkz:
33520 case VCVTPH2DQZ128rmk:
33521 case VCVTPH2DQZ128rmkz:
33522 case VCVTPH2DQZ128rr:
33523 case VCVTPH2DQZ128rrk:
33524 case VCVTPH2DQZ128rrkz:
33525 case VCVTPH2DQZ256rm:
33526 case VCVTPH2DQZ256rmb:
33527 case VCVTPH2DQZ256rmbk:
33528 case VCVTPH2DQZ256rmbkz:
33529 case VCVTPH2DQZ256rmk:
33530 case VCVTPH2DQZ256rmkz:
33531 case VCVTPH2DQZ256rr:
33532 case VCVTPH2DQZ256rrk:
33533 case VCVTPH2DQZ256rrkz:
33534 case VCVTPH2DQZrm:
33535 case VCVTPH2DQZrmb:
33536 case VCVTPH2DQZrmbk:
33537 case VCVTPH2DQZrmbkz:
33538 case VCVTPH2DQZrmk:
33539 case VCVTPH2DQZrmkz:
33540 case VCVTPH2DQZrr:
33541 case VCVTPH2DQZrrb:
33542 case VCVTPH2DQZrrbk:
33543 case VCVTPH2DQZrrbkz:
33544 case VCVTPH2DQZrrk:
33545 case VCVTPH2DQZrrkz:
33546 return true;
33547 }
33548 return false;
33549}
33550
33551bool isPCMPESTRIQ(unsigned Opcode) {
33552 switch (Opcode) {
33553 case PCMPESTRIQrmi:
33554 case PCMPESTRIQrri:
33555 return true;
33556 }
33557 return false;
33558}
33559
33560bool isFISUB(unsigned Opcode) {
33561 switch (Opcode) {
33562 case SUB_FI16m:
33563 case SUB_FI32m:
33564 return true;
33565 }
33566 return false;
33567}
33568
33569bool isVCVTPS2UDQ(unsigned Opcode) {
33570 switch (Opcode) {
33571 case VCVTPS2UDQZ128rm:
33572 case VCVTPS2UDQZ128rmb:
33573 case VCVTPS2UDQZ128rmbk:
33574 case VCVTPS2UDQZ128rmbkz:
33575 case VCVTPS2UDQZ128rmk:
33576 case VCVTPS2UDQZ128rmkz:
33577 case VCVTPS2UDQZ128rr:
33578 case VCVTPS2UDQZ128rrk:
33579 case VCVTPS2UDQZ128rrkz:
33580 case VCVTPS2UDQZ256rm:
33581 case VCVTPS2UDQZ256rmb:
33582 case VCVTPS2UDQZ256rmbk:
33583 case VCVTPS2UDQZ256rmbkz:
33584 case VCVTPS2UDQZ256rmk:
33585 case VCVTPS2UDQZ256rmkz:
33586 case VCVTPS2UDQZ256rr:
33587 case VCVTPS2UDQZ256rrk:
33588 case VCVTPS2UDQZ256rrkz:
33589 case VCVTPS2UDQZrm:
33590 case VCVTPS2UDQZrmb:
33591 case VCVTPS2UDQZrmbk:
33592 case VCVTPS2UDQZrmbkz:
33593 case VCVTPS2UDQZrmk:
33594 case VCVTPS2UDQZrmkz:
33595 case VCVTPS2UDQZrr:
33596 case VCVTPS2UDQZrrb:
33597 case VCVTPS2UDQZrrbk:
33598 case VCVTPS2UDQZrrbkz:
33599 case VCVTPS2UDQZrrk:
33600 case VCVTPS2UDQZrrkz:
33601 return true;
33602 }
33603 return false;
33604}
33605
33606bool isVMOVDDUP(unsigned Opcode) {
33607 switch (Opcode) {
33608 case VMOVDDUPYrm:
33609 case VMOVDDUPYrr:
33610 case VMOVDDUPZ128rm:
33611 case VMOVDDUPZ128rmk:
33612 case VMOVDDUPZ128rmkz:
33613 case VMOVDDUPZ128rr:
33614 case VMOVDDUPZ128rrk:
33615 case VMOVDDUPZ128rrkz:
33616 case VMOVDDUPZ256rm:
33617 case VMOVDDUPZ256rmk:
33618 case VMOVDDUPZ256rmkz:
33619 case VMOVDDUPZ256rr:
33620 case VMOVDDUPZ256rrk:
33621 case VMOVDDUPZ256rrkz:
33622 case VMOVDDUPZrm:
33623 case VMOVDDUPZrmk:
33624 case VMOVDDUPZrmkz:
33625 case VMOVDDUPZrr:
33626 case VMOVDDUPZrrk:
33627 case VMOVDDUPZrrkz:
33628 case VMOVDDUPrm:
33629 case VMOVDDUPrr:
33630 return true;
33631 }
33632 return false;
33633}
33634
33635bool isPCMPEQD(unsigned Opcode) {
33636 switch (Opcode) {
33637 case MMX_PCMPEQDrm:
33638 case MMX_PCMPEQDrr:
33639 case PCMPEQDrm:
33640 case PCMPEQDrr:
33641 return true;
33642 }
33643 return false;
33644}
33645
33646bool isVRSQRT28SD(unsigned Opcode) {
33647 switch (Opcode) {
33648 case VRSQRT28SDZm:
33649 case VRSQRT28SDZmk:
33650 case VRSQRT28SDZmkz:
33651 case VRSQRT28SDZr:
33652 case VRSQRT28SDZrb:
33653 case VRSQRT28SDZrbk:
33654 case VRSQRT28SDZrbkz:
33655 case VRSQRT28SDZrk:
33656 case VRSQRT28SDZrkz:
33657 return true;
33658 }
33659 return false;
33660}
33661
33662bool isTDPHBF8PS(unsigned Opcode) {
33663 return Opcode == TDPHBF8PS;
33664}
33665
33666bool isLODSW(unsigned Opcode) {
33667 return Opcode == LODSW;
33668}
33669
33670bool isVPOPCNTQ(unsigned Opcode) {
33671 switch (Opcode) {
33672 case VPOPCNTQZ128rm:
33673 case VPOPCNTQZ128rmb:
33674 case VPOPCNTQZ128rmbk:
33675 case VPOPCNTQZ128rmbkz:
33676 case VPOPCNTQZ128rmk:
33677 case VPOPCNTQZ128rmkz:
33678 case VPOPCNTQZ128rr:
33679 case VPOPCNTQZ128rrk:
33680 case VPOPCNTQZ128rrkz:
33681 case VPOPCNTQZ256rm:
33682 case VPOPCNTQZ256rmb:
33683 case VPOPCNTQZ256rmbk:
33684 case VPOPCNTQZ256rmbkz:
33685 case VPOPCNTQZ256rmk:
33686 case VPOPCNTQZ256rmkz:
33687 case VPOPCNTQZ256rr:
33688 case VPOPCNTQZ256rrk:
33689 case VPOPCNTQZ256rrkz:
33690 case VPOPCNTQZrm:
33691 case VPOPCNTQZrmb:
33692 case VPOPCNTQZrmbk:
33693 case VPOPCNTQZrmbkz:
33694 case VPOPCNTQZrmk:
33695 case VPOPCNTQZrmkz:
33696 case VPOPCNTQZrr:
33697 case VPOPCNTQZrrk:
33698 case VPOPCNTQZrrkz:
33699 return true;
33700 }
33701 return false;
33702}
33703
33704bool isKSHIFTRB(unsigned Opcode) {
33705 return Opcode == KSHIFTRBki;
33706}
33707
33708bool isVFNMADDPS(unsigned Opcode) {
33709 switch (Opcode) {
33710 case VFNMADDPS4Ymr:
33711 case VFNMADDPS4Yrm:
33712 case VFNMADDPS4Yrr:
33713 case VFNMADDPS4Yrr_REV:
33714 case VFNMADDPS4mr:
33715 case VFNMADDPS4rm:
33716 case VFNMADDPS4rr:
33717 case VFNMADDPS4rr_REV:
33718 return true;
33719 }
33720 return false;
33721}
33722
33723bool isCCMPCC(unsigned Opcode) {
33724 switch (Opcode) {
33725 case CCMP16mi:
33726 case CCMP16mi8:
33727 case CCMP16mr:
33728 case CCMP16ri:
33729 case CCMP16ri8:
33730 case CCMP16rm:
33731 case CCMP16rr:
33732 case CCMP16rr_REV:
33733 case CCMP32mi:
33734 case CCMP32mi8:
33735 case CCMP32mr:
33736 case CCMP32ri:
33737 case CCMP32ri8:
33738 case CCMP32rm:
33739 case CCMP32rr:
33740 case CCMP32rr_REV:
33741 case CCMP64mi32:
33742 case CCMP64mi8:
33743 case CCMP64mr:
33744 case CCMP64ri32:
33745 case CCMP64ri8:
33746 case CCMP64rm:
33747 case CCMP64rr:
33748 case CCMP64rr_REV:
33749 case CCMP8mi:
33750 case CCMP8mr:
33751 case CCMP8ri:
33752 case CCMP8rm:
33753 case CCMP8rr:
33754 case CCMP8rr_REV:
33755 return true;
33756 }
33757 return false;
33758}
33759
33760bool isFXRSTOR64(unsigned Opcode) {
33761 return Opcode == FXRSTOR64;
33762}
33763
33764bool isVFMSUBADD213PD(unsigned Opcode) {
33765 switch (Opcode) {
33766 case VFMSUBADD213PDYm:
33767 case VFMSUBADD213PDYr:
33768 case VFMSUBADD213PDZ128m:
33769 case VFMSUBADD213PDZ128mb:
33770 case VFMSUBADD213PDZ128mbk:
33771 case VFMSUBADD213PDZ128mbkz:
33772 case VFMSUBADD213PDZ128mk:
33773 case VFMSUBADD213PDZ128mkz:
33774 case VFMSUBADD213PDZ128r:
33775 case VFMSUBADD213PDZ128rk:
33776 case VFMSUBADD213PDZ128rkz:
33777 case VFMSUBADD213PDZ256m:
33778 case VFMSUBADD213PDZ256mb:
33779 case VFMSUBADD213PDZ256mbk:
33780 case VFMSUBADD213PDZ256mbkz:
33781 case VFMSUBADD213PDZ256mk:
33782 case VFMSUBADD213PDZ256mkz:
33783 case VFMSUBADD213PDZ256r:
33784 case VFMSUBADD213PDZ256rk:
33785 case VFMSUBADD213PDZ256rkz:
33786 case VFMSUBADD213PDZm:
33787 case VFMSUBADD213PDZmb:
33788 case VFMSUBADD213PDZmbk:
33789 case VFMSUBADD213PDZmbkz:
33790 case VFMSUBADD213PDZmk:
33791 case VFMSUBADD213PDZmkz:
33792 case VFMSUBADD213PDZr:
33793 case VFMSUBADD213PDZrb:
33794 case VFMSUBADD213PDZrbk:
33795 case VFMSUBADD213PDZrbkz:
33796 case VFMSUBADD213PDZrk:
33797 case VFMSUBADD213PDZrkz:
33798 case VFMSUBADD213PDm:
33799 case VFMSUBADD213PDr:
33800 return true;
33801 }
33802 return false;
33803}
33804
33805bool isVSQRTPH(unsigned Opcode) {
33806 switch (Opcode) {
33807 case VSQRTPHZ128m:
33808 case VSQRTPHZ128mb:
33809 case VSQRTPHZ128mbk:
33810 case VSQRTPHZ128mbkz:
33811 case VSQRTPHZ128mk:
33812 case VSQRTPHZ128mkz:
33813 case VSQRTPHZ128r:
33814 case VSQRTPHZ128rk:
33815 case VSQRTPHZ128rkz:
33816 case VSQRTPHZ256m:
33817 case VSQRTPHZ256mb:
33818 case VSQRTPHZ256mbk:
33819 case VSQRTPHZ256mbkz:
33820 case VSQRTPHZ256mk:
33821 case VSQRTPHZ256mkz:
33822 case VSQRTPHZ256r:
33823 case VSQRTPHZ256rk:
33824 case VSQRTPHZ256rkz:
33825 case VSQRTPHZm:
33826 case VSQRTPHZmb:
33827 case VSQRTPHZmbk:
33828 case VSQRTPHZmbkz:
33829 case VSQRTPHZmk:
33830 case VSQRTPHZmkz:
33831 case VSQRTPHZr:
33832 case VSQRTPHZrb:
33833 case VSQRTPHZrbk:
33834 case VSQRTPHZrbkz:
33835 case VSQRTPHZrk:
33836 case VSQRTPHZrkz:
33837 return true;
33838 }
33839 return false;
33840}
33841
33842bool isPOPF(unsigned Opcode) {
33843 return Opcode == POPF16;
33844}
33845
33846bool isVPSUBUSB(unsigned Opcode) {
33847 switch (Opcode) {
33848 case VPSUBUSBYrm:
33849 case VPSUBUSBYrr:
33850 case VPSUBUSBZ128rm:
33851 case VPSUBUSBZ128rmk:
33852 case VPSUBUSBZ128rmkz:
33853 case VPSUBUSBZ128rr:
33854 case VPSUBUSBZ128rrk:
33855 case VPSUBUSBZ128rrkz:
33856 case VPSUBUSBZ256rm:
33857 case VPSUBUSBZ256rmk:
33858 case VPSUBUSBZ256rmkz:
33859 case VPSUBUSBZ256rr:
33860 case VPSUBUSBZ256rrk:
33861 case VPSUBUSBZ256rrkz:
33862 case VPSUBUSBZrm:
33863 case VPSUBUSBZrmk:
33864 case VPSUBUSBZrmkz:
33865 case VPSUBUSBZrr:
33866 case VPSUBUSBZrrk:
33867 case VPSUBUSBZrrkz:
33868 case VPSUBUSBrm:
33869 case VPSUBUSBrr:
33870 return true;
33871 }
33872 return false;
33873}
33874
33875bool isTCVTROWPS2BF16L(unsigned Opcode) {
33876 switch (Opcode) {
33877 case TCVTROWPS2BF16Lrte:
33878 case TCVTROWPS2BF16Lrti:
33879 return true;
33880 }
33881 return false;
33882}
33883
33884bool isVPADDSW(unsigned Opcode) {
33885 switch (Opcode) {
33886 case VPADDSWYrm:
33887 case VPADDSWYrr:
33888 case VPADDSWZ128rm:
33889 case VPADDSWZ128rmk:
33890 case VPADDSWZ128rmkz:
33891 case VPADDSWZ128rr:
33892 case VPADDSWZ128rrk:
33893 case VPADDSWZ128rrkz:
33894 case VPADDSWZ256rm:
33895 case VPADDSWZ256rmk:
33896 case VPADDSWZ256rmkz:
33897 case VPADDSWZ256rr:
33898 case VPADDSWZ256rrk:
33899 case VPADDSWZ256rrkz:
33900 case VPADDSWZrm:
33901 case VPADDSWZrmk:
33902 case VPADDSWZrmkz:
33903 case VPADDSWZrr:
33904 case VPADDSWZrrk:
33905 case VPADDSWZrrkz:
33906 case VPADDSWrm:
33907 case VPADDSWrr:
33908 return true;
33909 }
33910 return false;
33911}
33912
33913bool isPREFETCHIT1(unsigned Opcode) {
33914 return Opcode == PREFETCHIT1;
33915}
33916
33917bool isVADDSUBPD(unsigned Opcode) {
33918 switch (Opcode) {
33919 case VADDSUBPDYrm:
33920 case VADDSUBPDYrr:
33921 case VADDSUBPDrm:
33922 case VADDSUBPDrr:
33923 return true;
33924 }
33925 return false;
33926}
33927
33928bool isKANDD(unsigned Opcode) {
33929 return Opcode == KANDDkk;
33930}
33931
33932bool isPREFETCHRST2(unsigned Opcode) {
33933 return Opcode == PREFETCHRST2;
33934}
33935
33936bool isOUTSB(unsigned Opcode) {
33937 return Opcode == OUTSB;
33938}
33939
33940bool isFNSTSW(unsigned Opcode) {
33941 switch (Opcode) {
33942 case FNSTSW16r:
33943 case FNSTSWm:
33944 return true;
33945 }
33946 return false;
33947}
33948
33949bool isPMINSB(unsigned Opcode) {
33950 switch (Opcode) {
33951 case PMINSBrm:
33952 case PMINSBrr:
33953 return true;
33954 }
33955 return false;
33956}
33957
33958
33959} // namespace llvm::X86
33960
33961#endif // GET_X86_MNEMONIC_TABLES_CPP
33962
33963