1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* X86 Mnemonic tables *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_X86_MNEMONIC_TABLES_H
10#undef GET_X86_MNEMONIC_TABLES_H
11
12namespace llvm::X86 {
13
14bool isFSUBRP(unsigned Opcode);
15bool isVPDPBUSDS(unsigned Opcode);
16bool isPUNPCKLWD(unsigned Opcode);
17bool isVREDUCEBF16(unsigned Opcode);
18bool isPUNPCKLQDQ(unsigned Opcode);
19bool isRDFSBASE(unsigned Opcode);
20bool isVPCMOV(unsigned Opcode);
21bool isVDIVSD(unsigned Opcode);
22bool isVCVTTPS2IBS(unsigned Opcode);
23bool isVPEXTRW(unsigned Opcode);
24bool isLODSD(unsigned Opcode);
25bool isVPTESTNMQ(unsigned Opcode);
26bool isCVTSS2SD(unsigned Opcode);
27bool isVGETMANTPD(unsigned Opcode);
28bool isVMOVDQA64(unsigned Opcode);
29bool isINVLPG(unsigned Opcode);
30bool isVGETEXPBF16(unsigned Opcode);
31bool isVBROADCASTF64X4(unsigned Opcode);
32bool isVPERMI2Q(unsigned Opcode);
33bool isVPMOVSXBD(unsigned Opcode);
34bool isVFMSUB132SS(unsigned Opcode);
35bool isVPMOVUSDW(unsigned Opcode);
36bool isAAD(unsigned Opcode);
37bool isIDIV(unsigned Opcode);
38bool isCVTTPS2DQ(unsigned Opcode);
39bool isVBROADCASTF32X8(unsigned Opcode);
40bool isVFMSUBSS(unsigned Opcode);
41bool isEMMS(unsigned Opcode);
42bool isVPDPBSUD(unsigned Opcode);
43bool isPMOVSXWQ(unsigned Opcode);
44bool isPSRLW(unsigned Opcode);
45bool isMOVNTDQA(unsigned Opcode);
46bool isFUCOMPI(unsigned Opcode);
47bool isANDNPS(unsigned Opcode);
48bool isVINSERTF64X2(unsigned Opcode);
49bool isCLTS(unsigned Opcode);
50bool isSETSSBSY(unsigned Opcode);
51bool isVMULPD(unsigned Opcode);
52bool isVFMADDSUB132PS(unsigned Opcode);
53bool isVPMADCSWD(unsigned Opcode);
54bool isVSCATTERPF0DPS(unsigned Opcode);
55bool isXCHG(unsigned Opcode);
56bool isVGATHERPF1QPS(unsigned Opcode);
57bool isVCVTNEPS2BF16(unsigned Opcode);
58bool isVFMADDSS(unsigned Opcode);
59bool isINTO(unsigned Opcode);
60bool isANDPD(unsigned Opcode);
61bool isSEAMCALL(unsigned Opcode);
62bool isVPDPBSSDS(unsigned Opcode);
63bool isUNPCKHPS(unsigned Opcode);
64bool isSETZUCC(unsigned Opcode);
65bool isSHUFPD(unsigned Opcode);
66bool isFCMOVNB(unsigned Opcode);
67bool isCVTTSS2SI(unsigned Opcode);
68bool isEXTRQ(unsigned Opcode);
69bool isSHLD(unsigned Opcode);
70bool isVBROADCASTSS(unsigned Opcode);
71bool isCLUI(unsigned Opcode);
72bool isVINSERTI128(unsigned Opcode);
73bool isVBLENDPD(unsigned Opcode);
74bool isVPSHLDW(unsigned Opcode);
75bool isVCVTNEEPH2PS(unsigned Opcode);
76bool isVCVTTSD2SI(unsigned Opcode);
77bool isVSM4KEY4(unsigned Opcode);
78bool isWRMSRNS(unsigned Opcode);
79bool isCMPSB(unsigned Opcode);
80bool isVRCPBF16(unsigned Opcode);
81bool isMULSS(unsigned Opcode);
82bool isVMRUN(unsigned Opcode);
83bool isVPSRLVD(unsigned Opcode);
84bool isLEAVE(unsigned Opcode);
85bool isVGETMANTPS(unsigned Opcode);
86bool isXSHA256(unsigned Opcode);
87bool isBOUND(unsigned Opcode);
88bool isSFENCE(unsigned Opcode);
89bool isVPHADDD(unsigned Opcode);
90bool isADOX(unsigned Opcode);
91bool isVPSLLQ(unsigned Opcode);
92bool isVCVTPH2HF8(unsigned Opcode);
93bool isPFRSQIT1(unsigned Opcode);
94bool isCLAC(unsigned Opcode);
95bool isKNOTW(unsigned Opcode);
96bool isVCVTPH2PD(unsigned Opcode);
97bool isVAESENC(unsigned Opcode);
98bool isMOVNTI(unsigned Opcode);
99bool isFXCH(unsigned Opcode);
100bool isPOPP(unsigned Opcode);
101bool isVPBLENDMD(unsigned Opcode);
102bool isFSINCOS(unsigned Opcode);
103bool isVPMULLW(unsigned Opcode);
104bool isVPMOVSXBW(unsigned Opcode);
105bool isSTC(unsigned Opcode);
106bool isVPINSRB(unsigned Opcode);
107bool isLWPVAL(unsigned Opcode);
108bool isKXORB(unsigned Opcode);
109bool isRSTORSSP(unsigned Opcode);
110bool isVPRORQ(unsigned Opcode);
111bool isVSM3MSG1(unsigned Opcode);
112bool isFICOM(unsigned Opcode);
113bool isMAXPS(unsigned Opcode);
114bool isFNCLEX(unsigned Opcode);
115bool isVMOVMSKPS(unsigned Opcode);
116bool isVPMOVDB(unsigned Opcode);
117bool isLLWPCB(unsigned Opcode);
118bool isVMULSS(unsigned Opcode);
119bool isAESENCLAST(unsigned Opcode);
120bool isTILEMOVROW(unsigned Opcode);
121bool isVMINMAXPH(unsigned Opcode);
122bool isVPMAXUB(unsigned Opcode);
123bool isAAS(unsigned Opcode);
124bool isFADD(unsigned Opcode);
125bool isJMP(unsigned Opcode);
126bool isXCRYPTECB(unsigned Opcode);
127bool isPFRCPIT1(unsigned Opcode);
128bool isPMULHRW(unsigned Opcode);
129bool isVCVTPH2PS(unsigned Opcode);
130bool isVPBLENDVB(unsigned Opcode);
131bool isPCMPESTRI(unsigned Opcode);
132bool isSENDUIPI(unsigned Opcode);
133bool isFLDLN2(unsigned Opcode);
134bool isVPMACSWD(unsigned Opcode);
135bool isSHA1MSG1(unsigned Opcode);
136bool isVADDPS(unsigned Opcode);
137bool isVCVTPS2DQ(unsigned Opcode);
138bool isPFPNACC(unsigned Opcode);
139bool isFMUL(unsigned Opcode);
140bool isFNSAVE(unsigned Opcode);
141bool isCDQE(unsigned Opcode);
142bool isVPMACSDD(unsigned Opcode);
143bool isVSQRTPS(unsigned Opcode);
144bool isCMPSQ(unsigned Opcode);
145bool isVPSCATTERDD(unsigned Opcode);
146bool isVCVTTSD2USIS(unsigned Opcode);
147bool isVRNDSCALESD(unsigned Opcode);
148bool isSUBPS(unsigned Opcode);
149bool isVMAXSH(unsigned Opcode);
150bool isFLDZ(unsigned Opcode);
151bool isVFNMADD132SS(unsigned Opcode);
152bool isLGDTW(unsigned Opcode);
153bool isTCVTROWPS2PHH(unsigned Opcode);
154bool isINC(unsigned Opcode);
155bool isVPANDN(unsigned Opcode);
156bool isPABSB(unsigned Opcode);
157bool isVSHA512RNDS2(unsigned Opcode);
158bool isPHADDSW(unsigned Opcode);
159bool isVPMAXUD(unsigned Opcode);
160bool isVPMOVSQW(unsigned Opcode);
161bool isADDSUBPS(unsigned Opcode);
162bool isVPMACSSDQL(unsigned Opcode);
163bool isPXOR(unsigned Opcode);
164bool isVPSRAD(unsigned Opcode);
165bool isVPSHAB(unsigned Opcode);
166bool isBTR(unsigned Opcode);
167bool isKORW(unsigned Opcode);
168bool isVRANGESS(unsigned Opcode);
169bool isVCMPPS(unsigned Opcode);
170bool isVPLZCNTD(unsigned Opcode);
171bool isTDPBUUD(unsigned Opcode);
172bool isROUNDPS(unsigned Opcode);
173bool isFABS(unsigned Opcode);
174bool isSUBPD(unsigned Opcode);
175bool isGF2P8MULB(unsigned Opcode);
176bool isTZMSK(unsigned Opcode);
177bool isVMINMAXSD(unsigned Opcode);
178bool isANDPS(unsigned Opcode);
179bool isVEXTRACTF32X8(unsigned Opcode);
180bool isSEAMRET(unsigned Opcode);
181bool isVPCOMW(unsigned Opcode);
182bool isVFIXUPIMMPD(unsigned Opcode);
183bool isKANDND(unsigned Opcode);
184bool isVMRESUME(unsigned Opcode);
185bool isCVTPD2DQ(unsigned Opcode);
186bool isVFNMADD213PS(unsigned Opcode);
187bool isVPEXTRD(unsigned Opcode);
188bool isPACKUSWB(unsigned Opcode);
189bool isVEXTRACTI32X8(unsigned Opcode);
190bool isVHADDPD(unsigned Opcode);
191bool isVPSADBW(unsigned Opcode);
192bool isMOVDQ2Q(unsigned Opcode);
193bool isPUNPCKHBW(unsigned Opcode);
194bool isXOR(unsigned Opcode);
195bool isPSIGNB(unsigned Opcode);
196bool isVPHADDSW(unsigned Opcode);
197bool isFADDP(unsigned Opcode);
198bool isNEG(unsigned Opcode);
199bool isFLDLG2(unsigned Opcode);
200bool isFNOP(unsigned Opcode);
201bool isVMINSS(unsigned Opcode);
202bool isPCMPISTRM(unsigned Opcode);
203bool isVFMADD132SS(unsigned Opcode);
204bool isFDIVRP(unsigned Opcode);
205bool isPUSHAL(unsigned Opcode);
206bool isVPMACSDQL(unsigned Opcode);
207bool isSUBSD(unsigned Opcode);
208bool isVPBLENDMQ(unsigned Opcode);
209bool isVGATHERDPS(unsigned Opcode);
210bool isSYSRET(unsigned Opcode);
211bool isVPADDB(unsigned Opcode);
212bool isXEND(unsigned Opcode);
213bool isWRSSD(unsigned Opcode);
214bool isVMINMAXSS(unsigned Opcode);
215bool isVCVTDQ2PH(unsigned Opcode);
216bool isCVTPD2PS(unsigned Opcode);
217bool isMAXPD(unsigned Opcode);
218bool isRCPSS(unsigned Opcode);
219bool isVMOVAPD(unsigned Opcode);
220bool isVPSUBSB(unsigned Opcode);
221bool isRDTSC(unsigned Opcode);
222bool isVCVTTPS2UDQS(unsigned Opcode);
223bool isVPMADCSSWD(unsigned Opcode);
224bool isVFNMADD213PH(unsigned Opcode);
225bool isVGF2P8AFFINEQB(unsigned Opcode);
226bool isPMOVZXWD(unsigned Opcode);
227bool isPMINUD(unsigned Opcode);
228bool isVCVTPH2UW(unsigned Opcode);
229bool isPADDSW(unsigned Opcode);
230bool isXSUSLDTRK(unsigned Opcode);
231bool isLFENCE(unsigned Opcode);
232bool isCRC32(unsigned Opcode);
233bool isAESENCWIDE256KL(unsigned Opcode);
234bool isMOVAPD(unsigned Opcode);
235bool isVFMADD213PS(unsigned Opcode);
236bool isVPDPWUUDS(unsigned Opcode);
237bool isMOVSLDUP(unsigned Opcode);
238bool isCLDEMOTE(unsigned Opcode);
239bool isVFNMADD231PS(unsigned Opcode);
240bool isVMOVMSKPD(unsigned Opcode);
241bool isPREFETCHT0(unsigned Opcode);
242bool isVCVTNEOBF162PS(unsigned Opcode);
243bool isVPCMPUD(unsigned Opcode);
244bool isVMAXSD(unsigned Opcode);
245bool isVRCP28SD(unsigned Opcode);
246bool isVMAXPS(unsigned Opcode);
247bool isVPMOVD2M(unsigned Opcode);
248bool isVPMACSSWD(unsigned Opcode);
249bool isVUCOMISD(unsigned Opcode);
250bool isLTR(unsigned Opcode);
251bool isVCVTUSI2SH(unsigned Opcode);
252bool isVSCATTERPF1QPS(unsigned Opcode);
253bool isWRGSBASE(unsigned Opcode);
254bool isSTOSQ(unsigned Opcode);
255bool isVSQRTSD(unsigned Opcode);
256bool isVPERMIL2PD(unsigned Opcode);
257bool isVFCMADDCSH(unsigned Opcode);
258bool isVFMADDSUB213PS(unsigned Opcode);
259bool isPFSUB(unsigned Opcode);
260bool isVSQRTSS(unsigned Opcode);
261bool isVEXPANDPS(unsigned Opcode);
262bool isVPCOMPRESSW(unsigned Opcode);
263bool isPEXTRD(unsigned Opcode);
264bool isVCVTTPS2UQQS(unsigned Opcode);
265bool isSYSEXITQ(unsigned Opcode);
266bool isROUNDSD(unsigned Opcode);
267bool isVFMADD132BF16(unsigned Opcode);
268bool isFCOM(unsigned Opcode);
269bool isVFNMSUBSS(unsigned Opcode);
270bool isKSHIFTLW(unsigned Opcode);
271bool isSCASD(unsigned Opcode);
272bool isVMPTRLD(unsigned Opcode);
273bool isVAESDECLAST(unsigned Opcode);
274bool isVFMADDSUBPS(unsigned Opcode);
275bool isVCVTUQQ2PS(unsigned Opcode);
276bool isVPMOVUSDB(unsigned Opcode);
277bool isVPROTW(unsigned Opcode);
278bool isVDPPS(unsigned Opcode);
279bool isVRSQRT14PD(unsigned Opcode);
280bool isVTESTPD(unsigned Opcode);
281bool isVFNMADD231SH(unsigned Opcode);
282bool isENDBR64(unsigned Opcode);
283bool isMULSD(unsigned Opcode);
284bool isXRSTORS(unsigned Opcode);
285bool isPREFETCHNTA(unsigned Opcode);
286bool isVPCOMD(unsigned Opcode);
287bool isVPCOMUB(unsigned Opcode);
288bool isVPHSUBD(unsigned Opcode);
289bool isVBROADCASTI64X2(unsigned Opcode);
290bool isFPATAN(unsigned Opcode);
291bool isLOOPE(unsigned Opcode);
292bool isPCMPEQW(unsigned Opcode);
293bool isVFMADDCSH(unsigned Opcode);
294bool isVPDPBSSD(unsigned Opcode);
295bool isMOVRS(unsigned Opcode);
296bool isVFMSUBADD132PH(unsigned Opcode);
297bool isKADDW(unsigned Opcode);
298bool isPTEST(unsigned Opcode);
299bool isVRSQRT28PS(unsigned Opcode);
300bool isVGF2P8AFFINEINVQB(unsigned Opcode);
301bool isSERIALIZE(unsigned Opcode);
302bool isVPHADDWQ(unsigned Opcode);
303bool isVRNDSCALESH(unsigned Opcode);
304bool isAAA(unsigned Opcode);
305bool isVADDBF16(unsigned Opcode);
306bool isWRMSRLIST(unsigned Opcode);
307bool isVCVTPH2PSX(unsigned Opcode);
308bool isVFMSUB231PH(unsigned Opcode);
309bool isVGATHERQPD(unsigned Opcode);
310bool isKADDB(unsigned Opcode);
311bool isCVTPD2PI(unsigned Opcode);
312bool isVFNMSUB213PH(unsigned Opcode);
313bool isXORPS(unsigned Opcode);
314bool isVPCMPESTRI(unsigned Opcode);
315bool isVPADDSB(unsigned Opcode);
316bool isPOP2(unsigned Opcode);
317bool isRDMSRLIST(unsigned Opcode);
318bool isVPSHRDW(unsigned Opcode);
319bool isVPDPBUSD(unsigned Opcode);
320bool isVCMPPH(unsigned Opcode);
321bool isVANDNPD(unsigned Opcode);
322bool isSUB(unsigned Opcode);
323bool isVRSQRT28PD(unsigned Opcode);
324bool isVFNMADD132PH(unsigned Opcode);
325bool isVPMACSSWW(unsigned Opcode);
326bool isXSTORE(unsigned Opcode);
327bool isVPROTQ(unsigned Opcode);
328bool isVPHADDBD(unsigned Opcode);
329bool isVPMAXSB(unsigned Opcode);
330bool isVMOVDQU8(unsigned Opcode);
331bool isVPMOVSXWD(unsigned Opcode);
332bool isVMINMAXPD(unsigned Opcode);
333bool isSHA256RNDS2(unsigned Opcode);
334bool isKANDB(unsigned Opcode);
335bool isTPAUSE(unsigned Opcode);
336bool isPUSH(unsigned Opcode);
337bool isVRNDSCALESS(unsigned Opcode);
338bool isVRNDSCALEBF16(unsigned Opcode);
339bool isVPCMPISTRI(unsigned Opcode);
340bool isSTGI(unsigned Opcode);
341bool isSBB(unsigned Opcode);
342bool isBLCS(unsigned Opcode);
343bool isVCVTSD2SH(unsigned Opcode);
344bool isVPERMW(unsigned Opcode);
345bool isXRESLDTRK(unsigned Opcode);
346bool isAESENC256KL(unsigned Opcode);
347bool isVGATHERDPD(unsigned Opcode);
348bool isHRESET(unsigned Opcode);
349bool isVFMSUBADD231PD(unsigned Opcode);
350bool isVFRCZSS(unsigned Opcode);
351bool isMINPS(unsigned Opcode);
352bool isFPREM1(unsigned Opcode);
353bool isVPCMPUB(unsigned Opcode);
354bool isVSQRTPD(unsigned Opcode);
355bool isVFRCZPS(unsigned Opcode);
356bool isVFNMADD213SS(unsigned Opcode);
357bool isVPMOVDW(unsigned Opcode);
358bool isVCVTPH2HF8S(unsigned Opcode);
359bool isVPSHRDVQ(unsigned Opcode);
360bool isVBROADCASTSD(unsigned Opcode);
361bool isVSHUFPD(unsigned Opcode);
362bool isVPSUBSW(unsigned Opcode);
363bool isKUNPCKBW(unsigned Opcode);
364bool isVPBLENDD(unsigned Opcode);
365bool isUNPCKHPD(unsigned Opcode);
366bool isVFNMADD231SD(unsigned Opcode);
367bool isVPBROADCASTMW2D(unsigned Opcode);
368bool isVPMULTISHIFTQB(unsigned Opcode);
369bool isVP2INTERSECTQ(unsigned Opcode);
370bool isVFNMSUB132BF16(unsigned Opcode);
371bool isVFMADD213BF16(unsigned Opcode);
372bool isVPUNPCKHWD(unsigned Opcode);
373bool isVPERM2F128(unsigned Opcode);
374bool isINSD(unsigned Opcode);
375bool isLFS(unsigned Opcode);
376bool isFMULP(unsigned Opcode);
377bool isCWD(unsigned Opcode);
378bool isVDIVSS(unsigned Opcode);
379bool isVPSRLQ(unsigned Opcode);
380bool isFSQRT(unsigned Opcode);
381bool isJRCXZ(unsigned Opcode);
382bool isVPMOVMSKB(unsigned Opcode);
383bool isAESDEC256KL(unsigned Opcode);
384bool isFLDENV(unsigned Opcode);
385bool isVPHSUBWD(unsigned Opcode);
386bool isWBNOINVD(unsigned Opcode);
387bool isVEXPANDPD(unsigned Opcode);
388bool isFYL2XP1(unsigned Opcode);
389bool isPREFETCHT2(unsigned Opcode);
390bool isVPDPBSUDS(unsigned Opcode);
391bool isVSHA512MSG2(unsigned Opcode);
392bool isPMULHUW(unsigned Opcode);
393bool isKANDNB(unsigned Opcode);
394bool isVCVTUW2PH(unsigned Opcode);
395bool isAESDECWIDE256KL(unsigned Opcode);
396bool isVPGATHERDD(unsigned Opcode);
397bool isVREDUCESH(unsigned Opcode);
398bool isPOPFQ(unsigned Opcode);
399bool isPAVGUSB(unsigned Opcode);
400bool isVALIGND(unsigned Opcode);
401bool isVPHMINPOSUW(unsigned Opcode);
402bool isLIDTD(unsigned Opcode);
403bool isVPERMT2PD(unsigned Opcode);
404bool isVMLAUNCH(unsigned Opcode);
405bool isVPXORQ(unsigned Opcode);
406bool isMOVNTDQ(unsigned Opcode);
407bool isPOP2P(unsigned Opcode);
408bool isVADDPD(unsigned Opcode);
409bool isSMSW(unsigned Opcode);
410bool isVEXP2PD(unsigned Opcode);
411bool isPMULUDQ(unsigned Opcode);
412bool isIRET(unsigned Opcode);
413bool isMULPS(unsigned Opcode);
414bool isTDPBF8PS(unsigned Opcode);
415bool isVFNMSUBPD(unsigned Opcode);
416bool isPHADDW(unsigned Opcode);
417bool isRDSEED(unsigned Opcode);
418bool isVPSHLW(unsigned Opcode);
419bool isRMPUPDATE(unsigned Opcode);
420bool isVFMADD231PH(unsigned Opcode);
421bool isVPSHAD(unsigned Opcode);
422bool isCLWB(unsigned Opcode);
423bool isPSUBUSB(unsigned Opcode);
424bool isVCVTTSD2USI(unsigned Opcode);
425bool isVEXTRACTPS(unsigned Opcode);
426bool isMOVLPD(unsigned Opcode);
427bool isLGDTD(unsigned Opcode);
428bool isVPBROADCASTMB2Q(unsigned Opcode);
429bool isOUT(unsigned Opcode);
430bool isVMSAVE(unsigned Opcode);
431bool isVCVTQQ2PD(unsigned Opcode);
432bool isVFMADD213PH(unsigned Opcode);
433bool isFCMOVBE(unsigned Opcode);
434bool isMOVSHDUP(unsigned Opcode);
435bool isVPMOVUSQB(unsigned Opcode);
436bool isFIST(unsigned Opcode);
437bool isHADDPD(unsigned Opcode);
438bool isPACKSSWB(unsigned Opcode);
439bool isVPMACSSDQH(unsigned Opcode);
440bool isVFNMSUB132SD(unsigned Opcode);
441bool isVPMASKMOVQ(unsigned Opcode);
442bool isVCOMPRESSPD(unsigned Opcode);
443bool isVFMADD213SS(unsigned Opcode);
444bool isVPCMPQ(unsigned Opcode);
445bool isVADDSH(unsigned Opcode);
446bool isVFNMADDSD(unsigned Opcode);
447bool isUMWAIT(unsigned Opcode);
448bool isVPUNPCKHDQ(unsigned Opcode);
449bool isLCALL(unsigned Opcode);
450bool isAESDEC128KL(unsigned Opcode);
451bool isVSUBPS(unsigned Opcode);
452bool isFSTP(unsigned Opcode);
453bool isVCVTUDQ2PD(unsigned Opcode);
454bool isVPMOVSWB(unsigned Opcode);
455bool isVPANDNQ(unsigned Opcode);
456bool isSYSENTER(unsigned Opcode);
457bool isVPHADDWD(unsigned Opcode);
458bool isVMOVHPD(unsigned Opcode);
459bool isMOVHPD(unsigned Opcode);
460bool isVDIVPH(unsigned Opcode);
461bool isFFREE(unsigned Opcode);
462bool isVGATHERPF1DPS(unsigned Opcode);
463bool isVFNMADD231PD(unsigned Opcode);
464bool isVFCMULCPH(unsigned Opcode);
465bool isVPADDD(unsigned Opcode);
466bool isVSM3MSG2(unsigned Opcode);
467bool isVPCOMUQ(unsigned Opcode);
468bool isVERR(unsigned Opcode);
469bool isKORTESTQ(unsigned Opcode);
470bool isVFMSUB132SD(unsigned Opcode);
471bool isTILEZERO(unsigned Opcode);
472bool isPFADD(unsigned Opcode);
473bool isVCVTSI2SD(unsigned Opcode);
474bool isTILELOADDRS(unsigned Opcode);
475bool isVSTMXCSR(unsigned Opcode);
476bool isVCVTTSH2SI(unsigned Opcode);
477bool isRET(unsigned Opcode);
478bool isLZCNT(unsigned Opcode);
479bool isMULPD(unsigned Opcode);
480bool isVBROADCASTI32X2(unsigned Opcode);
481bool isVCVTPH2W(unsigned Opcode);
482bool isCQO(unsigned Opcode);
483bool isFSUBR(unsigned Opcode);
484bool isDPPD(unsigned Opcode);
485bool isFCOS(unsigned Opcode);
486bool isXSAVES(unsigned Opcode);
487bool isTZCNT(unsigned Opcode);
488bool isLJMP(unsigned Opcode);
489bool isCMOVCC(unsigned Opcode);
490bool isVCVTBIASPH2HF8(unsigned Opcode);
491bool isINVEPT(unsigned Opcode);
492bool isADDSUBPD(unsigned Opcode);
493bool isVMOVSHDUP(unsigned Opcode);
494bool isKSHIFTRD(unsigned Opcode);
495bool isVCVTSS2SD(unsigned Opcode);
496bool isPADDQ(unsigned Opcode);
497bool isVEXTRACTI64X4(unsigned Opcode);
498bool isVFMSUB231SS(unsigned Opcode);
499bool isVPCMPEQB(unsigned Opcode);
500bool isVPTERNLOGD(unsigned Opcode);
501bool isLEA(unsigned Opcode);
502bool isPSUBB(unsigned Opcode);
503bool isKADDQ(unsigned Opcode);
504bool isMOVSX(unsigned Opcode);
505bool isVALIGNQ(unsigned Opcode);
506bool isVCVTNE2PS2BF16(unsigned Opcode);
507bool isVPSRAW(unsigned Opcode);
508bool isVFMSUBADD231PH(unsigned Opcode);
509bool isCVTDQ2PS(unsigned Opcode);
510bool isFBLD(unsigned Opcode);
511bool isLMSW(unsigned Opcode);
512bool isWRMSR(unsigned Opcode);
513bool isMINSS(unsigned Opcode);
514bool isFSCALE(unsigned Opcode);
515bool isVFNMADD213SH(unsigned Opcode);
516bool isIMULZU(unsigned Opcode);
517bool isVPHADDUBD(unsigned Opcode);
518bool isRDSSPQ(unsigned Opcode);
519bool isVCVTBF162IBS(unsigned Opcode);
520bool isLGDT(unsigned Opcode);
521bool isVPSHLDVD(unsigned Opcode);
522bool isPFCMPGT(unsigned Opcode);
523bool isVRNDSCALEPH(unsigned Opcode);
524bool isJCXZ(unsigned Opcode);
525bool isVPMOVZXBW(unsigned Opcode);
526bool isVFMADDSUB231PD(unsigned Opcode);
527bool isVBLENDMPD(unsigned Opcode);
528bool isHSUBPS(unsigned Opcode);
529bool isPREFETCHIT0(unsigned Opcode);
530bool isKTESTD(unsigned Opcode);
531bool isVCVTNEOPH2PS(unsigned Opcode);
532bool isVBLENDVPD(unsigned Opcode);
533bool isVCVTSS2USI(unsigned Opcode);
534bool isVCVTTPS2DQS(unsigned Opcode);
535bool isVPANDD(unsigned Opcode);
536bool isPMINSW(unsigned Opcode);
537bool isSTAC(unsigned Opcode);
538bool isVFMSUB213PS(unsigned Opcode);
539bool isPOPAL(unsigned Opcode);
540bool isVCVTPS2UQQ(unsigned Opcode);
541bool isRDRAND(unsigned Opcode);
542bool isJCC(unsigned Opcode);
543bool isVPMINSQ(unsigned Opcode);
544bool isVADDSD(unsigned Opcode);
545bool isDPPS(unsigned Opcode);
546bool isPINSRQ(unsigned Opcode);
547bool isVUCOMISS(unsigned Opcode);
548bool isVPDPWSUD(unsigned Opcode);
549bool isKANDNW(unsigned Opcode);
550bool isAOR(unsigned Opcode);
551bool isPMAXUB(unsigned Opcode);
552bool isANDNPD(unsigned Opcode);
553bool isINVPCID(unsigned Opcode);
554bool isRDGSBASE(unsigned Opcode);
555bool isVPMOVSQD(unsigned Opcode);
556bool isBT(unsigned Opcode);
557bool isVPROLVQ(unsigned Opcode);
558bool isVFMADDSUB132PD(unsigned Opcode);
559bool isRORX(unsigned Opcode);
560bool isPADDUSW(unsigned Opcode);
561bool isPFNACC(unsigned Opcode);
562bool isAND(unsigned Opcode);
563bool isPSLLQ(unsigned Opcode);
564bool isVFMSUB132PH(unsigned Opcode);
565bool isXSAVE(unsigned Opcode);
566bool isKNOTQ(unsigned Opcode);
567bool isXTEST(unsigned Opcode);
568bool isVINSERTPS(unsigned Opcode);
569bool isXSAVEOPT(unsigned Opcode);
570bool isLDS(unsigned Opcode);
571bool isVFMADDSUB213PD(unsigned Opcode);
572bool isVINSERTF32X4(unsigned Opcode);
573bool isVRSQRTPS(unsigned Opcode);
574bool isVSUBPH(unsigned Opcode);
575bool isPMOVSXBW(unsigned Opcode);
576bool isVPSRLDQ(unsigned Opcode);
577bool isADC(unsigned Opcode);
578bool isPHADDD(unsigned Opcode);
579bool isVDPPHPS(unsigned Opcode);
580bool isVMINPH(unsigned Opcode);
581bool isVMINSD(unsigned Opcode);
582bool isVROUNDPD(unsigned Opcode);
583bool isVFCMADDCPH(unsigned Opcode);
584bool isINCSSPQ(unsigned Opcode);
585bool isVPUNPCKLDQ(unsigned Opcode);
586bool isVMINSH(unsigned Opcode);
587bool isINSERTQ(unsigned Opcode);
588bool isBLCI(unsigned Opcode);
589bool isHLT(unsigned Opcode);
590bool isVPCOMUW(unsigned Opcode);
591bool isVPMOVSXDQ(unsigned Opcode);
592bool isVFNMSUB231PS(unsigned Opcode);
593bool isVFNMSUB213SH(unsigned Opcode);
594bool isVCVTTPD2UQQ(unsigned Opcode);
595bool isSQRTSS(unsigned Opcode);
596bool isIMUL(unsigned Opcode);
597bool isVCVTSS2SI(unsigned Opcode);
598bool isPUSHAW(unsigned Opcode);
599bool isSTOSD(unsigned Opcode);
600bool isPSRLDQ(unsigned Opcode);
601bool isVSCATTERQPS(unsigned Opcode);
602bool isFIDIV(unsigned Opcode);
603bool isVFMSUB213PD(unsigned Opcode);
604bool isVFMADDSUB231PH(unsigned Opcode);
605bool isTDCALL(unsigned Opcode);
606bool isPVALIDATE(unsigned Opcode);
607bool isVPSHUFLW(unsigned Opcode);
608bool isPCLMULQDQ(unsigned Opcode);
609bool isCMPXCHG8B(unsigned Opcode);
610bool isVPMOVM2B(unsigned Opcode);
611bool isVCVTUDQ2PH(unsigned Opcode);
612bool isPEXTRQ(unsigned Opcode);
613bool isXCRYPTCTR(unsigned Opcode);
614bool isVREDUCEPH(unsigned Opcode);
615bool isUCOMISD(unsigned Opcode);
616bool isOUTSD(unsigned Opcode);
617bool isSUBSS(unsigned Opcode);
618bool isVFMSUBPS(unsigned Opcode);
619bool isVPBLENDW(unsigned Opcode);
620bool isBZHI(unsigned Opcode);
621bool isVPRORVD(unsigned Opcode);
622bool isRMPQUERY(unsigned Opcode);
623bool isVPEXPANDB(unsigned Opcode);
624bool isVPSCATTERDQ(unsigned Opcode);
625bool isPSMASH(unsigned Opcode);
626bool isVPSHLDQ(unsigned Opcode);
627bool isVSCATTERPF1DPD(unsigned Opcode);
628bool isMONTMUL(unsigned Opcode);
629bool isVCVTPH2UQQ(unsigned Opcode);
630bool isPSLLD(unsigned Opcode);
631bool isSAR(unsigned Opcode);
632bool isLDTILECFG(unsigned Opcode);
633bool isPMINUB(unsigned Opcode);
634bool isVCVTNEEBF162PS(unsigned Opcode);
635bool isMOVDIR64B(unsigned Opcode);
636bool isSTR(unsigned Opcode);
637bool isKANDNQ(unsigned Opcode);
638bool isBSF(unsigned Opcode);
639bool isVPDPBUUDS(unsigned Opcode);
640bool isINCSSPD(unsigned Opcode);
641bool isSQRTPS(unsigned Opcode);
642bool isCMPXCHG(unsigned Opcode);
643bool isVPSIGNW(unsigned Opcode);
644bool isVCOMISBF16(unsigned Opcode);
645bool isLES(unsigned Opcode);
646bool isCVTSS2SI(unsigned Opcode);
647bool isVPMOVUSWB(unsigned Opcode);
648bool isFCOMPI(unsigned Opcode);
649bool isPUNPCKHWD(unsigned Opcode);
650bool isPFACC(unsigned Opcode);
651bool isVPTESTNMW(unsigned Opcode);
652bool isVPMULDQ(unsigned Opcode);
653bool isSHRX(unsigned Opcode);
654bool isKXORQ(unsigned Opcode);
655bool isVGETEXPSD(unsigned Opcode);
656bool isV4FNMADDPS(unsigned Opcode);
657bool isVFNMSUB231SD(unsigned Opcode);
658bool isVPSHLD(unsigned Opcode);
659bool isPAVGB(unsigned Opcode);
660bool isPMOVZXBD(unsigned Opcode);
661bool isKORTESTW(unsigned Opcode);
662bool isVSHUFPS(unsigned Opcode);
663bool isAESENCWIDE128KL(unsigned Opcode);
664bool isVPXORD(unsigned Opcode);
665bool isVPSHAW(unsigned Opcode);
666bool isVFMSUB132BF16(unsigned Opcode);
667bool isVPERMT2B(unsigned Opcode);
668bool isVFMADD213PD(unsigned Opcode);
669bool isVPGATHERQD(unsigned Opcode);
670bool isVFNMSUB213BF16(unsigned Opcode);
671bool isVCVTPS2IBS(unsigned Opcode);
672bool isVPCMPGTW(unsigned Opcode);
673bool isVMOVRSB(unsigned Opcode);
674bool isVGETMANTSH(unsigned Opcode);
675bool isVANDPS(unsigned Opcode);
676bool isVDIVPS(unsigned Opcode);
677bool isVANDNPS(unsigned Opcode);
678bool isVPBROADCASTW(unsigned Opcode);
679bool isFLDL2T(unsigned Opcode);
680bool isVPERMB(unsigned Opcode);
681bool isFCMOVNBE(unsigned Opcode);
682bool isVCVTTPH2W(unsigned Opcode);
683bool isPMOVZXBQ(unsigned Opcode);
684bool isPF2ID(unsigned Opcode);
685bool isVFNMADD132PD(unsigned Opcode);
686bool isPMULHRSW(unsigned Opcode);
687bool isKADDD(unsigned Opcode);
688bool isVFNMSUB132SH(unsigned Opcode);
689bool isUIRET(unsigned Opcode);
690bool isBSR(unsigned Opcode);
691bool isPCMPEQQ(unsigned Opcode);
692bool isCDQ(unsigned Opcode);
693bool isPMAXSW(unsigned Opcode);
694bool isSIDTD(unsigned Opcode);
695bool isVCVTPS2PHX(unsigned Opcode);
696bool isVPSLLVQ(unsigned Opcode);
697bool isMOVQ(unsigned Opcode);
698bool isVCMPBF16(unsigned Opcode);
699bool isPREFETCH(unsigned Opcode);
700bool isCLRSSBSY(unsigned Opcode);
701bool isTCVTROWPS2PHL(unsigned Opcode);
702bool isPSHUFW(unsigned Opcode);
703bool isVPDPWSUDS(unsigned Opcode);
704bool isVPMOVSXBQ(unsigned Opcode);
705bool isFICOMP(unsigned Opcode);
706bool isVLDMXCSR(unsigned Opcode);
707bool isVPSUBUSW(unsigned Opcode);
708bool isVFNMSUB132SS(unsigned Opcode);
709bool isRETF(unsigned Opcode);
710bool isKMOVQ(unsigned Opcode);
711bool isVPADDUSW(unsigned Opcode);
712bool isPACKSSDW(unsigned Opcode);
713bool isUMONITOR(unsigned Opcode);
714bool isENQCMDS(unsigned Opcode);
715bool isVCOMXSD(unsigned Opcode);
716bool isVPMAXSQ(unsigned Opcode);
717bool isVFMSUB213BF16(unsigned Opcode);
718bool isVPERMT2Q(unsigned Opcode);
719bool isFDECSTP(unsigned Opcode);
720bool isVPTESTMQ(unsigned Opcode);
721bool isVRCP14PD(unsigned Opcode);
722bool isARPL(unsigned Opcode);
723bool isVFMSUB213SD(unsigned Opcode);
724bool isJMPABS(unsigned Opcode);
725bool isVUNPCKHPS(unsigned Opcode);
726bool isVFNMADDSS(unsigned Opcode);
727bool isSIDT(unsigned Opcode);
728bool isVPCMPGTB(unsigned Opcode);
729bool isVPRORD(unsigned Opcode);
730bool isVSUBSS(unsigned Opcode);
731bool isPUSHFQ(unsigned Opcode);
732bool isVCVTHF82PH(unsigned Opcode);
733bool isVPCLMULQDQ(unsigned Opcode);
734bool isVPADDUSB(unsigned Opcode);
735bool isVPCMPD(unsigned Opcode);
736bool isMOVSD(unsigned Opcode);
737bool isPSUBUSW(unsigned Opcode);
738bool isVFMSUBADD132PS(unsigned Opcode);
739bool isMOVMSKPS(unsigned Opcode);
740bool isVFIXUPIMMSS(unsigned Opcode);
741bool isMFENCE(unsigned Opcode);
742bool isFTST(unsigned Opcode);
743bool isVPMADDWD(unsigned Opcode);
744bool isPOP(unsigned Opcode);
745bool isPSUBW(unsigned Opcode);
746bool isBSWAP(unsigned Opcode);
747bool isPFMIN(unsigned Opcode);
748bool isVFPCLASSPD(unsigned Opcode);
749bool isVPSHRDVD(unsigned Opcode);
750bool isPADDW(unsigned Opcode);
751bool isCVTSI2SD(unsigned Opcode);
752bool isENQCMD(unsigned Opcode);
753bool isXSHA1(unsigned Opcode);
754bool isVFNMADD132SD(unsigned Opcode);
755bool isMOVZX(unsigned Opcode);
756bool isVFIXUPIMMSD(unsigned Opcode);
757bool isINVD(unsigned Opcode);
758bool isVFIXUPIMMPS(unsigned Opcode);
759bool isMOVDQU(unsigned Opcode);
760bool isVFPCLASSPS(unsigned Opcode);
761bool isMOVSQ(unsigned Opcode);
762bool isAESDECWIDE128KL(unsigned Opcode);
763bool isROUNDSS(unsigned Opcode);
764bool isVPERMILPS(unsigned Opcode);
765bool isVPMOVW2M(unsigned Opcode);
766bool isVMULSD(unsigned Opcode);
767bool isVPERMI2W(unsigned Opcode);
768bool isVPSHUFB(unsigned Opcode);
769bool isFST(unsigned Opcode);
770bool isVPHSUBW(unsigned Opcode);
771bool isVREDUCESS(unsigned Opcode);
772bool isFRNDINT(unsigned Opcode);
773bool isSHR(unsigned Opcode);
774bool isLOOPNE(unsigned Opcode);
775bool isVCVTTPH2UQQ(unsigned Opcode);
776bool isSHA1NEXTE(unsigned Opcode);
777bool isVFMADD132SD(unsigned Opcode);
778bool isPSRAW(unsigned Opcode);
779bool isVPBROADCASTQ(unsigned Opcode);
780bool isCLC(unsigned Opcode);
781bool isPOPAW(unsigned Opcode);
782bool isTCMMIMFP16PS(unsigned Opcode);
783bool isVCVTTPS2UQQ(unsigned Opcode);
784bool isVCVTQQ2PH(unsigned Opcode);
785bool isVMOVUPD(unsigned Opcode);
786bool isFPTAN(unsigned Opcode);
787bool isVMASKMOVPD(unsigned Opcode);
788bool isVMOVLHPS(unsigned Opcode);
789bool isAESKEYGENASSIST(unsigned Opcode);
790bool isXSAVEOPT64(unsigned Opcode);
791bool isXSAVEC(unsigned Opcode);
792bool isVPLZCNTQ(unsigned Opcode);
793bool isVPSUBW(unsigned Opcode);
794bool isCMPCCXADD(unsigned Opcode);
795bool isVFMSUBADD213PH(unsigned Opcode);
796bool isVFMADDSUBPD(unsigned Opcode);
797bool isVPMINSW(unsigned Opcode);
798bool isVFNMSUB132PS(unsigned Opcode);
799bool isVMOVAPS(unsigned Opcode);
800bool isVPEXTRQ(unsigned Opcode);
801bool isVSCALEFSH(unsigned Opcode);
802bool isVCVTPD2PS(unsigned Opcode);
803bool isCLGI(unsigned Opcode);
804bool isVAESDEC(unsigned Opcode);
805bool isPFMUL(unsigned Opcode);
806bool isVCVTBIASPH2BF8S(unsigned Opcode);
807bool isMOVDIRI(unsigned Opcode);
808bool isSHUFPS(unsigned Opcode);
809bool isVFNMSUB231SS(unsigned Opcode);
810bool isVMWRITE(unsigned Opcode);
811bool isVINSERTF128(unsigned Opcode);
812bool isFISUBR(unsigned Opcode);
813bool isVINSERTI32X4(unsigned Opcode);
814bool isVPSLLDQ(unsigned Opcode);
815bool isPOPCNT(unsigned Opcode);
816bool isVXORPD(unsigned Opcode);
817bool isXLATB(unsigned Opcode);
818bool isDIV(unsigned Opcode);
819bool isVPSHLDVQ(unsigned Opcode);
820bool isMOVDDUP(unsigned Opcode);
821bool isVMOVDQU64(unsigned Opcode);
822bool isVPCOMPRESSQ(unsigned Opcode);
823bool isVFMSUBADD132PD(unsigned Opcode);
824bool isADDSD(unsigned Opcode);
825bool isBLENDPD(unsigned Opcode);
826bool isVPERMILPD(unsigned Opcode);
827bool isPMADDUBSW(unsigned Opcode);
828bool isPOPFD(unsigned Opcode);
829bool isCMPSW(unsigned Opcode);
830bool isLDMXCSR(unsigned Opcode);
831bool isVMULPS(unsigned Opcode);
832bool isVROUNDSD(unsigned Opcode);
833bool isVFMADD132PD(unsigned Opcode);
834bool isVPANDQ(unsigned Opcode);
835bool isVPSRAQ(unsigned Opcode);
836bool isVCOMISD(unsigned Opcode);
837bool isVCVTBIASPH2BF8(unsigned Opcode);
838bool isFFREEP(unsigned Opcode);
839bool isVFNMADD213PD(unsigned Opcode);
840bool isVCMPPD(unsigned Opcode);
841bool isVFNMSUB132PH(unsigned Opcode);
842bool isVPHADDBW(unsigned Opcode);
843bool isVPPERM(unsigned Opcode);
844bool isVCVTPS2PD(unsigned Opcode);
845bool isCBW(unsigned Opcode);
846bool isVMOVUPS(unsigned Opcode);
847bool isVPMAXUQ(unsigned Opcode);
848bool isWRSSQ(unsigned Opcode);
849bool isPACKUSDW(unsigned Opcode);
850bool isVCVTTBF162IBS(unsigned Opcode);
851bool isXBEGIN(unsigned Opcode);
852bool isVCVTPD2UQQ(unsigned Opcode);
853bool isFCMOVB(unsigned Opcode);
854bool isNOP(unsigned Opcode);
855bool isVPABSQ(unsigned Opcode);
856bool isVTESTPS(unsigned Opcode);
857bool isPHSUBW(unsigned Opcode);
858bool isPUSH2P(unsigned Opcode);
859bool isFISTTP(unsigned Opcode);
860bool isCFCMOVCC(unsigned Opcode);
861bool isVPINSRD(unsigned Opcode);
862bool isPCMPESTRM(unsigned Opcode);
863bool isVFNMSUB213PS(unsigned Opcode);
864bool isPHSUBD(unsigned Opcode);
865bool isVCVTTPD2DQS(unsigned Opcode);
866bool isSLDT(unsigned Opcode);
867bool isVHADDPS(unsigned Opcode);
868bool isVMOVNTDQ(unsigned Opcode);
869bool isVPMINSD(unsigned Opcode);
870bool isVFRCZSD(unsigned Opcode);
871bool isVPTESTMW(unsigned Opcode);
872bool isVPMOVZXWD(unsigned Opcode);
873bool isPSADBW(unsigned Opcode);
874bool isVCVTSD2SI(unsigned Opcode);
875bool isVMAXPH(unsigned Opcode);
876bool isLODSB(unsigned Opcode);
877bool isPHMINPOSUW(unsigned Opcode);
878bool isVPROLVD(unsigned Opcode);
879bool isWRFSBASE(unsigned Opcode);
880bool isVRSQRT14PS(unsigned Opcode);
881bool isVPHSUBDQ(unsigned Opcode);
882bool isIRETD(unsigned Opcode);
883bool isVMOVRSD(unsigned Opcode);
884bool isCVTSI2SS(unsigned Opcode);
885bool isVPMULHRSW(unsigned Opcode);
886bool isPI2FD(unsigned Opcode);
887bool isGF2P8AFFINEQB(unsigned Opcode);
888bool isPAND(unsigned Opcode);
889bool isVFNMSUB231SH(unsigned Opcode);
890bool isVCVTPH2BF8(unsigned Opcode);
891bool isVMOVHLPS(unsigned Opcode);
892bool isPEXTRB(unsigned Opcode);
893bool isVMMCALL(unsigned Opcode);
894bool isKNOTD(unsigned Opcode);
895bool isVCVTSH2SS(unsigned Opcode);
896bool isVPUNPCKLQDQ(unsigned Opcode);
897bool isVPERMIL2PS(unsigned Opcode);
898bool isVPCMPGTD(unsigned Opcode);
899bool isCMPXCHG16B(unsigned Opcode);
900bool isTDPHF8PS(unsigned Opcode);
901bool isVZEROUPPER(unsigned Opcode);
902bool isMOVAPS(unsigned Opcode);
903bool isVPCMPW(unsigned Opcode);
904bool isFUCOMPP(unsigned Opcode);
905bool isXSETBV(unsigned Opcode);
906bool isSLWPCB(unsigned Opcode);
907bool isSCASW(unsigned Opcode);
908bool isFCMOVNE(unsigned Opcode);
909bool isPBNDKB(unsigned Opcode);
910bool isVPMULLD(unsigned Opcode);
911bool isVP4DPWSSDS(unsigned Opcode);
912bool isVCVT2PH2HF8(unsigned Opcode);
913bool isPINSRW(unsigned Opcode);
914bool isVCVTSI2SH(unsigned Opcode);
915bool isVINSERTF32X8(unsigned Opcode);
916bool isKSHIFTLB(unsigned Opcode);
917bool isSEAMOPS(unsigned Opcode);
918bool isVPMULUDQ(unsigned Opcode);
919bool isVPMOVSQB(unsigned Opcode);
920bool isVPTESTMD(unsigned Opcode);
921bool isVPHADDDQ(unsigned Opcode);
922bool isKUNPCKDQ(unsigned Opcode);
923bool isT1MSKC(unsigned Opcode);
924bool isVPCOMB(unsigned Opcode);
925bool isVBLENDPS(unsigned Opcode);
926bool isPTWRITE(unsigned Opcode);
927bool isVCVTPH2BF8S(unsigned Opcode);
928bool isCVTPS2PI(unsigned Opcode);
929bool isVPROTD(unsigned Opcode);
930bool isCALL(unsigned Opcode);
931bool isTILELOADDRST1(unsigned Opcode);
932bool isVPERMPS(unsigned Opcode);
933bool isVPSHUFBITQMB(unsigned Opcode);
934bool isVMOVSLDUP(unsigned Opcode);
935bool isINVLPGA(unsigned Opcode);
936bool isVCVTPH2QQ(unsigned Opcode);
937bool isADD(unsigned Opcode);
938bool isPSUBSW(unsigned Opcode);
939bool isSIDTW(unsigned Opcode);
940bool isVFNMADD231PH(unsigned Opcode);
941bool isVEXTRACTF64X2(unsigned Opcode);
942bool isFCOMI(unsigned Opcode);
943bool isRSM(unsigned Opcode);
944bool isVPCOMUD(unsigned Opcode);
945bool isVPMOVZXBQ(unsigned Opcode);
946bool isUWRMSR(unsigned Opcode);
947bool isLGS(unsigned Opcode);
948bool isVMOVNTPD(unsigned Opcode);
949bool isRDPRU(unsigned Opcode);
950bool isVPUNPCKHBW(unsigned Opcode);
951bool isVUCOMXSD(unsigned Opcode);
952bool isANDN(unsigned Opcode);
953bool isVCVTTPH2UW(unsigned Opcode);
954bool isVMFUNC(unsigned Opcode);
955bool isFIMUL(unsigned Opcode);
956bool isBLCFILL(unsigned Opcode);
957bool isVGATHERPF0DPS(unsigned Opcode);
958bool isVFMSUBADD231PS(unsigned Opcode);
959bool isVREDUCESD(unsigned Opcode);
960bool isVCOMXSH(unsigned Opcode);
961bool isVXORPS(unsigned Opcode);
962bool isPSWAPD(unsigned Opcode);
963bool isPMAXSD(unsigned Opcode);
964bool isVCMPSS(unsigned Opcode);
965bool isEXTRACTPS(unsigned Opcode);
966bool isVPMOVZXBD(unsigned Opcode);
967bool isOUTSW(unsigned Opcode);
968bool isKORTESTB(unsigned Opcode);
969bool isVREDUCEPS(unsigned Opcode);
970bool isPEXTRW(unsigned Opcode);
971bool isFNINIT(unsigned Opcode);
972bool isVCVTPH2IBS(unsigned Opcode);
973bool isROL(unsigned Opcode);
974bool isVCVTPS2QQ(unsigned Opcode);
975bool isVGETMANTPH(unsigned Opcode);
976bool isPUNPCKLDQ(unsigned Opcode);
977bool isPADDD(unsigned Opcode);
978bool isVPSLLD(unsigned Opcode);
979bool isPFCMPGE(unsigned Opcode);
980bool isVGETMANTBF16(unsigned Opcode);
981bool isVSUBBF16(unsigned Opcode);
982bool isVPMOVM2D(unsigned Opcode);
983bool isVCVTTSS2USIS(unsigned Opcode);
984bool isVHSUBPS(unsigned Opcode);
985bool isENDBR32(unsigned Opcode);
986bool isMOVSXD(unsigned Opcode);
987bool isPSIGND(unsigned Opcode);
988bool isVPTEST(unsigned Opcode);
989bool isVPDPWUSD(unsigned Opcode);
990bool isHSUBPD(unsigned Opcode);
991bool isADCX(unsigned Opcode);
992bool isCVTTPD2PI(unsigned Opcode);
993bool isPDEP(unsigned Opcode);
994bool isTDPBUSD(unsigned Opcode);
995bool isVCVTBIASPH2HF8S(unsigned Opcode);
996bool isVBROADCASTI32X4(unsigned Opcode);
997bool isVCVTPH2UDQ(unsigned Opcode);
998bool isVPHADDW(unsigned Opcode);
999bool isFLDL2E(unsigned Opcode);
1000bool isCLZERO(unsigned Opcode);
1001bool isPBLENDW(unsigned Opcode);
1002bool isVCVTBF162IUBS(unsigned Opcode);
1003bool isVCVTSH2USI(unsigned Opcode);
1004bool isVANDPD(unsigned Opcode);
1005bool isBEXTR(unsigned Opcode);
1006bool isSTD(unsigned Opcode);
1007bool isVAESKEYGENASSIST(unsigned Opcode);
1008bool isCMPSD(unsigned Opcode);
1009bool isMOVSS(unsigned Opcode);
1010bool isVCVTUQQ2PD(unsigned Opcode);
1011bool isVEXTRACTI32X4(unsigned Opcode);
1012bool isFLDCW(unsigned Opcode);
1013bool isINSW(unsigned Opcode);
1014bool isRDPID(unsigned Opcode);
1015bool isVUCOMXSS(unsigned Opcode);
1016bool isKANDQ(unsigned Opcode);
1017bool isV4FMADDPS(unsigned Opcode);
1018bool isPMOVZXWQ(unsigned Opcode);
1019bool isVFPCLASSSD(unsigned Opcode);
1020bool isBLENDPS(unsigned Opcode);
1021bool isVPACKSSDW(unsigned Opcode);
1022bool isVPINSRW(unsigned Opcode);
1023bool isFXAM(unsigned Opcode);
1024bool isVMINMAXBF16(unsigned Opcode);
1025bool isVSHUFF64X2(unsigned Opcode);
1026bool isVPACKUSWB(unsigned Opcode);
1027bool isVRSQRT28SS(unsigned Opcode);
1028bool isGETSEC(unsigned Opcode);
1029bool isVEXTRACTF64X4(unsigned Opcode);
1030bool isVPHSUBBW(unsigned Opcode);
1031bool isBLSR(unsigned Opcode);
1032bool isFILD(unsigned Opcode);
1033bool isRETFQ(unsigned Opcode);
1034bool isVADDSS(unsigned Opcode);
1035bool isCOMISS(unsigned Opcode);
1036bool isCLI(unsigned Opcode);
1037bool isVERW(unsigned Opcode);
1038bool isBTC(unsigned Opcode);
1039bool isVPHADDUBQ(unsigned Opcode);
1040bool isVPORQ(unsigned Opcode);
1041bool isORPD(unsigned Opcode);
1042bool isVMOVSS(unsigned Opcode);
1043bool isVPSUBD(unsigned Opcode);
1044bool isVGATHERPF1QPD(unsigned Opcode);
1045bool isENCODEKEY256(unsigned Opcode);
1046bool isGF2P8AFFINEINVQB(unsigned Opcode);
1047bool isXRSTOR64(unsigned Opcode);
1048bool isKANDW(unsigned Opcode);
1049bool isLODSQ(unsigned Opcode);
1050bool isVMOVRSW(unsigned Opcode);
1051bool isVSUBSH(unsigned Opcode);
1052bool isLSS(unsigned Opcode);
1053bool isPMOVSXBQ(unsigned Opcode);
1054bool isVCVTTSD2SIS(unsigned Opcode);
1055bool isVCMPSH(unsigned Opcode);
1056bool isVFMADD132PS(unsigned Opcode);
1057bool isVPACKSSWB(unsigned Opcode);
1058bool isPCMPGTQ(unsigned Opcode);
1059bool isVFMADD132SH(unsigned Opcode);
1060bool isVCVTUQQ2PH(unsigned Opcode);
1061bool isVCVTQQ2PS(unsigned Opcode);
1062bool isVCVTTSS2USI(unsigned Opcode);
1063bool isVPMOVM2Q(unsigned Opcode);
1064bool isVMOVD(unsigned Opcode);
1065bool isVCVTTPS2QQS(unsigned Opcode);
1066bool isVSQRTBF16(unsigned Opcode);
1067bool isVFPCLASSPH(unsigned Opcode);
1068bool isVCVTSS2SH(unsigned Opcode);
1069bool isSCASB(unsigned Opcode);
1070bool isPSRLD(unsigned Opcode);
1071bool isVADDPH(unsigned Opcode);
1072bool isFSUB(unsigned Opcode);
1073bool isVCVTTPH2IBS(unsigned Opcode);
1074bool isVEXTRACTI64X2(unsigned Opcode);
1075bool isPMINUW(unsigned Opcode);
1076bool isPSUBSB(unsigned Opcode);
1077bool isVCVT2PS2PHX(unsigned Opcode);
1078bool isVPCMPEQD(unsigned Opcode);
1079bool isVPSCATTERQD(unsigned Opcode);
1080bool isVPSHLDD(unsigned Opcode);
1081bool isKXNORB(unsigned Opcode);
1082bool isLDDQU(unsigned Opcode);
1083bool isMASKMOVQ(unsigned Opcode);
1084bool isPABSW(unsigned Opcode);
1085bool isVPROLD(unsigned Opcode);
1086bool isVPCOMQ(unsigned Opcode);
1087bool isVSCATTERDPD(unsigned Opcode);
1088bool isFXRSTOR(unsigned Opcode);
1089bool isVPCMPUW(unsigned Opcode);
1090bool isWBINVD(unsigned Opcode);
1091bool isVCVTTPD2UDQ(unsigned Opcode);
1092bool isERETU(unsigned Opcode);
1093bool isPFRCPIT2(unsigned Opcode);
1094bool isVPERMT2W(unsigned Opcode);
1095bool isVEXTRACTF32X4(unsigned Opcode);
1096bool isVGATHERPF0DPD(unsigned Opcode);
1097bool isVBROADCASTF32X2(unsigned Opcode);
1098bool isVRCP14SD(unsigned Opcode);
1099bool isPABSD(unsigned Opcode);
1100bool isLAHF(unsigned Opcode);
1101bool isPINSRB(unsigned Opcode);
1102bool isSKINIT(unsigned Opcode);
1103bool isENTER(unsigned Opcode);
1104bool isVCVTSI2SS(unsigned Opcode);
1105bool isVFMADD231PD(unsigned Opcode);
1106bool isLOADIWKEY(unsigned Opcode);
1107bool isVMOVNTDQA(unsigned Opcode);
1108bool isVPERMT2PS(unsigned Opcode);
1109bool isPUSHF(unsigned Opcode);
1110bool isMPSADBW(unsigned Opcode);
1111bool isVMINMAXSH(unsigned Opcode);
1112bool isVRSQRT14SS(unsigned Opcode);
1113bool isVCVTDQ2PD(unsigned Opcode);
1114bool isVORPS(unsigned Opcode);
1115bool isVPEXPANDQ(unsigned Opcode);
1116bool isVPSHRDD(unsigned Opcode);
1117bool isTDPBSSD(unsigned Opcode);
1118bool isTESTUI(unsigned Opcode);
1119bool isVFMADDPD(unsigned Opcode);
1120bool isVPANDND(unsigned Opcode);
1121bool isVPMOVSDB(unsigned Opcode);
1122bool isVPBROADCASTB(unsigned Opcode);
1123bool isCVTPI2PD(unsigned Opcode);
1124bool isVPERMI2B(unsigned Opcode);
1125bool isVPMINSB(unsigned Opcode);
1126bool isLAR(unsigned Opcode);
1127bool isINVLPGB(unsigned Opcode);
1128bool isTLBSYNC(unsigned Opcode);
1129bool isFDIVP(unsigned Opcode);
1130bool isVPSRLW(unsigned Opcode);
1131bool isVRCP28SS(unsigned Opcode);
1132bool isVMOVHPS(unsigned Opcode);
1133bool isVPMACSSDD(unsigned Opcode);
1134bool isPEXT(unsigned Opcode);
1135bool isVMAXBF16(unsigned Opcode);
1136bool isVRSQRT14SD(unsigned Opcode);
1137bool isVPDPWSSD(unsigned Opcode);
1138bool isVFMSUB231SD(unsigned Opcode);
1139bool isVPMOVZXWQ(unsigned Opcode);
1140bool isVMOVDQA(unsigned Opcode);
1141bool isVFNMSUB213SD(unsigned Opcode);
1142bool isVMINPS(unsigned Opcode);
1143bool isVFMSUB231PS(unsigned Opcode);
1144bool isVPCOMPRESSB(unsigned Opcode);
1145bool isVPCMPEQQ(unsigned Opcode);
1146bool isVRCPSS(unsigned Opcode);
1147bool isVSCATTERPF1DPS(unsigned Opcode);
1148bool isVPHADDUBW(unsigned Opcode);
1149bool isXORPD(unsigned Opcode);
1150bool isVPSCATTERQQ(unsigned Opcode);
1151bool isVCVTW2PH(unsigned Opcode);
1152bool isVFMADDCPH(unsigned Opcode);
1153bool isVSUBPD(unsigned Opcode);
1154bool isVPACKUSDW(unsigned Opcode);
1155bool isVSCALEFSS(unsigned Opcode);
1156bool isAESIMC(unsigned Opcode);
1157bool isVRCP28PS(unsigned Opcode);
1158bool isAAND(unsigned Opcode);
1159bool isDAA(unsigned Opcode);
1160bool isVCVTPD2UDQ(unsigned Opcode);
1161bool isKTESTW(unsigned Opcode);
1162bool isVPADDQ(unsigned Opcode);
1163bool isPALIGNR(unsigned Opcode);
1164bool isPMAXUW(unsigned Opcode);
1165bool isVFMADDSD(unsigned Opcode);
1166bool isPFMAX(unsigned Opcode);
1167bool isVPOR(unsigned Opcode);
1168bool isVPSUBB(unsigned Opcode);
1169bool isVPAVGB(unsigned Opcode);
1170bool isINSB(unsigned Opcode);
1171bool isFYL2X(unsigned Opcode);
1172bool isVFNMSUB132PD(unsigned Opcode);
1173bool isVFNMSUBPS(unsigned Opcode);
1174bool isVFMADD231PS(unsigned Opcode);
1175bool isVCVTTSS2SI(unsigned Opcode);
1176bool isTCMMRLFP16PS(unsigned Opcode);
1177bool isFCOMPP(unsigned Opcode);
1178bool isMOVD(unsigned Opcode);
1179bool isMOVBE(unsigned Opcode);
1180bool isVP2INTERSECTD(unsigned Opcode);
1181bool isVPMULLQ(unsigned Opcode);
1182bool isVSCALEFPS(unsigned Opcode);
1183bool isVPMACSDQH(unsigned Opcode);
1184bool isVPTESTNMD(unsigned Opcode);
1185bool isFCOMP(unsigned Opcode);
1186bool isPREFETCHWT1(unsigned Opcode);
1187bool isVCMPSD(unsigned Opcode);
1188bool isSGDTD(unsigned Opcode);
1189bool isWRUSSD(unsigned Opcode);
1190bool isFSUBP(unsigned Opcode);
1191bool isVUNPCKLPS(unsigned Opcode);
1192bool isVFNMSUB213SS(unsigned Opcode);
1193bool isROUNDPD(unsigned Opcode);
1194bool isVPMAXSW(unsigned Opcode);
1195bool isVCVTTPH2DQ(unsigned Opcode);
1196bool isVPUNPCKLWD(unsigned Opcode);
1197bool isKSHIFTLD(unsigned Opcode);
1198bool isTCVTROWPS2BF16H(unsigned Opcode);
1199bool isVFMADD231SD(unsigned Opcode);
1200bool isADDPS(unsigned Opcode);
1201bool isVPSLLVD(unsigned Opcode);
1202bool isVFNMADD132SH(unsigned Opcode);
1203bool isVMOVNTPS(unsigned Opcode);
1204bool isVCVTPD2DQ(unsigned Opcode);
1205bool isVPXOR(unsigned Opcode);
1206bool isSTMXCSR(unsigned Opcode);
1207bool isVRCP14SS(unsigned Opcode);
1208bool isUD2(unsigned Opcode);
1209bool isVPOPCNTW(unsigned Opcode);
1210bool isVRSQRTSH(unsigned Opcode);
1211bool isVSCATTERPF0DPD(unsigned Opcode);
1212bool isVFMADDPS(unsigned Opcode);
1213bool isXSAVEC64(unsigned Opcode);
1214bool isVPMADDUBSW(unsigned Opcode);
1215bool isVPMOVZXDQ(unsigned Opcode);
1216bool isVRCP14PS(unsigned Opcode);
1217bool isVSQRTSH(unsigned Opcode);
1218bool isTCVTROWD2PS(unsigned Opcode);
1219bool isLOOP(unsigned Opcode);
1220bool isSTUI(unsigned Opcode);
1221bool isVCVTTPS2UDQ(unsigned Opcode);
1222bool isVCOMPRESSPS(unsigned Opcode);
1223bool isXABORT(unsigned Opcode);
1224bool isVCVTTBF162IUBS(unsigned Opcode);
1225bool isVPADDW(unsigned Opcode);
1226bool isVRNDSCALEPS(unsigned Opcode);
1227bool isVPSIGND(unsigned Opcode);
1228bool isVPHADDUWD(unsigned Opcode);
1229bool isVCVT2PH2HF8S(unsigned Opcode);
1230bool isVDBPSADBW(unsigned Opcode);
1231bool isPSLLW(unsigned Opcode);
1232bool isVPMOVQD(unsigned Opcode);
1233bool isVINSERTI64X4(unsigned Opcode);
1234bool isVPERMI2PS(unsigned Opcode);
1235bool isVMULPH(unsigned Opcode);
1236bool isVPCMPUQ(unsigned Opcode);
1237bool isVCVTUSI2SD(unsigned Opcode);
1238bool isKXNORW(unsigned Opcode);
1239bool isBLCIC(unsigned Opcode);
1240bool isVFNMADD213SD(unsigned Opcode);
1241bool isVPMACSWW(unsigned Opcode);
1242bool isVMOVLPS(unsigned Opcode);
1243bool isPCONFIG(unsigned Opcode);
1244bool isPANDN(unsigned Opcode);
1245bool isVGETEXPPD(unsigned Opcode);
1246bool isVPSRLVQ(unsigned Opcode);
1247bool isUD1(unsigned Opcode);
1248bool isPMAXSB(unsigned Opcode);
1249bool isVPROLQ(unsigned Opcode);
1250bool isVSCATTERPF1QPD(unsigned Opcode);
1251bool isVPSRLD(unsigned Opcode);
1252bool isINT3(unsigned Opcode);
1253bool isXRSTORS64(unsigned Opcode);
1254bool isCVTSD2SI(unsigned Opcode);
1255bool isVMAXSS(unsigned Opcode);
1256bool isVPMINUB(unsigned Opcode);
1257bool isKXNORQ(unsigned Opcode);
1258bool isFLD(unsigned Opcode);
1259bool isVSHUFI32X4(unsigned Opcode);
1260bool isSAHF(unsigned Opcode);
1261bool isPFRSQRT(unsigned Opcode);
1262bool isSHRD(unsigned Opcode);
1263bool isSYSEXIT(unsigned Opcode);
1264bool isXSAVE64(unsigned Opcode);
1265bool isVPMAXSD(unsigned Opcode);
1266bool isCVTTSD2SI(unsigned Opcode);
1267bool isVCVTTSS2SIS(unsigned Opcode);
1268bool isPMOVMSKB(unsigned Opcode);
1269bool isVRANGEPS(unsigned Opcode);
1270bool isVADDSUBPS(unsigned Opcode);
1271bool isVBROADCASTI128(unsigned Opcode);
1272bool isPADDUSB(unsigned Opcode);
1273bool isENCODEKEY128(unsigned Opcode);
1274bool isOR(unsigned Opcode);
1275bool isSTOSW(unsigned Opcode);
1276bool isVCVTTPD2UQQS(unsigned Opcode);
1277bool isPAVGW(unsigned Opcode);
1278bool isVCVTPD2PH(unsigned Opcode);
1279bool isSHLX(unsigned Opcode);
1280bool isVCVTSH2SD(unsigned Opcode);
1281bool isVFMADD231SS(unsigned Opcode);
1282bool isMOVNTSD(unsigned Opcode);
1283bool isFLDPI(unsigned Opcode);
1284bool isVCVTUSI2SS(unsigned Opcode);
1285bool isPMOVSXBD(unsigned Opcode);
1286bool isVPRORVQ(unsigned Opcode);
1287bool isVPERMT2D(unsigned Opcode);
1288bool isADDSS(unsigned Opcode);
1289bool isAADD(unsigned Opcode);
1290bool isVPSRLVW(unsigned Opcode);
1291bool isVRSQRTPH(unsigned Opcode);
1292bool isVLDDQU(unsigned Opcode);
1293bool isKMOVD(unsigned Opcode);
1294bool isENCLV(unsigned Opcode);
1295bool isENCLU(unsigned Opcode);
1296bool isPREFETCHT1(unsigned Opcode);
1297bool isRSQRTPS(unsigned Opcode);
1298bool isVCVTTSH2USI(unsigned Opcode);
1299bool isPADDB(unsigned Opcode);
1300bool isVMASKMOVDQU(unsigned Opcode);
1301bool isPUNPCKLBW(unsigned Opcode);
1302bool isMOV(unsigned Opcode);
1303bool isVCVTTPH2IUBS(unsigned Opcode);
1304bool isMUL(unsigned Opcode);
1305bool isRCL(unsigned Opcode);
1306bool isVRCPSH(unsigned Opcode);
1307bool isPFCMPEQ(unsigned Opcode);
1308bool isMONITOR(unsigned Opcode);
1309bool isFDIVR(unsigned Opcode);
1310bool isPMINSD(unsigned Opcode);
1311bool isPFRCP(unsigned Opcode);
1312bool isKTESTQ(unsigned Opcode);
1313bool isVCVTTPD2DQ(unsigned Opcode);
1314bool isVSHUFF32X4(unsigned Opcode);
1315bool isVPSLLVW(unsigned Opcode);
1316bool isTDPBSUD(unsigned Opcode);
1317bool isVPMINUQ(unsigned Opcode);
1318bool isFIADD(unsigned Opcode);
1319bool isFCMOVNU(unsigned Opcode);
1320bool isVHSUBPD(unsigned Opcode);
1321bool isKSHIFTRQ(unsigned Opcode);
1322bool isMOVUPS(unsigned Opcode);
1323bool isVMCALL(unsigned Opcode);
1324bool isXADD(unsigned Opcode);
1325bool isXRSTOR(unsigned Opcode);
1326bool isVGATHERPF1DPD(unsigned Opcode);
1327bool isRCR(unsigned Opcode);
1328bool isFNSTCW(unsigned Opcode);
1329bool isVPMOVSDW(unsigned Opcode);
1330bool isVFMSUB132SH(unsigned Opcode);
1331bool isVPCONFLICTQ(unsigned Opcode);
1332bool isSWAPGS(unsigned Opcode);
1333bool isVPMOVQ2M(unsigned Opcode);
1334bool isVPSRAVW(unsigned Opcode);
1335bool isMOVDQA(unsigned Opcode);
1336bool isDIVSD(unsigned Opcode);
1337bool isPCMPGTB(unsigned Opcode);
1338bool isSHA256MSG2(unsigned Opcode);
1339bool isKXORW(unsigned Opcode);
1340bool isLIDTW(unsigned Opcode);
1341bool isPMULHW(unsigned Opcode);
1342bool isVAESENCLAST(unsigned Opcode);
1343bool isVINSERTI32X8(unsigned Opcode);
1344bool isVRCPPS(unsigned Opcode);
1345bool isVRSQRTBF16(unsigned Opcode);
1346bool isVGATHERQPS(unsigned Opcode);
1347bool isCTESTCC(unsigned Opcode);
1348bool isPMADDWD(unsigned Opcode);
1349bool isUCOMISS(unsigned Opcode);
1350bool isXGETBV(unsigned Opcode);
1351bool isVCVTPD2QQ(unsigned Opcode);
1352bool isVGETEXPPS(unsigned Opcode);
1353bool isFISTP(unsigned Opcode);
1354bool isVINSERTF64X4(unsigned Opcode);
1355bool isVMOVDQU16(unsigned Opcode);
1356bool isVFMADD132PH(unsigned Opcode);
1357bool isVFMSUBADD213PS(unsigned Opcode);
1358bool isVMOVDQU32(unsigned Opcode);
1359bool isFUCOM(unsigned Opcode);
1360bool isVFNMADD213BF16(unsigned Opcode);
1361bool isHADDPS(unsigned Opcode);
1362bool isCMP(unsigned Opcode);
1363bool isCVTTPS2PI(unsigned Opcode);
1364bool isIRETQ(unsigned Opcode);
1365bool isPF2IW(unsigned Opcode);
1366bool isPSHUFD(unsigned Opcode);
1367bool isVDPPD(unsigned Opcode);
1368bool isPSHUFHW(unsigned Opcode);
1369bool isRMPADJUST(unsigned Opcode);
1370bool isPI2FW(unsigned Opcode);
1371bool isVCVTTPH2QQ(unsigned Opcode);
1372bool isDIVPD(unsigned Opcode);
1373bool isCLFLUSH(unsigned Opcode);
1374bool isVPMINUW(unsigned Opcode);
1375bool isIN(unsigned Opcode);
1376bool isWRPKRU(unsigned Opcode);
1377bool isINSERTPS(unsigned Opcode);
1378bool isAAM(unsigned Opcode);
1379bool isVPHADDUDQ(unsigned Opcode);
1380bool isVSHA512MSG1(unsigned Opcode);
1381bool isDIVPS(unsigned Opcode);
1382bool isKNOTB(unsigned Opcode);
1383bool isBLSFILL(unsigned Opcode);
1384bool isVPCMPGTQ(unsigned Opcode);
1385bool isMINSD(unsigned Opcode);
1386bool isFPREM(unsigned Opcode);
1387bool isVPUNPCKHQDQ(unsigned Opcode);
1388bool isMINPD(unsigned Opcode);
1389bool isVCVTTPD2QQ(unsigned Opcode);
1390bool isVFMSUBPD(unsigned Opcode);
1391bool isV4FMADDSS(unsigned Opcode);
1392bool isCPUID(unsigned Opcode);
1393bool isSETCC(unsigned Opcode);
1394bool isVPDPWUUD(unsigned Opcode);
1395bool isVCVTTPS2IUBS(unsigned Opcode);
1396bool isPMOVSXDQ(unsigned Opcode);
1397bool isMWAIT(unsigned Opcode);
1398bool isVPEXTRB(unsigned Opcode);
1399bool isINVVPID(unsigned Opcode);
1400bool isVPSHUFD(unsigned Opcode);
1401bool isVMINBF16(unsigned Opcode);
1402bool isMOVLPS(unsigned Opcode);
1403bool isVBLENDMPS(unsigned Opcode);
1404bool isPMULLW(unsigned Opcode);
1405bool isVCVTSH2SI(unsigned Opcode);
1406bool isVPMOVSXWQ(unsigned Opcode);
1407bool isFNSTENV(unsigned Opcode);
1408bool isVCVT2PH2BF8(unsigned Opcode);
1409bool isVPERMI2PD(unsigned Opcode);
1410bool isMAXSS(unsigned Opcode);
1411bool isCWDE(unsigned Opcode);
1412bool isVBROADCASTI32X8(unsigned Opcode);
1413bool isINT(unsigned Opcode);
1414bool isENCLS(unsigned Opcode);
1415bool isMOVNTQ(unsigned Opcode);
1416bool isVDIVSH(unsigned Opcode);
1417bool isMOVHLPS(unsigned Opcode);
1418bool isVPMASKMOVD(unsigned Opcode);
1419bool isVMOVSD(unsigned Opcode);
1420bool isVPMINUD(unsigned Opcode);
1421bool isVPCMPISTRM(unsigned Opcode);
1422bool isVGETMANTSD(unsigned Opcode);
1423bool isKSHIFTRW(unsigned Opcode);
1424bool isAESDECLAST(unsigned Opcode);
1425bool isVFNMSUB231BF16(unsigned Opcode);
1426bool isVMPTRST(unsigned Opcode);
1427bool isLLDT(unsigned Opcode);
1428bool isVPTESTMB(unsigned Opcode);
1429bool isMOVSB(unsigned Opcode);
1430bool isTILELOADD(unsigned Opcode);
1431bool isKTESTB(unsigned Opcode);
1432bool isMOVUPD(unsigned Opcode);
1433bool isLKGS(unsigned Opcode);
1434bool isSGDTW(unsigned Opcode);
1435bool isDIVSS(unsigned Opcode);
1436bool isPUNPCKHQDQ(unsigned Opcode);
1437bool isVFMADD213SD(unsigned Opcode);
1438bool isKXORD(unsigned Opcode);
1439bool isVPMOVB2M(unsigned Opcode);
1440bool isVMREAD(unsigned Opcode);
1441bool isVPDPWSSDS(unsigned Opcode);
1442bool isTILERELEASE(unsigned Opcode);
1443bool isVUCOMXSH(unsigned Opcode);
1444bool isCLFLUSHOPT(unsigned Opcode);
1445bool isDAS(unsigned Opcode);
1446bool isVSCALEFPH(unsigned Opcode);
1447bool isVSUBSD(unsigned Opcode);
1448bool isVCOMISS(unsigned Opcode);
1449bool isVMULBF16(unsigned Opcode);
1450bool isORPS(unsigned Opcode);
1451bool isTDPFP16PS(unsigned Opcode);
1452bool isVMAXPD(unsigned Opcode);
1453bool isVPMOVWB(unsigned Opcode);
1454bool isVEXP2PS(unsigned Opcode);
1455bool isVPGATHERDQ(unsigned Opcode);
1456bool isVPSRAVQ(unsigned Opcode);
1457bool isPCMPISTRI(unsigned Opcode);
1458bool isVFMSUB231PD(unsigned Opcode);
1459bool isRDMSR(unsigned Opcode);
1460bool isKORTESTD(unsigned Opcode);
1461bool isVPBLENDMW(unsigned Opcode);
1462bool isPSHUFB(unsigned Opcode);
1463bool isVDPBF16PS(unsigned Opcode);
1464bool isTDPBF16PS(unsigned Opcode);
1465bool isFCMOVE(unsigned Opcode);
1466bool isVFMADD231BF16(unsigned Opcode);
1467bool isCMPSS(unsigned Opcode);
1468bool isMASKMOVDQU(unsigned Opcode);
1469bool isVPDPWUSDS(unsigned Opcode);
1470bool isSARX(unsigned Opcode);
1471bool isSGDT(unsigned Opcode);
1472bool isVFMULCPH(unsigned Opcode);
1473bool isURDMSR(unsigned Opcode);
1474bool isKUNPCKWD(unsigned Opcode);
1475bool isVSCALEFBF16(unsigned Opcode);
1476bool isCVTPS2PD(unsigned Opcode);
1477bool isFBSTP(unsigned Opcode);
1478bool isPSUBQ(unsigned Opcode);
1479bool isFXSAVE64(unsigned Opcode);
1480bool isKMOVW(unsigned Opcode);
1481bool isBTS(unsigned Opcode);
1482bool isVPHADDBQ(unsigned Opcode);
1483bool isFRSTOR(unsigned Opcode);
1484bool isVFMSUB132PD(unsigned Opcode);
1485bool isPMULLD(unsigned Opcode);
1486bool isSHA1MSG2(unsigned Opcode);
1487bool isJECXZ(unsigned Opcode);
1488bool isVCVTUDQ2PS(unsigned Opcode);
1489bool isAESENC(unsigned Opcode);
1490bool isVMINMAXPS(unsigned Opcode);
1491bool isPSIGNW(unsigned Opcode);
1492bool isUNPCKLPD(unsigned Opcode);
1493bool isPUSHP(unsigned Opcode);
1494bool isBLSI(unsigned Opcode);
1495bool isVPTESTNMB(unsigned Opcode);
1496bool isWRUSSQ(unsigned Opcode);
1497bool isVGF2P8MULB(unsigned Opcode);
1498bool isVPUNPCKLBW(unsigned Opcode);
1499bool isVRANGESD(unsigned Opcode);
1500bool isCLD(unsigned Opcode);
1501bool isVSCALEFPD(unsigned Opcode);
1502bool isVCOMXSS(unsigned Opcode);
1503bool isVPERMQ(unsigned Opcode);
1504bool isVPSHLDVW(unsigned Opcode);
1505bool isROR(unsigned Opcode);
1506bool isVFMADDSUB132PH(unsigned Opcode);
1507bool isDEC(unsigned Opcode);
1508bool isVGETEXPSH(unsigned Opcode);
1509bool isAESDEC(unsigned Opcode);
1510bool isKORD(unsigned Opcode);
1511bool isVPMULHW(unsigned Opcode);
1512bool isTILELOADDT1(unsigned Opcode);
1513bool isVMASKMOVPS(unsigned Opcode);
1514bool isPMOVZXDQ(unsigned Opcode);
1515bool isVCVTPS2PH(unsigned Opcode);
1516bool isCVTDQ2PD(unsigned Opcode);
1517bool isVCVTSD2SS(unsigned Opcode);
1518bool isVFMSUB213PH(unsigned Opcode);
1519bool isVPROTB(unsigned Opcode);
1520bool isPINSRD(unsigned Opcode);
1521bool isVMXON(unsigned Opcode);
1522bool isVFCMULCSH(unsigned Opcode);
1523bool isVFMULCSH(unsigned Opcode);
1524bool isVRANGEPD(unsigned Opcode);
1525bool isCMC(unsigned Opcode);
1526bool isVFNMADD231BF16(unsigned Opcode);
1527bool isSHA256MSG1(unsigned Opcode);
1528bool isFLD1(unsigned Opcode);
1529bool isCMPPS(unsigned Opcode);
1530bool isVPAVGW(unsigned Opcode);
1531bool isVFMADD213SH(unsigned Opcode);
1532bool isVPINSRQ(unsigned Opcode);
1533bool isMOVABS(unsigned Opcode);
1534bool isVPSHAQ(unsigned Opcode);
1535bool isRDTSCP(unsigned Opcode);
1536bool isVFNMADD231SS(unsigned Opcode);
1537bool isTEST(unsigned Opcode);
1538bool isVPERMD(unsigned Opcode);
1539bool isVBCSTNESH2PS(unsigned Opcode);
1540bool isVGATHERPF0QPD(unsigned Opcode);
1541bool isVPERM2I128(unsigned Opcode);
1542bool isVMPSADBW(unsigned Opcode);
1543bool isVFNMSUB231PD(unsigned Opcode);
1544bool isPADDSB(unsigned Opcode);
1545bool isMWAITX(unsigned Opcode);
1546bool isMONITORX(unsigned Opcode);
1547bool isVPEXPANDD(unsigned Opcode);
1548bool isVFRCZPD(unsigned Opcode);
1549bool isVRCPPH(unsigned Opcode);
1550bool isFEMMS(unsigned Opcode);
1551bool isVSCATTERQPD(unsigned Opcode);
1552bool isVMOVW(unsigned Opcode);
1553bool isVPBROADCASTD(unsigned Opcode);
1554bool isSTOSB(unsigned Opcode);
1555bool isFUCOMI(unsigned Opcode);
1556bool isVBROADCASTI64X4(unsigned Opcode);
1557bool isFCMOVU(unsigned Opcode);
1558bool isPSHUFLW(unsigned Opcode);
1559bool isCVTPI2PS(unsigned Opcode);
1560bool isVCVTTPD2UDQS(unsigned Opcode);
1561bool isSYSCALL(unsigned Opcode);
1562bool isVFMADD231SH(unsigned Opcode);
1563bool isPMOVZXBW(unsigned Opcode);
1564bool isVPOPCNTB(unsigned Opcode);
1565bool isVCVTDQ2PS(unsigned Opcode);
1566bool isPSUBD(unsigned Opcode);
1567bool isVPCMPEQW(unsigned Opcode);
1568bool isMOVSW(unsigned Opcode);
1569bool isVSM3RNDS2(unsigned Opcode);
1570bool isVPMOVUSQD(unsigned Opcode);
1571bool isCVTTPD2DQ(unsigned Opcode);
1572bool isVPEXPANDW(unsigned Opcode);
1573bool isVUCOMISH(unsigned Opcode);
1574bool isVZEROALL(unsigned Opcode);
1575bool isVPAND(unsigned Opcode);
1576bool isPMULDQ(unsigned Opcode);
1577bool isVPSHUFHW(unsigned Opcode);
1578bool isVPALIGNR(unsigned Opcode);
1579bool isSQRTSD(unsigned Opcode);
1580bool isVCVTTPH2UDQ(unsigned Opcode);
1581bool isVGETEXPPH(unsigned Opcode);
1582bool isADDPD(unsigned Opcode);
1583bool isVFNMADDPD(unsigned Opcode);
1584bool isSTTILECFG(unsigned Opcode);
1585bool isVMINPD(unsigned Opcode);
1586bool isSHA1RNDS4(unsigned Opcode);
1587bool isPBLENDVB(unsigned Opcode);
1588bool isVBROADCASTF128(unsigned Opcode);
1589bool isVPSHRDQ(unsigned Opcode);
1590bool isVAESIMC(unsigned Opcode);
1591bool isCOMISD(unsigned Opcode);
1592bool isVMOVSH(unsigned Opcode);
1593bool isPFSUBR(unsigned Opcode);
1594bool isRDSSPD(unsigned Opcode);
1595bool isWAIT(unsigned Opcode);
1596bool isVFPCLASSSS(unsigned Opcode);
1597bool isPCMPGTD(unsigned Opcode);
1598bool isVGATHERPF0QPS(unsigned Opcode);
1599bool isBLENDVPS(unsigned Opcode);
1600bool isVBROADCASTF32X4(unsigned Opcode);
1601bool isVPMADD52LUQ(unsigned Opcode);
1602bool isVMOVLPD(unsigned Opcode);
1603bool isVMOVQ(unsigned Opcode);
1604bool isVMOVDQU(unsigned Opcode);
1605bool isAESENC128KL(unsigned Opcode);
1606bool isVFMADDSUB231PS(unsigned Opcode);
1607bool isVFNMSUB213PD(unsigned Opcode);
1608bool isVPCONFLICTD(unsigned Opcode);
1609bool isVFMADDSUB213PH(unsigned Opcode);
1610bool isVPHSUBSW(unsigned Opcode);
1611bool isPUNPCKHDQ(unsigned Opcode);
1612bool isVSHUFI64X2(unsigned Opcode);
1613bool isVFMSUBSD(unsigned Opcode);
1614bool isVPORD(unsigned Opcode);
1615bool isRCPPS(unsigned Opcode);
1616bool isVEXTRACTI128(unsigned Opcode);
1617bool isVCVT2PH2BF8S(unsigned Opcode);
1618bool isVPSHRDVW(unsigned Opcode);
1619bool isVUNPCKLPD(unsigned Opcode);
1620bool isVPSRAVD(unsigned Opcode);
1621bool isVMULSH(unsigned Opcode);
1622bool isMOVNTSS(unsigned Opcode);
1623bool isSTI(unsigned Opcode);
1624bool isVSM4RNDS4(unsigned Opcode);
1625bool isVMCLEAR(unsigned Opcode);
1626bool isVPMADD52HUQ(unsigned Opcode);
1627bool isLIDT(unsigned Opcode);
1628bool isPUSH2(unsigned Opcode);
1629bool isVCVTPS2IUBS(unsigned Opcode);
1630bool isRDPKRU(unsigned Opcode);
1631bool isVPCMPB(unsigned Opcode);
1632bool isVFMSUB231BF16(unsigned Opcode);
1633bool isFINCSTP(unsigned Opcode);
1634bool isKORQ(unsigned Opcode);
1635bool isXCRYPTCBC(unsigned Opcode);
1636bool isRDPMC(unsigned Opcode);
1637bool isMOVMSKPD(unsigned Opcode);
1638bool isVFMSUB231SH(unsigned Opcode);
1639bool isVEXTRACTF128(unsigned Opcode);
1640bool isVPSHLB(unsigned Opcode);
1641bool isXSAVES64(unsigned Opcode);
1642bool isSHL(unsigned Opcode);
1643bool isAXOR(unsigned Opcode);
1644bool isVINSERTI64X2(unsigned Opcode);
1645bool isSYSRETQ(unsigned Opcode);
1646bool isVSCATTERPF0QPD(unsigned Opcode);
1647bool isVFMSUB213SH(unsigned Opcode);
1648bool isVPMOVQW(unsigned Opcode);
1649bool isVREDUCEPD(unsigned Opcode);
1650bool isNOT(unsigned Opcode);
1651bool isLWPINS(unsigned Opcode);
1652bool isVSCATTERDPS(unsigned Opcode);
1653bool isVPMOVM2W(unsigned Opcode);
1654bool isVFNMADD132PS(unsigned Opcode);
1655bool isMOVNTPS(unsigned Opcode);
1656bool isVRSQRTSS(unsigned Opcode);
1657bool isKMOVB(unsigned Opcode);
1658bool isCVTSD2SS(unsigned Opcode);
1659bool isVBROADCASTF64X2(unsigned Opcode);
1660bool isMOVNTPD(unsigned Opcode);
1661bool isMAXSD(unsigned Opcode);
1662bool isCMPPD(unsigned Opcode);
1663bool isVPCMPESTRM(unsigned Opcode);
1664bool isVFMSUB132PS(unsigned Opcode);
1665bool isVCOMISH(unsigned Opcode);
1666bool isF2XM1(unsigned Opcode);
1667bool isVDIVBF16(unsigned Opcode);
1668bool isSQRTPD(unsigned Opcode);
1669bool isVFMSUBADDPS(unsigned Opcode);
1670bool isFXTRACT(unsigned Opcode);
1671bool isVP4DPWSSD(unsigned Opcode);
1672bool isTDPBHF8PS(unsigned Opcode);
1673bool isVFMSUBADDPD(unsigned Opcode);
1674bool isVBCSTNEBF162PS(unsigned Opcode);
1675bool isVPGATHERQQ(unsigned Opcode);
1676bool isPCMPEQB(unsigned Opcode);
1677bool isTILESTORED(unsigned Opcode);
1678bool isBLSMSK(unsigned Opcode);
1679bool isVCVTTPS2DQ(unsigned Opcode);
1680bool isVRNDSCALEPD(unsigned Opcode);
1681bool isVFPCLASSBF16(unsigned Opcode);
1682bool isVMLOAD(unsigned Opcode);
1683bool isVPTERNLOGQ(unsigned Opcode);
1684bool isKXNORD(unsigned Opcode);
1685bool isFXSAVE(unsigned Opcode);
1686bool isVUNPCKHPD(unsigned Opcode);
1687bool isCVTPS2DQ(unsigned Opcode);
1688bool isTMMULTF32PS(unsigned Opcode);
1689bool isVFMSUB213SS(unsigned Opcode);
1690bool isVPOPCNTD(unsigned Opcode);
1691bool isSALC(unsigned Opcode);
1692bool isV4FNMADDSS(unsigned Opcode);
1693bool isXCRYPTOFB(unsigned Opcode);
1694bool isVORPD(unsigned Opcode);
1695bool isLSL(unsigned Opcode);
1696bool isXCRYPTCFB(unsigned Opcode);
1697bool isVGETEXPSS(unsigned Opcode);
1698bool isPSLLDQ(unsigned Opcode);
1699bool isVPDPBUUD(unsigned Opcode);
1700bool isVMXOFF(unsigned Opcode);
1701bool isBLSIC(unsigned Opcode);
1702bool isMOVLHPS(unsigned Opcode);
1703bool isVMOVRSQ(unsigned Opcode);
1704bool isVFNMSUBSD(unsigned Opcode);
1705bool isVCVTPH2IUBS(unsigned Opcode);
1706bool isVFPCLASSSH(unsigned Opcode);
1707bool isVPSHLQ(unsigned Opcode);
1708bool isVROUNDPS(unsigned Opcode);
1709bool isVSCATTERPF0QPS(unsigned Opcode);
1710bool isERETS(unsigned Opcode);
1711bool isVPERMI2D(unsigned Opcode);
1712bool isFUCOMP(unsigned Opcode);
1713bool isVCVTTPS2QQ(unsigned Opcode);
1714bool isPUSHFD(unsigned Opcode);
1715bool isKORB(unsigned Opcode);
1716bool isVRCP28PD(unsigned Opcode);
1717bool isVPABSD(unsigned Opcode);
1718bool isVROUNDSS(unsigned Opcode);
1719bool isVCVTSD2USI(unsigned Opcode);
1720bool isVPABSB(unsigned Opcode);
1721bool isPMAXUD(unsigned Opcode);
1722bool isVPMULHUW(unsigned Opcode);
1723bool isVPERMPD(unsigned Opcode);
1724bool isFCHS(unsigned Opcode);
1725bool isVPBLENDMB(unsigned Opcode);
1726bool isVGETMANTSS(unsigned Opcode);
1727bool isVPSLLW(unsigned Opcode);
1728bool isVDIVPD(unsigned Opcode);
1729bool isBLCMSK(unsigned Opcode);
1730bool isFDIV(unsigned Opcode);
1731bool isRSQRTSS(unsigned Opcode);
1732bool isPOR(unsigned Opcode);
1733bool isVMOVDQA32(unsigned Opcode);
1734bool isVPHADDUWQ(unsigned Opcode);
1735bool isPSRAD(unsigned Opcode);
1736bool isPREFETCHW(unsigned Opcode);
1737bool isFIDIVR(unsigned Opcode);
1738bool isMOVHPS(unsigned Opcode);
1739bool isVFNMSUB231PH(unsigned Opcode);
1740bool isUNPCKLPS(unsigned Opcode);
1741bool isVPSIGNB(unsigned Opcode);
1742bool isSAVEPREVSSP(unsigned Opcode);
1743bool isVSCALEFSD(unsigned Opcode);
1744bool isFSIN(unsigned Opcode);
1745bool isSCASQ(unsigned Opcode);
1746bool isVCVTTPD2QQS(unsigned Opcode);
1747bool isPCMPGTW(unsigned Opcode);
1748bool isMULX(unsigned Opcode);
1749bool isVPMAXUW(unsigned Opcode);
1750bool isPAUSE(unsigned Opcode);
1751bool isMOVQ2DQ(unsigned Opcode);
1752bool isVPSUBQ(unsigned Opcode);
1753bool isVPABSW(unsigned Opcode);
1754bool isVPCOMPRESSD(unsigned Opcode);
1755bool isVPMOVUSQW(unsigned Opcode);
1756bool isBLENDVPD(unsigned Opcode);
1757bool isVFNMADD132BF16(unsigned Opcode);
1758bool isVPMOVQB(unsigned Opcode);
1759bool isVBLENDVPS(unsigned Opcode);
1760bool isKSHIFTLQ(unsigned Opcode);
1761bool isPMOVSXWD(unsigned Opcode);
1762bool isPHSUBSW(unsigned Opcode);
1763bool isPSRLQ(unsigned Opcode);
1764bool isVCVTPH2DQ(unsigned Opcode);
1765bool isFISUB(unsigned Opcode);
1766bool isVCVTPS2UDQ(unsigned Opcode);
1767bool isVMOVDDUP(unsigned Opcode);
1768bool isPCMPEQD(unsigned Opcode);
1769bool isVRSQRT28SD(unsigned Opcode);
1770bool isTDPHBF8PS(unsigned Opcode);
1771bool isLODSW(unsigned Opcode);
1772bool isVPOPCNTQ(unsigned Opcode);
1773bool isKSHIFTRB(unsigned Opcode);
1774bool isVFNMADDPS(unsigned Opcode);
1775bool isCCMPCC(unsigned Opcode);
1776bool isFXRSTOR64(unsigned Opcode);
1777bool isVFMSUBADD213PD(unsigned Opcode);
1778bool isVSQRTPH(unsigned Opcode);
1779bool isPOPF(unsigned Opcode);
1780bool isVPSUBUSB(unsigned Opcode);
1781bool isTCVTROWPS2BF16L(unsigned Opcode);
1782bool isPREFETCHIT1(unsigned Opcode);
1783bool isVPADDSW(unsigned Opcode);
1784bool isVADDSUBPD(unsigned Opcode);
1785bool isKANDD(unsigned Opcode);
1786bool isOUTSB(unsigned Opcode);
1787bool isPREFETCHRST2(unsigned Opcode);
1788bool isFNSTSW(unsigned Opcode);
1789bool isPMINSB(unsigned Opcode);
1790
1791} // namespace llvm::X86
1792
1793#endif // GET_X86_MNEMONIC_TABLES_H
1794
1795#ifdef GET_X86_MNEMONIC_TABLES_CPP
1796#undef GET_X86_MNEMONIC_TABLES_CPP
1797
1798namespace llvm::X86 {
1799
1800bool isFSUBRP(unsigned Opcode) {
1801 return Opcode == SUBR_FPrST0;
1802}
1803
1804bool isVPDPBUSDS(unsigned Opcode) {
1805 switch (Opcode) {
1806 case VPDPBUSDSYrm:
1807 case VPDPBUSDSYrr:
1808 case VPDPBUSDSZ128rm:
1809 case VPDPBUSDSZ128rmb:
1810 case VPDPBUSDSZ128rmbk:
1811 case VPDPBUSDSZ128rmbkz:
1812 case VPDPBUSDSZ128rmk:
1813 case VPDPBUSDSZ128rmkz:
1814 case VPDPBUSDSZ128rr:
1815 case VPDPBUSDSZ128rrk:
1816 case VPDPBUSDSZ128rrkz:
1817 case VPDPBUSDSZ256rm:
1818 case VPDPBUSDSZ256rmb:
1819 case VPDPBUSDSZ256rmbk:
1820 case VPDPBUSDSZ256rmbkz:
1821 case VPDPBUSDSZ256rmk:
1822 case VPDPBUSDSZ256rmkz:
1823 case VPDPBUSDSZ256rr:
1824 case VPDPBUSDSZ256rrk:
1825 case VPDPBUSDSZ256rrkz:
1826 case VPDPBUSDSZrm:
1827 case VPDPBUSDSZrmb:
1828 case VPDPBUSDSZrmbk:
1829 case VPDPBUSDSZrmbkz:
1830 case VPDPBUSDSZrmk:
1831 case VPDPBUSDSZrmkz:
1832 case VPDPBUSDSZrr:
1833 case VPDPBUSDSZrrk:
1834 case VPDPBUSDSZrrkz:
1835 case VPDPBUSDSrm:
1836 case VPDPBUSDSrr:
1837 return true;
1838 }
1839 return false;
1840}
1841
1842bool isPUNPCKLWD(unsigned Opcode) {
1843 switch (Opcode) {
1844 case MMX_PUNPCKLWDrm:
1845 case MMX_PUNPCKLWDrr:
1846 case PUNPCKLWDrm:
1847 case PUNPCKLWDrr:
1848 return true;
1849 }
1850 return false;
1851}
1852
1853bool isVREDUCEBF16(unsigned Opcode) {
1854 switch (Opcode) {
1855 case VREDUCEBF16Z128rmbi:
1856 case VREDUCEBF16Z128rmbik:
1857 case VREDUCEBF16Z128rmbikz:
1858 case VREDUCEBF16Z128rmi:
1859 case VREDUCEBF16Z128rmik:
1860 case VREDUCEBF16Z128rmikz:
1861 case VREDUCEBF16Z128rri:
1862 case VREDUCEBF16Z128rrik:
1863 case VREDUCEBF16Z128rrikz:
1864 case VREDUCEBF16Z256rmbi:
1865 case VREDUCEBF16Z256rmbik:
1866 case VREDUCEBF16Z256rmbikz:
1867 case VREDUCEBF16Z256rmi:
1868 case VREDUCEBF16Z256rmik:
1869 case VREDUCEBF16Z256rmikz:
1870 case VREDUCEBF16Z256rri:
1871 case VREDUCEBF16Z256rrik:
1872 case VREDUCEBF16Z256rrikz:
1873 case VREDUCEBF16Zrmbi:
1874 case VREDUCEBF16Zrmbik:
1875 case VREDUCEBF16Zrmbikz:
1876 case VREDUCEBF16Zrmi:
1877 case VREDUCEBF16Zrmik:
1878 case VREDUCEBF16Zrmikz:
1879 case VREDUCEBF16Zrri:
1880 case VREDUCEBF16Zrrik:
1881 case VREDUCEBF16Zrrikz:
1882 return true;
1883 }
1884 return false;
1885}
1886
1887bool isPUNPCKLQDQ(unsigned Opcode) {
1888 switch (Opcode) {
1889 case PUNPCKLQDQrm:
1890 case PUNPCKLQDQrr:
1891 return true;
1892 }
1893 return false;
1894}
1895
1896bool isRDFSBASE(unsigned Opcode) {
1897 switch (Opcode) {
1898 case RDFSBASE:
1899 case RDFSBASE64:
1900 return true;
1901 }
1902 return false;
1903}
1904
1905bool isVPCMOV(unsigned Opcode) {
1906 switch (Opcode) {
1907 case VPCMOVYrmr:
1908 case VPCMOVYrrm:
1909 case VPCMOVYrrr:
1910 case VPCMOVYrrr_REV:
1911 case VPCMOVrmr:
1912 case VPCMOVrrm:
1913 case VPCMOVrrr:
1914 case VPCMOVrrr_REV:
1915 return true;
1916 }
1917 return false;
1918}
1919
1920bool isVDIVSD(unsigned Opcode) {
1921 switch (Opcode) {
1922 case VDIVSDZrm_Int:
1923 case VDIVSDZrmk_Int:
1924 case VDIVSDZrmkz_Int:
1925 case VDIVSDZrr_Int:
1926 case VDIVSDZrrb_Int:
1927 case VDIVSDZrrbk_Int:
1928 case VDIVSDZrrbkz_Int:
1929 case VDIVSDZrrk_Int:
1930 case VDIVSDZrrkz_Int:
1931 case VDIVSDrm_Int:
1932 case VDIVSDrr_Int:
1933 return true;
1934 }
1935 return false;
1936}
1937
1938bool isVCVTTPS2IBS(unsigned Opcode) {
1939 switch (Opcode) {
1940 case VCVTTPS2IBSZ128rm:
1941 case VCVTTPS2IBSZ128rmb:
1942 case VCVTTPS2IBSZ128rmbk:
1943 case VCVTTPS2IBSZ128rmbkz:
1944 case VCVTTPS2IBSZ128rmk:
1945 case VCVTTPS2IBSZ128rmkz:
1946 case VCVTTPS2IBSZ128rr:
1947 case VCVTTPS2IBSZ128rrk:
1948 case VCVTTPS2IBSZ128rrkz:
1949 case VCVTTPS2IBSZ256rm:
1950 case VCVTTPS2IBSZ256rmb:
1951 case VCVTTPS2IBSZ256rmbk:
1952 case VCVTTPS2IBSZ256rmbkz:
1953 case VCVTTPS2IBSZ256rmk:
1954 case VCVTTPS2IBSZ256rmkz:
1955 case VCVTTPS2IBSZ256rr:
1956 case VCVTTPS2IBSZ256rrk:
1957 case VCVTTPS2IBSZ256rrkz:
1958 case VCVTTPS2IBSZrm:
1959 case VCVTTPS2IBSZrmb:
1960 case VCVTTPS2IBSZrmbk:
1961 case VCVTTPS2IBSZrmbkz:
1962 case VCVTTPS2IBSZrmk:
1963 case VCVTTPS2IBSZrmkz:
1964 case VCVTTPS2IBSZrr:
1965 case VCVTTPS2IBSZrrb:
1966 case VCVTTPS2IBSZrrbk:
1967 case VCVTTPS2IBSZrrbkz:
1968 case VCVTTPS2IBSZrrk:
1969 case VCVTTPS2IBSZrrkz:
1970 return true;
1971 }
1972 return false;
1973}
1974
1975bool isVPEXTRW(unsigned Opcode) {
1976 switch (Opcode) {
1977 case VPEXTRWZmri:
1978 case VPEXTRWZrri:
1979 case VPEXTRWZrri_REV:
1980 case VPEXTRWmri:
1981 case VPEXTRWrri:
1982 case VPEXTRWrri_REV:
1983 return true;
1984 }
1985 return false;
1986}
1987
1988bool isLODSD(unsigned Opcode) {
1989 return Opcode == LODSL;
1990}
1991
1992bool isVPTESTNMQ(unsigned Opcode) {
1993 switch (Opcode) {
1994 case VPTESTNMQZ128rm:
1995 case VPTESTNMQZ128rmb:
1996 case VPTESTNMQZ128rmbk:
1997 case VPTESTNMQZ128rmk:
1998 case VPTESTNMQZ128rr:
1999 case VPTESTNMQZ128rrk:
2000 case VPTESTNMQZ256rm:
2001 case VPTESTNMQZ256rmb:
2002 case VPTESTNMQZ256rmbk:
2003 case VPTESTNMQZ256rmk:
2004 case VPTESTNMQZ256rr:
2005 case VPTESTNMQZ256rrk:
2006 case VPTESTNMQZrm:
2007 case VPTESTNMQZrmb:
2008 case VPTESTNMQZrmbk:
2009 case VPTESTNMQZrmk:
2010 case VPTESTNMQZrr:
2011 case VPTESTNMQZrrk:
2012 return true;
2013 }
2014 return false;
2015}
2016
2017bool isCVTSS2SD(unsigned Opcode) {
2018 switch (Opcode) {
2019 case CVTSS2SDrm_Int:
2020 case CVTSS2SDrr_Int:
2021 return true;
2022 }
2023 return false;
2024}
2025
2026bool isVGETMANTPD(unsigned Opcode) {
2027 switch (Opcode) {
2028 case VGETMANTPDZ128rmbi:
2029 case VGETMANTPDZ128rmbik:
2030 case VGETMANTPDZ128rmbikz:
2031 case VGETMANTPDZ128rmi:
2032 case VGETMANTPDZ128rmik:
2033 case VGETMANTPDZ128rmikz:
2034 case VGETMANTPDZ128rri:
2035 case VGETMANTPDZ128rrik:
2036 case VGETMANTPDZ128rrikz:
2037 case VGETMANTPDZ256rmbi:
2038 case VGETMANTPDZ256rmbik:
2039 case VGETMANTPDZ256rmbikz:
2040 case VGETMANTPDZ256rmi:
2041 case VGETMANTPDZ256rmik:
2042 case VGETMANTPDZ256rmikz:
2043 case VGETMANTPDZ256rri:
2044 case VGETMANTPDZ256rrik:
2045 case VGETMANTPDZ256rrikz:
2046 case VGETMANTPDZrmbi:
2047 case VGETMANTPDZrmbik:
2048 case VGETMANTPDZrmbikz:
2049 case VGETMANTPDZrmi:
2050 case VGETMANTPDZrmik:
2051 case VGETMANTPDZrmikz:
2052 case VGETMANTPDZrri:
2053 case VGETMANTPDZrrib:
2054 case VGETMANTPDZrribk:
2055 case VGETMANTPDZrribkz:
2056 case VGETMANTPDZrrik:
2057 case VGETMANTPDZrrikz:
2058 return true;
2059 }
2060 return false;
2061}
2062
2063bool isVMOVDQA64(unsigned Opcode) {
2064 switch (Opcode) {
2065 case VMOVDQA64Z128mr:
2066 case VMOVDQA64Z128mrk:
2067 case VMOVDQA64Z128rm:
2068 case VMOVDQA64Z128rmk:
2069 case VMOVDQA64Z128rmkz:
2070 case VMOVDQA64Z128rr:
2071 case VMOVDQA64Z128rr_REV:
2072 case VMOVDQA64Z128rrk:
2073 case VMOVDQA64Z128rrk_REV:
2074 case VMOVDQA64Z128rrkz:
2075 case VMOVDQA64Z128rrkz_REV:
2076 case VMOVDQA64Z256mr:
2077 case VMOVDQA64Z256mrk:
2078 case VMOVDQA64Z256rm:
2079 case VMOVDQA64Z256rmk:
2080 case VMOVDQA64Z256rmkz:
2081 case VMOVDQA64Z256rr:
2082 case VMOVDQA64Z256rr_REV:
2083 case VMOVDQA64Z256rrk:
2084 case VMOVDQA64Z256rrk_REV:
2085 case VMOVDQA64Z256rrkz:
2086 case VMOVDQA64Z256rrkz_REV:
2087 case VMOVDQA64Zmr:
2088 case VMOVDQA64Zmrk:
2089 case VMOVDQA64Zrm:
2090 case VMOVDQA64Zrmk:
2091 case VMOVDQA64Zrmkz:
2092 case VMOVDQA64Zrr:
2093 case VMOVDQA64Zrr_REV:
2094 case VMOVDQA64Zrrk:
2095 case VMOVDQA64Zrrk_REV:
2096 case VMOVDQA64Zrrkz:
2097 case VMOVDQA64Zrrkz_REV:
2098 return true;
2099 }
2100 return false;
2101}
2102
2103bool isINVLPG(unsigned Opcode) {
2104 return Opcode == INVLPG;
2105}
2106
2107bool isVGETEXPBF16(unsigned Opcode) {
2108 switch (Opcode) {
2109 case VGETEXPBF16Z128m:
2110 case VGETEXPBF16Z128mb:
2111 case VGETEXPBF16Z128mbk:
2112 case VGETEXPBF16Z128mbkz:
2113 case VGETEXPBF16Z128mk:
2114 case VGETEXPBF16Z128mkz:
2115 case VGETEXPBF16Z128r:
2116 case VGETEXPBF16Z128rk:
2117 case VGETEXPBF16Z128rkz:
2118 case VGETEXPBF16Z256m:
2119 case VGETEXPBF16Z256mb:
2120 case VGETEXPBF16Z256mbk:
2121 case VGETEXPBF16Z256mbkz:
2122 case VGETEXPBF16Z256mk:
2123 case VGETEXPBF16Z256mkz:
2124 case VGETEXPBF16Z256r:
2125 case VGETEXPBF16Z256rk:
2126 case VGETEXPBF16Z256rkz:
2127 case VGETEXPBF16Zm:
2128 case VGETEXPBF16Zmb:
2129 case VGETEXPBF16Zmbk:
2130 case VGETEXPBF16Zmbkz:
2131 case VGETEXPBF16Zmk:
2132 case VGETEXPBF16Zmkz:
2133 case VGETEXPBF16Zr:
2134 case VGETEXPBF16Zrk:
2135 case VGETEXPBF16Zrkz:
2136 return true;
2137 }
2138 return false;
2139}
2140
2141bool isVBROADCASTF64X4(unsigned Opcode) {
2142 switch (Opcode) {
2143 case VBROADCASTF64X4Zrm:
2144 case VBROADCASTF64X4Zrmk:
2145 case VBROADCASTF64X4Zrmkz:
2146 return true;
2147 }
2148 return false;
2149}
2150
2151bool isVPERMI2Q(unsigned Opcode) {
2152 switch (Opcode) {
2153 case VPERMI2QZ128rm:
2154 case VPERMI2QZ128rmb:
2155 case VPERMI2QZ128rmbk:
2156 case VPERMI2QZ128rmbkz:
2157 case VPERMI2QZ128rmk:
2158 case VPERMI2QZ128rmkz:
2159 case VPERMI2QZ128rr:
2160 case VPERMI2QZ128rrk:
2161 case VPERMI2QZ128rrkz:
2162 case VPERMI2QZ256rm:
2163 case VPERMI2QZ256rmb:
2164 case VPERMI2QZ256rmbk:
2165 case VPERMI2QZ256rmbkz:
2166 case VPERMI2QZ256rmk:
2167 case VPERMI2QZ256rmkz:
2168 case VPERMI2QZ256rr:
2169 case VPERMI2QZ256rrk:
2170 case VPERMI2QZ256rrkz:
2171 case VPERMI2QZrm:
2172 case VPERMI2QZrmb:
2173 case VPERMI2QZrmbk:
2174 case VPERMI2QZrmbkz:
2175 case VPERMI2QZrmk:
2176 case VPERMI2QZrmkz:
2177 case VPERMI2QZrr:
2178 case VPERMI2QZrrk:
2179 case VPERMI2QZrrkz:
2180 return true;
2181 }
2182 return false;
2183}
2184
2185bool isVPMOVSXBD(unsigned Opcode) {
2186 switch (Opcode) {
2187 case VPMOVSXBDYrm:
2188 case VPMOVSXBDYrr:
2189 case VPMOVSXBDZ128rm:
2190 case VPMOVSXBDZ128rmk:
2191 case VPMOVSXBDZ128rmkz:
2192 case VPMOVSXBDZ128rr:
2193 case VPMOVSXBDZ128rrk:
2194 case VPMOVSXBDZ128rrkz:
2195 case VPMOVSXBDZ256rm:
2196 case VPMOVSXBDZ256rmk:
2197 case VPMOVSXBDZ256rmkz:
2198 case VPMOVSXBDZ256rr:
2199 case VPMOVSXBDZ256rrk:
2200 case VPMOVSXBDZ256rrkz:
2201 case VPMOVSXBDZrm:
2202 case VPMOVSXBDZrmk:
2203 case VPMOVSXBDZrmkz:
2204 case VPMOVSXBDZrr:
2205 case VPMOVSXBDZrrk:
2206 case VPMOVSXBDZrrkz:
2207 case VPMOVSXBDrm:
2208 case VPMOVSXBDrr:
2209 return true;
2210 }
2211 return false;
2212}
2213
2214bool isVFMSUB132SS(unsigned Opcode) {
2215 switch (Opcode) {
2216 case VFMSUB132SSZm_Int:
2217 case VFMSUB132SSZmk_Int:
2218 case VFMSUB132SSZmkz_Int:
2219 case VFMSUB132SSZr_Int:
2220 case VFMSUB132SSZrb_Int:
2221 case VFMSUB132SSZrbk_Int:
2222 case VFMSUB132SSZrbkz_Int:
2223 case VFMSUB132SSZrk_Int:
2224 case VFMSUB132SSZrkz_Int:
2225 case VFMSUB132SSm_Int:
2226 case VFMSUB132SSr_Int:
2227 return true;
2228 }
2229 return false;
2230}
2231
2232bool isVPMOVUSDW(unsigned Opcode) {
2233 switch (Opcode) {
2234 case VPMOVUSDWZ128mr:
2235 case VPMOVUSDWZ128mrk:
2236 case VPMOVUSDWZ128rr:
2237 case VPMOVUSDWZ128rrk:
2238 case VPMOVUSDWZ128rrkz:
2239 case VPMOVUSDWZ256mr:
2240 case VPMOVUSDWZ256mrk:
2241 case VPMOVUSDWZ256rr:
2242 case VPMOVUSDWZ256rrk:
2243 case VPMOVUSDWZ256rrkz:
2244 case VPMOVUSDWZmr:
2245 case VPMOVUSDWZmrk:
2246 case VPMOVUSDWZrr:
2247 case VPMOVUSDWZrrk:
2248 case VPMOVUSDWZrrkz:
2249 return true;
2250 }
2251 return false;
2252}
2253
2254bool isAAD(unsigned Opcode) {
2255 return Opcode == AAD8i8;
2256}
2257
2258bool isIDIV(unsigned Opcode) {
2259 switch (Opcode) {
2260 case IDIV16m:
2261 case IDIV16m_EVEX:
2262 case IDIV16m_NF:
2263 case IDIV16r:
2264 case IDIV16r_EVEX:
2265 case IDIV16r_NF:
2266 case IDIV32m:
2267 case IDIV32m_EVEX:
2268 case IDIV32m_NF:
2269 case IDIV32r:
2270 case IDIV32r_EVEX:
2271 case IDIV32r_NF:
2272 case IDIV64m:
2273 case IDIV64m_EVEX:
2274 case IDIV64m_NF:
2275 case IDIV64r:
2276 case IDIV64r_EVEX:
2277 case IDIV64r_NF:
2278 case IDIV8m:
2279 case IDIV8m_EVEX:
2280 case IDIV8m_NF:
2281 case IDIV8r:
2282 case IDIV8r_EVEX:
2283 case IDIV8r_NF:
2284 return true;
2285 }
2286 return false;
2287}
2288
2289bool isCVTTPS2DQ(unsigned Opcode) {
2290 switch (Opcode) {
2291 case CVTTPS2DQrm:
2292 case CVTTPS2DQrr:
2293 return true;
2294 }
2295 return false;
2296}
2297
2298bool isVBROADCASTF32X8(unsigned Opcode) {
2299 switch (Opcode) {
2300 case VBROADCASTF32X8Zrm:
2301 case VBROADCASTF32X8Zrmk:
2302 case VBROADCASTF32X8Zrmkz:
2303 return true;
2304 }
2305 return false;
2306}
2307
2308bool isVFMSUBSS(unsigned Opcode) {
2309 switch (Opcode) {
2310 case VFMSUBSS4mr:
2311 case VFMSUBSS4rm:
2312 case VFMSUBSS4rr:
2313 case VFMSUBSS4rr_REV:
2314 return true;
2315 }
2316 return false;
2317}
2318
2319bool isEMMS(unsigned Opcode) {
2320 return Opcode == MMX_EMMS;
2321}
2322
2323bool isVPDPBSUD(unsigned Opcode) {
2324 switch (Opcode) {
2325 case VPDPBSUDYrm:
2326 case VPDPBSUDYrr:
2327 case VPDPBSUDZ128rm:
2328 case VPDPBSUDZ128rmb:
2329 case VPDPBSUDZ128rmbk:
2330 case VPDPBSUDZ128rmbkz:
2331 case VPDPBSUDZ128rmk:
2332 case VPDPBSUDZ128rmkz:
2333 case VPDPBSUDZ128rr:
2334 case VPDPBSUDZ128rrk:
2335 case VPDPBSUDZ128rrkz:
2336 case VPDPBSUDZ256rm:
2337 case VPDPBSUDZ256rmb:
2338 case VPDPBSUDZ256rmbk:
2339 case VPDPBSUDZ256rmbkz:
2340 case VPDPBSUDZ256rmk:
2341 case VPDPBSUDZ256rmkz:
2342 case VPDPBSUDZ256rr:
2343 case VPDPBSUDZ256rrk:
2344 case VPDPBSUDZ256rrkz:
2345 case VPDPBSUDZrm:
2346 case VPDPBSUDZrmb:
2347 case VPDPBSUDZrmbk:
2348 case VPDPBSUDZrmbkz:
2349 case VPDPBSUDZrmk:
2350 case VPDPBSUDZrmkz:
2351 case VPDPBSUDZrr:
2352 case VPDPBSUDZrrk:
2353 case VPDPBSUDZrrkz:
2354 case VPDPBSUDrm:
2355 case VPDPBSUDrr:
2356 return true;
2357 }
2358 return false;
2359}
2360
2361bool isPMOVSXWQ(unsigned Opcode) {
2362 switch (Opcode) {
2363 case PMOVSXWQrm:
2364 case PMOVSXWQrr:
2365 return true;
2366 }
2367 return false;
2368}
2369
2370bool isPSRLW(unsigned Opcode) {
2371 switch (Opcode) {
2372 case MMX_PSRLWri:
2373 case MMX_PSRLWrm:
2374 case MMX_PSRLWrr:
2375 case PSRLWri:
2376 case PSRLWrm:
2377 case PSRLWrr:
2378 return true;
2379 }
2380 return false;
2381}
2382
2383bool isMOVNTDQA(unsigned Opcode) {
2384 return Opcode == MOVNTDQArm;
2385}
2386
2387bool isFUCOMPI(unsigned Opcode) {
2388 return Opcode == UCOM_FIPr;
2389}
2390
2391bool isANDNPS(unsigned Opcode) {
2392 switch (Opcode) {
2393 case ANDNPSrm:
2394 case ANDNPSrr:
2395 return true;
2396 }
2397 return false;
2398}
2399
2400bool isVINSERTF64X2(unsigned Opcode) {
2401 switch (Opcode) {
2402 case VINSERTF64X2Z256rmi:
2403 case VINSERTF64X2Z256rmik:
2404 case VINSERTF64X2Z256rmikz:
2405 case VINSERTF64X2Z256rri:
2406 case VINSERTF64X2Z256rrik:
2407 case VINSERTF64X2Z256rrikz:
2408 case VINSERTF64X2Zrmi:
2409 case VINSERTF64X2Zrmik:
2410 case VINSERTF64X2Zrmikz:
2411 case VINSERTF64X2Zrri:
2412 case VINSERTF64X2Zrrik:
2413 case VINSERTF64X2Zrrikz:
2414 return true;
2415 }
2416 return false;
2417}
2418
2419bool isCLTS(unsigned Opcode) {
2420 return Opcode == CLTS;
2421}
2422
2423bool isSETSSBSY(unsigned Opcode) {
2424 return Opcode == SETSSBSY;
2425}
2426
2427bool isVMULPD(unsigned Opcode) {
2428 switch (Opcode) {
2429 case VMULPDYrm:
2430 case VMULPDYrr:
2431 case VMULPDZ128rm:
2432 case VMULPDZ128rmb:
2433 case VMULPDZ128rmbk:
2434 case VMULPDZ128rmbkz:
2435 case VMULPDZ128rmk:
2436 case VMULPDZ128rmkz:
2437 case VMULPDZ128rr:
2438 case VMULPDZ128rrk:
2439 case VMULPDZ128rrkz:
2440 case VMULPDZ256rm:
2441 case VMULPDZ256rmb:
2442 case VMULPDZ256rmbk:
2443 case VMULPDZ256rmbkz:
2444 case VMULPDZ256rmk:
2445 case VMULPDZ256rmkz:
2446 case VMULPDZ256rr:
2447 case VMULPDZ256rrk:
2448 case VMULPDZ256rrkz:
2449 case VMULPDZrm:
2450 case VMULPDZrmb:
2451 case VMULPDZrmbk:
2452 case VMULPDZrmbkz:
2453 case VMULPDZrmk:
2454 case VMULPDZrmkz:
2455 case VMULPDZrr:
2456 case VMULPDZrrb:
2457 case VMULPDZrrbk:
2458 case VMULPDZrrbkz:
2459 case VMULPDZrrk:
2460 case VMULPDZrrkz:
2461 case VMULPDrm:
2462 case VMULPDrr:
2463 return true;
2464 }
2465 return false;
2466}
2467
2468bool isVFMADDSUB132PS(unsigned Opcode) {
2469 switch (Opcode) {
2470 case VFMADDSUB132PSYm:
2471 case VFMADDSUB132PSYr:
2472 case VFMADDSUB132PSZ128m:
2473 case VFMADDSUB132PSZ128mb:
2474 case VFMADDSUB132PSZ128mbk:
2475 case VFMADDSUB132PSZ128mbkz:
2476 case VFMADDSUB132PSZ128mk:
2477 case VFMADDSUB132PSZ128mkz:
2478 case VFMADDSUB132PSZ128r:
2479 case VFMADDSUB132PSZ128rk:
2480 case VFMADDSUB132PSZ128rkz:
2481 case VFMADDSUB132PSZ256m:
2482 case VFMADDSUB132PSZ256mb:
2483 case VFMADDSUB132PSZ256mbk:
2484 case VFMADDSUB132PSZ256mbkz:
2485 case VFMADDSUB132PSZ256mk:
2486 case VFMADDSUB132PSZ256mkz:
2487 case VFMADDSUB132PSZ256r:
2488 case VFMADDSUB132PSZ256rk:
2489 case VFMADDSUB132PSZ256rkz:
2490 case VFMADDSUB132PSZm:
2491 case VFMADDSUB132PSZmb:
2492 case VFMADDSUB132PSZmbk:
2493 case VFMADDSUB132PSZmbkz:
2494 case VFMADDSUB132PSZmk:
2495 case VFMADDSUB132PSZmkz:
2496 case VFMADDSUB132PSZr:
2497 case VFMADDSUB132PSZrb:
2498 case VFMADDSUB132PSZrbk:
2499 case VFMADDSUB132PSZrbkz:
2500 case VFMADDSUB132PSZrk:
2501 case VFMADDSUB132PSZrkz:
2502 case VFMADDSUB132PSm:
2503 case VFMADDSUB132PSr:
2504 return true;
2505 }
2506 return false;
2507}
2508
2509bool isVPMADCSWD(unsigned Opcode) {
2510 switch (Opcode) {
2511 case VPMADCSWDrm:
2512 case VPMADCSWDrr:
2513 return true;
2514 }
2515 return false;
2516}
2517
2518bool isVSCATTERPF0DPS(unsigned Opcode) {
2519 return Opcode == VSCATTERPF0DPSm;
2520}
2521
2522bool isXCHG(unsigned Opcode) {
2523 switch (Opcode) {
2524 case XCHG16ar:
2525 case XCHG16rm:
2526 case XCHG16rr:
2527 case XCHG32ar:
2528 case XCHG32rm:
2529 case XCHG32rr:
2530 case XCHG64ar:
2531 case XCHG64rm:
2532 case XCHG64rr:
2533 case XCHG8rm:
2534 case XCHG8rr:
2535 return true;
2536 }
2537 return false;
2538}
2539
2540bool isVGATHERPF1QPS(unsigned Opcode) {
2541 return Opcode == VGATHERPF1QPSm;
2542}
2543
2544bool isVCVTNEPS2BF16(unsigned Opcode) {
2545 switch (Opcode) {
2546 case VCVTNEPS2BF16Yrm:
2547 case VCVTNEPS2BF16Yrr:
2548 case VCVTNEPS2BF16Z128rm:
2549 case VCVTNEPS2BF16Z128rmb:
2550 case VCVTNEPS2BF16Z128rmbk:
2551 case VCVTNEPS2BF16Z128rmbkz:
2552 case VCVTNEPS2BF16Z128rmk:
2553 case VCVTNEPS2BF16Z128rmkz:
2554 case VCVTNEPS2BF16Z128rr:
2555 case VCVTNEPS2BF16Z128rrk:
2556 case VCVTNEPS2BF16Z128rrkz:
2557 case VCVTNEPS2BF16Z256rm:
2558 case VCVTNEPS2BF16Z256rmb:
2559 case VCVTNEPS2BF16Z256rmbk:
2560 case VCVTNEPS2BF16Z256rmbkz:
2561 case VCVTNEPS2BF16Z256rmk:
2562 case VCVTNEPS2BF16Z256rmkz:
2563 case VCVTNEPS2BF16Z256rr:
2564 case VCVTNEPS2BF16Z256rrk:
2565 case VCVTNEPS2BF16Z256rrkz:
2566 case VCVTNEPS2BF16Zrm:
2567 case VCVTNEPS2BF16Zrmb:
2568 case VCVTNEPS2BF16Zrmbk:
2569 case VCVTNEPS2BF16Zrmbkz:
2570 case VCVTNEPS2BF16Zrmk:
2571 case VCVTNEPS2BF16Zrmkz:
2572 case VCVTNEPS2BF16Zrr:
2573 case VCVTNEPS2BF16Zrrk:
2574 case VCVTNEPS2BF16Zrrkz:
2575 case VCVTNEPS2BF16rm:
2576 case VCVTNEPS2BF16rr:
2577 return true;
2578 }
2579 return false;
2580}
2581
2582bool isVFMADDSS(unsigned Opcode) {
2583 switch (Opcode) {
2584 case VFMADDSS4mr:
2585 case VFMADDSS4rm:
2586 case VFMADDSS4rr:
2587 case VFMADDSS4rr_REV:
2588 return true;
2589 }
2590 return false;
2591}
2592
2593bool isINTO(unsigned Opcode) {
2594 return Opcode == INTO;
2595}
2596
2597bool isANDPD(unsigned Opcode) {
2598 switch (Opcode) {
2599 case ANDPDrm:
2600 case ANDPDrr:
2601 return true;
2602 }
2603 return false;
2604}
2605
2606bool isSEAMCALL(unsigned Opcode) {
2607 return Opcode == SEAMCALL;
2608}
2609
2610bool isVPDPBSSDS(unsigned Opcode) {
2611 switch (Opcode) {
2612 case VPDPBSSDSYrm:
2613 case VPDPBSSDSYrr:
2614 case VPDPBSSDSZ128rm:
2615 case VPDPBSSDSZ128rmb:
2616 case VPDPBSSDSZ128rmbk:
2617 case VPDPBSSDSZ128rmbkz:
2618 case VPDPBSSDSZ128rmk:
2619 case VPDPBSSDSZ128rmkz:
2620 case VPDPBSSDSZ128rr:
2621 case VPDPBSSDSZ128rrk:
2622 case VPDPBSSDSZ128rrkz:
2623 case VPDPBSSDSZ256rm:
2624 case VPDPBSSDSZ256rmb:
2625 case VPDPBSSDSZ256rmbk:
2626 case VPDPBSSDSZ256rmbkz:
2627 case VPDPBSSDSZ256rmk:
2628 case VPDPBSSDSZ256rmkz:
2629 case VPDPBSSDSZ256rr:
2630 case VPDPBSSDSZ256rrk:
2631 case VPDPBSSDSZ256rrkz:
2632 case VPDPBSSDSZrm:
2633 case VPDPBSSDSZrmb:
2634 case VPDPBSSDSZrmbk:
2635 case VPDPBSSDSZrmbkz:
2636 case VPDPBSSDSZrmk:
2637 case VPDPBSSDSZrmkz:
2638 case VPDPBSSDSZrr:
2639 case VPDPBSSDSZrrk:
2640 case VPDPBSSDSZrrkz:
2641 case VPDPBSSDSrm:
2642 case VPDPBSSDSrr:
2643 return true;
2644 }
2645 return false;
2646}
2647
2648bool isUNPCKHPS(unsigned Opcode) {
2649 switch (Opcode) {
2650 case UNPCKHPSrm:
2651 case UNPCKHPSrr:
2652 return true;
2653 }
2654 return false;
2655}
2656
2657bool isSETZUCC(unsigned Opcode) {
2658 switch (Opcode) {
2659 case SETZUCCm:
2660 case SETZUCCr:
2661 return true;
2662 }
2663 return false;
2664}
2665
2666bool isSHUFPD(unsigned Opcode) {
2667 switch (Opcode) {
2668 case SHUFPDrmi:
2669 case SHUFPDrri:
2670 return true;
2671 }
2672 return false;
2673}
2674
2675bool isFCMOVNB(unsigned Opcode) {
2676 return Opcode == CMOVNB_F;
2677}
2678
2679bool isCVTTSS2SI(unsigned Opcode) {
2680 switch (Opcode) {
2681 case CVTTSS2SI64rm_Int:
2682 case CVTTSS2SI64rr_Int:
2683 case CVTTSS2SIrm_Int:
2684 case CVTTSS2SIrr_Int:
2685 return true;
2686 }
2687 return false;
2688}
2689
2690bool isEXTRQ(unsigned Opcode) {
2691 switch (Opcode) {
2692 case EXTRQ:
2693 case EXTRQI:
2694 return true;
2695 }
2696 return false;
2697}
2698
2699bool isSHLD(unsigned Opcode) {
2700 switch (Opcode) {
2701 case SHLD16mrCL:
2702 case SHLD16mrCL_EVEX:
2703 case SHLD16mrCL_ND:
2704 case SHLD16mrCL_NF:
2705 case SHLD16mrCL_NF_ND:
2706 case SHLD16mri8:
2707 case SHLD16mri8_EVEX:
2708 case SHLD16mri8_ND:
2709 case SHLD16mri8_NF:
2710 case SHLD16mri8_NF_ND:
2711 case SHLD16rrCL:
2712 case SHLD16rrCL_EVEX:
2713 case SHLD16rrCL_ND:
2714 case SHLD16rrCL_NF:
2715 case SHLD16rrCL_NF_ND:
2716 case SHLD16rri8:
2717 case SHLD16rri8_EVEX:
2718 case SHLD16rri8_ND:
2719 case SHLD16rri8_NF:
2720 case SHLD16rri8_NF_ND:
2721 case SHLD32mrCL:
2722 case SHLD32mrCL_EVEX:
2723 case SHLD32mrCL_ND:
2724 case SHLD32mrCL_NF:
2725 case SHLD32mrCL_NF_ND:
2726 case SHLD32mri8:
2727 case SHLD32mri8_EVEX:
2728 case SHLD32mri8_ND:
2729 case SHLD32mri8_NF:
2730 case SHLD32mri8_NF_ND:
2731 case SHLD32rrCL:
2732 case SHLD32rrCL_EVEX:
2733 case SHLD32rrCL_ND:
2734 case SHLD32rrCL_NF:
2735 case SHLD32rrCL_NF_ND:
2736 case SHLD32rri8:
2737 case SHLD32rri8_EVEX:
2738 case SHLD32rri8_ND:
2739 case SHLD32rri8_NF:
2740 case SHLD32rri8_NF_ND:
2741 case SHLD64mrCL:
2742 case SHLD64mrCL_EVEX:
2743 case SHLD64mrCL_ND:
2744 case SHLD64mrCL_NF:
2745 case SHLD64mrCL_NF_ND:
2746 case SHLD64mri8:
2747 case SHLD64mri8_EVEX:
2748 case SHLD64mri8_ND:
2749 case SHLD64mri8_NF:
2750 case SHLD64mri8_NF_ND:
2751 case SHLD64rrCL:
2752 case SHLD64rrCL_EVEX:
2753 case SHLD64rrCL_ND:
2754 case SHLD64rrCL_NF:
2755 case SHLD64rrCL_NF_ND:
2756 case SHLD64rri8:
2757 case SHLD64rri8_EVEX:
2758 case SHLD64rri8_ND:
2759 case SHLD64rri8_NF:
2760 case SHLD64rri8_NF_ND:
2761 return true;
2762 }
2763 return false;
2764}
2765
2766bool isVBROADCASTSS(unsigned Opcode) {
2767 switch (Opcode) {
2768 case VBROADCASTSSYrm:
2769 case VBROADCASTSSYrr:
2770 case VBROADCASTSSZ128rm:
2771 case VBROADCASTSSZ128rmk:
2772 case VBROADCASTSSZ128rmkz:
2773 case VBROADCASTSSZ128rr:
2774 case VBROADCASTSSZ128rrk:
2775 case VBROADCASTSSZ128rrkz:
2776 case VBROADCASTSSZ256rm:
2777 case VBROADCASTSSZ256rmk:
2778 case VBROADCASTSSZ256rmkz:
2779 case VBROADCASTSSZ256rr:
2780 case VBROADCASTSSZ256rrk:
2781 case VBROADCASTSSZ256rrkz:
2782 case VBROADCASTSSZrm:
2783 case VBROADCASTSSZrmk:
2784 case VBROADCASTSSZrmkz:
2785 case VBROADCASTSSZrr:
2786 case VBROADCASTSSZrrk:
2787 case VBROADCASTSSZrrkz:
2788 case VBROADCASTSSrm:
2789 case VBROADCASTSSrr:
2790 return true;
2791 }
2792 return false;
2793}
2794
2795bool isCLUI(unsigned Opcode) {
2796 return Opcode == CLUI;
2797}
2798
2799bool isVINSERTI128(unsigned Opcode) {
2800 switch (Opcode) {
2801 case VINSERTI128rmi:
2802 case VINSERTI128rri:
2803 return true;
2804 }
2805 return false;
2806}
2807
2808bool isVBLENDPD(unsigned Opcode) {
2809 switch (Opcode) {
2810 case VBLENDPDYrmi:
2811 case VBLENDPDYrri:
2812 case VBLENDPDrmi:
2813 case VBLENDPDrri:
2814 return true;
2815 }
2816 return false;
2817}
2818
2819bool isVPSHLDW(unsigned Opcode) {
2820 switch (Opcode) {
2821 case VPSHLDWZ128rmi:
2822 case VPSHLDWZ128rmik:
2823 case VPSHLDWZ128rmikz:
2824 case VPSHLDWZ128rri:
2825 case VPSHLDWZ128rrik:
2826 case VPSHLDWZ128rrikz:
2827 case VPSHLDWZ256rmi:
2828 case VPSHLDWZ256rmik:
2829 case VPSHLDWZ256rmikz:
2830 case VPSHLDWZ256rri:
2831 case VPSHLDWZ256rrik:
2832 case VPSHLDWZ256rrikz:
2833 case VPSHLDWZrmi:
2834 case VPSHLDWZrmik:
2835 case VPSHLDWZrmikz:
2836 case VPSHLDWZrri:
2837 case VPSHLDWZrrik:
2838 case VPSHLDWZrrikz:
2839 return true;
2840 }
2841 return false;
2842}
2843
2844bool isVCVTNEEPH2PS(unsigned Opcode) {
2845 switch (Opcode) {
2846 case VCVTNEEPH2PSYrm:
2847 case VCVTNEEPH2PSrm:
2848 return true;
2849 }
2850 return false;
2851}
2852
2853bool isVCVTTSD2SI(unsigned Opcode) {
2854 switch (Opcode) {
2855 case VCVTTSD2SI64Zrm_Int:
2856 case VCVTTSD2SI64Zrr_Int:
2857 case VCVTTSD2SI64Zrrb_Int:
2858 case VCVTTSD2SI64rm_Int:
2859 case VCVTTSD2SI64rr_Int:
2860 case VCVTTSD2SIZrm_Int:
2861 case VCVTTSD2SIZrr_Int:
2862 case VCVTTSD2SIZrrb_Int:
2863 case VCVTTSD2SIrm_Int:
2864 case VCVTTSD2SIrr_Int:
2865 return true;
2866 }
2867 return false;
2868}
2869
2870bool isVSM4KEY4(unsigned Opcode) {
2871 switch (Opcode) {
2872 case VSM4KEY4Yrm:
2873 case VSM4KEY4Yrr:
2874 case VSM4KEY4Z128rm:
2875 case VSM4KEY4Z128rr:
2876 case VSM4KEY4Z256rm:
2877 case VSM4KEY4Z256rr:
2878 case VSM4KEY4Zrm:
2879 case VSM4KEY4Zrr:
2880 case VSM4KEY4rm:
2881 case VSM4KEY4rr:
2882 return true;
2883 }
2884 return false;
2885}
2886
2887bool isWRMSRNS(unsigned Opcode) {
2888 switch (Opcode) {
2889 case WRMSRNS:
2890 case WRMSRNSir:
2891 case WRMSRNSir_EVEX:
2892 return true;
2893 }
2894 return false;
2895}
2896
2897bool isCMPSB(unsigned Opcode) {
2898 return Opcode == CMPSB;
2899}
2900
2901bool isVRCPBF16(unsigned Opcode) {
2902 switch (Opcode) {
2903 case VRCPBF16Z128m:
2904 case VRCPBF16Z128mb:
2905 case VRCPBF16Z128mbk:
2906 case VRCPBF16Z128mbkz:
2907 case VRCPBF16Z128mk:
2908 case VRCPBF16Z128mkz:
2909 case VRCPBF16Z128r:
2910 case VRCPBF16Z128rk:
2911 case VRCPBF16Z128rkz:
2912 case VRCPBF16Z256m:
2913 case VRCPBF16Z256mb:
2914 case VRCPBF16Z256mbk:
2915 case VRCPBF16Z256mbkz:
2916 case VRCPBF16Z256mk:
2917 case VRCPBF16Z256mkz:
2918 case VRCPBF16Z256r:
2919 case VRCPBF16Z256rk:
2920 case VRCPBF16Z256rkz:
2921 case VRCPBF16Zm:
2922 case VRCPBF16Zmb:
2923 case VRCPBF16Zmbk:
2924 case VRCPBF16Zmbkz:
2925 case VRCPBF16Zmk:
2926 case VRCPBF16Zmkz:
2927 case VRCPBF16Zr:
2928 case VRCPBF16Zrk:
2929 case VRCPBF16Zrkz:
2930 return true;
2931 }
2932 return false;
2933}
2934
2935bool isMULSS(unsigned Opcode) {
2936 switch (Opcode) {
2937 case MULSSrm_Int:
2938 case MULSSrr_Int:
2939 return true;
2940 }
2941 return false;
2942}
2943
2944bool isVMRUN(unsigned Opcode) {
2945 switch (Opcode) {
2946 case VMRUN32:
2947 case VMRUN64:
2948 return true;
2949 }
2950 return false;
2951}
2952
2953bool isVPSRLVD(unsigned Opcode) {
2954 switch (Opcode) {
2955 case VPSRLVDYrm:
2956 case VPSRLVDYrr:
2957 case VPSRLVDZ128rm:
2958 case VPSRLVDZ128rmb:
2959 case VPSRLVDZ128rmbk:
2960 case VPSRLVDZ128rmbkz:
2961 case VPSRLVDZ128rmk:
2962 case VPSRLVDZ128rmkz:
2963 case VPSRLVDZ128rr:
2964 case VPSRLVDZ128rrk:
2965 case VPSRLVDZ128rrkz:
2966 case VPSRLVDZ256rm:
2967 case VPSRLVDZ256rmb:
2968 case VPSRLVDZ256rmbk:
2969 case VPSRLVDZ256rmbkz:
2970 case VPSRLVDZ256rmk:
2971 case VPSRLVDZ256rmkz:
2972 case VPSRLVDZ256rr:
2973 case VPSRLVDZ256rrk:
2974 case VPSRLVDZ256rrkz:
2975 case VPSRLVDZrm:
2976 case VPSRLVDZrmb:
2977 case VPSRLVDZrmbk:
2978 case VPSRLVDZrmbkz:
2979 case VPSRLVDZrmk:
2980 case VPSRLVDZrmkz:
2981 case VPSRLVDZrr:
2982 case VPSRLVDZrrk:
2983 case VPSRLVDZrrkz:
2984 case VPSRLVDrm:
2985 case VPSRLVDrr:
2986 return true;
2987 }
2988 return false;
2989}
2990
2991bool isLEAVE(unsigned Opcode) {
2992 switch (Opcode) {
2993 case LEAVE:
2994 case LEAVE64:
2995 return true;
2996 }
2997 return false;
2998}
2999
3000bool isVGETMANTPS(unsigned Opcode) {
3001 switch (Opcode) {
3002 case VGETMANTPSZ128rmbi:
3003 case VGETMANTPSZ128rmbik:
3004 case VGETMANTPSZ128rmbikz:
3005 case VGETMANTPSZ128rmi:
3006 case VGETMANTPSZ128rmik:
3007 case VGETMANTPSZ128rmikz:
3008 case VGETMANTPSZ128rri:
3009 case VGETMANTPSZ128rrik:
3010 case VGETMANTPSZ128rrikz:
3011 case VGETMANTPSZ256rmbi:
3012 case VGETMANTPSZ256rmbik:
3013 case VGETMANTPSZ256rmbikz:
3014 case VGETMANTPSZ256rmi:
3015 case VGETMANTPSZ256rmik:
3016 case VGETMANTPSZ256rmikz:
3017 case VGETMANTPSZ256rri:
3018 case VGETMANTPSZ256rrik:
3019 case VGETMANTPSZ256rrikz:
3020 case VGETMANTPSZrmbi:
3021 case VGETMANTPSZrmbik:
3022 case VGETMANTPSZrmbikz:
3023 case VGETMANTPSZrmi:
3024 case VGETMANTPSZrmik:
3025 case VGETMANTPSZrmikz:
3026 case VGETMANTPSZrri:
3027 case VGETMANTPSZrrib:
3028 case VGETMANTPSZrribk:
3029 case VGETMANTPSZrribkz:
3030 case VGETMANTPSZrrik:
3031 case VGETMANTPSZrrikz:
3032 return true;
3033 }
3034 return false;
3035}
3036
3037bool isXSHA256(unsigned Opcode) {
3038 return Opcode == XSHA256;
3039}
3040
3041bool isBOUND(unsigned Opcode) {
3042 switch (Opcode) {
3043 case BOUNDS16rm:
3044 case BOUNDS32rm:
3045 return true;
3046 }
3047 return false;
3048}
3049
3050bool isSFENCE(unsigned Opcode) {
3051 return Opcode == SFENCE;
3052}
3053
3054bool isVPHADDD(unsigned Opcode) {
3055 switch (Opcode) {
3056 case VPHADDDYrm:
3057 case VPHADDDYrr:
3058 case VPHADDDrm:
3059 case VPHADDDrr:
3060 return true;
3061 }
3062 return false;
3063}
3064
3065bool isADOX(unsigned Opcode) {
3066 switch (Opcode) {
3067 case ADOX32rm:
3068 case ADOX32rm_EVEX:
3069 case ADOX32rm_ND:
3070 case ADOX32rr:
3071 case ADOX32rr_EVEX:
3072 case ADOX32rr_ND:
3073 case ADOX64rm:
3074 case ADOX64rm_EVEX:
3075 case ADOX64rm_ND:
3076 case ADOX64rr:
3077 case ADOX64rr_EVEX:
3078 case ADOX64rr_ND:
3079 return true;
3080 }
3081 return false;
3082}
3083
3084bool isVPSLLQ(unsigned Opcode) {
3085 switch (Opcode) {
3086 case VPSLLQYri:
3087 case VPSLLQYrm:
3088 case VPSLLQYrr:
3089 case VPSLLQZ128mbi:
3090 case VPSLLQZ128mbik:
3091 case VPSLLQZ128mbikz:
3092 case VPSLLQZ128mi:
3093 case VPSLLQZ128mik:
3094 case VPSLLQZ128mikz:
3095 case VPSLLQZ128ri:
3096 case VPSLLQZ128rik:
3097 case VPSLLQZ128rikz:
3098 case VPSLLQZ128rm:
3099 case VPSLLQZ128rmk:
3100 case VPSLLQZ128rmkz:
3101 case VPSLLQZ128rr:
3102 case VPSLLQZ128rrk:
3103 case VPSLLQZ128rrkz:
3104 case VPSLLQZ256mbi:
3105 case VPSLLQZ256mbik:
3106 case VPSLLQZ256mbikz:
3107 case VPSLLQZ256mi:
3108 case VPSLLQZ256mik:
3109 case VPSLLQZ256mikz:
3110 case VPSLLQZ256ri:
3111 case VPSLLQZ256rik:
3112 case VPSLLQZ256rikz:
3113 case VPSLLQZ256rm:
3114 case VPSLLQZ256rmk:
3115 case VPSLLQZ256rmkz:
3116 case VPSLLQZ256rr:
3117 case VPSLLQZ256rrk:
3118 case VPSLLQZ256rrkz:
3119 case VPSLLQZmbi:
3120 case VPSLLQZmbik:
3121 case VPSLLQZmbikz:
3122 case VPSLLQZmi:
3123 case VPSLLQZmik:
3124 case VPSLLQZmikz:
3125 case VPSLLQZri:
3126 case VPSLLQZrik:
3127 case VPSLLQZrikz:
3128 case VPSLLQZrm:
3129 case VPSLLQZrmk:
3130 case VPSLLQZrmkz:
3131 case VPSLLQZrr:
3132 case VPSLLQZrrk:
3133 case VPSLLQZrrkz:
3134 case VPSLLQri:
3135 case VPSLLQrm:
3136 case VPSLLQrr:
3137 return true;
3138 }
3139 return false;
3140}
3141
3142bool isVCVTPH2HF8(unsigned Opcode) {
3143 switch (Opcode) {
3144 case VCVTPH2HF8Z128rm:
3145 case VCVTPH2HF8Z128rmb:
3146 case VCVTPH2HF8Z128rmbk:
3147 case VCVTPH2HF8Z128rmbkz:
3148 case VCVTPH2HF8Z128rmk:
3149 case VCVTPH2HF8Z128rmkz:
3150 case VCVTPH2HF8Z128rr:
3151 case VCVTPH2HF8Z128rrk:
3152 case VCVTPH2HF8Z128rrkz:
3153 case VCVTPH2HF8Z256rm:
3154 case VCVTPH2HF8Z256rmb:
3155 case VCVTPH2HF8Z256rmbk:
3156 case VCVTPH2HF8Z256rmbkz:
3157 case VCVTPH2HF8Z256rmk:
3158 case VCVTPH2HF8Z256rmkz:
3159 case VCVTPH2HF8Z256rr:
3160 case VCVTPH2HF8Z256rrk:
3161 case VCVTPH2HF8Z256rrkz:
3162 case VCVTPH2HF8Zrm:
3163 case VCVTPH2HF8Zrmb:
3164 case VCVTPH2HF8Zrmbk:
3165 case VCVTPH2HF8Zrmbkz:
3166 case VCVTPH2HF8Zrmk:
3167 case VCVTPH2HF8Zrmkz:
3168 case VCVTPH2HF8Zrr:
3169 case VCVTPH2HF8Zrrk:
3170 case VCVTPH2HF8Zrrkz:
3171 return true;
3172 }
3173 return false;
3174}
3175
3176bool isPFRSQIT1(unsigned Opcode) {
3177 switch (Opcode) {
3178 case PFRSQIT1rm:
3179 case PFRSQIT1rr:
3180 return true;
3181 }
3182 return false;
3183}
3184
3185bool isCLAC(unsigned Opcode) {
3186 return Opcode == CLAC;
3187}
3188
3189bool isKNOTW(unsigned Opcode) {
3190 return Opcode == KNOTWkk;
3191}
3192
3193bool isVCVTPH2PD(unsigned Opcode) {
3194 switch (Opcode) {
3195 case VCVTPH2PDZ128rm:
3196 case VCVTPH2PDZ128rmb:
3197 case VCVTPH2PDZ128rmbk:
3198 case VCVTPH2PDZ128rmbkz:
3199 case VCVTPH2PDZ128rmk:
3200 case VCVTPH2PDZ128rmkz:
3201 case VCVTPH2PDZ128rr:
3202 case VCVTPH2PDZ128rrk:
3203 case VCVTPH2PDZ128rrkz:
3204 case VCVTPH2PDZ256rm:
3205 case VCVTPH2PDZ256rmb:
3206 case VCVTPH2PDZ256rmbk:
3207 case VCVTPH2PDZ256rmbkz:
3208 case VCVTPH2PDZ256rmk:
3209 case VCVTPH2PDZ256rmkz:
3210 case VCVTPH2PDZ256rr:
3211 case VCVTPH2PDZ256rrk:
3212 case VCVTPH2PDZ256rrkz:
3213 case VCVTPH2PDZrm:
3214 case VCVTPH2PDZrmb:
3215 case VCVTPH2PDZrmbk:
3216 case VCVTPH2PDZrmbkz:
3217 case VCVTPH2PDZrmk:
3218 case VCVTPH2PDZrmkz:
3219 case VCVTPH2PDZrr:
3220 case VCVTPH2PDZrrb:
3221 case VCVTPH2PDZrrbk:
3222 case VCVTPH2PDZrrbkz:
3223 case VCVTPH2PDZrrk:
3224 case VCVTPH2PDZrrkz:
3225 return true;
3226 }
3227 return false;
3228}
3229
3230bool isVAESENC(unsigned Opcode) {
3231 switch (Opcode) {
3232 case VAESENCYrm:
3233 case VAESENCYrr:
3234 case VAESENCZ128rm:
3235 case VAESENCZ128rr:
3236 case VAESENCZ256rm:
3237 case VAESENCZ256rr:
3238 case VAESENCZrm:
3239 case VAESENCZrr:
3240 case VAESENCrm:
3241 case VAESENCrr:
3242 return true;
3243 }
3244 return false;
3245}
3246
3247bool isMOVNTI(unsigned Opcode) {
3248 switch (Opcode) {
3249 case MOVNTI_64mr:
3250 case MOVNTImr:
3251 return true;
3252 }
3253 return false;
3254}
3255
3256bool isFXCH(unsigned Opcode) {
3257 return Opcode == XCH_F;
3258}
3259
3260bool isPOPP(unsigned Opcode) {
3261 return Opcode == POPP64r;
3262}
3263
3264bool isVPBLENDMD(unsigned Opcode) {
3265 switch (Opcode) {
3266 case VPBLENDMDZ128rm:
3267 case VPBLENDMDZ128rmb:
3268 case VPBLENDMDZ128rmbk:
3269 case VPBLENDMDZ128rmbkz:
3270 case VPBLENDMDZ128rmk:
3271 case VPBLENDMDZ128rmkz:
3272 case VPBLENDMDZ128rr:
3273 case VPBLENDMDZ128rrk:
3274 case VPBLENDMDZ128rrkz:
3275 case VPBLENDMDZ256rm:
3276 case VPBLENDMDZ256rmb:
3277 case VPBLENDMDZ256rmbk:
3278 case VPBLENDMDZ256rmbkz:
3279 case VPBLENDMDZ256rmk:
3280 case VPBLENDMDZ256rmkz:
3281 case VPBLENDMDZ256rr:
3282 case VPBLENDMDZ256rrk:
3283 case VPBLENDMDZ256rrkz:
3284 case VPBLENDMDZrm:
3285 case VPBLENDMDZrmb:
3286 case VPBLENDMDZrmbk:
3287 case VPBLENDMDZrmbkz:
3288 case VPBLENDMDZrmk:
3289 case VPBLENDMDZrmkz:
3290 case VPBLENDMDZrr:
3291 case VPBLENDMDZrrk:
3292 case VPBLENDMDZrrkz:
3293 return true;
3294 }
3295 return false;
3296}
3297
3298bool isFSINCOS(unsigned Opcode) {
3299 return Opcode == FSINCOS;
3300}
3301
3302bool isVPMULLW(unsigned Opcode) {
3303 switch (Opcode) {
3304 case VPMULLWYrm:
3305 case VPMULLWYrr:
3306 case VPMULLWZ128rm:
3307 case VPMULLWZ128rmk:
3308 case VPMULLWZ128rmkz:
3309 case VPMULLWZ128rr:
3310 case VPMULLWZ128rrk:
3311 case VPMULLWZ128rrkz:
3312 case VPMULLWZ256rm:
3313 case VPMULLWZ256rmk:
3314 case VPMULLWZ256rmkz:
3315 case VPMULLWZ256rr:
3316 case VPMULLWZ256rrk:
3317 case VPMULLWZ256rrkz:
3318 case VPMULLWZrm:
3319 case VPMULLWZrmk:
3320 case VPMULLWZrmkz:
3321 case VPMULLWZrr:
3322 case VPMULLWZrrk:
3323 case VPMULLWZrrkz:
3324 case VPMULLWrm:
3325 case VPMULLWrr:
3326 return true;
3327 }
3328 return false;
3329}
3330
3331bool isVPMOVSXBW(unsigned Opcode) {
3332 switch (Opcode) {
3333 case VPMOVSXBWYrm:
3334 case VPMOVSXBWYrr:
3335 case VPMOVSXBWZ128rm:
3336 case VPMOVSXBWZ128rmk:
3337 case VPMOVSXBWZ128rmkz:
3338 case VPMOVSXBWZ128rr:
3339 case VPMOVSXBWZ128rrk:
3340 case VPMOVSXBWZ128rrkz:
3341 case VPMOVSXBWZ256rm:
3342 case VPMOVSXBWZ256rmk:
3343 case VPMOVSXBWZ256rmkz:
3344 case VPMOVSXBWZ256rr:
3345 case VPMOVSXBWZ256rrk:
3346 case VPMOVSXBWZ256rrkz:
3347 case VPMOVSXBWZrm:
3348 case VPMOVSXBWZrmk:
3349 case VPMOVSXBWZrmkz:
3350 case VPMOVSXBWZrr:
3351 case VPMOVSXBWZrrk:
3352 case VPMOVSXBWZrrkz:
3353 case VPMOVSXBWrm:
3354 case VPMOVSXBWrr:
3355 return true;
3356 }
3357 return false;
3358}
3359
3360bool isSTC(unsigned Opcode) {
3361 return Opcode == STC;
3362}
3363
3364bool isVPINSRB(unsigned Opcode) {
3365 switch (Opcode) {
3366 case VPINSRBZrmi:
3367 case VPINSRBZrri:
3368 case VPINSRBrmi:
3369 case VPINSRBrri:
3370 return true;
3371 }
3372 return false;
3373}
3374
3375bool isLWPVAL(unsigned Opcode) {
3376 switch (Opcode) {
3377 case LWPVAL32rmi:
3378 case LWPVAL32rri:
3379 case LWPVAL64rmi:
3380 case LWPVAL64rri:
3381 return true;
3382 }
3383 return false;
3384}
3385
3386bool isKXORB(unsigned Opcode) {
3387 return Opcode == KXORBkk;
3388}
3389
3390bool isRSTORSSP(unsigned Opcode) {
3391 return Opcode == RSTORSSP;
3392}
3393
3394bool isVPRORQ(unsigned Opcode) {
3395 switch (Opcode) {
3396 case VPRORQZ128mbi:
3397 case VPRORQZ128mbik:
3398 case VPRORQZ128mbikz:
3399 case VPRORQZ128mi:
3400 case VPRORQZ128mik:
3401 case VPRORQZ128mikz:
3402 case VPRORQZ128ri:
3403 case VPRORQZ128rik:
3404 case VPRORQZ128rikz:
3405 case VPRORQZ256mbi:
3406 case VPRORQZ256mbik:
3407 case VPRORQZ256mbikz:
3408 case VPRORQZ256mi:
3409 case VPRORQZ256mik:
3410 case VPRORQZ256mikz:
3411 case VPRORQZ256ri:
3412 case VPRORQZ256rik:
3413 case VPRORQZ256rikz:
3414 case VPRORQZmbi:
3415 case VPRORQZmbik:
3416 case VPRORQZmbikz:
3417 case VPRORQZmi:
3418 case VPRORQZmik:
3419 case VPRORQZmikz:
3420 case VPRORQZri:
3421 case VPRORQZrik:
3422 case VPRORQZrikz:
3423 return true;
3424 }
3425 return false;
3426}
3427
3428bool isVSM3MSG1(unsigned Opcode) {
3429 switch (Opcode) {
3430 case VSM3MSG1rm:
3431 case VSM3MSG1rr:
3432 return true;
3433 }
3434 return false;
3435}
3436
3437bool isFICOM(unsigned Opcode) {
3438 switch (Opcode) {
3439 case FICOM16m:
3440 case FICOM32m:
3441 return true;
3442 }
3443 return false;
3444}
3445
3446bool isMAXPS(unsigned Opcode) {
3447 switch (Opcode) {
3448 case MAXPSrm:
3449 case MAXPSrr:
3450 return true;
3451 }
3452 return false;
3453}
3454
3455bool isFNCLEX(unsigned Opcode) {
3456 return Opcode == FNCLEX;
3457}
3458
3459bool isVMOVMSKPS(unsigned Opcode) {
3460 switch (Opcode) {
3461 case VMOVMSKPSYrr:
3462 case VMOVMSKPSrr:
3463 return true;
3464 }
3465 return false;
3466}
3467
3468bool isVPMOVDB(unsigned Opcode) {
3469 switch (Opcode) {
3470 case VPMOVDBZ128mr:
3471 case VPMOVDBZ128mrk:
3472 case VPMOVDBZ128rr:
3473 case VPMOVDBZ128rrk:
3474 case VPMOVDBZ128rrkz:
3475 case VPMOVDBZ256mr:
3476 case VPMOVDBZ256mrk:
3477 case VPMOVDBZ256rr:
3478 case VPMOVDBZ256rrk:
3479 case VPMOVDBZ256rrkz:
3480 case VPMOVDBZmr:
3481 case VPMOVDBZmrk:
3482 case VPMOVDBZrr:
3483 case VPMOVDBZrrk:
3484 case VPMOVDBZrrkz:
3485 return true;
3486 }
3487 return false;
3488}
3489
3490bool isLLWPCB(unsigned Opcode) {
3491 switch (Opcode) {
3492 case LLWPCB:
3493 case LLWPCB64:
3494 return true;
3495 }
3496 return false;
3497}
3498
3499bool isVMULSS(unsigned Opcode) {
3500 switch (Opcode) {
3501 case VMULSSZrm_Int:
3502 case VMULSSZrmk_Int:
3503 case VMULSSZrmkz_Int:
3504 case VMULSSZrr_Int:
3505 case VMULSSZrrb_Int:
3506 case VMULSSZrrbk_Int:
3507 case VMULSSZrrbkz_Int:
3508 case VMULSSZrrk_Int:
3509 case VMULSSZrrkz_Int:
3510 case VMULSSrm_Int:
3511 case VMULSSrr_Int:
3512 return true;
3513 }
3514 return false;
3515}
3516
3517bool isAESENCLAST(unsigned Opcode) {
3518 switch (Opcode) {
3519 case AESENCLASTrm:
3520 case AESENCLASTrr:
3521 return true;
3522 }
3523 return false;
3524}
3525
3526bool isTILEMOVROW(unsigned Opcode) {
3527 switch (Opcode) {
3528 case TILEMOVROWrte:
3529 case TILEMOVROWrti:
3530 return true;
3531 }
3532 return false;
3533}
3534
3535bool isVMINMAXPH(unsigned Opcode) {
3536 switch (Opcode) {
3537 case VMINMAXPHZ128rmbi:
3538 case VMINMAXPHZ128rmbik:
3539 case VMINMAXPHZ128rmbikz:
3540 case VMINMAXPHZ128rmi:
3541 case VMINMAXPHZ128rmik:
3542 case VMINMAXPHZ128rmikz:
3543 case VMINMAXPHZ128rri:
3544 case VMINMAXPHZ128rrik:
3545 case VMINMAXPHZ128rrikz:
3546 case VMINMAXPHZ256rmbi:
3547 case VMINMAXPHZ256rmbik:
3548 case VMINMAXPHZ256rmbikz:
3549 case VMINMAXPHZ256rmi:
3550 case VMINMAXPHZ256rmik:
3551 case VMINMAXPHZ256rmikz:
3552 case VMINMAXPHZ256rri:
3553 case VMINMAXPHZ256rrik:
3554 case VMINMAXPHZ256rrikz:
3555 case VMINMAXPHZrmbi:
3556 case VMINMAXPHZrmbik:
3557 case VMINMAXPHZrmbikz:
3558 case VMINMAXPHZrmi:
3559 case VMINMAXPHZrmik:
3560 case VMINMAXPHZrmikz:
3561 case VMINMAXPHZrri:
3562 case VMINMAXPHZrrib:
3563 case VMINMAXPHZrribk:
3564 case VMINMAXPHZrribkz:
3565 case VMINMAXPHZrrik:
3566 case VMINMAXPHZrrikz:
3567 return true;
3568 }
3569 return false;
3570}
3571
3572bool isVPMAXUB(unsigned Opcode) {
3573 switch (Opcode) {
3574 case VPMAXUBYrm:
3575 case VPMAXUBYrr:
3576 case VPMAXUBZ128rm:
3577 case VPMAXUBZ128rmk:
3578 case VPMAXUBZ128rmkz:
3579 case VPMAXUBZ128rr:
3580 case VPMAXUBZ128rrk:
3581 case VPMAXUBZ128rrkz:
3582 case VPMAXUBZ256rm:
3583 case VPMAXUBZ256rmk:
3584 case VPMAXUBZ256rmkz:
3585 case VPMAXUBZ256rr:
3586 case VPMAXUBZ256rrk:
3587 case VPMAXUBZ256rrkz:
3588 case VPMAXUBZrm:
3589 case VPMAXUBZrmk:
3590 case VPMAXUBZrmkz:
3591 case VPMAXUBZrr:
3592 case VPMAXUBZrrk:
3593 case VPMAXUBZrrkz:
3594 case VPMAXUBrm:
3595 case VPMAXUBrr:
3596 return true;
3597 }
3598 return false;
3599}
3600
3601bool isAAS(unsigned Opcode) {
3602 return Opcode == AAS;
3603}
3604
3605bool isFADD(unsigned Opcode) {
3606 switch (Opcode) {
3607 case ADD_F32m:
3608 case ADD_F64m:
3609 case ADD_FST0r:
3610 case ADD_FrST0:
3611 return true;
3612 }
3613 return false;
3614}
3615
3616bool isJMP(unsigned Opcode) {
3617 switch (Opcode) {
3618 case FARJMP32m:
3619 case JMP16m:
3620 case JMP16r:
3621 case JMP32m:
3622 case JMP32r:
3623 case JMP64m:
3624 case JMP64r:
3625 case JMP_1:
3626 case JMP_2:
3627 case JMP_4:
3628 return true;
3629 }
3630 return false;
3631}
3632
3633bool isXCRYPTECB(unsigned Opcode) {
3634 return Opcode == XCRYPTECB;
3635}
3636
3637bool isPFRCPIT1(unsigned Opcode) {
3638 switch (Opcode) {
3639 case PFRCPIT1rm:
3640 case PFRCPIT1rr:
3641 return true;
3642 }
3643 return false;
3644}
3645
3646bool isPMULHRW(unsigned Opcode) {
3647 switch (Opcode) {
3648 case PMULHRWrm:
3649 case PMULHRWrr:
3650 return true;
3651 }
3652 return false;
3653}
3654
3655bool isVCVTPH2PS(unsigned Opcode) {
3656 switch (Opcode) {
3657 case VCVTPH2PSYrm:
3658 case VCVTPH2PSYrr:
3659 case VCVTPH2PSZ128rm:
3660 case VCVTPH2PSZ128rmk:
3661 case VCVTPH2PSZ128rmkz:
3662 case VCVTPH2PSZ128rr:
3663 case VCVTPH2PSZ128rrk:
3664 case VCVTPH2PSZ128rrkz:
3665 case VCVTPH2PSZ256rm:
3666 case VCVTPH2PSZ256rmk:
3667 case VCVTPH2PSZ256rmkz:
3668 case VCVTPH2PSZ256rr:
3669 case VCVTPH2PSZ256rrk:
3670 case VCVTPH2PSZ256rrkz:
3671 case VCVTPH2PSZrm:
3672 case VCVTPH2PSZrmk:
3673 case VCVTPH2PSZrmkz:
3674 case VCVTPH2PSZrr:
3675 case VCVTPH2PSZrrb:
3676 case VCVTPH2PSZrrbk:
3677 case VCVTPH2PSZrrbkz:
3678 case VCVTPH2PSZrrk:
3679 case VCVTPH2PSZrrkz:
3680 case VCVTPH2PSrm:
3681 case VCVTPH2PSrr:
3682 return true;
3683 }
3684 return false;
3685}
3686
3687bool isVPBLENDVB(unsigned Opcode) {
3688 switch (Opcode) {
3689 case VPBLENDVBYrmr:
3690 case VPBLENDVBYrrr:
3691 case VPBLENDVBrmr:
3692 case VPBLENDVBrrr:
3693 return true;
3694 }
3695 return false;
3696}
3697
3698bool isPCMPESTRI(unsigned Opcode) {
3699 switch (Opcode) {
3700 case PCMPESTRIrmi:
3701 case PCMPESTRIrri:
3702 return true;
3703 }
3704 return false;
3705}
3706
3707bool isSENDUIPI(unsigned Opcode) {
3708 return Opcode == SENDUIPI;
3709}
3710
3711bool isFLDLN2(unsigned Opcode) {
3712 return Opcode == FLDLN2;
3713}
3714
3715bool isVPMACSWD(unsigned Opcode) {
3716 switch (Opcode) {
3717 case VPMACSWDrm:
3718 case VPMACSWDrr:
3719 return true;
3720 }
3721 return false;
3722}
3723
3724bool isSHA1MSG1(unsigned Opcode) {
3725 switch (Opcode) {
3726 case SHA1MSG1rm:
3727 case SHA1MSG1rr:
3728 return true;
3729 }
3730 return false;
3731}
3732
3733bool isVADDPS(unsigned Opcode) {
3734 switch (Opcode) {
3735 case VADDPSYrm:
3736 case VADDPSYrr:
3737 case VADDPSZ128rm:
3738 case VADDPSZ128rmb:
3739 case VADDPSZ128rmbk:
3740 case VADDPSZ128rmbkz:
3741 case VADDPSZ128rmk:
3742 case VADDPSZ128rmkz:
3743 case VADDPSZ128rr:
3744 case VADDPSZ128rrk:
3745 case VADDPSZ128rrkz:
3746 case VADDPSZ256rm:
3747 case VADDPSZ256rmb:
3748 case VADDPSZ256rmbk:
3749 case VADDPSZ256rmbkz:
3750 case VADDPSZ256rmk:
3751 case VADDPSZ256rmkz:
3752 case VADDPSZ256rr:
3753 case VADDPSZ256rrk:
3754 case VADDPSZ256rrkz:
3755 case VADDPSZrm:
3756 case VADDPSZrmb:
3757 case VADDPSZrmbk:
3758 case VADDPSZrmbkz:
3759 case VADDPSZrmk:
3760 case VADDPSZrmkz:
3761 case VADDPSZrr:
3762 case VADDPSZrrb:
3763 case VADDPSZrrbk:
3764 case VADDPSZrrbkz:
3765 case VADDPSZrrk:
3766 case VADDPSZrrkz:
3767 case VADDPSrm:
3768 case VADDPSrr:
3769 return true;
3770 }
3771 return false;
3772}
3773
3774bool isVCVTPS2DQ(unsigned Opcode) {
3775 switch (Opcode) {
3776 case VCVTPS2DQYrm:
3777 case VCVTPS2DQYrr:
3778 case VCVTPS2DQZ128rm:
3779 case VCVTPS2DQZ128rmb:
3780 case VCVTPS2DQZ128rmbk:
3781 case VCVTPS2DQZ128rmbkz:
3782 case VCVTPS2DQZ128rmk:
3783 case VCVTPS2DQZ128rmkz:
3784 case VCVTPS2DQZ128rr:
3785 case VCVTPS2DQZ128rrk:
3786 case VCVTPS2DQZ128rrkz:
3787 case VCVTPS2DQZ256rm:
3788 case VCVTPS2DQZ256rmb:
3789 case VCVTPS2DQZ256rmbk:
3790 case VCVTPS2DQZ256rmbkz:
3791 case VCVTPS2DQZ256rmk:
3792 case VCVTPS2DQZ256rmkz:
3793 case VCVTPS2DQZ256rr:
3794 case VCVTPS2DQZ256rrk:
3795 case VCVTPS2DQZ256rrkz:
3796 case VCVTPS2DQZrm:
3797 case VCVTPS2DQZrmb:
3798 case VCVTPS2DQZrmbk:
3799 case VCVTPS2DQZrmbkz:
3800 case VCVTPS2DQZrmk:
3801 case VCVTPS2DQZrmkz:
3802 case VCVTPS2DQZrr:
3803 case VCVTPS2DQZrrb:
3804 case VCVTPS2DQZrrbk:
3805 case VCVTPS2DQZrrbkz:
3806 case VCVTPS2DQZrrk:
3807 case VCVTPS2DQZrrkz:
3808 case VCVTPS2DQrm:
3809 case VCVTPS2DQrr:
3810 return true;
3811 }
3812 return false;
3813}
3814
3815bool isPFPNACC(unsigned Opcode) {
3816 switch (Opcode) {
3817 case PFPNACCrm:
3818 case PFPNACCrr:
3819 return true;
3820 }
3821 return false;
3822}
3823
3824bool isFMUL(unsigned Opcode) {
3825 switch (Opcode) {
3826 case MUL_F32m:
3827 case MUL_F64m:
3828 case MUL_FST0r:
3829 case MUL_FrST0:
3830 return true;
3831 }
3832 return false;
3833}
3834
3835bool isFNSAVE(unsigned Opcode) {
3836 return Opcode == FSAVEm;
3837}
3838
3839bool isCDQE(unsigned Opcode) {
3840 return Opcode == CDQE;
3841}
3842
3843bool isVPMACSDD(unsigned Opcode) {
3844 switch (Opcode) {
3845 case VPMACSDDrm:
3846 case VPMACSDDrr:
3847 return true;
3848 }
3849 return false;
3850}
3851
3852bool isVSQRTPS(unsigned Opcode) {
3853 switch (Opcode) {
3854 case VSQRTPSYm:
3855 case VSQRTPSYr:
3856 case VSQRTPSZ128m:
3857 case VSQRTPSZ128mb:
3858 case VSQRTPSZ128mbk:
3859 case VSQRTPSZ128mbkz:
3860 case VSQRTPSZ128mk:
3861 case VSQRTPSZ128mkz:
3862 case VSQRTPSZ128r:
3863 case VSQRTPSZ128rk:
3864 case VSQRTPSZ128rkz:
3865 case VSQRTPSZ256m:
3866 case VSQRTPSZ256mb:
3867 case VSQRTPSZ256mbk:
3868 case VSQRTPSZ256mbkz:
3869 case VSQRTPSZ256mk:
3870 case VSQRTPSZ256mkz:
3871 case VSQRTPSZ256r:
3872 case VSQRTPSZ256rk:
3873 case VSQRTPSZ256rkz:
3874 case VSQRTPSZm:
3875 case VSQRTPSZmb:
3876 case VSQRTPSZmbk:
3877 case VSQRTPSZmbkz:
3878 case VSQRTPSZmk:
3879 case VSQRTPSZmkz:
3880 case VSQRTPSZr:
3881 case VSQRTPSZrb:
3882 case VSQRTPSZrbk:
3883 case VSQRTPSZrbkz:
3884 case VSQRTPSZrk:
3885 case VSQRTPSZrkz:
3886 case VSQRTPSm:
3887 case VSQRTPSr:
3888 return true;
3889 }
3890 return false;
3891}
3892
3893bool isCMPSQ(unsigned Opcode) {
3894 return Opcode == CMPSQ;
3895}
3896
3897bool isVPSCATTERDD(unsigned Opcode) {
3898 switch (Opcode) {
3899 case VPSCATTERDDZ128mr:
3900 case VPSCATTERDDZ256mr:
3901 case VPSCATTERDDZmr:
3902 return true;
3903 }
3904 return false;
3905}
3906
3907bool isVCVTTSD2USIS(unsigned Opcode) {
3908 switch (Opcode) {
3909 case VCVTTSD2USI64Srm_Int:
3910 case VCVTTSD2USI64Srr_Int:
3911 case VCVTTSD2USI64Srrb_Int:
3912 case VCVTTSD2USISrm_Int:
3913 case VCVTTSD2USISrr_Int:
3914 case VCVTTSD2USISrrb_Int:
3915 return true;
3916 }
3917 return false;
3918}
3919
3920bool isVRNDSCALESD(unsigned Opcode) {
3921 switch (Opcode) {
3922 case VRNDSCALESDZrmi_Int:
3923 case VRNDSCALESDZrmik_Int:
3924 case VRNDSCALESDZrmikz_Int:
3925 case VRNDSCALESDZrri_Int:
3926 case VRNDSCALESDZrrib_Int:
3927 case VRNDSCALESDZrribk_Int:
3928 case VRNDSCALESDZrribkz_Int:
3929 case VRNDSCALESDZrrik_Int:
3930 case VRNDSCALESDZrrikz_Int:
3931 return true;
3932 }
3933 return false;
3934}
3935
3936bool isSUBPS(unsigned Opcode) {
3937 switch (Opcode) {
3938 case SUBPSrm:
3939 case SUBPSrr:
3940 return true;
3941 }
3942 return false;
3943}
3944
3945bool isVMAXSH(unsigned Opcode) {
3946 switch (Opcode) {
3947 case VMAXSHZrm_Int:
3948 case VMAXSHZrmk_Int:
3949 case VMAXSHZrmkz_Int:
3950 case VMAXSHZrr_Int:
3951 case VMAXSHZrrb_Int:
3952 case VMAXSHZrrbk_Int:
3953 case VMAXSHZrrbkz_Int:
3954 case VMAXSHZrrk_Int:
3955 case VMAXSHZrrkz_Int:
3956 return true;
3957 }
3958 return false;
3959}
3960
3961bool isFLDZ(unsigned Opcode) {
3962 return Opcode == LD_F0;
3963}
3964
3965bool isVFNMADD132SS(unsigned Opcode) {
3966 switch (Opcode) {
3967 case VFNMADD132SSZm_Int:
3968 case VFNMADD132SSZmk_Int:
3969 case VFNMADD132SSZmkz_Int:
3970 case VFNMADD132SSZr_Int:
3971 case VFNMADD132SSZrb_Int:
3972 case VFNMADD132SSZrbk_Int:
3973 case VFNMADD132SSZrbkz_Int:
3974 case VFNMADD132SSZrk_Int:
3975 case VFNMADD132SSZrkz_Int:
3976 case VFNMADD132SSm_Int:
3977 case VFNMADD132SSr_Int:
3978 return true;
3979 }
3980 return false;
3981}
3982
3983bool isLGDTW(unsigned Opcode) {
3984 return Opcode == LGDT16m;
3985}
3986
3987bool isTCVTROWPS2PHH(unsigned Opcode) {
3988 switch (Opcode) {
3989 case TCVTROWPS2PHHrte:
3990 case TCVTROWPS2PHHrti:
3991 return true;
3992 }
3993 return false;
3994}
3995
3996bool isINC(unsigned Opcode) {
3997 switch (Opcode) {
3998 case INC16m:
3999 case INC16m_EVEX:
4000 case INC16m_ND:
4001 case INC16m_NF:
4002 case INC16m_NF_ND:
4003 case INC16r:
4004 case INC16r_EVEX:
4005 case INC16r_ND:
4006 case INC16r_NF:
4007 case INC16r_NF_ND:
4008 case INC16r_alt:
4009 case INC32m:
4010 case INC32m_EVEX:
4011 case INC32m_ND:
4012 case INC32m_NF:
4013 case INC32m_NF_ND:
4014 case INC32r:
4015 case INC32r_EVEX:
4016 case INC32r_ND:
4017 case INC32r_NF:
4018 case INC32r_NF_ND:
4019 case INC32r_alt:
4020 case INC64m:
4021 case INC64m_EVEX:
4022 case INC64m_ND:
4023 case INC64m_NF:
4024 case INC64m_NF_ND:
4025 case INC64r:
4026 case INC64r_EVEX:
4027 case INC64r_ND:
4028 case INC64r_NF:
4029 case INC64r_NF_ND:
4030 case INC8m:
4031 case INC8m_EVEX:
4032 case INC8m_ND:
4033 case INC8m_NF:
4034 case INC8m_NF_ND:
4035 case INC8r:
4036 case INC8r_EVEX:
4037 case INC8r_ND:
4038 case INC8r_NF:
4039 case INC8r_NF_ND:
4040 return true;
4041 }
4042 return false;
4043}
4044
4045bool isVPANDN(unsigned Opcode) {
4046 switch (Opcode) {
4047 case VPANDNYrm:
4048 case VPANDNYrr:
4049 case VPANDNrm:
4050 case VPANDNrr:
4051 return true;
4052 }
4053 return false;
4054}
4055
4056bool isPABSB(unsigned Opcode) {
4057 switch (Opcode) {
4058 case MMX_PABSBrm:
4059 case MMX_PABSBrr:
4060 case PABSBrm:
4061 case PABSBrr:
4062 return true;
4063 }
4064 return false;
4065}
4066
4067bool isVSHA512RNDS2(unsigned Opcode) {
4068 return Opcode == VSHA512RNDS2rr;
4069}
4070
4071bool isPHADDSW(unsigned Opcode) {
4072 switch (Opcode) {
4073 case MMX_PHADDSWrm:
4074 case MMX_PHADDSWrr:
4075 case PHADDSWrm:
4076 case PHADDSWrr:
4077 return true;
4078 }
4079 return false;
4080}
4081
4082bool isVPMAXUD(unsigned Opcode) {
4083 switch (Opcode) {
4084 case VPMAXUDYrm:
4085 case VPMAXUDYrr:
4086 case VPMAXUDZ128rm:
4087 case VPMAXUDZ128rmb:
4088 case VPMAXUDZ128rmbk:
4089 case VPMAXUDZ128rmbkz:
4090 case VPMAXUDZ128rmk:
4091 case VPMAXUDZ128rmkz:
4092 case VPMAXUDZ128rr:
4093 case VPMAXUDZ128rrk:
4094 case VPMAXUDZ128rrkz:
4095 case VPMAXUDZ256rm:
4096 case VPMAXUDZ256rmb:
4097 case VPMAXUDZ256rmbk:
4098 case VPMAXUDZ256rmbkz:
4099 case VPMAXUDZ256rmk:
4100 case VPMAXUDZ256rmkz:
4101 case VPMAXUDZ256rr:
4102 case VPMAXUDZ256rrk:
4103 case VPMAXUDZ256rrkz:
4104 case VPMAXUDZrm:
4105 case VPMAXUDZrmb:
4106 case VPMAXUDZrmbk:
4107 case VPMAXUDZrmbkz:
4108 case VPMAXUDZrmk:
4109 case VPMAXUDZrmkz:
4110 case VPMAXUDZrr:
4111 case VPMAXUDZrrk:
4112 case VPMAXUDZrrkz:
4113 case VPMAXUDrm:
4114 case VPMAXUDrr:
4115 return true;
4116 }
4117 return false;
4118}
4119
4120bool isVPMOVSQW(unsigned Opcode) {
4121 switch (Opcode) {
4122 case VPMOVSQWZ128mr:
4123 case VPMOVSQWZ128mrk:
4124 case VPMOVSQWZ128rr:
4125 case VPMOVSQWZ128rrk:
4126 case VPMOVSQWZ128rrkz:
4127 case VPMOVSQWZ256mr:
4128 case VPMOVSQWZ256mrk:
4129 case VPMOVSQWZ256rr:
4130 case VPMOVSQWZ256rrk:
4131 case VPMOVSQWZ256rrkz:
4132 case VPMOVSQWZmr:
4133 case VPMOVSQWZmrk:
4134 case VPMOVSQWZrr:
4135 case VPMOVSQWZrrk:
4136 case VPMOVSQWZrrkz:
4137 return true;
4138 }
4139 return false;
4140}
4141
4142bool isADDSUBPS(unsigned Opcode) {
4143 switch (Opcode) {
4144 case ADDSUBPSrm:
4145 case ADDSUBPSrr:
4146 return true;
4147 }
4148 return false;
4149}
4150
4151bool isVPMACSSDQL(unsigned Opcode) {
4152 switch (Opcode) {
4153 case VPMACSSDQLrm:
4154 case VPMACSSDQLrr:
4155 return true;
4156 }
4157 return false;
4158}
4159
4160bool isPXOR(unsigned Opcode) {
4161 switch (Opcode) {
4162 case MMX_PXORrm:
4163 case MMX_PXORrr:
4164 case PXORrm:
4165 case PXORrr:
4166 return true;
4167 }
4168 return false;
4169}
4170
4171bool isVPSRAD(unsigned Opcode) {
4172 switch (Opcode) {
4173 case VPSRADYri:
4174 case VPSRADYrm:
4175 case VPSRADYrr:
4176 case VPSRADZ128mbi:
4177 case VPSRADZ128mbik:
4178 case VPSRADZ128mbikz:
4179 case VPSRADZ128mi:
4180 case VPSRADZ128mik:
4181 case VPSRADZ128mikz:
4182 case VPSRADZ128ri:
4183 case VPSRADZ128rik:
4184 case VPSRADZ128rikz:
4185 case VPSRADZ128rm:
4186 case VPSRADZ128rmk:
4187 case VPSRADZ128rmkz:
4188 case VPSRADZ128rr:
4189 case VPSRADZ128rrk:
4190 case VPSRADZ128rrkz:
4191 case VPSRADZ256mbi:
4192 case VPSRADZ256mbik:
4193 case VPSRADZ256mbikz:
4194 case VPSRADZ256mi:
4195 case VPSRADZ256mik:
4196 case VPSRADZ256mikz:
4197 case VPSRADZ256ri:
4198 case VPSRADZ256rik:
4199 case VPSRADZ256rikz:
4200 case VPSRADZ256rm:
4201 case VPSRADZ256rmk:
4202 case VPSRADZ256rmkz:
4203 case VPSRADZ256rr:
4204 case VPSRADZ256rrk:
4205 case VPSRADZ256rrkz:
4206 case VPSRADZmbi:
4207 case VPSRADZmbik:
4208 case VPSRADZmbikz:
4209 case VPSRADZmi:
4210 case VPSRADZmik:
4211 case VPSRADZmikz:
4212 case VPSRADZri:
4213 case VPSRADZrik:
4214 case VPSRADZrikz:
4215 case VPSRADZrm:
4216 case VPSRADZrmk:
4217 case VPSRADZrmkz:
4218 case VPSRADZrr:
4219 case VPSRADZrrk:
4220 case VPSRADZrrkz:
4221 case VPSRADri:
4222 case VPSRADrm:
4223 case VPSRADrr:
4224 return true;
4225 }
4226 return false;
4227}
4228
4229bool isVPSHAB(unsigned Opcode) {
4230 switch (Opcode) {
4231 case VPSHABmr:
4232 case VPSHABrm:
4233 case VPSHABrr:
4234 case VPSHABrr_REV:
4235 return true;
4236 }
4237 return false;
4238}
4239
4240bool isBTR(unsigned Opcode) {
4241 switch (Opcode) {
4242 case BTR16mi8:
4243 case BTR16mr:
4244 case BTR16ri8:
4245 case BTR16rr:
4246 case BTR32mi8:
4247 case BTR32mr:
4248 case BTR32ri8:
4249 case BTR32rr:
4250 case BTR64mi8:
4251 case BTR64mr:
4252 case BTR64ri8:
4253 case BTR64rr:
4254 return true;
4255 }
4256 return false;
4257}
4258
4259bool isKORW(unsigned Opcode) {
4260 return Opcode == KORWkk;
4261}
4262
4263bool isVRANGESS(unsigned Opcode) {
4264 switch (Opcode) {
4265 case VRANGESSZrmi:
4266 case VRANGESSZrmik:
4267 case VRANGESSZrmikz:
4268 case VRANGESSZrri:
4269 case VRANGESSZrrib:
4270 case VRANGESSZrribk:
4271 case VRANGESSZrribkz:
4272 case VRANGESSZrrik:
4273 case VRANGESSZrrikz:
4274 return true;
4275 }
4276 return false;
4277}
4278
4279bool isVCMPPS(unsigned Opcode) {
4280 switch (Opcode) {
4281 case VCMPPSYrmi:
4282 case VCMPPSYrri:
4283 case VCMPPSZ128rmbi:
4284 case VCMPPSZ128rmbik:
4285 case VCMPPSZ128rmi:
4286 case VCMPPSZ128rmik:
4287 case VCMPPSZ128rri:
4288 case VCMPPSZ128rrik:
4289 case VCMPPSZ256rmbi:
4290 case VCMPPSZ256rmbik:
4291 case VCMPPSZ256rmi:
4292 case VCMPPSZ256rmik:
4293 case VCMPPSZ256rri:
4294 case VCMPPSZ256rrik:
4295 case VCMPPSZrmbi:
4296 case VCMPPSZrmbik:
4297 case VCMPPSZrmi:
4298 case VCMPPSZrmik:
4299 case VCMPPSZrri:
4300 case VCMPPSZrrib:
4301 case VCMPPSZrribk:
4302 case VCMPPSZrrik:
4303 case VCMPPSrmi:
4304 case VCMPPSrri:
4305 return true;
4306 }
4307 return false;
4308}
4309
4310bool isVPLZCNTD(unsigned Opcode) {
4311 switch (Opcode) {
4312 case VPLZCNTDZ128rm:
4313 case VPLZCNTDZ128rmb:
4314 case VPLZCNTDZ128rmbk:
4315 case VPLZCNTDZ128rmbkz:
4316 case VPLZCNTDZ128rmk:
4317 case VPLZCNTDZ128rmkz:
4318 case VPLZCNTDZ128rr:
4319 case VPLZCNTDZ128rrk:
4320 case VPLZCNTDZ128rrkz:
4321 case VPLZCNTDZ256rm:
4322 case VPLZCNTDZ256rmb:
4323 case VPLZCNTDZ256rmbk:
4324 case VPLZCNTDZ256rmbkz:
4325 case VPLZCNTDZ256rmk:
4326 case VPLZCNTDZ256rmkz:
4327 case VPLZCNTDZ256rr:
4328 case VPLZCNTDZ256rrk:
4329 case VPLZCNTDZ256rrkz:
4330 case VPLZCNTDZrm:
4331 case VPLZCNTDZrmb:
4332 case VPLZCNTDZrmbk:
4333 case VPLZCNTDZrmbkz:
4334 case VPLZCNTDZrmk:
4335 case VPLZCNTDZrmkz:
4336 case VPLZCNTDZrr:
4337 case VPLZCNTDZrrk:
4338 case VPLZCNTDZrrkz:
4339 return true;
4340 }
4341 return false;
4342}
4343
4344bool isTDPBUUD(unsigned Opcode) {
4345 return Opcode == TDPBUUD;
4346}
4347
4348bool isROUNDPS(unsigned Opcode) {
4349 switch (Opcode) {
4350 case ROUNDPSmi:
4351 case ROUNDPSri:
4352 return true;
4353 }
4354 return false;
4355}
4356
4357bool isFABS(unsigned Opcode) {
4358 return Opcode == ABS_F;
4359}
4360
4361bool isSUBPD(unsigned Opcode) {
4362 switch (Opcode) {
4363 case SUBPDrm:
4364 case SUBPDrr:
4365 return true;
4366 }
4367 return false;
4368}
4369
4370bool isGF2P8MULB(unsigned Opcode) {
4371 switch (Opcode) {
4372 case GF2P8MULBrm:
4373 case GF2P8MULBrr:
4374 return true;
4375 }
4376 return false;
4377}
4378
4379bool isTZMSK(unsigned Opcode) {
4380 switch (Opcode) {
4381 case TZMSK32rm:
4382 case TZMSK32rr:
4383 case TZMSK64rm:
4384 case TZMSK64rr:
4385 return true;
4386 }
4387 return false;
4388}
4389
4390bool isVMINMAXSD(unsigned Opcode) {
4391 switch (Opcode) {
4392 case VMINMAXSDrmi_Int:
4393 case VMINMAXSDrmik_Int:
4394 case VMINMAXSDrmikz_Int:
4395 case VMINMAXSDrri_Int:
4396 case VMINMAXSDrrib_Int:
4397 case VMINMAXSDrribk_Int:
4398 case VMINMAXSDrribkz_Int:
4399 case VMINMAXSDrrik_Int:
4400 case VMINMAXSDrrikz_Int:
4401 return true;
4402 }
4403 return false;
4404}
4405
4406bool isANDPS(unsigned Opcode) {
4407 switch (Opcode) {
4408 case ANDPSrm:
4409 case ANDPSrr:
4410 return true;
4411 }
4412 return false;
4413}
4414
4415bool isVEXTRACTF32X8(unsigned Opcode) {
4416 switch (Opcode) {
4417 case VEXTRACTF32X8Zmri:
4418 case VEXTRACTF32X8Zmrik:
4419 case VEXTRACTF32X8Zrri:
4420 case VEXTRACTF32X8Zrrik:
4421 case VEXTRACTF32X8Zrrikz:
4422 return true;
4423 }
4424 return false;
4425}
4426
4427bool isSEAMRET(unsigned Opcode) {
4428 return Opcode == SEAMRET;
4429}
4430
4431bool isVPCOMW(unsigned Opcode) {
4432 switch (Opcode) {
4433 case VPCOMWmi:
4434 case VPCOMWri:
4435 return true;
4436 }
4437 return false;
4438}
4439
4440bool isVFIXUPIMMPD(unsigned Opcode) {
4441 switch (Opcode) {
4442 case VFIXUPIMMPDZ128rmbi:
4443 case VFIXUPIMMPDZ128rmbik:
4444 case VFIXUPIMMPDZ128rmbikz:
4445 case VFIXUPIMMPDZ128rmi:
4446 case VFIXUPIMMPDZ128rmik:
4447 case VFIXUPIMMPDZ128rmikz:
4448 case VFIXUPIMMPDZ128rri:
4449 case VFIXUPIMMPDZ128rrik:
4450 case VFIXUPIMMPDZ128rrikz:
4451 case VFIXUPIMMPDZ256rmbi:
4452 case VFIXUPIMMPDZ256rmbik:
4453 case VFIXUPIMMPDZ256rmbikz:
4454 case VFIXUPIMMPDZ256rmi:
4455 case VFIXUPIMMPDZ256rmik:
4456 case VFIXUPIMMPDZ256rmikz:
4457 case VFIXUPIMMPDZ256rri:
4458 case VFIXUPIMMPDZ256rrik:
4459 case VFIXUPIMMPDZ256rrikz:
4460 case VFIXUPIMMPDZrmbi:
4461 case VFIXUPIMMPDZrmbik:
4462 case VFIXUPIMMPDZrmbikz:
4463 case VFIXUPIMMPDZrmi:
4464 case VFIXUPIMMPDZrmik:
4465 case VFIXUPIMMPDZrmikz:
4466 case VFIXUPIMMPDZrri:
4467 case VFIXUPIMMPDZrrib:
4468 case VFIXUPIMMPDZrribk:
4469 case VFIXUPIMMPDZrribkz:
4470 case VFIXUPIMMPDZrrik:
4471 case VFIXUPIMMPDZrrikz:
4472 return true;
4473 }
4474 return false;
4475}
4476
4477bool isKANDND(unsigned Opcode) {
4478 return Opcode == KANDNDkk;
4479}
4480
4481bool isVMRESUME(unsigned Opcode) {
4482 return Opcode == VMRESUME;
4483}
4484
4485bool isCVTPD2DQ(unsigned Opcode) {
4486 switch (Opcode) {
4487 case CVTPD2DQrm:
4488 case CVTPD2DQrr:
4489 return true;
4490 }
4491 return false;
4492}
4493
4494bool isVFNMADD213PS(unsigned Opcode) {
4495 switch (Opcode) {
4496 case VFNMADD213PSYm:
4497 case VFNMADD213PSYr:
4498 case VFNMADD213PSZ128m:
4499 case VFNMADD213PSZ128mb:
4500 case VFNMADD213PSZ128mbk:
4501 case VFNMADD213PSZ128mbkz:
4502 case VFNMADD213PSZ128mk:
4503 case VFNMADD213PSZ128mkz:
4504 case VFNMADD213PSZ128r:
4505 case VFNMADD213PSZ128rk:
4506 case VFNMADD213PSZ128rkz:
4507 case VFNMADD213PSZ256m:
4508 case VFNMADD213PSZ256mb:
4509 case VFNMADD213PSZ256mbk:
4510 case VFNMADD213PSZ256mbkz:
4511 case VFNMADD213PSZ256mk:
4512 case VFNMADD213PSZ256mkz:
4513 case VFNMADD213PSZ256r:
4514 case VFNMADD213PSZ256rk:
4515 case VFNMADD213PSZ256rkz:
4516 case VFNMADD213PSZm:
4517 case VFNMADD213PSZmb:
4518 case VFNMADD213PSZmbk:
4519 case VFNMADD213PSZmbkz:
4520 case VFNMADD213PSZmk:
4521 case VFNMADD213PSZmkz:
4522 case VFNMADD213PSZr:
4523 case VFNMADD213PSZrb:
4524 case VFNMADD213PSZrbk:
4525 case VFNMADD213PSZrbkz:
4526 case VFNMADD213PSZrk:
4527 case VFNMADD213PSZrkz:
4528 case VFNMADD213PSm:
4529 case VFNMADD213PSr:
4530 return true;
4531 }
4532 return false;
4533}
4534
4535bool isVPEXTRD(unsigned Opcode) {
4536 switch (Opcode) {
4537 case VPEXTRDZmri:
4538 case VPEXTRDZrri:
4539 case VPEXTRDmri:
4540 case VPEXTRDrri:
4541 return true;
4542 }
4543 return false;
4544}
4545
4546bool isPACKUSWB(unsigned Opcode) {
4547 switch (Opcode) {
4548 case MMX_PACKUSWBrm:
4549 case MMX_PACKUSWBrr:
4550 case PACKUSWBrm:
4551 case PACKUSWBrr:
4552 return true;
4553 }
4554 return false;
4555}
4556
4557bool isVEXTRACTI32X8(unsigned Opcode) {
4558 switch (Opcode) {
4559 case VEXTRACTI32X8Zmri:
4560 case VEXTRACTI32X8Zmrik:
4561 case VEXTRACTI32X8Zrri:
4562 case VEXTRACTI32X8Zrrik:
4563 case VEXTRACTI32X8Zrrikz:
4564 return true;
4565 }
4566 return false;
4567}
4568
4569bool isVHADDPD(unsigned Opcode) {
4570 switch (Opcode) {
4571 case VHADDPDYrm:
4572 case VHADDPDYrr:
4573 case VHADDPDrm:
4574 case VHADDPDrr:
4575 return true;
4576 }
4577 return false;
4578}
4579
4580bool isVPSADBW(unsigned Opcode) {
4581 switch (Opcode) {
4582 case VPSADBWYrm:
4583 case VPSADBWYrr:
4584 case VPSADBWZ128rm:
4585 case VPSADBWZ128rr:
4586 case VPSADBWZ256rm:
4587 case VPSADBWZ256rr:
4588 case VPSADBWZrm:
4589 case VPSADBWZrr:
4590 case VPSADBWrm:
4591 case VPSADBWrr:
4592 return true;
4593 }
4594 return false;
4595}
4596
4597bool isMOVDQ2Q(unsigned Opcode) {
4598 return Opcode == MMX_MOVDQ2Qrr;
4599}
4600
4601bool isPUNPCKHBW(unsigned Opcode) {
4602 switch (Opcode) {
4603 case MMX_PUNPCKHBWrm:
4604 case MMX_PUNPCKHBWrr:
4605 case PUNPCKHBWrm:
4606 case PUNPCKHBWrr:
4607 return true;
4608 }
4609 return false;
4610}
4611
4612bool isXOR(unsigned Opcode) {
4613 switch (Opcode) {
4614 case XOR16i16:
4615 case XOR16mi:
4616 case XOR16mi8:
4617 case XOR16mi8_EVEX:
4618 case XOR16mi8_ND:
4619 case XOR16mi8_NF:
4620 case XOR16mi8_NF_ND:
4621 case XOR16mi_EVEX:
4622 case XOR16mi_ND:
4623 case XOR16mi_NF:
4624 case XOR16mi_NF_ND:
4625 case XOR16mr:
4626 case XOR16mr_EVEX:
4627 case XOR16mr_ND:
4628 case XOR16mr_NF:
4629 case XOR16mr_NF_ND:
4630 case XOR16ri:
4631 case XOR16ri8:
4632 case XOR16ri8_EVEX:
4633 case XOR16ri8_ND:
4634 case XOR16ri8_NF:
4635 case XOR16ri8_NF_ND:
4636 case XOR16ri_EVEX:
4637 case XOR16ri_ND:
4638 case XOR16ri_NF:
4639 case XOR16ri_NF_ND:
4640 case XOR16rm:
4641 case XOR16rm_EVEX:
4642 case XOR16rm_ND:
4643 case XOR16rm_NF:
4644 case XOR16rm_NF_ND:
4645 case XOR16rr:
4646 case XOR16rr_EVEX:
4647 case XOR16rr_EVEX_REV:
4648 case XOR16rr_ND:
4649 case XOR16rr_ND_REV:
4650 case XOR16rr_NF:
4651 case XOR16rr_NF_ND:
4652 case XOR16rr_NF_ND_REV:
4653 case XOR16rr_NF_REV:
4654 case XOR16rr_REV:
4655 case XOR32i32:
4656 case XOR32mi:
4657 case XOR32mi8:
4658 case XOR32mi8_EVEX:
4659 case XOR32mi8_ND:
4660 case XOR32mi8_NF:
4661 case XOR32mi8_NF_ND:
4662 case XOR32mi_EVEX:
4663 case XOR32mi_ND:
4664 case XOR32mi_NF:
4665 case XOR32mi_NF_ND:
4666 case XOR32mr:
4667 case XOR32mr_EVEX:
4668 case XOR32mr_ND:
4669 case XOR32mr_NF:
4670 case XOR32mr_NF_ND:
4671 case XOR32ri:
4672 case XOR32ri8:
4673 case XOR32ri8_EVEX:
4674 case XOR32ri8_ND:
4675 case XOR32ri8_NF:
4676 case XOR32ri8_NF_ND:
4677 case XOR32ri_EVEX:
4678 case XOR32ri_ND:
4679 case XOR32ri_NF:
4680 case XOR32ri_NF_ND:
4681 case XOR32rm:
4682 case XOR32rm_EVEX:
4683 case XOR32rm_ND:
4684 case XOR32rm_NF:
4685 case XOR32rm_NF_ND:
4686 case XOR32rr:
4687 case XOR32rr_EVEX:
4688 case XOR32rr_EVEX_REV:
4689 case XOR32rr_ND:
4690 case XOR32rr_ND_REV:
4691 case XOR32rr_NF:
4692 case XOR32rr_NF_ND:
4693 case XOR32rr_NF_ND_REV:
4694 case XOR32rr_NF_REV:
4695 case XOR32rr_REV:
4696 case XOR64i32:
4697 case XOR64mi32:
4698 case XOR64mi32_EVEX:
4699 case XOR64mi32_ND:
4700 case XOR64mi32_NF:
4701 case XOR64mi32_NF_ND:
4702 case XOR64mi8:
4703 case XOR64mi8_EVEX:
4704 case XOR64mi8_ND:
4705 case XOR64mi8_NF:
4706 case XOR64mi8_NF_ND:
4707 case XOR64mr:
4708 case XOR64mr_EVEX:
4709 case XOR64mr_ND:
4710 case XOR64mr_NF:
4711 case XOR64mr_NF_ND:
4712 case XOR64ri32:
4713 case XOR64ri32_EVEX:
4714 case XOR64ri32_ND:
4715 case XOR64ri32_NF:
4716 case XOR64ri32_NF_ND:
4717 case XOR64ri8:
4718 case XOR64ri8_EVEX:
4719 case XOR64ri8_ND:
4720 case XOR64ri8_NF:
4721 case XOR64ri8_NF_ND:
4722 case XOR64rm:
4723 case XOR64rm_EVEX:
4724 case XOR64rm_ND:
4725 case XOR64rm_NF:
4726 case XOR64rm_NF_ND:
4727 case XOR64rr:
4728 case XOR64rr_EVEX:
4729 case XOR64rr_EVEX_REV:
4730 case XOR64rr_ND:
4731 case XOR64rr_ND_REV:
4732 case XOR64rr_NF:
4733 case XOR64rr_NF_ND:
4734 case XOR64rr_NF_ND_REV:
4735 case XOR64rr_NF_REV:
4736 case XOR64rr_REV:
4737 case XOR8i8:
4738 case XOR8mi:
4739 case XOR8mi8:
4740 case XOR8mi_EVEX:
4741 case XOR8mi_ND:
4742 case XOR8mi_NF:
4743 case XOR8mi_NF_ND:
4744 case XOR8mr:
4745 case XOR8mr_EVEX:
4746 case XOR8mr_ND:
4747 case XOR8mr_NF:
4748 case XOR8mr_NF_ND:
4749 case XOR8ri:
4750 case XOR8ri8:
4751 case XOR8ri_EVEX:
4752 case XOR8ri_ND:
4753 case XOR8ri_NF:
4754 case XOR8ri_NF_ND:
4755 case XOR8rm:
4756 case XOR8rm_EVEX:
4757 case XOR8rm_ND:
4758 case XOR8rm_NF:
4759 case XOR8rm_NF_ND:
4760 case XOR8rr:
4761 case XOR8rr_EVEX:
4762 case XOR8rr_EVEX_REV:
4763 case XOR8rr_ND:
4764 case XOR8rr_ND_REV:
4765 case XOR8rr_NF:
4766 case XOR8rr_NF_ND:
4767 case XOR8rr_NF_ND_REV:
4768 case XOR8rr_NF_REV:
4769 case XOR8rr_REV:
4770 return true;
4771 }
4772 return false;
4773}
4774
4775bool isPSIGNB(unsigned Opcode) {
4776 switch (Opcode) {
4777 case MMX_PSIGNBrm:
4778 case MMX_PSIGNBrr:
4779 case PSIGNBrm:
4780 case PSIGNBrr:
4781 return true;
4782 }
4783 return false;
4784}
4785
4786bool isVPHADDSW(unsigned Opcode) {
4787 switch (Opcode) {
4788 case VPHADDSWYrm:
4789 case VPHADDSWYrr:
4790 case VPHADDSWrm:
4791 case VPHADDSWrr:
4792 return true;
4793 }
4794 return false;
4795}
4796
4797bool isFADDP(unsigned Opcode) {
4798 return Opcode == ADD_FPrST0;
4799}
4800
4801bool isNEG(unsigned Opcode) {
4802 switch (Opcode) {
4803 case NEG16m:
4804 case NEG16m_EVEX:
4805 case NEG16m_ND:
4806 case NEG16m_NF:
4807 case NEG16m_NF_ND:
4808 case NEG16r:
4809 case NEG16r_EVEX:
4810 case NEG16r_ND:
4811 case NEG16r_NF:
4812 case NEG16r_NF_ND:
4813 case NEG32m:
4814 case NEG32m_EVEX:
4815 case NEG32m_ND:
4816 case NEG32m_NF:
4817 case NEG32m_NF_ND:
4818 case NEG32r:
4819 case NEG32r_EVEX:
4820 case NEG32r_ND:
4821 case NEG32r_NF:
4822 case NEG32r_NF_ND:
4823 case NEG64m:
4824 case NEG64m_EVEX:
4825 case NEG64m_ND:
4826 case NEG64m_NF:
4827 case NEG64m_NF_ND:
4828 case NEG64r:
4829 case NEG64r_EVEX:
4830 case NEG64r_ND:
4831 case NEG64r_NF:
4832 case NEG64r_NF_ND:
4833 case NEG8m:
4834 case NEG8m_EVEX:
4835 case NEG8m_ND:
4836 case NEG8m_NF:
4837 case NEG8m_NF_ND:
4838 case NEG8r:
4839 case NEG8r_EVEX:
4840 case NEG8r_ND:
4841 case NEG8r_NF:
4842 case NEG8r_NF_ND:
4843 return true;
4844 }
4845 return false;
4846}
4847
4848bool isFLDLG2(unsigned Opcode) {
4849 return Opcode == FLDLG2;
4850}
4851
4852bool isFNOP(unsigned Opcode) {
4853 return Opcode == FNOP;
4854}
4855
4856bool isVMINSS(unsigned Opcode) {
4857 switch (Opcode) {
4858 case VMINSSZrm_Int:
4859 case VMINSSZrmk_Int:
4860 case VMINSSZrmkz_Int:
4861 case VMINSSZrr_Int:
4862 case VMINSSZrrb_Int:
4863 case VMINSSZrrbk_Int:
4864 case VMINSSZrrbkz_Int:
4865 case VMINSSZrrk_Int:
4866 case VMINSSZrrkz_Int:
4867 case VMINSSrm_Int:
4868 case VMINSSrr_Int:
4869 return true;
4870 }
4871 return false;
4872}
4873
4874bool isPCMPISTRM(unsigned Opcode) {
4875 switch (Opcode) {
4876 case PCMPISTRMrmi:
4877 case PCMPISTRMrri:
4878 return true;
4879 }
4880 return false;
4881}
4882
4883bool isVFMADD132SS(unsigned Opcode) {
4884 switch (Opcode) {
4885 case VFMADD132SSZm_Int:
4886 case VFMADD132SSZmk_Int:
4887 case VFMADD132SSZmkz_Int:
4888 case VFMADD132SSZr_Int:
4889 case VFMADD132SSZrb_Int:
4890 case VFMADD132SSZrbk_Int:
4891 case VFMADD132SSZrbkz_Int:
4892 case VFMADD132SSZrk_Int:
4893 case VFMADD132SSZrkz_Int:
4894 case VFMADD132SSm_Int:
4895 case VFMADD132SSr_Int:
4896 return true;
4897 }
4898 return false;
4899}
4900
4901bool isFDIVRP(unsigned Opcode) {
4902 return Opcode == DIVR_FPrST0;
4903}
4904
4905bool isPUSHAL(unsigned Opcode) {
4906 return Opcode == PUSHA32;
4907}
4908
4909bool isVPMACSDQL(unsigned Opcode) {
4910 switch (Opcode) {
4911 case VPMACSDQLrm:
4912 case VPMACSDQLrr:
4913 return true;
4914 }
4915 return false;
4916}
4917
4918bool isSUBSD(unsigned Opcode) {
4919 switch (Opcode) {
4920 case SUBSDrm_Int:
4921 case SUBSDrr_Int:
4922 return true;
4923 }
4924 return false;
4925}
4926
4927bool isVPBLENDMQ(unsigned Opcode) {
4928 switch (Opcode) {
4929 case VPBLENDMQZ128rm:
4930 case VPBLENDMQZ128rmb:
4931 case VPBLENDMQZ128rmbk:
4932 case VPBLENDMQZ128rmbkz:
4933 case VPBLENDMQZ128rmk:
4934 case VPBLENDMQZ128rmkz:
4935 case VPBLENDMQZ128rr:
4936 case VPBLENDMQZ128rrk:
4937 case VPBLENDMQZ128rrkz:
4938 case VPBLENDMQZ256rm:
4939 case VPBLENDMQZ256rmb:
4940 case VPBLENDMQZ256rmbk:
4941 case VPBLENDMQZ256rmbkz:
4942 case VPBLENDMQZ256rmk:
4943 case VPBLENDMQZ256rmkz:
4944 case VPBLENDMQZ256rr:
4945 case VPBLENDMQZ256rrk:
4946 case VPBLENDMQZ256rrkz:
4947 case VPBLENDMQZrm:
4948 case VPBLENDMQZrmb:
4949 case VPBLENDMQZrmbk:
4950 case VPBLENDMQZrmbkz:
4951 case VPBLENDMQZrmk:
4952 case VPBLENDMQZrmkz:
4953 case VPBLENDMQZrr:
4954 case VPBLENDMQZrrk:
4955 case VPBLENDMQZrrkz:
4956 return true;
4957 }
4958 return false;
4959}
4960
4961bool isVGATHERDPS(unsigned Opcode) {
4962 switch (Opcode) {
4963 case VGATHERDPSYrm:
4964 case VGATHERDPSZ128rm:
4965 case VGATHERDPSZ256rm:
4966 case VGATHERDPSZrm:
4967 case VGATHERDPSrm:
4968 return true;
4969 }
4970 return false;
4971}
4972
4973bool isSYSRET(unsigned Opcode) {
4974 return Opcode == SYSRET;
4975}
4976
4977bool isVPADDB(unsigned Opcode) {
4978 switch (Opcode) {
4979 case VPADDBYrm:
4980 case VPADDBYrr:
4981 case VPADDBZ128rm:
4982 case VPADDBZ128rmk:
4983 case VPADDBZ128rmkz:
4984 case VPADDBZ128rr:
4985 case VPADDBZ128rrk:
4986 case VPADDBZ128rrkz:
4987 case VPADDBZ256rm:
4988 case VPADDBZ256rmk:
4989 case VPADDBZ256rmkz:
4990 case VPADDBZ256rr:
4991 case VPADDBZ256rrk:
4992 case VPADDBZ256rrkz:
4993 case VPADDBZrm:
4994 case VPADDBZrmk:
4995 case VPADDBZrmkz:
4996 case VPADDBZrr:
4997 case VPADDBZrrk:
4998 case VPADDBZrrkz:
4999 case VPADDBrm:
5000 case VPADDBrr:
5001 return true;
5002 }
5003 return false;
5004}
5005
5006bool isXEND(unsigned Opcode) {
5007 return Opcode == XEND;
5008}
5009
5010bool isWRSSD(unsigned Opcode) {
5011 switch (Opcode) {
5012 case WRSSD:
5013 case WRSSD_EVEX:
5014 return true;
5015 }
5016 return false;
5017}
5018
5019bool isVMINMAXSS(unsigned Opcode) {
5020 switch (Opcode) {
5021 case VMINMAXSSrmi_Int:
5022 case VMINMAXSSrmik_Int:
5023 case VMINMAXSSrmikz_Int:
5024 case VMINMAXSSrri_Int:
5025 case VMINMAXSSrrib_Int:
5026 case VMINMAXSSrribk_Int:
5027 case VMINMAXSSrribkz_Int:
5028 case VMINMAXSSrrik_Int:
5029 case VMINMAXSSrrikz_Int:
5030 return true;
5031 }
5032 return false;
5033}
5034
5035bool isVCVTDQ2PH(unsigned Opcode) {
5036 switch (Opcode) {
5037 case VCVTDQ2PHZ128rm:
5038 case VCVTDQ2PHZ128rmb:
5039 case VCVTDQ2PHZ128rmbk:
5040 case VCVTDQ2PHZ128rmbkz:
5041 case VCVTDQ2PHZ128rmk:
5042 case VCVTDQ2PHZ128rmkz:
5043 case VCVTDQ2PHZ128rr:
5044 case VCVTDQ2PHZ128rrk:
5045 case VCVTDQ2PHZ128rrkz:
5046 case VCVTDQ2PHZ256rm:
5047 case VCVTDQ2PHZ256rmb:
5048 case VCVTDQ2PHZ256rmbk:
5049 case VCVTDQ2PHZ256rmbkz:
5050 case VCVTDQ2PHZ256rmk:
5051 case VCVTDQ2PHZ256rmkz:
5052 case VCVTDQ2PHZ256rr:
5053 case VCVTDQ2PHZ256rrk:
5054 case VCVTDQ2PHZ256rrkz:
5055 case VCVTDQ2PHZrm:
5056 case VCVTDQ2PHZrmb:
5057 case VCVTDQ2PHZrmbk:
5058 case VCVTDQ2PHZrmbkz:
5059 case VCVTDQ2PHZrmk:
5060 case VCVTDQ2PHZrmkz:
5061 case VCVTDQ2PHZrr:
5062 case VCVTDQ2PHZrrb:
5063 case VCVTDQ2PHZrrbk:
5064 case VCVTDQ2PHZrrbkz:
5065 case VCVTDQ2PHZrrk:
5066 case VCVTDQ2PHZrrkz:
5067 return true;
5068 }
5069 return false;
5070}
5071
5072bool isCVTPD2PS(unsigned Opcode) {
5073 switch (Opcode) {
5074 case CVTPD2PSrm:
5075 case CVTPD2PSrr:
5076 return true;
5077 }
5078 return false;
5079}
5080
5081bool isMAXPD(unsigned Opcode) {
5082 switch (Opcode) {
5083 case MAXPDrm:
5084 case MAXPDrr:
5085 return true;
5086 }
5087 return false;
5088}
5089
5090bool isRCPSS(unsigned Opcode) {
5091 switch (Opcode) {
5092 case RCPSSm_Int:
5093 case RCPSSr_Int:
5094 return true;
5095 }
5096 return false;
5097}
5098
5099bool isVMOVAPD(unsigned Opcode) {
5100 switch (Opcode) {
5101 case VMOVAPDYmr:
5102 case VMOVAPDYrm:
5103 case VMOVAPDYrr:
5104 case VMOVAPDYrr_REV:
5105 case VMOVAPDZ128mr:
5106 case VMOVAPDZ128mrk:
5107 case VMOVAPDZ128rm:
5108 case VMOVAPDZ128rmk:
5109 case VMOVAPDZ128rmkz:
5110 case VMOVAPDZ128rr:
5111 case VMOVAPDZ128rr_REV:
5112 case VMOVAPDZ128rrk:
5113 case VMOVAPDZ128rrk_REV:
5114 case VMOVAPDZ128rrkz:
5115 case VMOVAPDZ128rrkz_REV:
5116 case VMOVAPDZ256mr:
5117 case VMOVAPDZ256mrk:
5118 case VMOVAPDZ256rm:
5119 case VMOVAPDZ256rmk:
5120 case VMOVAPDZ256rmkz:
5121 case VMOVAPDZ256rr:
5122 case VMOVAPDZ256rr_REV:
5123 case VMOVAPDZ256rrk:
5124 case VMOVAPDZ256rrk_REV:
5125 case VMOVAPDZ256rrkz:
5126 case VMOVAPDZ256rrkz_REV:
5127 case VMOVAPDZmr:
5128 case VMOVAPDZmrk:
5129 case VMOVAPDZrm:
5130 case VMOVAPDZrmk:
5131 case VMOVAPDZrmkz:
5132 case VMOVAPDZrr:
5133 case VMOVAPDZrr_REV:
5134 case VMOVAPDZrrk:
5135 case VMOVAPDZrrk_REV:
5136 case VMOVAPDZrrkz:
5137 case VMOVAPDZrrkz_REV:
5138 case VMOVAPDmr:
5139 case VMOVAPDrm:
5140 case VMOVAPDrr:
5141 case VMOVAPDrr_REV:
5142 return true;
5143 }
5144 return false;
5145}
5146
5147bool isVPSUBSB(unsigned Opcode) {
5148 switch (Opcode) {
5149 case VPSUBSBYrm:
5150 case VPSUBSBYrr:
5151 case VPSUBSBZ128rm:
5152 case VPSUBSBZ128rmk:
5153 case VPSUBSBZ128rmkz:
5154 case VPSUBSBZ128rr:
5155 case VPSUBSBZ128rrk:
5156 case VPSUBSBZ128rrkz:
5157 case VPSUBSBZ256rm:
5158 case VPSUBSBZ256rmk:
5159 case VPSUBSBZ256rmkz:
5160 case VPSUBSBZ256rr:
5161 case VPSUBSBZ256rrk:
5162 case VPSUBSBZ256rrkz:
5163 case VPSUBSBZrm:
5164 case VPSUBSBZrmk:
5165 case VPSUBSBZrmkz:
5166 case VPSUBSBZrr:
5167 case VPSUBSBZrrk:
5168 case VPSUBSBZrrkz:
5169 case VPSUBSBrm:
5170 case VPSUBSBrr:
5171 return true;
5172 }
5173 return false;
5174}
5175
5176bool isRDTSC(unsigned Opcode) {
5177 return Opcode == RDTSC;
5178}
5179
5180bool isVCVTTPS2UDQS(unsigned Opcode) {
5181 switch (Opcode) {
5182 case VCVTTPS2UDQSZ128rm:
5183 case VCVTTPS2UDQSZ128rmb:
5184 case VCVTTPS2UDQSZ128rmbk:
5185 case VCVTTPS2UDQSZ128rmbkz:
5186 case VCVTTPS2UDQSZ128rmk:
5187 case VCVTTPS2UDQSZ128rmkz:
5188 case VCVTTPS2UDQSZ128rr:
5189 case VCVTTPS2UDQSZ128rrk:
5190 case VCVTTPS2UDQSZ128rrkz:
5191 case VCVTTPS2UDQSZ256rm:
5192 case VCVTTPS2UDQSZ256rmb:
5193 case VCVTTPS2UDQSZ256rmbk:
5194 case VCVTTPS2UDQSZ256rmbkz:
5195 case VCVTTPS2UDQSZ256rmk:
5196 case VCVTTPS2UDQSZ256rmkz:
5197 case VCVTTPS2UDQSZ256rr:
5198 case VCVTTPS2UDQSZ256rrk:
5199 case VCVTTPS2UDQSZ256rrkz:
5200 case VCVTTPS2UDQSZrm:
5201 case VCVTTPS2UDQSZrmb:
5202 case VCVTTPS2UDQSZrmbk:
5203 case VCVTTPS2UDQSZrmbkz:
5204 case VCVTTPS2UDQSZrmk:
5205 case VCVTTPS2UDQSZrmkz:
5206 case VCVTTPS2UDQSZrr:
5207 case VCVTTPS2UDQSZrrb:
5208 case VCVTTPS2UDQSZrrbk:
5209 case VCVTTPS2UDQSZrrbkz:
5210 case VCVTTPS2UDQSZrrk:
5211 case VCVTTPS2UDQSZrrkz:
5212 return true;
5213 }
5214 return false;
5215}
5216
5217bool isVPMADCSSWD(unsigned Opcode) {
5218 switch (Opcode) {
5219 case VPMADCSSWDrm:
5220 case VPMADCSSWDrr:
5221 return true;
5222 }
5223 return false;
5224}
5225
5226bool isVFNMADD213PH(unsigned Opcode) {
5227 switch (Opcode) {
5228 case VFNMADD213PHZ128m:
5229 case VFNMADD213PHZ128mb:
5230 case VFNMADD213PHZ128mbk:
5231 case VFNMADD213PHZ128mbkz:
5232 case VFNMADD213PHZ128mk:
5233 case VFNMADD213PHZ128mkz:
5234 case VFNMADD213PHZ128r:
5235 case VFNMADD213PHZ128rk:
5236 case VFNMADD213PHZ128rkz:
5237 case VFNMADD213PHZ256m:
5238 case VFNMADD213PHZ256mb:
5239 case VFNMADD213PHZ256mbk:
5240 case VFNMADD213PHZ256mbkz:
5241 case VFNMADD213PHZ256mk:
5242 case VFNMADD213PHZ256mkz:
5243 case VFNMADD213PHZ256r:
5244 case VFNMADD213PHZ256rk:
5245 case VFNMADD213PHZ256rkz:
5246 case VFNMADD213PHZm:
5247 case VFNMADD213PHZmb:
5248 case VFNMADD213PHZmbk:
5249 case VFNMADD213PHZmbkz:
5250 case VFNMADD213PHZmk:
5251 case VFNMADD213PHZmkz:
5252 case VFNMADD213PHZr:
5253 case VFNMADD213PHZrb:
5254 case VFNMADD213PHZrbk:
5255 case VFNMADD213PHZrbkz:
5256 case VFNMADD213PHZrk:
5257 case VFNMADD213PHZrkz:
5258 return true;
5259 }
5260 return false;
5261}
5262
5263bool isVGF2P8AFFINEQB(unsigned Opcode) {
5264 switch (Opcode) {
5265 case VGF2P8AFFINEQBYrmi:
5266 case VGF2P8AFFINEQBYrri:
5267 case VGF2P8AFFINEQBZ128rmbi:
5268 case VGF2P8AFFINEQBZ128rmbik:
5269 case VGF2P8AFFINEQBZ128rmbikz:
5270 case VGF2P8AFFINEQBZ128rmi:
5271 case VGF2P8AFFINEQBZ128rmik:
5272 case VGF2P8AFFINEQBZ128rmikz:
5273 case VGF2P8AFFINEQBZ128rri:
5274 case VGF2P8AFFINEQBZ128rrik:
5275 case VGF2P8AFFINEQBZ128rrikz:
5276 case VGF2P8AFFINEQBZ256rmbi:
5277 case VGF2P8AFFINEQBZ256rmbik:
5278 case VGF2P8AFFINEQBZ256rmbikz:
5279 case VGF2P8AFFINEQBZ256rmi:
5280 case VGF2P8AFFINEQBZ256rmik:
5281 case VGF2P8AFFINEQBZ256rmikz:
5282 case VGF2P8AFFINEQBZ256rri:
5283 case VGF2P8AFFINEQBZ256rrik:
5284 case VGF2P8AFFINEQBZ256rrikz:
5285 case VGF2P8AFFINEQBZrmbi:
5286 case VGF2P8AFFINEQBZrmbik:
5287 case VGF2P8AFFINEQBZrmbikz:
5288 case VGF2P8AFFINEQBZrmi:
5289 case VGF2P8AFFINEQBZrmik:
5290 case VGF2P8AFFINEQBZrmikz:
5291 case VGF2P8AFFINEQBZrri:
5292 case VGF2P8AFFINEQBZrrik:
5293 case VGF2P8AFFINEQBZrrikz:
5294 case VGF2P8AFFINEQBrmi:
5295 case VGF2P8AFFINEQBrri:
5296 return true;
5297 }
5298 return false;
5299}
5300
5301bool isPMOVZXWD(unsigned Opcode) {
5302 switch (Opcode) {
5303 case PMOVZXWDrm:
5304 case PMOVZXWDrr:
5305 return true;
5306 }
5307 return false;
5308}
5309
5310bool isPMINUD(unsigned Opcode) {
5311 switch (Opcode) {
5312 case PMINUDrm:
5313 case PMINUDrr:
5314 return true;
5315 }
5316 return false;
5317}
5318
5319bool isVCVTPH2UW(unsigned Opcode) {
5320 switch (Opcode) {
5321 case VCVTPH2UWZ128rm:
5322 case VCVTPH2UWZ128rmb:
5323 case VCVTPH2UWZ128rmbk:
5324 case VCVTPH2UWZ128rmbkz:
5325 case VCVTPH2UWZ128rmk:
5326 case VCVTPH2UWZ128rmkz:
5327 case VCVTPH2UWZ128rr:
5328 case VCVTPH2UWZ128rrk:
5329 case VCVTPH2UWZ128rrkz:
5330 case VCVTPH2UWZ256rm:
5331 case VCVTPH2UWZ256rmb:
5332 case VCVTPH2UWZ256rmbk:
5333 case VCVTPH2UWZ256rmbkz:
5334 case VCVTPH2UWZ256rmk:
5335 case VCVTPH2UWZ256rmkz:
5336 case VCVTPH2UWZ256rr:
5337 case VCVTPH2UWZ256rrk:
5338 case VCVTPH2UWZ256rrkz:
5339 case VCVTPH2UWZrm:
5340 case VCVTPH2UWZrmb:
5341 case VCVTPH2UWZrmbk:
5342 case VCVTPH2UWZrmbkz:
5343 case VCVTPH2UWZrmk:
5344 case VCVTPH2UWZrmkz:
5345 case VCVTPH2UWZrr:
5346 case VCVTPH2UWZrrb:
5347 case VCVTPH2UWZrrbk:
5348 case VCVTPH2UWZrrbkz:
5349 case VCVTPH2UWZrrk:
5350 case VCVTPH2UWZrrkz:
5351 return true;
5352 }
5353 return false;
5354}
5355
5356bool isPADDSW(unsigned Opcode) {
5357 switch (Opcode) {
5358 case MMX_PADDSWrm:
5359 case MMX_PADDSWrr:
5360 case PADDSWrm:
5361 case PADDSWrr:
5362 return true;
5363 }
5364 return false;
5365}
5366
5367bool isXSUSLDTRK(unsigned Opcode) {
5368 return Opcode == XSUSLDTRK;
5369}
5370
5371bool isLFENCE(unsigned Opcode) {
5372 return Opcode == LFENCE;
5373}
5374
5375bool isCRC32(unsigned Opcode) {
5376 switch (Opcode) {
5377 case CRC32r32m16:
5378 case CRC32r32m16_EVEX:
5379 case CRC32r32m32:
5380 case CRC32r32m32_EVEX:
5381 case CRC32r32m8:
5382 case CRC32r32m8_EVEX:
5383 case CRC32r32r16:
5384 case CRC32r32r16_EVEX:
5385 case CRC32r32r32:
5386 case CRC32r32r32_EVEX:
5387 case CRC32r32r8:
5388 case CRC32r32r8_EVEX:
5389 case CRC32r64m64:
5390 case CRC32r64m64_EVEX:
5391 case CRC32r64m8:
5392 case CRC32r64m8_EVEX:
5393 case CRC32r64r64:
5394 case CRC32r64r64_EVEX:
5395 case CRC32r64r8:
5396 case CRC32r64r8_EVEX:
5397 return true;
5398 }
5399 return false;
5400}
5401
5402bool isAESENCWIDE256KL(unsigned Opcode) {
5403 return Opcode == AESENCWIDE256KL;
5404}
5405
5406bool isMOVAPD(unsigned Opcode) {
5407 switch (Opcode) {
5408 case MOVAPDmr:
5409 case MOVAPDrm:
5410 case MOVAPDrr:
5411 case MOVAPDrr_REV:
5412 return true;
5413 }
5414 return false;
5415}
5416
5417bool isVFMADD213PS(unsigned Opcode) {
5418 switch (Opcode) {
5419 case VFMADD213PSYm:
5420 case VFMADD213PSYr:
5421 case VFMADD213PSZ128m:
5422 case VFMADD213PSZ128mb:
5423 case VFMADD213PSZ128mbk:
5424 case VFMADD213PSZ128mbkz:
5425 case VFMADD213PSZ128mk:
5426 case VFMADD213PSZ128mkz:
5427 case VFMADD213PSZ128r:
5428 case VFMADD213PSZ128rk:
5429 case VFMADD213PSZ128rkz:
5430 case VFMADD213PSZ256m:
5431 case VFMADD213PSZ256mb:
5432 case VFMADD213PSZ256mbk:
5433 case VFMADD213PSZ256mbkz:
5434 case VFMADD213PSZ256mk:
5435 case VFMADD213PSZ256mkz:
5436 case VFMADD213PSZ256r:
5437 case VFMADD213PSZ256rk:
5438 case VFMADD213PSZ256rkz:
5439 case VFMADD213PSZm:
5440 case VFMADD213PSZmb:
5441 case VFMADD213PSZmbk:
5442 case VFMADD213PSZmbkz:
5443 case VFMADD213PSZmk:
5444 case VFMADD213PSZmkz:
5445 case VFMADD213PSZr:
5446 case VFMADD213PSZrb:
5447 case VFMADD213PSZrbk:
5448 case VFMADD213PSZrbkz:
5449 case VFMADD213PSZrk:
5450 case VFMADD213PSZrkz:
5451 case VFMADD213PSm:
5452 case VFMADD213PSr:
5453 return true;
5454 }
5455 return false;
5456}
5457
5458bool isVPDPWUUDS(unsigned Opcode) {
5459 switch (Opcode) {
5460 case VPDPWUUDSYrm:
5461 case VPDPWUUDSYrr:
5462 case VPDPWUUDSZ128rm:
5463 case VPDPWUUDSZ128rmb:
5464 case VPDPWUUDSZ128rmbk:
5465 case VPDPWUUDSZ128rmbkz:
5466 case VPDPWUUDSZ128rmk:
5467 case VPDPWUUDSZ128rmkz:
5468 case VPDPWUUDSZ128rr:
5469 case VPDPWUUDSZ128rrk:
5470 case VPDPWUUDSZ128rrkz:
5471 case VPDPWUUDSZ256rm:
5472 case VPDPWUUDSZ256rmb:
5473 case VPDPWUUDSZ256rmbk:
5474 case VPDPWUUDSZ256rmbkz:
5475 case VPDPWUUDSZ256rmk:
5476 case VPDPWUUDSZ256rmkz:
5477 case VPDPWUUDSZ256rr:
5478 case VPDPWUUDSZ256rrk:
5479 case VPDPWUUDSZ256rrkz:
5480 case VPDPWUUDSZrm:
5481 case VPDPWUUDSZrmb:
5482 case VPDPWUUDSZrmbk:
5483 case VPDPWUUDSZrmbkz:
5484 case VPDPWUUDSZrmk:
5485 case VPDPWUUDSZrmkz:
5486 case VPDPWUUDSZrr:
5487 case VPDPWUUDSZrrk:
5488 case VPDPWUUDSZrrkz:
5489 case VPDPWUUDSrm:
5490 case VPDPWUUDSrr:
5491 return true;
5492 }
5493 return false;
5494}
5495
5496bool isMOVSLDUP(unsigned Opcode) {
5497 switch (Opcode) {
5498 case MOVSLDUPrm:
5499 case MOVSLDUPrr:
5500 return true;
5501 }
5502 return false;
5503}
5504
5505bool isCLDEMOTE(unsigned Opcode) {
5506 return Opcode == CLDEMOTE;
5507}
5508
5509bool isVFNMADD231PS(unsigned Opcode) {
5510 switch (Opcode) {
5511 case VFNMADD231PSYm:
5512 case VFNMADD231PSYr:
5513 case VFNMADD231PSZ128m:
5514 case VFNMADD231PSZ128mb:
5515 case VFNMADD231PSZ128mbk:
5516 case VFNMADD231PSZ128mbkz:
5517 case VFNMADD231PSZ128mk:
5518 case VFNMADD231PSZ128mkz:
5519 case VFNMADD231PSZ128r:
5520 case VFNMADD231PSZ128rk:
5521 case VFNMADD231PSZ128rkz:
5522 case VFNMADD231PSZ256m:
5523 case VFNMADD231PSZ256mb:
5524 case VFNMADD231PSZ256mbk:
5525 case VFNMADD231PSZ256mbkz:
5526 case VFNMADD231PSZ256mk:
5527 case VFNMADD231PSZ256mkz:
5528 case VFNMADD231PSZ256r:
5529 case VFNMADD231PSZ256rk:
5530 case VFNMADD231PSZ256rkz:
5531 case VFNMADD231PSZm:
5532 case VFNMADD231PSZmb:
5533 case VFNMADD231PSZmbk:
5534 case VFNMADD231PSZmbkz:
5535 case VFNMADD231PSZmk:
5536 case VFNMADD231PSZmkz:
5537 case VFNMADD231PSZr:
5538 case VFNMADD231PSZrb:
5539 case VFNMADD231PSZrbk:
5540 case VFNMADD231PSZrbkz:
5541 case VFNMADD231PSZrk:
5542 case VFNMADD231PSZrkz:
5543 case VFNMADD231PSm:
5544 case VFNMADD231PSr:
5545 return true;
5546 }
5547 return false;
5548}
5549
5550bool isVMOVMSKPD(unsigned Opcode) {
5551 switch (Opcode) {
5552 case VMOVMSKPDYrr:
5553 case VMOVMSKPDrr:
5554 return true;
5555 }
5556 return false;
5557}
5558
5559bool isPREFETCHT0(unsigned Opcode) {
5560 return Opcode == PREFETCHT0;
5561}
5562
5563bool isVCVTNEOBF162PS(unsigned Opcode) {
5564 switch (Opcode) {
5565 case VCVTNEOBF162PSYrm:
5566 case VCVTNEOBF162PSrm:
5567 return true;
5568 }
5569 return false;
5570}
5571
5572bool isVPCMPUD(unsigned Opcode) {
5573 switch (Opcode) {
5574 case VPCMPUDZ128rmbi:
5575 case VPCMPUDZ128rmbik:
5576 case VPCMPUDZ128rmi:
5577 case VPCMPUDZ128rmik:
5578 case VPCMPUDZ128rri:
5579 case VPCMPUDZ128rrik:
5580 case VPCMPUDZ256rmbi:
5581 case VPCMPUDZ256rmbik:
5582 case VPCMPUDZ256rmi:
5583 case VPCMPUDZ256rmik:
5584 case VPCMPUDZ256rri:
5585 case VPCMPUDZ256rrik:
5586 case VPCMPUDZrmbi:
5587 case VPCMPUDZrmbik:
5588 case VPCMPUDZrmi:
5589 case VPCMPUDZrmik:
5590 case VPCMPUDZrri:
5591 case VPCMPUDZrrik:
5592 return true;
5593 }
5594 return false;
5595}
5596
5597bool isVMAXSD(unsigned Opcode) {
5598 switch (Opcode) {
5599 case VMAXSDZrm_Int:
5600 case VMAXSDZrmk_Int:
5601 case VMAXSDZrmkz_Int:
5602 case VMAXSDZrr_Int:
5603 case VMAXSDZrrb_Int:
5604 case VMAXSDZrrbk_Int:
5605 case VMAXSDZrrbkz_Int:
5606 case VMAXSDZrrk_Int:
5607 case VMAXSDZrrkz_Int:
5608 case VMAXSDrm_Int:
5609 case VMAXSDrr_Int:
5610 return true;
5611 }
5612 return false;
5613}
5614
5615bool isVRCP28SD(unsigned Opcode) {
5616 switch (Opcode) {
5617 case VRCP28SDZm:
5618 case VRCP28SDZmk:
5619 case VRCP28SDZmkz:
5620 case VRCP28SDZr:
5621 case VRCP28SDZrb:
5622 case VRCP28SDZrbk:
5623 case VRCP28SDZrbkz:
5624 case VRCP28SDZrk:
5625 case VRCP28SDZrkz:
5626 return true;
5627 }
5628 return false;
5629}
5630
5631bool isVMAXPS(unsigned Opcode) {
5632 switch (Opcode) {
5633 case VMAXPSYrm:
5634 case VMAXPSYrr:
5635 case VMAXPSZ128rm:
5636 case VMAXPSZ128rmb:
5637 case VMAXPSZ128rmbk:
5638 case VMAXPSZ128rmbkz:
5639 case VMAXPSZ128rmk:
5640 case VMAXPSZ128rmkz:
5641 case VMAXPSZ128rr:
5642 case VMAXPSZ128rrk:
5643 case VMAXPSZ128rrkz:
5644 case VMAXPSZ256rm:
5645 case VMAXPSZ256rmb:
5646 case VMAXPSZ256rmbk:
5647 case VMAXPSZ256rmbkz:
5648 case VMAXPSZ256rmk:
5649 case VMAXPSZ256rmkz:
5650 case VMAXPSZ256rr:
5651 case VMAXPSZ256rrk:
5652 case VMAXPSZ256rrkz:
5653 case VMAXPSZrm:
5654 case VMAXPSZrmb:
5655 case VMAXPSZrmbk:
5656 case VMAXPSZrmbkz:
5657 case VMAXPSZrmk:
5658 case VMAXPSZrmkz:
5659 case VMAXPSZrr:
5660 case VMAXPSZrrb:
5661 case VMAXPSZrrbk:
5662 case VMAXPSZrrbkz:
5663 case VMAXPSZrrk:
5664 case VMAXPSZrrkz:
5665 case VMAXPSrm:
5666 case VMAXPSrr:
5667 return true;
5668 }
5669 return false;
5670}
5671
5672bool isVPMOVD2M(unsigned Opcode) {
5673 switch (Opcode) {
5674 case VPMOVD2MZ128kr:
5675 case VPMOVD2MZ256kr:
5676 case VPMOVD2MZkr:
5677 return true;
5678 }
5679 return false;
5680}
5681
5682bool isVPMACSSWD(unsigned Opcode) {
5683 switch (Opcode) {
5684 case VPMACSSWDrm:
5685 case VPMACSSWDrr:
5686 return true;
5687 }
5688 return false;
5689}
5690
5691bool isVUCOMISD(unsigned Opcode) {
5692 switch (Opcode) {
5693 case VUCOMISDZrm:
5694 case VUCOMISDZrr:
5695 case VUCOMISDZrrb:
5696 case VUCOMISDrm:
5697 case VUCOMISDrr:
5698 return true;
5699 }
5700 return false;
5701}
5702
5703bool isLTR(unsigned Opcode) {
5704 switch (Opcode) {
5705 case LTRm:
5706 case LTRr:
5707 return true;
5708 }
5709 return false;
5710}
5711
5712bool isVCVTUSI2SH(unsigned Opcode) {
5713 switch (Opcode) {
5714 case VCVTUSI2SHZrm_Int:
5715 case VCVTUSI2SHZrr_Int:
5716 case VCVTUSI2SHZrrb_Int:
5717 case VCVTUSI642SHZrm_Int:
5718 case VCVTUSI642SHZrr_Int:
5719 case VCVTUSI642SHZrrb_Int:
5720 return true;
5721 }
5722 return false;
5723}
5724
5725bool isVSCATTERPF1QPS(unsigned Opcode) {
5726 return Opcode == VSCATTERPF1QPSm;
5727}
5728
5729bool isWRGSBASE(unsigned Opcode) {
5730 switch (Opcode) {
5731 case WRGSBASE:
5732 case WRGSBASE64:
5733 return true;
5734 }
5735 return false;
5736}
5737
5738bool isSTOSQ(unsigned Opcode) {
5739 return Opcode == STOSQ;
5740}
5741
5742bool isVSQRTSD(unsigned Opcode) {
5743 switch (Opcode) {
5744 case VSQRTSDZm_Int:
5745 case VSQRTSDZmk_Int:
5746 case VSQRTSDZmkz_Int:
5747 case VSQRTSDZr_Int:
5748 case VSQRTSDZrb_Int:
5749 case VSQRTSDZrbk_Int:
5750 case VSQRTSDZrbkz_Int:
5751 case VSQRTSDZrk_Int:
5752 case VSQRTSDZrkz_Int:
5753 case VSQRTSDm_Int:
5754 case VSQRTSDr_Int:
5755 return true;
5756 }
5757 return false;
5758}
5759
5760bool isVPERMIL2PD(unsigned Opcode) {
5761 switch (Opcode) {
5762 case VPERMIL2PDYmr:
5763 case VPERMIL2PDYrm:
5764 case VPERMIL2PDYrr:
5765 case VPERMIL2PDYrr_REV:
5766 case VPERMIL2PDmr:
5767 case VPERMIL2PDrm:
5768 case VPERMIL2PDrr:
5769 case VPERMIL2PDrr_REV:
5770 return true;
5771 }
5772 return false;
5773}
5774
5775bool isVFCMADDCSH(unsigned Opcode) {
5776 switch (Opcode) {
5777 case VFCMADDCSHZm:
5778 case VFCMADDCSHZmk:
5779 case VFCMADDCSHZmkz:
5780 case VFCMADDCSHZr:
5781 case VFCMADDCSHZrb:
5782 case VFCMADDCSHZrbk:
5783 case VFCMADDCSHZrbkz:
5784 case VFCMADDCSHZrk:
5785 case VFCMADDCSHZrkz:
5786 return true;
5787 }
5788 return false;
5789}
5790
5791bool isVFMADDSUB213PS(unsigned Opcode) {
5792 switch (Opcode) {
5793 case VFMADDSUB213PSYm:
5794 case VFMADDSUB213PSYr:
5795 case VFMADDSUB213PSZ128m:
5796 case VFMADDSUB213PSZ128mb:
5797 case VFMADDSUB213PSZ128mbk:
5798 case VFMADDSUB213PSZ128mbkz:
5799 case VFMADDSUB213PSZ128mk:
5800 case VFMADDSUB213PSZ128mkz:
5801 case VFMADDSUB213PSZ128r:
5802 case VFMADDSUB213PSZ128rk:
5803 case VFMADDSUB213PSZ128rkz:
5804 case VFMADDSUB213PSZ256m:
5805 case VFMADDSUB213PSZ256mb:
5806 case VFMADDSUB213PSZ256mbk:
5807 case VFMADDSUB213PSZ256mbkz:
5808 case VFMADDSUB213PSZ256mk:
5809 case VFMADDSUB213PSZ256mkz:
5810 case VFMADDSUB213PSZ256r:
5811 case VFMADDSUB213PSZ256rk:
5812 case VFMADDSUB213PSZ256rkz:
5813 case VFMADDSUB213PSZm:
5814 case VFMADDSUB213PSZmb:
5815 case VFMADDSUB213PSZmbk:
5816 case VFMADDSUB213PSZmbkz:
5817 case VFMADDSUB213PSZmk:
5818 case VFMADDSUB213PSZmkz:
5819 case VFMADDSUB213PSZr:
5820 case VFMADDSUB213PSZrb:
5821 case VFMADDSUB213PSZrbk:
5822 case VFMADDSUB213PSZrbkz:
5823 case VFMADDSUB213PSZrk:
5824 case VFMADDSUB213PSZrkz:
5825 case VFMADDSUB213PSm:
5826 case VFMADDSUB213PSr:
5827 return true;
5828 }
5829 return false;
5830}
5831
5832bool isPFSUB(unsigned Opcode) {
5833 switch (Opcode) {
5834 case PFSUBrm:
5835 case PFSUBrr:
5836 return true;
5837 }
5838 return false;
5839}
5840
5841bool isVSQRTSS(unsigned Opcode) {
5842 switch (Opcode) {
5843 case VSQRTSSZm_Int:
5844 case VSQRTSSZmk_Int:
5845 case VSQRTSSZmkz_Int:
5846 case VSQRTSSZr_Int:
5847 case VSQRTSSZrb_Int:
5848 case VSQRTSSZrbk_Int:
5849 case VSQRTSSZrbkz_Int:
5850 case VSQRTSSZrk_Int:
5851 case VSQRTSSZrkz_Int:
5852 case VSQRTSSm_Int:
5853 case VSQRTSSr_Int:
5854 return true;
5855 }
5856 return false;
5857}
5858
5859bool isVEXPANDPS(unsigned Opcode) {
5860 switch (Opcode) {
5861 case VEXPANDPSZ128rm:
5862 case VEXPANDPSZ128rmk:
5863 case VEXPANDPSZ128rmkz:
5864 case VEXPANDPSZ128rr:
5865 case VEXPANDPSZ128rrk:
5866 case VEXPANDPSZ128rrkz:
5867 case VEXPANDPSZ256rm:
5868 case VEXPANDPSZ256rmk:
5869 case VEXPANDPSZ256rmkz:
5870 case VEXPANDPSZ256rr:
5871 case VEXPANDPSZ256rrk:
5872 case VEXPANDPSZ256rrkz:
5873 case VEXPANDPSZrm:
5874 case VEXPANDPSZrmk:
5875 case VEXPANDPSZrmkz:
5876 case VEXPANDPSZrr:
5877 case VEXPANDPSZrrk:
5878 case VEXPANDPSZrrkz:
5879 return true;
5880 }
5881 return false;
5882}
5883
5884bool isVPCOMPRESSW(unsigned Opcode) {
5885 switch (Opcode) {
5886 case VPCOMPRESSWZ128mr:
5887 case VPCOMPRESSWZ128mrk:
5888 case VPCOMPRESSWZ128rr:
5889 case VPCOMPRESSWZ128rrk:
5890 case VPCOMPRESSWZ128rrkz:
5891 case VPCOMPRESSWZ256mr:
5892 case VPCOMPRESSWZ256mrk:
5893 case VPCOMPRESSWZ256rr:
5894 case VPCOMPRESSWZ256rrk:
5895 case VPCOMPRESSWZ256rrkz:
5896 case VPCOMPRESSWZmr:
5897 case VPCOMPRESSWZmrk:
5898 case VPCOMPRESSWZrr:
5899 case VPCOMPRESSWZrrk:
5900 case VPCOMPRESSWZrrkz:
5901 return true;
5902 }
5903 return false;
5904}
5905
5906bool isPEXTRD(unsigned Opcode) {
5907 switch (Opcode) {
5908 case PEXTRDmri:
5909 case PEXTRDrri:
5910 return true;
5911 }
5912 return false;
5913}
5914
5915bool isVCVTTPS2UQQS(unsigned Opcode) {
5916 switch (Opcode) {
5917 case VCVTTPS2UQQSZ128rm:
5918 case VCVTTPS2UQQSZ128rmb:
5919 case VCVTTPS2UQQSZ128rmbk:
5920 case VCVTTPS2UQQSZ128rmbkz:
5921 case VCVTTPS2UQQSZ128rmk:
5922 case VCVTTPS2UQQSZ128rmkz:
5923 case VCVTTPS2UQQSZ128rr:
5924 case VCVTTPS2UQQSZ128rrk:
5925 case VCVTTPS2UQQSZ128rrkz:
5926 case VCVTTPS2UQQSZ256rm:
5927 case VCVTTPS2UQQSZ256rmb:
5928 case VCVTTPS2UQQSZ256rmbk:
5929 case VCVTTPS2UQQSZ256rmbkz:
5930 case VCVTTPS2UQQSZ256rmk:
5931 case VCVTTPS2UQQSZ256rmkz:
5932 case VCVTTPS2UQQSZ256rr:
5933 case VCVTTPS2UQQSZ256rrb:
5934 case VCVTTPS2UQQSZ256rrbk:
5935 case VCVTTPS2UQQSZ256rrbkz:
5936 case VCVTTPS2UQQSZ256rrk:
5937 case VCVTTPS2UQQSZ256rrkz:
5938 case VCVTTPS2UQQSZrm:
5939 case VCVTTPS2UQQSZrmb:
5940 case VCVTTPS2UQQSZrmbk:
5941 case VCVTTPS2UQQSZrmbkz:
5942 case VCVTTPS2UQQSZrmk:
5943 case VCVTTPS2UQQSZrmkz:
5944 case VCVTTPS2UQQSZrr:
5945 case VCVTTPS2UQQSZrrb:
5946 case VCVTTPS2UQQSZrrbk:
5947 case VCVTTPS2UQQSZrrbkz:
5948 case VCVTTPS2UQQSZrrk:
5949 case VCVTTPS2UQQSZrrkz:
5950 return true;
5951 }
5952 return false;
5953}
5954
5955bool isSYSEXITQ(unsigned Opcode) {
5956 return Opcode == SYSEXIT64;
5957}
5958
5959bool isROUNDSD(unsigned Opcode) {
5960 switch (Opcode) {
5961 case ROUNDSDmi_Int:
5962 case ROUNDSDri_Int:
5963 return true;
5964 }
5965 return false;
5966}
5967
5968bool isVFMADD132BF16(unsigned Opcode) {
5969 switch (Opcode) {
5970 case VFMADD132BF16Z128m:
5971 case VFMADD132BF16Z128mb:
5972 case VFMADD132BF16Z128mbk:
5973 case VFMADD132BF16Z128mbkz:
5974 case VFMADD132BF16Z128mk:
5975 case VFMADD132BF16Z128mkz:
5976 case VFMADD132BF16Z128r:
5977 case VFMADD132BF16Z128rk:
5978 case VFMADD132BF16Z128rkz:
5979 case VFMADD132BF16Z256m:
5980 case VFMADD132BF16Z256mb:
5981 case VFMADD132BF16Z256mbk:
5982 case VFMADD132BF16Z256mbkz:
5983 case VFMADD132BF16Z256mk:
5984 case VFMADD132BF16Z256mkz:
5985 case VFMADD132BF16Z256r:
5986 case VFMADD132BF16Z256rk:
5987 case VFMADD132BF16Z256rkz:
5988 case VFMADD132BF16Zm:
5989 case VFMADD132BF16Zmb:
5990 case VFMADD132BF16Zmbk:
5991 case VFMADD132BF16Zmbkz:
5992 case VFMADD132BF16Zmk:
5993 case VFMADD132BF16Zmkz:
5994 case VFMADD132BF16Zr:
5995 case VFMADD132BF16Zrk:
5996 case VFMADD132BF16Zrkz:
5997 return true;
5998 }
5999 return false;
6000}
6001
6002bool isFCOM(unsigned Opcode) {
6003 switch (Opcode) {
6004 case COM_FST0r:
6005 case FCOM32m:
6006 case FCOM64m:
6007 return true;
6008 }
6009 return false;
6010}
6011
6012bool isVFNMSUBSS(unsigned Opcode) {
6013 switch (Opcode) {
6014 case VFNMSUBSS4mr:
6015 case VFNMSUBSS4rm:
6016 case VFNMSUBSS4rr:
6017 case VFNMSUBSS4rr_REV:
6018 return true;
6019 }
6020 return false;
6021}
6022
6023bool isKSHIFTLW(unsigned Opcode) {
6024 return Opcode == KSHIFTLWki;
6025}
6026
6027bool isSCASD(unsigned Opcode) {
6028 return Opcode == SCASL;
6029}
6030
6031bool isVMPTRLD(unsigned Opcode) {
6032 return Opcode == VMPTRLDm;
6033}
6034
6035bool isVAESDECLAST(unsigned Opcode) {
6036 switch (Opcode) {
6037 case VAESDECLASTYrm:
6038 case VAESDECLASTYrr:
6039 case VAESDECLASTZ128rm:
6040 case VAESDECLASTZ128rr:
6041 case VAESDECLASTZ256rm:
6042 case VAESDECLASTZ256rr:
6043 case VAESDECLASTZrm:
6044 case VAESDECLASTZrr:
6045 case VAESDECLASTrm:
6046 case VAESDECLASTrr:
6047 return true;
6048 }
6049 return false;
6050}
6051
6052bool isVFMADDSUBPS(unsigned Opcode) {
6053 switch (Opcode) {
6054 case VFMADDSUBPS4Ymr:
6055 case VFMADDSUBPS4Yrm:
6056 case VFMADDSUBPS4Yrr:
6057 case VFMADDSUBPS4Yrr_REV:
6058 case VFMADDSUBPS4mr:
6059 case VFMADDSUBPS4rm:
6060 case VFMADDSUBPS4rr:
6061 case VFMADDSUBPS4rr_REV:
6062 return true;
6063 }
6064 return false;
6065}
6066
6067bool isVCVTUQQ2PS(unsigned Opcode) {
6068 switch (Opcode) {
6069 case VCVTUQQ2PSZ128rm:
6070 case VCVTUQQ2PSZ128rmb:
6071 case VCVTUQQ2PSZ128rmbk:
6072 case VCVTUQQ2PSZ128rmbkz:
6073 case VCVTUQQ2PSZ128rmk:
6074 case VCVTUQQ2PSZ128rmkz:
6075 case VCVTUQQ2PSZ128rr:
6076 case VCVTUQQ2PSZ128rrk:
6077 case VCVTUQQ2PSZ128rrkz:
6078 case VCVTUQQ2PSZ256rm:
6079 case VCVTUQQ2PSZ256rmb:
6080 case VCVTUQQ2PSZ256rmbk:
6081 case VCVTUQQ2PSZ256rmbkz:
6082 case VCVTUQQ2PSZ256rmk:
6083 case VCVTUQQ2PSZ256rmkz:
6084 case VCVTUQQ2PSZ256rr:
6085 case VCVTUQQ2PSZ256rrk:
6086 case VCVTUQQ2PSZ256rrkz:
6087 case VCVTUQQ2PSZrm:
6088 case VCVTUQQ2PSZrmb:
6089 case VCVTUQQ2PSZrmbk:
6090 case VCVTUQQ2PSZrmbkz:
6091 case VCVTUQQ2PSZrmk:
6092 case VCVTUQQ2PSZrmkz:
6093 case VCVTUQQ2PSZrr:
6094 case VCVTUQQ2PSZrrb:
6095 case VCVTUQQ2PSZrrbk:
6096 case VCVTUQQ2PSZrrbkz:
6097 case VCVTUQQ2PSZrrk:
6098 case VCVTUQQ2PSZrrkz:
6099 return true;
6100 }
6101 return false;
6102}
6103
6104bool isVPMOVUSDB(unsigned Opcode) {
6105 switch (Opcode) {
6106 case VPMOVUSDBZ128mr:
6107 case VPMOVUSDBZ128mrk:
6108 case VPMOVUSDBZ128rr:
6109 case VPMOVUSDBZ128rrk:
6110 case VPMOVUSDBZ128rrkz:
6111 case VPMOVUSDBZ256mr:
6112 case VPMOVUSDBZ256mrk:
6113 case VPMOVUSDBZ256rr:
6114 case VPMOVUSDBZ256rrk:
6115 case VPMOVUSDBZ256rrkz:
6116 case VPMOVUSDBZmr:
6117 case VPMOVUSDBZmrk:
6118 case VPMOVUSDBZrr:
6119 case VPMOVUSDBZrrk:
6120 case VPMOVUSDBZrrkz:
6121 return true;
6122 }
6123 return false;
6124}
6125
6126bool isVPROTW(unsigned Opcode) {
6127 switch (Opcode) {
6128 case VPROTWmi:
6129 case VPROTWmr:
6130 case VPROTWri:
6131 case VPROTWrm:
6132 case VPROTWrr:
6133 case VPROTWrr_REV:
6134 return true;
6135 }
6136 return false;
6137}
6138
6139bool isVDPPS(unsigned Opcode) {
6140 switch (Opcode) {
6141 case VDPPSYrmi:
6142 case VDPPSYrri:
6143 case VDPPSrmi:
6144 case VDPPSrri:
6145 return true;
6146 }
6147 return false;
6148}
6149
6150bool isVRSQRT14PD(unsigned Opcode) {
6151 switch (Opcode) {
6152 case VRSQRT14PDZ128m:
6153 case VRSQRT14PDZ128mb:
6154 case VRSQRT14PDZ128mbk:
6155 case VRSQRT14PDZ128mbkz:
6156 case VRSQRT14PDZ128mk:
6157 case VRSQRT14PDZ128mkz:
6158 case VRSQRT14PDZ128r:
6159 case VRSQRT14PDZ128rk:
6160 case VRSQRT14PDZ128rkz:
6161 case VRSQRT14PDZ256m:
6162 case VRSQRT14PDZ256mb:
6163 case VRSQRT14PDZ256mbk:
6164 case VRSQRT14PDZ256mbkz:
6165 case VRSQRT14PDZ256mk:
6166 case VRSQRT14PDZ256mkz:
6167 case VRSQRT14PDZ256r:
6168 case VRSQRT14PDZ256rk:
6169 case VRSQRT14PDZ256rkz:
6170 case VRSQRT14PDZm:
6171 case VRSQRT14PDZmb:
6172 case VRSQRT14PDZmbk:
6173 case VRSQRT14PDZmbkz:
6174 case VRSQRT14PDZmk:
6175 case VRSQRT14PDZmkz:
6176 case VRSQRT14PDZr:
6177 case VRSQRT14PDZrk:
6178 case VRSQRT14PDZrkz:
6179 return true;
6180 }
6181 return false;
6182}
6183
6184bool isVTESTPD(unsigned Opcode) {
6185 switch (Opcode) {
6186 case VTESTPDYrm:
6187 case VTESTPDYrr:
6188 case VTESTPDrm:
6189 case VTESTPDrr:
6190 return true;
6191 }
6192 return false;
6193}
6194
6195bool isVFNMADD231SH(unsigned Opcode) {
6196 switch (Opcode) {
6197 case VFNMADD231SHZm_Int:
6198 case VFNMADD231SHZmk_Int:
6199 case VFNMADD231SHZmkz_Int:
6200 case VFNMADD231SHZr_Int:
6201 case VFNMADD231SHZrb_Int:
6202 case VFNMADD231SHZrbk_Int:
6203 case VFNMADD231SHZrbkz_Int:
6204 case VFNMADD231SHZrk_Int:
6205 case VFNMADD231SHZrkz_Int:
6206 return true;
6207 }
6208 return false;
6209}
6210
6211bool isENDBR64(unsigned Opcode) {
6212 return Opcode == ENDBR64;
6213}
6214
6215bool isMULSD(unsigned Opcode) {
6216 switch (Opcode) {
6217 case MULSDrm_Int:
6218 case MULSDrr_Int:
6219 return true;
6220 }
6221 return false;
6222}
6223
6224bool isXRSTORS(unsigned Opcode) {
6225 return Opcode == XRSTORS;
6226}
6227
6228bool isPREFETCHNTA(unsigned Opcode) {
6229 return Opcode == PREFETCHNTA;
6230}
6231
6232bool isVPCOMD(unsigned Opcode) {
6233 switch (Opcode) {
6234 case VPCOMDmi:
6235 case VPCOMDri:
6236 return true;
6237 }
6238 return false;
6239}
6240
6241bool isVPCOMUB(unsigned Opcode) {
6242 switch (Opcode) {
6243 case VPCOMUBmi:
6244 case VPCOMUBri:
6245 return true;
6246 }
6247 return false;
6248}
6249
6250bool isVPHSUBD(unsigned Opcode) {
6251 switch (Opcode) {
6252 case VPHSUBDYrm:
6253 case VPHSUBDYrr:
6254 case VPHSUBDrm:
6255 case VPHSUBDrr:
6256 return true;
6257 }
6258 return false;
6259}
6260
6261bool isVBROADCASTI64X2(unsigned Opcode) {
6262 switch (Opcode) {
6263 case VBROADCASTI64X2Z256rm:
6264 case VBROADCASTI64X2Z256rmk:
6265 case VBROADCASTI64X2Z256rmkz:
6266 case VBROADCASTI64X2Zrm:
6267 case VBROADCASTI64X2Zrmk:
6268 case VBROADCASTI64X2Zrmkz:
6269 return true;
6270 }
6271 return false;
6272}
6273
6274bool isFPATAN(unsigned Opcode) {
6275 return Opcode == FPATAN;
6276}
6277
6278bool isLOOPE(unsigned Opcode) {
6279 return Opcode == LOOPE;
6280}
6281
6282bool isPCMPEQW(unsigned Opcode) {
6283 switch (Opcode) {
6284 case MMX_PCMPEQWrm:
6285 case MMX_PCMPEQWrr:
6286 case PCMPEQWrm:
6287 case PCMPEQWrr:
6288 return true;
6289 }
6290 return false;
6291}
6292
6293bool isVFMADDCSH(unsigned Opcode) {
6294 switch (Opcode) {
6295 case VFMADDCSHZm:
6296 case VFMADDCSHZmk:
6297 case VFMADDCSHZmkz:
6298 case VFMADDCSHZr:
6299 case VFMADDCSHZrb:
6300 case VFMADDCSHZrbk:
6301 case VFMADDCSHZrbkz:
6302 case VFMADDCSHZrk:
6303 case VFMADDCSHZrkz:
6304 return true;
6305 }
6306 return false;
6307}
6308
6309bool isVPDPBSSD(unsigned Opcode) {
6310 switch (Opcode) {
6311 case VPDPBSSDYrm:
6312 case VPDPBSSDYrr:
6313 case VPDPBSSDZ128rm:
6314 case VPDPBSSDZ128rmb:
6315 case VPDPBSSDZ128rmbk:
6316 case VPDPBSSDZ128rmbkz:
6317 case VPDPBSSDZ128rmk:
6318 case VPDPBSSDZ128rmkz:
6319 case VPDPBSSDZ128rr:
6320 case VPDPBSSDZ128rrk:
6321 case VPDPBSSDZ128rrkz:
6322 case VPDPBSSDZ256rm:
6323 case VPDPBSSDZ256rmb:
6324 case VPDPBSSDZ256rmbk:
6325 case VPDPBSSDZ256rmbkz:
6326 case VPDPBSSDZ256rmk:
6327 case VPDPBSSDZ256rmkz:
6328 case VPDPBSSDZ256rr:
6329 case VPDPBSSDZ256rrk:
6330 case VPDPBSSDZ256rrkz:
6331 case VPDPBSSDZrm:
6332 case VPDPBSSDZrmb:
6333 case VPDPBSSDZrmbk:
6334 case VPDPBSSDZrmbkz:
6335 case VPDPBSSDZrmk:
6336 case VPDPBSSDZrmkz:
6337 case VPDPBSSDZrr:
6338 case VPDPBSSDZrrk:
6339 case VPDPBSSDZrrkz:
6340 case VPDPBSSDrm:
6341 case VPDPBSSDrr:
6342 return true;
6343 }
6344 return false;
6345}
6346
6347bool isMOVRS(unsigned Opcode) {
6348 switch (Opcode) {
6349 case MOVRS16rm:
6350 case MOVRS16rm_EVEX:
6351 case MOVRS32rm:
6352 case MOVRS32rm_EVEX:
6353 case MOVRS64rm:
6354 case MOVRS64rm_EVEX:
6355 case MOVRS8rm:
6356 case MOVRS8rm_EVEX:
6357 return true;
6358 }
6359 return false;
6360}
6361
6362bool isVFMSUBADD132PH(unsigned Opcode) {
6363 switch (Opcode) {
6364 case VFMSUBADD132PHZ128m:
6365 case VFMSUBADD132PHZ128mb:
6366 case VFMSUBADD132PHZ128mbk:
6367 case VFMSUBADD132PHZ128mbkz:
6368 case VFMSUBADD132PHZ128mk:
6369 case VFMSUBADD132PHZ128mkz:
6370 case VFMSUBADD132PHZ128r:
6371 case VFMSUBADD132PHZ128rk:
6372 case VFMSUBADD132PHZ128rkz:
6373 case VFMSUBADD132PHZ256m:
6374 case VFMSUBADD132PHZ256mb:
6375 case VFMSUBADD132PHZ256mbk:
6376 case VFMSUBADD132PHZ256mbkz:
6377 case VFMSUBADD132PHZ256mk:
6378 case VFMSUBADD132PHZ256mkz:
6379 case VFMSUBADD132PHZ256r:
6380 case VFMSUBADD132PHZ256rk:
6381 case VFMSUBADD132PHZ256rkz:
6382 case VFMSUBADD132PHZm:
6383 case VFMSUBADD132PHZmb:
6384 case VFMSUBADD132PHZmbk:
6385 case VFMSUBADD132PHZmbkz:
6386 case VFMSUBADD132PHZmk:
6387 case VFMSUBADD132PHZmkz:
6388 case VFMSUBADD132PHZr:
6389 case VFMSUBADD132PHZrb:
6390 case VFMSUBADD132PHZrbk:
6391 case VFMSUBADD132PHZrbkz:
6392 case VFMSUBADD132PHZrk:
6393 case VFMSUBADD132PHZrkz:
6394 return true;
6395 }
6396 return false;
6397}
6398
6399bool isKADDW(unsigned Opcode) {
6400 return Opcode == KADDWkk;
6401}
6402
6403bool isPTEST(unsigned Opcode) {
6404 switch (Opcode) {
6405 case PTESTrm:
6406 case PTESTrr:
6407 return true;
6408 }
6409 return false;
6410}
6411
6412bool isVRSQRT28PS(unsigned Opcode) {
6413 switch (Opcode) {
6414 case VRSQRT28PSZm:
6415 case VRSQRT28PSZmb:
6416 case VRSQRT28PSZmbk:
6417 case VRSQRT28PSZmbkz:
6418 case VRSQRT28PSZmk:
6419 case VRSQRT28PSZmkz:
6420 case VRSQRT28PSZr:
6421 case VRSQRT28PSZrb:
6422 case VRSQRT28PSZrbk:
6423 case VRSQRT28PSZrbkz:
6424 case VRSQRT28PSZrk:
6425 case VRSQRT28PSZrkz:
6426 return true;
6427 }
6428 return false;
6429}
6430
6431bool isVGF2P8AFFINEINVQB(unsigned Opcode) {
6432 switch (Opcode) {
6433 case VGF2P8AFFINEINVQBYrmi:
6434 case VGF2P8AFFINEINVQBYrri:
6435 case VGF2P8AFFINEINVQBZ128rmbi:
6436 case VGF2P8AFFINEINVQBZ128rmbik:
6437 case VGF2P8AFFINEINVQBZ128rmbikz:
6438 case VGF2P8AFFINEINVQBZ128rmi:
6439 case VGF2P8AFFINEINVQBZ128rmik:
6440 case VGF2P8AFFINEINVQBZ128rmikz:
6441 case VGF2P8AFFINEINVQBZ128rri:
6442 case VGF2P8AFFINEINVQBZ128rrik:
6443 case VGF2P8AFFINEINVQBZ128rrikz:
6444 case VGF2P8AFFINEINVQBZ256rmbi:
6445 case VGF2P8AFFINEINVQBZ256rmbik:
6446 case VGF2P8AFFINEINVQBZ256rmbikz:
6447 case VGF2P8AFFINEINVQBZ256rmi:
6448 case VGF2P8AFFINEINVQBZ256rmik:
6449 case VGF2P8AFFINEINVQBZ256rmikz:
6450 case VGF2P8AFFINEINVQBZ256rri:
6451 case VGF2P8AFFINEINVQBZ256rrik:
6452 case VGF2P8AFFINEINVQBZ256rrikz:
6453 case VGF2P8AFFINEINVQBZrmbi:
6454 case VGF2P8AFFINEINVQBZrmbik:
6455 case VGF2P8AFFINEINVQBZrmbikz:
6456 case VGF2P8AFFINEINVQBZrmi:
6457 case VGF2P8AFFINEINVQBZrmik:
6458 case VGF2P8AFFINEINVQBZrmikz:
6459 case VGF2P8AFFINEINVQBZrri:
6460 case VGF2P8AFFINEINVQBZrrik:
6461 case VGF2P8AFFINEINVQBZrrikz:
6462 case VGF2P8AFFINEINVQBrmi:
6463 case VGF2P8AFFINEINVQBrri:
6464 return true;
6465 }
6466 return false;
6467}
6468
6469bool isSERIALIZE(unsigned Opcode) {
6470 return Opcode == SERIALIZE;
6471}
6472
6473bool isVPHADDWQ(unsigned Opcode) {
6474 switch (Opcode) {
6475 case VPHADDWQrm:
6476 case VPHADDWQrr:
6477 return true;
6478 }
6479 return false;
6480}
6481
6482bool isVRNDSCALESH(unsigned Opcode) {
6483 switch (Opcode) {
6484 case VRNDSCALESHZrmi_Int:
6485 case VRNDSCALESHZrmik_Int:
6486 case VRNDSCALESHZrmikz_Int:
6487 case VRNDSCALESHZrri_Int:
6488 case VRNDSCALESHZrrib_Int:
6489 case VRNDSCALESHZrribk_Int:
6490 case VRNDSCALESHZrribkz_Int:
6491 case VRNDSCALESHZrrik_Int:
6492 case VRNDSCALESHZrrikz_Int:
6493 return true;
6494 }
6495 return false;
6496}
6497
6498bool isAAA(unsigned Opcode) {
6499 return Opcode == AAA;
6500}
6501
6502bool isVADDBF16(unsigned Opcode) {
6503 switch (Opcode) {
6504 case VADDBF16Z128rm:
6505 case VADDBF16Z128rmb:
6506 case VADDBF16Z128rmbk:
6507 case VADDBF16Z128rmbkz:
6508 case VADDBF16Z128rmk:
6509 case VADDBF16Z128rmkz:
6510 case VADDBF16Z128rr:
6511 case VADDBF16Z128rrk:
6512 case VADDBF16Z128rrkz:
6513 case VADDBF16Z256rm:
6514 case VADDBF16Z256rmb:
6515 case VADDBF16Z256rmbk:
6516 case VADDBF16Z256rmbkz:
6517 case VADDBF16Z256rmk:
6518 case VADDBF16Z256rmkz:
6519 case VADDBF16Z256rr:
6520 case VADDBF16Z256rrk:
6521 case VADDBF16Z256rrkz:
6522 case VADDBF16Zrm:
6523 case VADDBF16Zrmb:
6524 case VADDBF16Zrmbk:
6525 case VADDBF16Zrmbkz:
6526 case VADDBF16Zrmk:
6527 case VADDBF16Zrmkz:
6528 case VADDBF16Zrr:
6529 case VADDBF16Zrrk:
6530 case VADDBF16Zrrkz:
6531 return true;
6532 }
6533 return false;
6534}
6535
6536bool isWRMSRLIST(unsigned Opcode) {
6537 return Opcode == WRMSRLIST;
6538}
6539
6540bool isVCVTPH2PSX(unsigned Opcode) {
6541 switch (Opcode) {
6542 case VCVTPH2PSXZ128rm:
6543 case VCVTPH2PSXZ128rmb:
6544 case VCVTPH2PSXZ128rmbk:
6545 case VCVTPH2PSXZ128rmbkz:
6546 case VCVTPH2PSXZ128rmk:
6547 case VCVTPH2PSXZ128rmkz:
6548 case VCVTPH2PSXZ128rr:
6549 case VCVTPH2PSXZ128rrk:
6550 case VCVTPH2PSXZ128rrkz:
6551 case VCVTPH2PSXZ256rm:
6552 case VCVTPH2PSXZ256rmb:
6553 case VCVTPH2PSXZ256rmbk:
6554 case VCVTPH2PSXZ256rmbkz:
6555 case VCVTPH2PSXZ256rmk:
6556 case VCVTPH2PSXZ256rmkz:
6557 case VCVTPH2PSXZ256rr:
6558 case VCVTPH2PSXZ256rrk:
6559 case VCVTPH2PSXZ256rrkz:
6560 case VCVTPH2PSXZrm:
6561 case VCVTPH2PSXZrmb:
6562 case VCVTPH2PSXZrmbk:
6563 case VCVTPH2PSXZrmbkz:
6564 case VCVTPH2PSXZrmk:
6565 case VCVTPH2PSXZrmkz:
6566 case VCVTPH2PSXZrr:
6567 case VCVTPH2PSXZrrb:
6568 case VCVTPH2PSXZrrbk:
6569 case VCVTPH2PSXZrrbkz:
6570 case VCVTPH2PSXZrrk:
6571 case VCVTPH2PSXZrrkz:
6572 return true;
6573 }
6574 return false;
6575}
6576
6577bool isVFMSUB231PH(unsigned Opcode) {
6578 switch (Opcode) {
6579 case VFMSUB231PHZ128m:
6580 case VFMSUB231PHZ128mb:
6581 case VFMSUB231PHZ128mbk:
6582 case VFMSUB231PHZ128mbkz:
6583 case VFMSUB231PHZ128mk:
6584 case VFMSUB231PHZ128mkz:
6585 case VFMSUB231PHZ128r:
6586 case VFMSUB231PHZ128rk:
6587 case VFMSUB231PHZ128rkz:
6588 case VFMSUB231PHZ256m:
6589 case VFMSUB231PHZ256mb:
6590 case VFMSUB231PHZ256mbk:
6591 case VFMSUB231PHZ256mbkz:
6592 case VFMSUB231PHZ256mk:
6593 case VFMSUB231PHZ256mkz:
6594 case VFMSUB231PHZ256r:
6595 case VFMSUB231PHZ256rk:
6596 case VFMSUB231PHZ256rkz:
6597 case VFMSUB231PHZm:
6598 case VFMSUB231PHZmb:
6599 case VFMSUB231PHZmbk:
6600 case VFMSUB231PHZmbkz:
6601 case VFMSUB231PHZmk:
6602 case VFMSUB231PHZmkz:
6603 case VFMSUB231PHZr:
6604 case VFMSUB231PHZrb:
6605 case VFMSUB231PHZrbk:
6606 case VFMSUB231PHZrbkz:
6607 case VFMSUB231PHZrk:
6608 case VFMSUB231PHZrkz:
6609 return true;
6610 }
6611 return false;
6612}
6613
6614bool isVGATHERQPD(unsigned Opcode) {
6615 switch (Opcode) {
6616 case VGATHERQPDYrm:
6617 case VGATHERQPDZ128rm:
6618 case VGATHERQPDZ256rm:
6619 case VGATHERQPDZrm:
6620 case VGATHERQPDrm:
6621 return true;
6622 }
6623 return false;
6624}
6625
6626bool isKADDB(unsigned Opcode) {
6627 return Opcode == KADDBkk;
6628}
6629
6630bool isCVTPD2PI(unsigned Opcode) {
6631 switch (Opcode) {
6632 case MMX_CVTPD2PIrm:
6633 case MMX_CVTPD2PIrr:
6634 return true;
6635 }
6636 return false;
6637}
6638
6639bool isVFNMSUB213PH(unsigned Opcode) {
6640 switch (Opcode) {
6641 case VFNMSUB213PHZ128m:
6642 case VFNMSUB213PHZ128mb:
6643 case VFNMSUB213PHZ128mbk:
6644 case VFNMSUB213PHZ128mbkz:
6645 case VFNMSUB213PHZ128mk:
6646 case VFNMSUB213PHZ128mkz:
6647 case VFNMSUB213PHZ128r:
6648 case VFNMSUB213PHZ128rk:
6649 case VFNMSUB213PHZ128rkz:
6650 case VFNMSUB213PHZ256m:
6651 case VFNMSUB213PHZ256mb:
6652 case VFNMSUB213PHZ256mbk:
6653 case VFNMSUB213PHZ256mbkz:
6654 case VFNMSUB213PHZ256mk:
6655 case VFNMSUB213PHZ256mkz:
6656 case VFNMSUB213PHZ256r:
6657 case VFNMSUB213PHZ256rk:
6658 case VFNMSUB213PHZ256rkz:
6659 case VFNMSUB213PHZm:
6660 case VFNMSUB213PHZmb:
6661 case VFNMSUB213PHZmbk:
6662 case VFNMSUB213PHZmbkz:
6663 case VFNMSUB213PHZmk:
6664 case VFNMSUB213PHZmkz:
6665 case VFNMSUB213PHZr:
6666 case VFNMSUB213PHZrb:
6667 case VFNMSUB213PHZrbk:
6668 case VFNMSUB213PHZrbkz:
6669 case VFNMSUB213PHZrk:
6670 case VFNMSUB213PHZrkz:
6671 return true;
6672 }
6673 return false;
6674}
6675
6676bool isXORPS(unsigned Opcode) {
6677 switch (Opcode) {
6678 case XORPSrm:
6679 case XORPSrr:
6680 return true;
6681 }
6682 return false;
6683}
6684
6685bool isVPCMPESTRI(unsigned Opcode) {
6686 switch (Opcode) {
6687 case VPCMPESTRIrmi:
6688 case VPCMPESTRIrri:
6689 return true;
6690 }
6691 return false;
6692}
6693
6694bool isVPADDSB(unsigned Opcode) {
6695 switch (Opcode) {
6696 case VPADDSBYrm:
6697 case VPADDSBYrr:
6698 case VPADDSBZ128rm:
6699 case VPADDSBZ128rmk:
6700 case VPADDSBZ128rmkz:
6701 case VPADDSBZ128rr:
6702 case VPADDSBZ128rrk:
6703 case VPADDSBZ128rrkz:
6704 case VPADDSBZ256rm:
6705 case VPADDSBZ256rmk:
6706 case VPADDSBZ256rmkz:
6707 case VPADDSBZ256rr:
6708 case VPADDSBZ256rrk:
6709 case VPADDSBZ256rrkz:
6710 case VPADDSBZrm:
6711 case VPADDSBZrmk:
6712 case VPADDSBZrmkz:
6713 case VPADDSBZrr:
6714 case VPADDSBZrrk:
6715 case VPADDSBZrrkz:
6716 case VPADDSBrm:
6717 case VPADDSBrr:
6718 return true;
6719 }
6720 return false;
6721}
6722
6723bool isPOP2(unsigned Opcode) {
6724 return Opcode == POP2;
6725}
6726
6727bool isRDMSRLIST(unsigned Opcode) {
6728 return Opcode == RDMSRLIST;
6729}
6730
6731bool isVPSHRDW(unsigned Opcode) {
6732 switch (Opcode) {
6733 case VPSHRDWZ128rmi:
6734 case VPSHRDWZ128rmik:
6735 case VPSHRDWZ128rmikz:
6736 case VPSHRDWZ128rri:
6737 case VPSHRDWZ128rrik:
6738 case VPSHRDWZ128rrikz:
6739 case VPSHRDWZ256rmi:
6740 case VPSHRDWZ256rmik:
6741 case VPSHRDWZ256rmikz:
6742 case VPSHRDWZ256rri:
6743 case VPSHRDWZ256rrik:
6744 case VPSHRDWZ256rrikz:
6745 case VPSHRDWZrmi:
6746 case VPSHRDWZrmik:
6747 case VPSHRDWZrmikz:
6748 case VPSHRDWZrri:
6749 case VPSHRDWZrrik:
6750 case VPSHRDWZrrikz:
6751 return true;
6752 }
6753 return false;
6754}
6755
6756bool isVPDPBUSD(unsigned Opcode) {
6757 switch (Opcode) {
6758 case VPDPBUSDYrm:
6759 case VPDPBUSDYrr:
6760 case VPDPBUSDZ128rm:
6761 case VPDPBUSDZ128rmb:
6762 case VPDPBUSDZ128rmbk:
6763 case VPDPBUSDZ128rmbkz:
6764 case VPDPBUSDZ128rmk:
6765 case VPDPBUSDZ128rmkz:
6766 case VPDPBUSDZ128rr:
6767 case VPDPBUSDZ128rrk:
6768 case VPDPBUSDZ128rrkz:
6769 case VPDPBUSDZ256rm:
6770 case VPDPBUSDZ256rmb:
6771 case VPDPBUSDZ256rmbk:
6772 case VPDPBUSDZ256rmbkz:
6773 case VPDPBUSDZ256rmk:
6774 case VPDPBUSDZ256rmkz:
6775 case VPDPBUSDZ256rr:
6776 case VPDPBUSDZ256rrk:
6777 case VPDPBUSDZ256rrkz:
6778 case VPDPBUSDZrm:
6779 case VPDPBUSDZrmb:
6780 case VPDPBUSDZrmbk:
6781 case VPDPBUSDZrmbkz:
6782 case VPDPBUSDZrmk:
6783 case VPDPBUSDZrmkz:
6784 case VPDPBUSDZrr:
6785 case VPDPBUSDZrrk:
6786 case VPDPBUSDZrrkz:
6787 case VPDPBUSDrm:
6788 case VPDPBUSDrr:
6789 return true;
6790 }
6791 return false;
6792}
6793
6794bool isVCMPPH(unsigned Opcode) {
6795 switch (Opcode) {
6796 case VCMPPHZ128rmbi:
6797 case VCMPPHZ128rmbik:
6798 case VCMPPHZ128rmi:
6799 case VCMPPHZ128rmik:
6800 case VCMPPHZ128rri:
6801 case VCMPPHZ128rrik:
6802 case VCMPPHZ256rmbi:
6803 case VCMPPHZ256rmbik:
6804 case VCMPPHZ256rmi:
6805 case VCMPPHZ256rmik:
6806 case VCMPPHZ256rri:
6807 case VCMPPHZ256rrik:
6808 case VCMPPHZrmbi:
6809 case VCMPPHZrmbik:
6810 case VCMPPHZrmi:
6811 case VCMPPHZrmik:
6812 case VCMPPHZrri:
6813 case VCMPPHZrrib:
6814 case VCMPPHZrribk:
6815 case VCMPPHZrrik:
6816 return true;
6817 }
6818 return false;
6819}
6820
6821bool isVANDNPD(unsigned Opcode) {
6822 switch (Opcode) {
6823 case VANDNPDYrm:
6824 case VANDNPDYrr:
6825 case VANDNPDZ128rm:
6826 case VANDNPDZ128rmb:
6827 case VANDNPDZ128rmbk:
6828 case VANDNPDZ128rmbkz:
6829 case VANDNPDZ128rmk:
6830 case VANDNPDZ128rmkz:
6831 case VANDNPDZ128rr:
6832 case VANDNPDZ128rrk:
6833 case VANDNPDZ128rrkz:
6834 case VANDNPDZ256rm:
6835 case VANDNPDZ256rmb:
6836 case VANDNPDZ256rmbk:
6837 case VANDNPDZ256rmbkz:
6838 case VANDNPDZ256rmk:
6839 case VANDNPDZ256rmkz:
6840 case VANDNPDZ256rr:
6841 case VANDNPDZ256rrk:
6842 case VANDNPDZ256rrkz:
6843 case VANDNPDZrm:
6844 case VANDNPDZrmb:
6845 case VANDNPDZrmbk:
6846 case VANDNPDZrmbkz:
6847 case VANDNPDZrmk:
6848 case VANDNPDZrmkz:
6849 case VANDNPDZrr:
6850 case VANDNPDZrrk:
6851 case VANDNPDZrrkz:
6852 case VANDNPDrm:
6853 case VANDNPDrr:
6854 return true;
6855 }
6856 return false;
6857}
6858
6859bool isSUB(unsigned Opcode) {
6860 switch (Opcode) {
6861 case SUB16i16:
6862 case SUB16mi:
6863 case SUB16mi8:
6864 case SUB16mi8_EVEX:
6865 case SUB16mi8_ND:
6866 case SUB16mi8_NF:
6867 case SUB16mi8_NF_ND:
6868 case SUB16mi_EVEX:
6869 case SUB16mi_ND:
6870 case SUB16mi_NF:
6871 case SUB16mi_NF_ND:
6872 case SUB16mr:
6873 case SUB16mr_EVEX:
6874 case SUB16mr_ND:
6875 case SUB16mr_NF:
6876 case SUB16mr_NF_ND:
6877 case SUB16ri:
6878 case SUB16ri8:
6879 case SUB16ri8_EVEX:
6880 case SUB16ri8_ND:
6881 case SUB16ri8_NF:
6882 case SUB16ri8_NF_ND:
6883 case SUB16ri_EVEX:
6884 case SUB16ri_ND:
6885 case SUB16ri_NF:
6886 case SUB16ri_NF_ND:
6887 case SUB16rm:
6888 case SUB16rm_EVEX:
6889 case SUB16rm_ND:
6890 case SUB16rm_NF:
6891 case SUB16rm_NF_ND:
6892 case SUB16rr:
6893 case SUB16rr_EVEX:
6894 case SUB16rr_EVEX_REV:
6895 case SUB16rr_ND:
6896 case SUB16rr_ND_REV:
6897 case SUB16rr_NF:
6898 case SUB16rr_NF_ND:
6899 case SUB16rr_NF_ND_REV:
6900 case SUB16rr_NF_REV:
6901 case SUB16rr_REV:
6902 case SUB32i32:
6903 case SUB32mi:
6904 case SUB32mi8:
6905 case SUB32mi8_EVEX:
6906 case SUB32mi8_ND:
6907 case SUB32mi8_NF:
6908 case SUB32mi8_NF_ND:
6909 case SUB32mi_EVEX:
6910 case SUB32mi_ND:
6911 case SUB32mi_NF:
6912 case SUB32mi_NF_ND:
6913 case SUB32mr:
6914 case SUB32mr_EVEX:
6915 case SUB32mr_ND:
6916 case SUB32mr_NF:
6917 case SUB32mr_NF_ND:
6918 case SUB32ri:
6919 case SUB32ri8:
6920 case SUB32ri8_EVEX:
6921 case SUB32ri8_ND:
6922 case SUB32ri8_NF:
6923 case SUB32ri8_NF_ND:
6924 case SUB32ri_EVEX:
6925 case SUB32ri_ND:
6926 case SUB32ri_NF:
6927 case SUB32ri_NF_ND:
6928 case SUB32rm:
6929 case SUB32rm_EVEX:
6930 case SUB32rm_ND:
6931 case SUB32rm_NF:
6932 case SUB32rm_NF_ND:
6933 case SUB32rr:
6934 case SUB32rr_EVEX:
6935 case SUB32rr_EVEX_REV:
6936 case SUB32rr_ND:
6937 case SUB32rr_ND_REV:
6938 case SUB32rr_NF:
6939 case SUB32rr_NF_ND:
6940 case SUB32rr_NF_ND_REV:
6941 case SUB32rr_NF_REV:
6942 case SUB32rr_REV:
6943 case SUB64i32:
6944 case SUB64mi32:
6945 case SUB64mi32_EVEX:
6946 case SUB64mi32_ND:
6947 case SUB64mi32_NF:
6948 case SUB64mi32_NF_ND:
6949 case SUB64mi8:
6950 case SUB64mi8_EVEX:
6951 case SUB64mi8_ND:
6952 case SUB64mi8_NF:
6953 case SUB64mi8_NF_ND:
6954 case SUB64mr:
6955 case SUB64mr_EVEX:
6956 case SUB64mr_ND:
6957 case SUB64mr_NF:
6958 case SUB64mr_NF_ND:
6959 case SUB64ri32:
6960 case SUB64ri32_EVEX:
6961 case SUB64ri32_ND:
6962 case SUB64ri32_NF:
6963 case SUB64ri32_NF_ND:
6964 case SUB64ri8:
6965 case SUB64ri8_EVEX:
6966 case SUB64ri8_ND:
6967 case SUB64ri8_NF:
6968 case SUB64ri8_NF_ND:
6969 case SUB64rm:
6970 case SUB64rm_EVEX:
6971 case SUB64rm_ND:
6972 case SUB64rm_NF:
6973 case SUB64rm_NF_ND:
6974 case SUB64rr:
6975 case SUB64rr_EVEX:
6976 case SUB64rr_EVEX_REV:
6977 case SUB64rr_ND:
6978 case SUB64rr_ND_REV:
6979 case SUB64rr_NF:
6980 case SUB64rr_NF_ND:
6981 case SUB64rr_NF_ND_REV:
6982 case SUB64rr_NF_REV:
6983 case SUB64rr_REV:
6984 case SUB8i8:
6985 case SUB8mi:
6986 case SUB8mi8:
6987 case SUB8mi_EVEX:
6988 case SUB8mi_ND:
6989 case SUB8mi_NF:
6990 case SUB8mi_NF_ND:
6991 case SUB8mr:
6992 case SUB8mr_EVEX:
6993 case SUB8mr_ND:
6994 case SUB8mr_NF:
6995 case SUB8mr_NF_ND:
6996 case SUB8ri:
6997 case SUB8ri8:
6998 case SUB8ri_EVEX:
6999 case SUB8ri_ND:
7000 case SUB8ri_NF:
7001 case SUB8ri_NF_ND:
7002 case SUB8rm:
7003 case SUB8rm_EVEX:
7004 case SUB8rm_ND:
7005 case SUB8rm_NF:
7006 case SUB8rm_NF_ND:
7007 case SUB8rr:
7008 case SUB8rr_EVEX:
7009 case SUB8rr_EVEX_REV:
7010 case SUB8rr_ND:
7011 case SUB8rr_ND_REV:
7012 case SUB8rr_NF:
7013 case SUB8rr_NF_ND:
7014 case SUB8rr_NF_ND_REV:
7015 case SUB8rr_NF_REV:
7016 case SUB8rr_REV:
7017 return true;
7018 }
7019 return false;
7020}
7021
7022bool isVRSQRT28PD(unsigned Opcode) {
7023 switch (Opcode) {
7024 case VRSQRT28PDZm:
7025 case VRSQRT28PDZmb:
7026 case VRSQRT28PDZmbk:
7027 case VRSQRT28PDZmbkz:
7028 case VRSQRT28PDZmk:
7029 case VRSQRT28PDZmkz:
7030 case VRSQRT28PDZr:
7031 case VRSQRT28PDZrb:
7032 case VRSQRT28PDZrbk:
7033 case VRSQRT28PDZrbkz:
7034 case VRSQRT28PDZrk:
7035 case VRSQRT28PDZrkz:
7036 return true;
7037 }
7038 return false;
7039}
7040
7041bool isVFNMADD132PH(unsigned Opcode) {
7042 switch (Opcode) {
7043 case VFNMADD132PHZ128m:
7044 case VFNMADD132PHZ128mb:
7045 case VFNMADD132PHZ128mbk:
7046 case VFNMADD132PHZ128mbkz:
7047 case VFNMADD132PHZ128mk:
7048 case VFNMADD132PHZ128mkz:
7049 case VFNMADD132PHZ128r:
7050 case VFNMADD132PHZ128rk:
7051 case VFNMADD132PHZ128rkz:
7052 case VFNMADD132PHZ256m:
7053 case VFNMADD132PHZ256mb:
7054 case VFNMADD132PHZ256mbk:
7055 case VFNMADD132PHZ256mbkz:
7056 case VFNMADD132PHZ256mk:
7057 case VFNMADD132PHZ256mkz:
7058 case VFNMADD132PHZ256r:
7059 case VFNMADD132PHZ256rk:
7060 case VFNMADD132PHZ256rkz:
7061 case VFNMADD132PHZm:
7062 case VFNMADD132PHZmb:
7063 case VFNMADD132PHZmbk:
7064 case VFNMADD132PHZmbkz:
7065 case VFNMADD132PHZmk:
7066 case VFNMADD132PHZmkz:
7067 case VFNMADD132PHZr:
7068 case VFNMADD132PHZrb:
7069 case VFNMADD132PHZrbk:
7070 case VFNMADD132PHZrbkz:
7071 case VFNMADD132PHZrk:
7072 case VFNMADD132PHZrkz:
7073 return true;
7074 }
7075 return false;
7076}
7077
7078bool isVPMACSSWW(unsigned Opcode) {
7079 switch (Opcode) {
7080 case VPMACSSWWrm:
7081 case VPMACSSWWrr:
7082 return true;
7083 }
7084 return false;
7085}
7086
7087bool isXSTORE(unsigned Opcode) {
7088 return Opcode == XSTORE;
7089}
7090
7091bool isVPROTQ(unsigned Opcode) {
7092 switch (Opcode) {
7093 case VPROTQmi:
7094 case VPROTQmr:
7095 case VPROTQri:
7096 case VPROTQrm:
7097 case VPROTQrr:
7098 case VPROTQrr_REV:
7099 return true;
7100 }
7101 return false;
7102}
7103
7104bool isVPHADDBD(unsigned Opcode) {
7105 switch (Opcode) {
7106 case VPHADDBDrm:
7107 case VPHADDBDrr:
7108 return true;
7109 }
7110 return false;
7111}
7112
7113bool isVPMAXSB(unsigned Opcode) {
7114 switch (Opcode) {
7115 case VPMAXSBYrm:
7116 case VPMAXSBYrr:
7117 case VPMAXSBZ128rm:
7118 case VPMAXSBZ128rmk:
7119 case VPMAXSBZ128rmkz:
7120 case VPMAXSBZ128rr:
7121 case VPMAXSBZ128rrk:
7122 case VPMAXSBZ128rrkz:
7123 case VPMAXSBZ256rm:
7124 case VPMAXSBZ256rmk:
7125 case VPMAXSBZ256rmkz:
7126 case VPMAXSBZ256rr:
7127 case VPMAXSBZ256rrk:
7128 case VPMAXSBZ256rrkz:
7129 case VPMAXSBZrm:
7130 case VPMAXSBZrmk:
7131 case VPMAXSBZrmkz:
7132 case VPMAXSBZrr:
7133 case VPMAXSBZrrk:
7134 case VPMAXSBZrrkz:
7135 case VPMAXSBrm:
7136 case VPMAXSBrr:
7137 return true;
7138 }
7139 return false;
7140}
7141
7142bool isVMOVDQU8(unsigned Opcode) {
7143 switch (Opcode) {
7144 case VMOVDQU8Z128mr:
7145 case VMOVDQU8Z128mrk:
7146 case VMOVDQU8Z128rm:
7147 case VMOVDQU8Z128rmk:
7148 case VMOVDQU8Z128rmkz:
7149 case VMOVDQU8Z128rr:
7150 case VMOVDQU8Z128rr_REV:
7151 case VMOVDQU8Z128rrk:
7152 case VMOVDQU8Z128rrk_REV:
7153 case VMOVDQU8Z128rrkz:
7154 case VMOVDQU8Z128rrkz_REV:
7155 case VMOVDQU8Z256mr:
7156 case VMOVDQU8Z256mrk:
7157 case VMOVDQU8Z256rm:
7158 case VMOVDQU8Z256rmk:
7159 case VMOVDQU8Z256rmkz:
7160 case VMOVDQU8Z256rr:
7161 case VMOVDQU8Z256rr_REV:
7162 case VMOVDQU8Z256rrk:
7163 case VMOVDQU8Z256rrk_REV:
7164 case VMOVDQU8Z256rrkz:
7165 case VMOVDQU8Z256rrkz_REV:
7166 case VMOVDQU8Zmr:
7167 case VMOVDQU8Zmrk:
7168 case VMOVDQU8Zrm:
7169 case VMOVDQU8Zrmk:
7170 case VMOVDQU8Zrmkz:
7171 case VMOVDQU8Zrr:
7172 case VMOVDQU8Zrr_REV:
7173 case VMOVDQU8Zrrk:
7174 case VMOVDQU8Zrrk_REV:
7175 case VMOVDQU8Zrrkz:
7176 case VMOVDQU8Zrrkz_REV:
7177 return true;
7178 }
7179 return false;
7180}
7181
7182bool isVPMOVSXWD(unsigned Opcode) {
7183 switch (Opcode) {
7184 case VPMOVSXWDYrm:
7185 case VPMOVSXWDYrr:
7186 case VPMOVSXWDZ128rm:
7187 case VPMOVSXWDZ128rmk:
7188 case VPMOVSXWDZ128rmkz:
7189 case VPMOVSXWDZ128rr:
7190 case VPMOVSXWDZ128rrk:
7191 case VPMOVSXWDZ128rrkz:
7192 case VPMOVSXWDZ256rm:
7193 case VPMOVSXWDZ256rmk:
7194 case VPMOVSXWDZ256rmkz:
7195 case VPMOVSXWDZ256rr:
7196 case VPMOVSXWDZ256rrk:
7197 case VPMOVSXWDZ256rrkz:
7198 case VPMOVSXWDZrm:
7199 case VPMOVSXWDZrmk:
7200 case VPMOVSXWDZrmkz:
7201 case VPMOVSXWDZrr:
7202 case VPMOVSXWDZrrk:
7203 case VPMOVSXWDZrrkz:
7204 case VPMOVSXWDrm:
7205 case VPMOVSXWDrr:
7206 return true;
7207 }
7208 return false;
7209}
7210
7211bool isVMINMAXPD(unsigned Opcode) {
7212 switch (Opcode) {
7213 case VMINMAXPDZ128rmbi:
7214 case VMINMAXPDZ128rmbik:
7215 case VMINMAXPDZ128rmbikz:
7216 case VMINMAXPDZ128rmi:
7217 case VMINMAXPDZ128rmik:
7218 case VMINMAXPDZ128rmikz:
7219 case VMINMAXPDZ128rri:
7220 case VMINMAXPDZ128rrik:
7221 case VMINMAXPDZ128rrikz:
7222 case VMINMAXPDZ256rmbi:
7223 case VMINMAXPDZ256rmbik:
7224 case VMINMAXPDZ256rmbikz:
7225 case VMINMAXPDZ256rmi:
7226 case VMINMAXPDZ256rmik:
7227 case VMINMAXPDZ256rmikz:
7228 case VMINMAXPDZ256rri:
7229 case VMINMAXPDZ256rrik:
7230 case VMINMAXPDZ256rrikz:
7231 case VMINMAXPDZrmbi:
7232 case VMINMAXPDZrmbik:
7233 case VMINMAXPDZrmbikz:
7234 case VMINMAXPDZrmi:
7235 case VMINMAXPDZrmik:
7236 case VMINMAXPDZrmikz:
7237 case VMINMAXPDZrri:
7238 case VMINMAXPDZrrib:
7239 case VMINMAXPDZrribk:
7240 case VMINMAXPDZrribkz:
7241 case VMINMAXPDZrrik:
7242 case VMINMAXPDZrrikz:
7243 return true;
7244 }
7245 return false;
7246}
7247
7248bool isSHA256RNDS2(unsigned Opcode) {
7249 switch (Opcode) {
7250 case SHA256RNDS2rm:
7251 case SHA256RNDS2rr:
7252 return true;
7253 }
7254 return false;
7255}
7256
7257bool isKANDB(unsigned Opcode) {
7258 return Opcode == KANDBkk;
7259}
7260
7261bool isTPAUSE(unsigned Opcode) {
7262 return Opcode == TPAUSE;
7263}
7264
7265bool isPUSH(unsigned Opcode) {
7266 switch (Opcode) {
7267 case PUSH16i:
7268 case PUSH16i8:
7269 case PUSH16r:
7270 case PUSH16rmm:
7271 case PUSH16rmr:
7272 case PUSH32i:
7273 case PUSH32i8:
7274 case PUSH32r:
7275 case PUSH32rmm:
7276 case PUSH32rmr:
7277 case PUSH64i32:
7278 case PUSH64i8:
7279 case PUSH64r:
7280 case PUSH64rmm:
7281 case PUSH64rmr:
7282 case PUSHCS16:
7283 case PUSHCS32:
7284 case PUSHDS16:
7285 case PUSHDS32:
7286 case PUSHES16:
7287 case PUSHES32:
7288 case PUSHFS16:
7289 case PUSHFS32:
7290 case PUSHFS64:
7291 case PUSHGS16:
7292 case PUSHGS32:
7293 case PUSHGS64:
7294 case PUSHSS16:
7295 case PUSHSS32:
7296 return true;
7297 }
7298 return false;
7299}
7300
7301bool isVRNDSCALESS(unsigned Opcode) {
7302 switch (Opcode) {
7303 case VRNDSCALESSZrmi_Int:
7304 case VRNDSCALESSZrmik_Int:
7305 case VRNDSCALESSZrmikz_Int:
7306 case VRNDSCALESSZrri_Int:
7307 case VRNDSCALESSZrrib_Int:
7308 case VRNDSCALESSZrribk_Int:
7309 case VRNDSCALESSZrribkz_Int:
7310 case VRNDSCALESSZrrik_Int:
7311 case VRNDSCALESSZrrikz_Int:
7312 return true;
7313 }
7314 return false;
7315}
7316
7317bool isVRNDSCALEBF16(unsigned Opcode) {
7318 switch (Opcode) {
7319 case VRNDSCALEBF16Z128rmbi:
7320 case VRNDSCALEBF16Z128rmbik:
7321 case VRNDSCALEBF16Z128rmbikz:
7322 case VRNDSCALEBF16Z128rmi:
7323 case VRNDSCALEBF16Z128rmik:
7324 case VRNDSCALEBF16Z128rmikz:
7325 case VRNDSCALEBF16Z128rri:
7326 case VRNDSCALEBF16Z128rrik:
7327 case VRNDSCALEBF16Z128rrikz:
7328 case VRNDSCALEBF16Z256rmbi:
7329 case VRNDSCALEBF16Z256rmbik:
7330 case VRNDSCALEBF16Z256rmbikz:
7331 case VRNDSCALEBF16Z256rmi:
7332 case VRNDSCALEBF16Z256rmik:
7333 case VRNDSCALEBF16Z256rmikz:
7334 case VRNDSCALEBF16Z256rri:
7335 case VRNDSCALEBF16Z256rrik:
7336 case VRNDSCALEBF16Z256rrikz:
7337 case VRNDSCALEBF16Zrmbi:
7338 case VRNDSCALEBF16Zrmbik:
7339 case VRNDSCALEBF16Zrmbikz:
7340 case VRNDSCALEBF16Zrmi:
7341 case VRNDSCALEBF16Zrmik:
7342 case VRNDSCALEBF16Zrmikz:
7343 case VRNDSCALEBF16Zrri:
7344 case VRNDSCALEBF16Zrrik:
7345 case VRNDSCALEBF16Zrrikz:
7346 return true;
7347 }
7348 return false;
7349}
7350
7351bool isVPCMPISTRI(unsigned Opcode) {
7352 switch (Opcode) {
7353 case VPCMPISTRIrmi:
7354 case VPCMPISTRIrri:
7355 return true;
7356 }
7357 return false;
7358}
7359
7360bool isSTGI(unsigned Opcode) {
7361 return Opcode == STGI;
7362}
7363
7364bool isSBB(unsigned Opcode) {
7365 switch (Opcode) {
7366 case SBB16i16:
7367 case SBB16mi:
7368 case SBB16mi8:
7369 case SBB16mi8_EVEX:
7370 case SBB16mi8_ND:
7371 case SBB16mi_EVEX:
7372 case SBB16mi_ND:
7373 case SBB16mr:
7374 case SBB16mr_EVEX:
7375 case SBB16mr_ND:
7376 case SBB16ri:
7377 case SBB16ri8:
7378 case SBB16ri8_EVEX:
7379 case SBB16ri8_ND:
7380 case SBB16ri_EVEX:
7381 case SBB16ri_ND:
7382 case SBB16rm:
7383 case SBB16rm_EVEX:
7384 case SBB16rm_ND:
7385 case SBB16rr:
7386 case SBB16rr_EVEX:
7387 case SBB16rr_EVEX_REV:
7388 case SBB16rr_ND:
7389 case SBB16rr_ND_REV:
7390 case SBB16rr_REV:
7391 case SBB32i32:
7392 case SBB32mi:
7393 case SBB32mi8:
7394 case SBB32mi8_EVEX:
7395 case SBB32mi8_ND:
7396 case SBB32mi_EVEX:
7397 case SBB32mi_ND:
7398 case SBB32mr:
7399 case SBB32mr_EVEX:
7400 case SBB32mr_ND:
7401 case SBB32ri:
7402 case SBB32ri8:
7403 case SBB32ri8_EVEX:
7404 case SBB32ri8_ND:
7405 case SBB32ri_EVEX:
7406 case SBB32ri_ND:
7407 case SBB32rm:
7408 case SBB32rm_EVEX:
7409 case SBB32rm_ND:
7410 case SBB32rr:
7411 case SBB32rr_EVEX:
7412 case SBB32rr_EVEX_REV:
7413 case SBB32rr_ND:
7414 case SBB32rr_ND_REV:
7415 case SBB32rr_REV:
7416 case SBB64i32:
7417 case SBB64mi32:
7418 case SBB64mi32_EVEX:
7419 case SBB64mi32_ND:
7420 case SBB64mi8:
7421 case SBB64mi8_EVEX:
7422 case SBB64mi8_ND:
7423 case SBB64mr:
7424 case SBB64mr_EVEX:
7425 case SBB64mr_ND:
7426 case SBB64ri32:
7427 case SBB64ri32_EVEX:
7428 case SBB64ri32_ND:
7429 case SBB64ri8:
7430 case SBB64ri8_EVEX:
7431 case SBB64ri8_ND:
7432 case SBB64rm:
7433 case SBB64rm_EVEX:
7434 case SBB64rm_ND:
7435 case SBB64rr:
7436 case SBB64rr_EVEX:
7437 case SBB64rr_EVEX_REV:
7438 case SBB64rr_ND:
7439 case SBB64rr_ND_REV:
7440 case SBB64rr_REV:
7441 case SBB8i8:
7442 case SBB8mi:
7443 case SBB8mi8:
7444 case SBB8mi_EVEX:
7445 case SBB8mi_ND:
7446 case SBB8mr:
7447 case SBB8mr_EVEX:
7448 case SBB8mr_ND:
7449 case SBB8ri:
7450 case SBB8ri8:
7451 case SBB8ri_EVEX:
7452 case SBB8ri_ND:
7453 case SBB8rm:
7454 case SBB8rm_EVEX:
7455 case SBB8rm_ND:
7456 case SBB8rr:
7457 case SBB8rr_EVEX:
7458 case SBB8rr_EVEX_REV:
7459 case SBB8rr_ND:
7460 case SBB8rr_ND_REV:
7461 case SBB8rr_REV:
7462 return true;
7463 }
7464 return false;
7465}
7466
7467bool isBLCS(unsigned Opcode) {
7468 switch (Opcode) {
7469 case BLCS32rm:
7470 case BLCS32rr:
7471 case BLCS64rm:
7472 case BLCS64rr:
7473 return true;
7474 }
7475 return false;
7476}
7477
7478bool isVCVTSD2SH(unsigned Opcode) {
7479 switch (Opcode) {
7480 case VCVTSD2SHZrm_Int:
7481 case VCVTSD2SHZrmk_Int:
7482 case VCVTSD2SHZrmkz_Int:
7483 case VCVTSD2SHZrr_Int:
7484 case VCVTSD2SHZrrb_Int:
7485 case VCVTSD2SHZrrbk_Int:
7486 case VCVTSD2SHZrrbkz_Int:
7487 case VCVTSD2SHZrrk_Int:
7488 case VCVTSD2SHZrrkz_Int:
7489 return true;
7490 }
7491 return false;
7492}
7493
7494bool isVPERMW(unsigned Opcode) {
7495 switch (Opcode) {
7496 case VPERMWZ128rm:
7497 case VPERMWZ128rmk:
7498 case VPERMWZ128rmkz:
7499 case VPERMWZ128rr:
7500 case VPERMWZ128rrk:
7501 case VPERMWZ128rrkz:
7502 case VPERMWZ256rm:
7503 case VPERMWZ256rmk:
7504 case VPERMWZ256rmkz:
7505 case VPERMWZ256rr:
7506 case VPERMWZ256rrk:
7507 case VPERMWZ256rrkz:
7508 case VPERMWZrm:
7509 case VPERMWZrmk:
7510 case VPERMWZrmkz:
7511 case VPERMWZrr:
7512 case VPERMWZrrk:
7513 case VPERMWZrrkz:
7514 return true;
7515 }
7516 return false;
7517}
7518
7519bool isXRESLDTRK(unsigned Opcode) {
7520 return Opcode == XRESLDTRK;
7521}
7522
7523bool isAESENC256KL(unsigned Opcode) {
7524 return Opcode == AESENC256KL;
7525}
7526
7527bool isVGATHERDPD(unsigned Opcode) {
7528 switch (Opcode) {
7529 case VGATHERDPDYrm:
7530 case VGATHERDPDZ128rm:
7531 case VGATHERDPDZ256rm:
7532 case VGATHERDPDZrm:
7533 case VGATHERDPDrm:
7534 return true;
7535 }
7536 return false;
7537}
7538
7539bool isHRESET(unsigned Opcode) {
7540 return Opcode == HRESET;
7541}
7542
7543bool isVFMSUBADD231PD(unsigned Opcode) {
7544 switch (Opcode) {
7545 case VFMSUBADD231PDYm:
7546 case VFMSUBADD231PDYr:
7547 case VFMSUBADD231PDZ128m:
7548 case VFMSUBADD231PDZ128mb:
7549 case VFMSUBADD231PDZ128mbk:
7550 case VFMSUBADD231PDZ128mbkz:
7551 case VFMSUBADD231PDZ128mk:
7552 case VFMSUBADD231PDZ128mkz:
7553 case VFMSUBADD231PDZ128r:
7554 case VFMSUBADD231PDZ128rk:
7555 case VFMSUBADD231PDZ128rkz:
7556 case VFMSUBADD231PDZ256m:
7557 case VFMSUBADD231PDZ256mb:
7558 case VFMSUBADD231PDZ256mbk:
7559 case VFMSUBADD231PDZ256mbkz:
7560 case VFMSUBADD231PDZ256mk:
7561 case VFMSUBADD231PDZ256mkz:
7562 case VFMSUBADD231PDZ256r:
7563 case VFMSUBADD231PDZ256rk:
7564 case VFMSUBADD231PDZ256rkz:
7565 case VFMSUBADD231PDZm:
7566 case VFMSUBADD231PDZmb:
7567 case VFMSUBADD231PDZmbk:
7568 case VFMSUBADD231PDZmbkz:
7569 case VFMSUBADD231PDZmk:
7570 case VFMSUBADD231PDZmkz:
7571 case VFMSUBADD231PDZr:
7572 case VFMSUBADD231PDZrb:
7573 case VFMSUBADD231PDZrbk:
7574 case VFMSUBADD231PDZrbkz:
7575 case VFMSUBADD231PDZrk:
7576 case VFMSUBADD231PDZrkz:
7577 case VFMSUBADD231PDm:
7578 case VFMSUBADD231PDr:
7579 return true;
7580 }
7581 return false;
7582}
7583
7584bool isVFRCZSS(unsigned Opcode) {
7585 switch (Opcode) {
7586 case VFRCZSSrm:
7587 case VFRCZSSrr:
7588 return true;
7589 }
7590 return false;
7591}
7592
7593bool isMINPS(unsigned Opcode) {
7594 switch (Opcode) {
7595 case MINPSrm:
7596 case MINPSrr:
7597 return true;
7598 }
7599 return false;
7600}
7601
7602bool isFPREM1(unsigned Opcode) {
7603 return Opcode == FPREM1;
7604}
7605
7606bool isVPCMPUB(unsigned Opcode) {
7607 switch (Opcode) {
7608 case VPCMPUBZ128rmi:
7609 case VPCMPUBZ128rmik:
7610 case VPCMPUBZ128rri:
7611 case VPCMPUBZ128rrik:
7612 case VPCMPUBZ256rmi:
7613 case VPCMPUBZ256rmik:
7614 case VPCMPUBZ256rri:
7615 case VPCMPUBZ256rrik:
7616 case VPCMPUBZrmi:
7617 case VPCMPUBZrmik:
7618 case VPCMPUBZrri:
7619 case VPCMPUBZrrik:
7620 return true;
7621 }
7622 return false;
7623}
7624
7625bool isVSQRTPD(unsigned Opcode) {
7626 switch (Opcode) {
7627 case VSQRTPDYm:
7628 case VSQRTPDYr:
7629 case VSQRTPDZ128m:
7630 case VSQRTPDZ128mb:
7631 case VSQRTPDZ128mbk:
7632 case VSQRTPDZ128mbkz:
7633 case VSQRTPDZ128mk:
7634 case VSQRTPDZ128mkz:
7635 case VSQRTPDZ128r:
7636 case VSQRTPDZ128rk:
7637 case VSQRTPDZ128rkz:
7638 case VSQRTPDZ256m:
7639 case VSQRTPDZ256mb:
7640 case VSQRTPDZ256mbk:
7641 case VSQRTPDZ256mbkz:
7642 case VSQRTPDZ256mk:
7643 case VSQRTPDZ256mkz:
7644 case VSQRTPDZ256r:
7645 case VSQRTPDZ256rk:
7646 case VSQRTPDZ256rkz:
7647 case VSQRTPDZm:
7648 case VSQRTPDZmb:
7649 case VSQRTPDZmbk:
7650 case VSQRTPDZmbkz:
7651 case VSQRTPDZmk:
7652 case VSQRTPDZmkz:
7653 case VSQRTPDZr:
7654 case VSQRTPDZrb:
7655 case VSQRTPDZrbk:
7656 case VSQRTPDZrbkz:
7657 case VSQRTPDZrk:
7658 case VSQRTPDZrkz:
7659 case VSQRTPDm:
7660 case VSQRTPDr:
7661 return true;
7662 }
7663 return false;
7664}
7665
7666bool isVFRCZPS(unsigned Opcode) {
7667 switch (Opcode) {
7668 case VFRCZPSYrm:
7669 case VFRCZPSYrr:
7670 case VFRCZPSrm:
7671 case VFRCZPSrr:
7672 return true;
7673 }
7674 return false;
7675}
7676
7677bool isVFNMADD213SS(unsigned Opcode) {
7678 switch (Opcode) {
7679 case VFNMADD213SSZm_Int:
7680 case VFNMADD213SSZmk_Int:
7681 case VFNMADD213SSZmkz_Int:
7682 case VFNMADD213SSZr_Int:
7683 case VFNMADD213SSZrb_Int:
7684 case VFNMADD213SSZrbk_Int:
7685 case VFNMADD213SSZrbkz_Int:
7686 case VFNMADD213SSZrk_Int:
7687 case VFNMADD213SSZrkz_Int:
7688 case VFNMADD213SSm_Int:
7689 case VFNMADD213SSr_Int:
7690 return true;
7691 }
7692 return false;
7693}
7694
7695bool isVPMOVDW(unsigned Opcode) {
7696 switch (Opcode) {
7697 case VPMOVDWZ128mr:
7698 case VPMOVDWZ128mrk:
7699 case VPMOVDWZ128rr:
7700 case VPMOVDWZ128rrk:
7701 case VPMOVDWZ128rrkz:
7702 case VPMOVDWZ256mr:
7703 case VPMOVDWZ256mrk:
7704 case VPMOVDWZ256rr:
7705 case VPMOVDWZ256rrk:
7706 case VPMOVDWZ256rrkz:
7707 case VPMOVDWZmr:
7708 case VPMOVDWZmrk:
7709 case VPMOVDWZrr:
7710 case VPMOVDWZrrk:
7711 case VPMOVDWZrrkz:
7712 return true;
7713 }
7714 return false;
7715}
7716
7717bool isVCVTPH2HF8S(unsigned Opcode) {
7718 switch (Opcode) {
7719 case VCVTPH2HF8SZ128rm:
7720 case VCVTPH2HF8SZ128rmb:
7721 case VCVTPH2HF8SZ128rmbk:
7722 case VCVTPH2HF8SZ128rmbkz:
7723 case VCVTPH2HF8SZ128rmk:
7724 case VCVTPH2HF8SZ128rmkz:
7725 case VCVTPH2HF8SZ128rr:
7726 case VCVTPH2HF8SZ128rrk:
7727 case VCVTPH2HF8SZ128rrkz:
7728 case VCVTPH2HF8SZ256rm:
7729 case VCVTPH2HF8SZ256rmb:
7730 case VCVTPH2HF8SZ256rmbk:
7731 case VCVTPH2HF8SZ256rmbkz:
7732 case VCVTPH2HF8SZ256rmk:
7733 case VCVTPH2HF8SZ256rmkz:
7734 case VCVTPH2HF8SZ256rr:
7735 case VCVTPH2HF8SZ256rrk:
7736 case VCVTPH2HF8SZ256rrkz:
7737 case VCVTPH2HF8SZrm:
7738 case VCVTPH2HF8SZrmb:
7739 case VCVTPH2HF8SZrmbk:
7740 case VCVTPH2HF8SZrmbkz:
7741 case VCVTPH2HF8SZrmk:
7742 case VCVTPH2HF8SZrmkz:
7743 case VCVTPH2HF8SZrr:
7744 case VCVTPH2HF8SZrrk:
7745 case VCVTPH2HF8SZrrkz:
7746 return true;
7747 }
7748 return false;
7749}
7750
7751bool isVPSHRDVQ(unsigned Opcode) {
7752 switch (Opcode) {
7753 case VPSHRDVQZ128m:
7754 case VPSHRDVQZ128mb:
7755 case VPSHRDVQZ128mbk:
7756 case VPSHRDVQZ128mbkz:
7757 case VPSHRDVQZ128mk:
7758 case VPSHRDVQZ128mkz:
7759 case VPSHRDVQZ128r:
7760 case VPSHRDVQZ128rk:
7761 case VPSHRDVQZ128rkz:
7762 case VPSHRDVQZ256m:
7763 case VPSHRDVQZ256mb:
7764 case VPSHRDVQZ256mbk:
7765 case VPSHRDVQZ256mbkz:
7766 case VPSHRDVQZ256mk:
7767 case VPSHRDVQZ256mkz:
7768 case VPSHRDVQZ256r:
7769 case VPSHRDVQZ256rk:
7770 case VPSHRDVQZ256rkz:
7771 case VPSHRDVQZm:
7772 case VPSHRDVQZmb:
7773 case VPSHRDVQZmbk:
7774 case VPSHRDVQZmbkz:
7775 case VPSHRDVQZmk:
7776 case VPSHRDVQZmkz:
7777 case VPSHRDVQZr:
7778 case VPSHRDVQZrk:
7779 case VPSHRDVQZrkz:
7780 return true;
7781 }
7782 return false;
7783}
7784
7785bool isVBROADCASTSD(unsigned Opcode) {
7786 switch (Opcode) {
7787 case VBROADCASTSDYrm:
7788 case VBROADCASTSDYrr:
7789 case VBROADCASTSDZ256rm:
7790 case VBROADCASTSDZ256rmk:
7791 case VBROADCASTSDZ256rmkz:
7792 case VBROADCASTSDZ256rr:
7793 case VBROADCASTSDZ256rrk:
7794 case VBROADCASTSDZ256rrkz:
7795 case VBROADCASTSDZrm:
7796 case VBROADCASTSDZrmk:
7797 case VBROADCASTSDZrmkz:
7798 case VBROADCASTSDZrr:
7799 case VBROADCASTSDZrrk:
7800 case VBROADCASTSDZrrkz:
7801 return true;
7802 }
7803 return false;
7804}
7805
7806bool isVSHUFPD(unsigned Opcode) {
7807 switch (Opcode) {
7808 case VSHUFPDYrmi:
7809 case VSHUFPDYrri:
7810 case VSHUFPDZ128rmbi:
7811 case VSHUFPDZ128rmbik:
7812 case VSHUFPDZ128rmbikz:
7813 case VSHUFPDZ128rmi:
7814 case VSHUFPDZ128rmik:
7815 case VSHUFPDZ128rmikz:
7816 case VSHUFPDZ128rri:
7817 case VSHUFPDZ128rrik:
7818 case VSHUFPDZ128rrikz:
7819 case VSHUFPDZ256rmbi:
7820 case VSHUFPDZ256rmbik:
7821 case VSHUFPDZ256rmbikz:
7822 case VSHUFPDZ256rmi:
7823 case VSHUFPDZ256rmik:
7824 case VSHUFPDZ256rmikz:
7825 case VSHUFPDZ256rri:
7826 case VSHUFPDZ256rrik:
7827 case VSHUFPDZ256rrikz:
7828 case VSHUFPDZrmbi:
7829 case VSHUFPDZrmbik:
7830 case VSHUFPDZrmbikz:
7831 case VSHUFPDZrmi:
7832 case VSHUFPDZrmik:
7833 case VSHUFPDZrmikz:
7834 case VSHUFPDZrri:
7835 case VSHUFPDZrrik:
7836 case VSHUFPDZrrikz:
7837 case VSHUFPDrmi:
7838 case VSHUFPDrri:
7839 return true;
7840 }
7841 return false;
7842}
7843
7844bool isVPSUBSW(unsigned Opcode) {
7845 switch (Opcode) {
7846 case VPSUBSWYrm:
7847 case VPSUBSWYrr:
7848 case VPSUBSWZ128rm:
7849 case VPSUBSWZ128rmk:
7850 case VPSUBSWZ128rmkz:
7851 case VPSUBSWZ128rr:
7852 case VPSUBSWZ128rrk:
7853 case VPSUBSWZ128rrkz:
7854 case VPSUBSWZ256rm:
7855 case VPSUBSWZ256rmk:
7856 case VPSUBSWZ256rmkz:
7857 case VPSUBSWZ256rr:
7858 case VPSUBSWZ256rrk:
7859 case VPSUBSWZ256rrkz:
7860 case VPSUBSWZrm:
7861 case VPSUBSWZrmk:
7862 case VPSUBSWZrmkz:
7863 case VPSUBSWZrr:
7864 case VPSUBSWZrrk:
7865 case VPSUBSWZrrkz:
7866 case VPSUBSWrm:
7867 case VPSUBSWrr:
7868 return true;
7869 }
7870 return false;
7871}
7872
7873bool isKUNPCKBW(unsigned Opcode) {
7874 return Opcode == KUNPCKBWkk;
7875}
7876
7877bool isVPBLENDD(unsigned Opcode) {
7878 switch (Opcode) {
7879 case VPBLENDDYrmi:
7880 case VPBLENDDYrri:
7881 case VPBLENDDrmi:
7882 case VPBLENDDrri:
7883 return true;
7884 }
7885 return false;
7886}
7887
7888bool isUNPCKHPD(unsigned Opcode) {
7889 switch (Opcode) {
7890 case UNPCKHPDrm:
7891 case UNPCKHPDrr:
7892 return true;
7893 }
7894 return false;
7895}
7896
7897bool isVFNMADD231SD(unsigned Opcode) {
7898 switch (Opcode) {
7899 case VFNMADD231SDZm_Int:
7900 case VFNMADD231SDZmk_Int:
7901 case VFNMADD231SDZmkz_Int:
7902 case VFNMADD231SDZr_Int:
7903 case VFNMADD231SDZrb_Int:
7904 case VFNMADD231SDZrbk_Int:
7905 case VFNMADD231SDZrbkz_Int:
7906 case VFNMADD231SDZrk_Int:
7907 case VFNMADD231SDZrkz_Int:
7908 case VFNMADD231SDm_Int:
7909 case VFNMADD231SDr_Int:
7910 return true;
7911 }
7912 return false;
7913}
7914
7915bool isVPBROADCASTMW2D(unsigned Opcode) {
7916 switch (Opcode) {
7917 case VPBROADCASTMW2DZ128rr:
7918 case VPBROADCASTMW2DZ256rr:
7919 case VPBROADCASTMW2DZrr:
7920 return true;
7921 }
7922 return false;
7923}
7924
7925bool isVPMULTISHIFTQB(unsigned Opcode) {
7926 switch (Opcode) {
7927 case VPMULTISHIFTQBZ128rm:
7928 case VPMULTISHIFTQBZ128rmb:
7929 case VPMULTISHIFTQBZ128rmbk:
7930 case VPMULTISHIFTQBZ128rmbkz:
7931 case VPMULTISHIFTQBZ128rmk:
7932 case VPMULTISHIFTQBZ128rmkz:
7933 case VPMULTISHIFTQBZ128rr:
7934 case VPMULTISHIFTQBZ128rrk:
7935 case VPMULTISHIFTQBZ128rrkz:
7936 case VPMULTISHIFTQBZ256rm:
7937 case VPMULTISHIFTQBZ256rmb:
7938 case VPMULTISHIFTQBZ256rmbk:
7939 case VPMULTISHIFTQBZ256rmbkz:
7940 case VPMULTISHIFTQBZ256rmk:
7941 case VPMULTISHIFTQBZ256rmkz:
7942 case VPMULTISHIFTQBZ256rr:
7943 case VPMULTISHIFTQBZ256rrk:
7944 case VPMULTISHIFTQBZ256rrkz:
7945 case VPMULTISHIFTQBZrm:
7946 case VPMULTISHIFTQBZrmb:
7947 case VPMULTISHIFTQBZrmbk:
7948 case VPMULTISHIFTQBZrmbkz:
7949 case VPMULTISHIFTQBZrmk:
7950 case VPMULTISHIFTQBZrmkz:
7951 case VPMULTISHIFTQBZrr:
7952 case VPMULTISHIFTQBZrrk:
7953 case VPMULTISHIFTQBZrrkz:
7954 return true;
7955 }
7956 return false;
7957}
7958
7959bool isVP2INTERSECTQ(unsigned Opcode) {
7960 switch (Opcode) {
7961 case VP2INTERSECTQZ128rm:
7962 case VP2INTERSECTQZ128rmb:
7963 case VP2INTERSECTQZ128rr:
7964 case VP2INTERSECTQZ256rm:
7965 case VP2INTERSECTQZ256rmb:
7966 case VP2INTERSECTQZ256rr:
7967 case VP2INTERSECTQZrm:
7968 case VP2INTERSECTQZrmb:
7969 case VP2INTERSECTQZrr:
7970 return true;
7971 }
7972 return false;
7973}
7974
7975bool isVFNMSUB132BF16(unsigned Opcode) {
7976 switch (Opcode) {
7977 case VFNMSUB132BF16Z128m:
7978 case VFNMSUB132BF16Z128mb:
7979 case VFNMSUB132BF16Z128mbk:
7980 case VFNMSUB132BF16Z128mbkz:
7981 case VFNMSUB132BF16Z128mk:
7982 case VFNMSUB132BF16Z128mkz:
7983 case VFNMSUB132BF16Z128r:
7984 case VFNMSUB132BF16Z128rk:
7985 case VFNMSUB132BF16Z128rkz:
7986 case VFNMSUB132BF16Z256m:
7987 case VFNMSUB132BF16Z256mb:
7988 case VFNMSUB132BF16Z256mbk:
7989 case VFNMSUB132BF16Z256mbkz:
7990 case VFNMSUB132BF16Z256mk:
7991 case VFNMSUB132BF16Z256mkz:
7992 case VFNMSUB132BF16Z256r:
7993 case VFNMSUB132BF16Z256rk:
7994 case VFNMSUB132BF16Z256rkz:
7995 case VFNMSUB132BF16Zm:
7996 case VFNMSUB132BF16Zmb:
7997 case VFNMSUB132BF16Zmbk:
7998 case VFNMSUB132BF16Zmbkz:
7999 case VFNMSUB132BF16Zmk:
8000 case VFNMSUB132BF16Zmkz:
8001 case VFNMSUB132BF16Zr:
8002 case VFNMSUB132BF16Zrk:
8003 case VFNMSUB132BF16Zrkz:
8004 return true;
8005 }
8006 return false;
8007}
8008
8009bool isVFMADD213BF16(unsigned Opcode) {
8010 switch (Opcode) {
8011 case VFMADD213BF16Z128m:
8012 case VFMADD213BF16Z128mb:
8013 case VFMADD213BF16Z128mbk:
8014 case VFMADD213BF16Z128mbkz:
8015 case VFMADD213BF16Z128mk:
8016 case VFMADD213BF16Z128mkz:
8017 case VFMADD213BF16Z128r:
8018 case VFMADD213BF16Z128rk:
8019 case VFMADD213BF16Z128rkz:
8020 case VFMADD213BF16Z256m:
8021 case VFMADD213BF16Z256mb:
8022 case VFMADD213BF16Z256mbk:
8023 case VFMADD213BF16Z256mbkz:
8024 case VFMADD213BF16Z256mk:
8025 case VFMADD213BF16Z256mkz:
8026 case VFMADD213BF16Z256r:
8027 case VFMADD213BF16Z256rk:
8028 case VFMADD213BF16Z256rkz:
8029 case VFMADD213BF16Zm:
8030 case VFMADD213BF16Zmb:
8031 case VFMADD213BF16Zmbk:
8032 case VFMADD213BF16Zmbkz:
8033 case VFMADD213BF16Zmk:
8034 case VFMADD213BF16Zmkz:
8035 case VFMADD213BF16Zr:
8036 case VFMADD213BF16Zrk:
8037 case VFMADD213BF16Zrkz:
8038 return true;
8039 }
8040 return false;
8041}
8042
8043bool isVPUNPCKHWD(unsigned Opcode) {
8044 switch (Opcode) {
8045 case VPUNPCKHWDYrm:
8046 case VPUNPCKHWDYrr:
8047 case VPUNPCKHWDZ128rm:
8048 case VPUNPCKHWDZ128rmk:
8049 case VPUNPCKHWDZ128rmkz:
8050 case VPUNPCKHWDZ128rr:
8051 case VPUNPCKHWDZ128rrk:
8052 case VPUNPCKHWDZ128rrkz:
8053 case VPUNPCKHWDZ256rm:
8054 case VPUNPCKHWDZ256rmk:
8055 case VPUNPCKHWDZ256rmkz:
8056 case VPUNPCKHWDZ256rr:
8057 case VPUNPCKHWDZ256rrk:
8058 case VPUNPCKHWDZ256rrkz:
8059 case VPUNPCKHWDZrm:
8060 case VPUNPCKHWDZrmk:
8061 case VPUNPCKHWDZrmkz:
8062 case VPUNPCKHWDZrr:
8063 case VPUNPCKHWDZrrk:
8064 case VPUNPCKHWDZrrkz:
8065 case VPUNPCKHWDrm:
8066 case VPUNPCKHWDrr:
8067 return true;
8068 }
8069 return false;
8070}
8071
8072bool isVPERM2F128(unsigned Opcode) {
8073 switch (Opcode) {
8074 case VPERM2F128rmi:
8075 case VPERM2F128rri:
8076 return true;
8077 }
8078 return false;
8079}
8080
8081bool isINSD(unsigned Opcode) {
8082 return Opcode == INSL;
8083}
8084
8085bool isLFS(unsigned Opcode) {
8086 switch (Opcode) {
8087 case LFS16rm:
8088 case LFS32rm:
8089 case LFS64rm:
8090 return true;
8091 }
8092 return false;
8093}
8094
8095bool isFMULP(unsigned Opcode) {
8096 return Opcode == MUL_FPrST0;
8097}
8098
8099bool isCWD(unsigned Opcode) {
8100 return Opcode == CWD;
8101}
8102
8103bool isVDIVSS(unsigned Opcode) {
8104 switch (Opcode) {
8105 case VDIVSSZrm_Int:
8106 case VDIVSSZrmk_Int:
8107 case VDIVSSZrmkz_Int:
8108 case VDIVSSZrr_Int:
8109 case VDIVSSZrrb_Int:
8110 case VDIVSSZrrbk_Int:
8111 case VDIVSSZrrbkz_Int:
8112 case VDIVSSZrrk_Int:
8113 case VDIVSSZrrkz_Int:
8114 case VDIVSSrm_Int:
8115 case VDIVSSrr_Int:
8116 return true;
8117 }
8118 return false;
8119}
8120
8121bool isVPSRLQ(unsigned Opcode) {
8122 switch (Opcode) {
8123 case VPSRLQYri:
8124 case VPSRLQYrm:
8125 case VPSRLQYrr:
8126 case VPSRLQZ128mbi:
8127 case VPSRLQZ128mbik:
8128 case VPSRLQZ128mbikz:
8129 case VPSRLQZ128mi:
8130 case VPSRLQZ128mik:
8131 case VPSRLQZ128mikz:
8132 case VPSRLQZ128ri:
8133 case VPSRLQZ128rik:
8134 case VPSRLQZ128rikz:
8135 case VPSRLQZ128rm:
8136 case VPSRLQZ128rmk:
8137 case VPSRLQZ128rmkz:
8138 case VPSRLQZ128rr:
8139 case VPSRLQZ128rrk:
8140 case VPSRLQZ128rrkz:
8141 case VPSRLQZ256mbi:
8142 case VPSRLQZ256mbik:
8143 case VPSRLQZ256mbikz:
8144 case VPSRLQZ256mi:
8145 case VPSRLQZ256mik:
8146 case VPSRLQZ256mikz:
8147 case VPSRLQZ256ri:
8148 case VPSRLQZ256rik:
8149 case VPSRLQZ256rikz:
8150 case VPSRLQZ256rm:
8151 case VPSRLQZ256rmk:
8152 case VPSRLQZ256rmkz:
8153 case VPSRLQZ256rr:
8154 case VPSRLQZ256rrk:
8155 case VPSRLQZ256rrkz:
8156 case VPSRLQZmbi:
8157 case VPSRLQZmbik:
8158 case VPSRLQZmbikz:
8159 case VPSRLQZmi:
8160 case VPSRLQZmik:
8161 case VPSRLQZmikz:
8162 case VPSRLQZri:
8163 case VPSRLQZrik:
8164 case VPSRLQZrikz:
8165 case VPSRLQZrm:
8166 case VPSRLQZrmk:
8167 case VPSRLQZrmkz:
8168 case VPSRLQZrr:
8169 case VPSRLQZrrk:
8170 case VPSRLQZrrkz:
8171 case VPSRLQri:
8172 case VPSRLQrm:
8173 case VPSRLQrr:
8174 return true;
8175 }
8176 return false;
8177}
8178
8179bool isFSQRT(unsigned Opcode) {
8180 return Opcode == SQRT_F;
8181}
8182
8183bool isJRCXZ(unsigned Opcode) {
8184 return Opcode == JRCXZ;
8185}
8186
8187bool isVPMOVMSKB(unsigned Opcode) {
8188 switch (Opcode) {
8189 case VPMOVMSKBYrr:
8190 case VPMOVMSKBrr:
8191 return true;
8192 }
8193 return false;
8194}
8195
8196bool isAESDEC256KL(unsigned Opcode) {
8197 return Opcode == AESDEC256KL;
8198}
8199
8200bool isFLDENV(unsigned Opcode) {
8201 return Opcode == FLDENVm;
8202}
8203
8204bool isVPHSUBWD(unsigned Opcode) {
8205 switch (Opcode) {
8206 case VPHSUBWDrm:
8207 case VPHSUBWDrr:
8208 return true;
8209 }
8210 return false;
8211}
8212
8213bool isWBNOINVD(unsigned Opcode) {
8214 return Opcode == WBNOINVD;
8215}
8216
8217bool isVEXPANDPD(unsigned Opcode) {
8218 switch (Opcode) {
8219 case VEXPANDPDZ128rm:
8220 case VEXPANDPDZ128rmk:
8221 case VEXPANDPDZ128rmkz:
8222 case VEXPANDPDZ128rr:
8223 case VEXPANDPDZ128rrk:
8224 case VEXPANDPDZ128rrkz:
8225 case VEXPANDPDZ256rm:
8226 case VEXPANDPDZ256rmk:
8227 case VEXPANDPDZ256rmkz:
8228 case VEXPANDPDZ256rr:
8229 case VEXPANDPDZ256rrk:
8230 case VEXPANDPDZ256rrkz:
8231 case VEXPANDPDZrm:
8232 case VEXPANDPDZrmk:
8233 case VEXPANDPDZrmkz:
8234 case VEXPANDPDZrr:
8235 case VEXPANDPDZrrk:
8236 case VEXPANDPDZrrkz:
8237 return true;
8238 }
8239 return false;
8240}
8241
8242bool isFYL2XP1(unsigned Opcode) {
8243 return Opcode == FYL2XP1;
8244}
8245
8246bool isPREFETCHT2(unsigned Opcode) {
8247 return Opcode == PREFETCHT2;
8248}
8249
8250bool isVPDPBSUDS(unsigned Opcode) {
8251 switch (Opcode) {
8252 case VPDPBSUDSYrm:
8253 case VPDPBSUDSYrr:
8254 case VPDPBSUDSZ128rm:
8255 case VPDPBSUDSZ128rmb:
8256 case VPDPBSUDSZ128rmbk:
8257 case VPDPBSUDSZ128rmbkz:
8258 case VPDPBSUDSZ128rmk:
8259 case VPDPBSUDSZ128rmkz:
8260 case VPDPBSUDSZ128rr:
8261 case VPDPBSUDSZ128rrk:
8262 case VPDPBSUDSZ128rrkz:
8263 case VPDPBSUDSZ256rm:
8264 case VPDPBSUDSZ256rmb:
8265 case VPDPBSUDSZ256rmbk:
8266 case VPDPBSUDSZ256rmbkz:
8267 case VPDPBSUDSZ256rmk:
8268 case VPDPBSUDSZ256rmkz:
8269 case VPDPBSUDSZ256rr:
8270 case VPDPBSUDSZ256rrk:
8271 case VPDPBSUDSZ256rrkz:
8272 case VPDPBSUDSZrm:
8273 case VPDPBSUDSZrmb:
8274 case VPDPBSUDSZrmbk:
8275 case VPDPBSUDSZrmbkz:
8276 case VPDPBSUDSZrmk:
8277 case VPDPBSUDSZrmkz:
8278 case VPDPBSUDSZrr:
8279 case VPDPBSUDSZrrk:
8280 case VPDPBSUDSZrrkz:
8281 case VPDPBSUDSrm:
8282 case VPDPBSUDSrr:
8283 return true;
8284 }
8285 return false;
8286}
8287
8288bool isVSHA512MSG2(unsigned Opcode) {
8289 return Opcode == VSHA512MSG2rr;
8290}
8291
8292bool isPMULHUW(unsigned Opcode) {
8293 switch (Opcode) {
8294 case MMX_PMULHUWrm:
8295 case MMX_PMULHUWrr:
8296 case PMULHUWrm:
8297 case PMULHUWrr:
8298 return true;
8299 }
8300 return false;
8301}
8302
8303bool isKANDNB(unsigned Opcode) {
8304 return Opcode == KANDNBkk;
8305}
8306
8307bool isVCVTUW2PH(unsigned Opcode) {
8308 switch (Opcode) {
8309 case VCVTUW2PHZ128rm:
8310 case VCVTUW2PHZ128rmb:
8311 case VCVTUW2PHZ128rmbk:
8312 case VCVTUW2PHZ128rmbkz:
8313 case VCVTUW2PHZ128rmk:
8314 case VCVTUW2PHZ128rmkz:
8315 case VCVTUW2PHZ128rr:
8316 case VCVTUW2PHZ128rrk:
8317 case VCVTUW2PHZ128rrkz:
8318 case VCVTUW2PHZ256rm:
8319 case VCVTUW2PHZ256rmb:
8320 case VCVTUW2PHZ256rmbk:
8321 case VCVTUW2PHZ256rmbkz:
8322 case VCVTUW2PHZ256rmk:
8323 case VCVTUW2PHZ256rmkz:
8324 case VCVTUW2PHZ256rr:
8325 case VCVTUW2PHZ256rrk:
8326 case VCVTUW2PHZ256rrkz:
8327 case VCVTUW2PHZrm:
8328 case VCVTUW2PHZrmb:
8329 case VCVTUW2PHZrmbk:
8330 case VCVTUW2PHZrmbkz:
8331 case VCVTUW2PHZrmk:
8332 case VCVTUW2PHZrmkz:
8333 case VCVTUW2PHZrr:
8334 case VCVTUW2PHZrrb:
8335 case VCVTUW2PHZrrbk:
8336 case VCVTUW2PHZrrbkz:
8337 case VCVTUW2PHZrrk:
8338 case VCVTUW2PHZrrkz:
8339 return true;
8340 }
8341 return false;
8342}
8343
8344bool isAESDECWIDE256KL(unsigned Opcode) {
8345 return Opcode == AESDECWIDE256KL;
8346}
8347
8348bool isVPGATHERDD(unsigned Opcode) {
8349 switch (Opcode) {
8350 case VPGATHERDDYrm:
8351 case VPGATHERDDZ128rm:
8352 case VPGATHERDDZ256rm:
8353 case VPGATHERDDZrm:
8354 case VPGATHERDDrm:
8355 return true;
8356 }
8357 return false;
8358}
8359
8360bool isVREDUCESH(unsigned Opcode) {
8361 switch (Opcode) {
8362 case VREDUCESHZrmi:
8363 case VREDUCESHZrmik:
8364 case VREDUCESHZrmikz:
8365 case VREDUCESHZrri:
8366 case VREDUCESHZrrib:
8367 case VREDUCESHZrribk:
8368 case VREDUCESHZrribkz:
8369 case VREDUCESHZrrik:
8370 case VREDUCESHZrrikz:
8371 return true;
8372 }
8373 return false;
8374}
8375
8376bool isPOPFQ(unsigned Opcode) {
8377 return Opcode == POPF64;
8378}
8379
8380bool isPAVGUSB(unsigned Opcode) {
8381 switch (Opcode) {
8382 case PAVGUSBrm:
8383 case PAVGUSBrr:
8384 return true;
8385 }
8386 return false;
8387}
8388
8389bool isVALIGND(unsigned Opcode) {
8390 switch (Opcode) {
8391 case VALIGNDZ128rmbi:
8392 case VALIGNDZ128rmbik:
8393 case VALIGNDZ128rmbikz:
8394 case VALIGNDZ128rmi:
8395 case VALIGNDZ128rmik:
8396 case VALIGNDZ128rmikz:
8397 case VALIGNDZ128rri:
8398 case VALIGNDZ128rrik:
8399 case VALIGNDZ128rrikz:
8400 case VALIGNDZ256rmbi:
8401 case VALIGNDZ256rmbik:
8402 case VALIGNDZ256rmbikz:
8403 case VALIGNDZ256rmi:
8404 case VALIGNDZ256rmik:
8405 case VALIGNDZ256rmikz:
8406 case VALIGNDZ256rri:
8407 case VALIGNDZ256rrik:
8408 case VALIGNDZ256rrikz:
8409 case VALIGNDZrmbi:
8410 case VALIGNDZrmbik:
8411 case VALIGNDZrmbikz:
8412 case VALIGNDZrmi:
8413 case VALIGNDZrmik:
8414 case VALIGNDZrmikz:
8415 case VALIGNDZrri:
8416 case VALIGNDZrrik:
8417 case VALIGNDZrrikz:
8418 return true;
8419 }
8420 return false;
8421}
8422
8423bool isVPHMINPOSUW(unsigned Opcode) {
8424 switch (Opcode) {
8425 case VPHMINPOSUWrm:
8426 case VPHMINPOSUWrr:
8427 return true;
8428 }
8429 return false;
8430}
8431
8432bool isLIDTD(unsigned Opcode) {
8433 return Opcode == LIDT32m;
8434}
8435
8436bool isVPERMT2PD(unsigned Opcode) {
8437 switch (Opcode) {
8438 case VPERMT2PDZ128rm:
8439 case VPERMT2PDZ128rmb:
8440 case VPERMT2PDZ128rmbk:
8441 case VPERMT2PDZ128rmbkz:
8442 case VPERMT2PDZ128rmk:
8443 case VPERMT2PDZ128rmkz:
8444 case VPERMT2PDZ128rr:
8445 case VPERMT2PDZ128rrk:
8446 case VPERMT2PDZ128rrkz:
8447 case VPERMT2PDZ256rm:
8448 case VPERMT2PDZ256rmb:
8449 case VPERMT2PDZ256rmbk:
8450 case VPERMT2PDZ256rmbkz:
8451 case VPERMT2PDZ256rmk:
8452 case VPERMT2PDZ256rmkz:
8453 case VPERMT2PDZ256rr:
8454 case VPERMT2PDZ256rrk:
8455 case VPERMT2PDZ256rrkz:
8456 case VPERMT2PDZrm:
8457 case VPERMT2PDZrmb:
8458 case VPERMT2PDZrmbk:
8459 case VPERMT2PDZrmbkz:
8460 case VPERMT2PDZrmk:
8461 case VPERMT2PDZrmkz:
8462 case VPERMT2PDZrr:
8463 case VPERMT2PDZrrk:
8464 case VPERMT2PDZrrkz:
8465 return true;
8466 }
8467 return false;
8468}
8469
8470bool isVMLAUNCH(unsigned Opcode) {
8471 return Opcode == VMLAUNCH;
8472}
8473
8474bool isVPXORQ(unsigned Opcode) {
8475 switch (Opcode) {
8476 case VPXORQZ128rm:
8477 case VPXORQZ128rmb:
8478 case VPXORQZ128rmbk:
8479 case VPXORQZ128rmbkz:
8480 case VPXORQZ128rmk:
8481 case VPXORQZ128rmkz:
8482 case VPXORQZ128rr:
8483 case VPXORQZ128rrk:
8484 case VPXORQZ128rrkz:
8485 case VPXORQZ256rm:
8486 case VPXORQZ256rmb:
8487 case VPXORQZ256rmbk:
8488 case VPXORQZ256rmbkz:
8489 case VPXORQZ256rmk:
8490 case VPXORQZ256rmkz:
8491 case VPXORQZ256rr:
8492 case VPXORQZ256rrk:
8493 case VPXORQZ256rrkz:
8494 case VPXORQZrm:
8495 case VPXORQZrmb:
8496 case VPXORQZrmbk:
8497 case VPXORQZrmbkz:
8498 case VPXORQZrmk:
8499 case VPXORQZrmkz:
8500 case VPXORQZrr:
8501 case VPXORQZrrk:
8502 case VPXORQZrrkz:
8503 return true;
8504 }
8505 return false;
8506}
8507
8508bool isMOVNTDQ(unsigned Opcode) {
8509 return Opcode == MOVNTDQmr;
8510}
8511
8512bool isPOP2P(unsigned Opcode) {
8513 return Opcode == POP2P;
8514}
8515
8516bool isVADDPD(unsigned Opcode) {
8517 switch (Opcode) {
8518 case VADDPDYrm:
8519 case VADDPDYrr:
8520 case VADDPDZ128rm:
8521 case VADDPDZ128rmb:
8522 case VADDPDZ128rmbk:
8523 case VADDPDZ128rmbkz:
8524 case VADDPDZ128rmk:
8525 case VADDPDZ128rmkz:
8526 case VADDPDZ128rr:
8527 case VADDPDZ128rrk:
8528 case VADDPDZ128rrkz:
8529 case VADDPDZ256rm:
8530 case VADDPDZ256rmb:
8531 case VADDPDZ256rmbk:
8532 case VADDPDZ256rmbkz:
8533 case VADDPDZ256rmk:
8534 case VADDPDZ256rmkz:
8535 case VADDPDZ256rr:
8536 case VADDPDZ256rrk:
8537 case VADDPDZ256rrkz:
8538 case VADDPDZrm:
8539 case VADDPDZrmb:
8540 case VADDPDZrmbk:
8541 case VADDPDZrmbkz:
8542 case VADDPDZrmk:
8543 case VADDPDZrmkz:
8544 case VADDPDZrr:
8545 case VADDPDZrrb:
8546 case VADDPDZrrbk:
8547 case VADDPDZrrbkz:
8548 case VADDPDZrrk:
8549 case VADDPDZrrkz:
8550 case VADDPDrm:
8551 case VADDPDrr:
8552 return true;
8553 }
8554 return false;
8555}
8556
8557bool isSMSW(unsigned Opcode) {
8558 switch (Opcode) {
8559 case SMSW16m:
8560 case SMSW16r:
8561 case SMSW32r:
8562 case SMSW64r:
8563 return true;
8564 }
8565 return false;
8566}
8567
8568bool isVEXP2PD(unsigned Opcode) {
8569 switch (Opcode) {
8570 case VEXP2PDZm:
8571 case VEXP2PDZmb:
8572 case VEXP2PDZmbk:
8573 case VEXP2PDZmbkz:
8574 case VEXP2PDZmk:
8575 case VEXP2PDZmkz:
8576 case VEXP2PDZr:
8577 case VEXP2PDZrb:
8578 case VEXP2PDZrbk:
8579 case VEXP2PDZrbkz:
8580 case VEXP2PDZrk:
8581 case VEXP2PDZrkz:
8582 return true;
8583 }
8584 return false;
8585}
8586
8587bool isPMULUDQ(unsigned Opcode) {
8588 switch (Opcode) {
8589 case MMX_PMULUDQrm:
8590 case MMX_PMULUDQrr:
8591 case PMULUDQrm:
8592 case PMULUDQrr:
8593 return true;
8594 }
8595 return false;
8596}
8597
8598bool isIRET(unsigned Opcode) {
8599 return Opcode == IRET16;
8600}
8601
8602bool isMULPS(unsigned Opcode) {
8603 switch (Opcode) {
8604 case MULPSrm:
8605 case MULPSrr:
8606 return true;
8607 }
8608 return false;
8609}
8610
8611bool isTDPBF8PS(unsigned Opcode) {
8612 return Opcode == TDPBF8PS;
8613}
8614
8615bool isVFNMSUBPD(unsigned Opcode) {
8616 switch (Opcode) {
8617 case VFNMSUBPD4Ymr:
8618 case VFNMSUBPD4Yrm:
8619 case VFNMSUBPD4Yrr:
8620 case VFNMSUBPD4Yrr_REV:
8621 case VFNMSUBPD4mr:
8622 case VFNMSUBPD4rm:
8623 case VFNMSUBPD4rr:
8624 case VFNMSUBPD4rr_REV:
8625 return true;
8626 }
8627 return false;
8628}
8629
8630bool isPHADDW(unsigned Opcode) {
8631 switch (Opcode) {
8632 case MMX_PHADDWrm:
8633 case MMX_PHADDWrr:
8634 case PHADDWrm:
8635 case PHADDWrr:
8636 return true;
8637 }
8638 return false;
8639}
8640
8641bool isRDSEED(unsigned Opcode) {
8642 switch (Opcode) {
8643 case RDSEED16r:
8644 case RDSEED32r:
8645 case RDSEED64r:
8646 return true;
8647 }
8648 return false;
8649}
8650
8651bool isVPSHLW(unsigned Opcode) {
8652 switch (Opcode) {
8653 case VPSHLWmr:
8654 case VPSHLWrm:
8655 case VPSHLWrr:
8656 case VPSHLWrr_REV:
8657 return true;
8658 }
8659 return false;
8660}
8661
8662bool isRMPUPDATE(unsigned Opcode) {
8663 return Opcode == RMPUPDATE;
8664}
8665
8666bool isVFMADD231PH(unsigned Opcode) {
8667 switch (Opcode) {
8668 case VFMADD231PHZ128m:
8669 case VFMADD231PHZ128mb:
8670 case VFMADD231PHZ128mbk:
8671 case VFMADD231PHZ128mbkz:
8672 case VFMADD231PHZ128mk:
8673 case VFMADD231PHZ128mkz:
8674 case VFMADD231PHZ128r:
8675 case VFMADD231PHZ128rk:
8676 case VFMADD231PHZ128rkz:
8677 case VFMADD231PHZ256m:
8678 case VFMADD231PHZ256mb:
8679 case VFMADD231PHZ256mbk:
8680 case VFMADD231PHZ256mbkz:
8681 case VFMADD231PHZ256mk:
8682 case VFMADD231PHZ256mkz:
8683 case VFMADD231PHZ256r:
8684 case VFMADD231PHZ256rk:
8685 case VFMADD231PHZ256rkz:
8686 case VFMADD231PHZm:
8687 case VFMADD231PHZmb:
8688 case VFMADD231PHZmbk:
8689 case VFMADD231PHZmbkz:
8690 case VFMADD231PHZmk:
8691 case VFMADD231PHZmkz:
8692 case VFMADD231PHZr:
8693 case VFMADD231PHZrb:
8694 case VFMADD231PHZrbk:
8695 case VFMADD231PHZrbkz:
8696 case VFMADD231PHZrk:
8697 case VFMADD231PHZrkz:
8698 return true;
8699 }
8700 return false;
8701}
8702
8703bool isVPSHAD(unsigned Opcode) {
8704 switch (Opcode) {
8705 case VPSHADmr:
8706 case VPSHADrm:
8707 case VPSHADrr:
8708 case VPSHADrr_REV:
8709 return true;
8710 }
8711 return false;
8712}
8713
8714bool isCLWB(unsigned Opcode) {
8715 return Opcode == CLWB;
8716}
8717
8718bool isPSUBUSB(unsigned Opcode) {
8719 switch (Opcode) {
8720 case MMX_PSUBUSBrm:
8721 case MMX_PSUBUSBrr:
8722 case PSUBUSBrm:
8723 case PSUBUSBrr:
8724 return true;
8725 }
8726 return false;
8727}
8728
8729bool isVCVTTSD2USI(unsigned Opcode) {
8730 switch (Opcode) {
8731 case VCVTTSD2USI64Zrm_Int:
8732 case VCVTTSD2USI64Zrr_Int:
8733 case VCVTTSD2USI64Zrrb_Int:
8734 case VCVTTSD2USIZrm_Int:
8735 case VCVTTSD2USIZrr_Int:
8736 case VCVTTSD2USIZrrb_Int:
8737 return true;
8738 }
8739 return false;
8740}
8741
8742bool isVEXTRACTPS(unsigned Opcode) {
8743 switch (Opcode) {
8744 case VEXTRACTPSZmri:
8745 case VEXTRACTPSZrri:
8746 case VEXTRACTPSmri:
8747 case VEXTRACTPSrri:
8748 return true;
8749 }
8750 return false;
8751}
8752
8753bool isMOVLPD(unsigned Opcode) {
8754 switch (Opcode) {
8755 case MOVLPDmr:
8756 case MOVLPDrm:
8757 return true;
8758 }
8759 return false;
8760}
8761
8762bool isLGDTD(unsigned Opcode) {
8763 return Opcode == LGDT32m;
8764}
8765
8766bool isVPBROADCASTMB2Q(unsigned Opcode) {
8767 switch (Opcode) {
8768 case VPBROADCASTMB2QZ128rr:
8769 case VPBROADCASTMB2QZ256rr:
8770 case VPBROADCASTMB2QZrr:
8771 return true;
8772 }
8773 return false;
8774}
8775
8776bool isOUT(unsigned Opcode) {
8777 switch (Opcode) {
8778 case OUT16ir:
8779 case OUT16rr:
8780 case OUT32ir:
8781 case OUT32rr:
8782 case OUT8ir:
8783 case OUT8rr:
8784 return true;
8785 }
8786 return false;
8787}
8788
8789bool isVMSAVE(unsigned Opcode) {
8790 switch (Opcode) {
8791 case VMSAVE32:
8792 case VMSAVE64:
8793 return true;
8794 }
8795 return false;
8796}
8797
8798bool isVCVTQQ2PD(unsigned Opcode) {
8799 switch (Opcode) {
8800 case VCVTQQ2PDZ128rm:
8801 case VCVTQQ2PDZ128rmb:
8802 case VCVTQQ2PDZ128rmbk:
8803 case VCVTQQ2PDZ128rmbkz:
8804 case VCVTQQ2PDZ128rmk:
8805 case VCVTQQ2PDZ128rmkz:
8806 case VCVTQQ2PDZ128rr:
8807 case VCVTQQ2PDZ128rrk:
8808 case VCVTQQ2PDZ128rrkz:
8809 case VCVTQQ2PDZ256rm:
8810 case VCVTQQ2PDZ256rmb:
8811 case VCVTQQ2PDZ256rmbk:
8812 case VCVTQQ2PDZ256rmbkz:
8813 case VCVTQQ2PDZ256rmk:
8814 case VCVTQQ2PDZ256rmkz:
8815 case VCVTQQ2PDZ256rr:
8816 case VCVTQQ2PDZ256rrk:
8817 case VCVTQQ2PDZ256rrkz:
8818 case VCVTQQ2PDZrm:
8819 case VCVTQQ2PDZrmb:
8820 case VCVTQQ2PDZrmbk:
8821 case VCVTQQ2PDZrmbkz:
8822 case VCVTQQ2PDZrmk:
8823 case VCVTQQ2PDZrmkz:
8824 case VCVTQQ2PDZrr:
8825 case VCVTQQ2PDZrrb:
8826 case VCVTQQ2PDZrrbk:
8827 case VCVTQQ2PDZrrbkz:
8828 case VCVTQQ2PDZrrk:
8829 case VCVTQQ2PDZrrkz:
8830 return true;
8831 }
8832 return false;
8833}
8834
8835bool isVFMADD213PH(unsigned Opcode) {
8836 switch (Opcode) {
8837 case VFMADD213PHZ128m:
8838 case VFMADD213PHZ128mb:
8839 case VFMADD213PHZ128mbk:
8840 case VFMADD213PHZ128mbkz:
8841 case VFMADD213PHZ128mk:
8842 case VFMADD213PHZ128mkz:
8843 case VFMADD213PHZ128r:
8844 case VFMADD213PHZ128rk:
8845 case VFMADD213PHZ128rkz:
8846 case VFMADD213PHZ256m:
8847 case VFMADD213PHZ256mb:
8848 case VFMADD213PHZ256mbk:
8849 case VFMADD213PHZ256mbkz:
8850 case VFMADD213PHZ256mk:
8851 case VFMADD213PHZ256mkz:
8852 case VFMADD213PHZ256r:
8853 case VFMADD213PHZ256rk:
8854 case VFMADD213PHZ256rkz:
8855 case VFMADD213PHZm:
8856 case VFMADD213PHZmb:
8857 case VFMADD213PHZmbk:
8858 case VFMADD213PHZmbkz:
8859 case VFMADD213PHZmk:
8860 case VFMADD213PHZmkz:
8861 case VFMADD213PHZr:
8862 case VFMADD213PHZrb:
8863 case VFMADD213PHZrbk:
8864 case VFMADD213PHZrbkz:
8865 case VFMADD213PHZrk:
8866 case VFMADD213PHZrkz:
8867 return true;
8868 }
8869 return false;
8870}
8871
8872bool isFCMOVBE(unsigned Opcode) {
8873 return Opcode == CMOVBE_F;
8874}
8875
8876bool isMOVSHDUP(unsigned Opcode) {
8877 switch (Opcode) {
8878 case MOVSHDUPrm:
8879 case MOVSHDUPrr:
8880 return true;
8881 }
8882 return false;
8883}
8884
8885bool isVPMOVUSQB(unsigned Opcode) {
8886 switch (Opcode) {
8887 case VPMOVUSQBZ128mr:
8888 case VPMOVUSQBZ128mrk:
8889 case VPMOVUSQBZ128rr:
8890 case VPMOVUSQBZ128rrk:
8891 case VPMOVUSQBZ128rrkz:
8892 case VPMOVUSQBZ256mr:
8893 case VPMOVUSQBZ256mrk:
8894 case VPMOVUSQBZ256rr:
8895 case VPMOVUSQBZ256rrk:
8896 case VPMOVUSQBZ256rrkz:
8897 case VPMOVUSQBZmr:
8898 case VPMOVUSQBZmrk:
8899 case VPMOVUSQBZrr:
8900 case VPMOVUSQBZrrk:
8901 case VPMOVUSQBZrrkz:
8902 return true;
8903 }
8904 return false;
8905}
8906
8907bool isFIST(unsigned Opcode) {
8908 switch (Opcode) {
8909 case IST_F16m:
8910 case IST_F32m:
8911 return true;
8912 }
8913 return false;
8914}
8915
8916bool isHADDPD(unsigned Opcode) {
8917 switch (Opcode) {
8918 case HADDPDrm:
8919 case HADDPDrr:
8920 return true;
8921 }
8922 return false;
8923}
8924
8925bool isPACKSSWB(unsigned Opcode) {
8926 switch (Opcode) {
8927 case MMX_PACKSSWBrm:
8928 case MMX_PACKSSWBrr:
8929 case PACKSSWBrm:
8930 case PACKSSWBrr:
8931 return true;
8932 }
8933 return false;
8934}
8935
8936bool isVPMACSSDQH(unsigned Opcode) {
8937 switch (Opcode) {
8938 case VPMACSSDQHrm:
8939 case VPMACSSDQHrr:
8940 return true;
8941 }
8942 return false;
8943}
8944
8945bool isVFNMSUB132SD(unsigned Opcode) {
8946 switch (Opcode) {
8947 case VFNMSUB132SDZm_Int:
8948 case VFNMSUB132SDZmk_Int:
8949 case VFNMSUB132SDZmkz_Int:
8950 case VFNMSUB132SDZr_Int:
8951 case VFNMSUB132SDZrb_Int:
8952 case VFNMSUB132SDZrbk_Int:
8953 case VFNMSUB132SDZrbkz_Int:
8954 case VFNMSUB132SDZrk_Int:
8955 case VFNMSUB132SDZrkz_Int:
8956 case VFNMSUB132SDm_Int:
8957 case VFNMSUB132SDr_Int:
8958 return true;
8959 }
8960 return false;
8961}
8962
8963bool isVPMASKMOVQ(unsigned Opcode) {
8964 switch (Opcode) {
8965 case VPMASKMOVQYmr:
8966 case VPMASKMOVQYrm:
8967 case VPMASKMOVQmr:
8968 case VPMASKMOVQrm:
8969 return true;
8970 }
8971 return false;
8972}
8973
8974bool isVCOMPRESSPD(unsigned Opcode) {
8975 switch (Opcode) {
8976 case VCOMPRESSPDZ128mr:
8977 case VCOMPRESSPDZ128mrk:
8978 case VCOMPRESSPDZ128rr:
8979 case VCOMPRESSPDZ128rrk:
8980 case VCOMPRESSPDZ128rrkz:
8981 case VCOMPRESSPDZ256mr:
8982 case VCOMPRESSPDZ256mrk:
8983 case VCOMPRESSPDZ256rr:
8984 case VCOMPRESSPDZ256rrk:
8985 case VCOMPRESSPDZ256rrkz:
8986 case VCOMPRESSPDZmr:
8987 case VCOMPRESSPDZmrk:
8988 case VCOMPRESSPDZrr:
8989 case VCOMPRESSPDZrrk:
8990 case VCOMPRESSPDZrrkz:
8991 return true;
8992 }
8993 return false;
8994}
8995
8996bool isVFMADD213SS(unsigned Opcode) {
8997 switch (Opcode) {
8998 case VFMADD213SSZm_Int:
8999 case VFMADD213SSZmk_Int:
9000 case VFMADD213SSZmkz_Int:
9001 case VFMADD213SSZr_Int:
9002 case VFMADD213SSZrb_Int:
9003 case VFMADD213SSZrbk_Int:
9004 case VFMADD213SSZrbkz_Int:
9005 case VFMADD213SSZrk_Int:
9006 case VFMADD213SSZrkz_Int:
9007 case VFMADD213SSm_Int:
9008 case VFMADD213SSr_Int:
9009 return true;
9010 }
9011 return false;
9012}
9013
9014bool isVPCMPQ(unsigned Opcode) {
9015 switch (Opcode) {
9016 case VPCMPQZ128rmbi:
9017 case VPCMPQZ128rmbik:
9018 case VPCMPQZ128rmi:
9019 case VPCMPQZ128rmik:
9020 case VPCMPQZ128rri:
9021 case VPCMPQZ128rrik:
9022 case VPCMPQZ256rmbi:
9023 case VPCMPQZ256rmbik:
9024 case VPCMPQZ256rmi:
9025 case VPCMPQZ256rmik:
9026 case VPCMPQZ256rri:
9027 case VPCMPQZ256rrik:
9028 case VPCMPQZrmbi:
9029 case VPCMPQZrmbik:
9030 case VPCMPQZrmi:
9031 case VPCMPQZrmik:
9032 case VPCMPQZrri:
9033 case VPCMPQZrrik:
9034 return true;
9035 }
9036 return false;
9037}
9038
9039bool isVADDSH(unsigned Opcode) {
9040 switch (Opcode) {
9041 case VADDSHZrm_Int:
9042 case VADDSHZrmk_Int:
9043 case VADDSHZrmkz_Int:
9044 case VADDSHZrr_Int:
9045 case VADDSHZrrb_Int:
9046 case VADDSHZrrbk_Int:
9047 case VADDSHZrrbkz_Int:
9048 case VADDSHZrrk_Int:
9049 case VADDSHZrrkz_Int:
9050 return true;
9051 }
9052 return false;
9053}
9054
9055bool isVFNMADDSD(unsigned Opcode) {
9056 switch (Opcode) {
9057 case VFNMADDSD4mr:
9058 case VFNMADDSD4rm:
9059 case VFNMADDSD4rr:
9060 case VFNMADDSD4rr_REV:
9061 return true;
9062 }
9063 return false;
9064}
9065
9066bool isUMWAIT(unsigned Opcode) {
9067 return Opcode == UMWAIT;
9068}
9069
9070bool isVPUNPCKHDQ(unsigned Opcode) {
9071 switch (Opcode) {
9072 case VPUNPCKHDQYrm:
9073 case VPUNPCKHDQYrr:
9074 case VPUNPCKHDQZ128rm:
9075 case VPUNPCKHDQZ128rmb:
9076 case VPUNPCKHDQZ128rmbk:
9077 case VPUNPCKHDQZ128rmbkz:
9078 case VPUNPCKHDQZ128rmk:
9079 case VPUNPCKHDQZ128rmkz:
9080 case VPUNPCKHDQZ128rr:
9081 case VPUNPCKHDQZ128rrk:
9082 case VPUNPCKHDQZ128rrkz:
9083 case VPUNPCKHDQZ256rm:
9084 case VPUNPCKHDQZ256rmb:
9085 case VPUNPCKHDQZ256rmbk:
9086 case VPUNPCKHDQZ256rmbkz:
9087 case VPUNPCKHDQZ256rmk:
9088 case VPUNPCKHDQZ256rmkz:
9089 case VPUNPCKHDQZ256rr:
9090 case VPUNPCKHDQZ256rrk:
9091 case VPUNPCKHDQZ256rrkz:
9092 case VPUNPCKHDQZrm:
9093 case VPUNPCKHDQZrmb:
9094 case VPUNPCKHDQZrmbk:
9095 case VPUNPCKHDQZrmbkz:
9096 case VPUNPCKHDQZrmk:
9097 case VPUNPCKHDQZrmkz:
9098 case VPUNPCKHDQZrr:
9099 case VPUNPCKHDQZrrk:
9100 case VPUNPCKHDQZrrkz:
9101 case VPUNPCKHDQrm:
9102 case VPUNPCKHDQrr:
9103 return true;
9104 }
9105 return false;
9106}
9107
9108bool isLCALL(unsigned Opcode) {
9109 switch (Opcode) {
9110 case FARCALL16i:
9111 case FARCALL16m:
9112 case FARCALL32i:
9113 case FARCALL64m:
9114 return true;
9115 }
9116 return false;
9117}
9118
9119bool isAESDEC128KL(unsigned Opcode) {
9120 return Opcode == AESDEC128KL;
9121}
9122
9123bool isVSUBPS(unsigned Opcode) {
9124 switch (Opcode) {
9125 case VSUBPSYrm:
9126 case VSUBPSYrr:
9127 case VSUBPSZ128rm:
9128 case VSUBPSZ128rmb:
9129 case VSUBPSZ128rmbk:
9130 case VSUBPSZ128rmbkz:
9131 case VSUBPSZ128rmk:
9132 case VSUBPSZ128rmkz:
9133 case VSUBPSZ128rr:
9134 case VSUBPSZ128rrk:
9135 case VSUBPSZ128rrkz:
9136 case VSUBPSZ256rm:
9137 case VSUBPSZ256rmb:
9138 case VSUBPSZ256rmbk:
9139 case VSUBPSZ256rmbkz:
9140 case VSUBPSZ256rmk:
9141 case VSUBPSZ256rmkz:
9142 case VSUBPSZ256rr:
9143 case VSUBPSZ256rrk:
9144 case VSUBPSZ256rrkz:
9145 case VSUBPSZrm:
9146 case VSUBPSZrmb:
9147 case VSUBPSZrmbk:
9148 case VSUBPSZrmbkz:
9149 case VSUBPSZrmk:
9150 case VSUBPSZrmkz:
9151 case VSUBPSZrr:
9152 case VSUBPSZrrb:
9153 case VSUBPSZrrbk:
9154 case VSUBPSZrrbkz:
9155 case VSUBPSZrrk:
9156 case VSUBPSZrrkz:
9157 case VSUBPSrm:
9158 case VSUBPSrr:
9159 return true;
9160 }
9161 return false;
9162}
9163
9164bool isFSTP(unsigned Opcode) {
9165 switch (Opcode) {
9166 case ST_FP32m:
9167 case ST_FP64m:
9168 case ST_FP80m:
9169 case ST_FPrr:
9170 return true;
9171 }
9172 return false;
9173}
9174
9175bool isVCVTUDQ2PD(unsigned Opcode) {
9176 switch (Opcode) {
9177 case VCVTUDQ2PDZ128rm:
9178 case VCVTUDQ2PDZ128rmb:
9179 case VCVTUDQ2PDZ128rmbk:
9180 case VCVTUDQ2PDZ128rmbkz:
9181 case VCVTUDQ2PDZ128rmk:
9182 case VCVTUDQ2PDZ128rmkz:
9183 case VCVTUDQ2PDZ128rr:
9184 case VCVTUDQ2PDZ128rrk:
9185 case VCVTUDQ2PDZ128rrkz:
9186 case VCVTUDQ2PDZ256rm:
9187 case VCVTUDQ2PDZ256rmb:
9188 case VCVTUDQ2PDZ256rmbk:
9189 case VCVTUDQ2PDZ256rmbkz:
9190 case VCVTUDQ2PDZ256rmk:
9191 case VCVTUDQ2PDZ256rmkz:
9192 case VCVTUDQ2PDZ256rr:
9193 case VCVTUDQ2PDZ256rrk:
9194 case VCVTUDQ2PDZ256rrkz:
9195 case VCVTUDQ2PDZrm:
9196 case VCVTUDQ2PDZrmb:
9197 case VCVTUDQ2PDZrmbk:
9198 case VCVTUDQ2PDZrmbkz:
9199 case VCVTUDQ2PDZrmk:
9200 case VCVTUDQ2PDZrmkz:
9201 case VCVTUDQ2PDZrr:
9202 case VCVTUDQ2PDZrrk:
9203 case VCVTUDQ2PDZrrkz:
9204 return true;
9205 }
9206 return false;
9207}
9208
9209bool isVPMOVSWB(unsigned Opcode) {
9210 switch (Opcode) {
9211 case VPMOVSWBZ128mr:
9212 case VPMOVSWBZ128mrk:
9213 case VPMOVSWBZ128rr:
9214 case VPMOVSWBZ128rrk:
9215 case VPMOVSWBZ128rrkz:
9216 case VPMOVSWBZ256mr:
9217 case VPMOVSWBZ256mrk:
9218 case VPMOVSWBZ256rr:
9219 case VPMOVSWBZ256rrk:
9220 case VPMOVSWBZ256rrkz:
9221 case VPMOVSWBZmr:
9222 case VPMOVSWBZmrk:
9223 case VPMOVSWBZrr:
9224 case VPMOVSWBZrrk:
9225 case VPMOVSWBZrrkz:
9226 return true;
9227 }
9228 return false;
9229}
9230
9231bool isVPANDNQ(unsigned Opcode) {
9232 switch (Opcode) {
9233 case VPANDNQZ128rm:
9234 case VPANDNQZ128rmb:
9235 case VPANDNQZ128rmbk:
9236 case VPANDNQZ128rmbkz:
9237 case VPANDNQZ128rmk:
9238 case VPANDNQZ128rmkz:
9239 case VPANDNQZ128rr:
9240 case VPANDNQZ128rrk:
9241 case VPANDNQZ128rrkz:
9242 case VPANDNQZ256rm:
9243 case VPANDNQZ256rmb:
9244 case VPANDNQZ256rmbk:
9245 case VPANDNQZ256rmbkz:
9246 case VPANDNQZ256rmk:
9247 case VPANDNQZ256rmkz:
9248 case VPANDNQZ256rr:
9249 case VPANDNQZ256rrk:
9250 case VPANDNQZ256rrkz:
9251 case VPANDNQZrm:
9252 case VPANDNQZrmb:
9253 case VPANDNQZrmbk:
9254 case VPANDNQZrmbkz:
9255 case VPANDNQZrmk:
9256 case VPANDNQZrmkz:
9257 case VPANDNQZrr:
9258 case VPANDNQZrrk:
9259 case VPANDNQZrrkz:
9260 return true;
9261 }
9262 return false;
9263}
9264
9265bool isSYSENTER(unsigned Opcode) {
9266 return Opcode == SYSENTER;
9267}
9268
9269bool isVPHADDWD(unsigned Opcode) {
9270 switch (Opcode) {
9271 case VPHADDWDrm:
9272 case VPHADDWDrr:
9273 return true;
9274 }
9275 return false;
9276}
9277
9278bool isVMOVHPD(unsigned Opcode) {
9279 switch (Opcode) {
9280 case VMOVHPDZ128mr:
9281 case VMOVHPDZ128rm:
9282 case VMOVHPDmr:
9283 case VMOVHPDrm:
9284 return true;
9285 }
9286 return false;
9287}
9288
9289bool isMOVHPD(unsigned Opcode) {
9290 switch (Opcode) {
9291 case MOVHPDmr:
9292 case MOVHPDrm:
9293 return true;
9294 }
9295 return false;
9296}
9297
9298bool isVDIVPH(unsigned Opcode) {
9299 switch (Opcode) {
9300 case VDIVPHZ128rm:
9301 case VDIVPHZ128rmb:
9302 case VDIVPHZ128rmbk:
9303 case VDIVPHZ128rmbkz:
9304 case VDIVPHZ128rmk:
9305 case VDIVPHZ128rmkz:
9306 case VDIVPHZ128rr:
9307 case VDIVPHZ128rrk:
9308 case VDIVPHZ128rrkz:
9309 case VDIVPHZ256rm:
9310 case VDIVPHZ256rmb:
9311 case VDIVPHZ256rmbk:
9312 case VDIVPHZ256rmbkz:
9313 case VDIVPHZ256rmk:
9314 case VDIVPHZ256rmkz:
9315 case VDIVPHZ256rr:
9316 case VDIVPHZ256rrk:
9317 case VDIVPHZ256rrkz:
9318 case VDIVPHZrm:
9319 case VDIVPHZrmb:
9320 case VDIVPHZrmbk:
9321 case VDIVPHZrmbkz:
9322 case VDIVPHZrmk:
9323 case VDIVPHZrmkz:
9324 case VDIVPHZrr:
9325 case VDIVPHZrrb:
9326 case VDIVPHZrrbk:
9327 case VDIVPHZrrbkz:
9328 case VDIVPHZrrk:
9329 case VDIVPHZrrkz:
9330 return true;
9331 }
9332 return false;
9333}
9334
9335bool isFFREE(unsigned Opcode) {
9336 return Opcode == FFREE;
9337}
9338
9339bool isVGATHERPF1DPS(unsigned Opcode) {
9340 return Opcode == VGATHERPF1DPSm;
9341}
9342
9343bool isVFNMADD231PD(unsigned Opcode) {
9344 switch (Opcode) {
9345 case VFNMADD231PDYm:
9346 case VFNMADD231PDYr:
9347 case VFNMADD231PDZ128m:
9348 case VFNMADD231PDZ128mb:
9349 case VFNMADD231PDZ128mbk:
9350 case VFNMADD231PDZ128mbkz:
9351 case VFNMADD231PDZ128mk:
9352 case VFNMADD231PDZ128mkz:
9353 case VFNMADD231PDZ128r:
9354 case VFNMADD231PDZ128rk:
9355 case VFNMADD231PDZ128rkz:
9356 case VFNMADD231PDZ256m:
9357 case VFNMADD231PDZ256mb:
9358 case VFNMADD231PDZ256mbk:
9359 case VFNMADD231PDZ256mbkz:
9360 case VFNMADD231PDZ256mk:
9361 case VFNMADD231PDZ256mkz:
9362 case VFNMADD231PDZ256r:
9363 case VFNMADD231PDZ256rk:
9364 case VFNMADD231PDZ256rkz:
9365 case VFNMADD231PDZm:
9366 case VFNMADD231PDZmb:
9367 case VFNMADD231PDZmbk:
9368 case VFNMADD231PDZmbkz:
9369 case VFNMADD231PDZmk:
9370 case VFNMADD231PDZmkz:
9371 case VFNMADD231PDZr:
9372 case VFNMADD231PDZrb:
9373 case VFNMADD231PDZrbk:
9374 case VFNMADD231PDZrbkz:
9375 case VFNMADD231PDZrk:
9376 case VFNMADD231PDZrkz:
9377 case VFNMADD231PDm:
9378 case VFNMADD231PDr:
9379 return true;
9380 }
9381 return false;
9382}
9383
9384bool isVFCMULCPH(unsigned Opcode) {
9385 switch (Opcode) {
9386 case VFCMULCPHZ128rm:
9387 case VFCMULCPHZ128rmb:
9388 case VFCMULCPHZ128rmbk:
9389 case VFCMULCPHZ128rmbkz:
9390 case VFCMULCPHZ128rmk:
9391 case VFCMULCPHZ128rmkz:
9392 case VFCMULCPHZ128rr:
9393 case VFCMULCPHZ128rrk:
9394 case VFCMULCPHZ128rrkz:
9395 case VFCMULCPHZ256rm:
9396 case VFCMULCPHZ256rmb:
9397 case VFCMULCPHZ256rmbk:
9398 case VFCMULCPHZ256rmbkz:
9399 case VFCMULCPHZ256rmk:
9400 case VFCMULCPHZ256rmkz:
9401 case VFCMULCPHZ256rr:
9402 case VFCMULCPHZ256rrk:
9403 case VFCMULCPHZ256rrkz:
9404 case VFCMULCPHZrm:
9405 case VFCMULCPHZrmb:
9406 case VFCMULCPHZrmbk:
9407 case VFCMULCPHZrmbkz:
9408 case VFCMULCPHZrmk:
9409 case VFCMULCPHZrmkz:
9410 case VFCMULCPHZrr:
9411 case VFCMULCPHZrrb:
9412 case VFCMULCPHZrrbk:
9413 case VFCMULCPHZrrbkz:
9414 case VFCMULCPHZrrk:
9415 case VFCMULCPHZrrkz:
9416 return true;
9417 }
9418 return false;
9419}
9420
9421bool isVPADDD(unsigned Opcode) {
9422 switch (Opcode) {
9423 case VPADDDYrm:
9424 case VPADDDYrr:
9425 case VPADDDZ128rm:
9426 case VPADDDZ128rmb:
9427 case VPADDDZ128rmbk:
9428 case VPADDDZ128rmbkz:
9429 case VPADDDZ128rmk:
9430 case VPADDDZ128rmkz:
9431 case VPADDDZ128rr:
9432 case VPADDDZ128rrk:
9433 case VPADDDZ128rrkz:
9434 case VPADDDZ256rm:
9435 case VPADDDZ256rmb:
9436 case VPADDDZ256rmbk:
9437 case VPADDDZ256rmbkz:
9438 case VPADDDZ256rmk:
9439 case VPADDDZ256rmkz:
9440 case VPADDDZ256rr:
9441 case VPADDDZ256rrk:
9442 case VPADDDZ256rrkz:
9443 case VPADDDZrm:
9444 case VPADDDZrmb:
9445 case VPADDDZrmbk:
9446 case VPADDDZrmbkz:
9447 case VPADDDZrmk:
9448 case VPADDDZrmkz:
9449 case VPADDDZrr:
9450 case VPADDDZrrk:
9451 case VPADDDZrrkz:
9452 case VPADDDrm:
9453 case VPADDDrr:
9454 return true;
9455 }
9456 return false;
9457}
9458
9459bool isVSM3MSG2(unsigned Opcode) {
9460 switch (Opcode) {
9461 case VSM3MSG2rm:
9462 case VSM3MSG2rr:
9463 return true;
9464 }
9465 return false;
9466}
9467
9468bool isVPCOMUQ(unsigned Opcode) {
9469 switch (Opcode) {
9470 case VPCOMUQmi:
9471 case VPCOMUQri:
9472 return true;
9473 }
9474 return false;
9475}
9476
9477bool isVERR(unsigned Opcode) {
9478 switch (Opcode) {
9479 case VERRm:
9480 case VERRr:
9481 return true;
9482 }
9483 return false;
9484}
9485
9486bool isKORTESTQ(unsigned Opcode) {
9487 return Opcode == KORTESTQkk;
9488}
9489
9490bool isVFMSUB132SD(unsigned Opcode) {
9491 switch (Opcode) {
9492 case VFMSUB132SDZm_Int:
9493 case VFMSUB132SDZmk_Int:
9494 case VFMSUB132SDZmkz_Int:
9495 case VFMSUB132SDZr_Int:
9496 case VFMSUB132SDZrb_Int:
9497 case VFMSUB132SDZrbk_Int:
9498 case VFMSUB132SDZrbkz_Int:
9499 case VFMSUB132SDZrk_Int:
9500 case VFMSUB132SDZrkz_Int:
9501 case VFMSUB132SDm_Int:
9502 case VFMSUB132SDr_Int:
9503 return true;
9504 }
9505 return false;
9506}
9507
9508bool isTILEZERO(unsigned Opcode) {
9509 return Opcode == TILEZERO;
9510}
9511
9512bool isPFADD(unsigned Opcode) {
9513 switch (Opcode) {
9514 case PFADDrm:
9515 case PFADDrr:
9516 return true;
9517 }
9518 return false;
9519}
9520
9521bool isVCVTSI2SD(unsigned Opcode) {
9522 switch (Opcode) {
9523 case VCVTSI2SDZrm_Int:
9524 case VCVTSI2SDZrr_Int:
9525 case VCVTSI2SDrm_Int:
9526 case VCVTSI2SDrr_Int:
9527 case VCVTSI642SDZrm_Int:
9528 case VCVTSI642SDZrr_Int:
9529 case VCVTSI642SDZrrb_Int:
9530 case VCVTSI642SDrm_Int:
9531 case VCVTSI642SDrr_Int:
9532 return true;
9533 }
9534 return false;
9535}
9536
9537bool isTILELOADDRS(unsigned Opcode) {
9538 switch (Opcode) {
9539 case TILELOADDRS:
9540 case TILELOADDRS_EVEX:
9541 return true;
9542 }
9543 return false;
9544}
9545
9546bool isVSTMXCSR(unsigned Opcode) {
9547 return Opcode == VSTMXCSR;
9548}
9549
9550bool isVCVTTSH2SI(unsigned Opcode) {
9551 switch (Opcode) {
9552 case VCVTTSH2SI64Zrm_Int:
9553 case VCVTTSH2SI64Zrr_Int:
9554 case VCVTTSH2SI64Zrrb_Int:
9555 case VCVTTSH2SIZrm_Int:
9556 case VCVTTSH2SIZrr_Int:
9557 case VCVTTSH2SIZrrb_Int:
9558 return true;
9559 }
9560 return false;
9561}
9562
9563bool isRET(unsigned Opcode) {
9564 switch (Opcode) {
9565 case RET16:
9566 case RET32:
9567 case RET64:
9568 case RETI16:
9569 case RETI32:
9570 case RETI64:
9571 return true;
9572 }
9573 return false;
9574}
9575
9576bool isLZCNT(unsigned Opcode) {
9577 switch (Opcode) {
9578 case LZCNT16rm:
9579 case LZCNT16rm_EVEX:
9580 case LZCNT16rm_NF:
9581 case LZCNT16rr:
9582 case LZCNT16rr_EVEX:
9583 case LZCNT16rr_NF:
9584 case LZCNT32rm:
9585 case LZCNT32rm_EVEX:
9586 case LZCNT32rm_NF:
9587 case LZCNT32rr:
9588 case LZCNT32rr_EVEX:
9589 case LZCNT32rr_NF:
9590 case LZCNT64rm:
9591 case LZCNT64rm_EVEX:
9592 case LZCNT64rm_NF:
9593 case LZCNT64rr:
9594 case LZCNT64rr_EVEX:
9595 case LZCNT64rr_NF:
9596 return true;
9597 }
9598 return false;
9599}
9600
9601bool isMULPD(unsigned Opcode) {
9602 switch (Opcode) {
9603 case MULPDrm:
9604 case MULPDrr:
9605 return true;
9606 }
9607 return false;
9608}
9609
9610bool isVBROADCASTI32X2(unsigned Opcode) {
9611 switch (Opcode) {
9612 case VBROADCASTI32X2Z128rm:
9613 case VBROADCASTI32X2Z128rmk:
9614 case VBROADCASTI32X2Z128rmkz:
9615 case VBROADCASTI32X2Z128rr:
9616 case VBROADCASTI32X2Z128rrk:
9617 case VBROADCASTI32X2Z128rrkz:
9618 case VBROADCASTI32X2Z256rm:
9619 case VBROADCASTI32X2Z256rmk:
9620 case VBROADCASTI32X2Z256rmkz:
9621 case VBROADCASTI32X2Z256rr:
9622 case VBROADCASTI32X2Z256rrk:
9623 case VBROADCASTI32X2Z256rrkz:
9624 case VBROADCASTI32X2Zrm:
9625 case VBROADCASTI32X2Zrmk:
9626 case VBROADCASTI32X2Zrmkz:
9627 case VBROADCASTI32X2Zrr:
9628 case VBROADCASTI32X2Zrrk:
9629 case VBROADCASTI32X2Zrrkz:
9630 return true;
9631 }
9632 return false;
9633}
9634
9635bool isVCVTPH2W(unsigned Opcode) {
9636 switch (Opcode) {
9637 case VCVTPH2WZ128rm:
9638 case VCVTPH2WZ128rmb:
9639 case VCVTPH2WZ128rmbk:
9640 case VCVTPH2WZ128rmbkz:
9641 case VCVTPH2WZ128rmk:
9642 case VCVTPH2WZ128rmkz:
9643 case VCVTPH2WZ128rr:
9644 case VCVTPH2WZ128rrk:
9645 case VCVTPH2WZ128rrkz:
9646 case VCVTPH2WZ256rm:
9647 case VCVTPH2WZ256rmb:
9648 case VCVTPH2WZ256rmbk:
9649 case VCVTPH2WZ256rmbkz:
9650 case VCVTPH2WZ256rmk:
9651 case VCVTPH2WZ256rmkz:
9652 case VCVTPH2WZ256rr:
9653 case VCVTPH2WZ256rrk:
9654 case VCVTPH2WZ256rrkz:
9655 case VCVTPH2WZrm:
9656 case VCVTPH2WZrmb:
9657 case VCVTPH2WZrmbk:
9658 case VCVTPH2WZrmbkz:
9659 case VCVTPH2WZrmk:
9660 case VCVTPH2WZrmkz:
9661 case VCVTPH2WZrr:
9662 case VCVTPH2WZrrb:
9663 case VCVTPH2WZrrbk:
9664 case VCVTPH2WZrrbkz:
9665 case VCVTPH2WZrrk:
9666 case VCVTPH2WZrrkz:
9667 return true;
9668 }
9669 return false;
9670}
9671
9672bool isCQO(unsigned Opcode) {
9673 return Opcode == CQO;
9674}
9675
9676bool isFSUBR(unsigned Opcode) {
9677 switch (Opcode) {
9678 case SUBR_F32m:
9679 case SUBR_F64m:
9680 case SUBR_FST0r:
9681 case SUBR_FrST0:
9682 return true;
9683 }
9684 return false;
9685}
9686
9687bool isDPPD(unsigned Opcode) {
9688 switch (Opcode) {
9689 case DPPDrmi:
9690 case DPPDrri:
9691 return true;
9692 }
9693 return false;
9694}
9695
9696bool isFCOS(unsigned Opcode) {
9697 return Opcode == FCOS;
9698}
9699
9700bool isXSAVES(unsigned Opcode) {
9701 return Opcode == XSAVES;
9702}
9703
9704bool isTZCNT(unsigned Opcode) {
9705 switch (Opcode) {
9706 case TZCNT16rm:
9707 case TZCNT16rm_EVEX:
9708 case TZCNT16rm_NF:
9709 case TZCNT16rr:
9710 case TZCNT16rr_EVEX:
9711 case TZCNT16rr_NF:
9712 case TZCNT32rm:
9713 case TZCNT32rm_EVEX:
9714 case TZCNT32rm_NF:
9715 case TZCNT32rr:
9716 case TZCNT32rr_EVEX:
9717 case TZCNT32rr_NF:
9718 case TZCNT64rm:
9719 case TZCNT64rm_EVEX:
9720 case TZCNT64rm_NF:
9721 case TZCNT64rr:
9722 case TZCNT64rr_EVEX:
9723 case TZCNT64rr_NF:
9724 return true;
9725 }
9726 return false;
9727}
9728
9729bool isLJMP(unsigned Opcode) {
9730 switch (Opcode) {
9731 case FARJMP16i:
9732 case FARJMP16m:
9733 case FARJMP32i:
9734 case FARJMP64m:
9735 return true;
9736 }
9737 return false;
9738}
9739
9740bool isCMOVCC(unsigned Opcode) {
9741 switch (Opcode) {
9742 case CMOV16rm:
9743 case CMOV16rm_ND:
9744 case CMOV16rr:
9745 case CMOV16rr_ND:
9746 case CMOV32rm:
9747 case CMOV32rm_ND:
9748 case CMOV32rr:
9749 case CMOV32rr_ND:
9750 case CMOV64rm:
9751 case CMOV64rm_ND:
9752 case CMOV64rr:
9753 case CMOV64rr_ND:
9754 return true;
9755 }
9756 return false;
9757}
9758
9759bool isVCVTBIASPH2HF8(unsigned Opcode) {
9760 switch (Opcode) {
9761 case VCVTBIASPH2HF8Z128rm:
9762 case VCVTBIASPH2HF8Z128rmb:
9763 case VCVTBIASPH2HF8Z128rmbk:
9764 case VCVTBIASPH2HF8Z128rmbkz:
9765 case VCVTBIASPH2HF8Z128rmk:
9766 case VCVTBIASPH2HF8Z128rmkz:
9767 case VCVTBIASPH2HF8Z128rr:
9768 case VCVTBIASPH2HF8Z128rrk:
9769 case VCVTBIASPH2HF8Z128rrkz:
9770 case VCVTBIASPH2HF8Z256rm:
9771 case VCVTBIASPH2HF8Z256rmb:
9772 case VCVTBIASPH2HF8Z256rmbk:
9773 case VCVTBIASPH2HF8Z256rmbkz:
9774 case VCVTBIASPH2HF8Z256rmk:
9775 case VCVTBIASPH2HF8Z256rmkz:
9776 case VCVTBIASPH2HF8Z256rr:
9777 case VCVTBIASPH2HF8Z256rrk:
9778 case VCVTBIASPH2HF8Z256rrkz:
9779 case VCVTBIASPH2HF8Zrm:
9780 case VCVTBIASPH2HF8Zrmb:
9781 case VCVTBIASPH2HF8Zrmbk:
9782 case VCVTBIASPH2HF8Zrmbkz:
9783 case VCVTBIASPH2HF8Zrmk:
9784 case VCVTBIASPH2HF8Zrmkz:
9785 case VCVTBIASPH2HF8Zrr:
9786 case VCVTBIASPH2HF8Zrrk:
9787 case VCVTBIASPH2HF8Zrrkz:
9788 return true;
9789 }
9790 return false;
9791}
9792
9793bool isINVEPT(unsigned Opcode) {
9794 switch (Opcode) {
9795 case INVEPT32:
9796 case INVEPT64:
9797 case INVEPT64_EVEX:
9798 return true;
9799 }
9800 return false;
9801}
9802
9803bool isADDSUBPD(unsigned Opcode) {
9804 switch (Opcode) {
9805 case ADDSUBPDrm:
9806 case ADDSUBPDrr:
9807 return true;
9808 }
9809 return false;
9810}
9811
9812bool isVMOVSHDUP(unsigned Opcode) {
9813 switch (Opcode) {
9814 case VMOVSHDUPYrm:
9815 case VMOVSHDUPYrr:
9816 case VMOVSHDUPZ128rm:
9817 case VMOVSHDUPZ128rmk:
9818 case VMOVSHDUPZ128rmkz:
9819 case VMOVSHDUPZ128rr:
9820 case VMOVSHDUPZ128rrk:
9821 case VMOVSHDUPZ128rrkz:
9822 case VMOVSHDUPZ256rm:
9823 case VMOVSHDUPZ256rmk:
9824 case VMOVSHDUPZ256rmkz:
9825 case VMOVSHDUPZ256rr:
9826 case VMOVSHDUPZ256rrk:
9827 case VMOVSHDUPZ256rrkz:
9828 case VMOVSHDUPZrm:
9829 case VMOVSHDUPZrmk:
9830 case VMOVSHDUPZrmkz:
9831 case VMOVSHDUPZrr:
9832 case VMOVSHDUPZrrk:
9833 case VMOVSHDUPZrrkz:
9834 case VMOVSHDUPrm:
9835 case VMOVSHDUPrr:
9836 return true;
9837 }
9838 return false;
9839}
9840
9841bool isKSHIFTRD(unsigned Opcode) {
9842 return Opcode == KSHIFTRDki;
9843}
9844
9845bool isVCVTSS2SD(unsigned Opcode) {
9846 switch (Opcode) {
9847 case VCVTSS2SDZrm_Int:
9848 case VCVTSS2SDZrmk_Int:
9849 case VCVTSS2SDZrmkz_Int:
9850 case VCVTSS2SDZrr_Int:
9851 case VCVTSS2SDZrrb_Int:
9852 case VCVTSS2SDZrrbk_Int:
9853 case VCVTSS2SDZrrbkz_Int:
9854 case VCVTSS2SDZrrk_Int:
9855 case VCVTSS2SDZrrkz_Int:
9856 case VCVTSS2SDrm_Int:
9857 case VCVTSS2SDrr_Int:
9858 return true;
9859 }
9860 return false;
9861}
9862
9863bool isPADDQ(unsigned Opcode) {
9864 switch (Opcode) {
9865 case MMX_PADDQrm:
9866 case MMX_PADDQrr:
9867 case PADDQrm:
9868 case PADDQrr:
9869 return true;
9870 }
9871 return false;
9872}
9873
9874bool isVEXTRACTI64X4(unsigned Opcode) {
9875 switch (Opcode) {
9876 case VEXTRACTI64X4Zmri:
9877 case VEXTRACTI64X4Zmrik:
9878 case VEXTRACTI64X4Zrri:
9879 case VEXTRACTI64X4Zrrik:
9880 case VEXTRACTI64X4Zrrikz:
9881 return true;
9882 }
9883 return false;
9884}
9885
9886bool isVFMSUB231SS(unsigned Opcode) {
9887 switch (Opcode) {
9888 case VFMSUB231SSZm_Int:
9889 case VFMSUB231SSZmk_Int:
9890 case VFMSUB231SSZmkz_Int:
9891 case VFMSUB231SSZr_Int:
9892 case VFMSUB231SSZrb_Int:
9893 case VFMSUB231SSZrbk_Int:
9894 case VFMSUB231SSZrbkz_Int:
9895 case VFMSUB231SSZrk_Int:
9896 case VFMSUB231SSZrkz_Int:
9897 case VFMSUB231SSm_Int:
9898 case VFMSUB231SSr_Int:
9899 return true;
9900 }
9901 return false;
9902}
9903
9904bool isVPCMPEQB(unsigned Opcode) {
9905 switch (Opcode) {
9906 case VPCMPEQBYrm:
9907 case VPCMPEQBYrr:
9908 case VPCMPEQBZ128rm:
9909 case VPCMPEQBZ128rmk:
9910 case VPCMPEQBZ128rr:
9911 case VPCMPEQBZ128rrk:
9912 case VPCMPEQBZ256rm:
9913 case VPCMPEQBZ256rmk:
9914 case VPCMPEQBZ256rr:
9915 case VPCMPEQBZ256rrk:
9916 case VPCMPEQBZrm:
9917 case VPCMPEQBZrmk:
9918 case VPCMPEQBZrr:
9919 case VPCMPEQBZrrk:
9920 case VPCMPEQBrm:
9921 case VPCMPEQBrr:
9922 return true;
9923 }
9924 return false;
9925}
9926
9927bool isVPTERNLOGD(unsigned Opcode) {
9928 switch (Opcode) {
9929 case VPTERNLOGDZ128rmbi:
9930 case VPTERNLOGDZ128rmbik:
9931 case VPTERNLOGDZ128rmbikz:
9932 case VPTERNLOGDZ128rmi:
9933 case VPTERNLOGDZ128rmik:
9934 case VPTERNLOGDZ128rmikz:
9935 case VPTERNLOGDZ128rri:
9936 case VPTERNLOGDZ128rrik:
9937 case VPTERNLOGDZ128rrikz:
9938 case VPTERNLOGDZ256rmbi:
9939 case VPTERNLOGDZ256rmbik:
9940 case VPTERNLOGDZ256rmbikz:
9941 case VPTERNLOGDZ256rmi:
9942 case VPTERNLOGDZ256rmik:
9943 case VPTERNLOGDZ256rmikz:
9944 case VPTERNLOGDZ256rri:
9945 case VPTERNLOGDZ256rrik:
9946 case VPTERNLOGDZ256rrikz:
9947 case VPTERNLOGDZrmbi:
9948 case VPTERNLOGDZrmbik:
9949 case VPTERNLOGDZrmbikz:
9950 case VPTERNLOGDZrmi:
9951 case VPTERNLOGDZrmik:
9952 case VPTERNLOGDZrmikz:
9953 case VPTERNLOGDZrri:
9954 case VPTERNLOGDZrrik:
9955 case VPTERNLOGDZrrikz:
9956 return true;
9957 }
9958 return false;
9959}
9960
9961bool isLEA(unsigned Opcode) {
9962 switch (Opcode) {
9963 case LEA16r:
9964 case LEA32r:
9965 case LEA64_32r:
9966 case LEA64r:
9967 return true;
9968 }
9969 return false;
9970}
9971
9972bool isPSUBB(unsigned Opcode) {
9973 switch (Opcode) {
9974 case MMX_PSUBBrm:
9975 case MMX_PSUBBrr:
9976 case PSUBBrm:
9977 case PSUBBrr:
9978 return true;
9979 }
9980 return false;
9981}
9982
9983bool isKADDQ(unsigned Opcode) {
9984 return Opcode == KADDQkk;
9985}
9986
9987bool isMOVSX(unsigned Opcode) {
9988 switch (Opcode) {
9989 case MOVSX16rm16:
9990 case MOVSX16rm8:
9991 case MOVSX16rr16:
9992 case MOVSX16rr8:
9993 case MOVSX32rm16:
9994 case MOVSX32rm8:
9995 case MOVSX32rr16:
9996 case MOVSX32rr8:
9997 case MOVSX64rm16:
9998 case MOVSX64rm8:
9999 case MOVSX64rr16:
10000 case MOVSX64rr8:
10001 return true;
10002 }
10003 return false;
10004}
10005
10006bool isVALIGNQ(unsigned Opcode) {
10007 switch (Opcode) {
10008 case VALIGNQZ128rmbi:
10009 case VALIGNQZ128rmbik:
10010 case VALIGNQZ128rmbikz:
10011 case VALIGNQZ128rmi:
10012 case VALIGNQZ128rmik:
10013 case VALIGNQZ128rmikz:
10014 case VALIGNQZ128rri:
10015 case VALIGNQZ128rrik:
10016 case VALIGNQZ128rrikz:
10017 case VALIGNQZ256rmbi:
10018 case VALIGNQZ256rmbik:
10019 case VALIGNQZ256rmbikz:
10020 case VALIGNQZ256rmi:
10021 case VALIGNQZ256rmik:
10022 case VALIGNQZ256rmikz:
10023 case VALIGNQZ256rri:
10024 case VALIGNQZ256rrik:
10025 case VALIGNQZ256rrikz:
10026 case VALIGNQZrmbi:
10027 case VALIGNQZrmbik:
10028 case VALIGNQZrmbikz:
10029 case VALIGNQZrmi:
10030 case VALIGNQZrmik:
10031 case VALIGNQZrmikz:
10032 case VALIGNQZrri:
10033 case VALIGNQZrrik:
10034 case VALIGNQZrrikz:
10035 return true;
10036 }
10037 return false;
10038}
10039
10040bool isVCVTNE2PS2BF16(unsigned Opcode) {
10041 switch (Opcode) {
10042 case VCVTNE2PS2BF16Z128rm:
10043 case VCVTNE2PS2BF16Z128rmb:
10044 case VCVTNE2PS2BF16Z128rmbk:
10045 case VCVTNE2PS2BF16Z128rmbkz:
10046 case VCVTNE2PS2BF16Z128rmk:
10047 case VCVTNE2PS2BF16Z128rmkz:
10048 case VCVTNE2PS2BF16Z128rr:
10049 case VCVTNE2PS2BF16Z128rrk:
10050 case VCVTNE2PS2BF16Z128rrkz:
10051 case VCVTNE2PS2BF16Z256rm:
10052 case VCVTNE2PS2BF16Z256rmb:
10053 case VCVTNE2PS2BF16Z256rmbk:
10054 case VCVTNE2PS2BF16Z256rmbkz:
10055 case VCVTNE2PS2BF16Z256rmk:
10056 case VCVTNE2PS2BF16Z256rmkz:
10057 case VCVTNE2PS2BF16Z256rr:
10058 case VCVTNE2PS2BF16Z256rrk:
10059 case VCVTNE2PS2BF16Z256rrkz:
10060 case VCVTNE2PS2BF16Zrm:
10061 case VCVTNE2PS2BF16Zrmb:
10062 case VCVTNE2PS2BF16Zrmbk:
10063 case VCVTNE2PS2BF16Zrmbkz:
10064 case VCVTNE2PS2BF16Zrmk:
10065 case VCVTNE2PS2BF16Zrmkz:
10066 case VCVTNE2PS2BF16Zrr:
10067 case VCVTNE2PS2BF16Zrrk:
10068 case VCVTNE2PS2BF16Zrrkz:
10069 return true;
10070 }
10071 return false;
10072}
10073
10074bool isVPSRAW(unsigned Opcode) {
10075 switch (Opcode) {
10076 case VPSRAWYri:
10077 case VPSRAWYrm:
10078 case VPSRAWYrr:
10079 case VPSRAWZ128mi:
10080 case VPSRAWZ128mik:
10081 case VPSRAWZ128mikz:
10082 case VPSRAWZ128ri:
10083 case VPSRAWZ128rik:
10084 case VPSRAWZ128rikz:
10085 case VPSRAWZ128rm:
10086 case VPSRAWZ128rmk:
10087 case VPSRAWZ128rmkz:
10088 case VPSRAWZ128rr:
10089 case VPSRAWZ128rrk:
10090 case VPSRAWZ128rrkz:
10091 case VPSRAWZ256mi:
10092 case VPSRAWZ256mik:
10093 case VPSRAWZ256mikz:
10094 case VPSRAWZ256ri:
10095 case VPSRAWZ256rik:
10096 case VPSRAWZ256rikz:
10097 case VPSRAWZ256rm:
10098 case VPSRAWZ256rmk:
10099 case VPSRAWZ256rmkz:
10100 case VPSRAWZ256rr:
10101 case VPSRAWZ256rrk:
10102 case VPSRAWZ256rrkz:
10103 case VPSRAWZmi:
10104 case VPSRAWZmik:
10105 case VPSRAWZmikz:
10106 case VPSRAWZri:
10107 case VPSRAWZrik:
10108 case VPSRAWZrikz:
10109 case VPSRAWZrm:
10110 case VPSRAWZrmk:
10111 case VPSRAWZrmkz:
10112 case VPSRAWZrr:
10113 case VPSRAWZrrk:
10114 case VPSRAWZrrkz:
10115 case VPSRAWri:
10116 case VPSRAWrm:
10117 case VPSRAWrr:
10118 return true;
10119 }
10120 return false;
10121}
10122
10123bool isVFMSUBADD231PH(unsigned Opcode) {
10124 switch (Opcode) {
10125 case VFMSUBADD231PHZ128m:
10126 case VFMSUBADD231PHZ128mb:
10127 case VFMSUBADD231PHZ128mbk:
10128 case VFMSUBADD231PHZ128mbkz:
10129 case VFMSUBADD231PHZ128mk:
10130 case VFMSUBADD231PHZ128mkz:
10131 case VFMSUBADD231PHZ128r:
10132 case VFMSUBADD231PHZ128rk:
10133 case VFMSUBADD231PHZ128rkz:
10134 case VFMSUBADD231PHZ256m:
10135 case VFMSUBADD231PHZ256mb:
10136 case VFMSUBADD231PHZ256mbk:
10137 case VFMSUBADD231PHZ256mbkz:
10138 case VFMSUBADD231PHZ256mk:
10139 case VFMSUBADD231PHZ256mkz:
10140 case VFMSUBADD231PHZ256r:
10141 case VFMSUBADD231PHZ256rk:
10142 case VFMSUBADD231PHZ256rkz:
10143 case VFMSUBADD231PHZm:
10144 case VFMSUBADD231PHZmb:
10145 case VFMSUBADD231PHZmbk:
10146 case VFMSUBADD231PHZmbkz:
10147 case VFMSUBADD231PHZmk:
10148 case VFMSUBADD231PHZmkz:
10149 case VFMSUBADD231PHZr:
10150 case VFMSUBADD231PHZrb:
10151 case VFMSUBADD231PHZrbk:
10152 case VFMSUBADD231PHZrbkz:
10153 case VFMSUBADD231PHZrk:
10154 case VFMSUBADD231PHZrkz:
10155 return true;
10156 }
10157 return false;
10158}
10159
10160bool isCVTDQ2PS(unsigned Opcode) {
10161 switch (Opcode) {
10162 case CVTDQ2PSrm:
10163 case CVTDQ2PSrr:
10164 return true;
10165 }
10166 return false;
10167}
10168
10169bool isFBLD(unsigned Opcode) {
10170 return Opcode == FBLDm;
10171}
10172
10173bool isLMSW(unsigned Opcode) {
10174 switch (Opcode) {
10175 case LMSW16m:
10176 case LMSW16r:
10177 return true;
10178 }
10179 return false;
10180}
10181
10182bool isWRMSR(unsigned Opcode) {
10183 return Opcode == WRMSR;
10184}
10185
10186bool isMINSS(unsigned Opcode) {
10187 switch (Opcode) {
10188 case MINSSrm_Int:
10189 case MINSSrr_Int:
10190 return true;
10191 }
10192 return false;
10193}
10194
10195bool isFSCALE(unsigned Opcode) {
10196 return Opcode == FSCALE;
10197}
10198
10199bool isVFNMADD213SH(unsigned Opcode) {
10200 switch (Opcode) {
10201 case VFNMADD213SHZm_Int:
10202 case VFNMADD213SHZmk_Int:
10203 case VFNMADD213SHZmkz_Int:
10204 case VFNMADD213SHZr_Int:
10205 case VFNMADD213SHZrb_Int:
10206 case VFNMADD213SHZrbk_Int:
10207 case VFNMADD213SHZrbkz_Int:
10208 case VFNMADD213SHZrk_Int:
10209 case VFNMADD213SHZrkz_Int:
10210 return true;
10211 }
10212 return false;
10213}
10214
10215bool isIMULZU(unsigned Opcode) {
10216 switch (Opcode) {
10217 case IMULZU16rmi:
10218 case IMULZU16rmi8:
10219 case IMULZU16rri:
10220 case IMULZU16rri8:
10221 case IMULZU32rmi:
10222 case IMULZU32rmi8:
10223 case IMULZU32rri:
10224 case IMULZU32rri8:
10225 case IMULZU64rmi32:
10226 case IMULZU64rmi8:
10227 case IMULZU64rri32:
10228 case IMULZU64rri8:
10229 return true;
10230 }
10231 return false;
10232}
10233
10234bool isVPHADDUBD(unsigned Opcode) {
10235 switch (Opcode) {
10236 case VPHADDUBDrm:
10237 case VPHADDUBDrr:
10238 return true;
10239 }
10240 return false;
10241}
10242
10243bool isRDSSPQ(unsigned Opcode) {
10244 return Opcode == RDSSPQ;
10245}
10246
10247bool isVCVTBF162IBS(unsigned Opcode) {
10248 switch (Opcode) {
10249 case VCVTBF162IBSZ128rm:
10250 case VCVTBF162IBSZ128rmb:
10251 case VCVTBF162IBSZ128rmbk:
10252 case VCVTBF162IBSZ128rmbkz:
10253 case VCVTBF162IBSZ128rmk:
10254 case VCVTBF162IBSZ128rmkz:
10255 case VCVTBF162IBSZ128rr:
10256 case VCVTBF162IBSZ128rrk:
10257 case VCVTBF162IBSZ128rrkz:
10258 case VCVTBF162IBSZ256rm:
10259 case VCVTBF162IBSZ256rmb:
10260 case VCVTBF162IBSZ256rmbk:
10261 case VCVTBF162IBSZ256rmbkz:
10262 case VCVTBF162IBSZ256rmk:
10263 case VCVTBF162IBSZ256rmkz:
10264 case VCVTBF162IBSZ256rr:
10265 case VCVTBF162IBSZ256rrk:
10266 case VCVTBF162IBSZ256rrkz:
10267 case VCVTBF162IBSZrm:
10268 case VCVTBF162IBSZrmb:
10269 case VCVTBF162IBSZrmbk:
10270 case VCVTBF162IBSZrmbkz:
10271 case VCVTBF162IBSZrmk:
10272 case VCVTBF162IBSZrmkz:
10273 case VCVTBF162IBSZrr:
10274 case VCVTBF162IBSZrrk:
10275 case VCVTBF162IBSZrrkz:
10276 return true;
10277 }
10278 return false;
10279}
10280
10281bool isLGDT(unsigned Opcode) {
10282 return Opcode == LGDT64m;
10283}
10284
10285bool isVPSHLDVD(unsigned Opcode) {
10286 switch (Opcode) {
10287 case VPSHLDVDZ128m:
10288 case VPSHLDVDZ128mb:
10289 case VPSHLDVDZ128mbk:
10290 case VPSHLDVDZ128mbkz:
10291 case VPSHLDVDZ128mk:
10292 case VPSHLDVDZ128mkz:
10293 case VPSHLDVDZ128r:
10294 case VPSHLDVDZ128rk:
10295 case VPSHLDVDZ128rkz:
10296 case VPSHLDVDZ256m:
10297 case VPSHLDVDZ256mb:
10298 case VPSHLDVDZ256mbk:
10299 case VPSHLDVDZ256mbkz:
10300 case VPSHLDVDZ256mk:
10301 case VPSHLDVDZ256mkz:
10302 case VPSHLDVDZ256r:
10303 case VPSHLDVDZ256rk:
10304 case VPSHLDVDZ256rkz:
10305 case VPSHLDVDZm:
10306 case VPSHLDVDZmb:
10307 case VPSHLDVDZmbk:
10308 case VPSHLDVDZmbkz:
10309 case VPSHLDVDZmk:
10310 case VPSHLDVDZmkz:
10311 case VPSHLDVDZr:
10312 case VPSHLDVDZrk:
10313 case VPSHLDVDZrkz:
10314 return true;
10315 }
10316 return false;
10317}
10318
10319bool isPFCMPGT(unsigned Opcode) {
10320 switch (Opcode) {
10321 case PFCMPGTrm:
10322 case PFCMPGTrr:
10323 return true;
10324 }
10325 return false;
10326}
10327
10328bool isVRNDSCALEPH(unsigned Opcode) {
10329 switch (Opcode) {
10330 case VRNDSCALEPHZ128rmbi:
10331 case VRNDSCALEPHZ128rmbik:
10332 case VRNDSCALEPHZ128rmbikz:
10333 case VRNDSCALEPHZ128rmi:
10334 case VRNDSCALEPHZ128rmik:
10335 case VRNDSCALEPHZ128rmikz:
10336 case VRNDSCALEPHZ128rri:
10337 case VRNDSCALEPHZ128rrik:
10338 case VRNDSCALEPHZ128rrikz:
10339 case VRNDSCALEPHZ256rmbi:
10340 case VRNDSCALEPHZ256rmbik:
10341 case VRNDSCALEPHZ256rmbikz:
10342 case VRNDSCALEPHZ256rmi:
10343 case VRNDSCALEPHZ256rmik:
10344 case VRNDSCALEPHZ256rmikz:
10345 case VRNDSCALEPHZ256rri:
10346 case VRNDSCALEPHZ256rrik:
10347 case VRNDSCALEPHZ256rrikz:
10348 case VRNDSCALEPHZrmbi:
10349 case VRNDSCALEPHZrmbik:
10350 case VRNDSCALEPHZrmbikz:
10351 case VRNDSCALEPHZrmi:
10352 case VRNDSCALEPHZrmik:
10353 case VRNDSCALEPHZrmikz:
10354 case VRNDSCALEPHZrri:
10355 case VRNDSCALEPHZrrib:
10356 case VRNDSCALEPHZrribk:
10357 case VRNDSCALEPHZrribkz:
10358 case VRNDSCALEPHZrrik:
10359 case VRNDSCALEPHZrrikz:
10360 return true;
10361 }
10362 return false;
10363}
10364
10365bool isJCXZ(unsigned Opcode) {
10366 return Opcode == JCXZ;
10367}
10368
10369bool isVPMOVZXBW(unsigned Opcode) {
10370 switch (Opcode) {
10371 case VPMOVZXBWYrm:
10372 case VPMOVZXBWYrr:
10373 case VPMOVZXBWZ128rm:
10374 case VPMOVZXBWZ128rmk:
10375 case VPMOVZXBWZ128rmkz:
10376 case VPMOVZXBWZ128rr:
10377 case VPMOVZXBWZ128rrk:
10378 case VPMOVZXBWZ128rrkz:
10379 case VPMOVZXBWZ256rm:
10380 case VPMOVZXBWZ256rmk:
10381 case VPMOVZXBWZ256rmkz:
10382 case VPMOVZXBWZ256rr:
10383 case VPMOVZXBWZ256rrk:
10384 case VPMOVZXBWZ256rrkz:
10385 case VPMOVZXBWZrm:
10386 case VPMOVZXBWZrmk:
10387 case VPMOVZXBWZrmkz:
10388 case VPMOVZXBWZrr:
10389 case VPMOVZXBWZrrk:
10390 case VPMOVZXBWZrrkz:
10391 case VPMOVZXBWrm:
10392 case VPMOVZXBWrr:
10393 return true;
10394 }
10395 return false;
10396}
10397
10398bool isVFMADDSUB231PD(unsigned Opcode) {
10399 switch (Opcode) {
10400 case VFMADDSUB231PDYm:
10401 case VFMADDSUB231PDYr:
10402 case VFMADDSUB231PDZ128m:
10403 case VFMADDSUB231PDZ128mb:
10404 case VFMADDSUB231PDZ128mbk:
10405 case VFMADDSUB231PDZ128mbkz:
10406 case VFMADDSUB231PDZ128mk:
10407 case VFMADDSUB231PDZ128mkz:
10408 case VFMADDSUB231PDZ128r:
10409 case VFMADDSUB231PDZ128rk:
10410 case VFMADDSUB231PDZ128rkz:
10411 case VFMADDSUB231PDZ256m:
10412 case VFMADDSUB231PDZ256mb:
10413 case VFMADDSUB231PDZ256mbk:
10414 case VFMADDSUB231PDZ256mbkz:
10415 case VFMADDSUB231PDZ256mk:
10416 case VFMADDSUB231PDZ256mkz:
10417 case VFMADDSUB231PDZ256r:
10418 case VFMADDSUB231PDZ256rk:
10419 case VFMADDSUB231PDZ256rkz:
10420 case VFMADDSUB231PDZm:
10421 case VFMADDSUB231PDZmb:
10422 case VFMADDSUB231PDZmbk:
10423 case VFMADDSUB231PDZmbkz:
10424 case VFMADDSUB231PDZmk:
10425 case VFMADDSUB231PDZmkz:
10426 case VFMADDSUB231PDZr:
10427 case VFMADDSUB231PDZrb:
10428 case VFMADDSUB231PDZrbk:
10429 case VFMADDSUB231PDZrbkz:
10430 case VFMADDSUB231PDZrk:
10431 case VFMADDSUB231PDZrkz:
10432 case VFMADDSUB231PDm:
10433 case VFMADDSUB231PDr:
10434 return true;
10435 }
10436 return false;
10437}
10438
10439bool isVBLENDMPD(unsigned Opcode) {
10440 switch (Opcode) {
10441 case VBLENDMPDZ128rm:
10442 case VBLENDMPDZ128rmb:
10443 case VBLENDMPDZ128rmbk:
10444 case VBLENDMPDZ128rmbkz:
10445 case VBLENDMPDZ128rmk:
10446 case VBLENDMPDZ128rmkz:
10447 case VBLENDMPDZ128rr:
10448 case VBLENDMPDZ128rrk:
10449 case VBLENDMPDZ128rrkz:
10450 case VBLENDMPDZ256rm:
10451 case VBLENDMPDZ256rmb:
10452 case VBLENDMPDZ256rmbk:
10453 case VBLENDMPDZ256rmbkz:
10454 case VBLENDMPDZ256rmk:
10455 case VBLENDMPDZ256rmkz:
10456 case VBLENDMPDZ256rr:
10457 case VBLENDMPDZ256rrk:
10458 case VBLENDMPDZ256rrkz:
10459 case VBLENDMPDZrm:
10460 case VBLENDMPDZrmb:
10461 case VBLENDMPDZrmbk:
10462 case VBLENDMPDZrmbkz:
10463 case VBLENDMPDZrmk:
10464 case VBLENDMPDZrmkz:
10465 case VBLENDMPDZrr:
10466 case VBLENDMPDZrrk:
10467 case VBLENDMPDZrrkz:
10468 return true;
10469 }
10470 return false;
10471}
10472
10473bool isHSUBPS(unsigned Opcode) {
10474 switch (Opcode) {
10475 case HSUBPSrm:
10476 case HSUBPSrr:
10477 return true;
10478 }
10479 return false;
10480}
10481
10482bool isPREFETCHIT0(unsigned Opcode) {
10483 return Opcode == PREFETCHIT0;
10484}
10485
10486bool isKTESTD(unsigned Opcode) {
10487 return Opcode == KTESTDkk;
10488}
10489
10490bool isVCVTNEOPH2PS(unsigned Opcode) {
10491 switch (Opcode) {
10492 case VCVTNEOPH2PSYrm:
10493 case VCVTNEOPH2PSrm:
10494 return true;
10495 }
10496 return false;
10497}
10498
10499bool isVBLENDVPD(unsigned Opcode) {
10500 switch (Opcode) {
10501 case VBLENDVPDYrmr:
10502 case VBLENDVPDYrrr:
10503 case VBLENDVPDrmr:
10504 case VBLENDVPDrrr:
10505 return true;
10506 }
10507 return false;
10508}
10509
10510bool isVCVTSS2USI(unsigned Opcode) {
10511 switch (Opcode) {
10512 case VCVTSS2USI64Zrm_Int:
10513 case VCVTSS2USI64Zrr_Int:
10514 case VCVTSS2USI64Zrrb_Int:
10515 case VCVTSS2USIZrm_Int:
10516 case VCVTSS2USIZrr_Int:
10517 case VCVTSS2USIZrrb_Int:
10518 return true;
10519 }
10520 return false;
10521}
10522
10523bool isVCVTTPS2DQS(unsigned Opcode) {
10524 switch (Opcode) {
10525 case VCVTTPS2DQSZ128rm:
10526 case VCVTTPS2DQSZ128rmb:
10527 case VCVTTPS2DQSZ128rmbk:
10528 case VCVTTPS2DQSZ128rmbkz:
10529 case VCVTTPS2DQSZ128rmk:
10530 case VCVTTPS2DQSZ128rmkz:
10531 case VCVTTPS2DQSZ128rr:
10532 case VCVTTPS2DQSZ128rrk:
10533 case VCVTTPS2DQSZ128rrkz:
10534 case VCVTTPS2DQSZ256rm:
10535 case VCVTTPS2DQSZ256rmb:
10536 case VCVTTPS2DQSZ256rmbk:
10537 case VCVTTPS2DQSZ256rmbkz:
10538 case VCVTTPS2DQSZ256rmk:
10539 case VCVTTPS2DQSZ256rmkz:
10540 case VCVTTPS2DQSZ256rr:
10541 case VCVTTPS2DQSZ256rrk:
10542 case VCVTTPS2DQSZ256rrkz:
10543 case VCVTTPS2DQSZrm:
10544 case VCVTTPS2DQSZrmb:
10545 case VCVTTPS2DQSZrmbk:
10546 case VCVTTPS2DQSZrmbkz:
10547 case VCVTTPS2DQSZrmk:
10548 case VCVTTPS2DQSZrmkz:
10549 case VCVTTPS2DQSZrr:
10550 case VCVTTPS2DQSZrrb:
10551 case VCVTTPS2DQSZrrbk:
10552 case VCVTTPS2DQSZrrbkz:
10553 case VCVTTPS2DQSZrrk:
10554 case VCVTTPS2DQSZrrkz:
10555 return true;
10556 }
10557 return false;
10558}
10559
10560bool isVPANDD(unsigned Opcode) {
10561 switch (Opcode) {
10562 case VPANDDZ128rm:
10563 case VPANDDZ128rmb:
10564 case VPANDDZ128rmbk:
10565 case VPANDDZ128rmbkz:
10566 case VPANDDZ128rmk:
10567 case VPANDDZ128rmkz:
10568 case VPANDDZ128rr:
10569 case VPANDDZ128rrk:
10570 case VPANDDZ128rrkz:
10571 case VPANDDZ256rm:
10572 case VPANDDZ256rmb:
10573 case VPANDDZ256rmbk:
10574 case VPANDDZ256rmbkz:
10575 case VPANDDZ256rmk:
10576 case VPANDDZ256rmkz:
10577 case VPANDDZ256rr:
10578 case VPANDDZ256rrk:
10579 case VPANDDZ256rrkz:
10580 case VPANDDZrm:
10581 case VPANDDZrmb:
10582 case VPANDDZrmbk:
10583 case VPANDDZrmbkz:
10584 case VPANDDZrmk:
10585 case VPANDDZrmkz:
10586 case VPANDDZrr:
10587 case VPANDDZrrk:
10588 case VPANDDZrrkz:
10589 return true;
10590 }
10591 return false;
10592}
10593
10594bool isPMINSW(unsigned Opcode) {
10595 switch (Opcode) {
10596 case MMX_PMINSWrm:
10597 case MMX_PMINSWrr:
10598 case PMINSWrm:
10599 case PMINSWrr:
10600 return true;
10601 }
10602 return false;
10603}
10604
10605bool isSTAC(unsigned Opcode) {
10606 return Opcode == STAC;
10607}
10608
10609bool isVFMSUB213PS(unsigned Opcode) {
10610 switch (Opcode) {
10611 case VFMSUB213PSYm:
10612 case VFMSUB213PSYr:
10613 case VFMSUB213PSZ128m:
10614 case VFMSUB213PSZ128mb:
10615 case VFMSUB213PSZ128mbk:
10616 case VFMSUB213PSZ128mbkz:
10617 case VFMSUB213PSZ128mk:
10618 case VFMSUB213PSZ128mkz:
10619 case VFMSUB213PSZ128r:
10620 case VFMSUB213PSZ128rk:
10621 case VFMSUB213PSZ128rkz:
10622 case VFMSUB213PSZ256m:
10623 case VFMSUB213PSZ256mb:
10624 case VFMSUB213PSZ256mbk:
10625 case VFMSUB213PSZ256mbkz:
10626 case VFMSUB213PSZ256mk:
10627 case VFMSUB213PSZ256mkz:
10628 case VFMSUB213PSZ256r:
10629 case VFMSUB213PSZ256rk:
10630 case VFMSUB213PSZ256rkz:
10631 case VFMSUB213PSZm:
10632 case VFMSUB213PSZmb:
10633 case VFMSUB213PSZmbk:
10634 case VFMSUB213PSZmbkz:
10635 case VFMSUB213PSZmk:
10636 case VFMSUB213PSZmkz:
10637 case VFMSUB213PSZr:
10638 case VFMSUB213PSZrb:
10639 case VFMSUB213PSZrbk:
10640 case VFMSUB213PSZrbkz:
10641 case VFMSUB213PSZrk:
10642 case VFMSUB213PSZrkz:
10643 case VFMSUB213PSm:
10644 case VFMSUB213PSr:
10645 return true;
10646 }
10647 return false;
10648}
10649
10650bool isPOPAL(unsigned Opcode) {
10651 return Opcode == POPA32;
10652}
10653
10654bool isVCVTPS2UQQ(unsigned Opcode) {
10655 switch (Opcode) {
10656 case VCVTPS2UQQZ128rm:
10657 case VCVTPS2UQQZ128rmb:
10658 case VCVTPS2UQQZ128rmbk:
10659 case VCVTPS2UQQZ128rmbkz:
10660 case VCVTPS2UQQZ128rmk:
10661 case VCVTPS2UQQZ128rmkz:
10662 case VCVTPS2UQQZ128rr:
10663 case VCVTPS2UQQZ128rrk:
10664 case VCVTPS2UQQZ128rrkz:
10665 case VCVTPS2UQQZ256rm:
10666 case VCVTPS2UQQZ256rmb:
10667 case VCVTPS2UQQZ256rmbk:
10668 case VCVTPS2UQQZ256rmbkz:
10669 case VCVTPS2UQQZ256rmk:
10670 case VCVTPS2UQQZ256rmkz:
10671 case VCVTPS2UQQZ256rr:
10672 case VCVTPS2UQQZ256rrk:
10673 case VCVTPS2UQQZ256rrkz:
10674 case VCVTPS2UQQZrm:
10675 case VCVTPS2UQQZrmb:
10676 case VCVTPS2UQQZrmbk:
10677 case VCVTPS2UQQZrmbkz:
10678 case VCVTPS2UQQZrmk:
10679 case VCVTPS2UQQZrmkz:
10680 case VCVTPS2UQQZrr:
10681 case VCVTPS2UQQZrrb:
10682 case VCVTPS2UQQZrrbk:
10683 case VCVTPS2UQQZrrbkz:
10684 case VCVTPS2UQQZrrk:
10685 case VCVTPS2UQQZrrkz:
10686 return true;
10687 }
10688 return false;
10689}
10690
10691bool isRDRAND(unsigned Opcode) {
10692 switch (Opcode) {
10693 case RDRAND16r:
10694 case RDRAND32r:
10695 case RDRAND64r:
10696 return true;
10697 }
10698 return false;
10699}
10700
10701bool isJCC(unsigned Opcode) {
10702 switch (Opcode) {
10703 case JCC_1:
10704 case JCC_2:
10705 case JCC_4:
10706 return true;
10707 }
10708 return false;
10709}
10710
10711bool isVPMINSQ(unsigned Opcode) {
10712 switch (Opcode) {
10713 case VPMINSQZ128rm:
10714 case VPMINSQZ128rmb:
10715 case VPMINSQZ128rmbk:
10716 case VPMINSQZ128rmbkz:
10717 case VPMINSQZ128rmk:
10718 case VPMINSQZ128rmkz:
10719 case VPMINSQZ128rr:
10720 case VPMINSQZ128rrk:
10721 case VPMINSQZ128rrkz:
10722 case VPMINSQZ256rm:
10723 case VPMINSQZ256rmb:
10724 case VPMINSQZ256rmbk:
10725 case VPMINSQZ256rmbkz:
10726 case VPMINSQZ256rmk:
10727 case VPMINSQZ256rmkz:
10728 case VPMINSQZ256rr:
10729 case VPMINSQZ256rrk:
10730 case VPMINSQZ256rrkz:
10731 case VPMINSQZrm:
10732 case VPMINSQZrmb:
10733 case VPMINSQZrmbk:
10734 case VPMINSQZrmbkz:
10735 case VPMINSQZrmk:
10736 case VPMINSQZrmkz:
10737 case VPMINSQZrr:
10738 case VPMINSQZrrk:
10739 case VPMINSQZrrkz:
10740 return true;
10741 }
10742 return false;
10743}
10744
10745bool isVADDSD(unsigned Opcode) {
10746 switch (Opcode) {
10747 case VADDSDZrm_Int:
10748 case VADDSDZrmk_Int:
10749 case VADDSDZrmkz_Int:
10750 case VADDSDZrr_Int:
10751 case VADDSDZrrb_Int:
10752 case VADDSDZrrbk_Int:
10753 case VADDSDZrrbkz_Int:
10754 case VADDSDZrrk_Int:
10755 case VADDSDZrrkz_Int:
10756 case VADDSDrm_Int:
10757 case VADDSDrr_Int:
10758 return true;
10759 }
10760 return false;
10761}
10762
10763bool isDPPS(unsigned Opcode) {
10764 switch (Opcode) {
10765 case DPPSrmi:
10766 case DPPSrri:
10767 return true;
10768 }
10769 return false;
10770}
10771
10772bool isPINSRQ(unsigned Opcode) {
10773 switch (Opcode) {
10774 case PINSRQrmi:
10775 case PINSRQrri:
10776 return true;
10777 }
10778 return false;
10779}
10780
10781bool isVUCOMISS(unsigned Opcode) {
10782 switch (Opcode) {
10783 case VUCOMISSZrm:
10784 case VUCOMISSZrr:
10785 case VUCOMISSZrrb:
10786 case VUCOMISSrm:
10787 case VUCOMISSrr:
10788 return true;
10789 }
10790 return false;
10791}
10792
10793bool isVPDPWSUD(unsigned Opcode) {
10794 switch (Opcode) {
10795 case VPDPWSUDYrm:
10796 case VPDPWSUDYrr:
10797 case VPDPWSUDZ128rm:
10798 case VPDPWSUDZ128rmb:
10799 case VPDPWSUDZ128rmbk:
10800 case VPDPWSUDZ128rmbkz:
10801 case VPDPWSUDZ128rmk:
10802 case VPDPWSUDZ128rmkz:
10803 case VPDPWSUDZ128rr:
10804 case VPDPWSUDZ128rrk:
10805 case VPDPWSUDZ128rrkz:
10806 case VPDPWSUDZ256rm:
10807 case VPDPWSUDZ256rmb:
10808 case VPDPWSUDZ256rmbk:
10809 case VPDPWSUDZ256rmbkz:
10810 case VPDPWSUDZ256rmk:
10811 case VPDPWSUDZ256rmkz:
10812 case VPDPWSUDZ256rr:
10813 case VPDPWSUDZ256rrk:
10814 case VPDPWSUDZ256rrkz:
10815 case VPDPWSUDZrm:
10816 case VPDPWSUDZrmb:
10817 case VPDPWSUDZrmbk:
10818 case VPDPWSUDZrmbkz:
10819 case VPDPWSUDZrmk:
10820 case VPDPWSUDZrmkz:
10821 case VPDPWSUDZrr:
10822 case VPDPWSUDZrrk:
10823 case VPDPWSUDZrrkz:
10824 case VPDPWSUDrm:
10825 case VPDPWSUDrr:
10826 return true;
10827 }
10828 return false;
10829}
10830
10831bool isKANDNW(unsigned Opcode) {
10832 return Opcode == KANDNWkk;
10833}
10834
10835bool isAOR(unsigned Opcode) {
10836 switch (Opcode) {
10837 case AOR32mr:
10838 case AOR32mr_EVEX:
10839 case AOR64mr:
10840 case AOR64mr_EVEX:
10841 return true;
10842 }
10843 return false;
10844}
10845
10846bool isPMAXUB(unsigned Opcode) {
10847 switch (Opcode) {
10848 case MMX_PMAXUBrm:
10849 case MMX_PMAXUBrr:
10850 case PMAXUBrm:
10851 case PMAXUBrr:
10852 return true;
10853 }
10854 return false;
10855}
10856
10857bool isANDNPD(unsigned Opcode) {
10858 switch (Opcode) {
10859 case ANDNPDrm:
10860 case ANDNPDrr:
10861 return true;
10862 }
10863 return false;
10864}
10865
10866bool isINVPCID(unsigned Opcode) {
10867 switch (Opcode) {
10868 case INVPCID32:
10869 case INVPCID64:
10870 case INVPCID64_EVEX:
10871 return true;
10872 }
10873 return false;
10874}
10875
10876bool isRDGSBASE(unsigned Opcode) {
10877 switch (Opcode) {
10878 case RDGSBASE:
10879 case RDGSBASE64:
10880 return true;
10881 }
10882 return false;
10883}
10884
10885bool isVPMOVSQD(unsigned Opcode) {
10886 switch (Opcode) {
10887 case VPMOVSQDZ128mr:
10888 case VPMOVSQDZ128mrk:
10889 case VPMOVSQDZ128rr:
10890 case VPMOVSQDZ128rrk:
10891 case VPMOVSQDZ128rrkz:
10892 case VPMOVSQDZ256mr:
10893 case VPMOVSQDZ256mrk:
10894 case VPMOVSQDZ256rr:
10895 case VPMOVSQDZ256rrk:
10896 case VPMOVSQDZ256rrkz:
10897 case VPMOVSQDZmr:
10898 case VPMOVSQDZmrk:
10899 case VPMOVSQDZrr:
10900 case VPMOVSQDZrrk:
10901 case VPMOVSQDZrrkz:
10902 return true;
10903 }
10904 return false;
10905}
10906
10907bool isBT(unsigned Opcode) {
10908 switch (Opcode) {
10909 case BT16mi8:
10910 case BT16mr:
10911 case BT16ri8:
10912 case BT16rr:
10913 case BT32mi8:
10914 case BT32mr:
10915 case BT32ri8:
10916 case BT32rr:
10917 case BT64mi8:
10918 case BT64mr:
10919 case BT64ri8:
10920 case BT64rr:
10921 return true;
10922 }
10923 return false;
10924}
10925
10926bool isVPROLVQ(unsigned Opcode) {
10927 switch (Opcode) {
10928 case VPROLVQZ128rm:
10929 case VPROLVQZ128rmb:
10930 case VPROLVQZ128rmbk:
10931 case VPROLVQZ128rmbkz:
10932 case VPROLVQZ128rmk:
10933 case VPROLVQZ128rmkz:
10934 case VPROLVQZ128rr:
10935 case VPROLVQZ128rrk:
10936 case VPROLVQZ128rrkz:
10937 case VPROLVQZ256rm:
10938 case VPROLVQZ256rmb:
10939 case VPROLVQZ256rmbk:
10940 case VPROLVQZ256rmbkz:
10941 case VPROLVQZ256rmk:
10942 case VPROLVQZ256rmkz:
10943 case VPROLVQZ256rr:
10944 case VPROLVQZ256rrk:
10945 case VPROLVQZ256rrkz:
10946 case VPROLVQZrm:
10947 case VPROLVQZrmb:
10948 case VPROLVQZrmbk:
10949 case VPROLVQZrmbkz:
10950 case VPROLVQZrmk:
10951 case VPROLVQZrmkz:
10952 case VPROLVQZrr:
10953 case VPROLVQZrrk:
10954 case VPROLVQZrrkz:
10955 return true;
10956 }
10957 return false;
10958}
10959
10960bool isVFMADDSUB132PD(unsigned Opcode) {
10961 switch (Opcode) {
10962 case VFMADDSUB132PDYm:
10963 case VFMADDSUB132PDYr:
10964 case VFMADDSUB132PDZ128m:
10965 case VFMADDSUB132PDZ128mb:
10966 case VFMADDSUB132PDZ128mbk:
10967 case VFMADDSUB132PDZ128mbkz:
10968 case VFMADDSUB132PDZ128mk:
10969 case VFMADDSUB132PDZ128mkz:
10970 case VFMADDSUB132PDZ128r:
10971 case VFMADDSUB132PDZ128rk:
10972 case VFMADDSUB132PDZ128rkz:
10973 case VFMADDSUB132PDZ256m:
10974 case VFMADDSUB132PDZ256mb:
10975 case VFMADDSUB132PDZ256mbk:
10976 case VFMADDSUB132PDZ256mbkz:
10977 case VFMADDSUB132PDZ256mk:
10978 case VFMADDSUB132PDZ256mkz:
10979 case VFMADDSUB132PDZ256r:
10980 case VFMADDSUB132PDZ256rk:
10981 case VFMADDSUB132PDZ256rkz:
10982 case VFMADDSUB132PDZm:
10983 case VFMADDSUB132PDZmb:
10984 case VFMADDSUB132PDZmbk:
10985 case VFMADDSUB132PDZmbkz:
10986 case VFMADDSUB132PDZmk:
10987 case VFMADDSUB132PDZmkz:
10988 case VFMADDSUB132PDZr:
10989 case VFMADDSUB132PDZrb:
10990 case VFMADDSUB132PDZrbk:
10991 case VFMADDSUB132PDZrbkz:
10992 case VFMADDSUB132PDZrk:
10993 case VFMADDSUB132PDZrkz:
10994 case VFMADDSUB132PDm:
10995 case VFMADDSUB132PDr:
10996 return true;
10997 }
10998 return false;
10999}
11000
11001bool isRORX(unsigned Opcode) {
11002 switch (Opcode) {
11003 case RORX32mi:
11004 case RORX32mi_EVEX:
11005 case RORX32ri:
11006 case RORX32ri_EVEX:
11007 case RORX64mi:
11008 case RORX64mi_EVEX:
11009 case RORX64ri:
11010 case RORX64ri_EVEX:
11011 return true;
11012 }
11013 return false;
11014}
11015
11016bool isPADDUSW(unsigned Opcode) {
11017 switch (Opcode) {
11018 case MMX_PADDUSWrm:
11019 case MMX_PADDUSWrr:
11020 case PADDUSWrm:
11021 case PADDUSWrr:
11022 return true;
11023 }
11024 return false;
11025}
11026
11027bool isPFNACC(unsigned Opcode) {
11028 switch (Opcode) {
11029 case PFNACCrm:
11030 case PFNACCrr:
11031 return true;
11032 }
11033 return false;
11034}
11035
11036bool isAND(unsigned Opcode) {
11037 switch (Opcode) {
11038 case AND16i16:
11039 case AND16mi:
11040 case AND16mi8:
11041 case AND16mi8_EVEX:
11042 case AND16mi8_ND:
11043 case AND16mi8_NF:
11044 case AND16mi8_NF_ND:
11045 case AND16mi_EVEX:
11046 case AND16mi_ND:
11047 case AND16mi_NF:
11048 case AND16mi_NF_ND:
11049 case AND16mr:
11050 case AND16mr_EVEX:
11051 case AND16mr_ND:
11052 case AND16mr_NF:
11053 case AND16mr_NF_ND:
11054 case AND16ri:
11055 case AND16ri8:
11056 case AND16ri8_EVEX:
11057 case AND16ri8_ND:
11058 case AND16ri8_NF:
11059 case AND16ri8_NF_ND:
11060 case AND16ri_EVEX:
11061 case AND16ri_ND:
11062 case AND16ri_NF:
11063 case AND16ri_NF_ND:
11064 case AND16rm:
11065 case AND16rm_EVEX:
11066 case AND16rm_ND:
11067 case AND16rm_NF:
11068 case AND16rm_NF_ND:
11069 case AND16rr:
11070 case AND16rr_EVEX:
11071 case AND16rr_EVEX_REV:
11072 case AND16rr_ND:
11073 case AND16rr_ND_REV:
11074 case AND16rr_NF:
11075 case AND16rr_NF_ND:
11076 case AND16rr_NF_ND_REV:
11077 case AND16rr_NF_REV:
11078 case AND16rr_REV:
11079 case AND32i32:
11080 case AND32mi:
11081 case AND32mi8:
11082 case AND32mi8_EVEX:
11083 case AND32mi8_ND:
11084 case AND32mi8_NF:
11085 case AND32mi8_NF_ND:
11086 case AND32mi_EVEX:
11087 case AND32mi_ND:
11088 case AND32mi_NF:
11089 case AND32mi_NF_ND:
11090 case AND32mr:
11091 case AND32mr_EVEX:
11092 case AND32mr_ND:
11093 case AND32mr_NF:
11094 case AND32mr_NF_ND:
11095 case AND32ri:
11096 case AND32ri8:
11097 case AND32ri8_EVEX:
11098 case AND32ri8_ND:
11099 case AND32ri8_NF:
11100 case AND32ri8_NF_ND:
11101 case AND32ri_EVEX:
11102 case AND32ri_ND:
11103 case AND32ri_NF:
11104 case AND32ri_NF_ND:
11105 case AND32rm:
11106 case AND32rm_EVEX:
11107 case AND32rm_ND:
11108 case AND32rm_NF:
11109 case AND32rm_NF_ND:
11110 case AND32rr:
11111 case AND32rr_EVEX:
11112 case AND32rr_EVEX_REV:
11113 case AND32rr_ND:
11114 case AND32rr_ND_REV:
11115 case AND32rr_NF:
11116 case AND32rr_NF_ND:
11117 case AND32rr_NF_ND_REV:
11118 case AND32rr_NF_REV:
11119 case AND32rr_REV:
11120 case AND64i32:
11121 case AND64mi32:
11122 case AND64mi32_EVEX:
11123 case AND64mi32_ND:
11124 case AND64mi32_NF:
11125 case AND64mi32_NF_ND:
11126 case AND64mi8:
11127 case AND64mi8_EVEX:
11128 case AND64mi8_ND:
11129 case AND64mi8_NF:
11130 case AND64mi8_NF_ND:
11131 case AND64mr:
11132 case AND64mr_EVEX:
11133 case AND64mr_ND:
11134 case AND64mr_NF:
11135 case AND64mr_NF_ND:
11136 case AND64ri32:
11137 case AND64ri32_EVEX:
11138 case AND64ri32_ND:
11139 case AND64ri32_NF:
11140 case AND64ri32_NF_ND:
11141 case AND64ri8:
11142 case AND64ri8_EVEX:
11143 case AND64ri8_ND:
11144 case AND64ri8_NF:
11145 case AND64ri8_NF_ND:
11146 case AND64rm:
11147 case AND64rm_EVEX:
11148 case AND64rm_ND:
11149 case AND64rm_NF:
11150 case AND64rm_NF_ND:
11151 case AND64rr:
11152 case AND64rr_EVEX:
11153 case AND64rr_EVEX_REV:
11154 case AND64rr_ND:
11155 case AND64rr_ND_REV:
11156 case AND64rr_NF:
11157 case AND64rr_NF_ND:
11158 case AND64rr_NF_ND_REV:
11159 case AND64rr_NF_REV:
11160 case AND64rr_REV:
11161 case AND8i8:
11162 case AND8mi:
11163 case AND8mi8:
11164 case AND8mi_EVEX:
11165 case AND8mi_ND:
11166 case AND8mi_NF:
11167 case AND8mi_NF_ND:
11168 case AND8mr:
11169 case AND8mr_EVEX:
11170 case AND8mr_ND:
11171 case AND8mr_NF:
11172 case AND8mr_NF_ND:
11173 case AND8ri:
11174 case AND8ri8:
11175 case AND8ri_EVEX:
11176 case AND8ri_ND:
11177 case AND8ri_NF:
11178 case AND8ri_NF_ND:
11179 case AND8rm:
11180 case AND8rm_EVEX:
11181 case AND8rm_ND:
11182 case AND8rm_NF:
11183 case AND8rm_NF_ND:
11184 case AND8rr:
11185 case AND8rr_EVEX:
11186 case AND8rr_EVEX_REV:
11187 case AND8rr_ND:
11188 case AND8rr_ND_REV:
11189 case AND8rr_NF:
11190 case AND8rr_NF_ND:
11191 case AND8rr_NF_ND_REV:
11192 case AND8rr_NF_REV:
11193 case AND8rr_REV:
11194 return true;
11195 }
11196 return false;
11197}
11198
11199bool isPSLLQ(unsigned Opcode) {
11200 switch (Opcode) {
11201 case MMX_PSLLQri:
11202 case MMX_PSLLQrm:
11203 case MMX_PSLLQrr:
11204 case PSLLQri:
11205 case PSLLQrm:
11206 case PSLLQrr:
11207 return true;
11208 }
11209 return false;
11210}
11211
11212bool isVFMSUB132PH(unsigned Opcode) {
11213 switch (Opcode) {
11214 case VFMSUB132PHZ128m:
11215 case VFMSUB132PHZ128mb:
11216 case VFMSUB132PHZ128mbk:
11217 case VFMSUB132PHZ128mbkz:
11218 case VFMSUB132PHZ128mk:
11219 case VFMSUB132PHZ128mkz:
11220 case VFMSUB132PHZ128r:
11221 case VFMSUB132PHZ128rk:
11222 case VFMSUB132PHZ128rkz:
11223 case VFMSUB132PHZ256m:
11224 case VFMSUB132PHZ256mb:
11225 case VFMSUB132PHZ256mbk:
11226 case VFMSUB132PHZ256mbkz:
11227 case VFMSUB132PHZ256mk:
11228 case VFMSUB132PHZ256mkz:
11229 case VFMSUB132PHZ256r:
11230 case VFMSUB132PHZ256rk:
11231 case VFMSUB132PHZ256rkz:
11232 case VFMSUB132PHZm:
11233 case VFMSUB132PHZmb:
11234 case VFMSUB132PHZmbk:
11235 case VFMSUB132PHZmbkz:
11236 case VFMSUB132PHZmk:
11237 case VFMSUB132PHZmkz:
11238 case VFMSUB132PHZr:
11239 case VFMSUB132PHZrb:
11240 case VFMSUB132PHZrbk:
11241 case VFMSUB132PHZrbkz:
11242 case VFMSUB132PHZrk:
11243 case VFMSUB132PHZrkz:
11244 return true;
11245 }
11246 return false;
11247}
11248
11249bool isXSAVE(unsigned Opcode) {
11250 return Opcode == XSAVE;
11251}
11252
11253bool isKNOTQ(unsigned Opcode) {
11254 return Opcode == KNOTQkk;
11255}
11256
11257bool isXTEST(unsigned Opcode) {
11258 return Opcode == XTEST;
11259}
11260
11261bool isVINSERTPS(unsigned Opcode) {
11262 switch (Opcode) {
11263 case VINSERTPSZrmi:
11264 case VINSERTPSZrri:
11265 case VINSERTPSrmi:
11266 case VINSERTPSrri:
11267 return true;
11268 }
11269 return false;
11270}
11271
11272bool isXSAVEOPT(unsigned Opcode) {
11273 return Opcode == XSAVEOPT;
11274}
11275
11276bool isLDS(unsigned Opcode) {
11277 switch (Opcode) {
11278 case LDS16rm:
11279 case LDS32rm:
11280 return true;
11281 }
11282 return false;
11283}
11284
11285bool isVFMADDSUB213PD(unsigned Opcode) {
11286 switch (Opcode) {
11287 case VFMADDSUB213PDYm:
11288 case VFMADDSUB213PDYr:
11289 case VFMADDSUB213PDZ128m:
11290 case VFMADDSUB213PDZ128mb:
11291 case VFMADDSUB213PDZ128mbk:
11292 case VFMADDSUB213PDZ128mbkz:
11293 case VFMADDSUB213PDZ128mk:
11294 case VFMADDSUB213PDZ128mkz:
11295 case VFMADDSUB213PDZ128r:
11296 case VFMADDSUB213PDZ128rk:
11297 case VFMADDSUB213PDZ128rkz:
11298 case VFMADDSUB213PDZ256m:
11299 case VFMADDSUB213PDZ256mb:
11300 case VFMADDSUB213PDZ256mbk:
11301 case VFMADDSUB213PDZ256mbkz:
11302 case VFMADDSUB213PDZ256mk:
11303 case VFMADDSUB213PDZ256mkz:
11304 case VFMADDSUB213PDZ256r:
11305 case VFMADDSUB213PDZ256rk:
11306 case VFMADDSUB213PDZ256rkz:
11307 case VFMADDSUB213PDZm:
11308 case VFMADDSUB213PDZmb:
11309 case VFMADDSUB213PDZmbk:
11310 case VFMADDSUB213PDZmbkz:
11311 case VFMADDSUB213PDZmk:
11312 case VFMADDSUB213PDZmkz:
11313 case VFMADDSUB213PDZr:
11314 case VFMADDSUB213PDZrb:
11315 case VFMADDSUB213PDZrbk:
11316 case VFMADDSUB213PDZrbkz:
11317 case VFMADDSUB213PDZrk:
11318 case VFMADDSUB213PDZrkz:
11319 case VFMADDSUB213PDm:
11320 case VFMADDSUB213PDr:
11321 return true;
11322 }
11323 return false;
11324}
11325
11326bool isVINSERTF32X4(unsigned Opcode) {
11327 switch (Opcode) {
11328 case VINSERTF32X4Z256rmi:
11329 case VINSERTF32X4Z256rmik:
11330 case VINSERTF32X4Z256rmikz:
11331 case VINSERTF32X4Z256rri:
11332 case VINSERTF32X4Z256rrik:
11333 case VINSERTF32X4Z256rrikz:
11334 case VINSERTF32X4Zrmi:
11335 case VINSERTF32X4Zrmik:
11336 case VINSERTF32X4Zrmikz:
11337 case VINSERTF32X4Zrri:
11338 case VINSERTF32X4Zrrik:
11339 case VINSERTF32X4Zrrikz:
11340 return true;
11341 }
11342 return false;
11343}
11344
11345bool isVRSQRTPS(unsigned Opcode) {
11346 switch (Opcode) {
11347 case VRSQRTPSYm:
11348 case VRSQRTPSYr:
11349 case VRSQRTPSm:
11350 case VRSQRTPSr:
11351 return true;
11352 }
11353 return false;
11354}
11355
11356bool isVSUBPH(unsigned Opcode) {
11357 switch (Opcode) {
11358 case VSUBPHZ128rm:
11359 case VSUBPHZ128rmb:
11360 case VSUBPHZ128rmbk:
11361 case VSUBPHZ128rmbkz:
11362 case VSUBPHZ128rmk:
11363 case VSUBPHZ128rmkz:
11364 case VSUBPHZ128rr:
11365 case VSUBPHZ128rrk:
11366 case VSUBPHZ128rrkz:
11367 case VSUBPHZ256rm:
11368 case VSUBPHZ256rmb:
11369 case VSUBPHZ256rmbk:
11370 case VSUBPHZ256rmbkz:
11371 case VSUBPHZ256rmk:
11372 case VSUBPHZ256rmkz:
11373 case VSUBPHZ256rr:
11374 case VSUBPHZ256rrk:
11375 case VSUBPHZ256rrkz:
11376 case VSUBPHZrm:
11377 case VSUBPHZrmb:
11378 case VSUBPHZrmbk:
11379 case VSUBPHZrmbkz:
11380 case VSUBPHZrmk:
11381 case VSUBPHZrmkz:
11382 case VSUBPHZrr:
11383 case VSUBPHZrrb:
11384 case VSUBPHZrrbk:
11385 case VSUBPHZrrbkz:
11386 case VSUBPHZrrk:
11387 case VSUBPHZrrkz:
11388 return true;
11389 }
11390 return false;
11391}
11392
11393bool isPMOVSXBW(unsigned Opcode) {
11394 switch (Opcode) {
11395 case PMOVSXBWrm:
11396 case PMOVSXBWrr:
11397 return true;
11398 }
11399 return false;
11400}
11401
11402bool isVPSRLDQ(unsigned Opcode) {
11403 switch (Opcode) {
11404 case VPSRLDQYri:
11405 case VPSRLDQZ128mi:
11406 case VPSRLDQZ128ri:
11407 case VPSRLDQZ256mi:
11408 case VPSRLDQZ256ri:
11409 case VPSRLDQZmi:
11410 case VPSRLDQZri:
11411 case VPSRLDQri:
11412 return true;
11413 }
11414 return false;
11415}
11416
11417bool isADC(unsigned Opcode) {
11418 switch (Opcode) {
11419 case ADC16i16:
11420 case ADC16mi:
11421 case ADC16mi8:
11422 case ADC16mi8_EVEX:
11423 case ADC16mi8_ND:
11424 case ADC16mi_EVEX:
11425 case ADC16mi_ND:
11426 case ADC16mr:
11427 case ADC16mr_EVEX:
11428 case ADC16mr_ND:
11429 case ADC16ri:
11430 case ADC16ri8:
11431 case ADC16ri8_EVEX:
11432 case ADC16ri8_ND:
11433 case ADC16ri_EVEX:
11434 case ADC16ri_ND:
11435 case ADC16rm:
11436 case ADC16rm_EVEX:
11437 case ADC16rm_ND:
11438 case ADC16rr:
11439 case ADC16rr_EVEX:
11440 case ADC16rr_EVEX_REV:
11441 case ADC16rr_ND:
11442 case ADC16rr_ND_REV:
11443 case ADC16rr_REV:
11444 case ADC32i32:
11445 case ADC32mi:
11446 case ADC32mi8:
11447 case ADC32mi8_EVEX:
11448 case ADC32mi8_ND:
11449 case ADC32mi_EVEX:
11450 case ADC32mi_ND:
11451 case ADC32mr:
11452 case ADC32mr_EVEX:
11453 case ADC32mr_ND:
11454 case ADC32ri:
11455 case ADC32ri8:
11456 case ADC32ri8_EVEX:
11457 case ADC32ri8_ND:
11458 case ADC32ri_EVEX:
11459 case ADC32ri_ND:
11460 case ADC32rm:
11461 case ADC32rm_EVEX:
11462 case ADC32rm_ND:
11463 case ADC32rr:
11464 case ADC32rr_EVEX:
11465 case ADC32rr_EVEX_REV:
11466 case ADC32rr_ND:
11467 case ADC32rr_ND_REV:
11468 case ADC32rr_REV:
11469 case ADC64i32:
11470 case ADC64mi32:
11471 case ADC64mi32_EVEX:
11472 case ADC64mi32_ND:
11473 case ADC64mi8:
11474 case ADC64mi8_EVEX:
11475 case ADC64mi8_ND:
11476 case ADC64mr:
11477 case ADC64mr_EVEX:
11478 case ADC64mr_ND:
11479 case ADC64ri32:
11480 case ADC64ri32_EVEX:
11481 case ADC64ri32_ND:
11482 case ADC64ri8:
11483 case ADC64ri8_EVEX:
11484 case ADC64ri8_ND:
11485 case ADC64rm:
11486 case ADC64rm_EVEX:
11487 case ADC64rm_ND:
11488 case ADC64rr:
11489 case ADC64rr_EVEX:
11490 case ADC64rr_EVEX_REV:
11491 case ADC64rr_ND:
11492 case ADC64rr_ND_REV:
11493 case ADC64rr_REV:
11494 case ADC8i8:
11495 case ADC8mi:
11496 case ADC8mi8:
11497 case ADC8mi_EVEX:
11498 case ADC8mi_ND:
11499 case ADC8mr:
11500 case ADC8mr_EVEX:
11501 case ADC8mr_ND:
11502 case ADC8ri:
11503 case ADC8ri8:
11504 case ADC8ri_EVEX:
11505 case ADC8ri_ND:
11506 case ADC8rm:
11507 case ADC8rm_EVEX:
11508 case ADC8rm_ND:
11509 case ADC8rr:
11510 case ADC8rr_EVEX:
11511 case ADC8rr_EVEX_REV:
11512 case ADC8rr_ND:
11513 case ADC8rr_ND_REV:
11514 case ADC8rr_REV:
11515 return true;
11516 }
11517 return false;
11518}
11519
11520bool isPHADDD(unsigned Opcode) {
11521 switch (Opcode) {
11522 case MMX_PHADDDrm:
11523 case MMX_PHADDDrr:
11524 case PHADDDrm:
11525 case PHADDDrr:
11526 return true;
11527 }
11528 return false;
11529}
11530
11531bool isVDPPHPS(unsigned Opcode) {
11532 switch (Opcode) {
11533 case VDPPHPSZ128m:
11534 case VDPPHPSZ128mb:
11535 case VDPPHPSZ128mbk:
11536 case VDPPHPSZ128mbkz:
11537 case VDPPHPSZ128mk:
11538 case VDPPHPSZ128mkz:
11539 case VDPPHPSZ128r:
11540 case VDPPHPSZ128rk:
11541 case VDPPHPSZ128rkz:
11542 case VDPPHPSZ256m:
11543 case VDPPHPSZ256mb:
11544 case VDPPHPSZ256mbk:
11545 case VDPPHPSZ256mbkz:
11546 case VDPPHPSZ256mk:
11547 case VDPPHPSZ256mkz:
11548 case VDPPHPSZ256r:
11549 case VDPPHPSZ256rk:
11550 case VDPPHPSZ256rkz:
11551 case VDPPHPSZm:
11552 case VDPPHPSZmb:
11553 case VDPPHPSZmbk:
11554 case VDPPHPSZmbkz:
11555 case VDPPHPSZmk:
11556 case VDPPHPSZmkz:
11557 case VDPPHPSZr:
11558 case VDPPHPSZrk:
11559 case VDPPHPSZrkz:
11560 return true;
11561 }
11562 return false;
11563}
11564
11565bool isVMINPH(unsigned Opcode) {
11566 switch (Opcode) {
11567 case VMINPHZ128rm:
11568 case VMINPHZ128rmb:
11569 case VMINPHZ128rmbk:
11570 case VMINPHZ128rmbkz:
11571 case VMINPHZ128rmk:
11572 case VMINPHZ128rmkz:
11573 case VMINPHZ128rr:
11574 case VMINPHZ128rrk:
11575 case VMINPHZ128rrkz:
11576 case VMINPHZ256rm:
11577 case VMINPHZ256rmb:
11578 case VMINPHZ256rmbk:
11579 case VMINPHZ256rmbkz:
11580 case VMINPHZ256rmk:
11581 case VMINPHZ256rmkz:
11582 case VMINPHZ256rr:
11583 case VMINPHZ256rrk:
11584 case VMINPHZ256rrkz:
11585 case VMINPHZrm:
11586 case VMINPHZrmb:
11587 case VMINPHZrmbk:
11588 case VMINPHZrmbkz:
11589 case VMINPHZrmk:
11590 case VMINPHZrmkz:
11591 case VMINPHZrr:
11592 case VMINPHZrrb:
11593 case VMINPHZrrbk:
11594 case VMINPHZrrbkz:
11595 case VMINPHZrrk:
11596 case VMINPHZrrkz:
11597 return true;
11598 }
11599 return false;
11600}
11601
11602bool isVMINSD(unsigned Opcode) {
11603 switch (Opcode) {
11604 case VMINSDZrm_Int:
11605 case VMINSDZrmk_Int:
11606 case VMINSDZrmkz_Int:
11607 case VMINSDZrr_Int:
11608 case VMINSDZrrb_Int:
11609 case VMINSDZrrbk_Int:
11610 case VMINSDZrrbkz_Int:
11611 case VMINSDZrrk_Int:
11612 case VMINSDZrrkz_Int:
11613 case VMINSDrm_Int:
11614 case VMINSDrr_Int:
11615 return true;
11616 }
11617 return false;
11618}
11619
11620bool isVROUNDPD(unsigned Opcode) {
11621 switch (Opcode) {
11622 case VROUNDPDYmi:
11623 case VROUNDPDYri:
11624 case VROUNDPDmi:
11625 case VROUNDPDri:
11626 return true;
11627 }
11628 return false;
11629}
11630
11631bool isVFCMADDCPH(unsigned Opcode) {
11632 switch (Opcode) {
11633 case VFCMADDCPHZ128m:
11634 case VFCMADDCPHZ128mb:
11635 case VFCMADDCPHZ128mbk:
11636 case VFCMADDCPHZ128mbkz:
11637 case VFCMADDCPHZ128mk:
11638 case VFCMADDCPHZ128mkz:
11639 case VFCMADDCPHZ128r:
11640 case VFCMADDCPHZ128rk:
11641 case VFCMADDCPHZ128rkz:
11642 case VFCMADDCPHZ256m:
11643 case VFCMADDCPHZ256mb:
11644 case VFCMADDCPHZ256mbk:
11645 case VFCMADDCPHZ256mbkz:
11646 case VFCMADDCPHZ256mk:
11647 case VFCMADDCPHZ256mkz:
11648 case VFCMADDCPHZ256r:
11649 case VFCMADDCPHZ256rk:
11650 case VFCMADDCPHZ256rkz:
11651 case VFCMADDCPHZm:
11652 case VFCMADDCPHZmb:
11653 case VFCMADDCPHZmbk:
11654 case VFCMADDCPHZmbkz:
11655 case VFCMADDCPHZmk:
11656 case VFCMADDCPHZmkz:
11657 case VFCMADDCPHZr:
11658 case VFCMADDCPHZrb:
11659 case VFCMADDCPHZrbk:
11660 case VFCMADDCPHZrbkz:
11661 case VFCMADDCPHZrk:
11662 case VFCMADDCPHZrkz:
11663 return true;
11664 }
11665 return false;
11666}
11667
11668bool isINCSSPQ(unsigned Opcode) {
11669 return Opcode == INCSSPQ;
11670}
11671
11672bool isVPUNPCKLDQ(unsigned Opcode) {
11673 switch (Opcode) {
11674 case VPUNPCKLDQYrm:
11675 case VPUNPCKLDQYrr:
11676 case VPUNPCKLDQZ128rm:
11677 case VPUNPCKLDQZ128rmb:
11678 case VPUNPCKLDQZ128rmbk:
11679 case VPUNPCKLDQZ128rmbkz:
11680 case VPUNPCKLDQZ128rmk:
11681 case VPUNPCKLDQZ128rmkz:
11682 case VPUNPCKLDQZ128rr:
11683 case VPUNPCKLDQZ128rrk:
11684 case VPUNPCKLDQZ128rrkz:
11685 case VPUNPCKLDQZ256rm:
11686 case VPUNPCKLDQZ256rmb:
11687 case VPUNPCKLDQZ256rmbk:
11688 case VPUNPCKLDQZ256rmbkz:
11689 case VPUNPCKLDQZ256rmk:
11690 case VPUNPCKLDQZ256rmkz:
11691 case VPUNPCKLDQZ256rr:
11692 case VPUNPCKLDQZ256rrk:
11693 case VPUNPCKLDQZ256rrkz:
11694 case VPUNPCKLDQZrm:
11695 case VPUNPCKLDQZrmb:
11696 case VPUNPCKLDQZrmbk:
11697 case VPUNPCKLDQZrmbkz:
11698 case VPUNPCKLDQZrmk:
11699 case VPUNPCKLDQZrmkz:
11700 case VPUNPCKLDQZrr:
11701 case VPUNPCKLDQZrrk:
11702 case VPUNPCKLDQZrrkz:
11703 case VPUNPCKLDQrm:
11704 case VPUNPCKLDQrr:
11705 return true;
11706 }
11707 return false;
11708}
11709
11710bool isVMINSH(unsigned Opcode) {
11711 switch (Opcode) {
11712 case VMINSHZrm_Int:
11713 case VMINSHZrmk_Int:
11714 case VMINSHZrmkz_Int:
11715 case VMINSHZrr_Int:
11716 case VMINSHZrrb_Int:
11717 case VMINSHZrrbk_Int:
11718 case VMINSHZrrbkz_Int:
11719 case VMINSHZrrk_Int:
11720 case VMINSHZrrkz_Int:
11721 return true;
11722 }
11723 return false;
11724}
11725
11726bool isINSERTQ(unsigned Opcode) {
11727 switch (Opcode) {
11728 case INSERTQ:
11729 case INSERTQI:
11730 return true;
11731 }
11732 return false;
11733}
11734
11735bool isBLCI(unsigned Opcode) {
11736 switch (Opcode) {
11737 case BLCI32rm:
11738 case BLCI32rr:
11739 case BLCI64rm:
11740 case BLCI64rr:
11741 return true;
11742 }
11743 return false;
11744}
11745
11746bool isHLT(unsigned Opcode) {
11747 return Opcode == HLT;
11748}
11749
11750bool isVPCOMUW(unsigned Opcode) {
11751 switch (Opcode) {
11752 case VPCOMUWmi:
11753 case VPCOMUWri:
11754 return true;
11755 }
11756 return false;
11757}
11758
11759bool isVPMOVSXDQ(unsigned Opcode) {
11760 switch (Opcode) {
11761 case VPMOVSXDQYrm:
11762 case VPMOVSXDQYrr:
11763 case VPMOVSXDQZ128rm:
11764 case VPMOVSXDQZ128rmk:
11765 case VPMOVSXDQZ128rmkz:
11766 case VPMOVSXDQZ128rr:
11767 case VPMOVSXDQZ128rrk:
11768 case VPMOVSXDQZ128rrkz:
11769 case VPMOVSXDQZ256rm:
11770 case VPMOVSXDQZ256rmk:
11771 case VPMOVSXDQZ256rmkz:
11772 case VPMOVSXDQZ256rr:
11773 case VPMOVSXDQZ256rrk:
11774 case VPMOVSXDQZ256rrkz:
11775 case VPMOVSXDQZrm:
11776 case VPMOVSXDQZrmk:
11777 case VPMOVSXDQZrmkz:
11778 case VPMOVSXDQZrr:
11779 case VPMOVSXDQZrrk:
11780 case VPMOVSXDQZrrkz:
11781 case VPMOVSXDQrm:
11782 case VPMOVSXDQrr:
11783 return true;
11784 }
11785 return false;
11786}
11787
11788bool isVFNMSUB231PS(unsigned Opcode) {
11789 switch (Opcode) {
11790 case VFNMSUB231PSYm:
11791 case VFNMSUB231PSYr:
11792 case VFNMSUB231PSZ128m:
11793 case VFNMSUB231PSZ128mb:
11794 case VFNMSUB231PSZ128mbk:
11795 case VFNMSUB231PSZ128mbkz:
11796 case VFNMSUB231PSZ128mk:
11797 case VFNMSUB231PSZ128mkz:
11798 case VFNMSUB231PSZ128r:
11799 case VFNMSUB231PSZ128rk:
11800 case VFNMSUB231PSZ128rkz:
11801 case VFNMSUB231PSZ256m:
11802 case VFNMSUB231PSZ256mb:
11803 case VFNMSUB231PSZ256mbk:
11804 case VFNMSUB231PSZ256mbkz:
11805 case VFNMSUB231PSZ256mk:
11806 case VFNMSUB231PSZ256mkz:
11807 case VFNMSUB231PSZ256r:
11808 case VFNMSUB231PSZ256rk:
11809 case VFNMSUB231PSZ256rkz:
11810 case VFNMSUB231PSZm:
11811 case VFNMSUB231PSZmb:
11812 case VFNMSUB231PSZmbk:
11813 case VFNMSUB231PSZmbkz:
11814 case VFNMSUB231PSZmk:
11815 case VFNMSUB231PSZmkz:
11816 case VFNMSUB231PSZr:
11817 case VFNMSUB231PSZrb:
11818 case VFNMSUB231PSZrbk:
11819 case VFNMSUB231PSZrbkz:
11820 case VFNMSUB231PSZrk:
11821 case VFNMSUB231PSZrkz:
11822 case VFNMSUB231PSm:
11823 case VFNMSUB231PSr:
11824 return true;
11825 }
11826 return false;
11827}
11828
11829bool isVFNMSUB213SH(unsigned Opcode) {
11830 switch (Opcode) {
11831 case VFNMSUB213SHZm_Int:
11832 case VFNMSUB213SHZmk_Int:
11833 case VFNMSUB213SHZmkz_Int:
11834 case VFNMSUB213SHZr_Int:
11835 case VFNMSUB213SHZrb_Int:
11836 case VFNMSUB213SHZrbk_Int:
11837 case VFNMSUB213SHZrbkz_Int:
11838 case VFNMSUB213SHZrk_Int:
11839 case VFNMSUB213SHZrkz_Int:
11840 return true;
11841 }
11842 return false;
11843}
11844
11845bool isVCVTTPD2UQQ(unsigned Opcode) {
11846 switch (Opcode) {
11847 case VCVTTPD2UQQZ128rm:
11848 case VCVTTPD2UQQZ128rmb:
11849 case VCVTTPD2UQQZ128rmbk:
11850 case VCVTTPD2UQQZ128rmbkz:
11851 case VCVTTPD2UQQZ128rmk:
11852 case VCVTTPD2UQQZ128rmkz:
11853 case VCVTTPD2UQQZ128rr:
11854 case VCVTTPD2UQQZ128rrk:
11855 case VCVTTPD2UQQZ128rrkz:
11856 case VCVTTPD2UQQZ256rm:
11857 case VCVTTPD2UQQZ256rmb:
11858 case VCVTTPD2UQQZ256rmbk:
11859 case VCVTTPD2UQQZ256rmbkz:
11860 case VCVTTPD2UQQZ256rmk:
11861 case VCVTTPD2UQQZ256rmkz:
11862 case VCVTTPD2UQQZ256rr:
11863 case VCVTTPD2UQQZ256rrk:
11864 case VCVTTPD2UQQZ256rrkz:
11865 case VCVTTPD2UQQZrm:
11866 case VCVTTPD2UQQZrmb:
11867 case VCVTTPD2UQQZrmbk:
11868 case VCVTTPD2UQQZrmbkz:
11869 case VCVTTPD2UQQZrmk:
11870 case VCVTTPD2UQQZrmkz:
11871 case VCVTTPD2UQQZrr:
11872 case VCVTTPD2UQQZrrb:
11873 case VCVTTPD2UQQZrrbk:
11874 case VCVTTPD2UQQZrrbkz:
11875 case VCVTTPD2UQQZrrk:
11876 case VCVTTPD2UQQZrrkz:
11877 return true;
11878 }
11879 return false;
11880}
11881
11882bool isSQRTSS(unsigned Opcode) {
11883 switch (Opcode) {
11884 case SQRTSSm_Int:
11885 case SQRTSSr_Int:
11886 return true;
11887 }
11888 return false;
11889}
11890
11891bool isIMUL(unsigned Opcode) {
11892 switch (Opcode) {
11893 case IMUL16m:
11894 case IMUL16m_EVEX:
11895 case IMUL16m_NF:
11896 case IMUL16r:
11897 case IMUL16r_EVEX:
11898 case IMUL16r_NF:
11899 case IMUL16rm:
11900 case IMUL16rm_EVEX:
11901 case IMUL16rm_ND:
11902 case IMUL16rm_NF:
11903 case IMUL16rm_NF_ND:
11904 case IMUL16rmi:
11905 case IMUL16rmi8:
11906 case IMUL16rmi8_EVEX:
11907 case IMUL16rmi8_NF:
11908 case IMUL16rmi_EVEX:
11909 case IMUL16rmi_NF:
11910 case IMUL16rr:
11911 case IMUL16rr_EVEX:
11912 case IMUL16rr_ND:
11913 case IMUL16rr_NF:
11914 case IMUL16rr_NF_ND:
11915 case IMUL16rri:
11916 case IMUL16rri8:
11917 case IMUL16rri8_EVEX:
11918 case IMUL16rri8_NF:
11919 case IMUL16rri_EVEX:
11920 case IMUL16rri_NF:
11921 case IMUL32m:
11922 case IMUL32m_EVEX:
11923 case IMUL32m_NF:
11924 case IMUL32r:
11925 case IMUL32r_EVEX:
11926 case IMUL32r_NF:
11927 case IMUL32rm:
11928 case IMUL32rm_EVEX:
11929 case IMUL32rm_ND:
11930 case IMUL32rm_NF:
11931 case IMUL32rm_NF_ND:
11932 case IMUL32rmi:
11933 case IMUL32rmi8:
11934 case IMUL32rmi8_EVEX:
11935 case IMUL32rmi8_NF:
11936 case IMUL32rmi_EVEX:
11937 case IMUL32rmi_NF:
11938 case IMUL32rr:
11939 case IMUL32rr_EVEX:
11940 case IMUL32rr_ND:
11941 case IMUL32rr_NF:
11942 case IMUL32rr_NF_ND:
11943 case IMUL32rri:
11944 case IMUL32rri8:
11945 case IMUL32rri8_EVEX:
11946 case IMUL32rri8_NF:
11947 case IMUL32rri_EVEX:
11948 case IMUL32rri_NF:
11949 case IMUL64m:
11950 case IMUL64m_EVEX:
11951 case IMUL64m_NF:
11952 case IMUL64r:
11953 case IMUL64r_EVEX:
11954 case IMUL64r_NF:
11955 case IMUL64rm:
11956 case IMUL64rm_EVEX:
11957 case IMUL64rm_ND:
11958 case IMUL64rm_NF:
11959 case IMUL64rm_NF_ND:
11960 case IMUL64rmi32:
11961 case IMUL64rmi32_EVEX:
11962 case IMUL64rmi32_NF:
11963 case IMUL64rmi8:
11964 case IMUL64rmi8_EVEX:
11965 case IMUL64rmi8_NF:
11966 case IMUL64rr:
11967 case IMUL64rr_EVEX:
11968 case IMUL64rr_ND:
11969 case IMUL64rr_NF:
11970 case IMUL64rr_NF_ND:
11971 case IMUL64rri32:
11972 case IMUL64rri32_EVEX:
11973 case IMUL64rri32_NF:
11974 case IMUL64rri8:
11975 case IMUL64rri8_EVEX:
11976 case IMUL64rri8_NF:
11977 case IMUL8m:
11978 case IMUL8m_EVEX:
11979 case IMUL8m_NF:
11980 case IMUL8r:
11981 case IMUL8r_EVEX:
11982 case IMUL8r_NF:
11983 return true;
11984 }
11985 return false;
11986}
11987
11988bool isVCVTSS2SI(unsigned Opcode) {
11989 switch (Opcode) {
11990 case VCVTSS2SI64Zrm_Int:
11991 case VCVTSS2SI64Zrr_Int:
11992 case VCVTSS2SI64Zrrb_Int:
11993 case VCVTSS2SI64rm_Int:
11994 case VCVTSS2SI64rr_Int:
11995 case VCVTSS2SIZrm_Int:
11996 case VCVTSS2SIZrr_Int:
11997 case VCVTSS2SIZrrb_Int:
11998 case VCVTSS2SIrm_Int:
11999 case VCVTSS2SIrr_Int:
12000 return true;
12001 }
12002 return false;
12003}
12004
12005bool isPUSHAW(unsigned Opcode) {
12006 return Opcode == PUSHA16;
12007}
12008
12009bool isSTOSD(unsigned Opcode) {
12010 return Opcode == STOSL;
12011}
12012
12013bool isPSRLDQ(unsigned Opcode) {
12014 return Opcode == PSRLDQri;
12015}
12016
12017bool isVSCATTERQPS(unsigned Opcode) {
12018 switch (Opcode) {
12019 case VSCATTERQPSZ128mr:
12020 case VSCATTERQPSZ256mr:
12021 case VSCATTERQPSZmr:
12022 return true;
12023 }
12024 return false;
12025}
12026
12027bool isFIDIV(unsigned Opcode) {
12028 switch (Opcode) {
12029 case DIV_FI16m:
12030 case DIV_FI32m:
12031 return true;
12032 }
12033 return false;
12034}
12035
12036bool isVFMSUB213PD(unsigned Opcode) {
12037 switch (Opcode) {
12038 case VFMSUB213PDYm:
12039 case VFMSUB213PDYr:
12040 case VFMSUB213PDZ128m:
12041 case VFMSUB213PDZ128mb:
12042 case VFMSUB213PDZ128mbk:
12043 case VFMSUB213PDZ128mbkz:
12044 case VFMSUB213PDZ128mk:
12045 case VFMSUB213PDZ128mkz:
12046 case VFMSUB213PDZ128r:
12047 case VFMSUB213PDZ128rk:
12048 case VFMSUB213PDZ128rkz:
12049 case VFMSUB213PDZ256m:
12050 case VFMSUB213PDZ256mb:
12051 case VFMSUB213PDZ256mbk:
12052 case VFMSUB213PDZ256mbkz:
12053 case VFMSUB213PDZ256mk:
12054 case VFMSUB213PDZ256mkz:
12055 case VFMSUB213PDZ256r:
12056 case VFMSUB213PDZ256rk:
12057 case VFMSUB213PDZ256rkz:
12058 case VFMSUB213PDZm:
12059 case VFMSUB213PDZmb:
12060 case VFMSUB213PDZmbk:
12061 case VFMSUB213PDZmbkz:
12062 case VFMSUB213PDZmk:
12063 case VFMSUB213PDZmkz:
12064 case VFMSUB213PDZr:
12065 case VFMSUB213PDZrb:
12066 case VFMSUB213PDZrbk:
12067 case VFMSUB213PDZrbkz:
12068 case VFMSUB213PDZrk:
12069 case VFMSUB213PDZrkz:
12070 case VFMSUB213PDm:
12071 case VFMSUB213PDr:
12072 return true;
12073 }
12074 return false;
12075}
12076
12077bool isVFMADDSUB231PH(unsigned Opcode) {
12078 switch (Opcode) {
12079 case VFMADDSUB231PHZ128m:
12080 case VFMADDSUB231PHZ128mb:
12081 case VFMADDSUB231PHZ128mbk:
12082 case VFMADDSUB231PHZ128mbkz:
12083 case VFMADDSUB231PHZ128mk:
12084 case VFMADDSUB231PHZ128mkz:
12085 case VFMADDSUB231PHZ128r:
12086 case VFMADDSUB231PHZ128rk:
12087 case VFMADDSUB231PHZ128rkz:
12088 case VFMADDSUB231PHZ256m:
12089 case VFMADDSUB231PHZ256mb:
12090 case VFMADDSUB231PHZ256mbk:
12091 case VFMADDSUB231PHZ256mbkz:
12092 case VFMADDSUB231PHZ256mk:
12093 case VFMADDSUB231PHZ256mkz:
12094 case VFMADDSUB231PHZ256r:
12095 case VFMADDSUB231PHZ256rk:
12096 case VFMADDSUB231PHZ256rkz:
12097 case VFMADDSUB231PHZm:
12098 case VFMADDSUB231PHZmb:
12099 case VFMADDSUB231PHZmbk:
12100 case VFMADDSUB231PHZmbkz:
12101 case VFMADDSUB231PHZmk:
12102 case VFMADDSUB231PHZmkz:
12103 case VFMADDSUB231PHZr:
12104 case VFMADDSUB231PHZrb:
12105 case VFMADDSUB231PHZrbk:
12106 case VFMADDSUB231PHZrbkz:
12107 case VFMADDSUB231PHZrk:
12108 case VFMADDSUB231PHZrkz:
12109 return true;
12110 }
12111 return false;
12112}
12113
12114bool isTDCALL(unsigned Opcode) {
12115 return Opcode == TDCALL;
12116}
12117
12118bool isPVALIDATE(unsigned Opcode) {
12119 switch (Opcode) {
12120 case PVALIDATE32:
12121 case PVALIDATE64:
12122 return true;
12123 }
12124 return false;
12125}
12126
12127bool isVPSHUFLW(unsigned Opcode) {
12128 switch (Opcode) {
12129 case VPSHUFLWYmi:
12130 case VPSHUFLWYri:
12131 case VPSHUFLWZ128mi:
12132 case VPSHUFLWZ128mik:
12133 case VPSHUFLWZ128mikz:
12134 case VPSHUFLWZ128ri:
12135 case VPSHUFLWZ128rik:
12136 case VPSHUFLWZ128rikz:
12137 case VPSHUFLWZ256mi:
12138 case VPSHUFLWZ256mik:
12139 case VPSHUFLWZ256mikz:
12140 case VPSHUFLWZ256ri:
12141 case VPSHUFLWZ256rik:
12142 case VPSHUFLWZ256rikz:
12143 case VPSHUFLWZmi:
12144 case VPSHUFLWZmik:
12145 case VPSHUFLWZmikz:
12146 case VPSHUFLWZri:
12147 case VPSHUFLWZrik:
12148 case VPSHUFLWZrikz:
12149 case VPSHUFLWmi:
12150 case VPSHUFLWri:
12151 return true;
12152 }
12153 return false;
12154}
12155
12156bool isPCLMULQDQ(unsigned Opcode) {
12157 switch (Opcode) {
12158 case PCLMULQDQrmi:
12159 case PCLMULQDQrri:
12160 return true;
12161 }
12162 return false;
12163}
12164
12165bool isCMPXCHG8B(unsigned Opcode) {
12166 return Opcode == CMPXCHG8B;
12167}
12168
12169bool isVPMOVM2B(unsigned Opcode) {
12170 switch (Opcode) {
12171 case VPMOVM2BZ128rk:
12172 case VPMOVM2BZ256rk:
12173 case VPMOVM2BZrk:
12174 return true;
12175 }
12176 return false;
12177}
12178
12179bool isVCVTUDQ2PH(unsigned Opcode) {
12180 switch (Opcode) {
12181 case VCVTUDQ2PHZ128rm:
12182 case VCVTUDQ2PHZ128rmb:
12183 case VCVTUDQ2PHZ128rmbk:
12184 case VCVTUDQ2PHZ128rmbkz:
12185 case VCVTUDQ2PHZ128rmk:
12186 case VCVTUDQ2PHZ128rmkz:
12187 case VCVTUDQ2PHZ128rr:
12188 case VCVTUDQ2PHZ128rrk:
12189 case VCVTUDQ2PHZ128rrkz:
12190 case VCVTUDQ2PHZ256rm:
12191 case VCVTUDQ2PHZ256rmb:
12192 case VCVTUDQ2PHZ256rmbk:
12193 case VCVTUDQ2PHZ256rmbkz:
12194 case VCVTUDQ2PHZ256rmk:
12195 case VCVTUDQ2PHZ256rmkz:
12196 case VCVTUDQ2PHZ256rr:
12197 case VCVTUDQ2PHZ256rrk:
12198 case VCVTUDQ2PHZ256rrkz:
12199 case VCVTUDQ2PHZrm:
12200 case VCVTUDQ2PHZrmb:
12201 case VCVTUDQ2PHZrmbk:
12202 case VCVTUDQ2PHZrmbkz:
12203 case VCVTUDQ2PHZrmk:
12204 case VCVTUDQ2PHZrmkz:
12205 case VCVTUDQ2PHZrr:
12206 case VCVTUDQ2PHZrrb:
12207 case VCVTUDQ2PHZrrbk:
12208 case VCVTUDQ2PHZrrbkz:
12209 case VCVTUDQ2PHZrrk:
12210 case VCVTUDQ2PHZrrkz:
12211 return true;
12212 }
12213 return false;
12214}
12215
12216bool isPEXTRQ(unsigned Opcode) {
12217 switch (Opcode) {
12218 case PEXTRQmri:
12219 case PEXTRQrri:
12220 return true;
12221 }
12222 return false;
12223}
12224
12225bool isXCRYPTCTR(unsigned Opcode) {
12226 return Opcode == XCRYPTCTR;
12227}
12228
12229bool isVREDUCEPH(unsigned Opcode) {
12230 switch (Opcode) {
12231 case VREDUCEPHZ128rmbi:
12232 case VREDUCEPHZ128rmbik:
12233 case VREDUCEPHZ128rmbikz:
12234 case VREDUCEPHZ128rmi:
12235 case VREDUCEPHZ128rmik:
12236 case VREDUCEPHZ128rmikz:
12237 case VREDUCEPHZ128rri:
12238 case VREDUCEPHZ128rrik:
12239 case VREDUCEPHZ128rrikz:
12240 case VREDUCEPHZ256rmbi:
12241 case VREDUCEPHZ256rmbik:
12242 case VREDUCEPHZ256rmbikz:
12243 case VREDUCEPHZ256rmi:
12244 case VREDUCEPHZ256rmik:
12245 case VREDUCEPHZ256rmikz:
12246 case VREDUCEPHZ256rri:
12247 case VREDUCEPHZ256rrik:
12248 case VREDUCEPHZ256rrikz:
12249 case VREDUCEPHZrmbi:
12250 case VREDUCEPHZrmbik:
12251 case VREDUCEPHZrmbikz:
12252 case VREDUCEPHZrmi:
12253 case VREDUCEPHZrmik:
12254 case VREDUCEPHZrmikz:
12255 case VREDUCEPHZrri:
12256 case VREDUCEPHZrrib:
12257 case VREDUCEPHZrribk:
12258 case VREDUCEPHZrribkz:
12259 case VREDUCEPHZrrik:
12260 case VREDUCEPHZrrikz:
12261 return true;
12262 }
12263 return false;
12264}
12265
12266bool isUCOMISD(unsigned Opcode) {
12267 switch (Opcode) {
12268 case UCOMISDrm:
12269 case UCOMISDrr:
12270 return true;
12271 }
12272 return false;
12273}
12274
12275bool isOUTSD(unsigned Opcode) {
12276 return Opcode == OUTSL;
12277}
12278
12279bool isSUBSS(unsigned Opcode) {
12280 switch (Opcode) {
12281 case SUBSSrm_Int:
12282 case SUBSSrr_Int:
12283 return true;
12284 }
12285 return false;
12286}
12287
12288bool isVFMSUBPS(unsigned Opcode) {
12289 switch (Opcode) {
12290 case VFMSUBPS4Ymr:
12291 case VFMSUBPS4Yrm:
12292 case VFMSUBPS4Yrr:
12293 case VFMSUBPS4Yrr_REV:
12294 case VFMSUBPS4mr:
12295 case VFMSUBPS4rm:
12296 case VFMSUBPS4rr:
12297 case VFMSUBPS4rr_REV:
12298 return true;
12299 }
12300 return false;
12301}
12302
12303bool isVPBLENDW(unsigned Opcode) {
12304 switch (Opcode) {
12305 case VPBLENDWYrmi:
12306 case VPBLENDWYrri:
12307 case VPBLENDWrmi:
12308 case VPBLENDWrri:
12309 return true;
12310 }
12311 return false;
12312}
12313
12314bool isBZHI(unsigned Opcode) {
12315 switch (Opcode) {
12316 case BZHI32rm:
12317 case BZHI32rm_EVEX:
12318 case BZHI32rm_NF:
12319 case BZHI32rr:
12320 case BZHI32rr_EVEX:
12321 case BZHI32rr_NF:
12322 case BZHI64rm:
12323 case BZHI64rm_EVEX:
12324 case BZHI64rm_NF:
12325 case BZHI64rr:
12326 case BZHI64rr_EVEX:
12327 case BZHI64rr_NF:
12328 return true;
12329 }
12330 return false;
12331}
12332
12333bool isVPRORVD(unsigned Opcode) {
12334 switch (Opcode) {
12335 case VPRORVDZ128rm:
12336 case VPRORVDZ128rmb:
12337 case VPRORVDZ128rmbk:
12338 case VPRORVDZ128rmbkz:
12339 case VPRORVDZ128rmk:
12340 case VPRORVDZ128rmkz:
12341 case VPRORVDZ128rr:
12342 case VPRORVDZ128rrk:
12343 case VPRORVDZ128rrkz:
12344 case VPRORVDZ256rm:
12345 case VPRORVDZ256rmb:
12346 case VPRORVDZ256rmbk:
12347 case VPRORVDZ256rmbkz:
12348 case VPRORVDZ256rmk:
12349 case VPRORVDZ256rmkz:
12350 case VPRORVDZ256rr:
12351 case VPRORVDZ256rrk:
12352 case VPRORVDZ256rrkz:
12353 case VPRORVDZrm:
12354 case VPRORVDZrmb:
12355 case VPRORVDZrmbk:
12356 case VPRORVDZrmbkz:
12357 case VPRORVDZrmk:
12358 case VPRORVDZrmkz:
12359 case VPRORVDZrr:
12360 case VPRORVDZrrk:
12361 case VPRORVDZrrkz:
12362 return true;
12363 }
12364 return false;
12365}
12366
12367bool isRMPQUERY(unsigned Opcode) {
12368 return Opcode == RMPQUERY;
12369}
12370
12371bool isVPEXPANDB(unsigned Opcode) {
12372 switch (Opcode) {
12373 case VPEXPANDBZ128rm:
12374 case VPEXPANDBZ128rmk:
12375 case VPEXPANDBZ128rmkz:
12376 case VPEXPANDBZ128rr:
12377 case VPEXPANDBZ128rrk:
12378 case VPEXPANDBZ128rrkz:
12379 case VPEXPANDBZ256rm:
12380 case VPEXPANDBZ256rmk:
12381 case VPEXPANDBZ256rmkz:
12382 case VPEXPANDBZ256rr:
12383 case VPEXPANDBZ256rrk:
12384 case VPEXPANDBZ256rrkz:
12385 case VPEXPANDBZrm:
12386 case VPEXPANDBZrmk:
12387 case VPEXPANDBZrmkz:
12388 case VPEXPANDBZrr:
12389 case VPEXPANDBZrrk:
12390 case VPEXPANDBZrrkz:
12391 return true;
12392 }
12393 return false;
12394}
12395
12396bool isVPSCATTERDQ(unsigned Opcode) {
12397 switch (Opcode) {
12398 case VPSCATTERDQZ128mr:
12399 case VPSCATTERDQZ256mr:
12400 case VPSCATTERDQZmr:
12401 return true;
12402 }
12403 return false;
12404}
12405
12406bool isPSMASH(unsigned Opcode) {
12407 return Opcode == PSMASH;
12408}
12409
12410bool isVPSHLDQ(unsigned Opcode) {
12411 switch (Opcode) {
12412 case VPSHLDQZ128rmbi:
12413 case VPSHLDQZ128rmbik:
12414 case VPSHLDQZ128rmbikz:
12415 case VPSHLDQZ128rmi:
12416 case VPSHLDQZ128rmik:
12417 case VPSHLDQZ128rmikz:
12418 case VPSHLDQZ128rri:
12419 case VPSHLDQZ128rrik:
12420 case VPSHLDQZ128rrikz:
12421 case VPSHLDQZ256rmbi:
12422 case VPSHLDQZ256rmbik:
12423 case VPSHLDQZ256rmbikz:
12424 case VPSHLDQZ256rmi:
12425 case VPSHLDQZ256rmik:
12426 case VPSHLDQZ256rmikz:
12427 case VPSHLDQZ256rri:
12428 case VPSHLDQZ256rrik:
12429 case VPSHLDQZ256rrikz:
12430 case VPSHLDQZrmbi:
12431 case VPSHLDQZrmbik:
12432 case VPSHLDQZrmbikz:
12433 case VPSHLDQZrmi:
12434 case VPSHLDQZrmik:
12435 case VPSHLDQZrmikz:
12436 case VPSHLDQZrri:
12437 case VPSHLDQZrrik:
12438 case VPSHLDQZrrikz:
12439 return true;
12440 }
12441 return false;
12442}
12443
12444bool isVSCATTERPF1DPD(unsigned Opcode) {
12445 return Opcode == VSCATTERPF1DPDm;
12446}
12447
12448bool isMONTMUL(unsigned Opcode) {
12449 return Opcode == MONTMUL;
12450}
12451
12452bool isVCVTPH2UQQ(unsigned Opcode) {
12453 switch (Opcode) {
12454 case VCVTPH2UQQZ128rm:
12455 case VCVTPH2UQQZ128rmb:
12456 case VCVTPH2UQQZ128rmbk:
12457 case VCVTPH2UQQZ128rmbkz:
12458 case VCVTPH2UQQZ128rmk:
12459 case VCVTPH2UQQZ128rmkz:
12460 case VCVTPH2UQQZ128rr:
12461 case VCVTPH2UQQZ128rrk:
12462 case VCVTPH2UQQZ128rrkz:
12463 case VCVTPH2UQQZ256rm:
12464 case VCVTPH2UQQZ256rmb:
12465 case VCVTPH2UQQZ256rmbk:
12466 case VCVTPH2UQQZ256rmbkz:
12467 case VCVTPH2UQQZ256rmk:
12468 case VCVTPH2UQQZ256rmkz:
12469 case VCVTPH2UQQZ256rr:
12470 case VCVTPH2UQQZ256rrk:
12471 case VCVTPH2UQQZ256rrkz:
12472 case VCVTPH2UQQZrm:
12473 case VCVTPH2UQQZrmb:
12474 case VCVTPH2UQQZrmbk:
12475 case VCVTPH2UQQZrmbkz:
12476 case VCVTPH2UQQZrmk:
12477 case VCVTPH2UQQZrmkz:
12478 case VCVTPH2UQQZrr:
12479 case VCVTPH2UQQZrrb:
12480 case VCVTPH2UQQZrrbk:
12481 case VCVTPH2UQQZrrbkz:
12482 case VCVTPH2UQQZrrk:
12483 case VCVTPH2UQQZrrkz:
12484 return true;
12485 }
12486 return false;
12487}
12488
12489bool isPSLLD(unsigned Opcode) {
12490 switch (Opcode) {
12491 case MMX_PSLLDri:
12492 case MMX_PSLLDrm:
12493 case MMX_PSLLDrr:
12494 case PSLLDri:
12495 case PSLLDrm:
12496 case PSLLDrr:
12497 return true;
12498 }
12499 return false;
12500}
12501
12502bool isSAR(unsigned Opcode) {
12503 switch (Opcode) {
12504 case SAR16m1:
12505 case SAR16m1_EVEX:
12506 case SAR16m1_ND:
12507 case SAR16m1_NF:
12508 case SAR16m1_NF_ND:
12509 case SAR16mCL:
12510 case SAR16mCL_EVEX:
12511 case SAR16mCL_ND:
12512 case SAR16mCL_NF:
12513 case SAR16mCL_NF_ND:
12514 case SAR16mi:
12515 case SAR16mi_EVEX:
12516 case SAR16mi_ND:
12517 case SAR16mi_NF:
12518 case SAR16mi_NF_ND:
12519 case SAR16r1:
12520 case SAR16r1_EVEX:
12521 case SAR16r1_ND:
12522 case SAR16r1_NF:
12523 case SAR16r1_NF_ND:
12524 case SAR16rCL:
12525 case SAR16rCL_EVEX:
12526 case SAR16rCL_ND:
12527 case SAR16rCL_NF:
12528 case SAR16rCL_NF_ND:
12529 case SAR16ri:
12530 case SAR16ri_EVEX:
12531 case SAR16ri_ND:
12532 case SAR16ri_NF:
12533 case SAR16ri_NF_ND:
12534 case SAR32m1:
12535 case SAR32m1_EVEX:
12536 case SAR32m1_ND:
12537 case SAR32m1_NF:
12538 case SAR32m1_NF_ND:
12539 case SAR32mCL:
12540 case SAR32mCL_EVEX:
12541 case SAR32mCL_ND:
12542 case SAR32mCL_NF:
12543 case SAR32mCL_NF_ND:
12544 case SAR32mi:
12545 case SAR32mi_EVEX:
12546 case SAR32mi_ND:
12547 case SAR32mi_NF:
12548 case SAR32mi_NF_ND:
12549 case SAR32r1:
12550 case SAR32r1_EVEX:
12551 case SAR32r1_ND:
12552 case SAR32r1_NF:
12553 case SAR32r1_NF_ND:
12554 case SAR32rCL:
12555 case SAR32rCL_EVEX:
12556 case SAR32rCL_ND:
12557 case SAR32rCL_NF:
12558 case SAR32rCL_NF_ND:
12559 case SAR32ri:
12560 case SAR32ri_EVEX:
12561 case SAR32ri_ND:
12562 case SAR32ri_NF:
12563 case SAR32ri_NF_ND:
12564 case SAR64m1:
12565 case SAR64m1_EVEX:
12566 case SAR64m1_ND:
12567 case SAR64m1_NF:
12568 case SAR64m1_NF_ND:
12569 case SAR64mCL:
12570 case SAR64mCL_EVEX:
12571 case SAR64mCL_ND:
12572 case SAR64mCL_NF:
12573 case SAR64mCL_NF_ND:
12574 case SAR64mi:
12575 case SAR64mi_EVEX:
12576 case SAR64mi_ND:
12577 case SAR64mi_NF:
12578 case SAR64mi_NF_ND:
12579 case SAR64r1:
12580 case SAR64r1_EVEX:
12581 case SAR64r1_ND:
12582 case SAR64r1_NF:
12583 case SAR64r1_NF_ND:
12584 case SAR64rCL:
12585 case SAR64rCL_EVEX:
12586 case SAR64rCL_ND:
12587 case SAR64rCL_NF:
12588 case SAR64rCL_NF_ND:
12589 case SAR64ri:
12590 case SAR64ri_EVEX:
12591 case SAR64ri_ND:
12592 case SAR64ri_NF:
12593 case SAR64ri_NF_ND:
12594 case SAR8m1:
12595 case SAR8m1_EVEX:
12596 case SAR8m1_ND:
12597 case SAR8m1_NF:
12598 case SAR8m1_NF_ND:
12599 case SAR8mCL:
12600 case SAR8mCL_EVEX:
12601 case SAR8mCL_ND:
12602 case SAR8mCL_NF:
12603 case SAR8mCL_NF_ND:
12604 case SAR8mi:
12605 case SAR8mi_EVEX:
12606 case SAR8mi_ND:
12607 case SAR8mi_NF:
12608 case SAR8mi_NF_ND:
12609 case SAR8r1:
12610 case SAR8r1_EVEX:
12611 case SAR8r1_ND:
12612 case SAR8r1_NF:
12613 case SAR8r1_NF_ND:
12614 case SAR8rCL:
12615 case SAR8rCL_EVEX:
12616 case SAR8rCL_ND:
12617 case SAR8rCL_NF:
12618 case SAR8rCL_NF_ND:
12619 case SAR8ri:
12620 case SAR8ri_EVEX:
12621 case SAR8ri_ND:
12622 case SAR8ri_NF:
12623 case SAR8ri_NF_ND:
12624 return true;
12625 }
12626 return false;
12627}
12628
12629bool isLDTILECFG(unsigned Opcode) {
12630 switch (Opcode) {
12631 case LDTILECFG:
12632 case LDTILECFG_EVEX:
12633 return true;
12634 }
12635 return false;
12636}
12637
12638bool isPMINUB(unsigned Opcode) {
12639 switch (Opcode) {
12640 case MMX_PMINUBrm:
12641 case MMX_PMINUBrr:
12642 case PMINUBrm:
12643 case PMINUBrr:
12644 return true;
12645 }
12646 return false;
12647}
12648
12649bool isVCVTNEEBF162PS(unsigned Opcode) {
12650 switch (Opcode) {
12651 case VCVTNEEBF162PSYrm:
12652 case VCVTNEEBF162PSrm:
12653 return true;
12654 }
12655 return false;
12656}
12657
12658bool isMOVDIR64B(unsigned Opcode) {
12659 switch (Opcode) {
12660 case MOVDIR64B16:
12661 case MOVDIR64B32:
12662 case MOVDIR64B32_EVEX:
12663 case MOVDIR64B64:
12664 case MOVDIR64B64_EVEX:
12665 return true;
12666 }
12667 return false;
12668}
12669
12670bool isSTR(unsigned Opcode) {
12671 switch (Opcode) {
12672 case STR16r:
12673 case STR32r:
12674 case STR64r:
12675 case STRm:
12676 return true;
12677 }
12678 return false;
12679}
12680
12681bool isKANDNQ(unsigned Opcode) {
12682 return Opcode == KANDNQkk;
12683}
12684
12685bool isBSF(unsigned Opcode) {
12686 switch (Opcode) {
12687 case BSF16rm:
12688 case BSF16rr:
12689 case BSF32rm:
12690 case BSF32rr:
12691 case BSF64rm:
12692 case BSF64rr:
12693 return true;
12694 }
12695 return false;
12696}
12697
12698bool isVPDPBUUDS(unsigned Opcode) {
12699 switch (Opcode) {
12700 case VPDPBUUDSYrm:
12701 case VPDPBUUDSYrr:
12702 case VPDPBUUDSZ128rm:
12703 case VPDPBUUDSZ128rmb:
12704 case VPDPBUUDSZ128rmbk:
12705 case VPDPBUUDSZ128rmbkz:
12706 case VPDPBUUDSZ128rmk:
12707 case VPDPBUUDSZ128rmkz:
12708 case VPDPBUUDSZ128rr:
12709 case VPDPBUUDSZ128rrk:
12710 case VPDPBUUDSZ128rrkz:
12711 case VPDPBUUDSZ256rm:
12712 case VPDPBUUDSZ256rmb:
12713 case VPDPBUUDSZ256rmbk:
12714 case VPDPBUUDSZ256rmbkz:
12715 case VPDPBUUDSZ256rmk:
12716 case VPDPBUUDSZ256rmkz:
12717 case VPDPBUUDSZ256rr:
12718 case VPDPBUUDSZ256rrk:
12719 case VPDPBUUDSZ256rrkz:
12720 case VPDPBUUDSZrm:
12721 case VPDPBUUDSZrmb:
12722 case VPDPBUUDSZrmbk:
12723 case VPDPBUUDSZrmbkz:
12724 case VPDPBUUDSZrmk:
12725 case VPDPBUUDSZrmkz:
12726 case VPDPBUUDSZrr:
12727 case VPDPBUUDSZrrk:
12728 case VPDPBUUDSZrrkz:
12729 case VPDPBUUDSrm:
12730 case VPDPBUUDSrr:
12731 return true;
12732 }
12733 return false;
12734}
12735
12736bool isINCSSPD(unsigned Opcode) {
12737 return Opcode == INCSSPD;
12738}
12739
12740bool isSQRTPS(unsigned Opcode) {
12741 switch (Opcode) {
12742 case SQRTPSm:
12743 case SQRTPSr:
12744 return true;
12745 }
12746 return false;
12747}
12748
12749bool isCMPXCHG(unsigned Opcode) {
12750 switch (Opcode) {
12751 case CMPXCHG16rm:
12752 case CMPXCHG16rr:
12753 case CMPXCHG32rm:
12754 case CMPXCHG32rr:
12755 case CMPXCHG64rm:
12756 case CMPXCHG64rr:
12757 case CMPXCHG8rm:
12758 case CMPXCHG8rr:
12759 return true;
12760 }
12761 return false;
12762}
12763
12764bool isVPSIGNW(unsigned Opcode) {
12765 switch (Opcode) {
12766 case VPSIGNWYrm:
12767 case VPSIGNWYrr:
12768 case VPSIGNWrm:
12769 case VPSIGNWrr:
12770 return true;
12771 }
12772 return false;
12773}
12774
12775bool isVCOMISBF16(unsigned Opcode) {
12776 switch (Opcode) {
12777 case VCOMISBF16Zrm:
12778 case VCOMISBF16Zrr:
12779 return true;
12780 }
12781 return false;
12782}
12783
12784bool isLES(unsigned Opcode) {
12785 switch (Opcode) {
12786 case LES16rm:
12787 case LES32rm:
12788 return true;
12789 }
12790 return false;
12791}
12792
12793bool isCVTSS2SI(unsigned Opcode) {
12794 switch (Opcode) {
12795 case CVTSS2SI64rm_Int:
12796 case CVTSS2SI64rr_Int:
12797 case CVTSS2SIrm_Int:
12798 case CVTSS2SIrr_Int:
12799 return true;
12800 }
12801 return false;
12802}
12803
12804bool isVPMOVUSWB(unsigned Opcode) {
12805 switch (Opcode) {
12806 case VPMOVUSWBZ128mr:
12807 case VPMOVUSWBZ128mrk:
12808 case VPMOVUSWBZ128rr:
12809 case VPMOVUSWBZ128rrk:
12810 case VPMOVUSWBZ128rrkz:
12811 case VPMOVUSWBZ256mr:
12812 case VPMOVUSWBZ256mrk:
12813 case VPMOVUSWBZ256rr:
12814 case VPMOVUSWBZ256rrk:
12815 case VPMOVUSWBZ256rrkz:
12816 case VPMOVUSWBZmr:
12817 case VPMOVUSWBZmrk:
12818 case VPMOVUSWBZrr:
12819 case VPMOVUSWBZrrk:
12820 case VPMOVUSWBZrrkz:
12821 return true;
12822 }
12823 return false;
12824}
12825
12826bool isFCOMPI(unsigned Opcode) {
12827 return Opcode == COM_FIPr;
12828}
12829
12830bool isPUNPCKHWD(unsigned Opcode) {
12831 switch (Opcode) {
12832 case MMX_PUNPCKHWDrm:
12833 case MMX_PUNPCKHWDrr:
12834 case PUNPCKHWDrm:
12835 case PUNPCKHWDrr:
12836 return true;
12837 }
12838 return false;
12839}
12840
12841bool isPFACC(unsigned Opcode) {
12842 switch (Opcode) {
12843 case PFACCrm:
12844 case PFACCrr:
12845 return true;
12846 }
12847 return false;
12848}
12849
12850bool isVPTESTNMW(unsigned Opcode) {
12851 switch (Opcode) {
12852 case VPTESTNMWZ128rm:
12853 case VPTESTNMWZ128rmk:
12854 case VPTESTNMWZ128rr:
12855 case VPTESTNMWZ128rrk:
12856 case VPTESTNMWZ256rm:
12857 case VPTESTNMWZ256rmk:
12858 case VPTESTNMWZ256rr:
12859 case VPTESTNMWZ256rrk:
12860 case VPTESTNMWZrm:
12861 case VPTESTNMWZrmk:
12862 case VPTESTNMWZrr:
12863 case VPTESTNMWZrrk:
12864 return true;
12865 }
12866 return false;
12867}
12868
12869bool isVPMULDQ(unsigned Opcode) {
12870 switch (Opcode) {
12871 case VPMULDQYrm:
12872 case VPMULDQYrr:
12873 case VPMULDQZ128rm:
12874 case VPMULDQZ128rmb:
12875 case VPMULDQZ128rmbk:
12876 case VPMULDQZ128rmbkz:
12877 case VPMULDQZ128rmk:
12878 case VPMULDQZ128rmkz:
12879 case VPMULDQZ128rr:
12880 case VPMULDQZ128rrk:
12881 case VPMULDQZ128rrkz:
12882 case VPMULDQZ256rm:
12883 case VPMULDQZ256rmb:
12884 case VPMULDQZ256rmbk:
12885 case VPMULDQZ256rmbkz:
12886 case VPMULDQZ256rmk:
12887 case VPMULDQZ256rmkz:
12888 case VPMULDQZ256rr:
12889 case VPMULDQZ256rrk:
12890 case VPMULDQZ256rrkz:
12891 case VPMULDQZrm:
12892 case VPMULDQZrmb:
12893 case VPMULDQZrmbk:
12894 case VPMULDQZrmbkz:
12895 case VPMULDQZrmk:
12896 case VPMULDQZrmkz:
12897 case VPMULDQZrr:
12898 case VPMULDQZrrk:
12899 case VPMULDQZrrkz:
12900 case VPMULDQrm:
12901 case VPMULDQrr:
12902 return true;
12903 }
12904 return false;
12905}
12906
12907bool isSHRX(unsigned Opcode) {
12908 switch (Opcode) {
12909 case SHRX32rm:
12910 case SHRX32rm_EVEX:
12911 case SHRX32rr:
12912 case SHRX32rr_EVEX:
12913 case SHRX64rm:
12914 case SHRX64rm_EVEX:
12915 case SHRX64rr:
12916 case SHRX64rr_EVEX:
12917 return true;
12918 }
12919 return false;
12920}
12921
12922bool isKXORQ(unsigned Opcode) {
12923 return Opcode == KXORQkk;
12924}
12925
12926bool isVGETEXPSD(unsigned Opcode) {
12927 switch (Opcode) {
12928 case VGETEXPSDZm:
12929 case VGETEXPSDZmk:
12930 case VGETEXPSDZmkz:
12931 case VGETEXPSDZr:
12932 case VGETEXPSDZrb:
12933 case VGETEXPSDZrbk:
12934 case VGETEXPSDZrbkz:
12935 case VGETEXPSDZrk:
12936 case VGETEXPSDZrkz:
12937 return true;
12938 }
12939 return false;
12940}
12941
12942bool isV4FNMADDPS(unsigned Opcode) {
12943 switch (Opcode) {
12944 case V4FNMADDPSrm:
12945 case V4FNMADDPSrmk:
12946 case V4FNMADDPSrmkz:
12947 return true;
12948 }
12949 return false;
12950}
12951
12952bool isVFNMSUB231SD(unsigned Opcode) {
12953 switch (Opcode) {
12954 case VFNMSUB231SDZm_Int:
12955 case VFNMSUB231SDZmk_Int:
12956 case VFNMSUB231SDZmkz_Int:
12957 case VFNMSUB231SDZr_Int:
12958 case VFNMSUB231SDZrb_Int:
12959 case VFNMSUB231SDZrbk_Int:
12960 case VFNMSUB231SDZrbkz_Int:
12961 case VFNMSUB231SDZrk_Int:
12962 case VFNMSUB231SDZrkz_Int:
12963 case VFNMSUB231SDm_Int:
12964 case VFNMSUB231SDr_Int:
12965 return true;
12966 }
12967 return false;
12968}
12969
12970bool isVPSHLD(unsigned Opcode) {
12971 switch (Opcode) {
12972 case VPSHLDmr:
12973 case VPSHLDrm:
12974 case VPSHLDrr:
12975 case VPSHLDrr_REV:
12976 return true;
12977 }
12978 return false;
12979}
12980
12981bool isPAVGB(unsigned Opcode) {
12982 switch (Opcode) {
12983 case MMX_PAVGBrm:
12984 case MMX_PAVGBrr:
12985 case PAVGBrm:
12986 case PAVGBrr:
12987 return true;
12988 }
12989 return false;
12990}
12991
12992bool isPMOVZXBD(unsigned Opcode) {
12993 switch (Opcode) {
12994 case PMOVZXBDrm:
12995 case PMOVZXBDrr:
12996 return true;
12997 }
12998 return false;
12999}
13000
13001bool isKORTESTW(unsigned Opcode) {
13002 return Opcode == KORTESTWkk;
13003}
13004
13005bool isVSHUFPS(unsigned Opcode) {
13006 switch (Opcode) {
13007 case VSHUFPSYrmi:
13008 case VSHUFPSYrri:
13009 case VSHUFPSZ128rmbi:
13010 case VSHUFPSZ128rmbik:
13011 case VSHUFPSZ128rmbikz:
13012 case VSHUFPSZ128rmi:
13013 case VSHUFPSZ128rmik:
13014 case VSHUFPSZ128rmikz:
13015 case VSHUFPSZ128rri:
13016 case VSHUFPSZ128rrik:
13017 case VSHUFPSZ128rrikz:
13018 case VSHUFPSZ256rmbi:
13019 case VSHUFPSZ256rmbik:
13020 case VSHUFPSZ256rmbikz:
13021 case VSHUFPSZ256rmi:
13022 case VSHUFPSZ256rmik:
13023 case VSHUFPSZ256rmikz:
13024 case VSHUFPSZ256rri:
13025 case VSHUFPSZ256rrik:
13026 case VSHUFPSZ256rrikz:
13027 case VSHUFPSZrmbi:
13028 case VSHUFPSZrmbik:
13029 case VSHUFPSZrmbikz:
13030 case VSHUFPSZrmi:
13031 case VSHUFPSZrmik:
13032 case VSHUFPSZrmikz:
13033 case VSHUFPSZrri:
13034 case VSHUFPSZrrik:
13035 case VSHUFPSZrrikz:
13036 case VSHUFPSrmi:
13037 case VSHUFPSrri:
13038 return true;
13039 }
13040 return false;
13041}
13042
13043bool isAESENCWIDE128KL(unsigned Opcode) {
13044 return Opcode == AESENCWIDE128KL;
13045}
13046
13047bool isVPXORD(unsigned Opcode) {
13048 switch (Opcode) {
13049 case VPXORDZ128rm:
13050 case VPXORDZ128rmb:
13051 case VPXORDZ128rmbk:
13052 case VPXORDZ128rmbkz:
13053 case VPXORDZ128rmk:
13054 case VPXORDZ128rmkz:
13055 case VPXORDZ128rr:
13056 case VPXORDZ128rrk:
13057 case VPXORDZ128rrkz:
13058 case VPXORDZ256rm:
13059 case VPXORDZ256rmb:
13060 case VPXORDZ256rmbk:
13061 case VPXORDZ256rmbkz:
13062 case VPXORDZ256rmk:
13063 case VPXORDZ256rmkz:
13064 case VPXORDZ256rr:
13065 case VPXORDZ256rrk:
13066 case VPXORDZ256rrkz:
13067 case VPXORDZrm:
13068 case VPXORDZrmb:
13069 case VPXORDZrmbk:
13070 case VPXORDZrmbkz:
13071 case VPXORDZrmk:
13072 case VPXORDZrmkz:
13073 case VPXORDZrr:
13074 case VPXORDZrrk:
13075 case VPXORDZrrkz:
13076 return true;
13077 }
13078 return false;
13079}
13080
13081bool isVPSHAW(unsigned Opcode) {
13082 switch (Opcode) {
13083 case VPSHAWmr:
13084 case VPSHAWrm:
13085 case VPSHAWrr:
13086 case VPSHAWrr_REV:
13087 return true;
13088 }
13089 return false;
13090}
13091
13092bool isVFMSUB132BF16(unsigned Opcode) {
13093 switch (Opcode) {
13094 case VFMSUB132BF16Z128m:
13095 case VFMSUB132BF16Z128mb:
13096 case VFMSUB132BF16Z128mbk:
13097 case VFMSUB132BF16Z128mbkz:
13098 case VFMSUB132BF16Z128mk:
13099 case VFMSUB132BF16Z128mkz:
13100 case VFMSUB132BF16Z128r:
13101 case VFMSUB132BF16Z128rk:
13102 case VFMSUB132BF16Z128rkz:
13103 case VFMSUB132BF16Z256m:
13104 case VFMSUB132BF16Z256mb:
13105 case VFMSUB132BF16Z256mbk:
13106 case VFMSUB132BF16Z256mbkz:
13107 case VFMSUB132BF16Z256mk:
13108 case VFMSUB132BF16Z256mkz:
13109 case VFMSUB132BF16Z256r:
13110 case VFMSUB132BF16Z256rk:
13111 case VFMSUB132BF16Z256rkz:
13112 case VFMSUB132BF16Zm:
13113 case VFMSUB132BF16Zmb:
13114 case VFMSUB132BF16Zmbk:
13115 case VFMSUB132BF16Zmbkz:
13116 case VFMSUB132BF16Zmk:
13117 case VFMSUB132BF16Zmkz:
13118 case VFMSUB132BF16Zr:
13119 case VFMSUB132BF16Zrk:
13120 case VFMSUB132BF16Zrkz:
13121 return true;
13122 }
13123 return false;
13124}
13125
13126bool isVPERMT2B(unsigned Opcode) {
13127 switch (Opcode) {
13128 case VPERMT2BZ128rm:
13129 case VPERMT2BZ128rmk:
13130 case VPERMT2BZ128rmkz:
13131 case VPERMT2BZ128rr:
13132 case VPERMT2BZ128rrk:
13133 case VPERMT2BZ128rrkz:
13134 case VPERMT2BZ256rm:
13135 case VPERMT2BZ256rmk:
13136 case VPERMT2BZ256rmkz:
13137 case VPERMT2BZ256rr:
13138 case VPERMT2BZ256rrk:
13139 case VPERMT2BZ256rrkz:
13140 case VPERMT2BZrm:
13141 case VPERMT2BZrmk:
13142 case VPERMT2BZrmkz:
13143 case VPERMT2BZrr:
13144 case VPERMT2BZrrk:
13145 case VPERMT2BZrrkz:
13146 return true;
13147 }
13148 return false;
13149}
13150
13151bool isVFMADD213PD(unsigned Opcode) {
13152 switch (Opcode) {
13153 case VFMADD213PDYm:
13154 case VFMADD213PDYr:
13155 case VFMADD213PDZ128m:
13156 case VFMADD213PDZ128mb:
13157 case VFMADD213PDZ128mbk:
13158 case VFMADD213PDZ128mbkz:
13159 case VFMADD213PDZ128mk:
13160 case VFMADD213PDZ128mkz:
13161 case VFMADD213PDZ128r:
13162 case VFMADD213PDZ128rk:
13163 case VFMADD213PDZ128rkz:
13164 case VFMADD213PDZ256m:
13165 case VFMADD213PDZ256mb:
13166 case VFMADD213PDZ256mbk:
13167 case VFMADD213PDZ256mbkz:
13168 case VFMADD213PDZ256mk:
13169 case VFMADD213PDZ256mkz:
13170 case VFMADD213PDZ256r:
13171 case VFMADD213PDZ256rk:
13172 case VFMADD213PDZ256rkz:
13173 case VFMADD213PDZm:
13174 case VFMADD213PDZmb:
13175 case VFMADD213PDZmbk:
13176 case VFMADD213PDZmbkz:
13177 case VFMADD213PDZmk:
13178 case VFMADD213PDZmkz:
13179 case VFMADD213PDZr:
13180 case VFMADD213PDZrb:
13181 case VFMADD213PDZrbk:
13182 case VFMADD213PDZrbkz:
13183 case VFMADD213PDZrk:
13184 case VFMADD213PDZrkz:
13185 case VFMADD213PDm:
13186 case VFMADD213PDr:
13187 return true;
13188 }
13189 return false;
13190}
13191
13192bool isVPGATHERQD(unsigned Opcode) {
13193 switch (Opcode) {
13194 case VPGATHERQDYrm:
13195 case VPGATHERQDZ128rm:
13196 case VPGATHERQDZ256rm:
13197 case VPGATHERQDZrm:
13198 case VPGATHERQDrm:
13199 return true;
13200 }
13201 return false;
13202}
13203
13204bool isVFNMSUB213BF16(unsigned Opcode) {
13205 switch (Opcode) {
13206 case VFNMSUB213BF16Z128m:
13207 case VFNMSUB213BF16Z128mb:
13208 case VFNMSUB213BF16Z128mbk:
13209 case VFNMSUB213BF16Z128mbkz:
13210 case VFNMSUB213BF16Z128mk:
13211 case VFNMSUB213BF16Z128mkz:
13212 case VFNMSUB213BF16Z128r:
13213 case VFNMSUB213BF16Z128rk:
13214 case VFNMSUB213BF16Z128rkz:
13215 case VFNMSUB213BF16Z256m:
13216 case VFNMSUB213BF16Z256mb:
13217 case VFNMSUB213BF16Z256mbk:
13218 case VFNMSUB213BF16Z256mbkz:
13219 case VFNMSUB213BF16Z256mk:
13220 case VFNMSUB213BF16Z256mkz:
13221 case VFNMSUB213BF16Z256r:
13222 case VFNMSUB213BF16Z256rk:
13223 case VFNMSUB213BF16Z256rkz:
13224 case VFNMSUB213BF16Zm:
13225 case VFNMSUB213BF16Zmb:
13226 case VFNMSUB213BF16Zmbk:
13227 case VFNMSUB213BF16Zmbkz:
13228 case VFNMSUB213BF16Zmk:
13229 case VFNMSUB213BF16Zmkz:
13230 case VFNMSUB213BF16Zr:
13231 case VFNMSUB213BF16Zrk:
13232 case VFNMSUB213BF16Zrkz:
13233 return true;
13234 }
13235 return false;
13236}
13237
13238bool isVCVTPS2IBS(unsigned Opcode) {
13239 switch (Opcode) {
13240 case VCVTPS2IBSZ128rm:
13241 case VCVTPS2IBSZ128rmb:
13242 case VCVTPS2IBSZ128rmbk:
13243 case VCVTPS2IBSZ128rmbkz:
13244 case VCVTPS2IBSZ128rmk:
13245 case VCVTPS2IBSZ128rmkz:
13246 case VCVTPS2IBSZ128rr:
13247 case VCVTPS2IBSZ128rrk:
13248 case VCVTPS2IBSZ128rrkz:
13249 case VCVTPS2IBSZ256rm:
13250 case VCVTPS2IBSZ256rmb:
13251 case VCVTPS2IBSZ256rmbk:
13252 case VCVTPS2IBSZ256rmbkz:
13253 case VCVTPS2IBSZ256rmk:
13254 case VCVTPS2IBSZ256rmkz:
13255 case VCVTPS2IBSZ256rr:
13256 case VCVTPS2IBSZ256rrk:
13257 case VCVTPS2IBSZ256rrkz:
13258 case VCVTPS2IBSZrm:
13259 case VCVTPS2IBSZrmb:
13260 case VCVTPS2IBSZrmbk:
13261 case VCVTPS2IBSZrmbkz:
13262 case VCVTPS2IBSZrmk:
13263 case VCVTPS2IBSZrmkz:
13264 case VCVTPS2IBSZrr:
13265 case VCVTPS2IBSZrrb:
13266 case VCVTPS2IBSZrrbk:
13267 case VCVTPS2IBSZrrbkz:
13268 case VCVTPS2IBSZrrk:
13269 case VCVTPS2IBSZrrkz:
13270 return true;
13271 }
13272 return false;
13273}
13274
13275bool isVPCMPGTW(unsigned Opcode) {
13276 switch (Opcode) {
13277 case VPCMPGTWYrm:
13278 case VPCMPGTWYrr:
13279 case VPCMPGTWZ128rm:
13280 case VPCMPGTWZ128rmk:
13281 case VPCMPGTWZ128rr:
13282 case VPCMPGTWZ128rrk:
13283 case VPCMPGTWZ256rm:
13284 case VPCMPGTWZ256rmk:
13285 case VPCMPGTWZ256rr:
13286 case VPCMPGTWZ256rrk:
13287 case VPCMPGTWZrm:
13288 case VPCMPGTWZrmk:
13289 case VPCMPGTWZrr:
13290 case VPCMPGTWZrrk:
13291 case VPCMPGTWrm:
13292 case VPCMPGTWrr:
13293 return true;
13294 }
13295 return false;
13296}
13297
13298bool isVMOVRSB(unsigned Opcode) {
13299 switch (Opcode) {
13300 case VMOVRSBZ128m:
13301 case VMOVRSBZ128mk:
13302 case VMOVRSBZ128mkz:
13303 case VMOVRSBZ256m:
13304 case VMOVRSBZ256mk:
13305 case VMOVRSBZ256mkz:
13306 case VMOVRSBZm:
13307 case VMOVRSBZmk:
13308 case VMOVRSBZmkz:
13309 return true;
13310 }
13311 return false;
13312}
13313
13314bool isVGETMANTSH(unsigned Opcode) {
13315 switch (Opcode) {
13316 case VGETMANTSHZrmi:
13317 case VGETMANTSHZrmik:
13318 case VGETMANTSHZrmikz:
13319 case VGETMANTSHZrri:
13320 case VGETMANTSHZrrib:
13321 case VGETMANTSHZrribk:
13322 case VGETMANTSHZrribkz:
13323 case VGETMANTSHZrrik:
13324 case VGETMANTSHZrrikz:
13325 return true;
13326 }
13327 return false;
13328}
13329
13330bool isVANDPS(unsigned Opcode) {
13331 switch (Opcode) {
13332 case VANDPSYrm:
13333 case VANDPSYrr:
13334 case VANDPSZ128rm:
13335 case VANDPSZ128rmb:
13336 case VANDPSZ128rmbk:
13337 case VANDPSZ128rmbkz:
13338 case VANDPSZ128rmk:
13339 case VANDPSZ128rmkz:
13340 case VANDPSZ128rr:
13341 case VANDPSZ128rrk:
13342 case VANDPSZ128rrkz:
13343 case VANDPSZ256rm:
13344 case VANDPSZ256rmb:
13345 case VANDPSZ256rmbk:
13346 case VANDPSZ256rmbkz:
13347 case VANDPSZ256rmk:
13348 case VANDPSZ256rmkz:
13349 case VANDPSZ256rr:
13350 case VANDPSZ256rrk:
13351 case VANDPSZ256rrkz:
13352 case VANDPSZrm:
13353 case VANDPSZrmb:
13354 case VANDPSZrmbk:
13355 case VANDPSZrmbkz:
13356 case VANDPSZrmk:
13357 case VANDPSZrmkz:
13358 case VANDPSZrr:
13359 case VANDPSZrrk:
13360 case VANDPSZrrkz:
13361 case VANDPSrm:
13362 case VANDPSrr:
13363 return true;
13364 }
13365 return false;
13366}
13367
13368bool isVDIVPS(unsigned Opcode) {
13369 switch (Opcode) {
13370 case VDIVPSYrm:
13371 case VDIVPSYrr:
13372 case VDIVPSZ128rm:
13373 case VDIVPSZ128rmb:
13374 case VDIVPSZ128rmbk:
13375 case VDIVPSZ128rmbkz:
13376 case VDIVPSZ128rmk:
13377 case VDIVPSZ128rmkz:
13378 case VDIVPSZ128rr:
13379 case VDIVPSZ128rrk:
13380 case VDIVPSZ128rrkz:
13381 case VDIVPSZ256rm:
13382 case VDIVPSZ256rmb:
13383 case VDIVPSZ256rmbk:
13384 case VDIVPSZ256rmbkz:
13385 case VDIVPSZ256rmk:
13386 case VDIVPSZ256rmkz:
13387 case VDIVPSZ256rr:
13388 case VDIVPSZ256rrk:
13389 case VDIVPSZ256rrkz:
13390 case VDIVPSZrm:
13391 case VDIVPSZrmb:
13392 case VDIVPSZrmbk:
13393 case VDIVPSZrmbkz:
13394 case VDIVPSZrmk:
13395 case VDIVPSZrmkz:
13396 case VDIVPSZrr:
13397 case VDIVPSZrrb:
13398 case VDIVPSZrrbk:
13399 case VDIVPSZrrbkz:
13400 case VDIVPSZrrk:
13401 case VDIVPSZrrkz:
13402 case VDIVPSrm:
13403 case VDIVPSrr:
13404 return true;
13405 }
13406 return false;
13407}
13408
13409bool isVANDNPS(unsigned Opcode) {
13410 switch (Opcode) {
13411 case VANDNPSYrm:
13412 case VANDNPSYrr:
13413 case VANDNPSZ128rm:
13414 case VANDNPSZ128rmb:
13415 case VANDNPSZ128rmbk:
13416 case VANDNPSZ128rmbkz:
13417 case VANDNPSZ128rmk:
13418 case VANDNPSZ128rmkz:
13419 case VANDNPSZ128rr:
13420 case VANDNPSZ128rrk:
13421 case VANDNPSZ128rrkz:
13422 case VANDNPSZ256rm:
13423 case VANDNPSZ256rmb:
13424 case VANDNPSZ256rmbk:
13425 case VANDNPSZ256rmbkz:
13426 case VANDNPSZ256rmk:
13427 case VANDNPSZ256rmkz:
13428 case VANDNPSZ256rr:
13429 case VANDNPSZ256rrk:
13430 case VANDNPSZ256rrkz:
13431 case VANDNPSZrm:
13432 case VANDNPSZrmb:
13433 case VANDNPSZrmbk:
13434 case VANDNPSZrmbkz:
13435 case VANDNPSZrmk:
13436 case VANDNPSZrmkz:
13437 case VANDNPSZrr:
13438 case VANDNPSZrrk:
13439 case VANDNPSZrrkz:
13440 case VANDNPSrm:
13441 case VANDNPSrr:
13442 return true;
13443 }
13444 return false;
13445}
13446
13447bool isVPBROADCASTW(unsigned Opcode) {
13448 switch (Opcode) {
13449 case VPBROADCASTWYrm:
13450 case VPBROADCASTWYrr:
13451 case VPBROADCASTWZ128rm:
13452 case VPBROADCASTWZ128rmk:
13453 case VPBROADCASTWZ128rmkz:
13454 case VPBROADCASTWZ128rr:
13455 case VPBROADCASTWZ128rrk:
13456 case VPBROADCASTWZ128rrkz:
13457 case VPBROADCASTWZ256rm:
13458 case VPBROADCASTWZ256rmk:
13459 case VPBROADCASTWZ256rmkz:
13460 case VPBROADCASTWZ256rr:
13461 case VPBROADCASTWZ256rrk:
13462 case VPBROADCASTWZ256rrkz:
13463 case VPBROADCASTWZrm:
13464 case VPBROADCASTWZrmk:
13465 case VPBROADCASTWZrmkz:
13466 case VPBROADCASTWZrr:
13467 case VPBROADCASTWZrrk:
13468 case VPBROADCASTWZrrkz:
13469 case VPBROADCASTWrZ128rr:
13470 case VPBROADCASTWrZ128rrk:
13471 case VPBROADCASTWrZ128rrkz:
13472 case VPBROADCASTWrZ256rr:
13473 case VPBROADCASTWrZ256rrk:
13474 case VPBROADCASTWrZ256rrkz:
13475 case VPBROADCASTWrZrr:
13476 case VPBROADCASTWrZrrk:
13477 case VPBROADCASTWrZrrkz:
13478 case VPBROADCASTWrm:
13479 case VPBROADCASTWrr:
13480 return true;
13481 }
13482 return false;
13483}
13484
13485bool isFLDL2T(unsigned Opcode) {
13486 return Opcode == FLDL2T;
13487}
13488
13489bool isVPERMB(unsigned Opcode) {
13490 switch (Opcode) {
13491 case VPERMBZ128rm:
13492 case VPERMBZ128rmk:
13493 case VPERMBZ128rmkz:
13494 case VPERMBZ128rr:
13495 case VPERMBZ128rrk:
13496 case VPERMBZ128rrkz:
13497 case VPERMBZ256rm:
13498 case VPERMBZ256rmk:
13499 case VPERMBZ256rmkz:
13500 case VPERMBZ256rr:
13501 case VPERMBZ256rrk:
13502 case VPERMBZ256rrkz:
13503 case VPERMBZrm:
13504 case VPERMBZrmk:
13505 case VPERMBZrmkz:
13506 case VPERMBZrr:
13507 case VPERMBZrrk:
13508 case VPERMBZrrkz:
13509 return true;
13510 }
13511 return false;
13512}
13513
13514bool isFCMOVNBE(unsigned Opcode) {
13515 return Opcode == CMOVNBE_F;
13516}
13517
13518bool isVCVTTPH2W(unsigned Opcode) {
13519 switch (Opcode) {
13520 case VCVTTPH2WZ128rm:
13521 case VCVTTPH2WZ128rmb:
13522 case VCVTTPH2WZ128rmbk:
13523 case VCVTTPH2WZ128rmbkz:
13524 case VCVTTPH2WZ128rmk:
13525 case VCVTTPH2WZ128rmkz:
13526 case VCVTTPH2WZ128rr:
13527 case VCVTTPH2WZ128rrk:
13528 case VCVTTPH2WZ128rrkz:
13529 case VCVTTPH2WZ256rm:
13530 case VCVTTPH2WZ256rmb:
13531 case VCVTTPH2WZ256rmbk:
13532 case VCVTTPH2WZ256rmbkz:
13533 case VCVTTPH2WZ256rmk:
13534 case VCVTTPH2WZ256rmkz:
13535 case VCVTTPH2WZ256rr:
13536 case VCVTTPH2WZ256rrk:
13537 case VCVTTPH2WZ256rrkz:
13538 case VCVTTPH2WZrm:
13539 case VCVTTPH2WZrmb:
13540 case VCVTTPH2WZrmbk:
13541 case VCVTTPH2WZrmbkz:
13542 case VCVTTPH2WZrmk:
13543 case VCVTTPH2WZrmkz:
13544 case VCVTTPH2WZrr:
13545 case VCVTTPH2WZrrb:
13546 case VCVTTPH2WZrrbk:
13547 case VCVTTPH2WZrrbkz:
13548 case VCVTTPH2WZrrk:
13549 case VCVTTPH2WZrrkz:
13550 return true;
13551 }
13552 return false;
13553}
13554
13555bool isPMOVZXBQ(unsigned Opcode) {
13556 switch (Opcode) {
13557 case PMOVZXBQrm:
13558 case PMOVZXBQrr:
13559 return true;
13560 }
13561 return false;
13562}
13563
13564bool isPF2ID(unsigned Opcode) {
13565 switch (Opcode) {
13566 case PF2IDrm:
13567 case PF2IDrr:
13568 return true;
13569 }
13570 return false;
13571}
13572
13573bool isVFNMADD132PD(unsigned Opcode) {
13574 switch (Opcode) {
13575 case VFNMADD132PDYm:
13576 case VFNMADD132PDYr:
13577 case VFNMADD132PDZ128m:
13578 case VFNMADD132PDZ128mb:
13579 case VFNMADD132PDZ128mbk:
13580 case VFNMADD132PDZ128mbkz:
13581 case VFNMADD132PDZ128mk:
13582 case VFNMADD132PDZ128mkz:
13583 case VFNMADD132PDZ128r:
13584 case VFNMADD132PDZ128rk:
13585 case VFNMADD132PDZ128rkz:
13586 case VFNMADD132PDZ256m:
13587 case VFNMADD132PDZ256mb:
13588 case VFNMADD132PDZ256mbk:
13589 case VFNMADD132PDZ256mbkz:
13590 case VFNMADD132PDZ256mk:
13591 case VFNMADD132PDZ256mkz:
13592 case VFNMADD132PDZ256r:
13593 case VFNMADD132PDZ256rk:
13594 case VFNMADD132PDZ256rkz:
13595 case VFNMADD132PDZm:
13596 case VFNMADD132PDZmb:
13597 case VFNMADD132PDZmbk:
13598 case VFNMADD132PDZmbkz:
13599 case VFNMADD132PDZmk:
13600 case VFNMADD132PDZmkz:
13601 case VFNMADD132PDZr:
13602 case VFNMADD132PDZrb:
13603 case VFNMADD132PDZrbk:
13604 case VFNMADD132PDZrbkz:
13605 case VFNMADD132PDZrk:
13606 case VFNMADD132PDZrkz:
13607 case VFNMADD132PDm:
13608 case VFNMADD132PDr:
13609 return true;
13610 }
13611 return false;
13612}
13613
13614bool isPMULHRSW(unsigned Opcode) {
13615 switch (Opcode) {
13616 case MMX_PMULHRSWrm:
13617 case MMX_PMULHRSWrr:
13618 case PMULHRSWrm:
13619 case PMULHRSWrr:
13620 return true;
13621 }
13622 return false;
13623}
13624
13625bool isKADDD(unsigned Opcode) {
13626 return Opcode == KADDDkk;
13627}
13628
13629bool isVFNMSUB132SH(unsigned Opcode) {
13630 switch (Opcode) {
13631 case VFNMSUB132SHZm_Int:
13632 case VFNMSUB132SHZmk_Int:
13633 case VFNMSUB132SHZmkz_Int:
13634 case VFNMSUB132SHZr_Int:
13635 case VFNMSUB132SHZrb_Int:
13636 case VFNMSUB132SHZrbk_Int:
13637 case VFNMSUB132SHZrbkz_Int:
13638 case VFNMSUB132SHZrk_Int:
13639 case VFNMSUB132SHZrkz_Int:
13640 return true;
13641 }
13642 return false;
13643}
13644
13645bool isUIRET(unsigned Opcode) {
13646 return Opcode == UIRET;
13647}
13648
13649bool isBSR(unsigned Opcode) {
13650 switch (Opcode) {
13651 case BSR16rm:
13652 case BSR16rr:
13653 case BSR32rm:
13654 case BSR32rr:
13655 case BSR64rm:
13656 case BSR64rr:
13657 return true;
13658 }
13659 return false;
13660}
13661
13662bool isPCMPEQQ(unsigned Opcode) {
13663 switch (Opcode) {
13664 case PCMPEQQrm:
13665 case PCMPEQQrr:
13666 return true;
13667 }
13668 return false;
13669}
13670
13671bool isCDQ(unsigned Opcode) {
13672 return Opcode == CDQ;
13673}
13674
13675bool isPMAXSW(unsigned Opcode) {
13676 switch (Opcode) {
13677 case MMX_PMAXSWrm:
13678 case MMX_PMAXSWrr:
13679 case PMAXSWrm:
13680 case PMAXSWrr:
13681 return true;
13682 }
13683 return false;
13684}
13685
13686bool isSIDTD(unsigned Opcode) {
13687 return Opcode == SIDT32m;
13688}
13689
13690bool isVCVTPS2PHX(unsigned Opcode) {
13691 switch (Opcode) {
13692 case VCVTPS2PHXZ128rm:
13693 case VCVTPS2PHXZ128rmb:
13694 case VCVTPS2PHXZ128rmbk:
13695 case VCVTPS2PHXZ128rmbkz:
13696 case VCVTPS2PHXZ128rmk:
13697 case VCVTPS2PHXZ128rmkz:
13698 case VCVTPS2PHXZ128rr:
13699 case VCVTPS2PHXZ128rrk:
13700 case VCVTPS2PHXZ128rrkz:
13701 case VCVTPS2PHXZ256rm:
13702 case VCVTPS2PHXZ256rmb:
13703 case VCVTPS2PHXZ256rmbk:
13704 case VCVTPS2PHXZ256rmbkz:
13705 case VCVTPS2PHXZ256rmk:
13706 case VCVTPS2PHXZ256rmkz:
13707 case VCVTPS2PHXZ256rr:
13708 case VCVTPS2PHXZ256rrk:
13709 case VCVTPS2PHXZ256rrkz:
13710 case VCVTPS2PHXZrm:
13711 case VCVTPS2PHXZrmb:
13712 case VCVTPS2PHXZrmbk:
13713 case VCVTPS2PHXZrmbkz:
13714 case VCVTPS2PHXZrmk:
13715 case VCVTPS2PHXZrmkz:
13716 case VCVTPS2PHXZrr:
13717 case VCVTPS2PHXZrrb:
13718 case VCVTPS2PHXZrrbk:
13719 case VCVTPS2PHXZrrbkz:
13720 case VCVTPS2PHXZrrk:
13721 case VCVTPS2PHXZrrkz:
13722 return true;
13723 }
13724 return false;
13725}
13726
13727bool isVPSLLVQ(unsigned Opcode) {
13728 switch (Opcode) {
13729 case VPSLLVQYrm:
13730 case VPSLLVQYrr:
13731 case VPSLLVQZ128rm:
13732 case VPSLLVQZ128rmb:
13733 case VPSLLVQZ128rmbk:
13734 case VPSLLVQZ128rmbkz:
13735 case VPSLLVQZ128rmk:
13736 case VPSLLVQZ128rmkz:
13737 case VPSLLVQZ128rr:
13738 case VPSLLVQZ128rrk:
13739 case VPSLLVQZ128rrkz:
13740 case VPSLLVQZ256rm:
13741 case VPSLLVQZ256rmb:
13742 case VPSLLVQZ256rmbk:
13743 case VPSLLVQZ256rmbkz:
13744 case VPSLLVQZ256rmk:
13745 case VPSLLVQZ256rmkz:
13746 case VPSLLVQZ256rr:
13747 case VPSLLVQZ256rrk:
13748 case VPSLLVQZ256rrkz:
13749 case VPSLLVQZrm:
13750 case VPSLLVQZrmb:
13751 case VPSLLVQZrmbk:
13752 case VPSLLVQZrmbkz:
13753 case VPSLLVQZrmk:
13754 case VPSLLVQZrmkz:
13755 case VPSLLVQZrr:
13756 case VPSLLVQZrrk:
13757 case VPSLLVQZrrkz:
13758 case VPSLLVQrm:
13759 case VPSLLVQrr:
13760 return true;
13761 }
13762 return false;
13763}
13764
13765bool isMOVQ(unsigned Opcode) {
13766 switch (Opcode) {
13767 case MMX_MOVD64from64mr:
13768 case MMX_MOVD64from64rr:
13769 case MMX_MOVD64to64rm:
13770 case MMX_MOVD64to64rr:
13771 case MMX_MOVQ64mr:
13772 case MMX_MOVQ64rm:
13773 case MMX_MOVQ64rr:
13774 case MMX_MOVQ64rr_REV:
13775 case MOV64toPQIrm:
13776 case MOV64toPQIrr:
13777 case MOVPQI2QImr:
13778 case MOVPQI2QIrr:
13779 case MOVPQIto64mr:
13780 case MOVPQIto64rr:
13781 case MOVQI2PQIrm:
13782 case MOVZPQILo2PQIrr:
13783 return true;
13784 }
13785 return false;
13786}
13787
13788bool isVCMPBF16(unsigned Opcode) {
13789 switch (Opcode) {
13790 case VCMPBF16Z128rmbi:
13791 case VCMPBF16Z128rmbik:
13792 case VCMPBF16Z128rmi:
13793 case VCMPBF16Z128rmik:
13794 case VCMPBF16Z128rri:
13795 case VCMPBF16Z128rrik:
13796 case VCMPBF16Z256rmbi:
13797 case VCMPBF16Z256rmbik:
13798 case VCMPBF16Z256rmi:
13799 case VCMPBF16Z256rmik:
13800 case VCMPBF16Z256rri:
13801 case VCMPBF16Z256rrik:
13802 case VCMPBF16Zrmbi:
13803 case VCMPBF16Zrmbik:
13804 case VCMPBF16Zrmi:
13805 case VCMPBF16Zrmik:
13806 case VCMPBF16Zrri:
13807 case VCMPBF16Zrrik:
13808 return true;
13809 }
13810 return false;
13811}
13812
13813bool isPREFETCH(unsigned Opcode) {
13814 return Opcode == PREFETCH;
13815}
13816
13817bool isCLRSSBSY(unsigned Opcode) {
13818 return Opcode == CLRSSBSY;
13819}
13820
13821bool isTCVTROWPS2PHL(unsigned Opcode) {
13822 switch (Opcode) {
13823 case TCVTROWPS2PHLrte:
13824 case TCVTROWPS2PHLrti:
13825 return true;
13826 }
13827 return false;
13828}
13829
13830bool isPSHUFW(unsigned Opcode) {
13831 switch (Opcode) {
13832 case MMX_PSHUFWmi:
13833 case MMX_PSHUFWri:
13834 return true;
13835 }
13836 return false;
13837}
13838
13839bool isVPDPWSUDS(unsigned Opcode) {
13840 switch (Opcode) {
13841 case VPDPWSUDSYrm:
13842 case VPDPWSUDSYrr:
13843 case VPDPWSUDSZ128rm:
13844 case VPDPWSUDSZ128rmb:
13845 case VPDPWSUDSZ128rmbk:
13846 case VPDPWSUDSZ128rmbkz:
13847 case VPDPWSUDSZ128rmk:
13848 case VPDPWSUDSZ128rmkz:
13849 case VPDPWSUDSZ128rr:
13850 case VPDPWSUDSZ128rrk:
13851 case VPDPWSUDSZ128rrkz:
13852 case VPDPWSUDSZ256rm:
13853 case VPDPWSUDSZ256rmb:
13854 case VPDPWSUDSZ256rmbk:
13855 case VPDPWSUDSZ256rmbkz:
13856 case VPDPWSUDSZ256rmk:
13857 case VPDPWSUDSZ256rmkz:
13858 case VPDPWSUDSZ256rr:
13859 case VPDPWSUDSZ256rrk:
13860 case VPDPWSUDSZ256rrkz:
13861 case VPDPWSUDSZrm:
13862 case VPDPWSUDSZrmb:
13863 case VPDPWSUDSZrmbk:
13864 case VPDPWSUDSZrmbkz:
13865 case VPDPWSUDSZrmk:
13866 case VPDPWSUDSZrmkz:
13867 case VPDPWSUDSZrr:
13868 case VPDPWSUDSZrrk:
13869 case VPDPWSUDSZrrkz:
13870 case VPDPWSUDSrm:
13871 case VPDPWSUDSrr:
13872 return true;
13873 }
13874 return false;
13875}
13876
13877bool isVPMOVSXBQ(unsigned Opcode) {
13878 switch (Opcode) {
13879 case VPMOVSXBQYrm:
13880 case VPMOVSXBQYrr:
13881 case VPMOVSXBQZ128rm:
13882 case VPMOVSXBQZ128rmk:
13883 case VPMOVSXBQZ128rmkz:
13884 case VPMOVSXBQZ128rr:
13885 case VPMOVSXBQZ128rrk:
13886 case VPMOVSXBQZ128rrkz:
13887 case VPMOVSXBQZ256rm:
13888 case VPMOVSXBQZ256rmk:
13889 case VPMOVSXBQZ256rmkz:
13890 case VPMOVSXBQZ256rr:
13891 case VPMOVSXBQZ256rrk:
13892 case VPMOVSXBQZ256rrkz:
13893 case VPMOVSXBQZrm:
13894 case VPMOVSXBQZrmk:
13895 case VPMOVSXBQZrmkz:
13896 case VPMOVSXBQZrr:
13897 case VPMOVSXBQZrrk:
13898 case VPMOVSXBQZrrkz:
13899 case VPMOVSXBQrm:
13900 case VPMOVSXBQrr:
13901 return true;
13902 }
13903 return false;
13904}
13905
13906bool isFICOMP(unsigned Opcode) {
13907 switch (Opcode) {
13908 case FICOMP16m:
13909 case FICOMP32m:
13910 return true;
13911 }
13912 return false;
13913}
13914
13915bool isVLDMXCSR(unsigned Opcode) {
13916 return Opcode == VLDMXCSR;
13917}
13918
13919bool isVPSUBUSW(unsigned Opcode) {
13920 switch (Opcode) {
13921 case VPSUBUSWYrm:
13922 case VPSUBUSWYrr:
13923 case VPSUBUSWZ128rm:
13924 case VPSUBUSWZ128rmk:
13925 case VPSUBUSWZ128rmkz:
13926 case VPSUBUSWZ128rr:
13927 case VPSUBUSWZ128rrk:
13928 case VPSUBUSWZ128rrkz:
13929 case VPSUBUSWZ256rm:
13930 case VPSUBUSWZ256rmk:
13931 case VPSUBUSWZ256rmkz:
13932 case VPSUBUSWZ256rr:
13933 case VPSUBUSWZ256rrk:
13934 case VPSUBUSWZ256rrkz:
13935 case VPSUBUSWZrm:
13936 case VPSUBUSWZrmk:
13937 case VPSUBUSWZrmkz:
13938 case VPSUBUSWZrr:
13939 case VPSUBUSWZrrk:
13940 case VPSUBUSWZrrkz:
13941 case VPSUBUSWrm:
13942 case VPSUBUSWrr:
13943 return true;
13944 }
13945 return false;
13946}
13947
13948bool isVFNMSUB132SS(unsigned Opcode) {
13949 switch (Opcode) {
13950 case VFNMSUB132SSZm_Int:
13951 case VFNMSUB132SSZmk_Int:
13952 case VFNMSUB132SSZmkz_Int:
13953 case VFNMSUB132SSZr_Int:
13954 case VFNMSUB132SSZrb_Int:
13955 case VFNMSUB132SSZrbk_Int:
13956 case VFNMSUB132SSZrbkz_Int:
13957 case VFNMSUB132SSZrk_Int:
13958 case VFNMSUB132SSZrkz_Int:
13959 case VFNMSUB132SSm_Int:
13960 case VFNMSUB132SSr_Int:
13961 return true;
13962 }
13963 return false;
13964}
13965
13966bool isRETF(unsigned Opcode) {
13967 switch (Opcode) {
13968 case LRET16:
13969 case LRET32:
13970 case LRETI16:
13971 case LRETI32:
13972 return true;
13973 }
13974 return false;
13975}
13976
13977bool isKMOVQ(unsigned Opcode) {
13978 switch (Opcode) {
13979 case KMOVQkk:
13980 case KMOVQkk_EVEX:
13981 case KMOVQkm:
13982 case KMOVQkm_EVEX:
13983 case KMOVQkr:
13984 case KMOVQkr_EVEX:
13985 case KMOVQmk:
13986 case KMOVQmk_EVEX:
13987 case KMOVQrk:
13988 case KMOVQrk_EVEX:
13989 return true;
13990 }
13991 return false;
13992}
13993
13994bool isVPADDUSW(unsigned Opcode) {
13995 switch (Opcode) {
13996 case VPADDUSWYrm:
13997 case VPADDUSWYrr:
13998 case VPADDUSWZ128rm:
13999 case VPADDUSWZ128rmk:
14000 case VPADDUSWZ128rmkz:
14001 case VPADDUSWZ128rr:
14002 case VPADDUSWZ128rrk:
14003 case VPADDUSWZ128rrkz:
14004 case VPADDUSWZ256rm:
14005 case VPADDUSWZ256rmk:
14006 case VPADDUSWZ256rmkz:
14007 case VPADDUSWZ256rr:
14008 case VPADDUSWZ256rrk:
14009 case VPADDUSWZ256rrkz:
14010 case VPADDUSWZrm:
14011 case VPADDUSWZrmk:
14012 case VPADDUSWZrmkz:
14013 case VPADDUSWZrr:
14014 case VPADDUSWZrrk:
14015 case VPADDUSWZrrkz:
14016 case VPADDUSWrm:
14017 case VPADDUSWrr:
14018 return true;
14019 }
14020 return false;
14021}
14022
14023bool isPACKSSDW(unsigned Opcode) {
14024 switch (Opcode) {
14025 case MMX_PACKSSDWrm:
14026 case MMX_PACKSSDWrr:
14027 case PACKSSDWrm:
14028 case PACKSSDWrr:
14029 return true;
14030 }
14031 return false;
14032}
14033
14034bool isUMONITOR(unsigned Opcode) {
14035 switch (Opcode) {
14036 case UMONITOR16:
14037 case UMONITOR32:
14038 case UMONITOR64:
14039 return true;
14040 }
14041 return false;
14042}
14043
14044bool isENQCMDS(unsigned Opcode) {
14045 switch (Opcode) {
14046 case ENQCMDS16:
14047 case ENQCMDS32:
14048 case ENQCMDS32_EVEX:
14049 case ENQCMDS64:
14050 case ENQCMDS64_EVEX:
14051 return true;
14052 }
14053 return false;
14054}
14055
14056bool isVCOMXSD(unsigned Opcode) {
14057 switch (Opcode) {
14058 case VCOMXSDZrm_Int:
14059 case VCOMXSDZrr_Int:
14060 case VCOMXSDZrrb_Int:
14061 return true;
14062 }
14063 return false;
14064}
14065
14066bool isVPMAXSQ(unsigned Opcode) {
14067 switch (Opcode) {
14068 case VPMAXSQZ128rm:
14069 case VPMAXSQZ128rmb:
14070 case VPMAXSQZ128rmbk:
14071 case VPMAXSQZ128rmbkz:
14072 case VPMAXSQZ128rmk:
14073 case VPMAXSQZ128rmkz:
14074 case VPMAXSQZ128rr:
14075 case VPMAXSQZ128rrk:
14076 case VPMAXSQZ128rrkz:
14077 case VPMAXSQZ256rm:
14078 case VPMAXSQZ256rmb:
14079 case VPMAXSQZ256rmbk:
14080 case VPMAXSQZ256rmbkz:
14081 case VPMAXSQZ256rmk:
14082 case VPMAXSQZ256rmkz:
14083 case VPMAXSQZ256rr:
14084 case VPMAXSQZ256rrk:
14085 case VPMAXSQZ256rrkz:
14086 case VPMAXSQZrm:
14087 case VPMAXSQZrmb:
14088 case VPMAXSQZrmbk:
14089 case VPMAXSQZrmbkz:
14090 case VPMAXSQZrmk:
14091 case VPMAXSQZrmkz:
14092 case VPMAXSQZrr:
14093 case VPMAXSQZrrk:
14094 case VPMAXSQZrrkz:
14095 return true;
14096 }
14097 return false;
14098}
14099
14100bool isVFMSUB213BF16(unsigned Opcode) {
14101 switch (Opcode) {
14102 case VFMSUB213BF16Z128m:
14103 case VFMSUB213BF16Z128mb:
14104 case VFMSUB213BF16Z128mbk:
14105 case VFMSUB213BF16Z128mbkz:
14106 case VFMSUB213BF16Z128mk:
14107 case VFMSUB213BF16Z128mkz:
14108 case VFMSUB213BF16Z128r:
14109 case VFMSUB213BF16Z128rk:
14110 case VFMSUB213BF16Z128rkz:
14111 case VFMSUB213BF16Z256m:
14112 case VFMSUB213BF16Z256mb:
14113 case VFMSUB213BF16Z256mbk:
14114 case VFMSUB213BF16Z256mbkz:
14115 case VFMSUB213BF16Z256mk:
14116 case VFMSUB213BF16Z256mkz:
14117 case VFMSUB213BF16Z256r:
14118 case VFMSUB213BF16Z256rk:
14119 case VFMSUB213BF16Z256rkz:
14120 case VFMSUB213BF16Zm:
14121 case VFMSUB213BF16Zmb:
14122 case VFMSUB213BF16Zmbk:
14123 case VFMSUB213BF16Zmbkz:
14124 case VFMSUB213BF16Zmk:
14125 case VFMSUB213BF16Zmkz:
14126 case VFMSUB213BF16Zr:
14127 case VFMSUB213BF16Zrk:
14128 case VFMSUB213BF16Zrkz:
14129 return true;
14130 }
14131 return false;
14132}
14133
14134bool isVPERMT2Q(unsigned Opcode) {
14135 switch (Opcode) {
14136 case VPERMT2QZ128rm:
14137 case VPERMT2QZ128rmb:
14138 case VPERMT2QZ128rmbk:
14139 case VPERMT2QZ128rmbkz:
14140 case VPERMT2QZ128rmk:
14141 case VPERMT2QZ128rmkz:
14142 case VPERMT2QZ128rr:
14143 case VPERMT2QZ128rrk:
14144 case VPERMT2QZ128rrkz:
14145 case VPERMT2QZ256rm:
14146 case VPERMT2QZ256rmb:
14147 case VPERMT2QZ256rmbk:
14148 case VPERMT2QZ256rmbkz:
14149 case VPERMT2QZ256rmk:
14150 case VPERMT2QZ256rmkz:
14151 case VPERMT2QZ256rr:
14152 case VPERMT2QZ256rrk:
14153 case VPERMT2QZ256rrkz:
14154 case VPERMT2QZrm:
14155 case VPERMT2QZrmb:
14156 case VPERMT2QZrmbk:
14157 case VPERMT2QZrmbkz:
14158 case VPERMT2QZrmk:
14159 case VPERMT2QZrmkz:
14160 case VPERMT2QZrr:
14161 case VPERMT2QZrrk:
14162 case VPERMT2QZrrkz:
14163 return true;
14164 }
14165 return false;
14166}
14167
14168bool isFDECSTP(unsigned Opcode) {
14169 return Opcode == FDECSTP;
14170}
14171
14172bool isVPTESTMQ(unsigned Opcode) {
14173 switch (Opcode) {
14174 case VPTESTMQZ128rm:
14175 case VPTESTMQZ128rmb:
14176 case VPTESTMQZ128rmbk:
14177 case VPTESTMQZ128rmk:
14178 case VPTESTMQZ128rr:
14179 case VPTESTMQZ128rrk:
14180 case VPTESTMQZ256rm:
14181 case VPTESTMQZ256rmb:
14182 case VPTESTMQZ256rmbk:
14183 case VPTESTMQZ256rmk:
14184 case VPTESTMQZ256rr:
14185 case VPTESTMQZ256rrk:
14186 case VPTESTMQZrm:
14187 case VPTESTMQZrmb:
14188 case VPTESTMQZrmbk:
14189 case VPTESTMQZrmk:
14190 case VPTESTMQZrr:
14191 case VPTESTMQZrrk:
14192 return true;
14193 }
14194 return false;
14195}
14196
14197bool isVRCP14PD(unsigned Opcode) {
14198 switch (Opcode) {
14199 case VRCP14PDZ128m:
14200 case VRCP14PDZ128mb:
14201 case VRCP14PDZ128mbk:
14202 case VRCP14PDZ128mbkz:
14203 case VRCP14PDZ128mk:
14204 case VRCP14PDZ128mkz:
14205 case VRCP14PDZ128r:
14206 case VRCP14PDZ128rk:
14207 case VRCP14PDZ128rkz:
14208 case VRCP14PDZ256m:
14209 case VRCP14PDZ256mb:
14210 case VRCP14PDZ256mbk:
14211 case VRCP14PDZ256mbkz:
14212 case VRCP14PDZ256mk:
14213 case VRCP14PDZ256mkz:
14214 case VRCP14PDZ256r:
14215 case VRCP14PDZ256rk:
14216 case VRCP14PDZ256rkz:
14217 case VRCP14PDZm:
14218 case VRCP14PDZmb:
14219 case VRCP14PDZmbk:
14220 case VRCP14PDZmbkz:
14221 case VRCP14PDZmk:
14222 case VRCP14PDZmkz:
14223 case VRCP14PDZr:
14224 case VRCP14PDZrk:
14225 case VRCP14PDZrkz:
14226 return true;
14227 }
14228 return false;
14229}
14230
14231bool isARPL(unsigned Opcode) {
14232 switch (Opcode) {
14233 case ARPL16mr:
14234 case ARPL16rr:
14235 return true;
14236 }
14237 return false;
14238}
14239
14240bool isVFMSUB213SD(unsigned Opcode) {
14241 switch (Opcode) {
14242 case VFMSUB213SDZm_Int:
14243 case VFMSUB213SDZmk_Int:
14244 case VFMSUB213SDZmkz_Int:
14245 case VFMSUB213SDZr_Int:
14246 case VFMSUB213SDZrb_Int:
14247 case VFMSUB213SDZrbk_Int:
14248 case VFMSUB213SDZrbkz_Int:
14249 case VFMSUB213SDZrk_Int:
14250 case VFMSUB213SDZrkz_Int:
14251 case VFMSUB213SDm_Int:
14252 case VFMSUB213SDr_Int:
14253 return true;
14254 }
14255 return false;
14256}
14257
14258bool isJMPABS(unsigned Opcode) {
14259 return Opcode == JMPABS64i;
14260}
14261
14262bool isVUNPCKHPS(unsigned Opcode) {
14263 switch (Opcode) {
14264 case VUNPCKHPSYrm:
14265 case VUNPCKHPSYrr:
14266 case VUNPCKHPSZ128rm:
14267 case VUNPCKHPSZ128rmb:
14268 case VUNPCKHPSZ128rmbk:
14269 case VUNPCKHPSZ128rmbkz:
14270 case VUNPCKHPSZ128rmk:
14271 case VUNPCKHPSZ128rmkz:
14272 case VUNPCKHPSZ128rr:
14273 case VUNPCKHPSZ128rrk:
14274 case VUNPCKHPSZ128rrkz:
14275 case VUNPCKHPSZ256rm:
14276 case VUNPCKHPSZ256rmb:
14277 case VUNPCKHPSZ256rmbk:
14278 case VUNPCKHPSZ256rmbkz:
14279 case VUNPCKHPSZ256rmk:
14280 case VUNPCKHPSZ256rmkz:
14281 case VUNPCKHPSZ256rr:
14282 case VUNPCKHPSZ256rrk:
14283 case VUNPCKHPSZ256rrkz:
14284 case VUNPCKHPSZrm:
14285 case VUNPCKHPSZrmb:
14286 case VUNPCKHPSZrmbk:
14287 case VUNPCKHPSZrmbkz:
14288 case VUNPCKHPSZrmk:
14289 case VUNPCKHPSZrmkz:
14290 case VUNPCKHPSZrr:
14291 case VUNPCKHPSZrrk:
14292 case VUNPCKHPSZrrkz:
14293 case VUNPCKHPSrm:
14294 case VUNPCKHPSrr:
14295 return true;
14296 }
14297 return false;
14298}
14299
14300bool isVFNMADDSS(unsigned Opcode) {
14301 switch (Opcode) {
14302 case VFNMADDSS4mr:
14303 case VFNMADDSS4rm:
14304 case VFNMADDSS4rr:
14305 case VFNMADDSS4rr_REV:
14306 return true;
14307 }
14308 return false;
14309}
14310
14311bool isSIDT(unsigned Opcode) {
14312 return Opcode == SIDT64m;
14313}
14314
14315bool isVPCMPGTB(unsigned Opcode) {
14316 switch (Opcode) {
14317 case VPCMPGTBYrm:
14318 case VPCMPGTBYrr:
14319 case VPCMPGTBZ128rm:
14320 case VPCMPGTBZ128rmk:
14321 case VPCMPGTBZ128rr:
14322 case VPCMPGTBZ128rrk:
14323 case VPCMPGTBZ256rm:
14324 case VPCMPGTBZ256rmk:
14325 case VPCMPGTBZ256rr:
14326 case VPCMPGTBZ256rrk:
14327 case VPCMPGTBZrm:
14328 case VPCMPGTBZrmk:
14329 case VPCMPGTBZrr:
14330 case VPCMPGTBZrrk:
14331 case VPCMPGTBrm:
14332 case VPCMPGTBrr:
14333 return true;
14334 }
14335 return false;
14336}
14337
14338bool isVPRORD(unsigned Opcode) {
14339 switch (Opcode) {
14340 case VPRORDZ128mbi:
14341 case VPRORDZ128mbik:
14342 case VPRORDZ128mbikz:
14343 case VPRORDZ128mi:
14344 case VPRORDZ128mik:
14345 case VPRORDZ128mikz:
14346 case VPRORDZ128ri:
14347 case VPRORDZ128rik:
14348 case VPRORDZ128rikz:
14349 case VPRORDZ256mbi:
14350 case VPRORDZ256mbik:
14351 case VPRORDZ256mbikz:
14352 case VPRORDZ256mi:
14353 case VPRORDZ256mik:
14354 case VPRORDZ256mikz:
14355 case VPRORDZ256ri:
14356 case VPRORDZ256rik:
14357 case VPRORDZ256rikz:
14358 case VPRORDZmbi:
14359 case VPRORDZmbik:
14360 case VPRORDZmbikz:
14361 case VPRORDZmi:
14362 case VPRORDZmik:
14363 case VPRORDZmikz:
14364 case VPRORDZri:
14365 case VPRORDZrik:
14366 case VPRORDZrikz:
14367 return true;
14368 }
14369 return false;
14370}
14371
14372bool isVSUBSS(unsigned Opcode) {
14373 switch (Opcode) {
14374 case VSUBSSZrm_Int:
14375 case VSUBSSZrmk_Int:
14376 case VSUBSSZrmkz_Int:
14377 case VSUBSSZrr_Int:
14378 case VSUBSSZrrb_Int:
14379 case VSUBSSZrrbk_Int:
14380 case VSUBSSZrrbkz_Int:
14381 case VSUBSSZrrk_Int:
14382 case VSUBSSZrrkz_Int:
14383 case VSUBSSrm_Int:
14384 case VSUBSSrr_Int:
14385 return true;
14386 }
14387 return false;
14388}
14389
14390bool isPUSHFQ(unsigned Opcode) {
14391 return Opcode == PUSHF64;
14392}
14393
14394bool isVCVTHF82PH(unsigned Opcode) {
14395 switch (Opcode) {
14396 case VCVTHF82PHZ128rm:
14397 case VCVTHF82PHZ128rmk:
14398 case VCVTHF82PHZ128rmkz:
14399 case VCVTHF82PHZ128rr:
14400 case VCVTHF82PHZ128rrk:
14401 case VCVTHF82PHZ128rrkz:
14402 case VCVTHF82PHZ256rm:
14403 case VCVTHF82PHZ256rmk:
14404 case VCVTHF82PHZ256rmkz:
14405 case VCVTHF82PHZ256rr:
14406 case VCVTHF82PHZ256rrk:
14407 case VCVTHF82PHZ256rrkz:
14408 case VCVTHF82PHZrm:
14409 case VCVTHF82PHZrmk:
14410 case VCVTHF82PHZrmkz:
14411 case VCVTHF82PHZrr:
14412 case VCVTHF82PHZrrk:
14413 case VCVTHF82PHZrrkz:
14414 return true;
14415 }
14416 return false;
14417}
14418
14419bool isVPCLMULQDQ(unsigned Opcode) {
14420 switch (Opcode) {
14421 case VPCLMULQDQYrmi:
14422 case VPCLMULQDQYrri:
14423 case VPCLMULQDQZ128rmi:
14424 case VPCLMULQDQZ128rri:
14425 case VPCLMULQDQZ256rmi:
14426 case VPCLMULQDQZ256rri:
14427 case VPCLMULQDQZrmi:
14428 case VPCLMULQDQZrri:
14429 case VPCLMULQDQrmi:
14430 case VPCLMULQDQrri:
14431 return true;
14432 }
14433 return false;
14434}
14435
14436bool isVPADDUSB(unsigned Opcode) {
14437 switch (Opcode) {
14438 case VPADDUSBYrm:
14439 case VPADDUSBYrr:
14440 case VPADDUSBZ128rm:
14441 case VPADDUSBZ128rmk:
14442 case VPADDUSBZ128rmkz:
14443 case VPADDUSBZ128rr:
14444 case VPADDUSBZ128rrk:
14445 case VPADDUSBZ128rrkz:
14446 case VPADDUSBZ256rm:
14447 case VPADDUSBZ256rmk:
14448 case VPADDUSBZ256rmkz:
14449 case VPADDUSBZ256rr:
14450 case VPADDUSBZ256rrk:
14451 case VPADDUSBZ256rrkz:
14452 case VPADDUSBZrm:
14453 case VPADDUSBZrmk:
14454 case VPADDUSBZrmkz:
14455 case VPADDUSBZrr:
14456 case VPADDUSBZrrk:
14457 case VPADDUSBZrrkz:
14458 case VPADDUSBrm:
14459 case VPADDUSBrr:
14460 return true;
14461 }
14462 return false;
14463}
14464
14465bool isVPCMPD(unsigned Opcode) {
14466 switch (Opcode) {
14467 case VPCMPDZ128rmbi:
14468 case VPCMPDZ128rmbik:
14469 case VPCMPDZ128rmi:
14470 case VPCMPDZ128rmik:
14471 case VPCMPDZ128rri:
14472 case VPCMPDZ128rrik:
14473 case VPCMPDZ256rmbi:
14474 case VPCMPDZ256rmbik:
14475 case VPCMPDZ256rmi:
14476 case VPCMPDZ256rmik:
14477 case VPCMPDZ256rri:
14478 case VPCMPDZ256rrik:
14479 case VPCMPDZrmbi:
14480 case VPCMPDZrmbik:
14481 case VPCMPDZrmi:
14482 case VPCMPDZrmik:
14483 case VPCMPDZrri:
14484 case VPCMPDZrrik:
14485 return true;
14486 }
14487 return false;
14488}
14489
14490bool isMOVSD(unsigned Opcode) {
14491 switch (Opcode) {
14492 case MOVSDmr:
14493 case MOVSDrm:
14494 case MOVSDrr:
14495 case MOVSDrr_REV:
14496 case MOVSL:
14497 return true;
14498 }
14499 return false;
14500}
14501
14502bool isPSUBUSW(unsigned Opcode) {
14503 switch (Opcode) {
14504 case MMX_PSUBUSWrm:
14505 case MMX_PSUBUSWrr:
14506 case PSUBUSWrm:
14507 case PSUBUSWrr:
14508 return true;
14509 }
14510 return false;
14511}
14512
14513bool isVFMSUBADD132PS(unsigned Opcode) {
14514 switch (Opcode) {
14515 case VFMSUBADD132PSYm:
14516 case VFMSUBADD132PSYr:
14517 case VFMSUBADD132PSZ128m:
14518 case VFMSUBADD132PSZ128mb:
14519 case VFMSUBADD132PSZ128mbk:
14520 case VFMSUBADD132PSZ128mbkz:
14521 case VFMSUBADD132PSZ128mk:
14522 case VFMSUBADD132PSZ128mkz:
14523 case VFMSUBADD132PSZ128r:
14524 case VFMSUBADD132PSZ128rk:
14525 case VFMSUBADD132PSZ128rkz:
14526 case VFMSUBADD132PSZ256m:
14527 case VFMSUBADD132PSZ256mb:
14528 case VFMSUBADD132PSZ256mbk:
14529 case VFMSUBADD132PSZ256mbkz:
14530 case VFMSUBADD132PSZ256mk:
14531 case VFMSUBADD132PSZ256mkz:
14532 case VFMSUBADD132PSZ256r:
14533 case VFMSUBADD132PSZ256rk:
14534 case VFMSUBADD132PSZ256rkz:
14535 case VFMSUBADD132PSZm:
14536 case VFMSUBADD132PSZmb:
14537 case VFMSUBADD132PSZmbk:
14538 case VFMSUBADD132PSZmbkz:
14539 case VFMSUBADD132PSZmk:
14540 case VFMSUBADD132PSZmkz:
14541 case VFMSUBADD132PSZr:
14542 case VFMSUBADD132PSZrb:
14543 case VFMSUBADD132PSZrbk:
14544 case VFMSUBADD132PSZrbkz:
14545 case VFMSUBADD132PSZrk:
14546 case VFMSUBADD132PSZrkz:
14547 case VFMSUBADD132PSm:
14548 case VFMSUBADD132PSr:
14549 return true;
14550 }
14551 return false;
14552}
14553
14554bool isMOVMSKPS(unsigned Opcode) {
14555 return Opcode == MOVMSKPSrr;
14556}
14557
14558bool isVFIXUPIMMSS(unsigned Opcode) {
14559 switch (Opcode) {
14560 case VFIXUPIMMSSZrmi:
14561 case VFIXUPIMMSSZrmik:
14562 case VFIXUPIMMSSZrmikz:
14563 case VFIXUPIMMSSZrri:
14564 case VFIXUPIMMSSZrrib:
14565 case VFIXUPIMMSSZrribk:
14566 case VFIXUPIMMSSZrribkz:
14567 case VFIXUPIMMSSZrrik:
14568 case VFIXUPIMMSSZrrikz:
14569 return true;
14570 }
14571 return false;
14572}
14573
14574bool isMFENCE(unsigned Opcode) {
14575 return Opcode == MFENCE;
14576}
14577
14578bool isFTST(unsigned Opcode) {
14579 return Opcode == TST_F;
14580}
14581
14582bool isVPMADDWD(unsigned Opcode) {
14583 switch (Opcode) {
14584 case VPMADDWDYrm:
14585 case VPMADDWDYrr:
14586 case VPMADDWDZ128rm:
14587 case VPMADDWDZ128rmk:
14588 case VPMADDWDZ128rmkz:
14589 case VPMADDWDZ128rr:
14590 case VPMADDWDZ128rrk:
14591 case VPMADDWDZ128rrkz:
14592 case VPMADDWDZ256rm:
14593 case VPMADDWDZ256rmk:
14594 case VPMADDWDZ256rmkz:
14595 case VPMADDWDZ256rr:
14596 case VPMADDWDZ256rrk:
14597 case VPMADDWDZ256rrkz:
14598 case VPMADDWDZrm:
14599 case VPMADDWDZrmk:
14600 case VPMADDWDZrmkz:
14601 case VPMADDWDZrr:
14602 case VPMADDWDZrrk:
14603 case VPMADDWDZrrkz:
14604 case VPMADDWDrm:
14605 case VPMADDWDrr:
14606 return true;
14607 }
14608 return false;
14609}
14610
14611bool isPOP(unsigned Opcode) {
14612 switch (Opcode) {
14613 case POP16r:
14614 case POP16rmm:
14615 case POP16rmr:
14616 case POP32r:
14617 case POP32rmm:
14618 case POP32rmr:
14619 case POP64r:
14620 case POP64rmm:
14621 case POP64rmr:
14622 case POPDS16:
14623 case POPDS32:
14624 case POPES16:
14625 case POPES32:
14626 case POPFS16:
14627 case POPFS32:
14628 case POPFS64:
14629 case POPGS16:
14630 case POPGS32:
14631 case POPGS64:
14632 case POPSS16:
14633 case POPSS32:
14634 return true;
14635 }
14636 return false;
14637}
14638
14639bool isPSUBW(unsigned Opcode) {
14640 switch (Opcode) {
14641 case MMX_PSUBWrm:
14642 case MMX_PSUBWrr:
14643 case PSUBWrm:
14644 case PSUBWrr:
14645 return true;
14646 }
14647 return false;
14648}
14649
14650bool isBSWAP(unsigned Opcode) {
14651 switch (Opcode) {
14652 case BSWAP16r_BAD:
14653 case BSWAP32r:
14654 case BSWAP64r:
14655 return true;
14656 }
14657 return false;
14658}
14659
14660bool isPFMIN(unsigned Opcode) {
14661 switch (Opcode) {
14662 case PFMINrm:
14663 case PFMINrr:
14664 return true;
14665 }
14666 return false;
14667}
14668
14669bool isVFPCLASSPD(unsigned Opcode) {
14670 switch (Opcode) {
14671 case VFPCLASSPDZ128mbi:
14672 case VFPCLASSPDZ128mbik:
14673 case VFPCLASSPDZ128mi:
14674 case VFPCLASSPDZ128mik:
14675 case VFPCLASSPDZ128ri:
14676 case VFPCLASSPDZ128rik:
14677 case VFPCLASSPDZ256mbi:
14678 case VFPCLASSPDZ256mbik:
14679 case VFPCLASSPDZ256mi:
14680 case VFPCLASSPDZ256mik:
14681 case VFPCLASSPDZ256ri:
14682 case VFPCLASSPDZ256rik:
14683 case VFPCLASSPDZmbi:
14684 case VFPCLASSPDZmbik:
14685 case VFPCLASSPDZmi:
14686 case VFPCLASSPDZmik:
14687 case VFPCLASSPDZri:
14688 case VFPCLASSPDZrik:
14689 return true;
14690 }
14691 return false;
14692}
14693
14694bool isVPSHRDVD(unsigned Opcode) {
14695 switch (Opcode) {
14696 case VPSHRDVDZ128m:
14697 case VPSHRDVDZ128mb:
14698 case VPSHRDVDZ128mbk:
14699 case VPSHRDVDZ128mbkz:
14700 case VPSHRDVDZ128mk:
14701 case VPSHRDVDZ128mkz:
14702 case VPSHRDVDZ128r:
14703 case VPSHRDVDZ128rk:
14704 case VPSHRDVDZ128rkz:
14705 case VPSHRDVDZ256m:
14706 case VPSHRDVDZ256mb:
14707 case VPSHRDVDZ256mbk:
14708 case VPSHRDVDZ256mbkz:
14709 case VPSHRDVDZ256mk:
14710 case VPSHRDVDZ256mkz:
14711 case VPSHRDVDZ256r:
14712 case VPSHRDVDZ256rk:
14713 case VPSHRDVDZ256rkz:
14714 case VPSHRDVDZm:
14715 case VPSHRDVDZmb:
14716 case VPSHRDVDZmbk:
14717 case VPSHRDVDZmbkz:
14718 case VPSHRDVDZmk:
14719 case VPSHRDVDZmkz:
14720 case VPSHRDVDZr:
14721 case VPSHRDVDZrk:
14722 case VPSHRDVDZrkz:
14723 return true;
14724 }
14725 return false;
14726}
14727
14728bool isPADDW(unsigned Opcode) {
14729 switch (Opcode) {
14730 case MMX_PADDWrm:
14731 case MMX_PADDWrr:
14732 case PADDWrm:
14733 case PADDWrr:
14734 return true;
14735 }
14736 return false;
14737}
14738
14739bool isCVTSI2SD(unsigned Opcode) {
14740 switch (Opcode) {
14741 case CVTSI2SDrm_Int:
14742 case CVTSI2SDrr_Int:
14743 case CVTSI642SDrm_Int:
14744 case CVTSI642SDrr_Int:
14745 return true;
14746 }
14747 return false;
14748}
14749
14750bool isENQCMD(unsigned Opcode) {
14751 switch (Opcode) {
14752 case ENQCMD16:
14753 case ENQCMD32:
14754 case ENQCMD32_EVEX:
14755 case ENQCMD64:
14756 case ENQCMD64_EVEX:
14757 return true;
14758 }
14759 return false;
14760}
14761
14762bool isXSHA1(unsigned Opcode) {
14763 return Opcode == XSHA1;
14764}
14765
14766bool isVFNMADD132SD(unsigned Opcode) {
14767 switch (Opcode) {
14768 case VFNMADD132SDZm_Int:
14769 case VFNMADD132SDZmk_Int:
14770 case VFNMADD132SDZmkz_Int:
14771 case VFNMADD132SDZr_Int:
14772 case VFNMADD132SDZrb_Int:
14773 case VFNMADD132SDZrbk_Int:
14774 case VFNMADD132SDZrbkz_Int:
14775 case VFNMADD132SDZrk_Int:
14776 case VFNMADD132SDZrkz_Int:
14777 case VFNMADD132SDm_Int:
14778 case VFNMADD132SDr_Int:
14779 return true;
14780 }
14781 return false;
14782}
14783
14784bool isMOVZX(unsigned Opcode) {
14785 switch (Opcode) {
14786 case MOVZX16rm16:
14787 case MOVZX16rm8:
14788 case MOVZX16rr16:
14789 case MOVZX16rr8:
14790 case MOVZX32rm16:
14791 case MOVZX32rm8:
14792 case MOVZX32rr16:
14793 case MOVZX32rr8:
14794 case MOVZX64rm16:
14795 case MOVZX64rm8:
14796 case MOVZX64rr16:
14797 case MOVZX64rr8:
14798 return true;
14799 }
14800 return false;
14801}
14802
14803bool isVFIXUPIMMSD(unsigned Opcode) {
14804 switch (Opcode) {
14805 case VFIXUPIMMSDZrmi:
14806 case VFIXUPIMMSDZrmik:
14807 case VFIXUPIMMSDZrmikz:
14808 case VFIXUPIMMSDZrri:
14809 case VFIXUPIMMSDZrrib:
14810 case VFIXUPIMMSDZrribk:
14811 case VFIXUPIMMSDZrribkz:
14812 case VFIXUPIMMSDZrrik:
14813 case VFIXUPIMMSDZrrikz:
14814 return true;
14815 }
14816 return false;
14817}
14818
14819bool isINVD(unsigned Opcode) {
14820 return Opcode == INVD;
14821}
14822
14823bool isVFIXUPIMMPS(unsigned Opcode) {
14824 switch (Opcode) {
14825 case VFIXUPIMMPSZ128rmbi:
14826 case VFIXUPIMMPSZ128rmbik:
14827 case VFIXUPIMMPSZ128rmbikz:
14828 case VFIXUPIMMPSZ128rmi:
14829 case VFIXUPIMMPSZ128rmik:
14830 case VFIXUPIMMPSZ128rmikz:
14831 case VFIXUPIMMPSZ128rri:
14832 case VFIXUPIMMPSZ128rrik:
14833 case VFIXUPIMMPSZ128rrikz:
14834 case VFIXUPIMMPSZ256rmbi:
14835 case VFIXUPIMMPSZ256rmbik:
14836 case VFIXUPIMMPSZ256rmbikz:
14837 case VFIXUPIMMPSZ256rmi:
14838 case VFIXUPIMMPSZ256rmik:
14839 case VFIXUPIMMPSZ256rmikz:
14840 case VFIXUPIMMPSZ256rri:
14841 case VFIXUPIMMPSZ256rrik:
14842 case VFIXUPIMMPSZ256rrikz:
14843 case VFIXUPIMMPSZrmbi:
14844 case VFIXUPIMMPSZrmbik:
14845 case VFIXUPIMMPSZrmbikz:
14846 case VFIXUPIMMPSZrmi:
14847 case VFIXUPIMMPSZrmik:
14848 case VFIXUPIMMPSZrmikz:
14849 case VFIXUPIMMPSZrri:
14850 case VFIXUPIMMPSZrrib:
14851 case VFIXUPIMMPSZrribk:
14852 case VFIXUPIMMPSZrribkz:
14853 case VFIXUPIMMPSZrrik:
14854 case VFIXUPIMMPSZrrikz:
14855 return true;
14856 }
14857 return false;
14858}
14859
14860bool isMOVDQU(unsigned Opcode) {
14861 switch (Opcode) {
14862 case MOVDQUmr:
14863 case MOVDQUrm:
14864 case MOVDQUrr:
14865 case MOVDQUrr_REV:
14866 return true;
14867 }
14868 return false;
14869}
14870
14871bool isVFPCLASSPS(unsigned Opcode) {
14872 switch (Opcode) {
14873 case VFPCLASSPSZ128mbi:
14874 case VFPCLASSPSZ128mbik:
14875 case VFPCLASSPSZ128mi:
14876 case VFPCLASSPSZ128mik:
14877 case VFPCLASSPSZ128ri:
14878 case VFPCLASSPSZ128rik:
14879 case VFPCLASSPSZ256mbi:
14880 case VFPCLASSPSZ256mbik:
14881 case VFPCLASSPSZ256mi:
14882 case VFPCLASSPSZ256mik:
14883 case VFPCLASSPSZ256ri:
14884 case VFPCLASSPSZ256rik:
14885 case VFPCLASSPSZmbi:
14886 case VFPCLASSPSZmbik:
14887 case VFPCLASSPSZmi:
14888 case VFPCLASSPSZmik:
14889 case VFPCLASSPSZri:
14890 case VFPCLASSPSZrik:
14891 return true;
14892 }
14893 return false;
14894}
14895
14896bool isMOVSQ(unsigned Opcode) {
14897 return Opcode == MOVSQ;
14898}
14899
14900bool isAESDECWIDE128KL(unsigned Opcode) {
14901 return Opcode == AESDECWIDE128KL;
14902}
14903
14904bool isROUNDSS(unsigned Opcode) {
14905 switch (Opcode) {
14906 case ROUNDSSmi_Int:
14907 case ROUNDSSri_Int:
14908 return true;
14909 }
14910 return false;
14911}
14912
14913bool isVPERMILPS(unsigned Opcode) {
14914 switch (Opcode) {
14915 case VPERMILPSYmi:
14916 case VPERMILPSYri:
14917 case VPERMILPSYrm:
14918 case VPERMILPSYrr:
14919 case VPERMILPSZ128mbi:
14920 case VPERMILPSZ128mbik:
14921 case VPERMILPSZ128mbikz:
14922 case VPERMILPSZ128mi:
14923 case VPERMILPSZ128mik:
14924 case VPERMILPSZ128mikz:
14925 case VPERMILPSZ128ri:
14926 case VPERMILPSZ128rik:
14927 case VPERMILPSZ128rikz:
14928 case VPERMILPSZ128rm:
14929 case VPERMILPSZ128rmb:
14930 case VPERMILPSZ128rmbk:
14931 case VPERMILPSZ128rmbkz:
14932 case VPERMILPSZ128rmk:
14933 case VPERMILPSZ128rmkz:
14934 case VPERMILPSZ128rr:
14935 case VPERMILPSZ128rrk:
14936 case VPERMILPSZ128rrkz:
14937 case VPERMILPSZ256mbi:
14938 case VPERMILPSZ256mbik:
14939 case VPERMILPSZ256mbikz:
14940 case VPERMILPSZ256mi:
14941 case VPERMILPSZ256mik:
14942 case VPERMILPSZ256mikz:
14943 case VPERMILPSZ256ri:
14944 case VPERMILPSZ256rik:
14945 case VPERMILPSZ256rikz:
14946 case VPERMILPSZ256rm:
14947 case VPERMILPSZ256rmb:
14948 case VPERMILPSZ256rmbk:
14949 case VPERMILPSZ256rmbkz:
14950 case VPERMILPSZ256rmk:
14951 case VPERMILPSZ256rmkz:
14952 case VPERMILPSZ256rr:
14953 case VPERMILPSZ256rrk:
14954 case VPERMILPSZ256rrkz:
14955 case VPERMILPSZmbi:
14956 case VPERMILPSZmbik:
14957 case VPERMILPSZmbikz:
14958 case VPERMILPSZmi:
14959 case VPERMILPSZmik:
14960 case VPERMILPSZmikz:
14961 case VPERMILPSZri:
14962 case VPERMILPSZrik:
14963 case VPERMILPSZrikz:
14964 case VPERMILPSZrm:
14965 case VPERMILPSZrmb:
14966 case VPERMILPSZrmbk:
14967 case VPERMILPSZrmbkz:
14968 case VPERMILPSZrmk:
14969 case VPERMILPSZrmkz:
14970 case VPERMILPSZrr:
14971 case VPERMILPSZrrk:
14972 case VPERMILPSZrrkz:
14973 case VPERMILPSmi:
14974 case VPERMILPSri:
14975 case VPERMILPSrm:
14976 case VPERMILPSrr:
14977 return true;
14978 }
14979 return false;
14980}
14981
14982bool isVPMOVW2M(unsigned Opcode) {
14983 switch (Opcode) {
14984 case VPMOVW2MZ128kr:
14985 case VPMOVW2MZ256kr:
14986 case VPMOVW2MZkr:
14987 return true;
14988 }
14989 return false;
14990}
14991
14992bool isVMULSD(unsigned Opcode) {
14993 switch (Opcode) {
14994 case VMULSDZrm_Int:
14995 case VMULSDZrmk_Int:
14996 case VMULSDZrmkz_Int:
14997 case VMULSDZrr_Int:
14998 case VMULSDZrrb_Int:
14999 case VMULSDZrrbk_Int:
15000 case VMULSDZrrbkz_Int:
15001 case VMULSDZrrk_Int:
15002 case VMULSDZrrkz_Int:
15003 case VMULSDrm_Int:
15004 case VMULSDrr_Int:
15005 return true;
15006 }
15007 return false;
15008}
15009
15010bool isVPERMI2W(unsigned Opcode) {
15011 switch (Opcode) {
15012 case VPERMI2WZ128rm:
15013 case VPERMI2WZ128rmk:
15014 case VPERMI2WZ128rmkz:
15015 case VPERMI2WZ128rr:
15016 case VPERMI2WZ128rrk:
15017 case VPERMI2WZ128rrkz:
15018 case VPERMI2WZ256rm:
15019 case VPERMI2WZ256rmk:
15020 case VPERMI2WZ256rmkz:
15021 case VPERMI2WZ256rr:
15022 case VPERMI2WZ256rrk:
15023 case VPERMI2WZ256rrkz:
15024 case VPERMI2WZrm:
15025 case VPERMI2WZrmk:
15026 case VPERMI2WZrmkz:
15027 case VPERMI2WZrr:
15028 case VPERMI2WZrrk:
15029 case VPERMI2WZrrkz:
15030 return true;
15031 }
15032 return false;
15033}
15034
15035bool isVPSHUFB(unsigned Opcode) {
15036 switch (Opcode) {
15037 case VPSHUFBYrm:
15038 case VPSHUFBYrr:
15039 case VPSHUFBZ128rm:
15040 case VPSHUFBZ128rmk:
15041 case VPSHUFBZ128rmkz:
15042 case VPSHUFBZ128rr:
15043 case VPSHUFBZ128rrk:
15044 case VPSHUFBZ128rrkz:
15045 case VPSHUFBZ256rm:
15046 case VPSHUFBZ256rmk:
15047 case VPSHUFBZ256rmkz:
15048 case VPSHUFBZ256rr:
15049 case VPSHUFBZ256rrk:
15050 case VPSHUFBZ256rrkz:
15051 case VPSHUFBZrm:
15052 case VPSHUFBZrmk:
15053 case VPSHUFBZrmkz:
15054 case VPSHUFBZrr:
15055 case VPSHUFBZrrk:
15056 case VPSHUFBZrrkz:
15057 case VPSHUFBrm:
15058 case VPSHUFBrr:
15059 return true;
15060 }
15061 return false;
15062}
15063
15064bool isFST(unsigned Opcode) {
15065 switch (Opcode) {
15066 case ST_F32m:
15067 case ST_F64m:
15068 case ST_Frr:
15069 return true;
15070 }
15071 return false;
15072}
15073
15074bool isVPHSUBW(unsigned Opcode) {
15075 switch (Opcode) {
15076 case VPHSUBWYrm:
15077 case VPHSUBWYrr:
15078 case VPHSUBWrm:
15079 case VPHSUBWrr:
15080 return true;
15081 }
15082 return false;
15083}
15084
15085bool isVREDUCESS(unsigned Opcode) {
15086 switch (Opcode) {
15087 case VREDUCESSZrmi:
15088 case VREDUCESSZrmik:
15089 case VREDUCESSZrmikz:
15090 case VREDUCESSZrri:
15091 case VREDUCESSZrrib:
15092 case VREDUCESSZrribk:
15093 case VREDUCESSZrribkz:
15094 case VREDUCESSZrrik:
15095 case VREDUCESSZrrikz:
15096 return true;
15097 }
15098 return false;
15099}
15100
15101bool isFRNDINT(unsigned Opcode) {
15102 return Opcode == FRNDINT;
15103}
15104
15105bool isSHR(unsigned Opcode) {
15106 switch (Opcode) {
15107 case SHR16m1:
15108 case SHR16m1_EVEX:
15109 case SHR16m1_ND:
15110 case SHR16m1_NF:
15111 case SHR16m1_NF_ND:
15112 case SHR16mCL:
15113 case SHR16mCL_EVEX:
15114 case SHR16mCL_ND:
15115 case SHR16mCL_NF:
15116 case SHR16mCL_NF_ND:
15117 case SHR16mi:
15118 case SHR16mi_EVEX:
15119 case SHR16mi_ND:
15120 case SHR16mi_NF:
15121 case SHR16mi_NF_ND:
15122 case SHR16r1:
15123 case SHR16r1_EVEX:
15124 case SHR16r1_ND:
15125 case SHR16r1_NF:
15126 case SHR16r1_NF_ND:
15127 case SHR16rCL:
15128 case SHR16rCL_EVEX:
15129 case SHR16rCL_ND:
15130 case SHR16rCL_NF:
15131 case SHR16rCL_NF_ND:
15132 case SHR16ri:
15133 case SHR16ri_EVEX:
15134 case SHR16ri_ND:
15135 case SHR16ri_NF:
15136 case SHR16ri_NF_ND:
15137 case SHR32m1:
15138 case SHR32m1_EVEX:
15139 case SHR32m1_ND:
15140 case SHR32m1_NF:
15141 case SHR32m1_NF_ND:
15142 case SHR32mCL:
15143 case SHR32mCL_EVEX:
15144 case SHR32mCL_ND:
15145 case SHR32mCL_NF:
15146 case SHR32mCL_NF_ND:
15147 case SHR32mi:
15148 case SHR32mi_EVEX:
15149 case SHR32mi_ND:
15150 case SHR32mi_NF:
15151 case SHR32mi_NF_ND:
15152 case SHR32r1:
15153 case SHR32r1_EVEX:
15154 case SHR32r1_ND:
15155 case SHR32r1_NF:
15156 case SHR32r1_NF_ND:
15157 case SHR32rCL:
15158 case SHR32rCL_EVEX:
15159 case SHR32rCL_ND:
15160 case SHR32rCL_NF:
15161 case SHR32rCL_NF_ND:
15162 case SHR32ri:
15163 case SHR32ri_EVEX:
15164 case SHR32ri_ND:
15165 case SHR32ri_NF:
15166 case SHR32ri_NF_ND:
15167 case SHR64m1:
15168 case SHR64m1_EVEX:
15169 case SHR64m1_ND:
15170 case SHR64m1_NF:
15171 case SHR64m1_NF_ND:
15172 case SHR64mCL:
15173 case SHR64mCL_EVEX:
15174 case SHR64mCL_ND:
15175 case SHR64mCL_NF:
15176 case SHR64mCL_NF_ND:
15177 case SHR64mi:
15178 case SHR64mi_EVEX:
15179 case SHR64mi_ND:
15180 case SHR64mi_NF:
15181 case SHR64mi_NF_ND:
15182 case SHR64r1:
15183 case SHR64r1_EVEX:
15184 case SHR64r1_ND:
15185 case SHR64r1_NF:
15186 case SHR64r1_NF_ND:
15187 case SHR64rCL:
15188 case SHR64rCL_EVEX:
15189 case SHR64rCL_ND:
15190 case SHR64rCL_NF:
15191 case SHR64rCL_NF_ND:
15192 case SHR64ri:
15193 case SHR64ri_EVEX:
15194 case SHR64ri_ND:
15195 case SHR64ri_NF:
15196 case SHR64ri_NF_ND:
15197 case SHR8m1:
15198 case SHR8m1_EVEX:
15199 case SHR8m1_ND:
15200 case SHR8m1_NF:
15201 case SHR8m1_NF_ND:
15202 case SHR8mCL:
15203 case SHR8mCL_EVEX:
15204 case SHR8mCL_ND:
15205 case SHR8mCL_NF:
15206 case SHR8mCL_NF_ND:
15207 case SHR8mi:
15208 case SHR8mi_EVEX:
15209 case SHR8mi_ND:
15210 case SHR8mi_NF:
15211 case SHR8mi_NF_ND:
15212 case SHR8r1:
15213 case SHR8r1_EVEX:
15214 case SHR8r1_ND:
15215 case SHR8r1_NF:
15216 case SHR8r1_NF_ND:
15217 case SHR8rCL:
15218 case SHR8rCL_EVEX:
15219 case SHR8rCL_ND:
15220 case SHR8rCL_NF:
15221 case SHR8rCL_NF_ND:
15222 case SHR8ri:
15223 case SHR8ri_EVEX:
15224 case SHR8ri_ND:
15225 case SHR8ri_NF:
15226 case SHR8ri_NF_ND:
15227 return true;
15228 }
15229 return false;
15230}
15231
15232bool isLOOPNE(unsigned Opcode) {
15233 return Opcode == LOOPNE;
15234}
15235
15236bool isVCVTTPH2UQQ(unsigned Opcode) {
15237 switch (Opcode) {
15238 case VCVTTPH2UQQZ128rm:
15239 case VCVTTPH2UQQZ128rmb:
15240 case VCVTTPH2UQQZ128rmbk:
15241 case VCVTTPH2UQQZ128rmbkz:
15242 case VCVTTPH2UQQZ128rmk:
15243 case VCVTTPH2UQQZ128rmkz:
15244 case VCVTTPH2UQQZ128rr:
15245 case VCVTTPH2UQQZ128rrk:
15246 case VCVTTPH2UQQZ128rrkz:
15247 case VCVTTPH2UQQZ256rm:
15248 case VCVTTPH2UQQZ256rmb:
15249 case VCVTTPH2UQQZ256rmbk:
15250 case VCVTTPH2UQQZ256rmbkz:
15251 case VCVTTPH2UQQZ256rmk:
15252 case VCVTTPH2UQQZ256rmkz:
15253 case VCVTTPH2UQQZ256rr:
15254 case VCVTTPH2UQQZ256rrk:
15255 case VCVTTPH2UQQZ256rrkz:
15256 case VCVTTPH2UQQZrm:
15257 case VCVTTPH2UQQZrmb:
15258 case VCVTTPH2UQQZrmbk:
15259 case VCVTTPH2UQQZrmbkz:
15260 case VCVTTPH2UQQZrmk:
15261 case VCVTTPH2UQQZrmkz:
15262 case VCVTTPH2UQQZrr:
15263 case VCVTTPH2UQQZrrb:
15264 case VCVTTPH2UQQZrrbk:
15265 case VCVTTPH2UQQZrrbkz:
15266 case VCVTTPH2UQQZrrk:
15267 case VCVTTPH2UQQZrrkz:
15268 return true;
15269 }
15270 return false;
15271}
15272
15273bool isSHA1NEXTE(unsigned Opcode) {
15274 switch (Opcode) {
15275 case SHA1NEXTErm:
15276 case SHA1NEXTErr:
15277 return true;
15278 }
15279 return false;
15280}
15281
15282bool isVFMADD132SD(unsigned Opcode) {
15283 switch (Opcode) {
15284 case VFMADD132SDZm_Int:
15285 case VFMADD132SDZmk_Int:
15286 case VFMADD132SDZmkz_Int:
15287 case VFMADD132SDZr_Int:
15288 case VFMADD132SDZrb_Int:
15289 case VFMADD132SDZrbk_Int:
15290 case VFMADD132SDZrbkz_Int:
15291 case VFMADD132SDZrk_Int:
15292 case VFMADD132SDZrkz_Int:
15293 case VFMADD132SDm_Int:
15294 case VFMADD132SDr_Int:
15295 return true;
15296 }
15297 return false;
15298}
15299
15300bool isPSRAW(unsigned Opcode) {
15301 switch (Opcode) {
15302 case MMX_PSRAWri:
15303 case MMX_PSRAWrm:
15304 case MMX_PSRAWrr:
15305 case PSRAWri:
15306 case PSRAWrm:
15307 case PSRAWrr:
15308 return true;
15309 }
15310 return false;
15311}
15312
15313bool isVPBROADCASTQ(unsigned Opcode) {
15314 switch (Opcode) {
15315 case VPBROADCASTQYrm:
15316 case VPBROADCASTQYrr:
15317 case VPBROADCASTQZ128rm:
15318 case VPBROADCASTQZ128rmk:
15319 case VPBROADCASTQZ128rmkz:
15320 case VPBROADCASTQZ128rr:
15321 case VPBROADCASTQZ128rrk:
15322 case VPBROADCASTQZ128rrkz:
15323 case VPBROADCASTQZ256rm:
15324 case VPBROADCASTQZ256rmk:
15325 case VPBROADCASTQZ256rmkz:
15326 case VPBROADCASTQZ256rr:
15327 case VPBROADCASTQZ256rrk:
15328 case VPBROADCASTQZ256rrkz:
15329 case VPBROADCASTQZrm:
15330 case VPBROADCASTQZrmk:
15331 case VPBROADCASTQZrmkz:
15332 case VPBROADCASTQZrr:
15333 case VPBROADCASTQZrrk:
15334 case VPBROADCASTQZrrkz:
15335 case VPBROADCASTQrZ128rr:
15336 case VPBROADCASTQrZ128rrk:
15337 case VPBROADCASTQrZ128rrkz:
15338 case VPBROADCASTQrZ256rr:
15339 case VPBROADCASTQrZ256rrk:
15340 case VPBROADCASTQrZ256rrkz:
15341 case VPBROADCASTQrZrr:
15342 case VPBROADCASTQrZrrk:
15343 case VPBROADCASTQrZrrkz:
15344 case VPBROADCASTQrm:
15345 case VPBROADCASTQrr:
15346 return true;
15347 }
15348 return false;
15349}
15350
15351bool isCLC(unsigned Opcode) {
15352 return Opcode == CLC;
15353}
15354
15355bool isPOPAW(unsigned Opcode) {
15356 return Opcode == POPA16;
15357}
15358
15359bool isTCMMIMFP16PS(unsigned Opcode) {
15360 return Opcode == TCMMIMFP16PS;
15361}
15362
15363bool isVCVTTPS2UQQ(unsigned Opcode) {
15364 switch (Opcode) {
15365 case VCVTTPS2UQQZ128rm:
15366 case VCVTTPS2UQQZ128rmb:
15367 case VCVTTPS2UQQZ128rmbk:
15368 case VCVTTPS2UQQZ128rmbkz:
15369 case VCVTTPS2UQQZ128rmk:
15370 case VCVTTPS2UQQZ128rmkz:
15371 case VCVTTPS2UQQZ128rr:
15372 case VCVTTPS2UQQZ128rrk:
15373 case VCVTTPS2UQQZ128rrkz:
15374 case VCVTTPS2UQQZ256rm:
15375 case VCVTTPS2UQQZ256rmb:
15376 case VCVTTPS2UQQZ256rmbk:
15377 case VCVTTPS2UQQZ256rmbkz:
15378 case VCVTTPS2UQQZ256rmk:
15379 case VCVTTPS2UQQZ256rmkz:
15380 case VCVTTPS2UQQZ256rr:
15381 case VCVTTPS2UQQZ256rrk:
15382 case VCVTTPS2UQQZ256rrkz:
15383 case VCVTTPS2UQQZrm:
15384 case VCVTTPS2UQQZrmb:
15385 case VCVTTPS2UQQZrmbk:
15386 case VCVTTPS2UQQZrmbkz:
15387 case VCVTTPS2UQQZrmk:
15388 case VCVTTPS2UQQZrmkz:
15389 case VCVTTPS2UQQZrr:
15390 case VCVTTPS2UQQZrrb:
15391 case VCVTTPS2UQQZrrbk:
15392 case VCVTTPS2UQQZrrbkz:
15393 case VCVTTPS2UQQZrrk:
15394 case VCVTTPS2UQQZrrkz:
15395 return true;
15396 }
15397 return false;
15398}
15399
15400bool isVCVTQQ2PH(unsigned Opcode) {
15401 switch (Opcode) {
15402 case VCVTQQ2PHZ128rm:
15403 case VCVTQQ2PHZ128rmb:
15404 case VCVTQQ2PHZ128rmbk:
15405 case VCVTQQ2PHZ128rmbkz:
15406 case VCVTQQ2PHZ128rmk:
15407 case VCVTQQ2PHZ128rmkz:
15408 case VCVTQQ2PHZ128rr:
15409 case VCVTQQ2PHZ128rrk:
15410 case VCVTQQ2PHZ128rrkz:
15411 case VCVTQQ2PHZ256rm:
15412 case VCVTQQ2PHZ256rmb:
15413 case VCVTQQ2PHZ256rmbk:
15414 case VCVTQQ2PHZ256rmbkz:
15415 case VCVTQQ2PHZ256rmk:
15416 case VCVTQQ2PHZ256rmkz:
15417 case VCVTQQ2PHZ256rr:
15418 case VCVTQQ2PHZ256rrk:
15419 case VCVTQQ2PHZ256rrkz:
15420 case VCVTQQ2PHZrm:
15421 case VCVTQQ2PHZrmb:
15422 case VCVTQQ2PHZrmbk:
15423 case VCVTQQ2PHZrmbkz:
15424 case VCVTQQ2PHZrmk:
15425 case VCVTQQ2PHZrmkz:
15426 case VCVTQQ2PHZrr:
15427 case VCVTQQ2PHZrrb:
15428 case VCVTQQ2PHZrrbk:
15429 case VCVTQQ2PHZrrbkz:
15430 case VCVTQQ2PHZrrk:
15431 case VCVTQQ2PHZrrkz:
15432 return true;
15433 }
15434 return false;
15435}
15436
15437bool isVMOVUPD(unsigned Opcode) {
15438 switch (Opcode) {
15439 case VMOVUPDYmr:
15440 case VMOVUPDYrm:
15441 case VMOVUPDYrr:
15442 case VMOVUPDYrr_REV:
15443 case VMOVUPDZ128mr:
15444 case VMOVUPDZ128mrk:
15445 case VMOVUPDZ128rm:
15446 case VMOVUPDZ128rmk:
15447 case VMOVUPDZ128rmkz:
15448 case VMOVUPDZ128rr:
15449 case VMOVUPDZ128rr_REV:
15450 case VMOVUPDZ128rrk:
15451 case VMOVUPDZ128rrk_REV:
15452 case VMOVUPDZ128rrkz:
15453 case VMOVUPDZ128rrkz_REV:
15454 case VMOVUPDZ256mr:
15455 case VMOVUPDZ256mrk:
15456 case VMOVUPDZ256rm:
15457 case VMOVUPDZ256rmk:
15458 case VMOVUPDZ256rmkz:
15459 case VMOVUPDZ256rr:
15460 case VMOVUPDZ256rr_REV:
15461 case VMOVUPDZ256rrk:
15462 case VMOVUPDZ256rrk_REV:
15463 case VMOVUPDZ256rrkz:
15464 case VMOVUPDZ256rrkz_REV:
15465 case VMOVUPDZmr:
15466 case VMOVUPDZmrk:
15467 case VMOVUPDZrm:
15468 case VMOVUPDZrmk:
15469 case VMOVUPDZrmkz:
15470 case VMOVUPDZrr:
15471 case VMOVUPDZrr_REV:
15472 case VMOVUPDZrrk:
15473 case VMOVUPDZrrk_REV:
15474 case VMOVUPDZrrkz:
15475 case VMOVUPDZrrkz_REV:
15476 case VMOVUPDmr:
15477 case VMOVUPDrm:
15478 case VMOVUPDrr:
15479 case VMOVUPDrr_REV:
15480 return true;
15481 }
15482 return false;
15483}
15484
15485bool isFPTAN(unsigned Opcode) {
15486 return Opcode == FPTAN;
15487}
15488
15489bool isVMASKMOVPD(unsigned Opcode) {
15490 switch (Opcode) {
15491 case VMASKMOVPDYmr:
15492 case VMASKMOVPDYrm:
15493 case VMASKMOVPDmr:
15494 case VMASKMOVPDrm:
15495 return true;
15496 }
15497 return false;
15498}
15499
15500bool isVMOVLHPS(unsigned Opcode) {
15501 switch (Opcode) {
15502 case VMOVLHPSZrr:
15503 case VMOVLHPSrr:
15504 return true;
15505 }
15506 return false;
15507}
15508
15509bool isAESKEYGENASSIST(unsigned Opcode) {
15510 switch (Opcode) {
15511 case AESKEYGENASSISTrmi:
15512 case AESKEYGENASSISTrri:
15513 return true;
15514 }
15515 return false;
15516}
15517
15518bool isXSAVEOPT64(unsigned Opcode) {
15519 return Opcode == XSAVEOPT64;
15520}
15521
15522bool isXSAVEC(unsigned Opcode) {
15523 return Opcode == XSAVEC;
15524}
15525
15526bool isVPLZCNTQ(unsigned Opcode) {
15527 switch (Opcode) {
15528 case VPLZCNTQZ128rm:
15529 case VPLZCNTQZ128rmb:
15530 case VPLZCNTQZ128rmbk:
15531 case VPLZCNTQZ128rmbkz:
15532 case VPLZCNTQZ128rmk:
15533 case VPLZCNTQZ128rmkz:
15534 case VPLZCNTQZ128rr:
15535 case VPLZCNTQZ128rrk:
15536 case VPLZCNTQZ128rrkz:
15537 case VPLZCNTQZ256rm:
15538 case VPLZCNTQZ256rmb:
15539 case VPLZCNTQZ256rmbk:
15540 case VPLZCNTQZ256rmbkz:
15541 case VPLZCNTQZ256rmk:
15542 case VPLZCNTQZ256rmkz:
15543 case VPLZCNTQZ256rr:
15544 case VPLZCNTQZ256rrk:
15545 case VPLZCNTQZ256rrkz:
15546 case VPLZCNTQZrm:
15547 case VPLZCNTQZrmb:
15548 case VPLZCNTQZrmbk:
15549 case VPLZCNTQZrmbkz:
15550 case VPLZCNTQZrmk:
15551 case VPLZCNTQZrmkz:
15552 case VPLZCNTQZrr:
15553 case VPLZCNTQZrrk:
15554 case VPLZCNTQZrrkz:
15555 return true;
15556 }
15557 return false;
15558}
15559
15560bool isVPSUBW(unsigned Opcode) {
15561 switch (Opcode) {
15562 case VPSUBWYrm:
15563 case VPSUBWYrr:
15564 case VPSUBWZ128rm:
15565 case VPSUBWZ128rmk:
15566 case VPSUBWZ128rmkz:
15567 case VPSUBWZ128rr:
15568 case VPSUBWZ128rrk:
15569 case VPSUBWZ128rrkz:
15570 case VPSUBWZ256rm:
15571 case VPSUBWZ256rmk:
15572 case VPSUBWZ256rmkz:
15573 case VPSUBWZ256rr:
15574 case VPSUBWZ256rrk:
15575 case VPSUBWZ256rrkz:
15576 case VPSUBWZrm:
15577 case VPSUBWZrmk:
15578 case VPSUBWZrmkz:
15579 case VPSUBWZrr:
15580 case VPSUBWZrrk:
15581 case VPSUBWZrrkz:
15582 case VPSUBWrm:
15583 case VPSUBWrr:
15584 return true;
15585 }
15586 return false;
15587}
15588
15589bool isCMPCCXADD(unsigned Opcode) {
15590 switch (Opcode) {
15591 case CMPCCXADDmr32:
15592 case CMPCCXADDmr32_EVEX:
15593 case CMPCCXADDmr64:
15594 case CMPCCXADDmr64_EVEX:
15595 return true;
15596 }
15597 return false;
15598}
15599
15600bool isVFMSUBADD213PH(unsigned Opcode) {
15601 switch (Opcode) {
15602 case VFMSUBADD213PHZ128m:
15603 case VFMSUBADD213PHZ128mb:
15604 case VFMSUBADD213PHZ128mbk:
15605 case VFMSUBADD213PHZ128mbkz:
15606 case VFMSUBADD213PHZ128mk:
15607 case VFMSUBADD213PHZ128mkz:
15608 case VFMSUBADD213PHZ128r:
15609 case VFMSUBADD213PHZ128rk:
15610 case VFMSUBADD213PHZ128rkz:
15611 case VFMSUBADD213PHZ256m:
15612 case VFMSUBADD213PHZ256mb:
15613 case VFMSUBADD213PHZ256mbk:
15614 case VFMSUBADD213PHZ256mbkz:
15615 case VFMSUBADD213PHZ256mk:
15616 case VFMSUBADD213PHZ256mkz:
15617 case VFMSUBADD213PHZ256r:
15618 case VFMSUBADD213PHZ256rk:
15619 case VFMSUBADD213PHZ256rkz:
15620 case VFMSUBADD213PHZm:
15621 case VFMSUBADD213PHZmb:
15622 case VFMSUBADD213PHZmbk:
15623 case VFMSUBADD213PHZmbkz:
15624 case VFMSUBADD213PHZmk:
15625 case VFMSUBADD213PHZmkz:
15626 case VFMSUBADD213PHZr:
15627 case VFMSUBADD213PHZrb:
15628 case VFMSUBADD213PHZrbk:
15629 case VFMSUBADD213PHZrbkz:
15630 case VFMSUBADD213PHZrk:
15631 case VFMSUBADD213PHZrkz:
15632 return true;
15633 }
15634 return false;
15635}
15636
15637bool isVFMADDSUBPD(unsigned Opcode) {
15638 switch (Opcode) {
15639 case VFMADDSUBPD4Ymr:
15640 case VFMADDSUBPD4Yrm:
15641 case VFMADDSUBPD4Yrr:
15642 case VFMADDSUBPD4Yrr_REV:
15643 case VFMADDSUBPD4mr:
15644 case VFMADDSUBPD4rm:
15645 case VFMADDSUBPD4rr:
15646 case VFMADDSUBPD4rr_REV:
15647 return true;
15648 }
15649 return false;
15650}
15651
15652bool isVPMINSW(unsigned Opcode) {
15653 switch (Opcode) {
15654 case VPMINSWYrm:
15655 case VPMINSWYrr:
15656 case VPMINSWZ128rm:
15657 case VPMINSWZ128rmk:
15658 case VPMINSWZ128rmkz:
15659 case VPMINSWZ128rr:
15660 case VPMINSWZ128rrk:
15661 case VPMINSWZ128rrkz:
15662 case VPMINSWZ256rm:
15663 case VPMINSWZ256rmk:
15664 case VPMINSWZ256rmkz:
15665 case VPMINSWZ256rr:
15666 case VPMINSWZ256rrk:
15667 case VPMINSWZ256rrkz:
15668 case VPMINSWZrm:
15669 case VPMINSWZrmk:
15670 case VPMINSWZrmkz:
15671 case VPMINSWZrr:
15672 case VPMINSWZrrk:
15673 case VPMINSWZrrkz:
15674 case VPMINSWrm:
15675 case VPMINSWrr:
15676 return true;
15677 }
15678 return false;
15679}
15680
15681bool isVFNMSUB132PS(unsigned Opcode) {
15682 switch (Opcode) {
15683 case VFNMSUB132PSYm:
15684 case VFNMSUB132PSYr:
15685 case VFNMSUB132PSZ128m:
15686 case VFNMSUB132PSZ128mb:
15687 case VFNMSUB132PSZ128mbk:
15688 case VFNMSUB132PSZ128mbkz:
15689 case VFNMSUB132PSZ128mk:
15690 case VFNMSUB132PSZ128mkz:
15691 case VFNMSUB132PSZ128r:
15692 case VFNMSUB132PSZ128rk:
15693 case VFNMSUB132PSZ128rkz:
15694 case VFNMSUB132PSZ256m:
15695 case VFNMSUB132PSZ256mb:
15696 case VFNMSUB132PSZ256mbk:
15697 case VFNMSUB132PSZ256mbkz:
15698 case VFNMSUB132PSZ256mk:
15699 case VFNMSUB132PSZ256mkz:
15700 case VFNMSUB132PSZ256r:
15701 case VFNMSUB132PSZ256rk:
15702 case VFNMSUB132PSZ256rkz:
15703 case VFNMSUB132PSZm:
15704 case VFNMSUB132PSZmb:
15705 case VFNMSUB132PSZmbk:
15706 case VFNMSUB132PSZmbkz:
15707 case VFNMSUB132PSZmk:
15708 case VFNMSUB132PSZmkz:
15709 case VFNMSUB132PSZr:
15710 case VFNMSUB132PSZrb:
15711 case VFNMSUB132PSZrbk:
15712 case VFNMSUB132PSZrbkz:
15713 case VFNMSUB132PSZrk:
15714 case VFNMSUB132PSZrkz:
15715 case VFNMSUB132PSm:
15716 case VFNMSUB132PSr:
15717 return true;
15718 }
15719 return false;
15720}
15721
15722bool isVMOVAPS(unsigned Opcode) {
15723 switch (Opcode) {
15724 case VMOVAPSYmr:
15725 case VMOVAPSYrm:
15726 case VMOVAPSYrr:
15727 case VMOVAPSYrr_REV:
15728 case VMOVAPSZ128mr:
15729 case VMOVAPSZ128mrk:
15730 case VMOVAPSZ128rm:
15731 case VMOVAPSZ128rmk:
15732 case VMOVAPSZ128rmkz:
15733 case VMOVAPSZ128rr:
15734 case VMOVAPSZ128rr_REV:
15735 case VMOVAPSZ128rrk:
15736 case VMOVAPSZ128rrk_REV:
15737 case VMOVAPSZ128rrkz:
15738 case VMOVAPSZ128rrkz_REV:
15739 case VMOVAPSZ256mr:
15740 case VMOVAPSZ256mrk:
15741 case VMOVAPSZ256rm:
15742 case VMOVAPSZ256rmk:
15743 case VMOVAPSZ256rmkz:
15744 case VMOVAPSZ256rr:
15745 case VMOVAPSZ256rr_REV:
15746 case VMOVAPSZ256rrk:
15747 case VMOVAPSZ256rrk_REV:
15748 case VMOVAPSZ256rrkz:
15749 case VMOVAPSZ256rrkz_REV:
15750 case VMOVAPSZmr:
15751 case VMOVAPSZmrk:
15752 case VMOVAPSZrm:
15753 case VMOVAPSZrmk:
15754 case VMOVAPSZrmkz:
15755 case VMOVAPSZrr:
15756 case VMOVAPSZrr_REV:
15757 case VMOVAPSZrrk:
15758 case VMOVAPSZrrk_REV:
15759 case VMOVAPSZrrkz:
15760 case VMOVAPSZrrkz_REV:
15761 case VMOVAPSmr:
15762 case VMOVAPSrm:
15763 case VMOVAPSrr:
15764 case VMOVAPSrr_REV:
15765 return true;
15766 }
15767 return false;
15768}
15769
15770bool isVPEXTRQ(unsigned Opcode) {
15771 switch (Opcode) {
15772 case VPEXTRQZmri:
15773 case VPEXTRQZrri:
15774 case VPEXTRQmri:
15775 case VPEXTRQrri:
15776 return true;
15777 }
15778 return false;
15779}
15780
15781bool isVSCALEFSH(unsigned Opcode) {
15782 switch (Opcode) {
15783 case VSCALEFSHZrm:
15784 case VSCALEFSHZrmk:
15785 case VSCALEFSHZrmkz:
15786 case VSCALEFSHZrr:
15787 case VSCALEFSHZrrb_Int:
15788 case VSCALEFSHZrrbk_Int:
15789 case VSCALEFSHZrrbkz_Int:
15790 case VSCALEFSHZrrk:
15791 case VSCALEFSHZrrkz:
15792 return true;
15793 }
15794 return false;
15795}
15796
15797bool isVCVTPD2PS(unsigned Opcode) {
15798 switch (Opcode) {
15799 case VCVTPD2PSYrm:
15800 case VCVTPD2PSYrr:
15801 case VCVTPD2PSZ128rm:
15802 case VCVTPD2PSZ128rmb:
15803 case VCVTPD2PSZ128rmbk:
15804 case VCVTPD2PSZ128rmbkz:
15805 case VCVTPD2PSZ128rmk:
15806 case VCVTPD2PSZ128rmkz:
15807 case VCVTPD2PSZ128rr:
15808 case VCVTPD2PSZ128rrk:
15809 case VCVTPD2PSZ128rrkz:
15810 case VCVTPD2PSZ256rm:
15811 case VCVTPD2PSZ256rmb:
15812 case VCVTPD2PSZ256rmbk:
15813 case VCVTPD2PSZ256rmbkz:
15814 case VCVTPD2PSZ256rmk:
15815 case VCVTPD2PSZ256rmkz:
15816 case VCVTPD2PSZ256rr:
15817 case VCVTPD2PSZ256rrk:
15818 case VCVTPD2PSZ256rrkz:
15819 case VCVTPD2PSZrm:
15820 case VCVTPD2PSZrmb:
15821 case VCVTPD2PSZrmbk:
15822 case VCVTPD2PSZrmbkz:
15823 case VCVTPD2PSZrmk:
15824 case VCVTPD2PSZrmkz:
15825 case VCVTPD2PSZrr:
15826 case VCVTPD2PSZrrb:
15827 case VCVTPD2PSZrrbk:
15828 case VCVTPD2PSZrrbkz:
15829 case VCVTPD2PSZrrk:
15830 case VCVTPD2PSZrrkz:
15831 case VCVTPD2PSrm:
15832 case VCVTPD2PSrr:
15833 return true;
15834 }
15835 return false;
15836}
15837
15838bool isCLGI(unsigned Opcode) {
15839 return Opcode == CLGI;
15840}
15841
15842bool isVAESDEC(unsigned Opcode) {
15843 switch (Opcode) {
15844 case VAESDECYrm:
15845 case VAESDECYrr:
15846 case VAESDECZ128rm:
15847 case VAESDECZ128rr:
15848 case VAESDECZ256rm:
15849 case VAESDECZ256rr:
15850 case VAESDECZrm:
15851 case VAESDECZrr:
15852 case VAESDECrm:
15853 case VAESDECrr:
15854 return true;
15855 }
15856 return false;
15857}
15858
15859bool isPFMUL(unsigned Opcode) {
15860 switch (Opcode) {
15861 case PFMULrm:
15862 case PFMULrr:
15863 return true;
15864 }
15865 return false;
15866}
15867
15868bool isVCVTBIASPH2BF8S(unsigned Opcode) {
15869 switch (Opcode) {
15870 case VCVTBIASPH2BF8SZ128rm:
15871 case VCVTBIASPH2BF8SZ128rmb:
15872 case VCVTBIASPH2BF8SZ128rmbk:
15873 case VCVTBIASPH2BF8SZ128rmbkz:
15874 case VCVTBIASPH2BF8SZ128rmk:
15875 case VCVTBIASPH2BF8SZ128rmkz:
15876 case VCVTBIASPH2BF8SZ128rr:
15877 case VCVTBIASPH2BF8SZ128rrk:
15878 case VCVTBIASPH2BF8SZ128rrkz:
15879 case VCVTBIASPH2BF8SZ256rm:
15880 case VCVTBIASPH2BF8SZ256rmb:
15881 case VCVTBIASPH2BF8SZ256rmbk:
15882 case VCVTBIASPH2BF8SZ256rmbkz:
15883 case VCVTBIASPH2BF8SZ256rmk:
15884 case VCVTBIASPH2BF8SZ256rmkz:
15885 case VCVTBIASPH2BF8SZ256rr:
15886 case VCVTBIASPH2BF8SZ256rrk:
15887 case VCVTBIASPH2BF8SZ256rrkz:
15888 case VCVTBIASPH2BF8SZrm:
15889 case VCVTBIASPH2BF8SZrmb:
15890 case VCVTBIASPH2BF8SZrmbk:
15891 case VCVTBIASPH2BF8SZrmbkz:
15892 case VCVTBIASPH2BF8SZrmk:
15893 case VCVTBIASPH2BF8SZrmkz:
15894 case VCVTBIASPH2BF8SZrr:
15895 case VCVTBIASPH2BF8SZrrk:
15896 case VCVTBIASPH2BF8SZrrkz:
15897 return true;
15898 }
15899 return false;
15900}
15901
15902bool isMOVDIRI(unsigned Opcode) {
15903 switch (Opcode) {
15904 case MOVDIRI32:
15905 case MOVDIRI32_EVEX:
15906 case MOVDIRI64:
15907 case MOVDIRI64_EVEX:
15908 return true;
15909 }
15910 return false;
15911}
15912
15913bool isSHUFPS(unsigned Opcode) {
15914 switch (Opcode) {
15915 case SHUFPSrmi:
15916 case SHUFPSrri:
15917 return true;
15918 }
15919 return false;
15920}
15921
15922bool isVFNMSUB231SS(unsigned Opcode) {
15923 switch (Opcode) {
15924 case VFNMSUB231SSZm_Int:
15925 case VFNMSUB231SSZmk_Int:
15926 case VFNMSUB231SSZmkz_Int:
15927 case VFNMSUB231SSZr_Int:
15928 case VFNMSUB231SSZrb_Int:
15929 case VFNMSUB231SSZrbk_Int:
15930 case VFNMSUB231SSZrbkz_Int:
15931 case VFNMSUB231SSZrk_Int:
15932 case VFNMSUB231SSZrkz_Int:
15933 case VFNMSUB231SSm_Int:
15934 case VFNMSUB231SSr_Int:
15935 return true;
15936 }
15937 return false;
15938}
15939
15940bool isVMWRITE(unsigned Opcode) {
15941 switch (Opcode) {
15942 case VMWRITE32rm:
15943 case VMWRITE32rr:
15944 case VMWRITE64rm:
15945 case VMWRITE64rr:
15946 return true;
15947 }
15948 return false;
15949}
15950
15951bool isVINSERTF128(unsigned Opcode) {
15952 switch (Opcode) {
15953 case VINSERTF128rmi:
15954 case VINSERTF128rri:
15955 return true;
15956 }
15957 return false;
15958}
15959
15960bool isFISUBR(unsigned Opcode) {
15961 switch (Opcode) {
15962 case SUBR_FI16m:
15963 case SUBR_FI32m:
15964 return true;
15965 }
15966 return false;
15967}
15968
15969bool isVINSERTI32X4(unsigned Opcode) {
15970 switch (Opcode) {
15971 case VINSERTI32X4Z256rmi:
15972 case VINSERTI32X4Z256rmik:
15973 case VINSERTI32X4Z256rmikz:
15974 case VINSERTI32X4Z256rri:
15975 case VINSERTI32X4Z256rrik:
15976 case VINSERTI32X4Z256rrikz:
15977 case VINSERTI32X4Zrmi:
15978 case VINSERTI32X4Zrmik:
15979 case VINSERTI32X4Zrmikz:
15980 case VINSERTI32X4Zrri:
15981 case VINSERTI32X4Zrrik:
15982 case VINSERTI32X4Zrrikz:
15983 return true;
15984 }
15985 return false;
15986}
15987
15988bool isVPSLLDQ(unsigned Opcode) {
15989 switch (Opcode) {
15990 case VPSLLDQYri:
15991 case VPSLLDQZ128mi:
15992 case VPSLLDQZ128ri:
15993 case VPSLLDQZ256mi:
15994 case VPSLLDQZ256ri:
15995 case VPSLLDQZmi:
15996 case VPSLLDQZri:
15997 case VPSLLDQri:
15998 return true;
15999 }
16000 return false;
16001}
16002
16003bool isPOPCNT(unsigned Opcode) {
16004 switch (Opcode) {
16005 case POPCNT16rm:
16006 case POPCNT16rm_EVEX:
16007 case POPCNT16rm_NF:
16008 case POPCNT16rr:
16009 case POPCNT16rr_EVEX:
16010 case POPCNT16rr_NF:
16011 case POPCNT32rm:
16012 case POPCNT32rm_EVEX:
16013 case POPCNT32rm_NF:
16014 case POPCNT32rr:
16015 case POPCNT32rr_EVEX:
16016 case POPCNT32rr_NF:
16017 case POPCNT64rm:
16018 case POPCNT64rm_EVEX:
16019 case POPCNT64rm_NF:
16020 case POPCNT64rr:
16021 case POPCNT64rr_EVEX:
16022 case POPCNT64rr_NF:
16023 return true;
16024 }
16025 return false;
16026}
16027
16028bool isVXORPD(unsigned Opcode) {
16029 switch (Opcode) {
16030 case VXORPDYrm:
16031 case VXORPDYrr:
16032 case VXORPDZ128rm:
16033 case VXORPDZ128rmb:
16034 case VXORPDZ128rmbk:
16035 case VXORPDZ128rmbkz:
16036 case VXORPDZ128rmk:
16037 case VXORPDZ128rmkz:
16038 case VXORPDZ128rr:
16039 case VXORPDZ128rrk:
16040 case VXORPDZ128rrkz:
16041 case VXORPDZ256rm:
16042 case VXORPDZ256rmb:
16043 case VXORPDZ256rmbk:
16044 case VXORPDZ256rmbkz:
16045 case VXORPDZ256rmk:
16046 case VXORPDZ256rmkz:
16047 case VXORPDZ256rr:
16048 case VXORPDZ256rrk:
16049 case VXORPDZ256rrkz:
16050 case VXORPDZrm:
16051 case VXORPDZrmb:
16052 case VXORPDZrmbk:
16053 case VXORPDZrmbkz:
16054 case VXORPDZrmk:
16055 case VXORPDZrmkz:
16056 case VXORPDZrr:
16057 case VXORPDZrrk:
16058 case VXORPDZrrkz:
16059 case VXORPDrm:
16060 case VXORPDrr:
16061 return true;
16062 }
16063 return false;
16064}
16065
16066bool isXLATB(unsigned Opcode) {
16067 return Opcode == XLAT;
16068}
16069
16070bool isDIV(unsigned Opcode) {
16071 switch (Opcode) {
16072 case DIV16m:
16073 case DIV16m_EVEX:
16074 case DIV16m_NF:
16075 case DIV16r:
16076 case DIV16r_EVEX:
16077 case DIV16r_NF:
16078 case DIV32m:
16079 case DIV32m_EVEX:
16080 case DIV32m_NF:
16081 case DIV32r:
16082 case DIV32r_EVEX:
16083 case DIV32r_NF:
16084 case DIV64m:
16085 case DIV64m_EVEX:
16086 case DIV64m_NF:
16087 case DIV64r:
16088 case DIV64r_EVEX:
16089 case DIV64r_NF:
16090 case DIV8m:
16091 case DIV8m_EVEX:
16092 case DIV8m_NF:
16093 case DIV8r:
16094 case DIV8r_EVEX:
16095 case DIV8r_NF:
16096 return true;
16097 }
16098 return false;
16099}
16100
16101bool isVPSHLDVQ(unsigned Opcode) {
16102 switch (Opcode) {
16103 case VPSHLDVQZ128m:
16104 case VPSHLDVQZ128mb:
16105 case VPSHLDVQZ128mbk:
16106 case VPSHLDVQZ128mbkz:
16107 case VPSHLDVQZ128mk:
16108 case VPSHLDVQZ128mkz:
16109 case VPSHLDVQZ128r:
16110 case VPSHLDVQZ128rk:
16111 case VPSHLDVQZ128rkz:
16112 case VPSHLDVQZ256m:
16113 case VPSHLDVQZ256mb:
16114 case VPSHLDVQZ256mbk:
16115 case VPSHLDVQZ256mbkz:
16116 case VPSHLDVQZ256mk:
16117 case VPSHLDVQZ256mkz:
16118 case VPSHLDVQZ256r:
16119 case VPSHLDVQZ256rk:
16120 case VPSHLDVQZ256rkz:
16121 case VPSHLDVQZm:
16122 case VPSHLDVQZmb:
16123 case VPSHLDVQZmbk:
16124 case VPSHLDVQZmbkz:
16125 case VPSHLDVQZmk:
16126 case VPSHLDVQZmkz:
16127 case VPSHLDVQZr:
16128 case VPSHLDVQZrk:
16129 case VPSHLDVQZrkz:
16130 return true;
16131 }
16132 return false;
16133}
16134
16135bool isMOVDDUP(unsigned Opcode) {
16136 switch (Opcode) {
16137 case MOVDDUPrm:
16138 case MOVDDUPrr:
16139 return true;
16140 }
16141 return false;
16142}
16143
16144bool isVMOVDQU64(unsigned Opcode) {
16145 switch (Opcode) {
16146 case VMOVDQU64Z128mr:
16147 case VMOVDQU64Z128mrk:
16148 case VMOVDQU64Z128rm:
16149 case VMOVDQU64Z128rmk:
16150 case VMOVDQU64Z128rmkz:
16151 case VMOVDQU64Z128rr:
16152 case VMOVDQU64Z128rr_REV:
16153 case VMOVDQU64Z128rrk:
16154 case VMOVDQU64Z128rrk_REV:
16155 case VMOVDQU64Z128rrkz:
16156 case VMOVDQU64Z128rrkz_REV:
16157 case VMOVDQU64Z256mr:
16158 case VMOVDQU64Z256mrk:
16159 case VMOVDQU64Z256rm:
16160 case VMOVDQU64Z256rmk:
16161 case VMOVDQU64Z256rmkz:
16162 case VMOVDQU64Z256rr:
16163 case VMOVDQU64Z256rr_REV:
16164 case VMOVDQU64Z256rrk:
16165 case VMOVDQU64Z256rrk_REV:
16166 case VMOVDQU64Z256rrkz:
16167 case VMOVDQU64Z256rrkz_REV:
16168 case VMOVDQU64Zmr:
16169 case VMOVDQU64Zmrk:
16170 case VMOVDQU64Zrm:
16171 case VMOVDQU64Zrmk:
16172 case VMOVDQU64Zrmkz:
16173 case VMOVDQU64Zrr:
16174 case VMOVDQU64Zrr_REV:
16175 case VMOVDQU64Zrrk:
16176 case VMOVDQU64Zrrk_REV:
16177 case VMOVDQU64Zrrkz:
16178 case VMOVDQU64Zrrkz_REV:
16179 return true;
16180 }
16181 return false;
16182}
16183
16184bool isVPCOMPRESSQ(unsigned Opcode) {
16185 switch (Opcode) {
16186 case VPCOMPRESSQZ128mr:
16187 case VPCOMPRESSQZ128mrk:
16188 case VPCOMPRESSQZ128rr:
16189 case VPCOMPRESSQZ128rrk:
16190 case VPCOMPRESSQZ128rrkz:
16191 case VPCOMPRESSQZ256mr:
16192 case VPCOMPRESSQZ256mrk:
16193 case VPCOMPRESSQZ256rr:
16194 case VPCOMPRESSQZ256rrk:
16195 case VPCOMPRESSQZ256rrkz:
16196 case VPCOMPRESSQZmr:
16197 case VPCOMPRESSQZmrk:
16198 case VPCOMPRESSQZrr:
16199 case VPCOMPRESSQZrrk:
16200 case VPCOMPRESSQZrrkz:
16201 return true;
16202 }
16203 return false;
16204}
16205
16206bool isVFMSUBADD132PD(unsigned Opcode) {
16207 switch (Opcode) {
16208 case VFMSUBADD132PDYm:
16209 case VFMSUBADD132PDYr:
16210 case VFMSUBADD132PDZ128m:
16211 case VFMSUBADD132PDZ128mb:
16212 case VFMSUBADD132PDZ128mbk:
16213 case VFMSUBADD132PDZ128mbkz:
16214 case VFMSUBADD132PDZ128mk:
16215 case VFMSUBADD132PDZ128mkz:
16216 case VFMSUBADD132PDZ128r:
16217 case VFMSUBADD132PDZ128rk:
16218 case VFMSUBADD132PDZ128rkz:
16219 case VFMSUBADD132PDZ256m:
16220 case VFMSUBADD132PDZ256mb:
16221 case VFMSUBADD132PDZ256mbk:
16222 case VFMSUBADD132PDZ256mbkz:
16223 case VFMSUBADD132PDZ256mk:
16224 case VFMSUBADD132PDZ256mkz:
16225 case VFMSUBADD132PDZ256r:
16226 case VFMSUBADD132PDZ256rk:
16227 case VFMSUBADD132PDZ256rkz:
16228 case VFMSUBADD132PDZm:
16229 case VFMSUBADD132PDZmb:
16230 case VFMSUBADD132PDZmbk:
16231 case VFMSUBADD132PDZmbkz:
16232 case VFMSUBADD132PDZmk:
16233 case VFMSUBADD132PDZmkz:
16234 case VFMSUBADD132PDZr:
16235 case VFMSUBADD132PDZrb:
16236 case VFMSUBADD132PDZrbk:
16237 case VFMSUBADD132PDZrbkz:
16238 case VFMSUBADD132PDZrk:
16239 case VFMSUBADD132PDZrkz:
16240 case VFMSUBADD132PDm:
16241 case VFMSUBADD132PDr:
16242 return true;
16243 }
16244 return false;
16245}
16246
16247bool isADDSD(unsigned Opcode) {
16248 switch (Opcode) {
16249 case ADDSDrm_Int:
16250 case ADDSDrr_Int:
16251 return true;
16252 }
16253 return false;
16254}
16255
16256bool isBLENDPD(unsigned Opcode) {
16257 switch (Opcode) {
16258 case BLENDPDrmi:
16259 case BLENDPDrri:
16260 return true;
16261 }
16262 return false;
16263}
16264
16265bool isVPERMILPD(unsigned Opcode) {
16266 switch (Opcode) {
16267 case VPERMILPDYmi:
16268 case VPERMILPDYri:
16269 case VPERMILPDYrm:
16270 case VPERMILPDYrr:
16271 case VPERMILPDZ128mbi:
16272 case VPERMILPDZ128mbik:
16273 case VPERMILPDZ128mbikz:
16274 case VPERMILPDZ128mi:
16275 case VPERMILPDZ128mik:
16276 case VPERMILPDZ128mikz:
16277 case VPERMILPDZ128ri:
16278 case VPERMILPDZ128rik:
16279 case VPERMILPDZ128rikz:
16280 case VPERMILPDZ128rm:
16281 case VPERMILPDZ128rmb:
16282 case VPERMILPDZ128rmbk:
16283 case VPERMILPDZ128rmbkz:
16284 case VPERMILPDZ128rmk:
16285 case VPERMILPDZ128rmkz:
16286 case VPERMILPDZ128rr:
16287 case VPERMILPDZ128rrk:
16288 case VPERMILPDZ128rrkz:
16289 case VPERMILPDZ256mbi:
16290 case VPERMILPDZ256mbik:
16291 case VPERMILPDZ256mbikz:
16292 case VPERMILPDZ256mi:
16293 case VPERMILPDZ256mik:
16294 case VPERMILPDZ256mikz:
16295 case VPERMILPDZ256ri:
16296 case VPERMILPDZ256rik:
16297 case VPERMILPDZ256rikz:
16298 case VPERMILPDZ256rm:
16299 case VPERMILPDZ256rmb:
16300 case VPERMILPDZ256rmbk:
16301 case VPERMILPDZ256rmbkz:
16302 case VPERMILPDZ256rmk:
16303 case VPERMILPDZ256rmkz:
16304 case VPERMILPDZ256rr:
16305 case VPERMILPDZ256rrk:
16306 case VPERMILPDZ256rrkz:
16307 case VPERMILPDZmbi:
16308 case VPERMILPDZmbik:
16309 case VPERMILPDZmbikz:
16310 case VPERMILPDZmi:
16311 case VPERMILPDZmik:
16312 case VPERMILPDZmikz:
16313 case VPERMILPDZri:
16314 case VPERMILPDZrik:
16315 case VPERMILPDZrikz:
16316 case VPERMILPDZrm:
16317 case VPERMILPDZrmb:
16318 case VPERMILPDZrmbk:
16319 case VPERMILPDZrmbkz:
16320 case VPERMILPDZrmk:
16321 case VPERMILPDZrmkz:
16322 case VPERMILPDZrr:
16323 case VPERMILPDZrrk:
16324 case VPERMILPDZrrkz:
16325 case VPERMILPDmi:
16326 case VPERMILPDri:
16327 case VPERMILPDrm:
16328 case VPERMILPDrr:
16329 return true;
16330 }
16331 return false;
16332}
16333
16334bool isPMADDUBSW(unsigned Opcode) {
16335 switch (Opcode) {
16336 case MMX_PMADDUBSWrm:
16337 case MMX_PMADDUBSWrr:
16338 case PMADDUBSWrm:
16339 case PMADDUBSWrr:
16340 return true;
16341 }
16342 return false;
16343}
16344
16345bool isPOPFD(unsigned Opcode) {
16346 return Opcode == POPF32;
16347}
16348
16349bool isCMPSW(unsigned Opcode) {
16350 return Opcode == CMPSW;
16351}
16352
16353bool isLDMXCSR(unsigned Opcode) {
16354 return Opcode == LDMXCSR;
16355}
16356
16357bool isVMULPS(unsigned Opcode) {
16358 switch (Opcode) {
16359 case VMULPSYrm:
16360 case VMULPSYrr:
16361 case VMULPSZ128rm:
16362 case VMULPSZ128rmb:
16363 case VMULPSZ128rmbk:
16364 case VMULPSZ128rmbkz:
16365 case VMULPSZ128rmk:
16366 case VMULPSZ128rmkz:
16367 case VMULPSZ128rr:
16368 case VMULPSZ128rrk:
16369 case VMULPSZ128rrkz:
16370 case VMULPSZ256rm:
16371 case VMULPSZ256rmb:
16372 case VMULPSZ256rmbk:
16373 case VMULPSZ256rmbkz:
16374 case VMULPSZ256rmk:
16375 case VMULPSZ256rmkz:
16376 case VMULPSZ256rr:
16377 case VMULPSZ256rrk:
16378 case VMULPSZ256rrkz:
16379 case VMULPSZrm:
16380 case VMULPSZrmb:
16381 case VMULPSZrmbk:
16382 case VMULPSZrmbkz:
16383 case VMULPSZrmk:
16384 case VMULPSZrmkz:
16385 case VMULPSZrr:
16386 case VMULPSZrrb:
16387 case VMULPSZrrbk:
16388 case VMULPSZrrbkz:
16389 case VMULPSZrrk:
16390 case VMULPSZrrkz:
16391 case VMULPSrm:
16392 case VMULPSrr:
16393 return true;
16394 }
16395 return false;
16396}
16397
16398bool isVROUNDSD(unsigned Opcode) {
16399 switch (Opcode) {
16400 case VROUNDSDmi_Int:
16401 case VROUNDSDri_Int:
16402 return true;
16403 }
16404 return false;
16405}
16406
16407bool isVFMADD132PD(unsigned Opcode) {
16408 switch (Opcode) {
16409 case VFMADD132PDYm:
16410 case VFMADD132PDYr:
16411 case VFMADD132PDZ128m:
16412 case VFMADD132PDZ128mb:
16413 case VFMADD132PDZ128mbk:
16414 case VFMADD132PDZ128mbkz:
16415 case VFMADD132PDZ128mk:
16416 case VFMADD132PDZ128mkz:
16417 case VFMADD132PDZ128r:
16418 case VFMADD132PDZ128rk:
16419 case VFMADD132PDZ128rkz:
16420 case VFMADD132PDZ256m:
16421 case VFMADD132PDZ256mb:
16422 case VFMADD132PDZ256mbk:
16423 case VFMADD132PDZ256mbkz:
16424 case VFMADD132PDZ256mk:
16425 case VFMADD132PDZ256mkz:
16426 case VFMADD132PDZ256r:
16427 case VFMADD132PDZ256rk:
16428 case VFMADD132PDZ256rkz:
16429 case VFMADD132PDZm:
16430 case VFMADD132PDZmb:
16431 case VFMADD132PDZmbk:
16432 case VFMADD132PDZmbkz:
16433 case VFMADD132PDZmk:
16434 case VFMADD132PDZmkz:
16435 case VFMADD132PDZr:
16436 case VFMADD132PDZrb:
16437 case VFMADD132PDZrbk:
16438 case VFMADD132PDZrbkz:
16439 case VFMADD132PDZrk:
16440 case VFMADD132PDZrkz:
16441 case VFMADD132PDm:
16442 case VFMADD132PDr:
16443 return true;
16444 }
16445 return false;
16446}
16447
16448bool isVPANDQ(unsigned Opcode) {
16449 switch (Opcode) {
16450 case VPANDQZ128rm:
16451 case VPANDQZ128rmb:
16452 case VPANDQZ128rmbk:
16453 case VPANDQZ128rmbkz:
16454 case VPANDQZ128rmk:
16455 case VPANDQZ128rmkz:
16456 case VPANDQZ128rr:
16457 case VPANDQZ128rrk:
16458 case VPANDQZ128rrkz:
16459 case VPANDQZ256rm:
16460 case VPANDQZ256rmb:
16461 case VPANDQZ256rmbk:
16462 case VPANDQZ256rmbkz:
16463 case VPANDQZ256rmk:
16464 case VPANDQZ256rmkz:
16465 case VPANDQZ256rr:
16466 case VPANDQZ256rrk:
16467 case VPANDQZ256rrkz:
16468 case VPANDQZrm:
16469 case VPANDQZrmb:
16470 case VPANDQZrmbk:
16471 case VPANDQZrmbkz:
16472 case VPANDQZrmk:
16473 case VPANDQZrmkz:
16474 case VPANDQZrr:
16475 case VPANDQZrrk:
16476 case VPANDQZrrkz:
16477 return true;
16478 }
16479 return false;
16480}
16481
16482bool isVPSRAQ(unsigned Opcode) {
16483 switch (Opcode) {
16484 case VPSRAQZ128mbi:
16485 case VPSRAQZ128mbik:
16486 case VPSRAQZ128mbikz:
16487 case VPSRAQZ128mi:
16488 case VPSRAQZ128mik:
16489 case VPSRAQZ128mikz:
16490 case VPSRAQZ128ri:
16491 case VPSRAQZ128rik:
16492 case VPSRAQZ128rikz:
16493 case VPSRAQZ128rm:
16494 case VPSRAQZ128rmk:
16495 case VPSRAQZ128rmkz:
16496 case VPSRAQZ128rr:
16497 case VPSRAQZ128rrk:
16498 case VPSRAQZ128rrkz:
16499 case VPSRAQZ256mbi:
16500 case VPSRAQZ256mbik:
16501 case VPSRAQZ256mbikz:
16502 case VPSRAQZ256mi:
16503 case VPSRAQZ256mik:
16504 case VPSRAQZ256mikz:
16505 case VPSRAQZ256ri:
16506 case VPSRAQZ256rik:
16507 case VPSRAQZ256rikz:
16508 case VPSRAQZ256rm:
16509 case VPSRAQZ256rmk:
16510 case VPSRAQZ256rmkz:
16511 case VPSRAQZ256rr:
16512 case VPSRAQZ256rrk:
16513 case VPSRAQZ256rrkz:
16514 case VPSRAQZmbi:
16515 case VPSRAQZmbik:
16516 case VPSRAQZmbikz:
16517 case VPSRAQZmi:
16518 case VPSRAQZmik:
16519 case VPSRAQZmikz:
16520 case VPSRAQZri:
16521 case VPSRAQZrik:
16522 case VPSRAQZrikz:
16523 case VPSRAQZrm:
16524 case VPSRAQZrmk:
16525 case VPSRAQZrmkz:
16526 case VPSRAQZrr:
16527 case VPSRAQZrrk:
16528 case VPSRAQZrrkz:
16529 return true;
16530 }
16531 return false;
16532}
16533
16534bool isVCOMISD(unsigned Opcode) {
16535 switch (Opcode) {
16536 case VCOMISDZrm:
16537 case VCOMISDZrr:
16538 case VCOMISDZrrb:
16539 case VCOMISDrm:
16540 case VCOMISDrr:
16541 return true;
16542 }
16543 return false;
16544}
16545
16546bool isVCVTBIASPH2BF8(unsigned Opcode) {
16547 switch (Opcode) {
16548 case VCVTBIASPH2BF8Z128rm:
16549 case VCVTBIASPH2BF8Z128rmb:
16550 case VCVTBIASPH2BF8Z128rmbk:
16551 case VCVTBIASPH2BF8Z128rmbkz:
16552 case VCVTBIASPH2BF8Z128rmk:
16553 case VCVTBIASPH2BF8Z128rmkz:
16554 case VCVTBIASPH2BF8Z128rr:
16555 case VCVTBIASPH2BF8Z128rrk:
16556 case VCVTBIASPH2BF8Z128rrkz:
16557 case VCVTBIASPH2BF8Z256rm:
16558 case VCVTBIASPH2BF8Z256rmb:
16559 case VCVTBIASPH2BF8Z256rmbk:
16560 case VCVTBIASPH2BF8Z256rmbkz:
16561 case VCVTBIASPH2BF8Z256rmk:
16562 case VCVTBIASPH2BF8Z256rmkz:
16563 case VCVTBIASPH2BF8Z256rr:
16564 case VCVTBIASPH2BF8Z256rrk:
16565 case VCVTBIASPH2BF8Z256rrkz:
16566 case VCVTBIASPH2BF8Zrm:
16567 case VCVTBIASPH2BF8Zrmb:
16568 case VCVTBIASPH2BF8Zrmbk:
16569 case VCVTBIASPH2BF8Zrmbkz:
16570 case VCVTBIASPH2BF8Zrmk:
16571 case VCVTBIASPH2BF8Zrmkz:
16572 case VCVTBIASPH2BF8Zrr:
16573 case VCVTBIASPH2BF8Zrrk:
16574 case VCVTBIASPH2BF8Zrrkz:
16575 return true;
16576 }
16577 return false;
16578}
16579
16580bool isFFREEP(unsigned Opcode) {
16581 return Opcode == FFREEP;
16582}
16583
16584bool isVFNMADD213PD(unsigned Opcode) {
16585 switch (Opcode) {
16586 case VFNMADD213PDYm:
16587 case VFNMADD213PDYr:
16588 case VFNMADD213PDZ128m:
16589 case VFNMADD213PDZ128mb:
16590 case VFNMADD213PDZ128mbk:
16591 case VFNMADD213PDZ128mbkz:
16592 case VFNMADD213PDZ128mk:
16593 case VFNMADD213PDZ128mkz:
16594 case VFNMADD213PDZ128r:
16595 case VFNMADD213PDZ128rk:
16596 case VFNMADD213PDZ128rkz:
16597 case VFNMADD213PDZ256m:
16598 case VFNMADD213PDZ256mb:
16599 case VFNMADD213PDZ256mbk:
16600 case VFNMADD213PDZ256mbkz:
16601 case VFNMADD213PDZ256mk:
16602 case VFNMADD213PDZ256mkz:
16603 case VFNMADD213PDZ256r:
16604 case VFNMADD213PDZ256rk:
16605 case VFNMADD213PDZ256rkz:
16606 case VFNMADD213PDZm:
16607 case VFNMADD213PDZmb:
16608 case VFNMADD213PDZmbk:
16609 case VFNMADD213PDZmbkz:
16610 case VFNMADD213PDZmk:
16611 case VFNMADD213PDZmkz:
16612 case VFNMADD213PDZr:
16613 case VFNMADD213PDZrb:
16614 case VFNMADD213PDZrbk:
16615 case VFNMADD213PDZrbkz:
16616 case VFNMADD213PDZrk:
16617 case VFNMADD213PDZrkz:
16618 case VFNMADD213PDm:
16619 case VFNMADD213PDr:
16620 return true;
16621 }
16622 return false;
16623}
16624
16625bool isVCMPPD(unsigned Opcode) {
16626 switch (Opcode) {
16627 case VCMPPDYrmi:
16628 case VCMPPDYrri:
16629 case VCMPPDZ128rmbi:
16630 case VCMPPDZ128rmbik:
16631 case VCMPPDZ128rmi:
16632 case VCMPPDZ128rmik:
16633 case VCMPPDZ128rri:
16634 case VCMPPDZ128rrik:
16635 case VCMPPDZ256rmbi:
16636 case VCMPPDZ256rmbik:
16637 case VCMPPDZ256rmi:
16638 case VCMPPDZ256rmik:
16639 case VCMPPDZ256rri:
16640 case VCMPPDZ256rrik:
16641 case VCMPPDZrmbi:
16642 case VCMPPDZrmbik:
16643 case VCMPPDZrmi:
16644 case VCMPPDZrmik:
16645 case VCMPPDZrri:
16646 case VCMPPDZrrib:
16647 case VCMPPDZrribk:
16648 case VCMPPDZrrik:
16649 case VCMPPDrmi:
16650 case VCMPPDrri:
16651 return true;
16652 }
16653 return false;
16654}
16655
16656bool isVFNMSUB132PH(unsigned Opcode) {
16657 switch (Opcode) {
16658 case VFNMSUB132PHZ128m:
16659 case VFNMSUB132PHZ128mb:
16660 case VFNMSUB132PHZ128mbk:
16661 case VFNMSUB132PHZ128mbkz:
16662 case VFNMSUB132PHZ128mk:
16663 case VFNMSUB132PHZ128mkz:
16664 case VFNMSUB132PHZ128r:
16665 case VFNMSUB132PHZ128rk:
16666 case VFNMSUB132PHZ128rkz:
16667 case VFNMSUB132PHZ256m:
16668 case VFNMSUB132PHZ256mb:
16669 case VFNMSUB132PHZ256mbk:
16670 case VFNMSUB132PHZ256mbkz:
16671 case VFNMSUB132PHZ256mk:
16672 case VFNMSUB132PHZ256mkz:
16673 case VFNMSUB132PHZ256r:
16674 case VFNMSUB132PHZ256rk:
16675 case VFNMSUB132PHZ256rkz:
16676 case VFNMSUB132PHZm:
16677 case VFNMSUB132PHZmb:
16678 case VFNMSUB132PHZmbk:
16679 case VFNMSUB132PHZmbkz:
16680 case VFNMSUB132PHZmk:
16681 case VFNMSUB132PHZmkz:
16682 case VFNMSUB132PHZr:
16683 case VFNMSUB132PHZrb:
16684 case VFNMSUB132PHZrbk:
16685 case VFNMSUB132PHZrbkz:
16686 case VFNMSUB132PHZrk:
16687 case VFNMSUB132PHZrkz:
16688 return true;
16689 }
16690 return false;
16691}
16692
16693bool isVPHADDBW(unsigned Opcode) {
16694 switch (Opcode) {
16695 case VPHADDBWrm:
16696 case VPHADDBWrr:
16697 return true;
16698 }
16699 return false;
16700}
16701
16702bool isVPPERM(unsigned Opcode) {
16703 switch (Opcode) {
16704 case VPPERMrmr:
16705 case VPPERMrrm:
16706 case VPPERMrrr:
16707 case VPPERMrrr_REV:
16708 return true;
16709 }
16710 return false;
16711}
16712
16713bool isVCVTPS2PD(unsigned Opcode) {
16714 switch (Opcode) {
16715 case VCVTPS2PDYrm:
16716 case VCVTPS2PDYrr:
16717 case VCVTPS2PDZ128rm:
16718 case VCVTPS2PDZ128rmb:
16719 case VCVTPS2PDZ128rmbk:
16720 case VCVTPS2PDZ128rmbkz:
16721 case VCVTPS2PDZ128rmk:
16722 case VCVTPS2PDZ128rmkz:
16723 case VCVTPS2PDZ128rr:
16724 case VCVTPS2PDZ128rrk:
16725 case VCVTPS2PDZ128rrkz:
16726 case VCVTPS2PDZ256rm:
16727 case VCVTPS2PDZ256rmb:
16728 case VCVTPS2PDZ256rmbk:
16729 case VCVTPS2PDZ256rmbkz:
16730 case VCVTPS2PDZ256rmk:
16731 case VCVTPS2PDZ256rmkz:
16732 case VCVTPS2PDZ256rr:
16733 case VCVTPS2PDZ256rrk:
16734 case VCVTPS2PDZ256rrkz:
16735 case VCVTPS2PDZrm:
16736 case VCVTPS2PDZrmb:
16737 case VCVTPS2PDZrmbk:
16738 case VCVTPS2PDZrmbkz:
16739 case VCVTPS2PDZrmk:
16740 case VCVTPS2PDZrmkz:
16741 case VCVTPS2PDZrr:
16742 case VCVTPS2PDZrrb:
16743 case VCVTPS2PDZrrbk:
16744 case VCVTPS2PDZrrbkz:
16745 case VCVTPS2PDZrrk:
16746 case VCVTPS2PDZrrkz:
16747 case VCVTPS2PDrm:
16748 case VCVTPS2PDrr:
16749 return true;
16750 }
16751 return false;
16752}
16753
16754bool isCBW(unsigned Opcode) {
16755 return Opcode == CBW;
16756}
16757
16758bool isVMOVUPS(unsigned Opcode) {
16759 switch (Opcode) {
16760 case VMOVUPSYmr:
16761 case VMOVUPSYrm:
16762 case VMOVUPSYrr:
16763 case VMOVUPSYrr_REV:
16764 case VMOVUPSZ128mr:
16765 case VMOVUPSZ128mrk:
16766 case VMOVUPSZ128rm:
16767 case VMOVUPSZ128rmk:
16768 case VMOVUPSZ128rmkz:
16769 case VMOVUPSZ128rr:
16770 case VMOVUPSZ128rr_REV:
16771 case VMOVUPSZ128rrk:
16772 case VMOVUPSZ128rrk_REV:
16773 case VMOVUPSZ128rrkz:
16774 case VMOVUPSZ128rrkz_REV:
16775 case VMOVUPSZ256mr:
16776 case VMOVUPSZ256mrk:
16777 case VMOVUPSZ256rm:
16778 case VMOVUPSZ256rmk:
16779 case VMOVUPSZ256rmkz:
16780 case VMOVUPSZ256rr:
16781 case VMOVUPSZ256rr_REV:
16782 case VMOVUPSZ256rrk:
16783 case VMOVUPSZ256rrk_REV:
16784 case VMOVUPSZ256rrkz:
16785 case VMOVUPSZ256rrkz_REV:
16786 case VMOVUPSZmr:
16787 case VMOVUPSZmrk:
16788 case VMOVUPSZrm:
16789 case VMOVUPSZrmk:
16790 case VMOVUPSZrmkz:
16791 case VMOVUPSZrr:
16792 case VMOVUPSZrr_REV:
16793 case VMOVUPSZrrk:
16794 case VMOVUPSZrrk_REV:
16795 case VMOVUPSZrrkz:
16796 case VMOVUPSZrrkz_REV:
16797 case VMOVUPSmr:
16798 case VMOVUPSrm:
16799 case VMOVUPSrr:
16800 case VMOVUPSrr_REV:
16801 return true;
16802 }
16803 return false;
16804}
16805
16806bool isVPMAXUQ(unsigned Opcode) {
16807 switch (Opcode) {
16808 case VPMAXUQZ128rm:
16809 case VPMAXUQZ128rmb:
16810 case VPMAXUQZ128rmbk:
16811 case VPMAXUQZ128rmbkz:
16812 case VPMAXUQZ128rmk:
16813 case VPMAXUQZ128rmkz:
16814 case VPMAXUQZ128rr:
16815 case VPMAXUQZ128rrk:
16816 case VPMAXUQZ128rrkz:
16817 case VPMAXUQZ256rm:
16818 case VPMAXUQZ256rmb:
16819 case VPMAXUQZ256rmbk:
16820 case VPMAXUQZ256rmbkz:
16821 case VPMAXUQZ256rmk:
16822 case VPMAXUQZ256rmkz:
16823 case VPMAXUQZ256rr:
16824 case VPMAXUQZ256rrk:
16825 case VPMAXUQZ256rrkz:
16826 case VPMAXUQZrm:
16827 case VPMAXUQZrmb:
16828 case VPMAXUQZrmbk:
16829 case VPMAXUQZrmbkz:
16830 case VPMAXUQZrmk:
16831 case VPMAXUQZrmkz:
16832 case VPMAXUQZrr:
16833 case VPMAXUQZrrk:
16834 case VPMAXUQZrrkz:
16835 return true;
16836 }
16837 return false;
16838}
16839
16840bool isWRSSQ(unsigned Opcode) {
16841 switch (Opcode) {
16842 case WRSSQ:
16843 case WRSSQ_EVEX:
16844 return true;
16845 }
16846 return false;
16847}
16848
16849bool isPACKUSDW(unsigned Opcode) {
16850 switch (Opcode) {
16851 case PACKUSDWrm:
16852 case PACKUSDWrr:
16853 return true;
16854 }
16855 return false;
16856}
16857
16858bool isVCVTTBF162IBS(unsigned Opcode) {
16859 switch (Opcode) {
16860 case VCVTTBF162IBSZ128rm:
16861 case VCVTTBF162IBSZ128rmb:
16862 case VCVTTBF162IBSZ128rmbk:
16863 case VCVTTBF162IBSZ128rmbkz:
16864 case VCVTTBF162IBSZ128rmk:
16865 case VCVTTBF162IBSZ128rmkz:
16866 case VCVTTBF162IBSZ128rr:
16867 case VCVTTBF162IBSZ128rrk:
16868 case VCVTTBF162IBSZ128rrkz:
16869 case VCVTTBF162IBSZ256rm:
16870 case VCVTTBF162IBSZ256rmb:
16871 case VCVTTBF162IBSZ256rmbk:
16872 case VCVTTBF162IBSZ256rmbkz:
16873 case VCVTTBF162IBSZ256rmk:
16874 case VCVTTBF162IBSZ256rmkz:
16875 case VCVTTBF162IBSZ256rr:
16876 case VCVTTBF162IBSZ256rrk:
16877 case VCVTTBF162IBSZ256rrkz:
16878 case VCVTTBF162IBSZrm:
16879 case VCVTTBF162IBSZrmb:
16880 case VCVTTBF162IBSZrmbk:
16881 case VCVTTBF162IBSZrmbkz:
16882 case VCVTTBF162IBSZrmk:
16883 case VCVTTBF162IBSZrmkz:
16884 case VCVTTBF162IBSZrr:
16885 case VCVTTBF162IBSZrrk:
16886 case VCVTTBF162IBSZrrkz:
16887 return true;
16888 }
16889 return false;
16890}
16891
16892bool isXBEGIN(unsigned Opcode) {
16893 switch (Opcode) {
16894 case XBEGIN_2:
16895 case XBEGIN_4:
16896 return true;
16897 }
16898 return false;
16899}
16900
16901bool isVCVTPD2UQQ(unsigned Opcode) {
16902 switch (Opcode) {
16903 case VCVTPD2UQQZ128rm:
16904 case VCVTPD2UQQZ128rmb:
16905 case VCVTPD2UQQZ128rmbk:
16906 case VCVTPD2UQQZ128rmbkz:
16907 case VCVTPD2UQQZ128rmk:
16908 case VCVTPD2UQQZ128rmkz:
16909 case VCVTPD2UQQZ128rr:
16910 case VCVTPD2UQQZ128rrk:
16911 case VCVTPD2UQQZ128rrkz:
16912 case VCVTPD2UQQZ256rm:
16913 case VCVTPD2UQQZ256rmb:
16914 case VCVTPD2UQQZ256rmbk:
16915 case VCVTPD2UQQZ256rmbkz:
16916 case VCVTPD2UQQZ256rmk:
16917 case VCVTPD2UQQZ256rmkz:
16918 case VCVTPD2UQQZ256rr:
16919 case VCVTPD2UQQZ256rrk:
16920 case VCVTPD2UQQZ256rrkz:
16921 case VCVTPD2UQQZrm:
16922 case VCVTPD2UQQZrmb:
16923 case VCVTPD2UQQZrmbk:
16924 case VCVTPD2UQQZrmbkz:
16925 case VCVTPD2UQQZrmk:
16926 case VCVTPD2UQQZrmkz:
16927 case VCVTPD2UQQZrr:
16928 case VCVTPD2UQQZrrb:
16929 case VCVTPD2UQQZrrbk:
16930 case VCVTPD2UQQZrrbkz:
16931 case VCVTPD2UQQZrrk:
16932 case VCVTPD2UQQZrrkz:
16933 return true;
16934 }
16935 return false;
16936}
16937
16938bool isFCMOVB(unsigned Opcode) {
16939 return Opcode == CMOVB_F;
16940}
16941
16942bool isNOP(unsigned Opcode) {
16943 switch (Opcode) {
16944 case NOOP:
16945 case NOOPL:
16946 case NOOPLr:
16947 case NOOPQ:
16948 case NOOPQr:
16949 case NOOPW:
16950 case NOOPWr:
16951 return true;
16952 }
16953 return false;
16954}
16955
16956bool isVPABSQ(unsigned Opcode) {
16957 switch (Opcode) {
16958 case VPABSQZ128rm:
16959 case VPABSQZ128rmb:
16960 case VPABSQZ128rmbk:
16961 case VPABSQZ128rmbkz:
16962 case VPABSQZ128rmk:
16963 case VPABSQZ128rmkz:
16964 case VPABSQZ128rr:
16965 case VPABSQZ128rrk:
16966 case VPABSQZ128rrkz:
16967 case VPABSQZ256rm:
16968 case VPABSQZ256rmb:
16969 case VPABSQZ256rmbk:
16970 case VPABSQZ256rmbkz:
16971 case VPABSQZ256rmk:
16972 case VPABSQZ256rmkz:
16973 case VPABSQZ256rr:
16974 case VPABSQZ256rrk:
16975 case VPABSQZ256rrkz:
16976 case VPABSQZrm:
16977 case VPABSQZrmb:
16978 case VPABSQZrmbk:
16979 case VPABSQZrmbkz:
16980 case VPABSQZrmk:
16981 case VPABSQZrmkz:
16982 case VPABSQZrr:
16983 case VPABSQZrrk:
16984 case VPABSQZrrkz:
16985 return true;
16986 }
16987 return false;
16988}
16989
16990bool isVTESTPS(unsigned Opcode) {
16991 switch (Opcode) {
16992 case VTESTPSYrm:
16993 case VTESTPSYrr:
16994 case VTESTPSrm:
16995 case VTESTPSrr:
16996 return true;
16997 }
16998 return false;
16999}
17000
17001bool isPHSUBW(unsigned Opcode) {
17002 switch (Opcode) {
17003 case MMX_PHSUBWrm:
17004 case MMX_PHSUBWrr:
17005 case PHSUBWrm:
17006 case PHSUBWrr:
17007 return true;
17008 }
17009 return false;
17010}
17011
17012bool isPUSH2P(unsigned Opcode) {
17013 return Opcode == PUSH2P;
17014}
17015
17016bool isFISTTP(unsigned Opcode) {
17017 switch (Opcode) {
17018 case ISTT_FP16m:
17019 case ISTT_FP32m:
17020 case ISTT_FP64m:
17021 return true;
17022 }
17023 return false;
17024}
17025
17026bool isCFCMOVCC(unsigned Opcode) {
17027 switch (Opcode) {
17028 case CFCMOV16mr:
17029 case CFCMOV16rm:
17030 case CFCMOV16rm_ND:
17031 case CFCMOV16rr:
17032 case CFCMOV16rr_ND:
17033 case CFCMOV16rr_REV:
17034 case CFCMOV32mr:
17035 case CFCMOV32rm:
17036 case CFCMOV32rm_ND:
17037 case CFCMOV32rr:
17038 case CFCMOV32rr_ND:
17039 case CFCMOV32rr_REV:
17040 case CFCMOV64mr:
17041 case CFCMOV64rm:
17042 case CFCMOV64rm_ND:
17043 case CFCMOV64rr:
17044 case CFCMOV64rr_ND:
17045 case CFCMOV64rr_REV:
17046 return true;
17047 }
17048 return false;
17049}
17050
17051bool isVPINSRD(unsigned Opcode) {
17052 switch (Opcode) {
17053 case VPINSRDZrmi:
17054 case VPINSRDZrri:
17055 case VPINSRDrmi:
17056 case VPINSRDrri:
17057 return true;
17058 }
17059 return false;
17060}
17061
17062bool isPCMPESTRM(unsigned Opcode) {
17063 switch (Opcode) {
17064 case PCMPESTRMrmi:
17065 case PCMPESTRMrri:
17066 return true;
17067 }
17068 return false;
17069}
17070
17071bool isVFNMSUB213PS(unsigned Opcode) {
17072 switch (Opcode) {
17073 case VFNMSUB213PSYm:
17074 case VFNMSUB213PSYr:
17075 case VFNMSUB213PSZ128m:
17076 case VFNMSUB213PSZ128mb:
17077 case VFNMSUB213PSZ128mbk:
17078 case VFNMSUB213PSZ128mbkz:
17079 case VFNMSUB213PSZ128mk:
17080 case VFNMSUB213PSZ128mkz:
17081 case VFNMSUB213PSZ128r:
17082 case VFNMSUB213PSZ128rk:
17083 case VFNMSUB213PSZ128rkz:
17084 case VFNMSUB213PSZ256m:
17085 case VFNMSUB213PSZ256mb:
17086 case VFNMSUB213PSZ256mbk:
17087 case VFNMSUB213PSZ256mbkz:
17088 case VFNMSUB213PSZ256mk:
17089 case VFNMSUB213PSZ256mkz:
17090 case VFNMSUB213PSZ256r:
17091 case VFNMSUB213PSZ256rk:
17092 case VFNMSUB213PSZ256rkz:
17093 case VFNMSUB213PSZm:
17094 case VFNMSUB213PSZmb:
17095 case VFNMSUB213PSZmbk:
17096 case VFNMSUB213PSZmbkz:
17097 case VFNMSUB213PSZmk:
17098 case VFNMSUB213PSZmkz:
17099 case VFNMSUB213PSZr:
17100 case VFNMSUB213PSZrb:
17101 case VFNMSUB213PSZrbk:
17102 case VFNMSUB213PSZrbkz:
17103 case VFNMSUB213PSZrk:
17104 case VFNMSUB213PSZrkz:
17105 case VFNMSUB213PSm:
17106 case VFNMSUB213PSr:
17107 return true;
17108 }
17109 return false;
17110}
17111
17112bool isPHSUBD(unsigned Opcode) {
17113 switch (Opcode) {
17114 case MMX_PHSUBDrm:
17115 case MMX_PHSUBDrr:
17116 case PHSUBDrm:
17117 case PHSUBDrr:
17118 return true;
17119 }
17120 return false;
17121}
17122
17123bool isVCVTTPD2DQS(unsigned Opcode) {
17124 switch (Opcode) {
17125 case VCVTTPD2DQSZ128rm:
17126 case VCVTTPD2DQSZ128rmb:
17127 case VCVTTPD2DQSZ128rmbk:
17128 case VCVTTPD2DQSZ128rmbkz:
17129 case VCVTTPD2DQSZ128rmk:
17130 case VCVTTPD2DQSZ128rmkz:
17131 case VCVTTPD2DQSZ128rr:
17132 case VCVTTPD2DQSZ128rrk:
17133 case VCVTTPD2DQSZ128rrkz:
17134 case VCVTTPD2DQSZ256rm:
17135 case VCVTTPD2DQSZ256rmb:
17136 case VCVTTPD2DQSZ256rmbk:
17137 case VCVTTPD2DQSZ256rmbkz:
17138 case VCVTTPD2DQSZ256rmk:
17139 case VCVTTPD2DQSZ256rmkz:
17140 case VCVTTPD2DQSZ256rr:
17141 case VCVTTPD2DQSZ256rrb:
17142 case VCVTTPD2DQSZ256rrbk:
17143 case VCVTTPD2DQSZ256rrbkz:
17144 case VCVTTPD2DQSZ256rrk:
17145 case VCVTTPD2DQSZ256rrkz:
17146 case VCVTTPD2DQSZrm:
17147 case VCVTTPD2DQSZrmb:
17148 case VCVTTPD2DQSZrmbk:
17149 case VCVTTPD2DQSZrmbkz:
17150 case VCVTTPD2DQSZrmk:
17151 case VCVTTPD2DQSZrmkz:
17152 case VCVTTPD2DQSZrr:
17153 case VCVTTPD2DQSZrrb:
17154 case VCVTTPD2DQSZrrbk:
17155 case VCVTTPD2DQSZrrbkz:
17156 case VCVTTPD2DQSZrrk:
17157 case VCVTTPD2DQSZrrkz:
17158 return true;
17159 }
17160 return false;
17161}
17162
17163bool isSLDT(unsigned Opcode) {
17164 switch (Opcode) {
17165 case SLDT16m:
17166 case SLDT16r:
17167 case SLDT32r:
17168 case SLDT64r:
17169 return true;
17170 }
17171 return false;
17172}
17173
17174bool isVHADDPS(unsigned Opcode) {
17175 switch (Opcode) {
17176 case VHADDPSYrm:
17177 case VHADDPSYrr:
17178 case VHADDPSrm:
17179 case VHADDPSrr:
17180 return true;
17181 }
17182 return false;
17183}
17184
17185bool isVMOVNTDQ(unsigned Opcode) {
17186 switch (Opcode) {
17187 case VMOVNTDQYmr:
17188 case VMOVNTDQZ128mr:
17189 case VMOVNTDQZ256mr:
17190 case VMOVNTDQZmr:
17191 case VMOVNTDQmr:
17192 return true;
17193 }
17194 return false;
17195}
17196
17197bool isVPMINSD(unsigned Opcode) {
17198 switch (Opcode) {
17199 case VPMINSDYrm:
17200 case VPMINSDYrr:
17201 case VPMINSDZ128rm:
17202 case VPMINSDZ128rmb:
17203 case VPMINSDZ128rmbk:
17204 case VPMINSDZ128rmbkz:
17205 case VPMINSDZ128rmk:
17206 case VPMINSDZ128rmkz:
17207 case VPMINSDZ128rr:
17208 case VPMINSDZ128rrk:
17209 case VPMINSDZ128rrkz:
17210 case VPMINSDZ256rm:
17211 case VPMINSDZ256rmb:
17212 case VPMINSDZ256rmbk:
17213 case VPMINSDZ256rmbkz:
17214 case VPMINSDZ256rmk:
17215 case VPMINSDZ256rmkz:
17216 case VPMINSDZ256rr:
17217 case VPMINSDZ256rrk:
17218 case VPMINSDZ256rrkz:
17219 case VPMINSDZrm:
17220 case VPMINSDZrmb:
17221 case VPMINSDZrmbk:
17222 case VPMINSDZrmbkz:
17223 case VPMINSDZrmk:
17224 case VPMINSDZrmkz:
17225 case VPMINSDZrr:
17226 case VPMINSDZrrk:
17227 case VPMINSDZrrkz:
17228 case VPMINSDrm:
17229 case VPMINSDrr:
17230 return true;
17231 }
17232 return false;
17233}
17234
17235bool isVFRCZSD(unsigned Opcode) {
17236 switch (Opcode) {
17237 case VFRCZSDrm:
17238 case VFRCZSDrr:
17239 return true;
17240 }
17241 return false;
17242}
17243
17244bool isVPTESTMW(unsigned Opcode) {
17245 switch (Opcode) {
17246 case VPTESTMWZ128rm:
17247 case VPTESTMWZ128rmk:
17248 case VPTESTMWZ128rr:
17249 case VPTESTMWZ128rrk:
17250 case VPTESTMWZ256rm:
17251 case VPTESTMWZ256rmk:
17252 case VPTESTMWZ256rr:
17253 case VPTESTMWZ256rrk:
17254 case VPTESTMWZrm:
17255 case VPTESTMWZrmk:
17256 case VPTESTMWZrr:
17257 case VPTESTMWZrrk:
17258 return true;
17259 }
17260 return false;
17261}
17262
17263bool isVPMOVZXWD(unsigned Opcode) {
17264 switch (Opcode) {
17265 case VPMOVZXWDYrm:
17266 case VPMOVZXWDYrr:
17267 case VPMOVZXWDZ128rm:
17268 case VPMOVZXWDZ128rmk:
17269 case VPMOVZXWDZ128rmkz:
17270 case VPMOVZXWDZ128rr:
17271 case VPMOVZXWDZ128rrk:
17272 case VPMOVZXWDZ128rrkz:
17273 case VPMOVZXWDZ256rm:
17274 case VPMOVZXWDZ256rmk:
17275 case VPMOVZXWDZ256rmkz:
17276 case VPMOVZXWDZ256rr:
17277 case VPMOVZXWDZ256rrk:
17278 case VPMOVZXWDZ256rrkz:
17279 case VPMOVZXWDZrm:
17280 case VPMOVZXWDZrmk:
17281 case VPMOVZXWDZrmkz:
17282 case VPMOVZXWDZrr:
17283 case VPMOVZXWDZrrk:
17284 case VPMOVZXWDZrrkz:
17285 case VPMOVZXWDrm:
17286 case VPMOVZXWDrr:
17287 return true;
17288 }
17289 return false;
17290}
17291
17292bool isPSADBW(unsigned Opcode) {
17293 switch (Opcode) {
17294 case MMX_PSADBWrm:
17295 case MMX_PSADBWrr:
17296 case PSADBWrm:
17297 case PSADBWrr:
17298 return true;
17299 }
17300 return false;
17301}
17302
17303bool isVCVTSD2SI(unsigned Opcode) {
17304 switch (Opcode) {
17305 case VCVTSD2SI64Zrm_Int:
17306 case VCVTSD2SI64Zrr_Int:
17307 case VCVTSD2SI64Zrrb_Int:
17308 case VCVTSD2SI64rm_Int:
17309 case VCVTSD2SI64rr_Int:
17310 case VCVTSD2SIZrm_Int:
17311 case VCVTSD2SIZrr_Int:
17312 case VCVTSD2SIZrrb_Int:
17313 case VCVTSD2SIrm_Int:
17314 case VCVTSD2SIrr_Int:
17315 return true;
17316 }
17317 return false;
17318}
17319
17320bool isVMAXPH(unsigned Opcode) {
17321 switch (Opcode) {
17322 case VMAXPHZ128rm:
17323 case VMAXPHZ128rmb:
17324 case VMAXPHZ128rmbk:
17325 case VMAXPHZ128rmbkz:
17326 case VMAXPHZ128rmk:
17327 case VMAXPHZ128rmkz:
17328 case VMAXPHZ128rr:
17329 case VMAXPHZ128rrk:
17330 case VMAXPHZ128rrkz:
17331 case VMAXPHZ256rm:
17332 case VMAXPHZ256rmb:
17333 case VMAXPHZ256rmbk:
17334 case VMAXPHZ256rmbkz:
17335 case VMAXPHZ256rmk:
17336 case VMAXPHZ256rmkz:
17337 case VMAXPHZ256rr:
17338 case VMAXPHZ256rrk:
17339 case VMAXPHZ256rrkz:
17340 case VMAXPHZrm:
17341 case VMAXPHZrmb:
17342 case VMAXPHZrmbk:
17343 case VMAXPHZrmbkz:
17344 case VMAXPHZrmk:
17345 case VMAXPHZrmkz:
17346 case VMAXPHZrr:
17347 case VMAXPHZrrb:
17348 case VMAXPHZrrbk:
17349 case VMAXPHZrrbkz:
17350 case VMAXPHZrrk:
17351 case VMAXPHZrrkz:
17352 return true;
17353 }
17354 return false;
17355}
17356
17357bool isLODSB(unsigned Opcode) {
17358 return Opcode == LODSB;
17359}
17360
17361bool isPHMINPOSUW(unsigned Opcode) {
17362 switch (Opcode) {
17363 case PHMINPOSUWrm:
17364 case PHMINPOSUWrr:
17365 return true;
17366 }
17367 return false;
17368}
17369
17370bool isVPROLVD(unsigned Opcode) {
17371 switch (Opcode) {
17372 case VPROLVDZ128rm:
17373 case VPROLVDZ128rmb:
17374 case VPROLVDZ128rmbk:
17375 case VPROLVDZ128rmbkz:
17376 case VPROLVDZ128rmk:
17377 case VPROLVDZ128rmkz:
17378 case VPROLVDZ128rr:
17379 case VPROLVDZ128rrk:
17380 case VPROLVDZ128rrkz:
17381 case VPROLVDZ256rm:
17382 case VPROLVDZ256rmb:
17383 case VPROLVDZ256rmbk:
17384 case VPROLVDZ256rmbkz:
17385 case VPROLVDZ256rmk:
17386 case VPROLVDZ256rmkz:
17387 case VPROLVDZ256rr:
17388 case VPROLVDZ256rrk:
17389 case VPROLVDZ256rrkz:
17390 case VPROLVDZrm:
17391 case VPROLVDZrmb:
17392 case VPROLVDZrmbk:
17393 case VPROLVDZrmbkz:
17394 case VPROLVDZrmk:
17395 case VPROLVDZrmkz:
17396 case VPROLVDZrr:
17397 case VPROLVDZrrk:
17398 case VPROLVDZrrkz:
17399 return true;
17400 }
17401 return false;
17402}
17403
17404bool isWRFSBASE(unsigned Opcode) {
17405 switch (Opcode) {
17406 case WRFSBASE:
17407 case WRFSBASE64:
17408 return true;
17409 }
17410 return false;
17411}
17412
17413bool isVRSQRT14PS(unsigned Opcode) {
17414 switch (Opcode) {
17415 case VRSQRT14PSZ128m:
17416 case VRSQRT14PSZ128mb:
17417 case VRSQRT14PSZ128mbk:
17418 case VRSQRT14PSZ128mbkz:
17419 case VRSQRT14PSZ128mk:
17420 case VRSQRT14PSZ128mkz:
17421 case VRSQRT14PSZ128r:
17422 case VRSQRT14PSZ128rk:
17423 case VRSQRT14PSZ128rkz:
17424 case VRSQRT14PSZ256m:
17425 case VRSQRT14PSZ256mb:
17426 case VRSQRT14PSZ256mbk:
17427 case VRSQRT14PSZ256mbkz:
17428 case VRSQRT14PSZ256mk:
17429 case VRSQRT14PSZ256mkz:
17430 case VRSQRT14PSZ256r:
17431 case VRSQRT14PSZ256rk:
17432 case VRSQRT14PSZ256rkz:
17433 case VRSQRT14PSZm:
17434 case VRSQRT14PSZmb:
17435 case VRSQRT14PSZmbk:
17436 case VRSQRT14PSZmbkz:
17437 case VRSQRT14PSZmk:
17438 case VRSQRT14PSZmkz:
17439 case VRSQRT14PSZr:
17440 case VRSQRT14PSZrk:
17441 case VRSQRT14PSZrkz:
17442 return true;
17443 }
17444 return false;
17445}
17446
17447bool isVPHSUBDQ(unsigned Opcode) {
17448 switch (Opcode) {
17449 case VPHSUBDQrm:
17450 case VPHSUBDQrr:
17451 return true;
17452 }
17453 return false;
17454}
17455
17456bool isIRETD(unsigned Opcode) {
17457 return Opcode == IRET32;
17458}
17459
17460bool isVMOVRSD(unsigned Opcode) {
17461 switch (Opcode) {
17462 case VMOVRSDZ128m:
17463 case VMOVRSDZ128mk:
17464 case VMOVRSDZ128mkz:
17465 case VMOVRSDZ256m:
17466 case VMOVRSDZ256mk:
17467 case VMOVRSDZ256mkz:
17468 case VMOVRSDZm:
17469 case VMOVRSDZmk:
17470 case VMOVRSDZmkz:
17471 return true;
17472 }
17473 return false;
17474}
17475
17476bool isCVTSI2SS(unsigned Opcode) {
17477 switch (Opcode) {
17478 case CVTSI2SSrm_Int:
17479 case CVTSI2SSrr_Int:
17480 case CVTSI642SSrm_Int:
17481 case CVTSI642SSrr_Int:
17482 return true;
17483 }
17484 return false;
17485}
17486
17487bool isVPMULHRSW(unsigned Opcode) {
17488 switch (Opcode) {
17489 case VPMULHRSWYrm:
17490 case VPMULHRSWYrr:
17491 case VPMULHRSWZ128rm:
17492 case VPMULHRSWZ128rmk:
17493 case VPMULHRSWZ128rmkz:
17494 case VPMULHRSWZ128rr:
17495 case VPMULHRSWZ128rrk:
17496 case VPMULHRSWZ128rrkz:
17497 case VPMULHRSWZ256rm:
17498 case VPMULHRSWZ256rmk:
17499 case VPMULHRSWZ256rmkz:
17500 case VPMULHRSWZ256rr:
17501 case VPMULHRSWZ256rrk:
17502 case VPMULHRSWZ256rrkz:
17503 case VPMULHRSWZrm:
17504 case VPMULHRSWZrmk:
17505 case VPMULHRSWZrmkz:
17506 case VPMULHRSWZrr:
17507 case VPMULHRSWZrrk:
17508 case VPMULHRSWZrrkz:
17509 case VPMULHRSWrm:
17510 case VPMULHRSWrr:
17511 return true;
17512 }
17513 return false;
17514}
17515
17516bool isPI2FD(unsigned Opcode) {
17517 switch (Opcode) {
17518 case PI2FDrm:
17519 case PI2FDrr:
17520 return true;
17521 }
17522 return false;
17523}
17524
17525bool isGF2P8AFFINEQB(unsigned Opcode) {
17526 switch (Opcode) {
17527 case GF2P8AFFINEQBrmi:
17528 case GF2P8AFFINEQBrri:
17529 return true;
17530 }
17531 return false;
17532}
17533
17534bool isPAND(unsigned Opcode) {
17535 switch (Opcode) {
17536 case MMX_PANDrm:
17537 case MMX_PANDrr:
17538 case PANDrm:
17539 case PANDrr:
17540 return true;
17541 }
17542 return false;
17543}
17544
17545bool isVFNMSUB231SH(unsigned Opcode) {
17546 switch (Opcode) {
17547 case VFNMSUB231SHZm_Int:
17548 case VFNMSUB231SHZmk_Int:
17549 case VFNMSUB231SHZmkz_Int:
17550 case VFNMSUB231SHZr_Int:
17551 case VFNMSUB231SHZrb_Int:
17552 case VFNMSUB231SHZrbk_Int:
17553 case VFNMSUB231SHZrbkz_Int:
17554 case VFNMSUB231SHZrk_Int:
17555 case VFNMSUB231SHZrkz_Int:
17556 return true;
17557 }
17558 return false;
17559}
17560
17561bool isVCVTPH2BF8(unsigned Opcode) {
17562 switch (Opcode) {
17563 case VCVTPH2BF8Z128rm:
17564 case VCVTPH2BF8Z128rmb:
17565 case VCVTPH2BF8Z128rmbk:
17566 case VCVTPH2BF8Z128rmbkz:
17567 case VCVTPH2BF8Z128rmk:
17568 case VCVTPH2BF8Z128rmkz:
17569 case VCVTPH2BF8Z128rr:
17570 case VCVTPH2BF8Z128rrk:
17571 case VCVTPH2BF8Z128rrkz:
17572 case VCVTPH2BF8Z256rm:
17573 case VCVTPH2BF8Z256rmb:
17574 case VCVTPH2BF8Z256rmbk:
17575 case VCVTPH2BF8Z256rmbkz:
17576 case VCVTPH2BF8Z256rmk:
17577 case VCVTPH2BF8Z256rmkz:
17578 case VCVTPH2BF8Z256rr:
17579 case VCVTPH2BF8Z256rrk:
17580 case VCVTPH2BF8Z256rrkz:
17581 case VCVTPH2BF8Zrm:
17582 case VCVTPH2BF8Zrmb:
17583 case VCVTPH2BF8Zrmbk:
17584 case VCVTPH2BF8Zrmbkz:
17585 case VCVTPH2BF8Zrmk:
17586 case VCVTPH2BF8Zrmkz:
17587 case VCVTPH2BF8Zrr:
17588 case VCVTPH2BF8Zrrk:
17589 case VCVTPH2BF8Zrrkz:
17590 return true;
17591 }
17592 return false;
17593}
17594
17595bool isVMOVHLPS(unsigned Opcode) {
17596 switch (Opcode) {
17597 case VMOVHLPSZrr:
17598 case VMOVHLPSrr:
17599 return true;
17600 }
17601 return false;
17602}
17603
17604bool isPEXTRB(unsigned Opcode) {
17605 switch (Opcode) {
17606 case PEXTRBmri:
17607 case PEXTRBrri:
17608 return true;
17609 }
17610 return false;
17611}
17612
17613bool isVMMCALL(unsigned Opcode) {
17614 return Opcode == VMMCALL;
17615}
17616
17617bool isKNOTD(unsigned Opcode) {
17618 return Opcode == KNOTDkk;
17619}
17620
17621bool isVCVTSH2SS(unsigned Opcode) {
17622 switch (Opcode) {
17623 case VCVTSH2SSZrm_Int:
17624 case VCVTSH2SSZrmk_Int:
17625 case VCVTSH2SSZrmkz_Int:
17626 case VCVTSH2SSZrr_Int:
17627 case VCVTSH2SSZrrb_Int:
17628 case VCVTSH2SSZrrbk_Int:
17629 case VCVTSH2SSZrrbkz_Int:
17630 case VCVTSH2SSZrrk_Int:
17631 case VCVTSH2SSZrrkz_Int:
17632 return true;
17633 }
17634 return false;
17635}
17636
17637bool isVPUNPCKLQDQ(unsigned Opcode) {
17638 switch (Opcode) {
17639 case VPUNPCKLQDQYrm:
17640 case VPUNPCKLQDQYrr:
17641 case VPUNPCKLQDQZ128rm:
17642 case VPUNPCKLQDQZ128rmb:
17643 case VPUNPCKLQDQZ128rmbk:
17644 case VPUNPCKLQDQZ128rmbkz:
17645 case VPUNPCKLQDQZ128rmk:
17646 case VPUNPCKLQDQZ128rmkz:
17647 case VPUNPCKLQDQZ128rr:
17648 case VPUNPCKLQDQZ128rrk:
17649 case VPUNPCKLQDQZ128rrkz:
17650 case VPUNPCKLQDQZ256rm:
17651 case VPUNPCKLQDQZ256rmb:
17652 case VPUNPCKLQDQZ256rmbk:
17653 case VPUNPCKLQDQZ256rmbkz:
17654 case VPUNPCKLQDQZ256rmk:
17655 case VPUNPCKLQDQZ256rmkz:
17656 case VPUNPCKLQDQZ256rr:
17657 case VPUNPCKLQDQZ256rrk:
17658 case VPUNPCKLQDQZ256rrkz:
17659 case VPUNPCKLQDQZrm:
17660 case VPUNPCKLQDQZrmb:
17661 case VPUNPCKLQDQZrmbk:
17662 case VPUNPCKLQDQZrmbkz:
17663 case VPUNPCKLQDQZrmk:
17664 case VPUNPCKLQDQZrmkz:
17665 case VPUNPCKLQDQZrr:
17666 case VPUNPCKLQDQZrrk:
17667 case VPUNPCKLQDQZrrkz:
17668 case VPUNPCKLQDQrm:
17669 case VPUNPCKLQDQrr:
17670 return true;
17671 }
17672 return false;
17673}
17674
17675bool isVPERMIL2PS(unsigned Opcode) {
17676 switch (Opcode) {
17677 case VPERMIL2PSYmr:
17678 case VPERMIL2PSYrm:
17679 case VPERMIL2PSYrr:
17680 case VPERMIL2PSYrr_REV:
17681 case VPERMIL2PSmr:
17682 case VPERMIL2PSrm:
17683 case VPERMIL2PSrr:
17684 case VPERMIL2PSrr_REV:
17685 return true;
17686 }
17687 return false;
17688}
17689
17690bool isVPCMPGTD(unsigned Opcode) {
17691 switch (Opcode) {
17692 case VPCMPGTDYrm:
17693 case VPCMPGTDYrr:
17694 case VPCMPGTDZ128rm:
17695 case VPCMPGTDZ128rmb:
17696 case VPCMPGTDZ128rmbk:
17697 case VPCMPGTDZ128rmk:
17698 case VPCMPGTDZ128rr:
17699 case VPCMPGTDZ128rrk:
17700 case VPCMPGTDZ256rm:
17701 case VPCMPGTDZ256rmb:
17702 case VPCMPGTDZ256rmbk:
17703 case VPCMPGTDZ256rmk:
17704 case VPCMPGTDZ256rr:
17705 case VPCMPGTDZ256rrk:
17706 case VPCMPGTDZrm:
17707 case VPCMPGTDZrmb:
17708 case VPCMPGTDZrmbk:
17709 case VPCMPGTDZrmk:
17710 case VPCMPGTDZrr:
17711 case VPCMPGTDZrrk:
17712 case VPCMPGTDrm:
17713 case VPCMPGTDrr:
17714 return true;
17715 }
17716 return false;
17717}
17718
17719bool isCMPXCHG16B(unsigned Opcode) {
17720 return Opcode == CMPXCHG16B;
17721}
17722
17723bool isTDPHF8PS(unsigned Opcode) {
17724 return Opcode == TDPHF8PS;
17725}
17726
17727bool isVZEROUPPER(unsigned Opcode) {
17728 return Opcode == VZEROUPPER;
17729}
17730
17731bool isMOVAPS(unsigned Opcode) {
17732 switch (Opcode) {
17733 case MOVAPSmr:
17734 case MOVAPSrm:
17735 case MOVAPSrr:
17736 case MOVAPSrr_REV:
17737 return true;
17738 }
17739 return false;
17740}
17741
17742bool isVPCMPW(unsigned Opcode) {
17743 switch (Opcode) {
17744 case VPCMPWZ128rmi:
17745 case VPCMPWZ128rmik:
17746 case VPCMPWZ128rri:
17747 case VPCMPWZ128rrik:
17748 case VPCMPWZ256rmi:
17749 case VPCMPWZ256rmik:
17750 case VPCMPWZ256rri:
17751 case VPCMPWZ256rrik:
17752 case VPCMPWZrmi:
17753 case VPCMPWZrmik:
17754 case VPCMPWZrri:
17755 case VPCMPWZrrik:
17756 return true;
17757 }
17758 return false;
17759}
17760
17761bool isFUCOMPP(unsigned Opcode) {
17762 return Opcode == UCOM_FPPr;
17763}
17764
17765bool isXSETBV(unsigned Opcode) {
17766 return Opcode == XSETBV;
17767}
17768
17769bool isSLWPCB(unsigned Opcode) {
17770 switch (Opcode) {
17771 case SLWPCB:
17772 case SLWPCB64:
17773 return true;
17774 }
17775 return false;
17776}
17777
17778bool isSCASW(unsigned Opcode) {
17779 return Opcode == SCASW;
17780}
17781
17782bool isFCMOVNE(unsigned Opcode) {
17783 return Opcode == CMOVNE_F;
17784}
17785
17786bool isPBNDKB(unsigned Opcode) {
17787 return Opcode == PBNDKB;
17788}
17789
17790bool isVPMULLD(unsigned Opcode) {
17791 switch (Opcode) {
17792 case VPMULLDYrm:
17793 case VPMULLDYrr:
17794 case VPMULLDZ128rm:
17795 case VPMULLDZ128rmb:
17796 case VPMULLDZ128rmbk:
17797 case VPMULLDZ128rmbkz:
17798 case VPMULLDZ128rmk:
17799 case VPMULLDZ128rmkz:
17800 case VPMULLDZ128rr:
17801 case VPMULLDZ128rrk:
17802 case VPMULLDZ128rrkz:
17803 case VPMULLDZ256rm:
17804 case VPMULLDZ256rmb:
17805 case VPMULLDZ256rmbk:
17806 case VPMULLDZ256rmbkz:
17807 case VPMULLDZ256rmk:
17808 case VPMULLDZ256rmkz:
17809 case VPMULLDZ256rr:
17810 case VPMULLDZ256rrk:
17811 case VPMULLDZ256rrkz:
17812 case VPMULLDZrm:
17813 case VPMULLDZrmb:
17814 case VPMULLDZrmbk:
17815 case VPMULLDZrmbkz:
17816 case VPMULLDZrmk:
17817 case VPMULLDZrmkz:
17818 case VPMULLDZrr:
17819 case VPMULLDZrrk:
17820 case VPMULLDZrrkz:
17821 case VPMULLDrm:
17822 case VPMULLDrr:
17823 return true;
17824 }
17825 return false;
17826}
17827
17828bool isVP4DPWSSDS(unsigned Opcode) {
17829 switch (Opcode) {
17830 case VP4DPWSSDSrm:
17831 case VP4DPWSSDSrmk:
17832 case VP4DPWSSDSrmkz:
17833 return true;
17834 }
17835 return false;
17836}
17837
17838bool isVCVT2PH2HF8(unsigned Opcode) {
17839 switch (Opcode) {
17840 case VCVT2PH2HF8Z128rm:
17841 case VCVT2PH2HF8Z128rmb:
17842 case VCVT2PH2HF8Z128rmbk:
17843 case VCVT2PH2HF8Z128rmbkz:
17844 case VCVT2PH2HF8Z128rmk:
17845 case VCVT2PH2HF8Z128rmkz:
17846 case VCVT2PH2HF8Z128rr:
17847 case VCVT2PH2HF8Z128rrk:
17848 case VCVT2PH2HF8Z128rrkz:
17849 case VCVT2PH2HF8Z256rm:
17850 case VCVT2PH2HF8Z256rmb:
17851 case VCVT2PH2HF8Z256rmbk:
17852 case VCVT2PH2HF8Z256rmbkz:
17853 case VCVT2PH2HF8Z256rmk:
17854 case VCVT2PH2HF8Z256rmkz:
17855 case VCVT2PH2HF8Z256rr:
17856 case VCVT2PH2HF8Z256rrk:
17857 case VCVT2PH2HF8Z256rrkz:
17858 case VCVT2PH2HF8Zrm:
17859 case VCVT2PH2HF8Zrmb:
17860 case VCVT2PH2HF8Zrmbk:
17861 case VCVT2PH2HF8Zrmbkz:
17862 case VCVT2PH2HF8Zrmk:
17863 case VCVT2PH2HF8Zrmkz:
17864 case VCVT2PH2HF8Zrr:
17865 case VCVT2PH2HF8Zrrk:
17866 case VCVT2PH2HF8Zrrkz:
17867 return true;
17868 }
17869 return false;
17870}
17871
17872bool isPINSRW(unsigned Opcode) {
17873 switch (Opcode) {
17874 case MMX_PINSRWrmi:
17875 case MMX_PINSRWrri:
17876 case PINSRWrmi:
17877 case PINSRWrri:
17878 return true;
17879 }
17880 return false;
17881}
17882
17883bool isVCVTSI2SH(unsigned Opcode) {
17884 switch (Opcode) {
17885 case VCVTSI2SHZrm_Int:
17886 case VCVTSI2SHZrr_Int:
17887 case VCVTSI2SHZrrb_Int:
17888 case VCVTSI642SHZrm_Int:
17889 case VCVTSI642SHZrr_Int:
17890 case VCVTSI642SHZrrb_Int:
17891 return true;
17892 }
17893 return false;
17894}
17895
17896bool isVINSERTF32X8(unsigned Opcode) {
17897 switch (Opcode) {
17898 case VINSERTF32X8Zrmi:
17899 case VINSERTF32X8Zrmik:
17900 case VINSERTF32X8Zrmikz:
17901 case VINSERTF32X8Zrri:
17902 case VINSERTF32X8Zrrik:
17903 case VINSERTF32X8Zrrikz:
17904 return true;
17905 }
17906 return false;
17907}
17908
17909bool isKSHIFTLB(unsigned Opcode) {
17910 return Opcode == KSHIFTLBki;
17911}
17912
17913bool isSEAMOPS(unsigned Opcode) {
17914 return Opcode == SEAMOPS;
17915}
17916
17917bool isVPMULUDQ(unsigned Opcode) {
17918 switch (Opcode) {
17919 case VPMULUDQYrm:
17920 case VPMULUDQYrr:
17921 case VPMULUDQZ128rm:
17922 case VPMULUDQZ128rmb:
17923 case VPMULUDQZ128rmbk:
17924 case VPMULUDQZ128rmbkz:
17925 case VPMULUDQZ128rmk:
17926 case VPMULUDQZ128rmkz:
17927 case VPMULUDQZ128rr:
17928 case VPMULUDQZ128rrk:
17929 case VPMULUDQZ128rrkz:
17930 case VPMULUDQZ256rm:
17931 case VPMULUDQZ256rmb:
17932 case VPMULUDQZ256rmbk:
17933 case VPMULUDQZ256rmbkz:
17934 case VPMULUDQZ256rmk:
17935 case VPMULUDQZ256rmkz:
17936 case VPMULUDQZ256rr:
17937 case VPMULUDQZ256rrk:
17938 case VPMULUDQZ256rrkz:
17939 case VPMULUDQZrm:
17940 case VPMULUDQZrmb:
17941 case VPMULUDQZrmbk:
17942 case VPMULUDQZrmbkz:
17943 case VPMULUDQZrmk:
17944 case VPMULUDQZrmkz:
17945 case VPMULUDQZrr:
17946 case VPMULUDQZrrk:
17947 case VPMULUDQZrrkz:
17948 case VPMULUDQrm:
17949 case VPMULUDQrr:
17950 return true;
17951 }
17952 return false;
17953}
17954
17955bool isVPMOVSQB(unsigned Opcode) {
17956 switch (Opcode) {
17957 case VPMOVSQBZ128mr:
17958 case VPMOVSQBZ128mrk:
17959 case VPMOVSQBZ128rr:
17960 case VPMOVSQBZ128rrk:
17961 case VPMOVSQBZ128rrkz:
17962 case VPMOVSQBZ256mr:
17963 case VPMOVSQBZ256mrk:
17964 case VPMOVSQBZ256rr:
17965 case VPMOVSQBZ256rrk:
17966 case VPMOVSQBZ256rrkz:
17967 case VPMOVSQBZmr:
17968 case VPMOVSQBZmrk:
17969 case VPMOVSQBZrr:
17970 case VPMOVSQBZrrk:
17971 case VPMOVSQBZrrkz:
17972 return true;
17973 }
17974 return false;
17975}
17976
17977bool isVPTESTMD(unsigned Opcode) {
17978 switch (Opcode) {
17979 case VPTESTMDZ128rm:
17980 case VPTESTMDZ128rmb:
17981 case VPTESTMDZ128rmbk:
17982 case VPTESTMDZ128rmk:
17983 case VPTESTMDZ128rr:
17984 case VPTESTMDZ128rrk:
17985 case VPTESTMDZ256rm:
17986 case VPTESTMDZ256rmb:
17987 case VPTESTMDZ256rmbk:
17988 case VPTESTMDZ256rmk:
17989 case VPTESTMDZ256rr:
17990 case VPTESTMDZ256rrk:
17991 case VPTESTMDZrm:
17992 case VPTESTMDZrmb:
17993 case VPTESTMDZrmbk:
17994 case VPTESTMDZrmk:
17995 case VPTESTMDZrr:
17996 case VPTESTMDZrrk:
17997 return true;
17998 }
17999 return false;
18000}
18001
18002bool isVPHADDDQ(unsigned Opcode) {
18003 switch (Opcode) {
18004 case VPHADDDQrm:
18005 case VPHADDDQrr:
18006 return true;
18007 }
18008 return false;
18009}
18010
18011bool isKUNPCKDQ(unsigned Opcode) {
18012 return Opcode == KUNPCKDQkk;
18013}
18014
18015bool isT1MSKC(unsigned Opcode) {
18016 switch (Opcode) {
18017 case T1MSKC32rm:
18018 case T1MSKC32rr:
18019 case T1MSKC64rm:
18020 case T1MSKC64rr:
18021 return true;
18022 }
18023 return false;
18024}
18025
18026bool isVPCOMB(unsigned Opcode) {
18027 switch (Opcode) {
18028 case VPCOMBmi:
18029 case VPCOMBri:
18030 return true;
18031 }
18032 return false;
18033}
18034
18035bool isVBLENDPS(unsigned Opcode) {
18036 switch (Opcode) {
18037 case VBLENDPSYrmi:
18038 case VBLENDPSYrri:
18039 case VBLENDPSrmi:
18040 case VBLENDPSrri:
18041 return true;
18042 }
18043 return false;
18044}
18045
18046bool isPTWRITE(unsigned Opcode) {
18047 switch (Opcode) {
18048 case PTWRITE64m:
18049 case PTWRITE64r:
18050 case PTWRITEm:
18051 case PTWRITEr:
18052 return true;
18053 }
18054 return false;
18055}
18056
18057bool isVCVTPH2BF8S(unsigned Opcode) {
18058 switch (Opcode) {
18059 case VCVTPH2BF8SZ128rm:
18060 case VCVTPH2BF8SZ128rmb:
18061 case VCVTPH2BF8SZ128rmbk:
18062 case VCVTPH2BF8SZ128rmbkz:
18063 case VCVTPH2BF8SZ128rmk:
18064 case VCVTPH2BF8SZ128rmkz:
18065 case VCVTPH2BF8SZ128rr:
18066 case VCVTPH2BF8SZ128rrk:
18067 case VCVTPH2BF8SZ128rrkz:
18068 case VCVTPH2BF8SZ256rm:
18069 case VCVTPH2BF8SZ256rmb:
18070 case VCVTPH2BF8SZ256rmbk:
18071 case VCVTPH2BF8SZ256rmbkz:
18072 case VCVTPH2BF8SZ256rmk:
18073 case VCVTPH2BF8SZ256rmkz:
18074 case VCVTPH2BF8SZ256rr:
18075 case VCVTPH2BF8SZ256rrk:
18076 case VCVTPH2BF8SZ256rrkz:
18077 case VCVTPH2BF8SZrm:
18078 case VCVTPH2BF8SZrmb:
18079 case VCVTPH2BF8SZrmbk:
18080 case VCVTPH2BF8SZrmbkz:
18081 case VCVTPH2BF8SZrmk:
18082 case VCVTPH2BF8SZrmkz:
18083 case VCVTPH2BF8SZrr:
18084 case VCVTPH2BF8SZrrk:
18085 case VCVTPH2BF8SZrrkz:
18086 return true;
18087 }
18088 return false;
18089}
18090
18091bool isCVTPS2PI(unsigned Opcode) {
18092 switch (Opcode) {
18093 case MMX_CVTPS2PIrm:
18094 case MMX_CVTPS2PIrr:
18095 return true;
18096 }
18097 return false;
18098}
18099
18100bool isVPROTD(unsigned Opcode) {
18101 switch (Opcode) {
18102 case VPROTDmi:
18103 case VPROTDmr:
18104 case VPROTDri:
18105 case VPROTDrm:
18106 case VPROTDrr:
18107 case VPROTDrr_REV:
18108 return true;
18109 }
18110 return false;
18111}
18112
18113bool isCALL(unsigned Opcode) {
18114 switch (Opcode) {
18115 case CALL16m:
18116 case CALL16r:
18117 case CALL32m:
18118 case CALL32r:
18119 case CALL64m:
18120 case CALL64pcrel32:
18121 case CALL64r:
18122 case CALLpcrel16:
18123 case CALLpcrel32:
18124 case FARCALL32m:
18125 return true;
18126 }
18127 return false;
18128}
18129
18130bool isTILELOADDRST1(unsigned Opcode) {
18131 switch (Opcode) {
18132 case TILELOADDRST1:
18133 case TILELOADDRST1_EVEX:
18134 return true;
18135 }
18136 return false;
18137}
18138
18139bool isVPERMPS(unsigned Opcode) {
18140 switch (Opcode) {
18141 case VPERMPSYrm:
18142 case VPERMPSYrr:
18143 case VPERMPSZ256rm:
18144 case VPERMPSZ256rmb:
18145 case VPERMPSZ256rmbk:
18146 case VPERMPSZ256rmbkz:
18147 case VPERMPSZ256rmk:
18148 case VPERMPSZ256rmkz:
18149 case VPERMPSZ256rr:
18150 case VPERMPSZ256rrk:
18151 case VPERMPSZ256rrkz:
18152 case VPERMPSZrm:
18153 case VPERMPSZrmb:
18154 case VPERMPSZrmbk:
18155 case VPERMPSZrmbkz:
18156 case VPERMPSZrmk:
18157 case VPERMPSZrmkz:
18158 case VPERMPSZrr:
18159 case VPERMPSZrrk:
18160 case VPERMPSZrrkz:
18161 return true;
18162 }
18163 return false;
18164}
18165
18166bool isVPSHUFBITQMB(unsigned Opcode) {
18167 switch (Opcode) {
18168 case VPSHUFBITQMBZ128rm:
18169 case VPSHUFBITQMBZ128rmk:
18170 case VPSHUFBITQMBZ128rr:
18171 case VPSHUFBITQMBZ128rrk:
18172 case VPSHUFBITQMBZ256rm:
18173 case VPSHUFBITQMBZ256rmk:
18174 case VPSHUFBITQMBZ256rr:
18175 case VPSHUFBITQMBZ256rrk:
18176 case VPSHUFBITQMBZrm:
18177 case VPSHUFBITQMBZrmk:
18178 case VPSHUFBITQMBZrr:
18179 case VPSHUFBITQMBZrrk:
18180 return true;
18181 }
18182 return false;
18183}
18184
18185bool isVMOVSLDUP(unsigned Opcode) {
18186 switch (Opcode) {
18187 case VMOVSLDUPYrm:
18188 case VMOVSLDUPYrr:
18189 case VMOVSLDUPZ128rm:
18190 case VMOVSLDUPZ128rmk:
18191 case VMOVSLDUPZ128rmkz:
18192 case VMOVSLDUPZ128rr:
18193 case VMOVSLDUPZ128rrk:
18194 case VMOVSLDUPZ128rrkz:
18195 case VMOVSLDUPZ256rm:
18196 case VMOVSLDUPZ256rmk:
18197 case VMOVSLDUPZ256rmkz:
18198 case VMOVSLDUPZ256rr:
18199 case VMOVSLDUPZ256rrk:
18200 case VMOVSLDUPZ256rrkz:
18201 case VMOVSLDUPZrm:
18202 case VMOVSLDUPZrmk:
18203 case VMOVSLDUPZrmkz:
18204 case VMOVSLDUPZrr:
18205 case VMOVSLDUPZrrk:
18206 case VMOVSLDUPZrrkz:
18207 case VMOVSLDUPrm:
18208 case VMOVSLDUPrr:
18209 return true;
18210 }
18211 return false;
18212}
18213
18214bool isINVLPGA(unsigned Opcode) {
18215 switch (Opcode) {
18216 case INVLPGA32:
18217 case INVLPGA64:
18218 return true;
18219 }
18220 return false;
18221}
18222
18223bool isVCVTPH2QQ(unsigned Opcode) {
18224 switch (Opcode) {
18225 case VCVTPH2QQZ128rm:
18226 case VCVTPH2QQZ128rmb:
18227 case VCVTPH2QQZ128rmbk:
18228 case VCVTPH2QQZ128rmbkz:
18229 case VCVTPH2QQZ128rmk:
18230 case VCVTPH2QQZ128rmkz:
18231 case VCVTPH2QQZ128rr:
18232 case VCVTPH2QQZ128rrk:
18233 case VCVTPH2QQZ128rrkz:
18234 case VCVTPH2QQZ256rm:
18235 case VCVTPH2QQZ256rmb:
18236 case VCVTPH2QQZ256rmbk:
18237 case VCVTPH2QQZ256rmbkz:
18238 case VCVTPH2QQZ256rmk:
18239 case VCVTPH2QQZ256rmkz:
18240 case VCVTPH2QQZ256rr:
18241 case VCVTPH2QQZ256rrk:
18242 case VCVTPH2QQZ256rrkz:
18243 case VCVTPH2QQZrm:
18244 case VCVTPH2QQZrmb:
18245 case VCVTPH2QQZrmbk:
18246 case VCVTPH2QQZrmbkz:
18247 case VCVTPH2QQZrmk:
18248 case VCVTPH2QQZrmkz:
18249 case VCVTPH2QQZrr:
18250 case VCVTPH2QQZrrb:
18251 case VCVTPH2QQZrrbk:
18252 case VCVTPH2QQZrrbkz:
18253 case VCVTPH2QQZrrk:
18254 case VCVTPH2QQZrrkz:
18255 return true;
18256 }
18257 return false;
18258}
18259
18260bool isADD(unsigned Opcode) {
18261 switch (Opcode) {
18262 case ADD16i16:
18263 case ADD16mi:
18264 case ADD16mi8:
18265 case ADD16mi8_EVEX:
18266 case ADD16mi8_ND:
18267 case ADD16mi8_NF:
18268 case ADD16mi8_NF_ND:
18269 case ADD16mi_EVEX:
18270 case ADD16mi_ND:
18271 case ADD16mi_NF:
18272 case ADD16mi_NF_ND:
18273 case ADD16mr:
18274 case ADD16mr_EVEX:
18275 case ADD16mr_ND:
18276 case ADD16mr_NF:
18277 case ADD16mr_NF_ND:
18278 case ADD16ri:
18279 case ADD16ri8:
18280 case ADD16ri8_EVEX:
18281 case ADD16ri8_ND:
18282 case ADD16ri8_NF:
18283 case ADD16ri8_NF_ND:
18284 case ADD16ri_EVEX:
18285 case ADD16ri_ND:
18286 case ADD16ri_NF:
18287 case ADD16ri_NF_ND:
18288 case ADD16rm:
18289 case ADD16rm_EVEX:
18290 case ADD16rm_ND:
18291 case ADD16rm_NF:
18292 case ADD16rm_NF_ND:
18293 case ADD16rr:
18294 case ADD16rr_EVEX:
18295 case ADD16rr_EVEX_REV:
18296 case ADD16rr_ND:
18297 case ADD16rr_ND_REV:
18298 case ADD16rr_NF:
18299 case ADD16rr_NF_ND:
18300 case ADD16rr_NF_ND_REV:
18301 case ADD16rr_NF_REV:
18302 case ADD16rr_REV:
18303 case ADD32i32:
18304 case ADD32mi:
18305 case ADD32mi8:
18306 case ADD32mi8_EVEX:
18307 case ADD32mi8_ND:
18308 case ADD32mi8_NF:
18309 case ADD32mi8_NF_ND:
18310 case ADD32mi_EVEX:
18311 case ADD32mi_ND:
18312 case ADD32mi_NF:
18313 case ADD32mi_NF_ND:
18314 case ADD32mr:
18315 case ADD32mr_EVEX:
18316 case ADD32mr_ND:
18317 case ADD32mr_NF:
18318 case ADD32mr_NF_ND:
18319 case ADD32ri:
18320 case ADD32ri8:
18321 case ADD32ri8_EVEX:
18322 case ADD32ri8_ND:
18323 case ADD32ri8_NF:
18324 case ADD32ri8_NF_ND:
18325 case ADD32ri_EVEX:
18326 case ADD32ri_ND:
18327 case ADD32ri_NF:
18328 case ADD32ri_NF_ND:
18329 case ADD32rm:
18330 case ADD32rm_EVEX:
18331 case ADD32rm_ND:
18332 case ADD32rm_NF:
18333 case ADD32rm_NF_ND:
18334 case ADD32rr:
18335 case ADD32rr_EVEX:
18336 case ADD32rr_EVEX_REV:
18337 case ADD32rr_ND:
18338 case ADD32rr_ND_REV:
18339 case ADD32rr_NF:
18340 case ADD32rr_NF_ND:
18341 case ADD32rr_NF_ND_REV:
18342 case ADD32rr_NF_REV:
18343 case ADD32rr_REV:
18344 case ADD64i32:
18345 case ADD64mi32:
18346 case ADD64mi32_EVEX:
18347 case ADD64mi32_ND:
18348 case ADD64mi32_NF:
18349 case ADD64mi32_NF_ND:
18350 case ADD64mi8:
18351 case ADD64mi8_EVEX:
18352 case ADD64mi8_ND:
18353 case ADD64mi8_NF:
18354 case ADD64mi8_NF_ND:
18355 case ADD64mr:
18356 case ADD64mr_EVEX:
18357 case ADD64mr_ND:
18358 case ADD64mr_NF:
18359 case ADD64mr_NF_ND:
18360 case ADD64ri32:
18361 case ADD64ri32_EVEX:
18362 case ADD64ri32_ND:
18363 case ADD64ri32_NF:
18364 case ADD64ri32_NF_ND:
18365 case ADD64ri8:
18366 case ADD64ri8_EVEX:
18367 case ADD64ri8_ND:
18368 case ADD64ri8_NF:
18369 case ADD64ri8_NF_ND:
18370 case ADD64rm:
18371 case ADD64rm_EVEX:
18372 case ADD64rm_ND:
18373 case ADD64rm_NF:
18374 case ADD64rm_NF_ND:
18375 case ADD64rr:
18376 case ADD64rr_EVEX:
18377 case ADD64rr_EVEX_REV:
18378 case ADD64rr_ND:
18379 case ADD64rr_ND_REV:
18380 case ADD64rr_NF:
18381 case ADD64rr_NF_ND:
18382 case ADD64rr_NF_ND_REV:
18383 case ADD64rr_NF_REV:
18384 case ADD64rr_REV:
18385 case ADD8i8:
18386 case ADD8mi:
18387 case ADD8mi8:
18388 case ADD8mi_EVEX:
18389 case ADD8mi_ND:
18390 case ADD8mi_NF:
18391 case ADD8mi_NF_ND:
18392 case ADD8mr:
18393 case ADD8mr_EVEX:
18394 case ADD8mr_ND:
18395 case ADD8mr_NF:
18396 case ADD8mr_NF_ND:
18397 case ADD8ri:
18398 case ADD8ri8:
18399 case ADD8ri_EVEX:
18400 case ADD8ri_ND:
18401 case ADD8ri_NF:
18402 case ADD8ri_NF_ND:
18403 case ADD8rm:
18404 case ADD8rm_EVEX:
18405 case ADD8rm_ND:
18406 case ADD8rm_NF:
18407 case ADD8rm_NF_ND:
18408 case ADD8rr:
18409 case ADD8rr_EVEX:
18410 case ADD8rr_EVEX_REV:
18411 case ADD8rr_ND:
18412 case ADD8rr_ND_REV:
18413 case ADD8rr_NF:
18414 case ADD8rr_NF_ND:
18415 case ADD8rr_NF_ND_REV:
18416 case ADD8rr_NF_REV:
18417 case ADD8rr_REV:
18418 return true;
18419 }
18420 return false;
18421}
18422
18423bool isPSUBSW(unsigned Opcode) {
18424 switch (Opcode) {
18425 case MMX_PSUBSWrm:
18426 case MMX_PSUBSWrr:
18427 case PSUBSWrm:
18428 case PSUBSWrr:
18429 return true;
18430 }
18431 return false;
18432}
18433
18434bool isSIDTW(unsigned Opcode) {
18435 return Opcode == SIDT16m;
18436}
18437
18438bool isVFNMADD231PH(unsigned Opcode) {
18439 switch (Opcode) {
18440 case VFNMADD231PHZ128m:
18441 case VFNMADD231PHZ128mb:
18442 case VFNMADD231PHZ128mbk:
18443 case VFNMADD231PHZ128mbkz:
18444 case VFNMADD231PHZ128mk:
18445 case VFNMADD231PHZ128mkz:
18446 case VFNMADD231PHZ128r:
18447 case VFNMADD231PHZ128rk:
18448 case VFNMADD231PHZ128rkz:
18449 case VFNMADD231PHZ256m:
18450 case VFNMADD231PHZ256mb:
18451 case VFNMADD231PHZ256mbk:
18452 case VFNMADD231PHZ256mbkz:
18453 case VFNMADD231PHZ256mk:
18454 case VFNMADD231PHZ256mkz:
18455 case VFNMADD231PHZ256r:
18456 case VFNMADD231PHZ256rk:
18457 case VFNMADD231PHZ256rkz:
18458 case VFNMADD231PHZm:
18459 case VFNMADD231PHZmb:
18460 case VFNMADD231PHZmbk:
18461 case VFNMADD231PHZmbkz:
18462 case VFNMADD231PHZmk:
18463 case VFNMADD231PHZmkz:
18464 case VFNMADD231PHZr:
18465 case VFNMADD231PHZrb:
18466 case VFNMADD231PHZrbk:
18467 case VFNMADD231PHZrbkz:
18468 case VFNMADD231PHZrk:
18469 case VFNMADD231PHZrkz:
18470 return true;
18471 }
18472 return false;
18473}
18474
18475bool isVEXTRACTF64X2(unsigned Opcode) {
18476 switch (Opcode) {
18477 case VEXTRACTF64X2Z256mri:
18478 case VEXTRACTF64X2Z256mrik:
18479 case VEXTRACTF64X2Z256rri:
18480 case VEXTRACTF64X2Z256rrik:
18481 case VEXTRACTF64X2Z256rrikz:
18482 case VEXTRACTF64X2Zmri:
18483 case VEXTRACTF64X2Zmrik:
18484 case VEXTRACTF64X2Zrri:
18485 case VEXTRACTF64X2Zrrik:
18486 case VEXTRACTF64X2Zrrikz:
18487 return true;
18488 }
18489 return false;
18490}
18491
18492bool isFCOMI(unsigned Opcode) {
18493 return Opcode == COM_FIr;
18494}
18495
18496bool isRSM(unsigned Opcode) {
18497 return Opcode == RSM;
18498}
18499
18500bool isVPCOMUD(unsigned Opcode) {
18501 switch (Opcode) {
18502 case VPCOMUDmi:
18503 case VPCOMUDri:
18504 return true;
18505 }
18506 return false;
18507}
18508
18509bool isVPMOVZXBQ(unsigned Opcode) {
18510 switch (Opcode) {
18511 case VPMOVZXBQYrm:
18512 case VPMOVZXBQYrr:
18513 case VPMOVZXBQZ128rm:
18514 case VPMOVZXBQZ128rmk:
18515 case VPMOVZXBQZ128rmkz:
18516 case VPMOVZXBQZ128rr:
18517 case VPMOVZXBQZ128rrk:
18518 case VPMOVZXBQZ128rrkz:
18519 case VPMOVZXBQZ256rm:
18520 case VPMOVZXBQZ256rmk:
18521 case VPMOVZXBQZ256rmkz:
18522 case VPMOVZXBQZ256rr:
18523 case VPMOVZXBQZ256rrk:
18524 case VPMOVZXBQZ256rrkz:
18525 case VPMOVZXBQZrm:
18526 case VPMOVZXBQZrmk:
18527 case VPMOVZXBQZrmkz:
18528 case VPMOVZXBQZrr:
18529 case VPMOVZXBQZrrk:
18530 case VPMOVZXBQZrrkz:
18531 case VPMOVZXBQrm:
18532 case VPMOVZXBQrr:
18533 return true;
18534 }
18535 return false;
18536}
18537
18538bool isUWRMSR(unsigned Opcode) {
18539 switch (Opcode) {
18540 case UWRMSRir:
18541 case UWRMSRir_EVEX:
18542 case UWRMSRrr:
18543 case UWRMSRrr_EVEX:
18544 return true;
18545 }
18546 return false;
18547}
18548
18549bool isLGS(unsigned Opcode) {
18550 switch (Opcode) {
18551 case LGS16rm:
18552 case LGS32rm:
18553 case LGS64rm:
18554 return true;
18555 }
18556 return false;
18557}
18558
18559bool isVMOVNTPD(unsigned Opcode) {
18560 switch (Opcode) {
18561 case VMOVNTPDYmr:
18562 case VMOVNTPDZ128mr:
18563 case VMOVNTPDZ256mr:
18564 case VMOVNTPDZmr:
18565 case VMOVNTPDmr:
18566 return true;
18567 }
18568 return false;
18569}
18570
18571bool isRDPRU(unsigned Opcode) {
18572 return Opcode == RDPRU;
18573}
18574
18575bool isVPUNPCKHBW(unsigned Opcode) {
18576 switch (Opcode) {
18577 case VPUNPCKHBWYrm:
18578 case VPUNPCKHBWYrr:
18579 case VPUNPCKHBWZ128rm:
18580 case VPUNPCKHBWZ128rmk:
18581 case VPUNPCKHBWZ128rmkz:
18582 case VPUNPCKHBWZ128rr:
18583 case VPUNPCKHBWZ128rrk:
18584 case VPUNPCKHBWZ128rrkz:
18585 case VPUNPCKHBWZ256rm:
18586 case VPUNPCKHBWZ256rmk:
18587 case VPUNPCKHBWZ256rmkz:
18588 case VPUNPCKHBWZ256rr:
18589 case VPUNPCKHBWZ256rrk:
18590 case VPUNPCKHBWZ256rrkz:
18591 case VPUNPCKHBWZrm:
18592 case VPUNPCKHBWZrmk:
18593 case VPUNPCKHBWZrmkz:
18594 case VPUNPCKHBWZrr:
18595 case VPUNPCKHBWZrrk:
18596 case VPUNPCKHBWZrrkz:
18597 case VPUNPCKHBWrm:
18598 case VPUNPCKHBWrr:
18599 return true;
18600 }
18601 return false;
18602}
18603
18604bool isVUCOMXSD(unsigned Opcode) {
18605 switch (Opcode) {
18606 case VUCOMXSDZrm_Int:
18607 case VUCOMXSDZrr_Int:
18608 case VUCOMXSDZrrb_Int:
18609 return true;
18610 }
18611 return false;
18612}
18613
18614bool isANDN(unsigned Opcode) {
18615 switch (Opcode) {
18616 case ANDN32rm:
18617 case ANDN32rm_EVEX:
18618 case ANDN32rm_NF:
18619 case ANDN32rr:
18620 case ANDN32rr_EVEX:
18621 case ANDN32rr_NF:
18622 case ANDN64rm:
18623 case ANDN64rm_EVEX:
18624 case ANDN64rm_NF:
18625 case ANDN64rr:
18626 case ANDN64rr_EVEX:
18627 case ANDN64rr_NF:
18628 return true;
18629 }
18630 return false;
18631}
18632
18633bool isVCVTTPH2UW(unsigned Opcode) {
18634 switch (Opcode) {
18635 case VCVTTPH2UWZ128rm:
18636 case VCVTTPH2UWZ128rmb:
18637 case VCVTTPH2UWZ128rmbk:
18638 case VCVTTPH2UWZ128rmbkz:
18639 case VCVTTPH2UWZ128rmk:
18640 case VCVTTPH2UWZ128rmkz:
18641 case VCVTTPH2UWZ128rr:
18642 case VCVTTPH2UWZ128rrk:
18643 case VCVTTPH2UWZ128rrkz:
18644 case VCVTTPH2UWZ256rm:
18645 case VCVTTPH2UWZ256rmb:
18646 case VCVTTPH2UWZ256rmbk:
18647 case VCVTTPH2UWZ256rmbkz:
18648 case VCVTTPH2UWZ256rmk:
18649 case VCVTTPH2UWZ256rmkz:
18650 case VCVTTPH2UWZ256rr:
18651 case VCVTTPH2UWZ256rrk:
18652 case VCVTTPH2UWZ256rrkz:
18653 case VCVTTPH2UWZrm:
18654 case VCVTTPH2UWZrmb:
18655 case VCVTTPH2UWZrmbk:
18656 case VCVTTPH2UWZrmbkz:
18657 case VCVTTPH2UWZrmk:
18658 case VCVTTPH2UWZrmkz:
18659 case VCVTTPH2UWZrr:
18660 case VCVTTPH2UWZrrb:
18661 case VCVTTPH2UWZrrbk:
18662 case VCVTTPH2UWZrrbkz:
18663 case VCVTTPH2UWZrrk:
18664 case VCVTTPH2UWZrrkz:
18665 return true;
18666 }
18667 return false;
18668}
18669
18670bool isVMFUNC(unsigned Opcode) {
18671 return Opcode == VMFUNC;
18672}
18673
18674bool isFIMUL(unsigned Opcode) {
18675 switch (Opcode) {
18676 case MUL_FI16m:
18677 case MUL_FI32m:
18678 return true;
18679 }
18680 return false;
18681}
18682
18683bool isBLCFILL(unsigned Opcode) {
18684 switch (Opcode) {
18685 case BLCFILL32rm:
18686 case BLCFILL32rr:
18687 case BLCFILL64rm:
18688 case BLCFILL64rr:
18689 return true;
18690 }
18691 return false;
18692}
18693
18694bool isVGATHERPF0DPS(unsigned Opcode) {
18695 return Opcode == VGATHERPF0DPSm;
18696}
18697
18698bool isVFMSUBADD231PS(unsigned Opcode) {
18699 switch (Opcode) {
18700 case VFMSUBADD231PSYm:
18701 case VFMSUBADD231PSYr:
18702 case VFMSUBADD231PSZ128m:
18703 case VFMSUBADD231PSZ128mb:
18704 case VFMSUBADD231PSZ128mbk:
18705 case VFMSUBADD231PSZ128mbkz:
18706 case VFMSUBADD231PSZ128mk:
18707 case VFMSUBADD231PSZ128mkz:
18708 case VFMSUBADD231PSZ128r:
18709 case VFMSUBADD231PSZ128rk:
18710 case VFMSUBADD231PSZ128rkz:
18711 case VFMSUBADD231PSZ256m:
18712 case VFMSUBADD231PSZ256mb:
18713 case VFMSUBADD231PSZ256mbk:
18714 case VFMSUBADD231PSZ256mbkz:
18715 case VFMSUBADD231PSZ256mk:
18716 case VFMSUBADD231PSZ256mkz:
18717 case VFMSUBADD231PSZ256r:
18718 case VFMSUBADD231PSZ256rk:
18719 case VFMSUBADD231PSZ256rkz:
18720 case VFMSUBADD231PSZm:
18721 case VFMSUBADD231PSZmb:
18722 case VFMSUBADD231PSZmbk:
18723 case VFMSUBADD231PSZmbkz:
18724 case VFMSUBADD231PSZmk:
18725 case VFMSUBADD231PSZmkz:
18726 case VFMSUBADD231PSZr:
18727 case VFMSUBADD231PSZrb:
18728 case VFMSUBADD231PSZrbk:
18729 case VFMSUBADD231PSZrbkz:
18730 case VFMSUBADD231PSZrk:
18731 case VFMSUBADD231PSZrkz:
18732 case VFMSUBADD231PSm:
18733 case VFMSUBADD231PSr:
18734 return true;
18735 }
18736 return false;
18737}
18738
18739bool isVREDUCESD(unsigned Opcode) {
18740 switch (Opcode) {
18741 case VREDUCESDZrmi:
18742 case VREDUCESDZrmik:
18743 case VREDUCESDZrmikz:
18744 case VREDUCESDZrri:
18745 case VREDUCESDZrrib:
18746 case VREDUCESDZrribk:
18747 case VREDUCESDZrribkz:
18748 case VREDUCESDZrrik:
18749 case VREDUCESDZrrikz:
18750 return true;
18751 }
18752 return false;
18753}
18754
18755bool isVCOMXSH(unsigned Opcode) {
18756 switch (Opcode) {
18757 case VCOMXSHZrm_Int:
18758 case VCOMXSHZrr_Int:
18759 case VCOMXSHZrrb_Int:
18760 return true;
18761 }
18762 return false;
18763}
18764
18765bool isVXORPS(unsigned Opcode) {
18766 switch (Opcode) {
18767 case VXORPSYrm:
18768 case VXORPSYrr:
18769 case VXORPSZ128rm:
18770 case VXORPSZ128rmb:
18771 case VXORPSZ128rmbk:
18772 case VXORPSZ128rmbkz:
18773 case VXORPSZ128rmk:
18774 case VXORPSZ128rmkz:
18775 case VXORPSZ128rr:
18776 case VXORPSZ128rrk:
18777 case VXORPSZ128rrkz:
18778 case VXORPSZ256rm:
18779 case VXORPSZ256rmb:
18780 case VXORPSZ256rmbk:
18781 case VXORPSZ256rmbkz:
18782 case VXORPSZ256rmk:
18783 case VXORPSZ256rmkz:
18784 case VXORPSZ256rr:
18785 case VXORPSZ256rrk:
18786 case VXORPSZ256rrkz:
18787 case VXORPSZrm:
18788 case VXORPSZrmb:
18789 case VXORPSZrmbk:
18790 case VXORPSZrmbkz:
18791 case VXORPSZrmk:
18792 case VXORPSZrmkz:
18793 case VXORPSZrr:
18794 case VXORPSZrrk:
18795 case VXORPSZrrkz:
18796 case VXORPSrm:
18797 case VXORPSrr:
18798 return true;
18799 }
18800 return false;
18801}
18802
18803bool isPSWAPD(unsigned Opcode) {
18804 switch (Opcode) {
18805 case PSWAPDrm:
18806 case PSWAPDrr:
18807 return true;
18808 }
18809 return false;
18810}
18811
18812bool isPMAXSD(unsigned Opcode) {
18813 switch (Opcode) {
18814 case PMAXSDrm:
18815 case PMAXSDrr:
18816 return true;
18817 }
18818 return false;
18819}
18820
18821bool isVCMPSS(unsigned Opcode) {
18822 switch (Opcode) {
18823 case VCMPSSZrmi_Int:
18824 case VCMPSSZrmik_Int:
18825 case VCMPSSZrri_Int:
18826 case VCMPSSZrrib_Int:
18827 case VCMPSSZrribk_Int:
18828 case VCMPSSZrrik_Int:
18829 case VCMPSSrmi_Int:
18830 case VCMPSSrri_Int:
18831 return true;
18832 }
18833 return false;
18834}
18835
18836bool isEXTRACTPS(unsigned Opcode) {
18837 switch (Opcode) {
18838 case EXTRACTPSmri:
18839 case EXTRACTPSrri:
18840 return true;
18841 }
18842 return false;
18843}
18844
18845bool isVPMOVZXBD(unsigned Opcode) {
18846 switch (Opcode) {
18847 case VPMOVZXBDYrm:
18848 case VPMOVZXBDYrr:
18849 case VPMOVZXBDZ128rm:
18850 case VPMOVZXBDZ128rmk:
18851 case VPMOVZXBDZ128rmkz:
18852 case VPMOVZXBDZ128rr:
18853 case VPMOVZXBDZ128rrk:
18854 case VPMOVZXBDZ128rrkz:
18855 case VPMOVZXBDZ256rm:
18856 case VPMOVZXBDZ256rmk:
18857 case VPMOVZXBDZ256rmkz:
18858 case VPMOVZXBDZ256rr:
18859 case VPMOVZXBDZ256rrk:
18860 case VPMOVZXBDZ256rrkz:
18861 case VPMOVZXBDZrm:
18862 case VPMOVZXBDZrmk:
18863 case VPMOVZXBDZrmkz:
18864 case VPMOVZXBDZrr:
18865 case VPMOVZXBDZrrk:
18866 case VPMOVZXBDZrrkz:
18867 case VPMOVZXBDrm:
18868 case VPMOVZXBDrr:
18869 return true;
18870 }
18871 return false;
18872}
18873
18874bool isOUTSW(unsigned Opcode) {
18875 return Opcode == OUTSW;
18876}
18877
18878bool isKORTESTB(unsigned Opcode) {
18879 return Opcode == KORTESTBkk;
18880}
18881
18882bool isVREDUCEPS(unsigned Opcode) {
18883 switch (Opcode) {
18884 case VREDUCEPSZ128rmbi:
18885 case VREDUCEPSZ128rmbik:
18886 case VREDUCEPSZ128rmbikz:
18887 case VREDUCEPSZ128rmi:
18888 case VREDUCEPSZ128rmik:
18889 case VREDUCEPSZ128rmikz:
18890 case VREDUCEPSZ128rri:
18891 case VREDUCEPSZ128rrik:
18892 case VREDUCEPSZ128rrikz:
18893 case VREDUCEPSZ256rmbi:
18894 case VREDUCEPSZ256rmbik:
18895 case VREDUCEPSZ256rmbikz:
18896 case VREDUCEPSZ256rmi:
18897 case VREDUCEPSZ256rmik:
18898 case VREDUCEPSZ256rmikz:
18899 case VREDUCEPSZ256rri:
18900 case VREDUCEPSZ256rrik:
18901 case VREDUCEPSZ256rrikz:
18902 case VREDUCEPSZrmbi:
18903 case VREDUCEPSZrmbik:
18904 case VREDUCEPSZrmbikz:
18905 case VREDUCEPSZrmi:
18906 case VREDUCEPSZrmik:
18907 case VREDUCEPSZrmikz:
18908 case VREDUCEPSZrri:
18909 case VREDUCEPSZrrib:
18910 case VREDUCEPSZrribk:
18911 case VREDUCEPSZrribkz:
18912 case VREDUCEPSZrrik:
18913 case VREDUCEPSZrrikz:
18914 return true;
18915 }
18916 return false;
18917}
18918
18919bool isPEXTRW(unsigned Opcode) {
18920 switch (Opcode) {
18921 case MMX_PEXTRWrri:
18922 case PEXTRWmri:
18923 case PEXTRWrri:
18924 case PEXTRWrri_REV:
18925 return true;
18926 }
18927 return false;
18928}
18929
18930bool isFNINIT(unsigned Opcode) {
18931 return Opcode == FNINIT;
18932}
18933
18934bool isVCVTPH2IBS(unsigned Opcode) {
18935 switch (Opcode) {
18936 case VCVTPH2IBSZ128rm:
18937 case VCVTPH2IBSZ128rmb:
18938 case VCVTPH2IBSZ128rmbk:
18939 case VCVTPH2IBSZ128rmbkz:
18940 case VCVTPH2IBSZ128rmk:
18941 case VCVTPH2IBSZ128rmkz:
18942 case VCVTPH2IBSZ128rr:
18943 case VCVTPH2IBSZ128rrk:
18944 case VCVTPH2IBSZ128rrkz:
18945 case VCVTPH2IBSZ256rm:
18946 case VCVTPH2IBSZ256rmb:
18947 case VCVTPH2IBSZ256rmbk:
18948 case VCVTPH2IBSZ256rmbkz:
18949 case VCVTPH2IBSZ256rmk:
18950 case VCVTPH2IBSZ256rmkz:
18951 case VCVTPH2IBSZ256rr:
18952 case VCVTPH2IBSZ256rrk:
18953 case VCVTPH2IBSZ256rrkz:
18954 case VCVTPH2IBSZrm:
18955 case VCVTPH2IBSZrmb:
18956 case VCVTPH2IBSZrmbk:
18957 case VCVTPH2IBSZrmbkz:
18958 case VCVTPH2IBSZrmk:
18959 case VCVTPH2IBSZrmkz:
18960 case VCVTPH2IBSZrr:
18961 case VCVTPH2IBSZrrb:
18962 case VCVTPH2IBSZrrbk:
18963 case VCVTPH2IBSZrrbkz:
18964 case VCVTPH2IBSZrrk:
18965 case VCVTPH2IBSZrrkz:
18966 return true;
18967 }
18968 return false;
18969}
18970
18971bool isROL(unsigned Opcode) {
18972 switch (Opcode) {
18973 case ROL16m1:
18974 case ROL16m1_EVEX:
18975 case ROL16m1_ND:
18976 case ROL16m1_NF:
18977 case ROL16m1_NF_ND:
18978 case ROL16mCL:
18979 case ROL16mCL_EVEX:
18980 case ROL16mCL_ND:
18981 case ROL16mCL_NF:
18982 case ROL16mCL_NF_ND:
18983 case ROL16mi:
18984 case ROL16mi_EVEX:
18985 case ROL16mi_ND:
18986 case ROL16mi_NF:
18987 case ROL16mi_NF_ND:
18988 case ROL16r1:
18989 case ROL16r1_EVEX:
18990 case ROL16r1_ND:
18991 case ROL16r1_NF:
18992 case ROL16r1_NF_ND:
18993 case ROL16rCL:
18994 case ROL16rCL_EVEX:
18995 case ROL16rCL_ND:
18996 case ROL16rCL_NF:
18997 case ROL16rCL_NF_ND:
18998 case ROL16ri:
18999 case ROL16ri_EVEX:
19000 case ROL16ri_ND:
19001 case ROL16ri_NF:
19002 case ROL16ri_NF_ND:
19003 case ROL32m1:
19004 case ROL32m1_EVEX:
19005 case ROL32m1_ND:
19006 case ROL32m1_NF:
19007 case ROL32m1_NF_ND:
19008 case ROL32mCL:
19009 case ROL32mCL_EVEX:
19010 case ROL32mCL_ND:
19011 case ROL32mCL_NF:
19012 case ROL32mCL_NF_ND:
19013 case ROL32mi:
19014 case ROL32mi_EVEX:
19015 case ROL32mi_ND:
19016 case ROL32mi_NF:
19017 case ROL32mi_NF_ND:
19018 case ROL32r1:
19019 case ROL32r1_EVEX:
19020 case ROL32r1_ND:
19021 case ROL32r1_NF:
19022 case ROL32r1_NF_ND:
19023 case ROL32rCL:
19024 case ROL32rCL_EVEX:
19025 case ROL32rCL_ND:
19026 case ROL32rCL_NF:
19027 case ROL32rCL_NF_ND:
19028 case ROL32ri:
19029 case ROL32ri_EVEX:
19030 case ROL32ri_ND:
19031 case ROL32ri_NF:
19032 case ROL32ri_NF_ND:
19033 case ROL64m1:
19034 case ROL64m1_EVEX:
19035 case ROL64m1_ND:
19036 case ROL64m1_NF:
19037 case ROL64m1_NF_ND:
19038 case ROL64mCL:
19039 case ROL64mCL_EVEX:
19040 case ROL64mCL_ND:
19041 case ROL64mCL_NF:
19042 case ROL64mCL_NF_ND:
19043 case ROL64mi:
19044 case ROL64mi_EVEX:
19045 case ROL64mi_ND:
19046 case ROL64mi_NF:
19047 case ROL64mi_NF_ND:
19048 case ROL64r1:
19049 case ROL64r1_EVEX:
19050 case ROL64r1_ND:
19051 case ROL64r1_NF:
19052 case ROL64r1_NF_ND:
19053 case ROL64rCL:
19054 case ROL64rCL_EVEX:
19055 case ROL64rCL_ND:
19056 case ROL64rCL_NF:
19057 case ROL64rCL_NF_ND:
19058 case ROL64ri:
19059 case ROL64ri_EVEX:
19060 case ROL64ri_ND:
19061 case ROL64ri_NF:
19062 case ROL64ri_NF_ND:
19063 case ROL8m1:
19064 case ROL8m1_EVEX:
19065 case ROL8m1_ND:
19066 case ROL8m1_NF:
19067 case ROL8m1_NF_ND:
19068 case ROL8mCL:
19069 case ROL8mCL_EVEX:
19070 case ROL8mCL_ND:
19071 case ROL8mCL_NF:
19072 case ROL8mCL_NF_ND:
19073 case ROL8mi:
19074 case ROL8mi_EVEX:
19075 case ROL8mi_ND:
19076 case ROL8mi_NF:
19077 case ROL8mi_NF_ND:
19078 case ROL8r1:
19079 case ROL8r1_EVEX:
19080 case ROL8r1_ND:
19081 case ROL8r1_NF:
19082 case ROL8r1_NF_ND:
19083 case ROL8rCL:
19084 case ROL8rCL_EVEX:
19085 case ROL8rCL_ND:
19086 case ROL8rCL_NF:
19087 case ROL8rCL_NF_ND:
19088 case ROL8ri:
19089 case ROL8ri_EVEX:
19090 case ROL8ri_ND:
19091 case ROL8ri_NF:
19092 case ROL8ri_NF_ND:
19093 return true;
19094 }
19095 return false;
19096}
19097
19098bool isVCVTPS2QQ(unsigned Opcode) {
19099 switch (Opcode) {
19100 case VCVTPS2QQZ128rm:
19101 case VCVTPS2QQZ128rmb:
19102 case VCVTPS2QQZ128rmbk:
19103 case VCVTPS2QQZ128rmbkz:
19104 case VCVTPS2QQZ128rmk:
19105 case VCVTPS2QQZ128rmkz:
19106 case VCVTPS2QQZ128rr:
19107 case VCVTPS2QQZ128rrk:
19108 case VCVTPS2QQZ128rrkz:
19109 case VCVTPS2QQZ256rm:
19110 case VCVTPS2QQZ256rmb:
19111 case VCVTPS2QQZ256rmbk:
19112 case VCVTPS2QQZ256rmbkz:
19113 case VCVTPS2QQZ256rmk:
19114 case VCVTPS2QQZ256rmkz:
19115 case VCVTPS2QQZ256rr:
19116 case VCVTPS2QQZ256rrk:
19117 case VCVTPS2QQZ256rrkz:
19118 case VCVTPS2QQZrm:
19119 case VCVTPS2QQZrmb:
19120 case VCVTPS2QQZrmbk:
19121 case VCVTPS2QQZrmbkz:
19122 case VCVTPS2QQZrmk:
19123 case VCVTPS2QQZrmkz:
19124 case VCVTPS2QQZrr:
19125 case VCVTPS2QQZrrb:
19126 case VCVTPS2QQZrrbk:
19127 case VCVTPS2QQZrrbkz:
19128 case VCVTPS2QQZrrk:
19129 case VCVTPS2QQZrrkz:
19130 return true;
19131 }
19132 return false;
19133}
19134
19135bool isVGETMANTPH(unsigned Opcode) {
19136 switch (Opcode) {
19137 case VGETMANTPHZ128rmbi:
19138 case VGETMANTPHZ128rmbik:
19139 case VGETMANTPHZ128rmbikz:
19140 case VGETMANTPHZ128rmi:
19141 case VGETMANTPHZ128rmik:
19142 case VGETMANTPHZ128rmikz:
19143 case VGETMANTPHZ128rri:
19144 case VGETMANTPHZ128rrik:
19145 case VGETMANTPHZ128rrikz:
19146 case VGETMANTPHZ256rmbi:
19147 case VGETMANTPHZ256rmbik:
19148 case VGETMANTPHZ256rmbikz:
19149 case VGETMANTPHZ256rmi:
19150 case VGETMANTPHZ256rmik:
19151 case VGETMANTPHZ256rmikz:
19152 case VGETMANTPHZ256rri:
19153 case VGETMANTPHZ256rrik:
19154 case VGETMANTPHZ256rrikz:
19155 case VGETMANTPHZrmbi:
19156 case VGETMANTPHZrmbik:
19157 case VGETMANTPHZrmbikz:
19158 case VGETMANTPHZrmi:
19159 case VGETMANTPHZrmik:
19160 case VGETMANTPHZrmikz:
19161 case VGETMANTPHZrri:
19162 case VGETMANTPHZrrib:
19163 case VGETMANTPHZrribk:
19164 case VGETMANTPHZrribkz:
19165 case VGETMANTPHZrrik:
19166 case VGETMANTPHZrrikz:
19167 return true;
19168 }
19169 return false;
19170}
19171
19172bool isPUNPCKLDQ(unsigned Opcode) {
19173 switch (Opcode) {
19174 case MMX_PUNPCKLDQrm:
19175 case MMX_PUNPCKLDQrr:
19176 case PUNPCKLDQrm:
19177 case PUNPCKLDQrr:
19178 return true;
19179 }
19180 return false;
19181}
19182
19183bool isPADDD(unsigned Opcode) {
19184 switch (Opcode) {
19185 case MMX_PADDDrm:
19186 case MMX_PADDDrr:
19187 case PADDDrm:
19188 case PADDDrr:
19189 return true;
19190 }
19191 return false;
19192}
19193
19194bool isVPSLLD(unsigned Opcode) {
19195 switch (Opcode) {
19196 case VPSLLDYri:
19197 case VPSLLDYrm:
19198 case VPSLLDYrr:
19199 case VPSLLDZ128mbi:
19200 case VPSLLDZ128mbik:
19201 case VPSLLDZ128mbikz:
19202 case VPSLLDZ128mi:
19203 case VPSLLDZ128mik:
19204 case VPSLLDZ128mikz:
19205 case VPSLLDZ128ri:
19206 case VPSLLDZ128rik:
19207 case VPSLLDZ128rikz:
19208 case VPSLLDZ128rm:
19209 case VPSLLDZ128rmk:
19210 case VPSLLDZ128rmkz:
19211 case VPSLLDZ128rr:
19212 case VPSLLDZ128rrk:
19213 case VPSLLDZ128rrkz:
19214 case VPSLLDZ256mbi:
19215 case VPSLLDZ256mbik:
19216 case VPSLLDZ256mbikz:
19217 case VPSLLDZ256mi:
19218 case VPSLLDZ256mik:
19219 case VPSLLDZ256mikz:
19220 case VPSLLDZ256ri:
19221 case VPSLLDZ256rik:
19222 case VPSLLDZ256rikz:
19223 case VPSLLDZ256rm:
19224 case VPSLLDZ256rmk:
19225 case VPSLLDZ256rmkz:
19226 case VPSLLDZ256rr:
19227 case VPSLLDZ256rrk:
19228 case VPSLLDZ256rrkz:
19229 case VPSLLDZmbi:
19230 case VPSLLDZmbik:
19231 case VPSLLDZmbikz:
19232 case VPSLLDZmi:
19233 case VPSLLDZmik:
19234 case VPSLLDZmikz:
19235 case VPSLLDZri:
19236 case VPSLLDZrik:
19237 case VPSLLDZrikz:
19238 case VPSLLDZrm:
19239 case VPSLLDZrmk:
19240 case VPSLLDZrmkz:
19241 case VPSLLDZrr:
19242 case VPSLLDZrrk:
19243 case VPSLLDZrrkz:
19244 case VPSLLDri:
19245 case VPSLLDrm:
19246 case VPSLLDrr:
19247 return true;
19248 }
19249 return false;
19250}
19251
19252bool isPFCMPGE(unsigned Opcode) {
19253 switch (Opcode) {
19254 case PFCMPGErm:
19255 case PFCMPGErr:
19256 return true;
19257 }
19258 return false;
19259}
19260
19261bool isVGETMANTBF16(unsigned Opcode) {
19262 switch (Opcode) {
19263 case VGETMANTBF16Z128rmbi:
19264 case VGETMANTBF16Z128rmbik:
19265 case VGETMANTBF16Z128rmbikz:
19266 case VGETMANTBF16Z128rmi:
19267 case VGETMANTBF16Z128rmik:
19268 case VGETMANTBF16Z128rmikz:
19269 case VGETMANTBF16Z128rri:
19270 case VGETMANTBF16Z128rrik:
19271 case VGETMANTBF16Z128rrikz:
19272 case VGETMANTBF16Z256rmbi:
19273 case VGETMANTBF16Z256rmbik:
19274 case VGETMANTBF16Z256rmbikz:
19275 case VGETMANTBF16Z256rmi:
19276 case VGETMANTBF16Z256rmik:
19277 case VGETMANTBF16Z256rmikz:
19278 case VGETMANTBF16Z256rri:
19279 case VGETMANTBF16Z256rrik:
19280 case VGETMANTBF16Z256rrikz:
19281 case VGETMANTBF16Zrmbi:
19282 case VGETMANTBF16Zrmbik:
19283 case VGETMANTBF16Zrmbikz:
19284 case VGETMANTBF16Zrmi:
19285 case VGETMANTBF16Zrmik:
19286 case VGETMANTBF16Zrmikz:
19287 case VGETMANTBF16Zrri:
19288 case VGETMANTBF16Zrrik:
19289 case VGETMANTBF16Zrrikz:
19290 return true;
19291 }
19292 return false;
19293}
19294
19295bool isVSUBBF16(unsigned Opcode) {
19296 switch (Opcode) {
19297 case VSUBBF16Z128rm:
19298 case VSUBBF16Z128rmb:
19299 case VSUBBF16Z128rmbk:
19300 case VSUBBF16Z128rmbkz:
19301 case VSUBBF16Z128rmk:
19302 case VSUBBF16Z128rmkz:
19303 case VSUBBF16Z128rr:
19304 case VSUBBF16Z128rrk:
19305 case VSUBBF16Z128rrkz:
19306 case VSUBBF16Z256rm:
19307 case VSUBBF16Z256rmb:
19308 case VSUBBF16Z256rmbk:
19309 case VSUBBF16Z256rmbkz:
19310 case VSUBBF16Z256rmk:
19311 case VSUBBF16Z256rmkz:
19312 case VSUBBF16Z256rr:
19313 case VSUBBF16Z256rrk:
19314 case VSUBBF16Z256rrkz:
19315 case VSUBBF16Zrm:
19316 case VSUBBF16Zrmb:
19317 case VSUBBF16Zrmbk:
19318 case VSUBBF16Zrmbkz:
19319 case VSUBBF16Zrmk:
19320 case VSUBBF16Zrmkz:
19321 case VSUBBF16Zrr:
19322 case VSUBBF16Zrrk:
19323 case VSUBBF16Zrrkz:
19324 return true;
19325 }
19326 return false;
19327}
19328
19329bool isVPMOVM2D(unsigned Opcode) {
19330 switch (Opcode) {
19331 case VPMOVM2DZ128rk:
19332 case VPMOVM2DZ256rk:
19333 case VPMOVM2DZrk:
19334 return true;
19335 }
19336 return false;
19337}
19338
19339bool isVCVTTSS2USIS(unsigned Opcode) {
19340 switch (Opcode) {
19341 case VCVTTSS2USI64Srm_Int:
19342 case VCVTTSS2USI64Srr_Int:
19343 case VCVTTSS2USI64Srrb_Int:
19344 case VCVTTSS2USISrm_Int:
19345 case VCVTTSS2USISrr_Int:
19346 case VCVTTSS2USISrrb_Int:
19347 return true;
19348 }
19349 return false;
19350}
19351
19352bool isVHSUBPS(unsigned Opcode) {
19353 switch (Opcode) {
19354 case VHSUBPSYrm:
19355 case VHSUBPSYrr:
19356 case VHSUBPSrm:
19357 case VHSUBPSrr:
19358 return true;
19359 }
19360 return false;
19361}
19362
19363bool isENDBR32(unsigned Opcode) {
19364 return Opcode == ENDBR32;
19365}
19366
19367bool isMOVSXD(unsigned Opcode) {
19368 switch (Opcode) {
19369 case MOVSX16rm32:
19370 case MOVSX16rr32:
19371 case MOVSX32rm32:
19372 case MOVSX32rr32:
19373 case MOVSX64rm32:
19374 case MOVSX64rr32:
19375 return true;
19376 }
19377 return false;
19378}
19379
19380bool isPSIGND(unsigned Opcode) {
19381 switch (Opcode) {
19382 case MMX_PSIGNDrm:
19383 case MMX_PSIGNDrr:
19384 case PSIGNDrm:
19385 case PSIGNDrr:
19386 return true;
19387 }
19388 return false;
19389}
19390
19391bool isVPTEST(unsigned Opcode) {
19392 switch (Opcode) {
19393 case VPTESTYrm:
19394 case VPTESTYrr:
19395 case VPTESTrm:
19396 case VPTESTrr:
19397 return true;
19398 }
19399 return false;
19400}
19401
19402bool isVPDPWUSD(unsigned Opcode) {
19403 switch (Opcode) {
19404 case VPDPWUSDYrm:
19405 case VPDPWUSDYrr:
19406 case VPDPWUSDZ128rm:
19407 case VPDPWUSDZ128rmb:
19408 case VPDPWUSDZ128rmbk:
19409 case VPDPWUSDZ128rmbkz:
19410 case VPDPWUSDZ128rmk:
19411 case VPDPWUSDZ128rmkz:
19412 case VPDPWUSDZ128rr:
19413 case VPDPWUSDZ128rrk:
19414 case VPDPWUSDZ128rrkz:
19415 case VPDPWUSDZ256rm:
19416 case VPDPWUSDZ256rmb:
19417 case VPDPWUSDZ256rmbk:
19418 case VPDPWUSDZ256rmbkz:
19419 case VPDPWUSDZ256rmk:
19420 case VPDPWUSDZ256rmkz:
19421 case VPDPWUSDZ256rr:
19422 case VPDPWUSDZ256rrk:
19423 case VPDPWUSDZ256rrkz:
19424 case VPDPWUSDZrm:
19425 case VPDPWUSDZrmb:
19426 case VPDPWUSDZrmbk:
19427 case VPDPWUSDZrmbkz:
19428 case VPDPWUSDZrmk:
19429 case VPDPWUSDZrmkz:
19430 case VPDPWUSDZrr:
19431 case VPDPWUSDZrrk:
19432 case VPDPWUSDZrrkz:
19433 case VPDPWUSDrm:
19434 case VPDPWUSDrr:
19435 return true;
19436 }
19437 return false;
19438}
19439
19440bool isHSUBPD(unsigned Opcode) {
19441 switch (Opcode) {
19442 case HSUBPDrm:
19443 case HSUBPDrr:
19444 return true;
19445 }
19446 return false;
19447}
19448
19449bool isADCX(unsigned Opcode) {
19450 switch (Opcode) {
19451 case ADCX32rm:
19452 case ADCX32rm_EVEX:
19453 case ADCX32rm_ND:
19454 case ADCX32rr:
19455 case ADCX32rr_EVEX:
19456 case ADCX32rr_ND:
19457 case ADCX64rm:
19458 case ADCX64rm_EVEX:
19459 case ADCX64rm_ND:
19460 case ADCX64rr:
19461 case ADCX64rr_EVEX:
19462 case ADCX64rr_ND:
19463 return true;
19464 }
19465 return false;
19466}
19467
19468bool isCVTTPD2PI(unsigned Opcode) {
19469 switch (Opcode) {
19470 case MMX_CVTTPD2PIrm:
19471 case MMX_CVTTPD2PIrr:
19472 return true;
19473 }
19474 return false;
19475}
19476
19477bool isPDEP(unsigned Opcode) {
19478 switch (Opcode) {
19479 case PDEP32rm:
19480 case PDEP32rm_EVEX:
19481 case PDEP32rr:
19482 case PDEP32rr_EVEX:
19483 case PDEP64rm:
19484 case PDEP64rm_EVEX:
19485 case PDEP64rr:
19486 case PDEP64rr_EVEX:
19487 return true;
19488 }
19489 return false;
19490}
19491
19492bool isTDPBUSD(unsigned Opcode) {
19493 return Opcode == TDPBUSD;
19494}
19495
19496bool isVCVTBIASPH2HF8S(unsigned Opcode) {
19497 switch (Opcode) {
19498 case VCVTBIASPH2HF8SZ128rm:
19499 case VCVTBIASPH2HF8SZ128rmb:
19500 case VCVTBIASPH2HF8SZ128rmbk:
19501 case VCVTBIASPH2HF8SZ128rmbkz:
19502 case VCVTBIASPH2HF8SZ128rmk:
19503 case VCVTBIASPH2HF8SZ128rmkz:
19504 case VCVTBIASPH2HF8SZ128rr:
19505 case VCVTBIASPH2HF8SZ128rrk:
19506 case VCVTBIASPH2HF8SZ128rrkz:
19507 case VCVTBIASPH2HF8SZ256rm:
19508 case VCVTBIASPH2HF8SZ256rmb:
19509 case VCVTBIASPH2HF8SZ256rmbk:
19510 case VCVTBIASPH2HF8SZ256rmbkz:
19511 case VCVTBIASPH2HF8SZ256rmk:
19512 case VCVTBIASPH2HF8SZ256rmkz:
19513 case VCVTBIASPH2HF8SZ256rr:
19514 case VCVTBIASPH2HF8SZ256rrk:
19515 case VCVTBIASPH2HF8SZ256rrkz:
19516 case VCVTBIASPH2HF8SZrm:
19517 case VCVTBIASPH2HF8SZrmb:
19518 case VCVTBIASPH2HF8SZrmbk:
19519 case VCVTBIASPH2HF8SZrmbkz:
19520 case VCVTBIASPH2HF8SZrmk:
19521 case VCVTBIASPH2HF8SZrmkz:
19522 case VCVTBIASPH2HF8SZrr:
19523 case VCVTBIASPH2HF8SZrrk:
19524 case VCVTBIASPH2HF8SZrrkz:
19525 return true;
19526 }
19527 return false;
19528}
19529
19530bool isVBROADCASTI32X4(unsigned Opcode) {
19531 switch (Opcode) {
19532 case VBROADCASTI32X4Z256rm:
19533 case VBROADCASTI32X4Z256rmk:
19534 case VBROADCASTI32X4Z256rmkz:
19535 case VBROADCASTI32X4Zrm:
19536 case VBROADCASTI32X4Zrmk:
19537 case VBROADCASTI32X4Zrmkz:
19538 return true;
19539 }
19540 return false;
19541}
19542
19543bool isVCVTPH2UDQ(unsigned Opcode) {
19544 switch (Opcode) {
19545 case VCVTPH2UDQZ128rm:
19546 case VCVTPH2UDQZ128rmb:
19547 case VCVTPH2UDQZ128rmbk:
19548 case VCVTPH2UDQZ128rmbkz:
19549 case VCVTPH2UDQZ128rmk:
19550 case VCVTPH2UDQZ128rmkz:
19551 case VCVTPH2UDQZ128rr:
19552 case VCVTPH2UDQZ128rrk:
19553 case VCVTPH2UDQZ128rrkz:
19554 case VCVTPH2UDQZ256rm:
19555 case VCVTPH2UDQZ256rmb:
19556 case VCVTPH2UDQZ256rmbk:
19557 case VCVTPH2UDQZ256rmbkz:
19558 case VCVTPH2UDQZ256rmk:
19559 case VCVTPH2UDQZ256rmkz:
19560 case VCVTPH2UDQZ256rr:
19561 case VCVTPH2UDQZ256rrk:
19562 case VCVTPH2UDQZ256rrkz:
19563 case VCVTPH2UDQZrm:
19564 case VCVTPH2UDQZrmb:
19565 case VCVTPH2UDQZrmbk:
19566 case VCVTPH2UDQZrmbkz:
19567 case VCVTPH2UDQZrmk:
19568 case VCVTPH2UDQZrmkz:
19569 case VCVTPH2UDQZrr:
19570 case VCVTPH2UDQZrrb:
19571 case VCVTPH2UDQZrrbk:
19572 case VCVTPH2UDQZrrbkz:
19573 case VCVTPH2UDQZrrk:
19574 case VCVTPH2UDQZrrkz:
19575 return true;
19576 }
19577 return false;
19578}
19579
19580bool isVPHADDW(unsigned Opcode) {
19581 switch (Opcode) {
19582 case VPHADDWYrm:
19583 case VPHADDWYrr:
19584 case VPHADDWrm:
19585 case VPHADDWrr:
19586 return true;
19587 }
19588 return false;
19589}
19590
19591bool isFLDL2E(unsigned Opcode) {
19592 return Opcode == FLDL2E;
19593}
19594
19595bool isCLZERO(unsigned Opcode) {
19596 switch (Opcode) {
19597 case CLZERO32r:
19598 case CLZERO64r:
19599 return true;
19600 }
19601 return false;
19602}
19603
19604bool isPBLENDW(unsigned Opcode) {
19605 switch (Opcode) {
19606 case PBLENDWrmi:
19607 case PBLENDWrri:
19608 return true;
19609 }
19610 return false;
19611}
19612
19613bool isVCVTBF162IUBS(unsigned Opcode) {
19614 switch (Opcode) {
19615 case VCVTBF162IUBSZ128rm:
19616 case VCVTBF162IUBSZ128rmb:
19617 case VCVTBF162IUBSZ128rmbk:
19618 case VCVTBF162IUBSZ128rmbkz:
19619 case VCVTBF162IUBSZ128rmk:
19620 case VCVTBF162IUBSZ128rmkz:
19621 case VCVTBF162IUBSZ128rr:
19622 case VCVTBF162IUBSZ128rrk:
19623 case VCVTBF162IUBSZ128rrkz:
19624 case VCVTBF162IUBSZ256rm:
19625 case VCVTBF162IUBSZ256rmb:
19626 case VCVTBF162IUBSZ256rmbk:
19627 case VCVTBF162IUBSZ256rmbkz:
19628 case VCVTBF162IUBSZ256rmk:
19629 case VCVTBF162IUBSZ256rmkz:
19630 case VCVTBF162IUBSZ256rr:
19631 case VCVTBF162IUBSZ256rrk:
19632 case VCVTBF162IUBSZ256rrkz:
19633 case VCVTBF162IUBSZrm:
19634 case VCVTBF162IUBSZrmb:
19635 case VCVTBF162IUBSZrmbk:
19636 case VCVTBF162IUBSZrmbkz:
19637 case VCVTBF162IUBSZrmk:
19638 case VCVTBF162IUBSZrmkz:
19639 case VCVTBF162IUBSZrr:
19640 case VCVTBF162IUBSZrrk:
19641 case VCVTBF162IUBSZrrkz:
19642 return true;
19643 }
19644 return false;
19645}
19646
19647bool isVCVTSH2USI(unsigned Opcode) {
19648 switch (Opcode) {
19649 case VCVTSH2USI64Zrm_Int:
19650 case VCVTSH2USI64Zrr_Int:
19651 case VCVTSH2USI64Zrrb_Int:
19652 case VCVTSH2USIZrm_Int:
19653 case VCVTSH2USIZrr_Int:
19654 case VCVTSH2USIZrrb_Int:
19655 return true;
19656 }
19657 return false;
19658}
19659
19660bool isVANDPD(unsigned Opcode) {
19661 switch (Opcode) {
19662 case VANDPDYrm:
19663 case VANDPDYrr:
19664 case VANDPDZ128rm:
19665 case VANDPDZ128rmb:
19666 case VANDPDZ128rmbk:
19667 case VANDPDZ128rmbkz:
19668 case VANDPDZ128rmk:
19669 case VANDPDZ128rmkz:
19670 case VANDPDZ128rr:
19671 case VANDPDZ128rrk:
19672 case VANDPDZ128rrkz:
19673 case VANDPDZ256rm:
19674 case VANDPDZ256rmb:
19675 case VANDPDZ256rmbk:
19676 case VANDPDZ256rmbkz:
19677 case VANDPDZ256rmk:
19678 case VANDPDZ256rmkz:
19679 case VANDPDZ256rr:
19680 case VANDPDZ256rrk:
19681 case VANDPDZ256rrkz:
19682 case VANDPDZrm:
19683 case VANDPDZrmb:
19684 case VANDPDZrmbk:
19685 case VANDPDZrmbkz:
19686 case VANDPDZrmk:
19687 case VANDPDZrmkz:
19688 case VANDPDZrr:
19689 case VANDPDZrrk:
19690 case VANDPDZrrkz:
19691 case VANDPDrm:
19692 case VANDPDrr:
19693 return true;
19694 }
19695 return false;
19696}
19697
19698bool isBEXTR(unsigned Opcode) {
19699 switch (Opcode) {
19700 case BEXTR32rm:
19701 case BEXTR32rm_EVEX:
19702 case BEXTR32rm_NF:
19703 case BEXTR32rr:
19704 case BEXTR32rr_EVEX:
19705 case BEXTR32rr_NF:
19706 case BEXTR64rm:
19707 case BEXTR64rm_EVEX:
19708 case BEXTR64rm_NF:
19709 case BEXTR64rr:
19710 case BEXTR64rr_EVEX:
19711 case BEXTR64rr_NF:
19712 case BEXTRI32mi:
19713 case BEXTRI32ri:
19714 case BEXTRI64mi:
19715 case BEXTRI64ri:
19716 return true;
19717 }
19718 return false;
19719}
19720
19721bool isSTD(unsigned Opcode) {
19722 return Opcode == STD;
19723}
19724
19725bool isVAESKEYGENASSIST(unsigned Opcode) {
19726 switch (Opcode) {
19727 case VAESKEYGENASSISTrmi:
19728 case VAESKEYGENASSISTrri:
19729 return true;
19730 }
19731 return false;
19732}
19733
19734bool isCMPSD(unsigned Opcode) {
19735 switch (Opcode) {
19736 case CMPSDrmi_Int:
19737 case CMPSDrri_Int:
19738 case CMPSL:
19739 return true;
19740 }
19741 return false;
19742}
19743
19744bool isMOVSS(unsigned Opcode) {
19745 switch (Opcode) {
19746 case MOVSSmr:
19747 case MOVSSrm:
19748 case MOVSSrr:
19749 case MOVSSrr_REV:
19750 return true;
19751 }
19752 return false;
19753}
19754
19755bool isVCVTUQQ2PD(unsigned Opcode) {
19756 switch (Opcode) {
19757 case VCVTUQQ2PDZ128rm:
19758 case VCVTUQQ2PDZ128rmb:
19759 case VCVTUQQ2PDZ128rmbk:
19760 case VCVTUQQ2PDZ128rmbkz:
19761 case VCVTUQQ2PDZ128rmk:
19762 case VCVTUQQ2PDZ128rmkz:
19763 case VCVTUQQ2PDZ128rr:
19764 case VCVTUQQ2PDZ128rrk:
19765 case VCVTUQQ2PDZ128rrkz:
19766 case VCVTUQQ2PDZ256rm:
19767 case VCVTUQQ2PDZ256rmb:
19768 case VCVTUQQ2PDZ256rmbk:
19769 case VCVTUQQ2PDZ256rmbkz:
19770 case VCVTUQQ2PDZ256rmk:
19771 case VCVTUQQ2PDZ256rmkz:
19772 case VCVTUQQ2PDZ256rr:
19773 case VCVTUQQ2PDZ256rrk:
19774 case VCVTUQQ2PDZ256rrkz:
19775 case VCVTUQQ2PDZrm:
19776 case VCVTUQQ2PDZrmb:
19777 case VCVTUQQ2PDZrmbk:
19778 case VCVTUQQ2PDZrmbkz:
19779 case VCVTUQQ2PDZrmk:
19780 case VCVTUQQ2PDZrmkz:
19781 case VCVTUQQ2PDZrr:
19782 case VCVTUQQ2PDZrrb:
19783 case VCVTUQQ2PDZrrbk:
19784 case VCVTUQQ2PDZrrbkz:
19785 case VCVTUQQ2PDZrrk:
19786 case VCVTUQQ2PDZrrkz:
19787 return true;
19788 }
19789 return false;
19790}
19791
19792bool isVEXTRACTI32X4(unsigned Opcode) {
19793 switch (Opcode) {
19794 case VEXTRACTI32X4Z256mri:
19795 case VEXTRACTI32X4Z256mrik:
19796 case VEXTRACTI32X4Z256rri:
19797 case VEXTRACTI32X4Z256rrik:
19798 case VEXTRACTI32X4Z256rrikz:
19799 case VEXTRACTI32X4Zmri:
19800 case VEXTRACTI32X4Zmrik:
19801 case VEXTRACTI32X4Zrri:
19802 case VEXTRACTI32X4Zrrik:
19803 case VEXTRACTI32X4Zrrikz:
19804 return true;
19805 }
19806 return false;
19807}
19808
19809bool isFLDCW(unsigned Opcode) {
19810 return Opcode == FLDCW16m;
19811}
19812
19813bool isINSW(unsigned Opcode) {
19814 return Opcode == INSW;
19815}
19816
19817bool isRDPID(unsigned Opcode) {
19818 switch (Opcode) {
19819 case RDPID32:
19820 case RDPID64:
19821 return true;
19822 }
19823 return false;
19824}
19825
19826bool isVUCOMXSS(unsigned Opcode) {
19827 switch (Opcode) {
19828 case VUCOMXSSZrm_Int:
19829 case VUCOMXSSZrr_Int:
19830 case VUCOMXSSZrrb_Int:
19831 return true;
19832 }
19833 return false;
19834}
19835
19836bool isKANDQ(unsigned Opcode) {
19837 return Opcode == KANDQkk;
19838}
19839
19840bool isV4FMADDPS(unsigned Opcode) {
19841 switch (Opcode) {
19842 case V4FMADDPSrm:
19843 case V4FMADDPSrmk:
19844 case V4FMADDPSrmkz:
19845 return true;
19846 }
19847 return false;
19848}
19849
19850bool isPMOVZXWQ(unsigned Opcode) {
19851 switch (Opcode) {
19852 case PMOVZXWQrm:
19853 case PMOVZXWQrr:
19854 return true;
19855 }
19856 return false;
19857}
19858
19859bool isVFPCLASSSD(unsigned Opcode) {
19860 switch (Opcode) {
19861 case VFPCLASSSDZmi:
19862 case VFPCLASSSDZmik:
19863 case VFPCLASSSDZri:
19864 case VFPCLASSSDZrik:
19865 return true;
19866 }
19867 return false;
19868}
19869
19870bool isBLENDPS(unsigned Opcode) {
19871 switch (Opcode) {
19872 case BLENDPSrmi:
19873 case BLENDPSrri:
19874 return true;
19875 }
19876 return false;
19877}
19878
19879bool isVPACKSSDW(unsigned Opcode) {
19880 switch (Opcode) {
19881 case VPACKSSDWYrm:
19882 case VPACKSSDWYrr:
19883 case VPACKSSDWZ128rm:
19884 case VPACKSSDWZ128rmb:
19885 case VPACKSSDWZ128rmbk:
19886 case VPACKSSDWZ128rmbkz:
19887 case VPACKSSDWZ128rmk:
19888 case VPACKSSDWZ128rmkz:
19889 case VPACKSSDWZ128rr:
19890 case VPACKSSDWZ128rrk:
19891 case VPACKSSDWZ128rrkz:
19892 case VPACKSSDWZ256rm:
19893 case VPACKSSDWZ256rmb:
19894 case VPACKSSDWZ256rmbk:
19895 case VPACKSSDWZ256rmbkz:
19896 case VPACKSSDWZ256rmk:
19897 case VPACKSSDWZ256rmkz:
19898 case VPACKSSDWZ256rr:
19899 case VPACKSSDWZ256rrk:
19900 case VPACKSSDWZ256rrkz:
19901 case VPACKSSDWZrm:
19902 case VPACKSSDWZrmb:
19903 case VPACKSSDWZrmbk:
19904 case VPACKSSDWZrmbkz:
19905 case VPACKSSDWZrmk:
19906 case VPACKSSDWZrmkz:
19907 case VPACKSSDWZrr:
19908 case VPACKSSDWZrrk:
19909 case VPACKSSDWZrrkz:
19910 case VPACKSSDWrm:
19911 case VPACKSSDWrr:
19912 return true;
19913 }
19914 return false;
19915}
19916
19917bool isVPINSRW(unsigned Opcode) {
19918 switch (Opcode) {
19919 case VPINSRWZrmi:
19920 case VPINSRWZrri:
19921 case VPINSRWrmi:
19922 case VPINSRWrri:
19923 return true;
19924 }
19925 return false;
19926}
19927
19928bool isFXAM(unsigned Opcode) {
19929 return Opcode == XAM_F;
19930}
19931
19932bool isVMINMAXBF16(unsigned Opcode) {
19933 switch (Opcode) {
19934 case VMINMAXBF16Z128rmbi:
19935 case VMINMAXBF16Z128rmbik:
19936 case VMINMAXBF16Z128rmbikz:
19937 case VMINMAXBF16Z128rmi:
19938 case VMINMAXBF16Z128rmik:
19939 case VMINMAXBF16Z128rmikz:
19940 case VMINMAXBF16Z128rri:
19941 case VMINMAXBF16Z128rrik:
19942 case VMINMAXBF16Z128rrikz:
19943 case VMINMAXBF16Z256rmbi:
19944 case VMINMAXBF16Z256rmbik:
19945 case VMINMAXBF16Z256rmbikz:
19946 case VMINMAXBF16Z256rmi:
19947 case VMINMAXBF16Z256rmik:
19948 case VMINMAXBF16Z256rmikz:
19949 case VMINMAXBF16Z256rri:
19950 case VMINMAXBF16Z256rrik:
19951 case VMINMAXBF16Z256rrikz:
19952 case VMINMAXBF16Zrmbi:
19953 case VMINMAXBF16Zrmbik:
19954 case VMINMAXBF16Zrmbikz:
19955 case VMINMAXBF16Zrmi:
19956 case VMINMAXBF16Zrmik:
19957 case VMINMAXBF16Zrmikz:
19958 case VMINMAXBF16Zrri:
19959 case VMINMAXBF16Zrrik:
19960 case VMINMAXBF16Zrrikz:
19961 return true;
19962 }
19963 return false;
19964}
19965
19966bool isVSHUFF64X2(unsigned Opcode) {
19967 switch (Opcode) {
19968 case VSHUFF64X2Z256rmbi:
19969 case VSHUFF64X2Z256rmbik:
19970 case VSHUFF64X2Z256rmbikz:
19971 case VSHUFF64X2Z256rmi:
19972 case VSHUFF64X2Z256rmik:
19973 case VSHUFF64X2Z256rmikz:
19974 case VSHUFF64X2Z256rri:
19975 case VSHUFF64X2Z256rrik:
19976 case VSHUFF64X2Z256rrikz:
19977 case VSHUFF64X2Zrmbi:
19978 case VSHUFF64X2Zrmbik:
19979 case VSHUFF64X2Zrmbikz:
19980 case VSHUFF64X2Zrmi:
19981 case VSHUFF64X2Zrmik:
19982 case VSHUFF64X2Zrmikz:
19983 case VSHUFF64X2Zrri:
19984 case VSHUFF64X2Zrrik:
19985 case VSHUFF64X2Zrrikz:
19986 return true;
19987 }
19988 return false;
19989}
19990
19991bool isVPACKUSWB(unsigned Opcode) {
19992 switch (Opcode) {
19993 case VPACKUSWBYrm:
19994 case VPACKUSWBYrr:
19995 case VPACKUSWBZ128rm:
19996 case VPACKUSWBZ128rmk:
19997 case VPACKUSWBZ128rmkz:
19998 case VPACKUSWBZ128rr:
19999 case VPACKUSWBZ128rrk:
20000 case VPACKUSWBZ128rrkz:
20001 case VPACKUSWBZ256rm:
20002 case VPACKUSWBZ256rmk:
20003 case VPACKUSWBZ256rmkz:
20004 case VPACKUSWBZ256rr:
20005 case VPACKUSWBZ256rrk:
20006 case VPACKUSWBZ256rrkz:
20007 case VPACKUSWBZrm:
20008 case VPACKUSWBZrmk:
20009 case VPACKUSWBZrmkz:
20010 case VPACKUSWBZrr:
20011 case VPACKUSWBZrrk:
20012 case VPACKUSWBZrrkz:
20013 case VPACKUSWBrm:
20014 case VPACKUSWBrr:
20015 return true;
20016 }
20017 return false;
20018}
20019
20020bool isVRSQRT28SS(unsigned Opcode) {
20021 switch (Opcode) {
20022 case VRSQRT28SSZm:
20023 case VRSQRT28SSZmk:
20024 case VRSQRT28SSZmkz:
20025 case VRSQRT28SSZr:
20026 case VRSQRT28SSZrb:
20027 case VRSQRT28SSZrbk:
20028 case VRSQRT28SSZrbkz:
20029 case VRSQRT28SSZrk:
20030 case VRSQRT28SSZrkz:
20031 return true;
20032 }
20033 return false;
20034}
20035
20036bool isGETSEC(unsigned Opcode) {
20037 return Opcode == GETSEC;
20038}
20039
20040bool isVEXTRACTF64X4(unsigned Opcode) {
20041 switch (Opcode) {
20042 case VEXTRACTF64X4Zmri:
20043 case VEXTRACTF64X4Zmrik:
20044 case VEXTRACTF64X4Zrri:
20045 case VEXTRACTF64X4Zrrik:
20046 case VEXTRACTF64X4Zrrikz:
20047 return true;
20048 }
20049 return false;
20050}
20051
20052bool isVPHSUBBW(unsigned Opcode) {
20053 switch (Opcode) {
20054 case VPHSUBBWrm:
20055 case VPHSUBBWrr:
20056 return true;
20057 }
20058 return false;
20059}
20060
20061bool isBLSR(unsigned Opcode) {
20062 switch (Opcode) {
20063 case BLSR32rm:
20064 case BLSR32rm_EVEX:
20065 case BLSR32rm_NF:
20066 case BLSR32rr:
20067 case BLSR32rr_EVEX:
20068 case BLSR32rr_NF:
20069 case BLSR64rm:
20070 case BLSR64rm_EVEX:
20071 case BLSR64rm_NF:
20072 case BLSR64rr:
20073 case BLSR64rr_EVEX:
20074 case BLSR64rr_NF:
20075 return true;
20076 }
20077 return false;
20078}
20079
20080bool isFILD(unsigned Opcode) {
20081 switch (Opcode) {
20082 case ILD_F16m:
20083 case ILD_F32m:
20084 case ILD_F64m:
20085 return true;
20086 }
20087 return false;
20088}
20089
20090bool isRETFQ(unsigned Opcode) {
20091 switch (Opcode) {
20092 case LRET64:
20093 case LRETI64:
20094 return true;
20095 }
20096 return false;
20097}
20098
20099bool isVADDSS(unsigned Opcode) {
20100 switch (Opcode) {
20101 case VADDSSZrm_Int:
20102 case VADDSSZrmk_Int:
20103 case VADDSSZrmkz_Int:
20104 case VADDSSZrr_Int:
20105 case VADDSSZrrb_Int:
20106 case VADDSSZrrbk_Int:
20107 case VADDSSZrrbkz_Int:
20108 case VADDSSZrrk_Int:
20109 case VADDSSZrrkz_Int:
20110 case VADDSSrm_Int:
20111 case VADDSSrr_Int:
20112 return true;
20113 }
20114 return false;
20115}
20116
20117bool isCOMISS(unsigned Opcode) {
20118 switch (Opcode) {
20119 case COMISSrm:
20120 case COMISSrr:
20121 return true;
20122 }
20123 return false;
20124}
20125
20126bool isCLI(unsigned Opcode) {
20127 return Opcode == CLI;
20128}
20129
20130bool isVERW(unsigned Opcode) {
20131 switch (Opcode) {
20132 case VERWm:
20133 case VERWr:
20134 return true;
20135 }
20136 return false;
20137}
20138
20139bool isBTC(unsigned Opcode) {
20140 switch (Opcode) {
20141 case BTC16mi8:
20142 case BTC16mr:
20143 case BTC16ri8:
20144 case BTC16rr:
20145 case BTC32mi8:
20146 case BTC32mr:
20147 case BTC32ri8:
20148 case BTC32rr:
20149 case BTC64mi8:
20150 case BTC64mr:
20151 case BTC64ri8:
20152 case BTC64rr:
20153 return true;
20154 }
20155 return false;
20156}
20157
20158bool isVPHADDUBQ(unsigned Opcode) {
20159 switch (Opcode) {
20160 case VPHADDUBQrm:
20161 case VPHADDUBQrr:
20162 return true;
20163 }
20164 return false;
20165}
20166
20167bool isVPORQ(unsigned Opcode) {
20168 switch (Opcode) {
20169 case VPORQZ128rm:
20170 case VPORQZ128rmb:
20171 case VPORQZ128rmbk:
20172 case VPORQZ128rmbkz:
20173 case VPORQZ128rmk:
20174 case VPORQZ128rmkz:
20175 case VPORQZ128rr:
20176 case VPORQZ128rrk:
20177 case VPORQZ128rrkz:
20178 case VPORQZ256rm:
20179 case VPORQZ256rmb:
20180 case VPORQZ256rmbk:
20181 case VPORQZ256rmbkz:
20182 case VPORQZ256rmk:
20183 case VPORQZ256rmkz:
20184 case VPORQZ256rr:
20185 case VPORQZ256rrk:
20186 case VPORQZ256rrkz:
20187 case VPORQZrm:
20188 case VPORQZrmb:
20189 case VPORQZrmbk:
20190 case VPORQZrmbkz:
20191 case VPORQZrmk:
20192 case VPORQZrmkz:
20193 case VPORQZrr:
20194 case VPORQZrrk:
20195 case VPORQZrrkz:
20196 return true;
20197 }
20198 return false;
20199}
20200
20201bool isORPD(unsigned Opcode) {
20202 switch (Opcode) {
20203 case ORPDrm:
20204 case ORPDrr:
20205 return true;
20206 }
20207 return false;
20208}
20209
20210bool isVMOVSS(unsigned Opcode) {
20211 switch (Opcode) {
20212 case VMOVSSZmr:
20213 case VMOVSSZmrk:
20214 case VMOVSSZrm:
20215 case VMOVSSZrmk:
20216 case VMOVSSZrmkz:
20217 case VMOVSSZrr:
20218 case VMOVSSZrr_REV:
20219 case VMOVSSZrrk:
20220 case VMOVSSZrrk_REV:
20221 case VMOVSSZrrkz:
20222 case VMOVSSZrrkz_REV:
20223 case VMOVSSmr:
20224 case VMOVSSrm:
20225 case VMOVSSrr:
20226 case VMOVSSrr_REV:
20227 return true;
20228 }
20229 return false;
20230}
20231
20232bool isVPSUBD(unsigned Opcode) {
20233 switch (Opcode) {
20234 case VPSUBDYrm:
20235 case VPSUBDYrr:
20236 case VPSUBDZ128rm:
20237 case VPSUBDZ128rmb:
20238 case VPSUBDZ128rmbk:
20239 case VPSUBDZ128rmbkz:
20240 case VPSUBDZ128rmk:
20241 case VPSUBDZ128rmkz:
20242 case VPSUBDZ128rr:
20243 case VPSUBDZ128rrk:
20244 case VPSUBDZ128rrkz:
20245 case VPSUBDZ256rm:
20246 case VPSUBDZ256rmb:
20247 case VPSUBDZ256rmbk:
20248 case VPSUBDZ256rmbkz:
20249 case VPSUBDZ256rmk:
20250 case VPSUBDZ256rmkz:
20251 case VPSUBDZ256rr:
20252 case VPSUBDZ256rrk:
20253 case VPSUBDZ256rrkz:
20254 case VPSUBDZrm:
20255 case VPSUBDZrmb:
20256 case VPSUBDZrmbk:
20257 case VPSUBDZrmbkz:
20258 case VPSUBDZrmk:
20259 case VPSUBDZrmkz:
20260 case VPSUBDZrr:
20261 case VPSUBDZrrk:
20262 case VPSUBDZrrkz:
20263 case VPSUBDrm:
20264 case VPSUBDrr:
20265 return true;
20266 }
20267 return false;
20268}
20269
20270bool isVGATHERPF1QPD(unsigned Opcode) {
20271 return Opcode == VGATHERPF1QPDm;
20272}
20273
20274bool isENCODEKEY256(unsigned Opcode) {
20275 return Opcode == ENCODEKEY256;
20276}
20277
20278bool isGF2P8AFFINEINVQB(unsigned Opcode) {
20279 switch (Opcode) {
20280 case GF2P8AFFINEINVQBrmi:
20281 case GF2P8AFFINEINVQBrri:
20282 return true;
20283 }
20284 return false;
20285}
20286
20287bool isXRSTOR64(unsigned Opcode) {
20288 return Opcode == XRSTOR64;
20289}
20290
20291bool isKANDW(unsigned Opcode) {
20292 return Opcode == KANDWkk;
20293}
20294
20295bool isLODSQ(unsigned Opcode) {
20296 return Opcode == LODSQ;
20297}
20298
20299bool isVMOVRSW(unsigned Opcode) {
20300 switch (Opcode) {
20301 case VMOVRSWZ128m:
20302 case VMOVRSWZ128mk:
20303 case VMOVRSWZ128mkz:
20304 case VMOVRSWZ256m:
20305 case VMOVRSWZ256mk:
20306 case VMOVRSWZ256mkz:
20307 case VMOVRSWZm:
20308 case VMOVRSWZmk:
20309 case VMOVRSWZmkz:
20310 return true;
20311 }
20312 return false;
20313}
20314
20315bool isVSUBSH(unsigned Opcode) {
20316 switch (Opcode) {
20317 case VSUBSHZrm_Int:
20318 case VSUBSHZrmk_Int:
20319 case VSUBSHZrmkz_Int:
20320 case VSUBSHZrr_Int:
20321 case VSUBSHZrrb_Int:
20322 case VSUBSHZrrbk_Int:
20323 case VSUBSHZrrbkz_Int:
20324 case VSUBSHZrrk_Int:
20325 case VSUBSHZrrkz_Int:
20326 return true;
20327 }
20328 return false;
20329}
20330
20331bool isLSS(unsigned Opcode) {
20332 switch (Opcode) {
20333 case LSS16rm:
20334 case LSS32rm:
20335 case LSS64rm:
20336 return true;
20337 }
20338 return false;
20339}
20340
20341bool isPMOVSXBQ(unsigned Opcode) {
20342 switch (Opcode) {
20343 case PMOVSXBQrm:
20344 case PMOVSXBQrr:
20345 return true;
20346 }
20347 return false;
20348}
20349
20350bool isVCVTTSD2SIS(unsigned Opcode) {
20351 switch (Opcode) {
20352 case VCVTTSD2SI64Srm_Int:
20353 case VCVTTSD2SI64Srr_Int:
20354 case VCVTTSD2SI64Srrb_Int:
20355 case VCVTTSD2SISrm_Int:
20356 case VCVTTSD2SISrr_Int:
20357 case VCVTTSD2SISrrb_Int:
20358 return true;
20359 }
20360 return false;
20361}
20362
20363bool isVCMPSH(unsigned Opcode) {
20364 switch (Opcode) {
20365 case VCMPSHZrmi_Int:
20366 case VCMPSHZrmik_Int:
20367 case VCMPSHZrri_Int:
20368 case VCMPSHZrrib_Int:
20369 case VCMPSHZrribk_Int:
20370 case VCMPSHZrrik_Int:
20371 return true;
20372 }
20373 return false;
20374}
20375
20376bool isVFMADD132PS(unsigned Opcode) {
20377 switch (Opcode) {
20378 case VFMADD132PSYm:
20379 case VFMADD132PSYr:
20380 case VFMADD132PSZ128m:
20381 case VFMADD132PSZ128mb:
20382 case VFMADD132PSZ128mbk:
20383 case VFMADD132PSZ128mbkz:
20384 case VFMADD132PSZ128mk:
20385 case VFMADD132PSZ128mkz:
20386 case VFMADD132PSZ128r:
20387 case VFMADD132PSZ128rk:
20388 case VFMADD132PSZ128rkz:
20389 case VFMADD132PSZ256m:
20390 case VFMADD132PSZ256mb:
20391 case VFMADD132PSZ256mbk:
20392 case VFMADD132PSZ256mbkz:
20393 case VFMADD132PSZ256mk:
20394 case VFMADD132PSZ256mkz:
20395 case VFMADD132PSZ256r:
20396 case VFMADD132PSZ256rk:
20397 case VFMADD132PSZ256rkz:
20398 case VFMADD132PSZm:
20399 case VFMADD132PSZmb:
20400 case VFMADD132PSZmbk:
20401 case VFMADD132PSZmbkz:
20402 case VFMADD132PSZmk:
20403 case VFMADD132PSZmkz:
20404 case VFMADD132PSZr:
20405 case VFMADD132PSZrb:
20406 case VFMADD132PSZrbk:
20407 case VFMADD132PSZrbkz:
20408 case VFMADD132PSZrk:
20409 case VFMADD132PSZrkz:
20410 case VFMADD132PSm:
20411 case VFMADD132PSr:
20412 return true;
20413 }
20414 return false;
20415}
20416
20417bool isVPACKSSWB(unsigned Opcode) {
20418 switch (Opcode) {
20419 case VPACKSSWBYrm:
20420 case VPACKSSWBYrr:
20421 case VPACKSSWBZ128rm:
20422 case VPACKSSWBZ128rmk:
20423 case VPACKSSWBZ128rmkz:
20424 case VPACKSSWBZ128rr:
20425 case VPACKSSWBZ128rrk:
20426 case VPACKSSWBZ128rrkz:
20427 case VPACKSSWBZ256rm:
20428 case VPACKSSWBZ256rmk:
20429 case VPACKSSWBZ256rmkz:
20430 case VPACKSSWBZ256rr:
20431 case VPACKSSWBZ256rrk:
20432 case VPACKSSWBZ256rrkz:
20433 case VPACKSSWBZrm:
20434 case VPACKSSWBZrmk:
20435 case VPACKSSWBZrmkz:
20436 case VPACKSSWBZrr:
20437 case VPACKSSWBZrrk:
20438 case VPACKSSWBZrrkz:
20439 case VPACKSSWBrm:
20440 case VPACKSSWBrr:
20441 return true;
20442 }
20443 return false;
20444}
20445
20446bool isPCMPGTQ(unsigned Opcode) {
20447 switch (Opcode) {
20448 case PCMPGTQrm:
20449 case PCMPGTQrr:
20450 return true;
20451 }
20452 return false;
20453}
20454
20455bool isVFMADD132SH(unsigned Opcode) {
20456 switch (Opcode) {
20457 case VFMADD132SHZm_Int:
20458 case VFMADD132SHZmk_Int:
20459 case VFMADD132SHZmkz_Int:
20460 case VFMADD132SHZr_Int:
20461 case VFMADD132SHZrb_Int:
20462 case VFMADD132SHZrbk_Int:
20463 case VFMADD132SHZrbkz_Int:
20464 case VFMADD132SHZrk_Int:
20465 case VFMADD132SHZrkz_Int:
20466 return true;
20467 }
20468 return false;
20469}
20470
20471bool isVCVTUQQ2PH(unsigned Opcode) {
20472 switch (Opcode) {
20473 case VCVTUQQ2PHZ128rm:
20474 case VCVTUQQ2PHZ128rmb:
20475 case VCVTUQQ2PHZ128rmbk:
20476 case VCVTUQQ2PHZ128rmbkz:
20477 case VCVTUQQ2PHZ128rmk:
20478 case VCVTUQQ2PHZ128rmkz:
20479 case VCVTUQQ2PHZ128rr:
20480 case VCVTUQQ2PHZ128rrk:
20481 case VCVTUQQ2PHZ128rrkz:
20482 case VCVTUQQ2PHZ256rm:
20483 case VCVTUQQ2PHZ256rmb:
20484 case VCVTUQQ2PHZ256rmbk:
20485 case VCVTUQQ2PHZ256rmbkz:
20486 case VCVTUQQ2PHZ256rmk:
20487 case VCVTUQQ2PHZ256rmkz:
20488 case VCVTUQQ2PHZ256rr:
20489 case VCVTUQQ2PHZ256rrk:
20490 case VCVTUQQ2PHZ256rrkz:
20491 case VCVTUQQ2PHZrm:
20492 case VCVTUQQ2PHZrmb:
20493 case VCVTUQQ2PHZrmbk:
20494 case VCVTUQQ2PHZrmbkz:
20495 case VCVTUQQ2PHZrmk:
20496 case VCVTUQQ2PHZrmkz:
20497 case VCVTUQQ2PHZrr:
20498 case VCVTUQQ2PHZrrb:
20499 case VCVTUQQ2PHZrrbk:
20500 case VCVTUQQ2PHZrrbkz:
20501 case VCVTUQQ2PHZrrk:
20502 case VCVTUQQ2PHZrrkz:
20503 return true;
20504 }
20505 return false;
20506}
20507
20508bool isVCVTQQ2PS(unsigned Opcode) {
20509 switch (Opcode) {
20510 case VCVTQQ2PSZ128rm:
20511 case VCVTQQ2PSZ128rmb:
20512 case VCVTQQ2PSZ128rmbk:
20513 case VCVTQQ2PSZ128rmbkz:
20514 case VCVTQQ2PSZ128rmk:
20515 case VCVTQQ2PSZ128rmkz:
20516 case VCVTQQ2PSZ128rr:
20517 case VCVTQQ2PSZ128rrk:
20518 case VCVTQQ2PSZ128rrkz:
20519 case VCVTQQ2PSZ256rm:
20520 case VCVTQQ2PSZ256rmb:
20521 case VCVTQQ2PSZ256rmbk:
20522 case VCVTQQ2PSZ256rmbkz:
20523 case VCVTQQ2PSZ256rmk:
20524 case VCVTQQ2PSZ256rmkz:
20525 case VCVTQQ2PSZ256rr:
20526 case VCVTQQ2PSZ256rrk:
20527 case VCVTQQ2PSZ256rrkz:
20528 case VCVTQQ2PSZrm:
20529 case VCVTQQ2PSZrmb:
20530 case VCVTQQ2PSZrmbk:
20531 case VCVTQQ2PSZrmbkz:
20532 case VCVTQQ2PSZrmk:
20533 case VCVTQQ2PSZrmkz:
20534 case VCVTQQ2PSZrr:
20535 case VCVTQQ2PSZrrb:
20536 case VCVTQQ2PSZrrbk:
20537 case VCVTQQ2PSZrrbkz:
20538 case VCVTQQ2PSZrrk:
20539 case VCVTQQ2PSZrrkz:
20540 return true;
20541 }
20542 return false;
20543}
20544
20545bool isVCVTTSS2USI(unsigned Opcode) {
20546 switch (Opcode) {
20547 case VCVTTSS2USI64Zrm_Int:
20548 case VCVTTSS2USI64Zrr_Int:
20549 case VCVTTSS2USI64Zrrb_Int:
20550 case VCVTTSS2USIZrm_Int:
20551 case VCVTTSS2USIZrr_Int:
20552 case VCVTTSS2USIZrrb_Int:
20553 return true;
20554 }
20555 return false;
20556}
20557
20558bool isVPMOVM2Q(unsigned Opcode) {
20559 switch (Opcode) {
20560 case VPMOVM2QZ128rk:
20561 case VPMOVM2QZ256rk:
20562 case VPMOVM2QZrk:
20563 return true;
20564 }
20565 return false;
20566}
20567
20568bool isVMOVD(unsigned Opcode) {
20569 switch (Opcode) {
20570 case VMOVDI2PDIZrm:
20571 case VMOVDI2PDIZrr:
20572 case VMOVDI2PDIrm:
20573 case VMOVDI2PDIrr:
20574 case VMOVPDI2DIZmr:
20575 case VMOVPDI2DIZrr:
20576 case VMOVPDI2DImr:
20577 case VMOVPDI2DIrr:
20578 case VMOVZPDILo2PDIZmr:
20579 case VMOVZPDILo2PDIZrm:
20580 case VMOVZPDILo2PDIZrr:
20581 case VMOVZPDILo2PDIZrr2:
20582 return true;
20583 }
20584 return false;
20585}
20586
20587bool isVCVTTPS2QQS(unsigned Opcode) {
20588 switch (Opcode) {
20589 case VCVTTPS2QQSZ128rm:
20590 case VCVTTPS2QQSZ128rmb:
20591 case VCVTTPS2QQSZ128rmbk:
20592 case VCVTTPS2QQSZ128rmbkz:
20593 case VCVTTPS2QQSZ128rmk:
20594 case VCVTTPS2QQSZ128rmkz:
20595 case VCVTTPS2QQSZ128rr:
20596 case VCVTTPS2QQSZ128rrk:
20597 case VCVTTPS2QQSZ128rrkz:
20598 case VCVTTPS2QQSZ256rm:
20599 case VCVTTPS2QQSZ256rmb:
20600 case VCVTTPS2QQSZ256rmbk:
20601 case VCVTTPS2QQSZ256rmbkz:
20602 case VCVTTPS2QQSZ256rmk:
20603 case VCVTTPS2QQSZ256rmkz:
20604 case VCVTTPS2QQSZ256rr:
20605 case VCVTTPS2QQSZ256rrb:
20606 case VCVTTPS2QQSZ256rrbk:
20607 case VCVTTPS2QQSZ256rrbkz:
20608 case VCVTTPS2QQSZ256rrk:
20609 case VCVTTPS2QQSZ256rrkz:
20610 case VCVTTPS2QQSZrm:
20611 case VCVTTPS2QQSZrmb:
20612 case VCVTTPS2QQSZrmbk:
20613 case VCVTTPS2QQSZrmbkz:
20614 case VCVTTPS2QQSZrmk:
20615 case VCVTTPS2QQSZrmkz:
20616 case VCVTTPS2QQSZrr:
20617 case VCVTTPS2QQSZrrb:
20618 case VCVTTPS2QQSZrrbk:
20619 case VCVTTPS2QQSZrrbkz:
20620 case VCVTTPS2QQSZrrk:
20621 case VCVTTPS2QQSZrrkz:
20622 return true;
20623 }
20624 return false;
20625}
20626
20627bool isVSQRTBF16(unsigned Opcode) {
20628 switch (Opcode) {
20629 case VSQRTBF16Z128m:
20630 case VSQRTBF16Z128mb:
20631 case VSQRTBF16Z128mbk:
20632 case VSQRTBF16Z128mbkz:
20633 case VSQRTBF16Z128mk:
20634 case VSQRTBF16Z128mkz:
20635 case VSQRTBF16Z128r:
20636 case VSQRTBF16Z128rk:
20637 case VSQRTBF16Z128rkz:
20638 case VSQRTBF16Z256m:
20639 case VSQRTBF16Z256mb:
20640 case VSQRTBF16Z256mbk:
20641 case VSQRTBF16Z256mbkz:
20642 case VSQRTBF16Z256mk:
20643 case VSQRTBF16Z256mkz:
20644 case VSQRTBF16Z256r:
20645 case VSQRTBF16Z256rk:
20646 case VSQRTBF16Z256rkz:
20647 case VSQRTBF16Zm:
20648 case VSQRTBF16Zmb:
20649 case VSQRTBF16Zmbk:
20650 case VSQRTBF16Zmbkz:
20651 case VSQRTBF16Zmk:
20652 case VSQRTBF16Zmkz:
20653 case VSQRTBF16Zr:
20654 case VSQRTBF16Zrk:
20655 case VSQRTBF16Zrkz:
20656 return true;
20657 }
20658 return false;
20659}
20660
20661bool isVFPCLASSPH(unsigned Opcode) {
20662 switch (Opcode) {
20663 case VFPCLASSPHZ128mbi:
20664 case VFPCLASSPHZ128mbik:
20665 case VFPCLASSPHZ128mi:
20666 case VFPCLASSPHZ128mik:
20667 case VFPCLASSPHZ128ri:
20668 case VFPCLASSPHZ128rik:
20669 case VFPCLASSPHZ256mbi:
20670 case VFPCLASSPHZ256mbik:
20671 case VFPCLASSPHZ256mi:
20672 case VFPCLASSPHZ256mik:
20673 case VFPCLASSPHZ256ri:
20674 case VFPCLASSPHZ256rik:
20675 case VFPCLASSPHZmbi:
20676 case VFPCLASSPHZmbik:
20677 case VFPCLASSPHZmi:
20678 case VFPCLASSPHZmik:
20679 case VFPCLASSPHZri:
20680 case VFPCLASSPHZrik:
20681 return true;
20682 }
20683 return false;
20684}
20685
20686bool isVCVTSS2SH(unsigned Opcode) {
20687 switch (Opcode) {
20688 case VCVTSS2SHZrm_Int:
20689 case VCVTSS2SHZrmk_Int:
20690 case VCVTSS2SHZrmkz_Int:
20691 case VCVTSS2SHZrr_Int:
20692 case VCVTSS2SHZrrb_Int:
20693 case VCVTSS2SHZrrbk_Int:
20694 case VCVTSS2SHZrrbkz_Int:
20695 case VCVTSS2SHZrrk_Int:
20696 case VCVTSS2SHZrrkz_Int:
20697 return true;
20698 }
20699 return false;
20700}
20701
20702bool isSCASB(unsigned Opcode) {
20703 return Opcode == SCASB;
20704}
20705
20706bool isPSRLD(unsigned Opcode) {
20707 switch (Opcode) {
20708 case MMX_PSRLDri:
20709 case MMX_PSRLDrm:
20710 case MMX_PSRLDrr:
20711 case PSRLDri:
20712 case PSRLDrm:
20713 case PSRLDrr:
20714 return true;
20715 }
20716 return false;
20717}
20718
20719bool isVADDPH(unsigned Opcode) {
20720 switch (Opcode) {
20721 case VADDPHZ128rm:
20722 case VADDPHZ128rmb:
20723 case VADDPHZ128rmbk:
20724 case VADDPHZ128rmbkz:
20725 case VADDPHZ128rmk:
20726 case VADDPHZ128rmkz:
20727 case VADDPHZ128rr:
20728 case VADDPHZ128rrk:
20729 case VADDPHZ128rrkz:
20730 case VADDPHZ256rm:
20731 case VADDPHZ256rmb:
20732 case VADDPHZ256rmbk:
20733 case VADDPHZ256rmbkz:
20734 case VADDPHZ256rmk:
20735 case VADDPHZ256rmkz:
20736 case VADDPHZ256rr:
20737 case VADDPHZ256rrk:
20738 case VADDPHZ256rrkz:
20739 case VADDPHZrm:
20740 case VADDPHZrmb:
20741 case VADDPHZrmbk:
20742 case VADDPHZrmbkz:
20743 case VADDPHZrmk:
20744 case VADDPHZrmkz:
20745 case VADDPHZrr:
20746 case VADDPHZrrb:
20747 case VADDPHZrrbk:
20748 case VADDPHZrrbkz:
20749 case VADDPHZrrk:
20750 case VADDPHZrrkz:
20751 return true;
20752 }
20753 return false;
20754}
20755
20756bool isFSUB(unsigned Opcode) {
20757 switch (Opcode) {
20758 case SUB_F32m:
20759 case SUB_F64m:
20760 case SUB_FST0r:
20761 case SUB_FrST0:
20762 return true;
20763 }
20764 return false;
20765}
20766
20767bool isVCVTTPH2IBS(unsigned Opcode) {
20768 switch (Opcode) {
20769 case VCVTTPH2IBSZ128rm:
20770 case VCVTTPH2IBSZ128rmb:
20771 case VCVTTPH2IBSZ128rmbk:
20772 case VCVTTPH2IBSZ128rmbkz:
20773 case VCVTTPH2IBSZ128rmk:
20774 case VCVTTPH2IBSZ128rmkz:
20775 case VCVTTPH2IBSZ128rr:
20776 case VCVTTPH2IBSZ128rrk:
20777 case VCVTTPH2IBSZ128rrkz:
20778 case VCVTTPH2IBSZ256rm:
20779 case VCVTTPH2IBSZ256rmb:
20780 case VCVTTPH2IBSZ256rmbk:
20781 case VCVTTPH2IBSZ256rmbkz:
20782 case VCVTTPH2IBSZ256rmk:
20783 case VCVTTPH2IBSZ256rmkz:
20784 case VCVTTPH2IBSZ256rr:
20785 case VCVTTPH2IBSZ256rrk:
20786 case VCVTTPH2IBSZ256rrkz:
20787 case VCVTTPH2IBSZrm:
20788 case VCVTTPH2IBSZrmb:
20789 case VCVTTPH2IBSZrmbk:
20790 case VCVTTPH2IBSZrmbkz:
20791 case VCVTTPH2IBSZrmk:
20792 case VCVTTPH2IBSZrmkz:
20793 case VCVTTPH2IBSZrr:
20794 case VCVTTPH2IBSZrrb:
20795 case VCVTTPH2IBSZrrbk:
20796 case VCVTTPH2IBSZrrbkz:
20797 case VCVTTPH2IBSZrrk:
20798 case VCVTTPH2IBSZrrkz:
20799 return true;
20800 }
20801 return false;
20802}
20803
20804bool isVEXTRACTI64X2(unsigned Opcode) {
20805 switch (Opcode) {
20806 case VEXTRACTI64X2Z256mri:
20807 case VEXTRACTI64X2Z256mrik:
20808 case VEXTRACTI64X2Z256rri:
20809 case VEXTRACTI64X2Z256rrik:
20810 case VEXTRACTI64X2Z256rrikz:
20811 case VEXTRACTI64X2Zmri:
20812 case VEXTRACTI64X2Zmrik:
20813 case VEXTRACTI64X2Zrri:
20814 case VEXTRACTI64X2Zrrik:
20815 case VEXTRACTI64X2Zrrikz:
20816 return true;
20817 }
20818 return false;
20819}
20820
20821bool isPMINUW(unsigned Opcode) {
20822 switch (Opcode) {
20823 case PMINUWrm:
20824 case PMINUWrr:
20825 return true;
20826 }
20827 return false;
20828}
20829
20830bool isPSUBSB(unsigned Opcode) {
20831 switch (Opcode) {
20832 case MMX_PSUBSBrm:
20833 case MMX_PSUBSBrr:
20834 case PSUBSBrm:
20835 case PSUBSBrr:
20836 return true;
20837 }
20838 return false;
20839}
20840
20841bool isVCVT2PS2PHX(unsigned Opcode) {
20842 switch (Opcode) {
20843 case VCVT2PS2PHXZ128rm:
20844 case VCVT2PS2PHXZ128rmb:
20845 case VCVT2PS2PHXZ128rmbk:
20846 case VCVT2PS2PHXZ128rmbkz:
20847 case VCVT2PS2PHXZ128rmk:
20848 case VCVT2PS2PHXZ128rmkz:
20849 case VCVT2PS2PHXZ128rr:
20850 case VCVT2PS2PHXZ128rrk:
20851 case VCVT2PS2PHXZ128rrkz:
20852 case VCVT2PS2PHXZ256rm:
20853 case VCVT2PS2PHXZ256rmb:
20854 case VCVT2PS2PHXZ256rmbk:
20855 case VCVT2PS2PHXZ256rmbkz:
20856 case VCVT2PS2PHXZ256rmk:
20857 case VCVT2PS2PHXZ256rmkz:
20858 case VCVT2PS2PHXZ256rr:
20859 case VCVT2PS2PHXZ256rrk:
20860 case VCVT2PS2PHXZ256rrkz:
20861 case VCVT2PS2PHXZrm:
20862 case VCVT2PS2PHXZrmb:
20863 case VCVT2PS2PHXZrmbk:
20864 case VCVT2PS2PHXZrmbkz:
20865 case VCVT2PS2PHXZrmk:
20866 case VCVT2PS2PHXZrmkz:
20867 case VCVT2PS2PHXZrr:
20868 case VCVT2PS2PHXZrrb:
20869 case VCVT2PS2PHXZrrbk:
20870 case VCVT2PS2PHXZrrbkz:
20871 case VCVT2PS2PHXZrrk:
20872 case VCVT2PS2PHXZrrkz:
20873 return true;
20874 }
20875 return false;
20876}
20877
20878bool isVPCMPEQD(unsigned Opcode) {
20879 switch (Opcode) {
20880 case VPCMPEQDYrm:
20881 case VPCMPEQDYrr:
20882 case VPCMPEQDZ128rm:
20883 case VPCMPEQDZ128rmb:
20884 case VPCMPEQDZ128rmbk:
20885 case VPCMPEQDZ128rmk:
20886 case VPCMPEQDZ128rr:
20887 case VPCMPEQDZ128rrk:
20888 case VPCMPEQDZ256rm:
20889 case VPCMPEQDZ256rmb:
20890 case VPCMPEQDZ256rmbk:
20891 case VPCMPEQDZ256rmk:
20892 case VPCMPEQDZ256rr:
20893 case VPCMPEQDZ256rrk:
20894 case VPCMPEQDZrm:
20895 case VPCMPEQDZrmb:
20896 case VPCMPEQDZrmbk:
20897 case VPCMPEQDZrmk:
20898 case VPCMPEQDZrr:
20899 case VPCMPEQDZrrk:
20900 case VPCMPEQDrm:
20901 case VPCMPEQDrr:
20902 return true;
20903 }
20904 return false;
20905}
20906
20907bool isVPSCATTERQD(unsigned Opcode) {
20908 switch (Opcode) {
20909 case VPSCATTERQDZ128mr:
20910 case VPSCATTERQDZ256mr:
20911 case VPSCATTERQDZmr:
20912 return true;
20913 }
20914 return false;
20915}
20916
20917bool isVPSHLDD(unsigned Opcode) {
20918 switch (Opcode) {
20919 case VPSHLDDZ128rmbi:
20920 case VPSHLDDZ128rmbik:
20921 case VPSHLDDZ128rmbikz:
20922 case VPSHLDDZ128rmi:
20923 case VPSHLDDZ128rmik:
20924 case VPSHLDDZ128rmikz:
20925 case VPSHLDDZ128rri:
20926 case VPSHLDDZ128rrik:
20927 case VPSHLDDZ128rrikz:
20928 case VPSHLDDZ256rmbi:
20929 case VPSHLDDZ256rmbik:
20930 case VPSHLDDZ256rmbikz:
20931 case VPSHLDDZ256rmi:
20932 case VPSHLDDZ256rmik:
20933 case VPSHLDDZ256rmikz:
20934 case VPSHLDDZ256rri:
20935 case VPSHLDDZ256rrik:
20936 case VPSHLDDZ256rrikz:
20937 case VPSHLDDZrmbi:
20938 case VPSHLDDZrmbik:
20939 case VPSHLDDZrmbikz:
20940 case VPSHLDDZrmi:
20941 case VPSHLDDZrmik:
20942 case VPSHLDDZrmikz:
20943 case VPSHLDDZrri:
20944 case VPSHLDDZrrik:
20945 case VPSHLDDZrrikz:
20946 return true;
20947 }
20948 return false;
20949}
20950
20951bool isKXNORB(unsigned Opcode) {
20952 return Opcode == KXNORBkk;
20953}
20954
20955bool isLDDQU(unsigned Opcode) {
20956 return Opcode == LDDQUrm;
20957}
20958
20959bool isMASKMOVQ(unsigned Opcode) {
20960 switch (Opcode) {
20961 case MMX_MASKMOVQ:
20962 case MMX_MASKMOVQ64:
20963 return true;
20964 }
20965 return false;
20966}
20967
20968bool isPABSW(unsigned Opcode) {
20969 switch (Opcode) {
20970 case MMX_PABSWrm:
20971 case MMX_PABSWrr:
20972 case PABSWrm:
20973 case PABSWrr:
20974 return true;
20975 }
20976 return false;
20977}
20978
20979bool isVPROLD(unsigned Opcode) {
20980 switch (Opcode) {
20981 case VPROLDZ128mbi:
20982 case VPROLDZ128mbik:
20983 case VPROLDZ128mbikz:
20984 case VPROLDZ128mi:
20985 case VPROLDZ128mik:
20986 case VPROLDZ128mikz:
20987 case VPROLDZ128ri:
20988 case VPROLDZ128rik:
20989 case VPROLDZ128rikz:
20990 case VPROLDZ256mbi:
20991 case VPROLDZ256mbik:
20992 case VPROLDZ256mbikz:
20993 case VPROLDZ256mi:
20994 case VPROLDZ256mik:
20995 case VPROLDZ256mikz:
20996 case VPROLDZ256ri:
20997 case VPROLDZ256rik:
20998 case VPROLDZ256rikz:
20999 case VPROLDZmbi:
21000 case VPROLDZmbik:
21001 case VPROLDZmbikz:
21002 case VPROLDZmi:
21003 case VPROLDZmik:
21004 case VPROLDZmikz:
21005 case VPROLDZri:
21006 case VPROLDZrik:
21007 case VPROLDZrikz:
21008 return true;
21009 }
21010 return false;
21011}
21012
21013bool isVPCOMQ(unsigned Opcode) {
21014 switch (Opcode) {
21015 case VPCOMQmi:
21016 case VPCOMQri:
21017 return true;
21018 }
21019 return false;
21020}
21021
21022bool isVSCATTERDPD(unsigned Opcode) {
21023 switch (Opcode) {
21024 case VSCATTERDPDZ128mr:
21025 case VSCATTERDPDZ256mr:
21026 case VSCATTERDPDZmr:
21027 return true;
21028 }
21029 return false;
21030}
21031
21032bool isFXRSTOR(unsigned Opcode) {
21033 return Opcode == FXRSTOR;
21034}
21035
21036bool isVPCMPUW(unsigned Opcode) {
21037 switch (Opcode) {
21038 case VPCMPUWZ128rmi:
21039 case VPCMPUWZ128rmik:
21040 case VPCMPUWZ128rri:
21041 case VPCMPUWZ128rrik:
21042 case VPCMPUWZ256rmi:
21043 case VPCMPUWZ256rmik:
21044 case VPCMPUWZ256rri:
21045 case VPCMPUWZ256rrik:
21046 case VPCMPUWZrmi:
21047 case VPCMPUWZrmik:
21048 case VPCMPUWZrri:
21049 case VPCMPUWZrrik:
21050 return true;
21051 }
21052 return false;
21053}
21054
21055bool isWBINVD(unsigned Opcode) {
21056 return Opcode == WBINVD;
21057}
21058
21059bool isVCVTTPD2UDQ(unsigned Opcode) {
21060 switch (Opcode) {
21061 case VCVTTPD2UDQZ128rm:
21062 case VCVTTPD2UDQZ128rmb:
21063 case VCVTTPD2UDQZ128rmbk:
21064 case VCVTTPD2UDQZ128rmbkz:
21065 case VCVTTPD2UDQZ128rmk:
21066 case VCVTTPD2UDQZ128rmkz:
21067 case VCVTTPD2UDQZ128rr:
21068 case VCVTTPD2UDQZ128rrk:
21069 case VCVTTPD2UDQZ128rrkz:
21070 case VCVTTPD2UDQZ256rm:
21071 case VCVTTPD2UDQZ256rmb:
21072 case VCVTTPD2UDQZ256rmbk:
21073 case VCVTTPD2UDQZ256rmbkz:
21074 case VCVTTPD2UDQZ256rmk:
21075 case VCVTTPD2UDQZ256rmkz:
21076 case VCVTTPD2UDQZ256rr:
21077 case VCVTTPD2UDQZ256rrk:
21078 case VCVTTPD2UDQZ256rrkz:
21079 case VCVTTPD2UDQZrm:
21080 case VCVTTPD2UDQZrmb:
21081 case VCVTTPD2UDQZrmbk:
21082 case VCVTTPD2UDQZrmbkz:
21083 case VCVTTPD2UDQZrmk:
21084 case VCVTTPD2UDQZrmkz:
21085 case VCVTTPD2UDQZrr:
21086 case VCVTTPD2UDQZrrb:
21087 case VCVTTPD2UDQZrrbk:
21088 case VCVTTPD2UDQZrrbkz:
21089 case VCVTTPD2UDQZrrk:
21090 case VCVTTPD2UDQZrrkz:
21091 return true;
21092 }
21093 return false;
21094}
21095
21096bool isERETU(unsigned Opcode) {
21097 return Opcode == ERETU;
21098}
21099
21100bool isPFRCPIT2(unsigned Opcode) {
21101 switch (Opcode) {
21102 case PFRCPIT2rm:
21103 case PFRCPIT2rr:
21104 return true;
21105 }
21106 return false;
21107}
21108
21109bool isVPERMT2W(unsigned Opcode) {
21110 switch (Opcode) {
21111 case VPERMT2WZ128rm:
21112 case VPERMT2WZ128rmk:
21113 case VPERMT2WZ128rmkz:
21114 case VPERMT2WZ128rr:
21115 case VPERMT2WZ128rrk:
21116 case VPERMT2WZ128rrkz:
21117 case VPERMT2WZ256rm:
21118 case VPERMT2WZ256rmk:
21119 case VPERMT2WZ256rmkz:
21120 case VPERMT2WZ256rr:
21121 case VPERMT2WZ256rrk:
21122 case VPERMT2WZ256rrkz:
21123 case VPERMT2WZrm:
21124 case VPERMT2WZrmk:
21125 case VPERMT2WZrmkz:
21126 case VPERMT2WZrr:
21127 case VPERMT2WZrrk:
21128 case VPERMT2WZrrkz:
21129 return true;
21130 }
21131 return false;
21132}
21133
21134bool isVEXTRACTF32X4(unsigned Opcode) {
21135 switch (Opcode) {
21136 case VEXTRACTF32X4Z256mri:
21137 case VEXTRACTF32X4Z256mrik:
21138 case VEXTRACTF32X4Z256rri:
21139 case VEXTRACTF32X4Z256rrik:
21140 case VEXTRACTF32X4Z256rrikz:
21141 case VEXTRACTF32X4Zmri:
21142 case VEXTRACTF32X4Zmrik:
21143 case VEXTRACTF32X4Zrri:
21144 case VEXTRACTF32X4Zrrik:
21145 case VEXTRACTF32X4Zrrikz:
21146 return true;
21147 }
21148 return false;
21149}
21150
21151bool isVGATHERPF0DPD(unsigned Opcode) {
21152 return Opcode == VGATHERPF0DPDm;
21153}
21154
21155bool isVBROADCASTF32X2(unsigned Opcode) {
21156 switch (Opcode) {
21157 case VBROADCASTF32X2Z256rm:
21158 case VBROADCASTF32X2Z256rmk:
21159 case VBROADCASTF32X2Z256rmkz:
21160 case VBROADCASTF32X2Z256rr:
21161 case VBROADCASTF32X2Z256rrk:
21162 case VBROADCASTF32X2Z256rrkz:
21163 case VBROADCASTF32X2Zrm:
21164 case VBROADCASTF32X2Zrmk:
21165 case VBROADCASTF32X2Zrmkz:
21166 case VBROADCASTF32X2Zrr:
21167 case VBROADCASTF32X2Zrrk:
21168 case VBROADCASTF32X2Zrrkz:
21169 return true;
21170 }
21171 return false;
21172}
21173
21174bool isVRCP14SD(unsigned Opcode) {
21175 switch (Opcode) {
21176 case VRCP14SDZrm:
21177 case VRCP14SDZrmk:
21178 case VRCP14SDZrmkz:
21179 case VRCP14SDZrr:
21180 case VRCP14SDZrrk:
21181 case VRCP14SDZrrkz:
21182 return true;
21183 }
21184 return false;
21185}
21186
21187bool isPABSD(unsigned Opcode) {
21188 switch (Opcode) {
21189 case MMX_PABSDrm:
21190 case MMX_PABSDrr:
21191 case PABSDrm:
21192 case PABSDrr:
21193 return true;
21194 }
21195 return false;
21196}
21197
21198bool isLAHF(unsigned Opcode) {
21199 return Opcode == LAHF;
21200}
21201
21202bool isPINSRB(unsigned Opcode) {
21203 switch (Opcode) {
21204 case PINSRBrmi:
21205 case PINSRBrri:
21206 return true;
21207 }
21208 return false;
21209}
21210
21211bool isSKINIT(unsigned Opcode) {
21212 return Opcode == SKINIT;
21213}
21214
21215bool isENTER(unsigned Opcode) {
21216 return Opcode == ENTER;
21217}
21218
21219bool isVCVTSI2SS(unsigned Opcode) {
21220 switch (Opcode) {
21221 case VCVTSI2SSZrm_Int:
21222 case VCVTSI2SSZrr_Int:
21223 case VCVTSI2SSZrrb_Int:
21224 case VCVTSI2SSrm_Int:
21225 case VCVTSI2SSrr_Int:
21226 case VCVTSI642SSZrm_Int:
21227 case VCVTSI642SSZrr_Int:
21228 case VCVTSI642SSZrrb_Int:
21229 case VCVTSI642SSrm_Int:
21230 case VCVTSI642SSrr_Int:
21231 return true;
21232 }
21233 return false;
21234}
21235
21236bool isVFMADD231PD(unsigned Opcode) {
21237 switch (Opcode) {
21238 case VFMADD231PDYm:
21239 case VFMADD231PDYr:
21240 case VFMADD231PDZ128m:
21241 case VFMADD231PDZ128mb:
21242 case VFMADD231PDZ128mbk:
21243 case VFMADD231PDZ128mbkz:
21244 case VFMADD231PDZ128mk:
21245 case VFMADD231PDZ128mkz:
21246 case VFMADD231PDZ128r:
21247 case VFMADD231PDZ128rk:
21248 case VFMADD231PDZ128rkz:
21249 case VFMADD231PDZ256m:
21250 case VFMADD231PDZ256mb:
21251 case VFMADD231PDZ256mbk:
21252 case VFMADD231PDZ256mbkz:
21253 case VFMADD231PDZ256mk:
21254 case VFMADD231PDZ256mkz:
21255 case VFMADD231PDZ256r:
21256 case VFMADD231PDZ256rk:
21257 case VFMADD231PDZ256rkz:
21258 case VFMADD231PDZm:
21259 case VFMADD231PDZmb:
21260 case VFMADD231PDZmbk:
21261 case VFMADD231PDZmbkz:
21262 case VFMADD231PDZmk:
21263 case VFMADD231PDZmkz:
21264 case VFMADD231PDZr:
21265 case VFMADD231PDZrb:
21266 case VFMADD231PDZrbk:
21267 case VFMADD231PDZrbkz:
21268 case VFMADD231PDZrk:
21269 case VFMADD231PDZrkz:
21270 case VFMADD231PDm:
21271 case VFMADD231PDr:
21272 return true;
21273 }
21274 return false;
21275}
21276
21277bool isLOADIWKEY(unsigned Opcode) {
21278 return Opcode == LOADIWKEY;
21279}
21280
21281bool isVMOVNTDQA(unsigned Opcode) {
21282 switch (Opcode) {
21283 case VMOVNTDQAYrm:
21284 case VMOVNTDQAZ128rm:
21285 case VMOVNTDQAZ256rm:
21286 case VMOVNTDQAZrm:
21287 case VMOVNTDQArm:
21288 return true;
21289 }
21290 return false;
21291}
21292
21293bool isVPERMT2PS(unsigned Opcode) {
21294 switch (Opcode) {
21295 case VPERMT2PSZ128rm:
21296 case VPERMT2PSZ128rmb:
21297 case VPERMT2PSZ128rmbk:
21298 case VPERMT2PSZ128rmbkz:
21299 case VPERMT2PSZ128rmk:
21300 case VPERMT2PSZ128rmkz:
21301 case VPERMT2PSZ128rr:
21302 case VPERMT2PSZ128rrk:
21303 case VPERMT2PSZ128rrkz:
21304 case VPERMT2PSZ256rm:
21305 case VPERMT2PSZ256rmb:
21306 case VPERMT2PSZ256rmbk:
21307 case VPERMT2PSZ256rmbkz:
21308 case VPERMT2PSZ256rmk:
21309 case VPERMT2PSZ256rmkz:
21310 case VPERMT2PSZ256rr:
21311 case VPERMT2PSZ256rrk:
21312 case VPERMT2PSZ256rrkz:
21313 case VPERMT2PSZrm:
21314 case VPERMT2PSZrmb:
21315 case VPERMT2PSZrmbk:
21316 case VPERMT2PSZrmbkz:
21317 case VPERMT2PSZrmk:
21318 case VPERMT2PSZrmkz:
21319 case VPERMT2PSZrr:
21320 case VPERMT2PSZrrk:
21321 case VPERMT2PSZrrkz:
21322 return true;
21323 }
21324 return false;
21325}
21326
21327bool isPUSHF(unsigned Opcode) {
21328 return Opcode == PUSHF16;
21329}
21330
21331bool isMPSADBW(unsigned Opcode) {
21332 switch (Opcode) {
21333 case MPSADBWrmi:
21334 case MPSADBWrri:
21335 return true;
21336 }
21337 return false;
21338}
21339
21340bool isVMINMAXSH(unsigned Opcode) {
21341 switch (Opcode) {
21342 case VMINMAXSHrmi_Int:
21343 case VMINMAXSHrmik_Int:
21344 case VMINMAXSHrmikz_Int:
21345 case VMINMAXSHrri_Int:
21346 case VMINMAXSHrrib_Int:
21347 case VMINMAXSHrribk_Int:
21348 case VMINMAXSHrribkz_Int:
21349 case VMINMAXSHrrik_Int:
21350 case VMINMAXSHrrikz_Int:
21351 return true;
21352 }
21353 return false;
21354}
21355
21356bool isVRSQRT14SS(unsigned Opcode) {
21357 switch (Opcode) {
21358 case VRSQRT14SSZrm:
21359 case VRSQRT14SSZrmk:
21360 case VRSQRT14SSZrmkz:
21361 case VRSQRT14SSZrr:
21362 case VRSQRT14SSZrrk:
21363 case VRSQRT14SSZrrkz:
21364 return true;
21365 }
21366 return false;
21367}
21368
21369bool isVCVTDQ2PD(unsigned Opcode) {
21370 switch (Opcode) {
21371 case VCVTDQ2PDYrm:
21372 case VCVTDQ2PDYrr:
21373 case VCVTDQ2PDZ128rm:
21374 case VCVTDQ2PDZ128rmb:
21375 case VCVTDQ2PDZ128rmbk:
21376 case VCVTDQ2PDZ128rmbkz:
21377 case VCVTDQ2PDZ128rmk:
21378 case VCVTDQ2PDZ128rmkz:
21379 case VCVTDQ2PDZ128rr:
21380 case VCVTDQ2PDZ128rrk:
21381 case VCVTDQ2PDZ128rrkz:
21382 case VCVTDQ2PDZ256rm:
21383 case VCVTDQ2PDZ256rmb:
21384 case VCVTDQ2PDZ256rmbk:
21385 case VCVTDQ2PDZ256rmbkz:
21386 case VCVTDQ2PDZ256rmk:
21387 case VCVTDQ2PDZ256rmkz:
21388 case VCVTDQ2PDZ256rr:
21389 case VCVTDQ2PDZ256rrk:
21390 case VCVTDQ2PDZ256rrkz:
21391 case VCVTDQ2PDZrm:
21392 case VCVTDQ2PDZrmb:
21393 case VCVTDQ2PDZrmbk:
21394 case VCVTDQ2PDZrmbkz:
21395 case VCVTDQ2PDZrmk:
21396 case VCVTDQ2PDZrmkz:
21397 case VCVTDQ2PDZrr:
21398 case VCVTDQ2PDZrrk:
21399 case VCVTDQ2PDZrrkz:
21400 case VCVTDQ2PDrm:
21401 case VCVTDQ2PDrr:
21402 return true;
21403 }
21404 return false;
21405}
21406
21407bool isVORPS(unsigned Opcode) {
21408 switch (Opcode) {
21409 case VORPSYrm:
21410 case VORPSYrr:
21411 case VORPSZ128rm:
21412 case VORPSZ128rmb:
21413 case VORPSZ128rmbk:
21414 case VORPSZ128rmbkz:
21415 case VORPSZ128rmk:
21416 case VORPSZ128rmkz:
21417 case VORPSZ128rr:
21418 case VORPSZ128rrk:
21419 case VORPSZ128rrkz:
21420 case VORPSZ256rm:
21421 case VORPSZ256rmb:
21422 case VORPSZ256rmbk:
21423 case VORPSZ256rmbkz:
21424 case VORPSZ256rmk:
21425 case VORPSZ256rmkz:
21426 case VORPSZ256rr:
21427 case VORPSZ256rrk:
21428 case VORPSZ256rrkz:
21429 case VORPSZrm:
21430 case VORPSZrmb:
21431 case VORPSZrmbk:
21432 case VORPSZrmbkz:
21433 case VORPSZrmk:
21434 case VORPSZrmkz:
21435 case VORPSZrr:
21436 case VORPSZrrk:
21437 case VORPSZrrkz:
21438 case VORPSrm:
21439 case VORPSrr:
21440 return true;
21441 }
21442 return false;
21443}
21444
21445bool isVPEXPANDQ(unsigned Opcode) {
21446 switch (Opcode) {
21447 case VPEXPANDQZ128rm:
21448 case VPEXPANDQZ128rmk:
21449 case VPEXPANDQZ128rmkz:
21450 case VPEXPANDQZ128rr:
21451 case VPEXPANDQZ128rrk:
21452 case VPEXPANDQZ128rrkz:
21453 case VPEXPANDQZ256rm:
21454 case VPEXPANDQZ256rmk:
21455 case VPEXPANDQZ256rmkz:
21456 case VPEXPANDQZ256rr:
21457 case VPEXPANDQZ256rrk:
21458 case VPEXPANDQZ256rrkz:
21459 case VPEXPANDQZrm:
21460 case VPEXPANDQZrmk:
21461 case VPEXPANDQZrmkz:
21462 case VPEXPANDQZrr:
21463 case VPEXPANDQZrrk:
21464 case VPEXPANDQZrrkz:
21465 return true;
21466 }
21467 return false;
21468}
21469
21470bool isVPSHRDD(unsigned Opcode) {
21471 switch (Opcode) {
21472 case VPSHRDDZ128rmbi:
21473 case VPSHRDDZ128rmbik:
21474 case VPSHRDDZ128rmbikz:
21475 case VPSHRDDZ128rmi:
21476 case VPSHRDDZ128rmik:
21477 case VPSHRDDZ128rmikz:
21478 case VPSHRDDZ128rri:
21479 case VPSHRDDZ128rrik:
21480 case VPSHRDDZ128rrikz:
21481 case VPSHRDDZ256rmbi:
21482 case VPSHRDDZ256rmbik:
21483 case VPSHRDDZ256rmbikz:
21484 case VPSHRDDZ256rmi:
21485 case VPSHRDDZ256rmik:
21486 case VPSHRDDZ256rmikz:
21487 case VPSHRDDZ256rri:
21488 case VPSHRDDZ256rrik:
21489 case VPSHRDDZ256rrikz:
21490 case VPSHRDDZrmbi:
21491 case VPSHRDDZrmbik:
21492 case VPSHRDDZrmbikz:
21493 case VPSHRDDZrmi:
21494 case VPSHRDDZrmik:
21495 case VPSHRDDZrmikz:
21496 case VPSHRDDZrri:
21497 case VPSHRDDZrrik:
21498 case VPSHRDDZrrikz:
21499 return true;
21500 }
21501 return false;
21502}
21503
21504bool isTDPBSSD(unsigned Opcode) {
21505 return Opcode == TDPBSSD;
21506}
21507
21508bool isTESTUI(unsigned Opcode) {
21509 return Opcode == TESTUI;
21510}
21511
21512bool isVFMADDPD(unsigned Opcode) {
21513 switch (Opcode) {
21514 case VFMADDPD4Ymr:
21515 case VFMADDPD4Yrm:
21516 case VFMADDPD4Yrr:
21517 case VFMADDPD4Yrr_REV:
21518 case VFMADDPD4mr:
21519 case VFMADDPD4rm:
21520 case VFMADDPD4rr:
21521 case VFMADDPD4rr_REV:
21522 return true;
21523 }
21524 return false;
21525}
21526
21527bool isVPANDND(unsigned Opcode) {
21528 switch (Opcode) {
21529 case VPANDNDZ128rm:
21530 case VPANDNDZ128rmb:
21531 case VPANDNDZ128rmbk:
21532 case VPANDNDZ128rmbkz:
21533 case VPANDNDZ128rmk:
21534 case VPANDNDZ128rmkz:
21535 case VPANDNDZ128rr:
21536 case VPANDNDZ128rrk:
21537 case VPANDNDZ128rrkz:
21538 case VPANDNDZ256rm:
21539 case VPANDNDZ256rmb:
21540 case VPANDNDZ256rmbk:
21541 case VPANDNDZ256rmbkz:
21542 case VPANDNDZ256rmk:
21543 case VPANDNDZ256rmkz:
21544 case VPANDNDZ256rr:
21545 case VPANDNDZ256rrk:
21546 case VPANDNDZ256rrkz:
21547 case VPANDNDZrm:
21548 case VPANDNDZrmb:
21549 case VPANDNDZrmbk:
21550 case VPANDNDZrmbkz:
21551 case VPANDNDZrmk:
21552 case VPANDNDZrmkz:
21553 case VPANDNDZrr:
21554 case VPANDNDZrrk:
21555 case VPANDNDZrrkz:
21556 return true;
21557 }
21558 return false;
21559}
21560
21561bool isVPMOVSDB(unsigned Opcode) {
21562 switch (Opcode) {
21563 case VPMOVSDBZ128mr:
21564 case VPMOVSDBZ128mrk:
21565 case VPMOVSDBZ128rr:
21566 case VPMOVSDBZ128rrk:
21567 case VPMOVSDBZ128rrkz:
21568 case VPMOVSDBZ256mr:
21569 case VPMOVSDBZ256mrk:
21570 case VPMOVSDBZ256rr:
21571 case VPMOVSDBZ256rrk:
21572 case VPMOVSDBZ256rrkz:
21573 case VPMOVSDBZmr:
21574 case VPMOVSDBZmrk:
21575 case VPMOVSDBZrr:
21576 case VPMOVSDBZrrk:
21577 case VPMOVSDBZrrkz:
21578 return true;
21579 }
21580 return false;
21581}
21582
21583bool isVPBROADCASTB(unsigned Opcode) {
21584 switch (Opcode) {
21585 case VPBROADCASTBYrm:
21586 case VPBROADCASTBYrr:
21587 case VPBROADCASTBZ128rm:
21588 case VPBROADCASTBZ128rmk:
21589 case VPBROADCASTBZ128rmkz:
21590 case VPBROADCASTBZ128rr:
21591 case VPBROADCASTBZ128rrk:
21592 case VPBROADCASTBZ128rrkz:
21593 case VPBROADCASTBZ256rm:
21594 case VPBROADCASTBZ256rmk:
21595 case VPBROADCASTBZ256rmkz:
21596 case VPBROADCASTBZ256rr:
21597 case VPBROADCASTBZ256rrk:
21598 case VPBROADCASTBZ256rrkz:
21599 case VPBROADCASTBZrm:
21600 case VPBROADCASTBZrmk:
21601 case VPBROADCASTBZrmkz:
21602 case VPBROADCASTBZrr:
21603 case VPBROADCASTBZrrk:
21604 case VPBROADCASTBZrrkz:
21605 case VPBROADCASTBrZ128rr:
21606 case VPBROADCASTBrZ128rrk:
21607 case VPBROADCASTBrZ128rrkz:
21608 case VPBROADCASTBrZ256rr:
21609 case VPBROADCASTBrZ256rrk:
21610 case VPBROADCASTBrZ256rrkz:
21611 case VPBROADCASTBrZrr:
21612 case VPBROADCASTBrZrrk:
21613 case VPBROADCASTBrZrrkz:
21614 case VPBROADCASTBrm:
21615 case VPBROADCASTBrr:
21616 return true;
21617 }
21618 return false;
21619}
21620
21621bool isCVTPI2PD(unsigned Opcode) {
21622 switch (Opcode) {
21623 case MMX_CVTPI2PDrm:
21624 case MMX_CVTPI2PDrr:
21625 return true;
21626 }
21627 return false;
21628}
21629
21630bool isVPERMI2B(unsigned Opcode) {
21631 switch (Opcode) {
21632 case VPERMI2BZ128rm:
21633 case VPERMI2BZ128rmk:
21634 case VPERMI2BZ128rmkz:
21635 case VPERMI2BZ128rr:
21636 case VPERMI2BZ128rrk:
21637 case VPERMI2BZ128rrkz:
21638 case VPERMI2BZ256rm:
21639 case VPERMI2BZ256rmk:
21640 case VPERMI2BZ256rmkz:
21641 case VPERMI2BZ256rr:
21642 case VPERMI2BZ256rrk:
21643 case VPERMI2BZ256rrkz:
21644 case VPERMI2BZrm:
21645 case VPERMI2BZrmk:
21646 case VPERMI2BZrmkz:
21647 case VPERMI2BZrr:
21648 case VPERMI2BZrrk:
21649 case VPERMI2BZrrkz:
21650 return true;
21651 }
21652 return false;
21653}
21654
21655bool isVPMINSB(unsigned Opcode) {
21656 switch (Opcode) {
21657 case VPMINSBYrm:
21658 case VPMINSBYrr:
21659 case VPMINSBZ128rm:
21660 case VPMINSBZ128rmk:
21661 case VPMINSBZ128rmkz:
21662 case VPMINSBZ128rr:
21663 case VPMINSBZ128rrk:
21664 case VPMINSBZ128rrkz:
21665 case VPMINSBZ256rm:
21666 case VPMINSBZ256rmk:
21667 case VPMINSBZ256rmkz:
21668 case VPMINSBZ256rr:
21669 case VPMINSBZ256rrk:
21670 case VPMINSBZ256rrkz:
21671 case VPMINSBZrm:
21672 case VPMINSBZrmk:
21673 case VPMINSBZrmkz:
21674 case VPMINSBZrr:
21675 case VPMINSBZrrk:
21676 case VPMINSBZrrkz:
21677 case VPMINSBrm:
21678 case VPMINSBrr:
21679 return true;
21680 }
21681 return false;
21682}
21683
21684bool isLAR(unsigned Opcode) {
21685 switch (Opcode) {
21686 case LAR16rm:
21687 case LAR16rr:
21688 case LAR32rm:
21689 case LAR32rr:
21690 case LAR64rm:
21691 case LAR64rr:
21692 return true;
21693 }
21694 return false;
21695}
21696
21697bool isINVLPGB(unsigned Opcode) {
21698 switch (Opcode) {
21699 case INVLPGB32:
21700 case INVLPGB64:
21701 return true;
21702 }
21703 return false;
21704}
21705
21706bool isTLBSYNC(unsigned Opcode) {
21707 return Opcode == TLBSYNC;
21708}
21709
21710bool isFDIVP(unsigned Opcode) {
21711 return Opcode == DIV_FPrST0;
21712}
21713
21714bool isVPSRLW(unsigned Opcode) {
21715 switch (Opcode) {
21716 case VPSRLWYri:
21717 case VPSRLWYrm:
21718 case VPSRLWYrr:
21719 case VPSRLWZ128mi:
21720 case VPSRLWZ128mik:
21721 case VPSRLWZ128mikz:
21722 case VPSRLWZ128ri:
21723 case VPSRLWZ128rik:
21724 case VPSRLWZ128rikz:
21725 case VPSRLWZ128rm:
21726 case VPSRLWZ128rmk:
21727 case VPSRLWZ128rmkz:
21728 case VPSRLWZ128rr:
21729 case VPSRLWZ128rrk:
21730 case VPSRLWZ128rrkz:
21731 case VPSRLWZ256mi:
21732 case VPSRLWZ256mik:
21733 case VPSRLWZ256mikz:
21734 case VPSRLWZ256ri:
21735 case VPSRLWZ256rik:
21736 case VPSRLWZ256rikz:
21737 case VPSRLWZ256rm:
21738 case VPSRLWZ256rmk:
21739 case VPSRLWZ256rmkz:
21740 case VPSRLWZ256rr:
21741 case VPSRLWZ256rrk:
21742 case VPSRLWZ256rrkz:
21743 case VPSRLWZmi:
21744 case VPSRLWZmik:
21745 case VPSRLWZmikz:
21746 case VPSRLWZri:
21747 case VPSRLWZrik:
21748 case VPSRLWZrikz:
21749 case VPSRLWZrm:
21750 case VPSRLWZrmk:
21751 case VPSRLWZrmkz:
21752 case VPSRLWZrr:
21753 case VPSRLWZrrk:
21754 case VPSRLWZrrkz:
21755 case VPSRLWri:
21756 case VPSRLWrm:
21757 case VPSRLWrr:
21758 return true;
21759 }
21760 return false;
21761}
21762
21763bool isVRCP28SS(unsigned Opcode) {
21764 switch (Opcode) {
21765 case VRCP28SSZm:
21766 case VRCP28SSZmk:
21767 case VRCP28SSZmkz:
21768 case VRCP28SSZr:
21769 case VRCP28SSZrb:
21770 case VRCP28SSZrbk:
21771 case VRCP28SSZrbkz:
21772 case VRCP28SSZrk:
21773 case VRCP28SSZrkz:
21774 return true;
21775 }
21776 return false;
21777}
21778
21779bool isVMOVHPS(unsigned Opcode) {
21780 switch (Opcode) {
21781 case VMOVHPSZ128mr:
21782 case VMOVHPSZ128rm:
21783 case VMOVHPSmr:
21784 case VMOVHPSrm:
21785 return true;
21786 }
21787 return false;
21788}
21789
21790bool isVPMACSSDD(unsigned Opcode) {
21791 switch (Opcode) {
21792 case VPMACSSDDrm:
21793 case VPMACSSDDrr:
21794 return true;
21795 }
21796 return false;
21797}
21798
21799bool isPEXT(unsigned Opcode) {
21800 switch (Opcode) {
21801 case PEXT32rm:
21802 case PEXT32rm_EVEX:
21803 case PEXT32rr:
21804 case PEXT32rr_EVEX:
21805 case PEXT64rm:
21806 case PEXT64rm_EVEX:
21807 case PEXT64rr:
21808 case PEXT64rr_EVEX:
21809 return true;
21810 }
21811 return false;
21812}
21813
21814bool isVMAXBF16(unsigned Opcode) {
21815 switch (Opcode) {
21816 case VMAXBF16Z128rm:
21817 case VMAXBF16Z128rmb:
21818 case VMAXBF16Z128rmbk:
21819 case VMAXBF16Z128rmbkz:
21820 case VMAXBF16Z128rmk:
21821 case VMAXBF16Z128rmkz:
21822 case VMAXBF16Z128rr:
21823 case VMAXBF16Z128rrk:
21824 case VMAXBF16Z128rrkz:
21825 case VMAXBF16Z256rm:
21826 case VMAXBF16Z256rmb:
21827 case VMAXBF16Z256rmbk:
21828 case VMAXBF16Z256rmbkz:
21829 case VMAXBF16Z256rmk:
21830 case VMAXBF16Z256rmkz:
21831 case VMAXBF16Z256rr:
21832 case VMAXBF16Z256rrk:
21833 case VMAXBF16Z256rrkz:
21834 case VMAXBF16Zrm:
21835 case VMAXBF16Zrmb:
21836 case VMAXBF16Zrmbk:
21837 case VMAXBF16Zrmbkz:
21838 case VMAXBF16Zrmk:
21839 case VMAXBF16Zrmkz:
21840 case VMAXBF16Zrr:
21841 case VMAXBF16Zrrk:
21842 case VMAXBF16Zrrkz:
21843 return true;
21844 }
21845 return false;
21846}
21847
21848bool isVRSQRT14SD(unsigned Opcode) {
21849 switch (Opcode) {
21850 case VRSQRT14SDZrm:
21851 case VRSQRT14SDZrmk:
21852 case VRSQRT14SDZrmkz:
21853 case VRSQRT14SDZrr:
21854 case VRSQRT14SDZrrk:
21855 case VRSQRT14SDZrrkz:
21856 return true;
21857 }
21858 return false;
21859}
21860
21861bool isVPDPWSSD(unsigned Opcode) {
21862 switch (Opcode) {
21863 case VPDPWSSDYrm:
21864 case VPDPWSSDYrr:
21865 case VPDPWSSDZ128rm:
21866 case VPDPWSSDZ128rmb:
21867 case VPDPWSSDZ128rmbk:
21868 case VPDPWSSDZ128rmbkz:
21869 case VPDPWSSDZ128rmk:
21870 case VPDPWSSDZ128rmkz:
21871 case VPDPWSSDZ128rr:
21872 case VPDPWSSDZ128rrk:
21873 case VPDPWSSDZ128rrkz:
21874 case VPDPWSSDZ256rm:
21875 case VPDPWSSDZ256rmb:
21876 case VPDPWSSDZ256rmbk:
21877 case VPDPWSSDZ256rmbkz:
21878 case VPDPWSSDZ256rmk:
21879 case VPDPWSSDZ256rmkz:
21880 case VPDPWSSDZ256rr:
21881 case VPDPWSSDZ256rrk:
21882 case VPDPWSSDZ256rrkz:
21883 case VPDPWSSDZrm:
21884 case VPDPWSSDZrmb:
21885 case VPDPWSSDZrmbk:
21886 case VPDPWSSDZrmbkz:
21887 case VPDPWSSDZrmk:
21888 case VPDPWSSDZrmkz:
21889 case VPDPWSSDZrr:
21890 case VPDPWSSDZrrk:
21891 case VPDPWSSDZrrkz:
21892 case VPDPWSSDrm:
21893 case VPDPWSSDrr:
21894 return true;
21895 }
21896 return false;
21897}
21898
21899bool isVFMSUB231SD(unsigned Opcode) {
21900 switch (Opcode) {
21901 case VFMSUB231SDZm_Int:
21902 case VFMSUB231SDZmk_Int:
21903 case VFMSUB231SDZmkz_Int:
21904 case VFMSUB231SDZr_Int:
21905 case VFMSUB231SDZrb_Int:
21906 case VFMSUB231SDZrbk_Int:
21907 case VFMSUB231SDZrbkz_Int:
21908 case VFMSUB231SDZrk_Int:
21909 case VFMSUB231SDZrkz_Int:
21910 case VFMSUB231SDm_Int:
21911 case VFMSUB231SDr_Int:
21912 return true;
21913 }
21914 return false;
21915}
21916
21917bool isVPMOVZXWQ(unsigned Opcode) {
21918 switch (Opcode) {
21919 case VPMOVZXWQYrm:
21920 case VPMOVZXWQYrr:
21921 case VPMOVZXWQZ128rm:
21922 case VPMOVZXWQZ128rmk:
21923 case VPMOVZXWQZ128rmkz:
21924 case VPMOVZXWQZ128rr:
21925 case VPMOVZXWQZ128rrk:
21926 case VPMOVZXWQZ128rrkz:
21927 case VPMOVZXWQZ256rm:
21928 case VPMOVZXWQZ256rmk:
21929 case VPMOVZXWQZ256rmkz:
21930 case VPMOVZXWQZ256rr:
21931 case VPMOVZXWQZ256rrk:
21932 case VPMOVZXWQZ256rrkz:
21933 case VPMOVZXWQZrm:
21934 case VPMOVZXWQZrmk:
21935 case VPMOVZXWQZrmkz:
21936 case VPMOVZXWQZrr:
21937 case VPMOVZXWQZrrk:
21938 case VPMOVZXWQZrrkz:
21939 case VPMOVZXWQrm:
21940 case VPMOVZXWQrr:
21941 return true;
21942 }
21943 return false;
21944}
21945
21946bool isVMOVDQA(unsigned Opcode) {
21947 switch (Opcode) {
21948 case VMOVDQAYmr:
21949 case VMOVDQAYrm:
21950 case VMOVDQAYrr:
21951 case VMOVDQAYrr_REV:
21952 case VMOVDQAmr:
21953 case VMOVDQArm:
21954 case VMOVDQArr:
21955 case VMOVDQArr_REV:
21956 return true;
21957 }
21958 return false;
21959}
21960
21961bool isVFNMSUB213SD(unsigned Opcode) {
21962 switch (Opcode) {
21963 case VFNMSUB213SDZm_Int:
21964 case VFNMSUB213SDZmk_Int:
21965 case VFNMSUB213SDZmkz_Int:
21966 case VFNMSUB213SDZr_Int:
21967 case VFNMSUB213SDZrb_Int:
21968 case VFNMSUB213SDZrbk_Int:
21969 case VFNMSUB213SDZrbkz_Int:
21970 case VFNMSUB213SDZrk_Int:
21971 case VFNMSUB213SDZrkz_Int:
21972 case VFNMSUB213SDm_Int:
21973 case VFNMSUB213SDr_Int:
21974 return true;
21975 }
21976 return false;
21977}
21978
21979bool isVMINPS(unsigned Opcode) {
21980 switch (Opcode) {
21981 case VMINPSYrm:
21982 case VMINPSYrr:
21983 case VMINPSZ128rm:
21984 case VMINPSZ128rmb:
21985 case VMINPSZ128rmbk:
21986 case VMINPSZ128rmbkz:
21987 case VMINPSZ128rmk:
21988 case VMINPSZ128rmkz:
21989 case VMINPSZ128rr:
21990 case VMINPSZ128rrk:
21991 case VMINPSZ128rrkz:
21992 case VMINPSZ256rm:
21993 case VMINPSZ256rmb:
21994 case VMINPSZ256rmbk:
21995 case VMINPSZ256rmbkz:
21996 case VMINPSZ256rmk:
21997 case VMINPSZ256rmkz:
21998 case VMINPSZ256rr:
21999 case VMINPSZ256rrk:
22000 case VMINPSZ256rrkz:
22001 case VMINPSZrm:
22002 case VMINPSZrmb:
22003 case VMINPSZrmbk:
22004 case VMINPSZrmbkz:
22005 case VMINPSZrmk:
22006 case VMINPSZrmkz:
22007 case VMINPSZrr:
22008 case VMINPSZrrb:
22009 case VMINPSZrrbk:
22010 case VMINPSZrrbkz:
22011 case VMINPSZrrk:
22012 case VMINPSZrrkz:
22013 case VMINPSrm:
22014 case VMINPSrr:
22015 return true;
22016 }
22017 return false;
22018}
22019
22020bool isVFMSUB231PS(unsigned Opcode) {
22021 switch (Opcode) {
22022 case VFMSUB231PSYm:
22023 case VFMSUB231PSYr:
22024 case VFMSUB231PSZ128m:
22025 case VFMSUB231PSZ128mb:
22026 case VFMSUB231PSZ128mbk:
22027 case VFMSUB231PSZ128mbkz:
22028 case VFMSUB231PSZ128mk:
22029 case VFMSUB231PSZ128mkz:
22030 case VFMSUB231PSZ128r:
22031 case VFMSUB231PSZ128rk:
22032 case VFMSUB231PSZ128rkz:
22033 case VFMSUB231PSZ256m:
22034 case VFMSUB231PSZ256mb:
22035 case VFMSUB231PSZ256mbk:
22036 case VFMSUB231PSZ256mbkz:
22037 case VFMSUB231PSZ256mk:
22038 case VFMSUB231PSZ256mkz:
22039 case VFMSUB231PSZ256r:
22040 case VFMSUB231PSZ256rk:
22041 case VFMSUB231PSZ256rkz:
22042 case VFMSUB231PSZm:
22043 case VFMSUB231PSZmb:
22044 case VFMSUB231PSZmbk:
22045 case VFMSUB231PSZmbkz:
22046 case VFMSUB231PSZmk:
22047 case VFMSUB231PSZmkz:
22048 case VFMSUB231PSZr:
22049 case VFMSUB231PSZrb:
22050 case VFMSUB231PSZrbk:
22051 case VFMSUB231PSZrbkz:
22052 case VFMSUB231PSZrk:
22053 case VFMSUB231PSZrkz:
22054 case VFMSUB231PSm:
22055 case VFMSUB231PSr:
22056 return true;
22057 }
22058 return false;
22059}
22060
22061bool isVPCOMPRESSB(unsigned Opcode) {
22062 switch (Opcode) {
22063 case VPCOMPRESSBZ128mr:
22064 case VPCOMPRESSBZ128mrk:
22065 case VPCOMPRESSBZ128rr:
22066 case VPCOMPRESSBZ128rrk:
22067 case VPCOMPRESSBZ128rrkz:
22068 case VPCOMPRESSBZ256mr:
22069 case VPCOMPRESSBZ256mrk:
22070 case VPCOMPRESSBZ256rr:
22071 case VPCOMPRESSBZ256rrk:
22072 case VPCOMPRESSBZ256rrkz:
22073 case VPCOMPRESSBZmr:
22074 case VPCOMPRESSBZmrk:
22075 case VPCOMPRESSBZrr:
22076 case VPCOMPRESSBZrrk:
22077 case VPCOMPRESSBZrrkz:
22078 return true;
22079 }
22080 return false;
22081}
22082
22083bool isVPCMPEQQ(unsigned Opcode) {
22084 switch (Opcode) {
22085 case VPCMPEQQYrm:
22086 case VPCMPEQQYrr:
22087 case VPCMPEQQZ128rm:
22088 case VPCMPEQQZ128rmb:
22089 case VPCMPEQQZ128rmbk:
22090 case VPCMPEQQZ128rmk:
22091 case VPCMPEQQZ128rr:
22092 case VPCMPEQQZ128rrk:
22093 case VPCMPEQQZ256rm:
22094 case VPCMPEQQZ256rmb:
22095 case VPCMPEQQZ256rmbk:
22096 case VPCMPEQQZ256rmk:
22097 case VPCMPEQQZ256rr:
22098 case VPCMPEQQZ256rrk:
22099 case VPCMPEQQZrm:
22100 case VPCMPEQQZrmb:
22101 case VPCMPEQQZrmbk:
22102 case VPCMPEQQZrmk:
22103 case VPCMPEQQZrr:
22104 case VPCMPEQQZrrk:
22105 case VPCMPEQQrm:
22106 case VPCMPEQQrr:
22107 return true;
22108 }
22109 return false;
22110}
22111
22112bool isVRCPSS(unsigned Opcode) {
22113 switch (Opcode) {
22114 case VRCPSSm_Int:
22115 case VRCPSSr_Int:
22116 return true;
22117 }
22118 return false;
22119}
22120
22121bool isVSCATTERPF1DPS(unsigned Opcode) {
22122 return Opcode == VSCATTERPF1DPSm;
22123}
22124
22125bool isVPHADDUBW(unsigned Opcode) {
22126 switch (Opcode) {
22127 case VPHADDUBWrm:
22128 case VPHADDUBWrr:
22129 return true;
22130 }
22131 return false;
22132}
22133
22134bool isXORPD(unsigned Opcode) {
22135 switch (Opcode) {
22136 case XORPDrm:
22137 case XORPDrr:
22138 return true;
22139 }
22140 return false;
22141}
22142
22143bool isVPSCATTERQQ(unsigned Opcode) {
22144 switch (Opcode) {
22145 case VPSCATTERQQZ128mr:
22146 case VPSCATTERQQZ256mr:
22147 case VPSCATTERQQZmr:
22148 return true;
22149 }
22150 return false;
22151}
22152
22153bool isVCVTW2PH(unsigned Opcode) {
22154 switch (Opcode) {
22155 case VCVTW2PHZ128rm:
22156 case VCVTW2PHZ128rmb:
22157 case VCVTW2PHZ128rmbk:
22158 case VCVTW2PHZ128rmbkz:
22159 case VCVTW2PHZ128rmk:
22160 case VCVTW2PHZ128rmkz:
22161 case VCVTW2PHZ128rr:
22162 case VCVTW2PHZ128rrk:
22163 case VCVTW2PHZ128rrkz:
22164 case VCVTW2PHZ256rm:
22165 case VCVTW2PHZ256rmb:
22166 case VCVTW2PHZ256rmbk:
22167 case VCVTW2PHZ256rmbkz:
22168 case VCVTW2PHZ256rmk:
22169 case VCVTW2PHZ256rmkz:
22170 case VCVTW2PHZ256rr:
22171 case VCVTW2PHZ256rrk:
22172 case VCVTW2PHZ256rrkz:
22173 case VCVTW2PHZrm:
22174 case VCVTW2PHZrmb:
22175 case VCVTW2PHZrmbk:
22176 case VCVTW2PHZrmbkz:
22177 case VCVTW2PHZrmk:
22178 case VCVTW2PHZrmkz:
22179 case VCVTW2PHZrr:
22180 case VCVTW2PHZrrb:
22181 case VCVTW2PHZrrbk:
22182 case VCVTW2PHZrrbkz:
22183 case VCVTW2PHZrrk:
22184 case VCVTW2PHZrrkz:
22185 return true;
22186 }
22187 return false;
22188}
22189
22190bool isVFMADDCPH(unsigned Opcode) {
22191 switch (Opcode) {
22192 case VFMADDCPHZ128m:
22193 case VFMADDCPHZ128mb:
22194 case VFMADDCPHZ128mbk:
22195 case VFMADDCPHZ128mbkz:
22196 case VFMADDCPHZ128mk:
22197 case VFMADDCPHZ128mkz:
22198 case VFMADDCPHZ128r:
22199 case VFMADDCPHZ128rk:
22200 case VFMADDCPHZ128rkz:
22201 case VFMADDCPHZ256m:
22202 case VFMADDCPHZ256mb:
22203 case VFMADDCPHZ256mbk:
22204 case VFMADDCPHZ256mbkz:
22205 case VFMADDCPHZ256mk:
22206 case VFMADDCPHZ256mkz:
22207 case VFMADDCPHZ256r:
22208 case VFMADDCPHZ256rk:
22209 case VFMADDCPHZ256rkz:
22210 case VFMADDCPHZm:
22211 case VFMADDCPHZmb:
22212 case VFMADDCPHZmbk:
22213 case VFMADDCPHZmbkz:
22214 case VFMADDCPHZmk:
22215 case VFMADDCPHZmkz:
22216 case VFMADDCPHZr:
22217 case VFMADDCPHZrb:
22218 case VFMADDCPHZrbk:
22219 case VFMADDCPHZrbkz:
22220 case VFMADDCPHZrk:
22221 case VFMADDCPHZrkz:
22222 return true;
22223 }
22224 return false;
22225}
22226
22227bool isVSUBPD(unsigned Opcode) {
22228 switch (Opcode) {
22229 case VSUBPDYrm:
22230 case VSUBPDYrr:
22231 case VSUBPDZ128rm:
22232 case VSUBPDZ128rmb:
22233 case VSUBPDZ128rmbk:
22234 case VSUBPDZ128rmbkz:
22235 case VSUBPDZ128rmk:
22236 case VSUBPDZ128rmkz:
22237 case VSUBPDZ128rr:
22238 case VSUBPDZ128rrk:
22239 case VSUBPDZ128rrkz:
22240 case VSUBPDZ256rm:
22241 case VSUBPDZ256rmb:
22242 case VSUBPDZ256rmbk:
22243 case VSUBPDZ256rmbkz:
22244 case VSUBPDZ256rmk:
22245 case VSUBPDZ256rmkz:
22246 case VSUBPDZ256rr:
22247 case VSUBPDZ256rrk:
22248 case VSUBPDZ256rrkz:
22249 case VSUBPDZrm:
22250 case VSUBPDZrmb:
22251 case VSUBPDZrmbk:
22252 case VSUBPDZrmbkz:
22253 case VSUBPDZrmk:
22254 case VSUBPDZrmkz:
22255 case VSUBPDZrr:
22256 case VSUBPDZrrb:
22257 case VSUBPDZrrbk:
22258 case VSUBPDZrrbkz:
22259 case VSUBPDZrrk:
22260 case VSUBPDZrrkz:
22261 case VSUBPDrm:
22262 case VSUBPDrr:
22263 return true;
22264 }
22265 return false;
22266}
22267
22268bool isVPACKUSDW(unsigned Opcode) {
22269 switch (Opcode) {
22270 case VPACKUSDWYrm:
22271 case VPACKUSDWYrr:
22272 case VPACKUSDWZ128rm:
22273 case VPACKUSDWZ128rmb:
22274 case VPACKUSDWZ128rmbk:
22275 case VPACKUSDWZ128rmbkz:
22276 case VPACKUSDWZ128rmk:
22277 case VPACKUSDWZ128rmkz:
22278 case VPACKUSDWZ128rr:
22279 case VPACKUSDWZ128rrk:
22280 case VPACKUSDWZ128rrkz:
22281 case VPACKUSDWZ256rm:
22282 case VPACKUSDWZ256rmb:
22283 case VPACKUSDWZ256rmbk:
22284 case VPACKUSDWZ256rmbkz:
22285 case VPACKUSDWZ256rmk:
22286 case VPACKUSDWZ256rmkz:
22287 case VPACKUSDWZ256rr:
22288 case VPACKUSDWZ256rrk:
22289 case VPACKUSDWZ256rrkz:
22290 case VPACKUSDWZrm:
22291 case VPACKUSDWZrmb:
22292 case VPACKUSDWZrmbk:
22293 case VPACKUSDWZrmbkz:
22294 case VPACKUSDWZrmk:
22295 case VPACKUSDWZrmkz:
22296 case VPACKUSDWZrr:
22297 case VPACKUSDWZrrk:
22298 case VPACKUSDWZrrkz:
22299 case VPACKUSDWrm:
22300 case VPACKUSDWrr:
22301 return true;
22302 }
22303 return false;
22304}
22305
22306bool isVSCALEFSS(unsigned Opcode) {
22307 switch (Opcode) {
22308 case VSCALEFSSZrm:
22309 case VSCALEFSSZrmk:
22310 case VSCALEFSSZrmkz:
22311 case VSCALEFSSZrr:
22312 case VSCALEFSSZrrb_Int:
22313 case VSCALEFSSZrrbk_Int:
22314 case VSCALEFSSZrrbkz_Int:
22315 case VSCALEFSSZrrk:
22316 case VSCALEFSSZrrkz:
22317 return true;
22318 }
22319 return false;
22320}
22321
22322bool isAESIMC(unsigned Opcode) {
22323 switch (Opcode) {
22324 case AESIMCrm:
22325 case AESIMCrr:
22326 return true;
22327 }
22328 return false;
22329}
22330
22331bool isVRCP28PS(unsigned Opcode) {
22332 switch (Opcode) {
22333 case VRCP28PSZm:
22334 case VRCP28PSZmb:
22335 case VRCP28PSZmbk:
22336 case VRCP28PSZmbkz:
22337 case VRCP28PSZmk:
22338 case VRCP28PSZmkz:
22339 case VRCP28PSZr:
22340 case VRCP28PSZrb:
22341 case VRCP28PSZrbk:
22342 case VRCP28PSZrbkz:
22343 case VRCP28PSZrk:
22344 case VRCP28PSZrkz:
22345 return true;
22346 }
22347 return false;
22348}
22349
22350bool isAAND(unsigned Opcode) {
22351 switch (Opcode) {
22352 case AAND32mr:
22353 case AAND32mr_EVEX:
22354 case AAND64mr:
22355 case AAND64mr_EVEX:
22356 return true;
22357 }
22358 return false;
22359}
22360
22361bool isDAA(unsigned Opcode) {
22362 return Opcode == DAA;
22363}
22364
22365bool isVCVTPD2UDQ(unsigned Opcode) {
22366 switch (Opcode) {
22367 case VCVTPD2UDQZ128rm:
22368 case VCVTPD2UDQZ128rmb:
22369 case VCVTPD2UDQZ128rmbk:
22370 case VCVTPD2UDQZ128rmbkz:
22371 case VCVTPD2UDQZ128rmk:
22372 case VCVTPD2UDQZ128rmkz:
22373 case VCVTPD2UDQZ128rr:
22374 case VCVTPD2UDQZ128rrk:
22375 case VCVTPD2UDQZ128rrkz:
22376 case VCVTPD2UDQZ256rm:
22377 case VCVTPD2UDQZ256rmb:
22378 case VCVTPD2UDQZ256rmbk:
22379 case VCVTPD2UDQZ256rmbkz:
22380 case VCVTPD2UDQZ256rmk:
22381 case VCVTPD2UDQZ256rmkz:
22382 case VCVTPD2UDQZ256rr:
22383 case VCVTPD2UDQZ256rrk:
22384 case VCVTPD2UDQZ256rrkz:
22385 case VCVTPD2UDQZrm:
22386 case VCVTPD2UDQZrmb:
22387 case VCVTPD2UDQZrmbk:
22388 case VCVTPD2UDQZrmbkz:
22389 case VCVTPD2UDQZrmk:
22390 case VCVTPD2UDQZrmkz:
22391 case VCVTPD2UDQZrr:
22392 case VCVTPD2UDQZrrb:
22393 case VCVTPD2UDQZrrbk:
22394 case VCVTPD2UDQZrrbkz:
22395 case VCVTPD2UDQZrrk:
22396 case VCVTPD2UDQZrrkz:
22397 return true;
22398 }
22399 return false;
22400}
22401
22402bool isKTESTW(unsigned Opcode) {
22403 return Opcode == KTESTWkk;
22404}
22405
22406bool isVPADDQ(unsigned Opcode) {
22407 switch (Opcode) {
22408 case VPADDQYrm:
22409 case VPADDQYrr:
22410 case VPADDQZ128rm:
22411 case VPADDQZ128rmb:
22412 case VPADDQZ128rmbk:
22413 case VPADDQZ128rmbkz:
22414 case VPADDQZ128rmk:
22415 case VPADDQZ128rmkz:
22416 case VPADDQZ128rr:
22417 case VPADDQZ128rrk:
22418 case VPADDQZ128rrkz:
22419 case VPADDQZ256rm:
22420 case VPADDQZ256rmb:
22421 case VPADDQZ256rmbk:
22422 case VPADDQZ256rmbkz:
22423 case VPADDQZ256rmk:
22424 case VPADDQZ256rmkz:
22425 case VPADDQZ256rr:
22426 case VPADDQZ256rrk:
22427 case VPADDQZ256rrkz:
22428 case VPADDQZrm:
22429 case VPADDQZrmb:
22430 case VPADDQZrmbk:
22431 case VPADDQZrmbkz:
22432 case VPADDQZrmk:
22433 case VPADDQZrmkz:
22434 case VPADDQZrr:
22435 case VPADDQZrrk:
22436 case VPADDQZrrkz:
22437 case VPADDQrm:
22438 case VPADDQrr:
22439 return true;
22440 }
22441 return false;
22442}
22443
22444bool isPALIGNR(unsigned Opcode) {
22445 switch (Opcode) {
22446 case MMX_PALIGNRrmi:
22447 case MMX_PALIGNRrri:
22448 case PALIGNRrmi:
22449 case PALIGNRrri:
22450 return true;
22451 }
22452 return false;
22453}
22454
22455bool isPMAXUW(unsigned Opcode) {
22456 switch (Opcode) {
22457 case PMAXUWrm:
22458 case PMAXUWrr:
22459 return true;
22460 }
22461 return false;
22462}
22463
22464bool isVFMADDSD(unsigned Opcode) {
22465 switch (Opcode) {
22466 case VFMADDSD4mr:
22467 case VFMADDSD4rm:
22468 case VFMADDSD4rr:
22469 case VFMADDSD4rr_REV:
22470 return true;
22471 }
22472 return false;
22473}
22474
22475bool isPFMAX(unsigned Opcode) {
22476 switch (Opcode) {
22477 case PFMAXrm:
22478 case PFMAXrr:
22479 return true;
22480 }
22481 return false;
22482}
22483
22484bool isVPOR(unsigned Opcode) {
22485 switch (Opcode) {
22486 case VPORYrm:
22487 case VPORYrr:
22488 case VPORrm:
22489 case VPORrr:
22490 return true;
22491 }
22492 return false;
22493}
22494
22495bool isVPSUBB(unsigned Opcode) {
22496 switch (Opcode) {
22497 case VPSUBBYrm:
22498 case VPSUBBYrr:
22499 case VPSUBBZ128rm:
22500 case VPSUBBZ128rmk:
22501 case VPSUBBZ128rmkz:
22502 case VPSUBBZ128rr:
22503 case VPSUBBZ128rrk:
22504 case VPSUBBZ128rrkz:
22505 case VPSUBBZ256rm:
22506 case VPSUBBZ256rmk:
22507 case VPSUBBZ256rmkz:
22508 case VPSUBBZ256rr:
22509 case VPSUBBZ256rrk:
22510 case VPSUBBZ256rrkz:
22511 case VPSUBBZrm:
22512 case VPSUBBZrmk:
22513 case VPSUBBZrmkz:
22514 case VPSUBBZrr:
22515 case VPSUBBZrrk:
22516 case VPSUBBZrrkz:
22517 case VPSUBBrm:
22518 case VPSUBBrr:
22519 return true;
22520 }
22521 return false;
22522}
22523
22524bool isVPAVGB(unsigned Opcode) {
22525 switch (Opcode) {
22526 case VPAVGBYrm:
22527 case VPAVGBYrr:
22528 case VPAVGBZ128rm:
22529 case VPAVGBZ128rmk:
22530 case VPAVGBZ128rmkz:
22531 case VPAVGBZ128rr:
22532 case VPAVGBZ128rrk:
22533 case VPAVGBZ128rrkz:
22534 case VPAVGBZ256rm:
22535 case VPAVGBZ256rmk:
22536 case VPAVGBZ256rmkz:
22537 case VPAVGBZ256rr:
22538 case VPAVGBZ256rrk:
22539 case VPAVGBZ256rrkz:
22540 case VPAVGBZrm:
22541 case VPAVGBZrmk:
22542 case VPAVGBZrmkz:
22543 case VPAVGBZrr:
22544 case VPAVGBZrrk:
22545 case VPAVGBZrrkz:
22546 case VPAVGBrm:
22547 case VPAVGBrr:
22548 return true;
22549 }
22550 return false;
22551}
22552
22553bool isINSB(unsigned Opcode) {
22554 return Opcode == INSB;
22555}
22556
22557bool isFYL2X(unsigned Opcode) {
22558 return Opcode == FYL2X;
22559}
22560
22561bool isVFNMSUB132PD(unsigned Opcode) {
22562 switch (Opcode) {
22563 case VFNMSUB132PDYm:
22564 case VFNMSUB132PDYr:
22565 case VFNMSUB132PDZ128m:
22566 case VFNMSUB132PDZ128mb:
22567 case VFNMSUB132PDZ128mbk:
22568 case VFNMSUB132PDZ128mbkz:
22569 case VFNMSUB132PDZ128mk:
22570 case VFNMSUB132PDZ128mkz:
22571 case VFNMSUB132PDZ128r:
22572 case VFNMSUB132PDZ128rk:
22573 case VFNMSUB132PDZ128rkz:
22574 case VFNMSUB132PDZ256m:
22575 case VFNMSUB132PDZ256mb:
22576 case VFNMSUB132PDZ256mbk:
22577 case VFNMSUB132PDZ256mbkz:
22578 case VFNMSUB132PDZ256mk:
22579 case VFNMSUB132PDZ256mkz:
22580 case VFNMSUB132PDZ256r:
22581 case VFNMSUB132PDZ256rk:
22582 case VFNMSUB132PDZ256rkz:
22583 case VFNMSUB132PDZm:
22584 case VFNMSUB132PDZmb:
22585 case VFNMSUB132PDZmbk:
22586 case VFNMSUB132PDZmbkz:
22587 case VFNMSUB132PDZmk:
22588 case VFNMSUB132PDZmkz:
22589 case VFNMSUB132PDZr:
22590 case VFNMSUB132PDZrb:
22591 case VFNMSUB132PDZrbk:
22592 case VFNMSUB132PDZrbkz:
22593 case VFNMSUB132PDZrk:
22594 case VFNMSUB132PDZrkz:
22595 case VFNMSUB132PDm:
22596 case VFNMSUB132PDr:
22597 return true;
22598 }
22599 return false;
22600}
22601
22602bool isVFNMSUBPS(unsigned Opcode) {
22603 switch (Opcode) {
22604 case VFNMSUBPS4Ymr:
22605 case VFNMSUBPS4Yrm:
22606 case VFNMSUBPS4Yrr:
22607 case VFNMSUBPS4Yrr_REV:
22608 case VFNMSUBPS4mr:
22609 case VFNMSUBPS4rm:
22610 case VFNMSUBPS4rr:
22611 case VFNMSUBPS4rr_REV:
22612 return true;
22613 }
22614 return false;
22615}
22616
22617bool isVFMADD231PS(unsigned Opcode) {
22618 switch (Opcode) {
22619 case VFMADD231PSYm:
22620 case VFMADD231PSYr:
22621 case VFMADD231PSZ128m:
22622 case VFMADD231PSZ128mb:
22623 case VFMADD231PSZ128mbk:
22624 case VFMADD231PSZ128mbkz:
22625 case VFMADD231PSZ128mk:
22626 case VFMADD231PSZ128mkz:
22627 case VFMADD231PSZ128r:
22628 case VFMADD231PSZ128rk:
22629 case VFMADD231PSZ128rkz:
22630 case VFMADD231PSZ256m:
22631 case VFMADD231PSZ256mb:
22632 case VFMADD231PSZ256mbk:
22633 case VFMADD231PSZ256mbkz:
22634 case VFMADD231PSZ256mk:
22635 case VFMADD231PSZ256mkz:
22636 case VFMADD231PSZ256r:
22637 case VFMADD231PSZ256rk:
22638 case VFMADD231PSZ256rkz:
22639 case VFMADD231PSZm:
22640 case VFMADD231PSZmb:
22641 case VFMADD231PSZmbk:
22642 case VFMADD231PSZmbkz:
22643 case VFMADD231PSZmk:
22644 case VFMADD231PSZmkz:
22645 case VFMADD231PSZr:
22646 case VFMADD231PSZrb:
22647 case VFMADD231PSZrbk:
22648 case VFMADD231PSZrbkz:
22649 case VFMADD231PSZrk:
22650 case VFMADD231PSZrkz:
22651 case VFMADD231PSm:
22652 case VFMADD231PSr:
22653 return true;
22654 }
22655 return false;
22656}
22657
22658bool isVCVTTSS2SI(unsigned Opcode) {
22659 switch (Opcode) {
22660 case VCVTTSS2SI64Zrm_Int:
22661 case VCVTTSS2SI64Zrr_Int:
22662 case VCVTTSS2SI64Zrrb_Int:
22663 case VCVTTSS2SI64rm_Int:
22664 case VCVTTSS2SI64rr_Int:
22665 case VCVTTSS2SIZrm_Int:
22666 case VCVTTSS2SIZrr_Int:
22667 case VCVTTSS2SIZrrb_Int:
22668 case VCVTTSS2SIrm_Int:
22669 case VCVTTSS2SIrr_Int:
22670 return true;
22671 }
22672 return false;
22673}
22674
22675bool isTCMMRLFP16PS(unsigned Opcode) {
22676 return Opcode == TCMMRLFP16PS;
22677}
22678
22679bool isFCOMPP(unsigned Opcode) {
22680 return Opcode == FCOMPP;
22681}
22682
22683bool isMOVD(unsigned Opcode) {
22684 switch (Opcode) {
22685 case MMX_MOVD64grr:
22686 case MMX_MOVD64mr:
22687 case MMX_MOVD64rm:
22688 case MMX_MOVD64rr:
22689 case MOVDI2PDIrm:
22690 case MOVDI2PDIrr:
22691 case MOVPDI2DImr:
22692 case MOVPDI2DIrr:
22693 return true;
22694 }
22695 return false;
22696}
22697
22698bool isMOVBE(unsigned Opcode) {
22699 switch (Opcode) {
22700 case MOVBE16mr:
22701 case MOVBE16mr_EVEX:
22702 case MOVBE16rm:
22703 case MOVBE16rm_EVEX:
22704 case MOVBE16rr:
22705 case MOVBE16rr_REV:
22706 case MOVBE32mr:
22707 case MOVBE32mr_EVEX:
22708 case MOVBE32rm:
22709 case MOVBE32rm_EVEX:
22710 case MOVBE32rr:
22711 case MOVBE32rr_REV:
22712 case MOVBE64mr:
22713 case MOVBE64mr_EVEX:
22714 case MOVBE64rm:
22715 case MOVBE64rm_EVEX:
22716 case MOVBE64rr:
22717 case MOVBE64rr_REV:
22718 return true;
22719 }
22720 return false;
22721}
22722
22723bool isVP2INTERSECTD(unsigned Opcode) {
22724 switch (Opcode) {
22725 case VP2INTERSECTDZ128rm:
22726 case VP2INTERSECTDZ128rmb:
22727 case VP2INTERSECTDZ128rr:
22728 case VP2INTERSECTDZ256rm:
22729 case VP2INTERSECTDZ256rmb:
22730 case VP2INTERSECTDZ256rr:
22731 case VP2INTERSECTDZrm:
22732 case VP2INTERSECTDZrmb:
22733 case VP2INTERSECTDZrr:
22734 return true;
22735 }
22736 return false;
22737}
22738
22739bool isVPMULLQ(unsigned Opcode) {
22740 switch (Opcode) {
22741 case VPMULLQZ128rm:
22742 case VPMULLQZ128rmb:
22743 case VPMULLQZ128rmbk:
22744 case VPMULLQZ128rmbkz:
22745 case VPMULLQZ128rmk:
22746 case VPMULLQZ128rmkz:
22747 case VPMULLQZ128rr:
22748 case VPMULLQZ128rrk:
22749 case VPMULLQZ128rrkz:
22750 case VPMULLQZ256rm:
22751 case VPMULLQZ256rmb:
22752 case VPMULLQZ256rmbk:
22753 case VPMULLQZ256rmbkz:
22754 case VPMULLQZ256rmk:
22755 case VPMULLQZ256rmkz:
22756 case VPMULLQZ256rr:
22757 case VPMULLQZ256rrk:
22758 case VPMULLQZ256rrkz:
22759 case VPMULLQZrm:
22760 case VPMULLQZrmb:
22761 case VPMULLQZrmbk:
22762 case VPMULLQZrmbkz:
22763 case VPMULLQZrmk:
22764 case VPMULLQZrmkz:
22765 case VPMULLQZrr:
22766 case VPMULLQZrrk:
22767 case VPMULLQZrrkz:
22768 return true;
22769 }
22770 return false;
22771}
22772
22773bool isVSCALEFPS(unsigned Opcode) {
22774 switch (Opcode) {
22775 case VSCALEFPSZ128rm:
22776 case VSCALEFPSZ128rmb:
22777 case VSCALEFPSZ128rmbk:
22778 case VSCALEFPSZ128rmbkz:
22779 case VSCALEFPSZ128rmk:
22780 case VSCALEFPSZ128rmkz:
22781 case VSCALEFPSZ128rr:
22782 case VSCALEFPSZ128rrk:
22783 case VSCALEFPSZ128rrkz:
22784 case VSCALEFPSZ256rm:
22785 case VSCALEFPSZ256rmb:
22786 case VSCALEFPSZ256rmbk:
22787 case VSCALEFPSZ256rmbkz:
22788 case VSCALEFPSZ256rmk:
22789 case VSCALEFPSZ256rmkz:
22790 case VSCALEFPSZ256rr:
22791 case VSCALEFPSZ256rrk:
22792 case VSCALEFPSZ256rrkz:
22793 case VSCALEFPSZrm:
22794 case VSCALEFPSZrmb:
22795 case VSCALEFPSZrmbk:
22796 case VSCALEFPSZrmbkz:
22797 case VSCALEFPSZrmk:
22798 case VSCALEFPSZrmkz:
22799 case VSCALEFPSZrr:
22800 case VSCALEFPSZrrb:
22801 case VSCALEFPSZrrbk:
22802 case VSCALEFPSZrrbkz:
22803 case VSCALEFPSZrrk:
22804 case VSCALEFPSZrrkz:
22805 return true;
22806 }
22807 return false;
22808}
22809
22810bool isVPMACSDQH(unsigned Opcode) {
22811 switch (Opcode) {
22812 case VPMACSDQHrm:
22813 case VPMACSDQHrr:
22814 return true;
22815 }
22816 return false;
22817}
22818
22819bool isVPTESTNMD(unsigned Opcode) {
22820 switch (Opcode) {
22821 case VPTESTNMDZ128rm:
22822 case VPTESTNMDZ128rmb:
22823 case VPTESTNMDZ128rmbk:
22824 case VPTESTNMDZ128rmk:
22825 case VPTESTNMDZ128rr:
22826 case VPTESTNMDZ128rrk:
22827 case VPTESTNMDZ256rm:
22828 case VPTESTNMDZ256rmb:
22829 case VPTESTNMDZ256rmbk:
22830 case VPTESTNMDZ256rmk:
22831 case VPTESTNMDZ256rr:
22832 case VPTESTNMDZ256rrk:
22833 case VPTESTNMDZrm:
22834 case VPTESTNMDZrmb:
22835 case VPTESTNMDZrmbk:
22836 case VPTESTNMDZrmk:
22837 case VPTESTNMDZrr:
22838 case VPTESTNMDZrrk:
22839 return true;
22840 }
22841 return false;
22842}
22843
22844bool isFCOMP(unsigned Opcode) {
22845 switch (Opcode) {
22846 case COMP_FST0r:
22847 case FCOMP32m:
22848 case FCOMP64m:
22849 return true;
22850 }
22851 return false;
22852}
22853
22854bool isPREFETCHWT1(unsigned Opcode) {
22855 return Opcode == PREFETCHWT1;
22856}
22857
22858bool isVCMPSD(unsigned Opcode) {
22859 switch (Opcode) {
22860 case VCMPSDZrmi_Int:
22861 case VCMPSDZrmik_Int:
22862 case VCMPSDZrri_Int:
22863 case VCMPSDZrrib_Int:
22864 case VCMPSDZrribk_Int:
22865 case VCMPSDZrrik_Int:
22866 case VCMPSDrmi_Int:
22867 case VCMPSDrri_Int:
22868 return true;
22869 }
22870 return false;
22871}
22872
22873bool isSGDTD(unsigned Opcode) {
22874 return Opcode == SGDT32m;
22875}
22876
22877bool isWRUSSD(unsigned Opcode) {
22878 switch (Opcode) {
22879 case WRUSSD:
22880 case WRUSSD_EVEX:
22881 return true;
22882 }
22883 return false;
22884}
22885
22886bool isFSUBP(unsigned Opcode) {
22887 return Opcode == SUB_FPrST0;
22888}
22889
22890bool isVUNPCKLPS(unsigned Opcode) {
22891 switch (Opcode) {
22892 case VUNPCKLPSYrm:
22893 case VUNPCKLPSYrr:
22894 case VUNPCKLPSZ128rm:
22895 case VUNPCKLPSZ128rmb:
22896 case VUNPCKLPSZ128rmbk:
22897 case VUNPCKLPSZ128rmbkz:
22898 case VUNPCKLPSZ128rmk:
22899 case VUNPCKLPSZ128rmkz:
22900 case VUNPCKLPSZ128rr:
22901 case VUNPCKLPSZ128rrk:
22902 case VUNPCKLPSZ128rrkz:
22903 case VUNPCKLPSZ256rm:
22904 case VUNPCKLPSZ256rmb:
22905 case VUNPCKLPSZ256rmbk:
22906 case VUNPCKLPSZ256rmbkz:
22907 case VUNPCKLPSZ256rmk:
22908 case VUNPCKLPSZ256rmkz:
22909 case VUNPCKLPSZ256rr:
22910 case VUNPCKLPSZ256rrk:
22911 case VUNPCKLPSZ256rrkz:
22912 case VUNPCKLPSZrm:
22913 case VUNPCKLPSZrmb:
22914 case VUNPCKLPSZrmbk:
22915 case VUNPCKLPSZrmbkz:
22916 case VUNPCKLPSZrmk:
22917 case VUNPCKLPSZrmkz:
22918 case VUNPCKLPSZrr:
22919 case VUNPCKLPSZrrk:
22920 case VUNPCKLPSZrrkz:
22921 case VUNPCKLPSrm:
22922 case VUNPCKLPSrr:
22923 return true;
22924 }
22925 return false;
22926}
22927
22928bool isVFNMSUB213SS(unsigned Opcode) {
22929 switch (Opcode) {
22930 case VFNMSUB213SSZm_Int:
22931 case VFNMSUB213SSZmk_Int:
22932 case VFNMSUB213SSZmkz_Int:
22933 case VFNMSUB213SSZr_Int:
22934 case VFNMSUB213SSZrb_Int:
22935 case VFNMSUB213SSZrbk_Int:
22936 case VFNMSUB213SSZrbkz_Int:
22937 case VFNMSUB213SSZrk_Int:
22938 case VFNMSUB213SSZrkz_Int:
22939 case VFNMSUB213SSm_Int:
22940 case VFNMSUB213SSr_Int:
22941 return true;
22942 }
22943 return false;
22944}
22945
22946bool isROUNDPD(unsigned Opcode) {
22947 switch (Opcode) {
22948 case ROUNDPDmi:
22949 case ROUNDPDri:
22950 return true;
22951 }
22952 return false;
22953}
22954
22955bool isVPMAXSW(unsigned Opcode) {
22956 switch (Opcode) {
22957 case VPMAXSWYrm:
22958 case VPMAXSWYrr:
22959 case VPMAXSWZ128rm:
22960 case VPMAXSWZ128rmk:
22961 case VPMAXSWZ128rmkz:
22962 case VPMAXSWZ128rr:
22963 case VPMAXSWZ128rrk:
22964 case VPMAXSWZ128rrkz:
22965 case VPMAXSWZ256rm:
22966 case VPMAXSWZ256rmk:
22967 case VPMAXSWZ256rmkz:
22968 case VPMAXSWZ256rr:
22969 case VPMAXSWZ256rrk:
22970 case VPMAXSWZ256rrkz:
22971 case VPMAXSWZrm:
22972 case VPMAXSWZrmk:
22973 case VPMAXSWZrmkz:
22974 case VPMAXSWZrr:
22975 case VPMAXSWZrrk:
22976 case VPMAXSWZrrkz:
22977 case VPMAXSWrm:
22978 case VPMAXSWrr:
22979 return true;
22980 }
22981 return false;
22982}
22983
22984bool isVCVTTPH2DQ(unsigned Opcode) {
22985 switch (Opcode) {
22986 case VCVTTPH2DQZ128rm:
22987 case VCVTTPH2DQZ128rmb:
22988 case VCVTTPH2DQZ128rmbk:
22989 case VCVTTPH2DQZ128rmbkz:
22990 case VCVTTPH2DQZ128rmk:
22991 case VCVTTPH2DQZ128rmkz:
22992 case VCVTTPH2DQZ128rr:
22993 case VCVTTPH2DQZ128rrk:
22994 case VCVTTPH2DQZ128rrkz:
22995 case VCVTTPH2DQZ256rm:
22996 case VCVTTPH2DQZ256rmb:
22997 case VCVTTPH2DQZ256rmbk:
22998 case VCVTTPH2DQZ256rmbkz:
22999 case VCVTTPH2DQZ256rmk:
23000 case VCVTTPH2DQZ256rmkz:
23001 case VCVTTPH2DQZ256rr:
23002 case VCVTTPH2DQZ256rrk:
23003 case VCVTTPH2DQZ256rrkz:
23004 case VCVTTPH2DQZrm:
23005 case VCVTTPH2DQZrmb:
23006 case VCVTTPH2DQZrmbk:
23007 case VCVTTPH2DQZrmbkz:
23008 case VCVTTPH2DQZrmk:
23009 case VCVTTPH2DQZrmkz:
23010 case VCVTTPH2DQZrr:
23011 case VCVTTPH2DQZrrb:
23012 case VCVTTPH2DQZrrbk:
23013 case VCVTTPH2DQZrrbkz:
23014 case VCVTTPH2DQZrrk:
23015 case VCVTTPH2DQZrrkz:
23016 return true;
23017 }
23018 return false;
23019}
23020
23021bool isVPUNPCKLWD(unsigned Opcode) {
23022 switch (Opcode) {
23023 case VPUNPCKLWDYrm:
23024 case VPUNPCKLWDYrr:
23025 case VPUNPCKLWDZ128rm:
23026 case VPUNPCKLWDZ128rmk:
23027 case VPUNPCKLWDZ128rmkz:
23028 case VPUNPCKLWDZ128rr:
23029 case VPUNPCKLWDZ128rrk:
23030 case VPUNPCKLWDZ128rrkz:
23031 case VPUNPCKLWDZ256rm:
23032 case VPUNPCKLWDZ256rmk:
23033 case VPUNPCKLWDZ256rmkz:
23034 case VPUNPCKLWDZ256rr:
23035 case VPUNPCKLWDZ256rrk:
23036 case VPUNPCKLWDZ256rrkz:
23037 case VPUNPCKLWDZrm:
23038 case VPUNPCKLWDZrmk:
23039 case VPUNPCKLWDZrmkz:
23040 case VPUNPCKLWDZrr:
23041 case VPUNPCKLWDZrrk:
23042 case VPUNPCKLWDZrrkz:
23043 case VPUNPCKLWDrm:
23044 case VPUNPCKLWDrr:
23045 return true;
23046 }
23047 return false;
23048}
23049
23050bool isKSHIFTLD(unsigned Opcode) {
23051 return Opcode == KSHIFTLDki;
23052}
23053
23054bool isTCVTROWPS2BF16H(unsigned Opcode) {
23055 switch (Opcode) {
23056 case TCVTROWPS2BF16Hrte:
23057 case TCVTROWPS2BF16Hrti:
23058 return true;
23059 }
23060 return false;
23061}
23062
23063bool isVFMADD231SD(unsigned Opcode) {
23064 switch (Opcode) {
23065 case VFMADD231SDZm_Int:
23066 case VFMADD231SDZmk_Int:
23067 case VFMADD231SDZmkz_Int:
23068 case VFMADD231SDZr_Int:
23069 case VFMADD231SDZrb_Int:
23070 case VFMADD231SDZrbk_Int:
23071 case VFMADD231SDZrbkz_Int:
23072 case VFMADD231SDZrk_Int:
23073 case VFMADD231SDZrkz_Int:
23074 case VFMADD231SDm_Int:
23075 case VFMADD231SDr_Int:
23076 return true;
23077 }
23078 return false;
23079}
23080
23081bool isADDPS(unsigned Opcode) {
23082 switch (Opcode) {
23083 case ADDPSrm:
23084 case ADDPSrr:
23085 return true;
23086 }
23087 return false;
23088}
23089
23090bool isVPSLLVD(unsigned Opcode) {
23091 switch (Opcode) {
23092 case VPSLLVDYrm:
23093 case VPSLLVDYrr:
23094 case VPSLLVDZ128rm:
23095 case VPSLLVDZ128rmb:
23096 case VPSLLVDZ128rmbk:
23097 case VPSLLVDZ128rmbkz:
23098 case VPSLLVDZ128rmk:
23099 case VPSLLVDZ128rmkz:
23100 case VPSLLVDZ128rr:
23101 case VPSLLVDZ128rrk:
23102 case VPSLLVDZ128rrkz:
23103 case VPSLLVDZ256rm:
23104 case VPSLLVDZ256rmb:
23105 case VPSLLVDZ256rmbk:
23106 case VPSLLVDZ256rmbkz:
23107 case VPSLLVDZ256rmk:
23108 case VPSLLVDZ256rmkz:
23109 case VPSLLVDZ256rr:
23110 case VPSLLVDZ256rrk:
23111 case VPSLLVDZ256rrkz:
23112 case VPSLLVDZrm:
23113 case VPSLLVDZrmb:
23114 case VPSLLVDZrmbk:
23115 case VPSLLVDZrmbkz:
23116 case VPSLLVDZrmk:
23117 case VPSLLVDZrmkz:
23118 case VPSLLVDZrr:
23119 case VPSLLVDZrrk:
23120 case VPSLLVDZrrkz:
23121 case VPSLLVDrm:
23122 case VPSLLVDrr:
23123 return true;
23124 }
23125 return false;
23126}
23127
23128bool isVFNMADD132SH(unsigned Opcode) {
23129 switch (Opcode) {
23130 case VFNMADD132SHZm_Int:
23131 case VFNMADD132SHZmk_Int:
23132 case VFNMADD132SHZmkz_Int:
23133 case VFNMADD132SHZr_Int:
23134 case VFNMADD132SHZrb_Int:
23135 case VFNMADD132SHZrbk_Int:
23136 case VFNMADD132SHZrbkz_Int:
23137 case VFNMADD132SHZrk_Int:
23138 case VFNMADD132SHZrkz_Int:
23139 return true;
23140 }
23141 return false;
23142}
23143
23144bool isVMOVNTPS(unsigned Opcode) {
23145 switch (Opcode) {
23146 case VMOVNTPSYmr:
23147 case VMOVNTPSZ128mr:
23148 case VMOVNTPSZ256mr:
23149 case VMOVNTPSZmr:
23150 case VMOVNTPSmr:
23151 return true;
23152 }
23153 return false;
23154}
23155
23156bool isVCVTPD2DQ(unsigned Opcode) {
23157 switch (Opcode) {
23158 case VCVTPD2DQYrm:
23159 case VCVTPD2DQYrr:
23160 case VCVTPD2DQZ128rm:
23161 case VCVTPD2DQZ128rmb:
23162 case VCVTPD2DQZ128rmbk:
23163 case VCVTPD2DQZ128rmbkz:
23164 case VCVTPD2DQZ128rmk:
23165 case VCVTPD2DQZ128rmkz:
23166 case VCVTPD2DQZ128rr:
23167 case VCVTPD2DQZ128rrk:
23168 case VCVTPD2DQZ128rrkz:
23169 case VCVTPD2DQZ256rm:
23170 case VCVTPD2DQZ256rmb:
23171 case VCVTPD2DQZ256rmbk:
23172 case VCVTPD2DQZ256rmbkz:
23173 case VCVTPD2DQZ256rmk:
23174 case VCVTPD2DQZ256rmkz:
23175 case VCVTPD2DQZ256rr:
23176 case VCVTPD2DQZ256rrk:
23177 case VCVTPD2DQZ256rrkz:
23178 case VCVTPD2DQZrm:
23179 case VCVTPD2DQZrmb:
23180 case VCVTPD2DQZrmbk:
23181 case VCVTPD2DQZrmbkz:
23182 case VCVTPD2DQZrmk:
23183 case VCVTPD2DQZrmkz:
23184 case VCVTPD2DQZrr:
23185 case VCVTPD2DQZrrb:
23186 case VCVTPD2DQZrrbk:
23187 case VCVTPD2DQZrrbkz:
23188 case VCVTPD2DQZrrk:
23189 case VCVTPD2DQZrrkz:
23190 case VCVTPD2DQrm:
23191 case VCVTPD2DQrr:
23192 return true;
23193 }
23194 return false;
23195}
23196
23197bool isVPXOR(unsigned Opcode) {
23198 switch (Opcode) {
23199 case VPXORYrm:
23200 case VPXORYrr:
23201 case VPXORrm:
23202 case VPXORrr:
23203 return true;
23204 }
23205 return false;
23206}
23207
23208bool isSTMXCSR(unsigned Opcode) {
23209 return Opcode == STMXCSR;
23210}
23211
23212bool isVRCP14SS(unsigned Opcode) {
23213 switch (Opcode) {
23214 case VRCP14SSZrm:
23215 case VRCP14SSZrmk:
23216 case VRCP14SSZrmkz:
23217 case VRCP14SSZrr:
23218 case VRCP14SSZrrk:
23219 case VRCP14SSZrrkz:
23220 return true;
23221 }
23222 return false;
23223}
23224
23225bool isUD2(unsigned Opcode) {
23226 return Opcode == TRAP;
23227}
23228
23229bool isVPOPCNTW(unsigned Opcode) {
23230 switch (Opcode) {
23231 case VPOPCNTWZ128rm:
23232 case VPOPCNTWZ128rmk:
23233 case VPOPCNTWZ128rmkz:
23234 case VPOPCNTWZ128rr:
23235 case VPOPCNTWZ128rrk:
23236 case VPOPCNTWZ128rrkz:
23237 case VPOPCNTWZ256rm:
23238 case VPOPCNTWZ256rmk:
23239 case VPOPCNTWZ256rmkz:
23240 case VPOPCNTWZ256rr:
23241 case VPOPCNTWZ256rrk:
23242 case VPOPCNTWZ256rrkz:
23243 case VPOPCNTWZrm:
23244 case VPOPCNTWZrmk:
23245 case VPOPCNTWZrmkz:
23246 case VPOPCNTWZrr:
23247 case VPOPCNTWZrrk:
23248 case VPOPCNTWZrrkz:
23249 return true;
23250 }
23251 return false;
23252}
23253
23254bool isVRSQRTSH(unsigned Opcode) {
23255 switch (Opcode) {
23256 case VRSQRTSHZrm:
23257 case VRSQRTSHZrmk:
23258 case VRSQRTSHZrmkz:
23259 case VRSQRTSHZrr:
23260 case VRSQRTSHZrrk:
23261 case VRSQRTSHZrrkz:
23262 return true;
23263 }
23264 return false;
23265}
23266
23267bool isVSCATTERPF0DPD(unsigned Opcode) {
23268 return Opcode == VSCATTERPF0DPDm;
23269}
23270
23271bool isVFMADDPS(unsigned Opcode) {
23272 switch (Opcode) {
23273 case VFMADDPS4Ymr:
23274 case VFMADDPS4Yrm:
23275 case VFMADDPS4Yrr:
23276 case VFMADDPS4Yrr_REV:
23277 case VFMADDPS4mr:
23278 case VFMADDPS4rm:
23279 case VFMADDPS4rr:
23280 case VFMADDPS4rr_REV:
23281 return true;
23282 }
23283 return false;
23284}
23285
23286bool isXSAVEC64(unsigned Opcode) {
23287 return Opcode == XSAVEC64;
23288}
23289
23290bool isVPMADDUBSW(unsigned Opcode) {
23291 switch (Opcode) {
23292 case VPMADDUBSWYrm:
23293 case VPMADDUBSWYrr:
23294 case VPMADDUBSWZ128rm:
23295 case VPMADDUBSWZ128rmk:
23296 case VPMADDUBSWZ128rmkz:
23297 case VPMADDUBSWZ128rr:
23298 case VPMADDUBSWZ128rrk:
23299 case VPMADDUBSWZ128rrkz:
23300 case VPMADDUBSWZ256rm:
23301 case VPMADDUBSWZ256rmk:
23302 case VPMADDUBSWZ256rmkz:
23303 case VPMADDUBSWZ256rr:
23304 case VPMADDUBSWZ256rrk:
23305 case VPMADDUBSWZ256rrkz:
23306 case VPMADDUBSWZrm:
23307 case VPMADDUBSWZrmk:
23308 case VPMADDUBSWZrmkz:
23309 case VPMADDUBSWZrr:
23310 case VPMADDUBSWZrrk:
23311 case VPMADDUBSWZrrkz:
23312 case VPMADDUBSWrm:
23313 case VPMADDUBSWrr:
23314 return true;
23315 }
23316 return false;
23317}
23318
23319bool isVPMOVZXDQ(unsigned Opcode) {
23320 switch (Opcode) {
23321 case VPMOVZXDQYrm:
23322 case VPMOVZXDQYrr:
23323 case VPMOVZXDQZ128rm:
23324 case VPMOVZXDQZ128rmk:
23325 case VPMOVZXDQZ128rmkz:
23326 case VPMOVZXDQZ128rr:
23327 case VPMOVZXDQZ128rrk:
23328 case VPMOVZXDQZ128rrkz:
23329 case VPMOVZXDQZ256rm:
23330 case VPMOVZXDQZ256rmk:
23331 case VPMOVZXDQZ256rmkz:
23332 case VPMOVZXDQZ256rr:
23333 case VPMOVZXDQZ256rrk:
23334 case VPMOVZXDQZ256rrkz:
23335 case VPMOVZXDQZrm:
23336 case VPMOVZXDQZrmk:
23337 case VPMOVZXDQZrmkz:
23338 case VPMOVZXDQZrr:
23339 case VPMOVZXDQZrrk:
23340 case VPMOVZXDQZrrkz:
23341 case VPMOVZXDQrm:
23342 case VPMOVZXDQrr:
23343 return true;
23344 }
23345 return false;
23346}
23347
23348bool isVRCP14PS(unsigned Opcode) {
23349 switch (Opcode) {
23350 case VRCP14PSZ128m:
23351 case VRCP14PSZ128mb:
23352 case VRCP14PSZ128mbk:
23353 case VRCP14PSZ128mbkz:
23354 case VRCP14PSZ128mk:
23355 case VRCP14PSZ128mkz:
23356 case VRCP14PSZ128r:
23357 case VRCP14PSZ128rk:
23358 case VRCP14PSZ128rkz:
23359 case VRCP14PSZ256m:
23360 case VRCP14PSZ256mb:
23361 case VRCP14PSZ256mbk:
23362 case VRCP14PSZ256mbkz:
23363 case VRCP14PSZ256mk:
23364 case VRCP14PSZ256mkz:
23365 case VRCP14PSZ256r:
23366 case VRCP14PSZ256rk:
23367 case VRCP14PSZ256rkz:
23368 case VRCP14PSZm:
23369 case VRCP14PSZmb:
23370 case VRCP14PSZmbk:
23371 case VRCP14PSZmbkz:
23372 case VRCP14PSZmk:
23373 case VRCP14PSZmkz:
23374 case VRCP14PSZr:
23375 case VRCP14PSZrk:
23376 case VRCP14PSZrkz:
23377 return true;
23378 }
23379 return false;
23380}
23381
23382bool isVSQRTSH(unsigned Opcode) {
23383 switch (Opcode) {
23384 case VSQRTSHZm_Int:
23385 case VSQRTSHZmk_Int:
23386 case VSQRTSHZmkz_Int:
23387 case VSQRTSHZr_Int:
23388 case VSQRTSHZrb_Int:
23389 case VSQRTSHZrbk_Int:
23390 case VSQRTSHZrbkz_Int:
23391 case VSQRTSHZrk_Int:
23392 case VSQRTSHZrkz_Int:
23393 return true;
23394 }
23395 return false;
23396}
23397
23398bool isTCVTROWD2PS(unsigned Opcode) {
23399 switch (Opcode) {
23400 case TCVTROWD2PSrte:
23401 case TCVTROWD2PSrti:
23402 return true;
23403 }
23404 return false;
23405}
23406
23407bool isLOOP(unsigned Opcode) {
23408 return Opcode == LOOP;
23409}
23410
23411bool isSTUI(unsigned Opcode) {
23412 return Opcode == STUI;
23413}
23414
23415bool isVCVTTPS2UDQ(unsigned Opcode) {
23416 switch (Opcode) {
23417 case VCVTTPS2UDQZ128rm:
23418 case VCVTTPS2UDQZ128rmb:
23419 case VCVTTPS2UDQZ128rmbk:
23420 case VCVTTPS2UDQZ128rmbkz:
23421 case VCVTTPS2UDQZ128rmk:
23422 case VCVTTPS2UDQZ128rmkz:
23423 case VCVTTPS2UDQZ128rr:
23424 case VCVTTPS2UDQZ128rrk:
23425 case VCVTTPS2UDQZ128rrkz:
23426 case VCVTTPS2UDQZ256rm:
23427 case VCVTTPS2UDQZ256rmb:
23428 case VCVTTPS2UDQZ256rmbk:
23429 case VCVTTPS2UDQZ256rmbkz:
23430 case VCVTTPS2UDQZ256rmk:
23431 case VCVTTPS2UDQZ256rmkz:
23432 case VCVTTPS2UDQZ256rr:
23433 case VCVTTPS2UDQZ256rrk:
23434 case VCVTTPS2UDQZ256rrkz:
23435 case VCVTTPS2UDQZrm:
23436 case VCVTTPS2UDQZrmb:
23437 case VCVTTPS2UDQZrmbk:
23438 case VCVTTPS2UDQZrmbkz:
23439 case VCVTTPS2UDQZrmk:
23440 case VCVTTPS2UDQZrmkz:
23441 case VCVTTPS2UDQZrr:
23442 case VCVTTPS2UDQZrrb:
23443 case VCVTTPS2UDQZrrbk:
23444 case VCVTTPS2UDQZrrbkz:
23445 case VCVTTPS2UDQZrrk:
23446 case VCVTTPS2UDQZrrkz:
23447 return true;
23448 }
23449 return false;
23450}
23451
23452bool isVCOMPRESSPS(unsigned Opcode) {
23453 switch (Opcode) {
23454 case VCOMPRESSPSZ128mr:
23455 case VCOMPRESSPSZ128mrk:
23456 case VCOMPRESSPSZ128rr:
23457 case VCOMPRESSPSZ128rrk:
23458 case VCOMPRESSPSZ128rrkz:
23459 case VCOMPRESSPSZ256mr:
23460 case VCOMPRESSPSZ256mrk:
23461 case VCOMPRESSPSZ256rr:
23462 case VCOMPRESSPSZ256rrk:
23463 case VCOMPRESSPSZ256rrkz:
23464 case VCOMPRESSPSZmr:
23465 case VCOMPRESSPSZmrk:
23466 case VCOMPRESSPSZrr:
23467 case VCOMPRESSPSZrrk:
23468 case VCOMPRESSPSZrrkz:
23469 return true;
23470 }
23471 return false;
23472}
23473
23474bool isXABORT(unsigned Opcode) {
23475 return Opcode == XABORT;
23476}
23477
23478bool isVCVTTBF162IUBS(unsigned Opcode) {
23479 switch (Opcode) {
23480 case VCVTTBF162IUBSZ128rm:
23481 case VCVTTBF162IUBSZ128rmb:
23482 case VCVTTBF162IUBSZ128rmbk:
23483 case VCVTTBF162IUBSZ128rmbkz:
23484 case VCVTTBF162IUBSZ128rmk:
23485 case VCVTTBF162IUBSZ128rmkz:
23486 case VCVTTBF162IUBSZ128rr:
23487 case VCVTTBF162IUBSZ128rrk:
23488 case VCVTTBF162IUBSZ128rrkz:
23489 case VCVTTBF162IUBSZ256rm:
23490 case VCVTTBF162IUBSZ256rmb:
23491 case VCVTTBF162IUBSZ256rmbk:
23492 case VCVTTBF162IUBSZ256rmbkz:
23493 case VCVTTBF162IUBSZ256rmk:
23494 case VCVTTBF162IUBSZ256rmkz:
23495 case VCVTTBF162IUBSZ256rr:
23496 case VCVTTBF162IUBSZ256rrk:
23497 case VCVTTBF162IUBSZ256rrkz:
23498 case VCVTTBF162IUBSZrm:
23499 case VCVTTBF162IUBSZrmb:
23500 case VCVTTBF162IUBSZrmbk:
23501 case VCVTTBF162IUBSZrmbkz:
23502 case VCVTTBF162IUBSZrmk:
23503 case VCVTTBF162IUBSZrmkz:
23504 case VCVTTBF162IUBSZrr:
23505 case VCVTTBF162IUBSZrrk:
23506 case VCVTTBF162IUBSZrrkz:
23507 return true;
23508 }
23509 return false;
23510}
23511
23512bool isVPADDW(unsigned Opcode) {
23513 switch (Opcode) {
23514 case VPADDWYrm:
23515 case VPADDWYrr:
23516 case VPADDWZ128rm:
23517 case VPADDWZ128rmk:
23518 case VPADDWZ128rmkz:
23519 case VPADDWZ128rr:
23520 case VPADDWZ128rrk:
23521 case VPADDWZ128rrkz:
23522 case VPADDWZ256rm:
23523 case VPADDWZ256rmk:
23524 case VPADDWZ256rmkz:
23525 case VPADDWZ256rr:
23526 case VPADDWZ256rrk:
23527 case VPADDWZ256rrkz:
23528 case VPADDWZrm:
23529 case VPADDWZrmk:
23530 case VPADDWZrmkz:
23531 case VPADDWZrr:
23532 case VPADDWZrrk:
23533 case VPADDWZrrkz:
23534 case VPADDWrm:
23535 case VPADDWrr:
23536 return true;
23537 }
23538 return false;
23539}
23540
23541bool isVRNDSCALEPS(unsigned Opcode) {
23542 switch (Opcode) {
23543 case VRNDSCALEPSZ128rmbi:
23544 case VRNDSCALEPSZ128rmbik:
23545 case VRNDSCALEPSZ128rmbikz:
23546 case VRNDSCALEPSZ128rmi:
23547 case VRNDSCALEPSZ128rmik:
23548 case VRNDSCALEPSZ128rmikz:
23549 case VRNDSCALEPSZ128rri:
23550 case VRNDSCALEPSZ128rrik:
23551 case VRNDSCALEPSZ128rrikz:
23552 case VRNDSCALEPSZ256rmbi:
23553 case VRNDSCALEPSZ256rmbik:
23554 case VRNDSCALEPSZ256rmbikz:
23555 case VRNDSCALEPSZ256rmi:
23556 case VRNDSCALEPSZ256rmik:
23557 case VRNDSCALEPSZ256rmikz:
23558 case VRNDSCALEPSZ256rri:
23559 case VRNDSCALEPSZ256rrik:
23560 case VRNDSCALEPSZ256rrikz:
23561 case VRNDSCALEPSZrmbi:
23562 case VRNDSCALEPSZrmbik:
23563 case VRNDSCALEPSZrmbikz:
23564 case VRNDSCALEPSZrmi:
23565 case VRNDSCALEPSZrmik:
23566 case VRNDSCALEPSZrmikz:
23567 case VRNDSCALEPSZrri:
23568 case VRNDSCALEPSZrrib:
23569 case VRNDSCALEPSZrribk:
23570 case VRNDSCALEPSZrribkz:
23571 case VRNDSCALEPSZrrik:
23572 case VRNDSCALEPSZrrikz:
23573 return true;
23574 }
23575 return false;
23576}
23577
23578bool isVPSIGND(unsigned Opcode) {
23579 switch (Opcode) {
23580 case VPSIGNDYrm:
23581 case VPSIGNDYrr:
23582 case VPSIGNDrm:
23583 case VPSIGNDrr:
23584 return true;
23585 }
23586 return false;
23587}
23588
23589bool isVPHADDUWD(unsigned Opcode) {
23590 switch (Opcode) {
23591 case VPHADDUWDrm:
23592 case VPHADDUWDrr:
23593 return true;
23594 }
23595 return false;
23596}
23597
23598bool isVCVT2PH2HF8S(unsigned Opcode) {
23599 switch (Opcode) {
23600 case VCVT2PH2HF8SZ128rm:
23601 case VCVT2PH2HF8SZ128rmb:
23602 case VCVT2PH2HF8SZ128rmbk:
23603 case VCVT2PH2HF8SZ128rmbkz:
23604 case VCVT2PH2HF8SZ128rmk:
23605 case VCVT2PH2HF8SZ128rmkz:
23606 case VCVT2PH2HF8SZ128rr:
23607 case VCVT2PH2HF8SZ128rrk:
23608 case VCVT2PH2HF8SZ128rrkz:
23609 case VCVT2PH2HF8SZ256rm:
23610 case VCVT2PH2HF8SZ256rmb:
23611 case VCVT2PH2HF8SZ256rmbk:
23612 case VCVT2PH2HF8SZ256rmbkz:
23613 case VCVT2PH2HF8SZ256rmk:
23614 case VCVT2PH2HF8SZ256rmkz:
23615 case VCVT2PH2HF8SZ256rr:
23616 case VCVT2PH2HF8SZ256rrk:
23617 case VCVT2PH2HF8SZ256rrkz:
23618 case VCVT2PH2HF8SZrm:
23619 case VCVT2PH2HF8SZrmb:
23620 case VCVT2PH2HF8SZrmbk:
23621 case VCVT2PH2HF8SZrmbkz:
23622 case VCVT2PH2HF8SZrmk:
23623 case VCVT2PH2HF8SZrmkz:
23624 case VCVT2PH2HF8SZrr:
23625 case VCVT2PH2HF8SZrrk:
23626 case VCVT2PH2HF8SZrrkz:
23627 return true;
23628 }
23629 return false;
23630}
23631
23632bool isVDBPSADBW(unsigned Opcode) {
23633 switch (Opcode) {
23634 case VDBPSADBWZ128rmi:
23635 case VDBPSADBWZ128rmik:
23636 case VDBPSADBWZ128rmikz:
23637 case VDBPSADBWZ128rri:
23638 case VDBPSADBWZ128rrik:
23639 case VDBPSADBWZ128rrikz:
23640 case VDBPSADBWZ256rmi:
23641 case VDBPSADBWZ256rmik:
23642 case VDBPSADBWZ256rmikz:
23643 case VDBPSADBWZ256rri:
23644 case VDBPSADBWZ256rrik:
23645 case VDBPSADBWZ256rrikz:
23646 case VDBPSADBWZrmi:
23647 case VDBPSADBWZrmik:
23648 case VDBPSADBWZrmikz:
23649 case VDBPSADBWZrri:
23650 case VDBPSADBWZrrik:
23651 case VDBPSADBWZrrikz:
23652 return true;
23653 }
23654 return false;
23655}
23656
23657bool isPSLLW(unsigned Opcode) {
23658 switch (Opcode) {
23659 case MMX_PSLLWri:
23660 case MMX_PSLLWrm:
23661 case MMX_PSLLWrr:
23662 case PSLLWri:
23663 case PSLLWrm:
23664 case PSLLWrr:
23665 return true;
23666 }
23667 return false;
23668}
23669
23670bool isVPMOVQD(unsigned Opcode) {
23671 switch (Opcode) {
23672 case VPMOVQDZ128mr:
23673 case VPMOVQDZ128mrk:
23674 case VPMOVQDZ128rr:
23675 case VPMOVQDZ128rrk:
23676 case VPMOVQDZ128rrkz:
23677 case VPMOVQDZ256mr:
23678 case VPMOVQDZ256mrk:
23679 case VPMOVQDZ256rr:
23680 case VPMOVQDZ256rrk:
23681 case VPMOVQDZ256rrkz:
23682 case VPMOVQDZmr:
23683 case VPMOVQDZmrk:
23684 case VPMOVQDZrr:
23685 case VPMOVQDZrrk:
23686 case VPMOVQDZrrkz:
23687 return true;
23688 }
23689 return false;
23690}
23691
23692bool isVINSERTI64X4(unsigned Opcode) {
23693 switch (Opcode) {
23694 case VINSERTI64X4Zrmi:
23695 case VINSERTI64X4Zrmik:
23696 case VINSERTI64X4Zrmikz:
23697 case VINSERTI64X4Zrri:
23698 case VINSERTI64X4Zrrik:
23699 case VINSERTI64X4Zrrikz:
23700 return true;
23701 }
23702 return false;
23703}
23704
23705bool isVPERMI2PS(unsigned Opcode) {
23706 switch (Opcode) {
23707 case VPERMI2PSZ128rm:
23708 case VPERMI2PSZ128rmb:
23709 case VPERMI2PSZ128rmbk:
23710 case VPERMI2PSZ128rmbkz:
23711 case VPERMI2PSZ128rmk:
23712 case VPERMI2PSZ128rmkz:
23713 case VPERMI2PSZ128rr:
23714 case VPERMI2PSZ128rrk:
23715 case VPERMI2PSZ128rrkz:
23716 case VPERMI2PSZ256rm:
23717 case VPERMI2PSZ256rmb:
23718 case VPERMI2PSZ256rmbk:
23719 case VPERMI2PSZ256rmbkz:
23720 case VPERMI2PSZ256rmk:
23721 case VPERMI2PSZ256rmkz:
23722 case VPERMI2PSZ256rr:
23723 case VPERMI2PSZ256rrk:
23724 case VPERMI2PSZ256rrkz:
23725 case VPERMI2PSZrm:
23726 case VPERMI2PSZrmb:
23727 case VPERMI2PSZrmbk:
23728 case VPERMI2PSZrmbkz:
23729 case VPERMI2PSZrmk:
23730 case VPERMI2PSZrmkz:
23731 case VPERMI2PSZrr:
23732 case VPERMI2PSZrrk:
23733 case VPERMI2PSZrrkz:
23734 return true;
23735 }
23736 return false;
23737}
23738
23739bool isVMULPH(unsigned Opcode) {
23740 switch (Opcode) {
23741 case VMULPHZ128rm:
23742 case VMULPHZ128rmb:
23743 case VMULPHZ128rmbk:
23744 case VMULPHZ128rmbkz:
23745 case VMULPHZ128rmk:
23746 case VMULPHZ128rmkz:
23747 case VMULPHZ128rr:
23748 case VMULPHZ128rrk:
23749 case VMULPHZ128rrkz:
23750 case VMULPHZ256rm:
23751 case VMULPHZ256rmb:
23752 case VMULPHZ256rmbk:
23753 case VMULPHZ256rmbkz:
23754 case VMULPHZ256rmk:
23755 case VMULPHZ256rmkz:
23756 case VMULPHZ256rr:
23757 case VMULPHZ256rrk:
23758 case VMULPHZ256rrkz:
23759 case VMULPHZrm:
23760 case VMULPHZrmb:
23761 case VMULPHZrmbk:
23762 case VMULPHZrmbkz:
23763 case VMULPHZrmk:
23764 case VMULPHZrmkz:
23765 case VMULPHZrr:
23766 case VMULPHZrrb:
23767 case VMULPHZrrbk:
23768 case VMULPHZrrbkz:
23769 case VMULPHZrrk:
23770 case VMULPHZrrkz:
23771 return true;
23772 }
23773 return false;
23774}
23775
23776bool isVPCMPUQ(unsigned Opcode) {
23777 switch (Opcode) {
23778 case VPCMPUQZ128rmbi:
23779 case VPCMPUQZ128rmbik:
23780 case VPCMPUQZ128rmi:
23781 case VPCMPUQZ128rmik:
23782 case VPCMPUQZ128rri:
23783 case VPCMPUQZ128rrik:
23784 case VPCMPUQZ256rmbi:
23785 case VPCMPUQZ256rmbik:
23786 case VPCMPUQZ256rmi:
23787 case VPCMPUQZ256rmik:
23788 case VPCMPUQZ256rri:
23789 case VPCMPUQZ256rrik:
23790 case VPCMPUQZrmbi:
23791 case VPCMPUQZrmbik:
23792 case VPCMPUQZrmi:
23793 case VPCMPUQZrmik:
23794 case VPCMPUQZrri:
23795 case VPCMPUQZrrik:
23796 return true;
23797 }
23798 return false;
23799}
23800
23801bool isVCVTUSI2SD(unsigned Opcode) {
23802 switch (Opcode) {
23803 case VCVTUSI2SDZrm_Int:
23804 case VCVTUSI2SDZrr_Int:
23805 case VCVTUSI642SDZrm_Int:
23806 case VCVTUSI642SDZrr_Int:
23807 case VCVTUSI642SDZrrb_Int:
23808 return true;
23809 }
23810 return false;
23811}
23812
23813bool isKXNORW(unsigned Opcode) {
23814 return Opcode == KXNORWkk;
23815}
23816
23817bool isBLCIC(unsigned Opcode) {
23818 switch (Opcode) {
23819 case BLCIC32rm:
23820 case BLCIC32rr:
23821 case BLCIC64rm:
23822 case BLCIC64rr:
23823 return true;
23824 }
23825 return false;
23826}
23827
23828bool isVFNMADD213SD(unsigned Opcode) {
23829 switch (Opcode) {
23830 case VFNMADD213SDZm_Int:
23831 case VFNMADD213SDZmk_Int:
23832 case VFNMADD213SDZmkz_Int:
23833 case VFNMADD213SDZr_Int:
23834 case VFNMADD213SDZrb_Int:
23835 case VFNMADD213SDZrbk_Int:
23836 case VFNMADD213SDZrbkz_Int:
23837 case VFNMADD213SDZrk_Int:
23838 case VFNMADD213SDZrkz_Int:
23839 case VFNMADD213SDm_Int:
23840 case VFNMADD213SDr_Int:
23841 return true;
23842 }
23843 return false;
23844}
23845
23846bool isVPMACSWW(unsigned Opcode) {
23847 switch (Opcode) {
23848 case VPMACSWWrm:
23849 case VPMACSWWrr:
23850 return true;
23851 }
23852 return false;
23853}
23854
23855bool isVMOVLPS(unsigned Opcode) {
23856 switch (Opcode) {
23857 case VMOVLPSZ128mr:
23858 case VMOVLPSZ128rm:
23859 case VMOVLPSmr:
23860 case VMOVLPSrm:
23861 return true;
23862 }
23863 return false;
23864}
23865
23866bool isPCONFIG(unsigned Opcode) {
23867 return Opcode == PCONFIG;
23868}
23869
23870bool isPANDN(unsigned Opcode) {
23871 switch (Opcode) {
23872 case MMX_PANDNrm:
23873 case MMX_PANDNrr:
23874 case PANDNrm:
23875 case PANDNrr:
23876 return true;
23877 }
23878 return false;
23879}
23880
23881bool isVGETEXPPD(unsigned Opcode) {
23882 switch (Opcode) {
23883 case VGETEXPPDZ128m:
23884 case VGETEXPPDZ128mb:
23885 case VGETEXPPDZ128mbk:
23886 case VGETEXPPDZ128mbkz:
23887 case VGETEXPPDZ128mk:
23888 case VGETEXPPDZ128mkz:
23889 case VGETEXPPDZ128r:
23890 case VGETEXPPDZ128rk:
23891 case VGETEXPPDZ128rkz:
23892 case VGETEXPPDZ256m:
23893 case VGETEXPPDZ256mb:
23894 case VGETEXPPDZ256mbk:
23895 case VGETEXPPDZ256mbkz:
23896 case VGETEXPPDZ256mk:
23897 case VGETEXPPDZ256mkz:
23898 case VGETEXPPDZ256r:
23899 case VGETEXPPDZ256rk:
23900 case VGETEXPPDZ256rkz:
23901 case VGETEXPPDZm:
23902 case VGETEXPPDZmb:
23903 case VGETEXPPDZmbk:
23904 case VGETEXPPDZmbkz:
23905 case VGETEXPPDZmk:
23906 case VGETEXPPDZmkz:
23907 case VGETEXPPDZr:
23908 case VGETEXPPDZrb:
23909 case VGETEXPPDZrbk:
23910 case VGETEXPPDZrbkz:
23911 case VGETEXPPDZrk:
23912 case VGETEXPPDZrkz:
23913 return true;
23914 }
23915 return false;
23916}
23917
23918bool isVPSRLVQ(unsigned Opcode) {
23919 switch (Opcode) {
23920 case VPSRLVQYrm:
23921 case VPSRLVQYrr:
23922 case VPSRLVQZ128rm:
23923 case VPSRLVQZ128rmb:
23924 case VPSRLVQZ128rmbk:
23925 case VPSRLVQZ128rmbkz:
23926 case VPSRLVQZ128rmk:
23927 case VPSRLVQZ128rmkz:
23928 case VPSRLVQZ128rr:
23929 case VPSRLVQZ128rrk:
23930 case VPSRLVQZ128rrkz:
23931 case VPSRLVQZ256rm:
23932 case VPSRLVQZ256rmb:
23933 case VPSRLVQZ256rmbk:
23934 case VPSRLVQZ256rmbkz:
23935 case VPSRLVQZ256rmk:
23936 case VPSRLVQZ256rmkz:
23937 case VPSRLVQZ256rr:
23938 case VPSRLVQZ256rrk:
23939 case VPSRLVQZ256rrkz:
23940 case VPSRLVQZrm:
23941 case VPSRLVQZrmb:
23942 case VPSRLVQZrmbk:
23943 case VPSRLVQZrmbkz:
23944 case VPSRLVQZrmk:
23945 case VPSRLVQZrmkz:
23946 case VPSRLVQZrr:
23947 case VPSRLVQZrrk:
23948 case VPSRLVQZrrkz:
23949 case VPSRLVQrm:
23950 case VPSRLVQrr:
23951 return true;
23952 }
23953 return false;
23954}
23955
23956bool isUD1(unsigned Opcode) {
23957 switch (Opcode) {
23958 case UD1Lm:
23959 case UD1Lr:
23960 case UD1Qm:
23961 case UD1Qr:
23962 case UD1Wm:
23963 case UD1Wr:
23964 return true;
23965 }
23966 return false;
23967}
23968
23969bool isPMAXSB(unsigned Opcode) {
23970 switch (Opcode) {
23971 case PMAXSBrm:
23972 case PMAXSBrr:
23973 return true;
23974 }
23975 return false;
23976}
23977
23978bool isVPROLQ(unsigned Opcode) {
23979 switch (Opcode) {
23980 case VPROLQZ128mbi:
23981 case VPROLQZ128mbik:
23982 case VPROLQZ128mbikz:
23983 case VPROLQZ128mi:
23984 case VPROLQZ128mik:
23985 case VPROLQZ128mikz:
23986 case VPROLQZ128ri:
23987 case VPROLQZ128rik:
23988 case VPROLQZ128rikz:
23989 case VPROLQZ256mbi:
23990 case VPROLQZ256mbik:
23991 case VPROLQZ256mbikz:
23992 case VPROLQZ256mi:
23993 case VPROLQZ256mik:
23994 case VPROLQZ256mikz:
23995 case VPROLQZ256ri:
23996 case VPROLQZ256rik:
23997 case VPROLQZ256rikz:
23998 case VPROLQZmbi:
23999 case VPROLQZmbik:
24000 case VPROLQZmbikz:
24001 case VPROLQZmi:
24002 case VPROLQZmik:
24003 case VPROLQZmikz:
24004 case VPROLQZri:
24005 case VPROLQZrik:
24006 case VPROLQZrikz:
24007 return true;
24008 }
24009 return false;
24010}
24011
24012bool isVSCATTERPF1QPD(unsigned Opcode) {
24013 return Opcode == VSCATTERPF1QPDm;
24014}
24015
24016bool isVPSRLD(unsigned Opcode) {
24017 switch (Opcode) {
24018 case VPSRLDYri:
24019 case VPSRLDYrm:
24020 case VPSRLDYrr:
24021 case VPSRLDZ128mbi:
24022 case VPSRLDZ128mbik:
24023 case VPSRLDZ128mbikz:
24024 case VPSRLDZ128mi:
24025 case VPSRLDZ128mik:
24026 case VPSRLDZ128mikz:
24027 case VPSRLDZ128ri:
24028 case VPSRLDZ128rik:
24029 case VPSRLDZ128rikz:
24030 case VPSRLDZ128rm:
24031 case VPSRLDZ128rmk:
24032 case VPSRLDZ128rmkz:
24033 case VPSRLDZ128rr:
24034 case VPSRLDZ128rrk:
24035 case VPSRLDZ128rrkz:
24036 case VPSRLDZ256mbi:
24037 case VPSRLDZ256mbik:
24038 case VPSRLDZ256mbikz:
24039 case VPSRLDZ256mi:
24040 case VPSRLDZ256mik:
24041 case VPSRLDZ256mikz:
24042 case VPSRLDZ256ri:
24043 case VPSRLDZ256rik:
24044 case VPSRLDZ256rikz:
24045 case VPSRLDZ256rm:
24046 case VPSRLDZ256rmk:
24047 case VPSRLDZ256rmkz:
24048 case VPSRLDZ256rr:
24049 case VPSRLDZ256rrk:
24050 case VPSRLDZ256rrkz:
24051 case VPSRLDZmbi:
24052 case VPSRLDZmbik:
24053 case VPSRLDZmbikz:
24054 case VPSRLDZmi:
24055 case VPSRLDZmik:
24056 case VPSRLDZmikz:
24057 case VPSRLDZri:
24058 case VPSRLDZrik:
24059 case VPSRLDZrikz:
24060 case VPSRLDZrm:
24061 case VPSRLDZrmk:
24062 case VPSRLDZrmkz:
24063 case VPSRLDZrr:
24064 case VPSRLDZrrk:
24065 case VPSRLDZrrkz:
24066 case VPSRLDri:
24067 case VPSRLDrm:
24068 case VPSRLDrr:
24069 return true;
24070 }
24071 return false;
24072}
24073
24074bool isINT3(unsigned Opcode) {
24075 return Opcode == INT3;
24076}
24077
24078bool isXRSTORS64(unsigned Opcode) {
24079 return Opcode == XRSTORS64;
24080}
24081
24082bool isCVTSD2SI(unsigned Opcode) {
24083 switch (Opcode) {
24084 case CVTSD2SI64rm_Int:
24085 case CVTSD2SI64rr_Int:
24086 case CVTSD2SIrm_Int:
24087 case CVTSD2SIrr_Int:
24088 return true;
24089 }
24090 return false;
24091}
24092
24093bool isVMAXSS(unsigned Opcode) {
24094 switch (Opcode) {
24095 case VMAXSSZrm_Int:
24096 case VMAXSSZrmk_Int:
24097 case VMAXSSZrmkz_Int:
24098 case VMAXSSZrr_Int:
24099 case VMAXSSZrrb_Int:
24100 case VMAXSSZrrbk_Int:
24101 case VMAXSSZrrbkz_Int:
24102 case VMAXSSZrrk_Int:
24103 case VMAXSSZrrkz_Int:
24104 case VMAXSSrm_Int:
24105 case VMAXSSrr_Int:
24106 return true;
24107 }
24108 return false;
24109}
24110
24111bool isVPMINUB(unsigned Opcode) {
24112 switch (Opcode) {
24113 case VPMINUBYrm:
24114 case VPMINUBYrr:
24115 case VPMINUBZ128rm:
24116 case VPMINUBZ128rmk:
24117 case VPMINUBZ128rmkz:
24118 case VPMINUBZ128rr:
24119 case VPMINUBZ128rrk:
24120 case VPMINUBZ128rrkz:
24121 case VPMINUBZ256rm:
24122 case VPMINUBZ256rmk:
24123 case VPMINUBZ256rmkz:
24124 case VPMINUBZ256rr:
24125 case VPMINUBZ256rrk:
24126 case VPMINUBZ256rrkz:
24127 case VPMINUBZrm:
24128 case VPMINUBZrmk:
24129 case VPMINUBZrmkz:
24130 case VPMINUBZrr:
24131 case VPMINUBZrrk:
24132 case VPMINUBZrrkz:
24133 case VPMINUBrm:
24134 case VPMINUBrr:
24135 return true;
24136 }
24137 return false;
24138}
24139
24140bool isKXNORQ(unsigned Opcode) {
24141 return Opcode == KXNORQkk;
24142}
24143
24144bool isFLD(unsigned Opcode) {
24145 switch (Opcode) {
24146 case LD_F32m:
24147 case LD_F64m:
24148 case LD_F80m:
24149 case LD_Frr:
24150 return true;
24151 }
24152 return false;
24153}
24154
24155bool isVSHUFI32X4(unsigned Opcode) {
24156 switch (Opcode) {
24157 case VSHUFI32X4Z256rmbi:
24158 case VSHUFI32X4Z256rmbik:
24159 case VSHUFI32X4Z256rmbikz:
24160 case VSHUFI32X4Z256rmi:
24161 case VSHUFI32X4Z256rmik:
24162 case VSHUFI32X4Z256rmikz:
24163 case VSHUFI32X4Z256rri:
24164 case VSHUFI32X4Z256rrik:
24165 case VSHUFI32X4Z256rrikz:
24166 case VSHUFI32X4Zrmbi:
24167 case VSHUFI32X4Zrmbik:
24168 case VSHUFI32X4Zrmbikz:
24169 case VSHUFI32X4Zrmi:
24170 case VSHUFI32X4Zrmik:
24171 case VSHUFI32X4Zrmikz:
24172 case VSHUFI32X4Zrri:
24173 case VSHUFI32X4Zrrik:
24174 case VSHUFI32X4Zrrikz:
24175 return true;
24176 }
24177 return false;
24178}
24179
24180bool isSAHF(unsigned Opcode) {
24181 return Opcode == SAHF;
24182}
24183
24184bool isPFRSQRT(unsigned Opcode) {
24185 switch (Opcode) {
24186 case PFRSQRTrm:
24187 case PFRSQRTrr:
24188 return true;
24189 }
24190 return false;
24191}
24192
24193bool isSHRD(unsigned Opcode) {
24194 switch (Opcode) {
24195 case SHRD16mrCL:
24196 case SHRD16mrCL_EVEX:
24197 case SHRD16mrCL_ND:
24198 case SHRD16mrCL_NF:
24199 case SHRD16mrCL_NF_ND:
24200 case SHRD16mri8:
24201 case SHRD16mri8_EVEX:
24202 case SHRD16mri8_ND:
24203 case SHRD16mri8_NF:
24204 case SHRD16mri8_NF_ND:
24205 case SHRD16rrCL:
24206 case SHRD16rrCL_EVEX:
24207 case SHRD16rrCL_ND:
24208 case SHRD16rrCL_NF:
24209 case SHRD16rrCL_NF_ND:
24210 case SHRD16rri8:
24211 case SHRD16rri8_EVEX:
24212 case SHRD16rri8_ND:
24213 case SHRD16rri8_NF:
24214 case SHRD16rri8_NF_ND:
24215 case SHRD32mrCL:
24216 case SHRD32mrCL_EVEX:
24217 case SHRD32mrCL_ND:
24218 case SHRD32mrCL_NF:
24219 case SHRD32mrCL_NF_ND:
24220 case SHRD32mri8:
24221 case SHRD32mri8_EVEX:
24222 case SHRD32mri8_ND:
24223 case SHRD32mri8_NF:
24224 case SHRD32mri8_NF_ND:
24225 case SHRD32rrCL:
24226 case SHRD32rrCL_EVEX:
24227 case SHRD32rrCL_ND:
24228 case SHRD32rrCL_NF:
24229 case SHRD32rrCL_NF_ND:
24230 case SHRD32rri8:
24231 case SHRD32rri8_EVEX:
24232 case SHRD32rri8_ND:
24233 case SHRD32rri8_NF:
24234 case SHRD32rri8_NF_ND:
24235 case SHRD64mrCL:
24236 case SHRD64mrCL_EVEX:
24237 case SHRD64mrCL_ND:
24238 case SHRD64mrCL_NF:
24239 case SHRD64mrCL_NF_ND:
24240 case SHRD64mri8:
24241 case SHRD64mri8_EVEX:
24242 case SHRD64mri8_ND:
24243 case SHRD64mri8_NF:
24244 case SHRD64mri8_NF_ND:
24245 case SHRD64rrCL:
24246 case SHRD64rrCL_EVEX:
24247 case SHRD64rrCL_ND:
24248 case SHRD64rrCL_NF:
24249 case SHRD64rrCL_NF_ND:
24250 case SHRD64rri8:
24251 case SHRD64rri8_EVEX:
24252 case SHRD64rri8_ND:
24253 case SHRD64rri8_NF:
24254 case SHRD64rri8_NF_ND:
24255 return true;
24256 }
24257 return false;
24258}
24259
24260bool isSYSEXIT(unsigned Opcode) {
24261 return Opcode == SYSEXIT;
24262}
24263
24264bool isXSAVE64(unsigned Opcode) {
24265 return Opcode == XSAVE64;
24266}
24267
24268bool isVPMAXSD(unsigned Opcode) {
24269 switch (Opcode) {
24270 case VPMAXSDYrm:
24271 case VPMAXSDYrr:
24272 case VPMAXSDZ128rm:
24273 case VPMAXSDZ128rmb:
24274 case VPMAXSDZ128rmbk:
24275 case VPMAXSDZ128rmbkz:
24276 case VPMAXSDZ128rmk:
24277 case VPMAXSDZ128rmkz:
24278 case VPMAXSDZ128rr:
24279 case VPMAXSDZ128rrk:
24280 case VPMAXSDZ128rrkz:
24281 case VPMAXSDZ256rm:
24282 case VPMAXSDZ256rmb:
24283 case VPMAXSDZ256rmbk:
24284 case VPMAXSDZ256rmbkz:
24285 case VPMAXSDZ256rmk:
24286 case VPMAXSDZ256rmkz:
24287 case VPMAXSDZ256rr:
24288 case VPMAXSDZ256rrk:
24289 case VPMAXSDZ256rrkz:
24290 case VPMAXSDZrm:
24291 case VPMAXSDZrmb:
24292 case VPMAXSDZrmbk:
24293 case VPMAXSDZrmbkz:
24294 case VPMAXSDZrmk:
24295 case VPMAXSDZrmkz:
24296 case VPMAXSDZrr:
24297 case VPMAXSDZrrk:
24298 case VPMAXSDZrrkz:
24299 case VPMAXSDrm:
24300 case VPMAXSDrr:
24301 return true;
24302 }
24303 return false;
24304}
24305
24306bool isCVTTSD2SI(unsigned Opcode) {
24307 switch (Opcode) {
24308 case CVTTSD2SI64rm_Int:
24309 case CVTTSD2SI64rr_Int:
24310 case CVTTSD2SIrm_Int:
24311 case CVTTSD2SIrr_Int:
24312 return true;
24313 }
24314 return false;
24315}
24316
24317bool isVCVTTSS2SIS(unsigned Opcode) {
24318 switch (Opcode) {
24319 case VCVTTSS2SI64Srm_Int:
24320 case VCVTTSS2SI64Srr_Int:
24321 case VCVTTSS2SI64Srrb_Int:
24322 case VCVTTSS2SISrm_Int:
24323 case VCVTTSS2SISrr_Int:
24324 case VCVTTSS2SISrrb_Int:
24325 return true;
24326 }
24327 return false;
24328}
24329
24330bool isPMOVMSKB(unsigned Opcode) {
24331 switch (Opcode) {
24332 case MMX_PMOVMSKBrr:
24333 case PMOVMSKBrr:
24334 return true;
24335 }
24336 return false;
24337}
24338
24339bool isVRANGEPS(unsigned Opcode) {
24340 switch (Opcode) {
24341 case VRANGEPSZ128rmbi:
24342 case VRANGEPSZ128rmbik:
24343 case VRANGEPSZ128rmbikz:
24344 case VRANGEPSZ128rmi:
24345 case VRANGEPSZ128rmik:
24346 case VRANGEPSZ128rmikz:
24347 case VRANGEPSZ128rri:
24348 case VRANGEPSZ128rrik:
24349 case VRANGEPSZ128rrikz:
24350 case VRANGEPSZ256rmbi:
24351 case VRANGEPSZ256rmbik:
24352 case VRANGEPSZ256rmbikz:
24353 case VRANGEPSZ256rmi:
24354 case VRANGEPSZ256rmik:
24355 case VRANGEPSZ256rmikz:
24356 case VRANGEPSZ256rri:
24357 case VRANGEPSZ256rrik:
24358 case VRANGEPSZ256rrikz:
24359 case VRANGEPSZrmbi:
24360 case VRANGEPSZrmbik:
24361 case VRANGEPSZrmbikz:
24362 case VRANGEPSZrmi:
24363 case VRANGEPSZrmik:
24364 case VRANGEPSZrmikz:
24365 case VRANGEPSZrri:
24366 case VRANGEPSZrrib:
24367 case VRANGEPSZrribk:
24368 case VRANGEPSZrribkz:
24369 case VRANGEPSZrrik:
24370 case VRANGEPSZrrikz:
24371 return true;
24372 }
24373 return false;
24374}
24375
24376bool isVADDSUBPS(unsigned Opcode) {
24377 switch (Opcode) {
24378 case VADDSUBPSYrm:
24379 case VADDSUBPSYrr:
24380 case VADDSUBPSrm:
24381 case VADDSUBPSrr:
24382 return true;
24383 }
24384 return false;
24385}
24386
24387bool isVBROADCASTI128(unsigned Opcode) {
24388 return Opcode == VBROADCASTI128rm;
24389}
24390
24391bool isPADDUSB(unsigned Opcode) {
24392 switch (Opcode) {
24393 case MMX_PADDUSBrm:
24394 case MMX_PADDUSBrr:
24395 case PADDUSBrm:
24396 case PADDUSBrr:
24397 return true;
24398 }
24399 return false;
24400}
24401
24402bool isENCODEKEY128(unsigned Opcode) {
24403 return Opcode == ENCODEKEY128;
24404}
24405
24406bool isOR(unsigned Opcode) {
24407 switch (Opcode) {
24408 case OR16i16:
24409 case OR16mi:
24410 case OR16mi8:
24411 case OR16mi8_EVEX:
24412 case OR16mi8_ND:
24413 case OR16mi8_NF:
24414 case OR16mi8_NF_ND:
24415 case OR16mi_EVEX:
24416 case OR16mi_ND:
24417 case OR16mi_NF:
24418 case OR16mi_NF_ND:
24419 case OR16mr:
24420 case OR16mr_EVEX:
24421 case OR16mr_ND:
24422 case OR16mr_NF:
24423 case OR16mr_NF_ND:
24424 case OR16ri:
24425 case OR16ri8:
24426 case OR16ri8_EVEX:
24427 case OR16ri8_ND:
24428 case OR16ri8_NF:
24429 case OR16ri8_NF_ND:
24430 case OR16ri_EVEX:
24431 case OR16ri_ND:
24432 case OR16ri_NF:
24433 case OR16ri_NF_ND:
24434 case OR16rm:
24435 case OR16rm_EVEX:
24436 case OR16rm_ND:
24437 case OR16rm_NF:
24438 case OR16rm_NF_ND:
24439 case OR16rr:
24440 case OR16rr_EVEX:
24441 case OR16rr_EVEX_REV:
24442 case OR16rr_ND:
24443 case OR16rr_ND_REV:
24444 case OR16rr_NF:
24445 case OR16rr_NF_ND:
24446 case OR16rr_NF_ND_REV:
24447 case OR16rr_NF_REV:
24448 case OR16rr_REV:
24449 case OR32i32:
24450 case OR32mi:
24451 case OR32mi8:
24452 case OR32mi8_EVEX:
24453 case OR32mi8_ND:
24454 case OR32mi8_NF:
24455 case OR32mi8_NF_ND:
24456 case OR32mi_EVEX:
24457 case OR32mi_ND:
24458 case OR32mi_NF:
24459 case OR32mi_NF_ND:
24460 case OR32mr:
24461 case OR32mr_EVEX:
24462 case OR32mr_ND:
24463 case OR32mr_NF:
24464 case OR32mr_NF_ND:
24465 case OR32ri:
24466 case OR32ri8:
24467 case OR32ri8_EVEX:
24468 case OR32ri8_ND:
24469 case OR32ri8_NF:
24470 case OR32ri8_NF_ND:
24471 case OR32ri_EVEX:
24472 case OR32ri_ND:
24473 case OR32ri_NF:
24474 case OR32ri_NF_ND:
24475 case OR32rm:
24476 case OR32rm_EVEX:
24477 case OR32rm_ND:
24478 case OR32rm_NF:
24479 case OR32rm_NF_ND:
24480 case OR32rr:
24481 case OR32rr_EVEX:
24482 case OR32rr_EVEX_REV:
24483 case OR32rr_ND:
24484 case OR32rr_ND_REV:
24485 case OR32rr_NF:
24486 case OR32rr_NF_ND:
24487 case OR32rr_NF_ND_REV:
24488 case OR32rr_NF_REV:
24489 case OR32rr_REV:
24490 case OR64i32:
24491 case OR64mi32:
24492 case OR64mi32_EVEX:
24493 case OR64mi32_ND:
24494 case OR64mi32_NF:
24495 case OR64mi32_NF_ND:
24496 case OR64mi8:
24497 case OR64mi8_EVEX:
24498 case OR64mi8_ND:
24499 case OR64mi8_NF:
24500 case OR64mi8_NF_ND:
24501 case OR64mr:
24502 case OR64mr_EVEX:
24503 case OR64mr_ND:
24504 case OR64mr_NF:
24505 case OR64mr_NF_ND:
24506 case OR64ri32:
24507 case OR64ri32_EVEX:
24508 case OR64ri32_ND:
24509 case OR64ri32_NF:
24510 case OR64ri32_NF_ND:
24511 case OR64ri8:
24512 case OR64ri8_EVEX:
24513 case OR64ri8_ND:
24514 case OR64ri8_NF:
24515 case OR64ri8_NF_ND:
24516 case OR64rm:
24517 case OR64rm_EVEX:
24518 case OR64rm_ND:
24519 case OR64rm_NF:
24520 case OR64rm_NF_ND:
24521 case OR64rr:
24522 case OR64rr_EVEX:
24523 case OR64rr_EVEX_REV:
24524 case OR64rr_ND:
24525 case OR64rr_ND_REV:
24526 case OR64rr_NF:
24527 case OR64rr_NF_ND:
24528 case OR64rr_NF_ND_REV:
24529 case OR64rr_NF_REV:
24530 case OR64rr_REV:
24531 case OR8i8:
24532 case OR8mi:
24533 case OR8mi8:
24534 case OR8mi_EVEX:
24535 case OR8mi_ND:
24536 case OR8mi_NF:
24537 case OR8mi_NF_ND:
24538 case OR8mr:
24539 case OR8mr_EVEX:
24540 case OR8mr_ND:
24541 case OR8mr_NF:
24542 case OR8mr_NF_ND:
24543 case OR8ri:
24544 case OR8ri8:
24545 case OR8ri_EVEX:
24546 case OR8ri_ND:
24547 case OR8ri_NF:
24548 case OR8ri_NF_ND:
24549 case OR8rm:
24550 case OR8rm_EVEX:
24551 case OR8rm_ND:
24552 case OR8rm_NF:
24553 case OR8rm_NF_ND:
24554 case OR8rr:
24555 case OR8rr_EVEX:
24556 case OR8rr_EVEX_REV:
24557 case OR8rr_ND:
24558 case OR8rr_ND_REV:
24559 case OR8rr_NF:
24560 case OR8rr_NF_ND:
24561 case OR8rr_NF_ND_REV:
24562 case OR8rr_NF_REV:
24563 case OR8rr_REV:
24564 return true;
24565 }
24566 return false;
24567}
24568
24569bool isSTOSW(unsigned Opcode) {
24570 return Opcode == STOSW;
24571}
24572
24573bool isVCVTTPD2UQQS(unsigned Opcode) {
24574 switch (Opcode) {
24575 case VCVTTPD2UQQSZ128rm:
24576 case VCVTTPD2UQQSZ128rmb:
24577 case VCVTTPD2UQQSZ128rmbk:
24578 case VCVTTPD2UQQSZ128rmbkz:
24579 case VCVTTPD2UQQSZ128rmk:
24580 case VCVTTPD2UQQSZ128rmkz:
24581 case VCVTTPD2UQQSZ128rr:
24582 case VCVTTPD2UQQSZ128rrk:
24583 case VCVTTPD2UQQSZ128rrkz:
24584 case VCVTTPD2UQQSZ256rm:
24585 case VCVTTPD2UQQSZ256rmb:
24586 case VCVTTPD2UQQSZ256rmbk:
24587 case VCVTTPD2UQQSZ256rmbkz:
24588 case VCVTTPD2UQQSZ256rmk:
24589 case VCVTTPD2UQQSZ256rmkz:
24590 case VCVTTPD2UQQSZ256rr:
24591 case VCVTTPD2UQQSZ256rrb:
24592 case VCVTTPD2UQQSZ256rrbk:
24593 case VCVTTPD2UQQSZ256rrbkz:
24594 case VCVTTPD2UQQSZ256rrk:
24595 case VCVTTPD2UQQSZ256rrkz:
24596 case VCVTTPD2UQQSZrm:
24597 case VCVTTPD2UQQSZrmb:
24598 case VCVTTPD2UQQSZrmbk:
24599 case VCVTTPD2UQQSZrmbkz:
24600 case VCVTTPD2UQQSZrmk:
24601 case VCVTTPD2UQQSZrmkz:
24602 case VCVTTPD2UQQSZrr:
24603 case VCVTTPD2UQQSZrrb:
24604 case VCVTTPD2UQQSZrrbk:
24605 case VCVTTPD2UQQSZrrbkz:
24606 case VCVTTPD2UQQSZrrk:
24607 case VCVTTPD2UQQSZrrkz:
24608 return true;
24609 }
24610 return false;
24611}
24612
24613bool isPAVGW(unsigned Opcode) {
24614 switch (Opcode) {
24615 case MMX_PAVGWrm:
24616 case MMX_PAVGWrr:
24617 case PAVGWrm:
24618 case PAVGWrr:
24619 return true;
24620 }
24621 return false;
24622}
24623
24624bool isVCVTPD2PH(unsigned Opcode) {
24625 switch (Opcode) {
24626 case VCVTPD2PHZ128rm:
24627 case VCVTPD2PHZ128rmb:
24628 case VCVTPD2PHZ128rmbk:
24629 case VCVTPD2PHZ128rmbkz:
24630 case VCVTPD2PHZ128rmk:
24631 case VCVTPD2PHZ128rmkz:
24632 case VCVTPD2PHZ128rr:
24633 case VCVTPD2PHZ128rrk:
24634 case VCVTPD2PHZ128rrkz:
24635 case VCVTPD2PHZ256rm:
24636 case VCVTPD2PHZ256rmb:
24637 case VCVTPD2PHZ256rmbk:
24638 case VCVTPD2PHZ256rmbkz:
24639 case VCVTPD2PHZ256rmk:
24640 case VCVTPD2PHZ256rmkz:
24641 case VCVTPD2PHZ256rr:
24642 case VCVTPD2PHZ256rrk:
24643 case VCVTPD2PHZ256rrkz:
24644 case VCVTPD2PHZrm:
24645 case VCVTPD2PHZrmb:
24646 case VCVTPD2PHZrmbk:
24647 case VCVTPD2PHZrmbkz:
24648 case VCVTPD2PHZrmk:
24649 case VCVTPD2PHZrmkz:
24650 case VCVTPD2PHZrr:
24651 case VCVTPD2PHZrrb:
24652 case VCVTPD2PHZrrbk:
24653 case VCVTPD2PHZrrbkz:
24654 case VCVTPD2PHZrrk:
24655 case VCVTPD2PHZrrkz:
24656 return true;
24657 }
24658 return false;
24659}
24660
24661bool isSHLX(unsigned Opcode) {
24662 switch (Opcode) {
24663 case SHLX32rm:
24664 case SHLX32rm_EVEX:
24665 case SHLX32rr:
24666 case SHLX32rr_EVEX:
24667 case SHLX64rm:
24668 case SHLX64rm_EVEX:
24669 case SHLX64rr:
24670 case SHLX64rr_EVEX:
24671 return true;
24672 }
24673 return false;
24674}
24675
24676bool isVCVTSH2SD(unsigned Opcode) {
24677 switch (Opcode) {
24678 case VCVTSH2SDZrm_Int:
24679 case VCVTSH2SDZrmk_Int:
24680 case VCVTSH2SDZrmkz_Int:
24681 case VCVTSH2SDZrr_Int:
24682 case VCVTSH2SDZrrb_Int:
24683 case VCVTSH2SDZrrbk_Int:
24684 case VCVTSH2SDZrrbkz_Int:
24685 case VCVTSH2SDZrrk_Int:
24686 case VCVTSH2SDZrrkz_Int:
24687 return true;
24688 }
24689 return false;
24690}
24691
24692bool isVFMADD231SS(unsigned Opcode) {
24693 switch (Opcode) {
24694 case VFMADD231SSZm_Int:
24695 case VFMADD231SSZmk_Int:
24696 case VFMADD231SSZmkz_Int:
24697 case VFMADD231SSZr_Int:
24698 case VFMADD231SSZrb_Int:
24699 case VFMADD231SSZrbk_Int:
24700 case VFMADD231SSZrbkz_Int:
24701 case VFMADD231SSZrk_Int:
24702 case VFMADD231SSZrkz_Int:
24703 case VFMADD231SSm_Int:
24704 case VFMADD231SSr_Int:
24705 return true;
24706 }
24707 return false;
24708}
24709
24710bool isMOVNTSD(unsigned Opcode) {
24711 return Opcode == MOVNTSD;
24712}
24713
24714bool isFLDPI(unsigned Opcode) {
24715 return Opcode == FLDPI;
24716}
24717
24718bool isVCVTUSI2SS(unsigned Opcode) {
24719 switch (Opcode) {
24720 case VCVTUSI2SSZrm_Int:
24721 case VCVTUSI2SSZrr_Int:
24722 case VCVTUSI2SSZrrb_Int:
24723 case VCVTUSI642SSZrm_Int:
24724 case VCVTUSI642SSZrr_Int:
24725 case VCVTUSI642SSZrrb_Int:
24726 return true;
24727 }
24728 return false;
24729}
24730
24731bool isPMOVSXBD(unsigned Opcode) {
24732 switch (Opcode) {
24733 case PMOVSXBDrm:
24734 case PMOVSXBDrr:
24735 return true;
24736 }
24737 return false;
24738}
24739
24740bool isVPRORVQ(unsigned Opcode) {
24741 switch (Opcode) {
24742 case VPRORVQZ128rm:
24743 case VPRORVQZ128rmb:
24744 case VPRORVQZ128rmbk:
24745 case VPRORVQZ128rmbkz:
24746 case VPRORVQZ128rmk:
24747 case VPRORVQZ128rmkz:
24748 case VPRORVQZ128rr:
24749 case VPRORVQZ128rrk:
24750 case VPRORVQZ128rrkz:
24751 case VPRORVQZ256rm:
24752 case VPRORVQZ256rmb:
24753 case VPRORVQZ256rmbk:
24754 case VPRORVQZ256rmbkz:
24755 case VPRORVQZ256rmk:
24756 case VPRORVQZ256rmkz:
24757 case VPRORVQZ256rr:
24758 case VPRORVQZ256rrk:
24759 case VPRORVQZ256rrkz:
24760 case VPRORVQZrm:
24761 case VPRORVQZrmb:
24762 case VPRORVQZrmbk:
24763 case VPRORVQZrmbkz:
24764 case VPRORVQZrmk:
24765 case VPRORVQZrmkz:
24766 case VPRORVQZrr:
24767 case VPRORVQZrrk:
24768 case VPRORVQZrrkz:
24769 return true;
24770 }
24771 return false;
24772}
24773
24774bool isVPERMT2D(unsigned Opcode) {
24775 switch (Opcode) {
24776 case VPERMT2DZ128rm:
24777 case VPERMT2DZ128rmb:
24778 case VPERMT2DZ128rmbk:
24779 case VPERMT2DZ128rmbkz:
24780 case VPERMT2DZ128rmk:
24781 case VPERMT2DZ128rmkz:
24782 case VPERMT2DZ128rr:
24783 case VPERMT2DZ128rrk:
24784 case VPERMT2DZ128rrkz:
24785 case VPERMT2DZ256rm:
24786 case VPERMT2DZ256rmb:
24787 case VPERMT2DZ256rmbk:
24788 case VPERMT2DZ256rmbkz:
24789 case VPERMT2DZ256rmk:
24790 case VPERMT2DZ256rmkz:
24791 case VPERMT2DZ256rr:
24792 case VPERMT2DZ256rrk:
24793 case VPERMT2DZ256rrkz:
24794 case VPERMT2DZrm:
24795 case VPERMT2DZrmb:
24796 case VPERMT2DZrmbk:
24797 case VPERMT2DZrmbkz:
24798 case VPERMT2DZrmk:
24799 case VPERMT2DZrmkz:
24800 case VPERMT2DZrr:
24801 case VPERMT2DZrrk:
24802 case VPERMT2DZrrkz:
24803 return true;
24804 }
24805 return false;
24806}
24807
24808bool isADDSS(unsigned Opcode) {
24809 switch (Opcode) {
24810 case ADDSSrm_Int:
24811 case ADDSSrr_Int:
24812 return true;
24813 }
24814 return false;
24815}
24816
24817bool isAADD(unsigned Opcode) {
24818 switch (Opcode) {
24819 case AADD32mr:
24820 case AADD32mr_EVEX:
24821 case AADD64mr:
24822 case AADD64mr_EVEX:
24823 return true;
24824 }
24825 return false;
24826}
24827
24828bool isVPSRLVW(unsigned Opcode) {
24829 switch (Opcode) {
24830 case VPSRLVWZ128rm:
24831 case VPSRLVWZ128rmk:
24832 case VPSRLVWZ128rmkz:
24833 case VPSRLVWZ128rr:
24834 case VPSRLVWZ128rrk:
24835 case VPSRLVWZ128rrkz:
24836 case VPSRLVWZ256rm:
24837 case VPSRLVWZ256rmk:
24838 case VPSRLVWZ256rmkz:
24839 case VPSRLVWZ256rr:
24840 case VPSRLVWZ256rrk:
24841 case VPSRLVWZ256rrkz:
24842 case VPSRLVWZrm:
24843 case VPSRLVWZrmk:
24844 case VPSRLVWZrmkz:
24845 case VPSRLVWZrr:
24846 case VPSRLVWZrrk:
24847 case VPSRLVWZrrkz:
24848 return true;
24849 }
24850 return false;
24851}
24852
24853bool isVRSQRTPH(unsigned Opcode) {
24854 switch (Opcode) {
24855 case VRSQRTPHZ128m:
24856 case VRSQRTPHZ128mb:
24857 case VRSQRTPHZ128mbk:
24858 case VRSQRTPHZ128mbkz:
24859 case VRSQRTPHZ128mk:
24860 case VRSQRTPHZ128mkz:
24861 case VRSQRTPHZ128r:
24862 case VRSQRTPHZ128rk:
24863 case VRSQRTPHZ128rkz:
24864 case VRSQRTPHZ256m:
24865 case VRSQRTPHZ256mb:
24866 case VRSQRTPHZ256mbk:
24867 case VRSQRTPHZ256mbkz:
24868 case VRSQRTPHZ256mk:
24869 case VRSQRTPHZ256mkz:
24870 case VRSQRTPHZ256r:
24871 case VRSQRTPHZ256rk:
24872 case VRSQRTPHZ256rkz:
24873 case VRSQRTPHZm:
24874 case VRSQRTPHZmb:
24875 case VRSQRTPHZmbk:
24876 case VRSQRTPHZmbkz:
24877 case VRSQRTPHZmk:
24878 case VRSQRTPHZmkz:
24879 case VRSQRTPHZr:
24880 case VRSQRTPHZrk:
24881 case VRSQRTPHZrkz:
24882 return true;
24883 }
24884 return false;
24885}
24886
24887bool isVLDDQU(unsigned Opcode) {
24888 switch (Opcode) {
24889 case VLDDQUYrm:
24890 case VLDDQUrm:
24891 return true;
24892 }
24893 return false;
24894}
24895
24896bool isKMOVD(unsigned Opcode) {
24897 switch (Opcode) {
24898 case KMOVDkk:
24899 case KMOVDkk_EVEX:
24900 case KMOVDkm:
24901 case KMOVDkm_EVEX:
24902 case KMOVDkr:
24903 case KMOVDkr_EVEX:
24904 case KMOVDmk:
24905 case KMOVDmk_EVEX:
24906 case KMOVDrk:
24907 case KMOVDrk_EVEX:
24908 return true;
24909 }
24910 return false;
24911}
24912
24913bool isENCLV(unsigned Opcode) {
24914 return Opcode == ENCLV;
24915}
24916
24917bool isENCLU(unsigned Opcode) {
24918 return Opcode == ENCLU;
24919}
24920
24921bool isPREFETCHT1(unsigned Opcode) {
24922 return Opcode == PREFETCHT1;
24923}
24924
24925bool isRSQRTPS(unsigned Opcode) {
24926 switch (Opcode) {
24927 case RSQRTPSm:
24928 case RSQRTPSr:
24929 return true;
24930 }
24931 return false;
24932}
24933
24934bool isVCVTTSH2USI(unsigned Opcode) {
24935 switch (Opcode) {
24936 case VCVTTSH2USI64Zrm_Int:
24937 case VCVTTSH2USI64Zrr_Int:
24938 case VCVTTSH2USI64Zrrb_Int:
24939 case VCVTTSH2USIZrm_Int:
24940 case VCVTTSH2USIZrr_Int:
24941 case VCVTTSH2USIZrrb_Int:
24942 return true;
24943 }
24944 return false;
24945}
24946
24947bool isPADDB(unsigned Opcode) {
24948 switch (Opcode) {
24949 case MMX_PADDBrm:
24950 case MMX_PADDBrr:
24951 case PADDBrm:
24952 case PADDBrr:
24953 return true;
24954 }
24955 return false;
24956}
24957
24958bool isVMASKMOVDQU(unsigned Opcode) {
24959 return Opcode == VMASKMOVDQU64;
24960}
24961
24962bool isPUNPCKLBW(unsigned Opcode) {
24963 switch (Opcode) {
24964 case MMX_PUNPCKLBWrm:
24965 case MMX_PUNPCKLBWrr:
24966 case PUNPCKLBWrm:
24967 case PUNPCKLBWrr:
24968 return true;
24969 }
24970 return false;
24971}
24972
24973bool isMOV(unsigned Opcode) {
24974 switch (Opcode) {
24975 case MOV16ao16:
24976 case MOV16ao32:
24977 case MOV16mi:
24978 case MOV16mr:
24979 case MOV16ms:
24980 case MOV16o16a:
24981 case MOV16o32a:
24982 case MOV16ri:
24983 case MOV16ri_alt:
24984 case MOV16rm:
24985 case MOV16rr:
24986 case MOV16rr_REV:
24987 case MOV16rs:
24988 case MOV16sm:
24989 case MOV16sr:
24990 case MOV32ao16:
24991 case MOV32ao32:
24992 case MOV32cr:
24993 case MOV32dr:
24994 case MOV32mi:
24995 case MOV32mr:
24996 case MOV32o16a:
24997 case MOV32o32a:
24998 case MOV32rc:
24999 case MOV32rd:
25000 case MOV32ri:
25001 case MOV32ri_alt:
25002 case MOV32rm:
25003 case MOV32rr:
25004 case MOV32rr_REV:
25005 case MOV32rs:
25006 case MOV32sr:
25007 case MOV64ao32:
25008 case MOV64cr:
25009 case MOV64dr:
25010 case MOV64mi32:
25011 case MOV64mr:
25012 case MOV64o32a:
25013 case MOV64rc:
25014 case MOV64rd:
25015 case MOV64ri32:
25016 case MOV64rm:
25017 case MOV64rr:
25018 case MOV64rr_REV:
25019 case MOV64rs:
25020 case MOV64sr:
25021 case MOV8ao16:
25022 case MOV8ao32:
25023 case MOV8mi:
25024 case MOV8mr:
25025 case MOV8o16a:
25026 case MOV8o32a:
25027 case MOV8ri:
25028 case MOV8ri_alt:
25029 case MOV8rm:
25030 case MOV8rr:
25031 case MOV8rr_REV:
25032 return true;
25033 }
25034 return false;
25035}
25036
25037bool isVCVTTPH2IUBS(unsigned Opcode) {
25038 switch (Opcode) {
25039 case VCVTTPH2IUBSZ128rm:
25040 case VCVTTPH2IUBSZ128rmb:
25041 case VCVTTPH2IUBSZ128rmbk:
25042 case VCVTTPH2IUBSZ128rmbkz:
25043 case VCVTTPH2IUBSZ128rmk:
25044 case VCVTTPH2IUBSZ128rmkz:
25045 case VCVTTPH2IUBSZ128rr:
25046 case VCVTTPH2IUBSZ128rrk:
25047 case VCVTTPH2IUBSZ128rrkz:
25048 case VCVTTPH2IUBSZ256rm:
25049 case VCVTTPH2IUBSZ256rmb:
25050 case VCVTTPH2IUBSZ256rmbk:
25051 case VCVTTPH2IUBSZ256rmbkz:
25052 case VCVTTPH2IUBSZ256rmk:
25053 case VCVTTPH2IUBSZ256rmkz:
25054 case VCVTTPH2IUBSZ256rr:
25055 case VCVTTPH2IUBSZ256rrk:
25056 case VCVTTPH2IUBSZ256rrkz:
25057 case VCVTTPH2IUBSZrm:
25058 case VCVTTPH2IUBSZrmb:
25059 case VCVTTPH2IUBSZrmbk:
25060 case VCVTTPH2IUBSZrmbkz:
25061 case VCVTTPH2IUBSZrmk:
25062 case VCVTTPH2IUBSZrmkz:
25063 case VCVTTPH2IUBSZrr:
25064 case VCVTTPH2IUBSZrrb:
25065 case VCVTTPH2IUBSZrrbk:
25066 case VCVTTPH2IUBSZrrbkz:
25067 case VCVTTPH2IUBSZrrk:
25068 case VCVTTPH2IUBSZrrkz:
25069 return true;
25070 }
25071 return false;
25072}
25073
25074bool isMUL(unsigned Opcode) {
25075 switch (Opcode) {
25076 case MUL16m:
25077 case MUL16m_EVEX:
25078 case MUL16m_NF:
25079 case MUL16r:
25080 case MUL16r_EVEX:
25081 case MUL16r_NF:
25082 case MUL32m:
25083 case MUL32m_EVEX:
25084 case MUL32m_NF:
25085 case MUL32r:
25086 case MUL32r_EVEX:
25087 case MUL32r_NF:
25088 case MUL64m:
25089 case MUL64m_EVEX:
25090 case MUL64m_NF:
25091 case MUL64r:
25092 case MUL64r_EVEX:
25093 case MUL64r_NF:
25094 case MUL8m:
25095 case MUL8m_EVEX:
25096 case MUL8m_NF:
25097 case MUL8r:
25098 case MUL8r_EVEX:
25099 case MUL8r_NF:
25100 return true;
25101 }
25102 return false;
25103}
25104
25105bool isRCL(unsigned Opcode) {
25106 switch (Opcode) {
25107 case RCL16m1:
25108 case RCL16m1_EVEX:
25109 case RCL16m1_ND:
25110 case RCL16mCL:
25111 case RCL16mCL_EVEX:
25112 case RCL16mCL_ND:
25113 case RCL16mi:
25114 case RCL16mi_EVEX:
25115 case RCL16mi_ND:
25116 case RCL16r1:
25117 case RCL16r1_EVEX:
25118 case RCL16r1_ND:
25119 case RCL16rCL:
25120 case RCL16rCL_EVEX:
25121 case RCL16rCL_ND:
25122 case RCL16ri:
25123 case RCL16ri_EVEX:
25124 case RCL16ri_ND:
25125 case RCL32m1:
25126 case RCL32m1_EVEX:
25127 case RCL32m1_ND:
25128 case RCL32mCL:
25129 case RCL32mCL_EVEX:
25130 case RCL32mCL_ND:
25131 case RCL32mi:
25132 case RCL32mi_EVEX:
25133 case RCL32mi_ND:
25134 case RCL32r1:
25135 case RCL32r1_EVEX:
25136 case RCL32r1_ND:
25137 case RCL32rCL:
25138 case RCL32rCL_EVEX:
25139 case RCL32rCL_ND:
25140 case RCL32ri:
25141 case RCL32ri_EVEX:
25142 case RCL32ri_ND:
25143 case RCL64m1:
25144 case RCL64m1_EVEX:
25145 case RCL64m1_ND:
25146 case RCL64mCL:
25147 case RCL64mCL_EVEX:
25148 case RCL64mCL_ND:
25149 case RCL64mi:
25150 case RCL64mi_EVEX:
25151 case RCL64mi_ND:
25152 case RCL64r1:
25153 case RCL64r1_EVEX:
25154 case RCL64r1_ND:
25155 case RCL64rCL:
25156 case RCL64rCL_EVEX:
25157 case RCL64rCL_ND:
25158 case RCL64ri:
25159 case RCL64ri_EVEX:
25160 case RCL64ri_ND:
25161 case RCL8m1:
25162 case RCL8m1_EVEX:
25163 case RCL8m1_ND:
25164 case RCL8mCL:
25165 case RCL8mCL_EVEX:
25166 case RCL8mCL_ND:
25167 case RCL8mi:
25168 case RCL8mi_EVEX:
25169 case RCL8mi_ND:
25170 case RCL8r1:
25171 case RCL8r1_EVEX:
25172 case RCL8r1_ND:
25173 case RCL8rCL:
25174 case RCL8rCL_EVEX:
25175 case RCL8rCL_ND:
25176 case RCL8ri:
25177 case RCL8ri_EVEX:
25178 case RCL8ri_ND:
25179 return true;
25180 }
25181 return false;
25182}
25183
25184bool isVRCPSH(unsigned Opcode) {
25185 switch (Opcode) {
25186 case VRCPSHZrm:
25187 case VRCPSHZrmk:
25188 case VRCPSHZrmkz:
25189 case VRCPSHZrr:
25190 case VRCPSHZrrk:
25191 case VRCPSHZrrkz:
25192 return true;
25193 }
25194 return false;
25195}
25196
25197bool isPFCMPEQ(unsigned Opcode) {
25198 switch (Opcode) {
25199 case PFCMPEQrm:
25200 case PFCMPEQrr:
25201 return true;
25202 }
25203 return false;
25204}
25205
25206bool isMONITOR(unsigned Opcode) {
25207 switch (Opcode) {
25208 case MONITOR32rrr:
25209 case MONITOR64rrr:
25210 return true;
25211 }
25212 return false;
25213}
25214
25215bool isFDIVR(unsigned Opcode) {
25216 switch (Opcode) {
25217 case DIVR_F32m:
25218 case DIVR_F64m:
25219 case DIVR_FST0r:
25220 case DIVR_FrST0:
25221 return true;
25222 }
25223 return false;
25224}
25225
25226bool isPMINSD(unsigned Opcode) {
25227 switch (Opcode) {
25228 case PMINSDrm:
25229 case PMINSDrr:
25230 return true;
25231 }
25232 return false;
25233}
25234
25235bool isPFRCP(unsigned Opcode) {
25236 switch (Opcode) {
25237 case PFRCPrm:
25238 case PFRCPrr:
25239 return true;
25240 }
25241 return false;
25242}
25243
25244bool isKTESTQ(unsigned Opcode) {
25245 return Opcode == KTESTQkk;
25246}
25247
25248bool isVCVTTPD2DQ(unsigned Opcode) {
25249 switch (Opcode) {
25250 case VCVTTPD2DQYrm:
25251 case VCVTTPD2DQYrr:
25252 case VCVTTPD2DQZ128rm:
25253 case VCVTTPD2DQZ128rmb:
25254 case VCVTTPD2DQZ128rmbk:
25255 case VCVTTPD2DQZ128rmbkz:
25256 case VCVTTPD2DQZ128rmk:
25257 case VCVTTPD2DQZ128rmkz:
25258 case VCVTTPD2DQZ128rr:
25259 case VCVTTPD2DQZ128rrk:
25260 case VCVTTPD2DQZ128rrkz:
25261 case VCVTTPD2DQZ256rm:
25262 case VCVTTPD2DQZ256rmb:
25263 case VCVTTPD2DQZ256rmbk:
25264 case VCVTTPD2DQZ256rmbkz:
25265 case VCVTTPD2DQZ256rmk:
25266 case VCVTTPD2DQZ256rmkz:
25267 case VCVTTPD2DQZ256rr:
25268 case VCVTTPD2DQZ256rrk:
25269 case VCVTTPD2DQZ256rrkz:
25270 case VCVTTPD2DQZrm:
25271 case VCVTTPD2DQZrmb:
25272 case VCVTTPD2DQZrmbk:
25273 case VCVTTPD2DQZrmbkz:
25274 case VCVTTPD2DQZrmk:
25275 case VCVTTPD2DQZrmkz:
25276 case VCVTTPD2DQZrr:
25277 case VCVTTPD2DQZrrb:
25278 case VCVTTPD2DQZrrbk:
25279 case VCVTTPD2DQZrrbkz:
25280 case VCVTTPD2DQZrrk:
25281 case VCVTTPD2DQZrrkz:
25282 case VCVTTPD2DQrm:
25283 case VCVTTPD2DQrr:
25284 return true;
25285 }
25286 return false;
25287}
25288
25289bool isVSHUFF32X4(unsigned Opcode) {
25290 switch (Opcode) {
25291 case VSHUFF32X4Z256rmbi:
25292 case VSHUFF32X4Z256rmbik:
25293 case VSHUFF32X4Z256rmbikz:
25294 case VSHUFF32X4Z256rmi:
25295 case VSHUFF32X4Z256rmik:
25296 case VSHUFF32X4Z256rmikz:
25297 case VSHUFF32X4Z256rri:
25298 case VSHUFF32X4Z256rrik:
25299 case VSHUFF32X4Z256rrikz:
25300 case VSHUFF32X4Zrmbi:
25301 case VSHUFF32X4Zrmbik:
25302 case VSHUFF32X4Zrmbikz:
25303 case VSHUFF32X4Zrmi:
25304 case VSHUFF32X4Zrmik:
25305 case VSHUFF32X4Zrmikz:
25306 case VSHUFF32X4Zrri:
25307 case VSHUFF32X4Zrrik:
25308 case VSHUFF32X4Zrrikz:
25309 return true;
25310 }
25311 return false;
25312}
25313
25314bool isVPSLLVW(unsigned Opcode) {
25315 switch (Opcode) {
25316 case VPSLLVWZ128rm:
25317 case VPSLLVWZ128rmk:
25318 case VPSLLVWZ128rmkz:
25319 case VPSLLVWZ128rr:
25320 case VPSLLVWZ128rrk:
25321 case VPSLLVWZ128rrkz:
25322 case VPSLLVWZ256rm:
25323 case VPSLLVWZ256rmk:
25324 case VPSLLVWZ256rmkz:
25325 case VPSLLVWZ256rr:
25326 case VPSLLVWZ256rrk:
25327 case VPSLLVWZ256rrkz:
25328 case VPSLLVWZrm:
25329 case VPSLLVWZrmk:
25330 case VPSLLVWZrmkz:
25331 case VPSLLVWZrr:
25332 case VPSLLVWZrrk:
25333 case VPSLLVWZrrkz:
25334 return true;
25335 }
25336 return false;
25337}
25338
25339bool isTDPBSUD(unsigned Opcode) {
25340 return Opcode == TDPBSUD;
25341}
25342
25343bool isVPMINUQ(unsigned Opcode) {
25344 switch (Opcode) {
25345 case VPMINUQZ128rm:
25346 case VPMINUQZ128rmb:
25347 case VPMINUQZ128rmbk:
25348 case VPMINUQZ128rmbkz:
25349 case VPMINUQZ128rmk:
25350 case VPMINUQZ128rmkz:
25351 case VPMINUQZ128rr:
25352 case VPMINUQZ128rrk:
25353 case VPMINUQZ128rrkz:
25354 case VPMINUQZ256rm:
25355 case VPMINUQZ256rmb:
25356 case VPMINUQZ256rmbk:
25357 case VPMINUQZ256rmbkz:
25358 case VPMINUQZ256rmk:
25359 case VPMINUQZ256rmkz:
25360 case VPMINUQZ256rr:
25361 case VPMINUQZ256rrk:
25362 case VPMINUQZ256rrkz:
25363 case VPMINUQZrm:
25364 case VPMINUQZrmb:
25365 case VPMINUQZrmbk:
25366 case VPMINUQZrmbkz:
25367 case VPMINUQZrmk:
25368 case VPMINUQZrmkz:
25369 case VPMINUQZrr:
25370 case VPMINUQZrrk:
25371 case VPMINUQZrrkz:
25372 return true;
25373 }
25374 return false;
25375}
25376
25377bool isFIADD(unsigned Opcode) {
25378 switch (Opcode) {
25379 case ADD_FI16m:
25380 case ADD_FI32m:
25381 return true;
25382 }
25383 return false;
25384}
25385
25386bool isFCMOVNU(unsigned Opcode) {
25387 return Opcode == CMOVNP_F;
25388}
25389
25390bool isVHSUBPD(unsigned Opcode) {
25391 switch (Opcode) {
25392 case VHSUBPDYrm:
25393 case VHSUBPDYrr:
25394 case VHSUBPDrm:
25395 case VHSUBPDrr:
25396 return true;
25397 }
25398 return false;
25399}
25400
25401bool isKSHIFTRQ(unsigned Opcode) {
25402 return Opcode == KSHIFTRQki;
25403}
25404
25405bool isMOVUPS(unsigned Opcode) {
25406 switch (Opcode) {
25407 case MOVUPSmr:
25408 case MOVUPSrm:
25409 case MOVUPSrr:
25410 case MOVUPSrr_REV:
25411 return true;
25412 }
25413 return false;
25414}
25415
25416bool isVMCALL(unsigned Opcode) {
25417 return Opcode == VMCALL;
25418}
25419
25420bool isXADD(unsigned Opcode) {
25421 switch (Opcode) {
25422 case XADD16rm:
25423 case XADD16rr:
25424 case XADD32rm:
25425 case XADD32rr:
25426 case XADD64rm:
25427 case XADD64rr:
25428 case XADD8rm:
25429 case XADD8rr:
25430 return true;
25431 }
25432 return false;
25433}
25434
25435bool isXRSTOR(unsigned Opcode) {
25436 return Opcode == XRSTOR;
25437}
25438
25439bool isVGATHERPF1DPD(unsigned Opcode) {
25440 return Opcode == VGATHERPF1DPDm;
25441}
25442
25443bool isRCR(unsigned Opcode) {
25444 switch (Opcode) {
25445 case RCR16m1:
25446 case RCR16m1_EVEX:
25447 case RCR16m1_ND:
25448 case RCR16mCL:
25449 case RCR16mCL_EVEX:
25450 case RCR16mCL_ND:
25451 case RCR16mi:
25452 case RCR16mi_EVEX:
25453 case RCR16mi_ND:
25454 case RCR16r1:
25455 case RCR16r1_EVEX:
25456 case RCR16r1_ND:
25457 case RCR16rCL:
25458 case RCR16rCL_EVEX:
25459 case RCR16rCL_ND:
25460 case RCR16ri:
25461 case RCR16ri_EVEX:
25462 case RCR16ri_ND:
25463 case RCR32m1:
25464 case RCR32m1_EVEX:
25465 case RCR32m1_ND:
25466 case RCR32mCL:
25467 case RCR32mCL_EVEX:
25468 case RCR32mCL_ND:
25469 case RCR32mi:
25470 case RCR32mi_EVEX:
25471 case RCR32mi_ND:
25472 case RCR32r1:
25473 case RCR32r1_EVEX:
25474 case RCR32r1_ND:
25475 case RCR32rCL:
25476 case RCR32rCL_EVEX:
25477 case RCR32rCL_ND:
25478 case RCR32ri:
25479 case RCR32ri_EVEX:
25480 case RCR32ri_ND:
25481 case RCR64m1:
25482 case RCR64m1_EVEX:
25483 case RCR64m1_ND:
25484 case RCR64mCL:
25485 case RCR64mCL_EVEX:
25486 case RCR64mCL_ND:
25487 case RCR64mi:
25488 case RCR64mi_EVEX:
25489 case RCR64mi_ND:
25490 case RCR64r1:
25491 case RCR64r1_EVEX:
25492 case RCR64r1_ND:
25493 case RCR64rCL:
25494 case RCR64rCL_EVEX:
25495 case RCR64rCL_ND:
25496 case RCR64ri:
25497 case RCR64ri_EVEX:
25498 case RCR64ri_ND:
25499 case RCR8m1:
25500 case RCR8m1_EVEX:
25501 case RCR8m1_ND:
25502 case RCR8mCL:
25503 case RCR8mCL_EVEX:
25504 case RCR8mCL_ND:
25505 case RCR8mi:
25506 case RCR8mi_EVEX:
25507 case RCR8mi_ND:
25508 case RCR8r1:
25509 case RCR8r1_EVEX:
25510 case RCR8r1_ND:
25511 case RCR8rCL:
25512 case RCR8rCL_EVEX:
25513 case RCR8rCL_ND:
25514 case RCR8ri:
25515 case RCR8ri_EVEX:
25516 case RCR8ri_ND:
25517 return true;
25518 }
25519 return false;
25520}
25521
25522bool isFNSTCW(unsigned Opcode) {
25523 return Opcode == FNSTCW16m;
25524}
25525
25526bool isVPMOVSDW(unsigned Opcode) {
25527 switch (Opcode) {
25528 case VPMOVSDWZ128mr:
25529 case VPMOVSDWZ128mrk:
25530 case VPMOVSDWZ128rr:
25531 case VPMOVSDWZ128rrk:
25532 case VPMOVSDWZ128rrkz:
25533 case VPMOVSDWZ256mr:
25534 case VPMOVSDWZ256mrk:
25535 case VPMOVSDWZ256rr:
25536 case VPMOVSDWZ256rrk:
25537 case VPMOVSDWZ256rrkz:
25538 case VPMOVSDWZmr:
25539 case VPMOVSDWZmrk:
25540 case VPMOVSDWZrr:
25541 case VPMOVSDWZrrk:
25542 case VPMOVSDWZrrkz:
25543 return true;
25544 }
25545 return false;
25546}
25547
25548bool isVFMSUB132SH(unsigned Opcode) {
25549 switch (Opcode) {
25550 case VFMSUB132SHZm_Int:
25551 case VFMSUB132SHZmk_Int:
25552 case VFMSUB132SHZmkz_Int:
25553 case VFMSUB132SHZr_Int:
25554 case VFMSUB132SHZrb_Int:
25555 case VFMSUB132SHZrbk_Int:
25556 case VFMSUB132SHZrbkz_Int:
25557 case VFMSUB132SHZrk_Int:
25558 case VFMSUB132SHZrkz_Int:
25559 return true;
25560 }
25561 return false;
25562}
25563
25564bool isVPCONFLICTQ(unsigned Opcode) {
25565 switch (Opcode) {
25566 case VPCONFLICTQZ128rm:
25567 case VPCONFLICTQZ128rmb:
25568 case VPCONFLICTQZ128rmbk:
25569 case VPCONFLICTQZ128rmbkz:
25570 case VPCONFLICTQZ128rmk:
25571 case VPCONFLICTQZ128rmkz:
25572 case VPCONFLICTQZ128rr:
25573 case VPCONFLICTQZ128rrk:
25574 case VPCONFLICTQZ128rrkz:
25575 case VPCONFLICTQZ256rm:
25576 case VPCONFLICTQZ256rmb:
25577 case VPCONFLICTQZ256rmbk:
25578 case VPCONFLICTQZ256rmbkz:
25579 case VPCONFLICTQZ256rmk:
25580 case VPCONFLICTQZ256rmkz:
25581 case VPCONFLICTQZ256rr:
25582 case VPCONFLICTQZ256rrk:
25583 case VPCONFLICTQZ256rrkz:
25584 case VPCONFLICTQZrm:
25585 case VPCONFLICTQZrmb:
25586 case VPCONFLICTQZrmbk:
25587 case VPCONFLICTQZrmbkz:
25588 case VPCONFLICTQZrmk:
25589 case VPCONFLICTQZrmkz:
25590 case VPCONFLICTQZrr:
25591 case VPCONFLICTQZrrk:
25592 case VPCONFLICTQZrrkz:
25593 return true;
25594 }
25595 return false;
25596}
25597
25598bool isSWAPGS(unsigned Opcode) {
25599 return Opcode == SWAPGS;
25600}
25601
25602bool isVPMOVQ2M(unsigned Opcode) {
25603 switch (Opcode) {
25604 case VPMOVQ2MZ128kr:
25605 case VPMOVQ2MZ256kr:
25606 case VPMOVQ2MZkr:
25607 return true;
25608 }
25609 return false;
25610}
25611
25612bool isVPSRAVW(unsigned Opcode) {
25613 switch (Opcode) {
25614 case VPSRAVWZ128rm:
25615 case VPSRAVWZ128rmk:
25616 case VPSRAVWZ128rmkz:
25617 case VPSRAVWZ128rr:
25618 case VPSRAVWZ128rrk:
25619 case VPSRAVWZ128rrkz:
25620 case VPSRAVWZ256rm:
25621 case VPSRAVWZ256rmk:
25622 case VPSRAVWZ256rmkz:
25623 case VPSRAVWZ256rr:
25624 case VPSRAVWZ256rrk:
25625 case VPSRAVWZ256rrkz:
25626 case VPSRAVWZrm:
25627 case VPSRAVWZrmk:
25628 case VPSRAVWZrmkz:
25629 case VPSRAVWZrr:
25630 case VPSRAVWZrrk:
25631 case VPSRAVWZrrkz:
25632 return true;
25633 }
25634 return false;
25635}
25636
25637bool isMOVDQA(unsigned Opcode) {
25638 switch (Opcode) {
25639 case MOVDQAmr:
25640 case MOVDQArm:
25641 case MOVDQArr:
25642 case MOVDQArr_REV:
25643 return true;
25644 }
25645 return false;
25646}
25647
25648bool isDIVSD(unsigned Opcode) {
25649 switch (Opcode) {
25650 case DIVSDrm_Int:
25651 case DIVSDrr_Int:
25652 return true;
25653 }
25654 return false;
25655}
25656
25657bool isPCMPGTB(unsigned Opcode) {
25658 switch (Opcode) {
25659 case MMX_PCMPGTBrm:
25660 case MMX_PCMPGTBrr:
25661 case PCMPGTBrm:
25662 case PCMPGTBrr:
25663 return true;
25664 }
25665 return false;
25666}
25667
25668bool isSHA256MSG2(unsigned Opcode) {
25669 switch (Opcode) {
25670 case SHA256MSG2rm:
25671 case SHA256MSG2rr:
25672 return true;
25673 }
25674 return false;
25675}
25676
25677bool isKXORW(unsigned Opcode) {
25678 return Opcode == KXORWkk;
25679}
25680
25681bool isLIDTW(unsigned Opcode) {
25682 return Opcode == LIDT16m;
25683}
25684
25685bool isPMULHW(unsigned Opcode) {
25686 switch (Opcode) {
25687 case MMX_PMULHWrm:
25688 case MMX_PMULHWrr:
25689 case PMULHWrm:
25690 case PMULHWrr:
25691 return true;
25692 }
25693 return false;
25694}
25695
25696bool isVAESENCLAST(unsigned Opcode) {
25697 switch (Opcode) {
25698 case VAESENCLASTYrm:
25699 case VAESENCLASTYrr:
25700 case VAESENCLASTZ128rm:
25701 case VAESENCLASTZ128rr:
25702 case VAESENCLASTZ256rm:
25703 case VAESENCLASTZ256rr:
25704 case VAESENCLASTZrm:
25705 case VAESENCLASTZrr:
25706 case VAESENCLASTrm:
25707 case VAESENCLASTrr:
25708 return true;
25709 }
25710 return false;
25711}
25712
25713bool isVINSERTI32X8(unsigned Opcode) {
25714 switch (Opcode) {
25715 case VINSERTI32X8Zrmi:
25716 case VINSERTI32X8Zrmik:
25717 case VINSERTI32X8Zrmikz:
25718 case VINSERTI32X8Zrri:
25719 case VINSERTI32X8Zrrik:
25720 case VINSERTI32X8Zrrikz:
25721 return true;
25722 }
25723 return false;
25724}
25725
25726bool isVRCPPS(unsigned Opcode) {
25727 switch (Opcode) {
25728 case VRCPPSYm:
25729 case VRCPPSYr:
25730 case VRCPPSm:
25731 case VRCPPSr:
25732 return true;
25733 }
25734 return false;
25735}
25736
25737bool isVRSQRTBF16(unsigned Opcode) {
25738 switch (Opcode) {
25739 case VRSQRTBF16Z128m:
25740 case VRSQRTBF16Z128mb:
25741 case VRSQRTBF16Z128mbk:
25742 case VRSQRTBF16Z128mbkz:
25743 case VRSQRTBF16Z128mk:
25744 case VRSQRTBF16Z128mkz:
25745 case VRSQRTBF16Z128r:
25746 case VRSQRTBF16Z128rk:
25747 case VRSQRTBF16Z128rkz:
25748 case VRSQRTBF16Z256m:
25749 case VRSQRTBF16Z256mb:
25750 case VRSQRTBF16Z256mbk:
25751 case VRSQRTBF16Z256mbkz:
25752 case VRSQRTBF16Z256mk:
25753 case VRSQRTBF16Z256mkz:
25754 case VRSQRTBF16Z256r:
25755 case VRSQRTBF16Z256rk:
25756 case VRSQRTBF16Z256rkz:
25757 case VRSQRTBF16Zm:
25758 case VRSQRTBF16Zmb:
25759 case VRSQRTBF16Zmbk:
25760 case VRSQRTBF16Zmbkz:
25761 case VRSQRTBF16Zmk:
25762 case VRSQRTBF16Zmkz:
25763 case VRSQRTBF16Zr:
25764 case VRSQRTBF16Zrk:
25765 case VRSQRTBF16Zrkz:
25766 return true;
25767 }
25768 return false;
25769}
25770
25771bool isVGATHERQPS(unsigned Opcode) {
25772 switch (Opcode) {
25773 case VGATHERQPSYrm:
25774 case VGATHERQPSZ128rm:
25775 case VGATHERQPSZ256rm:
25776 case VGATHERQPSZrm:
25777 case VGATHERQPSrm:
25778 return true;
25779 }
25780 return false;
25781}
25782
25783bool isCTESTCC(unsigned Opcode) {
25784 switch (Opcode) {
25785 case CTEST16mi:
25786 case CTEST16mr:
25787 case CTEST16ri:
25788 case CTEST16rr:
25789 case CTEST32mi:
25790 case CTEST32mr:
25791 case CTEST32ri:
25792 case CTEST32rr:
25793 case CTEST64mi32:
25794 case CTEST64mr:
25795 case CTEST64ri32:
25796 case CTEST64rr:
25797 case CTEST8mi:
25798 case CTEST8mr:
25799 case CTEST8ri:
25800 case CTEST8rr:
25801 return true;
25802 }
25803 return false;
25804}
25805
25806bool isPMADDWD(unsigned Opcode) {
25807 switch (Opcode) {
25808 case MMX_PMADDWDrm:
25809 case MMX_PMADDWDrr:
25810 case PMADDWDrm:
25811 case PMADDWDrr:
25812 return true;
25813 }
25814 return false;
25815}
25816
25817bool isUCOMISS(unsigned Opcode) {
25818 switch (Opcode) {
25819 case UCOMISSrm:
25820 case UCOMISSrr:
25821 return true;
25822 }
25823 return false;
25824}
25825
25826bool isXGETBV(unsigned Opcode) {
25827 return Opcode == XGETBV;
25828}
25829
25830bool isVCVTPD2QQ(unsigned Opcode) {
25831 switch (Opcode) {
25832 case VCVTPD2QQZ128rm:
25833 case VCVTPD2QQZ128rmb:
25834 case VCVTPD2QQZ128rmbk:
25835 case VCVTPD2QQZ128rmbkz:
25836 case VCVTPD2QQZ128rmk:
25837 case VCVTPD2QQZ128rmkz:
25838 case VCVTPD2QQZ128rr:
25839 case VCVTPD2QQZ128rrk:
25840 case VCVTPD2QQZ128rrkz:
25841 case VCVTPD2QQZ256rm:
25842 case VCVTPD2QQZ256rmb:
25843 case VCVTPD2QQZ256rmbk:
25844 case VCVTPD2QQZ256rmbkz:
25845 case VCVTPD2QQZ256rmk:
25846 case VCVTPD2QQZ256rmkz:
25847 case VCVTPD2QQZ256rr:
25848 case VCVTPD2QQZ256rrk:
25849 case VCVTPD2QQZ256rrkz:
25850 case VCVTPD2QQZrm:
25851 case VCVTPD2QQZrmb:
25852 case VCVTPD2QQZrmbk:
25853 case VCVTPD2QQZrmbkz:
25854 case VCVTPD2QQZrmk:
25855 case VCVTPD2QQZrmkz:
25856 case VCVTPD2QQZrr:
25857 case VCVTPD2QQZrrb:
25858 case VCVTPD2QQZrrbk:
25859 case VCVTPD2QQZrrbkz:
25860 case VCVTPD2QQZrrk:
25861 case VCVTPD2QQZrrkz:
25862 return true;
25863 }
25864 return false;
25865}
25866
25867bool isVGETEXPPS(unsigned Opcode) {
25868 switch (Opcode) {
25869 case VGETEXPPSZ128m:
25870 case VGETEXPPSZ128mb:
25871 case VGETEXPPSZ128mbk:
25872 case VGETEXPPSZ128mbkz:
25873 case VGETEXPPSZ128mk:
25874 case VGETEXPPSZ128mkz:
25875 case VGETEXPPSZ128r:
25876 case VGETEXPPSZ128rk:
25877 case VGETEXPPSZ128rkz:
25878 case VGETEXPPSZ256m:
25879 case VGETEXPPSZ256mb:
25880 case VGETEXPPSZ256mbk:
25881 case VGETEXPPSZ256mbkz:
25882 case VGETEXPPSZ256mk:
25883 case VGETEXPPSZ256mkz:
25884 case VGETEXPPSZ256r:
25885 case VGETEXPPSZ256rk:
25886 case VGETEXPPSZ256rkz:
25887 case VGETEXPPSZm:
25888 case VGETEXPPSZmb:
25889 case VGETEXPPSZmbk:
25890 case VGETEXPPSZmbkz:
25891 case VGETEXPPSZmk:
25892 case VGETEXPPSZmkz:
25893 case VGETEXPPSZr:
25894 case VGETEXPPSZrb:
25895 case VGETEXPPSZrbk:
25896 case VGETEXPPSZrbkz:
25897 case VGETEXPPSZrk:
25898 case VGETEXPPSZrkz:
25899 return true;
25900 }
25901 return false;
25902}
25903
25904bool isFISTP(unsigned Opcode) {
25905 switch (Opcode) {
25906 case IST_FP16m:
25907 case IST_FP32m:
25908 case IST_FP64m:
25909 return true;
25910 }
25911 return false;
25912}
25913
25914bool isVINSERTF64X4(unsigned Opcode) {
25915 switch (Opcode) {
25916 case VINSERTF64X4Zrmi:
25917 case VINSERTF64X4Zrmik:
25918 case VINSERTF64X4Zrmikz:
25919 case VINSERTF64X4Zrri:
25920 case VINSERTF64X4Zrrik:
25921 case VINSERTF64X4Zrrikz:
25922 return true;
25923 }
25924 return false;
25925}
25926
25927bool isVMOVDQU16(unsigned Opcode) {
25928 switch (Opcode) {
25929 case VMOVDQU16Z128mr:
25930 case VMOVDQU16Z128mrk:
25931 case VMOVDQU16Z128rm:
25932 case VMOVDQU16Z128rmk:
25933 case VMOVDQU16Z128rmkz:
25934 case VMOVDQU16Z128rr:
25935 case VMOVDQU16Z128rr_REV:
25936 case VMOVDQU16Z128rrk:
25937 case VMOVDQU16Z128rrk_REV:
25938 case VMOVDQU16Z128rrkz:
25939 case VMOVDQU16Z128rrkz_REV:
25940 case VMOVDQU16Z256mr:
25941 case VMOVDQU16Z256mrk:
25942 case VMOVDQU16Z256rm:
25943 case VMOVDQU16Z256rmk:
25944 case VMOVDQU16Z256rmkz:
25945 case VMOVDQU16Z256rr:
25946 case VMOVDQU16Z256rr_REV:
25947 case VMOVDQU16Z256rrk:
25948 case VMOVDQU16Z256rrk_REV:
25949 case VMOVDQU16Z256rrkz:
25950 case VMOVDQU16Z256rrkz_REV:
25951 case VMOVDQU16Zmr:
25952 case VMOVDQU16Zmrk:
25953 case VMOVDQU16Zrm:
25954 case VMOVDQU16Zrmk:
25955 case VMOVDQU16Zrmkz:
25956 case VMOVDQU16Zrr:
25957 case VMOVDQU16Zrr_REV:
25958 case VMOVDQU16Zrrk:
25959 case VMOVDQU16Zrrk_REV:
25960 case VMOVDQU16Zrrkz:
25961 case VMOVDQU16Zrrkz_REV:
25962 return true;
25963 }
25964 return false;
25965}
25966
25967bool isVFMADD132PH(unsigned Opcode) {
25968 switch (Opcode) {
25969 case VFMADD132PHZ128m:
25970 case VFMADD132PHZ128mb:
25971 case VFMADD132PHZ128mbk:
25972 case VFMADD132PHZ128mbkz:
25973 case VFMADD132PHZ128mk:
25974 case VFMADD132PHZ128mkz:
25975 case VFMADD132PHZ128r:
25976 case VFMADD132PHZ128rk:
25977 case VFMADD132PHZ128rkz:
25978 case VFMADD132PHZ256m:
25979 case VFMADD132PHZ256mb:
25980 case VFMADD132PHZ256mbk:
25981 case VFMADD132PHZ256mbkz:
25982 case VFMADD132PHZ256mk:
25983 case VFMADD132PHZ256mkz:
25984 case VFMADD132PHZ256r:
25985 case VFMADD132PHZ256rk:
25986 case VFMADD132PHZ256rkz:
25987 case VFMADD132PHZm:
25988 case VFMADD132PHZmb:
25989 case VFMADD132PHZmbk:
25990 case VFMADD132PHZmbkz:
25991 case VFMADD132PHZmk:
25992 case VFMADD132PHZmkz:
25993 case VFMADD132PHZr:
25994 case VFMADD132PHZrb:
25995 case VFMADD132PHZrbk:
25996 case VFMADD132PHZrbkz:
25997 case VFMADD132PHZrk:
25998 case VFMADD132PHZrkz:
25999 return true;
26000 }
26001 return false;
26002}
26003
26004bool isVFMSUBADD213PS(unsigned Opcode) {
26005 switch (Opcode) {
26006 case VFMSUBADD213PSYm:
26007 case VFMSUBADD213PSYr:
26008 case VFMSUBADD213PSZ128m:
26009 case VFMSUBADD213PSZ128mb:
26010 case VFMSUBADD213PSZ128mbk:
26011 case VFMSUBADD213PSZ128mbkz:
26012 case VFMSUBADD213PSZ128mk:
26013 case VFMSUBADD213PSZ128mkz:
26014 case VFMSUBADD213PSZ128r:
26015 case VFMSUBADD213PSZ128rk:
26016 case VFMSUBADD213PSZ128rkz:
26017 case VFMSUBADD213PSZ256m:
26018 case VFMSUBADD213PSZ256mb:
26019 case VFMSUBADD213PSZ256mbk:
26020 case VFMSUBADD213PSZ256mbkz:
26021 case VFMSUBADD213PSZ256mk:
26022 case VFMSUBADD213PSZ256mkz:
26023 case VFMSUBADD213PSZ256r:
26024 case VFMSUBADD213PSZ256rk:
26025 case VFMSUBADD213PSZ256rkz:
26026 case VFMSUBADD213PSZm:
26027 case VFMSUBADD213PSZmb:
26028 case VFMSUBADD213PSZmbk:
26029 case VFMSUBADD213PSZmbkz:
26030 case VFMSUBADD213PSZmk:
26031 case VFMSUBADD213PSZmkz:
26032 case VFMSUBADD213PSZr:
26033 case VFMSUBADD213PSZrb:
26034 case VFMSUBADD213PSZrbk:
26035 case VFMSUBADD213PSZrbkz:
26036 case VFMSUBADD213PSZrk:
26037 case VFMSUBADD213PSZrkz:
26038 case VFMSUBADD213PSm:
26039 case VFMSUBADD213PSr:
26040 return true;
26041 }
26042 return false;
26043}
26044
26045bool isVMOVDQU32(unsigned Opcode) {
26046 switch (Opcode) {
26047 case VMOVDQU32Z128mr:
26048 case VMOVDQU32Z128mrk:
26049 case VMOVDQU32Z128rm:
26050 case VMOVDQU32Z128rmk:
26051 case VMOVDQU32Z128rmkz:
26052 case VMOVDQU32Z128rr:
26053 case VMOVDQU32Z128rr_REV:
26054 case VMOVDQU32Z128rrk:
26055 case VMOVDQU32Z128rrk_REV:
26056 case VMOVDQU32Z128rrkz:
26057 case VMOVDQU32Z128rrkz_REV:
26058 case VMOVDQU32Z256mr:
26059 case VMOVDQU32Z256mrk:
26060 case VMOVDQU32Z256rm:
26061 case VMOVDQU32Z256rmk:
26062 case VMOVDQU32Z256rmkz:
26063 case VMOVDQU32Z256rr:
26064 case VMOVDQU32Z256rr_REV:
26065 case VMOVDQU32Z256rrk:
26066 case VMOVDQU32Z256rrk_REV:
26067 case VMOVDQU32Z256rrkz:
26068 case VMOVDQU32Z256rrkz_REV:
26069 case VMOVDQU32Zmr:
26070 case VMOVDQU32Zmrk:
26071 case VMOVDQU32Zrm:
26072 case VMOVDQU32Zrmk:
26073 case VMOVDQU32Zrmkz:
26074 case VMOVDQU32Zrr:
26075 case VMOVDQU32Zrr_REV:
26076 case VMOVDQU32Zrrk:
26077 case VMOVDQU32Zrrk_REV:
26078 case VMOVDQU32Zrrkz:
26079 case VMOVDQU32Zrrkz_REV:
26080 return true;
26081 }
26082 return false;
26083}
26084
26085bool isFUCOM(unsigned Opcode) {
26086 return Opcode == UCOM_Fr;
26087}
26088
26089bool isVFNMADD213BF16(unsigned Opcode) {
26090 switch (Opcode) {
26091 case VFNMADD213BF16Z128m:
26092 case VFNMADD213BF16Z128mb:
26093 case VFNMADD213BF16Z128mbk:
26094 case VFNMADD213BF16Z128mbkz:
26095 case VFNMADD213BF16Z128mk:
26096 case VFNMADD213BF16Z128mkz:
26097 case VFNMADD213BF16Z128r:
26098 case VFNMADD213BF16Z128rk:
26099 case VFNMADD213BF16Z128rkz:
26100 case VFNMADD213BF16Z256m:
26101 case VFNMADD213BF16Z256mb:
26102 case VFNMADD213BF16Z256mbk:
26103 case VFNMADD213BF16Z256mbkz:
26104 case VFNMADD213BF16Z256mk:
26105 case VFNMADD213BF16Z256mkz:
26106 case VFNMADD213BF16Z256r:
26107 case VFNMADD213BF16Z256rk:
26108 case VFNMADD213BF16Z256rkz:
26109 case VFNMADD213BF16Zm:
26110 case VFNMADD213BF16Zmb:
26111 case VFNMADD213BF16Zmbk:
26112 case VFNMADD213BF16Zmbkz:
26113 case VFNMADD213BF16Zmk:
26114 case VFNMADD213BF16Zmkz:
26115 case VFNMADD213BF16Zr:
26116 case VFNMADD213BF16Zrk:
26117 case VFNMADD213BF16Zrkz:
26118 return true;
26119 }
26120 return false;
26121}
26122
26123bool isHADDPS(unsigned Opcode) {
26124 switch (Opcode) {
26125 case HADDPSrm:
26126 case HADDPSrr:
26127 return true;
26128 }
26129 return false;
26130}
26131
26132bool isCMP(unsigned Opcode) {
26133 switch (Opcode) {
26134 case CMP16i16:
26135 case CMP16mi:
26136 case CMP16mi8:
26137 case CMP16mr:
26138 case CMP16ri:
26139 case CMP16ri8:
26140 case CMP16rm:
26141 case CMP16rr:
26142 case CMP16rr_REV:
26143 case CMP32i32:
26144 case CMP32mi:
26145 case CMP32mi8:
26146 case CMP32mr:
26147 case CMP32ri:
26148 case CMP32ri8:
26149 case CMP32rm:
26150 case CMP32rr:
26151 case CMP32rr_REV:
26152 case CMP64i32:
26153 case CMP64mi32:
26154 case CMP64mi8:
26155 case CMP64mr:
26156 case CMP64ri32:
26157 case CMP64ri8:
26158 case CMP64rm:
26159 case CMP64rr:
26160 case CMP64rr_REV:
26161 case CMP8i8:
26162 case CMP8mi:
26163 case CMP8mi8:
26164 case CMP8mr:
26165 case CMP8ri:
26166 case CMP8ri8:
26167 case CMP8rm:
26168 case CMP8rr:
26169 case CMP8rr_REV:
26170 return true;
26171 }
26172 return false;
26173}
26174
26175bool isCVTTPS2PI(unsigned Opcode) {
26176 switch (Opcode) {
26177 case MMX_CVTTPS2PIrm:
26178 case MMX_CVTTPS2PIrr:
26179 return true;
26180 }
26181 return false;
26182}
26183
26184bool isIRETQ(unsigned Opcode) {
26185 return Opcode == IRET64;
26186}
26187
26188bool isPF2IW(unsigned Opcode) {
26189 switch (Opcode) {
26190 case PF2IWrm:
26191 case PF2IWrr:
26192 return true;
26193 }
26194 return false;
26195}
26196
26197bool isPSHUFD(unsigned Opcode) {
26198 switch (Opcode) {
26199 case PSHUFDmi:
26200 case PSHUFDri:
26201 return true;
26202 }
26203 return false;
26204}
26205
26206bool isVDPPD(unsigned Opcode) {
26207 switch (Opcode) {
26208 case VDPPDrmi:
26209 case VDPPDrri:
26210 return true;
26211 }
26212 return false;
26213}
26214
26215bool isPSHUFHW(unsigned Opcode) {
26216 switch (Opcode) {
26217 case PSHUFHWmi:
26218 case PSHUFHWri:
26219 return true;
26220 }
26221 return false;
26222}
26223
26224bool isRMPADJUST(unsigned Opcode) {
26225 return Opcode == RMPADJUST;
26226}
26227
26228bool isPI2FW(unsigned Opcode) {
26229 switch (Opcode) {
26230 case PI2FWrm:
26231 case PI2FWrr:
26232 return true;
26233 }
26234 return false;
26235}
26236
26237bool isVCVTTPH2QQ(unsigned Opcode) {
26238 switch (Opcode) {
26239 case VCVTTPH2QQZ128rm:
26240 case VCVTTPH2QQZ128rmb:
26241 case VCVTTPH2QQZ128rmbk:
26242 case VCVTTPH2QQZ128rmbkz:
26243 case VCVTTPH2QQZ128rmk:
26244 case VCVTTPH2QQZ128rmkz:
26245 case VCVTTPH2QQZ128rr:
26246 case VCVTTPH2QQZ128rrk:
26247 case VCVTTPH2QQZ128rrkz:
26248 case VCVTTPH2QQZ256rm:
26249 case VCVTTPH2QQZ256rmb:
26250 case VCVTTPH2QQZ256rmbk:
26251 case VCVTTPH2QQZ256rmbkz:
26252 case VCVTTPH2QQZ256rmk:
26253 case VCVTTPH2QQZ256rmkz:
26254 case VCVTTPH2QQZ256rr:
26255 case VCVTTPH2QQZ256rrk:
26256 case VCVTTPH2QQZ256rrkz:
26257 case VCVTTPH2QQZrm:
26258 case VCVTTPH2QQZrmb:
26259 case VCVTTPH2QQZrmbk:
26260 case VCVTTPH2QQZrmbkz:
26261 case VCVTTPH2QQZrmk:
26262 case VCVTTPH2QQZrmkz:
26263 case VCVTTPH2QQZrr:
26264 case VCVTTPH2QQZrrb:
26265 case VCVTTPH2QQZrrbk:
26266 case VCVTTPH2QQZrrbkz:
26267 case VCVTTPH2QQZrrk:
26268 case VCVTTPH2QQZrrkz:
26269 return true;
26270 }
26271 return false;
26272}
26273
26274bool isDIVPD(unsigned Opcode) {
26275 switch (Opcode) {
26276 case DIVPDrm:
26277 case DIVPDrr:
26278 return true;
26279 }
26280 return false;
26281}
26282
26283bool isCLFLUSH(unsigned Opcode) {
26284 return Opcode == CLFLUSH;
26285}
26286
26287bool isVPMINUW(unsigned Opcode) {
26288 switch (Opcode) {
26289 case VPMINUWYrm:
26290 case VPMINUWYrr:
26291 case VPMINUWZ128rm:
26292 case VPMINUWZ128rmk:
26293 case VPMINUWZ128rmkz:
26294 case VPMINUWZ128rr:
26295 case VPMINUWZ128rrk:
26296 case VPMINUWZ128rrkz:
26297 case VPMINUWZ256rm:
26298 case VPMINUWZ256rmk:
26299 case VPMINUWZ256rmkz:
26300 case VPMINUWZ256rr:
26301 case VPMINUWZ256rrk:
26302 case VPMINUWZ256rrkz:
26303 case VPMINUWZrm:
26304 case VPMINUWZrmk:
26305 case VPMINUWZrmkz:
26306 case VPMINUWZrr:
26307 case VPMINUWZrrk:
26308 case VPMINUWZrrkz:
26309 case VPMINUWrm:
26310 case VPMINUWrr:
26311 return true;
26312 }
26313 return false;
26314}
26315
26316bool isIN(unsigned Opcode) {
26317 switch (Opcode) {
26318 case IN16ri:
26319 case IN16rr:
26320 case IN32ri:
26321 case IN32rr:
26322 case IN8ri:
26323 case IN8rr:
26324 return true;
26325 }
26326 return false;
26327}
26328
26329bool isWRPKRU(unsigned Opcode) {
26330 return Opcode == WRPKRUr;
26331}
26332
26333bool isINSERTPS(unsigned Opcode) {
26334 switch (Opcode) {
26335 case INSERTPSrmi:
26336 case INSERTPSrri:
26337 return true;
26338 }
26339 return false;
26340}
26341
26342bool isAAM(unsigned Opcode) {
26343 return Opcode == AAM8i8;
26344}
26345
26346bool isVPHADDUDQ(unsigned Opcode) {
26347 switch (Opcode) {
26348 case VPHADDUDQrm:
26349 case VPHADDUDQrr:
26350 return true;
26351 }
26352 return false;
26353}
26354
26355bool isVSHA512MSG1(unsigned Opcode) {
26356 return Opcode == VSHA512MSG1rr;
26357}
26358
26359bool isDIVPS(unsigned Opcode) {
26360 switch (Opcode) {
26361 case DIVPSrm:
26362 case DIVPSrr:
26363 return true;
26364 }
26365 return false;
26366}
26367
26368bool isKNOTB(unsigned Opcode) {
26369 return Opcode == KNOTBkk;
26370}
26371
26372bool isBLSFILL(unsigned Opcode) {
26373 switch (Opcode) {
26374 case BLSFILL32rm:
26375 case BLSFILL32rr:
26376 case BLSFILL64rm:
26377 case BLSFILL64rr:
26378 return true;
26379 }
26380 return false;
26381}
26382
26383bool isVPCMPGTQ(unsigned Opcode) {
26384 switch (Opcode) {
26385 case VPCMPGTQYrm:
26386 case VPCMPGTQYrr:
26387 case VPCMPGTQZ128rm:
26388 case VPCMPGTQZ128rmb:
26389 case VPCMPGTQZ128rmbk:
26390 case VPCMPGTQZ128rmk:
26391 case VPCMPGTQZ128rr:
26392 case VPCMPGTQZ128rrk:
26393 case VPCMPGTQZ256rm:
26394 case VPCMPGTQZ256rmb:
26395 case VPCMPGTQZ256rmbk:
26396 case VPCMPGTQZ256rmk:
26397 case VPCMPGTQZ256rr:
26398 case VPCMPGTQZ256rrk:
26399 case VPCMPGTQZrm:
26400 case VPCMPGTQZrmb:
26401 case VPCMPGTQZrmbk:
26402 case VPCMPGTQZrmk:
26403 case VPCMPGTQZrr:
26404 case VPCMPGTQZrrk:
26405 case VPCMPGTQrm:
26406 case VPCMPGTQrr:
26407 return true;
26408 }
26409 return false;
26410}
26411
26412bool isMINSD(unsigned Opcode) {
26413 switch (Opcode) {
26414 case MINSDrm_Int:
26415 case MINSDrr_Int:
26416 return true;
26417 }
26418 return false;
26419}
26420
26421bool isFPREM(unsigned Opcode) {
26422 return Opcode == FPREM;
26423}
26424
26425bool isVPUNPCKHQDQ(unsigned Opcode) {
26426 switch (Opcode) {
26427 case VPUNPCKHQDQYrm:
26428 case VPUNPCKHQDQYrr:
26429 case VPUNPCKHQDQZ128rm:
26430 case VPUNPCKHQDQZ128rmb:
26431 case VPUNPCKHQDQZ128rmbk:
26432 case VPUNPCKHQDQZ128rmbkz:
26433 case VPUNPCKHQDQZ128rmk:
26434 case VPUNPCKHQDQZ128rmkz:
26435 case VPUNPCKHQDQZ128rr:
26436 case VPUNPCKHQDQZ128rrk:
26437 case VPUNPCKHQDQZ128rrkz:
26438 case VPUNPCKHQDQZ256rm:
26439 case VPUNPCKHQDQZ256rmb:
26440 case VPUNPCKHQDQZ256rmbk:
26441 case VPUNPCKHQDQZ256rmbkz:
26442 case VPUNPCKHQDQZ256rmk:
26443 case VPUNPCKHQDQZ256rmkz:
26444 case VPUNPCKHQDQZ256rr:
26445 case VPUNPCKHQDQZ256rrk:
26446 case VPUNPCKHQDQZ256rrkz:
26447 case VPUNPCKHQDQZrm:
26448 case VPUNPCKHQDQZrmb:
26449 case VPUNPCKHQDQZrmbk:
26450 case VPUNPCKHQDQZrmbkz:
26451 case VPUNPCKHQDQZrmk:
26452 case VPUNPCKHQDQZrmkz:
26453 case VPUNPCKHQDQZrr:
26454 case VPUNPCKHQDQZrrk:
26455 case VPUNPCKHQDQZrrkz:
26456 case VPUNPCKHQDQrm:
26457 case VPUNPCKHQDQrr:
26458 return true;
26459 }
26460 return false;
26461}
26462
26463bool isMINPD(unsigned Opcode) {
26464 switch (Opcode) {
26465 case MINPDrm:
26466 case MINPDrr:
26467 return true;
26468 }
26469 return false;
26470}
26471
26472bool isVCVTTPD2QQ(unsigned Opcode) {
26473 switch (Opcode) {
26474 case VCVTTPD2QQZ128rm:
26475 case VCVTTPD2QQZ128rmb:
26476 case VCVTTPD2QQZ128rmbk:
26477 case VCVTTPD2QQZ128rmbkz:
26478 case VCVTTPD2QQZ128rmk:
26479 case VCVTTPD2QQZ128rmkz:
26480 case VCVTTPD2QQZ128rr:
26481 case VCVTTPD2QQZ128rrk:
26482 case VCVTTPD2QQZ128rrkz:
26483 case VCVTTPD2QQZ256rm:
26484 case VCVTTPD2QQZ256rmb:
26485 case VCVTTPD2QQZ256rmbk:
26486 case VCVTTPD2QQZ256rmbkz:
26487 case VCVTTPD2QQZ256rmk:
26488 case VCVTTPD2QQZ256rmkz:
26489 case VCVTTPD2QQZ256rr:
26490 case VCVTTPD2QQZ256rrk:
26491 case VCVTTPD2QQZ256rrkz:
26492 case VCVTTPD2QQZrm:
26493 case VCVTTPD2QQZrmb:
26494 case VCVTTPD2QQZrmbk:
26495 case VCVTTPD2QQZrmbkz:
26496 case VCVTTPD2QQZrmk:
26497 case VCVTTPD2QQZrmkz:
26498 case VCVTTPD2QQZrr:
26499 case VCVTTPD2QQZrrb:
26500 case VCVTTPD2QQZrrbk:
26501 case VCVTTPD2QQZrrbkz:
26502 case VCVTTPD2QQZrrk:
26503 case VCVTTPD2QQZrrkz:
26504 return true;
26505 }
26506 return false;
26507}
26508
26509bool isVFMSUBPD(unsigned Opcode) {
26510 switch (Opcode) {
26511 case VFMSUBPD4Ymr:
26512 case VFMSUBPD4Yrm:
26513 case VFMSUBPD4Yrr:
26514 case VFMSUBPD4Yrr_REV:
26515 case VFMSUBPD4mr:
26516 case VFMSUBPD4rm:
26517 case VFMSUBPD4rr:
26518 case VFMSUBPD4rr_REV:
26519 return true;
26520 }
26521 return false;
26522}
26523
26524bool isV4FMADDSS(unsigned Opcode) {
26525 switch (Opcode) {
26526 case V4FMADDSSrm:
26527 case V4FMADDSSrmk:
26528 case V4FMADDSSrmkz:
26529 return true;
26530 }
26531 return false;
26532}
26533
26534bool isCPUID(unsigned Opcode) {
26535 return Opcode == CPUID;
26536}
26537
26538bool isSETCC(unsigned Opcode) {
26539 switch (Opcode) {
26540 case SETCCm:
26541 case SETCCm_EVEX:
26542 case SETCCr:
26543 case SETCCr_EVEX:
26544 return true;
26545 }
26546 return false;
26547}
26548
26549bool isVPDPWUUD(unsigned Opcode) {
26550 switch (Opcode) {
26551 case VPDPWUUDYrm:
26552 case VPDPWUUDYrr:
26553 case VPDPWUUDZ128rm:
26554 case VPDPWUUDZ128rmb:
26555 case VPDPWUUDZ128rmbk:
26556 case VPDPWUUDZ128rmbkz:
26557 case VPDPWUUDZ128rmk:
26558 case VPDPWUUDZ128rmkz:
26559 case VPDPWUUDZ128rr:
26560 case VPDPWUUDZ128rrk:
26561 case VPDPWUUDZ128rrkz:
26562 case VPDPWUUDZ256rm:
26563 case VPDPWUUDZ256rmb:
26564 case VPDPWUUDZ256rmbk:
26565 case VPDPWUUDZ256rmbkz:
26566 case VPDPWUUDZ256rmk:
26567 case VPDPWUUDZ256rmkz:
26568 case VPDPWUUDZ256rr:
26569 case VPDPWUUDZ256rrk:
26570 case VPDPWUUDZ256rrkz:
26571 case VPDPWUUDZrm:
26572 case VPDPWUUDZrmb:
26573 case VPDPWUUDZrmbk:
26574 case VPDPWUUDZrmbkz:
26575 case VPDPWUUDZrmk:
26576 case VPDPWUUDZrmkz:
26577 case VPDPWUUDZrr:
26578 case VPDPWUUDZrrk:
26579 case VPDPWUUDZrrkz:
26580 case VPDPWUUDrm:
26581 case VPDPWUUDrr:
26582 return true;
26583 }
26584 return false;
26585}
26586
26587bool isVCVTTPS2IUBS(unsigned Opcode) {
26588 switch (Opcode) {
26589 case VCVTTPS2IUBSZ128rm:
26590 case VCVTTPS2IUBSZ128rmb:
26591 case VCVTTPS2IUBSZ128rmbk:
26592 case VCVTTPS2IUBSZ128rmbkz:
26593 case VCVTTPS2IUBSZ128rmk:
26594 case VCVTTPS2IUBSZ128rmkz:
26595 case VCVTTPS2IUBSZ128rr:
26596 case VCVTTPS2IUBSZ128rrk:
26597 case VCVTTPS2IUBSZ128rrkz:
26598 case VCVTTPS2IUBSZ256rm:
26599 case VCVTTPS2IUBSZ256rmb:
26600 case VCVTTPS2IUBSZ256rmbk:
26601 case VCVTTPS2IUBSZ256rmbkz:
26602 case VCVTTPS2IUBSZ256rmk:
26603 case VCVTTPS2IUBSZ256rmkz:
26604 case VCVTTPS2IUBSZ256rr:
26605 case VCVTTPS2IUBSZ256rrk:
26606 case VCVTTPS2IUBSZ256rrkz:
26607 case VCVTTPS2IUBSZrm:
26608 case VCVTTPS2IUBSZrmb:
26609 case VCVTTPS2IUBSZrmbk:
26610 case VCVTTPS2IUBSZrmbkz:
26611 case VCVTTPS2IUBSZrmk:
26612 case VCVTTPS2IUBSZrmkz:
26613 case VCVTTPS2IUBSZrr:
26614 case VCVTTPS2IUBSZrrb:
26615 case VCVTTPS2IUBSZrrbk:
26616 case VCVTTPS2IUBSZrrbkz:
26617 case VCVTTPS2IUBSZrrk:
26618 case VCVTTPS2IUBSZrrkz:
26619 return true;
26620 }
26621 return false;
26622}
26623
26624bool isPMOVSXDQ(unsigned Opcode) {
26625 switch (Opcode) {
26626 case PMOVSXDQrm:
26627 case PMOVSXDQrr:
26628 return true;
26629 }
26630 return false;
26631}
26632
26633bool isMWAIT(unsigned Opcode) {
26634 return Opcode == MWAITrr;
26635}
26636
26637bool isVPEXTRB(unsigned Opcode) {
26638 switch (Opcode) {
26639 case VPEXTRBZmri:
26640 case VPEXTRBZrri:
26641 case VPEXTRBmri:
26642 case VPEXTRBrri:
26643 return true;
26644 }
26645 return false;
26646}
26647
26648bool isINVVPID(unsigned Opcode) {
26649 switch (Opcode) {
26650 case INVVPID32:
26651 case INVVPID64:
26652 case INVVPID64_EVEX:
26653 return true;
26654 }
26655 return false;
26656}
26657
26658bool isVPSHUFD(unsigned Opcode) {
26659 switch (Opcode) {
26660 case VPSHUFDYmi:
26661 case VPSHUFDYri:
26662 case VPSHUFDZ128mbi:
26663 case VPSHUFDZ128mbik:
26664 case VPSHUFDZ128mbikz:
26665 case VPSHUFDZ128mi:
26666 case VPSHUFDZ128mik:
26667 case VPSHUFDZ128mikz:
26668 case VPSHUFDZ128ri:
26669 case VPSHUFDZ128rik:
26670 case VPSHUFDZ128rikz:
26671 case VPSHUFDZ256mbi:
26672 case VPSHUFDZ256mbik:
26673 case VPSHUFDZ256mbikz:
26674 case VPSHUFDZ256mi:
26675 case VPSHUFDZ256mik:
26676 case VPSHUFDZ256mikz:
26677 case VPSHUFDZ256ri:
26678 case VPSHUFDZ256rik:
26679 case VPSHUFDZ256rikz:
26680 case VPSHUFDZmbi:
26681 case VPSHUFDZmbik:
26682 case VPSHUFDZmbikz:
26683 case VPSHUFDZmi:
26684 case VPSHUFDZmik:
26685 case VPSHUFDZmikz:
26686 case VPSHUFDZri:
26687 case VPSHUFDZrik:
26688 case VPSHUFDZrikz:
26689 case VPSHUFDmi:
26690 case VPSHUFDri:
26691 return true;
26692 }
26693 return false;
26694}
26695
26696bool isVMINBF16(unsigned Opcode) {
26697 switch (Opcode) {
26698 case VMINBF16Z128rm:
26699 case VMINBF16Z128rmb:
26700 case VMINBF16Z128rmbk:
26701 case VMINBF16Z128rmbkz:
26702 case VMINBF16Z128rmk:
26703 case VMINBF16Z128rmkz:
26704 case VMINBF16Z128rr:
26705 case VMINBF16Z128rrk:
26706 case VMINBF16Z128rrkz:
26707 case VMINBF16Z256rm:
26708 case VMINBF16Z256rmb:
26709 case VMINBF16Z256rmbk:
26710 case VMINBF16Z256rmbkz:
26711 case VMINBF16Z256rmk:
26712 case VMINBF16Z256rmkz:
26713 case VMINBF16Z256rr:
26714 case VMINBF16Z256rrk:
26715 case VMINBF16Z256rrkz:
26716 case VMINBF16Zrm:
26717 case VMINBF16Zrmb:
26718 case VMINBF16Zrmbk:
26719 case VMINBF16Zrmbkz:
26720 case VMINBF16Zrmk:
26721 case VMINBF16Zrmkz:
26722 case VMINBF16Zrr:
26723 case VMINBF16Zrrk:
26724 case VMINBF16Zrrkz:
26725 return true;
26726 }
26727 return false;
26728}
26729
26730bool isMOVLPS(unsigned Opcode) {
26731 switch (Opcode) {
26732 case MOVLPSmr:
26733 case MOVLPSrm:
26734 return true;
26735 }
26736 return false;
26737}
26738
26739bool isVBLENDMPS(unsigned Opcode) {
26740 switch (Opcode) {
26741 case VBLENDMPSZ128rm:
26742 case VBLENDMPSZ128rmb:
26743 case VBLENDMPSZ128rmbk:
26744 case VBLENDMPSZ128rmbkz:
26745 case VBLENDMPSZ128rmk:
26746 case VBLENDMPSZ128rmkz:
26747 case VBLENDMPSZ128rr:
26748 case VBLENDMPSZ128rrk:
26749 case VBLENDMPSZ128rrkz:
26750 case VBLENDMPSZ256rm:
26751 case VBLENDMPSZ256rmb:
26752 case VBLENDMPSZ256rmbk:
26753 case VBLENDMPSZ256rmbkz:
26754 case VBLENDMPSZ256rmk:
26755 case VBLENDMPSZ256rmkz:
26756 case VBLENDMPSZ256rr:
26757 case VBLENDMPSZ256rrk:
26758 case VBLENDMPSZ256rrkz:
26759 case VBLENDMPSZrm:
26760 case VBLENDMPSZrmb:
26761 case VBLENDMPSZrmbk:
26762 case VBLENDMPSZrmbkz:
26763 case VBLENDMPSZrmk:
26764 case VBLENDMPSZrmkz:
26765 case VBLENDMPSZrr:
26766 case VBLENDMPSZrrk:
26767 case VBLENDMPSZrrkz:
26768 return true;
26769 }
26770 return false;
26771}
26772
26773bool isPMULLW(unsigned Opcode) {
26774 switch (Opcode) {
26775 case MMX_PMULLWrm:
26776 case MMX_PMULLWrr:
26777 case PMULLWrm:
26778 case PMULLWrr:
26779 return true;
26780 }
26781 return false;
26782}
26783
26784bool isVCVTSH2SI(unsigned Opcode) {
26785 switch (Opcode) {
26786 case VCVTSH2SI64Zrm_Int:
26787 case VCVTSH2SI64Zrr_Int:
26788 case VCVTSH2SI64Zrrb_Int:
26789 case VCVTSH2SIZrm_Int:
26790 case VCVTSH2SIZrr_Int:
26791 case VCVTSH2SIZrrb_Int:
26792 return true;
26793 }
26794 return false;
26795}
26796
26797bool isVPMOVSXWQ(unsigned Opcode) {
26798 switch (Opcode) {
26799 case VPMOVSXWQYrm:
26800 case VPMOVSXWQYrr:
26801 case VPMOVSXWQZ128rm:
26802 case VPMOVSXWQZ128rmk:
26803 case VPMOVSXWQZ128rmkz:
26804 case VPMOVSXWQZ128rr:
26805 case VPMOVSXWQZ128rrk:
26806 case VPMOVSXWQZ128rrkz:
26807 case VPMOVSXWQZ256rm:
26808 case VPMOVSXWQZ256rmk:
26809 case VPMOVSXWQZ256rmkz:
26810 case VPMOVSXWQZ256rr:
26811 case VPMOVSXWQZ256rrk:
26812 case VPMOVSXWQZ256rrkz:
26813 case VPMOVSXWQZrm:
26814 case VPMOVSXWQZrmk:
26815 case VPMOVSXWQZrmkz:
26816 case VPMOVSXWQZrr:
26817 case VPMOVSXWQZrrk:
26818 case VPMOVSXWQZrrkz:
26819 case VPMOVSXWQrm:
26820 case VPMOVSXWQrr:
26821 return true;
26822 }
26823 return false;
26824}
26825
26826bool isFNSTENV(unsigned Opcode) {
26827 return Opcode == FSTENVm;
26828}
26829
26830bool isVCVT2PH2BF8(unsigned Opcode) {
26831 switch (Opcode) {
26832 case VCVT2PH2BF8Z128rm:
26833 case VCVT2PH2BF8Z128rmb:
26834 case VCVT2PH2BF8Z128rmbk:
26835 case VCVT2PH2BF8Z128rmbkz:
26836 case VCVT2PH2BF8Z128rmk:
26837 case VCVT2PH2BF8Z128rmkz:
26838 case VCVT2PH2BF8Z128rr:
26839 case VCVT2PH2BF8Z128rrk:
26840 case VCVT2PH2BF8Z128rrkz:
26841 case VCVT2PH2BF8Z256rm:
26842 case VCVT2PH2BF8Z256rmb:
26843 case VCVT2PH2BF8Z256rmbk:
26844 case VCVT2PH2BF8Z256rmbkz:
26845 case VCVT2PH2BF8Z256rmk:
26846 case VCVT2PH2BF8Z256rmkz:
26847 case VCVT2PH2BF8Z256rr:
26848 case VCVT2PH2BF8Z256rrk:
26849 case VCVT2PH2BF8Z256rrkz:
26850 case VCVT2PH2BF8Zrm:
26851 case VCVT2PH2BF8Zrmb:
26852 case VCVT2PH2BF8Zrmbk:
26853 case VCVT2PH2BF8Zrmbkz:
26854 case VCVT2PH2BF8Zrmk:
26855 case VCVT2PH2BF8Zrmkz:
26856 case VCVT2PH2BF8Zrr:
26857 case VCVT2PH2BF8Zrrk:
26858 case VCVT2PH2BF8Zrrkz:
26859 return true;
26860 }
26861 return false;
26862}
26863
26864bool isVPERMI2PD(unsigned Opcode) {
26865 switch (Opcode) {
26866 case VPERMI2PDZ128rm:
26867 case VPERMI2PDZ128rmb:
26868 case VPERMI2PDZ128rmbk:
26869 case VPERMI2PDZ128rmbkz:
26870 case VPERMI2PDZ128rmk:
26871 case VPERMI2PDZ128rmkz:
26872 case VPERMI2PDZ128rr:
26873 case VPERMI2PDZ128rrk:
26874 case VPERMI2PDZ128rrkz:
26875 case VPERMI2PDZ256rm:
26876 case VPERMI2PDZ256rmb:
26877 case VPERMI2PDZ256rmbk:
26878 case VPERMI2PDZ256rmbkz:
26879 case VPERMI2PDZ256rmk:
26880 case VPERMI2PDZ256rmkz:
26881 case VPERMI2PDZ256rr:
26882 case VPERMI2PDZ256rrk:
26883 case VPERMI2PDZ256rrkz:
26884 case VPERMI2PDZrm:
26885 case VPERMI2PDZrmb:
26886 case VPERMI2PDZrmbk:
26887 case VPERMI2PDZrmbkz:
26888 case VPERMI2PDZrmk:
26889 case VPERMI2PDZrmkz:
26890 case VPERMI2PDZrr:
26891 case VPERMI2PDZrrk:
26892 case VPERMI2PDZrrkz:
26893 return true;
26894 }
26895 return false;
26896}
26897
26898bool isMAXSS(unsigned Opcode) {
26899 switch (Opcode) {
26900 case MAXSSrm_Int:
26901 case MAXSSrr_Int:
26902 return true;
26903 }
26904 return false;
26905}
26906
26907bool isCWDE(unsigned Opcode) {
26908 return Opcode == CWDE;
26909}
26910
26911bool isVBROADCASTI32X8(unsigned Opcode) {
26912 switch (Opcode) {
26913 case VBROADCASTI32X8Zrm:
26914 case VBROADCASTI32X8Zrmk:
26915 case VBROADCASTI32X8Zrmkz:
26916 return true;
26917 }
26918 return false;
26919}
26920
26921bool isINT(unsigned Opcode) {
26922 return Opcode == INT;
26923}
26924
26925bool isENCLS(unsigned Opcode) {
26926 return Opcode == ENCLS;
26927}
26928
26929bool isMOVNTQ(unsigned Opcode) {
26930 return Opcode == MMX_MOVNTQmr;
26931}
26932
26933bool isVDIVSH(unsigned Opcode) {
26934 switch (Opcode) {
26935 case VDIVSHZrm_Int:
26936 case VDIVSHZrmk_Int:
26937 case VDIVSHZrmkz_Int:
26938 case VDIVSHZrr_Int:
26939 case VDIVSHZrrb_Int:
26940 case VDIVSHZrrbk_Int:
26941 case VDIVSHZrrbkz_Int:
26942 case VDIVSHZrrk_Int:
26943 case VDIVSHZrrkz_Int:
26944 return true;
26945 }
26946 return false;
26947}
26948
26949bool isMOVHLPS(unsigned Opcode) {
26950 return Opcode == MOVHLPSrr;
26951}
26952
26953bool isVPMASKMOVD(unsigned Opcode) {
26954 switch (Opcode) {
26955 case VPMASKMOVDYmr:
26956 case VPMASKMOVDYrm:
26957 case VPMASKMOVDmr:
26958 case VPMASKMOVDrm:
26959 return true;
26960 }
26961 return false;
26962}
26963
26964bool isVMOVSD(unsigned Opcode) {
26965 switch (Opcode) {
26966 case VMOVSDZmr:
26967 case VMOVSDZmrk:
26968 case VMOVSDZrm:
26969 case VMOVSDZrmk:
26970 case VMOVSDZrmkz:
26971 case VMOVSDZrr:
26972 case VMOVSDZrr_REV:
26973 case VMOVSDZrrk:
26974 case VMOVSDZrrk_REV:
26975 case VMOVSDZrrkz:
26976 case VMOVSDZrrkz_REV:
26977 case VMOVSDmr:
26978 case VMOVSDrm:
26979 case VMOVSDrr:
26980 case VMOVSDrr_REV:
26981 return true;
26982 }
26983 return false;
26984}
26985
26986bool isVPMINUD(unsigned Opcode) {
26987 switch (Opcode) {
26988 case VPMINUDYrm:
26989 case VPMINUDYrr:
26990 case VPMINUDZ128rm:
26991 case VPMINUDZ128rmb:
26992 case VPMINUDZ128rmbk:
26993 case VPMINUDZ128rmbkz:
26994 case VPMINUDZ128rmk:
26995 case VPMINUDZ128rmkz:
26996 case VPMINUDZ128rr:
26997 case VPMINUDZ128rrk:
26998 case VPMINUDZ128rrkz:
26999 case VPMINUDZ256rm:
27000 case VPMINUDZ256rmb:
27001 case VPMINUDZ256rmbk:
27002 case VPMINUDZ256rmbkz:
27003 case VPMINUDZ256rmk:
27004 case VPMINUDZ256rmkz:
27005 case VPMINUDZ256rr:
27006 case VPMINUDZ256rrk:
27007 case VPMINUDZ256rrkz:
27008 case VPMINUDZrm:
27009 case VPMINUDZrmb:
27010 case VPMINUDZrmbk:
27011 case VPMINUDZrmbkz:
27012 case VPMINUDZrmk:
27013 case VPMINUDZrmkz:
27014 case VPMINUDZrr:
27015 case VPMINUDZrrk:
27016 case VPMINUDZrrkz:
27017 case VPMINUDrm:
27018 case VPMINUDrr:
27019 return true;
27020 }
27021 return false;
27022}
27023
27024bool isVPCMPISTRM(unsigned Opcode) {
27025 switch (Opcode) {
27026 case VPCMPISTRMrmi:
27027 case VPCMPISTRMrri:
27028 return true;
27029 }
27030 return false;
27031}
27032
27033bool isVGETMANTSD(unsigned Opcode) {
27034 switch (Opcode) {
27035 case VGETMANTSDZrmi:
27036 case VGETMANTSDZrmik:
27037 case VGETMANTSDZrmikz:
27038 case VGETMANTSDZrri:
27039 case VGETMANTSDZrrib:
27040 case VGETMANTSDZrribk:
27041 case VGETMANTSDZrribkz:
27042 case VGETMANTSDZrrik:
27043 case VGETMANTSDZrrikz:
27044 return true;
27045 }
27046 return false;
27047}
27048
27049bool isKSHIFTRW(unsigned Opcode) {
27050 return Opcode == KSHIFTRWki;
27051}
27052
27053bool isAESDECLAST(unsigned Opcode) {
27054 switch (Opcode) {
27055 case AESDECLASTrm:
27056 case AESDECLASTrr:
27057 return true;
27058 }
27059 return false;
27060}
27061
27062bool isVFNMSUB231BF16(unsigned Opcode) {
27063 switch (Opcode) {
27064 case VFNMSUB231BF16Z128m:
27065 case VFNMSUB231BF16Z128mb:
27066 case VFNMSUB231BF16Z128mbk:
27067 case VFNMSUB231BF16Z128mbkz:
27068 case VFNMSUB231BF16Z128mk:
27069 case VFNMSUB231BF16Z128mkz:
27070 case VFNMSUB231BF16Z128r:
27071 case VFNMSUB231BF16Z128rk:
27072 case VFNMSUB231BF16Z128rkz:
27073 case VFNMSUB231BF16Z256m:
27074 case VFNMSUB231BF16Z256mb:
27075 case VFNMSUB231BF16Z256mbk:
27076 case VFNMSUB231BF16Z256mbkz:
27077 case VFNMSUB231BF16Z256mk:
27078 case VFNMSUB231BF16Z256mkz:
27079 case VFNMSUB231BF16Z256r:
27080 case VFNMSUB231BF16Z256rk:
27081 case VFNMSUB231BF16Z256rkz:
27082 case VFNMSUB231BF16Zm:
27083 case VFNMSUB231BF16Zmb:
27084 case VFNMSUB231BF16Zmbk:
27085 case VFNMSUB231BF16Zmbkz:
27086 case VFNMSUB231BF16Zmk:
27087 case VFNMSUB231BF16Zmkz:
27088 case VFNMSUB231BF16Zr:
27089 case VFNMSUB231BF16Zrk:
27090 case VFNMSUB231BF16Zrkz:
27091 return true;
27092 }
27093 return false;
27094}
27095
27096bool isVMPTRST(unsigned Opcode) {
27097 return Opcode == VMPTRSTm;
27098}
27099
27100bool isLLDT(unsigned Opcode) {
27101 switch (Opcode) {
27102 case LLDT16m:
27103 case LLDT16r:
27104 return true;
27105 }
27106 return false;
27107}
27108
27109bool isVPTESTMB(unsigned Opcode) {
27110 switch (Opcode) {
27111 case VPTESTMBZ128rm:
27112 case VPTESTMBZ128rmk:
27113 case VPTESTMBZ128rr:
27114 case VPTESTMBZ128rrk:
27115 case VPTESTMBZ256rm:
27116 case VPTESTMBZ256rmk:
27117 case VPTESTMBZ256rr:
27118 case VPTESTMBZ256rrk:
27119 case VPTESTMBZrm:
27120 case VPTESTMBZrmk:
27121 case VPTESTMBZrr:
27122 case VPTESTMBZrrk:
27123 return true;
27124 }
27125 return false;
27126}
27127
27128bool isMOVSB(unsigned Opcode) {
27129 return Opcode == MOVSB;
27130}
27131
27132bool isTILELOADD(unsigned Opcode) {
27133 switch (Opcode) {
27134 case TILELOADD:
27135 case TILELOADD_EVEX:
27136 return true;
27137 }
27138 return false;
27139}
27140
27141bool isKTESTB(unsigned Opcode) {
27142 return Opcode == KTESTBkk;
27143}
27144
27145bool isMOVUPD(unsigned Opcode) {
27146 switch (Opcode) {
27147 case MOVUPDmr:
27148 case MOVUPDrm:
27149 case MOVUPDrr:
27150 case MOVUPDrr_REV:
27151 return true;
27152 }
27153 return false;
27154}
27155
27156bool isLKGS(unsigned Opcode) {
27157 switch (Opcode) {
27158 case LKGS16m:
27159 case LKGS16r:
27160 return true;
27161 }
27162 return false;
27163}
27164
27165bool isSGDTW(unsigned Opcode) {
27166 return Opcode == SGDT16m;
27167}
27168
27169bool isDIVSS(unsigned Opcode) {
27170 switch (Opcode) {
27171 case DIVSSrm_Int:
27172 case DIVSSrr_Int:
27173 return true;
27174 }
27175 return false;
27176}
27177
27178bool isPUNPCKHQDQ(unsigned Opcode) {
27179 switch (Opcode) {
27180 case PUNPCKHQDQrm:
27181 case PUNPCKHQDQrr:
27182 return true;
27183 }
27184 return false;
27185}
27186
27187bool isVFMADD213SD(unsigned Opcode) {
27188 switch (Opcode) {
27189 case VFMADD213SDZm_Int:
27190 case VFMADD213SDZmk_Int:
27191 case VFMADD213SDZmkz_Int:
27192 case VFMADD213SDZr_Int:
27193 case VFMADD213SDZrb_Int:
27194 case VFMADD213SDZrbk_Int:
27195 case VFMADD213SDZrbkz_Int:
27196 case VFMADD213SDZrk_Int:
27197 case VFMADD213SDZrkz_Int:
27198 case VFMADD213SDm_Int:
27199 case VFMADD213SDr_Int:
27200 return true;
27201 }
27202 return false;
27203}
27204
27205bool isKXORD(unsigned Opcode) {
27206 return Opcode == KXORDkk;
27207}
27208
27209bool isVPMOVB2M(unsigned Opcode) {
27210 switch (Opcode) {
27211 case VPMOVB2MZ128kr:
27212 case VPMOVB2MZ256kr:
27213 case VPMOVB2MZkr:
27214 return true;
27215 }
27216 return false;
27217}
27218
27219bool isVMREAD(unsigned Opcode) {
27220 switch (Opcode) {
27221 case VMREAD32mr:
27222 case VMREAD32rr:
27223 case VMREAD64mr:
27224 case VMREAD64rr:
27225 return true;
27226 }
27227 return false;
27228}
27229
27230bool isVPDPWSSDS(unsigned Opcode) {
27231 switch (Opcode) {
27232 case VPDPWSSDSYrm:
27233 case VPDPWSSDSYrr:
27234 case VPDPWSSDSZ128rm:
27235 case VPDPWSSDSZ128rmb:
27236 case VPDPWSSDSZ128rmbk:
27237 case VPDPWSSDSZ128rmbkz:
27238 case VPDPWSSDSZ128rmk:
27239 case VPDPWSSDSZ128rmkz:
27240 case VPDPWSSDSZ128rr:
27241 case VPDPWSSDSZ128rrk:
27242 case VPDPWSSDSZ128rrkz:
27243 case VPDPWSSDSZ256rm:
27244 case VPDPWSSDSZ256rmb:
27245 case VPDPWSSDSZ256rmbk:
27246 case VPDPWSSDSZ256rmbkz:
27247 case VPDPWSSDSZ256rmk:
27248 case VPDPWSSDSZ256rmkz:
27249 case VPDPWSSDSZ256rr:
27250 case VPDPWSSDSZ256rrk:
27251 case VPDPWSSDSZ256rrkz:
27252 case VPDPWSSDSZrm:
27253 case VPDPWSSDSZrmb:
27254 case VPDPWSSDSZrmbk:
27255 case VPDPWSSDSZrmbkz:
27256 case VPDPWSSDSZrmk:
27257 case VPDPWSSDSZrmkz:
27258 case VPDPWSSDSZrr:
27259 case VPDPWSSDSZrrk:
27260 case VPDPWSSDSZrrkz:
27261 case VPDPWSSDSrm:
27262 case VPDPWSSDSrr:
27263 return true;
27264 }
27265 return false;
27266}
27267
27268bool isTILERELEASE(unsigned Opcode) {
27269 return Opcode == TILERELEASE;
27270}
27271
27272bool isVUCOMXSH(unsigned Opcode) {
27273 switch (Opcode) {
27274 case VUCOMXSHZrm_Int:
27275 case VUCOMXSHZrr_Int:
27276 case VUCOMXSHZrrb_Int:
27277 return true;
27278 }
27279 return false;
27280}
27281
27282bool isCLFLUSHOPT(unsigned Opcode) {
27283 return Opcode == CLFLUSHOPT;
27284}
27285
27286bool isDAS(unsigned Opcode) {
27287 return Opcode == DAS;
27288}
27289
27290bool isVSCALEFPH(unsigned Opcode) {
27291 switch (Opcode) {
27292 case VSCALEFPHZ128rm:
27293 case VSCALEFPHZ128rmb:
27294 case VSCALEFPHZ128rmbk:
27295 case VSCALEFPHZ128rmbkz:
27296 case VSCALEFPHZ128rmk:
27297 case VSCALEFPHZ128rmkz:
27298 case VSCALEFPHZ128rr:
27299 case VSCALEFPHZ128rrk:
27300 case VSCALEFPHZ128rrkz:
27301 case VSCALEFPHZ256rm:
27302 case VSCALEFPHZ256rmb:
27303 case VSCALEFPHZ256rmbk:
27304 case VSCALEFPHZ256rmbkz:
27305 case VSCALEFPHZ256rmk:
27306 case VSCALEFPHZ256rmkz:
27307 case VSCALEFPHZ256rr:
27308 case VSCALEFPHZ256rrk:
27309 case VSCALEFPHZ256rrkz:
27310 case VSCALEFPHZrm:
27311 case VSCALEFPHZrmb:
27312 case VSCALEFPHZrmbk:
27313 case VSCALEFPHZrmbkz:
27314 case VSCALEFPHZrmk:
27315 case VSCALEFPHZrmkz:
27316 case VSCALEFPHZrr:
27317 case VSCALEFPHZrrb:
27318 case VSCALEFPHZrrbk:
27319 case VSCALEFPHZrrbkz:
27320 case VSCALEFPHZrrk:
27321 case VSCALEFPHZrrkz:
27322 return true;
27323 }
27324 return false;
27325}
27326
27327bool isVSUBSD(unsigned Opcode) {
27328 switch (Opcode) {
27329 case VSUBSDZrm_Int:
27330 case VSUBSDZrmk_Int:
27331 case VSUBSDZrmkz_Int:
27332 case VSUBSDZrr_Int:
27333 case VSUBSDZrrb_Int:
27334 case VSUBSDZrrbk_Int:
27335 case VSUBSDZrrbkz_Int:
27336 case VSUBSDZrrk_Int:
27337 case VSUBSDZrrkz_Int:
27338 case VSUBSDrm_Int:
27339 case VSUBSDrr_Int:
27340 return true;
27341 }
27342 return false;
27343}
27344
27345bool isVCOMISS(unsigned Opcode) {
27346 switch (Opcode) {
27347 case VCOMISSZrm:
27348 case VCOMISSZrr:
27349 case VCOMISSZrrb:
27350 case VCOMISSrm:
27351 case VCOMISSrr:
27352 return true;
27353 }
27354 return false;
27355}
27356
27357bool isVMULBF16(unsigned Opcode) {
27358 switch (Opcode) {
27359 case VMULBF16Z128rm:
27360 case VMULBF16Z128rmb:
27361 case VMULBF16Z128rmbk:
27362 case VMULBF16Z128rmbkz:
27363 case VMULBF16Z128rmk:
27364 case VMULBF16Z128rmkz:
27365 case VMULBF16Z128rr:
27366 case VMULBF16Z128rrk:
27367 case VMULBF16Z128rrkz:
27368 case VMULBF16Z256rm:
27369 case VMULBF16Z256rmb:
27370 case VMULBF16Z256rmbk:
27371 case VMULBF16Z256rmbkz:
27372 case VMULBF16Z256rmk:
27373 case VMULBF16Z256rmkz:
27374 case VMULBF16Z256rr:
27375 case VMULBF16Z256rrk:
27376 case VMULBF16Z256rrkz:
27377 case VMULBF16Zrm:
27378 case VMULBF16Zrmb:
27379 case VMULBF16Zrmbk:
27380 case VMULBF16Zrmbkz:
27381 case VMULBF16Zrmk:
27382 case VMULBF16Zrmkz:
27383 case VMULBF16Zrr:
27384 case VMULBF16Zrrk:
27385 case VMULBF16Zrrkz:
27386 return true;
27387 }
27388 return false;
27389}
27390
27391bool isORPS(unsigned Opcode) {
27392 switch (Opcode) {
27393 case ORPSrm:
27394 case ORPSrr:
27395 return true;
27396 }
27397 return false;
27398}
27399
27400bool isTDPFP16PS(unsigned Opcode) {
27401 return Opcode == TDPFP16PS;
27402}
27403
27404bool isVMAXPD(unsigned Opcode) {
27405 switch (Opcode) {
27406 case VMAXPDYrm:
27407 case VMAXPDYrr:
27408 case VMAXPDZ128rm:
27409 case VMAXPDZ128rmb:
27410 case VMAXPDZ128rmbk:
27411 case VMAXPDZ128rmbkz:
27412 case VMAXPDZ128rmk:
27413 case VMAXPDZ128rmkz:
27414 case VMAXPDZ128rr:
27415 case VMAXPDZ128rrk:
27416 case VMAXPDZ128rrkz:
27417 case VMAXPDZ256rm:
27418 case VMAXPDZ256rmb:
27419 case VMAXPDZ256rmbk:
27420 case VMAXPDZ256rmbkz:
27421 case VMAXPDZ256rmk:
27422 case VMAXPDZ256rmkz:
27423 case VMAXPDZ256rr:
27424 case VMAXPDZ256rrk:
27425 case VMAXPDZ256rrkz:
27426 case VMAXPDZrm:
27427 case VMAXPDZrmb:
27428 case VMAXPDZrmbk:
27429 case VMAXPDZrmbkz:
27430 case VMAXPDZrmk:
27431 case VMAXPDZrmkz:
27432 case VMAXPDZrr:
27433 case VMAXPDZrrb:
27434 case VMAXPDZrrbk:
27435 case VMAXPDZrrbkz:
27436 case VMAXPDZrrk:
27437 case VMAXPDZrrkz:
27438 case VMAXPDrm:
27439 case VMAXPDrr:
27440 return true;
27441 }
27442 return false;
27443}
27444
27445bool isVPMOVWB(unsigned Opcode) {
27446 switch (Opcode) {
27447 case VPMOVWBZ128mr:
27448 case VPMOVWBZ128mrk:
27449 case VPMOVWBZ128rr:
27450 case VPMOVWBZ128rrk:
27451 case VPMOVWBZ128rrkz:
27452 case VPMOVWBZ256mr:
27453 case VPMOVWBZ256mrk:
27454 case VPMOVWBZ256rr:
27455 case VPMOVWBZ256rrk:
27456 case VPMOVWBZ256rrkz:
27457 case VPMOVWBZmr:
27458 case VPMOVWBZmrk:
27459 case VPMOVWBZrr:
27460 case VPMOVWBZrrk:
27461 case VPMOVWBZrrkz:
27462 return true;
27463 }
27464 return false;
27465}
27466
27467bool isVEXP2PS(unsigned Opcode) {
27468 switch (Opcode) {
27469 case VEXP2PSZm:
27470 case VEXP2PSZmb:
27471 case VEXP2PSZmbk:
27472 case VEXP2PSZmbkz:
27473 case VEXP2PSZmk:
27474 case VEXP2PSZmkz:
27475 case VEXP2PSZr:
27476 case VEXP2PSZrb:
27477 case VEXP2PSZrbk:
27478 case VEXP2PSZrbkz:
27479 case VEXP2PSZrk:
27480 case VEXP2PSZrkz:
27481 return true;
27482 }
27483 return false;
27484}
27485
27486bool isVPGATHERDQ(unsigned Opcode) {
27487 switch (Opcode) {
27488 case VPGATHERDQYrm:
27489 case VPGATHERDQZ128rm:
27490 case VPGATHERDQZ256rm:
27491 case VPGATHERDQZrm:
27492 case VPGATHERDQrm:
27493 return true;
27494 }
27495 return false;
27496}
27497
27498bool isVPSRAVQ(unsigned Opcode) {
27499 switch (Opcode) {
27500 case VPSRAVQZ128rm:
27501 case VPSRAVQZ128rmb:
27502 case VPSRAVQZ128rmbk:
27503 case VPSRAVQZ128rmbkz:
27504 case VPSRAVQZ128rmk:
27505 case VPSRAVQZ128rmkz:
27506 case VPSRAVQZ128rr:
27507 case VPSRAVQZ128rrk:
27508 case VPSRAVQZ128rrkz:
27509 case VPSRAVQZ256rm:
27510 case VPSRAVQZ256rmb:
27511 case VPSRAVQZ256rmbk:
27512 case VPSRAVQZ256rmbkz:
27513 case VPSRAVQZ256rmk:
27514 case VPSRAVQZ256rmkz:
27515 case VPSRAVQZ256rr:
27516 case VPSRAVQZ256rrk:
27517 case VPSRAVQZ256rrkz:
27518 case VPSRAVQZrm:
27519 case VPSRAVQZrmb:
27520 case VPSRAVQZrmbk:
27521 case VPSRAVQZrmbkz:
27522 case VPSRAVQZrmk:
27523 case VPSRAVQZrmkz:
27524 case VPSRAVQZrr:
27525 case VPSRAVQZrrk:
27526 case VPSRAVQZrrkz:
27527 return true;
27528 }
27529 return false;
27530}
27531
27532bool isPCMPISTRI(unsigned Opcode) {
27533 switch (Opcode) {
27534 case PCMPISTRIrmi:
27535 case PCMPISTRIrri:
27536 return true;
27537 }
27538 return false;
27539}
27540
27541bool isVFMSUB231PD(unsigned Opcode) {
27542 switch (Opcode) {
27543 case VFMSUB231PDYm:
27544 case VFMSUB231PDYr:
27545 case VFMSUB231PDZ128m:
27546 case VFMSUB231PDZ128mb:
27547 case VFMSUB231PDZ128mbk:
27548 case VFMSUB231PDZ128mbkz:
27549 case VFMSUB231PDZ128mk:
27550 case VFMSUB231PDZ128mkz:
27551 case VFMSUB231PDZ128r:
27552 case VFMSUB231PDZ128rk:
27553 case VFMSUB231PDZ128rkz:
27554 case VFMSUB231PDZ256m:
27555 case VFMSUB231PDZ256mb:
27556 case VFMSUB231PDZ256mbk:
27557 case VFMSUB231PDZ256mbkz:
27558 case VFMSUB231PDZ256mk:
27559 case VFMSUB231PDZ256mkz:
27560 case VFMSUB231PDZ256r:
27561 case VFMSUB231PDZ256rk:
27562 case VFMSUB231PDZ256rkz:
27563 case VFMSUB231PDZm:
27564 case VFMSUB231PDZmb:
27565 case VFMSUB231PDZmbk:
27566 case VFMSUB231PDZmbkz:
27567 case VFMSUB231PDZmk:
27568 case VFMSUB231PDZmkz:
27569 case VFMSUB231PDZr:
27570 case VFMSUB231PDZrb:
27571 case VFMSUB231PDZrbk:
27572 case VFMSUB231PDZrbkz:
27573 case VFMSUB231PDZrk:
27574 case VFMSUB231PDZrkz:
27575 case VFMSUB231PDm:
27576 case VFMSUB231PDr:
27577 return true;
27578 }
27579 return false;
27580}
27581
27582bool isRDMSR(unsigned Opcode) {
27583 switch (Opcode) {
27584 case RDMSR:
27585 case RDMSRri:
27586 case RDMSRri_EVEX:
27587 return true;
27588 }
27589 return false;
27590}
27591
27592bool isKORTESTD(unsigned Opcode) {
27593 return Opcode == KORTESTDkk;
27594}
27595
27596bool isVPBLENDMW(unsigned Opcode) {
27597 switch (Opcode) {
27598 case VPBLENDMWZ128rm:
27599 case VPBLENDMWZ128rmk:
27600 case VPBLENDMWZ128rmkz:
27601 case VPBLENDMWZ128rr:
27602 case VPBLENDMWZ128rrk:
27603 case VPBLENDMWZ128rrkz:
27604 case VPBLENDMWZ256rm:
27605 case VPBLENDMWZ256rmk:
27606 case VPBLENDMWZ256rmkz:
27607 case VPBLENDMWZ256rr:
27608 case VPBLENDMWZ256rrk:
27609 case VPBLENDMWZ256rrkz:
27610 case VPBLENDMWZrm:
27611 case VPBLENDMWZrmk:
27612 case VPBLENDMWZrmkz:
27613 case VPBLENDMWZrr:
27614 case VPBLENDMWZrrk:
27615 case VPBLENDMWZrrkz:
27616 return true;
27617 }
27618 return false;
27619}
27620
27621bool isPSHUFB(unsigned Opcode) {
27622 switch (Opcode) {
27623 case MMX_PSHUFBrm:
27624 case MMX_PSHUFBrr:
27625 case PSHUFBrm:
27626 case PSHUFBrr:
27627 return true;
27628 }
27629 return false;
27630}
27631
27632bool isVDPBF16PS(unsigned Opcode) {
27633 switch (Opcode) {
27634 case VDPBF16PSZ128m:
27635 case VDPBF16PSZ128mb:
27636 case VDPBF16PSZ128mbk:
27637 case VDPBF16PSZ128mbkz:
27638 case VDPBF16PSZ128mk:
27639 case VDPBF16PSZ128mkz:
27640 case VDPBF16PSZ128r:
27641 case VDPBF16PSZ128rk:
27642 case VDPBF16PSZ128rkz:
27643 case VDPBF16PSZ256m:
27644 case VDPBF16PSZ256mb:
27645 case VDPBF16PSZ256mbk:
27646 case VDPBF16PSZ256mbkz:
27647 case VDPBF16PSZ256mk:
27648 case VDPBF16PSZ256mkz:
27649 case VDPBF16PSZ256r:
27650 case VDPBF16PSZ256rk:
27651 case VDPBF16PSZ256rkz:
27652 case VDPBF16PSZm:
27653 case VDPBF16PSZmb:
27654 case VDPBF16PSZmbk:
27655 case VDPBF16PSZmbkz:
27656 case VDPBF16PSZmk:
27657 case VDPBF16PSZmkz:
27658 case VDPBF16PSZr:
27659 case VDPBF16PSZrk:
27660 case VDPBF16PSZrkz:
27661 return true;
27662 }
27663 return false;
27664}
27665
27666bool isTDPBF16PS(unsigned Opcode) {
27667 return Opcode == TDPBF16PS;
27668}
27669
27670bool isFCMOVE(unsigned Opcode) {
27671 return Opcode == CMOVE_F;
27672}
27673
27674bool isVFMADD231BF16(unsigned Opcode) {
27675 switch (Opcode) {
27676 case VFMADD231BF16Z128m:
27677 case VFMADD231BF16Z128mb:
27678 case VFMADD231BF16Z128mbk:
27679 case VFMADD231BF16Z128mbkz:
27680 case VFMADD231BF16Z128mk:
27681 case VFMADD231BF16Z128mkz:
27682 case VFMADD231BF16Z128r:
27683 case VFMADD231BF16Z128rk:
27684 case VFMADD231BF16Z128rkz:
27685 case VFMADD231BF16Z256m:
27686 case VFMADD231BF16Z256mb:
27687 case VFMADD231BF16Z256mbk:
27688 case VFMADD231BF16Z256mbkz:
27689 case VFMADD231BF16Z256mk:
27690 case VFMADD231BF16Z256mkz:
27691 case VFMADD231BF16Z256r:
27692 case VFMADD231BF16Z256rk:
27693 case VFMADD231BF16Z256rkz:
27694 case VFMADD231BF16Zm:
27695 case VFMADD231BF16Zmb:
27696 case VFMADD231BF16Zmbk:
27697 case VFMADD231BF16Zmbkz:
27698 case VFMADD231BF16Zmk:
27699 case VFMADD231BF16Zmkz:
27700 case VFMADD231BF16Zr:
27701 case VFMADD231BF16Zrk:
27702 case VFMADD231BF16Zrkz:
27703 return true;
27704 }
27705 return false;
27706}
27707
27708bool isCMPSS(unsigned Opcode) {
27709 switch (Opcode) {
27710 case CMPSSrmi_Int:
27711 case CMPSSrri_Int:
27712 return true;
27713 }
27714 return false;
27715}
27716
27717bool isMASKMOVDQU(unsigned Opcode) {
27718 switch (Opcode) {
27719 case MASKMOVDQU:
27720 case MASKMOVDQU64:
27721 return true;
27722 }
27723 return false;
27724}
27725
27726bool isVPDPWUSDS(unsigned Opcode) {
27727 switch (Opcode) {
27728 case VPDPWUSDSYrm:
27729 case VPDPWUSDSYrr:
27730 case VPDPWUSDSZ128rm:
27731 case VPDPWUSDSZ128rmb:
27732 case VPDPWUSDSZ128rmbk:
27733 case VPDPWUSDSZ128rmbkz:
27734 case VPDPWUSDSZ128rmk:
27735 case VPDPWUSDSZ128rmkz:
27736 case VPDPWUSDSZ128rr:
27737 case VPDPWUSDSZ128rrk:
27738 case VPDPWUSDSZ128rrkz:
27739 case VPDPWUSDSZ256rm:
27740 case VPDPWUSDSZ256rmb:
27741 case VPDPWUSDSZ256rmbk:
27742 case VPDPWUSDSZ256rmbkz:
27743 case VPDPWUSDSZ256rmk:
27744 case VPDPWUSDSZ256rmkz:
27745 case VPDPWUSDSZ256rr:
27746 case VPDPWUSDSZ256rrk:
27747 case VPDPWUSDSZ256rrkz:
27748 case VPDPWUSDSZrm:
27749 case VPDPWUSDSZrmb:
27750 case VPDPWUSDSZrmbk:
27751 case VPDPWUSDSZrmbkz:
27752 case VPDPWUSDSZrmk:
27753 case VPDPWUSDSZrmkz:
27754 case VPDPWUSDSZrr:
27755 case VPDPWUSDSZrrk:
27756 case VPDPWUSDSZrrkz:
27757 case VPDPWUSDSrm:
27758 case VPDPWUSDSrr:
27759 return true;
27760 }
27761 return false;
27762}
27763
27764bool isSARX(unsigned Opcode) {
27765 switch (Opcode) {
27766 case SARX32rm:
27767 case SARX32rm_EVEX:
27768 case SARX32rr:
27769 case SARX32rr_EVEX:
27770 case SARX64rm:
27771 case SARX64rm_EVEX:
27772 case SARX64rr:
27773 case SARX64rr_EVEX:
27774 return true;
27775 }
27776 return false;
27777}
27778
27779bool isSGDT(unsigned Opcode) {
27780 return Opcode == SGDT64m;
27781}
27782
27783bool isVFMULCPH(unsigned Opcode) {
27784 switch (Opcode) {
27785 case VFMULCPHZ128rm:
27786 case VFMULCPHZ128rmb:
27787 case VFMULCPHZ128rmbk:
27788 case VFMULCPHZ128rmbkz:
27789 case VFMULCPHZ128rmk:
27790 case VFMULCPHZ128rmkz:
27791 case VFMULCPHZ128rr:
27792 case VFMULCPHZ128rrk:
27793 case VFMULCPHZ128rrkz:
27794 case VFMULCPHZ256rm:
27795 case VFMULCPHZ256rmb:
27796 case VFMULCPHZ256rmbk:
27797 case VFMULCPHZ256rmbkz:
27798 case VFMULCPHZ256rmk:
27799 case VFMULCPHZ256rmkz:
27800 case VFMULCPHZ256rr:
27801 case VFMULCPHZ256rrk:
27802 case VFMULCPHZ256rrkz:
27803 case VFMULCPHZrm:
27804 case VFMULCPHZrmb:
27805 case VFMULCPHZrmbk:
27806 case VFMULCPHZrmbkz:
27807 case VFMULCPHZrmk:
27808 case VFMULCPHZrmkz:
27809 case VFMULCPHZrr:
27810 case VFMULCPHZrrb:
27811 case VFMULCPHZrrbk:
27812 case VFMULCPHZrrbkz:
27813 case VFMULCPHZrrk:
27814 case VFMULCPHZrrkz:
27815 return true;
27816 }
27817 return false;
27818}
27819
27820bool isURDMSR(unsigned Opcode) {
27821 switch (Opcode) {
27822 case URDMSRri:
27823 case URDMSRri_EVEX:
27824 case URDMSRrr:
27825 case URDMSRrr_EVEX:
27826 return true;
27827 }
27828 return false;
27829}
27830
27831bool isKUNPCKWD(unsigned Opcode) {
27832 return Opcode == KUNPCKWDkk;
27833}
27834
27835bool isVSCALEFBF16(unsigned Opcode) {
27836 switch (Opcode) {
27837 case VSCALEFBF16Z128rm:
27838 case VSCALEFBF16Z128rmb:
27839 case VSCALEFBF16Z128rmbk:
27840 case VSCALEFBF16Z128rmbkz:
27841 case VSCALEFBF16Z128rmk:
27842 case VSCALEFBF16Z128rmkz:
27843 case VSCALEFBF16Z128rr:
27844 case VSCALEFBF16Z128rrk:
27845 case VSCALEFBF16Z128rrkz:
27846 case VSCALEFBF16Z256rm:
27847 case VSCALEFBF16Z256rmb:
27848 case VSCALEFBF16Z256rmbk:
27849 case VSCALEFBF16Z256rmbkz:
27850 case VSCALEFBF16Z256rmk:
27851 case VSCALEFBF16Z256rmkz:
27852 case VSCALEFBF16Z256rr:
27853 case VSCALEFBF16Z256rrk:
27854 case VSCALEFBF16Z256rrkz:
27855 case VSCALEFBF16Zrm:
27856 case VSCALEFBF16Zrmb:
27857 case VSCALEFBF16Zrmbk:
27858 case VSCALEFBF16Zrmbkz:
27859 case VSCALEFBF16Zrmk:
27860 case VSCALEFBF16Zrmkz:
27861 case VSCALEFBF16Zrr:
27862 case VSCALEFBF16Zrrk:
27863 case VSCALEFBF16Zrrkz:
27864 return true;
27865 }
27866 return false;
27867}
27868
27869bool isCVTPS2PD(unsigned Opcode) {
27870 switch (Opcode) {
27871 case CVTPS2PDrm:
27872 case CVTPS2PDrr:
27873 return true;
27874 }
27875 return false;
27876}
27877
27878bool isFBSTP(unsigned Opcode) {
27879 return Opcode == FBSTPm;
27880}
27881
27882bool isPSUBQ(unsigned Opcode) {
27883 switch (Opcode) {
27884 case MMX_PSUBQrm:
27885 case MMX_PSUBQrr:
27886 case PSUBQrm:
27887 case PSUBQrr:
27888 return true;
27889 }
27890 return false;
27891}
27892
27893bool isFXSAVE64(unsigned Opcode) {
27894 return Opcode == FXSAVE64;
27895}
27896
27897bool isKMOVW(unsigned Opcode) {
27898 switch (Opcode) {
27899 case KMOVWkk:
27900 case KMOVWkk_EVEX:
27901 case KMOVWkm:
27902 case KMOVWkm_EVEX:
27903 case KMOVWkr:
27904 case KMOVWkr_EVEX:
27905 case KMOVWmk:
27906 case KMOVWmk_EVEX:
27907 case KMOVWrk:
27908 case KMOVWrk_EVEX:
27909 return true;
27910 }
27911 return false;
27912}
27913
27914bool isBTS(unsigned Opcode) {
27915 switch (Opcode) {
27916 case BTS16mi8:
27917 case BTS16mr:
27918 case BTS16ri8:
27919 case BTS16rr:
27920 case BTS32mi8:
27921 case BTS32mr:
27922 case BTS32ri8:
27923 case BTS32rr:
27924 case BTS64mi8:
27925 case BTS64mr:
27926 case BTS64ri8:
27927 case BTS64rr:
27928 return true;
27929 }
27930 return false;
27931}
27932
27933bool isVPHADDBQ(unsigned Opcode) {
27934 switch (Opcode) {
27935 case VPHADDBQrm:
27936 case VPHADDBQrr:
27937 return true;
27938 }
27939 return false;
27940}
27941
27942bool isFRSTOR(unsigned Opcode) {
27943 return Opcode == FRSTORm;
27944}
27945
27946bool isVFMSUB132PD(unsigned Opcode) {
27947 switch (Opcode) {
27948 case VFMSUB132PDYm:
27949 case VFMSUB132PDYr:
27950 case VFMSUB132PDZ128m:
27951 case VFMSUB132PDZ128mb:
27952 case VFMSUB132PDZ128mbk:
27953 case VFMSUB132PDZ128mbkz:
27954 case VFMSUB132PDZ128mk:
27955 case VFMSUB132PDZ128mkz:
27956 case VFMSUB132PDZ128r:
27957 case VFMSUB132PDZ128rk:
27958 case VFMSUB132PDZ128rkz:
27959 case VFMSUB132PDZ256m:
27960 case VFMSUB132PDZ256mb:
27961 case VFMSUB132PDZ256mbk:
27962 case VFMSUB132PDZ256mbkz:
27963 case VFMSUB132PDZ256mk:
27964 case VFMSUB132PDZ256mkz:
27965 case VFMSUB132PDZ256r:
27966 case VFMSUB132PDZ256rk:
27967 case VFMSUB132PDZ256rkz:
27968 case VFMSUB132PDZm:
27969 case VFMSUB132PDZmb:
27970 case VFMSUB132PDZmbk:
27971 case VFMSUB132PDZmbkz:
27972 case VFMSUB132PDZmk:
27973 case VFMSUB132PDZmkz:
27974 case VFMSUB132PDZr:
27975 case VFMSUB132PDZrb:
27976 case VFMSUB132PDZrbk:
27977 case VFMSUB132PDZrbkz:
27978 case VFMSUB132PDZrk:
27979 case VFMSUB132PDZrkz:
27980 case VFMSUB132PDm:
27981 case VFMSUB132PDr:
27982 return true;
27983 }
27984 return false;
27985}
27986
27987bool isPMULLD(unsigned Opcode) {
27988 switch (Opcode) {
27989 case PMULLDrm:
27990 case PMULLDrr:
27991 return true;
27992 }
27993 return false;
27994}
27995
27996bool isSHA1MSG2(unsigned Opcode) {
27997 switch (Opcode) {
27998 case SHA1MSG2rm:
27999 case SHA1MSG2rr:
28000 return true;
28001 }
28002 return false;
28003}
28004
28005bool isJECXZ(unsigned Opcode) {
28006 return Opcode == JECXZ;
28007}
28008
28009bool isVCVTUDQ2PS(unsigned Opcode) {
28010 switch (Opcode) {
28011 case VCVTUDQ2PSZ128rm:
28012 case VCVTUDQ2PSZ128rmb:
28013 case VCVTUDQ2PSZ128rmbk:
28014 case VCVTUDQ2PSZ128rmbkz:
28015 case VCVTUDQ2PSZ128rmk:
28016 case VCVTUDQ2PSZ128rmkz:
28017 case VCVTUDQ2PSZ128rr:
28018 case VCVTUDQ2PSZ128rrk:
28019 case VCVTUDQ2PSZ128rrkz:
28020 case VCVTUDQ2PSZ256rm:
28021 case VCVTUDQ2PSZ256rmb:
28022 case VCVTUDQ2PSZ256rmbk:
28023 case VCVTUDQ2PSZ256rmbkz:
28024 case VCVTUDQ2PSZ256rmk:
28025 case VCVTUDQ2PSZ256rmkz:
28026 case VCVTUDQ2PSZ256rr:
28027 case VCVTUDQ2PSZ256rrk:
28028 case VCVTUDQ2PSZ256rrkz:
28029 case VCVTUDQ2PSZrm:
28030 case VCVTUDQ2PSZrmb:
28031 case VCVTUDQ2PSZrmbk:
28032 case VCVTUDQ2PSZrmbkz:
28033 case VCVTUDQ2PSZrmk:
28034 case VCVTUDQ2PSZrmkz:
28035 case VCVTUDQ2PSZrr:
28036 case VCVTUDQ2PSZrrb:
28037 case VCVTUDQ2PSZrrbk:
28038 case VCVTUDQ2PSZrrbkz:
28039 case VCVTUDQ2PSZrrk:
28040 case VCVTUDQ2PSZrrkz:
28041 return true;
28042 }
28043 return false;
28044}
28045
28046bool isAESENC(unsigned Opcode) {
28047 switch (Opcode) {
28048 case AESENCrm:
28049 case AESENCrr:
28050 return true;
28051 }
28052 return false;
28053}
28054
28055bool isVMINMAXPS(unsigned Opcode) {
28056 switch (Opcode) {
28057 case VMINMAXPSZ128rmbi:
28058 case VMINMAXPSZ128rmbik:
28059 case VMINMAXPSZ128rmbikz:
28060 case VMINMAXPSZ128rmi:
28061 case VMINMAXPSZ128rmik:
28062 case VMINMAXPSZ128rmikz:
28063 case VMINMAXPSZ128rri:
28064 case VMINMAXPSZ128rrik:
28065 case VMINMAXPSZ128rrikz:
28066 case VMINMAXPSZ256rmbi:
28067 case VMINMAXPSZ256rmbik:
28068 case VMINMAXPSZ256rmbikz:
28069 case VMINMAXPSZ256rmi:
28070 case VMINMAXPSZ256rmik:
28071 case VMINMAXPSZ256rmikz:
28072 case VMINMAXPSZ256rri:
28073 case VMINMAXPSZ256rrik:
28074 case VMINMAXPSZ256rrikz:
28075 case VMINMAXPSZrmbi:
28076 case VMINMAXPSZrmbik:
28077 case VMINMAXPSZrmbikz:
28078 case VMINMAXPSZrmi:
28079 case VMINMAXPSZrmik:
28080 case VMINMAXPSZrmikz:
28081 case VMINMAXPSZrri:
28082 case VMINMAXPSZrrib:
28083 case VMINMAXPSZrribk:
28084 case VMINMAXPSZrribkz:
28085 case VMINMAXPSZrrik:
28086 case VMINMAXPSZrrikz:
28087 return true;
28088 }
28089 return false;
28090}
28091
28092bool isPSIGNW(unsigned Opcode) {
28093 switch (Opcode) {
28094 case MMX_PSIGNWrm:
28095 case MMX_PSIGNWrr:
28096 case PSIGNWrm:
28097 case PSIGNWrr:
28098 return true;
28099 }
28100 return false;
28101}
28102
28103bool isUNPCKLPD(unsigned Opcode) {
28104 switch (Opcode) {
28105 case UNPCKLPDrm:
28106 case UNPCKLPDrr:
28107 return true;
28108 }
28109 return false;
28110}
28111
28112bool isPUSHP(unsigned Opcode) {
28113 return Opcode == PUSHP64r;
28114}
28115
28116bool isBLSI(unsigned Opcode) {
28117 switch (Opcode) {
28118 case BLSI32rm:
28119 case BLSI32rm_EVEX:
28120 case BLSI32rm_NF:
28121 case BLSI32rr:
28122 case BLSI32rr_EVEX:
28123 case BLSI32rr_NF:
28124 case BLSI64rm:
28125 case BLSI64rm_EVEX:
28126 case BLSI64rm_NF:
28127 case BLSI64rr:
28128 case BLSI64rr_EVEX:
28129 case BLSI64rr_NF:
28130 return true;
28131 }
28132 return false;
28133}
28134
28135bool isVPTESTNMB(unsigned Opcode) {
28136 switch (Opcode) {
28137 case VPTESTNMBZ128rm:
28138 case VPTESTNMBZ128rmk:
28139 case VPTESTNMBZ128rr:
28140 case VPTESTNMBZ128rrk:
28141 case VPTESTNMBZ256rm:
28142 case VPTESTNMBZ256rmk:
28143 case VPTESTNMBZ256rr:
28144 case VPTESTNMBZ256rrk:
28145 case VPTESTNMBZrm:
28146 case VPTESTNMBZrmk:
28147 case VPTESTNMBZrr:
28148 case VPTESTNMBZrrk:
28149 return true;
28150 }
28151 return false;
28152}
28153
28154bool isWRUSSQ(unsigned Opcode) {
28155 switch (Opcode) {
28156 case WRUSSQ:
28157 case WRUSSQ_EVEX:
28158 return true;
28159 }
28160 return false;
28161}
28162
28163bool isVGF2P8MULB(unsigned Opcode) {
28164 switch (Opcode) {
28165 case VGF2P8MULBYrm:
28166 case VGF2P8MULBYrr:
28167 case VGF2P8MULBZ128rm:
28168 case VGF2P8MULBZ128rmk:
28169 case VGF2P8MULBZ128rmkz:
28170 case VGF2P8MULBZ128rr:
28171 case VGF2P8MULBZ128rrk:
28172 case VGF2P8MULBZ128rrkz:
28173 case VGF2P8MULBZ256rm:
28174 case VGF2P8MULBZ256rmk:
28175 case VGF2P8MULBZ256rmkz:
28176 case VGF2P8MULBZ256rr:
28177 case VGF2P8MULBZ256rrk:
28178 case VGF2P8MULBZ256rrkz:
28179 case VGF2P8MULBZrm:
28180 case VGF2P8MULBZrmk:
28181 case VGF2P8MULBZrmkz:
28182 case VGF2P8MULBZrr:
28183 case VGF2P8MULBZrrk:
28184 case VGF2P8MULBZrrkz:
28185 case VGF2P8MULBrm:
28186 case VGF2P8MULBrr:
28187 return true;
28188 }
28189 return false;
28190}
28191
28192bool isVPUNPCKLBW(unsigned Opcode) {
28193 switch (Opcode) {
28194 case VPUNPCKLBWYrm:
28195 case VPUNPCKLBWYrr:
28196 case VPUNPCKLBWZ128rm:
28197 case VPUNPCKLBWZ128rmk:
28198 case VPUNPCKLBWZ128rmkz:
28199 case VPUNPCKLBWZ128rr:
28200 case VPUNPCKLBWZ128rrk:
28201 case VPUNPCKLBWZ128rrkz:
28202 case VPUNPCKLBWZ256rm:
28203 case VPUNPCKLBWZ256rmk:
28204 case VPUNPCKLBWZ256rmkz:
28205 case VPUNPCKLBWZ256rr:
28206 case VPUNPCKLBWZ256rrk:
28207 case VPUNPCKLBWZ256rrkz:
28208 case VPUNPCKLBWZrm:
28209 case VPUNPCKLBWZrmk:
28210 case VPUNPCKLBWZrmkz:
28211 case VPUNPCKLBWZrr:
28212 case VPUNPCKLBWZrrk:
28213 case VPUNPCKLBWZrrkz:
28214 case VPUNPCKLBWrm:
28215 case VPUNPCKLBWrr:
28216 return true;
28217 }
28218 return false;
28219}
28220
28221bool isVRANGESD(unsigned Opcode) {
28222 switch (Opcode) {
28223 case VRANGESDZrmi:
28224 case VRANGESDZrmik:
28225 case VRANGESDZrmikz:
28226 case VRANGESDZrri:
28227 case VRANGESDZrrib:
28228 case VRANGESDZrribk:
28229 case VRANGESDZrribkz:
28230 case VRANGESDZrrik:
28231 case VRANGESDZrrikz:
28232 return true;
28233 }
28234 return false;
28235}
28236
28237bool isCLD(unsigned Opcode) {
28238 return Opcode == CLD;
28239}
28240
28241bool isVSCALEFPD(unsigned Opcode) {
28242 switch (Opcode) {
28243 case VSCALEFPDZ128rm:
28244 case VSCALEFPDZ128rmb:
28245 case VSCALEFPDZ128rmbk:
28246 case VSCALEFPDZ128rmbkz:
28247 case VSCALEFPDZ128rmk:
28248 case VSCALEFPDZ128rmkz:
28249 case VSCALEFPDZ128rr:
28250 case VSCALEFPDZ128rrk:
28251 case VSCALEFPDZ128rrkz:
28252 case VSCALEFPDZ256rm:
28253 case VSCALEFPDZ256rmb:
28254 case VSCALEFPDZ256rmbk:
28255 case VSCALEFPDZ256rmbkz:
28256 case VSCALEFPDZ256rmk:
28257 case VSCALEFPDZ256rmkz:
28258 case VSCALEFPDZ256rr:
28259 case VSCALEFPDZ256rrk:
28260 case VSCALEFPDZ256rrkz:
28261 case VSCALEFPDZrm:
28262 case VSCALEFPDZrmb:
28263 case VSCALEFPDZrmbk:
28264 case VSCALEFPDZrmbkz:
28265 case VSCALEFPDZrmk:
28266 case VSCALEFPDZrmkz:
28267 case VSCALEFPDZrr:
28268 case VSCALEFPDZrrb:
28269 case VSCALEFPDZrrbk:
28270 case VSCALEFPDZrrbkz:
28271 case VSCALEFPDZrrk:
28272 case VSCALEFPDZrrkz:
28273 return true;
28274 }
28275 return false;
28276}
28277
28278bool isVCOMXSS(unsigned Opcode) {
28279 switch (Opcode) {
28280 case VCOMXSSZrm_Int:
28281 case VCOMXSSZrr_Int:
28282 case VCOMXSSZrrb_Int:
28283 return true;
28284 }
28285 return false;
28286}
28287
28288bool isVPERMQ(unsigned Opcode) {
28289 switch (Opcode) {
28290 case VPERMQYmi:
28291 case VPERMQYri:
28292 case VPERMQZ256mbi:
28293 case VPERMQZ256mbik:
28294 case VPERMQZ256mbikz:
28295 case VPERMQZ256mi:
28296 case VPERMQZ256mik:
28297 case VPERMQZ256mikz:
28298 case VPERMQZ256ri:
28299 case VPERMQZ256rik:
28300 case VPERMQZ256rikz:
28301 case VPERMQZ256rm:
28302 case VPERMQZ256rmb:
28303 case VPERMQZ256rmbk:
28304 case VPERMQZ256rmbkz:
28305 case VPERMQZ256rmk:
28306 case VPERMQZ256rmkz:
28307 case VPERMQZ256rr:
28308 case VPERMQZ256rrk:
28309 case VPERMQZ256rrkz:
28310 case VPERMQZmbi:
28311 case VPERMQZmbik:
28312 case VPERMQZmbikz:
28313 case VPERMQZmi:
28314 case VPERMQZmik:
28315 case VPERMQZmikz:
28316 case VPERMQZri:
28317 case VPERMQZrik:
28318 case VPERMQZrikz:
28319 case VPERMQZrm:
28320 case VPERMQZrmb:
28321 case VPERMQZrmbk:
28322 case VPERMQZrmbkz:
28323 case VPERMQZrmk:
28324 case VPERMQZrmkz:
28325 case VPERMQZrr:
28326 case VPERMQZrrk:
28327 case VPERMQZrrkz:
28328 return true;
28329 }
28330 return false;
28331}
28332
28333bool isVPSHLDVW(unsigned Opcode) {
28334 switch (Opcode) {
28335 case VPSHLDVWZ128m:
28336 case VPSHLDVWZ128mk:
28337 case VPSHLDVWZ128mkz:
28338 case VPSHLDVWZ128r:
28339 case VPSHLDVWZ128rk:
28340 case VPSHLDVWZ128rkz:
28341 case VPSHLDVWZ256m:
28342 case VPSHLDVWZ256mk:
28343 case VPSHLDVWZ256mkz:
28344 case VPSHLDVWZ256r:
28345 case VPSHLDVWZ256rk:
28346 case VPSHLDVWZ256rkz:
28347 case VPSHLDVWZm:
28348 case VPSHLDVWZmk:
28349 case VPSHLDVWZmkz:
28350 case VPSHLDVWZr:
28351 case VPSHLDVWZrk:
28352 case VPSHLDVWZrkz:
28353 return true;
28354 }
28355 return false;
28356}
28357
28358bool isROR(unsigned Opcode) {
28359 switch (Opcode) {
28360 case ROR16m1:
28361 case ROR16m1_EVEX:
28362 case ROR16m1_ND:
28363 case ROR16m1_NF:
28364 case ROR16m1_NF_ND:
28365 case ROR16mCL:
28366 case ROR16mCL_EVEX:
28367 case ROR16mCL_ND:
28368 case ROR16mCL_NF:
28369 case ROR16mCL_NF_ND:
28370 case ROR16mi:
28371 case ROR16mi_EVEX:
28372 case ROR16mi_ND:
28373 case ROR16mi_NF:
28374 case ROR16mi_NF_ND:
28375 case ROR16r1:
28376 case ROR16r1_EVEX:
28377 case ROR16r1_ND:
28378 case ROR16r1_NF:
28379 case ROR16r1_NF_ND:
28380 case ROR16rCL:
28381 case ROR16rCL_EVEX:
28382 case ROR16rCL_ND:
28383 case ROR16rCL_NF:
28384 case ROR16rCL_NF_ND:
28385 case ROR16ri:
28386 case ROR16ri_EVEX:
28387 case ROR16ri_ND:
28388 case ROR16ri_NF:
28389 case ROR16ri_NF_ND:
28390 case ROR32m1:
28391 case ROR32m1_EVEX:
28392 case ROR32m1_ND:
28393 case ROR32m1_NF:
28394 case ROR32m1_NF_ND:
28395 case ROR32mCL:
28396 case ROR32mCL_EVEX:
28397 case ROR32mCL_ND:
28398 case ROR32mCL_NF:
28399 case ROR32mCL_NF_ND:
28400 case ROR32mi:
28401 case ROR32mi_EVEX:
28402 case ROR32mi_ND:
28403 case ROR32mi_NF:
28404 case ROR32mi_NF_ND:
28405 case ROR32r1:
28406 case ROR32r1_EVEX:
28407 case ROR32r1_ND:
28408 case ROR32r1_NF:
28409 case ROR32r1_NF_ND:
28410 case ROR32rCL:
28411 case ROR32rCL_EVEX:
28412 case ROR32rCL_ND:
28413 case ROR32rCL_NF:
28414 case ROR32rCL_NF_ND:
28415 case ROR32ri:
28416 case ROR32ri_EVEX:
28417 case ROR32ri_ND:
28418 case ROR32ri_NF:
28419 case ROR32ri_NF_ND:
28420 case ROR64m1:
28421 case ROR64m1_EVEX:
28422 case ROR64m1_ND:
28423 case ROR64m1_NF:
28424 case ROR64m1_NF_ND:
28425 case ROR64mCL:
28426 case ROR64mCL_EVEX:
28427 case ROR64mCL_ND:
28428 case ROR64mCL_NF:
28429 case ROR64mCL_NF_ND:
28430 case ROR64mi:
28431 case ROR64mi_EVEX:
28432 case ROR64mi_ND:
28433 case ROR64mi_NF:
28434 case ROR64mi_NF_ND:
28435 case ROR64r1:
28436 case ROR64r1_EVEX:
28437 case ROR64r1_ND:
28438 case ROR64r1_NF:
28439 case ROR64r1_NF_ND:
28440 case ROR64rCL:
28441 case ROR64rCL_EVEX:
28442 case ROR64rCL_ND:
28443 case ROR64rCL_NF:
28444 case ROR64rCL_NF_ND:
28445 case ROR64ri:
28446 case ROR64ri_EVEX:
28447 case ROR64ri_ND:
28448 case ROR64ri_NF:
28449 case ROR64ri_NF_ND:
28450 case ROR8m1:
28451 case ROR8m1_EVEX:
28452 case ROR8m1_ND:
28453 case ROR8m1_NF:
28454 case ROR8m1_NF_ND:
28455 case ROR8mCL:
28456 case ROR8mCL_EVEX:
28457 case ROR8mCL_ND:
28458 case ROR8mCL_NF:
28459 case ROR8mCL_NF_ND:
28460 case ROR8mi:
28461 case ROR8mi_EVEX:
28462 case ROR8mi_ND:
28463 case ROR8mi_NF:
28464 case ROR8mi_NF_ND:
28465 case ROR8r1:
28466 case ROR8r1_EVEX:
28467 case ROR8r1_ND:
28468 case ROR8r1_NF:
28469 case ROR8r1_NF_ND:
28470 case ROR8rCL:
28471 case ROR8rCL_EVEX:
28472 case ROR8rCL_ND:
28473 case ROR8rCL_NF:
28474 case ROR8rCL_NF_ND:
28475 case ROR8ri:
28476 case ROR8ri_EVEX:
28477 case ROR8ri_ND:
28478 case ROR8ri_NF:
28479 case ROR8ri_NF_ND:
28480 return true;
28481 }
28482 return false;
28483}
28484
28485bool isVFMADDSUB132PH(unsigned Opcode) {
28486 switch (Opcode) {
28487 case VFMADDSUB132PHZ128m:
28488 case VFMADDSUB132PHZ128mb:
28489 case VFMADDSUB132PHZ128mbk:
28490 case VFMADDSUB132PHZ128mbkz:
28491 case VFMADDSUB132PHZ128mk:
28492 case VFMADDSUB132PHZ128mkz:
28493 case VFMADDSUB132PHZ128r:
28494 case VFMADDSUB132PHZ128rk:
28495 case VFMADDSUB132PHZ128rkz:
28496 case VFMADDSUB132PHZ256m:
28497 case VFMADDSUB132PHZ256mb:
28498 case VFMADDSUB132PHZ256mbk:
28499 case VFMADDSUB132PHZ256mbkz:
28500 case VFMADDSUB132PHZ256mk:
28501 case VFMADDSUB132PHZ256mkz:
28502 case VFMADDSUB132PHZ256r:
28503 case VFMADDSUB132PHZ256rk:
28504 case VFMADDSUB132PHZ256rkz:
28505 case VFMADDSUB132PHZm:
28506 case VFMADDSUB132PHZmb:
28507 case VFMADDSUB132PHZmbk:
28508 case VFMADDSUB132PHZmbkz:
28509 case VFMADDSUB132PHZmk:
28510 case VFMADDSUB132PHZmkz:
28511 case VFMADDSUB132PHZr:
28512 case VFMADDSUB132PHZrb:
28513 case VFMADDSUB132PHZrbk:
28514 case VFMADDSUB132PHZrbkz:
28515 case VFMADDSUB132PHZrk:
28516 case VFMADDSUB132PHZrkz:
28517 return true;
28518 }
28519 return false;
28520}
28521
28522bool isDEC(unsigned Opcode) {
28523 switch (Opcode) {
28524 case DEC16m:
28525 case DEC16m_EVEX:
28526 case DEC16m_ND:
28527 case DEC16m_NF:
28528 case DEC16m_NF_ND:
28529 case DEC16r:
28530 case DEC16r_EVEX:
28531 case DEC16r_ND:
28532 case DEC16r_NF:
28533 case DEC16r_NF_ND:
28534 case DEC16r_alt:
28535 case DEC32m:
28536 case DEC32m_EVEX:
28537 case DEC32m_ND:
28538 case DEC32m_NF:
28539 case DEC32m_NF_ND:
28540 case DEC32r:
28541 case DEC32r_EVEX:
28542 case DEC32r_ND:
28543 case DEC32r_NF:
28544 case DEC32r_NF_ND:
28545 case DEC32r_alt:
28546 case DEC64m:
28547 case DEC64m_EVEX:
28548 case DEC64m_ND:
28549 case DEC64m_NF:
28550 case DEC64m_NF_ND:
28551 case DEC64r:
28552 case DEC64r_EVEX:
28553 case DEC64r_ND:
28554 case DEC64r_NF:
28555 case DEC64r_NF_ND:
28556 case DEC8m:
28557 case DEC8m_EVEX:
28558 case DEC8m_ND:
28559 case DEC8m_NF:
28560 case DEC8m_NF_ND:
28561 case DEC8r:
28562 case DEC8r_EVEX:
28563 case DEC8r_ND:
28564 case DEC8r_NF:
28565 case DEC8r_NF_ND:
28566 return true;
28567 }
28568 return false;
28569}
28570
28571bool isVGETEXPSH(unsigned Opcode) {
28572 switch (Opcode) {
28573 case VGETEXPSHZm:
28574 case VGETEXPSHZmk:
28575 case VGETEXPSHZmkz:
28576 case VGETEXPSHZr:
28577 case VGETEXPSHZrb:
28578 case VGETEXPSHZrbk:
28579 case VGETEXPSHZrbkz:
28580 case VGETEXPSHZrk:
28581 case VGETEXPSHZrkz:
28582 return true;
28583 }
28584 return false;
28585}
28586
28587bool isAESDEC(unsigned Opcode) {
28588 switch (Opcode) {
28589 case AESDECrm:
28590 case AESDECrr:
28591 return true;
28592 }
28593 return false;
28594}
28595
28596bool isKORD(unsigned Opcode) {
28597 return Opcode == KORDkk;
28598}
28599
28600bool isVPMULHW(unsigned Opcode) {
28601 switch (Opcode) {
28602 case VPMULHWYrm:
28603 case VPMULHWYrr:
28604 case VPMULHWZ128rm:
28605 case VPMULHWZ128rmk:
28606 case VPMULHWZ128rmkz:
28607 case VPMULHWZ128rr:
28608 case VPMULHWZ128rrk:
28609 case VPMULHWZ128rrkz:
28610 case VPMULHWZ256rm:
28611 case VPMULHWZ256rmk:
28612 case VPMULHWZ256rmkz:
28613 case VPMULHWZ256rr:
28614 case VPMULHWZ256rrk:
28615 case VPMULHWZ256rrkz:
28616 case VPMULHWZrm:
28617 case VPMULHWZrmk:
28618 case VPMULHWZrmkz:
28619 case VPMULHWZrr:
28620 case VPMULHWZrrk:
28621 case VPMULHWZrrkz:
28622 case VPMULHWrm:
28623 case VPMULHWrr:
28624 return true;
28625 }
28626 return false;
28627}
28628
28629bool isTILELOADDT1(unsigned Opcode) {
28630 switch (Opcode) {
28631 case TILELOADDT1:
28632 case TILELOADDT1_EVEX:
28633 return true;
28634 }
28635 return false;
28636}
28637
28638bool isVMASKMOVPS(unsigned Opcode) {
28639 switch (Opcode) {
28640 case VMASKMOVPSYmr:
28641 case VMASKMOVPSYrm:
28642 case VMASKMOVPSmr:
28643 case VMASKMOVPSrm:
28644 return true;
28645 }
28646 return false;
28647}
28648
28649bool isPMOVZXDQ(unsigned Opcode) {
28650 switch (Opcode) {
28651 case PMOVZXDQrm:
28652 case PMOVZXDQrr:
28653 return true;
28654 }
28655 return false;
28656}
28657
28658bool isVCVTPS2PH(unsigned Opcode) {
28659 switch (Opcode) {
28660 case VCVTPS2PHYmr:
28661 case VCVTPS2PHYrr:
28662 case VCVTPS2PHZ128mr:
28663 case VCVTPS2PHZ128mrk:
28664 case VCVTPS2PHZ128rr:
28665 case VCVTPS2PHZ128rrk:
28666 case VCVTPS2PHZ128rrkz:
28667 case VCVTPS2PHZ256mr:
28668 case VCVTPS2PHZ256mrk:
28669 case VCVTPS2PHZ256rr:
28670 case VCVTPS2PHZ256rrk:
28671 case VCVTPS2PHZ256rrkz:
28672 case VCVTPS2PHZmr:
28673 case VCVTPS2PHZmrk:
28674 case VCVTPS2PHZrr:
28675 case VCVTPS2PHZrrb:
28676 case VCVTPS2PHZrrbk:
28677 case VCVTPS2PHZrrbkz:
28678 case VCVTPS2PHZrrk:
28679 case VCVTPS2PHZrrkz:
28680 case VCVTPS2PHmr:
28681 case VCVTPS2PHrr:
28682 return true;
28683 }
28684 return false;
28685}
28686
28687bool isCVTDQ2PD(unsigned Opcode) {
28688 switch (Opcode) {
28689 case CVTDQ2PDrm:
28690 case CVTDQ2PDrr:
28691 return true;
28692 }
28693 return false;
28694}
28695
28696bool isVCVTSD2SS(unsigned Opcode) {
28697 switch (Opcode) {
28698 case VCVTSD2SSZrm_Int:
28699 case VCVTSD2SSZrmk_Int:
28700 case VCVTSD2SSZrmkz_Int:
28701 case VCVTSD2SSZrr_Int:
28702 case VCVTSD2SSZrrb_Int:
28703 case VCVTSD2SSZrrbk_Int:
28704 case VCVTSD2SSZrrbkz_Int:
28705 case VCVTSD2SSZrrk_Int:
28706 case VCVTSD2SSZrrkz_Int:
28707 case VCVTSD2SSrm_Int:
28708 case VCVTSD2SSrr_Int:
28709 return true;
28710 }
28711 return false;
28712}
28713
28714bool isVFMSUB213PH(unsigned Opcode) {
28715 switch (Opcode) {
28716 case VFMSUB213PHZ128m:
28717 case VFMSUB213PHZ128mb:
28718 case VFMSUB213PHZ128mbk:
28719 case VFMSUB213PHZ128mbkz:
28720 case VFMSUB213PHZ128mk:
28721 case VFMSUB213PHZ128mkz:
28722 case VFMSUB213PHZ128r:
28723 case VFMSUB213PHZ128rk:
28724 case VFMSUB213PHZ128rkz:
28725 case VFMSUB213PHZ256m:
28726 case VFMSUB213PHZ256mb:
28727 case VFMSUB213PHZ256mbk:
28728 case VFMSUB213PHZ256mbkz:
28729 case VFMSUB213PHZ256mk:
28730 case VFMSUB213PHZ256mkz:
28731 case VFMSUB213PHZ256r:
28732 case VFMSUB213PHZ256rk:
28733 case VFMSUB213PHZ256rkz:
28734 case VFMSUB213PHZm:
28735 case VFMSUB213PHZmb:
28736 case VFMSUB213PHZmbk:
28737 case VFMSUB213PHZmbkz:
28738 case VFMSUB213PHZmk:
28739 case VFMSUB213PHZmkz:
28740 case VFMSUB213PHZr:
28741 case VFMSUB213PHZrb:
28742 case VFMSUB213PHZrbk:
28743 case VFMSUB213PHZrbkz:
28744 case VFMSUB213PHZrk:
28745 case VFMSUB213PHZrkz:
28746 return true;
28747 }
28748 return false;
28749}
28750
28751bool isVPROTB(unsigned Opcode) {
28752 switch (Opcode) {
28753 case VPROTBmi:
28754 case VPROTBmr:
28755 case VPROTBri:
28756 case VPROTBrm:
28757 case VPROTBrr:
28758 case VPROTBrr_REV:
28759 return true;
28760 }
28761 return false;
28762}
28763
28764bool isPINSRD(unsigned Opcode) {
28765 switch (Opcode) {
28766 case PINSRDrmi:
28767 case PINSRDrri:
28768 return true;
28769 }
28770 return false;
28771}
28772
28773bool isVMXON(unsigned Opcode) {
28774 return Opcode == VMXON;
28775}
28776
28777bool isVFCMULCSH(unsigned Opcode) {
28778 switch (Opcode) {
28779 case VFCMULCSHZrm:
28780 case VFCMULCSHZrmk:
28781 case VFCMULCSHZrmkz:
28782 case VFCMULCSHZrr:
28783 case VFCMULCSHZrrb:
28784 case VFCMULCSHZrrbk:
28785 case VFCMULCSHZrrbkz:
28786 case VFCMULCSHZrrk:
28787 case VFCMULCSHZrrkz:
28788 return true;
28789 }
28790 return false;
28791}
28792
28793bool isVFMULCSH(unsigned Opcode) {
28794 switch (Opcode) {
28795 case VFMULCSHZrm:
28796 case VFMULCSHZrmk:
28797 case VFMULCSHZrmkz:
28798 case VFMULCSHZrr:
28799 case VFMULCSHZrrb:
28800 case VFMULCSHZrrbk:
28801 case VFMULCSHZrrbkz:
28802 case VFMULCSHZrrk:
28803 case VFMULCSHZrrkz:
28804 return true;
28805 }
28806 return false;
28807}
28808
28809bool isVRANGEPD(unsigned Opcode) {
28810 switch (Opcode) {
28811 case VRANGEPDZ128rmbi:
28812 case VRANGEPDZ128rmbik:
28813 case VRANGEPDZ128rmbikz:
28814 case VRANGEPDZ128rmi:
28815 case VRANGEPDZ128rmik:
28816 case VRANGEPDZ128rmikz:
28817 case VRANGEPDZ128rri:
28818 case VRANGEPDZ128rrik:
28819 case VRANGEPDZ128rrikz:
28820 case VRANGEPDZ256rmbi:
28821 case VRANGEPDZ256rmbik:
28822 case VRANGEPDZ256rmbikz:
28823 case VRANGEPDZ256rmi:
28824 case VRANGEPDZ256rmik:
28825 case VRANGEPDZ256rmikz:
28826 case VRANGEPDZ256rri:
28827 case VRANGEPDZ256rrik:
28828 case VRANGEPDZ256rrikz:
28829 case VRANGEPDZrmbi:
28830 case VRANGEPDZrmbik:
28831 case VRANGEPDZrmbikz:
28832 case VRANGEPDZrmi:
28833 case VRANGEPDZrmik:
28834 case VRANGEPDZrmikz:
28835 case VRANGEPDZrri:
28836 case VRANGEPDZrrib:
28837 case VRANGEPDZrribk:
28838 case VRANGEPDZrribkz:
28839 case VRANGEPDZrrik:
28840 case VRANGEPDZrrikz:
28841 return true;
28842 }
28843 return false;
28844}
28845
28846bool isCMC(unsigned Opcode) {
28847 return Opcode == CMC;
28848}
28849
28850bool isVFNMADD231BF16(unsigned Opcode) {
28851 switch (Opcode) {
28852 case VFNMADD231BF16Z128m:
28853 case VFNMADD231BF16Z128mb:
28854 case VFNMADD231BF16Z128mbk:
28855 case VFNMADD231BF16Z128mbkz:
28856 case VFNMADD231BF16Z128mk:
28857 case VFNMADD231BF16Z128mkz:
28858 case VFNMADD231BF16Z128r:
28859 case VFNMADD231BF16Z128rk:
28860 case VFNMADD231BF16Z128rkz:
28861 case VFNMADD231BF16Z256m:
28862 case VFNMADD231BF16Z256mb:
28863 case VFNMADD231BF16Z256mbk:
28864 case VFNMADD231BF16Z256mbkz:
28865 case VFNMADD231BF16Z256mk:
28866 case VFNMADD231BF16Z256mkz:
28867 case VFNMADD231BF16Z256r:
28868 case VFNMADD231BF16Z256rk:
28869 case VFNMADD231BF16Z256rkz:
28870 case VFNMADD231BF16Zm:
28871 case VFNMADD231BF16Zmb:
28872 case VFNMADD231BF16Zmbk:
28873 case VFNMADD231BF16Zmbkz:
28874 case VFNMADD231BF16Zmk:
28875 case VFNMADD231BF16Zmkz:
28876 case VFNMADD231BF16Zr:
28877 case VFNMADD231BF16Zrk:
28878 case VFNMADD231BF16Zrkz:
28879 return true;
28880 }
28881 return false;
28882}
28883
28884bool isSHA256MSG1(unsigned Opcode) {
28885 switch (Opcode) {
28886 case SHA256MSG1rm:
28887 case SHA256MSG1rr:
28888 return true;
28889 }
28890 return false;
28891}
28892
28893bool isFLD1(unsigned Opcode) {
28894 return Opcode == LD_F1;
28895}
28896
28897bool isCMPPS(unsigned Opcode) {
28898 switch (Opcode) {
28899 case CMPPSrmi:
28900 case CMPPSrri:
28901 return true;
28902 }
28903 return false;
28904}
28905
28906bool isVPAVGW(unsigned Opcode) {
28907 switch (Opcode) {
28908 case VPAVGWYrm:
28909 case VPAVGWYrr:
28910 case VPAVGWZ128rm:
28911 case VPAVGWZ128rmk:
28912 case VPAVGWZ128rmkz:
28913 case VPAVGWZ128rr:
28914 case VPAVGWZ128rrk:
28915 case VPAVGWZ128rrkz:
28916 case VPAVGWZ256rm:
28917 case VPAVGWZ256rmk:
28918 case VPAVGWZ256rmkz:
28919 case VPAVGWZ256rr:
28920 case VPAVGWZ256rrk:
28921 case VPAVGWZ256rrkz:
28922 case VPAVGWZrm:
28923 case VPAVGWZrmk:
28924 case VPAVGWZrmkz:
28925 case VPAVGWZrr:
28926 case VPAVGWZrrk:
28927 case VPAVGWZrrkz:
28928 case VPAVGWrm:
28929 case VPAVGWrr:
28930 return true;
28931 }
28932 return false;
28933}
28934
28935bool isVFMADD213SH(unsigned Opcode) {
28936 switch (Opcode) {
28937 case VFMADD213SHZm_Int:
28938 case VFMADD213SHZmk_Int:
28939 case VFMADD213SHZmkz_Int:
28940 case VFMADD213SHZr_Int:
28941 case VFMADD213SHZrb_Int:
28942 case VFMADD213SHZrbk_Int:
28943 case VFMADD213SHZrbkz_Int:
28944 case VFMADD213SHZrk_Int:
28945 case VFMADD213SHZrkz_Int:
28946 return true;
28947 }
28948 return false;
28949}
28950
28951bool isVPINSRQ(unsigned Opcode) {
28952 switch (Opcode) {
28953 case VPINSRQZrmi:
28954 case VPINSRQZrri:
28955 case VPINSRQrmi:
28956 case VPINSRQrri:
28957 return true;
28958 }
28959 return false;
28960}
28961
28962bool isMOVABS(unsigned Opcode) {
28963 switch (Opcode) {
28964 case MOV16ao64:
28965 case MOV16o64a:
28966 case MOV32ao64:
28967 case MOV32o64a:
28968 case MOV64ao64:
28969 case MOV64o64a:
28970 case MOV64ri:
28971 case MOV8ao64:
28972 case MOV8o64a:
28973 return true;
28974 }
28975 return false;
28976}
28977
28978bool isVPSHAQ(unsigned Opcode) {
28979 switch (Opcode) {
28980 case VPSHAQmr:
28981 case VPSHAQrm:
28982 case VPSHAQrr:
28983 case VPSHAQrr_REV:
28984 return true;
28985 }
28986 return false;
28987}
28988
28989bool isRDTSCP(unsigned Opcode) {
28990 return Opcode == RDTSCP;
28991}
28992
28993bool isVFNMADD231SS(unsigned Opcode) {
28994 switch (Opcode) {
28995 case VFNMADD231SSZm_Int:
28996 case VFNMADD231SSZmk_Int:
28997 case VFNMADD231SSZmkz_Int:
28998 case VFNMADD231SSZr_Int:
28999 case VFNMADD231SSZrb_Int:
29000 case VFNMADD231SSZrbk_Int:
29001 case VFNMADD231SSZrbkz_Int:
29002 case VFNMADD231SSZrk_Int:
29003 case VFNMADD231SSZrkz_Int:
29004 case VFNMADD231SSm_Int:
29005 case VFNMADD231SSr_Int:
29006 return true;
29007 }
29008 return false;
29009}
29010
29011bool isTEST(unsigned Opcode) {
29012 switch (Opcode) {
29013 case TEST16i16:
29014 case TEST16mi:
29015 case TEST16mr:
29016 case TEST16ri:
29017 case TEST16rr:
29018 case TEST32i32:
29019 case TEST32mi:
29020 case TEST32mr:
29021 case TEST32ri:
29022 case TEST32rr:
29023 case TEST64i32:
29024 case TEST64mi32:
29025 case TEST64mr:
29026 case TEST64ri32:
29027 case TEST64rr:
29028 case TEST8i8:
29029 case TEST8mi:
29030 case TEST8mr:
29031 case TEST8ri:
29032 case TEST8rr:
29033 return true;
29034 }
29035 return false;
29036}
29037
29038bool isVPERMD(unsigned Opcode) {
29039 switch (Opcode) {
29040 case VPERMDYrm:
29041 case VPERMDYrr:
29042 case VPERMDZ256rm:
29043 case VPERMDZ256rmb:
29044 case VPERMDZ256rmbk:
29045 case VPERMDZ256rmbkz:
29046 case VPERMDZ256rmk:
29047 case VPERMDZ256rmkz:
29048 case VPERMDZ256rr:
29049 case VPERMDZ256rrk:
29050 case VPERMDZ256rrkz:
29051 case VPERMDZrm:
29052 case VPERMDZrmb:
29053 case VPERMDZrmbk:
29054 case VPERMDZrmbkz:
29055 case VPERMDZrmk:
29056 case VPERMDZrmkz:
29057 case VPERMDZrr:
29058 case VPERMDZrrk:
29059 case VPERMDZrrkz:
29060 return true;
29061 }
29062 return false;
29063}
29064
29065bool isVBCSTNESH2PS(unsigned Opcode) {
29066 switch (Opcode) {
29067 case VBCSTNESH2PSYrm:
29068 case VBCSTNESH2PSrm:
29069 return true;
29070 }
29071 return false;
29072}
29073
29074bool isVGATHERPF0QPD(unsigned Opcode) {
29075 return Opcode == VGATHERPF0QPDm;
29076}
29077
29078bool isVPERM2I128(unsigned Opcode) {
29079 switch (Opcode) {
29080 case VPERM2I128rmi:
29081 case VPERM2I128rri:
29082 return true;
29083 }
29084 return false;
29085}
29086
29087bool isVMPSADBW(unsigned Opcode) {
29088 switch (Opcode) {
29089 case VMPSADBWYrmi:
29090 case VMPSADBWYrri:
29091 case VMPSADBWZ128rmi:
29092 case VMPSADBWZ128rmik:
29093 case VMPSADBWZ128rmikz:
29094 case VMPSADBWZ128rri:
29095 case VMPSADBWZ128rrik:
29096 case VMPSADBWZ128rrikz:
29097 case VMPSADBWZ256rmi:
29098 case VMPSADBWZ256rmik:
29099 case VMPSADBWZ256rmikz:
29100 case VMPSADBWZ256rri:
29101 case VMPSADBWZ256rrik:
29102 case VMPSADBWZ256rrikz:
29103 case VMPSADBWZrmi:
29104 case VMPSADBWZrmik:
29105 case VMPSADBWZrmikz:
29106 case VMPSADBWZrri:
29107 case VMPSADBWZrrik:
29108 case VMPSADBWZrrikz:
29109 case VMPSADBWrmi:
29110 case VMPSADBWrri:
29111 return true;
29112 }
29113 return false;
29114}
29115
29116bool isVFNMSUB231PD(unsigned Opcode) {
29117 switch (Opcode) {
29118 case VFNMSUB231PDYm:
29119 case VFNMSUB231PDYr:
29120 case VFNMSUB231PDZ128m:
29121 case VFNMSUB231PDZ128mb:
29122 case VFNMSUB231PDZ128mbk:
29123 case VFNMSUB231PDZ128mbkz:
29124 case VFNMSUB231PDZ128mk:
29125 case VFNMSUB231PDZ128mkz:
29126 case VFNMSUB231PDZ128r:
29127 case VFNMSUB231PDZ128rk:
29128 case VFNMSUB231PDZ128rkz:
29129 case VFNMSUB231PDZ256m:
29130 case VFNMSUB231PDZ256mb:
29131 case VFNMSUB231PDZ256mbk:
29132 case VFNMSUB231PDZ256mbkz:
29133 case VFNMSUB231PDZ256mk:
29134 case VFNMSUB231PDZ256mkz:
29135 case VFNMSUB231PDZ256r:
29136 case VFNMSUB231PDZ256rk:
29137 case VFNMSUB231PDZ256rkz:
29138 case VFNMSUB231PDZm:
29139 case VFNMSUB231PDZmb:
29140 case VFNMSUB231PDZmbk:
29141 case VFNMSUB231PDZmbkz:
29142 case VFNMSUB231PDZmk:
29143 case VFNMSUB231PDZmkz:
29144 case VFNMSUB231PDZr:
29145 case VFNMSUB231PDZrb:
29146 case VFNMSUB231PDZrbk:
29147 case VFNMSUB231PDZrbkz:
29148 case VFNMSUB231PDZrk:
29149 case VFNMSUB231PDZrkz:
29150 case VFNMSUB231PDm:
29151 case VFNMSUB231PDr:
29152 return true;
29153 }
29154 return false;
29155}
29156
29157bool isPADDSB(unsigned Opcode) {
29158 switch (Opcode) {
29159 case MMX_PADDSBrm:
29160 case MMX_PADDSBrr:
29161 case PADDSBrm:
29162 case PADDSBrr:
29163 return true;
29164 }
29165 return false;
29166}
29167
29168bool isMWAITX(unsigned Opcode) {
29169 return Opcode == MWAITXrrr;
29170}
29171
29172bool isMONITORX(unsigned Opcode) {
29173 switch (Opcode) {
29174 case MONITORX32rrr:
29175 case MONITORX64rrr:
29176 return true;
29177 }
29178 return false;
29179}
29180
29181bool isVPEXPANDD(unsigned Opcode) {
29182 switch (Opcode) {
29183 case VPEXPANDDZ128rm:
29184 case VPEXPANDDZ128rmk:
29185 case VPEXPANDDZ128rmkz:
29186 case VPEXPANDDZ128rr:
29187 case VPEXPANDDZ128rrk:
29188 case VPEXPANDDZ128rrkz:
29189 case VPEXPANDDZ256rm:
29190 case VPEXPANDDZ256rmk:
29191 case VPEXPANDDZ256rmkz:
29192 case VPEXPANDDZ256rr:
29193 case VPEXPANDDZ256rrk:
29194 case VPEXPANDDZ256rrkz:
29195 case VPEXPANDDZrm:
29196 case VPEXPANDDZrmk:
29197 case VPEXPANDDZrmkz:
29198 case VPEXPANDDZrr:
29199 case VPEXPANDDZrrk:
29200 case VPEXPANDDZrrkz:
29201 return true;
29202 }
29203 return false;
29204}
29205
29206bool isVFRCZPD(unsigned Opcode) {
29207 switch (Opcode) {
29208 case VFRCZPDYrm:
29209 case VFRCZPDYrr:
29210 case VFRCZPDrm:
29211 case VFRCZPDrr:
29212 return true;
29213 }
29214 return false;
29215}
29216
29217bool isVRCPPH(unsigned Opcode) {
29218 switch (Opcode) {
29219 case VRCPPHZ128m:
29220 case VRCPPHZ128mb:
29221 case VRCPPHZ128mbk:
29222 case VRCPPHZ128mbkz:
29223 case VRCPPHZ128mk:
29224 case VRCPPHZ128mkz:
29225 case VRCPPHZ128r:
29226 case VRCPPHZ128rk:
29227 case VRCPPHZ128rkz:
29228 case VRCPPHZ256m:
29229 case VRCPPHZ256mb:
29230 case VRCPPHZ256mbk:
29231 case VRCPPHZ256mbkz:
29232 case VRCPPHZ256mk:
29233 case VRCPPHZ256mkz:
29234 case VRCPPHZ256r:
29235 case VRCPPHZ256rk:
29236 case VRCPPHZ256rkz:
29237 case VRCPPHZm:
29238 case VRCPPHZmb:
29239 case VRCPPHZmbk:
29240 case VRCPPHZmbkz:
29241 case VRCPPHZmk:
29242 case VRCPPHZmkz:
29243 case VRCPPHZr:
29244 case VRCPPHZrk:
29245 case VRCPPHZrkz:
29246 return true;
29247 }
29248 return false;
29249}
29250
29251bool isFEMMS(unsigned Opcode) {
29252 return Opcode == FEMMS;
29253}
29254
29255bool isVSCATTERQPD(unsigned Opcode) {
29256 switch (Opcode) {
29257 case VSCATTERQPDZ128mr:
29258 case VSCATTERQPDZ256mr:
29259 case VSCATTERQPDZmr:
29260 return true;
29261 }
29262 return false;
29263}
29264
29265bool isVMOVW(unsigned Opcode) {
29266 switch (Opcode) {
29267 case VMOVSH2Wrr:
29268 case VMOVSHtoW64rr:
29269 case VMOVW2SHrr:
29270 case VMOVW64toSHrr:
29271 case VMOVWmr:
29272 case VMOVWrm:
29273 case VMOVZPWILo2PWIZmr:
29274 case VMOVZPWILo2PWIZrm:
29275 case VMOVZPWILo2PWIZrr:
29276 case VMOVZPWILo2PWIZrr2:
29277 return true;
29278 }
29279 return false;
29280}
29281
29282bool isVPBROADCASTD(unsigned Opcode) {
29283 switch (Opcode) {
29284 case VPBROADCASTDYrm:
29285 case VPBROADCASTDYrr:
29286 case VPBROADCASTDZ128rm:
29287 case VPBROADCASTDZ128rmk:
29288 case VPBROADCASTDZ128rmkz:
29289 case VPBROADCASTDZ128rr:
29290 case VPBROADCASTDZ128rrk:
29291 case VPBROADCASTDZ128rrkz:
29292 case VPBROADCASTDZ256rm:
29293 case VPBROADCASTDZ256rmk:
29294 case VPBROADCASTDZ256rmkz:
29295 case VPBROADCASTDZ256rr:
29296 case VPBROADCASTDZ256rrk:
29297 case VPBROADCASTDZ256rrkz:
29298 case VPBROADCASTDZrm:
29299 case VPBROADCASTDZrmk:
29300 case VPBROADCASTDZrmkz:
29301 case VPBROADCASTDZrr:
29302 case VPBROADCASTDZrrk:
29303 case VPBROADCASTDZrrkz:
29304 case VPBROADCASTDrZ128rr:
29305 case VPBROADCASTDrZ128rrk:
29306 case VPBROADCASTDrZ128rrkz:
29307 case VPBROADCASTDrZ256rr:
29308 case VPBROADCASTDrZ256rrk:
29309 case VPBROADCASTDrZ256rrkz:
29310 case VPBROADCASTDrZrr:
29311 case VPBROADCASTDrZrrk:
29312 case VPBROADCASTDrZrrkz:
29313 case VPBROADCASTDrm:
29314 case VPBROADCASTDrr:
29315 return true;
29316 }
29317 return false;
29318}
29319
29320bool isSTOSB(unsigned Opcode) {
29321 return Opcode == STOSB;
29322}
29323
29324bool isFUCOMI(unsigned Opcode) {
29325 return Opcode == UCOM_FIr;
29326}
29327
29328bool isVBROADCASTI64X4(unsigned Opcode) {
29329 switch (Opcode) {
29330 case VBROADCASTI64X4Zrm:
29331 case VBROADCASTI64X4Zrmk:
29332 case VBROADCASTI64X4Zrmkz:
29333 return true;
29334 }
29335 return false;
29336}
29337
29338bool isFCMOVU(unsigned Opcode) {
29339 return Opcode == CMOVP_F;
29340}
29341
29342bool isPSHUFLW(unsigned Opcode) {
29343 switch (Opcode) {
29344 case PSHUFLWmi:
29345 case PSHUFLWri:
29346 return true;
29347 }
29348 return false;
29349}
29350
29351bool isCVTPI2PS(unsigned Opcode) {
29352 switch (Opcode) {
29353 case MMX_CVTPI2PSrm:
29354 case MMX_CVTPI2PSrr:
29355 return true;
29356 }
29357 return false;
29358}
29359
29360bool isVCVTTPD2UDQS(unsigned Opcode) {
29361 switch (Opcode) {
29362 case VCVTTPD2UDQSZ128rm:
29363 case VCVTTPD2UDQSZ128rmb:
29364 case VCVTTPD2UDQSZ128rmbk:
29365 case VCVTTPD2UDQSZ128rmbkz:
29366 case VCVTTPD2UDQSZ128rmk:
29367 case VCVTTPD2UDQSZ128rmkz:
29368 case VCVTTPD2UDQSZ128rr:
29369 case VCVTTPD2UDQSZ128rrk:
29370 case VCVTTPD2UDQSZ128rrkz:
29371 case VCVTTPD2UDQSZ256rm:
29372 case VCVTTPD2UDQSZ256rmb:
29373 case VCVTTPD2UDQSZ256rmbk:
29374 case VCVTTPD2UDQSZ256rmbkz:
29375 case VCVTTPD2UDQSZ256rmk:
29376 case VCVTTPD2UDQSZ256rmkz:
29377 case VCVTTPD2UDQSZ256rr:
29378 case VCVTTPD2UDQSZ256rrb:
29379 case VCVTTPD2UDQSZ256rrbk:
29380 case VCVTTPD2UDQSZ256rrbkz:
29381 case VCVTTPD2UDQSZ256rrk:
29382 case VCVTTPD2UDQSZ256rrkz:
29383 case VCVTTPD2UDQSZrm:
29384 case VCVTTPD2UDQSZrmb:
29385 case VCVTTPD2UDQSZrmbk:
29386 case VCVTTPD2UDQSZrmbkz:
29387 case VCVTTPD2UDQSZrmk:
29388 case VCVTTPD2UDQSZrmkz:
29389 case VCVTTPD2UDQSZrr:
29390 case VCVTTPD2UDQSZrrb:
29391 case VCVTTPD2UDQSZrrbk:
29392 case VCVTTPD2UDQSZrrbkz:
29393 case VCVTTPD2UDQSZrrk:
29394 case VCVTTPD2UDQSZrrkz:
29395 return true;
29396 }
29397 return false;
29398}
29399
29400bool isSYSCALL(unsigned Opcode) {
29401 return Opcode == SYSCALL;
29402}
29403
29404bool isVFMADD231SH(unsigned Opcode) {
29405 switch (Opcode) {
29406 case VFMADD231SHZm_Int:
29407 case VFMADD231SHZmk_Int:
29408 case VFMADD231SHZmkz_Int:
29409 case VFMADD231SHZr_Int:
29410 case VFMADD231SHZrb_Int:
29411 case VFMADD231SHZrbk_Int:
29412 case VFMADD231SHZrbkz_Int:
29413 case VFMADD231SHZrk_Int:
29414 case VFMADD231SHZrkz_Int:
29415 return true;
29416 }
29417 return false;
29418}
29419
29420bool isPMOVZXBW(unsigned Opcode) {
29421 switch (Opcode) {
29422 case PMOVZXBWrm:
29423 case PMOVZXBWrr:
29424 return true;
29425 }
29426 return false;
29427}
29428
29429bool isVPOPCNTB(unsigned Opcode) {
29430 switch (Opcode) {
29431 case VPOPCNTBZ128rm:
29432 case VPOPCNTBZ128rmk:
29433 case VPOPCNTBZ128rmkz:
29434 case VPOPCNTBZ128rr:
29435 case VPOPCNTBZ128rrk:
29436 case VPOPCNTBZ128rrkz:
29437 case VPOPCNTBZ256rm:
29438 case VPOPCNTBZ256rmk:
29439 case VPOPCNTBZ256rmkz:
29440 case VPOPCNTBZ256rr:
29441 case VPOPCNTBZ256rrk:
29442 case VPOPCNTBZ256rrkz:
29443 case VPOPCNTBZrm:
29444 case VPOPCNTBZrmk:
29445 case VPOPCNTBZrmkz:
29446 case VPOPCNTBZrr:
29447 case VPOPCNTBZrrk:
29448 case VPOPCNTBZrrkz:
29449 return true;
29450 }
29451 return false;
29452}
29453
29454bool isVCVTDQ2PS(unsigned Opcode) {
29455 switch (Opcode) {
29456 case VCVTDQ2PSYrm:
29457 case VCVTDQ2PSYrr:
29458 case VCVTDQ2PSZ128rm:
29459 case VCVTDQ2PSZ128rmb:
29460 case VCVTDQ2PSZ128rmbk:
29461 case VCVTDQ2PSZ128rmbkz:
29462 case VCVTDQ2PSZ128rmk:
29463 case VCVTDQ2PSZ128rmkz:
29464 case VCVTDQ2PSZ128rr:
29465 case VCVTDQ2PSZ128rrk:
29466 case VCVTDQ2PSZ128rrkz:
29467 case VCVTDQ2PSZ256rm:
29468 case VCVTDQ2PSZ256rmb:
29469 case VCVTDQ2PSZ256rmbk:
29470 case VCVTDQ2PSZ256rmbkz:
29471 case VCVTDQ2PSZ256rmk:
29472 case VCVTDQ2PSZ256rmkz:
29473 case VCVTDQ2PSZ256rr:
29474 case VCVTDQ2PSZ256rrk:
29475 case VCVTDQ2PSZ256rrkz:
29476 case VCVTDQ2PSZrm:
29477 case VCVTDQ2PSZrmb:
29478 case VCVTDQ2PSZrmbk:
29479 case VCVTDQ2PSZrmbkz:
29480 case VCVTDQ2PSZrmk:
29481 case VCVTDQ2PSZrmkz:
29482 case VCVTDQ2PSZrr:
29483 case VCVTDQ2PSZrrb:
29484 case VCVTDQ2PSZrrbk:
29485 case VCVTDQ2PSZrrbkz:
29486 case VCVTDQ2PSZrrk:
29487 case VCVTDQ2PSZrrkz:
29488 case VCVTDQ2PSrm:
29489 case VCVTDQ2PSrr:
29490 return true;
29491 }
29492 return false;
29493}
29494
29495bool isPSUBD(unsigned Opcode) {
29496 switch (Opcode) {
29497 case MMX_PSUBDrm:
29498 case MMX_PSUBDrr:
29499 case PSUBDrm:
29500 case PSUBDrr:
29501 return true;
29502 }
29503 return false;
29504}
29505
29506bool isVPCMPEQW(unsigned Opcode) {
29507 switch (Opcode) {
29508 case VPCMPEQWYrm:
29509 case VPCMPEQWYrr:
29510 case VPCMPEQWZ128rm:
29511 case VPCMPEQWZ128rmk:
29512 case VPCMPEQWZ128rr:
29513 case VPCMPEQWZ128rrk:
29514 case VPCMPEQWZ256rm:
29515 case VPCMPEQWZ256rmk:
29516 case VPCMPEQWZ256rr:
29517 case VPCMPEQWZ256rrk:
29518 case VPCMPEQWZrm:
29519 case VPCMPEQWZrmk:
29520 case VPCMPEQWZrr:
29521 case VPCMPEQWZrrk:
29522 case VPCMPEQWrm:
29523 case VPCMPEQWrr:
29524 return true;
29525 }
29526 return false;
29527}
29528
29529bool isMOVSW(unsigned Opcode) {
29530 return Opcode == MOVSW;
29531}
29532
29533bool isVSM3RNDS2(unsigned Opcode) {
29534 switch (Opcode) {
29535 case VSM3RNDS2rmi:
29536 case VSM3RNDS2rri:
29537 return true;
29538 }
29539 return false;
29540}
29541
29542bool isVPMOVUSQD(unsigned Opcode) {
29543 switch (Opcode) {
29544 case VPMOVUSQDZ128mr:
29545 case VPMOVUSQDZ128mrk:
29546 case VPMOVUSQDZ128rr:
29547 case VPMOVUSQDZ128rrk:
29548 case VPMOVUSQDZ128rrkz:
29549 case VPMOVUSQDZ256mr:
29550 case VPMOVUSQDZ256mrk:
29551 case VPMOVUSQDZ256rr:
29552 case VPMOVUSQDZ256rrk:
29553 case VPMOVUSQDZ256rrkz:
29554 case VPMOVUSQDZmr:
29555 case VPMOVUSQDZmrk:
29556 case VPMOVUSQDZrr:
29557 case VPMOVUSQDZrrk:
29558 case VPMOVUSQDZrrkz:
29559 return true;
29560 }
29561 return false;
29562}
29563
29564bool isCVTTPD2DQ(unsigned Opcode) {
29565 switch (Opcode) {
29566 case CVTTPD2DQrm:
29567 case CVTTPD2DQrr:
29568 return true;
29569 }
29570 return false;
29571}
29572
29573bool isVPEXPANDW(unsigned Opcode) {
29574 switch (Opcode) {
29575 case VPEXPANDWZ128rm:
29576 case VPEXPANDWZ128rmk:
29577 case VPEXPANDWZ128rmkz:
29578 case VPEXPANDWZ128rr:
29579 case VPEXPANDWZ128rrk:
29580 case VPEXPANDWZ128rrkz:
29581 case VPEXPANDWZ256rm:
29582 case VPEXPANDWZ256rmk:
29583 case VPEXPANDWZ256rmkz:
29584 case VPEXPANDWZ256rr:
29585 case VPEXPANDWZ256rrk:
29586 case VPEXPANDWZ256rrkz:
29587 case VPEXPANDWZrm:
29588 case VPEXPANDWZrmk:
29589 case VPEXPANDWZrmkz:
29590 case VPEXPANDWZrr:
29591 case VPEXPANDWZrrk:
29592 case VPEXPANDWZrrkz:
29593 return true;
29594 }
29595 return false;
29596}
29597
29598bool isVUCOMISH(unsigned Opcode) {
29599 switch (Opcode) {
29600 case VUCOMISHZrm:
29601 case VUCOMISHZrr:
29602 case VUCOMISHZrrb:
29603 return true;
29604 }
29605 return false;
29606}
29607
29608bool isVZEROALL(unsigned Opcode) {
29609 return Opcode == VZEROALL;
29610}
29611
29612bool isVPAND(unsigned Opcode) {
29613 switch (Opcode) {
29614 case VPANDYrm:
29615 case VPANDYrr:
29616 case VPANDrm:
29617 case VPANDrr:
29618 return true;
29619 }
29620 return false;
29621}
29622
29623bool isPMULDQ(unsigned Opcode) {
29624 switch (Opcode) {
29625 case PMULDQrm:
29626 case PMULDQrr:
29627 return true;
29628 }
29629 return false;
29630}
29631
29632bool isVPSHUFHW(unsigned Opcode) {
29633 switch (Opcode) {
29634 case VPSHUFHWYmi:
29635 case VPSHUFHWYri:
29636 case VPSHUFHWZ128mi:
29637 case VPSHUFHWZ128mik:
29638 case VPSHUFHWZ128mikz:
29639 case VPSHUFHWZ128ri:
29640 case VPSHUFHWZ128rik:
29641 case VPSHUFHWZ128rikz:
29642 case VPSHUFHWZ256mi:
29643 case VPSHUFHWZ256mik:
29644 case VPSHUFHWZ256mikz:
29645 case VPSHUFHWZ256ri:
29646 case VPSHUFHWZ256rik:
29647 case VPSHUFHWZ256rikz:
29648 case VPSHUFHWZmi:
29649 case VPSHUFHWZmik:
29650 case VPSHUFHWZmikz:
29651 case VPSHUFHWZri:
29652 case VPSHUFHWZrik:
29653 case VPSHUFHWZrikz:
29654 case VPSHUFHWmi:
29655 case VPSHUFHWri:
29656 return true;
29657 }
29658 return false;
29659}
29660
29661bool isVPALIGNR(unsigned Opcode) {
29662 switch (Opcode) {
29663 case VPALIGNRYrmi:
29664 case VPALIGNRYrri:
29665 case VPALIGNRZ128rmi:
29666 case VPALIGNRZ128rmik:
29667 case VPALIGNRZ128rmikz:
29668 case VPALIGNRZ128rri:
29669 case VPALIGNRZ128rrik:
29670 case VPALIGNRZ128rrikz:
29671 case VPALIGNRZ256rmi:
29672 case VPALIGNRZ256rmik:
29673 case VPALIGNRZ256rmikz:
29674 case VPALIGNRZ256rri:
29675 case VPALIGNRZ256rrik:
29676 case VPALIGNRZ256rrikz:
29677 case VPALIGNRZrmi:
29678 case VPALIGNRZrmik:
29679 case VPALIGNRZrmikz:
29680 case VPALIGNRZrri:
29681 case VPALIGNRZrrik:
29682 case VPALIGNRZrrikz:
29683 case VPALIGNRrmi:
29684 case VPALIGNRrri:
29685 return true;
29686 }
29687 return false;
29688}
29689
29690bool isSQRTSD(unsigned Opcode) {
29691 switch (Opcode) {
29692 case SQRTSDm_Int:
29693 case SQRTSDr_Int:
29694 return true;
29695 }
29696 return false;
29697}
29698
29699bool isVCVTTPH2UDQ(unsigned Opcode) {
29700 switch (Opcode) {
29701 case VCVTTPH2UDQZ128rm:
29702 case VCVTTPH2UDQZ128rmb:
29703 case VCVTTPH2UDQZ128rmbk:
29704 case VCVTTPH2UDQZ128rmbkz:
29705 case VCVTTPH2UDQZ128rmk:
29706 case VCVTTPH2UDQZ128rmkz:
29707 case VCVTTPH2UDQZ128rr:
29708 case VCVTTPH2UDQZ128rrk:
29709 case VCVTTPH2UDQZ128rrkz:
29710 case VCVTTPH2UDQZ256rm:
29711 case VCVTTPH2UDQZ256rmb:
29712 case VCVTTPH2UDQZ256rmbk:
29713 case VCVTTPH2UDQZ256rmbkz:
29714 case VCVTTPH2UDQZ256rmk:
29715 case VCVTTPH2UDQZ256rmkz:
29716 case VCVTTPH2UDQZ256rr:
29717 case VCVTTPH2UDQZ256rrk:
29718 case VCVTTPH2UDQZ256rrkz:
29719 case VCVTTPH2UDQZrm:
29720 case VCVTTPH2UDQZrmb:
29721 case VCVTTPH2UDQZrmbk:
29722 case VCVTTPH2UDQZrmbkz:
29723 case VCVTTPH2UDQZrmk:
29724 case VCVTTPH2UDQZrmkz:
29725 case VCVTTPH2UDQZrr:
29726 case VCVTTPH2UDQZrrb:
29727 case VCVTTPH2UDQZrrbk:
29728 case VCVTTPH2UDQZrrbkz:
29729 case VCVTTPH2UDQZrrk:
29730 case VCVTTPH2UDQZrrkz:
29731 return true;
29732 }
29733 return false;
29734}
29735
29736bool isVGETEXPPH(unsigned Opcode) {
29737 switch (Opcode) {
29738 case VGETEXPPHZ128m:
29739 case VGETEXPPHZ128mb:
29740 case VGETEXPPHZ128mbk:
29741 case VGETEXPPHZ128mbkz:
29742 case VGETEXPPHZ128mk:
29743 case VGETEXPPHZ128mkz:
29744 case VGETEXPPHZ128r:
29745 case VGETEXPPHZ128rk:
29746 case VGETEXPPHZ128rkz:
29747 case VGETEXPPHZ256m:
29748 case VGETEXPPHZ256mb:
29749 case VGETEXPPHZ256mbk:
29750 case VGETEXPPHZ256mbkz:
29751 case VGETEXPPHZ256mk:
29752 case VGETEXPPHZ256mkz:
29753 case VGETEXPPHZ256r:
29754 case VGETEXPPHZ256rk:
29755 case VGETEXPPHZ256rkz:
29756 case VGETEXPPHZm:
29757 case VGETEXPPHZmb:
29758 case VGETEXPPHZmbk:
29759 case VGETEXPPHZmbkz:
29760 case VGETEXPPHZmk:
29761 case VGETEXPPHZmkz:
29762 case VGETEXPPHZr:
29763 case VGETEXPPHZrb:
29764 case VGETEXPPHZrbk:
29765 case VGETEXPPHZrbkz:
29766 case VGETEXPPHZrk:
29767 case VGETEXPPHZrkz:
29768 return true;
29769 }
29770 return false;
29771}
29772
29773bool isADDPD(unsigned Opcode) {
29774 switch (Opcode) {
29775 case ADDPDrm:
29776 case ADDPDrr:
29777 return true;
29778 }
29779 return false;
29780}
29781
29782bool isVFNMADDPD(unsigned Opcode) {
29783 switch (Opcode) {
29784 case VFNMADDPD4Ymr:
29785 case VFNMADDPD4Yrm:
29786 case VFNMADDPD4Yrr:
29787 case VFNMADDPD4Yrr_REV:
29788 case VFNMADDPD4mr:
29789 case VFNMADDPD4rm:
29790 case VFNMADDPD4rr:
29791 case VFNMADDPD4rr_REV:
29792 return true;
29793 }
29794 return false;
29795}
29796
29797bool isSTTILECFG(unsigned Opcode) {
29798 switch (Opcode) {
29799 case STTILECFG:
29800 case STTILECFG_EVEX:
29801 return true;
29802 }
29803 return false;
29804}
29805
29806bool isVMINPD(unsigned Opcode) {
29807 switch (Opcode) {
29808 case VMINPDYrm:
29809 case VMINPDYrr:
29810 case VMINPDZ128rm:
29811 case VMINPDZ128rmb:
29812 case VMINPDZ128rmbk:
29813 case VMINPDZ128rmbkz:
29814 case VMINPDZ128rmk:
29815 case VMINPDZ128rmkz:
29816 case VMINPDZ128rr:
29817 case VMINPDZ128rrk:
29818 case VMINPDZ128rrkz:
29819 case VMINPDZ256rm:
29820 case VMINPDZ256rmb:
29821 case VMINPDZ256rmbk:
29822 case VMINPDZ256rmbkz:
29823 case VMINPDZ256rmk:
29824 case VMINPDZ256rmkz:
29825 case VMINPDZ256rr:
29826 case VMINPDZ256rrk:
29827 case VMINPDZ256rrkz:
29828 case VMINPDZrm:
29829 case VMINPDZrmb:
29830 case VMINPDZrmbk:
29831 case VMINPDZrmbkz:
29832 case VMINPDZrmk:
29833 case VMINPDZrmkz:
29834 case VMINPDZrr:
29835 case VMINPDZrrb:
29836 case VMINPDZrrbk:
29837 case VMINPDZrrbkz:
29838 case VMINPDZrrk:
29839 case VMINPDZrrkz:
29840 case VMINPDrm:
29841 case VMINPDrr:
29842 return true;
29843 }
29844 return false;
29845}
29846
29847bool isSHA1RNDS4(unsigned Opcode) {
29848 switch (Opcode) {
29849 case SHA1RNDS4rmi:
29850 case SHA1RNDS4rri:
29851 return true;
29852 }
29853 return false;
29854}
29855
29856bool isPBLENDVB(unsigned Opcode) {
29857 switch (Opcode) {
29858 case PBLENDVBrm0:
29859 case PBLENDVBrr0:
29860 return true;
29861 }
29862 return false;
29863}
29864
29865bool isVBROADCASTF128(unsigned Opcode) {
29866 return Opcode == VBROADCASTF128rm;
29867}
29868
29869bool isVPSHRDQ(unsigned Opcode) {
29870 switch (Opcode) {
29871 case VPSHRDQZ128rmbi:
29872 case VPSHRDQZ128rmbik:
29873 case VPSHRDQZ128rmbikz:
29874 case VPSHRDQZ128rmi:
29875 case VPSHRDQZ128rmik:
29876 case VPSHRDQZ128rmikz:
29877 case VPSHRDQZ128rri:
29878 case VPSHRDQZ128rrik:
29879 case VPSHRDQZ128rrikz:
29880 case VPSHRDQZ256rmbi:
29881 case VPSHRDQZ256rmbik:
29882 case VPSHRDQZ256rmbikz:
29883 case VPSHRDQZ256rmi:
29884 case VPSHRDQZ256rmik:
29885 case VPSHRDQZ256rmikz:
29886 case VPSHRDQZ256rri:
29887 case VPSHRDQZ256rrik:
29888 case VPSHRDQZ256rrikz:
29889 case VPSHRDQZrmbi:
29890 case VPSHRDQZrmbik:
29891 case VPSHRDQZrmbikz:
29892 case VPSHRDQZrmi:
29893 case VPSHRDQZrmik:
29894 case VPSHRDQZrmikz:
29895 case VPSHRDQZrri:
29896 case VPSHRDQZrrik:
29897 case VPSHRDQZrrikz:
29898 return true;
29899 }
29900 return false;
29901}
29902
29903bool isVAESIMC(unsigned Opcode) {
29904 switch (Opcode) {
29905 case VAESIMCrm:
29906 case VAESIMCrr:
29907 return true;
29908 }
29909 return false;
29910}
29911
29912bool isCOMISD(unsigned Opcode) {
29913 switch (Opcode) {
29914 case COMISDrm:
29915 case COMISDrr:
29916 return true;
29917 }
29918 return false;
29919}
29920
29921bool isVMOVSH(unsigned Opcode) {
29922 switch (Opcode) {
29923 case VMOVSHZmr:
29924 case VMOVSHZmrk:
29925 case VMOVSHZrm:
29926 case VMOVSHZrmk:
29927 case VMOVSHZrmkz:
29928 case VMOVSHZrr:
29929 case VMOVSHZrr_REV:
29930 case VMOVSHZrrk:
29931 case VMOVSHZrrk_REV:
29932 case VMOVSHZrrkz:
29933 case VMOVSHZrrkz_REV:
29934 return true;
29935 }
29936 return false;
29937}
29938
29939bool isPFSUBR(unsigned Opcode) {
29940 switch (Opcode) {
29941 case PFSUBRrm:
29942 case PFSUBRrr:
29943 return true;
29944 }
29945 return false;
29946}
29947
29948bool isRDSSPD(unsigned Opcode) {
29949 return Opcode == RDSSPD;
29950}
29951
29952bool isWAIT(unsigned Opcode) {
29953 return Opcode == WAIT;
29954}
29955
29956bool isVFPCLASSSS(unsigned Opcode) {
29957 switch (Opcode) {
29958 case VFPCLASSSSZmi:
29959 case VFPCLASSSSZmik:
29960 case VFPCLASSSSZri:
29961 case VFPCLASSSSZrik:
29962 return true;
29963 }
29964 return false;
29965}
29966
29967bool isPCMPGTD(unsigned Opcode) {
29968 switch (Opcode) {
29969 case MMX_PCMPGTDrm:
29970 case MMX_PCMPGTDrr:
29971 case PCMPGTDrm:
29972 case PCMPGTDrr:
29973 return true;
29974 }
29975 return false;
29976}
29977
29978bool isVGATHERPF0QPS(unsigned Opcode) {
29979 return Opcode == VGATHERPF0QPSm;
29980}
29981
29982bool isBLENDVPS(unsigned Opcode) {
29983 switch (Opcode) {
29984 case BLENDVPSrm0:
29985 case BLENDVPSrr0:
29986 return true;
29987 }
29988 return false;
29989}
29990
29991bool isVBROADCASTF32X4(unsigned Opcode) {
29992 switch (Opcode) {
29993 case VBROADCASTF32X4Z256rm:
29994 case VBROADCASTF32X4Z256rmk:
29995 case VBROADCASTF32X4Z256rmkz:
29996 case VBROADCASTF32X4Zrm:
29997 case VBROADCASTF32X4Zrmk:
29998 case VBROADCASTF32X4Zrmkz:
29999 return true;
30000 }
30001 return false;
30002}
30003
30004bool isVPMADD52LUQ(unsigned Opcode) {
30005 switch (Opcode) {
30006 case VPMADD52LUQYrm:
30007 case VPMADD52LUQYrr:
30008 case VPMADD52LUQZ128m:
30009 case VPMADD52LUQZ128mb:
30010 case VPMADD52LUQZ128mbk:
30011 case VPMADD52LUQZ128mbkz:
30012 case VPMADD52LUQZ128mk:
30013 case VPMADD52LUQZ128mkz:
30014 case VPMADD52LUQZ128r:
30015 case VPMADD52LUQZ128rk:
30016 case VPMADD52LUQZ128rkz:
30017 case VPMADD52LUQZ256m:
30018 case VPMADD52LUQZ256mb:
30019 case VPMADD52LUQZ256mbk:
30020 case VPMADD52LUQZ256mbkz:
30021 case VPMADD52LUQZ256mk:
30022 case VPMADD52LUQZ256mkz:
30023 case VPMADD52LUQZ256r:
30024 case VPMADD52LUQZ256rk:
30025 case VPMADD52LUQZ256rkz:
30026 case VPMADD52LUQZm:
30027 case VPMADD52LUQZmb:
30028 case VPMADD52LUQZmbk:
30029 case VPMADD52LUQZmbkz:
30030 case VPMADD52LUQZmk:
30031 case VPMADD52LUQZmkz:
30032 case VPMADD52LUQZr:
30033 case VPMADD52LUQZrk:
30034 case VPMADD52LUQZrkz:
30035 case VPMADD52LUQrm:
30036 case VPMADD52LUQrr:
30037 return true;
30038 }
30039 return false;
30040}
30041
30042bool isVMOVLPD(unsigned Opcode) {
30043 switch (Opcode) {
30044 case VMOVLPDZ128mr:
30045 case VMOVLPDZ128rm:
30046 case VMOVLPDmr:
30047 case VMOVLPDrm:
30048 return true;
30049 }
30050 return false;
30051}
30052
30053bool isVMOVQ(unsigned Opcode) {
30054 switch (Opcode) {
30055 case VMOV64toPQIZrm:
30056 case VMOV64toPQIZrr:
30057 case VMOV64toPQIrm:
30058 case VMOV64toPQIrr:
30059 case VMOVPQI2QIZmr:
30060 case VMOVPQI2QIZrr:
30061 case VMOVPQI2QImr:
30062 case VMOVPQI2QIrr:
30063 case VMOVPQIto64Zmr:
30064 case VMOVPQIto64Zrr:
30065 case VMOVPQIto64mr:
30066 case VMOVPQIto64rr:
30067 case VMOVQI2PQIZrm:
30068 case VMOVQI2PQIrm:
30069 case VMOVZPQILo2PQIZrr:
30070 case VMOVZPQILo2PQIrr:
30071 return true;
30072 }
30073 return false;
30074}
30075
30076bool isVMOVDQU(unsigned Opcode) {
30077 switch (Opcode) {
30078 case VMOVDQUYmr:
30079 case VMOVDQUYrm:
30080 case VMOVDQUYrr:
30081 case VMOVDQUYrr_REV:
30082 case VMOVDQUmr:
30083 case VMOVDQUrm:
30084 case VMOVDQUrr:
30085 case VMOVDQUrr_REV:
30086 return true;
30087 }
30088 return false;
30089}
30090
30091bool isAESENC128KL(unsigned Opcode) {
30092 return Opcode == AESENC128KL;
30093}
30094
30095bool isVFMADDSUB231PS(unsigned Opcode) {
30096 switch (Opcode) {
30097 case VFMADDSUB231PSYm:
30098 case VFMADDSUB231PSYr:
30099 case VFMADDSUB231PSZ128m:
30100 case VFMADDSUB231PSZ128mb:
30101 case VFMADDSUB231PSZ128mbk:
30102 case VFMADDSUB231PSZ128mbkz:
30103 case VFMADDSUB231PSZ128mk:
30104 case VFMADDSUB231PSZ128mkz:
30105 case VFMADDSUB231PSZ128r:
30106 case VFMADDSUB231PSZ128rk:
30107 case VFMADDSUB231PSZ128rkz:
30108 case VFMADDSUB231PSZ256m:
30109 case VFMADDSUB231PSZ256mb:
30110 case VFMADDSUB231PSZ256mbk:
30111 case VFMADDSUB231PSZ256mbkz:
30112 case VFMADDSUB231PSZ256mk:
30113 case VFMADDSUB231PSZ256mkz:
30114 case VFMADDSUB231PSZ256r:
30115 case VFMADDSUB231PSZ256rk:
30116 case VFMADDSUB231PSZ256rkz:
30117 case VFMADDSUB231PSZm:
30118 case VFMADDSUB231PSZmb:
30119 case VFMADDSUB231PSZmbk:
30120 case VFMADDSUB231PSZmbkz:
30121 case VFMADDSUB231PSZmk:
30122 case VFMADDSUB231PSZmkz:
30123 case VFMADDSUB231PSZr:
30124 case VFMADDSUB231PSZrb:
30125 case VFMADDSUB231PSZrbk:
30126 case VFMADDSUB231PSZrbkz:
30127 case VFMADDSUB231PSZrk:
30128 case VFMADDSUB231PSZrkz:
30129 case VFMADDSUB231PSm:
30130 case VFMADDSUB231PSr:
30131 return true;
30132 }
30133 return false;
30134}
30135
30136bool isVFNMSUB213PD(unsigned Opcode) {
30137 switch (Opcode) {
30138 case VFNMSUB213PDYm:
30139 case VFNMSUB213PDYr:
30140 case VFNMSUB213PDZ128m:
30141 case VFNMSUB213PDZ128mb:
30142 case VFNMSUB213PDZ128mbk:
30143 case VFNMSUB213PDZ128mbkz:
30144 case VFNMSUB213PDZ128mk:
30145 case VFNMSUB213PDZ128mkz:
30146 case VFNMSUB213PDZ128r:
30147 case VFNMSUB213PDZ128rk:
30148 case VFNMSUB213PDZ128rkz:
30149 case VFNMSUB213PDZ256m:
30150 case VFNMSUB213PDZ256mb:
30151 case VFNMSUB213PDZ256mbk:
30152 case VFNMSUB213PDZ256mbkz:
30153 case VFNMSUB213PDZ256mk:
30154 case VFNMSUB213PDZ256mkz:
30155 case VFNMSUB213PDZ256r:
30156 case VFNMSUB213PDZ256rk:
30157 case VFNMSUB213PDZ256rkz:
30158 case VFNMSUB213PDZm:
30159 case VFNMSUB213PDZmb:
30160 case VFNMSUB213PDZmbk:
30161 case VFNMSUB213PDZmbkz:
30162 case VFNMSUB213PDZmk:
30163 case VFNMSUB213PDZmkz:
30164 case VFNMSUB213PDZr:
30165 case VFNMSUB213PDZrb:
30166 case VFNMSUB213PDZrbk:
30167 case VFNMSUB213PDZrbkz:
30168 case VFNMSUB213PDZrk:
30169 case VFNMSUB213PDZrkz:
30170 case VFNMSUB213PDm:
30171 case VFNMSUB213PDr:
30172 return true;
30173 }
30174 return false;
30175}
30176
30177bool isVPCONFLICTD(unsigned Opcode) {
30178 switch (Opcode) {
30179 case VPCONFLICTDZ128rm:
30180 case VPCONFLICTDZ128rmb:
30181 case VPCONFLICTDZ128rmbk:
30182 case VPCONFLICTDZ128rmbkz:
30183 case VPCONFLICTDZ128rmk:
30184 case VPCONFLICTDZ128rmkz:
30185 case VPCONFLICTDZ128rr:
30186 case VPCONFLICTDZ128rrk:
30187 case VPCONFLICTDZ128rrkz:
30188 case VPCONFLICTDZ256rm:
30189 case VPCONFLICTDZ256rmb:
30190 case VPCONFLICTDZ256rmbk:
30191 case VPCONFLICTDZ256rmbkz:
30192 case VPCONFLICTDZ256rmk:
30193 case VPCONFLICTDZ256rmkz:
30194 case VPCONFLICTDZ256rr:
30195 case VPCONFLICTDZ256rrk:
30196 case VPCONFLICTDZ256rrkz:
30197 case VPCONFLICTDZrm:
30198 case VPCONFLICTDZrmb:
30199 case VPCONFLICTDZrmbk:
30200 case VPCONFLICTDZrmbkz:
30201 case VPCONFLICTDZrmk:
30202 case VPCONFLICTDZrmkz:
30203 case VPCONFLICTDZrr:
30204 case VPCONFLICTDZrrk:
30205 case VPCONFLICTDZrrkz:
30206 return true;
30207 }
30208 return false;
30209}
30210
30211bool isVFMADDSUB213PH(unsigned Opcode) {
30212 switch (Opcode) {
30213 case VFMADDSUB213PHZ128m:
30214 case VFMADDSUB213PHZ128mb:
30215 case VFMADDSUB213PHZ128mbk:
30216 case VFMADDSUB213PHZ128mbkz:
30217 case VFMADDSUB213PHZ128mk:
30218 case VFMADDSUB213PHZ128mkz:
30219 case VFMADDSUB213PHZ128r:
30220 case VFMADDSUB213PHZ128rk:
30221 case VFMADDSUB213PHZ128rkz:
30222 case VFMADDSUB213PHZ256m:
30223 case VFMADDSUB213PHZ256mb:
30224 case VFMADDSUB213PHZ256mbk:
30225 case VFMADDSUB213PHZ256mbkz:
30226 case VFMADDSUB213PHZ256mk:
30227 case VFMADDSUB213PHZ256mkz:
30228 case VFMADDSUB213PHZ256r:
30229 case VFMADDSUB213PHZ256rk:
30230 case VFMADDSUB213PHZ256rkz:
30231 case VFMADDSUB213PHZm:
30232 case VFMADDSUB213PHZmb:
30233 case VFMADDSUB213PHZmbk:
30234 case VFMADDSUB213PHZmbkz:
30235 case VFMADDSUB213PHZmk:
30236 case VFMADDSUB213PHZmkz:
30237 case VFMADDSUB213PHZr:
30238 case VFMADDSUB213PHZrb:
30239 case VFMADDSUB213PHZrbk:
30240 case VFMADDSUB213PHZrbkz:
30241 case VFMADDSUB213PHZrk:
30242 case VFMADDSUB213PHZrkz:
30243 return true;
30244 }
30245 return false;
30246}
30247
30248bool isVPHSUBSW(unsigned Opcode) {
30249 switch (Opcode) {
30250 case VPHSUBSWYrm:
30251 case VPHSUBSWYrr:
30252 case VPHSUBSWrm:
30253 case VPHSUBSWrr:
30254 return true;
30255 }
30256 return false;
30257}
30258
30259bool isPUNPCKHDQ(unsigned Opcode) {
30260 switch (Opcode) {
30261 case MMX_PUNPCKHDQrm:
30262 case MMX_PUNPCKHDQrr:
30263 case PUNPCKHDQrm:
30264 case PUNPCKHDQrr:
30265 return true;
30266 }
30267 return false;
30268}
30269
30270bool isVSHUFI64X2(unsigned Opcode) {
30271 switch (Opcode) {
30272 case VSHUFI64X2Z256rmbi:
30273 case VSHUFI64X2Z256rmbik:
30274 case VSHUFI64X2Z256rmbikz:
30275 case VSHUFI64X2Z256rmi:
30276 case VSHUFI64X2Z256rmik:
30277 case VSHUFI64X2Z256rmikz:
30278 case VSHUFI64X2Z256rri:
30279 case VSHUFI64X2Z256rrik:
30280 case VSHUFI64X2Z256rrikz:
30281 case VSHUFI64X2Zrmbi:
30282 case VSHUFI64X2Zrmbik:
30283 case VSHUFI64X2Zrmbikz:
30284 case VSHUFI64X2Zrmi:
30285 case VSHUFI64X2Zrmik:
30286 case VSHUFI64X2Zrmikz:
30287 case VSHUFI64X2Zrri:
30288 case VSHUFI64X2Zrrik:
30289 case VSHUFI64X2Zrrikz:
30290 return true;
30291 }
30292 return false;
30293}
30294
30295bool isVFMSUBSD(unsigned Opcode) {
30296 switch (Opcode) {
30297 case VFMSUBSD4mr:
30298 case VFMSUBSD4rm:
30299 case VFMSUBSD4rr:
30300 case VFMSUBSD4rr_REV:
30301 return true;
30302 }
30303 return false;
30304}
30305
30306bool isVPORD(unsigned Opcode) {
30307 switch (Opcode) {
30308 case VPORDZ128rm:
30309 case VPORDZ128rmb:
30310 case VPORDZ128rmbk:
30311 case VPORDZ128rmbkz:
30312 case VPORDZ128rmk:
30313 case VPORDZ128rmkz:
30314 case VPORDZ128rr:
30315 case VPORDZ128rrk:
30316 case VPORDZ128rrkz:
30317 case VPORDZ256rm:
30318 case VPORDZ256rmb:
30319 case VPORDZ256rmbk:
30320 case VPORDZ256rmbkz:
30321 case VPORDZ256rmk:
30322 case VPORDZ256rmkz:
30323 case VPORDZ256rr:
30324 case VPORDZ256rrk:
30325 case VPORDZ256rrkz:
30326 case VPORDZrm:
30327 case VPORDZrmb:
30328 case VPORDZrmbk:
30329 case VPORDZrmbkz:
30330 case VPORDZrmk:
30331 case VPORDZrmkz:
30332 case VPORDZrr:
30333 case VPORDZrrk:
30334 case VPORDZrrkz:
30335 return true;
30336 }
30337 return false;
30338}
30339
30340bool isRCPPS(unsigned Opcode) {
30341 switch (Opcode) {
30342 case RCPPSm:
30343 case RCPPSr:
30344 return true;
30345 }
30346 return false;
30347}
30348
30349bool isVEXTRACTI128(unsigned Opcode) {
30350 switch (Opcode) {
30351 case VEXTRACTI128mri:
30352 case VEXTRACTI128rri:
30353 return true;
30354 }
30355 return false;
30356}
30357
30358bool isVCVT2PH2BF8S(unsigned Opcode) {
30359 switch (Opcode) {
30360 case VCVT2PH2BF8SZ128rm:
30361 case VCVT2PH2BF8SZ128rmb:
30362 case VCVT2PH2BF8SZ128rmbk:
30363 case VCVT2PH2BF8SZ128rmbkz:
30364 case VCVT2PH2BF8SZ128rmk:
30365 case VCVT2PH2BF8SZ128rmkz:
30366 case VCVT2PH2BF8SZ128rr:
30367 case VCVT2PH2BF8SZ128rrk:
30368 case VCVT2PH2BF8SZ128rrkz:
30369 case VCVT2PH2BF8SZ256rm:
30370 case VCVT2PH2BF8SZ256rmb:
30371 case VCVT2PH2BF8SZ256rmbk:
30372 case VCVT2PH2BF8SZ256rmbkz:
30373 case VCVT2PH2BF8SZ256rmk:
30374 case VCVT2PH2BF8SZ256rmkz:
30375 case VCVT2PH2BF8SZ256rr:
30376 case VCVT2PH2BF8SZ256rrk:
30377 case VCVT2PH2BF8SZ256rrkz:
30378 case VCVT2PH2BF8SZrm:
30379 case VCVT2PH2BF8SZrmb:
30380 case VCVT2PH2BF8SZrmbk:
30381 case VCVT2PH2BF8SZrmbkz:
30382 case VCVT2PH2BF8SZrmk:
30383 case VCVT2PH2BF8SZrmkz:
30384 case VCVT2PH2BF8SZrr:
30385 case VCVT2PH2BF8SZrrk:
30386 case VCVT2PH2BF8SZrrkz:
30387 return true;
30388 }
30389 return false;
30390}
30391
30392bool isVPSHRDVW(unsigned Opcode) {
30393 switch (Opcode) {
30394 case VPSHRDVWZ128m:
30395 case VPSHRDVWZ128mk:
30396 case VPSHRDVWZ128mkz:
30397 case VPSHRDVWZ128r:
30398 case VPSHRDVWZ128rk:
30399 case VPSHRDVWZ128rkz:
30400 case VPSHRDVWZ256m:
30401 case VPSHRDVWZ256mk:
30402 case VPSHRDVWZ256mkz:
30403 case VPSHRDVWZ256r:
30404 case VPSHRDVWZ256rk:
30405 case VPSHRDVWZ256rkz:
30406 case VPSHRDVWZm:
30407 case VPSHRDVWZmk:
30408 case VPSHRDVWZmkz:
30409 case VPSHRDVWZr:
30410 case VPSHRDVWZrk:
30411 case VPSHRDVWZrkz:
30412 return true;
30413 }
30414 return false;
30415}
30416
30417bool isVUNPCKLPD(unsigned Opcode) {
30418 switch (Opcode) {
30419 case VUNPCKLPDYrm:
30420 case VUNPCKLPDYrr:
30421 case VUNPCKLPDZ128rm:
30422 case VUNPCKLPDZ128rmb:
30423 case VUNPCKLPDZ128rmbk:
30424 case VUNPCKLPDZ128rmbkz:
30425 case VUNPCKLPDZ128rmk:
30426 case VUNPCKLPDZ128rmkz:
30427 case VUNPCKLPDZ128rr:
30428 case VUNPCKLPDZ128rrk:
30429 case VUNPCKLPDZ128rrkz:
30430 case VUNPCKLPDZ256rm:
30431 case VUNPCKLPDZ256rmb:
30432 case VUNPCKLPDZ256rmbk:
30433 case VUNPCKLPDZ256rmbkz:
30434 case VUNPCKLPDZ256rmk:
30435 case VUNPCKLPDZ256rmkz:
30436 case VUNPCKLPDZ256rr:
30437 case VUNPCKLPDZ256rrk:
30438 case VUNPCKLPDZ256rrkz:
30439 case VUNPCKLPDZrm:
30440 case VUNPCKLPDZrmb:
30441 case VUNPCKLPDZrmbk:
30442 case VUNPCKLPDZrmbkz:
30443 case VUNPCKLPDZrmk:
30444 case VUNPCKLPDZrmkz:
30445 case VUNPCKLPDZrr:
30446 case VUNPCKLPDZrrk:
30447 case VUNPCKLPDZrrkz:
30448 case VUNPCKLPDrm:
30449 case VUNPCKLPDrr:
30450 return true;
30451 }
30452 return false;
30453}
30454
30455bool isVPSRAVD(unsigned Opcode) {
30456 switch (Opcode) {
30457 case VPSRAVDYrm:
30458 case VPSRAVDYrr:
30459 case VPSRAVDZ128rm:
30460 case VPSRAVDZ128rmb:
30461 case VPSRAVDZ128rmbk:
30462 case VPSRAVDZ128rmbkz:
30463 case VPSRAVDZ128rmk:
30464 case VPSRAVDZ128rmkz:
30465 case VPSRAVDZ128rr:
30466 case VPSRAVDZ128rrk:
30467 case VPSRAVDZ128rrkz:
30468 case VPSRAVDZ256rm:
30469 case VPSRAVDZ256rmb:
30470 case VPSRAVDZ256rmbk:
30471 case VPSRAVDZ256rmbkz:
30472 case VPSRAVDZ256rmk:
30473 case VPSRAVDZ256rmkz:
30474 case VPSRAVDZ256rr:
30475 case VPSRAVDZ256rrk:
30476 case VPSRAVDZ256rrkz:
30477 case VPSRAVDZrm:
30478 case VPSRAVDZrmb:
30479 case VPSRAVDZrmbk:
30480 case VPSRAVDZrmbkz:
30481 case VPSRAVDZrmk:
30482 case VPSRAVDZrmkz:
30483 case VPSRAVDZrr:
30484 case VPSRAVDZrrk:
30485 case VPSRAVDZrrkz:
30486 case VPSRAVDrm:
30487 case VPSRAVDrr:
30488 return true;
30489 }
30490 return false;
30491}
30492
30493bool isVMULSH(unsigned Opcode) {
30494 switch (Opcode) {
30495 case VMULSHZrm_Int:
30496 case VMULSHZrmk_Int:
30497 case VMULSHZrmkz_Int:
30498 case VMULSHZrr_Int:
30499 case VMULSHZrrb_Int:
30500 case VMULSHZrrbk_Int:
30501 case VMULSHZrrbkz_Int:
30502 case VMULSHZrrk_Int:
30503 case VMULSHZrrkz_Int:
30504 return true;
30505 }
30506 return false;
30507}
30508
30509bool isMOVNTSS(unsigned Opcode) {
30510 return Opcode == MOVNTSS;
30511}
30512
30513bool isSTI(unsigned Opcode) {
30514 return Opcode == STI;
30515}
30516
30517bool isVSM4RNDS4(unsigned Opcode) {
30518 switch (Opcode) {
30519 case VSM4RNDS4Yrm:
30520 case VSM4RNDS4Yrr:
30521 case VSM4RNDS4Z128rm:
30522 case VSM4RNDS4Z128rr:
30523 case VSM4RNDS4Z256rm:
30524 case VSM4RNDS4Z256rr:
30525 case VSM4RNDS4Zrm:
30526 case VSM4RNDS4Zrr:
30527 case VSM4RNDS4rm:
30528 case VSM4RNDS4rr:
30529 return true;
30530 }
30531 return false;
30532}
30533
30534bool isVMCLEAR(unsigned Opcode) {
30535 return Opcode == VMCLEARm;
30536}
30537
30538bool isVPMADD52HUQ(unsigned Opcode) {
30539 switch (Opcode) {
30540 case VPMADD52HUQYrm:
30541 case VPMADD52HUQYrr:
30542 case VPMADD52HUQZ128m:
30543 case VPMADD52HUQZ128mb:
30544 case VPMADD52HUQZ128mbk:
30545 case VPMADD52HUQZ128mbkz:
30546 case VPMADD52HUQZ128mk:
30547 case VPMADD52HUQZ128mkz:
30548 case VPMADD52HUQZ128r:
30549 case VPMADD52HUQZ128rk:
30550 case VPMADD52HUQZ128rkz:
30551 case VPMADD52HUQZ256m:
30552 case VPMADD52HUQZ256mb:
30553 case VPMADD52HUQZ256mbk:
30554 case VPMADD52HUQZ256mbkz:
30555 case VPMADD52HUQZ256mk:
30556 case VPMADD52HUQZ256mkz:
30557 case VPMADD52HUQZ256r:
30558 case VPMADD52HUQZ256rk:
30559 case VPMADD52HUQZ256rkz:
30560 case VPMADD52HUQZm:
30561 case VPMADD52HUQZmb:
30562 case VPMADD52HUQZmbk:
30563 case VPMADD52HUQZmbkz:
30564 case VPMADD52HUQZmk:
30565 case VPMADD52HUQZmkz:
30566 case VPMADD52HUQZr:
30567 case VPMADD52HUQZrk:
30568 case VPMADD52HUQZrkz:
30569 case VPMADD52HUQrm:
30570 case VPMADD52HUQrr:
30571 return true;
30572 }
30573 return false;
30574}
30575
30576bool isLIDT(unsigned Opcode) {
30577 return Opcode == LIDT64m;
30578}
30579
30580bool isPUSH2(unsigned Opcode) {
30581 return Opcode == PUSH2;
30582}
30583
30584bool isVCVTPS2IUBS(unsigned Opcode) {
30585 switch (Opcode) {
30586 case VCVTPS2IUBSZ128rm:
30587 case VCVTPS2IUBSZ128rmb:
30588 case VCVTPS2IUBSZ128rmbk:
30589 case VCVTPS2IUBSZ128rmbkz:
30590 case VCVTPS2IUBSZ128rmk:
30591 case VCVTPS2IUBSZ128rmkz:
30592 case VCVTPS2IUBSZ128rr:
30593 case VCVTPS2IUBSZ128rrk:
30594 case VCVTPS2IUBSZ128rrkz:
30595 case VCVTPS2IUBSZ256rm:
30596 case VCVTPS2IUBSZ256rmb:
30597 case VCVTPS2IUBSZ256rmbk:
30598 case VCVTPS2IUBSZ256rmbkz:
30599 case VCVTPS2IUBSZ256rmk:
30600 case VCVTPS2IUBSZ256rmkz:
30601 case VCVTPS2IUBSZ256rr:
30602 case VCVTPS2IUBSZ256rrk:
30603 case VCVTPS2IUBSZ256rrkz:
30604 case VCVTPS2IUBSZrm:
30605 case VCVTPS2IUBSZrmb:
30606 case VCVTPS2IUBSZrmbk:
30607 case VCVTPS2IUBSZrmbkz:
30608 case VCVTPS2IUBSZrmk:
30609 case VCVTPS2IUBSZrmkz:
30610 case VCVTPS2IUBSZrr:
30611 case VCVTPS2IUBSZrrb:
30612 case VCVTPS2IUBSZrrbk:
30613 case VCVTPS2IUBSZrrbkz:
30614 case VCVTPS2IUBSZrrk:
30615 case VCVTPS2IUBSZrrkz:
30616 return true;
30617 }
30618 return false;
30619}
30620
30621bool isRDPKRU(unsigned Opcode) {
30622 return Opcode == RDPKRUr;
30623}
30624
30625bool isVPCMPB(unsigned Opcode) {
30626 switch (Opcode) {
30627 case VPCMPBZ128rmi:
30628 case VPCMPBZ128rmik:
30629 case VPCMPBZ128rri:
30630 case VPCMPBZ128rrik:
30631 case VPCMPBZ256rmi:
30632 case VPCMPBZ256rmik:
30633 case VPCMPBZ256rri:
30634 case VPCMPBZ256rrik:
30635 case VPCMPBZrmi:
30636 case VPCMPBZrmik:
30637 case VPCMPBZrri:
30638 case VPCMPBZrrik:
30639 return true;
30640 }
30641 return false;
30642}
30643
30644bool isVFMSUB231BF16(unsigned Opcode) {
30645 switch (Opcode) {
30646 case VFMSUB231BF16Z128m:
30647 case VFMSUB231BF16Z128mb:
30648 case VFMSUB231BF16Z128mbk:
30649 case VFMSUB231BF16Z128mbkz:
30650 case VFMSUB231BF16Z128mk:
30651 case VFMSUB231BF16Z128mkz:
30652 case VFMSUB231BF16Z128r:
30653 case VFMSUB231BF16Z128rk:
30654 case VFMSUB231BF16Z128rkz:
30655 case VFMSUB231BF16Z256m:
30656 case VFMSUB231BF16Z256mb:
30657 case VFMSUB231BF16Z256mbk:
30658 case VFMSUB231BF16Z256mbkz:
30659 case VFMSUB231BF16Z256mk:
30660 case VFMSUB231BF16Z256mkz:
30661 case VFMSUB231BF16Z256r:
30662 case VFMSUB231BF16Z256rk:
30663 case VFMSUB231BF16Z256rkz:
30664 case VFMSUB231BF16Zm:
30665 case VFMSUB231BF16Zmb:
30666 case VFMSUB231BF16Zmbk:
30667 case VFMSUB231BF16Zmbkz:
30668 case VFMSUB231BF16Zmk:
30669 case VFMSUB231BF16Zmkz:
30670 case VFMSUB231BF16Zr:
30671 case VFMSUB231BF16Zrk:
30672 case VFMSUB231BF16Zrkz:
30673 return true;
30674 }
30675 return false;
30676}
30677
30678bool isFINCSTP(unsigned Opcode) {
30679 return Opcode == FINCSTP;
30680}
30681
30682bool isKORQ(unsigned Opcode) {
30683 return Opcode == KORQkk;
30684}
30685
30686bool isXCRYPTCBC(unsigned Opcode) {
30687 return Opcode == XCRYPTCBC;
30688}
30689
30690bool isRDPMC(unsigned Opcode) {
30691 return Opcode == RDPMC;
30692}
30693
30694bool isMOVMSKPD(unsigned Opcode) {
30695 return Opcode == MOVMSKPDrr;
30696}
30697
30698bool isVFMSUB231SH(unsigned Opcode) {
30699 switch (Opcode) {
30700 case VFMSUB231SHZm_Int:
30701 case VFMSUB231SHZmk_Int:
30702 case VFMSUB231SHZmkz_Int:
30703 case VFMSUB231SHZr_Int:
30704 case VFMSUB231SHZrb_Int:
30705 case VFMSUB231SHZrbk_Int:
30706 case VFMSUB231SHZrbkz_Int:
30707 case VFMSUB231SHZrk_Int:
30708 case VFMSUB231SHZrkz_Int:
30709 return true;
30710 }
30711 return false;
30712}
30713
30714bool isVEXTRACTF128(unsigned Opcode) {
30715 switch (Opcode) {
30716 case VEXTRACTF128mri:
30717 case VEXTRACTF128rri:
30718 return true;
30719 }
30720 return false;
30721}
30722
30723bool isVPSHLB(unsigned Opcode) {
30724 switch (Opcode) {
30725 case VPSHLBmr:
30726 case VPSHLBrm:
30727 case VPSHLBrr:
30728 case VPSHLBrr_REV:
30729 return true;
30730 }
30731 return false;
30732}
30733
30734bool isXSAVES64(unsigned Opcode) {
30735 return Opcode == XSAVES64;
30736}
30737
30738bool isSHL(unsigned Opcode) {
30739 switch (Opcode) {
30740 case SHL16m1:
30741 case SHL16m1_EVEX:
30742 case SHL16m1_ND:
30743 case SHL16m1_NF:
30744 case SHL16m1_NF_ND:
30745 case SHL16mCL:
30746 case SHL16mCL_EVEX:
30747 case SHL16mCL_ND:
30748 case SHL16mCL_NF:
30749 case SHL16mCL_NF_ND:
30750 case SHL16mi:
30751 case SHL16mi_EVEX:
30752 case SHL16mi_ND:
30753 case SHL16mi_NF:
30754 case SHL16mi_NF_ND:
30755 case SHL16r1:
30756 case SHL16r1_EVEX:
30757 case SHL16r1_ND:
30758 case SHL16r1_NF:
30759 case SHL16r1_NF_ND:
30760 case SHL16rCL:
30761 case SHL16rCL_EVEX:
30762 case SHL16rCL_ND:
30763 case SHL16rCL_NF:
30764 case SHL16rCL_NF_ND:
30765 case SHL16ri:
30766 case SHL16ri_EVEX:
30767 case SHL16ri_ND:
30768 case SHL16ri_NF:
30769 case SHL16ri_NF_ND:
30770 case SHL32m1:
30771 case SHL32m1_EVEX:
30772 case SHL32m1_ND:
30773 case SHL32m1_NF:
30774 case SHL32m1_NF_ND:
30775 case SHL32mCL:
30776 case SHL32mCL_EVEX:
30777 case SHL32mCL_ND:
30778 case SHL32mCL_NF:
30779 case SHL32mCL_NF_ND:
30780 case SHL32mi:
30781 case SHL32mi_EVEX:
30782 case SHL32mi_ND:
30783 case SHL32mi_NF:
30784 case SHL32mi_NF_ND:
30785 case SHL32r1:
30786 case SHL32r1_EVEX:
30787 case SHL32r1_ND:
30788 case SHL32r1_NF:
30789 case SHL32r1_NF_ND:
30790 case SHL32rCL:
30791 case SHL32rCL_EVEX:
30792 case SHL32rCL_ND:
30793 case SHL32rCL_NF:
30794 case SHL32rCL_NF_ND:
30795 case SHL32ri:
30796 case SHL32ri_EVEX:
30797 case SHL32ri_ND:
30798 case SHL32ri_NF:
30799 case SHL32ri_NF_ND:
30800 case SHL64m1:
30801 case SHL64m1_EVEX:
30802 case SHL64m1_ND:
30803 case SHL64m1_NF:
30804 case SHL64m1_NF_ND:
30805 case SHL64mCL:
30806 case SHL64mCL_EVEX:
30807 case SHL64mCL_ND:
30808 case SHL64mCL_NF:
30809 case SHL64mCL_NF_ND:
30810 case SHL64mi:
30811 case SHL64mi_EVEX:
30812 case SHL64mi_ND:
30813 case SHL64mi_NF:
30814 case SHL64mi_NF_ND:
30815 case SHL64r1:
30816 case SHL64r1_EVEX:
30817 case SHL64r1_ND:
30818 case SHL64r1_NF:
30819 case SHL64r1_NF_ND:
30820 case SHL64rCL:
30821 case SHL64rCL_EVEX:
30822 case SHL64rCL_ND:
30823 case SHL64rCL_NF:
30824 case SHL64rCL_NF_ND:
30825 case SHL64ri:
30826 case SHL64ri_EVEX:
30827 case SHL64ri_ND:
30828 case SHL64ri_NF:
30829 case SHL64ri_NF_ND:
30830 case SHL8m1:
30831 case SHL8m1_EVEX:
30832 case SHL8m1_ND:
30833 case SHL8m1_NF:
30834 case SHL8m1_NF_ND:
30835 case SHL8mCL:
30836 case SHL8mCL_EVEX:
30837 case SHL8mCL_ND:
30838 case SHL8mCL_NF:
30839 case SHL8mCL_NF_ND:
30840 case SHL8mi:
30841 case SHL8mi_EVEX:
30842 case SHL8mi_ND:
30843 case SHL8mi_NF:
30844 case SHL8mi_NF_ND:
30845 case SHL8r1:
30846 case SHL8r1_EVEX:
30847 case SHL8r1_ND:
30848 case SHL8r1_NF:
30849 case SHL8r1_NF_ND:
30850 case SHL8rCL:
30851 case SHL8rCL_EVEX:
30852 case SHL8rCL_ND:
30853 case SHL8rCL_NF:
30854 case SHL8rCL_NF_ND:
30855 case SHL8ri:
30856 case SHL8ri_EVEX:
30857 case SHL8ri_ND:
30858 case SHL8ri_NF:
30859 case SHL8ri_NF_ND:
30860 return true;
30861 }
30862 return false;
30863}
30864
30865bool isAXOR(unsigned Opcode) {
30866 switch (Opcode) {
30867 case AXOR32mr:
30868 case AXOR32mr_EVEX:
30869 case AXOR64mr:
30870 case AXOR64mr_EVEX:
30871 return true;
30872 }
30873 return false;
30874}
30875
30876bool isVINSERTI64X2(unsigned Opcode) {
30877 switch (Opcode) {
30878 case VINSERTI64X2Z256rmi:
30879 case VINSERTI64X2Z256rmik:
30880 case VINSERTI64X2Z256rmikz:
30881 case VINSERTI64X2Z256rri:
30882 case VINSERTI64X2Z256rrik:
30883 case VINSERTI64X2Z256rrikz:
30884 case VINSERTI64X2Zrmi:
30885 case VINSERTI64X2Zrmik:
30886 case VINSERTI64X2Zrmikz:
30887 case VINSERTI64X2Zrri:
30888 case VINSERTI64X2Zrrik:
30889 case VINSERTI64X2Zrrikz:
30890 return true;
30891 }
30892 return false;
30893}
30894
30895bool isSYSRETQ(unsigned Opcode) {
30896 return Opcode == SYSRET64;
30897}
30898
30899bool isVSCATTERPF0QPD(unsigned Opcode) {
30900 return Opcode == VSCATTERPF0QPDm;
30901}
30902
30903bool isVFMSUB213SH(unsigned Opcode) {
30904 switch (Opcode) {
30905 case VFMSUB213SHZm_Int:
30906 case VFMSUB213SHZmk_Int:
30907 case VFMSUB213SHZmkz_Int:
30908 case VFMSUB213SHZr_Int:
30909 case VFMSUB213SHZrb_Int:
30910 case VFMSUB213SHZrbk_Int:
30911 case VFMSUB213SHZrbkz_Int:
30912 case VFMSUB213SHZrk_Int:
30913 case VFMSUB213SHZrkz_Int:
30914 return true;
30915 }
30916 return false;
30917}
30918
30919bool isVPMOVQW(unsigned Opcode) {
30920 switch (Opcode) {
30921 case VPMOVQWZ128mr:
30922 case VPMOVQWZ128mrk:
30923 case VPMOVQWZ128rr:
30924 case VPMOVQWZ128rrk:
30925 case VPMOVQWZ128rrkz:
30926 case VPMOVQWZ256mr:
30927 case VPMOVQWZ256mrk:
30928 case VPMOVQWZ256rr:
30929 case VPMOVQWZ256rrk:
30930 case VPMOVQWZ256rrkz:
30931 case VPMOVQWZmr:
30932 case VPMOVQWZmrk:
30933 case VPMOVQWZrr:
30934 case VPMOVQWZrrk:
30935 case VPMOVQWZrrkz:
30936 return true;
30937 }
30938 return false;
30939}
30940
30941bool isVREDUCEPD(unsigned Opcode) {
30942 switch (Opcode) {
30943 case VREDUCEPDZ128rmbi:
30944 case VREDUCEPDZ128rmbik:
30945 case VREDUCEPDZ128rmbikz:
30946 case VREDUCEPDZ128rmi:
30947 case VREDUCEPDZ128rmik:
30948 case VREDUCEPDZ128rmikz:
30949 case VREDUCEPDZ128rri:
30950 case VREDUCEPDZ128rrik:
30951 case VREDUCEPDZ128rrikz:
30952 case VREDUCEPDZ256rmbi:
30953 case VREDUCEPDZ256rmbik:
30954 case VREDUCEPDZ256rmbikz:
30955 case VREDUCEPDZ256rmi:
30956 case VREDUCEPDZ256rmik:
30957 case VREDUCEPDZ256rmikz:
30958 case VREDUCEPDZ256rri:
30959 case VREDUCEPDZ256rrik:
30960 case VREDUCEPDZ256rrikz:
30961 case VREDUCEPDZrmbi:
30962 case VREDUCEPDZrmbik:
30963 case VREDUCEPDZrmbikz:
30964 case VREDUCEPDZrmi:
30965 case VREDUCEPDZrmik:
30966 case VREDUCEPDZrmikz:
30967 case VREDUCEPDZrri:
30968 case VREDUCEPDZrrib:
30969 case VREDUCEPDZrribk:
30970 case VREDUCEPDZrribkz:
30971 case VREDUCEPDZrrik:
30972 case VREDUCEPDZrrikz:
30973 return true;
30974 }
30975 return false;
30976}
30977
30978bool isNOT(unsigned Opcode) {
30979 switch (Opcode) {
30980 case NOT16m:
30981 case NOT16m_EVEX:
30982 case NOT16m_ND:
30983 case NOT16r:
30984 case NOT16r_EVEX:
30985 case NOT16r_ND:
30986 case NOT32m:
30987 case NOT32m_EVEX:
30988 case NOT32m_ND:
30989 case NOT32r:
30990 case NOT32r_EVEX:
30991 case NOT32r_ND:
30992 case NOT64m:
30993 case NOT64m_EVEX:
30994 case NOT64m_ND:
30995 case NOT64r:
30996 case NOT64r_EVEX:
30997 case NOT64r_ND:
30998 case NOT8m:
30999 case NOT8m_EVEX:
31000 case NOT8m_ND:
31001 case NOT8r:
31002 case NOT8r_EVEX:
31003 case NOT8r_ND:
31004 return true;
31005 }
31006 return false;
31007}
31008
31009bool isLWPINS(unsigned Opcode) {
31010 switch (Opcode) {
31011 case LWPINS32rmi:
31012 case LWPINS32rri:
31013 case LWPINS64rmi:
31014 case LWPINS64rri:
31015 return true;
31016 }
31017 return false;
31018}
31019
31020bool isVSCATTERDPS(unsigned Opcode) {
31021 switch (Opcode) {
31022 case VSCATTERDPSZ128mr:
31023 case VSCATTERDPSZ256mr:
31024 case VSCATTERDPSZmr:
31025 return true;
31026 }
31027 return false;
31028}
31029
31030bool isVPMOVM2W(unsigned Opcode) {
31031 switch (Opcode) {
31032 case VPMOVM2WZ128rk:
31033 case VPMOVM2WZ256rk:
31034 case VPMOVM2WZrk:
31035 return true;
31036 }
31037 return false;
31038}
31039
31040bool isVFNMADD132PS(unsigned Opcode) {
31041 switch (Opcode) {
31042 case VFNMADD132PSYm:
31043 case VFNMADD132PSYr:
31044 case VFNMADD132PSZ128m:
31045 case VFNMADD132PSZ128mb:
31046 case VFNMADD132PSZ128mbk:
31047 case VFNMADD132PSZ128mbkz:
31048 case VFNMADD132PSZ128mk:
31049 case VFNMADD132PSZ128mkz:
31050 case VFNMADD132PSZ128r:
31051 case VFNMADD132PSZ128rk:
31052 case VFNMADD132PSZ128rkz:
31053 case VFNMADD132PSZ256m:
31054 case VFNMADD132PSZ256mb:
31055 case VFNMADD132PSZ256mbk:
31056 case VFNMADD132PSZ256mbkz:
31057 case VFNMADD132PSZ256mk:
31058 case VFNMADD132PSZ256mkz:
31059 case VFNMADD132PSZ256r:
31060 case VFNMADD132PSZ256rk:
31061 case VFNMADD132PSZ256rkz:
31062 case VFNMADD132PSZm:
31063 case VFNMADD132PSZmb:
31064 case VFNMADD132PSZmbk:
31065 case VFNMADD132PSZmbkz:
31066 case VFNMADD132PSZmk:
31067 case VFNMADD132PSZmkz:
31068 case VFNMADD132PSZr:
31069 case VFNMADD132PSZrb:
31070 case VFNMADD132PSZrbk:
31071 case VFNMADD132PSZrbkz:
31072 case VFNMADD132PSZrk:
31073 case VFNMADD132PSZrkz:
31074 case VFNMADD132PSm:
31075 case VFNMADD132PSr:
31076 return true;
31077 }
31078 return false;
31079}
31080
31081bool isMOVNTPS(unsigned Opcode) {
31082 return Opcode == MOVNTPSmr;
31083}
31084
31085bool isVRSQRTSS(unsigned Opcode) {
31086 switch (Opcode) {
31087 case VRSQRTSSm_Int:
31088 case VRSQRTSSr_Int:
31089 return true;
31090 }
31091 return false;
31092}
31093
31094bool isKMOVB(unsigned Opcode) {
31095 switch (Opcode) {
31096 case KMOVBkk:
31097 case KMOVBkk_EVEX:
31098 case KMOVBkm:
31099 case KMOVBkm_EVEX:
31100 case KMOVBkr:
31101 case KMOVBkr_EVEX:
31102 case KMOVBmk:
31103 case KMOVBmk_EVEX:
31104 case KMOVBrk:
31105 case KMOVBrk_EVEX:
31106 return true;
31107 }
31108 return false;
31109}
31110
31111bool isCVTSD2SS(unsigned Opcode) {
31112 switch (Opcode) {
31113 case CVTSD2SSrm_Int:
31114 case CVTSD2SSrr_Int:
31115 return true;
31116 }
31117 return false;
31118}
31119
31120bool isVBROADCASTF64X2(unsigned Opcode) {
31121 switch (Opcode) {
31122 case VBROADCASTF64X2Z256rm:
31123 case VBROADCASTF64X2Z256rmk:
31124 case VBROADCASTF64X2Z256rmkz:
31125 case VBROADCASTF64X2Zrm:
31126 case VBROADCASTF64X2Zrmk:
31127 case VBROADCASTF64X2Zrmkz:
31128 return true;
31129 }
31130 return false;
31131}
31132
31133bool isMOVNTPD(unsigned Opcode) {
31134 return Opcode == MOVNTPDmr;
31135}
31136
31137bool isMAXSD(unsigned Opcode) {
31138 switch (Opcode) {
31139 case MAXSDrm_Int:
31140 case MAXSDrr_Int:
31141 return true;
31142 }
31143 return false;
31144}
31145
31146bool isCMPPD(unsigned Opcode) {
31147 switch (Opcode) {
31148 case CMPPDrmi:
31149 case CMPPDrri:
31150 return true;
31151 }
31152 return false;
31153}
31154
31155bool isVPCMPESTRM(unsigned Opcode) {
31156 switch (Opcode) {
31157 case VPCMPESTRMrmi:
31158 case VPCMPESTRMrri:
31159 return true;
31160 }
31161 return false;
31162}
31163
31164bool isVFMSUB132PS(unsigned Opcode) {
31165 switch (Opcode) {
31166 case VFMSUB132PSYm:
31167 case VFMSUB132PSYr:
31168 case VFMSUB132PSZ128m:
31169 case VFMSUB132PSZ128mb:
31170 case VFMSUB132PSZ128mbk:
31171 case VFMSUB132PSZ128mbkz:
31172 case VFMSUB132PSZ128mk:
31173 case VFMSUB132PSZ128mkz:
31174 case VFMSUB132PSZ128r:
31175 case VFMSUB132PSZ128rk:
31176 case VFMSUB132PSZ128rkz:
31177 case VFMSUB132PSZ256m:
31178 case VFMSUB132PSZ256mb:
31179 case VFMSUB132PSZ256mbk:
31180 case VFMSUB132PSZ256mbkz:
31181 case VFMSUB132PSZ256mk:
31182 case VFMSUB132PSZ256mkz:
31183 case VFMSUB132PSZ256r:
31184 case VFMSUB132PSZ256rk:
31185 case VFMSUB132PSZ256rkz:
31186 case VFMSUB132PSZm:
31187 case VFMSUB132PSZmb:
31188 case VFMSUB132PSZmbk:
31189 case VFMSUB132PSZmbkz:
31190 case VFMSUB132PSZmk:
31191 case VFMSUB132PSZmkz:
31192 case VFMSUB132PSZr:
31193 case VFMSUB132PSZrb:
31194 case VFMSUB132PSZrbk:
31195 case VFMSUB132PSZrbkz:
31196 case VFMSUB132PSZrk:
31197 case VFMSUB132PSZrkz:
31198 case VFMSUB132PSm:
31199 case VFMSUB132PSr:
31200 return true;
31201 }
31202 return false;
31203}
31204
31205bool isVCOMISH(unsigned Opcode) {
31206 switch (Opcode) {
31207 case VCOMISHZrm:
31208 case VCOMISHZrr:
31209 case VCOMISHZrrb:
31210 return true;
31211 }
31212 return false;
31213}
31214
31215bool isF2XM1(unsigned Opcode) {
31216 return Opcode == F2XM1;
31217}
31218
31219bool isVDIVBF16(unsigned Opcode) {
31220 switch (Opcode) {
31221 case VDIVBF16Z128rm:
31222 case VDIVBF16Z128rmb:
31223 case VDIVBF16Z128rmbk:
31224 case VDIVBF16Z128rmbkz:
31225 case VDIVBF16Z128rmk:
31226 case VDIVBF16Z128rmkz:
31227 case VDIVBF16Z128rr:
31228 case VDIVBF16Z128rrk:
31229 case VDIVBF16Z128rrkz:
31230 case VDIVBF16Z256rm:
31231 case VDIVBF16Z256rmb:
31232 case VDIVBF16Z256rmbk:
31233 case VDIVBF16Z256rmbkz:
31234 case VDIVBF16Z256rmk:
31235 case VDIVBF16Z256rmkz:
31236 case VDIVBF16Z256rr:
31237 case VDIVBF16Z256rrk:
31238 case VDIVBF16Z256rrkz:
31239 case VDIVBF16Zrm:
31240 case VDIVBF16Zrmb:
31241 case VDIVBF16Zrmbk:
31242 case VDIVBF16Zrmbkz:
31243 case VDIVBF16Zrmk:
31244 case VDIVBF16Zrmkz:
31245 case VDIVBF16Zrr:
31246 case VDIVBF16Zrrk:
31247 case VDIVBF16Zrrkz:
31248 return true;
31249 }
31250 return false;
31251}
31252
31253bool isSQRTPD(unsigned Opcode) {
31254 switch (Opcode) {
31255 case SQRTPDm:
31256 case SQRTPDr:
31257 return true;
31258 }
31259 return false;
31260}
31261
31262bool isVFMSUBADDPS(unsigned Opcode) {
31263 switch (Opcode) {
31264 case VFMSUBADDPS4Ymr:
31265 case VFMSUBADDPS4Yrm:
31266 case VFMSUBADDPS4Yrr:
31267 case VFMSUBADDPS4Yrr_REV:
31268 case VFMSUBADDPS4mr:
31269 case VFMSUBADDPS4rm:
31270 case VFMSUBADDPS4rr:
31271 case VFMSUBADDPS4rr_REV:
31272 return true;
31273 }
31274 return false;
31275}
31276
31277bool isFXTRACT(unsigned Opcode) {
31278 return Opcode == FXTRACT;
31279}
31280
31281bool isVP4DPWSSD(unsigned Opcode) {
31282 switch (Opcode) {
31283 case VP4DPWSSDrm:
31284 case VP4DPWSSDrmk:
31285 case VP4DPWSSDrmkz:
31286 return true;
31287 }
31288 return false;
31289}
31290
31291bool isTDPBHF8PS(unsigned Opcode) {
31292 return Opcode == TDPBHF8PS;
31293}
31294
31295bool isVFMSUBADDPD(unsigned Opcode) {
31296 switch (Opcode) {
31297 case VFMSUBADDPD4Ymr:
31298 case VFMSUBADDPD4Yrm:
31299 case VFMSUBADDPD4Yrr:
31300 case VFMSUBADDPD4Yrr_REV:
31301 case VFMSUBADDPD4mr:
31302 case VFMSUBADDPD4rm:
31303 case VFMSUBADDPD4rr:
31304 case VFMSUBADDPD4rr_REV:
31305 return true;
31306 }
31307 return false;
31308}
31309
31310bool isVBCSTNEBF162PS(unsigned Opcode) {
31311 switch (Opcode) {
31312 case VBCSTNEBF162PSYrm:
31313 case VBCSTNEBF162PSrm:
31314 return true;
31315 }
31316 return false;
31317}
31318
31319bool isVPGATHERQQ(unsigned Opcode) {
31320 switch (Opcode) {
31321 case VPGATHERQQYrm:
31322 case VPGATHERQQZ128rm:
31323 case VPGATHERQQZ256rm:
31324 case VPGATHERQQZrm:
31325 case VPGATHERQQrm:
31326 return true;
31327 }
31328 return false;
31329}
31330
31331bool isPCMPEQB(unsigned Opcode) {
31332 switch (Opcode) {
31333 case MMX_PCMPEQBrm:
31334 case MMX_PCMPEQBrr:
31335 case PCMPEQBrm:
31336 case PCMPEQBrr:
31337 return true;
31338 }
31339 return false;
31340}
31341
31342bool isTILESTORED(unsigned Opcode) {
31343 switch (Opcode) {
31344 case TILESTORED:
31345 case TILESTORED_EVEX:
31346 return true;
31347 }
31348 return false;
31349}
31350
31351bool isBLSMSK(unsigned Opcode) {
31352 switch (Opcode) {
31353 case BLSMSK32rm:
31354 case BLSMSK32rm_EVEX:
31355 case BLSMSK32rm_NF:
31356 case BLSMSK32rr:
31357 case BLSMSK32rr_EVEX:
31358 case BLSMSK32rr_NF:
31359 case BLSMSK64rm:
31360 case BLSMSK64rm_EVEX:
31361 case BLSMSK64rm_NF:
31362 case BLSMSK64rr:
31363 case BLSMSK64rr_EVEX:
31364 case BLSMSK64rr_NF:
31365 return true;
31366 }
31367 return false;
31368}
31369
31370bool isVCVTTPS2DQ(unsigned Opcode) {
31371 switch (Opcode) {
31372 case VCVTTPS2DQYrm:
31373 case VCVTTPS2DQYrr:
31374 case VCVTTPS2DQZ128rm:
31375 case VCVTTPS2DQZ128rmb:
31376 case VCVTTPS2DQZ128rmbk:
31377 case VCVTTPS2DQZ128rmbkz:
31378 case VCVTTPS2DQZ128rmk:
31379 case VCVTTPS2DQZ128rmkz:
31380 case VCVTTPS2DQZ128rr:
31381 case VCVTTPS2DQZ128rrk:
31382 case VCVTTPS2DQZ128rrkz:
31383 case VCVTTPS2DQZ256rm:
31384 case VCVTTPS2DQZ256rmb:
31385 case VCVTTPS2DQZ256rmbk:
31386 case VCVTTPS2DQZ256rmbkz:
31387 case VCVTTPS2DQZ256rmk:
31388 case VCVTTPS2DQZ256rmkz:
31389 case VCVTTPS2DQZ256rr:
31390 case VCVTTPS2DQZ256rrk:
31391 case VCVTTPS2DQZ256rrkz:
31392 case VCVTTPS2DQZrm:
31393 case VCVTTPS2DQZrmb:
31394 case VCVTTPS2DQZrmbk:
31395 case VCVTTPS2DQZrmbkz:
31396 case VCVTTPS2DQZrmk:
31397 case VCVTTPS2DQZrmkz:
31398 case VCVTTPS2DQZrr:
31399 case VCVTTPS2DQZrrb:
31400 case VCVTTPS2DQZrrbk:
31401 case VCVTTPS2DQZrrbkz:
31402 case VCVTTPS2DQZrrk:
31403 case VCVTTPS2DQZrrkz:
31404 case VCVTTPS2DQrm:
31405 case VCVTTPS2DQrr:
31406 return true;
31407 }
31408 return false;
31409}
31410
31411bool isVRNDSCALEPD(unsigned Opcode) {
31412 switch (Opcode) {
31413 case VRNDSCALEPDZ128rmbi:
31414 case VRNDSCALEPDZ128rmbik:
31415 case VRNDSCALEPDZ128rmbikz:
31416 case VRNDSCALEPDZ128rmi:
31417 case VRNDSCALEPDZ128rmik:
31418 case VRNDSCALEPDZ128rmikz:
31419 case VRNDSCALEPDZ128rri:
31420 case VRNDSCALEPDZ128rrik:
31421 case VRNDSCALEPDZ128rrikz:
31422 case VRNDSCALEPDZ256rmbi:
31423 case VRNDSCALEPDZ256rmbik:
31424 case VRNDSCALEPDZ256rmbikz:
31425 case VRNDSCALEPDZ256rmi:
31426 case VRNDSCALEPDZ256rmik:
31427 case VRNDSCALEPDZ256rmikz:
31428 case VRNDSCALEPDZ256rri:
31429 case VRNDSCALEPDZ256rrik:
31430 case VRNDSCALEPDZ256rrikz:
31431 case VRNDSCALEPDZrmbi:
31432 case VRNDSCALEPDZrmbik:
31433 case VRNDSCALEPDZrmbikz:
31434 case VRNDSCALEPDZrmi:
31435 case VRNDSCALEPDZrmik:
31436 case VRNDSCALEPDZrmikz:
31437 case VRNDSCALEPDZrri:
31438 case VRNDSCALEPDZrrib:
31439 case VRNDSCALEPDZrribk:
31440 case VRNDSCALEPDZrribkz:
31441 case VRNDSCALEPDZrrik:
31442 case VRNDSCALEPDZrrikz:
31443 return true;
31444 }
31445 return false;
31446}
31447
31448bool isVFPCLASSBF16(unsigned Opcode) {
31449 switch (Opcode) {
31450 case VFPCLASSBF16Z128mbi:
31451 case VFPCLASSBF16Z128mbik:
31452 case VFPCLASSBF16Z128mi:
31453 case VFPCLASSBF16Z128mik:
31454 case VFPCLASSBF16Z128ri:
31455 case VFPCLASSBF16Z128rik:
31456 case VFPCLASSBF16Z256mbi:
31457 case VFPCLASSBF16Z256mbik:
31458 case VFPCLASSBF16Z256mi:
31459 case VFPCLASSBF16Z256mik:
31460 case VFPCLASSBF16Z256ri:
31461 case VFPCLASSBF16Z256rik:
31462 case VFPCLASSBF16Zmbi:
31463 case VFPCLASSBF16Zmbik:
31464 case VFPCLASSBF16Zmi:
31465 case VFPCLASSBF16Zmik:
31466 case VFPCLASSBF16Zri:
31467 case VFPCLASSBF16Zrik:
31468 return true;
31469 }
31470 return false;
31471}
31472
31473bool isVMLOAD(unsigned Opcode) {
31474 switch (Opcode) {
31475 case VMLOAD32:
31476 case VMLOAD64:
31477 return true;
31478 }
31479 return false;
31480}
31481
31482bool isVPTERNLOGQ(unsigned Opcode) {
31483 switch (Opcode) {
31484 case VPTERNLOGQZ128rmbi:
31485 case VPTERNLOGQZ128rmbik:
31486 case VPTERNLOGQZ128rmbikz:
31487 case VPTERNLOGQZ128rmi:
31488 case VPTERNLOGQZ128rmik:
31489 case VPTERNLOGQZ128rmikz:
31490 case VPTERNLOGQZ128rri:
31491 case VPTERNLOGQZ128rrik:
31492 case VPTERNLOGQZ128rrikz:
31493 case VPTERNLOGQZ256rmbi:
31494 case VPTERNLOGQZ256rmbik:
31495 case VPTERNLOGQZ256rmbikz:
31496 case VPTERNLOGQZ256rmi:
31497 case VPTERNLOGQZ256rmik:
31498 case VPTERNLOGQZ256rmikz:
31499 case VPTERNLOGQZ256rri:
31500 case VPTERNLOGQZ256rrik:
31501 case VPTERNLOGQZ256rrikz:
31502 case VPTERNLOGQZrmbi:
31503 case VPTERNLOGQZrmbik:
31504 case VPTERNLOGQZrmbikz:
31505 case VPTERNLOGQZrmi:
31506 case VPTERNLOGQZrmik:
31507 case VPTERNLOGQZrmikz:
31508 case VPTERNLOGQZrri:
31509 case VPTERNLOGQZrrik:
31510 case VPTERNLOGQZrrikz:
31511 return true;
31512 }
31513 return false;
31514}
31515
31516bool isKXNORD(unsigned Opcode) {
31517 return Opcode == KXNORDkk;
31518}
31519
31520bool isFXSAVE(unsigned Opcode) {
31521 return Opcode == FXSAVE;
31522}
31523
31524bool isVUNPCKHPD(unsigned Opcode) {
31525 switch (Opcode) {
31526 case VUNPCKHPDYrm:
31527 case VUNPCKHPDYrr:
31528 case VUNPCKHPDZ128rm:
31529 case VUNPCKHPDZ128rmb:
31530 case VUNPCKHPDZ128rmbk:
31531 case VUNPCKHPDZ128rmbkz:
31532 case VUNPCKHPDZ128rmk:
31533 case VUNPCKHPDZ128rmkz:
31534 case VUNPCKHPDZ128rr:
31535 case VUNPCKHPDZ128rrk:
31536 case VUNPCKHPDZ128rrkz:
31537 case VUNPCKHPDZ256rm:
31538 case VUNPCKHPDZ256rmb:
31539 case VUNPCKHPDZ256rmbk:
31540 case VUNPCKHPDZ256rmbkz:
31541 case VUNPCKHPDZ256rmk:
31542 case VUNPCKHPDZ256rmkz:
31543 case VUNPCKHPDZ256rr:
31544 case VUNPCKHPDZ256rrk:
31545 case VUNPCKHPDZ256rrkz:
31546 case VUNPCKHPDZrm:
31547 case VUNPCKHPDZrmb:
31548 case VUNPCKHPDZrmbk:
31549 case VUNPCKHPDZrmbkz:
31550 case VUNPCKHPDZrmk:
31551 case VUNPCKHPDZrmkz:
31552 case VUNPCKHPDZrr:
31553 case VUNPCKHPDZrrk:
31554 case VUNPCKHPDZrrkz:
31555 case VUNPCKHPDrm:
31556 case VUNPCKHPDrr:
31557 return true;
31558 }
31559 return false;
31560}
31561
31562bool isCVTPS2DQ(unsigned Opcode) {
31563 switch (Opcode) {
31564 case CVTPS2DQrm:
31565 case CVTPS2DQrr:
31566 return true;
31567 }
31568 return false;
31569}
31570
31571bool isTMMULTF32PS(unsigned Opcode) {
31572 return Opcode == TMMULTF32PS;
31573}
31574
31575bool isVFMSUB213SS(unsigned Opcode) {
31576 switch (Opcode) {
31577 case VFMSUB213SSZm_Int:
31578 case VFMSUB213SSZmk_Int:
31579 case VFMSUB213SSZmkz_Int:
31580 case VFMSUB213SSZr_Int:
31581 case VFMSUB213SSZrb_Int:
31582 case VFMSUB213SSZrbk_Int:
31583 case VFMSUB213SSZrbkz_Int:
31584 case VFMSUB213SSZrk_Int:
31585 case VFMSUB213SSZrkz_Int:
31586 case VFMSUB213SSm_Int:
31587 case VFMSUB213SSr_Int:
31588 return true;
31589 }
31590 return false;
31591}
31592
31593bool isVPOPCNTD(unsigned Opcode) {
31594 switch (Opcode) {
31595 case VPOPCNTDZ128rm:
31596 case VPOPCNTDZ128rmb:
31597 case VPOPCNTDZ128rmbk:
31598 case VPOPCNTDZ128rmbkz:
31599 case VPOPCNTDZ128rmk:
31600 case VPOPCNTDZ128rmkz:
31601 case VPOPCNTDZ128rr:
31602 case VPOPCNTDZ128rrk:
31603 case VPOPCNTDZ128rrkz:
31604 case VPOPCNTDZ256rm:
31605 case VPOPCNTDZ256rmb:
31606 case VPOPCNTDZ256rmbk:
31607 case VPOPCNTDZ256rmbkz:
31608 case VPOPCNTDZ256rmk:
31609 case VPOPCNTDZ256rmkz:
31610 case VPOPCNTDZ256rr:
31611 case VPOPCNTDZ256rrk:
31612 case VPOPCNTDZ256rrkz:
31613 case VPOPCNTDZrm:
31614 case VPOPCNTDZrmb:
31615 case VPOPCNTDZrmbk:
31616 case VPOPCNTDZrmbkz:
31617 case VPOPCNTDZrmk:
31618 case VPOPCNTDZrmkz:
31619 case VPOPCNTDZrr:
31620 case VPOPCNTDZrrk:
31621 case VPOPCNTDZrrkz:
31622 return true;
31623 }
31624 return false;
31625}
31626
31627bool isSALC(unsigned Opcode) {
31628 return Opcode == SALC;
31629}
31630
31631bool isV4FNMADDSS(unsigned Opcode) {
31632 switch (Opcode) {
31633 case V4FNMADDSSrm:
31634 case V4FNMADDSSrmk:
31635 case V4FNMADDSSrmkz:
31636 return true;
31637 }
31638 return false;
31639}
31640
31641bool isXCRYPTOFB(unsigned Opcode) {
31642 return Opcode == XCRYPTOFB;
31643}
31644
31645bool isVORPD(unsigned Opcode) {
31646 switch (Opcode) {
31647 case VORPDYrm:
31648 case VORPDYrr:
31649 case VORPDZ128rm:
31650 case VORPDZ128rmb:
31651 case VORPDZ128rmbk:
31652 case VORPDZ128rmbkz:
31653 case VORPDZ128rmk:
31654 case VORPDZ128rmkz:
31655 case VORPDZ128rr:
31656 case VORPDZ128rrk:
31657 case VORPDZ128rrkz:
31658 case VORPDZ256rm:
31659 case VORPDZ256rmb:
31660 case VORPDZ256rmbk:
31661 case VORPDZ256rmbkz:
31662 case VORPDZ256rmk:
31663 case VORPDZ256rmkz:
31664 case VORPDZ256rr:
31665 case VORPDZ256rrk:
31666 case VORPDZ256rrkz:
31667 case VORPDZrm:
31668 case VORPDZrmb:
31669 case VORPDZrmbk:
31670 case VORPDZrmbkz:
31671 case VORPDZrmk:
31672 case VORPDZrmkz:
31673 case VORPDZrr:
31674 case VORPDZrrk:
31675 case VORPDZrrkz:
31676 case VORPDrm:
31677 case VORPDrr:
31678 return true;
31679 }
31680 return false;
31681}
31682
31683bool isLSL(unsigned Opcode) {
31684 switch (Opcode) {
31685 case LSL16rm:
31686 case LSL16rr:
31687 case LSL32rm:
31688 case LSL32rr:
31689 case LSL64rm:
31690 case LSL64rr:
31691 return true;
31692 }
31693 return false;
31694}
31695
31696bool isXCRYPTCFB(unsigned Opcode) {
31697 return Opcode == XCRYPTCFB;
31698}
31699
31700bool isVGETEXPSS(unsigned Opcode) {
31701 switch (Opcode) {
31702 case VGETEXPSSZm:
31703 case VGETEXPSSZmk:
31704 case VGETEXPSSZmkz:
31705 case VGETEXPSSZr:
31706 case VGETEXPSSZrb:
31707 case VGETEXPSSZrbk:
31708 case VGETEXPSSZrbkz:
31709 case VGETEXPSSZrk:
31710 case VGETEXPSSZrkz:
31711 return true;
31712 }
31713 return false;
31714}
31715
31716bool isPSLLDQ(unsigned Opcode) {
31717 return Opcode == PSLLDQri;
31718}
31719
31720bool isVPDPBUUD(unsigned Opcode) {
31721 switch (Opcode) {
31722 case VPDPBUUDYrm:
31723 case VPDPBUUDYrr:
31724 case VPDPBUUDZ128rm:
31725 case VPDPBUUDZ128rmb:
31726 case VPDPBUUDZ128rmbk:
31727 case VPDPBUUDZ128rmbkz:
31728 case VPDPBUUDZ128rmk:
31729 case VPDPBUUDZ128rmkz:
31730 case VPDPBUUDZ128rr:
31731 case VPDPBUUDZ128rrk:
31732 case VPDPBUUDZ128rrkz:
31733 case VPDPBUUDZ256rm:
31734 case VPDPBUUDZ256rmb:
31735 case VPDPBUUDZ256rmbk:
31736 case VPDPBUUDZ256rmbkz:
31737 case VPDPBUUDZ256rmk:
31738 case VPDPBUUDZ256rmkz:
31739 case VPDPBUUDZ256rr:
31740 case VPDPBUUDZ256rrk:
31741 case VPDPBUUDZ256rrkz:
31742 case VPDPBUUDZrm:
31743 case VPDPBUUDZrmb:
31744 case VPDPBUUDZrmbk:
31745 case VPDPBUUDZrmbkz:
31746 case VPDPBUUDZrmk:
31747 case VPDPBUUDZrmkz:
31748 case VPDPBUUDZrr:
31749 case VPDPBUUDZrrk:
31750 case VPDPBUUDZrrkz:
31751 case VPDPBUUDrm:
31752 case VPDPBUUDrr:
31753 return true;
31754 }
31755 return false;
31756}
31757
31758bool isVMXOFF(unsigned Opcode) {
31759 return Opcode == VMXOFF;
31760}
31761
31762bool isBLSIC(unsigned Opcode) {
31763 switch (Opcode) {
31764 case BLSIC32rm:
31765 case BLSIC32rr:
31766 case BLSIC64rm:
31767 case BLSIC64rr:
31768 return true;
31769 }
31770 return false;
31771}
31772
31773bool isMOVLHPS(unsigned Opcode) {
31774 return Opcode == MOVLHPSrr;
31775}
31776
31777bool isVMOVRSQ(unsigned Opcode) {
31778 switch (Opcode) {
31779 case VMOVRSQZ128m:
31780 case VMOVRSQZ128mk:
31781 case VMOVRSQZ128mkz:
31782 case VMOVRSQZ256m:
31783 case VMOVRSQZ256mk:
31784 case VMOVRSQZ256mkz:
31785 case VMOVRSQZm:
31786 case VMOVRSQZmk:
31787 case VMOVRSQZmkz:
31788 return true;
31789 }
31790 return false;
31791}
31792
31793bool isVFNMSUBSD(unsigned Opcode) {
31794 switch (Opcode) {
31795 case VFNMSUBSD4mr:
31796 case VFNMSUBSD4rm:
31797 case VFNMSUBSD4rr:
31798 case VFNMSUBSD4rr_REV:
31799 return true;
31800 }
31801 return false;
31802}
31803
31804bool isVCVTPH2IUBS(unsigned Opcode) {
31805 switch (Opcode) {
31806 case VCVTPH2IUBSZ128rm:
31807 case VCVTPH2IUBSZ128rmb:
31808 case VCVTPH2IUBSZ128rmbk:
31809 case VCVTPH2IUBSZ128rmbkz:
31810 case VCVTPH2IUBSZ128rmk:
31811 case VCVTPH2IUBSZ128rmkz:
31812 case VCVTPH2IUBSZ128rr:
31813 case VCVTPH2IUBSZ128rrk:
31814 case VCVTPH2IUBSZ128rrkz:
31815 case VCVTPH2IUBSZ256rm:
31816 case VCVTPH2IUBSZ256rmb:
31817 case VCVTPH2IUBSZ256rmbk:
31818 case VCVTPH2IUBSZ256rmbkz:
31819 case VCVTPH2IUBSZ256rmk:
31820 case VCVTPH2IUBSZ256rmkz:
31821 case VCVTPH2IUBSZ256rr:
31822 case VCVTPH2IUBSZ256rrk:
31823 case VCVTPH2IUBSZ256rrkz:
31824 case VCVTPH2IUBSZrm:
31825 case VCVTPH2IUBSZrmb:
31826 case VCVTPH2IUBSZrmbk:
31827 case VCVTPH2IUBSZrmbkz:
31828 case VCVTPH2IUBSZrmk:
31829 case VCVTPH2IUBSZrmkz:
31830 case VCVTPH2IUBSZrr:
31831 case VCVTPH2IUBSZrrb:
31832 case VCVTPH2IUBSZrrbk:
31833 case VCVTPH2IUBSZrrbkz:
31834 case VCVTPH2IUBSZrrk:
31835 case VCVTPH2IUBSZrrkz:
31836 return true;
31837 }
31838 return false;
31839}
31840
31841bool isVFPCLASSSH(unsigned Opcode) {
31842 switch (Opcode) {
31843 case VFPCLASSSHZmi:
31844 case VFPCLASSSHZmik:
31845 case VFPCLASSSHZri:
31846 case VFPCLASSSHZrik:
31847 return true;
31848 }
31849 return false;
31850}
31851
31852bool isVPSHLQ(unsigned Opcode) {
31853 switch (Opcode) {
31854 case VPSHLQmr:
31855 case VPSHLQrm:
31856 case VPSHLQrr:
31857 case VPSHLQrr_REV:
31858 return true;
31859 }
31860 return false;
31861}
31862
31863bool isVROUNDPS(unsigned Opcode) {
31864 switch (Opcode) {
31865 case VROUNDPSYmi:
31866 case VROUNDPSYri:
31867 case VROUNDPSmi:
31868 case VROUNDPSri:
31869 return true;
31870 }
31871 return false;
31872}
31873
31874bool isVSCATTERPF0QPS(unsigned Opcode) {
31875 return Opcode == VSCATTERPF0QPSm;
31876}
31877
31878bool isERETS(unsigned Opcode) {
31879 return Opcode == ERETS;
31880}
31881
31882bool isVPERMI2D(unsigned Opcode) {
31883 switch (Opcode) {
31884 case VPERMI2DZ128rm:
31885 case VPERMI2DZ128rmb:
31886 case VPERMI2DZ128rmbk:
31887 case VPERMI2DZ128rmbkz:
31888 case VPERMI2DZ128rmk:
31889 case VPERMI2DZ128rmkz:
31890 case VPERMI2DZ128rr:
31891 case VPERMI2DZ128rrk:
31892 case VPERMI2DZ128rrkz:
31893 case VPERMI2DZ256rm:
31894 case VPERMI2DZ256rmb:
31895 case VPERMI2DZ256rmbk:
31896 case VPERMI2DZ256rmbkz:
31897 case VPERMI2DZ256rmk:
31898 case VPERMI2DZ256rmkz:
31899 case VPERMI2DZ256rr:
31900 case VPERMI2DZ256rrk:
31901 case VPERMI2DZ256rrkz:
31902 case VPERMI2DZrm:
31903 case VPERMI2DZrmb:
31904 case VPERMI2DZrmbk:
31905 case VPERMI2DZrmbkz:
31906 case VPERMI2DZrmk:
31907 case VPERMI2DZrmkz:
31908 case VPERMI2DZrr:
31909 case VPERMI2DZrrk:
31910 case VPERMI2DZrrkz:
31911 return true;
31912 }
31913 return false;
31914}
31915
31916bool isFUCOMP(unsigned Opcode) {
31917 return Opcode == UCOM_FPr;
31918}
31919
31920bool isVCVTTPS2QQ(unsigned Opcode) {
31921 switch (Opcode) {
31922 case VCVTTPS2QQZ128rm:
31923 case VCVTTPS2QQZ128rmb:
31924 case VCVTTPS2QQZ128rmbk:
31925 case VCVTTPS2QQZ128rmbkz:
31926 case VCVTTPS2QQZ128rmk:
31927 case VCVTTPS2QQZ128rmkz:
31928 case VCVTTPS2QQZ128rr:
31929 case VCVTTPS2QQZ128rrk:
31930 case VCVTTPS2QQZ128rrkz:
31931 case VCVTTPS2QQZ256rm:
31932 case VCVTTPS2QQZ256rmb:
31933 case VCVTTPS2QQZ256rmbk:
31934 case VCVTTPS2QQZ256rmbkz:
31935 case VCVTTPS2QQZ256rmk:
31936 case VCVTTPS2QQZ256rmkz:
31937 case VCVTTPS2QQZ256rr:
31938 case VCVTTPS2QQZ256rrk:
31939 case VCVTTPS2QQZ256rrkz:
31940 case VCVTTPS2QQZrm:
31941 case VCVTTPS2QQZrmb:
31942 case VCVTTPS2QQZrmbk:
31943 case VCVTTPS2QQZrmbkz:
31944 case VCVTTPS2QQZrmk:
31945 case VCVTTPS2QQZrmkz:
31946 case VCVTTPS2QQZrr:
31947 case VCVTTPS2QQZrrb:
31948 case VCVTTPS2QQZrrbk:
31949 case VCVTTPS2QQZrrbkz:
31950 case VCVTTPS2QQZrrk:
31951 case VCVTTPS2QQZrrkz:
31952 return true;
31953 }
31954 return false;
31955}
31956
31957bool isPUSHFD(unsigned Opcode) {
31958 return Opcode == PUSHF32;
31959}
31960
31961bool isKORB(unsigned Opcode) {
31962 return Opcode == KORBkk;
31963}
31964
31965bool isVRCP28PD(unsigned Opcode) {
31966 switch (Opcode) {
31967 case VRCP28PDZm:
31968 case VRCP28PDZmb:
31969 case VRCP28PDZmbk:
31970 case VRCP28PDZmbkz:
31971 case VRCP28PDZmk:
31972 case VRCP28PDZmkz:
31973 case VRCP28PDZr:
31974 case VRCP28PDZrb:
31975 case VRCP28PDZrbk:
31976 case VRCP28PDZrbkz:
31977 case VRCP28PDZrk:
31978 case VRCP28PDZrkz:
31979 return true;
31980 }
31981 return false;
31982}
31983
31984bool isVPABSD(unsigned Opcode) {
31985 switch (Opcode) {
31986 case VPABSDYrm:
31987 case VPABSDYrr:
31988 case VPABSDZ128rm:
31989 case VPABSDZ128rmb:
31990 case VPABSDZ128rmbk:
31991 case VPABSDZ128rmbkz:
31992 case VPABSDZ128rmk:
31993 case VPABSDZ128rmkz:
31994 case VPABSDZ128rr:
31995 case VPABSDZ128rrk:
31996 case VPABSDZ128rrkz:
31997 case VPABSDZ256rm:
31998 case VPABSDZ256rmb:
31999 case VPABSDZ256rmbk:
32000 case VPABSDZ256rmbkz:
32001 case VPABSDZ256rmk:
32002 case VPABSDZ256rmkz:
32003 case VPABSDZ256rr:
32004 case VPABSDZ256rrk:
32005 case VPABSDZ256rrkz:
32006 case VPABSDZrm:
32007 case VPABSDZrmb:
32008 case VPABSDZrmbk:
32009 case VPABSDZrmbkz:
32010 case VPABSDZrmk:
32011 case VPABSDZrmkz:
32012 case VPABSDZrr:
32013 case VPABSDZrrk:
32014 case VPABSDZrrkz:
32015 case VPABSDrm:
32016 case VPABSDrr:
32017 return true;
32018 }
32019 return false;
32020}
32021
32022bool isVROUNDSS(unsigned Opcode) {
32023 switch (Opcode) {
32024 case VROUNDSSmi_Int:
32025 case VROUNDSSri_Int:
32026 return true;
32027 }
32028 return false;
32029}
32030
32031bool isVCVTSD2USI(unsigned Opcode) {
32032 switch (Opcode) {
32033 case VCVTSD2USI64Zrm_Int:
32034 case VCVTSD2USI64Zrr_Int:
32035 case VCVTSD2USI64Zrrb_Int:
32036 case VCVTSD2USIZrm_Int:
32037 case VCVTSD2USIZrr_Int:
32038 case VCVTSD2USIZrrb_Int:
32039 return true;
32040 }
32041 return false;
32042}
32043
32044bool isVPABSB(unsigned Opcode) {
32045 switch (Opcode) {
32046 case VPABSBYrm:
32047 case VPABSBYrr:
32048 case VPABSBZ128rm:
32049 case VPABSBZ128rmk:
32050 case VPABSBZ128rmkz:
32051 case VPABSBZ128rr:
32052 case VPABSBZ128rrk:
32053 case VPABSBZ128rrkz:
32054 case VPABSBZ256rm:
32055 case VPABSBZ256rmk:
32056 case VPABSBZ256rmkz:
32057 case VPABSBZ256rr:
32058 case VPABSBZ256rrk:
32059 case VPABSBZ256rrkz:
32060 case VPABSBZrm:
32061 case VPABSBZrmk:
32062 case VPABSBZrmkz:
32063 case VPABSBZrr:
32064 case VPABSBZrrk:
32065 case VPABSBZrrkz:
32066 case VPABSBrm:
32067 case VPABSBrr:
32068 return true;
32069 }
32070 return false;
32071}
32072
32073bool isPMAXUD(unsigned Opcode) {
32074 switch (Opcode) {
32075 case PMAXUDrm:
32076 case PMAXUDrr:
32077 return true;
32078 }
32079 return false;
32080}
32081
32082bool isVPMULHUW(unsigned Opcode) {
32083 switch (Opcode) {
32084 case VPMULHUWYrm:
32085 case VPMULHUWYrr:
32086 case VPMULHUWZ128rm:
32087 case VPMULHUWZ128rmk:
32088 case VPMULHUWZ128rmkz:
32089 case VPMULHUWZ128rr:
32090 case VPMULHUWZ128rrk:
32091 case VPMULHUWZ128rrkz:
32092 case VPMULHUWZ256rm:
32093 case VPMULHUWZ256rmk:
32094 case VPMULHUWZ256rmkz:
32095 case VPMULHUWZ256rr:
32096 case VPMULHUWZ256rrk:
32097 case VPMULHUWZ256rrkz:
32098 case VPMULHUWZrm:
32099 case VPMULHUWZrmk:
32100 case VPMULHUWZrmkz:
32101 case VPMULHUWZrr:
32102 case VPMULHUWZrrk:
32103 case VPMULHUWZrrkz:
32104 case VPMULHUWrm:
32105 case VPMULHUWrr:
32106 return true;
32107 }
32108 return false;
32109}
32110
32111bool isVPERMPD(unsigned Opcode) {
32112 switch (Opcode) {
32113 case VPERMPDYmi:
32114 case VPERMPDYri:
32115 case VPERMPDZ256mbi:
32116 case VPERMPDZ256mbik:
32117 case VPERMPDZ256mbikz:
32118 case VPERMPDZ256mi:
32119 case VPERMPDZ256mik:
32120 case VPERMPDZ256mikz:
32121 case VPERMPDZ256ri:
32122 case VPERMPDZ256rik:
32123 case VPERMPDZ256rikz:
32124 case VPERMPDZ256rm:
32125 case VPERMPDZ256rmb:
32126 case VPERMPDZ256rmbk:
32127 case VPERMPDZ256rmbkz:
32128 case VPERMPDZ256rmk:
32129 case VPERMPDZ256rmkz:
32130 case VPERMPDZ256rr:
32131 case VPERMPDZ256rrk:
32132 case VPERMPDZ256rrkz:
32133 case VPERMPDZmbi:
32134 case VPERMPDZmbik:
32135 case VPERMPDZmbikz:
32136 case VPERMPDZmi:
32137 case VPERMPDZmik:
32138 case VPERMPDZmikz:
32139 case VPERMPDZri:
32140 case VPERMPDZrik:
32141 case VPERMPDZrikz:
32142 case VPERMPDZrm:
32143 case VPERMPDZrmb:
32144 case VPERMPDZrmbk:
32145 case VPERMPDZrmbkz:
32146 case VPERMPDZrmk:
32147 case VPERMPDZrmkz:
32148 case VPERMPDZrr:
32149 case VPERMPDZrrk:
32150 case VPERMPDZrrkz:
32151 return true;
32152 }
32153 return false;
32154}
32155
32156bool isFCHS(unsigned Opcode) {
32157 return Opcode == CHS_F;
32158}
32159
32160bool isVPBLENDMB(unsigned Opcode) {
32161 switch (Opcode) {
32162 case VPBLENDMBZ128rm:
32163 case VPBLENDMBZ128rmk:
32164 case VPBLENDMBZ128rmkz:
32165 case VPBLENDMBZ128rr:
32166 case VPBLENDMBZ128rrk:
32167 case VPBLENDMBZ128rrkz:
32168 case VPBLENDMBZ256rm:
32169 case VPBLENDMBZ256rmk:
32170 case VPBLENDMBZ256rmkz:
32171 case VPBLENDMBZ256rr:
32172 case VPBLENDMBZ256rrk:
32173 case VPBLENDMBZ256rrkz:
32174 case VPBLENDMBZrm:
32175 case VPBLENDMBZrmk:
32176 case VPBLENDMBZrmkz:
32177 case VPBLENDMBZrr:
32178 case VPBLENDMBZrrk:
32179 case VPBLENDMBZrrkz:
32180 return true;
32181 }
32182 return false;
32183}
32184
32185bool isVGETMANTSS(unsigned Opcode) {
32186 switch (Opcode) {
32187 case VGETMANTSSZrmi:
32188 case VGETMANTSSZrmik:
32189 case VGETMANTSSZrmikz:
32190 case VGETMANTSSZrri:
32191 case VGETMANTSSZrrib:
32192 case VGETMANTSSZrribk:
32193 case VGETMANTSSZrribkz:
32194 case VGETMANTSSZrrik:
32195 case VGETMANTSSZrrikz:
32196 return true;
32197 }
32198 return false;
32199}
32200
32201bool isVPSLLW(unsigned Opcode) {
32202 switch (Opcode) {
32203 case VPSLLWYri:
32204 case VPSLLWYrm:
32205 case VPSLLWYrr:
32206 case VPSLLWZ128mi:
32207 case VPSLLWZ128mik:
32208 case VPSLLWZ128mikz:
32209 case VPSLLWZ128ri:
32210 case VPSLLWZ128rik:
32211 case VPSLLWZ128rikz:
32212 case VPSLLWZ128rm:
32213 case VPSLLWZ128rmk:
32214 case VPSLLWZ128rmkz:
32215 case VPSLLWZ128rr:
32216 case VPSLLWZ128rrk:
32217 case VPSLLWZ128rrkz:
32218 case VPSLLWZ256mi:
32219 case VPSLLWZ256mik:
32220 case VPSLLWZ256mikz:
32221 case VPSLLWZ256ri:
32222 case VPSLLWZ256rik:
32223 case VPSLLWZ256rikz:
32224 case VPSLLWZ256rm:
32225 case VPSLLWZ256rmk:
32226 case VPSLLWZ256rmkz:
32227 case VPSLLWZ256rr:
32228 case VPSLLWZ256rrk:
32229 case VPSLLWZ256rrkz:
32230 case VPSLLWZmi:
32231 case VPSLLWZmik:
32232 case VPSLLWZmikz:
32233 case VPSLLWZri:
32234 case VPSLLWZrik:
32235 case VPSLLWZrikz:
32236 case VPSLLWZrm:
32237 case VPSLLWZrmk:
32238 case VPSLLWZrmkz:
32239 case VPSLLWZrr:
32240 case VPSLLWZrrk:
32241 case VPSLLWZrrkz:
32242 case VPSLLWri:
32243 case VPSLLWrm:
32244 case VPSLLWrr:
32245 return true;
32246 }
32247 return false;
32248}
32249
32250bool isVDIVPD(unsigned Opcode) {
32251 switch (Opcode) {
32252 case VDIVPDYrm:
32253 case VDIVPDYrr:
32254 case VDIVPDZ128rm:
32255 case VDIVPDZ128rmb:
32256 case VDIVPDZ128rmbk:
32257 case VDIVPDZ128rmbkz:
32258 case VDIVPDZ128rmk:
32259 case VDIVPDZ128rmkz:
32260 case VDIVPDZ128rr:
32261 case VDIVPDZ128rrk:
32262 case VDIVPDZ128rrkz:
32263 case VDIVPDZ256rm:
32264 case VDIVPDZ256rmb:
32265 case VDIVPDZ256rmbk:
32266 case VDIVPDZ256rmbkz:
32267 case VDIVPDZ256rmk:
32268 case VDIVPDZ256rmkz:
32269 case VDIVPDZ256rr:
32270 case VDIVPDZ256rrk:
32271 case VDIVPDZ256rrkz:
32272 case VDIVPDZrm:
32273 case VDIVPDZrmb:
32274 case VDIVPDZrmbk:
32275 case VDIVPDZrmbkz:
32276 case VDIVPDZrmk:
32277 case VDIVPDZrmkz:
32278 case VDIVPDZrr:
32279 case VDIVPDZrrb:
32280 case VDIVPDZrrbk:
32281 case VDIVPDZrrbkz:
32282 case VDIVPDZrrk:
32283 case VDIVPDZrrkz:
32284 case VDIVPDrm:
32285 case VDIVPDrr:
32286 return true;
32287 }
32288 return false;
32289}
32290
32291bool isBLCMSK(unsigned Opcode) {
32292 switch (Opcode) {
32293 case BLCMSK32rm:
32294 case BLCMSK32rr:
32295 case BLCMSK64rm:
32296 case BLCMSK64rr:
32297 return true;
32298 }
32299 return false;
32300}
32301
32302bool isFDIV(unsigned Opcode) {
32303 switch (Opcode) {
32304 case DIV_F32m:
32305 case DIV_F64m:
32306 case DIV_FST0r:
32307 case DIV_FrST0:
32308 return true;
32309 }
32310 return false;
32311}
32312
32313bool isRSQRTSS(unsigned Opcode) {
32314 switch (Opcode) {
32315 case RSQRTSSm_Int:
32316 case RSQRTSSr_Int:
32317 return true;
32318 }
32319 return false;
32320}
32321
32322bool isPOR(unsigned Opcode) {
32323 switch (Opcode) {
32324 case MMX_PORrm:
32325 case MMX_PORrr:
32326 case PORrm:
32327 case PORrr:
32328 return true;
32329 }
32330 return false;
32331}
32332
32333bool isVMOVDQA32(unsigned Opcode) {
32334 switch (Opcode) {
32335 case VMOVDQA32Z128mr:
32336 case VMOVDQA32Z128mrk:
32337 case VMOVDQA32Z128rm:
32338 case VMOVDQA32Z128rmk:
32339 case VMOVDQA32Z128rmkz:
32340 case VMOVDQA32Z128rr:
32341 case VMOVDQA32Z128rr_REV:
32342 case VMOVDQA32Z128rrk:
32343 case VMOVDQA32Z128rrk_REV:
32344 case VMOVDQA32Z128rrkz:
32345 case VMOVDQA32Z128rrkz_REV:
32346 case VMOVDQA32Z256mr:
32347 case VMOVDQA32Z256mrk:
32348 case VMOVDQA32Z256rm:
32349 case VMOVDQA32Z256rmk:
32350 case VMOVDQA32Z256rmkz:
32351 case VMOVDQA32Z256rr:
32352 case VMOVDQA32Z256rr_REV:
32353 case VMOVDQA32Z256rrk:
32354 case VMOVDQA32Z256rrk_REV:
32355 case VMOVDQA32Z256rrkz:
32356 case VMOVDQA32Z256rrkz_REV:
32357 case VMOVDQA32Zmr:
32358 case VMOVDQA32Zmrk:
32359 case VMOVDQA32Zrm:
32360 case VMOVDQA32Zrmk:
32361 case VMOVDQA32Zrmkz:
32362 case VMOVDQA32Zrr:
32363 case VMOVDQA32Zrr_REV:
32364 case VMOVDQA32Zrrk:
32365 case VMOVDQA32Zrrk_REV:
32366 case VMOVDQA32Zrrkz:
32367 case VMOVDQA32Zrrkz_REV:
32368 return true;
32369 }
32370 return false;
32371}
32372
32373bool isVPHADDUWQ(unsigned Opcode) {
32374 switch (Opcode) {
32375 case VPHADDUWQrm:
32376 case VPHADDUWQrr:
32377 return true;
32378 }
32379 return false;
32380}
32381
32382bool isPSRAD(unsigned Opcode) {
32383 switch (Opcode) {
32384 case MMX_PSRADri:
32385 case MMX_PSRADrm:
32386 case MMX_PSRADrr:
32387 case PSRADri:
32388 case PSRADrm:
32389 case PSRADrr:
32390 return true;
32391 }
32392 return false;
32393}
32394
32395bool isPREFETCHW(unsigned Opcode) {
32396 return Opcode == PREFETCHW;
32397}
32398
32399bool isFIDIVR(unsigned Opcode) {
32400 switch (Opcode) {
32401 case DIVR_FI16m:
32402 case DIVR_FI32m:
32403 return true;
32404 }
32405 return false;
32406}
32407
32408bool isMOVHPS(unsigned Opcode) {
32409 switch (Opcode) {
32410 case MOVHPSmr:
32411 case MOVHPSrm:
32412 return true;
32413 }
32414 return false;
32415}
32416
32417bool isVFNMSUB231PH(unsigned Opcode) {
32418 switch (Opcode) {
32419 case VFNMSUB231PHZ128m:
32420 case VFNMSUB231PHZ128mb:
32421 case VFNMSUB231PHZ128mbk:
32422 case VFNMSUB231PHZ128mbkz:
32423 case VFNMSUB231PHZ128mk:
32424 case VFNMSUB231PHZ128mkz:
32425 case VFNMSUB231PHZ128r:
32426 case VFNMSUB231PHZ128rk:
32427 case VFNMSUB231PHZ128rkz:
32428 case VFNMSUB231PHZ256m:
32429 case VFNMSUB231PHZ256mb:
32430 case VFNMSUB231PHZ256mbk:
32431 case VFNMSUB231PHZ256mbkz:
32432 case VFNMSUB231PHZ256mk:
32433 case VFNMSUB231PHZ256mkz:
32434 case VFNMSUB231PHZ256r:
32435 case VFNMSUB231PHZ256rk:
32436 case VFNMSUB231PHZ256rkz:
32437 case VFNMSUB231PHZm:
32438 case VFNMSUB231PHZmb:
32439 case VFNMSUB231PHZmbk:
32440 case VFNMSUB231PHZmbkz:
32441 case VFNMSUB231PHZmk:
32442 case VFNMSUB231PHZmkz:
32443 case VFNMSUB231PHZr:
32444 case VFNMSUB231PHZrb:
32445 case VFNMSUB231PHZrbk:
32446 case VFNMSUB231PHZrbkz:
32447 case VFNMSUB231PHZrk:
32448 case VFNMSUB231PHZrkz:
32449 return true;
32450 }
32451 return false;
32452}
32453
32454bool isUNPCKLPS(unsigned Opcode) {
32455 switch (Opcode) {
32456 case UNPCKLPSrm:
32457 case UNPCKLPSrr:
32458 return true;
32459 }
32460 return false;
32461}
32462
32463bool isVPSIGNB(unsigned Opcode) {
32464 switch (Opcode) {
32465 case VPSIGNBYrm:
32466 case VPSIGNBYrr:
32467 case VPSIGNBrm:
32468 case VPSIGNBrr:
32469 return true;
32470 }
32471 return false;
32472}
32473
32474bool isSAVEPREVSSP(unsigned Opcode) {
32475 return Opcode == SAVEPREVSSP;
32476}
32477
32478bool isVSCALEFSD(unsigned Opcode) {
32479 switch (Opcode) {
32480 case VSCALEFSDZrm:
32481 case VSCALEFSDZrmk:
32482 case VSCALEFSDZrmkz:
32483 case VSCALEFSDZrr:
32484 case VSCALEFSDZrrb_Int:
32485 case VSCALEFSDZrrbk_Int:
32486 case VSCALEFSDZrrbkz_Int:
32487 case VSCALEFSDZrrk:
32488 case VSCALEFSDZrrkz:
32489 return true;
32490 }
32491 return false;
32492}
32493
32494bool isFSIN(unsigned Opcode) {
32495 return Opcode == FSIN;
32496}
32497
32498bool isSCASQ(unsigned Opcode) {
32499 return Opcode == SCASQ;
32500}
32501
32502bool isVCVTTPD2QQS(unsigned Opcode) {
32503 switch (Opcode) {
32504 case VCVTTPD2QQSZ128rm:
32505 case VCVTTPD2QQSZ128rmb:
32506 case VCVTTPD2QQSZ128rmbk:
32507 case VCVTTPD2QQSZ128rmbkz:
32508 case VCVTTPD2QQSZ128rmk:
32509 case VCVTTPD2QQSZ128rmkz:
32510 case VCVTTPD2QQSZ128rr:
32511 case VCVTTPD2QQSZ128rrk:
32512 case VCVTTPD2QQSZ128rrkz:
32513 case VCVTTPD2QQSZ256rm:
32514 case VCVTTPD2QQSZ256rmb:
32515 case VCVTTPD2QQSZ256rmbk:
32516 case VCVTTPD2QQSZ256rmbkz:
32517 case VCVTTPD2QQSZ256rmk:
32518 case VCVTTPD2QQSZ256rmkz:
32519 case VCVTTPD2QQSZ256rr:
32520 case VCVTTPD2QQSZ256rrb:
32521 case VCVTTPD2QQSZ256rrbk:
32522 case VCVTTPD2QQSZ256rrbkz:
32523 case VCVTTPD2QQSZ256rrk:
32524 case VCVTTPD2QQSZ256rrkz:
32525 case VCVTTPD2QQSZrm:
32526 case VCVTTPD2QQSZrmb:
32527 case VCVTTPD2QQSZrmbk:
32528 case VCVTTPD2QQSZrmbkz:
32529 case VCVTTPD2QQSZrmk:
32530 case VCVTTPD2QQSZrmkz:
32531 case VCVTTPD2QQSZrr:
32532 case VCVTTPD2QQSZrrb:
32533 case VCVTTPD2QQSZrrbk:
32534 case VCVTTPD2QQSZrrbkz:
32535 case VCVTTPD2QQSZrrk:
32536 case VCVTTPD2QQSZrrkz:
32537 return true;
32538 }
32539 return false;
32540}
32541
32542bool isPCMPGTW(unsigned Opcode) {
32543 switch (Opcode) {
32544 case MMX_PCMPGTWrm:
32545 case MMX_PCMPGTWrr:
32546 case PCMPGTWrm:
32547 case PCMPGTWrr:
32548 return true;
32549 }
32550 return false;
32551}
32552
32553bool isMULX(unsigned Opcode) {
32554 switch (Opcode) {
32555 case MULX32rm:
32556 case MULX32rm_EVEX:
32557 case MULX32rr:
32558 case MULX32rr_EVEX:
32559 case MULX64rm:
32560 case MULX64rm_EVEX:
32561 case MULX64rr:
32562 case MULX64rr_EVEX:
32563 return true;
32564 }
32565 return false;
32566}
32567
32568bool isVPMAXUW(unsigned Opcode) {
32569 switch (Opcode) {
32570 case VPMAXUWYrm:
32571 case VPMAXUWYrr:
32572 case VPMAXUWZ128rm:
32573 case VPMAXUWZ128rmk:
32574 case VPMAXUWZ128rmkz:
32575 case VPMAXUWZ128rr:
32576 case VPMAXUWZ128rrk:
32577 case VPMAXUWZ128rrkz:
32578 case VPMAXUWZ256rm:
32579 case VPMAXUWZ256rmk:
32580 case VPMAXUWZ256rmkz:
32581 case VPMAXUWZ256rr:
32582 case VPMAXUWZ256rrk:
32583 case VPMAXUWZ256rrkz:
32584 case VPMAXUWZrm:
32585 case VPMAXUWZrmk:
32586 case VPMAXUWZrmkz:
32587 case VPMAXUWZrr:
32588 case VPMAXUWZrrk:
32589 case VPMAXUWZrrkz:
32590 case VPMAXUWrm:
32591 case VPMAXUWrr:
32592 return true;
32593 }
32594 return false;
32595}
32596
32597bool isPAUSE(unsigned Opcode) {
32598 return Opcode == PAUSE;
32599}
32600
32601bool isMOVQ2DQ(unsigned Opcode) {
32602 return Opcode == MMX_MOVQ2DQrr;
32603}
32604
32605bool isVPSUBQ(unsigned Opcode) {
32606 switch (Opcode) {
32607 case VPSUBQYrm:
32608 case VPSUBQYrr:
32609 case VPSUBQZ128rm:
32610 case VPSUBQZ128rmb:
32611 case VPSUBQZ128rmbk:
32612 case VPSUBQZ128rmbkz:
32613 case VPSUBQZ128rmk:
32614 case VPSUBQZ128rmkz:
32615 case VPSUBQZ128rr:
32616 case VPSUBQZ128rrk:
32617 case VPSUBQZ128rrkz:
32618 case VPSUBQZ256rm:
32619 case VPSUBQZ256rmb:
32620 case VPSUBQZ256rmbk:
32621 case VPSUBQZ256rmbkz:
32622 case VPSUBQZ256rmk:
32623 case VPSUBQZ256rmkz:
32624 case VPSUBQZ256rr:
32625 case VPSUBQZ256rrk:
32626 case VPSUBQZ256rrkz:
32627 case VPSUBQZrm:
32628 case VPSUBQZrmb:
32629 case VPSUBQZrmbk:
32630 case VPSUBQZrmbkz:
32631 case VPSUBQZrmk:
32632 case VPSUBQZrmkz:
32633 case VPSUBQZrr:
32634 case VPSUBQZrrk:
32635 case VPSUBQZrrkz:
32636 case VPSUBQrm:
32637 case VPSUBQrr:
32638 return true;
32639 }
32640 return false;
32641}
32642
32643bool isVPABSW(unsigned Opcode) {
32644 switch (Opcode) {
32645 case VPABSWYrm:
32646 case VPABSWYrr:
32647 case VPABSWZ128rm:
32648 case VPABSWZ128rmk:
32649 case VPABSWZ128rmkz:
32650 case VPABSWZ128rr:
32651 case VPABSWZ128rrk:
32652 case VPABSWZ128rrkz:
32653 case VPABSWZ256rm:
32654 case VPABSWZ256rmk:
32655 case VPABSWZ256rmkz:
32656 case VPABSWZ256rr:
32657 case VPABSWZ256rrk:
32658 case VPABSWZ256rrkz:
32659 case VPABSWZrm:
32660 case VPABSWZrmk:
32661 case VPABSWZrmkz:
32662 case VPABSWZrr:
32663 case VPABSWZrrk:
32664 case VPABSWZrrkz:
32665 case VPABSWrm:
32666 case VPABSWrr:
32667 return true;
32668 }
32669 return false;
32670}
32671
32672bool isVPCOMPRESSD(unsigned Opcode) {
32673 switch (Opcode) {
32674 case VPCOMPRESSDZ128mr:
32675 case VPCOMPRESSDZ128mrk:
32676 case VPCOMPRESSDZ128rr:
32677 case VPCOMPRESSDZ128rrk:
32678 case VPCOMPRESSDZ128rrkz:
32679 case VPCOMPRESSDZ256mr:
32680 case VPCOMPRESSDZ256mrk:
32681 case VPCOMPRESSDZ256rr:
32682 case VPCOMPRESSDZ256rrk:
32683 case VPCOMPRESSDZ256rrkz:
32684 case VPCOMPRESSDZmr:
32685 case VPCOMPRESSDZmrk:
32686 case VPCOMPRESSDZrr:
32687 case VPCOMPRESSDZrrk:
32688 case VPCOMPRESSDZrrkz:
32689 return true;
32690 }
32691 return false;
32692}
32693
32694bool isVPMOVUSQW(unsigned Opcode) {
32695 switch (Opcode) {
32696 case VPMOVUSQWZ128mr:
32697 case VPMOVUSQWZ128mrk:
32698 case VPMOVUSQWZ128rr:
32699 case VPMOVUSQWZ128rrk:
32700 case VPMOVUSQWZ128rrkz:
32701 case VPMOVUSQWZ256mr:
32702 case VPMOVUSQWZ256mrk:
32703 case VPMOVUSQWZ256rr:
32704 case VPMOVUSQWZ256rrk:
32705 case VPMOVUSQWZ256rrkz:
32706 case VPMOVUSQWZmr:
32707 case VPMOVUSQWZmrk:
32708 case VPMOVUSQWZrr:
32709 case VPMOVUSQWZrrk:
32710 case VPMOVUSQWZrrkz:
32711 return true;
32712 }
32713 return false;
32714}
32715
32716bool isBLENDVPD(unsigned Opcode) {
32717 switch (Opcode) {
32718 case BLENDVPDrm0:
32719 case BLENDVPDrr0:
32720 return true;
32721 }
32722 return false;
32723}
32724
32725bool isVFNMADD132BF16(unsigned Opcode) {
32726 switch (Opcode) {
32727 case VFNMADD132BF16Z128m:
32728 case VFNMADD132BF16Z128mb:
32729 case VFNMADD132BF16Z128mbk:
32730 case VFNMADD132BF16Z128mbkz:
32731 case VFNMADD132BF16Z128mk:
32732 case VFNMADD132BF16Z128mkz:
32733 case VFNMADD132BF16Z128r:
32734 case VFNMADD132BF16Z128rk:
32735 case VFNMADD132BF16Z128rkz:
32736 case VFNMADD132BF16Z256m:
32737 case VFNMADD132BF16Z256mb:
32738 case VFNMADD132BF16Z256mbk:
32739 case VFNMADD132BF16Z256mbkz:
32740 case VFNMADD132BF16Z256mk:
32741 case VFNMADD132BF16Z256mkz:
32742 case VFNMADD132BF16Z256r:
32743 case VFNMADD132BF16Z256rk:
32744 case VFNMADD132BF16Z256rkz:
32745 case VFNMADD132BF16Zm:
32746 case VFNMADD132BF16Zmb:
32747 case VFNMADD132BF16Zmbk:
32748 case VFNMADD132BF16Zmbkz:
32749 case VFNMADD132BF16Zmk:
32750 case VFNMADD132BF16Zmkz:
32751 case VFNMADD132BF16Zr:
32752 case VFNMADD132BF16Zrk:
32753 case VFNMADD132BF16Zrkz:
32754 return true;
32755 }
32756 return false;
32757}
32758
32759bool isVPMOVQB(unsigned Opcode) {
32760 switch (Opcode) {
32761 case VPMOVQBZ128mr:
32762 case VPMOVQBZ128mrk:
32763 case VPMOVQBZ128rr:
32764 case VPMOVQBZ128rrk:
32765 case VPMOVQBZ128rrkz:
32766 case VPMOVQBZ256mr:
32767 case VPMOVQBZ256mrk:
32768 case VPMOVQBZ256rr:
32769 case VPMOVQBZ256rrk:
32770 case VPMOVQBZ256rrkz:
32771 case VPMOVQBZmr:
32772 case VPMOVQBZmrk:
32773 case VPMOVQBZrr:
32774 case VPMOVQBZrrk:
32775 case VPMOVQBZrrkz:
32776 return true;
32777 }
32778 return false;
32779}
32780
32781bool isVBLENDVPS(unsigned Opcode) {
32782 switch (Opcode) {
32783 case VBLENDVPSYrmr:
32784 case VBLENDVPSYrrr:
32785 case VBLENDVPSrmr:
32786 case VBLENDVPSrrr:
32787 return true;
32788 }
32789 return false;
32790}
32791
32792bool isKSHIFTLQ(unsigned Opcode) {
32793 return Opcode == KSHIFTLQki;
32794}
32795
32796bool isPMOVSXWD(unsigned Opcode) {
32797 switch (Opcode) {
32798 case PMOVSXWDrm:
32799 case PMOVSXWDrr:
32800 return true;
32801 }
32802 return false;
32803}
32804
32805bool isPHSUBSW(unsigned Opcode) {
32806 switch (Opcode) {
32807 case MMX_PHSUBSWrm:
32808 case MMX_PHSUBSWrr:
32809 case PHSUBSWrm:
32810 case PHSUBSWrr:
32811 return true;
32812 }
32813 return false;
32814}
32815
32816bool isPSRLQ(unsigned Opcode) {
32817 switch (Opcode) {
32818 case MMX_PSRLQri:
32819 case MMX_PSRLQrm:
32820 case MMX_PSRLQrr:
32821 case PSRLQri:
32822 case PSRLQrm:
32823 case PSRLQrr:
32824 return true;
32825 }
32826 return false;
32827}
32828
32829bool isVCVTPH2DQ(unsigned Opcode) {
32830 switch (Opcode) {
32831 case VCVTPH2DQZ128rm:
32832 case VCVTPH2DQZ128rmb:
32833 case VCVTPH2DQZ128rmbk:
32834 case VCVTPH2DQZ128rmbkz:
32835 case VCVTPH2DQZ128rmk:
32836 case VCVTPH2DQZ128rmkz:
32837 case VCVTPH2DQZ128rr:
32838 case VCVTPH2DQZ128rrk:
32839 case VCVTPH2DQZ128rrkz:
32840 case VCVTPH2DQZ256rm:
32841 case VCVTPH2DQZ256rmb:
32842 case VCVTPH2DQZ256rmbk:
32843 case VCVTPH2DQZ256rmbkz:
32844 case VCVTPH2DQZ256rmk:
32845 case VCVTPH2DQZ256rmkz:
32846 case VCVTPH2DQZ256rr:
32847 case VCVTPH2DQZ256rrk:
32848 case VCVTPH2DQZ256rrkz:
32849 case VCVTPH2DQZrm:
32850 case VCVTPH2DQZrmb:
32851 case VCVTPH2DQZrmbk:
32852 case VCVTPH2DQZrmbkz:
32853 case VCVTPH2DQZrmk:
32854 case VCVTPH2DQZrmkz:
32855 case VCVTPH2DQZrr:
32856 case VCVTPH2DQZrrb:
32857 case VCVTPH2DQZrrbk:
32858 case VCVTPH2DQZrrbkz:
32859 case VCVTPH2DQZrrk:
32860 case VCVTPH2DQZrrkz:
32861 return true;
32862 }
32863 return false;
32864}
32865
32866bool isFISUB(unsigned Opcode) {
32867 switch (Opcode) {
32868 case SUB_FI16m:
32869 case SUB_FI32m:
32870 return true;
32871 }
32872 return false;
32873}
32874
32875bool isVCVTPS2UDQ(unsigned Opcode) {
32876 switch (Opcode) {
32877 case VCVTPS2UDQZ128rm:
32878 case VCVTPS2UDQZ128rmb:
32879 case VCVTPS2UDQZ128rmbk:
32880 case VCVTPS2UDQZ128rmbkz:
32881 case VCVTPS2UDQZ128rmk:
32882 case VCVTPS2UDQZ128rmkz:
32883 case VCVTPS2UDQZ128rr:
32884 case VCVTPS2UDQZ128rrk:
32885 case VCVTPS2UDQZ128rrkz:
32886 case VCVTPS2UDQZ256rm:
32887 case VCVTPS2UDQZ256rmb:
32888 case VCVTPS2UDQZ256rmbk:
32889 case VCVTPS2UDQZ256rmbkz:
32890 case VCVTPS2UDQZ256rmk:
32891 case VCVTPS2UDQZ256rmkz:
32892 case VCVTPS2UDQZ256rr:
32893 case VCVTPS2UDQZ256rrk:
32894 case VCVTPS2UDQZ256rrkz:
32895 case VCVTPS2UDQZrm:
32896 case VCVTPS2UDQZrmb:
32897 case VCVTPS2UDQZrmbk:
32898 case VCVTPS2UDQZrmbkz:
32899 case VCVTPS2UDQZrmk:
32900 case VCVTPS2UDQZrmkz:
32901 case VCVTPS2UDQZrr:
32902 case VCVTPS2UDQZrrb:
32903 case VCVTPS2UDQZrrbk:
32904 case VCVTPS2UDQZrrbkz:
32905 case VCVTPS2UDQZrrk:
32906 case VCVTPS2UDQZrrkz:
32907 return true;
32908 }
32909 return false;
32910}
32911
32912bool isVMOVDDUP(unsigned Opcode) {
32913 switch (Opcode) {
32914 case VMOVDDUPYrm:
32915 case VMOVDDUPYrr:
32916 case VMOVDDUPZ128rm:
32917 case VMOVDDUPZ128rmk:
32918 case VMOVDDUPZ128rmkz:
32919 case VMOVDDUPZ128rr:
32920 case VMOVDDUPZ128rrk:
32921 case VMOVDDUPZ128rrkz:
32922 case VMOVDDUPZ256rm:
32923 case VMOVDDUPZ256rmk:
32924 case VMOVDDUPZ256rmkz:
32925 case VMOVDDUPZ256rr:
32926 case VMOVDDUPZ256rrk:
32927 case VMOVDDUPZ256rrkz:
32928 case VMOVDDUPZrm:
32929 case VMOVDDUPZrmk:
32930 case VMOVDDUPZrmkz:
32931 case VMOVDDUPZrr:
32932 case VMOVDDUPZrrk:
32933 case VMOVDDUPZrrkz:
32934 case VMOVDDUPrm:
32935 case VMOVDDUPrr:
32936 return true;
32937 }
32938 return false;
32939}
32940
32941bool isPCMPEQD(unsigned Opcode) {
32942 switch (Opcode) {
32943 case MMX_PCMPEQDrm:
32944 case MMX_PCMPEQDrr:
32945 case PCMPEQDrm:
32946 case PCMPEQDrr:
32947 return true;
32948 }
32949 return false;
32950}
32951
32952bool isVRSQRT28SD(unsigned Opcode) {
32953 switch (Opcode) {
32954 case VRSQRT28SDZm:
32955 case VRSQRT28SDZmk:
32956 case VRSQRT28SDZmkz:
32957 case VRSQRT28SDZr:
32958 case VRSQRT28SDZrb:
32959 case VRSQRT28SDZrbk:
32960 case VRSQRT28SDZrbkz:
32961 case VRSQRT28SDZrk:
32962 case VRSQRT28SDZrkz:
32963 return true;
32964 }
32965 return false;
32966}
32967
32968bool isTDPHBF8PS(unsigned Opcode) {
32969 return Opcode == TDPHBF8PS;
32970}
32971
32972bool isLODSW(unsigned Opcode) {
32973 return Opcode == LODSW;
32974}
32975
32976bool isVPOPCNTQ(unsigned Opcode) {
32977 switch (Opcode) {
32978 case VPOPCNTQZ128rm:
32979 case VPOPCNTQZ128rmb:
32980 case VPOPCNTQZ128rmbk:
32981 case VPOPCNTQZ128rmbkz:
32982 case VPOPCNTQZ128rmk:
32983 case VPOPCNTQZ128rmkz:
32984 case VPOPCNTQZ128rr:
32985 case VPOPCNTQZ128rrk:
32986 case VPOPCNTQZ128rrkz:
32987 case VPOPCNTQZ256rm:
32988 case VPOPCNTQZ256rmb:
32989 case VPOPCNTQZ256rmbk:
32990 case VPOPCNTQZ256rmbkz:
32991 case VPOPCNTQZ256rmk:
32992 case VPOPCNTQZ256rmkz:
32993 case VPOPCNTQZ256rr:
32994 case VPOPCNTQZ256rrk:
32995 case VPOPCNTQZ256rrkz:
32996 case VPOPCNTQZrm:
32997 case VPOPCNTQZrmb:
32998 case VPOPCNTQZrmbk:
32999 case VPOPCNTQZrmbkz:
33000 case VPOPCNTQZrmk:
33001 case VPOPCNTQZrmkz:
33002 case VPOPCNTQZrr:
33003 case VPOPCNTQZrrk:
33004 case VPOPCNTQZrrkz:
33005 return true;
33006 }
33007 return false;
33008}
33009
33010bool isKSHIFTRB(unsigned Opcode) {
33011 return Opcode == KSHIFTRBki;
33012}
33013
33014bool isVFNMADDPS(unsigned Opcode) {
33015 switch (Opcode) {
33016 case VFNMADDPS4Ymr:
33017 case VFNMADDPS4Yrm:
33018 case VFNMADDPS4Yrr:
33019 case VFNMADDPS4Yrr_REV:
33020 case VFNMADDPS4mr:
33021 case VFNMADDPS4rm:
33022 case VFNMADDPS4rr:
33023 case VFNMADDPS4rr_REV:
33024 return true;
33025 }
33026 return false;
33027}
33028
33029bool isCCMPCC(unsigned Opcode) {
33030 switch (Opcode) {
33031 case CCMP16mi:
33032 case CCMP16mi8:
33033 case CCMP16mr:
33034 case CCMP16ri:
33035 case CCMP16ri8:
33036 case CCMP16rm:
33037 case CCMP16rr:
33038 case CCMP16rr_REV:
33039 case CCMP32mi:
33040 case CCMP32mi8:
33041 case CCMP32mr:
33042 case CCMP32ri:
33043 case CCMP32ri8:
33044 case CCMP32rm:
33045 case CCMP32rr:
33046 case CCMP32rr_REV:
33047 case CCMP64mi32:
33048 case CCMP64mi8:
33049 case CCMP64mr:
33050 case CCMP64ri32:
33051 case CCMP64ri8:
33052 case CCMP64rm:
33053 case CCMP64rr:
33054 case CCMP64rr_REV:
33055 case CCMP8mi:
33056 case CCMP8mr:
33057 case CCMP8ri:
33058 case CCMP8rm:
33059 case CCMP8rr:
33060 case CCMP8rr_REV:
33061 return true;
33062 }
33063 return false;
33064}
33065
33066bool isFXRSTOR64(unsigned Opcode) {
33067 return Opcode == FXRSTOR64;
33068}
33069
33070bool isVFMSUBADD213PD(unsigned Opcode) {
33071 switch (Opcode) {
33072 case VFMSUBADD213PDYm:
33073 case VFMSUBADD213PDYr:
33074 case VFMSUBADD213PDZ128m:
33075 case VFMSUBADD213PDZ128mb:
33076 case VFMSUBADD213PDZ128mbk:
33077 case VFMSUBADD213PDZ128mbkz:
33078 case VFMSUBADD213PDZ128mk:
33079 case VFMSUBADD213PDZ128mkz:
33080 case VFMSUBADD213PDZ128r:
33081 case VFMSUBADD213PDZ128rk:
33082 case VFMSUBADD213PDZ128rkz:
33083 case VFMSUBADD213PDZ256m:
33084 case VFMSUBADD213PDZ256mb:
33085 case VFMSUBADD213PDZ256mbk:
33086 case VFMSUBADD213PDZ256mbkz:
33087 case VFMSUBADD213PDZ256mk:
33088 case VFMSUBADD213PDZ256mkz:
33089 case VFMSUBADD213PDZ256r:
33090 case VFMSUBADD213PDZ256rk:
33091 case VFMSUBADD213PDZ256rkz:
33092 case VFMSUBADD213PDZm:
33093 case VFMSUBADD213PDZmb:
33094 case VFMSUBADD213PDZmbk:
33095 case VFMSUBADD213PDZmbkz:
33096 case VFMSUBADD213PDZmk:
33097 case VFMSUBADD213PDZmkz:
33098 case VFMSUBADD213PDZr:
33099 case VFMSUBADD213PDZrb:
33100 case VFMSUBADD213PDZrbk:
33101 case VFMSUBADD213PDZrbkz:
33102 case VFMSUBADD213PDZrk:
33103 case VFMSUBADD213PDZrkz:
33104 case VFMSUBADD213PDm:
33105 case VFMSUBADD213PDr:
33106 return true;
33107 }
33108 return false;
33109}
33110
33111bool isVSQRTPH(unsigned Opcode) {
33112 switch (Opcode) {
33113 case VSQRTPHZ128m:
33114 case VSQRTPHZ128mb:
33115 case VSQRTPHZ128mbk:
33116 case VSQRTPHZ128mbkz:
33117 case VSQRTPHZ128mk:
33118 case VSQRTPHZ128mkz:
33119 case VSQRTPHZ128r:
33120 case VSQRTPHZ128rk:
33121 case VSQRTPHZ128rkz:
33122 case VSQRTPHZ256m:
33123 case VSQRTPHZ256mb:
33124 case VSQRTPHZ256mbk:
33125 case VSQRTPHZ256mbkz:
33126 case VSQRTPHZ256mk:
33127 case VSQRTPHZ256mkz:
33128 case VSQRTPHZ256r:
33129 case VSQRTPHZ256rk:
33130 case VSQRTPHZ256rkz:
33131 case VSQRTPHZm:
33132 case VSQRTPHZmb:
33133 case VSQRTPHZmbk:
33134 case VSQRTPHZmbkz:
33135 case VSQRTPHZmk:
33136 case VSQRTPHZmkz:
33137 case VSQRTPHZr:
33138 case VSQRTPHZrb:
33139 case VSQRTPHZrbk:
33140 case VSQRTPHZrbkz:
33141 case VSQRTPHZrk:
33142 case VSQRTPHZrkz:
33143 return true;
33144 }
33145 return false;
33146}
33147
33148bool isPOPF(unsigned Opcode) {
33149 return Opcode == POPF16;
33150}
33151
33152bool isVPSUBUSB(unsigned Opcode) {
33153 switch (Opcode) {
33154 case VPSUBUSBYrm:
33155 case VPSUBUSBYrr:
33156 case VPSUBUSBZ128rm:
33157 case VPSUBUSBZ128rmk:
33158 case VPSUBUSBZ128rmkz:
33159 case VPSUBUSBZ128rr:
33160 case VPSUBUSBZ128rrk:
33161 case VPSUBUSBZ128rrkz:
33162 case VPSUBUSBZ256rm:
33163 case VPSUBUSBZ256rmk:
33164 case VPSUBUSBZ256rmkz:
33165 case VPSUBUSBZ256rr:
33166 case VPSUBUSBZ256rrk:
33167 case VPSUBUSBZ256rrkz:
33168 case VPSUBUSBZrm:
33169 case VPSUBUSBZrmk:
33170 case VPSUBUSBZrmkz:
33171 case VPSUBUSBZrr:
33172 case VPSUBUSBZrrk:
33173 case VPSUBUSBZrrkz:
33174 case VPSUBUSBrm:
33175 case VPSUBUSBrr:
33176 return true;
33177 }
33178 return false;
33179}
33180
33181bool isTCVTROWPS2BF16L(unsigned Opcode) {
33182 switch (Opcode) {
33183 case TCVTROWPS2BF16Lrte:
33184 case TCVTROWPS2BF16Lrti:
33185 return true;
33186 }
33187 return false;
33188}
33189
33190bool isPREFETCHIT1(unsigned Opcode) {
33191 return Opcode == PREFETCHIT1;
33192}
33193
33194bool isVPADDSW(unsigned Opcode) {
33195 switch (Opcode) {
33196 case VPADDSWYrm:
33197 case VPADDSWYrr:
33198 case VPADDSWZ128rm:
33199 case VPADDSWZ128rmk:
33200 case VPADDSWZ128rmkz:
33201 case VPADDSWZ128rr:
33202 case VPADDSWZ128rrk:
33203 case VPADDSWZ128rrkz:
33204 case VPADDSWZ256rm:
33205 case VPADDSWZ256rmk:
33206 case VPADDSWZ256rmkz:
33207 case VPADDSWZ256rr:
33208 case VPADDSWZ256rrk:
33209 case VPADDSWZ256rrkz:
33210 case VPADDSWZrm:
33211 case VPADDSWZrmk:
33212 case VPADDSWZrmkz:
33213 case VPADDSWZrr:
33214 case VPADDSWZrrk:
33215 case VPADDSWZrrkz:
33216 case VPADDSWrm:
33217 case VPADDSWrr:
33218 return true;
33219 }
33220 return false;
33221}
33222
33223bool isVADDSUBPD(unsigned Opcode) {
33224 switch (Opcode) {
33225 case VADDSUBPDYrm:
33226 case VADDSUBPDYrr:
33227 case VADDSUBPDrm:
33228 case VADDSUBPDrr:
33229 return true;
33230 }
33231 return false;
33232}
33233
33234bool isKANDD(unsigned Opcode) {
33235 return Opcode == KANDDkk;
33236}
33237
33238bool isOUTSB(unsigned Opcode) {
33239 return Opcode == OUTSB;
33240}
33241
33242bool isPREFETCHRST2(unsigned Opcode) {
33243 return Opcode == PREFETCHRST2;
33244}
33245
33246bool isFNSTSW(unsigned Opcode) {
33247 switch (Opcode) {
33248 case FNSTSW16r:
33249 case FNSTSWm:
33250 return true;
33251 }
33252 return false;
33253}
33254
33255bool isPMINSB(unsigned Opcode) {
33256 switch (Opcode) {
33257 case PMINSBrm:
33258 case PMINSBrr:
33259 return true;
33260 }
33261 return false;
33262}
33263
33264
33265} // namespace llvm::X86
33266
33267#endif // GET_X86_MNEMONIC_TABLES_CPP
33268
33269