1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* X86 Mnemonic tables *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10namespace X86 {
11
12#ifdef GET_X86_MNEMONIC_TABLES_H
13#undef GET_X86_MNEMONIC_TABLES_H
14
15bool isFSUBRP(unsigned Opcode);
16bool isVPDPBUSDS(unsigned Opcode);
17bool isPUNPCKLWD(unsigned Opcode);
18bool isVREDUCEBF16(unsigned Opcode);
19bool isPUNPCKLQDQ(unsigned Opcode);
20bool isRDFSBASE(unsigned Opcode);
21bool isVPCMOV(unsigned Opcode);
22bool isVDIVSD(unsigned Opcode);
23bool isVCVTTPS2IBS(unsigned Opcode);
24bool isVPEXTRW(unsigned Opcode);
25bool isLODSD(unsigned Opcode);
26bool isVPTESTNMQ(unsigned Opcode);
27bool isCVTSS2SD(unsigned Opcode);
28bool isVGETMANTPD(unsigned Opcode);
29bool isVMOVDQA64(unsigned Opcode);
30bool isINVLPG(unsigned Opcode);
31bool isVGETEXPBF16(unsigned Opcode);
32bool isVBROADCASTF64X4(unsigned Opcode);
33bool isVPERMI2Q(unsigned Opcode);
34bool isVPMOVSXBD(unsigned Opcode);
35bool isVFMSUB132SS(unsigned Opcode);
36bool isVPMOVUSDW(unsigned Opcode);
37bool isAAD(unsigned Opcode);
38bool isIDIV(unsigned Opcode);
39bool isCVTTPS2DQ(unsigned Opcode);
40bool isVBROADCASTF32X8(unsigned Opcode);
41bool isVFMSUBSS(unsigned Opcode);
42bool isEMMS(unsigned Opcode);
43bool isVPDPBSUD(unsigned Opcode);
44bool isPMOVSXWQ(unsigned Opcode);
45bool isPSRLW(unsigned Opcode);
46bool isMOVNTDQA(unsigned Opcode);
47bool isFUCOMPI(unsigned Opcode);
48bool isANDNPS(unsigned Opcode);
49bool isVINSERTF64X2(unsigned Opcode);
50bool isCLTS(unsigned Opcode);
51bool isSETSSBSY(unsigned Opcode);
52bool isVMULPD(unsigned Opcode);
53bool isVFMADDSUB132PS(unsigned Opcode);
54bool isVPMADCSWD(unsigned Opcode);
55bool isVSCATTERPF0DPS(unsigned Opcode);
56bool isXCHG(unsigned Opcode);
57bool isVGATHERPF1QPS(unsigned Opcode);
58bool isVCVTNEPS2BF16(unsigned Opcode);
59bool isVFMADDSS(unsigned Opcode);
60bool isINTO(unsigned Opcode);
61bool isANDPD(unsigned Opcode);
62bool isSEAMCALL(unsigned Opcode);
63bool isVPDPBSSDS(unsigned Opcode);
64bool isUNPCKHPS(unsigned Opcode);
65bool isSETZUCC(unsigned Opcode);
66bool isSHUFPD(unsigned Opcode);
67bool isFCMOVNB(unsigned Opcode);
68bool isCVTTSS2SI(unsigned Opcode);
69bool isEXTRQ(unsigned Opcode);
70bool isSHLD(unsigned Opcode);
71bool isVBROADCASTSS(unsigned Opcode);
72bool isCLUI(unsigned Opcode);
73bool isVINSERTI128(unsigned Opcode);
74bool isVBLENDPD(unsigned Opcode);
75bool isVPSHLDW(unsigned Opcode);
76bool isVCVTNEEPH2PS(unsigned Opcode);
77bool isVCVTTSD2SI(unsigned Opcode);
78bool isVSM4KEY4(unsigned Opcode);
79bool isWRMSRNS(unsigned Opcode);
80bool isCMPSB(unsigned Opcode);
81bool isVRCPBF16(unsigned Opcode);
82bool isMULSS(unsigned Opcode);
83bool isVMRUN(unsigned Opcode);
84bool isVPSRLVD(unsigned Opcode);
85bool isLEAVE(unsigned Opcode);
86bool isVGETMANTPS(unsigned Opcode);
87bool isXSHA256(unsigned Opcode);
88bool isBOUND(unsigned Opcode);
89bool isSFENCE(unsigned Opcode);
90bool isVPHADDD(unsigned Opcode);
91bool isADOX(unsigned Opcode);
92bool isVPSLLQ(unsigned Opcode);
93bool isVCVTPH2HF8(unsigned Opcode);
94bool isPFRSQIT1(unsigned Opcode);
95bool isCLAC(unsigned Opcode);
96bool isKNOTW(unsigned Opcode);
97bool isVCVTPH2PD(unsigned Opcode);
98bool isVAESENC(unsigned Opcode);
99bool isMOVNTI(unsigned Opcode);
100bool isFXCH(unsigned Opcode);
101bool isPOPP(unsigned Opcode);
102bool isVPBLENDMD(unsigned Opcode);
103bool isFSINCOS(unsigned Opcode);
104bool isVPMULLW(unsigned Opcode);
105bool isVPMOVSXBW(unsigned Opcode);
106bool isSTC(unsigned Opcode);
107bool isVPINSRB(unsigned Opcode);
108bool isLWPVAL(unsigned Opcode);
109bool isKXORB(unsigned Opcode);
110bool isRSTORSSP(unsigned Opcode);
111bool isVPRORQ(unsigned Opcode);
112bool isVSM3MSG1(unsigned Opcode);
113bool isFICOM(unsigned Opcode);
114bool isMAXPS(unsigned Opcode);
115bool isFNCLEX(unsigned Opcode);
116bool isVMOVMSKPS(unsigned Opcode);
117bool isVPMOVDB(unsigned Opcode);
118bool isLLWPCB(unsigned Opcode);
119bool isVMULSS(unsigned Opcode);
120bool isAESENCLAST(unsigned Opcode);
121bool isTILEMOVROW(unsigned Opcode);
122bool isVMINMAXPH(unsigned Opcode);
123bool isVPMAXUB(unsigned Opcode);
124bool isAAS(unsigned Opcode);
125bool isFADD(unsigned Opcode);
126bool isJMP(unsigned Opcode);
127bool isXCRYPTECB(unsigned Opcode);
128bool isPFRCPIT1(unsigned Opcode);
129bool isPMULHRW(unsigned Opcode);
130bool isVCVTPH2PS(unsigned Opcode);
131bool isVPBLENDVB(unsigned Opcode);
132bool isPCMPESTRI(unsigned Opcode);
133bool isSENDUIPI(unsigned Opcode);
134bool isFLDLN2(unsigned Opcode);
135bool isVPMACSWD(unsigned Opcode);
136bool isSHA1MSG1(unsigned Opcode);
137bool isVADDPS(unsigned Opcode);
138bool isVCVTPS2DQ(unsigned Opcode);
139bool isPFPNACC(unsigned Opcode);
140bool isFMUL(unsigned Opcode);
141bool isFNSAVE(unsigned Opcode);
142bool isCDQE(unsigned Opcode);
143bool isVPMACSDD(unsigned Opcode);
144bool isVSQRTPS(unsigned Opcode);
145bool isCMPSQ(unsigned Opcode);
146bool isVPSCATTERDD(unsigned Opcode);
147bool isVCVTTSD2USIS(unsigned Opcode);
148bool isVRNDSCALESD(unsigned Opcode);
149bool isSUBPS(unsigned Opcode);
150bool isVMAXSH(unsigned Opcode);
151bool isFLDZ(unsigned Opcode);
152bool isVFNMADD132SS(unsigned Opcode);
153bool isLGDTW(unsigned Opcode);
154bool isTCVTROWPS2PHH(unsigned Opcode);
155bool isINC(unsigned Opcode);
156bool isVPANDN(unsigned Opcode);
157bool isPABSB(unsigned Opcode);
158bool isVSHA512RNDS2(unsigned Opcode);
159bool isPHADDSW(unsigned Opcode);
160bool isVPMAXUD(unsigned Opcode);
161bool isVPMOVSQW(unsigned Opcode);
162bool isADDSUBPS(unsigned Opcode);
163bool isVPMACSSDQL(unsigned Opcode);
164bool isPXOR(unsigned Opcode);
165bool isVPSRAD(unsigned Opcode);
166bool isVPSHAB(unsigned Opcode);
167bool isBTR(unsigned Opcode);
168bool isKORW(unsigned Opcode);
169bool isVRANGESS(unsigned Opcode);
170bool isVCMPPS(unsigned Opcode);
171bool isVPLZCNTD(unsigned Opcode);
172bool isTDPBUUD(unsigned Opcode);
173bool isROUNDPS(unsigned Opcode);
174bool isFABS(unsigned Opcode);
175bool isSUBPD(unsigned Opcode);
176bool isGF2P8MULB(unsigned Opcode);
177bool isTZMSK(unsigned Opcode);
178bool isVMINMAXSD(unsigned Opcode);
179bool isANDPS(unsigned Opcode);
180bool isVEXTRACTF32X8(unsigned Opcode);
181bool isSEAMRET(unsigned Opcode);
182bool isVPCOMW(unsigned Opcode);
183bool isVFIXUPIMMPD(unsigned Opcode);
184bool isKANDND(unsigned Opcode);
185bool isVMRESUME(unsigned Opcode);
186bool isCVTPD2DQ(unsigned Opcode);
187bool isVFNMADD213PS(unsigned Opcode);
188bool isVPEXTRD(unsigned Opcode);
189bool isPACKUSWB(unsigned Opcode);
190bool isVEXTRACTI32X8(unsigned Opcode);
191bool isVHADDPD(unsigned Opcode);
192bool isVPSADBW(unsigned Opcode);
193bool isMOVDQ2Q(unsigned Opcode);
194bool isPUNPCKHBW(unsigned Opcode);
195bool isXOR(unsigned Opcode);
196bool isPSIGNB(unsigned Opcode);
197bool isVPHADDSW(unsigned Opcode);
198bool isFADDP(unsigned Opcode);
199bool isNEG(unsigned Opcode);
200bool isFLDLG2(unsigned Opcode);
201bool isFNOP(unsigned Opcode);
202bool isVMINSS(unsigned Opcode);
203bool isPCMPISTRM(unsigned Opcode);
204bool isVFMADD132SS(unsigned Opcode);
205bool isFDIVRP(unsigned Opcode);
206bool isPUSHAL(unsigned Opcode);
207bool isVPMACSDQL(unsigned Opcode);
208bool isSUBSD(unsigned Opcode);
209bool isVPBLENDMQ(unsigned Opcode);
210bool isVGATHERDPS(unsigned Opcode);
211bool isSYSRET(unsigned Opcode);
212bool isVPADDB(unsigned Opcode);
213bool isXEND(unsigned Opcode);
214bool isWRSSD(unsigned Opcode);
215bool isVMINMAXSS(unsigned Opcode);
216bool isVCVTDQ2PH(unsigned Opcode);
217bool isCVTPD2PS(unsigned Opcode);
218bool isMAXPD(unsigned Opcode);
219bool isRCPSS(unsigned Opcode);
220bool isVMOVAPD(unsigned Opcode);
221bool isVPSUBSB(unsigned Opcode);
222bool isRDTSC(unsigned Opcode);
223bool isVCVTTPS2UDQS(unsigned Opcode);
224bool isVPMADCSSWD(unsigned Opcode);
225bool isVFNMADD213PH(unsigned Opcode);
226bool isVGF2P8AFFINEQB(unsigned Opcode);
227bool isPMOVZXWD(unsigned Opcode);
228bool isPMINUD(unsigned Opcode);
229bool isVCVTPH2UW(unsigned Opcode);
230bool isPADDSW(unsigned Opcode);
231bool isXSUSLDTRK(unsigned Opcode);
232bool isLFENCE(unsigned Opcode);
233bool isCRC32(unsigned Opcode);
234bool isAESENCWIDE256KL(unsigned Opcode);
235bool isMOVAPD(unsigned Opcode);
236bool isVFMADD213PS(unsigned Opcode);
237bool isVPDPWUUDS(unsigned Opcode);
238bool isMOVSLDUP(unsigned Opcode);
239bool isCLDEMOTE(unsigned Opcode);
240bool isVFNMADD231PS(unsigned Opcode);
241bool isVMOVMSKPD(unsigned Opcode);
242bool isPREFETCHT0(unsigned Opcode);
243bool isVCVTNEOBF162PS(unsigned Opcode);
244bool isVPCMPUD(unsigned Opcode);
245bool isVMAXSD(unsigned Opcode);
246bool isVRCP28SD(unsigned Opcode);
247bool isVMAXPS(unsigned Opcode);
248bool isVPMOVD2M(unsigned Opcode);
249bool isVPMACSSWD(unsigned Opcode);
250bool isVUCOMISD(unsigned Opcode);
251bool isLTR(unsigned Opcode);
252bool isVCVTUSI2SH(unsigned Opcode);
253bool isVSCATTERPF1QPS(unsigned Opcode);
254bool isWRGSBASE(unsigned Opcode);
255bool isSTOSQ(unsigned Opcode);
256bool isVSQRTSD(unsigned Opcode);
257bool isVPERMIL2PD(unsigned Opcode);
258bool isVFCMADDCSH(unsigned Opcode);
259bool isVFMADDSUB213PS(unsigned Opcode);
260bool isPFSUB(unsigned Opcode);
261bool isVSQRTSS(unsigned Opcode);
262bool isVEXPANDPS(unsigned Opcode);
263bool isVPCOMPRESSW(unsigned Opcode);
264bool isPEXTRD(unsigned Opcode);
265bool isVCVTTPS2UQQS(unsigned Opcode);
266bool isSYSEXITQ(unsigned Opcode);
267bool isROUNDSD(unsigned Opcode);
268bool isVFMADD132BF16(unsigned Opcode);
269bool isFCOM(unsigned Opcode);
270bool isVFNMSUBSS(unsigned Opcode);
271bool isKSHIFTLW(unsigned Opcode);
272bool isSCASD(unsigned Opcode);
273bool isVMPTRLD(unsigned Opcode);
274bool isVAESDECLAST(unsigned Opcode);
275bool isVFMADDSUBPS(unsigned Opcode);
276bool isVCVTUQQ2PS(unsigned Opcode);
277bool isVPMOVUSDB(unsigned Opcode);
278bool isVPROTW(unsigned Opcode);
279bool isVDPPS(unsigned Opcode);
280bool isVRSQRT14PD(unsigned Opcode);
281bool isVTESTPD(unsigned Opcode);
282bool isVFNMADD231SH(unsigned Opcode);
283bool isENDBR64(unsigned Opcode);
284bool isMULSD(unsigned Opcode);
285bool isXRSTORS(unsigned Opcode);
286bool isPREFETCHNTA(unsigned Opcode);
287bool isVPCOMD(unsigned Opcode);
288bool isVPCOMUB(unsigned Opcode);
289bool isVPHSUBD(unsigned Opcode);
290bool isVBROADCASTI64X2(unsigned Opcode);
291bool isFPATAN(unsigned Opcode);
292bool isLOOPE(unsigned Opcode);
293bool isPCMPEQW(unsigned Opcode);
294bool isVFMADDCSH(unsigned Opcode);
295bool isVPDPBSSD(unsigned Opcode);
296bool isMOVRS(unsigned Opcode);
297bool isVFMSUBADD132PH(unsigned Opcode);
298bool isKADDW(unsigned Opcode);
299bool isPTEST(unsigned Opcode);
300bool isVRSQRT28PS(unsigned Opcode);
301bool isVGF2P8AFFINEINVQB(unsigned Opcode);
302bool isSERIALIZE(unsigned Opcode);
303bool isVPHADDWQ(unsigned Opcode);
304bool isVRNDSCALESH(unsigned Opcode);
305bool isAAA(unsigned Opcode);
306bool isVADDBF16(unsigned Opcode);
307bool isWRMSRLIST(unsigned Opcode);
308bool isVCVTPH2PSX(unsigned Opcode);
309bool isVFMSUB231PH(unsigned Opcode);
310bool isVGATHERQPD(unsigned Opcode);
311bool isKADDB(unsigned Opcode);
312bool isCVTPD2PI(unsigned Opcode);
313bool isVFNMSUB213PH(unsigned Opcode);
314bool isXORPS(unsigned Opcode);
315bool isVPCMPESTRI(unsigned Opcode);
316bool isVPADDSB(unsigned Opcode);
317bool isPOP2(unsigned Opcode);
318bool isRDMSRLIST(unsigned Opcode);
319bool isVPSHRDW(unsigned Opcode);
320bool isVPDPBUSD(unsigned Opcode);
321bool isVCMPPH(unsigned Opcode);
322bool isVANDNPD(unsigned Opcode);
323bool isSUB(unsigned Opcode);
324bool isVRSQRT28PD(unsigned Opcode);
325bool isVFNMADD132PH(unsigned Opcode);
326bool isVPMACSSWW(unsigned Opcode);
327bool isXSTORE(unsigned Opcode);
328bool isVPROTQ(unsigned Opcode);
329bool isVPHADDBD(unsigned Opcode);
330bool isVPMAXSB(unsigned Opcode);
331bool isVMOVDQU8(unsigned Opcode);
332bool isVPMOVSXWD(unsigned Opcode);
333bool isVMINMAXPD(unsigned Opcode);
334bool isSHA256RNDS2(unsigned Opcode);
335bool isKANDB(unsigned Opcode);
336bool isTPAUSE(unsigned Opcode);
337bool isPUSH(unsigned Opcode);
338bool isVRNDSCALESS(unsigned Opcode);
339bool isVRNDSCALEBF16(unsigned Opcode);
340bool isVPCMPISTRI(unsigned Opcode);
341bool isSTGI(unsigned Opcode);
342bool isSBB(unsigned Opcode);
343bool isBLCS(unsigned Opcode);
344bool isVCVTSD2SH(unsigned Opcode);
345bool isVPERMW(unsigned Opcode);
346bool isXRESLDTRK(unsigned Opcode);
347bool isAESENC256KL(unsigned Opcode);
348bool isVGATHERDPD(unsigned Opcode);
349bool isHRESET(unsigned Opcode);
350bool isVFMSUBADD231PD(unsigned Opcode);
351bool isVFRCZSS(unsigned Opcode);
352bool isMINPS(unsigned Opcode);
353bool isFPREM1(unsigned Opcode);
354bool isVPCMPUB(unsigned Opcode);
355bool isVSQRTPD(unsigned Opcode);
356bool isVFRCZPS(unsigned Opcode);
357bool isVFNMADD213SS(unsigned Opcode);
358bool isVPMOVDW(unsigned Opcode);
359bool isVCVTPH2HF8S(unsigned Opcode);
360bool isVPSHRDVQ(unsigned Opcode);
361bool isVBROADCASTSD(unsigned Opcode);
362bool isVSHUFPD(unsigned Opcode);
363bool isVPSUBSW(unsigned Opcode);
364bool isKUNPCKBW(unsigned Opcode);
365bool isVPBLENDD(unsigned Opcode);
366bool isUNPCKHPD(unsigned Opcode);
367bool isVFNMADD231SD(unsigned Opcode);
368bool isVPBROADCASTMW2D(unsigned Opcode);
369bool isVPMULTISHIFTQB(unsigned Opcode);
370bool isVP2INTERSECTQ(unsigned Opcode);
371bool isVFNMSUB132BF16(unsigned Opcode);
372bool isVFMADD213BF16(unsigned Opcode);
373bool isVPUNPCKHWD(unsigned Opcode);
374bool isVPERM2F128(unsigned Opcode);
375bool isINSD(unsigned Opcode);
376bool isLFS(unsigned Opcode);
377bool isFMULP(unsigned Opcode);
378bool isCWD(unsigned Opcode);
379bool isVDIVSS(unsigned Opcode);
380bool isVPSRLQ(unsigned Opcode);
381bool isFSQRT(unsigned Opcode);
382bool isJRCXZ(unsigned Opcode);
383bool isVPMOVMSKB(unsigned Opcode);
384bool isAESDEC256KL(unsigned Opcode);
385bool isFLDENV(unsigned Opcode);
386bool isVPHSUBWD(unsigned Opcode);
387bool isWBNOINVD(unsigned Opcode);
388bool isVEXPANDPD(unsigned Opcode);
389bool isFYL2XP1(unsigned Opcode);
390bool isPREFETCHT2(unsigned Opcode);
391bool isVPDPBSUDS(unsigned Opcode);
392bool isVSHA512MSG2(unsigned Opcode);
393bool isPMULHUW(unsigned Opcode);
394bool isKANDNB(unsigned Opcode);
395bool isVCVTUW2PH(unsigned Opcode);
396bool isAESDECWIDE256KL(unsigned Opcode);
397bool isVPGATHERDD(unsigned Opcode);
398bool isVREDUCESH(unsigned Opcode);
399bool isPOPFQ(unsigned Opcode);
400bool isPAVGUSB(unsigned Opcode);
401bool isVALIGND(unsigned Opcode);
402bool isVPHMINPOSUW(unsigned Opcode);
403bool isLIDTD(unsigned Opcode);
404bool isVPERMT2PD(unsigned Opcode);
405bool isVMLAUNCH(unsigned Opcode);
406bool isVPXORQ(unsigned Opcode);
407bool isMOVNTDQ(unsigned Opcode);
408bool isPOP2P(unsigned Opcode);
409bool isVADDPD(unsigned Opcode);
410bool isSMSW(unsigned Opcode);
411bool isVEXP2PD(unsigned Opcode);
412bool isPMULUDQ(unsigned Opcode);
413bool isIRET(unsigned Opcode);
414bool isMULPS(unsigned Opcode);
415bool isTDPBF8PS(unsigned Opcode);
416bool isVFNMSUBPD(unsigned Opcode);
417bool isPHADDW(unsigned Opcode);
418bool isRDSEED(unsigned Opcode);
419bool isVPSHLW(unsigned Opcode);
420bool isRMPUPDATE(unsigned Opcode);
421bool isVFMADD231PH(unsigned Opcode);
422bool isVPSHAD(unsigned Opcode);
423bool isCLWB(unsigned Opcode);
424bool isPSUBUSB(unsigned Opcode);
425bool isVCVTTSD2USI(unsigned Opcode);
426bool isVEXTRACTPS(unsigned Opcode);
427bool isMOVLPD(unsigned Opcode);
428bool isLGDTD(unsigned Opcode);
429bool isVPBROADCASTMB2Q(unsigned Opcode);
430bool isOUT(unsigned Opcode);
431bool isVMSAVE(unsigned Opcode);
432bool isVCVTQQ2PD(unsigned Opcode);
433bool isVFMADD213PH(unsigned Opcode);
434bool isFCMOVBE(unsigned Opcode);
435bool isMOVSHDUP(unsigned Opcode);
436bool isVPMOVUSQB(unsigned Opcode);
437bool isFIST(unsigned Opcode);
438bool isHADDPD(unsigned Opcode);
439bool isPACKSSWB(unsigned Opcode);
440bool isVPMACSSDQH(unsigned Opcode);
441bool isVFNMSUB132SD(unsigned Opcode);
442bool isVPMASKMOVQ(unsigned Opcode);
443bool isVCOMPRESSPD(unsigned Opcode);
444bool isVFMADD213SS(unsigned Opcode);
445bool isVPCMPQ(unsigned Opcode);
446bool isVADDSH(unsigned Opcode);
447bool isVFNMADDSD(unsigned Opcode);
448bool isUMWAIT(unsigned Opcode);
449bool isVPUNPCKHDQ(unsigned Opcode);
450bool isLCALL(unsigned Opcode);
451bool isAESDEC128KL(unsigned Opcode);
452bool isVSUBPS(unsigned Opcode);
453bool isFSTP(unsigned Opcode);
454bool isVCVTUDQ2PD(unsigned Opcode);
455bool isVPMOVSWB(unsigned Opcode);
456bool isVPANDNQ(unsigned Opcode);
457bool isSYSENTER(unsigned Opcode);
458bool isVPHADDWD(unsigned Opcode);
459bool isVMOVHPD(unsigned Opcode);
460bool isMOVHPD(unsigned Opcode);
461bool isVDIVPH(unsigned Opcode);
462bool isFFREE(unsigned Opcode);
463bool isVGATHERPF1DPS(unsigned Opcode);
464bool isVFNMADD231PD(unsigned Opcode);
465bool isVFCMULCPH(unsigned Opcode);
466bool isVPADDD(unsigned Opcode);
467bool isVSM3MSG2(unsigned Opcode);
468bool isVPCOMUQ(unsigned Opcode);
469bool isVERR(unsigned Opcode);
470bool isKORTESTQ(unsigned Opcode);
471bool isVFMSUB132SD(unsigned Opcode);
472bool isTILEZERO(unsigned Opcode);
473bool isPFADD(unsigned Opcode);
474bool isVCVTSI2SD(unsigned Opcode);
475bool isTILELOADDRS(unsigned Opcode);
476bool isVSTMXCSR(unsigned Opcode);
477bool isVCVTTSH2SI(unsigned Opcode);
478bool isRET(unsigned Opcode);
479bool isLZCNT(unsigned Opcode);
480bool isMULPD(unsigned Opcode);
481bool isVBROADCASTI32X2(unsigned Opcode);
482bool isVCVTPH2W(unsigned Opcode);
483bool isCQO(unsigned Opcode);
484bool isFSUBR(unsigned Opcode);
485bool isDPPD(unsigned Opcode);
486bool isFCOS(unsigned Opcode);
487bool isXSAVES(unsigned Opcode);
488bool isTZCNT(unsigned Opcode);
489bool isLJMP(unsigned Opcode);
490bool isCMOVCC(unsigned Opcode);
491bool isVCVTBIASPH2HF8(unsigned Opcode);
492bool isINVEPT(unsigned Opcode);
493bool isADDSUBPD(unsigned Opcode);
494bool isVMOVSHDUP(unsigned Opcode);
495bool isKSHIFTRD(unsigned Opcode);
496bool isVCVTSS2SD(unsigned Opcode);
497bool isPADDQ(unsigned Opcode);
498bool isVEXTRACTI64X4(unsigned Opcode);
499bool isVFMSUB231SS(unsigned Opcode);
500bool isVPCMPEQB(unsigned Opcode);
501bool isVPTERNLOGD(unsigned Opcode);
502bool isLEA(unsigned Opcode);
503bool isPSUBB(unsigned Opcode);
504bool isKADDQ(unsigned Opcode);
505bool isMOVSX(unsigned Opcode);
506bool isVALIGNQ(unsigned Opcode);
507bool isVCVTNE2PS2BF16(unsigned Opcode);
508bool isVPSRAW(unsigned Opcode);
509bool isVFMSUBADD231PH(unsigned Opcode);
510bool isCVTDQ2PS(unsigned Opcode);
511bool isFBLD(unsigned Opcode);
512bool isLMSW(unsigned Opcode);
513bool isWRMSR(unsigned Opcode);
514bool isMINSS(unsigned Opcode);
515bool isFSCALE(unsigned Opcode);
516bool isVFNMADD213SH(unsigned Opcode);
517bool isIMULZU(unsigned Opcode);
518bool isVPHADDUBD(unsigned Opcode);
519bool isRDSSPQ(unsigned Opcode);
520bool isVCVTBF162IBS(unsigned Opcode);
521bool isLGDT(unsigned Opcode);
522bool isVPSHLDVD(unsigned Opcode);
523bool isPFCMPGT(unsigned Opcode);
524bool isVRNDSCALEPH(unsigned Opcode);
525bool isJCXZ(unsigned Opcode);
526bool isVPMOVZXBW(unsigned Opcode);
527bool isVFMADDSUB231PD(unsigned Opcode);
528bool isVBLENDMPD(unsigned Opcode);
529bool isHSUBPS(unsigned Opcode);
530bool isPREFETCHIT0(unsigned Opcode);
531bool isKTESTD(unsigned Opcode);
532bool isVCVTNEOPH2PS(unsigned Opcode);
533bool isVBLENDVPD(unsigned Opcode);
534bool isVCVTSS2USI(unsigned Opcode);
535bool isVCVTTPS2DQS(unsigned Opcode);
536bool isVPANDD(unsigned Opcode);
537bool isPMINSW(unsigned Opcode);
538bool isSTAC(unsigned Opcode);
539bool isVFMSUB213PS(unsigned Opcode);
540bool isPOPAL(unsigned Opcode);
541bool isVCVTPS2UQQ(unsigned Opcode);
542bool isRDRAND(unsigned Opcode);
543bool isJCC(unsigned Opcode);
544bool isVPMINSQ(unsigned Opcode);
545bool isVADDSD(unsigned Opcode);
546bool isDPPS(unsigned Opcode);
547bool isPINSRQ(unsigned Opcode);
548bool isVUCOMISS(unsigned Opcode);
549bool isVPDPWSUD(unsigned Opcode);
550bool isKANDNW(unsigned Opcode);
551bool isAOR(unsigned Opcode);
552bool isPMAXUB(unsigned Opcode);
553bool isANDNPD(unsigned Opcode);
554bool isINVPCID(unsigned Opcode);
555bool isRDGSBASE(unsigned Opcode);
556bool isVPMOVSQD(unsigned Opcode);
557bool isBT(unsigned Opcode);
558bool isVPROLVQ(unsigned Opcode);
559bool isVFMADDSUB132PD(unsigned Opcode);
560bool isRORX(unsigned Opcode);
561bool isPADDUSW(unsigned Opcode);
562bool isPFNACC(unsigned Opcode);
563bool isAND(unsigned Opcode);
564bool isPSLLQ(unsigned Opcode);
565bool isVFMSUB132PH(unsigned Opcode);
566bool isXSAVE(unsigned Opcode);
567bool isKNOTQ(unsigned Opcode);
568bool isXTEST(unsigned Opcode);
569bool isVINSERTPS(unsigned Opcode);
570bool isXSAVEOPT(unsigned Opcode);
571bool isLDS(unsigned Opcode);
572bool isVFMADDSUB213PD(unsigned Opcode);
573bool isVINSERTF32X4(unsigned Opcode);
574bool isVRSQRTPS(unsigned Opcode);
575bool isVSUBPH(unsigned Opcode);
576bool isPMOVSXBW(unsigned Opcode);
577bool isVPSRLDQ(unsigned Opcode);
578bool isADC(unsigned Opcode);
579bool isPHADDD(unsigned Opcode);
580bool isVDPPHPS(unsigned Opcode);
581bool isVMINPH(unsigned Opcode);
582bool isVMINSD(unsigned Opcode);
583bool isVROUNDPD(unsigned Opcode);
584bool isVFCMADDCPH(unsigned Opcode);
585bool isINCSSPQ(unsigned Opcode);
586bool isVPUNPCKLDQ(unsigned Opcode);
587bool isVMINSH(unsigned Opcode);
588bool isINSERTQ(unsigned Opcode);
589bool isBLCI(unsigned Opcode);
590bool isHLT(unsigned Opcode);
591bool isVPCOMUW(unsigned Opcode);
592bool isVPMOVSXDQ(unsigned Opcode);
593bool isVFNMSUB231PS(unsigned Opcode);
594bool isVFNMSUB213SH(unsigned Opcode);
595bool isVCVTTPD2UQQ(unsigned Opcode);
596bool isSQRTSS(unsigned Opcode);
597bool isIMUL(unsigned Opcode);
598bool isVCVTSS2SI(unsigned Opcode);
599bool isPUSHAW(unsigned Opcode);
600bool isSTOSD(unsigned Opcode);
601bool isPSRLDQ(unsigned Opcode);
602bool isVSCATTERQPS(unsigned Opcode);
603bool isFIDIV(unsigned Opcode);
604bool isVFMSUB213PD(unsigned Opcode);
605bool isVFMADDSUB231PH(unsigned Opcode);
606bool isTDCALL(unsigned Opcode);
607bool isPVALIDATE(unsigned Opcode);
608bool isVPSHUFLW(unsigned Opcode);
609bool isPCLMULQDQ(unsigned Opcode);
610bool isCMPXCHG8B(unsigned Opcode);
611bool isVPMOVM2B(unsigned Opcode);
612bool isVCVTUDQ2PH(unsigned Opcode);
613bool isPEXTRQ(unsigned Opcode);
614bool isXCRYPTCTR(unsigned Opcode);
615bool isVREDUCEPH(unsigned Opcode);
616bool isUCOMISD(unsigned Opcode);
617bool isOUTSD(unsigned Opcode);
618bool isSUBSS(unsigned Opcode);
619bool isVFMSUBPS(unsigned Opcode);
620bool isVPBLENDW(unsigned Opcode);
621bool isBZHI(unsigned Opcode);
622bool isVPRORVD(unsigned Opcode);
623bool isRMPQUERY(unsigned Opcode);
624bool isVPEXPANDB(unsigned Opcode);
625bool isVPSCATTERDQ(unsigned Opcode);
626bool isPSMASH(unsigned Opcode);
627bool isVPSHLDQ(unsigned Opcode);
628bool isVSCATTERPF1DPD(unsigned Opcode);
629bool isMONTMUL(unsigned Opcode);
630bool isVCVTPH2UQQ(unsigned Opcode);
631bool isPSLLD(unsigned Opcode);
632bool isSAR(unsigned Opcode);
633bool isLDTILECFG(unsigned Opcode);
634bool isPMINUB(unsigned Opcode);
635bool isVCVTNEEBF162PS(unsigned Opcode);
636bool isMOVDIR64B(unsigned Opcode);
637bool isSTR(unsigned Opcode);
638bool isKANDNQ(unsigned Opcode);
639bool isBSF(unsigned Opcode);
640bool isVPDPBUUDS(unsigned Opcode);
641bool isINCSSPD(unsigned Opcode);
642bool isSQRTPS(unsigned Opcode);
643bool isCMPXCHG(unsigned Opcode);
644bool isVPSIGNW(unsigned Opcode);
645bool isVCOMISBF16(unsigned Opcode);
646bool isLES(unsigned Opcode);
647bool isCVTSS2SI(unsigned Opcode);
648bool isVPMOVUSWB(unsigned Opcode);
649bool isFCOMPI(unsigned Opcode);
650bool isPUNPCKHWD(unsigned Opcode);
651bool isPFACC(unsigned Opcode);
652bool isVPTESTNMW(unsigned Opcode);
653bool isVPMULDQ(unsigned Opcode);
654bool isSHRX(unsigned Opcode);
655bool isKXORQ(unsigned Opcode);
656bool isVGETEXPSD(unsigned Opcode);
657bool isV4FNMADDPS(unsigned Opcode);
658bool isVFNMSUB231SD(unsigned Opcode);
659bool isVPSHLD(unsigned Opcode);
660bool isPAVGB(unsigned Opcode);
661bool isPMOVZXBD(unsigned Opcode);
662bool isKORTESTW(unsigned Opcode);
663bool isVSHUFPS(unsigned Opcode);
664bool isAESENCWIDE128KL(unsigned Opcode);
665bool isVPXORD(unsigned Opcode);
666bool isVPSHAW(unsigned Opcode);
667bool isVFMSUB132BF16(unsigned Opcode);
668bool isVPERMT2B(unsigned Opcode);
669bool isVFMADD213PD(unsigned Opcode);
670bool isVPGATHERQD(unsigned Opcode);
671bool isVFNMSUB213BF16(unsigned Opcode);
672bool isVCVTPS2IBS(unsigned Opcode);
673bool isVPCMPGTW(unsigned Opcode);
674bool isVMOVRSB(unsigned Opcode);
675bool isVGETMANTSH(unsigned Opcode);
676bool isVANDPS(unsigned Opcode);
677bool isVDIVPS(unsigned Opcode);
678bool isVANDNPS(unsigned Opcode);
679bool isVPBROADCASTW(unsigned Opcode);
680bool isFLDL2T(unsigned Opcode);
681bool isVPERMB(unsigned Opcode);
682bool isFCMOVNBE(unsigned Opcode);
683bool isVCVTTPH2W(unsigned Opcode);
684bool isPMOVZXBQ(unsigned Opcode);
685bool isPF2ID(unsigned Opcode);
686bool isVFNMADD132PD(unsigned Opcode);
687bool isPMULHRSW(unsigned Opcode);
688bool isKADDD(unsigned Opcode);
689bool isVFNMSUB132SH(unsigned Opcode);
690bool isUIRET(unsigned Opcode);
691bool isBSR(unsigned Opcode);
692bool isPCMPEQQ(unsigned Opcode);
693bool isCDQ(unsigned Opcode);
694bool isPMAXSW(unsigned Opcode);
695bool isSIDTD(unsigned Opcode);
696bool isVCVTPS2PHX(unsigned Opcode);
697bool isVPSLLVQ(unsigned Opcode);
698bool isMOVQ(unsigned Opcode);
699bool isVCMPBF16(unsigned Opcode);
700bool isPREFETCH(unsigned Opcode);
701bool isCLRSSBSY(unsigned Opcode);
702bool isTCVTROWPS2PHL(unsigned Opcode);
703bool isPSHUFW(unsigned Opcode);
704bool isVPDPWSUDS(unsigned Opcode);
705bool isVPMOVSXBQ(unsigned Opcode);
706bool isFICOMP(unsigned Opcode);
707bool isVLDMXCSR(unsigned Opcode);
708bool isVPSUBUSW(unsigned Opcode);
709bool isVFNMSUB132SS(unsigned Opcode);
710bool isRETF(unsigned Opcode);
711bool isKMOVQ(unsigned Opcode);
712bool isVPADDUSW(unsigned Opcode);
713bool isPACKSSDW(unsigned Opcode);
714bool isUMONITOR(unsigned Opcode);
715bool isENQCMDS(unsigned Opcode);
716bool isVCOMXSD(unsigned Opcode);
717bool isVPMAXSQ(unsigned Opcode);
718bool isVFMSUB213BF16(unsigned Opcode);
719bool isVPERMT2Q(unsigned Opcode);
720bool isFDECSTP(unsigned Opcode);
721bool isVPTESTMQ(unsigned Opcode);
722bool isVRCP14PD(unsigned Opcode);
723bool isARPL(unsigned Opcode);
724bool isVFMSUB213SD(unsigned Opcode);
725bool isJMPABS(unsigned Opcode);
726bool isVUNPCKHPS(unsigned Opcode);
727bool isVFNMADDSS(unsigned Opcode);
728bool isSIDT(unsigned Opcode);
729bool isVPCMPGTB(unsigned Opcode);
730bool isVPRORD(unsigned Opcode);
731bool isVSUBSS(unsigned Opcode);
732bool isPUSHFQ(unsigned Opcode);
733bool isVCVTHF82PH(unsigned Opcode);
734bool isVPCLMULQDQ(unsigned Opcode);
735bool isVPADDUSB(unsigned Opcode);
736bool isVPCMPD(unsigned Opcode);
737bool isMOVSD(unsigned Opcode);
738bool isPSUBUSW(unsigned Opcode);
739bool isVFMSUBADD132PS(unsigned Opcode);
740bool isMOVMSKPS(unsigned Opcode);
741bool isVFIXUPIMMSS(unsigned Opcode);
742bool isMFENCE(unsigned Opcode);
743bool isFTST(unsigned Opcode);
744bool isVPMADDWD(unsigned Opcode);
745bool isPOP(unsigned Opcode);
746bool isPSUBW(unsigned Opcode);
747bool isBSWAP(unsigned Opcode);
748bool isPFMIN(unsigned Opcode);
749bool isVFPCLASSPD(unsigned Opcode);
750bool isVPSHRDVD(unsigned Opcode);
751bool isPADDW(unsigned Opcode);
752bool isCVTSI2SD(unsigned Opcode);
753bool isENQCMD(unsigned Opcode);
754bool isXSHA1(unsigned Opcode);
755bool isVFNMADD132SD(unsigned Opcode);
756bool isMOVZX(unsigned Opcode);
757bool isVFIXUPIMMSD(unsigned Opcode);
758bool isINVD(unsigned Opcode);
759bool isVFIXUPIMMPS(unsigned Opcode);
760bool isMOVDQU(unsigned Opcode);
761bool isVFPCLASSPS(unsigned Opcode);
762bool isMOVSQ(unsigned Opcode);
763bool isAESDECWIDE128KL(unsigned Opcode);
764bool isROUNDSS(unsigned Opcode);
765bool isVPERMILPS(unsigned Opcode);
766bool isVPMOVW2M(unsigned Opcode);
767bool isVMULSD(unsigned Opcode);
768bool isVPERMI2W(unsigned Opcode);
769bool isVPSHUFB(unsigned Opcode);
770bool isFST(unsigned Opcode);
771bool isVPHSUBW(unsigned Opcode);
772bool isVREDUCESS(unsigned Opcode);
773bool isFRNDINT(unsigned Opcode);
774bool isSHR(unsigned Opcode);
775bool isLOOPNE(unsigned Opcode);
776bool isVCVTTPH2UQQ(unsigned Opcode);
777bool isSHA1NEXTE(unsigned Opcode);
778bool isVFMADD132SD(unsigned Opcode);
779bool isPSRAW(unsigned Opcode);
780bool isVPBROADCASTQ(unsigned Opcode);
781bool isCLC(unsigned Opcode);
782bool isPOPAW(unsigned Opcode);
783bool isTCMMIMFP16PS(unsigned Opcode);
784bool isVCVTTPS2UQQ(unsigned Opcode);
785bool isVCVTQQ2PH(unsigned Opcode);
786bool isVMOVUPD(unsigned Opcode);
787bool isFPTAN(unsigned Opcode);
788bool isVMASKMOVPD(unsigned Opcode);
789bool isVMOVLHPS(unsigned Opcode);
790bool isAESKEYGENASSIST(unsigned Opcode);
791bool isXSAVEOPT64(unsigned Opcode);
792bool isXSAVEC(unsigned Opcode);
793bool isVPLZCNTQ(unsigned Opcode);
794bool isVPSUBW(unsigned Opcode);
795bool isCMPCCXADD(unsigned Opcode);
796bool isVFMSUBADD213PH(unsigned Opcode);
797bool isVFMADDSUBPD(unsigned Opcode);
798bool isVPMINSW(unsigned Opcode);
799bool isVFNMSUB132PS(unsigned Opcode);
800bool isVMOVAPS(unsigned Opcode);
801bool isVPEXTRQ(unsigned Opcode);
802bool isVSCALEFSH(unsigned Opcode);
803bool isVCVTPD2PS(unsigned Opcode);
804bool isCLGI(unsigned Opcode);
805bool isVAESDEC(unsigned Opcode);
806bool isPFMUL(unsigned Opcode);
807bool isVCVTBIASPH2BF8S(unsigned Opcode);
808bool isMOVDIRI(unsigned Opcode);
809bool isSHUFPS(unsigned Opcode);
810bool isVFNMSUB231SS(unsigned Opcode);
811bool isVMWRITE(unsigned Opcode);
812bool isVINSERTF128(unsigned Opcode);
813bool isFISUBR(unsigned Opcode);
814bool isVINSERTI32X4(unsigned Opcode);
815bool isVPSLLDQ(unsigned Opcode);
816bool isPOPCNT(unsigned Opcode);
817bool isVXORPD(unsigned Opcode);
818bool isXLATB(unsigned Opcode);
819bool isDIV(unsigned Opcode);
820bool isVPSHLDVQ(unsigned Opcode);
821bool isMOVDDUP(unsigned Opcode);
822bool isVMOVDQU64(unsigned Opcode);
823bool isVPCOMPRESSQ(unsigned Opcode);
824bool isVFMSUBADD132PD(unsigned Opcode);
825bool isADDSD(unsigned Opcode);
826bool isBLENDPD(unsigned Opcode);
827bool isVPERMILPD(unsigned Opcode);
828bool isPMADDUBSW(unsigned Opcode);
829bool isPOPFD(unsigned Opcode);
830bool isCMPSW(unsigned Opcode);
831bool isLDMXCSR(unsigned Opcode);
832bool isVMULPS(unsigned Opcode);
833bool isVROUNDSD(unsigned Opcode);
834bool isVFMADD132PD(unsigned Opcode);
835bool isVPANDQ(unsigned Opcode);
836bool isVPSRAQ(unsigned Opcode);
837bool isVCOMISD(unsigned Opcode);
838bool isVCVTBIASPH2BF8(unsigned Opcode);
839bool isFFREEP(unsigned Opcode);
840bool isVFNMADD213PD(unsigned Opcode);
841bool isVCMPPD(unsigned Opcode);
842bool isVFNMSUB132PH(unsigned Opcode);
843bool isVPHADDBW(unsigned Opcode);
844bool isVPPERM(unsigned Opcode);
845bool isVCVTPS2PD(unsigned Opcode);
846bool isCBW(unsigned Opcode);
847bool isVMOVUPS(unsigned Opcode);
848bool isVPMAXUQ(unsigned Opcode);
849bool isWRSSQ(unsigned Opcode);
850bool isPACKUSDW(unsigned Opcode);
851bool isVCVTTBF162IBS(unsigned Opcode);
852bool isXBEGIN(unsigned Opcode);
853bool isVCVTPD2UQQ(unsigned Opcode);
854bool isFCMOVB(unsigned Opcode);
855bool isNOP(unsigned Opcode);
856bool isVPABSQ(unsigned Opcode);
857bool isVTESTPS(unsigned Opcode);
858bool isPHSUBW(unsigned Opcode);
859bool isPUSH2P(unsigned Opcode);
860bool isFISTTP(unsigned Opcode);
861bool isCFCMOVCC(unsigned Opcode);
862bool isVPINSRD(unsigned Opcode);
863bool isPCMPESTRM(unsigned Opcode);
864bool isVFNMSUB213PS(unsigned Opcode);
865bool isPHSUBD(unsigned Opcode);
866bool isVCVTTPD2DQS(unsigned Opcode);
867bool isSLDT(unsigned Opcode);
868bool isVHADDPS(unsigned Opcode);
869bool isVMOVNTDQ(unsigned Opcode);
870bool isVPMINSD(unsigned Opcode);
871bool isVFRCZSD(unsigned Opcode);
872bool isVPTESTMW(unsigned Opcode);
873bool isVPMOVZXWD(unsigned Opcode);
874bool isPSADBW(unsigned Opcode);
875bool isVCVTSD2SI(unsigned Opcode);
876bool isVMAXPH(unsigned Opcode);
877bool isLODSB(unsigned Opcode);
878bool isPHMINPOSUW(unsigned Opcode);
879bool isVPROLVD(unsigned Opcode);
880bool isWRFSBASE(unsigned Opcode);
881bool isVRSQRT14PS(unsigned Opcode);
882bool isVPHSUBDQ(unsigned Opcode);
883bool isIRETD(unsigned Opcode);
884bool isVMOVRSD(unsigned Opcode);
885bool isCVTSI2SS(unsigned Opcode);
886bool isVPMULHRSW(unsigned Opcode);
887bool isPI2FD(unsigned Opcode);
888bool isGF2P8AFFINEQB(unsigned Opcode);
889bool isPAND(unsigned Opcode);
890bool isVFNMSUB231SH(unsigned Opcode);
891bool isVCVTPH2BF8(unsigned Opcode);
892bool isVMOVHLPS(unsigned Opcode);
893bool isPEXTRB(unsigned Opcode);
894bool isVMMCALL(unsigned Opcode);
895bool isKNOTD(unsigned Opcode);
896bool isVCVTSH2SS(unsigned Opcode);
897bool isVPUNPCKLQDQ(unsigned Opcode);
898bool isVPERMIL2PS(unsigned Opcode);
899bool isVPCMPGTD(unsigned Opcode);
900bool isCMPXCHG16B(unsigned Opcode);
901bool isTDPHF8PS(unsigned Opcode);
902bool isVZEROUPPER(unsigned Opcode);
903bool isMOVAPS(unsigned Opcode);
904bool isVPCMPW(unsigned Opcode);
905bool isFUCOMPP(unsigned Opcode);
906bool isXSETBV(unsigned Opcode);
907bool isSLWPCB(unsigned Opcode);
908bool isSCASW(unsigned Opcode);
909bool isFCMOVNE(unsigned Opcode);
910bool isPBNDKB(unsigned Opcode);
911bool isVPMULLD(unsigned Opcode);
912bool isVP4DPWSSDS(unsigned Opcode);
913bool isVCVT2PH2HF8(unsigned Opcode);
914bool isPINSRW(unsigned Opcode);
915bool isVCVTSI2SH(unsigned Opcode);
916bool isVINSERTF32X8(unsigned Opcode);
917bool isKSHIFTLB(unsigned Opcode);
918bool isSEAMOPS(unsigned Opcode);
919bool isVPMULUDQ(unsigned Opcode);
920bool isVPMOVSQB(unsigned Opcode);
921bool isVPTESTMD(unsigned Opcode);
922bool isVPHADDDQ(unsigned Opcode);
923bool isKUNPCKDQ(unsigned Opcode);
924bool isT1MSKC(unsigned Opcode);
925bool isVPCOMB(unsigned Opcode);
926bool isVBLENDPS(unsigned Opcode);
927bool isPTWRITE(unsigned Opcode);
928bool isVCVTPH2BF8S(unsigned Opcode);
929bool isCVTPS2PI(unsigned Opcode);
930bool isVPROTD(unsigned Opcode);
931bool isCALL(unsigned Opcode);
932bool isTILELOADDRST1(unsigned Opcode);
933bool isVPERMPS(unsigned Opcode);
934bool isVPSHUFBITQMB(unsigned Opcode);
935bool isVMOVSLDUP(unsigned Opcode);
936bool isINVLPGA(unsigned Opcode);
937bool isVCVTPH2QQ(unsigned Opcode);
938bool isADD(unsigned Opcode);
939bool isPSUBSW(unsigned Opcode);
940bool isSIDTW(unsigned Opcode);
941bool isVFNMADD231PH(unsigned Opcode);
942bool isVEXTRACTF64X2(unsigned Opcode);
943bool isFCOMI(unsigned Opcode);
944bool isRSM(unsigned Opcode);
945bool isVPCOMUD(unsigned Opcode);
946bool isVPMOVZXBQ(unsigned Opcode);
947bool isUWRMSR(unsigned Opcode);
948bool isLGS(unsigned Opcode);
949bool isVMOVNTPD(unsigned Opcode);
950bool isRDPRU(unsigned Opcode);
951bool isVPUNPCKHBW(unsigned Opcode);
952bool isVUCOMXSD(unsigned Opcode);
953bool isANDN(unsigned Opcode);
954bool isVCVTTPH2UW(unsigned Opcode);
955bool isVMFUNC(unsigned Opcode);
956bool isFIMUL(unsigned Opcode);
957bool isBLCFILL(unsigned Opcode);
958bool isVGATHERPF0DPS(unsigned Opcode);
959bool isVFMSUBADD231PS(unsigned Opcode);
960bool isVREDUCESD(unsigned Opcode);
961bool isVCOMXSH(unsigned Opcode);
962bool isVXORPS(unsigned Opcode);
963bool isPSWAPD(unsigned Opcode);
964bool isPMAXSD(unsigned Opcode);
965bool isVCMPSS(unsigned Opcode);
966bool isEXTRACTPS(unsigned Opcode);
967bool isVPMOVZXBD(unsigned Opcode);
968bool isOUTSW(unsigned Opcode);
969bool isKORTESTB(unsigned Opcode);
970bool isVREDUCEPS(unsigned Opcode);
971bool isPEXTRW(unsigned Opcode);
972bool isFNINIT(unsigned Opcode);
973bool isVCVTPH2IBS(unsigned Opcode);
974bool isROL(unsigned Opcode);
975bool isVCVTPS2QQ(unsigned Opcode);
976bool isVGETMANTPH(unsigned Opcode);
977bool isPUNPCKLDQ(unsigned Opcode);
978bool isPADDD(unsigned Opcode);
979bool isVPSLLD(unsigned Opcode);
980bool isPFCMPGE(unsigned Opcode);
981bool isVGETMANTBF16(unsigned Opcode);
982bool isVSUBBF16(unsigned Opcode);
983bool isVPMOVM2D(unsigned Opcode);
984bool isVCVTTSS2USIS(unsigned Opcode);
985bool isVHSUBPS(unsigned Opcode);
986bool isENDBR32(unsigned Opcode);
987bool isMOVSXD(unsigned Opcode);
988bool isPSIGND(unsigned Opcode);
989bool isVPTEST(unsigned Opcode);
990bool isVPDPWUSD(unsigned Opcode);
991bool isHSUBPD(unsigned Opcode);
992bool isADCX(unsigned Opcode);
993bool isCVTTPD2PI(unsigned Opcode);
994bool isPDEP(unsigned Opcode);
995bool isTDPBUSD(unsigned Opcode);
996bool isVCVTBIASPH2HF8S(unsigned Opcode);
997bool isVBROADCASTI32X4(unsigned Opcode);
998bool isVCVTPH2UDQ(unsigned Opcode);
999bool isVPHADDW(unsigned Opcode);
1000bool isFLDL2E(unsigned Opcode);
1001bool isCLZERO(unsigned Opcode);
1002bool isPBLENDW(unsigned Opcode);
1003bool isVCVTBF162IUBS(unsigned Opcode);
1004bool isVCVTSH2USI(unsigned Opcode);
1005bool isVANDPD(unsigned Opcode);
1006bool isBEXTR(unsigned Opcode);
1007bool isSTD(unsigned Opcode);
1008bool isVAESKEYGENASSIST(unsigned Opcode);
1009bool isCMPSD(unsigned Opcode);
1010bool isMOVSS(unsigned Opcode);
1011bool isVCVTUQQ2PD(unsigned Opcode);
1012bool isVEXTRACTI32X4(unsigned Opcode);
1013bool isFLDCW(unsigned Opcode);
1014bool isINSW(unsigned Opcode);
1015bool isRDPID(unsigned Opcode);
1016bool isVUCOMXSS(unsigned Opcode);
1017bool isKANDQ(unsigned Opcode);
1018bool isV4FMADDPS(unsigned Opcode);
1019bool isPMOVZXWQ(unsigned Opcode);
1020bool isVFPCLASSSD(unsigned Opcode);
1021bool isBLENDPS(unsigned Opcode);
1022bool isVPACKSSDW(unsigned Opcode);
1023bool isVPINSRW(unsigned Opcode);
1024bool isFXAM(unsigned Opcode);
1025bool isVMINMAXBF16(unsigned Opcode);
1026bool isVSHUFF64X2(unsigned Opcode);
1027bool isVPACKUSWB(unsigned Opcode);
1028bool isVRSQRT28SS(unsigned Opcode);
1029bool isGETSEC(unsigned Opcode);
1030bool isVEXTRACTF64X4(unsigned Opcode);
1031bool isVPHSUBBW(unsigned Opcode);
1032bool isBLSR(unsigned Opcode);
1033bool isFILD(unsigned Opcode);
1034bool isRETFQ(unsigned Opcode);
1035bool isVADDSS(unsigned Opcode);
1036bool isCOMISS(unsigned Opcode);
1037bool isCLI(unsigned Opcode);
1038bool isVERW(unsigned Opcode);
1039bool isBTC(unsigned Opcode);
1040bool isVPHADDUBQ(unsigned Opcode);
1041bool isVPORQ(unsigned Opcode);
1042bool isORPD(unsigned Opcode);
1043bool isVMOVSS(unsigned Opcode);
1044bool isVPSUBD(unsigned Opcode);
1045bool isVGATHERPF1QPD(unsigned Opcode);
1046bool isENCODEKEY256(unsigned Opcode);
1047bool isGF2P8AFFINEINVQB(unsigned Opcode);
1048bool isXRSTOR64(unsigned Opcode);
1049bool isKANDW(unsigned Opcode);
1050bool isLODSQ(unsigned Opcode);
1051bool isVMOVRSW(unsigned Opcode);
1052bool isVSUBSH(unsigned Opcode);
1053bool isLSS(unsigned Opcode);
1054bool isPMOVSXBQ(unsigned Opcode);
1055bool isVCVTTSD2SIS(unsigned Opcode);
1056bool isVCMPSH(unsigned Opcode);
1057bool isVFMADD132PS(unsigned Opcode);
1058bool isVPACKSSWB(unsigned Opcode);
1059bool isPCMPGTQ(unsigned Opcode);
1060bool isVFMADD132SH(unsigned Opcode);
1061bool isVCVTUQQ2PH(unsigned Opcode);
1062bool isVCVTQQ2PS(unsigned Opcode);
1063bool isVCVTTSS2USI(unsigned Opcode);
1064bool isVPMOVM2Q(unsigned Opcode);
1065bool isVMOVD(unsigned Opcode);
1066bool isVCVTTPS2QQS(unsigned Opcode);
1067bool isVSQRTBF16(unsigned Opcode);
1068bool isVFPCLASSPH(unsigned Opcode);
1069bool isVCVTSS2SH(unsigned Opcode);
1070bool isSCASB(unsigned Opcode);
1071bool isPSRLD(unsigned Opcode);
1072bool isVADDPH(unsigned Opcode);
1073bool isFSUB(unsigned Opcode);
1074bool isVCVTTPH2IBS(unsigned Opcode);
1075bool isVEXTRACTI64X2(unsigned Opcode);
1076bool isPMINUW(unsigned Opcode);
1077bool isPSUBSB(unsigned Opcode);
1078bool isVCVT2PS2PHX(unsigned Opcode);
1079bool isVPCMPEQD(unsigned Opcode);
1080bool isVPSCATTERQD(unsigned Opcode);
1081bool isVPSHLDD(unsigned Opcode);
1082bool isKXNORB(unsigned Opcode);
1083bool isLDDQU(unsigned Opcode);
1084bool isMASKMOVQ(unsigned Opcode);
1085bool isPABSW(unsigned Opcode);
1086bool isVPROLD(unsigned Opcode);
1087bool isVPCOMQ(unsigned Opcode);
1088bool isVSCATTERDPD(unsigned Opcode);
1089bool isFXRSTOR(unsigned Opcode);
1090bool isVPCMPUW(unsigned Opcode);
1091bool isWBINVD(unsigned Opcode);
1092bool isVCVTTPD2UDQ(unsigned Opcode);
1093bool isERETU(unsigned Opcode);
1094bool isPFRCPIT2(unsigned Opcode);
1095bool isVPERMT2W(unsigned Opcode);
1096bool isVEXTRACTF32X4(unsigned Opcode);
1097bool isVGATHERPF0DPD(unsigned Opcode);
1098bool isVBROADCASTF32X2(unsigned Opcode);
1099bool isVRCP14SD(unsigned Opcode);
1100bool isPABSD(unsigned Opcode);
1101bool isLAHF(unsigned Opcode);
1102bool isPINSRB(unsigned Opcode);
1103bool isSKINIT(unsigned Opcode);
1104bool isENTER(unsigned Opcode);
1105bool isVCVTSI2SS(unsigned Opcode);
1106bool isVFMADD231PD(unsigned Opcode);
1107bool isLOADIWKEY(unsigned Opcode);
1108bool isVMOVNTDQA(unsigned Opcode);
1109bool isVPERMT2PS(unsigned Opcode);
1110bool isPUSHF(unsigned Opcode);
1111bool isMPSADBW(unsigned Opcode);
1112bool isVMINMAXSH(unsigned Opcode);
1113bool isVRSQRT14SS(unsigned Opcode);
1114bool isVCVTDQ2PD(unsigned Opcode);
1115bool isVORPS(unsigned Opcode);
1116bool isVPEXPANDQ(unsigned Opcode);
1117bool isVPSHRDD(unsigned Opcode);
1118bool isTDPBSSD(unsigned Opcode);
1119bool isTESTUI(unsigned Opcode);
1120bool isVFMADDPD(unsigned Opcode);
1121bool isVPANDND(unsigned Opcode);
1122bool isVPMOVSDB(unsigned Opcode);
1123bool isVPBROADCASTB(unsigned Opcode);
1124bool isCVTPI2PD(unsigned Opcode);
1125bool isVPERMI2B(unsigned Opcode);
1126bool isVPMINSB(unsigned Opcode);
1127bool isLAR(unsigned Opcode);
1128bool isINVLPGB(unsigned Opcode);
1129bool isTLBSYNC(unsigned Opcode);
1130bool isFDIVP(unsigned Opcode);
1131bool isVPSRLW(unsigned Opcode);
1132bool isVRCP28SS(unsigned Opcode);
1133bool isVMOVHPS(unsigned Opcode);
1134bool isVPMACSSDD(unsigned Opcode);
1135bool isPEXT(unsigned Opcode);
1136bool isVMAXBF16(unsigned Opcode);
1137bool isVRSQRT14SD(unsigned Opcode);
1138bool isVPDPWSSD(unsigned Opcode);
1139bool isVFMSUB231SD(unsigned Opcode);
1140bool isVPMOVZXWQ(unsigned Opcode);
1141bool isVMOVDQA(unsigned Opcode);
1142bool isVFNMSUB213SD(unsigned Opcode);
1143bool isVMINPS(unsigned Opcode);
1144bool isVFMSUB231PS(unsigned Opcode);
1145bool isVPCOMPRESSB(unsigned Opcode);
1146bool isVPCMPEQQ(unsigned Opcode);
1147bool isVRCPSS(unsigned Opcode);
1148bool isVSCATTERPF1DPS(unsigned Opcode);
1149bool isVPHADDUBW(unsigned Opcode);
1150bool isXORPD(unsigned Opcode);
1151bool isVPSCATTERQQ(unsigned Opcode);
1152bool isVCVTW2PH(unsigned Opcode);
1153bool isVFMADDCPH(unsigned Opcode);
1154bool isVSUBPD(unsigned Opcode);
1155bool isVPACKUSDW(unsigned Opcode);
1156bool isVSCALEFSS(unsigned Opcode);
1157bool isAESIMC(unsigned Opcode);
1158bool isVRCP28PS(unsigned Opcode);
1159bool isAAND(unsigned Opcode);
1160bool isDAA(unsigned Opcode);
1161bool isVCVTPD2UDQ(unsigned Opcode);
1162bool isKTESTW(unsigned Opcode);
1163bool isVPADDQ(unsigned Opcode);
1164bool isPALIGNR(unsigned Opcode);
1165bool isPMAXUW(unsigned Opcode);
1166bool isVFMADDSD(unsigned Opcode);
1167bool isPFMAX(unsigned Opcode);
1168bool isVPOR(unsigned Opcode);
1169bool isVPSUBB(unsigned Opcode);
1170bool isVPAVGB(unsigned Opcode);
1171bool isINSB(unsigned Opcode);
1172bool isFYL2X(unsigned Opcode);
1173bool isVFNMSUB132PD(unsigned Opcode);
1174bool isVFNMSUBPS(unsigned Opcode);
1175bool isVFMADD231PS(unsigned Opcode);
1176bool isVCVTTSS2SI(unsigned Opcode);
1177bool isTCMMRLFP16PS(unsigned Opcode);
1178bool isFCOMPP(unsigned Opcode);
1179bool isMOVD(unsigned Opcode);
1180bool isMOVBE(unsigned Opcode);
1181bool isVP2INTERSECTD(unsigned Opcode);
1182bool isVPMULLQ(unsigned Opcode);
1183bool isVSCALEFPS(unsigned Opcode);
1184bool isVPMACSDQH(unsigned Opcode);
1185bool isVPTESTNMD(unsigned Opcode);
1186bool isFCOMP(unsigned Opcode);
1187bool isPREFETCHWT1(unsigned Opcode);
1188bool isVCMPSD(unsigned Opcode);
1189bool isSGDTD(unsigned Opcode);
1190bool isWRUSSD(unsigned Opcode);
1191bool isFSUBP(unsigned Opcode);
1192bool isVUNPCKLPS(unsigned Opcode);
1193bool isVFNMSUB213SS(unsigned Opcode);
1194bool isROUNDPD(unsigned Opcode);
1195bool isVPMAXSW(unsigned Opcode);
1196bool isVCVTTPH2DQ(unsigned Opcode);
1197bool isVPUNPCKLWD(unsigned Opcode);
1198bool isKSHIFTLD(unsigned Opcode);
1199bool isTCVTROWPS2BF16H(unsigned Opcode);
1200bool isVFMADD231SD(unsigned Opcode);
1201bool isADDPS(unsigned Opcode);
1202bool isVPSLLVD(unsigned Opcode);
1203bool isVFNMADD132SH(unsigned Opcode);
1204bool isVMOVNTPS(unsigned Opcode);
1205bool isVCVTPD2DQ(unsigned Opcode);
1206bool isVPXOR(unsigned Opcode);
1207bool isSTMXCSR(unsigned Opcode);
1208bool isVRCP14SS(unsigned Opcode);
1209bool isUD2(unsigned Opcode);
1210bool isVPOPCNTW(unsigned Opcode);
1211bool isVRSQRTSH(unsigned Opcode);
1212bool isVSCATTERPF0DPD(unsigned Opcode);
1213bool isVFMADDPS(unsigned Opcode);
1214bool isXSAVEC64(unsigned Opcode);
1215bool isVPMADDUBSW(unsigned Opcode);
1216bool isVPMOVZXDQ(unsigned Opcode);
1217bool isVRCP14PS(unsigned Opcode);
1218bool isVSQRTSH(unsigned Opcode);
1219bool isTCVTROWD2PS(unsigned Opcode);
1220bool isLOOP(unsigned Opcode);
1221bool isSTUI(unsigned Opcode);
1222bool isVCVTTPS2UDQ(unsigned Opcode);
1223bool isVCOMPRESSPS(unsigned Opcode);
1224bool isXABORT(unsigned Opcode);
1225bool isVCVTTBF162IUBS(unsigned Opcode);
1226bool isVPADDW(unsigned Opcode);
1227bool isVRNDSCALEPS(unsigned Opcode);
1228bool isVPSIGND(unsigned Opcode);
1229bool isVPHADDUWD(unsigned Opcode);
1230bool isVCVT2PH2HF8S(unsigned Opcode);
1231bool isVDBPSADBW(unsigned Opcode);
1232bool isPSLLW(unsigned Opcode);
1233bool isVPMOVQD(unsigned Opcode);
1234bool isVINSERTI64X4(unsigned Opcode);
1235bool isVPERMI2PS(unsigned Opcode);
1236bool isVMULPH(unsigned Opcode);
1237bool isVPCMPUQ(unsigned Opcode);
1238bool isVCVTUSI2SD(unsigned Opcode);
1239bool isKXNORW(unsigned Opcode);
1240bool isBLCIC(unsigned Opcode);
1241bool isVFNMADD213SD(unsigned Opcode);
1242bool isVPMACSWW(unsigned Opcode);
1243bool isVMOVLPS(unsigned Opcode);
1244bool isPCONFIG(unsigned Opcode);
1245bool isPANDN(unsigned Opcode);
1246bool isVGETEXPPD(unsigned Opcode);
1247bool isVPSRLVQ(unsigned Opcode);
1248bool isUD1(unsigned Opcode);
1249bool isPMAXSB(unsigned Opcode);
1250bool isVPROLQ(unsigned Opcode);
1251bool isVSCATTERPF1QPD(unsigned Opcode);
1252bool isVPSRLD(unsigned Opcode);
1253bool isINT3(unsigned Opcode);
1254bool isXRSTORS64(unsigned Opcode);
1255bool isCVTSD2SI(unsigned Opcode);
1256bool isVMAXSS(unsigned Opcode);
1257bool isVPMINUB(unsigned Opcode);
1258bool isKXNORQ(unsigned Opcode);
1259bool isFLD(unsigned Opcode);
1260bool isVSHUFI32X4(unsigned Opcode);
1261bool isSAHF(unsigned Opcode);
1262bool isPFRSQRT(unsigned Opcode);
1263bool isSHRD(unsigned Opcode);
1264bool isSYSEXIT(unsigned Opcode);
1265bool isXSAVE64(unsigned Opcode);
1266bool isVPMAXSD(unsigned Opcode);
1267bool isCVTTSD2SI(unsigned Opcode);
1268bool isVCVTTSS2SIS(unsigned Opcode);
1269bool isPMOVMSKB(unsigned Opcode);
1270bool isVRANGEPS(unsigned Opcode);
1271bool isVADDSUBPS(unsigned Opcode);
1272bool isVBROADCASTI128(unsigned Opcode);
1273bool isPADDUSB(unsigned Opcode);
1274bool isENCODEKEY128(unsigned Opcode);
1275bool isOR(unsigned Opcode);
1276bool isSTOSW(unsigned Opcode);
1277bool isVCVTTPD2UQQS(unsigned Opcode);
1278bool isPAVGW(unsigned Opcode);
1279bool isVCVTPD2PH(unsigned Opcode);
1280bool isSHLX(unsigned Opcode);
1281bool isVCVTSH2SD(unsigned Opcode);
1282bool isVFMADD231SS(unsigned Opcode);
1283bool isMOVNTSD(unsigned Opcode);
1284bool isFLDPI(unsigned Opcode);
1285bool isVCVTUSI2SS(unsigned Opcode);
1286bool isPMOVSXBD(unsigned Opcode);
1287bool isVPRORVQ(unsigned Opcode);
1288bool isVPERMT2D(unsigned Opcode);
1289bool isADDSS(unsigned Opcode);
1290bool isAADD(unsigned Opcode);
1291bool isVPSRLVW(unsigned Opcode);
1292bool isVRSQRTPH(unsigned Opcode);
1293bool isVLDDQU(unsigned Opcode);
1294bool isKMOVD(unsigned Opcode);
1295bool isENCLV(unsigned Opcode);
1296bool isENCLU(unsigned Opcode);
1297bool isPREFETCHT1(unsigned Opcode);
1298bool isRSQRTPS(unsigned Opcode);
1299bool isVCVTTSH2USI(unsigned Opcode);
1300bool isPADDB(unsigned Opcode);
1301bool isVMASKMOVDQU(unsigned Opcode);
1302bool isPUNPCKLBW(unsigned Opcode);
1303bool isMOV(unsigned Opcode);
1304bool isVCVTTPH2IUBS(unsigned Opcode);
1305bool isMUL(unsigned Opcode);
1306bool isRCL(unsigned Opcode);
1307bool isVRCPSH(unsigned Opcode);
1308bool isPFCMPEQ(unsigned Opcode);
1309bool isMONITOR(unsigned Opcode);
1310bool isFDIVR(unsigned Opcode);
1311bool isPMINSD(unsigned Opcode);
1312bool isPFRCP(unsigned Opcode);
1313bool isKTESTQ(unsigned Opcode);
1314bool isVCVTTPD2DQ(unsigned Opcode);
1315bool isVSHUFF32X4(unsigned Opcode);
1316bool isVPSLLVW(unsigned Opcode);
1317bool isTDPBSUD(unsigned Opcode);
1318bool isVPMINUQ(unsigned Opcode);
1319bool isFIADD(unsigned Opcode);
1320bool isFCMOVNU(unsigned Opcode);
1321bool isVHSUBPD(unsigned Opcode);
1322bool isKSHIFTRQ(unsigned Opcode);
1323bool isMOVUPS(unsigned Opcode);
1324bool isVMCALL(unsigned Opcode);
1325bool isXADD(unsigned Opcode);
1326bool isXRSTOR(unsigned Opcode);
1327bool isVGATHERPF1DPD(unsigned Opcode);
1328bool isRCR(unsigned Opcode);
1329bool isFNSTCW(unsigned Opcode);
1330bool isVPMOVSDW(unsigned Opcode);
1331bool isVFMSUB132SH(unsigned Opcode);
1332bool isVPCONFLICTQ(unsigned Opcode);
1333bool isSWAPGS(unsigned Opcode);
1334bool isVPMOVQ2M(unsigned Opcode);
1335bool isVPSRAVW(unsigned Opcode);
1336bool isMOVDQA(unsigned Opcode);
1337bool isDIVSD(unsigned Opcode);
1338bool isPCMPGTB(unsigned Opcode);
1339bool isSHA256MSG2(unsigned Opcode);
1340bool isKXORW(unsigned Opcode);
1341bool isLIDTW(unsigned Opcode);
1342bool isPMULHW(unsigned Opcode);
1343bool isVAESENCLAST(unsigned Opcode);
1344bool isVINSERTI32X8(unsigned Opcode);
1345bool isVRCPPS(unsigned Opcode);
1346bool isVRSQRTBF16(unsigned Opcode);
1347bool isVGATHERQPS(unsigned Opcode);
1348bool isCTESTCC(unsigned Opcode);
1349bool isPMADDWD(unsigned Opcode);
1350bool isUCOMISS(unsigned Opcode);
1351bool isXGETBV(unsigned Opcode);
1352bool isVCVTPD2QQ(unsigned Opcode);
1353bool isVGETEXPPS(unsigned Opcode);
1354bool isFISTP(unsigned Opcode);
1355bool isVINSERTF64X4(unsigned Opcode);
1356bool isVMOVDQU16(unsigned Opcode);
1357bool isVFMADD132PH(unsigned Opcode);
1358bool isVFMSUBADD213PS(unsigned Opcode);
1359bool isVMOVDQU32(unsigned Opcode);
1360bool isFUCOM(unsigned Opcode);
1361bool isVFNMADD213BF16(unsigned Opcode);
1362bool isHADDPS(unsigned Opcode);
1363bool isCMP(unsigned Opcode);
1364bool isCVTTPS2PI(unsigned Opcode);
1365bool isIRETQ(unsigned Opcode);
1366bool isPF2IW(unsigned Opcode);
1367bool isPSHUFD(unsigned Opcode);
1368bool isVDPPD(unsigned Opcode);
1369bool isPSHUFHW(unsigned Opcode);
1370bool isRMPADJUST(unsigned Opcode);
1371bool isPI2FW(unsigned Opcode);
1372bool isVCVTTPH2QQ(unsigned Opcode);
1373bool isDIVPD(unsigned Opcode);
1374bool isCLFLUSH(unsigned Opcode);
1375bool isVPMINUW(unsigned Opcode);
1376bool isIN(unsigned Opcode);
1377bool isWRPKRU(unsigned Opcode);
1378bool isINSERTPS(unsigned Opcode);
1379bool isAAM(unsigned Opcode);
1380bool isVPHADDUDQ(unsigned Opcode);
1381bool isVSHA512MSG1(unsigned Opcode);
1382bool isDIVPS(unsigned Opcode);
1383bool isKNOTB(unsigned Opcode);
1384bool isBLSFILL(unsigned Opcode);
1385bool isVPCMPGTQ(unsigned Opcode);
1386bool isMINSD(unsigned Opcode);
1387bool isFPREM(unsigned Opcode);
1388bool isVPUNPCKHQDQ(unsigned Opcode);
1389bool isMINPD(unsigned Opcode);
1390bool isVCVTTPD2QQ(unsigned Opcode);
1391bool isVFMSUBPD(unsigned Opcode);
1392bool isV4FMADDSS(unsigned Opcode);
1393bool isCPUID(unsigned Opcode);
1394bool isSETCC(unsigned Opcode);
1395bool isVPDPWUUD(unsigned Opcode);
1396bool isVCVTTPS2IUBS(unsigned Opcode);
1397bool isPMOVSXDQ(unsigned Opcode);
1398bool isMWAIT(unsigned Opcode);
1399bool isVPEXTRB(unsigned Opcode);
1400bool isINVVPID(unsigned Opcode);
1401bool isVPSHUFD(unsigned Opcode);
1402bool isVMINBF16(unsigned Opcode);
1403bool isMOVLPS(unsigned Opcode);
1404bool isVBLENDMPS(unsigned Opcode);
1405bool isPMULLW(unsigned Opcode);
1406bool isVCVTSH2SI(unsigned Opcode);
1407bool isVPMOVSXWQ(unsigned Opcode);
1408bool isFNSTENV(unsigned Opcode);
1409bool isVCVT2PH2BF8(unsigned Opcode);
1410bool isVPERMI2PD(unsigned Opcode);
1411bool isMAXSS(unsigned Opcode);
1412bool isCWDE(unsigned Opcode);
1413bool isVBROADCASTI32X8(unsigned Opcode);
1414bool isINT(unsigned Opcode);
1415bool isENCLS(unsigned Opcode);
1416bool isMOVNTQ(unsigned Opcode);
1417bool isVDIVSH(unsigned Opcode);
1418bool isMOVHLPS(unsigned Opcode);
1419bool isVPMASKMOVD(unsigned Opcode);
1420bool isVMOVSD(unsigned Opcode);
1421bool isVPMINUD(unsigned Opcode);
1422bool isVPCMPISTRM(unsigned Opcode);
1423bool isVGETMANTSD(unsigned Opcode);
1424bool isKSHIFTRW(unsigned Opcode);
1425bool isAESDECLAST(unsigned Opcode);
1426bool isVFNMSUB231BF16(unsigned Opcode);
1427bool isVMPTRST(unsigned Opcode);
1428bool isLLDT(unsigned Opcode);
1429bool isVPTESTMB(unsigned Opcode);
1430bool isMOVSB(unsigned Opcode);
1431bool isTILELOADD(unsigned Opcode);
1432bool isKTESTB(unsigned Opcode);
1433bool isMOVUPD(unsigned Opcode);
1434bool isLKGS(unsigned Opcode);
1435bool isSGDTW(unsigned Opcode);
1436bool isDIVSS(unsigned Opcode);
1437bool isPUNPCKHQDQ(unsigned Opcode);
1438bool isVFMADD213SD(unsigned Opcode);
1439bool isKXORD(unsigned Opcode);
1440bool isVPMOVB2M(unsigned Opcode);
1441bool isVMREAD(unsigned Opcode);
1442bool isVPDPWSSDS(unsigned Opcode);
1443bool isTILERELEASE(unsigned Opcode);
1444bool isVUCOMXSH(unsigned Opcode);
1445bool isCLFLUSHOPT(unsigned Opcode);
1446bool isDAS(unsigned Opcode);
1447bool isVSCALEFPH(unsigned Opcode);
1448bool isVSUBSD(unsigned Opcode);
1449bool isVCOMISS(unsigned Opcode);
1450bool isVMULBF16(unsigned Opcode);
1451bool isORPS(unsigned Opcode);
1452bool isTDPFP16PS(unsigned Opcode);
1453bool isVMAXPD(unsigned Opcode);
1454bool isVPMOVWB(unsigned Opcode);
1455bool isVEXP2PS(unsigned Opcode);
1456bool isVPGATHERDQ(unsigned Opcode);
1457bool isVPSRAVQ(unsigned Opcode);
1458bool isPCMPISTRI(unsigned Opcode);
1459bool isVFMSUB231PD(unsigned Opcode);
1460bool isRDMSR(unsigned Opcode);
1461bool isKORTESTD(unsigned Opcode);
1462bool isVPBLENDMW(unsigned Opcode);
1463bool isPSHUFB(unsigned Opcode);
1464bool isVDPBF16PS(unsigned Opcode);
1465bool isTDPBF16PS(unsigned Opcode);
1466bool isFCMOVE(unsigned Opcode);
1467bool isVFMADD231BF16(unsigned Opcode);
1468bool isCMPSS(unsigned Opcode);
1469bool isMASKMOVDQU(unsigned Opcode);
1470bool isVPDPWUSDS(unsigned Opcode);
1471bool isSARX(unsigned Opcode);
1472bool isSGDT(unsigned Opcode);
1473bool isVFMULCPH(unsigned Opcode);
1474bool isURDMSR(unsigned Opcode);
1475bool isKUNPCKWD(unsigned Opcode);
1476bool isVSCALEFBF16(unsigned Opcode);
1477bool isCVTPS2PD(unsigned Opcode);
1478bool isFBSTP(unsigned Opcode);
1479bool isPSUBQ(unsigned Opcode);
1480bool isFXSAVE64(unsigned Opcode);
1481bool isKMOVW(unsigned Opcode);
1482bool isBTS(unsigned Opcode);
1483bool isVPHADDBQ(unsigned Opcode);
1484bool isFRSTOR(unsigned Opcode);
1485bool isVFMSUB132PD(unsigned Opcode);
1486bool isPMULLD(unsigned Opcode);
1487bool isSHA1MSG2(unsigned Opcode);
1488bool isJECXZ(unsigned Opcode);
1489bool isVCVTUDQ2PS(unsigned Opcode);
1490bool isAESENC(unsigned Opcode);
1491bool isVMINMAXPS(unsigned Opcode);
1492bool isPSIGNW(unsigned Opcode);
1493bool isUNPCKLPD(unsigned Opcode);
1494bool isPUSHP(unsigned Opcode);
1495bool isBLSI(unsigned Opcode);
1496bool isVPTESTNMB(unsigned Opcode);
1497bool isWRUSSQ(unsigned Opcode);
1498bool isVGF2P8MULB(unsigned Opcode);
1499bool isVPUNPCKLBW(unsigned Opcode);
1500bool isVRANGESD(unsigned Opcode);
1501bool isCLD(unsigned Opcode);
1502bool isVSCALEFPD(unsigned Opcode);
1503bool isVCOMXSS(unsigned Opcode);
1504bool isVPERMQ(unsigned Opcode);
1505bool isVPSHLDVW(unsigned Opcode);
1506bool isROR(unsigned Opcode);
1507bool isVFMADDSUB132PH(unsigned Opcode);
1508bool isDEC(unsigned Opcode);
1509bool isVGETEXPSH(unsigned Opcode);
1510bool isAESDEC(unsigned Opcode);
1511bool isKORD(unsigned Opcode);
1512bool isVPMULHW(unsigned Opcode);
1513bool isTILELOADDT1(unsigned Opcode);
1514bool isVMASKMOVPS(unsigned Opcode);
1515bool isPMOVZXDQ(unsigned Opcode);
1516bool isVCVTPS2PH(unsigned Opcode);
1517bool isCVTDQ2PD(unsigned Opcode);
1518bool isVCVTSD2SS(unsigned Opcode);
1519bool isVFMSUB213PH(unsigned Opcode);
1520bool isVPROTB(unsigned Opcode);
1521bool isPINSRD(unsigned Opcode);
1522bool isVMXON(unsigned Opcode);
1523bool isVFCMULCSH(unsigned Opcode);
1524bool isVFMULCSH(unsigned Opcode);
1525bool isVRANGEPD(unsigned Opcode);
1526bool isCMC(unsigned Opcode);
1527bool isVFNMADD231BF16(unsigned Opcode);
1528bool isSHA256MSG1(unsigned Opcode);
1529bool isFLD1(unsigned Opcode);
1530bool isCMPPS(unsigned Opcode);
1531bool isVPAVGW(unsigned Opcode);
1532bool isVFMADD213SH(unsigned Opcode);
1533bool isVPINSRQ(unsigned Opcode);
1534bool isMOVABS(unsigned Opcode);
1535bool isVPSHAQ(unsigned Opcode);
1536bool isRDTSCP(unsigned Opcode);
1537bool isVFNMADD231SS(unsigned Opcode);
1538bool isTEST(unsigned Opcode);
1539bool isVPERMD(unsigned Opcode);
1540bool isVBCSTNESH2PS(unsigned Opcode);
1541bool isVGATHERPF0QPD(unsigned Opcode);
1542bool isVPERM2I128(unsigned Opcode);
1543bool isVMPSADBW(unsigned Opcode);
1544bool isVFNMSUB231PD(unsigned Opcode);
1545bool isPADDSB(unsigned Opcode);
1546bool isMWAITX(unsigned Opcode);
1547bool isMONITORX(unsigned Opcode);
1548bool isVPEXPANDD(unsigned Opcode);
1549bool isVFRCZPD(unsigned Opcode);
1550bool isVRCPPH(unsigned Opcode);
1551bool isFEMMS(unsigned Opcode);
1552bool isVSCATTERQPD(unsigned Opcode);
1553bool isVMOVW(unsigned Opcode);
1554bool isVPBROADCASTD(unsigned Opcode);
1555bool isSTOSB(unsigned Opcode);
1556bool isFUCOMI(unsigned Opcode);
1557bool isVBROADCASTI64X4(unsigned Opcode);
1558bool isFCMOVU(unsigned Opcode);
1559bool isPSHUFLW(unsigned Opcode);
1560bool isCVTPI2PS(unsigned Opcode);
1561bool isVCVTTPD2UDQS(unsigned Opcode);
1562bool isSYSCALL(unsigned Opcode);
1563bool isVFMADD231SH(unsigned Opcode);
1564bool isPMOVZXBW(unsigned Opcode);
1565bool isVPOPCNTB(unsigned Opcode);
1566bool isVCVTDQ2PS(unsigned Opcode);
1567bool isPSUBD(unsigned Opcode);
1568bool isVPCMPEQW(unsigned Opcode);
1569bool isMOVSW(unsigned Opcode);
1570bool isVSM3RNDS2(unsigned Opcode);
1571bool isVPMOVUSQD(unsigned Opcode);
1572bool isCVTTPD2DQ(unsigned Opcode);
1573bool isVPEXPANDW(unsigned Opcode);
1574bool isVUCOMISH(unsigned Opcode);
1575bool isVZEROALL(unsigned Opcode);
1576bool isVPAND(unsigned Opcode);
1577bool isPMULDQ(unsigned Opcode);
1578bool isVPSHUFHW(unsigned Opcode);
1579bool isVPALIGNR(unsigned Opcode);
1580bool isSQRTSD(unsigned Opcode);
1581bool isVCVTTPH2UDQ(unsigned Opcode);
1582bool isVGETEXPPH(unsigned Opcode);
1583bool isADDPD(unsigned Opcode);
1584bool isVFNMADDPD(unsigned Opcode);
1585bool isSTTILECFG(unsigned Opcode);
1586bool isVMINPD(unsigned Opcode);
1587bool isSHA1RNDS4(unsigned Opcode);
1588bool isPBLENDVB(unsigned Opcode);
1589bool isVBROADCASTF128(unsigned Opcode);
1590bool isVPSHRDQ(unsigned Opcode);
1591bool isVAESIMC(unsigned Opcode);
1592bool isCOMISD(unsigned Opcode);
1593bool isVMOVSH(unsigned Opcode);
1594bool isPFSUBR(unsigned Opcode);
1595bool isRDSSPD(unsigned Opcode);
1596bool isWAIT(unsigned Opcode);
1597bool isVFPCLASSSS(unsigned Opcode);
1598bool isPCMPGTD(unsigned Opcode);
1599bool isVGATHERPF0QPS(unsigned Opcode);
1600bool isBLENDVPS(unsigned Opcode);
1601bool isVBROADCASTF32X4(unsigned Opcode);
1602bool isVPMADD52LUQ(unsigned Opcode);
1603bool isVMOVLPD(unsigned Opcode);
1604bool isVMOVQ(unsigned Opcode);
1605bool isVMOVDQU(unsigned Opcode);
1606bool isAESENC128KL(unsigned Opcode);
1607bool isVFMADDSUB231PS(unsigned Opcode);
1608bool isVFNMSUB213PD(unsigned Opcode);
1609bool isVPCONFLICTD(unsigned Opcode);
1610bool isVFMADDSUB213PH(unsigned Opcode);
1611bool isVPHSUBSW(unsigned Opcode);
1612bool isPUNPCKHDQ(unsigned Opcode);
1613bool isVSHUFI64X2(unsigned Opcode);
1614bool isVFMSUBSD(unsigned Opcode);
1615bool isVPORD(unsigned Opcode);
1616bool isRCPPS(unsigned Opcode);
1617bool isVEXTRACTI128(unsigned Opcode);
1618bool isVCVT2PH2BF8S(unsigned Opcode);
1619bool isVPSHRDVW(unsigned Opcode);
1620bool isVUNPCKLPD(unsigned Opcode);
1621bool isVPSRAVD(unsigned Opcode);
1622bool isVMULSH(unsigned Opcode);
1623bool isMOVNTSS(unsigned Opcode);
1624bool isSTI(unsigned Opcode);
1625bool isVSM4RNDS4(unsigned Opcode);
1626bool isVMCLEAR(unsigned Opcode);
1627bool isVPMADD52HUQ(unsigned Opcode);
1628bool isLIDT(unsigned Opcode);
1629bool isPUSH2(unsigned Opcode);
1630bool isVCVTPS2IUBS(unsigned Opcode);
1631bool isRDPKRU(unsigned Opcode);
1632bool isVPCMPB(unsigned Opcode);
1633bool isVFMSUB231BF16(unsigned Opcode);
1634bool isFINCSTP(unsigned Opcode);
1635bool isKORQ(unsigned Opcode);
1636bool isXCRYPTCBC(unsigned Opcode);
1637bool isRDPMC(unsigned Opcode);
1638bool isMOVMSKPD(unsigned Opcode);
1639bool isVFMSUB231SH(unsigned Opcode);
1640bool isVEXTRACTF128(unsigned Opcode);
1641bool isVPSHLB(unsigned Opcode);
1642bool isXSAVES64(unsigned Opcode);
1643bool isSHL(unsigned Opcode);
1644bool isAXOR(unsigned Opcode);
1645bool isVINSERTI64X2(unsigned Opcode);
1646bool isSYSRETQ(unsigned Opcode);
1647bool isVSCATTERPF0QPD(unsigned Opcode);
1648bool isVFMSUB213SH(unsigned Opcode);
1649bool isVPMOVQW(unsigned Opcode);
1650bool isVREDUCEPD(unsigned Opcode);
1651bool isNOT(unsigned Opcode);
1652bool isLWPINS(unsigned Opcode);
1653bool isVSCATTERDPS(unsigned Opcode);
1654bool isVPMOVM2W(unsigned Opcode);
1655bool isVFNMADD132PS(unsigned Opcode);
1656bool isMOVNTPS(unsigned Opcode);
1657bool isVRSQRTSS(unsigned Opcode);
1658bool isKMOVB(unsigned Opcode);
1659bool isCVTSD2SS(unsigned Opcode);
1660bool isVBROADCASTF64X2(unsigned Opcode);
1661bool isMOVNTPD(unsigned Opcode);
1662bool isMAXSD(unsigned Opcode);
1663bool isCMPPD(unsigned Opcode);
1664bool isVPCMPESTRM(unsigned Opcode);
1665bool isVFMSUB132PS(unsigned Opcode);
1666bool isVCOMISH(unsigned Opcode);
1667bool isF2XM1(unsigned Opcode);
1668bool isVDIVBF16(unsigned Opcode);
1669bool isSQRTPD(unsigned Opcode);
1670bool isVFMSUBADDPS(unsigned Opcode);
1671bool isFXTRACT(unsigned Opcode);
1672bool isVP4DPWSSD(unsigned Opcode);
1673bool isTDPBHF8PS(unsigned Opcode);
1674bool isVFMSUBADDPD(unsigned Opcode);
1675bool isVBCSTNEBF162PS(unsigned Opcode);
1676bool isVPGATHERQQ(unsigned Opcode);
1677bool isPCMPEQB(unsigned Opcode);
1678bool isTILESTORED(unsigned Opcode);
1679bool isBLSMSK(unsigned Opcode);
1680bool isVCVTTPS2DQ(unsigned Opcode);
1681bool isVRNDSCALEPD(unsigned Opcode);
1682bool isVFPCLASSBF16(unsigned Opcode);
1683bool isVMLOAD(unsigned Opcode);
1684bool isVPTERNLOGQ(unsigned Opcode);
1685bool isKXNORD(unsigned Opcode);
1686bool isFXSAVE(unsigned Opcode);
1687bool isVUNPCKHPD(unsigned Opcode);
1688bool isCVTPS2DQ(unsigned Opcode);
1689bool isTMMULTF32PS(unsigned Opcode);
1690bool isVFMSUB213SS(unsigned Opcode);
1691bool isVPOPCNTD(unsigned Opcode);
1692bool isSALC(unsigned Opcode);
1693bool isV4FNMADDSS(unsigned Opcode);
1694bool isXCRYPTOFB(unsigned Opcode);
1695bool isVORPD(unsigned Opcode);
1696bool isLSL(unsigned Opcode);
1697bool isXCRYPTCFB(unsigned Opcode);
1698bool isVGETEXPSS(unsigned Opcode);
1699bool isPSLLDQ(unsigned Opcode);
1700bool isVPDPBUUD(unsigned Opcode);
1701bool isVMXOFF(unsigned Opcode);
1702bool isBLSIC(unsigned Opcode);
1703bool isMOVLHPS(unsigned Opcode);
1704bool isVMOVRSQ(unsigned Opcode);
1705bool isVFNMSUBSD(unsigned Opcode);
1706bool isVCVTPH2IUBS(unsigned Opcode);
1707bool isVFPCLASSSH(unsigned Opcode);
1708bool isVPSHLQ(unsigned Opcode);
1709bool isVROUNDPS(unsigned Opcode);
1710bool isVSCATTERPF0QPS(unsigned Opcode);
1711bool isERETS(unsigned Opcode);
1712bool isVPERMI2D(unsigned Opcode);
1713bool isFUCOMP(unsigned Opcode);
1714bool isVCVTTPS2QQ(unsigned Opcode);
1715bool isPUSHFD(unsigned Opcode);
1716bool isKORB(unsigned Opcode);
1717bool isVRCP28PD(unsigned Opcode);
1718bool isVPABSD(unsigned Opcode);
1719bool isVROUNDSS(unsigned Opcode);
1720bool isVCVTSD2USI(unsigned Opcode);
1721bool isVPABSB(unsigned Opcode);
1722bool isPMAXUD(unsigned Opcode);
1723bool isVPMULHUW(unsigned Opcode);
1724bool isVPERMPD(unsigned Opcode);
1725bool isFCHS(unsigned Opcode);
1726bool isVPBLENDMB(unsigned Opcode);
1727bool isVGETMANTSS(unsigned Opcode);
1728bool isVPSLLW(unsigned Opcode);
1729bool isVDIVPD(unsigned Opcode);
1730bool isBLCMSK(unsigned Opcode);
1731bool isFDIV(unsigned Opcode);
1732bool isRSQRTSS(unsigned Opcode);
1733bool isPOR(unsigned Opcode);
1734bool isVMOVDQA32(unsigned Opcode);
1735bool isVPHADDUWQ(unsigned Opcode);
1736bool isPSRAD(unsigned Opcode);
1737bool isPREFETCHW(unsigned Opcode);
1738bool isFIDIVR(unsigned Opcode);
1739bool isMOVHPS(unsigned Opcode);
1740bool isVFNMSUB231PH(unsigned Opcode);
1741bool isUNPCKLPS(unsigned Opcode);
1742bool isVPSIGNB(unsigned Opcode);
1743bool isSAVEPREVSSP(unsigned Opcode);
1744bool isVSCALEFSD(unsigned Opcode);
1745bool isFSIN(unsigned Opcode);
1746bool isSCASQ(unsigned Opcode);
1747bool isVCVTTPD2QQS(unsigned Opcode);
1748bool isPCMPGTW(unsigned Opcode);
1749bool isMULX(unsigned Opcode);
1750bool isVPMAXUW(unsigned Opcode);
1751bool isPAUSE(unsigned Opcode);
1752bool isMOVQ2DQ(unsigned Opcode);
1753bool isVPSUBQ(unsigned Opcode);
1754bool isVPABSW(unsigned Opcode);
1755bool isVPCOMPRESSD(unsigned Opcode);
1756bool isVPMOVUSQW(unsigned Opcode);
1757bool isBLENDVPD(unsigned Opcode);
1758bool isVFNMADD132BF16(unsigned Opcode);
1759bool isVPMOVQB(unsigned Opcode);
1760bool isVBLENDVPS(unsigned Opcode);
1761bool isKSHIFTLQ(unsigned Opcode);
1762bool isPMOVSXWD(unsigned Opcode);
1763bool isPHSUBSW(unsigned Opcode);
1764bool isPSRLQ(unsigned Opcode);
1765bool isVCVTPH2DQ(unsigned Opcode);
1766bool isFISUB(unsigned Opcode);
1767bool isVCVTPS2UDQ(unsigned Opcode);
1768bool isVMOVDDUP(unsigned Opcode);
1769bool isPCMPEQD(unsigned Opcode);
1770bool isVRSQRT28SD(unsigned Opcode);
1771bool isTDPHBF8PS(unsigned Opcode);
1772bool isLODSW(unsigned Opcode);
1773bool isVPOPCNTQ(unsigned Opcode);
1774bool isKSHIFTRB(unsigned Opcode);
1775bool isVFNMADDPS(unsigned Opcode);
1776bool isCCMPCC(unsigned Opcode);
1777bool isFXRSTOR64(unsigned Opcode);
1778bool isVFMSUBADD213PD(unsigned Opcode);
1779bool isVSQRTPH(unsigned Opcode);
1780bool isPOPF(unsigned Opcode);
1781bool isVPSUBUSB(unsigned Opcode);
1782bool isTCVTROWPS2BF16L(unsigned Opcode);
1783bool isPREFETCHIT1(unsigned Opcode);
1784bool isVPADDSW(unsigned Opcode);
1785bool isVADDSUBPD(unsigned Opcode);
1786bool isKANDD(unsigned Opcode);
1787bool isOUTSB(unsigned Opcode);
1788bool isPREFETCHRST2(unsigned Opcode);
1789bool isFNSTSW(unsigned Opcode);
1790bool isPMINSB(unsigned Opcode);
1791#endif // GET_X86_MNEMONIC_TABLES_H
1792
1793#ifdef GET_X86_MNEMONIC_TABLES_CPP
1794#undef GET_X86_MNEMONIC_TABLES_CPP
1795
1796bool isFSUBRP(unsigned Opcode) {
1797 return Opcode == SUBR_FPrST0;
1798}
1799
1800bool isVPDPBUSDS(unsigned Opcode) {
1801 switch (Opcode) {
1802 case VPDPBUSDSYrm:
1803 case VPDPBUSDSYrr:
1804 case VPDPBUSDSZ128rm:
1805 case VPDPBUSDSZ128rmb:
1806 case VPDPBUSDSZ128rmbk:
1807 case VPDPBUSDSZ128rmbkz:
1808 case VPDPBUSDSZ128rmk:
1809 case VPDPBUSDSZ128rmkz:
1810 case VPDPBUSDSZ128rr:
1811 case VPDPBUSDSZ128rrk:
1812 case VPDPBUSDSZ128rrkz:
1813 case VPDPBUSDSZ256rm:
1814 case VPDPBUSDSZ256rmb:
1815 case VPDPBUSDSZ256rmbk:
1816 case VPDPBUSDSZ256rmbkz:
1817 case VPDPBUSDSZ256rmk:
1818 case VPDPBUSDSZ256rmkz:
1819 case VPDPBUSDSZ256rr:
1820 case VPDPBUSDSZ256rrk:
1821 case VPDPBUSDSZ256rrkz:
1822 case VPDPBUSDSZrm:
1823 case VPDPBUSDSZrmb:
1824 case VPDPBUSDSZrmbk:
1825 case VPDPBUSDSZrmbkz:
1826 case VPDPBUSDSZrmk:
1827 case VPDPBUSDSZrmkz:
1828 case VPDPBUSDSZrr:
1829 case VPDPBUSDSZrrk:
1830 case VPDPBUSDSZrrkz:
1831 case VPDPBUSDSrm:
1832 case VPDPBUSDSrr:
1833 return true;
1834 }
1835 return false;
1836}
1837
1838bool isPUNPCKLWD(unsigned Opcode) {
1839 switch (Opcode) {
1840 case MMX_PUNPCKLWDrm:
1841 case MMX_PUNPCKLWDrr:
1842 case PUNPCKLWDrm:
1843 case PUNPCKLWDrr:
1844 return true;
1845 }
1846 return false;
1847}
1848
1849bool isVREDUCEBF16(unsigned Opcode) {
1850 switch (Opcode) {
1851 case VREDUCEBF16Z128rmbi:
1852 case VREDUCEBF16Z128rmbik:
1853 case VREDUCEBF16Z128rmbikz:
1854 case VREDUCEBF16Z128rmi:
1855 case VREDUCEBF16Z128rmik:
1856 case VREDUCEBF16Z128rmikz:
1857 case VREDUCEBF16Z128rri:
1858 case VREDUCEBF16Z128rrik:
1859 case VREDUCEBF16Z128rrikz:
1860 case VREDUCEBF16Z256rmbi:
1861 case VREDUCEBF16Z256rmbik:
1862 case VREDUCEBF16Z256rmbikz:
1863 case VREDUCEBF16Z256rmi:
1864 case VREDUCEBF16Z256rmik:
1865 case VREDUCEBF16Z256rmikz:
1866 case VREDUCEBF16Z256rri:
1867 case VREDUCEBF16Z256rrik:
1868 case VREDUCEBF16Z256rrikz:
1869 case VREDUCEBF16Zrmbi:
1870 case VREDUCEBF16Zrmbik:
1871 case VREDUCEBF16Zrmbikz:
1872 case VREDUCEBF16Zrmi:
1873 case VREDUCEBF16Zrmik:
1874 case VREDUCEBF16Zrmikz:
1875 case VREDUCEBF16Zrri:
1876 case VREDUCEBF16Zrrik:
1877 case VREDUCEBF16Zrrikz:
1878 return true;
1879 }
1880 return false;
1881}
1882
1883bool isPUNPCKLQDQ(unsigned Opcode) {
1884 switch (Opcode) {
1885 case PUNPCKLQDQrm:
1886 case PUNPCKLQDQrr:
1887 return true;
1888 }
1889 return false;
1890}
1891
1892bool isRDFSBASE(unsigned Opcode) {
1893 switch (Opcode) {
1894 case RDFSBASE:
1895 case RDFSBASE64:
1896 return true;
1897 }
1898 return false;
1899}
1900
1901bool isVPCMOV(unsigned Opcode) {
1902 switch (Opcode) {
1903 case VPCMOVYrmr:
1904 case VPCMOVYrrm:
1905 case VPCMOVYrrr:
1906 case VPCMOVYrrr_REV:
1907 case VPCMOVrmr:
1908 case VPCMOVrrm:
1909 case VPCMOVrrr:
1910 case VPCMOVrrr_REV:
1911 return true;
1912 }
1913 return false;
1914}
1915
1916bool isVDIVSD(unsigned Opcode) {
1917 switch (Opcode) {
1918 case VDIVSDZrm_Int:
1919 case VDIVSDZrmk_Int:
1920 case VDIVSDZrmkz_Int:
1921 case VDIVSDZrr_Int:
1922 case VDIVSDZrrb_Int:
1923 case VDIVSDZrrbk_Int:
1924 case VDIVSDZrrbkz_Int:
1925 case VDIVSDZrrk_Int:
1926 case VDIVSDZrrkz_Int:
1927 case VDIVSDrm_Int:
1928 case VDIVSDrr_Int:
1929 return true;
1930 }
1931 return false;
1932}
1933
1934bool isVCVTTPS2IBS(unsigned Opcode) {
1935 switch (Opcode) {
1936 case VCVTTPS2IBSZ128rm:
1937 case VCVTTPS2IBSZ128rmb:
1938 case VCVTTPS2IBSZ128rmbk:
1939 case VCVTTPS2IBSZ128rmbkz:
1940 case VCVTTPS2IBSZ128rmk:
1941 case VCVTTPS2IBSZ128rmkz:
1942 case VCVTTPS2IBSZ128rr:
1943 case VCVTTPS2IBSZ128rrk:
1944 case VCVTTPS2IBSZ128rrkz:
1945 case VCVTTPS2IBSZ256rm:
1946 case VCVTTPS2IBSZ256rmb:
1947 case VCVTTPS2IBSZ256rmbk:
1948 case VCVTTPS2IBSZ256rmbkz:
1949 case VCVTTPS2IBSZ256rmk:
1950 case VCVTTPS2IBSZ256rmkz:
1951 case VCVTTPS2IBSZ256rr:
1952 case VCVTTPS2IBSZ256rrk:
1953 case VCVTTPS2IBSZ256rrkz:
1954 case VCVTTPS2IBSZrm:
1955 case VCVTTPS2IBSZrmb:
1956 case VCVTTPS2IBSZrmbk:
1957 case VCVTTPS2IBSZrmbkz:
1958 case VCVTTPS2IBSZrmk:
1959 case VCVTTPS2IBSZrmkz:
1960 case VCVTTPS2IBSZrr:
1961 case VCVTTPS2IBSZrrb:
1962 case VCVTTPS2IBSZrrbk:
1963 case VCVTTPS2IBSZrrbkz:
1964 case VCVTTPS2IBSZrrk:
1965 case VCVTTPS2IBSZrrkz:
1966 return true;
1967 }
1968 return false;
1969}
1970
1971bool isVPEXTRW(unsigned Opcode) {
1972 switch (Opcode) {
1973 case VPEXTRWZmri:
1974 case VPEXTRWZrri:
1975 case VPEXTRWZrri_REV:
1976 case VPEXTRWmri:
1977 case VPEXTRWrri:
1978 case VPEXTRWrri_REV:
1979 return true;
1980 }
1981 return false;
1982}
1983
1984bool isLODSD(unsigned Opcode) {
1985 return Opcode == LODSL;
1986}
1987
1988bool isVPTESTNMQ(unsigned Opcode) {
1989 switch (Opcode) {
1990 case VPTESTNMQZ128rm:
1991 case VPTESTNMQZ128rmb:
1992 case VPTESTNMQZ128rmbk:
1993 case VPTESTNMQZ128rmk:
1994 case VPTESTNMQZ128rr:
1995 case VPTESTNMQZ128rrk:
1996 case VPTESTNMQZ256rm:
1997 case VPTESTNMQZ256rmb:
1998 case VPTESTNMQZ256rmbk:
1999 case VPTESTNMQZ256rmk:
2000 case VPTESTNMQZ256rr:
2001 case VPTESTNMQZ256rrk:
2002 case VPTESTNMQZrm:
2003 case VPTESTNMQZrmb:
2004 case VPTESTNMQZrmbk:
2005 case VPTESTNMQZrmk:
2006 case VPTESTNMQZrr:
2007 case VPTESTNMQZrrk:
2008 return true;
2009 }
2010 return false;
2011}
2012
2013bool isCVTSS2SD(unsigned Opcode) {
2014 switch (Opcode) {
2015 case CVTSS2SDrm_Int:
2016 case CVTSS2SDrr_Int:
2017 return true;
2018 }
2019 return false;
2020}
2021
2022bool isVGETMANTPD(unsigned Opcode) {
2023 switch (Opcode) {
2024 case VGETMANTPDZ128rmbi:
2025 case VGETMANTPDZ128rmbik:
2026 case VGETMANTPDZ128rmbikz:
2027 case VGETMANTPDZ128rmi:
2028 case VGETMANTPDZ128rmik:
2029 case VGETMANTPDZ128rmikz:
2030 case VGETMANTPDZ128rri:
2031 case VGETMANTPDZ128rrik:
2032 case VGETMANTPDZ128rrikz:
2033 case VGETMANTPDZ256rmbi:
2034 case VGETMANTPDZ256rmbik:
2035 case VGETMANTPDZ256rmbikz:
2036 case VGETMANTPDZ256rmi:
2037 case VGETMANTPDZ256rmik:
2038 case VGETMANTPDZ256rmikz:
2039 case VGETMANTPDZ256rri:
2040 case VGETMANTPDZ256rrik:
2041 case VGETMANTPDZ256rrikz:
2042 case VGETMANTPDZrmbi:
2043 case VGETMANTPDZrmbik:
2044 case VGETMANTPDZrmbikz:
2045 case VGETMANTPDZrmi:
2046 case VGETMANTPDZrmik:
2047 case VGETMANTPDZrmikz:
2048 case VGETMANTPDZrri:
2049 case VGETMANTPDZrrib:
2050 case VGETMANTPDZrribk:
2051 case VGETMANTPDZrribkz:
2052 case VGETMANTPDZrrik:
2053 case VGETMANTPDZrrikz:
2054 return true;
2055 }
2056 return false;
2057}
2058
2059bool isVMOVDQA64(unsigned Opcode) {
2060 switch (Opcode) {
2061 case VMOVDQA64Z128mr:
2062 case VMOVDQA64Z128mrk:
2063 case VMOVDQA64Z128rm:
2064 case VMOVDQA64Z128rmk:
2065 case VMOVDQA64Z128rmkz:
2066 case VMOVDQA64Z128rr:
2067 case VMOVDQA64Z128rr_REV:
2068 case VMOVDQA64Z128rrk:
2069 case VMOVDQA64Z128rrk_REV:
2070 case VMOVDQA64Z128rrkz:
2071 case VMOVDQA64Z128rrkz_REV:
2072 case VMOVDQA64Z256mr:
2073 case VMOVDQA64Z256mrk:
2074 case VMOVDQA64Z256rm:
2075 case VMOVDQA64Z256rmk:
2076 case VMOVDQA64Z256rmkz:
2077 case VMOVDQA64Z256rr:
2078 case VMOVDQA64Z256rr_REV:
2079 case VMOVDQA64Z256rrk:
2080 case VMOVDQA64Z256rrk_REV:
2081 case VMOVDQA64Z256rrkz:
2082 case VMOVDQA64Z256rrkz_REV:
2083 case VMOVDQA64Zmr:
2084 case VMOVDQA64Zmrk:
2085 case VMOVDQA64Zrm:
2086 case VMOVDQA64Zrmk:
2087 case VMOVDQA64Zrmkz:
2088 case VMOVDQA64Zrr:
2089 case VMOVDQA64Zrr_REV:
2090 case VMOVDQA64Zrrk:
2091 case VMOVDQA64Zrrk_REV:
2092 case VMOVDQA64Zrrkz:
2093 case VMOVDQA64Zrrkz_REV:
2094 return true;
2095 }
2096 return false;
2097}
2098
2099bool isINVLPG(unsigned Opcode) {
2100 return Opcode == INVLPG;
2101}
2102
2103bool isVGETEXPBF16(unsigned Opcode) {
2104 switch (Opcode) {
2105 case VGETEXPBF16Z128m:
2106 case VGETEXPBF16Z128mb:
2107 case VGETEXPBF16Z128mbk:
2108 case VGETEXPBF16Z128mbkz:
2109 case VGETEXPBF16Z128mk:
2110 case VGETEXPBF16Z128mkz:
2111 case VGETEXPBF16Z128r:
2112 case VGETEXPBF16Z128rk:
2113 case VGETEXPBF16Z128rkz:
2114 case VGETEXPBF16Z256m:
2115 case VGETEXPBF16Z256mb:
2116 case VGETEXPBF16Z256mbk:
2117 case VGETEXPBF16Z256mbkz:
2118 case VGETEXPBF16Z256mk:
2119 case VGETEXPBF16Z256mkz:
2120 case VGETEXPBF16Z256r:
2121 case VGETEXPBF16Z256rk:
2122 case VGETEXPBF16Z256rkz:
2123 case VGETEXPBF16Zm:
2124 case VGETEXPBF16Zmb:
2125 case VGETEXPBF16Zmbk:
2126 case VGETEXPBF16Zmbkz:
2127 case VGETEXPBF16Zmk:
2128 case VGETEXPBF16Zmkz:
2129 case VGETEXPBF16Zr:
2130 case VGETEXPBF16Zrk:
2131 case VGETEXPBF16Zrkz:
2132 return true;
2133 }
2134 return false;
2135}
2136
2137bool isVBROADCASTF64X4(unsigned Opcode) {
2138 switch (Opcode) {
2139 case VBROADCASTF64X4Zrm:
2140 case VBROADCASTF64X4Zrmk:
2141 case VBROADCASTF64X4Zrmkz:
2142 return true;
2143 }
2144 return false;
2145}
2146
2147bool isVPERMI2Q(unsigned Opcode) {
2148 switch (Opcode) {
2149 case VPERMI2QZ128rm:
2150 case VPERMI2QZ128rmb:
2151 case VPERMI2QZ128rmbk:
2152 case VPERMI2QZ128rmbkz:
2153 case VPERMI2QZ128rmk:
2154 case VPERMI2QZ128rmkz:
2155 case VPERMI2QZ128rr:
2156 case VPERMI2QZ128rrk:
2157 case VPERMI2QZ128rrkz:
2158 case VPERMI2QZ256rm:
2159 case VPERMI2QZ256rmb:
2160 case VPERMI2QZ256rmbk:
2161 case VPERMI2QZ256rmbkz:
2162 case VPERMI2QZ256rmk:
2163 case VPERMI2QZ256rmkz:
2164 case VPERMI2QZ256rr:
2165 case VPERMI2QZ256rrk:
2166 case VPERMI2QZ256rrkz:
2167 case VPERMI2QZrm:
2168 case VPERMI2QZrmb:
2169 case VPERMI2QZrmbk:
2170 case VPERMI2QZrmbkz:
2171 case VPERMI2QZrmk:
2172 case VPERMI2QZrmkz:
2173 case VPERMI2QZrr:
2174 case VPERMI2QZrrk:
2175 case VPERMI2QZrrkz:
2176 return true;
2177 }
2178 return false;
2179}
2180
2181bool isVPMOVSXBD(unsigned Opcode) {
2182 switch (Opcode) {
2183 case VPMOVSXBDYrm:
2184 case VPMOVSXBDYrr:
2185 case VPMOVSXBDZ128rm:
2186 case VPMOVSXBDZ128rmk:
2187 case VPMOVSXBDZ128rmkz:
2188 case VPMOVSXBDZ128rr:
2189 case VPMOVSXBDZ128rrk:
2190 case VPMOVSXBDZ128rrkz:
2191 case VPMOVSXBDZ256rm:
2192 case VPMOVSXBDZ256rmk:
2193 case VPMOVSXBDZ256rmkz:
2194 case VPMOVSXBDZ256rr:
2195 case VPMOVSXBDZ256rrk:
2196 case VPMOVSXBDZ256rrkz:
2197 case VPMOVSXBDZrm:
2198 case VPMOVSXBDZrmk:
2199 case VPMOVSXBDZrmkz:
2200 case VPMOVSXBDZrr:
2201 case VPMOVSXBDZrrk:
2202 case VPMOVSXBDZrrkz:
2203 case VPMOVSXBDrm:
2204 case VPMOVSXBDrr:
2205 return true;
2206 }
2207 return false;
2208}
2209
2210bool isVFMSUB132SS(unsigned Opcode) {
2211 switch (Opcode) {
2212 case VFMSUB132SSZm_Int:
2213 case VFMSUB132SSZmk_Int:
2214 case VFMSUB132SSZmkz_Int:
2215 case VFMSUB132SSZr_Int:
2216 case VFMSUB132SSZrb_Int:
2217 case VFMSUB132SSZrbk_Int:
2218 case VFMSUB132SSZrbkz_Int:
2219 case VFMSUB132SSZrk_Int:
2220 case VFMSUB132SSZrkz_Int:
2221 case VFMSUB132SSm_Int:
2222 case VFMSUB132SSr_Int:
2223 return true;
2224 }
2225 return false;
2226}
2227
2228bool isVPMOVUSDW(unsigned Opcode) {
2229 switch (Opcode) {
2230 case VPMOVUSDWZ128mr:
2231 case VPMOVUSDWZ128mrk:
2232 case VPMOVUSDWZ128rr:
2233 case VPMOVUSDWZ128rrk:
2234 case VPMOVUSDWZ128rrkz:
2235 case VPMOVUSDWZ256mr:
2236 case VPMOVUSDWZ256mrk:
2237 case VPMOVUSDWZ256rr:
2238 case VPMOVUSDWZ256rrk:
2239 case VPMOVUSDWZ256rrkz:
2240 case VPMOVUSDWZmr:
2241 case VPMOVUSDWZmrk:
2242 case VPMOVUSDWZrr:
2243 case VPMOVUSDWZrrk:
2244 case VPMOVUSDWZrrkz:
2245 return true;
2246 }
2247 return false;
2248}
2249
2250bool isAAD(unsigned Opcode) {
2251 return Opcode == AAD8i8;
2252}
2253
2254bool isIDIV(unsigned Opcode) {
2255 switch (Opcode) {
2256 case IDIV16m:
2257 case IDIV16m_EVEX:
2258 case IDIV16m_NF:
2259 case IDIV16r:
2260 case IDIV16r_EVEX:
2261 case IDIV16r_NF:
2262 case IDIV32m:
2263 case IDIV32m_EVEX:
2264 case IDIV32m_NF:
2265 case IDIV32r:
2266 case IDIV32r_EVEX:
2267 case IDIV32r_NF:
2268 case IDIV64m:
2269 case IDIV64m_EVEX:
2270 case IDIV64m_NF:
2271 case IDIV64r:
2272 case IDIV64r_EVEX:
2273 case IDIV64r_NF:
2274 case IDIV8m:
2275 case IDIV8m_EVEX:
2276 case IDIV8m_NF:
2277 case IDIV8r:
2278 case IDIV8r_EVEX:
2279 case IDIV8r_NF:
2280 return true;
2281 }
2282 return false;
2283}
2284
2285bool isCVTTPS2DQ(unsigned Opcode) {
2286 switch (Opcode) {
2287 case CVTTPS2DQrm:
2288 case CVTTPS2DQrr:
2289 return true;
2290 }
2291 return false;
2292}
2293
2294bool isVBROADCASTF32X8(unsigned Opcode) {
2295 switch (Opcode) {
2296 case VBROADCASTF32X8Zrm:
2297 case VBROADCASTF32X8Zrmk:
2298 case VBROADCASTF32X8Zrmkz:
2299 return true;
2300 }
2301 return false;
2302}
2303
2304bool isVFMSUBSS(unsigned Opcode) {
2305 switch (Opcode) {
2306 case VFMSUBSS4mr:
2307 case VFMSUBSS4rm:
2308 case VFMSUBSS4rr:
2309 case VFMSUBSS4rr_REV:
2310 return true;
2311 }
2312 return false;
2313}
2314
2315bool isEMMS(unsigned Opcode) {
2316 return Opcode == MMX_EMMS;
2317}
2318
2319bool isVPDPBSUD(unsigned Opcode) {
2320 switch (Opcode) {
2321 case VPDPBSUDYrm:
2322 case VPDPBSUDYrr:
2323 case VPDPBSUDZ128rm:
2324 case VPDPBSUDZ128rmb:
2325 case VPDPBSUDZ128rmbk:
2326 case VPDPBSUDZ128rmbkz:
2327 case VPDPBSUDZ128rmk:
2328 case VPDPBSUDZ128rmkz:
2329 case VPDPBSUDZ128rr:
2330 case VPDPBSUDZ128rrk:
2331 case VPDPBSUDZ128rrkz:
2332 case VPDPBSUDZ256rm:
2333 case VPDPBSUDZ256rmb:
2334 case VPDPBSUDZ256rmbk:
2335 case VPDPBSUDZ256rmbkz:
2336 case VPDPBSUDZ256rmk:
2337 case VPDPBSUDZ256rmkz:
2338 case VPDPBSUDZ256rr:
2339 case VPDPBSUDZ256rrk:
2340 case VPDPBSUDZ256rrkz:
2341 case VPDPBSUDZrm:
2342 case VPDPBSUDZrmb:
2343 case VPDPBSUDZrmbk:
2344 case VPDPBSUDZrmbkz:
2345 case VPDPBSUDZrmk:
2346 case VPDPBSUDZrmkz:
2347 case VPDPBSUDZrr:
2348 case VPDPBSUDZrrk:
2349 case VPDPBSUDZrrkz:
2350 case VPDPBSUDrm:
2351 case VPDPBSUDrr:
2352 return true;
2353 }
2354 return false;
2355}
2356
2357bool isPMOVSXWQ(unsigned Opcode) {
2358 switch (Opcode) {
2359 case PMOVSXWQrm:
2360 case PMOVSXWQrr:
2361 return true;
2362 }
2363 return false;
2364}
2365
2366bool isPSRLW(unsigned Opcode) {
2367 switch (Opcode) {
2368 case MMX_PSRLWri:
2369 case MMX_PSRLWrm:
2370 case MMX_PSRLWrr:
2371 case PSRLWri:
2372 case PSRLWrm:
2373 case PSRLWrr:
2374 return true;
2375 }
2376 return false;
2377}
2378
2379bool isMOVNTDQA(unsigned Opcode) {
2380 return Opcode == MOVNTDQArm;
2381}
2382
2383bool isFUCOMPI(unsigned Opcode) {
2384 return Opcode == UCOM_FIPr;
2385}
2386
2387bool isANDNPS(unsigned Opcode) {
2388 switch (Opcode) {
2389 case ANDNPSrm:
2390 case ANDNPSrr:
2391 return true;
2392 }
2393 return false;
2394}
2395
2396bool isVINSERTF64X2(unsigned Opcode) {
2397 switch (Opcode) {
2398 case VINSERTF64X2Z256rmi:
2399 case VINSERTF64X2Z256rmik:
2400 case VINSERTF64X2Z256rmikz:
2401 case VINSERTF64X2Z256rri:
2402 case VINSERTF64X2Z256rrik:
2403 case VINSERTF64X2Z256rrikz:
2404 case VINSERTF64X2Zrmi:
2405 case VINSERTF64X2Zrmik:
2406 case VINSERTF64X2Zrmikz:
2407 case VINSERTF64X2Zrri:
2408 case VINSERTF64X2Zrrik:
2409 case VINSERTF64X2Zrrikz:
2410 return true;
2411 }
2412 return false;
2413}
2414
2415bool isCLTS(unsigned Opcode) {
2416 return Opcode == CLTS;
2417}
2418
2419bool isSETSSBSY(unsigned Opcode) {
2420 return Opcode == SETSSBSY;
2421}
2422
2423bool isVMULPD(unsigned Opcode) {
2424 switch (Opcode) {
2425 case VMULPDYrm:
2426 case VMULPDYrr:
2427 case VMULPDZ128rm:
2428 case VMULPDZ128rmb:
2429 case VMULPDZ128rmbk:
2430 case VMULPDZ128rmbkz:
2431 case VMULPDZ128rmk:
2432 case VMULPDZ128rmkz:
2433 case VMULPDZ128rr:
2434 case VMULPDZ128rrk:
2435 case VMULPDZ128rrkz:
2436 case VMULPDZ256rm:
2437 case VMULPDZ256rmb:
2438 case VMULPDZ256rmbk:
2439 case VMULPDZ256rmbkz:
2440 case VMULPDZ256rmk:
2441 case VMULPDZ256rmkz:
2442 case VMULPDZ256rr:
2443 case VMULPDZ256rrk:
2444 case VMULPDZ256rrkz:
2445 case VMULPDZrm:
2446 case VMULPDZrmb:
2447 case VMULPDZrmbk:
2448 case VMULPDZrmbkz:
2449 case VMULPDZrmk:
2450 case VMULPDZrmkz:
2451 case VMULPDZrr:
2452 case VMULPDZrrb:
2453 case VMULPDZrrbk:
2454 case VMULPDZrrbkz:
2455 case VMULPDZrrk:
2456 case VMULPDZrrkz:
2457 case VMULPDrm:
2458 case VMULPDrr:
2459 return true;
2460 }
2461 return false;
2462}
2463
2464bool isVFMADDSUB132PS(unsigned Opcode) {
2465 switch (Opcode) {
2466 case VFMADDSUB132PSYm:
2467 case VFMADDSUB132PSYr:
2468 case VFMADDSUB132PSZ128m:
2469 case VFMADDSUB132PSZ128mb:
2470 case VFMADDSUB132PSZ128mbk:
2471 case VFMADDSUB132PSZ128mbkz:
2472 case VFMADDSUB132PSZ128mk:
2473 case VFMADDSUB132PSZ128mkz:
2474 case VFMADDSUB132PSZ128r:
2475 case VFMADDSUB132PSZ128rk:
2476 case VFMADDSUB132PSZ128rkz:
2477 case VFMADDSUB132PSZ256m:
2478 case VFMADDSUB132PSZ256mb:
2479 case VFMADDSUB132PSZ256mbk:
2480 case VFMADDSUB132PSZ256mbkz:
2481 case VFMADDSUB132PSZ256mk:
2482 case VFMADDSUB132PSZ256mkz:
2483 case VFMADDSUB132PSZ256r:
2484 case VFMADDSUB132PSZ256rk:
2485 case VFMADDSUB132PSZ256rkz:
2486 case VFMADDSUB132PSZm:
2487 case VFMADDSUB132PSZmb:
2488 case VFMADDSUB132PSZmbk:
2489 case VFMADDSUB132PSZmbkz:
2490 case VFMADDSUB132PSZmk:
2491 case VFMADDSUB132PSZmkz:
2492 case VFMADDSUB132PSZr:
2493 case VFMADDSUB132PSZrb:
2494 case VFMADDSUB132PSZrbk:
2495 case VFMADDSUB132PSZrbkz:
2496 case VFMADDSUB132PSZrk:
2497 case VFMADDSUB132PSZrkz:
2498 case VFMADDSUB132PSm:
2499 case VFMADDSUB132PSr:
2500 return true;
2501 }
2502 return false;
2503}
2504
2505bool isVPMADCSWD(unsigned Opcode) {
2506 switch (Opcode) {
2507 case VPMADCSWDrm:
2508 case VPMADCSWDrr:
2509 return true;
2510 }
2511 return false;
2512}
2513
2514bool isVSCATTERPF0DPS(unsigned Opcode) {
2515 return Opcode == VSCATTERPF0DPSm;
2516}
2517
2518bool isXCHG(unsigned Opcode) {
2519 switch (Opcode) {
2520 case XCHG16ar:
2521 case XCHG16rm:
2522 case XCHG16rr:
2523 case XCHG32ar:
2524 case XCHG32rm:
2525 case XCHG32rr:
2526 case XCHG64ar:
2527 case XCHG64rm:
2528 case XCHG64rr:
2529 case XCHG8rm:
2530 case XCHG8rr:
2531 return true;
2532 }
2533 return false;
2534}
2535
2536bool isVGATHERPF1QPS(unsigned Opcode) {
2537 return Opcode == VGATHERPF1QPSm;
2538}
2539
2540bool isVCVTNEPS2BF16(unsigned Opcode) {
2541 switch (Opcode) {
2542 case VCVTNEPS2BF16Yrm:
2543 case VCVTNEPS2BF16Yrr:
2544 case VCVTNEPS2BF16Z128rm:
2545 case VCVTNEPS2BF16Z128rmb:
2546 case VCVTNEPS2BF16Z128rmbk:
2547 case VCVTNEPS2BF16Z128rmbkz:
2548 case VCVTNEPS2BF16Z128rmk:
2549 case VCVTNEPS2BF16Z128rmkz:
2550 case VCVTNEPS2BF16Z128rr:
2551 case VCVTNEPS2BF16Z128rrk:
2552 case VCVTNEPS2BF16Z128rrkz:
2553 case VCVTNEPS2BF16Z256rm:
2554 case VCVTNEPS2BF16Z256rmb:
2555 case VCVTNEPS2BF16Z256rmbk:
2556 case VCVTNEPS2BF16Z256rmbkz:
2557 case VCVTNEPS2BF16Z256rmk:
2558 case VCVTNEPS2BF16Z256rmkz:
2559 case VCVTNEPS2BF16Z256rr:
2560 case VCVTNEPS2BF16Z256rrk:
2561 case VCVTNEPS2BF16Z256rrkz:
2562 case VCVTNEPS2BF16Zrm:
2563 case VCVTNEPS2BF16Zrmb:
2564 case VCVTNEPS2BF16Zrmbk:
2565 case VCVTNEPS2BF16Zrmbkz:
2566 case VCVTNEPS2BF16Zrmk:
2567 case VCVTNEPS2BF16Zrmkz:
2568 case VCVTNEPS2BF16Zrr:
2569 case VCVTNEPS2BF16Zrrk:
2570 case VCVTNEPS2BF16Zrrkz:
2571 case VCVTNEPS2BF16rm:
2572 case VCVTNEPS2BF16rr:
2573 return true;
2574 }
2575 return false;
2576}
2577
2578bool isVFMADDSS(unsigned Opcode) {
2579 switch (Opcode) {
2580 case VFMADDSS4mr:
2581 case VFMADDSS4rm:
2582 case VFMADDSS4rr:
2583 case VFMADDSS4rr_REV:
2584 return true;
2585 }
2586 return false;
2587}
2588
2589bool isINTO(unsigned Opcode) {
2590 return Opcode == INTO;
2591}
2592
2593bool isANDPD(unsigned Opcode) {
2594 switch (Opcode) {
2595 case ANDPDrm:
2596 case ANDPDrr:
2597 return true;
2598 }
2599 return false;
2600}
2601
2602bool isSEAMCALL(unsigned Opcode) {
2603 return Opcode == SEAMCALL;
2604}
2605
2606bool isVPDPBSSDS(unsigned Opcode) {
2607 switch (Opcode) {
2608 case VPDPBSSDSYrm:
2609 case VPDPBSSDSYrr:
2610 case VPDPBSSDSZ128rm:
2611 case VPDPBSSDSZ128rmb:
2612 case VPDPBSSDSZ128rmbk:
2613 case VPDPBSSDSZ128rmbkz:
2614 case VPDPBSSDSZ128rmk:
2615 case VPDPBSSDSZ128rmkz:
2616 case VPDPBSSDSZ128rr:
2617 case VPDPBSSDSZ128rrk:
2618 case VPDPBSSDSZ128rrkz:
2619 case VPDPBSSDSZ256rm:
2620 case VPDPBSSDSZ256rmb:
2621 case VPDPBSSDSZ256rmbk:
2622 case VPDPBSSDSZ256rmbkz:
2623 case VPDPBSSDSZ256rmk:
2624 case VPDPBSSDSZ256rmkz:
2625 case VPDPBSSDSZ256rr:
2626 case VPDPBSSDSZ256rrk:
2627 case VPDPBSSDSZ256rrkz:
2628 case VPDPBSSDSZrm:
2629 case VPDPBSSDSZrmb:
2630 case VPDPBSSDSZrmbk:
2631 case VPDPBSSDSZrmbkz:
2632 case VPDPBSSDSZrmk:
2633 case VPDPBSSDSZrmkz:
2634 case VPDPBSSDSZrr:
2635 case VPDPBSSDSZrrk:
2636 case VPDPBSSDSZrrkz:
2637 case VPDPBSSDSrm:
2638 case VPDPBSSDSrr:
2639 return true;
2640 }
2641 return false;
2642}
2643
2644bool isUNPCKHPS(unsigned Opcode) {
2645 switch (Opcode) {
2646 case UNPCKHPSrm:
2647 case UNPCKHPSrr:
2648 return true;
2649 }
2650 return false;
2651}
2652
2653bool isSETZUCC(unsigned Opcode) {
2654 switch (Opcode) {
2655 case SETZUCCm:
2656 case SETZUCCr:
2657 return true;
2658 }
2659 return false;
2660}
2661
2662bool isSHUFPD(unsigned Opcode) {
2663 switch (Opcode) {
2664 case SHUFPDrmi:
2665 case SHUFPDrri:
2666 return true;
2667 }
2668 return false;
2669}
2670
2671bool isFCMOVNB(unsigned Opcode) {
2672 return Opcode == CMOVNB_F;
2673}
2674
2675bool isCVTTSS2SI(unsigned Opcode) {
2676 switch (Opcode) {
2677 case CVTTSS2SI64rm_Int:
2678 case CVTTSS2SI64rr_Int:
2679 case CVTTSS2SIrm_Int:
2680 case CVTTSS2SIrr_Int:
2681 return true;
2682 }
2683 return false;
2684}
2685
2686bool isEXTRQ(unsigned Opcode) {
2687 switch (Opcode) {
2688 case EXTRQ:
2689 case EXTRQI:
2690 return true;
2691 }
2692 return false;
2693}
2694
2695bool isSHLD(unsigned Opcode) {
2696 switch (Opcode) {
2697 case SHLD16mrCL:
2698 case SHLD16mrCL_EVEX:
2699 case SHLD16mrCL_ND:
2700 case SHLD16mrCL_NF:
2701 case SHLD16mrCL_NF_ND:
2702 case SHLD16mri8:
2703 case SHLD16mri8_EVEX:
2704 case SHLD16mri8_ND:
2705 case SHLD16mri8_NF:
2706 case SHLD16mri8_NF_ND:
2707 case SHLD16rrCL:
2708 case SHLD16rrCL_EVEX:
2709 case SHLD16rrCL_ND:
2710 case SHLD16rrCL_NF:
2711 case SHLD16rrCL_NF_ND:
2712 case SHLD16rri8:
2713 case SHLD16rri8_EVEX:
2714 case SHLD16rri8_ND:
2715 case SHLD16rri8_NF:
2716 case SHLD16rri8_NF_ND:
2717 case SHLD32mrCL:
2718 case SHLD32mrCL_EVEX:
2719 case SHLD32mrCL_ND:
2720 case SHLD32mrCL_NF:
2721 case SHLD32mrCL_NF_ND:
2722 case SHLD32mri8:
2723 case SHLD32mri8_EVEX:
2724 case SHLD32mri8_ND:
2725 case SHLD32mri8_NF:
2726 case SHLD32mri8_NF_ND:
2727 case SHLD32rrCL:
2728 case SHLD32rrCL_EVEX:
2729 case SHLD32rrCL_ND:
2730 case SHLD32rrCL_NF:
2731 case SHLD32rrCL_NF_ND:
2732 case SHLD32rri8:
2733 case SHLD32rri8_EVEX:
2734 case SHLD32rri8_ND:
2735 case SHLD32rri8_NF:
2736 case SHLD32rri8_NF_ND:
2737 case SHLD64mrCL:
2738 case SHLD64mrCL_EVEX:
2739 case SHLD64mrCL_ND:
2740 case SHLD64mrCL_NF:
2741 case SHLD64mrCL_NF_ND:
2742 case SHLD64mri8:
2743 case SHLD64mri8_EVEX:
2744 case SHLD64mri8_ND:
2745 case SHLD64mri8_NF:
2746 case SHLD64mri8_NF_ND:
2747 case SHLD64rrCL:
2748 case SHLD64rrCL_EVEX:
2749 case SHLD64rrCL_ND:
2750 case SHLD64rrCL_NF:
2751 case SHLD64rrCL_NF_ND:
2752 case SHLD64rri8:
2753 case SHLD64rri8_EVEX:
2754 case SHLD64rri8_ND:
2755 case SHLD64rri8_NF:
2756 case SHLD64rri8_NF_ND:
2757 return true;
2758 }
2759 return false;
2760}
2761
2762bool isVBROADCASTSS(unsigned Opcode) {
2763 switch (Opcode) {
2764 case VBROADCASTSSYrm:
2765 case VBROADCASTSSYrr:
2766 case VBROADCASTSSZ128rm:
2767 case VBROADCASTSSZ128rmk:
2768 case VBROADCASTSSZ128rmkz:
2769 case VBROADCASTSSZ128rr:
2770 case VBROADCASTSSZ128rrk:
2771 case VBROADCASTSSZ128rrkz:
2772 case VBROADCASTSSZ256rm:
2773 case VBROADCASTSSZ256rmk:
2774 case VBROADCASTSSZ256rmkz:
2775 case VBROADCASTSSZ256rr:
2776 case VBROADCASTSSZ256rrk:
2777 case VBROADCASTSSZ256rrkz:
2778 case VBROADCASTSSZrm:
2779 case VBROADCASTSSZrmk:
2780 case VBROADCASTSSZrmkz:
2781 case VBROADCASTSSZrr:
2782 case VBROADCASTSSZrrk:
2783 case VBROADCASTSSZrrkz:
2784 case VBROADCASTSSrm:
2785 case VBROADCASTSSrr:
2786 return true;
2787 }
2788 return false;
2789}
2790
2791bool isCLUI(unsigned Opcode) {
2792 return Opcode == CLUI;
2793}
2794
2795bool isVINSERTI128(unsigned Opcode) {
2796 switch (Opcode) {
2797 case VINSERTI128rmi:
2798 case VINSERTI128rri:
2799 return true;
2800 }
2801 return false;
2802}
2803
2804bool isVBLENDPD(unsigned Opcode) {
2805 switch (Opcode) {
2806 case VBLENDPDYrmi:
2807 case VBLENDPDYrri:
2808 case VBLENDPDrmi:
2809 case VBLENDPDrri:
2810 return true;
2811 }
2812 return false;
2813}
2814
2815bool isVPSHLDW(unsigned Opcode) {
2816 switch (Opcode) {
2817 case VPSHLDWZ128rmi:
2818 case VPSHLDWZ128rmik:
2819 case VPSHLDWZ128rmikz:
2820 case VPSHLDWZ128rri:
2821 case VPSHLDWZ128rrik:
2822 case VPSHLDWZ128rrikz:
2823 case VPSHLDWZ256rmi:
2824 case VPSHLDWZ256rmik:
2825 case VPSHLDWZ256rmikz:
2826 case VPSHLDWZ256rri:
2827 case VPSHLDWZ256rrik:
2828 case VPSHLDWZ256rrikz:
2829 case VPSHLDWZrmi:
2830 case VPSHLDWZrmik:
2831 case VPSHLDWZrmikz:
2832 case VPSHLDWZrri:
2833 case VPSHLDWZrrik:
2834 case VPSHLDWZrrikz:
2835 return true;
2836 }
2837 return false;
2838}
2839
2840bool isVCVTNEEPH2PS(unsigned Opcode) {
2841 switch (Opcode) {
2842 case VCVTNEEPH2PSYrm:
2843 case VCVTNEEPH2PSrm:
2844 return true;
2845 }
2846 return false;
2847}
2848
2849bool isVCVTTSD2SI(unsigned Opcode) {
2850 switch (Opcode) {
2851 case VCVTTSD2SI64Zrm_Int:
2852 case VCVTTSD2SI64Zrr_Int:
2853 case VCVTTSD2SI64Zrrb_Int:
2854 case VCVTTSD2SI64rm_Int:
2855 case VCVTTSD2SI64rr_Int:
2856 case VCVTTSD2SIZrm_Int:
2857 case VCVTTSD2SIZrr_Int:
2858 case VCVTTSD2SIZrrb_Int:
2859 case VCVTTSD2SIrm_Int:
2860 case VCVTTSD2SIrr_Int:
2861 return true;
2862 }
2863 return false;
2864}
2865
2866bool isVSM4KEY4(unsigned Opcode) {
2867 switch (Opcode) {
2868 case VSM4KEY4Yrm:
2869 case VSM4KEY4Yrr:
2870 case VSM4KEY4Z128rm:
2871 case VSM4KEY4Z128rr:
2872 case VSM4KEY4Z256rm:
2873 case VSM4KEY4Z256rr:
2874 case VSM4KEY4Zrm:
2875 case VSM4KEY4Zrr:
2876 case VSM4KEY4rm:
2877 case VSM4KEY4rr:
2878 return true;
2879 }
2880 return false;
2881}
2882
2883bool isWRMSRNS(unsigned Opcode) {
2884 switch (Opcode) {
2885 case WRMSRNS:
2886 case WRMSRNSir:
2887 case WRMSRNSir_EVEX:
2888 return true;
2889 }
2890 return false;
2891}
2892
2893bool isCMPSB(unsigned Opcode) {
2894 return Opcode == CMPSB;
2895}
2896
2897bool isVRCPBF16(unsigned Opcode) {
2898 switch (Opcode) {
2899 case VRCPBF16Z128m:
2900 case VRCPBF16Z128mb:
2901 case VRCPBF16Z128mbk:
2902 case VRCPBF16Z128mbkz:
2903 case VRCPBF16Z128mk:
2904 case VRCPBF16Z128mkz:
2905 case VRCPBF16Z128r:
2906 case VRCPBF16Z128rk:
2907 case VRCPBF16Z128rkz:
2908 case VRCPBF16Z256m:
2909 case VRCPBF16Z256mb:
2910 case VRCPBF16Z256mbk:
2911 case VRCPBF16Z256mbkz:
2912 case VRCPBF16Z256mk:
2913 case VRCPBF16Z256mkz:
2914 case VRCPBF16Z256r:
2915 case VRCPBF16Z256rk:
2916 case VRCPBF16Z256rkz:
2917 case VRCPBF16Zm:
2918 case VRCPBF16Zmb:
2919 case VRCPBF16Zmbk:
2920 case VRCPBF16Zmbkz:
2921 case VRCPBF16Zmk:
2922 case VRCPBF16Zmkz:
2923 case VRCPBF16Zr:
2924 case VRCPBF16Zrk:
2925 case VRCPBF16Zrkz:
2926 return true;
2927 }
2928 return false;
2929}
2930
2931bool isMULSS(unsigned Opcode) {
2932 switch (Opcode) {
2933 case MULSSrm_Int:
2934 case MULSSrr_Int:
2935 return true;
2936 }
2937 return false;
2938}
2939
2940bool isVMRUN(unsigned Opcode) {
2941 switch (Opcode) {
2942 case VMRUN32:
2943 case VMRUN64:
2944 return true;
2945 }
2946 return false;
2947}
2948
2949bool isVPSRLVD(unsigned Opcode) {
2950 switch (Opcode) {
2951 case VPSRLVDYrm:
2952 case VPSRLVDYrr:
2953 case VPSRLVDZ128rm:
2954 case VPSRLVDZ128rmb:
2955 case VPSRLVDZ128rmbk:
2956 case VPSRLVDZ128rmbkz:
2957 case VPSRLVDZ128rmk:
2958 case VPSRLVDZ128rmkz:
2959 case VPSRLVDZ128rr:
2960 case VPSRLVDZ128rrk:
2961 case VPSRLVDZ128rrkz:
2962 case VPSRLVDZ256rm:
2963 case VPSRLVDZ256rmb:
2964 case VPSRLVDZ256rmbk:
2965 case VPSRLVDZ256rmbkz:
2966 case VPSRLVDZ256rmk:
2967 case VPSRLVDZ256rmkz:
2968 case VPSRLVDZ256rr:
2969 case VPSRLVDZ256rrk:
2970 case VPSRLVDZ256rrkz:
2971 case VPSRLVDZrm:
2972 case VPSRLVDZrmb:
2973 case VPSRLVDZrmbk:
2974 case VPSRLVDZrmbkz:
2975 case VPSRLVDZrmk:
2976 case VPSRLVDZrmkz:
2977 case VPSRLVDZrr:
2978 case VPSRLVDZrrk:
2979 case VPSRLVDZrrkz:
2980 case VPSRLVDrm:
2981 case VPSRLVDrr:
2982 return true;
2983 }
2984 return false;
2985}
2986
2987bool isLEAVE(unsigned Opcode) {
2988 switch (Opcode) {
2989 case LEAVE:
2990 case LEAVE64:
2991 return true;
2992 }
2993 return false;
2994}
2995
2996bool isVGETMANTPS(unsigned Opcode) {
2997 switch (Opcode) {
2998 case VGETMANTPSZ128rmbi:
2999 case VGETMANTPSZ128rmbik:
3000 case VGETMANTPSZ128rmbikz:
3001 case VGETMANTPSZ128rmi:
3002 case VGETMANTPSZ128rmik:
3003 case VGETMANTPSZ128rmikz:
3004 case VGETMANTPSZ128rri:
3005 case VGETMANTPSZ128rrik:
3006 case VGETMANTPSZ128rrikz:
3007 case VGETMANTPSZ256rmbi:
3008 case VGETMANTPSZ256rmbik:
3009 case VGETMANTPSZ256rmbikz:
3010 case VGETMANTPSZ256rmi:
3011 case VGETMANTPSZ256rmik:
3012 case VGETMANTPSZ256rmikz:
3013 case VGETMANTPSZ256rri:
3014 case VGETMANTPSZ256rrik:
3015 case VGETMANTPSZ256rrikz:
3016 case VGETMANTPSZrmbi:
3017 case VGETMANTPSZrmbik:
3018 case VGETMANTPSZrmbikz:
3019 case VGETMANTPSZrmi:
3020 case VGETMANTPSZrmik:
3021 case VGETMANTPSZrmikz:
3022 case VGETMANTPSZrri:
3023 case VGETMANTPSZrrib:
3024 case VGETMANTPSZrribk:
3025 case VGETMANTPSZrribkz:
3026 case VGETMANTPSZrrik:
3027 case VGETMANTPSZrrikz:
3028 return true;
3029 }
3030 return false;
3031}
3032
3033bool isXSHA256(unsigned Opcode) {
3034 return Opcode == XSHA256;
3035}
3036
3037bool isBOUND(unsigned Opcode) {
3038 switch (Opcode) {
3039 case BOUNDS16rm:
3040 case BOUNDS32rm:
3041 return true;
3042 }
3043 return false;
3044}
3045
3046bool isSFENCE(unsigned Opcode) {
3047 return Opcode == SFENCE;
3048}
3049
3050bool isVPHADDD(unsigned Opcode) {
3051 switch (Opcode) {
3052 case VPHADDDYrm:
3053 case VPHADDDYrr:
3054 case VPHADDDrm:
3055 case VPHADDDrr:
3056 return true;
3057 }
3058 return false;
3059}
3060
3061bool isADOX(unsigned Opcode) {
3062 switch (Opcode) {
3063 case ADOX32rm:
3064 case ADOX32rm_EVEX:
3065 case ADOX32rm_ND:
3066 case ADOX32rr:
3067 case ADOX32rr_EVEX:
3068 case ADOX32rr_ND:
3069 case ADOX64rm:
3070 case ADOX64rm_EVEX:
3071 case ADOX64rm_ND:
3072 case ADOX64rr:
3073 case ADOX64rr_EVEX:
3074 case ADOX64rr_ND:
3075 return true;
3076 }
3077 return false;
3078}
3079
3080bool isVPSLLQ(unsigned Opcode) {
3081 switch (Opcode) {
3082 case VPSLLQYri:
3083 case VPSLLQYrm:
3084 case VPSLLQYrr:
3085 case VPSLLQZ128mbi:
3086 case VPSLLQZ128mbik:
3087 case VPSLLQZ128mbikz:
3088 case VPSLLQZ128mi:
3089 case VPSLLQZ128mik:
3090 case VPSLLQZ128mikz:
3091 case VPSLLQZ128ri:
3092 case VPSLLQZ128rik:
3093 case VPSLLQZ128rikz:
3094 case VPSLLQZ128rm:
3095 case VPSLLQZ128rmk:
3096 case VPSLLQZ128rmkz:
3097 case VPSLLQZ128rr:
3098 case VPSLLQZ128rrk:
3099 case VPSLLQZ128rrkz:
3100 case VPSLLQZ256mbi:
3101 case VPSLLQZ256mbik:
3102 case VPSLLQZ256mbikz:
3103 case VPSLLQZ256mi:
3104 case VPSLLQZ256mik:
3105 case VPSLLQZ256mikz:
3106 case VPSLLQZ256ri:
3107 case VPSLLQZ256rik:
3108 case VPSLLQZ256rikz:
3109 case VPSLLQZ256rm:
3110 case VPSLLQZ256rmk:
3111 case VPSLLQZ256rmkz:
3112 case VPSLLQZ256rr:
3113 case VPSLLQZ256rrk:
3114 case VPSLLQZ256rrkz:
3115 case VPSLLQZmbi:
3116 case VPSLLQZmbik:
3117 case VPSLLQZmbikz:
3118 case VPSLLQZmi:
3119 case VPSLLQZmik:
3120 case VPSLLQZmikz:
3121 case VPSLLQZri:
3122 case VPSLLQZrik:
3123 case VPSLLQZrikz:
3124 case VPSLLQZrm:
3125 case VPSLLQZrmk:
3126 case VPSLLQZrmkz:
3127 case VPSLLQZrr:
3128 case VPSLLQZrrk:
3129 case VPSLLQZrrkz:
3130 case VPSLLQri:
3131 case VPSLLQrm:
3132 case VPSLLQrr:
3133 return true;
3134 }
3135 return false;
3136}
3137
3138bool isVCVTPH2HF8(unsigned Opcode) {
3139 switch (Opcode) {
3140 case VCVTPH2HF8Z128rm:
3141 case VCVTPH2HF8Z128rmb:
3142 case VCVTPH2HF8Z128rmbk:
3143 case VCVTPH2HF8Z128rmbkz:
3144 case VCVTPH2HF8Z128rmk:
3145 case VCVTPH2HF8Z128rmkz:
3146 case VCVTPH2HF8Z128rr:
3147 case VCVTPH2HF8Z128rrk:
3148 case VCVTPH2HF8Z128rrkz:
3149 case VCVTPH2HF8Z256rm:
3150 case VCVTPH2HF8Z256rmb:
3151 case VCVTPH2HF8Z256rmbk:
3152 case VCVTPH2HF8Z256rmbkz:
3153 case VCVTPH2HF8Z256rmk:
3154 case VCVTPH2HF8Z256rmkz:
3155 case VCVTPH2HF8Z256rr:
3156 case VCVTPH2HF8Z256rrk:
3157 case VCVTPH2HF8Z256rrkz:
3158 case VCVTPH2HF8Zrm:
3159 case VCVTPH2HF8Zrmb:
3160 case VCVTPH2HF8Zrmbk:
3161 case VCVTPH2HF8Zrmbkz:
3162 case VCVTPH2HF8Zrmk:
3163 case VCVTPH2HF8Zrmkz:
3164 case VCVTPH2HF8Zrr:
3165 case VCVTPH2HF8Zrrk:
3166 case VCVTPH2HF8Zrrkz:
3167 return true;
3168 }
3169 return false;
3170}
3171
3172bool isPFRSQIT1(unsigned Opcode) {
3173 switch (Opcode) {
3174 case PFRSQIT1rm:
3175 case PFRSQIT1rr:
3176 return true;
3177 }
3178 return false;
3179}
3180
3181bool isCLAC(unsigned Opcode) {
3182 return Opcode == CLAC;
3183}
3184
3185bool isKNOTW(unsigned Opcode) {
3186 return Opcode == KNOTWkk;
3187}
3188
3189bool isVCVTPH2PD(unsigned Opcode) {
3190 switch (Opcode) {
3191 case VCVTPH2PDZ128rm:
3192 case VCVTPH2PDZ128rmb:
3193 case VCVTPH2PDZ128rmbk:
3194 case VCVTPH2PDZ128rmbkz:
3195 case VCVTPH2PDZ128rmk:
3196 case VCVTPH2PDZ128rmkz:
3197 case VCVTPH2PDZ128rr:
3198 case VCVTPH2PDZ128rrk:
3199 case VCVTPH2PDZ128rrkz:
3200 case VCVTPH2PDZ256rm:
3201 case VCVTPH2PDZ256rmb:
3202 case VCVTPH2PDZ256rmbk:
3203 case VCVTPH2PDZ256rmbkz:
3204 case VCVTPH2PDZ256rmk:
3205 case VCVTPH2PDZ256rmkz:
3206 case VCVTPH2PDZ256rr:
3207 case VCVTPH2PDZ256rrk:
3208 case VCVTPH2PDZ256rrkz:
3209 case VCVTPH2PDZrm:
3210 case VCVTPH2PDZrmb:
3211 case VCVTPH2PDZrmbk:
3212 case VCVTPH2PDZrmbkz:
3213 case VCVTPH2PDZrmk:
3214 case VCVTPH2PDZrmkz:
3215 case VCVTPH2PDZrr:
3216 case VCVTPH2PDZrrb:
3217 case VCVTPH2PDZrrbk:
3218 case VCVTPH2PDZrrbkz:
3219 case VCVTPH2PDZrrk:
3220 case VCVTPH2PDZrrkz:
3221 return true;
3222 }
3223 return false;
3224}
3225
3226bool isVAESENC(unsigned Opcode) {
3227 switch (Opcode) {
3228 case VAESENCYrm:
3229 case VAESENCYrr:
3230 case VAESENCZ128rm:
3231 case VAESENCZ128rr:
3232 case VAESENCZ256rm:
3233 case VAESENCZ256rr:
3234 case VAESENCZrm:
3235 case VAESENCZrr:
3236 case VAESENCrm:
3237 case VAESENCrr:
3238 return true;
3239 }
3240 return false;
3241}
3242
3243bool isMOVNTI(unsigned Opcode) {
3244 switch (Opcode) {
3245 case MOVNTI_64mr:
3246 case MOVNTImr:
3247 return true;
3248 }
3249 return false;
3250}
3251
3252bool isFXCH(unsigned Opcode) {
3253 return Opcode == XCH_F;
3254}
3255
3256bool isPOPP(unsigned Opcode) {
3257 return Opcode == POPP64r;
3258}
3259
3260bool isVPBLENDMD(unsigned Opcode) {
3261 switch (Opcode) {
3262 case VPBLENDMDZ128rm:
3263 case VPBLENDMDZ128rmb:
3264 case VPBLENDMDZ128rmbk:
3265 case VPBLENDMDZ128rmbkz:
3266 case VPBLENDMDZ128rmk:
3267 case VPBLENDMDZ128rmkz:
3268 case VPBLENDMDZ128rr:
3269 case VPBLENDMDZ128rrk:
3270 case VPBLENDMDZ128rrkz:
3271 case VPBLENDMDZ256rm:
3272 case VPBLENDMDZ256rmb:
3273 case VPBLENDMDZ256rmbk:
3274 case VPBLENDMDZ256rmbkz:
3275 case VPBLENDMDZ256rmk:
3276 case VPBLENDMDZ256rmkz:
3277 case VPBLENDMDZ256rr:
3278 case VPBLENDMDZ256rrk:
3279 case VPBLENDMDZ256rrkz:
3280 case VPBLENDMDZrm:
3281 case VPBLENDMDZrmb:
3282 case VPBLENDMDZrmbk:
3283 case VPBLENDMDZrmbkz:
3284 case VPBLENDMDZrmk:
3285 case VPBLENDMDZrmkz:
3286 case VPBLENDMDZrr:
3287 case VPBLENDMDZrrk:
3288 case VPBLENDMDZrrkz:
3289 return true;
3290 }
3291 return false;
3292}
3293
3294bool isFSINCOS(unsigned Opcode) {
3295 return Opcode == FSINCOS;
3296}
3297
3298bool isVPMULLW(unsigned Opcode) {
3299 switch (Opcode) {
3300 case VPMULLWYrm:
3301 case VPMULLWYrr:
3302 case VPMULLWZ128rm:
3303 case VPMULLWZ128rmk:
3304 case VPMULLWZ128rmkz:
3305 case VPMULLWZ128rr:
3306 case VPMULLWZ128rrk:
3307 case VPMULLWZ128rrkz:
3308 case VPMULLWZ256rm:
3309 case VPMULLWZ256rmk:
3310 case VPMULLWZ256rmkz:
3311 case VPMULLWZ256rr:
3312 case VPMULLWZ256rrk:
3313 case VPMULLWZ256rrkz:
3314 case VPMULLWZrm:
3315 case VPMULLWZrmk:
3316 case VPMULLWZrmkz:
3317 case VPMULLWZrr:
3318 case VPMULLWZrrk:
3319 case VPMULLWZrrkz:
3320 case VPMULLWrm:
3321 case VPMULLWrr:
3322 return true;
3323 }
3324 return false;
3325}
3326
3327bool isVPMOVSXBW(unsigned Opcode) {
3328 switch (Opcode) {
3329 case VPMOVSXBWYrm:
3330 case VPMOVSXBWYrr:
3331 case VPMOVSXBWZ128rm:
3332 case VPMOVSXBWZ128rmk:
3333 case VPMOVSXBWZ128rmkz:
3334 case VPMOVSXBWZ128rr:
3335 case VPMOVSXBWZ128rrk:
3336 case VPMOVSXBWZ128rrkz:
3337 case VPMOVSXBWZ256rm:
3338 case VPMOVSXBWZ256rmk:
3339 case VPMOVSXBWZ256rmkz:
3340 case VPMOVSXBWZ256rr:
3341 case VPMOVSXBWZ256rrk:
3342 case VPMOVSXBWZ256rrkz:
3343 case VPMOVSXBWZrm:
3344 case VPMOVSXBWZrmk:
3345 case VPMOVSXBWZrmkz:
3346 case VPMOVSXBWZrr:
3347 case VPMOVSXBWZrrk:
3348 case VPMOVSXBWZrrkz:
3349 case VPMOVSXBWrm:
3350 case VPMOVSXBWrr:
3351 return true;
3352 }
3353 return false;
3354}
3355
3356bool isSTC(unsigned Opcode) {
3357 return Opcode == STC;
3358}
3359
3360bool isVPINSRB(unsigned Opcode) {
3361 switch (Opcode) {
3362 case VPINSRBZrmi:
3363 case VPINSRBZrri:
3364 case VPINSRBrmi:
3365 case VPINSRBrri:
3366 return true;
3367 }
3368 return false;
3369}
3370
3371bool isLWPVAL(unsigned Opcode) {
3372 switch (Opcode) {
3373 case LWPVAL32rmi:
3374 case LWPVAL32rri:
3375 case LWPVAL64rmi:
3376 case LWPVAL64rri:
3377 return true;
3378 }
3379 return false;
3380}
3381
3382bool isKXORB(unsigned Opcode) {
3383 return Opcode == KXORBkk;
3384}
3385
3386bool isRSTORSSP(unsigned Opcode) {
3387 return Opcode == RSTORSSP;
3388}
3389
3390bool isVPRORQ(unsigned Opcode) {
3391 switch (Opcode) {
3392 case VPRORQZ128mbi:
3393 case VPRORQZ128mbik:
3394 case VPRORQZ128mbikz:
3395 case VPRORQZ128mi:
3396 case VPRORQZ128mik:
3397 case VPRORQZ128mikz:
3398 case VPRORQZ128ri:
3399 case VPRORQZ128rik:
3400 case VPRORQZ128rikz:
3401 case VPRORQZ256mbi:
3402 case VPRORQZ256mbik:
3403 case VPRORQZ256mbikz:
3404 case VPRORQZ256mi:
3405 case VPRORQZ256mik:
3406 case VPRORQZ256mikz:
3407 case VPRORQZ256ri:
3408 case VPRORQZ256rik:
3409 case VPRORQZ256rikz:
3410 case VPRORQZmbi:
3411 case VPRORQZmbik:
3412 case VPRORQZmbikz:
3413 case VPRORQZmi:
3414 case VPRORQZmik:
3415 case VPRORQZmikz:
3416 case VPRORQZri:
3417 case VPRORQZrik:
3418 case VPRORQZrikz:
3419 return true;
3420 }
3421 return false;
3422}
3423
3424bool isVSM3MSG1(unsigned Opcode) {
3425 switch (Opcode) {
3426 case VSM3MSG1rm:
3427 case VSM3MSG1rr:
3428 return true;
3429 }
3430 return false;
3431}
3432
3433bool isFICOM(unsigned Opcode) {
3434 switch (Opcode) {
3435 case FICOM16m:
3436 case FICOM32m:
3437 return true;
3438 }
3439 return false;
3440}
3441
3442bool isMAXPS(unsigned Opcode) {
3443 switch (Opcode) {
3444 case MAXPSrm:
3445 case MAXPSrr:
3446 return true;
3447 }
3448 return false;
3449}
3450
3451bool isFNCLEX(unsigned Opcode) {
3452 return Opcode == FNCLEX;
3453}
3454
3455bool isVMOVMSKPS(unsigned Opcode) {
3456 switch (Opcode) {
3457 case VMOVMSKPSYrr:
3458 case VMOVMSKPSrr:
3459 return true;
3460 }
3461 return false;
3462}
3463
3464bool isVPMOVDB(unsigned Opcode) {
3465 switch (Opcode) {
3466 case VPMOVDBZ128mr:
3467 case VPMOVDBZ128mrk:
3468 case VPMOVDBZ128rr:
3469 case VPMOVDBZ128rrk:
3470 case VPMOVDBZ128rrkz:
3471 case VPMOVDBZ256mr:
3472 case VPMOVDBZ256mrk:
3473 case VPMOVDBZ256rr:
3474 case VPMOVDBZ256rrk:
3475 case VPMOVDBZ256rrkz:
3476 case VPMOVDBZmr:
3477 case VPMOVDBZmrk:
3478 case VPMOVDBZrr:
3479 case VPMOVDBZrrk:
3480 case VPMOVDBZrrkz:
3481 return true;
3482 }
3483 return false;
3484}
3485
3486bool isLLWPCB(unsigned Opcode) {
3487 switch (Opcode) {
3488 case LLWPCB:
3489 case LLWPCB64:
3490 return true;
3491 }
3492 return false;
3493}
3494
3495bool isVMULSS(unsigned Opcode) {
3496 switch (Opcode) {
3497 case VMULSSZrm_Int:
3498 case VMULSSZrmk_Int:
3499 case VMULSSZrmkz_Int:
3500 case VMULSSZrr_Int:
3501 case VMULSSZrrb_Int:
3502 case VMULSSZrrbk_Int:
3503 case VMULSSZrrbkz_Int:
3504 case VMULSSZrrk_Int:
3505 case VMULSSZrrkz_Int:
3506 case VMULSSrm_Int:
3507 case VMULSSrr_Int:
3508 return true;
3509 }
3510 return false;
3511}
3512
3513bool isAESENCLAST(unsigned Opcode) {
3514 switch (Opcode) {
3515 case AESENCLASTrm:
3516 case AESENCLASTrr:
3517 return true;
3518 }
3519 return false;
3520}
3521
3522bool isTILEMOVROW(unsigned Opcode) {
3523 switch (Opcode) {
3524 case TILEMOVROWrte:
3525 case TILEMOVROWrti:
3526 return true;
3527 }
3528 return false;
3529}
3530
3531bool isVMINMAXPH(unsigned Opcode) {
3532 switch (Opcode) {
3533 case VMINMAXPHZ128rmbi:
3534 case VMINMAXPHZ128rmbik:
3535 case VMINMAXPHZ128rmbikz:
3536 case VMINMAXPHZ128rmi:
3537 case VMINMAXPHZ128rmik:
3538 case VMINMAXPHZ128rmikz:
3539 case VMINMAXPHZ128rri:
3540 case VMINMAXPHZ128rrik:
3541 case VMINMAXPHZ128rrikz:
3542 case VMINMAXPHZ256rmbi:
3543 case VMINMAXPHZ256rmbik:
3544 case VMINMAXPHZ256rmbikz:
3545 case VMINMAXPHZ256rmi:
3546 case VMINMAXPHZ256rmik:
3547 case VMINMAXPHZ256rmikz:
3548 case VMINMAXPHZ256rri:
3549 case VMINMAXPHZ256rrik:
3550 case VMINMAXPHZ256rrikz:
3551 case VMINMAXPHZrmbi:
3552 case VMINMAXPHZrmbik:
3553 case VMINMAXPHZrmbikz:
3554 case VMINMAXPHZrmi:
3555 case VMINMAXPHZrmik:
3556 case VMINMAXPHZrmikz:
3557 case VMINMAXPHZrri:
3558 case VMINMAXPHZrrib:
3559 case VMINMAXPHZrribk:
3560 case VMINMAXPHZrribkz:
3561 case VMINMAXPHZrrik:
3562 case VMINMAXPHZrrikz:
3563 return true;
3564 }
3565 return false;
3566}
3567
3568bool isVPMAXUB(unsigned Opcode) {
3569 switch (Opcode) {
3570 case VPMAXUBYrm:
3571 case VPMAXUBYrr:
3572 case VPMAXUBZ128rm:
3573 case VPMAXUBZ128rmk:
3574 case VPMAXUBZ128rmkz:
3575 case VPMAXUBZ128rr:
3576 case VPMAXUBZ128rrk:
3577 case VPMAXUBZ128rrkz:
3578 case VPMAXUBZ256rm:
3579 case VPMAXUBZ256rmk:
3580 case VPMAXUBZ256rmkz:
3581 case VPMAXUBZ256rr:
3582 case VPMAXUBZ256rrk:
3583 case VPMAXUBZ256rrkz:
3584 case VPMAXUBZrm:
3585 case VPMAXUBZrmk:
3586 case VPMAXUBZrmkz:
3587 case VPMAXUBZrr:
3588 case VPMAXUBZrrk:
3589 case VPMAXUBZrrkz:
3590 case VPMAXUBrm:
3591 case VPMAXUBrr:
3592 return true;
3593 }
3594 return false;
3595}
3596
3597bool isAAS(unsigned Opcode) {
3598 return Opcode == AAS;
3599}
3600
3601bool isFADD(unsigned Opcode) {
3602 switch (Opcode) {
3603 case ADD_F32m:
3604 case ADD_F64m:
3605 case ADD_FST0r:
3606 case ADD_FrST0:
3607 return true;
3608 }
3609 return false;
3610}
3611
3612bool isJMP(unsigned Opcode) {
3613 switch (Opcode) {
3614 case FARJMP32m:
3615 case JMP16m:
3616 case JMP16r:
3617 case JMP32m:
3618 case JMP32r:
3619 case JMP64m:
3620 case JMP64r:
3621 case JMP_1:
3622 case JMP_2:
3623 case JMP_4:
3624 return true;
3625 }
3626 return false;
3627}
3628
3629bool isXCRYPTECB(unsigned Opcode) {
3630 return Opcode == XCRYPTECB;
3631}
3632
3633bool isPFRCPIT1(unsigned Opcode) {
3634 switch (Opcode) {
3635 case PFRCPIT1rm:
3636 case PFRCPIT1rr:
3637 return true;
3638 }
3639 return false;
3640}
3641
3642bool isPMULHRW(unsigned Opcode) {
3643 switch (Opcode) {
3644 case PMULHRWrm:
3645 case PMULHRWrr:
3646 return true;
3647 }
3648 return false;
3649}
3650
3651bool isVCVTPH2PS(unsigned Opcode) {
3652 switch (Opcode) {
3653 case VCVTPH2PSYrm:
3654 case VCVTPH2PSYrr:
3655 case VCVTPH2PSZ128rm:
3656 case VCVTPH2PSZ128rmk:
3657 case VCVTPH2PSZ128rmkz:
3658 case VCVTPH2PSZ128rr:
3659 case VCVTPH2PSZ128rrk:
3660 case VCVTPH2PSZ128rrkz:
3661 case VCVTPH2PSZ256rm:
3662 case VCVTPH2PSZ256rmk:
3663 case VCVTPH2PSZ256rmkz:
3664 case VCVTPH2PSZ256rr:
3665 case VCVTPH2PSZ256rrk:
3666 case VCVTPH2PSZ256rrkz:
3667 case VCVTPH2PSZrm:
3668 case VCVTPH2PSZrmk:
3669 case VCVTPH2PSZrmkz:
3670 case VCVTPH2PSZrr:
3671 case VCVTPH2PSZrrb:
3672 case VCVTPH2PSZrrbk:
3673 case VCVTPH2PSZrrbkz:
3674 case VCVTPH2PSZrrk:
3675 case VCVTPH2PSZrrkz:
3676 case VCVTPH2PSrm:
3677 case VCVTPH2PSrr:
3678 return true;
3679 }
3680 return false;
3681}
3682
3683bool isVPBLENDVB(unsigned Opcode) {
3684 switch (Opcode) {
3685 case VPBLENDVBYrmr:
3686 case VPBLENDVBYrrr:
3687 case VPBLENDVBrmr:
3688 case VPBLENDVBrrr:
3689 return true;
3690 }
3691 return false;
3692}
3693
3694bool isPCMPESTRI(unsigned Opcode) {
3695 switch (Opcode) {
3696 case PCMPESTRIrmi:
3697 case PCMPESTRIrri:
3698 return true;
3699 }
3700 return false;
3701}
3702
3703bool isSENDUIPI(unsigned Opcode) {
3704 return Opcode == SENDUIPI;
3705}
3706
3707bool isFLDLN2(unsigned Opcode) {
3708 return Opcode == FLDLN2;
3709}
3710
3711bool isVPMACSWD(unsigned Opcode) {
3712 switch (Opcode) {
3713 case VPMACSWDrm:
3714 case VPMACSWDrr:
3715 return true;
3716 }
3717 return false;
3718}
3719
3720bool isSHA1MSG1(unsigned Opcode) {
3721 switch (Opcode) {
3722 case SHA1MSG1rm:
3723 case SHA1MSG1rr:
3724 return true;
3725 }
3726 return false;
3727}
3728
3729bool isVADDPS(unsigned Opcode) {
3730 switch (Opcode) {
3731 case VADDPSYrm:
3732 case VADDPSYrr:
3733 case VADDPSZ128rm:
3734 case VADDPSZ128rmb:
3735 case VADDPSZ128rmbk:
3736 case VADDPSZ128rmbkz:
3737 case VADDPSZ128rmk:
3738 case VADDPSZ128rmkz:
3739 case VADDPSZ128rr:
3740 case VADDPSZ128rrk:
3741 case VADDPSZ128rrkz:
3742 case VADDPSZ256rm:
3743 case VADDPSZ256rmb:
3744 case VADDPSZ256rmbk:
3745 case VADDPSZ256rmbkz:
3746 case VADDPSZ256rmk:
3747 case VADDPSZ256rmkz:
3748 case VADDPSZ256rr:
3749 case VADDPSZ256rrk:
3750 case VADDPSZ256rrkz:
3751 case VADDPSZrm:
3752 case VADDPSZrmb:
3753 case VADDPSZrmbk:
3754 case VADDPSZrmbkz:
3755 case VADDPSZrmk:
3756 case VADDPSZrmkz:
3757 case VADDPSZrr:
3758 case VADDPSZrrb:
3759 case VADDPSZrrbk:
3760 case VADDPSZrrbkz:
3761 case VADDPSZrrk:
3762 case VADDPSZrrkz:
3763 case VADDPSrm:
3764 case VADDPSrr:
3765 return true;
3766 }
3767 return false;
3768}
3769
3770bool isVCVTPS2DQ(unsigned Opcode) {
3771 switch (Opcode) {
3772 case VCVTPS2DQYrm:
3773 case VCVTPS2DQYrr:
3774 case VCVTPS2DQZ128rm:
3775 case VCVTPS2DQZ128rmb:
3776 case VCVTPS2DQZ128rmbk:
3777 case VCVTPS2DQZ128rmbkz:
3778 case VCVTPS2DQZ128rmk:
3779 case VCVTPS2DQZ128rmkz:
3780 case VCVTPS2DQZ128rr:
3781 case VCVTPS2DQZ128rrk:
3782 case VCVTPS2DQZ128rrkz:
3783 case VCVTPS2DQZ256rm:
3784 case VCVTPS2DQZ256rmb:
3785 case VCVTPS2DQZ256rmbk:
3786 case VCVTPS2DQZ256rmbkz:
3787 case VCVTPS2DQZ256rmk:
3788 case VCVTPS2DQZ256rmkz:
3789 case VCVTPS2DQZ256rr:
3790 case VCVTPS2DQZ256rrk:
3791 case VCVTPS2DQZ256rrkz:
3792 case VCVTPS2DQZrm:
3793 case VCVTPS2DQZrmb:
3794 case VCVTPS2DQZrmbk:
3795 case VCVTPS2DQZrmbkz:
3796 case VCVTPS2DQZrmk:
3797 case VCVTPS2DQZrmkz:
3798 case VCVTPS2DQZrr:
3799 case VCVTPS2DQZrrb:
3800 case VCVTPS2DQZrrbk:
3801 case VCVTPS2DQZrrbkz:
3802 case VCVTPS2DQZrrk:
3803 case VCVTPS2DQZrrkz:
3804 case VCVTPS2DQrm:
3805 case VCVTPS2DQrr:
3806 return true;
3807 }
3808 return false;
3809}
3810
3811bool isPFPNACC(unsigned Opcode) {
3812 switch (Opcode) {
3813 case PFPNACCrm:
3814 case PFPNACCrr:
3815 return true;
3816 }
3817 return false;
3818}
3819
3820bool isFMUL(unsigned Opcode) {
3821 switch (Opcode) {
3822 case MUL_F32m:
3823 case MUL_F64m:
3824 case MUL_FST0r:
3825 case MUL_FrST0:
3826 return true;
3827 }
3828 return false;
3829}
3830
3831bool isFNSAVE(unsigned Opcode) {
3832 return Opcode == FSAVEm;
3833}
3834
3835bool isCDQE(unsigned Opcode) {
3836 return Opcode == CDQE;
3837}
3838
3839bool isVPMACSDD(unsigned Opcode) {
3840 switch (Opcode) {
3841 case VPMACSDDrm:
3842 case VPMACSDDrr:
3843 return true;
3844 }
3845 return false;
3846}
3847
3848bool isVSQRTPS(unsigned Opcode) {
3849 switch (Opcode) {
3850 case VSQRTPSYm:
3851 case VSQRTPSYr:
3852 case VSQRTPSZ128m:
3853 case VSQRTPSZ128mb:
3854 case VSQRTPSZ128mbk:
3855 case VSQRTPSZ128mbkz:
3856 case VSQRTPSZ128mk:
3857 case VSQRTPSZ128mkz:
3858 case VSQRTPSZ128r:
3859 case VSQRTPSZ128rk:
3860 case VSQRTPSZ128rkz:
3861 case VSQRTPSZ256m:
3862 case VSQRTPSZ256mb:
3863 case VSQRTPSZ256mbk:
3864 case VSQRTPSZ256mbkz:
3865 case VSQRTPSZ256mk:
3866 case VSQRTPSZ256mkz:
3867 case VSQRTPSZ256r:
3868 case VSQRTPSZ256rk:
3869 case VSQRTPSZ256rkz:
3870 case VSQRTPSZm:
3871 case VSQRTPSZmb:
3872 case VSQRTPSZmbk:
3873 case VSQRTPSZmbkz:
3874 case VSQRTPSZmk:
3875 case VSQRTPSZmkz:
3876 case VSQRTPSZr:
3877 case VSQRTPSZrb:
3878 case VSQRTPSZrbk:
3879 case VSQRTPSZrbkz:
3880 case VSQRTPSZrk:
3881 case VSQRTPSZrkz:
3882 case VSQRTPSm:
3883 case VSQRTPSr:
3884 return true;
3885 }
3886 return false;
3887}
3888
3889bool isCMPSQ(unsigned Opcode) {
3890 return Opcode == CMPSQ;
3891}
3892
3893bool isVPSCATTERDD(unsigned Opcode) {
3894 switch (Opcode) {
3895 case VPSCATTERDDZ128mr:
3896 case VPSCATTERDDZ256mr:
3897 case VPSCATTERDDZmr:
3898 return true;
3899 }
3900 return false;
3901}
3902
3903bool isVCVTTSD2USIS(unsigned Opcode) {
3904 switch (Opcode) {
3905 case VCVTTSD2USI64Srm_Int:
3906 case VCVTTSD2USI64Srr_Int:
3907 case VCVTTSD2USI64Srrb_Int:
3908 case VCVTTSD2USISrm_Int:
3909 case VCVTTSD2USISrr_Int:
3910 case VCVTTSD2USISrrb_Int:
3911 return true;
3912 }
3913 return false;
3914}
3915
3916bool isVRNDSCALESD(unsigned Opcode) {
3917 switch (Opcode) {
3918 case VRNDSCALESDZrmi_Int:
3919 case VRNDSCALESDZrmik_Int:
3920 case VRNDSCALESDZrmikz_Int:
3921 case VRNDSCALESDZrri_Int:
3922 case VRNDSCALESDZrrib_Int:
3923 case VRNDSCALESDZrribk_Int:
3924 case VRNDSCALESDZrribkz_Int:
3925 case VRNDSCALESDZrrik_Int:
3926 case VRNDSCALESDZrrikz_Int:
3927 return true;
3928 }
3929 return false;
3930}
3931
3932bool isSUBPS(unsigned Opcode) {
3933 switch (Opcode) {
3934 case SUBPSrm:
3935 case SUBPSrr:
3936 return true;
3937 }
3938 return false;
3939}
3940
3941bool isVMAXSH(unsigned Opcode) {
3942 switch (Opcode) {
3943 case VMAXSHZrm_Int:
3944 case VMAXSHZrmk_Int:
3945 case VMAXSHZrmkz_Int:
3946 case VMAXSHZrr_Int:
3947 case VMAXSHZrrb_Int:
3948 case VMAXSHZrrbk_Int:
3949 case VMAXSHZrrbkz_Int:
3950 case VMAXSHZrrk_Int:
3951 case VMAXSHZrrkz_Int:
3952 return true;
3953 }
3954 return false;
3955}
3956
3957bool isFLDZ(unsigned Opcode) {
3958 return Opcode == LD_F0;
3959}
3960
3961bool isVFNMADD132SS(unsigned Opcode) {
3962 switch (Opcode) {
3963 case VFNMADD132SSZm_Int:
3964 case VFNMADD132SSZmk_Int:
3965 case VFNMADD132SSZmkz_Int:
3966 case VFNMADD132SSZr_Int:
3967 case VFNMADD132SSZrb_Int:
3968 case VFNMADD132SSZrbk_Int:
3969 case VFNMADD132SSZrbkz_Int:
3970 case VFNMADD132SSZrk_Int:
3971 case VFNMADD132SSZrkz_Int:
3972 case VFNMADD132SSm_Int:
3973 case VFNMADD132SSr_Int:
3974 return true;
3975 }
3976 return false;
3977}
3978
3979bool isLGDTW(unsigned Opcode) {
3980 return Opcode == LGDT16m;
3981}
3982
3983bool isTCVTROWPS2PHH(unsigned Opcode) {
3984 switch (Opcode) {
3985 case TCVTROWPS2PHHrte:
3986 case TCVTROWPS2PHHrti:
3987 return true;
3988 }
3989 return false;
3990}
3991
3992bool isINC(unsigned Opcode) {
3993 switch (Opcode) {
3994 case INC16m:
3995 case INC16m_EVEX:
3996 case INC16m_ND:
3997 case INC16m_NF:
3998 case INC16m_NF_ND:
3999 case INC16r:
4000 case INC16r_EVEX:
4001 case INC16r_ND:
4002 case INC16r_NF:
4003 case INC16r_NF_ND:
4004 case INC16r_alt:
4005 case INC32m:
4006 case INC32m_EVEX:
4007 case INC32m_ND:
4008 case INC32m_NF:
4009 case INC32m_NF_ND:
4010 case INC32r:
4011 case INC32r_EVEX:
4012 case INC32r_ND:
4013 case INC32r_NF:
4014 case INC32r_NF_ND:
4015 case INC32r_alt:
4016 case INC64m:
4017 case INC64m_EVEX:
4018 case INC64m_ND:
4019 case INC64m_NF:
4020 case INC64m_NF_ND:
4021 case INC64r:
4022 case INC64r_EVEX:
4023 case INC64r_ND:
4024 case INC64r_NF:
4025 case INC64r_NF_ND:
4026 case INC8m:
4027 case INC8m_EVEX:
4028 case INC8m_ND:
4029 case INC8m_NF:
4030 case INC8m_NF_ND:
4031 case INC8r:
4032 case INC8r_EVEX:
4033 case INC8r_ND:
4034 case INC8r_NF:
4035 case INC8r_NF_ND:
4036 return true;
4037 }
4038 return false;
4039}
4040
4041bool isVPANDN(unsigned Opcode) {
4042 switch (Opcode) {
4043 case VPANDNYrm:
4044 case VPANDNYrr:
4045 case VPANDNrm:
4046 case VPANDNrr:
4047 return true;
4048 }
4049 return false;
4050}
4051
4052bool isPABSB(unsigned Opcode) {
4053 switch (Opcode) {
4054 case MMX_PABSBrm:
4055 case MMX_PABSBrr:
4056 case PABSBrm:
4057 case PABSBrr:
4058 return true;
4059 }
4060 return false;
4061}
4062
4063bool isVSHA512RNDS2(unsigned Opcode) {
4064 return Opcode == VSHA512RNDS2rr;
4065}
4066
4067bool isPHADDSW(unsigned Opcode) {
4068 switch (Opcode) {
4069 case MMX_PHADDSWrm:
4070 case MMX_PHADDSWrr:
4071 case PHADDSWrm:
4072 case PHADDSWrr:
4073 return true;
4074 }
4075 return false;
4076}
4077
4078bool isVPMAXUD(unsigned Opcode) {
4079 switch (Opcode) {
4080 case VPMAXUDYrm:
4081 case VPMAXUDYrr:
4082 case VPMAXUDZ128rm:
4083 case VPMAXUDZ128rmb:
4084 case VPMAXUDZ128rmbk:
4085 case VPMAXUDZ128rmbkz:
4086 case VPMAXUDZ128rmk:
4087 case VPMAXUDZ128rmkz:
4088 case VPMAXUDZ128rr:
4089 case VPMAXUDZ128rrk:
4090 case VPMAXUDZ128rrkz:
4091 case VPMAXUDZ256rm:
4092 case VPMAXUDZ256rmb:
4093 case VPMAXUDZ256rmbk:
4094 case VPMAXUDZ256rmbkz:
4095 case VPMAXUDZ256rmk:
4096 case VPMAXUDZ256rmkz:
4097 case VPMAXUDZ256rr:
4098 case VPMAXUDZ256rrk:
4099 case VPMAXUDZ256rrkz:
4100 case VPMAXUDZrm:
4101 case VPMAXUDZrmb:
4102 case VPMAXUDZrmbk:
4103 case VPMAXUDZrmbkz:
4104 case VPMAXUDZrmk:
4105 case VPMAXUDZrmkz:
4106 case VPMAXUDZrr:
4107 case VPMAXUDZrrk:
4108 case VPMAXUDZrrkz:
4109 case VPMAXUDrm:
4110 case VPMAXUDrr:
4111 return true;
4112 }
4113 return false;
4114}
4115
4116bool isVPMOVSQW(unsigned Opcode) {
4117 switch (Opcode) {
4118 case VPMOVSQWZ128mr:
4119 case VPMOVSQWZ128mrk:
4120 case VPMOVSQWZ128rr:
4121 case VPMOVSQWZ128rrk:
4122 case VPMOVSQWZ128rrkz:
4123 case VPMOVSQWZ256mr:
4124 case VPMOVSQWZ256mrk:
4125 case VPMOVSQWZ256rr:
4126 case VPMOVSQWZ256rrk:
4127 case VPMOVSQWZ256rrkz:
4128 case VPMOVSQWZmr:
4129 case VPMOVSQWZmrk:
4130 case VPMOVSQWZrr:
4131 case VPMOVSQWZrrk:
4132 case VPMOVSQWZrrkz:
4133 return true;
4134 }
4135 return false;
4136}
4137
4138bool isADDSUBPS(unsigned Opcode) {
4139 switch (Opcode) {
4140 case ADDSUBPSrm:
4141 case ADDSUBPSrr:
4142 return true;
4143 }
4144 return false;
4145}
4146
4147bool isVPMACSSDQL(unsigned Opcode) {
4148 switch (Opcode) {
4149 case VPMACSSDQLrm:
4150 case VPMACSSDQLrr:
4151 return true;
4152 }
4153 return false;
4154}
4155
4156bool isPXOR(unsigned Opcode) {
4157 switch (Opcode) {
4158 case MMX_PXORrm:
4159 case MMX_PXORrr:
4160 case PXORrm:
4161 case PXORrr:
4162 return true;
4163 }
4164 return false;
4165}
4166
4167bool isVPSRAD(unsigned Opcode) {
4168 switch (Opcode) {
4169 case VPSRADYri:
4170 case VPSRADYrm:
4171 case VPSRADYrr:
4172 case VPSRADZ128mbi:
4173 case VPSRADZ128mbik:
4174 case VPSRADZ128mbikz:
4175 case VPSRADZ128mi:
4176 case VPSRADZ128mik:
4177 case VPSRADZ128mikz:
4178 case VPSRADZ128ri:
4179 case VPSRADZ128rik:
4180 case VPSRADZ128rikz:
4181 case VPSRADZ128rm:
4182 case VPSRADZ128rmk:
4183 case VPSRADZ128rmkz:
4184 case VPSRADZ128rr:
4185 case VPSRADZ128rrk:
4186 case VPSRADZ128rrkz:
4187 case VPSRADZ256mbi:
4188 case VPSRADZ256mbik:
4189 case VPSRADZ256mbikz:
4190 case VPSRADZ256mi:
4191 case VPSRADZ256mik:
4192 case VPSRADZ256mikz:
4193 case VPSRADZ256ri:
4194 case VPSRADZ256rik:
4195 case VPSRADZ256rikz:
4196 case VPSRADZ256rm:
4197 case VPSRADZ256rmk:
4198 case VPSRADZ256rmkz:
4199 case VPSRADZ256rr:
4200 case VPSRADZ256rrk:
4201 case VPSRADZ256rrkz:
4202 case VPSRADZmbi:
4203 case VPSRADZmbik:
4204 case VPSRADZmbikz:
4205 case VPSRADZmi:
4206 case VPSRADZmik:
4207 case VPSRADZmikz:
4208 case VPSRADZri:
4209 case VPSRADZrik:
4210 case VPSRADZrikz:
4211 case VPSRADZrm:
4212 case VPSRADZrmk:
4213 case VPSRADZrmkz:
4214 case VPSRADZrr:
4215 case VPSRADZrrk:
4216 case VPSRADZrrkz:
4217 case VPSRADri:
4218 case VPSRADrm:
4219 case VPSRADrr:
4220 return true;
4221 }
4222 return false;
4223}
4224
4225bool isVPSHAB(unsigned Opcode) {
4226 switch (Opcode) {
4227 case VPSHABmr:
4228 case VPSHABrm:
4229 case VPSHABrr:
4230 case VPSHABrr_REV:
4231 return true;
4232 }
4233 return false;
4234}
4235
4236bool isBTR(unsigned Opcode) {
4237 switch (Opcode) {
4238 case BTR16mi8:
4239 case BTR16mr:
4240 case BTR16ri8:
4241 case BTR16rr:
4242 case BTR32mi8:
4243 case BTR32mr:
4244 case BTR32ri8:
4245 case BTR32rr:
4246 case BTR64mi8:
4247 case BTR64mr:
4248 case BTR64ri8:
4249 case BTR64rr:
4250 return true;
4251 }
4252 return false;
4253}
4254
4255bool isKORW(unsigned Opcode) {
4256 return Opcode == KORWkk;
4257}
4258
4259bool isVRANGESS(unsigned Opcode) {
4260 switch (Opcode) {
4261 case VRANGESSZrmi:
4262 case VRANGESSZrmik:
4263 case VRANGESSZrmikz:
4264 case VRANGESSZrri:
4265 case VRANGESSZrrib:
4266 case VRANGESSZrribk:
4267 case VRANGESSZrribkz:
4268 case VRANGESSZrrik:
4269 case VRANGESSZrrikz:
4270 return true;
4271 }
4272 return false;
4273}
4274
4275bool isVCMPPS(unsigned Opcode) {
4276 switch (Opcode) {
4277 case VCMPPSYrmi:
4278 case VCMPPSYrri:
4279 case VCMPPSZ128rmbi:
4280 case VCMPPSZ128rmbik:
4281 case VCMPPSZ128rmi:
4282 case VCMPPSZ128rmik:
4283 case VCMPPSZ128rri:
4284 case VCMPPSZ128rrik:
4285 case VCMPPSZ256rmbi:
4286 case VCMPPSZ256rmbik:
4287 case VCMPPSZ256rmi:
4288 case VCMPPSZ256rmik:
4289 case VCMPPSZ256rri:
4290 case VCMPPSZ256rrik:
4291 case VCMPPSZrmbi:
4292 case VCMPPSZrmbik:
4293 case VCMPPSZrmi:
4294 case VCMPPSZrmik:
4295 case VCMPPSZrri:
4296 case VCMPPSZrrib:
4297 case VCMPPSZrribk:
4298 case VCMPPSZrrik:
4299 case VCMPPSrmi:
4300 case VCMPPSrri:
4301 return true;
4302 }
4303 return false;
4304}
4305
4306bool isVPLZCNTD(unsigned Opcode) {
4307 switch (Opcode) {
4308 case VPLZCNTDZ128rm:
4309 case VPLZCNTDZ128rmb:
4310 case VPLZCNTDZ128rmbk:
4311 case VPLZCNTDZ128rmbkz:
4312 case VPLZCNTDZ128rmk:
4313 case VPLZCNTDZ128rmkz:
4314 case VPLZCNTDZ128rr:
4315 case VPLZCNTDZ128rrk:
4316 case VPLZCNTDZ128rrkz:
4317 case VPLZCNTDZ256rm:
4318 case VPLZCNTDZ256rmb:
4319 case VPLZCNTDZ256rmbk:
4320 case VPLZCNTDZ256rmbkz:
4321 case VPLZCNTDZ256rmk:
4322 case VPLZCNTDZ256rmkz:
4323 case VPLZCNTDZ256rr:
4324 case VPLZCNTDZ256rrk:
4325 case VPLZCNTDZ256rrkz:
4326 case VPLZCNTDZrm:
4327 case VPLZCNTDZrmb:
4328 case VPLZCNTDZrmbk:
4329 case VPLZCNTDZrmbkz:
4330 case VPLZCNTDZrmk:
4331 case VPLZCNTDZrmkz:
4332 case VPLZCNTDZrr:
4333 case VPLZCNTDZrrk:
4334 case VPLZCNTDZrrkz:
4335 return true;
4336 }
4337 return false;
4338}
4339
4340bool isTDPBUUD(unsigned Opcode) {
4341 return Opcode == TDPBUUD;
4342}
4343
4344bool isROUNDPS(unsigned Opcode) {
4345 switch (Opcode) {
4346 case ROUNDPSmi:
4347 case ROUNDPSri:
4348 return true;
4349 }
4350 return false;
4351}
4352
4353bool isFABS(unsigned Opcode) {
4354 return Opcode == ABS_F;
4355}
4356
4357bool isSUBPD(unsigned Opcode) {
4358 switch (Opcode) {
4359 case SUBPDrm:
4360 case SUBPDrr:
4361 return true;
4362 }
4363 return false;
4364}
4365
4366bool isGF2P8MULB(unsigned Opcode) {
4367 switch (Opcode) {
4368 case GF2P8MULBrm:
4369 case GF2P8MULBrr:
4370 return true;
4371 }
4372 return false;
4373}
4374
4375bool isTZMSK(unsigned Opcode) {
4376 switch (Opcode) {
4377 case TZMSK32rm:
4378 case TZMSK32rr:
4379 case TZMSK64rm:
4380 case TZMSK64rr:
4381 return true;
4382 }
4383 return false;
4384}
4385
4386bool isVMINMAXSD(unsigned Opcode) {
4387 switch (Opcode) {
4388 case VMINMAXSDrmi_Int:
4389 case VMINMAXSDrmik_Int:
4390 case VMINMAXSDrmikz_Int:
4391 case VMINMAXSDrri_Int:
4392 case VMINMAXSDrrib_Int:
4393 case VMINMAXSDrribk_Int:
4394 case VMINMAXSDrribkz_Int:
4395 case VMINMAXSDrrik_Int:
4396 case VMINMAXSDrrikz_Int:
4397 return true;
4398 }
4399 return false;
4400}
4401
4402bool isANDPS(unsigned Opcode) {
4403 switch (Opcode) {
4404 case ANDPSrm:
4405 case ANDPSrr:
4406 return true;
4407 }
4408 return false;
4409}
4410
4411bool isVEXTRACTF32X8(unsigned Opcode) {
4412 switch (Opcode) {
4413 case VEXTRACTF32X8Zmri:
4414 case VEXTRACTF32X8Zmrik:
4415 case VEXTRACTF32X8Zrri:
4416 case VEXTRACTF32X8Zrrik:
4417 case VEXTRACTF32X8Zrrikz:
4418 return true;
4419 }
4420 return false;
4421}
4422
4423bool isSEAMRET(unsigned Opcode) {
4424 return Opcode == SEAMRET;
4425}
4426
4427bool isVPCOMW(unsigned Opcode) {
4428 switch (Opcode) {
4429 case VPCOMWmi:
4430 case VPCOMWri:
4431 return true;
4432 }
4433 return false;
4434}
4435
4436bool isVFIXUPIMMPD(unsigned Opcode) {
4437 switch (Opcode) {
4438 case VFIXUPIMMPDZ128rmbi:
4439 case VFIXUPIMMPDZ128rmbik:
4440 case VFIXUPIMMPDZ128rmbikz:
4441 case VFIXUPIMMPDZ128rmi:
4442 case VFIXUPIMMPDZ128rmik:
4443 case VFIXUPIMMPDZ128rmikz:
4444 case VFIXUPIMMPDZ128rri:
4445 case VFIXUPIMMPDZ128rrik:
4446 case VFIXUPIMMPDZ128rrikz:
4447 case VFIXUPIMMPDZ256rmbi:
4448 case VFIXUPIMMPDZ256rmbik:
4449 case VFIXUPIMMPDZ256rmbikz:
4450 case VFIXUPIMMPDZ256rmi:
4451 case VFIXUPIMMPDZ256rmik:
4452 case VFIXUPIMMPDZ256rmikz:
4453 case VFIXUPIMMPDZ256rri:
4454 case VFIXUPIMMPDZ256rrik:
4455 case VFIXUPIMMPDZ256rrikz:
4456 case VFIXUPIMMPDZrmbi:
4457 case VFIXUPIMMPDZrmbik:
4458 case VFIXUPIMMPDZrmbikz:
4459 case VFIXUPIMMPDZrmi:
4460 case VFIXUPIMMPDZrmik:
4461 case VFIXUPIMMPDZrmikz:
4462 case VFIXUPIMMPDZrri:
4463 case VFIXUPIMMPDZrrib:
4464 case VFIXUPIMMPDZrribk:
4465 case VFIXUPIMMPDZrribkz:
4466 case VFIXUPIMMPDZrrik:
4467 case VFIXUPIMMPDZrrikz:
4468 return true;
4469 }
4470 return false;
4471}
4472
4473bool isKANDND(unsigned Opcode) {
4474 return Opcode == KANDNDkk;
4475}
4476
4477bool isVMRESUME(unsigned Opcode) {
4478 return Opcode == VMRESUME;
4479}
4480
4481bool isCVTPD2DQ(unsigned Opcode) {
4482 switch (Opcode) {
4483 case CVTPD2DQrm:
4484 case CVTPD2DQrr:
4485 return true;
4486 }
4487 return false;
4488}
4489
4490bool isVFNMADD213PS(unsigned Opcode) {
4491 switch (Opcode) {
4492 case VFNMADD213PSYm:
4493 case VFNMADD213PSYr:
4494 case VFNMADD213PSZ128m:
4495 case VFNMADD213PSZ128mb:
4496 case VFNMADD213PSZ128mbk:
4497 case VFNMADD213PSZ128mbkz:
4498 case VFNMADD213PSZ128mk:
4499 case VFNMADD213PSZ128mkz:
4500 case VFNMADD213PSZ128r:
4501 case VFNMADD213PSZ128rk:
4502 case VFNMADD213PSZ128rkz:
4503 case VFNMADD213PSZ256m:
4504 case VFNMADD213PSZ256mb:
4505 case VFNMADD213PSZ256mbk:
4506 case VFNMADD213PSZ256mbkz:
4507 case VFNMADD213PSZ256mk:
4508 case VFNMADD213PSZ256mkz:
4509 case VFNMADD213PSZ256r:
4510 case VFNMADD213PSZ256rk:
4511 case VFNMADD213PSZ256rkz:
4512 case VFNMADD213PSZm:
4513 case VFNMADD213PSZmb:
4514 case VFNMADD213PSZmbk:
4515 case VFNMADD213PSZmbkz:
4516 case VFNMADD213PSZmk:
4517 case VFNMADD213PSZmkz:
4518 case VFNMADD213PSZr:
4519 case VFNMADD213PSZrb:
4520 case VFNMADD213PSZrbk:
4521 case VFNMADD213PSZrbkz:
4522 case VFNMADD213PSZrk:
4523 case VFNMADD213PSZrkz:
4524 case VFNMADD213PSm:
4525 case VFNMADD213PSr:
4526 return true;
4527 }
4528 return false;
4529}
4530
4531bool isVPEXTRD(unsigned Opcode) {
4532 switch (Opcode) {
4533 case VPEXTRDZmri:
4534 case VPEXTRDZrri:
4535 case VPEXTRDmri:
4536 case VPEXTRDrri:
4537 return true;
4538 }
4539 return false;
4540}
4541
4542bool isPACKUSWB(unsigned Opcode) {
4543 switch (Opcode) {
4544 case MMX_PACKUSWBrm:
4545 case MMX_PACKUSWBrr:
4546 case PACKUSWBrm:
4547 case PACKUSWBrr:
4548 return true;
4549 }
4550 return false;
4551}
4552
4553bool isVEXTRACTI32X8(unsigned Opcode) {
4554 switch (Opcode) {
4555 case VEXTRACTI32X8Zmri:
4556 case VEXTRACTI32X8Zmrik:
4557 case VEXTRACTI32X8Zrri:
4558 case VEXTRACTI32X8Zrrik:
4559 case VEXTRACTI32X8Zrrikz:
4560 return true;
4561 }
4562 return false;
4563}
4564
4565bool isVHADDPD(unsigned Opcode) {
4566 switch (Opcode) {
4567 case VHADDPDYrm:
4568 case VHADDPDYrr:
4569 case VHADDPDrm:
4570 case VHADDPDrr:
4571 return true;
4572 }
4573 return false;
4574}
4575
4576bool isVPSADBW(unsigned Opcode) {
4577 switch (Opcode) {
4578 case VPSADBWYrm:
4579 case VPSADBWYrr:
4580 case VPSADBWZ128rm:
4581 case VPSADBWZ128rr:
4582 case VPSADBWZ256rm:
4583 case VPSADBWZ256rr:
4584 case VPSADBWZrm:
4585 case VPSADBWZrr:
4586 case VPSADBWrm:
4587 case VPSADBWrr:
4588 return true;
4589 }
4590 return false;
4591}
4592
4593bool isMOVDQ2Q(unsigned Opcode) {
4594 return Opcode == MMX_MOVDQ2Qrr;
4595}
4596
4597bool isPUNPCKHBW(unsigned Opcode) {
4598 switch (Opcode) {
4599 case MMX_PUNPCKHBWrm:
4600 case MMX_PUNPCKHBWrr:
4601 case PUNPCKHBWrm:
4602 case PUNPCKHBWrr:
4603 return true;
4604 }
4605 return false;
4606}
4607
4608bool isXOR(unsigned Opcode) {
4609 switch (Opcode) {
4610 case XOR16i16:
4611 case XOR16mi:
4612 case XOR16mi8:
4613 case XOR16mi8_EVEX:
4614 case XOR16mi8_ND:
4615 case XOR16mi8_NF:
4616 case XOR16mi8_NF_ND:
4617 case XOR16mi_EVEX:
4618 case XOR16mi_ND:
4619 case XOR16mi_NF:
4620 case XOR16mi_NF_ND:
4621 case XOR16mr:
4622 case XOR16mr_EVEX:
4623 case XOR16mr_ND:
4624 case XOR16mr_NF:
4625 case XOR16mr_NF_ND:
4626 case XOR16ri:
4627 case XOR16ri8:
4628 case XOR16ri8_EVEX:
4629 case XOR16ri8_ND:
4630 case XOR16ri8_NF:
4631 case XOR16ri8_NF_ND:
4632 case XOR16ri_EVEX:
4633 case XOR16ri_ND:
4634 case XOR16ri_NF:
4635 case XOR16ri_NF_ND:
4636 case XOR16rm:
4637 case XOR16rm_EVEX:
4638 case XOR16rm_ND:
4639 case XOR16rm_NF:
4640 case XOR16rm_NF_ND:
4641 case XOR16rr:
4642 case XOR16rr_EVEX:
4643 case XOR16rr_EVEX_REV:
4644 case XOR16rr_ND:
4645 case XOR16rr_ND_REV:
4646 case XOR16rr_NF:
4647 case XOR16rr_NF_ND:
4648 case XOR16rr_NF_ND_REV:
4649 case XOR16rr_NF_REV:
4650 case XOR16rr_REV:
4651 case XOR32i32:
4652 case XOR32mi:
4653 case XOR32mi8:
4654 case XOR32mi8_EVEX:
4655 case XOR32mi8_ND:
4656 case XOR32mi8_NF:
4657 case XOR32mi8_NF_ND:
4658 case XOR32mi_EVEX:
4659 case XOR32mi_ND:
4660 case XOR32mi_NF:
4661 case XOR32mi_NF_ND:
4662 case XOR32mr:
4663 case XOR32mr_EVEX:
4664 case XOR32mr_ND:
4665 case XOR32mr_NF:
4666 case XOR32mr_NF_ND:
4667 case XOR32ri:
4668 case XOR32ri8:
4669 case XOR32ri8_EVEX:
4670 case XOR32ri8_ND:
4671 case XOR32ri8_NF:
4672 case XOR32ri8_NF_ND:
4673 case XOR32ri_EVEX:
4674 case XOR32ri_ND:
4675 case XOR32ri_NF:
4676 case XOR32ri_NF_ND:
4677 case XOR32rm:
4678 case XOR32rm_EVEX:
4679 case XOR32rm_ND:
4680 case XOR32rm_NF:
4681 case XOR32rm_NF_ND:
4682 case XOR32rr:
4683 case XOR32rr_EVEX:
4684 case XOR32rr_EVEX_REV:
4685 case XOR32rr_ND:
4686 case XOR32rr_ND_REV:
4687 case XOR32rr_NF:
4688 case XOR32rr_NF_ND:
4689 case XOR32rr_NF_ND_REV:
4690 case XOR32rr_NF_REV:
4691 case XOR32rr_REV:
4692 case XOR64i32:
4693 case XOR64mi32:
4694 case XOR64mi32_EVEX:
4695 case XOR64mi32_ND:
4696 case XOR64mi32_NF:
4697 case XOR64mi32_NF_ND:
4698 case XOR64mi8:
4699 case XOR64mi8_EVEX:
4700 case XOR64mi8_ND:
4701 case XOR64mi8_NF:
4702 case XOR64mi8_NF_ND:
4703 case XOR64mr:
4704 case XOR64mr_EVEX:
4705 case XOR64mr_ND:
4706 case XOR64mr_NF:
4707 case XOR64mr_NF_ND:
4708 case XOR64ri32:
4709 case XOR64ri32_EVEX:
4710 case XOR64ri32_ND:
4711 case XOR64ri32_NF:
4712 case XOR64ri32_NF_ND:
4713 case XOR64ri8:
4714 case XOR64ri8_EVEX:
4715 case XOR64ri8_ND:
4716 case XOR64ri8_NF:
4717 case XOR64ri8_NF_ND:
4718 case XOR64rm:
4719 case XOR64rm_EVEX:
4720 case XOR64rm_ND:
4721 case XOR64rm_NF:
4722 case XOR64rm_NF_ND:
4723 case XOR64rr:
4724 case XOR64rr_EVEX:
4725 case XOR64rr_EVEX_REV:
4726 case XOR64rr_ND:
4727 case XOR64rr_ND_REV:
4728 case XOR64rr_NF:
4729 case XOR64rr_NF_ND:
4730 case XOR64rr_NF_ND_REV:
4731 case XOR64rr_NF_REV:
4732 case XOR64rr_REV:
4733 case XOR8i8:
4734 case XOR8mi:
4735 case XOR8mi8:
4736 case XOR8mi_EVEX:
4737 case XOR8mi_ND:
4738 case XOR8mi_NF:
4739 case XOR8mi_NF_ND:
4740 case XOR8mr:
4741 case XOR8mr_EVEX:
4742 case XOR8mr_ND:
4743 case XOR8mr_NF:
4744 case XOR8mr_NF_ND:
4745 case XOR8ri:
4746 case XOR8ri8:
4747 case XOR8ri_EVEX:
4748 case XOR8ri_ND:
4749 case XOR8ri_NF:
4750 case XOR8ri_NF_ND:
4751 case XOR8rm:
4752 case XOR8rm_EVEX:
4753 case XOR8rm_ND:
4754 case XOR8rm_NF:
4755 case XOR8rm_NF_ND:
4756 case XOR8rr:
4757 case XOR8rr_EVEX:
4758 case XOR8rr_EVEX_REV:
4759 case XOR8rr_ND:
4760 case XOR8rr_ND_REV:
4761 case XOR8rr_NF:
4762 case XOR8rr_NF_ND:
4763 case XOR8rr_NF_ND_REV:
4764 case XOR8rr_NF_REV:
4765 case XOR8rr_REV:
4766 return true;
4767 }
4768 return false;
4769}
4770
4771bool isPSIGNB(unsigned Opcode) {
4772 switch (Opcode) {
4773 case MMX_PSIGNBrm:
4774 case MMX_PSIGNBrr:
4775 case PSIGNBrm:
4776 case PSIGNBrr:
4777 return true;
4778 }
4779 return false;
4780}
4781
4782bool isVPHADDSW(unsigned Opcode) {
4783 switch (Opcode) {
4784 case VPHADDSWYrm:
4785 case VPHADDSWYrr:
4786 case VPHADDSWrm:
4787 case VPHADDSWrr:
4788 return true;
4789 }
4790 return false;
4791}
4792
4793bool isFADDP(unsigned Opcode) {
4794 return Opcode == ADD_FPrST0;
4795}
4796
4797bool isNEG(unsigned Opcode) {
4798 switch (Opcode) {
4799 case NEG16m:
4800 case NEG16m_EVEX:
4801 case NEG16m_ND:
4802 case NEG16m_NF:
4803 case NEG16m_NF_ND:
4804 case NEG16r:
4805 case NEG16r_EVEX:
4806 case NEG16r_ND:
4807 case NEG16r_NF:
4808 case NEG16r_NF_ND:
4809 case NEG32m:
4810 case NEG32m_EVEX:
4811 case NEG32m_ND:
4812 case NEG32m_NF:
4813 case NEG32m_NF_ND:
4814 case NEG32r:
4815 case NEG32r_EVEX:
4816 case NEG32r_ND:
4817 case NEG32r_NF:
4818 case NEG32r_NF_ND:
4819 case NEG64m:
4820 case NEG64m_EVEX:
4821 case NEG64m_ND:
4822 case NEG64m_NF:
4823 case NEG64m_NF_ND:
4824 case NEG64r:
4825 case NEG64r_EVEX:
4826 case NEG64r_ND:
4827 case NEG64r_NF:
4828 case NEG64r_NF_ND:
4829 case NEG8m:
4830 case NEG8m_EVEX:
4831 case NEG8m_ND:
4832 case NEG8m_NF:
4833 case NEG8m_NF_ND:
4834 case NEG8r:
4835 case NEG8r_EVEX:
4836 case NEG8r_ND:
4837 case NEG8r_NF:
4838 case NEG8r_NF_ND:
4839 return true;
4840 }
4841 return false;
4842}
4843
4844bool isFLDLG2(unsigned Opcode) {
4845 return Opcode == FLDLG2;
4846}
4847
4848bool isFNOP(unsigned Opcode) {
4849 return Opcode == FNOP;
4850}
4851
4852bool isVMINSS(unsigned Opcode) {
4853 switch (Opcode) {
4854 case VMINSSZrm_Int:
4855 case VMINSSZrmk_Int:
4856 case VMINSSZrmkz_Int:
4857 case VMINSSZrr_Int:
4858 case VMINSSZrrb_Int:
4859 case VMINSSZrrbk_Int:
4860 case VMINSSZrrbkz_Int:
4861 case VMINSSZrrk_Int:
4862 case VMINSSZrrkz_Int:
4863 case VMINSSrm_Int:
4864 case VMINSSrr_Int:
4865 return true;
4866 }
4867 return false;
4868}
4869
4870bool isPCMPISTRM(unsigned Opcode) {
4871 switch (Opcode) {
4872 case PCMPISTRMrmi:
4873 case PCMPISTRMrri:
4874 return true;
4875 }
4876 return false;
4877}
4878
4879bool isVFMADD132SS(unsigned Opcode) {
4880 switch (Opcode) {
4881 case VFMADD132SSZm_Int:
4882 case VFMADD132SSZmk_Int:
4883 case VFMADD132SSZmkz_Int:
4884 case VFMADD132SSZr_Int:
4885 case VFMADD132SSZrb_Int:
4886 case VFMADD132SSZrbk_Int:
4887 case VFMADD132SSZrbkz_Int:
4888 case VFMADD132SSZrk_Int:
4889 case VFMADD132SSZrkz_Int:
4890 case VFMADD132SSm_Int:
4891 case VFMADD132SSr_Int:
4892 return true;
4893 }
4894 return false;
4895}
4896
4897bool isFDIVRP(unsigned Opcode) {
4898 return Opcode == DIVR_FPrST0;
4899}
4900
4901bool isPUSHAL(unsigned Opcode) {
4902 return Opcode == PUSHA32;
4903}
4904
4905bool isVPMACSDQL(unsigned Opcode) {
4906 switch (Opcode) {
4907 case VPMACSDQLrm:
4908 case VPMACSDQLrr:
4909 return true;
4910 }
4911 return false;
4912}
4913
4914bool isSUBSD(unsigned Opcode) {
4915 switch (Opcode) {
4916 case SUBSDrm_Int:
4917 case SUBSDrr_Int:
4918 return true;
4919 }
4920 return false;
4921}
4922
4923bool isVPBLENDMQ(unsigned Opcode) {
4924 switch (Opcode) {
4925 case VPBLENDMQZ128rm:
4926 case VPBLENDMQZ128rmb:
4927 case VPBLENDMQZ128rmbk:
4928 case VPBLENDMQZ128rmbkz:
4929 case VPBLENDMQZ128rmk:
4930 case VPBLENDMQZ128rmkz:
4931 case VPBLENDMQZ128rr:
4932 case VPBLENDMQZ128rrk:
4933 case VPBLENDMQZ128rrkz:
4934 case VPBLENDMQZ256rm:
4935 case VPBLENDMQZ256rmb:
4936 case VPBLENDMQZ256rmbk:
4937 case VPBLENDMQZ256rmbkz:
4938 case VPBLENDMQZ256rmk:
4939 case VPBLENDMQZ256rmkz:
4940 case VPBLENDMQZ256rr:
4941 case VPBLENDMQZ256rrk:
4942 case VPBLENDMQZ256rrkz:
4943 case VPBLENDMQZrm:
4944 case VPBLENDMQZrmb:
4945 case VPBLENDMQZrmbk:
4946 case VPBLENDMQZrmbkz:
4947 case VPBLENDMQZrmk:
4948 case VPBLENDMQZrmkz:
4949 case VPBLENDMQZrr:
4950 case VPBLENDMQZrrk:
4951 case VPBLENDMQZrrkz:
4952 return true;
4953 }
4954 return false;
4955}
4956
4957bool isVGATHERDPS(unsigned Opcode) {
4958 switch (Opcode) {
4959 case VGATHERDPSYrm:
4960 case VGATHERDPSZ128rm:
4961 case VGATHERDPSZ256rm:
4962 case VGATHERDPSZrm:
4963 case VGATHERDPSrm:
4964 return true;
4965 }
4966 return false;
4967}
4968
4969bool isSYSRET(unsigned Opcode) {
4970 return Opcode == SYSRET;
4971}
4972
4973bool isVPADDB(unsigned Opcode) {
4974 switch (Opcode) {
4975 case VPADDBYrm:
4976 case VPADDBYrr:
4977 case VPADDBZ128rm:
4978 case VPADDBZ128rmk:
4979 case VPADDBZ128rmkz:
4980 case VPADDBZ128rr:
4981 case VPADDBZ128rrk:
4982 case VPADDBZ128rrkz:
4983 case VPADDBZ256rm:
4984 case VPADDBZ256rmk:
4985 case VPADDBZ256rmkz:
4986 case VPADDBZ256rr:
4987 case VPADDBZ256rrk:
4988 case VPADDBZ256rrkz:
4989 case VPADDBZrm:
4990 case VPADDBZrmk:
4991 case VPADDBZrmkz:
4992 case VPADDBZrr:
4993 case VPADDBZrrk:
4994 case VPADDBZrrkz:
4995 case VPADDBrm:
4996 case VPADDBrr:
4997 return true;
4998 }
4999 return false;
5000}
5001
5002bool isXEND(unsigned Opcode) {
5003 return Opcode == XEND;
5004}
5005
5006bool isWRSSD(unsigned Opcode) {
5007 switch (Opcode) {
5008 case WRSSD:
5009 case WRSSD_EVEX:
5010 return true;
5011 }
5012 return false;
5013}
5014
5015bool isVMINMAXSS(unsigned Opcode) {
5016 switch (Opcode) {
5017 case VMINMAXSSrmi_Int:
5018 case VMINMAXSSrmik_Int:
5019 case VMINMAXSSrmikz_Int:
5020 case VMINMAXSSrri_Int:
5021 case VMINMAXSSrrib_Int:
5022 case VMINMAXSSrribk_Int:
5023 case VMINMAXSSrribkz_Int:
5024 case VMINMAXSSrrik_Int:
5025 case VMINMAXSSrrikz_Int:
5026 return true;
5027 }
5028 return false;
5029}
5030
5031bool isVCVTDQ2PH(unsigned Opcode) {
5032 switch (Opcode) {
5033 case VCVTDQ2PHZ128rm:
5034 case VCVTDQ2PHZ128rmb:
5035 case VCVTDQ2PHZ128rmbk:
5036 case VCVTDQ2PHZ128rmbkz:
5037 case VCVTDQ2PHZ128rmk:
5038 case VCVTDQ2PHZ128rmkz:
5039 case VCVTDQ2PHZ128rr:
5040 case VCVTDQ2PHZ128rrk:
5041 case VCVTDQ2PHZ128rrkz:
5042 case VCVTDQ2PHZ256rm:
5043 case VCVTDQ2PHZ256rmb:
5044 case VCVTDQ2PHZ256rmbk:
5045 case VCVTDQ2PHZ256rmbkz:
5046 case VCVTDQ2PHZ256rmk:
5047 case VCVTDQ2PHZ256rmkz:
5048 case VCVTDQ2PHZ256rr:
5049 case VCVTDQ2PHZ256rrk:
5050 case VCVTDQ2PHZ256rrkz:
5051 case VCVTDQ2PHZrm:
5052 case VCVTDQ2PHZrmb:
5053 case VCVTDQ2PHZrmbk:
5054 case VCVTDQ2PHZrmbkz:
5055 case VCVTDQ2PHZrmk:
5056 case VCVTDQ2PHZrmkz:
5057 case VCVTDQ2PHZrr:
5058 case VCVTDQ2PHZrrb:
5059 case VCVTDQ2PHZrrbk:
5060 case VCVTDQ2PHZrrbkz:
5061 case VCVTDQ2PHZrrk:
5062 case VCVTDQ2PHZrrkz:
5063 return true;
5064 }
5065 return false;
5066}
5067
5068bool isCVTPD2PS(unsigned Opcode) {
5069 switch (Opcode) {
5070 case CVTPD2PSrm:
5071 case CVTPD2PSrr:
5072 return true;
5073 }
5074 return false;
5075}
5076
5077bool isMAXPD(unsigned Opcode) {
5078 switch (Opcode) {
5079 case MAXPDrm:
5080 case MAXPDrr:
5081 return true;
5082 }
5083 return false;
5084}
5085
5086bool isRCPSS(unsigned Opcode) {
5087 switch (Opcode) {
5088 case RCPSSm_Int:
5089 case RCPSSr_Int:
5090 return true;
5091 }
5092 return false;
5093}
5094
5095bool isVMOVAPD(unsigned Opcode) {
5096 switch (Opcode) {
5097 case VMOVAPDYmr:
5098 case VMOVAPDYrm:
5099 case VMOVAPDYrr:
5100 case VMOVAPDYrr_REV:
5101 case VMOVAPDZ128mr:
5102 case VMOVAPDZ128mrk:
5103 case VMOVAPDZ128rm:
5104 case VMOVAPDZ128rmk:
5105 case VMOVAPDZ128rmkz:
5106 case VMOVAPDZ128rr:
5107 case VMOVAPDZ128rr_REV:
5108 case VMOVAPDZ128rrk:
5109 case VMOVAPDZ128rrk_REV:
5110 case VMOVAPDZ128rrkz:
5111 case VMOVAPDZ128rrkz_REV:
5112 case VMOVAPDZ256mr:
5113 case VMOVAPDZ256mrk:
5114 case VMOVAPDZ256rm:
5115 case VMOVAPDZ256rmk:
5116 case VMOVAPDZ256rmkz:
5117 case VMOVAPDZ256rr:
5118 case VMOVAPDZ256rr_REV:
5119 case VMOVAPDZ256rrk:
5120 case VMOVAPDZ256rrk_REV:
5121 case VMOVAPDZ256rrkz:
5122 case VMOVAPDZ256rrkz_REV:
5123 case VMOVAPDZmr:
5124 case VMOVAPDZmrk:
5125 case VMOVAPDZrm:
5126 case VMOVAPDZrmk:
5127 case VMOVAPDZrmkz:
5128 case VMOVAPDZrr:
5129 case VMOVAPDZrr_REV:
5130 case VMOVAPDZrrk:
5131 case VMOVAPDZrrk_REV:
5132 case VMOVAPDZrrkz:
5133 case VMOVAPDZrrkz_REV:
5134 case VMOVAPDmr:
5135 case VMOVAPDrm:
5136 case VMOVAPDrr:
5137 case VMOVAPDrr_REV:
5138 return true;
5139 }
5140 return false;
5141}
5142
5143bool isVPSUBSB(unsigned Opcode) {
5144 switch (Opcode) {
5145 case VPSUBSBYrm:
5146 case VPSUBSBYrr:
5147 case VPSUBSBZ128rm:
5148 case VPSUBSBZ128rmk:
5149 case VPSUBSBZ128rmkz:
5150 case VPSUBSBZ128rr:
5151 case VPSUBSBZ128rrk:
5152 case VPSUBSBZ128rrkz:
5153 case VPSUBSBZ256rm:
5154 case VPSUBSBZ256rmk:
5155 case VPSUBSBZ256rmkz:
5156 case VPSUBSBZ256rr:
5157 case VPSUBSBZ256rrk:
5158 case VPSUBSBZ256rrkz:
5159 case VPSUBSBZrm:
5160 case VPSUBSBZrmk:
5161 case VPSUBSBZrmkz:
5162 case VPSUBSBZrr:
5163 case VPSUBSBZrrk:
5164 case VPSUBSBZrrkz:
5165 case VPSUBSBrm:
5166 case VPSUBSBrr:
5167 return true;
5168 }
5169 return false;
5170}
5171
5172bool isRDTSC(unsigned Opcode) {
5173 return Opcode == RDTSC;
5174}
5175
5176bool isVCVTTPS2UDQS(unsigned Opcode) {
5177 switch (Opcode) {
5178 case VCVTTPS2UDQSZ128rm:
5179 case VCVTTPS2UDQSZ128rmb:
5180 case VCVTTPS2UDQSZ128rmbk:
5181 case VCVTTPS2UDQSZ128rmbkz:
5182 case VCVTTPS2UDQSZ128rmk:
5183 case VCVTTPS2UDQSZ128rmkz:
5184 case VCVTTPS2UDQSZ128rr:
5185 case VCVTTPS2UDQSZ128rrk:
5186 case VCVTTPS2UDQSZ128rrkz:
5187 case VCVTTPS2UDQSZ256rm:
5188 case VCVTTPS2UDQSZ256rmb:
5189 case VCVTTPS2UDQSZ256rmbk:
5190 case VCVTTPS2UDQSZ256rmbkz:
5191 case VCVTTPS2UDQSZ256rmk:
5192 case VCVTTPS2UDQSZ256rmkz:
5193 case VCVTTPS2UDQSZ256rr:
5194 case VCVTTPS2UDQSZ256rrk:
5195 case VCVTTPS2UDQSZ256rrkz:
5196 case VCVTTPS2UDQSZrm:
5197 case VCVTTPS2UDQSZrmb:
5198 case VCVTTPS2UDQSZrmbk:
5199 case VCVTTPS2UDQSZrmbkz:
5200 case VCVTTPS2UDQSZrmk:
5201 case VCVTTPS2UDQSZrmkz:
5202 case VCVTTPS2UDQSZrr:
5203 case VCVTTPS2UDQSZrrb:
5204 case VCVTTPS2UDQSZrrbk:
5205 case VCVTTPS2UDQSZrrbkz:
5206 case VCVTTPS2UDQSZrrk:
5207 case VCVTTPS2UDQSZrrkz:
5208 return true;
5209 }
5210 return false;
5211}
5212
5213bool isVPMADCSSWD(unsigned Opcode) {
5214 switch (Opcode) {
5215 case VPMADCSSWDrm:
5216 case VPMADCSSWDrr:
5217 return true;
5218 }
5219 return false;
5220}
5221
5222bool isVFNMADD213PH(unsigned Opcode) {
5223 switch (Opcode) {
5224 case VFNMADD213PHZ128m:
5225 case VFNMADD213PHZ128mb:
5226 case VFNMADD213PHZ128mbk:
5227 case VFNMADD213PHZ128mbkz:
5228 case VFNMADD213PHZ128mk:
5229 case VFNMADD213PHZ128mkz:
5230 case VFNMADD213PHZ128r:
5231 case VFNMADD213PHZ128rk:
5232 case VFNMADD213PHZ128rkz:
5233 case VFNMADD213PHZ256m:
5234 case VFNMADD213PHZ256mb:
5235 case VFNMADD213PHZ256mbk:
5236 case VFNMADD213PHZ256mbkz:
5237 case VFNMADD213PHZ256mk:
5238 case VFNMADD213PHZ256mkz:
5239 case VFNMADD213PHZ256r:
5240 case VFNMADD213PHZ256rk:
5241 case VFNMADD213PHZ256rkz:
5242 case VFNMADD213PHZm:
5243 case VFNMADD213PHZmb:
5244 case VFNMADD213PHZmbk:
5245 case VFNMADD213PHZmbkz:
5246 case VFNMADD213PHZmk:
5247 case VFNMADD213PHZmkz:
5248 case VFNMADD213PHZr:
5249 case VFNMADD213PHZrb:
5250 case VFNMADD213PHZrbk:
5251 case VFNMADD213PHZrbkz:
5252 case VFNMADD213PHZrk:
5253 case VFNMADD213PHZrkz:
5254 return true;
5255 }
5256 return false;
5257}
5258
5259bool isVGF2P8AFFINEQB(unsigned Opcode) {
5260 switch (Opcode) {
5261 case VGF2P8AFFINEQBYrmi:
5262 case VGF2P8AFFINEQBYrri:
5263 case VGF2P8AFFINEQBZ128rmbi:
5264 case VGF2P8AFFINEQBZ128rmbik:
5265 case VGF2P8AFFINEQBZ128rmbikz:
5266 case VGF2P8AFFINEQBZ128rmi:
5267 case VGF2P8AFFINEQBZ128rmik:
5268 case VGF2P8AFFINEQBZ128rmikz:
5269 case VGF2P8AFFINEQBZ128rri:
5270 case VGF2P8AFFINEQBZ128rrik:
5271 case VGF2P8AFFINEQBZ128rrikz:
5272 case VGF2P8AFFINEQBZ256rmbi:
5273 case VGF2P8AFFINEQBZ256rmbik:
5274 case VGF2P8AFFINEQBZ256rmbikz:
5275 case VGF2P8AFFINEQBZ256rmi:
5276 case VGF2P8AFFINEQBZ256rmik:
5277 case VGF2P8AFFINEQBZ256rmikz:
5278 case VGF2P8AFFINEQBZ256rri:
5279 case VGF2P8AFFINEQBZ256rrik:
5280 case VGF2P8AFFINEQBZ256rrikz:
5281 case VGF2P8AFFINEQBZrmbi:
5282 case VGF2P8AFFINEQBZrmbik:
5283 case VGF2P8AFFINEQBZrmbikz:
5284 case VGF2P8AFFINEQBZrmi:
5285 case VGF2P8AFFINEQBZrmik:
5286 case VGF2P8AFFINEQBZrmikz:
5287 case VGF2P8AFFINEQBZrri:
5288 case VGF2P8AFFINEQBZrrik:
5289 case VGF2P8AFFINEQBZrrikz:
5290 case VGF2P8AFFINEQBrmi:
5291 case VGF2P8AFFINEQBrri:
5292 return true;
5293 }
5294 return false;
5295}
5296
5297bool isPMOVZXWD(unsigned Opcode) {
5298 switch (Opcode) {
5299 case PMOVZXWDrm:
5300 case PMOVZXWDrr:
5301 return true;
5302 }
5303 return false;
5304}
5305
5306bool isPMINUD(unsigned Opcode) {
5307 switch (Opcode) {
5308 case PMINUDrm:
5309 case PMINUDrr:
5310 return true;
5311 }
5312 return false;
5313}
5314
5315bool isVCVTPH2UW(unsigned Opcode) {
5316 switch (Opcode) {
5317 case VCVTPH2UWZ128rm:
5318 case VCVTPH2UWZ128rmb:
5319 case VCVTPH2UWZ128rmbk:
5320 case VCVTPH2UWZ128rmbkz:
5321 case VCVTPH2UWZ128rmk:
5322 case VCVTPH2UWZ128rmkz:
5323 case VCVTPH2UWZ128rr:
5324 case VCVTPH2UWZ128rrk:
5325 case VCVTPH2UWZ128rrkz:
5326 case VCVTPH2UWZ256rm:
5327 case VCVTPH2UWZ256rmb:
5328 case VCVTPH2UWZ256rmbk:
5329 case VCVTPH2UWZ256rmbkz:
5330 case VCVTPH2UWZ256rmk:
5331 case VCVTPH2UWZ256rmkz:
5332 case VCVTPH2UWZ256rr:
5333 case VCVTPH2UWZ256rrk:
5334 case VCVTPH2UWZ256rrkz:
5335 case VCVTPH2UWZrm:
5336 case VCVTPH2UWZrmb:
5337 case VCVTPH2UWZrmbk:
5338 case VCVTPH2UWZrmbkz:
5339 case VCVTPH2UWZrmk:
5340 case VCVTPH2UWZrmkz:
5341 case VCVTPH2UWZrr:
5342 case VCVTPH2UWZrrb:
5343 case VCVTPH2UWZrrbk:
5344 case VCVTPH2UWZrrbkz:
5345 case VCVTPH2UWZrrk:
5346 case VCVTPH2UWZrrkz:
5347 return true;
5348 }
5349 return false;
5350}
5351
5352bool isPADDSW(unsigned Opcode) {
5353 switch (Opcode) {
5354 case MMX_PADDSWrm:
5355 case MMX_PADDSWrr:
5356 case PADDSWrm:
5357 case PADDSWrr:
5358 return true;
5359 }
5360 return false;
5361}
5362
5363bool isXSUSLDTRK(unsigned Opcode) {
5364 return Opcode == XSUSLDTRK;
5365}
5366
5367bool isLFENCE(unsigned Opcode) {
5368 return Opcode == LFENCE;
5369}
5370
5371bool isCRC32(unsigned Opcode) {
5372 switch (Opcode) {
5373 case CRC32r32m16:
5374 case CRC32r32m16_EVEX:
5375 case CRC32r32m32:
5376 case CRC32r32m32_EVEX:
5377 case CRC32r32m8:
5378 case CRC32r32m8_EVEX:
5379 case CRC32r32r16:
5380 case CRC32r32r16_EVEX:
5381 case CRC32r32r32:
5382 case CRC32r32r32_EVEX:
5383 case CRC32r32r8:
5384 case CRC32r32r8_EVEX:
5385 case CRC32r64m64:
5386 case CRC32r64m64_EVEX:
5387 case CRC32r64m8:
5388 case CRC32r64m8_EVEX:
5389 case CRC32r64r64:
5390 case CRC32r64r64_EVEX:
5391 case CRC32r64r8:
5392 case CRC32r64r8_EVEX:
5393 return true;
5394 }
5395 return false;
5396}
5397
5398bool isAESENCWIDE256KL(unsigned Opcode) {
5399 return Opcode == AESENCWIDE256KL;
5400}
5401
5402bool isMOVAPD(unsigned Opcode) {
5403 switch (Opcode) {
5404 case MOVAPDmr:
5405 case MOVAPDrm:
5406 case MOVAPDrr:
5407 case MOVAPDrr_REV:
5408 return true;
5409 }
5410 return false;
5411}
5412
5413bool isVFMADD213PS(unsigned Opcode) {
5414 switch (Opcode) {
5415 case VFMADD213PSYm:
5416 case VFMADD213PSYr:
5417 case VFMADD213PSZ128m:
5418 case VFMADD213PSZ128mb:
5419 case VFMADD213PSZ128mbk:
5420 case VFMADD213PSZ128mbkz:
5421 case VFMADD213PSZ128mk:
5422 case VFMADD213PSZ128mkz:
5423 case VFMADD213PSZ128r:
5424 case VFMADD213PSZ128rk:
5425 case VFMADD213PSZ128rkz:
5426 case VFMADD213PSZ256m:
5427 case VFMADD213PSZ256mb:
5428 case VFMADD213PSZ256mbk:
5429 case VFMADD213PSZ256mbkz:
5430 case VFMADD213PSZ256mk:
5431 case VFMADD213PSZ256mkz:
5432 case VFMADD213PSZ256r:
5433 case VFMADD213PSZ256rk:
5434 case VFMADD213PSZ256rkz:
5435 case VFMADD213PSZm:
5436 case VFMADD213PSZmb:
5437 case VFMADD213PSZmbk:
5438 case VFMADD213PSZmbkz:
5439 case VFMADD213PSZmk:
5440 case VFMADD213PSZmkz:
5441 case VFMADD213PSZr:
5442 case VFMADD213PSZrb:
5443 case VFMADD213PSZrbk:
5444 case VFMADD213PSZrbkz:
5445 case VFMADD213PSZrk:
5446 case VFMADD213PSZrkz:
5447 case VFMADD213PSm:
5448 case VFMADD213PSr:
5449 return true;
5450 }
5451 return false;
5452}
5453
5454bool isVPDPWUUDS(unsigned Opcode) {
5455 switch (Opcode) {
5456 case VPDPWUUDSYrm:
5457 case VPDPWUUDSYrr:
5458 case VPDPWUUDSZ128rm:
5459 case VPDPWUUDSZ128rmb:
5460 case VPDPWUUDSZ128rmbk:
5461 case VPDPWUUDSZ128rmbkz:
5462 case VPDPWUUDSZ128rmk:
5463 case VPDPWUUDSZ128rmkz:
5464 case VPDPWUUDSZ128rr:
5465 case VPDPWUUDSZ128rrk:
5466 case VPDPWUUDSZ128rrkz:
5467 case VPDPWUUDSZ256rm:
5468 case VPDPWUUDSZ256rmb:
5469 case VPDPWUUDSZ256rmbk:
5470 case VPDPWUUDSZ256rmbkz:
5471 case VPDPWUUDSZ256rmk:
5472 case VPDPWUUDSZ256rmkz:
5473 case VPDPWUUDSZ256rr:
5474 case VPDPWUUDSZ256rrk:
5475 case VPDPWUUDSZ256rrkz:
5476 case VPDPWUUDSZrm:
5477 case VPDPWUUDSZrmb:
5478 case VPDPWUUDSZrmbk:
5479 case VPDPWUUDSZrmbkz:
5480 case VPDPWUUDSZrmk:
5481 case VPDPWUUDSZrmkz:
5482 case VPDPWUUDSZrr:
5483 case VPDPWUUDSZrrk:
5484 case VPDPWUUDSZrrkz:
5485 case VPDPWUUDSrm:
5486 case VPDPWUUDSrr:
5487 return true;
5488 }
5489 return false;
5490}
5491
5492bool isMOVSLDUP(unsigned Opcode) {
5493 switch (Opcode) {
5494 case MOVSLDUPrm:
5495 case MOVSLDUPrr:
5496 return true;
5497 }
5498 return false;
5499}
5500
5501bool isCLDEMOTE(unsigned Opcode) {
5502 return Opcode == CLDEMOTE;
5503}
5504
5505bool isVFNMADD231PS(unsigned Opcode) {
5506 switch (Opcode) {
5507 case VFNMADD231PSYm:
5508 case VFNMADD231PSYr:
5509 case VFNMADD231PSZ128m:
5510 case VFNMADD231PSZ128mb:
5511 case VFNMADD231PSZ128mbk:
5512 case VFNMADD231PSZ128mbkz:
5513 case VFNMADD231PSZ128mk:
5514 case VFNMADD231PSZ128mkz:
5515 case VFNMADD231PSZ128r:
5516 case VFNMADD231PSZ128rk:
5517 case VFNMADD231PSZ128rkz:
5518 case VFNMADD231PSZ256m:
5519 case VFNMADD231PSZ256mb:
5520 case VFNMADD231PSZ256mbk:
5521 case VFNMADD231PSZ256mbkz:
5522 case VFNMADD231PSZ256mk:
5523 case VFNMADD231PSZ256mkz:
5524 case VFNMADD231PSZ256r:
5525 case VFNMADD231PSZ256rk:
5526 case VFNMADD231PSZ256rkz:
5527 case VFNMADD231PSZm:
5528 case VFNMADD231PSZmb:
5529 case VFNMADD231PSZmbk:
5530 case VFNMADD231PSZmbkz:
5531 case VFNMADD231PSZmk:
5532 case VFNMADD231PSZmkz:
5533 case VFNMADD231PSZr:
5534 case VFNMADD231PSZrb:
5535 case VFNMADD231PSZrbk:
5536 case VFNMADD231PSZrbkz:
5537 case VFNMADD231PSZrk:
5538 case VFNMADD231PSZrkz:
5539 case VFNMADD231PSm:
5540 case VFNMADD231PSr:
5541 return true;
5542 }
5543 return false;
5544}
5545
5546bool isVMOVMSKPD(unsigned Opcode) {
5547 switch (Opcode) {
5548 case VMOVMSKPDYrr:
5549 case VMOVMSKPDrr:
5550 return true;
5551 }
5552 return false;
5553}
5554
5555bool isPREFETCHT0(unsigned Opcode) {
5556 return Opcode == PREFETCHT0;
5557}
5558
5559bool isVCVTNEOBF162PS(unsigned Opcode) {
5560 switch (Opcode) {
5561 case VCVTNEOBF162PSYrm:
5562 case VCVTNEOBF162PSrm:
5563 return true;
5564 }
5565 return false;
5566}
5567
5568bool isVPCMPUD(unsigned Opcode) {
5569 switch (Opcode) {
5570 case VPCMPUDZ128rmbi:
5571 case VPCMPUDZ128rmbik:
5572 case VPCMPUDZ128rmi:
5573 case VPCMPUDZ128rmik:
5574 case VPCMPUDZ128rri:
5575 case VPCMPUDZ128rrik:
5576 case VPCMPUDZ256rmbi:
5577 case VPCMPUDZ256rmbik:
5578 case VPCMPUDZ256rmi:
5579 case VPCMPUDZ256rmik:
5580 case VPCMPUDZ256rri:
5581 case VPCMPUDZ256rrik:
5582 case VPCMPUDZrmbi:
5583 case VPCMPUDZrmbik:
5584 case VPCMPUDZrmi:
5585 case VPCMPUDZrmik:
5586 case VPCMPUDZrri:
5587 case VPCMPUDZrrik:
5588 return true;
5589 }
5590 return false;
5591}
5592
5593bool isVMAXSD(unsigned Opcode) {
5594 switch (Opcode) {
5595 case VMAXSDZrm_Int:
5596 case VMAXSDZrmk_Int:
5597 case VMAXSDZrmkz_Int:
5598 case VMAXSDZrr_Int:
5599 case VMAXSDZrrb_Int:
5600 case VMAXSDZrrbk_Int:
5601 case VMAXSDZrrbkz_Int:
5602 case VMAXSDZrrk_Int:
5603 case VMAXSDZrrkz_Int:
5604 case VMAXSDrm_Int:
5605 case VMAXSDrr_Int:
5606 return true;
5607 }
5608 return false;
5609}
5610
5611bool isVRCP28SD(unsigned Opcode) {
5612 switch (Opcode) {
5613 case VRCP28SDZm:
5614 case VRCP28SDZmk:
5615 case VRCP28SDZmkz:
5616 case VRCP28SDZr:
5617 case VRCP28SDZrb:
5618 case VRCP28SDZrbk:
5619 case VRCP28SDZrbkz:
5620 case VRCP28SDZrk:
5621 case VRCP28SDZrkz:
5622 return true;
5623 }
5624 return false;
5625}
5626
5627bool isVMAXPS(unsigned Opcode) {
5628 switch (Opcode) {
5629 case VMAXPSYrm:
5630 case VMAXPSYrr:
5631 case VMAXPSZ128rm:
5632 case VMAXPSZ128rmb:
5633 case VMAXPSZ128rmbk:
5634 case VMAXPSZ128rmbkz:
5635 case VMAXPSZ128rmk:
5636 case VMAXPSZ128rmkz:
5637 case VMAXPSZ128rr:
5638 case VMAXPSZ128rrk:
5639 case VMAXPSZ128rrkz:
5640 case VMAXPSZ256rm:
5641 case VMAXPSZ256rmb:
5642 case VMAXPSZ256rmbk:
5643 case VMAXPSZ256rmbkz:
5644 case VMAXPSZ256rmk:
5645 case VMAXPSZ256rmkz:
5646 case VMAXPSZ256rr:
5647 case VMAXPSZ256rrk:
5648 case VMAXPSZ256rrkz:
5649 case VMAXPSZrm:
5650 case VMAXPSZrmb:
5651 case VMAXPSZrmbk:
5652 case VMAXPSZrmbkz:
5653 case VMAXPSZrmk:
5654 case VMAXPSZrmkz:
5655 case VMAXPSZrr:
5656 case VMAXPSZrrb:
5657 case VMAXPSZrrbk:
5658 case VMAXPSZrrbkz:
5659 case VMAXPSZrrk:
5660 case VMAXPSZrrkz:
5661 case VMAXPSrm:
5662 case VMAXPSrr:
5663 return true;
5664 }
5665 return false;
5666}
5667
5668bool isVPMOVD2M(unsigned Opcode) {
5669 switch (Opcode) {
5670 case VPMOVD2MZ128kr:
5671 case VPMOVD2MZ256kr:
5672 case VPMOVD2MZkr:
5673 return true;
5674 }
5675 return false;
5676}
5677
5678bool isVPMACSSWD(unsigned Opcode) {
5679 switch (Opcode) {
5680 case VPMACSSWDrm:
5681 case VPMACSSWDrr:
5682 return true;
5683 }
5684 return false;
5685}
5686
5687bool isVUCOMISD(unsigned Opcode) {
5688 switch (Opcode) {
5689 case VUCOMISDZrm:
5690 case VUCOMISDZrr:
5691 case VUCOMISDZrrb:
5692 case VUCOMISDrm:
5693 case VUCOMISDrr:
5694 return true;
5695 }
5696 return false;
5697}
5698
5699bool isLTR(unsigned Opcode) {
5700 switch (Opcode) {
5701 case LTRm:
5702 case LTRr:
5703 return true;
5704 }
5705 return false;
5706}
5707
5708bool isVCVTUSI2SH(unsigned Opcode) {
5709 switch (Opcode) {
5710 case VCVTUSI2SHZrm_Int:
5711 case VCVTUSI2SHZrr_Int:
5712 case VCVTUSI2SHZrrb_Int:
5713 case VCVTUSI642SHZrm_Int:
5714 case VCVTUSI642SHZrr_Int:
5715 case VCVTUSI642SHZrrb_Int:
5716 return true;
5717 }
5718 return false;
5719}
5720
5721bool isVSCATTERPF1QPS(unsigned Opcode) {
5722 return Opcode == VSCATTERPF1QPSm;
5723}
5724
5725bool isWRGSBASE(unsigned Opcode) {
5726 switch (Opcode) {
5727 case WRGSBASE:
5728 case WRGSBASE64:
5729 return true;
5730 }
5731 return false;
5732}
5733
5734bool isSTOSQ(unsigned Opcode) {
5735 return Opcode == STOSQ;
5736}
5737
5738bool isVSQRTSD(unsigned Opcode) {
5739 switch (Opcode) {
5740 case VSQRTSDZm_Int:
5741 case VSQRTSDZmk_Int:
5742 case VSQRTSDZmkz_Int:
5743 case VSQRTSDZr_Int:
5744 case VSQRTSDZrb_Int:
5745 case VSQRTSDZrbk_Int:
5746 case VSQRTSDZrbkz_Int:
5747 case VSQRTSDZrk_Int:
5748 case VSQRTSDZrkz_Int:
5749 case VSQRTSDm_Int:
5750 case VSQRTSDr_Int:
5751 return true;
5752 }
5753 return false;
5754}
5755
5756bool isVPERMIL2PD(unsigned Opcode) {
5757 switch (Opcode) {
5758 case VPERMIL2PDYmr:
5759 case VPERMIL2PDYrm:
5760 case VPERMIL2PDYrr:
5761 case VPERMIL2PDYrr_REV:
5762 case VPERMIL2PDmr:
5763 case VPERMIL2PDrm:
5764 case VPERMIL2PDrr:
5765 case VPERMIL2PDrr_REV:
5766 return true;
5767 }
5768 return false;
5769}
5770
5771bool isVFCMADDCSH(unsigned Opcode) {
5772 switch (Opcode) {
5773 case VFCMADDCSHZm:
5774 case VFCMADDCSHZmk:
5775 case VFCMADDCSHZmkz:
5776 case VFCMADDCSHZr:
5777 case VFCMADDCSHZrb:
5778 case VFCMADDCSHZrbk:
5779 case VFCMADDCSHZrbkz:
5780 case VFCMADDCSHZrk:
5781 case VFCMADDCSHZrkz:
5782 return true;
5783 }
5784 return false;
5785}
5786
5787bool isVFMADDSUB213PS(unsigned Opcode) {
5788 switch (Opcode) {
5789 case VFMADDSUB213PSYm:
5790 case VFMADDSUB213PSYr:
5791 case VFMADDSUB213PSZ128m:
5792 case VFMADDSUB213PSZ128mb:
5793 case VFMADDSUB213PSZ128mbk:
5794 case VFMADDSUB213PSZ128mbkz:
5795 case VFMADDSUB213PSZ128mk:
5796 case VFMADDSUB213PSZ128mkz:
5797 case VFMADDSUB213PSZ128r:
5798 case VFMADDSUB213PSZ128rk:
5799 case VFMADDSUB213PSZ128rkz:
5800 case VFMADDSUB213PSZ256m:
5801 case VFMADDSUB213PSZ256mb:
5802 case VFMADDSUB213PSZ256mbk:
5803 case VFMADDSUB213PSZ256mbkz:
5804 case VFMADDSUB213PSZ256mk:
5805 case VFMADDSUB213PSZ256mkz:
5806 case VFMADDSUB213PSZ256r:
5807 case VFMADDSUB213PSZ256rk:
5808 case VFMADDSUB213PSZ256rkz:
5809 case VFMADDSUB213PSZm:
5810 case VFMADDSUB213PSZmb:
5811 case VFMADDSUB213PSZmbk:
5812 case VFMADDSUB213PSZmbkz:
5813 case VFMADDSUB213PSZmk:
5814 case VFMADDSUB213PSZmkz:
5815 case VFMADDSUB213PSZr:
5816 case VFMADDSUB213PSZrb:
5817 case VFMADDSUB213PSZrbk:
5818 case VFMADDSUB213PSZrbkz:
5819 case VFMADDSUB213PSZrk:
5820 case VFMADDSUB213PSZrkz:
5821 case VFMADDSUB213PSm:
5822 case VFMADDSUB213PSr:
5823 return true;
5824 }
5825 return false;
5826}
5827
5828bool isPFSUB(unsigned Opcode) {
5829 switch (Opcode) {
5830 case PFSUBrm:
5831 case PFSUBrr:
5832 return true;
5833 }
5834 return false;
5835}
5836
5837bool isVSQRTSS(unsigned Opcode) {
5838 switch (Opcode) {
5839 case VSQRTSSZm_Int:
5840 case VSQRTSSZmk_Int:
5841 case VSQRTSSZmkz_Int:
5842 case VSQRTSSZr_Int:
5843 case VSQRTSSZrb_Int:
5844 case VSQRTSSZrbk_Int:
5845 case VSQRTSSZrbkz_Int:
5846 case VSQRTSSZrk_Int:
5847 case VSQRTSSZrkz_Int:
5848 case VSQRTSSm_Int:
5849 case VSQRTSSr_Int:
5850 return true;
5851 }
5852 return false;
5853}
5854
5855bool isVEXPANDPS(unsigned Opcode) {
5856 switch (Opcode) {
5857 case VEXPANDPSZ128rm:
5858 case VEXPANDPSZ128rmk:
5859 case VEXPANDPSZ128rmkz:
5860 case VEXPANDPSZ128rr:
5861 case VEXPANDPSZ128rrk:
5862 case VEXPANDPSZ128rrkz:
5863 case VEXPANDPSZ256rm:
5864 case VEXPANDPSZ256rmk:
5865 case VEXPANDPSZ256rmkz:
5866 case VEXPANDPSZ256rr:
5867 case VEXPANDPSZ256rrk:
5868 case VEXPANDPSZ256rrkz:
5869 case VEXPANDPSZrm:
5870 case VEXPANDPSZrmk:
5871 case VEXPANDPSZrmkz:
5872 case VEXPANDPSZrr:
5873 case VEXPANDPSZrrk:
5874 case VEXPANDPSZrrkz:
5875 return true;
5876 }
5877 return false;
5878}
5879
5880bool isVPCOMPRESSW(unsigned Opcode) {
5881 switch (Opcode) {
5882 case VPCOMPRESSWZ128mr:
5883 case VPCOMPRESSWZ128mrk:
5884 case VPCOMPRESSWZ128rr:
5885 case VPCOMPRESSWZ128rrk:
5886 case VPCOMPRESSWZ128rrkz:
5887 case VPCOMPRESSWZ256mr:
5888 case VPCOMPRESSWZ256mrk:
5889 case VPCOMPRESSWZ256rr:
5890 case VPCOMPRESSWZ256rrk:
5891 case VPCOMPRESSWZ256rrkz:
5892 case VPCOMPRESSWZmr:
5893 case VPCOMPRESSWZmrk:
5894 case VPCOMPRESSWZrr:
5895 case VPCOMPRESSWZrrk:
5896 case VPCOMPRESSWZrrkz:
5897 return true;
5898 }
5899 return false;
5900}
5901
5902bool isPEXTRD(unsigned Opcode) {
5903 switch (Opcode) {
5904 case PEXTRDmri:
5905 case PEXTRDrri:
5906 return true;
5907 }
5908 return false;
5909}
5910
5911bool isVCVTTPS2UQQS(unsigned Opcode) {
5912 switch (Opcode) {
5913 case VCVTTPS2UQQSZ128rm:
5914 case VCVTTPS2UQQSZ128rmb:
5915 case VCVTTPS2UQQSZ128rmbk:
5916 case VCVTTPS2UQQSZ128rmbkz:
5917 case VCVTTPS2UQQSZ128rmk:
5918 case VCVTTPS2UQQSZ128rmkz:
5919 case VCVTTPS2UQQSZ128rr:
5920 case VCVTTPS2UQQSZ128rrk:
5921 case VCVTTPS2UQQSZ128rrkz:
5922 case VCVTTPS2UQQSZ256rm:
5923 case VCVTTPS2UQQSZ256rmb:
5924 case VCVTTPS2UQQSZ256rmbk:
5925 case VCVTTPS2UQQSZ256rmbkz:
5926 case VCVTTPS2UQQSZ256rmk:
5927 case VCVTTPS2UQQSZ256rmkz:
5928 case VCVTTPS2UQQSZ256rr:
5929 case VCVTTPS2UQQSZ256rrb:
5930 case VCVTTPS2UQQSZ256rrbk:
5931 case VCVTTPS2UQQSZ256rrbkz:
5932 case VCVTTPS2UQQSZ256rrk:
5933 case VCVTTPS2UQQSZ256rrkz:
5934 case VCVTTPS2UQQSZrm:
5935 case VCVTTPS2UQQSZrmb:
5936 case VCVTTPS2UQQSZrmbk:
5937 case VCVTTPS2UQQSZrmbkz:
5938 case VCVTTPS2UQQSZrmk:
5939 case VCVTTPS2UQQSZrmkz:
5940 case VCVTTPS2UQQSZrr:
5941 case VCVTTPS2UQQSZrrb:
5942 case VCVTTPS2UQQSZrrbk:
5943 case VCVTTPS2UQQSZrrbkz:
5944 case VCVTTPS2UQQSZrrk:
5945 case VCVTTPS2UQQSZrrkz:
5946 return true;
5947 }
5948 return false;
5949}
5950
5951bool isSYSEXITQ(unsigned Opcode) {
5952 return Opcode == SYSEXIT64;
5953}
5954
5955bool isROUNDSD(unsigned Opcode) {
5956 switch (Opcode) {
5957 case ROUNDSDmi_Int:
5958 case ROUNDSDri_Int:
5959 return true;
5960 }
5961 return false;
5962}
5963
5964bool isVFMADD132BF16(unsigned Opcode) {
5965 switch (Opcode) {
5966 case VFMADD132BF16Z128m:
5967 case VFMADD132BF16Z128mb:
5968 case VFMADD132BF16Z128mbk:
5969 case VFMADD132BF16Z128mbkz:
5970 case VFMADD132BF16Z128mk:
5971 case VFMADD132BF16Z128mkz:
5972 case VFMADD132BF16Z128r:
5973 case VFMADD132BF16Z128rk:
5974 case VFMADD132BF16Z128rkz:
5975 case VFMADD132BF16Z256m:
5976 case VFMADD132BF16Z256mb:
5977 case VFMADD132BF16Z256mbk:
5978 case VFMADD132BF16Z256mbkz:
5979 case VFMADD132BF16Z256mk:
5980 case VFMADD132BF16Z256mkz:
5981 case VFMADD132BF16Z256r:
5982 case VFMADD132BF16Z256rk:
5983 case VFMADD132BF16Z256rkz:
5984 case VFMADD132BF16Zm:
5985 case VFMADD132BF16Zmb:
5986 case VFMADD132BF16Zmbk:
5987 case VFMADD132BF16Zmbkz:
5988 case VFMADD132BF16Zmk:
5989 case VFMADD132BF16Zmkz:
5990 case VFMADD132BF16Zr:
5991 case VFMADD132BF16Zrk:
5992 case VFMADD132BF16Zrkz:
5993 return true;
5994 }
5995 return false;
5996}
5997
5998bool isFCOM(unsigned Opcode) {
5999 switch (Opcode) {
6000 case COM_FST0r:
6001 case FCOM32m:
6002 case FCOM64m:
6003 return true;
6004 }
6005 return false;
6006}
6007
6008bool isVFNMSUBSS(unsigned Opcode) {
6009 switch (Opcode) {
6010 case VFNMSUBSS4mr:
6011 case VFNMSUBSS4rm:
6012 case VFNMSUBSS4rr:
6013 case VFNMSUBSS4rr_REV:
6014 return true;
6015 }
6016 return false;
6017}
6018
6019bool isKSHIFTLW(unsigned Opcode) {
6020 return Opcode == KSHIFTLWki;
6021}
6022
6023bool isSCASD(unsigned Opcode) {
6024 return Opcode == SCASL;
6025}
6026
6027bool isVMPTRLD(unsigned Opcode) {
6028 return Opcode == VMPTRLDm;
6029}
6030
6031bool isVAESDECLAST(unsigned Opcode) {
6032 switch (Opcode) {
6033 case VAESDECLASTYrm:
6034 case VAESDECLASTYrr:
6035 case VAESDECLASTZ128rm:
6036 case VAESDECLASTZ128rr:
6037 case VAESDECLASTZ256rm:
6038 case VAESDECLASTZ256rr:
6039 case VAESDECLASTZrm:
6040 case VAESDECLASTZrr:
6041 case VAESDECLASTrm:
6042 case VAESDECLASTrr:
6043 return true;
6044 }
6045 return false;
6046}
6047
6048bool isVFMADDSUBPS(unsigned Opcode) {
6049 switch (Opcode) {
6050 case VFMADDSUBPS4Ymr:
6051 case VFMADDSUBPS4Yrm:
6052 case VFMADDSUBPS4Yrr:
6053 case VFMADDSUBPS4Yrr_REV:
6054 case VFMADDSUBPS4mr:
6055 case VFMADDSUBPS4rm:
6056 case VFMADDSUBPS4rr:
6057 case VFMADDSUBPS4rr_REV:
6058 return true;
6059 }
6060 return false;
6061}
6062
6063bool isVCVTUQQ2PS(unsigned Opcode) {
6064 switch (Opcode) {
6065 case VCVTUQQ2PSZ128rm:
6066 case VCVTUQQ2PSZ128rmb:
6067 case VCVTUQQ2PSZ128rmbk:
6068 case VCVTUQQ2PSZ128rmbkz:
6069 case VCVTUQQ2PSZ128rmk:
6070 case VCVTUQQ2PSZ128rmkz:
6071 case VCVTUQQ2PSZ128rr:
6072 case VCVTUQQ2PSZ128rrk:
6073 case VCVTUQQ2PSZ128rrkz:
6074 case VCVTUQQ2PSZ256rm:
6075 case VCVTUQQ2PSZ256rmb:
6076 case VCVTUQQ2PSZ256rmbk:
6077 case VCVTUQQ2PSZ256rmbkz:
6078 case VCVTUQQ2PSZ256rmk:
6079 case VCVTUQQ2PSZ256rmkz:
6080 case VCVTUQQ2PSZ256rr:
6081 case VCVTUQQ2PSZ256rrk:
6082 case VCVTUQQ2PSZ256rrkz:
6083 case VCVTUQQ2PSZrm:
6084 case VCVTUQQ2PSZrmb:
6085 case VCVTUQQ2PSZrmbk:
6086 case VCVTUQQ2PSZrmbkz:
6087 case VCVTUQQ2PSZrmk:
6088 case VCVTUQQ2PSZrmkz:
6089 case VCVTUQQ2PSZrr:
6090 case VCVTUQQ2PSZrrb:
6091 case VCVTUQQ2PSZrrbk:
6092 case VCVTUQQ2PSZrrbkz:
6093 case VCVTUQQ2PSZrrk:
6094 case VCVTUQQ2PSZrrkz:
6095 return true;
6096 }
6097 return false;
6098}
6099
6100bool isVPMOVUSDB(unsigned Opcode) {
6101 switch (Opcode) {
6102 case VPMOVUSDBZ128mr:
6103 case VPMOVUSDBZ128mrk:
6104 case VPMOVUSDBZ128rr:
6105 case VPMOVUSDBZ128rrk:
6106 case VPMOVUSDBZ128rrkz:
6107 case VPMOVUSDBZ256mr:
6108 case VPMOVUSDBZ256mrk:
6109 case VPMOVUSDBZ256rr:
6110 case VPMOVUSDBZ256rrk:
6111 case VPMOVUSDBZ256rrkz:
6112 case VPMOVUSDBZmr:
6113 case VPMOVUSDBZmrk:
6114 case VPMOVUSDBZrr:
6115 case VPMOVUSDBZrrk:
6116 case VPMOVUSDBZrrkz:
6117 return true;
6118 }
6119 return false;
6120}
6121
6122bool isVPROTW(unsigned Opcode) {
6123 switch (Opcode) {
6124 case VPROTWmi:
6125 case VPROTWmr:
6126 case VPROTWri:
6127 case VPROTWrm:
6128 case VPROTWrr:
6129 case VPROTWrr_REV:
6130 return true;
6131 }
6132 return false;
6133}
6134
6135bool isVDPPS(unsigned Opcode) {
6136 switch (Opcode) {
6137 case VDPPSYrmi:
6138 case VDPPSYrri:
6139 case VDPPSrmi:
6140 case VDPPSrri:
6141 return true;
6142 }
6143 return false;
6144}
6145
6146bool isVRSQRT14PD(unsigned Opcode) {
6147 switch (Opcode) {
6148 case VRSQRT14PDZ128m:
6149 case VRSQRT14PDZ128mb:
6150 case VRSQRT14PDZ128mbk:
6151 case VRSQRT14PDZ128mbkz:
6152 case VRSQRT14PDZ128mk:
6153 case VRSQRT14PDZ128mkz:
6154 case VRSQRT14PDZ128r:
6155 case VRSQRT14PDZ128rk:
6156 case VRSQRT14PDZ128rkz:
6157 case VRSQRT14PDZ256m:
6158 case VRSQRT14PDZ256mb:
6159 case VRSQRT14PDZ256mbk:
6160 case VRSQRT14PDZ256mbkz:
6161 case VRSQRT14PDZ256mk:
6162 case VRSQRT14PDZ256mkz:
6163 case VRSQRT14PDZ256r:
6164 case VRSQRT14PDZ256rk:
6165 case VRSQRT14PDZ256rkz:
6166 case VRSQRT14PDZm:
6167 case VRSQRT14PDZmb:
6168 case VRSQRT14PDZmbk:
6169 case VRSQRT14PDZmbkz:
6170 case VRSQRT14PDZmk:
6171 case VRSQRT14PDZmkz:
6172 case VRSQRT14PDZr:
6173 case VRSQRT14PDZrk:
6174 case VRSQRT14PDZrkz:
6175 return true;
6176 }
6177 return false;
6178}
6179
6180bool isVTESTPD(unsigned Opcode) {
6181 switch (Opcode) {
6182 case VTESTPDYrm:
6183 case VTESTPDYrr:
6184 case VTESTPDrm:
6185 case VTESTPDrr:
6186 return true;
6187 }
6188 return false;
6189}
6190
6191bool isVFNMADD231SH(unsigned Opcode) {
6192 switch (Opcode) {
6193 case VFNMADD231SHZm_Int:
6194 case VFNMADD231SHZmk_Int:
6195 case VFNMADD231SHZmkz_Int:
6196 case VFNMADD231SHZr_Int:
6197 case VFNMADD231SHZrb_Int:
6198 case VFNMADD231SHZrbk_Int:
6199 case VFNMADD231SHZrbkz_Int:
6200 case VFNMADD231SHZrk_Int:
6201 case VFNMADD231SHZrkz_Int:
6202 return true;
6203 }
6204 return false;
6205}
6206
6207bool isENDBR64(unsigned Opcode) {
6208 return Opcode == ENDBR64;
6209}
6210
6211bool isMULSD(unsigned Opcode) {
6212 switch (Opcode) {
6213 case MULSDrm_Int:
6214 case MULSDrr_Int:
6215 return true;
6216 }
6217 return false;
6218}
6219
6220bool isXRSTORS(unsigned Opcode) {
6221 return Opcode == XRSTORS;
6222}
6223
6224bool isPREFETCHNTA(unsigned Opcode) {
6225 return Opcode == PREFETCHNTA;
6226}
6227
6228bool isVPCOMD(unsigned Opcode) {
6229 switch (Opcode) {
6230 case VPCOMDmi:
6231 case VPCOMDri:
6232 return true;
6233 }
6234 return false;
6235}
6236
6237bool isVPCOMUB(unsigned Opcode) {
6238 switch (Opcode) {
6239 case VPCOMUBmi:
6240 case VPCOMUBri:
6241 return true;
6242 }
6243 return false;
6244}
6245
6246bool isVPHSUBD(unsigned Opcode) {
6247 switch (Opcode) {
6248 case VPHSUBDYrm:
6249 case VPHSUBDYrr:
6250 case VPHSUBDrm:
6251 case VPHSUBDrr:
6252 return true;
6253 }
6254 return false;
6255}
6256
6257bool isVBROADCASTI64X2(unsigned Opcode) {
6258 switch (Opcode) {
6259 case VBROADCASTI64X2Z256rm:
6260 case VBROADCASTI64X2Z256rmk:
6261 case VBROADCASTI64X2Z256rmkz:
6262 case VBROADCASTI64X2Zrm:
6263 case VBROADCASTI64X2Zrmk:
6264 case VBROADCASTI64X2Zrmkz:
6265 return true;
6266 }
6267 return false;
6268}
6269
6270bool isFPATAN(unsigned Opcode) {
6271 return Opcode == FPATAN;
6272}
6273
6274bool isLOOPE(unsigned Opcode) {
6275 return Opcode == LOOPE;
6276}
6277
6278bool isPCMPEQW(unsigned Opcode) {
6279 switch (Opcode) {
6280 case MMX_PCMPEQWrm:
6281 case MMX_PCMPEQWrr:
6282 case PCMPEQWrm:
6283 case PCMPEQWrr:
6284 return true;
6285 }
6286 return false;
6287}
6288
6289bool isVFMADDCSH(unsigned Opcode) {
6290 switch (Opcode) {
6291 case VFMADDCSHZm:
6292 case VFMADDCSHZmk:
6293 case VFMADDCSHZmkz:
6294 case VFMADDCSHZr:
6295 case VFMADDCSHZrb:
6296 case VFMADDCSHZrbk:
6297 case VFMADDCSHZrbkz:
6298 case VFMADDCSHZrk:
6299 case VFMADDCSHZrkz:
6300 return true;
6301 }
6302 return false;
6303}
6304
6305bool isVPDPBSSD(unsigned Opcode) {
6306 switch (Opcode) {
6307 case VPDPBSSDYrm:
6308 case VPDPBSSDYrr:
6309 case VPDPBSSDZ128rm:
6310 case VPDPBSSDZ128rmb:
6311 case VPDPBSSDZ128rmbk:
6312 case VPDPBSSDZ128rmbkz:
6313 case VPDPBSSDZ128rmk:
6314 case VPDPBSSDZ128rmkz:
6315 case VPDPBSSDZ128rr:
6316 case VPDPBSSDZ128rrk:
6317 case VPDPBSSDZ128rrkz:
6318 case VPDPBSSDZ256rm:
6319 case VPDPBSSDZ256rmb:
6320 case VPDPBSSDZ256rmbk:
6321 case VPDPBSSDZ256rmbkz:
6322 case VPDPBSSDZ256rmk:
6323 case VPDPBSSDZ256rmkz:
6324 case VPDPBSSDZ256rr:
6325 case VPDPBSSDZ256rrk:
6326 case VPDPBSSDZ256rrkz:
6327 case VPDPBSSDZrm:
6328 case VPDPBSSDZrmb:
6329 case VPDPBSSDZrmbk:
6330 case VPDPBSSDZrmbkz:
6331 case VPDPBSSDZrmk:
6332 case VPDPBSSDZrmkz:
6333 case VPDPBSSDZrr:
6334 case VPDPBSSDZrrk:
6335 case VPDPBSSDZrrkz:
6336 case VPDPBSSDrm:
6337 case VPDPBSSDrr:
6338 return true;
6339 }
6340 return false;
6341}
6342
6343bool isMOVRS(unsigned Opcode) {
6344 switch (Opcode) {
6345 case MOVRS16rm:
6346 case MOVRS16rm_EVEX:
6347 case MOVRS32rm:
6348 case MOVRS32rm_EVEX:
6349 case MOVRS64rm:
6350 case MOVRS64rm_EVEX:
6351 case MOVRS8rm:
6352 case MOVRS8rm_EVEX:
6353 return true;
6354 }
6355 return false;
6356}
6357
6358bool isVFMSUBADD132PH(unsigned Opcode) {
6359 switch (Opcode) {
6360 case VFMSUBADD132PHZ128m:
6361 case VFMSUBADD132PHZ128mb:
6362 case VFMSUBADD132PHZ128mbk:
6363 case VFMSUBADD132PHZ128mbkz:
6364 case VFMSUBADD132PHZ128mk:
6365 case VFMSUBADD132PHZ128mkz:
6366 case VFMSUBADD132PHZ128r:
6367 case VFMSUBADD132PHZ128rk:
6368 case VFMSUBADD132PHZ128rkz:
6369 case VFMSUBADD132PHZ256m:
6370 case VFMSUBADD132PHZ256mb:
6371 case VFMSUBADD132PHZ256mbk:
6372 case VFMSUBADD132PHZ256mbkz:
6373 case VFMSUBADD132PHZ256mk:
6374 case VFMSUBADD132PHZ256mkz:
6375 case VFMSUBADD132PHZ256r:
6376 case VFMSUBADD132PHZ256rk:
6377 case VFMSUBADD132PHZ256rkz:
6378 case VFMSUBADD132PHZm:
6379 case VFMSUBADD132PHZmb:
6380 case VFMSUBADD132PHZmbk:
6381 case VFMSUBADD132PHZmbkz:
6382 case VFMSUBADD132PHZmk:
6383 case VFMSUBADD132PHZmkz:
6384 case VFMSUBADD132PHZr:
6385 case VFMSUBADD132PHZrb:
6386 case VFMSUBADD132PHZrbk:
6387 case VFMSUBADD132PHZrbkz:
6388 case VFMSUBADD132PHZrk:
6389 case VFMSUBADD132PHZrkz:
6390 return true;
6391 }
6392 return false;
6393}
6394
6395bool isKADDW(unsigned Opcode) {
6396 return Opcode == KADDWkk;
6397}
6398
6399bool isPTEST(unsigned Opcode) {
6400 switch (Opcode) {
6401 case PTESTrm:
6402 case PTESTrr:
6403 return true;
6404 }
6405 return false;
6406}
6407
6408bool isVRSQRT28PS(unsigned Opcode) {
6409 switch (Opcode) {
6410 case VRSQRT28PSZm:
6411 case VRSQRT28PSZmb:
6412 case VRSQRT28PSZmbk:
6413 case VRSQRT28PSZmbkz:
6414 case VRSQRT28PSZmk:
6415 case VRSQRT28PSZmkz:
6416 case VRSQRT28PSZr:
6417 case VRSQRT28PSZrb:
6418 case VRSQRT28PSZrbk:
6419 case VRSQRT28PSZrbkz:
6420 case VRSQRT28PSZrk:
6421 case VRSQRT28PSZrkz:
6422 return true;
6423 }
6424 return false;
6425}
6426
6427bool isVGF2P8AFFINEINVQB(unsigned Opcode) {
6428 switch (Opcode) {
6429 case VGF2P8AFFINEINVQBYrmi:
6430 case VGF2P8AFFINEINVQBYrri:
6431 case VGF2P8AFFINEINVQBZ128rmbi:
6432 case VGF2P8AFFINEINVQBZ128rmbik:
6433 case VGF2P8AFFINEINVQBZ128rmbikz:
6434 case VGF2P8AFFINEINVQBZ128rmi:
6435 case VGF2P8AFFINEINVQBZ128rmik:
6436 case VGF2P8AFFINEINVQBZ128rmikz:
6437 case VGF2P8AFFINEINVQBZ128rri:
6438 case VGF2P8AFFINEINVQBZ128rrik:
6439 case VGF2P8AFFINEINVQBZ128rrikz:
6440 case VGF2P8AFFINEINVQBZ256rmbi:
6441 case VGF2P8AFFINEINVQBZ256rmbik:
6442 case VGF2P8AFFINEINVQBZ256rmbikz:
6443 case VGF2P8AFFINEINVQBZ256rmi:
6444 case VGF2P8AFFINEINVQBZ256rmik:
6445 case VGF2P8AFFINEINVQBZ256rmikz:
6446 case VGF2P8AFFINEINVQBZ256rri:
6447 case VGF2P8AFFINEINVQBZ256rrik:
6448 case VGF2P8AFFINEINVQBZ256rrikz:
6449 case VGF2P8AFFINEINVQBZrmbi:
6450 case VGF2P8AFFINEINVQBZrmbik:
6451 case VGF2P8AFFINEINVQBZrmbikz:
6452 case VGF2P8AFFINEINVQBZrmi:
6453 case VGF2P8AFFINEINVQBZrmik:
6454 case VGF2P8AFFINEINVQBZrmikz:
6455 case VGF2P8AFFINEINVQBZrri:
6456 case VGF2P8AFFINEINVQBZrrik:
6457 case VGF2P8AFFINEINVQBZrrikz:
6458 case VGF2P8AFFINEINVQBrmi:
6459 case VGF2P8AFFINEINVQBrri:
6460 return true;
6461 }
6462 return false;
6463}
6464
6465bool isSERIALIZE(unsigned Opcode) {
6466 return Opcode == SERIALIZE;
6467}
6468
6469bool isVPHADDWQ(unsigned Opcode) {
6470 switch (Opcode) {
6471 case VPHADDWQrm:
6472 case VPHADDWQrr:
6473 return true;
6474 }
6475 return false;
6476}
6477
6478bool isVRNDSCALESH(unsigned Opcode) {
6479 switch (Opcode) {
6480 case VRNDSCALESHZrmi_Int:
6481 case VRNDSCALESHZrmik_Int:
6482 case VRNDSCALESHZrmikz_Int:
6483 case VRNDSCALESHZrri_Int:
6484 case VRNDSCALESHZrrib_Int:
6485 case VRNDSCALESHZrribk_Int:
6486 case VRNDSCALESHZrribkz_Int:
6487 case VRNDSCALESHZrrik_Int:
6488 case VRNDSCALESHZrrikz_Int:
6489 return true;
6490 }
6491 return false;
6492}
6493
6494bool isAAA(unsigned Opcode) {
6495 return Opcode == AAA;
6496}
6497
6498bool isVADDBF16(unsigned Opcode) {
6499 switch (Opcode) {
6500 case VADDBF16Z128rm:
6501 case VADDBF16Z128rmb:
6502 case VADDBF16Z128rmbk:
6503 case VADDBF16Z128rmbkz:
6504 case VADDBF16Z128rmk:
6505 case VADDBF16Z128rmkz:
6506 case VADDBF16Z128rr:
6507 case VADDBF16Z128rrk:
6508 case VADDBF16Z128rrkz:
6509 case VADDBF16Z256rm:
6510 case VADDBF16Z256rmb:
6511 case VADDBF16Z256rmbk:
6512 case VADDBF16Z256rmbkz:
6513 case VADDBF16Z256rmk:
6514 case VADDBF16Z256rmkz:
6515 case VADDBF16Z256rr:
6516 case VADDBF16Z256rrk:
6517 case VADDBF16Z256rrkz:
6518 case VADDBF16Zrm:
6519 case VADDBF16Zrmb:
6520 case VADDBF16Zrmbk:
6521 case VADDBF16Zrmbkz:
6522 case VADDBF16Zrmk:
6523 case VADDBF16Zrmkz:
6524 case VADDBF16Zrr:
6525 case VADDBF16Zrrk:
6526 case VADDBF16Zrrkz:
6527 return true;
6528 }
6529 return false;
6530}
6531
6532bool isWRMSRLIST(unsigned Opcode) {
6533 return Opcode == WRMSRLIST;
6534}
6535
6536bool isVCVTPH2PSX(unsigned Opcode) {
6537 switch (Opcode) {
6538 case VCVTPH2PSXZ128rm:
6539 case VCVTPH2PSXZ128rmb:
6540 case VCVTPH2PSXZ128rmbk:
6541 case VCVTPH2PSXZ128rmbkz:
6542 case VCVTPH2PSXZ128rmk:
6543 case VCVTPH2PSXZ128rmkz:
6544 case VCVTPH2PSXZ128rr:
6545 case VCVTPH2PSXZ128rrk:
6546 case VCVTPH2PSXZ128rrkz:
6547 case VCVTPH2PSXZ256rm:
6548 case VCVTPH2PSXZ256rmb:
6549 case VCVTPH2PSXZ256rmbk:
6550 case VCVTPH2PSXZ256rmbkz:
6551 case VCVTPH2PSXZ256rmk:
6552 case VCVTPH2PSXZ256rmkz:
6553 case VCVTPH2PSXZ256rr:
6554 case VCVTPH2PSXZ256rrk:
6555 case VCVTPH2PSXZ256rrkz:
6556 case VCVTPH2PSXZrm:
6557 case VCVTPH2PSXZrmb:
6558 case VCVTPH2PSXZrmbk:
6559 case VCVTPH2PSXZrmbkz:
6560 case VCVTPH2PSXZrmk:
6561 case VCVTPH2PSXZrmkz:
6562 case VCVTPH2PSXZrr:
6563 case VCVTPH2PSXZrrb:
6564 case VCVTPH2PSXZrrbk:
6565 case VCVTPH2PSXZrrbkz:
6566 case VCVTPH2PSXZrrk:
6567 case VCVTPH2PSXZrrkz:
6568 return true;
6569 }
6570 return false;
6571}
6572
6573bool isVFMSUB231PH(unsigned Opcode) {
6574 switch (Opcode) {
6575 case VFMSUB231PHZ128m:
6576 case VFMSUB231PHZ128mb:
6577 case VFMSUB231PHZ128mbk:
6578 case VFMSUB231PHZ128mbkz:
6579 case VFMSUB231PHZ128mk:
6580 case VFMSUB231PHZ128mkz:
6581 case VFMSUB231PHZ128r:
6582 case VFMSUB231PHZ128rk:
6583 case VFMSUB231PHZ128rkz:
6584 case VFMSUB231PHZ256m:
6585 case VFMSUB231PHZ256mb:
6586 case VFMSUB231PHZ256mbk:
6587 case VFMSUB231PHZ256mbkz:
6588 case VFMSUB231PHZ256mk:
6589 case VFMSUB231PHZ256mkz:
6590 case VFMSUB231PHZ256r:
6591 case VFMSUB231PHZ256rk:
6592 case VFMSUB231PHZ256rkz:
6593 case VFMSUB231PHZm:
6594 case VFMSUB231PHZmb:
6595 case VFMSUB231PHZmbk:
6596 case VFMSUB231PHZmbkz:
6597 case VFMSUB231PHZmk:
6598 case VFMSUB231PHZmkz:
6599 case VFMSUB231PHZr:
6600 case VFMSUB231PHZrb:
6601 case VFMSUB231PHZrbk:
6602 case VFMSUB231PHZrbkz:
6603 case VFMSUB231PHZrk:
6604 case VFMSUB231PHZrkz:
6605 return true;
6606 }
6607 return false;
6608}
6609
6610bool isVGATHERQPD(unsigned Opcode) {
6611 switch (Opcode) {
6612 case VGATHERQPDYrm:
6613 case VGATHERQPDZ128rm:
6614 case VGATHERQPDZ256rm:
6615 case VGATHERQPDZrm:
6616 case VGATHERQPDrm:
6617 return true;
6618 }
6619 return false;
6620}
6621
6622bool isKADDB(unsigned Opcode) {
6623 return Opcode == KADDBkk;
6624}
6625
6626bool isCVTPD2PI(unsigned Opcode) {
6627 switch (Opcode) {
6628 case MMX_CVTPD2PIrm:
6629 case MMX_CVTPD2PIrr:
6630 return true;
6631 }
6632 return false;
6633}
6634
6635bool isVFNMSUB213PH(unsigned Opcode) {
6636 switch (Opcode) {
6637 case VFNMSUB213PHZ128m:
6638 case VFNMSUB213PHZ128mb:
6639 case VFNMSUB213PHZ128mbk:
6640 case VFNMSUB213PHZ128mbkz:
6641 case VFNMSUB213PHZ128mk:
6642 case VFNMSUB213PHZ128mkz:
6643 case VFNMSUB213PHZ128r:
6644 case VFNMSUB213PHZ128rk:
6645 case VFNMSUB213PHZ128rkz:
6646 case VFNMSUB213PHZ256m:
6647 case VFNMSUB213PHZ256mb:
6648 case VFNMSUB213PHZ256mbk:
6649 case VFNMSUB213PHZ256mbkz:
6650 case VFNMSUB213PHZ256mk:
6651 case VFNMSUB213PHZ256mkz:
6652 case VFNMSUB213PHZ256r:
6653 case VFNMSUB213PHZ256rk:
6654 case VFNMSUB213PHZ256rkz:
6655 case VFNMSUB213PHZm:
6656 case VFNMSUB213PHZmb:
6657 case VFNMSUB213PHZmbk:
6658 case VFNMSUB213PHZmbkz:
6659 case VFNMSUB213PHZmk:
6660 case VFNMSUB213PHZmkz:
6661 case VFNMSUB213PHZr:
6662 case VFNMSUB213PHZrb:
6663 case VFNMSUB213PHZrbk:
6664 case VFNMSUB213PHZrbkz:
6665 case VFNMSUB213PHZrk:
6666 case VFNMSUB213PHZrkz:
6667 return true;
6668 }
6669 return false;
6670}
6671
6672bool isXORPS(unsigned Opcode) {
6673 switch (Opcode) {
6674 case XORPSrm:
6675 case XORPSrr:
6676 return true;
6677 }
6678 return false;
6679}
6680
6681bool isVPCMPESTRI(unsigned Opcode) {
6682 switch (Opcode) {
6683 case VPCMPESTRIrmi:
6684 case VPCMPESTRIrri:
6685 return true;
6686 }
6687 return false;
6688}
6689
6690bool isVPADDSB(unsigned Opcode) {
6691 switch (Opcode) {
6692 case VPADDSBYrm:
6693 case VPADDSBYrr:
6694 case VPADDSBZ128rm:
6695 case VPADDSBZ128rmk:
6696 case VPADDSBZ128rmkz:
6697 case VPADDSBZ128rr:
6698 case VPADDSBZ128rrk:
6699 case VPADDSBZ128rrkz:
6700 case VPADDSBZ256rm:
6701 case VPADDSBZ256rmk:
6702 case VPADDSBZ256rmkz:
6703 case VPADDSBZ256rr:
6704 case VPADDSBZ256rrk:
6705 case VPADDSBZ256rrkz:
6706 case VPADDSBZrm:
6707 case VPADDSBZrmk:
6708 case VPADDSBZrmkz:
6709 case VPADDSBZrr:
6710 case VPADDSBZrrk:
6711 case VPADDSBZrrkz:
6712 case VPADDSBrm:
6713 case VPADDSBrr:
6714 return true;
6715 }
6716 return false;
6717}
6718
6719bool isPOP2(unsigned Opcode) {
6720 return Opcode == POP2;
6721}
6722
6723bool isRDMSRLIST(unsigned Opcode) {
6724 return Opcode == RDMSRLIST;
6725}
6726
6727bool isVPSHRDW(unsigned Opcode) {
6728 switch (Opcode) {
6729 case VPSHRDWZ128rmi:
6730 case VPSHRDWZ128rmik:
6731 case VPSHRDWZ128rmikz:
6732 case VPSHRDWZ128rri:
6733 case VPSHRDWZ128rrik:
6734 case VPSHRDWZ128rrikz:
6735 case VPSHRDWZ256rmi:
6736 case VPSHRDWZ256rmik:
6737 case VPSHRDWZ256rmikz:
6738 case VPSHRDWZ256rri:
6739 case VPSHRDWZ256rrik:
6740 case VPSHRDWZ256rrikz:
6741 case VPSHRDWZrmi:
6742 case VPSHRDWZrmik:
6743 case VPSHRDWZrmikz:
6744 case VPSHRDWZrri:
6745 case VPSHRDWZrrik:
6746 case VPSHRDWZrrikz:
6747 return true;
6748 }
6749 return false;
6750}
6751
6752bool isVPDPBUSD(unsigned Opcode) {
6753 switch (Opcode) {
6754 case VPDPBUSDYrm:
6755 case VPDPBUSDYrr:
6756 case VPDPBUSDZ128rm:
6757 case VPDPBUSDZ128rmb:
6758 case VPDPBUSDZ128rmbk:
6759 case VPDPBUSDZ128rmbkz:
6760 case VPDPBUSDZ128rmk:
6761 case VPDPBUSDZ128rmkz:
6762 case VPDPBUSDZ128rr:
6763 case VPDPBUSDZ128rrk:
6764 case VPDPBUSDZ128rrkz:
6765 case VPDPBUSDZ256rm:
6766 case VPDPBUSDZ256rmb:
6767 case VPDPBUSDZ256rmbk:
6768 case VPDPBUSDZ256rmbkz:
6769 case VPDPBUSDZ256rmk:
6770 case VPDPBUSDZ256rmkz:
6771 case VPDPBUSDZ256rr:
6772 case VPDPBUSDZ256rrk:
6773 case VPDPBUSDZ256rrkz:
6774 case VPDPBUSDZrm:
6775 case VPDPBUSDZrmb:
6776 case VPDPBUSDZrmbk:
6777 case VPDPBUSDZrmbkz:
6778 case VPDPBUSDZrmk:
6779 case VPDPBUSDZrmkz:
6780 case VPDPBUSDZrr:
6781 case VPDPBUSDZrrk:
6782 case VPDPBUSDZrrkz:
6783 case VPDPBUSDrm:
6784 case VPDPBUSDrr:
6785 return true;
6786 }
6787 return false;
6788}
6789
6790bool isVCMPPH(unsigned Opcode) {
6791 switch (Opcode) {
6792 case VCMPPHZ128rmbi:
6793 case VCMPPHZ128rmbik:
6794 case VCMPPHZ128rmi:
6795 case VCMPPHZ128rmik:
6796 case VCMPPHZ128rri:
6797 case VCMPPHZ128rrik:
6798 case VCMPPHZ256rmbi:
6799 case VCMPPHZ256rmbik:
6800 case VCMPPHZ256rmi:
6801 case VCMPPHZ256rmik:
6802 case VCMPPHZ256rri:
6803 case VCMPPHZ256rrik:
6804 case VCMPPHZrmbi:
6805 case VCMPPHZrmbik:
6806 case VCMPPHZrmi:
6807 case VCMPPHZrmik:
6808 case VCMPPHZrri:
6809 case VCMPPHZrrib:
6810 case VCMPPHZrribk:
6811 case VCMPPHZrrik:
6812 return true;
6813 }
6814 return false;
6815}
6816
6817bool isVANDNPD(unsigned Opcode) {
6818 switch (Opcode) {
6819 case VANDNPDYrm:
6820 case VANDNPDYrr:
6821 case VANDNPDZ128rm:
6822 case VANDNPDZ128rmb:
6823 case VANDNPDZ128rmbk:
6824 case VANDNPDZ128rmbkz:
6825 case VANDNPDZ128rmk:
6826 case VANDNPDZ128rmkz:
6827 case VANDNPDZ128rr:
6828 case VANDNPDZ128rrk:
6829 case VANDNPDZ128rrkz:
6830 case VANDNPDZ256rm:
6831 case VANDNPDZ256rmb:
6832 case VANDNPDZ256rmbk:
6833 case VANDNPDZ256rmbkz:
6834 case VANDNPDZ256rmk:
6835 case VANDNPDZ256rmkz:
6836 case VANDNPDZ256rr:
6837 case VANDNPDZ256rrk:
6838 case VANDNPDZ256rrkz:
6839 case VANDNPDZrm:
6840 case VANDNPDZrmb:
6841 case VANDNPDZrmbk:
6842 case VANDNPDZrmbkz:
6843 case VANDNPDZrmk:
6844 case VANDNPDZrmkz:
6845 case VANDNPDZrr:
6846 case VANDNPDZrrk:
6847 case VANDNPDZrrkz:
6848 case VANDNPDrm:
6849 case VANDNPDrr:
6850 return true;
6851 }
6852 return false;
6853}
6854
6855bool isSUB(unsigned Opcode) {
6856 switch (Opcode) {
6857 case SUB16i16:
6858 case SUB16mi:
6859 case SUB16mi8:
6860 case SUB16mi8_EVEX:
6861 case SUB16mi8_ND:
6862 case SUB16mi8_NF:
6863 case SUB16mi8_NF_ND:
6864 case SUB16mi_EVEX:
6865 case SUB16mi_ND:
6866 case SUB16mi_NF:
6867 case SUB16mi_NF_ND:
6868 case SUB16mr:
6869 case SUB16mr_EVEX:
6870 case SUB16mr_ND:
6871 case SUB16mr_NF:
6872 case SUB16mr_NF_ND:
6873 case SUB16ri:
6874 case SUB16ri8:
6875 case SUB16ri8_EVEX:
6876 case SUB16ri8_ND:
6877 case SUB16ri8_NF:
6878 case SUB16ri8_NF_ND:
6879 case SUB16ri_EVEX:
6880 case SUB16ri_ND:
6881 case SUB16ri_NF:
6882 case SUB16ri_NF_ND:
6883 case SUB16rm:
6884 case SUB16rm_EVEX:
6885 case SUB16rm_ND:
6886 case SUB16rm_NF:
6887 case SUB16rm_NF_ND:
6888 case SUB16rr:
6889 case SUB16rr_EVEX:
6890 case SUB16rr_EVEX_REV:
6891 case SUB16rr_ND:
6892 case SUB16rr_ND_REV:
6893 case SUB16rr_NF:
6894 case SUB16rr_NF_ND:
6895 case SUB16rr_NF_ND_REV:
6896 case SUB16rr_NF_REV:
6897 case SUB16rr_REV:
6898 case SUB32i32:
6899 case SUB32mi:
6900 case SUB32mi8:
6901 case SUB32mi8_EVEX:
6902 case SUB32mi8_ND:
6903 case SUB32mi8_NF:
6904 case SUB32mi8_NF_ND:
6905 case SUB32mi_EVEX:
6906 case SUB32mi_ND:
6907 case SUB32mi_NF:
6908 case SUB32mi_NF_ND:
6909 case SUB32mr:
6910 case SUB32mr_EVEX:
6911 case SUB32mr_ND:
6912 case SUB32mr_NF:
6913 case SUB32mr_NF_ND:
6914 case SUB32ri:
6915 case SUB32ri8:
6916 case SUB32ri8_EVEX:
6917 case SUB32ri8_ND:
6918 case SUB32ri8_NF:
6919 case SUB32ri8_NF_ND:
6920 case SUB32ri_EVEX:
6921 case SUB32ri_ND:
6922 case SUB32ri_NF:
6923 case SUB32ri_NF_ND:
6924 case SUB32rm:
6925 case SUB32rm_EVEX:
6926 case SUB32rm_ND:
6927 case SUB32rm_NF:
6928 case SUB32rm_NF_ND:
6929 case SUB32rr:
6930 case SUB32rr_EVEX:
6931 case SUB32rr_EVEX_REV:
6932 case SUB32rr_ND:
6933 case SUB32rr_ND_REV:
6934 case SUB32rr_NF:
6935 case SUB32rr_NF_ND:
6936 case SUB32rr_NF_ND_REV:
6937 case SUB32rr_NF_REV:
6938 case SUB32rr_REV:
6939 case SUB64i32:
6940 case SUB64mi32:
6941 case SUB64mi32_EVEX:
6942 case SUB64mi32_ND:
6943 case SUB64mi32_NF:
6944 case SUB64mi32_NF_ND:
6945 case SUB64mi8:
6946 case SUB64mi8_EVEX:
6947 case SUB64mi8_ND:
6948 case SUB64mi8_NF:
6949 case SUB64mi8_NF_ND:
6950 case SUB64mr:
6951 case SUB64mr_EVEX:
6952 case SUB64mr_ND:
6953 case SUB64mr_NF:
6954 case SUB64mr_NF_ND:
6955 case SUB64ri32:
6956 case SUB64ri32_EVEX:
6957 case SUB64ri32_ND:
6958 case SUB64ri32_NF:
6959 case SUB64ri32_NF_ND:
6960 case SUB64ri8:
6961 case SUB64ri8_EVEX:
6962 case SUB64ri8_ND:
6963 case SUB64ri8_NF:
6964 case SUB64ri8_NF_ND:
6965 case SUB64rm:
6966 case SUB64rm_EVEX:
6967 case SUB64rm_ND:
6968 case SUB64rm_NF:
6969 case SUB64rm_NF_ND:
6970 case SUB64rr:
6971 case SUB64rr_EVEX:
6972 case SUB64rr_EVEX_REV:
6973 case SUB64rr_ND:
6974 case SUB64rr_ND_REV:
6975 case SUB64rr_NF:
6976 case SUB64rr_NF_ND:
6977 case SUB64rr_NF_ND_REV:
6978 case SUB64rr_NF_REV:
6979 case SUB64rr_REV:
6980 case SUB8i8:
6981 case SUB8mi:
6982 case SUB8mi8:
6983 case SUB8mi_EVEX:
6984 case SUB8mi_ND:
6985 case SUB8mi_NF:
6986 case SUB8mi_NF_ND:
6987 case SUB8mr:
6988 case SUB8mr_EVEX:
6989 case SUB8mr_ND:
6990 case SUB8mr_NF:
6991 case SUB8mr_NF_ND:
6992 case SUB8ri:
6993 case SUB8ri8:
6994 case SUB8ri_EVEX:
6995 case SUB8ri_ND:
6996 case SUB8ri_NF:
6997 case SUB8ri_NF_ND:
6998 case SUB8rm:
6999 case SUB8rm_EVEX:
7000 case SUB8rm_ND:
7001 case SUB8rm_NF:
7002 case SUB8rm_NF_ND:
7003 case SUB8rr:
7004 case SUB8rr_EVEX:
7005 case SUB8rr_EVEX_REV:
7006 case SUB8rr_ND:
7007 case SUB8rr_ND_REV:
7008 case SUB8rr_NF:
7009 case SUB8rr_NF_ND:
7010 case SUB8rr_NF_ND_REV:
7011 case SUB8rr_NF_REV:
7012 case SUB8rr_REV:
7013 return true;
7014 }
7015 return false;
7016}
7017
7018bool isVRSQRT28PD(unsigned Opcode) {
7019 switch (Opcode) {
7020 case VRSQRT28PDZm:
7021 case VRSQRT28PDZmb:
7022 case VRSQRT28PDZmbk:
7023 case VRSQRT28PDZmbkz:
7024 case VRSQRT28PDZmk:
7025 case VRSQRT28PDZmkz:
7026 case VRSQRT28PDZr:
7027 case VRSQRT28PDZrb:
7028 case VRSQRT28PDZrbk:
7029 case VRSQRT28PDZrbkz:
7030 case VRSQRT28PDZrk:
7031 case VRSQRT28PDZrkz:
7032 return true;
7033 }
7034 return false;
7035}
7036
7037bool isVFNMADD132PH(unsigned Opcode) {
7038 switch (Opcode) {
7039 case VFNMADD132PHZ128m:
7040 case VFNMADD132PHZ128mb:
7041 case VFNMADD132PHZ128mbk:
7042 case VFNMADD132PHZ128mbkz:
7043 case VFNMADD132PHZ128mk:
7044 case VFNMADD132PHZ128mkz:
7045 case VFNMADD132PHZ128r:
7046 case VFNMADD132PHZ128rk:
7047 case VFNMADD132PHZ128rkz:
7048 case VFNMADD132PHZ256m:
7049 case VFNMADD132PHZ256mb:
7050 case VFNMADD132PHZ256mbk:
7051 case VFNMADD132PHZ256mbkz:
7052 case VFNMADD132PHZ256mk:
7053 case VFNMADD132PHZ256mkz:
7054 case VFNMADD132PHZ256r:
7055 case VFNMADD132PHZ256rk:
7056 case VFNMADD132PHZ256rkz:
7057 case VFNMADD132PHZm:
7058 case VFNMADD132PHZmb:
7059 case VFNMADD132PHZmbk:
7060 case VFNMADD132PHZmbkz:
7061 case VFNMADD132PHZmk:
7062 case VFNMADD132PHZmkz:
7063 case VFNMADD132PHZr:
7064 case VFNMADD132PHZrb:
7065 case VFNMADD132PHZrbk:
7066 case VFNMADD132PHZrbkz:
7067 case VFNMADD132PHZrk:
7068 case VFNMADD132PHZrkz:
7069 return true;
7070 }
7071 return false;
7072}
7073
7074bool isVPMACSSWW(unsigned Opcode) {
7075 switch (Opcode) {
7076 case VPMACSSWWrm:
7077 case VPMACSSWWrr:
7078 return true;
7079 }
7080 return false;
7081}
7082
7083bool isXSTORE(unsigned Opcode) {
7084 return Opcode == XSTORE;
7085}
7086
7087bool isVPROTQ(unsigned Opcode) {
7088 switch (Opcode) {
7089 case VPROTQmi:
7090 case VPROTQmr:
7091 case VPROTQri:
7092 case VPROTQrm:
7093 case VPROTQrr:
7094 case VPROTQrr_REV:
7095 return true;
7096 }
7097 return false;
7098}
7099
7100bool isVPHADDBD(unsigned Opcode) {
7101 switch (Opcode) {
7102 case VPHADDBDrm:
7103 case VPHADDBDrr:
7104 return true;
7105 }
7106 return false;
7107}
7108
7109bool isVPMAXSB(unsigned Opcode) {
7110 switch (Opcode) {
7111 case VPMAXSBYrm:
7112 case VPMAXSBYrr:
7113 case VPMAXSBZ128rm:
7114 case VPMAXSBZ128rmk:
7115 case VPMAXSBZ128rmkz:
7116 case VPMAXSBZ128rr:
7117 case VPMAXSBZ128rrk:
7118 case VPMAXSBZ128rrkz:
7119 case VPMAXSBZ256rm:
7120 case VPMAXSBZ256rmk:
7121 case VPMAXSBZ256rmkz:
7122 case VPMAXSBZ256rr:
7123 case VPMAXSBZ256rrk:
7124 case VPMAXSBZ256rrkz:
7125 case VPMAXSBZrm:
7126 case VPMAXSBZrmk:
7127 case VPMAXSBZrmkz:
7128 case VPMAXSBZrr:
7129 case VPMAXSBZrrk:
7130 case VPMAXSBZrrkz:
7131 case VPMAXSBrm:
7132 case VPMAXSBrr:
7133 return true;
7134 }
7135 return false;
7136}
7137
7138bool isVMOVDQU8(unsigned Opcode) {
7139 switch (Opcode) {
7140 case VMOVDQU8Z128mr:
7141 case VMOVDQU8Z128mrk:
7142 case VMOVDQU8Z128rm:
7143 case VMOVDQU8Z128rmk:
7144 case VMOVDQU8Z128rmkz:
7145 case VMOVDQU8Z128rr:
7146 case VMOVDQU8Z128rr_REV:
7147 case VMOVDQU8Z128rrk:
7148 case VMOVDQU8Z128rrk_REV:
7149 case VMOVDQU8Z128rrkz:
7150 case VMOVDQU8Z128rrkz_REV:
7151 case VMOVDQU8Z256mr:
7152 case VMOVDQU8Z256mrk:
7153 case VMOVDQU8Z256rm:
7154 case VMOVDQU8Z256rmk:
7155 case VMOVDQU8Z256rmkz:
7156 case VMOVDQU8Z256rr:
7157 case VMOVDQU8Z256rr_REV:
7158 case VMOVDQU8Z256rrk:
7159 case VMOVDQU8Z256rrk_REV:
7160 case VMOVDQU8Z256rrkz:
7161 case VMOVDQU8Z256rrkz_REV:
7162 case VMOVDQU8Zmr:
7163 case VMOVDQU8Zmrk:
7164 case VMOVDQU8Zrm:
7165 case VMOVDQU8Zrmk:
7166 case VMOVDQU8Zrmkz:
7167 case VMOVDQU8Zrr:
7168 case VMOVDQU8Zrr_REV:
7169 case VMOVDQU8Zrrk:
7170 case VMOVDQU8Zrrk_REV:
7171 case VMOVDQU8Zrrkz:
7172 case VMOVDQU8Zrrkz_REV:
7173 return true;
7174 }
7175 return false;
7176}
7177
7178bool isVPMOVSXWD(unsigned Opcode) {
7179 switch (Opcode) {
7180 case VPMOVSXWDYrm:
7181 case VPMOVSXWDYrr:
7182 case VPMOVSXWDZ128rm:
7183 case VPMOVSXWDZ128rmk:
7184 case VPMOVSXWDZ128rmkz:
7185 case VPMOVSXWDZ128rr:
7186 case VPMOVSXWDZ128rrk:
7187 case VPMOVSXWDZ128rrkz:
7188 case VPMOVSXWDZ256rm:
7189 case VPMOVSXWDZ256rmk:
7190 case VPMOVSXWDZ256rmkz:
7191 case VPMOVSXWDZ256rr:
7192 case VPMOVSXWDZ256rrk:
7193 case VPMOVSXWDZ256rrkz:
7194 case VPMOVSXWDZrm:
7195 case VPMOVSXWDZrmk:
7196 case VPMOVSXWDZrmkz:
7197 case VPMOVSXWDZrr:
7198 case VPMOVSXWDZrrk:
7199 case VPMOVSXWDZrrkz:
7200 case VPMOVSXWDrm:
7201 case VPMOVSXWDrr:
7202 return true;
7203 }
7204 return false;
7205}
7206
7207bool isVMINMAXPD(unsigned Opcode) {
7208 switch (Opcode) {
7209 case VMINMAXPDZ128rmbi:
7210 case VMINMAXPDZ128rmbik:
7211 case VMINMAXPDZ128rmbikz:
7212 case VMINMAXPDZ128rmi:
7213 case VMINMAXPDZ128rmik:
7214 case VMINMAXPDZ128rmikz:
7215 case VMINMAXPDZ128rri:
7216 case VMINMAXPDZ128rrik:
7217 case VMINMAXPDZ128rrikz:
7218 case VMINMAXPDZ256rmbi:
7219 case VMINMAXPDZ256rmbik:
7220 case VMINMAXPDZ256rmbikz:
7221 case VMINMAXPDZ256rmi:
7222 case VMINMAXPDZ256rmik:
7223 case VMINMAXPDZ256rmikz:
7224 case VMINMAXPDZ256rri:
7225 case VMINMAXPDZ256rrik:
7226 case VMINMAXPDZ256rrikz:
7227 case VMINMAXPDZrmbi:
7228 case VMINMAXPDZrmbik:
7229 case VMINMAXPDZrmbikz:
7230 case VMINMAXPDZrmi:
7231 case VMINMAXPDZrmik:
7232 case VMINMAXPDZrmikz:
7233 case VMINMAXPDZrri:
7234 case VMINMAXPDZrrib:
7235 case VMINMAXPDZrribk:
7236 case VMINMAXPDZrribkz:
7237 case VMINMAXPDZrrik:
7238 case VMINMAXPDZrrikz:
7239 return true;
7240 }
7241 return false;
7242}
7243
7244bool isSHA256RNDS2(unsigned Opcode) {
7245 switch (Opcode) {
7246 case SHA256RNDS2rm:
7247 case SHA256RNDS2rr:
7248 return true;
7249 }
7250 return false;
7251}
7252
7253bool isKANDB(unsigned Opcode) {
7254 return Opcode == KANDBkk;
7255}
7256
7257bool isTPAUSE(unsigned Opcode) {
7258 return Opcode == TPAUSE;
7259}
7260
7261bool isPUSH(unsigned Opcode) {
7262 switch (Opcode) {
7263 case PUSH16i:
7264 case PUSH16i8:
7265 case PUSH16r:
7266 case PUSH16rmm:
7267 case PUSH16rmr:
7268 case PUSH32i:
7269 case PUSH32i8:
7270 case PUSH32r:
7271 case PUSH32rmm:
7272 case PUSH32rmr:
7273 case PUSH64i32:
7274 case PUSH64i8:
7275 case PUSH64r:
7276 case PUSH64rmm:
7277 case PUSH64rmr:
7278 case PUSHCS16:
7279 case PUSHCS32:
7280 case PUSHDS16:
7281 case PUSHDS32:
7282 case PUSHES16:
7283 case PUSHES32:
7284 case PUSHFS16:
7285 case PUSHFS32:
7286 case PUSHFS64:
7287 case PUSHGS16:
7288 case PUSHGS32:
7289 case PUSHGS64:
7290 case PUSHSS16:
7291 case PUSHSS32:
7292 return true;
7293 }
7294 return false;
7295}
7296
7297bool isVRNDSCALESS(unsigned Opcode) {
7298 switch (Opcode) {
7299 case VRNDSCALESSZrmi_Int:
7300 case VRNDSCALESSZrmik_Int:
7301 case VRNDSCALESSZrmikz_Int:
7302 case VRNDSCALESSZrri_Int:
7303 case VRNDSCALESSZrrib_Int:
7304 case VRNDSCALESSZrribk_Int:
7305 case VRNDSCALESSZrribkz_Int:
7306 case VRNDSCALESSZrrik_Int:
7307 case VRNDSCALESSZrrikz_Int:
7308 return true;
7309 }
7310 return false;
7311}
7312
7313bool isVRNDSCALEBF16(unsigned Opcode) {
7314 switch (Opcode) {
7315 case VRNDSCALEBF16Z128rmbi:
7316 case VRNDSCALEBF16Z128rmbik:
7317 case VRNDSCALEBF16Z128rmbikz:
7318 case VRNDSCALEBF16Z128rmi:
7319 case VRNDSCALEBF16Z128rmik:
7320 case VRNDSCALEBF16Z128rmikz:
7321 case VRNDSCALEBF16Z128rri:
7322 case VRNDSCALEBF16Z128rrik:
7323 case VRNDSCALEBF16Z128rrikz:
7324 case VRNDSCALEBF16Z256rmbi:
7325 case VRNDSCALEBF16Z256rmbik:
7326 case VRNDSCALEBF16Z256rmbikz:
7327 case VRNDSCALEBF16Z256rmi:
7328 case VRNDSCALEBF16Z256rmik:
7329 case VRNDSCALEBF16Z256rmikz:
7330 case VRNDSCALEBF16Z256rri:
7331 case VRNDSCALEBF16Z256rrik:
7332 case VRNDSCALEBF16Z256rrikz:
7333 case VRNDSCALEBF16Zrmbi:
7334 case VRNDSCALEBF16Zrmbik:
7335 case VRNDSCALEBF16Zrmbikz:
7336 case VRNDSCALEBF16Zrmi:
7337 case VRNDSCALEBF16Zrmik:
7338 case VRNDSCALEBF16Zrmikz:
7339 case VRNDSCALEBF16Zrri:
7340 case VRNDSCALEBF16Zrrik:
7341 case VRNDSCALEBF16Zrrikz:
7342 return true;
7343 }
7344 return false;
7345}
7346
7347bool isVPCMPISTRI(unsigned Opcode) {
7348 switch (Opcode) {
7349 case VPCMPISTRIrmi:
7350 case VPCMPISTRIrri:
7351 return true;
7352 }
7353 return false;
7354}
7355
7356bool isSTGI(unsigned Opcode) {
7357 return Opcode == STGI;
7358}
7359
7360bool isSBB(unsigned Opcode) {
7361 switch (Opcode) {
7362 case SBB16i16:
7363 case SBB16mi:
7364 case SBB16mi8:
7365 case SBB16mi8_EVEX:
7366 case SBB16mi8_ND:
7367 case SBB16mi_EVEX:
7368 case SBB16mi_ND:
7369 case SBB16mr:
7370 case SBB16mr_EVEX:
7371 case SBB16mr_ND:
7372 case SBB16ri:
7373 case SBB16ri8:
7374 case SBB16ri8_EVEX:
7375 case SBB16ri8_ND:
7376 case SBB16ri_EVEX:
7377 case SBB16ri_ND:
7378 case SBB16rm:
7379 case SBB16rm_EVEX:
7380 case SBB16rm_ND:
7381 case SBB16rr:
7382 case SBB16rr_EVEX:
7383 case SBB16rr_EVEX_REV:
7384 case SBB16rr_ND:
7385 case SBB16rr_ND_REV:
7386 case SBB16rr_REV:
7387 case SBB32i32:
7388 case SBB32mi:
7389 case SBB32mi8:
7390 case SBB32mi8_EVEX:
7391 case SBB32mi8_ND:
7392 case SBB32mi_EVEX:
7393 case SBB32mi_ND:
7394 case SBB32mr:
7395 case SBB32mr_EVEX:
7396 case SBB32mr_ND:
7397 case SBB32ri:
7398 case SBB32ri8:
7399 case SBB32ri8_EVEX:
7400 case SBB32ri8_ND:
7401 case SBB32ri_EVEX:
7402 case SBB32ri_ND:
7403 case SBB32rm:
7404 case SBB32rm_EVEX:
7405 case SBB32rm_ND:
7406 case SBB32rr:
7407 case SBB32rr_EVEX:
7408 case SBB32rr_EVEX_REV:
7409 case SBB32rr_ND:
7410 case SBB32rr_ND_REV:
7411 case SBB32rr_REV:
7412 case SBB64i32:
7413 case SBB64mi32:
7414 case SBB64mi32_EVEX:
7415 case SBB64mi32_ND:
7416 case SBB64mi8:
7417 case SBB64mi8_EVEX:
7418 case SBB64mi8_ND:
7419 case SBB64mr:
7420 case SBB64mr_EVEX:
7421 case SBB64mr_ND:
7422 case SBB64ri32:
7423 case SBB64ri32_EVEX:
7424 case SBB64ri32_ND:
7425 case SBB64ri8:
7426 case SBB64ri8_EVEX:
7427 case SBB64ri8_ND:
7428 case SBB64rm:
7429 case SBB64rm_EVEX:
7430 case SBB64rm_ND:
7431 case SBB64rr:
7432 case SBB64rr_EVEX:
7433 case SBB64rr_EVEX_REV:
7434 case SBB64rr_ND:
7435 case SBB64rr_ND_REV:
7436 case SBB64rr_REV:
7437 case SBB8i8:
7438 case SBB8mi:
7439 case SBB8mi8:
7440 case SBB8mi_EVEX:
7441 case SBB8mi_ND:
7442 case SBB8mr:
7443 case SBB8mr_EVEX:
7444 case SBB8mr_ND:
7445 case SBB8ri:
7446 case SBB8ri8:
7447 case SBB8ri_EVEX:
7448 case SBB8ri_ND:
7449 case SBB8rm:
7450 case SBB8rm_EVEX:
7451 case SBB8rm_ND:
7452 case SBB8rr:
7453 case SBB8rr_EVEX:
7454 case SBB8rr_EVEX_REV:
7455 case SBB8rr_ND:
7456 case SBB8rr_ND_REV:
7457 case SBB8rr_REV:
7458 return true;
7459 }
7460 return false;
7461}
7462
7463bool isBLCS(unsigned Opcode) {
7464 switch (Opcode) {
7465 case BLCS32rm:
7466 case BLCS32rr:
7467 case BLCS64rm:
7468 case BLCS64rr:
7469 return true;
7470 }
7471 return false;
7472}
7473
7474bool isVCVTSD2SH(unsigned Opcode) {
7475 switch (Opcode) {
7476 case VCVTSD2SHZrm_Int:
7477 case VCVTSD2SHZrmk_Int:
7478 case VCVTSD2SHZrmkz_Int:
7479 case VCVTSD2SHZrr_Int:
7480 case VCVTSD2SHZrrb_Int:
7481 case VCVTSD2SHZrrbk_Int:
7482 case VCVTSD2SHZrrbkz_Int:
7483 case VCVTSD2SHZrrk_Int:
7484 case VCVTSD2SHZrrkz_Int:
7485 return true;
7486 }
7487 return false;
7488}
7489
7490bool isVPERMW(unsigned Opcode) {
7491 switch (Opcode) {
7492 case VPERMWZ128rm:
7493 case VPERMWZ128rmk:
7494 case VPERMWZ128rmkz:
7495 case VPERMWZ128rr:
7496 case VPERMWZ128rrk:
7497 case VPERMWZ128rrkz:
7498 case VPERMWZ256rm:
7499 case VPERMWZ256rmk:
7500 case VPERMWZ256rmkz:
7501 case VPERMWZ256rr:
7502 case VPERMWZ256rrk:
7503 case VPERMWZ256rrkz:
7504 case VPERMWZrm:
7505 case VPERMWZrmk:
7506 case VPERMWZrmkz:
7507 case VPERMWZrr:
7508 case VPERMWZrrk:
7509 case VPERMWZrrkz:
7510 return true;
7511 }
7512 return false;
7513}
7514
7515bool isXRESLDTRK(unsigned Opcode) {
7516 return Opcode == XRESLDTRK;
7517}
7518
7519bool isAESENC256KL(unsigned Opcode) {
7520 return Opcode == AESENC256KL;
7521}
7522
7523bool isVGATHERDPD(unsigned Opcode) {
7524 switch (Opcode) {
7525 case VGATHERDPDYrm:
7526 case VGATHERDPDZ128rm:
7527 case VGATHERDPDZ256rm:
7528 case VGATHERDPDZrm:
7529 case VGATHERDPDrm:
7530 return true;
7531 }
7532 return false;
7533}
7534
7535bool isHRESET(unsigned Opcode) {
7536 return Opcode == HRESET;
7537}
7538
7539bool isVFMSUBADD231PD(unsigned Opcode) {
7540 switch (Opcode) {
7541 case VFMSUBADD231PDYm:
7542 case VFMSUBADD231PDYr:
7543 case VFMSUBADD231PDZ128m:
7544 case VFMSUBADD231PDZ128mb:
7545 case VFMSUBADD231PDZ128mbk:
7546 case VFMSUBADD231PDZ128mbkz:
7547 case VFMSUBADD231PDZ128mk:
7548 case VFMSUBADD231PDZ128mkz:
7549 case VFMSUBADD231PDZ128r:
7550 case VFMSUBADD231PDZ128rk:
7551 case VFMSUBADD231PDZ128rkz:
7552 case VFMSUBADD231PDZ256m:
7553 case VFMSUBADD231PDZ256mb:
7554 case VFMSUBADD231PDZ256mbk:
7555 case VFMSUBADD231PDZ256mbkz:
7556 case VFMSUBADD231PDZ256mk:
7557 case VFMSUBADD231PDZ256mkz:
7558 case VFMSUBADD231PDZ256r:
7559 case VFMSUBADD231PDZ256rk:
7560 case VFMSUBADD231PDZ256rkz:
7561 case VFMSUBADD231PDZm:
7562 case VFMSUBADD231PDZmb:
7563 case VFMSUBADD231PDZmbk:
7564 case VFMSUBADD231PDZmbkz:
7565 case VFMSUBADD231PDZmk:
7566 case VFMSUBADD231PDZmkz:
7567 case VFMSUBADD231PDZr:
7568 case VFMSUBADD231PDZrb:
7569 case VFMSUBADD231PDZrbk:
7570 case VFMSUBADD231PDZrbkz:
7571 case VFMSUBADD231PDZrk:
7572 case VFMSUBADD231PDZrkz:
7573 case VFMSUBADD231PDm:
7574 case VFMSUBADD231PDr:
7575 return true;
7576 }
7577 return false;
7578}
7579
7580bool isVFRCZSS(unsigned Opcode) {
7581 switch (Opcode) {
7582 case VFRCZSSrm:
7583 case VFRCZSSrr:
7584 return true;
7585 }
7586 return false;
7587}
7588
7589bool isMINPS(unsigned Opcode) {
7590 switch (Opcode) {
7591 case MINPSrm:
7592 case MINPSrr:
7593 return true;
7594 }
7595 return false;
7596}
7597
7598bool isFPREM1(unsigned Opcode) {
7599 return Opcode == FPREM1;
7600}
7601
7602bool isVPCMPUB(unsigned Opcode) {
7603 switch (Opcode) {
7604 case VPCMPUBZ128rmi:
7605 case VPCMPUBZ128rmik:
7606 case VPCMPUBZ128rri:
7607 case VPCMPUBZ128rrik:
7608 case VPCMPUBZ256rmi:
7609 case VPCMPUBZ256rmik:
7610 case VPCMPUBZ256rri:
7611 case VPCMPUBZ256rrik:
7612 case VPCMPUBZrmi:
7613 case VPCMPUBZrmik:
7614 case VPCMPUBZrri:
7615 case VPCMPUBZrrik:
7616 return true;
7617 }
7618 return false;
7619}
7620
7621bool isVSQRTPD(unsigned Opcode) {
7622 switch (Opcode) {
7623 case VSQRTPDYm:
7624 case VSQRTPDYr:
7625 case VSQRTPDZ128m:
7626 case VSQRTPDZ128mb:
7627 case VSQRTPDZ128mbk:
7628 case VSQRTPDZ128mbkz:
7629 case VSQRTPDZ128mk:
7630 case VSQRTPDZ128mkz:
7631 case VSQRTPDZ128r:
7632 case VSQRTPDZ128rk:
7633 case VSQRTPDZ128rkz:
7634 case VSQRTPDZ256m:
7635 case VSQRTPDZ256mb:
7636 case VSQRTPDZ256mbk:
7637 case VSQRTPDZ256mbkz:
7638 case VSQRTPDZ256mk:
7639 case VSQRTPDZ256mkz:
7640 case VSQRTPDZ256r:
7641 case VSQRTPDZ256rk:
7642 case VSQRTPDZ256rkz:
7643 case VSQRTPDZm:
7644 case VSQRTPDZmb:
7645 case VSQRTPDZmbk:
7646 case VSQRTPDZmbkz:
7647 case VSQRTPDZmk:
7648 case VSQRTPDZmkz:
7649 case VSQRTPDZr:
7650 case VSQRTPDZrb:
7651 case VSQRTPDZrbk:
7652 case VSQRTPDZrbkz:
7653 case VSQRTPDZrk:
7654 case VSQRTPDZrkz:
7655 case VSQRTPDm:
7656 case VSQRTPDr:
7657 return true;
7658 }
7659 return false;
7660}
7661
7662bool isVFRCZPS(unsigned Opcode) {
7663 switch (Opcode) {
7664 case VFRCZPSYrm:
7665 case VFRCZPSYrr:
7666 case VFRCZPSrm:
7667 case VFRCZPSrr:
7668 return true;
7669 }
7670 return false;
7671}
7672
7673bool isVFNMADD213SS(unsigned Opcode) {
7674 switch (Opcode) {
7675 case VFNMADD213SSZm_Int:
7676 case VFNMADD213SSZmk_Int:
7677 case VFNMADD213SSZmkz_Int:
7678 case VFNMADD213SSZr_Int:
7679 case VFNMADD213SSZrb_Int:
7680 case VFNMADD213SSZrbk_Int:
7681 case VFNMADD213SSZrbkz_Int:
7682 case VFNMADD213SSZrk_Int:
7683 case VFNMADD213SSZrkz_Int:
7684 case VFNMADD213SSm_Int:
7685 case VFNMADD213SSr_Int:
7686 return true;
7687 }
7688 return false;
7689}
7690
7691bool isVPMOVDW(unsigned Opcode) {
7692 switch (Opcode) {
7693 case VPMOVDWZ128mr:
7694 case VPMOVDWZ128mrk:
7695 case VPMOVDWZ128rr:
7696 case VPMOVDWZ128rrk:
7697 case VPMOVDWZ128rrkz:
7698 case VPMOVDWZ256mr:
7699 case VPMOVDWZ256mrk:
7700 case VPMOVDWZ256rr:
7701 case VPMOVDWZ256rrk:
7702 case VPMOVDWZ256rrkz:
7703 case VPMOVDWZmr:
7704 case VPMOVDWZmrk:
7705 case VPMOVDWZrr:
7706 case VPMOVDWZrrk:
7707 case VPMOVDWZrrkz:
7708 return true;
7709 }
7710 return false;
7711}
7712
7713bool isVCVTPH2HF8S(unsigned Opcode) {
7714 switch (Opcode) {
7715 case VCVTPH2HF8SZ128rm:
7716 case VCVTPH2HF8SZ128rmb:
7717 case VCVTPH2HF8SZ128rmbk:
7718 case VCVTPH2HF8SZ128rmbkz:
7719 case VCVTPH2HF8SZ128rmk:
7720 case VCVTPH2HF8SZ128rmkz:
7721 case VCVTPH2HF8SZ128rr:
7722 case VCVTPH2HF8SZ128rrk:
7723 case VCVTPH2HF8SZ128rrkz:
7724 case VCVTPH2HF8SZ256rm:
7725 case VCVTPH2HF8SZ256rmb:
7726 case VCVTPH2HF8SZ256rmbk:
7727 case VCVTPH2HF8SZ256rmbkz:
7728 case VCVTPH2HF8SZ256rmk:
7729 case VCVTPH2HF8SZ256rmkz:
7730 case VCVTPH2HF8SZ256rr:
7731 case VCVTPH2HF8SZ256rrk:
7732 case VCVTPH2HF8SZ256rrkz:
7733 case VCVTPH2HF8SZrm:
7734 case VCVTPH2HF8SZrmb:
7735 case VCVTPH2HF8SZrmbk:
7736 case VCVTPH2HF8SZrmbkz:
7737 case VCVTPH2HF8SZrmk:
7738 case VCVTPH2HF8SZrmkz:
7739 case VCVTPH2HF8SZrr:
7740 case VCVTPH2HF8SZrrk:
7741 case VCVTPH2HF8SZrrkz:
7742 return true;
7743 }
7744 return false;
7745}
7746
7747bool isVPSHRDVQ(unsigned Opcode) {
7748 switch (Opcode) {
7749 case VPSHRDVQZ128m:
7750 case VPSHRDVQZ128mb:
7751 case VPSHRDVQZ128mbk:
7752 case VPSHRDVQZ128mbkz:
7753 case VPSHRDVQZ128mk:
7754 case VPSHRDVQZ128mkz:
7755 case VPSHRDVQZ128r:
7756 case VPSHRDVQZ128rk:
7757 case VPSHRDVQZ128rkz:
7758 case VPSHRDVQZ256m:
7759 case VPSHRDVQZ256mb:
7760 case VPSHRDVQZ256mbk:
7761 case VPSHRDVQZ256mbkz:
7762 case VPSHRDVQZ256mk:
7763 case VPSHRDVQZ256mkz:
7764 case VPSHRDVQZ256r:
7765 case VPSHRDVQZ256rk:
7766 case VPSHRDVQZ256rkz:
7767 case VPSHRDVQZm:
7768 case VPSHRDVQZmb:
7769 case VPSHRDVQZmbk:
7770 case VPSHRDVQZmbkz:
7771 case VPSHRDVQZmk:
7772 case VPSHRDVQZmkz:
7773 case VPSHRDVQZr:
7774 case VPSHRDVQZrk:
7775 case VPSHRDVQZrkz:
7776 return true;
7777 }
7778 return false;
7779}
7780
7781bool isVBROADCASTSD(unsigned Opcode) {
7782 switch (Opcode) {
7783 case VBROADCASTSDYrm:
7784 case VBROADCASTSDYrr:
7785 case VBROADCASTSDZ256rm:
7786 case VBROADCASTSDZ256rmk:
7787 case VBROADCASTSDZ256rmkz:
7788 case VBROADCASTSDZ256rr:
7789 case VBROADCASTSDZ256rrk:
7790 case VBROADCASTSDZ256rrkz:
7791 case VBROADCASTSDZrm:
7792 case VBROADCASTSDZrmk:
7793 case VBROADCASTSDZrmkz:
7794 case VBROADCASTSDZrr:
7795 case VBROADCASTSDZrrk:
7796 case VBROADCASTSDZrrkz:
7797 return true;
7798 }
7799 return false;
7800}
7801
7802bool isVSHUFPD(unsigned Opcode) {
7803 switch (Opcode) {
7804 case VSHUFPDYrmi:
7805 case VSHUFPDYrri:
7806 case VSHUFPDZ128rmbi:
7807 case VSHUFPDZ128rmbik:
7808 case VSHUFPDZ128rmbikz:
7809 case VSHUFPDZ128rmi:
7810 case VSHUFPDZ128rmik:
7811 case VSHUFPDZ128rmikz:
7812 case VSHUFPDZ128rri:
7813 case VSHUFPDZ128rrik:
7814 case VSHUFPDZ128rrikz:
7815 case VSHUFPDZ256rmbi:
7816 case VSHUFPDZ256rmbik:
7817 case VSHUFPDZ256rmbikz:
7818 case VSHUFPDZ256rmi:
7819 case VSHUFPDZ256rmik:
7820 case VSHUFPDZ256rmikz:
7821 case VSHUFPDZ256rri:
7822 case VSHUFPDZ256rrik:
7823 case VSHUFPDZ256rrikz:
7824 case VSHUFPDZrmbi:
7825 case VSHUFPDZrmbik:
7826 case VSHUFPDZrmbikz:
7827 case VSHUFPDZrmi:
7828 case VSHUFPDZrmik:
7829 case VSHUFPDZrmikz:
7830 case VSHUFPDZrri:
7831 case VSHUFPDZrrik:
7832 case VSHUFPDZrrikz:
7833 case VSHUFPDrmi:
7834 case VSHUFPDrri:
7835 return true;
7836 }
7837 return false;
7838}
7839
7840bool isVPSUBSW(unsigned Opcode) {
7841 switch (Opcode) {
7842 case VPSUBSWYrm:
7843 case VPSUBSWYrr:
7844 case VPSUBSWZ128rm:
7845 case VPSUBSWZ128rmk:
7846 case VPSUBSWZ128rmkz:
7847 case VPSUBSWZ128rr:
7848 case VPSUBSWZ128rrk:
7849 case VPSUBSWZ128rrkz:
7850 case VPSUBSWZ256rm:
7851 case VPSUBSWZ256rmk:
7852 case VPSUBSWZ256rmkz:
7853 case VPSUBSWZ256rr:
7854 case VPSUBSWZ256rrk:
7855 case VPSUBSWZ256rrkz:
7856 case VPSUBSWZrm:
7857 case VPSUBSWZrmk:
7858 case VPSUBSWZrmkz:
7859 case VPSUBSWZrr:
7860 case VPSUBSWZrrk:
7861 case VPSUBSWZrrkz:
7862 case VPSUBSWrm:
7863 case VPSUBSWrr:
7864 return true;
7865 }
7866 return false;
7867}
7868
7869bool isKUNPCKBW(unsigned Opcode) {
7870 return Opcode == KUNPCKBWkk;
7871}
7872
7873bool isVPBLENDD(unsigned Opcode) {
7874 switch (Opcode) {
7875 case VPBLENDDYrmi:
7876 case VPBLENDDYrri:
7877 case VPBLENDDrmi:
7878 case VPBLENDDrri:
7879 return true;
7880 }
7881 return false;
7882}
7883
7884bool isUNPCKHPD(unsigned Opcode) {
7885 switch (Opcode) {
7886 case UNPCKHPDrm:
7887 case UNPCKHPDrr:
7888 return true;
7889 }
7890 return false;
7891}
7892
7893bool isVFNMADD231SD(unsigned Opcode) {
7894 switch (Opcode) {
7895 case VFNMADD231SDZm_Int:
7896 case VFNMADD231SDZmk_Int:
7897 case VFNMADD231SDZmkz_Int:
7898 case VFNMADD231SDZr_Int:
7899 case VFNMADD231SDZrb_Int:
7900 case VFNMADD231SDZrbk_Int:
7901 case VFNMADD231SDZrbkz_Int:
7902 case VFNMADD231SDZrk_Int:
7903 case VFNMADD231SDZrkz_Int:
7904 case VFNMADD231SDm_Int:
7905 case VFNMADD231SDr_Int:
7906 return true;
7907 }
7908 return false;
7909}
7910
7911bool isVPBROADCASTMW2D(unsigned Opcode) {
7912 switch (Opcode) {
7913 case VPBROADCASTMW2DZ128rr:
7914 case VPBROADCASTMW2DZ256rr:
7915 case VPBROADCASTMW2DZrr:
7916 return true;
7917 }
7918 return false;
7919}
7920
7921bool isVPMULTISHIFTQB(unsigned Opcode) {
7922 switch (Opcode) {
7923 case VPMULTISHIFTQBZ128rm:
7924 case VPMULTISHIFTQBZ128rmb:
7925 case VPMULTISHIFTQBZ128rmbk:
7926 case VPMULTISHIFTQBZ128rmbkz:
7927 case VPMULTISHIFTQBZ128rmk:
7928 case VPMULTISHIFTQBZ128rmkz:
7929 case VPMULTISHIFTQBZ128rr:
7930 case VPMULTISHIFTQBZ128rrk:
7931 case VPMULTISHIFTQBZ128rrkz:
7932 case VPMULTISHIFTQBZ256rm:
7933 case VPMULTISHIFTQBZ256rmb:
7934 case VPMULTISHIFTQBZ256rmbk:
7935 case VPMULTISHIFTQBZ256rmbkz:
7936 case VPMULTISHIFTQBZ256rmk:
7937 case VPMULTISHIFTQBZ256rmkz:
7938 case VPMULTISHIFTQBZ256rr:
7939 case VPMULTISHIFTQBZ256rrk:
7940 case VPMULTISHIFTQBZ256rrkz:
7941 case VPMULTISHIFTQBZrm:
7942 case VPMULTISHIFTQBZrmb:
7943 case VPMULTISHIFTQBZrmbk:
7944 case VPMULTISHIFTQBZrmbkz:
7945 case VPMULTISHIFTQBZrmk:
7946 case VPMULTISHIFTQBZrmkz:
7947 case VPMULTISHIFTQBZrr:
7948 case VPMULTISHIFTQBZrrk:
7949 case VPMULTISHIFTQBZrrkz:
7950 return true;
7951 }
7952 return false;
7953}
7954
7955bool isVP2INTERSECTQ(unsigned Opcode) {
7956 switch (Opcode) {
7957 case VP2INTERSECTQZ128rm:
7958 case VP2INTERSECTQZ128rmb:
7959 case VP2INTERSECTQZ128rr:
7960 case VP2INTERSECTQZ256rm:
7961 case VP2INTERSECTQZ256rmb:
7962 case VP2INTERSECTQZ256rr:
7963 case VP2INTERSECTQZrm:
7964 case VP2INTERSECTQZrmb:
7965 case VP2INTERSECTQZrr:
7966 return true;
7967 }
7968 return false;
7969}
7970
7971bool isVFNMSUB132BF16(unsigned Opcode) {
7972 switch (Opcode) {
7973 case VFNMSUB132BF16Z128m:
7974 case VFNMSUB132BF16Z128mb:
7975 case VFNMSUB132BF16Z128mbk:
7976 case VFNMSUB132BF16Z128mbkz:
7977 case VFNMSUB132BF16Z128mk:
7978 case VFNMSUB132BF16Z128mkz:
7979 case VFNMSUB132BF16Z128r:
7980 case VFNMSUB132BF16Z128rk:
7981 case VFNMSUB132BF16Z128rkz:
7982 case VFNMSUB132BF16Z256m:
7983 case VFNMSUB132BF16Z256mb:
7984 case VFNMSUB132BF16Z256mbk:
7985 case VFNMSUB132BF16Z256mbkz:
7986 case VFNMSUB132BF16Z256mk:
7987 case VFNMSUB132BF16Z256mkz:
7988 case VFNMSUB132BF16Z256r:
7989 case VFNMSUB132BF16Z256rk:
7990 case VFNMSUB132BF16Z256rkz:
7991 case VFNMSUB132BF16Zm:
7992 case VFNMSUB132BF16Zmb:
7993 case VFNMSUB132BF16Zmbk:
7994 case VFNMSUB132BF16Zmbkz:
7995 case VFNMSUB132BF16Zmk:
7996 case VFNMSUB132BF16Zmkz:
7997 case VFNMSUB132BF16Zr:
7998 case VFNMSUB132BF16Zrk:
7999 case VFNMSUB132BF16Zrkz:
8000 return true;
8001 }
8002 return false;
8003}
8004
8005bool isVFMADD213BF16(unsigned Opcode) {
8006 switch (Opcode) {
8007 case VFMADD213BF16Z128m:
8008 case VFMADD213BF16Z128mb:
8009 case VFMADD213BF16Z128mbk:
8010 case VFMADD213BF16Z128mbkz:
8011 case VFMADD213BF16Z128mk:
8012 case VFMADD213BF16Z128mkz:
8013 case VFMADD213BF16Z128r:
8014 case VFMADD213BF16Z128rk:
8015 case VFMADD213BF16Z128rkz:
8016 case VFMADD213BF16Z256m:
8017 case VFMADD213BF16Z256mb:
8018 case VFMADD213BF16Z256mbk:
8019 case VFMADD213BF16Z256mbkz:
8020 case VFMADD213BF16Z256mk:
8021 case VFMADD213BF16Z256mkz:
8022 case VFMADD213BF16Z256r:
8023 case VFMADD213BF16Z256rk:
8024 case VFMADD213BF16Z256rkz:
8025 case VFMADD213BF16Zm:
8026 case VFMADD213BF16Zmb:
8027 case VFMADD213BF16Zmbk:
8028 case VFMADD213BF16Zmbkz:
8029 case VFMADD213BF16Zmk:
8030 case VFMADD213BF16Zmkz:
8031 case VFMADD213BF16Zr:
8032 case VFMADD213BF16Zrk:
8033 case VFMADD213BF16Zrkz:
8034 return true;
8035 }
8036 return false;
8037}
8038
8039bool isVPUNPCKHWD(unsigned Opcode) {
8040 switch (Opcode) {
8041 case VPUNPCKHWDYrm:
8042 case VPUNPCKHWDYrr:
8043 case VPUNPCKHWDZ128rm:
8044 case VPUNPCKHWDZ128rmk:
8045 case VPUNPCKHWDZ128rmkz:
8046 case VPUNPCKHWDZ128rr:
8047 case VPUNPCKHWDZ128rrk:
8048 case VPUNPCKHWDZ128rrkz:
8049 case VPUNPCKHWDZ256rm:
8050 case VPUNPCKHWDZ256rmk:
8051 case VPUNPCKHWDZ256rmkz:
8052 case VPUNPCKHWDZ256rr:
8053 case VPUNPCKHWDZ256rrk:
8054 case VPUNPCKHWDZ256rrkz:
8055 case VPUNPCKHWDZrm:
8056 case VPUNPCKHWDZrmk:
8057 case VPUNPCKHWDZrmkz:
8058 case VPUNPCKHWDZrr:
8059 case VPUNPCKHWDZrrk:
8060 case VPUNPCKHWDZrrkz:
8061 case VPUNPCKHWDrm:
8062 case VPUNPCKHWDrr:
8063 return true;
8064 }
8065 return false;
8066}
8067
8068bool isVPERM2F128(unsigned Opcode) {
8069 switch (Opcode) {
8070 case VPERM2F128rmi:
8071 case VPERM2F128rri:
8072 return true;
8073 }
8074 return false;
8075}
8076
8077bool isINSD(unsigned Opcode) {
8078 return Opcode == INSL;
8079}
8080
8081bool isLFS(unsigned Opcode) {
8082 switch (Opcode) {
8083 case LFS16rm:
8084 case LFS32rm:
8085 case LFS64rm:
8086 return true;
8087 }
8088 return false;
8089}
8090
8091bool isFMULP(unsigned Opcode) {
8092 return Opcode == MUL_FPrST0;
8093}
8094
8095bool isCWD(unsigned Opcode) {
8096 return Opcode == CWD;
8097}
8098
8099bool isVDIVSS(unsigned Opcode) {
8100 switch (Opcode) {
8101 case VDIVSSZrm_Int:
8102 case VDIVSSZrmk_Int:
8103 case VDIVSSZrmkz_Int:
8104 case VDIVSSZrr_Int:
8105 case VDIVSSZrrb_Int:
8106 case VDIVSSZrrbk_Int:
8107 case VDIVSSZrrbkz_Int:
8108 case VDIVSSZrrk_Int:
8109 case VDIVSSZrrkz_Int:
8110 case VDIVSSrm_Int:
8111 case VDIVSSrr_Int:
8112 return true;
8113 }
8114 return false;
8115}
8116
8117bool isVPSRLQ(unsigned Opcode) {
8118 switch (Opcode) {
8119 case VPSRLQYri:
8120 case VPSRLQYrm:
8121 case VPSRLQYrr:
8122 case VPSRLQZ128mbi:
8123 case VPSRLQZ128mbik:
8124 case VPSRLQZ128mbikz:
8125 case VPSRLQZ128mi:
8126 case VPSRLQZ128mik:
8127 case VPSRLQZ128mikz:
8128 case VPSRLQZ128ri:
8129 case VPSRLQZ128rik:
8130 case VPSRLQZ128rikz:
8131 case VPSRLQZ128rm:
8132 case VPSRLQZ128rmk:
8133 case VPSRLQZ128rmkz:
8134 case VPSRLQZ128rr:
8135 case VPSRLQZ128rrk:
8136 case VPSRLQZ128rrkz:
8137 case VPSRLQZ256mbi:
8138 case VPSRLQZ256mbik:
8139 case VPSRLQZ256mbikz:
8140 case VPSRLQZ256mi:
8141 case VPSRLQZ256mik:
8142 case VPSRLQZ256mikz:
8143 case VPSRLQZ256ri:
8144 case VPSRLQZ256rik:
8145 case VPSRLQZ256rikz:
8146 case VPSRLQZ256rm:
8147 case VPSRLQZ256rmk:
8148 case VPSRLQZ256rmkz:
8149 case VPSRLQZ256rr:
8150 case VPSRLQZ256rrk:
8151 case VPSRLQZ256rrkz:
8152 case VPSRLQZmbi:
8153 case VPSRLQZmbik:
8154 case VPSRLQZmbikz:
8155 case VPSRLQZmi:
8156 case VPSRLQZmik:
8157 case VPSRLQZmikz:
8158 case VPSRLQZri:
8159 case VPSRLQZrik:
8160 case VPSRLQZrikz:
8161 case VPSRLQZrm:
8162 case VPSRLQZrmk:
8163 case VPSRLQZrmkz:
8164 case VPSRLQZrr:
8165 case VPSRLQZrrk:
8166 case VPSRLQZrrkz:
8167 case VPSRLQri:
8168 case VPSRLQrm:
8169 case VPSRLQrr:
8170 return true;
8171 }
8172 return false;
8173}
8174
8175bool isFSQRT(unsigned Opcode) {
8176 return Opcode == SQRT_F;
8177}
8178
8179bool isJRCXZ(unsigned Opcode) {
8180 return Opcode == JRCXZ;
8181}
8182
8183bool isVPMOVMSKB(unsigned Opcode) {
8184 switch (Opcode) {
8185 case VPMOVMSKBYrr:
8186 case VPMOVMSKBrr:
8187 return true;
8188 }
8189 return false;
8190}
8191
8192bool isAESDEC256KL(unsigned Opcode) {
8193 return Opcode == AESDEC256KL;
8194}
8195
8196bool isFLDENV(unsigned Opcode) {
8197 return Opcode == FLDENVm;
8198}
8199
8200bool isVPHSUBWD(unsigned Opcode) {
8201 switch (Opcode) {
8202 case VPHSUBWDrm:
8203 case VPHSUBWDrr:
8204 return true;
8205 }
8206 return false;
8207}
8208
8209bool isWBNOINVD(unsigned Opcode) {
8210 return Opcode == WBNOINVD;
8211}
8212
8213bool isVEXPANDPD(unsigned Opcode) {
8214 switch (Opcode) {
8215 case VEXPANDPDZ128rm:
8216 case VEXPANDPDZ128rmk:
8217 case VEXPANDPDZ128rmkz:
8218 case VEXPANDPDZ128rr:
8219 case VEXPANDPDZ128rrk:
8220 case VEXPANDPDZ128rrkz:
8221 case VEXPANDPDZ256rm:
8222 case VEXPANDPDZ256rmk:
8223 case VEXPANDPDZ256rmkz:
8224 case VEXPANDPDZ256rr:
8225 case VEXPANDPDZ256rrk:
8226 case VEXPANDPDZ256rrkz:
8227 case VEXPANDPDZrm:
8228 case VEXPANDPDZrmk:
8229 case VEXPANDPDZrmkz:
8230 case VEXPANDPDZrr:
8231 case VEXPANDPDZrrk:
8232 case VEXPANDPDZrrkz:
8233 return true;
8234 }
8235 return false;
8236}
8237
8238bool isFYL2XP1(unsigned Opcode) {
8239 return Opcode == FYL2XP1;
8240}
8241
8242bool isPREFETCHT2(unsigned Opcode) {
8243 return Opcode == PREFETCHT2;
8244}
8245
8246bool isVPDPBSUDS(unsigned Opcode) {
8247 switch (Opcode) {
8248 case VPDPBSUDSYrm:
8249 case VPDPBSUDSYrr:
8250 case VPDPBSUDSZ128rm:
8251 case VPDPBSUDSZ128rmb:
8252 case VPDPBSUDSZ128rmbk:
8253 case VPDPBSUDSZ128rmbkz:
8254 case VPDPBSUDSZ128rmk:
8255 case VPDPBSUDSZ128rmkz:
8256 case VPDPBSUDSZ128rr:
8257 case VPDPBSUDSZ128rrk:
8258 case VPDPBSUDSZ128rrkz:
8259 case VPDPBSUDSZ256rm:
8260 case VPDPBSUDSZ256rmb:
8261 case VPDPBSUDSZ256rmbk:
8262 case VPDPBSUDSZ256rmbkz:
8263 case VPDPBSUDSZ256rmk:
8264 case VPDPBSUDSZ256rmkz:
8265 case VPDPBSUDSZ256rr:
8266 case VPDPBSUDSZ256rrk:
8267 case VPDPBSUDSZ256rrkz:
8268 case VPDPBSUDSZrm:
8269 case VPDPBSUDSZrmb:
8270 case VPDPBSUDSZrmbk:
8271 case VPDPBSUDSZrmbkz:
8272 case VPDPBSUDSZrmk:
8273 case VPDPBSUDSZrmkz:
8274 case VPDPBSUDSZrr:
8275 case VPDPBSUDSZrrk:
8276 case VPDPBSUDSZrrkz:
8277 case VPDPBSUDSrm:
8278 case VPDPBSUDSrr:
8279 return true;
8280 }
8281 return false;
8282}
8283
8284bool isVSHA512MSG2(unsigned Opcode) {
8285 return Opcode == VSHA512MSG2rr;
8286}
8287
8288bool isPMULHUW(unsigned Opcode) {
8289 switch (Opcode) {
8290 case MMX_PMULHUWrm:
8291 case MMX_PMULHUWrr:
8292 case PMULHUWrm:
8293 case PMULHUWrr:
8294 return true;
8295 }
8296 return false;
8297}
8298
8299bool isKANDNB(unsigned Opcode) {
8300 return Opcode == KANDNBkk;
8301}
8302
8303bool isVCVTUW2PH(unsigned Opcode) {
8304 switch (Opcode) {
8305 case VCVTUW2PHZ128rm:
8306 case VCVTUW2PHZ128rmb:
8307 case VCVTUW2PHZ128rmbk:
8308 case VCVTUW2PHZ128rmbkz:
8309 case VCVTUW2PHZ128rmk:
8310 case VCVTUW2PHZ128rmkz:
8311 case VCVTUW2PHZ128rr:
8312 case VCVTUW2PHZ128rrk:
8313 case VCVTUW2PHZ128rrkz:
8314 case VCVTUW2PHZ256rm:
8315 case VCVTUW2PHZ256rmb:
8316 case VCVTUW2PHZ256rmbk:
8317 case VCVTUW2PHZ256rmbkz:
8318 case VCVTUW2PHZ256rmk:
8319 case VCVTUW2PHZ256rmkz:
8320 case VCVTUW2PHZ256rr:
8321 case VCVTUW2PHZ256rrk:
8322 case VCVTUW2PHZ256rrkz:
8323 case VCVTUW2PHZrm:
8324 case VCVTUW2PHZrmb:
8325 case VCVTUW2PHZrmbk:
8326 case VCVTUW2PHZrmbkz:
8327 case VCVTUW2PHZrmk:
8328 case VCVTUW2PHZrmkz:
8329 case VCVTUW2PHZrr:
8330 case VCVTUW2PHZrrb:
8331 case VCVTUW2PHZrrbk:
8332 case VCVTUW2PHZrrbkz:
8333 case VCVTUW2PHZrrk:
8334 case VCVTUW2PHZrrkz:
8335 return true;
8336 }
8337 return false;
8338}
8339
8340bool isAESDECWIDE256KL(unsigned Opcode) {
8341 return Opcode == AESDECWIDE256KL;
8342}
8343
8344bool isVPGATHERDD(unsigned Opcode) {
8345 switch (Opcode) {
8346 case VPGATHERDDYrm:
8347 case VPGATHERDDZ128rm:
8348 case VPGATHERDDZ256rm:
8349 case VPGATHERDDZrm:
8350 case VPGATHERDDrm:
8351 return true;
8352 }
8353 return false;
8354}
8355
8356bool isVREDUCESH(unsigned Opcode) {
8357 switch (Opcode) {
8358 case VREDUCESHZrmi:
8359 case VREDUCESHZrmik:
8360 case VREDUCESHZrmikz:
8361 case VREDUCESHZrri:
8362 case VREDUCESHZrrib:
8363 case VREDUCESHZrribk:
8364 case VREDUCESHZrribkz:
8365 case VREDUCESHZrrik:
8366 case VREDUCESHZrrikz:
8367 return true;
8368 }
8369 return false;
8370}
8371
8372bool isPOPFQ(unsigned Opcode) {
8373 return Opcode == POPF64;
8374}
8375
8376bool isPAVGUSB(unsigned Opcode) {
8377 switch (Opcode) {
8378 case PAVGUSBrm:
8379 case PAVGUSBrr:
8380 return true;
8381 }
8382 return false;
8383}
8384
8385bool isVALIGND(unsigned Opcode) {
8386 switch (Opcode) {
8387 case VALIGNDZ128rmbi:
8388 case VALIGNDZ128rmbik:
8389 case VALIGNDZ128rmbikz:
8390 case VALIGNDZ128rmi:
8391 case VALIGNDZ128rmik:
8392 case VALIGNDZ128rmikz:
8393 case VALIGNDZ128rri:
8394 case VALIGNDZ128rrik:
8395 case VALIGNDZ128rrikz:
8396 case VALIGNDZ256rmbi:
8397 case VALIGNDZ256rmbik:
8398 case VALIGNDZ256rmbikz:
8399 case VALIGNDZ256rmi:
8400 case VALIGNDZ256rmik:
8401 case VALIGNDZ256rmikz:
8402 case VALIGNDZ256rri:
8403 case VALIGNDZ256rrik:
8404 case VALIGNDZ256rrikz:
8405 case VALIGNDZrmbi:
8406 case VALIGNDZrmbik:
8407 case VALIGNDZrmbikz:
8408 case VALIGNDZrmi:
8409 case VALIGNDZrmik:
8410 case VALIGNDZrmikz:
8411 case VALIGNDZrri:
8412 case VALIGNDZrrik:
8413 case VALIGNDZrrikz:
8414 return true;
8415 }
8416 return false;
8417}
8418
8419bool isVPHMINPOSUW(unsigned Opcode) {
8420 switch (Opcode) {
8421 case VPHMINPOSUWrm:
8422 case VPHMINPOSUWrr:
8423 return true;
8424 }
8425 return false;
8426}
8427
8428bool isLIDTD(unsigned Opcode) {
8429 return Opcode == LIDT32m;
8430}
8431
8432bool isVPERMT2PD(unsigned Opcode) {
8433 switch (Opcode) {
8434 case VPERMT2PDZ128rm:
8435 case VPERMT2PDZ128rmb:
8436 case VPERMT2PDZ128rmbk:
8437 case VPERMT2PDZ128rmbkz:
8438 case VPERMT2PDZ128rmk:
8439 case VPERMT2PDZ128rmkz:
8440 case VPERMT2PDZ128rr:
8441 case VPERMT2PDZ128rrk:
8442 case VPERMT2PDZ128rrkz:
8443 case VPERMT2PDZ256rm:
8444 case VPERMT2PDZ256rmb:
8445 case VPERMT2PDZ256rmbk:
8446 case VPERMT2PDZ256rmbkz:
8447 case VPERMT2PDZ256rmk:
8448 case VPERMT2PDZ256rmkz:
8449 case VPERMT2PDZ256rr:
8450 case VPERMT2PDZ256rrk:
8451 case VPERMT2PDZ256rrkz:
8452 case VPERMT2PDZrm:
8453 case VPERMT2PDZrmb:
8454 case VPERMT2PDZrmbk:
8455 case VPERMT2PDZrmbkz:
8456 case VPERMT2PDZrmk:
8457 case VPERMT2PDZrmkz:
8458 case VPERMT2PDZrr:
8459 case VPERMT2PDZrrk:
8460 case VPERMT2PDZrrkz:
8461 return true;
8462 }
8463 return false;
8464}
8465
8466bool isVMLAUNCH(unsigned Opcode) {
8467 return Opcode == VMLAUNCH;
8468}
8469
8470bool isVPXORQ(unsigned Opcode) {
8471 switch (Opcode) {
8472 case VPXORQZ128rm:
8473 case VPXORQZ128rmb:
8474 case VPXORQZ128rmbk:
8475 case VPXORQZ128rmbkz:
8476 case VPXORQZ128rmk:
8477 case VPXORQZ128rmkz:
8478 case VPXORQZ128rr:
8479 case VPXORQZ128rrk:
8480 case VPXORQZ128rrkz:
8481 case VPXORQZ256rm:
8482 case VPXORQZ256rmb:
8483 case VPXORQZ256rmbk:
8484 case VPXORQZ256rmbkz:
8485 case VPXORQZ256rmk:
8486 case VPXORQZ256rmkz:
8487 case VPXORQZ256rr:
8488 case VPXORQZ256rrk:
8489 case VPXORQZ256rrkz:
8490 case VPXORQZrm:
8491 case VPXORQZrmb:
8492 case VPXORQZrmbk:
8493 case VPXORQZrmbkz:
8494 case VPXORQZrmk:
8495 case VPXORQZrmkz:
8496 case VPXORQZrr:
8497 case VPXORQZrrk:
8498 case VPXORQZrrkz:
8499 return true;
8500 }
8501 return false;
8502}
8503
8504bool isMOVNTDQ(unsigned Opcode) {
8505 return Opcode == MOVNTDQmr;
8506}
8507
8508bool isPOP2P(unsigned Opcode) {
8509 return Opcode == POP2P;
8510}
8511
8512bool isVADDPD(unsigned Opcode) {
8513 switch (Opcode) {
8514 case VADDPDYrm:
8515 case VADDPDYrr:
8516 case VADDPDZ128rm:
8517 case VADDPDZ128rmb:
8518 case VADDPDZ128rmbk:
8519 case VADDPDZ128rmbkz:
8520 case VADDPDZ128rmk:
8521 case VADDPDZ128rmkz:
8522 case VADDPDZ128rr:
8523 case VADDPDZ128rrk:
8524 case VADDPDZ128rrkz:
8525 case VADDPDZ256rm:
8526 case VADDPDZ256rmb:
8527 case VADDPDZ256rmbk:
8528 case VADDPDZ256rmbkz:
8529 case VADDPDZ256rmk:
8530 case VADDPDZ256rmkz:
8531 case VADDPDZ256rr:
8532 case VADDPDZ256rrk:
8533 case VADDPDZ256rrkz:
8534 case VADDPDZrm:
8535 case VADDPDZrmb:
8536 case VADDPDZrmbk:
8537 case VADDPDZrmbkz:
8538 case VADDPDZrmk:
8539 case VADDPDZrmkz:
8540 case VADDPDZrr:
8541 case VADDPDZrrb:
8542 case VADDPDZrrbk:
8543 case VADDPDZrrbkz:
8544 case VADDPDZrrk:
8545 case VADDPDZrrkz:
8546 case VADDPDrm:
8547 case VADDPDrr:
8548 return true;
8549 }
8550 return false;
8551}
8552
8553bool isSMSW(unsigned Opcode) {
8554 switch (Opcode) {
8555 case SMSW16m:
8556 case SMSW16r:
8557 case SMSW32r:
8558 case SMSW64r:
8559 return true;
8560 }
8561 return false;
8562}
8563
8564bool isVEXP2PD(unsigned Opcode) {
8565 switch (Opcode) {
8566 case VEXP2PDZm:
8567 case VEXP2PDZmb:
8568 case VEXP2PDZmbk:
8569 case VEXP2PDZmbkz:
8570 case VEXP2PDZmk:
8571 case VEXP2PDZmkz:
8572 case VEXP2PDZr:
8573 case VEXP2PDZrb:
8574 case VEXP2PDZrbk:
8575 case VEXP2PDZrbkz:
8576 case VEXP2PDZrk:
8577 case VEXP2PDZrkz:
8578 return true;
8579 }
8580 return false;
8581}
8582
8583bool isPMULUDQ(unsigned Opcode) {
8584 switch (Opcode) {
8585 case MMX_PMULUDQrm:
8586 case MMX_PMULUDQrr:
8587 case PMULUDQrm:
8588 case PMULUDQrr:
8589 return true;
8590 }
8591 return false;
8592}
8593
8594bool isIRET(unsigned Opcode) {
8595 return Opcode == IRET16;
8596}
8597
8598bool isMULPS(unsigned Opcode) {
8599 switch (Opcode) {
8600 case MULPSrm:
8601 case MULPSrr:
8602 return true;
8603 }
8604 return false;
8605}
8606
8607bool isTDPBF8PS(unsigned Opcode) {
8608 return Opcode == TDPBF8PS;
8609}
8610
8611bool isVFNMSUBPD(unsigned Opcode) {
8612 switch (Opcode) {
8613 case VFNMSUBPD4Ymr:
8614 case VFNMSUBPD4Yrm:
8615 case VFNMSUBPD4Yrr:
8616 case VFNMSUBPD4Yrr_REV:
8617 case VFNMSUBPD4mr:
8618 case VFNMSUBPD4rm:
8619 case VFNMSUBPD4rr:
8620 case VFNMSUBPD4rr_REV:
8621 return true;
8622 }
8623 return false;
8624}
8625
8626bool isPHADDW(unsigned Opcode) {
8627 switch (Opcode) {
8628 case MMX_PHADDWrm:
8629 case MMX_PHADDWrr:
8630 case PHADDWrm:
8631 case PHADDWrr:
8632 return true;
8633 }
8634 return false;
8635}
8636
8637bool isRDSEED(unsigned Opcode) {
8638 switch (Opcode) {
8639 case RDSEED16r:
8640 case RDSEED32r:
8641 case RDSEED64r:
8642 return true;
8643 }
8644 return false;
8645}
8646
8647bool isVPSHLW(unsigned Opcode) {
8648 switch (Opcode) {
8649 case VPSHLWmr:
8650 case VPSHLWrm:
8651 case VPSHLWrr:
8652 case VPSHLWrr_REV:
8653 return true;
8654 }
8655 return false;
8656}
8657
8658bool isRMPUPDATE(unsigned Opcode) {
8659 return Opcode == RMPUPDATE;
8660}
8661
8662bool isVFMADD231PH(unsigned Opcode) {
8663 switch (Opcode) {
8664 case VFMADD231PHZ128m:
8665 case VFMADD231PHZ128mb:
8666 case VFMADD231PHZ128mbk:
8667 case VFMADD231PHZ128mbkz:
8668 case VFMADD231PHZ128mk:
8669 case VFMADD231PHZ128mkz:
8670 case VFMADD231PHZ128r:
8671 case VFMADD231PHZ128rk:
8672 case VFMADD231PHZ128rkz:
8673 case VFMADD231PHZ256m:
8674 case VFMADD231PHZ256mb:
8675 case VFMADD231PHZ256mbk:
8676 case VFMADD231PHZ256mbkz:
8677 case VFMADD231PHZ256mk:
8678 case VFMADD231PHZ256mkz:
8679 case VFMADD231PHZ256r:
8680 case VFMADD231PHZ256rk:
8681 case VFMADD231PHZ256rkz:
8682 case VFMADD231PHZm:
8683 case VFMADD231PHZmb:
8684 case VFMADD231PHZmbk:
8685 case VFMADD231PHZmbkz:
8686 case VFMADD231PHZmk:
8687 case VFMADD231PHZmkz:
8688 case VFMADD231PHZr:
8689 case VFMADD231PHZrb:
8690 case VFMADD231PHZrbk:
8691 case VFMADD231PHZrbkz:
8692 case VFMADD231PHZrk:
8693 case VFMADD231PHZrkz:
8694 return true;
8695 }
8696 return false;
8697}
8698
8699bool isVPSHAD(unsigned Opcode) {
8700 switch (Opcode) {
8701 case VPSHADmr:
8702 case VPSHADrm:
8703 case VPSHADrr:
8704 case VPSHADrr_REV:
8705 return true;
8706 }
8707 return false;
8708}
8709
8710bool isCLWB(unsigned Opcode) {
8711 return Opcode == CLWB;
8712}
8713
8714bool isPSUBUSB(unsigned Opcode) {
8715 switch (Opcode) {
8716 case MMX_PSUBUSBrm:
8717 case MMX_PSUBUSBrr:
8718 case PSUBUSBrm:
8719 case PSUBUSBrr:
8720 return true;
8721 }
8722 return false;
8723}
8724
8725bool isVCVTTSD2USI(unsigned Opcode) {
8726 switch (Opcode) {
8727 case VCVTTSD2USI64Zrm_Int:
8728 case VCVTTSD2USI64Zrr_Int:
8729 case VCVTTSD2USI64Zrrb_Int:
8730 case VCVTTSD2USIZrm_Int:
8731 case VCVTTSD2USIZrr_Int:
8732 case VCVTTSD2USIZrrb_Int:
8733 return true;
8734 }
8735 return false;
8736}
8737
8738bool isVEXTRACTPS(unsigned Opcode) {
8739 switch (Opcode) {
8740 case VEXTRACTPSZmri:
8741 case VEXTRACTPSZrri:
8742 case VEXTRACTPSmri:
8743 case VEXTRACTPSrri:
8744 return true;
8745 }
8746 return false;
8747}
8748
8749bool isMOVLPD(unsigned Opcode) {
8750 switch (Opcode) {
8751 case MOVLPDmr:
8752 case MOVLPDrm:
8753 return true;
8754 }
8755 return false;
8756}
8757
8758bool isLGDTD(unsigned Opcode) {
8759 return Opcode == LGDT32m;
8760}
8761
8762bool isVPBROADCASTMB2Q(unsigned Opcode) {
8763 switch (Opcode) {
8764 case VPBROADCASTMB2QZ128rr:
8765 case VPBROADCASTMB2QZ256rr:
8766 case VPBROADCASTMB2QZrr:
8767 return true;
8768 }
8769 return false;
8770}
8771
8772bool isOUT(unsigned Opcode) {
8773 switch (Opcode) {
8774 case OUT16ir:
8775 case OUT16rr:
8776 case OUT32ir:
8777 case OUT32rr:
8778 case OUT8ir:
8779 case OUT8rr:
8780 return true;
8781 }
8782 return false;
8783}
8784
8785bool isVMSAVE(unsigned Opcode) {
8786 switch (Opcode) {
8787 case VMSAVE32:
8788 case VMSAVE64:
8789 return true;
8790 }
8791 return false;
8792}
8793
8794bool isVCVTQQ2PD(unsigned Opcode) {
8795 switch (Opcode) {
8796 case VCVTQQ2PDZ128rm:
8797 case VCVTQQ2PDZ128rmb:
8798 case VCVTQQ2PDZ128rmbk:
8799 case VCVTQQ2PDZ128rmbkz:
8800 case VCVTQQ2PDZ128rmk:
8801 case VCVTQQ2PDZ128rmkz:
8802 case VCVTQQ2PDZ128rr:
8803 case VCVTQQ2PDZ128rrk:
8804 case VCVTQQ2PDZ128rrkz:
8805 case VCVTQQ2PDZ256rm:
8806 case VCVTQQ2PDZ256rmb:
8807 case VCVTQQ2PDZ256rmbk:
8808 case VCVTQQ2PDZ256rmbkz:
8809 case VCVTQQ2PDZ256rmk:
8810 case VCVTQQ2PDZ256rmkz:
8811 case VCVTQQ2PDZ256rr:
8812 case VCVTQQ2PDZ256rrk:
8813 case VCVTQQ2PDZ256rrkz:
8814 case VCVTQQ2PDZrm:
8815 case VCVTQQ2PDZrmb:
8816 case VCVTQQ2PDZrmbk:
8817 case VCVTQQ2PDZrmbkz:
8818 case VCVTQQ2PDZrmk:
8819 case VCVTQQ2PDZrmkz:
8820 case VCVTQQ2PDZrr:
8821 case VCVTQQ2PDZrrb:
8822 case VCVTQQ2PDZrrbk:
8823 case VCVTQQ2PDZrrbkz:
8824 case VCVTQQ2PDZrrk:
8825 case VCVTQQ2PDZrrkz:
8826 return true;
8827 }
8828 return false;
8829}
8830
8831bool isVFMADD213PH(unsigned Opcode) {
8832 switch (Opcode) {
8833 case VFMADD213PHZ128m:
8834 case VFMADD213PHZ128mb:
8835 case VFMADD213PHZ128mbk:
8836 case VFMADD213PHZ128mbkz:
8837 case VFMADD213PHZ128mk:
8838 case VFMADD213PHZ128mkz:
8839 case VFMADD213PHZ128r:
8840 case VFMADD213PHZ128rk:
8841 case VFMADD213PHZ128rkz:
8842 case VFMADD213PHZ256m:
8843 case VFMADD213PHZ256mb:
8844 case VFMADD213PHZ256mbk:
8845 case VFMADD213PHZ256mbkz:
8846 case VFMADD213PHZ256mk:
8847 case VFMADD213PHZ256mkz:
8848 case VFMADD213PHZ256r:
8849 case VFMADD213PHZ256rk:
8850 case VFMADD213PHZ256rkz:
8851 case VFMADD213PHZm:
8852 case VFMADD213PHZmb:
8853 case VFMADD213PHZmbk:
8854 case VFMADD213PHZmbkz:
8855 case VFMADD213PHZmk:
8856 case VFMADD213PHZmkz:
8857 case VFMADD213PHZr:
8858 case VFMADD213PHZrb:
8859 case VFMADD213PHZrbk:
8860 case VFMADD213PHZrbkz:
8861 case VFMADD213PHZrk:
8862 case VFMADD213PHZrkz:
8863 return true;
8864 }
8865 return false;
8866}
8867
8868bool isFCMOVBE(unsigned Opcode) {
8869 return Opcode == CMOVBE_F;
8870}
8871
8872bool isMOVSHDUP(unsigned Opcode) {
8873 switch (Opcode) {
8874 case MOVSHDUPrm:
8875 case MOVSHDUPrr:
8876 return true;
8877 }
8878 return false;
8879}
8880
8881bool isVPMOVUSQB(unsigned Opcode) {
8882 switch (Opcode) {
8883 case VPMOVUSQBZ128mr:
8884 case VPMOVUSQBZ128mrk:
8885 case VPMOVUSQBZ128rr:
8886 case VPMOVUSQBZ128rrk:
8887 case VPMOVUSQBZ128rrkz:
8888 case VPMOVUSQBZ256mr:
8889 case VPMOVUSQBZ256mrk:
8890 case VPMOVUSQBZ256rr:
8891 case VPMOVUSQBZ256rrk:
8892 case VPMOVUSQBZ256rrkz:
8893 case VPMOVUSQBZmr:
8894 case VPMOVUSQBZmrk:
8895 case VPMOVUSQBZrr:
8896 case VPMOVUSQBZrrk:
8897 case VPMOVUSQBZrrkz:
8898 return true;
8899 }
8900 return false;
8901}
8902
8903bool isFIST(unsigned Opcode) {
8904 switch (Opcode) {
8905 case IST_F16m:
8906 case IST_F32m:
8907 return true;
8908 }
8909 return false;
8910}
8911
8912bool isHADDPD(unsigned Opcode) {
8913 switch (Opcode) {
8914 case HADDPDrm:
8915 case HADDPDrr:
8916 return true;
8917 }
8918 return false;
8919}
8920
8921bool isPACKSSWB(unsigned Opcode) {
8922 switch (Opcode) {
8923 case MMX_PACKSSWBrm:
8924 case MMX_PACKSSWBrr:
8925 case PACKSSWBrm:
8926 case PACKSSWBrr:
8927 return true;
8928 }
8929 return false;
8930}
8931
8932bool isVPMACSSDQH(unsigned Opcode) {
8933 switch (Opcode) {
8934 case VPMACSSDQHrm:
8935 case VPMACSSDQHrr:
8936 return true;
8937 }
8938 return false;
8939}
8940
8941bool isVFNMSUB132SD(unsigned Opcode) {
8942 switch (Opcode) {
8943 case VFNMSUB132SDZm_Int:
8944 case VFNMSUB132SDZmk_Int:
8945 case VFNMSUB132SDZmkz_Int:
8946 case VFNMSUB132SDZr_Int:
8947 case VFNMSUB132SDZrb_Int:
8948 case VFNMSUB132SDZrbk_Int:
8949 case VFNMSUB132SDZrbkz_Int:
8950 case VFNMSUB132SDZrk_Int:
8951 case VFNMSUB132SDZrkz_Int:
8952 case VFNMSUB132SDm_Int:
8953 case VFNMSUB132SDr_Int:
8954 return true;
8955 }
8956 return false;
8957}
8958
8959bool isVPMASKMOVQ(unsigned Opcode) {
8960 switch (Opcode) {
8961 case VPMASKMOVQYmr:
8962 case VPMASKMOVQYrm:
8963 case VPMASKMOVQmr:
8964 case VPMASKMOVQrm:
8965 return true;
8966 }
8967 return false;
8968}
8969
8970bool isVCOMPRESSPD(unsigned Opcode) {
8971 switch (Opcode) {
8972 case VCOMPRESSPDZ128mr:
8973 case VCOMPRESSPDZ128mrk:
8974 case VCOMPRESSPDZ128rr:
8975 case VCOMPRESSPDZ128rrk:
8976 case VCOMPRESSPDZ128rrkz:
8977 case VCOMPRESSPDZ256mr:
8978 case VCOMPRESSPDZ256mrk:
8979 case VCOMPRESSPDZ256rr:
8980 case VCOMPRESSPDZ256rrk:
8981 case VCOMPRESSPDZ256rrkz:
8982 case VCOMPRESSPDZmr:
8983 case VCOMPRESSPDZmrk:
8984 case VCOMPRESSPDZrr:
8985 case VCOMPRESSPDZrrk:
8986 case VCOMPRESSPDZrrkz:
8987 return true;
8988 }
8989 return false;
8990}
8991
8992bool isVFMADD213SS(unsigned Opcode) {
8993 switch (Opcode) {
8994 case VFMADD213SSZm_Int:
8995 case VFMADD213SSZmk_Int:
8996 case VFMADD213SSZmkz_Int:
8997 case VFMADD213SSZr_Int:
8998 case VFMADD213SSZrb_Int:
8999 case VFMADD213SSZrbk_Int:
9000 case VFMADD213SSZrbkz_Int:
9001 case VFMADD213SSZrk_Int:
9002 case VFMADD213SSZrkz_Int:
9003 case VFMADD213SSm_Int:
9004 case VFMADD213SSr_Int:
9005 return true;
9006 }
9007 return false;
9008}
9009
9010bool isVPCMPQ(unsigned Opcode) {
9011 switch (Opcode) {
9012 case VPCMPQZ128rmbi:
9013 case VPCMPQZ128rmbik:
9014 case VPCMPQZ128rmi:
9015 case VPCMPQZ128rmik:
9016 case VPCMPQZ128rri:
9017 case VPCMPQZ128rrik:
9018 case VPCMPQZ256rmbi:
9019 case VPCMPQZ256rmbik:
9020 case VPCMPQZ256rmi:
9021 case VPCMPQZ256rmik:
9022 case VPCMPQZ256rri:
9023 case VPCMPQZ256rrik:
9024 case VPCMPQZrmbi:
9025 case VPCMPQZrmbik:
9026 case VPCMPQZrmi:
9027 case VPCMPQZrmik:
9028 case VPCMPQZrri:
9029 case VPCMPQZrrik:
9030 return true;
9031 }
9032 return false;
9033}
9034
9035bool isVADDSH(unsigned Opcode) {
9036 switch (Opcode) {
9037 case VADDSHZrm_Int:
9038 case VADDSHZrmk_Int:
9039 case VADDSHZrmkz_Int:
9040 case VADDSHZrr_Int:
9041 case VADDSHZrrb_Int:
9042 case VADDSHZrrbk_Int:
9043 case VADDSHZrrbkz_Int:
9044 case VADDSHZrrk_Int:
9045 case VADDSHZrrkz_Int:
9046 return true;
9047 }
9048 return false;
9049}
9050
9051bool isVFNMADDSD(unsigned Opcode) {
9052 switch (Opcode) {
9053 case VFNMADDSD4mr:
9054 case VFNMADDSD4rm:
9055 case VFNMADDSD4rr:
9056 case VFNMADDSD4rr_REV:
9057 return true;
9058 }
9059 return false;
9060}
9061
9062bool isUMWAIT(unsigned Opcode) {
9063 return Opcode == UMWAIT;
9064}
9065
9066bool isVPUNPCKHDQ(unsigned Opcode) {
9067 switch (Opcode) {
9068 case VPUNPCKHDQYrm:
9069 case VPUNPCKHDQYrr:
9070 case VPUNPCKHDQZ128rm:
9071 case VPUNPCKHDQZ128rmb:
9072 case VPUNPCKHDQZ128rmbk:
9073 case VPUNPCKHDQZ128rmbkz:
9074 case VPUNPCKHDQZ128rmk:
9075 case VPUNPCKHDQZ128rmkz:
9076 case VPUNPCKHDQZ128rr:
9077 case VPUNPCKHDQZ128rrk:
9078 case VPUNPCKHDQZ128rrkz:
9079 case VPUNPCKHDQZ256rm:
9080 case VPUNPCKHDQZ256rmb:
9081 case VPUNPCKHDQZ256rmbk:
9082 case VPUNPCKHDQZ256rmbkz:
9083 case VPUNPCKHDQZ256rmk:
9084 case VPUNPCKHDQZ256rmkz:
9085 case VPUNPCKHDQZ256rr:
9086 case VPUNPCKHDQZ256rrk:
9087 case VPUNPCKHDQZ256rrkz:
9088 case VPUNPCKHDQZrm:
9089 case VPUNPCKHDQZrmb:
9090 case VPUNPCKHDQZrmbk:
9091 case VPUNPCKHDQZrmbkz:
9092 case VPUNPCKHDQZrmk:
9093 case VPUNPCKHDQZrmkz:
9094 case VPUNPCKHDQZrr:
9095 case VPUNPCKHDQZrrk:
9096 case VPUNPCKHDQZrrkz:
9097 case VPUNPCKHDQrm:
9098 case VPUNPCKHDQrr:
9099 return true;
9100 }
9101 return false;
9102}
9103
9104bool isLCALL(unsigned Opcode) {
9105 switch (Opcode) {
9106 case FARCALL16i:
9107 case FARCALL16m:
9108 case FARCALL32i:
9109 case FARCALL64m:
9110 return true;
9111 }
9112 return false;
9113}
9114
9115bool isAESDEC128KL(unsigned Opcode) {
9116 return Opcode == AESDEC128KL;
9117}
9118
9119bool isVSUBPS(unsigned Opcode) {
9120 switch (Opcode) {
9121 case VSUBPSYrm:
9122 case VSUBPSYrr:
9123 case VSUBPSZ128rm:
9124 case VSUBPSZ128rmb:
9125 case VSUBPSZ128rmbk:
9126 case VSUBPSZ128rmbkz:
9127 case VSUBPSZ128rmk:
9128 case VSUBPSZ128rmkz:
9129 case VSUBPSZ128rr:
9130 case VSUBPSZ128rrk:
9131 case VSUBPSZ128rrkz:
9132 case VSUBPSZ256rm:
9133 case VSUBPSZ256rmb:
9134 case VSUBPSZ256rmbk:
9135 case VSUBPSZ256rmbkz:
9136 case VSUBPSZ256rmk:
9137 case VSUBPSZ256rmkz:
9138 case VSUBPSZ256rr:
9139 case VSUBPSZ256rrk:
9140 case VSUBPSZ256rrkz:
9141 case VSUBPSZrm:
9142 case VSUBPSZrmb:
9143 case VSUBPSZrmbk:
9144 case VSUBPSZrmbkz:
9145 case VSUBPSZrmk:
9146 case VSUBPSZrmkz:
9147 case VSUBPSZrr:
9148 case VSUBPSZrrb:
9149 case VSUBPSZrrbk:
9150 case VSUBPSZrrbkz:
9151 case VSUBPSZrrk:
9152 case VSUBPSZrrkz:
9153 case VSUBPSrm:
9154 case VSUBPSrr:
9155 return true;
9156 }
9157 return false;
9158}
9159
9160bool isFSTP(unsigned Opcode) {
9161 switch (Opcode) {
9162 case ST_FP32m:
9163 case ST_FP64m:
9164 case ST_FP80m:
9165 case ST_FPrr:
9166 return true;
9167 }
9168 return false;
9169}
9170
9171bool isVCVTUDQ2PD(unsigned Opcode) {
9172 switch (Opcode) {
9173 case VCVTUDQ2PDZ128rm:
9174 case VCVTUDQ2PDZ128rmb:
9175 case VCVTUDQ2PDZ128rmbk:
9176 case VCVTUDQ2PDZ128rmbkz:
9177 case VCVTUDQ2PDZ128rmk:
9178 case VCVTUDQ2PDZ128rmkz:
9179 case VCVTUDQ2PDZ128rr:
9180 case VCVTUDQ2PDZ128rrk:
9181 case VCVTUDQ2PDZ128rrkz:
9182 case VCVTUDQ2PDZ256rm:
9183 case VCVTUDQ2PDZ256rmb:
9184 case VCVTUDQ2PDZ256rmbk:
9185 case VCVTUDQ2PDZ256rmbkz:
9186 case VCVTUDQ2PDZ256rmk:
9187 case VCVTUDQ2PDZ256rmkz:
9188 case VCVTUDQ2PDZ256rr:
9189 case VCVTUDQ2PDZ256rrk:
9190 case VCVTUDQ2PDZ256rrkz:
9191 case VCVTUDQ2PDZrm:
9192 case VCVTUDQ2PDZrmb:
9193 case VCVTUDQ2PDZrmbk:
9194 case VCVTUDQ2PDZrmbkz:
9195 case VCVTUDQ2PDZrmk:
9196 case VCVTUDQ2PDZrmkz:
9197 case VCVTUDQ2PDZrr:
9198 case VCVTUDQ2PDZrrk:
9199 case VCVTUDQ2PDZrrkz:
9200 return true;
9201 }
9202 return false;
9203}
9204
9205bool isVPMOVSWB(unsigned Opcode) {
9206 switch (Opcode) {
9207 case VPMOVSWBZ128mr:
9208 case VPMOVSWBZ128mrk:
9209 case VPMOVSWBZ128rr:
9210 case VPMOVSWBZ128rrk:
9211 case VPMOVSWBZ128rrkz:
9212 case VPMOVSWBZ256mr:
9213 case VPMOVSWBZ256mrk:
9214 case VPMOVSWBZ256rr:
9215 case VPMOVSWBZ256rrk:
9216 case VPMOVSWBZ256rrkz:
9217 case VPMOVSWBZmr:
9218 case VPMOVSWBZmrk:
9219 case VPMOVSWBZrr:
9220 case VPMOVSWBZrrk:
9221 case VPMOVSWBZrrkz:
9222 return true;
9223 }
9224 return false;
9225}
9226
9227bool isVPANDNQ(unsigned Opcode) {
9228 switch (Opcode) {
9229 case VPANDNQZ128rm:
9230 case VPANDNQZ128rmb:
9231 case VPANDNQZ128rmbk:
9232 case VPANDNQZ128rmbkz:
9233 case VPANDNQZ128rmk:
9234 case VPANDNQZ128rmkz:
9235 case VPANDNQZ128rr:
9236 case VPANDNQZ128rrk:
9237 case VPANDNQZ128rrkz:
9238 case VPANDNQZ256rm:
9239 case VPANDNQZ256rmb:
9240 case VPANDNQZ256rmbk:
9241 case VPANDNQZ256rmbkz:
9242 case VPANDNQZ256rmk:
9243 case VPANDNQZ256rmkz:
9244 case VPANDNQZ256rr:
9245 case VPANDNQZ256rrk:
9246 case VPANDNQZ256rrkz:
9247 case VPANDNQZrm:
9248 case VPANDNQZrmb:
9249 case VPANDNQZrmbk:
9250 case VPANDNQZrmbkz:
9251 case VPANDNQZrmk:
9252 case VPANDNQZrmkz:
9253 case VPANDNQZrr:
9254 case VPANDNQZrrk:
9255 case VPANDNQZrrkz:
9256 return true;
9257 }
9258 return false;
9259}
9260
9261bool isSYSENTER(unsigned Opcode) {
9262 return Opcode == SYSENTER;
9263}
9264
9265bool isVPHADDWD(unsigned Opcode) {
9266 switch (Opcode) {
9267 case VPHADDWDrm:
9268 case VPHADDWDrr:
9269 return true;
9270 }
9271 return false;
9272}
9273
9274bool isVMOVHPD(unsigned Opcode) {
9275 switch (Opcode) {
9276 case VMOVHPDZ128mr:
9277 case VMOVHPDZ128rm:
9278 case VMOVHPDmr:
9279 case VMOVHPDrm:
9280 return true;
9281 }
9282 return false;
9283}
9284
9285bool isMOVHPD(unsigned Opcode) {
9286 switch (Opcode) {
9287 case MOVHPDmr:
9288 case MOVHPDrm:
9289 return true;
9290 }
9291 return false;
9292}
9293
9294bool isVDIVPH(unsigned Opcode) {
9295 switch (Opcode) {
9296 case VDIVPHZ128rm:
9297 case VDIVPHZ128rmb:
9298 case VDIVPHZ128rmbk:
9299 case VDIVPHZ128rmbkz:
9300 case VDIVPHZ128rmk:
9301 case VDIVPHZ128rmkz:
9302 case VDIVPHZ128rr:
9303 case VDIVPHZ128rrk:
9304 case VDIVPHZ128rrkz:
9305 case VDIVPHZ256rm:
9306 case VDIVPHZ256rmb:
9307 case VDIVPHZ256rmbk:
9308 case VDIVPHZ256rmbkz:
9309 case VDIVPHZ256rmk:
9310 case VDIVPHZ256rmkz:
9311 case VDIVPHZ256rr:
9312 case VDIVPHZ256rrk:
9313 case VDIVPHZ256rrkz:
9314 case VDIVPHZrm:
9315 case VDIVPHZrmb:
9316 case VDIVPHZrmbk:
9317 case VDIVPHZrmbkz:
9318 case VDIVPHZrmk:
9319 case VDIVPHZrmkz:
9320 case VDIVPHZrr:
9321 case VDIVPHZrrb:
9322 case VDIVPHZrrbk:
9323 case VDIVPHZrrbkz:
9324 case VDIVPHZrrk:
9325 case VDIVPHZrrkz:
9326 return true;
9327 }
9328 return false;
9329}
9330
9331bool isFFREE(unsigned Opcode) {
9332 return Opcode == FFREE;
9333}
9334
9335bool isVGATHERPF1DPS(unsigned Opcode) {
9336 return Opcode == VGATHERPF1DPSm;
9337}
9338
9339bool isVFNMADD231PD(unsigned Opcode) {
9340 switch (Opcode) {
9341 case VFNMADD231PDYm:
9342 case VFNMADD231PDYr:
9343 case VFNMADD231PDZ128m:
9344 case VFNMADD231PDZ128mb:
9345 case VFNMADD231PDZ128mbk:
9346 case VFNMADD231PDZ128mbkz:
9347 case VFNMADD231PDZ128mk:
9348 case VFNMADD231PDZ128mkz:
9349 case VFNMADD231PDZ128r:
9350 case VFNMADD231PDZ128rk:
9351 case VFNMADD231PDZ128rkz:
9352 case VFNMADD231PDZ256m:
9353 case VFNMADD231PDZ256mb:
9354 case VFNMADD231PDZ256mbk:
9355 case VFNMADD231PDZ256mbkz:
9356 case VFNMADD231PDZ256mk:
9357 case VFNMADD231PDZ256mkz:
9358 case VFNMADD231PDZ256r:
9359 case VFNMADD231PDZ256rk:
9360 case VFNMADD231PDZ256rkz:
9361 case VFNMADD231PDZm:
9362 case VFNMADD231PDZmb:
9363 case VFNMADD231PDZmbk:
9364 case VFNMADD231PDZmbkz:
9365 case VFNMADD231PDZmk:
9366 case VFNMADD231PDZmkz:
9367 case VFNMADD231PDZr:
9368 case VFNMADD231PDZrb:
9369 case VFNMADD231PDZrbk:
9370 case VFNMADD231PDZrbkz:
9371 case VFNMADD231PDZrk:
9372 case VFNMADD231PDZrkz:
9373 case VFNMADD231PDm:
9374 case VFNMADD231PDr:
9375 return true;
9376 }
9377 return false;
9378}
9379
9380bool isVFCMULCPH(unsigned Opcode) {
9381 switch (Opcode) {
9382 case VFCMULCPHZ128rm:
9383 case VFCMULCPHZ128rmb:
9384 case VFCMULCPHZ128rmbk:
9385 case VFCMULCPHZ128rmbkz:
9386 case VFCMULCPHZ128rmk:
9387 case VFCMULCPHZ128rmkz:
9388 case VFCMULCPHZ128rr:
9389 case VFCMULCPHZ128rrk:
9390 case VFCMULCPHZ128rrkz:
9391 case VFCMULCPHZ256rm:
9392 case VFCMULCPHZ256rmb:
9393 case VFCMULCPHZ256rmbk:
9394 case VFCMULCPHZ256rmbkz:
9395 case VFCMULCPHZ256rmk:
9396 case VFCMULCPHZ256rmkz:
9397 case VFCMULCPHZ256rr:
9398 case VFCMULCPHZ256rrk:
9399 case VFCMULCPHZ256rrkz:
9400 case VFCMULCPHZrm:
9401 case VFCMULCPHZrmb:
9402 case VFCMULCPHZrmbk:
9403 case VFCMULCPHZrmbkz:
9404 case VFCMULCPHZrmk:
9405 case VFCMULCPHZrmkz:
9406 case VFCMULCPHZrr:
9407 case VFCMULCPHZrrb:
9408 case VFCMULCPHZrrbk:
9409 case VFCMULCPHZrrbkz:
9410 case VFCMULCPHZrrk:
9411 case VFCMULCPHZrrkz:
9412 return true;
9413 }
9414 return false;
9415}
9416
9417bool isVPADDD(unsigned Opcode) {
9418 switch (Opcode) {
9419 case VPADDDYrm:
9420 case VPADDDYrr:
9421 case VPADDDZ128rm:
9422 case VPADDDZ128rmb:
9423 case VPADDDZ128rmbk:
9424 case VPADDDZ128rmbkz:
9425 case VPADDDZ128rmk:
9426 case VPADDDZ128rmkz:
9427 case VPADDDZ128rr:
9428 case VPADDDZ128rrk:
9429 case VPADDDZ128rrkz:
9430 case VPADDDZ256rm:
9431 case VPADDDZ256rmb:
9432 case VPADDDZ256rmbk:
9433 case VPADDDZ256rmbkz:
9434 case VPADDDZ256rmk:
9435 case VPADDDZ256rmkz:
9436 case VPADDDZ256rr:
9437 case VPADDDZ256rrk:
9438 case VPADDDZ256rrkz:
9439 case VPADDDZrm:
9440 case VPADDDZrmb:
9441 case VPADDDZrmbk:
9442 case VPADDDZrmbkz:
9443 case VPADDDZrmk:
9444 case VPADDDZrmkz:
9445 case VPADDDZrr:
9446 case VPADDDZrrk:
9447 case VPADDDZrrkz:
9448 case VPADDDrm:
9449 case VPADDDrr:
9450 return true;
9451 }
9452 return false;
9453}
9454
9455bool isVSM3MSG2(unsigned Opcode) {
9456 switch (Opcode) {
9457 case VSM3MSG2rm:
9458 case VSM3MSG2rr:
9459 return true;
9460 }
9461 return false;
9462}
9463
9464bool isVPCOMUQ(unsigned Opcode) {
9465 switch (Opcode) {
9466 case VPCOMUQmi:
9467 case VPCOMUQri:
9468 return true;
9469 }
9470 return false;
9471}
9472
9473bool isVERR(unsigned Opcode) {
9474 switch (Opcode) {
9475 case VERRm:
9476 case VERRr:
9477 return true;
9478 }
9479 return false;
9480}
9481
9482bool isKORTESTQ(unsigned Opcode) {
9483 return Opcode == KORTESTQkk;
9484}
9485
9486bool isVFMSUB132SD(unsigned Opcode) {
9487 switch (Opcode) {
9488 case VFMSUB132SDZm_Int:
9489 case VFMSUB132SDZmk_Int:
9490 case VFMSUB132SDZmkz_Int:
9491 case VFMSUB132SDZr_Int:
9492 case VFMSUB132SDZrb_Int:
9493 case VFMSUB132SDZrbk_Int:
9494 case VFMSUB132SDZrbkz_Int:
9495 case VFMSUB132SDZrk_Int:
9496 case VFMSUB132SDZrkz_Int:
9497 case VFMSUB132SDm_Int:
9498 case VFMSUB132SDr_Int:
9499 return true;
9500 }
9501 return false;
9502}
9503
9504bool isTILEZERO(unsigned Opcode) {
9505 return Opcode == TILEZERO;
9506}
9507
9508bool isPFADD(unsigned Opcode) {
9509 switch (Opcode) {
9510 case PFADDrm:
9511 case PFADDrr:
9512 return true;
9513 }
9514 return false;
9515}
9516
9517bool isVCVTSI2SD(unsigned Opcode) {
9518 switch (Opcode) {
9519 case VCVTSI2SDZrm_Int:
9520 case VCVTSI2SDZrr_Int:
9521 case VCVTSI2SDrm_Int:
9522 case VCVTSI2SDrr_Int:
9523 case VCVTSI642SDZrm_Int:
9524 case VCVTSI642SDZrr_Int:
9525 case VCVTSI642SDZrrb_Int:
9526 case VCVTSI642SDrm_Int:
9527 case VCVTSI642SDrr_Int:
9528 return true;
9529 }
9530 return false;
9531}
9532
9533bool isTILELOADDRS(unsigned Opcode) {
9534 switch (Opcode) {
9535 case TILELOADDRS:
9536 case TILELOADDRS_EVEX:
9537 return true;
9538 }
9539 return false;
9540}
9541
9542bool isVSTMXCSR(unsigned Opcode) {
9543 return Opcode == VSTMXCSR;
9544}
9545
9546bool isVCVTTSH2SI(unsigned Opcode) {
9547 switch (Opcode) {
9548 case VCVTTSH2SI64Zrm_Int:
9549 case VCVTTSH2SI64Zrr_Int:
9550 case VCVTTSH2SI64Zrrb_Int:
9551 case VCVTTSH2SIZrm_Int:
9552 case VCVTTSH2SIZrr_Int:
9553 case VCVTTSH2SIZrrb_Int:
9554 return true;
9555 }
9556 return false;
9557}
9558
9559bool isRET(unsigned Opcode) {
9560 switch (Opcode) {
9561 case RET16:
9562 case RET32:
9563 case RET64:
9564 case RETI16:
9565 case RETI32:
9566 case RETI64:
9567 return true;
9568 }
9569 return false;
9570}
9571
9572bool isLZCNT(unsigned Opcode) {
9573 switch (Opcode) {
9574 case LZCNT16rm:
9575 case LZCNT16rm_EVEX:
9576 case LZCNT16rm_NF:
9577 case LZCNT16rr:
9578 case LZCNT16rr_EVEX:
9579 case LZCNT16rr_NF:
9580 case LZCNT32rm:
9581 case LZCNT32rm_EVEX:
9582 case LZCNT32rm_NF:
9583 case LZCNT32rr:
9584 case LZCNT32rr_EVEX:
9585 case LZCNT32rr_NF:
9586 case LZCNT64rm:
9587 case LZCNT64rm_EVEX:
9588 case LZCNT64rm_NF:
9589 case LZCNT64rr:
9590 case LZCNT64rr_EVEX:
9591 case LZCNT64rr_NF:
9592 return true;
9593 }
9594 return false;
9595}
9596
9597bool isMULPD(unsigned Opcode) {
9598 switch (Opcode) {
9599 case MULPDrm:
9600 case MULPDrr:
9601 return true;
9602 }
9603 return false;
9604}
9605
9606bool isVBROADCASTI32X2(unsigned Opcode) {
9607 switch (Opcode) {
9608 case VBROADCASTI32X2Z128rm:
9609 case VBROADCASTI32X2Z128rmk:
9610 case VBROADCASTI32X2Z128rmkz:
9611 case VBROADCASTI32X2Z128rr:
9612 case VBROADCASTI32X2Z128rrk:
9613 case VBROADCASTI32X2Z128rrkz:
9614 case VBROADCASTI32X2Z256rm:
9615 case VBROADCASTI32X2Z256rmk:
9616 case VBROADCASTI32X2Z256rmkz:
9617 case VBROADCASTI32X2Z256rr:
9618 case VBROADCASTI32X2Z256rrk:
9619 case VBROADCASTI32X2Z256rrkz:
9620 case VBROADCASTI32X2Zrm:
9621 case VBROADCASTI32X2Zrmk:
9622 case VBROADCASTI32X2Zrmkz:
9623 case VBROADCASTI32X2Zrr:
9624 case VBROADCASTI32X2Zrrk:
9625 case VBROADCASTI32X2Zrrkz:
9626 return true;
9627 }
9628 return false;
9629}
9630
9631bool isVCVTPH2W(unsigned Opcode) {
9632 switch (Opcode) {
9633 case VCVTPH2WZ128rm:
9634 case VCVTPH2WZ128rmb:
9635 case VCVTPH2WZ128rmbk:
9636 case VCVTPH2WZ128rmbkz:
9637 case VCVTPH2WZ128rmk:
9638 case VCVTPH2WZ128rmkz:
9639 case VCVTPH2WZ128rr:
9640 case VCVTPH2WZ128rrk:
9641 case VCVTPH2WZ128rrkz:
9642 case VCVTPH2WZ256rm:
9643 case VCVTPH2WZ256rmb:
9644 case VCVTPH2WZ256rmbk:
9645 case VCVTPH2WZ256rmbkz:
9646 case VCVTPH2WZ256rmk:
9647 case VCVTPH2WZ256rmkz:
9648 case VCVTPH2WZ256rr:
9649 case VCVTPH2WZ256rrk:
9650 case VCVTPH2WZ256rrkz:
9651 case VCVTPH2WZrm:
9652 case VCVTPH2WZrmb:
9653 case VCVTPH2WZrmbk:
9654 case VCVTPH2WZrmbkz:
9655 case VCVTPH2WZrmk:
9656 case VCVTPH2WZrmkz:
9657 case VCVTPH2WZrr:
9658 case VCVTPH2WZrrb:
9659 case VCVTPH2WZrrbk:
9660 case VCVTPH2WZrrbkz:
9661 case VCVTPH2WZrrk:
9662 case VCVTPH2WZrrkz:
9663 return true;
9664 }
9665 return false;
9666}
9667
9668bool isCQO(unsigned Opcode) {
9669 return Opcode == CQO;
9670}
9671
9672bool isFSUBR(unsigned Opcode) {
9673 switch (Opcode) {
9674 case SUBR_F32m:
9675 case SUBR_F64m:
9676 case SUBR_FST0r:
9677 case SUBR_FrST0:
9678 return true;
9679 }
9680 return false;
9681}
9682
9683bool isDPPD(unsigned Opcode) {
9684 switch (Opcode) {
9685 case DPPDrmi:
9686 case DPPDrri:
9687 return true;
9688 }
9689 return false;
9690}
9691
9692bool isFCOS(unsigned Opcode) {
9693 return Opcode == FCOS;
9694}
9695
9696bool isXSAVES(unsigned Opcode) {
9697 return Opcode == XSAVES;
9698}
9699
9700bool isTZCNT(unsigned Opcode) {
9701 switch (Opcode) {
9702 case TZCNT16rm:
9703 case TZCNT16rm_EVEX:
9704 case TZCNT16rm_NF:
9705 case TZCNT16rr:
9706 case TZCNT16rr_EVEX:
9707 case TZCNT16rr_NF:
9708 case TZCNT32rm:
9709 case TZCNT32rm_EVEX:
9710 case TZCNT32rm_NF:
9711 case TZCNT32rr:
9712 case TZCNT32rr_EVEX:
9713 case TZCNT32rr_NF:
9714 case TZCNT64rm:
9715 case TZCNT64rm_EVEX:
9716 case TZCNT64rm_NF:
9717 case TZCNT64rr:
9718 case TZCNT64rr_EVEX:
9719 case TZCNT64rr_NF:
9720 return true;
9721 }
9722 return false;
9723}
9724
9725bool isLJMP(unsigned Opcode) {
9726 switch (Opcode) {
9727 case FARJMP16i:
9728 case FARJMP16m:
9729 case FARJMP32i:
9730 case FARJMP64m:
9731 return true;
9732 }
9733 return false;
9734}
9735
9736bool isCMOVCC(unsigned Opcode) {
9737 switch (Opcode) {
9738 case CMOV16rm:
9739 case CMOV16rm_ND:
9740 case CMOV16rr:
9741 case CMOV16rr_ND:
9742 case CMOV32rm:
9743 case CMOV32rm_ND:
9744 case CMOV32rr:
9745 case CMOV32rr_ND:
9746 case CMOV64rm:
9747 case CMOV64rm_ND:
9748 case CMOV64rr:
9749 case CMOV64rr_ND:
9750 return true;
9751 }
9752 return false;
9753}
9754
9755bool isVCVTBIASPH2HF8(unsigned Opcode) {
9756 switch (Opcode) {
9757 case VCVTBIASPH2HF8Z128rm:
9758 case VCVTBIASPH2HF8Z128rmb:
9759 case VCVTBIASPH2HF8Z128rmbk:
9760 case VCVTBIASPH2HF8Z128rmbkz:
9761 case VCVTBIASPH2HF8Z128rmk:
9762 case VCVTBIASPH2HF8Z128rmkz:
9763 case VCVTBIASPH2HF8Z128rr:
9764 case VCVTBIASPH2HF8Z128rrk:
9765 case VCVTBIASPH2HF8Z128rrkz:
9766 case VCVTBIASPH2HF8Z256rm:
9767 case VCVTBIASPH2HF8Z256rmb:
9768 case VCVTBIASPH2HF8Z256rmbk:
9769 case VCVTBIASPH2HF8Z256rmbkz:
9770 case VCVTBIASPH2HF8Z256rmk:
9771 case VCVTBIASPH2HF8Z256rmkz:
9772 case VCVTBIASPH2HF8Z256rr:
9773 case VCVTBIASPH2HF8Z256rrk:
9774 case VCVTBIASPH2HF8Z256rrkz:
9775 case VCVTBIASPH2HF8Zrm:
9776 case VCVTBIASPH2HF8Zrmb:
9777 case VCVTBIASPH2HF8Zrmbk:
9778 case VCVTBIASPH2HF8Zrmbkz:
9779 case VCVTBIASPH2HF8Zrmk:
9780 case VCVTBIASPH2HF8Zrmkz:
9781 case VCVTBIASPH2HF8Zrr:
9782 case VCVTBIASPH2HF8Zrrk:
9783 case VCVTBIASPH2HF8Zrrkz:
9784 return true;
9785 }
9786 return false;
9787}
9788
9789bool isINVEPT(unsigned Opcode) {
9790 switch (Opcode) {
9791 case INVEPT32:
9792 case INVEPT64:
9793 case INVEPT64_EVEX:
9794 return true;
9795 }
9796 return false;
9797}
9798
9799bool isADDSUBPD(unsigned Opcode) {
9800 switch (Opcode) {
9801 case ADDSUBPDrm:
9802 case ADDSUBPDrr:
9803 return true;
9804 }
9805 return false;
9806}
9807
9808bool isVMOVSHDUP(unsigned Opcode) {
9809 switch (Opcode) {
9810 case VMOVSHDUPYrm:
9811 case VMOVSHDUPYrr:
9812 case VMOVSHDUPZ128rm:
9813 case VMOVSHDUPZ128rmk:
9814 case VMOVSHDUPZ128rmkz:
9815 case VMOVSHDUPZ128rr:
9816 case VMOVSHDUPZ128rrk:
9817 case VMOVSHDUPZ128rrkz:
9818 case VMOVSHDUPZ256rm:
9819 case VMOVSHDUPZ256rmk:
9820 case VMOVSHDUPZ256rmkz:
9821 case VMOVSHDUPZ256rr:
9822 case VMOVSHDUPZ256rrk:
9823 case VMOVSHDUPZ256rrkz:
9824 case VMOVSHDUPZrm:
9825 case VMOVSHDUPZrmk:
9826 case VMOVSHDUPZrmkz:
9827 case VMOVSHDUPZrr:
9828 case VMOVSHDUPZrrk:
9829 case VMOVSHDUPZrrkz:
9830 case VMOVSHDUPrm:
9831 case VMOVSHDUPrr:
9832 return true;
9833 }
9834 return false;
9835}
9836
9837bool isKSHIFTRD(unsigned Opcode) {
9838 return Opcode == KSHIFTRDki;
9839}
9840
9841bool isVCVTSS2SD(unsigned Opcode) {
9842 switch (Opcode) {
9843 case VCVTSS2SDZrm_Int:
9844 case VCVTSS2SDZrmk_Int:
9845 case VCVTSS2SDZrmkz_Int:
9846 case VCVTSS2SDZrr_Int:
9847 case VCVTSS2SDZrrb_Int:
9848 case VCVTSS2SDZrrbk_Int:
9849 case VCVTSS2SDZrrbkz_Int:
9850 case VCVTSS2SDZrrk_Int:
9851 case VCVTSS2SDZrrkz_Int:
9852 case VCVTSS2SDrm_Int:
9853 case VCVTSS2SDrr_Int:
9854 return true;
9855 }
9856 return false;
9857}
9858
9859bool isPADDQ(unsigned Opcode) {
9860 switch (Opcode) {
9861 case MMX_PADDQrm:
9862 case MMX_PADDQrr:
9863 case PADDQrm:
9864 case PADDQrr:
9865 return true;
9866 }
9867 return false;
9868}
9869
9870bool isVEXTRACTI64X4(unsigned Opcode) {
9871 switch (Opcode) {
9872 case VEXTRACTI64X4Zmri:
9873 case VEXTRACTI64X4Zmrik:
9874 case VEXTRACTI64X4Zrri:
9875 case VEXTRACTI64X4Zrrik:
9876 case VEXTRACTI64X4Zrrikz:
9877 return true;
9878 }
9879 return false;
9880}
9881
9882bool isVFMSUB231SS(unsigned Opcode) {
9883 switch (Opcode) {
9884 case VFMSUB231SSZm_Int:
9885 case VFMSUB231SSZmk_Int:
9886 case VFMSUB231SSZmkz_Int:
9887 case VFMSUB231SSZr_Int:
9888 case VFMSUB231SSZrb_Int:
9889 case VFMSUB231SSZrbk_Int:
9890 case VFMSUB231SSZrbkz_Int:
9891 case VFMSUB231SSZrk_Int:
9892 case VFMSUB231SSZrkz_Int:
9893 case VFMSUB231SSm_Int:
9894 case VFMSUB231SSr_Int:
9895 return true;
9896 }
9897 return false;
9898}
9899
9900bool isVPCMPEQB(unsigned Opcode) {
9901 switch (Opcode) {
9902 case VPCMPEQBYrm:
9903 case VPCMPEQBYrr:
9904 case VPCMPEQBZ128rm:
9905 case VPCMPEQBZ128rmk:
9906 case VPCMPEQBZ128rr:
9907 case VPCMPEQBZ128rrk:
9908 case VPCMPEQBZ256rm:
9909 case VPCMPEQBZ256rmk:
9910 case VPCMPEQBZ256rr:
9911 case VPCMPEQBZ256rrk:
9912 case VPCMPEQBZrm:
9913 case VPCMPEQBZrmk:
9914 case VPCMPEQBZrr:
9915 case VPCMPEQBZrrk:
9916 case VPCMPEQBrm:
9917 case VPCMPEQBrr:
9918 return true;
9919 }
9920 return false;
9921}
9922
9923bool isVPTERNLOGD(unsigned Opcode) {
9924 switch (Opcode) {
9925 case VPTERNLOGDZ128rmbi:
9926 case VPTERNLOGDZ128rmbik:
9927 case VPTERNLOGDZ128rmbikz:
9928 case VPTERNLOGDZ128rmi:
9929 case VPTERNLOGDZ128rmik:
9930 case VPTERNLOGDZ128rmikz:
9931 case VPTERNLOGDZ128rri:
9932 case VPTERNLOGDZ128rrik:
9933 case VPTERNLOGDZ128rrikz:
9934 case VPTERNLOGDZ256rmbi:
9935 case VPTERNLOGDZ256rmbik:
9936 case VPTERNLOGDZ256rmbikz:
9937 case VPTERNLOGDZ256rmi:
9938 case VPTERNLOGDZ256rmik:
9939 case VPTERNLOGDZ256rmikz:
9940 case VPTERNLOGDZ256rri:
9941 case VPTERNLOGDZ256rrik:
9942 case VPTERNLOGDZ256rrikz:
9943 case VPTERNLOGDZrmbi:
9944 case VPTERNLOGDZrmbik:
9945 case VPTERNLOGDZrmbikz:
9946 case VPTERNLOGDZrmi:
9947 case VPTERNLOGDZrmik:
9948 case VPTERNLOGDZrmikz:
9949 case VPTERNLOGDZrri:
9950 case VPTERNLOGDZrrik:
9951 case VPTERNLOGDZrrikz:
9952 return true;
9953 }
9954 return false;
9955}
9956
9957bool isLEA(unsigned Opcode) {
9958 switch (Opcode) {
9959 case LEA16r:
9960 case LEA32r:
9961 case LEA64_32r:
9962 case LEA64r:
9963 return true;
9964 }
9965 return false;
9966}
9967
9968bool isPSUBB(unsigned Opcode) {
9969 switch (Opcode) {
9970 case MMX_PSUBBrm:
9971 case MMX_PSUBBrr:
9972 case PSUBBrm:
9973 case PSUBBrr:
9974 return true;
9975 }
9976 return false;
9977}
9978
9979bool isKADDQ(unsigned Opcode) {
9980 return Opcode == KADDQkk;
9981}
9982
9983bool isMOVSX(unsigned Opcode) {
9984 switch (Opcode) {
9985 case MOVSX16rm16:
9986 case MOVSX16rm8:
9987 case MOVSX16rr16:
9988 case MOVSX16rr8:
9989 case MOVSX32rm16:
9990 case MOVSX32rm8:
9991 case MOVSX32rr16:
9992 case MOVSX32rr8:
9993 case MOVSX64rm16:
9994 case MOVSX64rm8:
9995 case MOVSX64rr16:
9996 case MOVSX64rr8:
9997 return true;
9998 }
9999 return false;
10000}
10001
10002bool isVALIGNQ(unsigned Opcode) {
10003 switch (Opcode) {
10004 case VALIGNQZ128rmbi:
10005 case VALIGNQZ128rmbik:
10006 case VALIGNQZ128rmbikz:
10007 case VALIGNQZ128rmi:
10008 case VALIGNQZ128rmik:
10009 case VALIGNQZ128rmikz:
10010 case VALIGNQZ128rri:
10011 case VALIGNQZ128rrik:
10012 case VALIGNQZ128rrikz:
10013 case VALIGNQZ256rmbi:
10014 case VALIGNQZ256rmbik:
10015 case VALIGNQZ256rmbikz:
10016 case VALIGNQZ256rmi:
10017 case VALIGNQZ256rmik:
10018 case VALIGNQZ256rmikz:
10019 case VALIGNQZ256rri:
10020 case VALIGNQZ256rrik:
10021 case VALIGNQZ256rrikz:
10022 case VALIGNQZrmbi:
10023 case VALIGNQZrmbik:
10024 case VALIGNQZrmbikz:
10025 case VALIGNQZrmi:
10026 case VALIGNQZrmik:
10027 case VALIGNQZrmikz:
10028 case VALIGNQZrri:
10029 case VALIGNQZrrik:
10030 case VALIGNQZrrikz:
10031 return true;
10032 }
10033 return false;
10034}
10035
10036bool isVCVTNE2PS2BF16(unsigned Opcode) {
10037 switch (Opcode) {
10038 case VCVTNE2PS2BF16Z128rm:
10039 case VCVTNE2PS2BF16Z128rmb:
10040 case VCVTNE2PS2BF16Z128rmbk:
10041 case VCVTNE2PS2BF16Z128rmbkz:
10042 case VCVTNE2PS2BF16Z128rmk:
10043 case VCVTNE2PS2BF16Z128rmkz:
10044 case VCVTNE2PS2BF16Z128rr:
10045 case VCVTNE2PS2BF16Z128rrk:
10046 case VCVTNE2PS2BF16Z128rrkz:
10047 case VCVTNE2PS2BF16Z256rm:
10048 case VCVTNE2PS2BF16Z256rmb:
10049 case VCVTNE2PS2BF16Z256rmbk:
10050 case VCVTNE2PS2BF16Z256rmbkz:
10051 case VCVTNE2PS2BF16Z256rmk:
10052 case VCVTNE2PS2BF16Z256rmkz:
10053 case VCVTNE2PS2BF16Z256rr:
10054 case VCVTNE2PS2BF16Z256rrk:
10055 case VCVTNE2PS2BF16Z256rrkz:
10056 case VCVTNE2PS2BF16Zrm:
10057 case VCVTNE2PS2BF16Zrmb:
10058 case VCVTNE2PS2BF16Zrmbk:
10059 case VCVTNE2PS2BF16Zrmbkz:
10060 case VCVTNE2PS2BF16Zrmk:
10061 case VCVTNE2PS2BF16Zrmkz:
10062 case VCVTNE2PS2BF16Zrr:
10063 case VCVTNE2PS2BF16Zrrk:
10064 case VCVTNE2PS2BF16Zrrkz:
10065 return true;
10066 }
10067 return false;
10068}
10069
10070bool isVPSRAW(unsigned Opcode) {
10071 switch (Opcode) {
10072 case VPSRAWYri:
10073 case VPSRAWYrm:
10074 case VPSRAWYrr:
10075 case VPSRAWZ128mi:
10076 case VPSRAWZ128mik:
10077 case VPSRAWZ128mikz:
10078 case VPSRAWZ128ri:
10079 case VPSRAWZ128rik:
10080 case VPSRAWZ128rikz:
10081 case VPSRAWZ128rm:
10082 case VPSRAWZ128rmk:
10083 case VPSRAWZ128rmkz:
10084 case VPSRAWZ128rr:
10085 case VPSRAWZ128rrk:
10086 case VPSRAWZ128rrkz:
10087 case VPSRAWZ256mi:
10088 case VPSRAWZ256mik:
10089 case VPSRAWZ256mikz:
10090 case VPSRAWZ256ri:
10091 case VPSRAWZ256rik:
10092 case VPSRAWZ256rikz:
10093 case VPSRAWZ256rm:
10094 case VPSRAWZ256rmk:
10095 case VPSRAWZ256rmkz:
10096 case VPSRAWZ256rr:
10097 case VPSRAWZ256rrk:
10098 case VPSRAWZ256rrkz:
10099 case VPSRAWZmi:
10100 case VPSRAWZmik:
10101 case VPSRAWZmikz:
10102 case VPSRAWZri:
10103 case VPSRAWZrik:
10104 case VPSRAWZrikz:
10105 case VPSRAWZrm:
10106 case VPSRAWZrmk:
10107 case VPSRAWZrmkz:
10108 case VPSRAWZrr:
10109 case VPSRAWZrrk:
10110 case VPSRAWZrrkz:
10111 case VPSRAWri:
10112 case VPSRAWrm:
10113 case VPSRAWrr:
10114 return true;
10115 }
10116 return false;
10117}
10118
10119bool isVFMSUBADD231PH(unsigned Opcode) {
10120 switch (Opcode) {
10121 case VFMSUBADD231PHZ128m:
10122 case VFMSUBADD231PHZ128mb:
10123 case VFMSUBADD231PHZ128mbk:
10124 case VFMSUBADD231PHZ128mbkz:
10125 case VFMSUBADD231PHZ128mk:
10126 case VFMSUBADD231PHZ128mkz:
10127 case VFMSUBADD231PHZ128r:
10128 case VFMSUBADD231PHZ128rk:
10129 case VFMSUBADD231PHZ128rkz:
10130 case VFMSUBADD231PHZ256m:
10131 case VFMSUBADD231PHZ256mb:
10132 case VFMSUBADD231PHZ256mbk:
10133 case VFMSUBADD231PHZ256mbkz:
10134 case VFMSUBADD231PHZ256mk:
10135 case VFMSUBADD231PHZ256mkz:
10136 case VFMSUBADD231PHZ256r:
10137 case VFMSUBADD231PHZ256rk:
10138 case VFMSUBADD231PHZ256rkz:
10139 case VFMSUBADD231PHZm:
10140 case VFMSUBADD231PHZmb:
10141 case VFMSUBADD231PHZmbk:
10142 case VFMSUBADD231PHZmbkz:
10143 case VFMSUBADD231PHZmk:
10144 case VFMSUBADD231PHZmkz:
10145 case VFMSUBADD231PHZr:
10146 case VFMSUBADD231PHZrb:
10147 case VFMSUBADD231PHZrbk:
10148 case VFMSUBADD231PHZrbkz:
10149 case VFMSUBADD231PHZrk:
10150 case VFMSUBADD231PHZrkz:
10151 return true;
10152 }
10153 return false;
10154}
10155
10156bool isCVTDQ2PS(unsigned Opcode) {
10157 switch (Opcode) {
10158 case CVTDQ2PSrm:
10159 case CVTDQ2PSrr:
10160 return true;
10161 }
10162 return false;
10163}
10164
10165bool isFBLD(unsigned Opcode) {
10166 return Opcode == FBLDm;
10167}
10168
10169bool isLMSW(unsigned Opcode) {
10170 switch (Opcode) {
10171 case LMSW16m:
10172 case LMSW16r:
10173 return true;
10174 }
10175 return false;
10176}
10177
10178bool isWRMSR(unsigned Opcode) {
10179 return Opcode == WRMSR;
10180}
10181
10182bool isMINSS(unsigned Opcode) {
10183 switch (Opcode) {
10184 case MINSSrm_Int:
10185 case MINSSrr_Int:
10186 return true;
10187 }
10188 return false;
10189}
10190
10191bool isFSCALE(unsigned Opcode) {
10192 return Opcode == FSCALE;
10193}
10194
10195bool isVFNMADD213SH(unsigned Opcode) {
10196 switch (Opcode) {
10197 case VFNMADD213SHZm_Int:
10198 case VFNMADD213SHZmk_Int:
10199 case VFNMADD213SHZmkz_Int:
10200 case VFNMADD213SHZr_Int:
10201 case VFNMADD213SHZrb_Int:
10202 case VFNMADD213SHZrbk_Int:
10203 case VFNMADD213SHZrbkz_Int:
10204 case VFNMADD213SHZrk_Int:
10205 case VFNMADD213SHZrkz_Int:
10206 return true;
10207 }
10208 return false;
10209}
10210
10211bool isIMULZU(unsigned Opcode) {
10212 switch (Opcode) {
10213 case IMULZU16rmi:
10214 case IMULZU16rmi8:
10215 case IMULZU16rri:
10216 case IMULZU16rri8:
10217 case IMULZU32rmi:
10218 case IMULZU32rmi8:
10219 case IMULZU32rri:
10220 case IMULZU32rri8:
10221 case IMULZU64rmi32:
10222 case IMULZU64rmi8:
10223 case IMULZU64rri32:
10224 case IMULZU64rri8:
10225 return true;
10226 }
10227 return false;
10228}
10229
10230bool isVPHADDUBD(unsigned Opcode) {
10231 switch (Opcode) {
10232 case VPHADDUBDrm:
10233 case VPHADDUBDrr:
10234 return true;
10235 }
10236 return false;
10237}
10238
10239bool isRDSSPQ(unsigned Opcode) {
10240 return Opcode == RDSSPQ;
10241}
10242
10243bool isVCVTBF162IBS(unsigned Opcode) {
10244 switch (Opcode) {
10245 case VCVTBF162IBSZ128rm:
10246 case VCVTBF162IBSZ128rmb:
10247 case VCVTBF162IBSZ128rmbk:
10248 case VCVTBF162IBSZ128rmbkz:
10249 case VCVTBF162IBSZ128rmk:
10250 case VCVTBF162IBSZ128rmkz:
10251 case VCVTBF162IBSZ128rr:
10252 case VCVTBF162IBSZ128rrk:
10253 case VCVTBF162IBSZ128rrkz:
10254 case VCVTBF162IBSZ256rm:
10255 case VCVTBF162IBSZ256rmb:
10256 case VCVTBF162IBSZ256rmbk:
10257 case VCVTBF162IBSZ256rmbkz:
10258 case VCVTBF162IBSZ256rmk:
10259 case VCVTBF162IBSZ256rmkz:
10260 case VCVTBF162IBSZ256rr:
10261 case VCVTBF162IBSZ256rrk:
10262 case VCVTBF162IBSZ256rrkz:
10263 case VCVTBF162IBSZrm:
10264 case VCVTBF162IBSZrmb:
10265 case VCVTBF162IBSZrmbk:
10266 case VCVTBF162IBSZrmbkz:
10267 case VCVTBF162IBSZrmk:
10268 case VCVTBF162IBSZrmkz:
10269 case VCVTBF162IBSZrr:
10270 case VCVTBF162IBSZrrk:
10271 case VCVTBF162IBSZrrkz:
10272 return true;
10273 }
10274 return false;
10275}
10276
10277bool isLGDT(unsigned Opcode) {
10278 return Opcode == LGDT64m;
10279}
10280
10281bool isVPSHLDVD(unsigned Opcode) {
10282 switch (Opcode) {
10283 case VPSHLDVDZ128m:
10284 case VPSHLDVDZ128mb:
10285 case VPSHLDVDZ128mbk:
10286 case VPSHLDVDZ128mbkz:
10287 case VPSHLDVDZ128mk:
10288 case VPSHLDVDZ128mkz:
10289 case VPSHLDVDZ128r:
10290 case VPSHLDVDZ128rk:
10291 case VPSHLDVDZ128rkz:
10292 case VPSHLDVDZ256m:
10293 case VPSHLDVDZ256mb:
10294 case VPSHLDVDZ256mbk:
10295 case VPSHLDVDZ256mbkz:
10296 case VPSHLDVDZ256mk:
10297 case VPSHLDVDZ256mkz:
10298 case VPSHLDVDZ256r:
10299 case VPSHLDVDZ256rk:
10300 case VPSHLDVDZ256rkz:
10301 case VPSHLDVDZm:
10302 case VPSHLDVDZmb:
10303 case VPSHLDVDZmbk:
10304 case VPSHLDVDZmbkz:
10305 case VPSHLDVDZmk:
10306 case VPSHLDVDZmkz:
10307 case VPSHLDVDZr:
10308 case VPSHLDVDZrk:
10309 case VPSHLDVDZrkz:
10310 return true;
10311 }
10312 return false;
10313}
10314
10315bool isPFCMPGT(unsigned Opcode) {
10316 switch (Opcode) {
10317 case PFCMPGTrm:
10318 case PFCMPGTrr:
10319 return true;
10320 }
10321 return false;
10322}
10323
10324bool isVRNDSCALEPH(unsigned Opcode) {
10325 switch (Opcode) {
10326 case VRNDSCALEPHZ128rmbi:
10327 case VRNDSCALEPHZ128rmbik:
10328 case VRNDSCALEPHZ128rmbikz:
10329 case VRNDSCALEPHZ128rmi:
10330 case VRNDSCALEPHZ128rmik:
10331 case VRNDSCALEPHZ128rmikz:
10332 case VRNDSCALEPHZ128rri:
10333 case VRNDSCALEPHZ128rrik:
10334 case VRNDSCALEPHZ128rrikz:
10335 case VRNDSCALEPHZ256rmbi:
10336 case VRNDSCALEPHZ256rmbik:
10337 case VRNDSCALEPHZ256rmbikz:
10338 case VRNDSCALEPHZ256rmi:
10339 case VRNDSCALEPHZ256rmik:
10340 case VRNDSCALEPHZ256rmikz:
10341 case VRNDSCALEPHZ256rri:
10342 case VRNDSCALEPHZ256rrik:
10343 case VRNDSCALEPHZ256rrikz:
10344 case VRNDSCALEPHZrmbi:
10345 case VRNDSCALEPHZrmbik:
10346 case VRNDSCALEPHZrmbikz:
10347 case VRNDSCALEPHZrmi:
10348 case VRNDSCALEPHZrmik:
10349 case VRNDSCALEPHZrmikz:
10350 case VRNDSCALEPHZrri:
10351 case VRNDSCALEPHZrrib:
10352 case VRNDSCALEPHZrribk:
10353 case VRNDSCALEPHZrribkz:
10354 case VRNDSCALEPHZrrik:
10355 case VRNDSCALEPHZrrikz:
10356 return true;
10357 }
10358 return false;
10359}
10360
10361bool isJCXZ(unsigned Opcode) {
10362 return Opcode == JCXZ;
10363}
10364
10365bool isVPMOVZXBW(unsigned Opcode) {
10366 switch (Opcode) {
10367 case VPMOVZXBWYrm:
10368 case VPMOVZXBWYrr:
10369 case VPMOVZXBWZ128rm:
10370 case VPMOVZXBWZ128rmk:
10371 case VPMOVZXBWZ128rmkz:
10372 case VPMOVZXBWZ128rr:
10373 case VPMOVZXBWZ128rrk:
10374 case VPMOVZXBWZ128rrkz:
10375 case VPMOVZXBWZ256rm:
10376 case VPMOVZXBWZ256rmk:
10377 case VPMOVZXBWZ256rmkz:
10378 case VPMOVZXBWZ256rr:
10379 case VPMOVZXBWZ256rrk:
10380 case VPMOVZXBWZ256rrkz:
10381 case VPMOVZXBWZrm:
10382 case VPMOVZXBWZrmk:
10383 case VPMOVZXBWZrmkz:
10384 case VPMOVZXBWZrr:
10385 case VPMOVZXBWZrrk:
10386 case VPMOVZXBWZrrkz:
10387 case VPMOVZXBWrm:
10388 case VPMOVZXBWrr:
10389 return true;
10390 }
10391 return false;
10392}
10393
10394bool isVFMADDSUB231PD(unsigned Opcode) {
10395 switch (Opcode) {
10396 case VFMADDSUB231PDYm:
10397 case VFMADDSUB231PDYr:
10398 case VFMADDSUB231PDZ128m:
10399 case VFMADDSUB231PDZ128mb:
10400 case VFMADDSUB231PDZ128mbk:
10401 case VFMADDSUB231PDZ128mbkz:
10402 case VFMADDSUB231PDZ128mk:
10403 case VFMADDSUB231PDZ128mkz:
10404 case VFMADDSUB231PDZ128r:
10405 case VFMADDSUB231PDZ128rk:
10406 case VFMADDSUB231PDZ128rkz:
10407 case VFMADDSUB231PDZ256m:
10408 case VFMADDSUB231PDZ256mb:
10409 case VFMADDSUB231PDZ256mbk:
10410 case VFMADDSUB231PDZ256mbkz:
10411 case VFMADDSUB231PDZ256mk:
10412 case VFMADDSUB231PDZ256mkz:
10413 case VFMADDSUB231PDZ256r:
10414 case VFMADDSUB231PDZ256rk:
10415 case VFMADDSUB231PDZ256rkz:
10416 case VFMADDSUB231PDZm:
10417 case VFMADDSUB231PDZmb:
10418 case VFMADDSUB231PDZmbk:
10419 case VFMADDSUB231PDZmbkz:
10420 case VFMADDSUB231PDZmk:
10421 case VFMADDSUB231PDZmkz:
10422 case VFMADDSUB231PDZr:
10423 case VFMADDSUB231PDZrb:
10424 case VFMADDSUB231PDZrbk:
10425 case VFMADDSUB231PDZrbkz:
10426 case VFMADDSUB231PDZrk:
10427 case VFMADDSUB231PDZrkz:
10428 case VFMADDSUB231PDm:
10429 case VFMADDSUB231PDr:
10430 return true;
10431 }
10432 return false;
10433}
10434
10435bool isVBLENDMPD(unsigned Opcode) {
10436 switch (Opcode) {
10437 case VBLENDMPDZ128rm:
10438 case VBLENDMPDZ128rmb:
10439 case VBLENDMPDZ128rmbk:
10440 case VBLENDMPDZ128rmbkz:
10441 case VBLENDMPDZ128rmk:
10442 case VBLENDMPDZ128rmkz:
10443 case VBLENDMPDZ128rr:
10444 case VBLENDMPDZ128rrk:
10445 case VBLENDMPDZ128rrkz:
10446 case VBLENDMPDZ256rm:
10447 case VBLENDMPDZ256rmb:
10448 case VBLENDMPDZ256rmbk:
10449 case VBLENDMPDZ256rmbkz:
10450 case VBLENDMPDZ256rmk:
10451 case VBLENDMPDZ256rmkz:
10452 case VBLENDMPDZ256rr:
10453 case VBLENDMPDZ256rrk:
10454 case VBLENDMPDZ256rrkz:
10455 case VBLENDMPDZrm:
10456 case VBLENDMPDZrmb:
10457 case VBLENDMPDZrmbk:
10458 case VBLENDMPDZrmbkz:
10459 case VBLENDMPDZrmk:
10460 case VBLENDMPDZrmkz:
10461 case VBLENDMPDZrr:
10462 case VBLENDMPDZrrk:
10463 case VBLENDMPDZrrkz:
10464 return true;
10465 }
10466 return false;
10467}
10468
10469bool isHSUBPS(unsigned Opcode) {
10470 switch (Opcode) {
10471 case HSUBPSrm:
10472 case HSUBPSrr:
10473 return true;
10474 }
10475 return false;
10476}
10477
10478bool isPREFETCHIT0(unsigned Opcode) {
10479 return Opcode == PREFETCHIT0;
10480}
10481
10482bool isKTESTD(unsigned Opcode) {
10483 return Opcode == KTESTDkk;
10484}
10485
10486bool isVCVTNEOPH2PS(unsigned Opcode) {
10487 switch (Opcode) {
10488 case VCVTNEOPH2PSYrm:
10489 case VCVTNEOPH2PSrm:
10490 return true;
10491 }
10492 return false;
10493}
10494
10495bool isVBLENDVPD(unsigned Opcode) {
10496 switch (Opcode) {
10497 case VBLENDVPDYrmr:
10498 case VBLENDVPDYrrr:
10499 case VBLENDVPDrmr:
10500 case VBLENDVPDrrr:
10501 return true;
10502 }
10503 return false;
10504}
10505
10506bool isVCVTSS2USI(unsigned Opcode) {
10507 switch (Opcode) {
10508 case VCVTSS2USI64Zrm_Int:
10509 case VCVTSS2USI64Zrr_Int:
10510 case VCVTSS2USI64Zrrb_Int:
10511 case VCVTSS2USIZrm_Int:
10512 case VCVTSS2USIZrr_Int:
10513 case VCVTSS2USIZrrb_Int:
10514 return true;
10515 }
10516 return false;
10517}
10518
10519bool isVCVTTPS2DQS(unsigned Opcode) {
10520 switch (Opcode) {
10521 case VCVTTPS2DQSZ128rm:
10522 case VCVTTPS2DQSZ128rmb:
10523 case VCVTTPS2DQSZ128rmbk:
10524 case VCVTTPS2DQSZ128rmbkz:
10525 case VCVTTPS2DQSZ128rmk:
10526 case VCVTTPS2DQSZ128rmkz:
10527 case VCVTTPS2DQSZ128rr:
10528 case VCVTTPS2DQSZ128rrk:
10529 case VCVTTPS2DQSZ128rrkz:
10530 case VCVTTPS2DQSZ256rm:
10531 case VCVTTPS2DQSZ256rmb:
10532 case VCVTTPS2DQSZ256rmbk:
10533 case VCVTTPS2DQSZ256rmbkz:
10534 case VCVTTPS2DQSZ256rmk:
10535 case VCVTTPS2DQSZ256rmkz:
10536 case VCVTTPS2DQSZ256rr:
10537 case VCVTTPS2DQSZ256rrk:
10538 case VCVTTPS2DQSZ256rrkz:
10539 case VCVTTPS2DQSZrm:
10540 case VCVTTPS2DQSZrmb:
10541 case VCVTTPS2DQSZrmbk:
10542 case VCVTTPS2DQSZrmbkz:
10543 case VCVTTPS2DQSZrmk:
10544 case VCVTTPS2DQSZrmkz:
10545 case VCVTTPS2DQSZrr:
10546 case VCVTTPS2DQSZrrb:
10547 case VCVTTPS2DQSZrrbk:
10548 case VCVTTPS2DQSZrrbkz:
10549 case VCVTTPS2DQSZrrk:
10550 case VCVTTPS2DQSZrrkz:
10551 return true;
10552 }
10553 return false;
10554}
10555
10556bool isVPANDD(unsigned Opcode) {
10557 switch (Opcode) {
10558 case VPANDDZ128rm:
10559 case VPANDDZ128rmb:
10560 case VPANDDZ128rmbk:
10561 case VPANDDZ128rmbkz:
10562 case VPANDDZ128rmk:
10563 case VPANDDZ128rmkz:
10564 case VPANDDZ128rr:
10565 case VPANDDZ128rrk:
10566 case VPANDDZ128rrkz:
10567 case VPANDDZ256rm:
10568 case VPANDDZ256rmb:
10569 case VPANDDZ256rmbk:
10570 case VPANDDZ256rmbkz:
10571 case VPANDDZ256rmk:
10572 case VPANDDZ256rmkz:
10573 case VPANDDZ256rr:
10574 case VPANDDZ256rrk:
10575 case VPANDDZ256rrkz:
10576 case VPANDDZrm:
10577 case VPANDDZrmb:
10578 case VPANDDZrmbk:
10579 case VPANDDZrmbkz:
10580 case VPANDDZrmk:
10581 case VPANDDZrmkz:
10582 case VPANDDZrr:
10583 case VPANDDZrrk:
10584 case VPANDDZrrkz:
10585 return true;
10586 }
10587 return false;
10588}
10589
10590bool isPMINSW(unsigned Opcode) {
10591 switch (Opcode) {
10592 case MMX_PMINSWrm:
10593 case MMX_PMINSWrr:
10594 case PMINSWrm:
10595 case PMINSWrr:
10596 return true;
10597 }
10598 return false;
10599}
10600
10601bool isSTAC(unsigned Opcode) {
10602 return Opcode == STAC;
10603}
10604
10605bool isVFMSUB213PS(unsigned Opcode) {
10606 switch (Opcode) {
10607 case VFMSUB213PSYm:
10608 case VFMSUB213PSYr:
10609 case VFMSUB213PSZ128m:
10610 case VFMSUB213PSZ128mb:
10611 case VFMSUB213PSZ128mbk:
10612 case VFMSUB213PSZ128mbkz:
10613 case VFMSUB213PSZ128mk:
10614 case VFMSUB213PSZ128mkz:
10615 case VFMSUB213PSZ128r:
10616 case VFMSUB213PSZ128rk:
10617 case VFMSUB213PSZ128rkz:
10618 case VFMSUB213PSZ256m:
10619 case VFMSUB213PSZ256mb:
10620 case VFMSUB213PSZ256mbk:
10621 case VFMSUB213PSZ256mbkz:
10622 case VFMSUB213PSZ256mk:
10623 case VFMSUB213PSZ256mkz:
10624 case VFMSUB213PSZ256r:
10625 case VFMSUB213PSZ256rk:
10626 case VFMSUB213PSZ256rkz:
10627 case VFMSUB213PSZm:
10628 case VFMSUB213PSZmb:
10629 case VFMSUB213PSZmbk:
10630 case VFMSUB213PSZmbkz:
10631 case VFMSUB213PSZmk:
10632 case VFMSUB213PSZmkz:
10633 case VFMSUB213PSZr:
10634 case VFMSUB213PSZrb:
10635 case VFMSUB213PSZrbk:
10636 case VFMSUB213PSZrbkz:
10637 case VFMSUB213PSZrk:
10638 case VFMSUB213PSZrkz:
10639 case VFMSUB213PSm:
10640 case VFMSUB213PSr:
10641 return true;
10642 }
10643 return false;
10644}
10645
10646bool isPOPAL(unsigned Opcode) {
10647 return Opcode == POPA32;
10648}
10649
10650bool isVCVTPS2UQQ(unsigned Opcode) {
10651 switch (Opcode) {
10652 case VCVTPS2UQQZ128rm:
10653 case VCVTPS2UQQZ128rmb:
10654 case VCVTPS2UQQZ128rmbk:
10655 case VCVTPS2UQQZ128rmbkz:
10656 case VCVTPS2UQQZ128rmk:
10657 case VCVTPS2UQQZ128rmkz:
10658 case VCVTPS2UQQZ128rr:
10659 case VCVTPS2UQQZ128rrk:
10660 case VCVTPS2UQQZ128rrkz:
10661 case VCVTPS2UQQZ256rm:
10662 case VCVTPS2UQQZ256rmb:
10663 case VCVTPS2UQQZ256rmbk:
10664 case VCVTPS2UQQZ256rmbkz:
10665 case VCVTPS2UQQZ256rmk:
10666 case VCVTPS2UQQZ256rmkz:
10667 case VCVTPS2UQQZ256rr:
10668 case VCVTPS2UQQZ256rrk:
10669 case VCVTPS2UQQZ256rrkz:
10670 case VCVTPS2UQQZrm:
10671 case VCVTPS2UQQZrmb:
10672 case VCVTPS2UQQZrmbk:
10673 case VCVTPS2UQQZrmbkz:
10674 case VCVTPS2UQQZrmk:
10675 case VCVTPS2UQQZrmkz:
10676 case VCVTPS2UQQZrr:
10677 case VCVTPS2UQQZrrb:
10678 case VCVTPS2UQQZrrbk:
10679 case VCVTPS2UQQZrrbkz:
10680 case VCVTPS2UQQZrrk:
10681 case VCVTPS2UQQZrrkz:
10682 return true;
10683 }
10684 return false;
10685}
10686
10687bool isRDRAND(unsigned Opcode) {
10688 switch (Opcode) {
10689 case RDRAND16r:
10690 case RDRAND32r:
10691 case RDRAND64r:
10692 return true;
10693 }
10694 return false;
10695}
10696
10697bool isJCC(unsigned Opcode) {
10698 switch (Opcode) {
10699 case JCC_1:
10700 case JCC_2:
10701 case JCC_4:
10702 return true;
10703 }
10704 return false;
10705}
10706
10707bool isVPMINSQ(unsigned Opcode) {
10708 switch (Opcode) {
10709 case VPMINSQZ128rm:
10710 case VPMINSQZ128rmb:
10711 case VPMINSQZ128rmbk:
10712 case VPMINSQZ128rmbkz:
10713 case VPMINSQZ128rmk:
10714 case VPMINSQZ128rmkz:
10715 case VPMINSQZ128rr:
10716 case VPMINSQZ128rrk:
10717 case VPMINSQZ128rrkz:
10718 case VPMINSQZ256rm:
10719 case VPMINSQZ256rmb:
10720 case VPMINSQZ256rmbk:
10721 case VPMINSQZ256rmbkz:
10722 case VPMINSQZ256rmk:
10723 case VPMINSQZ256rmkz:
10724 case VPMINSQZ256rr:
10725 case VPMINSQZ256rrk:
10726 case VPMINSQZ256rrkz:
10727 case VPMINSQZrm:
10728 case VPMINSQZrmb:
10729 case VPMINSQZrmbk:
10730 case VPMINSQZrmbkz:
10731 case VPMINSQZrmk:
10732 case VPMINSQZrmkz:
10733 case VPMINSQZrr:
10734 case VPMINSQZrrk:
10735 case VPMINSQZrrkz:
10736 return true;
10737 }
10738 return false;
10739}
10740
10741bool isVADDSD(unsigned Opcode) {
10742 switch (Opcode) {
10743 case VADDSDZrm_Int:
10744 case VADDSDZrmk_Int:
10745 case VADDSDZrmkz_Int:
10746 case VADDSDZrr_Int:
10747 case VADDSDZrrb_Int:
10748 case VADDSDZrrbk_Int:
10749 case VADDSDZrrbkz_Int:
10750 case VADDSDZrrk_Int:
10751 case VADDSDZrrkz_Int:
10752 case VADDSDrm_Int:
10753 case VADDSDrr_Int:
10754 return true;
10755 }
10756 return false;
10757}
10758
10759bool isDPPS(unsigned Opcode) {
10760 switch (Opcode) {
10761 case DPPSrmi:
10762 case DPPSrri:
10763 return true;
10764 }
10765 return false;
10766}
10767
10768bool isPINSRQ(unsigned Opcode) {
10769 switch (Opcode) {
10770 case PINSRQrmi:
10771 case PINSRQrri:
10772 return true;
10773 }
10774 return false;
10775}
10776
10777bool isVUCOMISS(unsigned Opcode) {
10778 switch (Opcode) {
10779 case VUCOMISSZrm:
10780 case VUCOMISSZrr:
10781 case VUCOMISSZrrb:
10782 case VUCOMISSrm:
10783 case VUCOMISSrr:
10784 return true;
10785 }
10786 return false;
10787}
10788
10789bool isVPDPWSUD(unsigned Opcode) {
10790 switch (Opcode) {
10791 case VPDPWSUDYrm:
10792 case VPDPWSUDYrr:
10793 case VPDPWSUDZ128rm:
10794 case VPDPWSUDZ128rmb:
10795 case VPDPWSUDZ128rmbk:
10796 case VPDPWSUDZ128rmbkz:
10797 case VPDPWSUDZ128rmk:
10798 case VPDPWSUDZ128rmkz:
10799 case VPDPWSUDZ128rr:
10800 case VPDPWSUDZ128rrk:
10801 case VPDPWSUDZ128rrkz:
10802 case VPDPWSUDZ256rm:
10803 case VPDPWSUDZ256rmb:
10804 case VPDPWSUDZ256rmbk:
10805 case VPDPWSUDZ256rmbkz:
10806 case VPDPWSUDZ256rmk:
10807 case VPDPWSUDZ256rmkz:
10808 case VPDPWSUDZ256rr:
10809 case VPDPWSUDZ256rrk:
10810 case VPDPWSUDZ256rrkz:
10811 case VPDPWSUDZrm:
10812 case VPDPWSUDZrmb:
10813 case VPDPWSUDZrmbk:
10814 case VPDPWSUDZrmbkz:
10815 case VPDPWSUDZrmk:
10816 case VPDPWSUDZrmkz:
10817 case VPDPWSUDZrr:
10818 case VPDPWSUDZrrk:
10819 case VPDPWSUDZrrkz:
10820 case VPDPWSUDrm:
10821 case VPDPWSUDrr:
10822 return true;
10823 }
10824 return false;
10825}
10826
10827bool isKANDNW(unsigned Opcode) {
10828 return Opcode == KANDNWkk;
10829}
10830
10831bool isAOR(unsigned Opcode) {
10832 switch (Opcode) {
10833 case AOR32mr:
10834 case AOR32mr_EVEX:
10835 case AOR64mr:
10836 case AOR64mr_EVEX:
10837 return true;
10838 }
10839 return false;
10840}
10841
10842bool isPMAXUB(unsigned Opcode) {
10843 switch (Opcode) {
10844 case MMX_PMAXUBrm:
10845 case MMX_PMAXUBrr:
10846 case PMAXUBrm:
10847 case PMAXUBrr:
10848 return true;
10849 }
10850 return false;
10851}
10852
10853bool isANDNPD(unsigned Opcode) {
10854 switch (Opcode) {
10855 case ANDNPDrm:
10856 case ANDNPDrr:
10857 return true;
10858 }
10859 return false;
10860}
10861
10862bool isINVPCID(unsigned Opcode) {
10863 switch (Opcode) {
10864 case INVPCID32:
10865 case INVPCID64:
10866 case INVPCID64_EVEX:
10867 return true;
10868 }
10869 return false;
10870}
10871
10872bool isRDGSBASE(unsigned Opcode) {
10873 switch (Opcode) {
10874 case RDGSBASE:
10875 case RDGSBASE64:
10876 return true;
10877 }
10878 return false;
10879}
10880
10881bool isVPMOVSQD(unsigned Opcode) {
10882 switch (Opcode) {
10883 case VPMOVSQDZ128mr:
10884 case VPMOVSQDZ128mrk:
10885 case VPMOVSQDZ128rr:
10886 case VPMOVSQDZ128rrk:
10887 case VPMOVSQDZ128rrkz:
10888 case VPMOVSQDZ256mr:
10889 case VPMOVSQDZ256mrk:
10890 case VPMOVSQDZ256rr:
10891 case VPMOVSQDZ256rrk:
10892 case VPMOVSQDZ256rrkz:
10893 case VPMOVSQDZmr:
10894 case VPMOVSQDZmrk:
10895 case VPMOVSQDZrr:
10896 case VPMOVSQDZrrk:
10897 case VPMOVSQDZrrkz:
10898 return true;
10899 }
10900 return false;
10901}
10902
10903bool isBT(unsigned Opcode) {
10904 switch (Opcode) {
10905 case BT16mi8:
10906 case BT16mr:
10907 case BT16ri8:
10908 case BT16rr:
10909 case BT32mi8:
10910 case BT32mr:
10911 case BT32ri8:
10912 case BT32rr:
10913 case BT64mi8:
10914 case BT64mr:
10915 case BT64ri8:
10916 case BT64rr:
10917 return true;
10918 }
10919 return false;
10920}
10921
10922bool isVPROLVQ(unsigned Opcode) {
10923 switch (Opcode) {
10924 case VPROLVQZ128rm:
10925 case VPROLVQZ128rmb:
10926 case VPROLVQZ128rmbk:
10927 case VPROLVQZ128rmbkz:
10928 case VPROLVQZ128rmk:
10929 case VPROLVQZ128rmkz:
10930 case VPROLVQZ128rr:
10931 case VPROLVQZ128rrk:
10932 case VPROLVQZ128rrkz:
10933 case VPROLVQZ256rm:
10934 case VPROLVQZ256rmb:
10935 case VPROLVQZ256rmbk:
10936 case VPROLVQZ256rmbkz:
10937 case VPROLVQZ256rmk:
10938 case VPROLVQZ256rmkz:
10939 case VPROLVQZ256rr:
10940 case VPROLVQZ256rrk:
10941 case VPROLVQZ256rrkz:
10942 case VPROLVQZrm:
10943 case VPROLVQZrmb:
10944 case VPROLVQZrmbk:
10945 case VPROLVQZrmbkz:
10946 case VPROLVQZrmk:
10947 case VPROLVQZrmkz:
10948 case VPROLVQZrr:
10949 case VPROLVQZrrk:
10950 case VPROLVQZrrkz:
10951 return true;
10952 }
10953 return false;
10954}
10955
10956bool isVFMADDSUB132PD(unsigned Opcode) {
10957 switch (Opcode) {
10958 case VFMADDSUB132PDYm:
10959 case VFMADDSUB132PDYr:
10960 case VFMADDSUB132PDZ128m:
10961 case VFMADDSUB132PDZ128mb:
10962 case VFMADDSUB132PDZ128mbk:
10963 case VFMADDSUB132PDZ128mbkz:
10964 case VFMADDSUB132PDZ128mk:
10965 case VFMADDSUB132PDZ128mkz:
10966 case VFMADDSUB132PDZ128r:
10967 case VFMADDSUB132PDZ128rk:
10968 case VFMADDSUB132PDZ128rkz:
10969 case VFMADDSUB132PDZ256m:
10970 case VFMADDSUB132PDZ256mb:
10971 case VFMADDSUB132PDZ256mbk:
10972 case VFMADDSUB132PDZ256mbkz:
10973 case VFMADDSUB132PDZ256mk:
10974 case VFMADDSUB132PDZ256mkz:
10975 case VFMADDSUB132PDZ256r:
10976 case VFMADDSUB132PDZ256rk:
10977 case VFMADDSUB132PDZ256rkz:
10978 case VFMADDSUB132PDZm:
10979 case VFMADDSUB132PDZmb:
10980 case VFMADDSUB132PDZmbk:
10981 case VFMADDSUB132PDZmbkz:
10982 case VFMADDSUB132PDZmk:
10983 case VFMADDSUB132PDZmkz:
10984 case VFMADDSUB132PDZr:
10985 case VFMADDSUB132PDZrb:
10986 case VFMADDSUB132PDZrbk:
10987 case VFMADDSUB132PDZrbkz:
10988 case VFMADDSUB132PDZrk:
10989 case VFMADDSUB132PDZrkz:
10990 case VFMADDSUB132PDm:
10991 case VFMADDSUB132PDr:
10992 return true;
10993 }
10994 return false;
10995}
10996
10997bool isRORX(unsigned Opcode) {
10998 switch (Opcode) {
10999 case RORX32mi:
11000 case RORX32mi_EVEX:
11001 case RORX32ri:
11002 case RORX32ri_EVEX:
11003 case RORX64mi:
11004 case RORX64mi_EVEX:
11005 case RORX64ri:
11006 case RORX64ri_EVEX:
11007 return true;
11008 }
11009 return false;
11010}
11011
11012bool isPADDUSW(unsigned Opcode) {
11013 switch (Opcode) {
11014 case MMX_PADDUSWrm:
11015 case MMX_PADDUSWrr:
11016 case PADDUSWrm:
11017 case PADDUSWrr:
11018 return true;
11019 }
11020 return false;
11021}
11022
11023bool isPFNACC(unsigned Opcode) {
11024 switch (Opcode) {
11025 case PFNACCrm:
11026 case PFNACCrr:
11027 return true;
11028 }
11029 return false;
11030}
11031
11032bool isAND(unsigned Opcode) {
11033 switch (Opcode) {
11034 case AND16i16:
11035 case AND16mi:
11036 case AND16mi8:
11037 case AND16mi8_EVEX:
11038 case AND16mi8_ND:
11039 case AND16mi8_NF:
11040 case AND16mi8_NF_ND:
11041 case AND16mi_EVEX:
11042 case AND16mi_ND:
11043 case AND16mi_NF:
11044 case AND16mi_NF_ND:
11045 case AND16mr:
11046 case AND16mr_EVEX:
11047 case AND16mr_ND:
11048 case AND16mr_NF:
11049 case AND16mr_NF_ND:
11050 case AND16ri:
11051 case AND16ri8:
11052 case AND16ri8_EVEX:
11053 case AND16ri8_ND:
11054 case AND16ri8_NF:
11055 case AND16ri8_NF_ND:
11056 case AND16ri_EVEX:
11057 case AND16ri_ND:
11058 case AND16ri_NF:
11059 case AND16ri_NF_ND:
11060 case AND16rm:
11061 case AND16rm_EVEX:
11062 case AND16rm_ND:
11063 case AND16rm_NF:
11064 case AND16rm_NF_ND:
11065 case AND16rr:
11066 case AND16rr_EVEX:
11067 case AND16rr_EVEX_REV:
11068 case AND16rr_ND:
11069 case AND16rr_ND_REV:
11070 case AND16rr_NF:
11071 case AND16rr_NF_ND:
11072 case AND16rr_NF_ND_REV:
11073 case AND16rr_NF_REV:
11074 case AND16rr_REV:
11075 case AND32i32:
11076 case AND32mi:
11077 case AND32mi8:
11078 case AND32mi8_EVEX:
11079 case AND32mi8_ND:
11080 case AND32mi8_NF:
11081 case AND32mi8_NF_ND:
11082 case AND32mi_EVEX:
11083 case AND32mi_ND:
11084 case AND32mi_NF:
11085 case AND32mi_NF_ND:
11086 case AND32mr:
11087 case AND32mr_EVEX:
11088 case AND32mr_ND:
11089 case AND32mr_NF:
11090 case AND32mr_NF_ND:
11091 case AND32ri:
11092 case AND32ri8:
11093 case AND32ri8_EVEX:
11094 case AND32ri8_ND:
11095 case AND32ri8_NF:
11096 case AND32ri8_NF_ND:
11097 case AND32ri_EVEX:
11098 case AND32ri_ND:
11099 case AND32ri_NF:
11100 case AND32ri_NF_ND:
11101 case AND32rm:
11102 case AND32rm_EVEX:
11103 case AND32rm_ND:
11104 case AND32rm_NF:
11105 case AND32rm_NF_ND:
11106 case AND32rr:
11107 case AND32rr_EVEX:
11108 case AND32rr_EVEX_REV:
11109 case AND32rr_ND:
11110 case AND32rr_ND_REV:
11111 case AND32rr_NF:
11112 case AND32rr_NF_ND:
11113 case AND32rr_NF_ND_REV:
11114 case AND32rr_NF_REV:
11115 case AND32rr_REV:
11116 case AND64i32:
11117 case AND64mi32:
11118 case AND64mi32_EVEX:
11119 case AND64mi32_ND:
11120 case AND64mi32_NF:
11121 case AND64mi32_NF_ND:
11122 case AND64mi8:
11123 case AND64mi8_EVEX:
11124 case AND64mi8_ND:
11125 case AND64mi8_NF:
11126 case AND64mi8_NF_ND:
11127 case AND64mr:
11128 case AND64mr_EVEX:
11129 case AND64mr_ND:
11130 case AND64mr_NF:
11131 case AND64mr_NF_ND:
11132 case AND64ri32:
11133 case AND64ri32_EVEX:
11134 case AND64ri32_ND:
11135 case AND64ri32_NF:
11136 case AND64ri32_NF_ND:
11137 case AND64ri8:
11138 case AND64ri8_EVEX:
11139 case AND64ri8_ND:
11140 case AND64ri8_NF:
11141 case AND64ri8_NF_ND:
11142 case AND64rm:
11143 case AND64rm_EVEX:
11144 case AND64rm_ND:
11145 case AND64rm_NF:
11146 case AND64rm_NF_ND:
11147 case AND64rr:
11148 case AND64rr_EVEX:
11149 case AND64rr_EVEX_REV:
11150 case AND64rr_ND:
11151 case AND64rr_ND_REV:
11152 case AND64rr_NF:
11153 case AND64rr_NF_ND:
11154 case AND64rr_NF_ND_REV:
11155 case AND64rr_NF_REV:
11156 case AND64rr_REV:
11157 case AND8i8:
11158 case AND8mi:
11159 case AND8mi8:
11160 case AND8mi_EVEX:
11161 case AND8mi_ND:
11162 case AND8mi_NF:
11163 case AND8mi_NF_ND:
11164 case AND8mr:
11165 case AND8mr_EVEX:
11166 case AND8mr_ND:
11167 case AND8mr_NF:
11168 case AND8mr_NF_ND:
11169 case AND8ri:
11170 case AND8ri8:
11171 case AND8ri_EVEX:
11172 case AND8ri_ND:
11173 case AND8ri_NF:
11174 case AND8ri_NF_ND:
11175 case AND8rm:
11176 case AND8rm_EVEX:
11177 case AND8rm_ND:
11178 case AND8rm_NF:
11179 case AND8rm_NF_ND:
11180 case AND8rr:
11181 case AND8rr_EVEX:
11182 case AND8rr_EVEX_REV:
11183 case AND8rr_ND:
11184 case AND8rr_ND_REV:
11185 case AND8rr_NF:
11186 case AND8rr_NF_ND:
11187 case AND8rr_NF_ND_REV:
11188 case AND8rr_NF_REV:
11189 case AND8rr_REV:
11190 return true;
11191 }
11192 return false;
11193}
11194
11195bool isPSLLQ(unsigned Opcode) {
11196 switch (Opcode) {
11197 case MMX_PSLLQri:
11198 case MMX_PSLLQrm:
11199 case MMX_PSLLQrr:
11200 case PSLLQri:
11201 case PSLLQrm:
11202 case PSLLQrr:
11203 return true;
11204 }
11205 return false;
11206}
11207
11208bool isVFMSUB132PH(unsigned Opcode) {
11209 switch (Opcode) {
11210 case VFMSUB132PHZ128m:
11211 case VFMSUB132PHZ128mb:
11212 case VFMSUB132PHZ128mbk:
11213 case VFMSUB132PHZ128mbkz:
11214 case VFMSUB132PHZ128mk:
11215 case VFMSUB132PHZ128mkz:
11216 case VFMSUB132PHZ128r:
11217 case VFMSUB132PHZ128rk:
11218 case VFMSUB132PHZ128rkz:
11219 case VFMSUB132PHZ256m:
11220 case VFMSUB132PHZ256mb:
11221 case VFMSUB132PHZ256mbk:
11222 case VFMSUB132PHZ256mbkz:
11223 case VFMSUB132PHZ256mk:
11224 case VFMSUB132PHZ256mkz:
11225 case VFMSUB132PHZ256r:
11226 case VFMSUB132PHZ256rk:
11227 case VFMSUB132PHZ256rkz:
11228 case VFMSUB132PHZm:
11229 case VFMSUB132PHZmb:
11230 case VFMSUB132PHZmbk:
11231 case VFMSUB132PHZmbkz:
11232 case VFMSUB132PHZmk:
11233 case VFMSUB132PHZmkz:
11234 case VFMSUB132PHZr:
11235 case VFMSUB132PHZrb:
11236 case VFMSUB132PHZrbk:
11237 case VFMSUB132PHZrbkz:
11238 case VFMSUB132PHZrk:
11239 case VFMSUB132PHZrkz:
11240 return true;
11241 }
11242 return false;
11243}
11244
11245bool isXSAVE(unsigned Opcode) {
11246 return Opcode == XSAVE;
11247}
11248
11249bool isKNOTQ(unsigned Opcode) {
11250 return Opcode == KNOTQkk;
11251}
11252
11253bool isXTEST(unsigned Opcode) {
11254 return Opcode == XTEST;
11255}
11256
11257bool isVINSERTPS(unsigned Opcode) {
11258 switch (Opcode) {
11259 case VINSERTPSZrmi:
11260 case VINSERTPSZrri:
11261 case VINSERTPSrmi:
11262 case VINSERTPSrri:
11263 return true;
11264 }
11265 return false;
11266}
11267
11268bool isXSAVEOPT(unsigned Opcode) {
11269 return Opcode == XSAVEOPT;
11270}
11271
11272bool isLDS(unsigned Opcode) {
11273 switch (Opcode) {
11274 case LDS16rm:
11275 case LDS32rm:
11276 return true;
11277 }
11278 return false;
11279}
11280
11281bool isVFMADDSUB213PD(unsigned Opcode) {
11282 switch (Opcode) {
11283 case VFMADDSUB213PDYm:
11284 case VFMADDSUB213PDYr:
11285 case VFMADDSUB213PDZ128m:
11286 case VFMADDSUB213PDZ128mb:
11287 case VFMADDSUB213PDZ128mbk:
11288 case VFMADDSUB213PDZ128mbkz:
11289 case VFMADDSUB213PDZ128mk:
11290 case VFMADDSUB213PDZ128mkz:
11291 case VFMADDSUB213PDZ128r:
11292 case VFMADDSUB213PDZ128rk:
11293 case VFMADDSUB213PDZ128rkz:
11294 case VFMADDSUB213PDZ256m:
11295 case VFMADDSUB213PDZ256mb:
11296 case VFMADDSUB213PDZ256mbk:
11297 case VFMADDSUB213PDZ256mbkz:
11298 case VFMADDSUB213PDZ256mk:
11299 case VFMADDSUB213PDZ256mkz:
11300 case VFMADDSUB213PDZ256r:
11301 case VFMADDSUB213PDZ256rk:
11302 case VFMADDSUB213PDZ256rkz:
11303 case VFMADDSUB213PDZm:
11304 case VFMADDSUB213PDZmb:
11305 case VFMADDSUB213PDZmbk:
11306 case VFMADDSUB213PDZmbkz:
11307 case VFMADDSUB213PDZmk:
11308 case VFMADDSUB213PDZmkz:
11309 case VFMADDSUB213PDZr:
11310 case VFMADDSUB213PDZrb:
11311 case VFMADDSUB213PDZrbk:
11312 case VFMADDSUB213PDZrbkz:
11313 case VFMADDSUB213PDZrk:
11314 case VFMADDSUB213PDZrkz:
11315 case VFMADDSUB213PDm:
11316 case VFMADDSUB213PDr:
11317 return true;
11318 }
11319 return false;
11320}
11321
11322bool isVINSERTF32X4(unsigned Opcode) {
11323 switch (Opcode) {
11324 case VINSERTF32X4Z256rmi:
11325 case VINSERTF32X4Z256rmik:
11326 case VINSERTF32X4Z256rmikz:
11327 case VINSERTF32X4Z256rri:
11328 case VINSERTF32X4Z256rrik:
11329 case VINSERTF32X4Z256rrikz:
11330 case VINSERTF32X4Zrmi:
11331 case VINSERTF32X4Zrmik:
11332 case VINSERTF32X4Zrmikz:
11333 case VINSERTF32X4Zrri:
11334 case VINSERTF32X4Zrrik:
11335 case VINSERTF32X4Zrrikz:
11336 return true;
11337 }
11338 return false;
11339}
11340
11341bool isVRSQRTPS(unsigned Opcode) {
11342 switch (Opcode) {
11343 case VRSQRTPSYm:
11344 case VRSQRTPSYr:
11345 case VRSQRTPSm:
11346 case VRSQRTPSr:
11347 return true;
11348 }
11349 return false;
11350}
11351
11352bool isVSUBPH(unsigned Opcode) {
11353 switch (Opcode) {
11354 case VSUBPHZ128rm:
11355 case VSUBPHZ128rmb:
11356 case VSUBPHZ128rmbk:
11357 case VSUBPHZ128rmbkz:
11358 case VSUBPHZ128rmk:
11359 case VSUBPHZ128rmkz:
11360 case VSUBPHZ128rr:
11361 case VSUBPHZ128rrk:
11362 case VSUBPHZ128rrkz:
11363 case VSUBPHZ256rm:
11364 case VSUBPHZ256rmb:
11365 case VSUBPHZ256rmbk:
11366 case VSUBPHZ256rmbkz:
11367 case VSUBPHZ256rmk:
11368 case VSUBPHZ256rmkz:
11369 case VSUBPHZ256rr:
11370 case VSUBPHZ256rrk:
11371 case VSUBPHZ256rrkz:
11372 case VSUBPHZrm:
11373 case VSUBPHZrmb:
11374 case VSUBPHZrmbk:
11375 case VSUBPHZrmbkz:
11376 case VSUBPHZrmk:
11377 case VSUBPHZrmkz:
11378 case VSUBPHZrr:
11379 case VSUBPHZrrb:
11380 case VSUBPHZrrbk:
11381 case VSUBPHZrrbkz:
11382 case VSUBPHZrrk:
11383 case VSUBPHZrrkz:
11384 return true;
11385 }
11386 return false;
11387}
11388
11389bool isPMOVSXBW(unsigned Opcode) {
11390 switch (Opcode) {
11391 case PMOVSXBWrm:
11392 case PMOVSXBWrr:
11393 return true;
11394 }
11395 return false;
11396}
11397
11398bool isVPSRLDQ(unsigned Opcode) {
11399 switch (Opcode) {
11400 case VPSRLDQYri:
11401 case VPSRLDQZ128mi:
11402 case VPSRLDQZ128ri:
11403 case VPSRLDQZ256mi:
11404 case VPSRLDQZ256ri:
11405 case VPSRLDQZmi:
11406 case VPSRLDQZri:
11407 case VPSRLDQri:
11408 return true;
11409 }
11410 return false;
11411}
11412
11413bool isADC(unsigned Opcode) {
11414 switch (Opcode) {
11415 case ADC16i16:
11416 case ADC16mi:
11417 case ADC16mi8:
11418 case ADC16mi8_EVEX:
11419 case ADC16mi8_ND:
11420 case ADC16mi_EVEX:
11421 case ADC16mi_ND:
11422 case ADC16mr:
11423 case ADC16mr_EVEX:
11424 case ADC16mr_ND:
11425 case ADC16ri:
11426 case ADC16ri8:
11427 case ADC16ri8_EVEX:
11428 case ADC16ri8_ND:
11429 case ADC16ri_EVEX:
11430 case ADC16ri_ND:
11431 case ADC16rm:
11432 case ADC16rm_EVEX:
11433 case ADC16rm_ND:
11434 case ADC16rr:
11435 case ADC16rr_EVEX:
11436 case ADC16rr_EVEX_REV:
11437 case ADC16rr_ND:
11438 case ADC16rr_ND_REV:
11439 case ADC16rr_REV:
11440 case ADC32i32:
11441 case ADC32mi:
11442 case ADC32mi8:
11443 case ADC32mi8_EVEX:
11444 case ADC32mi8_ND:
11445 case ADC32mi_EVEX:
11446 case ADC32mi_ND:
11447 case ADC32mr:
11448 case ADC32mr_EVEX:
11449 case ADC32mr_ND:
11450 case ADC32ri:
11451 case ADC32ri8:
11452 case ADC32ri8_EVEX:
11453 case ADC32ri8_ND:
11454 case ADC32ri_EVEX:
11455 case ADC32ri_ND:
11456 case ADC32rm:
11457 case ADC32rm_EVEX:
11458 case ADC32rm_ND:
11459 case ADC32rr:
11460 case ADC32rr_EVEX:
11461 case ADC32rr_EVEX_REV:
11462 case ADC32rr_ND:
11463 case ADC32rr_ND_REV:
11464 case ADC32rr_REV:
11465 case ADC64i32:
11466 case ADC64mi32:
11467 case ADC64mi32_EVEX:
11468 case ADC64mi32_ND:
11469 case ADC64mi8:
11470 case ADC64mi8_EVEX:
11471 case ADC64mi8_ND:
11472 case ADC64mr:
11473 case ADC64mr_EVEX:
11474 case ADC64mr_ND:
11475 case ADC64ri32:
11476 case ADC64ri32_EVEX:
11477 case ADC64ri32_ND:
11478 case ADC64ri8:
11479 case ADC64ri8_EVEX:
11480 case ADC64ri8_ND:
11481 case ADC64rm:
11482 case ADC64rm_EVEX:
11483 case ADC64rm_ND:
11484 case ADC64rr:
11485 case ADC64rr_EVEX:
11486 case ADC64rr_EVEX_REV:
11487 case ADC64rr_ND:
11488 case ADC64rr_ND_REV:
11489 case ADC64rr_REV:
11490 case ADC8i8:
11491 case ADC8mi:
11492 case ADC8mi8:
11493 case ADC8mi_EVEX:
11494 case ADC8mi_ND:
11495 case ADC8mr:
11496 case ADC8mr_EVEX:
11497 case ADC8mr_ND:
11498 case ADC8ri:
11499 case ADC8ri8:
11500 case ADC8ri_EVEX:
11501 case ADC8ri_ND:
11502 case ADC8rm:
11503 case ADC8rm_EVEX:
11504 case ADC8rm_ND:
11505 case ADC8rr:
11506 case ADC8rr_EVEX:
11507 case ADC8rr_EVEX_REV:
11508 case ADC8rr_ND:
11509 case ADC8rr_ND_REV:
11510 case ADC8rr_REV:
11511 return true;
11512 }
11513 return false;
11514}
11515
11516bool isPHADDD(unsigned Opcode) {
11517 switch (Opcode) {
11518 case MMX_PHADDDrm:
11519 case MMX_PHADDDrr:
11520 case PHADDDrm:
11521 case PHADDDrr:
11522 return true;
11523 }
11524 return false;
11525}
11526
11527bool isVDPPHPS(unsigned Opcode) {
11528 switch (Opcode) {
11529 case VDPPHPSZ128m:
11530 case VDPPHPSZ128mb:
11531 case VDPPHPSZ128mbk:
11532 case VDPPHPSZ128mbkz:
11533 case VDPPHPSZ128mk:
11534 case VDPPHPSZ128mkz:
11535 case VDPPHPSZ128r:
11536 case VDPPHPSZ128rk:
11537 case VDPPHPSZ128rkz:
11538 case VDPPHPSZ256m:
11539 case VDPPHPSZ256mb:
11540 case VDPPHPSZ256mbk:
11541 case VDPPHPSZ256mbkz:
11542 case VDPPHPSZ256mk:
11543 case VDPPHPSZ256mkz:
11544 case VDPPHPSZ256r:
11545 case VDPPHPSZ256rk:
11546 case VDPPHPSZ256rkz:
11547 case VDPPHPSZm:
11548 case VDPPHPSZmb:
11549 case VDPPHPSZmbk:
11550 case VDPPHPSZmbkz:
11551 case VDPPHPSZmk:
11552 case VDPPHPSZmkz:
11553 case VDPPHPSZr:
11554 case VDPPHPSZrk:
11555 case VDPPHPSZrkz:
11556 return true;
11557 }
11558 return false;
11559}
11560
11561bool isVMINPH(unsigned Opcode) {
11562 switch (Opcode) {
11563 case VMINPHZ128rm:
11564 case VMINPHZ128rmb:
11565 case VMINPHZ128rmbk:
11566 case VMINPHZ128rmbkz:
11567 case VMINPHZ128rmk:
11568 case VMINPHZ128rmkz:
11569 case VMINPHZ128rr:
11570 case VMINPHZ128rrk:
11571 case VMINPHZ128rrkz:
11572 case VMINPHZ256rm:
11573 case VMINPHZ256rmb:
11574 case VMINPHZ256rmbk:
11575 case VMINPHZ256rmbkz:
11576 case VMINPHZ256rmk:
11577 case VMINPHZ256rmkz:
11578 case VMINPHZ256rr:
11579 case VMINPHZ256rrk:
11580 case VMINPHZ256rrkz:
11581 case VMINPHZrm:
11582 case VMINPHZrmb:
11583 case VMINPHZrmbk:
11584 case VMINPHZrmbkz:
11585 case VMINPHZrmk:
11586 case VMINPHZrmkz:
11587 case VMINPHZrr:
11588 case VMINPHZrrb:
11589 case VMINPHZrrbk:
11590 case VMINPHZrrbkz:
11591 case VMINPHZrrk:
11592 case VMINPHZrrkz:
11593 return true;
11594 }
11595 return false;
11596}
11597
11598bool isVMINSD(unsigned Opcode) {
11599 switch (Opcode) {
11600 case VMINSDZrm_Int:
11601 case VMINSDZrmk_Int:
11602 case VMINSDZrmkz_Int:
11603 case VMINSDZrr_Int:
11604 case VMINSDZrrb_Int:
11605 case VMINSDZrrbk_Int:
11606 case VMINSDZrrbkz_Int:
11607 case VMINSDZrrk_Int:
11608 case VMINSDZrrkz_Int:
11609 case VMINSDrm_Int:
11610 case VMINSDrr_Int:
11611 return true;
11612 }
11613 return false;
11614}
11615
11616bool isVROUNDPD(unsigned Opcode) {
11617 switch (Opcode) {
11618 case VROUNDPDYmi:
11619 case VROUNDPDYri:
11620 case VROUNDPDmi:
11621 case VROUNDPDri:
11622 return true;
11623 }
11624 return false;
11625}
11626
11627bool isVFCMADDCPH(unsigned Opcode) {
11628 switch (Opcode) {
11629 case VFCMADDCPHZ128m:
11630 case VFCMADDCPHZ128mb:
11631 case VFCMADDCPHZ128mbk:
11632 case VFCMADDCPHZ128mbkz:
11633 case VFCMADDCPHZ128mk:
11634 case VFCMADDCPHZ128mkz:
11635 case VFCMADDCPHZ128r:
11636 case VFCMADDCPHZ128rk:
11637 case VFCMADDCPHZ128rkz:
11638 case VFCMADDCPHZ256m:
11639 case VFCMADDCPHZ256mb:
11640 case VFCMADDCPHZ256mbk:
11641 case VFCMADDCPHZ256mbkz:
11642 case VFCMADDCPHZ256mk:
11643 case VFCMADDCPHZ256mkz:
11644 case VFCMADDCPHZ256r:
11645 case VFCMADDCPHZ256rk:
11646 case VFCMADDCPHZ256rkz:
11647 case VFCMADDCPHZm:
11648 case VFCMADDCPHZmb:
11649 case VFCMADDCPHZmbk:
11650 case VFCMADDCPHZmbkz:
11651 case VFCMADDCPHZmk:
11652 case VFCMADDCPHZmkz:
11653 case VFCMADDCPHZr:
11654 case VFCMADDCPHZrb:
11655 case VFCMADDCPHZrbk:
11656 case VFCMADDCPHZrbkz:
11657 case VFCMADDCPHZrk:
11658 case VFCMADDCPHZrkz:
11659 return true;
11660 }
11661 return false;
11662}
11663
11664bool isINCSSPQ(unsigned Opcode) {
11665 return Opcode == INCSSPQ;
11666}
11667
11668bool isVPUNPCKLDQ(unsigned Opcode) {
11669 switch (Opcode) {
11670 case VPUNPCKLDQYrm:
11671 case VPUNPCKLDQYrr:
11672 case VPUNPCKLDQZ128rm:
11673 case VPUNPCKLDQZ128rmb:
11674 case VPUNPCKLDQZ128rmbk:
11675 case VPUNPCKLDQZ128rmbkz:
11676 case VPUNPCKLDQZ128rmk:
11677 case VPUNPCKLDQZ128rmkz:
11678 case VPUNPCKLDQZ128rr:
11679 case VPUNPCKLDQZ128rrk:
11680 case VPUNPCKLDQZ128rrkz:
11681 case VPUNPCKLDQZ256rm:
11682 case VPUNPCKLDQZ256rmb:
11683 case VPUNPCKLDQZ256rmbk:
11684 case VPUNPCKLDQZ256rmbkz:
11685 case VPUNPCKLDQZ256rmk:
11686 case VPUNPCKLDQZ256rmkz:
11687 case VPUNPCKLDQZ256rr:
11688 case VPUNPCKLDQZ256rrk:
11689 case VPUNPCKLDQZ256rrkz:
11690 case VPUNPCKLDQZrm:
11691 case VPUNPCKLDQZrmb:
11692 case VPUNPCKLDQZrmbk:
11693 case VPUNPCKLDQZrmbkz:
11694 case VPUNPCKLDQZrmk:
11695 case VPUNPCKLDQZrmkz:
11696 case VPUNPCKLDQZrr:
11697 case VPUNPCKLDQZrrk:
11698 case VPUNPCKLDQZrrkz:
11699 case VPUNPCKLDQrm:
11700 case VPUNPCKLDQrr:
11701 return true;
11702 }
11703 return false;
11704}
11705
11706bool isVMINSH(unsigned Opcode) {
11707 switch (Opcode) {
11708 case VMINSHZrm_Int:
11709 case VMINSHZrmk_Int:
11710 case VMINSHZrmkz_Int:
11711 case VMINSHZrr_Int:
11712 case VMINSHZrrb_Int:
11713 case VMINSHZrrbk_Int:
11714 case VMINSHZrrbkz_Int:
11715 case VMINSHZrrk_Int:
11716 case VMINSHZrrkz_Int:
11717 return true;
11718 }
11719 return false;
11720}
11721
11722bool isINSERTQ(unsigned Opcode) {
11723 switch (Opcode) {
11724 case INSERTQ:
11725 case INSERTQI:
11726 return true;
11727 }
11728 return false;
11729}
11730
11731bool isBLCI(unsigned Opcode) {
11732 switch (Opcode) {
11733 case BLCI32rm:
11734 case BLCI32rr:
11735 case BLCI64rm:
11736 case BLCI64rr:
11737 return true;
11738 }
11739 return false;
11740}
11741
11742bool isHLT(unsigned Opcode) {
11743 return Opcode == HLT;
11744}
11745
11746bool isVPCOMUW(unsigned Opcode) {
11747 switch (Opcode) {
11748 case VPCOMUWmi:
11749 case VPCOMUWri:
11750 return true;
11751 }
11752 return false;
11753}
11754
11755bool isVPMOVSXDQ(unsigned Opcode) {
11756 switch (Opcode) {
11757 case VPMOVSXDQYrm:
11758 case VPMOVSXDQYrr:
11759 case VPMOVSXDQZ128rm:
11760 case VPMOVSXDQZ128rmk:
11761 case VPMOVSXDQZ128rmkz:
11762 case VPMOVSXDQZ128rr:
11763 case VPMOVSXDQZ128rrk:
11764 case VPMOVSXDQZ128rrkz:
11765 case VPMOVSXDQZ256rm:
11766 case VPMOVSXDQZ256rmk:
11767 case VPMOVSXDQZ256rmkz:
11768 case VPMOVSXDQZ256rr:
11769 case VPMOVSXDQZ256rrk:
11770 case VPMOVSXDQZ256rrkz:
11771 case VPMOVSXDQZrm:
11772 case VPMOVSXDQZrmk:
11773 case VPMOVSXDQZrmkz:
11774 case VPMOVSXDQZrr:
11775 case VPMOVSXDQZrrk:
11776 case VPMOVSXDQZrrkz:
11777 case VPMOVSXDQrm:
11778 case VPMOVSXDQrr:
11779 return true;
11780 }
11781 return false;
11782}
11783
11784bool isVFNMSUB231PS(unsigned Opcode) {
11785 switch (Opcode) {
11786 case VFNMSUB231PSYm:
11787 case VFNMSUB231PSYr:
11788 case VFNMSUB231PSZ128m:
11789 case VFNMSUB231PSZ128mb:
11790 case VFNMSUB231PSZ128mbk:
11791 case VFNMSUB231PSZ128mbkz:
11792 case VFNMSUB231PSZ128mk:
11793 case VFNMSUB231PSZ128mkz:
11794 case VFNMSUB231PSZ128r:
11795 case VFNMSUB231PSZ128rk:
11796 case VFNMSUB231PSZ128rkz:
11797 case VFNMSUB231PSZ256m:
11798 case VFNMSUB231PSZ256mb:
11799 case VFNMSUB231PSZ256mbk:
11800 case VFNMSUB231PSZ256mbkz:
11801 case VFNMSUB231PSZ256mk:
11802 case VFNMSUB231PSZ256mkz:
11803 case VFNMSUB231PSZ256r:
11804 case VFNMSUB231PSZ256rk:
11805 case VFNMSUB231PSZ256rkz:
11806 case VFNMSUB231PSZm:
11807 case VFNMSUB231PSZmb:
11808 case VFNMSUB231PSZmbk:
11809 case VFNMSUB231PSZmbkz:
11810 case VFNMSUB231PSZmk:
11811 case VFNMSUB231PSZmkz:
11812 case VFNMSUB231PSZr:
11813 case VFNMSUB231PSZrb:
11814 case VFNMSUB231PSZrbk:
11815 case VFNMSUB231PSZrbkz:
11816 case VFNMSUB231PSZrk:
11817 case VFNMSUB231PSZrkz:
11818 case VFNMSUB231PSm:
11819 case VFNMSUB231PSr:
11820 return true;
11821 }
11822 return false;
11823}
11824
11825bool isVFNMSUB213SH(unsigned Opcode) {
11826 switch (Opcode) {
11827 case VFNMSUB213SHZm_Int:
11828 case VFNMSUB213SHZmk_Int:
11829 case VFNMSUB213SHZmkz_Int:
11830 case VFNMSUB213SHZr_Int:
11831 case VFNMSUB213SHZrb_Int:
11832 case VFNMSUB213SHZrbk_Int:
11833 case VFNMSUB213SHZrbkz_Int:
11834 case VFNMSUB213SHZrk_Int:
11835 case VFNMSUB213SHZrkz_Int:
11836 return true;
11837 }
11838 return false;
11839}
11840
11841bool isVCVTTPD2UQQ(unsigned Opcode) {
11842 switch (Opcode) {
11843 case VCVTTPD2UQQZ128rm:
11844 case VCVTTPD2UQQZ128rmb:
11845 case VCVTTPD2UQQZ128rmbk:
11846 case VCVTTPD2UQQZ128rmbkz:
11847 case VCVTTPD2UQQZ128rmk:
11848 case VCVTTPD2UQQZ128rmkz:
11849 case VCVTTPD2UQQZ128rr:
11850 case VCVTTPD2UQQZ128rrk:
11851 case VCVTTPD2UQQZ128rrkz:
11852 case VCVTTPD2UQQZ256rm:
11853 case VCVTTPD2UQQZ256rmb:
11854 case VCVTTPD2UQQZ256rmbk:
11855 case VCVTTPD2UQQZ256rmbkz:
11856 case VCVTTPD2UQQZ256rmk:
11857 case VCVTTPD2UQQZ256rmkz:
11858 case VCVTTPD2UQQZ256rr:
11859 case VCVTTPD2UQQZ256rrk:
11860 case VCVTTPD2UQQZ256rrkz:
11861 case VCVTTPD2UQQZrm:
11862 case VCVTTPD2UQQZrmb:
11863 case VCVTTPD2UQQZrmbk:
11864 case VCVTTPD2UQQZrmbkz:
11865 case VCVTTPD2UQQZrmk:
11866 case VCVTTPD2UQQZrmkz:
11867 case VCVTTPD2UQQZrr:
11868 case VCVTTPD2UQQZrrb:
11869 case VCVTTPD2UQQZrrbk:
11870 case VCVTTPD2UQQZrrbkz:
11871 case VCVTTPD2UQQZrrk:
11872 case VCVTTPD2UQQZrrkz:
11873 return true;
11874 }
11875 return false;
11876}
11877
11878bool isSQRTSS(unsigned Opcode) {
11879 switch (Opcode) {
11880 case SQRTSSm_Int:
11881 case SQRTSSr_Int:
11882 return true;
11883 }
11884 return false;
11885}
11886
11887bool isIMUL(unsigned Opcode) {
11888 switch (Opcode) {
11889 case IMUL16m:
11890 case IMUL16m_EVEX:
11891 case IMUL16m_NF:
11892 case IMUL16r:
11893 case IMUL16r_EVEX:
11894 case IMUL16r_NF:
11895 case IMUL16rm:
11896 case IMUL16rm_EVEX:
11897 case IMUL16rm_ND:
11898 case IMUL16rm_NF:
11899 case IMUL16rm_NF_ND:
11900 case IMUL16rmi:
11901 case IMUL16rmi8:
11902 case IMUL16rmi8_EVEX:
11903 case IMUL16rmi8_NF:
11904 case IMUL16rmi_EVEX:
11905 case IMUL16rmi_NF:
11906 case IMUL16rr:
11907 case IMUL16rr_EVEX:
11908 case IMUL16rr_ND:
11909 case IMUL16rr_NF:
11910 case IMUL16rr_NF_ND:
11911 case IMUL16rri:
11912 case IMUL16rri8:
11913 case IMUL16rri8_EVEX:
11914 case IMUL16rri8_NF:
11915 case IMUL16rri_EVEX:
11916 case IMUL16rri_NF:
11917 case IMUL32m:
11918 case IMUL32m_EVEX:
11919 case IMUL32m_NF:
11920 case IMUL32r:
11921 case IMUL32r_EVEX:
11922 case IMUL32r_NF:
11923 case IMUL32rm:
11924 case IMUL32rm_EVEX:
11925 case IMUL32rm_ND:
11926 case IMUL32rm_NF:
11927 case IMUL32rm_NF_ND:
11928 case IMUL32rmi:
11929 case IMUL32rmi8:
11930 case IMUL32rmi8_EVEX:
11931 case IMUL32rmi8_NF:
11932 case IMUL32rmi_EVEX:
11933 case IMUL32rmi_NF:
11934 case IMUL32rr:
11935 case IMUL32rr_EVEX:
11936 case IMUL32rr_ND:
11937 case IMUL32rr_NF:
11938 case IMUL32rr_NF_ND:
11939 case IMUL32rri:
11940 case IMUL32rri8:
11941 case IMUL32rri8_EVEX:
11942 case IMUL32rri8_NF:
11943 case IMUL32rri_EVEX:
11944 case IMUL32rri_NF:
11945 case IMUL64m:
11946 case IMUL64m_EVEX:
11947 case IMUL64m_NF:
11948 case IMUL64r:
11949 case IMUL64r_EVEX:
11950 case IMUL64r_NF:
11951 case IMUL64rm:
11952 case IMUL64rm_EVEX:
11953 case IMUL64rm_ND:
11954 case IMUL64rm_NF:
11955 case IMUL64rm_NF_ND:
11956 case IMUL64rmi32:
11957 case IMUL64rmi32_EVEX:
11958 case IMUL64rmi32_NF:
11959 case IMUL64rmi8:
11960 case IMUL64rmi8_EVEX:
11961 case IMUL64rmi8_NF:
11962 case IMUL64rr:
11963 case IMUL64rr_EVEX:
11964 case IMUL64rr_ND:
11965 case IMUL64rr_NF:
11966 case IMUL64rr_NF_ND:
11967 case IMUL64rri32:
11968 case IMUL64rri32_EVEX:
11969 case IMUL64rri32_NF:
11970 case IMUL64rri8:
11971 case IMUL64rri8_EVEX:
11972 case IMUL64rri8_NF:
11973 case IMUL8m:
11974 case IMUL8m_EVEX:
11975 case IMUL8m_NF:
11976 case IMUL8r:
11977 case IMUL8r_EVEX:
11978 case IMUL8r_NF:
11979 return true;
11980 }
11981 return false;
11982}
11983
11984bool isVCVTSS2SI(unsigned Opcode) {
11985 switch (Opcode) {
11986 case VCVTSS2SI64Zrm_Int:
11987 case VCVTSS2SI64Zrr_Int:
11988 case VCVTSS2SI64Zrrb_Int:
11989 case VCVTSS2SI64rm_Int:
11990 case VCVTSS2SI64rr_Int:
11991 case VCVTSS2SIZrm_Int:
11992 case VCVTSS2SIZrr_Int:
11993 case VCVTSS2SIZrrb_Int:
11994 case VCVTSS2SIrm_Int:
11995 case VCVTSS2SIrr_Int:
11996 return true;
11997 }
11998 return false;
11999}
12000
12001bool isPUSHAW(unsigned Opcode) {
12002 return Opcode == PUSHA16;
12003}
12004
12005bool isSTOSD(unsigned Opcode) {
12006 return Opcode == STOSL;
12007}
12008
12009bool isPSRLDQ(unsigned Opcode) {
12010 return Opcode == PSRLDQri;
12011}
12012
12013bool isVSCATTERQPS(unsigned Opcode) {
12014 switch (Opcode) {
12015 case VSCATTERQPSZ128mr:
12016 case VSCATTERQPSZ256mr:
12017 case VSCATTERQPSZmr:
12018 return true;
12019 }
12020 return false;
12021}
12022
12023bool isFIDIV(unsigned Opcode) {
12024 switch (Opcode) {
12025 case DIV_FI16m:
12026 case DIV_FI32m:
12027 return true;
12028 }
12029 return false;
12030}
12031
12032bool isVFMSUB213PD(unsigned Opcode) {
12033 switch (Opcode) {
12034 case VFMSUB213PDYm:
12035 case VFMSUB213PDYr:
12036 case VFMSUB213PDZ128m:
12037 case VFMSUB213PDZ128mb:
12038 case VFMSUB213PDZ128mbk:
12039 case VFMSUB213PDZ128mbkz:
12040 case VFMSUB213PDZ128mk:
12041 case VFMSUB213PDZ128mkz:
12042 case VFMSUB213PDZ128r:
12043 case VFMSUB213PDZ128rk:
12044 case VFMSUB213PDZ128rkz:
12045 case VFMSUB213PDZ256m:
12046 case VFMSUB213PDZ256mb:
12047 case VFMSUB213PDZ256mbk:
12048 case VFMSUB213PDZ256mbkz:
12049 case VFMSUB213PDZ256mk:
12050 case VFMSUB213PDZ256mkz:
12051 case VFMSUB213PDZ256r:
12052 case VFMSUB213PDZ256rk:
12053 case VFMSUB213PDZ256rkz:
12054 case VFMSUB213PDZm:
12055 case VFMSUB213PDZmb:
12056 case VFMSUB213PDZmbk:
12057 case VFMSUB213PDZmbkz:
12058 case VFMSUB213PDZmk:
12059 case VFMSUB213PDZmkz:
12060 case VFMSUB213PDZr:
12061 case VFMSUB213PDZrb:
12062 case VFMSUB213PDZrbk:
12063 case VFMSUB213PDZrbkz:
12064 case VFMSUB213PDZrk:
12065 case VFMSUB213PDZrkz:
12066 case VFMSUB213PDm:
12067 case VFMSUB213PDr:
12068 return true;
12069 }
12070 return false;
12071}
12072
12073bool isVFMADDSUB231PH(unsigned Opcode) {
12074 switch (Opcode) {
12075 case VFMADDSUB231PHZ128m:
12076 case VFMADDSUB231PHZ128mb:
12077 case VFMADDSUB231PHZ128mbk:
12078 case VFMADDSUB231PHZ128mbkz:
12079 case VFMADDSUB231PHZ128mk:
12080 case VFMADDSUB231PHZ128mkz:
12081 case VFMADDSUB231PHZ128r:
12082 case VFMADDSUB231PHZ128rk:
12083 case VFMADDSUB231PHZ128rkz:
12084 case VFMADDSUB231PHZ256m:
12085 case VFMADDSUB231PHZ256mb:
12086 case VFMADDSUB231PHZ256mbk:
12087 case VFMADDSUB231PHZ256mbkz:
12088 case VFMADDSUB231PHZ256mk:
12089 case VFMADDSUB231PHZ256mkz:
12090 case VFMADDSUB231PHZ256r:
12091 case VFMADDSUB231PHZ256rk:
12092 case VFMADDSUB231PHZ256rkz:
12093 case VFMADDSUB231PHZm:
12094 case VFMADDSUB231PHZmb:
12095 case VFMADDSUB231PHZmbk:
12096 case VFMADDSUB231PHZmbkz:
12097 case VFMADDSUB231PHZmk:
12098 case VFMADDSUB231PHZmkz:
12099 case VFMADDSUB231PHZr:
12100 case VFMADDSUB231PHZrb:
12101 case VFMADDSUB231PHZrbk:
12102 case VFMADDSUB231PHZrbkz:
12103 case VFMADDSUB231PHZrk:
12104 case VFMADDSUB231PHZrkz:
12105 return true;
12106 }
12107 return false;
12108}
12109
12110bool isTDCALL(unsigned Opcode) {
12111 return Opcode == TDCALL;
12112}
12113
12114bool isPVALIDATE(unsigned Opcode) {
12115 switch (Opcode) {
12116 case PVALIDATE32:
12117 case PVALIDATE64:
12118 return true;
12119 }
12120 return false;
12121}
12122
12123bool isVPSHUFLW(unsigned Opcode) {
12124 switch (Opcode) {
12125 case VPSHUFLWYmi:
12126 case VPSHUFLWYri:
12127 case VPSHUFLWZ128mi:
12128 case VPSHUFLWZ128mik:
12129 case VPSHUFLWZ128mikz:
12130 case VPSHUFLWZ128ri:
12131 case VPSHUFLWZ128rik:
12132 case VPSHUFLWZ128rikz:
12133 case VPSHUFLWZ256mi:
12134 case VPSHUFLWZ256mik:
12135 case VPSHUFLWZ256mikz:
12136 case VPSHUFLWZ256ri:
12137 case VPSHUFLWZ256rik:
12138 case VPSHUFLWZ256rikz:
12139 case VPSHUFLWZmi:
12140 case VPSHUFLWZmik:
12141 case VPSHUFLWZmikz:
12142 case VPSHUFLWZri:
12143 case VPSHUFLWZrik:
12144 case VPSHUFLWZrikz:
12145 case VPSHUFLWmi:
12146 case VPSHUFLWri:
12147 return true;
12148 }
12149 return false;
12150}
12151
12152bool isPCLMULQDQ(unsigned Opcode) {
12153 switch (Opcode) {
12154 case PCLMULQDQrmi:
12155 case PCLMULQDQrri:
12156 return true;
12157 }
12158 return false;
12159}
12160
12161bool isCMPXCHG8B(unsigned Opcode) {
12162 return Opcode == CMPXCHG8B;
12163}
12164
12165bool isVPMOVM2B(unsigned Opcode) {
12166 switch (Opcode) {
12167 case VPMOVM2BZ128rk:
12168 case VPMOVM2BZ256rk:
12169 case VPMOVM2BZrk:
12170 return true;
12171 }
12172 return false;
12173}
12174
12175bool isVCVTUDQ2PH(unsigned Opcode) {
12176 switch (Opcode) {
12177 case VCVTUDQ2PHZ128rm:
12178 case VCVTUDQ2PHZ128rmb:
12179 case VCVTUDQ2PHZ128rmbk:
12180 case VCVTUDQ2PHZ128rmbkz:
12181 case VCVTUDQ2PHZ128rmk:
12182 case VCVTUDQ2PHZ128rmkz:
12183 case VCVTUDQ2PHZ128rr:
12184 case VCVTUDQ2PHZ128rrk:
12185 case VCVTUDQ2PHZ128rrkz:
12186 case VCVTUDQ2PHZ256rm:
12187 case VCVTUDQ2PHZ256rmb:
12188 case VCVTUDQ2PHZ256rmbk:
12189 case VCVTUDQ2PHZ256rmbkz:
12190 case VCVTUDQ2PHZ256rmk:
12191 case VCVTUDQ2PHZ256rmkz:
12192 case VCVTUDQ2PHZ256rr:
12193 case VCVTUDQ2PHZ256rrk:
12194 case VCVTUDQ2PHZ256rrkz:
12195 case VCVTUDQ2PHZrm:
12196 case VCVTUDQ2PHZrmb:
12197 case VCVTUDQ2PHZrmbk:
12198 case VCVTUDQ2PHZrmbkz:
12199 case VCVTUDQ2PHZrmk:
12200 case VCVTUDQ2PHZrmkz:
12201 case VCVTUDQ2PHZrr:
12202 case VCVTUDQ2PHZrrb:
12203 case VCVTUDQ2PHZrrbk:
12204 case VCVTUDQ2PHZrrbkz:
12205 case VCVTUDQ2PHZrrk:
12206 case VCVTUDQ2PHZrrkz:
12207 return true;
12208 }
12209 return false;
12210}
12211
12212bool isPEXTRQ(unsigned Opcode) {
12213 switch (Opcode) {
12214 case PEXTRQmri:
12215 case PEXTRQrri:
12216 return true;
12217 }
12218 return false;
12219}
12220
12221bool isXCRYPTCTR(unsigned Opcode) {
12222 return Opcode == XCRYPTCTR;
12223}
12224
12225bool isVREDUCEPH(unsigned Opcode) {
12226 switch (Opcode) {
12227 case VREDUCEPHZ128rmbi:
12228 case VREDUCEPHZ128rmbik:
12229 case VREDUCEPHZ128rmbikz:
12230 case VREDUCEPHZ128rmi:
12231 case VREDUCEPHZ128rmik:
12232 case VREDUCEPHZ128rmikz:
12233 case VREDUCEPHZ128rri:
12234 case VREDUCEPHZ128rrik:
12235 case VREDUCEPHZ128rrikz:
12236 case VREDUCEPHZ256rmbi:
12237 case VREDUCEPHZ256rmbik:
12238 case VREDUCEPHZ256rmbikz:
12239 case VREDUCEPHZ256rmi:
12240 case VREDUCEPHZ256rmik:
12241 case VREDUCEPHZ256rmikz:
12242 case VREDUCEPHZ256rri:
12243 case VREDUCEPHZ256rrik:
12244 case VREDUCEPHZ256rrikz:
12245 case VREDUCEPHZrmbi:
12246 case VREDUCEPHZrmbik:
12247 case VREDUCEPHZrmbikz:
12248 case VREDUCEPHZrmi:
12249 case VREDUCEPHZrmik:
12250 case VREDUCEPHZrmikz:
12251 case VREDUCEPHZrri:
12252 case VREDUCEPHZrrib:
12253 case VREDUCEPHZrribk:
12254 case VREDUCEPHZrribkz:
12255 case VREDUCEPHZrrik:
12256 case VREDUCEPHZrrikz:
12257 return true;
12258 }
12259 return false;
12260}
12261
12262bool isUCOMISD(unsigned Opcode) {
12263 switch (Opcode) {
12264 case UCOMISDrm:
12265 case UCOMISDrr:
12266 return true;
12267 }
12268 return false;
12269}
12270
12271bool isOUTSD(unsigned Opcode) {
12272 return Opcode == OUTSL;
12273}
12274
12275bool isSUBSS(unsigned Opcode) {
12276 switch (Opcode) {
12277 case SUBSSrm_Int:
12278 case SUBSSrr_Int:
12279 return true;
12280 }
12281 return false;
12282}
12283
12284bool isVFMSUBPS(unsigned Opcode) {
12285 switch (Opcode) {
12286 case VFMSUBPS4Ymr:
12287 case VFMSUBPS4Yrm:
12288 case VFMSUBPS4Yrr:
12289 case VFMSUBPS4Yrr_REV:
12290 case VFMSUBPS4mr:
12291 case VFMSUBPS4rm:
12292 case VFMSUBPS4rr:
12293 case VFMSUBPS4rr_REV:
12294 return true;
12295 }
12296 return false;
12297}
12298
12299bool isVPBLENDW(unsigned Opcode) {
12300 switch (Opcode) {
12301 case VPBLENDWYrmi:
12302 case VPBLENDWYrri:
12303 case VPBLENDWrmi:
12304 case VPBLENDWrri:
12305 return true;
12306 }
12307 return false;
12308}
12309
12310bool isBZHI(unsigned Opcode) {
12311 switch (Opcode) {
12312 case BZHI32rm:
12313 case BZHI32rm_EVEX:
12314 case BZHI32rm_NF:
12315 case BZHI32rr:
12316 case BZHI32rr_EVEX:
12317 case BZHI32rr_NF:
12318 case BZHI64rm:
12319 case BZHI64rm_EVEX:
12320 case BZHI64rm_NF:
12321 case BZHI64rr:
12322 case BZHI64rr_EVEX:
12323 case BZHI64rr_NF:
12324 return true;
12325 }
12326 return false;
12327}
12328
12329bool isVPRORVD(unsigned Opcode) {
12330 switch (Opcode) {
12331 case VPRORVDZ128rm:
12332 case VPRORVDZ128rmb:
12333 case VPRORVDZ128rmbk:
12334 case VPRORVDZ128rmbkz:
12335 case VPRORVDZ128rmk:
12336 case VPRORVDZ128rmkz:
12337 case VPRORVDZ128rr:
12338 case VPRORVDZ128rrk:
12339 case VPRORVDZ128rrkz:
12340 case VPRORVDZ256rm:
12341 case VPRORVDZ256rmb:
12342 case VPRORVDZ256rmbk:
12343 case VPRORVDZ256rmbkz:
12344 case VPRORVDZ256rmk:
12345 case VPRORVDZ256rmkz:
12346 case VPRORVDZ256rr:
12347 case VPRORVDZ256rrk:
12348 case VPRORVDZ256rrkz:
12349 case VPRORVDZrm:
12350 case VPRORVDZrmb:
12351 case VPRORVDZrmbk:
12352 case VPRORVDZrmbkz:
12353 case VPRORVDZrmk:
12354 case VPRORVDZrmkz:
12355 case VPRORVDZrr:
12356 case VPRORVDZrrk:
12357 case VPRORVDZrrkz:
12358 return true;
12359 }
12360 return false;
12361}
12362
12363bool isRMPQUERY(unsigned Opcode) {
12364 return Opcode == RMPQUERY;
12365}
12366
12367bool isVPEXPANDB(unsigned Opcode) {
12368 switch (Opcode) {
12369 case VPEXPANDBZ128rm:
12370 case VPEXPANDBZ128rmk:
12371 case VPEXPANDBZ128rmkz:
12372 case VPEXPANDBZ128rr:
12373 case VPEXPANDBZ128rrk:
12374 case VPEXPANDBZ128rrkz:
12375 case VPEXPANDBZ256rm:
12376 case VPEXPANDBZ256rmk:
12377 case VPEXPANDBZ256rmkz:
12378 case VPEXPANDBZ256rr:
12379 case VPEXPANDBZ256rrk:
12380 case VPEXPANDBZ256rrkz:
12381 case VPEXPANDBZrm:
12382 case VPEXPANDBZrmk:
12383 case VPEXPANDBZrmkz:
12384 case VPEXPANDBZrr:
12385 case VPEXPANDBZrrk:
12386 case VPEXPANDBZrrkz:
12387 return true;
12388 }
12389 return false;
12390}
12391
12392bool isVPSCATTERDQ(unsigned Opcode) {
12393 switch (Opcode) {
12394 case VPSCATTERDQZ128mr:
12395 case VPSCATTERDQZ256mr:
12396 case VPSCATTERDQZmr:
12397 return true;
12398 }
12399 return false;
12400}
12401
12402bool isPSMASH(unsigned Opcode) {
12403 return Opcode == PSMASH;
12404}
12405
12406bool isVPSHLDQ(unsigned Opcode) {
12407 switch (Opcode) {
12408 case VPSHLDQZ128rmbi:
12409 case VPSHLDQZ128rmbik:
12410 case VPSHLDQZ128rmbikz:
12411 case VPSHLDQZ128rmi:
12412 case VPSHLDQZ128rmik:
12413 case VPSHLDQZ128rmikz:
12414 case VPSHLDQZ128rri:
12415 case VPSHLDQZ128rrik:
12416 case VPSHLDQZ128rrikz:
12417 case VPSHLDQZ256rmbi:
12418 case VPSHLDQZ256rmbik:
12419 case VPSHLDQZ256rmbikz:
12420 case VPSHLDQZ256rmi:
12421 case VPSHLDQZ256rmik:
12422 case VPSHLDQZ256rmikz:
12423 case VPSHLDQZ256rri:
12424 case VPSHLDQZ256rrik:
12425 case VPSHLDQZ256rrikz:
12426 case VPSHLDQZrmbi:
12427 case VPSHLDQZrmbik:
12428 case VPSHLDQZrmbikz:
12429 case VPSHLDQZrmi:
12430 case VPSHLDQZrmik:
12431 case VPSHLDQZrmikz:
12432 case VPSHLDQZrri:
12433 case VPSHLDQZrrik:
12434 case VPSHLDQZrrikz:
12435 return true;
12436 }
12437 return false;
12438}
12439
12440bool isVSCATTERPF1DPD(unsigned Opcode) {
12441 return Opcode == VSCATTERPF1DPDm;
12442}
12443
12444bool isMONTMUL(unsigned Opcode) {
12445 return Opcode == MONTMUL;
12446}
12447
12448bool isVCVTPH2UQQ(unsigned Opcode) {
12449 switch (Opcode) {
12450 case VCVTPH2UQQZ128rm:
12451 case VCVTPH2UQQZ128rmb:
12452 case VCVTPH2UQQZ128rmbk:
12453 case VCVTPH2UQQZ128rmbkz:
12454 case VCVTPH2UQQZ128rmk:
12455 case VCVTPH2UQQZ128rmkz:
12456 case VCVTPH2UQQZ128rr:
12457 case VCVTPH2UQQZ128rrk:
12458 case VCVTPH2UQQZ128rrkz:
12459 case VCVTPH2UQQZ256rm:
12460 case VCVTPH2UQQZ256rmb:
12461 case VCVTPH2UQQZ256rmbk:
12462 case VCVTPH2UQQZ256rmbkz:
12463 case VCVTPH2UQQZ256rmk:
12464 case VCVTPH2UQQZ256rmkz:
12465 case VCVTPH2UQQZ256rr:
12466 case VCVTPH2UQQZ256rrk:
12467 case VCVTPH2UQQZ256rrkz:
12468 case VCVTPH2UQQZrm:
12469 case VCVTPH2UQQZrmb:
12470 case VCVTPH2UQQZrmbk:
12471 case VCVTPH2UQQZrmbkz:
12472 case VCVTPH2UQQZrmk:
12473 case VCVTPH2UQQZrmkz:
12474 case VCVTPH2UQQZrr:
12475 case VCVTPH2UQQZrrb:
12476 case VCVTPH2UQQZrrbk:
12477 case VCVTPH2UQQZrrbkz:
12478 case VCVTPH2UQQZrrk:
12479 case VCVTPH2UQQZrrkz:
12480 return true;
12481 }
12482 return false;
12483}
12484
12485bool isPSLLD(unsigned Opcode) {
12486 switch (Opcode) {
12487 case MMX_PSLLDri:
12488 case MMX_PSLLDrm:
12489 case MMX_PSLLDrr:
12490 case PSLLDri:
12491 case PSLLDrm:
12492 case PSLLDrr:
12493 return true;
12494 }
12495 return false;
12496}
12497
12498bool isSAR(unsigned Opcode) {
12499 switch (Opcode) {
12500 case SAR16m1:
12501 case SAR16m1_EVEX:
12502 case SAR16m1_ND:
12503 case SAR16m1_NF:
12504 case SAR16m1_NF_ND:
12505 case SAR16mCL:
12506 case SAR16mCL_EVEX:
12507 case SAR16mCL_ND:
12508 case SAR16mCL_NF:
12509 case SAR16mCL_NF_ND:
12510 case SAR16mi:
12511 case SAR16mi_EVEX:
12512 case SAR16mi_ND:
12513 case SAR16mi_NF:
12514 case SAR16mi_NF_ND:
12515 case SAR16r1:
12516 case SAR16r1_EVEX:
12517 case SAR16r1_ND:
12518 case SAR16r1_NF:
12519 case SAR16r1_NF_ND:
12520 case SAR16rCL:
12521 case SAR16rCL_EVEX:
12522 case SAR16rCL_ND:
12523 case SAR16rCL_NF:
12524 case SAR16rCL_NF_ND:
12525 case SAR16ri:
12526 case SAR16ri_EVEX:
12527 case SAR16ri_ND:
12528 case SAR16ri_NF:
12529 case SAR16ri_NF_ND:
12530 case SAR32m1:
12531 case SAR32m1_EVEX:
12532 case SAR32m1_ND:
12533 case SAR32m1_NF:
12534 case SAR32m1_NF_ND:
12535 case SAR32mCL:
12536 case SAR32mCL_EVEX:
12537 case SAR32mCL_ND:
12538 case SAR32mCL_NF:
12539 case SAR32mCL_NF_ND:
12540 case SAR32mi:
12541 case SAR32mi_EVEX:
12542 case SAR32mi_ND:
12543 case SAR32mi_NF:
12544 case SAR32mi_NF_ND:
12545 case SAR32r1:
12546 case SAR32r1_EVEX:
12547 case SAR32r1_ND:
12548 case SAR32r1_NF:
12549 case SAR32r1_NF_ND:
12550 case SAR32rCL:
12551 case SAR32rCL_EVEX:
12552 case SAR32rCL_ND:
12553 case SAR32rCL_NF:
12554 case SAR32rCL_NF_ND:
12555 case SAR32ri:
12556 case SAR32ri_EVEX:
12557 case SAR32ri_ND:
12558 case SAR32ri_NF:
12559 case SAR32ri_NF_ND:
12560 case SAR64m1:
12561 case SAR64m1_EVEX:
12562 case SAR64m1_ND:
12563 case SAR64m1_NF:
12564 case SAR64m1_NF_ND:
12565 case SAR64mCL:
12566 case SAR64mCL_EVEX:
12567 case SAR64mCL_ND:
12568 case SAR64mCL_NF:
12569 case SAR64mCL_NF_ND:
12570 case SAR64mi:
12571 case SAR64mi_EVEX:
12572 case SAR64mi_ND:
12573 case SAR64mi_NF:
12574 case SAR64mi_NF_ND:
12575 case SAR64r1:
12576 case SAR64r1_EVEX:
12577 case SAR64r1_ND:
12578 case SAR64r1_NF:
12579 case SAR64r1_NF_ND:
12580 case SAR64rCL:
12581 case SAR64rCL_EVEX:
12582 case SAR64rCL_ND:
12583 case SAR64rCL_NF:
12584 case SAR64rCL_NF_ND:
12585 case SAR64ri:
12586 case SAR64ri_EVEX:
12587 case SAR64ri_ND:
12588 case SAR64ri_NF:
12589 case SAR64ri_NF_ND:
12590 case SAR8m1:
12591 case SAR8m1_EVEX:
12592 case SAR8m1_ND:
12593 case SAR8m1_NF:
12594 case SAR8m1_NF_ND:
12595 case SAR8mCL:
12596 case SAR8mCL_EVEX:
12597 case SAR8mCL_ND:
12598 case SAR8mCL_NF:
12599 case SAR8mCL_NF_ND:
12600 case SAR8mi:
12601 case SAR8mi_EVEX:
12602 case SAR8mi_ND:
12603 case SAR8mi_NF:
12604 case SAR8mi_NF_ND:
12605 case SAR8r1:
12606 case SAR8r1_EVEX:
12607 case SAR8r1_ND:
12608 case SAR8r1_NF:
12609 case SAR8r1_NF_ND:
12610 case SAR8rCL:
12611 case SAR8rCL_EVEX:
12612 case SAR8rCL_ND:
12613 case SAR8rCL_NF:
12614 case SAR8rCL_NF_ND:
12615 case SAR8ri:
12616 case SAR8ri_EVEX:
12617 case SAR8ri_ND:
12618 case SAR8ri_NF:
12619 case SAR8ri_NF_ND:
12620 return true;
12621 }
12622 return false;
12623}
12624
12625bool isLDTILECFG(unsigned Opcode) {
12626 switch (Opcode) {
12627 case LDTILECFG:
12628 case LDTILECFG_EVEX:
12629 return true;
12630 }
12631 return false;
12632}
12633
12634bool isPMINUB(unsigned Opcode) {
12635 switch (Opcode) {
12636 case MMX_PMINUBrm:
12637 case MMX_PMINUBrr:
12638 case PMINUBrm:
12639 case PMINUBrr:
12640 return true;
12641 }
12642 return false;
12643}
12644
12645bool isVCVTNEEBF162PS(unsigned Opcode) {
12646 switch (Opcode) {
12647 case VCVTNEEBF162PSYrm:
12648 case VCVTNEEBF162PSrm:
12649 return true;
12650 }
12651 return false;
12652}
12653
12654bool isMOVDIR64B(unsigned Opcode) {
12655 switch (Opcode) {
12656 case MOVDIR64B16:
12657 case MOVDIR64B32:
12658 case MOVDIR64B32_EVEX:
12659 case MOVDIR64B64:
12660 case MOVDIR64B64_EVEX:
12661 return true;
12662 }
12663 return false;
12664}
12665
12666bool isSTR(unsigned Opcode) {
12667 switch (Opcode) {
12668 case STR16r:
12669 case STR32r:
12670 case STR64r:
12671 case STRm:
12672 return true;
12673 }
12674 return false;
12675}
12676
12677bool isKANDNQ(unsigned Opcode) {
12678 return Opcode == KANDNQkk;
12679}
12680
12681bool isBSF(unsigned Opcode) {
12682 switch (Opcode) {
12683 case BSF16rm:
12684 case BSF16rr:
12685 case BSF32rm:
12686 case BSF32rr:
12687 case BSF64rm:
12688 case BSF64rr:
12689 return true;
12690 }
12691 return false;
12692}
12693
12694bool isVPDPBUUDS(unsigned Opcode) {
12695 switch (Opcode) {
12696 case VPDPBUUDSYrm:
12697 case VPDPBUUDSYrr:
12698 case VPDPBUUDSZ128rm:
12699 case VPDPBUUDSZ128rmb:
12700 case VPDPBUUDSZ128rmbk:
12701 case VPDPBUUDSZ128rmbkz:
12702 case VPDPBUUDSZ128rmk:
12703 case VPDPBUUDSZ128rmkz:
12704 case VPDPBUUDSZ128rr:
12705 case VPDPBUUDSZ128rrk:
12706 case VPDPBUUDSZ128rrkz:
12707 case VPDPBUUDSZ256rm:
12708 case VPDPBUUDSZ256rmb:
12709 case VPDPBUUDSZ256rmbk:
12710 case VPDPBUUDSZ256rmbkz:
12711 case VPDPBUUDSZ256rmk:
12712 case VPDPBUUDSZ256rmkz:
12713 case VPDPBUUDSZ256rr:
12714 case VPDPBUUDSZ256rrk:
12715 case VPDPBUUDSZ256rrkz:
12716 case VPDPBUUDSZrm:
12717 case VPDPBUUDSZrmb:
12718 case VPDPBUUDSZrmbk:
12719 case VPDPBUUDSZrmbkz:
12720 case VPDPBUUDSZrmk:
12721 case VPDPBUUDSZrmkz:
12722 case VPDPBUUDSZrr:
12723 case VPDPBUUDSZrrk:
12724 case VPDPBUUDSZrrkz:
12725 case VPDPBUUDSrm:
12726 case VPDPBUUDSrr:
12727 return true;
12728 }
12729 return false;
12730}
12731
12732bool isINCSSPD(unsigned Opcode) {
12733 return Opcode == INCSSPD;
12734}
12735
12736bool isSQRTPS(unsigned Opcode) {
12737 switch (Opcode) {
12738 case SQRTPSm:
12739 case SQRTPSr:
12740 return true;
12741 }
12742 return false;
12743}
12744
12745bool isCMPXCHG(unsigned Opcode) {
12746 switch (Opcode) {
12747 case CMPXCHG16rm:
12748 case CMPXCHG16rr:
12749 case CMPXCHG32rm:
12750 case CMPXCHG32rr:
12751 case CMPXCHG64rm:
12752 case CMPXCHG64rr:
12753 case CMPXCHG8rm:
12754 case CMPXCHG8rr:
12755 return true;
12756 }
12757 return false;
12758}
12759
12760bool isVPSIGNW(unsigned Opcode) {
12761 switch (Opcode) {
12762 case VPSIGNWYrm:
12763 case VPSIGNWYrr:
12764 case VPSIGNWrm:
12765 case VPSIGNWrr:
12766 return true;
12767 }
12768 return false;
12769}
12770
12771bool isVCOMISBF16(unsigned Opcode) {
12772 switch (Opcode) {
12773 case VCOMISBF16Zrm:
12774 case VCOMISBF16Zrr:
12775 return true;
12776 }
12777 return false;
12778}
12779
12780bool isLES(unsigned Opcode) {
12781 switch (Opcode) {
12782 case LES16rm:
12783 case LES32rm:
12784 return true;
12785 }
12786 return false;
12787}
12788
12789bool isCVTSS2SI(unsigned Opcode) {
12790 switch (Opcode) {
12791 case CVTSS2SI64rm_Int:
12792 case CVTSS2SI64rr_Int:
12793 case CVTSS2SIrm_Int:
12794 case CVTSS2SIrr_Int:
12795 return true;
12796 }
12797 return false;
12798}
12799
12800bool isVPMOVUSWB(unsigned Opcode) {
12801 switch (Opcode) {
12802 case VPMOVUSWBZ128mr:
12803 case VPMOVUSWBZ128mrk:
12804 case VPMOVUSWBZ128rr:
12805 case VPMOVUSWBZ128rrk:
12806 case VPMOVUSWBZ128rrkz:
12807 case VPMOVUSWBZ256mr:
12808 case VPMOVUSWBZ256mrk:
12809 case VPMOVUSWBZ256rr:
12810 case VPMOVUSWBZ256rrk:
12811 case VPMOVUSWBZ256rrkz:
12812 case VPMOVUSWBZmr:
12813 case VPMOVUSWBZmrk:
12814 case VPMOVUSWBZrr:
12815 case VPMOVUSWBZrrk:
12816 case VPMOVUSWBZrrkz:
12817 return true;
12818 }
12819 return false;
12820}
12821
12822bool isFCOMPI(unsigned Opcode) {
12823 return Opcode == COM_FIPr;
12824}
12825
12826bool isPUNPCKHWD(unsigned Opcode) {
12827 switch (Opcode) {
12828 case MMX_PUNPCKHWDrm:
12829 case MMX_PUNPCKHWDrr:
12830 case PUNPCKHWDrm:
12831 case PUNPCKHWDrr:
12832 return true;
12833 }
12834 return false;
12835}
12836
12837bool isPFACC(unsigned Opcode) {
12838 switch (Opcode) {
12839 case PFACCrm:
12840 case PFACCrr:
12841 return true;
12842 }
12843 return false;
12844}
12845
12846bool isVPTESTNMW(unsigned Opcode) {
12847 switch (Opcode) {
12848 case VPTESTNMWZ128rm:
12849 case VPTESTNMWZ128rmk:
12850 case VPTESTNMWZ128rr:
12851 case VPTESTNMWZ128rrk:
12852 case VPTESTNMWZ256rm:
12853 case VPTESTNMWZ256rmk:
12854 case VPTESTNMWZ256rr:
12855 case VPTESTNMWZ256rrk:
12856 case VPTESTNMWZrm:
12857 case VPTESTNMWZrmk:
12858 case VPTESTNMWZrr:
12859 case VPTESTNMWZrrk:
12860 return true;
12861 }
12862 return false;
12863}
12864
12865bool isVPMULDQ(unsigned Opcode) {
12866 switch (Opcode) {
12867 case VPMULDQYrm:
12868 case VPMULDQYrr:
12869 case VPMULDQZ128rm:
12870 case VPMULDQZ128rmb:
12871 case VPMULDQZ128rmbk:
12872 case VPMULDQZ128rmbkz:
12873 case VPMULDQZ128rmk:
12874 case VPMULDQZ128rmkz:
12875 case VPMULDQZ128rr:
12876 case VPMULDQZ128rrk:
12877 case VPMULDQZ128rrkz:
12878 case VPMULDQZ256rm:
12879 case VPMULDQZ256rmb:
12880 case VPMULDQZ256rmbk:
12881 case VPMULDQZ256rmbkz:
12882 case VPMULDQZ256rmk:
12883 case VPMULDQZ256rmkz:
12884 case VPMULDQZ256rr:
12885 case VPMULDQZ256rrk:
12886 case VPMULDQZ256rrkz:
12887 case VPMULDQZrm:
12888 case VPMULDQZrmb:
12889 case VPMULDQZrmbk:
12890 case VPMULDQZrmbkz:
12891 case VPMULDQZrmk:
12892 case VPMULDQZrmkz:
12893 case VPMULDQZrr:
12894 case VPMULDQZrrk:
12895 case VPMULDQZrrkz:
12896 case VPMULDQrm:
12897 case VPMULDQrr:
12898 return true;
12899 }
12900 return false;
12901}
12902
12903bool isSHRX(unsigned Opcode) {
12904 switch (Opcode) {
12905 case SHRX32rm:
12906 case SHRX32rm_EVEX:
12907 case SHRX32rr:
12908 case SHRX32rr_EVEX:
12909 case SHRX64rm:
12910 case SHRX64rm_EVEX:
12911 case SHRX64rr:
12912 case SHRX64rr_EVEX:
12913 return true;
12914 }
12915 return false;
12916}
12917
12918bool isKXORQ(unsigned Opcode) {
12919 return Opcode == KXORQkk;
12920}
12921
12922bool isVGETEXPSD(unsigned Opcode) {
12923 switch (Opcode) {
12924 case VGETEXPSDZm:
12925 case VGETEXPSDZmk:
12926 case VGETEXPSDZmkz:
12927 case VGETEXPSDZr:
12928 case VGETEXPSDZrb:
12929 case VGETEXPSDZrbk:
12930 case VGETEXPSDZrbkz:
12931 case VGETEXPSDZrk:
12932 case VGETEXPSDZrkz:
12933 return true;
12934 }
12935 return false;
12936}
12937
12938bool isV4FNMADDPS(unsigned Opcode) {
12939 switch (Opcode) {
12940 case V4FNMADDPSrm:
12941 case V4FNMADDPSrmk:
12942 case V4FNMADDPSrmkz:
12943 return true;
12944 }
12945 return false;
12946}
12947
12948bool isVFNMSUB231SD(unsigned Opcode) {
12949 switch (Opcode) {
12950 case VFNMSUB231SDZm_Int:
12951 case VFNMSUB231SDZmk_Int:
12952 case VFNMSUB231SDZmkz_Int:
12953 case VFNMSUB231SDZr_Int:
12954 case VFNMSUB231SDZrb_Int:
12955 case VFNMSUB231SDZrbk_Int:
12956 case VFNMSUB231SDZrbkz_Int:
12957 case VFNMSUB231SDZrk_Int:
12958 case VFNMSUB231SDZrkz_Int:
12959 case VFNMSUB231SDm_Int:
12960 case VFNMSUB231SDr_Int:
12961 return true;
12962 }
12963 return false;
12964}
12965
12966bool isVPSHLD(unsigned Opcode) {
12967 switch (Opcode) {
12968 case VPSHLDmr:
12969 case VPSHLDrm:
12970 case VPSHLDrr:
12971 case VPSHLDrr_REV:
12972 return true;
12973 }
12974 return false;
12975}
12976
12977bool isPAVGB(unsigned Opcode) {
12978 switch (Opcode) {
12979 case MMX_PAVGBrm:
12980 case MMX_PAVGBrr:
12981 case PAVGBrm:
12982 case PAVGBrr:
12983 return true;
12984 }
12985 return false;
12986}
12987
12988bool isPMOVZXBD(unsigned Opcode) {
12989 switch (Opcode) {
12990 case PMOVZXBDrm:
12991 case PMOVZXBDrr:
12992 return true;
12993 }
12994 return false;
12995}
12996
12997bool isKORTESTW(unsigned Opcode) {
12998 return Opcode == KORTESTWkk;
12999}
13000
13001bool isVSHUFPS(unsigned Opcode) {
13002 switch (Opcode) {
13003 case VSHUFPSYrmi:
13004 case VSHUFPSYrri:
13005 case VSHUFPSZ128rmbi:
13006 case VSHUFPSZ128rmbik:
13007 case VSHUFPSZ128rmbikz:
13008 case VSHUFPSZ128rmi:
13009 case VSHUFPSZ128rmik:
13010 case VSHUFPSZ128rmikz:
13011 case VSHUFPSZ128rri:
13012 case VSHUFPSZ128rrik:
13013 case VSHUFPSZ128rrikz:
13014 case VSHUFPSZ256rmbi:
13015 case VSHUFPSZ256rmbik:
13016 case VSHUFPSZ256rmbikz:
13017 case VSHUFPSZ256rmi:
13018 case VSHUFPSZ256rmik:
13019 case VSHUFPSZ256rmikz:
13020 case VSHUFPSZ256rri:
13021 case VSHUFPSZ256rrik:
13022 case VSHUFPSZ256rrikz:
13023 case VSHUFPSZrmbi:
13024 case VSHUFPSZrmbik:
13025 case VSHUFPSZrmbikz:
13026 case VSHUFPSZrmi:
13027 case VSHUFPSZrmik:
13028 case VSHUFPSZrmikz:
13029 case VSHUFPSZrri:
13030 case VSHUFPSZrrik:
13031 case VSHUFPSZrrikz:
13032 case VSHUFPSrmi:
13033 case VSHUFPSrri:
13034 return true;
13035 }
13036 return false;
13037}
13038
13039bool isAESENCWIDE128KL(unsigned Opcode) {
13040 return Opcode == AESENCWIDE128KL;
13041}
13042
13043bool isVPXORD(unsigned Opcode) {
13044 switch (Opcode) {
13045 case VPXORDZ128rm:
13046 case VPXORDZ128rmb:
13047 case VPXORDZ128rmbk:
13048 case VPXORDZ128rmbkz:
13049 case VPXORDZ128rmk:
13050 case VPXORDZ128rmkz:
13051 case VPXORDZ128rr:
13052 case VPXORDZ128rrk:
13053 case VPXORDZ128rrkz:
13054 case VPXORDZ256rm:
13055 case VPXORDZ256rmb:
13056 case VPXORDZ256rmbk:
13057 case VPXORDZ256rmbkz:
13058 case VPXORDZ256rmk:
13059 case VPXORDZ256rmkz:
13060 case VPXORDZ256rr:
13061 case VPXORDZ256rrk:
13062 case VPXORDZ256rrkz:
13063 case VPXORDZrm:
13064 case VPXORDZrmb:
13065 case VPXORDZrmbk:
13066 case VPXORDZrmbkz:
13067 case VPXORDZrmk:
13068 case VPXORDZrmkz:
13069 case VPXORDZrr:
13070 case VPXORDZrrk:
13071 case VPXORDZrrkz:
13072 return true;
13073 }
13074 return false;
13075}
13076
13077bool isVPSHAW(unsigned Opcode) {
13078 switch (Opcode) {
13079 case VPSHAWmr:
13080 case VPSHAWrm:
13081 case VPSHAWrr:
13082 case VPSHAWrr_REV:
13083 return true;
13084 }
13085 return false;
13086}
13087
13088bool isVFMSUB132BF16(unsigned Opcode) {
13089 switch (Opcode) {
13090 case VFMSUB132BF16Z128m:
13091 case VFMSUB132BF16Z128mb:
13092 case VFMSUB132BF16Z128mbk:
13093 case VFMSUB132BF16Z128mbkz:
13094 case VFMSUB132BF16Z128mk:
13095 case VFMSUB132BF16Z128mkz:
13096 case VFMSUB132BF16Z128r:
13097 case VFMSUB132BF16Z128rk:
13098 case VFMSUB132BF16Z128rkz:
13099 case VFMSUB132BF16Z256m:
13100 case VFMSUB132BF16Z256mb:
13101 case VFMSUB132BF16Z256mbk:
13102 case VFMSUB132BF16Z256mbkz:
13103 case VFMSUB132BF16Z256mk:
13104 case VFMSUB132BF16Z256mkz:
13105 case VFMSUB132BF16Z256r:
13106 case VFMSUB132BF16Z256rk:
13107 case VFMSUB132BF16Z256rkz:
13108 case VFMSUB132BF16Zm:
13109 case VFMSUB132BF16Zmb:
13110 case VFMSUB132BF16Zmbk:
13111 case VFMSUB132BF16Zmbkz:
13112 case VFMSUB132BF16Zmk:
13113 case VFMSUB132BF16Zmkz:
13114 case VFMSUB132BF16Zr:
13115 case VFMSUB132BF16Zrk:
13116 case VFMSUB132BF16Zrkz:
13117 return true;
13118 }
13119 return false;
13120}
13121
13122bool isVPERMT2B(unsigned Opcode) {
13123 switch (Opcode) {
13124 case VPERMT2BZ128rm:
13125 case VPERMT2BZ128rmk:
13126 case VPERMT2BZ128rmkz:
13127 case VPERMT2BZ128rr:
13128 case VPERMT2BZ128rrk:
13129 case VPERMT2BZ128rrkz:
13130 case VPERMT2BZ256rm:
13131 case VPERMT2BZ256rmk:
13132 case VPERMT2BZ256rmkz:
13133 case VPERMT2BZ256rr:
13134 case VPERMT2BZ256rrk:
13135 case VPERMT2BZ256rrkz:
13136 case VPERMT2BZrm:
13137 case VPERMT2BZrmk:
13138 case VPERMT2BZrmkz:
13139 case VPERMT2BZrr:
13140 case VPERMT2BZrrk:
13141 case VPERMT2BZrrkz:
13142 return true;
13143 }
13144 return false;
13145}
13146
13147bool isVFMADD213PD(unsigned Opcode) {
13148 switch (Opcode) {
13149 case VFMADD213PDYm:
13150 case VFMADD213PDYr:
13151 case VFMADD213PDZ128m:
13152 case VFMADD213PDZ128mb:
13153 case VFMADD213PDZ128mbk:
13154 case VFMADD213PDZ128mbkz:
13155 case VFMADD213PDZ128mk:
13156 case VFMADD213PDZ128mkz:
13157 case VFMADD213PDZ128r:
13158 case VFMADD213PDZ128rk:
13159 case VFMADD213PDZ128rkz:
13160 case VFMADD213PDZ256m:
13161 case VFMADD213PDZ256mb:
13162 case VFMADD213PDZ256mbk:
13163 case VFMADD213PDZ256mbkz:
13164 case VFMADD213PDZ256mk:
13165 case VFMADD213PDZ256mkz:
13166 case VFMADD213PDZ256r:
13167 case VFMADD213PDZ256rk:
13168 case VFMADD213PDZ256rkz:
13169 case VFMADD213PDZm:
13170 case VFMADD213PDZmb:
13171 case VFMADD213PDZmbk:
13172 case VFMADD213PDZmbkz:
13173 case VFMADD213PDZmk:
13174 case VFMADD213PDZmkz:
13175 case VFMADD213PDZr:
13176 case VFMADD213PDZrb:
13177 case VFMADD213PDZrbk:
13178 case VFMADD213PDZrbkz:
13179 case VFMADD213PDZrk:
13180 case VFMADD213PDZrkz:
13181 case VFMADD213PDm:
13182 case VFMADD213PDr:
13183 return true;
13184 }
13185 return false;
13186}
13187
13188bool isVPGATHERQD(unsigned Opcode) {
13189 switch (Opcode) {
13190 case VPGATHERQDYrm:
13191 case VPGATHERQDZ128rm:
13192 case VPGATHERQDZ256rm:
13193 case VPGATHERQDZrm:
13194 case VPGATHERQDrm:
13195 return true;
13196 }
13197 return false;
13198}
13199
13200bool isVFNMSUB213BF16(unsigned Opcode) {
13201 switch (Opcode) {
13202 case VFNMSUB213BF16Z128m:
13203 case VFNMSUB213BF16Z128mb:
13204 case VFNMSUB213BF16Z128mbk:
13205 case VFNMSUB213BF16Z128mbkz:
13206 case VFNMSUB213BF16Z128mk:
13207 case VFNMSUB213BF16Z128mkz:
13208 case VFNMSUB213BF16Z128r:
13209 case VFNMSUB213BF16Z128rk:
13210 case VFNMSUB213BF16Z128rkz:
13211 case VFNMSUB213BF16Z256m:
13212 case VFNMSUB213BF16Z256mb:
13213 case VFNMSUB213BF16Z256mbk:
13214 case VFNMSUB213BF16Z256mbkz:
13215 case VFNMSUB213BF16Z256mk:
13216 case VFNMSUB213BF16Z256mkz:
13217 case VFNMSUB213BF16Z256r:
13218 case VFNMSUB213BF16Z256rk:
13219 case VFNMSUB213BF16Z256rkz:
13220 case VFNMSUB213BF16Zm:
13221 case VFNMSUB213BF16Zmb:
13222 case VFNMSUB213BF16Zmbk:
13223 case VFNMSUB213BF16Zmbkz:
13224 case VFNMSUB213BF16Zmk:
13225 case VFNMSUB213BF16Zmkz:
13226 case VFNMSUB213BF16Zr:
13227 case VFNMSUB213BF16Zrk:
13228 case VFNMSUB213BF16Zrkz:
13229 return true;
13230 }
13231 return false;
13232}
13233
13234bool isVCVTPS2IBS(unsigned Opcode) {
13235 switch (Opcode) {
13236 case VCVTPS2IBSZ128rm:
13237 case VCVTPS2IBSZ128rmb:
13238 case VCVTPS2IBSZ128rmbk:
13239 case VCVTPS2IBSZ128rmbkz:
13240 case VCVTPS2IBSZ128rmk:
13241 case VCVTPS2IBSZ128rmkz:
13242 case VCVTPS2IBSZ128rr:
13243 case VCVTPS2IBSZ128rrk:
13244 case VCVTPS2IBSZ128rrkz:
13245 case VCVTPS2IBSZ256rm:
13246 case VCVTPS2IBSZ256rmb:
13247 case VCVTPS2IBSZ256rmbk:
13248 case VCVTPS2IBSZ256rmbkz:
13249 case VCVTPS2IBSZ256rmk:
13250 case VCVTPS2IBSZ256rmkz:
13251 case VCVTPS2IBSZ256rr:
13252 case VCVTPS2IBSZ256rrk:
13253 case VCVTPS2IBSZ256rrkz:
13254 case VCVTPS2IBSZrm:
13255 case VCVTPS2IBSZrmb:
13256 case VCVTPS2IBSZrmbk:
13257 case VCVTPS2IBSZrmbkz:
13258 case VCVTPS2IBSZrmk:
13259 case VCVTPS2IBSZrmkz:
13260 case VCVTPS2IBSZrr:
13261 case VCVTPS2IBSZrrb:
13262 case VCVTPS2IBSZrrbk:
13263 case VCVTPS2IBSZrrbkz:
13264 case VCVTPS2IBSZrrk:
13265 case VCVTPS2IBSZrrkz:
13266 return true;
13267 }
13268 return false;
13269}
13270
13271bool isVPCMPGTW(unsigned Opcode) {
13272 switch (Opcode) {
13273 case VPCMPGTWYrm:
13274 case VPCMPGTWYrr:
13275 case VPCMPGTWZ128rm:
13276 case VPCMPGTWZ128rmk:
13277 case VPCMPGTWZ128rr:
13278 case VPCMPGTWZ128rrk:
13279 case VPCMPGTWZ256rm:
13280 case VPCMPGTWZ256rmk:
13281 case VPCMPGTWZ256rr:
13282 case VPCMPGTWZ256rrk:
13283 case VPCMPGTWZrm:
13284 case VPCMPGTWZrmk:
13285 case VPCMPGTWZrr:
13286 case VPCMPGTWZrrk:
13287 case VPCMPGTWrm:
13288 case VPCMPGTWrr:
13289 return true;
13290 }
13291 return false;
13292}
13293
13294bool isVMOVRSB(unsigned Opcode) {
13295 switch (Opcode) {
13296 case VMOVRSBZ128m:
13297 case VMOVRSBZ128mk:
13298 case VMOVRSBZ128mkz:
13299 case VMOVRSBZ256m:
13300 case VMOVRSBZ256mk:
13301 case VMOVRSBZ256mkz:
13302 case VMOVRSBZm:
13303 case VMOVRSBZmk:
13304 case VMOVRSBZmkz:
13305 return true;
13306 }
13307 return false;
13308}
13309
13310bool isVGETMANTSH(unsigned Opcode) {
13311 switch (Opcode) {
13312 case VGETMANTSHZrmi:
13313 case VGETMANTSHZrmik:
13314 case VGETMANTSHZrmikz:
13315 case VGETMANTSHZrri:
13316 case VGETMANTSHZrrib:
13317 case VGETMANTSHZrribk:
13318 case VGETMANTSHZrribkz:
13319 case VGETMANTSHZrrik:
13320 case VGETMANTSHZrrikz:
13321 return true;
13322 }
13323 return false;
13324}
13325
13326bool isVANDPS(unsigned Opcode) {
13327 switch (Opcode) {
13328 case VANDPSYrm:
13329 case VANDPSYrr:
13330 case VANDPSZ128rm:
13331 case VANDPSZ128rmb:
13332 case VANDPSZ128rmbk:
13333 case VANDPSZ128rmbkz:
13334 case VANDPSZ128rmk:
13335 case VANDPSZ128rmkz:
13336 case VANDPSZ128rr:
13337 case VANDPSZ128rrk:
13338 case VANDPSZ128rrkz:
13339 case VANDPSZ256rm:
13340 case VANDPSZ256rmb:
13341 case VANDPSZ256rmbk:
13342 case VANDPSZ256rmbkz:
13343 case VANDPSZ256rmk:
13344 case VANDPSZ256rmkz:
13345 case VANDPSZ256rr:
13346 case VANDPSZ256rrk:
13347 case VANDPSZ256rrkz:
13348 case VANDPSZrm:
13349 case VANDPSZrmb:
13350 case VANDPSZrmbk:
13351 case VANDPSZrmbkz:
13352 case VANDPSZrmk:
13353 case VANDPSZrmkz:
13354 case VANDPSZrr:
13355 case VANDPSZrrk:
13356 case VANDPSZrrkz:
13357 case VANDPSrm:
13358 case VANDPSrr:
13359 return true;
13360 }
13361 return false;
13362}
13363
13364bool isVDIVPS(unsigned Opcode) {
13365 switch (Opcode) {
13366 case VDIVPSYrm:
13367 case VDIVPSYrr:
13368 case VDIVPSZ128rm:
13369 case VDIVPSZ128rmb:
13370 case VDIVPSZ128rmbk:
13371 case VDIVPSZ128rmbkz:
13372 case VDIVPSZ128rmk:
13373 case VDIVPSZ128rmkz:
13374 case VDIVPSZ128rr:
13375 case VDIVPSZ128rrk:
13376 case VDIVPSZ128rrkz:
13377 case VDIVPSZ256rm:
13378 case VDIVPSZ256rmb:
13379 case VDIVPSZ256rmbk:
13380 case VDIVPSZ256rmbkz:
13381 case VDIVPSZ256rmk:
13382 case VDIVPSZ256rmkz:
13383 case VDIVPSZ256rr:
13384 case VDIVPSZ256rrk:
13385 case VDIVPSZ256rrkz:
13386 case VDIVPSZrm:
13387 case VDIVPSZrmb:
13388 case VDIVPSZrmbk:
13389 case VDIVPSZrmbkz:
13390 case VDIVPSZrmk:
13391 case VDIVPSZrmkz:
13392 case VDIVPSZrr:
13393 case VDIVPSZrrb:
13394 case VDIVPSZrrbk:
13395 case VDIVPSZrrbkz:
13396 case VDIVPSZrrk:
13397 case VDIVPSZrrkz:
13398 case VDIVPSrm:
13399 case VDIVPSrr:
13400 return true;
13401 }
13402 return false;
13403}
13404
13405bool isVANDNPS(unsigned Opcode) {
13406 switch (Opcode) {
13407 case VANDNPSYrm:
13408 case VANDNPSYrr:
13409 case VANDNPSZ128rm:
13410 case VANDNPSZ128rmb:
13411 case VANDNPSZ128rmbk:
13412 case VANDNPSZ128rmbkz:
13413 case VANDNPSZ128rmk:
13414 case VANDNPSZ128rmkz:
13415 case VANDNPSZ128rr:
13416 case VANDNPSZ128rrk:
13417 case VANDNPSZ128rrkz:
13418 case VANDNPSZ256rm:
13419 case VANDNPSZ256rmb:
13420 case VANDNPSZ256rmbk:
13421 case VANDNPSZ256rmbkz:
13422 case VANDNPSZ256rmk:
13423 case VANDNPSZ256rmkz:
13424 case VANDNPSZ256rr:
13425 case VANDNPSZ256rrk:
13426 case VANDNPSZ256rrkz:
13427 case VANDNPSZrm:
13428 case VANDNPSZrmb:
13429 case VANDNPSZrmbk:
13430 case VANDNPSZrmbkz:
13431 case VANDNPSZrmk:
13432 case VANDNPSZrmkz:
13433 case VANDNPSZrr:
13434 case VANDNPSZrrk:
13435 case VANDNPSZrrkz:
13436 case VANDNPSrm:
13437 case VANDNPSrr:
13438 return true;
13439 }
13440 return false;
13441}
13442
13443bool isVPBROADCASTW(unsigned Opcode) {
13444 switch (Opcode) {
13445 case VPBROADCASTWYrm:
13446 case VPBROADCASTWYrr:
13447 case VPBROADCASTWZ128rm:
13448 case VPBROADCASTWZ128rmk:
13449 case VPBROADCASTWZ128rmkz:
13450 case VPBROADCASTWZ128rr:
13451 case VPBROADCASTWZ128rrk:
13452 case VPBROADCASTWZ128rrkz:
13453 case VPBROADCASTWZ256rm:
13454 case VPBROADCASTWZ256rmk:
13455 case VPBROADCASTWZ256rmkz:
13456 case VPBROADCASTWZ256rr:
13457 case VPBROADCASTWZ256rrk:
13458 case VPBROADCASTWZ256rrkz:
13459 case VPBROADCASTWZrm:
13460 case VPBROADCASTWZrmk:
13461 case VPBROADCASTWZrmkz:
13462 case VPBROADCASTWZrr:
13463 case VPBROADCASTWZrrk:
13464 case VPBROADCASTWZrrkz:
13465 case VPBROADCASTWrZ128rr:
13466 case VPBROADCASTWrZ128rrk:
13467 case VPBROADCASTWrZ128rrkz:
13468 case VPBROADCASTWrZ256rr:
13469 case VPBROADCASTWrZ256rrk:
13470 case VPBROADCASTWrZ256rrkz:
13471 case VPBROADCASTWrZrr:
13472 case VPBROADCASTWrZrrk:
13473 case VPBROADCASTWrZrrkz:
13474 case VPBROADCASTWrm:
13475 case VPBROADCASTWrr:
13476 return true;
13477 }
13478 return false;
13479}
13480
13481bool isFLDL2T(unsigned Opcode) {
13482 return Opcode == FLDL2T;
13483}
13484
13485bool isVPERMB(unsigned Opcode) {
13486 switch (Opcode) {
13487 case VPERMBZ128rm:
13488 case VPERMBZ128rmk:
13489 case VPERMBZ128rmkz:
13490 case VPERMBZ128rr:
13491 case VPERMBZ128rrk:
13492 case VPERMBZ128rrkz:
13493 case VPERMBZ256rm:
13494 case VPERMBZ256rmk:
13495 case VPERMBZ256rmkz:
13496 case VPERMBZ256rr:
13497 case VPERMBZ256rrk:
13498 case VPERMBZ256rrkz:
13499 case VPERMBZrm:
13500 case VPERMBZrmk:
13501 case VPERMBZrmkz:
13502 case VPERMBZrr:
13503 case VPERMBZrrk:
13504 case VPERMBZrrkz:
13505 return true;
13506 }
13507 return false;
13508}
13509
13510bool isFCMOVNBE(unsigned Opcode) {
13511 return Opcode == CMOVNBE_F;
13512}
13513
13514bool isVCVTTPH2W(unsigned Opcode) {
13515 switch (Opcode) {
13516 case VCVTTPH2WZ128rm:
13517 case VCVTTPH2WZ128rmb:
13518 case VCVTTPH2WZ128rmbk:
13519 case VCVTTPH2WZ128rmbkz:
13520 case VCVTTPH2WZ128rmk:
13521 case VCVTTPH2WZ128rmkz:
13522 case VCVTTPH2WZ128rr:
13523 case VCVTTPH2WZ128rrk:
13524 case VCVTTPH2WZ128rrkz:
13525 case VCVTTPH2WZ256rm:
13526 case VCVTTPH2WZ256rmb:
13527 case VCVTTPH2WZ256rmbk:
13528 case VCVTTPH2WZ256rmbkz:
13529 case VCVTTPH2WZ256rmk:
13530 case VCVTTPH2WZ256rmkz:
13531 case VCVTTPH2WZ256rr:
13532 case VCVTTPH2WZ256rrk:
13533 case VCVTTPH2WZ256rrkz:
13534 case VCVTTPH2WZrm:
13535 case VCVTTPH2WZrmb:
13536 case VCVTTPH2WZrmbk:
13537 case VCVTTPH2WZrmbkz:
13538 case VCVTTPH2WZrmk:
13539 case VCVTTPH2WZrmkz:
13540 case VCVTTPH2WZrr:
13541 case VCVTTPH2WZrrb:
13542 case VCVTTPH2WZrrbk:
13543 case VCVTTPH2WZrrbkz:
13544 case VCVTTPH2WZrrk:
13545 case VCVTTPH2WZrrkz:
13546 return true;
13547 }
13548 return false;
13549}
13550
13551bool isPMOVZXBQ(unsigned Opcode) {
13552 switch (Opcode) {
13553 case PMOVZXBQrm:
13554 case PMOVZXBQrr:
13555 return true;
13556 }
13557 return false;
13558}
13559
13560bool isPF2ID(unsigned Opcode) {
13561 switch (Opcode) {
13562 case PF2IDrm:
13563 case PF2IDrr:
13564 return true;
13565 }
13566 return false;
13567}
13568
13569bool isVFNMADD132PD(unsigned Opcode) {
13570 switch (Opcode) {
13571 case VFNMADD132PDYm:
13572 case VFNMADD132PDYr:
13573 case VFNMADD132PDZ128m:
13574 case VFNMADD132PDZ128mb:
13575 case VFNMADD132PDZ128mbk:
13576 case VFNMADD132PDZ128mbkz:
13577 case VFNMADD132PDZ128mk:
13578 case VFNMADD132PDZ128mkz:
13579 case VFNMADD132PDZ128r:
13580 case VFNMADD132PDZ128rk:
13581 case VFNMADD132PDZ128rkz:
13582 case VFNMADD132PDZ256m:
13583 case VFNMADD132PDZ256mb:
13584 case VFNMADD132PDZ256mbk:
13585 case VFNMADD132PDZ256mbkz:
13586 case VFNMADD132PDZ256mk:
13587 case VFNMADD132PDZ256mkz:
13588 case VFNMADD132PDZ256r:
13589 case VFNMADD132PDZ256rk:
13590 case VFNMADD132PDZ256rkz:
13591 case VFNMADD132PDZm:
13592 case VFNMADD132PDZmb:
13593 case VFNMADD132PDZmbk:
13594 case VFNMADD132PDZmbkz:
13595 case VFNMADD132PDZmk:
13596 case VFNMADD132PDZmkz:
13597 case VFNMADD132PDZr:
13598 case VFNMADD132PDZrb:
13599 case VFNMADD132PDZrbk:
13600 case VFNMADD132PDZrbkz:
13601 case VFNMADD132PDZrk:
13602 case VFNMADD132PDZrkz:
13603 case VFNMADD132PDm:
13604 case VFNMADD132PDr:
13605 return true;
13606 }
13607 return false;
13608}
13609
13610bool isPMULHRSW(unsigned Opcode) {
13611 switch (Opcode) {
13612 case MMX_PMULHRSWrm:
13613 case MMX_PMULHRSWrr:
13614 case PMULHRSWrm:
13615 case PMULHRSWrr:
13616 return true;
13617 }
13618 return false;
13619}
13620
13621bool isKADDD(unsigned Opcode) {
13622 return Opcode == KADDDkk;
13623}
13624
13625bool isVFNMSUB132SH(unsigned Opcode) {
13626 switch (Opcode) {
13627 case VFNMSUB132SHZm_Int:
13628 case VFNMSUB132SHZmk_Int:
13629 case VFNMSUB132SHZmkz_Int:
13630 case VFNMSUB132SHZr_Int:
13631 case VFNMSUB132SHZrb_Int:
13632 case VFNMSUB132SHZrbk_Int:
13633 case VFNMSUB132SHZrbkz_Int:
13634 case VFNMSUB132SHZrk_Int:
13635 case VFNMSUB132SHZrkz_Int:
13636 return true;
13637 }
13638 return false;
13639}
13640
13641bool isUIRET(unsigned Opcode) {
13642 return Opcode == UIRET;
13643}
13644
13645bool isBSR(unsigned Opcode) {
13646 switch (Opcode) {
13647 case BSR16rm:
13648 case BSR16rr:
13649 case BSR32rm:
13650 case BSR32rr:
13651 case BSR64rm:
13652 case BSR64rr:
13653 return true;
13654 }
13655 return false;
13656}
13657
13658bool isPCMPEQQ(unsigned Opcode) {
13659 switch (Opcode) {
13660 case PCMPEQQrm:
13661 case PCMPEQQrr:
13662 return true;
13663 }
13664 return false;
13665}
13666
13667bool isCDQ(unsigned Opcode) {
13668 return Opcode == CDQ;
13669}
13670
13671bool isPMAXSW(unsigned Opcode) {
13672 switch (Opcode) {
13673 case MMX_PMAXSWrm:
13674 case MMX_PMAXSWrr:
13675 case PMAXSWrm:
13676 case PMAXSWrr:
13677 return true;
13678 }
13679 return false;
13680}
13681
13682bool isSIDTD(unsigned Opcode) {
13683 return Opcode == SIDT32m;
13684}
13685
13686bool isVCVTPS2PHX(unsigned Opcode) {
13687 switch (Opcode) {
13688 case VCVTPS2PHXZ128rm:
13689 case VCVTPS2PHXZ128rmb:
13690 case VCVTPS2PHXZ128rmbk:
13691 case VCVTPS2PHXZ128rmbkz:
13692 case VCVTPS2PHXZ128rmk:
13693 case VCVTPS2PHXZ128rmkz:
13694 case VCVTPS2PHXZ128rr:
13695 case VCVTPS2PHXZ128rrk:
13696 case VCVTPS2PHXZ128rrkz:
13697 case VCVTPS2PHXZ256rm:
13698 case VCVTPS2PHXZ256rmb:
13699 case VCVTPS2PHXZ256rmbk:
13700 case VCVTPS2PHXZ256rmbkz:
13701 case VCVTPS2PHXZ256rmk:
13702 case VCVTPS2PHXZ256rmkz:
13703 case VCVTPS2PHXZ256rr:
13704 case VCVTPS2PHXZ256rrk:
13705 case VCVTPS2PHXZ256rrkz:
13706 case VCVTPS2PHXZrm:
13707 case VCVTPS2PHXZrmb:
13708 case VCVTPS2PHXZrmbk:
13709 case VCVTPS2PHXZrmbkz:
13710 case VCVTPS2PHXZrmk:
13711 case VCVTPS2PHXZrmkz:
13712 case VCVTPS2PHXZrr:
13713 case VCVTPS2PHXZrrb:
13714 case VCVTPS2PHXZrrbk:
13715 case VCVTPS2PHXZrrbkz:
13716 case VCVTPS2PHXZrrk:
13717 case VCVTPS2PHXZrrkz:
13718 return true;
13719 }
13720 return false;
13721}
13722
13723bool isVPSLLVQ(unsigned Opcode) {
13724 switch (Opcode) {
13725 case VPSLLVQYrm:
13726 case VPSLLVQYrr:
13727 case VPSLLVQZ128rm:
13728 case VPSLLVQZ128rmb:
13729 case VPSLLVQZ128rmbk:
13730 case VPSLLVQZ128rmbkz:
13731 case VPSLLVQZ128rmk:
13732 case VPSLLVQZ128rmkz:
13733 case VPSLLVQZ128rr:
13734 case VPSLLVQZ128rrk:
13735 case VPSLLVQZ128rrkz:
13736 case VPSLLVQZ256rm:
13737 case VPSLLVQZ256rmb:
13738 case VPSLLVQZ256rmbk:
13739 case VPSLLVQZ256rmbkz:
13740 case VPSLLVQZ256rmk:
13741 case VPSLLVQZ256rmkz:
13742 case VPSLLVQZ256rr:
13743 case VPSLLVQZ256rrk:
13744 case VPSLLVQZ256rrkz:
13745 case VPSLLVQZrm:
13746 case VPSLLVQZrmb:
13747 case VPSLLVQZrmbk:
13748 case VPSLLVQZrmbkz:
13749 case VPSLLVQZrmk:
13750 case VPSLLVQZrmkz:
13751 case VPSLLVQZrr:
13752 case VPSLLVQZrrk:
13753 case VPSLLVQZrrkz:
13754 case VPSLLVQrm:
13755 case VPSLLVQrr:
13756 return true;
13757 }
13758 return false;
13759}
13760
13761bool isMOVQ(unsigned Opcode) {
13762 switch (Opcode) {
13763 case MMX_MOVD64from64mr:
13764 case MMX_MOVD64from64rr:
13765 case MMX_MOVD64to64rm:
13766 case MMX_MOVD64to64rr:
13767 case MMX_MOVQ64mr:
13768 case MMX_MOVQ64rm:
13769 case MMX_MOVQ64rr:
13770 case MMX_MOVQ64rr_REV:
13771 case MOV64toPQIrm:
13772 case MOV64toPQIrr:
13773 case MOVPQI2QImr:
13774 case MOVPQI2QIrr:
13775 case MOVPQIto64mr:
13776 case MOVPQIto64rr:
13777 case MOVQI2PQIrm:
13778 case MOVZPQILo2PQIrr:
13779 return true;
13780 }
13781 return false;
13782}
13783
13784bool isVCMPBF16(unsigned Opcode) {
13785 switch (Opcode) {
13786 case VCMPBF16Z128rmbi:
13787 case VCMPBF16Z128rmbik:
13788 case VCMPBF16Z128rmi:
13789 case VCMPBF16Z128rmik:
13790 case VCMPBF16Z128rri:
13791 case VCMPBF16Z128rrik:
13792 case VCMPBF16Z256rmbi:
13793 case VCMPBF16Z256rmbik:
13794 case VCMPBF16Z256rmi:
13795 case VCMPBF16Z256rmik:
13796 case VCMPBF16Z256rri:
13797 case VCMPBF16Z256rrik:
13798 case VCMPBF16Zrmbi:
13799 case VCMPBF16Zrmbik:
13800 case VCMPBF16Zrmi:
13801 case VCMPBF16Zrmik:
13802 case VCMPBF16Zrri:
13803 case VCMPBF16Zrrik:
13804 return true;
13805 }
13806 return false;
13807}
13808
13809bool isPREFETCH(unsigned Opcode) {
13810 return Opcode == PREFETCH;
13811}
13812
13813bool isCLRSSBSY(unsigned Opcode) {
13814 return Opcode == CLRSSBSY;
13815}
13816
13817bool isTCVTROWPS2PHL(unsigned Opcode) {
13818 switch (Opcode) {
13819 case TCVTROWPS2PHLrte:
13820 case TCVTROWPS2PHLrti:
13821 return true;
13822 }
13823 return false;
13824}
13825
13826bool isPSHUFW(unsigned Opcode) {
13827 switch (Opcode) {
13828 case MMX_PSHUFWmi:
13829 case MMX_PSHUFWri:
13830 return true;
13831 }
13832 return false;
13833}
13834
13835bool isVPDPWSUDS(unsigned Opcode) {
13836 switch (Opcode) {
13837 case VPDPWSUDSYrm:
13838 case VPDPWSUDSYrr:
13839 case VPDPWSUDSZ128rm:
13840 case VPDPWSUDSZ128rmb:
13841 case VPDPWSUDSZ128rmbk:
13842 case VPDPWSUDSZ128rmbkz:
13843 case VPDPWSUDSZ128rmk:
13844 case VPDPWSUDSZ128rmkz:
13845 case VPDPWSUDSZ128rr:
13846 case VPDPWSUDSZ128rrk:
13847 case VPDPWSUDSZ128rrkz:
13848 case VPDPWSUDSZ256rm:
13849 case VPDPWSUDSZ256rmb:
13850 case VPDPWSUDSZ256rmbk:
13851 case VPDPWSUDSZ256rmbkz:
13852 case VPDPWSUDSZ256rmk:
13853 case VPDPWSUDSZ256rmkz:
13854 case VPDPWSUDSZ256rr:
13855 case VPDPWSUDSZ256rrk:
13856 case VPDPWSUDSZ256rrkz:
13857 case VPDPWSUDSZrm:
13858 case VPDPWSUDSZrmb:
13859 case VPDPWSUDSZrmbk:
13860 case VPDPWSUDSZrmbkz:
13861 case VPDPWSUDSZrmk:
13862 case VPDPWSUDSZrmkz:
13863 case VPDPWSUDSZrr:
13864 case VPDPWSUDSZrrk:
13865 case VPDPWSUDSZrrkz:
13866 case VPDPWSUDSrm:
13867 case VPDPWSUDSrr:
13868 return true;
13869 }
13870 return false;
13871}
13872
13873bool isVPMOVSXBQ(unsigned Opcode) {
13874 switch (Opcode) {
13875 case VPMOVSXBQYrm:
13876 case VPMOVSXBQYrr:
13877 case VPMOVSXBQZ128rm:
13878 case VPMOVSXBQZ128rmk:
13879 case VPMOVSXBQZ128rmkz:
13880 case VPMOVSXBQZ128rr:
13881 case VPMOVSXBQZ128rrk:
13882 case VPMOVSXBQZ128rrkz:
13883 case VPMOVSXBQZ256rm:
13884 case VPMOVSXBQZ256rmk:
13885 case VPMOVSXBQZ256rmkz:
13886 case VPMOVSXBQZ256rr:
13887 case VPMOVSXBQZ256rrk:
13888 case VPMOVSXBQZ256rrkz:
13889 case VPMOVSXBQZrm:
13890 case VPMOVSXBQZrmk:
13891 case VPMOVSXBQZrmkz:
13892 case VPMOVSXBQZrr:
13893 case VPMOVSXBQZrrk:
13894 case VPMOVSXBQZrrkz:
13895 case VPMOVSXBQrm:
13896 case VPMOVSXBQrr:
13897 return true;
13898 }
13899 return false;
13900}
13901
13902bool isFICOMP(unsigned Opcode) {
13903 switch (Opcode) {
13904 case FICOMP16m:
13905 case FICOMP32m:
13906 return true;
13907 }
13908 return false;
13909}
13910
13911bool isVLDMXCSR(unsigned Opcode) {
13912 return Opcode == VLDMXCSR;
13913}
13914
13915bool isVPSUBUSW(unsigned Opcode) {
13916 switch (Opcode) {
13917 case VPSUBUSWYrm:
13918 case VPSUBUSWYrr:
13919 case VPSUBUSWZ128rm:
13920 case VPSUBUSWZ128rmk:
13921 case VPSUBUSWZ128rmkz:
13922 case VPSUBUSWZ128rr:
13923 case VPSUBUSWZ128rrk:
13924 case VPSUBUSWZ128rrkz:
13925 case VPSUBUSWZ256rm:
13926 case VPSUBUSWZ256rmk:
13927 case VPSUBUSWZ256rmkz:
13928 case VPSUBUSWZ256rr:
13929 case VPSUBUSWZ256rrk:
13930 case VPSUBUSWZ256rrkz:
13931 case VPSUBUSWZrm:
13932 case VPSUBUSWZrmk:
13933 case VPSUBUSWZrmkz:
13934 case VPSUBUSWZrr:
13935 case VPSUBUSWZrrk:
13936 case VPSUBUSWZrrkz:
13937 case VPSUBUSWrm:
13938 case VPSUBUSWrr:
13939 return true;
13940 }
13941 return false;
13942}
13943
13944bool isVFNMSUB132SS(unsigned Opcode) {
13945 switch (Opcode) {
13946 case VFNMSUB132SSZm_Int:
13947 case VFNMSUB132SSZmk_Int:
13948 case VFNMSUB132SSZmkz_Int:
13949 case VFNMSUB132SSZr_Int:
13950 case VFNMSUB132SSZrb_Int:
13951 case VFNMSUB132SSZrbk_Int:
13952 case VFNMSUB132SSZrbkz_Int:
13953 case VFNMSUB132SSZrk_Int:
13954 case VFNMSUB132SSZrkz_Int:
13955 case VFNMSUB132SSm_Int:
13956 case VFNMSUB132SSr_Int:
13957 return true;
13958 }
13959 return false;
13960}
13961
13962bool isRETF(unsigned Opcode) {
13963 switch (Opcode) {
13964 case LRET16:
13965 case LRET32:
13966 case LRETI16:
13967 case LRETI32:
13968 return true;
13969 }
13970 return false;
13971}
13972
13973bool isKMOVQ(unsigned Opcode) {
13974 switch (Opcode) {
13975 case KMOVQkk:
13976 case KMOVQkk_EVEX:
13977 case KMOVQkm:
13978 case KMOVQkm_EVEX:
13979 case KMOVQkr:
13980 case KMOVQkr_EVEX:
13981 case KMOVQmk:
13982 case KMOVQmk_EVEX:
13983 case KMOVQrk:
13984 case KMOVQrk_EVEX:
13985 return true;
13986 }
13987 return false;
13988}
13989
13990bool isVPADDUSW(unsigned Opcode) {
13991 switch (Opcode) {
13992 case VPADDUSWYrm:
13993 case VPADDUSWYrr:
13994 case VPADDUSWZ128rm:
13995 case VPADDUSWZ128rmk:
13996 case VPADDUSWZ128rmkz:
13997 case VPADDUSWZ128rr:
13998 case VPADDUSWZ128rrk:
13999 case VPADDUSWZ128rrkz:
14000 case VPADDUSWZ256rm:
14001 case VPADDUSWZ256rmk:
14002 case VPADDUSWZ256rmkz:
14003 case VPADDUSWZ256rr:
14004 case VPADDUSWZ256rrk:
14005 case VPADDUSWZ256rrkz:
14006 case VPADDUSWZrm:
14007 case VPADDUSWZrmk:
14008 case VPADDUSWZrmkz:
14009 case VPADDUSWZrr:
14010 case VPADDUSWZrrk:
14011 case VPADDUSWZrrkz:
14012 case VPADDUSWrm:
14013 case VPADDUSWrr:
14014 return true;
14015 }
14016 return false;
14017}
14018
14019bool isPACKSSDW(unsigned Opcode) {
14020 switch (Opcode) {
14021 case MMX_PACKSSDWrm:
14022 case MMX_PACKSSDWrr:
14023 case PACKSSDWrm:
14024 case PACKSSDWrr:
14025 return true;
14026 }
14027 return false;
14028}
14029
14030bool isUMONITOR(unsigned Opcode) {
14031 switch (Opcode) {
14032 case UMONITOR16:
14033 case UMONITOR32:
14034 case UMONITOR64:
14035 return true;
14036 }
14037 return false;
14038}
14039
14040bool isENQCMDS(unsigned Opcode) {
14041 switch (Opcode) {
14042 case ENQCMDS16:
14043 case ENQCMDS32:
14044 case ENQCMDS32_EVEX:
14045 case ENQCMDS64:
14046 case ENQCMDS64_EVEX:
14047 return true;
14048 }
14049 return false;
14050}
14051
14052bool isVCOMXSD(unsigned Opcode) {
14053 switch (Opcode) {
14054 case VCOMXSDZrm_Int:
14055 case VCOMXSDZrr_Int:
14056 case VCOMXSDZrrb_Int:
14057 return true;
14058 }
14059 return false;
14060}
14061
14062bool isVPMAXSQ(unsigned Opcode) {
14063 switch (Opcode) {
14064 case VPMAXSQZ128rm:
14065 case VPMAXSQZ128rmb:
14066 case VPMAXSQZ128rmbk:
14067 case VPMAXSQZ128rmbkz:
14068 case VPMAXSQZ128rmk:
14069 case VPMAXSQZ128rmkz:
14070 case VPMAXSQZ128rr:
14071 case VPMAXSQZ128rrk:
14072 case VPMAXSQZ128rrkz:
14073 case VPMAXSQZ256rm:
14074 case VPMAXSQZ256rmb:
14075 case VPMAXSQZ256rmbk:
14076 case VPMAXSQZ256rmbkz:
14077 case VPMAXSQZ256rmk:
14078 case VPMAXSQZ256rmkz:
14079 case VPMAXSQZ256rr:
14080 case VPMAXSQZ256rrk:
14081 case VPMAXSQZ256rrkz:
14082 case VPMAXSQZrm:
14083 case VPMAXSQZrmb:
14084 case VPMAXSQZrmbk:
14085 case VPMAXSQZrmbkz:
14086 case VPMAXSQZrmk:
14087 case VPMAXSQZrmkz:
14088 case VPMAXSQZrr:
14089 case VPMAXSQZrrk:
14090 case VPMAXSQZrrkz:
14091 return true;
14092 }
14093 return false;
14094}
14095
14096bool isVFMSUB213BF16(unsigned Opcode) {
14097 switch (Opcode) {
14098 case VFMSUB213BF16Z128m:
14099 case VFMSUB213BF16Z128mb:
14100 case VFMSUB213BF16Z128mbk:
14101 case VFMSUB213BF16Z128mbkz:
14102 case VFMSUB213BF16Z128mk:
14103 case VFMSUB213BF16Z128mkz:
14104 case VFMSUB213BF16Z128r:
14105 case VFMSUB213BF16Z128rk:
14106 case VFMSUB213BF16Z128rkz:
14107 case VFMSUB213BF16Z256m:
14108 case VFMSUB213BF16Z256mb:
14109 case VFMSUB213BF16Z256mbk:
14110 case VFMSUB213BF16Z256mbkz:
14111 case VFMSUB213BF16Z256mk:
14112 case VFMSUB213BF16Z256mkz:
14113 case VFMSUB213BF16Z256r:
14114 case VFMSUB213BF16Z256rk:
14115 case VFMSUB213BF16Z256rkz:
14116 case VFMSUB213BF16Zm:
14117 case VFMSUB213BF16Zmb:
14118 case VFMSUB213BF16Zmbk:
14119 case VFMSUB213BF16Zmbkz:
14120 case VFMSUB213BF16Zmk:
14121 case VFMSUB213BF16Zmkz:
14122 case VFMSUB213BF16Zr:
14123 case VFMSUB213BF16Zrk:
14124 case VFMSUB213BF16Zrkz:
14125 return true;
14126 }
14127 return false;
14128}
14129
14130bool isVPERMT2Q(unsigned Opcode) {
14131 switch (Opcode) {
14132 case VPERMT2QZ128rm:
14133 case VPERMT2QZ128rmb:
14134 case VPERMT2QZ128rmbk:
14135 case VPERMT2QZ128rmbkz:
14136 case VPERMT2QZ128rmk:
14137 case VPERMT2QZ128rmkz:
14138 case VPERMT2QZ128rr:
14139 case VPERMT2QZ128rrk:
14140 case VPERMT2QZ128rrkz:
14141 case VPERMT2QZ256rm:
14142 case VPERMT2QZ256rmb:
14143 case VPERMT2QZ256rmbk:
14144 case VPERMT2QZ256rmbkz:
14145 case VPERMT2QZ256rmk:
14146 case VPERMT2QZ256rmkz:
14147 case VPERMT2QZ256rr:
14148 case VPERMT2QZ256rrk:
14149 case VPERMT2QZ256rrkz:
14150 case VPERMT2QZrm:
14151 case VPERMT2QZrmb:
14152 case VPERMT2QZrmbk:
14153 case VPERMT2QZrmbkz:
14154 case VPERMT2QZrmk:
14155 case VPERMT2QZrmkz:
14156 case VPERMT2QZrr:
14157 case VPERMT2QZrrk:
14158 case VPERMT2QZrrkz:
14159 return true;
14160 }
14161 return false;
14162}
14163
14164bool isFDECSTP(unsigned Opcode) {
14165 return Opcode == FDECSTP;
14166}
14167
14168bool isVPTESTMQ(unsigned Opcode) {
14169 switch (Opcode) {
14170 case VPTESTMQZ128rm:
14171 case VPTESTMQZ128rmb:
14172 case VPTESTMQZ128rmbk:
14173 case VPTESTMQZ128rmk:
14174 case VPTESTMQZ128rr:
14175 case VPTESTMQZ128rrk:
14176 case VPTESTMQZ256rm:
14177 case VPTESTMQZ256rmb:
14178 case VPTESTMQZ256rmbk:
14179 case VPTESTMQZ256rmk:
14180 case VPTESTMQZ256rr:
14181 case VPTESTMQZ256rrk:
14182 case VPTESTMQZrm:
14183 case VPTESTMQZrmb:
14184 case VPTESTMQZrmbk:
14185 case VPTESTMQZrmk:
14186 case VPTESTMQZrr:
14187 case VPTESTMQZrrk:
14188 return true;
14189 }
14190 return false;
14191}
14192
14193bool isVRCP14PD(unsigned Opcode) {
14194 switch (Opcode) {
14195 case VRCP14PDZ128m:
14196 case VRCP14PDZ128mb:
14197 case VRCP14PDZ128mbk:
14198 case VRCP14PDZ128mbkz:
14199 case VRCP14PDZ128mk:
14200 case VRCP14PDZ128mkz:
14201 case VRCP14PDZ128r:
14202 case VRCP14PDZ128rk:
14203 case VRCP14PDZ128rkz:
14204 case VRCP14PDZ256m:
14205 case VRCP14PDZ256mb:
14206 case VRCP14PDZ256mbk:
14207 case VRCP14PDZ256mbkz:
14208 case VRCP14PDZ256mk:
14209 case VRCP14PDZ256mkz:
14210 case VRCP14PDZ256r:
14211 case VRCP14PDZ256rk:
14212 case VRCP14PDZ256rkz:
14213 case VRCP14PDZm:
14214 case VRCP14PDZmb:
14215 case VRCP14PDZmbk:
14216 case VRCP14PDZmbkz:
14217 case VRCP14PDZmk:
14218 case VRCP14PDZmkz:
14219 case VRCP14PDZr:
14220 case VRCP14PDZrk:
14221 case VRCP14PDZrkz:
14222 return true;
14223 }
14224 return false;
14225}
14226
14227bool isARPL(unsigned Opcode) {
14228 switch (Opcode) {
14229 case ARPL16mr:
14230 case ARPL16rr:
14231 return true;
14232 }
14233 return false;
14234}
14235
14236bool isVFMSUB213SD(unsigned Opcode) {
14237 switch (Opcode) {
14238 case VFMSUB213SDZm_Int:
14239 case VFMSUB213SDZmk_Int:
14240 case VFMSUB213SDZmkz_Int:
14241 case VFMSUB213SDZr_Int:
14242 case VFMSUB213SDZrb_Int:
14243 case VFMSUB213SDZrbk_Int:
14244 case VFMSUB213SDZrbkz_Int:
14245 case VFMSUB213SDZrk_Int:
14246 case VFMSUB213SDZrkz_Int:
14247 case VFMSUB213SDm_Int:
14248 case VFMSUB213SDr_Int:
14249 return true;
14250 }
14251 return false;
14252}
14253
14254bool isJMPABS(unsigned Opcode) {
14255 return Opcode == JMPABS64i;
14256}
14257
14258bool isVUNPCKHPS(unsigned Opcode) {
14259 switch (Opcode) {
14260 case VUNPCKHPSYrm:
14261 case VUNPCKHPSYrr:
14262 case VUNPCKHPSZ128rm:
14263 case VUNPCKHPSZ128rmb:
14264 case VUNPCKHPSZ128rmbk:
14265 case VUNPCKHPSZ128rmbkz:
14266 case VUNPCKHPSZ128rmk:
14267 case VUNPCKHPSZ128rmkz:
14268 case VUNPCKHPSZ128rr:
14269 case VUNPCKHPSZ128rrk:
14270 case VUNPCKHPSZ128rrkz:
14271 case VUNPCKHPSZ256rm:
14272 case VUNPCKHPSZ256rmb:
14273 case VUNPCKHPSZ256rmbk:
14274 case VUNPCKHPSZ256rmbkz:
14275 case VUNPCKHPSZ256rmk:
14276 case VUNPCKHPSZ256rmkz:
14277 case VUNPCKHPSZ256rr:
14278 case VUNPCKHPSZ256rrk:
14279 case VUNPCKHPSZ256rrkz:
14280 case VUNPCKHPSZrm:
14281 case VUNPCKHPSZrmb:
14282 case VUNPCKHPSZrmbk:
14283 case VUNPCKHPSZrmbkz:
14284 case VUNPCKHPSZrmk:
14285 case VUNPCKHPSZrmkz:
14286 case VUNPCKHPSZrr:
14287 case VUNPCKHPSZrrk:
14288 case VUNPCKHPSZrrkz:
14289 case VUNPCKHPSrm:
14290 case VUNPCKHPSrr:
14291 return true;
14292 }
14293 return false;
14294}
14295
14296bool isVFNMADDSS(unsigned Opcode) {
14297 switch (Opcode) {
14298 case VFNMADDSS4mr:
14299 case VFNMADDSS4rm:
14300 case VFNMADDSS4rr:
14301 case VFNMADDSS4rr_REV:
14302 return true;
14303 }
14304 return false;
14305}
14306
14307bool isSIDT(unsigned Opcode) {
14308 return Opcode == SIDT64m;
14309}
14310
14311bool isVPCMPGTB(unsigned Opcode) {
14312 switch (Opcode) {
14313 case VPCMPGTBYrm:
14314 case VPCMPGTBYrr:
14315 case VPCMPGTBZ128rm:
14316 case VPCMPGTBZ128rmk:
14317 case VPCMPGTBZ128rr:
14318 case VPCMPGTBZ128rrk:
14319 case VPCMPGTBZ256rm:
14320 case VPCMPGTBZ256rmk:
14321 case VPCMPGTBZ256rr:
14322 case VPCMPGTBZ256rrk:
14323 case VPCMPGTBZrm:
14324 case VPCMPGTBZrmk:
14325 case VPCMPGTBZrr:
14326 case VPCMPGTBZrrk:
14327 case VPCMPGTBrm:
14328 case VPCMPGTBrr:
14329 return true;
14330 }
14331 return false;
14332}
14333
14334bool isVPRORD(unsigned Opcode) {
14335 switch (Opcode) {
14336 case VPRORDZ128mbi:
14337 case VPRORDZ128mbik:
14338 case VPRORDZ128mbikz:
14339 case VPRORDZ128mi:
14340 case VPRORDZ128mik:
14341 case VPRORDZ128mikz:
14342 case VPRORDZ128ri:
14343 case VPRORDZ128rik:
14344 case VPRORDZ128rikz:
14345 case VPRORDZ256mbi:
14346 case VPRORDZ256mbik:
14347 case VPRORDZ256mbikz:
14348 case VPRORDZ256mi:
14349 case VPRORDZ256mik:
14350 case VPRORDZ256mikz:
14351 case VPRORDZ256ri:
14352 case VPRORDZ256rik:
14353 case VPRORDZ256rikz:
14354 case VPRORDZmbi:
14355 case VPRORDZmbik:
14356 case VPRORDZmbikz:
14357 case VPRORDZmi:
14358 case VPRORDZmik:
14359 case VPRORDZmikz:
14360 case VPRORDZri:
14361 case VPRORDZrik:
14362 case VPRORDZrikz:
14363 return true;
14364 }
14365 return false;
14366}
14367
14368bool isVSUBSS(unsigned Opcode) {
14369 switch (Opcode) {
14370 case VSUBSSZrm_Int:
14371 case VSUBSSZrmk_Int:
14372 case VSUBSSZrmkz_Int:
14373 case VSUBSSZrr_Int:
14374 case VSUBSSZrrb_Int:
14375 case VSUBSSZrrbk_Int:
14376 case VSUBSSZrrbkz_Int:
14377 case VSUBSSZrrk_Int:
14378 case VSUBSSZrrkz_Int:
14379 case VSUBSSrm_Int:
14380 case VSUBSSrr_Int:
14381 return true;
14382 }
14383 return false;
14384}
14385
14386bool isPUSHFQ(unsigned Opcode) {
14387 return Opcode == PUSHF64;
14388}
14389
14390bool isVCVTHF82PH(unsigned Opcode) {
14391 switch (Opcode) {
14392 case VCVTHF82PHZ128rm:
14393 case VCVTHF82PHZ128rmk:
14394 case VCVTHF82PHZ128rmkz:
14395 case VCVTHF82PHZ128rr:
14396 case VCVTHF82PHZ128rrk:
14397 case VCVTHF82PHZ128rrkz:
14398 case VCVTHF82PHZ256rm:
14399 case VCVTHF82PHZ256rmk:
14400 case VCVTHF82PHZ256rmkz:
14401 case VCVTHF82PHZ256rr:
14402 case VCVTHF82PHZ256rrk:
14403 case VCVTHF82PHZ256rrkz:
14404 case VCVTHF82PHZrm:
14405 case VCVTHF82PHZrmk:
14406 case VCVTHF82PHZrmkz:
14407 case VCVTHF82PHZrr:
14408 case VCVTHF82PHZrrk:
14409 case VCVTHF82PHZrrkz:
14410 return true;
14411 }
14412 return false;
14413}
14414
14415bool isVPCLMULQDQ(unsigned Opcode) {
14416 switch (Opcode) {
14417 case VPCLMULQDQYrmi:
14418 case VPCLMULQDQYrri:
14419 case VPCLMULQDQZ128rmi:
14420 case VPCLMULQDQZ128rri:
14421 case VPCLMULQDQZ256rmi:
14422 case VPCLMULQDQZ256rri:
14423 case VPCLMULQDQZrmi:
14424 case VPCLMULQDQZrri:
14425 case VPCLMULQDQrmi:
14426 case VPCLMULQDQrri:
14427 return true;
14428 }
14429 return false;
14430}
14431
14432bool isVPADDUSB(unsigned Opcode) {
14433 switch (Opcode) {
14434 case VPADDUSBYrm:
14435 case VPADDUSBYrr:
14436 case VPADDUSBZ128rm:
14437 case VPADDUSBZ128rmk:
14438 case VPADDUSBZ128rmkz:
14439 case VPADDUSBZ128rr:
14440 case VPADDUSBZ128rrk:
14441 case VPADDUSBZ128rrkz:
14442 case VPADDUSBZ256rm:
14443 case VPADDUSBZ256rmk:
14444 case VPADDUSBZ256rmkz:
14445 case VPADDUSBZ256rr:
14446 case VPADDUSBZ256rrk:
14447 case VPADDUSBZ256rrkz:
14448 case VPADDUSBZrm:
14449 case VPADDUSBZrmk:
14450 case VPADDUSBZrmkz:
14451 case VPADDUSBZrr:
14452 case VPADDUSBZrrk:
14453 case VPADDUSBZrrkz:
14454 case VPADDUSBrm:
14455 case VPADDUSBrr:
14456 return true;
14457 }
14458 return false;
14459}
14460
14461bool isVPCMPD(unsigned Opcode) {
14462 switch (Opcode) {
14463 case VPCMPDZ128rmbi:
14464 case VPCMPDZ128rmbik:
14465 case VPCMPDZ128rmi:
14466 case VPCMPDZ128rmik:
14467 case VPCMPDZ128rri:
14468 case VPCMPDZ128rrik:
14469 case VPCMPDZ256rmbi:
14470 case VPCMPDZ256rmbik:
14471 case VPCMPDZ256rmi:
14472 case VPCMPDZ256rmik:
14473 case VPCMPDZ256rri:
14474 case VPCMPDZ256rrik:
14475 case VPCMPDZrmbi:
14476 case VPCMPDZrmbik:
14477 case VPCMPDZrmi:
14478 case VPCMPDZrmik:
14479 case VPCMPDZrri:
14480 case VPCMPDZrrik:
14481 return true;
14482 }
14483 return false;
14484}
14485
14486bool isMOVSD(unsigned Opcode) {
14487 switch (Opcode) {
14488 case MOVSDmr:
14489 case MOVSDrm:
14490 case MOVSDrr:
14491 case MOVSDrr_REV:
14492 case MOVSL:
14493 return true;
14494 }
14495 return false;
14496}
14497
14498bool isPSUBUSW(unsigned Opcode) {
14499 switch (Opcode) {
14500 case MMX_PSUBUSWrm:
14501 case MMX_PSUBUSWrr:
14502 case PSUBUSWrm:
14503 case PSUBUSWrr:
14504 return true;
14505 }
14506 return false;
14507}
14508
14509bool isVFMSUBADD132PS(unsigned Opcode) {
14510 switch (Opcode) {
14511 case VFMSUBADD132PSYm:
14512 case VFMSUBADD132PSYr:
14513 case VFMSUBADD132PSZ128m:
14514 case VFMSUBADD132PSZ128mb:
14515 case VFMSUBADD132PSZ128mbk:
14516 case VFMSUBADD132PSZ128mbkz:
14517 case VFMSUBADD132PSZ128mk:
14518 case VFMSUBADD132PSZ128mkz:
14519 case VFMSUBADD132PSZ128r:
14520 case VFMSUBADD132PSZ128rk:
14521 case VFMSUBADD132PSZ128rkz:
14522 case VFMSUBADD132PSZ256m:
14523 case VFMSUBADD132PSZ256mb:
14524 case VFMSUBADD132PSZ256mbk:
14525 case VFMSUBADD132PSZ256mbkz:
14526 case VFMSUBADD132PSZ256mk:
14527 case VFMSUBADD132PSZ256mkz:
14528 case VFMSUBADD132PSZ256r:
14529 case VFMSUBADD132PSZ256rk:
14530 case VFMSUBADD132PSZ256rkz:
14531 case VFMSUBADD132PSZm:
14532 case VFMSUBADD132PSZmb:
14533 case VFMSUBADD132PSZmbk:
14534 case VFMSUBADD132PSZmbkz:
14535 case VFMSUBADD132PSZmk:
14536 case VFMSUBADD132PSZmkz:
14537 case VFMSUBADD132PSZr:
14538 case VFMSUBADD132PSZrb:
14539 case VFMSUBADD132PSZrbk:
14540 case VFMSUBADD132PSZrbkz:
14541 case VFMSUBADD132PSZrk:
14542 case VFMSUBADD132PSZrkz:
14543 case VFMSUBADD132PSm:
14544 case VFMSUBADD132PSr:
14545 return true;
14546 }
14547 return false;
14548}
14549
14550bool isMOVMSKPS(unsigned Opcode) {
14551 return Opcode == MOVMSKPSrr;
14552}
14553
14554bool isVFIXUPIMMSS(unsigned Opcode) {
14555 switch (Opcode) {
14556 case VFIXUPIMMSSZrmi:
14557 case VFIXUPIMMSSZrmik:
14558 case VFIXUPIMMSSZrmikz:
14559 case VFIXUPIMMSSZrri:
14560 case VFIXUPIMMSSZrrib:
14561 case VFIXUPIMMSSZrribk:
14562 case VFIXUPIMMSSZrribkz:
14563 case VFIXUPIMMSSZrrik:
14564 case VFIXUPIMMSSZrrikz:
14565 return true;
14566 }
14567 return false;
14568}
14569
14570bool isMFENCE(unsigned Opcode) {
14571 return Opcode == MFENCE;
14572}
14573
14574bool isFTST(unsigned Opcode) {
14575 return Opcode == TST_F;
14576}
14577
14578bool isVPMADDWD(unsigned Opcode) {
14579 switch (Opcode) {
14580 case VPMADDWDYrm:
14581 case VPMADDWDYrr:
14582 case VPMADDWDZ128rm:
14583 case VPMADDWDZ128rmk:
14584 case VPMADDWDZ128rmkz:
14585 case VPMADDWDZ128rr:
14586 case VPMADDWDZ128rrk:
14587 case VPMADDWDZ128rrkz:
14588 case VPMADDWDZ256rm:
14589 case VPMADDWDZ256rmk:
14590 case VPMADDWDZ256rmkz:
14591 case VPMADDWDZ256rr:
14592 case VPMADDWDZ256rrk:
14593 case VPMADDWDZ256rrkz:
14594 case VPMADDWDZrm:
14595 case VPMADDWDZrmk:
14596 case VPMADDWDZrmkz:
14597 case VPMADDWDZrr:
14598 case VPMADDWDZrrk:
14599 case VPMADDWDZrrkz:
14600 case VPMADDWDrm:
14601 case VPMADDWDrr:
14602 return true;
14603 }
14604 return false;
14605}
14606
14607bool isPOP(unsigned Opcode) {
14608 switch (Opcode) {
14609 case POP16r:
14610 case POP16rmm:
14611 case POP16rmr:
14612 case POP32r:
14613 case POP32rmm:
14614 case POP32rmr:
14615 case POP64r:
14616 case POP64rmm:
14617 case POP64rmr:
14618 case POPDS16:
14619 case POPDS32:
14620 case POPES16:
14621 case POPES32:
14622 case POPFS16:
14623 case POPFS32:
14624 case POPFS64:
14625 case POPGS16:
14626 case POPGS32:
14627 case POPGS64:
14628 case POPSS16:
14629 case POPSS32:
14630 return true;
14631 }
14632 return false;
14633}
14634
14635bool isPSUBW(unsigned Opcode) {
14636 switch (Opcode) {
14637 case MMX_PSUBWrm:
14638 case MMX_PSUBWrr:
14639 case PSUBWrm:
14640 case PSUBWrr:
14641 return true;
14642 }
14643 return false;
14644}
14645
14646bool isBSWAP(unsigned Opcode) {
14647 switch (Opcode) {
14648 case BSWAP16r_BAD:
14649 case BSWAP32r:
14650 case BSWAP64r:
14651 return true;
14652 }
14653 return false;
14654}
14655
14656bool isPFMIN(unsigned Opcode) {
14657 switch (Opcode) {
14658 case PFMINrm:
14659 case PFMINrr:
14660 return true;
14661 }
14662 return false;
14663}
14664
14665bool isVFPCLASSPD(unsigned Opcode) {
14666 switch (Opcode) {
14667 case VFPCLASSPDZ128mbi:
14668 case VFPCLASSPDZ128mbik:
14669 case VFPCLASSPDZ128mi:
14670 case VFPCLASSPDZ128mik:
14671 case VFPCLASSPDZ128ri:
14672 case VFPCLASSPDZ128rik:
14673 case VFPCLASSPDZ256mbi:
14674 case VFPCLASSPDZ256mbik:
14675 case VFPCLASSPDZ256mi:
14676 case VFPCLASSPDZ256mik:
14677 case VFPCLASSPDZ256ri:
14678 case VFPCLASSPDZ256rik:
14679 case VFPCLASSPDZmbi:
14680 case VFPCLASSPDZmbik:
14681 case VFPCLASSPDZmi:
14682 case VFPCLASSPDZmik:
14683 case VFPCLASSPDZri:
14684 case VFPCLASSPDZrik:
14685 return true;
14686 }
14687 return false;
14688}
14689
14690bool isVPSHRDVD(unsigned Opcode) {
14691 switch (Opcode) {
14692 case VPSHRDVDZ128m:
14693 case VPSHRDVDZ128mb:
14694 case VPSHRDVDZ128mbk:
14695 case VPSHRDVDZ128mbkz:
14696 case VPSHRDVDZ128mk:
14697 case VPSHRDVDZ128mkz:
14698 case VPSHRDVDZ128r:
14699 case VPSHRDVDZ128rk:
14700 case VPSHRDVDZ128rkz:
14701 case VPSHRDVDZ256m:
14702 case VPSHRDVDZ256mb:
14703 case VPSHRDVDZ256mbk:
14704 case VPSHRDVDZ256mbkz:
14705 case VPSHRDVDZ256mk:
14706 case VPSHRDVDZ256mkz:
14707 case VPSHRDVDZ256r:
14708 case VPSHRDVDZ256rk:
14709 case VPSHRDVDZ256rkz:
14710 case VPSHRDVDZm:
14711 case VPSHRDVDZmb:
14712 case VPSHRDVDZmbk:
14713 case VPSHRDVDZmbkz:
14714 case VPSHRDVDZmk:
14715 case VPSHRDVDZmkz:
14716 case VPSHRDVDZr:
14717 case VPSHRDVDZrk:
14718 case VPSHRDVDZrkz:
14719 return true;
14720 }
14721 return false;
14722}
14723
14724bool isPADDW(unsigned Opcode) {
14725 switch (Opcode) {
14726 case MMX_PADDWrm:
14727 case MMX_PADDWrr:
14728 case PADDWrm:
14729 case PADDWrr:
14730 return true;
14731 }
14732 return false;
14733}
14734
14735bool isCVTSI2SD(unsigned Opcode) {
14736 switch (Opcode) {
14737 case CVTSI2SDrm_Int:
14738 case CVTSI2SDrr_Int:
14739 case CVTSI642SDrm_Int:
14740 case CVTSI642SDrr_Int:
14741 return true;
14742 }
14743 return false;
14744}
14745
14746bool isENQCMD(unsigned Opcode) {
14747 switch (Opcode) {
14748 case ENQCMD16:
14749 case ENQCMD32:
14750 case ENQCMD32_EVEX:
14751 case ENQCMD64:
14752 case ENQCMD64_EVEX:
14753 return true;
14754 }
14755 return false;
14756}
14757
14758bool isXSHA1(unsigned Opcode) {
14759 return Opcode == XSHA1;
14760}
14761
14762bool isVFNMADD132SD(unsigned Opcode) {
14763 switch (Opcode) {
14764 case VFNMADD132SDZm_Int:
14765 case VFNMADD132SDZmk_Int:
14766 case VFNMADD132SDZmkz_Int:
14767 case VFNMADD132SDZr_Int:
14768 case VFNMADD132SDZrb_Int:
14769 case VFNMADD132SDZrbk_Int:
14770 case VFNMADD132SDZrbkz_Int:
14771 case VFNMADD132SDZrk_Int:
14772 case VFNMADD132SDZrkz_Int:
14773 case VFNMADD132SDm_Int:
14774 case VFNMADD132SDr_Int:
14775 return true;
14776 }
14777 return false;
14778}
14779
14780bool isMOVZX(unsigned Opcode) {
14781 switch (Opcode) {
14782 case MOVZX16rm16:
14783 case MOVZX16rm8:
14784 case MOVZX16rr16:
14785 case MOVZX16rr8:
14786 case MOVZX32rm16:
14787 case MOVZX32rm8:
14788 case MOVZX32rr16:
14789 case MOVZX32rr8:
14790 case MOVZX64rm16:
14791 case MOVZX64rm8:
14792 case MOVZX64rr16:
14793 case MOVZX64rr8:
14794 return true;
14795 }
14796 return false;
14797}
14798
14799bool isVFIXUPIMMSD(unsigned Opcode) {
14800 switch (Opcode) {
14801 case VFIXUPIMMSDZrmi:
14802 case VFIXUPIMMSDZrmik:
14803 case VFIXUPIMMSDZrmikz:
14804 case VFIXUPIMMSDZrri:
14805 case VFIXUPIMMSDZrrib:
14806 case VFIXUPIMMSDZrribk:
14807 case VFIXUPIMMSDZrribkz:
14808 case VFIXUPIMMSDZrrik:
14809 case VFIXUPIMMSDZrrikz:
14810 return true;
14811 }
14812 return false;
14813}
14814
14815bool isINVD(unsigned Opcode) {
14816 return Opcode == INVD;
14817}
14818
14819bool isVFIXUPIMMPS(unsigned Opcode) {
14820 switch (Opcode) {
14821 case VFIXUPIMMPSZ128rmbi:
14822 case VFIXUPIMMPSZ128rmbik:
14823 case VFIXUPIMMPSZ128rmbikz:
14824 case VFIXUPIMMPSZ128rmi:
14825 case VFIXUPIMMPSZ128rmik:
14826 case VFIXUPIMMPSZ128rmikz:
14827 case VFIXUPIMMPSZ128rri:
14828 case VFIXUPIMMPSZ128rrik:
14829 case VFIXUPIMMPSZ128rrikz:
14830 case VFIXUPIMMPSZ256rmbi:
14831 case VFIXUPIMMPSZ256rmbik:
14832 case VFIXUPIMMPSZ256rmbikz:
14833 case VFIXUPIMMPSZ256rmi:
14834 case VFIXUPIMMPSZ256rmik:
14835 case VFIXUPIMMPSZ256rmikz:
14836 case VFIXUPIMMPSZ256rri:
14837 case VFIXUPIMMPSZ256rrik:
14838 case VFIXUPIMMPSZ256rrikz:
14839 case VFIXUPIMMPSZrmbi:
14840 case VFIXUPIMMPSZrmbik:
14841 case VFIXUPIMMPSZrmbikz:
14842 case VFIXUPIMMPSZrmi:
14843 case VFIXUPIMMPSZrmik:
14844 case VFIXUPIMMPSZrmikz:
14845 case VFIXUPIMMPSZrri:
14846 case VFIXUPIMMPSZrrib:
14847 case VFIXUPIMMPSZrribk:
14848 case VFIXUPIMMPSZrribkz:
14849 case VFIXUPIMMPSZrrik:
14850 case VFIXUPIMMPSZrrikz:
14851 return true;
14852 }
14853 return false;
14854}
14855
14856bool isMOVDQU(unsigned Opcode) {
14857 switch (Opcode) {
14858 case MOVDQUmr:
14859 case MOVDQUrm:
14860 case MOVDQUrr:
14861 case MOVDQUrr_REV:
14862 return true;
14863 }
14864 return false;
14865}
14866
14867bool isVFPCLASSPS(unsigned Opcode) {
14868 switch (Opcode) {
14869 case VFPCLASSPSZ128mbi:
14870 case VFPCLASSPSZ128mbik:
14871 case VFPCLASSPSZ128mi:
14872 case VFPCLASSPSZ128mik:
14873 case VFPCLASSPSZ128ri:
14874 case VFPCLASSPSZ128rik:
14875 case VFPCLASSPSZ256mbi:
14876 case VFPCLASSPSZ256mbik:
14877 case VFPCLASSPSZ256mi:
14878 case VFPCLASSPSZ256mik:
14879 case VFPCLASSPSZ256ri:
14880 case VFPCLASSPSZ256rik:
14881 case VFPCLASSPSZmbi:
14882 case VFPCLASSPSZmbik:
14883 case VFPCLASSPSZmi:
14884 case VFPCLASSPSZmik:
14885 case VFPCLASSPSZri:
14886 case VFPCLASSPSZrik:
14887 return true;
14888 }
14889 return false;
14890}
14891
14892bool isMOVSQ(unsigned Opcode) {
14893 return Opcode == MOVSQ;
14894}
14895
14896bool isAESDECWIDE128KL(unsigned Opcode) {
14897 return Opcode == AESDECWIDE128KL;
14898}
14899
14900bool isROUNDSS(unsigned Opcode) {
14901 switch (Opcode) {
14902 case ROUNDSSmi_Int:
14903 case ROUNDSSri_Int:
14904 return true;
14905 }
14906 return false;
14907}
14908
14909bool isVPERMILPS(unsigned Opcode) {
14910 switch (Opcode) {
14911 case VPERMILPSYmi:
14912 case VPERMILPSYri:
14913 case VPERMILPSYrm:
14914 case VPERMILPSYrr:
14915 case VPERMILPSZ128mbi:
14916 case VPERMILPSZ128mbik:
14917 case VPERMILPSZ128mbikz:
14918 case VPERMILPSZ128mi:
14919 case VPERMILPSZ128mik:
14920 case VPERMILPSZ128mikz:
14921 case VPERMILPSZ128ri:
14922 case VPERMILPSZ128rik:
14923 case VPERMILPSZ128rikz:
14924 case VPERMILPSZ128rm:
14925 case VPERMILPSZ128rmb:
14926 case VPERMILPSZ128rmbk:
14927 case VPERMILPSZ128rmbkz:
14928 case VPERMILPSZ128rmk:
14929 case VPERMILPSZ128rmkz:
14930 case VPERMILPSZ128rr:
14931 case VPERMILPSZ128rrk:
14932 case VPERMILPSZ128rrkz:
14933 case VPERMILPSZ256mbi:
14934 case VPERMILPSZ256mbik:
14935 case VPERMILPSZ256mbikz:
14936 case VPERMILPSZ256mi:
14937 case VPERMILPSZ256mik:
14938 case VPERMILPSZ256mikz:
14939 case VPERMILPSZ256ri:
14940 case VPERMILPSZ256rik:
14941 case VPERMILPSZ256rikz:
14942 case VPERMILPSZ256rm:
14943 case VPERMILPSZ256rmb:
14944 case VPERMILPSZ256rmbk:
14945 case VPERMILPSZ256rmbkz:
14946 case VPERMILPSZ256rmk:
14947 case VPERMILPSZ256rmkz:
14948 case VPERMILPSZ256rr:
14949 case VPERMILPSZ256rrk:
14950 case VPERMILPSZ256rrkz:
14951 case VPERMILPSZmbi:
14952 case VPERMILPSZmbik:
14953 case VPERMILPSZmbikz:
14954 case VPERMILPSZmi:
14955 case VPERMILPSZmik:
14956 case VPERMILPSZmikz:
14957 case VPERMILPSZri:
14958 case VPERMILPSZrik:
14959 case VPERMILPSZrikz:
14960 case VPERMILPSZrm:
14961 case VPERMILPSZrmb:
14962 case VPERMILPSZrmbk:
14963 case VPERMILPSZrmbkz:
14964 case VPERMILPSZrmk:
14965 case VPERMILPSZrmkz:
14966 case VPERMILPSZrr:
14967 case VPERMILPSZrrk:
14968 case VPERMILPSZrrkz:
14969 case VPERMILPSmi:
14970 case VPERMILPSri:
14971 case VPERMILPSrm:
14972 case VPERMILPSrr:
14973 return true;
14974 }
14975 return false;
14976}
14977
14978bool isVPMOVW2M(unsigned Opcode) {
14979 switch (Opcode) {
14980 case VPMOVW2MZ128kr:
14981 case VPMOVW2MZ256kr:
14982 case VPMOVW2MZkr:
14983 return true;
14984 }
14985 return false;
14986}
14987
14988bool isVMULSD(unsigned Opcode) {
14989 switch (Opcode) {
14990 case VMULSDZrm_Int:
14991 case VMULSDZrmk_Int:
14992 case VMULSDZrmkz_Int:
14993 case VMULSDZrr_Int:
14994 case VMULSDZrrb_Int:
14995 case VMULSDZrrbk_Int:
14996 case VMULSDZrrbkz_Int:
14997 case VMULSDZrrk_Int:
14998 case VMULSDZrrkz_Int:
14999 case VMULSDrm_Int:
15000 case VMULSDrr_Int:
15001 return true;
15002 }
15003 return false;
15004}
15005
15006bool isVPERMI2W(unsigned Opcode) {
15007 switch (Opcode) {
15008 case VPERMI2WZ128rm:
15009 case VPERMI2WZ128rmk:
15010 case VPERMI2WZ128rmkz:
15011 case VPERMI2WZ128rr:
15012 case VPERMI2WZ128rrk:
15013 case VPERMI2WZ128rrkz:
15014 case VPERMI2WZ256rm:
15015 case VPERMI2WZ256rmk:
15016 case VPERMI2WZ256rmkz:
15017 case VPERMI2WZ256rr:
15018 case VPERMI2WZ256rrk:
15019 case VPERMI2WZ256rrkz:
15020 case VPERMI2WZrm:
15021 case VPERMI2WZrmk:
15022 case VPERMI2WZrmkz:
15023 case VPERMI2WZrr:
15024 case VPERMI2WZrrk:
15025 case VPERMI2WZrrkz:
15026 return true;
15027 }
15028 return false;
15029}
15030
15031bool isVPSHUFB(unsigned Opcode) {
15032 switch (Opcode) {
15033 case VPSHUFBYrm:
15034 case VPSHUFBYrr:
15035 case VPSHUFBZ128rm:
15036 case VPSHUFBZ128rmk:
15037 case VPSHUFBZ128rmkz:
15038 case VPSHUFBZ128rr:
15039 case VPSHUFBZ128rrk:
15040 case VPSHUFBZ128rrkz:
15041 case VPSHUFBZ256rm:
15042 case VPSHUFBZ256rmk:
15043 case VPSHUFBZ256rmkz:
15044 case VPSHUFBZ256rr:
15045 case VPSHUFBZ256rrk:
15046 case VPSHUFBZ256rrkz:
15047 case VPSHUFBZrm:
15048 case VPSHUFBZrmk:
15049 case VPSHUFBZrmkz:
15050 case VPSHUFBZrr:
15051 case VPSHUFBZrrk:
15052 case VPSHUFBZrrkz:
15053 case VPSHUFBrm:
15054 case VPSHUFBrr:
15055 return true;
15056 }
15057 return false;
15058}
15059
15060bool isFST(unsigned Opcode) {
15061 switch (Opcode) {
15062 case ST_F32m:
15063 case ST_F64m:
15064 case ST_Frr:
15065 return true;
15066 }
15067 return false;
15068}
15069
15070bool isVPHSUBW(unsigned Opcode) {
15071 switch (Opcode) {
15072 case VPHSUBWYrm:
15073 case VPHSUBWYrr:
15074 case VPHSUBWrm:
15075 case VPHSUBWrr:
15076 return true;
15077 }
15078 return false;
15079}
15080
15081bool isVREDUCESS(unsigned Opcode) {
15082 switch (Opcode) {
15083 case VREDUCESSZrmi:
15084 case VREDUCESSZrmik:
15085 case VREDUCESSZrmikz:
15086 case VREDUCESSZrri:
15087 case VREDUCESSZrrib:
15088 case VREDUCESSZrribk:
15089 case VREDUCESSZrribkz:
15090 case VREDUCESSZrrik:
15091 case VREDUCESSZrrikz:
15092 return true;
15093 }
15094 return false;
15095}
15096
15097bool isFRNDINT(unsigned Opcode) {
15098 return Opcode == FRNDINT;
15099}
15100
15101bool isSHR(unsigned Opcode) {
15102 switch (Opcode) {
15103 case SHR16m1:
15104 case SHR16m1_EVEX:
15105 case SHR16m1_ND:
15106 case SHR16m1_NF:
15107 case SHR16m1_NF_ND:
15108 case SHR16mCL:
15109 case SHR16mCL_EVEX:
15110 case SHR16mCL_ND:
15111 case SHR16mCL_NF:
15112 case SHR16mCL_NF_ND:
15113 case SHR16mi:
15114 case SHR16mi_EVEX:
15115 case SHR16mi_ND:
15116 case SHR16mi_NF:
15117 case SHR16mi_NF_ND:
15118 case SHR16r1:
15119 case SHR16r1_EVEX:
15120 case SHR16r1_ND:
15121 case SHR16r1_NF:
15122 case SHR16r1_NF_ND:
15123 case SHR16rCL:
15124 case SHR16rCL_EVEX:
15125 case SHR16rCL_ND:
15126 case SHR16rCL_NF:
15127 case SHR16rCL_NF_ND:
15128 case SHR16ri:
15129 case SHR16ri_EVEX:
15130 case SHR16ri_ND:
15131 case SHR16ri_NF:
15132 case SHR16ri_NF_ND:
15133 case SHR32m1:
15134 case SHR32m1_EVEX:
15135 case SHR32m1_ND:
15136 case SHR32m1_NF:
15137 case SHR32m1_NF_ND:
15138 case SHR32mCL:
15139 case SHR32mCL_EVEX:
15140 case SHR32mCL_ND:
15141 case SHR32mCL_NF:
15142 case SHR32mCL_NF_ND:
15143 case SHR32mi:
15144 case SHR32mi_EVEX:
15145 case SHR32mi_ND:
15146 case SHR32mi_NF:
15147 case SHR32mi_NF_ND:
15148 case SHR32r1:
15149 case SHR32r1_EVEX:
15150 case SHR32r1_ND:
15151 case SHR32r1_NF:
15152 case SHR32r1_NF_ND:
15153 case SHR32rCL:
15154 case SHR32rCL_EVEX:
15155 case SHR32rCL_ND:
15156 case SHR32rCL_NF:
15157 case SHR32rCL_NF_ND:
15158 case SHR32ri:
15159 case SHR32ri_EVEX:
15160 case SHR32ri_ND:
15161 case SHR32ri_NF:
15162 case SHR32ri_NF_ND:
15163 case SHR64m1:
15164 case SHR64m1_EVEX:
15165 case SHR64m1_ND:
15166 case SHR64m1_NF:
15167 case SHR64m1_NF_ND:
15168 case SHR64mCL:
15169 case SHR64mCL_EVEX:
15170 case SHR64mCL_ND:
15171 case SHR64mCL_NF:
15172 case SHR64mCL_NF_ND:
15173 case SHR64mi:
15174 case SHR64mi_EVEX:
15175 case SHR64mi_ND:
15176 case SHR64mi_NF:
15177 case SHR64mi_NF_ND:
15178 case SHR64r1:
15179 case SHR64r1_EVEX:
15180 case SHR64r1_ND:
15181 case SHR64r1_NF:
15182 case SHR64r1_NF_ND:
15183 case SHR64rCL:
15184 case SHR64rCL_EVEX:
15185 case SHR64rCL_ND:
15186 case SHR64rCL_NF:
15187 case SHR64rCL_NF_ND:
15188 case SHR64ri:
15189 case SHR64ri_EVEX:
15190 case SHR64ri_ND:
15191 case SHR64ri_NF:
15192 case SHR64ri_NF_ND:
15193 case SHR8m1:
15194 case SHR8m1_EVEX:
15195 case SHR8m1_ND:
15196 case SHR8m1_NF:
15197 case SHR8m1_NF_ND:
15198 case SHR8mCL:
15199 case SHR8mCL_EVEX:
15200 case SHR8mCL_ND:
15201 case SHR8mCL_NF:
15202 case SHR8mCL_NF_ND:
15203 case SHR8mi:
15204 case SHR8mi_EVEX:
15205 case SHR8mi_ND:
15206 case SHR8mi_NF:
15207 case SHR8mi_NF_ND:
15208 case SHR8r1:
15209 case SHR8r1_EVEX:
15210 case SHR8r1_ND:
15211 case SHR8r1_NF:
15212 case SHR8r1_NF_ND:
15213 case SHR8rCL:
15214 case SHR8rCL_EVEX:
15215 case SHR8rCL_ND:
15216 case SHR8rCL_NF:
15217 case SHR8rCL_NF_ND:
15218 case SHR8ri:
15219 case SHR8ri_EVEX:
15220 case SHR8ri_ND:
15221 case SHR8ri_NF:
15222 case SHR8ri_NF_ND:
15223 return true;
15224 }
15225 return false;
15226}
15227
15228bool isLOOPNE(unsigned Opcode) {
15229 return Opcode == LOOPNE;
15230}
15231
15232bool isVCVTTPH2UQQ(unsigned Opcode) {
15233 switch (Opcode) {
15234 case VCVTTPH2UQQZ128rm:
15235 case VCVTTPH2UQQZ128rmb:
15236 case VCVTTPH2UQQZ128rmbk:
15237 case VCVTTPH2UQQZ128rmbkz:
15238 case VCVTTPH2UQQZ128rmk:
15239 case VCVTTPH2UQQZ128rmkz:
15240 case VCVTTPH2UQQZ128rr:
15241 case VCVTTPH2UQQZ128rrk:
15242 case VCVTTPH2UQQZ128rrkz:
15243 case VCVTTPH2UQQZ256rm:
15244 case VCVTTPH2UQQZ256rmb:
15245 case VCVTTPH2UQQZ256rmbk:
15246 case VCVTTPH2UQQZ256rmbkz:
15247 case VCVTTPH2UQQZ256rmk:
15248 case VCVTTPH2UQQZ256rmkz:
15249 case VCVTTPH2UQQZ256rr:
15250 case VCVTTPH2UQQZ256rrk:
15251 case VCVTTPH2UQQZ256rrkz:
15252 case VCVTTPH2UQQZrm:
15253 case VCVTTPH2UQQZrmb:
15254 case VCVTTPH2UQQZrmbk:
15255 case VCVTTPH2UQQZrmbkz:
15256 case VCVTTPH2UQQZrmk:
15257 case VCVTTPH2UQQZrmkz:
15258 case VCVTTPH2UQQZrr:
15259 case VCVTTPH2UQQZrrb:
15260 case VCVTTPH2UQQZrrbk:
15261 case VCVTTPH2UQQZrrbkz:
15262 case VCVTTPH2UQQZrrk:
15263 case VCVTTPH2UQQZrrkz:
15264 return true;
15265 }
15266 return false;
15267}
15268
15269bool isSHA1NEXTE(unsigned Opcode) {
15270 switch (Opcode) {
15271 case SHA1NEXTErm:
15272 case SHA1NEXTErr:
15273 return true;
15274 }
15275 return false;
15276}
15277
15278bool isVFMADD132SD(unsigned Opcode) {
15279 switch (Opcode) {
15280 case VFMADD132SDZm_Int:
15281 case VFMADD132SDZmk_Int:
15282 case VFMADD132SDZmkz_Int:
15283 case VFMADD132SDZr_Int:
15284 case VFMADD132SDZrb_Int:
15285 case VFMADD132SDZrbk_Int:
15286 case VFMADD132SDZrbkz_Int:
15287 case VFMADD132SDZrk_Int:
15288 case VFMADD132SDZrkz_Int:
15289 case VFMADD132SDm_Int:
15290 case VFMADD132SDr_Int:
15291 return true;
15292 }
15293 return false;
15294}
15295
15296bool isPSRAW(unsigned Opcode) {
15297 switch (Opcode) {
15298 case MMX_PSRAWri:
15299 case MMX_PSRAWrm:
15300 case MMX_PSRAWrr:
15301 case PSRAWri:
15302 case PSRAWrm:
15303 case PSRAWrr:
15304 return true;
15305 }
15306 return false;
15307}
15308
15309bool isVPBROADCASTQ(unsigned Opcode) {
15310 switch (Opcode) {
15311 case VPBROADCASTQYrm:
15312 case VPBROADCASTQYrr:
15313 case VPBROADCASTQZ128rm:
15314 case VPBROADCASTQZ128rmk:
15315 case VPBROADCASTQZ128rmkz:
15316 case VPBROADCASTQZ128rr:
15317 case VPBROADCASTQZ128rrk:
15318 case VPBROADCASTQZ128rrkz:
15319 case VPBROADCASTQZ256rm:
15320 case VPBROADCASTQZ256rmk:
15321 case VPBROADCASTQZ256rmkz:
15322 case VPBROADCASTQZ256rr:
15323 case VPBROADCASTQZ256rrk:
15324 case VPBROADCASTQZ256rrkz:
15325 case VPBROADCASTQZrm:
15326 case VPBROADCASTQZrmk:
15327 case VPBROADCASTQZrmkz:
15328 case VPBROADCASTQZrr:
15329 case VPBROADCASTQZrrk:
15330 case VPBROADCASTQZrrkz:
15331 case VPBROADCASTQrZ128rr:
15332 case VPBROADCASTQrZ128rrk:
15333 case VPBROADCASTQrZ128rrkz:
15334 case VPBROADCASTQrZ256rr:
15335 case VPBROADCASTQrZ256rrk:
15336 case VPBROADCASTQrZ256rrkz:
15337 case VPBROADCASTQrZrr:
15338 case VPBROADCASTQrZrrk:
15339 case VPBROADCASTQrZrrkz:
15340 case VPBROADCASTQrm:
15341 case VPBROADCASTQrr:
15342 return true;
15343 }
15344 return false;
15345}
15346
15347bool isCLC(unsigned Opcode) {
15348 return Opcode == CLC;
15349}
15350
15351bool isPOPAW(unsigned Opcode) {
15352 return Opcode == POPA16;
15353}
15354
15355bool isTCMMIMFP16PS(unsigned Opcode) {
15356 return Opcode == TCMMIMFP16PS;
15357}
15358
15359bool isVCVTTPS2UQQ(unsigned Opcode) {
15360 switch (Opcode) {
15361 case VCVTTPS2UQQZ128rm:
15362 case VCVTTPS2UQQZ128rmb:
15363 case VCVTTPS2UQQZ128rmbk:
15364 case VCVTTPS2UQQZ128rmbkz:
15365 case VCVTTPS2UQQZ128rmk:
15366 case VCVTTPS2UQQZ128rmkz:
15367 case VCVTTPS2UQQZ128rr:
15368 case VCVTTPS2UQQZ128rrk:
15369 case VCVTTPS2UQQZ128rrkz:
15370 case VCVTTPS2UQQZ256rm:
15371 case VCVTTPS2UQQZ256rmb:
15372 case VCVTTPS2UQQZ256rmbk:
15373 case VCVTTPS2UQQZ256rmbkz:
15374 case VCVTTPS2UQQZ256rmk:
15375 case VCVTTPS2UQQZ256rmkz:
15376 case VCVTTPS2UQQZ256rr:
15377 case VCVTTPS2UQQZ256rrk:
15378 case VCVTTPS2UQQZ256rrkz:
15379 case VCVTTPS2UQQZrm:
15380 case VCVTTPS2UQQZrmb:
15381 case VCVTTPS2UQQZrmbk:
15382 case VCVTTPS2UQQZrmbkz:
15383 case VCVTTPS2UQQZrmk:
15384 case VCVTTPS2UQQZrmkz:
15385 case VCVTTPS2UQQZrr:
15386 case VCVTTPS2UQQZrrb:
15387 case VCVTTPS2UQQZrrbk:
15388 case VCVTTPS2UQQZrrbkz:
15389 case VCVTTPS2UQQZrrk:
15390 case VCVTTPS2UQQZrrkz:
15391 return true;
15392 }
15393 return false;
15394}
15395
15396bool isVCVTQQ2PH(unsigned Opcode) {
15397 switch (Opcode) {
15398 case VCVTQQ2PHZ128rm:
15399 case VCVTQQ2PHZ128rmb:
15400 case VCVTQQ2PHZ128rmbk:
15401 case VCVTQQ2PHZ128rmbkz:
15402 case VCVTQQ2PHZ128rmk:
15403 case VCVTQQ2PHZ128rmkz:
15404 case VCVTQQ2PHZ128rr:
15405 case VCVTQQ2PHZ128rrk:
15406 case VCVTQQ2PHZ128rrkz:
15407 case VCVTQQ2PHZ256rm:
15408 case VCVTQQ2PHZ256rmb:
15409 case VCVTQQ2PHZ256rmbk:
15410 case VCVTQQ2PHZ256rmbkz:
15411 case VCVTQQ2PHZ256rmk:
15412 case VCVTQQ2PHZ256rmkz:
15413 case VCVTQQ2PHZ256rr:
15414 case VCVTQQ2PHZ256rrk:
15415 case VCVTQQ2PHZ256rrkz:
15416 case VCVTQQ2PHZrm:
15417 case VCVTQQ2PHZrmb:
15418 case VCVTQQ2PHZrmbk:
15419 case VCVTQQ2PHZrmbkz:
15420 case VCVTQQ2PHZrmk:
15421 case VCVTQQ2PHZrmkz:
15422 case VCVTQQ2PHZrr:
15423 case VCVTQQ2PHZrrb:
15424 case VCVTQQ2PHZrrbk:
15425 case VCVTQQ2PHZrrbkz:
15426 case VCVTQQ2PHZrrk:
15427 case VCVTQQ2PHZrrkz:
15428 return true;
15429 }
15430 return false;
15431}
15432
15433bool isVMOVUPD(unsigned Opcode) {
15434 switch (Opcode) {
15435 case VMOVUPDYmr:
15436 case VMOVUPDYrm:
15437 case VMOVUPDYrr:
15438 case VMOVUPDYrr_REV:
15439 case VMOVUPDZ128mr:
15440 case VMOVUPDZ128mrk:
15441 case VMOVUPDZ128rm:
15442 case VMOVUPDZ128rmk:
15443 case VMOVUPDZ128rmkz:
15444 case VMOVUPDZ128rr:
15445 case VMOVUPDZ128rr_REV:
15446 case VMOVUPDZ128rrk:
15447 case VMOVUPDZ128rrk_REV:
15448 case VMOVUPDZ128rrkz:
15449 case VMOVUPDZ128rrkz_REV:
15450 case VMOVUPDZ256mr:
15451 case VMOVUPDZ256mrk:
15452 case VMOVUPDZ256rm:
15453 case VMOVUPDZ256rmk:
15454 case VMOVUPDZ256rmkz:
15455 case VMOVUPDZ256rr:
15456 case VMOVUPDZ256rr_REV:
15457 case VMOVUPDZ256rrk:
15458 case VMOVUPDZ256rrk_REV:
15459 case VMOVUPDZ256rrkz:
15460 case VMOVUPDZ256rrkz_REV:
15461 case VMOVUPDZmr:
15462 case VMOVUPDZmrk:
15463 case VMOVUPDZrm:
15464 case VMOVUPDZrmk:
15465 case VMOVUPDZrmkz:
15466 case VMOVUPDZrr:
15467 case VMOVUPDZrr_REV:
15468 case VMOVUPDZrrk:
15469 case VMOVUPDZrrk_REV:
15470 case VMOVUPDZrrkz:
15471 case VMOVUPDZrrkz_REV:
15472 case VMOVUPDmr:
15473 case VMOVUPDrm:
15474 case VMOVUPDrr:
15475 case VMOVUPDrr_REV:
15476 return true;
15477 }
15478 return false;
15479}
15480
15481bool isFPTAN(unsigned Opcode) {
15482 return Opcode == FPTAN;
15483}
15484
15485bool isVMASKMOVPD(unsigned Opcode) {
15486 switch (Opcode) {
15487 case VMASKMOVPDYmr:
15488 case VMASKMOVPDYrm:
15489 case VMASKMOVPDmr:
15490 case VMASKMOVPDrm:
15491 return true;
15492 }
15493 return false;
15494}
15495
15496bool isVMOVLHPS(unsigned Opcode) {
15497 switch (Opcode) {
15498 case VMOVLHPSZrr:
15499 case VMOVLHPSrr:
15500 return true;
15501 }
15502 return false;
15503}
15504
15505bool isAESKEYGENASSIST(unsigned Opcode) {
15506 switch (Opcode) {
15507 case AESKEYGENASSISTrmi:
15508 case AESKEYGENASSISTrri:
15509 return true;
15510 }
15511 return false;
15512}
15513
15514bool isXSAVEOPT64(unsigned Opcode) {
15515 return Opcode == XSAVEOPT64;
15516}
15517
15518bool isXSAVEC(unsigned Opcode) {
15519 return Opcode == XSAVEC;
15520}
15521
15522bool isVPLZCNTQ(unsigned Opcode) {
15523 switch (Opcode) {
15524 case VPLZCNTQZ128rm:
15525 case VPLZCNTQZ128rmb:
15526 case VPLZCNTQZ128rmbk:
15527 case VPLZCNTQZ128rmbkz:
15528 case VPLZCNTQZ128rmk:
15529 case VPLZCNTQZ128rmkz:
15530 case VPLZCNTQZ128rr:
15531 case VPLZCNTQZ128rrk:
15532 case VPLZCNTQZ128rrkz:
15533 case VPLZCNTQZ256rm:
15534 case VPLZCNTQZ256rmb:
15535 case VPLZCNTQZ256rmbk:
15536 case VPLZCNTQZ256rmbkz:
15537 case VPLZCNTQZ256rmk:
15538 case VPLZCNTQZ256rmkz:
15539 case VPLZCNTQZ256rr:
15540 case VPLZCNTQZ256rrk:
15541 case VPLZCNTQZ256rrkz:
15542 case VPLZCNTQZrm:
15543 case VPLZCNTQZrmb:
15544 case VPLZCNTQZrmbk:
15545 case VPLZCNTQZrmbkz:
15546 case VPLZCNTQZrmk:
15547 case VPLZCNTQZrmkz:
15548 case VPLZCNTQZrr:
15549 case VPLZCNTQZrrk:
15550 case VPLZCNTQZrrkz:
15551 return true;
15552 }
15553 return false;
15554}
15555
15556bool isVPSUBW(unsigned Opcode) {
15557 switch (Opcode) {
15558 case VPSUBWYrm:
15559 case VPSUBWYrr:
15560 case VPSUBWZ128rm:
15561 case VPSUBWZ128rmk:
15562 case VPSUBWZ128rmkz:
15563 case VPSUBWZ128rr:
15564 case VPSUBWZ128rrk:
15565 case VPSUBWZ128rrkz:
15566 case VPSUBWZ256rm:
15567 case VPSUBWZ256rmk:
15568 case VPSUBWZ256rmkz:
15569 case VPSUBWZ256rr:
15570 case VPSUBWZ256rrk:
15571 case VPSUBWZ256rrkz:
15572 case VPSUBWZrm:
15573 case VPSUBWZrmk:
15574 case VPSUBWZrmkz:
15575 case VPSUBWZrr:
15576 case VPSUBWZrrk:
15577 case VPSUBWZrrkz:
15578 case VPSUBWrm:
15579 case VPSUBWrr:
15580 return true;
15581 }
15582 return false;
15583}
15584
15585bool isCMPCCXADD(unsigned Opcode) {
15586 switch (Opcode) {
15587 case CMPCCXADDmr32:
15588 case CMPCCXADDmr32_EVEX:
15589 case CMPCCXADDmr64:
15590 case CMPCCXADDmr64_EVEX:
15591 return true;
15592 }
15593 return false;
15594}
15595
15596bool isVFMSUBADD213PH(unsigned Opcode) {
15597 switch (Opcode) {
15598 case VFMSUBADD213PHZ128m:
15599 case VFMSUBADD213PHZ128mb:
15600 case VFMSUBADD213PHZ128mbk:
15601 case VFMSUBADD213PHZ128mbkz:
15602 case VFMSUBADD213PHZ128mk:
15603 case VFMSUBADD213PHZ128mkz:
15604 case VFMSUBADD213PHZ128r:
15605 case VFMSUBADD213PHZ128rk:
15606 case VFMSUBADD213PHZ128rkz:
15607 case VFMSUBADD213PHZ256m:
15608 case VFMSUBADD213PHZ256mb:
15609 case VFMSUBADD213PHZ256mbk:
15610 case VFMSUBADD213PHZ256mbkz:
15611 case VFMSUBADD213PHZ256mk:
15612 case VFMSUBADD213PHZ256mkz:
15613 case VFMSUBADD213PHZ256r:
15614 case VFMSUBADD213PHZ256rk:
15615 case VFMSUBADD213PHZ256rkz:
15616 case VFMSUBADD213PHZm:
15617 case VFMSUBADD213PHZmb:
15618 case VFMSUBADD213PHZmbk:
15619 case VFMSUBADD213PHZmbkz:
15620 case VFMSUBADD213PHZmk:
15621 case VFMSUBADD213PHZmkz:
15622 case VFMSUBADD213PHZr:
15623 case VFMSUBADD213PHZrb:
15624 case VFMSUBADD213PHZrbk:
15625 case VFMSUBADD213PHZrbkz:
15626 case VFMSUBADD213PHZrk:
15627 case VFMSUBADD213PHZrkz:
15628 return true;
15629 }
15630 return false;
15631}
15632
15633bool isVFMADDSUBPD(unsigned Opcode) {
15634 switch (Opcode) {
15635 case VFMADDSUBPD4Ymr:
15636 case VFMADDSUBPD4Yrm:
15637 case VFMADDSUBPD4Yrr:
15638 case VFMADDSUBPD4Yrr_REV:
15639 case VFMADDSUBPD4mr:
15640 case VFMADDSUBPD4rm:
15641 case VFMADDSUBPD4rr:
15642 case VFMADDSUBPD4rr_REV:
15643 return true;
15644 }
15645 return false;
15646}
15647
15648bool isVPMINSW(unsigned Opcode) {
15649 switch (Opcode) {
15650 case VPMINSWYrm:
15651 case VPMINSWYrr:
15652 case VPMINSWZ128rm:
15653 case VPMINSWZ128rmk:
15654 case VPMINSWZ128rmkz:
15655 case VPMINSWZ128rr:
15656 case VPMINSWZ128rrk:
15657 case VPMINSWZ128rrkz:
15658 case VPMINSWZ256rm:
15659 case VPMINSWZ256rmk:
15660 case VPMINSWZ256rmkz:
15661 case VPMINSWZ256rr:
15662 case VPMINSWZ256rrk:
15663 case VPMINSWZ256rrkz:
15664 case VPMINSWZrm:
15665 case VPMINSWZrmk:
15666 case VPMINSWZrmkz:
15667 case VPMINSWZrr:
15668 case VPMINSWZrrk:
15669 case VPMINSWZrrkz:
15670 case VPMINSWrm:
15671 case VPMINSWrr:
15672 return true;
15673 }
15674 return false;
15675}
15676
15677bool isVFNMSUB132PS(unsigned Opcode) {
15678 switch (Opcode) {
15679 case VFNMSUB132PSYm:
15680 case VFNMSUB132PSYr:
15681 case VFNMSUB132PSZ128m:
15682 case VFNMSUB132PSZ128mb:
15683 case VFNMSUB132PSZ128mbk:
15684 case VFNMSUB132PSZ128mbkz:
15685 case VFNMSUB132PSZ128mk:
15686 case VFNMSUB132PSZ128mkz:
15687 case VFNMSUB132PSZ128r:
15688 case VFNMSUB132PSZ128rk:
15689 case VFNMSUB132PSZ128rkz:
15690 case VFNMSUB132PSZ256m:
15691 case VFNMSUB132PSZ256mb:
15692 case VFNMSUB132PSZ256mbk:
15693 case VFNMSUB132PSZ256mbkz:
15694 case VFNMSUB132PSZ256mk:
15695 case VFNMSUB132PSZ256mkz:
15696 case VFNMSUB132PSZ256r:
15697 case VFNMSUB132PSZ256rk:
15698 case VFNMSUB132PSZ256rkz:
15699 case VFNMSUB132PSZm:
15700 case VFNMSUB132PSZmb:
15701 case VFNMSUB132PSZmbk:
15702 case VFNMSUB132PSZmbkz:
15703 case VFNMSUB132PSZmk:
15704 case VFNMSUB132PSZmkz:
15705 case VFNMSUB132PSZr:
15706 case VFNMSUB132PSZrb:
15707 case VFNMSUB132PSZrbk:
15708 case VFNMSUB132PSZrbkz:
15709 case VFNMSUB132PSZrk:
15710 case VFNMSUB132PSZrkz:
15711 case VFNMSUB132PSm:
15712 case VFNMSUB132PSr:
15713 return true;
15714 }
15715 return false;
15716}
15717
15718bool isVMOVAPS(unsigned Opcode) {
15719 switch (Opcode) {
15720 case VMOVAPSYmr:
15721 case VMOVAPSYrm:
15722 case VMOVAPSYrr:
15723 case VMOVAPSYrr_REV:
15724 case VMOVAPSZ128mr:
15725 case VMOVAPSZ128mrk:
15726 case VMOVAPSZ128rm:
15727 case VMOVAPSZ128rmk:
15728 case VMOVAPSZ128rmkz:
15729 case VMOVAPSZ128rr:
15730 case VMOVAPSZ128rr_REV:
15731 case VMOVAPSZ128rrk:
15732 case VMOVAPSZ128rrk_REV:
15733 case VMOVAPSZ128rrkz:
15734 case VMOVAPSZ128rrkz_REV:
15735 case VMOVAPSZ256mr:
15736 case VMOVAPSZ256mrk:
15737 case VMOVAPSZ256rm:
15738 case VMOVAPSZ256rmk:
15739 case VMOVAPSZ256rmkz:
15740 case VMOVAPSZ256rr:
15741 case VMOVAPSZ256rr_REV:
15742 case VMOVAPSZ256rrk:
15743 case VMOVAPSZ256rrk_REV:
15744 case VMOVAPSZ256rrkz:
15745 case VMOVAPSZ256rrkz_REV:
15746 case VMOVAPSZmr:
15747 case VMOVAPSZmrk:
15748 case VMOVAPSZrm:
15749 case VMOVAPSZrmk:
15750 case VMOVAPSZrmkz:
15751 case VMOVAPSZrr:
15752 case VMOVAPSZrr_REV:
15753 case VMOVAPSZrrk:
15754 case VMOVAPSZrrk_REV:
15755 case VMOVAPSZrrkz:
15756 case VMOVAPSZrrkz_REV:
15757 case VMOVAPSmr:
15758 case VMOVAPSrm:
15759 case VMOVAPSrr:
15760 case VMOVAPSrr_REV:
15761 return true;
15762 }
15763 return false;
15764}
15765
15766bool isVPEXTRQ(unsigned Opcode) {
15767 switch (Opcode) {
15768 case VPEXTRQZmri:
15769 case VPEXTRQZrri:
15770 case VPEXTRQmri:
15771 case VPEXTRQrri:
15772 return true;
15773 }
15774 return false;
15775}
15776
15777bool isVSCALEFSH(unsigned Opcode) {
15778 switch (Opcode) {
15779 case VSCALEFSHZrm:
15780 case VSCALEFSHZrmk:
15781 case VSCALEFSHZrmkz:
15782 case VSCALEFSHZrr:
15783 case VSCALEFSHZrrb_Int:
15784 case VSCALEFSHZrrbk_Int:
15785 case VSCALEFSHZrrbkz_Int:
15786 case VSCALEFSHZrrk:
15787 case VSCALEFSHZrrkz:
15788 return true;
15789 }
15790 return false;
15791}
15792
15793bool isVCVTPD2PS(unsigned Opcode) {
15794 switch (Opcode) {
15795 case VCVTPD2PSYrm:
15796 case VCVTPD2PSYrr:
15797 case VCVTPD2PSZ128rm:
15798 case VCVTPD2PSZ128rmb:
15799 case VCVTPD2PSZ128rmbk:
15800 case VCVTPD2PSZ128rmbkz:
15801 case VCVTPD2PSZ128rmk:
15802 case VCVTPD2PSZ128rmkz:
15803 case VCVTPD2PSZ128rr:
15804 case VCVTPD2PSZ128rrk:
15805 case VCVTPD2PSZ128rrkz:
15806 case VCVTPD2PSZ256rm:
15807 case VCVTPD2PSZ256rmb:
15808 case VCVTPD2PSZ256rmbk:
15809 case VCVTPD2PSZ256rmbkz:
15810 case VCVTPD2PSZ256rmk:
15811 case VCVTPD2PSZ256rmkz:
15812 case VCVTPD2PSZ256rr:
15813 case VCVTPD2PSZ256rrk:
15814 case VCVTPD2PSZ256rrkz:
15815 case VCVTPD2PSZrm:
15816 case VCVTPD2PSZrmb:
15817 case VCVTPD2PSZrmbk:
15818 case VCVTPD2PSZrmbkz:
15819 case VCVTPD2PSZrmk:
15820 case VCVTPD2PSZrmkz:
15821 case VCVTPD2PSZrr:
15822 case VCVTPD2PSZrrb:
15823 case VCVTPD2PSZrrbk:
15824 case VCVTPD2PSZrrbkz:
15825 case VCVTPD2PSZrrk:
15826 case VCVTPD2PSZrrkz:
15827 case VCVTPD2PSrm:
15828 case VCVTPD2PSrr:
15829 return true;
15830 }
15831 return false;
15832}
15833
15834bool isCLGI(unsigned Opcode) {
15835 return Opcode == CLGI;
15836}
15837
15838bool isVAESDEC(unsigned Opcode) {
15839 switch (Opcode) {
15840 case VAESDECYrm:
15841 case VAESDECYrr:
15842 case VAESDECZ128rm:
15843 case VAESDECZ128rr:
15844 case VAESDECZ256rm:
15845 case VAESDECZ256rr:
15846 case VAESDECZrm:
15847 case VAESDECZrr:
15848 case VAESDECrm:
15849 case VAESDECrr:
15850 return true;
15851 }
15852 return false;
15853}
15854
15855bool isPFMUL(unsigned Opcode) {
15856 switch (Opcode) {
15857 case PFMULrm:
15858 case PFMULrr:
15859 return true;
15860 }
15861 return false;
15862}
15863
15864bool isVCVTBIASPH2BF8S(unsigned Opcode) {
15865 switch (Opcode) {
15866 case VCVTBIASPH2BF8SZ128rm:
15867 case VCVTBIASPH2BF8SZ128rmb:
15868 case VCVTBIASPH2BF8SZ128rmbk:
15869 case VCVTBIASPH2BF8SZ128rmbkz:
15870 case VCVTBIASPH2BF8SZ128rmk:
15871 case VCVTBIASPH2BF8SZ128rmkz:
15872 case VCVTBIASPH2BF8SZ128rr:
15873 case VCVTBIASPH2BF8SZ128rrk:
15874 case VCVTBIASPH2BF8SZ128rrkz:
15875 case VCVTBIASPH2BF8SZ256rm:
15876 case VCVTBIASPH2BF8SZ256rmb:
15877 case VCVTBIASPH2BF8SZ256rmbk:
15878 case VCVTBIASPH2BF8SZ256rmbkz:
15879 case VCVTBIASPH2BF8SZ256rmk:
15880 case VCVTBIASPH2BF8SZ256rmkz:
15881 case VCVTBIASPH2BF8SZ256rr:
15882 case VCVTBIASPH2BF8SZ256rrk:
15883 case VCVTBIASPH2BF8SZ256rrkz:
15884 case VCVTBIASPH2BF8SZrm:
15885 case VCVTBIASPH2BF8SZrmb:
15886 case VCVTBIASPH2BF8SZrmbk:
15887 case VCVTBIASPH2BF8SZrmbkz:
15888 case VCVTBIASPH2BF8SZrmk:
15889 case VCVTBIASPH2BF8SZrmkz:
15890 case VCVTBIASPH2BF8SZrr:
15891 case VCVTBIASPH2BF8SZrrk:
15892 case VCVTBIASPH2BF8SZrrkz:
15893 return true;
15894 }
15895 return false;
15896}
15897
15898bool isMOVDIRI(unsigned Opcode) {
15899 switch (Opcode) {
15900 case MOVDIRI32:
15901 case MOVDIRI32_EVEX:
15902 case MOVDIRI64:
15903 case MOVDIRI64_EVEX:
15904 return true;
15905 }
15906 return false;
15907}
15908
15909bool isSHUFPS(unsigned Opcode) {
15910 switch (Opcode) {
15911 case SHUFPSrmi:
15912 case SHUFPSrri:
15913 return true;
15914 }
15915 return false;
15916}
15917
15918bool isVFNMSUB231SS(unsigned Opcode) {
15919 switch (Opcode) {
15920 case VFNMSUB231SSZm_Int:
15921 case VFNMSUB231SSZmk_Int:
15922 case VFNMSUB231SSZmkz_Int:
15923 case VFNMSUB231SSZr_Int:
15924 case VFNMSUB231SSZrb_Int:
15925 case VFNMSUB231SSZrbk_Int:
15926 case VFNMSUB231SSZrbkz_Int:
15927 case VFNMSUB231SSZrk_Int:
15928 case VFNMSUB231SSZrkz_Int:
15929 case VFNMSUB231SSm_Int:
15930 case VFNMSUB231SSr_Int:
15931 return true;
15932 }
15933 return false;
15934}
15935
15936bool isVMWRITE(unsigned Opcode) {
15937 switch (Opcode) {
15938 case VMWRITE32rm:
15939 case VMWRITE32rr:
15940 case VMWRITE64rm:
15941 case VMWRITE64rr:
15942 return true;
15943 }
15944 return false;
15945}
15946
15947bool isVINSERTF128(unsigned Opcode) {
15948 switch (Opcode) {
15949 case VINSERTF128rmi:
15950 case VINSERTF128rri:
15951 return true;
15952 }
15953 return false;
15954}
15955
15956bool isFISUBR(unsigned Opcode) {
15957 switch (Opcode) {
15958 case SUBR_FI16m:
15959 case SUBR_FI32m:
15960 return true;
15961 }
15962 return false;
15963}
15964
15965bool isVINSERTI32X4(unsigned Opcode) {
15966 switch (Opcode) {
15967 case VINSERTI32X4Z256rmi:
15968 case VINSERTI32X4Z256rmik:
15969 case VINSERTI32X4Z256rmikz:
15970 case VINSERTI32X4Z256rri:
15971 case VINSERTI32X4Z256rrik:
15972 case VINSERTI32X4Z256rrikz:
15973 case VINSERTI32X4Zrmi:
15974 case VINSERTI32X4Zrmik:
15975 case VINSERTI32X4Zrmikz:
15976 case VINSERTI32X4Zrri:
15977 case VINSERTI32X4Zrrik:
15978 case VINSERTI32X4Zrrikz:
15979 return true;
15980 }
15981 return false;
15982}
15983
15984bool isVPSLLDQ(unsigned Opcode) {
15985 switch (Opcode) {
15986 case VPSLLDQYri:
15987 case VPSLLDQZ128mi:
15988 case VPSLLDQZ128ri:
15989 case VPSLLDQZ256mi:
15990 case VPSLLDQZ256ri:
15991 case VPSLLDQZmi:
15992 case VPSLLDQZri:
15993 case VPSLLDQri:
15994 return true;
15995 }
15996 return false;
15997}
15998
15999bool isPOPCNT(unsigned Opcode) {
16000 switch (Opcode) {
16001 case POPCNT16rm:
16002 case POPCNT16rm_EVEX:
16003 case POPCNT16rm_NF:
16004 case POPCNT16rr:
16005 case POPCNT16rr_EVEX:
16006 case POPCNT16rr_NF:
16007 case POPCNT32rm:
16008 case POPCNT32rm_EVEX:
16009 case POPCNT32rm_NF:
16010 case POPCNT32rr:
16011 case POPCNT32rr_EVEX:
16012 case POPCNT32rr_NF:
16013 case POPCNT64rm:
16014 case POPCNT64rm_EVEX:
16015 case POPCNT64rm_NF:
16016 case POPCNT64rr:
16017 case POPCNT64rr_EVEX:
16018 case POPCNT64rr_NF:
16019 return true;
16020 }
16021 return false;
16022}
16023
16024bool isVXORPD(unsigned Opcode) {
16025 switch (Opcode) {
16026 case VXORPDYrm:
16027 case VXORPDYrr:
16028 case VXORPDZ128rm:
16029 case VXORPDZ128rmb:
16030 case VXORPDZ128rmbk:
16031 case VXORPDZ128rmbkz:
16032 case VXORPDZ128rmk:
16033 case VXORPDZ128rmkz:
16034 case VXORPDZ128rr:
16035 case VXORPDZ128rrk:
16036 case VXORPDZ128rrkz:
16037 case VXORPDZ256rm:
16038 case VXORPDZ256rmb:
16039 case VXORPDZ256rmbk:
16040 case VXORPDZ256rmbkz:
16041 case VXORPDZ256rmk:
16042 case VXORPDZ256rmkz:
16043 case VXORPDZ256rr:
16044 case VXORPDZ256rrk:
16045 case VXORPDZ256rrkz:
16046 case VXORPDZrm:
16047 case VXORPDZrmb:
16048 case VXORPDZrmbk:
16049 case VXORPDZrmbkz:
16050 case VXORPDZrmk:
16051 case VXORPDZrmkz:
16052 case VXORPDZrr:
16053 case VXORPDZrrk:
16054 case VXORPDZrrkz:
16055 case VXORPDrm:
16056 case VXORPDrr:
16057 return true;
16058 }
16059 return false;
16060}
16061
16062bool isXLATB(unsigned Opcode) {
16063 return Opcode == XLAT;
16064}
16065
16066bool isDIV(unsigned Opcode) {
16067 switch (Opcode) {
16068 case DIV16m:
16069 case DIV16m_EVEX:
16070 case DIV16m_NF:
16071 case DIV16r:
16072 case DIV16r_EVEX:
16073 case DIV16r_NF:
16074 case DIV32m:
16075 case DIV32m_EVEX:
16076 case DIV32m_NF:
16077 case DIV32r:
16078 case DIV32r_EVEX:
16079 case DIV32r_NF:
16080 case DIV64m:
16081 case DIV64m_EVEX:
16082 case DIV64m_NF:
16083 case DIV64r:
16084 case DIV64r_EVEX:
16085 case DIV64r_NF:
16086 case DIV8m:
16087 case DIV8m_EVEX:
16088 case DIV8m_NF:
16089 case DIV8r:
16090 case DIV8r_EVEX:
16091 case DIV8r_NF:
16092 return true;
16093 }
16094 return false;
16095}
16096
16097bool isVPSHLDVQ(unsigned Opcode) {
16098 switch (Opcode) {
16099 case VPSHLDVQZ128m:
16100 case VPSHLDVQZ128mb:
16101 case VPSHLDVQZ128mbk:
16102 case VPSHLDVQZ128mbkz:
16103 case VPSHLDVQZ128mk:
16104 case VPSHLDVQZ128mkz:
16105 case VPSHLDVQZ128r:
16106 case VPSHLDVQZ128rk:
16107 case VPSHLDVQZ128rkz:
16108 case VPSHLDVQZ256m:
16109 case VPSHLDVQZ256mb:
16110 case VPSHLDVQZ256mbk:
16111 case VPSHLDVQZ256mbkz:
16112 case VPSHLDVQZ256mk:
16113 case VPSHLDVQZ256mkz:
16114 case VPSHLDVQZ256r:
16115 case VPSHLDVQZ256rk:
16116 case VPSHLDVQZ256rkz:
16117 case VPSHLDVQZm:
16118 case VPSHLDVQZmb:
16119 case VPSHLDVQZmbk:
16120 case VPSHLDVQZmbkz:
16121 case VPSHLDVQZmk:
16122 case VPSHLDVQZmkz:
16123 case VPSHLDVQZr:
16124 case VPSHLDVQZrk:
16125 case VPSHLDVQZrkz:
16126 return true;
16127 }
16128 return false;
16129}
16130
16131bool isMOVDDUP(unsigned Opcode) {
16132 switch (Opcode) {
16133 case MOVDDUPrm:
16134 case MOVDDUPrr:
16135 return true;
16136 }
16137 return false;
16138}
16139
16140bool isVMOVDQU64(unsigned Opcode) {
16141 switch (Opcode) {
16142 case VMOVDQU64Z128mr:
16143 case VMOVDQU64Z128mrk:
16144 case VMOVDQU64Z128rm:
16145 case VMOVDQU64Z128rmk:
16146 case VMOVDQU64Z128rmkz:
16147 case VMOVDQU64Z128rr:
16148 case VMOVDQU64Z128rr_REV:
16149 case VMOVDQU64Z128rrk:
16150 case VMOVDQU64Z128rrk_REV:
16151 case VMOVDQU64Z128rrkz:
16152 case VMOVDQU64Z128rrkz_REV:
16153 case VMOVDQU64Z256mr:
16154 case VMOVDQU64Z256mrk:
16155 case VMOVDQU64Z256rm:
16156 case VMOVDQU64Z256rmk:
16157 case VMOVDQU64Z256rmkz:
16158 case VMOVDQU64Z256rr:
16159 case VMOVDQU64Z256rr_REV:
16160 case VMOVDQU64Z256rrk:
16161 case VMOVDQU64Z256rrk_REV:
16162 case VMOVDQU64Z256rrkz:
16163 case VMOVDQU64Z256rrkz_REV:
16164 case VMOVDQU64Zmr:
16165 case VMOVDQU64Zmrk:
16166 case VMOVDQU64Zrm:
16167 case VMOVDQU64Zrmk:
16168 case VMOVDQU64Zrmkz:
16169 case VMOVDQU64Zrr:
16170 case VMOVDQU64Zrr_REV:
16171 case VMOVDQU64Zrrk:
16172 case VMOVDQU64Zrrk_REV:
16173 case VMOVDQU64Zrrkz:
16174 case VMOVDQU64Zrrkz_REV:
16175 return true;
16176 }
16177 return false;
16178}
16179
16180bool isVPCOMPRESSQ(unsigned Opcode) {
16181 switch (Opcode) {
16182 case VPCOMPRESSQZ128mr:
16183 case VPCOMPRESSQZ128mrk:
16184 case VPCOMPRESSQZ128rr:
16185 case VPCOMPRESSQZ128rrk:
16186 case VPCOMPRESSQZ128rrkz:
16187 case VPCOMPRESSQZ256mr:
16188 case VPCOMPRESSQZ256mrk:
16189 case VPCOMPRESSQZ256rr:
16190 case VPCOMPRESSQZ256rrk:
16191 case VPCOMPRESSQZ256rrkz:
16192 case VPCOMPRESSQZmr:
16193 case VPCOMPRESSQZmrk:
16194 case VPCOMPRESSQZrr:
16195 case VPCOMPRESSQZrrk:
16196 case VPCOMPRESSQZrrkz:
16197 return true;
16198 }
16199 return false;
16200}
16201
16202bool isVFMSUBADD132PD(unsigned Opcode) {
16203 switch (Opcode) {
16204 case VFMSUBADD132PDYm:
16205 case VFMSUBADD132PDYr:
16206 case VFMSUBADD132PDZ128m:
16207 case VFMSUBADD132PDZ128mb:
16208 case VFMSUBADD132PDZ128mbk:
16209 case VFMSUBADD132PDZ128mbkz:
16210 case VFMSUBADD132PDZ128mk:
16211 case VFMSUBADD132PDZ128mkz:
16212 case VFMSUBADD132PDZ128r:
16213 case VFMSUBADD132PDZ128rk:
16214 case VFMSUBADD132PDZ128rkz:
16215 case VFMSUBADD132PDZ256m:
16216 case VFMSUBADD132PDZ256mb:
16217 case VFMSUBADD132PDZ256mbk:
16218 case VFMSUBADD132PDZ256mbkz:
16219 case VFMSUBADD132PDZ256mk:
16220 case VFMSUBADD132PDZ256mkz:
16221 case VFMSUBADD132PDZ256r:
16222 case VFMSUBADD132PDZ256rk:
16223 case VFMSUBADD132PDZ256rkz:
16224 case VFMSUBADD132PDZm:
16225 case VFMSUBADD132PDZmb:
16226 case VFMSUBADD132PDZmbk:
16227 case VFMSUBADD132PDZmbkz:
16228 case VFMSUBADD132PDZmk:
16229 case VFMSUBADD132PDZmkz:
16230 case VFMSUBADD132PDZr:
16231 case VFMSUBADD132PDZrb:
16232 case VFMSUBADD132PDZrbk:
16233 case VFMSUBADD132PDZrbkz:
16234 case VFMSUBADD132PDZrk:
16235 case VFMSUBADD132PDZrkz:
16236 case VFMSUBADD132PDm:
16237 case VFMSUBADD132PDr:
16238 return true;
16239 }
16240 return false;
16241}
16242
16243bool isADDSD(unsigned Opcode) {
16244 switch (Opcode) {
16245 case ADDSDrm_Int:
16246 case ADDSDrr_Int:
16247 return true;
16248 }
16249 return false;
16250}
16251
16252bool isBLENDPD(unsigned Opcode) {
16253 switch (Opcode) {
16254 case BLENDPDrmi:
16255 case BLENDPDrri:
16256 return true;
16257 }
16258 return false;
16259}
16260
16261bool isVPERMILPD(unsigned Opcode) {
16262 switch (Opcode) {
16263 case VPERMILPDYmi:
16264 case VPERMILPDYri:
16265 case VPERMILPDYrm:
16266 case VPERMILPDYrr:
16267 case VPERMILPDZ128mbi:
16268 case VPERMILPDZ128mbik:
16269 case VPERMILPDZ128mbikz:
16270 case VPERMILPDZ128mi:
16271 case VPERMILPDZ128mik:
16272 case VPERMILPDZ128mikz:
16273 case VPERMILPDZ128ri:
16274 case VPERMILPDZ128rik:
16275 case VPERMILPDZ128rikz:
16276 case VPERMILPDZ128rm:
16277 case VPERMILPDZ128rmb:
16278 case VPERMILPDZ128rmbk:
16279 case VPERMILPDZ128rmbkz:
16280 case VPERMILPDZ128rmk:
16281 case VPERMILPDZ128rmkz:
16282 case VPERMILPDZ128rr:
16283 case VPERMILPDZ128rrk:
16284 case VPERMILPDZ128rrkz:
16285 case VPERMILPDZ256mbi:
16286 case VPERMILPDZ256mbik:
16287 case VPERMILPDZ256mbikz:
16288 case VPERMILPDZ256mi:
16289 case VPERMILPDZ256mik:
16290 case VPERMILPDZ256mikz:
16291 case VPERMILPDZ256ri:
16292 case VPERMILPDZ256rik:
16293 case VPERMILPDZ256rikz:
16294 case VPERMILPDZ256rm:
16295 case VPERMILPDZ256rmb:
16296 case VPERMILPDZ256rmbk:
16297 case VPERMILPDZ256rmbkz:
16298 case VPERMILPDZ256rmk:
16299 case VPERMILPDZ256rmkz:
16300 case VPERMILPDZ256rr:
16301 case VPERMILPDZ256rrk:
16302 case VPERMILPDZ256rrkz:
16303 case VPERMILPDZmbi:
16304 case VPERMILPDZmbik:
16305 case VPERMILPDZmbikz:
16306 case VPERMILPDZmi:
16307 case VPERMILPDZmik:
16308 case VPERMILPDZmikz:
16309 case VPERMILPDZri:
16310 case VPERMILPDZrik:
16311 case VPERMILPDZrikz:
16312 case VPERMILPDZrm:
16313 case VPERMILPDZrmb:
16314 case VPERMILPDZrmbk:
16315 case VPERMILPDZrmbkz:
16316 case VPERMILPDZrmk:
16317 case VPERMILPDZrmkz:
16318 case VPERMILPDZrr:
16319 case VPERMILPDZrrk:
16320 case VPERMILPDZrrkz:
16321 case VPERMILPDmi:
16322 case VPERMILPDri:
16323 case VPERMILPDrm:
16324 case VPERMILPDrr:
16325 return true;
16326 }
16327 return false;
16328}
16329
16330bool isPMADDUBSW(unsigned Opcode) {
16331 switch (Opcode) {
16332 case MMX_PMADDUBSWrm:
16333 case MMX_PMADDUBSWrr:
16334 case PMADDUBSWrm:
16335 case PMADDUBSWrr:
16336 return true;
16337 }
16338 return false;
16339}
16340
16341bool isPOPFD(unsigned Opcode) {
16342 return Opcode == POPF32;
16343}
16344
16345bool isCMPSW(unsigned Opcode) {
16346 return Opcode == CMPSW;
16347}
16348
16349bool isLDMXCSR(unsigned Opcode) {
16350 return Opcode == LDMXCSR;
16351}
16352
16353bool isVMULPS(unsigned Opcode) {
16354 switch (Opcode) {
16355 case VMULPSYrm:
16356 case VMULPSYrr:
16357 case VMULPSZ128rm:
16358 case VMULPSZ128rmb:
16359 case VMULPSZ128rmbk:
16360 case VMULPSZ128rmbkz:
16361 case VMULPSZ128rmk:
16362 case VMULPSZ128rmkz:
16363 case VMULPSZ128rr:
16364 case VMULPSZ128rrk:
16365 case VMULPSZ128rrkz:
16366 case VMULPSZ256rm:
16367 case VMULPSZ256rmb:
16368 case VMULPSZ256rmbk:
16369 case VMULPSZ256rmbkz:
16370 case VMULPSZ256rmk:
16371 case VMULPSZ256rmkz:
16372 case VMULPSZ256rr:
16373 case VMULPSZ256rrk:
16374 case VMULPSZ256rrkz:
16375 case VMULPSZrm:
16376 case VMULPSZrmb:
16377 case VMULPSZrmbk:
16378 case VMULPSZrmbkz:
16379 case VMULPSZrmk:
16380 case VMULPSZrmkz:
16381 case VMULPSZrr:
16382 case VMULPSZrrb:
16383 case VMULPSZrrbk:
16384 case VMULPSZrrbkz:
16385 case VMULPSZrrk:
16386 case VMULPSZrrkz:
16387 case VMULPSrm:
16388 case VMULPSrr:
16389 return true;
16390 }
16391 return false;
16392}
16393
16394bool isVROUNDSD(unsigned Opcode) {
16395 switch (Opcode) {
16396 case VROUNDSDmi_Int:
16397 case VROUNDSDri_Int:
16398 return true;
16399 }
16400 return false;
16401}
16402
16403bool isVFMADD132PD(unsigned Opcode) {
16404 switch (Opcode) {
16405 case VFMADD132PDYm:
16406 case VFMADD132PDYr:
16407 case VFMADD132PDZ128m:
16408 case VFMADD132PDZ128mb:
16409 case VFMADD132PDZ128mbk:
16410 case VFMADD132PDZ128mbkz:
16411 case VFMADD132PDZ128mk:
16412 case VFMADD132PDZ128mkz:
16413 case VFMADD132PDZ128r:
16414 case VFMADD132PDZ128rk:
16415 case VFMADD132PDZ128rkz:
16416 case VFMADD132PDZ256m:
16417 case VFMADD132PDZ256mb:
16418 case VFMADD132PDZ256mbk:
16419 case VFMADD132PDZ256mbkz:
16420 case VFMADD132PDZ256mk:
16421 case VFMADD132PDZ256mkz:
16422 case VFMADD132PDZ256r:
16423 case VFMADD132PDZ256rk:
16424 case VFMADD132PDZ256rkz:
16425 case VFMADD132PDZm:
16426 case VFMADD132PDZmb:
16427 case VFMADD132PDZmbk:
16428 case VFMADD132PDZmbkz:
16429 case VFMADD132PDZmk:
16430 case VFMADD132PDZmkz:
16431 case VFMADD132PDZr:
16432 case VFMADD132PDZrb:
16433 case VFMADD132PDZrbk:
16434 case VFMADD132PDZrbkz:
16435 case VFMADD132PDZrk:
16436 case VFMADD132PDZrkz:
16437 case VFMADD132PDm:
16438 case VFMADD132PDr:
16439 return true;
16440 }
16441 return false;
16442}
16443
16444bool isVPANDQ(unsigned Opcode) {
16445 switch (Opcode) {
16446 case VPANDQZ128rm:
16447 case VPANDQZ128rmb:
16448 case VPANDQZ128rmbk:
16449 case VPANDQZ128rmbkz:
16450 case VPANDQZ128rmk:
16451 case VPANDQZ128rmkz:
16452 case VPANDQZ128rr:
16453 case VPANDQZ128rrk:
16454 case VPANDQZ128rrkz:
16455 case VPANDQZ256rm:
16456 case VPANDQZ256rmb:
16457 case VPANDQZ256rmbk:
16458 case VPANDQZ256rmbkz:
16459 case VPANDQZ256rmk:
16460 case VPANDQZ256rmkz:
16461 case VPANDQZ256rr:
16462 case VPANDQZ256rrk:
16463 case VPANDQZ256rrkz:
16464 case VPANDQZrm:
16465 case VPANDQZrmb:
16466 case VPANDQZrmbk:
16467 case VPANDQZrmbkz:
16468 case VPANDQZrmk:
16469 case VPANDQZrmkz:
16470 case VPANDQZrr:
16471 case VPANDQZrrk:
16472 case VPANDQZrrkz:
16473 return true;
16474 }
16475 return false;
16476}
16477
16478bool isVPSRAQ(unsigned Opcode) {
16479 switch (Opcode) {
16480 case VPSRAQZ128mbi:
16481 case VPSRAQZ128mbik:
16482 case VPSRAQZ128mbikz:
16483 case VPSRAQZ128mi:
16484 case VPSRAQZ128mik:
16485 case VPSRAQZ128mikz:
16486 case VPSRAQZ128ri:
16487 case VPSRAQZ128rik:
16488 case VPSRAQZ128rikz:
16489 case VPSRAQZ128rm:
16490 case VPSRAQZ128rmk:
16491 case VPSRAQZ128rmkz:
16492 case VPSRAQZ128rr:
16493 case VPSRAQZ128rrk:
16494 case VPSRAQZ128rrkz:
16495 case VPSRAQZ256mbi:
16496 case VPSRAQZ256mbik:
16497 case VPSRAQZ256mbikz:
16498 case VPSRAQZ256mi:
16499 case VPSRAQZ256mik:
16500 case VPSRAQZ256mikz:
16501 case VPSRAQZ256ri:
16502 case VPSRAQZ256rik:
16503 case VPSRAQZ256rikz:
16504 case VPSRAQZ256rm:
16505 case VPSRAQZ256rmk:
16506 case VPSRAQZ256rmkz:
16507 case VPSRAQZ256rr:
16508 case VPSRAQZ256rrk:
16509 case VPSRAQZ256rrkz:
16510 case VPSRAQZmbi:
16511 case VPSRAQZmbik:
16512 case VPSRAQZmbikz:
16513 case VPSRAQZmi:
16514 case VPSRAQZmik:
16515 case VPSRAQZmikz:
16516 case VPSRAQZri:
16517 case VPSRAQZrik:
16518 case VPSRAQZrikz:
16519 case VPSRAQZrm:
16520 case VPSRAQZrmk:
16521 case VPSRAQZrmkz:
16522 case VPSRAQZrr:
16523 case VPSRAQZrrk:
16524 case VPSRAQZrrkz:
16525 return true;
16526 }
16527 return false;
16528}
16529
16530bool isVCOMISD(unsigned Opcode) {
16531 switch (Opcode) {
16532 case VCOMISDZrm:
16533 case VCOMISDZrr:
16534 case VCOMISDZrrb:
16535 case VCOMISDrm:
16536 case VCOMISDrr:
16537 return true;
16538 }
16539 return false;
16540}
16541
16542bool isVCVTBIASPH2BF8(unsigned Opcode) {
16543 switch (Opcode) {
16544 case VCVTBIASPH2BF8Z128rm:
16545 case VCVTBIASPH2BF8Z128rmb:
16546 case VCVTBIASPH2BF8Z128rmbk:
16547 case VCVTBIASPH2BF8Z128rmbkz:
16548 case VCVTBIASPH2BF8Z128rmk:
16549 case VCVTBIASPH2BF8Z128rmkz:
16550 case VCVTBIASPH2BF8Z128rr:
16551 case VCVTBIASPH2BF8Z128rrk:
16552 case VCVTBIASPH2BF8Z128rrkz:
16553 case VCVTBIASPH2BF8Z256rm:
16554 case VCVTBIASPH2BF8Z256rmb:
16555 case VCVTBIASPH2BF8Z256rmbk:
16556 case VCVTBIASPH2BF8Z256rmbkz:
16557 case VCVTBIASPH2BF8Z256rmk:
16558 case VCVTBIASPH2BF8Z256rmkz:
16559 case VCVTBIASPH2BF8Z256rr:
16560 case VCVTBIASPH2BF8Z256rrk:
16561 case VCVTBIASPH2BF8Z256rrkz:
16562 case VCVTBIASPH2BF8Zrm:
16563 case VCVTBIASPH2BF8Zrmb:
16564 case VCVTBIASPH2BF8Zrmbk:
16565 case VCVTBIASPH2BF8Zrmbkz:
16566 case VCVTBIASPH2BF8Zrmk:
16567 case VCVTBIASPH2BF8Zrmkz:
16568 case VCVTBIASPH2BF8Zrr:
16569 case VCVTBIASPH2BF8Zrrk:
16570 case VCVTBIASPH2BF8Zrrkz:
16571 return true;
16572 }
16573 return false;
16574}
16575
16576bool isFFREEP(unsigned Opcode) {
16577 return Opcode == FFREEP;
16578}
16579
16580bool isVFNMADD213PD(unsigned Opcode) {
16581 switch (Opcode) {
16582 case VFNMADD213PDYm:
16583 case VFNMADD213PDYr:
16584 case VFNMADD213PDZ128m:
16585 case VFNMADD213PDZ128mb:
16586 case VFNMADD213PDZ128mbk:
16587 case VFNMADD213PDZ128mbkz:
16588 case VFNMADD213PDZ128mk:
16589 case VFNMADD213PDZ128mkz:
16590 case VFNMADD213PDZ128r:
16591 case VFNMADD213PDZ128rk:
16592 case VFNMADD213PDZ128rkz:
16593 case VFNMADD213PDZ256m:
16594 case VFNMADD213PDZ256mb:
16595 case VFNMADD213PDZ256mbk:
16596 case VFNMADD213PDZ256mbkz:
16597 case VFNMADD213PDZ256mk:
16598 case VFNMADD213PDZ256mkz:
16599 case VFNMADD213PDZ256r:
16600 case VFNMADD213PDZ256rk:
16601 case VFNMADD213PDZ256rkz:
16602 case VFNMADD213PDZm:
16603 case VFNMADD213PDZmb:
16604 case VFNMADD213PDZmbk:
16605 case VFNMADD213PDZmbkz:
16606 case VFNMADD213PDZmk:
16607 case VFNMADD213PDZmkz:
16608 case VFNMADD213PDZr:
16609 case VFNMADD213PDZrb:
16610 case VFNMADD213PDZrbk:
16611 case VFNMADD213PDZrbkz:
16612 case VFNMADD213PDZrk:
16613 case VFNMADD213PDZrkz:
16614 case VFNMADD213PDm:
16615 case VFNMADD213PDr:
16616 return true;
16617 }
16618 return false;
16619}
16620
16621bool isVCMPPD(unsigned Opcode) {
16622 switch (Opcode) {
16623 case VCMPPDYrmi:
16624 case VCMPPDYrri:
16625 case VCMPPDZ128rmbi:
16626 case VCMPPDZ128rmbik:
16627 case VCMPPDZ128rmi:
16628 case VCMPPDZ128rmik:
16629 case VCMPPDZ128rri:
16630 case VCMPPDZ128rrik:
16631 case VCMPPDZ256rmbi:
16632 case VCMPPDZ256rmbik:
16633 case VCMPPDZ256rmi:
16634 case VCMPPDZ256rmik:
16635 case VCMPPDZ256rri:
16636 case VCMPPDZ256rrik:
16637 case VCMPPDZrmbi:
16638 case VCMPPDZrmbik:
16639 case VCMPPDZrmi:
16640 case VCMPPDZrmik:
16641 case VCMPPDZrri:
16642 case VCMPPDZrrib:
16643 case VCMPPDZrribk:
16644 case VCMPPDZrrik:
16645 case VCMPPDrmi:
16646 case VCMPPDrri:
16647 return true;
16648 }
16649 return false;
16650}
16651
16652bool isVFNMSUB132PH(unsigned Opcode) {
16653 switch (Opcode) {
16654 case VFNMSUB132PHZ128m:
16655 case VFNMSUB132PHZ128mb:
16656 case VFNMSUB132PHZ128mbk:
16657 case VFNMSUB132PHZ128mbkz:
16658 case VFNMSUB132PHZ128mk:
16659 case VFNMSUB132PHZ128mkz:
16660 case VFNMSUB132PHZ128r:
16661 case VFNMSUB132PHZ128rk:
16662 case VFNMSUB132PHZ128rkz:
16663 case VFNMSUB132PHZ256m:
16664 case VFNMSUB132PHZ256mb:
16665 case VFNMSUB132PHZ256mbk:
16666 case VFNMSUB132PHZ256mbkz:
16667 case VFNMSUB132PHZ256mk:
16668 case VFNMSUB132PHZ256mkz:
16669 case VFNMSUB132PHZ256r:
16670 case VFNMSUB132PHZ256rk:
16671 case VFNMSUB132PHZ256rkz:
16672 case VFNMSUB132PHZm:
16673 case VFNMSUB132PHZmb:
16674 case VFNMSUB132PHZmbk:
16675 case VFNMSUB132PHZmbkz:
16676 case VFNMSUB132PHZmk:
16677 case VFNMSUB132PHZmkz:
16678 case VFNMSUB132PHZr:
16679 case VFNMSUB132PHZrb:
16680 case VFNMSUB132PHZrbk:
16681 case VFNMSUB132PHZrbkz:
16682 case VFNMSUB132PHZrk:
16683 case VFNMSUB132PHZrkz:
16684 return true;
16685 }
16686 return false;
16687}
16688
16689bool isVPHADDBW(unsigned Opcode) {
16690 switch (Opcode) {
16691 case VPHADDBWrm:
16692 case VPHADDBWrr:
16693 return true;
16694 }
16695 return false;
16696}
16697
16698bool isVPPERM(unsigned Opcode) {
16699 switch (Opcode) {
16700 case VPPERMrmr:
16701 case VPPERMrrm:
16702 case VPPERMrrr:
16703 case VPPERMrrr_REV:
16704 return true;
16705 }
16706 return false;
16707}
16708
16709bool isVCVTPS2PD(unsigned Opcode) {
16710 switch (Opcode) {
16711 case VCVTPS2PDYrm:
16712 case VCVTPS2PDYrr:
16713 case VCVTPS2PDZ128rm:
16714 case VCVTPS2PDZ128rmb:
16715 case VCVTPS2PDZ128rmbk:
16716 case VCVTPS2PDZ128rmbkz:
16717 case VCVTPS2PDZ128rmk:
16718 case VCVTPS2PDZ128rmkz:
16719 case VCVTPS2PDZ128rr:
16720 case VCVTPS2PDZ128rrk:
16721 case VCVTPS2PDZ128rrkz:
16722 case VCVTPS2PDZ256rm:
16723 case VCVTPS2PDZ256rmb:
16724 case VCVTPS2PDZ256rmbk:
16725 case VCVTPS2PDZ256rmbkz:
16726 case VCVTPS2PDZ256rmk:
16727 case VCVTPS2PDZ256rmkz:
16728 case VCVTPS2PDZ256rr:
16729 case VCVTPS2PDZ256rrk:
16730 case VCVTPS2PDZ256rrkz:
16731 case VCVTPS2PDZrm:
16732 case VCVTPS2PDZrmb:
16733 case VCVTPS2PDZrmbk:
16734 case VCVTPS2PDZrmbkz:
16735 case VCVTPS2PDZrmk:
16736 case VCVTPS2PDZrmkz:
16737 case VCVTPS2PDZrr:
16738 case VCVTPS2PDZrrb:
16739 case VCVTPS2PDZrrbk:
16740 case VCVTPS2PDZrrbkz:
16741 case VCVTPS2PDZrrk:
16742 case VCVTPS2PDZrrkz:
16743 case VCVTPS2PDrm:
16744 case VCVTPS2PDrr:
16745 return true;
16746 }
16747 return false;
16748}
16749
16750bool isCBW(unsigned Opcode) {
16751 return Opcode == CBW;
16752}
16753
16754bool isVMOVUPS(unsigned Opcode) {
16755 switch (Opcode) {
16756 case VMOVUPSYmr:
16757 case VMOVUPSYrm:
16758 case VMOVUPSYrr:
16759 case VMOVUPSYrr_REV:
16760 case VMOVUPSZ128mr:
16761 case VMOVUPSZ128mrk:
16762 case VMOVUPSZ128rm:
16763 case VMOVUPSZ128rmk:
16764 case VMOVUPSZ128rmkz:
16765 case VMOVUPSZ128rr:
16766 case VMOVUPSZ128rr_REV:
16767 case VMOVUPSZ128rrk:
16768 case VMOVUPSZ128rrk_REV:
16769 case VMOVUPSZ128rrkz:
16770 case VMOVUPSZ128rrkz_REV:
16771 case VMOVUPSZ256mr:
16772 case VMOVUPSZ256mrk:
16773 case VMOVUPSZ256rm:
16774 case VMOVUPSZ256rmk:
16775 case VMOVUPSZ256rmkz:
16776 case VMOVUPSZ256rr:
16777 case VMOVUPSZ256rr_REV:
16778 case VMOVUPSZ256rrk:
16779 case VMOVUPSZ256rrk_REV:
16780 case VMOVUPSZ256rrkz:
16781 case VMOVUPSZ256rrkz_REV:
16782 case VMOVUPSZmr:
16783 case VMOVUPSZmrk:
16784 case VMOVUPSZrm:
16785 case VMOVUPSZrmk:
16786 case VMOVUPSZrmkz:
16787 case VMOVUPSZrr:
16788 case VMOVUPSZrr_REV:
16789 case VMOVUPSZrrk:
16790 case VMOVUPSZrrk_REV:
16791 case VMOVUPSZrrkz:
16792 case VMOVUPSZrrkz_REV:
16793 case VMOVUPSmr:
16794 case VMOVUPSrm:
16795 case VMOVUPSrr:
16796 case VMOVUPSrr_REV:
16797 return true;
16798 }
16799 return false;
16800}
16801
16802bool isVPMAXUQ(unsigned Opcode) {
16803 switch (Opcode) {
16804 case VPMAXUQZ128rm:
16805 case VPMAXUQZ128rmb:
16806 case VPMAXUQZ128rmbk:
16807 case VPMAXUQZ128rmbkz:
16808 case VPMAXUQZ128rmk:
16809 case VPMAXUQZ128rmkz:
16810 case VPMAXUQZ128rr:
16811 case VPMAXUQZ128rrk:
16812 case VPMAXUQZ128rrkz:
16813 case VPMAXUQZ256rm:
16814 case VPMAXUQZ256rmb:
16815 case VPMAXUQZ256rmbk:
16816 case VPMAXUQZ256rmbkz:
16817 case VPMAXUQZ256rmk:
16818 case VPMAXUQZ256rmkz:
16819 case VPMAXUQZ256rr:
16820 case VPMAXUQZ256rrk:
16821 case VPMAXUQZ256rrkz:
16822 case VPMAXUQZrm:
16823 case VPMAXUQZrmb:
16824 case VPMAXUQZrmbk:
16825 case VPMAXUQZrmbkz:
16826 case VPMAXUQZrmk:
16827 case VPMAXUQZrmkz:
16828 case VPMAXUQZrr:
16829 case VPMAXUQZrrk:
16830 case VPMAXUQZrrkz:
16831 return true;
16832 }
16833 return false;
16834}
16835
16836bool isWRSSQ(unsigned Opcode) {
16837 switch (Opcode) {
16838 case WRSSQ:
16839 case WRSSQ_EVEX:
16840 return true;
16841 }
16842 return false;
16843}
16844
16845bool isPACKUSDW(unsigned Opcode) {
16846 switch (Opcode) {
16847 case PACKUSDWrm:
16848 case PACKUSDWrr:
16849 return true;
16850 }
16851 return false;
16852}
16853
16854bool isVCVTTBF162IBS(unsigned Opcode) {
16855 switch (Opcode) {
16856 case VCVTTBF162IBSZ128rm:
16857 case VCVTTBF162IBSZ128rmb:
16858 case VCVTTBF162IBSZ128rmbk:
16859 case VCVTTBF162IBSZ128rmbkz:
16860 case VCVTTBF162IBSZ128rmk:
16861 case VCVTTBF162IBSZ128rmkz:
16862 case VCVTTBF162IBSZ128rr:
16863 case VCVTTBF162IBSZ128rrk:
16864 case VCVTTBF162IBSZ128rrkz:
16865 case VCVTTBF162IBSZ256rm:
16866 case VCVTTBF162IBSZ256rmb:
16867 case VCVTTBF162IBSZ256rmbk:
16868 case VCVTTBF162IBSZ256rmbkz:
16869 case VCVTTBF162IBSZ256rmk:
16870 case VCVTTBF162IBSZ256rmkz:
16871 case VCVTTBF162IBSZ256rr:
16872 case VCVTTBF162IBSZ256rrk:
16873 case VCVTTBF162IBSZ256rrkz:
16874 case VCVTTBF162IBSZrm:
16875 case VCVTTBF162IBSZrmb:
16876 case VCVTTBF162IBSZrmbk:
16877 case VCVTTBF162IBSZrmbkz:
16878 case VCVTTBF162IBSZrmk:
16879 case VCVTTBF162IBSZrmkz:
16880 case VCVTTBF162IBSZrr:
16881 case VCVTTBF162IBSZrrk:
16882 case VCVTTBF162IBSZrrkz:
16883 return true;
16884 }
16885 return false;
16886}
16887
16888bool isXBEGIN(unsigned Opcode) {
16889 switch (Opcode) {
16890 case XBEGIN_2:
16891 case XBEGIN_4:
16892 return true;
16893 }
16894 return false;
16895}
16896
16897bool isVCVTPD2UQQ(unsigned Opcode) {
16898 switch (Opcode) {
16899 case VCVTPD2UQQZ128rm:
16900 case VCVTPD2UQQZ128rmb:
16901 case VCVTPD2UQQZ128rmbk:
16902 case VCVTPD2UQQZ128rmbkz:
16903 case VCVTPD2UQQZ128rmk:
16904 case VCVTPD2UQQZ128rmkz:
16905 case VCVTPD2UQQZ128rr:
16906 case VCVTPD2UQQZ128rrk:
16907 case VCVTPD2UQQZ128rrkz:
16908 case VCVTPD2UQQZ256rm:
16909 case VCVTPD2UQQZ256rmb:
16910 case VCVTPD2UQQZ256rmbk:
16911 case VCVTPD2UQQZ256rmbkz:
16912 case VCVTPD2UQQZ256rmk:
16913 case VCVTPD2UQQZ256rmkz:
16914 case VCVTPD2UQQZ256rr:
16915 case VCVTPD2UQQZ256rrk:
16916 case VCVTPD2UQQZ256rrkz:
16917 case VCVTPD2UQQZrm:
16918 case VCVTPD2UQQZrmb:
16919 case VCVTPD2UQQZrmbk:
16920 case VCVTPD2UQQZrmbkz:
16921 case VCVTPD2UQQZrmk:
16922 case VCVTPD2UQQZrmkz:
16923 case VCVTPD2UQQZrr:
16924 case VCVTPD2UQQZrrb:
16925 case VCVTPD2UQQZrrbk:
16926 case VCVTPD2UQQZrrbkz:
16927 case VCVTPD2UQQZrrk:
16928 case VCVTPD2UQQZrrkz:
16929 return true;
16930 }
16931 return false;
16932}
16933
16934bool isFCMOVB(unsigned Opcode) {
16935 return Opcode == CMOVB_F;
16936}
16937
16938bool isNOP(unsigned Opcode) {
16939 switch (Opcode) {
16940 case NOOP:
16941 case NOOPL:
16942 case NOOPLr:
16943 case NOOPQ:
16944 case NOOPQr:
16945 case NOOPW:
16946 case NOOPWr:
16947 return true;
16948 }
16949 return false;
16950}
16951
16952bool isVPABSQ(unsigned Opcode) {
16953 switch (Opcode) {
16954 case VPABSQZ128rm:
16955 case VPABSQZ128rmb:
16956 case VPABSQZ128rmbk:
16957 case VPABSQZ128rmbkz:
16958 case VPABSQZ128rmk:
16959 case VPABSQZ128rmkz:
16960 case VPABSQZ128rr:
16961 case VPABSQZ128rrk:
16962 case VPABSQZ128rrkz:
16963 case VPABSQZ256rm:
16964 case VPABSQZ256rmb:
16965 case VPABSQZ256rmbk:
16966 case VPABSQZ256rmbkz:
16967 case VPABSQZ256rmk:
16968 case VPABSQZ256rmkz:
16969 case VPABSQZ256rr:
16970 case VPABSQZ256rrk:
16971 case VPABSQZ256rrkz:
16972 case VPABSQZrm:
16973 case VPABSQZrmb:
16974 case VPABSQZrmbk:
16975 case VPABSQZrmbkz:
16976 case VPABSQZrmk:
16977 case VPABSQZrmkz:
16978 case VPABSQZrr:
16979 case VPABSQZrrk:
16980 case VPABSQZrrkz:
16981 return true;
16982 }
16983 return false;
16984}
16985
16986bool isVTESTPS(unsigned Opcode) {
16987 switch (Opcode) {
16988 case VTESTPSYrm:
16989 case VTESTPSYrr:
16990 case VTESTPSrm:
16991 case VTESTPSrr:
16992 return true;
16993 }
16994 return false;
16995}
16996
16997bool isPHSUBW(unsigned Opcode) {
16998 switch (Opcode) {
16999 case MMX_PHSUBWrm:
17000 case MMX_PHSUBWrr:
17001 case PHSUBWrm:
17002 case PHSUBWrr:
17003 return true;
17004 }
17005 return false;
17006}
17007
17008bool isPUSH2P(unsigned Opcode) {
17009 return Opcode == PUSH2P;
17010}
17011
17012bool isFISTTP(unsigned Opcode) {
17013 switch (Opcode) {
17014 case ISTT_FP16m:
17015 case ISTT_FP32m:
17016 case ISTT_FP64m:
17017 return true;
17018 }
17019 return false;
17020}
17021
17022bool isCFCMOVCC(unsigned Opcode) {
17023 switch (Opcode) {
17024 case CFCMOV16mr:
17025 case CFCMOV16rm:
17026 case CFCMOV16rm_ND:
17027 case CFCMOV16rr:
17028 case CFCMOV16rr_ND:
17029 case CFCMOV16rr_REV:
17030 case CFCMOV32mr:
17031 case CFCMOV32rm:
17032 case CFCMOV32rm_ND:
17033 case CFCMOV32rr:
17034 case CFCMOV32rr_ND:
17035 case CFCMOV32rr_REV:
17036 case CFCMOV64mr:
17037 case CFCMOV64rm:
17038 case CFCMOV64rm_ND:
17039 case CFCMOV64rr:
17040 case CFCMOV64rr_ND:
17041 case CFCMOV64rr_REV:
17042 return true;
17043 }
17044 return false;
17045}
17046
17047bool isVPINSRD(unsigned Opcode) {
17048 switch (Opcode) {
17049 case VPINSRDZrmi:
17050 case VPINSRDZrri:
17051 case VPINSRDrmi:
17052 case VPINSRDrri:
17053 return true;
17054 }
17055 return false;
17056}
17057
17058bool isPCMPESTRM(unsigned Opcode) {
17059 switch (Opcode) {
17060 case PCMPESTRMrmi:
17061 case PCMPESTRMrri:
17062 return true;
17063 }
17064 return false;
17065}
17066
17067bool isVFNMSUB213PS(unsigned Opcode) {
17068 switch (Opcode) {
17069 case VFNMSUB213PSYm:
17070 case VFNMSUB213PSYr:
17071 case VFNMSUB213PSZ128m:
17072 case VFNMSUB213PSZ128mb:
17073 case VFNMSUB213PSZ128mbk:
17074 case VFNMSUB213PSZ128mbkz:
17075 case VFNMSUB213PSZ128mk:
17076 case VFNMSUB213PSZ128mkz:
17077 case VFNMSUB213PSZ128r:
17078 case VFNMSUB213PSZ128rk:
17079 case VFNMSUB213PSZ128rkz:
17080 case VFNMSUB213PSZ256m:
17081 case VFNMSUB213PSZ256mb:
17082 case VFNMSUB213PSZ256mbk:
17083 case VFNMSUB213PSZ256mbkz:
17084 case VFNMSUB213PSZ256mk:
17085 case VFNMSUB213PSZ256mkz:
17086 case VFNMSUB213PSZ256r:
17087 case VFNMSUB213PSZ256rk:
17088 case VFNMSUB213PSZ256rkz:
17089 case VFNMSUB213PSZm:
17090 case VFNMSUB213PSZmb:
17091 case VFNMSUB213PSZmbk:
17092 case VFNMSUB213PSZmbkz:
17093 case VFNMSUB213PSZmk:
17094 case VFNMSUB213PSZmkz:
17095 case VFNMSUB213PSZr:
17096 case VFNMSUB213PSZrb:
17097 case VFNMSUB213PSZrbk:
17098 case VFNMSUB213PSZrbkz:
17099 case VFNMSUB213PSZrk:
17100 case VFNMSUB213PSZrkz:
17101 case VFNMSUB213PSm:
17102 case VFNMSUB213PSr:
17103 return true;
17104 }
17105 return false;
17106}
17107
17108bool isPHSUBD(unsigned Opcode) {
17109 switch (Opcode) {
17110 case MMX_PHSUBDrm:
17111 case MMX_PHSUBDrr:
17112 case PHSUBDrm:
17113 case PHSUBDrr:
17114 return true;
17115 }
17116 return false;
17117}
17118
17119bool isVCVTTPD2DQS(unsigned Opcode) {
17120 switch (Opcode) {
17121 case VCVTTPD2DQSZ128rm:
17122 case VCVTTPD2DQSZ128rmb:
17123 case VCVTTPD2DQSZ128rmbk:
17124 case VCVTTPD2DQSZ128rmbkz:
17125 case VCVTTPD2DQSZ128rmk:
17126 case VCVTTPD2DQSZ128rmkz:
17127 case VCVTTPD2DQSZ128rr:
17128 case VCVTTPD2DQSZ128rrk:
17129 case VCVTTPD2DQSZ128rrkz:
17130 case VCVTTPD2DQSZ256rm:
17131 case VCVTTPD2DQSZ256rmb:
17132 case VCVTTPD2DQSZ256rmbk:
17133 case VCVTTPD2DQSZ256rmbkz:
17134 case VCVTTPD2DQSZ256rmk:
17135 case VCVTTPD2DQSZ256rmkz:
17136 case VCVTTPD2DQSZ256rr:
17137 case VCVTTPD2DQSZ256rrb:
17138 case VCVTTPD2DQSZ256rrbk:
17139 case VCVTTPD2DQSZ256rrbkz:
17140 case VCVTTPD2DQSZ256rrk:
17141 case VCVTTPD2DQSZ256rrkz:
17142 case VCVTTPD2DQSZrm:
17143 case VCVTTPD2DQSZrmb:
17144 case VCVTTPD2DQSZrmbk:
17145 case VCVTTPD2DQSZrmbkz:
17146 case VCVTTPD2DQSZrmk:
17147 case VCVTTPD2DQSZrmkz:
17148 case VCVTTPD2DQSZrr:
17149 case VCVTTPD2DQSZrrb:
17150 case VCVTTPD2DQSZrrbk:
17151 case VCVTTPD2DQSZrrbkz:
17152 case VCVTTPD2DQSZrrk:
17153 case VCVTTPD2DQSZrrkz:
17154 return true;
17155 }
17156 return false;
17157}
17158
17159bool isSLDT(unsigned Opcode) {
17160 switch (Opcode) {
17161 case SLDT16m:
17162 case SLDT16r:
17163 case SLDT32r:
17164 case SLDT64r:
17165 return true;
17166 }
17167 return false;
17168}
17169
17170bool isVHADDPS(unsigned Opcode) {
17171 switch (Opcode) {
17172 case VHADDPSYrm:
17173 case VHADDPSYrr:
17174 case VHADDPSrm:
17175 case VHADDPSrr:
17176 return true;
17177 }
17178 return false;
17179}
17180
17181bool isVMOVNTDQ(unsigned Opcode) {
17182 switch (Opcode) {
17183 case VMOVNTDQYmr:
17184 case VMOVNTDQZ128mr:
17185 case VMOVNTDQZ256mr:
17186 case VMOVNTDQZmr:
17187 case VMOVNTDQmr:
17188 return true;
17189 }
17190 return false;
17191}
17192
17193bool isVPMINSD(unsigned Opcode) {
17194 switch (Opcode) {
17195 case VPMINSDYrm:
17196 case VPMINSDYrr:
17197 case VPMINSDZ128rm:
17198 case VPMINSDZ128rmb:
17199 case VPMINSDZ128rmbk:
17200 case VPMINSDZ128rmbkz:
17201 case VPMINSDZ128rmk:
17202 case VPMINSDZ128rmkz:
17203 case VPMINSDZ128rr:
17204 case VPMINSDZ128rrk:
17205 case VPMINSDZ128rrkz:
17206 case VPMINSDZ256rm:
17207 case VPMINSDZ256rmb:
17208 case VPMINSDZ256rmbk:
17209 case VPMINSDZ256rmbkz:
17210 case VPMINSDZ256rmk:
17211 case VPMINSDZ256rmkz:
17212 case VPMINSDZ256rr:
17213 case VPMINSDZ256rrk:
17214 case VPMINSDZ256rrkz:
17215 case VPMINSDZrm:
17216 case VPMINSDZrmb:
17217 case VPMINSDZrmbk:
17218 case VPMINSDZrmbkz:
17219 case VPMINSDZrmk:
17220 case VPMINSDZrmkz:
17221 case VPMINSDZrr:
17222 case VPMINSDZrrk:
17223 case VPMINSDZrrkz:
17224 case VPMINSDrm:
17225 case VPMINSDrr:
17226 return true;
17227 }
17228 return false;
17229}
17230
17231bool isVFRCZSD(unsigned Opcode) {
17232 switch (Opcode) {
17233 case VFRCZSDrm:
17234 case VFRCZSDrr:
17235 return true;
17236 }
17237 return false;
17238}
17239
17240bool isVPTESTMW(unsigned Opcode) {
17241 switch (Opcode) {
17242 case VPTESTMWZ128rm:
17243 case VPTESTMWZ128rmk:
17244 case VPTESTMWZ128rr:
17245 case VPTESTMWZ128rrk:
17246 case VPTESTMWZ256rm:
17247 case VPTESTMWZ256rmk:
17248 case VPTESTMWZ256rr:
17249 case VPTESTMWZ256rrk:
17250 case VPTESTMWZrm:
17251 case VPTESTMWZrmk:
17252 case VPTESTMWZrr:
17253 case VPTESTMWZrrk:
17254 return true;
17255 }
17256 return false;
17257}
17258
17259bool isVPMOVZXWD(unsigned Opcode) {
17260 switch (Opcode) {
17261 case VPMOVZXWDYrm:
17262 case VPMOVZXWDYrr:
17263 case VPMOVZXWDZ128rm:
17264 case VPMOVZXWDZ128rmk:
17265 case VPMOVZXWDZ128rmkz:
17266 case VPMOVZXWDZ128rr:
17267 case VPMOVZXWDZ128rrk:
17268 case VPMOVZXWDZ128rrkz:
17269 case VPMOVZXWDZ256rm:
17270 case VPMOVZXWDZ256rmk:
17271 case VPMOVZXWDZ256rmkz:
17272 case VPMOVZXWDZ256rr:
17273 case VPMOVZXWDZ256rrk:
17274 case VPMOVZXWDZ256rrkz:
17275 case VPMOVZXWDZrm:
17276 case VPMOVZXWDZrmk:
17277 case VPMOVZXWDZrmkz:
17278 case VPMOVZXWDZrr:
17279 case VPMOVZXWDZrrk:
17280 case VPMOVZXWDZrrkz:
17281 case VPMOVZXWDrm:
17282 case VPMOVZXWDrr:
17283 return true;
17284 }
17285 return false;
17286}
17287
17288bool isPSADBW(unsigned Opcode) {
17289 switch (Opcode) {
17290 case MMX_PSADBWrm:
17291 case MMX_PSADBWrr:
17292 case PSADBWrm:
17293 case PSADBWrr:
17294 return true;
17295 }
17296 return false;
17297}
17298
17299bool isVCVTSD2SI(unsigned Opcode) {
17300 switch (Opcode) {
17301 case VCVTSD2SI64Zrm_Int:
17302 case VCVTSD2SI64Zrr_Int:
17303 case VCVTSD2SI64Zrrb_Int:
17304 case VCVTSD2SI64rm_Int:
17305 case VCVTSD2SI64rr_Int:
17306 case VCVTSD2SIZrm_Int:
17307 case VCVTSD2SIZrr_Int:
17308 case VCVTSD2SIZrrb_Int:
17309 case VCVTSD2SIrm_Int:
17310 case VCVTSD2SIrr_Int:
17311 return true;
17312 }
17313 return false;
17314}
17315
17316bool isVMAXPH(unsigned Opcode) {
17317 switch (Opcode) {
17318 case VMAXPHZ128rm:
17319 case VMAXPHZ128rmb:
17320 case VMAXPHZ128rmbk:
17321 case VMAXPHZ128rmbkz:
17322 case VMAXPHZ128rmk:
17323 case VMAXPHZ128rmkz:
17324 case VMAXPHZ128rr:
17325 case VMAXPHZ128rrk:
17326 case VMAXPHZ128rrkz:
17327 case VMAXPHZ256rm:
17328 case VMAXPHZ256rmb:
17329 case VMAXPHZ256rmbk:
17330 case VMAXPHZ256rmbkz:
17331 case VMAXPHZ256rmk:
17332 case VMAXPHZ256rmkz:
17333 case VMAXPHZ256rr:
17334 case VMAXPHZ256rrk:
17335 case VMAXPHZ256rrkz:
17336 case VMAXPHZrm:
17337 case VMAXPHZrmb:
17338 case VMAXPHZrmbk:
17339 case VMAXPHZrmbkz:
17340 case VMAXPHZrmk:
17341 case VMAXPHZrmkz:
17342 case VMAXPHZrr:
17343 case VMAXPHZrrb:
17344 case VMAXPHZrrbk:
17345 case VMAXPHZrrbkz:
17346 case VMAXPHZrrk:
17347 case VMAXPHZrrkz:
17348 return true;
17349 }
17350 return false;
17351}
17352
17353bool isLODSB(unsigned Opcode) {
17354 return Opcode == LODSB;
17355}
17356
17357bool isPHMINPOSUW(unsigned Opcode) {
17358 switch (Opcode) {
17359 case PHMINPOSUWrm:
17360 case PHMINPOSUWrr:
17361 return true;
17362 }
17363 return false;
17364}
17365
17366bool isVPROLVD(unsigned Opcode) {
17367 switch (Opcode) {
17368 case VPROLVDZ128rm:
17369 case VPROLVDZ128rmb:
17370 case VPROLVDZ128rmbk:
17371 case VPROLVDZ128rmbkz:
17372 case VPROLVDZ128rmk:
17373 case VPROLVDZ128rmkz:
17374 case VPROLVDZ128rr:
17375 case VPROLVDZ128rrk:
17376 case VPROLVDZ128rrkz:
17377 case VPROLVDZ256rm:
17378 case VPROLVDZ256rmb:
17379 case VPROLVDZ256rmbk:
17380 case VPROLVDZ256rmbkz:
17381 case VPROLVDZ256rmk:
17382 case VPROLVDZ256rmkz:
17383 case VPROLVDZ256rr:
17384 case VPROLVDZ256rrk:
17385 case VPROLVDZ256rrkz:
17386 case VPROLVDZrm:
17387 case VPROLVDZrmb:
17388 case VPROLVDZrmbk:
17389 case VPROLVDZrmbkz:
17390 case VPROLVDZrmk:
17391 case VPROLVDZrmkz:
17392 case VPROLVDZrr:
17393 case VPROLVDZrrk:
17394 case VPROLVDZrrkz:
17395 return true;
17396 }
17397 return false;
17398}
17399
17400bool isWRFSBASE(unsigned Opcode) {
17401 switch (Opcode) {
17402 case WRFSBASE:
17403 case WRFSBASE64:
17404 return true;
17405 }
17406 return false;
17407}
17408
17409bool isVRSQRT14PS(unsigned Opcode) {
17410 switch (Opcode) {
17411 case VRSQRT14PSZ128m:
17412 case VRSQRT14PSZ128mb:
17413 case VRSQRT14PSZ128mbk:
17414 case VRSQRT14PSZ128mbkz:
17415 case VRSQRT14PSZ128mk:
17416 case VRSQRT14PSZ128mkz:
17417 case VRSQRT14PSZ128r:
17418 case VRSQRT14PSZ128rk:
17419 case VRSQRT14PSZ128rkz:
17420 case VRSQRT14PSZ256m:
17421 case VRSQRT14PSZ256mb:
17422 case VRSQRT14PSZ256mbk:
17423 case VRSQRT14PSZ256mbkz:
17424 case VRSQRT14PSZ256mk:
17425 case VRSQRT14PSZ256mkz:
17426 case VRSQRT14PSZ256r:
17427 case VRSQRT14PSZ256rk:
17428 case VRSQRT14PSZ256rkz:
17429 case VRSQRT14PSZm:
17430 case VRSQRT14PSZmb:
17431 case VRSQRT14PSZmbk:
17432 case VRSQRT14PSZmbkz:
17433 case VRSQRT14PSZmk:
17434 case VRSQRT14PSZmkz:
17435 case VRSQRT14PSZr:
17436 case VRSQRT14PSZrk:
17437 case VRSQRT14PSZrkz:
17438 return true;
17439 }
17440 return false;
17441}
17442
17443bool isVPHSUBDQ(unsigned Opcode) {
17444 switch (Opcode) {
17445 case VPHSUBDQrm:
17446 case VPHSUBDQrr:
17447 return true;
17448 }
17449 return false;
17450}
17451
17452bool isIRETD(unsigned Opcode) {
17453 return Opcode == IRET32;
17454}
17455
17456bool isVMOVRSD(unsigned Opcode) {
17457 switch (Opcode) {
17458 case VMOVRSDZ128m:
17459 case VMOVRSDZ128mk:
17460 case VMOVRSDZ128mkz:
17461 case VMOVRSDZ256m:
17462 case VMOVRSDZ256mk:
17463 case VMOVRSDZ256mkz:
17464 case VMOVRSDZm:
17465 case VMOVRSDZmk:
17466 case VMOVRSDZmkz:
17467 return true;
17468 }
17469 return false;
17470}
17471
17472bool isCVTSI2SS(unsigned Opcode) {
17473 switch (Opcode) {
17474 case CVTSI2SSrm_Int:
17475 case CVTSI2SSrr_Int:
17476 case CVTSI642SSrm_Int:
17477 case CVTSI642SSrr_Int:
17478 return true;
17479 }
17480 return false;
17481}
17482
17483bool isVPMULHRSW(unsigned Opcode) {
17484 switch (Opcode) {
17485 case VPMULHRSWYrm:
17486 case VPMULHRSWYrr:
17487 case VPMULHRSWZ128rm:
17488 case VPMULHRSWZ128rmk:
17489 case VPMULHRSWZ128rmkz:
17490 case VPMULHRSWZ128rr:
17491 case VPMULHRSWZ128rrk:
17492 case VPMULHRSWZ128rrkz:
17493 case VPMULHRSWZ256rm:
17494 case VPMULHRSWZ256rmk:
17495 case VPMULHRSWZ256rmkz:
17496 case VPMULHRSWZ256rr:
17497 case VPMULHRSWZ256rrk:
17498 case VPMULHRSWZ256rrkz:
17499 case VPMULHRSWZrm:
17500 case VPMULHRSWZrmk:
17501 case VPMULHRSWZrmkz:
17502 case VPMULHRSWZrr:
17503 case VPMULHRSWZrrk:
17504 case VPMULHRSWZrrkz:
17505 case VPMULHRSWrm:
17506 case VPMULHRSWrr:
17507 return true;
17508 }
17509 return false;
17510}
17511
17512bool isPI2FD(unsigned Opcode) {
17513 switch (Opcode) {
17514 case PI2FDrm:
17515 case PI2FDrr:
17516 return true;
17517 }
17518 return false;
17519}
17520
17521bool isGF2P8AFFINEQB(unsigned Opcode) {
17522 switch (Opcode) {
17523 case GF2P8AFFINEQBrmi:
17524 case GF2P8AFFINEQBrri:
17525 return true;
17526 }
17527 return false;
17528}
17529
17530bool isPAND(unsigned Opcode) {
17531 switch (Opcode) {
17532 case MMX_PANDrm:
17533 case MMX_PANDrr:
17534 case PANDrm:
17535 case PANDrr:
17536 return true;
17537 }
17538 return false;
17539}
17540
17541bool isVFNMSUB231SH(unsigned Opcode) {
17542 switch (Opcode) {
17543 case VFNMSUB231SHZm_Int:
17544 case VFNMSUB231SHZmk_Int:
17545 case VFNMSUB231SHZmkz_Int:
17546 case VFNMSUB231SHZr_Int:
17547 case VFNMSUB231SHZrb_Int:
17548 case VFNMSUB231SHZrbk_Int:
17549 case VFNMSUB231SHZrbkz_Int:
17550 case VFNMSUB231SHZrk_Int:
17551 case VFNMSUB231SHZrkz_Int:
17552 return true;
17553 }
17554 return false;
17555}
17556
17557bool isVCVTPH2BF8(unsigned Opcode) {
17558 switch (Opcode) {
17559 case VCVTPH2BF8Z128rm:
17560 case VCVTPH2BF8Z128rmb:
17561 case VCVTPH2BF8Z128rmbk:
17562 case VCVTPH2BF8Z128rmbkz:
17563 case VCVTPH2BF8Z128rmk:
17564 case VCVTPH2BF8Z128rmkz:
17565 case VCVTPH2BF8Z128rr:
17566 case VCVTPH2BF8Z128rrk:
17567 case VCVTPH2BF8Z128rrkz:
17568 case VCVTPH2BF8Z256rm:
17569 case VCVTPH2BF8Z256rmb:
17570 case VCVTPH2BF8Z256rmbk:
17571 case VCVTPH2BF8Z256rmbkz:
17572 case VCVTPH2BF8Z256rmk:
17573 case VCVTPH2BF8Z256rmkz:
17574 case VCVTPH2BF8Z256rr:
17575 case VCVTPH2BF8Z256rrk:
17576 case VCVTPH2BF8Z256rrkz:
17577 case VCVTPH2BF8Zrm:
17578 case VCVTPH2BF8Zrmb:
17579 case VCVTPH2BF8Zrmbk:
17580 case VCVTPH2BF8Zrmbkz:
17581 case VCVTPH2BF8Zrmk:
17582 case VCVTPH2BF8Zrmkz:
17583 case VCVTPH2BF8Zrr:
17584 case VCVTPH2BF8Zrrk:
17585 case VCVTPH2BF8Zrrkz:
17586 return true;
17587 }
17588 return false;
17589}
17590
17591bool isVMOVHLPS(unsigned Opcode) {
17592 switch (Opcode) {
17593 case VMOVHLPSZrr:
17594 case VMOVHLPSrr:
17595 return true;
17596 }
17597 return false;
17598}
17599
17600bool isPEXTRB(unsigned Opcode) {
17601 switch (Opcode) {
17602 case PEXTRBmri:
17603 case PEXTRBrri:
17604 return true;
17605 }
17606 return false;
17607}
17608
17609bool isVMMCALL(unsigned Opcode) {
17610 return Opcode == VMMCALL;
17611}
17612
17613bool isKNOTD(unsigned Opcode) {
17614 return Opcode == KNOTDkk;
17615}
17616
17617bool isVCVTSH2SS(unsigned Opcode) {
17618 switch (Opcode) {
17619 case VCVTSH2SSZrm_Int:
17620 case VCVTSH2SSZrmk_Int:
17621 case VCVTSH2SSZrmkz_Int:
17622 case VCVTSH2SSZrr_Int:
17623 case VCVTSH2SSZrrb_Int:
17624 case VCVTSH2SSZrrbk_Int:
17625 case VCVTSH2SSZrrbkz_Int:
17626 case VCVTSH2SSZrrk_Int:
17627 case VCVTSH2SSZrrkz_Int:
17628 return true;
17629 }
17630 return false;
17631}
17632
17633bool isVPUNPCKLQDQ(unsigned Opcode) {
17634 switch (Opcode) {
17635 case VPUNPCKLQDQYrm:
17636 case VPUNPCKLQDQYrr:
17637 case VPUNPCKLQDQZ128rm:
17638 case VPUNPCKLQDQZ128rmb:
17639 case VPUNPCKLQDQZ128rmbk:
17640 case VPUNPCKLQDQZ128rmbkz:
17641 case VPUNPCKLQDQZ128rmk:
17642 case VPUNPCKLQDQZ128rmkz:
17643 case VPUNPCKLQDQZ128rr:
17644 case VPUNPCKLQDQZ128rrk:
17645 case VPUNPCKLQDQZ128rrkz:
17646 case VPUNPCKLQDQZ256rm:
17647 case VPUNPCKLQDQZ256rmb:
17648 case VPUNPCKLQDQZ256rmbk:
17649 case VPUNPCKLQDQZ256rmbkz:
17650 case VPUNPCKLQDQZ256rmk:
17651 case VPUNPCKLQDQZ256rmkz:
17652 case VPUNPCKLQDQZ256rr:
17653 case VPUNPCKLQDQZ256rrk:
17654 case VPUNPCKLQDQZ256rrkz:
17655 case VPUNPCKLQDQZrm:
17656 case VPUNPCKLQDQZrmb:
17657 case VPUNPCKLQDQZrmbk:
17658 case VPUNPCKLQDQZrmbkz:
17659 case VPUNPCKLQDQZrmk:
17660 case VPUNPCKLQDQZrmkz:
17661 case VPUNPCKLQDQZrr:
17662 case VPUNPCKLQDQZrrk:
17663 case VPUNPCKLQDQZrrkz:
17664 case VPUNPCKLQDQrm:
17665 case VPUNPCKLQDQrr:
17666 return true;
17667 }
17668 return false;
17669}
17670
17671bool isVPERMIL2PS(unsigned Opcode) {
17672 switch (Opcode) {
17673 case VPERMIL2PSYmr:
17674 case VPERMIL2PSYrm:
17675 case VPERMIL2PSYrr:
17676 case VPERMIL2PSYrr_REV:
17677 case VPERMIL2PSmr:
17678 case VPERMIL2PSrm:
17679 case VPERMIL2PSrr:
17680 case VPERMIL2PSrr_REV:
17681 return true;
17682 }
17683 return false;
17684}
17685
17686bool isVPCMPGTD(unsigned Opcode) {
17687 switch (Opcode) {
17688 case VPCMPGTDYrm:
17689 case VPCMPGTDYrr:
17690 case VPCMPGTDZ128rm:
17691 case VPCMPGTDZ128rmb:
17692 case VPCMPGTDZ128rmbk:
17693 case VPCMPGTDZ128rmk:
17694 case VPCMPGTDZ128rr:
17695 case VPCMPGTDZ128rrk:
17696 case VPCMPGTDZ256rm:
17697 case VPCMPGTDZ256rmb:
17698 case VPCMPGTDZ256rmbk:
17699 case VPCMPGTDZ256rmk:
17700 case VPCMPGTDZ256rr:
17701 case VPCMPGTDZ256rrk:
17702 case VPCMPGTDZrm:
17703 case VPCMPGTDZrmb:
17704 case VPCMPGTDZrmbk:
17705 case VPCMPGTDZrmk:
17706 case VPCMPGTDZrr:
17707 case VPCMPGTDZrrk:
17708 case VPCMPGTDrm:
17709 case VPCMPGTDrr:
17710 return true;
17711 }
17712 return false;
17713}
17714
17715bool isCMPXCHG16B(unsigned Opcode) {
17716 return Opcode == CMPXCHG16B;
17717}
17718
17719bool isTDPHF8PS(unsigned Opcode) {
17720 return Opcode == TDPHF8PS;
17721}
17722
17723bool isVZEROUPPER(unsigned Opcode) {
17724 return Opcode == VZEROUPPER;
17725}
17726
17727bool isMOVAPS(unsigned Opcode) {
17728 switch (Opcode) {
17729 case MOVAPSmr:
17730 case MOVAPSrm:
17731 case MOVAPSrr:
17732 case MOVAPSrr_REV:
17733 return true;
17734 }
17735 return false;
17736}
17737
17738bool isVPCMPW(unsigned Opcode) {
17739 switch (Opcode) {
17740 case VPCMPWZ128rmi:
17741 case VPCMPWZ128rmik:
17742 case VPCMPWZ128rri:
17743 case VPCMPWZ128rrik:
17744 case VPCMPWZ256rmi:
17745 case VPCMPWZ256rmik:
17746 case VPCMPWZ256rri:
17747 case VPCMPWZ256rrik:
17748 case VPCMPWZrmi:
17749 case VPCMPWZrmik:
17750 case VPCMPWZrri:
17751 case VPCMPWZrrik:
17752 return true;
17753 }
17754 return false;
17755}
17756
17757bool isFUCOMPP(unsigned Opcode) {
17758 return Opcode == UCOM_FPPr;
17759}
17760
17761bool isXSETBV(unsigned Opcode) {
17762 return Opcode == XSETBV;
17763}
17764
17765bool isSLWPCB(unsigned Opcode) {
17766 switch (Opcode) {
17767 case SLWPCB:
17768 case SLWPCB64:
17769 return true;
17770 }
17771 return false;
17772}
17773
17774bool isSCASW(unsigned Opcode) {
17775 return Opcode == SCASW;
17776}
17777
17778bool isFCMOVNE(unsigned Opcode) {
17779 return Opcode == CMOVNE_F;
17780}
17781
17782bool isPBNDKB(unsigned Opcode) {
17783 return Opcode == PBNDKB;
17784}
17785
17786bool isVPMULLD(unsigned Opcode) {
17787 switch (Opcode) {
17788 case VPMULLDYrm:
17789 case VPMULLDYrr:
17790 case VPMULLDZ128rm:
17791 case VPMULLDZ128rmb:
17792 case VPMULLDZ128rmbk:
17793 case VPMULLDZ128rmbkz:
17794 case VPMULLDZ128rmk:
17795 case VPMULLDZ128rmkz:
17796 case VPMULLDZ128rr:
17797 case VPMULLDZ128rrk:
17798 case VPMULLDZ128rrkz:
17799 case VPMULLDZ256rm:
17800 case VPMULLDZ256rmb:
17801 case VPMULLDZ256rmbk:
17802 case VPMULLDZ256rmbkz:
17803 case VPMULLDZ256rmk:
17804 case VPMULLDZ256rmkz:
17805 case VPMULLDZ256rr:
17806 case VPMULLDZ256rrk:
17807 case VPMULLDZ256rrkz:
17808 case VPMULLDZrm:
17809 case VPMULLDZrmb:
17810 case VPMULLDZrmbk:
17811 case VPMULLDZrmbkz:
17812 case VPMULLDZrmk:
17813 case VPMULLDZrmkz:
17814 case VPMULLDZrr:
17815 case VPMULLDZrrk:
17816 case VPMULLDZrrkz:
17817 case VPMULLDrm:
17818 case VPMULLDrr:
17819 return true;
17820 }
17821 return false;
17822}
17823
17824bool isVP4DPWSSDS(unsigned Opcode) {
17825 switch (Opcode) {
17826 case VP4DPWSSDSrm:
17827 case VP4DPWSSDSrmk:
17828 case VP4DPWSSDSrmkz:
17829 return true;
17830 }
17831 return false;
17832}
17833
17834bool isVCVT2PH2HF8(unsigned Opcode) {
17835 switch (Opcode) {
17836 case VCVT2PH2HF8Z128rm:
17837 case VCVT2PH2HF8Z128rmb:
17838 case VCVT2PH2HF8Z128rmbk:
17839 case VCVT2PH2HF8Z128rmbkz:
17840 case VCVT2PH2HF8Z128rmk:
17841 case VCVT2PH2HF8Z128rmkz:
17842 case VCVT2PH2HF8Z128rr:
17843 case VCVT2PH2HF8Z128rrk:
17844 case VCVT2PH2HF8Z128rrkz:
17845 case VCVT2PH2HF8Z256rm:
17846 case VCVT2PH2HF8Z256rmb:
17847 case VCVT2PH2HF8Z256rmbk:
17848 case VCVT2PH2HF8Z256rmbkz:
17849 case VCVT2PH2HF8Z256rmk:
17850 case VCVT2PH2HF8Z256rmkz:
17851 case VCVT2PH2HF8Z256rr:
17852 case VCVT2PH2HF8Z256rrk:
17853 case VCVT2PH2HF8Z256rrkz:
17854 case VCVT2PH2HF8Zrm:
17855 case VCVT2PH2HF8Zrmb:
17856 case VCVT2PH2HF8Zrmbk:
17857 case VCVT2PH2HF8Zrmbkz:
17858 case VCVT2PH2HF8Zrmk:
17859 case VCVT2PH2HF8Zrmkz:
17860 case VCVT2PH2HF8Zrr:
17861 case VCVT2PH2HF8Zrrk:
17862 case VCVT2PH2HF8Zrrkz:
17863 return true;
17864 }
17865 return false;
17866}
17867
17868bool isPINSRW(unsigned Opcode) {
17869 switch (Opcode) {
17870 case MMX_PINSRWrmi:
17871 case MMX_PINSRWrri:
17872 case PINSRWrmi:
17873 case PINSRWrri:
17874 return true;
17875 }
17876 return false;
17877}
17878
17879bool isVCVTSI2SH(unsigned Opcode) {
17880 switch (Opcode) {
17881 case VCVTSI2SHZrm_Int:
17882 case VCVTSI2SHZrr_Int:
17883 case VCVTSI2SHZrrb_Int:
17884 case VCVTSI642SHZrm_Int:
17885 case VCVTSI642SHZrr_Int:
17886 case VCVTSI642SHZrrb_Int:
17887 return true;
17888 }
17889 return false;
17890}
17891
17892bool isVINSERTF32X8(unsigned Opcode) {
17893 switch (Opcode) {
17894 case VINSERTF32X8Zrmi:
17895 case VINSERTF32X8Zrmik:
17896 case VINSERTF32X8Zrmikz:
17897 case VINSERTF32X8Zrri:
17898 case VINSERTF32X8Zrrik:
17899 case VINSERTF32X8Zrrikz:
17900 return true;
17901 }
17902 return false;
17903}
17904
17905bool isKSHIFTLB(unsigned Opcode) {
17906 return Opcode == KSHIFTLBki;
17907}
17908
17909bool isSEAMOPS(unsigned Opcode) {
17910 return Opcode == SEAMOPS;
17911}
17912
17913bool isVPMULUDQ(unsigned Opcode) {
17914 switch (Opcode) {
17915 case VPMULUDQYrm:
17916 case VPMULUDQYrr:
17917 case VPMULUDQZ128rm:
17918 case VPMULUDQZ128rmb:
17919 case VPMULUDQZ128rmbk:
17920 case VPMULUDQZ128rmbkz:
17921 case VPMULUDQZ128rmk:
17922 case VPMULUDQZ128rmkz:
17923 case VPMULUDQZ128rr:
17924 case VPMULUDQZ128rrk:
17925 case VPMULUDQZ128rrkz:
17926 case VPMULUDQZ256rm:
17927 case VPMULUDQZ256rmb:
17928 case VPMULUDQZ256rmbk:
17929 case VPMULUDQZ256rmbkz:
17930 case VPMULUDQZ256rmk:
17931 case VPMULUDQZ256rmkz:
17932 case VPMULUDQZ256rr:
17933 case VPMULUDQZ256rrk:
17934 case VPMULUDQZ256rrkz:
17935 case VPMULUDQZrm:
17936 case VPMULUDQZrmb:
17937 case VPMULUDQZrmbk:
17938 case VPMULUDQZrmbkz:
17939 case VPMULUDQZrmk:
17940 case VPMULUDQZrmkz:
17941 case VPMULUDQZrr:
17942 case VPMULUDQZrrk:
17943 case VPMULUDQZrrkz:
17944 case VPMULUDQrm:
17945 case VPMULUDQrr:
17946 return true;
17947 }
17948 return false;
17949}
17950
17951bool isVPMOVSQB(unsigned Opcode) {
17952 switch (Opcode) {
17953 case VPMOVSQBZ128mr:
17954 case VPMOVSQBZ128mrk:
17955 case VPMOVSQBZ128rr:
17956 case VPMOVSQBZ128rrk:
17957 case VPMOVSQBZ128rrkz:
17958 case VPMOVSQBZ256mr:
17959 case VPMOVSQBZ256mrk:
17960 case VPMOVSQBZ256rr:
17961 case VPMOVSQBZ256rrk:
17962 case VPMOVSQBZ256rrkz:
17963 case VPMOVSQBZmr:
17964 case VPMOVSQBZmrk:
17965 case VPMOVSQBZrr:
17966 case VPMOVSQBZrrk:
17967 case VPMOVSQBZrrkz:
17968 return true;
17969 }
17970 return false;
17971}
17972
17973bool isVPTESTMD(unsigned Opcode) {
17974 switch (Opcode) {
17975 case VPTESTMDZ128rm:
17976 case VPTESTMDZ128rmb:
17977 case VPTESTMDZ128rmbk:
17978 case VPTESTMDZ128rmk:
17979 case VPTESTMDZ128rr:
17980 case VPTESTMDZ128rrk:
17981 case VPTESTMDZ256rm:
17982 case VPTESTMDZ256rmb:
17983 case VPTESTMDZ256rmbk:
17984 case VPTESTMDZ256rmk:
17985 case VPTESTMDZ256rr:
17986 case VPTESTMDZ256rrk:
17987 case VPTESTMDZrm:
17988 case VPTESTMDZrmb:
17989 case VPTESTMDZrmbk:
17990 case VPTESTMDZrmk:
17991 case VPTESTMDZrr:
17992 case VPTESTMDZrrk:
17993 return true;
17994 }
17995 return false;
17996}
17997
17998bool isVPHADDDQ(unsigned Opcode) {
17999 switch (Opcode) {
18000 case VPHADDDQrm:
18001 case VPHADDDQrr:
18002 return true;
18003 }
18004 return false;
18005}
18006
18007bool isKUNPCKDQ(unsigned Opcode) {
18008 return Opcode == KUNPCKDQkk;
18009}
18010
18011bool isT1MSKC(unsigned Opcode) {
18012 switch (Opcode) {
18013 case T1MSKC32rm:
18014 case T1MSKC32rr:
18015 case T1MSKC64rm:
18016 case T1MSKC64rr:
18017 return true;
18018 }
18019 return false;
18020}
18021
18022bool isVPCOMB(unsigned Opcode) {
18023 switch (Opcode) {
18024 case VPCOMBmi:
18025 case VPCOMBri:
18026 return true;
18027 }
18028 return false;
18029}
18030
18031bool isVBLENDPS(unsigned Opcode) {
18032 switch (Opcode) {
18033 case VBLENDPSYrmi:
18034 case VBLENDPSYrri:
18035 case VBLENDPSrmi:
18036 case VBLENDPSrri:
18037 return true;
18038 }
18039 return false;
18040}
18041
18042bool isPTWRITE(unsigned Opcode) {
18043 switch (Opcode) {
18044 case PTWRITE64m:
18045 case PTWRITE64r:
18046 case PTWRITEm:
18047 case PTWRITEr:
18048 return true;
18049 }
18050 return false;
18051}
18052
18053bool isVCVTPH2BF8S(unsigned Opcode) {
18054 switch (Opcode) {
18055 case VCVTPH2BF8SZ128rm:
18056 case VCVTPH2BF8SZ128rmb:
18057 case VCVTPH2BF8SZ128rmbk:
18058 case VCVTPH2BF8SZ128rmbkz:
18059 case VCVTPH2BF8SZ128rmk:
18060 case VCVTPH2BF8SZ128rmkz:
18061 case VCVTPH2BF8SZ128rr:
18062 case VCVTPH2BF8SZ128rrk:
18063 case VCVTPH2BF8SZ128rrkz:
18064 case VCVTPH2BF8SZ256rm:
18065 case VCVTPH2BF8SZ256rmb:
18066 case VCVTPH2BF8SZ256rmbk:
18067 case VCVTPH2BF8SZ256rmbkz:
18068 case VCVTPH2BF8SZ256rmk:
18069 case VCVTPH2BF8SZ256rmkz:
18070 case VCVTPH2BF8SZ256rr:
18071 case VCVTPH2BF8SZ256rrk:
18072 case VCVTPH2BF8SZ256rrkz:
18073 case VCVTPH2BF8SZrm:
18074 case VCVTPH2BF8SZrmb:
18075 case VCVTPH2BF8SZrmbk:
18076 case VCVTPH2BF8SZrmbkz:
18077 case VCVTPH2BF8SZrmk:
18078 case VCVTPH2BF8SZrmkz:
18079 case VCVTPH2BF8SZrr:
18080 case VCVTPH2BF8SZrrk:
18081 case VCVTPH2BF8SZrrkz:
18082 return true;
18083 }
18084 return false;
18085}
18086
18087bool isCVTPS2PI(unsigned Opcode) {
18088 switch (Opcode) {
18089 case MMX_CVTPS2PIrm:
18090 case MMX_CVTPS2PIrr:
18091 return true;
18092 }
18093 return false;
18094}
18095
18096bool isVPROTD(unsigned Opcode) {
18097 switch (Opcode) {
18098 case VPROTDmi:
18099 case VPROTDmr:
18100 case VPROTDri:
18101 case VPROTDrm:
18102 case VPROTDrr:
18103 case VPROTDrr_REV:
18104 return true;
18105 }
18106 return false;
18107}
18108
18109bool isCALL(unsigned Opcode) {
18110 switch (Opcode) {
18111 case CALL16m:
18112 case CALL16r:
18113 case CALL32m:
18114 case CALL32r:
18115 case CALL64m:
18116 case CALL64pcrel32:
18117 case CALL64r:
18118 case CALLpcrel16:
18119 case CALLpcrel32:
18120 case FARCALL32m:
18121 return true;
18122 }
18123 return false;
18124}
18125
18126bool isTILELOADDRST1(unsigned Opcode) {
18127 switch (Opcode) {
18128 case TILELOADDRST1:
18129 case TILELOADDRST1_EVEX:
18130 return true;
18131 }
18132 return false;
18133}
18134
18135bool isVPERMPS(unsigned Opcode) {
18136 switch (Opcode) {
18137 case VPERMPSYrm:
18138 case VPERMPSYrr:
18139 case VPERMPSZ256rm:
18140 case VPERMPSZ256rmb:
18141 case VPERMPSZ256rmbk:
18142 case VPERMPSZ256rmbkz:
18143 case VPERMPSZ256rmk:
18144 case VPERMPSZ256rmkz:
18145 case VPERMPSZ256rr:
18146 case VPERMPSZ256rrk:
18147 case VPERMPSZ256rrkz:
18148 case VPERMPSZrm:
18149 case VPERMPSZrmb:
18150 case VPERMPSZrmbk:
18151 case VPERMPSZrmbkz:
18152 case VPERMPSZrmk:
18153 case VPERMPSZrmkz:
18154 case VPERMPSZrr:
18155 case VPERMPSZrrk:
18156 case VPERMPSZrrkz:
18157 return true;
18158 }
18159 return false;
18160}
18161
18162bool isVPSHUFBITQMB(unsigned Opcode) {
18163 switch (Opcode) {
18164 case VPSHUFBITQMBZ128rm:
18165 case VPSHUFBITQMBZ128rmk:
18166 case VPSHUFBITQMBZ128rr:
18167 case VPSHUFBITQMBZ128rrk:
18168 case VPSHUFBITQMBZ256rm:
18169 case VPSHUFBITQMBZ256rmk:
18170 case VPSHUFBITQMBZ256rr:
18171 case VPSHUFBITQMBZ256rrk:
18172 case VPSHUFBITQMBZrm:
18173 case VPSHUFBITQMBZrmk:
18174 case VPSHUFBITQMBZrr:
18175 case VPSHUFBITQMBZrrk:
18176 return true;
18177 }
18178 return false;
18179}
18180
18181bool isVMOVSLDUP(unsigned Opcode) {
18182 switch (Opcode) {
18183 case VMOVSLDUPYrm:
18184 case VMOVSLDUPYrr:
18185 case VMOVSLDUPZ128rm:
18186 case VMOVSLDUPZ128rmk:
18187 case VMOVSLDUPZ128rmkz:
18188 case VMOVSLDUPZ128rr:
18189 case VMOVSLDUPZ128rrk:
18190 case VMOVSLDUPZ128rrkz:
18191 case VMOVSLDUPZ256rm:
18192 case VMOVSLDUPZ256rmk:
18193 case VMOVSLDUPZ256rmkz:
18194 case VMOVSLDUPZ256rr:
18195 case VMOVSLDUPZ256rrk:
18196 case VMOVSLDUPZ256rrkz:
18197 case VMOVSLDUPZrm:
18198 case VMOVSLDUPZrmk:
18199 case VMOVSLDUPZrmkz:
18200 case VMOVSLDUPZrr:
18201 case VMOVSLDUPZrrk:
18202 case VMOVSLDUPZrrkz:
18203 case VMOVSLDUPrm:
18204 case VMOVSLDUPrr:
18205 return true;
18206 }
18207 return false;
18208}
18209
18210bool isINVLPGA(unsigned Opcode) {
18211 switch (Opcode) {
18212 case INVLPGA32:
18213 case INVLPGA64:
18214 return true;
18215 }
18216 return false;
18217}
18218
18219bool isVCVTPH2QQ(unsigned Opcode) {
18220 switch (Opcode) {
18221 case VCVTPH2QQZ128rm:
18222 case VCVTPH2QQZ128rmb:
18223 case VCVTPH2QQZ128rmbk:
18224 case VCVTPH2QQZ128rmbkz:
18225 case VCVTPH2QQZ128rmk:
18226 case VCVTPH2QQZ128rmkz:
18227 case VCVTPH2QQZ128rr:
18228 case VCVTPH2QQZ128rrk:
18229 case VCVTPH2QQZ128rrkz:
18230 case VCVTPH2QQZ256rm:
18231 case VCVTPH2QQZ256rmb:
18232 case VCVTPH2QQZ256rmbk:
18233 case VCVTPH2QQZ256rmbkz:
18234 case VCVTPH2QQZ256rmk:
18235 case VCVTPH2QQZ256rmkz:
18236 case VCVTPH2QQZ256rr:
18237 case VCVTPH2QQZ256rrk:
18238 case VCVTPH2QQZ256rrkz:
18239 case VCVTPH2QQZrm:
18240 case VCVTPH2QQZrmb:
18241 case VCVTPH2QQZrmbk:
18242 case VCVTPH2QQZrmbkz:
18243 case VCVTPH2QQZrmk:
18244 case VCVTPH2QQZrmkz:
18245 case VCVTPH2QQZrr:
18246 case VCVTPH2QQZrrb:
18247 case VCVTPH2QQZrrbk:
18248 case VCVTPH2QQZrrbkz:
18249 case VCVTPH2QQZrrk:
18250 case VCVTPH2QQZrrkz:
18251 return true;
18252 }
18253 return false;
18254}
18255
18256bool isADD(unsigned Opcode) {
18257 switch (Opcode) {
18258 case ADD16i16:
18259 case ADD16mi:
18260 case ADD16mi8:
18261 case ADD16mi8_EVEX:
18262 case ADD16mi8_ND:
18263 case ADD16mi8_NF:
18264 case ADD16mi8_NF_ND:
18265 case ADD16mi_EVEX:
18266 case ADD16mi_ND:
18267 case ADD16mi_NF:
18268 case ADD16mi_NF_ND:
18269 case ADD16mr:
18270 case ADD16mr_EVEX:
18271 case ADD16mr_ND:
18272 case ADD16mr_NF:
18273 case ADD16mr_NF_ND:
18274 case ADD16ri:
18275 case ADD16ri8:
18276 case ADD16ri8_EVEX:
18277 case ADD16ri8_ND:
18278 case ADD16ri8_NF:
18279 case ADD16ri8_NF_ND:
18280 case ADD16ri_EVEX:
18281 case ADD16ri_ND:
18282 case ADD16ri_NF:
18283 case ADD16ri_NF_ND:
18284 case ADD16rm:
18285 case ADD16rm_EVEX:
18286 case ADD16rm_ND:
18287 case ADD16rm_NF:
18288 case ADD16rm_NF_ND:
18289 case ADD16rr:
18290 case ADD16rr_EVEX:
18291 case ADD16rr_EVEX_REV:
18292 case ADD16rr_ND:
18293 case ADD16rr_ND_REV:
18294 case ADD16rr_NF:
18295 case ADD16rr_NF_ND:
18296 case ADD16rr_NF_ND_REV:
18297 case ADD16rr_NF_REV:
18298 case ADD16rr_REV:
18299 case ADD32i32:
18300 case ADD32mi:
18301 case ADD32mi8:
18302 case ADD32mi8_EVEX:
18303 case ADD32mi8_ND:
18304 case ADD32mi8_NF:
18305 case ADD32mi8_NF_ND:
18306 case ADD32mi_EVEX:
18307 case ADD32mi_ND:
18308 case ADD32mi_NF:
18309 case ADD32mi_NF_ND:
18310 case ADD32mr:
18311 case ADD32mr_EVEX:
18312 case ADD32mr_ND:
18313 case ADD32mr_NF:
18314 case ADD32mr_NF_ND:
18315 case ADD32ri:
18316 case ADD32ri8:
18317 case ADD32ri8_EVEX:
18318 case ADD32ri8_ND:
18319 case ADD32ri8_NF:
18320 case ADD32ri8_NF_ND:
18321 case ADD32ri_EVEX:
18322 case ADD32ri_ND:
18323 case ADD32ri_NF:
18324 case ADD32ri_NF_ND:
18325 case ADD32rm:
18326 case ADD32rm_EVEX:
18327 case ADD32rm_ND:
18328 case ADD32rm_NF:
18329 case ADD32rm_NF_ND:
18330 case ADD32rr:
18331 case ADD32rr_EVEX:
18332 case ADD32rr_EVEX_REV:
18333 case ADD32rr_ND:
18334 case ADD32rr_ND_REV:
18335 case ADD32rr_NF:
18336 case ADD32rr_NF_ND:
18337 case ADD32rr_NF_ND_REV:
18338 case ADD32rr_NF_REV:
18339 case ADD32rr_REV:
18340 case ADD64i32:
18341 case ADD64mi32:
18342 case ADD64mi32_EVEX:
18343 case ADD64mi32_ND:
18344 case ADD64mi32_NF:
18345 case ADD64mi32_NF_ND:
18346 case ADD64mi8:
18347 case ADD64mi8_EVEX:
18348 case ADD64mi8_ND:
18349 case ADD64mi8_NF:
18350 case ADD64mi8_NF_ND:
18351 case ADD64mr:
18352 case ADD64mr_EVEX:
18353 case ADD64mr_ND:
18354 case ADD64mr_NF:
18355 case ADD64mr_NF_ND:
18356 case ADD64ri32:
18357 case ADD64ri32_EVEX:
18358 case ADD64ri32_ND:
18359 case ADD64ri32_NF:
18360 case ADD64ri32_NF_ND:
18361 case ADD64ri8:
18362 case ADD64ri8_EVEX:
18363 case ADD64ri8_ND:
18364 case ADD64ri8_NF:
18365 case ADD64ri8_NF_ND:
18366 case ADD64rm:
18367 case ADD64rm_EVEX:
18368 case ADD64rm_ND:
18369 case ADD64rm_NF:
18370 case ADD64rm_NF_ND:
18371 case ADD64rr:
18372 case ADD64rr_EVEX:
18373 case ADD64rr_EVEX_REV:
18374 case ADD64rr_ND:
18375 case ADD64rr_ND_REV:
18376 case ADD64rr_NF:
18377 case ADD64rr_NF_ND:
18378 case ADD64rr_NF_ND_REV:
18379 case ADD64rr_NF_REV:
18380 case ADD64rr_REV:
18381 case ADD8i8:
18382 case ADD8mi:
18383 case ADD8mi8:
18384 case ADD8mi_EVEX:
18385 case ADD8mi_ND:
18386 case ADD8mi_NF:
18387 case ADD8mi_NF_ND:
18388 case ADD8mr:
18389 case ADD8mr_EVEX:
18390 case ADD8mr_ND:
18391 case ADD8mr_NF:
18392 case ADD8mr_NF_ND:
18393 case ADD8ri:
18394 case ADD8ri8:
18395 case ADD8ri_EVEX:
18396 case ADD8ri_ND:
18397 case ADD8ri_NF:
18398 case ADD8ri_NF_ND:
18399 case ADD8rm:
18400 case ADD8rm_EVEX:
18401 case ADD8rm_ND:
18402 case ADD8rm_NF:
18403 case ADD8rm_NF_ND:
18404 case ADD8rr:
18405 case ADD8rr_EVEX:
18406 case ADD8rr_EVEX_REV:
18407 case ADD8rr_ND:
18408 case ADD8rr_ND_REV:
18409 case ADD8rr_NF:
18410 case ADD8rr_NF_ND:
18411 case ADD8rr_NF_ND_REV:
18412 case ADD8rr_NF_REV:
18413 case ADD8rr_REV:
18414 return true;
18415 }
18416 return false;
18417}
18418
18419bool isPSUBSW(unsigned Opcode) {
18420 switch (Opcode) {
18421 case MMX_PSUBSWrm:
18422 case MMX_PSUBSWrr:
18423 case PSUBSWrm:
18424 case PSUBSWrr:
18425 return true;
18426 }
18427 return false;
18428}
18429
18430bool isSIDTW(unsigned Opcode) {
18431 return Opcode == SIDT16m;
18432}
18433
18434bool isVFNMADD231PH(unsigned Opcode) {
18435 switch (Opcode) {
18436 case VFNMADD231PHZ128m:
18437 case VFNMADD231PHZ128mb:
18438 case VFNMADD231PHZ128mbk:
18439 case VFNMADD231PHZ128mbkz:
18440 case VFNMADD231PHZ128mk:
18441 case VFNMADD231PHZ128mkz:
18442 case VFNMADD231PHZ128r:
18443 case VFNMADD231PHZ128rk:
18444 case VFNMADD231PHZ128rkz:
18445 case VFNMADD231PHZ256m:
18446 case VFNMADD231PHZ256mb:
18447 case VFNMADD231PHZ256mbk:
18448 case VFNMADD231PHZ256mbkz:
18449 case VFNMADD231PHZ256mk:
18450 case VFNMADD231PHZ256mkz:
18451 case VFNMADD231PHZ256r:
18452 case VFNMADD231PHZ256rk:
18453 case VFNMADD231PHZ256rkz:
18454 case VFNMADD231PHZm:
18455 case VFNMADD231PHZmb:
18456 case VFNMADD231PHZmbk:
18457 case VFNMADD231PHZmbkz:
18458 case VFNMADD231PHZmk:
18459 case VFNMADD231PHZmkz:
18460 case VFNMADD231PHZr:
18461 case VFNMADD231PHZrb:
18462 case VFNMADD231PHZrbk:
18463 case VFNMADD231PHZrbkz:
18464 case VFNMADD231PHZrk:
18465 case VFNMADD231PHZrkz:
18466 return true;
18467 }
18468 return false;
18469}
18470
18471bool isVEXTRACTF64X2(unsigned Opcode) {
18472 switch (Opcode) {
18473 case VEXTRACTF64X2Z256mri:
18474 case VEXTRACTF64X2Z256mrik:
18475 case VEXTRACTF64X2Z256rri:
18476 case VEXTRACTF64X2Z256rrik:
18477 case VEXTRACTF64X2Z256rrikz:
18478 case VEXTRACTF64X2Zmri:
18479 case VEXTRACTF64X2Zmrik:
18480 case VEXTRACTF64X2Zrri:
18481 case VEXTRACTF64X2Zrrik:
18482 case VEXTRACTF64X2Zrrikz:
18483 return true;
18484 }
18485 return false;
18486}
18487
18488bool isFCOMI(unsigned Opcode) {
18489 return Opcode == COM_FIr;
18490}
18491
18492bool isRSM(unsigned Opcode) {
18493 return Opcode == RSM;
18494}
18495
18496bool isVPCOMUD(unsigned Opcode) {
18497 switch (Opcode) {
18498 case VPCOMUDmi:
18499 case VPCOMUDri:
18500 return true;
18501 }
18502 return false;
18503}
18504
18505bool isVPMOVZXBQ(unsigned Opcode) {
18506 switch (Opcode) {
18507 case VPMOVZXBQYrm:
18508 case VPMOVZXBQYrr:
18509 case VPMOVZXBQZ128rm:
18510 case VPMOVZXBQZ128rmk:
18511 case VPMOVZXBQZ128rmkz:
18512 case VPMOVZXBQZ128rr:
18513 case VPMOVZXBQZ128rrk:
18514 case VPMOVZXBQZ128rrkz:
18515 case VPMOVZXBQZ256rm:
18516 case VPMOVZXBQZ256rmk:
18517 case VPMOVZXBQZ256rmkz:
18518 case VPMOVZXBQZ256rr:
18519 case VPMOVZXBQZ256rrk:
18520 case VPMOVZXBQZ256rrkz:
18521 case VPMOVZXBQZrm:
18522 case VPMOVZXBQZrmk:
18523 case VPMOVZXBQZrmkz:
18524 case VPMOVZXBQZrr:
18525 case VPMOVZXBQZrrk:
18526 case VPMOVZXBQZrrkz:
18527 case VPMOVZXBQrm:
18528 case VPMOVZXBQrr:
18529 return true;
18530 }
18531 return false;
18532}
18533
18534bool isUWRMSR(unsigned Opcode) {
18535 switch (Opcode) {
18536 case UWRMSRir:
18537 case UWRMSRir_EVEX:
18538 case UWRMSRrr:
18539 case UWRMSRrr_EVEX:
18540 return true;
18541 }
18542 return false;
18543}
18544
18545bool isLGS(unsigned Opcode) {
18546 switch (Opcode) {
18547 case LGS16rm:
18548 case LGS32rm:
18549 case LGS64rm:
18550 return true;
18551 }
18552 return false;
18553}
18554
18555bool isVMOVNTPD(unsigned Opcode) {
18556 switch (Opcode) {
18557 case VMOVNTPDYmr:
18558 case VMOVNTPDZ128mr:
18559 case VMOVNTPDZ256mr:
18560 case VMOVNTPDZmr:
18561 case VMOVNTPDmr:
18562 return true;
18563 }
18564 return false;
18565}
18566
18567bool isRDPRU(unsigned Opcode) {
18568 return Opcode == RDPRU;
18569}
18570
18571bool isVPUNPCKHBW(unsigned Opcode) {
18572 switch (Opcode) {
18573 case VPUNPCKHBWYrm:
18574 case VPUNPCKHBWYrr:
18575 case VPUNPCKHBWZ128rm:
18576 case VPUNPCKHBWZ128rmk:
18577 case VPUNPCKHBWZ128rmkz:
18578 case VPUNPCKHBWZ128rr:
18579 case VPUNPCKHBWZ128rrk:
18580 case VPUNPCKHBWZ128rrkz:
18581 case VPUNPCKHBWZ256rm:
18582 case VPUNPCKHBWZ256rmk:
18583 case VPUNPCKHBWZ256rmkz:
18584 case VPUNPCKHBWZ256rr:
18585 case VPUNPCKHBWZ256rrk:
18586 case VPUNPCKHBWZ256rrkz:
18587 case VPUNPCKHBWZrm:
18588 case VPUNPCKHBWZrmk:
18589 case VPUNPCKHBWZrmkz:
18590 case VPUNPCKHBWZrr:
18591 case VPUNPCKHBWZrrk:
18592 case VPUNPCKHBWZrrkz:
18593 case VPUNPCKHBWrm:
18594 case VPUNPCKHBWrr:
18595 return true;
18596 }
18597 return false;
18598}
18599
18600bool isVUCOMXSD(unsigned Opcode) {
18601 switch (Opcode) {
18602 case VUCOMXSDZrm_Int:
18603 case VUCOMXSDZrr_Int:
18604 case VUCOMXSDZrrb_Int:
18605 return true;
18606 }
18607 return false;
18608}
18609
18610bool isANDN(unsigned Opcode) {
18611 switch (Opcode) {
18612 case ANDN32rm:
18613 case ANDN32rm_EVEX:
18614 case ANDN32rm_NF:
18615 case ANDN32rr:
18616 case ANDN32rr_EVEX:
18617 case ANDN32rr_NF:
18618 case ANDN64rm:
18619 case ANDN64rm_EVEX:
18620 case ANDN64rm_NF:
18621 case ANDN64rr:
18622 case ANDN64rr_EVEX:
18623 case ANDN64rr_NF:
18624 return true;
18625 }
18626 return false;
18627}
18628
18629bool isVCVTTPH2UW(unsigned Opcode) {
18630 switch (Opcode) {
18631 case VCVTTPH2UWZ128rm:
18632 case VCVTTPH2UWZ128rmb:
18633 case VCVTTPH2UWZ128rmbk:
18634 case VCVTTPH2UWZ128rmbkz:
18635 case VCVTTPH2UWZ128rmk:
18636 case VCVTTPH2UWZ128rmkz:
18637 case VCVTTPH2UWZ128rr:
18638 case VCVTTPH2UWZ128rrk:
18639 case VCVTTPH2UWZ128rrkz:
18640 case VCVTTPH2UWZ256rm:
18641 case VCVTTPH2UWZ256rmb:
18642 case VCVTTPH2UWZ256rmbk:
18643 case VCVTTPH2UWZ256rmbkz:
18644 case VCVTTPH2UWZ256rmk:
18645 case VCVTTPH2UWZ256rmkz:
18646 case VCVTTPH2UWZ256rr:
18647 case VCVTTPH2UWZ256rrk:
18648 case VCVTTPH2UWZ256rrkz:
18649 case VCVTTPH2UWZrm:
18650 case VCVTTPH2UWZrmb:
18651 case VCVTTPH2UWZrmbk:
18652 case VCVTTPH2UWZrmbkz:
18653 case VCVTTPH2UWZrmk:
18654 case VCVTTPH2UWZrmkz:
18655 case VCVTTPH2UWZrr:
18656 case VCVTTPH2UWZrrb:
18657 case VCVTTPH2UWZrrbk:
18658 case VCVTTPH2UWZrrbkz:
18659 case VCVTTPH2UWZrrk:
18660 case VCVTTPH2UWZrrkz:
18661 return true;
18662 }
18663 return false;
18664}
18665
18666bool isVMFUNC(unsigned Opcode) {
18667 return Opcode == VMFUNC;
18668}
18669
18670bool isFIMUL(unsigned Opcode) {
18671 switch (Opcode) {
18672 case MUL_FI16m:
18673 case MUL_FI32m:
18674 return true;
18675 }
18676 return false;
18677}
18678
18679bool isBLCFILL(unsigned Opcode) {
18680 switch (Opcode) {
18681 case BLCFILL32rm:
18682 case BLCFILL32rr:
18683 case BLCFILL64rm:
18684 case BLCFILL64rr:
18685 return true;
18686 }
18687 return false;
18688}
18689
18690bool isVGATHERPF0DPS(unsigned Opcode) {
18691 return Opcode == VGATHERPF0DPSm;
18692}
18693
18694bool isVFMSUBADD231PS(unsigned Opcode) {
18695 switch (Opcode) {
18696 case VFMSUBADD231PSYm:
18697 case VFMSUBADD231PSYr:
18698 case VFMSUBADD231PSZ128m:
18699 case VFMSUBADD231PSZ128mb:
18700 case VFMSUBADD231PSZ128mbk:
18701 case VFMSUBADD231PSZ128mbkz:
18702 case VFMSUBADD231PSZ128mk:
18703 case VFMSUBADD231PSZ128mkz:
18704 case VFMSUBADD231PSZ128r:
18705 case VFMSUBADD231PSZ128rk:
18706 case VFMSUBADD231PSZ128rkz:
18707 case VFMSUBADD231PSZ256m:
18708 case VFMSUBADD231PSZ256mb:
18709 case VFMSUBADD231PSZ256mbk:
18710 case VFMSUBADD231PSZ256mbkz:
18711 case VFMSUBADD231PSZ256mk:
18712 case VFMSUBADD231PSZ256mkz:
18713 case VFMSUBADD231PSZ256r:
18714 case VFMSUBADD231PSZ256rk:
18715 case VFMSUBADD231PSZ256rkz:
18716 case VFMSUBADD231PSZm:
18717 case VFMSUBADD231PSZmb:
18718 case VFMSUBADD231PSZmbk:
18719 case VFMSUBADD231PSZmbkz:
18720 case VFMSUBADD231PSZmk:
18721 case VFMSUBADD231PSZmkz:
18722 case VFMSUBADD231PSZr:
18723 case VFMSUBADD231PSZrb:
18724 case VFMSUBADD231PSZrbk:
18725 case VFMSUBADD231PSZrbkz:
18726 case VFMSUBADD231PSZrk:
18727 case VFMSUBADD231PSZrkz:
18728 case VFMSUBADD231PSm:
18729 case VFMSUBADD231PSr:
18730 return true;
18731 }
18732 return false;
18733}
18734
18735bool isVREDUCESD(unsigned Opcode) {
18736 switch (Opcode) {
18737 case VREDUCESDZrmi:
18738 case VREDUCESDZrmik:
18739 case VREDUCESDZrmikz:
18740 case VREDUCESDZrri:
18741 case VREDUCESDZrrib:
18742 case VREDUCESDZrribk:
18743 case VREDUCESDZrribkz:
18744 case VREDUCESDZrrik:
18745 case VREDUCESDZrrikz:
18746 return true;
18747 }
18748 return false;
18749}
18750
18751bool isVCOMXSH(unsigned Opcode) {
18752 switch (Opcode) {
18753 case VCOMXSHZrm_Int:
18754 case VCOMXSHZrr_Int:
18755 case VCOMXSHZrrb_Int:
18756 return true;
18757 }
18758 return false;
18759}
18760
18761bool isVXORPS(unsigned Opcode) {
18762 switch (Opcode) {
18763 case VXORPSYrm:
18764 case VXORPSYrr:
18765 case VXORPSZ128rm:
18766 case VXORPSZ128rmb:
18767 case VXORPSZ128rmbk:
18768 case VXORPSZ128rmbkz:
18769 case VXORPSZ128rmk:
18770 case VXORPSZ128rmkz:
18771 case VXORPSZ128rr:
18772 case VXORPSZ128rrk:
18773 case VXORPSZ128rrkz:
18774 case VXORPSZ256rm:
18775 case VXORPSZ256rmb:
18776 case VXORPSZ256rmbk:
18777 case VXORPSZ256rmbkz:
18778 case VXORPSZ256rmk:
18779 case VXORPSZ256rmkz:
18780 case VXORPSZ256rr:
18781 case VXORPSZ256rrk:
18782 case VXORPSZ256rrkz:
18783 case VXORPSZrm:
18784 case VXORPSZrmb:
18785 case VXORPSZrmbk:
18786 case VXORPSZrmbkz:
18787 case VXORPSZrmk:
18788 case VXORPSZrmkz:
18789 case VXORPSZrr:
18790 case VXORPSZrrk:
18791 case VXORPSZrrkz:
18792 case VXORPSrm:
18793 case VXORPSrr:
18794 return true;
18795 }
18796 return false;
18797}
18798
18799bool isPSWAPD(unsigned Opcode) {
18800 switch (Opcode) {
18801 case PSWAPDrm:
18802 case PSWAPDrr:
18803 return true;
18804 }
18805 return false;
18806}
18807
18808bool isPMAXSD(unsigned Opcode) {
18809 switch (Opcode) {
18810 case PMAXSDrm:
18811 case PMAXSDrr:
18812 return true;
18813 }
18814 return false;
18815}
18816
18817bool isVCMPSS(unsigned Opcode) {
18818 switch (Opcode) {
18819 case VCMPSSZrmi_Int:
18820 case VCMPSSZrmik_Int:
18821 case VCMPSSZrri_Int:
18822 case VCMPSSZrrib_Int:
18823 case VCMPSSZrribk_Int:
18824 case VCMPSSZrrik_Int:
18825 case VCMPSSrmi_Int:
18826 case VCMPSSrri_Int:
18827 return true;
18828 }
18829 return false;
18830}
18831
18832bool isEXTRACTPS(unsigned Opcode) {
18833 switch (Opcode) {
18834 case EXTRACTPSmri:
18835 case EXTRACTPSrri:
18836 return true;
18837 }
18838 return false;
18839}
18840
18841bool isVPMOVZXBD(unsigned Opcode) {
18842 switch (Opcode) {
18843 case VPMOVZXBDYrm:
18844 case VPMOVZXBDYrr:
18845 case VPMOVZXBDZ128rm:
18846 case VPMOVZXBDZ128rmk:
18847 case VPMOVZXBDZ128rmkz:
18848 case VPMOVZXBDZ128rr:
18849 case VPMOVZXBDZ128rrk:
18850 case VPMOVZXBDZ128rrkz:
18851 case VPMOVZXBDZ256rm:
18852 case VPMOVZXBDZ256rmk:
18853 case VPMOVZXBDZ256rmkz:
18854 case VPMOVZXBDZ256rr:
18855 case VPMOVZXBDZ256rrk:
18856 case VPMOVZXBDZ256rrkz:
18857 case VPMOVZXBDZrm:
18858 case VPMOVZXBDZrmk:
18859 case VPMOVZXBDZrmkz:
18860 case VPMOVZXBDZrr:
18861 case VPMOVZXBDZrrk:
18862 case VPMOVZXBDZrrkz:
18863 case VPMOVZXBDrm:
18864 case VPMOVZXBDrr:
18865 return true;
18866 }
18867 return false;
18868}
18869
18870bool isOUTSW(unsigned Opcode) {
18871 return Opcode == OUTSW;
18872}
18873
18874bool isKORTESTB(unsigned Opcode) {
18875 return Opcode == KORTESTBkk;
18876}
18877
18878bool isVREDUCEPS(unsigned Opcode) {
18879 switch (Opcode) {
18880 case VREDUCEPSZ128rmbi:
18881 case VREDUCEPSZ128rmbik:
18882 case VREDUCEPSZ128rmbikz:
18883 case VREDUCEPSZ128rmi:
18884 case VREDUCEPSZ128rmik:
18885 case VREDUCEPSZ128rmikz:
18886 case VREDUCEPSZ128rri:
18887 case VREDUCEPSZ128rrik:
18888 case VREDUCEPSZ128rrikz:
18889 case VREDUCEPSZ256rmbi:
18890 case VREDUCEPSZ256rmbik:
18891 case VREDUCEPSZ256rmbikz:
18892 case VREDUCEPSZ256rmi:
18893 case VREDUCEPSZ256rmik:
18894 case VREDUCEPSZ256rmikz:
18895 case VREDUCEPSZ256rri:
18896 case VREDUCEPSZ256rrik:
18897 case VREDUCEPSZ256rrikz:
18898 case VREDUCEPSZrmbi:
18899 case VREDUCEPSZrmbik:
18900 case VREDUCEPSZrmbikz:
18901 case VREDUCEPSZrmi:
18902 case VREDUCEPSZrmik:
18903 case VREDUCEPSZrmikz:
18904 case VREDUCEPSZrri:
18905 case VREDUCEPSZrrib:
18906 case VREDUCEPSZrribk:
18907 case VREDUCEPSZrribkz:
18908 case VREDUCEPSZrrik:
18909 case VREDUCEPSZrrikz:
18910 return true;
18911 }
18912 return false;
18913}
18914
18915bool isPEXTRW(unsigned Opcode) {
18916 switch (Opcode) {
18917 case MMX_PEXTRWrri:
18918 case PEXTRWmri:
18919 case PEXTRWrri:
18920 case PEXTRWrri_REV:
18921 return true;
18922 }
18923 return false;
18924}
18925
18926bool isFNINIT(unsigned Opcode) {
18927 return Opcode == FNINIT;
18928}
18929
18930bool isVCVTPH2IBS(unsigned Opcode) {
18931 switch (Opcode) {
18932 case VCVTPH2IBSZ128rm:
18933 case VCVTPH2IBSZ128rmb:
18934 case VCVTPH2IBSZ128rmbk:
18935 case VCVTPH2IBSZ128rmbkz:
18936 case VCVTPH2IBSZ128rmk:
18937 case VCVTPH2IBSZ128rmkz:
18938 case VCVTPH2IBSZ128rr:
18939 case VCVTPH2IBSZ128rrk:
18940 case VCVTPH2IBSZ128rrkz:
18941 case VCVTPH2IBSZ256rm:
18942 case VCVTPH2IBSZ256rmb:
18943 case VCVTPH2IBSZ256rmbk:
18944 case VCVTPH2IBSZ256rmbkz:
18945 case VCVTPH2IBSZ256rmk:
18946 case VCVTPH2IBSZ256rmkz:
18947 case VCVTPH2IBSZ256rr:
18948 case VCVTPH2IBSZ256rrk:
18949 case VCVTPH2IBSZ256rrkz:
18950 case VCVTPH2IBSZrm:
18951 case VCVTPH2IBSZrmb:
18952 case VCVTPH2IBSZrmbk:
18953 case VCVTPH2IBSZrmbkz:
18954 case VCVTPH2IBSZrmk:
18955 case VCVTPH2IBSZrmkz:
18956 case VCVTPH2IBSZrr:
18957 case VCVTPH2IBSZrrb:
18958 case VCVTPH2IBSZrrbk:
18959 case VCVTPH2IBSZrrbkz:
18960 case VCVTPH2IBSZrrk:
18961 case VCVTPH2IBSZrrkz:
18962 return true;
18963 }
18964 return false;
18965}
18966
18967bool isROL(unsigned Opcode) {
18968 switch (Opcode) {
18969 case ROL16m1:
18970 case ROL16m1_EVEX:
18971 case ROL16m1_ND:
18972 case ROL16m1_NF:
18973 case ROL16m1_NF_ND:
18974 case ROL16mCL:
18975 case ROL16mCL_EVEX:
18976 case ROL16mCL_ND:
18977 case ROL16mCL_NF:
18978 case ROL16mCL_NF_ND:
18979 case ROL16mi:
18980 case ROL16mi_EVEX:
18981 case ROL16mi_ND:
18982 case ROL16mi_NF:
18983 case ROL16mi_NF_ND:
18984 case ROL16r1:
18985 case ROL16r1_EVEX:
18986 case ROL16r1_ND:
18987 case ROL16r1_NF:
18988 case ROL16r1_NF_ND:
18989 case ROL16rCL:
18990 case ROL16rCL_EVEX:
18991 case ROL16rCL_ND:
18992 case ROL16rCL_NF:
18993 case ROL16rCL_NF_ND:
18994 case ROL16ri:
18995 case ROL16ri_EVEX:
18996 case ROL16ri_ND:
18997 case ROL16ri_NF:
18998 case ROL16ri_NF_ND:
18999 case ROL32m1:
19000 case ROL32m1_EVEX:
19001 case ROL32m1_ND:
19002 case ROL32m1_NF:
19003 case ROL32m1_NF_ND:
19004 case ROL32mCL:
19005 case ROL32mCL_EVEX:
19006 case ROL32mCL_ND:
19007 case ROL32mCL_NF:
19008 case ROL32mCL_NF_ND:
19009 case ROL32mi:
19010 case ROL32mi_EVEX:
19011 case ROL32mi_ND:
19012 case ROL32mi_NF:
19013 case ROL32mi_NF_ND:
19014 case ROL32r1:
19015 case ROL32r1_EVEX:
19016 case ROL32r1_ND:
19017 case ROL32r1_NF:
19018 case ROL32r1_NF_ND:
19019 case ROL32rCL:
19020 case ROL32rCL_EVEX:
19021 case ROL32rCL_ND:
19022 case ROL32rCL_NF:
19023 case ROL32rCL_NF_ND:
19024 case ROL32ri:
19025 case ROL32ri_EVEX:
19026 case ROL32ri_ND:
19027 case ROL32ri_NF:
19028 case ROL32ri_NF_ND:
19029 case ROL64m1:
19030 case ROL64m1_EVEX:
19031 case ROL64m1_ND:
19032 case ROL64m1_NF:
19033 case ROL64m1_NF_ND:
19034 case ROL64mCL:
19035 case ROL64mCL_EVEX:
19036 case ROL64mCL_ND:
19037 case ROL64mCL_NF:
19038 case ROL64mCL_NF_ND:
19039 case ROL64mi:
19040 case ROL64mi_EVEX:
19041 case ROL64mi_ND:
19042 case ROL64mi_NF:
19043 case ROL64mi_NF_ND:
19044 case ROL64r1:
19045 case ROL64r1_EVEX:
19046 case ROL64r1_ND:
19047 case ROL64r1_NF:
19048 case ROL64r1_NF_ND:
19049 case ROL64rCL:
19050 case ROL64rCL_EVEX:
19051 case ROL64rCL_ND:
19052 case ROL64rCL_NF:
19053 case ROL64rCL_NF_ND:
19054 case ROL64ri:
19055 case ROL64ri_EVEX:
19056 case ROL64ri_ND:
19057 case ROL64ri_NF:
19058 case ROL64ri_NF_ND:
19059 case ROL8m1:
19060 case ROL8m1_EVEX:
19061 case ROL8m1_ND:
19062 case ROL8m1_NF:
19063 case ROL8m1_NF_ND:
19064 case ROL8mCL:
19065 case ROL8mCL_EVEX:
19066 case ROL8mCL_ND:
19067 case ROL8mCL_NF:
19068 case ROL8mCL_NF_ND:
19069 case ROL8mi:
19070 case ROL8mi_EVEX:
19071 case ROL8mi_ND:
19072 case ROL8mi_NF:
19073 case ROL8mi_NF_ND:
19074 case ROL8r1:
19075 case ROL8r1_EVEX:
19076 case ROL8r1_ND:
19077 case ROL8r1_NF:
19078 case ROL8r1_NF_ND:
19079 case ROL8rCL:
19080 case ROL8rCL_EVEX:
19081 case ROL8rCL_ND:
19082 case ROL8rCL_NF:
19083 case ROL8rCL_NF_ND:
19084 case ROL8ri:
19085 case ROL8ri_EVEX:
19086 case ROL8ri_ND:
19087 case ROL8ri_NF:
19088 case ROL8ri_NF_ND:
19089 return true;
19090 }
19091 return false;
19092}
19093
19094bool isVCVTPS2QQ(unsigned Opcode) {
19095 switch (Opcode) {
19096 case VCVTPS2QQZ128rm:
19097 case VCVTPS2QQZ128rmb:
19098 case VCVTPS2QQZ128rmbk:
19099 case VCVTPS2QQZ128rmbkz:
19100 case VCVTPS2QQZ128rmk:
19101 case VCVTPS2QQZ128rmkz:
19102 case VCVTPS2QQZ128rr:
19103 case VCVTPS2QQZ128rrk:
19104 case VCVTPS2QQZ128rrkz:
19105 case VCVTPS2QQZ256rm:
19106 case VCVTPS2QQZ256rmb:
19107 case VCVTPS2QQZ256rmbk:
19108 case VCVTPS2QQZ256rmbkz:
19109 case VCVTPS2QQZ256rmk:
19110 case VCVTPS2QQZ256rmkz:
19111 case VCVTPS2QQZ256rr:
19112 case VCVTPS2QQZ256rrk:
19113 case VCVTPS2QQZ256rrkz:
19114 case VCVTPS2QQZrm:
19115 case VCVTPS2QQZrmb:
19116 case VCVTPS2QQZrmbk:
19117 case VCVTPS2QQZrmbkz:
19118 case VCVTPS2QQZrmk:
19119 case VCVTPS2QQZrmkz:
19120 case VCVTPS2QQZrr:
19121 case VCVTPS2QQZrrb:
19122 case VCVTPS2QQZrrbk:
19123 case VCVTPS2QQZrrbkz:
19124 case VCVTPS2QQZrrk:
19125 case VCVTPS2QQZrrkz:
19126 return true;
19127 }
19128 return false;
19129}
19130
19131bool isVGETMANTPH(unsigned Opcode) {
19132 switch (Opcode) {
19133 case VGETMANTPHZ128rmbi:
19134 case VGETMANTPHZ128rmbik:
19135 case VGETMANTPHZ128rmbikz:
19136 case VGETMANTPHZ128rmi:
19137 case VGETMANTPHZ128rmik:
19138 case VGETMANTPHZ128rmikz:
19139 case VGETMANTPHZ128rri:
19140 case VGETMANTPHZ128rrik:
19141 case VGETMANTPHZ128rrikz:
19142 case VGETMANTPHZ256rmbi:
19143 case VGETMANTPHZ256rmbik:
19144 case VGETMANTPHZ256rmbikz:
19145 case VGETMANTPHZ256rmi:
19146 case VGETMANTPHZ256rmik:
19147 case VGETMANTPHZ256rmikz:
19148 case VGETMANTPHZ256rri:
19149 case VGETMANTPHZ256rrik:
19150 case VGETMANTPHZ256rrikz:
19151 case VGETMANTPHZrmbi:
19152 case VGETMANTPHZrmbik:
19153 case VGETMANTPHZrmbikz:
19154 case VGETMANTPHZrmi:
19155 case VGETMANTPHZrmik:
19156 case VGETMANTPHZrmikz:
19157 case VGETMANTPHZrri:
19158 case VGETMANTPHZrrib:
19159 case VGETMANTPHZrribk:
19160 case VGETMANTPHZrribkz:
19161 case VGETMANTPHZrrik:
19162 case VGETMANTPHZrrikz:
19163 return true;
19164 }
19165 return false;
19166}
19167
19168bool isPUNPCKLDQ(unsigned Opcode) {
19169 switch (Opcode) {
19170 case MMX_PUNPCKLDQrm:
19171 case MMX_PUNPCKLDQrr:
19172 case PUNPCKLDQrm:
19173 case PUNPCKLDQrr:
19174 return true;
19175 }
19176 return false;
19177}
19178
19179bool isPADDD(unsigned Opcode) {
19180 switch (Opcode) {
19181 case MMX_PADDDrm:
19182 case MMX_PADDDrr:
19183 case PADDDrm:
19184 case PADDDrr:
19185 return true;
19186 }
19187 return false;
19188}
19189
19190bool isVPSLLD(unsigned Opcode) {
19191 switch (Opcode) {
19192 case VPSLLDYri:
19193 case VPSLLDYrm:
19194 case VPSLLDYrr:
19195 case VPSLLDZ128mbi:
19196 case VPSLLDZ128mbik:
19197 case VPSLLDZ128mbikz:
19198 case VPSLLDZ128mi:
19199 case VPSLLDZ128mik:
19200 case VPSLLDZ128mikz:
19201 case VPSLLDZ128ri:
19202 case VPSLLDZ128rik:
19203 case VPSLLDZ128rikz:
19204 case VPSLLDZ128rm:
19205 case VPSLLDZ128rmk:
19206 case VPSLLDZ128rmkz:
19207 case VPSLLDZ128rr:
19208 case VPSLLDZ128rrk:
19209 case VPSLLDZ128rrkz:
19210 case VPSLLDZ256mbi:
19211 case VPSLLDZ256mbik:
19212 case VPSLLDZ256mbikz:
19213 case VPSLLDZ256mi:
19214 case VPSLLDZ256mik:
19215 case VPSLLDZ256mikz:
19216 case VPSLLDZ256ri:
19217 case VPSLLDZ256rik:
19218 case VPSLLDZ256rikz:
19219 case VPSLLDZ256rm:
19220 case VPSLLDZ256rmk:
19221 case VPSLLDZ256rmkz:
19222 case VPSLLDZ256rr:
19223 case VPSLLDZ256rrk:
19224 case VPSLLDZ256rrkz:
19225 case VPSLLDZmbi:
19226 case VPSLLDZmbik:
19227 case VPSLLDZmbikz:
19228 case VPSLLDZmi:
19229 case VPSLLDZmik:
19230 case VPSLLDZmikz:
19231 case VPSLLDZri:
19232 case VPSLLDZrik:
19233 case VPSLLDZrikz:
19234 case VPSLLDZrm:
19235 case VPSLLDZrmk:
19236 case VPSLLDZrmkz:
19237 case VPSLLDZrr:
19238 case VPSLLDZrrk:
19239 case VPSLLDZrrkz:
19240 case VPSLLDri:
19241 case VPSLLDrm:
19242 case VPSLLDrr:
19243 return true;
19244 }
19245 return false;
19246}
19247
19248bool isPFCMPGE(unsigned Opcode) {
19249 switch (Opcode) {
19250 case PFCMPGErm:
19251 case PFCMPGErr:
19252 return true;
19253 }
19254 return false;
19255}
19256
19257bool isVGETMANTBF16(unsigned Opcode) {
19258 switch (Opcode) {
19259 case VGETMANTBF16Z128rmbi:
19260 case VGETMANTBF16Z128rmbik:
19261 case VGETMANTBF16Z128rmbikz:
19262 case VGETMANTBF16Z128rmi:
19263 case VGETMANTBF16Z128rmik:
19264 case VGETMANTBF16Z128rmikz:
19265 case VGETMANTBF16Z128rri:
19266 case VGETMANTBF16Z128rrik:
19267 case VGETMANTBF16Z128rrikz:
19268 case VGETMANTBF16Z256rmbi:
19269 case VGETMANTBF16Z256rmbik:
19270 case VGETMANTBF16Z256rmbikz:
19271 case VGETMANTBF16Z256rmi:
19272 case VGETMANTBF16Z256rmik:
19273 case VGETMANTBF16Z256rmikz:
19274 case VGETMANTBF16Z256rri:
19275 case VGETMANTBF16Z256rrik:
19276 case VGETMANTBF16Z256rrikz:
19277 case VGETMANTBF16Zrmbi:
19278 case VGETMANTBF16Zrmbik:
19279 case VGETMANTBF16Zrmbikz:
19280 case VGETMANTBF16Zrmi:
19281 case VGETMANTBF16Zrmik:
19282 case VGETMANTBF16Zrmikz:
19283 case VGETMANTBF16Zrri:
19284 case VGETMANTBF16Zrrik:
19285 case VGETMANTBF16Zrrikz:
19286 return true;
19287 }
19288 return false;
19289}
19290
19291bool isVSUBBF16(unsigned Opcode) {
19292 switch (Opcode) {
19293 case VSUBBF16Z128rm:
19294 case VSUBBF16Z128rmb:
19295 case VSUBBF16Z128rmbk:
19296 case VSUBBF16Z128rmbkz:
19297 case VSUBBF16Z128rmk:
19298 case VSUBBF16Z128rmkz:
19299 case VSUBBF16Z128rr:
19300 case VSUBBF16Z128rrk:
19301 case VSUBBF16Z128rrkz:
19302 case VSUBBF16Z256rm:
19303 case VSUBBF16Z256rmb:
19304 case VSUBBF16Z256rmbk:
19305 case VSUBBF16Z256rmbkz:
19306 case VSUBBF16Z256rmk:
19307 case VSUBBF16Z256rmkz:
19308 case VSUBBF16Z256rr:
19309 case VSUBBF16Z256rrk:
19310 case VSUBBF16Z256rrkz:
19311 case VSUBBF16Zrm:
19312 case VSUBBF16Zrmb:
19313 case VSUBBF16Zrmbk:
19314 case VSUBBF16Zrmbkz:
19315 case VSUBBF16Zrmk:
19316 case VSUBBF16Zrmkz:
19317 case VSUBBF16Zrr:
19318 case VSUBBF16Zrrk:
19319 case VSUBBF16Zrrkz:
19320 return true;
19321 }
19322 return false;
19323}
19324
19325bool isVPMOVM2D(unsigned Opcode) {
19326 switch (Opcode) {
19327 case VPMOVM2DZ128rk:
19328 case VPMOVM2DZ256rk:
19329 case VPMOVM2DZrk:
19330 return true;
19331 }
19332 return false;
19333}
19334
19335bool isVCVTTSS2USIS(unsigned Opcode) {
19336 switch (Opcode) {
19337 case VCVTTSS2USI64Srm_Int:
19338 case VCVTTSS2USI64Srr_Int:
19339 case VCVTTSS2USI64Srrb_Int:
19340 case VCVTTSS2USISrm_Int:
19341 case VCVTTSS2USISrr_Int:
19342 case VCVTTSS2USISrrb_Int:
19343 return true;
19344 }
19345 return false;
19346}
19347
19348bool isVHSUBPS(unsigned Opcode) {
19349 switch (Opcode) {
19350 case VHSUBPSYrm:
19351 case VHSUBPSYrr:
19352 case VHSUBPSrm:
19353 case VHSUBPSrr:
19354 return true;
19355 }
19356 return false;
19357}
19358
19359bool isENDBR32(unsigned Opcode) {
19360 return Opcode == ENDBR32;
19361}
19362
19363bool isMOVSXD(unsigned Opcode) {
19364 switch (Opcode) {
19365 case MOVSX16rm32:
19366 case MOVSX16rr32:
19367 case MOVSX32rm32:
19368 case MOVSX32rr32:
19369 case MOVSX64rm32:
19370 case MOVSX64rr32:
19371 return true;
19372 }
19373 return false;
19374}
19375
19376bool isPSIGND(unsigned Opcode) {
19377 switch (Opcode) {
19378 case MMX_PSIGNDrm:
19379 case MMX_PSIGNDrr:
19380 case PSIGNDrm:
19381 case PSIGNDrr:
19382 return true;
19383 }
19384 return false;
19385}
19386
19387bool isVPTEST(unsigned Opcode) {
19388 switch (Opcode) {
19389 case VPTESTYrm:
19390 case VPTESTYrr:
19391 case VPTESTrm:
19392 case VPTESTrr:
19393 return true;
19394 }
19395 return false;
19396}
19397
19398bool isVPDPWUSD(unsigned Opcode) {
19399 switch (Opcode) {
19400 case VPDPWUSDYrm:
19401 case VPDPWUSDYrr:
19402 case VPDPWUSDZ128rm:
19403 case VPDPWUSDZ128rmb:
19404 case VPDPWUSDZ128rmbk:
19405 case VPDPWUSDZ128rmbkz:
19406 case VPDPWUSDZ128rmk:
19407 case VPDPWUSDZ128rmkz:
19408 case VPDPWUSDZ128rr:
19409 case VPDPWUSDZ128rrk:
19410 case VPDPWUSDZ128rrkz:
19411 case VPDPWUSDZ256rm:
19412 case VPDPWUSDZ256rmb:
19413 case VPDPWUSDZ256rmbk:
19414 case VPDPWUSDZ256rmbkz:
19415 case VPDPWUSDZ256rmk:
19416 case VPDPWUSDZ256rmkz:
19417 case VPDPWUSDZ256rr:
19418 case VPDPWUSDZ256rrk:
19419 case VPDPWUSDZ256rrkz:
19420 case VPDPWUSDZrm:
19421 case VPDPWUSDZrmb:
19422 case VPDPWUSDZrmbk:
19423 case VPDPWUSDZrmbkz:
19424 case VPDPWUSDZrmk:
19425 case VPDPWUSDZrmkz:
19426 case VPDPWUSDZrr:
19427 case VPDPWUSDZrrk:
19428 case VPDPWUSDZrrkz:
19429 case VPDPWUSDrm:
19430 case VPDPWUSDrr:
19431 return true;
19432 }
19433 return false;
19434}
19435
19436bool isHSUBPD(unsigned Opcode) {
19437 switch (Opcode) {
19438 case HSUBPDrm:
19439 case HSUBPDrr:
19440 return true;
19441 }
19442 return false;
19443}
19444
19445bool isADCX(unsigned Opcode) {
19446 switch (Opcode) {
19447 case ADCX32rm:
19448 case ADCX32rm_EVEX:
19449 case ADCX32rm_ND:
19450 case ADCX32rr:
19451 case ADCX32rr_EVEX:
19452 case ADCX32rr_ND:
19453 case ADCX64rm:
19454 case ADCX64rm_EVEX:
19455 case ADCX64rm_ND:
19456 case ADCX64rr:
19457 case ADCX64rr_EVEX:
19458 case ADCX64rr_ND:
19459 return true;
19460 }
19461 return false;
19462}
19463
19464bool isCVTTPD2PI(unsigned Opcode) {
19465 switch (Opcode) {
19466 case MMX_CVTTPD2PIrm:
19467 case MMX_CVTTPD2PIrr:
19468 return true;
19469 }
19470 return false;
19471}
19472
19473bool isPDEP(unsigned Opcode) {
19474 switch (Opcode) {
19475 case PDEP32rm:
19476 case PDEP32rm_EVEX:
19477 case PDEP32rr:
19478 case PDEP32rr_EVEX:
19479 case PDEP64rm:
19480 case PDEP64rm_EVEX:
19481 case PDEP64rr:
19482 case PDEP64rr_EVEX:
19483 return true;
19484 }
19485 return false;
19486}
19487
19488bool isTDPBUSD(unsigned Opcode) {
19489 return Opcode == TDPBUSD;
19490}
19491
19492bool isVCVTBIASPH2HF8S(unsigned Opcode) {
19493 switch (Opcode) {
19494 case VCVTBIASPH2HF8SZ128rm:
19495 case VCVTBIASPH2HF8SZ128rmb:
19496 case VCVTBIASPH2HF8SZ128rmbk:
19497 case VCVTBIASPH2HF8SZ128rmbkz:
19498 case VCVTBIASPH2HF8SZ128rmk:
19499 case VCVTBIASPH2HF8SZ128rmkz:
19500 case VCVTBIASPH2HF8SZ128rr:
19501 case VCVTBIASPH2HF8SZ128rrk:
19502 case VCVTBIASPH2HF8SZ128rrkz:
19503 case VCVTBIASPH2HF8SZ256rm:
19504 case VCVTBIASPH2HF8SZ256rmb:
19505 case VCVTBIASPH2HF8SZ256rmbk:
19506 case VCVTBIASPH2HF8SZ256rmbkz:
19507 case VCVTBIASPH2HF8SZ256rmk:
19508 case VCVTBIASPH2HF8SZ256rmkz:
19509 case VCVTBIASPH2HF8SZ256rr:
19510 case VCVTBIASPH2HF8SZ256rrk:
19511 case VCVTBIASPH2HF8SZ256rrkz:
19512 case VCVTBIASPH2HF8SZrm:
19513 case VCVTBIASPH2HF8SZrmb:
19514 case VCVTBIASPH2HF8SZrmbk:
19515 case VCVTBIASPH2HF8SZrmbkz:
19516 case VCVTBIASPH2HF8SZrmk:
19517 case VCVTBIASPH2HF8SZrmkz:
19518 case VCVTBIASPH2HF8SZrr:
19519 case VCVTBIASPH2HF8SZrrk:
19520 case VCVTBIASPH2HF8SZrrkz:
19521 return true;
19522 }
19523 return false;
19524}
19525
19526bool isVBROADCASTI32X4(unsigned Opcode) {
19527 switch (Opcode) {
19528 case VBROADCASTI32X4Z256rm:
19529 case VBROADCASTI32X4Z256rmk:
19530 case VBROADCASTI32X4Z256rmkz:
19531 case VBROADCASTI32X4Zrm:
19532 case VBROADCASTI32X4Zrmk:
19533 case VBROADCASTI32X4Zrmkz:
19534 return true;
19535 }
19536 return false;
19537}
19538
19539bool isVCVTPH2UDQ(unsigned Opcode) {
19540 switch (Opcode) {
19541 case VCVTPH2UDQZ128rm:
19542 case VCVTPH2UDQZ128rmb:
19543 case VCVTPH2UDQZ128rmbk:
19544 case VCVTPH2UDQZ128rmbkz:
19545 case VCVTPH2UDQZ128rmk:
19546 case VCVTPH2UDQZ128rmkz:
19547 case VCVTPH2UDQZ128rr:
19548 case VCVTPH2UDQZ128rrk:
19549 case VCVTPH2UDQZ128rrkz:
19550 case VCVTPH2UDQZ256rm:
19551 case VCVTPH2UDQZ256rmb:
19552 case VCVTPH2UDQZ256rmbk:
19553 case VCVTPH2UDQZ256rmbkz:
19554 case VCVTPH2UDQZ256rmk:
19555 case VCVTPH2UDQZ256rmkz:
19556 case VCVTPH2UDQZ256rr:
19557 case VCVTPH2UDQZ256rrk:
19558 case VCVTPH2UDQZ256rrkz:
19559 case VCVTPH2UDQZrm:
19560 case VCVTPH2UDQZrmb:
19561 case VCVTPH2UDQZrmbk:
19562 case VCVTPH2UDQZrmbkz:
19563 case VCVTPH2UDQZrmk:
19564 case VCVTPH2UDQZrmkz:
19565 case VCVTPH2UDQZrr:
19566 case VCVTPH2UDQZrrb:
19567 case VCVTPH2UDQZrrbk:
19568 case VCVTPH2UDQZrrbkz:
19569 case VCVTPH2UDQZrrk:
19570 case VCVTPH2UDQZrrkz:
19571 return true;
19572 }
19573 return false;
19574}
19575
19576bool isVPHADDW(unsigned Opcode) {
19577 switch (Opcode) {
19578 case VPHADDWYrm:
19579 case VPHADDWYrr:
19580 case VPHADDWrm:
19581 case VPHADDWrr:
19582 return true;
19583 }
19584 return false;
19585}
19586
19587bool isFLDL2E(unsigned Opcode) {
19588 return Opcode == FLDL2E;
19589}
19590
19591bool isCLZERO(unsigned Opcode) {
19592 switch (Opcode) {
19593 case CLZERO32r:
19594 case CLZERO64r:
19595 return true;
19596 }
19597 return false;
19598}
19599
19600bool isPBLENDW(unsigned Opcode) {
19601 switch (Opcode) {
19602 case PBLENDWrmi:
19603 case PBLENDWrri:
19604 return true;
19605 }
19606 return false;
19607}
19608
19609bool isVCVTBF162IUBS(unsigned Opcode) {
19610 switch (Opcode) {
19611 case VCVTBF162IUBSZ128rm:
19612 case VCVTBF162IUBSZ128rmb:
19613 case VCVTBF162IUBSZ128rmbk:
19614 case VCVTBF162IUBSZ128rmbkz:
19615 case VCVTBF162IUBSZ128rmk:
19616 case VCVTBF162IUBSZ128rmkz:
19617 case VCVTBF162IUBSZ128rr:
19618 case VCVTBF162IUBSZ128rrk:
19619 case VCVTBF162IUBSZ128rrkz:
19620 case VCVTBF162IUBSZ256rm:
19621 case VCVTBF162IUBSZ256rmb:
19622 case VCVTBF162IUBSZ256rmbk:
19623 case VCVTBF162IUBSZ256rmbkz:
19624 case VCVTBF162IUBSZ256rmk:
19625 case VCVTBF162IUBSZ256rmkz:
19626 case VCVTBF162IUBSZ256rr:
19627 case VCVTBF162IUBSZ256rrk:
19628 case VCVTBF162IUBSZ256rrkz:
19629 case VCVTBF162IUBSZrm:
19630 case VCVTBF162IUBSZrmb:
19631 case VCVTBF162IUBSZrmbk:
19632 case VCVTBF162IUBSZrmbkz:
19633 case VCVTBF162IUBSZrmk:
19634 case VCVTBF162IUBSZrmkz:
19635 case VCVTBF162IUBSZrr:
19636 case VCVTBF162IUBSZrrk:
19637 case VCVTBF162IUBSZrrkz:
19638 return true;
19639 }
19640 return false;
19641}
19642
19643bool isVCVTSH2USI(unsigned Opcode) {
19644 switch (Opcode) {
19645 case VCVTSH2USI64Zrm_Int:
19646 case VCVTSH2USI64Zrr_Int:
19647 case VCVTSH2USI64Zrrb_Int:
19648 case VCVTSH2USIZrm_Int:
19649 case VCVTSH2USIZrr_Int:
19650 case VCVTSH2USIZrrb_Int:
19651 return true;
19652 }
19653 return false;
19654}
19655
19656bool isVANDPD(unsigned Opcode) {
19657 switch (Opcode) {
19658 case VANDPDYrm:
19659 case VANDPDYrr:
19660 case VANDPDZ128rm:
19661 case VANDPDZ128rmb:
19662 case VANDPDZ128rmbk:
19663 case VANDPDZ128rmbkz:
19664 case VANDPDZ128rmk:
19665 case VANDPDZ128rmkz:
19666 case VANDPDZ128rr:
19667 case VANDPDZ128rrk:
19668 case VANDPDZ128rrkz:
19669 case VANDPDZ256rm:
19670 case VANDPDZ256rmb:
19671 case VANDPDZ256rmbk:
19672 case VANDPDZ256rmbkz:
19673 case VANDPDZ256rmk:
19674 case VANDPDZ256rmkz:
19675 case VANDPDZ256rr:
19676 case VANDPDZ256rrk:
19677 case VANDPDZ256rrkz:
19678 case VANDPDZrm:
19679 case VANDPDZrmb:
19680 case VANDPDZrmbk:
19681 case VANDPDZrmbkz:
19682 case VANDPDZrmk:
19683 case VANDPDZrmkz:
19684 case VANDPDZrr:
19685 case VANDPDZrrk:
19686 case VANDPDZrrkz:
19687 case VANDPDrm:
19688 case VANDPDrr:
19689 return true;
19690 }
19691 return false;
19692}
19693
19694bool isBEXTR(unsigned Opcode) {
19695 switch (Opcode) {
19696 case BEXTR32rm:
19697 case BEXTR32rm_EVEX:
19698 case BEXTR32rm_NF:
19699 case BEXTR32rr:
19700 case BEXTR32rr_EVEX:
19701 case BEXTR32rr_NF:
19702 case BEXTR64rm:
19703 case BEXTR64rm_EVEX:
19704 case BEXTR64rm_NF:
19705 case BEXTR64rr:
19706 case BEXTR64rr_EVEX:
19707 case BEXTR64rr_NF:
19708 case BEXTRI32mi:
19709 case BEXTRI32ri:
19710 case BEXTRI64mi:
19711 case BEXTRI64ri:
19712 return true;
19713 }
19714 return false;
19715}
19716
19717bool isSTD(unsigned Opcode) {
19718 return Opcode == STD;
19719}
19720
19721bool isVAESKEYGENASSIST(unsigned Opcode) {
19722 switch (Opcode) {
19723 case VAESKEYGENASSISTrmi:
19724 case VAESKEYGENASSISTrri:
19725 return true;
19726 }
19727 return false;
19728}
19729
19730bool isCMPSD(unsigned Opcode) {
19731 switch (Opcode) {
19732 case CMPSDrmi_Int:
19733 case CMPSDrri_Int:
19734 case CMPSL:
19735 return true;
19736 }
19737 return false;
19738}
19739
19740bool isMOVSS(unsigned Opcode) {
19741 switch (Opcode) {
19742 case MOVSSmr:
19743 case MOVSSrm:
19744 case MOVSSrr:
19745 case MOVSSrr_REV:
19746 return true;
19747 }
19748 return false;
19749}
19750
19751bool isVCVTUQQ2PD(unsigned Opcode) {
19752 switch (Opcode) {
19753 case VCVTUQQ2PDZ128rm:
19754 case VCVTUQQ2PDZ128rmb:
19755 case VCVTUQQ2PDZ128rmbk:
19756 case VCVTUQQ2PDZ128rmbkz:
19757 case VCVTUQQ2PDZ128rmk:
19758 case VCVTUQQ2PDZ128rmkz:
19759 case VCVTUQQ2PDZ128rr:
19760 case VCVTUQQ2PDZ128rrk:
19761 case VCVTUQQ2PDZ128rrkz:
19762 case VCVTUQQ2PDZ256rm:
19763 case VCVTUQQ2PDZ256rmb:
19764 case VCVTUQQ2PDZ256rmbk:
19765 case VCVTUQQ2PDZ256rmbkz:
19766 case VCVTUQQ2PDZ256rmk:
19767 case VCVTUQQ2PDZ256rmkz:
19768 case VCVTUQQ2PDZ256rr:
19769 case VCVTUQQ2PDZ256rrk:
19770 case VCVTUQQ2PDZ256rrkz:
19771 case VCVTUQQ2PDZrm:
19772 case VCVTUQQ2PDZrmb:
19773 case VCVTUQQ2PDZrmbk:
19774 case VCVTUQQ2PDZrmbkz:
19775 case VCVTUQQ2PDZrmk:
19776 case VCVTUQQ2PDZrmkz:
19777 case VCVTUQQ2PDZrr:
19778 case VCVTUQQ2PDZrrb:
19779 case VCVTUQQ2PDZrrbk:
19780 case VCVTUQQ2PDZrrbkz:
19781 case VCVTUQQ2PDZrrk:
19782 case VCVTUQQ2PDZrrkz:
19783 return true;
19784 }
19785 return false;
19786}
19787
19788bool isVEXTRACTI32X4(unsigned Opcode) {
19789 switch (Opcode) {
19790 case VEXTRACTI32X4Z256mri:
19791 case VEXTRACTI32X4Z256mrik:
19792 case VEXTRACTI32X4Z256rri:
19793 case VEXTRACTI32X4Z256rrik:
19794 case VEXTRACTI32X4Z256rrikz:
19795 case VEXTRACTI32X4Zmri:
19796 case VEXTRACTI32X4Zmrik:
19797 case VEXTRACTI32X4Zrri:
19798 case VEXTRACTI32X4Zrrik:
19799 case VEXTRACTI32X4Zrrikz:
19800 return true;
19801 }
19802 return false;
19803}
19804
19805bool isFLDCW(unsigned Opcode) {
19806 return Opcode == FLDCW16m;
19807}
19808
19809bool isINSW(unsigned Opcode) {
19810 return Opcode == INSW;
19811}
19812
19813bool isRDPID(unsigned Opcode) {
19814 switch (Opcode) {
19815 case RDPID32:
19816 case RDPID64:
19817 return true;
19818 }
19819 return false;
19820}
19821
19822bool isVUCOMXSS(unsigned Opcode) {
19823 switch (Opcode) {
19824 case VUCOMXSSZrm_Int:
19825 case VUCOMXSSZrr_Int:
19826 case VUCOMXSSZrrb_Int:
19827 return true;
19828 }
19829 return false;
19830}
19831
19832bool isKANDQ(unsigned Opcode) {
19833 return Opcode == KANDQkk;
19834}
19835
19836bool isV4FMADDPS(unsigned Opcode) {
19837 switch (Opcode) {
19838 case V4FMADDPSrm:
19839 case V4FMADDPSrmk:
19840 case V4FMADDPSrmkz:
19841 return true;
19842 }
19843 return false;
19844}
19845
19846bool isPMOVZXWQ(unsigned Opcode) {
19847 switch (Opcode) {
19848 case PMOVZXWQrm:
19849 case PMOVZXWQrr:
19850 return true;
19851 }
19852 return false;
19853}
19854
19855bool isVFPCLASSSD(unsigned Opcode) {
19856 switch (Opcode) {
19857 case VFPCLASSSDZmi:
19858 case VFPCLASSSDZmik:
19859 case VFPCLASSSDZri:
19860 case VFPCLASSSDZrik:
19861 return true;
19862 }
19863 return false;
19864}
19865
19866bool isBLENDPS(unsigned Opcode) {
19867 switch (Opcode) {
19868 case BLENDPSrmi:
19869 case BLENDPSrri:
19870 return true;
19871 }
19872 return false;
19873}
19874
19875bool isVPACKSSDW(unsigned Opcode) {
19876 switch (Opcode) {
19877 case VPACKSSDWYrm:
19878 case VPACKSSDWYrr:
19879 case VPACKSSDWZ128rm:
19880 case VPACKSSDWZ128rmb:
19881 case VPACKSSDWZ128rmbk:
19882 case VPACKSSDWZ128rmbkz:
19883 case VPACKSSDWZ128rmk:
19884 case VPACKSSDWZ128rmkz:
19885 case VPACKSSDWZ128rr:
19886 case VPACKSSDWZ128rrk:
19887 case VPACKSSDWZ128rrkz:
19888 case VPACKSSDWZ256rm:
19889 case VPACKSSDWZ256rmb:
19890 case VPACKSSDWZ256rmbk:
19891 case VPACKSSDWZ256rmbkz:
19892 case VPACKSSDWZ256rmk:
19893 case VPACKSSDWZ256rmkz:
19894 case VPACKSSDWZ256rr:
19895 case VPACKSSDWZ256rrk:
19896 case VPACKSSDWZ256rrkz:
19897 case VPACKSSDWZrm:
19898 case VPACKSSDWZrmb:
19899 case VPACKSSDWZrmbk:
19900 case VPACKSSDWZrmbkz:
19901 case VPACKSSDWZrmk:
19902 case VPACKSSDWZrmkz:
19903 case VPACKSSDWZrr:
19904 case VPACKSSDWZrrk:
19905 case VPACKSSDWZrrkz:
19906 case VPACKSSDWrm:
19907 case VPACKSSDWrr:
19908 return true;
19909 }
19910 return false;
19911}
19912
19913bool isVPINSRW(unsigned Opcode) {
19914 switch (Opcode) {
19915 case VPINSRWZrmi:
19916 case VPINSRWZrri:
19917 case VPINSRWrmi:
19918 case VPINSRWrri:
19919 return true;
19920 }
19921 return false;
19922}
19923
19924bool isFXAM(unsigned Opcode) {
19925 return Opcode == XAM_F;
19926}
19927
19928bool isVMINMAXBF16(unsigned Opcode) {
19929 switch (Opcode) {
19930 case VMINMAXBF16Z128rmbi:
19931 case VMINMAXBF16Z128rmbik:
19932 case VMINMAXBF16Z128rmbikz:
19933 case VMINMAXBF16Z128rmi:
19934 case VMINMAXBF16Z128rmik:
19935 case VMINMAXBF16Z128rmikz:
19936 case VMINMAXBF16Z128rri:
19937 case VMINMAXBF16Z128rrik:
19938 case VMINMAXBF16Z128rrikz:
19939 case VMINMAXBF16Z256rmbi:
19940 case VMINMAXBF16Z256rmbik:
19941 case VMINMAXBF16Z256rmbikz:
19942 case VMINMAXBF16Z256rmi:
19943 case VMINMAXBF16Z256rmik:
19944 case VMINMAXBF16Z256rmikz:
19945 case VMINMAXBF16Z256rri:
19946 case VMINMAXBF16Z256rrik:
19947 case VMINMAXBF16Z256rrikz:
19948 case VMINMAXBF16Zrmbi:
19949 case VMINMAXBF16Zrmbik:
19950 case VMINMAXBF16Zrmbikz:
19951 case VMINMAXBF16Zrmi:
19952 case VMINMAXBF16Zrmik:
19953 case VMINMAXBF16Zrmikz:
19954 case VMINMAXBF16Zrri:
19955 case VMINMAXBF16Zrrik:
19956 case VMINMAXBF16Zrrikz:
19957 return true;
19958 }
19959 return false;
19960}
19961
19962bool isVSHUFF64X2(unsigned Opcode) {
19963 switch (Opcode) {
19964 case VSHUFF64X2Z256rmbi:
19965 case VSHUFF64X2Z256rmbik:
19966 case VSHUFF64X2Z256rmbikz:
19967 case VSHUFF64X2Z256rmi:
19968 case VSHUFF64X2Z256rmik:
19969 case VSHUFF64X2Z256rmikz:
19970 case VSHUFF64X2Z256rri:
19971 case VSHUFF64X2Z256rrik:
19972 case VSHUFF64X2Z256rrikz:
19973 case VSHUFF64X2Zrmbi:
19974 case VSHUFF64X2Zrmbik:
19975 case VSHUFF64X2Zrmbikz:
19976 case VSHUFF64X2Zrmi:
19977 case VSHUFF64X2Zrmik:
19978 case VSHUFF64X2Zrmikz:
19979 case VSHUFF64X2Zrri:
19980 case VSHUFF64X2Zrrik:
19981 case VSHUFF64X2Zrrikz:
19982 return true;
19983 }
19984 return false;
19985}
19986
19987bool isVPACKUSWB(unsigned Opcode) {
19988 switch (Opcode) {
19989 case VPACKUSWBYrm:
19990 case VPACKUSWBYrr:
19991 case VPACKUSWBZ128rm:
19992 case VPACKUSWBZ128rmk:
19993 case VPACKUSWBZ128rmkz:
19994 case VPACKUSWBZ128rr:
19995 case VPACKUSWBZ128rrk:
19996 case VPACKUSWBZ128rrkz:
19997 case VPACKUSWBZ256rm:
19998 case VPACKUSWBZ256rmk:
19999 case VPACKUSWBZ256rmkz:
20000 case VPACKUSWBZ256rr:
20001 case VPACKUSWBZ256rrk:
20002 case VPACKUSWBZ256rrkz:
20003 case VPACKUSWBZrm:
20004 case VPACKUSWBZrmk:
20005 case VPACKUSWBZrmkz:
20006 case VPACKUSWBZrr:
20007 case VPACKUSWBZrrk:
20008 case VPACKUSWBZrrkz:
20009 case VPACKUSWBrm:
20010 case VPACKUSWBrr:
20011 return true;
20012 }
20013 return false;
20014}
20015
20016bool isVRSQRT28SS(unsigned Opcode) {
20017 switch (Opcode) {
20018 case VRSQRT28SSZm:
20019 case VRSQRT28SSZmk:
20020 case VRSQRT28SSZmkz:
20021 case VRSQRT28SSZr:
20022 case VRSQRT28SSZrb:
20023 case VRSQRT28SSZrbk:
20024 case VRSQRT28SSZrbkz:
20025 case VRSQRT28SSZrk:
20026 case VRSQRT28SSZrkz:
20027 return true;
20028 }
20029 return false;
20030}
20031
20032bool isGETSEC(unsigned Opcode) {
20033 return Opcode == GETSEC;
20034}
20035
20036bool isVEXTRACTF64X4(unsigned Opcode) {
20037 switch (Opcode) {
20038 case VEXTRACTF64X4Zmri:
20039 case VEXTRACTF64X4Zmrik:
20040 case VEXTRACTF64X4Zrri:
20041 case VEXTRACTF64X4Zrrik:
20042 case VEXTRACTF64X4Zrrikz:
20043 return true;
20044 }
20045 return false;
20046}
20047
20048bool isVPHSUBBW(unsigned Opcode) {
20049 switch (Opcode) {
20050 case VPHSUBBWrm:
20051 case VPHSUBBWrr:
20052 return true;
20053 }
20054 return false;
20055}
20056
20057bool isBLSR(unsigned Opcode) {
20058 switch (Opcode) {
20059 case BLSR32rm:
20060 case BLSR32rm_EVEX:
20061 case BLSR32rm_NF:
20062 case BLSR32rr:
20063 case BLSR32rr_EVEX:
20064 case BLSR32rr_NF:
20065 case BLSR64rm:
20066 case BLSR64rm_EVEX:
20067 case BLSR64rm_NF:
20068 case BLSR64rr:
20069 case BLSR64rr_EVEX:
20070 case BLSR64rr_NF:
20071 return true;
20072 }
20073 return false;
20074}
20075
20076bool isFILD(unsigned Opcode) {
20077 switch (Opcode) {
20078 case ILD_F16m:
20079 case ILD_F32m:
20080 case ILD_F64m:
20081 return true;
20082 }
20083 return false;
20084}
20085
20086bool isRETFQ(unsigned Opcode) {
20087 switch (Opcode) {
20088 case LRET64:
20089 case LRETI64:
20090 return true;
20091 }
20092 return false;
20093}
20094
20095bool isVADDSS(unsigned Opcode) {
20096 switch (Opcode) {
20097 case VADDSSZrm_Int:
20098 case VADDSSZrmk_Int:
20099 case VADDSSZrmkz_Int:
20100 case VADDSSZrr_Int:
20101 case VADDSSZrrb_Int:
20102 case VADDSSZrrbk_Int:
20103 case VADDSSZrrbkz_Int:
20104 case VADDSSZrrk_Int:
20105 case VADDSSZrrkz_Int:
20106 case VADDSSrm_Int:
20107 case VADDSSrr_Int:
20108 return true;
20109 }
20110 return false;
20111}
20112
20113bool isCOMISS(unsigned Opcode) {
20114 switch (Opcode) {
20115 case COMISSrm:
20116 case COMISSrr:
20117 return true;
20118 }
20119 return false;
20120}
20121
20122bool isCLI(unsigned Opcode) {
20123 return Opcode == CLI;
20124}
20125
20126bool isVERW(unsigned Opcode) {
20127 switch (Opcode) {
20128 case VERWm:
20129 case VERWr:
20130 return true;
20131 }
20132 return false;
20133}
20134
20135bool isBTC(unsigned Opcode) {
20136 switch (Opcode) {
20137 case BTC16mi8:
20138 case BTC16mr:
20139 case BTC16ri8:
20140 case BTC16rr:
20141 case BTC32mi8:
20142 case BTC32mr:
20143 case BTC32ri8:
20144 case BTC32rr:
20145 case BTC64mi8:
20146 case BTC64mr:
20147 case BTC64ri8:
20148 case BTC64rr:
20149 return true;
20150 }
20151 return false;
20152}
20153
20154bool isVPHADDUBQ(unsigned Opcode) {
20155 switch (Opcode) {
20156 case VPHADDUBQrm:
20157 case VPHADDUBQrr:
20158 return true;
20159 }
20160 return false;
20161}
20162
20163bool isVPORQ(unsigned Opcode) {
20164 switch (Opcode) {
20165 case VPORQZ128rm:
20166 case VPORQZ128rmb:
20167 case VPORQZ128rmbk:
20168 case VPORQZ128rmbkz:
20169 case VPORQZ128rmk:
20170 case VPORQZ128rmkz:
20171 case VPORQZ128rr:
20172 case VPORQZ128rrk:
20173 case VPORQZ128rrkz:
20174 case VPORQZ256rm:
20175 case VPORQZ256rmb:
20176 case VPORQZ256rmbk:
20177 case VPORQZ256rmbkz:
20178 case VPORQZ256rmk:
20179 case VPORQZ256rmkz:
20180 case VPORQZ256rr:
20181 case VPORQZ256rrk:
20182 case VPORQZ256rrkz:
20183 case VPORQZrm:
20184 case VPORQZrmb:
20185 case VPORQZrmbk:
20186 case VPORQZrmbkz:
20187 case VPORQZrmk:
20188 case VPORQZrmkz:
20189 case VPORQZrr:
20190 case VPORQZrrk:
20191 case VPORQZrrkz:
20192 return true;
20193 }
20194 return false;
20195}
20196
20197bool isORPD(unsigned Opcode) {
20198 switch (Opcode) {
20199 case ORPDrm:
20200 case ORPDrr:
20201 return true;
20202 }
20203 return false;
20204}
20205
20206bool isVMOVSS(unsigned Opcode) {
20207 switch (Opcode) {
20208 case VMOVSSZmr:
20209 case VMOVSSZmrk:
20210 case VMOVSSZrm:
20211 case VMOVSSZrmk:
20212 case VMOVSSZrmkz:
20213 case VMOVSSZrr:
20214 case VMOVSSZrr_REV:
20215 case VMOVSSZrrk:
20216 case VMOVSSZrrk_REV:
20217 case VMOVSSZrrkz:
20218 case VMOVSSZrrkz_REV:
20219 case VMOVSSmr:
20220 case VMOVSSrm:
20221 case VMOVSSrr:
20222 case VMOVSSrr_REV:
20223 return true;
20224 }
20225 return false;
20226}
20227
20228bool isVPSUBD(unsigned Opcode) {
20229 switch (Opcode) {
20230 case VPSUBDYrm:
20231 case VPSUBDYrr:
20232 case VPSUBDZ128rm:
20233 case VPSUBDZ128rmb:
20234 case VPSUBDZ128rmbk:
20235 case VPSUBDZ128rmbkz:
20236 case VPSUBDZ128rmk:
20237 case VPSUBDZ128rmkz:
20238 case VPSUBDZ128rr:
20239 case VPSUBDZ128rrk:
20240 case VPSUBDZ128rrkz:
20241 case VPSUBDZ256rm:
20242 case VPSUBDZ256rmb:
20243 case VPSUBDZ256rmbk:
20244 case VPSUBDZ256rmbkz:
20245 case VPSUBDZ256rmk:
20246 case VPSUBDZ256rmkz:
20247 case VPSUBDZ256rr:
20248 case VPSUBDZ256rrk:
20249 case VPSUBDZ256rrkz:
20250 case VPSUBDZrm:
20251 case VPSUBDZrmb:
20252 case VPSUBDZrmbk:
20253 case VPSUBDZrmbkz:
20254 case VPSUBDZrmk:
20255 case VPSUBDZrmkz:
20256 case VPSUBDZrr:
20257 case VPSUBDZrrk:
20258 case VPSUBDZrrkz:
20259 case VPSUBDrm:
20260 case VPSUBDrr:
20261 return true;
20262 }
20263 return false;
20264}
20265
20266bool isVGATHERPF1QPD(unsigned Opcode) {
20267 return Opcode == VGATHERPF1QPDm;
20268}
20269
20270bool isENCODEKEY256(unsigned Opcode) {
20271 return Opcode == ENCODEKEY256;
20272}
20273
20274bool isGF2P8AFFINEINVQB(unsigned Opcode) {
20275 switch (Opcode) {
20276 case GF2P8AFFINEINVQBrmi:
20277 case GF2P8AFFINEINVQBrri:
20278 return true;
20279 }
20280 return false;
20281}
20282
20283bool isXRSTOR64(unsigned Opcode) {
20284 return Opcode == XRSTOR64;
20285}
20286
20287bool isKANDW(unsigned Opcode) {
20288 return Opcode == KANDWkk;
20289}
20290
20291bool isLODSQ(unsigned Opcode) {
20292 return Opcode == LODSQ;
20293}
20294
20295bool isVMOVRSW(unsigned Opcode) {
20296 switch (Opcode) {
20297 case VMOVRSWZ128m:
20298 case VMOVRSWZ128mk:
20299 case VMOVRSWZ128mkz:
20300 case VMOVRSWZ256m:
20301 case VMOVRSWZ256mk:
20302 case VMOVRSWZ256mkz:
20303 case VMOVRSWZm:
20304 case VMOVRSWZmk:
20305 case VMOVRSWZmkz:
20306 return true;
20307 }
20308 return false;
20309}
20310
20311bool isVSUBSH(unsigned Opcode) {
20312 switch (Opcode) {
20313 case VSUBSHZrm_Int:
20314 case VSUBSHZrmk_Int:
20315 case VSUBSHZrmkz_Int:
20316 case VSUBSHZrr_Int:
20317 case VSUBSHZrrb_Int:
20318 case VSUBSHZrrbk_Int:
20319 case VSUBSHZrrbkz_Int:
20320 case VSUBSHZrrk_Int:
20321 case VSUBSHZrrkz_Int:
20322 return true;
20323 }
20324 return false;
20325}
20326
20327bool isLSS(unsigned Opcode) {
20328 switch (Opcode) {
20329 case LSS16rm:
20330 case LSS32rm:
20331 case LSS64rm:
20332 return true;
20333 }
20334 return false;
20335}
20336
20337bool isPMOVSXBQ(unsigned Opcode) {
20338 switch (Opcode) {
20339 case PMOVSXBQrm:
20340 case PMOVSXBQrr:
20341 return true;
20342 }
20343 return false;
20344}
20345
20346bool isVCVTTSD2SIS(unsigned Opcode) {
20347 switch (Opcode) {
20348 case VCVTTSD2SI64Srm_Int:
20349 case VCVTTSD2SI64Srr_Int:
20350 case VCVTTSD2SI64Srrb_Int:
20351 case VCVTTSD2SISrm_Int:
20352 case VCVTTSD2SISrr_Int:
20353 case VCVTTSD2SISrrb_Int:
20354 return true;
20355 }
20356 return false;
20357}
20358
20359bool isVCMPSH(unsigned Opcode) {
20360 switch (Opcode) {
20361 case VCMPSHZrmi_Int:
20362 case VCMPSHZrmik_Int:
20363 case VCMPSHZrri_Int:
20364 case VCMPSHZrrib_Int:
20365 case VCMPSHZrribk_Int:
20366 case VCMPSHZrrik_Int:
20367 return true;
20368 }
20369 return false;
20370}
20371
20372bool isVFMADD132PS(unsigned Opcode) {
20373 switch (Opcode) {
20374 case VFMADD132PSYm:
20375 case VFMADD132PSYr:
20376 case VFMADD132PSZ128m:
20377 case VFMADD132PSZ128mb:
20378 case VFMADD132PSZ128mbk:
20379 case VFMADD132PSZ128mbkz:
20380 case VFMADD132PSZ128mk:
20381 case VFMADD132PSZ128mkz:
20382 case VFMADD132PSZ128r:
20383 case VFMADD132PSZ128rk:
20384 case VFMADD132PSZ128rkz:
20385 case VFMADD132PSZ256m:
20386 case VFMADD132PSZ256mb:
20387 case VFMADD132PSZ256mbk:
20388 case VFMADD132PSZ256mbkz:
20389 case VFMADD132PSZ256mk:
20390 case VFMADD132PSZ256mkz:
20391 case VFMADD132PSZ256r:
20392 case VFMADD132PSZ256rk:
20393 case VFMADD132PSZ256rkz:
20394 case VFMADD132PSZm:
20395 case VFMADD132PSZmb:
20396 case VFMADD132PSZmbk:
20397 case VFMADD132PSZmbkz:
20398 case VFMADD132PSZmk:
20399 case VFMADD132PSZmkz:
20400 case VFMADD132PSZr:
20401 case VFMADD132PSZrb:
20402 case VFMADD132PSZrbk:
20403 case VFMADD132PSZrbkz:
20404 case VFMADD132PSZrk:
20405 case VFMADD132PSZrkz:
20406 case VFMADD132PSm:
20407 case VFMADD132PSr:
20408 return true;
20409 }
20410 return false;
20411}
20412
20413bool isVPACKSSWB(unsigned Opcode) {
20414 switch (Opcode) {
20415 case VPACKSSWBYrm:
20416 case VPACKSSWBYrr:
20417 case VPACKSSWBZ128rm:
20418 case VPACKSSWBZ128rmk:
20419 case VPACKSSWBZ128rmkz:
20420 case VPACKSSWBZ128rr:
20421 case VPACKSSWBZ128rrk:
20422 case VPACKSSWBZ128rrkz:
20423 case VPACKSSWBZ256rm:
20424 case VPACKSSWBZ256rmk:
20425 case VPACKSSWBZ256rmkz:
20426 case VPACKSSWBZ256rr:
20427 case VPACKSSWBZ256rrk:
20428 case VPACKSSWBZ256rrkz:
20429 case VPACKSSWBZrm:
20430 case VPACKSSWBZrmk:
20431 case VPACKSSWBZrmkz:
20432 case VPACKSSWBZrr:
20433 case VPACKSSWBZrrk:
20434 case VPACKSSWBZrrkz:
20435 case VPACKSSWBrm:
20436 case VPACKSSWBrr:
20437 return true;
20438 }
20439 return false;
20440}
20441
20442bool isPCMPGTQ(unsigned Opcode) {
20443 switch (Opcode) {
20444 case PCMPGTQrm:
20445 case PCMPGTQrr:
20446 return true;
20447 }
20448 return false;
20449}
20450
20451bool isVFMADD132SH(unsigned Opcode) {
20452 switch (Opcode) {
20453 case VFMADD132SHZm_Int:
20454 case VFMADD132SHZmk_Int:
20455 case VFMADD132SHZmkz_Int:
20456 case VFMADD132SHZr_Int:
20457 case VFMADD132SHZrb_Int:
20458 case VFMADD132SHZrbk_Int:
20459 case VFMADD132SHZrbkz_Int:
20460 case VFMADD132SHZrk_Int:
20461 case VFMADD132SHZrkz_Int:
20462 return true;
20463 }
20464 return false;
20465}
20466
20467bool isVCVTUQQ2PH(unsigned Opcode) {
20468 switch (Opcode) {
20469 case VCVTUQQ2PHZ128rm:
20470 case VCVTUQQ2PHZ128rmb:
20471 case VCVTUQQ2PHZ128rmbk:
20472 case VCVTUQQ2PHZ128rmbkz:
20473 case VCVTUQQ2PHZ128rmk:
20474 case VCVTUQQ2PHZ128rmkz:
20475 case VCVTUQQ2PHZ128rr:
20476 case VCVTUQQ2PHZ128rrk:
20477 case VCVTUQQ2PHZ128rrkz:
20478 case VCVTUQQ2PHZ256rm:
20479 case VCVTUQQ2PHZ256rmb:
20480 case VCVTUQQ2PHZ256rmbk:
20481 case VCVTUQQ2PHZ256rmbkz:
20482 case VCVTUQQ2PHZ256rmk:
20483 case VCVTUQQ2PHZ256rmkz:
20484 case VCVTUQQ2PHZ256rr:
20485 case VCVTUQQ2PHZ256rrk:
20486 case VCVTUQQ2PHZ256rrkz:
20487 case VCVTUQQ2PHZrm:
20488 case VCVTUQQ2PHZrmb:
20489 case VCVTUQQ2PHZrmbk:
20490 case VCVTUQQ2PHZrmbkz:
20491 case VCVTUQQ2PHZrmk:
20492 case VCVTUQQ2PHZrmkz:
20493 case VCVTUQQ2PHZrr:
20494 case VCVTUQQ2PHZrrb:
20495 case VCVTUQQ2PHZrrbk:
20496 case VCVTUQQ2PHZrrbkz:
20497 case VCVTUQQ2PHZrrk:
20498 case VCVTUQQ2PHZrrkz:
20499 return true;
20500 }
20501 return false;
20502}
20503
20504bool isVCVTQQ2PS(unsigned Opcode) {
20505 switch (Opcode) {
20506 case VCVTQQ2PSZ128rm:
20507 case VCVTQQ2PSZ128rmb:
20508 case VCVTQQ2PSZ128rmbk:
20509 case VCVTQQ2PSZ128rmbkz:
20510 case VCVTQQ2PSZ128rmk:
20511 case VCVTQQ2PSZ128rmkz:
20512 case VCVTQQ2PSZ128rr:
20513 case VCVTQQ2PSZ128rrk:
20514 case VCVTQQ2PSZ128rrkz:
20515 case VCVTQQ2PSZ256rm:
20516 case VCVTQQ2PSZ256rmb:
20517 case VCVTQQ2PSZ256rmbk:
20518 case VCVTQQ2PSZ256rmbkz:
20519 case VCVTQQ2PSZ256rmk:
20520 case VCVTQQ2PSZ256rmkz:
20521 case VCVTQQ2PSZ256rr:
20522 case VCVTQQ2PSZ256rrk:
20523 case VCVTQQ2PSZ256rrkz:
20524 case VCVTQQ2PSZrm:
20525 case VCVTQQ2PSZrmb:
20526 case VCVTQQ2PSZrmbk:
20527 case VCVTQQ2PSZrmbkz:
20528 case VCVTQQ2PSZrmk:
20529 case VCVTQQ2PSZrmkz:
20530 case VCVTQQ2PSZrr:
20531 case VCVTQQ2PSZrrb:
20532 case VCVTQQ2PSZrrbk:
20533 case VCVTQQ2PSZrrbkz:
20534 case VCVTQQ2PSZrrk:
20535 case VCVTQQ2PSZrrkz:
20536 return true;
20537 }
20538 return false;
20539}
20540
20541bool isVCVTTSS2USI(unsigned Opcode) {
20542 switch (Opcode) {
20543 case VCVTTSS2USI64Zrm_Int:
20544 case VCVTTSS2USI64Zrr_Int:
20545 case VCVTTSS2USI64Zrrb_Int:
20546 case VCVTTSS2USIZrm_Int:
20547 case VCVTTSS2USIZrr_Int:
20548 case VCVTTSS2USIZrrb_Int:
20549 return true;
20550 }
20551 return false;
20552}
20553
20554bool isVPMOVM2Q(unsigned Opcode) {
20555 switch (Opcode) {
20556 case VPMOVM2QZ128rk:
20557 case VPMOVM2QZ256rk:
20558 case VPMOVM2QZrk:
20559 return true;
20560 }
20561 return false;
20562}
20563
20564bool isVMOVD(unsigned Opcode) {
20565 switch (Opcode) {
20566 case VMOVDI2PDIZrm:
20567 case VMOVDI2PDIZrr:
20568 case VMOVDI2PDIrm:
20569 case VMOVDI2PDIrr:
20570 case VMOVPDI2DIZmr:
20571 case VMOVPDI2DIZrr:
20572 case VMOVPDI2DImr:
20573 case VMOVPDI2DIrr:
20574 case VMOVZPDILo2PDIZmr:
20575 case VMOVZPDILo2PDIZrm:
20576 case VMOVZPDILo2PDIZrr:
20577 case VMOVZPDILo2PDIZrr2:
20578 return true;
20579 }
20580 return false;
20581}
20582
20583bool isVCVTTPS2QQS(unsigned Opcode) {
20584 switch (Opcode) {
20585 case VCVTTPS2QQSZ128rm:
20586 case VCVTTPS2QQSZ128rmb:
20587 case VCVTTPS2QQSZ128rmbk:
20588 case VCVTTPS2QQSZ128rmbkz:
20589 case VCVTTPS2QQSZ128rmk:
20590 case VCVTTPS2QQSZ128rmkz:
20591 case VCVTTPS2QQSZ128rr:
20592 case VCVTTPS2QQSZ128rrk:
20593 case VCVTTPS2QQSZ128rrkz:
20594 case VCVTTPS2QQSZ256rm:
20595 case VCVTTPS2QQSZ256rmb:
20596 case VCVTTPS2QQSZ256rmbk:
20597 case VCVTTPS2QQSZ256rmbkz:
20598 case VCVTTPS2QQSZ256rmk:
20599 case VCVTTPS2QQSZ256rmkz:
20600 case VCVTTPS2QQSZ256rr:
20601 case VCVTTPS2QQSZ256rrb:
20602 case VCVTTPS2QQSZ256rrbk:
20603 case VCVTTPS2QQSZ256rrbkz:
20604 case VCVTTPS2QQSZ256rrk:
20605 case VCVTTPS2QQSZ256rrkz:
20606 case VCVTTPS2QQSZrm:
20607 case VCVTTPS2QQSZrmb:
20608 case VCVTTPS2QQSZrmbk:
20609 case VCVTTPS2QQSZrmbkz:
20610 case VCVTTPS2QQSZrmk:
20611 case VCVTTPS2QQSZrmkz:
20612 case VCVTTPS2QQSZrr:
20613 case VCVTTPS2QQSZrrb:
20614 case VCVTTPS2QQSZrrbk:
20615 case VCVTTPS2QQSZrrbkz:
20616 case VCVTTPS2QQSZrrk:
20617 case VCVTTPS2QQSZrrkz:
20618 return true;
20619 }
20620 return false;
20621}
20622
20623bool isVSQRTBF16(unsigned Opcode) {
20624 switch (Opcode) {
20625 case VSQRTBF16Z128m:
20626 case VSQRTBF16Z128mb:
20627 case VSQRTBF16Z128mbk:
20628 case VSQRTBF16Z128mbkz:
20629 case VSQRTBF16Z128mk:
20630 case VSQRTBF16Z128mkz:
20631 case VSQRTBF16Z128r:
20632 case VSQRTBF16Z128rk:
20633 case VSQRTBF16Z128rkz:
20634 case VSQRTBF16Z256m:
20635 case VSQRTBF16Z256mb:
20636 case VSQRTBF16Z256mbk:
20637 case VSQRTBF16Z256mbkz:
20638 case VSQRTBF16Z256mk:
20639 case VSQRTBF16Z256mkz:
20640 case VSQRTBF16Z256r:
20641 case VSQRTBF16Z256rk:
20642 case VSQRTBF16Z256rkz:
20643 case VSQRTBF16Zm:
20644 case VSQRTBF16Zmb:
20645 case VSQRTBF16Zmbk:
20646 case VSQRTBF16Zmbkz:
20647 case VSQRTBF16Zmk:
20648 case VSQRTBF16Zmkz:
20649 case VSQRTBF16Zr:
20650 case VSQRTBF16Zrk:
20651 case VSQRTBF16Zrkz:
20652 return true;
20653 }
20654 return false;
20655}
20656
20657bool isVFPCLASSPH(unsigned Opcode) {
20658 switch (Opcode) {
20659 case VFPCLASSPHZ128mbi:
20660 case VFPCLASSPHZ128mbik:
20661 case VFPCLASSPHZ128mi:
20662 case VFPCLASSPHZ128mik:
20663 case VFPCLASSPHZ128ri:
20664 case VFPCLASSPHZ128rik:
20665 case VFPCLASSPHZ256mbi:
20666 case VFPCLASSPHZ256mbik:
20667 case VFPCLASSPHZ256mi:
20668 case VFPCLASSPHZ256mik:
20669 case VFPCLASSPHZ256ri:
20670 case VFPCLASSPHZ256rik:
20671 case VFPCLASSPHZmbi:
20672 case VFPCLASSPHZmbik:
20673 case VFPCLASSPHZmi:
20674 case VFPCLASSPHZmik:
20675 case VFPCLASSPHZri:
20676 case VFPCLASSPHZrik:
20677 return true;
20678 }
20679 return false;
20680}
20681
20682bool isVCVTSS2SH(unsigned Opcode) {
20683 switch (Opcode) {
20684 case VCVTSS2SHZrm_Int:
20685 case VCVTSS2SHZrmk_Int:
20686 case VCVTSS2SHZrmkz_Int:
20687 case VCVTSS2SHZrr_Int:
20688 case VCVTSS2SHZrrb_Int:
20689 case VCVTSS2SHZrrbk_Int:
20690 case VCVTSS2SHZrrbkz_Int:
20691 case VCVTSS2SHZrrk_Int:
20692 case VCVTSS2SHZrrkz_Int:
20693 return true;
20694 }
20695 return false;
20696}
20697
20698bool isSCASB(unsigned Opcode) {
20699 return Opcode == SCASB;
20700}
20701
20702bool isPSRLD(unsigned Opcode) {
20703 switch (Opcode) {
20704 case MMX_PSRLDri:
20705 case MMX_PSRLDrm:
20706 case MMX_PSRLDrr:
20707 case PSRLDri:
20708 case PSRLDrm:
20709 case PSRLDrr:
20710 return true;
20711 }
20712 return false;
20713}
20714
20715bool isVADDPH(unsigned Opcode) {
20716 switch (Opcode) {
20717 case VADDPHZ128rm:
20718 case VADDPHZ128rmb:
20719 case VADDPHZ128rmbk:
20720 case VADDPHZ128rmbkz:
20721 case VADDPHZ128rmk:
20722 case VADDPHZ128rmkz:
20723 case VADDPHZ128rr:
20724 case VADDPHZ128rrk:
20725 case VADDPHZ128rrkz:
20726 case VADDPHZ256rm:
20727 case VADDPHZ256rmb:
20728 case VADDPHZ256rmbk:
20729 case VADDPHZ256rmbkz:
20730 case VADDPHZ256rmk:
20731 case VADDPHZ256rmkz:
20732 case VADDPHZ256rr:
20733 case VADDPHZ256rrk:
20734 case VADDPHZ256rrkz:
20735 case VADDPHZrm:
20736 case VADDPHZrmb:
20737 case VADDPHZrmbk:
20738 case VADDPHZrmbkz:
20739 case VADDPHZrmk:
20740 case VADDPHZrmkz:
20741 case VADDPHZrr:
20742 case VADDPHZrrb:
20743 case VADDPHZrrbk:
20744 case VADDPHZrrbkz:
20745 case VADDPHZrrk:
20746 case VADDPHZrrkz:
20747 return true;
20748 }
20749 return false;
20750}
20751
20752bool isFSUB(unsigned Opcode) {
20753 switch (Opcode) {
20754 case SUB_F32m:
20755 case SUB_F64m:
20756 case SUB_FST0r:
20757 case SUB_FrST0:
20758 return true;
20759 }
20760 return false;
20761}
20762
20763bool isVCVTTPH2IBS(unsigned Opcode) {
20764 switch (Opcode) {
20765 case VCVTTPH2IBSZ128rm:
20766 case VCVTTPH2IBSZ128rmb:
20767 case VCVTTPH2IBSZ128rmbk:
20768 case VCVTTPH2IBSZ128rmbkz:
20769 case VCVTTPH2IBSZ128rmk:
20770 case VCVTTPH2IBSZ128rmkz:
20771 case VCVTTPH2IBSZ128rr:
20772 case VCVTTPH2IBSZ128rrk:
20773 case VCVTTPH2IBSZ128rrkz:
20774 case VCVTTPH2IBSZ256rm:
20775 case VCVTTPH2IBSZ256rmb:
20776 case VCVTTPH2IBSZ256rmbk:
20777 case VCVTTPH2IBSZ256rmbkz:
20778 case VCVTTPH2IBSZ256rmk:
20779 case VCVTTPH2IBSZ256rmkz:
20780 case VCVTTPH2IBSZ256rr:
20781 case VCVTTPH2IBSZ256rrk:
20782 case VCVTTPH2IBSZ256rrkz:
20783 case VCVTTPH2IBSZrm:
20784 case VCVTTPH2IBSZrmb:
20785 case VCVTTPH2IBSZrmbk:
20786 case VCVTTPH2IBSZrmbkz:
20787 case VCVTTPH2IBSZrmk:
20788 case VCVTTPH2IBSZrmkz:
20789 case VCVTTPH2IBSZrr:
20790 case VCVTTPH2IBSZrrb:
20791 case VCVTTPH2IBSZrrbk:
20792 case VCVTTPH2IBSZrrbkz:
20793 case VCVTTPH2IBSZrrk:
20794 case VCVTTPH2IBSZrrkz:
20795 return true;
20796 }
20797 return false;
20798}
20799
20800bool isVEXTRACTI64X2(unsigned Opcode) {
20801 switch (Opcode) {
20802 case VEXTRACTI64X2Z256mri:
20803 case VEXTRACTI64X2Z256mrik:
20804 case VEXTRACTI64X2Z256rri:
20805 case VEXTRACTI64X2Z256rrik:
20806 case VEXTRACTI64X2Z256rrikz:
20807 case VEXTRACTI64X2Zmri:
20808 case VEXTRACTI64X2Zmrik:
20809 case VEXTRACTI64X2Zrri:
20810 case VEXTRACTI64X2Zrrik:
20811 case VEXTRACTI64X2Zrrikz:
20812 return true;
20813 }
20814 return false;
20815}
20816
20817bool isPMINUW(unsigned Opcode) {
20818 switch (Opcode) {
20819 case PMINUWrm:
20820 case PMINUWrr:
20821 return true;
20822 }
20823 return false;
20824}
20825
20826bool isPSUBSB(unsigned Opcode) {
20827 switch (Opcode) {
20828 case MMX_PSUBSBrm:
20829 case MMX_PSUBSBrr:
20830 case PSUBSBrm:
20831 case PSUBSBrr:
20832 return true;
20833 }
20834 return false;
20835}
20836
20837bool isVCVT2PS2PHX(unsigned Opcode) {
20838 switch (Opcode) {
20839 case VCVT2PS2PHXZ128rm:
20840 case VCVT2PS2PHXZ128rmb:
20841 case VCVT2PS2PHXZ128rmbk:
20842 case VCVT2PS2PHXZ128rmbkz:
20843 case VCVT2PS2PHXZ128rmk:
20844 case VCVT2PS2PHXZ128rmkz:
20845 case VCVT2PS2PHXZ128rr:
20846 case VCVT2PS2PHXZ128rrk:
20847 case VCVT2PS2PHXZ128rrkz:
20848 case VCVT2PS2PHXZ256rm:
20849 case VCVT2PS2PHXZ256rmb:
20850 case VCVT2PS2PHXZ256rmbk:
20851 case VCVT2PS2PHXZ256rmbkz:
20852 case VCVT2PS2PHXZ256rmk:
20853 case VCVT2PS2PHXZ256rmkz:
20854 case VCVT2PS2PHXZ256rr:
20855 case VCVT2PS2PHXZ256rrk:
20856 case VCVT2PS2PHXZ256rrkz:
20857 case VCVT2PS2PHXZrm:
20858 case VCVT2PS2PHXZrmb:
20859 case VCVT2PS2PHXZrmbk:
20860 case VCVT2PS2PHXZrmbkz:
20861 case VCVT2PS2PHXZrmk:
20862 case VCVT2PS2PHXZrmkz:
20863 case VCVT2PS2PHXZrr:
20864 case VCVT2PS2PHXZrrb:
20865 case VCVT2PS2PHXZrrbk:
20866 case VCVT2PS2PHXZrrbkz:
20867 case VCVT2PS2PHXZrrk:
20868 case VCVT2PS2PHXZrrkz:
20869 return true;
20870 }
20871 return false;
20872}
20873
20874bool isVPCMPEQD(unsigned Opcode) {
20875 switch (Opcode) {
20876 case VPCMPEQDYrm:
20877 case VPCMPEQDYrr:
20878 case VPCMPEQDZ128rm:
20879 case VPCMPEQDZ128rmb:
20880 case VPCMPEQDZ128rmbk:
20881 case VPCMPEQDZ128rmk:
20882 case VPCMPEQDZ128rr:
20883 case VPCMPEQDZ128rrk:
20884 case VPCMPEQDZ256rm:
20885 case VPCMPEQDZ256rmb:
20886 case VPCMPEQDZ256rmbk:
20887 case VPCMPEQDZ256rmk:
20888 case VPCMPEQDZ256rr:
20889 case VPCMPEQDZ256rrk:
20890 case VPCMPEQDZrm:
20891 case VPCMPEQDZrmb:
20892 case VPCMPEQDZrmbk:
20893 case VPCMPEQDZrmk:
20894 case VPCMPEQDZrr:
20895 case VPCMPEQDZrrk:
20896 case VPCMPEQDrm:
20897 case VPCMPEQDrr:
20898 return true;
20899 }
20900 return false;
20901}
20902
20903bool isVPSCATTERQD(unsigned Opcode) {
20904 switch (Opcode) {
20905 case VPSCATTERQDZ128mr:
20906 case VPSCATTERQDZ256mr:
20907 case VPSCATTERQDZmr:
20908 return true;
20909 }
20910 return false;
20911}
20912
20913bool isVPSHLDD(unsigned Opcode) {
20914 switch (Opcode) {
20915 case VPSHLDDZ128rmbi:
20916 case VPSHLDDZ128rmbik:
20917 case VPSHLDDZ128rmbikz:
20918 case VPSHLDDZ128rmi:
20919 case VPSHLDDZ128rmik:
20920 case VPSHLDDZ128rmikz:
20921 case VPSHLDDZ128rri:
20922 case VPSHLDDZ128rrik:
20923 case VPSHLDDZ128rrikz:
20924 case VPSHLDDZ256rmbi:
20925 case VPSHLDDZ256rmbik:
20926 case VPSHLDDZ256rmbikz:
20927 case VPSHLDDZ256rmi:
20928 case VPSHLDDZ256rmik:
20929 case VPSHLDDZ256rmikz:
20930 case VPSHLDDZ256rri:
20931 case VPSHLDDZ256rrik:
20932 case VPSHLDDZ256rrikz:
20933 case VPSHLDDZrmbi:
20934 case VPSHLDDZrmbik:
20935 case VPSHLDDZrmbikz:
20936 case VPSHLDDZrmi:
20937 case VPSHLDDZrmik:
20938 case VPSHLDDZrmikz:
20939 case VPSHLDDZrri:
20940 case VPSHLDDZrrik:
20941 case VPSHLDDZrrikz:
20942 return true;
20943 }
20944 return false;
20945}
20946
20947bool isKXNORB(unsigned Opcode) {
20948 return Opcode == KXNORBkk;
20949}
20950
20951bool isLDDQU(unsigned Opcode) {
20952 return Opcode == LDDQUrm;
20953}
20954
20955bool isMASKMOVQ(unsigned Opcode) {
20956 switch (Opcode) {
20957 case MMX_MASKMOVQ:
20958 case MMX_MASKMOVQ64:
20959 return true;
20960 }
20961 return false;
20962}
20963
20964bool isPABSW(unsigned Opcode) {
20965 switch (Opcode) {
20966 case MMX_PABSWrm:
20967 case MMX_PABSWrr:
20968 case PABSWrm:
20969 case PABSWrr:
20970 return true;
20971 }
20972 return false;
20973}
20974
20975bool isVPROLD(unsigned Opcode) {
20976 switch (Opcode) {
20977 case VPROLDZ128mbi:
20978 case VPROLDZ128mbik:
20979 case VPROLDZ128mbikz:
20980 case VPROLDZ128mi:
20981 case VPROLDZ128mik:
20982 case VPROLDZ128mikz:
20983 case VPROLDZ128ri:
20984 case VPROLDZ128rik:
20985 case VPROLDZ128rikz:
20986 case VPROLDZ256mbi:
20987 case VPROLDZ256mbik:
20988 case VPROLDZ256mbikz:
20989 case VPROLDZ256mi:
20990 case VPROLDZ256mik:
20991 case VPROLDZ256mikz:
20992 case VPROLDZ256ri:
20993 case VPROLDZ256rik:
20994 case VPROLDZ256rikz:
20995 case VPROLDZmbi:
20996 case VPROLDZmbik:
20997 case VPROLDZmbikz:
20998 case VPROLDZmi:
20999 case VPROLDZmik:
21000 case VPROLDZmikz:
21001 case VPROLDZri:
21002 case VPROLDZrik:
21003 case VPROLDZrikz:
21004 return true;
21005 }
21006 return false;
21007}
21008
21009bool isVPCOMQ(unsigned Opcode) {
21010 switch (Opcode) {
21011 case VPCOMQmi:
21012 case VPCOMQri:
21013 return true;
21014 }
21015 return false;
21016}
21017
21018bool isVSCATTERDPD(unsigned Opcode) {
21019 switch (Opcode) {
21020 case VSCATTERDPDZ128mr:
21021 case VSCATTERDPDZ256mr:
21022 case VSCATTERDPDZmr:
21023 return true;
21024 }
21025 return false;
21026}
21027
21028bool isFXRSTOR(unsigned Opcode) {
21029 return Opcode == FXRSTOR;
21030}
21031
21032bool isVPCMPUW(unsigned Opcode) {
21033 switch (Opcode) {
21034 case VPCMPUWZ128rmi:
21035 case VPCMPUWZ128rmik:
21036 case VPCMPUWZ128rri:
21037 case VPCMPUWZ128rrik:
21038 case VPCMPUWZ256rmi:
21039 case VPCMPUWZ256rmik:
21040 case VPCMPUWZ256rri:
21041 case VPCMPUWZ256rrik:
21042 case VPCMPUWZrmi:
21043 case VPCMPUWZrmik:
21044 case VPCMPUWZrri:
21045 case VPCMPUWZrrik:
21046 return true;
21047 }
21048 return false;
21049}
21050
21051bool isWBINVD(unsigned Opcode) {
21052 return Opcode == WBINVD;
21053}
21054
21055bool isVCVTTPD2UDQ(unsigned Opcode) {
21056 switch (Opcode) {
21057 case VCVTTPD2UDQZ128rm:
21058 case VCVTTPD2UDQZ128rmb:
21059 case VCVTTPD2UDQZ128rmbk:
21060 case VCVTTPD2UDQZ128rmbkz:
21061 case VCVTTPD2UDQZ128rmk:
21062 case VCVTTPD2UDQZ128rmkz:
21063 case VCVTTPD2UDQZ128rr:
21064 case VCVTTPD2UDQZ128rrk:
21065 case VCVTTPD2UDQZ128rrkz:
21066 case VCVTTPD2UDQZ256rm:
21067 case VCVTTPD2UDQZ256rmb:
21068 case VCVTTPD2UDQZ256rmbk:
21069 case VCVTTPD2UDQZ256rmbkz:
21070 case VCVTTPD2UDQZ256rmk:
21071 case VCVTTPD2UDQZ256rmkz:
21072 case VCVTTPD2UDQZ256rr:
21073 case VCVTTPD2UDQZ256rrk:
21074 case VCVTTPD2UDQZ256rrkz:
21075 case VCVTTPD2UDQZrm:
21076 case VCVTTPD2UDQZrmb:
21077 case VCVTTPD2UDQZrmbk:
21078 case VCVTTPD2UDQZrmbkz:
21079 case VCVTTPD2UDQZrmk:
21080 case VCVTTPD2UDQZrmkz:
21081 case VCVTTPD2UDQZrr:
21082 case VCVTTPD2UDQZrrb:
21083 case VCVTTPD2UDQZrrbk:
21084 case VCVTTPD2UDQZrrbkz:
21085 case VCVTTPD2UDQZrrk:
21086 case VCVTTPD2UDQZrrkz:
21087 return true;
21088 }
21089 return false;
21090}
21091
21092bool isERETU(unsigned Opcode) {
21093 return Opcode == ERETU;
21094}
21095
21096bool isPFRCPIT2(unsigned Opcode) {
21097 switch (Opcode) {
21098 case PFRCPIT2rm:
21099 case PFRCPIT2rr:
21100 return true;
21101 }
21102 return false;
21103}
21104
21105bool isVPERMT2W(unsigned Opcode) {
21106 switch (Opcode) {
21107 case VPERMT2WZ128rm:
21108 case VPERMT2WZ128rmk:
21109 case VPERMT2WZ128rmkz:
21110 case VPERMT2WZ128rr:
21111 case VPERMT2WZ128rrk:
21112 case VPERMT2WZ128rrkz:
21113 case VPERMT2WZ256rm:
21114 case VPERMT2WZ256rmk:
21115 case VPERMT2WZ256rmkz:
21116 case VPERMT2WZ256rr:
21117 case VPERMT2WZ256rrk:
21118 case VPERMT2WZ256rrkz:
21119 case VPERMT2WZrm:
21120 case VPERMT2WZrmk:
21121 case VPERMT2WZrmkz:
21122 case VPERMT2WZrr:
21123 case VPERMT2WZrrk:
21124 case VPERMT2WZrrkz:
21125 return true;
21126 }
21127 return false;
21128}
21129
21130bool isVEXTRACTF32X4(unsigned Opcode) {
21131 switch (Opcode) {
21132 case VEXTRACTF32X4Z256mri:
21133 case VEXTRACTF32X4Z256mrik:
21134 case VEXTRACTF32X4Z256rri:
21135 case VEXTRACTF32X4Z256rrik:
21136 case VEXTRACTF32X4Z256rrikz:
21137 case VEXTRACTF32X4Zmri:
21138 case VEXTRACTF32X4Zmrik:
21139 case VEXTRACTF32X4Zrri:
21140 case VEXTRACTF32X4Zrrik:
21141 case VEXTRACTF32X4Zrrikz:
21142 return true;
21143 }
21144 return false;
21145}
21146
21147bool isVGATHERPF0DPD(unsigned Opcode) {
21148 return Opcode == VGATHERPF0DPDm;
21149}
21150
21151bool isVBROADCASTF32X2(unsigned Opcode) {
21152 switch (Opcode) {
21153 case VBROADCASTF32X2Z256rm:
21154 case VBROADCASTF32X2Z256rmk:
21155 case VBROADCASTF32X2Z256rmkz:
21156 case VBROADCASTF32X2Z256rr:
21157 case VBROADCASTF32X2Z256rrk:
21158 case VBROADCASTF32X2Z256rrkz:
21159 case VBROADCASTF32X2Zrm:
21160 case VBROADCASTF32X2Zrmk:
21161 case VBROADCASTF32X2Zrmkz:
21162 case VBROADCASTF32X2Zrr:
21163 case VBROADCASTF32X2Zrrk:
21164 case VBROADCASTF32X2Zrrkz:
21165 return true;
21166 }
21167 return false;
21168}
21169
21170bool isVRCP14SD(unsigned Opcode) {
21171 switch (Opcode) {
21172 case VRCP14SDZrm:
21173 case VRCP14SDZrmk:
21174 case VRCP14SDZrmkz:
21175 case VRCP14SDZrr:
21176 case VRCP14SDZrrk:
21177 case VRCP14SDZrrkz:
21178 return true;
21179 }
21180 return false;
21181}
21182
21183bool isPABSD(unsigned Opcode) {
21184 switch (Opcode) {
21185 case MMX_PABSDrm:
21186 case MMX_PABSDrr:
21187 case PABSDrm:
21188 case PABSDrr:
21189 return true;
21190 }
21191 return false;
21192}
21193
21194bool isLAHF(unsigned Opcode) {
21195 return Opcode == LAHF;
21196}
21197
21198bool isPINSRB(unsigned Opcode) {
21199 switch (Opcode) {
21200 case PINSRBrmi:
21201 case PINSRBrri:
21202 return true;
21203 }
21204 return false;
21205}
21206
21207bool isSKINIT(unsigned Opcode) {
21208 return Opcode == SKINIT;
21209}
21210
21211bool isENTER(unsigned Opcode) {
21212 return Opcode == ENTER;
21213}
21214
21215bool isVCVTSI2SS(unsigned Opcode) {
21216 switch (Opcode) {
21217 case VCVTSI2SSZrm_Int:
21218 case VCVTSI2SSZrr_Int:
21219 case VCVTSI2SSZrrb_Int:
21220 case VCVTSI2SSrm_Int:
21221 case VCVTSI2SSrr_Int:
21222 case VCVTSI642SSZrm_Int:
21223 case VCVTSI642SSZrr_Int:
21224 case VCVTSI642SSZrrb_Int:
21225 case VCVTSI642SSrm_Int:
21226 case VCVTSI642SSrr_Int:
21227 return true;
21228 }
21229 return false;
21230}
21231
21232bool isVFMADD231PD(unsigned Opcode) {
21233 switch (Opcode) {
21234 case VFMADD231PDYm:
21235 case VFMADD231PDYr:
21236 case VFMADD231PDZ128m:
21237 case VFMADD231PDZ128mb:
21238 case VFMADD231PDZ128mbk:
21239 case VFMADD231PDZ128mbkz:
21240 case VFMADD231PDZ128mk:
21241 case VFMADD231PDZ128mkz:
21242 case VFMADD231PDZ128r:
21243 case VFMADD231PDZ128rk:
21244 case VFMADD231PDZ128rkz:
21245 case VFMADD231PDZ256m:
21246 case VFMADD231PDZ256mb:
21247 case VFMADD231PDZ256mbk:
21248 case VFMADD231PDZ256mbkz:
21249 case VFMADD231PDZ256mk:
21250 case VFMADD231PDZ256mkz:
21251 case VFMADD231PDZ256r:
21252 case VFMADD231PDZ256rk:
21253 case VFMADD231PDZ256rkz:
21254 case VFMADD231PDZm:
21255 case VFMADD231PDZmb:
21256 case VFMADD231PDZmbk:
21257 case VFMADD231PDZmbkz:
21258 case VFMADD231PDZmk:
21259 case VFMADD231PDZmkz:
21260 case VFMADD231PDZr:
21261 case VFMADD231PDZrb:
21262 case VFMADD231PDZrbk:
21263 case VFMADD231PDZrbkz:
21264 case VFMADD231PDZrk:
21265 case VFMADD231PDZrkz:
21266 case VFMADD231PDm:
21267 case VFMADD231PDr:
21268 return true;
21269 }
21270 return false;
21271}
21272
21273bool isLOADIWKEY(unsigned Opcode) {
21274 return Opcode == LOADIWKEY;
21275}
21276
21277bool isVMOVNTDQA(unsigned Opcode) {
21278 switch (Opcode) {
21279 case VMOVNTDQAYrm:
21280 case VMOVNTDQAZ128rm:
21281 case VMOVNTDQAZ256rm:
21282 case VMOVNTDQAZrm:
21283 case VMOVNTDQArm:
21284 return true;
21285 }
21286 return false;
21287}
21288
21289bool isVPERMT2PS(unsigned Opcode) {
21290 switch (Opcode) {
21291 case VPERMT2PSZ128rm:
21292 case VPERMT2PSZ128rmb:
21293 case VPERMT2PSZ128rmbk:
21294 case VPERMT2PSZ128rmbkz:
21295 case VPERMT2PSZ128rmk:
21296 case VPERMT2PSZ128rmkz:
21297 case VPERMT2PSZ128rr:
21298 case VPERMT2PSZ128rrk:
21299 case VPERMT2PSZ128rrkz:
21300 case VPERMT2PSZ256rm:
21301 case VPERMT2PSZ256rmb:
21302 case VPERMT2PSZ256rmbk:
21303 case VPERMT2PSZ256rmbkz:
21304 case VPERMT2PSZ256rmk:
21305 case VPERMT2PSZ256rmkz:
21306 case VPERMT2PSZ256rr:
21307 case VPERMT2PSZ256rrk:
21308 case VPERMT2PSZ256rrkz:
21309 case VPERMT2PSZrm:
21310 case VPERMT2PSZrmb:
21311 case VPERMT2PSZrmbk:
21312 case VPERMT2PSZrmbkz:
21313 case VPERMT2PSZrmk:
21314 case VPERMT2PSZrmkz:
21315 case VPERMT2PSZrr:
21316 case VPERMT2PSZrrk:
21317 case VPERMT2PSZrrkz:
21318 return true;
21319 }
21320 return false;
21321}
21322
21323bool isPUSHF(unsigned Opcode) {
21324 return Opcode == PUSHF16;
21325}
21326
21327bool isMPSADBW(unsigned Opcode) {
21328 switch (Opcode) {
21329 case MPSADBWrmi:
21330 case MPSADBWrri:
21331 return true;
21332 }
21333 return false;
21334}
21335
21336bool isVMINMAXSH(unsigned Opcode) {
21337 switch (Opcode) {
21338 case VMINMAXSHrmi_Int:
21339 case VMINMAXSHrmik_Int:
21340 case VMINMAXSHrmikz_Int:
21341 case VMINMAXSHrri_Int:
21342 case VMINMAXSHrrib_Int:
21343 case VMINMAXSHrribk_Int:
21344 case VMINMAXSHrribkz_Int:
21345 case VMINMAXSHrrik_Int:
21346 case VMINMAXSHrrikz_Int:
21347 return true;
21348 }
21349 return false;
21350}
21351
21352bool isVRSQRT14SS(unsigned Opcode) {
21353 switch (Opcode) {
21354 case VRSQRT14SSZrm:
21355 case VRSQRT14SSZrmk:
21356 case VRSQRT14SSZrmkz:
21357 case VRSQRT14SSZrr:
21358 case VRSQRT14SSZrrk:
21359 case VRSQRT14SSZrrkz:
21360 return true;
21361 }
21362 return false;
21363}
21364
21365bool isVCVTDQ2PD(unsigned Opcode) {
21366 switch (Opcode) {
21367 case VCVTDQ2PDYrm:
21368 case VCVTDQ2PDYrr:
21369 case VCVTDQ2PDZ128rm:
21370 case VCVTDQ2PDZ128rmb:
21371 case VCVTDQ2PDZ128rmbk:
21372 case VCVTDQ2PDZ128rmbkz:
21373 case VCVTDQ2PDZ128rmk:
21374 case VCVTDQ2PDZ128rmkz:
21375 case VCVTDQ2PDZ128rr:
21376 case VCVTDQ2PDZ128rrk:
21377 case VCVTDQ2PDZ128rrkz:
21378 case VCVTDQ2PDZ256rm:
21379 case VCVTDQ2PDZ256rmb:
21380 case VCVTDQ2PDZ256rmbk:
21381 case VCVTDQ2PDZ256rmbkz:
21382 case VCVTDQ2PDZ256rmk:
21383 case VCVTDQ2PDZ256rmkz:
21384 case VCVTDQ2PDZ256rr:
21385 case VCVTDQ2PDZ256rrk:
21386 case VCVTDQ2PDZ256rrkz:
21387 case VCVTDQ2PDZrm:
21388 case VCVTDQ2PDZrmb:
21389 case VCVTDQ2PDZrmbk:
21390 case VCVTDQ2PDZrmbkz:
21391 case VCVTDQ2PDZrmk:
21392 case VCVTDQ2PDZrmkz:
21393 case VCVTDQ2PDZrr:
21394 case VCVTDQ2PDZrrk:
21395 case VCVTDQ2PDZrrkz:
21396 case VCVTDQ2PDrm:
21397 case VCVTDQ2PDrr:
21398 return true;
21399 }
21400 return false;
21401}
21402
21403bool isVORPS(unsigned Opcode) {
21404 switch (Opcode) {
21405 case VORPSYrm:
21406 case VORPSYrr:
21407 case VORPSZ128rm:
21408 case VORPSZ128rmb:
21409 case VORPSZ128rmbk:
21410 case VORPSZ128rmbkz:
21411 case VORPSZ128rmk:
21412 case VORPSZ128rmkz:
21413 case VORPSZ128rr:
21414 case VORPSZ128rrk:
21415 case VORPSZ128rrkz:
21416 case VORPSZ256rm:
21417 case VORPSZ256rmb:
21418 case VORPSZ256rmbk:
21419 case VORPSZ256rmbkz:
21420 case VORPSZ256rmk:
21421 case VORPSZ256rmkz:
21422 case VORPSZ256rr:
21423 case VORPSZ256rrk:
21424 case VORPSZ256rrkz:
21425 case VORPSZrm:
21426 case VORPSZrmb:
21427 case VORPSZrmbk:
21428 case VORPSZrmbkz:
21429 case VORPSZrmk:
21430 case VORPSZrmkz:
21431 case VORPSZrr:
21432 case VORPSZrrk:
21433 case VORPSZrrkz:
21434 case VORPSrm:
21435 case VORPSrr:
21436 return true;
21437 }
21438 return false;
21439}
21440
21441bool isVPEXPANDQ(unsigned Opcode) {
21442 switch (Opcode) {
21443 case VPEXPANDQZ128rm:
21444 case VPEXPANDQZ128rmk:
21445 case VPEXPANDQZ128rmkz:
21446 case VPEXPANDQZ128rr:
21447 case VPEXPANDQZ128rrk:
21448 case VPEXPANDQZ128rrkz:
21449 case VPEXPANDQZ256rm:
21450 case VPEXPANDQZ256rmk:
21451 case VPEXPANDQZ256rmkz:
21452 case VPEXPANDQZ256rr:
21453 case VPEXPANDQZ256rrk:
21454 case VPEXPANDQZ256rrkz:
21455 case VPEXPANDQZrm:
21456 case VPEXPANDQZrmk:
21457 case VPEXPANDQZrmkz:
21458 case VPEXPANDQZrr:
21459 case VPEXPANDQZrrk:
21460 case VPEXPANDQZrrkz:
21461 return true;
21462 }
21463 return false;
21464}
21465
21466bool isVPSHRDD(unsigned Opcode) {
21467 switch (Opcode) {
21468 case VPSHRDDZ128rmbi:
21469 case VPSHRDDZ128rmbik:
21470 case VPSHRDDZ128rmbikz:
21471 case VPSHRDDZ128rmi:
21472 case VPSHRDDZ128rmik:
21473 case VPSHRDDZ128rmikz:
21474 case VPSHRDDZ128rri:
21475 case VPSHRDDZ128rrik:
21476 case VPSHRDDZ128rrikz:
21477 case VPSHRDDZ256rmbi:
21478 case VPSHRDDZ256rmbik:
21479 case VPSHRDDZ256rmbikz:
21480 case VPSHRDDZ256rmi:
21481 case VPSHRDDZ256rmik:
21482 case VPSHRDDZ256rmikz:
21483 case VPSHRDDZ256rri:
21484 case VPSHRDDZ256rrik:
21485 case VPSHRDDZ256rrikz:
21486 case VPSHRDDZrmbi:
21487 case VPSHRDDZrmbik:
21488 case VPSHRDDZrmbikz:
21489 case VPSHRDDZrmi:
21490 case VPSHRDDZrmik:
21491 case VPSHRDDZrmikz:
21492 case VPSHRDDZrri:
21493 case VPSHRDDZrrik:
21494 case VPSHRDDZrrikz:
21495 return true;
21496 }
21497 return false;
21498}
21499
21500bool isTDPBSSD(unsigned Opcode) {
21501 return Opcode == TDPBSSD;
21502}
21503
21504bool isTESTUI(unsigned Opcode) {
21505 return Opcode == TESTUI;
21506}
21507
21508bool isVFMADDPD(unsigned Opcode) {
21509 switch (Opcode) {
21510 case VFMADDPD4Ymr:
21511 case VFMADDPD4Yrm:
21512 case VFMADDPD4Yrr:
21513 case VFMADDPD4Yrr_REV:
21514 case VFMADDPD4mr:
21515 case VFMADDPD4rm:
21516 case VFMADDPD4rr:
21517 case VFMADDPD4rr_REV:
21518 return true;
21519 }
21520 return false;
21521}
21522
21523bool isVPANDND(unsigned Opcode) {
21524 switch (Opcode) {
21525 case VPANDNDZ128rm:
21526 case VPANDNDZ128rmb:
21527 case VPANDNDZ128rmbk:
21528 case VPANDNDZ128rmbkz:
21529 case VPANDNDZ128rmk:
21530 case VPANDNDZ128rmkz:
21531 case VPANDNDZ128rr:
21532 case VPANDNDZ128rrk:
21533 case VPANDNDZ128rrkz:
21534 case VPANDNDZ256rm:
21535 case VPANDNDZ256rmb:
21536 case VPANDNDZ256rmbk:
21537 case VPANDNDZ256rmbkz:
21538 case VPANDNDZ256rmk:
21539 case VPANDNDZ256rmkz:
21540 case VPANDNDZ256rr:
21541 case VPANDNDZ256rrk:
21542 case VPANDNDZ256rrkz:
21543 case VPANDNDZrm:
21544 case VPANDNDZrmb:
21545 case VPANDNDZrmbk:
21546 case VPANDNDZrmbkz:
21547 case VPANDNDZrmk:
21548 case VPANDNDZrmkz:
21549 case VPANDNDZrr:
21550 case VPANDNDZrrk:
21551 case VPANDNDZrrkz:
21552 return true;
21553 }
21554 return false;
21555}
21556
21557bool isVPMOVSDB(unsigned Opcode) {
21558 switch (Opcode) {
21559 case VPMOVSDBZ128mr:
21560 case VPMOVSDBZ128mrk:
21561 case VPMOVSDBZ128rr:
21562 case VPMOVSDBZ128rrk:
21563 case VPMOVSDBZ128rrkz:
21564 case VPMOVSDBZ256mr:
21565 case VPMOVSDBZ256mrk:
21566 case VPMOVSDBZ256rr:
21567 case VPMOVSDBZ256rrk:
21568 case VPMOVSDBZ256rrkz:
21569 case VPMOVSDBZmr:
21570 case VPMOVSDBZmrk:
21571 case VPMOVSDBZrr:
21572 case VPMOVSDBZrrk:
21573 case VPMOVSDBZrrkz:
21574 return true;
21575 }
21576 return false;
21577}
21578
21579bool isVPBROADCASTB(unsigned Opcode) {
21580 switch (Opcode) {
21581 case VPBROADCASTBYrm:
21582 case VPBROADCASTBYrr:
21583 case VPBROADCASTBZ128rm:
21584 case VPBROADCASTBZ128rmk:
21585 case VPBROADCASTBZ128rmkz:
21586 case VPBROADCASTBZ128rr:
21587 case VPBROADCASTBZ128rrk:
21588 case VPBROADCASTBZ128rrkz:
21589 case VPBROADCASTBZ256rm:
21590 case VPBROADCASTBZ256rmk:
21591 case VPBROADCASTBZ256rmkz:
21592 case VPBROADCASTBZ256rr:
21593 case VPBROADCASTBZ256rrk:
21594 case VPBROADCASTBZ256rrkz:
21595 case VPBROADCASTBZrm:
21596 case VPBROADCASTBZrmk:
21597 case VPBROADCASTBZrmkz:
21598 case VPBROADCASTBZrr:
21599 case VPBROADCASTBZrrk:
21600 case VPBROADCASTBZrrkz:
21601 case VPBROADCASTBrZ128rr:
21602 case VPBROADCASTBrZ128rrk:
21603 case VPBROADCASTBrZ128rrkz:
21604 case VPBROADCASTBrZ256rr:
21605 case VPBROADCASTBrZ256rrk:
21606 case VPBROADCASTBrZ256rrkz:
21607 case VPBROADCASTBrZrr:
21608 case VPBROADCASTBrZrrk:
21609 case VPBROADCASTBrZrrkz:
21610 case VPBROADCASTBrm:
21611 case VPBROADCASTBrr:
21612 return true;
21613 }
21614 return false;
21615}
21616
21617bool isCVTPI2PD(unsigned Opcode) {
21618 switch (Opcode) {
21619 case MMX_CVTPI2PDrm:
21620 case MMX_CVTPI2PDrr:
21621 return true;
21622 }
21623 return false;
21624}
21625
21626bool isVPERMI2B(unsigned Opcode) {
21627 switch (Opcode) {
21628 case VPERMI2BZ128rm:
21629 case VPERMI2BZ128rmk:
21630 case VPERMI2BZ128rmkz:
21631 case VPERMI2BZ128rr:
21632 case VPERMI2BZ128rrk:
21633 case VPERMI2BZ128rrkz:
21634 case VPERMI2BZ256rm:
21635 case VPERMI2BZ256rmk:
21636 case VPERMI2BZ256rmkz:
21637 case VPERMI2BZ256rr:
21638 case VPERMI2BZ256rrk:
21639 case VPERMI2BZ256rrkz:
21640 case VPERMI2BZrm:
21641 case VPERMI2BZrmk:
21642 case VPERMI2BZrmkz:
21643 case VPERMI2BZrr:
21644 case VPERMI2BZrrk:
21645 case VPERMI2BZrrkz:
21646 return true;
21647 }
21648 return false;
21649}
21650
21651bool isVPMINSB(unsigned Opcode) {
21652 switch (Opcode) {
21653 case VPMINSBYrm:
21654 case VPMINSBYrr:
21655 case VPMINSBZ128rm:
21656 case VPMINSBZ128rmk:
21657 case VPMINSBZ128rmkz:
21658 case VPMINSBZ128rr:
21659 case VPMINSBZ128rrk:
21660 case VPMINSBZ128rrkz:
21661 case VPMINSBZ256rm:
21662 case VPMINSBZ256rmk:
21663 case VPMINSBZ256rmkz:
21664 case VPMINSBZ256rr:
21665 case VPMINSBZ256rrk:
21666 case VPMINSBZ256rrkz:
21667 case VPMINSBZrm:
21668 case VPMINSBZrmk:
21669 case VPMINSBZrmkz:
21670 case VPMINSBZrr:
21671 case VPMINSBZrrk:
21672 case VPMINSBZrrkz:
21673 case VPMINSBrm:
21674 case VPMINSBrr:
21675 return true;
21676 }
21677 return false;
21678}
21679
21680bool isLAR(unsigned Opcode) {
21681 switch (Opcode) {
21682 case LAR16rm:
21683 case LAR16rr:
21684 case LAR32rm:
21685 case LAR32rr:
21686 case LAR64rm:
21687 case LAR64rr:
21688 return true;
21689 }
21690 return false;
21691}
21692
21693bool isINVLPGB(unsigned Opcode) {
21694 switch (Opcode) {
21695 case INVLPGB32:
21696 case INVLPGB64:
21697 return true;
21698 }
21699 return false;
21700}
21701
21702bool isTLBSYNC(unsigned Opcode) {
21703 return Opcode == TLBSYNC;
21704}
21705
21706bool isFDIVP(unsigned Opcode) {
21707 return Opcode == DIV_FPrST0;
21708}
21709
21710bool isVPSRLW(unsigned Opcode) {
21711 switch (Opcode) {
21712 case VPSRLWYri:
21713 case VPSRLWYrm:
21714 case VPSRLWYrr:
21715 case VPSRLWZ128mi:
21716 case VPSRLWZ128mik:
21717 case VPSRLWZ128mikz:
21718 case VPSRLWZ128ri:
21719 case VPSRLWZ128rik:
21720 case VPSRLWZ128rikz:
21721 case VPSRLWZ128rm:
21722 case VPSRLWZ128rmk:
21723 case VPSRLWZ128rmkz:
21724 case VPSRLWZ128rr:
21725 case VPSRLWZ128rrk:
21726 case VPSRLWZ128rrkz:
21727 case VPSRLWZ256mi:
21728 case VPSRLWZ256mik:
21729 case VPSRLWZ256mikz:
21730 case VPSRLWZ256ri:
21731 case VPSRLWZ256rik:
21732 case VPSRLWZ256rikz:
21733 case VPSRLWZ256rm:
21734 case VPSRLWZ256rmk:
21735 case VPSRLWZ256rmkz:
21736 case VPSRLWZ256rr:
21737 case VPSRLWZ256rrk:
21738 case VPSRLWZ256rrkz:
21739 case VPSRLWZmi:
21740 case VPSRLWZmik:
21741 case VPSRLWZmikz:
21742 case VPSRLWZri:
21743 case VPSRLWZrik:
21744 case VPSRLWZrikz:
21745 case VPSRLWZrm:
21746 case VPSRLWZrmk:
21747 case VPSRLWZrmkz:
21748 case VPSRLWZrr:
21749 case VPSRLWZrrk:
21750 case VPSRLWZrrkz:
21751 case VPSRLWri:
21752 case VPSRLWrm:
21753 case VPSRLWrr:
21754 return true;
21755 }
21756 return false;
21757}
21758
21759bool isVRCP28SS(unsigned Opcode) {
21760 switch (Opcode) {
21761 case VRCP28SSZm:
21762 case VRCP28SSZmk:
21763 case VRCP28SSZmkz:
21764 case VRCP28SSZr:
21765 case VRCP28SSZrb:
21766 case VRCP28SSZrbk:
21767 case VRCP28SSZrbkz:
21768 case VRCP28SSZrk:
21769 case VRCP28SSZrkz:
21770 return true;
21771 }
21772 return false;
21773}
21774
21775bool isVMOVHPS(unsigned Opcode) {
21776 switch (Opcode) {
21777 case VMOVHPSZ128mr:
21778 case VMOVHPSZ128rm:
21779 case VMOVHPSmr:
21780 case VMOVHPSrm:
21781 return true;
21782 }
21783 return false;
21784}
21785
21786bool isVPMACSSDD(unsigned Opcode) {
21787 switch (Opcode) {
21788 case VPMACSSDDrm:
21789 case VPMACSSDDrr:
21790 return true;
21791 }
21792 return false;
21793}
21794
21795bool isPEXT(unsigned Opcode) {
21796 switch (Opcode) {
21797 case PEXT32rm:
21798 case PEXT32rm_EVEX:
21799 case PEXT32rr:
21800 case PEXT32rr_EVEX:
21801 case PEXT64rm:
21802 case PEXT64rm_EVEX:
21803 case PEXT64rr:
21804 case PEXT64rr_EVEX:
21805 return true;
21806 }
21807 return false;
21808}
21809
21810bool isVMAXBF16(unsigned Opcode) {
21811 switch (Opcode) {
21812 case VMAXBF16Z128rm:
21813 case VMAXBF16Z128rmb:
21814 case VMAXBF16Z128rmbk:
21815 case VMAXBF16Z128rmbkz:
21816 case VMAXBF16Z128rmk:
21817 case VMAXBF16Z128rmkz:
21818 case VMAXBF16Z128rr:
21819 case VMAXBF16Z128rrk:
21820 case VMAXBF16Z128rrkz:
21821 case VMAXBF16Z256rm:
21822 case VMAXBF16Z256rmb:
21823 case VMAXBF16Z256rmbk:
21824 case VMAXBF16Z256rmbkz:
21825 case VMAXBF16Z256rmk:
21826 case VMAXBF16Z256rmkz:
21827 case VMAXBF16Z256rr:
21828 case VMAXBF16Z256rrk:
21829 case VMAXBF16Z256rrkz:
21830 case VMAXBF16Zrm:
21831 case VMAXBF16Zrmb:
21832 case VMAXBF16Zrmbk:
21833 case VMAXBF16Zrmbkz:
21834 case VMAXBF16Zrmk:
21835 case VMAXBF16Zrmkz:
21836 case VMAXBF16Zrr:
21837 case VMAXBF16Zrrk:
21838 case VMAXBF16Zrrkz:
21839 return true;
21840 }
21841 return false;
21842}
21843
21844bool isVRSQRT14SD(unsigned Opcode) {
21845 switch (Opcode) {
21846 case VRSQRT14SDZrm:
21847 case VRSQRT14SDZrmk:
21848 case VRSQRT14SDZrmkz:
21849 case VRSQRT14SDZrr:
21850 case VRSQRT14SDZrrk:
21851 case VRSQRT14SDZrrkz:
21852 return true;
21853 }
21854 return false;
21855}
21856
21857bool isVPDPWSSD(unsigned Opcode) {
21858 switch (Opcode) {
21859 case VPDPWSSDYrm:
21860 case VPDPWSSDYrr:
21861 case VPDPWSSDZ128rm:
21862 case VPDPWSSDZ128rmb:
21863 case VPDPWSSDZ128rmbk:
21864 case VPDPWSSDZ128rmbkz:
21865 case VPDPWSSDZ128rmk:
21866 case VPDPWSSDZ128rmkz:
21867 case VPDPWSSDZ128rr:
21868 case VPDPWSSDZ128rrk:
21869 case VPDPWSSDZ128rrkz:
21870 case VPDPWSSDZ256rm:
21871 case VPDPWSSDZ256rmb:
21872 case VPDPWSSDZ256rmbk:
21873 case VPDPWSSDZ256rmbkz:
21874 case VPDPWSSDZ256rmk:
21875 case VPDPWSSDZ256rmkz:
21876 case VPDPWSSDZ256rr:
21877 case VPDPWSSDZ256rrk:
21878 case VPDPWSSDZ256rrkz:
21879 case VPDPWSSDZrm:
21880 case VPDPWSSDZrmb:
21881 case VPDPWSSDZrmbk:
21882 case VPDPWSSDZrmbkz:
21883 case VPDPWSSDZrmk:
21884 case VPDPWSSDZrmkz:
21885 case VPDPWSSDZrr:
21886 case VPDPWSSDZrrk:
21887 case VPDPWSSDZrrkz:
21888 case VPDPWSSDrm:
21889 case VPDPWSSDrr:
21890 return true;
21891 }
21892 return false;
21893}
21894
21895bool isVFMSUB231SD(unsigned Opcode) {
21896 switch (Opcode) {
21897 case VFMSUB231SDZm_Int:
21898 case VFMSUB231SDZmk_Int:
21899 case VFMSUB231SDZmkz_Int:
21900 case VFMSUB231SDZr_Int:
21901 case VFMSUB231SDZrb_Int:
21902 case VFMSUB231SDZrbk_Int:
21903 case VFMSUB231SDZrbkz_Int:
21904 case VFMSUB231SDZrk_Int:
21905 case VFMSUB231SDZrkz_Int:
21906 case VFMSUB231SDm_Int:
21907 case VFMSUB231SDr_Int:
21908 return true;
21909 }
21910 return false;
21911}
21912
21913bool isVPMOVZXWQ(unsigned Opcode) {
21914 switch (Opcode) {
21915 case VPMOVZXWQYrm:
21916 case VPMOVZXWQYrr:
21917 case VPMOVZXWQZ128rm:
21918 case VPMOVZXWQZ128rmk:
21919 case VPMOVZXWQZ128rmkz:
21920 case VPMOVZXWQZ128rr:
21921 case VPMOVZXWQZ128rrk:
21922 case VPMOVZXWQZ128rrkz:
21923 case VPMOVZXWQZ256rm:
21924 case VPMOVZXWQZ256rmk:
21925 case VPMOVZXWQZ256rmkz:
21926 case VPMOVZXWQZ256rr:
21927 case VPMOVZXWQZ256rrk:
21928 case VPMOVZXWQZ256rrkz:
21929 case VPMOVZXWQZrm:
21930 case VPMOVZXWQZrmk:
21931 case VPMOVZXWQZrmkz:
21932 case VPMOVZXWQZrr:
21933 case VPMOVZXWQZrrk:
21934 case VPMOVZXWQZrrkz:
21935 case VPMOVZXWQrm:
21936 case VPMOVZXWQrr:
21937 return true;
21938 }
21939 return false;
21940}
21941
21942bool isVMOVDQA(unsigned Opcode) {
21943 switch (Opcode) {
21944 case VMOVDQAYmr:
21945 case VMOVDQAYrm:
21946 case VMOVDQAYrr:
21947 case VMOVDQAYrr_REV:
21948 case VMOVDQAmr:
21949 case VMOVDQArm:
21950 case VMOVDQArr:
21951 case VMOVDQArr_REV:
21952 return true;
21953 }
21954 return false;
21955}
21956
21957bool isVFNMSUB213SD(unsigned Opcode) {
21958 switch (Opcode) {
21959 case VFNMSUB213SDZm_Int:
21960 case VFNMSUB213SDZmk_Int:
21961 case VFNMSUB213SDZmkz_Int:
21962 case VFNMSUB213SDZr_Int:
21963 case VFNMSUB213SDZrb_Int:
21964 case VFNMSUB213SDZrbk_Int:
21965 case VFNMSUB213SDZrbkz_Int:
21966 case VFNMSUB213SDZrk_Int:
21967 case VFNMSUB213SDZrkz_Int:
21968 case VFNMSUB213SDm_Int:
21969 case VFNMSUB213SDr_Int:
21970 return true;
21971 }
21972 return false;
21973}
21974
21975bool isVMINPS(unsigned Opcode) {
21976 switch (Opcode) {
21977 case VMINPSYrm:
21978 case VMINPSYrr:
21979 case VMINPSZ128rm:
21980 case VMINPSZ128rmb:
21981 case VMINPSZ128rmbk:
21982 case VMINPSZ128rmbkz:
21983 case VMINPSZ128rmk:
21984 case VMINPSZ128rmkz:
21985 case VMINPSZ128rr:
21986 case VMINPSZ128rrk:
21987 case VMINPSZ128rrkz:
21988 case VMINPSZ256rm:
21989 case VMINPSZ256rmb:
21990 case VMINPSZ256rmbk:
21991 case VMINPSZ256rmbkz:
21992 case VMINPSZ256rmk:
21993 case VMINPSZ256rmkz:
21994 case VMINPSZ256rr:
21995 case VMINPSZ256rrk:
21996 case VMINPSZ256rrkz:
21997 case VMINPSZrm:
21998 case VMINPSZrmb:
21999 case VMINPSZrmbk:
22000 case VMINPSZrmbkz:
22001 case VMINPSZrmk:
22002 case VMINPSZrmkz:
22003 case VMINPSZrr:
22004 case VMINPSZrrb:
22005 case VMINPSZrrbk:
22006 case VMINPSZrrbkz:
22007 case VMINPSZrrk:
22008 case VMINPSZrrkz:
22009 case VMINPSrm:
22010 case VMINPSrr:
22011 return true;
22012 }
22013 return false;
22014}
22015
22016bool isVFMSUB231PS(unsigned Opcode) {
22017 switch (Opcode) {
22018 case VFMSUB231PSYm:
22019 case VFMSUB231PSYr:
22020 case VFMSUB231PSZ128m:
22021 case VFMSUB231PSZ128mb:
22022 case VFMSUB231PSZ128mbk:
22023 case VFMSUB231PSZ128mbkz:
22024 case VFMSUB231PSZ128mk:
22025 case VFMSUB231PSZ128mkz:
22026 case VFMSUB231PSZ128r:
22027 case VFMSUB231PSZ128rk:
22028 case VFMSUB231PSZ128rkz:
22029 case VFMSUB231PSZ256m:
22030 case VFMSUB231PSZ256mb:
22031 case VFMSUB231PSZ256mbk:
22032 case VFMSUB231PSZ256mbkz:
22033 case VFMSUB231PSZ256mk:
22034 case VFMSUB231PSZ256mkz:
22035 case VFMSUB231PSZ256r:
22036 case VFMSUB231PSZ256rk:
22037 case VFMSUB231PSZ256rkz:
22038 case VFMSUB231PSZm:
22039 case VFMSUB231PSZmb:
22040 case VFMSUB231PSZmbk:
22041 case VFMSUB231PSZmbkz:
22042 case VFMSUB231PSZmk:
22043 case VFMSUB231PSZmkz:
22044 case VFMSUB231PSZr:
22045 case VFMSUB231PSZrb:
22046 case VFMSUB231PSZrbk:
22047 case VFMSUB231PSZrbkz:
22048 case VFMSUB231PSZrk:
22049 case VFMSUB231PSZrkz:
22050 case VFMSUB231PSm:
22051 case VFMSUB231PSr:
22052 return true;
22053 }
22054 return false;
22055}
22056
22057bool isVPCOMPRESSB(unsigned Opcode) {
22058 switch (Opcode) {
22059 case VPCOMPRESSBZ128mr:
22060 case VPCOMPRESSBZ128mrk:
22061 case VPCOMPRESSBZ128rr:
22062 case VPCOMPRESSBZ128rrk:
22063 case VPCOMPRESSBZ128rrkz:
22064 case VPCOMPRESSBZ256mr:
22065 case VPCOMPRESSBZ256mrk:
22066 case VPCOMPRESSBZ256rr:
22067 case VPCOMPRESSBZ256rrk:
22068 case VPCOMPRESSBZ256rrkz:
22069 case VPCOMPRESSBZmr:
22070 case VPCOMPRESSBZmrk:
22071 case VPCOMPRESSBZrr:
22072 case VPCOMPRESSBZrrk:
22073 case VPCOMPRESSBZrrkz:
22074 return true;
22075 }
22076 return false;
22077}
22078
22079bool isVPCMPEQQ(unsigned Opcode) {
22080 switch (Opcode) {
22081 case VPCMPEQQYrm:
22082 case VPCMPEQQYrr:
22083 case VPCMPEQQZ128rm:
22084 case VPCMPEQQZ128rmb:
22085 case VPCMPEQQZ128rmbk:
22086 case VPCMPEQQZ128rmk:
22087 case VPCMPEQQZ128rr:
22088 case VPCMPEQQZ128rrk:
22089 case VPCMPEQQZ256rm:
22090 case VPCMPEQQZ256rmb:
22091 case VPCMPEQQZ256rmbk:
22092 case VPCMPEQQZ256rmk:
22093 case VPCMPEQQZ256rr:
22094 case VPCMPEQQZ256rrk:
22095 case VPCMPEQQZrm:
22096 case VPCMPEQQZrmb:
22097 case VPCMPEQQZrmbk:
22098 case VPCMPEQQZrmk:
22099 case VPCMPEQQZrr:
22100 case VPCMPEQQZrrk:
22101 case VPCMPEQQrm:
22102 case VPCMPEQQrr:
22103 return true;
22104 }
22105 return false;
22106}
22107
22108bool isVRCPSS(unsigned Opcode) {
22109 switch (Opcode) {
22110 case VRCPSSm_Int:
22111 case VRCPSSr_Int:
22112 return true;
22113 }
22114 return false;
22115}
22116
22117bool isVSCATTERPF1DPS(unsigned Opcode) {
22118 return Opcode == VSCATTERPF1DPSm;
22119}
22120
22121bool isVPHADDUBW(unsigned Opcode) {
22122 switch (Opcode) {
22123 case VPHADDUBWrm:
22124 case VPHADDUBWrr:
22125 return true;
22126 }
22127 return false;
22128}
22129
22130bool isXORPD(unsigned Opcode) {
22131 switch (Opcode) {
22132 case XORPDrm:
22133 case XORPDrr:
22134 return true;
22135 }
22136 return false;
22137}
22138
22139bool isVPSCATTERQQ(unsigned Opcode) {
22140 switch (Opcode) {
22141 case VPSCATTERQQZ128mr:
22142 case VPSCATTERQQZ256mr:
22143 case VPSCATTERQQZmr:
22144 return true;
22145 }
22146 return false;
22147}
22148
22149bool isVCVTW2PH(unsigned Opcode) {
22150 switch (Opcode) {
22151 case VCVTW2PHZ128rm:
22152 case VCVTW2PHZ128rmb:
22153 case VCVTW2PHZ128rmbk:
22154 case VCVTW2PHZ128rmbkz:
22155 case VCVTW2PHZ128rmk:
22156 case VCVTW2PHZ128rmkz:
22157 case VCVTW2PHZ128rr:
22158 case VCVTW2PHZ128rrk:
22159 case VCVTW2PHZ128rrkz:
22160 case VCVTW2PHZ256rm:
22161 case VCVTW2PHZ256rmb:
22162 case VCVTW2PHZ256rmbk:
22163 case VCVTW2PHZ256rmbkz:
22164 case VCVTW2PHZ256rmk:
22165 case VCVTW2PHZ256rmkz:
22166 case VCVTW2PHZ256rr:
22167 case VCVTW2PHZ256rrk:
22168 case VCVTW2PHZ256rrkz:
22169 case VCVTW2PHZrm:
22170 case VCVTW2PHZrmb:
22171 case VCVTW2PHZrmbk:
22172 case VCVTW2PHZrmbkz:
22173 case VCVTW2PHZrmk:
22174 case VCVTW2PHZrmkz:
22175 case VCVTW2PHZrr:
22176 case VCVTW2PHZrrb:
22177 case VCVTW2PHZrrbk:
22178 case VCVTW2PHZrrbkz:
22179 case VCVTW2PHZrrk:
22180 case VCVTW2PHZrrkz:
22181 return true;
22182 }
22183 return false;
22184}
22185
22186bool isVFMADDCPH(unsigned Opcode) {
22187 switch (Opcode) {
22188 case VFMADDCPHZ128m:
22189 case VFMADDCPHZ128mb:
22190 case VFMADDCPHZ128mbk:
22191 case VFMADDCPHZ128mbkz:
22192 case VFMADDCPHZ128mk:
22193 case VFMADDCPHZ128mkz:
22194 case VFMADDCPHZ128r:
22195 case VFMADDCPHZ128rk:
22196 case VFMADDCPHZ128rkz:
22197 case VFMADDCPHZ256m:
22198 case VFMADDCPHZ256mb:
22199 case VFMADDCPHZ256mbk:
22200 case VFMADDCPHZ256mbkz:
22201 case VFMADDCPHZ256mk:
22202 case VFMADDCPHZ256mkz:
22203 case VFMADDCPHZ256r:
22204 case VFMADDCPHZ256rk:
22205 case VFMADDCPHZ256rkz:
22206 case VFMADDCPHZm:
22207 case VFMADDCPHZmb:
22208 case VFMADDCPHZmbk:
22209 case VFMADDCPHZmbkz:
22210 case VFMADDCPHZmk:
22211 case VFMADDCPHZmkz:
22212 case VFMADDCPHZr:
22213 case VFMADDCPHZrb:
22214 case VFMADDCPHZrbk:
22215 case VFMADDCPHZrbkz:
22216 case VFMADDCPHZrk:
22217 case VFMADDCPHZrkz:
22218 return true;
22219 }
22220 return false;
22221}
22222
22223bool isVSUBPD(unsigned Opcode) {
22224 switch (Opcode) {
22225 case VSUBPDYrm:
22226 case VSUBPDYrr:
22227 case VSUBPDZ128rm:
22228 case VSUBPDZ128rmb:
22229 case VSUBPDZ128rmbk:
22230 case VSUBPDZ128rmbkz:
22231 case VSUBPDZ128rmk:
22232 case VSUBPDZ128rmkz:
22233 case VSUBPDZ128rr:
22234 case VSUBPDZ128rrk:
22235 case VSUBPDZ128rrkz:
22236 case VSUBPDZ256rm:
22237 case VSUBPDZ256rmb:
22238 case VSUBPDZ256rmbk:
22239 case VSUBPDZ256rmbkz:
22240 case VSUBPDZ256rmk:
22241 case VSUBPDZ256rmkz:
22242 case VSUBPDZ256rr:
22243 case VSUBPDZ256rrk:
22244 case VSUBPDZ256rrkz:
22245 case VSUBPDZrm:
22246 case VSUBPDZrmb:
22247 case VSUBPDZrmbk:
22248 case VSUBPDZrmbkz:
22249 case VSUBPDZrmk:
22250 case VSUBPDZrmkz:
22251 case VSUBPDZrr:
22252 case VSUBPDZrrb:
22253 case VSUBPDZrrbk:
22254 case VSUBPDZrrbkz:
22255 case VSUBPDZrrk:
22256 case VSUBPDZrrkz:
22257 case VSUBPDrm:
22258 case VSUBPDrr:
22259 return true;
22260 }
22261 return false;
22262}
22263
22264bool isVPACKUSDW(unsigned Opcode) {
22265 switch (Opcode) {
22266 case VPACKUSDWYrm:
22267 case VPACKUSDWYrr:
22268 case VPACKUSDWZ128rm:
22269 case VPACKUSDWZ128rmb:
22270 case VPACKUSDWZ128rmbk:
22271 case VPACKUSDWZ128rmbkz:
22272 case VPACKUSDWZ128rmk:
22273 case VPACKUSDWZ128rmkz:
22274 case VPACKUSDWZ128rr:
22275 case VPACKUSDWZ128rrk:
22276 case VPACKUSDWZ128rrkz:
22277 case VPACKUSDWZ256rm:
22278 case VPACKUSDWZ256rmb:
22279 case VPACKUSDWZ256rmbk:
22280 case VPACKUSDWZ256rmbkz:
22281 case VPACKUSDWZ256rmk:
22282 case VPACKUSDWZ256rmkz:
22283 case VPACKUSDWZ256rr:
22284 case VPACKUSDWZ256rrk:
22285 case VPACKUSDWZ256rrkz:
22286 case VPACKUSDWZrm:
22287 case VPACKUSDWZrmb:
22288 case VPACKUSDWZrmbk:
22289 case VPACKUSDWZrmbkz:
22290 case VPACKUSDWZrmk:
22291 case VPACKUSDWZrmkz:
22292 case VPACKUSDWZrr:
22293 case VPACKUSDWZrrk:
22294 case VPACKUSDWZrrkz:
22295 case VPACKUSDWrm:
22296 case VPACKUSDWrr:
22297 return true;
22298 }
22299 return false;
22300}
22301
22302bool isVSCALEFSS(unsigned Opcode) {
22303 switch (Opcode) {
22304 case VSCALEFSSZrm:
22305 case VSCALEFSSZrmk:
22306 case VSCALEFSSZrmkz:
22307 case VSCALEFSSZrr:
22308 case VSCALEFSSZrrb_Int:
22309 case VSCALEFSSZrrbk_Int:
22310 case VSCALEFSSZrrbkz_Int:
22311 case VSCALEFSSZrrk:
22312 case VSCALEFSSZrrkz:
22313 return true;
22314 }
22315 return false;
22316}
22317
22318bool isAESIMC(unsigned Opcode) {
22319 switch (Opcode) {
22320 case AESIMCrm:
22321 case AESIMCrr:
22322 return true;
22323 }
22324 return false;
22325}
22326
22327bool isVRCP28PS(unsigned Opcode) {
22328 switch (Opcode) {
22329 case VRCP28PSZm:
22330 case VRCP28PSZmb:
22331 case VRCP28PSZmbk:
22332 case VRCP28PSZmbkz:
22333 case VRCP28PSZmk:
22334 case VRCP28PSZmkz:
22335 case VRCP28PSZr:
22336 case VRCP28PSZrb:
22337 case VRCP28PSZrbk:
22338 case VRCP28PSZrbkz:
22339 case VRCP28PSZrk:
22340 case VRCP28PSZrkz:
22341 return true;
22342 }
22343 return false;
22344}
22345
22346bool isAAND(unsigned Opcode) {
22347 switch (Opcode) {
22348 case AAND32mr:
22349 case AAND32mr_EVEX:
22350 case AAND64mr:
22351 case AAND64mr_EVEX:
22352 return true;
22353 }
22354 return false;
22355}
22356
22357bool isDAA(unsigned Opcode) {
22358 return Opcode == DAA;
22359}
22360
22361bool isVCVTPD2UDQ(unsigned Opcode) {
22362 switch (Opcode) {
22363 case VCVTPD2UDQZ128rm:
22364 case VCVTPD2UDQZ128rmb:
22365 case VCVTPD2UDQZ128rmbk:
22366 case VCVTPD2UDQZ128rmbkz:
22367 case VCVTPD2UDQZ128rmk:
22368 case VCVTPD2UDQZ128rmkz:
22369 case VCVTPD2UDQZ128rr:
22370 case VCVTPD2UDQZ128rrk:
22371 case VCVTPD2UDQZ128rrkz:
22372 case VCVTPD2UDQZ256rm:
22373 case VCVTPD2UDQZ256rmb:
22374 case VCVTPD2UDQZ256rmbk:
22375 case VCVTPD2UDQZ256rmbkz:
22376 case VCVTPD2UDQZ256rmk:
22377 case VCVTPD2UDQZ256rmkz:
22378 case VCVTPD2UDQZ256rr:
22379 case VCVTPD2UDQZ256rrk:
22380 case VCVTPD2UDQZ256rrkz:
22381 case VCVTPD2UDQZrm:
22382 case VCVTPD2UDQZrmb:
22383 case VCVTPD2UDQZrmbk:
22384 case VCVTPD2UDQZrmbkz:
22385 case VCVTPD2UDQZrmk:
22386 case VCVTPD2UDQZrmkz:
22387 case VCVTPD2UDQZrr:
22388 case VCVTPD2UDQZrrb:
22389 case VCVTPD2UDQZrrbk:
22390 case VCVTPD2UDQZrrbkz:
22391 case VCVTPD2UDQZrrk:
22392 case VCVTPD2UDQZrrkz:
22393 return true;
22394 }
22395 return false;
22396}
22397
22398bool isKTESTW(unsigned Opcode) {
22399 return Opcode == KTESTWkk;
22400}
22401
22402bool isVPADDQ(unsigned Opcode) {
22403 switch (Opcode) {
22404 case VPADDQYrm:
22405 case VPADDQYrr:
22406 case VPADDQZ128rm:
22407 case VPADDQZ128rmb:
22408 case VPADDQZ128rmbk:
22409 case VPADDQZ128rmbkz:
22410 case VPADDQZ128rmk:
22411 case VPADDQZ128rmkz:
22412 case VPADDQZ128rr:
22413 case VPADDQZ128rrk:
22414 case VPADDQZ128rrkz:
22415 case VPADDQZ256rm:
22416 case VPADDQZ256rmb:
22417 case VPADDQZ256rmbk:
22418 case VPADDQZ256rmbkz:
22419 case VPADDQZ256rmk:
22420 case VPADDQZ256rmkz:
22421 case VPADDQZ256rr:
22422 case VPADDQZ256rrk:
22423 case VPADDQZ256rrkz:
22424 case VPADDQZrm:
22425 case VPADDQZrmb:
22426 case VPADDQZrmbk:
22427 case VPADDQZrmbkz:
22428 case VPADDQZrmk:
22429 case VPADDQZrmkz:
22430 case VPADDQZrr:
22431 case VPADDQZrrk:
22432 case VPADDQZrrkz:
22433 case VPADDQrm:
22434 case VPADDQrr:
22435 return true;
22436 }
22437 return false;
22438}
22439
22440bool isPALIGNR(unsigned Opcode) {
22441 switch (Opcode) {
22442 case MMX_PALIGNRrmi:
22443 case MMX_PALIGNRrri:
22444 case PALIGNRrmi:
22445 case PALIGNRrri:
22446 return true;
22447 }
22448 return false;
22449}
22450
22451bool isPMAXUW(unsigned Opcode) {
22452 switch (Opcode) {
22453 case PMAXUWrm:
22454 case PMAXUWrr:
22455 return true;
22456 }
22457 return false;
22458}
22459
22460bool isVFMADDSD(unsigned Opcode) {
22461 switch (Opcode) {
22462 case VFMADDSD4mr:
22463 case VFMADDSD4rm:
22464 case VFMADDSD4rr:
22465 case VFMADDSD4rr_REV:
22466 return true;
22467 }
22468 return false;
22469}
22470
22471bool isPFMAX(unsigned Opcode) {
22472 switch (Opcode) {
22473 case PFMAXrm:
22474 case PFMAXrr:
22475 return true;
22476 }
22477 return false;
22478}
22479
22480bool isVPOR(unsigned Opcode) {
22481 switch (Opcode) {
22482 case VPORYrm:
22483 case VPORYrr:
22484 case VPORrm:
22485 case VPORrr:
22486 return true;
22487 }
22488 return false;
22489}
22490
22491bool isVPSUBB(unsigned Opcode) {
22492 switch (Opcode) {
22493 case VPSUBBYrm:
22494 case VPSUBBYrr:
22495 case VPSUBBZ128rm:
22496 case VPSUBBZ128rmk:
22497 case VPSUBBZ128rmkz:
22498 case VPSUBBZ128rr:
22499 case VPSUBBZ128rrk:
22500 case VPSUBBZ128rrkz:
22501 case VPSUBBZ256rm:
22502 case VPSUBBZ256rmk:
22503 case VPSUBBZ256rmkz:
22504 case VPSUBBZ256rr:
22505 case VPSUBBZ256rrk:
22506 case VPSUBBZ256rrkz:
22507 case VPSUBBZrm:
22508 case VPSUBBZrmk:
22509 case VPSUBBZrmkz:
22510 case VPSUBBZrr:
22511 case VPSUBBZrrk:
22512 case VPSUBBZrrkz:
22513 case VPSUBBrm:
22514 case VPSUBBrr:
22515 return true;
22516 }
22517 return false;
22518}
22519
22520bool isVPAVGB(unsigned Opcode) {
22521 switch (Opcode) {
22522 case VPAVGBYrm:
22523 case VPAVGBYrr:
22524 case VPAVGBZ128rm:
22525 case VPAVGBZ128rmk:
22526 case VPAVGBZ128rmkz:
22527 case VPAVGBZ128rr:
22528 case VPAVGBZ128rrk:
22529 case VPAVGBZ128rrkz:
22530 case VPAVGBZ256rm:
22531 case VPAVGBZ256rmk:
22532 case VPAVGBZ256rmkz:
22533 case VPAVGBZ256rr:
22534 case VPAVGBZ256rrk:
22535 case VPAVGBZ256rrkz:
22536 case VPAVGBZrm:
22537 case VPAVGBZrmk:
22538 case VPAVGBZrmkz:
22539 case VPAVGBZrr:
22540 case VPAVGBZrrk:
22541 case VPAVGBZrrkz:
22542 case VPAVGBrm:
22543 case VPAVGBrr:
22544 return true;
22545 }
22546 return false;
22547}
22548
22549bool isINSB(unsigned Opcode) {
22550 return Opcode == INSB;
22551}
22552
22553bool isFYL2X(unsigned Opcode) {
22554 return Opcode == FYL2X;
22555}
22556
22557bool isVFNMSUB132PD(unsigned Opcode) {
22558 switch (Opcode) {
22559 case VFNMSUB132PDYm:
22560 case VFNMSUB132PDYr:
22561 case VFNMSUB132PDZ128m:
22562 case VFNMSUB132PDZ128mb:
22563 case VFNMSUB132PDZ128mbk:
22564 case VFNMSUB132PDZ128mbkz:
22565 case VFNMSUB132PDZ128mk:
22566 case VFNMSUB132PDZ128mkz:
22567 case VFNMSUB132PDZ128r:
22568 case VFNMSUB132PDZ128rk:
22569 case VFNMSUB132PDZ128rkz:
22570 case VFNMSUB132PDZ256m:
22571 case VFNMSUB132PDZ256mb:
22572 case VFNMSUB132PDZ256mbk:
22573 case VFNMSUB132PDZ256mbkz:
22574 case VFNMSUB132PDZ256mk:
22575 case VFNMSUB132PDZ256mkz:
22576 case VFNMSUB132PDZ256r:
22577 case VFNMSUB132PDZ256rk:
22578 case VFNMSUB132PDZ256rkz:
22579 case VFNMSUB132PDZm:
22580 case VFNMSUB132PDZmb:
22581 case VFNMSUB132PDZmbk:
22582 case VFNMSUB132PDZmbkz:
22583 case VFNMSUB132PDZmk:
22584 case VFNMSUB132PDZmkz:
22585 case VFNMSUB132PDZr:
22586 case VFNMSUB132PDZrb:
22587 case VFNMSUB132PDZrbk:
22588 case VFNMSUB132PDZrbkz:
22589 case VFNMSUB132PDZrk:
22590 case VFNMSUB132PDZrkz:
22591 case VFNMSUB132PDm:
22592 case VFNMSUB132PDr:
22593 return true;
22594 }
22595 return false;
22596}
22597
22598bool isVFNMSUBPS(unsigned Opcode) {
22599 switch (Opcode) {
22600 case VFNMSUBPS4Ymr:
22601 case VFNMSUBPS4Yrm:
22602 case VFNMSUBPS4Yrr:
22603 case VFNMSUBPS4Yrr_REV:
22604 case VFNMSUBPS4mr:
22605 case VFNMSUBPS4rm:
22606 case VFNMSUBPS4rr:
22607 case VFNMSUBPS4rr_REV:
22608 return true;
22609 }
22610 return false;
22611}
22612
22613bool isVFMADD231PS(unsigned Opcode) {
22614 switch (Opcode) {
22615 case VFMADD231PSYm:
22616 case VFMADD231PSYr:
22617 case VFMADD231PSZ128m:
22618 case VFMADD231PSZ128mb:
22619 case VFMADD231PSZ128mbk:
22620 case VFMADD231PSZ128mbkz:
22621 case VFMADD231PSZ128mk:
22622 case VFMADD231PSZ128mkz:
22623 case VFMADD231PSZ128r:
22624 case VFMADD231PSZ128rk:
22625 case VFMADD231PSZ128rkz:
22626 case VFMADD231PSZ256m:
22627 case VFMADD231PSZ256mb:
22628 case VFMADD231PSZ256mbk:
22629 case VFMADD231PSZ256mbkz:
22630 case VFMADD231PSZ256mk:
22631 case VFMADD231PSZ256mkz:
22632 case VFMADD231PSZ256r:
22633 case VFMADD231PSZ256rk:
22634 case VFMADD231PSZ256rkz:
22635 case VFMADD231PSZm:
22636 case VFMADD231PSZmb:
22637 case VFMADD231PSZmbk:
22638 case VFMADD231PSZmbkz:
22639 case VFMADD231PSZmk:
22640 case VFMADD231PSZmkz:
22641 case VFMADD231PSZr:
22642 case VFMADD231PSZrb:
22643 case VFMADD231PSZrbk:
22644 case VFMADD231PSZrbkz:
22645 case VFMADD231PSZrk:
22646 case VFMADD231PSZrkz:
22647 case VFMADD231PSm:
22648 case VFMADD231PSr:
22649 return true;
22650 }
22651 return false;
22652}
22653
22654bool isVCVTTSS2SI(unsigned Opcode) {
22655 switch (Opcode) {
22656 case VCVTTSS2SI64Zrm_Int:
22657 case VCVTTSS2SI64Zrr_Int:
22658 case VCVTTSS2SI64Zrrb_Int:
22659 case VCVTTSS2SI64rm_Int:
22660 case VCVTTSS2SI64rr_Int:
22661 case VCVTTSS2SIZrm_Int:
22662 case VCVTTSS2SIZrr_Int:
22663 case VCVTTSS2SIZrrb_Int:
22664 case VCVTTSS2SIrm_Int:
22665 case VCVTTSS2SIrr_Int:
22666 return true;
22667 }
22668 return false;
22669}
22670
22671bool isTCMMRLFP16PS(unsigned Opcode) {
22672 return Opcode == TCMMRLFP16PS;
22673}
22674
22675bool isFCOMPP(unsigned Opcode) {
22676 return Opcode == FCOMPP;
22677}
22678
22679bool isMOVD(unsigned Opcode) {
22680 switch (Opcode) {
22681 case MMX_MOVD64grr:
22682 case MMX_MOVD64mr:
22683 case MMX_MOVD64rm:
22684 case MMX_MOVD64rr:
22685 case MOVDI2PDIrm:
22686 case MOVDI2PDIrr:
22687 case MOVPDI2DImr:
22688 case MOVPDI2DIrr:
22689 return true;
22690 }
22691 return false;
22692}
22693
22694bool isMOVBE(unsigned Opcode) {
22695 switch (Opcode) {
22696 case MOVBE16mr:
22697 case MOVBE16mr_EVEX:
22698 case MOVBE16rm:
22699 case MOVBE16rm_EVEX:
22700 case MOVBE16rr:
22701 case MOVBE16rr_REV:
22702 case MOVBE32mr:
22703 case MOVBE32mr_EVEX:
22704 case MOVBE32rm:
22705 case MOVBE32rm_EVEX:
22706 case MOVBE32rr:
22707 case MOVBE32rr_REV:
22708 case MOVBE64mr:
22709 case MOVBE64mr_EVEX:
22710 case MOVBE64rm:
22711 case MOVBE64rm_EVEX:
22712 case MOVBE64rr:
22713 case MOVBE64rr_REV:
22714 return true;
22715 }
22716 return false;
22717}
22718
22719bool isVP2INTERSECTD(unsigned Opcode) {
22720 switch (Opcode) {
22721 case VP2INTERSECTDZ128rm:
22722 case VP2INTERSECTDZ128rmb:
22723 case VP2INTERSECTDZ128rr:
22724 case VP2INTERSECTDZ256rm:
22725 case VP2INTERSECTDZ256rmb:
22726 case VP2INTERSECTDZ256rr:
22727 case VP2INTERSECTDZrm:
22728 case VP2INTERSECTDZrmb:
22729 case VP2INTERSECTDZrr:
22730 return true;
22731 }
22732 return false;
22733}
22734
22735bool isVPMULLQ(unsigned Opcode) {
22736 switch (Opcode) {
22737 case VPMULLQZ128rm:
22738 case VPMULLQZ128rmb:
22739 case VPMULLQZ128rmbk:
22740 case VPMULLQZ128rmbkz:
22741 case VPMULLQZ128rmk:
22742 case VPMULLQZ128rmkz:
22743 case VPMULLQZ128rr:
22744 case VPMULLQZ128rrk:
22745 case VPMULLQZ128rrkz:
22746 case VPMULLQZ256rm:
22747 case VPMULLQZ256rmb:
22748 case VPMULLQZ256rmbk:
22749 case VPMULLQZ256rmbkz:
22750 case VPMULLQZ256rmk:
22751 case VPMULLQZ256rmkz:
22752 case VPMULLQZ256rr:
22753 case VPMULLQZ256rrk:
22754 case VPMULLQZ256rrkz:
22755 case VPMULLQZrm:
22756 case VPMULLQZrmb:
22757 case VPMULLQZrmbk:
22758 case VPMULLQZrmbkz:
22759 case VPMULLQZrmk:
22760 case VPMULLQZrmkz:
22761 case VPMULLQZrr:
22762 case VPMULLQZrrk:
22763 case VPMULLQZrrkz:
22764 return true;
22765 }
22766 return false;
22767}
22768
22769bool isVSCALEFPS(unsigned Opcode) {
22770 switch (Opcode) {
22771 case VSCALEFPSZ128rm:
22772 case VSCALEFPSZ128rmb:
22773 case VSCALEFPSZ128rmbk:
22774 case VSCALEFPSZ128rmbkz:
22775 case VSCALEFPSZ128rmk:
22776 case VSCALEFPSZ128rmkz:
22777 case VSCALEFPSZ128rr:
22778 case VSCALEFPSZ128rrk:
22779 case VSCALEFPSZ128rrkz:
22780 case VSCALEFPSZ256rm:
22781 case VSCALEFPSZ256rmb:
22782 case VSCALEFPSZ256rmbk:
22783 case VSCALEFPSZ256rmbkz:
22784 case VSCALEFPSZ256rmk:
22785 case VSCALEFPSZ256rmkz:
22786 case VSCALEFPSZ256rr:
22787 case VSCALEFPSZ256rrk:
22788 case VSCALEFPSZ256rrkz:
22789 case VSCALEFPSZrm:
22790 case VSCALEFPSZrmb:
22791 case VSCALEFPSZrmbk:
22792 case VSCALEFPSZrmbkz:
22793 case VSCALEFPSZrmk:
22794 case VSCALEFPSZrmkz:
22795 case VSCALEFPSZrr:
22796 case VSCALEFPSZrrb:
22797 case VSCALEFPSZrrbk:
22798 case VSCALEFPSZrrbkz:
22799 case VSCALEFPSZrrk:
22800 case VSCALEFPSZrrkz:
22801 return true;
22802 }
22803 return false;
22804}
22805
22806bool isVPMACSDQH(unsigned Opcode) {
22807 switch (Opcode) {
22808 case VPMACSDQHrm:
22809 case VPMACSDQHrr:
22810 return true;
22811 }
22812 return false;
22813}
22814
22815bool isVPTESTNMD(unsigned Opcode) {
22816 switch (Opcode) {
22817 case VPTESTNMDZ128rm:
22818 case VPTESTNMDZ128rmb:
22819 case VPTESTNMDZ128rmbk:
22820 case VPTESTNMDZ128rmk:
22821 case VPTESTNMDZ128rr:
22822 case VPTESTNMDZ128rrk:
22823 case VPTESTNMDZ256rm:
22824 case VPTESTNMDZ256rmb:
22825 case VPTESTNMDZ256rmbk:
22826 case VPTESTNMDZ256rmk:
22827 case VPTESTNMDZ256rr:
22828 case VPTESTNMDZ256rrk:
22829 case VPTESTNMDZrm:
22830 case VPTESTNMDZrmb:
22831 case VPTESTNMDZrmbk:
22832 case VPTESTNMDZrmk:
22833 case VPTESTNMDZrr:
22834 case VPTESTNMDZrrk:
22835 return true;
22836 }
22837 return false;
22838}
22839
22840bool isFCOMP(unsigned Opcode) {
22841 switch (Opcode) {
22842 case COMP_FST0r:
22843 case FCOMP32m:
22844 case FCOMP64m:
22845 return true;
22846 }
22847 return false;
22848}
22849
22850bool isPREFETCHWT1(unsigned Opcode) {
22851 return Opcode == PREFETCHWT1;
22852}
22853
22854bool isVCMPSD(unsigned Opcode) {
22855 switch (Opcode) {
22856 case VCMPSDZrmi_Int:
22857 case VCMPSDZrmik_Int:
22858 case VCMPSDZrri_Int:
22859 case VCMPSDZrrib_Int:
22860 case VCMPSDZrribk_Int:
22861 case VCMPSDZrrik_Int:
22862 case VCMPSDrmi_Int:
22863 case VCMPSDrri_Int:
22864 return true;
22865 }
22866 return false;
22867}
22868
22869bool isSGDTD(unsigned Opcode) {
22870 return Opcode == SGDT32m;
22871}
22872
22873bool isWRUSSD(unsigned Opcode) {
22874 switch (Opcode) {
22875 case WRUSSD:
22876 case WRUSSD_EVEX:
22877 return true;
22878 }
22879 return false;
22880}
22881
22882bool isFSUBP(unsigned Opcode) {
22883 return Opcode == SUB_FPrST0;
22884}
22885
22886bool isVUNPCKLPS(unsigned Opcode) {
22887 switch (Opcode) {
22888 case VUNPCKLPSYrm:
22889 case VUNPCKLPSYrr:
22890 case VUNPCKLPSZ128rm:
22891 case VUNPCKLPSZ128rmb:
22892 case VUNPCKLPSZ128rmbk:
22893 case VUNPCKLPSZ128rmbkz:
22894 case VUNPCKLPSZ128rmk:
22895 case VUNPCKLPSZ128rmkz:
22896 case VUNPCKLPSZ128rr:
22897 case VUNPCKLPSZ128rrk:
22898 case VUNPCKLPSZ128rrkz:
22899 case VUNPCKLPSZ256rm:
22900 case VUNPCKLPSZ256rmb:
22901 case VUNPCKLPSZ256rmbk:
22902 case VUNPCKLPSZ256rmbkz:
22903 case VUNPCKLPSZ256rmk:
22904 case VUNPCKLPSZ256rmkz:
22905 case VUNPCKLPSZ256rr:
22906 case VUNPCKLPSZ256rrk:
22907 case VUNPCKLPSZ256rrkz:
22908 case VUNPCKLPSZrm:
22909 case VUNPCKLPSZrmb:
22910 case VUNPCKLPSZrmbk:
22911 case VUNPCKLPSZrmbkz:
22912 case VUNPCKLPSZrmk:
22913 case VUNPCKLPSZrmkz:
22914 case VUNPCKLPSZrr:
22915 case VUNPCKLPSZrrk:
22916 case VUNPCKLPSZrrkz:
22917 case VUNPCKLPSrm:
22918 case VUNPCKLPSrr:
22919 return true;
22920 }
22921 return false;
22922}
22923
22924bool isVFNMSUB213SS(unsigned Opcode) {
22925 switch (Opcode) {
22926 case VFNMSUB213SSZm_Int:
22927 case VFNMSUB213SSZmk_Int:
22928 case VFNMSUB213SSZmkz_Int:
22929 case VFNMSUB213SSZr_Int:
22930 case VFNMSUB213SSZrb_Int:
22931 case VFNMSUB213SSZrbk_Int:
22932 case VFNMSUB213SSZrbkz_Int:
22933 case VFNMSUB213SSZrk_Int:
22934 case VFNMSUB213SSZrkz_Int:
22935 case VFNMSUB213SSm_Int:
22936 case VFNMSUB213SSr_Int:
22937 return true;
22938 }
22939 return false;
22940}
22941
22942bool isROUNDPD(unsigned Opcode) {
22943 switch (Opcode) {
22944 case ROUNDPDmi:
22945 case ROUNDPDri:
22946 return true;
22947 }
22948 return false;
22949}
22950
22951bool isVPMAXSW(unsigned Opcode) {
22952 switch (Opcode) {
22953 case VPMAXSWYrm:
22954 case VPMAXSWYrr:
22955 case VPMAXSWZ128rm:
22956 case VPMAXSWZ128rmk:
22957 case VPMAXSWZ128rmkz:
22958 case VPMAXSWZ128rr:
22959 case VPMAXSWZ128rrk:
22960 case VPMAXSWZ128rrkz:
22961 case VPMAXSWZ256rm:
22962 case VPMAXSWZ256rmk:
22963 case VPMAXSWZ256rmkz:
22964 case VPMAXSWZ256rr:
22965 case VPMAXSWZ256rrk:
22966 case VPMAXSWZ256rrkz:
22967 case VPMAXSWZrm:
22968 case VPMAXSWZrmk:
22969 case VPMAXSWZrmkz:
22970 case VPMAXSWZrr:
22971 case VPMAXSWZrrk:
22972 case VPMAXSWZrrkz:
22973 case VPMAXSWrm:
22974 case VPMAXSWrr:
22975 return true;
22976 }
22977 return false;
22978}
22979
22980bool isVCVTTPH2DQ(unsigned Opcode) {
22981 switch (Opcode) {
22982 case VCVTTPH2DQZ128rm:
22983 case VCVTTPH2DQZ128rmb:
22984 case VCVTTPH2DQZ128rmbk:
22985 case VCVTTPH2DQZ128rmbkz:
22986 case VCVTTPH2DQZ128rmk:
22987 case VCVTTPH2DQZ128rmkz:
22988 case VCVTTPH2DQZ128rr:
22989 case VCVTTPH2DQZ128rrk:
22990 case VCVTTPH2DQZ128rrkz:
22991 case VCVTTPH2DQZ256rm:
22992 case VCVTTPH2DQZ256rmb:
22993 case VCVTTPH2DQZ256rmbk:
22994 case VCVTTPH2DQZ256rmbkz:
22995 case VCVTTPH2DQZ256rmk:
22996 case VCVTTPH2DQZ256rmkz:
22997 case VCVTTPH2DQZ256rr:
22998 case VCVTTPH2DQZ256rrk:
22999 case VCVTTPH2DQZ256rrkz:
23000 case VCVTTPH2DQZrm:
23001 case VCVTTPH2DQZrmb:
23002 case VCVTTPH2DQZrmbk:
23003 case VCVTTPH2DQZrmbkz:
23004 case VCVTTPH2DQZrmk:
23005 case VCVTTPH2DQZrmkz:
23006 case VCVTTPH2DQZrr:
23007 case VCVTTPH2DQZrrb:
23008 case VCVTTPH2DQZrrbk:
23009 case VCVTTPH2DQZrrbkz:
23010 case VCVTTPH2DQZrrk:
23011 case VCVTTPH2DQZrrkz:
23012 return true;
23013 }
23014 return false;
23015}
23016
23017bool isVPUNPCKLWD(unsigned Opcode) {
23018 switch (Opcode) {
23019 case VPUNPCKLWDYrm:
23020 case VPUNPCKLWDYrr:
23021 case VPUNPCKLWDZ128rm:
23022 case VPUNPCKLWDZ128rmk:
23023 case VPUNPCKLWDZ128rmkz:
23024 case VPUNPCKLWDZ128rr:
23025 case VPUNPCKLWDZ128rrk:
23026 case VPUNPCKLWDZ128rrkz:
23027 case VPUNPCKLWDZ256rm:
23028 case VPUNPCKLWDZ256rmk:
23029 case VPUNPCKLWDZ256rmkz:
23030 case VPUNPCKLWDZ256rr:
23031 case VPUNPCKLWDZ256rrk:
23032 case VPUNPCKLWDZ256rrkz:
23033 case VPUNPCKLWDZrm:
23034 case VPUNPCKLWDZrmk:
23035 case VPUNPCKLWDZrmkz:
23036 case VPUNPCKLWDZrr:
23037 case VPUNPCKLWDZrrk:
23038 case VPUNPCKLWDZrrkz:
23039 case VPUNPCKLWDrm:
23040 case VPUNPCKLWDrr:
23041 return true;
23042 }
23043 return false;
23044}
23045
23046bool isKSHIFTLD(unsigned Opcode) {
23047 return Opcode == KSHIFTLDki;
23048}
23049
23050bool isTCVTROWPS2BF16H(unsigned Opcode) {
23051 switch (Opcode) {
23052 case TCVTROWPS2BF16Hrte:
23053 case TCVTROWPS2BF16Hrti:
23054 return true;
23055 }
23056 return false;
23057}
23058
23059bool isVFMADD231SD(unsigned Opcode) {
23060 switch (Opcode) {
23061 case VFMADD231SDZm_Int:
23062 case VFMADD231SDZmk_Int:
23063 case VFMADD231SDZmkz_Int:
23064 case VFMADD231SDZr_Int:
23065 case VFMADD231SDZrb_Int:
23066 case VFMADD231SDZrbk_Int:
23067 case VFMADD231SDZrbkz_Int:
23068 case VFMADD231SDZrk_Int:
23069 case VFMADD231SDZrkz_Int:
23070 case VFMADD231SDm_Int:
23071 case VFMADD231SDr_Int:
23072 return true;
23073 }
23074 return false;
23075}
23076
23077bool isADDPS(unsigned Opcode) {
23078 switch (Opcode) {
23079 case ADDPSrm:
23080 case ADDPSrr:
23081 return true;
23082 }
23083 return false;
23084}
23085
23086bool isVPSLLVD(unsigned Opcode) {
23087 switch (Opcode) {
23088 case VPSLLVDYrm:
23089 case VPSLLVDYrr:
23090 case VPSLLVDZ128rm:
23091 case VPSLLVDZ128rmb:
23092 case VPSLLVDZ128rmbk:
23093 case VPSLLVDZ128rmbkz:
23094 case VPSLLVDZ128rmk:
23095 case VPSLLVDZ128rmkz:
23096 case VPSLLVDZ128rr:
23097 case VPSLLVDZ128rrk:
23098 case VPSLLVDZ128rrkz:
23099 case VPSLLVDZ256rm:
23100 case VPSLLVDZ256rmb:
23101 case VPSLLVDZ256rmbk:
23102 case VPSLLVDZ256rmbkz:
23103 case VPSLLVDZ256rmk:
23104 case VPSLLVDZ256rmkz:
23105 case VPSLLVDZ256rr:
23106 case VPSLLVDZ256rrk:
23107 case VPSLLVDZ256rrkz:
23108 case VPSLLVDZrm:
23109 case VPSLLVDZrmb:
23110 case VPSLLVDZrmbk:
23111 case VPSLLVDZrmbkz:
23112 case VPSLLVDZrmk:
23113 case VPSLLVDZrmkz:
23114 case VPSLLVDZrr:
23115 case VPSLLVDZrrk:
23116 case VPSLLVDZrrkz:
23117 case VPSLLVDrm:
23118 case VPSLLVDrr:
23119 return true;
23120 }
23121 return false;
23122}
23123
23124bool isVFNMADD132SH(unsigned Opcode) {
23125 switch (Opcode) {
23126 case VFNMADD132SHZm_Int:
23127 case VFNMADD132SHZmk_Int:
23128 case VFNMADD132SHZmkz_Int:
23129 case VFNMADD132SHZr_Int:
23130 case VFNMADD132SHZrb_Int:
23131 case VFNMADD132SHZrbk_Int:
23132 case VFNMADD132SHZrbkz_Int:
23133 case VFNMADD132SHZrk_Int:
23134 case VFNMADD132SHZrkz_Int:
23135 return true;
23136 }
23137 return false;
23138}
23139
23140bool isVMOVNTPS(unsigned Opcode) {
23141 switch (Opcode) {
23142 case VMOVNTPSYmr:
23143 case VMOVNTPSZ128mr:
23144 case VMOVNTPSZ256mr:
23145 case VMOVNTPSZmr:
23146 case VMOVNTPSmr:
23147 return true;
23148 }
23149 return false;
23150}
23151
23152bool isVCVTPD2DQ(unsigned Opcode) {
23153 switch (Opcode) {
23154 case VCVTPD2DQYrm:
23155 case VCVTPD2DQYrr:
23156 case VCVTPD2DQZ128rm:
23157 case VCVTPD2DQZ128rmb:
23158 case VCVTPD2DQZ128rmbk:
23159 case VCVTPD2DQZ128rmbkz:
23160 case VCVTPD2DQZ128rmk:
23161 case VCVTPD2DQZ128rmkz:
23162 case VCVTPD2DQZ128rr:
23163 case VCVTPD2DQZ128rrk:
23164 case VCVTPD2DQZ128rrkz:
23165 case VCVTPD2DQZ256rm:
23166 case VCVTPD2DQZ256rmb:
23167 case VCVTPD2DQZ256rmbk:
23168 case VCVTPD2DQZ256rmbkz:
23169 case VCVTPD2DQZ256rmk:
23170 case VCVTPD2DQZ256rmkz:
23171 case VCVTPD2DQZ256rr:
23172 case VCVTPD2DQZ256rrk:
23173 case VCVTPD2DQZ256rrkz:
23174 case VCVTPD2DQZrm:
23175 case VCVTPD2DQZrmb:
23176 case VCVTPD2DQZrmbk:
23177 case VCVTPD2DQZrmbkz:
23178 case VCVTPD2DQZrmk:
23179 case VCVTPD2DQZrmkz:
23180 case VCVTPD2DQZrr:
23181 case VCVTPD2DQZrrb:
23182 case VCVTPD2DQZrrbk:
23183 case VCVTPD2DQZrrbkz:
23184 case VCVTPD2DQZrrk:
23185 case VCVTPD2DQZrrkz:
23186 case VCVTPD2DQrm:
23187 case VCVTPD2DQrr:
23188 return true;
23189 }
23190 return false;
23191}
23192
23193bool isVPXOR(unsigned Opcode) {
23194 switch (Opcode) {
23195 case VPXORYrm:
23196 case VPXORYrr:
23197 case VPXORrm:
23198 case VPXORrr:
23199 return true;
23200 }
23201 return false;
23202}
23203
23204bool isSTMXCSR(unsigned Opcode) {
23205 return Opcode == STMXCSR;
23206}
23207
23208bool isVRCP14SS(unsigned Opcode) {
23209 switch (Opcode) {
23210 case VRCP14SSZrm:
23211 case VRCP14SSZrmk:
23212 case VRCP14SSZrmkz:
23213 case VRCP14SSZrr:
23214 case VRCP14SSZrrk:
23215 case VRCP14SSZrrkz:
23216 return true;
23217 }
23218 return false;
23219}
23220
23221bool isUD2(unsigned Opcode) {
23222 return Opcode == TRAP;
23223}
23224
23225bool isVPOPCNTW(unsigned Opcode) {
23226 switch (Opcode) {
23227 case VPOPCNTWZ128rm:
23228 case VPOPCNTWZ128rmk:
23229 case VPOPCNTWZ128rmkz:
23230 case VPOPCNTWZ128rr:
23231 case VPOPCNTWZ128rrk:
23232 case VPOPCNTWZ128rrkz:
23233 case VPOPCNTWZ256rm:
23234 case VPOPCNTWZ256rmk:
23235 case VPOPCNTWZ256rmkz:
23236 case VPOPCNTWZ256rr:
23237 case VPOPCNTWZ256rrk:
23238 case VPOPCNTWZ256rrkz:
23239 case VPOPCNTWZrm:
23240 case VPOPCNTWZrmk:
23241 case VPOPCNTWZrmkz:
23242 case VPOPCNTWZrr:
23243 case VPOPCNTWZrrk:
23244 case VPOPCNTWZrrkz:
23245 return true;
23246 }
23247 return false;
23248}
23249
23250bool isVRSQRTSH(unsigned Opcode) {
23251 switch (Opcode) {
23252 case VRSQRTSHZrm:
23253 case VRSQRTSHZrmk:
23254 case VRSQRTSHZrmkz:
23255 case VRSQRTSHZrr:
23256 case VRSQRTSHZrrk:
23257 case VRSQRTSHZrrkz:
23258 return true;
23259 }
23260 return false;
23261}
23262
23263bool isVSCATTERPF0DPD(unsigned Opcode) {
23264 return Opcode == VSCATTERPF0DPDm;
23265}
23266
23267bool isVFMADDPS(unsigned Opcode) {
23268 switch (Opcode) {
23269 case VFMADDPS4Ymr:
23270 case VFMADDPS4Yrm:
23271 case VFMADDPS4Yrr:
23272 case VFMADDPS4Yrr_REV:
23273 case VFMADDPS4mr:
23274 case VFMADDPS4rm:
23275 case VFMADDPS4rr:
23276 case VFMADDPS4rr_REV:
23277 return true;
23278 }
23279 return false;
23280}
23281
23282bool isXSAVEC64(unsigned Opcode) {
23283 return Opcode == XSAVEC64;
23284}
23285
23286bool isVPMADDUBSW(unsigned Opcode) {
23287 switch (Opcode) {
23288 case VPMADDUBSWYrm:
23289 case VPMADDUBSWYrr:
23290 case VPMADDUBSWZ128rm:
23291 case VPMADDUBSWZ128rmk:
23292 case VPMADDUBSWZ128rmkz:
23293 case VPMADDUBSWZ128rr:
23294 case VPMADDUBSWZ128rrk:
23295 case VPMADDUBSWZ128rrkz:
23296 case VPMADDUBSWZ256rm:
23297 case VPMADDUBSWZ256rmk:
23298 case VPMADDUBSWZ256rmkz:
23299 case VPMADDUBSWZ256rr:
23300 case VPMADDUBSWZ256rrk:
23301 case VPMADDUBSWZ256rrkz:
23302 case VPMADDUBSWZrm:
23303 case VPMADDUBSWZrmk:
23304 case VPMADDUBSWZrmkz:
23305 case VPMADDUBSWZrr:
23306 case VPMADDUBSWZrrk:
23307 case VPMADDUBSWZrrkz:
23308 case VPMADDUBSWrm:
23309 case VPMADDUBSWrr:
23310 return true;
23311 }
23312 return false;
23313}
23314
23315bool isVPMOVZXDQ(unsigned Opcode) {
23316 switch (Opcode) {
23317 case VPMOVZXDQYrm:
23318 case VPMOVZXDQYrr:
23319 case VPMOVZXDQZ128rm:
23320 case VPMOVZXDQZ128rmk:
23321 case VPMOVZXDQZ128rmkz:
23322 case VPMOVZXDQZ128rr:
23323 case VPMOVZXDQZ128rrk:
23324 case VPMOVZXDQZ128rrkz:
23325 case VPMOVZXDQZ256rm:
23326 case VPMOVZXDQZ256rmk:
23327 case VPMOVZXDQZ256rmkz:
23328 case VPMOVZXDQZ256rr:
23329 case VPMOVZXDQZ256rrk:
23330 case VPMOVZXDQZ256rrkz:
23331 case VPMOVZXDQZrm:
23332 case VPMOVZXDQZrmk:
23333 case VPMOVZXDQZrmkz:
23334 case VPMOVZXDQZrr:
23335 case VPMOVZXDQZrrk:
23336 case VPMOVZXDQZrrkz:
23337 case VPMOVZXDQrm:
23338 case VPMOVZXDQrr:
23339 return true;
23340 }
23341 return false;
23342}
23343
23344bool isVRCP14PS(unsigned Opcode) {
23345 switch (Opcode) {
23346 case VRCP14PSZ128m:
23347 case VRCP14PSZ128mb:
23348 case VRCP14PSZ128mbk:
23349 case VRCP14PSZ128mbkz:
23350 case VRCP14PSZ128mk:
23351 case VRCP14PSZ128mkz:
23352 case VRCP14PSZ128r:
23353 case VRCP14PSZ128rk:
23354 case VRCP14PSZ128rkz:
23355 case VRCP14PSZ256m:
23356 case VRCP14PSZ256mb:
23357 case VRCP14PSZ256mbk:
23358 case VRCP14PSZ256mbkz:
23359 case VRCP14PSZ256mk:
23360 case VRCP14PSZ256mkz:
23361 case VRCP14PSZ256r:
23362 case VRCP14PSZ256rk:
23363 case VRCP14PSZ256rkz:
23364 case VRCP14PSZm:
23365 case VRCP14PSZmb:
23366 case VRCP14PSZmbk:
23367 case VRCP14PSZmbkz:
23368 case VRCP14PSZmk:
23369 case VRCP14PSZmkz:
23370 case VRCP14PSZr:
23371 case VRCP14PSZrk:
23372 case VRCP14PSZrkz:
23373 return true;
23374 }
23375 return false;
23376}
23377
23378bool isVSQRTSH(unsigned Opcode) {
23379 switch (Opcode) {
23380 case VSQRTSHZm_Int:
23381 case VSQRTSHZmk_Int:
23382 case VSQRTSHZmkz_Int:
23383 case VSQRTSHZr_Int:
23384 case VSQRTSHZrb_Int:
23385 case VSQRTSHZrbk_Int:
23386 case VSQRTSHZrbkz_Int:
23387 case VSQRTSHZrk_Int:
23388 case VSQRTSHZrkz_Int:
23389 return true;
23390 }
23391 return false;
23392}
23393
23394bool isTCVTROWD2PS(unsigned Opcode) {
23395 switch (Opcode) {
23396 case TCVTROWD2PSrte:
23397 case TCVTROWD2PSrti:
23398 return true;
23399 }
23400 return false;
23401}
23402
23403bool isLOOP(unsigned Opcode) {
23404 return Opcode == LOOP;
23405}
23406
23407bool isSTUI(unsigned Opcode) {
23408 return Opcode == STUI;
23409}
23410
23411bool isVCVTTPS2UDQ(unsigned Opcode) {
23412 switch (Opcode) {
23413 case VCVTTPS2UDQZ128rm:
23414 case VCVTTPS2UDQZ128rmb:
23415 case VCVTTPS2UDQZ128rmbk:
23416 case VCVTTPS2UDQZ128rmbkz:
23417 case VCVTTPS2UDQZ128rmk:
23418 case VCVTTPS2UDQZ128rmkz:
23419 case VCVTTPS2UDQZ128rr:
23420 case VCVTTPS2UDQZ128rrk:
23421 case VCVTTPS2UDQZ128rrkz:
23422 case VCVTTPS2UDQZ256rm:
23423 case VCVTTPS2UDQZ256rmb:
23424 case VCVTTPS2UDQZ256rmbk:
23425 case VCVTTPS2UDQZ256rmbkz:
23426 case VCVTTPS2UDQZ256rmk:
23427 case VCVTTPS2UDQZ256rmkz:
23428 case VCVTTPS2UDQZ256rr:
23429 case VCVTTPS2UDQZ256rrk:
23430 case VCVTTPS2UDQZ256rrkz:
23431 case VCVTTPS2UDQZrm:
23432 case VCVTTPS2UDQZrmb:
23433 case VCVTTPS2UDQZrmbk:
23434 case VCVTTPS2UDQZrmbkz:
23435 case VCVTTPS2UDQZrmk:
23436 case VCVTTPS2UDQZrmkz:
23437 case VCVTTPS2UDQZrr:
23438 case VCVTTPS2UDQZrrb:
23439 case VCVTTPS2UDQZrrbk:
23440 case VCVTTPS2UDQZrrbkz:
23441 case VCVTTPS2UDQZrrk:
23442 case VCVTTPS2UDQZrrkz:
23443 return true;
23444 }
23445 return false;
23446}
23447
23448bool isVCOMPRESSPS(unsigned Opcode) {
23449 switch (Opcode) {
23450 case VCOMPRESSPSZ128mr:
23451 case VCOMPRESSPSZ128mrk:
23452 case VCOMPRESSPSZ128rr:
23453 case VCOMPRESSPSZ128rrk:
23454 case VCOMPRESSPSZ128rrkz:
23455 case VCOMPRESSPSZ256mr:
23456 case VCOMPRESSPSZ256mrk:
23457 case VCOMPRESSPSZ256rr:
23458 case VCOMPRESSPSZ256rrk:
23459 case VCOMPRESSPSZ256rrkz:
23460 case VCOMPRESSPSZmr:
23461 case VCOMPRESSPSZmrk:
23462 case VCOMPRESSPSZrr:
23463 case VCOMPRESSPSZrrk:
23464 case VCOMPRESSPSZrrkz:
23465 return true;
23466 }
23467 return false;
23468}
23469
23470bool isXABORT(unsigned Opcode) {
23471 return Opcode == XABORT;
23472}
23473
23474bool isVCVTTBF162IUBS(unsigned Opcode) {
23475 switch (Opcode) {
23476 case VCVTTBF162IUBSZ128rm:
23477 case VCVTTBF162IUBSZ128rmb:
23478 case VCVTTBF162IUBSZ128rmbk:
23479 case VCVTTBF162IUBSZ128rmbkz:
23480 case VCVTTBF162IUBSZ128rmk:
23481 case VCVTTBF162IUBSZ128rmkz:
23482 case VCVTTBF162IUBSZ128rr:
23483 case VCVTTBF162IUBSZ128rrk:
23484 case VCVTTBF162IUBSZ128rrkz:
23485 case VCVTTBF162IUBSZ256rm:
23486 case VCVTTBF162IUBSZ256rmb:
23487 case VCVTTBF162IUBSZ256rmbk:
23488 case VCVTTBF162IUBSZ256rmbkz:
23489 case VCVTTBF162IUBSZ256rmk:
23490 case VCVTTBF162IUBSZ256rmkz:
23491 case VCVTTBF162IUBSZ256rr:
23492 case VCVTTBF162IUBSZ256rrk:
23493 case VCVTTBF162IUBSZ256rrkz:
23494 case VCVTTBF162IUBSZrm:
23495 case VCVTTBF162IUBSZrmb:
23496 case VCVTTBF162IUBSZrmbk:
23497 case VCVTTBF162IUBSZrmbkz:
23498 case VCVTTBF162IUBSZrmk:
23499 case VCVTTBF162IUBSZrmkz:
23500 case VCVTTBF162IUBSZrr:
23501 case VCVTTBF162IUBSZrrk:
23502 case VCVTTBF162IUBSZrrkz:
23503 return true;
23504 }
23505 return false;
23506}
23507
23508bool isVPADDW(unsigned Opcode) {
23509 switch (Opcode) {
23510 case VPADDWYrm:
23511 case VPADDWYrr:
23512 case VPADDWZ128rm:
23513 case VPADDWZ128rmk:
23514 case VPADDWZ128rmkz:
23515 case VPADDWZ128rr:
23516 case VPADDWZ128rrk:
23517 case VPADDWZ128rrkz:
23518 case VPADDWZ256rm:
23519 case VPADDWZ256rmk:
23520 case VPADDWZ256rmkz:
23521 case VPADDWZ256rr:
23522 case VPADDWZ256rrk:
23523 case VPADDWZ256rrkz:
23524 case VPADDWZrm:
23525 case VPADDWZrmk:
23526 case VPADDWZrmkz:
23527 case VPADDWZrr:
23528 case VPADDWZrrk:
23529 case VPADDWZrrkz:
23530 case VPADDWrm:
23531 case VPADDWrr:
23532 return true;
23533 }
23534 return false;
23535}
23536
23537bool isVRNDSCALEPS(unsigned Opcode) {
23538 switch (Opcode) {
23539 case VRNDSCALEPSZ128rmbi:
23540 case VRNDSCALEPSZ128rmbik:
23541 case VRNDSCALEPSZ128rmbikz:
23542 case VRNDSCALEPSZ128rmi:
23543 case VRNDSCALEPSZ128rmik:
23544 case VRNDSCALEPSZ128rmikz:
23545 case VRNDSCALEPSZ128rri:
23546 case VRNDSCALEPSZ128rrik:
23547 case VRNDSCALEPSZ128rrikz:
23548 case VRNDSCALEPSZ256rmbi:
23549 case VRNDSCALEPSZ256rmbik:
23550 case VRNDSCALEPSZ256rmbikz:
23551 case VRNDSCALEPSZ256rmi:
23552 case VRNDSCALEPSZ256rmik:
23553 case VRNDSCALEPSZ256rmikz:
23554 case VRNDSCALEPSZ256rri:
23555 case VRNDSCALEPSZ256rrik:
23556 case VRNDSCALEPSZ256rrikz:
23557 case VRNDSCALEPSZrmbi:
23558 case VRNDSCALEPSZrmbik:
23559 case VRNDSCALEPSZrmbikz:
23560 case VRNDSCALEPSZrmi:
23561 case VRNDSCALEPSZrmik:
23562 case VRNDSCALEPSZrmikz:
23563 case VRNDSCALEPSZrri:
23564 case VRNDSCALEPSZrrib:
23565 case VRNDSCALEPSZrribk:
23566 case VRNDSCALEPSZrribkz:
23567 case VRNDSCALEPSZrrik:
23568 case VRNDSCALEPSZrrikz:
23569 return true;
23570 }
23571 return false;
23572}
23573
23574bool isVPSIGND(unsigned Opcode) {
23575 switch (Opcode) {
23576 case VPSIGNDYrm:
23577 case VPSIGNDYrr:
23578 case VPSIGNDrm:
23579 case VPSIGNDrr:
23580 return true;
23581 }
23582 return false;
23583}
23584
23585bool isVPHADDUWD(unsigned Opcode) {
23586 switch (Opcode) {
23587 case VPHADDUWDrm:
23588 case VPHADDUWDrr:
23589 return true;
23590 }
23591 return false;
23592}
23593
23594bool isVCVT2PH2HF8S(unsigned Opcode) {
23595 switch (Opcode) {
23596 case VCVT2PH2HF8SZ128rm:
23597 case VCVT2PH2HF8SZ128rmb:
23598 case VCVT2PH2HF8SZ128rmbk:
23599 case VCVT2PH2HF8SZ128rmbkz:
23600 case VCVT2PH2HF8SZ128rmk:
23601 case VCVT2PH2HF8SZ128rmkz:
23602 case VCVT2PH2HF8SZ128rr:
23603 case VCVT2PH2HF8SZ128rrk:
23604 case VCVT2PH2HF8SZ128rrkz:
23605 case VCVT2PH2HF8SZ256rm:
23606 case VCVT2PH2HF8SZ256rmb:
23607 case VCVT2PH2HF8SZ256rmbk:
23608 case VCVT2PH2HF8SZ256rmbkz:
23609 case VCVT2PH2HF8SZ256rmk:
23610 case VCVT2PH2HF8SZ256rmkz:
23611 case VCVT2PH2HF8SZ256rr:
23612 case VCVT2PH2HF8SZ256rrk:
23613 case VCVT2PH2HF8SZ256rrkz:
23614 case VCVT2PH2HF8SZrm:
23615 case VCVT2PH2HF8SZrmb:
23616 case VCVT2PH2HF8SZrmbk:
23617 case VCVT2PH2HF8SZrmbkz:
23618 case VCVT2PH2HF8SZrmk:
23619 case VCVT2PH2HF8SZrmkz:
23620 case VCVT2PH2HF8SZrr:
23621 case VCVT2PH2HF8SZrrk:
23622 case VCVT2PH2HF8SZrrkz:
23623 return true;
23624 }
23625 return false;
23626}
23627
23628bool isVDBPSADBW(unsigned Opcode) {
23629 switch (Opcode) {
23630 case VDBPSADBWZ128rmi:
23631 case VDBPSADBWZ128rmik:
23632 case VDBPSADBWZ128rmikz:
23633 case VDBPSADBWZ128rri:
23634 case VDBPSADBWZ128rrik:
23635 case VDBPSADBWZ128rrikz:
23636 case VDBPSADBWZ256rmi:
23637 case VDBPSADBWZ256rmik:
23638 case VDBPSADBWZ256rmikz:
23639 case VDBPSADBWZ256rri:
23640 case VDBPSADBWZ256rrik:
23641 case VDBPSADBWZ256rrikz:
23642 case VDBPSADBWZrmi:
23643 case VDBPSADBWZrmik:
23644 case VDBPSADBWZrmikz:
23645 case VDBPSADBWZrri:
23646 case VDBPSADBWZrrik:
23647 case VDBPSADBWZrrikz:
23648 return true;
23649 }
23650 return false;
23651}
23652
23653bool isPSLLW(unsigned Opcode) {
23654 switch (Opcode) {
23655 case MMX_PSLLWri:
23656 case MMX_PSLLWrm:
23657 case MMX_PSLLWrr:
23658 case PSLLWri:
23659 case PSLLWrm:
23660 case PSLLWrr:
23661 return true;
23662 }
23663 return false;
23664}
23665
23666bool isVPMOVQD(unsigned Opcode) {
23667 switch (Opcode) {
23668 case VPMOVQDZ128mr:
23669 case VPMOVQDZ128mrk:
23670 case VPMOVQDZ128rr:
23671 case VPMOVQDZ128rrk:
23672 case VPMOVQDZ128rrkz:
23673 case VPMOVQDZ256mr:
23674 case VPMOVQDZ256mrk:
23675 case VPMOVQDZ256rr:
23676 case VPMOVQDZ256rrk:
23677 case VPMOVQDZ256rrkz:
23678 case VPMOVQDZmr:
23679 case VPMOVQDZmrk:
23680 case VPMOVQDZrr:
23681 case VPMOVQDZrrk:
23682 case VPMOVQDZrrkz:
23683 return true;
23684 }
23685 return false;
23686}
23687
23688bool isVINSERTI64X4(unsigned Opcode) {
23689 switch (Opcode) {
23690 case VINSERTI64X4Zrmi:
23691 case VINSERTI64X4Zrmik:
23692 case VINSERTI64X4Zrmikz:
23693 case VINSERTI64X4Zrri:
23694 case VINSERTI64X4Zrrik:
23695 case VINSERTI64X4Zrrikz:
23696 return true;
23697 }
23698 return false;
23699}
23700
23701bool isVPERMI2PS(unsigned Opcode) {
23702 switch (Opcode) {
23703 case VPERMI2PSZ128rm:
23704 case VPERMI2PSZ128rmb:
23705 case VPERMI2PSZ128rmbk:
23706 case VPERMI2PSZ128rmbkz:
23707 case VPERMI2PSZ128rmk:
23708 case VPERMI2PSZ128rmkz:
23709 case VPERMI2PSZ128rr:
23710 case VPERMI2PSZ128rrk:
23711 case VPERMI2PSZ128rrkz:
23712 case VPERMI2PSZ256rm:
23713 case VPERMI2PSZ256rmb:
23714 case VPERMI2PSZ256rmbk:
23715 case VPERMI2PSZ256rmbkz:
23716 case VPERMI2PSZ256rmk:
23717 case VPERMI2PSZ256rmkz:
23718 case VPERMI2PSZ256rr:
23719 case VPERMI2PSZ256rrk:
23720 case VPERMI2PSZ256rrkz:
23721 case VPERMI2PSZrm:
23722 case VPERMI2PSZrmb:
23723 case VPERMI2PSZrmbk:
23724 case VPERMI2PSZrmbkz:
23725 case VPERMI2PSZrmk:
23726 case VPERMI2PSZrmkz:
23727 case VPERMI2PSZrr:
23728 case VPERMI2PSZrrk:
23729 case VPERMI2PSZrrkz:
23730 return true;
23731 }
23732 return false;
23733}
23734
23735bool isVMULPH(unsigned Opcode) {
23736 switch (Opcode) {
23737 case VMULPHZ128rm:
23738 case VMULPHZ128rmb:
23739 case VMULPHZ128rmbk:
23740 case VMULPHZ128rmbkz:
23741 case VMULPHZ128rmk:
23742 case VMULPHZ128rmkz:
23743 case VMULPHZ128rr:
23744 case VMULPHZ128rrk:
23745 case VMULPHZ128rrkz:
23746 case VMULPHZ256rm:
23747 case VMULPHZ256rmb:
23748 case VMULPHZ256rmbk:
23749 case VMULPHZ256rmbkz:
23750 case VMULPHZ256rmk:
23751 case VMULPHZ256rmkz:
23752 case VMULPHZ256rr:
23753 case VMULPHZ256rrk:
23754 case VMULPHZ256rrkz:
23755 case VMULPHZrm:
23756 case VMULPHZrmb:
23757 case VMULPHZrmbk:
23758 case VMULPHZrmbkz:
23759 case VMULPHZrmk:
23760 case VMULPHZrmkz:
23761 case VMULPHZrr:
23762 case VMULPHZrrb:
23763 case VMULPHZrrbk:
23764 case VMULPHZrrbkz:
23765 case VMULPHZrrk:
23766 case VMULPHZrrkz:
23767 return true;
23768 }
23769 return false;
23770}
23771
23772bool isVPCMPUQ(unsigned Opcode) {
23773 switch (Opcode) {
23774 case VPCMPUQZ128rmbi:
23775 case VPCMPUQZ128rmbik:
23776 case VPCMPUQZ128rmi:
23777 case VPCMPUQZ128rmik:
23778 case VPCMPUQZ128rri:
23779 case VPCMPUQZ128rrik:
23780 case VPCMPUQZ256rmbi:
23781 case VPCMPUQZ256rmbik:
23782 case VPCMPUQZ256rmi:
23783 case VPCMPUQZ256rmik:
23784 case VPCMPUQZ256rri:
23785 case VPCMPUQZ256rrik:
23786 case VPCMPUQZrmbi:
23787 case VPCMPUQZrmbik:
23788 case VPCMPUQZrmi:
23789 case VPCMPUQZrmik:
23790 case VPCMPUQZrri:
23791 case VPCMPUQZrrik:
23792 return true;
23793 }
23794 return false;
23795}
23796
23797bool isVCVTUSI2SD(unsigned Opcode) {
23798 switch (Opcode) {
23799 case VCVTUSI2SDZrm_Int:
23800 case VCVTUSI2SDZrr_Int:
23801 case VCVTUSI642SDZrm_Int:
23802 case VCVTUSI642SDZrr_Int:
23803 case VCVTUSI642SDZrrb_Int:
23804 return true;
23805 }
23806 return false;
23807}
23808
23809bool isKXNORW(unsigned Opcode) {
23810 return Opcode == KXNORWkk;
23811}
23812
23813bool isBLCIC(unsigned Opcode) {
23814 switch (Opcode) {
23815 case BLCIC32rm:
23816 case BLCIC32rr:
23817 case BLCIC64rm:
23818 case BLCIC64rr:
23819 return true;
23820 }
23821 return false;
23822}
23823
23824bool isVFNMADD213SD(unsigned Opcode) {
23825 switch (Opcode) {
23826 case VFNMADD213SDZm_Int:
23827 case VFNMADD213SDZmk_Int:
23828 case VFNMADD213SDZmkz_Int:
23829 case VFNMADD213SDZr_Int:
23830 case VFNMADD213SDZrb_Int:
23831 case VFNMADD213SDZrbk_Int:
23832 case VFNMADD213SDZrbkz_Int:
23833 case VFNMADD213SDZrk_Int:
23834 case VFNMADD213SDZrkz_Int:
23835 case VFNMADD213SDm_Int:
23836 case VFNMADD213SDr_Int:
23837 return true;
23838 }
23839 return false;
23840}
23841
23842bool isVPMACSWW(unsigned Opcode) {
23843 switch (Opcode) {
23844 case VPMACSWWrm:
23845 case VPMACSWWrr:
23846 return true;
23847 }
23848 return false;
23849}
23850
23851bool isVMOVLPS(unsigned Opcode) {
23852 switch (Opcode) {
23853 case VMOVLPSZ128mr:
23854 case VMOVLPSZ128rm:
23855 case VMOVLPSmr:
23856 case VMOVLPSrm:
23857 return true;
23858 }
23859 return false;
23860}
23861
23862bool isPCONFIG(unsigned Opcode) {
23863 return Opcode == PCONFIG;
23864}
23865
23866bool isPANDN(unsigned Opcode) {
23867 switch (Opcode) {
23868 case MMX_PANDNrm:
23869 case MMX_PANDNrr:
23870 case PANDNrm:
23871 case PANDNrr:
23872 return true;
23873 }
23874 return false;
23875}
23876
23877bool isVGETEXPPD(unsigned Opcode) {
23878 switch (Opcode) {
23879 case VGETEXPPDZ128m:
23880 case VGETEXPPDZ128mb:
23881 case VGETEXPPDZ128mbk:
23882 case VGETEXPPDZ128mbkz:
23883 case VGETEXPPDZ128mk:
23884 case VGETEXPPDZ128mkz:
23885 case VGETEXPPDZ128r:
23886 case VGETEXPPDZ128rk:
23887 case VGETEXPPDZ128rkz:
23888 case VGETEXPPDZ256m:
23889 case VGETEXPPDZ256mb:
23890 case VGETEXPPDZ256mbk:
23891 case VGETEXPPDZ256mbkz:
23892 case VGETEXPPDZ256mk:
23893 case VGETEXPPDZ256mkz:
23894 case VGETEXPPDZ256r:
23895 case VGETEXPPDZ256rk:
23896 case VGETEXPPDZ256rkz:
23897 case VGETEXPPDZm:
23898 case VGETEXPPDZmb:
23899 case VGETEXPPDZmbk:
23900 case VGETEXPPDZmbkz:
23901 case VGETEXPPDZmk:
23902 case VGETEXPPDZmkz:
23903 case VGETEXPPDZr:
23904 case VGETEXPPDZrb:
23905 case VGETEXPPDZrbk:
23906 case VGETEXPPDZrbkz:
23907 case VGETEXPPDZrk:
23908 case VGETEXPPDZrkz:
23909 return true;
23910 }
23911 return false;
23912}
23913
23914bool isVPSRLVQ(unsigned Opcode) {
23915 switch (Opcode) {
23916 case VPSRLVQYrm:
23917 case VPSRLVQYrr:
23918 case VPSRLVQZ128rm:
23919 case VPSRLVQZ128rmb:
23920 case VPSRLVQZ128rmbk:
23921 case VPSRLVQZ128rmbkz:
23922 case VPSRLVQZ128rmk:
23923 case VPSRLVQZ128rmkz:
23924 case VPSRLVQZ128rr:
23925 case VPSRLVQZ128rrk:
23926 case VPSRLVQZ128rrkz:
23927 case VPSRLVQZ256rm:
23928 case VPSRLVQZ256rmb:
23929 case VPSRLVQZ256rmbk:
23930 case VPSRLVQZ256rmbkz:
23931 case VPSRLVQZ256rmk:
23932 case VPSRLVQZ256rmkz:
23933 case VPSRLVQZ256rr:
23934 case VPSRLVQZ256rrk:
23935 case VPSRLVQZ256rrkz:
23936 case VPSRLVQZrm:
23937 case VPSRLVQZrmb:
23938 case VPSRLVQZrmbk:
23939 case VPSRLVQZrmbkz:
23940 case VPSRLVQZrmk:
23941 case VPSRLVQZrmkz:
23942 case VPSRLVQZrr:
23943 case VPSRLVQZrrk:
23944 case VPSRLVQZrrkz:
23945 case VPSRLVQrm:
23946 case VPSRLVQrr:
23947 return true;
23948 }
23949 return false;
23950}
23951
23952bool isUD1(unsigned Opcode) {
23953 switch (Opcode) {
23954 case UD1Lm:
23955 case UD1Lr:
23956 case UD1Qm:
23957 case UD1Qr:
23958 case UD1Wm:
23959 case UD1Wr:
23960 return true;
23961 }
23962 return false;
23963}
23964
23965bool isPMAXSB(unsigned Opcode) {
23966 switch (Opcode) {
23967 case PMAXSBrm:
23968 case PMAXSBrr:
23969 return true;
23970 }
23971 return false;
23972}
23973
23974bool isVPROLQ(unsigned Opcode) {
23975 switch (Opcode) {
23976 case VPROLQZ128mbi:
23977 case VPROLQZ128mbik:
23978 case VPROLQZ128mbikz:
23979 case VPROLQZ128mi:
23980 case VPROLQZ128mik:
23981 case VPROLQZ128mikz:
23982 case VPROLQZ128ri:
23983 case VPROLQZ128rik:
23984 case VPROLQZ128rikz:
23985 case VPROLQZ256mbi:
23986 case VPROLQZ256mbik:
23987 case VPROLQZ256mbikz:
23988 case VPROLQZ256mi:
23989 case VPROLQZ256mik:
23990 case VPROLQZ256mikz:
23991 case VPROLQZ256ri:
23992 case VPROLQZ256rik:
23993 case VPROLQZ256rikz:
23994 case VPROLQZmbi:
23995 case VPROLQZmbik:
23996 case VPROLQZmbikz:
23997 case VPROLQZmi:
23998 case VPROLQZmik:
23999 case VPROLQZmikz:
24000 case VPROLQZri:
24001 case VPROLQZrik:
24002 case VPROLQZrikz:
24003 return true;
24004 }
24005 return false;
24006}
24007
24008bool isVSCATTERPF1QPD(unsigned Opcode) {
24009 return Opcode == VSCATTERPF1QPDm;
24010}
24011
24012bool isVPSRLD(unsigned Opcode) {
24013 switch (Opcode) {
24014 case VPSRLDYri:
24015 case VPSRLDYrm:
24016 case VPSRLDYrr:
24017 case VPSRLDZ128mbi:
24018 case VPSRLDZ128mbik:
24019 case VPSRLDZ128mbikz:
24020 case VPSRLDZ128mi:
24021 case VPSRLDZ128mik:
24022 case VPSRLDZ128mikz:
24023 case VPSRLDZ128ri:
24024 case VPSRLDZ128rik:
24025 case VPSRLDZ128rikz:
24026 case VPSRLDZ128rm:
24027 case VPSRLDZ128rmk:
24028 case VPSRLDZ128rmkz:
24029 case VPSRLDZ128rr:
24030 case VPSRLDZ128rrk:
24031 case VPSRLDZ128rrkz:
24032 case VPSRLDZ256mbi:
24033 case VPSRLDZ256mbik:
24034 case VPSRLDZ256mbikz:
24035 case VPSRLDZ256mi:
24036 case VPSRLDZ256mik:
24037 case VPSRLDZ256mikz:
24038 case VPSRLDZ256ri:
24039 case VPSRLDZ256rik:
24040 case VPSRLDZ256rikz:
24041 case VPSRLDZ256rm:
24042 case VPSRLDZ256rmk:
24043 case VPSRLDZ256rmkz:
24044 case VPSRLDZ256rr:
24045 case VPSRLDZ256rrk:
24046 case VPSRLDZ256rrkz:
24047 case VPSRLDZmbi:
24048 case VPSRLDZmbik:
24049 case VPSRLDZmbikz:
24050 case VPSRLDZmi:
24051 case VPSRLDZmik:
24052 case VPSRLDZmikz:
24053 case VPSRLDZri:
24054 case VPSRLDZrik:
24055 case VPSRLDZrikz:
24056 case VPSRLDZrm:
24057 case VPSRLDZrmk:
24058 case VPSRLDZrmkz:
24059 case VPSRLDZrr:
24060 case VPSRLDZrrk:
24061 case VPSRLDZrrkz:
24062 case VPSRLDri:
24063 case VPSRLDrm:
24064 case VPSRLDrr:
24065 return true;
24066 }
24067 return false;
24068}
24069
24070bool isINT3(unsigned Opcode) {
24071 return Opcode == INT3;
24072}
24073
24074bool isXRSTORS64(unsigned Opcode) {
24075 return Opcode == XRSTORS64;
24076}
24077
24078bool isCVTSD2SI(unsigned Opcode) {
24079 switch (Opcode) {
24080 case CVTSD2SI64rm_Int:
24081 case CVTSD2SI64rr_Int:
24082 case CVTSD2SIrm_Int:
24083 case CVTSD2SIrr_Int:
24084 return true;
24085 }
24086 return false;
24087}
24088
24089bool isVMAXSS(unsigned Opcode) {
24090 switch (Opcode) {
24091 case VMAXSSZrm_Int:
24092 case VMAXSSZrmk_Int:
24093 case VMAXSSZrmkz_Int:
24094 case VMAXSSZrr_Int:
24095 case VMAXSSZrrb_Int:
24096 case VMAXSSZrrbk_Int:
24097 case VMAXSSZrrbkz_Int:
24098 case VMAXSSZrrk_Int:
24099 case VMAXSSZrrkz_Int:
24100 case VMAXSSrm_Int:
24101 case VMAXSSrr_Int:
24102 return true;
24103 }
24104 return false;
24105}
24106
24107bool isVPMINUB(unsigned Opcode) {
24108 switch (Opcode) {
24109 case VPMINUBYrm:
24110 case VPMINUBYrr:
24111 case VPMINUBZ128rm:
24112 case VPMINUBZ128rmk:
24113 case VPMINUBZ128rmkz:
24114 case VPMINUBZ128rr:
24115 case VPMINUBZ128rrk:
24116 case VPMINUBZ128rrkz:
24117 case VPMINUBZ256rm:
24118 case VPMINUBZ256rmk:
24119 case VPMINUBZ256rmkz:
24120 case VPMINUBZ256rr:
24121 case VPMINUBZ256rrk:
24122 case VPMINUBZ256rrkz:
24123 case VPMINUBZrm:
24124 case VPMINUBZrmk:
24125 case VPMINUBZrmkz:
24126 case VPMINUBZrr:
24127 case VPMINUBZrrk:
24128 case VPMINUBZrrkz:
24129 case VPMINUBrm:
24130 case VPMINUBrr:
24131 return true;
24132 }
24133 return false;
24134}
24135
24136bool isKXNORQ(unsigned Opcode) {
24137 return Opcode == KXNORQkk;
24138}
24139
24140bool isFLD(unsigned Opcode) {
24141 switch (Opcode) {
24142 case LD_F32m:
24143 case LD_F64m:
24144 case LD_F80m:
24145 case LD_Frr:
24146 return true;
24147 }
24148 return false;
24149}
24150
24151bool isVSHUFI32X4(unsigned Opcode) {
24152 switch (Opcode) {
24153 case VSHUFI32X4Z256rmbi:
24154 case VSHUFI32X4Z256rmbik:
24155 case VSHUFI32X4Z256rmbikz:
24156 case VSHUFI32X4Z256rmi:
24157 case VSHUFI32X4Z256rmik:
24158 case VSHUFI32X4Z256rmikz:
24159 case VSHUFI32X4Z256rri:
24160 case VSHUFI32X4Z256rrik:
24161 case VSHUFI32X4Z256rrikz:
24162 case VSHUFI32X4Zrmbi:
24163 case VSHUFI32X4Zrmbik:
24164 case VSHUFI32X4Zrmbikz:
24165 case VSHUFI32X4Zrmi:
24166 case VSHUFI32X4Zrmik:
24167 case VSHUFI32X4Zrmikz:
24168 case VSHUFI32X4Zrri:
24169 case VSHUFI32X4Zrrik:
24170 case VSHUFI32X4Zrrikz:
24171 return true;
24172 }
24173 return false;
24174}
24175
24176bool isSAHF(unsigned Opcode) {
24177 return Opcode == SAHF;
24178}
24179
24180bool isPFRSQRT(unsigned Opcode) {
24181 switch (Opcode) {
24182 case PFRSQRTrm:
24183 case PFRSQRTrr:
24184 return true;
24185 }
24186 return false;
24187}
24188
24189bool isSHRD(unsigned Opcode) {
24190 switch (Opcode) {
24191 case SHRD16mrCL:
24192 case SHRD16mrCL_EVEX:
24193 case SHRD16mrCL_ND:
24194 case SHRD16mrCL_NF:
24195 case SHRD16mrCL_NF_ND:
24196 case SHRD16mri8:
24197 case SHRD16mri8_EVEX:
24198 case SHRD16mri8_ND:
24199 case SHRD16mri8_NF:
24200 case SHRD16mri8_NF_ND:
24201 case SHRD16rrCL:
24202 case SHRD16rrCL_EVEX:
24203 case SHRD16rrCL_ND:
24204 case SHRD16rrCL_NF:
24205 case SHRD16rrCL_NF_ND:
24206 case SHRD16rri8:
24207 case SHRD16rri8_EVEX:
24208 case SHRD16rri8_ND:
24209 case SHRD16rri8_NF:
24210 case SHRD16rri8_NF_ND:
24211 case SHRD32mrCL:
24212 case SHRD32mrCL_EVEX:
24213 case SHRD32mrCL_ND:
24214 case SHRD32mrCL_NF:
24215 case SHRD32mrCL_NF_ND:
24216 case SHRD32mri8:
24217 case SHRD32mri8_EVEX:
24218 case SHRD32mri8_ND:
24219 case SHRD32mri8_NF:
24220 case SHRD32mri8_NF_ND:
24221 case SHRD32rrCL:
24222 case SHRD32rrCL_EVEX:
24223 case SHRD32rrCL_ND:
24224 case SHRD32rrCL_NF:
24225 case SHRD32rrCL_NF_ND:
24226 case SHRD32rri8:
24227 case SHRD32rri8_EVEX:
24228 case SHRD32rri8_ND:
24229 case SHRD32rri8_NF:
24230 case SHRD32rri8_NF_ND:
24231 case SHRD64mrCL:
24232 case SHRD64mrCL_EVEX:
24233 case SHRD64mrCL_ND:
24234 case SHRD64mrCL_NF:
24235 case SHRD64mrCL_NF_ND:
24236 case SHRD64mri8:
24237 case SHRD64mri8_EVEX:
24238 case SHRD64mri8_ND:
24239 case SHRD64mri8_NF:
24240 case SHRD64mri8_NF_ND:
24241 case SHRD64rrCL:
24242 case SHRD64rrCL_EVEX:
24243 case SHRD64rrCL_ND:
24244 case SHRD64rrCL_NF:
24245 case SHRD64rrCL_NF_ND:
24246 case SHRD64rri8:
24247 case SHRD64rri8_EVEX:
24248 case SHRD64rri8_ND:
24249 case SHRD64rri8_NF:
24250 case SHRD64rri8_NF_ND:
24251 return true;
24252 }
24253 return false;
24254}
24255
24256bool isSYSEXIT(unsigned Opcode) {
24257 return Opcode == SYSEXIT;
24258}
24259
24260bool isXSAVE64(unsigned Opcode) {
24261 return Opcode == XSAVE64;
24262}
24263
24264bool isVPMAXSD(unsigned Opcode) {
24265 switch (Opcode) {
24266 case VPMAXSDYrm:
24267 case VPMAXSDYrr:
24268 case VPMAXSDZ128rm:
24269 case VPMAXSDZ128rmb:
24270 case VPMAXSDZ128rmbk:
24271 case VPMAXSDZ128rmbkz:
24272 case VPMAXSDZ128rmk:
24273 case VPMAXSDZ128rmkz:
24274 case VPMAXSDZ128rr:
24275 case VPMAXSDZ128rrk:
24276 case VPMAXSDZ128rrkz:
24277 case VPMAXSDZ256rm:
24278 case VPMAXSDZ256rmb:
24279 case VPMAXSDZ256rmbk:
24280 case VPMAXSDZ256rmbkz:
24281 case VPMAXSDZ256rmk:
24282 case VPMAXSDZ256rmkz:
24283 case VPMAXSDZ256rr:
24284 case VPMAXSDZ256rrk:
24285 case VPMAXSDZ256rrkz:
24286 case VPMAXSDZrm:
24287 case VPMAXSDZrmb:
24288 case VPMAXSDZrmbk:
24289 case VPMAXSDZrmbkz:
24290 case VPMAXSDZrmk:
24291 case VPMAXSDZrmkz:
24292 case VPMAXSDZrr:
24293 case VPMAXSDZrrk:
24294 case VPMAXSDZrrkz:
24295 case VPMAXSDrm:
24296 case VPMAXSDrr:
24297 return true;
24298 }
24299 return false;
24300}
24301
24302bool isCVTTSD2SI(unsigned Opcode) {
24303 switch (Opcode) {
24304 case CVTTSD2SI64rm_Int:
24305 case CVTTSD2SI64rr_Int:
24306 case CVTTSD2SIrm_Int:
24307 case CVTTSD2SIrr_Int:
24308 return true;
24309 }
24310 return false;
24311}
24312
24313bool isVCVTTSS2SIS(unsigned Opcode) {
24314 switch (Opcode) {
24315 case VCVTTSS2SI64Srm_Int:
24316 case VCVTTSS2SI64Srr_Int:
24317 case VCVTTSS2SI64Srrb_Int:
24318 case VCVTTSS2SISrm_Int:
24319 case VCVTTSS2SISrr_Int:
24320 case VCVTTSS2SISrrb_Int:
24321 return true;
24322 }
24323 return false;
24324}
24325
24326bool isPMOVMSKB(unsigned Opcode) {
24327 switch (Opcode) {
24328 case MMX_PMOVMSKBrr:
24329 case PMOVMSKBrr:
24330 return true;
24331 }
24332 return false;
24333}
24334
24335bool isVRANGEPS(unsigned Opcode) {
24336 switch (Opcode) {
24337 case VRANGEPSZ128rmbi:
24338 case VRANGEPSZ128rmbik:
24339 case VRANGEPSZ128rmbikz:
24340 case VRANGEPSZ128rmi:
24341 case VRANGEPSZ128rmik:
24342 case VRANGEPSZ128rmikz:
24343 case VRANGEPSZ128rri:
24344 case VRANGEPSZ128rrik:
24345 case VRANGEPSZ128rrikz:
24346 case VRANGEPSZ256rmbi:
24347 case VRANGEPSZ256rmbik:
24348 case VRANGEPSZ256rmbikz:
24349 case VRANGEPSZ256rmi:
24350 case VRANGEPSZ256rmik:
24351 case VRANGEPSZ256rmikz:
24352 case VRANGEPSZ256rri:
24353 case VRANGEPSZ256rrik:
24354 case VRANGEPSZ256rrikz:
24355 case VRANGEPSZrmbi:
24356 case VRANGEPSZrmbik:
24357 case VRANGEPSZrmbikz:
24358 case VRANGEPSZrmi:
24359 case VRANGEPSZrmik:
24360 case VRANGEPSZrmikz:
24361 case VRANGEPSZrri:
24362 case VRANGEPSZrrib:
24363 case VRANGEPSZrribk:
24364 case VRANGEPSZrribkz:
24365 case VRANGEPSZrrik:
24366 case VRANGEPSZrrikz:
24367 return true;
24368 }
24369 return false;
24370}
24371
24372bool isVADDSUBPS(unsigned Opcode) {
24373 switch (Opcode) {
24374 case VADDSUBPSYrm:
24375 case VADDSUBPSYrr:
24376 case VADDSUBPSrm:
24377 case VADDSUBPSrr:
24378 return true;
24379 }
24380 return false;
24381}
24382
24383bool isVBROADCASTI128(unsigned Opcode) {
24384 return Opcode == VBROADCASTI128rm;
24385}
24386
24387bool isPADDUSB(unsigned Opcode) {
24388 switch (Opcode) {
24389 case MMX_PADDUSBrm:
24390 case MMX_PADDUSBrr:
24391 case PADDUSBrm:
24392 case PADDUSBrr:
24393 return true;
24394 }
24395 return false;
24396}
24397
24398bool isENCODEKEY128(unsigned Opcode) {
24399 return Opcode == ENCODEKEY128;
24400}
24401
24402bool isOR(unsigned Opcode) {
24403 switch (Opcode) {
24404 case OR16i16:
24405 case OR16mi:
24406 case OR16mi8:
24407 case OR16mi8_EVEX:
24408 case OR16mi8_ND:
24409 case OR16mi8_NF:
24410 case OR16mi8_NF_ND:
24411 case OR16mi_EVEX:
24412 case OR16mi_ND:
24413 case OR16mi_NF:
24414 case OR16mi_NF_ND:
24415 case OR16mr:
24416 case OR16mr_EVEX:
24417 case OR16mr_ND:
24418 case OR16mr_NF:
24419 case OR16mr_NF_ND:
24420 case OR16ri:
24421 case OR16ri8:
24422 case OR16ri8_EVEX:
24423 case OR16ri8_ND:
24424 case OR16ri8_NF:
24425 case OR16ri8_NF_ND:
24426 case OR16ri_EVEX:
24427 case OR16ri_ND:
24428 case OR16ri_NF:
24429 case OR16ri_NF_ND:
24430 case OR16rm:
24431 case OR16rm_EVEX:
24432 case OR16rm_ND:
24433 case OR16rm_NF:
24434 case OR16rm_NF_ND:
24435 case OR16rr:
24436 case OR16rr_EVEX:
24437 case OR16rr_EVEX_REV:
24438 case OR16rr_ND:
24439 case OR16rr_ND_REV:
24440 case OR16rr_NF:
24441 case OR16rr_NF_ND:
24442 case OR16rr_NF_ND_REV:
24443 case OR16rr_NF_REV:
24444 case OR16rr_REV:
24445 case OR32i32:
24446 case OR32mi:
24447 case OR32mi8:
24448 case OR32mi8_EVEX:
24449 case OR32mi8_ND:
24450 case OR32mi8_NF:
24451 case OR32mi8_NF_ND:
24452 case OR32mi_EVEX:
24453 case OR32mi_ND:
24454 case OR32mi_NF:
24455 case OR32mi_NF_ND:
24456 case OR32mr:
24457 case OR32mr_EVEX:
24458 case OR32mr_ND:
24459 case OR32mr_NF:
24460 case OR32mr_NF_ND:
24461 case OR32ri:
24462 case OR32ri8:
24463 case OR32ri8_EVEX:
24464 case OR32ri8_ND:
24465 case OR32ri8_NF:
24466 case OR32ri8_NF_ND:
24467 case OR32ri_EVEX:
24468 case OR32ri_ND:
24469 case OR32ri_NF:
24470 case OR32ri_NF_ND:
24471 case OR32rm:
24472 case OR32rm_EVEX:
24473 case OR32rm_ND:
24474 case OR32rm_NF:
24475 case OR32rm_NF_ND:
24476 case OR32rr:
24477 case OR32rr_EVEX:
24478 case OR32rr_EVEX_REV:
24479 case OR32rr_ND:
24480 case OR32rr_ND_REV:
24481 case OR32rr_NF:
24482 case OR32rr_NF_ND:
24483 case OR32rr_NF_ND_REV:
24484 case OR32rr_NF_REV:
24485 case OR32rr_REV:
24486 case OR64i32:
24487 case OR64mi32:
24488 case OR64mi32_EVEX:
24489 case OR64mi32_ND:
24490 case OR64mi32_NF:
24491 case OR64mi32_NF_ND:
24492 case OR64mi8:
24493 case OR64mi8_EVEX:
24494 case OR64mi8_ND:
24495 case OR64mi8_NF:
24496 case OR64mi8_NF_ND:
24497 case OR64mr:
24498 case OR64mr_EVEX:
24499 case OR64mr_ND:
24500 case OR64mr_NF:
24501 case OR64mr_NF_ND:
24502 case OR64ri32:
24503 case OR64ri32_EVEX:
24504 case OR64ri32_ND:
24505 case OR64ri32_NF:
24506 case OR64ri32_NF_ND:
24507 case OR64ri8:
24508 case OR64ri8_EVEX:
24509 case OR64ri8_ND:
24510 case OR64ri8_NF:
24511 case OR64ri8_NF_ND:
24512 case OR64rm:
24513 case OR64rm_EVEX:
24514 case OR64rm_ND:
24515 case OR64rm_NF:
24516 case OR64rm_NF_ND:
24517 case OR64rr:
24518 case OR64rr_EVEX:
24519 case OR64rr_EVEX_REV:
24520 case OR64rr_ND:
24521 case OR64rr_ND_REV:
24522 case OR64rr_NF:
24523 case OR64rr_NF_ND:
24524 case OR64rr_NF_ND_REV:
24525 case OR64rr_NF_REV:
24526 case OR64rr_REV:
24527 case OR8i8:
24528 case OR8mi:
24529 case OR8mi8:
24530 case OR8mi_EVEX:
24531 case OR8mi_ND:
24532 case OR8mi_NF:
24533 case OR8mi_NF_ND:
24534 case OR8mr:
24535 case OR8mr_EVEX:
24536 case OR8mr_ND:
24537 case OR8mr_NF:
24538 case OR8mr_NF_ND:
24539 case OR8ri:
24540 case OR8ri8:
24541 case OR8ri_EVEX:
24542 case OR8ri_ND:
24543 case OR8ri_NF:
24544 case OR8ri_NF_ND:
24545 case OR8rm:
24546 case OR8rm_EVEX:
24547 case OR8rm_ND:
24548 case OR8rm_NF:
24549 case OR8rm_NF_ND:
24550 case OR8rr:
24551 case OR8rr_EVEX:
24552 case OR8rr_EVEX_REV:
24553 case OR8rr_ND:
24554 case OR8rr_ND_REV:
24555 case OR8rr_NF:
24556 case OR8rr_NF_ND:
24557 case OR8rr_NF_ND_REV:
24558 case OR8rr_NF_REV:
24559 case OR8rr_REV:
24560 return true;
24561 }
24562 return false;
24563}
24564
24565bool isSTOSW(unsigned Opcode) {
24566 return Opcode == STOSW;
24567}
24568
24569bool isVCVTTPD2UQQS(unsigned Opcode) {
24570 switch (Opcode) {
24571 case VCVTTPD2UQQSZ128rm:
24572 case VCVTTPD2UQQSZ128rmb:
24573 case VCVTTPD2UQQSZ128rmbk:
24574 case VCVTTPD2UQQSZ128rmbkz:
24575 case VCVTTPD2UQQSZ128rmk:
24576 case VCVTTPD2UQQSZ128rmkz:
24577 case VCVTTPD2UQQSZ128rr:
24578 case VCVTTPD2UQQSZ128rrk:
24579 case VCVTTPD2UQQSZ128rrkz:
24580 case VCVTTPD2UQQSZ256rm:
24581 case VCVTTPD2UQQSZ256rmb:
24582 case VCVTTPD2UQQSZ256rmbk:
24583 case VCVTTPD2UQQSZ256rmbkz:
24584 case VCVTTPD2UQQSZ256rmk:
24585 case VCVTTPD2UQQSZ256rmkz:
24586 case VCVTTPD2UQQSZ256rr:
24587 case VCVTTPD2UQQSZ256rrb:
24588 case VCVTTPD2UQQSZ256rrbk:
24589 case VCVTTPD2UQQSZ256rrbkz:
24590 case VCVTTPD2UQQSZ256rrk:
24591 case VCVTTPD2UQQSZ256rrkz:
24592 case VCVTTPD2UQQSZrm:
24593 case VCVTTPD2UQQSZrmb:
24594 case VCVTTPD2UQQSZrmbk:
24595 case VCVTTPD2UQQSZrmbkz:
24596 case VCVTTPD2UQQSZrmk:
24597 case VCVTTPD2UQQSZrmkz:
24598 case VCVTTPD2UQQSZrr:
24599 case VCVTTPD2UQQSZrrb:
24600 case VCVTTPD2UQQSZrrbk:
24601 case VCVTTPD2UQQSZrrbkz:
24602 case VCVTTPD2UQQSZrrk:
24603 case VCVTTPD2UQQSZrrkz:
24604 return true;
24605 }
24606 return false;
24607}
24608
24609bool isPAVGW(unsigned Opcode) {
24610 switch (Opcode) {
24611 case MMX_PAVGWrm:
24612 case MMX_PAVGWrr:
24613 case PAVGWrm:
24614 case PAVGWrr:
24615 return true;
24616 }
24617 return false;
24618}
24619
24620bool isVCVTPD2PH(unsigned Opcode) {
24621 switch (Opcode) {
24622 case VCVTPD2PHZ128rm:
24623 case VCVTPD2PHZ128rmb:
24624 case VCVTPD2PHZ128rmbk:
24625 case VCVTPD2PHZ128rmbkz:
24626 case VCVTPD2PHZ128rmk:
24627 case VCVTPD2PHZ128rmkz:
24628 case VCVTPD2PHZ128rr:
24629 case VCVTPD2PHZ128rrk:
24630 case VCVTPD2PHZ128rrkz:
24631 case VCVTPD2PHZ256rm:
24632 case VCVTPD2PHZ256rmb:
24633 case VCVTPD2PHZ256rmbk:
24634 case VCVTPD2PHZ256rmbkz:
24635 case VCVTPD2PHZ256rmk:
24636 case VCVTPD2PHZ256rmkz:
24637 case VCVTPD2PHZ256rr:
24638 case VCVTPD2PHZ256rrk:
24639 case VCVTPD2PHZ256rrkz:
24640 case VCVTPD2PHZrm:
24641 case VCVTPD2PHZrmb:
24642 case VCVTPD2PHZrmbk:
24643 case VCVTPD2PHZrmbkz:
24644 case VCVTPD2PHZrmk:
24645 case VCVTPD2PHZrmkz:
24646 case VCVTPD2PHZrr:
24647 case VCVTPD2PHZrrb:
24648 case VCVTPD2PHZrrbk:
24649 case VCVTPD2PHZrrbkz:
24650 case VCVTPD2PHZrrk:
24651 case VCVTPD2PHZrrkz:
24652 return true;
24653 }
24654 return false;
24655}
24656
24657bool isSHLX(unsigned Opcode) {
24658 switch (Opcode) {
24659 case SHLX32rm:
24660 case SHLX32rm_EVEX:
24661 case SHLX32rr:
24662 case SHLX32rr_EVEX:
24663 case SHLX64rm:
24664 case SHLX64rm_EVEX:
24665 case SHLX64rr:
24666 case SHLX64rr_EVEX:
24667 return true;
24668 }
24669 return false;
24670}
24671
24672bool isVCVTSH2SD(unsigned Opcode) {
24673 switch (Opcode) {
24674 case VCVTSH2SDZrm_Int:
24675 case VCVTSH2SDZrmk_Int:
24676 case VCVTSH2SDZrmkz_Int:
24677 case VCVTSH2SDZrr_Int:
24678 case VCVTSH2SDZrrb_Int:
24679 case VCVTSH2SDZrrbk_Int:
24680 case VCVTSH2SDZrrbkz_Int:
24681 case VCVTSH2SDZrrk_Int:
24682 case VCVTSH2SDZrrkz_Int:
24683 return true;
24684 }
24685 return false;
24686}
24687
24688bool isVFMADD231SS(unsigned Opcode) {
24689 switch (Opcode) {
24690 case VFMADD231SSZm_Int:
24691 case VFMADD231SSZmk_Int:
24692 case VFMADD231SSZmkz_Int:
24693 case VFMADD231SSZr_Int:
24694 case VFMADD231SSZrb_Int:
24695 case VFMADD231SSZrbk_Int:
24696 case VFMADD231SSZrbkz_Int:
24697 case VFMADD231SSZrk_Int:
24698 case VFMADD231SSZrkz_Int:
24699 case VFMADD231SSm_Int:
24700 case VFMADD231SSr_Int:
24701 return true;
24702 }
24703 return false;
24704}
24705
24706bool isMOVNTSD(unsigned Opcode) {
24707 return Opcode == MOVNTSD;
24708}
24709
24710bool isFLDPI(unsigned Opcode) {
24711 return Opcode == FLDPI;
24712}
24713
24714bool isVCVTUSI2SS(unsigned Opcode) {
24715 switch (Opcode) {
24716 case VCVTUSI2SSZrm_Int:
24717 case VCVTUSI2SSZrr_Int:
24718 case VCVTUSI2SSZrrb_Int:
24719 case VCVTUSI642SSZrm_Int:
24720 case VCVTUSI642SSZrr_Int:
24721 case VCVTUSI642SSZrrb_Int:
24722 return true;
24723 }
24724 return false;
24725}
24726
24727bool isPMOVSXBD(unsigned Opcode) {
24728 switch (Opcode) {
24729 case PMOVSXBDrm:
24730 case PMOVSXBDrr:
24731 return true;
24732 }
24733 return false;
24734}
24735
24736bool isVPRORVQ(unsigned Opcode) {
24737 switch (Opcode) {
24738 case VPRORVQZ128rm:
24739 case VPRORVQZ128rmb:
24740 case VPRORVQZ128rmbk:
24741 case VPRORVQZ128rmbkz:
24742 case VPRORVQZ128rmk:
24743 case VPRORVQZ128rmkz:
24744 case VPRORVQZ128rr:
24745 case VPRORVQZ128rrk:
24746 case VPRORVQZ128rrkz:
24747 case VPRORVQZ256rm:
24748 case VPRORVQZ256rmb:
24749 case VPRORVQZ256rmbk:
24750 case VPRORVQZ256rmbkz:
24751 case VPRORVQZ256rmk:
24752 case VPRORVQZ256rmkz:
24753 case VPRORVQZ256rr:
24754 case VPRORVQZ256rrk:
24755 case VPRORVQZ256rrkz:
24756 case VPRORVQZrm:
24757 case VPRORVQZrmb:
24758 case VPRORVQZrmbk:
24759 case VPRORVQZrmbkz:
24760 case VPRORVQZrmk:
24761 case VPRORVQZrmkz:
24762 case VPRORVQZrr:
24763 case VPRORVQZrrk:
24764 case VPRORVQZrrkz:
24765 return true;
24766 }
24767 return false;
24768}
24769
24770bool isVPERMT2D(unsigned Opcode) {
24771 switch (Opcode) {
24772 case VPERMT2DZ128rm:
24773 case VPERMT2DZ128rmb:
24774 case VPERMT2DZ128rmbk:
24775 case VPERMT2DZ128rmbkz:
24776 case VPERMT2DZ128rmk:
24777 case VPERMT2DZ128rmkz:
24778 case VPERMT2DZ128rr:
24779 case VPERMT2DZ128rrk:
24780 case VPERMT2DZ128rrkz:
24781 case VPERMT2DZ256rm:
24782 case VPERMT2DZ256rmb:
24783 case VPERMT2DZ256rmbk:
24784 case VPERMT2DZ256rmbkz:
24785 case VPERMT2DZ256rmk:
24786 case VPERMT2DZ256rmkz:
24787 case VPERMT2DZ256rr:
24788 case VPERMT2DZ256rrk:
24789 case VPERMT2DZ256rrkz:
24790 case VPERMT2DZrm:
24791 case VPERMT2DZrmb:
24792 case VPERMT2DZrmbk:
24793 case VPERMT2DZrmbkz:
24794 case VPERMT2DZrmk:
24795 case VPERMT2DZrmkz:
24796 case VPERMT2DZrr:
24797 case VPERMT2DZrrk:
24798 case VPERMT2DZrrkz:
24799 return true;
24800 }
24801 return false;
24802}
24803
24804bool isADDSS(unsigned Opcode) {
24805 switch (Opcode) {
24806 case ADDSSrm_Int:
24807 case ADDSSrr_Int:
24808 return true;
24809 }
24810 return false;
24811}
24812
24813bool isAADD(unsigned Opcode) {
24814 switch (Opcode) {
24815 case AADD32mr:
24816 case AADD32mr_EVEX:
24817 case AADD64mr:
24818 case AADD64mr_EVEX:
24819 return true;
24820 }
24821 return false;
24822}
24823
24824bool isVPSRLVW(unsigned Opcode) {
24825 switch (Opcode) {
24826 case VPSRLVWZ128rm:
24827 case VPSRLVWZ128rmk:
24828 case VPSRLVWZ128rmkz:
24829 case VPSRLVWZ128rr:
24830 case VPSRLVWZ128rrk:
24831 case VPSRLVWZ128rrkz:
24832 case VPSRLVWZ256rm:
24833 case VPSRLVWZ256rmk:
24834 case VPSRLVWZ256rmkz:
24835 case VPSRLVWZ256rr:
24836 case VPSRLVWZ256rrk:
24837 case VPSRLVWZ256rrkz:
24838 case VPSRLVWZrm:
24839 case VPSRLVWZrmk:
24840 case VPSRLVWZrmkz:
24841 case VPSRLVWZrr:
24842 case VPSRLVWZrrk:
24843 case VPSRLVWZrrkz:
24844 return true;
24845 }
24846 return false;
24847}
24848
24849bool isVRSQRTPH(unsigned Opcode) {
24850 switch (Opcode) {
24851 case VRSQRTPHZ128m:
24852 case VRSQRTPHZ128mb:
24853 case VRSQRTPHZ128mbk:
24854 case VRSQRTPHZ128mbkz:
24855 case VRSQRTPHZ128mk:
24856 case VRSQRTPHZ128mkz:
24857 case VRSQRTPHZ128r:
24858 case VRSQRTPHZ128rk:
24859 case VRSQRTPHZ128rkz:
24860 case VRSQRTPHZ256m:
24861 case VRSQRTPHZ256mb:
24862 case VRSQRTPHZ256mbk:
24863 case VRSQRTPHZ256mbkz:
24864 case VRSQRTPHZ256mk:
24865 case VRSQRTPHZ256mkz:
24866 case VRSQRTPHZ256r:
24867 case VRSQRTPHZ256rk:
24868 case VRSQRTPHZ256rkz:
24869 case VRSQRTPHZm:
24870 case VRSQRTPHZmb:
24871 case VRSQRTPHZmbk:
24872 case VRSQRTPHZmbkz:
24873 case VRSQRTPHZmk:
24874 case VRSQRTPHZmkz:
24875 case VRSQRTPHZr:
24876 case VRSQRTPHZrk:
24877 case VRSQRTPHZrkz:
24878 return true;
24879 }
24880 return false;
24881}
24882
24883bool isVLDDQU(unsigned Opcode) {
24884 switch (Opcode) {
24885 case VLDDQUYrm:
24886 case VLDDQUrm:
24887 return true;
24888 }
24889 return false;
24890}
24891
24892bool isKMOVD(unsigned Opcode) {
24893 switch (Opcode) {
24894 case KMOVDkk:
24895 case KMOVDkk_EVEX:
24896 case KMOVDkm:
24897 case KMOVDkm_EVEX:
24898 case KMOVDkr:
24899 case KMOVDkr_EVEX:
24900 case KMOVDmk:
24901 case KMOVDmk_EVEX:
24902 case KMOVDrk:
24903 case KMOVDrk_EVEX:
24904 return true;
24905 }
24906 return false;
24907}
24908
24909bool isENCLV(unsigned Opcode) {
24910 return Opcode == ENCLV;
24911}
24912
24913bool isENCLU(unsigned Opcode) {
24914 return Opcode == ENCLU;
24915}
24916
24917bool isPREFETCHT1(unsigned Opcode) {
24918 return Opcode == PREFETCHT1;
24919}
24920
24921bool isRSQRTPS(unsigned Opcode) {
24922 switch (Opcode) {
24923 case RSQRTPSm:
24924 case RSQRTPSr:
24925 return true;
24926 }
24927 return false;
24928}
24929
24930bool isVCVTTSH2USI(unsigned Opcode) {
24931 switch (Opcode) {
24932 case VCVTTSH2USI64Zrm_Int:
24933 case VCVTTSH2USI64Zrr_Int:
24934 case VCVTTSH2USI64Zrrb_Int:
24935 case VCVTTSH2USIZrm_Int:
24936 case VCVTTSH2USIZrr_Int:
24937 case VCVTTSH2USIZrrb_Int:
24938 return true;
24939 }
24940 return false;
24941}
24942
24943bool isPADDB(unsigned Opcode) {
24944 switch (Opcode) {
24945 case MMX_PADDBrm:
24946 case MMX_PADDBrr:
24947 case PADDBrm:
24948 case PADDBrr:
24949 return true;
24950 }
24951 return false;
24952}
24953
24954bool isVMASKMOVDQU(unsigned Opcode) {
24955 return Opcode == VMASKMOVDQU64;
24956}
24957
24958bool isPUNPCKLBW(unsigned Opcode) {
24959 switch (Opcode) {
24960 case MMX_PUNPCKLBWrm:
24961 case MMX_PUNPCKLBWrr:
24962 case PUNPCKLBWrm:
24963 case PUNPCKLBWrr:
24964 return true;
24965 }
24966 return false;
24967}
24968
24969bool isMOV(unsigned Opcode) {
24970 switch (Opcode) {
24971 case MOV16ao16:
24972 case MOV16ao32:
24973 case MOV16mi:
24974 case MOV16mr:
24975 case MOV16ms:
24976 case MOV16o16a:
24977 case MOV16o32a:
24978 case MOV16ri:
24979 case MOV16ri_alt:
24980 case MOV16rm:
24981 case MOV16rr:
24982 case MOV16rr_REV:
24983 case MOV16rs:
24984 case MOV16sm:
24985 case MOV16sr:
24986 case MOV32ao16:
24987 case MOV32ao32:
24988 case MOV32cr:
24989 case MOV32dr:
24990 case MOV32mi:
24991 case MOV32mr:
24992 case MOV32o16a:
24993 case MOV32o32a:
24994 case MOV32rc:
24995 case MOV32rd:
24996 case MOV32ri:
24997 case MOV32ri_alt:
24998 case MOV32rm:
24999 case MOV32rr:
25000 case MOV32rr_REV:
25001 case MOV32rs:
25002 case MOV32sr:
25003 case MOV64ao32:
25004 case MOV64cr:
25005 case MOV64dr:
25006 case MOV64mi32:
25007 case MOV64mr:
25008 case MOV64o32a:
25009 case MOV64rc:
25010 case MOV64rd:
25011 case MOV64ri32:
25012 case MOV64rm:
25013 case MOV64rr:
25014 case MOV64rr_REV:
25015 case MOV64rs:
25016 case MOV64sr:
25017 case MOV8ao16:
25018 case MOV8ao32:
25019 case MOV8mi:
25020 case MOV8mr:
25021 case MOV8o16a:
25022 case MOV8o32a:
25023 case MOV8ri:
25024 case MOV8ri_alt:
25025 case MOV8rm:
25026 case MOV8rr:
25027 case MOV8rr_REV:
25028 return true;
25029 }
25030 return false;
25031}
25032
25033bool isVCVTTPH2IUBS(unsigned Opcode) {
25034 switch (Opcode) {
25035 case VCVTTPH2IUBSZ128rm:
25036 case VCVTTPH2IUBSZ128rmb:
25037 case VCVTTPH2IUBSZ128rmbk:
25038 case VCVTTPH2IUBSZ128rmbkz:
25039 case VCVTTPH2IUBSZ128rmk:
25040 case VCVTTPH2IUBSZ128rmkz:
25041 case VCVTTPH2IUBSZ128rr:
25042 case VCVTTPH2IUBSZ128rrk:
25043 case VCVTTPH2IUBSZ128rrkz:
25044 case VCVTTPH2IUBSZ256rm:
25045 case VCVTTPH2IUBSZ256rmb:
25046 case VCVTTPH2IUBSZ256rmbk:
25047 case VCVTTPH2IUBSZ256rmbkz:
25048 case VCVTTPH2IUBSZ256rmk:
25049 case VCVTTPH2IUBSZ256rmkz:
25050 case VCVTTPH2IUBSZ256rr:
25051 case VCVTTPH2IUBSZ256rrk:
25052 case VCVTTPH2IUBSZ256rrkz:
25053 case VCVTTPH2IUBSZrm:
25054 case VCVTTPH2IUBSZrmb:
25055 case VCVTTPH2IUBSZrmbk:
25056 case VCVTTPH2IUBSZrmbkz:
25057 case VCVTTPH2IUBSZrmk:
25058 case VCVTTPH2IUBSZrmkz:
25059 case VCVTTPH2IUBSZrr:
25060 case VCVTTPH2IUBSZrrb:
25061 case VCVTTPH2IUBSZrrbk:
25062 case VCVTTPH2IUBSZrrbkz:
25063 case VCVTTPH2IUBSZrrk:
25064 case VCVTTPH2IUBSZrrkz:
25065 return true;
25066 }
25067 return false;
25068}
25069
25070bool isMUL(unsigned Opcode) {
25071 switch (Opcode) {
25072 case MUL16m:
25073 case MUL16m_EVEX:
25074 case MUL16m_NF:
25075 case MUL16r:
25076 case MUL16r_EVEX:
25077 case MUL16r_NF:
25078 case MUL32m:
25079 case MUL32m_EVEX:
25080 case MUL32m_NF:
25081 case MUL32r:
25082 case MUL32r_EVEX:
25083 case MUL32r_NF:
25084 case MUL64m:
25085 case MUL64m_EVEX:
25086 case MUL64m_NF:
25087 case MUL64r:
25088 case MUL64r_EVEX:
25089 case MUL64r_NF:
25090 case MUL8m:
25091 case MUL8m_EVEX:
25092 case MUL8m_NF:
25093 case MUL8r:
25094 case MUL8r_EVEX:
25095 case MUL8r_NF:
25096 return true;
25097 }
25098 return false;
25099}
25100
25101bool isRCL(unsigned Opcode) {
25102 switch (Opcode) {
25103 case RCL16m1:
25104 case RCL16m1_EVEX:
25105 case RCL16m1_ND:
25106 case RCL16mCL:
25107 case RCL16mCL_EVEX:
25108 case RCL16mCL_ND:
25109 case RCL16mi:
25110 case RCL16mi_EVEX:
25111 case RCL16mi_ND:
25112 case RCL16r1:
25113 case RCL16r1_EVEX:
25114 case RCL16r1_ND:
25115 case RCL16rCL:
25116 case RCL16rCL_EVEX:
25117 case RCL16rCL_ND:
25118 case RCL16ri:
25119 case RCL16ri_EVEX:
25120 case RCL16ri_ND:
25121 case RCL32m1:
25122 case RCL32m1_EVEX:
25123 case RCL32m1_ND:
25124 case RCL32mCL:
25125 case RCL32mCL_EVEX:
25126 case RCL32mCL_ND:
25127 case RCL32mi:
25128 case RCL32mi_EVEX:
25129 case RCL32mi_ND:
25130 case RCL32r1:
25131 case RCL32r1_EVEX:
25132 case RCL32r1_ND:
25133 case RCL32rCL:
25134 case RCL32rCL_EVEX:
25135 case RCL32rCL_ND:
25136 case RCL32ri:
25137 case RCL32ri_EVEX:
25138 case RCL32ri_ND:
25139 case RCL64m1:
25140 case RCL64m1_EVEX:
25141 case RCL64m1_ND:
25142 case RCL64mCL:
25143 case RCL64mCL_EVEX:
25144 case RCL64mCL_ND:
25145 case RCL64mi:
25146 case RCL64mi_EVEX:
25147 case RCL64mi_ND:
25148 case RCL64r1:
25149 case RCL64r1_EVEX:
25150 case RCL64r1_ND:
25151 case RCL64rCL:
25152 case RCL64rCL_EVEX:
25153 case RCL64rCL_ND:
25154 case RCL64ri:
25155 case RCL64ri_EVEX:
25156 case RCL64ri_ND:
25157 case RCL8m1:
25158 case RCL8m1_EVEX:
25159 case RCL8m1_ND:
25160 case RCL8mCL:
25161 case RCL8mCL_EVEX:
25162 case RCL8mCL_ND:
25163 case RCL8mi:
25164 case RCL8mi_EVEX:
25165 case RCL8mi_ND:
25166 case RCL8r1:
25167 case RCL8r1_EVEX:
25168 case RCL8r1_ND:
25169 case RCL8rCL:
25170 case RCL8rCL_EVEX:
25171 case RCL8rCL_ND:
25172 case RCL8ri:
25173 case RCL8ri_EVEX:
25174 case RCL8ri_ND:
25175 return true;
25176 }
25177 return false;
25178}
25179
25180bool isVRCPSH(unsigned Opcode) {
25181 switch (Opcode) {
25182 case VRCPSHZrm:
25183 case VRCPSHZrmk:
25184 case VRCPSHZrmkz:
25185 case VRCPSHZrr:
25186 case VRCPSHZrrk:
25187 case VRCPSHZrrkz:
25188 return true;
25189 }
25190 return false;
25191}
25192
25193bool isPFCMPEQ(unsigned Opcode) {
25194 switch (Opcode) {
25195 case PFCMPEQrm:
25196 case PFCMPEQrr:
25197 return true;
25198 }
25199 return false;
25200}
25201
25202bool isMONITOR(unsigned Opcode) {
25203 switch (Opcode) {
25204 case MONITOR32rrr:
25205 case MONITOR64rrr:
25206 return true;
25207 }
25208 return false;
25209}
25210
25211bool isFDIVR(unsigned Opcode) {
25212 switch (Opcode) {
25213 case DIVR_F32m:
25214 case DIVR_F64m:
25215 case DIVR_FST0r:
25216 case DIVR_FrST0:
25217 return true;
25218 }
25219 return false;
25220}
25221
25222bool isPMINSD(unsigned Opcode) {
25223 switch (Opcode) {
25224 case PMINSDrm:
25225 case PMINSDrr:
25226 return true;
25227 }
25228 return false;
25229}
25230
25231bool isPFRCP(unsigned Opcode) {
25232 switch (Opcode) {
25233 case PFRCPrm:
25234 case PFRCPrr:
25235 return true;
25236 }
25237 return false;
25238}
25239
25240bool isKTESTQ(unsigned Opcode) {
25241 return Opcode == KTESTQkk;
25242}
25243
25244bool isVCVTTPD2DQ(unsigned Opcode) {
25245 switch (Opcode) {
25246 case VCVTTPD2DQYrm:
25247 case VCVTTPD2DQYrr:
25248 case VCVTTPD2DQZ128rm:
25249 case VCVTTPD2DQZ128rmb:
25250 case VCVTTPD2DQZ128rmbk:
25251 case VCVTTPD2DQZ128rmbkz:
25252 case VCVTTPD2DQZ128rmk:
25253 case VCVTTPD2DQZ128rmkz:
25254 case VCVTTPD2DQZ128rr:
25255 case VCVTTPD2DQZ128rrk:
25256 case VCVTTPD2DQZ128rrkz:
25257 case VCVTTPD2DQZ256rm:
25258 case VCVTTPD2DQZ256rmb:
25259 case VCVTTPD2DQZ256rmbk:
25260 case VCVTTPD2DQZ256rmbkz:
25261 case VCVTTPD2DQZ256rmk:
25262 case VCVTTPD2DQZ256rmkz:
25263 case VCVTTPD2DQZ256rr:
25264 case VCVTTPD2DQZ256rrk:
25265 case VCVTTPD2DQZ256rrkz:
25266 case VCVTTPD2DQZrm:
25267 case VCVTTPD2DQZrmb:
25268 case VCVTTPD2DQZrmbk:
25269 case VCVTTPD2DQZrmbkz:
25270 case VCVTTPD2DQZrmk:
25271 case VCVTTPD2DQZrmkz:
25272 case VCVTTPD2DQZrr:
25273 case VCVTTPD2DQZrrb:
25274 case VCVTTPD2DQZrrbk:
25275 case VCVTTPD2DQZrrbkz:
25276 case VCVTTPD2DQZrrk:
25277 case VCVTTPD2DQZrrkz:
25278 case VCVTTPD2DQrm:
25279 case VCVTTPD2DQrr:
25280 return true;
25281 }
25282 return false;
25283}
25284
25285bool isVSHUFF32X4(unsigned Opcode) {
25286 switch (Opcode) {
25287 case VSHUFF32X4Z256rmbi:
25288 case VSHUFF32X4Z256rmbik:
25289 case VSHUFF32X4Z256rmbikz:
25290 case VSHUFF32X4Z256rmi:
25291 case VSHUFF32X4Z256rmik:
25292 case VSHUFF32X4Z256rmikz:
25293 case VSHUFF32X4Z256rri:
25294 case VSHUFF32X4Z256rrik:
25295 case VSHUFF32X4Z256rrikz:
25296 case VSHUFF32X4Zrmbi:
25297 case VSHUFF32X4Zrmbik:
25298 case VSHUFF32X4Zrmbikz:
25299 case VSHUFF32X4Zrmi:
25300 case VSHUFF32X4Zrmik:
25301 case VSHUFF32X4Zrmikz:
25302 case VSHUFF32X4Zrri:
25303 case VSHUFF32X4Zrrik:
25304 case VSHUFF32X4Zrrikz:
25305 return true;
25306 }
25307 return false;
25308}
25309
25310bool isVPSLLVW(unsigned Opcode) {
25311 switch (Opcode) {
25312 case VPSLLVWZ128rm:
25313 case VPSLLVWZ128rmk:
25314 case VPSLLVWZ128rmkz:
25315 case VPSLLVWZ128rr:
25316 case VPSLLVWZ128rrk:
25317 case VPSLLVWZ128rrkz:
25318 case VPSLLVWZ256rm:
25319 case VPSLLVWZ256rmk:
25320 case VPSLLVWZ256rmkz:
25321 case VPSLLVWZ256rr:
25322 case VPSLLVWZ256rrk:
25323 case VPSLLVWZ256rrkz:
25324 case VPSLLVWZrm:
25325 case VPSLLVWZrmk:
25326 case VPSLLVWZrmkz:
25327 case VPSLLVWZrr:
25328 case VPSLLVWZrrk:
25329 case VPSLLVWZrrkz:
25330 return true;
25331 }
25332 return false;
25333}
25334
25335bool isTDPBSUD(unsigned Opcode) {
25336 return Opcode == TDPBSUD;
25337}
25338
25339bool isVPMINUQ(unsigned Opcode) {
25340 switch (Opcode) {
25341 case VPMINUQZ128rm:
25342 case VPMINUQZ128rmb:
25343 case VPMINUQZ128rmbk:
25344 case VPMINUQZ128rmbkz:
25345 case VPMINUQZ128rmk:
25346 case VPMINUQZ128rmkz:
25347 case VPMINUQZ128rr:
25348 case VPMINUQZ128rrk:
25349 case VPMINUQZ128rrkz:
25350 case VPMINUQZ256rm:
25351 case VPMINUQZ256rmb:
25352 case VPMINUQZ256rmbk:
25353 case VPMINUQZ256rmbkz:
25354 case VPMINUQZ256rmk:
25355 case VPMINUQZ256rmkz:
25356 case VPMINUQZ256rr:
25357 case VPMINUQZ256rrk:
25358 case VPMINUQZ256rrkz:
25359 case VPMINUQZrm:
25360 case VPMINUQZrmb:
25361 case VPMINUQZrmbk:
25362 case VPMINUQZrmbkz:
25363 case VPMINUQZrmk:
25364 case VPMINUQZrmkz:
25365 case VPMINUQZrr:
25366 case VPMINUQZrrk:
25367 case VPMINUQZrrkz:
25368 return true;
25369 }
25370 return false;
25371}
25372
25373bool isFIADD(unsigned Opcode) {
25374 switch (Opcode) {
25375 case ADD_FI16m:
25376 case ADD_FI32m:
25377 return true;
25378 }
25379 return false;
25380}
25381
25382bool isFCMOVNU(unsigned Opcode) {
25383 return Opcode == CMOVNP_F;
25384}
25385
25386bool isVHSUBPD(unsigned Opcode) {
25387 switch (Opcode) {
25388 case VHSUBPDYrm:
25389 case VHSUBPDYrr:
25390 case VHSUBPDrm:
25391 case VHSUBPDrr:
25392 return true;
25393 }
25394 return false;
25395}
25396
25397bool isKSHIFTRQ(unsigned Opcode) {
25398 return Opcode == KSHIFTRQki;
25399}
25400
25401bool isMOVUPS(unsigned Opcode) {
25402 switch (Opcode) {
25403 case MOVUPSmr:
25404 case MOVUPSrm:
25405 case MOVUPSrr:
25406 case MOVUPSrr_REV:
25407 return true;
25408 }
25409 return false;
25410}
25411
25412bool isVMCALL(unsigned Opcode) {
25413 return Opcode == VMCALL;
25414}
25415
25416bool isXADD(unsigned Opcode) {
25417 switch (Opcode) {
25418 case XADD16rm:
25419 case XADD16rr:
25420 case XADD32rm:
25421 case XADD32rr:
25422 case XADD64rm:
25423 case XADD64rr:
25424 case XADD8rm:
25425 case XADD8rr:
25426 return true;
25427 }
25428 return false;
25429}
25430
25431bool isXRSTOR(unsigned Opcode) {
25432 return Opcode == XRSTOR;
25433}
25434
25435bool isVGATHERPF1DPD(unsigned Opcode) {
25436 return Opcode == VGATHERPF1DPDm;
25437}
25438
25439bool isRCR(unsigned Opcode) {
25440 switch (Opcode) {
25441 case RCR16m1:
25442 case RCR16m1_EVEX:
25443 case RCR16m1_ND:
25444 case RCR16mCL:
25445 case RCR16mCL_EVEX:
25446 case RCR16mCL_ND:
25447 case RCR16mi:
25448 case RCR16mi_EVEX:
25449 case RCR16mi_ND:
25450 case RCR16r1:
25451 case RCR16r1_EVEX:
25452 case RCR16r1_ND:
25453 case RCR16rCL:
25454 case RCR16rCL_EVEX:
25455 case RCR16rCL_ND:
25456 case RCR16ri:
25457 case RCR16ri_EVEX:
25458 case RCR16ri_ND:
25459 case RCR32m1:
25460 case RCR32m1_EVEX:
25461 case RCR32m1_ND:
25462 case RCR32mCL:
25463 case RCR32mCL_EVEX:
25464 case RCR32mCL_ND:
25465 case RCR32mi:
25466 case RCR32mi_EVEX:
25467 case RCR32mi_ND:
25468 case RCR32r1:
25469 case RCR32r1_EVEX:
25470 case RCR32r1_ND:
25471 case RCR32rCL:
25472 case RCR32rCL_EVEX:
25473 case RCR32rCL_ND:
25474 case RCR32ri:
25475 case RCR32ri_EVEX:
25476 case RCR32ri_ND:
25477 case RCR64m1:
25478 case RCR64m1_EVEX:
25479 case RCR64m1_ND:
25480 case RCR64mCL:
25481 case RCR64mCL_EVEX:
25482 case RCR64mCL_ND:
25483 case RCR64mi:
25484 case RCR64mi_EVEX:
25485 case RCR64mi_ND:
25486 case RCR64r1:
25487 case RCR64r1_EVEX:
25488 case RCR64r1_ND:
25489 case RCR64rCL:
25490 case RCR64rCL_EVEX:
25491 case RCR64rCL_ND:
25492 case RCR64ri:
25493 case RCR64ri_EVEX:
25494 case RCR64ri_ND:
25495 case RCR8m1:
25496 case RCR8m1_EVEX:
25497 case RCR8m1_ND:
25498 case RCR8mCL:
25499 case RCR8mCL_EVEX:
25500 case RCR8mCL_ND:
25501 case RCR8mi:
25502 case RCR8mi_EVEX:
25503 case RCR8mi_ND:
25504 case RCR8r1:
25505 case RCR8r1_EVEX:
25506 case RCR8r1_ND:
25507 case RCR8rCL:
25508 case RCR8rCL_EVEX:
25509 case RCR8rCL_ND:
25510 case RCR8ri:
25511 case RCR8ri_EVEX:
25512 case RCR8ri_ND:
25513 return true;
25514 }
25515 return false;
25516}
25517
25518bool isFNSTCW(unsigned Opcode) {
25519 return Opcode == FNSTCW16m;
25520}
25521
25522bool isVPMOVSDW(unsigned Opcode) {
25523 switch (Opcode) {
25524 case VPMOVSDWZ128mr:
25525 case VPMOVSDWZ128mrk:
25526 case VPMOVSDWZ128rr:
25527 case VPMOVSDWZ128rrk:
25528 case VPMOVSDWZ128rrkz:
25529 case VPMOVSDWZ256mr:
25530 case VPMOVSDWZ256mrk:
25531 case VPMOVSDWZ256rr:
25532 case VPMOVSDWZ256rrk:
25533 case VPMOVSDWZ256rrkz:
25534 case VPMOVSDWZmr:
25535 case VPMOVSDWZmrk:
25536 case VPMOVSDWZrr:
25537 case VPMOVSDWZrrk:
25538 case VPMOVSDWZrrkz:
25539 return true;
25540 }
25541 return false;
25542}
25543
25544bool isVFMSUB132SH(unsigned Opcode) {
25545 switch (Opcode) {
25546 case VFMSUB132SHZm_Int:
25547 case VFMSUB132SHZmk_Int:
25548 case VFMSUB132SHZmkz_Int:
25549 case VFMSUB132SHZr_Int:
25550 case VFMSUB132SHZrb_Int:
25551 case VFMSUB132SHZrbk_Int:
25552 case VFMSUB132SHZrbkz_Int:
25553 case VFMSUB132SHZrk_Int:
25554 case VFMSUB132SHZrkz_Int:
25555 return true;
25556 }
25557 return false;
25558}
25559
25560bool isVPCONFLICTQ(unsigned Opcode) {
25561 switch (Opcode) {
25562 case VPCONFLICTQZ128rm:
25563 case VPCONFLICTQZ128rmb:
25564 case VPCONFLICTQZ128rmbk:
25565 case VPCONFLICTQZ128rmbkz:
25566 case VPCONFLICTQZ128rmk:
25567 case VPCONFLICTQZ128rmkz:
25568 case VPCONFLICTQZ128rr:
25569 case VPCONFLICTQZ128rrk:
25570 case VPCONFLICTQZ128rrkz:
25571 case VPCONFLICTQZ256rm:
25572 case VPCONFLICTQZ256rmb:
25573 case VPCONFLICTQZ256rmbk:
25574 case VPCONFLICTQZ256rmbkz:
25575 case VPCONFLICTQZ256rmk:
25576 case VPCONFLICTQZ256rmkz:
25577 case VPCONFLICTQZ256rr:
25578 case VPCONFLICTQZ256rrk:
25579 case VPCONFLICTQZ256rrkz:
25580 case VPCONFLICTQZrm:
25581 case VPCONFLICTQZrmb:
25582 case VPCONFLICTQZrmbk:
25583 case VPCONFLICTQZrmbkz:
25584 case VPCONFLICTQZrmk:
25585 case VPCONFLICTQZrmkz:
25586 case VPCONFLICTQZrr:
25587 case VPCONFLICTQZrrk:
25588 case VPCONFLICTQZrrkz:
25589 return true;
25590 }
25591 return false;
25592}
25593
25594bool isSWAPGS(unsigned Opcode) {
25595 return Opcode == SWAPGS;
25596}
25597
25598bool isVPMOVQ2M(unsigned Opcode) {
25599 switch (Opcode) {
25600 case VPMOVQ2MZ128kr:
25601 case VPMOVQ2MZ256kr:
25602 case VPMOVQ2MZkr:
25603 return true;
25604 }
25605 return false;
25606}
25607
25608bool isVPSRAVW(unsigned Opcode) {
25609 switch (Opcode) {
25610 case VPSRAVWZ128rm:
25611 case VPSRAVWZ128rmk:
25612 case VPSRAVWZ128rmkz:
25613 case VPSRAVWZ128rr:
25614 case VPSRAVWZ128rrk:
25615 case VPSRAVWZ128rrkz:
25616 case VPSRAVWZ256rm:
25617 case VPSRAVWZ256rmk:
25618 case VPSRAVWZ256rmkz:
25619 case VPSRAVWZ256rr:
25620 case VPSRAVWZ256rrk:
25621 case VPSRAVWZ256rrkz:
25622 case VPSRAVWZrm:
25623 case VPSRAVWZrmk:
25624 case VPSRAVWZrmkz:
25625 case VPSRAVWZrr:
25626 case VPSRAVWZrrk:
25627 case VPSRAVWZrrkz:
25628 return true;
25629 }
25630 return false;
25631}
25632
25633bool isMOVDQA(unsigned Opcode) {
25634 switch (Opcode) {
25635 case MOVDQAmr:
25636 case MOVDQArm:
25637 case MOVDQArr:
25638 case MOVDQArr_REV:
25639 return true;
25640 }
25641 return false;
25642}
25643
25644bool isDIVSD(unsigned Opcode) {
25645 switch (Opcode) {
25646 case DIVSDrm_Int:
25647 case DIVSDrr_Int:
25648 return true;
25649 }
25650 return false;
25651}
25652
25653bool isPCMPGTB(unsigned Opcode) {
25654 switch (Opcode) {
25655 case MMX_PCMPGTBrm:
25656 case MMX_PCMPGTBrr:
25657 case PCMPGTBrm:
25658 case PCMPGTBrr:
25659 return true;
25660 }
25661 return false;
25662}
25663
25664bool isSHA256MSG2(unsigned Opcode) {
25665 switch (Opcode) {
25666 case SHA256MSG2rm:
25667 case SHA256MSG2rr:
25668 return true;
25669 }
25670 return false;
25671}
25672
25673bool isKXORW(unsigned Opcode) {
25674 return Opcode == KXORWkk;
25675}
25676
25677bool isLIDTW(unsigned Opcode) {
25678 return Opcode == LIDT16m;
25679}
25680
25681bool isPMULHW(unsigned Opcode) {
25682 switch (Opcode) {
25683 case MMX_PMULHWrm:
25684 case MMX_PMULHWrr:
25685 case PMULHWrm:
25686 case PMULHWrr:
25687 return true;
25688 }
25689 return false;
25690}
25691
25692bool isVAESENCLAST(unsigned Opcode) {
25693 switch (Opcode) {
25694 case VAESENCLASTYrm:
25695 case VAESENCLASTYrr:
25696 case VAESENCLASTZ128rm:
25697 case VAESENCLASTZ128rr:
25698 case VAESENCLASTZ256rm:
25699 case VAESENCLASTZ256rr:
25700 case VAESENCLASTZrm:
25701 case VAESENCLASTZrr:
25702 case VAESENCLASTrm:
25703 case VAESENCLASTrr:
25704 return true;
25705 }
25706 return false;
25707}
25708
25709bool isVINSERTI32X8(unsigned Opcode) {
25710 switch (Opcode) {
25711 case VINSERTI32X8Zrmi:
25712 case VINSERTI32X8Zrmik:
25713 case VINSERTI32X8Zrmikz:
25714 case VINSERTI32X8Zrri:
25715 case VINSERTI32X8Zrrik:
25716 case VINSERTI32X8Zrrikz:
25717 return true;
25718 }
25719 return false;
25720}
25721
25722bool isVRCPPS(unsigned Opcode) {
25723 switch (Opcode) {
25724 case VRCPPSYm:
25725 case VRCPPSYr:
25726 case VRCPPSm:
25727 case VRCPPSr:
25728 return true;
25729 }
25730 return false;
25731}
25732
25733bool isVRSQRTBF16(unsigned Opcode) {
25734 switch (Opcode) {
25735 case VRSQRTBF16Z128m:
25736 case VRSQRTBF16Z128mb:
25737 case VRSQRTBF16Z128mbk:
25738 case VRSQRTBF16Z128mbkz:
25739 case VRSQRTBF16Z128mk:
25740 case VRSQRTBF16Z128mkz:
25741 case VRSQRTBF16Z128r:
25742 case VRSQRTBF16Z128rk:
25743 case VRSQRTBF16Z128rkz:
25744 case VRSQRTBF16Z256m:
25745 case VRSQRTBF16Z256mb:
25746 case VRSQRTBF16Z256mbk:
25747 case VRSQRTBF16Z256mbkz:
25748 case VRSQRTBF16Z256mk:
25749 case VRSQRTBF16Z256mkz:
25750 case VRSQRTBF16Z256r:
25751 case VRSQRTBF16Z256rk:
25752 case VRSQRTBF16Z256rkz:
25753 case VRSQRTBF16Zm:
25754 case VRSQRTBF16Zmb:
25755 case VRSQRTBF16Zmbk:
25756 case VRSQRTBF16Zmbkz:
25757 case VRSQRTBF16Zmk:
25758 case VRSQRTBF16Zmkz:
25759 case VRSQRTBF16Zr:
25760 case VRSQRTBF16Zrk:
25761 case VRSQRTBF16Zrkz:
25762 return true;
25763 }
25764 return false;
25765}
25766
25767bool isVGATHERQPS(unsigned Opcode) {
25768 switch (Opcode) {
25769 case VGATHERQPSYrm:
25770 case VGATHERQPSZ128rm:
25771 case VGATHERQPSZ256rm:
25772 case VGATHERQPSZrm:
25773 case VGATHERQPSrm:
25774 return true;
25775 }
25776 return false;
25777}
25778
25779bool isCTESTCC(unsigned Opcode) {
25780 switch (Opcode) {
25781 case CTEST16mi:
25782 case CTEST16mr:
25783 case CTEST16ri:
25784 case CTEST16rr:
25785 case CTEST32mi:
25786 case CTEST32mr:
25787 case CTEST32ri:
25788 case CTEST32rr:
25789 case CTEST64mi32:
25790 case CTEST64mr:
25791 case CTEST64ri32:
25792 case CTEST64rr:
25793 case CTEST8mi:
25794 case CTEST8mr:
25795 case CTEST8ri:
25796 case CTEST8rr:
25797 return true;
25798 }
25799 return false;
25800}
25801
25802bool isPMADDWD(unsigned Opcode) {
25803 switch (Opcode) {
25804 case MMX_PMADDWDrm:
25805 case MMX_PMADDWDrr:
25806 case PMADDWDrm:
25807 case PMADDWDrr:
25808 return true;
25809 }
25810 return false;
25811}
25812
25813bool isUCOMISS(unsigned Opcode) {
25814 switch (Opcode) {
25815 case UCOMISSrm:
25816 case UCOMISSrr:
25817 return true;
25818 }
25819 return false;
25820}
25821
25822bool isXGETBV(unsigned Opcode) {
25823 return Opcode == XGETBV;
25824}
25825
25826bool isVCVTPD2QQ(unsigned Opcode) {
25827 switch (Opcode) {
25828 case VCVTPD2QQZ128rm:
25829 case VCVTPD2QQZ128rmb:
25830 case VCVTPD2QQZ128rmbk:
25831 case VCVTPD2QQZ128rmbkz:
25832 case VCVTPD2QQZ128rmk:
25833 case VCVTPD2QQZ128rmkz:
25834 case VCVTPD2QQZ128rr:
25835 case VCVTPD2QQZ128rrk:
25836 case VCVTPD2QQZ128rrkz:
25837 case VCVTPD2QQZ256rm:
25838 case VCVTPD2QQZ256rmb:
25839 case VCVTPD2QQZ256rmbk:
25840 case VCVTPD2QQZ256rmbkz:
25841 case VCVTPD2QQZ256rmk:
25842 case VCVTPD2QQZ256rmkz:
25843 case VCVTPD2QQZ256rr:
25844 case VCVTPD2QQZ256rrk:
25845 case VCVTPD2QQZ256rrkz:
25846 case VCVTPD2QQZrm:
25847 case VCVTPD2QQZrmb:
25848 case VCVTPD2QQZrmbk:
25849 case VCVTPD2QQZrmbkz:
25850 case VCVTPD2QQZrmk:
25851 case VCVTPD2QQZrmkz:
25852 case VCVTPD2QQZrr:
25853 case VCVTPD2QQZrrb:
25854 case VCVTPD2QQZrrbk:
25855 case VCVTPD2QQZrrbkz:
25856 case VCVTPD2QQZrrk:
25857 case VCVTPD2QQZrrkz:
25858 return true;
25859 }
25860 return false;
25861}
25862
25863bool isVGETEXPPS(unsigned Opcode) {
25864 switch (Opcode) {
25865 case VGETEXPPSZ128m:
25866 case VGETEXPPSZ128mb:
25867 case VGETEXPPSZ128mbk:
25868 case VGETEXPPSZ128mbkz:
25869 case VGETEXPPSZ128mk:
25870 case VGETEXPPSZ128mkz:
25871 case VGETEXPPSZ128r:
25872 case VGETEXPPSZ128rk:
25873 case VGETEXPPSZ128rkz:
25874 case VGETEXPPSZ256m:
25875 case VGETEXPPSZ256mb:
25876 case VGETEXPPSZ256mbk:
25877 case VGETEXPPSZ256mbkz:
25878 case VGETEXPPSZ256mk:
25879 case VGETEXPPSZ256mkz:
25880 case VGETEXPPSZ256r:
25881 case VGETEXPPSZ256rk:
25882 case VGETEXPPSZ256rkz:
25883 case VGETEXPPSZm:
25884 case VGETEXPPSZmb:
25885 case VGETEXPPSZmbk:
25886 case VGETEXPPSZmbkz:
25887 case VGETEXPPSZmk:
25888 case VGETEXPPSZmkz:
25889 case VGETEXPPSZr:
25890 case VGETEXPPSZrb:
25891 case VGETEXPPSZrbk:
25892 case VGETEXPPSZrbkz:
25893 case VGETEXPPSZrk:
25894 case VGETEXPPSZrkz:
25895 return true;
25896 }
25897 return false;
25898}
25899
25900bool isFISTP(unsigned Opcode) {
25901 switch (Opcode) {
25902 case IST_FP16m:
25903 case IST_FP32m:
25904 case IST_FP64m:
25905 return true;
25906 }
25907 return false;
25908}
25909
25910bool isVINSERTF64X4(unsigned Opcode) {
25911 switch (Opcode) {
25912 case VINSERTF64X4Zrmi:
25913 case VINSERTF64X4Zrmik:
25914 case VINSERTF64X4Zrmikz:
25915 case VINSERTF64X4Zrri:
25916 case VINSERTF64X4Zrrik:
25917 case VINSERTF64X4Zrrikz:
25918 return true;
25919 }
25920 return false;
25921}
25922
25923bool isVMOVDQU16(unsigned Opcode) {
25924 switch (Opcode) {
25925 case VMOVDQU16Z128mr:
25926 case VMOVDQU16Z128mrk:
25927 case VMOVDQU16Z128rm:
25928 case VMOVDQU16Z128rmk:
25929 case VMOVDQU16Z128rmkz:
25930 case VMOVDQU16Z128rr:
25931 case VMOVDQU16Z128rr_REV:
25932 case VMOVDQU16Z128rrk:
25933 case VMOVDQU16Z128rrk_REV:
25934 case VMOVDQU16Z128rrkz:
25935 case VMOVDQU16Z128rrkz_REV:
25936 case VMOVDQU16Z256mr:
25937 case VMOVDQU16Z256mrk:
25938 case VMOVDQU16Z256rm:
25939 case VMOVDQU16Z256rmk:
25940 case VMOVDQU16Z256rmkz:
25941 case VMOVDQU16Z256rr:
25942 case VMOVDQU16Z256rr_REV:
25943 case VMOVDQU16Z256rrk:
25944 case VMOVDQU16Z256rrk_REV:
25945 case VMOVDQU16Z256rrkz:
25946 case VMOVDQU16Z256rrkz_REV:
25947 case VMOVDQU16Zmr:
25948 case VMOVDQU16Zmrk:
25949 case VMOVDQU16Zrm:
25950 case VMOVDQU16Zrmk:
25951 case VMOVDQU16Zrmkz:
25952 case VMOVDQU16Zrr:
25953 case VMOVDQU16Zrr_REV:
25954 case VMOVDQU16Zrrk:
25955 case VMOVDQU16Zrrk_REV:
25956 case VMOVDQU16Zrrkz:
25957 case VMOVDQU16Zrrkz_REV:
25958 return true;
25959 }
25960 return false;
25961}
25962
25963bool isVFMADD132PH(unsigned Opcode) {
25964 switch (Opcode) {
25965 case VFMADD132PHZ128m:
25966 case VFMADD132PHZ128mb:
25967 case VFMADD132PHZ128mbk:
25968 case VFMADD132PHZ128mbkz:
25969 case VFMADD132PHZ128mk:
25970 case VFMADD132PHZ128mkz:
25971 case VFMADD132PHZ128r:
25972 case VFMADD132PHZ128rk:
25973 case VFMADD132PHZ128rkz:
25974 case VFMADD132PHZ256m:
25975 case VFMADD132PHZ256mb:
25976 case VFMADD132PHZ256mbk:
25977 case VFMADD132PHZ256mbkz:
25978 case VFMADD132PHZ256mk:
25979 case VFMADD132PHZ256mkz:
25980 case VFMADD132PHZ256r:
25981 case VFMADD132PHZ256rk:
25982 case VFMADD132PHZ256rkz:
25983 case VFMADD132PHZm:
25984 case VFMADD132PHZmb:
25985 case VFMADD132PHZmbk:
25986 case VFMADD132PHZmbkz:
25987 case VFMADD132PHZmk:
25988 case VFMADD132PHZmkz:
25989 case VFMADD132PHZr:
25990 case VFMADD132PHZrb:
25991 case VFMADD132PHZrbk:
25992 case VFMADD132PHZrbkz:
25993 case VFMADD132PHZrk:
25994 case VFMADD132PHZrkz:
25995 return true;
25996 }
25997 return false;
25998}
25999
26000bool isVFMSUBADD213PS(unsigned Opcode) {
26001 switch (Opcode) {
26002 case VFMSUBADD213PSYm:
26003 case VFMSUBADD213PSYr:
26004 case VFMSUBADD213PSZ128m:
26005 case VFMSUBADD213PSZ128mb:
26006 case VFMSUBADD213PSZ128mbk:
26007 case VFMSUBADD213PSZ128mbkz:
26008 case VFMSUBADD213PSZ128mk:
26009 case VFMSUBADD213PSZ128mkz:
26010 case VFMSUBADD213PSZ128r:
26011 case VFMSUBADD213PSZ128rk:
26012 case VFMSUBADD213PSZ128rkz:
26013 case VFMSUBADD213PSZ256m:
26014 case VFMSUBADD213PSZ256mb:
26015 case VFMSUBADD213PSZ256mbk:
26016 case VFMSUBADD213PSZ256mbkz:
26017 case VFMSUBADD213PSZ256mk:
26018 case VFMSUBADD213PSZ256mkz:
26019 case VFMSUBADD213PSZ256r:
26020 case VFMSUBADD213PSZ256rk:
26021 case VFMSUBADD213PSZ256rkz:
26022 case VFMSUBADD213PSZm:
26023 case VFMSUBADD213PSZmb:
26024 case VFMSUBADD213PSZmbk:
26025 case VFMSUBADD213PSZmbkz:
26026 case VFMSUBADD213PSZmk:
26027 case VFMSUBADD213PSZmkz:
26028 case VFMSUBADD213PSZr:
26029 case VFMSUBADD213PSZrb:
26030 case VFMSUBADD213PSZrbk:
26031 case VFMSUBADD213PSZrbkz:
26032 case VFMSUBADD213PSZrk:
26033 case VFMSUBADD213PSZrkz:
26034 case VFMSUBADD213PSm:
26035 case VFMSUBADD213PSr:
26036 return true;
26037 }
26038 return false;
26039}
26040
26041bool isVMOVDQU32(unsigned Opcode) {
26042 switch (Opcode) {
26043 case VMOVDQU32Z128mr:
26044 case VMOVDQU32Z128mrk:
26045 case VMOVDQU32Z128rm:
26046 case VMOVDQU32Z128rmk:
26047 case VMOVDQU32Z128rmkz:
26048 case VMOVDQU32Z128rr:
26049 case VMOVDQU32Z128rr_REV:
26050 case VMOVDQU32Z128rrk:
26051 case VMOVDQU32Z128rrk_REV:
26052 case VMOVDQU32Z128rrkz:
26053 case VMOVDQU32Z128rrkz_REV:
26054 case VMOVDQU32Z256mr:
26055 case VMOVDQU32Z256mrk:
26056 case VMOVDQU32Z256rm:
26057 case VMOVDQU32Z256rmk:
26058 case VMOVDQU32Z256rmkz:
26059 case VMOVDQU32Z256rr:
26060 case VMOVDQU32Z256rr_REV:
26061 case VMOVDQU32Z256rrk:
26062 case VMOVDQU32Z256rrk_REV:
26063 case VMOVDQU32Z256rrkz:
26064 case VMOVDQU32Z256rrkz_REV:
26065 case VMOVDQU32Zmr:
26066 case VMOVDQU32Zmrk:
26067 case VMOVDQU32Zrm:
26068 case VMOVDQU32Zrmk:
26069 case VMOVDQU32Zrmkz:
26070 case VMOVDQU32Zrr:
26071 case VMOVDQU32Zrr_REV:
26072 case VMOVDQU32Zrrk:
26073 case VMOVDQU32Zrrk_REV:
26074 case VMOVDQU32Zrrkz:
26075 case VMOVDQU32Zrrkz_REV:
26076 return true;
26077 }
26078 return false;
26079}
26080
26081bool isFUCOM(unsigned Opcode) {
26082 return Opcode == UCOM_Fr;
26083}
26084
26085bool isVFNMADD213BF16(unsigned Opcode) {
26086 switch (Opcode) {
26087 case VFNMADD213BF16Z128m:
26088 case VFNMADD213BF16Z128mb:
26089 case VFNMADD213BF16Z128mbk:
26090 case VFNMADD213BF16Z128mbkz:
26091 case VFNMADD213BF16Z128mk:
26092 case VFNMADD213BF16Z128mkz:
26093 case VFNMADD213BF16Z128r:
26094 case VFNMADD213BF16Z128rk:
26095 case VFNMADD213BF16Z128rkz:
26096 case VFNMADD213BF16Z256m:
26097 case VFNMADD213BF16Z256mb:
26098 case VFNMADD213BF16Z256mbk:
26099 case VFNMADD213BF16Z256mbkz:
26100 case VFNMADD213BF16Z256mk:
26101 case VFNMADD213BF16Z256mkz:
26102 case VFNMADD213BF16Z256r:
26103 case VFNMADD213BF16Z256rk:
26104 case VFNMADD213BF16Z256rkz:
26105 case VFNMADD213BF16Zm:
26106 case VFNMADD213BF16Zmb:
26107 case VFNMADD213BF16Zmbk:
26108 case VFNMADD213BF16Zmbkz:
26109 case VFNMADD213BF16Zmk:
26110 case VFNMADD213BF16Zmkz:
26111 case VFNMADD213BF16Zr:
26112 case VFNMADD213BF16Zrk:
26113 case VFNMADD213BF16Zrkz:
26114 return true;
26115 }
26116 return false;
26117}
26118
26119bool isHADDPS(unsigned Opcode) {
26120 switch (Opcode) {
26121 case HADDPSrm:
26122 case HADDPSrr:
26123 return true;
26124 }
26125 return false;
26126}
26127
26128bool isCMP(unsigned Opcode) {
26129 switch (Opcode) {
26130 case CMP16i16:
26131 case CMP16mi:
26132 case CMP16mi8:
26133 case CMP16mr:
26134 case CMP16ri:
26135 case CMP16ri8:
26136 case CMP16rm:
26137 case CMP16rr:
26138 case CMP16rr_REV:
26139 case CMP32i32:
26140 case CMP32mi:
26141 case CMP32mi8:
26142 case CMP32mr:
26143 case CMP32ri:
26144 case CMP32ri8:
26145 case CMP32rm:
26146 case CMP32rr:
26147 case CMP32rr_REV:
26148 case CMP64i32:
26149 case CMP64mi32:
26150 case CMP64mi8:
26151 case CMP64mr:
26152 case CMP64ri32:
26153 case CMP64ri8:
26154 case CMP64rm:
26155 case CMP64rr:
26156 case CMP64rr_REV:
26157 case CMP8i8:
26158 case CMP8mi:
26159 case CMP8mi8:
26160 case CMP8mr:
26161 case CMP8ri:
26162 case CMP8ri8:
26163 case CMP8rm:
26164 case CMP8rr:
26165 case CMP8rr_REV:
26166 return true;
26167 }
26168 return false;
26169}
26170
26171bool isCVTTPS2PI(unsigned Opcode) {
26172 switch (Opcode) {
26173 case MMX_CVTTPS2PIrm:
26174 case MMX_CVTTPS2PIrr:
26175 return true;
26176 }
26177 return false;
26178}
26179
26180bool isIRETQ(unsigned Opcode) {
26181 return Opcode == IRET64;
26182}
26183
26184bool isPF2IW(unsigned Opcode) {
26185 switch (Opcode) {
26186 case PF2IWrm:
26187 case PF2IWrr:
26188 return true;
26189 }
26190 return false;
26191}
26192
26193bool isPSHUFD(unsigned Opcode) {
26194 switch (Opcode) {
26195 case PSHUFDmi:
26196 case PSHUFDri:
26197 return true;
26198 }
26199 return false;
26200}
26201
26202bool isVDPPD(unsigned Opcode) {
26203 switch (Opcode) {
26204 case VDPPDrmi:
26205 case VDPPDrri:
26206 return true;
26207 }
26208 return false;
26209}
26210
26211bool isPSHUFHW(unsigned Opcode) {
26212 switch (Opcode) {
26213 case PSHUFHWmi:
26214 case PSHUFHWri:
26215 return true;
26216 }
26217 return false;
26218}
26219
26220bool isRMPADJUST(unsigned Opcode) {
26221 return Opcode == RMPADJUST;
26222}
26223
26224bool isPI2FW(unsigned Opcode) {
26225 switch (Opcode) {
26226 case PI2FWrm:
26227 case PI2FWrr:
26228 return true;
26229 }
26230 return false;
26231}
26232
26233bool isVCVTTPH2QQ(unsigned Opcode) {
26234 switch (Opcode) {
26235 case VCVTTPH2QQZ128rm:
26236 case VCVTTPH2QQZ128rmb:
26237 case VCVTTPH2QQZ128rmbk:
26238 case VCVTTPH2QQZ128rmbkz:
26239 case VCVTTPH2QQZ128rmk:
26240 case VCVTTPH2QQZ128rmkz:
26241 case VCVTTPH2QQZ128rr:
26242 case VCVTTPH2QQZ128rrk:
26243 case VCVTTPH2QQZ128rrkz:
26244 case VCVTTPH2QQZ256rm:
26245 case VCVTTPH2QQZ256rmb:
26246 case VCVTTPH2QQZ256rmbk:
26247 case VCVTTPH2QQZ256rmbkz:
26248 case VCVTTPH2QQZ256rmk:
26249 case VCVTTPH2QQZ256rmkz:
26250 case VCVTTPH2QQZ256rr:
26251 case VCVTTPH2QQZ256rrk:
26252 case VCVTTPH2QQZ256rrkz:
26253 case VCVTTPH2QQZrm:
26254 case VCVTTPH2QQZrmb:
26255 case VCVTTPH2QQZrmbk:
26256 case VCVTTPH2QQZrmbkz:
26257 case VCVTTPH2QQZrmk:
26258 case VCVTTPH2QQZrmkz:
26259 case VCVTTPH2QQZrr:
26260 case VCVTTPH2QQZrrb:
26261 case VCVTTPH2QQZrrbk:
26262 case VCVTTPH2QQZrrbkz:
26263 case VCVTTPH2QQZrrk:
26264 case VCVTTPH2QQZrrkz:
26265 return true;
26266 }
26267 return false;
26268}
26269
26270bool isDIVPD(unsigned Opcode) {
26271 switch (Opcode) {
26272 case DIVPDrm:
26273 case DIVPDrr:
26274 return true;
26275 }
26276 return false;
26277}
26278
26279bool isCLFLUSH(unsigned Opcode) {
26280 return Opcode == CLFLUSH;
26281}
26282
26283bool isVPMINUW(unsigned Opcode) {
26284 switch (Opcode) {
26285 case VPMINUWYrm:
26286 case VPMINUWYrr:
26287 case VPMINUWZ128rm:
26288 case VPMINUWZ128rmk:
26289 case VPMINUWZ128rmkz:
26290 case VPMINUWZ128rr:
26291 case VPMINUWZ128rrk:
26292 case VPMINUWZ128rrkz:
26293 case VPMINUWZ256rm:
26294 case VPMINUWZ256rmk:
26295 case VPMINUWZ256rmkz:
26296 case VPMINUWZ256rr:
26297 case VPMINUWZ256rrk:
26298 case VPMINUWZ256rrkz:
26299 case VPMINUWZrm:
26300 case VPMINUWZrmk:
26301 case VPMINUWZrmkz:
26302 case VPMINUWZrr:
26303 case VPMINUWZrrk:
26304 case VPMINUWZrrkz:
26305 case VPMINUWrm:
26306 case VPMINUWrr:
26307 return true;
26308 }
26309 return false;
26310}
26311
26312bool isIN(unsigned Opcode) {
26313 switch (Opcode) {
26314 case IN16ri:
26315 case IN16rr:
26316 case IN32ri:
26317 case IN32rr:
26318 case IN8ri:
26319 case IN8rr:
26320 return true;
26321 }
26322 return false;
26323}
26324
26325bool isWRPKRU(unsigned Opcode) {
26326 return Opcode == WRPKRUr;
26327}
26328
26329bool isINSERTPS(unsigned Opcode) {
26330 switch (Opcode) {
26331 case INSERTPSrmi:
26332 case INSERTPSrri:
26333 return true;
26334 }
26335 return false;
26336}
26337
26338bool isAAM(unsigned Opcode) {
26339 return Opcode == AAM8i8;
26340}
26341
26342bool isVPHADDUDQ(unsigned Opcode) {
26343 switch (Opcode) {
26344 case VPHADDUDQrm:
26345 case VPHADDUDQrr:
26346 return true;
26347 }
26348 return false;
26349}
26350
26351bool isVSHA512MSG1(unsigned Opcode) {
26352 return Opcode == VSHA512MSG1rr;
26353}
26354
26355bool isDIVPS(unsigned Opcode) {
26356 switch (Opcode) {
26357 case DIVPSrm:
26358 case DIVPSrr:
26359 return true;
26360 }
26361 return false;
26362}
26363
26364bool isKNOTB(unsigned Opcode) {
26365 return Opcode == KNOTBkk;
26366}
26367
26368bool isBLSFILL(unsigned Opcode) {
26369 switch (Opcode) {
26370 case BLSFILL32rm:
26371 case BLSFILL32rr:
26372 case BLSFILL64rm:
26373 case BLSFILL64rr:
26374 return true;
26375 }
26376 return false;
26377}
26378
26379bool isVPCMPGTQ(unsigned Opcode) {
26380 switch (Opcode) {
26381 case VPCMPGTQYrm:
26382 case VPCMPGTQYrr:
26383 case VPCMPGTQZ128rm:
26384 case VPCMPGTQZ128rmb:
26385 case VPCMPGTQZ128rmbk:
26386 case VPCMPGTQZ128rmk:
26387 case VPCMPGTQZ128rr:
26388 case VPCMPGTQZ128rrk:
26389 case VPCMPGTQZ256rm:
26390 case VPCMPGTQZ256rmb:
26391 case VPCMPGTQZ256rmbk:
26392 case VPCMPGTQZ256rmk:
26393 case VPCMPGTQZ256rr:
26394 case VPCMPGTQZ256rrk:
26395 case VPCMPGTQZrm:
26396 case VPCMPGTQZrmb:
26397 case VPCMPGTQZrmbk:
26398 case VPCMPGTQZrmk:
26399 case VPCMPGTQZrr:
26400 case VPCMPGTQZrrk:
26401 case VPCMPGTQrm:
26402 case VPCMPGTQrr:
26403 return true;
26404 }
26405 return false;
26406}
26407
26408bool isMINSD(unsigned Opcode) {
26409 switch (Opcode) {
26410 case MINSDrm_Int:
26411 case MINSDrr_Int:
26412 return true;
26413 }
26414 return false;
26415}
26416
26417bool isFPREM(unsigned Opcode) {
26418 return Opcode == FPREM;
26419}
26420
26421bool isVPUNPCKHQDQ(unsigned Opcode) {
26422 switch (Opcode) {
26423 case VPUNPCKHQDQYrm:
26424 case VPUNPCKHQDQYrr:
26425 case VPUNPCKHQDQZ128rm:
26426 case VPUNPCKHQDQZ128rmb:
26427 case VPUNPCKHQDQZ128rmbk:
26428 case VPUNPCKHQDQZ128rmbkz:
26429 case VPUNPCKHQDQZ128rmk:
26430 case VPUNPCKHQDQZ128rmkz:
26431 case VPUNPCKHQDQZ128rr:
26432 case VPUNPCKHQDQZ128rrk:
26433 case VPUNPCKHQDQZ128rrkz:
26434 case VPUNPCKHQDQZ256rm:
26435 case VPUNPCKHQDQZ256rmb:
26436 case VPUNPCKHQDQZ256rmbk:
26437 case VPUNPCKHQDQZ256rmbkz:
26438 case VPUNPCKHQDQZ256rmk:
26439 case VPUNPCKHQDQZ256rmkz:
26440 case VPUNPCKHQDQZ256rr:
26441 case VPUNPCKHQDQZ256rrk:
26442 case VPUNPCKHQDQZ256rrkz:
26443 case VPUNPCKHQDQZrm:
26444 case VPUNPCKHQDQZrmb:
26445 case VPUNPCKHQDQZrmbk:
26446 case VPUNPCKHQDQZrmbkz:
26447 case VPUNPCKHQDQZrmk:
26448 case VPUNPCKHQDQZrmkz:
26449 case VPUNPCKHQDQZrr:
26450 case VPUNPCKHQDQZrrk:
26451 case VPUNPCKHQDQZrrkz:
26452 case VPUNPCKHQDQrm:
26453 case VPUNPCKHQDQrr:
26454 return true;
26455 }
26456 return false;
26457}
26458
26459bool isMINPD(unsigned Opcode) {
26460 switch (Opcode) {
26461 case MINPDrm:
26462 case MINPDrr:
26463 return true;
26464 }
26465 return false;
26466}
26467
26468bool isVCVTTPD2QQ(unsigned Opcode) {
26469 switch (Opcode) {
26470 case VCVTTPD2QQZ128rm:
26471 case VCVTTPD2QQZ128rmb:
26472 case VCVTTPD2QQZ128rmbk:
26473 case VCVTTPD2QQZ128rmbkz:
26474 case VCVTTPD2QQZ128rmk:
26475 case VCVTTPD2QQZ128rmkz:
26476 case VCVTTPD2QQZ128rr:
26477 case VCVTTPD2QQZ128rrk:
26478 case VCVTTPD2QQZ128rrkz:
26479 case VCVTTPD2QQZ256rm:
26480 case VCVTTPD2QQZ256rmb:
26481 case VCVTTPD2QQZ256rmbk:
26482 case VCVTTPD2QQZ256rmbkz:
26483 case VCVTTPD2QQZ256rmk:
26484 case VCVTTPD2QQZ256rmkz:
26485 case VCVTTPD2QQZ256rr:
26486 case VCVTTPD2QQZ256rrk:
26487 case VCVTTPD2QQZ256rrkz:
26488 case VCVTTPD2QQZrm:
26489 case VCVTTPD2QQZrmb:
26490 case VCVTTPD2QQZrmbk:
26491 case VCVTTPD2QQZrmbkz:
26492 case VCVTTPD2QQZrmk:
26493 case VCVTTPD2QQZrmkz:
26494 case VCVTTPD2QQZrr:
26495 case VCVTTPD2QQZrrb:
26496 case VCVTTPD2QQZrrbk:
26497 case VCVTTPD2QQZrrbkz:
26498 case VCVTTPD2QQZrrk:
26499 case VCVTTPD2QQZrrkz:
26500 return true;
26501 }
26502 return false;
26503}
26504
26505bool isVFMSUBPD(unsigned Opcode) {
26506 switch (Opcode) {
26507 case VFMSUBPD4Ymr:
26508 case VFMSUBPD4Yrm:
26509 case VFMSUBPD4Yrr:
26510 case VFMSUBPD4Yrr_REV:
26511 case VFMSUBPD4mr:
26512 case VFMSUBPD4rm:
26513 case VFMSUBPD4rr:
26514 case VFMSUBPD4rr_REV:
26515 return true;
26516 }
26517 return false;
26518}
26519
26520bool isV4FMADDSS(unsigned Opcode) {
26521 switch (Opcode) {
26522 case V4FMADDSSrm:
26523 case V4FMADDSSrmk:
26524 case V4FMADDSSrmkz:
26525 return true;
26526 }
26527 return false;
26528}
26529
26530bool isCPUID(unsigned Opcode) {
26531 return Opcode == CPUID;
26532}
26533
26534bool isSETCC(unsigned Opcode) {
26535 switch (Opcode) {
26536 case SETCCm:
26537 case SETCCm_EVEX:
26538 case SETCCr:
26539 case SETCCr_EVEX:
26540 return true;
26541 }
26542 return false;
26543}
26544
26545bool isVPDPWUUD(unsigned Opcode) {
26546 switch (Opcode) {
26547 case VPDPWUUDYrm:
26548 case VPDPWUUDYrr:
26549 case VPDPWUUDZ128rm:
26550 case VPDPWUUDZ128rmb:
26551 case VPDPWUUDZ128rmbk:
26552 case VPDPWUUDZ128rmbkz:
26553 case VPDPWUUDZ128rmk:
26554 case VPDPWUUDZ128rmkz:
26555 case VPDPWUUDZ128rr:
26556 case VPDPWUUDZ128rrk:
26557 case VPDPWUUDZ128rrkz:
26558 case VPDPWUUDZ256rm:
26559 case VPDPWUUDZ256rmb:
26560 case VPDPWUUDZ256rmbk:
26561 case VPDPWUUDZ256rmbkz:
26562 case VPDPWUUDZ256rmk:
26563 case VPDPWUUDZ256rmkz:
26564 case VPDPWUUDZ256rr:
26565 case VPDPWUUDZ256rrk:
26566 case VPDPWUUDZ256rrkz:
26567 case VPDPWUUDZrm:
26568 case VPDPWUUDZrmb:
26569 case VPDPWUUDZrmbk:
26570 case VPDPWUUDZrmbkz:
26571 case VPDPWUUDZrmk:
26572 case VPDPWUUDZrmkz:
26573 case VPDPWUUDZrr:
26574 case VPDPWUUDZrrk:
26575 case VPDPWUUDZrrkz:
26576 case VPDPWUUDrm:
26577 case VPDPWUUDrr:
26578 return true;
26579 }
26580 return false;
26581}
26582
26583bool isVCVTTPS2IUBS(unsigned Opcode) {
26584 switch (Opcode) {
26585 case VCVTTPS2IUBSZ128rm:
26586 case VCVTTPS2IUBSZ128rmb:
26587 case VCVTTPS2IUBSZ128rmbk:
26588 case VCVTTPS2IUBSZ128rmbkz:
26589 case VCVTTPS2IUBSZ128rmk:
26590 case VCVTTPS2IUBSZ128rmkz:
26591 case VCVTTPS2IUBSZ128rr:
26592 case VCVTTPS2IUBSZ128rrk:
26593 case VCVTTPS2IUBSZ128rrkz:
26594 case VCVTTPS2IUBSZ256rm:
26595 case VCVTTPS2IUBSZ256rmb:
26596 case VCVTTPS2IUBSZ256rmbk:
26597 case VCVTTPS2IUBSZ256rmbkz:
26598 case VCVTTPS2IUBSZ256rmk:
26599 case VCVTTPS2IUBSZ256rmkz:
26600 case VCVTTPS2IUBSZ256rr:
26601 case VCVTTPS2IUBSZ256rrk:
26602 case VCVTTPS2IUBSZ256rrkz:
26603 case VCVTTPS2IUBSZrm:
26604 case VCVTTPS2IUBSZrmb:
26605 case VCVTTPS2IUBSZrmbk:
26606 case VCVTTPS2IUBSZrmbkz:
26607 case VCVTTPS2IUBSZrmk:
26608 case VCVTTPS2IUBSZrmkz:
26609 case VCVTTPS2IUBSZrr:
26610 case VCVTTPS2IUBSZrrb:
26611 case VCVTTPS2IUBSZrrbk:
26612 case VCVTTPS2IUBSZrrbkz:
26613 case VCVTTPS2IUBSZrrk:
26614 case VCVTTPS2IUBSZrrkz:
26615 return true;
26616 }
26617 return false;
26618}
26619
26620bool isPMOVSXDQ(unsigned Opcode) {
26621 switch (Opcode) {
26622 case PMOVSXDQrm:
26623 case PMOVSXDQrr:
26624 return true;
26625 }
26626 return false;
26627}
26628
26629bool isMWAIT(unsigned Opcode) {
26630 return Opcode == MWAITrr;
26631}
26632
26633bool isVPEXTRB(unsigned Opcode) {
26634 switch (Opcode) {
26635 case VPEXTRBZmri:
26636 case VPEXTRBZrri:
26637 case VPEXTRBmri:
26638 case VPEXTRBrri:
26639 return true;
26640 }
26641 return false;
26642}
26643
26644bool isINVVPID(unsigned Opcode) {
26645 switch (Opcode) {
26646 case INVVPID32:
26647 case INVVPID64:
26648 case INVVPID64_EVEX:
26649 return true;
26650 }
26651 return false;
26652}
26653
26654bool isVPSHUFD(unsigned Opcode) {
26655 switch (Opcode) {
26656 case VPSHUFDYmi:
26657 case VPSHUFDYri:
26658 case VPSHUFDZ128mbi:
26659 case VPSHUFDZ128mbik:
26660 case VPSHUFDZ128mbikz:
26661 case VPSHUFDZ128mi:
26662 case VPSHUFDZ128mik:
26663 case VPSHUFDZ128mikz:
26664 case VPSHUFDZ128ri:
26665 case VPSHUFDZ128rik:
26666 case VPSHUFDZ128rikz:
26667 case VPSHUFDZ256mbi:
26668 case VPSHUFDZ256mbik:
26669 case VPSHUFDZ256mbikz:
26670 case VPSHUFDZ256mi:
26671 case VPSHUFDZ256mik:
26672 case VPSHUFDZ256mikz:
26673 case VPSHUFDZ256ri:
26674 case VPSHUFDZ256rik:
26675 case VPSHUFDZ256rikz:
26676 case VPSHUFDZmbi:
26677 case VPSHUFDZmbik:
26678 case VPSHUFDZmbikz:
26679 case VPSHUFDZmi:
26680 case VPSHUFDZmik:
26681 case VPSHUFDZmikz:
26682 case VPSHUFDZri:
26683 case VPSHUFDZrik:
26684 case VPSHUFDZrikz:
26685 case VPSHUFDmi:
26686 case VPSHUFDri:
26687 return true;
26688 }
26689 return false;
26690}
26691
26692bool isVMINBF16(unsigned Opcode) {
26693 switch (Opcode) {
26694 case VMINBF16Z128rm:
26695 case VMINBF16Z128rmb:
26696 case VMINBF16Z128rmbk:
26697 case VMINBF16Z128rmbkz:
26698 case VMINBF16Z128rmk:
26699 case VMINBF16Z128rmkz:
26700 case VMINBF16Z128rr:
26701 case VMINBF16Z128rrk:
26702 case VMINBF16Z128rrkz:
26703 case VMINBF16Z256rm:
26704 case VMINBF16Z256rmb:
26705 case VMINBF16Z256rmbk:
26706 case VMINBF16Z256rmbkz:
26707 case VMINBF16Z256rmk:
26708 case VMINBF16Z256rmkz:
26709 case VMINBF16Z256rr:
26710 case VMINBF16Z256rrk:
26711 case VMINBF16Z256rrkz:
26712 case VMINBF16Zrm:
26713 case VMINBF16Zrmb:
26714 case VMINBF16Zrmbk:
26715 case VMINBF16Zrmbkz:
26716 case VMINBF16Zrmk:
26717 case VMINBF16Zrmkz:
26718 case VMINBF16Zrr:
26719 case VMINBF16Zrrk:
26720 case VMINBF16Zrrkz:
26721 return true;
26722 }
26723 return false;
26724}
26725
26726bool isMOVLPS(unsigned Opcode) {
26727 switch (Opcode) {
26728 case MOVLPSmr:
26729 case MOVLPSrm:
26730 return true;
26731 }
26732 return false;
26733}
26734
26735bool isVBLENDMPS(unsigned Opcode) {
26736 switch (Opcode) {
26737 case VBLENDMPSZ128rm:
26738 case VBLENDMPSZ128rmb:
26739 case VBLENDMPSZ128rmbk:
26740 case VBLENDMPSZ128rmbkz:
26741 case VBLENDMPSZ128rmk:
26742 case VBLENDMPSZ128rmkz:
26743 case VBLENDMPSZ128rr:
26744 case VBLENDMPSZ128rrk:
26745 case VBLENDMPSZ128rrkz:
26746 case VBLENDMPSZ256rm:
26747 case VBLENDMPSZ256rmb:
26748 case VBLENDMPSZ256rmbk:
26749 case VBLENDMPSZ256rmbkz:
26750 case VBLENDMPSZ256rmk:
26751 case VBLENDMPSZ256rmkz:
26752 case VBLENDMPSZ256rr:
26753 case VBLENDMPSZ256rrk:
26754 case VBLENDMPSZ256rrkz:
26755 case VBLENDMPSZrm:
26756 case VBLENDMPSZrmb:
26757 case VBLENDMPSZrmbk:
26758 case VBLENDMPSZrmbkz:
26759 case VBLENDMPSZrmk:
26760 case VBLENDMPSZrmkz:
26761 case VBLENDMPSZrr:
26762 case VBLENDMPSZrrk:
26763 case VBLENDMPSZrrkz:
26764 return true;
26765 }
26766 return false;
26767}
26768
26769bool isPMULLW(unsigned Opcode) {
26770 switch (Opcode) {
26771 case MMX_PMULLWrm:
26772 case MMX_PMULLWrr:
26773 case PMULLWrm:
26774 case PMULLWrr:
26775 return true;
26776 }
26777 return false;
26778}
26779
26780bool isVCVTSH2SI(unsigned Opcode) {
26781 switch (Opcode) {
26782 case VCVTSH2SI64Zrm_Int:
26783 case VCVTSH2SI64Zrr_Int:
26784 case VCVTSH2SI64Zrrb_Int:
26785 case VCVTSH2SIZrm_Int:
26786 case VCVTSH2SIZrr_Int:
26787 case VCVTSH2SIZrrb_Int:
26788 return true;
26789 }
26790 return false;
26791}
26792
26793bool isVPMOVSXWQ(unsigned Opcode) {
26794 switch (Opcode) {
26795 case VPMOVSXWQYrm:
26796 case VPMOVSXWQYrr:
26797 case VPMOVSXWQZ128rm:
26798 case VPMOVSXWQZ128rmk:
26799 case VPMOVSXWQZ128rmkz:
26800 case VPMOVSXWQZ128rr:
26801 case VPMOVSXWQZ128rrk:
26802 case VPMOVSXWQZ128rrkz:
26803 case VPMOVSXWQZ256rm:
26804 case VPMOVSXWQZ256rmk:
26805 case VPMOVSXWQZ256rmkz:
26806 case VPMOVSXWQZ256rr:
26807 case VPMOVSXWQZ256rrk:
26808 case VPMOVSXWQZ256rrkz:
26809 case VPMOVSXWQZrm:
26810 case VPMOVSXWQZrmk:
26811 case VPMOVSXWQZrmkz:
26812 case VPMOVSXWQZrr:
26813 case VPMOVSXWQZrrk:
26814 case VPMOVSXWQZrrkz:
26815 case VPMOVSXWQrm:
26816 case VPMOVSXWQrr:
26817 return true;
26818 }
26819 return false;
26820}
26821
26822bool isFNSTENV(unsigned Opcode) {
26823 return Opcode == FSTENVm;
26824}
26825
26826bool isVCVT2PH2BF8(unsigned Opcode) {
26827 switch (Opcode) {
26828 case VCVT2PH2BF8Z128rm:
26829 case VCVT2PH2BF8Z128rmb:
26830 case VCVT2PH2BF8Z128rmbk:
26831 case VCVT2PH2BF8Z128rmbkz:
26832 case VCVT2PH2BF8Z128rmk:
26833 case VCVT2PH2BF8Z128rmkz:
26834 case VCVT2PH2BF8Z128rr:
26835 case VCVT2PH2BF8Z128rrk:
26836 case VCVT2PH2BF8Z128rrkz:
26837 case VCVT2PH2BF8Z256rm:
26838 case VCVT2PH2BF8Z256rmb:
26839 case VCVT2PH2BF8Z256rmbk:
26840 case VCVT2PH2BF8Z256rmbkz:
26841 case VCVT2PH2BF8Z256rmk:
26842 case VCVT2PH2BF8Z256rmkz:
26843 case VCVT2PH2BF8Z256rr:
26844 case VCVT2PH2BF8Z256rrk:
26845 case VCVT2PH2BF8Z256rrkz:
26846 case VCVT2PH2BF8Zrm:
26847 case VCVT2PH2BF8Zrmb:
26848 case VCVT2PH2BF8Zrmbk:
26849 case VCVT2PH2BF8Zrmbkz:
26850 case VCVT2PH2BF8Zrmk:
26851 case VCVT2PH2BF8Zrmkz:
26852 case VCVT2PH2BF8Zrr:
26853 case VCVT2PH2BF8Zrrk:
26854 case VCVT2PH2BF8Zrrkz:
26855 return true;
26856 }
26857 return false;
26858}
26859
26860bool isVPERMI2PD(unsigned Opcode) {
26861 switch (Opcode) {
26862 case VPERMI2PDZ128rm:
26863 case VPERMI2PDZ128rmb:
26864 case VPERMI2PDZ128rmbk:
26865 case VPERMI2PDZ128rmbkz:
26866 case VPERMI2PDZ128rmk:
26867 case VPERMI2PDZ128rmkz:
26868 case VPERMI2PDZ128rr:
26869 case VPERMI2PDZ128rrk:
26870 case VPERMI2PDZ128rrkz:
26871 case VPERMI2PDZ256rm:
26872 case VPERMI2PDZ256rmb:
26873 case VPERMI2PDZ256rmbk:
26874 case VPERMI2PDZ256rmbkz:
26875 case VPERMI2PDZ256rmk:
26876 case VPERMI2PDZ256rmkz:
26877 case VPERMI2PDZ256rr:
26878 case VPERMI2PDZ256rrk:
26879 case VPERMI2PDZ256rrkz:
26880 case VPERMI2PDZrm:
26881 case VPERMI2PDZrmb:
26882 case VPERMI2PDZrmbk:
26883 case VPERMI2PDZrmbkz:
26884 case VPERMI2PDZrmk:
26885 case VPERMI2PDZrmkz:
26886 case VPERMI2PDZrr:
26887 case VPERMI2PDZrrk:
26888 case VPERMI2PDZrrkz:
26889 return true;
26890 }
26891 return false;
26892}
26893
26894bool isMAXSS(unsigned Opcode) {
26895 switch (Opcode) {
26896 case MAXSSrm_Int:
26897 case MAXSSrr_Int:
26898 return true;
26899 }
26900 return false;
26901}
26902
26903bool isCWDE(unsigned Opcode) {
26904 return Opcode == CWDE;
26905}
26906
26907bool isVBROADCASTI32X8(unsigned Opcode) {
26908 switch (Opcode) {
26909 case VBROADCASTI32X8Zrm:
26910 case VBROADCASTI32X8Zrmk:
26911 case VBROADCASTI32X8Zrmkz:
26912 return true;
26913 }
26914 return false;
26915}
26916
26917bool isINT(unsigned Opcode) {
26918 return Opcode == INT;
26919}
26920
26921bool isENCLS(unsigned Opcode) {
26922 return Opcode == ENCLS;
26923}
26924
26925bool isMOVNTQ(unsigned Opcode) {
26926 return Opcode == MMX_MOVNTQmr;
26927}
26928
26929bool isVDIVSH(unsigned Opcode) {
26930 switch (Opcode) {
26931 case VDIVSHZrm_Int:
26932 case VDIVSHZrmk_Int:
26933 case VDIVSHZrmkz_Int:
26934 case VDIVSHZrr_Int:
26935 case VDIVSHZrrb_Int:
26936 case VDIVSHZrrbk_Int:
26937 case VDIVSHZrrbkz_Int:
26938 case VDIVSHZrrk_Int:
26939 case VDIVSHZrrkz_Int:
26940 return true;
26941 }
26942 return false;
26943}
26944
26945bool isMOVHLPS(unsigned Opcode) {
26946 return Opcode == MOVHLPSrr;
26947}
26948
26949bool isVPMASKMOVD(unsigned Opcode) {
26950 switch (Opcode) {
26951 case VPMASKMOVDYmr:
26952 case VPMASKMOVDYrm:
26953 case VPMASKMOVDmr:
26954 case VPMASKMOVDrm:
26955 return true;
26956 }
26957 return false;
26958}
26959
26960bool isVMOVSD(unsigned Opcode) {
26961 switch (Opcode) {
26962 case VMOVSDZmr:
26963 case VMOVSDZmrk:
26964 case VMOVSDZrm:
26965 case VMOVSDZrmk:
26966 case VMOVSDZrmkz:
26967 case VMOVSDZrr:
26968 case VMOVSDZrr_REV:
26969 case VMOVSDZrrk:
26970 case VMOVSDZrrk_REV:
26971 case VMOVSDZrrkz:
26972 case VMOVSDZrrkz_REV:
26973 case VMOVSDmr:
26974 case VMOVSDrm:
26975 case VMOVSDrr:
26976 case VMOVSDrr_REV:
26977 return true;
26978 }
26979 return false;
26980}
26981
26982bool isVPMINUD(unsigned Opcode) {
26983 switch (Opcode) {
26984 case VPMINUDYrm:
26985 case VPMINUDYrr:
26986 case VPMINUDZ128rm:
26987 case VPMINUDZ128rmb:
26988 case VPMINUDZ128rmbk:
26989 case VPMINUDZ128rmbkz:
26990 case VPMINUDZ128rmk:
26991 case VPMINUDZ128rmkz:
26992 case VPMINUDZ128rr:
26993 case VPMINUDZ128rrk:
26994 case VPMINUDZ128rrkz:
26995 case VPMINUDZ256rm:
26996 case VPMINUDZ256rmb:
26997 case VPMINUDZ256rmbk:
26998 case VPMINUDZ256rmbkz:
26999 case VPMINUDZ256rmk:
27000 case VPMINUDZ256rmkz:
27001 case VPMINUDZ256rr:
27002 case VPMINUDZ256rrk:
27003 case VPMINUDZ256rrkz:
27004 case VPMINUDZrm:
27005 case VPMINUDZrmb:
27006 case VPMINUDZrmbk:
27007 case VPMINUDZrmbkz:
27008 case VPMINUDZrmk:
27009 case VPMINUDZrmkz:
27010 case VPMINUDZrr:
27011 case VPMINUDZrrk:
27012 case VPMINUDZrrkz:
27013 case VPMINUDrm:
27014 case VPMINUDrr:
27015 return true;
27016 }
27017 return false;
27018}
27019
27020bool isVPCMPISTRM(unsigned Opcode) {
27021 switch (Opcode) {
27022 case VPCMPISTRMrmi:
27023 case VPCMPISTRMrri:
27024 return true;
27025 }
27026 return false;
27027}
27028
27029bool isVGETMANTSD(unsigned Opcode) {
27030 switch (Opcode) {
27031 case VGETMANTSDZrmi:
27032 case VGETMANTSDZrmik:
27033 case VGETMANTSDZrmikz:
27034 case VGETMANTSDZrri:
27035 case VGETMANTSDZrrib:
27036 case VGETMANTSDZrribk:
27037 case VGETMANTSDZrribkz:
27038 case VGETMANTSDZrrik:
27039 case VGETMANTSDZrrikz:
27040 return true;
27041 }
27042 return false;
27043}
27044
27045bool isKSHIFTRW(unsigned Opcode) {
27046 return Opcode == KSHIFTRWki;
27047}
27048
27049bool isAESDECLAST(unsigned Opcode) {
27050 switch (Opcode) {
27051 case AESDECLASTrm:
27052 case AESDECLASTrr:
27053 return true;
27054 }
27055 return false;
27056}
27057
27058bool isVFNMSUB231BF16(unsigned Opcode) {
27059 switch (Opcode) {
27060 case VFNMSUB231BF16Z128m:
27061 case VFNMSUB231BF16Z128mb:
27062 case VFNMSUB231BF16Z128mbk:
27063 case VFNMSUB231BF16Z128mbkz:
27064 case VFNMSUB231BF16Z128mk:
27065 case VFNMSUB231BF16Z128mkz:
27066 case VFNMSUB231BF16Z128r:
27067 case VFNMSUB231BF16Z128rk:
27068 case VFNMSUB231BF16Z128rkz:
27069 case VFNMSUB231BF16Z256m:
27070 case VFNMSUB231BF16Z256mb:
27071 case VFNMSUB231BF16Z256mbk:
27072 case VFNMSUB231BF16Z256mbkz:
27073 case VFNMSUB231BF16Z256mk:
27074 case VFNMSUB231BF16Z256mkz:
27075 case VFNMSUB231BF16Z256r:
27076 case VFNMSUB231BF16Z256rk:
27077 case VFNMSUB231BF16Z256rkz:
27078 case VFNMSUB231BF16Zm:
27079 case VFNMSUB231BF16Zmb:
27080 case VFNMSUB231BF16Zmbk:
27081 case VFNMSUB231BF16Zmbkz:
27082 case VFNMSUB231BF16Zmk:
27083 case VFNMSUB231BF16Zmkz:
27084 case VFNMSUB231BF16Zr:
27085 case VFNMSUB231BF16Zrk:
27086 case VFNMSUB231BF16Zrkz:
27087 return true;
27088 }
27089 return false;
27090}
27091
27092bool isVMPTRST(unsigned Opcode) {
27093 return Opcode == VMPTRSTm;
27094}
27095
27096bool isLLDT(unsigned Opcode) {
27097 switch (Opcode) {
27098 case LLDT16m:
27099 case LLDT16r:
27100 return true;
27101 }
27102 return false;
27103}
27104
27105bool isVPTESTMB(unsigned Opcode) {
27106 switch (Opcode) {
27107 case VPTESTMBZ128rm:
27108 case VPTESTMBZ128rmk:
27109 case VPTESTMBZ128rr:
27110 case VPTESTMBZ128rrk:
27111 case VPTESTMBZ256rm:
27112 case VPTESTMBZ256rmk:
27113 case VPTESTMBZ256rr:
27114 case VPTESTMBZ256rrk:
27115 case VPTESTMBZrm:
27116 case VPTESTMBZrmk:
27117 case VPTESTMBZrr:
27118 case VPTESTMBZrrk:
27119 return true;
27120 }
27121 return false;
27122}
27123
27124bool isMOVSB(unsigned Opcode) {
27125 return Opcode == MOVSB;
27126}
27127
27128bool isTILELOADD(unsigned Opcode) {
27129 switch (Opcode) {
27130 case TILELOADD:
27131 case TILELOADD_EVEX:
27132 return true;
27133 }
27134 return false;
27135}
27136
27137bool isKTESTB(unsigned Opcode) {
27138 return Opcode == KTESTBkk;
27139}
27140
27141bool isMOVUPD(unsigned Opcode) {
27142 switch (Opcode) {
27143 case MOVUPDmr:
27144 case MOVUPDrm:
27145 case MOVUPDrr:
27146 case MOVUPDrr_REV:
27147 return true;
27148 }
27149 return false;
27150}
27151
27152bool isLKGS(unsigned Opcode) {
27153 switch (Opcode) {
27154 case LKGS16m:
27155 case LKGS16r:
27156 return true;
27157 }
27158 return false;
27159}
27160
27161bool isSGDTW(unsigned Opcode) {
27162 return Opcode == SGDT16m;
27163}
27164
27165bool isDIVSS(unsigned Opcode) {
27166 switch (Opcode) {
27167 case DIVSSrm_Int:
27168 case DIVSSrr_Int:
27169 return true;
27170 }
27171 return false;
27172}
27173
27174bool isPUNPCKHQDQ(unsigned Opcode) {
27175 switch (Opcode) {
27176 case PUNPCKHQDQrm:
27177 case PUNPCKHQDQrr:
27178 return true;
27179 }
27180 return false;
27181}
27182
27183bool isVFMADD213SD(unsigned Opcode) {
27184 switch (Opcode) {
27185 case VFMADD213SDZm_Int:
27186 case VFMADD213SDZmk_Int:
27187 case VFMADD213SDZmkz_Int:
27188 case VFMADD213SDZr_Int:
27189 case VFMADD213SDZrb_Int:
27190 case VFMADD213SDZrbk_Int:
27191 case VFMADD213SDZrbkz_Int:
27192 case VFMADD213SDZrk_Int:
27193 case VFMADD213SDZrkz_Int:
27194 case VFMADD213SDm_Int:
27195 case VFMADD213SDr_Int:
27196 return true;
27197 }
27198 return false;
27199}
27200
27201bool isKXORD(unsigned Opcode) {
27202 return Opcode == KXORDkk;
27203}
27204
27205bool isVPMOVB2M(unsigned Opcode) {
27206 switch (Opcode) {
27207 case VPMOVB2MZ128kr:
27208 case VPMOVB2MZ256kr:
27209 case VPMOVB2MZkr:
27210 return true;
27211 }
27212 return false;
27213}
27214
27215bool isVMREAD(unsigned Opcode) {
27216 switch (Opcode) {
27217 case VMREAD32mr:
27218 case VMREAD32rr:
27219 case VMREAD64mr:
27220 case VMREAD64rr:
27221 return true;
27222 }
27223 return false;
27224}
27225
27226bool isVPDPWSSDS(unsigned Opcode) {
27227 switch (Opcode) {
27228 case VPDPWSSDSYrm:
27229 case VPDPWSSDSYrr:
27230 case VPDPWSSDSZ128rm:
27231 case VPDPWSSDSZ128rmb:
27232 case VPDPWSSDSZ128rmbk:
27233 case VPDPWSSDSZ128rmbkz:
27234 case VPDPWSSDSZ128rmk:
27235 case VPDPWSSDSZ128rmkz:
27236 case VPDPWSSDSZ128rr:
27237 case VPDPWSSDSZ128rrk:
27238 case VPDPWSSDSZ128rrkz:
27239 case VPDPWSSDSZ256rm:
27240 case VPDPWSSDSZ256rmb:
27241 case VPDPWSSDSZ256rmbk:
27242 case VPDPWSSDSZ256rmbkz:
27243 case VPDPWSSDSZ256rmk:
27244 case VPDPWSSDSZ256rmkz:
27245 case VPDPWSSDSZ256rr:
27246 case VPDPWSSDSZ256rrk:
27247 case VPDPWSSDSZ256rrkz:
27248 case VPDPWSSDSZrm:
27249 case VPDPWSSDSZrmb:
27250 case VPDPWSSDSZrmbk:
27251 case VPDPWSSDSZrmbkz:
27252 case VPDPWSSDSZrmk:
27253 case VPDPWSSDSZrmkz:
27254 case VPDPWSSDSZrr:
27255 case VPDPWSSDSZrrk:
27256 case VPDPWSSDSZrrkz:
27257 case VPDPWSSDSrm:
27258 case VPDPWSSDSrr:
27259 return true;
27260 }
27261 return false;
27262}
27263
27264bool isTILERELEASE(unsigned Opcode) {
27265 return Opcode == TILERELEASE;
27266}
27267
27268bool isVUCOMXSH(unsigned Opcode) {
27269 switch (Opcode) {
27270 case VUCOMXSHZrm_Int:
27271 case VUCOMXSHZrr_Int:
27272 case VUCOMXSHZrrb_Int:
27273 return true;
27274 }
27275 return false;
27276}
27277
27278bool isCLFLUSHOPT(unsigned Opcode) {
27279 return Opcode == CLFLUSHOPT;
27280}
27281
27282bool isDAS(unsigned Opcode) {
27283 return Opcode == DAS;
27284}
27285
27286bool isVSCALEFPH(unsigned Opcode) {
27287 switch (Opcode) {
27288 case VSCALEFPHZ128rm:
27289 case VSCALEFPHZ128rmb:
27290 case VSCALEFPHZ128rmbk:
27291 case VSCALEFPHZ128rmbkz:
27292 case VSCALEFPHZ128rmk:
27293 case VSCALEFPHZ128rmkz:
27294 case VSCALEFPHZ128rr:
27295 case VSCALEFPHZ128rrk:
27296 case VSCALEFPHZ128rrkz:
27297 case VSCALEFPHZ256rm:
27298 case VSCALEFPHZ256rmb:
27299 case VSCALEFPHZ256rmbk:
27300 case VSCALEFPHZ256rmbkz:
27301 case VSCALEFPHZ256rmk:
27302 case VSCALEFPHZ256rmkz:
27303 case VSCALEFPHZ256rr:
27304 case VSCALEFPHZ256rrk:
27305 case VSCALEFPHZ256rrkz:
27306 case VSCALEFPHZrm:
27307 case VSCALEFPHZrmb:
27308 case VSCALEFPHZrmbk:
27309 case VSCALEFPHZrmbkz:
27310 case VSCALEFPHZrmk:
27311 case VSCALEFPHZrmkz:
27312 case VSCALEFPHZrr:
27313 case VSCALEFPHZrrb:
27314 case VSCALEFPHZrrbk:
27315 case VSCALEFPHZrrbkz:
27316 case VSCALEFPHZrrk:
27317 case VSCALEFPHZrrkz:
27318 return true;
27319 }
27320 return false;
27321}
27322
27323bool isVSUBSD(unsigned Opcode) {
27324 switch (Opcode) {
27325 case VSUBSDZrm_Int:
27326 case VSUBSDZrmk_Int:
27327 case VSUBSDZrmkz_Int:
27328 case VSUBSDZrr_Int:
27329 case VSUBSDZrrb_Int:
27330 case VSUBSDZrrbk_Int:
27331 case VSUBSDZrrbkz_Int:
27332 case VSUBSDZrrk_Int:
27333 case VSUBSDZrrkz_Int:
27334 case VSUBSDrm_Int:
27335 case VSUBSDrr_Int:
27336 return true;
27337 }
27338 return false;
27339}
27340
27341bool isVCOMISS(unsigned Opcode) {
27342 switch (Opcode) {
27343 case VCOMISSZrm:
27344 case VCOMISSZrr:
27345 case VCOMISSZrrb:
27346 case VCOMISSrm:
27347 case VCOMISSrr:
27348 return true;
27349 }
27350 return false;
27351}
27352
27353bool isVMULBF16(unsigned Opcode) {
27354 switch (Opcode) {
27355 case VMULBF16Z128rm:
27356 case VMULBF16Z128rmb:
27357 case VMULBF16Z128rmbk:
27358 case VMULBF16Z128rmbkz:
27359 case VMULBF16Z128rmk:
27360 case VMULBF16Z128rmkz:
27361 case VMULBF16Z128rr:
27362 case VMULBF16Z128rrk:
27363 case VMULBF16Z128rrkz:
27364 case VMULBF16Z256rm:
27365 case VMULBF16Z256rmb:
27366 case VMULBF16Z256rmbk:
27367 case VMULBF16Z256rmbkz:
27368 case VMULBF16Z256rmk:
27369 case VMULBF16Z256rmkz:
27370 case VMULBF16Z256rr:
27371 case VMULBF16Z256rrk:
27372 case VMULBF16Z256rrkz:
27373 case VMULBF16Zrm:
27374 case VMULBF16Zrmb:
27375 case VMULBF16Zrmbk:
27376 case VMULBF16Zrmbkz:
27377 case VMULBF16Zrmk:
27378 case VMULBF16Zrmkz:
27379 case VMULBF16Zrr:
27380 case VMULBF16Zrrk:
27381 case VMULBF16Zrrkz:
27382 return true;
27383 }
27384 return false;
27385}
27386
27387bool isORPS(unsigned Opcode) {
27388 switch (Opcode) {
27389 case ORPSrm:
27390 case ORPSrr:
27391 return true;
27392 }
27393 return false;
27394}
27395
27396bool isTDPFP16PS(unsigned Opcode) {
27397 return Opcode == TDPFP16PS;
27398}
27399
27400bool isVMAXPD(unsigned Opcode) {
27401 switch (Opcode) {
27402 case VMAXPDYrm:
27403 case VMAXPDYrr:
27404 case VMAXPDZ128rm:
27405 case VMAXPDZ128rmb:
27406 case VMAXPDZ128rmbk:
27407 case VMAXPDZ128rmbkz:
27408 case VMAXPDZ128rmk:
27409 case VMAXPDZ128rmkz:
27410 case VMAXPDZ128rr:
27411 case VMAXPDZ128rrk:
27412 case VMAXPDZ128rrkz:
27413 case VMAXPDZ256rm:
27414 case VMAXPDZ256rmb:
27415 case VMAXPDZ256rmbk:
27416 case VMAXPDZ256rmbkz:
27417 case VMAXPDZ256rmk:
27418 case VMAXPDZ256rmkz:
27419 case VMAXPDZ256rr:
27420 case VMAXPDZ256rrk:
27421 case VMAXPDZ256rrkz:
27422 case VMAXPDZrm:
27423 case VMAXPDZrmb:
27424 case VMAXPDZrmbk:
27425 case VMAXPDZrmbkz:
27426 case VMAXPDZrmk:
27427 case VMAXPDZrmkz:
27428 case VMAXPDZrr:
27429 case VMAXPDZrrb:
27430 case VMAXPDZrrbk:
27431 case VMAXPDZrrbkz:
27432 case VMAXPDZrrk:
27433 case VMAXPDZrrkz:
27434 case VMAXPDrm:
27435 case VMAXPDrr:
27436 return true;
27437 }
27438 return false;
27439}
27440
27441bool isVPMOVWB(unsigned Opcode) {
27442 switch (Opcode) {
27443 case VPMOVWBZ128mr:
27444 case VPMOVWBZ128mrk:
27445 case VPMOVWBZ128rr:
27446 case VPMOVWBZ128rrk:
27447 case VPMOVWBZ128rrkz:
27448 case VPMOVWBZ256mr:
27449 case VPMOVWBZ256mrk:
27450 case VPMOVWBZ256rr:
27451 case VPMOVWBZ256rrk:
27452 case VPMOVWBZ256rrkz:
27453 case VPMOVWBZmr:
27454 case VPMOVWBZmrk:
27455 case VPMOVWBZrr:
27456 case VPMOVWBZrrk:
27457 case VPMOVWBZrrkz:
27458 return true;
27459 }
27460 return false;
27461}
27462
27463bool isVEXP2PS(unsigned Opcode) {
27464 switch (Opcode) {
27465 case VEXP2PSZm:
27466 case VEXP2PSZmb:
27467 case VEXP2PSZmbk:
27468 case VEXP2PSZmbkz:
27469 case VEXP2PSZmk:
27470 case VEXP2PSZmkz:
27471 case VEXP2PSZr:
27472 case VEXP2PSZrb:
27473 case VEXP2PSZrbk:
27474 case VEXP2PSZrbkz:
27475 case VEXP2PSZrk:
27476 case VEXP2PSZrkz:
27477 return true;
27478 }
27479 return false;
27480}
27481
27482bool isVPGATHERDQ(unsigned Opcode) {
27483 switch (Opcode) {
27484 case VPGATHERDQYrm:
27485 case VPGATHERDQZ128rm:
27486 case VPGATHERDQZ256rm:
27487 case VPGATHERDQZrm:
27488 case VPGATHERDQrm:
27489 return true;
27490 }
27491 return false;
27492}
27493
27494bool isVPSRAVQ(unsigned Opcode) {
27495 switch (Opcode) {
27496 case VPSRAVQZ128rm:
27497 case VPSRAVQZ128rmb:
27498 case VPSRAVQZ128rmbk:
27499 case VPSRAVQZ128rmbkz:
27500 case VPSRAVQZ128rmk:
27501 case VPSRAVQZ128rmkz:
27502 case VPSRAVQZ128rr:
27503 case VPSRAVQZ128rrk:
27504 case VPSRAVQZ128rrkz:
27505 case VPSRAVQZ256rm:
27506 case VPSRAVQZ256rmb:
27507 case VPSRAVQZ256rmbk:
27508 case VPSRAVQZ256rmbkz:
27509 case VPSRAVQZ256rmk:
27510 case VPSRAVQZ256rmkz:
27511 case VPSRAVQZ256rr:
27512 case VPSRAVQZ256rrk:
27513 case VPSRAVQZ256rrkz:
27514 case VPSRAVQZrm:
27515 case VPSRAVQZrmb:
27516 case VPSRAVQZrmbk:
27517 case VPSRAVQZrmbkz:
27518 case VPSRAVQZrmk:
27519 case VPSRAVQZrmkz:
27520 case VPSRAVQZrr:
27521 case VPSRAVQZrrk:
27522 case VPSRAVQZrrkz:
27523 return true;
27524 }
27525 return false;
27526}
27527
27528bool isPCMPISTRI(unsigned Opcode) {
27529 switch (Opcode) {
27530 case PCMPISTRIrmi:
27531 case PCMPISTRIrri:
27532 return true;
27533 }
27534 return false;
27535}
27536
27537bool isVFMSUB231PD(unsigned Opcode) {
27538 switch (Opcode) {
27539 case VFMSUB231PDYm:
27540 case VFMSUB231PDYr:
27541 case VFMSUB231PDZ128m:
27542 case VFMSUB231PDZ128mb:
27543 case VFMSUB231PDZ128mbk:
27544 case VFMSUB231PDZ128mbkz:
27545 case VFMSUB231PDZ128mk:
27546 case VFMSUB231PDZ128mkz:
27547 case VFMSUB231PDZ128r:
27548 case VFMSUB231PDZ128rk:
27549 case VFMSUB231PDZ128rkz:
27550 case VFMSUB231PDZ256m:
27551 case VFMSUB231PDZ256mb:
27552 case VFMSUB231PDZ256mbk:
27553 case VFMSUB231PDZ256mbkz:
27554 case VFMSUB231PDZ256mk:
27555 case VFMSUB231PDZ256mkz:
27556 case VFMSUB231PDZ256r:
27557 case VFMSUB231PDZ256rk:
27558 case VFMSUB231PDZ256rkz:
27559 case VFMSUB231PDZm:
27560 case VFMSUB231PDZmb:
27561 case VFMSUB231PDZmbk:
27562 case VFMSUB231PDZmbkz:
27563 case VFMSUB231PDZmk:
27564 case VFMSUB231PDZmkz:
27565 case VFMSUB231PDZr:
27566 case VFMSUB231PDZrb:
27567 case VFMSUB231PDZrbk:
27568 case VFMSUB231PDZrbkz:
27569 case VFMSUB231PDZrk:
27570 case VFMSUB231PDZrkz:
27571 case VFMSUB231PDm:
27572 case VFMSUB231PDr:
27573 return true;
27574 }
27575 return false;
27576}
27577
27578bool isRDMSR(unsigned Opcode) {
27579 switch (Opcode) {
27580 case RDMSR:
27581 case RDMSRri:
27582 case RDMSRri_EVEX:
27583 return true;
27584 }
27585 return false;
27586}
27587
27588bool isKORTESTD(unsigned Opcode) {
27589 return Opcode == KORTESTDkk;
27590}
27591
27592bool isVPBLENDMW(unsigned Opcode) {
27593 switch (Opcode) {
27594 case VPBLENDMWZ128rm:
27595 case VPBLENDMWZ128rmk:
27596 case VPBLENDMWZ128rmkz:
27597 case VPBLENDMWZ128rr:
27598 case VPBLENDMWZ128rrk:
27599 case VPBLENDMWZ128rrkz:
27600 case VPBLENDMWZ256rm:
27601 case VPBLENDMWZ256rmk:
27602 case VPBLENDMWZ256rmkz:
27603 case VPBLENDMWZ256rr:
27604 case VPBLENDMWZ256rrk:
27605 case VPBLENDMWZ256rrkz:
27606 case VPBLENDMWZrm:
27607 case VPBLENDMWZrmk:
27608 case VPBLENDMWZrmkz:
27609 case VPBLENDMWZrr:
27610 case VPBLENDMWZrrk:
27611 case VPBLENDMWZrrkz:
27612 return true;
27613 }
27614 return false;
27615}
27616
27617bool isPSHUFB(unsigned Opcode) {
27618 switch (Opcode) {
27619 case MMX_PSHUFBrm:
27620 case MMX_PSHUFBrr:
27621 case PSHUFBrm:
27622 case PSHUFBrr:
27623 return true;
27624 }
27625 return false;
27626}
27627
27628bool isVDPBF16PS(unsigned Opcode) {
27629 switch (Opcode) {
27630 case VDPBF16PSZ128m:
27631 case VDPBF16PSZ128mb:
27632 case VDPBF16PSZ128mbk:
27633 case VDPBF16PSZ128mbkz:
27634 case VDPBF16PSZ128mk:
27635 case VDPBF16PSZ128mkz:
27636 case VDPBF16PSZ128r:
27637 case VDPBF16PSZ128rk:
27638 case VDPBF16PSZ128rkz:
27639 case VDPBF16PSZ256m:
27640 case VDPBF16PSZ256mb:
27641 case VDPBF16PSZ256mbk:
27642 case VDPBF16PSZ256mbkz:
27643 case VDPBF16PSZ256mk:
27644 case VDPBF16PSZ256mkz:
27645 case VDPBF16PSZ256r:
27646 case VDPBF16PSZ256rk:
27647 case VDPBF16PSZ256rkz:
27648 case VDPBF16PSZm:
27649 case VDPBF16PSZmb:
27650 case VDPBF16PSZmbk:
27651 case VDPBF16PSZmbkz:
27652 case VDPBF16PSZmk:
27653 case VDPBF16PSZmkz:
27654 case VDPBF16PSZr:
27655 case VDPBF16PSZrk:
27656 case VDPBF16PSZrkz:
27657 return true;
27658 }
27659 return false;
27660}
27661
27662bool isTDPBF16PS(unsigned Opcode) {
27663 return Opcode == TDPBF16PS;
27664}
27665
27666bool isFCMOVE(unsigned Opcode) {
27667 return Opcode == CMOVE_F;
27668}
27669
27670bool isVFMADD231BF16(unsigned Opcode) {
27671 switch (Opcode) {
27672 case VFMADD231BF16Z128m:
27673 case VFMADD231BF16Z128mb:
27674 case VFMADD231BF16Z128mbk:
27675 case VFMADD231BF16Z128mbkz:
27676 case VFMADD231BF16Z128mk:
27677 case VFMADD231BF16Z128mkz:
27678 case VFMADD231BF16Z128r:
27679 case VFMADD231BF16Z128rk:
27680 case VFMADD231BF16Z128rkz:
27681 case VFMADD231BF16Z256m:
27682 case VFMADD231BF16Z256mb:
27683 case VFMADD231BF16Z256mbk:
27684 case VFMADD231BF16Z256mbkz:
27685 case VFMADD231BF16Z256mk:
27686 case VFMADD231BF16Z256mkz:
27687 case VFMADD231BF16Z256r:
27688 case VFMADD231BF16Z256rk:
27689 case VFMADD231BF16Z256rkz:
27690 case VFMADD231BF16Zm:
27691 case VFMADD231BF16Zmb:
27692 case VFMADD231BF16Zmbk:
27693 case VFMADD231BF16Zmbkz:
27694 case VFMADD231BF16Zmk:
27695 case VFMADD231BF16Zmkz:
27696 case VFMADD231BF16Zr:
27697 case VFMADD231BF16Zrk:
27698 case VFMADD231BF16Zrkz:
27699 return true;
27700 }
27701 return false;
27702}
27703
27704bool isCMPSS(unsigned Opcode) {
27705 switch (Opcode) {
27706 case CMPSSrmi_Int:
27707 case CMPSSrri_Int:
27708 return true;
27709 }
27710 return false;
27711}
27712
27713bool isMASKMOVDQU(unsigned Opcode) {
27714 switch (Opcode) {
27715 case MASKMOVDQU:
27716 case MASKMOVDQU64:
27717 return true;
27718 }
27719 return false;
27720}
27721
27722bool isVPDPWUSDS(unsigned Opcode) {
27723 switch (Opcode) {
27724 case VPDPWUSDSYrm:
27725 case VPDPWUSDSYrr:
27726 case VPDPWUSDSZ128rm:
27727 case VPDPWUSDSZ128rmb:
27728 case VPDPWUSDSZ128rmbk:
27729 case VPDPWUSDSZ128rmbkz:
27730 case VPDPWUSDSZ128rmk:
27731 case VPDPWUSDSZ128rmkz:
27732 case VPDPWUSDSZ128rr:
27733 case VPDPWUSDSZ128rrk:
27734 case VPDPWUSDSZ128rrkz:
27735 case VPDPWUSDSZ256rm:
27736 case VPDPWUSDSZ256rmb:
27737 case VPDPWUSDSZ256rmbk:
27738 case VPDPWUSDSZ256rmbkz:
27739 case VPDPWUSDSZ256rmk:
27740 case VPDPWUSDSZ256rmkz:
27741 case VPDPWUSDSZ256rr:
27742 case VPDPWUSDSZ256rrk:
27743 case VPDPWUSDSZ256rrkz:
27744 case VPDPWUSDSZrm:
27745 case VPDPWUSDSZrmb:
27746 case VPDPWUSDSZrmbk:
27747 case VPDPWUSDSZrmbkz:
27748 case VPDPWUSDSZrmk:
27749 case VPDPWUSDSZrmkz:
27750 case VPDPWUSDSZrr:
27751 case VPDPWUSDSZrrk:
27752 case VPDPWUSDSZrrkz:
27753 case VPDPWUSDSrm:
27754 case VPDPWUSDSrr:
27755 return true;
27756 }
27757 return false;
27758}
27759
27760bool isSARX(unsigned Opcode) {
27761 switch (Opcode) {
27762 case SARX32rm:
27763 case SARX32rm_EVEX:
27764 case SARX32rr:
27765 case SARX32rr_EVEX:
27766 case SARX64rm:
27767 case SARX64rm_EVEX:
27768 case SARX64rr:
27769 case SARX64rr_EVEX:
27770 return true;
27771 }
27772 return false;
27773}
27774
27775bool isSGDT(unsigned Opcode) {
27776 return Opcode == SGDT64m;
27777}
27778
27779bool isVFMULCPH(unsigned Opcode) {
27780 switch (Opcode) {
27781 case VFMULCPHZ128rm:
27782 case VFMULCPHZ128rmb:
27783 case VFMULCPHZ128rmbk:
27784 case VFMULCPHZ128rmbkz:
27785 case VFMULCPHZ128rmk:
27786 case VFMULCPHZ128rmkz:
27787 case VFMULCPHZ128rr:
27788 case VFMULCPHZ128rrk:
27789 case VFMULCPHZ128rrkz:
27790 case VFMULCPHZ256rm:
27791 case VFMULCPHZ256rmb:
27792 case VFMULCPHZ256rmbk:
27793 case VFMULCPHZ256rmbkz:
27794 case VFMULCPHZ256rmk:
27795 case VFMULCPHZ256rmkz:
27796 case VFMULCPHZ256rr:
27797 case VFMULCPHZ256rrk:
27798 case VFMULCPHZ256rrkz:
27799 case VFMULCPHZrm:
27800 case VFMULCPHZrmb:
27801 case VFMULCPHZrmbk:
27802 case VFMULCPHZrmbkz:
27803 case VFMULCPHZrmk:
27804 case VFMULCPHZrmkz:
27805 case VFMULCPHZrr:
27806 case VFMULCPHZrrb:
27807 case VFMULCPHZrrbk:
27808 case VFMULCPHZrrbkz:
27809 case VFMULCPHZrrk:
27810 case VFMULCPHZrrkz:
27811 return true;
27812 }
27813 return false;
27814}
27815
27816bool isURDMSR(unsigned Opcode) {
27817 switch (Opcode) {
27818 case URDMSRri:
27819 case URDMSRri_EVEX:
27820 case URDMSRrr:
27821 case URDMSRrr_EVEX:
27822 return true;
27823 }
27824 return false;
27825}
27826
27827bool isKUNPCKWD(unsigned Opcode) {
27828 return Opcode == KUNPCKWDkk;
27829}
27830
27831bool isVSCALEFBF16(unsigned Opcode) {
27832 switch (Opcode) {
27833 case VSCALEFBF16Z128rm:
27834 case VSCALEFBF16Z128rmb:
27835 case VSCALEFBF16Z128rmbk:
27836 case VSCALEFBF16Z128rmbkz:
27837 case VSCALEFBF16Z128rmk:
27838 case VSCALEFBF16Z128rmkz:
27839 case VSCALEFBF16Z128rr:
27840 case VSCALEFBF16Z128rrk:
27841 case VSCALEFBF16Z128rrkz:
27842 case VSCALEFBF16Z256rm:
27843 case VSCALEFBF16Z256rmb:
27844 case VSCALEFBF16Z256rmbk:
27845 case VSCALEFBF16Z256rmbkz:
27846 case VSCALEFBF16Z256rmk:
27847 case VSCALEFBF16Z256rmkz:
27848 case VSCALEFBF16Z256rr:
27849 case VSCALEFBF16Z256rrk:
27850 case VSCALEFBF16Z256rrkz:
27851 case VSCALEFBF16Zrm:
27852 case VSCALEFBF16Zrmb:
27853 case VSCALEFBF16Zrmbk:
27854 case VSCALEFBF16Zrmbkz:
27855 case VSCALEFBF16Zrmk:
27856 case VSCALEFBF16Zrmkz:
27857 case VSCALEFBF16Zrr:
27858 case VSCALEFBF16Zrrk:
27859 case VSCALEFBF16Zrrkz:
27860 return true;
27861 }
27862 return false;
27863}
27864
27865bool isCVTPS2PD(unsigned Opcode) {
27866 switch (Opcode) {
27867 case CVTPS2PDrm:
27868 case CVTPS2PDrr:
27869 return true;
27870 }
27871 return false;
27872}
27873
27874bool isFBSTP(unsigned Opcode) {
27875 return Opcode == FBSTPm;
27876}
27877
27878bool isPSUBQ(unsigned Opcode) {
27879 switch (Opcode) {
27880 case MMX_PSUBQrm:
27881 case MMX_PSUBQrr:
27882 case PSUBQrm:
27883 case PSUBQrr:
27884 return true;
27885 }
27886 return false;
27887}
27888
27889bool isFXSAVE64(unsigned Opcode) {
27890 return Opcode == FXSAVE64;
27891}
27892
27893bool isKMOVW(unsigned Opcode) {
27894 switch (Opcode) {
27895 case KMOVWkk:
27896 case KMOVWkk_EVEX:
27897 case KMOVWkm:
27898 case KMOVWkm_EVEX:
27899 case KMOVWkr:
27900 case KMOVWkr_EVEX:
27901 case KMOVWmk:
27902 case KMOVWmk_EVEX:
27903 case KMOVWrk:
27904 case KMOVWrk_EVEX:
27905 return true;
27906 }
27907 return false;
27908}
27909
27910bool isBTS(unsigned Opcode) {
27911 switch (Opcode) {
27912 case BTS16mi8:
27913 case BTS16mr:
27914 case BTS16ri8:
27915 case BTS16rr:
27916 case BTS32mi8:
27917 case BTS32mr:
27918 case BTS32ri8:
27919 case BTS32rr:
27920 case BTS64mi8:
27921 case BTS64mr:
27922 case BTS64ri8:
27923 case BTS64rr:
27924 return true;
27925 }
27926 return false;
27927}
27928
27929bool isVPHADDBQ(unsigned Opcode) {
27930 switch (Opcode) {
27931 case VPHADDBQrm:
27932 case VPHADDBQrr:
27933 return true;
27934 }
27935 return false;
27936}
27937
27938bool isFRSTOR(unsigned Opcode) {
27939 return Opcode == FRSTORm;
27940}
27941
27942bool isVFMSUB132PD(unsigned Opcode) {
27943 switch (Opcode) {
27944 case VFMSUB132PDYm:
27945 case VFMSUB132PDYr:
27946 case VFMSUB132PDZ128m:
27947 case VFMSUB132PDZ128mb:
27948 case VFMSUB132PDZ128mbk:
27949 case VFMSUB132PDZ128mbkz:
27950 case VFMSUB132PDZ128mk:
27951 case VFMSUB132PDZ128mkz:
27952 case VFMSUB132PDZ128r:
27953 case VFMSUB132PDZ128rk:
27954 case VFMSUB132PDZ128rkz:
27955 case VFMSUB132PDZ256m:
27956 case VFMSUB132PDZ256mb:
27957 case VFMSUB132PDZ256mbk:
27958 case VFMSUB132PDZ256mbkz:
27959 case VFMSUB132PDZ256mk:
27960 case VFMSUB132PDZ256mkz:
27961 case VFMSUB132PDZ256r:
27962 case VFMSUB132PDZ256rk:
27963 case VFMSUB132PDZ256rkz:
27964 case VFMSUB132PDZm:
27965 case VFMSUB132PDZmb:
27966 case VFMSUB132PDZmbk:
27967 case VFMSUB132PDZmbkz:
27968 case VFMSUB132PDZmk:
27969 case VFMSUB132PDZmkz:
27970 case VFMSUB132PDZr:
27971 case VFMSUB132PDZrb:
27972 case VFMSUB132PDZrbk:
27973 case VFMSUB132PDZrbkz:
27974 case VFMSUB132PDZrk:
27975 case VFMSUB132PDZrkz:
27976 case VFMSUB132PDm:
27977 case VFMSUB132PDr:
27978 return true;
27979 }
27980 return false;
27981}
27982
27983bool isPMULLD(unsigned Opcode) {
27984 switch (Opcode) {
27985 case PMULLDrm:
27986 case PMULLDrr:
27987 return true;
27988 }
27989 return false;
27990}
27991
27992bool isSHA1MSG2(unsigned Opcode) {
27993 switch (Opcode) {
27994 case SHA1MSG2rm:
27995 case SHA1MSG2rr:
27996 return true;
27997 }
27998 return false;
27999}
28000
28001bool isJECXZ(unsigned Opcode) {
28002 return Opcode == JECXZ;
28003}
28004
28005bool isVCVTUDQ2PS(unsigned Opcode) {
28006 switch (Opcode) {
28007 case VCVTUDQ2PSZ128rm:
28008 case VCVTUDQ2PSZ128rmb:
28009 case VCVTUDQ2PSZ128rmbk:
28010 case VCVTUDQ2PSZ128rmbkz:
28011 case VCVTUDQ2PSZ128rmk:
28012 case VCVTUDQ2PSZ128rmkz:
28013 case VCVTUDQ2PSZ128rr:
28014 case VCVTUDQ2PSZ128rrk:
28015 case VCVTUDQ2PSZ128rrkz:
28016 case VCVTUDQ2PSZ256rm:
28017 case VCVTUDQ2PSZ256rmb:
28018 case VCVTUDQ2PSZ256rmbk:
28019 case VCVTUDQ2PSZ256rmbkz:
28020 case VCVTUDQ2PSZ256rmk:
28021 case VCVTUDQ2PSZ256rmkz:
28022 case VCVTUDQ2PSZ256rr:
28023 case VCVTUDQ2PSZ256rrk:
28024 case VCVTUDQ2PSZ256rrkz:
28025 case VCVTUDQ2PSZrm:
28026 case VCVTUDQ2PSZrmb:
28027 case VCVTUDQ2PSZrmbk:
28028 case VCVTUDQ2PSZrmbkz:
28029 case VCVTUDQ2PSZrmk:
28030 case VCVTUDQ2PSZrmkz:
28031 case VCVTUDQ2PSZrr:
28032 case VCVTUDQ2PSZrrb:
28033 case VCVTUDQ2PSZrrbk:
28034 case VCVTUDQ2PSZrrbkz:
28035 case VCVTUDQ2PSZrrk:
28036 case VCVTUDQ2PSZrrkz:
28037 return true;
28038 }
28039 return false;
28040}
28041
28042bool isAESENC(unsigned Opcode) {
28043 switch (Opcode) {
28044 case AESENCrm:
28045 case AESENCrr:
28046 return true;
28047 }
28048 return false;
28049}
28050
28051bool isVMINMAXPS(unsigned Opcode) {
28052 switch (Opcode) {
28053 case VMINMAXPSZ128rmbi:
28054 case VMINMAXPSZ128rmbik:
28055 case VMINMAXPSZ128rmbikz:
28056 case VMINMAXPSZ128rmi:
28057 case VMINMAXPSZ128rmik:
28058 case VMINMAXPSZ128rmikz:
28059 case VMINMAXPSZ128rri:
28060 case VMINMAXPSZ128rrik:
28061 case VMINMAXPSZ128rrikz:
28062 case VMINMAXPSZ256rmbi:
28063 case VMINMAXPSZ256rmbik:
28064 case VMINMAXPSZ256rmbikz:
28065 case VMINMAXPSZ256rmi:
28066 case VMINMAXPSZ256rmik:
28067 case VMINMAXPSZ256rmikz:
28068 case VMINMAXPSZ256rri:
28069 case VMINMAXPSZ256rrik:
28070 case VMINMAXPSZ256rrikz:
28071 case VMINMAXPSZrmbi:
28072 case VMINMAXPSZrmbik:
28073 case VMINMAXPSZrmbikz:
28074 case VMINMAXPSZrmi:
28075 case VMINMAXPSZrmik:
28076 case VMINMAXPSZrmikz:
28077 case VMINMAXPSZrri:
28078 case VMINMAXPSZrrib:
28079 case VMINMAXPSZrribk:
28080 case VMINMAXPSZrribkz:
28081 case VMINMAXPSZrrik:
28082 case VMINMAXPSZrrikz:
28083 return true;
28084 }
28085 return false;
28086}
28087
28088bool isPSIGNW(unsigned Opcode) {
28089 switch (Opcode) {
28090 case MMX_PSIGNWrm:
28091 case MMX_PSIGNWrr:
28092 case PSIGNWrm:
28093 case PSIGNWrr:
28094 return true;
28095 }
28096 return false;
28097}
28098
28099bool isUNPCKLPD(unsigned Opcode) {
28100 switch (Opcode) {
28101 case UNPCKLPDrm:
28102 case UNPCKLPDrr:
28103 return true;
28104 }
28105 return false;
28106}
28107
28108bool isPUSHP(unsigned Opcode) {
28109 return Opcode == PUSHP64r;
28110}
28111
28112bool isBLSI(unsigned Opcode) {
28113 switch (Opcode) {
28114 case BLSI32rm:
28115 case BLSI32rm_EVEX:
28116 case BLSI32rm_NF:
28117 case BLSI32rr:
28118 case BLSI32rr_EVEX:
28119 case BLSI32rr_NF:
28120 case BLSI64rm:
28121 case BLSI64rm_EVEX:
28122 case BLSI64rm_NF:
28123 case BLSI64rr:
28124 case BLSI64rr_EVEX:
28125 case BLSI64rr_NF:
28126 return true;
28127 }
28128 return false;
28129}
28130
28131bool isVPTESTNMB(unsigned Opcode) {
28132 switch (Opcode) {
28133 case VPTESTNMBZ128rm:
28134 case VPTESTNMBZ128rmk:
28135 case VPTESTNMBZ128rr:
28136 case VPTESTNMBZ128rrk:
28137 case VPTESTNMBZ256rm:
28138 case VPTESTNMBZ256rmk:
28139 case VPTESTNMBZ256rr:
28140 case VPTESTNMBZ256rrk:
28141 case VPTESTNMBZrm:
28142 case VPTESTNMBZrmk:
28143 case VPTESTNMBZrr:
28144 case VPTESTNMBZrrk:
28145 return true;
28146 }
28147 return false;
28148}
28149
28150bool isWRUSSQ(unsigned Opcode) {
28151 switch (Opcode) {
28152 case WRUSSQ:
28153 case WRUSSQ_EVEX:
28154 return true;
28155 }
28156 return false;
28157}
28158
28159bool isVGF2P8MULB(unsigned Opcode) {
28160 switch (Opcode) {
28161 case VGF2P8MULBYrm:
28162 case VGF2P8MULBYrr:
28163 case VGF2P8MULBZ128rm:
28164 case VGF2P8MULBZ128rmk:
28165 case VGF2P8MULBZ128rmkz:
28166 case VGF2P8MULBZ128rr:
28167 case VGF2P8MULBZ128rrk:
28168 case VGF2P8MULBZ128rrkz:
28169 case VGF2P8MULBZ256rm:
28170 case VGF2P8MULBZ256rmk:
28171 case VGF2P8MULBZ256rmkz:
28172 case VGF2P8MULBZ256rr:
28173 case VGF2P8MULBZ256rrk:
28174 case VGF2P8MULBZ256rrkz:
28175 case VGF2P8MULBZrm:
28176 case VGF2P8MULBZrmk:
28177 case VGF2P8MULBZrmkz:
28178 case VGF2P8MULBZrr:
28179 case VGF2P8MULBZrrk:
28180 case VGF2P8MULBZrrkz:
28181 case VGF2P8MULBrm:
28182 case VGF2P8MULBrr:
28183 return true;
28184 }
28185 return false;
28186}
28187
28188bool isVPUNPCKLBW(unsigned Opcode) {
28189 switch (Opcode) {
28190 case VPUNPCKLBWYrm:
28191 case VPUNPCKLBWYrr:
28192 case VPUNPCKLBWZ128rm:
28193 case VPUNPCKLBWZ128rmk:
28194 case VPUNPCKLBWZ128rmkz:
28195 case VPUNPCKLBWZ128rr:
28196 case VPUNPCKLBWZ128rrk:
28197 case VPUNPCKLBWZ128rrkz:
28198 case VPUNPCKLBWZ256rm:
28199 case VPUNPCKLBWZ256rmk:
28200 case VPUNPCKLBWZ256rmkz:
28201 case VPUNPCKLBWZ256rr:
28202 case VPUNPCKLBWZ256rrk:
28203 case VPUNPCKLBWZ256rrkz:
28204 case VPUNPCKLBWZrm:
28205 case VPUNPCKLBWZrmk:
28206 case VPUNPCKLBWZrmkz:
28207 case VPUNPCKLBWZrr:
28208 case VPUNPCKLBWZrrk:
28209 case VPUNPCKLBWZrrkz:
28210 case VPUNPCKLBWrm:
28211 case VPUNPCKLBWrr:
28212 return true;
28213 }
28214 return false;
28215}
28216
28217bool isVRANGESD(unsigned Opcode) {
28218 switch (Opcode) {
28219 case VRANGESDZrmi:
28220 case VRANGESDZrmik:
28221 case VRANGESDZrmikz:
28222 case VRANGESDZrri:
28223 case VRANGESDZrrib:
28224 case VRANGESDZrribk:
28225 case VRANGESDZrribkz:
28226 case VRANGESDZrrik:
28227 case VRANGESDZrrikz:
28228 return true;
28229 }
28230 return false;
28231}
28232
28233bool isCLD(unsigned Opcode) {
28234 return Opcode == CLD;
28235}
28236
28237bool isVSCALEFPD(unsigned Opcode) {
28238 switch (Opcode) {
28239 case VSCALEFPDZ128rm:
28240 case VSCALEFPDZ128rmb:
28241 case VSCALEFPDZ128rmbk:
28242 case VSCALEFPDZ128rmbkz:
28243 case VSCALEFPDZ128rmk:
28244 case VSCALEFPDZ128rmkz:
28245 case VSCALEFPDZ128rr:
28246 case VSCALEFPDZ128rrk:
28247 case VSCALEFPDZ128rrkz:
28248 case VSCALEFPDZ256rm:
28249 case VSCALEFPDZ256rmb:
28250 case VSCALEFPDZ256rmbk:
28251 case VSCALEFPDZ256rmbkz:
28252 case VSCALEFPDZ256rmk:
28253 case VSCALEFPDZ256rmkz:
28254 case VSCALEFPDZ256rr:
28255 case VSCALEFPDZ256rrk:
28256 case VSCALEFPDZ256rrkz:
28257 case VSCALEFPDZrm:
28258 case VSCALEFPDZrmb:
28259 case VSCALEFPDZrmbk:
28260 case VSCALEFPDZrmbkz:
28261 case VSCALEFPDZrmk:
28262 case VSCALEFPDZrmkz:
28263 case VSCALEFPDZrr:
28264 case VSCALEFPDZrrb:
28265 case VSCALEFPDZrrbk:
28266 case VSCALEFPDZrrbkz:
28267 case VSCALEFPDZrrk:
28268 case VSCALEFPDZrrkz:
28269 return true;
28270 }
28271 return false;
28272}
28273
28274bool isVCOMXSS(unsigned Opcode) {
28275 switch (Opcode) {
28276 case VCOMXSSZrm_Int:
28277 case VCOMXSSZrr_Int:
28278 case VCOMXSSZrrb_Int:
28279 return true;
28280 }
28281 return false;
28282}
28283
28284bool isVPERMQ(unsigned Opcode) {
28285 switch (Opcode) {
28286 case VPERMQYmi:
28287 case VPERMQYri:
28288 case VPERMQZ256mbi:
28289 case VPERMQZ256mbik:
28290 case VPERMQZ256mbikz:
28291 case VPERMQZ256mi:
28292 case VPERMQZ256mik:
28293 case VPERMQZ256mikz:
28294 case VPERMQZ256ri:
28295 case VPERMQZ256rik:
28296 case VPERMQZ256rikz:
28297 case VPERMQZ256rm:
28298 case VPERMQZ256rmb:
28299 case VPERMQZ256rmbk:
28300 case VPERMQZ256rmbkz:
28301 case VPERMQZ256rmk:
28302 case VPERMQZ256rmkz:
28303 case VPERMQZ256rr:
28304 case VPERMQZ256rrk:
28305 case VPERMQZ256rrkz:
28306 case VPERMQZmbi:
28307 case VPERMQZmbik:
28308 case VPERMQZmbikz:
28309 case VPERMQZmi:
28310 case VPERMQZmik:
28311 case VPERMQZmikz:
28312 case VPERMQZri:
28313 case VPERMQZrik:
28314 case VPERMQZrikz:
28315 case VPERMQZrm:
28316 case VPERMQZrmb:
28317 case VPERMQZrmbk:
28318 case VPERMQZrmbkz:
28319 case VPERMQZrmk:
28320 case VPERMQZrmkz:
28321 case VPERMQZrr:
28322 case VPERMQZrrk:
28323 case VPERMQZrrkz:
28324 return true;
28325 }
28326 return false;
28327}
28328
28329bool isVPSHLDVW(unsigned Opcode) {
28330 switch (Opcode) {
28331 case VPSHLDVWZ128m:
28332 case VPSHLDVWZ128mk:
28333 case VPSHLDVWZ128mkz:
28334 case VPSHLDVWZ128r:
28335 case VPSHLDVWZ128rk:
28336 case VPSHLDVWZ128rkz:
28337 case VPSHLDVWZ256m:
28338 case VPSHLDVWZ256mk:
28339 case VPSHLDVWZ256mkz:
28340 case VPSHLDVWZ256r:
28341 case VPSHLDVWZ256rk:
28342 case VPSHLDVWZ256rkz:
28343 case VPSHLDVWZm:
28344 case VPSHLDVWZmk:
28345 case VPSHLDVWZmkz:
28346 case VPSHLDVWZr:
28347 case VPSHLDVWZrk:
28348 case VPSHLDVWZrkz:
28349 return true;
28350 }
28351 return false;
28352}
28353
28354bool isROR(unsigned Opcode) {
28355 switch (Opcode) {
28356 case ROR16m1:
28357 case ROR16m1_EVEX:
28358 case ROR16m1_ND:
28359 case ROR16m1_NF:
28360 case ROR16m1_NF_ND:
28361 case ROR16mCL:
28362 case ROR16mCL_EVEX:
28363 case ROR16mCL_ND:
28364 case ROR16mCL_NF:
28365 case ROR16mCL_NF_ND:
28366 case ROR16mi:
28367 case ROR16mi_EVEX:
28368 case ROR16mi_ND:
28369 case ROR16mi_NF:
28370 case ROR16mi_NF_ND:
28371 case ROR16r1:
28372 case ROR16r1_EVEX:
28373 case ROR16r1_ND:
28374 case ROR16r1_NF:
28375 case ROR16r1_NF_ND:
28376 case ROR16rCL:
28377 case ROR16rCL_EVEX:
28378 case ROR16rCL_ND:
28379 case ROR16rCL_NF:
28380 case ROR16rCL_NF_ND:
28381 case ROR16ri:
28382 case ROR16ri_EVEX:
28383 case ROR16ri_ND:
28384 case ROR16ri_NF:
28385 case ROR16ri_NF_ND:
28386 case ROR32m1:
28387 case ROR32m1_EVEX:
28388 case ROR32m1_ND:
28389 case ROR32m1_NF:
28390 case ROR32m1_NF_ND:
28391 case ROR32mCL:
28392 case ROR32mCL_EVEX:
28393 case ROR32mCL_ND:
28394 case ROR32mCL_NF:
28395 case ROR32mCL_NF_ND:
28396 case ROR32mi:
28397 case ROR32mi_EVEX:
28398 case ROR32mi_ND:
28399 case ROR32mi_NF:
28400 case ROR32mi_NF_ND:
28401 case ROR32r1:
28402 case ROR32r1_EVEX:
28403 case ROR32r1_ND:
28404 case ROR32r1_NF:
28405 case ROR32r1_NF_ND:
28406 case ROR32rCL:
28407 case ROR32rCL_EVEX:
28408 case ROR32rCL_ND:
28409 case ROR32rCL_NF:
28410 case ROR32rCL_NF_ND:
28411 case ROR32ri:
28412 case ROR32ri_EVEX:
28413 case ROR32ri_ND:
28414 case ROR32ri_NF:
28415 case ROR32ri_NF_ND:
28416 case ROR64m1:
28417 case ROR64m1_EVEX:
28418 case ROR64m1_ND:
28419 case ROR64m1_NF:
28420 case ROR64m1_NF_ND:
28421 case ROR64mCL:
28422 case ROR64mCL_EVEX:
28423 case ROR64mCL_ND:
28424 case ROR64mCL_NF:
28425 case ROR64mCL_NF_ND:
28426 case ROR64mi:
28427 case ROR64mi_EVEX:
28428 case ROR64mi_ND:
28429 case ROR64mi_NF:
28430 case ROR64mi_NF_ND:
28431 case ROR64r1:
28432 case ROR64r1_EVEX:
28433 case ROR64r1_ND:
28434 case ROR64r1_NF:
28435 case ROR64r1_NF_ND:
28436 case ROR64rCL:
28437 case ROR64rCL_EVEX:
28438 case ROR64rCL_ND:
28439 case ROR64rCL_NF:
28440 case ROR64rCL_NF_ND:
28441 case ROR64ri:
28442 case ROR64ri_EVEX:
28443 case ROR64ri_ND:
28444 case ROR64ri_NF:
28445 case ROR64ri_NF_ND:
28446 case ROR8m1:
28447 case ROR8m1_EVEX:
28448 case ROR8m1_ND:
28449 case ROR8m1_NF:
28450 case ROR8m1_NF_ND:
28451 case ROR8mCL:
28452 case ROR8mCL_EVEX:
28453 case ROR8mCL_ND:
28454 case ROR8mCL_NF:
28455 case ROR8mCL_NF_ND:
28456 case ROR8mi:
28457 case ROR8mi_EVEX:
28458 case ROR8mi_ND:
28459 case ROR8mi_NF:
28460 case ROR8mi_NF_ND:
28461 case ROR8r1:
28462 case ROR8r1_EVEX:
28463 case ROR8r1_ND:
28464 case ROR8r1_NF:
28465 case ROR8r1_NF_ND:
28466 case ROR8rCL:
28467 case ROR8rCL_EVEX:
28468 case ROR8rCL_ND:
28469 case ROR8rCL_NF:
28470 case ROR8rCL_NF_ND:
28471 case ROR8ri:
28472 case ROR8ri_EVEX:
28473 case ROR8ri_ND:
28474 case ROR8ri_NF:
28475 case ROR8ri_NF_ND:
28476 return true;
28477 }
28478 return false;
28479}
28480
28481bool isVFMADDSUB132PH(unsigned Opcode) {
28482 switch (Opcode) {
28483 case VFMADDSUB132PHZ128m:
28484 case VFMADDSUB132PHZ128mb:
28485 case VFMADDSUB132PHZ128mbk:
28486 case VFMADDSUB132PHZ128mbkz:
28487 case VFMADDSUB132PHZ128mk:
28488 case VFMADDSUB132PHZ128mkz:
28489 case VFMADDSUB132PHZ128r:
28490 case VFMADDSUB132PHZ128rk:
28491 case VFMADDSUB132PHZ128rkz:
28492 case VFMADDSUB132PHZ256m:
28493 case VFMADDSUB132PHZ256mb:
28494 case VFMADDSUB132PHZ256mbk:
28495 case VFMADDSUB132PHZ256mbkz:
28496 case VFMADDSUB132PHZ256mk:
28497 case VFMADDSUB132PHZ256mkz:
28498 case VFMADDSUB132PHZ256r:
28499 case VFMADDSUB132PHZ256rk:
28500 case VFMADDSUB132PHZ256rkz:
28501 case VFMADDSUB132PHZm:
28502 case VFMADDSUB132PHZmb:
28503 case VFMADDSUB132PHZmbk:
28504 case VFMADDSUB132PHZmbkz:
28505 case VFMADDSUB132PHZmk:
28506 case VFMADDSUB132PHZmkz:
28507 case VFMADDSUB132PHZr:
28508 case VFMADDSUB132PHZrb:
28509 case VFMADDSUB132PHZrbk:
28510 case VFMADDSUB132PHZrbkz:
28511 case VFMADDSUB132PHZrk:
28512 case VFMADDSUB132PHZrkz:
28513 return true;
28514 }
28515 return false;
28516}
28517
28518bool isDEC(unsigned Opcode) {
28519 switch (Opcode) {
28520 case DEC16m:
28521 case DEC16m_EVEX:
28522 case DEC16m_ND:
28523 case DEC16m_NF:
28524 case DEC16m_NF_ND:
28525 case DEC16r:
28526 case DEC16r_EVEX:
28527 case DEC16r_ND:
28528 case DEC16r_NF:
28529 case DEC16r_NF_ND:
28530 case DEC16r_alt:
28531 case DEC32m:
28532 case DEC32m_EVEX:
28533 case DEC32m_ND:
28534 case DEC32m_NF:
28535 case DEC32m_NF_ND:
28536 case DEC32r:
28537 case DEC32r_EVEX:
28538 case DEC32r_ND:
28539 case DEC32r_NF:
28540 case DEC32r_NF_ND:
28541 case DEC32r_alt:
28542 case DEC64m:
28543 case DEC64m_EVEX:
28544 case DEC64m_ND:
28545 case DEC64m_NF:
28546 case DEC64m_NF_ND:
28547 case DEC64r:
28548 case DEC64r_EVEX:
28549 case DEC64r_ND:
28550 case DEC64r_NF:
28551 case DEC64r_NF_ND:
28552 case DEC8m:
28553 case DEC8m_EVEX:
28554 case DEC8m_ND:
28555 case DEC8m_NF:
28556 case DEC8m_NF_ND:
28557 case DEC8r:
28558 case DEC8r_EVEX:
28559 case DEC8r_ND:
28560 case DEC8r_NF:
28561 case DEC8r_NF_ND:
28562 return true;
28563 }
28564 return false;
28565}
28566
28567bool isVGETEXPSH(unsigned Opcode) {
28568 switch (Opcode) {
28569 case VGETEXPSHZm:
28570 case VGETEXPSHZmk:
28571 case VGETEXPSHZmkz:
28572 case VGETEXPSHZr:
28573 case VGETEXPSHZrb:
28574 case VGETEXPSHZrbk:
28575 case VGETEXPSHZrbkz:
28576 case VGETEXPSHZrk:
28577 case VGETEXPSHZrkz:
28578 return true;
28579 }
28580 return false;
28581}
28582
28583bool isAESDEC(unsigned Opcode) {
28584 switch (Opcode) {
28585 case AESDECrm:
28586 case AESDECrr:
28587 return true;
28588 }
28589 return false;
28590}
28591
28592bool isKORD(unsigned Opcode) {
28593 return Opcode == KORDkk;
28594}
28595
28596bool isVPMULHW(unsigned Opcode) {
28597 switch (Opcode) {
28598 case VPMULHWYrm:
28599 case VPMULHWYrr:
28600 case VPMULHWZ128rm:
28601 case VPMULHWZ128rmk:
28602 case VPMULHWZ128rmkz:
28603 case VPMULHWZ128rr:
28604 case VPMULHWZ128rrk:
28605 case VPMULHWZ128rrkz:
28606 case VPMULHWZ256rm:
28607 case VPMULHWZ256rmk:
28608 case VPMULHWZ256rmkz:
28609 case VPMULHWZ256rr:
28610 case VPMULHWZ256rrk:
28611 case VPMULHWZ256rrkz:
28612 case VPMULHWZrm:
28613 case VPMULHWZrmk:
28614 case VPMULHWZrmkz:
28615 case VPMULHWZrr:
28616 case VPMULHWZrrk:
28617 case VPMULHWZrrkz:
28618 case VPMULHWrm:
28619 case VPMULHWrr:
28620 return true;
28621 }
28622 return false;
28623}
28624
28625bool isTILELOADDT1(unsigned Opcode) {
28626 switch (Opcode) {
28627 case TILELOADDT1:
28628 case TILELOADDT1_EVEX:
28629 return true;
28630 }
28631 return false;
28632}
28633
28634bool isVMASKMOVPS(unsigned Opcode) {
28635 switch (Opcode) {
28636 case VMASKMOVPSYmr:
28637 case VMASKMOVPSYrm:
28638 case VMASKMOVPSmr:
28639 case VMASKMOVPSrm:
28640 return true;
28641 }
28642 return false;
28643}
28644
28645bool isPMOVZXDQ(unsigned Opcode) {
28646 switch (Opcode) {
28647 case PMOVZXDQrm:
28648 case PMOVZXDQrr:
28649 return true;
28650 }
28651 return false;
28652}
28653
28654bool isVCVTPS2PH(unsigned Opcode) {
28655 switch (Opcode) {
28656 case VCVTPS2PHYmr:
28657 case VCVTPS2PHYrr:
28658 case VCVTPS2PHZ128mr:
28659 case VCVTPS2PHZ128mrk:
28660 case VCVTPS2PHZ128rr:
28661 case VCVTPS2PHZ128rrk:
28662 case VCVTPS2PHZ128rrkz:
28663 case VCVTPS2PHZ256mr:
28664 case VCVTPS2PHZ256mrk:
28665 case VCVTPS2PHZ256rr:
28666 case VCVTPS2PHZ256rrk:
28667 case VCVTPS2PHZ256rrkz:
28668 case VCVTPS2PHZmr:
28669 case VCVTPS2PHZmrk:
28670 case VCVTPS2PHZrr:
28671 case VCVTPS2PHZrrb:
28672 case VCVTPS2PHZrrbk:
28673 case VCVTPS2PHZrrbkz:
28674 case VCVTPS2PHZrrk:
28675 case VCVTPS2PHZrrkz:
28676 case VCVTPS2PHmr:
28677 case VCVTPS2PHrr:
28678 return true;
28679 }
28680 return false;
28681}
28682
28683bool isCVTDQ2PD(unsigned Opcode) {
28684 switch (Opcode) {
28685 case CVTDQ2PDrm:
28686 case CVTDQ2PDrr:
28687 return true;
28688 }
28689 return false;
28690}
28691
28692bool isVCVTSD2SS(unsigned Opcode) {
28693 switch (Opcode) {
28694 case VCVTSD2SSZrm_Int:
28695 case VCVTSD2SSZrmk_Int:
28696 case VCVTSD2SSZrmkz_Int:
28697 case VCVTSD2SSZrr_Int:
28698 case VCVTSD2SSZrrb_Int:
28699 case VCVTSD2SSZrrbk_Int:
28700 case VCVTSD2SSZrrbkz_Int:
28701 case VCVTSD2SSZrrk_Int:
28702 case VCVTSD2SSZrrkz_Int:
28703 case VCVTSD2SSrm_Int:
28704 case VCVTSD2SSrr_Int:
28705 return true;
28706 }
28707 return false;
28708}
28709
28710bool isVFMSUB213PH(unsigned Opcode) {
28711 switch (Opcode) {
28712 case VFMSUB213PHZ128m:
28713 case VFMSUB213PHZ128mb:
28714 case VFMSUB213PHZ128mbk:
28715 case VFMSUB213PHZ128mbkz:
28716 case VFMSUB213PHZ128mk:
28717 case VFMSUB213PHZ128mkz:
28718 case VFMSUB213PHZ128r:
28719 case VFMSUB213PHZ128rk:
28720 case VFMSUB213PHZ128rkz:
28721 case VFMSUB213PHZ256m:
28722 case VFMSUB213PHZ256mb:
28723 case VFMSUB213PHZ256mbk:
28724 case VFMSUB213PHZ256mbkz:
28725 case VFMSUB213PHZ256mk:
28726 case VFMSUB213PHZ256mkz:
28727 case VFMSUB213PHZ256r:
28728 case VFMSUB213PHZ256rk:
28729 case VFMSUB213PHZ256rkz:
28730 case VFMSUB213PHZm:
28731 case VFMSUB213PHZmb:
28732 case VFMSUB213PHZmbk:
28733 case VFMSUB213PHZmbkz:
28734 case VFMSUB213PHZmk:
28735 case VFMSUB213PHZmkz:
28736 case VFMSUB213PHZr:
28737 case VFMSUB213PHZrb:
28738 case VFMSUB213PHZrbk:
28739 case VFMSUB213PHZrbkz:
28740 case VFMSUB213PHZrk:
28741 case VFMSUB213PHZrkz:
28742 return true;
28743 }
28744 return false;
28745}
28746
28747bool isVPROTB(unsigned Opcode) {
28748 switch (Opcode) {
28749 case VPROTBmi:
28750 case VPROTBmr:
28751 case VPROTBri:
28752 case VPROTBrm:
28753 case VPROTBrr:
28754 case VPROTBrr_REV:
28755 return true;
28756 }
28757 return false;
28758}
28759
28760bool isPINSRD(unsigned Opcode) {
28761 switch (Opcode) {
28762 case PINSRDrmi:
28763 case PINSRDrri:
28764 return true;
28765 }
28766 return false;
28767}
28768
28769bool isVMXON(unsigned Opcode) {
28770 return Opcode == VMXON;
28771}
28772
28773bool isVFCMULCSH(unsigned Opcode) {
28774 switch (Opcode) {
28775 case VFCMULCSHZrm:
28776 case VFCMULCSHZrmk:
28777 case VFCMULCSHZrmkz:
28778 case VFCMULCSHZrr:
28779 case VFCMULCSHZrrb:
28780 case VFCMULCSHZrrbk:
28781 case VFCMULCSHZrrbkz:
28782 case VFCMULCSHZrrk:
28783 case VFCMULCSHZrrkz:
28784 return true;
28785 }
28786 return false;
28787}
28788
28789bool isVFMULCSH(unsigned Opcode) {
28790 switch (Opcode) {
28791 case VFMULCSHZrm:
28792 case VFMULCSHZrmk:
28793 case VFMULCSHZrmkz:
28794 case VFMULCSHZrr:
28795 case VFMULCSHZrrb:
28796 case VFMULCSHZrrbk:
28797 case VFMULCSHZrrbkz:
28798 case VFMULCSHZrrk:
28799 case VFMULCSHZrrkz:
28800 return true;
28801 }
28802 return false;
28803}
28804
28805bool isVRANGEPD(unsigned Opcode) {
28806 switch (Opcode) {
28807 case VRANGEPDZ128rmbi:
28808 case VRANGEPDZ128rmbik:
28809 case VRANGEPDZ128rmbikz:
28810 case VRANGEPDZ128rmi:
28811 case VRANGEPDZ128rmik:
28812 case VRANGEPDZ128rmikz:
28813 case VRANGEPDZ128rri:
28814 case VRANGEPDZ128rrik:
28815 case VRANGEPDZ128rrikz:
28816 case VRANGEPDZ256rmbi:
28817 case VRANGEPDZ256rmbik:
28818 case VRANGEPDZ256rmbikz:
28819 case VRANGEPDZ256rmi:
28820 case VRANGEPDZ256rmik:
28821 case VRANGEPDZ256rmikz:
28822 case VRANGEPDZ256rri:
28823 case VRANGEPDZ256rrik:
28824 case VRANGEPDZ256rrikz:
28825 case VRANGEPDZrmbi:
28826 case VRANGEPDZrmbik:
28827 case VRANGEPDZrmbikz:
28828 case VRANGEPDZrmi:
28829 case VRANGEPDZrmik:
28830 case VRANGEPDZrmikz:
28831 case VRANGEPDZrri:
28832 case VRANGEPDZrrib:
28833 case VRANGEPDZrribk:
28834 case VRANGEPDZrribkz:
28835 case VRANGEPDZrrik:
28836 case VRANGEPDZrrikz:
28837 return true;
28838 }
28839 return false;
28840}
28841
28842bool isCMC(unsigned Opcode) {
28843 return Opcode == CMC;
28844}
28845
28846bool isVFNMADD231BF16(unsigned Opcode) {
28847 switch (Opcode) {
28848 case VFNMADD231BF16Z128m:
28849 case VFNMADD231BF16Z128mb:
28850 case VFNMADD231BF16Z128mbk:
28851 case VFNMADD231BF16Z128mbkz:
28852 case VFNMADD231BF16Z128mk:
28853 case VFNMADD231BF16Z128mkz:
28854 case VFNMADD231BF16Z128r:
28855 case VFNMADD231BF16Z128rk:
28856 case VFNMADD231BF16Z128rkz:
28857 case VFNMADD231BF16Z256m:
28858 case VFNMADD231BF16Z256mb:
28859 case VFNMADD231BF16Z256mbk:
28860 case VFNMADD231BF16Z256mbkz:
28861 case VFNMADD231BF16Z256mk:
28862 case VFNMADD231BF16Z256mkz:
28863 case VFNMADD231BF16Z256r:
28864 case VFNMADD231BF16Z256rk:
28865 case VFNMADD231BF16Z256rkz:
28866 case VFNMADD231BF16Zm:
28867 case VFNMADD231BF16Zmb:
28868 case VFNMADD231BF16Zmbk:
28869 case VFNMADD231BF16Zmbkz:
28870 case VFNMADD231BF16Zmk:
28871 case VFNMADD231BF16Zmkz:
28872 case VFNMADD231BF16Zr:
28873 case VFNMADD231BF16Zrk:
28874 case VFNMADD231BF16Zrkz:
28875 return true;
28876 }
28877 return false;
28878}
28879
28880bool isSHA256MSG1(unsigned Opcode) {
28881 switch (Opcode) {
28882 case SHA256MSG1rm:
28883 case SHA256MSG1rr:
28884 return true;
28885 }
28886 return false;
28887}
28888
28889bool isFLD1(unsigned Opcode) {
28890 return Opcode == LD_F1;
28891}
28892
28893bool isCMPPS(unsigned Opcode) {
28894 switch (Opcode) {
28895 case CMPPSrmi:
28896 case CMPPSrri:
28897 return true;
28898 }
28899 return false;
28900}
28901
28902bool isVPAVGW(unsigned Opcode) {
28903 switch (Opcode) {
28904 case VPAVGWYrm:
28905 case VPAVGWYrr:
28906 case VPAVGWZ128rm:
28907 case VPAVGWZ128rmk:
28908 case VPAVGWZ128rmkz:
28909 case VPAVGWZ128rr:
28910 case VPAVGWZ128rrk:
28911 case VPAVGWZ128rrkz:
28912 case VPAVGWZ256rm:
28913 case VPAVGWZ256rmk:
28914 case VPAVGWZ256rmkz:
28915 case VPAVGWZ256rr:
28916 case VPAVGWZ256rrk:
28917 case VPAVGWZ256rrkz:
28918 case VPAVGWZrm:
28919 case VPAVGWZrmk:
28920 case VPAVGWZrmkz:
28921 case VPAVGWZrr:
28922 case VPAVGWZrrk:
28923 case VPAVGWZrrkz:
28924 case VPAVGWrm:
28925 case VPAVGWrr:
28926 return true;
28927 }
28928 return false;
28929}
28930
28931bool isVFMADD213SH(unsigned Opcode) {
28932 switch (Opcode) {
28933 case VFMADD213SHZm_Int:
28934 case VFMADD213SHZmk_Int:
28935 case VFMADD213SHZmkz_Int:
28936 case VFMADD213SHZr_Int:
28937 case VFMADD213SHZrb_Int:
28938 case VFMADD213SHZrbk_Int:
28939 case VFMADD213SHZrbkz_Int:
28940 case VFMADD213SHZrk_Int:
28941 case VFMADD213SHZrkz_Int:
28942 return true;
28943 }
28944 return false;
28945}
28946
28947bool isVPINSRQ(unsigned Opcode) {
28948 switch (Opcode) {
28949 case VPINSRQZrmi:
28950 case VPINSRQZrri:
28951 case VPINSRQrmi:
28952 case VPINSRQrri:
28953 return true;
28954 }
28955 return false;
28956}
28957
28958bool isMOVABS(unsigned Opcode) {
28959 switch (Opcode) {
28960 case MOV16ao64:
28961 case MOV16o64a:
28962 case MOV32ao64:
28963 case MOV32o64a:
28964 case MOV64ao64:
28965 case MOV64o64a:
28966 case MOV64ri:
28967 case MOV8ao64:
28968 case MOV8o64a:
28969 return true;
28970 }
28971 return false;
28972}
28973
28974bool isVPSHAQ(unsigned Opcode) {
28975 switch (Opcode) {
28976 case VPSHAQmr:
28977 case VPSHAQrm:
28978 case VPSHAQrr:
28979 case VPSHAQrr_REV:
28980 return true;
28981 }
28982 return false;
28983}
28984
28985bool isRDTSCP(unsigned Opcode) {
28986 return Opcode == RDTSCP;
28987}
28988
28989bool isVFNMADD231SS(unsigned Opcode) {
28990 switch (Opcode) {
28991 case VFNMADD231SSZm_Int:
28992 case VFNMADD231SSZmk_Int:
28993 case VFNMADD231SSZmkz_Int:
28994 case VFNMADD231SSZr_Int:
28995 case VFNMADD231SSZrb_Int:
28996 case VFNMADD231SSZrbk_Int:
28997 case VFNMADD231SSZrbkz_Int:
28998 case VFNMADD231SSZrk_Int:
28999 case VFNMADD231SSZrkz_Int:
29000 case VFNMADD231SSm_Int:
29001 case VFNMADD231SSr_Int:
29002 return true;
29003 }
29004 return false;
29005}
29006
29007bool isTEST(unsigned Opcode) {
29008 switch (Opcode) {
29009 case TEST16i16:
29010 case TEST16mi:
29011 case TEST16mr:
29012 case TEST16ri:
29013 case TEST16rr:
29014 case TEST32i32:
29015 case TEST32mi:
29016 case TEST32mr:
29017 case TEST32ri:
29018 case TEST32rr:
29019 case TEST64i32:
29020 case TEST64mi32:
29021 case TEST64mr:
29022 case TEST64ri32:
29023 case TEST64rr:
29024 case TEST8i8:
29025 case TEST8mi:
29026 case TEST8mr:
29027 case TEST8ri:
29028 case TEST8rr:
29029 return true;
29030 }
29031 return false;
29032}
29033
29034bool isVPERMD(unsigned Opcode) {
29035 switch (Opcode) {
29036 case VPERMDYrm:
29037 case VPERMDYrr:
29038 case VPERMDZ256rm:
29039 case VPERMDZ256rmb:
29040 case VPERMDZ256rmbk:
29041 case VPERMDZ256rmbkz:
29042 case VPERMDZ256rmk:
29043 case VPERMDZ256rmkz:
29044 case VPERMDZ256rr:
29045 case VPERMDZ256rrk:
29046 case VPERMDZ256rrkz:
29047 case VPERMDZrm:
29048 case VPERMDZrmb:
29049 case VPERMDZrmbk:
29050 case VPERMDZrmbkz:
29051 case VPERMDZrmk:
29052 case VPERMDZrmkz:
29053 case VPERMDZrr:
29054 case VPERMDZrrk:
29055 case VPERMDZrrkz:
29056 return true;
29057 }
29058 return false;
29059}
29060
29061bool isVBCSTNESH2PS(unsigned Opcode) {
29062 switch (Opcode) {
29063 case VBCSTNESH2PSYrm:
29064 case VBCSTNESH2PSrm:
29065 return true;
29066 }
29067 return false;
29068}
29069
29070bool isVGATHERPF0QPD(unsigned Opcode) {
29071 return Opcode == VGATHERPF0QPDm;
29072}
29073
29074bool isVPERM2I128(unsigned Opcode) {
29075 switch (Opcode) {
29076 case VPERM2I128rmi:
29077 case VPERM2I128rri:
29078 return true;
29079 }
29080 return false;
29081}
29082
29083bool isVMPSADBW(unsigned Opcode) {
29084 switch (Opcode) {
29085 case VMPSADBWYrmi:
29086 case VMPSADBWYrri:
29087 case VMPSADBWZ128rmi:
29088 case VMPSADBWZ128rmik:
29089 case VMPSADBWZ128rmikz:
29090 case VMPSADBWZ128rri:
29091 case VMPSADBWZ128rrik:
29092 case VMPSADBWZ128rrikz:
29093 case VMPSADBWZ256rmi:
29094 case VMPSADBWZ256rmik:
29095 case VMPSADBWZ256rmikz:
29096 case VMPSADBWZ256rri:
29097 case VMPSADBWZ256rrik:
29098 case VMPSADBWZ256rrikz:
29099 case VMPSADBWZrmi:
29100 case VMPSADBWZrmik:
29101 case VMPSADBWZrmikz:
29102 case VMPSADBWZrri:
29103 case VMPSADBWZrrik:
29104 case VMPSADBWZrrikz:
29105 case VMPSADBWrmi:
29106 case VMPSADBWrri:
29107 return true;
29108 }
29109 return false;
29110}
29111
29112bool isVFNMSUB231PD(unsigned Opcode) {
29113 switch (Opcode) {
29114 case VFNMSUB231PDYm:
29115 case VFNMSUB231PDYr:
29116 case VFNMSUB231PDZ128m:
29117 case VFNMSUB231PDZ128mb:
29118 case VFNMSUB231PDZ128mbk:
29119 case VFNMSUB231PDZ128mbkz:
29120 case VFNMSUB231PDZ128mk:
29121 case VFNMSUB231PDZ128mkz:
29122 case VFNMSUB231PDZ128r:
29123 case VFNMSUB231PDZ128rk:
29124 case VFNMSUB231PDZ128rkz:
29125 case VFNMSUB231PDZ256m:
29126 case VFNMSUB231PDZ256mb:
29127 case VFNMSUB231PDZ256mbk:
29128 case VFNMSUB231PDZ256mbkz:
29129 case VFNMSUB231PDZ256mk:
29130 case VFNMSUB231PDZ256mkz:
29131 case VFNMSUB231PDZ256r:
29132 case VFNMSUB231PDZ256rk:
29133 case VFNMSUB231PDZ256rkz:
29134 case VFNMSUB231PDZm:
29135 case VFNMSUB231PDZmb:
29136 case VFNMSUB231PDZmbk:
29137 case VFNMSUB231PDZmbkz:
29138 case VFNMSUB231PDZmk:
29139 case VFNMSUB231PDZmkz:
29140 case VFNMSUB231PDZr:
29141 case VFNMSUB231PDZrb:
29142 case VFNMSUB231PDZrbk:
29143 case VFNMSUB231PDZrbkz:
29144 case VFNMSUB231PDZrk:
29145 case VFNMSUB231PDZrkz:
29146 case VFNMSUB231PDm:
29147 case VFNMSUB231PDr:
29148 return true;
29149 }
29150 return false;
29151}
29152
29153bool isPADDSB(unsigned Opcode) {
29154 switch (Opcode) {
29155 case MMX_PADDSBrm:
29156 case MMX_PADDSBrr:
29157 case PADDSBrm:
29158 case PADDSBrr:
29159 return true;
29160 }
29161 return false;
29162}
29163
29164bool isMWAITX(unsigned Opcode) {
29165 return Opcode == MWAITXrrr;
29166}
29167
29168bool isMONITORX(unsigned Opcode) {
29169 switch (Opcode) {
29170 case MONITORX32rrr:
29171 case MONITORX64rrr:
29172 return true;
29173 }
29174 return false;
29175}
29176
29177bool isVPEXPANDD(unsigned Opcode) {
29178 switch (Opcode) {
29179 case VPEXPANDDZ128rm:
29180 case VPEXPANDDZ128rmk:
29181 case VPEXPANDDZ128rmkz:
29182 case VPEXPANDDZ128rr:
29183 case VPEXPANDDZ128rrk:
29184 case VPEXPANDDZ128rrkz:
29185 case VPEXPANDDZ256rm:
29186 case VPEXPANDDZ256rmk:
29187 case VPEXPANDDZ256rmkz:
29188 case VPEXPANDDZ256rr:
29189 case VPEXPANDDZ256rrk:
29190 case VPEXPANDDZ256rrkz:
29191 case VPEXPANDDZrm:
29192 case VPEXPANDDZrmk:
29193 case VPEXPANDDZrmkz:
29194 case VPEXPANDDZrr:
29195 case VPEXPANDDZrrk:
29196 case VPEXPANDDZrrkz:
29197 return true;
29198 }
29199 return false;
29200}
29201
29202bool isVFRCZPD(unsigned Opcode) {
29203 switch (Opcode) {
29204 case VFRCZPDYrm:
29205 case VFRCZPDYrr:
29206 case VFRCZPDrm:
29207 case VFRCZPDrr:
29208 return true;
29209 }
29210 return false;
29211}
29212
29213bool isVRCPPH(unsigned Opcode) {
29214 switch (Opcode) {
29215 case VRCPPHZ128m:
29216 case VRCPPHZ128mb:
29217 case VRCPPHZ128mbk:
29218 case VRCPPHZ128mbkz:
29219 case VRCPPHZ128mk:
29220 case VRCPPHZ128mkz:
29221 case VRCPPHZ128r:
29222 case VRCPPHZ128rk:
29223 case VRCPPHZ128rkz:
29224 case VRCPPHZ256m:
29225 case VRCPPHZ256mb:
29226 case VRCPPHZ256mbk:
29227 case VRCPPHZ256mbkz:
29228 case VRCPPHZ256mk:
29229 case VRCPPHZ256mkz:
29230 case VRCPPHZ256r:
29231 case VRCPPHZ256rk:
29232 case VRCPPHZ256rkz:
29233 case VRCPPHZm:
29234 case VRCPPHZmb:
29235 case VRCPPHZmbk:
29236 case VRCPPHZmbkz:
29237 case VRCPPHZmk:
29238 case VRCPPHZmkz:
29239 case VRCPPHZr:
29240 case VRCPPHZrk:
29241 case VRCPPHZrkz:
29242 return true;
29243 }
29244 return false;
29245}
29246
29247bool isFEMMS(unsigned Opcode) {
29248 return Opcode == FEMMS;
29249}
29250
29251bool isVSCATTERQPD(unsigned Opcode) {
29252 switch (Opcode) {
29253 case VSCATTERQPDZ128mr:
29254 case VSCATTERQPDZ256mr:
29255 case VSCATTERQPDZmr:
29256 return true;
29257 }
29258 return false;
29259}
29260
29261bool isVMOVW(unsigned Opcode) {
29262 switch (Opcode) {
29263 case VMOVSH2Wrr:
29264 case VMOVSHtoW64rr:
29265 case VMOVW2SHrr:
29266 case VMOVW64toSHrr:
29267 case VMOVWmr:
29268 case VMOVWrm:
29269 case VMOVZPWILo2PWIZmr:
29270 case VMOVZPWILo2PWIZrm:
29271 case VMOVZPWILo2PWIZrr:
29272 case VMOVZPWILo2PWIZrr2:
29273 return true;
29274 }
29275 return false;
29276}
29277
29278bool isVPBROADCASTD(unsigned Opcode) {
29279 switch (Opcode) {
29280 case VPBROADCASTDYrm:
29281 case VPBROADCASTDYrr:
29282 case VPBROADCASTDZ128rm:
29283 case VPBROADCASTDZ128rmk:
29284 case VPBROADCASTDZ128rmkz:
29285 case VPBROADCASTDZ128rr:
29286 case VPBROADCASTDZ128rrk:
29287 case VPBROADCASTDZ128rrkz:
29288 case VPBROADCASTDZ256rm:
29289 case VPBROADCASTDZ256rmk:
29290 case VPBROADCASTDZ256rmkz:
29291 case VPBROADCASTDZ256rr:
29292 case VPBROADCASTDZ256rrk:
29293 case VPBROADCASTDZ256rrkz:
29294 case VPBROADCASTDZrm:
29295 case VPBROADCASTDZrmk:
29296 case VPBROADCASTDZrmkz:
29297 case VPBROADCASTDZrr:
29298 case VPBROADCASTDZrrk:
29299 case VPBROADCASTDZrrkz:
29300 case VPBROADCASTDrZ128rr:
29301 case VPBROADCASTDrZ128rrk:
29302 case VPBROADCASTDrZ128rrkz:
29303 case VPBROADCASTDrZ256rr:
29304 case VPBROADCASTDrZ256rrk:
29305 case VPBROADCASTDrZ256rrkz:
29306 case VPBROADCASTDrZrr:
29307 case VPBROADCASTDrZrrk:
29308 case VPBROADCASTDrZrrkz:
29309 case VPBROADCASTDrm:
29310 case VPBROADCASTDrr:
29311 return true;
29312 }
29313 return false;
29314}
29315
29316bool isSTOSB(unsigned Opcode) {
29317 return Opcode == STOSB;
29318}
29319
29320bool isFUCOMI(unsigned Opcode) {
29321 return Opcode == UCOM_FIr;
29322}
29323
29324bool isVBROADCASTI64X4(unsigned Opcode) {
29325 switch (Opcode) {
29326 case VBROADCASTI64X4Zrm:
29327 case VBROADCASTI64X4Zrmk:
29328 case VBROADCASTI64X4Zrmkz:
29329 return true;
29330 }
29331 return false;
29332}
29333
29334bool isFCMOVU(unsigned Opcode) {
29335 return Opcode == CMOVP_F;
29336}
29337
29338bool isPSHUFLW(unsigned Opcode) {
29339 switch (Opcode) {
29340 case PSHUFLWmi:
29341 case PSHUFLWri:
29342 return true;
29343 }
29344 return false;
29345}
29346
29347bool isCVTPI2PS(unsigned Opcode) {
29348 switch (Opcode) {
29349 case MMX_CVTPI2PSrm:
29350 case MMX_CVTPI2PSrr:
29351 return true;
29352 }
29353 return false;
29354}
29355
29356bool isVCVTTPD2UDQS(unsigned Opcode) {
29357 switch (Opcode) {
29358 case VCVTTPD2UDQSZ128rm:
29359 case VCVTTPD2UDQSZ128rmb:
29360 case VCVTTPD2UDQSZ128rmbk:
29361 case VCVTTPD2UDQSZ128rmbkz:
29362 case VCVTTPD2UDQSZ128rmk:
29363 case VCVTTPD2UDQSZ128rmkz:
29364 case VCVTTPD2UDQSZ128rr:
29365 case VCVTTPD2UDQSZ128rrk:
29366 case VCVTTPD2UDQSZ128rrkz:
29367 case VCVTTPD2UDQSZ256rm:
29368 case VCVTTPD2UDQSZ256rmb:
29369 case VCVTTPD2UDQSZ256rmbk:
29370 case VCVTTPD2UDQSZ256rmbkz:
29371 case VCVTTPD2UDQSZ256rmk:
29372 case VCVTTPD2UDQSZ256rmkz:
29373 case VCVTTPD2UDQSZ256rr:
29374 case VCVTTPD2UDQSZ256rrb:
29375 case VCVTTPD2UDQSZ256rrbk:
29376 case VCVTTPD2UDQSZ256rrbkz:
29377 case VCVTTPD2UDQSZ256rrk:
29378 case VCVTTPD2UDQSZ256rrkz:
29379 case VCVTTPD2UDQSZrm:
29380 case VCVTTPD2UDQSZrmb:
29381 case VCVTTPD2UDQSZrmbk:
29382 case VCVTTPD2UDQSZrmbkz:
29383 case VCVTTPD2UDQSZrmk:
29384 case VCVTTPD2UDQSZrmkz:
29385 case VCVTTPD2UDQSZrr:
29386 case VCVTTPD2UDQSZrrb:
29387 case VCVTTPD2UDQSZrrbk:
29388 case VCVTTPD2UDQSZrrbkz:
29389 case VCVTTPD2UDQSZrrk:
29390 case VCVTTPD2UDQSZrrkz:
29391 return true;
29392 }
29393 return false;
29394}
29395
29396bool isSYSCALL(unsigned Opcode) {
29397 return Opcode == SYSCALL;
29398}
29399
29400bool isVFMADD231SH(unsigned Opcode) {
29401 switch (Opcode) {
29402 case VFMADD231SHZm_Int:
29403 case VFMADD231SHZmk_Int:
29404 case VFMADD231SHZmkz_Int:
29405 case VFMADD231SHZr_Int:
29406 case VFMADD231SHZrb_Int:
29407 case VFMADD231SHZrbk_Int:
29408 case VFMADD231SHZrbkz_Int:
29409 case VFMADD231SHZrk_Int:
29410 case VFMADD231SHZrkz_Int:
29411 return true;
29412 }
29413 return false;
29414}
29415
29416bool isPMOVZXBW(unsigned Opcode) {
29417 switch (Opcode) {
29418 case PMOVZXBWrm:
29419 case PMOVZXBWrr:
29420 return true;
29421 }
29422 return false;
29423}
29424
29425bool isVPOPCNTB(unsigned Opcode) {
29426 switch (Opcode) {
29427 case VPOPCNTBZ128rm:
29428 case VPOPCNTBZ128rmk:
29429 case VPOPCNTBZ128rmkz:
29430 case VPOPCNTBZ128rr:
29431 case VPOPCNTBZ128rrk:
29432 case VPOPCNTBZ128rrkz:
29433 case VPOPCNTBZ256rm:
29434 case VPOPCNTBZ256rmk:
29435 case VPOPCNTBZ256rmkz:
29436 case VPOPCNTBZ256rr:
29437 case VPOPCNTBZ256rrk:
29438 case VPOPCNTBZ256rrkz:
29439 case VPOPCNTBZrm:
29440 case VPOPCNTBZrmk:
29441 case VPOPCNTBZrmkz:
29442 case VPOPCNTBZrr:
29443 case VPOPCNTBZrrk:
29444 case VPOPCNTBZrrkz:
29445 return true;
29446 }
29447 return false;
29448}
29449
29450bool isVCVTDQ2PS(unsigned Opcode) {
29451 switch (Opcode) {
29452 case VCVTDQ2PSYrm:
29453 case VCVTDQ2PSYrr:
29454 case VCVTDQ2PSZ128rm:
29455 case VCVTDQ2PSZ128rmb:
29456 case VCVTDQ2PSZ128rmbk:
29457 case VCVTDQ2PSZ128rmbkz:
29458 case VCVTDQ2PSZ128rmk:
29459 case VCVTDQ2PSZ128rmkz:
29460 case VCVTDQ2PSZ128rr:
29461 case VCVTDQ2PSZ128rrk:
29462 case VCVTDQ2PSZ128rrkz:
29463 case VCVTDQ2PSZ256rm:
29464 case VCVTDQ2PSZ256rmb:
29465 case VCVTDQ2PSZ256rmbk:
29466 case VCVTDQ2PSZ256rmbkz:
29467 case VCVTDQ2PSZ256rmk:
29468 case VCVTDQ2PSZ256rmkz:
29469 case VCVTDQ2PSZ256rr:
29470 case VCVTDQ2PSZ256rrk:
29471 case VCVTDQ2PSZ256rrkz:
29472 case VCVTDQ2PSZrm:
29473 case VCVTDQ2PSZrmb:
29474 case VCVTDQ2PSZrmbk:
29475 case VCVTDQ2PSZrmbkz:
29476 case VCVTDQ2PSZrmk:
29477 case VCVTDQ2PSZrmkz:
29478 case VCVTDQ2PSZrr:
29479 case VCVTDQ2PSZrrb:
29480 case VCVTDQ2PSZrrbk:
29481 case VCVTDQ2PSZrrbkz:
29482 case VCVTDQ2PSZrrk:
29483 case VCVTDQ2PSZrrkz:
29484 case VCVTDQ2PSrm:
29485 case VCVTDQ2PSrr:
29486 return true;
29487 }
29488 return false;
29489}
29490
29491bool isPSUBD(unsigned Opcode) {
29492 switch (Opcode) {
29493 case MMX_PSUBDrm:
29494 case MMX_PSUBDrr:
29495 case PSUBDrm:
29496 case PSUBDrr:
29497 return true;
29498 }
29499 return false;
29500}
29501
29502bool isVPCMPEQW(unsigned Opcode) {
29503 switch (Opcode) {
29504 case VPCMPEQWYrm:
29505 case VPCMPEQWYrr:
29506 case VPCMPEQWZ128rm:
29507 case VPCMPEQWZ128rmk:
29508 case VPCMPEQWZ128rr:
29509 case VPCMPEQWZ128rrk:
29510 case VPCMPEQWZ256rm:
29511 case VPCMPEQWZ256rmk:
29512 case VPCMPEQWZ256rr:
29513 case VPCMPEQWZ256rrk:
29514 case VPCMPEQWZrm:
29515 case VPCMPEQWZrmk:
29516 case VPCMPEQWZrr:
29517 case VPCMPEQWZrrk:
29518 case VPCMPEQWrm:
29519 case VPCMPEQWrr:
29520 return true;
29521 }
29522 return false;
29523}
29524
29525bool isMOVSW(unsigned Opcode) {
29526 return Opcode == MOVSW;
29527}
29528
29529bool isVSM3RNDS2(unsigned Opcode) {
29530 switch (Opcode) {
29531 case VSM3RNDS2rmi:
29532 case VSM3RNDS2rri:
29533 return true;
29534 }
29535 return false;
29536}
29537
29538bool isVPMOVUSQD(unsigned Opcode) {
29539 switch (Opcode) {
29540 case VPMOVUSQDZ128mr:
29541 case VPMOVUSQDZ128mrk:
29542 case VPMOVUSQDZ128rr:
29543 case VPMOVUSQDZ128rrk:
29544 case VPMOVUSQDZ128rrkz:
29545 case VPMOVUSQDZ256mr:
29546 case VPMOVUSQDZ256mrk:
29547 case VPMOVUSQDZ256rr:
29548 case VPMOVUSQDZ256rrk:
29549 case VPMOVUSQDZ256rrkz:
29550 case VPMOVUSQDZmr:
29551 case VPMOVUSQDZmrk:
29552 case VPMOVUSQDZrr:
29553 case VPMOVUSQDZrrk:
29554 case VPMOVUSQDZrrkz:
29555 return true;
29556 }
29557 return false;
29558}
29559
29560bool isCVTTPD2DQ(unsigned Opcode) {
29561 switch (Opcode) {
29562 case CVTTPD2DQrm:
29563 case CVTTPD2DQrr:
29564 return true;
29565 }
29566 return false;
29567}
29568
29569bool isVPEXPANDW(unsigned Opcode) {
29570 switch (Opcode) {
29571 case VPEXPANDWZ128rm:
29572 case VPEXPANDWZ128rmk:
29573 case VPEXPANDWZ128rmkz:
29574 case VPEXPANDWZ128rr:
29575 case VPEXPANDWZ128rrk:
29576 case VPEXPANDWZ128rrkz:
29577 case VPEXPANDWZ256rm:
29578 case VPEXPANDWZ256rmk:
29579 case VPEXPANDWZ256rmkz:
29580 case VPEXPANDWZ256rr:
29581 case VPEXPANDWZ256rrk:
29582 case VPEXPANDWZ256rrkz:
29583 case VPEXPANDWZrm:
29584 case VPEXPANDWZrmk:
29585 case VPEXPANDWZrmkz:
29586 case VPEXPANDWZrr:
29587 case VPEXPANDWZrrk:
29588 case VPEXPANDWZrrkz:
29589 return true;
29590 }
29591 return false;
29592}
29593
29594bool isVUCOMISH(unsigned Opcode) {
29595 switch (Opcode) {
29596 case VUCOMISHZrm:
29597 case VUCOMISHZrr:
29598 case VUCOMISHZrrb:
29599 return true;
29600 }
29601 return false;
29602}
29603
29604bool isVZEROALL(unsigned Opcode) {
29605 return Opcode == VZEROALL;
29606}
29607
29608bool isVPAND(unsigned Opcode) {
29609 switch (Opcode) {
29610 case VPANDYrm:
29611 case VPANDYrr:
29612 case VPANDrm:
29613 case VPANDrr:
29614 return true;
29615 }
29616 return false;
29617}
29618
29619bool isPMULDQ(unsigned Opcode) {
29620 switch (Opcode) {
29621 case PMULDQrm:
29622 case PMULDQrr:
29623 return true;
29624 }
29625 return false;
29626}
29627
29628bool isVPSHUFHW(unsigned Opcode) {
29629 switch (Opcode) {
29630 case VPSHUFHWYmi:
29631 case VPSHUFHWYri:
29632 case VPSHUFHWZ128mi:
29633 case VPSHUFHWZ128mik:
29634 case VPSHUFHWZ128mikz:
29635 case VPSHUFHWZ128ri:
29636 case VPSHUFHWZ128rik:
29637 case VPSHUFHWZ128rikz:
29638 case VPSHUFHWZ256mi:
29639 case VPSHUFHWZ256mik:
29640 case VPSHUFHWZ256mikz:
29641 case VPSHUFHWZ256ri:
29642 case VPSHUFHWZ256rik:
29643 case VPSHUFHWZ256rikz:
29644 case VPSHUFHWZmi:
29645 case VPSHUFHWZmik:
29646 case VPSHUFHWZmikz:
29647 case VPSHUFHWZri:
29648 case VPSHUFHWZrik:
29649 case VPSHUFHWZrikz:
29650 case VPSHUFHWmi:
29651 case VPSHUFHWri:
29652 return true;
29653 }
29654 return false;
29655}
29656
29657bool isVPALIGNR(unsigned Opcode) {
29658 switch (Opcode) {
29659 case VPALIGNRYrmi:
29660 case VPALIGNRYrri:
29661 case VPALIGNRZ128rmi:
29662 case VPALIGNRZ128rmik:
29663 case VPALIGNRZ128rmikz:
29664 case VPALIGNRZ128rri:
29665 case VPALIGNRZ128rrik:
29666 case VPALIGNRZ128rrikz:
29667 case VPALIGNRZ256rmi:
29668 case VPALIGNRZ256rmik:
29669 case VPALIGNRZ256rmikz:
29670 case VPALIGNRZ256rri:
29671 case VPALIGNRZ256rrik:
29672 case VPALIGNRZ256rrikz:
29673 case VPALIGNRZrmi:
29674 case VPALIGNRZrmik:
29675 case VPALIGNRZrmikz:
29676 case VPALIGNRZrri:
29677 case VPALIGNRZrrik:
29678 case VPALIGNRZrrikz:
29679 case VPALIGNRrmi:
29680 case VPALIGNRrri:
29681 return true;
29682 }
29683 return false;
29684}
29685
29686bool isSQRTSD(unsigned Opcode) {
29687 switch (Opcode) {
29688 case SQRTSDm_Int:
29689 case SQRTSDr_Int:
29690 return true;
29691 }
29692 return false;
29693}
29694
29695bool isVCVTTPH2UDQ(unsigned Opcode) {
29696 switch (Opcode) {
29697 case VCVTTPH2UDQZ128rm:
29698 case VCVTTPH2UDQZ128rmb:
29699 case VCVTTPH2UDQZ128rmbk:
29700 case VCVTTPH2UDQZ128rmbkz:
29701 case VCVTTPH2UDQZ128rmk:
29702 case VCVTTPH2UDQZ128rmkz:
29703 case VCVTTPH2UDQZ128rr:
29704 case VCVTTPH2UDQZ128rrk:
29705 case VCVTTPH2UDQZ128rrkz:
29706 case VCVTTPH2UDQZ256rm:
29707 case VCVTTPH2UDQZ256rmb:
29708 case VCVTTPH2UDQZ256rmbk:
29709 case VCVTTPH2UDQZ256rmbkz:
29710 case VCVTTPH2UDQZ256rmk:
29711 case VCVTTPH2UDQZ256rmkz:
29712 case VCVTTPH2UDQZ256rr:
29713 case VCVTTPH2UDQZ256rrk:
29714 case VCVTTPH2UDQZ256rrkz:
29715 case VCVTTPH2UDQZrm:
29716 case VCVTTPH2UDQZrmb:
29717 case VCVTTPH2UDQZrmbk:
29718 case VCVTTPH2UDQZrmbkz:
29719 case VCVTTPH2UDQZrmk:
29720 case VCVTTPH2UDQZrmkz:
29721 case VCVTTPH2UDQZrr:
29722 case VCVTTPH2UDQZrrb:
29723 case VCVTTPH2UDQZrrbk:
29724 case VCVTTPH2UDQZrrbkz:
29725 case VCVTTPH2UDQZrrk:
29726 case VCVTTPH2UDQZrrkz:
29727 return true;
29728 }
29729 return false;
29730}
29731
29732bool isVGETEXPPH(unsigned Opcode) {
29733 switch (Opcode) {
29734 case VGETEXPPHZ128m:
29735 case VGETEXPPHZ128mb:
29736 case VGETEXPPHZ128mbk:
29737 case VGETEXPPHZ128mbkz:
29738 case VGETEXPPHZ128mk:
29739 case VGETEXPPHZ128mkz:
29740 case VGETEXPPHZ128r:
29741 case VGETEXPPHZ128rk:
29742 case VGETEXPPHZ128rkz:
29743 case VGETEXPPHZ256m:
29744 case VGETEXPPHZ256mb:
29745 case VGETEXPPHZ256mbk:
29746 case VGETEXPPHZ256mbkz:
29747 case VGETEXPPHZ256mk:
29748 case VGETEXPPHZ256mkz:
29749 case VGETEXPPHZ256r:
29750 case VGETEXPPHZ256rk:
29751 case VGETEXPPHZ256rkz:
29752 case VGETEXPPHZm:
29753 case VGETEXPPHZmb:
29754 case VGETEXPPHZmbk:
29755 case VGETEXPPHZmbkz:
29756 case VGETEXPPHZmk:
29757 case VGETEXPPHZmkz:
29758 case VGETEXPPHZr:
29759 case VGETEXPPHZrb:
29760 case VGETEXPPHZrbk:
29761 case VGETEXPPHZrbkz:
29762 case VGETEXPPHZrk:
29763 case VGETEXPPHZrkz:
29764 return true;
29765 }
29766 return false;
29767}
29768
29769bool isADDPD(unsigned Opcode) {
29770 switch (Opcode) {
29771 case ADDPDrm:
29772 case ADDPDrr:
29773 return true;
29774 }
29775 return false;
29776}
29777
29778bool isVFNMADDPD(unsigned Opcode) {
29779 switch (Opcode) {
29780 case VFNMADDPD4Ymr:
29781 case VFNMADDPD4Yrm:
29782 case VFNMADDPD4Yrr:
29783 case VFNMADDPD4Yrr_REV:
29784 case VFNMADDPD4mr:
29785 case VFNMADDPD4rm:
29786 case VFNMADDPD4rr:
29787 case VFNMADDPD4rr_REV:
29788 return true;
29789 }
29790 return false;
29791}
29792
29793bool isSTTILECFG(unsigned Opcode) {
29794 switch (Opcode) {
29795 case STTILECFG:
29796 case STTILECFG_EVEX:
29797 return true;
29798 }
29799 return false;
29800}
29801
29802bool isVMINPD(unsigned Opcode) {
29803 switch (Opcode) {
29804 case VMINPDYrm:
29805 case VMINPDYrr:
29806 case VMINPDZ128rm:
29807 case VMINPDZ128rmb:
29808 case VMINPDZ128rmbk:
29809 case VMINPDZ128rmbkz:
29810 case VMINPDZ128rmk:
29811 case VMINPDZ128rmkz:
29812 case VMINPDZ128rr:
29813 case VMINPDZ128rrk:
29814 case VMINPDZ128rrkz:
29815 case VMINPDZ256rm:
29816 case VMINPDZ256rmb:
29817 case VMINPDZ256rmbk:
29818 case VMINPDZ256rmbkz:
29819 case VMINPDZ256rmk:
29820 case VMINPDZ256rmkz:
29821 case VMINPDZ256rr:
29822 case VMINPDZ256rrk:
29823 case VMINPDZ256rrkz:
29824 case VMINPDZrm:
29825 case VMINPDZrmb:
29826 case VMINPDZrmbk:
29827 case VMINPDZrmbkz:
29828 case VMINPDZrmk:
29829 case VMINPDZrmkz:
29830 case VMINPDZrr:
29831 case VMINPDZrrb:
29832 case VMINPDZrrbk:
29833 case VMINPDZrrbkz:
29834 case VMINPDZrrk:
29835 case VMINPDZrrkz:
29836 case VMINPDrm:
29837 case VMINPDrr:
29838 return true;
29839 }
29840 return false;
29841}
29842
29843bool isSHA1RNDS4(unsigned Opcode) {
29844 switch (Opcode) {
29845 case SHA1RNDS4rmi:
29846 case SHA1RNDS4rri:
29847 return true;
29848 }
29849 return false;
29850}
29851
29852bool isPBLENDVB(unsigned Opcode) {
29853 switch (Opcode) {
29854 case PBLENDVBrm0:
29855 case PBLENDVBrr0:
29856 return true;
29857 }
29858 return false;
29859}
29860
29861bool isVBROADCASTF128(unsigned Opcode) {
29862 return Opcode == VBROADCASTF128rm;
29863}
29864
29865bool isVPSHRDQ(unsigned Opcode) {
29866 switch (Opcode) {
29867 case VPSHRDQZ128rmbi:
29868 case VPSHRDQZ128rmbik:
29869 case VPSHRDQZ128rmbikz:
29870 case VPSHRDQZ128rmi:
29871 case VPSHRDQZ128rmik:
29872 case VPSHRDQZ128rmikz:
29873 case VPSHRDQZ128rri:
29874 case VPSHRDQZ128rrik:
29875 case VPSHRDQZ128rrikz:
29876 case VPSHRDQZ256rmbi:
29877 case VPSHRDQZ256rmbik:
29878 case VPSHRDQZ256rmbikz:
29879 case VPSHRDQZ256rmi:
29880 case VPSHRDQZ256rmik:
29881 case VPSHRDQZ256rmikz:
29882 case VPSHRDQZ256rri:
29883 case VPSHRDQZ256rrik:
29884 case VPSHRDQZ256rrikz:
29885 case VPSHRDQZrmbi:
29886 case VPSHRDQZrmbik:
29887 case VPSHRDQZrmbikz:
29888 case VPSHRDQZrmi:
29889 case VPSHRDQZrmik:
29890 case VPSHRDQZrmikz:
29891 case VPSHRDQZrri:
29892 case VPSHRDQZrrik:
29893 case VPSHRDQZrrikz:
29894 return true;
29895 }
29896 return false;
29897}
29898
29899bool isVAESIMC(unsigned Opcode) {
29900 switch (Opcode) {
29901 case VAESIMCrm:
29902 case VAESIMCrr:
29903 return true;
29904 }
29905 return false;
29906}
29907
29908bool isCOMISD(unsigned Opcode) {
29909 switch (Opcode) {
29910 case COMISDrm:
29911 case COMISDrr:
29912 return true;
29913 }
29914 return false;
29915}
29916
29917bool isVMOVSH(unsigned Opcode) {
29918 switch (Opcode) {
29919 case VMOVSHZmr:
29920 case VMOVSHZmrk:
29921 case VMOVSHZrm:
29922 case VMOVSHZrmk:
29923 case VMOVSHZrmkz:
29924 case VMOVSHZrr:
29925 case VMOVSHZrr_REV:
29926 case VMOVSHZrrk:
29927 case VMOVSHZrrk_REV:
29928 case VMOVSHZrrkz:
29929 case VMOVSHZrrkz_REV:
29930 return true;
29931 }
29932 return false;
29933}
29934
29935bool isPFSUBR(unsigned Opcode) {
29936 switch (Opcode) {
29937 case PFSUBRrm:
29938 case PFSUBRrr:
29939 return true;
29940 }
29941 return false;
29942}
29943
29944bool isRDSSPD(unsigned Opcode) {
29945 return Opcode == RDSSPD;
29946}
29947
29948bool isWAIT(unsigned Opcode) {
29949 return Opcode == WAIT;
29950}
29951
29952bool isVFPCLASSSS(unsigned Opcode) {
29953 switch (Opcode) {
29954 case VFPCLASSSSZmi:
29955 case VFPCLASSSSZmik:
29956 case VFPCLASSSSZri:
29957 case VFPCLASSSSZrik:
29958 return true;
29959 }
29960 return false;
29961}
29962
29963bool isPCMPGTD(unsigned Opcode) {
29964 switch (Opcode) {
29965 case MMX_PCMPGTDrm:
29966 case MMX_PCMPGTDrr:
29967 case PCMPGTDrm:
29968 case PCMPGTDrr:
29969 return true;
29970 }
29971 return false;
29972}
29973
29974bool isVGATHERPF0QPS(unsigned Opcode) {
29975 return Opcode == VGATHERPF0QPSm;
29976}
29977
29978bool isBLENDVPS(unsigned Opcode) {
29979 switch (Opcode) {
29980 case BLENDVPSrm0:
29981 case BLENDVPSrr0:
29982 return true;
29983 }
29984 return false;
29985}
29986
29987bool isVBROADCASTF32X4(unsigned Opcode) {
29988 switch (Opcode) {
29989 case VBROADCASTF32X4Z256rm:
29990 case VBROADCASTF32X4Z256rmk:
29991 case VBROADCASTF32X4Z256rmkz:
29992 case VBROADCASTF32X4Zrm:
29993 case VBROADCASTF32X4Zrmk:
29994 case VBROADCASTF32X4Zrmkz:
29995 return true;
29996 }
29997 return false;
29998}
29999
30000bool isVPMADD52LUQ(unsigned Opcode) {
30001 switch (Opcode) {
30002 case VPMADD52LUQYrm:
30003 case VPMADD52LUQYrr:
30004 case VPMADD52LUQZ128m:
30005 case VPMADD52LUQZ128mb:
30006 case VPMADD52LUQZ128mbk:
30007 case VPMADD52LUQZ128mbkz:
30008 case VPMADD52LUQZ128mk:
30009 case VPMADD52LUQZ128mkz:
30010 case VPMADD52LUQZ128r:
30011 case VPMADD52LUQZ128rk:
30012 case VPMADD52LUQZ128rkz:
30013 case VPMADD52LUQZ256m:
30014 case VPMADD52LUQZ256mb:
30015 case VPMADD52LUQZ256mbk:
30016 case VPMADD52LUQZ256mbkz:
30017 case VPMADD52LUQZ256mk:
30018 case VPMADD52LUQZ256mkz:
30019 case VPMADD52LUQZ256r:
30020 case VPMADD52LUQZ256rk:
30021 case VPMADD52LUQZ256rkz:
30022 case VPMADD52LUQZm:
30023 case VPMADD52LUQZmb:
30024 case VPMADD52LUQZmbk:
30025 case VPMADD52LUQZmbkz:
30026 case VPMADD52LUQZmk:
30027 case VPMADD52LUQZmkz:
30028 case VPMADD52LUQZr:
30029 case VPMADD52LUQZrk:
30030 case VPMADD52LUQZrkz:
30031 case VPMADD52LUQrm:
30032 case VPMADD52LUQrr:
30033 return true;
30034 }
30035 return false;
30036}
30037
30038bool isVMOVLPD(unsigned Opcode) {
30039 switch (Opcode) {
30040 case VMOVLPDZ128mr:
30041 case VMOVLPDZ128rm:
30042 case VMOVLPDmr:
30043 case VMOVLPDrm:
30044 return true;
30045 }
30046 return false;
30047}
30048
30049bool isVMOVQ(unsigned Opcode) {
30050 switch (Opcode) {
30051 case VMOV64toPQIZrm:
30052 case VMOV64toPQIZrr:
30053 case VMOV64toPQIrm:
30054 case VMOV64toPQIrr:
30055 case VMOVPQI2QIZmr:
30056 case VMOVPQI2QIZrr:
30057 case VMOVPQI2QImr:
30058 case VMOVPQI2QIrr:
30059 case VMOVPQIto64Zmr:
30060 case VMOVPQIto64Zrr:
30061 case VMOVPQIto64mr:
30062 case VMOVPQIto64rr:
30063 case VMOVQI2PQIZrm:
30064 case VMOVQI2PQIrm:
30065 case VMOVZPQILo2PQIZrr:
30066 case VMOVZPQILo2PQIrr:
30067 return true;
30068 }
30069 return false;
30070}
30071
30072bool isVMOVDQU(unsigned Opcode) {
30073 switch (Opcode) {
30074 case VMOVDQUYmr:
30075 case VMOVDQUYrm:
30076 case VMOVDQUYrr:
30077 case VMOVDQUYrr_REV:
30078 case VMOVDQUmr:
30079 case VMOVDQUrm:
30080 case VMOVDQUrr:
30081 case VMOVDQUrr_REV:
30082 return true;
30083 }
30084 return false;
30085}
30086
30087bool isAESENC128KL(unsigned Opcode) {
30088 return Opcode == AESENC128KL;
30089}
30090
30091bool isVFMADDSUB231PS(unsigned Opcode) {
30092 switch (Opcode) {
30093 case VFMADDSUB231PSYm:
30094 case VFMADDSUB231PSYr:
30095 case VFMADDSUB231PSZ128m:
30096 case VFMADDSUB231PSZ128mb:
30097 case VFMADDSUB231PSZ128mbk:
30098 case VFMADDSUB231PSZ128mbkz:
30099 case VFMADDSUB231PSZ128mk:
30100 case VFMADDSUB231PSZ128mkz:
30101 case VFMADDSUB231PSZ128r:
30102 case VFMADDSUB231PSZ128rk:
30103 case VFMADDSUB231PSZ128rkz:
30104 case VFMADDSUB231PSZ256m:
30105 case VFMADDSUB231PSZ256mb:
30106 case VFMADDSUB231PSZ256mbk:
30107 case VFMADDSUB231PSZ256mbkz:
30108 case VFMADDSUB231PSZ256mk:
30109 case VFMADDSUB231PSZ256mkz:
30110 case VFMADDSUB231PSZ256r:
30111 case VFMADDSUB231PSZ256rk:
30112 case VFMADDSUB231PSZ256rkz:
30113 case VFMADDSUB231PSZm:
30114 case VFMADDSUB231PSZmb:
30115 case VFMADDSUB231PSZmbk:
30116 case VFMADDSUB231PSZmbkz:
30117 case VFMADDSUB231PSZmk:
30118 case VFMADDSUB231PSZmkz:
30119 case VFMADDSUB231PSZr:
30120 case VFMADDSUB231PSZrb:
30121 case VFMADDSUB231PSZrbk:
30122 case VFMADDSUB231PSZrbkz:
30123 case VFMADDSUB231PSZrk:
30124 case VFMADDSUB231PSZrkz:
30125 case VFMADDSUB231PSm:
30126 case VFMADDSUB231PSr:
30127 return true;
30128 }
30129 return false;
30130}
30131
30132bool isVFNMSUB213PD(unsigned Opcode) {
30133 switch (Opcode) {
30134 case VFNMSUB213PDYm:
30135 case VFNMSUB213PDYr:
30136 case VFNMSUB213PDZ128m:
30137 case VFNMSUB213PDZ128mb:
30138 case VFNMSUB213PDZ128mbk:
30139 case VFNMSUB213PDZ128mbkz:
30140 case VFNMSUB213PDZ128mk:
30141 case VFNMSUB213PDZ128mkz:
30142 case VFNMSUB213PDZ128r:
30143 case VFNMSUB213PDZ128rk:
30144 case VFNMSUB213PDZ128rkz:
30145 case VFNMSUB213PDZ256m:
30146 case VFNMSUB213PDZ256mb:
30147 case VFNMSUB213PDZ256mbk:
30148 case VFNMSUB213PDZ256mbkz:
30149 case VFNMSUB213PDZ256mk:
30150 case VFNMSUB213PDZ256mkz:
30151 case VFNMSUB213PDZ256r:
30152 case VFNMSUB213PDZ256rk:
30153 case VFNMSUB213PDZ256rkz:
30154 case VFNMSUB213PDZm:
30155 case VFNMSUB213PDZmb:
30156 case VFNMSUB213PDZmbk:
30157 case VFNMSUB213PDZmbkz:
30158 case VFNMSUB213PDZmk:
30159 case VFNMSUB213PDZmkz:
30160 case VFNMSUB213PDZr:
30161 case VFNMSUB213PDZrb:
30162 case VFNMSUB213PDZrbk:
30163 case VFNMSUB213PDZrbkz:
30164 case VFNMSUB213PDZrk:
30165 case VFNMSUB213PDZrkz:
30166 case VFNMSUB213PDm:
30167 case VFNMSUB213PDr:
30168 return true;
30169 }
30170 return false;
30171}
30172
30173bool isVPCONFLICTD(unsigned Opcode) {
30174 switch (Opcode) {
30175 case VPCONFLICTDZ128rm:
30176 case VPCONFLICTDZ128rmb:
30177 case VPCONFLICTDZ128rmbk:
30178 case VPCONFLICTDZ128rmbkz:
30179 case VPCONFLICTDZ128rmk:
30180 case VPCONFLICTDZ128rmkz:
30181 case VPCONFLICTDZ128rr:
30182 case VPCONFLICTDZ128rrk:
30183 case VPCONFLICTDZ128rrkz:
30184 case VPCONFLICTDZ256rm:
30185 case VPCONFLICTDZ256rmb:
30186 case VPCONFLICTDZ256rmbk:
30187 case VPCONFLICTDZ256rmbkz:
30188 case VPCONFLICTDZ256rmk:
30189 case VPCONFLICTDZ256rmkz:
30190 case VPCONFLICTDZ256rr:
30191 case VPCONFLICTDZ256rrk:
30192 case VPCONFLICTDZ256rrkz:
30193 case VPCONFLICTDZrm:
30194 case VPCONFLICTDZrmb:
30195 case VPCONFLICTDZrmbk:
30196 case VPCONFLICTDZrmbkz:
30197 case VPCONFLICTDZrmk:
30198 case VPCONFLICTDZrmkz:
30199 case VPCONFLICTDZrr:
30200 case VPCONFLICTDZrrk:
30201 case VPCONFLICTDZrrkz:
30202 return true;
30203 }
30204 return false;
30205}
30206
30207bool isVFMADDSUB213PH(unsigned Opcode) {
30208 switch (Opcode) {
30209 case VFMADDSUB213PHZ128m:
30210 case VFMADDSUB213PHZ128mb:
30211 case VFMADDSUB213PHZ128mbk:
30212 case VFMADDSUB213PHZ128mbkz:
30213 case VFMADDSUB213PHZ128mk:
30214 case VFMADDSUB213PHZ128mkz:
30215 case VFMADDSUB213PHZ128r:
30216 case VFMADDSUB213PHZ128rk:
30217 case VFMADDSUB213PHZ128rkz:
30218 case VFMADDSUB213PHZ256m:
30219 case VFMADDSUB213PHZ256mb:
30220 case VFMADDSUB213PHZ256mbk:
30221 case VFMADDSUB213PHZ256mbkz:
30222 case VFMADDSUB213PHZ256mk:
30223 case VFMADDSUB213PHZ256mkz:
30224 case VFMADDSUB213PHZ256r:
30225 case VFMADDSUB213PHZ256rk:
30226 case VFMADDSUB213PHZ256rkz:
30227 case VFMADDSUB213PHZm:
30228 case VFMADDSUB213PHZmb:
30229 case VFMADDSUB213PHZmbk:
30230 case VFMADDSUB213PHZmbkz:
30231 case VFMADDSUB213PHZmk:
30232 case VFMADDSUB213PHZmkz:
30233 case VFMADDSUB213PHZr:
30234 case VFMADDSUB213PHZrb:
30235 case VFMADDSUB213PHZrbk:
30236 case VFMADDSUB213PHZrbkz:
30237 case VFMADDSUB213PHZrk:
30238 case VFMADDSUB213PHZrkz:
30239 return true;
30240 }
30241 return false;
30242}
30243
30244bool isVPHSUBSW(unsigned Opcode) {
30245 switch (Opcode) {
30246 case VPHSUBSWYrm:
30247 case VPHSUBSWYrr:
30248 case VPHSUBSWrm:
30249 case VPHSUBSWrr:
30250 return true;
30251 }
30252 return false;
30253}
30254
30255bool isPUNPCKHDQ(unsigned Opcode) {
30256 switch (Opcode) {
30257 case MMX_PUNPCKHDQrm:
30258 case MMX_PUNPCKHDQrr:
30259 case PUNPCKHDQrm:
30260 case PUNPCKHDQrr:
30261 return true;
30262 }
30263 return false;
30264}
30265
30266bool isVSHUFI64X2(unsigned Opcode) {
30267 switch (Opcode) {
30268 case VSHUFI64X2Z256rmbi:
30269 case VSHUFI64X2Z256rmbik:
30270 case VSHUFI64X2Z256rmbikz:
30271 case VSHUFI64X2Z256rmi:
30272 case VSHUFI64X2Z256rmik:
30273 case VSHUFI64X2Z256rmikz:
30274 case VSHUFI64X2Z256rri:
30275 case VSHUFI64X2Z256rrik:
30276 case VSHUFI64X2Z256rrikz:
30277 case VSHUFI64X2Zrmbi:
30278 case VSHUFI64X2Zrmbik:
30279 case VSHUFI64X2Zrmbikz:
30280 case VSHUFI64X2Zrmi:
30281 case VSHUFI64X2Zrmik:
30282 case VSHUFI64X2Zrmikz:
30283 case VSHUFI64X2Zrri:
30284 case VSHUFI64X2Zrrik:
30285 case VSHUFI64X2Zrrikz:
30286 return true;
30287 }
30288 return false;
30289}
30290
30291bool isVFMSUBSD(unsigned Opcode) {
30292 switch (Opcode) {
30293 case VFMSUBSD4mr:
30294 case VFMSUBSD4rm:
30295 case VFMSUBSD4rr:
30296 case VFMSUBSD4rr_REV:
30297 return true;
30298 }
30299 return false;
30300}
30301
30302bool isVPORD(unsigned Opcode) {
30303 switch (Opcode) {
30304 case VPORDZ128rm:
30305 case VPORDZ128rmb:
30306 case VPORDZ128rmbk:
30307 case VPORDZ128rmbkz:
30308 case VPORDZ128rmk:
30309 case VPORDZ128rmkz:
30310 case VPORDZ128rr:
30311 case VPORDZ128rrk:
30312 case VPORDZ128rrkz:
30313 case VPORDZ256rm:
30314 case VPORDZ256rmb:
30315 case VPORDZ256rmbk:
30316 case VPORDZ256rmbkz:
30317 case VPORDZ256rmk:
30318 case VPORDZ256rmkz:
30319 case VPORDZ256rr:
30320 case VPORDZ256rrk:
30321 case VPORDZ256rrkz:
30322 case VPORDZrm:
30323 case VPORDZrmb:
30324 case VPORDZrmbk:
30325 case VPORDZrmbkz:
30326 case VPORDZrmk:
30327 case VPORDZrmkz:
30328 case VPORDZrr:
30329 case VPORDZrrk:
30330 case VPORDZrrkz:
30331 return true;
30332 }
30333 return false;
30334}
30335
30336bool isRCPPS(unsigned Opcode) {
30337 switch (Opcode) {
30338 case RCPPSm:
30339 case RCPPSr:
30340 return true;
30341 }
30342 return false;
30343}
30344
30345bool isVEXTRACTI128(unsigned Opcode) {
30346 switch (Opcode) {
30347 case VEXTRACTI128mri:
30348 case VEXTRACTI128rri:
30349 return true;
30350 }
30351 return false;
30352}
30353
30354bool isVCVT2PH2BF8S(unsigned Opcode) {
30355 switch (Opcode) {
30356 case VCVT2PH2BF8SZ128rm:
30357 case VCVT2PH2BF8SZ128rmb:
30358 case VCVT2PH2BF8SZ128rmbk:
30359 case VCVT2PH2BF8SZ128rmbkz:
30360 case VCVT2PH2BF8SZ128rmk:
30361 case VCVT2PH2BF8SZ128rmkz:
30362 case VCVT2PH2BF8SZ128rr:
30363 case VCVT2PH2BF8SZ128rrk:
30364 case VCVT2PH2BF8SZ128rrkz:
30365 case VCVT2PH2BF8SZ256rm:
30366 case VCVT2PH2BF8SZ256rmb:
30367 case VCVT2PH2BF8SZ256rmbk:
30368 case VCVT2PH2BF8SZ256rmbkz:
30369 case VCVT2PH2BF8SZ256rmk:
30370 case VCVT2PH2BF8SZ256rmkz:
30371 case VCVT2PH2BF8SZ256rr:
30372 case VCVT2PH2BF8SZ256rrk:
30373 case VCVT2PH2BF8SZ256rrkz:
30374 case VCVT2PH2BF8SZrm:
30375 case VCVT2PH2BF8SZrmb:
30376 case VCVT2PH2BF8SZrmbk:
30377 case VCVT2PH2BF8SZrmbkz:
30378 case VCVT2PH2BF8SZrmk:
30379 case VCVT2PH2BF8SZrmkz:
30380 case VCVT2PH2BF8SZrr:
30381 case VCVT2PH2BF8SZrrk:
30382 case VCVT2PH2BF8SZrrkz:
30383 return true;
30384 }
30385 return false;
30386}
30387
30388bool isVPSHRDVW(unsigned Opcode) {
30389 switch (Opcode) {
30390 case VPSHRDVWZ128m:
30391 case VPSHRDVWZ128mk:
30392 case VPSHRDVWZ128mkz:
30393 case VPSHRDVWZ128r:
30394 case VPSHRDVWZ128rk:
30395 case VPSHRDVWZ128rkz:
30396 case VPSHRDVWZ256m:
30397 case VPSHRDVWZ256mk:
30398 case VPSHRDVWZ256mkz:
30399 case VPSHRDVWZ256r:
30400 case VPSHRDVWZ256rk:
30401 case VPSHRDVWZ256rkz:
30402 case VPSHRDVWZm:
30403 case VPSHRDVWZmk:
30404 case VPSHRDVWZmkz:
30405 case VPSHRDVWZr:
30406 case VPSHRDVWZrk:
30407 case VPSHRDVWZrkz:
30408 return true;
30409 }
30410 return false;
30411}
30412
30413bool isVUNPCKLPD(unsigned Opcode) {
30414 switch (Opcode) {
30415 case VUNPCKLPDYrm:
30416 case VUNPCKLPDYrr:
30417 case VUNPCKLPDZ128rm:
30418 case VUNPCKLPDZ128rmb:
30419 case VUNPCKLPDZ128rmbk:
30420 case VUNPCKLPDZ128rmbkz:
30421 case VUNPCKLPDZ128rmk:
30422 case VUNPCKLPDZ128rmkz:
30423 case VUNPCKLPDZ128rr:
30424 case VUNPCKLPDZ128rrk:
30425 case VUNPCKLPDZ128rrkz:
30426 case VUNPCKLPDZ256rm:
30427 case VUNPCKLPDZ256rmb:
30428 case VUNPCKLPDZ256rmbk:
30429 case VUNPCKLPDZ256rmbkz:
30430 case VUNPCKLPDZ256rmk:
30431 case VUNPCKLPDZ256rmkz:
30432 case VUNPCKLPDZ256rr:
30433 case VUNPCKLPDZ256rrk:
30434 case VUNPCKLPDZ256rrkz:
30435 case VUNPCKLPDZrm:
30436 case VUNPCKLPDZrmb:
30437 case VUNPCKLPDZrmbk:
30438 case VUNPCKLPDZrmbkz:
30439 case VUNPCKLPDZrmk:
30440 case VUNPCKLPDZrmkz:
30441 case VUNPCKLPDZrr:
30442 case VUNPCKLPDZrrk:
30443 case VUNPCKLPDZrrkz:
30444 case VUNPCKLPDrm:
30445 case VUNPCKLPDrr:
30446 return true;
30447 }
30448 return false;
30449}
30450
30451bool isVPSRAVD(unsigned Opcode) {
30452 switch (Opcode) {
30453 case VPSRAVDYrm:
30454 case VPSRAVDYrr:
30455 case VPSRAVDZ128rm:
30456 case VPSRAVDZ128rmb:
30457 case VPSRAVDZ128rmbk:
30458 case VPSRAVDZ128rmbkz:
30459 case VPSRAVDZ128rmk:
30460 case VPSRAVDZ128rmkz:
30461 case VPSRAVDZ128rr:
30462 case VPSRAVDZ128rrk:
30463 case VPSRAVDZ128rrkz:
30464 case VPSRAVDZ256rm:
30465 case VPSRAVDZ256rmb:
30466 case VPSRAVDZ256rmbk:
30467 case VPSRAVDZ256rmbkz:
30468 case VPSRAVDZ256rmk:
30469 case VPSRAVDZ256rmkz:
30470 case VPSRAVDZ256rr:
30471 case VPSRAVDZ256rrk:
30472 case VPSRAVDZ256rrkz:
30473 case VPSRAVDZrm:
30474 case VPSRAVDZrmb:
30475 case VPSRAVDZrmbk:
30476 case VPSRAVDZrmbkz:
30477 case VPSRAVDZrmk:
30478 case VPSRAVDZrmkz:
30479 case VPSRAVDZrr:
30480 case VPSRAVDZrrk:
30481 case VPSRAVDZrrkz:
30482 case VPSRAVDrm:
30483 case VPSRAVDrr:
30484 return true;
30485 }
30486 return false;
30487}
30488
30489bool isVMULSH(unsigned Opcode) {
30490 switch (Opcode) {
30491 case VMULSHZrm_Int:
30492 case VMULSHZrmk_Int:
30493 case VMULSHZrmkz_Int:
30494 case VMULSHZrr_Int:
30495 case VMULSHZrrb_Int:
30496 case VMULSHZrrbk_Int:
30497 case VMULSHZrrbkz_Int:
30498 case VMULSHZrrk_Int:
30499 case VMULSHZrrkz_Int:
30500 return true;
30501 }
30502 return false;
30503}
30504
30505bool isMOVNTSS(unsigned Opcode) {
30506 return Opcode == MOVNTSS;
30507}
30508
30509bool isSTI(unsigned Opcode) {
30510 return Opcode == STI;
30511}
30512
30513bool isVSM4RNDS4(unsigned Opcode) {
30514 switch (Opcode) {
30515 case VSM4RNDS4Yrm:
30516 case VSM4RNDS4Yrr:
30517 case VSM4RNDS4Z128rm:
30518 case VSM4RNDS4Z128rr:
30519 case VSM4RNDS4Z256rm:
30520 case VSM4RNDS4Z256rr:
30521 case VSM4RNDS4Zrm:
30522 case VSM4RNDS4Zrr:
30523 case VSM4RNDS4rm:
30524 case VSM4RNDS4rr:
30525 return true;
30526 }
30527 return false;
30528}
30529
30530bool isVMCLEAR(unsigned Opcode) {
30531 return Opcode == VMCLEARm;
30532}
30533
30534bool isVPMADD52HUQ(unsigned Opcode) {
30535 switch (Opcode) {
30536 case VPMADD52HUQYrm:
30537 case VPMADD52HUQYrr:
30538 case VPMADD52HUQZ128m:
30539 case VPMADD52HUQZ128mb:
30540 case VPMADD52HUQZ128mbk:
30541 case VPMADD52HUQZ128mbkz:
30542 case VPMADD52HUQZ128mk:
30543 case VPMADD52HUQZ128mkz:
30544 case VPMADD52HUQZ128r:
30545 case VPMADD52HUQZ128rk:
30546 case VPMADD52HUQZ128rkz:
30547 case VPMADD52HUQZ256m:
30548 case VPMADD52HUQZ256mb:
30549 case VPMADD52HUQZ256mbk:
30550 case VPMADD52HUQZ256mbkz:
30551 case VPMADD52HUQZ256mk:
30552 case VPMADD52HUQZ256mkz:
30553 case VPMADD52HUQZ256r:
30554 case VPMADD52HUQZ256rk:
30555 case VPMADD52HUQZ256rkz:
30556 case VPMADD52HUQZm:
30557 case VPMADD52HUQZmb:
30558 case VPMADD52HUQZmbk:
30559 case VPMADD52HUQZmbkz:
30560 case VPMADD52HUQZmk:
30561 case VPMADD52HUQZmkz:
30562 case VPMADD52HUQZr:
30563 case VPMADD52HUQZrk:
30564 case VPMADD52HUQZrkz:
30565 case VPMADD52HUQrm:
30566 case VPMADD52HUQrr:
30567 return true;
30568 }
30569 return false;
30570}
30571
30572bool isLIDT(unsigned Opcode) {
30573 return Opcode == LIDT64m;
30574}
30575
30576bool isPUSH2(unsigned Opcode) {
30577 return Opcode == PUSH2;
30578}
30579
30580bool isVCVTPS2IUBS(unsigned Opcode) {
30581 switch (Opcode) {
30582 case VCVTPS2IUBSZ128rm:
30583 case VCVTPS2IUBSZ128rmb:
30584 case VCVTPS2IUBSZ128rmbk:
30585 case VCVTPS2IUBSZ128rmbkz:
30586 case VCVTPS2IUBSZ128rmk:
30587 case VCVTPS2IUBSZ128rmkz:
30588 case VCVTPS2IUBSZ128rr:
30589 case VCVTPS2IUBSZ128rrk:
30590 case VCVTPS2IUBSZ128rrkz:
30591 case VCVTPS2IUBSZ256rm:
30592 case VCVTPS2IUBSZ256rmb:
30593 case VCVTPS2IUBSZ256rmbk:
30594 case VCVTPS2IUBSZ256rmbkz:
30595 case VCVTPS2IUBSZ256rmk:
30596 case VCVTPS2IUBSZ256rmkz:
30597 case VCVTPS2IUBSZ256rr:
30598 case VCVTPS2IUBSZ256rrk:
30599 case VCVTPS2IUBSZ256rrkz:
30600 case VCVTPS2IUBSZrm:
30601 case VCVTPS2IUBSZrmb:
30602 case VCVTPS2IUBSZrmbk:
30603 case VCVTPS2IUBSZrmbkz:
30604 case VCVTPS2IUBSZrmk:
30605 case VCVTPS2IUBSZrmkz:
30606 case VCVTPS2IUBSZrr:
30607 case VCVTPS2IUBSZrrb:
30608 case VCVTPS2IUBSZrrbk:
30609 case VCVTPS2IUBSZrrbkz:
30610 case VCVTPS2IUBSZrrk:
30611 case VCVTPS2IUBSZrrkz:
30612 return true;
30613 }
30614 return false;
30615}
30616
30617bool isRDPKRU(unsigned Opcode) {
30618 return Opcode == RDPKRUr;
30619}
30620
30621bool isVPCMPB(unsigned Opcode) {
30622 switch (Opcode) {
30623 case VPCMPBZ128rmi:
30624 case VPCMPBZ128rmik:
30625 case VPCMPBZ128rri:
30626 case VPCMPBZ128rrik:
30627 case VPCMPBZ256rmi:
30628 case VPCMPBZ256rmik:
30629 case VPCMPBZ256rri:
30630 case VPCMPBZ256rrik:
30631 case VPCMPBZrmi:
30632 case VPCMPBZrmik:
30633 case VPCMPBZrri:
30634 case VPCMPBZrrik:
30635 return true;
30636 }
30637 return false;
30638}
30639
30640bool isVFMSUB231BF16(unsigned Opcode) {
30641 switch (Opcode) {
30642 case VFMSUB231BF16Z128m:
30643 case VFMSUB231BF16Z128mb:
30644 case VFMSUB231BF16Z128mbk:
30645 case VFMSUB231BF16Z128mbkz:
30646 case VFMSUB231BF16Z128mk:
30647 case VFMSUB231BF16Z128mkz:
30648 case VFMSUB231BF16Z128r:
30649 case VFMSUB231BF16Z128rk:
30650 case VFMSUB231BF16Z128rkz:
30651 case VFMSUB231BF16Z256m:
30652 case VFMSUB231BF16Z256mb:
30653 case VFMSUB231BF16Z256mbk:
30654 case VFMSUB231BF16Z256mbkz:
30655 case VFMSUB231BF16Z256mk:
30656 case VFMSUB231BF16Z256mkz:
30657 case VFMSUB231BF16Z256r:
30658 case VFMSUB231BF16Z256rk:
30659 case VFMSUB231BF16Z256rkz:
30660 case VFMSUB231BF16Zm:
30661 case VFMSUB231BF16Zmb:
30662 case VFMSUB231BF16Zmbk:
30663 case VFMSUB231BF16Zmbkz:
30664 case VFMSUB231BF16Zmk:
30665 case VFMSUB231BF16Zmkz:
30666 case VFMSUB231BF16Zr:
30667 case VFMSUB231BF16Zrk:
30668 case VFMSUB231BF16Zrkz:
30669 return true;
30670 }
30671 return false;
30672}
30673
30674bool isFINCSTP(unsigned Opcode) {
30675 return Opcode == FINCSTP;
30676}
30677
30678bool isKORQ(unsigned Opcode) {
30679 return Opcode == KORQkk;
30680}
30681
30682bool isXCRYPTCBC(unsigned Opcode) {
30683 return Opcode == XCRYPTCBC;
30684}
30685
30686bool isRDPMC(unsigned Opcode) {
30687 return Opcode == RDPMC;
30688}
30689
30690bool isMOVMSKPD(unsigned Opcode) {
30691 return Opcode == MOVMSKPDrr;
30692}
30693
30694bool isVFMSUB231SH(unsigned Opcode) {
30695 switch (Opcode) {
30696 case VFMSUB231SHZm_Int:
30697 case VFMSUB231SHZmk_Int:
30698 case VFMSUB231SHZmkz_Int:
30699 case VFMSUB231SHZr_Int:
30700 case VFMSUB231SHZrb_Int:
30701 case VFMSUB231SHZrbk_Int:
30702 case VFMSUB231SHZrbkz_Int:
30703 case VFMSUB231SHZrk_Int:
30704 case VFMSUB231SHZrkz_Int:
30705 return true;
30706 }
30707 return false;
30708}
30709
30710bool isVEXTRACTF128(unsigned Opcode) {
30711 switch (Opcode) {
30712 case VEXTRACTF128mri:
30713 case VEXTRACTF128rri:
30714 return true;
30715 }
30716 return false;
30717}
30718
30719bool isVPSHLB(unsigned Opcode) {
30720 switch (Opcode) {
30721 case VPSHLBmr:
30722 case VPSHLBrm:
30723 case VPSHLBrr:
30724 case VPSHLBrr_REV:
30725 return true;
30726 }
30727 return false;
30728}
30729
30730bool isXSAVES64(unsigned Opcode) {
30731 return Opcode == XSAVES64;
30732}
30733
30734bool isSHL(unsigned Opcode) {
30735 switch (Opcode) {
30736 case SHL16m1:
30737 case SHL16m1_EVEX:
30738 case SHL16m1_ND:
30739 case SHL16m1_NF:
30740 case SHL16m1_NF_ND:
30741 case SHL16mCL:
30742 case SHL16mCL_EVEX:
30743 case SHL16mCL_ND:
30744 case SHL16mCL_NF:
30745 case SHL16mCL_NF_ND:
30746 case SHL16mi:
30747 case SHL16mi_EVEX:
30748 case SHL16mi_ND:
30749 case SHL16mi_NF:
30750 case SHL16mi_NF_ND:
30751 case SHL16r1:
30752 case SHL16r1_EVEX:
30753 case SHL16r1_ND:
30754 case SHL16r1_NF:
30755 case SHL16r1_NF_ND:
30756 case SHL16rCL:
30757 case SHL16rCL_EVEX:
30758 case SHL16rCL_ND:
30759 case SHL16rCL_NF:
30760 case SHL16rCL_NF_ND:
30761 case SHL16ri:
30762 case SHL16ri_EVEX:
30763 case SHL16ri_ND:
30764 case SHL16ri_NF:
30765 case SHL16ri_NF_ND:
30766 case SHL32m1:
30767 case SHL32m1_EVEX:
30768 case SHL32m1_ND:
30769 case SHL32m1_NF:
30770 case SHL32m1_NF_ND:
30771 case SHL32mCL:
30772 case SHL32mCL_EVEX:
30773 case SHL32mCL_ND:
30774 case SHL32mCL_NF:
30775 case SHL32mCL_NF_ND:
30776 case SHL32mi:
30777 case SHL32mi_EVEX:
30778 case SHL32mi_ND:
30779 case SHL32mi_NF:
30780 case SHL32mi_NF_ND:
30781 case SHL32r1:
30782 case SHL32r1_EVEX:
30783 case SHL32r1_ND:
30784 case SHL32r1_NF:
30785 case SHL32r1_NF_ND:
30786 case SHL32rCL:
30787 case SHL32rCL_EVEX:
30788 case SHL32rCL_ND:
30789 case SHL32rCL_NF:
30790 case SHL32rCL_NF_ND:
30791 case SHL32ri:
30792 case SHL32ri_EVEX:
30793 case SHL32ri_ND:
30794 case SHL32ri_NF:
30795 case SHL32ri_NF_ND:
30796 case SHL64m1:
30797 case SHL64m1_EVEX:
30798 case SHL64m1_ND:
30799 case SHL64m1_NF:
30800 case SHL64m1_NF_ND:
30801 case SHL64mCL:
30802 case SHL64mCL_EVEX:
30803 case SHL64mCL_ND:
30804 case SHL64mCL_NF:
30805 case SHL64mCL_NF_ND:
30806 case SHL64mi:
30807 case SHL64mi_EVEX:
30808 case SHL64mi_ND:
30809 case SHL64mi_NF:
30810 case SHL64mi_NF_ND:
30811 case SHL64r1:
30812 case SHL64r1_EVEX:
30813 case SHL64r1_ND:
30814 case SHL64r1_NF:
30815 case SHL64r1_NF_ND:
30816 case SHL64rCL:
30817 case SHL64rCL_EVEX:
30818 case SHL64rCL_ND:
30819 case SHL64rCL_NF:
30820 case SHL64rCL_NF_ND:
30821 case SHL64ri:
30822 case SHL64ri_EVEX:
30823 case SHL64ri_ND:
30824 case SHL64ri_NF:
30825 case SHL64ri_NF_ND:
30826 case SHL8m1:
30827 case SHL8m1_EVEX:
30828 case SHL8m1_ND:
30829 case SHL8m1_NF:
30830 case SHL8m1_NF_ND:
30831 case SHL8mCL:
30832 case SHL8mCL_EVEX:
30833 case SHL8mCL_ND:
30834 case SHL8mCL_NF:
30835 case SHL8mCL_NF_ND:
30836 case SHL8mi:
30837 case SHL8mi_EVEX:
30838 case SHL8mi_ND:
30839 case SHL8mi_NF:
30840 case SHL8mi_NF_ND:
30841 case SHL8r1:
30842 case SHL8r1_EVEX:
30843 case SHL8r1_ND:
30844 case SHL8r1_NF:
30845 case SHL8r1_NF_ND:
30846 case SHL8rCL:
30847 case SHL8rCL_EVEX:
30848 case SHL8rCL_ND:
30849 case SHL8rCL_NF:
30850 case SHL8rCL_NF_ND:
30851 case SHL8ri:
30852 case SHL8ri_EVEX:
30853 case SHL8ri_ND:
30854 case SHL8ri_NF:
30855 case SHL8ri_NF_ND:
30856 return true;
30857 }
30858 return false;
30859}
30860
30861bool isAXOR(unsigned Opcode) {
30862 switch (Opcode) {
30863 case AXOR32mr:
30864 case AXOR32mr_EVEX:
30865 case AXOR64mr:
30866 case AXOR64mr_EVEX:
30867 return true;
30868 }
30869 return false;
30870}
30871
30872bool isVINSERTI64X2(unsigned Opcode) {
30873 switch (Opcode) {
30874 case VINSERTI64X2Z256rmi:
30875 case VINSERTI64X2Z256rmik:
30876 case VINSERTI64X2Z256rmikz:
30877 case VINSERTI64X2Z256rri:
30878 case VINSERTI64X2Z256rrik:
30879 case VINSERTI64X2Z256rrikz:
30880 case VINSERTI64X2Zrmi:
30881 case VINSERTI64X2Zrmik:
30882 case VINSERTI64X2Zrmikz:
30883 case VINSERTI64X2Zrri:
30884 case VINSERTI64X2Zrrik:
30885 case VINSERTI64X2Zrrikz:
30886 return true;
30887 }
30888 return false;
30889}
30890
30891bool isSYSRETQ(unsigned Opcode) {
30892 return Opcode == SYSRET64;
30893}
30894
30895bool isVSCATTERPF0QPD(unsigned Opcode) {
30896 return Opcode == VSCATTERPF0QPDm;
30897}
30898
30899bool isVFMSUB213SH(unsigned Opcode) {
30900 switch (Opcode) {
30901 case VFMSUB213SHZm_Int:
30902 case VFMSUB213SHZmk_Int:
30903 case VFMSUB213SHZmkz_Int:
30904 case VFMSUB213SHZr_Int:
30905 case VFMSUB213SHZrb_Int:
30906 case VFMSUB213SHZrbk_Int:
30907 case VFMSUB213SHZrbkz_Int:
30908 case VFMSUB213SHZrk_Int:
30909 case VFMSUB213SHZrkz_Int:
30910 return true;
30911 }
30912 return false;
30913}
30914
30915bool isVPMOVQW(unsigned Opcode) {
30916 switch (Opcode) {
30917 case VPMOVQWZ128mr:
30918 case VPMOVQWZ128mrk:
30919 case VPMOVQWZ128rr:
30920 case VPMOVQWZ128rrk:
30921 case VPMOVQWZ128rrkz:
30922 case VPMOVQWZ256mr:
30923 case VPMOVQWZ256mrk:
30924 case VPMOVQWZ256rr:
30925 case VPMOVQWZ256rrk:
30926 case VPMOVQWZ256rrkz:
30927 case VPMOVQWZmr:
30928 case VPMOVQWZmrk:
30929 case VPMOVQWZrr:
30930 case VPMOVQWZrrk:
30931 case VPMOVQWZrrkz:
30932 return true;
30933 }
30934 return false;
30935}
30936
30937bool isVREDUCEPD(unsigned Opcode) {
30938 switch (Opcode) {
30939 case VREDUCEPDZ128rmbi:
30940 case VREDUCEPDZ128rmbik:
30941 case VREDUCEPDZ128rmbikz:
30942 case VREDUCEPDZ128rmi:
30943 case VREDUCEPDZ128rmik:
30944 case VREDUCEPDZ128rmikz:
30945 case VREDUCEPDZ128rri:
30946 case VREDUCEPDZ128rrik:
30947 case VREDUCEPDZ128rrikz:
30948 case VREDUCEPDZ256rmbi:
30949 case VREDUCEPDZ256rmbik:
30950 case VREDUCEPDZ256rmbikz:
30951 case VREDUCEPDZ256rmi:
30952 case VREDUCEPDZ256rmik:
30953 case VREDUCEPDZ256rmikz:
30954 case VREDUCEPDZ256rri:
30955 case VREDUCEPDZ256rrik:
30956 case VREDUCEPDZ256rrikz:
30957 case VREDUCEPDZrmbi:
30958 case VREDUCEPDZrmbik:
30959 case VREDUCEPDZrmbikz:
30960 case VREDUCEPDZrmi:
30961 case VREDUCEPDZrmik:
30962 case VREDUCEPDZrmikz:
30963 case VREDUCEPDZrri:
30964 case VREDUCEPDZrrib:
30965 case VREDUCEPDZrribk:
30966 case VREDUCEPDZrribkz:
30967 case VREDUCEPDZrrik:
30968 case VREDUCEPDZrrikz:
30969 return true;
30970 }
30971 return false;
30972}
30973
30974bool isNOT(unsigned Opcode) {
30975 switch (Opcode) {
30976 case NOT16m:
30977 case NOT16m_EVEX:
30978 case NOT16m_ND:
30979 case NOT16r:
30980 case NOT16r_EVEX:
30981 case NOT16r_ND:
30982 case NOT32m:
30983 case NOT32m_EVEX:
30984 case NOT32m_ND:
30985 case NOT32r:
30986 case NOT32r_EVEX:
30987 case NOT32r_ND:
30988 case NOT64m:
30989 case NOT64m_EVEX:
30990 case NOT64m_ND:
30991 case NOT64r:
30992 case NOT64r_EVEX:
30993 case NOT64r_ND:
30994 case NOT8m:
30995 case NOT8m_EVEX:
30996 case NOT8m_ND:
30997 case NOT8r:
30998 case NOT8r_EVEX:
30999 case NOT8r_ND:
31000 return true;
31001 }
31002 return false;
31003}
31004
31005bool isLWPINS(unsigned Opcode) {
31006 switch (Opcode) {
31007 case LWPINS32rmi:
31008 case LWPINS32rri:
31009 case LWPINS64rmi:
31010 case LWPINS64rri:
31011 return true;
31012 }
31013 return false;
31014}
31015
31016bool isVSCATTERDPS(unsigned Opcode) {
31017 switch (Opcode) {
31018 case VSCATTERDPSZ128mr:
31019 case VSCATTERDPSZ256mr:
31020 case VSCATTERDPSZmr:
31021 return true;
31022 }
31023 return false;
31024}
31025
31026bool isVPMOVM2W(unsigned Opcode) {
31027 switch (Opcode) {
31028 case VPMOVM2WZ128rk:
31029 case VPMOVM2WZ256rk:
31030 case VPMOVM2WZrk:
31031 return true;
31032 }
31033 return false;
31034}
31035
31036bool isVFNMADD132PS(unsigned Opcode) {
31037 switch (Opcode) {
31038 case VFNMADD132PSYm:
31039 case VFNMADD132PSYr:
31040 case VFNMADD132PSZ128m:
31041 case VFNMADD132PSZ128mb:
31042 case VFNMADD132PSZ128mbk:
31043 case VFNMADD132PSZ128mbkz:
31044 case VFNMADD132PSZ128mk:
31045 case VFNMADD132PSZ128mkz:
31046 case VFNMADD132PSZ128r:
31047 case VFNMADD132PSZ128rk:
31048 case VFNMADD132PSZ128rkz:
31049 case VFNMADD132PSZ256m:
31050 case VFNMADD132PSZ256mb:
31051 case VFNMADD132PSZ256mbk:
31052 case VFNMADD132PSZ256mbkz:
31053 case VFNMADD132PSZ256mk:
31054 case VFNMADD132PSZ256mkz:
31055 case VFNMADD132PSZ256r:
31056 case VFNMADD132PSZ256rk:
31057 case VFNMADD132PSZ256rkz:
31058 case VFNMADD132PSZm:
31059 case VFNMADD132PSZmb:
31060 case VFNMADD132PSZmbk:
31061 case VFNMADD132PSZmbkz:
31062 case VFNMADD132PSZmk:
31063 case VFNMADD132PSZmkz:
31064 case VFNMADD132PSZr:
31065 case VFNMADD132PSZrb:
31066 case VFNMADD132PSZrbk:
31067 case VFNMADD132PSZrbkz:
31068 case VFNMADD132PSZrk:
31069 case VFNMADD132PSZrkz:
31070 case VFNMADD132PSm:
31071 case VFNMADD132PSr:
31072 return true;
31073 }
31074 return false;
31075}
31076
31077bool isMOVNTPS(unsigned Opcode) {
31078 return Opcode == MOVNTPSmr;
31079}
31080
31081bool isVRSQRTSS(unsigned Opcode) {
31082 switch (Opcode) {
31083 case VRSQRTSSm_Int:
31084 case VRSQRTSSr_Int:
31085 return true;
31086 }
31087 return false;
31088}
31089
31090bool isKMOVB(unsigned Opcode) {
31091 switch (Opcode) {
31092 case KMOVBkk:
31093 case KMOVBkk_EVEX:
31094 case KMOVBkm:
31095 case KMOVBkm_EVEX:
31096 case KMOVBkr:
31097 case KMOVBkr_EVEX:
31098 case KMOVBmk:
31099 case KMOVBmk_EVEX:
31100 case KMOVBrk:
31101 case KMOVBrk_EVEX:
31102 return true;
31103 }
31104 return false;
31105}
31106
31107bool isCVTSD2SS(unsigned Opcode) {
31108 switch (Opcode) {
31109 case CVTSD2SSrm_Int:
31110 case CVTSD2SSrr_Int:
31111 return true;
31112 }
31113 return false;
31114}
31115
31116bool isVBROADCASTF64X2(unsigned Opcode) {
31117 switch (Opcode) {
31118 case VBROADCASTF64X2Z256rm:
31119 case VBROADCASTF64X2Z256rmk:
31120 case VBROADCASTF64X2Z256rmkz:
31121 case VBROADCASTF64X2Zrm:
31122 case VBROADCASTF64X2Zrmk:
31123 case VBROADCASTF64X2Zrmkz:
31124 return true;
31125 }
31126 return false;
31127}
31128
31129bool isMOVNTPD(unsigned Opcode) {
31130 return Opcode == MOVNTPDmr;
31131}
31132
31133bool isMAXSD(unsigned Opcode) {
31134 switch (Opcode) {
31135 case MAXSDrm_Int:
31136 case MAXSDrr_Int:
31137 return true;
31138 }
31139 return false;
31140}
31141
31142bool isCMPPD(unsigned Opcode) {
31143 switch (Opcode) {
31144 case CMPPDrmi:
31145 case CMPPDrri:
31146 return true;
31147 }
31148 return false;
31149}
31150
31151bool isVPCMPESTRM(unsigned Opcode) {
31152 switch (Opcode) {
31153 case VPCMPESTRMrmi:
31154 case VPCMPESTRMrri:
31155 return true;
31156 }
31157 return false;
31158}
31159
31160bool isVFMSUB132PS(unsigned Opcode) {
31161 switch (Opcode) {
31162 case VFMSUB132PSYm:
31163 case VFMSUB132PSYr:
31164 case VFMSUB132PSZ128m:
31165 case VFMSUB132PSZ128mb:
31166 case VFMSUB132PSZ128mbk:
31167 case VFMSUB132PSZ128mbkz:
31168 case VFMSUB132PSZ128mk:
31169 case VFMSUB132PSZ128mkz:
31170 case VFMSUB132PSZ128r:
31171 case VFMSUB132PSZ128rk:
31172 case VFMSUB132PSZ128rkz:
31173 case VFMSUB132PSZ256m:
31174 case VFMSUB132PSZ256mb:
31175 case VFMSUB132PSZ256mbk:
31176 case VFMSUB132PSZ256mbkz:
31177 case VFMSUB132PSZ256mk:
31178 case VFMSUB132PSZ256mkz:
31179 case VFMSUB132PSZ256r:
31180 case VFMSUB132PSZ256rk:
31181 case VFMSUB132PSZ256rkz:
31182 case VFMSUB132PSZm:
31183 case VFMSUB132PSZmb:
31184 case VFMSUB132PSZmbk:
31185 case VFMSUB132PSZmbkz:
31186 case VFMSUB132PSZmk:
31187 case VFMSUB132PSZmkz:
31188 case VFMSUB132PSZr:
31189 case VFMSUB132PSZrb:
31190 case VFMSUB132PSZrbk:
31191 case VFMSUB132PSZrbkz:
31192 case VFMSUB132PSZrk:
31193 case VFMSUB132PSZrkz:
31194 case VFMSUB132PSm:
31195 case VFMSUB132PSr:
31196 return true;
31197 }
31198 return false;
31199}
31200
31201bool isVCOMISH(unsigned Opcode) {
31202 switch (Opcode) {
31203 case VCOMISHZrm:
31204 case VCOMISHZrr:
31205 case VCOMISHZrrb:
31206 return true;
31207 }
31208 return false;
31209}
31210
31211bool isF2XM1(unsigned Opcode) {
31212 return Opcode == F2XM1;
31213}
31214
31215bool isVDIVBF16(unsigned Opcode) {
31216 switch (Opcode) {
31217 case VDIVBF16Z128rm:
31218 case VDIVBF16Z128rmb:
31219 case VDIVBF16Z128rmbk:
31220 case VDIVBF16Z128rmbkz:
31221 case VDIVBF16Z128rmk:
31222 case VDIVBF16Z128rmkz:
31223 case VDIVBF16Z128rr:
31224 case VDIVBF16Z128rrk:
31225 case VDIVBF16Z128rrkz:
31226 case VDIVBF16Z256rm:
31227 case VDIVBF16Z256rmb:
31228 case VDIVBF16Z256rmbk:
31229 case VDIVBF16Z256rmbkz:
31230 case VDIVBF16Z256rmk:
31231 case VDIVBF16Z256rmkz:
31232 case VDIVBF16Z256rr:
31233 case VDIVBF16Z256rrk:
31234 case VDIVBF16Z256rrkz:
31235 case VDIVBF16Zrm:
31236 case VDIVBF16Zrmb:
31237 case VDIVBF16Zrmbk:
31238 case VDIVBF16Zrmbkz:
31239 case VDIVBF16Zrmk:
31240 case VDIVBF16Zrmkz:
31241 case VDIVBF16Zrr:
31242 case VDIVBF16Zrrk:
31243 case VDIVBF16Zrrkz:
31244 return true;
31245 }
31246 return false;
31247}
31248
31249bool isSQRTPD(unsigned Opcode) {
31250 switch (Opcode) {
31251 case SQRTPDm:
31252 case SQRTPDr:
31253 return true;
31254 }
31255 return false;
31256}
31257
31258bool isVFMSUBADDPS(unsigned Opcode) {
31259 switch (Opcode) {
31260 case VFMSUBADDPS4Ymr:
31261 case VFMSUBADDPS4Yrm:
31262 case VFMSUBADDPS4Yrr:
31263 case VFMSUBADDPS4Yrr_REV:
31264 case VFMSUBADDPS4mr:
31265 case VFMSUBADDPS4rm:
31266 case VFMSUBADDPS4rr:
31267 case VFMSUBADDPS4rr_REV:
31268 return true;
31269 }
31270 return false;
31271}
31272
31273bool isFXTRACT(unsigned Opcode) {
31274 return Opcode == FXTRACT;
31275}
31276
31277bool isVP4DPWSSD(unsigned Opcode) {
31278 switch (Opcode) {
31279 case VP4DPWSSDrm:
31280 case VP4DPWSSDrmk:
31281 case VP4DPWSSDrmkz:
31282 return true;
31283 }
31284 return false;
31285}
31286
31287bool isTDPBHF8PS(unsigned Opcode) {
31288 return Opcode == TDPBHF8PS;
31289}
31290
31291bool isVFMSUBADDPD(unsigned Opcode) {
31292 switch (Opcode) {
31293 case VFMSUBADDPD4Ymr:
31294 case VFMSUBADDPD4Yrm:
31295 case VFMSUBADDPD4Yrr:
31296 case VFMSUBADDPD4Yrr_REV:
31297 case VFMSUBADDPD4mr:
31298 case VFMSUBADDPD4rm:
31299 case VFMSUBADDPD4rr:
31300 case VFMSUBADDPD4rr_REV:
31301 return true;
31302 }
31303 return false;
31304}
31305
31306bool isVBCSTNEBF162PS(unsigned Opcode) {
31307 switch (Opcode) {
31308 case VBCSTNEBF162PSYrm:
31309 case VBCSTNEBF162PSrm:
31310 return true;
31311 }
31312 return false;
31313}
31314
31315bool isVPGATHERQQ(unsigned Opcode) {
31316 switch (Opcode) {
31317 case VPGATHERQQYrm:
31318 case VPGATHERQQZ128rm:
31319 case VPGATHERQQZ256rm:
31320 case VPGATHERQQZrm:
31321 case VPGATHERQQrm:
31322 return true;
31323 }
31324 return false;
31325}
31326
31327bool isPCMPEQB(unsigned Opcode) {
31328 switch (Opcode) {
31329 case MMX_PCMPEQBrm:
31330 case MMX_PCMPEQBrr:
31331 case PCMPEQBrm:
31332 case PCMPEQBrr:
31333 return true;
31334 }
31335 return false;
31336}
31337
31338bool isTILESTORED(unsigned Opcode) {
31339 switch (Opcode) {
31340 case TILESTORED:
31341 case TILESTORED_EVEX:
31342 return true;
31343 }
31344 return false;
31345}
31346
31347bool isBLSMSK(unsigned Opcode) {
31348 switch (Opcode) {
31349 case BLSMSK32rm:
31350 case BLSMSK32rm_EVEX:
31351 case BLSMSK32rm_NF:
31352 case BLSMSK32rr:
31353 case BLSMSK32rr_EVEX:
31354 case BLSMSK32rr_NF:
31355 case BLSMSK64rm:
31356 case BLSMSK64rm_EVEX:
31357 case BLSMSK64rm_NF:
31358 case BLSMSK64rr:
31359 case BLSMSK64rr_EVEX:
31360 case BLSMSK64rr_NF:
31361 return true;
31362 }
31363 return false;
31364}
31365
31366bool isVCVTTPS2DQ(unsigned Opcode) {
31367 switch (Opcode) {
31368 case VCVTTPS2DQYrm:
31369 case VCVTTPS2DQYrr:
31370 case VCVTTPS2DQZ128rm:
31371 case VCVTTPS2DQZ128rmb:
31372 case VCVTTPS2DQZ128rmbk:
31373 case VCVTTPS2DQZ128rmbkz:
31374 case VCVTTPS2DQZ128rmk:
31375 case VCVTTPS2DQZ128rmkz:
31376 case VCVTTPS2DQZ128rr:
31377 case VCVTTPS2DQZ128rrk:
31378 case VCVTTPS2DQZ128rrkz:
31379 case VCVTTPS2DQZ256rm:
31380 case VCVTTPS2DQZ256rmb:
31381 case VCVTTPS2DQZ256rmbk:
31382 case VCVTTPS2DQZ256rmbkz:
31383 case VCVTTPS2DQZ256rmk:
31384 case VCVTTPS2DQZ256rmkz:
31385 case VCVTTPS2DQZ256rr:
31386 case VCVTTPS2DQZ256rrk:
31387 case VCVTTPS2DQZ256rrkz:
31388 case VCVTTPS2DQZrm:
31389 case VCVTTPS2DQZrmb:
31390 case VCVTTPS2DQZrmbk:
31391 case VCVTTPS2DQZrmbkz:
31392 case VCVTTPS2DQZrmk:
31393 case VCVTTPS2DQZrmkz:
31394 case VCVTTPS2DQZrr:
31395 case VCVTTPS2DQZrrb:
31396 case VCVTTPS2DQZrrbk:
31397 case VCVTTPS2DQZrrbkz:
31398 case VCVTTPS2DQZrrk:
31399 case VCVTTPS2DQZrrkz:
31400 case VCVTTPS2DQrm:
31401 case VCVTTPS2DQrr:
31402 return true;
31403 }
31404 return false;
31405}
31406
31407bool isVRNDSCALEPD(unsigned Opcode) {
31408 switch (Opcode) {
31409 case VRNDSCALEPDZ128rmbi:
31410 case VRNDSCALEPDZ128rmbik:
31411 case VRNDSCALEPDZ128rmbikz:
31412 case VRNDSCALEPDZ128rmi:
31413 case VRNDSCALEPDZ128rmik:
31414 case VRNDSCALEPDZ128rmikz:
31415 case VRNDSCALEPDZ128rri:
31416 case VRNDSCALEPDZ128rrik:
31417 case VRNDSCALEPDZ128rrikz:
31418 case VRNDSCALEPDZ256rmbi:
31419 case VRNDSCALEPDZ256rmbik:
31420 case VRNDSCALEPDZ256rmbikz:
31421 case VRNDSCALEPDZ256rmi:
31422 case VRNDSCALEPDZ256rmik:
31423 case VRNDSCALEPDZ256rmikz:
31424 case VRNDSCALEPDZ256rri:
31425 case VRNDSCALEPDZ256rrik:
31426 case VRNDSCALEPDZ256rrikz:
31427 case VRNDSCALEPDZrmbi:
31428 case VRNDSCALEPDZrmbik:
31429 case VRNDSCALEPDZrmbikz:
31430 case VRNDSCALEPDZrmi:
31431 case VRNDSCALEPDZrmik:
31432 case VRNDSCALEPDZrmikz:
31433 case VRNDSCALEPDZrri:
31434 case VRNDSCALEPDZrrib:
31435 case VRNDSCALEPDZrribk:
31436 case VRNDSCALEPDZrribkz:
31437 case VRNDSCALEPDZrrik:
31438 case VRNDSCALEPDZrrikz:
31439 return true;
31440 }
31441 return false;
31442}
31443
31444bool isVFPCLASSBF16(unsigned Opcode) {
31445 switch (Opcode) {
31446 case VFPCLASSBF16Z128mbi:
31447 case VFPCLASSBF16Z128mbik:
31448 case VFPCLASSBF16Z128mi:
31449 case VFPCLASSBF16Z128mik:
31450 case VFPCLASSBF16Z128ri:
31451 case VFPCLASSBF16Z128rik:
31452 case VFPCLASSBF16Z256mbi:
31453 case VFPCLASSBF16Z256mbik:
31454 case VFPCLASSBF16Z256mi:
31455 case VFPCLASSBF16Z256mik:
31456 case VFPCLASSBF16Z256ri:
31457 case VFPCLASSBF16Z256rik:
31458 case VFPCLASSBF16Zmbi:
31459 case VFPCLASSBF16Zmbik:
31460 case VFPCLASSBF16Zmi:
31461 case VFPCLASSBF16Zmik:
31462 case VFPCLASSBF16Zri:
31463 case VFPCLASSBF16Zrik:
31464 return true;
31465 }
31466 return false;
31467}
31468
31469bool isVMLOAD(unsigned Opcode) {
31470 switch (Opcode) {
31471 case VMLOAD32:
31472 case VMLOAD64:
31473 return true;
31474 }
31475 return false;
31476}
31477
31478bool isVPTERNLOGQ(unsigned Opcode) {
31479 switch (Opcode) {
31480 case VPTERNLOGQZ128rmbi:
31481 case VPTERNLOGQZ128rmbik:
31482 case VPTERNLOGQZ128rmbikz:
31483 case VPTERNLOGQZ128rmi:
31484 case VPTERNLOGQZ128rmik:
31485 case VPTERNLOGQZ128rmikz:
31486 case VPTERNLOGQZ128rri:
31487 case VPTERNLOGQZ128rrik:
31488 case VPTERNLOGQZ128rrikz:
31489 case VPTERNLOGQZ256rmbi:
31490 case VPTERNLOGQZ256rmbik:
31491 case VPTERNLOGQZ256rmbikz:
31492 case VPTERNLOGQZ256rmi:
31493 case VPTERNLOGQZ256rmik:
31494 case VPTERNLOGQZ256rmikz:
31495 case VPTERNLOGQZ256rri:
31496 case VPTERNLOGQZ256rrik:
31497 case VPTERNLOGQZ256rrikz:
31498 case VPTERNLOGQZrmbi:
31499 case VPTERNLOGQZrmbik:
31500 case VPTERNLOGQZrmbikz:
31501 case VPTERNLOGQZrmi:
31502 case VPTERNLOGQZrmik:
31503 case VPTERNLOGQZrmikz:
31504 case VPTERNLOGQZrri:
31505 case VPTERNLOGQZrrik:
31506 case VPTERNLOGQZrrikz:
31507 return true;
31508 }
31509 return false;
31510}
31511
31512bool isKXNORD(unsigned Opcode) {
31513 return Opcode == KXNORDkk;
31514}
31515
31516bool isFXSAVE(unsigned Opcode) {
31517 return Opcode == FXSAVE;
31518}
31519
31520bool isVUNPCKHPD(unsigned Opcode) {
31521 switch (Opcode) {
31522 case VUNPCKHPDYrm:
31523 case VUNPCKHPDYrr:
31524 case VUNPCKHPDZ128rm:
31525 case VUNPCKHPDZ128rmb:
31526 case VUNPCKHPDZ128rmbk:
31527 case VUNPCKHPDZ128rmbkz:
31528 case VUNPCKHPDZ128rmk:
31529 case VUNPCKHPDZ128rmkz:
31530 case VUNPCKHPDZ128rr:
31531 case VUNPCKHPDZ128rrk:
31532 case VUNPCKHPDZ128rrkz:
31533 case VUNPCKHPDZ256rm:
31534 case VUNPCKHPDZ256rmb:
31535 case VUNPCKHPDZ256rmbk:
31536 case VUNPCKHPDZ256rmbkz:
31537 case VUNPCKHPDZ256rmk:
31538 case VUNPCKHPDZ256rmkz:
31539 case VUNPCKHPDZ256rr:
31540 case VUNPCKHPDZ256rrk:
31541 case VUNPCKHPDZ256rrkz:
31542 case VUNPCKHPDZrm:
31543 case VUNPCKHPDZrmb:
31544 case VUNPCKHPDZrmbk:
31545 case VUNPCKHPDZrmbkz:
31546 case VUNPCKHPDZrmk:
31547 case VUNPCKHPDZrmkz:
31548 case VUNPCKHPDZrr:
31549 case VUNPCKHPDZrrk:
31550 case VUNPCKHPDZrrkz:
31551 case VUNPCKHPDrm:
31552 case VUNPCKHPDrr:
31553 return true;
31554 }
31555 return false;
31556}
31557
31558bool isCVTPS2DQ(unsigned Opcode) {
31559 switch (Opcode) {
31560 case CVTPS2DQrm:
31561 case CVTPS2DQrr:
31562 return true;
31563 }
31564 return false;
31565}
31566
31567bool isTMMULTF32PS(unsigned Opcode) {
31568 return Opcode == TMMULTF32PS;
31569}
31570
31571bool isVFMSUB213SS(unsigned Opcode) {
31572 switch (Opcode) {
31573 case VFMSUB213SSZm_Int:
31574 case VFMSUB213SSZmk_Int:
31575 case VFMSUB213SSZmkz_Int:
31576 case VFMSUB213SSZr_Int:
31577 case VFMSUB213SSZrb_Int:
31578 case VFMSUB213SSZrbk_Int:
31579 case VFMSUB213SSZrbkz_Int:
31580 case VFMSUB213SSZrk_Int:
31581 case VFMSUB213SSZrkz_Int:
31582 case VFMSUB213SSm_Int:
31583 case VFMSUB213SSr_Int:
31584 return true;
31585 }
31586 return false;
31587}
31588
31589bool isVPOPCNTD(unsigned Opcode) {
31590 switch (Opcode) {
31591 case VPOPCNTDZ128rm:
31592 case VPOPCNTDZ128rmb:
31593 case VPOPCNTDZ128rmbk:
31594 case VPOPCNTDZ128rmbkz:
31595 case VPOPCNTDZ128rmk:
31596 case VPOPCNTDZ128rmkz:
31597 case VPOPCNTDZ128rr:
31598 case VPOPCNTDZ128rrk:
31599 case VPOPCNTDZ128rrkz:
31600 case VPOPCNTDZ256rm:
31601 case VPOPCNTDZ256rmb:
31602 case VPOPCNTDZ256rmbk:
31603 case VPOPCNTDZ256rmbkz:
31604 case VPOPCNTDZ256rmk:
31605 case VPOPCNTDZ256rmkz:
31606 case VPOPCNTDZ256rr:
31607 case VPOPCNTDZ256rrk:
31608 case VPOPCNTDZ256rrkz:
31609 case VPOPCNTDZrm:
31610 case VPOPCNTDZrmb:
31611 case VPOPCNTDZrmbk:
31612 case VPOPCNTDZrmbkz:
31613 case VPOPCNTDZrmk:
31614 case VPOPCNTDZrmkz:
31615 case VPOPCNTDZrr:
31616 case VPOPCNTDZrrk:
31617 case VPOPCNTDZrrkz:
31618 return true;
31619 }
31620 return false;
31621}
31622
31623bool isSALC(unsigned Opcode) {
31624 return Opcode == SALC;
31625}
31626
31627bool isV4FNMADDSS(unsigned Opcode) {
31628 switch (Opcode) {
31629 case V4FNMADDSSrm:
31630 case V4FNMADDSSrmk:
31631 case V4FNMADDSSrmkz:
31632 return true;
31633 }
31634 return false;
31635}
31636
31637bool isXCRYPTOFB(unsigned Opcode) {
31638 return Opcode == XCRYPTOFB;
31639}
31640
31641bool isVORPD(unsigned Opcode) {
31642 switch (Opcode) {
31643 case VORPDYrm:
31644 case VORPDYrr:
31645 case VORPDZ128rm:
31646 case VORPDZ128rmb:
31647 case VORPDZ128rmbk:
31648 case VORPDZ128rmbkz:
31649 case VORPDZ128rmk:
31650 case VORPDZ128rmkz:
31651 case VORPDZ128rr:
31652 case VORPDZ128rrk:
31653 case VORPDZ128rrkz:
31654 case VORPDZ256rm:
31655 case VORPDZ256rmb:
31656 case VORPDZ256rmbk:
31657 case VORPDZ256rmbkz:
31658 case VORPDZ256rmk:
31659 case VORPDZ256rmkz:
31660 case VORPDZ256rr:
31661 case VORPDZ256rrk:
31662 case VORPDZ256rrkz:
31663 case VORPDZrm:
31664 case VORPDZrmb:
31665 case VORPDZrmbk:
31666 case VORPDZrmbkz:
31667 case VORPDZrmk:
31668 case VORPDZrmkz:
31669 case VORPDZrr:
31670 case VORPDZrrk:
31671 case VORPDZrrkz:
31672 case VORPDrm:
31673 case VORPDrr:
31674 return true;
31675 }
31676 return false;
31677}
31678
31679bool isLSL(unsigned Opcode) {
31680 switch (Opcode) {
31681 case LSL16rm:
31682 case LSL16rr:
31683 case LSL32rm:
31684 case LSL32rr:
31685 case LSL64rm:
31686 case LSL64rr:
31687 return true;
31688 }
31689 return false;
31690}
31691
31692bool isXCRYPTCFB(unsigned Opcode) {
31693 return Opcode == XCRYPTCFB;
31694}
31695
31696bool isVGETEXPSS(unsigned Opcode) {
31697 switch (Opcode) {
31698 case VGETEXPSSZm:
31699 case VGETEXPSSZmk:
31700 case VGETEXPSSZmkz:
31701 case VGETEXPSSZr:
31702 case VGETEXPSSZrb:
31703 case VGETEXPSSZrbk:
31704 case VGETEXPSSZrbkz:
31705 case VGETEXPSSZrk:
31706 case VGETEXPSSZrkz:
31707 return true;
31708 }
31709 return false;
31710}
31711
31712bool isPSLLDQ(unsigned Opcode) {
31713 return Opcode == PSLLDQri;
31714}
31715
31716bool isVPDPBUUD(unsigned Opcode) {
31717 switch (Opcode) {
31718 case VPDPBUUDYrm:
31719 case VPDPBUUDYrr:
31720 case VPDPBUUDZ128rm:
31721 case VPDPBUUDZ128rmb:
31722 case VPDPBUUDZ128rmbk:
31723 case VPDPBUUDZ128rmbkz:
31724 case VPDPBUUDZ128rmk:
31725 case VPDPBUUDZ128rmkz:
31726 case VPDPBUUDZ128rr:
31727 case VPDPBUUDZ128rrk:
31728 case VPDPBUUDZ128rrkz:
31729 case VPDPBUUDZ256rm:
31730 case VPDPBUUDZ256rmb:
31731 case VPDPBUUDZ256rmbk:
31732 case VPDPBUUDZ256rmbkz:
31733 case VPDPBUUDZ256rmk:
31734 case VPDPBUUDZ256rmkz:
31735 case VPDPBUUDZ256rr:
31736 case VPDPBUUDZ256rrk:
31737 case VPDPBUUDZ256rrkz:
31738 case VPDPBUUDZrm:
31739 case VPDPBUUDZrmb:
31740 case VPDPBUUDZrmbk:
31741 case VPDPBUUDZrmbkz:
31742 case VPDPBUUDZrmk:
31743 case VPDPBUUDZrmkz:
31744 case VPDPBUUDZrr:
31745 case VPDPBUUDZrrk:
31746 case VPDPBUUDZrrkz:
31747 case VPDPBUUDrm:
31748 case VPDPBUUDrr:
31749 return true;
31750 }
31751 return false;
31752}
31753
31754bool isVMXOFF(unsigned Opcode) {
31755 return Opcode == VMXOFF;
31756}
31757
31758bool isBLSIC(unsigned Opcode) {
31759 switch (Opcode) {
31760 case BLSIC32rm:
31761 case BLSIC32rr:
31762 case BLSIC64rm:
31763 case BLSIC64rr:
31764 return true;
31765 }
31766 return false;
31767}
31768
31769bool isMOVLHPS(unsigned Opcode) {
31770 return Opcode == MOVLHPSrr;
31771}
31772
31773bool isVMOVRSQ(unsigned Opcode) {
31774 switch (Opcode) {
31775 case VMOVRSQZ128m:
31776 case VMOVRSQZ128mk:
31777 case VMOVRSQZ128mkz:
31778 case VMOVRSQZ256m:
31779 case VMOVRSQZ256mk:
31780 case VMOVRSQZ256mkz:
31781 case VMOVRSQZm:
31782 case VMOVRSQZmk:
31783 case VMOVRSQZmkz:
31784 return true;
31785 }
31786 return false;
31787}
31788
31789bool isVFNMSUBSD(unsigned Opcode) {
31790 switch (Opcode) {
31791 case VFNMSUBSD4mr:
31792 case VFNMSUBSD4rm:
31793 case VFNMSUBSD4rr:
31794 case VFNMSUBSD4rr_REV:
31795 return true;
31796 }
31797 return false;
31798}
31799
31800bool isVCVTPH2IUBS(unsigned Opcode) {
31801 switch (Opcode) {
31802 case VCVTPH2IUBSZ128rm:
31803 case VCVTPH2IUBSZ128rmb:
31804 case VCVTPH2IUBSZ128rmbk:
31805 case VCVTPH2IUBSZ128rmbkz:
31806 case VCVTPH2IUBSZ128rmk:
31807 case VCVTPH2IUBSZ128rmkz:
31808 case VCVTPH2IUBSZ128rr:
31809 case VCVTPH2IUBSZ128rrk:
31810 case VCVTPH2IUBSZ128rrkz:
31811 case VCVTPH2IUBSZ256rm:
31812 case VCVTPH2IUBSZ256rmb:
31813 case VCVTPH2IUBSZ256rmbk:
31814 case VCVTPH2IUBSZ256rmbkz:
31815 case VCVTPH2IUBSZ256rmk:
31816 case VCVTPH2IUBSZ256rmkz:
31817 case VCVTPH2IUBSZ256rr:
31818 case VCVTPH2IUBSZ256rrk:
31819 case VCVTPH2IUBSZ256rrkz:
31820 case VCVTPH2IUBSZrm:
31821 case VCVTPH2IUBSZrmb:
31822 case VCVTPH2IUBSZrmbk:
31823 case VCVTPH2IUBSZrmbkz:
31824 case VCVTPH2IUBSZrmk:
31825 case VCVTPH2IUBSZrmkz:
31826 case VCVTPH2IUBSZrr:
31827 case VCVTPH2IUBSZrrb:
31828 case VCVTPH2IUBSZrrbk:
31829 case VCVTPH2IUBSZrrbkz:
31830 case VCVTPH2IUBSZrrk:
31831 case VCVTPH2IUBSZrrkz:
31832 return true;
31833 }
31834 return false;
31835}
31836
31837bool isVFPCLASSSH(unsigned Opcode) {
31838 switch (Opcode) {
31839 case VFPCLASSSHZmi:
31840 case VFPCLASSSHZmik:
31841 case VFPCLASSSHZri:
31842 case VFPCLASSSHZrik:
31843 return true;
31844 }
31845 return false;
31846}
31847
31848bool isVPSHLQ(unsigned Opcode) {
31849 switch (Opcode) {
31850 case VPSHLQmr:
31851 case VPSHLQrm:
31852 case VPSHLQrr:
31853 case VPSHLQrr_REV:
31854 return true;
31855 }
31856 return false;
31857}
31858
31859bool isVROUNDPS(unsigned Opcode) {
31860 switch (Opcode) {
31861 case VROUNDPSYmi:
31862 case VROUNDPSYri:
31863 case VROUNDPSmi:
31864 case VROUNDPSri:
31865 return true;
31866 }
31867 return false;
31868}
31869
31870bool isVSCATTERPF0QPS(unsigned Opcode) {
31871 return Opcode == VSCATTERPF0QPSm;
31872}
31873
31874bool isERETS(unsigned Opcode) {
31875 return Opcode == ERETS;
31876}
31877
31878bool isVPERMI2D(unsigned Opcode) {
31879 switch (Opcode) {
31880 case VPERMI2DZ128rm:
31881 case VPERMI2DZ128rmb:
31882 case VPERMI2DZ128rmbk:
31883 case VPERMI2DZ128rmbkz:
31884 case VPERMI2DZ128rmk:
31885 case VPERMI2DZ128rmkz:
31886 case VPERMI2DZ128rr:
31887 case VPERMI2DZ128rrk:
31888 case VPERMI2DZ128rrkz:
31889 case VPERMI2DZ256rm:
31890 case VPERMI2DZ256rmb:
31891 case VPERMI2DZ256rmbk:
31892 case VPERMI2DZ256rmbkz:
31893 case VPERMI2DZ256rmk:
31894 case VPERMI2DZ256rmkz:
31895 case VPERMI2DZ256rr:
31896 case VPERMI2DZ256rrk:
31897 case VPERMI2DZ256rrkz:
31898 case VPERMI2DZrm:
31899 case VPERMI2DZrmb:
31900 case VPERMI2DZrmbk:
31901 case VPERMI2DZrmbkz:
31902 case VPERMI2DZrmk:
31903 case VPERMI2DZrmkz:
31904 case VPERMI2DZrr:
31905 case VPERMI2DZrrk:
31906 case VPERMI2DZrrkz:
31907 return true;
31908 }
31909 return false;
31910}
31911
31912bool isFUCOMP(unsigned Opcode) {
31913 return Opcode == UCOM_FPr;
31914}
31915
31916bool isVCVTTPS2QQ(unsigned Opcode) {
31917 switch (Opcode) {
31918 case VCVTTPS2QQZ128rm:
31919 case VCVTTPS2QQZ128rmb:
31920 case VCVTTPS2QQZ128rmbk:
31921 case VCVTTPS2QQZ128rmbkz:
31922 case VCVTTPS2QQZ128rmk:
31923 case VCVTTPS2QQZ128rmkz:
31924 case VCVTTPS2QQZ128rr:
31925 case VCVTTPS2QQZ128rrk:
31926 case VCVTTPS2QQZ128rrkz:
31927 case VCVTTPS2QQZ256rm:
31928 case VCVTTPS2QQZ256rmb:
31929 case VCVTTPS2QQZ256rmbk:
31930 case VCVTTPS2QQZ256rmbkz:
31931 case VCVTTPS2QQZ256rmk:
31932 case VCVTTPS2QQZ256rmkz:
31933 case VCVTTPS2QQZ256rr:
31934 case VCVTTPS2QQZ256rrk:
31935 case VCVTTPS2QQZ256rrkz:
31936 case VCVTTPS2QQZrm:
31937 case VCVTTPS2QQZrmb:
31938 case VCVTTPS2QQZrmbk:
31939 case VCVTTPS2QQZrmbkz:
31940 case VCVTTPS2QQZrmk:
31941 case VCVTTPS2QQZrmkz:
31942 case VCVTTPS2QQZrr:
31943 case VCVTTPS2QQZrrb:
31944 case VCVTTPS2QQZrrbk:
31945 case VCVTTPS2QQZrrbkz:
31946 case VCVTTPS2QQZrrk:
31947 case VCVTTPS2QQZrrkz:
31948 return true;
31949 }
31950 return false;
31951}
31952
31953bool isPUSHFD(unsigned Opcode) {
31954 return Opcode == PUSHF32;
31955}
31956
31957bool isKORB(unsigned Opcode) {
31958 return Opcode == KORBkk;
31959}
31960
31961bool isVRCP28PD(unsigned Opcode) {
31962 switch (Opcode) {
31963 case VRCP28PDZm:
31964 case VRCP28PDZmb:
31965 case VRCP28PDZmbk:
31966 case VRCP28PDZmbkz:
31967 case VRCP28PDZmk:
31968 case VRCP28PDZmkz:
31969 case VRCP28PDZr:
31970 case VRCP28PDZrb:
31971 case VRCP28PDZrbk:
31972 case VRCP28PDZrbkz:
31973 case VRCP28PDZrk:
31974 case VRCP28PDZrkz:
31975 return true;
31976 }
31977 return false;
31978}
31979
31980bool isVPABSD(unsigned Opcode) {
31981 switch (Opcode) {
31982 case VPABSDYrm:
31983 case VPABSDYrr:
31984 case VPABSDZ128rm:
31985 case VPABSDZ128rmb:
31986 case VPABSDZ128rmbk:
31987 case VPABSDZ128rmbkz:
31988 case VPABSDZ128rmk:
31989 case VPABSDZ128rmkz:
31990 case VPABSDZ128rr:
31991 case VPABSDZ128rrk:
31992 case VPABSDZ128rrkz:
31993 case VPABSDZ256rm:
31994 case VPABSDZ256rmb:
31995 case VPABSDZ256rmbk:
31996 case VPABSDZ256rmbkz:
31997 case VPABSDZ256rmk:
31998 case VPABSDZ256rmkz:
31999 case VPABSDZ256rr:
32000 case VPABSDZ256rrk:
32001 case VPABSDZ256rrkz:
32002 case VPABSDZrm:
32003 case VPABSDZrmb:
32004 case VPABSDZrmbk:
32005 case VPABSDZrmbkz:
32006 case VPABSDZrmk:
32007 case VPABSDZrmkz:
32008 case VPABSDZrr:
32009 case VPABSDZrrk:
32010 case VPABSDZrrkz:
32011 case VPABSDrm:
32012 case VPABSDrr:
32013 return true;
32014 }
32015 return false;
32016}
32017
32018bool isVROUNDSS(unsigned Opcode) {
32019 switch (Opcode) {
32020 case VROUNDSSmi_Int:
32021 case VROUNDSSri_Int:
32022 return true;
32023 }
32024 return false;
32025}
32026
32027bool isVCVTSD2USI(unsigned Opcode) {
32028 switch (Opcode) {
32029 case VCVTSD2USI64Zrm_Int:
32030 case VCVTSD2USI64Zrr_Int:
32031 case VCVTSD2USI64Zrrb_Int:
32032 case VCVTSD2USIZrm_Int:
32033 case VCVTSD2USIZrr_Int:
32034 case VCVTSD2USIZrrb_Int:
32035 return true;
32036 }
32037 return false;
32038}
32039
32040bool isVPABSB(unsigned Opcode) {
32041 switch (Opcode) {
32042 case VPABSBYrm:
32043 case VPABSBYrr:
32044 case VPABSBZ128rm:
32045 case VPABSBZ128rmk:
32046 case VPABSBZ128rmkz:
32047 case VPABSBZ128rr:
32048 case VPABSBZ128rrk:
32049 case VPABSBZ128rrkz:
32050 case VPABSBZ256rm:
32051 case VPABSBZ256rmk:
32052 case VPABSBZ256rmkz:
32053 case VPABSBZ256rr:
32054 case VPABSBZ256rrk:
32055 case VPABSBZ256rrkz:
32056 case VPABSBZrm:
32057 case VPABSBZrmk:
32058 case VPABSBZrmkz:
32059 case VPABSBZrr:
32060 case VPABSBZrrk:
32061 case VPABSBZrrkz:
32062 case VPABSBrm:
32063 case VPABSBrr:
32064 return true;
32065 }
32066 return false;
32067}
32068
32069bool isPMAXUD(unsigned Opcode) {
32070 switch (Opcode) {
32071 case PMAXUDrm:
32072 case PMAXUDrr:
32073 return true;
32074 }
32075 return false;
32076}
32077
32078bool isVPMULHUW(unsigned Opcode) {
32079 switch (Opcode) {
32080 case VPMULHUWYrm:
32081 case VPMULHUWYrr:
32082 case VPMULHUWZ128rm:
32083 case VPMULHUWZ128rmk:
32084 case VPMULHUWZ128rmkz:
32085 case VPMULHUWZ128rr:
32086 case VPMULHUWZ128rrk:
32087 case VPMULHUWZ128rrkz:
32088 case VPMULHUWZ256rm:
32089 case VPMULHUWZ256rmk:
32090 case VPMULHUWZ256rmkz:
32091 case VPMULHUWZ256rr:
32092 case VPMULHUWZ256rrk:
32093 case VPMULHUWZ256rrkz:
32094 case VPMULHUWZrm:
32095 case VPMULHUWZrmk:
32096 case VPMULHUWZrmkz:
32097 case VPMULHUWZrr:
32098 case VPMULHUWZrrk:
32099 case VPMULHUWZrrkz:
32100 case VPMULHUWrm:
32101 case VPMULHUWrr:
32102 return true;
32103 }
32104 return false;
32105}
32106
32107bool isVPERMPD(unsigned Opcode) {
32108 switch (Opcode) {
32109 case VPERMPDYmi:
32110 case VPERMPDYri:
32111 case VPERMPDZ256mbi:
32112 case VPERMPDZ256mbik:
32113 case VPERMPDZ256mbikz:
32114 case VPERMPDZ256mi:
32115 case VPERMPDZ256mik:
32116 case VPERMPDZ256mikz:
32117 case VPERMPDZ256ri:
32118 case VPERMPDZ256rik:
32119 case VPERMPDZ256rikz:
32120 case VPERMPDZ256rm:
32121 case VPERMPDZ256rmb:
32122 case VPERMPDZ256rmbk:
32123 case VPERMPDZ256rmbkz:
32124 case VPERMPDZ256rmk:
32125 case VPERMPDZ256rmkz:
32126 case VPERMPDZ256rr:
32127 case VPERMPDZ256rrk:
32128 case VPERMPDZ256rrkz:
32129 case VPERMPDZmbi:
32130 case VPERMPDZmbik:
32131 case VPERMPDZmbikz:
32132 case VPERMPDZmi:
32133 case VPERMPDZmik:
32134 case VPERMPDZmikz:
32135 case VPERMPDZri:
32136 case VPERMPDZrik:
32137 case VPERMPDZrikz:
32138 case VPERMPDZrm:
32139 case VPERMPDZrmb:
32140 case VPERMPDZrmbk:
32141 case VPERMPDZrmbkz:
32142 case VPERMPDZrmk:
32143 case VPERMPDZrmkz:
32144 case VPERMPDZrr:
32145 case VPERMPDZrrk:
32146 case VPERMPDZrrkz:
32147 return true;
32148 }
32149 return false;
32150}
32151
32152bool isFCHS(unsigned Opcode) {
32153 return Opcode == CHS_F;
32154}
32155
32156bool isVPBLENDMB(unsigned Opcode) {
32157 switch (Opcode) {
32158 case VPBLENDMBZ128rm:
32159 case VPBLENDMBZ128rmk:
32160 case VPBLENDMBZ128rmkz:
32161 case VPBLENDMBZ128rr:
32162 case VPBLENDMBZ128rrk:
32163 case VPBLENDMBZ128rrkz:
32164 case VPBLENDMBZ256rm:
32165 case VPBLENDMBZ256rmk:
32166 case VPBLENDMBZ256rmkz:
32167 case VPBLENDMBZ256rr:
32168 case VPBLENDMBZ256rrk:
32169 case VPBLENDMBZ256rrkz:
32170 case VPBLENDMBZrm:
32171 case VPBLENDMBZrmk:
32172 case VPBLENDMBZrmkz:
32173 case VPBLENDMBZrr:
32174 case VPBLENDMBZrrk:
32175 case VPBLENDMBZrrkz:
32176 return true;
32177 }
32178 return false;
32179}
32180
32181bool isVGETMANTSS(unsigned Opcode) {
32182 switch (Opcode) {
32183 case VGETMANTSSZrmi:
32184 case VGETMANTSSZrmik:
32185 case VGETMANTSSZrmikz:
32186 case VGETMANTSSZrri:
32187 case VGETMANTSSZrrib:
32188 case VGETMANTSSZrribk:
32189 case VGETMANTSSZrribkz:
32190 case VGETMANTSSZrrik:
32191 case VGETMANTSSZrrikz:
32192 return true;
32193 }
32194 return false;
32195}
32196
32197bool isVPSLLW(unsigned Opcode) {
32198 switch (Opcode) {
32199 case VPSLLWYri:
32200 case VPSLLWYrm:
32201 case VPSLLWYrr:
32202 case VPSLLWZ128mi:
32203 case VPSLLWZ128mik:
32204 case VPSLLWZ128mikz:
32205 case VPSLLWZ128ri:
32206 case VPSLLWZ128rik:
32207 case VPSLLWZ128rikz:
32208 case VPSLLWZ128rm:
32209 case VPSLLWZ128rmk:
32210 case VPSLLWZ128rmkz:
32211 case VPSLLWZ128rr:
32212 case VPSLLWZ128rrk:
32213 case VPSLLWZ128rrkz:
32214 case VPSLLWZ256mi:
32215 case VPSLLWZ256mik:
32216 case VPSLLWZ256mikz:
32217 case VPSLLWZ256ri:
32218 case VPSLLWZ256rik:
32219 case VPSLLWZ256rikz:
32220 case VPSLLWZ256rm:
32221 case VPSLLWZ256rmk:
32222 case VPSLLWZ256rmkz:
32223 case VPSLLWZ256rr:
32224 case VPSLLWZ256rrk:
32225 case VPSLLWZ256rrkz:
32226 case VPSLLWZmi:
32227 case VPSLLWZmik:
32228 case VPSLLWZmikz:
32229 case VPSLLWZri:
32230 case VPSLLWZrik:
32231 case VPSLLWZrikz:
32232 case VPSLLWZrm:
32233 case VPSLLWZrmk:
32234 case VPSLLWZrmkz:
32235 case VPSLLWZrr:
32236 case VPSLLWZrrk:
32237 case VPSLLWZrrkz:
32238 case VPSLLWri:
32239 case VPSLLWrm:
32240 case VPSLLWrr:
32241 return true;
32242 }
32243 return false;
32244}
32245
32246bool isVDIVPD(unsigned Opcode) {
32247 switch (Opcode) {
32248 case VDIVPDYrm:
32249 case VDIVPDYrr:
32250 case VDIVPDZ128rm:
32251 case VDIVPDZ128rmb:
32252 case VDIVPDZ128rmbk:
32253 case VDIVPDZ128rmbkz:
32254 case VDIVPDZ128rmk:
32255 case VDIVPDZ128rmkz:
32256 case VDIVPDZ128rr:
32257 case VDIVPDZ128rrk:
32258 case VDIVPDZ128rrkz:
32259 case VDIVPDZ256rm:
32260 case VDIVPDZ256rmb:
32261 case VDIVPDZ256rmbk:
32262 case VDIVPDZ256rmbkz:
32263 case VDIVPDZ256rmk:
32264 case VDIVPDZ256rmkz:
32265 case VDIVPDZ256rr:
32266 case VDIVPDZ256rrk:
32267 case VDIVPDZ256rrkz:
32268 case VDIVPDZrm:
32269 case VDIVPDZrmb:
32270 case VDIVPDZrmbk:
32271 case VDIVPDZrmbkz:
32272 case VDIVPDZrmk:
32273 case VDIVPDZrmkz:
32274 case VDIVPDZrr:
32275 case VDIVPDZrrb:
32276 case VDIVPDZrrbk:
32277 case VDIVPDZrrbkz:
32278 case VDIVPDZrrk:
32279 case VDIVPDZrrkz:
32280 case VDIVPDrm:
32281 case VDIVPDrr:
32282 return true;
32283 }
32284 return false;
32285}
32286
32287bool isBLCMSK(unsigned Opcode) {
32288 switch (Opcode) {
32289 case BLCMSK32rm:
32290 case BLCMSK32rr:
32291 case BLCMSK64rm:
32292 case BLCMSK64rr:
32293 return true;
32294 }
32295 return false;
32296}
32297
32298bool isFDIV(unsigned Opcode) {
32299 switch (Opcode) {
32300 case DIV_F32m:
32301 case DIV_F64m:
32302 case DIV_FST0r:
32303 case DIV_FrST0:
32304 return true;
32305 }
32306 return false;
32307}
32308
32309bool isRSQRTSS(unsigned Opcode) {
32310 switch (Opcode) {
32311 case RSQRTSSm_Int:
32312 case RSQRTSSr_Int:
32313 return true;
32314 }
32315 return false;
32316}
32317
32318bool isPOR(unsigned Opcode) {
32319 switch (Opcode) {
32320 case MMX_PORrm:
32321 case MMX_PORrr:
32322 case PORrm:
32323 case PORrr:
32324 return true;
32325 }
32326 return false;
32327}
32328
32329bool isVMOVDQA32(unsigned Opcode) {
32330 switch (Opcode) {
32331 case VMOVDQA32Z128mr:
32332 case VMOVDQA32Z128mrk:
32333 case VMOVDQA32Z128rm:
32334 case VMOVDQA32Z128rmk:
32335 case VMOVDQA32Z128rmkz:
32336 case VMOVDQA32Z128rr:
32337 case VMOVDQA32Z128rr_REV:
32338 case VMOVDQA32Z128rrk:
32339 case VMOVDQA32Z128rrk_REV:
32340 case VMOVDQA32Z128rrkz:
32341 case VMOVDQA32Z128rrkz_REV:
32342 case VMOVDQA32Z256mr:
32343 case VMOVDQA32Z256mrk:
32344 case VMOVDQA32Z256rm:
32345 case VMOVDQA32Z256rmk:
32346 case VMOVDQA32Z256rmkz:
32347 case VMOVDQA32Z256rr:
32348 case VMOVDQA32Z256rr_REV:
32349 case VMOVDQA32Z256rrk:
32350 case VMOVDQA32Z256rrk_REV:
32351 case VMOVDQA32Z256rrkz:
32352 case VMOVDQA32Z256rrkz_REV:
32353 case VMOVDQA32Zmr:
32354 case VMOVDQA32Zmrk:
32355 case VMOVDQA32Zrm:
32356 case VMOVDQA32Zrmk:
32357 case VMOVDQA32Zrmkz:
32358 case VMOVDQA32Zrr:
32359 case VMOVDQA32Zrr_REV:
32360 case VMOVDQA32Zrrk:
32361 case VMOVDQA32Zrrk_REV:
32362 case VMOVDQA32Zrrkz:
32363 case VMOVDQA32Zrrkz_REV:
32364 return true;
32365 }
32366 return false;
32367}
32368
32369bool isVPHADDUWQ(unsigned Opcode) {
32370 switch (Opcode) {
32371 case VPHADDUWQrm:
32372 case VPHADDUWQrr:
32373 return true;
32374 }
32375 return false;
32376}
32377
32378bool isPSRAD(unsigned Opcode) {
32379 switch (Opcode) {
32380 case MMX_PSRADri:
32381 case MMX_PSRADrm:
32382 case MMX_PSRADrr:
32383 case PSRADri:
32384 case PSRADrm:
32385 case PSRADrr:
32386 return true;
32387 }
32388 return false;
32389}
32390
32391bool isPREFETCHW(unsigned Opcode) {
32392 return Opcode == PREFETCHW;
32393}
32394
32395bool isFIDIVR(unsigned Opcode) {
32396 switch (Opcode) {
32397 case DIVR_FI16m:
32398 case DIVR_FI32m:
32399 return true;
32400 }
32401 return false;
32402}
32403
32404bool isMOVHPS(unsigned Opcode) {
32405 switch (Opcode) {
32406 case MOVHPSmr:
32407 case MOVHPSrm:
32408 return true;
32409 }
32410 return false;
32411}
32412
32413bool isVFNMSUB231PH(unsigned Opcode) {
32414 switch (Opcode) {
32415 case VFNMSUB231PHZ128m:
32416 case VFNMSUB231PHZ128mb:
32417 case VFNMSUB231PHZ128mbk:
32418 case VFNMSUB231PHZ128mbkz:
32419 case VFNMSUB231PHZ128mk:
32420 case VFNMSUB231PHZ128mkz:
32421 case VFNMSUB231PHZ128r:
32422 case VFNMSUB231PHZ128rk:
32423 case VFNMSUB231PHZ128rkz:
32424 case VFNMSUB231PHZ256m:
32425 case VFNMSUB231PHZ256mb:
32426 case VFNMSUB231PHZ256mbk:
32427 case VFNMSUB231PHZ256mbkz:
32428 case VFNMSUB231PHZ256mk:
32429 case VFNMSUB231PHZ256mkz:
32430 case VFNMSUB231PHZ256r:
32431 case VFNMSUB231PHZ256rk:
32432 case VFNMSUB231PHZ256rkz:
32433 case VFNMSUB231PHZm:
32434 case VFNMSUB231PHZmb:
32435 case VFNMSUB231PHZmbk:
32436 case VFNMSUB231PHZmbkz:
32437 case VFNMSUB231PHZmk:
32438 case VFNMSUB231PHZmkz:
32439 case VFNMSUB231PHZr:
32440 case VFNMSUB231PHZrb:
32441 case VFNMSUB231PHZrbk:
32442 case VFNMSUB231PHZrbkz:
32443 case VFNMSUB231PHZrk:
32444 case VFNMSUB231PHZrkz:
32445 return true;
32446 }
32447 return false;
32448}
32449
32450bool isUNPCKLPS(unsigned Opcode) {
32451 switch (Opcode) {
32452 case UNPCKLPSrm:
32453 case UNPCKLPSrr:
32454 return true;
32455 }
32456 return false;
32457}
32458
32459bool isVPSIGNB(unsigned Opcode) {
32460 switch (Opcode) {
32461 case VPSIGNBYrm:
32462 case VPSIGNBYrr:
32463 case VPSIGNBrm:
32464 case VPSIGNBrr:
32465 return true;
32466 }
32467 return false;
32468}
32469
32470bool isSAVEPREVSSP(unsigned Opcode) {
32471 return Opcode == SAVEPREVSSP;
32472}
32473
32474bool isVSCALEFSD(unsigned Opcode) {
32475 switch (Opcode) {
32476 case VSCALEFSDZrm:
32477 case VSCALEFSDZrmk:
32478 case VSCALEFSDZrmkz:
32479 case VSCALEFSDZrr:
32480 case VSCALEFSDZrrb_Int:
32481 case VSCALEFSDZrrbk_Int:
32482 case VSCALEFSDZrrbkz_Int:
32483 case VSCALEFSDZrrk:
32484 case VSCALEFSDZrrkz:
32485 return true;
32486 }
32487 return false;
32488}
32489
32490bool isFSIN(unsigned Opcode) {
32491 return Opcode == FSIN;
32492}
32493
32494bool isSCASQ(unsigned Opcode) {
32495 return Opcode == SCASQ;
32496}
32497
32498bool isVCVTTPD2QQS(unsigned Opcode) {
32499 switch (Opcode) {
32500 case VCVTTPD2QQSZ128rm:
32501 case VCVTTPD2QQSZ128rmb:
32502 case VCVTTPD2QQSZ128rmbk:
32503 case VCVTTPD2QQSZ128rmbkz:
32504 case VCVTTPD2QQSZ128rmk:
32505 case VCVTTPD2QQSZ128rmkz:
32506 case VCVTTPD2QQSZ128rr:
32507 case VCVTTPD2QQSZ128rrk:
32508 case VCVTTPD2QQSZ128rrkz:
32509 case VCVTTPD2QQSZ256rm:
32510 case VCVTTPD2QQSZ256rmb:
32511 case VCVTTPD2QQSZ256rmbk:
32512 case VCVTTPD2QQSZ256rmbkz:
32513 case VCVTTPD2QQSZ256rmk:
32514 case VCVTTPD2QQSZ256rmkz:
32515 case VCVTTPD2QQSZ256rr:
32516 case VCVTTPD2QQSZ256rrb:
32517 case VCVTTPD2QQSZ256rrbk:
32518 case VCVTTPD2QQSZ256rrbkz:
32519 case VCVTTPD2QQSZ256rrk:
32520 case VCVTTPD2QQSZ256rrkz:
32521 case VCVTTPD2QQSZrm:
32522 case VCVTTPD2QQSZrmb:
32523 case VCVTTPD2QQSZrmbk:
32524 case VCVTTPD2QQSZrmbkz:
32525 case VCVTTPD2QQSZrmk:
32526 case VCVTTPD2QQSZrmkz:
32527 case VCVTTPD2QQSZrr:
32528 case VCVTTPD2QQSZrrb:
32529 case VCVTTPD2QQSZrrbk:
32530 case VCVTTPD2QQSZrrbkz:
32531 case VCVTTPD2QQSZrrk:
32532 case VCVTTPD2QQSZrrkz:
32533 return true;
32534 }
32535 return false;
32536}
32537
32538bool isPCMPGTW(unsigned Opcode) {
32539 switch (Opcode) {
32540 case MMX_PCMPGTWrm:
32541 case MMX_PCMPGTWrr:
32542 case PCMPGTWrm:
32543 case PCMPGTWrr:
32544 return true;
32545 }
32546 return false;
32547}
32548
32549bool isMULX(unsigned Opcode) {
32550 switch (Opcode) {
32551 case MULX32rm:
32552 case MULX32rm_EVEX:
32553 case MULX32rr:
32554 case MULX32rr_EVEX:
32555 case MULX64rm:
32556 case MULX64rm_EVEX:
32557 case MULX64rr:
32558 case MULX64rr_EVEX:
32559 return true;
32560 }
32561 return false;
32562}
32563
32564bool isVPMAXUW(unsigned Opcode) {
32565 switch (Opcode) {
32566 case VPMAXUWYrm:
32567 case VPMAXUWYrr:
32568 case VPMAXUWZ128rm:
32569 case VPMAXUWZ128rmk:
32570 case VPMAXUWZ128rmkz:
32571 case VPMAXUWZ128rr:
32572 case VPMAXUWZ128rrk:
32573 case VPMAXUWZ128rrkz:
32574 case VPMAXUWZ256rm:
32575 case VPMAXUWZ256rmk:
32576 case VPMAXUWZ256rmkz:
32577 case VPMAXUWZ256rr:
32578 case VPMAXUWZ256rrk:
32579 case VPMAXUWZ256rrkz:
32580 case VPMAXUWZrm:
32581 case VPMAXUWZrmk:
32582 case VPMAXUWZrmkz:
32583 case VPMAXUWZrr:
32584 case VPMAXUWZrrk:
32585 case VPMAXUWZrrkz:
32586 case VPMAXUWrm:
32587 case VPMAXUWrr:
32588 return true;
32589 }
32590 return false;
32591}
32592
32593bool isPAUSE(unsigned Opcode) {
32594 return Opcode == PAUSE;
32595}
32596
32597bool isMOVQ2DQ(unsigned Opcode) {
32598 return Opcode == MMX_MOVQ2DQrr;
32599}
32600
32601bool isVPSUBQ(unsigned Opcode) {
32602 switch (Opcode) {
32603 case VPSUBQYrm:
32604 case VPSUBQYrr:
32605 case VPSUBQZ128rm:
32606 case VPSUBQZ128rmb:
32607 case VPSUBQZ128rmbk:
32608 case VPSUBQZ128rmbkz:
32609 case VPSUBQZ128rmk:
32610 case VPSUBQZ128rmkz:
32611 case VPSUBQZ128rr:
32612 case VPSUBQZ128rrk:
32613 case VPSUBQZ128rrkz:
32614 case VPSUBQZ256rm:
32615 case VPSUBQZ256rmb:
32616 case VPSUBQZ256rmbk:
32617 case VPSUBQZ256rmbkz:
32618 case VPSUBQZ256rmk:
32619 case VPSUBQZ256rmkz:
32620 case VPSUBQZ256rr:
32621 case VPSUBQZ256rrk:
32622 case VPSUBQZ256rrkz:
32623 case VPSUBQZrm:
32624 case VPSUBQZrmb:
32625 case VPSUBQZrmbk:
32626 case VPSUBQZrmbkz:
32627 case VPSUBQZrmk:
32628 case VPSUBQZrmkz:
32629 case VPSUBQZrr:
32630 case VPSUBQZrrk:
32631 case VPSUBQZrrkz:
32632 case VPSUBQrm:
32633 case VPSUBQrr:
32634 return true;
32635 }
32636 return false;
32637}
32638
32639bool isVPABSW(unsigned Opcode) {
32640 switch (Opcode) {
32641 case VPABSWYrm:
32642 case VPABSWYrr:
32643 case VPABSWZ128rm:
32644 case VPABSWZ128rmk:
32645 case VPABSWZ128rmkz:
32646 case VPABSWZ128rr:
32647 case VPABSWZ128rrk:
32648 case VPABSWZ128rrkz:
32649 case VPABSWZ256rm:
32650 case VPABSWZ256rmk:
32651 case VPABSWZ256rmkz:
32652 case VPABSWZ256rr:
32653 case VPABSWZ256rrk:
32654 case VPABSWZ256rrkz:
32655 case VPABSWZrm:
32656 case VPABSWZrmk:
32657 case VPABSWZrmkz:
32658 case VPABSWZrr:
32659 case VPABSWZrrk:
32660 case VPABSWZrrkz:
32661 case VPABSWrm:
32662 case VPABSWrr:
32663 return true;
32664 }
32665 return false;
32666}
32667
32668bool isVPCOMPRESSD(unsigned Opcode) {
32669 switch (Opcode) {
32670 case VPCOMPRESSDZ128mr:
32671 case VPCOMPRESSDZ128mrk:
32672 case VPCOMPRESSDZ128rr:
32673 case VPCOMPRESSDZ128rrk:
32674 case VPCOMPRESSDZ128rrkz:
32675 case VPCOMPRESSDZ256mr:
32676 case VPCOMPRESSDZ256mrk:
32677 case VPCOMPRESSDZ256rr:
32678 case VPCOMPRESSDZ256rrk:
32679 case VPCOMPRESSDZ256rrkz:
32680 case VPCOMPRESSDZmr:
32681 case VPCOMPRESSDZmrk:
32682 case VPCOMPRESSDZrr:
32683 case VPCOMPRESSDZrrk:
32684 case VPCOMPRESSDZrrkz:
32685 return true;
32686 }
32687 return false;
32688}
32689
32690bool isVPMOVUSQW(unsigned Opcode) {
32691 switch (Opcode) {
32692 case VPMOVUSQWZ128mr:
32693 case VPMOVUSQWZ128mrk:
32694 case VPMOVUSQWZ128rr:
32695 case VPMOVUSQWZ128rrk:
32696 case VPMOVUSQWZ128rrkz:
32697 case VPMOVUSQWZ256mr:
32698 case VPMOVUSQWZ256mrk:
32699 case VPMOVUSQWZ256rr:
32700 case VPMOVUSQWZ256rrk:
32701 case VPMOVUSQWZ256rrkz:
32702 case VPMOVUSQWZmr:
32703 case VPMOVUSQWZmrk:
32704 case VPMOVUSQWZrr:
32705 case VPMOVUSQWZrrk:
32706 case VPMOVUSQWZrrkz:
32707 return true;
32708 }
32709 return false;
32710}
32711
32712bool isBLENDVPD(unsigned Opcode) {
32713 switch (Opcode) {
32714 case BLENDVPDrm0:
32715 case BLENDVPDrr0:
32716 return true;
32717 }
32718 return false;
32719}
32720
32721bool isVFNMADD132BF16(unsigned Opcode) {
32722 switch (Opcode) {
32723 case VFNMADD132BF16Z128m:
32724 case VFNMADD132BF16Z128mb:
32725 case VFNMADD132BF16Z128mbk:
32726 case VFNMADD132BF16Z128mbkz:
32727 case VFNMADD132BF16Z128mk:
32728 case VFNMADD132BF16Z128mkz:
32729 case VFNMADD132BF16Z128r:
32730 case VFNMADD132BF16Z128rk:
32731 case VFNMADD132BF16Z128rkz:
32732 case VFNMADD132BF16Z256m:
32733 case VFNMADD132BF16Z256mb:
32734 case VFNMADD132BF16Z256mbk:
32735 case VFNMADD132BF16Z256mbkz:
32736 case VFNMADD132BF16Z256mk:
32737 case VFNMADD132BF16Z256mkz:
32738 case VFNMADD132BF16Z256r:
32739 case VFNMADD132BF16Z256rk:
32740 case VFNMADD132BF16Z256rkz:
32741 case VFNMADD132BF16Zm:
32742 case VFNMADD132BF16Zmb:
32743 case VFNMADD132BF16Zmbk:
32744 case VFNMADD132BF16Zmbkz:
32745 case VFNMADD132BF16Zmk:
32746 case VFNMADD132BF16Zmkz:
32747 case VFNMADD132BF16Zr:
32748 case VFNMADD132BF16Zrk:
32749 case VFNMADD132BF16Zrkz:
32750 return true;
32751 }
32752 return false;
32753}
32754
32755bool isVPMOVQB(unsigned Opcode) {
32756 switch (Opcode) {
32757 case VPMOVQBZ128mr:
32758 case VPMOVQBZ128mrk:
32759 case VPMOVQBZ128rr:
32760 case VPMOVQBZ128rrk:
32761 case VPMOVQBZ128rrkz:
32762 case VPMOVQBZ256mr:
32763 case VPMOVQBZ256mrk:
32764 case VPMOVQBZ256rr:
32765 case VPMOVQBZ256rrk:
32766 case VPMOVQBZ256rrkz:
32767 case VPMOVQBZmr:
32768 case VPMOVQBZmrk:
32769 case VPMOVQBZrr:
32770 case VPMOVQBZrrk:
32771 case VPMOVQBZrrkz:
32772 return true;
32773 }
32774 return false;
32775}
32776
32777bool isVBLENDVPS(unsigned Opcode) {
32778 switch (Opcode) {
32779 case VBLENDVPSYrmr:
32780 case VBLENDVPSYrrr:
32781 case VBLENDVPSrmr:
32782 case VBLENDVPSrrr:
32783 return true;
32784 }
32785 return false;
32786}
32787
32788bool isKSHIFTLQ(unsigned Opcode) {
32789 return Opcode == KSHIFTLQki;
32790}
32791
32792bool isPMOVSXWD(unsigned Opcode) {
32793 switch (Opcode) {
32794 case PMOVSXWDrm:
32795 case PMOVSXWDrr:
32796 return true;
32797 }
32798 return false;
32799}
32800
32801bool isPHSUBSW(unsigned Opcode) {
32802 switch (Opcode) {
32803 case MMX_PHSUBSWrm:
32804 case MMX_PHSUBSWrr:
32805 case PHSUBSWrm:
32806 case PHSUBSWrr:
32807 return true;
32808 }
32809 return false;
32810}
32811
32812bool isPSRLQ(unsigned Opcode) {
32813 switch (Opcode) {
32814 case MMX_PSRLQri:
32815 case MMX_PSRLQrm:
32816 case MMX_PSRLQrr:
32817 case PSRLQri:
32818 case PSRLQrm:
32819 case PSRLQrr:
32820 return true;
32821 }
32822 return false;
32823}
32824
32825bool isVCVTPH2DQ(unsigned Opcode) {
32826 switch (Opcode) {
32827 case VCVTPH2DQZ128rm:
32828 case VCVTPH2DQZ128rmb:
32829 case VCVTPH2DQZ128rmbk:
32830 case VCVTPH2DQZ128rmbkz:
32831 case VCVTPH2DQZ128rmk:
32832 case VCVTPH2DQZ128rmkz:
32833 case VCVTPH2DQZ128rr:
32834 case VCVTPH2DQZ128rrk:
32835 case VCVTPH2DQZ128rrkz:
32836 case VCVTPH2DQZ256rm:
32837 case VCVTPH2DQZ256rmb:
32838 case VCVTPH2DQZ256rmbk:
32839 case VCVTPH2DQZ256rmbkz:
32840 case VCVTPH2DQZ256rmk:
32841 case VCVTPH2DQZ256rmkz:
32842 case VCVTPH2DQZ256rr:
32843 case VCVTPH2DQZ256rrk:
32844 case VCVTPH2DQZ256rrkz:
32845 case VCVTPH2DQZrm:
32846 case VCVTPH2DQZrmb:
32847 case VCVTPH2DQZrmbk:
32848 case VCVTPH2DQZrmbkz:
32849 case VCVTPH2DQZrmk:
32850 case VCVTPH2DQZrmkz:
32851 case VCVTPH2DQZrr:
32852 case VCVTPH2DQZrrb:
32853 case VCVTPH2DQZrrbk:
32854 case VCVTPH2DQZrrbkz:
32855 case VCVTPH2DQZrrk:
32856 case VCVTPH2DQZrrkz:
32857 return true;
32858 }
32859 return false;
32860}
32861
32862bool isFISUB(unsigned Opcode) {
32863 switch (Opcode) {
32864 case SUB_FI16m:
32865 case SUB_FI32m:
32866 return true;
32867 }
32868 return false;
32869}
32870
32871bool isVCVTPS2UDQ(unsigned Opcode) {
32872 switch (Opcode) {
32873 case VCVTPS2UDQZ128rm:
32874 case VCVTPS2UDQZ128rmb:
32875 case VCVTPS2UDQZ128rmbk:
32876 case VCVTPS2UDQZ128rmbkz:
32877 case VCVTPS2UDQZ128rmk:
32878 case VCVTPS2UDQZ128rmkz:
32879 case VCVTPS2UDQZ128rr:
32880 case VCVTPS2UDQZ128rrk:
32881 case VCVTPS2UDQZ128rrkz:
32882 case VCVTPS2UDQZ256rm:
32883 case VCVTPS2UDQZ256rmb:
32884 case VCVTPS2UDQZ256rmbk:
32885 case VCVTPS2UDQZ256rmbkz:
32886 case VCVTPS2UDQZ256rmk:
32887 case VCVTPS2UDQZ256rmkz:
32888 case VCVTPS2UDQZ256rr:
32889 case VCVTPS2UDQZ256rrk:
32890 case VCVTPS2UDQZ256rrkz:
32891 case VCVTPS2UDQZrm:
32892 case VCVTPS2UDQZrmb:
32893 case VCVTPS2UDQZrmbk:
32894 case VCVTPS2UDQZrmbkz:
32895 case VCVTPS2UDQZrmk:
32896 case VCVTPS2UDQZrmkz:
32897 case VCVTPS2UDQZrr:
32898 case VCVTPS2UDQZrrb:
32899 case VCVTPS2UDQZrrbk:
32900 case VCVTPS2UDQZrrbkz:
32901 case VCVTPS2UDQZrrk:
32902 case VCVTPS2UDQZrrkz:
32903 return true;
32904 }
32905 return false;
32906}
32907
32908bool isVMOVDDUP(unsigned Opcode) {
32909 switch (Opcode) {
32910 case VMOVDDUPYrm:
32911 case VMOVDDUPYrr:
32912 case VMOVDDUPZ128rm:
32913 case VMOVDDUPZ128rmk:
32914 case VMOVDDUPZ128rmkz:
32915 case VMOVDDUPZ128rr:
32916 case VMOVDDUPZ128rrk:
32917 case VMOVDDUPZ128rrkz:
32918 case VMOVDDUPZ256rm:
32919 case VMOVDDUPZ256rmk:
32920 case VMOVDDUPZ256rmkz:
32921 case VMOVDDUPZ256rr:
32922 case VMOVDDUPZ256rrk:
32923 case VMOVDDUPZ256rrkz:
32924 case VMOVDDUPZrm:
32925 case VMOVDDUPZrmk:
32926 case VMOVDDUPZrmkz:
32927 case VMOVDDUPZrr:
32928 case VMOVDDUPZrrk:
32929 case VMOVDDUPZrrkz:
32930 case VMOVDDUPrm:
32931 case VMOVDDUPrr:
32932 return true;
32933 }
32934 return false;
32935}
32936
32937bool isPCMPEQD(unsigned Opcode) {
32938 switch (Opcode) {
32939 case MMX_PCMPEQDrm:
32940 case MMX_PCMPEQDrr:
32941 case PCMPEQDrm:
32942 case PCMPEQDrr:
32943 return true;
32944 }
32945 return false;
32946}
32947
32948bool isVRSQRT28SD(unsigned Opcode) {
32949 switch (Opcode) {
32950 case VRSQRT28SDZm:
32951 case VRSQRT28SDZmk:
32952 case VRSQRT28SDZmkz:
32953 case VRSQRT28SDZr:
32954 case VRSQRT28SDZrb:
32955 case VRSQRT28SDZrbk:
32956 case VRSQRT28SDZrbkz:
32957 case VRSQRT28SDZrk:
32958 case VRSQRT28SDZrkz:
32959 return true;
32960 }
32961 return false;
32962}
32963
32964bool isTDPHBF8PS(unsigned Opcode) {
32965 return Opcode == TDPHBF8PS;
32966}
32967
32968bool isLODSW(unsigned Opcode) {
32969 return Opcode == LODSW;
32970}
32971
32972bool isVPOPCNTQ(unsigned Opcode) {
32973 switch (Opcode) {
32974 case VPOPCNTQZ128rm:
32975 case VPOPCNTQZ128rmb:
32976 case VPOPCNTQZ128rmbk:
32977 case VPOPCNTQZ128rmbkz:
32978 case VPOPCNTQZ128rmk:
32979 case VPOPCNTQZ128rmkz:
32980 case VPOPCNTQZ128rr:
32981 case VPOPCNTQZ128rrk:
32982 case VPOPCNTQZ128rrkz:
32983 case VPOPCNTQZ256rm:
32984 case VPOPCNTQZ256rmb:
32985 case VPOPCNTQZ256rmbk:
32986 case VPOPCNTQZ256rmbkz:
32987 case VPOPCNTQZ256rmk:
32988 case VPOPCNTQZ256rmkz:
32989 case VPOPCNTQZ256rr:
32990 case VPOPCNTQZ256rrk:
32991 case VPOPCNTQZ256rrkz:
32992 case VPOPCNTQZrm:
32993 case VPOPCNTQZrmb:
32994 case VPOPCNTQZrmbk:
32995 case VPOPCNTQZrmbkz:
32996 case VPOPCNTQZrmk:
32997 case VPOPCNTQZrmkz:
32998 case VPOPCNTQZrr:
32999 case VPOPCNTQZrrk:
33000 case VPOPCNTQZrrkz:
33001 return true;
33002 }
33003 return false;
33004}
33005
33006bool isKSHIFTRB(unsigned Opcode) {
33007 return Opcode == KSHIFTRBki;
33008}
33009
33010bool isVFNMADDPS(unsigned Opcode) {
33011 switch (Opcode) {
33012 case VFNMADDPS4Ymr:
33013 case VFNMADDPS4Yrm:
33014 case VFNMADDPS4Yrr:
33015 case VFNMADDPS4Yrr_REV:
33016 case VFNMADDPS4mr:
33017 case VFNMADDPS4rm:
33018 case VFNMADDPS4rr:
33019 case VFNMADDPS4rr_REV:
33020 return true;
33021 }
33022 return false;
33023}
33024
33025bool isCCMPCC(unsigned Opcode) {
33026 switch (Opcode) {
33027 case CCMP16mi:
33028 case CCMP16mi8:
33029 case CCMP16mr:
33030 case CCMP16ri:
33031 case CCMP16ri8:
33032 case CCMP16rm:
33033 case CCMP16rr:
33034 case CCMP16rr_REV:
33035 case CCMP32mi:
33036 case CCMP32mi8:
33037 case CCMP32mr:
33038 case CCMP32ri:
33039 case CCMP32ri8:
33040 case CCMP32rm:
33041 case CCMP32rr:
33042 case CCMP32rr_REV:
33043 case CCMP64mi32:
33044 case CCMP64mi8:
33045 case CCMP64mr:
33046 case CCMP64ri32:
33047 case CCMP64ri8:
33048 case CCMP64rm:
33049 case CCMP64rr:
33050 case CCMP64rr_REV:
33051 case CCMP8mi:
33052 case CCMP8mr:
33053 case CCMP8ri:
33054 case CCMP8rm:
33055 case CCMP8rr:
33056 case CCMP8rr_REV:
33057 return true;
33058 }
33059 return false;
33060}
33061
33062bool isFXRSTOR64(unsigned Opcode) {
33063 return Opcode == FXRSTOR64;
33064}
33065
33066bool isVFMSUBADD213PD(unsigned Opcode) {
33067 switch (Opcode) {
33068 case VFMSUBADD213PDYm:
33069 case VFMSUBADD213PDYr:
33070 case VFMSUBADD213PDZ128m:
33071 case VFMSUBADD213PDZ128mb:
33072 case VFMSUBADD213PDZ128mbk:
33073 case VFMSUBADD213PDZ128mbkz:
33074 case VFMSUBADD213PDZ128mk:
33075 case VFMSUBADD213PDZ128mkz:
33076 case VFMSUBADD213PDZ128r:
33077 case VFMSUBADD213PDZ128rk:
33078 case VFMSUBADD213PDZ128rkz:
33079 case VFMSUBADD213PDZ256m:
33080 case VFMSUBADD213PDZ256mb:
33081 case VFMSUBADD213PDZ256mbk:
33082 case VFMSUBADD213PDZ256mbkz:
33083 case VFMSUBADD213PDZ256mk:
33084 case VFMSUBADD213PDZ256mkz:
33085 case VFMSUBADD213PDZ256r:
33086 case VFMSUBADD213PDZ256rk:
33087 case VFMSUBADD213PDZ256rkz:
33088 case VFMSUBADD213PDZm:
33089 case VFMSUBADD213PDZmb:
33090 case VFMSUBADD213PDZmbk:
33091 case VFMSUBADD213PDZmbkz:
33092 case VFMSUBADD213PDZmk:
33093 case VFMSUBADD213PDZmkz:
33094 case VFMSUBADD213PDZr:
33095 case VFMSUBADD213PDZrb:
33096 case VFMSUBADD213PDZrbk:
33097 case VFMSUBADD213PDZrbkz:
33098 case VFMSUBADD213PDZrk:
33099 case VFMSUBADD213PDZrkz:
33100 case VFMSUBADD213PDm:
33101 case VFMSUBADD213PDr:
33102 return true;
33103 }
33104 return false;
33105}
33106
33107bool isVSQRTPH(unsigned Opcode) {
33108 switch (Opcode) {
33109 case VSQRTPHZ128m:
33110 case VSQRTPHZ128mb:
33111 case VSQRTPHZ128mbk:
33112 case VSQRTPHZ128mbkz:
33113 case VSQRTPHZ128mk:
33114 case VSQRTPHZ128mkz:
33115 case VSQRTPHZ128r:
33116 case VSQRTPHZ128rk:
33117 case VSQRTPHZ128rkz:
33118 case VSQRTPHZ256m:
33119 case VSQRTPHZ256mb:
33120 case VSQRTPHZ256mbk:
33121 case VSQRTPHZ256mbkz:
33122 case VSQRTPHZ256mk:
33123 case VSQRTPHZ256mkz:
33124 case VSQRTPHZ256r:
33125 case VSQRTPHZ256rk:
33126 case VSQRTPHZ256rkz:
33127 case VSQRTPHZm:
33128 case VSQRTPHZmb:
33129 case VSQRTPHZmbk:
33130 case VSQRTPHZmbkz:
33131 case VSQRTPHZmk:
33132 case VSQRTPHZmkz:
33133 case VSQRTPHZr:
33134 case VSQRTPHZrb:
33135 case VSQRTPHZrbk:
33136 case VSQRTPHZrbkz:
33137 case VSQRTPHZrk:
33138 case VSQRTPHZrkz:
33139 return true;
33140 }
33141 return false;
33142}
33143
33144bool isPOPF(unsigned Opcode) {
33145 return Opcode == POPF16;
33146}
33147
33148bool isVPSUBUSB(unsigned Opcode) {
33149 switch (Opcode) {
33150 case VPSUBUSBYrm:
33151 case VPSUBUSBYrr:
33152 case VPSUBUSBZ128rm:
33153 case VPSUBUSBZ128rmk:
33154 case VPSUBUSBZ128rmkz:
33155 case VPSUBUSBZ128rr:
33156 case VPSUBUSBZ128rrk:
33157 case VPSUBUSBZ128rrkz:
33158 case VPSUBUSBZ256rm:
33159 case VPSUBUSBZ256rmk:
33160 case VPSUBUSBZ256rmkz:
33161 case VPSUBUSBZ256rr:
33162 case VPSUBUSBZ256rrk:
33163 case VPSUBUSBZ256rrkz:
33164 case VPSUBUSBZrm:
33165 case VPSUBUSBZrmk:
33166 case VPSUBUSBZrmkz:
33167 case VPSUBUSBZrr:
33168 case VPSUBUSBZrrk:
33169 case VPSUBUSBZrrkz:
33170 case VPSUBUSBrm:
33171 case VPSUBUSBrr:
33172 return true;
33173 }
33174 return false;
33175}
33176
33177bool isTCVTROWPS2BF16L(unsigned Opcode) {
33178 switch (Opcode) {
33179 case TCVTROWPS2BF16Lrte:
33180 case TCVTROWPS2BF16Lrti:
33181 return true;
33182 }
33183 return false;
33184}
33185
33186bool isPREFETCHIT1(unsigned Opcode) {
33187 return Opcode == PREFETCHIT1;
33188}
33189
33190bool isVPADDSW(unsigned Opcode) {
33191 switch (Opcode) {
33192 case VPADDSWYrm:
33193 case VPADDSWYrr:
33194 case VPADDSWZ128rm:
33195 case VPADDSWZ128rmk:
33196 case VPADDSWZ128rmkz:
33197 case VPADDSWZ128rr:
33198 case VPADDSWZ128rrk:
33199 case VPADDSWZ128rrkz:
33200 case VPADDSWZ256rm:
33201 case VPADDSWZ256rmk:
33202 case VPADDSWZ256rmkz:
33203 case VPADDSWZ256rr:
33204 case VPADDSWZ256rrk:
33205 case VPADDSWZ256rrkz:
33206 case VPADDSWZrm:
33207 case VPADDSWZrmk:
33208 case VPADDSWZrmkz:
33209 case VPADDSWZrr:
33210 case VPADDSWZrrk:
33211 case VPADDSWZrrkz:
33212 case VPADDSWrm:
33213 case VPADDSWrr:
33214 return true;
33215 }
33216 return false;
33217}
33218
33219bool isVADDSUBPD(unsigned Opcode) {
33220 switch (Opcode) {
33221 case VADDSUBPDYrm:
33222 case VADDSUBPDYrr:
33223 case VADDSUBPDrm:
33224 case VADDSUBPDrr:
33225 return true;
33226 }
33227 return false;
33228}
33229
33230bool isKANDD(unsigned Opcode) {
33231 return Opcode == KANDDkk;
33232}
33233
33234bool isOUTSB(unsigned Opcode) {
33235 return Opcode == OUTSB;
33236}
33237
33238bool isPREFETCHRST2(unsigned Opcode) {
33239 return Opcode == PREFETCHRST2;
33240}
33241
33242bool isFNSTSW(unsigned Opcode) {
33243 switch (Opcode) {
33244 case FNSTSW16r:
33245 case FNSTSWm:
33246 return true;
33247 }
33248 return false;
33249}
33250
33251bool isPMINSB(unsigned Opcode) {
33252 switch (Opcode) {
33253 case PMINSBrm:
33254 case PMINSBrr:
33255 return true;
33256 }
33257 return false;
33258}
33259
33260#endif // GET_X86_MNEMONIC_TABLES_CPP
33261
33262} // end namespace X86
33263} // end namespace llvm