1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* X86 Mnemonic tables *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_X86_MNEMONIC_TABLES_H
10#undef GET_X86_MNEMONIC_TABLES_H
11
12namespace llvm::X86 {
13
14bool isFSUBRP(unsigned Opcode);
15bool isVPDPBUSDS(unsigned Opcode);
16bool isPUNPCKLWD(unsigned Opcode);
17bool isVREDUCEBF16(unsigned Opcode);
18bool isPUNPCKLQDQ(unsigned Opcode);
19bool isRDFSBASE(unsigned Opcode);
20bool isVPCMOV(unsigned Opcode);
21bool isVDIVSD(unsigned Opcode);
22bool isVCVTTPS2IBS(unsigned Opcode);
23bool isVPEXTRW(unsigned Opcode);
24bool isLODSD(unsigned Opcode);
25bool isVPTESTNMQ(unsigned Opcode);
26bool isCVTSS2SD(unsigned Opcode);
27bool isVGETMANTPD(unsigned Opcode);
28bool isVMOVDQA64(unsigned Opcode);
29bool isINVLPG(unsigned Opcode);
30bool isVGETEXPBF16(unsigned Opcode);
31bool isVBROADCASTF64X4(unsigned Opcode);
32bool isVPERMI2Q(unsigned Opcode);
33bool isVPMOVSXBD(unsigned Opcode);
34bool isVFMSUB132SS(unsigned Opcode);
35bool isVPMOVUSDW(unsigned Opcode);
36bool isAAD(unsigned Opcode);
37bool isIDIV(unsigned Opcode);
38bool isCVTTPS2DQ(unsigned Opcode);
39bool isVBROADCASTF32X8(unsigned Opcode);
40bool isVFMSUBSS(unsigned Opcode);
41bool isEMMS(unsigned Opcode);
42bool isVPDPBSUD(unsigned Opcode);
43bool isPMOVSXWQ(unsigned Opcode);
44bool isPSRLW(unsigned Opcode);
45bool isMOVNTDQA(unsigned Opcode);
46bool isFUCOMPI(unsigned Opcode);
47bool isANDNPS(unsigned Opcode);
48bool isVINSERTF64X2(unsigned Opcode);
49bool isCLTS(unsigned Opcode);
50bool isSETSSBSY(unsigned Opcode);
51bool isVMULPD(unsigned Opcode);
52bool isVFMADDSUB132PS(unsigned Opcode);
53bool isVPMADCSWD(unsigned Opcode);
54bool isVSCATTERPF0DPS(unsigned Opcode);
55bool isXCHG(unsigned Opcode);
56bool isVGATHERPF1QPS(unsigned Opcode);
57bool isVCVTNEPS2BF16(unsigned Opcode);
58bool isVFMADDSS(unsigned Opcode);
59bool isINTO(unsigned Opcode);
60bool isANDPD(unsigned Opcode);
61bool isSEAMCALL(unsigned Opcode);
62bool isVPDPBSSDS(unsigned Opcode);
63bool isUNPCKHPS(unsigned Opcode);
64bool isSETZUCC(unsigned Opcode);
65bool isSHUFPD(unsigned Opcode);
66bool isFCMOVNB(unsigned Opcode);
67bool isCVTTSS2SI(unsigned Opcode);
68bool isEXTRQ(unsigned Opcode);
69bool isSHLD(unsigned Opcode);
70bool isVBROADCASTSS(unsigned Opcode);
71bool isCLUI(unsigned Opcode);
72bool isVINSERTI128(unsigned Opcode);
73bool isVBLENDPD(unsigned Opcode);
74bool isVPSHLDW(unsigned Opcode);
75bool isVCVTNEEPH2PS(unsigned Opcode);
76bool isVCVTTSD2SI(unsigned Opcode);
77bool isVSM4KEY4(unsigned Opcode);
78bool isWRMSRNS(unsigned Opcode);
79bool isCMPSB(unsigned Opcode);
80bool isVRCPBF16(unsigned Opcode);
81bool isMULSS(unsigned Opcode);
82bool isVMRUN(unsigned Opcode);
83bool isVPSRLVD(unsigned Opcode);
84bool isLEAVE(unsigned Opcode);
85bool isVGETMANTPS(unsigned Opcode);
86bool isXSHA256(unsigned Opcode);
87bool isBOUND(unsigned Opcode);
88bool isSFENCE(unsigned Opcode);
89bool isVPHADDD(unsigned Opcode);
90bool isADOX(unsigned Opcode);
91bool isVPSLLQ(unsigned Opcode);
92bool isVCVTPH2HF8(unsigned Opcode);
93bool isPFRSQIT1(unsigned Opcode);
94bool isCLAC(unsigned Opcode);
95bool isKNOTW(unsigned Opcode);
96bool isVCVTPH2PD(unsigned Opcode);
97bool isVAESENC(unsigned Opcode);
98bool isMOVNTI(unsigned Opcode);
99bool isFXCH(unsigned Opcode);
100bool isPOPP(unsigned Opcode);
101bool isVPBLENDMD(unsigned Opcode);
102bool isFSINCOS(unsigned Opcode);
103bool isVPMULLW(unsigned Opcode);
104bool isVPMOVSXBW(unsigned Opcode);
105bool isSTC(unsigned Opcode);
106bool isVPINSRB(unsigned Opcode);
107bool isLWPVAL(unsigned Opcode);
108bool isKXORB(unsigned Opcode);
109bool isRSTORSSP(unsigned Opcode);
110bool isVPRORQ(unsigned Opcode);
111bool isVSM3MSG1(unsigned Opcode);
112bool isFICOM(unsigned Opcode);
113bool isMAXPS(unsigned Opcode);
114bool isFNCLEX(unsigned Opcode);
115bool isVMOVMSKPS(unsigned Opcode);
116bool isVPMOVDB(unsigned Opcode);
117bool isLLWPCB(unsigned Opcode);
118bool isVMULSS(unsigned Opcode);
119bool isAESENCLAST(unsigned Opcode);
120bool isTILEMOVROW(unsigned Opcode);
121bool isVMINMAXPH(unsigned Opcode);
122bool isVPMAXUB(unsigned Opcode);
123bool isAAS(unsigned Opcode);
124bool isFADD(unsigned Opcode);
125bool isJMP(unsigned Opcode);
126bool isXCRYPTECB(unsigned Opcode);
127bool isPFRCPIT1(unsigned Opcode);
128bool isPMULHRW(unsigned Opcode);
129bool isVCVTPH2PS(unsigned Opcode);
130bool isVPBLENDVB(unsigned Opcode);
131bool isPCMPESTRI(unsigned Opcode);
132bool isSENDUIPI(unsigned Opcode);
133bool isFLDLN2(unsigned Opcode);
134bool isVPMACSWD(unsigned Opcode);
135bool isSHA1MSG1(unsigned Opcode);
136bool isVADDPS(unsigned Opcode);
137bool isVCVTPS2DQ(unsigned Opcode);
138bool isPFPNACC(unsigned Opcode);
139bool isFMUL(unsigned Opcode);
140bool isFNSAVE(unsigned Opcode);
141bool isCDQE(unsigned Opcode);
142bool isVPMACSDD(unsigned Opcode);
143bool isVSQRTPS(unsigned Opcode);
144bool isCMPSQ(unsigned Opcode);
145bool isVPSCATTERDD(unsigned Opcode);
146bool isVCVTTSD2USIS(unsigned Opcode);
147bool isVRNDSCALESD(unsigned Opcode);
148bool isSUBPS(unsigned Opcode);
149bool isVMAXSH(unsigned Opcode);
150bool isFLDZ(unsigned Opcode);
151bool isVFNMADD132SS(unsigned Opcode);
152bool isLGDTW(unsigned Opcode);
153bool isTCVTROWPS2PHH(unsigned Opcode);
154bool isINC(unsigned Opcode);
155bool isVPANDN(unsigned Opcode);
156bool isPABSB(unsigned Opcode);
157bool isVSHA512RNDS2(unsigned Opcode);
158bool isPHADDSW(unsigned Opcode);
159bool isVPMAXUD(unsigned Opcode);
160bool isVPMOVSQW(unsigned Opcode);
161bool isADDSUBPS(unsigned Opcode);
162bool isVPMACSSDQL(unsigned Opcode);
163bool isPXOR(unsigned Opcode);
164bool isVPSRAD(unsigned Opcode);
165bool isVPSHAB(unsigned Opcode);
166bool isBTR(unsigned Opcode);
167bool isKORW(unsigned Opcode);
168bool isVRANGESS(unsigned Opcode);
169bool isVCMPPS(unsigned Opcode);
170bool isVPLZCNTD(unsigned Opcode);
171bool isTDPBUUD(unsigned Opcode);
172bool isROUNDPS(unsigned Opcode);
173bool isFABS(unsigned Opcode);
174bool isSUBPD(unsigned Opcode);
175bool isGF2P8MULB(unsigned Opcode);
176bool isTZMSK(unsigned Opcode);
177bool isVMINMAXSD(unsigned Opcode);
178bool isANDPS(unsigned Opcode);
179bool isVEXTRACTF32X8(unsigned Opcode);
180bool isSEAMRET(unsigned Opcode);
181bool isVPCOMW(unsigned Opcode);
182bool isVFIXUPIMMPD(unsigned Opcode);
183bool isKANDND(unsigned Opcode);
184bool isVMRESUME(unsigned Opcode);
185bool isCVTPD2DQ(unsigned Opcode);
186bool isVFNMADD213PS(unsigned Opcode);
187bool isVPEXTRD(unsigned Opcode);
188bool isPACKUSWB(unsigned Opcode);
189bool isVEXTRACTI32X8(unsigned Opcode);
190bool isVHADDPD(unsigned Opcode);
191bool isVPSADBW(unsigned Opcode);
192bool isMOVDQ2Q(unsigned Opcode);
193bool isPUNPCKHBW(unsigned Opcode);
194bool isXOR(unsigned Opcode);
195bool isPSIGNB(unsigned Opcode);
196bool isVPHADDSW(unsigned Opcode);
197bool isFADDP(unsigned Opcode);
198bool isNEG(unsigned Opcode);
199bool isFLDLG2(unsigned Opcode);
200bool isFNOP(unsigned Opcode);
201bool isVMINSS(unsigned Opcode);
202bool isPCMPISTRM(unsigned Opcode);
203bool isVFMADD132SS(unsigned Opcode);
204bool isFDIVRP(unsigned Opcode);
205bool isPUSHAL(unsigned Opcode);
206bool isVPMACSDQL(unsigned Opcode);
207bool isSUBSD(unsigned Opcode);
208bool isVPBLENDMQ(unsigned Opcode);
209bool isVGATHERDPS(unsigned Opcode);
210bool isSYSRET(unsigned Opcode);
211bool isVPADDB(unsigned Opcode);
212bool isXEND(unsigned Opcode);
213bool isWRSSD(unsigned Opcode);
214bool isVMINMAXSS(unsigned Opcode);
215bool isVCVTDQ2PH(unsigned Opcode);
216bool isCVTPD2PS(unsigned Opcode);
217bool isMAXPD(unsigned Opcode);
218bool isRCPSS(unsigned Opcode);
219bool isVMOVAPD(unsigned Opcode);
220bool isVPSUBSB(unsigned Opcode);
221bool isRDTSC(unsigned Opcode);
222bool isVCVTTPS2UDQS(unsigned Opcode);
223bool isVPMADCSSWD(unsigned Opcode);
224bool isVFNMADD213PH(unsigned Opcode);
225bool isVGF2P8AFFINEQB(unsigned Opcode);
226bool isPMOVZXWD(unsigned Opcode);
227bool isPMINUD(unsigned Opcode);
228bool isVCVTPH2UW(unsigned Opcode);
229bool isPADDSW(unsigned Opcode);
230bool isXSUSLDTRK(unsigned Opcode);
231bool isLFENCE(unsigned Opcode);
232bool isCRC32(unsigned Opcode);
233bool isAESENCWIDE256KL(unsigned Opcode);
234bool isMOVAPD(unsigned Opcode);
235bool isVFMADD213PS(unsigned Opcode);
236bool isVPDPWUUDS(unsigned Opcode);
237bool isMOVSLDUP(unsigned Opcode);
238bool isCLDEMOTE(unsigned Opcode);
239bool isVFNMADD231PS(unsigned Opcode);
240bool isVMOVMSKPD(unsigned Opcode);
241bool isPREFETCHT0(unsigned Opcode);
242bool isVCVTNEOBF162PS(unsigned Opcode);
243bool isVPCMPUD(unsigned Opcode);
244bool isVMAXSD(unsigned Opcode);
245bool isVRCP28SD(unsigned Opcode);
246bool isVMAXPS(unsigned Opcode);
247bool isVPMOVD2M(unsigned Opcode);
248bool isVPMACSSWD(unsigned Opcode);
249bool isVUCOMISD(unsigned Opcode);
250bool isLTR(unsigned Opcode);
251bool isVCVTUSI2SH(unsigned Opcode);
252bool isVSCATTERPF1QPS(unsigned Opcode);
253bool isWRGSBASE(unsigned Opcode);
254bool isSTOSQ(unsigned Opcode);
255bool isVSQRTSD(unsigned Opcode);
256bool isVPERMIL2PD(unsigned Opcode);
257bool isVFCMADDCSH(unsigned Opcode);
258bool isVFMADDSUB213PS(unsigned Opcode);
259bool isPFSUB(unsigned Opcode);
260bool isVSQRTSS(unsigned Opcode);
261bool isVEXPANDPS(unsigned Opcode);
262bool isVPCOMPRESSW(unsigned Opcode);
263bool isPEXTRD(unsigned Opcode);
264bool isVCVTTPS2UQQS(unsigned Opcode);
265bool isSYSEXITQ(unsigned Opcode);
266bool isROUNDSD(unsigned Opcode);
267bool isVFMADD132BF16(unsigned Opcode);
268bool isFCOM(unsigned Opcode);
269bool isVFNMSUBSS(unsigned Opcode);
270bool isKSHIFTLW(unsigned Opcode);
271bool isSCASD(unsigned Opcode);
272bool isVMPTRLD(unsigned Opcode);
273bool isVAESDECLAST(unsigned Opcode);
274bool isVFMADDSUBPS(unsigned Opcode);
275bool isVCVTUQQ2PS(unsigned Opcode);
276bool isVPMOVUSDB(unsigned Opcode);
277bool isVPROTW(unsigned Opcode);
278bool isVDPPS(unsigned Opcode);
279bool isVRSQRT14PD(unsigned Opcode);
280bool isVTESTPD(unsigned Opcode);
281bool isVFNMADD231SH(unsigned Opcode);
282bool isENDBR64(unsigned Opcode);
283bool isMULSD(unsigned Opcode);
284bool isXRSTORS(unsigned Opcode);
285bool isPREFETCHNTA(unsigned Opcode);
286bool isVPCOMD(unsigned Opcode);
287bool isVPCOMUB(unsigned Opcode);
288bool isVPHSUBD(unsigned Opcode);
289bool isVBROADCASTI64X2(unsigned Opcode);
290bool isFPATAN(unsigned Opcode);
291bool isLOOPE(unsigned Opcode);
292bool isPCMPEQW(unsigned Opcode);
293bool isVFMADDCSH(unsigned Opcode);
294bool isVPDPBSSD(unsigned Opcode);
295bool isMOVRS(unsigned Opcode);
296bool isVFMSUBADD132PH(unsigned Opcode);
297bool isKADDW(unsigned Opcode);
298bool isPTEST(unsigned Opcode);
299bool isVRSQRT28PS(unsigned Opcode);
300bool isVGF2P8AFFINEINVQB(unsigned Opcode);
301bool isSERIALIZE(unsigned Opcode);
302bool isVPHADDWQ(unsigned Opcode);
303bool isVRNDSCALESH(unsigned Opcode);
304bool isAAA(unsigned Opcode);
305bool isVADDBF16(unsigned Opcode);
306bool isWRMSRLIST(unsigned Opcode);
307bool isVCVTPH2PSX(unsigned Opcode);
308bool isVFMSUB231PH(unsigned Opcode);
309bool isVGATHERQPD(unsigned Opcode);
310bool isKADDB(unsigned Opcode);
311bool isCVTPD2PI(unsigned Opcode);
312bool isVFNMSUB213PH(unsigned Opcode);
313bool isXORPS(unsigned Opcode);
314bool isVPCMPESTRI(unsigned Opcode);
315bool isVPADDSB(unsigned Opcode);
316bool isPOP2(unsigned Opcode);
317bool isRDMSRLIST(unsigned Opcode);
318bool isVPSHRDW(unsigned Opcode);
319bool isVPDPBUSD(unsigned Opcode);
320bool isVCMPPH(unsigned Opcode);
321bool isVANDNPD(unsigned Opcode);
322bool isSUB(unsigned Opcode);
323bool isVRSQRT28PD(unsigned Opcode);
324bool isVFNMADD132PH(unsigned Opcode);
325bool isVPMACSSWW(unsigned Opcode);
326bool isXSTORE(unsigned Opcode);
327bool isVPROTQ(unsigned Opcode);
328bool isVPHADDBD(unsigned Opcode);
329bool isVPMAXSB(unsigned Opcode);
330bool isVMOVDQU8(unsigned Opcode);
331bool isVPMOVSXWD(unsigned Opcode);
332bool isVMINMAXPD(unsigned Opcode);
333bool isSHA256RNDS2(unsigned Opcode);
334bool isKANDB(unsigned Opcode);
335bool isTPAUSE(unsigned Opcode);
336bool isPUSH(unsigned Opcode);
337bool isVRNDSCALESS(unsigned Opcode);
338bool isVRNDSCALEBF16(unsigned Opcode);
339bool isVPCMPISTRI(unsigned Opcode);
340bool isSTGI(unsigned Opcode);
341bool isSBB(unsigned Opcode);
342bool isBLCS(unsigned Opcode);
343bool isVCVTSD2SH(unsigned Opcode);
344bool isVPERMW(unsigned Opcode);
345bool isXRESLDTRK(unsigned Opcode);
346bool isAESENC256KL(unsigned Opcode);
347bool isVGATHERDPD(unsigned Opcode);
348bool isHRESET(unsigned Opcode);
349bool isVFMSUBADD231PD(unsigned Opcode);
350bool isVFRCZSS(unsigned Opcode);
351bool isMINPS(unsigned Opcode);
352bool isFPREM1(unsigned Opcode);
353bool isVPCMPUB(unsigned Opcode);
354bool isVSQRTPD(unsigned Opcode);
355bool isVFRCZPS(unsigned Opcode);
356bool isVFNMADD213SS(unsigned Opcode);
357bool isVPMOVDW(unsigned Opcode);
358bool isVCVTPH2HF8S(unsigned Opcode);
359bool isVPSHRDVQ(unsigned Opcode);
360bool isVBROADCASTSD(unsigned Opcode);
361bool isVSHUFPD(unsigned Opcode);
362bool isVPSUBSW(unsigned Opcode);
363bool isKUNPCKBW(unsigned Opcode);
364bool isVPBLENDD(unsigned Opcode);
365bool isUNPCKHPD(unsigned Opcode);
366bool isVFNMADD231SD(unsigned Opcode);
367bool isVPBROADCASTMW2D(unsigned Opcode);
368bool isVPMULTISHIFTQB(unsigned Opcode);
369bool isVP2INTERSECTQ(unsigned Opcode);
370bool isVFNMSUB132BF16(unsigned Opcode);
371bool isVFMADD213BF16(unsigned Opcode);
372bool isVPUNPCKHWD(unsigned Opcode);
373bool isVPERM2F128(unsigned Opcode);
374bool isINSD(unsigned Opcode);
375bool isLFS(unsigned Opcode);
376bool isFMULP(unsigned Opcode);
377bool isCWD(unsigned Opcode);
378bool isVDIVSS(unsigned Opcode);
379bool isVPSRLQ(unsigned Opcode);
380bool isFSQRT(unsigned Opcode);
381bool isJRCXZ(unsigned Opcode);
382bool isVPMOVMSKB(unsigned Opcode);
383bool isAESDEC256KL(unsigned Opcode);
384bool isFLDENV(unsigned Opcode);
385bool isVPHSUBWD(unsigned Opcode);
386bool isWBNOINVD(unsigned Opcode);
387bool isVEXPANDPD(unsigned Opcode);
388bool isFYL2XP1(unsigned Opcode);
389bool isPREFETCHT2(unsigned Opcode);
390bool isVPDPBSUDS(unsigned Opcode);
391bool isVSHA512MSG2(unsigned Opcode);
392bool isPMULHUW(unsigned Opcode);
393bool isKANDNB(unsigned Opcode);
394bool isVCVTUW2PH(unsigned Opcode);
395bool isAESDECWIDE256KL(unsigned Opcode);
396bool isVPGATHERDD(unsigned Opcode);
397bool isVREDUCESH(unsigned Opcode);
398bool isPOPFQ(unsigned Opcode);
399bool isPAVGUSB(unsigned Opcode);
400bool isVALIGND(unsigned Opcode);
401bool isVPHMINPOSUW(unsigned Opcode);
402bool isLIDTD(unsigned Opcode);
403bool isVPERMT2PD(unsigned Opcode);
404bool isVMLAUNCH(unsigned Opcode);
405bool isVPXORQ(unsigned Opcode);
406bool isMOVNTDQ(unsigned Opcode);
407bool isPOP2P(unsigned Opcode);
408bool isVADDPD(unsigned Opcode);
409bool isSMSW(unsigned Opcode);
410bool isVEXP2PD(unsigned Opcode);
411bool isPMULUDQ(unsigned Opcode);
412bool isIRET(unsigned Opcode);
413bool isMULPS(unsigned Opcode);
414bool isTDPBF8PS(unsigned Opcode);
415bool isVFNMSUBPD(unsigned Opcode);
416bool isPHADDW(unsigned Opcode);
417bool isRDSEED(unsigned Opcode);
418bool isVPSHLW(unsigned Opcode);
419bool isRMPUPDATE(unsigned Opcode);
420bool isVFMADD231PH(unsigned Opcode);
421bool isVPSHAD(unsigned Opcode);
422bool isCLWB(unsigned Opcode);
423bool isPSUBUSB(unsigned Opcode);
424bool isVCVTTSD2USI(unsigned Opcode);
425bool isVEXTRACTPS(unsigned Opcode);
426bool isMOVLPD(unsigned Opcode);
427bool isLGDTD(unsigned Opcode);
428bool isVPBROADCASTMB2Q(unsigned Opcode);
429bool isOUT(unsigned Opcode);
430bool isVMSAVE(unsigned Opcode);
431bool isVCVTQQ2PD(unsigned Opcode);
432bool isVFMADD213PH(unsigned Opcode);
433bool isFCMOVBE(unsigned Opcode);
434bool isMOVSHDUP(unsigned Opcode);
435bool isVPMOVUSQB(unsigned Opcode);
436bool isFIST(unsigned Opcode);
437bool isHADDPD(unsigned Opcode);
438bool isPACKSSWB(unsigned Opcode);
439bool isVPMACSSDQH(unsigned Opcode);
440bool isVFNMSUB132SD(unsigned Opcode);
441bool isVPMASKMOVQ(unsigned Opcode);
442bool isVCOMPRESSPD(unsigned Opcode);
443bool isVFMADD213SS(unsigned Opcode);
444bool isVPCMPQ(unsigned Opcode);
445bool isVADDSH(unsigned Opcode);
446bool isVFNMADDSD(unsigned Opcode);
447bool isUMWAIT(unsigned Opcode);
448bool isVPUNPCKHDQ(unsigned Opcode);
449bool isLCALL(unsigned Opcode);
450bool isAESDEC128KL(unsigned Opcode);
451bool isVSUBPS(unsigned Opcode);
452bool isFSTP(unsigned Opcode);
453bool isVCVTUDQ2PD(unsigned Opcode);
454bool isVPMOVSWB(unsigned Opcode);
455bool isVPANDNQ(unsigned Opcode);
456bool isSYSENTER(unsigned Opcode);
457bool isVPHADDWD(unsigned Opcode);
458bool isVMOVHPD(unsigned Opcode);
459bool isMOVHPD(unsigned Opcode);
460bool isVDIVPH(unsigned Opcode);
461bool isFFREE(unsigned Opcode);
462bool isVGATHERPF1DPS(unsigned Opcode);
463bool isVPCMPESTRIQ(unsigned Opcode);
464bool isVFNMADD231PD(unsigned Opcode);
465bool isVFCMULCPH(unsigned Opcode);
466bool isVPADDD(unsigned Opcode);
467bool isVSM3MSG2(unsigned Opcode);
468bool isVPCOMUQ(unsigned Opcode);
469bool isVERR(unsigned Opcode);
470bool isKORTESTQ(unsigned Opcode);
471bool isVFMSUB132SD(unsigned Opcode);
472bool isTILEZERO(unsigned Opcode);
473bool isPFADD(unsigned Opcode);
474bool isVCVTSI2SD(unsigned Opcode);
475bool isTILELOADDRS(unsigned Opcode);
476bool isVSTMXCSR(unsigned Opcode);
477bool isVCVTTSH2SI(unsigned Opcode);
478bool isRET(unsigned Opcode);
479bool isLZCNT(unsigned Opcode);
480bool isMULPD(unsigned Opcode);
481bool isVBROADCASTI32X2(unsigned Opcode);
482bool isVCVTPH2W(unsigned Opcode);
483bool isCQO(unsigned Opcode);
484bool isFSUBR(unsigned Opcode);
485bool isDPPD(unsigned Opcode);
486bool isFCOS(unsigned Opcode);
487bool isXSAVES(unsigned Opcode);
488bool isTZCNT(unsigned Opcode);
489bool isLJMP(unsigned Opcode);
490bool isCMOVCC(unsigned Opcode);
491bool isVCVTBIASPH2HF8(unsigned Opcode);
492bool isINVEPT(unsigned Opcode);
493bool isADDSUBPD(unsigned Opcode);
494bool isVMOVSHDUP(unsigned Opcode);
495bool isKSHIFTRD(unsigned Opcode);
496bool isVCVTSS2SD(unsigned Opcode);
497bool isPADDQ(unsigned Opcode);
498bool isVEXTRACTI64X4(unsigned Opcode);
499bool isVFMSUB231SS(unsigned Opcode);
500bool isVPCMPEQB(unsigned Opcode);
501bool isVPTERNLOGD(unsigned Opcode);
502bool isLEA(unsigned Opcode);
503bool isPSUBB(unsigned Opcode);
504bool isKADDQ(unsigned Opcode);
505bool isMOVSX(unsigned Opcode);
506bool isVALIGNQ(unsigned Opcode);
507bool isVCVTNE2PS2BF16(unsigned Opcode);
508bool isVPSRAW(unsigned Opcode);
509bool isVFMSUBADD231PH(unsigned Opcode);
510bool isCVTDQ2PS(unsigned Opcode);
511bool isFBLD(unsigned Opcode);
512bool isLMSW(unsigned Opcode);
513bool isWRMSR(unsigned Opcode);
514bool isMINSS(unsigned Opcode);
515bool isFSCALE(unsigned Opcode);
516bool isVFNMADD213SH(unsigned Opcode);
517bool isIMULZU(unsigned Opcode);
518bool isVPHADDUBD(unsigned Opcode);
519bool isRDSSPQ(unsigned Opcode);
520bool isVCVTBF162IBS(unsigned Opcode);
521bool isLGDT(unsigned Opcode);
522bool isVPSHLDVD(unsigned Opcode);
523bool isPFCMPGT(unsigned Opcode);
524bool isVRNDSCALEPH(unsigned Opcode);
525bool isJCXZ(unsigned Opcode);
526bool isVPMOVZXBW(unsigned Opcode);
527bool isVFMADDSUB231PD(unsigned Opcode);
528bool isVBLENDMPD(unsigned Opcode);
529bool isHSUBPS(unsigned Opcode);
530bool isPREFETCHIT0(unsigned Opcode);
531bool isKTESTD(unsigned Opcode);
532bool isVCVTNEOPH2PS(unsigned Opcode);
533bool isVBLENDVPD(unsigned Opcode);
534bool isVCVTSS2USI(unsigned Opcode);
535bool isVCVTTPS2DQS(unsigned Opcode);
536bool isVPANDD(unsigned Opcode);
537bool isPMINSW(unsigned Opcode);
538bool isSTAC(unsigned Opcode);
539bool isVFMSUB213PS(unsigned Opcode);
540bool isPOPAL(unsigned Opcode);
541bool isVCVTPS2UQQ(unsigned Opcode);
542bool isRDRAND(unsigned Opcode);
543bool isJCC(unsigned Opcode);
544bool isVPMINSQ(unsigned Opcode);
545bool isVADDSD(unsigned Opcode);
546bool isDPPS(unsigned Opcode);
547bool isPINSRQ(unsigned Opcode);
548bool isVUCOMISS(unsigned Opcode);
549bool isVPDPWSUD(unsigned Opcode);
550bool isKANDNW(unsigned Opcode);
551bool isAOR(unsigned Opcode);
552bool isPMAXUB(unsigned Opcode);
553bool isANDNPD(unsigned Opcode);
554bool isINVPCID(unsigned Opcode);
555bool isRDGSBASE(unsigned Opcode);
556bool isVPMOVSQD(unsigned Opcode);
557bool isBT(unsigned Opcode);
558bool isVPROLVQ(unsigned Opcode);
559bool isVFMADDSUB132PD(unsigned Opcode);
560bool isRORX(unsigned Opcode);
561bool isPADDUSW(unsigned Opcode);
562bool isPFNACC(unsigned Opcode);
563bool isAND(unsigned Opcode);
564bool isPSLLQ(unsigned Opcode);
565bool isVFMSUB132PH(unsigned Opcode);
566bool isXSAVE(unsigned Opcode);
567bool isKNOTQ(unsigned Opcode);
568bool isXTEST(unsigned Opcode);
569bool isVINSERTPS(unsigned Opcode);
570bool isXSAVEOPT(unsigned Opcode);
571bool isLDS(unsigned Opcode);
572bool isVFMADDSUB213PD(unsigned Opcode);
573bool isVINSERTF32X4(unsigned Opcode);
574bool isVRSQRTPS(unsigned Opcode);
575bool isVSUBPH(unsigned Opcode);
576bool isPMOVSXBW(unsigned Opcode);
577bool isVPSRLDQ(unsigned Opcode);
578bool isADC(unsigned Opcode);
579bool isPHADDD(unsigned Opcode);
580bool isVDPPHPS(unsigned Opcode);
581bool isVMINPH(unsigned Opcode);
582bool isVMINSD(unsigned Opcode);
583bool isVROUNDPD(unsigned Opcode);
584bool isVFCMADDCPH(unsigned Opcode);
585bool isINCSSPQ(unsigned Opcode);
586bool isVPUNPCKLDQ(unsigned Opcode);
587bool isVMINSH(unsigned Opcode);
588bool isINSERTQ(unsigned Opcode);
589bool isBLCI(unsigned Opcode);
590bool isHLT(unsigned Opcode);
591bool isVPCOMUW(unsigned Opcode);
592bool isVPMOVSXDQ(unsigned Opcode);
593bool isVFNMSUB231PS(unsigned Opcode);
594bool isVFNMSUB213SH(unsigned Opcode);
595bool isVCVTTPD2UQQ(unsigned Opcode);
596bool isSQRTSS(unsigned Opcode);
597bool isIMUL(unsigned Opcode);
598bool isVCVTSS2SI(unsigned Opcode);
599bool isPUSHAW(unsigned Opcode);
600bool isSTOSD(unsigned Opcode);
601bool isPSRLDQ(unsigned Opcode);
602bool isVSCATTERQPS(unsigned Opcode);
603bool isFIDIV(unsigned Opcode);
604bool isVFMSUB213PD(unsigned Opcode);
605bool isVFMADDSUB231PH(unsigned Opcode);
606bool isTDCALL(unsigned Opcode);
607bool isPVALIDATE(unsigned Opcode);
608bool isVPSHUFLW(unsigned Opcode);
609bool isPCLMULQDQ(unsigned Opcode);
610bool isCMPXCHG8B(unsigned Opcode);
611bool isVPMOVM2B(unsigned Opcode);
612bool isVCVTUDQ2PH(unsigned Opcode);
613bool isPEXTRQ(unsigned Opcode);
614bool isXCRYPTCTR(unsigned Opcode);
615bool isVREDUCEPH(unsigned Opcode);
616bool isUCOMISD(unsigned Opcode);
617bool isOUTSD(unsigned Opcode);
618bool isSUBSS(unsigned Opcode);
619bool isVFMSUBPS(unsigned Opcode);
620bool isVPBLENDW(unsigned Opcode);
621bool isBZHI(unsigned Opcode);
622bool isVPRORVD(unsigned Opcode);
623bool isRMPQUERY(unsigned Opcode);
624bool isVPEXPANDB(unsigned Opcode);
625bool isVPSCATTERDQ(unsigned Opcode);
626bool isPSMASH(unsigned Opcode);
627bool isVPSHLDQ(unsigned Opcode);
628bool isVSCATTERPF1DPD(unsigned Opcode);
629bool isMONTMUL(unsigned Opcode);
630bool isVCVTPH2UQQ(unsigned Opcode);
631bool isPSLLD(unsigned Opcode);
632bool isSAR(unsigned Opcode);
633bool isLDTILECFG(unsigned Opcode);
634bool isPMINUB(unsigned Opcode);
635bool isVCVTNEEBF162PS(unsigned Opcode);
636bool isMOVDIR64B(unsigned Opcode);
637bool isSTR(unsigned Opcode);
638bool isKANDNQ(unsigned Opcode);
639bool isBSF(unsigned Opcode);
640bool isVPDPBUUDS(unsigned Opcode);
641bool isINCSSPD(unsigned Opcode);
642bool isSQRTPS(unsigned Opcode);
643bool isCMPXCHG(unsigned Opcode);
644bool isVPSIGNW(unsigned Opcode);
645bool isVCOMISBF16(unsigned Opcode);
646bool isLES(unsigned Opcode);
647bool isCVTSS2SI(unsigned Opcode);
648bool isVPMOVUSWB(unsigned Opcode);
649bool isFCOMPI(unsigned Opcode);
650bool isPUNPCKHWD(unsigned Opcode);
651bool isPFACC(unsigned Opcode);
652bool isVPTESTNMW(unsigned Opcode);
653bool isVPMULDQ(unsigned Opcode);
654bool isSHRX(unsigned Opcode);
655bool isKXORQ(unsigned Opcode);
656bool isVGETEXPSD(unsigned Opcode);
657bool isV4FNMADDPS(unsigned Opcode);
658bool isVFNMSUB231SD(unsigned Opcode);
659bool isVPSHLD(unsigned Opcode);
660bool isPAVGB(unsigned Opcode);
661bool isPMOVZXBD(unsigned Opcode);
662bool isKORTESTW(unsigned Opcode);
663bool isVSHUFPS(unsigned Opcode);
664bool isAESENCWIDE128KL(unsigned Opcode);
665bool isVPXORD(unsigned Opcode);
666bool isVPSHAW(unsigned Opcode);
667bool isVFMSUB132BF16(unsigned Opcode);
668bool isVPERMT2B(unsigned Opcode);
669bool isVFMADD213PD(unsigned Opcode);
670bool isVPGATHERQD(unsigned Opcode);
671bool isVFNMSUB213BF16(unsigned Opcode);
672bool isVCVTPS2IBS(unsigned Opcode);
673bool isVPCMPGTW(unsigned Opcode);
674bool isVMOVRSB(unsigned Opcode);
675bool isVGETMANTSH(unsigned Opcode);
676bool isVANDPS(unsigned Opcode);
677bool isVDIVPS(unsigned Opcode);
678bool isVANDNPS(unsigned Opcode);
679bool isVPBROADCASTW(unsigned Opcode);
680bool isFLDL2T(unsigned Opcode);
681bool isVPERMB(unsigned Opcode);
682bool isFCMOVNBE(unsigned Opcode);
683bool isVCVTTPH2W(unsigned Opcode);
684bool isPMOVZXBQ(unsigned Opcode);
685bool isPF2ID(unsigned Opcode);
686bool isVFNMADD132PD(unsigned Opcode);
687bool isPMULHRSW(unsigned Opcode);
688bool isKADDD(unsigned Opcode);
689bool isVFNMSUB132SH(unsigned Opcode);
690bool isUIRET(unsigned Opcode);
691bool isBSR(unsigned Opcode);
692bool isPCMPEQQ(unsigned Opcode);
693bool isCDQ(unsigned Opcode);
694bool isPMAXSW(unsigned Opcode);
695bool isSIDTD(unsigned Opcode);
696bool isVCVTPS2PHX(unsigned Opcode);
697bool isVPSLLVQ(unsigned Opcode);
698bool isMOVQ(unsigned Opcode);
699bool isVCMPBF16(unsigned Opcode);
700bool isPREFETCH(unsigned Opcode);
701bool isCLRSSBSY(unsigned Opcode);
702bool isTCVTROWPS2PHL(unsigned Opcode);
703bool isPSHUFW(unsigned Opcode);
704bool isVPDPWSUDS(unsigned Opcode);
705bool isVPMOVSXBQ(unsigned Opcode);
706bool isFICOMP(unsigned Opcode);
707bool isVLDMXCSR(unsigned Opcode);
708bool isVPSUBUSW(unsigned Opcode);
709bool isVFNMSUB132SS(unsigned Opcode);
710bool isRETF(unsigned Opcode);
711bool isKMOVQ(unsigned Opcode);
712bool isVPADDUSW(unsigned Opcode);
713bool isPACKSSDW(unsigned Opcode);
714bool isUMONITOR(unsigned Opcode);
715bool isENQCMDS(unsigned Opcode);
716bool isVCOMXSD(unsigned Opcode);
717bool isVPMAXSQ(unsigned Opcode);
718bool isVFMSUB213BF16(unsigned Opcode);
719bool isVPERMT2Q(unsigned Opcode);
720bool isFDECSTP(unsigned Opcode);
721bool isVPTESTMQ(unsigned Opcode);
722bool isVRCP14PD(unsigned Opcode);
723bool isARPL(unsigned Opcode);
724bool isVFMSUB213SD(unsigned Opcode);
725bool isJMPABS(unsigned Opcode);
726bool isVUNPCKHPS(unsigned Opcode);
727bool isVFNMADDSS(unsigned Opcode);
728bool isSIDT(unsigned Opcode);
729bool isVPCMPGTB(unsigned Opcode);
730bool isVPRORD(unsigned Opcode);
731bool isVSUBSS(unsigned Opcode);
732bool isPUSHFQ(unsigned Opcode);
733bool isVCVTHF82PH(unsigned Opcode);
734bool isVPCLMULQDQ(unsigned Opcode);
735bool isVPADDUSB(unsigned Opcode);
736bool isVPCMPD(unsigned Opcode);
737bool isMOVSD(unsigned Opcode);
738bool isPSUBUSW(unsigned Opcode);
739bool isVFMSUBADD132PS(unsigned Opcode);
740bool isMOVMSKPS(unsigned Opcode);
741bool isVFIXUPIMMSS(unsigned Opcode);
742bool isMFENCE(unsigned Opcode);
743bool isFTST(unsigned Opcode);
744bool isVPMADDWD(unsigned Opcode);
745bool isPOP(unsigned Opcode);
746bool isPSUBW(unsigned Opcode);
747bool isBSWAP(unsigned Opcode);
748bool isPFMIN(unsigned Opcode);
749bool isVFPCLASSPD(unsigned Opcode);
750bool isVPSHRDVD(unsigned Opcode);
751bool isPADDW(unsigned Opcode);
752bool isCVTSI2SD(unsigned Opcode);
753bool isENQCMD(unsigned Opcode);
754bool isXSHA1(unsigned Opcode);
755bool isVFNMADD132SD(unsigned Opcode);
756bool isMOVZX(unsigned Opcode);
757bool isVFIXUPIMMSD(unsigned Opcode);
758bool isINVD(unsigned Opcode);
759bool isVFIXUPIMMPS(unsigned Opcode);
760bool isMOVDQU(unsigned Opcode);
761bool isVFPCLASSPS(unsigned Opcode);
762bool isMOVSQ(unsigned Opcode);
763bool isAESDECWIDE128KL(unsigned Opcode);
764bool isROUNDSS(unsigned Opcode);
765bool isVPERMILPS(unsigned Opcode);
766bool isVPMOVW2M(unsigned Opcode);
767bool isVMULSD(unsigned Opcode);
768bool isVPERMI2W(unsigned Opcode);
769bool isVPSHUFB(unsigned Opcode);
770bool isFST(unsigned Opcode);
771bool isVPHSUBW(unsigned Opcode);
772bool isVREDUCESS(unsigned Opcode);
773bool isFRNDINT(unsigned Opcode);
774bool isSHR(unsigned Opcode);
775bool isLOOPNE(unsigned Opcode);
776bool isVCVTTPH2UQQ(unsigned Opcode);
777bool isSHA1NEXTE(unsigned Opcode);
778bool isVFMADD132SD(unsigned Opcode);
779bool isPSRAW(unsigned Opcode);
780bool isVPBROADCASTQ(unsigned Opcode);
781bool isCLC(unsigned Opcode);
782bool isPOPAW(unsigned Opcode);
783bool isTCMMIMFP16PS(unsigned Opcode);
784bool isVCVTTPS2UQQ(unsigned Opcode);
785bool isVCVTQQ2PH(unsigned Opcode);
786bool isVMOVUPD(unsigned Opcode);
787bool isFPTAN(unsigned Opcode);
788bool isVMASKMOVPD(unsigned Opcode);
789bool isVMOVLHPS(unsigned Opcode);
790bool isAESKEYGENASSIST(unsigned Opcode);
791bool isXSAVEOPT64(unsigned Opcode);
792bool isXSAVEC(unsigned Opcode);
793bool isVPLZCNTQ(unsigned Opcode);
794bool isVPSUBW(unsigned Opcode);
795bool isCMPCCXADD(unsigned Opcode);
796bool isVFMSUBADD213PH(unsigned Opcode);
797bool isVFMADDSUBPD(unsigned Opcode);
798bool isVPMINSW(unsigned Opcode);
799bool isVFNMSUB132PS(unsigned Opcode);
800bool isVMOVAPS(unsigned Opcode);
801bool isVPEXTRQ(unsigned Opcode);
802bool isVSCALEFSH(unsigned Opcode);
803bool isVCVTPD2PS(unsigned Opcode);
804bool isCLGI(unsigned Opcode);
805bool isVAESDEC(unsigned Opcode);
806bool isPFMUL(unsigned Opcode);
807bool isVCVTBIASPH2BF8S(unsigned Opcode);
808bool isMOVDIRI(unsigned Opcode);
809bool isSHUFPS(unsigned Opcode);
810bool isVFNMSUB231SS(unsigned Opcode);
811bool isVMWRITE(unsigned Opcode);
812bool isVINSERTF128(unsigned Opcode);
813bool isFISUBR(unsigned Opcode);
814bool isVINSERTI32X4(unsigned Opcode);
815bool isVPSLLDQ(unsigned Opcode);
816bool isPOPCNT(unsigned Opcode);
817bool isVXORPD(unsigned Opcode);
818bool isXLATB(unsigned Opcode);
819bool isDIV(unsigned Opcode);
820bool isVPSHLDVQ(unsigned Opcode);
821bool isMOVDDUP(unsigned Opcode);
822bool isVMOVDQU64(unsigned Opcode);
823bool isVPCOMPRESSQ(unsigned Opcode);
824bool isVFMSUBADD132PD(unsigned Opcode);
825bool isADDSD(unsigned Opcode);
826bool isBLENDPD(unsigned Opcode);
827bool isVPERMILPD(unsigned Opcode);
828bool isPMADDUBSW(unsigned Opcode);
829bool isPOPFD(unsigned Opcode);
830bool isCMPSW(unsigned Opcode);
831bool isLDMXCSR(unsigned Opcode);
832bool isVMULPS(unsigned Opcode);
833bool isVROUNDSD(unsigned Opcode);
834bool isVFMADD132PD(unsigned Opcode);
835bool isVPANDQ(unsigned Opcode);
836bool isVPSRAQ(unsigned Opcode);
837bool isVCOMISD(unsigned Opcode);
838bool isVCVTBIASPH2BF8(unsigned Opcode);
839bool isFFREEP(unsigned Opcode);
840bool isVFNMADD213PD(unsigned Opcode);
841bool isVCMPPD(unsigned Opcode);
842bool isVFNMSUB132PH(unsigned Opcode);
843bool isVPHADDBW(unsigned Opcode);
844bool isVPPERM(unsigned Opcode);
845bool isVCVTPS2PD(unsigned Opcode);
846bool isCBW(unsigned Opcode);
847bool isVMOVUPS(unsigned Opcode);
848bool isVPMAXUQ(unsigned Opcode);
849bool isWRSSQ(unsigned Opcode);
850bool isPACKUSDW(unsigned Opcode);
851bool isVCVTTBF162IBS(unsigned Opcode);
852bool isXBEGIN(unsigned Opcode);
853bool isVCVTPD2UQQ(unsigned Opcode);
854bool isFCMOVB(unsigned Opcode);
855bool isNOP(unsigned Opcode);
856bool isVPABSQ(unsigned Opcode);
857bool isVTESTPS(unsigned Opcode);
858bool isPHSUBW(unsigned Opcode);
859bool isPUSH2P(unsigned Opcode);
860bool isFISTTP(unsigned Opcode);
861bool isCFCMOVCC(unsigned Opcode);
862bool isVPINSRD(unsigned Opcode);
863bool isPCMPESTRM(unsigned Opcode);
864bool isVFNMSUB213PS(unsigned Opcode);
865bool isPHSUBD(unsigned Opcode);
866bool isVCVTTPD2DQS(unsigned Opcode);
867bool isSLDT(unsigned Opcode);
868bool isVHADDPS(unsigned Opcode);
869bool isVMOVNTDQ(unsigned Opcode);
870bool isVPMINSD(unsigned Opcode);
871bool isVFRCZSD(unsigned Opcode);
872bool isVPTESTMW(unsigned Opcode);
873bool isVPMOVZXWD(unsigned Opcode);
874bool isPSADBW(unsigned Opcode);
875bool isVCVTSD2SI(unsigned Opcode);
876bool isVMAXPH(unsigned Opcode);
877bool isLODSB(unsigned Opcode);
878bool isPHMINPOSUW(unsigned Opcode);
879bool isVPROLVD(unsigned Opcode);
880bool isWRFSBASE(unsigned Opcode);
881bool isVRSQRT14PS(unsigned Opcode);
882bool isVPHSUBDQ(unsigned Opcode);
883bool isIRETD(unsigned Opcode);
884bool isVMOVRSD(unsigned Opcode);
885bool isCVTSI2SS(unsigned Opcode);
886bool isVPMULHRSW(unsigned Opcode);
887bool isPI2FD(unsigned Opcode);
888bool isGF2P8AFFINEQB(unsigned Opcode);
889bool isPAND(unsigned Opcode);
890bool isVFNMSUB231SH(unsigned Opcode);
891bool isVCVTPH2BF8(unsigned Opcode);
892bool isVMOVHLPS(unsigned Opcode);
893bool isPEXTRB(unsigned Opcode);
894bool isVMMCALL(unsigned Opcode);
895bool isKNOTD(unsigned Opcode);
896bool isVCVTSH2SS(unsigned Opcode);
897bool isVPUNPCKLQDQ(unsigned Opcode);
898bool isVPERMIL2PS(unsigned Opcode);
899bool isVPCMPGTD(unsigned Opcode);
900bool isCMPXCHG16B(unsigned Opcode);
901bool isTDPHF8PS(unsigned Opcode);
902bool isVZEROUPPER(unsigned Opcode);
903bool isMOVAPS(unsigned Opcode);
904bool isVPCMPW(unsigned Opcode);
905bool isFUCOMPP(unsigned Opcode);
906bool isXSETBV(unsigned Opcode);
907bool isSLWPCB(unsigned Opcode);
908bool isSCASW(unsigned Opcode);
909bool isFCMOVNE(unsigned Opcode);
910bool isPBNDKB(unsigned Opcode);
911bool isVPMULLD(unsigned Opcode);
912bool isVP4DPWSSDS(unsigned Opcode);
913bool isVCVT2PH2HF8(unsigned Opcode);
914bool isPINSRW(unsigned Opcode);
915bool isVCVTSI2SH(unsigned Opcode);
916bool isVINSERTF32X8(unsigned Opcode);
917bool isKSHIFTLB(unsigned Opcode);
918bool isSEAMOPS(unsigned Opcode);
919bool isVPMULUDQ(unsigned Opcode);
920bool isVPMOVSQB(unsigned Opcode);
921bool isVPTESTMD(unsigned Opcode);
922bool isVPHADDDQ(unsigned Opcode);
923bool isKUNPCKDQ(unsigned Opcode);
924bool isT1MSKC(unsigned Opcode);
925bool isVPCOMB(unsigned Opcode);
926bool isVBLENDPS(unsigned Opcode);
927bool isPTWRITE(unsigned Opcode);
928bool isVCVTPH2BF8S(unsigned Opcode);
929bool isCVTPS2PI(unsigned Opcode);
930bool isVPROTD(unsigned Opcode);
931bool isCALL(unsigned Opcode);
932bool isTILELOADDRST1(unsigned Opcode);
933bool isVPERMPS(unsigned Opcode);
934bool isVPSHUFBITQMB(unsigned Opcode);
935bool isVMOVSLDUP(unsigned Opcode);
936bool isINVLPGA(unsigned Opcode);
937bool isVCVTPH2QQ(unsigned Opcode);
938bool isADD(unsigned Opcode);
939bool isPSUBSW(unsigned Opcode);
940bool isSIDTW(unsigned Opcode);
941bool isVFNMADD231PH(unsigned Opcode);
942bool isVEXTRACTF64X2(unsigned Opcode);
943bool isFCOMI(unsigned Opcode);
944bool isRSM(unsigned Opcode);
945bool isVPCOMUD(unsigned Opcode);
946bool isVPMOVZXBQ(unsigned Opcode);
947bool isUWRMSR(unsigned Opcode);
948bool isLGS(unsigned Opcode);
949bool isVMOVNTPD(unsigned Opcode);
950bool isPCMPESTRMQ(unsigned Opcode);
951bool isRDPRU(unsigned Opcode);
952bool isVPUNPCKHBW(unsigned Opcode);
953bool isVUCOMXSD(unsigned Opcode);
954bool isANDN(unsigned Opcode);
955bool isVCVTTPH2UW(unsigned Opcode);
956bool isVMFUNC(unsigned Opcode);
957bool isFIMUL(unsigned Opcode);
958bool isBLCFILL(unsigned Opcode);
959bool isVGATHERPF0DPS(unsigned Opcode);
960bool isVFMSUBADD231PS(unsigned Opcode);
961bool isVREDUCESD(unsigned Opcode);
962bool isVCOMXSH(unsigned Opcode);
963bool isVXORPS(unsigned Opcode);
964bool isPSWAPD(unsigned Opcode);
965bool isPMAXSD(unsigned Opcode);
966bool isVCMPSS(unsigned Opcode);
967bool isEXTRACTPS(unsigned Opcode);
968bool isVPMOVZXBD(unsigned Opcode);
969bool isOUTSW(unsigned Opcode);
970bool isKORTESTB(unsigned Opcode);
971bool isVREDUCEPS(unsigned Opcode);
972bool isPEXTRW(unsigned Opcode);
973bool isFNINIT(unsigned Opcode);
974bool isVCVTPH2IBS(unsigned Opcode);
975bool isROL(unsigned Opcode);
976bool isVCVTPS2QQ(unsigned Opcode);
977bool isVGETMANTPH(unsigned Opcode);
978bool isPUNPCKLDQ(unsigned Opcode);
979bool isPADDD(unsigned Opcode);
980bool isVPSLLD(unsigned Opcode);
981bool isPFCMPGE(unsigned Opcode);
982bool isVGETMANTBF16(unsigned Opcode);
983bool isVSUBBF16(unsigned Opcode);
984bool isVPMOVM2D(unsigned Opcode);
985bool isVCVTTSS2USIS(unsigned Opcode);
986bool isVHSUBPS(unsigned Opcode);
987bool isENDBR32(unsigned Opcode);
988bool isMOVSXD(unsigned Opcode);
989bool isPSIGND(unsigned Opcode);
990bool isVPTEST(unsigned Opcode);
991bool isVPDPWUSD(unsigned Opcode);
992bool isHSUBPD(unsigned Opcode);
993bool isADCX(unsigned Opcode);
994bool isCVTTPD2PI(unsigned Opcode);
995bool isPDEP(unsigned Opcode);
996bool isTDPBUSD(unsigned Opcode);
997bool isVCVTBIASPH2HF8S(unsigned Opcode);
998bool isVBROADCASTI32X4(unsigned Opcode);
999bool isVCVTPH2UDQ(unsigned Opcode);
1000bool isVPHADDW(unsigned Opcode);
1001bool isFLDL2E(unsigned Opcode);
1002bool isCLZERO(unsigned Opcode);
1003bool isPBLENDW(unsigned Opcode);
1004bool isVCVTBF162IUBS(unsigned Opcode);
1005bool isVCVTSH2USI(unsigned Opcode);
1006bool isVANDPD(unsigned Opcode);
1007bool isBEXTR(unsigned Opcode);
1008bool isSTD(unsigned Opcode);
1009bool isVAESKEYGENASSIST(unsigned Opcode);
1010bool isCMPSD(unsigned Opcode);
1011bool isMOVSS(unsigned Opcode);
1012bool isVCVTUQQ2PD(unsigned Opcode);
1013bool isVEXTRACTI32X4(unsigned Opcode);
1014bool isFLDCW(unsigned Opcode);
1015bool isINSW(unsigned Opcode);
1016bool isRDPID(unsigned Opcode);
1017bool isVUCOMXSS(unsigned Opcode);
1018bool isKANDQ(unsigned Opcode);
1019bool isV4FMADDPS(unsigned Opcode);
1020bool isPMOVZXWQ(unsigned Opcode);
1021bool isVFPCLASSSD(unsigned Opcode);
1022bool isBLENDPS(unsigned Opcode);
1023bool isVPACKSSDW(unsigned Opcode);
1024bool isVPINSRW(unsigned Opcode);
1025bool isFXAM(unsigned Opcode);
1026bool isVMINMAXBF16(unsigned Opcode);
1027bool isVSHUFF64X2(unsigned Opcode);
1028bool isVPACKUSWB(unsigned Opcode);
1029bool isVRSQRT28SS(unsigned Opcode);
1030bool isGETSEC(unsigned Opcode);
1031bool isVEXTRACTF64X4(unsigned Opcode);
1032bool isVPHSUBBW(unsigned Opcode);
1033bool isBLSR(unsigned Opcode);
1034bool isFILD(unsigned Opcode);
1035bool isRETFQ(unsigned Opcode);
1036bool isVADDSS(unsigned Opcode);
1037bool isCOMISS(unsigned Opcode);
1038bool isCLI(unsigned Opcode);
1039bool isVERW(unsigned Opcode);
1040bool isBTC(unsigned Opcode);
1041bool isVPHADDUBQ(unsigned Opcode);
1042bool isVPORQ(unsigned Opcode);
1043bool isORPD(unsigned Opcode);
1044bool isVMOVSS(unsigned Opcode);
1045bool isVPSUBD(unsigned Opcode);
1046bool isVGATHERPF1QPD(unsigned Opcode);
1047bool isENCODEKEY256(unsigned Opcode);
1048bool isGF2P8AFFINEINVQB(unsigned Opcode);
1049bool isXRSTOR64(unsigned Opcode);
1050bool isKANDW(unsigned Opcode);
1051bool isLODSQ(unsigned Opcode);
1052bool isVMOVRSW(unsigned Opcode);
1053bool isVSUBSH(unsigned Opcode);
1054bool isLSS(unsigned Opcode);
1055bool isPMOVSXBQ(unsigned Opcode);
1056bool isVCVTTSD2SIS(unsigned Opcode);
1057bool isVCMPSH(unsigned Opcode);
1058bool isVFMADD132PS(unsigned Opcode);
1059bool isVPACKSSWB(unsigned Opcode);
1060bool isPCMPGTQ(unsigned Opcode);
1061bool isVFMADD132SH(unsigned Opcode);
1062bool isVCVTUQQ2PH(unsigned Opcode);
1063bool isVCVTQQ2PS(unsigned Opcode);
1064bool isVCVTTSS2USI(unsigned Opcode);
1065bool isVPMOVM2Q(unsigned Opcode);
1066bool isVMOVD(unsigned Opcode);
1067bool isVCVTTPS2QQS(unsigned Opcode);
1068bool isVSQRTBF16(unsigned Opcode);
1069bool isVFPCLASSPH(unsigned Opcode);
1070bool isVCVTSS2SH(unsigned Opcode);
1071bool isSCASB(unsigned Opcode);
1072bool isPSRLD(unsigned Opcode);
1073bool isVADDPH(unsigned Opcode);
1074bool isFSUB(unsigned Opcode);
1075bool isVCVTTPH2IBS(unsigned Opcode);
1076bool isVEXTRACTI64X2(unsigned Opcode);
1077bool isPMINUW(unsigned Opcode);
1078bool isPSUBSB(unsigned Opcode);
1079bool isVCVT2PS2PHX(unsigned Opcode);
1080bool isVPCMPEQD(unsigned Opcode);
1081bool isVPSCATTERQD(unsigned Opcode);
1082bool isVPSHLDD(unsigned Opcode);
1083bool isKXNORB(unsigned Opcode);
1084bool isLDDQU(unsigned Opcode);
1085bool isMASKMOVQ(unsigned Opcode);
1086bool isPABSW(unsigned Opcode);
1087bool isVPROLD(unsigned Opcode);
1088bool isVPCOMQ(unsigned Opcode);
1089bool isVSCATTERDPD(unsigned Opcode);
1090bool isFXRSTOR(unsigned Opcode);
1091bool isVPCMPUW(unsigned Opcode);
1092bool isWBINVD(unsigned Opcode);
1093bool isVCVTTPD2UDQ(unsigned Opcode);
1094bool isERETU(unsigned Opcode);
1095bool isPFRCPIT2(unsigned Opcode);
1096bool isVPERMT2W(unsigned Opcode);
1097bool isVEXTRACTF32X4(unsigned Opcode);
1098bool isVGATHERPF0DPD(unsigned Opcode);
1099bool isVBROADCASTF32X2(unsigned Opcode);
1100bool isVRCP14SD(unsigned Opcode);
1101bool isPABSD(unsigned Opcode);
1102bool isLAHF(unsigned Opcode);
1103bool isPINSRB(unsigned Opcode);
1104bool isSKINIT(unsigned Opcode);
1105bool isENTER(unsigned Opcode);
1106bool isVCVTSI2SS(unsigned Opcode);
1107bool isVFMADD231PD(unsigned Opcode);
1108bool isLOADIWKEY(unsigned Opcode);
1109bool isVMOVNTDQA(unsigned Opcode);
1110bool isVPERMT2PS(unsigned Opcode);
1111bool isPUSHF(unsigned Opcode);
1112bool isMPSADBW(unsigned Opcode);
1113bool isVMINMAXSH(unsigned Opcode);
1114bool isVRSQRT14SS(unsigned Opcode);
1115bool isVCVTDQ2PD(unsigned Opcode);
1116bool isVORPS(unsigned Opcode);
1117bool isVPEXPANDQ(unsigned Opcode);
1118bool isVPSHRDD(unsigned Opcode);
1119bool isTDPBSSD(unsigned Opcode);
1120bool isTESTUI(unsigned Opcode);
1121bool isVFMADDPD(unsigned Opcode);
1122bool isVPANDND(unsigned Opcode);
1123bool isVPMOVSDB(unsigned Opcode);
1124bool isVPBROADCASTB(unsigned Opcode);
1125bool isCVTPI2PD(unsigned Opcode);
1126bool isVPERMI2B(unsigned Opcode);
1127bool isVPMINSB(unsigned Opcode);
1128bool isLAR(unsigned Opcode);
1129bool isINVLPGB(unsigned Opcode);
1130bool isTLBSYNC(unsigned Opcode);
1131bool isFDIVP(unsigned Opcode);
1132bool isVPSRLW(unsigned Opcode);
1133bool isVRCP28SS(unsigned Opcode);
1134bool isVMOVHPS(unsigned Opcode);
1135bool isVPMACSSDD(unsigned Opcode);
1136bool isPEXT(unsigned Opcode);
1137bool isVMAXBF16(unsigned Opcode);
1138bool isVRSQRT14SD(unsigned Opcode);
1139bool isVPDPWSSD(unsigned Opcode);
1140bool isVFMSUB231SD(unsigned Opcode);
1141bool isVPMOVZXWQ(unsigned Opcode);
1142bool isVMOVDQA(unsigned Opcode);
1143bool isVFNMSUB213SD(unsigned Opcode);
1144bool isVMINPS(unsigned Opcode);
1145bool isVFMSUB231PS(unsigned Opcode);
1146bool isVPCOMPRESSB(unsigned Opcode);
1147bool isVPCMPEQQ(unsigned Opcode);
1148bool isVRCPSS(unsigned Opcode);
1149bool isVSCATTERPF1DPS(unsigned Opcode);
1150bool isVPHADDUBW(unsigned Opcode);
1151bool isXORPD(unsigned Opcode);
1152bool isVPSCATTERQQ(unsigned Opcode);
1153bool isVCVTW2PH(unsigned Opcode);
1154bool isVFMADDCPH(unsigned Opcode);
1155bool isVSUBPD(unsigned Opcode);
1156bool isVPACKUSDW(unsigned Opcode);
1157bool isVSCALEFSS(unsigned Opcode);
1158bool isAESIMC(unsigned Opcode);
1159bool isVRCP28PS(unsigned Opcode);
1160bool isAAND(unsigned Opcode);
1161bool isDAA(unsigned Opcode);
1162bool isVCVTPD2UDQ(unsigned Opcode);
1163bool isKTESTW(unsigned Opcode);
1164bool isVPADDQ(unsigned Opcode);
1165bool isPALIGNR(unsigned Opcode);
1166bool isPMAXUW(unsigned Opcode);
1167bool isVFMADDSD(unsigned Opcode);
1168bool isPFMAX(unsigned Opcode);
1169bool isVPOR(unsigned Opcode);
1170bool isVPSUBB(unsigned Opcode);
1171bool isVPAVGB(unsigned Opcode);
1172bool isINSB(unsigned Opcode);
1173bool isFYL2X(unsigned Opcode);
1174bool isVFNMSUB132PD(unsigned Opcode);
1175bool isVFNMSUBPS(unsigned Opcode);
1176bool isVFMADD231PS(unsigned Opcode);
1177bool isVCVTTSS2SI(unsigned Opcode);
1178bool isTCMMRLFP16PS(unsigned Opcode);
1179bool isFCOMPP(unsigned Opcode);
1180bool isMOVD(unsigned Opcode);
1181bool isMOVBE(unsigned Opcode);
1182bool isVP2INTERSECTD(unsigned Opcode);
1183bool isVPMULLQ(unsigned Opcode);
1184bool isVSCALEFPS(unsigned Opcode);
1185bool isVPMACSDQH(unsigned Opcode);
1186bool isVPTESTNMD(unsigned Opcode);
1187bool isFCOMP(unsigned Opcode);
1188bool isPREFETCHWT1(unsigned Opcode);
1189bool isVCMPSD(unsigned Opcode);
1190bool isSGDTD(unsigned Opcode);
1191bool isWRUSSD(unsigned Opcode);
1192bool isFSUBP(unsigned Opcode);
1193bool isVUNPCKLPS(unsigned Opcode);
1194bool isVFNMSUB213SS(unsigned Opcode);
1195bool isROUNDPD(unsigned Opcode);
1196bool isVPMAXSW(unsigned Opcode);
1197bool isVCVTTPH2DQ(unsigned Opcode);
1198bool isVPUNPCKLWD(unsigned Opcode);
1199bool isKSHIFTLD(unsigned Opcode);
1200bool isTCVTROWPS2BF16H(unsigned Opcode);
1201bool isVFMADD231SD(unsigned Opcode);
1202bool isADDPS(unsigned Opcode);
1203bool isVPSLLVD(unsigned Opcode);
1204bool isVFNMADD132SH(unsigned Opcode);
1205bool isVMOVNTPS(unsigned Opcode);
1206bool isVCVTPD2DQ(unsigned Opcode);
1207bool isVPXOR(unsigned Opcode);
1208bool isSTMXCSR(unsigned Opcode);
1209bool isVRCP14SS(unsigned Opcode);
1210bool isUD2(unsigned Opcode);
1211bool isVPOPCNTW(unsigned Opcode);
1212bool isVRSQRTSH(unsigned Opcode);
1213bool isVSCATTERPF0DPD(unsigned Opcode);
1214bool isVFMADDPS(unsigned Opcode);
1215bool isXSAVEC64(unsigned Opcode);
1216bool isVPMADDUBSW(unsigned Opcode);
1217bool isVPMOVZXDQ(unsigned Opcode);
1218bool isVRCP14PS(unsigned Opcode);
1219bool isVSQRTSH(unsigned Opcode);
1220bool isTCVTROWD2PS(unsigned Opcode);
1221bool isLOOP(unsigned Opcode);
1222bool isSTUI(unsigned Opcode);
1223bool isVCVTTPS2UDQ(unsigned Opcode);
1224bool isVCOMPRESSPS(unsigned Opcode);
1225bool isXABORT(unsigned Opcode);
1226bool isVCVTTBF162IUBS(unsigned Opcode);
1227bool isVPADDW(unsigned Opcode);
1228bool isVRNDSCALEPS(unsigned Opcode);
1229bool isVPSIGND(unsigned Opcode);
1230bool isVPHADDUWD(unsigned Opcode);
1231bool isVCVT2PH2HF8S(unsigned Opcode);
1232bool isVDBPSADBW(unsigned Opcode);
1233bool isPSLLW(unsigned Opcode);
1234bool isVPMOVQD(unsigned Opcode);
1235bool isVINSERTI64X4(unsigned Opcode);
1236bool isVPERMI2PS(unsigned Opcode);
1237bool isVMULPH(unsigned Opcode);
1238bool isVPCMPUQ(unsigned Opcode);
1239bool isVCVTUSI2SD(unsigned Opcode);
1240bool isKXNORW(unsigned Opcode);
1241bool isBLCIC(unsigned Opcode);
1242bool isVFNMADD213SD(unsigned Opcode);
1243bool isVPMACSWW(unsigned Opcode);
1244bool isVMOVLPS(unsigned Opcode);
1245bool isPCONFIG(unsigned Opcode);
1246bool isPANDN(unsigned Opcode);
1247bool isVGETEXPPD(unsigned Opcode);
1248bool isVPSRLVQ(unsigned Opcode);
1249bool isUD1(unsigned Opcode);
1250bool isPMAXSB(unsigned Opcode);
1251bool isVPROLQ(unsigned Opcode);
1252bool isVSCATTERPF1QPD(unsigned Opcode);
1253bool isVPSRLD(unsigned Opcode);
1254bool isINT3(unsigned Opcode);
1255bool isXRSTORS64(unsigned Opcode);
1256bool isCVTSD2SI(unsigned Opcode);
1257bool isVMAXSS(unsigned Opcode);
1258bool isVPMINUB(unsigned Opcode);
1259bool isKXNORQ(unsigned Opcode);
1260bool isFLD(unsigned Opcode);
1261bool isVSHUFI32X4(unsigned Opcode);
1262bool isSAHF(unsigned Opcode);
1263bool isPFRSQRT(unsigned Opcode);
1264bool isSHRD(unsigned Opcode);
1265bool isSYSEXIT(unsigned Opcode);
1266bool isXSAVE64(unsigned Opcode);
1267bool isVPMAXSD(unsigned Opcode);
1268bool isCVTTSD2SI(unsigned Opcode);
1269bool isVCVTTSS2SIS(unsigned Opcode);
1270bool isPMOVMSKB(unsigned Opcode);
1271bool isVRANGEPS(unsigned Opcode);
1272bool isVADDSUBPS(unsigned Opcode);
1273bool isVBROADCASTI128(unsigned Opcode);
1274bool isPADDUSB(unsigned Opcode);
1275bool isENCODEKEY128(unsigned Opcode);
1276bool isOR(unsigned Opcode);
1277bool isSTOSW(unsigned Opcode);
1278bool isVCVTTPD2UQQS(unsigned Opcode);
1279bool isPAVGW(unsigned Opcode);
1280bool isVCVTPD2PH(unsigned Opcode);
1281bool isSHLX(unsigned Opcode);
1282bool isVCVTSH2SD(unsigned Opcode);
1283bool isVFMADD231SS(unsigned Opcode);
1284bool isMOVNTSD(unsigned Opcode);
1285bool isFLDPI(unsigned Opcode);
1286bool isVCVTUSI2SS(unsigned Opcode);
1287bool isPMOVSXBD(unsigned Opcode);
1288bool isVPRORVQ(unsigned Opcode);
1289bool isVPERMT2D(unsigned Opcode);
1290bool isADDSS(unsigned Opcode);
1291bool isAADD(unsigned Opcode);
1292bool isVPSRLVW(unsigned Opcode);
1293bool isVRSQRTPH(unsigned Opcode);
1294bool isVLDDQU(unsigned Opcode);
1295bool isKMOVD(unsigned Opcode);
1296bool isENCLV(unsigned Opcode);
1297bool isENCLU(unsigned Opcode);
1298bool isPREFETCHT1(unsigned Opcode);
1299bool isRSQRTPS(unsigned Opcode);
1300bool isVCVTTSH2USI(unsigned Opcode);
1301bool isPADDB(unsigned Opcode);
1302bool isVMASKMOVDQU(unsigned Opcode);
1303bool isPUNPCKLBW(unsigned Opcode);
1304bool isMOV(unsigned Opcode);
1305bool isVCVTTPH2IUBS(unsigned Opcode);
1306bool isMUL(unsigned Opcode);
1307bool isRCL(unsigned Opcode);
1308bool isVRCPSH(unsigned Opcode);
1309bool isPFCMPEQ(unsigned Opcode);
1310bool isMONITOR(unsigned Opcode);
1311bool isFDIVR(unsigned Opcode);
1312bool isPMINSD(unsigned Opcode);
1313bool isPFRCP(unsigned Opcode);
1314bool isKTESTQ(unsigned Opcode);
1315bool isVCVTTPD2DQ(unsigned Opcode);
1316bool isVSHUFF32X4(unsigned Opcode);
1317bool isVPSLLVW(unsigned Opcode);
1318bool isTDPBSUD(unsigned Opcode);
1319bool isVPMINUQ(unsigned Opcode);
1320bool isFIADD(unsigned Opcode);
1321bool isFCMOVNU(unsigned Opcode);
1322bool isVHSUBPD(unsigned Opcode);
1323bool isKSHIFTRQ(unsigned Opcode);
1324bool isMOVUPS(unsigned Opcode);
1325bool isVMCALL(unsigned Opcode);
1326bool isXADD(unsigned Opcode);
1327bool isXRSTOR(unsigned Opcode);
1328bool isVGATHERPF1DPD(unsigned Opcode);
1329bool isRCR(unsigned Opcode);
1330bool isFNSTCW(unsigned Opcode);
1331bool isVPMOVSDW(unsigned Opcode);
1332bool isVFMSUB132SH(unsigned Opcode);
1333bool isVPCONFLICTQ(unsigned Opcode);
1334bool isSWAPGS(unsigned Opcode);
1335bool isVPMOVQ2M(unsigned Opcode);
1336bool isVPSRAVW(unsigned Opcode);
1337bool isMOVDQA(unsigned Opcode);
1338bool isDIVSD(unsigned Opcode);
1339bool isPCMPGTB(unsigned Opcode);
1340bool isSHA256MSG2(unsigned Opcode);
1341bool isKXORW(unsigned Opcode);
1342bool isLIDTW(unsigned Opcode);
1343bool isPMULHW(unsigned Opcode);
1344bool isVAESENCLAST(unsigned Opcode);
1345bool isVINSERTI32X8(unsigned Opcode);
1346bool isVRCPPS(unsigned Opcode);
1347bool isVRSQRTBF16(unsigned Opcode);
1348bool isVGATHERQPS(unsigned Opcode);
1349bool isCTESTCC(unsigned Opcode);
1350bool isPMADDWD(unsigned Opcode);
1351bool isUCOMISS(unsigned Opcode);
1352bool isXGETBV(unsigned Opcode);
1353bool isVCVTPD2QQ(unsigned Opcode);
1354bool isVGETEXPPS(unsigned Opcode);
1355bool isFISTP(unsigned Opcode);
1356bool isVINSERTF64X4(unsigned Opcode);
1357bool isVMOVDQU16(unsigned Opcode);
1358bool isVFMADD132PH(unsigned Opcode);
1359bool isVFMSUBADD213PS(unsigned Opcode);
1360bool isVMOVDQU32(unsigned Opcode);
1361bool isFUCOM(unsigned Opcode);
1362bool isVFNMADD213BF16(unsigned Opcode);
1363bool isHADDPS(unsigned Opcode);
1364bool isCMP(unsigned Opcode);
1365bool isCVTTPS2PI(unsigned Opcode);
1366bool isIRETQ(unsigned Opcode);
1367bool isPF2IW(unsigned Opcode);
1368bool isPSHUFD(unsigned Opcode);
1369bool isVDPPD(unsigned Opcode);
1370bool isPSHUFHW(unsigned Opcode);
1371bool isRMPADJUST(unsigned Opcode);
1372bool isPI2FW(unsigned Opcode);
1373bool isVCVTTPH2QQ(unsigned Opcode);
1374bool isDIVPD(unsigned Opcode);
1375bool isCLFLUSH(unsigned Opcode);
1376bool isVPMINUW(unsigned Opcode);
1377bool isIN(unsigned Opcode);
1378bool isWRPKRU(unsigned Opcode);
1379bool isINSERTPS(unsigned Opcode);
1380bool isAAM(unsigned Opcode);
1381bool isVPHADDUDQ(unsigned Opcode);
1382bool isVSHA512MSG1(unsigned Opcode);
1383bool isDIVPS(unsigned Opcode);
1384bool isKNOTB(unsigned Opcode);
1385bool isBLSFILL(unsigned Opcode);
1386bool isVPCMPGTQ(unsigned Opcode);
1387bool isMINSD(unsigned Opcode);
1388bool isFPREM(unsigned Opcode);
1389bool isVPUNPCKHQDQ(unsigned Opcode);
1390bool isMINPD(unsigned Opcode);
1391bool isVCVTTPD2QQ(unsigned Opcode);
1392bool isVFMSUBPD(unsigned Opcode);
1393bool isV4FMADDSS(unsigned Opcode);
1394bool isCPUID(unsigned Opcode);
1395bool isSETCC(unsigned Opcode);
1396bool isVPDPWUUD(unsigned Opcode);
1397bool isVCVTTPS2IUBS(unsigned Opcode);
1398bool isPMOVSXDQ(unsigned Opcode);
1399bool isMWAIT(unsigned Opcode);
1400bool isVPEXTRB(unsigned Opcode);
1401bool isINVVPID(unsigned Opcode);
1402bool isVPSHUFD(unsigned Opcode);
1403bool isVMINBF16(unsigned Opcode);
1404bool isMOVLPS(unsigned Opcode);
1405bool isVBLENDMPS(unsigned Opcode);
1406bool isPMULLW(unsigned Opcode);
1407bool isVCVTSH2SI(unsigned Opcode);
1408bool isVPMOVSXWQ(unsigned Opcode);
1409bool isFNSTENV(unsigned Opcode);
1410bool isVCVT2PH2BF8(unsigned Opcode);
1411bool isVPERMI2PD(unsigned Opcode);
1412bool isMAXSS(unsigned Opcode);
1413bool isCWDE(unsigned Opcode);
1414bool isVBROADCASTI32X8(unsigned Opcode);
1415bool isINT(unsigned Opcode);
1416bool isENCLS(unsigned Opcode);
1417bool isMOVNTQ(unsigned Opcode);
1418bool isVDIVSH(unsigned Opcode);
1419bool isMOVHLPS(unsigned Opcode);
1420bool isVPMASKMOVD(unsigned Opcode);
1421bool isVMOVSD(unsigned Opcode);
1422bool isVPMINUD(unsigned Opcode);
1423bool isVPCMPISTRM(unsigned Opcode);
1424bool isVGETMANTSD(unsigned Opcode);
1425bool isKSHIFTRW(unsigned Opcode);
1426bool isAESDECLAST(unsigned Opcode);
1427bool isVFNMSUB231BF16(unsigned Opcode);
1428bool isVMPTRST(unsigned Opcode);
1429bool isLLDT(unsigned Opcode);
1430bool isVPTESTMB(unsigned Opcode);
1431bool isMOVSB(unsigned Opcode);
1432bool isTILELOADD(unsigned Opcode);
1433bool isKTESTB(unsigned Opcode);
1434bool isMOVUPD(unsigned Opcode);
1435bool isLKGS(unsigned Opcode);
1436bool isSGDTW(unsigned Opcode);
1437bool isDIVSS(unsigned Opcode);
1438bool isPUNPCKHQDQ(unsigned Opcode);
1439bool isVFMADD213SD(unsigned Opcode);
1440bool isKXORD(unsigned Opcode);
1441bool isVPMOVB2M(unsigned Opcode);
1442bool isVMREAD(unsigned Opcode);
1443bool isVPDPWSSDS(unsigned Opcode);
1444bool isTILERELEASE(unsigned Opcode);
1445bool isVUCOMXSH(unsigned Opcode);
1446bool isCLFLUSHOPT(unsigned Opcode);
1447bool isDAS(unsigned Opcode);
1448bool isVSCALEFPH(unsigned Opcode);
1449bool isVSUBSD(unsigned Opcode);
1450bool isVCOMISS(unsigned Opcode);
1451bool isVMULBF16(unsigned Opcode);
1452bool isORPS(unsigned Opcode);
1453bool isTDPFP16PS(unsigned Opcode);
1454bool isVMAXPD(unsigned Opcode);
1455bool isVPMOVWB(unsigned Opcode);
1456bool isVEXP2PS(unsigned Opcode);
1457bool isVPGATHERDQ(unsigned Opcode);
1458bool isVPSRAVQ(unsigned Opcode);
1459bool isPCMPISTRI(unsigned Opcode);
1460bool isVFMSUB231PD(unsigned Opcode);
1461bool isRDMSR(unsigned Opcode);
1462bool isKORTESTD(unsigned Opcode);
1463bool isVPBLENDMW(unsigned Opcode);
1464bool isPSHUFB(unsigned Opcode);
1465bool isVDPBF16PS(unsigned Opcode);
1466bool isTDPBF16PS(unsigned Opcode);
1467bool isFCMOVE(unsigned Opcode);
1468bool isVFMADD231BF16(unsigned Opcode);
1469bool isCMPSS(unsigned Opcode);
1470bool isMASKMOVDQU(unsigned Opcode);
1471bool isVPDPWUSDS(unsigned Opcode);
1472bool isSARX(unsigned Opcode);
1473bool isSGDT(unsigned Opcode);
1474bool isVFMULCPH(unsigned Opcode);
1475bool isURDMSR(unsigned Opcode);
1476bool isKUNPCKWD(unsigned Opcode);
1477bool isVSCALEFBF16(unsigned Opcode);
1478bool isCVTPS2PD(unsigned Opcode);
1479bool isFBSTP(unsigned Opcode);
1480bool isPSUBQ(unsigned Opcode);
1481bool isFXSAVE64(unsigned Opcode);
1482bool isKMOVW(unsigned Opcode);
1483bool isBTS(unsigned Opcode);
1484bool isVPHADDBQ(unsigned Opcode);
1485bool isFRSTOR(unsigned Opcode);
1486bool isVFMSUB132PD(unsigned Opcode);
1487bool isPMULLD(unsigned Opcode);
1488bool isSHA1MSG2(unsigned Opcode);
1489bool isJECXZ(unsigned Opcode);
1490bool isVCVTUDQ2PS(unsigned Opcode);
1491bool isAESENC(unsigned Opcode);
1492bool isVMINMAXPS(unsigned Opcode);
1493bool isPSIGNW(unsigned Opcode);
1494bool isUNPCKLPD(unsigned Opcode);
1495bool isPUSHP(unsigned Opcode);
1496bool isBLSI(unsigned Opcode);
1497bool isVPTESTNMB(unsigned Opcode);
1498bool isWRUSSQ(unsigned Opcode);
1499bool isVGF2P8MULB(unsigned Opcode);
1500bool isVPUNPCKLBW(unsigned Opcode);
1501bool isVRANGESD(unsigned Opcode);
1502bool isCLD(unsigned Opcode);
1503bool isVSCALEFPD(unsigned Opcode);
1504bool isVCOMXSS(unsigned Opcode);
1505bool isVPERMQ(unsigned Opcode);
1506bool isVPSHLDVW(unsigned Opcode);
1507bool isROR(unsigned Opcode);
1508bool isVFMADDSUB132PH(unsigned Opcode);
1509bool isDEC(unsigned Opcode);
1510bool isVGETEXPSH(unsigned Opcode);
1511bool isAESDEC(unsigned Opcode);
1512bool isKORD(unsigned Opcode);
1513bool isVPMULHW(unsigned Opcode);
1514bool isTILELOADDT1(unsigned Opcode);
1515bool isVMASKMOVPS(unsigned Opcode);
1516bool isPMOVZXDQ(unsigned Opcode);
1517bool isVCVTPS2PH(unsigned Opcode);
1518bool isCVTDQ2PD(unsigned Opcode);
1519bool isVCVTSD2SS(unsigned Opcode);
1520bool isVFMSUB213PH(unsigned Opcode);
1521bool isVPROTB(unsigned Opcode);
1522bool isPINSRD(unsigned Opcode);
1523bool isVMXON(unsigned Opcode);
1524bool isVFCMULCSH(unsigned Opcode);
1525bool isVFMULCSH(unsigned Opcode);
1526bool isVRANGEPD(unsigned Opcode);
1527bool isCMC(unsigned Opcode);
1528bool isVFNMADD231BF16(unsigned Opcode);
1529bool isSHA256MSG1(unsigned Opcode);
1530bool isFLD1(unsigned Opcode);
1531bool isCMPPS(unsigned Opcode);
1532bool isVPAVGW(unsigned Opcode);
1533bool isVFMADD213SH(unsigned Opcode);
1534bool isVPCMPESTRMQ(unsigned Opcode);
1535bool isVPINSRQ(unsigned Opcode);
1536bool isMOVABS(unsigned Opcode);
1537bool isVPSHAQ(unsigned Opcode);
1538bool isRDTSCP(unsigned Opcode);
1539bool isVFNMADD231SS(unsigned Opcode);
1540bool isTEST(unsigned Opcode);
1541bool isVPERMD(unsigned Opcode);
1542bool isVBCSTNESH2PS(unsigned Opcode);
1543bool isVGATHERPF0QPD(unsigned Opcode);
1544bool isVPERM2I128(unsigned Opcode);
1545bool isVMPSADBW(unsigned Opcode);
1546bool isVFNMSUB231PD(unsigned Opcode);
1547bool isPADDSB(unsigned Opcode);
1548bool isMWAITX(unsigned Opcode);
1549bool isMONITORX(unsigned Opcode);
1550bool isVPEXPANDD(unsigned Opcode);
1551bool isVFRCZPD(unsigned Opcode);
1552bool isVRCPPH(unsigned Opcode);
1553bool isFEMMS(unsigned Opcode);
1554bool isVSCATTERQPD(unsigned Opcode);
1555bool isVMOVW(unsigned Opcode);
1556bool isVPBROADCASTD(unsigned Opcode);
1557bool isSTOSB(unsigned Opcode);
1558bool isFUCOMI(unsigned Opcode);
1559bool isVBROADCASTI64X4(unsigned Opcode);
1560bool isFCMOVU(unsigned Opcode);
1561bool isPSHUFLW(unsigned Opcode);
1562bool isCVTPI2PS(unsigned Opcode);
1563bool isVCVTTPD2UDQS(unsigned Opcode);
1564bool isSYSCALL(unsigned Opcode);
1565bool isVFMADD231SH(unsigned Opcode);
1566bool isPMOVZXBW(unsigned Opcode);
1567bool isVPOPCNTB(unsigned Opcode);
1568bool isVCVTDQ2PS(unsigned Opcode);
1569bool isPSUBD(unsigned Opcode);
1570bool isVPCMPEQW(unsigned Opcode);
1571bool isMOVSW(unsigned Opcode);
1572bool isVSM3RNDS2(unsigned Opcode);
1573bool isVPMOVUSQD(unsigned Opcode);
1574bool isCVTTPD2DQ(unsigned Opcode);
1575bool isVPEXPANDW(unsigned Opcode);
1576bool isVUCOMISH(unsigned Opcode);
1577bool isVZEROALL(unsigned Opcode);
1578bool isVPAND(unsigned Opcode);
1579bool isPMULDQ(unsigned Opcode);
1580bool isVPSHUFHW(unsigned Opcode);
1581bool isVPALIGNR(unsigned Opcode);
1582bool isSQRTSD(unsigned Opcode);
1583bool isVCVTTPH2UDQ(unsigned Opcode);
1584bool isVGETEXPPH(unsigned Opcode);
1585bool isADDPD(unsigned Opcode);
1586bool isVFNMADDPD(unsigned Opcode);
1587bool isSTTILECFG(unsigned Opcode);
1588bool isVMINPD(unsigned Opcode);
1589bool isSHA1RNDS4(unsigned Opcode);
1590bool isPBLENDVB(unsigned Opcode);
1591bool isVBROADCASTF128(unsigned Opcode);
1592bool isVPSHRDQ(unsigned Opcode);
1593bool isVAESIMC(unsigned Opcode);
1594bool isCOMISD(unsigned Opcode);
1595bool isVMOVSH(unsigned Opcode);
1596bool isPFSUBR(unsigned Opcode);
1597bool isRDSSPD(unsigned Opcode);
1598bool isWAIT(unsigned Opcode);
1599bool isVFPCLASSSS(unsigned Opcode);
1600bool isPCMPGTD(unsigned Opcode);
1601bool isVGATHERPF0QPS(unsigned Opcode);
1602bool isBLENDVPS(unsigned Opcode);
1603bool isVBROADCASTF32X4(unsigned Opcode);
1604bool isVPMADD52LUQ(unsigned Opcode);
1605bool isVMOVLPD(unsigned Opcode);
1606bool isVMOVQ(unsigned Opcode);
1607bool isVMOVDQU(unsigned Opcode);
1608bool isAESENC128KL(unsigned Opcode);
1609bool isVFMADDSUB231PS(unsigned Opcode);
1610bool isVFNMSUB213PD(unsigned Opcode);
1611bool isVPCONFLICTD(unsigned Opcode);
1612bool isVFMADDSUB213PH(unsigned Opcode);
1613bool isVPHSUBSW(unsigned Opcode);
1614bool isPUNPCKHDQ(unsigned Opcode);
1615bool isVSHUFI64X2(unsigned Opcode);
1616bool isVFMSUBSD(unsigned Opcode);
1617bool isVPORD(unsigned Opcode);
1618bool isRCPPS(unsigned Opcode);
1619bool isVEXTRACTI128(unsigned Opcode);
1620bool isVCVT2PH2BF8S(unsigned Opcode);
1621bool isVPSHRDVW(unsigned Opcode);
1622bool isVUNPCKLPD(unsigned Opcode);
1623bool isVPSRAVD(unsigned Opcode);
1624bool isVMULSH(unsigned Opcode);
1625bool isMOVNTSS(unsigned Opcode);
1626bool isSTI(unsigned Opcode);
1627bool isVSM4RNDS4(unsigned Opcode);
1628bool isVMCLEAR(unsigned Opcode);
1629bool isVPMADD52HUQ(unsigned Opcode);
1630bool isLIDT(unsigned Opcode);
1631bool isPUSH2(unsigned Opcode);
1632bool isVCVTPS2IUBS(unsigned Opcode);
1633bool isRDPKRU(unsigned Opcode);
1634bool isVPCMPB(unsigned Opcode);
1635bool isVFMSUB231BF16(unsigned Opcode);
1636bool isFINCSTP(unsigned Opcode);
1637bool isKORQ(unsigned Opcode);
1638bool isXCRYPTCBC(unsigned Opcode);
1639bool isRDPMC(unsigned Opcode);
1640bool isMOVMSKPD(unsigned Opcode);
1641bool isVFMSUB231SH(unsigned Opcode);
1642bool isVEXTRACTF128(unsigned Opcode);
1643bool isVPSHLB(unsigned Opcode);
1644bool isXSAVES64(unsigned Opcode);
1645bool isSHL(unsigned Opcode);
1646bool isAXOR(unsigned Opcode);
1647bool isVINSERTI64X2(unsigned Opcode);
1648bool isSYSRETQ(unsigned Opcode);
1649bool isVSCATTERPF0QPD(unsigned Opcode);
1650bool isVFMSUB213SH(unsigned Opcode);
1651bool isVPMOVQW(unsigned Opcode);
1652bool isVREDUCEPD(unsigned Opcode);
1653bool isNOT(unsigned Opcode);
1654bool isLWPINS(unsigned Opcode);
1655bool isVSCATTERDPS(unsigned Opcode);
1656bool isVPMOVM2W(unsigned Opcode);
1657bool isVFNMADD132PS(unsigned Opcode);
1658bool isMOVNTPS(unsigned Opcode);
1659bool isVRSQRTSS(unsigned Opcode);
1660bool isKMOVB(unsigned Opcode);
1661bool isCVTSD2SS(unsigned Opcode);
1662bool isVBROADCASTF64X2(unsigned Opcode);
1663bool isMOVNTPD(unsigned Opcode);
1664bool isMAXSD(unsigned Opcode);
1665bool isCMPPD(unsigned Opcode);
1666bool isVPCMPESTRM(unsigned Opcode);
1667bool isVFMSUB132PS(unsigned Opcode);
1668bool isVCOMISH(unsigned Opcode);
1669bool isF2XM1(unsigned Opcode);
1670bool isVDIVBF16(unsigned Opcode);
1671bool isSQRTPD(unsigned Opcode);
1672bool isVFMSUBADDPS(unsigned Opcode);
1673bool isFXTRACT(unsigned Opcode);
1674bool isVP4DPWSSD(unsigned Opcode);
1675bool isTDPBHF8PS(unsigned Opcode);
1676bool isVFMSUBADDPD(unsigned Opcode);
1677bool isVBCSTNEBF162PS(unsigned Opcode);
1678bool isVPGATHERQQ(unsigned Opcode);
1679bool isPCMPEQB(unsigned Opcode);
1680bool isTILESTORED(unsigned Opcode);
1681bool isBLSMSK(unsigned Opcode);
1682bool isVCVTTPS2DQ(unsigned Opcode);
1683bool isVRNDSCALEPD(unsigned Opcode);
1684bool isVFPCLASSBF16(unsigned Opcode);
1685bool isVMLOAD(unsigned Opcode);
1686bool isVPTERNLOGQ(unsigned Opcode);
1687bool isKXNORD(unsigned Opcode);
1688bool isFXSAVE(unsigned Opcode);
1689bool isVUNPCKHPD(unsigned Opcode);
1690bool isCVTPS2DQ(unsigned Opcode);
1691bool isTMMULTF32PS(unsigned Opcode);
1692bool isVFMSUB213SS(unsigned Opcode);
1693bool isVPOPCNTD(unsigned Opcode);
1694bool isSALC(unsigned Opcode);
1695bool isV4FNMADDSS(unsigned Opcode);
1696bool isXCRYPTOFB(unsigned Opcode);
1697bool isVORPD(unsigned Opcode);
1698bool isLSL(unsigned Opcode);
1699bool isXCRYPTCFB(unsigned Opcode);
1700bool isVGETEXPSS(unsigned Opcode);
1701bool isPSLLDQ(unsigned Opcode);
1702bool isVPDPBUUD(unsigned Opcode);
1703bool isVMXOFF(unsigned Opcode);
1704bool isBLSIC(unsigned Opcode);
1705bool isMOVLHPS(unsigned Opcode);
1706bool isVMOVRSQ(unsigned Opcode);
1707bool isVFNMSUBSD(unsigned Opcode);
1708bool isVCVTPH2IUBS(unsigned Opcode);
1709bool isVFPCLASSSH(unsigned Opcode);
1710bool isVPSHLQ(unsigned Opcode);
1711bool isVROUNDPS(unsigned Opcode);
1712bool isVSCATTERPF0QPS(unsigned Opcode);
1713bool isERETS(unsigned Opcode);
1714bool isVPERMI2D(unsigned Opcode);
1715bool isFUCOMP(unsigned Opcode);
1716bool isVCVTTPS2QQ(unsigned Opcode);
1717bool isPUSHFD(unsigned Opcode);
1718bool isKORB(unsigned Opcode);
1719bool isVRCP28PD(unsigned Opcode);
1720bool isVPABSD(unsigned Opcode);
1721bool isVROUNDSS(unsigned Opcode);
1722bool isVCVTSD2USI(unsigned Opcode);
1723bool isVPABSB(unsigned Opcode);
1724bool isPMAXUD(unsigned Opcode);
1725bool isVPMULHUW(unsigned Opcode);
1726bool isVPERMPD(unsigned Opcode);
1727bool isFCHS(unsigned Opcode);
1728bool isVPBLENDMB(unsigned Opcode);
1729bool isVGETMANTSS(unsigned Opcode);
1730bool isVPSLLW(unsigned Opcode);
1731bool isVDIVPD(unsigned Opcode);
1732bool isBLCMSK(unsigned Opcode);
1733bool isFDIV(unsigned Opcode);
1734bool isRSQRTSS(unsigned Opcode);
1735bool isPOR(unsigned Opcode);
1736bool isVMOVDQA32(unsigned Opcode);
1737bool isVPHADDUWQ(unsigned Opcode);
1738bool isPSRAD(unsigned Opcode);
1739bool isPREFETCHW(unsigned Opcode);
1740bool isFIDIVR(unsigned Opcode);
1741bool isMOVHPS(unsigned Opcode);
1742bool isVFNMSUB231PH(unsigned Opcode);
1743bool isUNPCKLPS(unsigned Opcode);
1744bool isVPSIGNB(unsigned Opcode);
1745bool isSAVEPREVSSP(unsigned Opcode);
1746bool isVSCALEFSD(unsigned Opcode);
1747bool isFSIN(unsigned Opcode);
1748bool isSCASQ(unsigned Opcode);
1749bool isVCVTTPD2QQS(unsigned Opcode);
1750bool isPCMPGTW(unsigned Opcode);
1751bool isMULX(unsigned Opcode);
1752bool isVPMAXUW(unsigned Opcode);
1753bool isPAUSE(unsigned Opcode);
1754bool isMOVQ2DQ(unsigned Opcode);
1755bool isVPSUBQ(unsigned Opcode);
1756bool isVPABSW(unsigned Opcode);
1757bool isVPCOMPRESSD(unsigned Opcode);
1758bool isVPMOVUSQW(unsigned Opcode);
1759bool isBLENDVPD(unsigned Opcode);
1760bool isVFNMADD132BF16(unsigned Opcode);
1761bool isVPMOVQB(unsigned Opcode);
1762bool isVBLENDVPS(unsigned Opcode);
1763bool isKSHIFTLQ(unsigned Opcode);
1764bool isPMOVSXWD(unsigned Opcode);
1765bool isPHSUBSW(unsigned Opcode);
1766bool isPSRLQ(unsigned Opcode);
1767bool isVCVTPH2DQ(unsigned Opcode);
1768bool isPCMPESTRIQ(unsigned Opcode);
1769bool isFISUB(unsigned Opcode);
1770bool isVCVTPS2UDQ(unsigned Opcode);
1771bool isVMOVDDUP(unsigned Opcode);
1772bool isPCMPEQD(unsigned Opcode);
1773bool isVRSQRT28SD(unsigned Opcode);
1774bool isTDPHBF8PS(unsigned Opcode);
1775bool isLODSW(unsigned Opcode);
1776bool isVPOPCNTQ(unsigned Opcode);
1777bool isKSHIFTRB(unsigned Opcode);
1778bool isVFNMADDPS(unsigned Opcode);
1779bool isCCMPCC(unsigned Opcode);
1780bool isFXRSTOR64(unsigned Opcode);
1781bool isVFMSUBADD213PD(unsigned Opcode);
1782bool isVSQRTPH(unsigned Opcode);
1783bool isPOPF(unsigned Opcode);
1784bool isVPSUBUSB(unsigned Opcode);
1785bool isTCVTROWPS2BF16L(unsigned Opcode);
1786bool isPREFETCHIT1(unsigned Opcode);
1787bool isVPADDSW(unsigned Opcode);
1788bool isVADDSUBPD(unsigned Opcode);
1789bool isKANDD(unsigned Opcode);
1790bool isOUTSB(unsigned Opcode);
1791bool isPREFETCHRST2(unsigned Opcode);
1792bool isFNSTSW(unsigned Opcode);
1793bool isPMINSB(unsigned Opcode);
1794
1795} // namespace llvm::X86
1796
1797#endif // GET_X86_MNEMONIC_TABLES_H
1798
1799#ifdef GET_X86_MNEMONIC_TABLES_CPP
1800#undef GET_X86_MNEMONIC_TABLES_CPP
1801
1802namespace llvm::X86 {
1803
1804bool isFSUBRP(unsigned Opcode) {
1805 return Opcode == SUBR_FPrST0;
1806}
1807
1808bool isVPDPBUSDS(unsigned Opcode) {
1809 switch (Opcode) {
1810 case VPDPBUSDSYrm:
1811 case VPDPBUSDSYrr:
1812 case VPDPBUSDSZ128rm:
1813 case VPDPBUSDSZ128rmb:
1814 case VPDPBUSDSZ128rmbk:
1815 case VPDPBUSDSZ128rmbkz:
1816 case VPDPBUSDSZ128rmk:
1817 case VPDPBUSDSZ128rmkz:
1818 case VPDPBUSDSZ128rr:
1819 case VPDPBUSDSZ128rrk:
1820 case VPDPBUSDSZ128rrkz:
1821 case VPDPBUSDSZ256rm:
1822 case VPDPBUSDSZ256rmb:
1823 case VPDPBUSDSZ256rmbk:
1824 case VPDPBUSDSZ256rmbkz:
1825 case VPDPBUSDSZ256rmk:
1826 case VPDPBUSDSZ256rmkz:
1827 case VPDPBUSDSZ256rr:
1828 case VPDPBUSDSZ256rrk:
1829 case VPDPBUSDSZ256rrkz:
1830 case VPDPBUSDSZrm:
1831 case VPDPBUSDSZrmb:
1832 case VPDPBUSDSZrmbk:
1833 case VPDPBUSDSZrmbkz:
1834 case VPDPBUSDSZrmk:
1835 case VPDPBUSDSZrmkz:
1836 case VPDPBUSDSZrr:
1837 case VPDPBUSDSZrrk:
1838 case VPDPBUSDSZrrkz:
1839 case VPDPBUSDSrm:
1840 case VPDPBUSDSrr:
1841 return true;
1842 }
1843 return false;
1844}
1845
1846bool isPUNPCKLWD(unsigned Opcode) {
1847 switch (Opcode) {
1848 case MMX_PUNPCKLWDrm:
1849 case MMX_PUNPCKLWDrr:
1850 case PUNPCKLWDrm:
1851 case PUNPCKLWDrr:
1852 return true;
1853 }
1854 return false;
1855}
1856
1857bool isVREDUCEBF16(unsigned Opcode) {
1858 switch (Opcode) {
1859 case VREDUCEBF16Z128rmbi:
1860 case VREDUCEBF16Z128rmbik:
1861 case VREDUCEBF16Z128rmbikz:
1862 case VREDUCEBF16Z128rmi:
1863 case VREDUCEBF16Z128rmik:
1864 case VREDUCEBF16Z128rmikz:
1865 case VREDUCEBF16Z128rri:
1866 case VREDUCEBF16Z128rrik:
1867 case VREDUCEBF16Z128rrikz:
1868 case VREDUCEBF16Z256rmbi:
1869 case VREDUCEBF16Z256rmbik:
1870 case VREDUCEBF16Z256rmbikz:
1871 case VREDUCEBF16Z256rmi:
1872 case VREDUCEBF16Z256rmik:
1873 case VREDUCEBF16Z256rmikz:
1874 case VREDUCEBF16Z256rri:
1875 case VREDUCEBF16Z256rrik:
1876 case VREDUCEBF16Z256rrikz:
1877 case VREDUCEBF16Zrmbi:
1878 case VREDUCEBF16Zrmbik:
1879 case VREDUCEBF16Zrmbikz:
1880 case VREDUCEBF16Zrmi:
1881 case VREDUCEBF16Zrmik:
1882 case VREDUCEBF16Zrmikz:
1883 case VREDUCEBF16Zrri:
1884 case VREDUCEBF16Zrrik:
1885 case VREDUCEBF16Zrrikz:
1886 return true;
1887 }
1888 return false;
1889}
1890
1891bool isPUNPCKLQDQ(unsigned Opcode) {
1892 switch (Opcode) {
1893 case PUNPCKLQDQrm:
1894 case PUNPCKLQDQrr:
1895 return true;
1896 }
1897 return false;
1898}
1899
1900bool isRDFSBASE(unsigned Opcode) {
1901 switch (Opcode) {
1902 case RDFSBASE:
1903 case RDFSBASE64:
1904 return true;
1905 }
1906 return false;
1907}
1908
1909bool isVPCMOV(unsigned Opcode) {
1910 switch (Opcode) {
1911 case VPCMOVYrmr:
1912 case VPCMOVYrrm:
1913 case VPCMOVYrrr:
1914 case VPCMOVYrrr_REV:
1915 case VPCMOVrmr:
1916 case VPCMOVrrm:
1917 case VPCMOVrrr:
1918 case VPCMOVrrr_REV:
1919 return true;
1920 }
1921 return false;
1922}
1923
1924bool isVDIVSD(unsigned Opcode) {
1925 switch (Opcode) {
1926 case VDIVSDZrm_Int:
1927 case VDIVSDZrmk_Int:
1928 case VDIVSDZrmkz_Int:
1929 case VDIVSDZrr_Int:
1930 case VDIVSDZrrb_Int:
1931 case VDIVSDZrrbk_Int:
1932 case VDIVSDZrrbkz_Int:
1933 case VDIVSDZrrk_Int:
1934 case VDIVSDZrrkz_Int:
1935 case VDIVSDrm_Int:
1936 case VDIVSDrr_Int:
1937 return true;
1938 }
1939 return false;
1940}
1941
1942bool isVCVTTPS2IBS(unsigned Opcode) {
1943 switch (Opcode) {
1944 case VCVTTPS2IBSZ128rm:
1945 case VCVTTPS2IBSZ128rmb:
1946 case VCVTTPS2IBSZ128rmbk:
1947 case VCVTTPS2IBSZ128rmbkz:
1948 case VCVTTPS2IBSZ128rmk:
1949 case VCVTTPS2IBSZ128rmkz:
1950 case VCVTTPS2IBSZ128rr:
1951 case VCVTTPS2IBSZ128rrk:
1952 case VCVTTPS2IBSZ128rrkz:
1953 case VCVTTPS2IBSZ256rm:
1954 case VCVTTPS2IBSZ256rmb:
1955 case VCVTTPS2IBSZ256rmbk:
1956 case VCVTTPS2IBSZ256rmbkz:
1957 case VCVTTPS2IBSZ256rmk:
1958 case VCVTTPS2IBSZ256rmkz:
1959 case VCVTTPS2IBSZ256rr:
1960 case VCVTTPS2IBSZ256rrk:
1961 case VCVTTPS2IBSZ256rrkz:
1962 case VCVTTPS2IBSZrm:
1963 case VCVTTPS2IBSZrmb:
1964 case VCVTTPS2IBSZrmbk:
1965 case VCVTTPS2IBSZrmbkz:
1966 case VCVTTPS2IBSZrmk:
1967 case VCVTTPS2IBSZrmkz:
1968 case VCVTTPS2IBSZrr:
1969 case VCVTTPS2IBSZrrb:
1970 case VCVTTPS2IBSZrrbk:
1971 case VCVTTPS2IBSZrrbkz:
1972 case VCVTTPS2IBSZrrk:
1973 case VCVTTPS2IBSZrrkz:
1974 return true;
1975 }
1976 return false;
1977}
1978
1979bool isVPEXTRW(unsigned Opcode) {
1980 switch (Opcode) {
1981 case VPEXTRWZmri:
1982 case VPEXTRWZrri:
1983 case VPEXTRWZrri_REV:
1984 case VPEXTRWmri:
1985 case VPEXTRWrri:
1986 case VPEXTRWrri_REV:
1987 return true;
1988 }
1989 return false;
1990}
1991
1992bool isLODSD(unsigned Opcode) {
1993 return Opcode == LODSL;
1994}
1995
1996bool isVPTESTNMQ(unsigned Opcode) {
1997 switch (Opcode) {
1998 case VPTESTNMQZ128rm:
1999 case VPTESTNMQZ128rmb:
2000 case VPTESTNMQZ128rmbk:
2001 case VPTESTNMQZ128rmk:
2002 case VPTESTNMQZ128rr:
2003 case VPTESTNMQZ128rrk:
2004 case VPTESTNMQZ256rm:
2005 case VPTESTNMQZ256rmb:
2006 case VPTESTNMQZ256rmbk:
2007 case VPTESTNMQZ256rmk:
2008 case VPTESTNMQZ256rr:
2009 case VPTESTNMQZ256rrk:
2010 case VPTESTNMQZrm:
2011 case VPTESTNMQZrmb:
2012 case VPTESTNMQZrmbk:
2013 case VPTESTNMQZrmk:
2014 case VPTESTNMQZrr:
2015 case VPTESTNMQZrrk:
2016 return true;
2017 }
2018 return false;
2019}
2020
2021bool isCVTSS2SD(unsigned Opcode) {
2022 switch (Opcode) {
2023 case CVTSS2SDrm_Int:
2024 case CVTSS2SDrr_Int:
2025 return true;
2026 }
2027 return false;
2028}
2029
2030bool isVGETMANTPD(unsigned Opcode) {
2031 switch (Opcode) {
2032 case VGETMANTPDZ128rmbi:
2033 case VGETMANTPDZ128rmbik:
2034 case VGETMANTPDZ128rmbikz:
2035 case VGETMANTPDZ128rmi:
2036 case VGETMANTPDZ128rmik:
2037 case VGETMANTPDZ128rmikz:
2038 case VGETMANTPDZ128rri:
2039 case VGETMANTPDZ128rrik:
2040 case VGETMANTPDZ128rrikz:
2041 case VGETMANTPDZ256rmbi:
2042 case VGETMANTPDZ256rmbik:
2043 case VGETMANTPDZ256rmbikz:
2044 case VGETMANTPDZ256rmi:
2045 case VGETMANTPDZ256rmik:
2046 case VGETMANTPDZ256rmikz:
2047 case VGETMANTPDZ256rri:
2048 case VGETMANTPDZ256rrik:
2049 case VGETMANTPDZ256rrikz:
2050 case VGETMANTPDZrmbi:
2051 case VGETMANTPDZrmbik:
2052 case VGETMANTPDZrmbikz:
2053 case VGETMANTPDZrmi:
2054 case VGETMANTPDZrmik:
2055 case VGETMANTPDZrmikz:
2056 case VGETMANTPDZrri:
2057 case VGETMANTPDZrrib:
2058 case VGETMANTPDZrribk:
2059 case VGETMANTPDZrribkz:
2060 case VGETMANTPDZrrik:
2061 case VGETMANTPDZrrikz:
2062 return true;
2063 }
2064 return false;
2065}
2066
2067bool isVMOVDQA64(unsigned Opcode) {
2068 switch (Opcode) {
2069 case VMOVDQA64Z128mr:
2070 case VMOVDQA64Z128mrk:
2071 case VMOVDQA64Z128rm:
2072 case VMOVDQA64Z128rmk:
2073 case VMOVDQA64Z128rmkz:
2074 case VMOVDQA64Z128rr:
2075 case VMOVDQA64Z128rr_REV:
2076 case VMOVDQA64Z128rrk:
2077 case VMOVDQA64Z128rrk_REV:
2078 case VMOVDQA64Z128rrkz:
2079 case VMOVDQA64Z128rrkz_REV:
2080 case VMOVDQA64Z256mr:
2081 case VMOVDQA64Z256mrk:
2082 case VMOVDQA64Z256rm:
2083 case VMOVDQA64Z256rmk:
2084 case VMOVDQA64Z256rmkz:
2085 case VMOVDQA64Z256rr:
2086 case VMOVDQA64Z256rr_REV:
2087 case VMOVDQA64Z256rrk:
2088 case VMOVDQA64Z256rrk_REV:
2089 case VMOVDQA64Z256rrkz:
2090 case VMOVDQA64Z256rrkz_REV:
2091 case VMOVDQA64Zmr:
2092 case VMOVDQA64Zmrk:
2093 case VMOVDQA64Zrm:
2094 case VMOVDQA64Zrmk:
2095 case VMOVDQA64Zrmkz:
2096 case VMOVDQA64Zrr:
2097 case VMOVDQA64Zrr_REV:
2098 case VMOVDQA64Zrrk:
2099 case VMOVDQA64Zrrk_REV:
2100 case VMOVDQA64Zrrkz:
2101 case VMOVDQA64Zrrkz_REV:
2102 return true;
2103 }
2104 return false;
2105}
2106
2107bool isINVLPG(unsigned Opcode) {
2108 return Opcode == INVLPG;
2109}
2110
2111bool isVGETEXPBF16(unsigned Opcode) {
2112 switch (Opcode) {
2113 case VGETEXPBF16Z128m:
2114 case VGETEXPBF16Z128mb:
2115 case VGETEXPBF16Z128mbk:
2116 case VGETEXPBF16Z128mbkz:
2117 case VGETEXPBF16Z128mk:
2118 case VGETEXPBF16Z128mkz:
2119 case VGETEXPBF16Z128r:
2120 case VGETEXPBF16Z128rk:
2121 case VGETEXPBF16Z128rkz:
2122 case VGETEXPBF16Z256m:
2123 case VGETEXPBF16Z256mb:
2124 case VGETEXPBF16Z256mbk:
2125 case VGETEXPBF16Z256mbkz:
2126 case VGETEXPBF16Z256mk:
2127 case VGETEXPBF16Z256mkz:
2128 case VGETEXPBF16Z256r:
2129 case VGETEXPBF16Z256rk:
2130 case VGETEXPBF16Z256rkz:
2131 case VGETEXPBF16Zm:
2132 case VGETEXPBF16Zmb:
2133 case VGETEXPBF16Zmbk:
2134 case VGETEXPBF16Zmbkz:
2135 case VGETEXPBF16Zmk:
2136 case VGETEXPBF16Zmkz:
2137 case VGETEXPBF16Zr:
2138 case VGETEXPBF16Zrk:
2139 case VGETEXPBF16Zrkz:
2140 return true;
2141 }
2142 return false;
2143}
2144
2145bool isVBROADCASTF64X4(unsigned Opcode) {
2146 switch (Opcode) {
2147 case VBROADCASTF64X4Zrm:
2148 case VBROADCASTF64X4Zrmk:
2149 case VBROADCASTF64X4Zrmkz:
2150 return true;
2151 }
2152 return false;
2153}
2154
2155bool isVPERMI2Q(unsigned Opcode) {
2156 switch (Opcode) {
2157 case VPERMI2QZ128rm:
2158 case VPERMI2QZ128rmb:
2159 case VPERMI2QZ128rmbk:
2160 case VPERMI2QZ128rmbkz:
2161 case VPERMI2QZ128rmk:
2162 case VPERMI2QZ128rmkz:
2163 case VPERMI2QZ128rr:
2164 case VPERMI2QZ128rrk:
2165 case VPERMI2QZ128rrkz:
2166 case VPERMI2QZ256rm:
2167 case VPERMI2QZ256rmb:
2168 case VPERMI2QZ256rmbk:
2169 case VPERMI2QZ256rmbkz:
2170 case VPERMI2QZ256rmk:
2171 case VPERMI2QZ256rmkz:
2172 case VPERMI2QZ256rr:
2173 case VPERMI2QZ256rrk:
2174 case VPERMI2QZ256rrkz:
2175 case VPERMI2QZrm:
2176 case VPERMI2QZrmb:
2177 case VPERMI2QZrmbk:
2178 case VPERMI2QZrmbkz:
2179 case VPERMI2QZrmk:
2180 case VPERMI2QZrmkz:
2181 case VPERMI2QZrr:
2182 case VPERMI2QZrrk:
2183 case VPERMI2QZrrkz:
2184 return true;
2185 }
2186 return false;
2187}
2188
2189bool isVPMOVSXBD(unsigned Opcode) {
2190 switch (Opcode) {
2191 case VPMOVSXBDYrm:
2192 case VPMOVSXBDYrr:
2193 case VPMOVSXBDZ128rm:
2194 case VPMOVSXBDZ128rmk:
2195 case VPMOVSXBDZ128rmkz:
2196 case VPMOVSXBDZ128rr:
2197 case VPMOVSXBDZ128rrk:
2198 case VPMOVSXBDZ128rrkz:
2199 case VPMOVSXBDZ256rm:
2200 case VPMOVSXBDZ256rmk:
2201 case VPMOVSXBDZ256rmkz:
2202 case VPMOVSXBDZ256rr:
2203 case VPMOVSXBDZ256rrk:
2204 case VPMOVSXBDZ256rrkz:
2205 case VPMOVSXBDZrm:
2206 case VPMOVSXBDZrmk:
2207 case VPMOVSXBDZrmkz:
2208 case VPMOVSXBDZrr:
2209 case VPMOVSXBDZrrk:
2210 case VPMOVSXBDZrrkz:
2211 case VPMOVSXBDrm:
2212 case VPMOVSXBDrr:
2213 return true;
2214 }
2215 return false;
2216}
2217
2218bool isVFMSUB132SS(unsigned Opcode) {
2219 switch (Opcode) {
2220 case VFMSUB132SSZm_Int:
2221 case VFMSUB132SSZmk_Int:
2222 case VFMSUB132SSZmkz_Int:
2223 case VFMSUB132SSZr_Int:
2224 case VFMSUB132SSZrb_Int:
2225 case VFMSUB132SSZrbk_Int:
2226 case VFMSUB132SSZrbkz_Int:
2227 case VFMSUB132SSZrk_Int:
2228 case VFMSUB132SSZrkz_Int:
2229 case VFMSUB132SSm_Int:
2230 case VFMSUB132SSr_Int:
2231 return true;
2232 }
2233 return false;
2234}
2235
2236bool isVPMOVUSDW(unsigned Opcode) {
2237 switch (Opcode) {
2238 case VPMOVUSDWZ128mr:
2239 case VPMOVUSDWZ128mrk:
2240 case VPMOVUSDWZ128rr:
2241 case VPMOVUSDWZ128rrk:
2242 case VPMOVUSDWZ128rrkz:
2243 case VPMOVUSDWZ256mr:
2244 case VPMOVUSDWZ256mrk:
2245 case VPMOVUSDWZ256rr:
2246 case VPMOVUSDWZ256rrk:
2247 case VPMOVUSDWZ256rrkz:
2248 case VPMOVUSDWZmr:
2249 case VPMOVUSDWZmrk:
2250 case VPMOVUSDWZrr:
2251 case VPMOVUSDWZrrk:
2252 case VPMOVUSDWZrrkz:
2253 return true;
2254 }
2255 return false;
2256}
2257
2258bool isAAD(unsigned Opcode) {
2259 return Opcode == AAD8i8;
2260}
2261
2262bool isIDIV(unsigned Opcode) {
2263 switch (Opcode) {
2264 case IDIV16m:
2265 case IDIV16m_EVEX:
2266 case IDIV16m_NF:
2267 case IDIV16r:
2268 case IDIV16r_EVEX:
2269 case IDIV16r_NF:
2270 case IDIV32m:
2271 case IDIV32m_EVEX:
2272 case IDIV32m_NF:
2273 case IDIV32r:
2274 case IDIV32r_EVEX:
2275 case IDIV32r_NF:
2276 case IDIV64m:
2277 case IDIV64m_EVEX:
2278 case IDIV64m_NF:
2279 case IDIV64r:
2280 case IDIV64r_EVEX:
2281 case IDIV64r_NF:
2282 case IDIV8m:
2283 case IDIV8m_EVEX:
2284 case IDIV8m_NF:
2285 case IDIV8r:
2286 case IDIV8r_EVEX:
2287 case IDIV8r_NF:
2288 return true;
2289 }
2290 return false;
2291}
2292
2293bool isCVTTPS2DQ(unsigned Opcode) {
2294 switch (Opcode) {
2295 case CVTTPS2DQrm:
2296 case CVTTPS2DQrr:
2297 return true;
2298 }
2299 return false;
2300}
2301
2302bool isVBROADCASTF32X8(unsigned Opcode) {
2303 switch (Opcode) {
2304 case VBROADCASTF32X8Zrm:
2305 case VBROADCASTF32X8Zrmk:
2306 case VBROADCASTF32X8Zrmkz:
2307 return true;
2308 }
2309 return false;
2310}
2311
2312bool isVFMSUBSS(unsigned Opcode) {
2313 switch (Opcode) {
2314 case VFMSUBSS4mr:
2315 case VFMSUBSS4rm:
2316 case VFMSUBSS4rr:
2317 case VFMSUBSS4rr_REV:
2318 return true;
2319 }
2320 return false;
2321}
2322
2323bool isEMMS(unsigned Opcode) {
2324 return Opcode == MMX_EMMS;
2325}
2326
2327bool isVPDPBSUD(unsigned Opcode) {
2328 switch (Opcode) {
2329 case VPDPBSUDYrm:
2330 case VPDPBSUDYrr:
2331 case VPDPBSUDZ128rm:
2332 case VPDPBSUDZ128rmb:
2333 case VPDPBSUDZ128rmbk:
2334 case VPDPBSUDZ128rmbkz:
2335 case VPDPBSUDZ128rmk:
2336 case VPDPBSUDZ128rmkz:
2337 case VPDPBSUDZ128rr:
2338 case VPDPBSUDZ128rrk:
2339 case VPDPBSUDZ128rrkz:
2340 case VPDPBSUDZ256rm:
2341 case VPDPBSUDZ256rmb:
2342 case VPDPBSUDZ256rmbk:
2343 case VPDPBSUDZ256rmbkz:
2344 case VPDPBSUDZ256rmk:
2345 case VPDPBSUDZ256rmkz:
2346 case VPDPBSUDZ256rr:
2347 case VPDPBSUDZ256rrk:
2348 case VPDPBSUDZ256rrkz:
2349 case VPDPBSUDZrm:
2350 case VPDPBSUDZrmb:
2351 case VPDPBSUDZrmbk:
2352 case VPDPBSUDZrmbkz:
2353 case VPDPBSUDZrmk:
2354 case VPDPBSUDZrmkz:
2355 case VPDPBSUDZrr:
2356 case VPDPBSUDZrrk:
2357 case VPDPBSUDZrrkz:
2358 case VPDPBSUDrm:
2359 case VPDPBSUDrr:
2360 return true;
2361 }
2362 return false;
2363}
2364
2365bool isPMOVSXWQ(unsigned Opcode) {
2366 switch (Opcode) {
2367 case PMOVSXWQrm:
2368 case PMOVSXWQrr:
2369 return true;
2370 }
2371 return false;
2372}
2373
2374bool isPSRLW(unsigned Opcode) {
2375 switch (Opcode) {
2376 case MMX_PSRLWri:
2377 case MMX_PSRLWrm:
2378 case MMX_PSRLWrr:
2379 case PSRLWri:
2380 case PSRLWrm:
2381 case PSRLWrr:
2382 return true;
2383 }
2384 return false;
2385}
2386
2387bool isMOVNTDQA(unsigned Opcode) {
2388 return Opcode == MOVNTDQArm;
2389}
2390
2391bool isFUCOMPI(unsigned Opcode) {
2392 return Opcode == UCOM_FIPr;
2393}
2394
2395bool isANDNPS(unsigned Opcode) {
2396 switch (Opcode) {
2397 case ANDNPSrm:
2398 case ANDNPSrr:
2399 return true;
2400 }
2401 return false;
2402}
2403
2404bool isVINSERTF64X2(unsigned Opcode) {
2405 switch (Opcode) {
2406 case VINSERTF64X2Z256rmi:
2407 case VINSERTF64X2Z256rmik:
2408 case VINSERTF64X2Z256rmikz:
2409 case VINSERTF64X2Z256rri:
2410 case VINSERTF64X2Z256rrik:
2411 case VINSERTF64X2Z256rrikz:
2412 case VINSERTF64X2Zrmi:
2413 case VINSERTF64X2Zrmik:
2414 case VINSERTF64X2Zrmikz:
2415 case VINSERTF64X2Zrri:
2416 case VINSERTF64X2Zrrik:
2417 case VINSERTF64X2Zrrikz:
2418 return true;
2419 }
2420 return false;
2421}
2422
2423bool isCLTS(unsigned Opcode) {
2424 return Opcode == CLTS;
2425}
2426
2427bool isSETSSBSY(unsigned Opcode) {
2428 return Opcode == SETSSBSY;
2429}
2430
2431bool isVMULPD(unsigned Opcode) {
2432 switch (Opcode) {
2433 case VMULPDYrm:
2434 case VMULPDYrr:
2435 case VMULPDZ128rm:
2436 case VMULPDZ128rmb:
2437 case VMULPDZ128rmbk:
2438 case VMULPDZ128rmbkz:
2439 case VMULPDZ128rmk:
2440 case VMULPDZ128rmkz:
2441 case VMULPDZ128rr:
2442 case VMULPDZ128rrk:
2443 case VMULPDZ128rrkz:
2444 case VMULPDZ256rm:
2445 case VMULPDZ256rmb:
2446 case VMULPDZ256rmbk:
2447 case VMULPDZ256rmbkz:
2448 case VMULPDZ256rmk:
2449 case VMULPDZ256rmkz:
2450 case VMULPDZ256rr:
2451 case VMULPDZ256rrk:
2452 case VMULPDZ256rrkz:
2453 case VMULPDZrm:
2454 case VMULPDZrmb:
2455 case VMULPDZrmbk:
2456 case VMULPDZrmbkz:
2457 case VMULPDZrmk:
2458 case VMULPDZrmkz:
2459 case VMULPDZrr:
2460 case VMULPDZrrb:
2461 case VMULPDZrrbk:
2462 case VMULPDZrrbkz:
2463 case VMULPDZrrk:
2464 case VMULPDZrrkz:
2465 case VMULPDrm:
2466 case VMULPDrr:
2467 return true;
2468 }
2469 return false;
2470}
2471
2472bool isVFMADDSUB132PS(unsigned Opcode) {
2473 switch (Opcode) {
2474 case VFMADDSUB132PSYm:
2475 case VFMADDSUB132PSYr:
2476 case VFMADDSUB132PSZ128m:
2477 case VFMADDSUB132PSZ128mb:
2478 case VFMADDSUB132PSZ128mbk:
2479 case VFMADDSUB132PSZ128mbkz:
2480 case VFMADDSUB132PSZ128mk:
2481 case VFMADDSUB132PSZ128mkz:
2482 case VFMADDSUB132PSZ128r:
2483 case VFMADDSUB132PSZ128rk:
2484 case VFMADDSUB132PSZ128rkz:
2485 case VFMADDSUB132PSZ256m:
2486 case VFMADDSUB132PSZ256mb:
2487 case VFMADDSUB132PSZ256mbk:
2488 case VFMADDSUB132PSZ256mbkz:
2489 case VFMADDSUB132PSZ256mk:
2490 case VFMADDSUB132PSZ256mkz:
2491 case VFMADDSUB132PSZ256r:
2492 case VFMADDSUB132PSZ256rk:
2493 case VFMADDSUB132PSZ256rkz:
2494 case VFMADDSUB132PSZm:
2495 case VFMADDSUB132PSZmb:
2496 case VFMADDSUB132PSZmbk:
2497 case VFMADDSUB132PSZmbkz:
2498 case VFMADDSUB132PSZmk:
2499 case VFMADDSUB132PSZmkz:
2500 case VFMADDSUB132PSZr:
2501 case VFMADDSUB132PSZrb:
2502 case VFMADDSUB132PSZrbk:
2503 case VFMADDSUB132PSZrbkz:
2504 case VFMADDSUB132PSZrk:
2505 case VFMADDSUB132PSZrkz:
2506 case VFMADDSUB132PSm:
2507 case VFMADDSUB132PSr:
2508 return true;
2509 }
2510 return false;
2511}
2512
2513bool isVPMADCSWD(unsigned Opcode) {
2514 switch (Opcode) {
2515 case VPMADCSWDrm:
2516 case VPMADCSWDrr:
2517 return true;
2518 }
2519 return false;
2520}
2521
2522bool isVSCATTERPF0DPS(unsigned Opcode) {
2523 return Opcode == VSCATTERPF0DPSm;
2524}
2525
2526bool isXCHG(unsigned Opcode) {
2527 switch (Opcode) {
2528 case XCHG16ar:
2529 case XCHG16rm:
2530 case XCHG16rr:
2531 case XCHG32ar:
2532 case XCHG32rm:
2533 case XCHG32rr:
2534 case XCHG64ar:
2535 case XCHG64rm:
2536 case XCHG64rr:
2537 case XCHG8rm:
2538 case XCHG8rr:
2539 return true;
2540 }
2541 return false;
2542}
2543
2544bool isVGATHERPF1QPS(unsigned Opcode) {
2545 return Opcode == VGATHERPF1QPSm;
2546}
2547
2548bool isVCVTNEPS2BF16(unsigned Opcode) {
2549 switch (Opcode) {
2550 case VCVTNEPS2BF16Yrm:
2551 case VCVTNEPS2BF16Yrr:
2552 case VCVTNEPS2BF16Z128rm:
2553 case VCVTNEPS2BF16Z128rmb:
2554 case VCVTNEPS2BF16Z128rmbk:
2555 case VCVTNEPS2BF16Z128rmbkz:
2556 case VCVTNEPS2BF16Z128rmk:
2557 case VCVTNEPS2BF16Z128rmkz:
2558 case VCVTNEPS2BF16Z128rr:
2559 case VCVTNEPS2BF16Z128rrk:
2560 case VCVTNEPS2BF16Z128rrkz:
2561 case VCVTNEPS2BF16Z256rm:
2562 case VCVTNEPS2BF16Z256rmb:
2563 case VCVTNEPS2BF16Z256rmbk:
2564 case VCVTNEPS2BF16Z256rmbkz:
2565 case VCVTNEPS2BF16Z256rmk:
2566 case VCVTNEPS2BF16Z256rmkz:
2567 case VCVTNEPS2BF16Z256rr:
2568 case VCVTNEPS2BF16Z256rrk:
2569 case VCVTNEPS2BF16Z256rrkz:
2570 case VCVTNEPS2BF16Zrm:
2571 case VCVTNEPS2BF16Zrmb:
2572 case VCVTNEPS2BF16Zrmbk:
2573 case VCVTNEPS2BF16Zrmbkz:
2574 case VCVTNEPS2BF16Zrmk:
2575 case VCVTNEPS2BF16Zrmkz:
2576 case VCVTNEPS2BF16Zrr:
2577 case VCVTNEPS2BF16Zrrk:
2578 case VCVTNEPS2BF16Zrrkz:
2579 case VCVTNEPS2BF16rm:
2580 case VCVTNEPS2BF16rr:
2581 return true;
2582 }
2583 return false;
2584}
2585
2586bool isVFMADDSS(unsigned Opcode) {
2587 switch (Opcode) {
2588 case VFMADDSS4mr:
2589 case VFMADDSS4rm:
2590 case VFMADDSS4rr:
2591 case VFMADDSS4rr_REV:
2592 return true;
2593 }
2594 return false;
2595}
2596
2597bool isINTO(unsigned Opcode) {
2598 return Opcode == INTO;
2599}
2600
2601bool isANDPD(unsigned Opcode) {
2602 switch (Opcode) {
2603 case ANDPDrm:
2604 case ANDPDrr:
2605 return true;
2606 }
2607 return false;
2608}
2609
2610bool isSEAMCALL(unsigned Opcode) {
2611 return Opcode == SEAMCALL;
2612}
2613
2614bool isVPDPBSSDS(unsigned Opcode) {
2615 switch (Opcode) {
2616 case VPDPBSSDSYrm:
2617 case VPDPBSSDSYrr:
2618 case VPDPBSSDSZ128rm:
2619 case VPDPBSSDSZ128rmb:
2620 case VPDPBSSDSZ128rmbk:
2621 case VPDPBSSDSZ128rmbkz:
2622 case VPDPBSSDSZ128rmk:
2623 case VPDPBSSDSZ128rmkz:
2624 case VPDPBSSDSZ128rr:
2625 case VPDPBSSDSZ128rrk:
2626 case VPDPBSSDSZ128rrkz:
2627 case VPDPBSSDSZ256rm:
2628 case VPDPBSSDSZ256rmb:
2629 case VPDPBSSDSZ256rmbk:
2630 case VPDPBSSDSZ256rmbkz:
2631 case VPDPBSSDSZ256rmk:
2632 case VPDPBSSDSZ256rmkz:
2633 case VPDPBSSDSZ256rr:
2634 case VPDPBSSDSZ256rrk:
2635 case VPDPBSSDSZ256rrkz:
2636 case VPDPBSSDSZrm:
2637 case VPDPBSSDSZrmb:
2638 case VPDPBSSDSZrmbk:
2639 case VPDPBSSDSZrmbkz:
2640 case VPDPBSSDSZrmk:
2641 case VPDPBSSDSZrmkz:
2642 case VPDPBSSDSZrr:
2643 case VPDPBSSDSZrrk:
2644 case VPDPBSSDSZrrkz:
2645 case VPDPBSSDSrm:
2646 case VPDPBSSDSrr:
2647 return true;
2648 }
2649 return false;
2650}
2651
2652bool isUNPCKHPS(unsigned Opcode) {
2653 switch (Opcode) {
2654 case UNPCKHPSrm:
2655 case UNPCKHPSrr:
2656 return true;
2657 }
2658 return false;
2659}
2660
2661bool isSETZUCC(unsigned Opcode) {
2662 switch (Opcode) {
2663 case SETZUCCm:
2664 case SETZUCCr:
2665 return true;
2666 }
2667 return false;
2668}
2669
2670bool isSHUFPD(unsigned Opcode) {
2671 switch (Opcode) {
2672 case SHUFPDrmi:
2673 case SHUFPDrri:
2674 return true;
2675 }
2676 return false;
2677}
2678
2679bool isFCMOVNB(unsigned Opcode) {
2680 return Opcode == CMOVNB_F;
2681}
2682
2683bool isCVTTSS2SI(unsigned Opcode) {
2684 switch (Opcode) {
2685 case CVTTSS2SI64rm_Int:
2686 case CVTTSS2SI64rr_Int:
2687 case CVTTSS2SIrm_Int:
2688 case CVTTSS2SIrr_Int:
2689 return true;
2690 }
2691 return false;
2692}
2693
2694bool isEXTRQ(unsigned Opcode) {
2695 switch (Opcode) {
2696 case EXTRQ:
2697 case EXTRQI:
2698 return true;
2699 }
2700 return false;
2701}
2702
2703bool isSHLD(unsigned Opcode) {
2704 switch (Opcode) {
2705 case SHLD16mrCL:
2706 case SHLD16mrCL_EVEX:
2707 case SHLD16mrCL_ND:
2708 case SHLD16mrCL_NF:
2709 case SHLD16mrCL_NF_ND:
2710 case SHLD16mri8:
2711 case SHLD16mri8_EVEX:
2712 case SHLD16mri8_ND:
2713 case SHLD16mri8_NF:
2714 case SHLD16mri8_NF_ND:
2715 case SHLD16rrCL:
2716 case SHLD16rrCL_EVEX:
2717 case SHLD16rrCL_ND:
2718 case SHLD16rrCL_NF:
2719 case SHLD16rrCL_NF_ND:
2720 case SHLD16rri8:
2721 case SHLD16rri8_EVEX:
2722 case SHLD16rri8_ND:
2723 case SHLD16rri8_NF:
2724 case SHLD16rri8_NF_ND:
2725 case SHLD32mrCL:
2726 case SHLD32mrCL_EVEX:
2727 case SHLD32mrCL_ND:
2728 case SHLD32mrCL_NF:
2729 case SHLD32mrCL_NF_ND:
2730 case SHLD32mri8:
2731 case SHLD32mri8_EVEX:
2732 case SHLD32mri8_ND:
2733 case SHLD32mri8_NF:
2734 case SHLD32mri8_NF_ND:
2735 case SHLD32rrCL:
2736 case SHLD32rrCL_EVEX:
2737 case SHLD32rrCL_ND:
2738 case SHLD32rrCL_NF:
2739 case SHLD32rrCL_NF_ND:
2740 case SHLD32rri8:
2741 case SHLD32rri8_EVEX:
2742 case SHLD32rri8_ND:
2743 case SHLD32rri8_NF:
2744 case SHLD32rri8_NF_ND:
2745 case SHLD64mrCL:
2746 case SHLD64mrCL_EVEX:
2747 case SHLD64mrCL_ND:
2748 case SHLD64mrCL_NF:
2749 case SHLD64mrCL_NF_ND:
2750 case SHLD64mri8:
2751 case SHLD64mri8_EVEX:
2752 case SHLD64mri8_ND:
2753 case SHLD64mri8_NF:
2754 case SHLD64mri8_NF_ND:
2755 case SHLD64rrCL:
2756 case SHLD64rrCL_EVEX:
2757 case SHLD64rrCL_ND:
2758 case SHLD64rrCL_NF:
2759 case SHLD64rrCL_NF_ND:
2760 case SHLD64rri8:
2761 case SHLD64rri8_EVEX:
2762 case SHLD64rri8_ND:
2763 case SHLD64rri8_NF:
2764 case SHLD64rri8_NF_ND:
2765 return true;
2766 }
2767 return false;
2768}
2769
2770bool isVBROADCASTSS(unsigned Opcode) {
2771 switch (Opcode) {
2772 case VBROADCASTSSYrm:
2773 case VBROADCASTSSYrr:
2774 case VBROADCASTSSZ128rm:
2775 case VBROADCASTSSZ128rmk:
2776 case VBROADCASTSSZ128rmkz:
2777 case VBROADCASTSSZ128rr:
2778 case VBROADCASTSSZ128rrk:
2779 case VBROADCASTSSZ128rrkz:
2780 case VBROADCASTSSZ256rm:
2781 case VBROADCASTSSZ256rmk:
2782 case VBROADCASTSSZ256rmkz:
2783 case VBROADCASTSSZ256rr:
2784 case VBROADCASTSSZ256rrk:
2785 case VBROADCASTSSZ256rrkz:
2786 case VBROADCASTSSZrm:
2787 case VBROADCASTSSZrmk:
2788 case VBROADCASTSSZrmkz:
2789 case VBROADCASTSSZrr:
2790 case VBROADCASTSSZrrk:
2791 case VBROADCASTSSZrrkz:
2792 case VBROADCASTSSrm:
2793 case VBROADCASTSSrr:
2794 return true;
2795 }
2796 return false;
2797}
2798
2799bool isCLUI(unsigned Opcode) {
2800 return Opcode == CLUI;
2801}
2802
2803bool isVINSERTI128(unsigned Opcode) {
2804 switch (Opcode) {
2805 case VINSERTI128rmi:
2806 case VINSERTI128rri:
2807 return true;
2808 }
2809 return false;
2810}
2811
2812bool isVBLENDPD(unsigned Opcode) {
2813 switch (Opcode) {
2814 case VBLENDPDYrmi:
2815 case VBLENDPDYrri:
2816 case VBLENDPDrmi:
2817 case VBLENDPDrri:
2818 return true;
2819 }
2820 return false;
2821}
2822
2823bool isVPSHLDW(unsigned Opcode) {
2824 switch (Opcode) {
2825 case VPSHLDWZ128rmi:
2826 case VPSHLDWZ128rmik:
2827 case VPSHLDWZ128rmikz:
2828 case VPSHLDWZ128rri:
2829 case VPSHLDWZ128rrik:
2830 case VPSHLDWZ128rrikz:
2831 case VPSHLDWZ256rmi:
2832 case VPSHLDWZ256rmik:
2833 case VPSHLDWZ256rmikz:
2834 case VPSHLDWZ256rri:
2835 case VPSHLDWZ256rrik:
2836 case VPSHLDWZ256rrikz:
2837 case VPSHLDWZrmi:
2838 case VPSHLDWZrmik:
2839 case VPSHLDWZrmikz:
2840 case VPSHLDWZrri:
2841 case VPSHLDWZrrik:
2842 case VPSHLDWZrrikz:
2843 return true;
2844 }
2845 return false;
2846}
2847
2848bool isVCVTNEEPH2PS(unsigned Opcode) {
2849 switch (Opcode) {
2850 case VCVTNEEPH2PSYrm:
2851 case VCVTNEEPH2PSrm:
2852 return true;
2853 }
2854 return false;
2855}
2856
2857bool isVCVTTSD2SI(unsigned Opcode) {
2858 switch (Opcode) {
2859 case VCVTTSD2SI64Zrm_Int:
2860 case VCVTTSD2SI64Zrr_Int:
2861 case VCVTTSD2SI64Zrrb_Int:
2862 case VCVTTSD2SI64rm_Int:
2863 case VCVTTSD2SI64rr_Int:
2864 case VCVTTSD2SIZrm_Int:
2865 case VCVTTSD2SIZrr_Int:
2866 case VCVTTSD2SIZrrb_Int:
2867 case VCVTTSD2SIrm_Int:
2868 case VCVTTSD2SIrr_Int:
2869 return true;
2870 }
2871 return false;
2872}
2873
2874bool isVSM4KEY4(unsigned Opcode) {
2875 switch (Opcode) {
2876 case VSM4KEY4Yrm:
2877 case VSM4KEY4Yrr:
2878 case VSM4KEY4Z128rm:
2879 case VSM4KEY4Z128rr:
2880 case VSM4KEY4Z256rm:
2881 case VSM4KEY4Z256rr:
2882 case VSM4KEY4Zrm:
2883 case VSM4KEY4Zrr:
2884 case VSM4KEY4rm:
2885 case VSM4KEY4rr:
2886 return true;
2887 }
2888 return false;
2889}
2890
2891bool isWRMSRNS(unsigned Opcode) {
2892 switch (Opcode) {
2893 case WRMSRNS:
2894 case WRMSRNSir:
2895 case WRMSRNSir_EVEX:
2896 return true;
2897 }
2898 return false;
2899}
2900
2901bool isCMPSB(unsigned Opcode) {
2902 return Opcode == CMPSB;
2903}
2904
2905bool isVRCPBF16(unsigned Opcode) {
2906 switch (Opcode) {
2907 case VRCPBF16Z128m:
2908 case VRCPBF16Z128mb:
2909 case VRCPBF16Z128mbk:
2910 case VRCPBF16Z128mbkz:
2911 case VRCPBF16Z128mk:
2912 case VRCPBF16Z128mkz:
2913 case VRCPBF16Z128r:
2914 case VRCPBF16Z128rk:
2915 case VRCPBF16Z128rkz:
2916 case VRCPBF16Z256m:
2917 case VRCPBF16Z256mb:
2918 case VRCPBF16Z256mbk:
2919 case VRCPBF16Z256mbkz:
2920 case VRCPBF16Z256mk:
2921 case VRCPBF16Z256mkz:
2922 case VRCPBF16Z256r:
2923 case VRCPBF16Z256rk:
2924 case VRCPBF16Z256rkz:
2925 case VRCPBF16Zm:
2926 case VRCPBF16Zmb:
2927 case VRCPBF16Zmbk:
2928 case VRCPBF16Zmbkz:
2929 case VRCPBF16Zmk:
2930 case VRCPBF16Zmkz:
2931 case VRCPBF16Zr:
2932 case VRCPBF16Zrk:
2933 case VRCPBF16Zrkz:
2934 return true;
2935 }
2936 return false;
2937}
2938
2939bool isMULSS(unsigned Opcode) {
2940 switch (Opcode) {
2941 case MULSSrm_Int:
2942 case MULSSrr_Int:
2943 return true;
2944 }
2945 return false;
2946}
2947
2948bool isVMRUN(unsigned Opcode) {
2949 switch (Opcode) {
2950 case VMRUN32:
2951 case VMRUN64:
2952 return true;
2953 }
2954 return false;
2955}
2956
2957bool isVPSRLVD(unsigned Opcode) {
2958 switch (Opcode) {
2959 case VPSRLVDYrm:
2960 case VPSRLVDYrr:
2961 case VPSRLVDZ128rm:
2962 case VPSRLVDZ128rmb:
2963 case VPSRLVDZ128rmbk:
2964 case VPSRLVDZ128rmbkz:
2965 case VPSRLVDZ128rmk:
2966 case VPSRLVDZ128rmkz:
2967 case VPSRLVDZ128rr:
2968 case VPSRLVDZ128rrk:
2969 case VPSRLVDZ128rrkz:
2970 case VPSRLVDZ256rm:
2971 case VPSRLVDZ256rmb:
2972 case VPSRLVDZ256rmbk:
2973 case VPSRLVDZ256rmbkz:
2974 case VPSRLVDZ256rmk:
2975 case VPSRLVDZ256rmkz:
2976 case VPSRLVDZ256rr:
2977 case VPSRLVDZ256rrk:
2978 case VPSRLVDZ256rrkz:
2979 case VPSRLVDZrm:
2980 case VPSRLVDZrmb:
2981 case VPSRLVDZrmbk:
2982 case VPSRLVDZrmbkz:
2983 case VPSRLVDZrmk:
2984 case VPSRLVDZrmkz:
2985 case VPSRLVDZrr:
2986 case VPSRLVDZrrk:
2987 case VPSRLVDZrrkz:
2988 case VPSRLVDrm:
2989 case VPSRLVDrr:
2990 return true;
2991 }
2992 return false;
2993}
2994
2995bool isLEAVE(unsigned Opcode) {
2996 switch (Opcode) {
2997 case LEAVE:
2998 case LEAVE64:
2999 return true;
3000 }
3001 return false;
3002}
3003
3004bool isVGETMANTPS(unsigned Opcode) {
3005 switch (Opcode) {
3006 case VGETMANTPSZ128rmbi:
3007 case VGETMANTPSZ128rmbik:
3008 case VGETMANTPSZ128rmbikz:
3009 case VGETMANTPSZ128rmi:
3010 case VGETMANTPSZ128rmik:
3011 case VGETMANTPSZ128rmikz:
3012 case VGETMANTPSZ128rri:
3013 case VGETMANTPSZ128rrik:
3014 case VGETMANTPSZ128rrikz:
3015 case VGETMANTPSZ256rmbi:
3016 case VGETMANTPSZ256rmbik:
3017 case VGETMANTPSZ256rmbikz:
3018 case VGETMANTPSZ256rmi:
3019 case VGETMANTPSZ256rmik:
3020 case VGETMANTPSZ256rmikz:
3021 case VGETMANTPSZ256rri:
3022 case VGETMANTPSZ256rrik:
3023 case VGETMANTPSZ256rrikz:
3024 case VGETMANTPSZrmbi:
3025 case VGETMANTPSZrmbik:
3026 case VGETMANTPSZrmbikz:
3027 case VGETMANTPSZrmi:
3028 case VGETMANTPSZrmik:
3029 case VGETMANTPSZrmikz:
3030 case VGETMANTPSZrri:
3031 case VGETMANTPSZrrib:
3032 case VGETMANTPSZrribk:
3033 case VGETMANTPSZrribkz:
3034 case VGETMANTPSZrrik:
3035 case VGETMANTPSZrrikz:
3036 return true;
3037 }
3038 return false;
3039}
3040
3041bool isXSHA256(unsigned Opcode) {
3042 return Opcode == XSHA256;
3043}
3044
3045bool isBOUND(unsigned Opcode) {
3046 switch (Opcode) {
3047 case BOUNDS16rm:
3048 case BOUNDS32rm:
3049 return true;
3050 }
3051 return false;
3052}
3053
3054bool isSFENCE(unsigned Opcode) {
3055 return Opcode == SFENCE;
3056}
3057
3058bool isVPHADDD(unsigned Opcode) {
3059 switch (Opcode) {
3060 case VPHADDDYrm:
3061 case VPHADDDYrr:
3062 case VPHADDDrm:
3063 case VPHADDDrr:
3064 return true;
3065 }
3066 return false;
3067}
3068
3069bool isADOX(unsigned Opcode) {
3070 switch (Opcode) {
3071 case ADOX32rm:
3072 case ADOX32rm_EVEX:
3073 case ADOX32rm_ND:
3074 case ADOX32rr:
3075 case ADOX32rr_EVEX:
3076 case ADOX32rr_ND:
3077 case ADOX64rm:
3078 case ADOX64rm_EVEX:
3079 case ADOX64rm_ND:
3080 case ADOX64rr:
3081 case ADOX64rr_EVEX:
3082 case ADOX64rr_ND:
3083 return true;
3084 }
3085 return false;
3086}
3087
3088bool isVPSLLQ(unsigned Opcode) {
3089 switch (Opcode) {
3090 case VPSLLQYri:
3091 case VPSLLQYrm:
3092 case VPSLLQYrr:
3093 case VPSLLQZ128mbi:
3094 case VPSLLQZ128mbik:
3095 case VPSLLQZ128mbikz:
3096 case VPSLLQZ128mi:
3097 case VPSLLQZ128mik:
3098 case VPSLLQZ128mikz:
3099 case VPSLLQZ128ri:
3100 case VPSLLQZ128rik:
3101 case VPSLLQZ128rikz:
3102 case VPSLLQZ128rm:
3103 case VPSLLQZ128rmk:
3104 case VPSLLQZ128rmkz:
3105 case VPSLLQZ128rr:
3106 case VPSLLQZ128rrk:
3107 case VPSLLQZ128rrkz:
3108 case VPSLLQZ256mbi:
3109 case VPSLLQZ256mbik:
3110 case VPSLLQZ256mbikz:
3111 case VPSLLQZ256mi:
3112 case VPSLLQZ256mik:
3113 case VPSLLQZ256mikz:
3114 case VPSLLQZ256ri:
3115 case VPSLLQZ256rik:
3116 case VPSLLQZ256rikz:
3117 case VPSLLQZ256rm:
3118 case VPSLLQZ256rmk:
3119 case VPSLLQZ256rmkz:
3120 case VPSLLQZ256rr:
3121 case VPSLLQZ256rrk:
3122 case VPSLLQZ256rrkz:
3123 case VPSLLQZmbi:
3124 case VPSLLQZmbik:
3125 case VPSLLQZmbikz:
3126 case VPSLLQZmi:
3127 case VPSLLQZmik:
3128 case VPSLLQZmikz:
3129 case VPSLLQZri:
3130 case VPSLLQZrik:
3131 case VPSLLQZrikz:
3132 case VPSLLQZrm:
3133 case VPSLLQZrmk:
3134 case VPSLLQZrmkz:
3135 case VPSLLQZrr:
3136 case VPSLLQZrrk:
3137 case VPSLLQZrrkz:
3138 case VPSLLQri:
3139 case VPSLLQrm:
3140 case VPSLLQrr:
3141 return true;
3142 }
3143 return false;
3144}
3145
3146bool isVCVTPH2HF8(unsigned Opcode) {
3147 switch (Opcode) {
3148 case VCVTPH2HF8Z128rm:
3149 case VCVTPH2HF8Z128rmb:
3150 case VCVTPH2HF8Z128rmbk:
3151 case VCVTPH2HF8Z128rmbkz:
3152 case VCVTPH2HF8Z128rmk:
3153 case VCVTPH2HF8Z128rmkz:
3154 case VCVTPH2HF8Z128rr:
3155 case VCVTPH2HF8Z128rrk:
3156 case VCVTPH2HF8Z128rrkz:
3157 case VCVTPH2HF8Z256rm:
3158 case VCVTPH2HF8Z256rmb:
3159 case VCVTPH2HF8Z256rmbk:
3160 case VCVTPH2HF8Z256rmbkz:
3161 case VCVTPH2HF8Z256rmk:
3162 case VCVTPH2HF8Z256rmkz:
3163 case VCVTPH2HF8Z256rr:
3164 case VCVTPH2HF8Z256rrk:
3165 case VCVTPH2HF8Z256rrkz:
3166 case VCVTPH2HF8Zrm:
3167 case VCVTPH2HF8Zrmb:
3168 case VCVTPH2HF8Zrmbk:
3169 case VCVTPH2HF8Zrmbkz:
3170 case VCVTPH2HF8Zrmk:
3171 case VCVTPH2HF8Zrmkz:
3172 case VCVTPH2HF8Zrr:
3173 case VCVTPH2HF8Zrrk:
3174 case VCVTPH2HF8Zrrkz:
3175 return true;
3176 }
3177 return false;
3178}
3179
3180bool isPFRSQIT1(unsigned Opcode) {
3181 switch (Opcode) {
3182 case PFRSQIT1rm:
3183 case PFRSQIT1rr:
3184 return true;
3185 }
3186 return false;
3187}
3188
3189bool isCLAC(unsigned Opcode) {
3190 return Opcode == CLAC;
3191}
3192
3193bool isKNOTW(unsigned Opcode) {
3194 return Opcode == KNOTWkk;
3195}
3196
3197bool isVCVTPH2PD(unsigned Opcode) {
3198 switch (Opcode) {
3199 case VCVTPH2PDZ128rm:
3200 case VCVTPH2PDZ128rmb:
3201 case VCVTPH2PDZ128rmbk:
3202 case VCVTPH2PDZ128rmbkz:
3203 case VCVTPH2PDZ128rmk:
3204 case VCVTPH2PDZ128rmkz:
3205 case VCVTPH2PDZ128rr:
3206 case VCVTPH2PDZ128rrk:
3207 case VCVTPH2PDZ128rrkz:
3208 case VCVTPH2PDZ256rm:
3209 case VCVTPH2PDZ256rmb:
3210 case VCVTPH2PDZ256rmbk:
3211 case VCVTPH2PDZ256rmbkz:
3212 case VCVTPH2PDZ256rmk:
3213 case VCVTPH2PDZ256rmkz:
3214 case VCVTPH2PDZ256rr:
3215 case VCVTPH2PDZ256rrk:
3216 case VCVTPH2PDZ256rrkz:
3217 case VCVTPH2PDZrm:
3218 case VCVTPH2PDZrmb:
3219 case VCVTPH2PDZrmbk:
3220 case VCVTPH2PDZrmbkz:
3221 case VCVTPH2PDZrmk:
3222 case VCVTPH2PDZrmkz:
3223 case VCVTPH2PDZrr:
3224 case VCVTPH2PDZrrb:
3225 case VCVTPH2PDZrrbk:
3226 case VCVTPH2PDZrrbkz:
3227 case VCVTPH2PDZrrk:
3228 case VCVTPH2PDZrrkz:
3229 return true;
3230 }
3231 return false;
3232}
3233
3234bool isVAESENC(unsigned Opcode) {
3235 switch (Opcode) {
3236 case VAESENCYrm:
3237 case VAESENCYrr:
3238 case VAESENCZ128rm:
3239 case VAESENCZ128rr:
3240 case VAESENCZ256rm:
3241 case VAESENCZ256rr:
3242 case VAESENCZrm:
3243 case VAESENCZrr:
3244 case VAESENCrm:
3245 case VAESENCrr:
3246 return true;
3247 }
3248 return false;
3249}
3250
3251bool isMOVNTI(unsigned Opcode) {
3252 switch (Opcode) {
3253 case MOVNTI_64mr:
3254 case MOVNTImr:
3255 return true;
3256 }
3257 return false;
3258}
3259
3260bool isFXCH(unsigned Opcode) {
3261 return Opcode == XCH_F;
3262}
3263
3264bool isPOPP(unsigned Opcode) {
3265 return Opcode == POPP64r;
3266}
3267
3268bool isVPBLENDMD(unsigned Opcode) {
3269 switch (Opcode) {
3270 case VPBLENDMDZ128rm:
3271 case VPBLENDMDZ128rmb:
3272 case VPBLENDMDZ128rmbk:
3273 case VPBLENDMDZ128rmbkz:
3274 case VPBLENDMDZ128rmk:
3275 case VPBLENDMDZ128rmkz:
3276 case VPBLENDMDZ128rr:
3277 case VPBLENDMDZ128rrk:
3278 case VPBLENDMDZ128rrkz:
3279 case VPBLENDMDZ256rm:
3280 case VPBLENDMDZ256rmb:
3281 case VPBLENDMDZ256rmbk:
3282 case VPBLENDMDZ256rmbkz:
3283 case VPBLENDMDZ256rmk:
3284 case VPBLENDMDZ256rmkz:
3285 case VPBLENDMDZ256rr:
3286 case VPBLENDMDZ256rrk:
3287 case VPBLENDMDZ256rrkz:
3288 case VPBLENDMDZrm:
3289 case VPBLENDMDZrmb:
3290 case VPBLENDMDZrmbk:
3291 case VPBLENDMDZrmbkz:
3292 case VPBLENDMDZrmk:
3293 case VPBLENDMDZrmkz:
3294 case VPBLENDMDZrr:
3295 case VPBLENDMDZrrk:
3296 case VPBLENDMDZrrkz:
3297 return true;
3298 }
3299 return false;
3300}
3301
3302bool isFSINCOS(unsigned Opcode) {
3303 return Opcode == FSINCOS;
3304}
3305
3306bool isVPMULLW(unsigned Opcode) {
3307 switch (Opcode) {
3308 case VPMULLWYrm:
3309 case VPMULLWYrr:
3310 case VPMULLWZ128rm:
3311 case VPMULLWZ128rmk:
3312 case VPMULLWZ128rmkz:
3313 case VPMULLWZ128rr:
3314 case VPMULLWZ128rrk:
3315 case VPMULLWZ128rrkz:
3316 case VPMULLWZ256rm:
3317 case VPMULLWZ256rmk:
3318 case VPMULLWZ256rmkz:
3319 case VPMULLWZ256rr:
3320 case VPMULLWZ256rrk:
3321 case VPMULLWZ256rrkz:
3322 case VPMULLWZrm:
3323 case VPMULLWZrmk:
3324 case VPMULLWZrmkz:
3325 case VPMULLWZrr:
3326 case VPMULLWZrrk:
3327 case VPMULLWZrrkz:
3328 case VPMULLWrm:
3329 case VPMULLWrr:
3330 return true;
3331 }
3332 return false;
3333}
3334
3335bool isVPMOVSXBW(unsigned Opcode) {
3336 switch (Opcode) {
3337 case VPMOVSXBWYrm:
3338 case VPMOVSXBWYrr:
3339 case VPMOVSXBWZ128rm:
3340 case VPMOVSXBWZ128rmk:
3341 case VPMOVSXBWZ128rmkz:
3342 case VPMOVSXBWZ128rr:
3343 case VPMOVSXBWZ128rrk:
3344 case VPMOVSXBWZ128rrkz:
3345 case VPMOVSXBWZ256rm:
3346 case VPMOVSXBWZ256rmk:
3347 case VPMOVSXBWZ256rmkz:
3348 case VPMOVSXBWZ256rr:
3349 case VPMOVSXBWZ256rrk:
3350 case VPMOVSXBWZ256rrkz:
3351 case VPMOVSXBWZrm:
3352 case VPMOVSXBWZrmk:
3353 case VPMOVSXBWZrmkz:
3354 case VPMOVSXBWZrr:
3355 case VPMOVSXBWZrrk:
3356 case VPMOVSXBWZrrkz:
3357 case VPMOVSXBWrm:
3358 case VPMOVSXBWrr:
3359 return true;
3360 }
3361 return false;
3362}
3363
3364bool isSTC(unsigned Opcode) {
3365 return Opcode == STC;
3366}
3367
3368bool isVPINSRB(unsigned Opcode) {
3369 switch (Opcode) {
3370 case VPINSRBZrmi:
3371 case VPINSRBZrri:
3372 case VPINSRBrmi:
3373 case VPINSRBrri:
3374 return true;
3375 }
3376 return false;
3377}
3378
3379bool isLWPVAL(unsigned Opcode) {
3380 switch (Opcode) {
3381 case LWPVAL32rmi:
3382 case LWPVAL32rri:
3383 case LWPVAL64rmi:
3384 case LWPVAL64rri:
3385 return true;
3386 }
3387 return false;
3388}
3389
3390bool isKXORB(unsigned Opcode) {
3391 return Opcode == KXORBkk;
3392}
3393
3394bool isRSTORSSP(unsigned Opcode) {
3395 return Opcode == RSTORSSP;
3396}
3397
3398bool isVPRORQ(unsigned Opcode) {
3399 switch (Opcode) {
3400 case VPRORQZ128mbi:
3401 case VPRORQZ128mbik:
3402 case VPRORQZ128mbikz:
3403 case VPRORQZ128mi:
3404 case VPRORQZ128mik:
3405 case VPRORQZ128mikz:
3406 case VPRORQZ128ri:
3407 case VPRORQZ128rik:
3408 case VPRORQZ128rikz:
3409 case VPRORQZ256mbi:
3410 case VPRORQZ256mbik:
3411 case VPRORQZ256mbikz:
3412 case VPRORQZ256mi:
3413 case VPRORQZ256mik:
3414 case VPRORQZ256mikz:
3415 case VPRORQZ256ri:
3416 case VPRORQZ256rik:
3417 case VPRORQZ256rikz:
3418 case VPRORQZmbi:
3419 case VPRORQZmbik:
3420 case VPRORQZmbikz:
3421 case VPRORQZmi:
3422 case VPRORQZmik:
3423 case VPRORQZmikz:
3424 case VPRORQZri:
3425 case VPRORQZrik:
3426 case VPRORQZrikz:
3427 return true;
3428 }
3429 return false;
3430}
3431
3432bool isVSM3MSG1(unsigned Opcode) {
3433 switch (Opcode) {
3434 case VSM3MSG1rm:
3435 case VSM3MSG1rr:
3436 return true;
3437 }
3438 return false;
3439}
3440
3441bool isFICOM(unsigned Opcode) {
3442 switch (Opcode) {
3443 case FICOM16m:
3444 case FICOM32m:
3445 return true;
3446 }
3447 return false;
3448}
3449
3450bool isMAXPS(unsigned Opcode) {
3451 switch (Opcode) {
3452 case MAXPSrm:
3453 case MAXPSrr:
3454 return true;
3455 }
3456 return false;
3457}
3458
3459bool isFNCLEX(unsigned Opcode) {
3460 return Opcode == FNCLEX;
3461}
3462
3463bool isVMOVMSKPS(unsigned Opcode) {
3464 switch (Opcode) {
3465 case VMOVMSKPSYrr:
3466 case VMOVMSKPSrr:
3467 return true;
3468 }
3469 return false;
3470}
3471
3472bool isVPMOVDB(unsigned Opcode) {
3473 switch (Opcode) {
3474 case VPMOVDBZ128mr:
3475 case VPMOVDBZ128mrk:
3476 case VPMOVDBZ128rr:
3477 case VPMOVDBZ128rrk:
3478 case VPMOVDBZ128rrkz:
3479 case VPMOVDBZ256mr:
3480 case VPMOVDBZ256mrk:
3481 case VPMOVDBZ256rr:
3482 case VPMOVDBZ256rrk:
3483 case VPMOVDBZ256rrkz:
3484 case VPMOVDBZmr:
3485 case VPMOVDBZmrk:
3486 case VPMOVDBZrr:
3487 case VPMOVDBZrrk:
3488 case VPMOVDBZrrkz:
3489 return true;
3490 }
3491 return false;
3492}
3493
3494bool isLLWPCB(unsigned Opcode) {
3495 switch (Opcode) {
3496 case LLWPCB:
3497 case LLWPCB64:
3498 return true;
3499 }
3500 return false;
3501}
3502
3503bool isVMULSS(unsigned Opcode) {
3504 switch (Opcode) {
3505 case VMULSSZrm_Int:
3506 case VMULSSZrmk_Int:
3507 case VMULSSZrmkz_Int:
3508 case VMULSSZrr_Int:
3509 case VMULSSZrrb_Int:
3510 case VMULSSZrrbk_Int:
3511 case VMULSSZrrbkz_Int:
3512 case VMULSSZrrk_Int:
3513 case VMULSSZrrkz_Int:
3514 case VMULSSrm_Int:
3515 case VMULSSrr_Int:
3516 return true;
3517 }
3518 return false;
3519}
3520
3521bool isAESENCLAST(unsigned Opcode) {
3522 switch (Opcode) {
3523 case AESENCLASTrm:
3524 case AESENCLASTrr:
3525 return true;
3526 }
3527 return false;
3528}
3529
3530bool isTILEMOVROW(unsigned Opcode) {
3531 switch (Opcode) {
3532 case TILEMOVROWrte:
3533 case TILEMOVROWrti:
3534 return true;
3535 }
3536 return false;
3537}
3538
3539bool isVMINMAXPH(unsigned Opcode) {
3540 switch (Opcode) {
3541 case VMINMAXPHZ128rmbi:
3542 case VMINMAXPHZ128rmbik:
3543 case VMINMAXPHZ128rmbikz:
3544 case VMINMAXPHZ128rmi:
3545 case VMINMAXPHZ128rmik:
3546 case VMINMAXPHZ128rmikz:
3547 case VMINMAXPHZ128rri:
3548 case VMINMAXPHZ128rrik:
3549 case VMINMAXPHZ128rrikz:
3550 case VMINMAXPHZ256rmbi:
3551 case VMINMAXPHZ256rmbik:
3552 case VMINMAXPHZ256rmbikz:
3553 case VMINMAXPHZ256rmi:
3554 case VMINMAXPHZ256rmik:
3555 case VMINMAXPHZ256rmikz:
3556 case VMINMAXPHZ256rri:
3557 case VMINMAXPHZ256rrik:
3558 case VMINMAXPHZ256rrikz:
3559 case VMINMAXPHZrmbi:
3560 case VMINMAXPHZrmbik:
3561 case VMINMAXPHZrmbikz:
3562 case VMINMAXPHZrmi:
3563 case VMINMAXPHZrmik:
3564 case VMINMAXPHZrmikz:
3565 case VMINMAXPHZrri:
3566 case VMINMAXPHZrrib:
3567 case VMINMAXPHZrribk:
3568 case VMINMAXPHZrribkz:
3569 case VMINMAXPHZrrik:
3570 case VMINMAXPHZrrikz:
3571 return true;
3572 }
3573 return false;
3574}
3575
3576bool isVPMAXUB(unsigned Opcode) {
3577 switch (Opcode) {
3578 case VPMAXUBYrm:
3579 case VPMAXUBYrr:
3580 case VPMAXUBZ128rm:
3581 case VPMAXUBZ128rmk:
3582 case VPMAXUBZ128rmkz:
3583 case VPMAXUBZ128rr:
3584 case VPMAXUBZ128rrk:
3585 case VPMAXUBZ128rrkz:
3586 case VPMAXUBZ256rm:
3587 case VPMAXUBZ256rmk:
3588 case VPMAXUBZ256rmkz:
3589 case VPMAXUBZ256rr:
3590 case VPMAXUBZ256rrk:
3591 case VPMAXUBZ256rrkz:
3592 case VPMAXUBZrm:
3593 case VPMAXUBZrmk:
3594 case VPMAXUBZrmkz:
3595 case VPMAXUBZrr:
3596 case VPMAXUBZrrk:
3597 case VPMAXUBZrrkz:
3598 case VPMAXUBrm:
3599 case VPMAXUBrr:
3600 return true;
3601 }
3602 return false;
3603}
3604
3605bool isAAS(unsigned Opcode) {
3606 return Opcode == AAS;
3607}
3608
3609bool isFADD(unsigned Opcode) {
3610 switch (Opcode) {
3611 case ADD_F32m:
3612 case ADD_F64m:
3613 case ADD_FST0r:
3614 case ADD_FrST0:
3615 return true;
3616 }
3617 return false;
3618}
3619
3620bool isJMP(unsigned Opcode) {
3621 switch (Opcode) {
3622 case FARJMP32m:
3623 case JMP16m:
3624 case JMP16r:
3625 case JMP32m:
3626 case JMP32r:
3627 case JMP64m:
3628 case JMP64r:
3629 case JMP_1:
3630 case JMP_2:
3631 case JMP_4:
3632 return true;
3633 }
3634 return false;
3635}
3636
3637bool isXCRYPTECB(unsigned Opcode) {
3638 return Opcode == XCRYPTECB;
3639}
3640
3641bool isPFRCPIT1(unsigned Opcode) {
3642 switch (Opcode) {
3643 case PFRCPIT1rm:
3644 case PFRCPIT1rr:
3645 return true;
3646 }
3647 return false;
3648}
3649
3650bool isPMULHRW(unsigned Opcode) {
3651 switch (Opcode) {
3652 case PMULHRWrm:
3653 case PMULHRWrr:
3654 return true;
3655 }
3656 return false;
3657}
3658
3659bool isVCVTPH2PS(unsigned Opcode) {
3660 switch (Opcode) {
3661 case VCVTPH2PSYrm:
3662 case VCVTPH2PSYrr:
3663 case VCVTPH2PSZ128rm:
3664 case VCVTPH2PSZ128rmk:
3665 case VCVTPH2PSZ128rmkz:
3666 case VCVTPH2PSZ128rr:
3667 case VCVTPH2PSZ128rrk:
3668 case VCVTPH2PSZ128rrkz:
3669 case VCVTPH2PSZ256rm:
3670 case VCVTPH2PSZ256rmk:
3671 case VCVTPH2PSZ256rmkz:
3672 case VCVTPH2PSZ256rr:
3673 case VCVTPH2PSZ256rrk:
3674 case VCVTPH2PSZ256rrkz:
3675 case VCVTPH2PSZrm:
3676 case VCVTPH2PSZrmk:
3677 case VCVTPH2PSZrmkz:
3678 case VCVTPH2PSZrr:
3679 case VCVTPH2PSZrrb:
3680 case VCVTPH2PSZrrbk:
3681 case VCVTPH2PSZrrbkz:
3682 case VCVTPH2PSZrrk:
3683 case VCVTPH2PSZrrkz:
3684 case VCVTPH2PSrm:
3685 case VCVTPH2PSrr:
3686 return true;
3687 }
3688 return false;
3689}
3690
3691bool isVPBLENDVB(unsigned Opcode) {
3692 switch (Opcode) {
3693 case VPBLENDVBYrmr:
3694 case VPBLENDVBYrrr:
3695 case VPBLENDVBrmr:
3696 case VPBLENDVBrrr:
3697 return true;
3698 }
3699 return false;
3700}
3701
3702bool isPCMPESTRI(unsigned Opcode) {
3703 switch (Opcode) {
3704 case PCMPESTRIrmi:
3705 case PCMPESTRIrri:
3706 return true;
3707 }
3708 return false;
3709}
3710
3711bool isSENDUIPI(unsigned Opcode) {
3712 return Opcode == SENDUIPI;
3713}
3714
3715bool isFLDLN2(unsigned Opcode) {
3716 return Opcode == FLDLN2;
3717}
3718
3719bool isVPMACSWD(unsigned Opcode) {
3720 switch (Opcode) {
3721 case VPMACSWDrm:
3722 case VPMACSWDrr:
3723 return true;
3724 }
3725 return false;
3726}
3727
3728bool isSHA1MSG1(unsigned Opcode) {
3729 switch (Opcode) {
3730 case SHA1MSG1rm:
3731 case SHA1MSG1rr:
3732 return true;
3733 }
3734 return false;
3735}
3736
3737bool isVADDPS(unsigned Opcode) {
3738 switch (Opcode) {
3739 case VADDPSYrm:
3740 case VADDPSYrr:
3741 case VADDPSZ128rm:
3742 case VADDPSZ128rmb:
3743 case VADDPSZ128rmbk:
3744 case VADDPSZ128rmbkz:
3745 case VADDPSZ128rmk:
3746 case VADDPSZ128rmkz:
3747 case VADDPSZ128rr:
3748 case VADDPSZ128rrk:
3749 case VADDPSZ128rrkz:
3750 case VADDPSZ256rm:
3751 case VADDPSZ256rmb:
3752 case VADDPSZ256rmbk:
3753 case VADDPSZ256rmbkz:
3754 case VADDPSZ256rmk:
3755 case VADDPSZ256rmkz:
3756 case VADDPSZ256rr:
3757 case VADDPSZ256rrk:
3758 case VADDPSZ256rrkz:
3759 case VADDPSZrm:
3760 case VADDPSZrmb:
3761 case VADDPSZrmbk:
3762 case VADDPSZrmbkz:
3763 case VADDPSZrmk:
3764 case VADDPSZrmkz:
3765 case VADDPSZrr:
3766 case VADDPSZrrb:
3767 case VADDPSZrrbk:
3768 case VADDPSZrrbkz:
3769 case VADDPSZrrk:
3770 case VADDPSZrrkz:
3771 case VADDPSrm:
3772 case VADDPSrr:
3773 return true;
3774 }
3775 return false;
3776}
3777
3778bool isVCVTPS2DQ(unsigned Opcode) {
3779 switch (Opcode) {
3780 case VCVTPS2DQYrm:
3781 case VCVTPS2DQYrr:
3782 case VCVTPS2DQZ128rm:
3783 case VCVTPS2DQZ128rmb:
3784 case VCVTPS2DQZ128rmbk:
3785 case VCVTPS2DQZ128rmbkz:
3786 case VCVTPS2DQZ128rmk:
3787 case VCVTPS2DQZ128rmkz:
3788 case VCVTPS2DQZ128rr:
3789 case VCVTPS2DQZ128rrk:
3790 case VCVTPS2DQZ128rrkz:
3791 case VCVTPS2DQZ256rm:
3792 case VCVTPS2DQZ256rmb:
3793 case VCVTPS2DQZ256rmbk:
3794 case VCVTPS2DQZ256rmbkz:
3795 case VCVTPS2DQZ256rmk:
3796 case VCVTPS2DQZ256rmkz:
3797 case VCVTPS2DQZ256rr:
3798 case VCVTPS2DQZ256rrk:
3799 case VCVTPS2DQZ256rrkz:
3800 case VCVTPS2DQZrm:
3801 case VCVTPS2DQZrmb:
3802 case VCVTPS2DQZrmbk:
3803 case VCVTPS2DQZrmbkz:
3804 case VCVTPS2DQZrmk:
3805 case VCVTPS2DQZrmkz:
3806 case VCVTPS2DQZrr:
3807 case VCVTPS2DQZrrb:
3808 case VCVTPS2DQZrrbk:
3809 case VCVTPS2DQZrrbkz:
3810 case VCVTPS2DQZrrk:
3811 case VCVTPS2DQZrrkz:
3812 case VCVTPS2DQrm:
3813 case VCVTPS2DQrr:
3814 return true;
3815 }
3816 return false;
3817}
3818
3819bool isPFPNACC(unsigned Opcode) {
3820 switch (Opcode) {
3821 case PFPNACCrm:
3822 case PFPNACCrr:
3823 return true;
3824 }
3825 return false;
3826}
3827
3828bool isFMUL(unsigned Opcode) {
3829 switch (Opcode) {
3830 case MUL_F32m:
3831 case MUL_F64m:
3832 case MUL_FST0r:
3833 case MUL_FrST0:
3834 return true;
3835 }
3836 return false;
3837}
3838
3839bool isFNSAVE(unsigned Opcode) {
3840 return Opcode == FSAVEm;
3841}
3842
3843bool isCDQE(unsigned Opcode) {
3844 return Opcode == CDQE;
3845}
3846
3847bool isVPMACSDD(unsigned Opcode) {
3848 switch (Opcode) {
3849 case VPMACSDDrm:
3850 case VPMACSDDrr:
3851 return true;
3852 }
3853 return false;
3854}
3855
3856bool isVSQRTPS(unsigned Opcode) {
3857 switch (Opcode) {
3858 case VSQRTPSYm:
3859 case VSQRTPSYr:
3860 case VSQRTPSZ128m:
3861 case VSQRTPSZ128mb:
3862 case VSQRTPSZ128mbk:
3863 case VSQRTPSZ128mbkz:
3864 case VSQRTPSZ128mk:
3865 case VSQRTPSZ128mkz:
3866 case VSQRTPSZ128r:
3867 case VSQRTPSZ128rk:
3868 case VSQRTPSZ128rkz:
3869 case VSQRTPSZ256m:
3870 case VSQRTPSZ256mb:
3871 case VSQRTPSZ256mbk:
3872 case VSQRTPSZ256mbkz:
3873 case VSQRTPSZ256mk:
3874 case VSQRTPSZ256mkz:
3875 case VSQRTPSZ256r:
3876 case VSQRTPSZ256rk:
3877 case VSQRTPSZ256rkz:
3878 case VSQRTPSZm:
3879 case VSQRTPSZmb:
3880 case VSQRTPSZmbk:
3881 case VSQRTPSZmbkz:
3882 case VSQRTPSZmk:
3883 case VSQRTPSZmkz:
3884 case VSQRTPSZr:
3885 case VSQRTPSZrb:
3886 case VSQRTPSZrbk:
3887 case VSQRTPSZrbkz:
3888 case VSQRTPSZrk:
3889 case VSQRTPSZrkz:
3890 case VSQRTPSm:
3891 case VSQRTPSr:
3892 return true;
3893 }
3894 return false;
3895}
3896
3897bool isCMPSQ(unsigned Opcode) {
3898 return Opcode == CMPSQ;
3899}
3900
3901bool isVPSCATTERDD(unsigned Opcode) {
3902 switch (Opcode) {
3903 case VPSCATTERDDZ128mr:
3904 case VPSCATTERDDZ256mr:
3905 case VPSCATTERDDZmr:
3906 return true;
3907 }
3908 return false;
3909}
3910
3911bool isVCVTTSD2USIS(unsigned Opcode) {
3912 switch (Opcode) {
3913 case VCVTTSD2USI64Srm_Int:
3914 case VCVTTSD2USI64Srr_Int:
3915 case VCVTTSD2USI64Srrb_Int:
3916 case VCVTTSD2USISrm_Int:
3917 case VCVTTSD2USISrr_Int:
3918 case VCVTTSD2USISrrb_Int:
3919 return true;
3920 }
3921 return false;
3922}
3923
3924bool isVRNDSCALESD(unsigned Opcode) {
3925 switch (Opcode) {
3926 case VRNDSCALESDZrmi_Int:
3927 case VRNDSCALESDZrmik_Int:
3928 case VRNDSCALESDZrmikz_Int:
3929 case VRNDSCALESDZrri_Int:
3930 case VRNDSCALESDZrrib_Int:
3931 case VRNDSCALESDZrribk_Int:
3932 case VRNDSCALESDZrribkz_Int:
3933 case VRNDSCALESDZrrik_Int:
3934 case VRNDSCALESDZrrikz_Int:
3935 return true;
3936 }
3937 return false;
3938}
3939
3940bool isSUBPS(unsigned Opcode) {
3941 switch (Opcode) {
3942 case SUBPSrm:
3943 case SUBPSrr:
3944 return true;
3945 }
3946 return false;
3947}
3948
3949bool isVMAXSH(unsigned Opcode) {
3950 switch (Opcode) {
3951 case VMAXSHZrm_Int:
3952 case VMAXSHZrmk_Int:
3953 case VMAXSHZrmkz_Int:
3954 case VMAXSHZrr_Int:
3955 case VMAXSHZrrb_Int:
3956 case VMAXSHZrrbk_Int:
3957 case VMAXSHZrrbkz_Int:
3958 case VMAXSHZrrk_Int:
3959 case VMAXSHZrrkz_Int:
3960 return true;
3961 }
3962 return false;
3963}
3964
3965bool isFLDZ(unsigned Opcode) {
3966 return Opcode == LD_F0;
3967}
3968
3969bool isVFNMADD132SS(unsigned Opcode) {
3970 switch (Opcode) {
3971 case VFNMADD132SSZm_Int:
3972 case VFNMADD132SSZmk_Int:
3973 case VFNMADD132SSZmkz_Int:
3974 case VFNMADD132SSZr_Int:
3975 case VFNMADD132SSZrb_Int:
3976 case VFNMADD132SSZrbk_Int:
3977 case VFNMADD132SSZrbkz_Int:
3978 case VFNMADD132SSZrk_Int:
3979 case VFNMADD132SSZrkz_Int:
3980 case VFNMADD132SSm_Int:
3981 case VFNMADD132SSr_Int:
3982 return true;
3983 }
3984 return false;
3985}
3986
3987bool isLGDTW(unsigned Opcode) {
3988 return Opcode == LGDT16m;
3989}
3990
3991bool isTCVTROWPS2PHH(unsigned Opcode) {
3992 switch (Opcode) {
3993 case TCVTROWPS2PHHrte:
3994 case TCVTROWPS2PHHrti:
3995 return true;
3996 }
3997 return false;
3998}
3999
4000bool isINC(unsigned Opcode) {
4001 switch (Opcode) {
4002 case INC16m:
4003 case INC16m_EVEX:
4004 case INC16m_ND:
4005 case INC16m_NF:
4006 case INC16m_NF_ND:
4007 case INC16r:
4008 case INC16r_EVEX:
4009 case INC16r_ND:
4010 case INC16r_NF:
4011 case INC16r_NF_ND:
4012 case INC16r_alt:
4013 case INC32m:
4014 case INC32m_EVEX:
4015 case INC32m_ND:
4016 case INC32m_NF:
4017 case INC32m_NF_ND:
4018 case INC32r:
4019 case INC32r_EVEX:
4020 case INC32r_ND:
4021 case INC32r_NF:
4022 case INC32r_NF_ND:
4023 case INC32r_alt:
4024 case INC64m:
4025 case INC64m_EVEX:
4026 case INC64m_ND:
4027 case INC64m_NF:
4028 case INC64m_NF_ND:
4029 case INC64r:
4030 case INC64r_EVEX:
4031 case INC64r_ND:
4032 case INC64r_NF:
4033 case INC64r_NF_ND:
4034 case INC8m:
4035 case INC8m_EVEX:
4036 case INC8m_ND:
4037 case INC8m_NF:
4038 case INC8m_NF_ND:
4039 case INC8r:
4040 case INC8r_EVEX:
4041 case INC8r_ND:
4042 case INC8r_NF:
4043 case INC8r_NF_ND:
4044 return true;
4045 }
4046 return false;
4047}
4048
4049bool isVPANDN(unsigned Opcode) {
4050 switch (Opcode) {
4051 case VPANDNYrm:
4052 case VPANDNYrr:
4053 case VPANDNrm:
4054 case VPANDNrr:
4055 return true;
4056 }
4057 return false;
4058}
4059
4060bool isPABSB(unsigned Opcode) {
4061 switch (Opcode) {
4062 case MMX_PABSBrm:
4063 case MMX_PABSBrr:
4064 case PABSBrm:
4065 case PABSBrr:
4066 return true;
4067 }
4068 return false;
4069}
4070
4071bool isVSHA512RNDS2(unsigned Opcode) {
4072 return Opcode == VSHA512RNDS2rr;
4073}
4074
4075bool isPHADDSW(unsigned Opcode) {
4076 switch (Opcode) {
4077 case MMX_PHADDSWrm:
4078 case MMX_PHADDSWrr:
4079 case PHADDSWrm:
4080 case PHADDSWrr:
4081 return true;
4082 }
4083 return false;
4084}
4085
4086bool isVPMAXUD(unsigned Opcode) {
4087 switch (Opcode) {
4088 case VPMAXUDYrm:
4089 case VPMAXUDYrr:
4090 case VPMAXUDZ128rm:
4091 case VPMAXUDZ128rmb:
4092 case VPMAXUDZ128rmbk:
4093 case VPMAXUDZ128rmbkz:
4094 case VPMAXUDZ128rmk:
4095 case VPMAXUDZ128rmkz:
4096 case VPMAXUDZ128rr:
4097 case VPMAXUDZ128rrk:
4098 case VPMAXUDZ128rrkz:
4099 case VPMAXUDZ256rm:
4100 case VPMAXUDZ256rmb:
4101 case VPMAXUDZ256rmbk:
4102 case VPMAXUDZ256rmbkz:
4103 case VPMAXUDZ256rmk:
4104 case VPMAXUDZ256rmkz:
4105 case VPMAXUDZ256rr:
4106 case VPMAXUDZ256rrk:
4107 case VPMAXUDZ256rrkz:
4108 case VPMAXUDZrm:
4109 case VPMAXUDZrmb:
4110 case VPMAXUDZrmbk:
4111 case VPMAXUDZrmbkz:
4112 case VPMAXUDZrmk:
4113 case VPMAXUDZrmkz:
4114 case VPMAXUDZrr:
4115 case VPMAXUDZrrk:
4116 case VPMAXUDZrrkz:
4117 case VPMAXUDrm:
4118 case VPMAXUDrr:
4119 return true;
4120 }
4121 return false;
4122}
4123
4124bool isVPMOVSQW(unsigned Opcode) {
4125 switch (Opcode) {
4126 case VPMOVSQWZ128mr:
4127 case VPMOVSQWZ128mrk:
4128 case VPMOVSQWZ128rr:
4129 case VPMOVSQWZ128rrk:
4130 case VPMOVSQWZ128rrkz:
4131 case VPMOVSQWZ256mr:
4132 case VPMOVSQWZ256mrk:
4133 case VPMOVSQWZ256rr:
4134 case VPMOVSQWZ256rrk:
4135 case VPMOVSQWZ256rrkz:
4136 case VPMOVSQWZmr:
4137 case VPMOVSQWZmrk:
4138 case VPMOVSQWZrr:
4139 case VPMOVSQWZrrk:
4140 case VPMOVSQWZrrkz:
4141 return true;
4142 }
4143 return false;
4144}
4145
4146bool isADDSUBPS(unsigned Opcode) {
4147 switch (Opcode) {
4148 case ADDSUBPSrm:
4149 case ADDSUBPSrr:
4150 return true;
4151 }
4152 return false;
4153}
4154
4155bool isVPMACSSDQL(unsigned Opcode) {
4156 switch (Opcode) {
4157 case VPMACSSDQLrm:
4158 case VPMACSSDQLrr:
4159 return true;
4160 }
4161 return false;
4162}
4163
4164bool isPXOR(unsigned Opcode) {
4165 switch (Opcode) {
4166 case MMX_PXORrm:
4167 case MMX_PXORrr:
4168 case PXORrm:
4169 case PXORrr:
4170 return true;
4171 }
4172 return false;
4173}
4174
4175bool isVPSRAD(unsigned Opcode) {
4176 switch (Opcode) {
4177 case VPSRADYri:
4178 case VPSRADYrm:
4179 case VPSRADYrr:
4180 case VPSRADZ128mbi:
4181 case VPSRADZ128mbik:
4182 case VPSRADZ128mbikz:
4183 case VPSRADZ128mi:
4184 case VPSRADZ128mik:
4185 case VPSRADZ128mikz:
4186 case VPSRADZ128ri:
4187 case VPSRADZ128rik:
4188 case VPSRADZ128rikz:
4189 case VPSRADZ128rm:
4190 case VPSRADZ128rmk:
4191 case VPSRADZ128rmkz:
4192 case VPSRADZ128rr:
4193 case VPSRADZ128rrk:
4194 case VPSRADZ128rrkz:
4195 case VPSRADZ256mbi:
4196 case VPSRADZ256mbik:
4197 case VPSRADZ256mbikz:
4198 case VPSRADZ256mi:
4199 case VPSRADZ256mik:
4200 case VPSRADZ256mikz:
4201 case VPSRADZ256ri:
4202 case VPSRADZ256rik:
4203 case VPSRADZ256rikz:
4204 case VPSRADZ256rm:
4205 case VPSRADZ256rmk:
4206 case VPSRADZ256rmkz:
4207 case VPSRADZ256rr:
4208 case VPSRADZ256rrk:
4209 case VPSRADZ256rrkz:
4210 case VPSRADZmbi:
4211 case VPSRADZmbik:
4212 case VPSRADZmbikz:
4213 case VPSRADZmi:
4214 case VPSRADZmik:
4215 case VPSRADZmikz:
4216 case VPSRADZri:
4217 case VPSRADZrik:
4218 case VPSRADZrikz:
4219 case VPSRADZrm:
4220 case VPSRADZrmk:
4221 case VPSRADZrmkz:
4222 case VPSRADZrr:
4223 case VPSRADZrrk:
4224 case VPSRADZrrkz:
4225 case VPSRADri:
4226 case VPSRADrm:
4227 case VPSRADrr:
4228 return true;
4229 }
4230 return false;
4231}
4232
4233bool isVPSHAB(unsigned Opcode) {
4234 switch (Opcode) {
4235 case VPSHABmr:
4236 case VPSHABrm:
4237 case VPSHABrr:
4238 case VPSHABrr_REV:
4239 return true;
4240 }
4241 return false;
4242}
4243
4244bool isBTR(unsigned Opcode) {
4245 switch (Opcode) {
4246 case BTR16mi8:
4247 case BTR16mr:
4248 case BTR16ri8:
4249 case BTR16rr:
4250 case BTR32mi8:
4251 case BTR32mr:
4252 case BTR32ri8:
4253 case BTR32rr:
4254 case BTR64mi8:
4255 case BTR64mr:
4256 case BTR64ri8:
4257 case BTR64rr:
4258 return true;
4259 }
4260 return false;
4261}
4262
4263bool isKORW(unsigned Opcode) {
4264 return Opcode == KORWkk;
4265}
4266
4267bool isVRANGESS(unsigned Opcode) {
4268 switch (Opcode) {
4269 case VRANGESSZrmi:
4270 case VRANGESSZrmik:
4271 case VRANGESSZrmikz:
4272 case VRANGESSZrri:
4273 case VRANGESSZrrib:
4274 case VRANGESSZrribk:
4275 case VRANGESSZrribkz:
4276 case VRANGESSZrrik:
4277 case VRANGESSZrrikz:
4278 return true;
4279 }
4280 return false;
4281}
4282
4283bool isVCMPPS(unsigned Opcode) {
4284 switch (Opcode) {
4285 case VCMPPSYrmi:
4286 case VCMPPSYrri:
4287 case VCMPPSZ128rmbi:
4288 case VCMPPSZ128rmbik:
4289 case VCMPPSZ128rmi:
4290 case VCMPPSZ128rmik:
4291 case VCMPPSZ128rri:
4292 case VCMPPSZ128rrik:
4293 case VCMPPSZ256rmbi:
4294 case VCMPPSZ256rmbik:
4295 case VCMPPSZ256rmi:
4296 case VCMPPSZ256rmik:
4297 case VCMPPSZ256rri:
4298 case VCMPPSZ256rrik:
4299 case VCMPPSZrmbi:
4300 case VCMPPSZrmbik:
4301 case VCMPPSZrmi:
4302 case VCMPPSZrmik:
4303 case VCMPPSZrri:
4304 case VCMPPSZrrib:
4305 case VCMPPSZrribk:
4306 case VCMPPSZrrik:
4307 case VCMPPSrmi:
4308 case VCMPPSrri:
4309 return true;
4310 }
4311 return false;
4312}
4313
4314bool isVPLZCNTD(unsigned Opcode) {
4315 switch (Opcode) {
4316 case VPLZCNTDZ128rm:
4317 case VPLZCNTDZ128rmb:
4318 case VPLZCNTDZ128rmbk:
4319 case VPLZCNTDZ128rmbkz:
4320 case VPLZCNTDZ128rmk:
4321 case VPLZCNTDZ128rmkz:
4322 case VPLZCNTDZ128rr:
4323 case VPLZCNTDZ128rrk:
4324 case VPLZCNTDZ128rrkz:
4325 case VPLZCNTDZ256rm:
4326 case VPLZCNTDZ256rmb:
4327 case VPLZCNTDZ256rmbk:
4328 case VPLZCNTDZ256rmbkz:
4329 case VPLZCNTDZ256rmk:
4330 case VPLZCNTDZ256rmkz:
4331 case VPLZCNTDZ256rr:
4332 case VPLZCNTDZ256rrk:
4333 case VPLZCNTDZ256rrkz:
4334 case VPLZCNTDZrm:
4335 case VPLZCNTDZrmb:
4336 case VPLZCNTDZrmbk:
4337 case VPLZCNTDZrmbkz:
4338 case VPLZCNTDZrmk:
4339 case VPLZCNTDZrmkz:
4340 case VPLZCNTDZrr:
4341 case VPLZCNTDZrrk:
4342 case VPLZCNTDZrrkz:
4343 return true;
4344 }
4345 return false;
4346}
4347
4348bool isTDPBUUD(unsigned Opcode) {
4349 return Opcode == TDPBUUD;
4350}
4351
4352bool isROUNDPS(unsigned Opcode) {
4353 switch (Opcode) {
4354 case ROUNDPSmi:
4355 case ROUNDPSri:
4356 return true;
4357 }
4358 return false;
4359}
4360
4361bool isFABS(unsigned Opcode) {
4362 return Opcode == ABS_F;
4363}
4364
4365bool isSUBPD(unsigned Opcode) {
4366 switch (Opcode) {
4367 case SUBPDrm:
4368 case SUBPDrr:
4369 return true;
4370 }
4371 return false;
4372}
4373
4374bool isGF2P8MULB(unsigned Opcode) {
4375 switch (Opcode) {
4376 case GF2P8MULBrm:
4377 case GF2P8MULBrr:
4378 return true;
4379 }
4380 return false;
4381}
4382
4383bool isTZMSK(unsigned Opcode) {
4384 switch (Opcode) {
4385 case TZMSK32rm:
4386 case TZMSK32rr:
4387 case TZMSK64rm:
4388 case TZMSK64rr:
4389 return true;
4390 }
4391 return false;
4392}
4393
4394bool isVMINMAXSD(unsigned Opcode) {
4395 switch (Opcode) {
4396 case VMINMAXSDrmi_Int:
4397 case VMINMAXSDrmik_Int:
4398 case VMINMAXSDrmikz_Int:
4399 case VMINMAXSDrri_Int:
4400 case VMINMAXSDrrib_Int:
4401 case VMINMAXSDrribk_Int:
4402 case VMINMAXSDrribkz_Int:
4403 case VMINMAXSDrrik_Int:
4404 case VMINMAXSDrrikz_Int:
4405 return true;
4406 }
4407 return false;
4408}
4409
4410bool isANDPS(unsigned Opcode) {
4411 switch (Opcode) {
4412 case ANDPSrm:
4413 case ANDPSrr:
4414 return true;
4415 }
4416 return false;
4417}
4418
4419bool isVEXTRACTF32X8(unsigned Opcode) {
4420 switch (Opcode) {
4421 case VEXTRACTF32X8Zmri:
4422 case VEXTRACTF32X8Zmrik:
4423 case VEXTRACTF32X8Zrri:
4424 case VEXTRACTF32X8Zrrik:
4425 case VEXTRACTF32X8Zrrikz:
4426 return true;
4427 }
4428 return false;
4429}
4430
4431bool isSEAMRET(unsigned Opcode) {
4432 return Opcode == SEAMRET;
4433}
4434
4435bool isVPCOMW(unsigned Opcode) {
4436 switch (Opcode) {
4437 case VPCOMWmi:
4438 case VPCOMWri:
4439 return true;
4440 }
4441 return false;
4442}
4443
4444bool isVFIXUPIMMPD(unsigned Opcode) {
4445 switch (Opcode) {
4446 case VFIXUPIMMPDZ128rmbi:
4447 case VFIXUPIMMPDZ128rmbik:
4448 case VFIXUPIMMPDZ128rmbikz:
4449 case VFIXUPIMMPDZ128rmi:
4450 case VFIXUPIMMPDZ128rmik:
4451 case VFIXUPIMMPDZ128rmikz:
4452 case VFIXUPIMMPDZ128rri:
4453 case VFIXUPIMMPDZ128rrik:
4454 case VFIXUPIMMPDZ128rrikz:
4455 case VFIXUPIMMPDZ256rmbi:
4456 case VFIXUPIMMPDZ256rmbik:
4457 case VFIXUPIMMPDZ256rmbikz:
4458 case VFIXUPIMMPDZ256rmi:
4459 case VFIXUPIMMPDZ256rmik:
4460 case VFIXUPIMMPDZ256rmikz:
4461 case VFIXUPIMMPDZ256rri:
4462 case VFIXUPIMMPDZ256rrik:
4463 case VFIXUPIMMPDZ256rrikz:
4464 case VFIXUPIMMPDZrmbi:
4465 case VFIXUPIMMPDZrmbik:
4466 case VFIXUPIMMPDZrmbikz:
4467 case VFIXUPIMMPDZrmi:
4468 case VFIXUPIMMPDZrmik:
4469 case VFIXUPIMMPDZrmikz:
4470 case VFIXUPIMMPDZrri:
4471 case VFIXUPIMMPDZrrib:
4472 case VFIXUPIMMPDZrribk:
4473 case VFIXUPIMMPDZrribkz:
4474 case VFIXUPIMMPDZrrik:
4475 case VFIXUPIMMPDZrrikz:
4476 return true;
4477 }
4478 return false;
4479}
4480
4481bool isKANDND(unsigned Opcode) {
4482 return Opcode == KANDNDkk;
4483}
4484
4485bool isVMRESUME(unsigned Opcode) {
4486 return Opcode == VMRESUME;
4487}
4488
4489bool isCVTPD2DQ(unsigned Opcode) {
4490 switch (Opcode) {
4491 case CVTPD2DQrm:
4492 case CVTPD2DQrr:
4493 return true;
4494 }
4495 return false;
4496}
4497
4498bool isVFNMADD213PS(unsigned Opcode) {
4499 switch (Opcode) {
4500 case VFNMADD213PSYm:
4501 case VFNMADD213PSYr:
4502 case VFNMADD213PSZ128m:
4503 case VFNMADD213PSZ128mb:
4504 case VFNMADD213PSZ128mbk:
4505 case VFNMADD213PSZ128mbkz:
4506 case VFNMADD213PSZ128mk:
4507 case VFNMADD213PSZ128mkz:
4508 case VFNMADD213PSZ128r:
4509 case VFNMADD213PSZ128rk:
4510 case VFNMADD213PSZ128rkz:
4511 case VFNMADD213PSZ256m:
4512 case VFNMADD213PSZ256mb:
4513 case VFNMADD213PSZ256mbk:
4514 case VFNMADD213PSZ256mbkz:
4515 case VFNMADD213PSZ256mk:
4516 case VFNMADD213PSZ256mkz:
4517 case VFNMADD213PSZ256r:
4518 case VFNMADD213PSZ256rk:
4519 case VFNMADD213PSZ256rkz:
4520 case VFNMADD213PSZm:
4521 case VFNMADD213PSZmb:
4522 case VFNMADD213PSZmbk:
4523 case VFNMADD213PSZmbkz:
4524 case VFNMADD213PSZmk:
4525 case VFNMADD213PSZmkz:
4526 case VFNMADD213PSZr:
4527 case VFNMADD213PSZrb:
4528 case VFNMADD213PSZrbk:
4529 case VFNMADD213PSZrbkz:
4530 case VFNMADD213PSZrk:
4531 case VFNMADD213PSZrkz:
4532 case VFNMADD213PSm:
4533 case VFNMADD213PSr:
4534 return true;
4535 }
4536 return false;
4537}
4538
4539bool isVPEXTRD(unsigned Opcode) {
4540 switch (Opcode) {
4541 case VPEXTRDZmri:
4542 case VPEXTRDZrri:
4543 case VPEXTRDmri:
4544 case VPEXTRDrri:
4545 return true;
4546 }
4547 return false;
4548}
4549
4550bool isPACKUSWB(unsigned Opcode) {
4551 switch (Opcode) {
4552 case MMX_PACKUSWBrm:
4553 case MMX_PACKUSWBrr:
4554 case PACKUSWBrm:
4555 case PACKUSWBrr:
4556 return true;
4557 }
4558 return false;
4559}
4560
4561bool isVEXTRACTI32X8(unsigned Opcode) {
4562 switch (Opcode) {
4563 case VEXTRACTI32X8Zmri:
4564 case VEXTRACTI32X8Zmrik:
4565 case VEXTRACTI32X8Zrri:
4566 case VEXTRACTI32X8Zrrik:
4567 case VEXTRACTI32X8Zrrikz:
4568 return true;
4569 }
4570 return false;
4571}
4572
4573bool isVHADDPD(unsigned Opcode) {
4574 switch (Opcode) {
4575 case VHADDPDYrm:
4576 case VHADDPDYrr:
4577 case VHADDPDrm:
4578 case VHADDPDrr:
4579 return true;
4580 }
4581 return false;
4582}
4583
4584bool isVPSADBW(unsigned Opcode) {
4585 switch (Opcode) {
4586 case VPSADBWYrm:
4587 case VPSADBWYrr:
4588 case VPSADBWZ128rm:
4589 case VPSADBWZ128rr:
4590 case VPSADBWZ256rm:
4591 case VPSADBWZ256rr:
4592 case VPSADBWZrm:
4593 case VPSADBWZrr:
4594 case VPSADBWrm:
4595 case VPSADBWrr:
4596 return true;
4597 }
4598 return false;
4599}
4600
4601bool isMOVDQ2Q(unsigned Opcode) {
4602 return Opcode == MMX_MOVDQ2Qrr;
4603}
4604
4605bool isPUNPCKHBW(unsigned Opcode) {
4606 switch (Opcode) {
4607 case MMX_PUNPCKHBWrm:
4608 case MMX_PUNPCKHBWrr:
4609 case PUNPCKHBWrm:
4610 case PUNPCKHBWrr:
4611 return true;
4612 }
4613 return false;
4614}
4615
4616bool isXOR(unsigned Opcode) {
4617 switch (Opcode) {
4618 case XOR16i16:
4619 case XOR16mi:
4620 case XOR16mi8:
4621 case XOR16mi8_EVEX:
4622 case XOR16mi8_ND:
4623 case XOR16mi8_NF:
4624 case XOR16mi8_NF_ND:
4625 case XOR16mi_EVEX:
4626 case XOR16mi_ND:
4627 case XOR16mi_NF:
4628 case XOR16mi_NF_ND:
4629 case XOR16mr:
4630 case XOR16mr_EVEX:
4631 case XOR16mr_ND:
4632 case XOR16mr_NF:
4633 case XOR16mr_NF_ND:
4634 case XOR16ri:
4635 case XOR16ri8:
4636 case XOR16ri8_EVEX:
4637 case XOR16ri8_ND:
4638 case XOR16ri8_NF:
4639 case XOR16ri8_NF_ND:
4640 case XOR16ri_EVEX:
4641 case XOR16ri_ND:
4642 case XOR16ri_NF:
4643 case XOR16ri_NF_ND:
4644 case XOR16rm:
4645 case XOR16rm_EVEX:
4646 case XOR16rm_ND:
4647 case XOR16rm_NF:
4648 case XOR16rm_NF_ND:
4649 case XOR16rr:
4650 case XOR16rr_EVEX:
4651 case XOR16rr_EVEX_REV:
4652 case XOR16rr_ND:
4653 case XOR16rr_ND_REV:
4654 case XOR16rr_NF:
4655 case XOR16rr_NF_ND:
4656 case XOR16rr_NF_ND_REV:
4657 case XOR16rr_NF_REV:
4658 case XOR16rr_REV:
4659 case XOR32i32:
4660 case XOR32mi:
4661 case XOR32mi8:
4662 case XOR32mi8_EVEX:
4663 case XOR32mi8_ND:
4664 case XOR32mi8_NF:
4665 case XOR32mi8_NF_ND:
4666 case XOR32mi_EVEX:
4667 case XOR32mi_ND:
4668 case XOR32mi_NF:
4669 case XOR32mi_NF_ND:
4670 case XOR32mr:
4671 case XOR32mr_EVEX:
4672 case XOR32mr_ND:
4673 case XOR32mr_NF:
4674 case XOR32mr_NF_ND:
4675 case XOR32ri:
4676 case XOR32ri8:
4677 case XOR32ri8_EVEX:
4678 case XOR32ri8_ND:
4679 case XOR32ri8_NF:
4680 case XOR32ri8_NF_ND:
4681 case XOR32ri_EVEX:
4682 case XOR32ri_ND:
4683 case XOR32ri_NF:
4684 case XOR32ri_NF_ND:
4685 case XOR32rm:
4686 case XOR32rm_EVEX:
4687 case XOR32rm_ND:
4688 case XOR32rm_NF:
4689 case XOR32rm_NF_ND:
4690 case XOR32rr:
4691 case XOR32rr_EVEX:
4692 case XOR32rr_EVEX_REV:
4693 case XOR32rr_ND:
4694 case XOR32rr_ND_REV:
4695 case XOR32rr_NF:
4696 case XOR32rr_NF_ND:
4697 case XOR32rr_NF_ND_REV:
4698 case XOR32rr_NF_REV:
4699 case XOR32rr_REV:
4700 case XOR64i32:
4701 case XOR64mi32:
4702 case XOR64mi32_EVEX:
4703 case XOR64mi32_ND:
4704 case XOR64mi32_NF:
4705 case XOR64mi32_NF_ND:
4706 case XOR64mi8:
4707 case XOR64mi8_EVEX:
4708 case XOR64mi8_ND:
4709 case XOR64mi8_NF:
4710 case XOR64mi8_NF_ND:
4711 case XOR64mr:
4712 case XOR64mr_EVEX:
4713 case XOR64mr_ND:
4714 case XOR64mr_NF:
4715 case XOR64mr_NF_ND:
4716 case XOR64ri32:
4717 case XOR64ri32_EVEX:
4718 case XOR64ri32_ND:
4719 case XOR64ri32_NF:
4720 case XOR64ri32_NF_ND:
4721 case XOR64ri8:
4722 case XOR64ri8_EVEX:
4723 case XOR64ri8_ND:
4724 case XOR64ri8_NF:
4725 case XOR64ri8_NF_ND:
4726 case XOR64rm:
4727 case XOR64rm_EVEX:
4728 case XOR64rm_ND:
4729 case XOR64rm_NF:
4730 case XOR64rm_NF_ND:
4731 case XOR64rr:
4732 case XOR64rr_EVEX:
4733 case XOR64rr_EVEX_REV:
4734 case XOR64rr_ND:
4735 case XOR64rr_ND_REV:
4736 case XOR64rr_NF:
4737 case XOR64rr_NF_ND:
4738 case XOR64rr_NF_ND_REV:
4739 case XOR64rr_NF_REV:
4740 case XOR64rr_REV:
4741 case XOR8i8:
4742 case XOR8mi:
4743 case XOR8mi8:
4744 case XOR8mi_EVEX:
4745 case XOR8mi_ND:
4746 case XOR8mi_NF:
4747 case XOR8mi_NF_ND:
4748 case XOR8mr:
4749 case XOR8mr_EVEX:
4750 case XOR8mr_ND:
4751 case XOR8mr_NF:
4752 case XOR8mr_NF_ND:
4753 case XOR8ri:
4754 case XOR8ri8:
4755 case XOR8ri_EVEX:
4756 case XOR8ri_ND:
4757 case XOR8ri_NF:
4758 case XOR8ri_NF_ND:
4759 case XOR8rm:
4760 case XOR8rm_EVEX:
4761 case XOR8rm_ND:
4762 case XOR8rm_NF:
4763 case XOR8rm_NF_ND:
4764 case XOR8rr:
4765 case XOR8rr_EVEX:
4766 case XOR8rr_EVEX_REV:
4767 case XOR8rr_ND:
4768 case XOR8rr_ND_REV:
4769 case XOR8rr_NF:
4770 case XOR8rr_NF_ND:
4771 case XOR8rr_NF_ND_REV:
4772 case XOR8rr_NF_REV:
4773 case XOR8rr_REV:
4774 return true;
4775 }
4776 return false;
4777}
4778
4779bool isPSIGNB(unsigned Opcode) {
4780 switch (Opcode) {
4781 case MMX_PSIGNBrm:
4782 case MMX_PSIGNBrr:
4783 case PSIGNBrm:
4784 case PSIGNBrr:
4785 return true;
4786 }
4787 return false;
4788}
4789
4790bool isVPHADDSW(unsigned Opcode) {
4791 switch (Opcode) {
4792 case VPHADDSWYrm:
4793 case VPHADDSWYrr:
4794 case VPHADDSWrm:
4795 case VPHADDSWrr:
4796 return true;
4797 }
4798 return false;
4799}
4800
4801bool isFADDP(unsigned Opcode) {
4802 return Opcode == ADD_FPrST0;
4803}
4804
4805bool isNEG(unsigned Opcode) {
4806 switch (Opcode) {
4807 case NEG16m:
4808 case NEG16m_EVEX:
4809 case NEG16m_ND:
4810 case NEG16m_NF:
4811 case NEG16m_NF_ND:
4812 case NEG16r:
4813 case NEG16r_EVEX:
4814 case NEG16r_ND:
4815 case NEG16r_NF:
4816 case NEG16r_NF_ND:
4817 case NEG32m:
4818 case NEG32m_EVEX:
4819 case NEG32m_ND:
4820 case NEG32m_NF:
4821 case NEG32m_NF_ND:
4822 case NEG32r:
4823 case NEG32r_EVEX:
4824 case NEG32r_ND:
4825 case NEG32r_NF:
4826 case NEG32r_NF_ND:
4827 case NEG64m:
4828 case NEG64m_EVEX:
4829 case NEG64m_ND:
4830 case NEG64m_NF:
4831 case NEG64m_NF_ND:
4832 case NEG64r:
4833 case NEG64r_EVEX:
4834 case NEG64r_ND:
4835 case NEG64r_NF:
4836 case NEG64r_NF_ND:
4837 case NEG8m:
4838 case NEG8m_EVEX:
4839 case NEG8m_ND:
4840 case NEG8m_NF:
4841 case NEG8m_NF_ND:
4842 case NEG8r:
4843 case NEG8r_EVEX:
4844 case NEG8r_ND:
4845 case NEG8r_NF:
4846 case NEG8r_NF_ND:
4847 return true;
4848 }
4849 return false;
4850}
4851
4852bool isFLDLG2(unsigned Opcode) {
4853 return Opcode == FLDLG2;
4854}
4855
4856bool isFNOP(unsigned Opcode) {
4857 return Opcode == FNOP;
4858}
4859
4860bool isVMINSS(unsigned Opcode) {
4861 switch (Opcode) {
4862 case VMINSSZrm_Int:
4863 case VMINSSZrmk_Int:
4864 case VMINSSZrmkz_Int:
4865 case VMINSSZrr_Int:
4866 case VMINSSZrrb_Int:
4867 case VMINSSZrrbk_Int:
4868 case VMINSSZrrbkz_Int:
4869 case VMINSSZrrk_Int:
4870 case VMINSSZrrkz_Int:
4871 case VMINSSrm_Int:
4872 case VMINSSrr_Int:
4873 return true;
4874 }
4875 return false;
4876}
4877
4878bool isPCMPISTRM(unsigned Opcode) {
4879 switch (Opcode) {
4880 case PCMPISTRMrmi:
4881 case PCMPISTRMrri:
4882 return true;
4883 }
4884 return false;
4885}
4886
4887bool isVFMADD132SS(unsigned Opcode) {
4888 switch (Opcode) {
4889 case VFMADD132SSZm_Int:
4890 case VFMADD132SSZmk_Int:
4891 case VFMADD132SSZmkz_Int:
4892 case VFMADD132SSZr_Int:
4893 case VFMADD132SSZrb_Int:
4894 case VFMADD132SSZrbk_Int:
4895 case VFMADD132SSZrbkz_Int:
4896 case VFMADD132SSZrk_Int:
4897 case VFMADD132SSZrkz_Int:
4898 case VFMADD132SSm_Int:
4899 case VFMADD132SSr_Int:
4900 return true;
4901 }
4902 return false;
4903}
4904
4905bool isFDIVRP(unsigned Opcode) {
4906 return Opcode == DIVR_FPrST0;
4907}
4908
4909bool isPUSHAL(unsigned Opcode) {
4910 return Opcode == PUSHA32;
4911}
4912
4913bool isVPMACSDQL(unsigned Opcode) {
4914 switch (Opcode) {
4915 case VPMACSDQLrm:
4916 case VPMACSDQLrr:
4917 return true;
4918 }
4919 return false;
4920}
4921
4922bool isSUBSD(unsigned Opcode) {
4923 switch (Opcode) {
4924 case SUBSDrm_Int:
4925 case SUBSDrr_Int:
4926 return true;
4927 }
4928 return false;
4929}
4930
4931bool isVPBLENDMQ(unsigned Opcode) {
4932 switch (Opcode) {
4933 case VPBLENDMQZ128rm:
4934 case VPBLENDMQZ128rmb:
4935 case VPBLENDMQZ128rmbk:
4936 case VPBLENDMQZ128rmbkz:
4937 case VPBLENDMQZ128rmk:
4938 case VPBLENDMQZ128rmkz:
4939 case VPBLENDMQZ128rr:
4940 case VPBLENDMQZ128rrk:
4941 case VPBLENDMQZ128rrkz:
4942 case VPBLENDMQZ256rm:
4943 case VPBLENDMQZ256rmb:
4944 case VPBLENDMQZ256rmbk:
4945 case VPBLENDMQZ256rmbkz:
4946 case VPBLENDMQZ256rmk:
4947 case VPBLENDMQZ256rmkz:
4948 case VPBLENDMQZ256rr:
4949 case VPBLENDMQZ256rrk:
4950 case VPBLENDMQZ256rrkz:
4951 case VPBLENDMQZrm:
4952 case VPBLENDMQZrmb:
4953 case VPBLENDMQZrmbk:
4954 case VPBLENDMQZrmbkz:
4955 case VPBLENDMQZrmk:
4956 case VPBLENDMQZrmkz:
4957 case VPBLENDMQZrr:
4958 case VPBLENDMQZrrk:
4959 case VPBLENDMQZrrkz:
4960 return true;
4961 }
4962 return false;
4963}
4964
4965bool isVGATHERDPS(unsigned Opcode) {
4966 switch (Opcode) {
4967 case VGATHERDPSYrm:
4968 case VGATHERDPSZ128rm:
4969 case VGATHERDPSZ256rm:
4970 case VGATHERDPSZrm:
4971 case VGATHERDPSrm:
4972 return true;
4973 }
4974 return false;
4975}
4976
4977bool isSYSRET(unsigned Opcode) {
4978 return Opcode == SYSRET;
4979}
4980
4981bool isVPADDB(unsigned Opcode) {
4982 switch (Opcode) {
4983 case VPADDBYrm:
4984 case VPADDBYrr:
4985 case VPADDBZ128rm:
4986 case VPADDBZ128rmk:
4987 case VPADDBZ128rmkz:
4988 case VPADDBZ128rr:
4989 case VPADDBZ128rrk:
4990 case VPADDBZ128rrkz:
4991 case VPADDBZ256rm:
4992 case VPADDBZ256rmk:
4993 case VPADDBZ256rmkz:
4994 case VPADDBZ256rr:
4995 case VPADDBZ256rrk:
4996 case VPADDBZ256rrkz:
4997 case VPADDBZrm:
4998 case VPADDBZrmk:
4999 case VPADDBZrmkz:
5000 case VPADDBZrr:
5001 case VPADDBZrrk:
5002 case VPADDBZrrkz:
5003 case VPADDBrm:
5004 case VPADDBrr:
5005 return true;
5006 }
5007 return false;
5008}
5009
5010bool isXEND(unsigned Opcode) {
5011 return Opcode == XEND;
5012}
5013
5014bool isWRSSD(unsigned Opcode) {
5015 switch (Opcode) {
5016 case WRSSD:
5017 case WRSSD_EVEX:
5018 return true;
5019 }
5020 return false;
5021}
5022
5023bool isVMINMAXSS(unsigned Opcode) {
5024 switch (Opcode) {
5025 case VMINMAXSSrmi_Int:
5026 case VMINMAXSSrmik_Int:
5027 case VMINMAXSSrmikz_Int:
5028 case VMINMAXSSrri_Int:
5029 case VMINMAXSSrrib_Int:
5030 case VMINMAXSSrribk_Int:
5031 case VMINMAXSSrribkz_Int:
5032 case VMINMAXSSrrik_Int:
5033 case VMINMAXSSrrikz_Int:
5034 return true;
5035 }
5036 return false;
5037}
5038
5039bool isVCVTDQ2PH(unsigned Opcode) {
5040 switch (Opcode) {
5041 case VCVTDQ2PHZ128rm:
5042 case VCVTDQ2PHZ128rmb:
5043 case VCVTDQ2PHZ128rmbk:
5044 case VCVTDQ2PHZ128rmbkz:
5045 case VCVTDQ2PHZ128rmk:
5046 case VCVTDQ2PHZ128rmkz:
5047 case VCVTDQ2PHZ128rr:
5048 case VCVTDQ2PHZ128rrk:
5049 case VCVTDQ2PHZ128rrkz:
5050 case VCVTDQ2PHZ256rm:
5051 case VCVTDQ2PHZ256rmb:
5052 case VCVTDQ2PHZ256rmbk:
5053 case VCVTDQ2PHZ256rmbkz:
5054 case VCVTDQ2PHZ256rmk:
5055 case VCVTDQ2PHZ256rmkz:
5056 case VCVTDQ2PHZ256rr:
5057 case VCVTDQ2PHZ256rrk:
5058 case VCVTDQ2PHZ256rrkz:
5059 case VCVTDQ2PHZrm:
5060 case VCVTDQ2PHZrmb:
5061 case VCVTDQ2PHZrmbk:
5062 case VCVTDQ2PHZrmbkz:
5063 case VCVTDQ2PHZrmk:
5064 case VCVTDQ2PHZrmkz:
5065 case VCVTDQ2PHZrr:
5066 case VCVTDQ2PHZrrb:
5067 case VCVTDQ2PHZrrbk:
5068 case VCVTDQ2PHZrrbkz:
5069 case VCVTDQ2PHZrrk:
5070 case VCVTDQ2PHZrrkz:
5071 return true;
5072 }
5073 return false;
5074}
5075
5076bool isCVTPD2PS(unsigned Opcode) {
5077 switch (Opcode) {
5078 case CVTPD2PSrm:
5079 case CVTPD2PSrr:
5080 return true;
5081 }
5082 return false;
5083}
5084
5085bool isMAXPD(unsigned Opcode) {
5086 switch (Opcode) {
5087 case MAXPDrm:
5088 case MAXPDrr:
5089 return true;
5090 }
5091 return false;
5092}
5093
5094bool isRCPSS(unsigned Opcode) {
5095 switch (Opcode) {
5096 case RCPSSm_Int:
5097 case RCPSSr_Int:
5098 return true;
5099 }
5100 return false;
5101}
5102
5103bool isVMOVAPD(unsigned Opcode) {
5104 switch (Opcode) {
5105 case VMOVAPDYmr:
5106 case VMOVAPDYrm:
5107 case VMOVAPDYrr:
5108 case VMOVAPDYrr_REV:
5109 case VMOVAPDZ128mr:
5110 case VMOVAPDZ128mrk:
5111 case VMOVAPDZ128rm:
5112 case VMOVAPDZ128rmk:
5113 case VMOVAPDZ128rmkz:
5114 case VMOVAPDZ128rr:
5115 case VMOVAPDZ128rr_REV:
5116 case VMOVAPDZ128rrk:
5117 case VMOVAPDZ128rrk_REV:
5118 case VMOVAPDZ128rrkz:
5119 case VMOVAPDZ128rrkz_REV:
5120 case VMOVAPDZ256mr:
5121 case VMOVAPDZ256mrk:
5122 case VMOVAPDZ256rm:
5123 case VMOVAPDZ256rmk:
5124 case VMOVAPDZ256rmkz:
5125 case VMOVAPDZ256rr:
5126 case VMOVAPDZ256rr_REV:
5127 case VMOVAPDZ256rrk:
5128 case VMOVAPDZ256rrk_REV:
5129 case VMOVAPDZ256rrkz:
5130 case VMOVAPDZ256rrkz_REV:
5131 case VMOVAPDZmr:
5132 case VMOVAPDZmrk:
5133 case VMOVAPDZrm:
5134 case VMOVAPDZrmk:
5135 case VMOVAPDZrmkz:
5136 case VMOVAPDZrr:
5137 case VMOVAPDZrr_REV:
5138 case VMOVAPDZrrk:
5139 case VMOVAPDZrrk_REV:
5140 case VMOVAPDZrrkz:
5141 case VMOVAPDZrrkz_REV:
5142 case VMOVAPDmr:
5143 case VMOVAPDrm:
5144 case VMOVAPDrr:
5145 case VMOVAPDrr_REV:
5146 return true;
5147 }
5148 return false;
5149}
5150
5151bool isVPSUBSB(unsigned Opcode) {
5152 switch (Opcode) {
5153 case VPSUBSBYrm:
5154 case VPSUBSBYrr:
5155 case VPSUBSBZ128rm:
5156 case VPSUBSBZ128rmk:
5157 case VPSUBSBZ128rmkz:
5158 case VPSUBSBZ128rr:
5159 case VPSUBSBZ128rrk:
5160 case VPSUBSBZ128rrkz:
5161 case VPSUBSBZ256rm:
5162 case VPSUBSBZ256rmk:
5163 case VPSUBSBZ256rmkz:
5164 case VPSUBSBZ256rr:
5165 case VPSUBSBZ256rrk:
5166 case VPSUBSBZ256rrkz:
5167 case VPSUBSBZrm:
5168 case VPSUBSBZrmk:
5169 case VPSUBSBZrmkz:
5170 case VPSUBSBZrr:
5171 case VPSUBSBZrrk:
5172 case VPSUBSBZrrkz:
5173 case VPSUBSBrm:
5174 case VPSUBSBrr:
5175 return true;
5176 }
5177 return false;
5178}
5179
5180bool isRDTSC(unsigned Opcode) {
5181 return Opcode == RDTSC;
5182}
5183
5184bool isVCVTTPS2UDQS(unsigned Opcode) {
5185 switch (Opcode) {
5186 case VCVTTPS2UDQSZ128rm:
5187 case VCVTTPS2UDQSZ128rmb:
5188 case VCVTTPS2UDQSZ128rmbk:
5189 case VCVTTPS2UDQSZ128rmbkz:
5190 case VCVTTPS2UDQSZ128rmk:
5191 case VCVTTPS2UDQSZ128rmkz:
5192 case VCVTTPS2UDQSZ128rr:
5193 case VCVTTPS2UDQSZ128rrk:
5194 case VCVTTPS2UDQSZ128rrkz:
5195 case VCVTTPS2UDQSZ256rm:
5196 case VCVTTPS2UDQSZ256rmb:
5197 case VCVTTPS2UDQSZ256rmbk:
5198 case VCVTTPS2UDQSZ256rmbkz:
5199 case VCVTTPS2UDQSZ256rmk:
5200 case VCVTTPS2UDQSZ256rmkz:
5201 case VCVTTPS2UDQSZ256rr:
5202 case VCVTTPS2UDQSZ256rrk:
5203 case VCVTTPS2UDQSZ256rrkz:
5204 case VCVTTPS2UDQSZrm:
5205 case VCVTTPS2UDQSZrmb:
5206 case VCVTTPS2UDQSZrmbk:
5207 case VCVTTPS2UDQSZrmbkz:
5208 case VCVTTPS2UDQSZrmk:
5209 case VCVTTPS2UDQSZrmkz:
5210 case VCVTTPS2UDQSZrr:
5211 case VCVTTPS2UDQSZrrb:
5212 case VCVTTPS2UDQSZrrbk:
5213 case VCVTTPS2UDQSZrrbkz:
5214 case VCVTTPS2UDQSZrrk:
5215 case VCVTTPS2UDQSZrrkz:
5216 return true;
5217 }
5218 return false;
5219}
5220
5221bool isVPMADCSSWD(unsigned Opcode) {
5222 switch (Opcode) {
5223 case VPMADCSSWDrm:
5224 case VPMADCSSWDrr:
5225 return true;
5226 }
5227 return false;
5228}
5229
5230bool isVFNMADD213PH(unsigned Opcode) {
5231 switch (Opcode) {
5232 case VFNMADD213PHZ128m:
5233 case VFNMADD213PHZ128mb:
5234 case VFNMADD213PHZ128mbk:
5235 case VFNMADD213PHZ128mbkz:
5236 case VFNMADD213PHZ128mk:
5237 case VFNMADD213PHZ128mkz:
5238 case VFNMADD213PHZ128r:
5239 case VFNMADD213PHZ128rk:
5240 case VFNMADD213PHZ128rkz:
5241 case VFNMADD213PHZ256m:
5242 case VFNMADD213PHZ256mb:
5243 case VFNMADD213PHZ256mbk:
5244 case VFNMADD213PHZ256mbkz:
5245 case VFNMADD213PHZ256mk:
5246 case VFNMADD213PHZ256mkz:
5247 case VFNMADD213PHZ256r:
5248 case VFNMADD213PHZ256rk:
5249 case VFNMADD213PHZ256rkz:
5250 case VFNMADD213PHZm:
5251 case VFNMADD213PHZmb:
5252 case VFNMADD213PHZmbk:
5253 case VFNMADD213PHZmbkz:
5254 case VFNMADD213PHZmk:
5255 case VFNMADD213PHZmkz:
5256 case VFNMADD213PHZr:
5257 case VFNMADD213PHZrb:
5258 case VFNMADD213PHZrbk:
5259 case VFNMADD213PHZrbkz:
5260 case VFNMADD213PHZrk:
5261 case VFNMADD213PHZrkz:
5262 return true;
5263 }
5264 return false;
5265}
5266
5267bool isVGF2P8AFFINEQB(unsigned Opcode) {
5268 switch (Opcode) {
5269 case VGF2P8AFFINEQBYrmi:
5270 case VGF2P8AFFINEQBYrri:
5271 case VGF2P8AFFINEQBZ128rmbi:
5272 case VGF2P8AFFINEQBZ128rmbik:
5273 case VGF2P8AFFINEQBZ128rmbikz:
5274 case VGF2P8AFFINEQBZ128rmi:
5275 case VGF2P8AFFINEQBZ128rmik:
5276 case VGF2P8AFFINEQBZ128rmikz:
5277 case VGF2P8AFFINEQBZ128rri:
5278 case VGF2P8AFFINEQBZ128rrik:
5279 case VGF2P8AFFINEQBZ128rrikz:
5280 case VGF2P8AFFINEQBZ256rmbi:
5281 case VGF2P8AFFINEQBZ256rmbik:
5282 case VGF2P8AFFINEQBZ256rmbikz:
5283 case VGF2P8AFFINEQBZ256rmi:
5284 case VGF2P8AFFINEQBZ256rmik:
5285 case VGF2P8AFFINEQBZ256rmikz:
5286 case VGF2P8AFFINEQBZ256rri:
5287 case VGF2P8AFFINEQBZ256rrik:
5288 case VGF2P8AFFINEQBZ256rrikz:
5289 case VGF2P8AFFINEQBZrmbi:
5290 case VGF2P8AFFINEQBZrmbik:
5291 case VGF2P8AFFINEQBZrmbikz:
5292 case VGF2P8AFFINEQBZrmi:
5293 case VGF2P8AFFINEQBZrmik:
5294 case VGF2P8AFFINEQBZrmikz:
5295 case VGF2P8AFFINEQBZrri:
5296 case VGF2P8AFFINEQBZrrik:
5297 case VGF2P8AFFINEQBZrrikz:
5298 case VGF2P8AFFINEQBrmi:
5299 case VGF2P8AFFINEQBrri:
5300 return true;
5301 }
5302 return false;
5303}
5304
5305bool isPMOVZXWD(unsigned Opcode) {
5306 switch (Opcode) {
5307 case PMOVZXWDrm:
5308 case PMOVZXWDrr:
5309 return true;
5310 }
5311 return false;
5312}
5313
5314bool isPMINUD(unsigned Opcode) {
5315 switch (Opcode) {
5316 case PMINUDrm:
5317 case PMINUDrr:
5318 return true;
5319 }
5320 return false;
5321}
5322
5323bool isVCVTPH2UW(unsigned Opcode) {
5324 switch (Opcode) {
5325 case VCVTPH2UWZ128rm:
5326 case VCVTPH2UWZ128rmb:
5327 case VCVTPH2UWZ128rmbk:
5328 case VCVTPH2UWZ128rmbkz:
5329 case VCVTPH2UWZ128rmk:
5330 case VCVTPH2UWZ128rmkz:
5331 case VCVTPH2UWZ128rr:
5332 case VCVTPH2UWZ128rrk:
5333 case VCVTPH2UWZ128rrkz:
5334 case VCVTPH2UWZ256rm:
5335 case VCVTPH2UWZ256rmb:
5336 case VCVTPH2UWZ256rmbk:
5337 case VCVTPH2UWZ256rmbkz:
5338 case VCVTPH2UWZ256rmk:
5339 case VCVTPH2UWZ256rmkz:
5340 case VCVTPH2UWZ256rr:
5341 case VCVTPH2UWZ256rrk:
5342 case VCVTPH2UWZ256rrkz:
5343 case VCVTPH2UWZrm:
5344 case VCVTPH2UWZrmb:
5345 case VCVTPH2UWZrmbk:
5346 case VCVTPH2UWZrmbkz:
5347 case VCVTPH2UWZrmk:
5348 case VCVTPH2UWZrmkz:
5349 case VCVTPH2UWZrr:
5350 case VCVTPH2UWZrrb:
5351 case VCVTPH2UWZrrbk:
5352 case VCVTPH2UWZrrbkz:
5353 case VCVTPH2UWZrrk:
5354 case VCVTPH2UWZrrkz:
5355 return true;
5356 }
5357 return false;
5358}
5359
5360bool isPADDSW(unsigned Opcode) {
5361 switch (Opcode) {
5362 case MMX_PADDSWrm:
5363 case MMX_PADDSWrr:
5364 case PADDSWrm:
5365 case PADDSWrr:
5366 return true;
5367 }
5368 return false;
5369}
5370
5371bool isXSUSLDTRK(unsigned Opcode) {
5372 return Opcode == XSUSLDTRK;
5373}
5374
5375bool isLFENCE(unsigned Opcode) {
5376 return Opcode == LFENCE;
5377}
5378
5379bool isCRC32(unsigned Opcode) {
5380 switch (Opcode) {
5381 case CRC32r32m16:
5382 case CRC32r32m16_EVEX:
5383 case CRC32r32m32:
5384 case CRC32r32m32_EVEX:
5385 case CRC32r32m8:
5386 case CRC32r32m8_EVEX:
5387 case CRC32r32r16:
5388 case CRC32r32r16_EVEX:
5389 case CRC32r32r32:
5390 case CRC32r32r32_EVEX:
5391 case CRC32r32r8:
5392 case CRC32r32r8_EVEX:
5393 case CRC32r64m64:
5394 case CRC32r64m64_EVEX:
5395 case CRC32r64m8:
5396 case CRC32r64m8_EVEX:
5397 case CRC32r64r64:
5398 case CRC32r64r64_EVEX:
5399 case CRC32r64r8:
5400 case CRC32r64r8_EVEX:
5401 return true;
5402 }
5403 return false;
5404}
5405
5406bool isAESENCWIDE256KL(unsigned Opcode) {
5407 return Opcode == AESENCWIDE256KL;
5408}
5409
5410bool isMOVAPD(unsigned Opcode) {
5411 switch (Opcode) {
5412 case MOVAPDmr:
5413 case MOVAPDrm:
5414 case MOVAPDrr:
5415 case MOVAPDrr_REV:
5416 return true;
5417 }
5418 return false;
5419}
5420
5421bool isVFMADD213PS(unsigned Opcode) {
5422 switch (Opcode) {
5423 case VFMADD213PSYm:
5424 case VFMADD213PSYr:
5425 case VFMADD213PSZ128m:
5426 case VFMADD213PSZ128mb:
5427 case VFMADD213PSZ128mbk:
5428 case VFMADD213PSZ128mbkz:
5429 case VFMADD213PSZ128mk:
5430 case VFMADD213PSZ128mkz:
5431 case VFMADD213PSZ128r:
5432 case VFMADD213PSZ128rk:
5433 case VFMADD213PSZ128rkz:
5434 case VFMADD213PSZ256m:
5435 case VFMADD213PSZ256mb:
5436 case VFMADD213PSZ256mbk:
5437 case VFMADD213PSZ256mbkz:
5438 case VFMADD213PSZ256mk:
5439 case VFMADD213PSZ256mkz:
5440 case VFMADD213PSZ256r:
5441 case VFMADD213PSZ256rk:
5442 case VFMADD213PSZ256rkz:
5443 case VFMADD213PSZm:
5444 case VFMADD213PSZmb:
5445 case VFMADD213PSZmbk:
5446 case VFMADD213PSZmbkz:
5447 case VFMADD213PSZmk:
5448 case VFMADD213PSZmkz:
5449 case VFMADD213PSZr:
5450 case VFMADD213PSZrb:
5451 case VFMADD213PSZrbk:
5452 case VFMADD213PSZrbkz:
5453 case VFMADD213PSZrk:
5454 case VFMADD213PSZrkz:
5455 case VFMADD213PSm:
5456 case VFMADD213PSr:
5457 return true;
5458 }
5459 return false;
5460}
5461
5462bool isVPDPWUUDS(unsigned Opcode) {
5463 switch (Opcode) {
5464 case VPDPWUUDSYrm:
5465 case VPDPWUUDSYrr:
5466 case VPDPWUUDSZ128rm:
5467 case VPDPWUUDSZ128rmb:
5468 case VPDPWUUDSZ128rmbk:
5469 case VPDPWUUDSZ128rmbkz:
5470 case VPDPWUUDSZ128rmk:
5471 case VPDPWUUDSZ128rmkz:
5472 case VPDPWUUDSZ128rr:
5473 case VPDPWUUDSZ128rrk:
5474 case VPDPWUUDSZ128rrkz:
5475 case VPDPWUUDSZ256rm:
5476 case VPDPWUUDSZ256rmb:
5477 case VPDPWUUDSZ256rmbk:
5478 case VPDPWUUDSZ256rmbkz:
5479 case VPDPWUUDSZ256rmk:
5480 case VPDPWUUDSZ256rmkz:
5481 case VPDPWUUDSZ256rr:
5482 case VPDPWUUDSZ256rrk:
5483 case VPDPWUUDSZ256rrkz:
5484 case VPDPWUUDSZrm:
5485 case VPDPWUUDSZrmb:
5486 case VPDPWUUDSZrmbk:
5487 case VPDPWUUDSZrmbkz:
5488 case VPDPWUUDSZrmk:
5489 case VPDPWUUDSZrmkz:
5490 case VPDPWUUDSZrr:
5491 case VPDPWUUDSZrrk:
5492 case VPDPWUUDSZrrkz:
5493 case VPDPWUUDSrm:
5494 case VPDPWUUDSrr:
5495 return true;
5496 }
5497 return false;
5498}
5499
5500bool isMOVSLDUP(unsigned Opcode) {
5501 switch (Opcode) {
5502 case MOVSLDUPrm:
5503 case MOVSLDUPrr:
5504 return true;
5505 }
5506 return false;
5507}
5508
5509bool isCLDEMOTE(unsigned Opcode) {
5510 return Opcode == CLDEMOTE;
5511}
5512
5513bool isVFNMADD231PS(unsigned Opcode) {
5514 switch (Opcode) {
5515 case VFNMADD231PSYm:
5516 case VFNMADD231PSYr:
5517 case VFNMADD231PSZ128m:
5518 case VFNMADD231PSZ128mb:
5519 case VFNMADD231PSZ128mbk:
5520 case VFNMADD231PSZ128mbkz:
5521 case VFNMADD231PSZ128mk:
5522 case VFNMADD231PSZ128mkz:
5523 case VFNMADD231PSZ128r:
5524 case VFNMADD231PSZ128rk:
5525 case VFNMADD231PSZ128rkz:
5526 case VFNMADD231PSZ256m:
5527 case VFNMADD231PSZ256mb:
5528 case VFNMADD231PSZ256mbk:
5529 case VFNMADD231PSZ256mbkz:
5530 case VFNMADD231PSZ256mk:
5531 case VFNMADD231PSZ256mkz:
5532 case VFNMADD231PSZ256r:
5533 case VFNMADD231PSZ256rk:
5534 case VFNMADD231PSZ256rkz:
5535 case VFNMADD231PSZm:
5536 case VFNMADD231PSZmb:
5537 case VFNMADD231PSZmbk:
5538 case VFNMADD231PSZmbkz:
5539 case VFNMADD231PSZmk:
5540 case VFNMADD231PSZmkz:
5541 case VFNMADD231PSZr:
5542 case VFNMADD231PSZrb:
5543 case VFNMADD231PSZrbk:
5544 case VFNMADD231PSZrbkz:
5545 case VFNMADD231PSZrk:
5546 case VFNMADD231PSZrkz:
5547 case VFNMADD231PSm:
5548 case VFNMADD231PSr:
5549 return true;
5550 }
5551 return false;
5552}
5553
5554bool isVMOVMSKPD(unsigned Opcode) {
5555 switch (Opcode) {
5556 case VMOVMSKPDYrr:
5557 case VMOVMSKPDrr:
5558 return true;
5559 }
5560 return false;
5561}
5562
5563bool isPREFETCHT0(unsigned Opcode) {
5564 return Opcode == PREFETCHT0;
5565}
5566
5567bool isVCVTNEOBF162PS(unsigned Opcode) {
5568 switch (Opcode) {
5569 case VCVTNEOBF162PSYrm:
5570 case VCVTNEOBF162PSrm:
5571 return true;
5572 }
5573 return false;
5574}
5575
5576bool isVPCMPUD(unsigned Opcode) {
5577 switch (Opcode) {
5578 case VPCMPUDZ128rmbi:
5579 case VPCMPUDZ128rmbik:
5580 case VPCMPUDZ128rmi:
5581 case VPCMPUDZ128rmik:
5582 case VPCMPUDZ128rri:
5583 case VPCMPUDZ128rrik:
5584 case VPCMPUDZ256rmbi:
5585 case VPCMPUDZ256rmbik:
5586 case VPCMPUDZ256rmi:
5587 case VPCMPUDZ256rmik:
5588 case VPCMPUDZ256rri:
5589 case VPCMPUDZ256rrik:
5590 case VPCMPUDZrmbi:
5591 case VPCMPUDZrmbik:
5592 case VPCMPUDZrmi:
5593 case VPCMPUDZrmik:
5594 case VPCMPUDZrri:
5595 case VPCMPUDZrrik:
5596 return true;
5597 }
5598 return false;
5599}
5600
5601bool isVMAXSD(unsigned Opcode) {
5602 switch (Opcode) {
5603 case VMAXSDZrm_Int:
5604 case VMAXSDZrmk_Int:
5605 case VMAXSDZrmkz_Int:
5606 case VMAXSDZrr_Int:
5607 case VMAXSDZrrb_Int:
5608 case VMAXSDZrrbk_Int:
5609 case VMAXSDZrrbkz_Int:
5610 case VMAXSDZrrk_Int:
5611 case VMAXSDZrrkz_Int:
5612 case VMAXSDrm_Int:
5613 case VMAXSDrr_Int:
5614 return true;
5615 }
5616 return false;
5617}
5618
5619bool isVRCP28SD(unsigned Opcode) {
5620 switch (Opcode) {
5621 case VRCP28SDZm:
5622 case VRCP28SDZmk:
5623 case VRCP28SDZmkz:
5624 case VRCP28SDZr:
5625 case VRCP28SDZrb:
5626 case VRCP28SDZrbk:
5627 case VRCP28SDZrbkz:
5628 case VRCP28SDZrk:
5629 case VRCP28SDZrkz:
5630 return true;
5631 }
5632 return false;
5633}
5634
5635bool isVMAXPS(unsigned Opcode) {
5636 switch (Opcode) {
5637 case VMAXPSYrm:
5638 case VMAXPSYrr:
5639 case VMAXPSZ128rm:
5640 case VMAXPSZ128rmb:
5641 case VMAXPSZ128rmbk:
5642 case VMAXPSZ128rmbkz:
5643 case VMAXPSZ128rmk:
5644 case VMAXPSZ128rmkz:
5645 case VMAXPSZ128rr:
5646 case VMAXPSZ128rrk:
5647 case VMAXPSZ128rrkz:
5648 case VMAXPSZ256rm:
5649 case VMAXPSZ256rmb:
5650 case VMAXPSZ256rmbk:
5651 case VMAXPSZ256rmbkz:
5652 case VMAXPSZ256rmk:
5653 case VMAXPSZ256rmkz:
5654 case VMAXPSZ256rr:
5655 case VMAXPSZ256rrk:
5656 case VMAXPSZ256rrkz:
5657 case VMAXPSZrm:
5658 case VMAXPSZrmb:
5659 case VMAXPSZrmbk:
5660 case VMAXPSZrmbkz:
5661 case VMAXPSZrmk:
5662 case VMAXPSZrmkz:
5663 case VMAXPSZrr:
5664 case VMAXPSZrrb:
5665 case VMAXPSZrrbk:
5666 case VMAXPSZrrbkz:
5667 case VMAXPSZrrk:
5668 case VMAXPSZrrkz:
5669 case VMAXPSrm:
5670 case VMAXPSrr:
5671 return true;
5672 }
5673 return false;
5674}
5675
5676bool isVPMOVD2M(unsigned Opcode) {
5677 switch (Opcode) {
5678 case VPMOVD2MZ128kr:
5679 case VPMOVD2MZ256kr:
5680 case VPMOVD2MZkr:
5681 return true;
5682 }
5683 return false;
5684}
5685
5686bool isVPMACSSWD(unsigned Opcode) {
5687 switch (Opcode) {
5688 case VPMACSSWDrm:
5689 case VPMACSSWDrr:
5690 return true;
5691 }
5692 return false;
5693}
5694
5695bool isVUCOMISD(unsigned Opcode) {
5696 switch (Opcode) {
5697 case VUCOMISDZrm:
5698 case VUCOMISDZrr:
5699 case VUCOMISDZrrb:
5700 case VUCOMISDrm:
5701 case VUCOMISDrr:
5702 return true;
5703 }
5704 return false;
5705}
5706
5707bool isLTR(unsigned Opcode) {
5708 switch (Opcode) {
5709 case LTRm:
5710 case LTRr:
5711 return true;
5712 }
5713 return false;
5714}
5715
5716bool isVCVTUSI2SH(unsigned Opcode) {
5717 switch (Opcode) {
5718 case VCVTUSI2SHZrm_Int:
5719 case VCVTUSI2SHZrr_Int:
5720 case VCVTUSI2SHZrrb_Int:
5721 case VCVTUSI642SHZrm_Int:
5722 case VCVTUSI642SHZrr_Int:
5723 case VCVTUSI642SHZrrb_Int:
5724 return true;
5725 }
5726 return false;
5727}
5728
5729bool isVSCATTERPF1QPS(unsigned Opcode) {
5730 return Opcode == VSCATTERPF1QPSm;
5731}
5732
5733bool isWRGSBASE(unsigned Opcode) {
5734 switch (Opcode) {
5735 case WRGSBASE:
5736 case WRGSBASE64:
5737 return true;
5738 }
5739 return false;
5740}
5741
5742bool isSTOSQ(unsigned Opcode) {
5743 return Opcode == STOSQ;
5744}
5745
5746bool isVSQRTSD(unsigned Opcode) {
5747 switch (Opcode) {
5748 case VSQRTSDZm_Int:
5749 case VSQRTSDZmk_Int:
5750 case VSQRTSDZmkz_Int:
5751 case VSQRTSDZr_Int:
5752 case VSQRTSDZrb_Int:
5753 case VSQRTSDZrbk_Int:
5754 case VSQRTSDZrbkz_Int:
5755 case VSQRTSDZrk_Int:
5756 case VSQRTSDZrkz_Int:
5757 case VSQRTSDm_Int:
5758 case VSQRTSDr_Int:
5759 return true;
5760 }
5761 return false;
5762}
5763
5764bool isVPERMIL2PD(unsigned Opcode) {
5765 switch (Opcode) {
5766 case VPERMIL2PDYmr:
5767 case VPERMIL2PDYrm:
5768 case VPERMIL2PDYrr:
5769 case VPERMIL2PDYrr_REV:
5770 case VPERMIL2PDmr:
5771 case VPERMIL2PDrm:
5772 case VPERMIL2PDrr:
5773 case VPERMIL2PDrr_REV:
5774 return true;
5775 }
5776 return false;
5777}
5778
5779bool isVFCMADDCSH(unsigned Opcode) {
5780 switch (Opcode) {
5781 case VFCMADDCSHZm:
5782 case VFCMADDCSHZmk:
5783 case VFCMADDCSHZmkz:
5784 case VFCMADDCSHZr:
5785 case VFCMADDCSHZrb:
5786 case VFCMADDCSHZrbk:
5787 case VFCMADDCSHZrbkz:
5788 case VFCMADDCSHZrk:
5789 case VFCMADDCSHZrkz:
5790 return true;
5791 }
5792 return false;
5793}
5794
5795bool isVFMADDSUB213PS(unsigned Opcode) {
5796 switch (Opcode) {
5797 case VFMADDSUB213PSYm:
5798 case VFMADDSUB213PSYr:
5799 case VFMADDSUB213PSZ128m:
5800 case VFMADDSUB213PSZ128mb:
5801 case VFMADDSUB213PSZ128mbk:
5802 case VFMADDSUB213PSZ128mbkz:
5803 case VFMADDSUB213PSZ128mk:
5804 case VFMADDSUB213PSZ128mkz:
5805 case VFMADDSUB213PSZ128r:
5806 case VFMADDSUB213PSZ128rk:
5807 case VFMADDSUB213PSZ128rkz:
5808 case VFMADDSUB213PSZ256m:
5809 case VFMADDSUB213PSZ256mb:
5810 case VFMADDSUB213PSZ256mbk:
5811 case VFMADDSUB213PSZ256mbkz:
5812 case VFMADDSUB213PSZ256mk:
5813 case VFMADDSUB213PSZ256mkz:
5814 case VFMADDSUB213PSZ256r:
5815 case VFMADDSUB213PSZ256rk:
5816 case VFMADDSUB213PSZ256rkz:
5817 case VFMADDSUB213PSZm:
5818 case VFMADDSUB213PSZmb:
5819 case VFMADDSUB213PSZmbk:
5820 case VFMADDSUB213PSZmbkz:
5821 case VFMADDSUB213PSZmk:
5822 case VFMADDSUB213PSZmkz:
5823 case VFMADDSUB213PSZr:
5824 case VFMADDSUB213PSZrb:
5825 case VFMADDSUB213PSZrbk:
5826 case VFMADDSUB213PSZrbkz:
5827 case VFMADDSUB213PSZrk:
5828 case VFMADDSUB213PSZrkz:
5829 case VFMADDSUB213PSm:
5830 case VFMADDSUB213PSr:
5831 return true;
5832 }
5833 return false;
5834}
5835
5836bool isPFSUB(unsigned Opcode) {
5837 switch (Opcode) {
5838 case PFSUBrm:
5839 case PFSUBrr:
5840 return true;
5841 }
5842 return false;
5843}
5844
5845bool isVSQRTSS(unsigned Opcode) {
5846 switch (Opcode) {
5847 case VSQRTSSZm_Int:
5848 case VSQRTSSZmk_Int:
5849 case VSQRTSSZmkz_Int:
5850 case VSQRTSSZr_Int:
5851 case VSQRTSSZrb_Int:
5852 case VSQRTSSZrbk_Int:
5853 case VSQRTSSZrbkz_Int:
5854 case VSQRTSSZrk_Int:
5855 case VSQRTSSZrkz_Int:
5856 case VSQRTSSm_Int:
5857 case VSQRTSSr_Int:
5858 return true;
5859 }
5860 return false;
5861}
5862
5863bool isVEXPANDPS(unsigned Opcode) {
5864 switch (Opcode) {
5865 case VEXPANDPSZ128rm:
5866 case VEXPANDPSZ128rmk:
5867 case VEXPANDPSZ128rmkz:
5868 case VEXPANDPSZ128rr:
5869 case VEXPANDPSZ128rrk:
5870 case VEXPANDPSZ128rrkz:
5871 case VEXPANDPSZ256rm:
5872 case VEXPANDPSZ256rmk:
5873 case VEXPANDPSZ256rmkz:
5874 case VEXPANDPSZ256rr:
5875 case VEXPANDPSZ256rrk:
5876 case VEXPANDPSZ256rrkz:
5877 case VEXPANDPSZrm:
5878 case VEXPANDPSZrmk:
5879 case VEXPANDPSZrmkz:
5880 case VEXPANDPSZrr:
5881 case VEXPANDPSZrrk:
5882 case VEXPANDPSZrrkz:
5883 return true;
5884 }
5885 return false;
5886}
5887
5888bool isVPCOMPRESSW(unsigned Opcode) {
5889 switch (Opcode) {
5890 case VPCOMPRESSWZ128mr:
5891 case VPCOMPRESSWZ128mrk:
5892 case VPCOMPRESSWZ128rr:
5893 case VPCOMPRESSWZ128rrk:
5894 case VPCOMPRESSWZ128rrkz:
5895 case VPCOMPRESSWZ256mr:
5896 case VPCOMPRESSWZ256mrk:
5897 case VPCOMPRESSWZ256rr:
5898 case VPCOMPRESSWZ256rrk:
5899 case VPCOMPRESSWZ256rrkz:
5900 case VPCOMPRESSWZmr:
5901 case VPCOMPRESSWZmrk:
5902 case VPCOMPRESSWZrr:
5903 case VPCOMPRESSWZrrk:
5904 case VPCOMPRESSWZrrkz:
5905 return true;
5906 }
5907 return false;
5908}
5909
5910bool isPEXTRD(unsigned Opcode) {
5911 switch (Opcode) {
5912 case PEXTRDmri:
5913 case PEXTRDrri:
5914 return true;
5915 }
5916 return false;
5917}
5918
5919bool isVCVTTPS2UQQS(unsigned Opcode) {
5920 switch (Opcode) {
5921 case VCVTTPS2UQQSZ128rm:
5922 case VCVTTPS2UQQSZ128rmb:
5923 case VCVTTPS2UQQSZ128rmbk:
5924 case VCVTTPS2UQQSZ128rmbkz:
5925 case VCVTTPS2UQQSZ128rmk:
5926 case VCVTTPS2UQQSZ128rmkz:
5927 case VCVTTPS2UQQSZ128rr:
5928 case VCVTTPS2UQQSZ128rrk:
5929 case VCVTTPS2UQQSZ128rrkz:
5930 case VCVTTPS2UQQSZ256rm:
5931 case VCVTTPS2UQQSZ256rmb:
5932 case VCVTTPS2UQQSZ256rmbk:
5933 case VCVTTPS2UQQSZ256rmbkz:
5934 case VCVTTPS2UQQSZ256rmk:
5935 case VCVTTPS2UQQSZ256rmkz:
5936 case VCVTTPS2UQQSZ256rr:
5937 case VCVTTPS2UQQSZ256rrb:
5938 case VCVTTPS2UQQSZ256rrbk:
5939 case VCVTTPS2UQQSZ256rrbkz:
5940 case VCVTTPS2UQQSZ256rrk:
5941 case VCVTTPS2UQQSZ256rrkz:
5942 case VCVTTPS2UQQSZrm:
5943 case VCVTTPS2UQQSZrmb:
5944 case VCVTTPS2UQQSZrmbk:
5945 case VCVTTPS2UQQSZrmbkz:
5946 case VCVTTPS2UQQSZrmk:
5947 case VCVTTPS2UQQSZrmkz:
5948 case VCVTTPS2UQQSZrr:
5949 case VCVTTPS2UQQSZrrb:
5950 case VCVTTPS2UQQSZrrbk:
5951 case VCVTTPS2UQQSZrrbkz:
5952 case VCVTTPS2UQQSZrrk:
5953 case VCVTTPS2UQQSZrrkz:
5954 return true;
5955 }
5956 return false;
5957}
5958
5959bool isSYSEXITQ(unsigned Opcode) {
5960 return Opcode == SYSEXIT64;
5961}
5962
5963bool isROUNDSD(unsigned Opcode) {
5964 switch (Opcode) {
5965 case ROUNDSDmi_Int:
5966 case ROUNDSDri_Int:
5967 return true;
5968 }
5969 return false;
5970}
5971
5972bool isVFMADD132BF16(unsigned Opcode) {
5973 switch (Opcode) {
5974 case VFMADD132BF16Z128m:
5975 case VFMADD132BF16Z128mb:
5976 case VFMADD132BF16Z128mbk:
5977 case VFMADD132BF16Z128mbkz:
5978 case VFMADD132BF16Z128mk:
5979 case VFMADD132BF16Z128mkz:
5980 case VFMADD132BF16Z128r:
5981 case VFMADD132BF16Z128rk:
5982 case VFMADD132BF16Z128rkz:
5983 case VFMADD132BF16Z256m:
5984 case VFMADD132BF16Z256mb:
5985 case VFMADD132BF16Z256mbk:
5986 case VFMADD132BF16Z256mbkz:
5987 case VFMADD132BF16Z256mk:
5988 case VFMADD132BF16Z256mkz:
5989 case VFMADD132BF16Z256r:
5990 case VFMADD132BF16Z256rk:
5991 case VFMADD132BF16Z256rkz:
5992 case VFMADD132BF16Zm:
5993 case VFMADD132BF16Zmb:
5994 case VFMADD132BF16Zmbk:
5995 case VFMADD132BF16Zmbkz:
5996 case VFMADD132BF16Zmk:
5997 case VFMADD132BF16Zmkz:
5998 case VFMADD132BF16Zr:
5999 case VFMADD132BF16Zrk:
6000 case VFMADD132BF16Zrkz:
6001 return true;
6002 }
6003 return false;
6004}
6005
6006bool isFCOM(unsigned Opcode) {
6007 switch (Opcode) {
6008 case COM_FST0r:
6009 case FCOM32m:
6010 case FCOM64m:
6011 return true;
6012 }
6013 return false;
6014}
6015
6016bool isVFNMSUBSS(unsigned Opcode) {
6017 switch (Opcode) {
6018 case VFNMSUBSS4mr:
6019 case VFNMSUBSS4rm:
6020 case VFNMSUBSS4rr:
6021 case VFNMSUBSS4rr_REV:
6022 return true;
6023 }
6024 return false;
6025}
6026
6027bool isKSHIFTLW(unsigned Opcode) {
6028 return Opcode == KSHIFTLWki;
6029}
6030
6031bool isSCASD(unsigned Opcode) {
6032 return Opcode == SCASL;
6033}
6034
6035bool isVMPTRLD(unsigned Opcode) {
6036 return Opcode == VMPTRLDm;
6037}
6038
6039bool isVAESDECLAST(unsigned Opcode) {
6040 switch (Opcode) {
6041 case VAESDECLASTYrm:
6042 case VAESDECLASTYrr:
6043 case VAESDECLASTZ128rm:
6044 case VAESDECLASTZ128rr:
6045 case VAESDECLASTZ256rm:
6046 case VAESDECLASTZ256rr:
6047 case VAESDECLASTZrm:
6048 case VAESDECLASTZrr:
6049 case VAESDECLASTrm:
6050 case VAESDECLASTrr:
6051 return true;
6052 }
6053 return false;
6054}
6055
6056bool isVFMADDSUBPS(unsigned Opcode) {
6057 switch (Opcode) {
6058 case VFMADDSUBPS4Ymr:
6059 case VFMADDSUBPS4Yrm:
6060 case VFMADDSUBPS4Yrr:
6061 case VFMADDSUBPS4Yrr_REV:
6062 case VFMADDSUBPS4mr:
6063 case VFMADDSUBPS4rm:
6064 case VFMADDSUBPS4rr:
6065 case VFMADDSUBPS4rr_REV:
6066 return true;
6067 }
6068 return false;
6069}
6070
6071bool isVCVTUQQ2PS(unsigned Opcode) {
6072 switch (Opcode) {
6073 case VCVTUQQ2PSZ128rm:
6074 case VCVTUQQ2PSZ128rmb:
6075 case VCVTUQQ2PSZ128rmbk:
6076 case VCVTUQQ2PSZ128rmbkz:
6077 case VCVTUQQ2PSZ128rmk:
6078 case VCVTUQQ2PSZ128rmkz:
6079 case VCVTUQQ2PSZ128rr:
6080 case VCVTUQQ2PSZ128rrk:
6081 case VCVTUQQ2PSZ128rrkz:
6082 case VCVTUQQ2PSZ256rm:
6083 case VCVTUQQ2PSZ256rmb:
6084 case VCVTUQQ2PSZ256rmbk:
6085 case VCVTUQQ2PSZ256rmbkz:
6086 case VCVTUQQ2PSZ256rmk:
6087 case VCVTUQQ2PSZ256rmkz:
6088 case VCVTUQQ2PSZ256rr:
6089 case VCVTUQQ2PSZ256rrk:
6090 case VCVTUQQ2PSZ256rrkz:
6091 case VCVTUQQ2PSZrm:
6092 case VCVTUQQ2PSZrmb:
6093 case VCVTUQQ2PSZrmbk:
6094 case VCVTUQQ2PSZrmbkz:
6095 case VCVTUQQ2PSZrmk:
6096 case VCVTUQQ2PSZrmkz:
6097 case VCVTUQQ2PSZrr:
6098 case VCVTUQQ2PSZrrb:
6099 case VCVTUQQ2PSZrrbk:
6100 case VCVTUQQ2PSZrrbkz:
6101 case VCVTUQQ2PSZrrk:
6102 case VCVTUQQ2PSZrrkz:
6103 return true;
6104 }
6105 return false;
6106}
6107
6108bool isVPMOVUSDB(unsigned Opcode) {
6109 switch (Opcode) {
6110 case VPMOVUSDBZ128mr:
6111 case VPMOVUSDBZ128mrk:
6112 case VPMOVUSDBZ128rr:
6113 case VPMOVUSDBZ128rrk:
6114 case VPMOVUSDBZ128rrkz:
6115 case VPMOVUSDBZ256mr:
6116 case VPMOVUSDBZ256mrk:
6117 case VPMOVUSDBZ256rr:
6118 case VPMOVUSDBZ256rrk:
6119 case VPMOVUSDBZ256rrkz:
6120 case VPMOVUSDBZmr:
6121 case VPMOVUSDBZmrk:
6122 case VPMOVUSDBZrr:
6123 case VPMOVUSDBZrrk:
6124 case VPMOVUSDBZrrkz:
6125 return true;
6126 }
6127 return false;
6128}
6129
6130bool isVPROTW(unsigned Opcode) {
6131 switch (Opcode) {
6132 case VPROTWmi:
6133 case VPROTWmr:
6134 case VPROTWri:
6135 case VPROTWrm:
6136 case VPROTWrr:
6137 case VPROTWrr_REV:
6138 return true;
6139 }
6140 return false;
6141}
6142
6143bool isVDPPS(unsigned Opcode) {
6144 switch (Opcode) {
6145 case VDPPSYrmi:
6146 case VDPPSYrri:
6147 case VDPPSrmi:
6148 case VDPPSrri:
6149 return true;
6150 }
6151 return false;
6152}
6153
6154bool isVRSQRT14PD(unsigned Opcode) {
6155 switch (Opcode) {
6156 case VRSQRT14PDZ128m:
6157 case VRSQRT14PDZ128mb:
6158 case VRSQRT14PDZ128mbk:
6159 case VRSQRT14PDZ128mbkz:
6160 case VRSQRT14PDZ128mk:
6161 case VRSQRT14PDZ128mkz:
6162 case VRSQRT14PDZ128r:
6163 case VRSQRT14PDZ128rk:
6164 case VRSQRT14PDZ128rkz:
6165 case VRSQRT14PDZ256m:
6166 case VRSQRT14PDZ256mb:
6167 case VRSQRT14PDZ256mbk:
6168 case VRSQRT14PDZ256mbkz:
6169 case VRSQRT14PDZ256mk:
6170 case VRSQRT14PDZ256mkz:
6171 case VRSQRT14PDZ256r:
6172 case VRSQRT14PDZ256rk:
6173 case VRSQRT14PDZ256rkz:
6174 case VRSQRT14PDZm:
6175 case VRSQRT14PDZmb:
6176 case VRSQRT14PDZmbk:
6177 case VRSQRT14PDZmbkz:
6178 case VRSQRT14PDZmk:
6179 case VRSQRT14PDZmkz:
6180 case VRSQRT14PDZr:
6181 case VRSQRT14PDZrk:
6182 case VRSQRT14PDZrkz:
6183 return true;
6184 }
6185 return false;
6186}
6187
6188bool isVTESTPD(unsigned Opcode) {
6189 switch (Opcode) {
6190 case VTESTPDYrm:
6191 case VTESTPDYrr:
6192 case VTESTPDrm:
6193 case VTESTPDrr:
6194 return true;
6195 }
6196 return false;
6197}
6198
6199bool isVFNMADD231SH(unsigned Opcode) {
6200 switch (Opcode) {
6201 case VFNMADD231SHZm_Int:
6202 case VFNMADD231SHZmk_Int:
6203 case VFNMADD231SHZmkz_Int:
6204 case VFNMADD231SHZr_Int:
6205 case VFNMADD231SHZrb_Int:
6206 case VFNMADD231SHZrbk_Int:
6207 case VFNMADD231SHZrbkz_Int:
6208 case VFNMADD231SHZrk_Int:
6209 case VFNMADD231SHZrkz_Int:
6210 return true;
6211 }
6212 return false;
6213}
6214
6215bool isENDBR64(unsigned Opcode) {
6216 return Opcode == ENDBR64;
6217}
6218
6219bool isMULSD(unsigned Opcode) {
6220 switch (Opcode) {
6221 case MULSDrm_Int:
6222 case MULSDrr_Int:
6223 return true;
6224 }
6225 return false;
6226}
6227
6228bool isXRSTORS(unsigned Opcode) {
6229 return Opcode == XRSTORS;
6230}
6231
6232bool isPREFETCHNTA(unsigned Opcode) {
6233 return Opcode == PREFETCHNTA;
6234}
6235
6236bool isVPCOMD(unsigned Opcode) {
6237 switch (Opcode) {
6238 case VPCOMDmi:
6239 case VPCOMDri:
6240 return true;
6241 }
6242 return false;
6243}
6244
6245bool isVPCOMUB(unsigned Opcode) {
6246 switch (Opcode) {
6247 case VPCOMUBmi:
6248 case VPCOMUBri:
6249 return true;
6250 }
6251 return false;
6252}
6253
6254bool isVPHSUBD(unsigned Opcode) {
6255 switch (Opcode) {
6256 case VPHSUBDYrm:
6257 case VPHSUBDYrr:
6258 case VPHSUBDrm:
6259 case VPHSUBDrr:
6260 return true;
6261 }
6262 return false;
6263}
6264
6265bool isVBROADCASTI64X2(unsigned Opcode) {
6266 switch (Opcode) {
6267 case VBROADCASTI64X2Z256rm:
6268 case VBROADCASTI64X2Z256rmk:
6269 case VBROADCASTI64X2Z256rmkz:
6270 case VBROADCASTI64X2Zrm:
6271 case VBROADCASTI64X2Zrmk:
6272 case VBROADCASTI64X2Zrmkz:
6273 return true;
6274 }
6275 return false;
6276}
6277
6278bool isFPATAN(unsigned Opcode) {
6279 return Opcode == FPATAN;
6280}
6281
6282bool isLOOPE(unsigned Opcode) {
6283 return Opcode == LOOPE;
6284}
6285
6286bool isPCMPEQW(unsigned Opcode) {
6287 switch (Opcode) {
6288 case MMX_PCMPEQWrm:
6289 case MMX_PCMPEQWrr:
6290 case PCMPEQWrm:
6291 case PCMPEQWrr:
6292 return true;
6293 }
6294 return false;
6295}
6296
6297bool isVFMADDCSH(unsigned Opcode) {
6298 switch (Opcode) {
6299 case VFMADDCSHZm:
6300 case VFMADDCSHZmk:
6301 case VFMADDCSHZmkz:
6302 case VFMADDCSHZr:
6303 case VFMADDCSHZrb:
6304 case VFMADDCSHZrbk:
6305 case VFMADDCSHZrbkz:
6306 case VFMADDCSHZrk:
6307 case VFMADDCSHZrkz:
6308 return true;
6309 }
6310 return false;
6311}
6312
6313bool isVPDPBSSD(unsigned Opcode) {
6314 switch (Opcode) {
6315 case VPDPBSSDYrm:
6316 case VPDPBSSDYrr:
6317 case VPDPBSSDZ128rm:
6318 case VPDPBSSDZ128rmb:
6319 case VPDPBSSDZ128rmbk:
6320 case VPDPBSSDZ128rmbkz:
6321 case VPDPBSSDZ128rmk:
6322 case VPDPBSSDZ128rmkz:
6323 case VPDPBSSDZ128rr:
6324 case VPDPBSSDZ128rrk:
6325 case VPDPBSSDZ128rrkz:
6326 case VPDPBSSDZ256rm:
6327 case VPDPBSSDZ256rmb:
6328 case VPDPBSSDZ256rmbk:
6329 case VPDPBSSDZ256rmbkz:
6330 case VPDPBSSDZ256rmk:
6331 case VPDPBSSDZ256rmkz:
6332 case VPDPBSSDZ256rr:
6333 case VPDPBSSDZ256rrk:
6334 case VPDPBSSDZ256rrkz:
6335 case VPDPBSSDZrm:
6336 case VPDPBSSDZrmb:
6337 case VPDPBSSDZrmbk:
6338 case VPDPBSSDZrmbkz:
6339 case VPDPBSSDZrmk:
6340 case VPDPBSSDZrmkz:
6341 case VPDPBSSDZrr:
6342 case VPDPBSSDZrrk:
6343 case VPDPBSSDZrrkz:
6344 case VPDPBSSDrm:
6345 case VPDPBSSDrr:
6346 return true;
6347 }
6348 return false;
6349}
6350
6351bool isMOVRS(unsigned Opcode) {
6352 switch (Opcode) {
6353 case MOVRS16rm:
6354 case MOVRS16rm_EVEX:
6355 case MOVRS32rm:
6356 case MOVRS32rm_EVEX:
6357 case MOVRS64rm:
6358 case MOVRS64rm_EVEX:
6359 case MOVRS8rm:
6360 case MOVRS8rm_EVEX:
6361 return true;
6362 }
6363 return false;
6364}
6365
6366bool isVFMSUBADD132PH(unsigned Opcode) {
6367 switch (Opcode) {
6368 case VFMSUBADD132PHZ128m:
6369 case VFMSUBADD132PHZ128mb:
6370 case VFMSUBADD132PHZ128mbk:
6371 case VFMSUBADD132PHZ128mbkz:
6372 case VFMSUBADD132PHZ128mk:
6373 case VFMSUBADD132PHZ128mkz:
6374 case VFMSUBADD132PHZ128r:
6375 case VFMSUBADD132PHZ128rk:
6376 case VFMSUBADD132PHZ128rkz:
6377 case VFMSUBADD132PHZ256m:
6378 case VFMSUBADD132PHZ256mb:
6379 case VFMSUBADD132PHZ256mbk:
6380 case VFMSUBADD132PHZ256mbkz:
6381 case VFMSUBADD132PHZ256mk:
6382 case VFMSUBADD132PHZ256mkz:
6383 case VFMSUBADD132PHZ256r:
6384 case VFMSUBADD132PHZ256rk:
6385 case VFMSUBADD132PHZ256rkz:
6386 case VFMSUBADD132PHZm:
6387 case VFMSUBADD132PHZmb:
6388 case VFMSUBADD132PHZmbk:
6389 case VFMSUBADD132PHZmbkz:
6390 case VFMSUBADD132PHZmk:
6391 case VFMSUBADD132PHZmkz:
6392 case VFMSUBADD132PHZr:
6393 case VFMSUBADD132PHZrb:
6394 case VFMSUBADD132PHZrbk:
6395 case VFMSUBADD132PHZrbkz:
6396 case VFMSUBADD132PHZrk:
6397 case VFMSUBADD132PHZrkz:
6398 return true;
6399 }
6400 return false;
6401}
6402
6403bool isKADDW(unsigned Opcode) {
6404 return Opcode == KADDWkk;
6405}
6406
6407bool isPTEST(unsigned Opcode) {
6408 switch (Opcode) {
6409 case PTESTrm:
6410 case PTESTrr:
6411 return true;
6412 }
6413 return false;
6414}
6415
6416bool isVRSQRT28PS(unsigned Opcode) {
6417 switch (Opcode) {
6418 case VRSQRT28PSZm:
6419 case VRSQRT28PSZmb:
6420 case VRSQRT28PSZmbk:
6421 case VRSQRT28PSZmbkz:
6422 case VRSQRT28PSZmk:
6423 case VRSQRT28PSZmkz:
6424 case VRSQRT28PSZr:
6425 case VRSQRT28PSZrb:
6426 case VRSQRT28PSZrbk:
6427 case VRSQRT28PSZrbkz:
6428 case VRSQRT28PSZrk:
6429 case VRSQRT28PSZrkz:
6430 return true;
6431 }
6432 return false;
6433}
6434
6435bool isVGF2P8AFFINEINVQB(unsigned Opcode) {
6436 switch (Opcode) {
6437 case VGF2P8AFFINEINVQBYrmi:
6438 case VGF2P8AFFINEINVQBYrri:
6439 case VGF2P8AFFINEINVQBZ128rmbi:
6440 case VGF2P8AFFINEINVQBZ128rmbik:
6441 case VGF2P8AFFINEINVQBZ128rmbikz:
6442 case VGF2P8AFFINEINVQBZ128rmi:
6443 case VGF2P8AFFINEINVQBZ128rmik:
6444 case VGF2P8AFFINEINVQBZ128rmikz:
6445 case VGF2P8AFFINEINVQBZ128rri:
6446 case VGF2P8AFFINEINVQBZ128rrik:
6447 case VGF2P8AFFINEINVQBZ128rrikz:
6448 case VGF2P8AFFINEINVQBZ256rmbi:
6449 case VGF2P8AFFINEINVQBZ256rmbik:
6450 case VGF2P8AFFINEINVQBZ256rmbikz:
6451 case VGF2P8AFFINEINVQBZ256rmi:
6452 case VGF2P8AFFINEINVQBZ256rmik:
6453 case VGF2P8AFFINEINVQBZ256rmikz:
6454 case VGF2P8AFFINEINVQBZ256rri:
6455 case VGF2P8AFFINEINVQBZ256rrik:
6456 case VGF2P8AFFINEINVQBZ256rrikz:
6457 case VGF2P8AFFINEINVQBZrmbi:
6458 case VGF2P8AFFINEINVQBZrmbik:
6459 case VGF2P8AFFINEINVQBZrmbikz:
6460 case VGF2P8AFFINEINVQBZrmi:
6461 case VGF2P8AFFINEINVQBZrmik:
6462 case VGF2P8AFFINEINVQBZrmikz:
6463 case VGF2P8AFFINEINVQBZrri:
6464 case VGF2P8AFFINEINVQBZrrik:
6465 case VGF2P8AFFINEINVQBZrrikz:
6466 case VGF2P8AFFINEINVQBrmi:
6467 case VGF2P8AFFINEINVQBrri:
6468 return true;
6469 }
6470 return false;
6471}
6472
6473bool isSERIALIZE(unsigned Opcode) {
6474 return Opcode == SERIALIZE;
6475}
6476
6477bool isVPHADDWQ(unsigned Opcode) {
6478 switch (Opcode) {
6479 case VPHADDWQrm:
6480 case VPHADDWQrr:
6481 return true;
6482 }
6483 return false;
6484}
6485
6486bool isVRNDSCALESH(unsigned Opcode) {
6487 switch (Opcode) {
6488 case VRNDSCALESHZrmi_Int:
6489 case VRNDSCALESHZrmik_Int:
6490 case VRNDSCALESHZrmikz_Int:
6491 case VRNDSCALESHZrri_Int:
6492 case VRNDSCALESHZrrib_Int:
6493 case VRNDSCALESHZrribk_Int:
6494 case VRNDSCALESHZrribkz_Int:
6495 case VRNDSCALESHZrrik_Int:
6496 case VRNDSCALESHZrrikz_Int:
6497 return true;
6498 }
6499 return false;
6500}
6501
6502bool isAAA(unsigned Opcode) {
6503 return Opcode == AAA;
6504}
6505
6506bool isVADDBF16(unsigned Opcode) {
6507 switch (Opcode) {
6508 case VADDBF16Z128rm:
6509 case VADDBF16Z128rmb:
6510 case VADDBF16Z128rmbk:
6511 case VADDBF16Z128rmbkz:
6512 case VADDBF16Z128rmk:
6513 case VADDBF16Z128rmkz:
6514 case VADDBF16Z128rr:
6515 case VADDBF16Z128rrk:
6516 case VADDBF16Z128rrkz:
6517 case VADDBF16Z256rm:
6518 case VADDBF16Z256rmb:
6519 case VADDBF16Z256rmbk:
6520 case VADDBF16Z256rmbkz:
6521 case VADDBF16Z256rmk:
6522 case VADDBF16Z256rmkz:
6523 case VADDBF16Z256rr:
6524 case VADDBF16Z256rrk:
6525 case VADDBF16Z256rrkz:
6526 case VADDBF16Zrm:
6527 case VADDBF16Zrmb:
6528 case VADDBF16Zrmbk:
6529 case VADDBF16Zrmbkz:
6530 case VADDBF16Zrmk:
6531 case VADDBF16Zrmkz:
6532 case VADDBF16Zrr:
6533 case VADDBF16Zrrk:
6534 case VADDBF16Zrrkz:
6535 return true;
6536 }
6537 return false;
6538}
6539
6540bool isWRMSRLIST(unsigned Opcode) {
6541 return Opcode == WRMSRLIST;
6542}
6543
6544bool isVCVTPH2PSX(unsigned Opcode) {
6545 switch (Opcode) {
6546 case VCVTPH2PSXZ128rm:
6547 case VCVTPH2PSXZ128rmb:
6548 case VCVTPH2PSXZ128rmbk:
6549 case VCVTPH2PSXZ128rmbkz:
6550 case VCVTPH2PSXZ128rmk:
6551 case VCVTPH2PSXZ128rmkz:
6552 case VCVTPH2PSXZ128rr:
6553 case VCVTPH2PSXZ128rrk:
6554 case VCVTPH2PSXZ128rrkz:
6555 case VCVTPH2PSXZ256rm:
6556 case VCVTPH2PSXZ256rmb:
6557 case VCVTPH2PSXZ256rmbk:
6558 case VCVTPH2PSXZ256rmbkz:
6559 case VCVTPH2PSXZ256rmk:
6560 case VCVTPH2PSXZ256rmkz:
6561 case VCVTPH2PSXZ256rr:
6562 case VCVTPH2PSXZ256rrk:
6563 case VCVTPH2PSXZ256rrkz:
6564 case VCVTPH2PSXZrm:
6565 case VCVTPH2PSXZrmb:
6566 case VCVTPH2PSXZrmbk:
6567 case VCVTPH2PSXZrmbkz:
6568 case VCVTPH2PSXZrmk:
6569 case VCVTPH2PSXZrmkz:
6570 case VCVTPH2PSXZrr:
6571 case VCVTPH2PSXZrrb:
6572 case VCVTPH2PSXZrrbk:
6573 case VCVTPH2PSXZrrbkz:
6574 case VCVTPH2PSXZrrk:
6575 case VCVTPH2PSXZrrkz:
6576 return true;
6577 }
6578 return false;
6579}
6580
6581bool isVFMSUB231PH(unsigned Opcode) {
6582 switch (Opcode) {
6583 case VFMSUB231PHZ128m:
6584 case VFMSUB231PHZ128mb:
6585 case VFMSUB231PHZ128mbk:
6586 case VFMSUB231PHZ128mbkz:
6587 case VFMSUB231PHZ128mk:
6588 case VFMSUB231PHZ128mkz:
6589 case VFMSUB231PHZ128r:
6590 case VFMSUB231PHZ128rk:
6591 case VFMSUB231PHZ128rkz:
6592 case VFMSUB231PHZ256m:
6593 case VFMSUB231PHZ256mb:
6594 case VFMSUB231PHZ256mbk:
6595 case VFMSUB231PHZ256mbkz:
6596 case VFMSUB231PHZ256mk:
6597 case VFMSUB231PHZ256mkz:
6598 case VFMSUB231PHZ256r:
6599 case VFMSUB231PHZ256rk:
6600 case VFMSUB231PHZ256rkz:
6601 case VFMSUB231PHZm:
6602 case VFMSUB231PHZmb:
6603 case VFMSUB231PHZmbk:
6604 case VFMSUB231PHZmbkz:
6605 case VFMSUB231PHZmk:
6606 case VFMSUB231PHZmkz:
6607 case VFMSUB231PHZr:
6608 case VFMSUB231PHZrb:
6609 case VFMSUB231PHZrbk:
6610 case VFMSUB231PHZrbkz:
6611 case VFMSUB231PHZrk:
6612 case VFMSUB231PHZrkz:
6613 return true;
6614 }
6615 return false;
6616}
6617
6618bool isVGATHERQPD(unsigned Opcode) {
6619 switch (Opcode) {
6620 case VGATHERQPDYrm:
6621 case VGATHERQPDZ128rm:
6622 case VGATHERQPDZ256rm:
6623 case VGATHERQPDZrm:
6624 case VGATHERQPDrm:
6625 return true;
6626 }
6627 return false;
6628}
6629
6630bool isKADDB(unsigned Opcode) {
6631 return Opcode == KADDBkk;
6632}
6633
6634bool isCVTPD2PI(unsigned Opcode) {
6635 switch (Opcode) {
6636 case MMX_CVTPD2PIrm:
6637 case MMX_CVTPD2PIrr:
6638 return true;
6639 }
6640 return false;
6641}
6642
6643bool isVFNMSUB213PH(unsigned Opcode) {
6644 switch (Opcode) {
6645 case VFNMSUB213PHZ128m:
6646 case VFNMSUB213PHZ128mb:
6647 case VFNMSUB213PHZ128mbk:
6648 case VFNMSUB213PHZ128mbkz:
6649 case VFNMSUB213PHZ128mk:
6650 case VFNMSUB213PHZ128mkz:
6651 case VFNMSUB213PHZ128r:
6652 case VFNMSUB213PHZ128rk:
6653 case VFNMSUB213PHZ128rkz:
6654 case VFNMSUB213PHZ256m:
6655 case VFNMSUB213PHZ256mb:
6656 case VFNMSUB213PHZ256mbk:
6657 case VFNMSUB213PHZ256mbkz:
6658 case VFNMSUB213PHZ256mk:
6659 case VFNMSUB213PHZ256mkz:
6660 case VFNMSUB213PHZ256r:
6661 case VFNMSUB213PHZ256rk:
6662 case VFNMSUB213PHZ256rkz:
6663 case VFNMSUB213PHZm:
6664 case VFNMSUB213PHZmb:
6665 case VFNMSUB213PHZmbk:
6666 case VFNMSUB213PHZmbkz:
6667 case VFNMSUB213PHZmk:
6668 case VFNMSUB213PHZmkz:
6669 case VFNMSUB213PHZr:
6670 case VFNMSUB213PHZrb:
6671 case VFNMSUB213PHZrbk:
6672 case VFNMSUB213PHZrbkz:
6673 case VFNMSUB213PHZrk:
6674 case VFNMSUB213PHZrkz:
6675 return true;
6676 }
6677 return false;
6678}
6679
6680bool isXORPS(unsigned Opcode) {
6681 switch (Opcode) {
6682 case XORPSrm:
6683 case XORPSrr:
6684 return true;
6685 }
6686 return false;
6687}
6688
6689bool isVPCMPESTRI(unsigned Opcode) {
6690 switch (Opcode) {
6691 case VPCMPESTRIrmi:
6692 case VPCMPESTRIrri:
6693 return true;
6694 }
6695 return false;
6696}
6697
6698bool isVPADDSB(unsigned Opcode) {
6699 switch (Opcode) {
6700 case VPADDSBYrm:
6701 case VPADDSBYrr:
6702 case VPADDSBZ128rm:
6703 case VPADDSBZ128rmk:
6704 case VPADDSBZ128rmkz:
6705 case VPADDSBZ128rr:
6706 case VPADDSBZ128rrk:
6707 case VPADDSBZ128rrkz:
6708 case VPADDSBZ256rm:
6709 case VPADDSBZ256rmk:
6710 case VPADDSBZ256rmkz:
6711 case VPADDSBZ256rr:
6712 case VPADDSBZ256rrk:
6713 case VPADDSBZ256rrkz:
6714 case VPADDSBZrm:
6715 case VPADDSBZrmk:
6716 case VPADDSBZrmkz:
6717 case VPADDSBZrr:
6718 case VPADDSBZrrk:
6719 case VPADDSBZrrkz:
6720 case VPADDSBrm:
6721 case VPADDSBrr:
6722 return true;
6723 }
6724 return false;
6725}
6726
6727bool isPOP2(unsigned Opcode) {
6728 return Opcode == POP2;
6729}
6730
6731bool isRDMSRLIST(unsigned Opcode) {
6732 return Opcode == RDMSRLIST;
6733}
6734
6735bool isVPSHRDW(unsigned Opcode) {
6736 switch (Opcode) {
6737 case VPSHRDWZ128rmi:
6738 case VPSHRDWZ128rmik:
6739 case VPSHRDWZ128rmikz:
6740 case VPSHRDWZ128rri:
6741 case VPSHRDWZ128rrik:
6742 case VPSHRDWZ128rrikz:
6743 case VPSHRDWZ256rmi:
6744 case VPSHRDWZ256rmik:
6745 case VPSHRDWZ256rmikz:
6746 case VPSHRDWZ256rri:
6747 case VPSHRDWZ256rrik:
6748 case VPSHRDWZ256rrikz:
6749 case VPSHRDWZrmi:
6750 case VPSHRDWZrmik:
6751 case VPSHRDWZrmikz:
6752 case VPSHRDWZrri:
6753 case VPSHRDWZrrik:
6754 case VPSHRDWZrrikz:
6755 return true;
6756 }
6757 return false;
6758}
6759
6760bool isVPDPBUSD(unsigned Opcode) {
6761 switch (Opcode) {
6762 case VPDPBUSDYrm:
6763 case VPDPBUSDYrr:
6764 case VPDPBUSDZ128rm:
6765 case VPDPBUSDZ128rmb:
6766 case VPDPBUSDZ128rmbk:
6767 case VPDPBUSDZ128rmbkz:
6768 case VPDPBUSDZ128rmk:
6769 case VPDPBUSDZ128rmkz:
6770 case VPDPBUSDZ128rr:
6771 case VPDPBUSDZ128rrk:
6772 case VPDPBUSDZ128rrkz:
6773 case VPDPBUSDZ256rm:
6774 case VPDPBUSDZ256rmb:
6775 case VPDPBUSDZ256rmbk:
6776 case VPDPBUSDZ256rmbkz:
6777 case VPDPBUSDZ256rmk:
6778 case VPDPBUSDZ256rmkz:
6779 case VPDPBUSDZ256rr:
6780 case VPDPBUSDZ256rrk:
6781 case VPDPBUSDZ256rrkz:
6782 case VPDPBUSDZrm:
6783 case VPDPBUSDZrmb:
6784 case VPDPBUSDZrmbk:
6785 case VPDPBUSDZrmbkz:
6786 case VPDPBUSDZrmk:
6787 case VPDPBUSDZrmkz:
6788 case VPDPBUSDZrr:
6789 case VPDPBUSDZrrk:
6790 case VPDPBUSDZrrkz:
6791 case VPDPBUSDrm:
6792 case VPDPBUSDrr:
6793 return true;
6794 }
6795 return false;
6796}
6797
6798bool isVCMPPH(unsigned Opcode) {
6799 switch (Opcode) {
6800 case VCMPPHZ128rmbi:
6801 case VCMPPHZ128rmbik:
6802 case VCMPPHZ128rmi:
6803 case VCMPPHZ128rmik:
6804 case VCMPPHZ128rri:
6805 case VCMPPHZ128rrik:
6806 case VCMPPHZ256rmbi:
6807 case VCMPPHZ256rmbik:
6808 case VCMPPHZ256rmi:
6809 case VCMPPHZ256rmik:
6810 case VCMPPHZ256rri:
6811 case VCMPPHZ256rrik:
6812 case VCMPPHZrmbi:
6813 case VCMPPHZrmbik:
6814 case VCMPPHZrmi:
6815 case VCMPPHZrmik:
6816 case VCMPPHZrri:
6817 case VCMPPHZrrib:
6818 case VCMPPHZrribk:
6819 case VCMPPHZrrik:
6820 return true;
6821 }
6822 return false;
6823}
6824
6825bool isVANDNPD(unsigned Opcode) {
6826 switch (Opcode) {
6827 case VANDNPDYrm:
6828 case VANDNPDYrr:
6829 case VANDNPDZ128rm:
6830 case VANDNPDZ128rmb:
6831 case VANDNPDZ128rmbk:
6832 case VANDNPDZ128rmbkz:
6833 case VANDNPDZ128rmk:
6834 case VANDNPDZ128rmkz:
6835 case VANDNPDZ128rr:
6836 case VANDNPDZ128rrk:
6837 case VANDNPDZ128rrkz:
6838 case VANDNPDZ256rm:
6839 case VANDNPDZ256rmb:
6840 case VANDNPDZ256rmbk:
6841 case VANDNPDZ256rmbkz:
6842 case VANDNPDZ256rmk:
6843 case VANDNPDZ256rmkz:
6844 case VANDNPDZ256rr:
6845 case VANDNPDZ256rrk:
6846 case VANDNPDZ256rrkz:
6847 case VANDNPDZrm:
6848 case VANDNPDZrmb:
6849 case VANDNPDZrmbk:
6850 case VANDNPDZrmbkz:
6851 case VANDNPDZrmk:
6852 case VANDNPDZrmkz:
6853 case VANDNPDZrr:
6854 case VANDNPDZrrk:
6855 case VANDNPDZrrkz:
6856 case VANDNPDrm:
6857 case VANDNPDrr:
6858 return true;
6859 }
6860 return false;
6861}
6862
6863bool isSUB(unsigned Opcode) {
6864 switch (Opcode) {
6865 case SUB16i16:
6866 case SUB16mi:
6867 case SUB16mi8:
6868 case SUB16mi8_EVEX:
6869 case SUB16mi8_ND:
6870 case SUB16mi8_NF:
6871 case SUB16mi8_NF_ND:
6872 case SUB16mi_EVEX:
6873 case SUB16mi_ND:
6874 case SUB16mi_NF:
6875 case SUB16mi_NF_ND:
6876 case SUB16mr:
6877 case SUB16mr_EVEX:
6878 case SUB16mr_ND:
6879 case SUB16mr_NF:
6880 case SUB16mr_NF_ND:
6881 case SUB16ri:
6882 case SUB16ri8:
6883 case SUB16ri8_EVEX:
6884 case SUB16ri8_ND:
6885 case SUB16ri8_NF:
6886 case SUB16ri8_NF_ND:
6887 case SUB16ri_EVEX:
6888 case SUB16ri_ND:
6889 case SUB16ri_NF:
6890 case SUB16ri_NF_ND:
6891 case SUB16rm:
6892 case SUB16rm_EVEX:
6893 case SUB16rm_ND:
6894 case SUB16rm_NF:
6895 case SUB16rm_NF_ND:
6896 case SUB16rr:
6897 case SUB16rr_EVEX:
6898 case SUB16rr_EVEX_REV:
6899 case SUB16rr_ND:
6900 case SUB16rr_ND_REV:
6901 case SUB16rr_NF:
6902 case SUB16rr_NF_ND:
6903 case SUB16rr_NF_ND_REV:
6904 case SUB16rr_NF_REV:
6905 case SUB16rr_REV:
6906 case SUB32i32:
6907 case SUB32mi:
6908 case SUB32mi8:
6909 case SUB32mi8_EVEX:
6910 case SUB32mi8_ND:
6911 case SUB32mi8_NF:
6912 case SUB32mi8_NF_ND:
6913 case SUB32mi_EVEX:
6914 case SUB32mi_ND:
6915 case SUB32mi_NF:
6916 case SUB32mi_NF_ND:
6917 case SUB32mr:
6918 case SUB32mr_EVEX:
6919 case SUB32mr_ND:
6920 case SUB32mr_NF:
6921 case SUB32mr_NF_ND:
6922 case SUB32ri:
6923 case SUB32ri8:
6924 case SUB32ri8_EVEX:
6925 case SUB32ri8_ND:
6926 case SUB32ri8_NF:
6927 case SUB32ri8_NF_ND:
6928 case SUB32ri_EVEX:
6929 case SUB32ri_ND:
6930 case SUB32ri_NF:
6931 case SUB32ri_NF_ND:
6932 case SUB32rm:
6933 case SUB32rm_EVEX:
6934 case SUB32rm_ND:
6935 case SUB32rm_NF:
6936 case SUB32rm_NF_ND:
6937 case SUB32rr:
6938 case SUB32rr_EVEX:
6939 case SUB32rr_EVEX_REV:
6940 case SUB32rr_ND:
6941 case SUB32rr_ND_REV:
6942 case SUB32rr_NF:
6943 case SUB32rr_NF_ND:
6944 case SUB32rr_NF_ND_REV:
6945 case SUB32rr_NF_REV:
6946 case SUB32rr_REV:
6947 case SUB64i32:
6948 case SUB64mi32:
6949 case SUB64mi32_EVEX:
6950 case SUB64mi32_ND:
6951 case SUB64mi32_NF:
6952 case SUB64mi32_NF_ND:
6953 case SUB64mi8:
6954 case SUB64mi8_EVEX:
6955 case SUB64mi8_ND:
6956 case SUB64mi8_NF:
6957 case SUB64mi8_NF_ND:
6958 case SUB64mr:
6959 case SUB64mr_EVEX:
6960 case SUB64mr_ND:
6961 case SUB64mr_NF:
6962 case SUB64mr_NF_ND:
6963 case SUB64ri32:
6964 case SUB64ri32_EVEX:
6965 case SUB64ri32_ND:
6966 case SUB64ri32_NF:
6967 case SUB64ri32_NF_ND:
6968 case SUB64ri8:
6969 case SUB64ri8_EVEX:
6970 case SUB64ri8_ND:
6971 case SUB64ri8_NF:
6972 case SUB64ri8_NF_ND:
6973 case SUB64rm:
6974 case SUB64rm_EVEX:
6975 case SUB64rm_ND:
6976 case SUB64rm_NF:
6977 case SUB64rm_NF_ND:
6978 case SUB64rr:
6979 case SUB64rr_EVEX:
6980 case SUB64rr_EVEX_REV:
6981 case SUB64rr_ND:
6982 case SUB64rr_ND_REV:
6983 case SUB64rr_NF:
6984 case SUB64rr_NF_ND:
6985 case SUB64rr_NF_ND_REV:
6986 case SUB64rr_NF_REV:
6987 case SUB64rr_REV:
6988 case SUB8i8:
6989 case SUB8mi:
6990 case SUB8mi8:
6991 case SUB8mi_EVEX:
6992 case SUB8mi_ND:
6993 case SUB8mi_NF:
6994 case SUB8mi_NF_ND:
6995 case SUB8mr:
6996 case SUB8mr_EVEX:
6997 case SUB8mr_ND:
6998 case SUB8mr_NF:
6999 case SUB8mr_NF_ND:
7000 case SUB8ri:
7001 case SUB8ri8:
7002 case SUB8ri_EVEX:
7003 case SUB8ri_ND:
7004 case SUB8ri_NF:
7005 case SUB8ri_NF_ND:
7006 case SUB8rm:
7007 case SUB8rm_EVEX:
7008 case SUB8rm_ND:
7009 case SUB8rm_NF:
7010 case SUB8rm_NF_ND:
7011 case SUB8rr:
7012 case SUB8rr_EVEX:
7013 case SUB8rr_EVEX_REV:
7014 case SUB8rr_ND:
7015 case SUB8rr_ND_REV:
7016 case SUB8rr_NF:
7017 case SUB8rr_NF_ND:
7018 case SUB8rr_NF_ND_REV:
7019 case SUB8rr_NF_REV:
7020 case SUB8rr_REV:
7021 return true;
7022 }
7023 return false;
7024}
7025
7026bool isVRSQRT28PD(unsigned Opcode) {
7027 switch (Opcode) {
7028 case VRSQRT28PDZm:
7029 case VRSQRT28PDZmb:
7030 case VRSQRT28PDZmbk:
7031 case VRSQRT28PDZmbkz:
7032 case VRSQRT28PDZmk:
7033 case VRSQRT28PDZmkz:
7034 case VRSQRT28PDZr:
7035 case VRSQRT28PDZrb:
7036 case VRSQRT28PDZrbk:
7037 case VRSQRT28PDZrbkz:
7038 case VRSQRT28PDZrk:
7039 case VRSQRT28PDZrkz:
7040 return true;
7041 }
7042 return false;
7043}
7044
7045bool isVFNMADD132PH(unsigned Opcode) {
7046 switch (Opcode) {
7047 case VFNMADD132PHZ128m:
7048 case VFNMADD132PHZ128mb:
7049 case VFNMADD132PHZ128mbk:
7050 case VFNMADD132PHZ128mbkz:
7051 case VFNMADD132PHZ128mk:
7052 case VFNMADD132PHZ128mkz:
7053 case VFNMADD132PHZ128r:
7054 case VFNMADD132PHZ128rk:
7055 case VFNMADD132PHZ128rkz:
7056 case VFNMADD132PHZ256m:
7057 case VFNMADD132PHZ256mb:
7058 case VFNMADD132PHZ256mbk:
7059 case VFNMADD132PHZ256mbkz:
7060 case VFNMADD132PHZ256mk:
7061 case VFNMADD132PHZ256mkz:
7062 case VFNMADD132PHZ256r:
7063 case VFNMADD132PHZ256rk:
7064 case VFNMADD132PHZ256rkz:
7065 case VFNMADD132PHZm:
7066 case VFNMADD132PHZmb:
7067 case VFNMADD132PHZmbk:
7068 case VFNMADD132PHZmbkz:
7069 case VFNMADD132PHZmk:
7070 case VFNMADD132PHZmkz:
7071 case VFNMADD132PHZr:
7072 case VFNMADD132PHZrb:
7073 case VFNMADD132PHZrbk:
7074 case VFNMADD132PHZrbkz:
7075 case VFNMADD132PHZrk:
7076 case VFNMADD132PHZrkz:
7077 return true;
7078 }
7079 return false;
7080}
7081
7082bool isVPMACSSWW(unsigned Opcode) {
7083 switch (Opcode) {
7084 case VPMACSSWWrm:
7085 case VPMACSSWWrr:
7086 return true;
7087 }
7088 return false;
7089}
7090
7091bool isXSTORE(unsigned Opcode) {
7092 return Opcode == XSTORE;
7093}
7094
7095bool isVPROTQ(unsigned Opcode) {
7096 switch (Opcode) {
7097 case VPROTQmi:
7098 case VPROTQmr:
7099 case VPROTQri:
7100 case VPROTQrm:
7101 case VPROTQrr:
7102 case VPROTQrr_REV:
7103 return true;
7104 }
7105 return false;
7106}
7107
7108bool isVPHADDBD(unsigned Opcode) {
7109 switch (Opcode) {
7110 case VPHADDBDrm:
7111 case VPHADDBDrr:
7112 return true;
7113 }
7114 return false;
7115}
7116
7117bool isVPMAXSB(unsigned Opcode) {
7118 switch (Opcode) {
7119 case VPMAXSBYrm:
7120 case VPMAXSBYrr:
7121 case VPMAXSBZ128rm:
7122 case VPMAXSBZ128rmk:
7123 case VPMAXSBZ128rmkz:
7124 case VPMAXSBZ128rr:
7125 case VPMAXSBZ128rrk:
7126 case VPMAXSBZ128rrkz:
7127 case VPMAXSBZ256rm:
7128 case VPMAXSBZ256rmk:
7129 case VPMAXSBZ256rmkz:
7130 case VPMAXSBZ256rr:
7131 case VPMAXSBZ256rrk:
7132 case VPMAXSBZ256rrkz:
7133 case VPMAXSBZrm:
7134 case VPMAXSBZrmk:
7135 case VPMAXSBZrmkz:
7136 case VPMAXSBZrr:
7137 case VPMAXSBZrrk:
7138 case VPMAXSBZrrkz:
7139 case VPMAXSBrm:
7140 case VPMAXSBrr:
7141 return true;
7142 }
7143 return false;
7144}
7145
7146bool isVMOVDQU8(unsigned Opcode) {
7147 switch (Opcode) {
7148 case VMOVDQU8Z128mr:
7149 case VMOVDQU8Z128mrk:
7150 case VMOVDQU8Z128rm:
7151 case VMOVDQU8Z128rmk:
7152 case VMOVDQU8Z128rmkz:
7153 case VMOVDQU8Z128rr:
7154 case VMOVDQU8Z128rr_REV:
7155 case VMOVDQU8Z128rrk:
7156 case VMOVDQU8Z128rrk_REV:
7157 case VMOVDQU8Z128rrkz:
7158 case VMOVDQU8Z128rrkz_REV:
7159 case VMOVDQU8Z256mr:
7160 case VMOVDQU8Z256mrk:
7161 case VMOVDQU8Z256rm:
7162 case VMOVDQU8Z256rmk:
7163 case VMOVDQU8Z256rmkz:
7164 case VMOVDQU8Z256rr:
7165 case VMOVDQU8Z256rr_REV:
7166 case VMOVDQU8Z256rrk:
7167 case VMOVDQU8Z256rrk_REV:
7168 case VMOVDQU8Z256rrkz:
7169 case VMOVDQU8Z256rrkz_REV:
7170 case VMOVDQU8Zmr:
7171 case VMOVDQU8Zmrk:
7172 case VMOVDQU8Zrm:
7173 case VMOVDQU8Zrmk:
7174 case VMOVDQU8Zrmkz:
7175 case VMOVDQU8Zrr:
7176 case VMOVDQU8Zrr_REV:
7177 case VMOVDQU8Zrrk:
7178 case VMOVDQU8Zrrk_REV:
7179 case VMOVDQU8Zrrkz:
7180 case VMOVDQU8Zrrkz_REV:
7181 return true;
7182 }
7183 return false;
7184}
7185
7186bool isVPMOVSXWD(unsigned Opcode) {
7187 switch (Opcode) {
7188 case VPMOVSXWDYrm:
7189 case VPMOVSXWDYrr:
7190 case VPMOVSXWDZ128rm:
7191 case VPMOVSXWDZ128rmk:
7192 case VPMOVSXWDZ128rmkz:
7193 case VPMOVSXWDZ128rr:
7194 case VPMOVSXWDZ128rrk:
7195 case VPMOVSXWDZ128rrkz:
7196 case VPMOVSXWDZ256rm:
7197 case VPMOVSXWDZ256rmk:
7198 case VPMOVSXWDZ256rmkz:
7199 case VPMOVSXWDZ256rr:
7200 case VPMOVSXWDZ256rrk:
7201 case VPMOVSXWDZ256rrkz:
7202 case VPMOVSXWDZrm:
7203 case VPMOVSXWDZrmk:
7204 case VPMOVSXWDZrmkz:
7205 case VPMOVSXWDZrr:
7206 case VPMOVSXWDZrrk:
7207 case VPMOVSXWDZrrkz:
7208 case VPMOVSXWDrm:
7209 case VPMOVSXWDrr:
7210 return true;
7211 }
7212 return false;
7213}
7214
7215bool isVMINMAXPD(unsigned Opcode) {
7216 switch (Opcode) {
7217 case VMINMAXPDZ128rmbi:
7218 case VMINMAXPDZ128rmbik:
7219 case VMINMAXPDZ128rmbikz:
7220 case VMINMAXPDZ128rmi:
7221 case VMINMAXPDZ128rmik:
7222 case VMINMAXPDZ128rmikz:
7223 case VMINMAXPDZ128rri:
7224 case VMINMAXPDZ128rrik:
7225 case VMINMAXPDZ128rrikz:
7226 case VMINMAXPDZ256rmbi:
7227 case VMINMAXPDZ256rmbik:
7228 case VMINMAXPDZ256rmbikz:
7229 case VMINMAXPDZ256rmi:
7230 case VMINMAXPDZ256rmik:
7231 case VMINMAXPDZ256rmikz:
7232 case VMINMAXPDZ256rri:
7233 case VMINMAXPDZ256rrik:
7234 case VMINMAXPDZ256rrikz:
7235 case VMINMAXPDZrmbi:
7236 case VMINMAXPDZrmbik:
7237 case VMINMAXPDZrmbikz:
7238 case VMINMAXPDZrmi:
7239 case VMINMAXPDZrmik:
7240 case VMINMAXPDZrmikz:
7241 case VMINMAXPDZrri:
7242 case VMINMAXPDZrrib:
7243 case VMINMAXPDZrribk:
7244 case VMINMAXPDZrribkz:
7245 case VMINMAXPDZrrik:
7246 case VMINMAXPDZrrikz:
7247 return true;
7248 }
7249 return false;
7250}
7251
7252bool isSHA256RNDS2(unsigned Opcode) {
7253 switch (Opcode) {
7254 case SHA256RNDS2rm:
7255 case SHA256RNDS2rr:
7256 return true;
7257 }
7258 return false;
7259}
7260
7261bool isKANDB(unsigned Opcode) {
7262 return Opcode == KANDBkk;
7263}
7264
7265bool isTPAUSE(unsigned Opcode) {
7266 return Opcode == TPAUSE;
7267}
7268
7269bool isPUSH(unsigned Opcode) {
7270 switch (Opcode) {
7271 case PUSH16i:
7272 case PUSH16i8:
7273 case PUSH16r:
7274 case PUSH16rmm:
7275 case PUSH16rmr:
7276 case PUSH32i:
7277 case PUSH32i8:
7278 case PUSH32r:
7279 case PUSH32rmm:
7280 case PUSH32rmr:
7281 case PUSH64i32:
7282 case PUSH64i8:
7283 case PUSH64r:
7284 case PUSH64rmm:
7285 case PUSH64rmr:
7286 case PUSHCS16:
7287 case PUSHCS32:
7288 case PUSHDS16:
7289 case PUSHDS32:
7290 case PUSHES16:
7291 case PUSHES32:
7292 case PUSHFS16:
7293 case PUSHFS32:
7294 case PUSHFS64:
7295 case PUSHGS16:
7296 case PUSHGS32:
7297 case PUSHGS64:
7298 case PUSHSS16:
7299 case PUSHSS32:
7300 return true;
7301 }
7302 return false;
7303}
7304
7305bool isVRNDSCALESS(unsigned Opcode) {
7306 switch (Opcode) {
7307 case VRNDSCALESSZrmi_Int:
7308 case VRNDSCALESSZrmik_Int:
7309 case VRNDSCALESSZrmikz_Int:
7310 case VRNDSCALESSZrri_Int:
7311 case VRNDSCALESSZrrib_Int:
7312 case VRNDSCALESSZrribk_Int:
7313 case VRNDSCALESSZrribkz_Int:
7314 case VRNDSCALESSZrrik_Int:
7315 case VRNDSCALESSZrrikz_Int:
7316 return true;
7317 }
7318 return false;
7319}
7320
7321bool isVRNDSCALEBF16(unsigned Opcode) {
7322 switch (Opcode) {
7323 case VRNDSCALEBF16Z128rmbi:
7324 case VRNDSCALEBF16Z128rmbik:
7325 case VRNDSCALEBF16Z128rmbikz:
7326 case VRNDSCALEBF16Z128rmi:
7327 case VRNDSCALEBF16Z128rmik:
7328 case VRNDSCALEBF16Z128rmikz:
7329 case VRNDSCALEBF16Z128rri:
7330 case VRNDSCALEBF16Z128rrik:
7331 case VRNDSCALEBF16Z128rrikz:
7332 case VRNDSCALEBF16Z256rmbi:
7333 case VRNDSCALEBF16Z256rmbik:
7334 case VRNDSCALEBF16Z256rmbikz:
7335 case VRNDSCALEBF16Z256rmi:
7336 case VRNDSCALEBF16Z256rmik:
7337 case VRNDSCALEBF16Z256rmikz:
7338 case VRNDSCALEBF16Z256rri:
7339 case VRNDSCALEBF16Z256rrik:
7340 case VRNDSCALEBF16Z256rrikz:
7341 case VRNDSCALEBF16Zrmbi:
7342 case VRNDSCALEBF16Zrmbik:
7343 case VRNDSCALEBF16Zrmbikz:
7344 case VRNDSCALEBF16Zrmi:
7345 case VRNDSCALEBF16Zrmik:
7346 case VRNDSCALEBF16Zrmikz:
7347 case VRNDSCALEBF16Zrri:
7348 case VRNDSCALEBF16Zrrik:
7349 case VRNDSCALEBF16Zrrikz:
7350 return true;
7351 }
7352 return false;
7353}
7354
7355bool isVPCMPISTRI(unsigned Opcode) {
7356 switch (Opcode) {
7357 case VPCMPISTRIrmi:
7358 case VPCMPISTRIrri:
7359 return true;
7360 }
7361 return false;
7362}
7363
7364bool isSTGI(unsigned Opcode) {
7365 return Opcode == STGI;
7366}
7367
7368bool isSBB(unsigned Opcode) {
7369 switch (Opcode) {
7370 case SBB16i16:
7371 case SBB16mi:
7372 case SBB16mi8:
7373 case SBB16mi8_EVEX:
7374 case SBB16mi8_ND:
7375 case SBB16mi_EVEX:
7376 case SBB16mi_ND:
7377 case SBB16mr:
7378 case SBB16mr_EVEX:
7379 case SBB16mr_ND:
7380 case SBB16ri:
7381 case SBB16ri8:
7382 case SBB16ri8_EVEX:
7383 case SBB16ri8_ND:
7384 case SBB16ri_EVEX:
7385 case SBB16ri_ND:
7386 case SBB16rm:
7387 case SBB16rm_EVEX:
7388 case SBB16rm_ND:
7389 case SBB16rr:
7390 case SBB16rr_EVEX:
7391 case SBB16rr_EVEX_REV:
7392 case SBB16rr_ND:
7393 case SBB16rr_ND_REV:
7394 case SBB16rr_REV:
7395 case SBB32i32:
7396 case SBB32mi:
7397 case SBB32mi8:
7398 case SBB32mi8_EVEX:
7399 case SBB32mi8_ND:
7400 case SBB32mi_EVEX:
7401 case SBB32mi_ND:
7402 case SBB32mr:
7403 case SBB32mr_EVEX:
7404 case SBB32mr_ND:
7405 case SBB32ri:
7406 case SBB32ri8:
7407 case SBB32ri8_EVEX:
7408 case SBB32ri8_ND:
7409 case SBB32ri_EVEX:
7410 case SBB32ri_ND:
7411 case SBB32rm:
7412 case SBB32rm_EVEX:
7413 case SBB32rm_ND:
7414 case SBB32rr:
7415 case SBB32rr_EVEX:
7416 case SBB32rr_EVEX_REV:
7417 case SBB32rr_ND:
7418 case SBB32rr_ND_REV:
7419 case SBB32rr_REV:
7420 case SBB64i32:
7421 case SBB64mi32:
7422 case SBB64mi32_EVEX:
7423 case SBB64mi32_ND:
7424 case SBB64mi8:
7425 case SBB64mi8_EVEX:
7426 case SBB64mi8_ND:
7427 case SBB64mr:
7428 case SBB64mr_EVEX:
7429 case SBB64mr_ND:
7430 case SBB64ri32:
7431 case SBB64ri32_EVEX:
7432 case SBB64ri32_ND:
7433 case SBB64ri8:
7434 case SBB64ri8_EVEX:
7435 case SBB64ri8_ND:
7436 case SBB64rm:
7437 case SBB64rm_EVEX:
7438 case SBB64rm_ND:
7439 case SBB64rr:
7440 case SBB64rr_EVEX:
7441 case SBB64rr_EVEX_REV:
7442 case SBB64rr_ND:
7443 case SBB64rr_ND_REV:
7444 case SBB64rr_REV:
7445 case SBB8i8:
7446 case SBB8mi:
7447 case SBB8mi8:
7448 case SBB8mi_EVEX:
7449 case SBB8mi_ND:
7450 case SBB8mr:
7451 case SBB8mr_EVEX:
7452 case SBB8mr_ND:
7453 case SBB8ri:
7454 case SBB8ri8:
7455 case SBB8ri_EVEX:
7456 case SBB8ri_ND:
7457 case SBB8rm:
7458 case SBB8rm_EVEX:
7459 case SBB8rm_ND:
7460 case SBB8rr:
7461 case SBB8rr_EVEX:
7462 case SBB8rr_EVEX_REV:
7463 case SBB8rr_ND:
7464 case SBB8rr_ND_REV:
7465 case SBB8rr_REV:
7466 return true;
7467 }
7468 return false;
7469}
7470
7471bool isBLCS(unsigned Opcode) {
7472 switch (Opcode) {
7473 case BLCS32rm:
7474 case BLCS32rr:
7475 case BLCS64rm:
7476 case BLCS64rr:
7477 return true;
7478 }
7479 return false;
7480}
7481
7482bool isVCVTSD2SH(unsigned Opcode) {
7483 switch (Opcode) {
7484 case VCVTSD2SHZrm_Int:
7485 case VCVTSD2SHZrmk_Int:
7486 case VCVTSD2SHZrmkz_Int:
7487 case VCVTSD2SHZrr_Int:
7488 case VCVTSD2SHZrrb_Int:
7489 case VCVTSD2SHZrrbk_Int:
7490 case VCVTSD2SHZrrbkz_Int:
7491 case VCVTSD2SHZrrk_Int:
7492 case VCVTSD2SHZrrkz_Int:
7493 return true;
7494 }
7495 return false;
7496}
7497
7498bool isVPERMW(unsigned Opcode) {
7499 switch (Opcode) {
7500 case VPERMWZ128rm:
7501 case VPERMWZ128rmk:
7502 case VPERMWZ128rmkz:
7503 case VPERMWZ128rr:
7504 case VPERMWZ128rrk:
7505 case VPERMWZ128rrkz:
7506 case VPERMWZ256rm:
7507 case VPERMWZ256rmk:
7508 case VPERMWZ256rmkz:
7509 case VPERMWZ256rr:
7510 case VPERMWZ256rrk:
7511 case VPERMWZ256rrkz:
7512 case VPERMWZrm:
7513 case VPERMWZrmk:
7514 case VPERMWZrmkz:
7515 case VPERMWZrr:
7516 case VPERMWZrrk:
7517 case VPERMWZrrkz:
7518 return true;
7519 }
7520 return false;
7521}
7522
7523bool isXRESLDTRK(unsigned Opcode) {
7524 return Opcode == XRESLDTRK;
7525}
7526
7527bool isAESENC256KL(unsigned Opcode) {
7528 return Opcode == AESENC256KL;
7529}
7530
7531bool isVGATHERDPD(unsigned Opcode) {
7532 switch (Opcode) {
7533 case VGATHERDPDYrm:
7534 case VGATHERDPDZ128rm:
7535 case VGATHERDPDZ256rm:
7536 case VGATHERDPDZrm:
7537 case VGATHERDPDrm:
7538 return true;
7539 }
7540 return false;
7541}
7542
7543bool isHRESET(unsigned Opcode) {
7544 return Opcode == HRESET;
7545}
7546
7547bool isVFMSUBADD231PD(unsigned Opcode) {
7548 switch (Opcode) {
7549 case VFMSUBADD231PDYm:
7550 case VFMSUBADD231PDYr:
7551 case VFMSUBADD231PDZ128m:
7552 case VFMSUBADD231PDZ128mb:
7553 case VFMSUBADD231PDZ128mbk:
7554 case VFMSUBADD231PDZ128mbkz:
7555 case VFMSUBADD231PDZ128mk:
7556 case VFMSUBADD231PDZ128mkz:
7557 case VFMSUBADD231PDZ128r:
7558 case VFMSUBADD231PDZ128rk:
7559 case VFMSUBADD231PDZ128rkz:
7560 case VFMSUBADD231PDZ256m:
7561 case VFMSUBADD231PDZ256mb:
7562 case VFMSUBADD231PDZ256mbk:
7563 case VFMSUBADD231PDZ256mbkz:
7564 case VFMSUBADD231PDZ256mk:
7565 case VFMSUBADD231PDZ256mkz:
7566 case VFMSUBADD231PDZ256r:
7567 case VFMSUBADD231PDZ256rk:
7568 case VFMSUBADD231PDZ256rkz:
7569 case VFMSUBADD231PDZm:
7570 case VFMSUBADD231PDZmb:
7571 case VFMSUBADD231PDZmbk:
7572 case VFMSUBADD231PDZmbkz:
7573 case VFMSUBADD231PDZmk:
7574 case VFMSUBADD231PDZmkz:
7575 case VFMSUBADD231PDZr:
7576 case VFMSUBADD231PDZrb:
7577 case VFMSUBADD231PDZrbk:
7578 case VFMSUBADD231PDZrbkz:
7579 case VFMSUBADD231PDZrk:
7580 case VFMSUBADD231PDZrkz:
7581 case VFMSUBADD231PDm:
7582 case VFMSUBADD231PDr:
7583 return true;
7584 }
7585 return false;
7586}
7587
7588bool isVFRCZSS(unsigned Opcode) {
7589 switch (Opcode) {
7590 case VFRCZSSrm:
7591 case VFRCZSSrr:
7592 return true;
7593 }
7594 return false;
7595}
7596
7597bool isMINPS(unsigned Opcode) {
7598 switch (Opcode) {
7599 case MINPSrm:
7600 case MINPSrr:
7601 return true;
7602 }
7603 return false;
7604}
7605
7606bool isFPREM1(unsigned Opcode) {
7607 return Opcode == FPREM1;
7608}
7609
7610bool isVPCMPUB(unsigned Opcode) {
7611 switch (Opcode) {
7612 case VPCMPUBZ128rmi:
7613 case VPCMPUBZ128rmik:
7614 case VPCMPUBZ128rri:
7615 case VPCMPUBZ128rrik:
7616 case VPCMPUBZ256rmi:
7617 case VPCMPUBZ256rmik:
7618 case VPCMPUBZ256rri:
7619 case VPCMPUBZ256rrik:
7620 case VPCMPUBZrmi:
7621 case VPCMPUBZrmik:
7622 case VPCMPUBZrri:
7623 case VPCMPUBZrrik:
7624 return true;
7625 }
7626 return false;
7627}
7628
7629bool isVSQRTPD(unsigned Opcode) {
7630 switch (Opcode) {
7631 case VSQRTPDYm:
7632 case VSQRTPDYr:
7633 case VSQRTPDZ128m:
7634 case VSQRTPDZ128mb:
7635 case VSQRTPDZ128mbk:
7636 case VSQRTPDZ128mbkz:
7637 case VSQRTPDZ128mk:
7638 case VSQRTPDZ128mkz:
7639 case VSQRTPDZ128r:
7640 case VSQRTPDZ128rk:
7641 case VSQRTPDZ128rkz:
7642 case VSQRTPDZ256m:
7643 case VSQRTPDZ256mb:
7644 case VSQRTPDZ256mbk:
7645 case VSQRTPDZ256mbkz:
7646 case VSQRTPDZ256mk:
7647 case VSQRTPDZ256mkz:
7648 case VSQRTPDZ256r:
7649 case VSQRTPDZ256rk:
7650 case VSQRTPDZ256rkz:
7651 case VSQRTPDZm:
7652 case VSQRTPDZmb:
7653 case VSQRTPDZmbk:
7654 case VSQRTPDZmbkz:
7655 case VSQRTPDZmk:
7656 case VSQRTPDZmkz:
7657 case VSQRTPDZr:
7658 case VSQRTPDZrb:
7659 case VSQRTPDZrbk:
7660 case VSQRTPDZrbkz:
7661 case VSQRTPDZrk:
7662 case VSQRTPDZrkz:
7663 case VSQRTPDm:
7664 case VSQRTPDr:
7665 return true;
7666 }
7667 return false;
7668}
7669
7670bool isVFRCZPS(unsigned Opcode) {
7671 switch (Opcode) {
7672 case VFRCZPSYrm:
7673 case VFRCZPSYrr:
7674 case VFRCZPSrm:
7675 case VFRCZPSrr:
7676 return true;
7677 }
7678 return false;
7679}
7680
7681bool isVFNMADD213SS(unsigned Opcode) {
7682 switch (Opcode) {
7683 case VFNMADD213SSZm_Int:
7684 case VFNMADD213SSZmk_Int:
7685 case VFNMADD213SSZmkz_Int:
7686 case VFNMADD213SSZr_Int:
7687 case VFNMADD213SSZrb_Int:
7688 case VFNMADD213SSZrbk_Int:
7689 case VFNMADD213SSZrbkz_Int:
7690 case VFNMADD213SSZrk_Int:
7691 case VFNMADD213SSZrkz_Int:
7692 case VFNMADD213SSm_Int:
7693 case VFNMADD213SSr_Int:
7694 return true;
7695 }
7696 return false;
7697}
7698
7699bool isVPMOVDW(unsigned Opcode) {
7700 switch (Opcode) {
7701 case VPMOVDWZ128mr:
7702 case VPMOVDWZ128mrk:
7703 case VPMOVDWZ128rr:
7704 case VPMOVDWZ128rrk:
7705 case VPMOVDWZ128rrkz:
7706 case VPMOVDWZ256mr:
7707 case VPMOVDWZ256mrk:
7708 case VPMOVDWZ256rr:
7709 case VPMOVDWZ256rrk:
7710 case VPMOVDWZ256rrkz:
7711 case VPMOVDWZmr:
7712 case VPMOVDWZmrk:
7713 case VPMOVDWZrr:
7714 case VPMOVDWZrrk:
7715 case VPMOVDWZrrkz:
7716 return true;
7717 }
7718 return false;
7719}
7720
7721bool isVCVTPH2HF8S(unsigned Opcode) {
7722 switch (Opcode) {
7723 case VCVTPH2HF8SZ128rm:
7724 case VCVTPH2HF8SZ128rmb:
7725 case VCVTPH2HF8SZ128rmbk:
7726 case VCVTPH2HF8SZ128rmbkz:
7727 case VCVTPH2HF8SZ128rmk:
7728 case VCVTPH2HF8SZ128rmkz:
7729 case VCVTPH2HF8SZ128rr:
7730 case VCVTPH2HF8SZ128rrk:
7731 case VCVTPH2HF8SZ128rrkz:
7732 case VCVTPH2HF8SZ256rm:
7733 case VCVTPH2HF8SZ256rmb:
7734 case VCVTPH2HF8SZ256rmbk:
7735 case VCVTPH2HF8SZ256rmbkz:
7736 case VCVTPH2HF8SZ256rmk:
7737 case VCVTPH2HF8SZ256rmkz:
7738 case VCVTPH2HF8SZ256rr:
7739 case VCVTPH2HF8SZ256rrk:
7740 case VCVTPH2HF8SZ256rrkz:
7741 case VCVTPH2HF8SZrm:
7742 case VCVTPH2HF8SZrmb:
7743 case VCVTPH2HF8SZrmbk:
7744 case VCVTPH2HF8SZrmbkz:
7745 case VCVTPH2HF8SZrmk:
7746 case VCVTPH2HF8SZrmkz:
7747 case VCVTPH2HF8SZrr:
7748 case VCVTPH2HF8SZrrk:
7749 case VCVTPH2HF8SZrrkz:
7750 return true;
7751 }
7752 return false;
7753}
7754
7755bool isVPSHRDVQ(unsigned Opcode) {
7756 switch (Opcode) {
7757 case VPSHRDVQZ128m:
7758 case VPSHRDVQZ128mb:
7759 case VPSHRDVQZ128mbk:
7760 case VPSHRDVQZ128mbkz:
7761 case VPSHRDVQZ128mk:
7762 case VPSHRDVQZ128mkz:
7763 case VPSHRDVQZ128r:
7764 case VPSHRDVQZ128rk:
7765 case VPSHRDVQZ128rkz:
7766 case VPSHRDVQZ256m:
7767 case VPSHRDVQZ256mb:
7768 case VPSHRDVQZ256mbk:
7769 case VPSHRDVQZ256mbkz:
7770 case VPSHRDVQZ256mk:
7771 case VPSHRDVQZ256mkz:
7772 case VPSHRDVQZ256r:
7773 case VPSHRDVQZ256rk:
7774 case VPSHRDVQZ256rkz:
7775 case VPSHRDVQZm:
7776 case VPSHRDVQZmb:
7777 case VPSHRDVQZmbk:
7778 case VPSHRDVQZmbkz:
7779 case VPSHRDVQZmk:
7780 case VPSHRDVQZmkz:
7781 case VPSHRDVQZr:
7782 case VPSHRDVQZrk:
7783 case VPSHRDVQZrkz:
7784 return true;
7785 }
7786 return false;
7787}
7788
7789bool isVBROADCASTSD(unsigned Opcode) {
7790 switch (Opcode) {
7791 case VBROADCASTSDYrm:
7792 case VBROADCASTSDYrr:
7793 case VBROADCASTSDZ256rm:
7794 case VBROADCASTSDZ256rmk:
7795 case VBROADCASTSDZ256rmkz:
7796 case VBROADCASTSDZ256rr:
7797 case VBROADCASTSDZ256rrk:
7798 case VBROADCASTSDZ256rrkz:
7799 case VBROADCASTSDZrm:
7800 case VBROADCASTSDZrmk:
7801 case VBROADCASTSDZrmkz:
7802 case VBROADCASTSDZrr:
7803 case VBROADCASTSDZrrk:
7804 case VBROADCASTSDZrrkz:
7805 return true;
7806 }
7807 return false;
7808}
7809
7810bool isVSHUFPD(unsigned Opcode) {
7811 switch (Opcode) {
7812 case VSHUFPDYrmi:
7813 case VSHUFPDYrri:
7814 case VSHUFPDZ128rmbi:
7815 case VSHUFPDZ128rmbik:
7816 case VSHUFPDZ128rmbikz:
7817 case VSHUFPDZ128rmi:
7818 case VSHUFPDZ128rmik:
7819 case VSHUFPDZ128rmikz:
7820 case VSHUFPDZ128rri:
7821 case VSHUFPDZ128rrik:
7822 case VSHUFPDZ128rrikz:
7823 case VSHUFPDZ256rmbi:
7824 case VSHUFPDZ256rmbik:
7825 case VSHUFPDZ256rmbikz:
7826 case VSHUFPDZ256rmi:
7827 case VSHUFPDZ256rmik:
7828 case VSHUFPDZ256rmikz:
7829 case VSHUFPDZ256rri:
7830 case VSHUFPDZ256rrik:
7831 case VSHUFPDZ256rrikz:
7832 case VSHUFPDZrmbi:
7833 case VSHUFPDZrmbik:
7834 case VSHUFPDZrmbikz:
7835 case VSHUFPDZrmi:
7836 case VSHUFPDZrmik:
7837 case VSHUFPDZrmikz:
7838 case VSHUFPDZrri:
7839 case VSHUFPDZrrik:
7840 case VSHUFPDZrrikz:
7841 case VSHUFPDrmi:
7842 case VSHUFPDrri:
7843 return true;
7844 }
7845 return false;
7846}
7847
7848bool isVPSUBSW(unsigned Opcode) {
7849 switch (Opcode) {
7850 case VPSUBSWYrm:
7851 case VPSUBSWYrr:
7852 case VPSUBSWZ128rm:
7853 case VPSUBSWZ128rmk:
7854 case VPSUBSWZ128rmkz:
7855 case VPSUBSWZ128rr:
7856 case VPSUBSWZ128rrk:
7857 case VPSUBSWZ128rrkz:
7858 case VPSUBSWZ256rm:
7859 case VPSUBSWZ256rmk:
7860 case VPSUBSWZ256rmkz:
7861 case VPSUBSWZ256rr:
7862 case VPSUBSWZ256rrk:
7863 case VPSUBSWZ256rrkz:
7864 case VPSUBSWZrm:
7865 case VPSUBSWZrmk:
7866 case VPSUBSWZrmkz:
7867 case VPSUBSWZrr:
7868 case VPSUBSWZrrk:
7869 case VPSUBSWZrrkz:
7870 case VPSUBSWrm:
7871 case VPSUBSWrr:
7872 return true;
7873 }
7874 return false;
7875}
7876
7877bool isKUNPCKBW(unsigned Opcode) {
7878 return Opcode == KUNPCKBWkk;
7879}
7880
7881bool isVPBLENDD(unsigned Opcode) {
7882 switch (Opcode) {
7883 case VPBLENDDYrmi:
7884 case VPBLENDDYrri:
7885 case VPBLENDDrmi:
7886 case VPBLENDDrri:
7887 return true;
7888 }
7889 return false;
7890}
7891
7892bool isUNPCKHPD(unsigned Opcode) {
7893 switch (Opcode) {
7894 case UNPCKHPDrm:
7895 case UNPCKHPDrr:
7896 return true;
7897 }
7898 return false;
7899}
7900
7901bool isVFNMADD231SD(unsigned Opcode) {
7902 switch (Opcode) {
7903 case VFNMADD231SDZm_Int:
7904 case VFNMADD231SDZmk_Int:
7905 case VFNMADD231SDZmkz_Int:
7906 case VFNMADD231SDZr_Int:
7907 case VFNMADD231SDZrb_Int:
7908 case VFNMADD231SDZrbk_Int:
7909 case VFNMADD231SDZrbkz_Int:
7910 case VFNMADD231SDZrk_Int:
7911 case VFNMADD231SDZrkz_Int:
7912 case VFNMADD231SDm_Int:
7913 case VFNMADD231SDr_Int:
7914 return true;
7915 }
7916 return false;
7917}
7918
7919bool isVPBROADCASTMW2D(unsigned Opcode) {
7920 switch (Opcode) {
7921 case VPBROADCASTMW2DZ128rr:
7922 case VPBROADCASTMW2DZ256rr:
7923 case VPBROADCASTMW2DZrr:
7924 return true;
7925 }
7926 return false;
7927}
7928
7929bool isVPMULTISHIFTQB(unsigned Opcode) {
7930 switch (Opcode) {
7931 case VPMULTISHIFTQBZ128rm:
7932 case VPMULTISHIFTQBZ128rmb:
7933 case VPMULTISHIFTQBZ128rmbk:
7934 case VPMULTISHIFTQBZ128rmbkz:
7935 case VPMULTISHIFTQBZ128rmk:
7936 case VPMULTISHIFTQBZ128rmkz:
7937 case VPMULTISHIFTQBZ128rr:
7938 case VPMULTISHIFTQBZ128rrk:
7939 case VPMULTISHIFTQBZ128rrkz:
7940 case VPMULTISHIFTQBZ256rm:
7941 case VPMULTISHIFTQBZ256rmb:
7942 case VPMULTISHIFTQBZ256rmbk:
7943 case VPMULTISHIFTQBZ256rmbkz:
7944 case VPMULTISHIFTQBZ256rmk:
7945 case VPMULTISHIFTQBZ256rmkz:
7946 case VPMULTISHIFTQBZ256rr:
7947 case VPMULTISHIFTQBZ256rrk:
7948 case VPMULTISHIFTQBZ256rrkz:
7949 case VPMULTISHIFTQBZrm:
7950 case VPMULTISHIFTQBZrmb:
7951 case VPMULTISHIFTQBZrmbk:
7952 case VPMULTISHIFTQBZrmbkz:
7953 case VPMULTISHIFTQBZrmk:
7954 case VPMULTISHIFTQBZrmkz:
7955 case VPMULTISHIFTQBZrr:
7956 case VPMULTISHIFTQBZrrk:
7957 case VPMULTISHIFTQBZrrkz:
7958 return true;
7959 }
7960 return false;
7961}
7962
7963bool isVP2INTERSECTQ(unsigned Opcode) {
7964 switch (Opcode) {
7965 case VP2INTERSECTQZ128rm:
7966 case VP2INTERSECTQZ128rmb:
7967 case VP2INTERSECTQZ128rr:
7968 case VP2INTERSECTQZ256rm:
7969 case VP2INTERSECTQZ256rmb:
7970 case VP2INTERSECTQZ256rr:
7971 case VP2INTERSECTQZrm:
7972 case VP2INTERSECTQZrmb:
7973 case VP2INTERSECTQZrr:
7974 return true;
7975 }
7976 return false;
7977}
7978
7979bool isVFNMSUB132BF16(unsigned Opcode) {
7980 switch (Opcode) {
7981 case VFNMSUB132BF16Z128m:
7982 case VFNMSUB132BF16Z128mb:
7983 case VFNMSUB132BF16Z128mbk:
7984 case VFNMSUB132BF16Z128mbkz:
7985 case VFNMSUB132BF16Z128mk:
7986 case VFNMSUB132BF16Z128mkz:
7987 case VFNMSUB132BF16Z128r:
7988 case VFNMSUB132BF16Z128rk:
7989 case VFNMSUB132BF16Z128rkz:
7990 case VFNMSUB132BF16Z256m:
7991 case VFNMSUB132BF16Z256mb:
7992 case VFNMSUB132BF16Z256mbk:
7993 case VFNMSUB132BF16Z256mbkz:
7994 case VFNMSUB132BF16Z256mk:
7995 case VFNMSUB132BF16Z256mkz:
7996 case VFNMSUB132BF16Z256r:
7997 case VFNMSUB132BF16Z256rk:
7998 case VFNMSUB132BF16Z256rkz:
7999 case VFNMSUB132BF16Zm:
8000 case VFNMSUB132BF16Zmb:
8001 case VFNMSUB132BF16Zmbk:
8002 case VFNMSUB132BF16Zmbkz:
8003 case VFNMSUB132BF16Zmk:
8004 case VFNMSUB132BF16Zmkz:
8005 case VFNMSUB132BF16Zr:
8006 case VFNMSUB132BF16Zrk:
8007 case VFNMSUB132BF16Zrkz:
8008 return true;
8009 }
8010 return false;
8011}
8012
8013bool isVFMADD213BF16(unsigned Opcode) {
8014 switch (Opcode) {
8015 case VFMADD213BF16Z128m:
8016 case VFMADD213BF16Z128mb:
8017 case VFMADD213BF16Z128mbk:
8018 case VFMADD213BF16Z128mbkz:
8019 case VFMADD213BF16Z128mk:
8020 case VFMADD213BF16Z128mkz:
8021 case VFMADD213BF16Z128r:
8022 case VFMADD213BF16Z128rk:
8023 case VFMADD213BF16Z128rkz:
8024 case VFMADD213BF16Z256m:
8025 case VFMADD213BF16Z256mb:
8026 case VFMADD213BF16Z256mbk:
8027 case VFMADD213BF16Z256mbkz:
8028 case VFMADD213BF16Z256mk:
8029 case VFMADD213BF16Z256mkz:
8030 case VFMADD213BF16Z256r:
8031 case VFMADD213BF16Z256rk:
8032 case VFMADD213BF16Z256rkz:
8033 case VFMADD213BF16Zm:
8034 case VFMADD213BF16Zmb:
8035 case VFMADD213BF16Zmbk:
8036 case VFMADD213BF16Zmbkz:
8037 case VFMADD213BF16Zmk:
8038 case VFMADD213BF16Zmkz:
8039 case VFMADD213BF16Zr:
8040 case VFMADD213BF16Zrk:
8041 case VFMADD213BF16Zrkz:
8042 return true;
8043 }
8044 return false;
8045}
8046
8047bool isVPUNPCKHWD(unsigned Opcode) {
8048 switch (Opcode) {
8049 case VPUNPCKHWDYrm:
8050 case VPUNPCKHWDYrr:
8051 case VPUNPCKHWDZ128rm:
8052 case VPUNPCKHWDZ128rmk:
8053 case VPUNPCKHWDZ128rmkz:
8054 case VPUNPCKHWDZ128rr:
8055 case VPUNPCKHWDZ128rrk:
8056 case VPUNPCKHWDZ128rrkz:
8057 case VPUNPCKHWDZ256rm:
8058 case VPUNPCKHWDZ256rmk:
8059 case VPUNPCKHWDZ256rmkz:
8060 case VPUNPCKHWDZ256rr:
8061 case VPUNPCKHWDZ256rrk:
8062 case VPUNPCKHWDZ256rrkz:
8063 case VPUNPCKHWDZrm:
8064 case VPUNPCKHWDZrmk:
8065 case VPUNPCKHWDZrmkz:
8066 case VPUNPCKHWDZrr:
8067 case VPUNPCKHWDZrrk:
8068 case VPUNPCKHWDZrrkz:
8069 case VPUNPCKHWDrm:
8070 case VPUNPCKHWDrr:
8071 return true;
8072 }
8073 return false;
8074}
8075
8076bool isVPERM2F128(unsigned Opcode) {
8077 switch (Opcode) {
8078 case VPERM2F128rmi:
8079 case VPERM2F128rri:
8080 return true;
8081 }
8082 return false;
8083}
8084
8085bool isINSD(unsigned Opcode) {
8086 return Opcode == INSL;
8087}
8088
8089bool isLFS(unsigned Opcode) {
8090 switch (Opcode) {
8091 case LFS16rm:
8092 case LFS32rm:
8093 case LFS64rm:
8094 return true;
8095 }
8096 return false;
8097}
8098
8099bool isFMULP(unsigned Opcode) {
8100 return Opcode == MUL_FPrST0;
8101}
8102
8103bool isCWD(unsigned Opcode) {
8104 return Opcode == CWD;
8105}
8106
8107bool isVDIVSS(unsigned Opcode) {
8108 switch (Opcode) {
8109 case VDIVSSZrm_Int:
8110 case VDIVSSZrmk_Int:
8111 case VDIVSSZrmkz_Int:
8112 case VDIVSSZrr_Int:
8113 case VDIVSSZrrb_Int:
8114 case VDIVSSZrrbk_Int:
8115 case VDIVSSZrrbkz_Int:
8116 case VDIVSSZrrk_Int:
8117 case VDIVSSZrrkz_Int:
8118 case VDIVSSrm_Int:
8119 case VDIVSSrr_Int:
8120 return true;
8121 }
8122 return false;
8123}
8124
8125bool isVPSRLQ(unsigned Opcode) {
8126 switch (Opcode) {
8127 case VPSRLQYri:
8128 case VPSRLQYrm:
8129 case VPSRLQYrr:
8130 case VPSRLQZ128mbi:
8131 case VPSRLQZ128mbik:
8132 case VPSRLQZ128mbikz:
8133 case VPSRLQZ128mi:
8134 case VPSRLQZ128mik:
8135 case VPSRLQZ128mikz:
8136 case VPSRLQZ128ri:
8137 case VPSRLQZ128rik:
8138 case VPSRLQZ128rikz:
8139 case VPSRLQZ128rm:
8140 case VPSRLQZ128rmk:
8141 case VPSRLQZ128rmkz:
8142 case VPSRLQZ128rr:
8143 case VPSRLQZ128rrk:
8144 case VPSRLQZ128rrkz:
8145 case VPSRLQZ256mbi:
8146 case VPSRLQZ256mbik:
8147 case VPSRLQZ256mbikz:
8148 case VPSRLQZ256mi:
8149 case VPSRLQZ256mik:
8150 case VPSRLQZ256mikz:
8151 case VPSRLQZ256ri:
8152 case VPSRLQZ256rik:
8153 case VPSRLQZ256rikz:
8154 case VPSRLQZ256rm:
8155 case VPSRLQZ256rmk:
8156 case VPSRLQZ256rmkz:
8157 case VPSRLQZ256rr:
8158 case VPSRLQZ256rrk:
8159 case VPSRLQZ256rrkz:
8160 case VPSRLQZmbi:
8161 case VPSRLQZmbik:
8162 case VPSRLQZmbikz:
8163 case VPSRLQZmi:
8164 case VPSRLQZmik:
8165 case VPSRLQZmikz:
8166 case VPSRLQZri:
8167 case VPSRLQZrik:
8168 case VPSRLQZrikz:
8169 case VPSRLQZrm:
8170 case VPSRLQZrmk:
8171 case VPSRLQZrmkz:
8172 case VPSRLQZrr:
8173 case VPSRLQZrrk:
8174 case VPSRLQZrrkz:
8175 case VPSRLQri:
8176 case VPSRLQrm:
8177 case VPSRLQrr:
8178 return true;
8179 }
8180 return false;
8181}
8182
8183bool isFSQRT(unsigned Opcode) {
8184 return Opcode == SQRT_F;
8185}
8186
8187bool isJRCXZ(unsigned Opcode) {
8188 return Opcode == JRCXZ;
8189}
8190
8191bool isVPMOVMSKB(unsigned Opcode) {
8192 switch (Opcode) {
8193 case VPMOVMSKBYrr:
8194 case VPMOVMSKBrr:
8195 return true;
8196 }
8197 return false;
8198}
8199
8200bool isAESDEC256KL(unsigned Opcode) {
8201 return Opcode == AESDEC256KL;
8202}
8203
8204bool isFLDENV(unsigned Opcode) {
8205 return Opcode == FLDENVm;
8206}
8207
8208bool isVPHSUBWD(unsigned Opcode) {
8209 switch (Opcode) {
8210 case VPHSUBWDrm:
8211 case VPHSUBWDrr:
8212 return true;
8213 }
8214 return false;
8215}
8216
8217bool isWBNOINVD(unsigned Opcode) {
8218 return Opcode == WBNOINVD;
8219}
8220
8221bool isVEXPANDPD(unsigned Opcode) {
8222 switch (Opcode) {
8223 case VEXPANDPDZ128rm:
8224 case VEXPANDPDZ128rmk:
8225 case VEXPANDPDZ128rmkz:
8226 case VEXPANDPDZ128rr:
8227 case VEXPANDPDZ128rrk:
8228 case VEXPANDPDZ128rrkz:
8229 case VEXPANDPDZ256rm:
8230 case VEXPANDPDZ256rmk:
8231 case VEXPANDPDZ256rmkz:
8232 case VEXPANDPDZ256rr:
8233 case VEXPANDPDZ256rrk:
8234 case VEXPANDPDZ256rrkz:
8235 case VEXPANDPDZrm:
8236 case VEXPANDPDZrmk:
8237 case VEXPANDPDZrmkz:
8238 case VEXPANDPDZrr:
8239 case VEXPANDPDZrrk:
8240 case VEXPANDPDZrrkz:
8241 return true;
8242 }
8243 return false;
8244}
8245
8246bool isFYL2XP1(unsigned Opcode) {
8247 return Opcode == FYL2XP1;
8248}
8249
8250bool isPREFETCHT2(unsigned Opcode) {
8251 return Opcode == PREFETCHT2;
8252}
8253
8254bool isVPDPBSUDS(unsigned Opcode) {
8255 switch (Opcode) {
8256 case VPDPBSUDSYrm:
8257 case VPDPBSUDSYrr:
8258 case VPDPBSUDSZ128rm:
8259 case VPDPBSUDSZ128rmb:
8260 case VPDPBSUDSZ128rmbk:
8261 case VPDPBSUDSZ128rmbkz:
8262 case VPDPBSUDSZ128rmk:
8263 case VPDPBSUDSZ128rmkz:
8264 case VPDPBSUDSZ128rr:
8265 case VPDPBSUDSZ128rrk:
8266 case VPDPBSUDSZ128rrkz:
8267 case VPDPBSUDSZ256rm:
8268 case VPDPBSUDSZ256rmb:
8269 case VPDPBSUDSZ256rmbk:
8270 case VPDPBSUDSZ256rmbkz:
8271 case VPDPBSUDSZ256rmk:
8272 case VPDPBSUDSZ256rmkz:
8273 case VPDPBSUDSZ256rr:
8274 case VPDPBSUDSZ256rrk:
8275 case VPDPBSUDSZ256rrkz:
8276 case VPDPBSUDSZrm:
8277 case VPDPBSUDSZrmb:
8278 case VPDPBSUDSZrmbk:
8279 case VPDPBSUDSZrmbkz:
8280 case VPDPBSUDSZrmk:
8281 case VPDPBSUDSZrmkz:
8282 case VPDPBSUDSZrr:
8283 case VPDPBSUDSZrrk:
8284 case VPDPBSUDSZrrkz:
8285 case VPDPBSUDSrm:
8286 case VPDPBSUDSrr:
8287 return true;
8288 }
8289 return false;
8290}
8291
8292bool isVSHA512MSG2(unsigned Opcode) {
8293 return Opcode == VSHA512MSG2rr;
8294}
8295
8296bool isPMULHUW(unsigned Opcode) {
8297 switch (Opcode) {
8298 case MMX_PMULHUWrm:
8299 case MMX_PMULHUWrr:
8300 case PMULHUWrm:
8301 case PMULHUWrr:
8302 return true;
8303 }
8304 return false;
8305}
8306
8307bool isKANDNB(unsigned Opcode) {
8308 return Opcode == KANDNBkk;
8309}
8310
8311bool isVCVTUW2PH(unsigned Opcode) {
8312 switch (Opcode) {
8313 case VCVTUW2PHZ128rm:
8314 case VCVTUW2PHZ128rmb:
8315 case VCVTUW2PHZ128rmbk:
8316 case VCVTUW2PHZ128rmbkz:
8317 case VCVTUW2PHZ128rmk:
8318 case VCVTUW2PHZ128rmkz:
8319 case VCVTUW2PHZ128rr:
8320 case VCVTUW2PHZ128rrk:
8321 case VCVTUW2PHZ128rrkz:
8322 case VCVTUW2PHZ256rm:
8323 case VCVTUW2PHZ256rmb:
8324 case VCVTUW2PHZ256rmbk:
8325 case VCVTUW2PHZ256rmbkz:
8326 case VCVTUW2PHZ256rmk:
8327 case VCVTUW2PHZ256rmkz:
8328 case VCVTUW2PHZ256rr:
8329 case VCVTUW2PHZ256rrk:
8330 case VCVTUW2PHZ256rrkz:
8331 case VCVTUW2PHZrm:
8332 case VCVTUW2PHZrmb:
8333 case VCVTUW2PHZrmbk:
8334 case VCVTUW2PHZrmbkz:
8335 case VCVTUW2PHZrmk:
8336 case VCVTUW2PHZrmkz:
8337 case VCVTUW2PHZrr:
8338 case VCVTUW2PHZrrb:
8339 case VCVTUW2PHZrrbk:
8340 case VCVTUW2PHZrrbkz:
8341 case VCVTUW2PHZrrk:
8342 case VCVTUW2PHZrrkz:
8343 return true;
8344 }
8345 return false;
8346}
8347
8348bool isAESDECWIDE256KL(unsigned Opcode) {
8349 return Opcode == AESDECWIDE256KL;
8350}
8351
8352bool isVPGATHERDD(unsigned Opcode) {
8353 switch (Opcode) {
8354 case VPGATHERDDYrm:
8355 case VPGATHERDDZ128rm:
8356 case VPGATHERDDZ256rm:
8357 case VPGATHERDDZrm:
8358 case VPGATHERDDrm:
8359 return true;
8360 }
8361 return false;
8362}
8363
8364bool isVREDUCESH(unsigned Opcode) {
8365 switch (Opcode) {
8366 case VREDUCESHZrmi:
8367 case VREDUCESHZrmik:
8368 case VREDUCESHZrmikz:
8369 case VREDUCESHZrri:
8370 case VREDUCESHZrrib:
8371 case VREDUCESHZrribk:
8372 case VREDUCESHZrribkz:
8373 case VREDUCESHZrrik:
8374 case VREDUCESHZrrikz:
8375 return true;
8376 }
8377 return false;
8378}
8379
8380bool isPOPFQ(unsigned Opcode) {
8381 return Opcode == POPF64;
8382}
8383
8384bool isPAVGUSB(unsigned Opcode) {
8385 switch (Opcode) {
8386 case PAVGUSBrm:
8387 case PAVGUSBrr:
8388 return true;
8389 }
8390 return false;
8391}
8392
8393bool isVALIGND(unsigned Opcode) {
8394 switch (Opcode) {
8395 case VALIGNDZ128rmbi:
8396 case VALIGNDZ128rmbik:
8397 case VALIGNDZ128rmbikz:
8398 case VALIGNDZ128rmi:
8399 case VALIGNDZ128rmik:
8400 case VALIGNDZ128rmikz:
8401 case VALIGNDZ128rri:
8402 case VALIGNDZ128rrik:
8403 case VALIGNDZ128rrikz:
8404 case VALIGNDZ256rmbi:
8405 case VALIGNDZ256rmbik:
8406 case VALIGNDZ256rmbikz:
8407 case VALIGNDZ256rmi:
8408 case VALIGNDZ256rmik:
8409 case VALIGNDZ256rmikz:
8410 case VALIGNDZ256rri:
8411 case VALIGNDZ256rrik:
8412 case VALIGNDZ256rrikz:
8413 case VALIGNDZrmbi:
8414 case VALIGNDZrmbik:
8415 case VALIGNDZrmbikz:
8416 case VALIGNDZrmi:
8417 case VALIGNDZrmik:
8418 case VALIGNDZrmikz:
8419 case VALIGNDZrri:
8420 case VALIGNDZrrik:
8421 case VALIGNDZrrikz:
8422 return true;
8423 }
8424 return false;
8425}
8426
8427bool isVPHMINPOSUW(unsigned Opcode) {
8428 switch (Opcode) {
8429 case VPHMINPOSUWrm:
8430 case VPHMINPOSUWrr:
8431 return true;
8432 }
8433 return false;
8434}
8435
8436bool isLIDTD(unsigned Opcode) {
8437 return Opcode == LIDT32m;
8438}
8439
8440bool isVPERMT2PD(unsigned Opcode) {
8441 switch (Opcode) {
8442 case VPERMT2PDZ128rm:
8443 case VPERMT2PDZ128rmb:
8444 case VPERMT2PDZ128rmbk:
8445 case VPERMT2PDZ128rmbkz:
8446 case VPERMT2PDZ128rmk:
8447 case VPERMT2PDZ128rmkz:
8448 case VPERMT2PDZ128rr:
8449 case VPERMT2PDZ128rrk:
8450 case VPERMT2PDZ128rrkz:
8451 case VPERMT2PDZ256rm:
8452 case VPERMT2PDZ256rmb:
8453 case VPERMT2PDZ256rmbk:
8454 case VPERMT2PDZ256rmbkz:
8455 case VPERMT2PDZ256rmk:
8456 case VPERMT2PDZ256rmkz:
8457 case VPERMT2PDZ256rr:
8458 case VPERMT2PDZ256rrk:
8459 case VPERMT2PDZ256rrkz:
8460 case VPERMT2PDZrm:
8461 case VPERMT2PDZrmb:
8462 case VPERMT2PDZrmbk:
8463 case VPERMT2PDZrmbkz:
8464 case VPERMT2PDZrmk:
8465 case VPERMT2PDZrmkz:
8466 case VPERMT2PDZrr:
8467 case VPERMT2PDZrrk:
8468 case VPERMT2PDZrrkz:
8469 return true;
8470 }
8471 return false;
8472}
8473
8474bool isVMLAUNCH(unsigned Opcode) {
8475 return Opcode == VMLAUNCH;
8476}
8477
8478bool isVPXORQ(unsigned Opcode) {
8479 switch (Opcode) {
8480 case VPXORQZ128rm:
8481 case VPXORQZ128rmb:
8482 case VPXORQZ128rmbk:
8483 case VPXORQZ128rmbkz:
8484 case VPXORQZ128rmk:
8485 case VPXORQZ128rmkz:
8486 case VPXORQZ128rr:
8487 case VPXORQZ128rrk:
8488 case VPXORQZ128rrkz:
8489 case VPXORQZ256rm:
8490 case VPXORQZ256rmb:
8491 case VPXORQZ256rmbk:
8492 case VPXORQZ256rmbkz:
8493 case VPXORQZ256rmk:
8494 case VPXORQZ256rmkz:
8495 case VPXORQZ256rr:
8496 case VPXORQZ256rrk:
8497 case VPXORQZ256rrkz:
8498 case VPXORQZrm:
8499 case VPXORQZrmb:
8500 case VPXORQZrmbk:
8501 case VPXORQZrmbkz:
8502 case VPXORQZrmk:
8503 case VPXORQZrmkz:
8504 case VPXORQZrr:
8505 case VPXORQZrrk:
8506 case VPXORQZrrkz:
8507 return true;
8508 }
8509 return false;
8510}
8511
8512bool isMOVNTDQ(unsigned Opcode) {
8513 return Opcode == MOVNTDQmr;
8514}
8515
8516bool isPOP2P(unsigned Opcode) {
8517 return Opcode == POP2P;
8518}
8519
8520bool isVADDPD(unsigned Opcode) {
8521 switch (Opcode) {
8522 case VADDPDYrm:
8523 case VADDPDYrr:
8524 case VADDPDZ128rm:
8525 case VADDPDZ128rmb:
8526 case VADDPDZ128rmbk:
8527 case VADDPDZ128rmbkz:
8528 case VADDPDZ128rmk:
8529 case VADDPDZ128rmkz:
8530 case VADDPDZ128rr:
8531 case VADDPDZ128rrk:
8532 case VADDPDZ128rrkz:
8533 case VADDPDZ256rm:
8534 case VADDPDZ256rmb:
8535 case VADDPDZ256rmbk:
8536 case VADDPDZ256rmbkz:
8537 case VADDPDZ256rmk:
8538 case VADDPDZ256rmkz:
8539 case VADDPDZ256rr:
8540 case VADDPDZ256rrk:
8541 case VADDPDZ256rrkz:
8542 case VADDPDZrm:
8543 case VADDPDZrmb:
8544 case VADDPDZrmbk:
8545 case VADDPDZrmbkz:
8546 case VADDPDZrmk:
8547 case VADDPDZrmkz:
8548 case VADDPDZrr:
8549 case VADDPDZrrb:
8550 case VADDPDZrrbk:
8551 case VADDPDZrrbkz:
8552 case VADDPDZrrk:
8553 case VADDPDZrrkz:
8554 case VADDPDrm:
8555 case VADDPDrr:
8556 return true;
8557 }
8558 return false;
8559}
8560
8561bool isSMSW(unsigned Opcode) {
8562 switch (Opcode) {
8563 case SMSW16m:
8564 case SMSW16r:
8565 case SMSW32r:
8566 case SMSW64r:
8567 return true;
8568 }
8569 return false;
8570}
8571
8572bool isVEXP2PD(unsigned Opcode) {
8573 switch (Opcode) {
8574 case VEXP2PDZm:
8575 case VEXP2PDZmb:
8576 case VEXP2PDZmbk:
8577 case VEXP2PDZmbkz:
8578 case VEXP2PDZmk:
8579 case VEXP2PDZmkz:
8580 case VEXP2PDZr:
8581 case VEXP2PDZrb:
8582 case VEXP2PDZrbk:
8583 case VEXP2PDZrbkz:
8584 case VEXP2PDZrk:
8585 case VEXP2PDZrkz:
8586 return true;
8587 }
8588 return false;
8589}
8590
8591bool isPMULUDQ(unsigned Opcode) {
8592 switch (Opcode) {
8593 case MMX_PMULUDQrm:
8594 case MMX_PMULUDQrr:
8595 case PMULUDQrm:
8596 case PMULUDQrr:
8597 return true;
8598 }
8599 return false;
8600}
8601
8602bool isIRET(unsigned Opcode) {
8603 return Opcode == IRET16;
8604}
8605
8606bool isMULPS(unsigned Opcode) {
8607 switch (Opcode) {
8608 case MULPSrm:
8609 case MULPSrr:
8610 return true;
8611 }
8612 return false;
8613}
8614
8615bool isTDPBF8PS(unsigned Opcode) {
8616 return Opcode == TDPBF8PS;
8617}
8618
8619bool isVFNMSUBPD(unsigned Opcode) {
8620 switch (Opcode) {
8621 case VFNMSUBPD4Ymr:
8622 case VFNMSUBPD4Yrm:
8623 case VFNMSUBPD4Yrr:
8624 case VFNMSUBPD4Yrr_REV:
8625 case VFNMSUBPD4mr:
8626 case VFNMSUBPD4rm:
8627 case VFNMSUBPD4rr:
8628 case VFNMSUBPD4rr_REV:
8629 return true;
8630 }
8631 return false;
8632}
8633
8634bool isPHADDW(unsigned Opcode) {
8635 switch (Opcode) {
8636 case MMX_PHADDWrm:
8637 case MMX_PHADDWrr:
8638 case PHADDWrm:
8639 case PHADDWrr:
8640 return true;
8641 }
8642 return false;
8643}
8644
8645bool isRDSEED(unsigned Opcode) {
8646 switch (Opcode) {
8647 case RDSEED16r:
8648 case RDSEED32r:
8649 case RDSEED64r:
8650 return true;
8651 }
8652 return false;
8653}
8654
8655bool isVPSHLW(unsigned Opcode) {
8656 switch (Opcode) {
8657 case VPSHLWmr:
8658 case VPSHLWrm:
8659 case VPSHLWrr:
8660 case VPSHLWrr_REV:
8661 return true;
8662 }
8663 return false;
8664}
8665
8666bool isRMPUPDATE(unsigned Opcode) {
8667 return Opcode == RMPUPDATE;
8668}
8669
8670bool isVFMADD231PH(unsigned Opcode) {
8671 switch (Opcode) {
8672 case VFMADD231PHZ128m:
8673 case VFMADD231PHZ128mb:
8674 case VFMADD231PHZ128mbk:
8675 case VFMADD231PHZ128mbkz:
8676 case VFMADD231PHZ128mk:
8677 case VFMADD231PHZ128mkz:
8678 case VFMADD231PHZ128r:
8679 case VFMADD231PHZ128rk:
8680 case VFMADD231PHZ128rkz:
8681 case VFMADD231PHZ256m:
8682 case VFMADD231PHZ256mb:
8683 case VFMADD231PHZ256mbk:
8684 case VFMADD231PHZ256mbkz:
8685 case VFMADD231PHZ256mk:
8686 case VFMADD231PHZ256mkz:
8687 case VFMADD231PHZ256r:
8688 case VFMADD231PHZ256rk:
8689 case VFMADD231PHZ256rkz:
8690 case VFMADD231PHZm:
8691 case VFMADD231PHZmb:
8692 case VFMADD231PHZmbk:
8693 case VFMADD231PHZmbkz:
8694 case VFMADD231PHZmk:
8695 case VFMADD231PHZmkz:
8696 case VFMADD231PHZr:
8697 case VFMADD231PHZrb:
8698 case VFMADD231PHZrbk:
8699 case VFMADD231PHZrbkz:
8700 case VFMADD231PHZrk:
8701 case VFMADD231PHZrkz:
8702 return true;
8703 }
8704 return false;
8705}
8706
8707bool isVPSHAD(unsigned Opcode) {
8708 switch (Opcode) {
8709 case VPSHADmr:
8710 case VPSHADrm:
8711 case VPSHADrr:
8712 case VPSHADrr_REV:
8713 return true;
8714 }
8715 return false;
8716}
8717
8718bool isCLWB(unsigned Opcode) {
8719 return Opcode == CLWB;
8720}
8721
8722bool isPSUBUSB(unsigned Opcode) {
8723 switch (Opcode) {
8724 case MMX_PSUBUSBrm:
8725 case MMX_PSUBUSBrr:
8726 case PSUBUSBrm:
8727 case PSUBUSBrr:
8728 return true;
8729 }
8730 return false;
8731}
8732
8733bool isVCVTTSD2USI(unsigned Opcode) {
8734 switch (Opcode) {
8735 case VCVTTSD2USI64Zrm_Int:
8736 case VCVTTSD2USI64Zrr_Int:
8737 case VCVTTSD2USI64Zrrb_Int:
8738 case VCVTTSD2USIZrm_Int:
8739 case VCVTTSD2USIZrr_Int:
8740 case VCVTTSD2USIZrrb_Int:
8741 return true;
8742 }
8743 return false;
8744}
8745
8746bool isVEXTRACTPS(unsigned Opcode) {
8747 switch (Opcode) {
8748 case VEXTRACTPSZmri:
8749 case VEXTRACTPSZrri:
8750 case VEXTRACTPSmri:
8751 case VEXTRACTPSrri:
8752 return true;
8753 }
8754 return false;
8755}
8756
8757bool isMOVLPD(unsigned Opcode) {
8758 switch (Opcode) {
8759 case MOVLPDmr:
8760 case MOVLPDrm:
8761 return true;
8762 }
8763 return false;
8764}
8765
8766bool isLGDTD(unsigned Opcode) {
8767 return Opcode == LGDT32m;
8768}
8769
8770bool isVPBROADCASTMB2Q(unsigned Opcode) {
8771 switch (Opcode) {
8772 case VPBROADCASTMB2QZ128rr:
8773 case VPBROADCASTMB2QZ256rr:
8774 case VPBROADCASTMB2QZrr:
8775 return true;
8776 }
8777 return false;
8778}
8779
8780bool isOUT(unsigned Opcode) {
8781 switch (Opcode) {
8782 case OUT16ir:
8783 case OUT16rr:
8784 case OUT32ir:
8785 case OUT32rr:
8786 case OUT8ir:
8787 case OUT8rr:
8788 return true;
8789 }
8790 return false;
8791}
8792
8793bool isVMSAVE(unsigned Opcode) {
8794 switch (Opcode) {
8795 case VMSAVE32:
8796 case VMSAVE64:
8797 return true;
8798 }
8799 return false;
8800}
8801
8802bool isVCVTQQ2PD(unsigned Opcode) {
8803 switch (Opcode) {
8804 case VCVTQQ2PDZ128rm:
8805 case VCVTQQ2PDZ128rmb:
8806 case VCVTQQ2PDZ128rmbk:
8807 case VCVTQQ2PDZ128rmbkz:
8808 case VCVTQQ2PDZ128rmk:
8809 case VCVTQQ2PDZ128rmkz:
8810 case VCVTQQ2PDZ128rr:
8811 case VCVTQQ2PDZ128rrk:
8812 case VCVTQQ2PDZ128rrkz:
8813 case VCVTQQ2PDZ256rm:
8814 case VCVTQQ2PDZ256rmb:
8815 case VCVTQQ2PDZ256rmbk:
8816 case VCVTQQ2PDZ256rmbkz:
8817 case VCVTQQ2PDZ256rmk:
8818 case VCVTQQ2PDZ256rmkz:
8819 case VCVTQQ2PDZ256rr:
8820 case VCVTQQ2PDZ256rrk:
8821 case VCVTQQ2PDZ256rrkz:
8822 case VCVTQQ2PDZrm:
8823 case VCVTQQ2PDZrmb:
8824 case VCVTQQ2PDZrmbk:
8825 case VCVTQQ2PDZrmbkz:
8826 case VCVTQQ2PDZrmk:
8827 case VCVTQQ2PDZrmkz:
8828 case VCVTQQ2PDZrr:
8829 case VCVTQQ2PDZrrb:
8830 case VCVTQQ2PDZrrbk:
8831 case VCVTQQ2PDZrrbkz:
8832 case VCVTQQ2PDZrrk:
8833 case VCVTQQ2PDZrrkz:
8834 return true;
8835 }
8836 return false;
8837}
8838
8839bool isVFMADD213PH(unsigned Opcode) {
8840 switch (Opcode) {
8841 case VFMADD213PHZ128m:
8842 case VFMADD213PHZ128mb:
8843 case VFMADD213PHZ128mbk:
8844 case VFMADD213PHZ128mbkz:
8845 case VFMADD213PHZ128mk:
8846 case VFMADD213PHZ128mkz:
8847 case VFMADD213PHZ128r:
8848 case VFMADD213PHZ128rk:
8849 case VFMADD213PHZ128rkz:
8850 case VFMADD213PHZ256m:
8851 case VFMADD213PHZ256mb:
8852 case VFMADD213PHZ256mbk:
8853 case VFMADD213PHZ256mbkz:
8854 case VFMADD213PHZ256mk:
8855 case VFMADD213PHZ256mkz:
8856 case VFMADD213PHZ256r:
8857 case VFMADD213PHZ256rk:
8858 case VFMADD213PHZ256rkz:
8859 case VFMADD213PHZm:
8860 case VFMADD213PHZmb:
8861 case VFMADD213PHZmbk:
8862 case VFMADD213PHZmbkz:
8863 case VFMADD213PHZmk:
8864 case VFMADD213PHZmkz:
8865 case VFMADD213PHZr:
8866 case VFMADD213PHZrb:
8867 case VFMADD213PHZrbk:
8868 case VFMADD213PHZrbkz:
8869 case VFMADD213PHZrk:
8870 case VFMADD213PHZrkz:
8871 return true;
8872 }
8873 return false;
8874}
8875
8876bool isFCMOVBE(unsigned Opcode) {
8877 return Opcode == CMOVBE_F;
8878}
8879
8880bool isMOVSHDUP(unsigned Opcode) {
8881 switch (Opcode) {
8882 case MOVSHDUPrm:
8883 case MOVSHDUPrr:
8884 return true;
8885 }
8886 return false;
8887}
8888
8889bool isVPMOVUSQB(unsigned Opcode) {
8890 switch (Opcode) {
8891 case VPMOVUSQBZ128mr:
8892 case VPMOVUSQBZ128mrk:
8893 case VPMOVUSQBZ128rr:
8894 case VPMOVUSQBZ128rrk:
8895 case VPMOVUSQBZ128rrkz:
8896 case VPMOVUSQBZ256mr:
8897 case VPMOVUSQBZ256mrk:
8898 case VPMOVUSQBZ256rr:
8899 case VPMOVUSQBZ256rrk:
8900 case VPMOVUSQBZ256rrkz:
8901 case VPMOVUSQBZmr:
8902 case VPMOVUSQBZmrk:
8903 case VPMOVUSQBZrr:
8904 case VPMOVUSQBZrrk:
8905 case VPMOVUSQBZrrkz:
8906 return true;
8907 }
8908 return false;
8909}
8910
8911bool isFIST(unsigned Opcode) {
8912 switch (Opcode) {
8913 case IST_F16m:
8914 case IST_F32m:
8915 return true;
8916 }
8917 return false;
8918}
8919
8920bool isHADDPD(unsigned Opcode) {
8921 switch (Opcode) {
8922 case HADDPDrm:
8923 case HADDPDrr:
8924 return true;
8925 }
8926 return false;
8927}
8928
8929bool isPACKSSWB(unsigned Opcode) {
8930 switch (Opcode) {
8931 case MMX_PACKSSWBrm:
8932 case MMX_PACKSSWBrr:
8933 case PACKSSWBrm:
8934 case PACKSSWBrr:
8935 return true;
8936 }
8937 return false;
8938}
8939
8940bool isVPMACSSDQH(unsigned Opcode) {
8941 switch (Opcode) {
8942 case VPMACSSDQHrm:
8943 case VPMACSSDQHrr:
8944 return true;
8945 }
8946 return false;
8947}
8948
8949bool isVFNMSUB132SD(unsigned Opcode) {
8950 switch (Opcode) {
8951 case VFNMSUB132SDZm_Int:
8952 case VFNMSUB132SDZmk_Int:
8953 case VFNMSUB132SDZmkz_Int:
8954 case VFNMSUB132SDZr_Int:
8955 case VFNMSUB132SDZrb_Int:
8956 case VFNMSUB132SDZrbk_Int:
8957 case VFNMSUB132SDZrbkz_Int:
8958 case VFNMSUB132SDZrk_Int:
8959 case VFNMSUB132SDZrkz_Int:
8960 case VFNMSUB132SDm_Int:
8961 case VFNMSUB132SDr_Int:
8962 return true;
8963 }
8964 return false;
8965}
8966
8967bool isVPMASKMOVQ(unsigned Opcode) {
8968 switch (Opcode) {
8969 case VPMASKMOVQYmr:
8970 case VPMASKMOVQYrm:
8971 case VPMASKMOVQmr:
8972 case VPMASKMOVQrm:
8973 return true;
8974 }
8975 return false;
8976}
8977
8978bool isVCOMPRESSPD(unsigned Opcode) {
8979 switch (Opcode) {
8980 case VCOMPRESSPDZ128mr:
8981 case VCOMPRESSPDZ128mrk:
8982 case VCOMPRESSPDZ128rr:
8983 case VCOMPRESSPDZ128rrk:
8984 case VCOMPRESSPDZ128rrkz:
8985 case VCOMPRESSPDZ256mr:
8986 case VCOMPRESSPDZ256mrk:
8987 case VCOMPRESSPDZ256rr:
8988 case VCOMPRESSPDZ256rrk:
8989 case VCOMPRESSPDZ256rrkz:
8990 case VCOMPRESSPDZmr:
8991 case VCOMPRESSPDZmrk:
8992 case VCOMPRESSPDZrr:
8993 case VCOMPRESSPDZrrk:
8994 case VCOMPRESSPDZrrkz:
8995 return true;
8996 }
8997 return false;
8998}
8999
9000bool isVFMADD213SS(unsigned Opcode) {
9001 switch (Opcode) {
9002 case VFMADD213SSZm_Int:
9003 case VFMADD213SSZmk_Int:
9004 case VFMADD213SSZmkz_Int:
9005 case VFMADD213SSZr_Int:
9006 case VFMADD213SSZrb_Int:
9007 case VFMADD213SSZrbk_Int:
9008 case VFMADD213SSZrbkz_Int:
9009 case VFMADD213SSZrk_Int:
9010 case VFMADD213SSZrkz_Int:
9011 case VFMADD213SSm_Int:
9012 case VFMADD213SSr_Int:
9013 return true;
9014 }
9015 return false;
9016}
9017
9018bool isVPCMPQ(unsigned Opcode) {
9019 switch (Opcode) {
9020 case VPCMPQZ128rmbi:
9021 case VPCMPQZ128rmbik:
9022 case VPCMPQZ128rmi:
9023 case VPCMPQZ128rmik:
9024 case VPCMPQZ128rri:
9025 case VPCMPQZ128rrik:
9026 case VPCMPQZ256rmbi:
9027 case VPCMPQZ256rmbik:
9028 case VPCMPQZ256rmi:
9029 case VPCMPQZ256rmik:
9030 case VPCMPQZ256rri:
9031 case VPCMPQZ256rrik:
9032 case VPCMPQZrmbi:
9033 case VPCMPQZrmbik:
9034 case VPCMPQZrmi:
9035 case VPCMPQZrmik:
9036 case VPCMPQZrri:
9037 case VPCMPQZrrik:
9038 return true;
9039 }
9040 return false;
9041}
9042
9043bool isVADDSH(unsigned Opcode) {
9044 switch (Opcode) {
9045 case VADDSHZrm_Int:
9046 case VADDSHZrmk_Int:
9047 case VADDSHZrmkz_Int:
9048 case VADDSHZrr_Int:
9049 case VADDSHZrrb_Int:
9050 case VADDSHZrrbk_Int:
9051 case VADDSHZrrbkz_Int:
9052 case VADDSHZrrk_Int:
9053 case VADDSHZrrkz_Int:
9054 return true;
9055 }
9056 return false;
9057}
9058
9059bool isVFNMADDSD(unsigned Opcode) {
9060 switch (Opcode) {
9061 case VFNMADDSD4mr:
9062 case VFNMADDSD4rm:
9063 case VFNMADDSD4rr:
9064 case VFNMADDSD4rr_REV:
9065 return true;
9066 }
9067 return false;
9068}
9069
9070bool isUMWAIT(unsigned Opcode) {
9071 return Opcode == UMWAIT;
9072}
9073
9074bool isVPUNPCKHDQ(unsigned Opcode) {
9075 switch (Opcode) {
9076 case VPUNPCKHDQYrm:
9077 case VPUNPCKHDQYrr:
9078 case VPUNPCKHDQZ128rm:
9079 case VPUNPCKHDQZ128rmb:
9080 case VPUNPCKHDQZ128rmbk:
9081 case VPUNPCKHDQZ128rmbkz:
9082 case VPUNPCKHDQZ128rmk:
9083 case VPUNPCKHDQZ128rmkz:
9084 case VPUNPCKHDQZ128rr:
9085 case VPUNPCKHDQZ128rrk:
9086 case VPUNPCKHDQZ128rrkz:
9087 case VPUNPCKHDQZ256rm:
9088 case VPUNPCKHDQZ256rmb:
9089 case VPUNPCKHDQZ256rmbk:
9090 case VPUNPCKHDQZ256rmbkz:
9091 case VPUNPCKHDQZ256rmk:
9092 case VPUNPCKHDQZ256rmkz:
9093 case VPUNPCKHDQZ256rr:
9094 case VPUNPCKHDQZ256rrk:
9095 case VPUNPCKHDQZ256rrkz:
9096 case VPUNPCKHDQZrm:
9097 case VPUNPCKHDQZrmb:
9098 case VPUNPCKHDQZrmbk:
9099 case VPUNPCKHDQZrmbkz:
9100 case VPUNPCKHDQZrmk:
9101 case VPUNPCKHDQZrmkz:
9102 case VPUNPCKHDQZrr:
9103 case VPUNPCKHDQZrrk:
9104 case VPUNPCKHDQZrrkz:
9105 case VPUNPCKHDQrm:
9106 case VPUNPCKHDQrr:
9107 return true;
9108 }
9109 return false;
9110}
9111
9112bool isLCALL(unsigned Opcode) {
9113 switch (Opcode) {
9114 case FARCALL16i:
9115 case FARCALL16m:
9116 case FARCALL32i:
9117 case FARCALL64m:
9118 return true;
9119 }
9120 return false;
9121}
9122
9123bool isAESDEC128KL(unsigned Opcode) {
9124 return Opcode == AESDEC128KL;
9125}
9126
9127bool isVSUBPS(unsigned Opcode) {
9128 switch (Opcode) {
9129 case VSUBPSYrm:
9130 case VSUBPSYrr:
9131 case VSUBPSZ128rm:
9132 case VSUBPSZ128rmb:
9133 case VSUBPSZ128rmbk:
9134 case VSUBPSZ128rmbkz:
9135 case VSUBPSZ128rmk:
9136 case VSUBPSZ128rmkz:
9137 case VSUBPSZ128rr:
9138 case VSUBPSZ128rrk:
9139 case VSUBPSZ128rrkz:
9140 case VSUBPSZ256rm:
9141 case VSUBPSZ256rmb:
9142 case VSUBPSZ256rmbk:
9143 case VSUBPSZ256rmbkz:
9144 case VSUBPSZ256rmk:
9145 case VSUBPSZ256rmkz:
9146 case VSUBPSZ256rr:
9147 case VSUBPSZ256rrk:
9148 case VSUBPSZ256rrkz:
9149 case VSUBPSZrm:
9150 case VSUBPSZrmb:
9151 case VSUBPSZrmbk:
9152 case VSUBPSZrmbkz:
9153 case VSUBPSZrmk:
9154 case VSUBPSZrmkz:
9155 case VSUBPSZrr:
9156 case VSUBPSZrrb:
9157 case VSUBPSZrrbk:
9158 case VSUBPSZrrbkz:
9159 case VSUBPSZrrk:
9160 case VSUBPSZrrkz:
9161 case VSUBPSrm:
9162 case VSUBPSrr:
9163 return true;
9164 }
9165 return false;
9166}
9167
9168bool isFSTP(unsigned Opcode) {
9169 switch (Opcode) {
9170 case ST_FP32m:
9171 case ST_FP64m:
9172 case ST_FP80m:
9173 case ST_FPrr:
9174 return true;
9175 }
9176 return false;
9177}
9178
9179bool isVCVTUDQ2PD(unsigned Opcode) {
9180 switch (Opcode) {
9181 case VCVTUDQ2PDZ128rm:
9182 case VCVTUDQ2PDZ128rmb:
9183 case VCVTUDQ2PDZ128rmbk:
9184 case VCVTUDQ2PDZ128rmbkz:
9185 case VCVTUDQ2PDZ128rmk:
9186 case VCVTUDQ2PDZ128rmkz:
9187 case VCVTUDQ2PDZ128rr:
9188 case VCVTUDQ2PDZ128rrk:
9189 case VCVTUDQ2PDZ128rrkz:
9190 case VCVTUDQ2PDZ256rm:
9191 case VCVTUDQ2PDZ256rmb:
9192 case VCVTUDQ2PDZ256rmbk:
9193 case VCVTUDQ2PDZ256rmbkz:
9194 case VCVTUDQ2PDZ256rmk:
9195 case VCVTUDQ2PDZ256rmkz:
9196 case VCVTUDQ2PDZ256rr:
9197 case VCVTUDQ2PDZ256rrk:
9198 case VCVTUDQ2PDZ256rrkz:
9199 case VCVTUDQ2PDZrm:
9200 case VCVTUDQ2PDZrmb:
9201 case VCVTUDQ2PDZrmbk:
9202 case VCVTUDQ2PDZrmbkz:
9203 case VCVTUDQ2PDZrmk:
9204 case VCVTUDQ2PDZrmkz:
9205 case VCVTUDQ2PDZrr:
9206 case VCVTUDQ2PDZrrk:
9207 case VCVTUDQ2PDZrrkz:
9208 return true;
9209 }
9210 return false;
9211}
9212
9213bool isVPMOVSWB(unsigned Opcode) {
9214 switch (Opcode) {
9215 case VPMOVSWBZ128mr:
9216 case VPMOVSWBZ128mrk:
9217 case VPMOVSWBZ128rr:
9218 case VPMOVSWBZ128rrk:
9219 case VPMOVSWBZ128rrkz:
9220 case VPMOVSWBZ256mr:
9221 case VPMOVSWBZ256mrk:
9222 case VPMOVSWBZ256rr:
9223 case VPMOVSWBZ256rrk:
9224 case VPMOVSWBZ256rrkz:
9225 case VPMOVSWBZmr:
9226 case VPMOVSWBZmrk:
9227 case VPMOVSWBZrr:
9228 case VPMOVSWBZrrk:
9229 case VPMOVSWBZrrkz:
9230 return true;
9231 }
9232 return false;
9233}
9234
9235bool isVPANDNQ(unsigned Opcode) {
9236 switch (Opcode) {
9237 case VPANDNQZ128rm:
9238 case VPANDNQZ128rmb:
9239 case VPANDNQZ128rmbk:
9240 case VPANDNQZ128rmbkz:
9241 case VPANDNQZ128rmk:
9242 case VPANDNQZ128rmkz:
9243 case VPANDNQZ128rr:
9244 case VPANDNQZ128rrk:
9245 case VPANDNQZ128rrkz:
9246 case VPANDNQZ256rm:
9247 case VPANDNQZ256rmb:
9248 case VPANDNQZ256rmbk:
9249 case VPANDNQZ256rmbkz:
9250 case VPANDNQZ256rmk:
9251 case VPANDNQZ256rmkz:
9252 case VPANDNQZ256rr:
9253 case VPANDNQZ256rrk:
9254 case VPANDNQZ256rrkz:
9255 case VPANDNQZrm:
9256 case VPANDNQZrmb:
9257 case VPANDNQZrmbk:
9258 case VPANDNQZrmbkz:
9259 case VPANDNQZrmk:
9260 case VPANDNQZrmkz:
9261 case VPANDNQZrr:
9262 case VPANDNQZrrk:
9263 case VPANDNQZrrkz:
9264 return true;
9265 }
9266 return false;
9267}
9268
9269bool isSYSENTER(unsigned Opcode) {
9270 return Opcode == SYSENTER;
9271}
9272
9273bool isVPHADDWD(unsigned Opcode) {
9274 switch (Opcode) {
9275 case VPHADDWDrm:
9276 case VPHADDWDrr:
9277 return true;
9278 }
9279 return false;
9280}
9281
9282bool isVMOVHPD(unsigned Opcode) {
9283 switch (Opcode) {
9284 case VMOVHPDZ128mr:
9285 case VMOVHPDZ128rm:
9286 case VMOVHPDmr:
9287 case VMOVHPDrm:
9288 return true;
9289 }
9290 return false;
9291}
9292
9293bool isMOVHPD(unsigned Opcode) {
9294 switch (Opcode) {
9295 case MOVHPDmr:
9296 case MOVHPDrm:
9297 return true;
9298 }
9299 return false;
9300}
9301
9302bool isVDIVPH(unsigned Opcode) {
9303 switch (Opcode) {
9304 case VDIVPHZ128rm:
9305 case VDIVPHZ128rmb:
9306 case VDIVPHZ128rmbk:
9307 case VDIVPHZ128rmbkz:
9308 case VDIVPHZ128rmk:
9309 case VDIVPHZ128rmkz:
9310 case VDIVPHZ128rr:
9311 case VDIVPHZ128rrk:
9312 case VDIVPHZ128rrkz:
9313 case VDIVPHZ256rm:
9314 case VDIVPHZ256rmb:
9315 case VDIVPHZ256rmbk:
9316 case VDIVPHZ256rmbkz:
9317 case VDIVPHZ256rmk:
9318 case VDIVPHZ256rmkz:
9319 case VDIVPHZ256rr:
9320 case VDIVPHZ256rrk:
9321 case VDIVPHZ256rrkz:
9322 case VDIVPHZrm:
9323 case VDIVPHZrmb:
9324 case VDIVPHZrmbk:
9325 case VDIVPHZrmbkz:
9326 case VDIVPHZrmk:
9327 case VDIVPHZrmkz:
9328 case VDIVPHZrr:
9329 case VDIVPHZrrb:
9330 case VDIVPHZrrbk:
9331 case VDIVPHZrrbkz:
9332 case VDIVPHZrrk:
9333 case VDIVPHZrrkz:
9334 return true;
9335 }
9336 return false;
9337}
9338
9339bool isFFREE(unsigned Opcode) {
9340 return Opcode == FFREE;
9341}
9342
9343bool isVGATHERPF1DPS(unsigned Opcode) {
9344 return Opcode == VGATHERPF1DPSm;
9345}
9346
9347bool isVPCMPESTRIQ(unsigned Opcode) {
9348 switch (Opcode) {
9349 case VPCMPESTRIQrmi:
9350 case VPCMPESTRIQrri:
9351 return true;
9352 }
9353 return false;
9354}
9355
9356bool isVFNMADD231PD(unsigned Opcode) {
9357 switch (Opcode) {
9358 case VFNMADD231PDYm:
9359 case VFNMADD231PDYr:
9360 case VFNMADD231PDZ128m:
9361 case VFNMADD231PDZ128mb:
9362 case VFNMADD231PDZ128mbk:
9363 case VFNMADD231PDZ128mbkz:
9364 case VFNMADD231PDZ128mk:
9365 case VFNMADD231PDZ128mkz:
9366 case VFNMADD231PDZ128r:
9367 case VFNMADD231PDZ128rk:
9368 case VFNMADD231PDZ128rkz:
9369 case VFNMADD231PDZ256m:
9370 case VFNMADD231PDZ256mb:
9371 case VFNMADD231PDZ256mbk:
9372 case VFNMADD231PDZ256mbkz:
9373 case VFNMADD231PDZ256mk:
9374 case VFNMADD231PDZ256mkz:
9375 case VFNMADD231PDZ256r:
9376 case VFNMADD231PDZ256rk:
9377 case VFNMADD231PDZ256rkz:
9378 case VFNMADD231PDZm:
9379 case VFNMADD231PDZmb:
9380 case VFNMADD231PDZmbk:
9381 case VFNMADD231PDZmbkz:
9382 case VFNMADD231PDZmk:
9383 case VFNMADD231PDZmkz:
9384 case VFNMADD231PDZr:
9385 case VFNMADD231PDZrb:
9386 case VFNMADD231PDZrbk:
9387 case VFNMADD231PDZrbkz:
9388 case VFNMADD231PDZrk:
9389 case VFNMADD231PDZrkz:
9390 case VFNMADD231PDm:
9391 case VFNMADD231PDr:
9392 return true;
9393 }
9394 return false;
9395}
9396
9397bool isVFCMULCPH(unsigned Opcode) {
9398 switch (Opcode) {
9399 case VFCMULCPHZ128rm:
9400 case VFCMULCPHZ128rmb:
9401 case VFCMULCPHZ128rmbk:
9402 case VFCMULCPHZ128rmbkz:
9403 case VFCMULCPHZ128rmk:
9404 case VFCMULCPHZ128rmkz:
9405 case VFCMULCPHZ128rr:
9406 case VFCMULCPHZ128rrk:
9407 case VFCMULCPHZ128rrkz:
9408 case VFCMULCPHZ256rm:
9409 case VFCMULCPHZ256rmb:
9410 case VFCMULCPHZ256rmbk:
9411 case VFCMULCPHZ256rmbkz:
9412 case VFCMULCPHZ256rmk:
9413 case VFCMULCPHZ256rmkz:
9414 case VFCMULCPHZ256rr:
9415 case VFCMULCPHZ256rrk:
9416 case VFCMULCPHZ256rrkz:
9417 case VFCMULCPHZrm:
9418 case VFCMULCPHZrmb:
9419 case VFCMULCPHZrmbk:
9420 case VFCMULCPHZrmbkz:
9421 case VFCMULCPHZrmk:
9422 case VFCMULCPHZrmkz:
9423 case VFCMULCPHZrr:
9424 case VFCMULCPHZrrb:
9425 case VFCMULCPHZrrbk:
9426 case VFCMULCPHZrrbkz:
9427 case VFCMULCPHZrrk:
9428 case VFCMULCPHZrrkz:
9429 return true;
9430 }
9431 return false;
9432}
9433
9434bool isVPADDD(unsigned Opcode) {
9435 switch (Opcode) {
9436 case VPADDDYrm:
9437 case VPADDDYrr:
9438 case VPADDDZ128rm:
9439 case VPADDDZ128rmb:
9440 case VPADDDZ128rmbk:
9441 case VPADDDZ128rmbkz:
9442 case VPADDDZ128rmk:
9443 case VPADDDZ128rmkz:
9444 case VPADDDZ128rr:
9445 case VPADDDZ128rrk:
9446 case VPADDDZ128rrkz:
9447 case VPADDDZ256rm:
9448 case VPADDDZ256rmb:
9449 case VPADDDZ256rmbk:
9450 case VPADDDZ256rmbkz:
9451 case VPADDDZ256rmk:
9452 case VPADDDZ256rmkz:
9453 case VPADDDZ256rr:
9454 case VPADDDZ256rrk:
9455 case VPADDDZ256rrkz:
9456 case VPADDDZrm:
9457 case VPADDDZrmb:
9458 case VPADDDZrmbk:
9459 case VPADDDZrmbkz:
9460 case VPADDDZrmk:
9461 case VPADDDZrmkz:
9462 case VPADDDZrr:
9463 case VPADDDZrrk:
9464 case VPADDDZrrkz:
9465 case VPADDDrm:
9466 case VPADDDrr:
9467 return true;
9468 }
9469 return false;
9470}
9471
9472bool isVSM3MSG2(unsigned Opcode) {
9473 switch (Opcode) {
9474 case VSM3MSG2rm:
9475 case VSM3MSG2rr:
9476 return true;
9477 }
9478 return false;
9479}
9480
9481bool isVPCOMUQ(unsigned Opcode) {
9482 switch (Opcode) {
9483 case VPCOMUQmi:
9484 case VPCOMUQri:
9485 return true;
9486 }
9487 return false;
9488}
9489
9490bool isVERR(unsigned Opcode) {
9491 switch (Opcode) {
9492 case VERRm:
9493 case VERRr:
9494 return true;
9495 }
9496 return false;
9497}
9498
9499bool isKORTESTQ(unsigned Opcode) {
9500 return Opcode == KORTESTQkk;
9501}
9502
9503bool isVFMSUB132SD(unsigned Opcode) {
9504 switch (Opcode) {
9505 case VFMSUB132SDZm_Int:
9506 case VFMSUB132SDZmk_Int:
9507 case VFMSUB132SDZmkz_Int:
9508 case VFMSUB132SDZr_Int:
9509 case VFMSUB132SDZrb_Int:
9510 case VFMSUB132SDZrbk_Int:
9511 case VFMSUB132SDZrbkz_Int:
9512 case VFMSUB132SDZrk_Int:
9513 case VFMSUB132SDZrkz_Int:
9514 case VFMSUB132SDm_Int:
9515 case VFMSUB132SDr_Int:
9516 return true;
9517 }
9518 return false;
9519}
9520
9521bool isTILEZERO(unsigned Opcode) {
9522 return Opcode == TILEZERO;
9523}
9524
9525bool isPFADD(unsigned Opcode) {
9526 switch (Opcode) {
9527 case PFADDrm:
9528 case PFADDrr:
9529 return true;
9530 }
9531 return false;
9532}
9533
9534bool isVCVTSI2SD(unsigned Opcode) {
9535 switch (Opcode) {
9536 case VCVTSI2SDZrm_Int:
9537 case VCVTSI2SDZrr_Int:
9538 case VCVTSI2SDrm_Int:
9539 case VCVTSI2SDrr_Int:
9540 case VCVTSI642SDZrm_Int:
9541 case VCVTSI642SDZrr_Int:
9542 case VCVTSI642SDZrrb_Int:
9543 case VCVTSI642SDrm_Int:
9544 case VCVTSI642SDrr_Int:
9545 return true;
9546 }
9547 return false;
9548}
9549
9550bool isTILELOADDRS(unsigned Opcode) {
9551 switch (Opcode) {
9552 case TILELOADDRS:
9553 case TILELOADDRS_EVEX:
9554 return true;
9555 }
9556 return false;
9557}
9558
9559bool isVSTMXCSR(unsigned Opcode) {
9560 return Opcode == VSTMXCSR;
9561}
9562
9563bool isVCVTTSH2SI(unsigned Opcode) {
9564 switch (Opcode) {
9565 case VCVTTSH2SI64Zrm_Int:
9566 case VCVTTSH2SI64Zrr_Int:
9567 case VCVTTSH2SI64Zrrb_Int:
9568 case VCVTTSH2SIZrm_Int:
9569 case VCVTTSH2SIZrr_Int:
9570 case VCVTTSH2SIZrrb_Int:
9571 return true;
9572 }
9573 return false;
9574}
9575
9576bool isRET(unsigned Opcode) {
9577 switch (Opcode) {
9578 case RET16:
9579 case RET32:
9580 case RET64:
9581 case RETI16:
9582 case RETI32:
9583 case RETI64:
9584 return true;
9585 }
9586 return false;
9587}
9588
9589bool isLZCNT(unsigned Opcode) {
9590 switch (Opcode) {
9591 case LZCNT16rm:
9592 case LZCNT16rm_EVEX:
9593 case LZCNT16rm_NF:
9594 case LZCNT16rr:
9595 case LZCNT16rr_EVEX:
9596 case LZCNT16rr_NF:
9597 case LZCNT32rm:
9598 case LZCNT32rm_EVEX:
9599 case LZCNT32rm_NF:
9600 case LZCNT32rr:
9601 case LZCNT32rr_EVEX:
9602 case LZCNT32rr_NF:
9603 case LZCNT64rm:
9604 case LZCNT64rm_EVEX:
9605 case LZCNT64rm_NF:
9606 case LZCNT64rr:
9607 case LZCNT64rr_EVEX:
9608 case LZCNT64rr_NF:
9609 return true;
9610 }
9611 return false;
9612}
9613
9614bool isMULPD(unsigned Opcode) {
9615 switch (Opcode) {
9616 case MULPDrm:
9617 case MULPDrr:
9618 return true;
9619 }
9620 return false;
9621}
9622
9623bool isVBROADCASTI32X2(unsigned Opcode) {
9624 switch (Opcode) {
9625 case VBROADCASTI32X2Z128rm:
9626 case VBROADCASTI32X2Z128rmk:
9627 case VBROADCASTI32X2Z128rmkz:
9628 case VBROADCASTI32X2Z128rr:
9629 case VBROADCASTI32X2Z128rrk:
9630 case VBROADCASTI32X2Z128rrkz:
9631 case VBROADCASTI32X2Z256rm:
9632 case VBROADCASTI32X2Z256rmk:
9633 case VBROADCASTI32X2Z256rmkz:
9634 case VBROADCASTI32X2Z256rr:
9635 case VBROADCASTI32X2Z256rrk:
9636 case VBROADCASTI32X2Z256rrkz:
9637 case VBROADCASTI32X2Zrm:
9638 case VBROADCASTI32X2Zrmk:
9639 case VBROADCASTI32X2Zrmkz:
9640 case VBROADCASTI32X2Zrr:
9641 case VBROADCASTI32X2Zrrk:
9642 case VBROADCASTI32X2Zrrkz:
9643 return true;
9644 }
9645 return false;
9646}
9647
9648bool isVCVTPH2W(unsigned Opcode) {
9649 switch (Opcode) {
9650 case VCVTPH2WZ128rm:
9651 case VCVTPH2WZ128rmb:
9652 case VCVTPH2WZ128rmbk:
9653 case VCVTPH2WZ128rmbkz:
9654 case VCVTPH2WZ128rmk:
9655 case VCVTPH2WZ128rmkz:
9656 case VCVTPH2WZ128rr:
9657 case VCVTPH2WZ128rrk:
9658 case VCVTPH2WZ128rrkz:
9659 case VCVTPH2WZ256rm:
9660 case VCVTPH2WZ256rmb:
9661 case VCVTPH2WZ256rmbk:
9662 case VCVTPH2WZ256rmbkz:
9663 case VCVTPH2WZ256rmk:
9664 case VCVTPH2WZ256rmkz:
9665 case VCVTPH2WZ256rr:
9666 case VCVTPH2WZ256rrk:
9667 case VCVTPH2WZ256rrkz:
9668 case VCVTPH2WZrm:
9669 case VCVTPH2WZrmb:
9670 case VCVTPH2WZrmbk:
9671 case VCVTPH2WZrmbkz:
9672 case VCVTPH2WZrmk:
9673 case VCVTPH2WZrmkz:
9674 case VCVTPH2WZrr:
9675 case VCVTPH2WZrrb:
9676 case VCVTPH2WZrrbk:
9677 case VCVTPH2WZrrbkz:
9678 case VCVTPH2WZrrk:
9679 case VCVTPH2WZrrkz:
9680 return true;
9681 }
9682 return false;
9683}
9684
9685bool isCQO(unsigned Opcode) {
9686 return Opcode == CQO;
9687}
9688
9689bool isFSUBR(unsigned Opcode) {
9690 switch (Opcode) {
9691 case SUBR_F32m:
9692 case SUBR_F64m:
9693 case SUBR_FST0r:
9694 case SUBR_FrST0:
9695 return true;
9696 }
9697 return false;
9698}
9699
9700bool isDPPD(unsigned Opcode) {
9701 switch (Opcode) {
9702 case DPPDrmi:
9703 case DPPDrri:
9704 return true;
9705 }
9706 return false;
9707}
9708
9709bool isFCOS(unsigned Opcode) {
9710 return Opcode == FCOS;
9711}
9712
9713bool isXSAVES(unsigned Opcode) {
9714 return Opcode == XSAVES;
9715}
9716
9717bool isTZCNT(unsigned Opcode) {
9718 switch (Opcode) {
9719 case TZCNT16rm:
9720 case TZCNT16rm_EVEX:
9721 case TZCNT16rm_NF:
9722 case TZCNT16rr:
9723 case TZCNT16rr_EVEX:
9724 case TZCNT16rr_NF:
9725 case TZCNT32rm:
9726 case TZCNT32rm_EVEX:
9727 case TZCNT32rm_NF:
9728 case TZCNT32rr:
9729 case TZCNT32rr_EVEX:
9730 case TZCNT32rr_NF:
9731 case TZCNT64rm:
9732 case TZCNT64rm_EVEX:
9733 case TZCNT64rm_NF:
9734 case TZCNT64rr:
9735 case TZCNT64rr_EVEX:
9736 case TZCNT64rr_NF:
9737 return true;
9738 }
9739 return false;
9740}
9741
9742bool isLJMP(unsigned Opcode) {
9743 switch (Opcode) {
9744 case FARJMP16i:
9745 case FARJMP16m:
9746 case FARJMP32i:
9747 case FARJMP64m:
9748 return true;
9749 }
9750 return false;
9751}
9752
9753bool isCMOVCC(unsigned Opcode) {
9754 switch (Opcode) {
9755 case CMOV16rm:
9756 case CMOV16rm_ND:
9757 case CMOV16rr:
9758 case CMOV16rr_ND:
9759 case CMOV32rm:
9760 case CMOV32rm_ND:
9761 case CMOV32rr:
9762 case CMOV32rr_ND:
9763 case CMOV64rm:
9764 case CMOV64rm_ND:
9765 case CMOV64rr:
9766 case CMOV64rr_ND:
9767 return true;
9768 }
9769 return false;
9770}
9771
9772bool isVCVTBIASPH2HF8(unsigned Opcode) {
9773 switch (Opcode) {
9774 case VCVTBIASPH2HF8Z128rm:
9775 case VCVTBIASPH2HF8Z128rmb:
9776 case VCVTBIASPH2HF8Z128rmbk:
9777 case VCVTBIASPH2HF8Z128rmbkz:
9778 case VCVTBIASPH2HF8Z128rmk:
9779 case VCVTBIASPH2HF8Z128rmkz:
9780 case VCVTBIASPH2HF8Z128rr:
9781 case VCVTBIASPH2HF8Z128rrk:
9782 case VCVTBIASPH2HF8Z128rrkz:
9783 case VCVTBIASPH2HF8Z256rm:
9784 case VCVTBIASPH2HF8Z256rmb:
9785 case VCVTBIASPH2HF8Z256rmbk:
9786 case VCVTBIASPH2HF8Z256rmbkz:
9787 case VCVTBIASPH2HF8Z256rmk:
9788 case VCVTBIASPH2HF8Z256rmkz:
9789 case VCVTBIASPH2HF8Z256rr:
9790 case VCVTBIASPH2HF8Z256rrk:
9791 case VCVTBIASPH2HF8Z256rrkz:
9792 case VCVTBIASPH2HF8Zrm:
9793 case VCVTBIASPH2HF8Zrmb:
9794 case VCVTBIASPH2HF8Zrmbk:
9795 case VCVTBIASPH2HF8Zrmbkz:
9796 case VCVTBIASPH2HF8Zrmk:
9797 case VCVTBIASPH2HF8Zrmkz:
9798 case VCVTBIASPH2HF8Zrr:
9799 case VCVTBIASPH2HF8Zrrk:
9800 case VCVTBIASPH2HF8Zrrkz:
9801 return true;
9802 }
9803 return false;
9804}
9805
9806bool isINVEPT(unsigned Opcode) {
9807 switch (Opcode) {
9808 case INVEPT32:
9809 case INVEPT64:
9810 case INVEPT64_EVEX:
9811 return true;
9812 }
9813 return false;
9814}
9815
9816bool isADDSUBPD(unsigned Opcode) {
9817 switch (Opcode) {
9818 case ADDSUBPDrm:
9819 case ADDSUBPDrr:
9820 return true;
9821 }
9822 return false;
9823}
9824
9825bool isVMOVSHDUP(unsigned Opcode) {
9826 switch (Opcode) {
9827 case VMOVSHDUPYrm:
9828 case VMOVSHDUPYrr:
9829 case VMOVSHDUPZ128rm:
9830 case VMOVSHDUPZ128rmk:
9831 case VMOVSHDUPZ128rmkz:
9832 case VMOVSHDUPZ128rr:
9833 case VMOVSHDUPZ128rrk:
9834 case VMOVSHDUPZ128rrkz:
9835 case VMOVSHDUPZ256rm:
9836 case VMOVSHDUPZ256rmk:
9837 case VMOVSHDUPZ256rmkz:
9838 case VMOVSHDUPZ256rr:
9839 case VMOVSHDUPZ256rrk:
9840 case VMOVSHDUPZ256rrkz:
9841 case VMOVSHDUPZrm:
9842 case VMOVSHDUPZrmk:
9843 case VMOVSHDUPZrmkz:
9844 case VMOVSHDUPZrr:
9845 case VMOVSHDUPZrrk:
9846 case VMOVSHDUPZrrkz:
9847 case VMOVSHDUPrm:
9848 case VMOVSHDUPrr:
9849 return true;
9850 }
9851 return false;
9852}
9853
9854bool isKSHIFTRD(unsigned Opcode) {
9855 return Opcode == KSHIFTRDki;
9856}
9857
9858bool isVCVTSS2SD(unsigned Opcode) {
9859 switch (Opcode) {
9860 case VCVTSS2SDZrm_Int:
9861 case VCVTSS2SDZrmk_Int:
9862 case VCVTSS2SDZrmkz_Int:
9863 case VCVTSS2SDZrr_Int:
9864 case VCVTSS2SDZrrb_Int:
9865 case VCVTSS2SDZrrbk_Int:
9866 case VCVTSS2SDZrrbkz_Int:
9867 case VCVTSS2SDZrrk_Int:
9868 case VCVTSS2SDZrrkz_Int:
9869 case VCVTSS2SDrm_Int:
9870 case VCVTSS2SDrr_Int:
9871 return true;
9872 }
9873 return false;
9874}
9875
9876bool isPADDQ(unsigned Opcode) {
9877 switch (Opcode) {
9878 case MMX_PADDQrm:
9879 case MMX_PADDQrr:
9880 case PADDQrm:
9881 case PADDQrr:
9882 return true;
9883 }
9884 return false;
9885}
9886
9887bool isVEXTRACTI64X4(unsigned Opcode) {
9888 switch (Opcode) {
9889 case VEXTRACTI64X4Zmri:
9890 case VEXTRACTI64X4Zmrik:
9891 case VEXTRACTI64X4Zrri:
9892 case VEXTRACTI64X4Zrrik:
9893 case VEXTRACTI64X4Zrrikz:
9894 return true;
9895 }
9896 return false;
9897}
9898
9899bool isVFMSUB231SS(unsigned Opcode) {
9900 switch (Opcode) {
9901 case VFMSUB231SSZm_Int:
9902 case VFMSUB231SSZmk_Int:
9903 case VFMSUB231SSZmkz_Int:
9904 case VFMSUB231SSZr_Int:
9905 case VFMSUB231SSZrb_Int:
9906 case VFMSUB231SSZrbk_Int:
9907 case VFMSUB231SSZrbkz_Int:
9908 case VFMSUB231SSZrk_Int:
9909 case VFMSUB231SSZrkz_Int:
9910 case VFMSUB231SSm_Int:
9911 case VFMSUB231SSr_Int:
9912 return true;
9913 }
9914 return false;
9915}
9916
9917bool isVPCMPEQB(unsigned Opcode) {
9918 switch (Opcode) {
9919 case VPCMPEQBYrm:
9920 case VPCMPEQBYrr:
9921 case VPCMPEQBZ128rm:
9922 case VPCMPEQBZ128rmk:
9923 case VPCMPEQBZ128rr:
9924 case VPCMPEQBZ128rrk:
9925 case VPCMPEQBZ256rm:
9926 case VPCMPEQBZ256rmk:
9927 case VPCMPEQBZ256rr:
9928 case VPCMPEQBZ256rrk:
9929 case VPCMPEQBZrm:
9930 case VPCMPEQBZrmk:
9931 case VPCMPEQBZrr:
9932 case VPCMPEQBZrrk:
9933 case VPCMPEQBrm:
9934 case VPCMPEQBrr:
9935 return true;
9936 }
9937 return false;
9938}
9939
9940bool isVPTERNLOGD(unsigned Opcode) {
9941 switch (Opcode) {
9942 case VPTERNLOGDZ128rmbi:
9943 case VPTERNLOGDZ128rmbik:
9944 case VPTERNLOGDZ128rmbikz:
9945 case VPTERNLOGDZ128rmi:
9946 case VPTERNLOGDZ128rmik:
9947 case VPTERNLOGDZ128rmikz:
9948 case VPTERNLOGDZ128rri:
9949 case VPTERNLOGDZ128rrik:
9950 case VPTERNLOGDZ128rrikz:
9951 case VPTERNLOGDZ256rmbi:
9952 case VPTERNLOGDZ256rmbik:
9953 case VPTERNLOGDZ256rmbikz:
9954 case VPTERNLOGDZ256rmi:
9955 case VPTERNLOGDZ256rmik:
9956 case VPTERNLOGDZ256rmikz:
9957 case VPTERNLOGDZ256rri:
9958 case VPTERNLOGDZ256rrik:
9959 case VPTERNLOGDZ256rrikz:
9960 case VPTERNLOGDZrmbi:
9961 case VPTERNLOGDZrmbik:
9962 case VPTERNLOGDZrmbikz:
9963 case VPTERNLOGDZrmi:
9964 case VPTERNLOGDZrmik:
9965 case VPTERNLOGDZrmikz:
9966 case VPTERNLOGDZrri:
9967 case VPTERNLOGDZrrik:
9968 case VPTERNLOGDZrrikz:
9969 return true;
9970 }
9971 return false;
9972}
9973
9974bool isLEA(unsigned Opcode) {
9975 switch (Opcode) {
9976 case LEA16r:
9977 case LEA32r:
9978 case LEA64_32r:
9979 case LEA64r:
9980 return true;
9981 }
9982 return false;
9983}
9984
9985bool isPSUBB(unsigned Opcode) {
9986 switch (Opcode) {
9987 case MMX_PSUBBrm:
9988 case MMX_PSUBBrr:
9989 case PSUBBrm:
9990 case PSUBBrr:
9991 return true;
9992 }
9993 return false;
9994}
9995
9996bool isKADDQ(unsigned Opcode) {
9997 return Opcode == KADDQkk;
9998}
9999
10000bool isMOVSX(unsigned Opcode) {
10001 switch (Opcode) {
10002 case MOVSX16rm16:
10003 case MOVSX16rm8:
10004 case MOVSX16rr16:
10005 case MOVSX16rr8:
10006 case MOVSX32rm16:
10007 case MOVSX32rm8:
10008 case MOVSX32rr16:
10009 case MOVSX32rr8:
10010 case MOVSX64rm16:
10011 case MOVSX64rm8:
10012 case MOVSX64rr16:
10013 case MOVSX64rr8:
10014 return true;
10015 }
10016 return false;
10017}
10018
10019bool isVALIGNQ(unsigned Opcode) {
10020 switch (Opcode) {
10021 case VALIGNQZ128rmbi:
10022 case VALIGNQZ128rmbik:
10023 case VALIGNQZ128rmbikz:
10024 case VALIGNQZ128rmi:
10025 case VALIGNQZ128rmik:
10026 case VALIGNQZ128rmikz:
10027 case VALIGNQZ128rri:
10028 case VALIGNQZ128rrik:
10029 case VALIGNQZ128rrikz:
10030 case VALIGNQZ256rmbi:
10031 case VALIGNQZ256rmbik:
10032 case VALIGNQZ256rmbikz:
10033 case VALIGNQZ256rmi:
10034 case VALIGNQZ256rmik:
10035 case VALIGNQZ256rmikz:
10036 case VALIGNQZ256rri:
10037 case VALIGNQZ256rrik:
10038 case VALIGNQZ256rrikz:
10039 case VALIGNQZrmbi:
10040 case VALIGNQZrmbik:
10041 case VALIGNQZrmbikz:
10042 case VALIGNQZrmi:
10043 case VALIGNQZrmik:
10044 case VALIGNQZrmikz:
10045 case VALIGNQZrri:
10046 case VALIGNQZrrik:
10047 case VALIGNQZrrikz:
10048 return true;
10049 }
10050 return false;
10051}
10052
10053bool isVCVTNE2PS2BF16(unsigned Opcode) {
10054 switch (Opcode) {
10055 case VCVTNE2PS2BF16Z128rm:
10056 case VCVTNE2PS2BF16Z128rmb:
10057 case VCVTNE2PS2BF16Z128rmbk:
10058 case VCVTNE2PS2BF16Z128rmbkz:
10059 case VCVTNE2PS2BF16Z128rmk:
10060 case VCVTNE2PS2BF16Z128rmkz:
10061 case VCVTNE2PS2BF16Z128rr:
10062 case VCVTNE2PS2BF16Z128rrk:
10063 case VCVTNE2PS2BF16Z128rrkz:
10064 case VCVTNE2PS2BF16Z256rm:
10065 case VCVTNE2PS2BF16Z256rmb:
10066 case VCVTNE2PS2BF16Z256rmbk:
10067 case VCVTNE2PS2BF16Z256rmbkz:
10068 case VCVTNE2PS2BF16Z256rmk:
10069 case VCVTNE2PS2BF16Z256rmkz:
10070 case VCVTNE2PS2BF16Z256rr:
10071 case VCVTNE2PS2BF16Z256rrk:
10072 case VCVTNE2PS2BF16Z256rrkz:
10073 case VCVTNE2PS2BF16Zrm:
10074 case VCVTNE2PS2BF16Zrmb:
10075 case VCVTNE2PS2BF16Zrmbk:
10076 case VCVTNE2PS2BF16Zrmbkz:
10077 case VCVTNE2PS2BF16Zrmk:
10078 case VCVTNE2PS2BF16Zrmkz:
10079 case VCVTNE2PS2BF16Zrr:
10080 case VCVTNE2PS2BF16Zrrk:
10081 case VCVTNE2PS2BF16Zrrkz:
10082 return true;
10083 }
10084 return false;
10085}
10086
10087bool isVPSRAW(unsigned Opcode) {
10088 switch (Opcode) {
10089 case VPSRAWYri:
10090 case VPSRAWYrm:
10091 case VPSRAWYrr:
10092 case VPSRAWZ128mi:
10093 case VPSRAWZ128mik:
10094 case VPSRAWZ128mikz:
10095 case VPSRAWZ128ri:
10096 case VPSRAWZ128rik:
10097 case VPSRAWZ128rikz:
10098 case VPSRAWZ128rm:
10099 case VPSRAWZ128rmk:
10100 case VPSRAWZ128rmkz:
10101 case VPSRAWZ128rr:
10102 case VPSRAWZ128rrk:
10103 case VPSRAWZ128rrkz:
10104 case VPSRAWZ256mi:
10105 case VPSRAWZ256mik:
10106 case VPSRAWZ256mikz:
10107 case VPSRAWZ256ri:
10108 case VPSRAWZ256rik:
10109 case VPSRAWZ256rikz:
10110 case VPSRAWZ256rm:
10111 case VPSRAWZ256rmk:
10112 case VPSRAWZ256rmkz:
10113 case VPSRAWZ256rr:
10114 case VPSRAWZ256rrk:
10115 case VPSRAWZ256rrkz:
10116 case VPSRAWZmi:
10117 case VPSRAWZmik:
10118 case VPSRAWZmikz:
10119 case VPSRAWZri:
10120 case VPSRAWZrik:
10121 case VPSRAWZrikz:
10122 case VPSRAWZrm:
10123 case VPSRAWZrmk:
10124 case VPSRAWZrmkz:
10125 case VPSRAWZrr:
10126 case VPSRAWZrrk:
10127 case VPSRAWZrrkz:
10128 case VPSRAWri:
10129 case VPSRAWrm:
10130 case VPSRAWrr:
10131 return true;
10132 }
10133 return false;
10134}
10135
10136bool isVFMSUBADD231PH(unsigned Opcode) {
10137 switch (Opcode) {
10138 case VFMSUBADD231PHZ128m:
10139 case VFMSUBADD231PHZ128mb:
10140 case VFMSUBADD231PHZ128mbk:
10141 case VFMSUBADD231PHZ128mbkz:
10142 case VFMSUBADD231PHZ128mk:
10143 case VFMSUBADD231PHZ128mkz:
10144 case VFMSUBADD231PHZ128r:
10145 case VFMSUBADD231PHZ128rk:
10146 case VFMSUBADD231PHZ128rkz:
10147 case VFMSUBADD231PHZ256m:
10148 case VFMSUBADD231PHZ256mb:
10149 case VFMSUBADD231PHZ256mbk:
10150 case VFMSUBADD231PHZ256mbkz:
10151 case VFMSUBADD231PHZ256mk:
10152 case VFMSUBADD231PHZ256mkz:
10153 case VFMSUBADD231PHZ256r:
10154 case VFMSUBADD231PHZ256rk:
10155 case VFMSUBADD231PHZ256rkz:
10156 case VFMSUBADD231PHZm:
10157 case VFMSUBADD231PHZmb:
10158 case VFMSUBADD231PHZmbk:
10159 case VFMSUBADD231PHZmbkz:
10160 case VFMSUBADD231PHZmk:
10161 case VFMSUBADD231PHZmkz:
10162 case VFMSUBADD231PHZr:
10163 case VFMSUBADD231PHZrb:
10164 case VFMSUBADD231PHZrbk:
10165 case VFMSUBADD231PHZrbkz:
10166 case VFMSUBADD231PHZrk:
10167 case VFMSUBADD231PHZrkz:
10168 return true;
10169 }
10170 return false;
10171}
10172
10173bool isCVTDQ2PS(unsigned Opcode) {
10174 switch (Opcode) {
10175 case CVTDQ2PSrm:
10176 case CVTDQ2PSrr:
10177 return true;
10178 }
10179 return false;
10180}
10181
10182bool isFBLD(unsigned Opcode) {
10183 return Opcode == FBLDm;
10184}
10185
10186bool isLMSW(unsigned Opcode) {
10187 switch (Opcode) {
10188 case LMSW16m:
10189 case LMSW16r:
10190 return true;
10191 }
10192 return false;
10193}
10194
10195bool isWRMSR(unsigned Opcode) {
10196 return Opcode == WRMSR;
10197}
10198
10199bool isMINSS(unsigned Opcode) {
10200 switch (Opcode) {
10201 case MINSSrm_Int:
10202 case MINSSrr_Int:
10203 return true;
10204 }
10205 return false;
10206}
10207
10208bool isFSCALE(unsigned Opcode) {
10209 return Opcode == FSCALE;
10210}
10211
10212bool isVFNMADD213SH(unsigned Opcode) {
10213 switch (Opcode) {
10214 case VFNMADD213SHZm_Int:
10215 case VFNMADD213SHZmk_Int:
10216 case VFNMADD213SHZmkz_Int:
10217 case VFNMADD213SHZr_Int:
10218 case VFNMADD213SHZrb_Int:
10219 case VFNMADD213SHZrbk_Int:
10220 case VFNMADD213SHZrbkz_Int:
10221 case VFNMADD213SHZrk_Int:
10222 case VFNMADD213SHZrkz_Int:
10223 return true;
10224 }
10225 return false;
10226}
10227
10228bool isIMULZU(unsigned Opcode) {
10229 switch (Opcode) {
10230 case IMULZU16rmi:
10231 case IMULZU16rmi8:
10232 case IMULZU16rri:
10233 case IMULZU16rri8:
10234 case IMULZU32rmi:
10235 case IMULZU32rmi8:
10236 case IMULZU32rri:
10237 case IMULZU32rri8:
10238 case IMULZU64rmi32:
10239 case IMULZU64rmi8:
10240 case IMULZU64rri32:
10241 case IMULZU64rri8:
10242 return true;
10243 }
10244 return false;
10245}
10246
10247bool isVPHADDUBD(unsigned Opcode) {
10248 switch (Opcode) {
10249 case VPHADDUBDrm:
10250 case VPHADDUBDrr:
10251 return true;
10252 }
10253 return false;
10254}
10255
10256bool isRDSSPQ(unsigned Opcode) {
10257 return Opcode == RDSSPQ;
10258}
10259
10260bool isVCVTBF162IBS(unsigned Opcode) {
10261 switch (Opcode) {
10262 case VCVTBF162IBSZ128rm:
10263 case VCVTBF162IBSZ128rmb:
10264 case VCVTBF162IBSZ128rmbk:
10265 case VCVTBF162IBSZ128rmbkz:
10266 case VCVTBF162IBSZ128rmk:
10267 case VCVTBF162IBSZ128rmkz:
10268 case VCVTBF162IBSZ128rr:
10269 case VCVTBF162IBSZ128rrk:
10270 case VCVTBF162IBSZ128rrkz:
10271 case VCVTBF162IBSZ256rm:
10272 case VCVTBF162IBSZ256rmb:
10273 case VCVTBF162IBSZ256rmbk:
10274 case VCVTBF162IBSZ256rmbkz:
10275 case VCVTBF162IBSZ256rmk:
10276 case VCVTBF162IBSZ256rmkz:
10277 case VCVTBF162IBSZ256rr:
10278 case VCVTBF162IBSZ256rrk:
10279 case VCVTBF162IBSZ256rrkz:
10280 case VCVTBF162IBSZrm:
10281 case VCVTBF162IBSZrmb:
10282 case VCVTBF162IBSZrmbk:
10283 case VCVTBF162IBSZrmbkz:
10284 case VCVTBF162IBSZrmk:
10285 case VCVTBF162IBSZrmkz:
10286 case VCVTBF162IBSZrr:
10287 case VCVTBF162IBSZrrk:
10288 case VCVTBF162IBSZrrkz:
10289 return true;
10290 }
10291 return false;
10292}
10293
10294bool isLGDT(unsigned Opcode) {
10295 return Opcode == LGDT64m;
10296}
10297
10298bool isVPSHLDVD(unsigned Opcode) {
10299 switch (Opcode) {
10300 case VPSHLDVDZ128m:
10301 case VPSHLDVDZ128mb:
10302 case VPSHLDVDZ128mbk:
10303 case VPSHLDVDZ128mbkz:
10304 case VPSHLDVDZ128mk:
10305 case VPSHLDVDZ128mkz:
10306 case VPSHLDVDZ128r:
10307 case VPSHLDVDZ128rk:
10308 case VPSHLDVDZ128rkz:
10309 case VPSHLDVDZ256m:
10310 case VPSHLDVDZ256mb:
10311 case VPSHLDVDZ256mbk:
10312 case VPSHLDVDZ256mbkz:
10313 case VPSHLDVDZ256mk:
10314 case VPSHLDVDZ256mkz:
10315 case VPSHLDVDZ256r:
10316 case VPSHLDVDZ256rk:
10317 case VPSHLDVDZ256rkz:
10318 case VPSHLDVDZm:
10319 case VPSHLDVDZmb:
10320 case VPSHLDVDZmbk:
10321 case VPSHLDVDZmbkz:
10322 case VPSHLDVDZmk:
10323 case VPSHLDVDZmkz:
10324 case VPSHLDVDZr:
10325 case VPSHLDVDZrk:
10326 case VPSHLDVDZrkz:
10327 return true;
10328 }
10329 return false;
10330}
10331
10332bool isPFCMPGT(unsigned Opcode) {
10333 switch (Opcode) {
10334 case PFCMPGTrm:
10335 case PFCMPGTrr:
10336 return true;
10337 }
10338 return false;
10339}
10340
10341bool isVRNDSCALEPH(unsigned Opcode) {
10342 switch (Opcode) {
10343 case VRNDSCALEPHZ128rmbi:
10344 case VRNDSCALEPHZ128rmbik:
10345 case VRNDSCALEPHZ128rmbikz:
10346 case VRNDSCALEPHZ128rmi:
10347 case VRNDSCALEPHZ128rmik:
10348 case VRNDSCALEPHZ128rmikz:
10349 case VRNDSCALEPHZ128rri:
10350 case VRNDSCALEPHZ128rrik:
10351 case VRNDSCALEPHZ128rrikz:
10352 case VRNDSCALEPHZ256rmbi:
10353 case VRNDSCALEPHZ256rmbik:
10354 case VRNDSCALEPHZ256rmbikz:
10355 case VRNDSCALEPHZ256rmi:
10356 case VRNDSCALEPHZ256rmik:
10357 case VRNDSCALEPHZ256rmikz:
10358 case VRNDSCALEPHZ256rri:
10359 case VRNDSCALEPHZ256rrik:
10360 case VRNDSCALEPHZ256rrikz:
10361 case VRNDSCALEPHZrmbi:
10362 case VRNDSCALEPHZrmbik:
10363 case VRNDSCALEPHZrmbikz:
10364 case VRNDSCALEPHZrmi:
10365 case VRNDSCALEPHZrmik:
10366 case VRNDSCALEPHZrmikz:
10367 case VRNDSCALEPHZrri:
10368 case VRNDSCALEPHZrrib:
10369 case VRNDSCALEPHZrribk:
10370 case VRNDSCALEPHZrribkz:
10371 case VRNDSCALEPHZrrik:
10372 case VRNDSCALEPHZrrikz:
10373 return true;
10374 }
10375 return false;
10376}
10377
10378bool isJCXZ(unsigned Opcode) {
10379 return Opcode == JCXZ;
10380}
10381
10382bool isVPMOVZXBW(unsigned Opcode) {
10383 switch (Opcode) {
10384 case VPMOVZXBWYrm:
10385 case VPMOVZXBWYrr:
10386 case VPMOVZXBWZ128rm:
10387 case VPMOVZXBWZ128rmk:
10388 case VPMOVZXBWZ128rmkz:
10389 case VPMOVZXBWZ128rr:
10390 case VPMOVZXBWZ128rrk:
10391 case VPMOVZXBWZ128rrkz:
10392 case VPMOVZXBWZ256rm:
10393 case VPMOVZXBWZ256rmk:
10394 case VPMOVZXBWZ256rmkz:
10395 case VPMOVZXBWZ256rr:
10396 case VPMOVZXBWZ256rrk:
10397 case VPMOVZXBWZ256rrkz:
10398 case VPMOVZXBWZrm:
10399 case VPMOVZXBWZrmk:
10400 case VPMOVZXBWZrmkz:
10401 case VPMOVZXBWZrr:
10402 case VPMOVZXBWZrrk:
10403 case VPMOVZXBWZrrkz:
10404 case VPMOVZXBWrm:
10405 case VPMOVZXBWrr:
10406 return true;
10407 }
10408 return false;
10409}
10410
10411bool isVFMADDSUB231PD(unsigned Opcode) {
10412 switch (Opcode) {
10413 case VFMADDSUB231PDYm:
10414 case VFMADDSUB231PDYr:
10415 case VFMADDSUB231PDZ128m:
10416 case VFMADDSUB231PDZ128mb:
10417 case VFMADDSUB231PDZ128mbk:
10418 case VFMADDSUB231PDZ128mbkz:
10419 case VFMADDSUB231PDZ128mk:
10420 case VFMADDSUB231PDZ128mkz:
10421 case VFMADDSUB231PDZ128r:
10422 case VFMADDSUB231PDZ128rk:
10423 case VFMADDSUB231PDZ128rkz:
10424 case VFMADDSUB231PDZ256m:
10425 case VFMADDSUB231PDZ256mb:
10426 case VFMADDSUB231PDZ256mbk:
10427 case VFMADDSUB231PDZ256mbkz:
10428 case VFMADDSUB231PDZ256mk:
10429 case VFMADDSUB231PDZ256mkz:
10430 case VFMADDSUB231PDZ256r:
10431 case VFMADDSUB231PDZ256rk:
10432 case VFMADDSUB231PDZ256rkz:
10433 case VFMADDSUB231PDZm:
10434 case VFMADDSUB231PDZmb:
10435 case VFMADDSUB231PDZmbk:
10436 case VFMADDSUB231PDZmbkz:
10437 case VFMADDSUB231PDZmk:
10438 case VFMADDSUB231PDZmkz:
10439 case VFMADDSUB231PDZr:
10440 case VFMADDSUB231PDZrb:
10441 case VFMADDSUB231PDZrbk:
10442 case VFMADDSUB231PDZrbkz:
10443 case VFMADDSUB231PDZrk:
10444 case VFMADDSUB231PDZrkz:
10445 case VFMADDSUB231PDm:
10446 case VFMADDSUB231PDr:
10447 return true;
10448 }
10449 return false;
10450}
10451
10452bool isVBLENDMPD(unsigned Opcode) {
10453 switch (Opcode) {
10454 case VBLENDMPDZ128rm:
10455 case VBLENDMPDZ128rmb:
10456 case VBLENDMPDZ128rmbk:
10457 case VBLENDMPDZ128rmbkz:
10458 case VBLENDMPDZ128rmk:
10459 case VBLENDMPDZ128rmkz:
10460 case VBLENDMPDZ128rr:
10461 case VBLENDMPDZ128rrk:
10462 case VBLENDMPDZ128rrkz:
10463 case VBLENDMPDZ256rm:
10464 case VBLENDMPDZ256rmb:
10465 case VBLENDMPDZ256rmbk:
10466 case VBLENDMPDZ256rmbkz:
10467 case VBLENDMPDZ256rmk:
10468 case VBLENDMPDZ256rmkz:
10469 case VBLENDMPDZ256rr:
10470 case VBLENDMPDZ256rrk:
10471 case VBLENDMPDZ256rrkz:
10472 case VBLENDMPDZrm:
10473 case VBLENDMPDZrmb:
10474 case VBLENDMPDZrmbk:
10475 case VBLENDMPDZrmbkz:
10476 case VBLENDMPDZrmk:
10477 case VBLENDMPDZrmkz:
10478 case VBLENDMPDZrr:
10479 case VBLENDMPDZrrk:
10480 case VBLENDMPDZrrkz:
10481 return true;
10482 }
10483 return false;
10484}
10485
10486bool isHSUBPS(unsigned Opcode) {
10487 switch (Opcode) {
10488 case HSUBPSrm:
10489 case HSUBPSrr:
10490 return true;
10491 }
10492 return false;
10493}
10494
10495bool isPREFETCHIT0(unsigned Opcode) {
10496 return Opcode == PREFETCHIT0;
10497}
10498
10499bool isKTESTD(unsigned Opcode) {
10500 return Opcode == KTESTDkk;
10501}
10502
10503bool isVCVTNEOPH2PS(unsigned Opcode) {
10504 switch (Opcode) {
10505 case VCVTNEOPH2PSYrm:
10506 case VCVTNEOPH2PSrm:
10507 return true;
10508 }
10509 return false;
10510}
10511
10512bool isVBLENDVPD(unsigned Opcode) {
10513 switch (Opcode) {
10514 case VBLENDVPDYrmr:
10515 case VBLENDVPDYrrr:
10516 case VBLENDVPDrmr:
10517 case VBLENDVPDrrr:
10518 return true;
10519 }
10520 return false;
10521}
10522
10523bool isVCVTSS2USI(unsigned Opcode) {
10524 switch (Opcode) {
10525 case VCVTSS2USI64Zrm_Int:
10526 case VCVTSS2USI64Zrr_Int:
10527 case VCVTSS2USI64Zrrb_Int:
10528 case VCVTSS2USIZrm_Int:
10529 case VCVTSS2USIZrr_Int:
10530 case VCVTSS2USIZrrb_Int:
10531 return true;
10532 }
10533 return false;
10534}
10535
10536bool isVCVTTPS2DQS(unsigned Opcode) {
10537 switch (Opcode) {
10538 case VCVTTPS2DQSZ128rm:
10539 case VCVTTPS2DQSZ128rmb:
10540 case VCVTTPS2DQSZ128rmbk:
10541 case VCVTTPS2DQSZ128rmbkz:
10542 case VCVTTPS2DQSZ128rmk:
10543 case VCVTTPS2DQSZ128rmkz:
10544 case VCVTTPS2DQSZ128rr:
10545 case VCVTTPS2DQSZ128rrk:
10546 case VCVTTPS2DQSZ128rrkz:
10547 case VCVTTPS2DQSZ256rm:
10548 case VCVTTPS2DQSZ256rmb:
10549 case VCVTTPS2DQSZ256rmbk:
10550 case VCVTTPS2DQSZ256rmbkz:
10551 case VCVTTPS2DQSZ256rmk:
10552 case VCVTTPS2DQSZ256rmkz:
10553 case VCVTTPS2DQSZ256rr:
10554 case VCVTTPS2DQSZ256rrk:
10555 case VCVTTPS2DQSZ256rrkz:
10556 case VCVTTPS2DQSZrm:
10557 case VCVTTPS2DQSZrmb:
10558 case VCVTTPS2DQSZrmbk:
10559 case VCVTTPS2DQSZrmbkz:
10560 case VCVTTPS2DQSZrmk:
10561 case VCVTTPS2DQSZrmkz:
10562 case VCVTTPS2DQSZrr:
10563 case VCVTTPS2DQSZrrb:
10564 case VCVTTPS2DQSZrrbk:
10565 case VCVTTPS2DQSZrrbkz:
10566 case VCVTTPS2DQSZrrk:
10567 case VCVTTPS2DQSZrrkz:
10568 return true;
10569 }
10570 return false;
10571}
10572
10573bool isVPANDD(unsigned Opcode) {
10574 switch (Opcode) {
10575 case VPANDDZ128rm:
10576 case VPANDDZ128rmb:
10577 case VPANDDZ128rmbk:
10578 case VPANDDZ128rmbkz:
10579 case VPANDDZ128rmk:
10580 case VPANDDZ128rmkz:
10581 case VPANDDZ128rr:
10582 case VPANDDZ128rrk:
10583 case VPANDDZ128rrkz:
10584 case VPANDDZ256rm:
10585 case VPANDDZ256rmb:
10586 case VPANDDZ256rmbk:
10587 case VPANDDZ256rmbkz:
10588 case VPANDDZ256rmk:
10589 case VPANDDZ256rmkz:
10590 case VPANDDZ256rr:
10591 case VPANDDZ256rrk:
10592 case VPANDDZ256rrkz:
10593 case VPANDDZrm:
10594 case VPANDDZrmb:
10595 case VPANDDZrmbk:
10596 case VPANDDZrmbkz:
10597 case VPANDDZrmk:
10598 case VPANDDZrmkz:
10599 case VPANDDZrr:
10600 case VPANDDZrrk:
10601 case VPANDDZrrkz:
10602 return true;
10603 }
10604 return false;
10605}
10606
10607bool isPMINSW(unsigned Opcode) {
10608 switch (Opcode) {
10609 case MMX_PMINSWrm:
10610 case MMX_PMINSWrr:
10611 case PMINSWrm:
10612 case PMINSWrr:
10613 return true;
10614 }
10615 return false;
10616}
10617
10618bool isSTAC(unsigned Opcode) {
10619 return Opcode == STAC;
10620}
10621
10622bool isVFMSUB213PS(unsigned Opcode) {
10623 switch (Opcode) {
10624 case VFMSUB213PSYm:
10625 case VFMSUB213PSYr:
10626 case VFMSUB213PSZ128m:
10627 case VFMSUB213PSZ128mb:
10628 case VFMSUB213PSZ128mbk:
10629 case VFMSUB213PSZ128mbkz:
10630 case VFMSUB213PSZ128mk:
10631 case VFMSUB213PSZ128mkz:
10632 case VFMSUB213PSZ128r:
10633 case VFMSUB213PSZ128rk:
10634 case VFMSUB213PSZ128rkz:
10635 case VFMSUB213PSZ256m:
10636 case VFMSUB213PSZ256mb:
10637 case VFMSUB213PSZ256mbk:
10638 case VFMSUB213PSZ256mbkz:
10639 case VFMSUB213PSZ256mk:
10640 case VFMSUB213PSZ256mkz:
10641 case VFMSUB213PSZ256r:
10642 case VFMSUB213PSZ256rk:
10643 case VFMSUB213PSZ256rkz:
10644 case VFMSUB213PSZm:
10645 case VFMSUB213PSZmb:
10646 case VFMSUB213PSZmbk:
10647 case VFMSUB213PSZmbkz:
10648 case VFMSUB213PSZmk:
10649 case VFMSUB213PSZmkz:
10650 case VFMSUB213PSZr:
10651 case VFMSUB213PSZrb:
10652 case VFMSUB213PSZrbk:
10653 case VFMSUB213PSZrbkz:
10654 case VFMSUB213PSZrk:
10655 case VFMSUB213PSZrkz:
10656 case VFMSUB213PSm:
10657 case VFMSUB213PSr:
10658 return true;
10659 }
10660 return false;
10661}
10662
10663bool isPOPAL(unsigned Opcode) {
10664 return Opcode == POPA32;
10665}
10666
10667bool isVCVTPS2UQQ(unsigned Opcode) {
10668 switch (Opcode) {
10669 case VCVTPS2UQQZ128rm:
10670 case VCVTPS2UQQZ128rmb:
10671 case VCVTPS2UQQZ128rmbk:
10672 case VCVTPS2UQQZ128rmbkz:
10673 case VCVTPS2UQQZ128rmk:
10674 case VCVTPS2UQQZ128rmkz:
10675 case VCVTPS2UQQZ128rr:
10676 case VCVTPS2UQQZ128rrk:
10677 case VCVTPS2UQQZ128rrkz:
10678 case VCVTPS2UQQZ256rm:
10679 case VCVTPS2UQQZ256rmb:
10680 case VCVTPS2UQQZ256rmbk:
10681 case VCVTPS2UQQZ256rmbkz:
10682 case VCVTPS2UQQZ256rmk:
10683 case VCVTPS2UQQZ256rmkz:
10684 case VCVTPS2UQQZ256rr:
10685 case VCVTPS2UQQZ256rrk:
10686 case VCVTPS2UQQZ256rrkz:
10687 case VCVTPS2UQQZrm:
10688 case VCVTPS2UQQZrmb:
10689 case VCVTPS2UQQZrmbk:
10690 case VCVTPS2UQQZrmbkz:
10691 case VCVTPS2UQQZrmk:
10692 case VCVTPS2UQQZrmkz:
10693 case VCVTPS2UQQZrr:
10694 case VCVTPS2UQQZrrb:
10695 case VCVTPS2UQQZrrbk:
10696 case VCVTPS2UQQZrrbkz:
10697 case VCVTPS2UQQZrrk:
10698 case VCVTPS2UQQZrrkz:
10699 return true;
10700 }
10701 return false;
10702}
10703
10704bool isRDRAND(unsigned Opcode) {
10705 switch (Opcode) {
10706 case RDRAND16r:
10707 case RDRAND32r:
10708 case RDRAND64r:
10709 return true;
10710 }
10711 return false;
10712}
10713
10714bool isJCC(unsigned Opcode) {
10715 switch (Opcode) {
10716 case JCC_1:
10717 case JCC_2:
10718 case JCC_4:
10719 return true;
10720 }
10721 return false;
10722}
10723
10724bool isVPMINSQ(unsigned Opcode) {
10725 switch (Opcode) {
10726 case VPMINSQZ128rm:
10727 case VPMINSQZ128rmb:
10728 case VPMINSQZ128rmbk:
10729 case VPMINSQZ128rmbkz:
10730 case VPMINSQZ128rmk:
10731 case VPMINSQZ128rmkz:
10732 case VPMINSQZ128rr:
10733 case VPMINSQZ128rrk:
10734 case VPMINSQZ128rrkz:
10735 case VPMINSQZ256rm:
10736 case VPMINSQZ256rmb:
10737 case VPMINSQZ256rmbk:
10738 case VPMINSQZ256rmbkz:
10739 case VPMINSQZ256rmk:
10740 case VPMINSQZ256rmkz:
10741 case VPMINSQZ256rr:
10742 case VPMINSQZ256rrk:
10743 case VPMINSQZ256rrkz:
10744 case VPMINSQZrm:
10745 case VPMINSQZrmb:
10746 case VPMINSQZrmbk:
10747 case VPMINSQZrmbkz:
10748 case VPMINSQZrmk:
10749 case VPMINSQZrmkz:
10750 case VPMINSQZrr:
10751 case VPMINSQZrrk:
10752 case VPMINSQZrrkz:
10753 return true;
10754 }
10755 return false;
10756}
10757
10758bool isVADDSD(unsigned Opcode) {
10759 switch (Opcode) {
10760 case VADDSDZrm_Int:
10761 case VADDSDZrmk_Int:
10762 case VADDSDZrmkz_Int:
10763 case VADDSDZrr_Int:
10764 case VADDSDZrrb_Int:
10765 case VADDSDZrrbk_Int:
10766 case VADDSDZrrbkz_Int:
10767 case VADDSDZrrk_Int:
10768 case VADDSDZrrkz_Int:
10769 case VADDSDrm_Int:
10770 case VADDSDrr_Int:
10771 return true;
10772 }
10773 return false;
10774}
10775
10776bool isDPPS(unsigned Opcode) {
10777 switch (Opcode) {
10778 case DPPSrmi:
10779 case DPPSrri:
10780 return true;
10781 }
10782 return false;
10783}
10784
10785bool isPINSRQ(unsigned Opcode) {
10786 switch (Opcode) {
10787 case PINSRQrmi:
10788 case PINSRQrri:
10789 return true;
10790 }
10791 return false;
10792}
10793
10794bool isVUCOMISS(unsigned Opcode) {
10795 switch (Opcode) {
10796 case VUCOMISSZrm:
10797 case VUCOMISSZrr:
10798 case VUCOMISSZrrb:
10799 case VUCOMISSrm:
10800 case VUCOMISSrr:
10801 return true;
10802 }
10803 return false;
10804}
10805
10806bool isVPDPWSUD(unsigned Opcode) {
10807 switch (Opcode) {
10808 case VPDPWSUDYrm:
10809 case VPDPWSUDYrr:
10810 case VPDPWSUDZ128rm:
10811 case VPDPWSUDZ128rmb:
10812 case VPDPWSUDZ128rmbk:
10813 case VPDPWSUDZ128rmbkz:
10814 case VPDPWSUDZ128rmk:
10815 case VPDPWSUDZ128rmkz:
10816 case VPDPWSUDZ128rr:
10817 case VPDPWSUDZ128rrk:
10818 case VPDPWSUDZ128rrkz:
10819 case VPDPWSUDZ256rm:
10820 case VPDPWSUDZ256rmb:
10821 case VPDPWSUDZ256rmbk:
10822 case VPDPWSUDZ256rmbkz:
10823 case VPDPWSUDZ256rmk:
10824 case VPDPWSUDZ256rmkz:
10825 case VPDPWSUDZ256rr:
10826 case VPDPWSUDZ256rrk:
10827 case VPDPWSUDZ256rrkz:
10828 case VPDPWSUDZrm:
10829 case VPDPWSUDZrmb:
10830 case VPDPWSUDZrmbk:
10831 case VPDPWSUDZrmbkz:
10832 case VPDPWSUDZrmk:
10833 case VPDPWSUDZrmkz:
10834 case VPDPWSUDZrr:
10835 case VPDPWSUDZrrk:
10836 case VPDPWSUDZrrkz:
10837 case VPDPWSUDrm:
10838 case VPDPWSUDrr:
10839 return true;
10840 }
10841 return false;
10842}
10843
10844bool isKANDNW(unsigned Opcode) {
10845 return Opcode == KANDNWkk;
10846}
10847
10848bool isAOR(unsigned Opcode) {
10849 switch (Opcode) {
10850 case AOR32mr:
10851 case AOR32mr_EVEX:
10852 case AOR64mr:
10853 case AOR64mr_EVEX:
10854 return true;
10855 }
10856 return false;
10857}
10858
10859bool isPMAXUB(unsigned Opcode) {
10860 switch (Opcode) {
10861 case MMX_PMAXUBrm:
10862 case MMX_PMAXUBrr:
10863 case PMAXUBrm:
10864 case PMAXUBrr:
10865 return true;
10866 }
10867 return false;
10868}
10869
10870bool isANDNPD(unsigned Opcode) {
10871 switch (Opcode) {
10872 case ANDNPDrm:
10873 case ANDNPDrr:
10874 return true;
10875 }
10876 return false;
10877}
10878
10879bool isINVPCID(unsigned Opcode) {
10880 switch (Opcode) {
10881 case INVPCID32:
10882 case INVPCID64:
10883 case INVPCID64_EVEX:
10884 return true;
10885 }
10886 return false;
10887}
10888
10889bool isRDGSBASE(unsigned Opcode) {
10890 switch (Opcode) {
10891 case RDGSBASE:
10892 case RDGSBASE64:
10893 return true;
10894 }
10895 return false;
10896}
10897
10898bool isVPMOVSQD(unsigned Opcode) {
10899 switch (Opcode) {
10900 case VPMOVSQDZ128mr:
10901 case VPMOVSQDZ128mrk:
10902 case VPMOVSQDZ128rr:
10903 case VPMOVSQDZ128rrk:
10904 case VPMOVSQDZ128rrkz:
10905 case VPMOVSQDZ256mr:
10906 case VPMOVSQDZ256mrk:
10907 case VPMOVSQDZ256rr:
10908 case VPMOVSQDZ256rrk:
10909 case VPMOVSQDZ256rrkz:
10910 case VPMOVSQDZmr:
10911 case VPMOVSQDZmrk:
10912 case VPMOVSQDZrr:
10913 case VPMOVSQDZrrk:
10914 case VPMOVSQDZrrkz:
10915 return true;
10916 }
10917 return false;
10918}
10919
10920bool isBT(unsigned Opcode) {
10921 switch (Opcode) {
10922 case BT16mi8:
10923 case BT16mr:
10924 case BT16ri8:
10925 case BT16rr:
10926 case BT32mi8:
10927 case BT32mr:
10928 case BT32ri8:
10929 case BT32rr:
10930 case BT64mi8:
10931 case BT64mr:
10932 case BT64ri8:
10933 case BT64rr:
10934 return true;
10935 }
10936 return false;
10937}
10938
10939bool isVPROLVQ(unsigned Opcode) {
10940 switch (Opcode) {
10941 case VPROLVQZ128rm:
10942 case VPROLVQZ128rmb:
10943 case VPROLVQZ128rmbk:
10944 case VPROLVQZ128rmbkz:
10945 case VPROLVQZ128rmk:
10946 case VPROLVQZ128rmkz:
10947 case VPROLVQZ128rr:
10948 case VPROLVQZ128rrk:
10949 case VPROLVQZ128rrkz:
10950 case VPROLVQZ256rm:
10951 case VPROLVQZ256rmb:
10952 case VPROLVQZ256rmbk:
10953 case VPROLVQZ256rmbkz:
10954 case VPROLVQZ256rmk:
10955 case VPROLVQZ256rmkz:
10956 case VPROLVQZ256rr:
10957 case VPROLVQZ256rrk:
10958 case VPROLVQZ256rrkz:
10959 case VPROLVQZrm:
10960 case VPROLVQZrmb:
10961 case VPROLVQZrmbk:
10962 case VPROLVQZrmbkz:
10963 case VPROLVQZrmk:
10964 case VPROLVQZrmkz:
10965 case VPROLVQZrr:
10966 case VPROLVQZrrk:
10967 case VPROLVQZrrkz:
10968 return true;
10969 }
10970 return false;
10971}
10972
10973bool isVFMADDSUB132PD(unsigned Opcode) {
10974 switch (Opcode) {
10975 case VFMADDSUB132PDYm:
10976 case VFMADDSUB132PDYr:
10977 case VFMADDSUB132PDZ128m:
10978 case VFMADDSUB132PDZ128mb:
10979 case VFMADDSUB132PDZ128mbk:
10980 case VFMADDSUB132PDZ128mbkz:
10981 case VFMADDSUB132PDZ128mk:
10982 case VFMADDSUB132PDZ128mkz:
10983 case VFMADDSUB132PDZ128r:
10984 case VFMADDSUB132PDZ128rk:
10985 case VFMADDSUB132PDZ128rkz:
10986 case VFMADDSUB132PDZ256m:
10987 case VFMADDSUB132PDZ256mb:
10988 case VFMADDSUB132PDZ256mbk:
10989 case VFMADDSUB132PDZ256mbkz:
10990 case VFMADDSUB132PDZ256mk:
10991 case VFMADDSUB132PDZ256mkz:
10992 case VFMADDSUB132PDZ256r:
10993 case VFMADDSUB132PDZ256rk:
10994 case VFMADDSUB132PDZ256rkz:
10995 case VFMADDSUB132PDZm:
10996 case VFMADDSUB132PDZmb:
10997 case VFMADDSUB132PDZmbk:
10998 case VFMADDSUB132PDZmbkz:
10999 case VFMADDSUB132PDZmk:
11000 case VFMADDSUB132PDZmkz:
11001 case VFMADDSUB132PDZr:
11002 case VFMADDSUB132PDZrb:
11003 case VFMADDSUB132PDZrbk:
11004 case VFMADDSUB132PDZrbkz:
11005 case VFMADDSUB132PDZrk:
11006 case VFMADDSUB132PDZrkz:
11007 case VFMADDSUB132PDm:
11008 case VFMADDSUB132PDr:
11009 return true;
11010 }
11011 return false;
11012}
11013
11014bool isRORX(unsigned Opcode) {
11015 switch (Opcode) {
11016 case RORX32mi:
11017 case RORX32mi_EVEX:
11018 case RORX32ri:
11019 case RORX32ri_EVEX:
11020 case RORX64mi:
11021 case RORX64mi_EVEX:
11022 case RORX64ri:
11023 case RORX64ri_EVEX:
11024 return true;
11025 }
11026 return false;
11027}
11028
11029bool isPADDUSW(unsigned Opcode) {
11030 switch (Opcode) {
11031 case MMX_PADDUSWrm:
11032 case MMX_PADDUSWrr:
11033 case PADDUSWrm:
11034 case PADDUSWrr:
11035 return true;
11036 }
11037 return false;
11038}
11039
11040bool isPFNACC(unsigned Opcode) {
11041 switch (Opcode) {
11042 case PFNACCrm:
11043 case PFNACCrr:
11044 return true;
11045 }
11046 return false;
11047}
11048
11049bool isAND(unsigned Opcode) {
11050 switch (Opcode) {
11051 case AND16i16:
11052 case AND16mi:
11053 case AND16mi8:
11054 case AND16mi8_EVEX:
11055 case AND16mi8_ND:
11056 case AND16mi8_NF:
11057 case AND16mi8_NF_ND:
11058 case AND16mi_EVEX:
11059 case AND16mi_ND:
11060 case AND16mi_NF:
11061 case AND16mi_NF_ND:
11062 case AND16mr:
11063 case AND16mr_EVEX:
11064 case AND16mr_ND:
11065 case AND16mr_NF:
11066 case AND16mr_NF_ND:
11067 case AND16ri:
11068 case AND16ri8:
11069 case AND16ri8_EVEX:
11070 case AND16ri8_ND:
11071 case AND16ri8_NF:
11072 case AND16ri8_NF_ND:
11073 case AND16ri_EVEX:
11074 case AND16ri_ND:
11075 case AND16ri_NF:
11076 case AND16ri_NF_ND:
11077 case AND16rm:
11078 case AND16rm_EVEX:
11079 case AND16rm_ND:
11080 case AND16rm_NF:
11081 case AND16rm_NF_ND:
11082 case AND16rr:
11083 case AND16rr_EVEX:
11084 case AND16rr_EVEX_REV:
11085 case AND16rr_ND:
11086 case AND16rr_ND_REV:
11087 case AND16rr_NF:
11088 case AND16rr_NF_ND:
11089 case AND16rr_NF_ND_REV:
11090 case AND16rr_NF_REV:
11091 case AND16rr_REV:
11092 case AND32i32:
11093 case AND32mi:
11094 case AND32mi8:
11095 case AND32mi8_EVEX:
11096 case AND32mi8_ND:
11097 case AND32mi8_NF:
11098 case AND32mi8_NF_ND:
11099 case AND32mi_EVEX:
11100 case AND32mi_ND:
11101 case AND32mi_NF:
11102 case AND32mi_NF_ND:
11103 case AND32mr:
11104 case AND32mr_EVEX:
11105 case AND32mr_ND:
11106 case AND32mr_NF:
11107 case AND32mr_NF_ND:
11108 case AND32ri:
11109 case AND32ri8:
11110 case AND32ri8_EVEX:
11111 case AND32ri8_ND:
11112 case AND32ri8_NF:
11113 case AND32ri8_NF_ND:
11114 case AND32ri_EVEX:
11115 case AND32ri_ND:
11116 case AND32ri_NF:
11117 case AND32ri_NF_ND:
11118 case AND32rm:
11119 case AND32rm_EVEX:
11120 case AND32rm_ND:
11121 case AND32rm_NF:
11122 case AND32rm_NF_ND:
11123 case AND32rr:
11124 case AND32rr_EVEX:
11125 case AND32rr_EVEX_REV:
11126 case AND32rr_ND:
11127 case AND32rr_ND_REV:
11128 case AND32rr_NF:
11129 case AND32rr_NF_ND:
11130 case AND32rr_NF_ND_REV:
11131 case AND32rr_NF_REV:
11132 case AND32rr_REV:
11133 case AND64i32:
11134 case AND64mi32:
11135 case AND64mi32_EVEX:
11136 case AND64mi32_ND:
11137 case AND64mi32_NF:
11138 case AND64mi32_NF_ND:
11139 case AND64mi8:
11140 case AND64mi8_EVEX:
11141 case AND64mi8_ND:
11142 case AND64mi8_NF:
11143 case AND64mi8_NF_ND:
11144 case AND64mr:
11145 case AND64mr_EVEX:
11146 case AND64mr_ND:
11147 case AND64mr_NF:
11148 case AND64mr_NF_ND:
11149 case AND64ri32:
11150 case AND64ri32_EVEX:
11151 case AND64ri32_ND:
11152 case AND64ri32_NF:
11153 case AND64ri32_NF_ND:
11154 case AND64ri8:
11155 case AND64ri8_EVEX:
11156 case AND64ri8_ND:
11157 case AND64ri8_NF:
11158 case AND64ri8_NF_ND:
11159 case AND64rm:
11160 case AND64rm_EVEX:
11161 case AND64rm_ND:
11162 case AND64rm_NF:
11163 case AND64rm_NF_ND:
11164 case AND64rr:
11165 case AND64rr_EVEX:
11166 case AND64rr_EVEX_REV:
11167 case AND64rr_ND:
11168 case AND64rr_ND_REV:
11169 case AND64rr_NF:
11170 case AND64rr_NF_ND:
11171 case AND64rr_NF_ND_REV:
11172 case AND64rr_NF_REV:
11173 case AND64rr_REV:
11174 case AND8i8:
11175 case AND8mi:
11176 case AND8mi8:
11177 case AND8mi_EVEX:
11178 case AND8mi_ND:
11179 case AND8mi_NF:
11180 case AND8mi_NF_ND:
11181 case AND8mr:
11182 case AND8mr_EVEX:
11183 case AND8mr_ND:
11184 case AND8mr_NF:
11185 case AND8mr_NF_ND:
11186 case AND8ri:
11187 case AND8ri8:
11188 case AND8ri_EVEX:
11189 case AND8ri_ND:
11190 case AND8ri_NF:
11191 case AND8ri_NF_ND:
11192 case AND8rm:
11193 case AND8rm_EVEX:
11194 case AND8rm_ND:
11195 case AND8rm_NF:
11196 case AND8rm_NF_ND:
11197 case AND8rr:
11198 case AND8rr_EVEX:
11199 case AND8rr_EVEX_REV:
11200 case AND8rr_ND:
11201 case AND8rr_ND_REV:
11202 case AND8rr_NF:
11203 case AND8rr_NF_ND:
11204 case AND8rr_NF_ND_REV:
11205 case AND8rr_NF_REV:
11206 case AND8rr_REV:
11207 return true;
11208 }
11209 return false;
11210}
11211
11212bool isPSLLQ(unsigned Opcode) {
11213 switch (Opcode) {
11214 case MMX_PSLLQri:
11215 case MMX_PSLLQrm:
11216 case MMX_PSLLQrr:
11217 case PSLLQri:
11218 case PSLLQrm:
11219 case PSLLQrr:
11220 return true;
11221 }
11222 return false;
11223}
11224
11225bool isVFMSUB132PH(unsigned Opcode) {
11226 switch (Opcode) {
11227 case VFMSUB132PHZ128m:
11228 case VFMSUB132PHZ128mb:
11229 case VFMSUB132PHZ128mbk:
11230 case VFMSUB132PHZ128mbkz:
11231 case VFMSUB132PHZ128mk:
11232 case VFMSUB132PHZ128mkz:
11233 case VFMSUB132PHZ128r:
11234 case VFMSUB132PHZ128rk:
11235 case VFMSUB132PHZ128rkz:
11236 case VFMSUB132PHZ256m:
11237 case VFMSUB132PHZ256mb:
11238 case VFMSUB132PHZ256mbk:
11239 case VFMSUB132PHZ256mbkz:
11240 case VFMSUB132PHZ256mk:
11241 case VFMSUB132PHZ256mkz:
11242 case VFMSUB132PHZ256r:
11243 case VFMSUB132PHZ256rk:
11244 case VFMSUB132PHZ256rkz:
11245 case VFMSUB132PHZm:
11246 case VFMSUB132PHZmb:
11247 case VFMSUB132PHZmbk:
11248 case VFMSUB132PHZmbkz:
11249 case VFMSUB132PHZmk:
11250 case VFMSUB132PHZmkz:
11251 case VFMSUB132PHZr:
11252 case VFMSUB132PHZrb:
11253 case VFMSUB132PHZrbk:
11254 case VFMSUB132PHZrbkz:
11255 case VFMSUB132PHZrk:
11256 case VFMSUB132PHZrkz:
11257 return true;
11258 }
11259 return false;
11260}
11261
11262bool isXSAVE(unsigned Opcode) {
11263 return Opcode == XSAVE;
11264}
11265
11266bool isKNOTQ(unsigned Opcode) {
11267 return Opcode == KNOTQkk;
11268}
11269
11270bool isXTEST(unsigned Opcode) {
11271 return Opcode == XTEST;
11272}
11273
11274bool isVINSERTPS(unsigned Opcode) {
11275 switch (Opcode) {
11276 case VINSERTPSZrmi:
11277 case VINSERTPSZrri:
11278 case VINSERTPSrmi:
11279 case VINSERTPSrri:
11280 return true;
11281 }
11282 return false;
11283}
11284
11285bool isXSAVEOPT(unsigned Opcode) {
11286 return Opcode == XSAVEOPT;
11287}
11288
11289bool isLDS(unsigned Opcode) {
11290 switch (Opcode) {
11291 case LDS16rm:
11292 case LDS32rm:
11293 return true;
11294 }
11295 return false;
11296}
11297
11298bool isVFMADDSUB213PD(unsigned Opcode) {
11299 switch (Opcode) {
11300 case VFMADDSUB213PDYm:
11301 case VFMADDSUB213PDYr:
11302 case VFMADDSUB213PDZ128m:
11303 case VFMADDSUB213PDZ128mb:
11304 case VFMADDSUB213PDZ128mbk:
11305 case VFMADDSUB213PDZ128mbkz:
11306 case VFMADDSUB213PDZ128mk:
11307 case VFMADDSUB213PDZ128mkz:
11308 case VFMADDSUB213PDZ128r:
11309 case VFMADDSUB213PDZ128rk:
11310 case VFMADDSUB213PDZ128rkz:
11311 case VFMADDSUB213PDZ256m:
11312 case VFMADDSUB213PDZ256mb:
11313 case VFMADDSUB213PDZ256mbk:
11314 case VFMADDSUB213PDZ256mbkz:
11315 case VFMADDSUB213PDZ256mk:
11316 case VFMADDSUB213PDZ256mkz:
11317 case VFMADDSUB213PDZ256r:
11318 case VFMADDSUB213PDZ256rk:
11319 case VFMADDSUB213PDZ256rkz:
11320 case VFMADDSUB213PDZm:
11321 case VFMADDSUB213PDZmb:
11322 case VFMADDSUB213PDZmbk:
11323 case VFMADDSUB213PDZmbkz:
11324 case VFMADDSUB213PDZmk:
11325 case VFMADDSUB213PDZmkz:
11326 case VFMADDSUB213PDZr:
11327 case VFMADDSUB213PDZrb:
11328 case VFMADDSUB213PDZrbk:
11329 case VFMADDSUB213PDZrbkz:
11330 case VFMADDSUB213PDZrk:
11331 case VFMADDSUB213PDZrkz:
11332 case VFMADDSUB213PDm:
11333 case VFMADDSUB213PDr:
11334 return true;
11335 }
11336 return false;
11337}
11338
11339bool isVINSERTF32X4(unsigned Opcode) {
11340 switch (Opcode) {
11341 case VINSERTF32X4Z256rmi:
11342 case VINSERTF32X4Z256rmik:
11343 case VINSERTF32X4Z256rmikz:
11344 case VINSERTF32X4Z256rri:
11345 case VINSERTF32X4Z256rrik:
11346 case VINSERTF32X4Z256rrikz:
11347 case VINSERTF32X4Zrmi:
11348 case VINSERTF32X4Zrmik:
11349 case VINSERTF32X4Zrmikz:
11350 case VINSERTF32X4Zrri:
11351 case VINSERTF32X4Zrrik:
11352 case VINSERTF32X4Zrrikz:
11353 return true;
11354 }
11355 return false;
11356}
11357
11358bool isVRSQRTPS(unsigned Opcode) {
11359 switch (Opcode) {
11360 case VRSQRTPSYm:
11361 case VRSQRTPSYr:
11362 case VRSQRTPSm:
11363 case VRSQRTPSr:
11364 return true;
11365 }
11366 return false;
11367}
11368
11369bool isVSUBPH(unsigned Opcode) {
11370 switch (Opcode) {
11371 case VSUBPHZ128rm:
11372 case VSUBPHZ128rmb:
11373 case VSUBPHZ128rmbk:
11374 case VSUBPHZ128rmbkz:
11375 case VSUBPHZ128rmk:
11376 case VSUBPHZ128rmkz:
11377 case VSUBPHZ128rr:
11378 case VSUBPHZ128rrk:
11379 case VSUBPHZ128rrkz:
11380 case VSUBPHZ256rm:
11381 case VSUBPHZ256rmb:
11382 case VSUBPHZ256rmbk:
11383 case VSUBPHZ256rmbkz:
11384 case VSUBPHZ256rmk:
11385 case VSUBPHZ256rmkz:
11386 case VSUBPHZ256rr:
11387 case VSUBPHZ256rrk:
11388 case VSUBPHZ256rrkz:
11389 case VSUBPHZrm:
11390 case VSUBPHZrmb:
11391 case VSUBPHZrmbk:
11392 case VSUBPHZrmbkz:
11393 case VSUBPHZrmk:
11394 case VSUBPHZrmkz:
11395 case VSUBPHZrr:
11396 case VSUBPHZrrb:
11397 case VSUBPHZrrbk:
11398 case VSUBPHZrrbkz:
11399 case VSUBPHZrrk:
11400 case VSUBPHZrrkz:
11401 return true;
11402 }
11403 return false;
11404}
11405
11406bool isPMOVSXBW(unsigned Opcode) {
11407 switch (Opcode) {
11408 case PMOVSXBWrm:
11409 case PMOVSXBWrr:
11410 return true;
11411 }
11412 return false;
11413}
11414
11415bool isVPSRLDQ(unsigned Opcode) {
11416 switch (Opcode) {
11417 case VPSRLDQYri:
11418 case VPSRLDQZ128mi:
11419 case VPSRLDQZ128ri:
11420 case VPSRLDQZ256mi:
11421 case VPSRLDQZ256ri:
11422 case VPSRLDQZmi:
11423 case VPSRLDQZri:
11424 case VPSRLDQri:
11425 return true;
11426 }
11427 return false;
11428}
11429
11430bool isADC(unsigned Opcode) {
11431 switch (Opcode) {
11432 case ADC16i16:
11433 case ADC16mi:
11434 case ADC16mi8:
11435 case ADC16mi8_EVEX:
11436 case ADC16mi8_ND:
11437 case ADC16mi_EVEX:
11438 case ADC16mi_ND:
11439 case ADC16mr:
11440 case ADC16mr_EVEX:
11441 case ADC16mr_ND:
11442 case ADC16ri:
11443 case ADC16ri8:
11444 case ADC16ri8_EVEX:
11445 case ADC16ri8_ND:
11446 case ADC16ri_EVEX:
11447 case ADC16ri_ND:
11448 case ADC16rm:
11449 case ADC16rm_EVEX:
11450 case ADC16rm_ND:
11451 case ADC16rr:
11452 case ADC16rr_EVEX:
11453 case ADC16rr_EVEX_REV:
11454 case ADC16rr_ND:
11455 case ADC16rr_ND_REV:
11456 case ADC16rr_REV:
11457 case ADC32i32:
11458 case ADC32mi:
11459 case ADC32mi8:
11460 case ADC32mi8_EVEX:
11461 case ADC32mi8_ND:
11462 case ADC32mi_EVEX:
11463 case ADC32mi_ND:
11464 case ADC32mr:
11465 case ADC32mr_EVEX:
11466 case ADC32mr_ND:
11467 case ADC32ri:
11468 case ADC32ri8:
11469 case ADC32ri8_EVEX:
11470 case ADC32ri8_ND:
11471 case ADC32ri_EVEX:
11472 case ADC32ri_ND:
11473 case ADC32rm:
11474 case ADC32rm_EVEX:
11475 case ADC32rm_ND:
11476 case ADC32rr:
11477 case ADC32rr_EVEX:
11478 case ADC32rr_EVEX_REV:
11479 case ADC32rr_ND:
11480 case ADC32rr_ND_REV:
11481 case ADC32rr_REV:
11482 case ADC64i32:
11483 case ADC64mi32:
11484 case ADC64mi32_EVEX:
11485 case ADC64mi32_ND:
11486 case ADC64mi8:
11487 case ADC64mi8_EVEX:
11488 case ADC64mi8_ND:
11489 case ADC64mr:
11490 case ADC64mr_EVEX:
11491 case ADC64mr_ND:
11492 case ADC64ri32:
11493 case ADC64ri32_EVEX:
11494 case ADC64ri32_ND:
11495 case ADC64ri8:
11496 case ADC64ri8_EVEX:
11497 case ADC64ri8_ND:
11498 case ADC64rm:
11499 case ADC64rm_EVEX:
11500 case ADC64rm_ND:
11501 case ADC64rr:
11502 case ADC64rr_EVEX:
11503 case ADC64rr_EVEX_REV:
11504 case ADC64rr_ND:
11505 case ADC64rr_ND_REV:
11506 case ADC64rr_REV:
11507 case ADC8i8:
11508 case ADC8mi:
11509 case ADC8mi8:
11510 case ADC8mi_EVEX:
11511 case ADC8mi_ND:
11512 case ADC8mr:
11513 case ADC8mr_EVEX:
11514 case ADC8mr_ND:
11515 case ADC8ri:
11516 case ADC8ri8:
11517 case ADC8ri_EVEX:
11518 case ADC8ri_ND:
11519 case ADC8rm:
11520 case ADC8rm_EVEX:
11521 case ADC8rm_ND:
11522 case ADC8rr:
11523 case ADC8rr_EVEX:
11524 case ADC8rr_EVEX_REV:
11525 case ADC8rr_ND:
11526 case ADC8rr_ND_REV:
11527 case ADC8rr_REV:
11528 return true;
11529 }
11530 return false;
11531}
11532
11533bool isPHADDD(unsigned Opcode) {
11534 switch (Opcode) {
11535 case MMX_PHADDDrm:
11536 case MMX_PHADDDrr:
11537 case PHADDDrm:
11538 case PHADDDrr:
11539 return true;
11540 }
11541 return false;
11542}
11543
11544bool isVDPPHPS(unsigned Opcode) {
11545 switch (Opcode) {
11546 case VDPPHPSZ128m:
11547 case VDPPHPSZ128mb:
11548 case VDPPHPSZ128mbk:
11549 case VDPPHPSZ128mbkz:
11550 case VDPPHPSZ128mk:
11551 case VDPPHPSZ128mkz:
11552 case VDPPHPSZ128r:
11553 case VDPPHPSZ128rk:
11554 case VDPPHPSZ128rkz:
11555 case VDPPHPSZ256m:
11556 case VDPPHPSZ256mb:
11557 case VDPPHPSZ256mbk:
11558 case VDPPHPSZ256mbkz:
11559 case VDPPHPSZ256mk:
11560 case VDPPHPSZ256mkz:
11561 case VDPPHPSZ256r:
11562 case VDPPHPSZ256rk:
11563 case VDPPHPSZ256rkz:
11564 case VDPPHPSZm:
11565 case VDPPHPSZmb:
11566 case VDPPHPSZmbk:
11567 case VDPPHPSZmbkz:
11568 case VDPPHPSZmk:
11569 case VDPPHPSZmkz:
11570 case VDPPHPSZr:
11571 case VDPPHPSZrk:
11572 case VDPPHPSZrkz:
11573 return true;
11574 }
11575 return false;
11576}
11577
11578bool isVMINPH(unsigned Opcode) {
11579 switch (Opcode) {
11580 case VMINPHZ128rm:
11581 case VMINPHZ128rmb:
11582 case VMINPHZ128rmbk:
11583 case VMINPHZ128rmbkz:
11584 case VMINPHZ128rmk:
11585 case VMINPHZ128rmkz:
11586 case VMINPHZ128rr:
11587 case VMINPHZ128rrk:
11588 case VMINPHZ128rrkz:
11589 case VMINPHZ256rm:
11590 case VMINPHZ256rmb:
11591 case VMINPHZ256rmbk:
11592 case VMINPHZ256rmbkz:
11593 case VMINPHZ256rmk:
11594 case VMINPHZ256rmkz:
11595 case VMINPHZ256rr:
11596 case VMINPHZ256rrk:
11597 case VMINPHZ256rrkz:
11598 case VMINPHZrm:
11599 case VMINPHZrmb:
11600 case VMINPHZrmbk:
11601 case VMINPHZrmbkz:
11602 case VMINPHZrmk:
11603 case VMINPHZrmkz:
11604 case VMINPHZrr:
11605 case VMINPHZrrb:
11606 case VMINPHZrrbk:
11607 case VMINPHZrrbkz:
11608 case VMINPHZrrk:
11609 case VMINPHZrrkz:
11610 return true;
11611 }
11612 return false;
11613}
11614
11615bool isVMINSD(unsigned Opcode) {
11616 switch (Opcode) {
11617 case VMINSDZrm_Int:
11618 case VMINSDZrmk_Int:
11619 case VMINSDZrmkz_Int:
11620 case VMINSDZrr_Int:
11621 case VMINSDZrrb_Int:
11622 case VMINSDZrrbk_Int:
11623 case VMINSDZrrbkz_Int:
11624 case VMINSDZrrk_Int:
11625 case VMINSDZrrkz_Int:
11626 case VMINSDrm_Int:
11627 case VMINSDrr_Int:
11628 return true;
11629 }
11630 return false;
11631}
11632
11633bool isVROUNDPD(unsigned Opcode) {
11634 switch (Opcode) {
11635 case VROUNDPDYmi:
11636 case VROUNDPDYri:
11637 case VROUNDPDmi:
11638 case VROUNDPDri:
11639 return true;
11640 }
11641 return false;
11642}
11643
11644bool isVFCMADDCPH(unsigned Opcode) {
11645 switch (Opcode) {
11646 case VFCMADDCPHZ128m:
11647 case VFCMADDCPHZ128mb:
11648 case VFCMADDCPHZ128mbk:
11649 case VFCMADDCPHZ128mbkz:
11650 case VFCMADDCPHZ128mk:
11651 case VFCMADDCPHZ128mkz:
11652 case VFCMADDCPHZ128r:
11653 case VFCMADDCPHZ128rk:
11654 case VFCMADDCPHZ128rkz:
11655 case VFCMADDCPHZ256m:
11656 case VFCMADDCPHZ256mb:
11657 case VFCMADDCPHZ256mbk:
11658 case VFCMADDCPHZ256mbkz:
11659 case VFCMADDCPHZ256mk:
11660 case VFCMADDCPHZ256mkz:
11661 case VFCMADDCPHZ256r:
11662 case VFCMADDCPHZ256rk:
11663 case VFCMADDCPHZ256rkz:
11664 case VFCMADDCPHZm:
11665 case VFCMADDCPHZmb:
11666 case VFCMADDCPHZmbk:
11667 case VFCMADDCPHZmbkz:
11668 case VFCMADDCPHZmk:
11669 case VFCMADDCPHZmkz:
11670 case VFCMADDCPHZr:
11671 case VFCMADDCPHZrb:
11672 case VFCMADDCPHZrbk:
11673 case VFCMADDCPHZrbkz:
11674 case VFCMADDCPHZrk:
11675 case VFCMADDCPHZrkz:
11676 return true;
11677 }
11678 return false;
11679}
11680
11681bool isINCSSPQ(unsigned Opcode) {
11682 return Opcode == INCSSPQ;
11683}
11684
11685bool isVPUNPCKLDQ(unsigned Opcode) {
11686 switch (Opcode) {
11687 case VPUNPCKLDQYrm:
11688 case VPUNPCKLDQYrr:
11689 case VPUNPCKLDQZ128rm:
11690 case VPUNPCKLDQZ128rmb:
11691 case VPUNPCKLDQZ128rmbk:
11692 case VPUNPCKLDQZ128rmbkz:
11693 case VPUNPCKLDQZ128rmk:
11694 case VPUNPCKLDQZ128rmkz:
11695 case VPUNPCKLDQZ128rr:
11696 case VPUNPCKLDQZ128rrk:
11697 case VPUNPCKLDQZ128rrkz:
11698 case VPUNPCKLDQZ256rm:
11699 case VPUNPCKLDQZ256rmb:
11700 case VPUNPCKLDQZ256rmbk:
11701 case VPUNPCKLDQZ256rmbkz:
11702 case VPUNPCKLDQZ256rmk:
11703 case VPUNPCKLDQZ256rmkz:
11704 case VPUNPCKLDQZ256rr:
11705 case VPUNPCKLDQZ256rrk:
11706 case VPUNPCKLDQZ256rrkz:
11707 case VPUNPCKLDQZrm:
11708 case VPUNPCKLDQZrmb:
11709 case VPUNPCKLDQZrmbk:
11710 case VPUNPCKLDQZrmbkz:
11711 case VPUNPCKLDQZrmk:
11712 case VPUNPCKLDQZrmkz:
11713 case VPUNPCKLDQZrr:
11714 case VPUNPCKLDQZrrk:
11715 case VPUNPCKLDQZrrkz:
11716 case VPUNPCKLDQrm:
11717 case VPUNPCKLDQrr:
11718 return true;
11719 }
11720 return false;
11721}
11722
11723bool isVMINSH(unsigned Opcode) {
11724 switch (Opcode) {
11725 case VMINSHZrm_Int:
11726 case VMINSHZrmk_Int:
11727 case VMINSHZrmkz_Int:
11728 case VMINSHZrr_Int:
11729 case VMINSHZrrb_Int:
11730 case VMINSHZrrbk_Int:
11731 case VMINSHZrrbkz_Int:
11732 case VMINSHZrrk_Int:
11733 case VMINSHZrrkz_Int:
11734 return true;
11735 }
11736 return false;
11737}
11738
11739bool isINSERTQ(unsigned Opcode) {
11740 switch (Opcode) {
11741 case INSERTQ:
11742 case INSERTQI:
11743 return true;
11744 }
11745 return false;
11746}
11747
11748bool isBLCI(unsigned Opcode) {
11749 switch (Opcode) {
11750 case BLCI32rm:
11751 case BLCI32rr:
11752 case BLCI64rm:
11753 case BLCI64rr:
11754 return true;
11755 }
11756 return false;
11757}
11758
11759bool isHLT(unsigned Opcode) {
11760 return Opcode == HLT;
11761}
11762
11763bool isVPCOMUW(unsigned Opcode) {
11764 switch (Opcode) {
11765 case VPCOMUWmi:
11766 case VPCOMUWri:
11767 return true;
11768 }
11769 return false;
11770}
11771
11772bool isVPMOVSXDQ(unsigned Opcode) {
11773 switch (Opcode) {
11774 case VPMOVSXDQYrm:
11775 case VPMOVSXDQYrr:
11776 case VPMOVSXDQZ128rm:
11777 case VPMOVSXDQZ128rmk:
11778 case VPMOVSXDQZ128rmkz:
11779 case VPMOVSXDQZ128rr:
11780 case VPMOVSXDQZ128rrk:
11781 case VPMOVSXDQZ128rrkz:
11782 case VPMOVSXDQZ256rm:
11783 case VPMOVSXDQZ256rmk:
11784 case VPMOVSXDQZ256rmkz:
11785 case VPMOVSXDQZ256rr:
11786 case VPMOVSXDQZ256rrk:
11787 case VPMOVSXDQZ256rrkz:
11788 case VPMOVSXDQZrm:
11789 case VPMOVSXDQZrmk:
11790 case VPMOVSXDQZrmkz:
11791 case VPMOVSXDQZrr:
11792 case VPMOVSXDQZrrk:
11793 case VPMOVSXDQZrrkz:
11794 case VPMOVSXDQrm:
11795 case VPMOVSXDQrr:
11796 return true;
11797 }
11798 return false;
11799}
11800
11801bool isVFNMSUB231PS(unsigned Opcode) {
11802 switch (Opcode) {
11803 case VFNMSUB231PSYm:
11804 case VFNMSUB231PSYr:
11805 case VFNMSUB231PSZ128m:
11806 case VFNMSUB231PSZ128mb:
11807 case VFNMSUB231PSZ128mbk:
11808 case VFNMSUB231PSZ128mbkz:
11809 case VFNMSUB231PSZ128mk:
11810 case VFNMSUB231PSZ128mkz:
11811 case VFNMSUB231PSZ128r:
11812 case VFNMSUB231PSZ128rk:
11813 case VFNMSUB231PSZ128rkz:
11814 case VFNMSUB231PSZ256m:
11815 case VFNMSUB231PSZ256mb:
11816 case VFNMSUB231PSZ256mbk:
11817 case VFNMSUB231PSZ256mbkz:
11818 case VFNMSUB231PSZ256mk:
11819 case VFNMSUB231PSZ256mkz:
11820 case VFNMSUB231PSZ256r:
11821 case VFNMSUB231PSZ256rk:
11822 case VFNMSUB231PSZ256rkz:
11823 case VFNMSUB231PSZm:
11824 case VFNMSUB231PSZmb:
11825 case VFNMSUB231PSZmbk:
11826 case VFNMSUB231PSZmbkz:
11827 case VFNMSUB231PSZmk:
11828 case VFNMSUB231PSZmkz:
11829 case VFNMSUB231PSZr:
11830 case VFNMSUB231PSZrb:
11831 case VFNMSUB231PSZrbk:
11832 case VFNMSUB231PSZrbkz:
11833 case VFNMSUB231PSZrk:
11834 case VFNMSUB231PSZrkz:
11835 case VFNMSUB231PSm:
11836 case VFNMSUB231PSr:
11837 return true;
11838 }
11839 return false;
11840}
11841
11842bool isVFNMSUB213SH(unsigned Opcode) {
11843 switch (Opcode) {
11844 case VFNMSUB213SHZm_Int:
11845 case VFNMSUB213SHZmk_Int:
11846 case VFNMSUB213SHZmkz_Int:
11847 case VFNMSUB213SHZr_Int:
11848 case VFNMSUB213SHZrb_Int:
11849 case VFNMSUB213SHZrbk_Int:
11850 case VFNMSUB213SHZrbkz_Int:
11851 case VFNMSUB213SHZrk_Int:
11852 case VFNMSUB213SHZrkz_Int:
11853 return true;
11854 }
11855 return false;
11856}
11857
11858bool isVCVTTPD2UQQ(unsigned Opcode) {
11859 switch (Opcode) {
11860 case VCVTTPD2UQQZ128rm:
11861 case VCVTTPD2UQQZ128rmb:
11862 case VCVTTPD2UQQZ128rmbk:
11863 case VCVTTPD2UQQZ128rmbkz:
11864 case VCVTTPD2UQQZ128rmk:
11865 case VCVTTPD2UQQZ128rmkz:
11866 case VCVTTPD2UQQZ128rr:
11867 case VCVTTPD2UQQZ128rrk:
11868 case VCVTTPD2UQQZ128rrkz:
11869 case VCVTTPD2UQQZ256rm:
11870 case VCVTTPD2UQQZ256rmb:
11871 case VCVTTPD2UQQZ256rmbk:
11872 case VCVTTPD2UQQZ256rmbkz:
11873 case VCVTTPD2UQQZ256rmk:
11874 case VCVTTPD2UQQZ256rmkz:
11875 case VCVTTPD2UQQZ256rr:
11876 case VCVTTPD2UQQZ256rrk:
11877 case VCVTTPD2UQQZ256rrkz:
11878 case VCVTTPD2UQQZrm:
11879 case VCVTTPD2UQQZrmb:
11880 case VCVTTPD2UQQZrmbk:
11881 case VCVTTPD2UQQZrmbkz:
11882 case VCVTTPD2UQQZrmk:
11883 case VCVTTPD2UQQZrmkz:
11884 case VCVTTPD2UQQZrr:
11885 case VCVTTPD2UQQZrrb:
11886 case VCVTTPD2UQQZrrbk:
11887 case VCVTTPD2UQQZrrbkz:
11888 case VCVTTPD2UQQZrrk:
11889 case VCVTTPD2UQQZrrkz:
11890 return true;
11891 }
11892 return false;
11893}
11894
11895bool isSQRTSS(unsigned Opcode) {
11896 switch (Opcode) {
11897 case SQRTSSm_Int:
11898 case SQRTSSr_Int:
11899 return true;
11900 }
11901 return false;
11902}
11903
11904bool isIMUL(unsigned Opcode) {
11905 switch (Opcode) {
11906 case IMUL16m:
11907 case IMUL16m_EVEX:
11908 case IMUL16m_NF:
11909 case IMUL16r:
11910 case IMUL16r_EVEX:
11911 case IMUL16r_NF:
11912 case IMUL16rm:
11913 case IMUL16rm_EVEX:
11914 case IMUL16rm_ND:
11915 case IMUL16rm_NF:
11916 case IMUL16rm_NF_ND:
11917 case IMUL16rmi:
11918 case IMUL16rmi8:
11919 case IMUL16rmi8_EVEX:
11920 case IMUL16rmi8_NF:
11921 case IMUL16rmi_EVEX:
11922 case IMUL16rmi_NF:
11923 case IMUL16rr:
11924 case IMUL16rr_EVEX:
11925 case IMUL16rr_ND:
11926 case IMUL16rr_NF:
11927 case IMUL16rr_NF_ND:
11928 case IMUL16rri:
11929 case IMUL16rri8:
11930 case IMUL16rri8_EVEX:
11931 case IMUL16rri8_NF:
11932 case IMUL16rri_EVEX:
11933 case IMUL16rri_NF:
11934 case IMUL32m:
11935 case IMUL32m_EVEX:
11936 case IMUL32m_NF:
11937 case IMUL32r:
11938 case IMUL32r_EVEX:
11939 case IMUL32r_NF:
11940 case IMUL32rm:
11941 case IMUL32rm_EVEX:
11942 case IMUL32rm_ND:
11943 case IMUL32rm_NF:
11944 case IMUL32rm_NF_ND:
11945 case IMUL32rmi:
11946 case IMUL32rmi8:
11947 case IMUL32rmi8_EVEX:
11948 case IMUL32rmi8_NF:
11949 case IMUL32rmi_EVEX:
11950 case IMUL32rmi_NF:
11951 case IMUL32rr:
11952 case IMUL32rr_EVEX:
11953 case IMUL32rr_ND:
11954 case IMUL32rr_NF:
11955 case IMUL32rr_NF_ND:
11956 case IMUL32rri:
11957 case IMUL32rri8:
11958 case IMUL32rri8_EVEX:
11959 case IMUL32rri8_NF:
11960 case IMUL32rri_EVEX:
11961 case IMUL32rri_NF:
11962 case IMUL64m:
11963 case IMUL64m_EVEX:
11964 case IMUL64m_NF:
11965 case IMUL64r:
11966 case IMUL64r_EVEX:
11967 case IMUL64r_NF:
11968 case IMUL64rm:
11969 case IMUL64rm_EVEX:
11970 case IMUL64rm_ND:
11971 case IMUL64rm_NF:
11972 case IMUL64rm_NF_ND:
11973 case IMUL64rmi32:
11974 case IMUL64rmi32_EVEX:
11975 case IMUL64rmi32_NF:
11976 case IMUL64rmi8:
11977 case IMUL64rmi8_EVEX:
11978 case IMUL64rmi8_NF:
11979 case IMUL64rr:
11980 case IMUL64rr_EVEX:
11981 case IMUL64rr_ND:
11982 case IMUL64rr_NF:
11983 case IMUL64rr_NF_ND:
11984 case IMUL64rri32:
11985 case IMUL64rri32_EVEX:
11986 case IMUL64rri32_NF:
11987 case IMUL64rri8:
11988 case IMUL64rri8_EVEX:
11989 case IMUL64rri8_NF:
11990 case IMUL8m:
11991 case IMUL8m_EVEX:
11992 case IMUL8m_NF:
11993 case IMUL8r:
11994 case IMUL8r_EVEX:
11995 case IMUL8r_NF:
11996 return true;
11997 }
11998 return false;
11999}
12000
12001bool isVCVTSS2SI(unsigned Opcode) {
12002 switch (Opcode) {
12003 case VCVTSS2SI64Zrm_Int:
12004 case VCVTSS2SI64Zrr_Int:
12005 case VCVTSS2SI64Zrrb_Int:
12006 case VCVTSS2SI64rm_Int:
12007 case VCVTSS2SI64rr_Int:
12008 case VCVTSS2SIZrm_Int:
12009 case VCVTSS2SIZrr_Int:
12010 case VCVTSS2SIZrrb_Int:
12011 case VCVTSS2SIrm_Int:
12012 case VCVTSS2SIrr_Int:
12013 return true;
12014 }
12015 return false;
12016}
12017
12018bool isPUSHAW(unsigned Opcode) {
12019 return Opcode == PUSHA16;
12020}
12021
12022bool isSTOSD(unsigned Opcode) {
12023 return Opcode == STOSL;
12024}
12025
12026bool isPSRLDQ(unsigned Opcode) {
12027 return Opcode == PSRLDQri;
12028}
12029
12030bool isVSCATTERQPS(unsigned Opcode) {
12031 switch (Opcode) {
12032 case VSCATTERQPSZ128mr:
12033 case VSCATTERQPSZ256mr:
12034 case VSCATTERQPSZmr:
12035 return true;
12036 }
12037 return false;
12038}
12039
12040bool isFIDIV(unsigned Opcode) {
12041 switch (Opcode) {
12042 case DIV_FI16m:
12043 case DIV_FI32m:
12044 return true;
12045 }
12046 return false;
12047}
12048
12049bool isVFMSUB213PD(unsigned Opcode) {
12050 switch (Opcode) {
12051 case VFMSUB213PDYm:
12052 case VFMSUB213PDYr:
12053 case VFMSUB213PDZ128m:
12054 case VFMSUB213PDZ128mb:
12055 case VFMSUB213PDZ128mbk:
12056 case VFMSUB213PDZ128mbkz:
12057 case VFMSUB213PDZ128mk:
12058 case VFMSUB213PDZ128mkz:
12059 case VFMSUB213PDZ128r:
12060 case VFMSUB213PDZ128rk:
12061 case VFMSUB213PDZ128rkz:
12062 case VFMSUB213PDZ256m:
12063 case VFMSUB213PDZ256mb:
12064 case VFMSUB213PDZ256mbk:
12065 case VFMSUB213PDZ256mbkz:
12066 case VFMSUB213PDZ256mk:
12067 case VFMSUB213PDZ256mkz:
12068 case VFMSUB213PDZ256r:
12069 case VFMSUB213PDZ256rk:
12070 case VFMSUB213PDZ256rkz:
12071 case VFMSUB213PDZm:
12072 case VFMSUB213PDZmb:
12073 case VFMSUB213PDZmbk:
12074 case VFMSUB213PDZmbkz:
12075 case VFMSUB213PDZmk:
12076 case VFMSUB213PDZmkz:
12077 case VFMSUB213PDZr:
12078 case VFMSUB213PDZrb:
12079 case VFMSUB213PDZrbk:
12080 case VFMSUB213PDZrbkz:
12081 case VFMSUB213PDZrk:
12082 case VFMSUB213PDZrkz:
12083 case VFMSUB213PDm:
12084 case VFMSUB213PDr:
12085 return true;
12086 }
12087 return false;
12088}
12089
12090bool isVFMADDSUB231PH(unsigned Opcode) {
12091 switch (Opcode) {
12092 case VFMADDSUB231PHZ128m:
12093 case VFMADDSUB231PHZ128mb:
12094 case VFMADDSUB231PHZ128mbk:
12095 case VFMADDSUB231PHZ128mbkz:
12096 case VFMADDSUB231PHZ128mk:
12097 case VFMADDSUB231PHZ128mkz:
12098 case VFMADDSUB231PHZ128r:
12099 case VFMADDSUB231PHZ128rk:
12100 case VFMADDSUB231PHZ128rkz:
12101 case VFMADDSUB231PHZ256m:
12102 case VFMADDSUB231PHZ256mb:
12103 case VFMADDSUB231PHZ256mbk:
12104 case VFMADDSUB231PHZ256mbkz:
12105 case VFMADDSUB231PHZ256mk:
12106 case VFMADDSUB231PHZ256mkz:
12107 case VFMADDSUB231PHZ256r:
12108 case VFMADDSUB231PHZ256rk:
12109 case VFMADDSUB231PHZ256rkz:
12110 case VFMADDSUB231PHZm:
12111 case VFMADDSUB231PHZmb:
12112 case VFMADDSUB231PHZmbk:
12113 case VFMADDSUB231PHZmbkz:
12114 case VFMADDSUB231PHZmk:
12115 case VFMADDSUB231PHZmkz:
12116 case VFMADDSUB231PHZr:
12117 case VFMADDSUB231PHZrb:
12118 case VFMADDSUB231PHZrbk:
12119 case VFMADDSUB231PHZrbkz:
12120 case VFMADDSUB231PHZrk:
12121 case VFMADDSUB231PHZrkz:
12122 return true;
12123 }
12124 return false;
12125}
12126
12127bool isTDCALL(unsigned Opcode) {
12128 return Opcode == TDCALL;
12129}
12130
12131bool isPVALIDATE(unsigned Opcode) {
12132 switch (Opcode) {
12133 case PVALIDATE32:
12134 case PVALIDATE64:
12135 return true;
12136 }
12137 return false;
12138}
12139
12140bool isVPSHUFLW(unsigned Opcode) {
12141 switch (Opcode) {
12142 case VPSHUFLWYmi:
12143 case VPSHUFLWYri:
12144 case VPSHUFLWZ128mi:
12145 case VPSHUFLWZ128mik:
12146 case VPSHUFLWZ128mikz:
12147 case VPSHUFLWZ128ri:
12148 case VPSHUFLWZ128rik:
12149 case VPSHUFLWZ128rikz:
12150 case VPSHUFLWZ256mi:
12151 case VPSHUFLWZ256mik:
12152 case VPSHUFLWZ256mikz:
12153 case VPSHUFLWZ256ri:
12154 case VPSHUFLWZ256rik:
12155 case VPSHUFLWZ256rikz:
12156 case VPSHUFLWZmi:
12157 case VPSHUFLWZmik:
12158 case VPSHUFLWZmikz:
12159 case VPSHUFLWZri:
12160 case VPSHUFLWZrik:
12161 case VPSHUFLWZrikz:
12162 case VPSHUFLWmi:
12163 case VPSHUFLWri:
12164 return true;
12165 }
12166 return false;
12167}
12168
12169bool isPCLMULQDQ(unsigned Opcode) {
12170 switch (Opcode) {
12171 case PCLMULQDQrmi:
12172 case PCLMULQDQrri:
12173 return true;
12174 }
12175 return false;
12176}
12177
12178bool isCMPXCHG8B(unsigned Opcode) {
12179 return Opcode == CMPXCHG8B;
12180}
12181
12182bool isVPMOVM2B(unsigned Opcode) {
12183 switch (Opcode) {
12184 case VPMOVM2BZ128rk:
12185 case VPMOVM2BZ256rk:
12186 case VPMOVM2BZrk:
12187 return true;
12188 }
12189 return false;
12190}
12191
12192bool isVCVTUDQ2PH(unsigned Opcode) {
12193 switch (Opcode) {
12194 case VCVTUDQ2PHZ128rm:
12195 case VCVTUDQ2PHZ128rmb:
12196 case VCVTUDQ2PHZ128rmbk:
12197 case VCVTUDQ2PHZ128rmbkz:
12198 case VCVTUDQ2PHZ128rmk:
12199 case VCVTUDQ2PHZ128rmkz:
12200 case VCVTUDQ2PHZ128rr:
12201 case VCVTUDQ2PHZ128rrk:
12202 case VCVTUDQ2PHZ128rrkz:
12203 case VCVTUDQ2PHZ256rm:
12204 case VCVTUDQ2PHZ256rmb:
12205 case VCVTUDQ2PHZ256rmbk:
12206 case VCVTUDQ2PHZ256rmbkz:
12207 case VCVTUDQ2PHZ256rmk:
12208 case VCVTUDQ2PHZ256rmkz:
12209 case VCVTUDQ2PHZ256rr:
12210 case VCVTUDQ2PHZ256rrk:
12211 case VCVTUDQ2PHZ256rrkz:
12212 case VCVTUDQ2PHZrm:
12213 case VCVTUDQ2PHZrmb:
12214 case VCVTUDQ2PHZrmbk:
12215 case VCVTUDQ2PHZrmbkz:
12216 case VCVTUDQ2PHZrmk:
12217 case VCVTUDQ2PHZrmkz:
12218 case VCVTUDQ2PHZrr:
12219 case VCVTUDQ2PHZrrb:
12220 case VCVTUDQ2PHZrrbk:
12221 case VCVTUDQ2PHZrrbkz:
12222 case VCVTUDQ2PHZrrk:
12223 case VCVTUDQ2PHZrrkz:
12224 return true;
12225 }
12226 return false;
12227}
12228
12229bool isPEXTRQ(unsigned Opcode) {
12230 switch (Opcode) {
12231 case PEXTRQmri:
12232 case PEXTRQrri:
12233 return true;
12234 }
12235 return false;
12236}
12237
12238bool isXCRYPTCTR(unsigned Opcode) {
12239 return Opcode == XCRYPTCTR;
12240}
12241
12242bool isVREDUCEPH(unsigned Opcode) {
12243 switch (Opcode) {
12244 case VREDUCEPHZ128rmbi:
12245 case VREDUCEPHZ128rmbik:
12246 case VREDUCEPHZ128rmbikz:
12247 case VREDUCEPHZ128rmi:
12248 case VREDUCEPHZ128rmik:
12249 case VREDUCEPHZ128rmikz:
12250 case VREDUCEPHZ128rri:
12251 case VREDUCEPHZ128rrik:
12252 case VREDUCEPHZ128rrikz:
12253 case VREDUCEPHZ256rmbi:
12254 case VREDUCEPHZ256rmbik:
12255 case VREDUCEPHZ256rmbikz:
12256 case VREDUCEPHZ256rmi:
12257 case VREDUCEPHZ256rmik:
12258 case VREDUCEPHZ256rmikz:
12259 case VREDUCEPHZ256rri:
12260 case VREDUCEPHZ256rrik:
12261 case VREDUCEPHZ256rrikz:
12262 case VREDUCEPHZrmbi:
12263 case VREDUCEPHZrmbik:
12264 case VREDUCEPHZrmbikz:
12265 case VREDUCEPHZrmi:
12266 case VREDUCEPHZrmik:
12267 case VREDUCEPHZrmikz:
12268 case VREDUCEPHZrri:
12269 case VREDUCEPHZrrib:
12270 case VREDUCEPHZrribk:
12271 case VREDUCEPHZrribkz:
12272 case VREDUCEPHZrrik:
12273 case VREDUCEPHZrrikz:
12274 return true;
12275 }
12276 return false;
12277}
12278
12279bool isUCOMISD(unsigned Opcode) {
12280 switch (Opcode) {
12281 case UCOMISDrm:
12282 case UCOMISDrr:
12283 return true;
12284 }
12285 return false;
12286}
12287
12288bool isOUTSD(unsigned Opcode) {
12289 return Opcode == OUTSL;
12290}
12291
12292bool isSUBSS(unsigned Opcode) {
12293 switch (Opcode) {
12294 case SUBSSrm_Int:
12295 case SUBSSrr_Int:
12296 return true;
12297 }
12298 return false;
12299}
12300
12301bool isVFMSUBPS(unsigned Opcode) {
12302 switch (Opcode) {
12303 case VFMSUBPS4Ymr:
12304 case VFMSUBPS4Yrm:
12305 case VFMSUBPS4Yrr:
12306 case VFMSUBPS4Yrr_REV:
12307 case VFMSUBPS4mr:
12308 case VFMSUBPS4rm:
12309 case VFMSUBPS4rr:
12310 case VFMSUBPS4rr_REV:
12311 return true;
12312 }
12313 return false;
12314}
12315
12316bool isVPBLENDW(unsigned Opcode) {
12317 switch (Opcode) {
12318 case VPBLENDWYrmi:
12319 case VPBLENDWYrri:
12320 case VPBLENDWrmi:
12321 case VPBLENDWrri:
12322 return true;
12323 }
12324 return false;
12325}
12326
12327bool isBZHI(unsigned Opcode) {
12328 switch (Opcode) {
12329 case BZHI32rm:
12330 case BZHI32rm_EVEX:
12331 case BZHI32rm_NF:
12332 case BZHI32rr:
12333 case BZHI32rr_EVEX:
12334 case BZHI32rr_NF:
12335 case BZHI64rm:
12336 case BZHI64rm_EVEX:
12337 case BZHI64rm_NF:
12338 case BZHI64rr:
12339 case BZHI64rr_EVEX:
12340 case BZHI64rr_NF:
12341 return true;
12342 }
12343 return false;
12344}
12345
12346bool isVPRORVD(unsigned Opcode) {
12347 switch (Opcode) {
12348 case VPRORVDZ128rm:
12349 case VPRORVDZ128rmb:
12350 case VPRORVDZ128rmbk:
12351 case VPRORVDZ128rmbkz:
12352 case VPRORVDZ128rmk:
12353 case VPRORVDZ128rmkz:
12354 case VPRORVDZ128rr:
12355 case VPRORVDZ128rrk:
12356 case VPRORVDZ128rrkz:
12357 case VPRORVDZ256rm:
12358 case VPRORVDZ256rmb:
12359 case VPRORVDZ256rmbk:
12360 case VPRORVDZ256rmbkz:
12361 case VPRORVDZ256rmk:
12362 case VPRORVDZ256rmkz:
12363 case VPRORVDZ256rr:
12364 case VPRORVDZ256rrk:
12365 case VPRORVDZ256rrkz:
12366 case VPRORVDZrm:
12367 case VPRORVDZrmb:
12368 case VPRORVDZrmbk:
12369 case VPRORVDZrmbkz:
12370 case VPRORVDZrmk:
12371 case VPRORVDZrmkz:
12372 case VPRORVDZrr:
12373 case VPRORVDZrrk:
12374 case VPRORVDZrrkz:
12375 return true;
12376 }
12377 return false;
12378}
12379
12380bool isRMPQUERY(unsigned Opcode) {
12381 return Opcode == RMPQUERY;
12382}
12383
12384bool isVPEXPANDB(unsigned Opcode) {
12385 switch (Opcode) {
12386 case VPEXPANDBZ128rm:
12387 case VPEXPANDBZ128rmk:
12388 case VPEXPANDBZ128rmkz:
12389 case VPEXPANDBZ128rr:
12390 case VPEXPANDBZ128rrk:
12391 case VPEXPANDBZ128rrkz:
12392 case VPEXPANDBZ256rm:
12393 case VPEXPANDBZ256rmk:
12394 case VPEXPANDBZ256rmkz:
12395 case VPEXPANDBZ256rr:
12396 case VPEXPANDBZ256rrk:
12397 case VPEXPANDBZ256rrkz:
12398 case VPEXPANDBZrm:
12399 case VPEXPANDBZrmk:
12400 case VPEXPANDBZrmkz:
12401 case VPEXPANDBZrr:
12402 case VPEXPANDBZrrk:
12403 case VPEXPANDBZrrkz:
12404 return true;
12405 }
12406 return false;
12407}
12408
12409bool isVPSCATTERDQ(unsigned Opcode) {
12410 switch (Opcode) {
12411 case VPSCATTERDQZ128mr:
12412 case VPSCATTERDQZ256mr:
12413 case VPSCATTERDQZmr:
12414 return true;
12415 }
12416 return false;
12417}
12418
12419bool isPSMASH(unsigned Opcode) {
12420 return Opcode == PSMASH;
12421}
12422
12423bool isVPSHLDQ(unsigned Opcode) {
12424 switch (Opcode) {
12425 case VPSHLDQZ128rmbi:
12426 case VPSHLDQZ128rmbik:
12427 case VPSHLDQZ128rmbikz:
12428 case VPSHLDQZ128rmi:
12429 case VPSHLDQZ128rmik:
12430 case VPSHLDQZ128rmikz:
12431 case VPSHLDQZ128rri:
12432 case VPSHLDQZ128rrik:
12433 case VPSHLDQZ128rrikz:
12434 case VPSHLDQZ256rmbi:
12435 case VPSHLDQZ256rmbik:
12436 case VPSHLDQZ256rmbikz:
12437 case VPSHLDQZ256rmi:
12438 case VPSHLDQZ256rmik:
12439 case VPSHLDQZ256rmikz:
12440 case VPSHLDQZ256rri:
12441 case VPSHLDQZ256rrik:
12442 case VPSHLDQZ256rrikz:
12443 case VPSHLDQZrmbi:
12444 case VPSHLDQZrmbik:
12445 case VPSHLDQZrmbikz:
12446 case VPSHLDQZrmi:
12447 case VPSHLDQZrmik:
12448 case VPSHLDQZrmikz:
12449 case VPSHLDQZrri:
12450 case VPSHLDQZrrik:
12451 case VPSHLDQZrrikz:
12452 return true;
12453 }
12454 return false;
12455}
12456
12457bool isVSCATTERPF1DPD(unsigned Opcode) {
12458 return Opcode == VSCATTERPF1DPDm;
12459}
12460
12461bool isMONTMUL(unsigned Opcode) {
12462 return Opcode == MONTMUL;
12463}
12464
12465bool isVCVTPH2UQQ(unsigned Opcode) {
12466 switch (Opcode) {
12467 case VCVTPH2UQQZ128rm:
12468 case VCVTPH2UQQZ128rmb:
12469 case VCVTPH2UQQZ128rmbk:
12470 case VCVTPH2UQQZ128rmbkz:
12471 case VCVTPH2UQQZ128rmk:
12472 case VCVTPH2UQQZ128rmkz:
12473 case VCVTPH2UQQZ128rr:
12474 case VCVTPH2UQQZ128rrk:
12475 case VCVTPH2UQQZ128rrkz:
12476 case VCVTPH2UQQZ256rm:
12477 case VCVTPH2UQQZ256rmb:
12478 case VCVTPH2UQQZ256rmbk:
12479 case VCVTPH2UQQZ256rmbkz:
12480 case VCVTPH2UQQZ256rmk:
12481 case VCVTPH2UQQZ256rmkz:
12482 case VCVTPH2UQQZ256rr:
12483 case VCVTPH2UQQZ256rrk:
12484 case VCVTPH2UQQZ256rrkz:
12485 case VCVTPH2UQQZrm:
12486 case VCVTPH2UQQZrmb:
12487 case VCVTPH2UQQZrmbk:
12488 case VCVTPH2UQQZrmbkz:
12489 case VCVTPH2UQQZrmk:
12490 case VCVTPH2UQQZrmkz:
12491 case VCVTPH2UQQZrr:
12492 case VCVTPH2UQQZrrb:
12493 case VCVTPH2UQQZrrbk:
12494 case VCVTPH2UQQZrrbkz:
12495 case VCVTPH2UQQZrrk:
12496 case VCVTPH2UQQZrrkz:
12497 return true;
12498 }
12499 return false;
12500}
12501
12502bool isPSLLD(unsigned Opcode) {
12503 switch (Opcode) {
12504 case MMX_PSLLDri:
12505 case MMX_PSLLDrm:
12506 case MMX_PSLLDrr:
12507 case PSLLDri:
12508 case PSLLDrm:
12509 case PSLLDrr:
12510 return true;
12511 }
12512 return false;
12513}
12514
12515bool isSAR(unsigned Opcode) {
12516 switch (Opcode) {
12517 case SAR16m1:
12518 case SAR16m1_EVEX:
12519 case SAR16m1_ND:
12520 case SAR16m1_NF:
12521 case SAR16m1_NF_ND:
12522 case SAR16mCL:
12523 case SAR16mCL_EVEX:
12524 case SAR16mCL_ND:
12525 case SAR16mCL_NF:
12526 case SAR16mCL_NF_ND:
12527 case SAR16mi:
12528 case SAR16mi_EVEX:
12529 case SAR16mi_ND:
12530 case SAR16mi_NF:
12531 case SAR16mi_NF_ND:
12532 case SAR16r1:
12533 case SAR16r1_EVEX:
12534 case SAR16r1_ND:
12535 case SAR16r1_NF:
12536 case SAR16r1_NF_ND:
12537 case SAR16rCL:
12538 case SAR16rCL_EVEX:
12539 case SAR16rCL_ND:
12540 case SAR16rCL_NF:
12541 case SAR16rCL_NF_ND:
12542 case SAR16ri:
12543 case SAR16ri_EVEX:
12544 case SAR16ri_ND:
12545 case SAR16ri_NF:
12546 case SAR16ri_NF_ND:
12547 case SAR32m1:
12548 case SAR32m1_EVEX:
12549 case SAR32m1_ND:
12550 case SAR32m1_NF:
12551 case SAR32m1_NF_ND:
12552 case SAR32mCL:
12553 case SAR32mCL_EVEX:
12554 case SAR32mCL_ND:
12555 case SAR32mCL_NF:
12556 case SAR32mCL_NF_ND:
12557 case SAR32mi:
12558 case SAR32mi_EVEX:
12559 case SAR32mi_ND:
12560 case SAR32mi_NF:
12561 case SAR32mi_NF_ND:
12562 case SAR32r1:
12563 case SAR32r1_EVEX:
12564 case SAR32r1_ND:
12565 case SAR32r1_NF:
12566 case SAR32r1_NF_ND:
12567 case SAR32rCL:
12568 case SAR32rCL_EVEX:
12569 case SAR32rCL_ND:
12570 case SAR32rCL_NF:
12571 case SAR32rCL_NF_ND:
12572 case SAR32ri:
12573 case SAR32ri_EVEX:
12574 case SAR32ri_ND:
12575 case SAR32ri_NF:
12576 case SAR32ri_NF_ND:
12577 case SAR64m1:
12578 case SAR64m1_EVEX:
12579 case SAR64m1_ND:
12580 case SAR64m1_NF:
12581 case SAR64m1_NF_ND:
12582 case SAR64mCL:
12583 case SAR64mCL_EVEX:
12584 case SAR64mCL_ND:
12585 case SAR64mCL_NF:
12586 case SAR64mCL_NF_ND:
12587 case SAR64mi:
12588 case SAR64mi_EVEX:
12589 case SAR64mi_ND:
12590 case SAR64mi_NF:
12591 case SAR64mi_NF_ND:
12592 case SAR64r1:
12593 case SAR64r1_EVEX:
12594 case SAR64r1_ND:
12595 case SAR64r1_NF:
12596 case SAR64r1_NF_ND:
12597 case SAR64rCL:
12598 case SAR64rCL_EVEX:
12599 case SAR64rCL_ND:
12600 case SAR64rCL_NF:
12601 case SAR64rCL_NF_ND:
12602 case SAR64ri:
12603 case SAR64ri_EVEX:
12604 case SAR64ri_ND:
12605 case SAR64ri_NF:
12606 case SAR64ri_NF_ND:
12607 case SAR8m1:
12608 case SAR8m1_EVEX:
12609 case SAR8m1_ND:
12610 case SAR8m1_NF:
12611 case SAR8m1_NF_ND:
12612 case SAR8mCL:
12613 case SAR8mCL_EVEX:
12614 case SAR8mCL_ND:
12615 case SAR8mCL_NF:
12616 case SAR8mCL_NF_ND:
12617 case SAR8mi:
12618 case SAR8mi_EVEX:
12619 case SAR8mi_ND:
12620 case SAR8mi_NF:
12621 case SAR8mi_NF_ND:
12622 case SAR8r1:
12623 case SAR8r1_EVEX:
12624 case SAR8r1_ND:
12625 case SAR8r1_NF:
12626 case SAR8r1_NF_ND:
12627 case SAR8rCL:
12628 case SAR8rCL_EVEX:
12629 case SAR8rCL_ND:
12630 case SAR8rCL_NF:
12631 case SAR8rCL_NF_ND:
12632 case SAR8ri:
12633 case SAR8ri_EVEX:
12634 case SAR8ri_ND:
12635 case SAR8ri_NF:
12636 case SAR8ri_NF_ND:
12637 return true;
12638 }
12639 return false;
12640}
12641
12642bool isLDTILECFG(unsigned Opcode) {
12643 switch (Opcode) {
12644 case LDTILECFG:
12645 case LDTILECFG_EVEX:
12646 return true;
12647 }
12648 return false;
12649}
12650
12651bool isPMINUB(unsigned Opcode) {
12652 switch (Opcode) {
12653 case MMX_PMINUBrm:
12654 case MMX_PMINUBrr:
12655 case PMINUBrm:
12656 case PMINUBrr:
12657 return true;
12658 }
12659 return false;
12660}
12661
12662bool isVCVTNEEBF162PS(unsigned Opcode) {
12663 switch (Opcode) {
12664 case VCVTNEEBF162PSYrm:
12665 case VCVTNEEBF162PSrm:
12666 return true;
12667 }
12668 return false;
12669}
12670
12671bool isMOVDIR64B(unsigned Opcode) {
12672 switch (Opcode) {
12673 case MOVDIR64B16:
12674 case MOVDIR64B32:
12675 case MOVDIR64B32_EVEX:
12676 case MOVDIR64B64:
12677 case MOVDIR64B64_EVEX:
12678 return true;
12679 }
12680 return false;
12681}
12682
12683bool isSTR(unsigned Opcode) {
12684 switch (Opcode) {
12685 case STR16r:
12686 case STR32r:
12687 case STR64r:
12688 case STRm:
12689 return true;
12690 }
12691 return false;
12692}
12693
12694bool isKANDNQ(unsigned Opcode) {
12695 return Opcode == KANDNQkk;
12696}
12697
12698bool isBSF(unsigned Opcode) {
12699 switch (Opcode) {
12700 case BSF16rm:
12701 case BSF16rr:
12702 case BSF32rm:
12703 case BSF32rr:
12704 case BSF64rm:
12705 case BSF64rr:
12706 return true;
12707 }
12708 return false;
12709}
12710
12711bool isVPDPBUUDS(unsigned Opcode) {
12712 switch (Opcode) {
12713 case VPDPBUUDSYrm:
12714 case VPDPBUUDSYrr:
12715 case VPDPBUUDSZ128rm:
12716 case VPDPBUUDSZ128rmb:
12717 case VPDPBUUDSZ128rmbk:
12718 case VPDPBUUDSZ128rmbkz:
12719 case VPDPBUUDSZ128rmk:
12720 case VPDPBUUDSZ128rmkz:
12721 case VPDPBUUDSZ128rr:
12722 case VPDPBUUDSZ128rrk:
12723 case VPDPBUUDSZ128rrkz:
12724 case VPDPBUUDSZ256rm:
12725 case VPDPBUUDSZ256rmb:
12726 case VPDPBUUDSZ256rmbk:
12727 case VPDPBUUDSZ256rmbkz:
12728 case VPDPBUUDSZ256rmk:
12729 case VPDPBUUDSZ256rmkz:
12730 case VPDPBUUDSZ256rr:
12731 case VPDPBUUDSZ256rrk:
12732 case VPDPBUUDSZ256rrkz:
12733 case VPDPBUUDSZrm:
12734 case VPDPBUUDSZrmb:
12735 case VPDPBUUDSZrmbk:
12736 case VPDPBUUDSZrmbkz:
12737 case VPDPBUUDSZrmk:
12738 case VPDPBUUDSZrmkz:
12739 case VPDPBUUDSZrr:
12740 case VPDPBUUDSZrrk:
12741 case VPDPBUUDSZrrkz:
12742 case VPDPBUUDSrm:
12743 case VPDPBUUDSrr:
12744 return true;
12745 }
12746 return false;
12747}
12748
12749bool isINCSSPD(unsigned Opcode) {
12750 return Opcode == INCSSPD;
12751}
12752
12753bool isSQRTPS(unsigned Opcode) {
12754 switch (Opcode) {
12755 case SQRTPSm:
12756 case SQRTPSr:
12757 return true;
12758 }
12759 return false;
12760}
12761
12762bool isCMPXCHG(unsigned Opcode) {
12763 switch (Opcode) {
12764 case CMPXCHG16rm:
12765 case CMPXCHG16rr:
12766 case CMPXCHG32rm:
12767 case CMPXCHG32rr:
12768 case CMPXCHG64rm:
12769 case CMPXCHG64rr:
12770 case CMPXCHG8rm:
12771 case CMPXCHG8rr:
12772 return true;
12773 }
12774 return false;
12775}
12776
12777bool isVPSIGNW(unsigned Opcode) {
12778 switch (Opcode) {
12779 case VPSIGNWYrm:
12780 case VPSIGNWYrr:
12781 case VPSIGNWrm:
12782 case VPSIGNWrr:
12783 return true;
12784 }
12785 return false;
12786}
12787
12788bool isVCOMISBF16(unsigned Opcode) {
12789 switch (Opcode) {
12790 case VCOMISBF16Zrm:
12791 case VCOMISBF16Zrr:
12792 return true;
12793 }
12794 return false;
12795}
12796
12797bool isLES(unsigned Opcode) {
12798 switch (Opcode) {
12799 case LES16rm:
12800 case LES32rm:
12801 return true;
12802 }
12803 return false;
12804}
12805
12806bool isCVTSS2SI(unsigned Opcode) {
12807 switch (Opcode) {
12808 case CVTSS2SI64rm_Int:
12809 case CVTSS2SI64rr_Int:
12810 case CVTSS2SIrm_Int:
12811 case CVTSS2SIrr_Int:
12812 return true;
12813 }
12814 return false;
12815}
12816
12817bool isVPMOVUSWB(unsigned Opcode) {
12818 switch (Opcode) {
12819 case VPMOVUSWBZ128mr:
12820 case VPMOVUSWBZ128mrk:
12821 case VPMOVUSWBZ128rr:
12822 case VPMOVUSWBZ128rrk:
12823 case VPMOVUSWBZ128rrkz:
12824 case VPMOVUSWBZ256mr:
12825 case VPMOVUSWBZ256mrk:
12826 case VPMOVUSWBZ256rr:
12827 case VPMOVUSWBZ256rrk:
12828 case VPMOVUSWBZ256rrkz:
12829 case VPMOVUSWBZmr:
12830 case VPMOVUSWBZmrk:
12831 case VPMOVUSWBZrr:
12832 case VPMOVUSWBZrrk:
12833 case VPMOVUSWBZrrkz:
12834 return true;
12835 }
12836 return false;
12837}
12838
12839bool isFCOMPI(unsigned Opcode) {
12840 return Opcode == COM_FIPr;
12841}
12842
12843bool isPUNPCKHWD(unsigned Opcode) {
12844 switch (Opcode) {
12845 case MMX_PUNPCKHWDrm:
12846 case MMX_PUNPCKHWDrr:
12847 case PUNPCKHWDrm:
12848 case PUNPCKHWDrr:
12849 return true;
12850 }
12851 return false;
12852}
12853
12854bool isPFACC(unsigned Opcode) {
12855 switch (Opcode) {
12856 case PFACCrm:
12857 case PFACCrr:
12858 return true;
12859 }
12860 return false;
12861}
12862
12863bool isVPTESTNMW(unsigned Opcode) {
12864 switch (Opcode) {
12865 case VPTESTNMWZ128rm:
12866 case VPTESTNMWZ128rmk:
12867 case VPTESTNMWZ128rr:
12868 case VPTESTNMWZ128rrk:
12869 case VPTESTNMWZ256rm:
12870 case VPTESTNMWZ256rmk:
12871 case VPTESTNMWZ256rr:
12872 case VPTESTNMWZ256rrk:
12873 case VPTESTNMWZrm:
12874 case VPTESTNMWZrmk:
12875 case VPTESTNMWZrr:
12876 case VPTESTNMWZrrk:
12877 return true;
12878 }
12879 return false;
12880}
12881
12882bool isVPMULDQ(unsigned Opcode) {
12883 switch (Opcode) {
12884 case VPMULDQYrm:
12885 case VPMULDQYrr:
12886 case VPMULDQZ128rm:
12887 case VPMULDQZ128rmb:
12888 case VPMULDQZ128rmbk:
12889 case VPMULDQZ128rmbkz:
12890 case VPMULDQZ128rmk:
12891 case VPMULDQZ128rmkz:
12892 case VPMULDQZ128rr:
12893 case VPMULDQZ128rrk:
12894 case VPMULDQZ128rrkz:
12895 case VPMULDQZ256rm:
12896 case VPMULDQZ256rmb:
12897 case VPMULDQZ256rmbk:
12898 case VPMULDQZ256rmbkz:
12899 case VPMULDQZ256rmk:
12900 case VPMULDQZ256rmkz:
12901 case VPMULDQZ256rr:
12902 case VPMULDQZ256rrk:
12903 case VPMULDQZ256rrkz:
12904 case VPMULDQZrm:
12905 case VPMULDQZrmb:
12906 case VPMULDQZrmbk:
12907 case VPMULDQZrmbkz:
12908 case VPMULDQZrmk:
12909 case VPMULDQZrmkz:
12910 case VPMULDQZrr:
12911 case VPMULDQZrrk:
12912 case VPMULDQZrrkz:
12913 case VPMULDQrm:
12914 case VPMULDQrr:
12915 return true;
12916 }
12917 return false;
12918}
12919
12920bool isSHRX(unsigned Opcode) {
12921 switch (Opcode) {
12922 case SHRX32rm:
12923 case SHRX32rm_EVEX:
12924 case SHRX32rr:
12925 case SHRX32rr_EVEX:
12926 case SHRX64rm:
12927 case SHRX64rm_EVEX:
12928 case SHRX64rr:
12929 case SHRX64rr_EVEX:
12930 return true;
12931 }
12932 return false;
12933}
12934
12935bool isKXORQ(unsigned Opcode) {
12936 return Opcode == KXORQkk;
12937}
12938
12939bool isVGETEXPSD(unsigned Opcode) {
12940 switch (Opcode) {
12941 case VGETEXPSDZm:
12942 case VGETEXPSDZmk:
12943 case VGETEXPSDZmkz:
12944 case VGETEXPSDZr:
12945 case VGETEXPSDZrb:
12946 case VGETEXPSDZrbk:
12947 case VGETEXPSDZrbkz:
12948 case VGETEXPSDZrk:
12949 case VGETEXPSDZrkz:
12950 return true;
12951 }
12952 return false;
12953}
12954
12955bool isV4FNMADDPS(unsigned Opcode) {
12956 switch (Opcode) {
12957 case V4FNMADDPSrm:
12958 case V4FNMADDPSrmk:
12959 case V4FNMADDPSrmkz:
12960 return true;
12961 }
12962 return false;
12963}
12964
12965bool isVFNMSUB231SD(unsigned Opcode) {
12966 switch (Opcode) {
12967 case VFNMSUB231SDZm_Int:
12968 case VFNMSUB231SDZmk_Int:
12969 case VFNMSUB231SDZmkz_Int:
12970 case VFNMSUB231SDZr_Int:
12971 case VFNMSUB231SDZrb_Int:
12972 case VFNMSUB231SDZrbk_Int:
12973 case VFNMSUB231SDZrbkz_Int:
12974 case VFNMSUB231SDZrk_Int:
12975 case VFNMSUB231SDZrkz_Int:
12976 case VFNMSUB231SDm_Int:
12977 case VFNMSUB231SDr_Int:
12978 return true;
12979 }
12980 return false;
12981}
12982
12983bool isVPSHLD(unsigned Opcode) {
12984 switch (Opcode) {
12985 case VPSHLDmr:
12986 case VPSHLDrm:
12987 case VPSHLDrr:
12988 case VPSHLDrr_REV:
12989 return true;
12990 }
12991 return false;
12992}
12993
12994bool isPAVGB(unsigned Opcode) {
12995 switch (Opcode) {
12996 case MMX_PAVGBrm:
12997 case MMX_PAVGBrr:
12998 case PAVGBrm:
12999 case PAVGBrr:
13000 return true;
13001 }
13002 return false;
13003}
13004
13005bool isPMOVZXBD(unsigned Opcode) {
13006 switch (Opcode) {
13007 case PMOVZXBDrm:
13008 case PMOVZXBDrr:
13009 return true;
13010 }
13011 return false;
13012}
13013
13014bool isKORTESTW(unsigned Opcode) {
13015 return Opcode == KORTESTWkk;
13016}
13017
13018bool isVSHUFPS(unsigned Opcode) {
13019 switch (Opcode) {
13020 case VSHUFPSYrmi:
13021 case VSHUFPSYrri:
13022 case VSHUFPSZ128rmbi:
13023 case VSHUFPSZ128rmbik:
13024 case VSHUFPSZ128rmbikz:
13025 case VSHUFPSZ128rmi:
13026 case VSHUFPSZ128rmik:
13027 case VSHUFPSZ128rmikz:
13028 case VSHUFPSZ128rri:
13029 case VSHUFPSZ128rrik:
13030 case VSHUFPSZ128rrikz:
13031 case VSHUFPSZ256rmbi:
13032 case VSHUFPSZ256rmbik:
13033 case VSHUFPSZ256rmbikz:
13034 case VSHUFPSZ256rmi:
13035 case VSHUFPSZ256rmik:
13036 case VSHUFPSZ256rmikz:
13037 case VSHUFPSZ256rri:
13038 case VSHUFPSZ256rrik:
13039 case VSHUFPSZ256rrikz:
13040 case VSHUFPSZrmbi:
13041 case VSHUFPSZrmbik:
13042 case VSHUFPSZrmbikz:
13043 case VSHUFPSZrmi:
13044 case VSHUFPSZrmik:
13045 case VSHUFPSZrmikz:
13046 case VSHUFPSZrri:
13047 case VSHUFPSZrrik:
13048 case VSHUFPSZrrikz:
13049 case VSHUFPSrmi:
13050 case VSHUFPSrri:
13051 return true;
13052 }
13053 return false;
13054}
13055
13056bool isAESENCWIDE128KL(unsigned Opcode) {
13057 return Opcode == AESENCWIDE128KL;
13058}
13059
13060bool isVPXORD(unsigned Opcode) {
13061 switch (Opcode) {
13062 case VPXORDZ128rm:
13063 case VPXORDZ128rmb:
13064 case VPXORDZ128rmbk:
13065 case VPXORDZ128rmbkz:
13066 case VPXORDZ128rmk:
13067 case VPXORDZ128rmkz:
13068 case VPXORDZ128rr:
13069 case VPXORDZ128rrk:
13070 case VPXORDZ128rrkz:
13071 case VPXORDZ256rm:
13072 case VPXORDZ256rmb:
13073 case VPXORDZ256rmbk:
13074 case VPXORDZ256rmbkz:
13075 case VPXORDZ256rmk:
13076 case VPXORDZ256rmkz:
13077 case VPXORDZ256rr:
13078 case VPXORDZ256rrk:
13079 case VPXORDZ256rrkz:
13080 case VPXORDZrm:
13081 case VPXORDZrmb:
13082 case VPXORDZrmbk:
13083 case VPXORDZrmbkz:
13084 case VPXORDZrmk:
13085 case VPXORDZrmkz:
13086 case VPXORDZrr:
13087 case VPXORDZrrk:
13088 case VPXORDZrrkz:
13089 return true;
13090 }
13091 return false;
13092}
13093
13094bool isVPSHAW(unsigned Opcode) {
13095 switch (Opcode) {
13096 case VPSHAWmr:
13097 case VPSHAWrm:
13098 case VPSHAWrr:
13099 case VPSHAWrr_REV:
13100 return true;
13101 }
13102 return false;
13103}
13104
13105bool isVFMSUB132BF16(unsigned Opcode) {
13106 switch (Opcode) {
13107 case VFMSUB132BF16Z128m:
13108 case VFMSUB132BF16Z128mb:
13109 case VFMSUB132BF16Z128mbk:
13110 case VFMSUB132BF16Z128mbkz:
13111 case VFMSUB132BF16Z128mk:
13112 case VFMSUB132BF16Z128mkz:
13113 case VFMSUB132BF16Z128r:
13114 case VFMSUB132BF16Z128rk:
13115 case VFMSUB132BF16Z128rkz:
13116 case VFMSUB132BF16Z256m:
13117 case VFMSUB132BF16Z256mb:
13118 case VFMSUB132BF16Z256mbk:
13119 case VFMSUB132BF16Z256mbkz:
13120 case VFMSUB132BF16Z256mk:
13121 case VFMSUB132BF16Z256mkz:
13122 case VFMSUB132BF16Z256r:
13123 case VFMSUB132BF16Z256rk:
13124 case VFMSUB132BF16Z256rkz:
13125 case VFMSUB132BF16Zm:
13126 case VFMSUB132BF16Zmb:
13127 case VFMSUB132BF16Zmbk:
13128 case VFMSUB132BF16Zmbkz:
13129 case VFMSUB132BF16Zmk:
13130 case VFMSUB132BF16Zmkz:
13131 case VFMSUB132BF16Zr:
13132 case VFMSUB132BF16Zrk:
13133 case VFMSUB132BF16Zrkz:
13134 return true;
13135 }
13136 return false;
13137}
13138
13139bool isVPERMT2B(unsigned Opcode) {
13140 switch (Opcode) {
13141 case VPERMT2BZ128rm:
13142 case VPERMT2BZ128rmk:
13143 case VPERMT2BZ128rmkz:
13144 case VPERMT2BZ128rr:
13145 case VPERMT2BZ128rrk:
13146 case VPERMT2BZ128rrkz:
13147 case VPERMT2BZ256rm:
13148 case VPERMT2BZ256rmk:
13149 case VPERMT2BZ256rmkz:
13150 case VPERMT2BZ256rr:
13151 case VPERMT2BZ256rrk:
13152 case VPERMT2BZ256rrkz:
13153 case VPERMT2BZrm:
13154 case VPERMT2BZrmk:
13155 case VPERMT2BZrmkz:
13156 case VPERMT2BZrr:
13157 case VPERMT2BZrrk:
13158 case VPERMT2BZrrkz:
13159 return true;
13160 }
13161 return false;
13162}
13163
13164bool isVFMADD213PD(unsigned Opcode) {
13165 switch (Opcode) {
13166 case VFMADD213PDYm:
13167 case VFMADD213PDYr:
13168 case VFMADD213PDZ128m:
13169 case VFMADD213PDZ128mb:
13170 case VFMADD213PDZ128mbk:
13171 case VFMADD213PDZ128mbkz:
13172 case VFMADD213PDZ128mk:
13173 case VFMADD213PDZ128mkz:
13174 case VFMADD213PDZ128r:
13175 case VFMADD213PDZ128rk:
13176 case VFMADD213PDZ128rkz:
13177 case VFMADD213PDZ256m:
13178 case VFMADD213PDZ256mb:
13179 case VFMADD213PDZ256mbk:
13180 case VFMADD213PDZ256mbkz:
13181 case VFMADD213PDZ256mk:
13182 case VFMADD213PDZ256mkz:
13183 case VFMADD213PDZ256r:
13184 case VFMADD213PDZ256rk:
13185 case VFMADD213PDZ256rkz:
13186 case VFMADD213PDZm:
13187 case VFMADD213PDZmb:
13188 case VFMADD213PDZmbk:
13189 case VFMADD213PDZmbkz:
13190 case VFMADD213PDZmk:
13191 case VFMADD213PDZmkz:
13192 case VFMADD213PDZr:
13193 case VFMADD213PDZrb:
13194 case VFMADD213PDZrbk:
13195 case VFMADD213PDZrbkz:
13196 case VFMADD213PDZrk:
13197 case VFMADD213PDZrkz:
13198 case VFMADD213PDm:
13199 case VFMADD213PDr:
13200 return true;
13201 }
13202 return false;
13203}
13204
13205bool isVPGATHERQD(unsigned Opcode) {
13206 switch (Opcode) {
13207 case VPGATHERQDYrm:
13208 case VPGATHERQDZ128rm:
13209 case VPGATHERQDZ256rm:
13210 case VPGATHERQDZrm:
13211 case VPGATHERQDrm:
13212 return true;
13213 }
13214 return false;
13215}
13216
13217bool isVFNMSUB213BF16(unsigned Opcode) {
13218 switch (Opcode) {
13219 case VFNMSUB213BF16Z128m:
13220 case VFNMSUB213BF16Z128mb:
13221 case VFNMSUB213BF16Z128mbk:
13222 case VFNMSUB213BF16Z128mbkz:
13223 case VFNMSUB213BF16Z128mk:
13224 case VFNMSUB213BF16Z128mkz:
13225 case VFNMSUB213BF16Z128r:
13226 case VFNMSUB213BF16Z128rk:
13227 case VFNMSUB213BF16Z128rkz:
13228 case VFNMSUB213BF16Z256m:
13229 case VFNMSUB213BF16Z256mb:
13230 case VFNMSUB213BF16Z256mbk:
13231 case VFNMSUB213BF16Z256mbkz:
13232 case VFNMSUB213BF16Z256mk:
13233 case VFNMSUB213BF16Z256mkz:
13234 case VFNMSUB213BF16Z256r:
13235 case VFNMSUB213BF16Z256rk:
13236 case VFNMSUB213BF16Z256rkz:
13237 case VFNMSUB213BF16Zm:
13238 case VFNMSUB213BF16Zmb:
13239 case VFNMSUB213BF16Zmbk:
13240 case VFNMSUB213BF16Zmbkz:
13241 case VFNMSUB213BF16Zmk:
13242 case VFNMSUB213BF16Zmkz:
13243 case VFNMSUB213BF16Zr:
13244 case VFNMSUB213BF16Zrk:
13245 case VFNMSUB213BF16Zrkz:
13246 return true;
13247 }
13248 return false;
13249}
13250
13251bool isVCVTPS2IBS(unsigned Opcode) {
13252 switch (Opcode) {
13253 case VCVTPS2IBSZ128rm:
13254 case VCVTPS2IBSZ128rmb:
13255 case VCVTPS2IBSZ128rmbk:
13256 case VCVTPS2IBSZ128rmbkz:
13257 case VCVTPS2IBSZ128rmk:
13258 case VCVTPS2IBSZ128rmkz:
13259 case VCVTPS2IBSZ128rr:
13260 case VCVTPS2IBSZ128rrk:
13261 case VCVTPS2IBSZ128rrkz:
13262 case VCVTPS2IBSZ256rm:
13263 case VCVTPS2IBSZ256rmb:
13264 case VCVTPS2IBSZ256rmbk:
13265 case VCVTPS2IBSZ256rmbkz:
13266 case VCVTPS2IBSZ256rmk:
13267 case VCVTPS2IBSZ256rmkz:
13268 case VCVTPS2IBSZ256rr:
13269 case VCVTPS2IBSZ256rrk:
13270 case VCVTPS2IBSZ256rrkz:
13271 case VCVTPS2IBSZrm:
13272 case VCVTPS2IBSZrmb:
13273 case VCVTPS2IBSZrmbk:
13274 case VCVTPS2IBSZrmbkz:
13275 case VCVTPS2IBSZrmk:
13276 case VCVTPS2IBSZrmkz:
13277 case VCVTPS2IBSZrr:
13278 case VCVTPS2IBSZrrb:
13279 case VCVTPS2IBSZrrbk:
13280 case VCVTPS2IBSZrrbkz:
13281 case VCVTPS2IBSZrrk:
13282 case VCVTPS2IBSZrrkz:
13283 return true;
13284 }
13285 return false;
13286}
13287
13288bool isVPCMPGTW(unsigned Opcode) {
13289 switch (Opcode) {
13290 case VPCMPGTWYrm:
13291 case VPCMPGTWYrr:
13292 case VPCMPGTWZ128rm:
13293 case VPCMPGTWZ128rmk:
13294 case VPCMPGTWZ128rr:
13295 case VPCMPGTWZ128rrk:
13296 case VPCMPGTWZ256rm:
13297 case VPCMPGTWZ256rmk:
13298 case VPCMPGTWZ256rr:
13299 case VPCMPGTWZ256rrk:
13300 case VPCMPGTWZrm:
13301 case VPCMPGTWZrmk:
13302 case VPCMPGTWZrr:
13303 case VPCMPGTWZrrk:
13304 case VPCMPGTWrm:
13305 case VPCMPGTWrr:
13306 return true;
13307 }
13308 return false;
13309}
13310
13311bool isVMOVRSB(unsigned Opcode) {
13312 switch (Opcode) {
13313 case VMOVRSBZ128m:
13314 case VMOVRSBZ128mk:
13315 case VMOVRSBZ128mkz:
13316 case VMOVRSBZ256m:
13317 case VMOVRSBZ256mk:
13318 case VMOVRSBZ256mkz:
13319 case VMOVRSBZm:
13320 case VMOVRSBZmk:
13321 case VMOVRSBZmkz:
13322 return true;
13323 }
13324 return false;
13325}
13326
13327bool isVGETMANTSH(unsigned Opcode) {
13328 switch (Opcode) {
13329 case VGETMANTSHZrmi:
13330 case VGETMANTSHZrmik:
13331 case VGETMANTSHZrmikz:
13332 case VGETMANTSHZrri:
13333 case VGETMANTSHZrrib:
13334 case VGETMANTSHZrribk:
13335 case VGETMANTSHZrribkz:
13336 case VGETMANTSHZrrik:
13337 case VGETMANTSHZrrikz:
13338 return true;
13339 }
13340 return false;
13341}
13342
13343bool isVANDPS(unsigned Opcode) {
13344 switch (Opcode) {
13345 case VANDPSYrm:
13346 case VANDPSYrr:
13347 case VANDPSZ128rm:
13348 case VANDPSZ128rmb:
13349 case VANDPSZ128rmbk:
13350 case VANDPSZ128rmbkz:
13351 case VANDPSZ128rmk:
13352 case VANDPSZ128rmkz:
13353 case VANDPSZ128rr:
13354 case VANDPSZ128rrk:
13355 case VANDPSZ128rrkz:
13356 case VANDPSZ256rm:
13357 case VANDPSZ256rmb:
13358 case VANDPSZ256rmbk:
13359 case VANDPSZ256rmbkz:
13360 case VANDPSZ256rmk:
13361 case VANDPSZ256rmkz:
13362 case VANDPSZ256rr:
13363 case VANDPSZ256rrk:
13364 case VANDPSZ256rrkz:
13365 case VANDPSZrm:
13366 case VANDPSZrmb:
13367 case VANDPSZrmbk:
13368 case VANDPSZrmbkz:
13369 case VANDPSZrmk:
13370 case VANDPSZrmkz:
13371 case VANDPSZrr:
13372 case VANDPSZrrk:
13373 case VANDPSZrrkz:
13374 case VANDPSrm:
13375 case VANDPSrr:
13376 return true;
13377 }
13378 return false;
13379}
13380
13381bool isVDIVPS(unsigned Opcode) {
13382 switch (Opcode) {
13383 case VDIVPSYrm:
13384 case VDIVPSYrr:
13385 case VDIVPSZ128rm:
13386 case VDIVPSZ128rmb:
13387 case VDIVPSZ128rmbk:
13388 case VDIVPSZ128rmbkz:
13389 case VDIVPSZ128rmk:
13390 case VDIVPSZ128rmkz:
13391 case VDIVPSZ128rr:
13392 case VDIVPSZ128rrk:
13393 case VDIVPSZ128rrkz:
13394 case VDIVPSZ256rm:
13395 case VDIVPSZ256rmb:
13396 case VDIVPSZ256rmbk:
13397 case VDIVPSZ256rmbkz:
13398 case VDIVPSZ256rmk:
13399 case VDIVPSZ256rmkz:
13400 case VDIVPSZ256rr:
13401 case VDIVPSZ256rrk:
13402 case VDIVPSZ256rrkz:
13403 case VDIVPSZrm:
13404 case VDIVPSZrmb:
13405 case VDIVPSZrmbk:
13406 case VDIVPSZrmbkz:
13407 case VDIVPSZrmk:
13408 case VDIVPSZrmkz:
13409 case VDIVPSZrr:
13410 case VDIVPSZrrb:
13411 case VDIVPSZrrbk:
13412 case VDIVPSZrrbkz:
13413 case VDIVPSZrrk:
13414 case VDIVPSZrrkz:
13415 case VDIVPSrm:
13416 case VDIVPSrr:
13417 return true;
13418 }
13419 return false;
13420}
13421
13422bool isVANDNPS(unsigned Opcode) {
13423 switch (Opcode) {
13424 case VANDNPSYrm:
13425 case VANDNPSYrr:
13426 case VANDNPSZ128rm:
13427 case VANDNPSZ128rmb:
13428 case VANDNPSZ128rmbk:
13429 case VANDNPSZ128rmbkz:
13430 case VANDNPSZ128rmk:
13431 case VANDNPSZ128rmkz:
13432 case VANDNPSZ128rr:
13433 case VANDNPSZ128rrk:
13434 case VANDNPSZ128rrkz:
13435 case VANDNPSZ256rm:
13436 case VANDNPSZ256rmb:
13437 case VANDNPSZ256rmbk:
13438 case VANDNPSZ256rmbkz:
13439 case VANDNPSZ256rmk:
13440 case VANDNPSZ256rmkz:
13441 case VANDNPSZ256rr:
13442 case VANDNPSZ256rrk:
13443 case VANDNPSZ256rrkz:
13444 case VANDNPSZrm:
13445 case VANDNPSZrmb:
13446 case VANDNPSZrmbk:
13447 case VANDNPSZrmbkz:
13448 case VANDNPSZrmk:
13449 case VANDNPSZrmkz:
13450 case VANDNPSZrr:
13451 case VANDNPSZrrk:
13452 case VANDNPSZrrkz:
13453 case VANDNPSrm:
13454 case VANDNPSrr:
13455 return true;
13456 }
13457 return false;
13458}
13459
13460bool isVPBROADCASTW(unsigned Opcode) {
13461 switch (Opcode) {
13462 case VPBROADCASTWYrm:
13463 case VPBROADCASTWYrr:
13464 case VPBROADCASTWZ128rm:
13465 case VPBROADCASTWZ128rmk:
13466 case VPBROADCASTWZ128rmkz:
13467 case VPBROADCASTWZ128rr:
13468 case VPBROADCASTWZ128rrk:
13469 case VPBROADCASTWZ128rrkz:
13470 case VPBROADCASTWZ256rm:
13471 case VPBROADCASTWZ256rmk:
13472 case VPBROADCASTWZ256rmkz:
13473 case VPBROADCASTWZ256rr:
13474 case VPBROADCASTWZ256rrk:
13475 case VPBROADCASTWZ256rrkz:
13476 case VPBROADCASTWZrm:
13477 case VPBROADCASTWZrmk:
13478 case VPBROADCASTWZrmkz:
13479 case VPBROADCASTWZrr:
13480 case VPBROADCASTWZrrk:
13481 case VPBROADCASTWZrrkz:
13482 case VPBROADCASTWrZ128rr:
13483 case VPBROADCASTWrZ128rrk:
13484 case VPBROADCASTWrZ128rrkz:
13485 case VPBROADCASTWrZ256rr:
13486 case VPBROADCASTWrZ256rrk:
13487 case VPBROADCASTWrZ256rrkz:
13488 case VPBROADCASTWrZrr:
13489 case VPBROADCASTWrZrrk:
13490 case VPBROADCASTWrZrrkz:
13491 case VPBROADCASTWrm:
13492 case VPBROADCASTWrr:
13493 return true;
13494 }
13495 return false;
13496}
13497
13498bool isFLDL2T(unsigned Opcode) {
13499 return Opcode == FLDL2T;
13500}
13501
13502bool isVPERMB(unsigned Opcode) {
13503 switch (Opcode) {
13504 case VPERMBZ128rm:
13505 case VPERMBZ128rmk:
13506 case VPERMBZ128rmkz:
13507 case VPERMBZ128rr:
13508 case VPERMBZ128rrk:
13509 case VPERMBZ128rrkz:
13510 case VPERMBZ256rm:
13511 case VPERMBZ256rmk:
13512 case VPERMBZ256rmkz:
13513 case VPERMBZ256rr:
13514 case VPERMBZ256rrk:
13515 case VPERMBZ256rrkz:
13516 case VPERMBZrm:
13517 case VPERMBZrmk:
13518 case VPERMBZrmkz:
13519 case VPERMBZrr:
13520 case VPERMBZrrk:
13521 case VPERMBZrrkz:
13522 return true;
13523 }
13524 return false;
13525}
13526
13527bool isFCMOVNBE(unsigned Opcode) {
13528 return Opcode == CMOVNBE_F;
13529}
13530
13531bool isVCVTTPH2W(unsigned Opcode) {
13532 switch (Opcode) {
13533 case VCVTTPH2WZ128rm:
13534 case VCVTTPH2WZ128rmb:
13535 case VCVTTPH2WZ128rmbk:
13536 case VCVTTPH2WZ128rmbkz:
13537 case VCVTTPH2WZ128rmk:
13538 case VCVTTPH2WZ128rmkz:
13539 case VCVTTPH2WZ128rr:
13540 case VCVTTPH2WZ128rrk:
13541 case VCVTTPH2WZ128rrkz:
13542 case VCVTTPH2WZ256rm:
13543 case VCVTTPH2WZ256rmb:
13544 case VCVTTPH2WZ256rmbk:
13545 case VCVTTPH2WZ256rmbkz:
13546 case VCVTTPH2WZ256rmk:
13547 case VCVTTPH2WZ256rmkz:
13548 case VCVTTPH2WZ256rr:
13549 case VCVTTPH2WZ256rrk:
13550 case VCVTTPH2WZ256rrkz:
13551 case VCVTTPH2WZrm:
13552 case VCVTTPH2WZrmb:
13553 case VCVTTPH2WZrmbk:
13554 case VCVTTPH2WZrmbkz:
13555 case VCVTTPH2WZrmk:
13556 case VCVTTPH2WZrmkz:
13557 case VCVTTPH2WZrr:
13558 case VCVTTPH2WZrrb:
13559 case VCVTTPH2WZrrbk:
13560 case VCVTTPH2WZrrbkz:
13561 case VCVTTPH2WZrrk:
13562 case VCVTTPH2WZrrkz:
13563 return true;
13564 }
13565 return false;
13566}
13567
13568bool isPMOVZXBQ(unsigned Opcode) {
13569 switch (Opcode) {
13570 case PMOVZXBQrm:
13571 case PMOVZXBQrr:
13572 return true;
13573 }
13574 return false;
13575}
13576
13577bool isPF2ID(unsigned Opcode) {
13578 switch (Opcode) {
13579 case PF2IDrm:
13580 case PF2IDrr:
13581 return true;
13582 }
13583 return false;
13584}
13585
13586bool isVFNMADD132PD(unsigned Opcode) {
13587 switch (Opcode) {
13588 case VFNMADD132PDYm:
13589 case VFNMADD132PDYr:
13590 case VFNMADD132PDZ128m:
13591 case VFNMADD132PDZ128mb:
13592 case VFNMADD132PDZ128mbk:
13593 case VFNMADD132PDZ128mbkz:
13594 case VFNMADD132PDZ128mk:
13595 case VFNMADD132PDZ128mkz:
13596 case VFNMADD132PDZ128r:
13597 case VFNMADD132PDZ128rk:
13598 case VFNMADD132PDZ128rkz:
13599 case VFNMADD132PDZ256m:
13600 case VFNMADD132PDZ256mb:
13601 case VFNMADD132PDZ256mbk:
13602 case VFNMADD132PDZ256mbkz:
13603 case VFNMADD132PDZ256mk:
13604 case VFNMADD132PDZ256mkz:
13605 case VFNMADD132PDZ256r:
13606 case VFNMADD132PDZ256rk:
13607 case VFNMADD132PDZ256rkz:
13608 case VFNMADD132PDZm:
13609 case VFNMADD132PDZmb:
13610 case VFNMADD132PDZmbk:
13611 case VFNMADD132PDZmbkz:
13612 case VFNMADD132PDZmk:
13613 case VFNMADD132PDZmkz:
13614 case VFNMADD132PDZr:
13615 case VFNMADD132PDZrb:
13616 case VFNMADD132PDZrbk:
13617 case VFNMADD132PDZrbkz:
13618 case VFNMADD132PDZrk:
13619 case VFNMADD132PDZrkz:
13620 case VFNMADD132PDm:
13621 case VFNMADD132PDr:
13622 return true;
13623 }
13624 return false;
13625}
13626
13627bool isPMULHRSW(unsigned Opcode) {
13628 switch (Opcode) {
13629 case MMX_PMULHRSWrm:
13630 case MMX_PMULHRSWrr:
13631 case PMULHRSWrm:
13632 case PMULHRSWrr:
13633 return true;
13634 }
13635 return false;
13636}
13637
13638bool isKADDD(unsigned Opcode) {
13639 return Opcode == KADDDkk;
13640}
13641
13642bool isVFNMSUB132SH(unsigned Opcode) {
13643 switch (Opcode) {
13644 case VFNMSUB132SHZm_Int:
13645 case VFNMSUB132SHZmk_Int:
13646 case VFNMSUB132SHZmkz_Int:
13647 case VFNMSUB132SHZr_Int:
13648 case VFNMSUB132SHZrb_Int:
13649 case VFNMSUB132SHZrbk_Int:
13650 case VFNMSUB132SHZrbkz_Int:
13651 case VFNMSUB132SHZrk_Int:
13652 case VFNMSUB132SHZrkz_Int:
13653 return true;
13654 }
13655 return false;
13656}
13657
13658bool isUIRET(unsigned Opcode) {
13659 return Opcode == UIRET;
13660}
13661
13662bool isBSR(unsigned Opcode) {
13663 switch (Opcode) {
13664 case BSR16rm:
13665 case BSR16rr:
13666 case BSR32rm:
13667 case BSR32rr:
13668 case BSR64rm:
13669 case BSR64rr:
13670 return true;
13671 }
13672 return false;
13673}
13674
13675bool isPCMPEQQ(unsigned Opcode) {
13676 switch (Opcode) {
13677 case PCMPEQQrm:
13678 case PCMPEQQrr:
13679 return true;
13680 }
13681 return false;
13682}
13683
13684bool isCDQ(unsigned Opcode) {
13685 return Opcode == CDQ;
13686}
13687
13688bool isPMAXSW(unsigned Opcode) {
13689 switch (Opcode) {
13690 case MMX_PMAXSWrm:
13691 case MMX_PMAXSWrr:
13692 case PMAXSWrm:
13693 case PMAXSWrr:
13694 return true;
13695 }
13696 return false;
13697}
13698
13699bool isSIDTD(unsigned Opcode) {
13700 return Opcode == SIDT32m;
13701}
13702
13703bool isVCVTPS2PHX(unsigned Opcode) {
13704 switch (Opcode) {
13705 case VCVTPS2PHXZ128rm:
13706 case VCVTPS2PHXZ128rmb:
13707 case VCVTPS2PHXZ128rmbk:
13708 case VCVTPS2PHXZ128rmbkz:
13709 case VCVTPS2PHXZ128rmk:
13710 case VCVTPS2PHXZ128rmkz:
13711 case VCVTPS2PHXZ128rr:
13712 case VCVTPS2PHXZ128rrk:
13713 case VCVTPS2PHXZ128rrkz:
13714 case VCVTPS2PHXZ256rm:
13715 case VCVTPS2PHXZ256rmb:
13716 case VCVTPS2PHXZ256rmbk:
13717 case VCVTPS2PHXZ256rmbkz:
13718 case VCVTPS2PHXZ256rmk:
13719 case VCVTPS2PHXZ256rmkz:
13720 case VCVTPS2PHXZ256rr:
13721 case VCVTPS2PHXZ256rrk:
13722 case VCVTPS2PHXZ256rrkz:
13723 case VCVTPS2PHXZrm:
13724 case VCVTPS2PHXZrmb:
13725 case VCVTPS2PHXZrmbk:
13726 case VCVTPS2PHXZrmbkz:
13727 case VCVTPS2PHXZrmk:
13728 case VCVTPS2PHXZrmkz:
13729 case VCVTPS2PHXZrr:
13730 case VCVTPS2PHXZrrb:
13731 case VCVTPS2PHXZrrbk:
13732 case VCVTPS2PHXZrrbkz:
13733 case VCVTPS2PHXZrrk:
13734 case VCVTPS2PHXZrrkz:
13735 return true;
13736 }
13737 return false;
13738}
13739
13740bool isVPSLLVQ(unsigned Opcode) {
13741 switch (Opcode) {
13742 case VPSLLVQYrm:
13743 case VPSLLVQYrr:
13744 case VPSLLVQZ128rm:
13745 case VPSLLVQZ128rmb:
13746 case VPSLLVQZ128rmbk:
13747 case VPSLLVQZ128rmbkz:
13748 case VPSLLVQZ128rmk:
13749 case VPSLLVQZ128rmkz:
13750 case VPSLLVQZ128rr:
13751 case VPSLLVQZ128rrk:
13752 case VPSLLVQZ128rrkz:
13753 case VPSLLVQZ256rm:
13754 case VPSLLVQZ256rmb:
13755 case VPSLLVQZ256rmbk:
13756 case VPSLLVQZ256rmbkz:
13757 case VPSLLVQZ256rmk:
13758 case VPSLLVQZ256rmkz:
13759 case VPSLLVQZ256rr:
13760 case VPSLLVQZ256rrk:
13761 case VPSLLVQZ256rrkz:
13762 case VPSLLVQZrm:
13763 case VPSLLVQZrmb:
13764 case VPSLLVQZrmbk:
13765 case VPSLLVQZrmbkz:
13766 case VPSLLVQZrmk:
13767 case VPSLLVQZrmkz:
13768 case VPSLLVQZrr:
13769 case VPSLLVQZrrk:
13770 case VPSLLVQZrrkz:
13771 case VPSLLVQrm:
13772 case VPSLLVQrr:
13773 return true;
13774 }
13775 return false;
13776}
13777
13778bool isMOVQ(unsigned Opcode) {
13779 switch (Opcode) {
13780 case MMX_MOVD64from64mr:
13781 case MMX_MOVD64from64rr:
13782 case MMX_MOVD64to64rm:
13783 case MMX_MOVD64to64rr:
13784 case MMX_MOVQ64mr:
13785 case MMX_MOVQ64rm:
13786 case MMX_MOVQ64rr:
13787 case MMX_MOVQ64rr_REV:
13788 case MOV64toPQIrm:
13789 case MOV64toPQIrr:
13790 case MOVPQI2QImr:
13791 case MOVPQI2QIrr:
13792 case MOVPQIto64mr:
13793 case MOVPQIto64rr:
13794 case MOVQI2PQIrm:
13795 case MOVZPQILo2PQIrr:
13796 return true;
13797 }
13798 return false;
13799}
13800
13801bool isVCMPBF16(unsigned Opcode) {
13802 switch (Opcode) {
13803 case VCMPBF16Z128rmbi:
13804 case VCMPBF16Z128rmbik:
13805 case VCMPBF16Z128rmi:
13806 case VCMPBF16Z128rmik:
13807 case VCMPBF16Z128rri:
13808 case VCMPBF16Z128rrik:
13809 case VCMPBF16Z256rmbi:
13810 case VCMPBF16Z256rmbik:
13811 case VCMPBF16Z256rmi:
13812 case VCMPBF16Z256rmik:
13813 case VCMPBF16Z256rri:
13814 case VCMPBF16Z256rrik:
13815 case VCMPBF16Zrmbi:
13816 case VCMPBF16Zrmbik:
13817 case VCMPBF16Zrmi:
13818 case VCMPBF16Zrmik:
13819 case VCMPBF16Zrri:
13820 case VCMPBF16Zrrik:
13821 return true;
13822 }
13823 return false;
13824}
13825
13826bool isPREFETCH(unsigned Opcode) {
13827 return Opcode == PREFETCH;
13828}
13829
13830bool isCLRSSBSY(unsigned Opcode) {
13831 return Opcode == CLRSSBSY;
13832}
13833
13834bool isTCVTROWPS2PHL(unsigned Opcode) {
13835 switch (Opcode) {
13836 case TCVTROWPS2PHLrte:
13837 case TCVTROWPS2PHLrti:
13838 return true;
13839 }
13840 return false;
13841}
13842
13843bool isPSHUFW(unsigned Opcode) {
13844 switch (Opcode) {
13845 case MMX_PSHUFWmi:
13846 case MMX_PSHUFWri:
13847 return true;
13848 }
13849 return false;
13850}
13851
13852bool isVPDPWSUDS(unsigned Opcode) {
13853 switch (Opcode) {
13854 case VPDPWSUDSYrm:
13855 case VPDPWSUDSYrr:
13856 case VPDPWSUDSZ128rm:
13857 case VPDPWSUDSZ128rmb:
13858 case VPDPWSUDSZ128rmbk:
13859 case VPDPWSUDSZ128rmbkz:
13860 case VPDPWSUDSZ128rmk:
13861 case VPDPWSUDSZ128rmkz:
13862 case VPDPWSUDSZ128rr:
13863 case VPDPWSUDSZ128rrk:
13864 case VPDPWSUDSZ128rrkz:
13865 case VPDPWSUDSZ256rm:
13866 case VPDPWSUDSZ256rmb:
13867 case VPDPWSUDSZ256rmbk:
13868 case VPDPWSUDSZ256rmbkz:
13869 case VPDPWSUDSZ256rmk:
13870 case VPDPWSUDSZ256rmkz:
13871 case VPDPWSUDSZ256rr:
13872 case VPDPWSUDSZ256rrk:
13873 case VPDPWSUDSZ256rrkz:
13874 case VPDPWSUDSZrm:
13875 case VPDPWSUDSZrmb:
13876 case VPDPWSUDSZrmbk:
13877 case VPDPWSUDSZrmbkz:
13878 case VPDPWSUDSZrmk:
13879 case VPDPWSUDSZrmkz:
13880 case VPDPWSUDSZrr:
13881 case VPDPWSUDSZrrk:
13882 case VPDPWSUDSZrrkz:
13883 case VPDPWSUDSrm:
13884 case VPDPWSUDSrr:
13885 return true;
13886 }
13887 return false;
13888}
13889
13890bool isVPMOVSXBQ(unsigned Opcode) {
13891 switch (Opcode) {
13892 case VPMOVSXBQYrm:
13893 case VPMOVSXBQYrr:
13894 case VPMOVSXBQZ128rm:
13895 case VPMOVSXBQZ128rmk:
13896 case VPMOVSXBQZ128rmkz:
13897 case VPMOVSXBQZ128rr:
13898 case VPMOVSXBQZ128rrk:
13899 case VPMOVSXBQZ128rrkz:
13900 case VPMOVSXBQZ256rm:
13901 case VPMOVSXBQZ256rmk:
13902 case VPMOVSXBQZ256rmkz:
13903 case VPMOVSXBQZ256rr:
13904 case VPMOVSXBQZ256rrk:
13905 case VPMOVSXBQZ256rrkz:
13906 case VPMOVSXBQZrm:
13907 case VPMOVSXBQZrmk:
13908 case VPMOVSXBQZrmkz:
13909 case VPMOVSXBQZrr:
13910 case VPMOVSXBQZrrk:
13911 case VPMOVSXBQZrrkz:
13912 case VPMOVSXBQrm:
13913 case VPMOVSXBQrr:
13914 return true;
13915 }
13916 return false;
13917}
13918
13919bool isFICOMP(unsigned Opcode) {
13920 switch (Opcode) {
13921 case FICOMP16m:
13922 case FICOMP32m:
13923 return true;
13924 }
13925 return false;
13926}
13927
13928bool isVLDMXCSR(unsigned Opcode) {
13929 return Opcode == VLDMXCSR;
13930}
13931
13932bool isVPSUBUSW(unsigned Opcode) {
13933 switch (Opcode) {
13934 case VPSUBUSWYrm:
13935 case VPSUBUSWYrr:
13936 case VPSUBUSWZ128rm:
13937 case VPSUBUSWZ128rmk:
13938 case VPSUBUSWZ128rmkz:
13939 case VPSUBUSWZ128rr:
13940 case VPSUBUSWZ128rrk:
13941 case VPSUBUSWZ128rrkz:
13942 case VPSUBUSWZ256rm:
13943 case VPSUBUSWZ256rmk:
13944 case VPSUBUSWZ256rmkz:
13945 case VPSUBUSWZ256rr:
13946 case VPSUBUSWZ256rrk:
13947 case VPSUBUSWZ256rrkz:
13948 case VPSUBUSWZrm:
13949 case VPSUBUSWZrmk:
13950 case VPSUBUSWZrmkz:
13951 case VPSUBUSWZrr:
13952 case VPSUBUSWZrrk:
13953 case VPSUBUSWZrrkz:
13954 case VPSUBUSWrm:
13955 case VPSUBUSWrr:
13956 return true;
13957 }
13958 return false;
13959}
13960
13961bool isVFNMSUB132SS(unsigned Opcode) {
13962 switch (Opcode) {
13963 case VFNMSUB132SSZm_Int:
13964 case VFNMSUB132SSZmk_Int:
13965 case VFNMSUB132SSZmkz_Int:
13966 case VFNMSUB132SSZr_Int:
13967 case VFNMSUB132SSZrb_Int:
13968 case VFNMSUB132SSZrbk_Int:
13969 case VFNMSUB132SSZrbkz_Int:
13970 case VFNMSUB132SSZrk_Int:
13971 case VFNMSUB132SSZrkz_Int:
13972 case VFNMSUB132SSm_Int:
13973 case VFNMSUB132SSr_Int:
13974 return true;
13975 }
13976 return false;
13977}
13978
13979bool isRETF(unsigned Opcode) {
13980 switch (Opcode) {
13981 case LRET16:
13982 case LRET32:
13983 case LRETI16:
13984 case LRETI32:
13985 return true;
13986 }
13987 return false;
13988}
13989
13990bool isKMOVQ(unsigned Opcode) {
13991 switch (Opcode) {
13992 case KMOVQkk:
13993 case KMOVQkk_EVEX:
13994 case KMOVQkm:
13995 case KMOVQkm_EVEX:
13996 case KMOVQkr:
13997 case KMOVQkr_EVEX:
13998 case KMOVQmk:
13999 case KMOVQmk_EVEX:
14000 case KMOVQrk:
14001 case KMOVQrk_EVEX:
14002 return true;
14003 }
14004 return false;
14005}
14006
14007bool isVPADDUSW(unsigned Opcode) {
14008 switch (Opcode) {
14009 case VPADDUSWYrm:
14010 case VPADDUSWYrr:
14011 case VPADDUSWZ128rm:
14012 case VPADDUSWZ128rmk:
14013 case VPADDUSWZ128rmkz:
14014 case VPADDUSWZ128rr:
14015 case VPADDUSWZ128rrk:
14016 case VPADDUSWZ128rrkz:
14017 case VPADDUSWZ256rm:
14018 case VPADDUSWZ256rmk:
14019 case VPADDUSWZ256rmkz:
14020 case VPADDUSWZ256rr:
14021 case VPADDUSWZ256rrk:
14022 case VPADDUSWZ256rrkz:
14023 case VPADDUSWZrm:
14024 case VPADDUSWZrmk:
14025 case VPADDUSWZrmkz:
14026 case VPADDUSWZrr:
14027 case VPADDUSWZrrk:
14028 case VPADDUSWZrrkz:
14029 case VPADDUSWrm:
14030 case VPADDUSWrr:
14031 return true;
14032 }
14033 return false;
14034}
14035
14036bool isPACKSSDW(unsigned Opcode) {
14037 switch (Opcode) {
14038 case MMX_PACKSSDWrm:
14039 case MMX_PACKSSDWrr:
14040 case PACKSSDWrm:
14041 case PACKSSDWrr:
14042 return true;
14043 }
14044 return false;
14045}
14046
14047bool isUMONITOR(unsigned Opcode) {
14048 switch (Opcode) {
14049 case UMONITOR16:
14050 case UMONITOR32:
14051 case UMONITOR64:
14052 return true;
14053 }
14054 return false;
14055}
14056
14057bool isENQCMDS(unsigned Opcode) {
14058 switch (Opcode) {
14059 case ENQCMDS16:
14060 case ENQCMDS32:
14061 case ENQCMDS32_EVEX:
14062 case ENQCMDS64:
14063 case ENQCMDS64_EVEX:
14064 return true;
14065 }
14066 return false;
14067}
14068
14069bool isVCOMXSD(unsigned Opcode) {
14070 switch (Opcode) {
14071 case VCOMXSDZrm_Int:
14072 case VCOMXSDZrr_Int:
14073 case VCOMXSDZrrb_Int:
14074 return true;
14075 }
14076 return false;
14077}
14078
14079bool isVPMAXSQ(unsigned Opcode) {
14080 switch (Opcode) {
14081 case VPMAXSQZ128rm:
14082 case VPMAXSQZ128rmb:
14083 case VPMAXSQZ128rmbk:
14084 case VPMAXSQZ128rmbkz:
14085 case VPMAXSQZ128rmk:
14086 case VPMAXSQZ128rmkz:
14087 case VPMAXSQZ128rr:
14088 case VPMAXSQZ128rrk:
14089 case VPMAXSQZ128rrkz:
14090 case VPMAXSQZ256rm:
14091 case VPMAXSQZ256rmb:
14092 case VPMAXSQZ256rmbk:
14093 case VPMAXSQZ256rmbkz:
14094 case VPMAXSQZ256rmk:
14095 case VPMAXSQZ256rmkz:
14096 case VPMAXSQZ256rr:
14097 case VPMAXSQZ256rrk:
14098 case VPMAXSQZ256rrkz:
14099 case VPMAXSQZrm:
14100 case VPMAXSQZrmb:
14101 case VPMAXSQZrmbk:
14102 case VPMAXSQZrmbkz:
14103 case VPMAXSQZrmk:
14104 case VPMAXSQZrmkz:
14105 case VPMAXSQZrr:
14106 case VPMAXSQZrrk:
14107 case VPMAXSQZrrkz:
14108 return true;
14109 }
14110 return false;
14111}
14112
14113bool isVFMSUB213BF16(unsigned Opcode) {
14114 switch (Opcode) {
14115 case VFMSUB213BF16Z128m:
14116 case VFMSUB213BF16Z128mb:
14117 case VFMSUB213BF16Z128mbk:
14118 case VFMSUB213BF16Z128mbkz:
14119 case VFMSUB213BF16Z128mk:
14120 case VFMSUB213BF16Z128mkz:
14121 case VFMSUB213BF16Z128r:
14122 case VFMSUB213BF16Z128rk:
14123 case VFMSUB213BF16Z128rkz:
14124 case VFMSUB213BF16Z256m:
14125 case VFMSUB213BF16Z256mb:
14126 case VFMSUB213BF16Z256mbk:
14127 case VFMSUB213BF16Z256mbkz:
14128 case VFMSUB213BF16Z256mk:
14129 case VFMSUB213BF16Z256mkz:
14130 case VFMSUB213BF16Z256r:
14131 case VFMSUB213BF16Z256rk:
14132 case VFMSUB213BF16Z256rkz:
14133 case VFMSUB213BF16Zm:
14134 case VFMSUB213BF16Zmb:
14135 case VFMSUB213BF16Zmbk:
14136 case VFMSUB213BF16Zmbkz:
14137 case VFMSUB213BF16Zmk:
14138 case VFMSUB213BF16Zmkz:
14139 case VFMSUB213BF16Zr:
14140 case VFMSUB213BF16Zrk:
14141 case VFMSUB213BF16Zrkz:
14142 return true;
14143 }
14144 return false;
14145}
14146
14147bool isVPERMT2Q(unsigned Opcode) {
14148 switch (Opcode) {
14149 case VPERMT2QZ128rm:
14150 case VPERMT2QZ128rmb:
14151 case VPERMT2QZ128rmbk:
14152 case VPERMT2QZ128rmbkz:
14153 case VPERMT2QZ128rmk:
14154 case VPERMT2QZ128rmkz:
14155 case VPERMT2QZ128rr:
14156 case VPERMT2QZ128rrk:
14157 case VPERMT2QZ128rrkz:
14158 case VPERMT2QZ256rm:
14159 case VPERMT2QZ256rmb:
14160 case VPERMT2QZ256rmbk:
14161 case VPERMT2QZ256rmbkz:
14162 case VPERMT2QZ256rmk:
14163 case VPERMT2QZ256rmkz:
14164 case VPERMT2QZ256rr:
14165 case VPERMT2QZ256rrk:
14166 case VPERMT2QZ256rrkz:
14167 case VPERMT2QZrm:
14168 case VPERMT2QZrmb:
14169 case VPERMT2QZrmbk:
14170 case VPERMT2QZrmbkz:
14171 case VPERMT2QZrmk:
14172 case VPERMT2QZrmkz:
14173 case VPERMT2QZrr:
14174 case VPERMT2QZrrk:
14175 case VPERMT2QZrrkz:
14176 return true;
14177 }
14178 return false;
14179}
14180
14181bool isFDECSTP(unsigned Opcode) {
14182 return Opcode == FDECSTP;
14183}
14184
14185bool isVPTESTMQ(unsigned Opcode) {
14186 switch (Opcode) {
14187 case VPTESTMQZ128rm:
14188 case VPTESTMQZ128rmb:
14189 case VPTESTMQZ128rmbk:
14190 case VPTESTMQZ128rmk:
14191 case VPTESTMQZ128rr:
14192 case VPTESTMQZ128rrk:
14193 case VPTESTMQZ256rm:
14194 case VPTESTMQZ256rmb:
14195 case VPTESTMQZ256rmbk:
14196 case VPTESTMQZ256rmk:
14197 case VPTESTMQZ256rr:
14198 case VPTESTMQZ256rrk:
14199 case VPTESTMQZrm:
14200 case VPTESTMQZrmb:
14201 case VPTESTMQZrmbk:
14202 case VPTESTMQZrmk:
14203 case VPTESTMQZrr:
14204 case VPTESTMQZrrk:
14205 return true;
14206 }
14207 return false;
14208}
14209
14210bool isVRCP14PD(unsigned Opcode) {
14211 switch (Opcode) {
14212 case VRCP14PDZ128m:
14213 case VRCP14PDZ128mb:
14214 case VRCP14PDZ128mbk:
14215 case VRCP14PDZ128mbkz:
14216 case VRCP14PDZ128mk:
14217 case VRCP14PDZ128mkz:
14218 case VRCP14PDZ128r:
14219 case VRCP14PDZ128rk:
14220 case VRCP14PDZ128rkz:
14221 case VRCP14PDZ256m:
14222 case VRCP14PDZ256mb:
14223 case VRCP14PDZ256mbk:
14224 case VRCP14PDZ256mbkz:
14225 case VRCP14PDZ256mk:
14226 case VRCP14PDZ256mkz:
14227 case VRCP14PDZ256r:
14228 case VRCP14PDZ256rk:
14229 case VRCP14PDZ256rkz:
14230 case VRCP14PDZm:
14231 case VRCP14PDZmb:
14232 case VRCP14PDZmbk:
14233 case VRCP14PDZmbkz:
14234 case VRCP14PDZmk:
14235 case VRCP14PDZmkz:
14236 case VRCP14PDZr:
14237 case VRCP14PDZrk:
14238 case VRCP14PDZrkz:
14239 return true;
14240 }
14241 return false;
14242}
14243
14244bool isARPL(unsigned Opcode) {
14245 switch (Opcode) {
14246 case ARPL16mr:
14247 case ARPL16rr:
14248 return true;
14249 }
14250 return false;
14251}
14252
14253bool isVFMSUB213SD(unsigned Opcode) {
14254 switch (Opcode) {
14255 case VFMSUB213SDZm_Int:
14256 case VFMSUB213SDZmk_Int:
14257 case VFMSUB213SDZmkz_Int:
14258 case VFMSUB213SDZr_Int:
14259 case VFMSUB213SDZrb_Int:
14260 case VFMSUB213SDZrbk_Int:
14261 case VFMSUB213SDZrbkz_Int:
14262 case VFMSUB213SDZrk_Int:
14263 case VFMSUB213SDZrkz_Int:
14264 case VFMSUB213SDm_Int:
14265 case VFMSUB213SDr_Int:
14266 return true;
14267 }
14268 return false;
14269}
14270
14271bool isJMPABS(unsigned Opcode) {
14272 return Opcode == JMPABS64i;
14273}
14274
14275bool isVUNPCKHPS(unsigned Opcode) {
14276 switch (Opcode) {
14277 case VUNPCKHPSYrm:
14278 case VUNPCKHPSYrr:
14279 case VUNPCKHPSZ128rm:
14280 case VUNPCKHPSZ128rmb:
14281 case VUNPCKHPSZ128rmbk:
14282 case VUNPCKHPSZ128rmbkz:
14283 case VUNPCKHPSZ128rmk:
14284 case VUNPCKHPSZ128rmkz:
14285 case VUNPCKHPSZ128rr:
14286 case VUNPCKHPSZ128rrk:
14287 case VUNPCKHPSZ128rrkz:
14288 case VUNPCKHPSZ256rm:
14289 case VUNPCKHPSZ256rmb:
14290 case VUNPCKHPSZ256rmbk:
14291 case VUNPCKHPSZ256rmbkz:
14292 case VUNPCKHPSZ256rmk:
14293 case VUNPCKHPSZ256rmkz:
14294 case VUNPCKHPSZ256rr:
14295 case VUNPCKHPSZ256rrk:
14296 case VUNPCKHPSZ256rrkz:
14297 case VUNPCKHPSZrm:
14298 case VUNPCKHPSZrmb:
14299 case VUNPCKHPSZrmbk:
14300 case VUNPCKHPSZrmbkz:
14301 case VUNPCKHPSZrmk:
14302 case VUNPCKHPSZrmkz:
14303 case VUNPCKHPSZrr:
14304 case VUNPCKHPSZrrk:
14305 case VUNPCKHPSZrrkz:
14306 case VUNPCKHPSrm:
14307 case VUNPCKHPSrr:
14308 return true;
14309 }
14310 return false;
14311}
14312
14313bool isVFNMADDSS(unsigned Opcode) {
14314 switch (Opcode) {
14315 case VFNMADDSS4mr:
14316 case VFNMADDSS4rm:
14317 case VFNMADDSS4rr:
14318 case VFNMADDSS4rr_REV:
14319 return true;
14320 }
14321 return false;
14322}
14323
14324bool isSIDT(unsigned Opcode) {
14325 return Opcode == SIDT64m;
14326}
14327
14328bool isVPCMPGTB(unsigned Opcode) {
14329 switch (Opcode) {
14330 case VPCMPGTBYrm:
14331 case VPCMPGTBYrr:
14332 case VPCMPGTBZ128rm:
14333 case VPCMPGTBZ128rmk:
14334 case VPCMPGTBZ128rr:
14335 case VPCMPGTBZ128rrk:
14336 case VPCMPGTBZ256rm:
14337 case VPCMPGTBZ256rmk:
14338 case VPCMPGTBZ256rr:
14339 case VPCMPGTBZ256rrk:
14340 case VPCMPGTBZrm:
14341 case VPCMPGTBZrmk:
14342 case VPCMPGTBZrr:
14343 case VPCMPGTBZrrk:
14344 case VPCMPGTBrm:
14345 case VPCMPGTBrr:
14346 return true;
14347 }
14348 return false;
14349}
14350
14351bool isVPRORD(unsigned Opcode) {
14352 switch (Opcode) {
14353 case VPRORDZ128mbi:
14354 case VPRORDZ128mbik:
14355 case VPRORDZ128mbikz:
14356 case VPRORDZ128mi:
14357 case VPRORDZ128mik:
14358 case VPRORDZ128mikz:
14359 case VPRORDZ128ri:
14360 case VPRORDZ128rik:
14361 case VPRORDZ128rikz:
14362 case VPRORDZ256mbi:
14363 case VPRORDZ256mbik:
14364 case VPRORDZ256mbikz:
14365 case VPRORDZ256mi:
14366 case VPRORDZ256mik:
14367 case VPRORDZ256mikz:
14368 case VPRORDZ256ri:
14369 case VPRORDZ256rik:
14370 case VPRORDZ256rikz:
14371 case VPRORDZmbi:
14372 case VPRORDZmbik:
14373 case VPRORDZmbikz:
14374 case VPRORDZmi:
14375 case VPRORDZmik:
14376 case VPRORDZmikz:
14377 case VPRORDZri:
14378 case VPRORDZrik:
14379 case VPRORDZrikz:
14380 return true;
14381 }
14382 return false;
14383}
14384
14385bool isVSUBSS(unsigned Opcode) {
14386 switch (Opcode) {
14387 case VSUBSSZrm_Int:
14388 case VSUBSSZrmk_Int:
14389 case VSUBSSZrmkz_Int:
14390 case VSUBSSZrr_Int:
14391 case VSUBSSZrrb_Int:
14392 case VSUBSSZrrbk_Int:
14393 case VSUBSSZrrbkz_Int:
14394 case VSUBSSZrrk_Int:
14395 case VSUBSSZrrkz_Int:
14396 case VSUBSSrm_Int:
14397 case VSUBSSrr_Int:
14398 return true;
14399 }
14400 return false;
14401}
14402
14403bool isPUSHFQ(unsigned Opcode) {
14404 return Opcode == PUSHF64;
14405}
14406
14407bool isVCVTHF82PH(unsigned Opcode) {
14408 switch (Opcode) {
14409 case VCVTHF82PHZ128rm:
14410 case VCVTHF82PHZ128rmk:
14411 case VCVTHF82PHZ128rmkz:
14412 case VCVTHF82PHZ128rr:
14413 case VCVTHF82PHZ128rrk:
14414 case VCVTHF82PHZ128rrkz:
14415 case VCVTHF82PHZ256rm:
14416 case VCVTHF82PHZ256rmk:
14417 case VCVTHF82PHZ256rmkz:
14418 case VCVTHF82PHZ256rr:
14419 case VCVTHF82PHZ256rrk:
14420 case VCVTHF82PHZ256rrkz:
14421 case VCVTHF82PHZrm:
14422 case VCVTHF82PHZrmk:
14423 case VCVTHF82PHZrmkz:
14424 case VCVTHF82PHZrr:
14425 case VCVTHF82PHZrrk:
14426 case VCVTHF82PHZrrkz:
14427 return true;
14428 }
14429 return false;
14430}
14431
14432bool isVPCLMULQDQ(unsigned Opcode) {
14433 switch (Opcode) {
14434 case VPCLMULQDQYrmi:
14435 case VPCLMULQDQYrri:
14436 case VPCLMULQDQZ128rmi:
14437 case VPCLMULQDQZ128rri:
14438 case VPCLMULQDQZ256rmi:
14439 case VPCLMULQDQZ256rri:
14440 case VPCLMULQDQZrmi:
14441 case VPCLMULQDQZrri:
14442 case VPCLMULQDQrmi:
14443 case VPCLMULQDQrri:
14444 return true;
14445 }
14446 return false;
14447}
14448
14449bool isVPADDUSB(unsigned Opcode) {
14450 switch (Opcode) {
14451 case VPADDUSBYrm:
14452 case VPADDUSBYrr:
14453 case VPADDUSBZ128rm:
14454 case VPADDUSBZ128rmk:
14455 case VPADDUSBZ128rmkz:
14456 case VPADDUSBZ128rr:
14457 case VPADDUSBZ128rrk:
14458 case VPADDUSBZ128rrkz:
14459 case VPADDUSBZ256rm:
14460 case VPADDUSBZ256rmk:
14461 case VPADDUSBZ256rmkz:
14462 case VPADDUSBZ256rr:
14463 case VPADDUSBZ256rrk:
14464 case VPADDUSBZ256rrkz:
14465 case VPADDUSBZrm:
14466 case VPADDUSBZrmk:
14467 case VPADDUSBZrmkz:
14468 case VPADDUSBZrr:
14469 case VPADDUSBZrrk:
14470 case VPADDUSBZrrkz:
14471 case VPADDUSBrm:
14472 case VPADDUSBrr:
14473 return true;
14474 }
14475 return false;
14476}
14477
14478bool isVPCMPD(unsigned Opcode) {
14479 switch (Opcode) {
14480 case VPCMPDZ128rmbi:
14481 case VPCMPDZ128rmbik:
14482 case VPCMPDZ128rmi:
14483 case VPCMPDZ128rmik:
14484 case VPCMPDZ128rri:
14485 case VPCMPDZ128rrik:
14486 case VPCMPDZ256rmbi:
14487 case VPCMPDZ256rmbik:
14488 case VPCMPDZ256rmi:
14489 case VPCMPDZ256rmik:
14490 case VPCMPDZ256rri:
14491 case VPCMPDZ256rrik:
14492 case VPCMPDZrmbi:
14493 case VPCMPDZrmbik:
14494 case VPCMPDZrmi:
14495 case VPCMPDZrmik:
14496 case VPCMPDZrri:
14497 case VPCMPDZrrik:
14498 return true;
14499 }
14500 return false;
14501}
14502
14503bool isMOVSD(unsigned Opcode) {
14504 switch (Opcode) {
14505 case MOVSDmr:
14506 case MOVSDrm:
14507 case MOVSDrr:
14508 case MOVSDrr_REV:
14509 case MOVSL:
14510 return true;
14511 }
14512 return false;
14513}
14514
14515bool isPSUBUSW(unsigned Opcode) {
14516 switch (Opcode) {
14517 case MMX_PSUBUSWrm:
14518 case MMX_PSUBUSWrr:
14519 case PSUBUSWrm:
14520 case PSUBUSWrr:
14521 return true;
14522 }
14523 return false;
14524}
14525
14526bool isVFMSUBADD132PS(unsigned Opcode) {
14527 switch (Opcode) {
14528 case VFMSUBADD132PSYm:
14529 case VFMSUBADD132PSYr:
14530 case VFMSUBADD132PSZ128m:
14531 case VFMSUBADD132PSZ128mb:
14532 case VFMSUBADD132PSZ128mbk:
14533 case VFMSUBADD132PSZ128mbkz:
14534 case VFMSUBADD132PSZ128mk:
14535 case VFMSUBADD132PSZ128mkz:
14536 case VFMSUBADD132PSZ128r:
14537 case VFMSUBADD132PSZ128rk:
14538 case VFMSUBADD132PSZ128rkz:
14539 case VFMSUBADD132PSZ256m:
14540 case VFMSUBADD132PSZ256mb:
14541 case VFMSUBADD132PSZ256mbk:
14542 case VFMSUBADD132PSZ256mbkz:
14543 case VFMSUBADD132PSZ256mk:
14544 case VFMSUBADD132PSZ256mkz:
14545 case VFMSUBADD132PSZ256r:
14546 case VFMSUBADD132PSZ256rk:
14547 case VFMSUBADD132PSZ256rkz:
14548 case VFMSUBADD132PSZm:
14549 case VFMSUBADD132PSZmb:
14550 case VFMSUBADD132PSZmbk:
14551 case VFMSUBADD132PSZmbkz:
14552 case VFMSUBADD132PSZmk:
14553 case VFMSUBADD132PSZmkz:
14554 case VFMSUBADD132PSZr:
14555 case VFMSUBADD132PSZrb:
14556 case VFMSUBADD132PSZrbk:
14557 case VFMSUBADD132PSZrbkz:
14558 case VFMSUBADD132PSZrk:
14559 case VFMSUBADD132PSZrkz:
14560 case VFMSUBADD132PSm:
14561 case VFMSUBADD132PSr:
14562 return true;
14563 }
14564 return false;
14565}
14566
14567bool isMOVMSKPS(unsigned Opcode) {
14568 return Opcode == MOVMSKPSrr;
14569}
14570
14571bool isVFIXUPIMMSS(unsigned Opcode) {
14572 switch (Opcode) {
14573 case VFIXUPIMMSSZrmi:
14574 case VFIXUPIMMSSZrmik:
14575 case VFIXUPIMMSSZrmikz:
14576 case VFIXUPIMMSSZrri:
14577 case VFIXUPIMMSSZrrib:
14578 case VFIXUPIMMSSZrribk:
14579 case VFIXUPIMMSSZrribkz:
14580 case VFIXUPIMMSSZrrik:
14581 case VFIXUPIMMSSZrrikz:
14582 return true;
14583 }
14584 return false;
14585}
14586
14587bool isMFENCE(unsigned Opcode) {
14588 return Opcode == MFENCE;
14589}
14590
14591bool isFTST(unsigned Opcode) {
14592 return Opcode == TST_F;
14593}
14594
14595bool isVPMADDWD(unsigned Opcode) {
14596 switch (Opcode) {
14597 case VPMADDWDYrm:
14598 case VPMADDWDYrr:
14599 case VPMADDWDZ128rm:
14600 case VPMADDWDZ128rmk:
14601 case VPMADDWDZ128rmkz:
14602 case VPMADDWDZ128rr:
14603 case VPMADDWDZ128rrk:
14604 case VPMADDWDZ128rrkz:
14605 case VPMADDWDZ256rm:
14606 case VPMADDWDZ256rmk:
14607 case VPMADDWDZ256rmkz:
14608 case VPMADDWDZ256rr:
14609 case VPMADDWDZ256rrk:
14610 case VPMADDWDZ256rrkz:
14611 case VPMADDWDZrm:
14612 case VPMADDWDZrmk:
14613 case VPMADDWDZrmkz:
14614 case VPMADDWDZrr:
14615 case VPMADDWDZrrk:
14616 case VPMADDWDZrrkz:
14617 case VPMADDWDrm:
14618 case VPMADDWDrr:
14619 return true;
14620 }
14621 return false;
14622}
14623
14624bool isPOP(unsigned Opcode) {
14625 switch (Opcode) {
14626 case POP16r:
14627 case POP16rmm:
14628 case POP16rmr:
14629 case POP32r:
14630 case POP32rmm:
14631 case POP32rmr:
14632 case POP64r:
14633 case POP64rmm:
14634 case POP64rmr:
14635 case POPDS16:
14636 case POPDS32:
14637 case POPES16:
14638 case POPES32:
14639 case POPFS16:
14640 case POPFS32:
14641 case POPFS64:
14642 case POPGS16:
14643 case POPGS32:
14644 case POPGS64:
14645 case POPSS16:
14646 case POPSS32:
14647 return true;
14648 }
14649 return false;
14650}
14651
14652bool isPSUBW(unsigned Opcode) {
14653 switch (Opcode) {
14654 case MMX_PSUBWrm:
14655 case MMX_PSUBWrr:
14656 case PSUBWrm:
14657 case PSUBWrr:
14658 return true;
14659 }
14660 return false;
14661}
14662
14663bool isBSWAP(unsigned Opcode) {
14664 switch (Opcode) {
14665 case BSWAP16r_BAD:
14666 case BSWAP32r:
14667 case BSWAP64r:
14668 return true;
14669 }
14670 return false;
14671}
14672
14673bool isPFMIN(unsigned Opcode) {
14674 switch (Opcode) {
14675 case PFMINrm:
14676 case PFMINrr:
14677 return true;
14678 }
14679 return false;
14680}
14681
14682bool isVFPCLASSPD(unsigned Opcode) {
14683 switch (Opcode) {
14684 case VFPCLASSPDZ128mbi:
14685 case VFPCLASSPDZ128mbik:
14686 case VFPCLASSPDZ128mi:
14687 case VFPCLASSPDZ128mik:
14688 case VFPCLASSPDZ128ri:
14689 case VFPCLASSPDZ128rik:
14690 case VFPCLASSPDZ256mbi:
14691 case VFPCLASSPDZ256mbik:
14692 case VFPCLASSPDZ256mi:
14693 case VFPCLASSPDZ256mik:
14694 case VFPCLASSPDZ256ri:
14695 case VFPCLASSPDZ256rik:
14696 case VFPCLASSPDZmbi:
14697 case VFPCLASSPDZmbik:
14698 case VFPCLASSPDZmi:
14699 case VFPCLASSPDZmik:
14700 case VFPCLASSPDZri:
14701 case VFPCLASSPDZrik:
14702 return true;
14703 }
14704 return false;
14705}
14706
14707bool isVPSHRDVD(unsigned Opcode) {
14708 switch (Opcode) {
14709 case VPSHRDVDZ128m:
14710 case VPSHRDVDZ128mb:
14711 case VPSHRDVDZ128mbk:
14712 case VPSHRDVDZ128mbkz:
14713 case VPSHRDVDZ128mk:
14714 case VPSHRDVDZ128mkz:
14715 case VPSHRDVDZ128r:
14716 case VPSHRDVDZ128rk:
14717 case VPSHRDVDZ128rkz:
14718 case VPSHRDVDZ256m:
14719 case VPSHRDVDZ256mb:
14720 case VPSHRDVDZ256mbk:
14721 case VPSHRDVDZ256mbkz:
14722 case VPSHRDVDZ256mk:
14723 case VPSHRDVDZ256mkz:
14724 case VPSHRDVDZ256r:
14725 case VPSHRDVDZ256rk:
14726 case VPSHRDVDZ256rkz:
14727 case VPSHRDVDZm:
14728 case VPSHRDVDZmb:
14729 case VPSHRDVDZmbk:
14730 case VPSHRDVDZmbkz:
14731 case VPSHRDVDZmk:
14732 case VPSHRDVDZmkz:
14733 case VPSHRDVDZr:
14734 case VPSHRDVDZrk:
14735 case VPSHRDVDZrkz:
14736 return true;
14737 }
14738 return false;
14739}
14740
14741bool isPADDW(unsigned Opcode) {
14742 switch (Opcode) {
14743 case MMX_PADDWrm:
14744 case MMX_PADDWrr:
14745 case PADDWrm:
14746 case PADDWrr:
14747 return true;
14748 }
14749 return false;
14750}
14751
14752bool isCVTSI2SD(unsigned Opcode) {
14753 switch (Opcode) {
14754 case CVTSI2SDrm_Int:
14755 case CVTSI2SDrr_Int:
14756 case CVTSI642SDrm_Int:
14757 case CVTSI642SDrr_Int:
14758 return true;
14759 }
14760 return false;
14761}
14762
14763bool isENQCMD(unsigned Opcode) {
14764 switch (Opcode) {
14765 case ENQCMD16:
14766 case ENQCMD32:
14767 case ENQCMD32_EVEX:
14768 case ENQCMD64:
14769 case ENQCMD64_EVEX:
14770 return true;
14771 }
14772 return false;
14773}
14774
14775bool isXSHA1(unsigned Opcode) {
14776 return Opcode == XSHA1;
14777}
14778
14779bool isVFNMADD132SD(unsigned Opcode) {
14780 switch (Opcode) {
14781 case VFNMADD132SDZm_Int:
14782 case VFNMADD132SDZmk_Int:
14783 case VFNMADD132SDZmkz_Int:
14784 case VFNMADD132SDZr_Int:
14785 case VFNMADD132SDZrb_Int:
14786 case VFNMADD132SDZrbk_Int:
14787 case VFNMADD132SDZrbkz_Int:
14788 case VFNMADD132SDZrk_Int:
14789 case VFNMADD132SDZrkz_Int:
14790 case VFNMADD132SDm_Int:
14791 case VFNMADD132SDr_Int:
14792 return true;
14793 }
14794 return false;
14795}
14796
14797bool isMOVZX(unsigned Opcode) {
14798 switch (Opcode) {
14799 case MOVZX16rm16:
14800 case MOVZX16rm8:
14801 case MOVZX16rr16:
14802 case MOVZX16rr8:
14803 case MOVZX32rm16:
14804 case MOVZX32rm8:
14805 case MOVZX32rr16:
14806 case MOVZX32rr8:
14807 case MOVZX64rm16:
14808 case MOVZX64rm8:
14809 case MOVZX64rr16:
14810 case MOVZX64rr8:
14811 return true;
14812 }
14813 return false;
14814}
14815
14816bool isVFIXUPIMMSD(unsigned Opcode) {
14817 switch (Opcode) {
14818 case VFIXUPIMMSDZrmi:
14819 case VFIXUPIMMSDZrmik:
14820 case VFIXUPIMMSDZrmikz:
14821 case VFIXUPIMMSDZrri:
14822 case VFIXUPIMMSDZrrib:
14823 case VFIXUPIMMSDZrribk:
14824 case VFIXUPIMMSDZrribkz:
14825 case VFIXUPIMMSDZrrik:
14826 case VFIXUPIMMSDZrrikz:
14827 return true;
14828 }
14829 return false;
14830}
14831
14832bool isINVD(unsigned Opcode) {
14833 return Opcode == INVD;
14834}
14835
14836bool isVFIXUPIMMPS(unsigned Opcode) {
14837 switch (Opcode) {
14838 case VFIXUPIMMPSZ128rmbi:
14839 case VFIXUPIMMPSZ128rmbik:
14840 case VFIXUPIMMPSZ128rmbikz:
14841 case VFIXUPIMMPSZ128rmi:
14842 case VFIXUPIMMPSZ128rmik:
14843 case VFIXUPIMMPSZ128rmikz:
14844 case VFIXUPIMMPSZ128rri:
14845 case VFIXUPIMMPSZ128rrik:
14846 case VFIXUPIMMPSZ128rrikz:
14847 case VFIXUPIMMPSZ256rmbi:
14848 case VFIXUPIMMPSZ256rmbik:
14849 case VFIXUPIMMPSZ256rmbikz:
14850 case VFIXUPIMMPSZ256rmi:
14851 case VFIXUPIMMPSZ256rmik:
14852 case VFIXUPIMMPSZ256rmikz:
14853 case VFIXUPIMMPSZ256rri:
14854 case VFIXUPIMMPSZ256rrik:
14855 case VFIXUPIMMPSZ256rrikz:
14856 case VFIXUPIMMPSZrmbi:
14857 case VFIXUPIMMPSZrmbik:
14858 case VFIXUPIMMPSZrmbikz:
14859 case VFIXUPIMMPSZrmi:
14860 case VFIXUPIMMPSZrmik:
14861 case VFIXUPIMMPSZrmikz:
14862 case VFIXUPIMMPSZrri:
14863 case VFIXUPIMMPSZrrib:
14864 case VFIXUPIMMPSZrribk:
14865 case VFIXUPIMMPSZrribkz:
14866 case VFIXUPIMMPSZrrik:
14867 case VFIXUPIMMPSZrrikz:
14868 return true;
14869 }
14870 return false;
14871}
14872
14873bool isMOVDQU(unsigned Opcode) {
14874 switch (Opcode) {
14875 case MOVDQUmr:
14876 case MOVDQUrm:
14877 case MOVDQUrr:
14878 case MOVDQUrr_REV:
14879 return true;
14880 }
14881 return false;
14882}
14883
14884bool isVFPCLASSPS(unsigned Opcode) {
14885 switch (Opcode) {
14886 case VFPCLASSPSZ128mbi:
14887 case VFPCLASSPSZ128mbik:
14888 case VFPCLASSPSZ128mi:
14889 case VFPCLASSPSZ128mik:
14890 case VFPCLASSPSZ128ri:
14891 case VFPCLASSPSZ128rik:
14892 case VFPCLASSPSZ256mbi:
14893 case VFPCLASSPSZ256mbik:
14894 case VFPCLASSPSZ256mi:
14895 case VFPCLASSPSZ256mik:
14896 case VFPCLASSPSZ256ri:
14897 case VFPCLASSPSZ256rik:
14898 case VFPCLASSPSZmbi:
14899 case VFPCLASSPSZmbik:
14900 case VFPCLASSPSZmi:
14901 case VFPCLASSPSZmik:
14902 case VFPCLASSPSZri:
14903 case VFPCLASSPSZrik:
14904 return true;
14905 }
14906 return false;
14907}
14908
14909bool isMOVSQ(unsigned Opcode) {
14910 return Opcode == MOVSQ;
14911}
14912
14913bool isAESDECWIDE128KL(unsigned Opcode) {
14914 return Opcode == AESDECWIDE128KL;
14915}
14916
14917bool isROUNDSS(unsigned Opcode) {
14918 switch (Opcode) {
14919 case ROUNDSSmi_Int:
14920 case ROUNDSSri_Int:
14921 return true;
14922 }
14923 return false;
14924}
14925
14926bool isVPERMILPS(unsigned Opcode) {
14927 switch (Opcode) {
14928 case VPERMILPSYmi:
14929 case VPERMILPSYri:
14930 case VPERMILPSYrm:
14931 case VPERMILPSYrr:
14932 case VPERMILPSZ128mbi:
14933 case VPERMILPSZ128mbik:
14934 case VPERMILPSZ128mbikz:
14935 case VPERMILPSZ128mi:
14936 case VPERMILPSZ128mik:
14937 case VPERMILPSZ128mikz:
14938 case VPERMILPSZ128ri:
14939 case VPERMILPSZ128rik:
14940 case VPERMILPSZ128rikz:
14941 case VPERMILPSZ128rm:
14942 case VPERMILPSZ128rmb:
14943 case VPERMILPSZ128rmbk:
14944 case VPERMILPSZ128rmbkz:
14945 case VPERMILPSZ128rmk:
14946 case VPERMILPSZ128rmkz:
14947 case VPERMILPSZ128rr:
14948 case VPERMILPSZ128rrk:
14949 case VPERMILPSZ128rrkz:
14950 case VPERMILPSZ256mbi:
14951 case VPERMILPSZ256mbik:
14952 case VPERMILPSZ256mbikz:
14953 case VPERMILPSZ256mi:
14954 case VPERMILPSZ256mik:
14955 case VPERMILPSZ256mikz:
14956 case VPERMILPSZ256ri:
14957 case VPERMILPSZ256rik:
14958 case VPERMILPSZ256rikz:
14959 case VPERMILPSZ256rm:
14960 case VPERMILPSZ256rmb:
14961 case VPERMILPSZ256rmbk:
14962 case VPERMILPSZ256rmbkz:
14963 case VPERMILPSZ256rmk:
14964 case VPERMILPSZ256rmkz:
14965 case VPERMILPSZ256rr:
14966 case VPERMILPSZ256rrk:
14967 case VPERMILPSZ256rrkz:
14968 case VPERMILPSZmbi:
14969 case VPERMILPSZmbik:
14970 case VPERMILPSZmbikz:
14971 case VPERMILPSZmi:
14972 case VPERMILPSZmik:
14973 case VPERMILPSZmikz:
14974 case VPERMILPSZri:
14975 case VPERMILPSZrik:
14976 case VPERMILPSZrikz:
14977 case VPERMILPSZrm:
14978 case VPERMILPSZrmb:
14979 case VPERMILPSZrmbk:
14980 case VPERMILPSZrmbkz:
14981 case VPERMILPSZrmk:
14982 case VPERMILPSZrmkz:
14983 case VPERMILPSZrr:
14984 case VPERMILPSZrrk:
14985 case VPERMILPSZrrkz:
14986 case VPERMILPSmi:
14987 case VPERMILPSri:
14988 case VPERMILPSrm:
14989 case VPERMILPSrr:
14990 return true;
14991 }
14992 return false;
14993}
14994
14995bool isVPMOVW2M(unsigned Opcode) {
14996 switch (Opcode) {
14997 case VPMOVW2MZ128kr:
14998 case VPMOVW2MZ256kr:
14999 case VPMOVW2MZkr:
15000 return true;
15001 }
15002 return false;
15003}
15004
15005bool isVMULSD(unsigned Opcode) {
15006 switch (Opcode) {
15007 case VMULSDZrm_Int:
15008 case VMULSDZrmk_Int:
15009 case VMULSDZrmkz_Int:
15010 case VMULSDZrr_Int:
15011 case VMULSDZrrb_Int:
15012 case VMULSDZrrbk_Int:
15013 case VMULSDZrrbkz_Int:
15014 case VMULSDZrrk_Int:
15015 case VMULSDZrrkz_Int:
15016 case VMULSDrm_Int:
15017 case VMULSDrr_Int:
15018 return true;
15019 }
15020 return false;
15021}
15022
15023bool isVPERMI2W(unsigned Opcode) {
15024 switch (Opcode) {
15025 case VPERMI2WZ128rm:
15026 case VPERMI2WZ128rmk:
15027 case VPERMI2WZ128rmkz:
15028 case VPERMI2WZ128rr:
15029 case VPERMI2WZ128rrk:
15030 case VPERMI2WZ128rrkz:
15031 case VPERMI2WZ256rm:
15032 case VPERMI2WZ256rmk:
15033 case VPERMI2WZ256rmkz:
15034 case VPERMI2WZ256rr:
15035 case VPERMI2WZ256rrk:
15036 case VPERMI2WZ256rrkz:
15037 case VPERMI2WZrm:
15038 case VPERMI2WZrmk:
15039 case VPERMI2WZrmkz:
15040 case VPERMI2WZrr:
15041 case VPERMI2WZrrk:
15042 case VPERMI2WZrrkz:
15043 return true;
15044 }
15045 return false;
15046}
15047
15048bool isVPSHUFB(unsigned Opcode) {
15049 switch (Opcode) {
15050 case VPSHUFBYrm:
15051 case VPSHUFBYrr:
15052 case VPSHUFBZ128rm:
15053 case VPSHUFBZ128rmk:
15054 case VPSHUFBZ128rmkz:
15055 case VPSHUFBZ128rr:
15056 case VPSHUFBZ128rrk:
15057 case VPSHUFBZ128rrkz:
15058 case VPSHUFBZ256rm:
15059 case VPSHUFBZ256rmk:
15060 case VPSHUFBZ256rmkz:
15061 case VPSHUFBZ256rr:
15062 case VPSHUFBZ256rrk:
15063 case VPSHUFBZ256rrkz:
15064 case VPSHUFBZrm:
15065 case VPSHUFBZrmk:
15066 case VPSHUFBZrmkz:
15067 case VPSHUFBZrr:
15068 case VPSHUFBZrrk:
15069 case VPSHUFBZrrkz:
15070 case VPSHUFBrm:
15071 case VPSHUFBrr:
15072 return true;
15073 }
15074 return false;
15075}
15076
15077bool isFST(unsigned Opcode) {
15078 switch (Opcode) {
15079 case ST_F32m:
15080 case ST_F64m:
15081 case ST_Frr:
15082 return true;
15083 }
15084 return false;
15085}
15086
15087bool isVPHSUBW(unsigned Opcode) {
15088 switch (Opcode) {
15089 case VPHSUBWYrm:
15090 case VPHSUBWYrr:
15091 case VPHSUBWrm:
15092 case VPHSUBWrr:
15093 return true;
15094 }
15095 return false;
15096}
15097
15098bool isVREDUCESS(unsigned Opcode) {
15099 switch (Opcode) {
15100 case VREDUCESSZrmi:
15101 case VREDUCESSZrmik:
15102 case VREDUCESSZrmikz:
15103 case VREDUCESSZrri:
15104 case VREDUCESSZrrib:
15105 case VREDUCESSZrribk:
15106 case VREDUCESSZrribkz:
15107 case VREDUCESSZrrik:
15108 case VREDUCESSZrrikz:
15109 return true;
15110 }
15111 return false;
15112}
15113
15114bool isFRNDINT(unsigned Opcode) {
15115 return Opcode == FRNDINT;
15116}
15117
15118bool isSHR(unsigned Opcode) {
15119 switch (Opcode) {
15120 case SHR16m1:
15121 case SHR16m1_EVEX:
15122 case SHR16m1_ND:
15123 case SHR16m1_NF:
15124 case SHR16m1_NF_ND:
15125 case SHR16mCL:
15126 case SHR16mCL_EVEX:
15127 case SHR16mCL_ND:
15128 case SHR16mCL_NF:
15129 case SHR16mCL_NF_ND:
15130 case SHR16mi:
15131 case SHR16mi_EVEX:
15132 case SHR16mi_ND:
15133 case SHR16mi_NF:
15134 case SHR16mi_NF_ND:
15135 case SHR16r1:
15136 case SHR16r1_EVEX:
15137 case SHR16r1_ND:
15138 case SHR16r1_NF:
15139 case SHR16r1_NF_ND:
15140 case SHR16rCL:
15141 case SHR16rCL_EVEX:
15142 case SHR16rCL_ND:
15143 case SHR16rCL_NF:
15144 case SHR16rCL_NF_ND:
15145 case SHR16ri:
15146 case SHR16ri_EVEX:
15147 case SHR16ri_ND:
15148 case SHR16ri_NF:
15149 case SHR16ri_NF_ND:
15150 case SHR32m1:
15151 case SHR32m1_EVEX:
15152 case SHR32m1_ND:
15153 case SHR32m1_NF:
15154 case SHR32m1_NF_ND:
15155 case SHR32mCL:
15156 case SHR32mCL_EVEX:
15157 case SHR32mCL_ND:
15158 case SHR32mCL_NF:
15159 case SHR32mCL_NF_ND:
15160 case SHR32mi:
15161 case SHR32mi_EVEX:
15162 case SHR32mi_ND:
15163 case SHR32mi_NF:
15164 case SHR32mi_NF_ND:
15165 case SHR32r1:
15166 case SHR32r1_EVEX:
15167 case SHR32r1_ND:
15168 case SHR32r1_NF:
15169 case SHR32r1_NF_ND:
15170 case SHR32rCL:
15171 case SHR32rCL_EVEX:
15172 case SHR32rCL_ND:
15173 case SHR32rCL_NF:
15174 case SHR32rCL_NF_ND:
15175 case SHR32ri:
15176 case SHR32ri_EVEX:
15177 case SHR32ri_ND:
15178 case SHR32ri_NF:
15179 case SHR32ri_NF_ND:
15180 case SHR64m1:
15181 case SHR64m1_EVEX:
15182 case SHR64m1_ND:
15183 case SHR64m1_NF:
15184 case SHR64m1_NF_ND:
15185 case SHR64mCL:
15186 case SHR64mCL_EVEX:
15187 case SHR64mCL_ND:
15188 case SHR64mCL_NF:
15189 case SHR64mCL_NF_ND:
15190 case SHR64mi:
15191 case SHR64mi_EVEX:
15192 case SHR64mi_ND:
15193 case SHR64mi_NF:
15194 case SHR64mi_NF_ND:
15195 case SHR64r1:
15196 case SHR64r1_EVEX:
15197 case SHR64r1_ND:
15198 case SHR64r1_NF:
15199 case SHR64r1_NF_ND:
15200 case SHR64rCL:
15201 case SHR64rCL_EVEX:
15202 case SHR64rCL_ND:
15203 case SHR64rCL_NF:
15204 case SHR64rCL_NF_ND:
15205 case SHR64ri:
15206 case SHR64ri_EVEX:
15207 case SHR64ri_ND:
15208 case SHR64ri_NF:
15209 case SHR64ri_NF_ND:
15210 case SHR8m1:
15211 case SHR8m1_EVEX:
15212 case SHR8m1_ND:
15213 case SHR8m1_NF:
15214 case SHR8m1_NF_ND:
15215 case SHR8mCL:
15216 case SHR8mCL_EVEX:
15217 case SHR8mCL_ND:
15218 case SHR8mCL_NF:
15219 case SHR8mCL_NF_ND:
15220 case SHR8mi:
15221 case SHR8mi_EVEX:
15222 case SHR8mi_ND:
15223 case SHR8mi_NF:
15224 case SHR8mi_NF_ND:
15225 case SHR8r1:
15226 case SHR8r1_EVEX:
15227 case SHR8r1_ND:
15228 case SHR8r1_NF:
15229 case SHR8r1_NF_ND:
15230 case SHR8rCL:
15231 case SHR8rCL_EVEX:
15232 case SHR8rCL_ND:
15233 case SHR8rCL_NF:
15234 case SHR8rCL_NF_ND:
15235 case SHR8ri:
15236 case SHR8ri_EVEX:
15237 case SHR8ri_ND:
15238 case SHR8ri_NF:
15239 case SHR8ri_NF_ND:
15240 return true;
15241 }
15242 return false;
15243}
15244
15245bool isLOOPNE(unsigned Opcode) {
15246 return Opcode == LOOPNE;
15247}
15248
15249bool isVCVTTPH2UQQ(unsigned Opcode) {
15250 switch (Opcode) {
15251 case VCVTTPH2UQQZ128rm:
15252 case VCVTTPH2UQQZ128rmb:
15253 case VCVTTPH2UQQZ128rmbk:
15254 case VCVTTPH2UQQZ128rmbkz:
15255 case VCVTTPH2UQQZ128rmk:
15256 case VCVTTPH2UQQZ128rmkz:
15257 case VCVTTPH2UQQZ128rr:
15258 case VCVTTPH2UQQZ128rrk:
15259 case VCVTTPH2UQQZ128rrkz:
15260 case VCVTTPH2UQQZ256rm:
15261 case VCVTTPH2UQQZ256rmb:
15262 case VCVTTPH2UQQZ256rmbk:
15263 case VCVTTPH2UQQZ256rmbkz:
15264 case VCVTTPH2UQQZ256rmk:
15265 case VCVTTPH2UQQZ256rmkz:
15266 case VCVTTPH2UQQZ256rr:
15267 case VCVTTPH2UQQZ256rrk:
15268 case VCVTTPH2UQQZ256rrkz:
15269 case VCVTTPH2UQQZrm:
15270 case VCVTTPH2UQQZrmb:
15271 case VCVTTPH2UQQZrmbk:
15272 case VCVTTPH2UQQZrmbkz:
15273 case VCVTTPH2UQQZrmk:
15274 case VCVTTPH2UQQZrmkz:
15275 case VCVTTPH2UQQZrr:
15276 case VCVTTPH2UQQZrrb:
15277 case VCVTTPH2UQQZrrbk:
15278 case VCVTTPH2UQQZrrbkz:
15279 case VCVTTPH2UQQZrrk:
15280 case VCVTTPH2UQQZrrkz:
15281 return true;
15282 }
15283 return false;
15284}
15285
15286bool isSHA1NEXTE(unsigned Opcode) {
15287 switch (Opcode) {
15288 case SHA1NEXTErm:
15289 case SHA1NEXTErr:
15290 return true;
15291 }
15292 return false;
15293}
15294
15295bool isVFMADD132SD(unsigned Opcode) {
15296 switch (Opcode) {
15297 case VFMADD132SDZm_Int:
15298 case VFMADD132SDZmk_Int:
15299 case VFMADD132SDZmkz_Int:
15300 case VFMADD132SDZr_Int:
15301 case VFMADD132SDZrb_Int:
15302 case VFMADD132SDZrbk_Int:
15303 case VFMADD132SDZrbkz_Int:
15304 case VFMADD132SDZrk_Int:
15305 case VFMADD132SDZrkz_Int:
15306 case VFMADD132SDm_Int:
15307 case VFMADD132SDr_Int:
15308 return true;
15309 }
15310 return false;
15311}
15312
15313bool isPSRAW(unsigned Opcode) {
15314 switch (Opcode) {
15315 case MMX_PSRAWri:
15316 case MMX_PSRAWrm:
15317 case MMX_PSRAWrr:
15318 case PSRAWri:
15319 case PSRAWrm:
15320 case PSRAWrr:
15321 return true;
15322 }
15323 return false;
15324}
15325
15326bool isVPBROADCASTQ(unsigned Opcode) {
15327 switch (Opcode) {
15328 case VPBROADCASTQYrm:
15329 case VPBROADCASTQYrr:
15330 case VPBROADCASTQZ128rm:
15331 case VPBROADCASTQZ128rmk:
15332 case VPBROADCASTQZ128rmkz:
15333 case VPBROADCASTQZ128rr:
15334 case VPBROADCASTQZ128rrk:
15335 case VPBROADCASTQZ128rrkz:
15336 case VPBROADCASTQZ256rm:
15337 case VPBROADCASTQZ256rmk:
15338 case VPBROADCASTQZ256rmkz:
15339 case VPBROADCASTQZ256rr:
15340 case VPBROADCASTQZ256rrk:
15341 case VPBROADCASTQZ256rrkz:
15342 case VPBROADCASTQZrm:
15343 case VPBROADCASTQZrmk:
15344 case VPBROADCASTQZrmkz:
15345 case VPBROADCASTQZrr:
15346 case VPBROADCASTQZrrk:
15347 case VPBROADCASTQZrrkz:
15348 case VPBROADCASTQrZ128rr:
15349 case VPBROADCASTQrZ128rrk:
15350 case VPBROADCASTQrZ128rrkz:
15351 case VPBROADCASTQrZ256rr:
15352 case VPBROADCASTQrZ256rrk:
15353 case VPBROADCASTQrZ256rrkz:
15354 case VPBROADCASTQrZrr:
15355 case VPBROADCASTQrZrrk:
15356 case VPBROADCASTQrZrrkz:
15357 case VPBROADCASTQrm:
15358 case VPBROADCASTQrr:
15359 return true;
15360 }
15361 return false;
15362}
15363
15364bool isCLC(unsigned Opcode) {
15365 return Opcode == CLC;
15366}
15367
15368bool isPOPAW(unsigned Opcode) {
15369 return Opcode == POPA16;
15370}
15371
15372bool isTCMMIMFP16PS(unsigned Opcode) {
15373 return Opcode == TCMMIMFP16PS;
15374}
15375
15376bool isVCVTTPS2UQQ(unsigned Opcode) {
15377 switch (Opcode) {
15378 case VCVTTPS2UQQZ128rm:
15379 case VCVTTPS2UQQZ128rmb:
15380 case VCVTTPS2UQQZ128rmbk:
15381 case VCVTTPS2UQQZ128rmbkz:
15382 case VCVTTPS2UQQZ128rmk:
15383 case VCVTTPS2UQQZ128rmkz:
15384 case VCVTTPS2UQQZ128rr:
15385 case VCVTTPS2UQQZ128rrk:
15386 case VCVTTPS2UQQZ128rrkz:
15387 case VCVTTPS2UQQZ256rm:
15388 case VCVTTPS2UQQZ256rmb:
15389 case VCVTTPS2UQQZ256rmbk:
15390 case VCVTTPS2UQQZ256rmbkz:
15391 case VCVTTPS2UQQZ256rmk:
15392 case VCVTTPS2UQQZ256rmkz:
15393 case VCVTTPS2UQQZ256rr:
15394 case VCVTTPS2UQQZ256rrk:
15395 case VCVTTPS2UQQZ256rrkz:
15396 case VCVTTPS2UQQZrm:
15397 case VCVTTPS2UQQZrmb:
15398 case VCVTTPS2UQQZrmbk:
15399 case VCVTTPS2UQQZrmbkz:
15400 case VCVTTPS2UQQZrmk:
15401 case VCVTTPS2UQQZrmkz:
15402 case VCVTTPS2UQQZrr:
15403 case VCVTTPS2UQQZrrb:
15404 case VCVTTPS2UQQZrrbk:
15405 case VCVTTPS2UQQZrrbkz:
15406 case VCVTTPS2UQQZrrk:
15407 case VCVTTPS2UQQZrrkz:
15408 return true;
15409 }
15410 return false;
15411}
15412
15413bool isVCVTQQ2PH(unsigned Opcode) {
15414 switch (Opcode) {
15415 case VCVTQQ2PHZ128rm:
15416 case VCVTQQ2PHZ128rmb:
15417 case VCVTQQ2PHZ128rmbk:
15418 case VCVTQQ2PHZ128rmbkz:
15419 case VCVTQQ2PHZ128rmk:
15420 case VCVTQQ2PHZ128rmkz:
15421 case VCVTQQ2PHZ128rr:
15422 case VCVTQQ2PHZ128rrk:
15423 case VCVTQQ2PHZ128rrkz:
15424 case VCVTQQ2PHZ256rm:
15425 case VCVTQQ2PHZ256rmb:
15426 case VCVTQQ2PHZ256rmbk:
15427 case VCVTQQ2PHZ256rmbkz:
15428 case VCVTQQ2PHZ256rmk:
15429 case VCVTQQ2PHZ256rmkz:
15430 case VCVTQQ2PHZ256rr:
15431 case VCVTQQ2PHZ256rrk:
15432 case VCVTQQ2PHZ256rrkz:
15433 case VCVTQQ2PHZrm:
15434 case VCVTQQ2PHZrmb:
15435 case VCVTQQ2PHZrmbk:
15436 case VCVTQQ2PHZrmbkz:
15437 case VCVTQQ2PHZrmk:
15438 case VCVTQQ2PHZrmkz:
15439 case VCVTQQ2PHZrr:
15440 case VCVTQQ2PHZrrb:
15441 case VCVTQQ2PHZrrbk:
15442 case VCVTQQ2PHZrrbkz:
15443 case VCVTQQ2PHZrrk:
15444 case VCVTQQ2PHZrrkz:
15445 return true;
15446 }
15447 return false;
15448}
15449
15450bool isVMOVUPD(unsigned Opcode) {
15451 switch (Opcode) {
15452 case VMOVUPDYmr:
15453 case VMOVUPDYrm:
15454 case VMOVUPDYrr:
15455 case VMOVUPDYrr_REV:
15456 case VMOVUPDZ128mr:
15457 case VMOVUPDZ128mrk:
15458 case VMOVUPDZ128rm:
15459 case VMOVUPDZ128rmk:
15460 case VMOVUPDZ128rmkz:
15461 case VMOVUPDZ128rr:
15462 case VMOVUPDZ128rr_REV:
15463 case VMOVUPDZ128rrk:
15464 case VMOVUPDZ128rrk_REV:
15465 case VMOVUPDZ128rrkz:
15466 case VMOVUPDZ128rrkz_REV:
15467 case VMOVUPDZ256mr:
15468 case VMOVUPDZ256mrk:
15469 case VMOVUPDZ256rm:
15470 case VMOVUPDZ256rmk:
15471 case VMOVUPDZ256rmkz:
15472 case VMOVUPDZ256rr:
15473 case VMOVUPDZ256rr_REV:
15474 case VMOVUPDZ256rrk:
15475 case VMOVUPDZ256rrk_REV:
15476 case VMOVUPDZ256rrkz:
15477 case VMOVUPDZ256rrkz_REV:
15478 case VMOVUPDZmr:
15479 case VMOVUPDZmrk:
15480 case VMOVUPDZrm:
15481 case VMOVUPDZrmk:
15482 case VMOVUPDZrmkz:
15483 case VMOVUPDZrr:
15484 case VMOVUPDZrr_REV:
15485 case VMOVUPDZrrk:
15486 case VMOVUPDZrrk_REV:
15487 case VMOVUPDZrrkz:
15488 case VMOVUPDZrrkz_REV:
15489 case VMOVUPDmr:
15490 case VMOVUPDrm:
15491 case VMOVUPDrr:
15492 case VMOVUPDrr_REV:
15493 return true;
15494 }
15495 return false;
15496}
15497
15498bool isFPTAN(unsigned Opcode) {
15499 return Opcode == FPTAN;
15500}
15501
15502bool isVMASKMOVPD(unsigned Opcode) {
15503 switch (Opcode) {
15504 case VMASKMOVPDYmr:
15505 case VMASKMOVPDYrm:
15506 case VMASKMOVPDmr:
15507 case VMASKMOVPDrm:
15508 return true;
15509 }
15510 return false;
15511}
15512
15513bool isVMOVLHPS(unsigned Opcode) {
15514 switch (Opcode) {
15515 case VMOVLHPSZrr:
15516 case VMOVLHPSrr:
15517 return true;
15518 }
15519 return false;
15520}
15521
15522bool isAESKEYGENASSIST(unsigned Opcode) {
15523 switch (Opcode) {
15524 case AESKEYGENASSISTrmi:
15525 case AESKEYGENASSISTrri:
15526 return true;
15527 }
15528 return false;
15529}
15530
15531bool isXSAVEOPT64(unsigned Opcode) {
15532 return Opcode == XSAVEOPT64;
15533}
15534
15535bool isXSAVEC(unsigned Opcode) {
15536 return Opcode == XSAVEC;
15537}
15538
15539bool isVPLZCNTQ(unsigned Opcode) {
15540 switch (Opcode) {
15541 case VPLZCNTQZ128rm:
15542 case VPLZCNTQZ128rmb:
15543 case VPLZCNTQZ128rmbk:
15544 case VPLZCNTQZ128rmbkz:
15545 case VPLZCNTQZ128rmk:
15546 case VPLZCNTQZ128rmkz:
15547 case VPLZCNTQZ128rr:
15548 case VPLZCNTQZ128rrk:
15549 case VPLZCNTQZ128rrkz:
15550 case VPLZCNTQZ256rm:
15551 case VPLZCNTQZ256rmb:
15552 case VPLZCNTQZ256rmbk:
15553 case VPLZCNTQZ256rmbkz:
15554 case VPLZCNTQZ256rmk:
15555 case VPLZCNTQZ256rmkz:
15556 case VPLZCNTQZ256rr:
15557 case VPLZCNTQZ256rrk:
15558 case VPLZCNTQZ256rrkz:
15559 case VPLZCNTQZrm:
15560 case VPLZCNTQZrmb:
15561 case VPLZCNTQZrmbk:
15562 case VPLZCNTQZrmbkz:
15563 case VPLZCNTQZrmk:
15564 case VPLZCNTQZrmkz:
15565 case VPLZCNTQZrr:
15566 case VPLZCNTQZrrk:
15567 case VPLZCNTQZrrkz:
15568 return true;
15569 }
15570 return false;
15571}
15572
15573bool isVPSUBW(unsigned Opcode) {
15574 switch (Opcode) {
15575 case VPSUBWYrm:
15576 case VPSUBWYrr:
15577 case VPSUBWZ128rm:
15578 case VPSUBWZ128rmk:
15579 case VPSUBWZ128rmkz:
15580 case VPSUBWZ128rr:
15581 case VPSUBWZ128rrk:
15582 case VPSUBWZ128rrkz:
15583 case VPSUBWZ256rm:
15584 case VPSUBWZ256rmk:
15585 case VPSUBWZ256rmkz:
15586 case VPSUBWZ256rr:
15587 case VPSUBWZ256rrk:
15588 case VPSUBWZ256rrkz:
15589 case VPSUBWZrm:
15590 case VPSUBWZrmk:
15591 case VPSUBWZrmkz:
15592 case VPSUBWZrr:
15593 case VPSUBWZrrk:
15594 case VPSUBWZrrkz:
15595 case VPSUBWrm:
15596 case VPSUBWrr:
15597 return true;
15598 }
15599 return false;
15600}
15601
15602bool isCMPCCXADD(unsigned Opcode) {
15603 switch (Opcode) {
15604 case CMPCCXADDmr32:
15605 case CMPCCXADDmr32_EVEX:
15606 case CMPCCXADDmr64:
15607 case CMPCCXADDmr64_EVEX:
15608 return true;
15609 }
15610 return false;
15611}
15612
15613bool isVFMSUBADD213PH(unsigned Opcode) {
15614 switch (Opcode) {
15615 case VFMSUBADD213PHZ128m:
15616 case VFMSUBADD213PHZ128mb:
15617 case VFMSUBADD213PHZ128mbk:
15618 case VFMSUBADD213PHZ128mbkz:
15619 case VFMSUBADD213PHZ128mk:
15620 case VFMSUBADD213PHZ128mkz:
15621 case VFMSUBADD213PHZ128r:
15622 case VFMSUBADD213PHZ128rk:
15623 case VFMSUBADD213PHZ128rkz:
15624 case VFMSUBADD213PHZ256m:
15625 case VFMSUBADD213PHZ256mb:
15626 case VFMSUBADD213PHZ256mbk:
15627 case VFMSUBADD213PHZ256mbkz:
15628 case VFMSUBADD213PHZ256mk:
15629 case VFMSUBADD213PHZ256mkz:
15630 case VFMSUBADD213PHZ256r:
15631 case VFMSUBADD213PHZ256rk:
15632 case VFMSUBADD213PHZ256rkz:
15633 case VFMSUBADD213PHZm:
15634 case VFMSUBADD213PHZmb:
15635 case VFMSUBADD213PHZmbk:
15636 case VFMSUBADD213PHZmbkz:
15637 case VFMSUBADD213PHZmk:
15638 case VFMSUBADD213PHZmkz:
15639 case VFMSUBADD213PHZr:
15640 case VFMSUBADD213PHZrb:
15641 case VFMSUBADD213PHZrbk:
15642 case VFMSUBADD213PHZrbkz:
15643 case VFMSUBADD213PHZrk:
15644 case VFMSUBADD213PHZrkz:
15645 return true;
15646 }
15647 return false;
15648}
15649
15650bool isVFMADDSUBPD(unsigned Opcode) {
15651 switch (Opcode) {
15652 case VFMADDSUBPD4Ymr:
15653 case VFMADDSUBPD4Yrm:
15654 case VFMADDSUBPD4Yrr:
15655 case VFMADDSUBPD4Yrr_REV:
15656 case VFMADDSUBPD4mr:
15657 case VFMADDSUBPD4rm:
15658 case VFMADDSUBPD4rr:
15659 case VFMADDSUBPD4rr_REV:
15660 return true;
15661 }
15662 return false;
15663}
15664
15665bool isVPMINSW(unsigned Opcode) {
15666 switch (Opcode) {
15667 case VPMINSWYrm:
15668 case VPMINSWYrr:
15669 case VPMINSWZ128rm:
15670 case VPMINSWZ128rmk:
15671 case VPMINSWZ128rmkz:
15672 case VPMINSWZ128rr:
15673 case VPMINSWZ128rrk:
15674 case VPMINSWZ128rrkz:
15675 case VPMINSWZ256rm:
15676 case VPMINSWZ256rmk:
15677 case VPMINSWZ256rmkz:
15678 case VPMINSWZ256rr:
15679 case VPMINSWZ256rrk:
15680 case VPMINSWZ256rrkz:
15681 case VPMINSWZrm:
15682 case VPMINSWZrmk:
15683 case VPMINSWZrmkz:
15684 case VPMINSWZrr:
15685 case VPMINSWZrrk:
15686 case VPMINSWZrrkz:
15687 case VPMINSWrm:
15688 case VPMINSWrr:
15689 return true;
15690 }
15691 return false;
15692}
15693
15694bool isVFNMSUB132PS(unsigned Opcode) {
15695 switch (Opcode) {
15696 case VFNMSUB132PSYm:
15697 case VFNMSUB132PSYr:
15698 case VFNMSUB132PSZ128m:
15699 case VFNMSUB132PSZ128mb:
15700 case VFNMSUB132PSZ128mbk:
15701 case VFNMSUB132PSZ128mbkz:
15702 case VFNMSUB132PSZ128mk:
15703 case VFNMSUB132PSZ128mkz:
15704 case VFNMSUB132PSZ128r:
15705 case VFNMSUB132PSZ128rk:
15706 case VFNMSUB132PSZ128rkz:
15707 case VFNMSUB132PSZ256m:
15708 case VFNMSUB132PSZ256mb:
15709 case VFNMSUB132PSZ256mbk:
15710 case VFNMSUB132PSZ256mbkz:
15711 case VFNMSUB132PSZ256mk:
15712 case VFNMSUB132PSZ256mkz:
15713 case VFNMSUB132PSZ256r:
15714 case VFNMSUB132PSZ256rk:
15715 case VFNMSUB132PSZ256rkz:
15716 case VFNMSUB132PSZm:
15717 case VFNMSUB132PSZmb:
15718 case VFNMSUB132PSZmbk:
15719 case VFNMSUB132PSZmbkz:
15720 case VFNMSUB132PSZmk:
15721 case VFNMSUB132PSZmkz:
15722 case VFNMSUB132PSZr:
15723 case VFNMSUB132PSZrb:
15724 case VFNMSUB132PSZrbk:
15725 case VFNMSUB132PSZrbkz:
15726 case VFNMSUB132PSZrk:
15727 case VFNMSUB132PSZrkz:
15728 case VFNMSUB132PSm:
15729 case VFNMSUB132PSr:
15730 return true;
15731 }
15732 return false;
15733}
15734
15735bool isVMOVAPS(unsigned Opcode) {
15736 switch (Opcode) {
15737 case VMOVAPSYmr:
15738 case VMOVAPSYrm:
15739 case VMOVAPSYrr:
15740 case VMOVAPSYrr_REV:
15741 case VMOVAPSZ128mr:
15742 case VMOVAPSZ128mrk:
15743 case VMOVAPSZ128rm:
15744 case VMOVAPSZ128rmk:
15745 case VMOVAPSZ128rmkz:
15746 case VMOVAPSZ128rr:
15747 case VMOVAPSZ128rr_REV:
15748 case VMOVAPSZ128rrk:
15749 case VMOVAPSZ128rrk_REV:
15750 case VMOVAPSZ128rrkz:
15751 case VMOVAPSZ128rrkz_REV:
15752 case VMOVAPSZ256mr:
15753 case VMOVAPSZ256mrk:
15754 case VMOVAPSZ256rm:
15755 case VMOVAPSZ256rmk:
15756 case VMOVAPSZ256rmkz:
15757 case VMOVAPSZ256rr:
15758 case VMOVAPSZ256rr_REV:
15759 case VMOVAPSZ256rrk:
15760 case VMOVAPSZ256rrk_REV:
15761 case VMOVAPSZ256rrkz:
15762 case VMOVAPSZ256rrkz_REV:
15763 case VMOVAPSZmr:
15764 case VMOVAPSZmrk:
15765 case VMOVAPSZrm:
15766 case VMOVAPSZrmk:
15767 case VMOVAPSZrmkz:
15768 case VMOVAPSZrr:
15769 case VMOVAPSZrr_REV:
15770 case VMOVAPSZrrk:
15771 case VMOVAPSZrrk_REV:
15772 case VMOVAPSZrrkz:
15773 case VMOVAPSZrrkz_REV:
15774 case VMOVAPSmr:
15775 case VMOVAPSrm:
15776 case VMOVAPSrr:
15777 case VMOVAPSrr_REV:
15778 return true;
15779 }
15780 return false;
15781}
15782
15783bool isVPEXTRQ(unsigned Opcode) {
15784 switch (Opcode) {
15785 case VPEXTRQZmri:
15786 case VPEXTRQZrri:
15787 case VPEXTRQmri:
15788 case VPEXTRQrri:
15789 return true;
15790 }
15791 return false;
15792}
15793
15794bool isVSCALEFSH(unsigned Opcode) {
15795 switch (Opcode) {
15796 case VSCALEFSHZrm:
15797 case VSCALEFSHZrmk:
15798 case VSCALEFSHZrmkz:
15799 case VSCALEFSHZrr:
15800 case VSCALEFSHZrrb_Int:
15801 case VSCALEFSHZrrbk_Int:
15802 case VSCALEFSHZrrbkz_Int:
15803 case VSCALEFSHZrrk:
15804 case VSCALEFSHZrrkz:
15805 return true;
15806 }
15807 return false;
15808}
15809
15810bool isVCVTPD2PS(unsigned Opcode) {
15811 switch (Opcode) {
15812 case VCVTPD2PSYrm:
15813 case VCVTPD2PSYrr:
15814 case VCVTPD2PSZ128rm:
15815 case VCVTPD2PSZ128rmb:
15816 case VCVTPD2PSZ128rmbk:
15817 case VCVTPD2PSZ128rmbkz:
15818 case VCVTPD2PSZ128rmk:
15819 case VCVTPD2PSZ128rmkz:
15820 case VCVTPD2PSZ128rr:
15821 case VCVTPD2PSZ128rrk:
15822 case VCVTPD2PSZ128rrkz:
15823 case VCVTPD2PSZ256rm:
15824 case VCVTPD2PSZ256rmb:
15825 case VCVTPD2PSZ256rmbk:
15826 case VCVTPD2PSZ256rmbkz:
15827 case VCVTPD2PSZ256rmk:
15828 case VCVTPD2PSZ256rmkz:
15829 case VCVTPD2PSZ256rr:
15830 case VCVTPD2PSZ256rrk:
15831 case VCVTPD2PSZ256rrkz:
15832 case VCVTPD2PSZrm:
15833 case VCVTPD2PSZrmb:
15834 case VCVTPD2PSZrmbk:
15835 case VCVTPD2PSZrmbkz:
15836 case VCVTPD2PSZrmk:
15837 case VCVTPD2PSZrmkz:
15838 case VCVTPD2PSZrr:
15839 case VCVTPD2PSZrrb:
15840 case VCVTPD2PSZrrbk:
15841 case VCVTPD2PSZrrbkz:
15842 case VCVTPD2PSZrrk:
15843 case VCVTPD2PSZrrkz:
15844 case VCVTPD2PSrm:
15845 case VCVTPD2PSrr:
15846 return true;
15847 }
15848 return false;
15849}
15850
15851bool isCLGI(unsigned Opcode) {
15852 return Opcode == CLGI;
15853}
15854
15855bool isVAESDEC(unsigned Opcode) {
15856 switch (Opcode) {
15857 case VAESDECYrm:
15858 case VAESDECYrr:
15859 case VAESDECZ128rm:
15860 case VAESDECZ128rr:
15861 case VAESDECZ256rm:
15862 case VAESDECZ256rr:
15863 case VAESDECZrm:
15864 case VAESDECZrr:
15865 case VAESDECrm:
15866 case VAESDECrr:
15867 return true;
15868 }
15869 return false;
15870}
15871
15872bool isPFMUL(unsigned Opcode) {
15873 switch (Opcode) {
15874 case PFMULrm:
15875 case PFMULrr:
15876 return true;
15877 }
15878 return false;
15879}
15880
15881bool isVCVTBIASPH2BF8S(unsigned Opcode) {
15882 switch (Opcode) {
15883 case VCVTBIASPH2BF8SZ128rm:
15884 case VCVTBIASPH2BF8SZ128rmb:
15885 case VCVTBIASPH2BF8SZ128rmbk:
15886 case VCVTBIASPH2BF8SZ128rmbkz:
15887 case VCVTBIASPH2BF8SZ128rmk:
15888 case VCVTBIASPH2BF8SZ128rmkz:
15889 case VCVTBIASPH2BF8SZ128rr:
15890 case VCVTBIASPH2BF8SZ128rrk:
15891 case VCVTBIASPH2BF8SZ128rrkz:
15892 case VCVTBIASPH2BF8SZ256rm:
15893 case VCVTBIASPH2BF8SZ256rmb:
15894 case VCVTBIASPH2BF8SZ256rmbk:
15895 case VCVTBIASPH2BF8SZ256rmbkz:
15896 case VCVTBIASPH2BF8SZ256rmk:
15897 case VCVTBIASPH2BF8SZ256rmkz:
15898 case VCVTBIASPH2BF8SZ256rr:
15899 case VCVTBIASPH2BF8SZ256rrk:
15900 case VCVTBIASPH2BF8SZ256rrkz:
15901 case VCVTBIASPH2BF8SZrm:
15902 case VCVTBIASPH2BF8SZrmb:
15903 case VCVTBIASPH2BF8SZrmbk:
15904 case VCVTBIASPH2BF8SZrmbkz:
15905 case VCVTBIASPH2BF8SZrmk:
15906 case VCVTBIASPH2BF8SZrmkz:
15907 case VCVTBIASPH2BF8SZrr:
15908 case VCVTBIASPH2BF8SZrrk:
15909 case VCVTBIASPH2BF8SZrrkz:
15910 return true;
15911 }
15912 return false;
15913}
15914
15915bool isMOVDIRI(unsigned Opcode) {
15916 switch (Opcode) {
15917 case MOVDIRI32:
15918 case MOVDIRI32_EVEX:
15919 case MOVDIRI64:
15920 case MOVDIRI64_EVEX:
15921 return true;
15922 }
15923 return false;
15924}
15925
15926bool isSHUFPS(unsigned Opcode) {
15927 switch (Opcode) {
15928 case SHUFPSrmi:
15929 case SHUFPSrri:
15930 return true;
15931 }
15932 return false;
15933}
15934
15935bool isVFNMSUB231SS(unsigned Opcode) {
15936 switch (Opcode) {
15937 case VFNMSUB231SSZm_Int:
15938 case VFNMSUB231SSZmk_Int:
15939 case VFNMSUB231SSZmkz_Int:
15940 case VFNMSUB231SSZr_Int:
15941 case VFNMSUB231SSZrb_Int:
15942 case VFNMSUB231SSZrbk_Int:
15943 case VFNMSUB231SSZrbkz_Int:
15944 case VFNMSUB231SSZrk_Int:
15945 case VFNMSUB231SSZrkz_Int:
15946 case VFNMSUB231SSm_Int:
15947 case VFNMSUB231SSr_Int:
15948 return true;
15949 }
15950 return false;
15951}
15952
15953bool isVMWRITE(unsigned Opcode) {
15954 switch (Opcode) {
15955 case VMWRITE32rm:
15956 case VMWRITE32rr:
15957 case VMWRITE64rm:
15958 case VMWRITE64rr:
15959 return true;
15960 }
15961 return false;
15962}
15963
15964bool isVINSERTF128(unsigned Opcode) {
15965 switch (Opcode) {
15966 case VINSERTF128rmi:
15967 case VINSERTF128rri:
15968 return true;
15969 }
15970 return false;
15971}
15972
15973bool isFISUBR(unsigned Opcode) {
15974 switch (Opcode) {
15975 case SUBR_FI16m:
15976 case SUBR_FI32m:
15977 return true;
15978 }
15979 return false;
15980}
15981
15982bool isVINSERTI32X4(unsigned Opcode) {
15983 switch (Opcode) {
15984 case VINSERTI32X4Z256rmi:
15985 case VINSERTI32X4Z256rmik:
15986 case VINSERTI32X4Z256rmikz:
15987 case VINSERTI32X4Z256rri:
15988 case VINSERTI32X4Z256rrik:
15989 case VINSERTI32X4Z256rrikz:
15990 case VINSERTI32X4Zrmi:
15991 case VINSERTI32X4Zrmik:
15992 case VINSERTI32X4Zrmikz:
15993 case VINSERTI32X4Zrri:
15994 case VINSERTI32X4Zrrik:
15995 case VINSERTI32X4Zrrikz:
15996 return true;
15997 }
15998 return false;
15999}
16000
16001bool isVPSLLDQ(unsigned Opcode) {
16002 switch (Opcode) {
16003 case VPSLLDQYri:
16004 case VPSLLDQZ128mi:
16005 case VPSLLDQZ128ri:
16006 case VPSLLDQZ256mi:
16007 case VPSLLDQZ256ri:
16008 case VPSLLDQZmi:
16009 case VPSLLDQZri:
16010 case VPSLLDQri:
16011 return true;
16012 }
16013 return false;
16014}
16015
16016bool isPOPCNT(unsigned Opcode) {
16017 switch (Opcode) {
16018 case POPCNT16rm:
16019 case POPCNT16rm_EVEX:
16020 case POPCNT16rm_NF:
16021 case POPCNT16rr:
16022 case POPCNT16rr_EVEX:
16023 case POPCNT16rr_NF:
16024 case POPCNT32rm:
16025 case POPCNT32rm_EVEX:
16026 case POPCNT32rm_NF:
16027 case POPCNT32rr:
16028 case POPCNT32rr_EVEX:
16029 case POPCNT32rr_NF:
16030 case POPCNT64rm:
16031 case POPCNT64rm_EVEX:
16032 case POPCNT64rm_NF:
16033 case POPCNT64rr:
16034 case POPCNT64rr_EVEX:
16035 case POPCNT64rr_NF:
16036 return true;
16037 }
16038 return false;
16039}
16040
16041bool isVXORPD(unsigned Opcode) {
16042 switch (Opcode) {
16043 case VXORPDYrm:
16044 case VXORPDYrr:
16045 case VXORPDZ128rm:
16046 case VXORPDZ128rmb:
16047 case VXORPDZ128rmbk:
16048 case VXORPDZ128rmbkz:
16049 case VXORPDZ128rmk:
16050 case VXORPDZ128rmkz:
16051 case VXORPDZ128rr:
16052 case VXORPDZ128rrk:
16053 case VXORPDZ128rrkz:
16054 case VXORPDZ256rm:
16055 case VXORPDZ256rmb:
16056 case VXORPDZ256rmbk:
16057 case VXORPDZ256rmbkz:
16058 case VXORPDZ256rmk:
16059 case VXORPDZ256rmkz:
16060 case VXORPDZ256rr:
16061 case VXORPDZ256rrk:
16062 case VXORPDZ256rrkz:
16063 case VXORPDZrm:
16064 case VXORPDZrmb:
16065 case VXORPDZrmbk:
16066 case VXORPDZrmbkz:
16067 case VXORPDZrmk:
16068 case VXORPDZrmkz:
16069 case VXORPDZrr:
16070 case VXORPDZrrk:
16071 case VXORPDZrrkz:
16072 case VXORPDrm:
16073 case VXORPDrr:
16074 return true;
16075 }
16076 return false;
16077}
16078
16079bool isXLATB(unsigned Opcode) {
16080 return Opcode == XLAT;
16081}
16082
16083bool isDIV(unsigned Opcode) {
16084 switch (Opcode) {
16085 case DIV16m:
16086 case DIV16m_EVEX:
16087 case DIV16m_NF:
16088 case DIV16r:
16089 case DIV16r_EVEX:
16090 case DIV16r_NF:
16091 case DIV32m:
16092 case DIV32m_EVEX:
16093 case DIV32m_NF:
16094 case DIV32r:
16095 case DIV32r_EVEX:
16096 case DIV32r_NF:
16097 case DIV64m:
16098 case DIV64m_EVEX:
16099 case DIV64m_NF:
16100 case DIV64r:
16101 case DIV64r_EVEX:
16102 case DIV64r_NF:
16103 case DIV8m:
16104 case DIV8m_EVEX:
16105 case DIV8m_NF:
16106 case DIV8r:
16107 case DIV8r_EVEX:
16108 case DIV8r_NF:
16109 return true;
16110 }
16111 return false;
16112}
16113
16114bool isVPSHLDVQ(unsigned Opcode) {
16115 switch (Opcode) {
16116 case VPSHLDVQZ128m:
16117 case VPSHLDVQZ128mb:
16118 case VPSHLDVQZ128mbk:
16119 case VPSHLDVQZ128mbkz:
16120 case VPSHLDVQZ128mk:
16121 case VPSHLDVQZ128mkz:
16122 case VPSHLDVQZ128r:
16123 case VPSHLDVQZ128rk:
16124 case VPSHLDVQZ128rkz:
16125 case VPSHLDVQZ256m:
16126 case VPSHLDVQZ256mb:
16127 case VPSHLDVQZ256mbk:
16128 case VPSHLDVQZ256mbkz:
16129 case VPSHLDVQZ256mk:
16130 case VPSHLDVQZ256mkz:
16131 case VPSHLDVQZ256r:
16132 case VPSHLDVQZ256rk:
16133 case VPSHLDVQZ256rkz:
16134 case VPSHLDVQZm:
16135 case VPSHLDVQZmb:
16136 case VPSHLDVQZmbk:
16137 case VPSHLDVQZmbkz:
16138 case VPSHLDVQZmk:
16139 case VPSHLDVQZmkz:
16140 case VPSHLDVQZr:
16141 case VPSHLDVQZrk:
16142 case VPSHLDVQZrkz:
16143 return true;
16144 }
16145 return false;
16146}
16147
16148bool isMOVDDUP(unsigned Opcode) {
16149 switch (Opcode) {
16150 case MOVDDUPrm:
16151 case MOVDDUPrr:
16152 return true;
16153 }
16154 return false;
16155}
16156
16157bool isVMOVDQU64(unsigned Opcode) {
16158 switch (Opcode) {
16159 case VMOVDQU64Z128mr:
16160 case VMOVDQU64Z128mrk:
16161 case VMOVDQU64Z128rm:
16162 case VMOVDQU64Z128rmk:
16163 case VMOVDQU64Z128rmkz:
16164 case VMOVDQU64Z128rr:
16165 case VMOVDQU64Z128rr_REV:
16166 case VMOVDQU64Z128rrk:
16167 case VMOVDQU64Z128rrk_REV:
16168 case VMOVDQU64Z128rrkz:
16169 case VMOVDQU64Z128rrkz_REV:
16170 case VMOVDQU64Z256mr:
16171 case VMOVDQU64Z256mrk:
16172 case VMOVDQU64Z256rm:
16173 case VMOVDQU64Z256rmk:
16174 case VMOVDQU64Z256rmkz:
16175 case VMOVDQU64Z256rr:
16176 case VMOVDQU64Z256rr_REV:
16177 case VMOVDQU64Z256rrk:
16178 case VMOVDQU64Z256rrk_REV:
16179 case VMOVDQU64Z256rrkz:
16180 case VMOVDQU64Z256rrkz_REV:
16181 case VMOVDQU64Zmr:
16182 case VMOVDQU64Zmrk:
16183 case VMOVDQU64Zrm:
16184 case VMOVDQU64Zrmk:
16185 case VMOVDQU64Zrmkz:
16186 case VMOVDQU64Zrr:
16187 case VMOVDQU64Zrr_REV:
16188 case VMOVDQU64Zrrk:
16189 case VMOVDQU64Zrrk_REV:
16190 case VMOVDQU64Zrrkz:
16191 case VMOVDQU64Zrrkz_REV:
16192 return true;
16193 }
16194 return false;
16195}
16196
16197bool isVPCOMPRESSQ(unsigned Opcode) {
16198 switch (Opcode) {
16199 case VPCOMPRESSQZ128mr:
16200 case VPCOMPRESSQZ128mrk:
16201 case VPCOMPRESSQZ128rr:
16202 case VPCOMPRESSQZ128rrk:
16203 case VPCOMPRESSQZ128rrkz:
16204 case VPCOMPRESSQZ256mr:
16205 case VPCOMPRESSQZ256mrk:
16206 case VPCOMPRESSQZ256rr:
16207 case VPCOMPRESSQZ256rrk:
16208 case VPCOMPRESSQZ256rrkz:
16209 case VPCOMPRESSQZmr:
16210 case VPCOMPRESSQZmrk:
16211 case VPCOMPRESSQZrr:
16212 case VPCOMPRESSQZrrk:
16213 case VPCOMPRESSQZrrkz:
16214 return true;
16215 }
16216 return false;
16217}
16218
16219bool isVFMSUBADD132PD(unsigned Opcode) {
16220 switch (Opcode) {
16221 case VFMSUBADD132PDYm:
16222 case VFMSUBADD132PDYr:
16223 case VFMSUBADD132PDZ128m:
16224 case VFMSUBADD132PDZ128mb:
16225 case VFMSUBADD132PDZ128mbk:
16226 case VFMSUBADD132PDZ128mbkz:
16227 case VFMSUBADD132PDZ128mk:
16228 case VFMSUBADD132PDZ128mkz:
16229 case VFMSUBADD132PDZ128r:
16230 case VFMSUBADD132PDZ128rk:
16231 case VFMSUBADD132PDZ128rkz:
16232 case VFMSUBADD132PDZ256m:
16233 case VFMSUBADD132PDZ256mb:
16234 case VFMSUBADD132PDZ256mbk:
16235 case VFMSUBADD132PDZ256mbkz:
16236 case VFMSUBADD132PDZ256mk:
16237 case VFMSUBADD132PDZ256mkz:
16238 case VFMSUBADD132PDZ256r:
16239 case VFMSUBADD132PDZ256rk:
16240 case VFMSUBADD132PDZ256rkz:
16241 case VFMSUBADD132PDZm:
16242 case VFMSUBADD132PDZmb:
16243 case VFMSUBADD132PDZmbk:
16244 case VFMSUBADD132PDZmbkz:
16245 case VFMSUBADD132PDZmk:
16246 case VFMSUBADD132PDZmkz:
16247 case VFMSUBADD132PDZr:
16248 case VFMSUBADD132PDZrb:
16249 case VFMSUBADD132PDZrbk:
16250 case VFMSUBADD132PDZrbkz:
16251 case VFMSUBADD132PDZrk:
16252 case VFMSUBADD132PDZrkz:
16253 case VFMSUBADD132PDm:
16254 case VFMSUBADD132PDr:
16255 return true;
16256 }
16257 return false;
16258}
16259
16260bool isADDSD(unsigned Opcode) {
16261 switch (Opcode) {
16262 case ADDSDrm_Int:
16263 case ADDSDrr_Int:
16264 return true;
16265 }
16266 return false;
16267}
16268
16269bool isBLENDPD(unsigned Opcode) {
16270 switch (Opcode) {
16271 case BLENDPDrmi:
16272 case BLENDPDrri:
16273 return true;
16274 }
16275 return false;
16276}
16277
16278bool isVPERMILPD(unsigned Opcode) {
16279 switch (Opcode) {
16280 case VPERMILPDYmi:
16281 case VPERMILPDYri:
16282 case VPERMILPDYrm:
16283 case VPERMILPDYrr:
16284 case VPERMILPDZ128mbi:
16285 case VPERMILPDZ128mbik:
16286 case VPERMILPDZ128mbikz:
16287 case VPERMILPDZ128mi:
16288 case VPERMILPDZ128mik:
16289 case VPERMILPDZ128mikz:
16290 case VPERMILPDZ128ri:
16291 case VPERMILPDZ128rik:
16292 case VPERMILPDZ128rikz:
16293 case VPERMILPDZ128rm:
16294 case VPERMILPDZ128rmb:
16295 case VPERMILPDZ128rmbk:
16296 case VPERMILPDZ128rmbkz:
16297 case VPERMILPDZ128rmk:
16298 case VPERMILPDZ128rmkz:
16299 case VPERMILPDZ128rr:
16300 case VPERMILPDZ128rrk:
16301 case VPERMILPDZ128rrkz:
16302 case VPERMILPDZ256mbi:
16303 case VPERMILPDZ256mbik:
16304 case VPERMILPDZ256mbikz:
16305 case VPERMILPDZ256mi:
16306 case VPERMILPDZ256mik:
16307 case VPERMILPDZ256mikz:
16308 case VPERMILPDZ256ri:
16309 case VPERMILPDZ256rik:
16310 case VPERMILPDZ256rikz:
16311 case VPERMILPDZ256rm:
16312 case VPERMILPDZ256rmb:
16313 case VPERMILPDZ256rmbk:
16314 case VPERMILPDZ256rmbkz:
16315 case VPERMILPDZ256rmk:
16316 case VPERMILPDZ256rmkz:
16317 case VPERMILPDZ256rr:
16318 case VPERMILPDZ256rrk:
16319 case VPERMILPDZ256rrkz:
16320 case VPERMILPDZmbi:
16321 case VPERMILPDZmbik:
16322 case VPERMILPDZmbikz:
16323 case VPERMILPDZmi:
16324 case VPERMILPDZmik:
16325 case VPERMILPDZmikz:
16326 case VPERMILPDZri:
16327 case VPERMILPDZrik:
16328 case VPERMILPDZrikz:
16329 case VPERMILPDZrm:
16330 case VPERMILPDZrmb:
16331 case VPERMILPDZrmbk:
16332 case VPERMILPDZrmbkz:
16333 case VPERMILPDZrmk:
16334 case VPERMILPDZrmkz:
16335 case VPERMILPDZrr:
16336 case VPERMILPDZrrk:
16337 case VPERMILPDZrrkz:
16338 case VPERMILPDmi:
16339 case VPERMILPDri:
16340 case VPERMILPDrm:
16341 case VPERMILPDrr:
16342 return true;
16343 }
16344 return false;
16345}
16346
16347bool isPMADDUBSW(unsigned Opcode) {
16348 switch (Opcode) {
16349 case MMX_PMADDUBSWrm:
16350 case MMX_PMADDUBSWrr:
16351 case PMADDUBSWrm:
16352 case PMADDUBSWrr:
16353 return true;
16354 }
16355 return false;
16356}
16357
16358bool isPOPFD(unsigned Opcode) {
16359 return Opcode == POPF32;
16360}
16361
16362bool isCMPSW(unsigned Opcode) {
16363 return Opcode == CMPSW;
16364}
16365
16366bool isLDMXCSR(unsigned Opcode) {
16367 return Opcode == LDMXCSR;
16368}
16369
16370bool isVMULPS(unsigned Opcode) {
16371 switch (Opcode) {
16372 case VMULPSYrm:
16373 case VMULPSYrr:
16374 case VMULPSZ128rm:
16375 case VMULPSZ128rmb:
16376 case VMULPSZ128rmbk:
16377 case VMULPSZ128rmbkz:
16378 case VMULPSZ128rmk:
16379 case VMULPSZ128rmkz:
16380 case VMULPSZ128rr:
16381 case VMULPSZ128rrk:
16382 case VMULPSZ128rrkz:
16383 case VMULPSZ256rm:
16384 case VMULPSZ256rmb:
16385 case VMULPSZ256rmbk:
16386 case VMULPSZ256rmbkz:
16387 case VMULPSZ256rmk:
16388 case VMULPSZ256rmkz:
16389 case VMULPSZ256rr:
16390 case VMULPSZ256rrk:
16391 case VMULPSZ256rrkz:
16392 case VMULPSZrm:
16393 case VMULPSZrmb:
16394 case VMULPSZrmbk:
16395 case VMULPSZrmbkz:
16396 case VMULPSZrmk:
16397 case VMULPSZrmkz:
16398 case VMULPSZrr:
16399 case VMULPSZrrb:
16400 case VMULPSZrrbk:
16401 case VMULPSZrrbkz:
16402 case VMULPSZrrk:
16403 case VMULPSZrrkz:
16404 case VMULPSrm:
16405 case VMULPSrr:
16406 return true;
16407 }
16408 return false;
16409}
16410
16411bool isVROUNDSD(unsigned Opcode) {
16412 switch (Opcode) {
16413 case VROUNDSDmi_Int:
16414 case VROUNDSDri_Int:
16415 return true;
16416 }
16417 return false;
16418}
16419
16420bool isVFMADD132PD(unsigned Opcode) {
16421 switch (Opcode) {
16422 case VFMADD132PDYm:
16423 case VFMADD132PDYr:
16424 case VFMADD132PDZ128m:
16425 case VFMADD132PDZ128mb:
16426 case VFMADD132PDZ128mbk:
16427 case VFMADD132PDZ128mbkz:
16428 case VFMADD132PDZ128mk:
16429 case VFMADD132PDZ128mkz:
16430 case VFMADD132PDZ128r:
16431 case VFMADD132PDZ128rk:
16432 case VFMADD132PDZ128rkz:
16433 case VFMADD132PDZ256m:
16434 case VFMADD132PDZ256mb:
16435 case VFMADD132PDZ256mbk:
16436 case VFMADD132PDZ256mbkz:
16437 case VFMADD132PDZ256mk:
16438 case VFMADD132PDZ256mkz:
16439 case VFMADD132PDZ256r:
16440 case VFMADD132PDZ256rk:
16441 case VFMADD132PDZ256rkz:
16442 case VFMADD132PDZm:
16443 case VFMADD132PDZmb:
16444 case VFMADD132PDZmbk:
16445 case VFMADD132PDZmbkz:
16446 case VFMADD132PDZmk:
16447 case VFMADD132PDZmkz:
16448 case VFMADD132PDZr:
16449 case VFMADD132PDZrb:
16450 case VFMADD132PDZrbk:
16451 case VFMADD132PDZrbkz:
16452 case VFMADD132PDZrk:
16453 case VFMADD132PDZrkz:
16454 case VFMADD132PDm:
16455 case VFMADD132PDr:
16456 return true;
16457 }
16458 return false;
16459}
16460
16461bool isVPANDQ(unsigned Opcode) {
16462 switch (Opcode) {
16463 case VPANDQZ128rm:
16464 case VPANDQZ128rmb:
16465 case VPANDQZ128rmbk:
16466 case VPANDQZ128rmbkz:
16467 case VPANDQZ128rmk:
16468 case VPANDQZ128rmkz:
16469 case VPANDQZ128rr:
16470 case VPANDQZ128rrk:
16471 case VPANDQZ128rrkz:
16472 case VPANDQZ256rm:
16473 case VPANDQZ256rmb:
16474 case VPANDQZ256rmbk:
16475 case VPANDQZ256rmbkz:
16476 case VPANDQZ256rmk:
16477 case VPANDQZ256rmkz:
16478 case VPANDQZ256rr:
16479 case VPANDQZ256rrk:
16480 case VPANDQZ256rrkz:
16481 case VPANDQZrm:
16482 case VPANDQZrmb:
16483 case VPANDQZrmbk:
16484 case VPANDQZrmbkz:
16485 case VPANDQZrmk:
16486 case VPANDQZrmkz:
16487 case VPANDQZrr:
16488 case VPANDQZrrk:
16489 case VPANDQZrrkz:
16490 return true;
16491 }
16492 return false;
16493}
16494
16495bool isVPSRAQ(unsigned Opcode) {
16496 switch (Opcode) {
16497 case VPSRAQZ128mbi:
16498 case VPSRAQZ128mbik:
16499 case VPSRAQZ128mbikz:
16500 case VPSRAQZ128mi:
16501 case VPSRAQZ128mik:
16502 case VPSRAQZ128mikz:
16503 case VPSRAQZ128ri:
16504 case VPSRAQZ128rik:
16505 case VPSRAQZ128rikz:
16506 case VPSRAQZ128rm:
16507 case VPSRAQZ128rmk:
16508 case VPSRAQZ128rmkz:
16509 case VPSRAQZ128rr:
16510 case VPSRAQZ128rrk:
16511 case VPSRAQZ128rrkz:
16512 case VPSRAQZ256mbi:
16513 case VPSRAQZ256mbik:
16514 case VPSRAQZ256mbikz:
16515 case VPSRAQZ256mi:
16516 case VPSRAQZ256mik:
16517 case VPSRAQZ256mikz:
16518 case VPSRAQZ256ri:
16519 case VPSRAQZ256rik:
16520 case VPSRAQZ256rikz:
16521 case VPSRAQZ256rm:
16522 case VPSRAQZ256rmk:
16523 case VPSRAQZ256rmkz:
16524 case VPSRAQZ256rr:
16525 case VPSRAQZ256rrk:
16526 case VPSRAQZ256rrkz:
16527 case VPSRAQZmbi:
16528 case VPSRAQZmbik:
16529 case VPSRAQZmbikz:
16530 case VPSRAQZmi:
16531 case VPSRAQZmik:
16532 case VPSRAQZmikz:
16533 case VPSRAQZri:
16534 case VPSRAQZrik:
16535 case VPSRAQZrikz:
16536 case VPSRAQZrm:
16537 case VPSRAQZrmk:
16538 case VPSRAQZrmkz:
16539 case VPSRAQZrr:
16540 case VPSRAQZrrk:
16541 case VPSRAQZrrkz:
16542 return true;
16543 }
16544 return false;
16545}
16546
16547bool isVCOMISD(unsigned Opcode) {
16548 switch (Opcode) {
16549 case VCOMISDZrm:
16550 case VCOMISDZrr:
16551 case VCOMISDZrrb:
16552 case VCOMISDrm:
16553 case VCOMISDrr:
16554 return true;
16555 }
16556 return false;
16557}
16558
16559bool isVCVTBIASPH2BF8(unsigned Opcode) {
16560 switch (Opcode) {
16561 case VCVTBIASPH2BF8Z128rm:
16562 case VCVTBIASPH2BF8Z128rmb:
16563 case VCVTBIASPH2BF8Z128rmbk:
16564 case VCVTBIASPH2BF8Z128rmbkz:
16565 case VCVTBIASPH2BF8Z128rmk:
16566 case VCVTBIASPH2BF8Z128rmkz:
16567 case VCVTBIASPH2BF8Z128rr:
16568 case VCVTBIASPH2BF8Z128rrk:
16569 case VCVTBIASPH2BF8Z128rrkz:
16570 case VCVTBIASPH2BF8Z256rm:
16571 case VCVTBIASPH2BF8Z256rmb:
16572 case VCVTBIASPH2BF8Z256rmbk:
16573 case VCVTBIASPH2BF8Z256rmbkz:
16574 case VCVTBIASPH2BF8Z256rmk:
16575 case VCVTBIASPH2BF8Z256rmkz:
16576 case VCVTBIASPH2BF8Z256rr:
16577 case VCVTBIASPH2BF8Z256rrk:
16578 case VCVTBIASPH2BF8Z256rrkz:
16579 case VCVTBIASPH2BF8Zrm:
16580 case VCVTBIASPH2BF8Zrmb:
16581 case VCVTBIASPH2BF8Zrmbk:
16582 case VCVTBIASPH2BF8Zrmbkz:
16583 case VCVTBIASPH2BF8Zrmk:
16584 case VCVTBIASPH2BF8Zrmkz:
16585 case VCVTBIASPH2BF8Zrr:
16586 case VCVTBIASPH2BF8Zrrk:
16587 case VCVTBIASPH2BF8Zrrkz:
16588 return true;
16589 }
16590 return false;
16591}
16592
16593bool isFFREEP(unsigned Opcode) {
16594 return Opcode == FFREEP;
16595}
16596
16597bool isVFNMADD213PD(unsigned Opcode) {
16598 switch (Opcode) {
16599 case VFNMADD213PDYm:
16600 case VFNMADD213PDYr:
16601 case VFNMADD213PDZ128m:
16602 case VFNMADD213PDZ128mb:
16603 case VFNMADD213PDZ128mbk:
16604 case VFNMADD213PDZ128mbkz:
16605 case VFNMADD213PDZ128mk:
16606 case VFNMADD213PDZ128mkz:
16607 case VFNMADD213PDZ128r:
16608 case VFNMADD213PDZ128rk:
16609 case VFNMADD213PDZ128rkz:
16610 case VFNMADD213PDZ256m:
16611 case VFNMADD213PDZ256mb:
16612 case VFNMADD213PDZ256mbk:
16613 case VFNMADD213PDZ256mbkz:
16614 case VFNMADD213PDZ256mk:
16615 case VFNMADD213PDZ256mkz:
16616 case VFNMADD213PDZ256r:
16617 case VFNMADD213PDZ256rk:
16618 case VFNMADD213PDZ256rkz:
16619 case VFNMADD213PDZm:
16620 case VFNMADD213PDZmb:
16621 case VFNMADD213PDZmbk:
16622 case VFNMADD213PDZmbkz:
16623 case VFNMADD213PDZmk:
16624 case VFNMADD213PDZmkz:
16625 case VFNMADD213PDZr:
16626 case VFNMADD213PDZrb:
16627 case VFNMADD213PDZrbk:
16628 case VFNMADD213PDZrbkz:
16629 case VFNMADD213PDZrk:
16630 case VFNMADD213PDZrkz:
16631 case VFNMADD213PDm:
16632 case VFNMADD213PDr:
16633 return true;
16634 }
16635 return false;
16636}
16637
16638bool isVCMPPD(unsigned Opcode) {
16639 switch (Opcode) {
16640 case VCMPPDYrmi:
16641 case VCMPPDYrri:
16642 case VCMPPDZ128rmbi:
16643 case VCMPPDZ128rmbik:
16644 case VCMPPDZ128rmi:
16645 case VCMPPDZ128rmik:
16646 case VCMPPDZ128rri:
16647 case VCMPPDZ128rrik:
16648 case VCMPPDZ256rmbi:
16649 case VCMPPDZ256rmbik:
16650 case VCMPPDZ256rmi:
16651 case VCMPPDZ256rmik:
16652 case VCMPPDZ256rri:
16653 case VCMPPDZ256rrik:
16654 case VCMPPDZrmbi:
16655 case VCMPPDZrmbik:
16656 case VCMPPDZrmi:
16657 case VCMPPDZrmik:
16658 case VCMPPDZrri:
16659 case VCMPPDZrrib:
16660 case VCMPPDZrribk:
16661 case VCMPPDZrrik:
16662 case VCMPPDrmi:
16663 case VCMPPDrri:
16664 return true;
16665 }
16666 return false;
16667}
16668
16669bool isVFNMSUB132PH(unsigned Opcode) {
16670 switch (Opcode) {
16671 case VFNMSUB132PHZ128m:
16672 case VFNMSUB132PHZ128mb:
16673 case VFNMSUB132PHZ128mbk:
16674 case VFNMSUB132PHZ128mbkz:
16675 case VFNMSUB132PHZ128mk:
16676 case VFNMSUB132PHZ128mkz:
16677 case VFNMSUB132PHZ128r:
16678 case VFNMSUB132PHZ128rk:
16679 case VFNMSUB132PHZ128rkz:
16680 case VFNMSUB132PHZ256m:
16681 case VFNMSUB132PHZ256mb:
16682 case VFNMSUB132PHZ256mbk:
16683 case VFNMSUB132PHZ256mbkz:
16684 case VFNMSUB132PHZ256mk:
16685 case VFNMSUB132PHZ256mkz:
16686 case VFNMSUB132PHZ256r:
16687 case VFNMSUB132PHZ256rk:
16688 case VFNMSUB132PHZ256rkz:
16689 case VFNMSUB132PHZm:
16690 case VFNMSUB132PHZmb:
16691 case VFNMSUB132PHZmbk:
16692 case VFNMSUB132PHZmbkz:
16693 case VFNMSUB132PHZmk:
16694 case VFNMSUB132PHZmkz:
16695 case VFNMSUB132PHZr:
16696 case VFNMSUB132PHZrb:
16697 case VFNMSUB132PHZrbk:
16698 case VFNMSUB132PHZrbkz:
16699 case VFNMSUB132PHZrk:
16700 case VFNMSUB132PHZrkz:
16701 return true;
16702 }
16703 return false;
16704}
16705
16706bool isVPHADDBW(unsigned Opcode) {
16707 switch (Opcode) {
16708 case VPHADDBWrm:
16709 case VPHADDBWrr:
16710 return true;
16711 }
16712 return false;
16713}
16714
16715bool isVPPERM(unsigned Opcode) {
16716 switch (Opcode) {
16717 case VPPERMrmr:
16718 case VPPERMrrm:
16719 case VPPERMrrr:
16720 case VPPERMrrr_REV:
16721 return true;
16722 }
16723 return false;
16724}
16725
16726bool isVCVTPS2PD(unsigned Opcode) {
16727 switch (Opcode) {
16728 case VCVTPS2PDYrm:
16729 case VCVTPS2PDYrr:
16730 case VCVTPS2PDZ128rm:
16731 case VCVTPS2PDZ128rmb:
16732 case VCVTPS2PDZ128rmbk:
16733 case VCVTPS2PDZ128rmbkz:
16734 case VCVTPS2PDZ128rmk:
16735 case VCVTPS2PDZ128rmkz:
16736 case VCVTPS2PDZ128rr:
16737 case VCVTPS2PDZ128rrk:
16738 case VCVTPS2PDZ128rrkz:
16739 case VCVTPS2PDZ256rm:
16740 case VCVTPS2PDZ256rmb:
16741 case VCVTPS2PDZ256rmbk:
16742 case VCVTPS2PDZ256rmbkz:
16743 case VCVTPS2PDZ256rmk:
16744 case VCVTPS2PDZ256rmkz:
16745 case VCVTPS2PDZ256rr:
16746 case VCVTPS2PDZ256rrk:
16747 case VCVTPS2PDZ256rrkz:
16748 case VCVTPS2PDZrm:
16749 case VCVTPS2PDZrmb:
16750 case VCVTPS2PDZrmbk:
16751 case VCVTPS2PDZrmbkz:
16752 case VCVTPS2PDZrmk:
16753 case VCVTPS2PDZrmkz:
16754 case VCVTPS2PDZrr:
16755 case VCVTPS2PDZrrb:
16756 case VCVTPS2PDZrrbk:
16757 case VCVTPS2PDZrrbkz:
16758 case VCVTPS2PDZrrk:
16759 case VCVTPS2PDZrrkz:
16760 case VCVTPS2PDrm:
16761 case VCVTPS2PDrr:
16762 return true;
16763 }
16764 return false;
16765}
16766
16767bool isCBW(unsigned Opcode) {
16768 return Opcode == CBW;
16769}
16770
16771bool isVMOVUPS(unsigned Opcode) {
16772 switch (Opcode) {
16773 case VMOVUPSYmr:
16774 case VMOVUPSYrm:
16775 case VMOVUPSYrr:
16776 case VMOVUPSYrr_REV:
16777 case VMOVUPSZ128mr:
16778 case VMOVUPSZ128mrk:
16779 case VMOVUPSZ128rm:
16780 case VMOVUPSZ128rmk:
16781 case VMOVUPSZ128rmkz:
16782 case VMOVUPSZ128rr:
16783 case VMOVUPSZ128rr_REV:
16784 case VMOVUPSZ128rrk:
16785 case VMOVUPSZ128rrk_REV:
16786 case VMOVUPSZ128rrkz:
16787 case VMOVUPSZ128rrkz_REV:
16788 case VMOVUPSZ256mr:
16789 case VMOVUPSZ256mrk:
16790 case VMOVUPSZ256rm:
16791 case VMOVUPSZ256rmk:
16792 case VMOVUPSZ256rmkz:
16793 case VMOVUPSZ256rr:
16794 case VMOVUPSZ256rr_REV:
16795 case VMOVUPSZ256rrk:
16796 case VMOVUPSZ256rrk_REV:
16797 case VMOVUPSZ256rrkz:
16798 case VMOVUPSZ256rrkz_REV:
16799 case VMOVUPSZmr:
16800 case VMOVUPSZmrk:
16801 case VMOVUPSZrm:
16802 case VMOVUPSZrmk:
16803 case VMOVUPSZrmkz:
16804 case VMOVUPSZrr:
16805 case VMOVUPSZrr_REV:
16806 case VMOVUPSZrrk:
16807 case VMOVUPSZrrk_REV:
16808 case VMOVUPSZrrkz:
16809 case VMOVUPSZrrkz_REV:
16810 case VMOVUPSmr:
16811 case VMOVUPSrm:
16812 case VMOVUPSrr:
16813 case VMOVUPSrr_REV:
16814 return true;
16815 }
16816 return false;
16817}
16818
16819bool isVPMAXUQ(unsigned Opcode) {
16820 switch (Opcode) {
16821 case VPMAXUQZ128rm:
16822 case VPMAXUQZ128rmb:
16823 case VPMAXUQZ128rmbk:
16824 case VPMAXUQZ128rmbkz:
16825 case VPMAXUQZ128rmk:
16826 case VPMAXUQZ128rmkz:
16827 case VPMAXUQZ128rr:
16828 case VPMAXUQZ128rrk:
16829 case VPMAXUQZ128rrkz:
16830 case VPMAXUQZ256rm:
16831 case VPMAXUQZ256rmb:
16832 case VPMAXUQZ256rmbk:
16833 case VPMAXUQZ256rmbkz:
16834 case VPMAXUQZ256rmk:
16835 case VPMAXUQZ256rmkz:
16836 case VPMAXUQZ256rr:
16837 case VPMAXUQZ256rrk:
16838 case VPMAXUQZ256rrkz:
16839 case VPMAXUQZrm:
16840 case VPMAXUQZrmb:
16841 case VPMAXUQZrmbk:
16842 case VPMAXUQZrmbkz:
16843 case VPMAXUQZrmk:
16844 case VPMAXUQZrmkz:
16845 case VPMAXUQZrr:
16846 case VPMAXUQZrrk:
16847 case VPMAXUQZrrkz:
16848 return true;
16849 }
16850 return false;
16851}
16852
16853bool isWRSSQ(unsigned Opcode) {
16854 switch (Opcode) {
16855 case WRSSQ:
16856 case WRSSQ_EVEX:
16857 return true;
16858 }
16859 return false;
16860}
16861
16862bool isPACKUSDW(unsigned Opcode) {
16863 switch (Opcode) {
16864 case PACKUSDWrm:
16865 case PACKUSDWrr:
16866 return true;
16867 }
16868 return false;
16869}
16870
16871bool isVCVTTBF162IBS(unsigned Opcode) {
16872 switch (Opcode) {
16873 case VCVTTBF162IBSZ128rm:
16874 case VCVTTBF162IBSZ128rmb:
16875 case VCVTTBF162IBSZ128rmbk:
16876 case VCVTTBF162IBSZ128rmbkz:
16877 case VCVTTBF162IBSZ128rmk:
16878 case VCVTTBF162IBSZ128rmkz:
16879 case VCVTTBF162IBSZ128rr:
16880 case VCVTTBF162IBSZ128rrk:
16881 case VCVTTBF162IBSZ128rrkz:
16882 case VCVTTBF162IBSZ256rm:
16883 case VCVTTBF162IBSZ256rmb:
16884 case VCVTTBF162IBSZ256rmbk:
16885 case VCVTTBF162IBSZ256rmbkz:
16886 case VCVTTBF162IBSZ256rmk:
16887 case VCVTTBF162IBSZ256rmkz:
16888 case VCVTTBF162IBSZ256rr:
16889 case VCVTTBF162IBSZ256rrk:
16890 case VCVTTBF162IBSZ256rrkz:
16891 case VCVTTBF162IBSZrm:
16892 case VCVTTBF162IBSZrmb:
16893 case VCVTTBF162IBSZrmbk:
16894 case VCVTTBF162IBSZrmbkz:
16895 case VCVTTBF162IBSZrmk:
16896 case VCVTTBF162IBSZrmkz:
16897 case VCVTTBF162IBSZrr:
16898 case VCVTTBF162IBSZrrk:
16899 case VCVTTBF162IBSZrrkz:
16900 return true;
16901 }
16902 return false;
16903}
16904
16905bool isXBEGIN(unsigned Opcode) {
16906 switch (Opcode) {
16907 case XBEGIN_2:
16908 case XBEGIN_4:
16909 return true;
16910 }
16911 return false;
16912}
16913
16914bool isVCVTPD2UQQ(unsigned Opcode) {
16915 switch (Opcode) {
16916 case VCVTPD2UQQZ128rm:
16917 case VCVTPD2UQQZ128rmb:
16918 case VCVTPD2UQQZ128rmbk:
16919 case VCVTPD2UQQZ128rmbkz:
16920 case VCVTPD2UQQZ128rmk:
16921 case VCVTPD2UQQZ128rmkz:
16922 case VCVTPD2UQQZ128rr:
16923 case VCVTPD2UQQZ128rrk:
16924 case VCVTPD2UQQZ128rrkz:
16925 case VCVTPD2UQQZ256rm:
16926 case VCVTPD2UQQZ256rmb:
16927 case VCVTPD2UQQZ256rmbk:
16928 case VCVTPD2UQQZ256rmbkz:
16929 case VCVTPD2UQQZ256rmk:
16930 case VCVTPD2UQQZ256rmkz:
16931 case VCVTPD2UQQZ256rr:
16932 case VCVTPD2UQQZ256rrk:
16933 case VCVTPD2UQQZ256rrkz:
16934 case VCVTPD2UQQZrm:
16935 case VCVTPD2UQQZrmb:
16936 case VCVTPD2UQQZrmbk:
16937 case VCVTPD2UQQZrmbkz:
16938 case VCVTPD2UQQZrmk:
16939 case VCVTPD2UQQZrmkz:
16940 case VCVTPD2UQQZrr:
16941 case VCVTPD2UQQZrrb:
16942 case VCVTPD2UQQZrrbk:
16943 case VCVTPD2UQQZrrbkz:
16944 case VCVTPD2UQQZrrk:
16945 case VCVTPD2UQQZrrkz:
16946 return true;
16947 }
16948 return false;
16949}
16950
16951bool isFCMOVB(unsigned Opcode) {
16952 return Opcode == CMOVB_F;
16953}
16954
16955bool isNOP(unsigned Opcode) {
16956 switch (Opcode) {
16957 case NOOP:
16958 case NOOPL:
16959 case NOOPLr:
16960 case NOOPQ:
16961 case NOOPQr:
16962 case NOOPW:
16963 case NOOPWr:
16964 return true;
16965 }
16966 return false;
16967}
16968
16969bool isVPABSQ(unsigned Opcode) {
16970 switch (Opcode) {
16971 case VPABSQZ128rm:
16972 case VPABSQZ128rmb:
16973 case VPABSQZ128rmbk:
16974 case VPABSQZ128rmbkz:
16975 case VPABSQZ128rmk:
16976 case VPABSQZ128rmkz:
16977 case VPABSQZ128rr:
16978 case VPABSQZ128rrk:
16979 case VPABSQZ128rrkz:
16980 case VPABSQZ256rm:
16981 case VPABSQZ256rmb:
16982 case VPABSQZ256rmbk:
16983 case VPABSQZ256rmbkz:
16984 case VPABSQZ256rmk:
16985 case VPABSQZ256rmkz:
16986 case VPABSQZ256rr:
16987 case VPABSQZ256rrk:
16988 case VPABSQZ256rrkz:
16989 case VPABSQZrm:
16990 case VPABSQZrmb:
16991 case VPABSQZrmbk:
16992 case VPABSQZrmbkz:
16993 case VPABSQZrmk:
16994 case VPABSQZrmkz:
16995 case VPABSQZrr:
16996 case VPABSQZrrk:
16997 case VPABSQZrrkz:
16998 return true;
16999 }
17000 return false;
17001}
17002
17003bool isVTESTPS(unsigned Opcode) {
17004 switch (Opcode) {
17005 case VTESTPSYrm:
17006 case VTESTPSYrr:
17007 case VTESTPSrm:
17008 case VTESTPSrr:
17009 return true;
17010 }
17011 return false;
17012}
17013
17014bool isPHSUBW(unsigned Opcode) {
17015 switch (Opcode) {
17016 case MMX_PHSUBWrm:
17017 case MMX_PHSUBWrr:
17018 case PHSUBWrm:
17019 case PHSUBWrr:
17020 return true;
17021 }
17022 return false;
17023}
17024
17025bool isPUSH2P(unsigned Opcode) {
17026 return Opcode == PUSH2P;
17027}
17028
17029bool isFISTTP(unsigned Opcode) {
17030 switch (Opcode) {
17031 case ISTT_FP16m:
17032 case ISTT_FP32m:
17033 case ISTT_FP64m:
17034 return true;
17035 }
17036 return false;
17037}
17038
17039bool isCFCMOVCC(unsigned Opcode) {
17040 switch (Opcode) {
17041 case CFCMOV16mr:
17042 case CFCMOV16rm:
17043 case CFCMOV16rm_ND:
17044 case CFCMOV16rr:
17045 case CFCMOV16rr_ND:
17046 case CFCMOV16rr_REV:
17047 case CFCMOV32mr:
17048 case CFCMOV32rm:
17049 case CFCMOV32rm_ND:
17050 case CFCMOV32rr:
17051 case CFCMOV32rr_ND:
17052 case CFCMOV32rr_REV:
17053 case CFCMOV64mr:
17054 case CFCMOV64rm:
17055 case CFCMOV64rm_ND:
17056 case CFCMOV64rr:
17057 case CFCMOV64rr_ND:
17058 case CFCMOV64rr_REV:
17059 return true;
17060 }
17061 return false;
17062}
17063
17064bool isVPINSRD(unsigned Opcode) {
17065 switch (Opcode) {
17066 case VPINSRDZrmi:
17067 case VPINSRDZrri:
17068 case VPINSRDrmi:
17069 case VPINSRDrri:
17070 return true;
17071 }
17072 return false;
17073}
17074
17075bool isPCMPESTRM(unsigned Opcode) {
17076 switch (Opcode) {
17077 case PCMPESTRMrmi:
17078 case PCMPESTRMrri:
17079 return true;
17080 }
17081 return false;
17082}
17083
17084bool isVFNMSUB213PS(unsigned Opcode) {
17085 switch (Opcode) {
17086 case VFNMSUB213PSYm:
17087 case VFNMSUB213PSYr:
17088 case VFNMSUB213PSZ128m:
17089 case VFNMSUB213PSZ128mb:
17090 case VFNMSUB213PSZ128mbk:
17091 case VFNMSUB213PSZ128mbkz:
17092 case VFNMSUB213PSZ128mk:
17093 case VFNMSUB213PSZ128mkz:
17094 case VFNMSUB213PSZ128r:
17095 case VFNMSUB213PSZ128rk:
17096 case VFNMSUB213PSZ128rkz:
17097 case VFNMSUB213PSZ256m:
17098 case VFNMSUB213PSZ256mb:
17099 case VFNMSUB213PSZ256mbk:
17100 case VFNMSUB213PSZ256mbkz:
17101 case VFNMSUB213PSZ256mk:
17102 case VFNMSUB213PSZ256mkz:
17103 case VFNMSUB213PSZ256r:
17104 case VFNMSUB213PSZ256rk:
17105 case VFNMSUB213PSZ256rkz:
17106 case VFNMSUB213PSZm:
17107 case VFNMSUB213PSZmb:
17108 case VFNMSUB213PSZmbk:
17109 case VFNMSUB213PSZmbkz:
17110 case VFNMSUB213PSZmk:
17111 case VFNMSUB213PSZmkz:
17112 case VFNMSUB213PSZr:
17113 case VFNMSUB213PSZrb:
17114 case VFNMSUB213PSZrbk:
17115 case VFNMSUB213PSZrbkz:
17116 case VFNMSUB213PSZrk:
17117 case VFNMSUB213PSZrkz:
17118 case VFNMSUB213PSm:
17119 case VFNMSUB213PSr:
17120 return true;
17121 }
17122 return false;
17123}
17124
17125bool isPHSUBD(unsigned Opcode) {
17126 switch (Opcode) {
17127 case MMX_PHSUBDrm:
17128 case MMX_PHSUBDrr:
17129 case PHSUBDrm:
17130 case PHSUBDrr:
17131 return true;
17132 }
17133 return false;
17134}
17135
17136bool isVCVTTPD2DQS(unsigned Opcode) {
17137 switch (Opcode) {
17138 case VCVTTPD2DQSZ128rm:
17139 case VCVTTPD2DQSZ128rmb:
17140 case VCVTTPD2DQSZ128rmbk:
17141 case VCVTTPD2DQSZ128rmbkz:
17142 case VCVTTPD2DQSZ128rmk:
17143 case VCVTTPD2DQSZ128rmkz:
17144 case VCVTTPD2DQSZ128rr:
17145 case VCVTTPD2DQSZ128rrk:
17146 case VCVTTPD2DQSZ128rrkz:
17147 case VCVTTPD2DQSZ256rm:
17148 case VCVTTPD2DQSZ256rmb:
17149 case VCVTTPD2DQSZ256rmbk:
17150 case VCVTTPD2DQSZ256rmbkz:
17151 case VCVTTPD2DQSZ256rmk:
17152 case VCVTTPD2DQSZ256rmkz:
17153 case VCVTTPD2DQSZ256rr:
17154 case VCVTTPD2DQSZ256rrb:
17155 case VCVTTPD2DQSZ256rrbk:
17156 case VCVTTPD2DQSZ256rrbkz:
17157 case VCVTTPD2DQSZ256rrk:
17158 case VCVTTPD2DQSZ256rrkz:
17159 case VCVTTPD2DQSZrm:
17160 case VCVTTPD2DQSZrmb:
17161 case VCVTTPD2DQSZrmbk:
17162 case VCVTTPD2DQSZrmbkz:
17163 case VCVTTPD2DQSZrmk:
17164 case VCVTTPD2DQSZrmkz:
17165 case VCVTTPD2DQSZrr:
17166 case VCVTTPD2DQSZrrb:
17167 case VCVTTPD2DQSZrrbk:
17168 case VCVTTPD2DQSZrrbkz:
17169 case VCVTTPD2DQSZrrk:
17170 case VCVTTPD2DQSZrrkz:
17171 return true;
17172 }
17173 return false;
17174}
17175
17176bool isSLDT(unsigned Opcode) {
17177 switch (Opcode) {
17178 case SLDT16m:
17179 case SLDT16r:
17180 case SLDT32r:
17181 case SLDT64r:
17182 return true;
17183 }
17184 return false;
17185}
17186
17187bool isVHADDPS(unsigned Opcode) {
17188 switch (Opcode) {
17189 case VHADDPSYrm:
17190 case VHADDPSYrr:
17191 case VHADDPSrm:
17192 case VHADDPSrr:
17193 return true;
17194 }
17195 return false;
17196}
17197
17198bool isVMOVNTDQ(unsigned Opcode) {
17199 switch (Opcode) {
17200 case VMOVNTDQYmr:
17201 case VMOVNTDQZ128mr:
17202 case VMOVNTDQZ256mr:
17203 case VMOVNTDQZmr:
17204 case VMOVNTDQmr:
17205 return true;
17206 }
17207 return false;
17208}
17209
17210bool isVPMINSD(unsigned Opcode) {
17211 switch (Opcode) {
17212 case VPMINSDYrm:
17213 case VPMINSDYrr:
17214 case VPMINSDZ128rm:
17215 case VPMINSDZ128rmb:
17216 case VPMINSDZ128rmbk:
17217 case VPMINSDZ128rmbkz:
17218 case VPMINSDZ128rmk:
17219 case VPMINSDZ128rmkz:
17220 case VPMINSDZ128rr:
17221 case VPMINSDZ128rrk:
17222 case VPMINSDZ128rrkz:
17223 case VPMINSDZ256rm:
17224 case VPMINSDZ256rmb:
17225 case VPMINSDZ256rmbk:
17226 case VPMINSDZ256rmbkz:
17227 case VPMINSDZ256rmk:
17228 case VPMINSDZ256rmkz:
17229 case VPMINSDZ256rr:
17230 case VPMINSDZ256rrk:
17231 case VPMINSDZ256rrkz:
17232 case VPMINSDZrm:
17233 case VPMINSDZrmb:
17234 case VPMINSDZrmbk:
17235 case VPMINSDZrmbkz:
17236 case VPMINSDZrmk:
17237 case VPMINSDZrmkz:
17238 case VPMINSDZrr:
17239 case VPMINSDZrrk:
17240 case VPMINSDZrrkz:
17241 case VPMINSDrm:
17242 case VPMINSDrr:
17243 return true;
17244 }
17245 return false;
17246}
17247
17248bool isVFRCZSD(unsigned Opcode) {
17249 switch (Opcode) {
17250 case VFRCZSDrm:
17251 case VFRCZSDrr:
17252 return true;
17253 }
17254 return false;
17255}
17256
17257bool isVPTESTMW(unsigned Opcode) {
17258 switch (Opcode) {
17259 case VPTESTMWZ128rm:
17260 case VPTESTMWZ128rmk:
17261 case VPTESTMWZ128rr:
17262 case VPTESTMWZ128rrk:
17263 case VPTESTMWZ256rm:
17264 case VPTESTMWZ256rmk:
17265 case VPTESTMWZ256rr:
17266 case VPTESTMWZ256rrk:
17267 case VPTESTMWZrm:
17268 case VPTESTMWZrmk:
17269 case VPTESTMWZrr:
17270 case VPTESTMWZrrk:
17271 return true;
17272 }
17273 return false;
17274}
17275
17276bool isVPMOVZXWD(unsigned Opcode) {
17277 switch (Opcode) {
17278 case VPMOVZXWDYrm:
17279 case VPMOVZXWDYrr:
17280 case VPMOVZXWDZ128rm:
17281 case VPMOVZXWDZ128rmk:
17282 case VPMOVZXWDZ128rmkz:
17283 case VPMOVZXWDZ128rr:
17284 case VPMOVZXWDZ128rrk:
17285 case VPMOVZXWDZ128rrkz:
17286 case VPMOVZXWDZ256rm:
17287 case VPMOVZXWDZ256rmk:
17288 case VPMOVZXWDZ256rmkz:
17289 case VPMOVZXWDZ256rr:
17290 case VPMOVZXWDZ256rrk:
17291 case VPMOVZXWDZ256rrkz:
17292 case VPMOVZXWDZrm:
17293 case VPMOVZXWDZrmk:
17294 case VPMOVZXWDZrmkz:
17295 case VPMOVZXWDZrr:
17296 case VPMOVZXWDZrrk:
17297 case VPMOVZXWDZrrkz:
17298 case VPMOVZXWDrm:
17299 case VPMOVZXWDrr:
17300 return true;
17301 }
17302 return false;
17303}
17304
17305bool isPSADBW(unsigned Opcode) {
17306 switch (Opcode) {
17307 case MMX_PSADBWrm:
17308 case MMX_PSADBWrr:
17309 case PSADBWrm:
17310 case PSADBWrr:
17311 return true;
17312 }
17313 return false;
17314}
17315
17316bool isVCVTSD2SI(unsigned Opcode) {
17317 switch (Opcode) {
17318 case VCVTSD2SI64Zrm_Int:
17319 case VCVTSD2SI64Zrr_Int:
17320 case VCVTSD2SI64Zrrb_Int:
17321 case VCVTSD2SI64rm_Int:
17322 case VCVTSD2SI64rr_Int:
17323 case VCVTSD2SIZrm_Int:
17324 case VCVTSD2SIZrr_Int:
17325 case VCVTSD2SIZrrb_Int:
17326 case VCVTSD2SIrm_Int:
17327 case VCVTSD2SIrr_Int:
17328 return true;
17329 }
17330 return false;
17331}
17332
17333bool isVMAXPH(unsigned Opcode) {
17334 switch (Opcode) {
17335 case VMAXPHZ128rm:
17336 case VMAXPHZ128rmb:
17337 case VMAXPHZ128rmbk:
17338 case VMAXPHZ128rmbkz:
17339 case VMAXPHZ128rmk:
17340 case VMAXPHZ128rmkz:
17341 case VMAXPHZ128rr:
17342 case VMAXPHZ128rrk:
17343 case VMAXPHZ128rrkz:
17344 case VMAXPHZ256rm:
17345 case VMAXPHZ256rmb:
17346 case VMAXPHZ256rmbk:
17347 case VMAXPHZ256rmbkz:
17348 case VMAXPHZ256rmk:
17349 case VMAXPHZ256rmkz:
17350 case VMAXPHZ256rr:
17351 case VMAXPHZ256rrk:
17352 case VMAXPHZ256rrkz:
17353 case VMAXPHZrm:
17354 case VMAXPHZrmb:
17355 case VMAXPHZrmbk:
17356 case VMAXPHZrmbkz:
17357 case VMAXPHZrmk:
17358 case VMAXPHZrmkz:
17359 case VMAXPHZrr:
17360 case VMAXPHZrrb:
17361 case VMAXPHZrrbk:
17362 case VMAXPHZrrbkz:
17363 case VMAXPHZrrk:
17364 case VMAXPHZrrkz:
17365 return true;
17366 }
17367 return false;
17368}
17369
17370bool isLODSB(unsigned Opcode) {
17371 return Opcode == LODSB;
17372}
17373
17374bool isPHMINPOSUW(unsigned Opcode) {
17375 switch (Opcode) {
17376 case PHMINPOSUWrm:
17377 case PHMINPOSUWrr:
17378 return true;
17379 }
17380 return false;
17381}
17382
17383bool isVPROLVD(unsigned Opcode) {
17384 switch (Opcode) {
17385 case VPROLVDZ128rm:
17386 case VPROLVDZ128rmb:
17387 case VPROLVDZ128rmbk:
17388 case VPROLVDZ128rmbkz:
17389 case VPROLVDZ128rmk:
17390 case VPROLVDZ128rmkz:
17391 case VPROLVDZ128rr:
17392 case VPROLVDZ128rrk:
17393 case VPROLVDZ128rrkz:
17394 case VPROLVDZ256rm:
17395 case VPROLVDZ256rmb:
17396 case VPROLVDZ256rmbk:
17397 case VPROLVDZ256rmbkz:
17398 case VPROLVDZ256rmk:
17399 case VPROLVDZ256rmkz:
17400 case VPROLVDZ256rr:
17401 case VPROLVDZ256rrk:
17402 case VPROLVDZ256rrkz:
17403 case VPROLVDZrm:
17404 case VPROLVDZrmb:
17405 case VPROLVDZrmbk:
17406 case VPROLVDZrmbkz:
17407 case VPROLVDZrmk:
17408 case VPROLVDZrmkz:
17409 case VPROLVDZrr:
17410 case VPROLVDZrrk:
17411 case VPROLVDZrrkz:
17412 return true;
17413 }
17414 return false;
17415}
17416
17417bool isWRFSBASE(unsigned Opcode) {
17418 switch (Opcode) {
17419 case WRFSBASE:
17420 case WRFSBASE64:
17421 return true;
17422 }
17423 return false;
17424}
17425
17426bool isVRSQRT14PS(unsigned Opcode) {
17427 switch (Opcode) {
17428 case VRSQRT14PSZ128m:
17429 case VRSQRT14PSZ128mb:
17430 case VRSQRT14PSZ128mbk:
17431 case VRSQRT14PSZ128mbkz:
17432 case VRSQRT14PSZ128mk:
17433 case VRSQRT14PSZ128mkz:
17434 case VRSQRT14PSZ128r:
17435 case VRSQRT14PSZ128rk:
17436 case VRSQRT14PSZ128rkz:
17437 case VRSQRT14PSZ256m:
17438 case VRSQRT14PSZ256mb:
17439 case VRSQRT14PSZ256mbk:
17440 case VRSQRT14PSZ256mbkz:
17441 case VRSQRT14PSZ256mk:
17442 case VRSQRT14PSZ256mkz:
17443 case VRSQRT14PSZ256r:
17444 case VRSQRT14PSZ256rk:
17445 case VRSQRT14PSZ256rkz:
17446 case VRSQRT14PSZm:
17447 case VRSQRT14PSZmb:
17448 case VRSQRT14PSZmbk:
17449 case VRSQRT14PSZmbkz:
17450 case VRSQRT14PSZmk:
17451 case VRSQRT14PSZmkz:
17452 case VRSQRT14PSZr:
17453 case VRSQRT14PSZrk:
17454 case VRSQRT14PSZrkz:
17455 return true;
17456 }
17457 return false;
17458}
17459
17460bool isVPHSUBDQ(unsigned Opcode) {
17461 switch (Opcode) {
17462 case VPHSUBDQrm:
17463 case VPHSUBDQrr:
17464 return true;
17465 }
17466 return false;
17467}
17468
17469bool isIRETD(unsigned Opcode) {
17470 return Opcode == IRET32;
17471}
17472
17473bool isVMOVRSD(unsigned Opcode) {
17474 switch (Opcode) {
17475 case VMOVRSDZ128m:
17476 case VMOVRSDZ128mk:
17477 case VMOVRSDZ128mkz:
17478 case VMOVRSDZ256m:
17479 case VMOVRSDZ256mk:
17480 case VMOVRSDZ256mkz:
17481 case VMOVRSDZm:
17482 case VMOVRSDZmk:
17483 case VMOVRSDZmkz:
17484 return true;
17485 }
17486 return false;
17487}
17488
17489bool isCVTSI2SS(unsigned Opcode) {
17490 switch (Opcode) {
17491 case CVTSI2SSrm_Int:
17492 case CVTSI2SSrr_Int:
17493 case CVTSI642SSrm_Int:
17494 case CVTSI642SSrr_Int:
17495 return true;
17496 }
17497 return false;
17498}
17499
17500bool isVPMULHRSW(unsigned Opcode) {
17501 switch (Opcode) {
17502 case VPMULHRSWYrm:
17503 case VPMULHRSWYrr:
17504 case VPMULHRSWZ128rm:
17505 case VPMULHRSWZ128rmk:
17506 case VPMULHRSWZ128rmkz:
17507 case VPMULHRSWZ128rr:
17508 case VPMULHRSWZ128rrk:
17509 case VPMULHRSWZ128rrkz:
17510 case VPMULHRSWZ256rm:
17511 case VPMULHRSWZ256rmk:
17512 case VPMULHRSWZ256rmkz:
17513 case VPMULHRSWZ256rr:
17514 case VPMULHRSWZ256rrk:
17515 case VPMULHRSWZ256rrkz:
17516 case VPMULHRSWZrm:
17517 case VPMULHRSWZrmk:
17518 case VPMULHRSWZrmkz:
17519 case VPMULHRSWZrr:
17520 case VPMULHRSWZrrk:
17521 case VPMULHRSWZrrkz:
17522 case VPMULHRSWrm:
17523 case VPMULHRSWrr:
17524 return true;
17525 }
17526 return false;
17527}
17528
17529bool isPI2FD(unsigned Opcode) {
17530 switch (Opcode) {
17531 case PI2FDrm:
17532 case PI2FDrr:
17533 return true;
17534 }
17535 return false;
17536}
17537
17538bool isGF2P8AFFINEQB(unsigned Opcode) {
17539 switch (Opcode) {
17540 case GF2P8AFFINEQBrmi:
17541 case GF2P8AFFINEQBrri:
17542 return true;
17543 }
17544 return false;
17545}
17546
17547bool isPAND(unsigned Opcode) {
17548 switch (Opcode) {
17549 case MMX_PANDrm:
17550 case MMX_PANDrr:
17551 case PANDrm:
17552 case PANDrr:
17553 return true;
17554 }
17555 return false;
17556}
17557
17558bool isVFNMSUB231SH(unsigned Opcode) {
17559 switch (Opcode) {
17560 case VFNMSUB231SHZm_Int:
17561 case VFNMSUB231SHZmk_Int:
17562 case VFNMSUB231SHZmkz_Int:
17563 case VFNMSUB231SHZr_Int:
17564 case VFNMSUB231SHZrb_Int:
17565 case VFNMSUB231SHZrbk_Int:
17566 case VFNMSUB231SHZrbkz_Int:
17567 case VFNMSUB231SHZrk_Int:
17568 case VFNMSUB231SHZrkz_Int:
17569 return true;
17570 }
17571 return false;
17572}
17573
17574bool isVCVTPH2BF8(unsigned Opcode) {
17575 switch (Opcode) {
17576 case VCVTPH2BF8Z128rm:
17577 case VCVTPH2BF8Z128rmb:
17578 case VCVTPH2BF8Z128rmbk:
17579 case VCVTPH2BF8Z128rmbkz:
17580 case VCVTPH2BF8Z128rmk:
17581 case VCVTPH2BF8Z128rmkz:
17582 case VCVTPH2BF8Z128rr:
17583 case VCVTPH2BF8Z128rrk:
17584 case VCVTPH2BF8Z128rrkz:
17585 case VCVTPH2BF8Z256rm:
17586 case VCVTPH2BF8Z256rmb:
17587 case VCVTPH2BF8Z256rmbk:
17588 case VCVTPH2BF8Z256rmbkz:
17589 case VCVTPH2BF8Z256rmk:
17590 case VCVTPH2BF8Z256rmkz:
17591 case VCVTPH2BF8Z256rr:
17592 case VCVTPH2BF8Z256rrk:
17593 case VCVTPH2BF8Z256rrkz:
17594 case VCVTPH2BF8Zrm:
17595 case VCVTPH2BF8Zrmb:
17596 case VCVTPH2BF8Zrmbk:
17597 case VCVTPH2BF8Zrmbkz:
17598 case VCVTPH2BF8Zrmk:
17599 case VCVTPH2BF8Zrmkz:
17600 case VCVTPH2BF8Zrr:
17601 case VCVTPH2BF8Zrrk:
17602 case VCVTPH2BF8Zrrkz:
17603 return true;
17604 }
17605 return false;
17606}
17607
17608bool isVMOVHLPS(unsigned Opcode) {
17609 switch (Opcode) {
17610 case VMOVHLPSZrr:
17611 case VMOVHLPSrr:
17612 return true;
17613 }
17614 return false;
17615}
17616
17617bool isPEXTRB(unsigned Opcode) {
17618 switch (Opcode) {
17619 case PEXTRBmri:
17620 case PEXTRBrri:
17621 return true;
17622 }
17623 return false;
17624}
17625
17626bool isVMMCALL(unsigned Opcode) {
17627 return Opcode == VMMCALL;
17628}
17629
17630bool isKNOTD(unsigned Opcode) {
17631 return Opcode == KNOTDkk;
17632}
17633
17634bool isVCVTSH2SS(unsigned Opcode) {
17635 switch (Opcode) {
17636 case VCVTSH2SSZrm_Int:
17637 case VCVTSH2SSZrmk_Int:
17638 case VCVTSH2SSZrmkz_Int:
17639 case VCVTSH2SSZrr_Int:
17640 case VCVTSH2SSZrrb_Int:
17641 case VCVTSH2SSZrrbk_Int:
17642 case VCVTSH2SSZrrbkz_Int:
17643 case VCVTSH2SSZrrk_Int:
17644 case VCVTSH2SSZrrkz_Int:
17645 return true;
17646 }
17647 return false;
17648}
17649
17650bool isVPUNPCKLQDQ(unsigned Opcode) {
17651 switch (Opcode) {
17652 case VPUNPCKLQDQYrm:
17653 case VPUNPCKLQDQYrr:
17654 case VPUNPCKLQDQZ128rm:
17655 case VPUNPCKLQDQZ128rmb:
17656 case VPUNPCKLQDQZ128rmbk:
17657 case VPUNPCKLQDQZ128rmbkz:
17658 case VPUNPCKLQDQZ128rmk:
17659 case VPUNPCKLQDQZ128rmkz:
17660 case VPUNPCKLQDQZ128rr:
17661 case VPUNPCKLQDQZ128rrk:
17662 case VPUNPCKLQDQZ128rrkz:
17663 case VPUNPCKLQDQZ256rm:
17664 case VPUNPCKLQDQZ256rmb:
17665 case VPUNPCKLQDQZ256rmbk:
17666 case VPUNPCKLQDQZ256rmbkz:
17667 case VPUNPCKLQDQZ256rmk:
17668 case VPUNPCKLQDQZ256rmkz:
17669 case VPUNPCKLQDQZ256rr:
17670 case VPUNPCKLQDQZ256rrk:
17671 case VPUNPCKLQDQZ256rrkz:
17672 case VPUNPCKLQDQZrm:
17673 case VPUNPCKLQDQZrmb:
17674 case VPUNPCKLQDQZrmbk:
17675 case VPUNPCKLQDQZrmbkz:
17676 case VPUNPCKLQDQZrmk:
17677 case VPUNPCKLQDQZrmkz:
17678 case VPUNPCKLQDQZrr:
17679 case VPUNPCKLQDQZrrk:
17680 case VPUNPCKLQDQZrrkz:
17681 case VPUNPCKLQDQrm:
17682 case VPUNPCKLQDQrr:
17683 return true;
17684 }
17685 return false;
17686}
17687
17688bool isVPERMIL2PS(unsigned Opcode) {
17689 switch (Opcode) {
17690 case VPERMIL2PSYmr:
17691 case VPERMIL2PSYrm:
17692 case VPERMIL2PSYrr:
17693 case VPERMIL2PSYrr_REV:
17694 case VPERMIL2PSmr:
17695 case VPERMIL2PSrm:
17696 case VPERMIL2PSrr:
17697 case VPERMIL2PSrr_REV:
17698 return true;
17699 }
17700 return false;
17701}
17702
17703bool isVPCMPGTD(unsigned Opcode) {
17704 switch (Opcode) {
17705 case VPCMPGTDYrm:
17706 case VPCMPGTDYrr:
17707 case VPCMPGTDZ128rm:
17708 case VPCMPGTDZ128rmb:
17709 case VPCMPGTDZ128rmbk:
17710 case VPCMPGTDZ128rmk:
17711 case VPCMPGTDZ128rr:
17712 case VPCMPGTDZ128rrk:
17713 case VPCMPGTDZ256rm:
17714 case VPCMPGTDZ256rmb:
17715 case VPCMPGTDZ256rmbk:
17716 case VPCMPGTDZ256rmk:
17717 case VPCMPGTDZ256rr:
17718 case VPCMPGTDZ256rrk:
17719 case VPCMPGTDZrm:
17720 case VPCMPGTDZrmb:
17721 case VPCMPGTDZrmbk:
17722 case VPCMPGTDZrmk:
17723 case VPCMPGTDZrr:
17724 case VPCMPGTDZrrk:
17725 case VPCMPGTDrm:
17726 case VPCMPGTDrr:
17727 return true;
17728 }
17729 return false;
17730}
17731
17732bool isCMPXCHG16B(unsigned Opcode) {
17733 return Opcode == CMPXCHG16B;
17734}
17735
17736bool isTDPHF8PS(unsigned Opcode) {
17737 return Opcode == TDPHF8PS;
17738}
17739
17740bool isVZEROUPPER(unsigned Opcode) {
17741 return Opcode == VZEROUPPER;
17742}
17743
17744bool isMOVAPS(unsigned Opcode) {
17745 switch (Opcode) {
17746 case MOVAPSmr:
17747 case MOVAPSrm:
17748 case MOVAPSrr:
17749 case MOVAPSrr_REV:
17750 return true;
17751 }
17752 return false;
17753}
17754
17755bool isVPCMPW(unsigned Opcode) {
17756 switch (Opcode) {
17757 case VPCMPWZ128rmi:
17758 case VPCMPWZ128rmik:
17759 case VPCMPWZ128rri:
17760 case VPCMPWZ128rrik:
17761 case VPCMPWZ256rmi:
17762 case VPCMPWZ256rmik:
17763 case VPCMPWZ256rri:
17764 case VPCMPWZ256rrik:
17765 case VPCMPWZrmi:
17766 case VPCMPWZrmik:
17767 case VPCMPWZrri:
17768 case VPCMPWZrrik:
17769 return true;
17770 }
17771 return false;
17772}
17773
17774bool isFUCOMPP(unsigned Opcode) {
17775 return Opcode == UCOM_FPPr;
17776}
17777
17778bool isXSETBV(unsigned Opcode) {
17779 return Opcode == XSETBV;
17780}
17781
17782bool isSLWPCB(unsigned Opcode) {
17783 switch (Opcode) {
17784 case SLWPCB:
17785 case SLWPCB64:
17786 return true;
17787 }
17788 return false;
17789}
17790
17791bool isSCASW(unsigned Opcode) {
17792 return Opcode == SCASW;
17793}
17794
17795bool isFCMOVNE(unsigned Opcode) {
17796 return Opcode == CMOVNE_F;
17797}
17798
17799bool isPBNDKB(unsigned Opcode) {
17800 return Opcode == PBNDKB;
17801}
17802
17803bool isVPMULLD(unsigned Opcode) {
17804 switch (Opcode) {
17805 case VPMULLDYrm:
17806 case VPMULLDYrr:
17807 case VPMULLDZ128rm:
17808 case VPMULLDZ128rmb:
17809 case VPMULLDZ128rmbk:
17810 case VPMULLDZ128rmbkz:
17811 case VPMULLDZ128rmk:
17812 case VPMULLDZ128rmkz:
17813 case VPMULLDZ128rr:
17814 case VPMULLDZ128rrk:
17815 case VPMULLDZ128rrkz:
17816 case VPMULLDZ256rm:
17817 case VPMULLDZ256rmb:
17818 case VPMULLDZ256rmbk:
17819 case VPMULLDZ256rmbkz:
17820 case VPMULLDZ256rmk:
17821 case VPMULLDZ256rmkz:
17822 case VPMULLDZ256rr:
17823 case VPMULLDZ256rrk:
17824 case VPMULLDZ256rrkz:
17825 case VPMULLDZrm:
17826 case VPMULLDZrmb:
17827 case VPMULLDZrmbk:
17828 case VPMULLDZrmbkz:
17829 case VPMULLDZrmk:
17830 case VPMULLDZrmkz:
17831 case VPMULLDZrr:
17832 case VPMULLDZrrk:
17833 case VPMULLDZrrkz:
17834 case VPMULLDrm:
17835 case VPMULLDrr:
17836 return true;
17837 }
17838 return false;
17839}
17840
17841bool isVP4DPWSSDS(unsigned Opcode) {
17842 switch (Opcode) {
17843 case VP4DPWSSDSrm:
17844 case VP4DPWSSDSrmk:
17845 case VP4DPWSSDSrmkz:
17846 return true;
17847 }
17848 return false;
17849}
17850
17851bool isVCVT2PH2HF8(unsigned Opcode) {
17852 switch (Opcode) {
17853 case VCVT2PH2HF8Z128rm:
17854 case VCVT2PH2HF8Z128rmb:
17855 case VCVT2PH2HF8Z128rmbk:
17856 case VCVT2PH2HF8Z128rmbkz:
17857 case VCVT2PH2HF8Z128rmk:
17858 case VCVT2PH2HF8Z128rmkz:
17859 case VCVT2PH2HF8Z128rr:
17860 case VCVT2PH2HF8Z128rrk:
17861 case VCVT2PH2HF8Z128rrkz:
17862 case VCVT2PH2HF8Z256rm:
17863 case VCVT2PH2HF8Z256rmb:
17864 case VCVT2PH2HF8Z256rmbk:
17865 case VCVT2PH2HF8Z256rmbkz:
17866 case VCVT2PH2HF8Z256rmk:
17867 case VCVT2PH2HF8Z256rmkz:
17868 case VCVT2PH2HF8Z256rr:
17869 case VCVT2PH2HF8Z256rrk:
17870 case VCVT2PH2HF8Z256rrkz:
17871 case VCVT2PH2HF8Zrm:
17872 case VCVT2PH2HF8Zrmb:
17873 case VCVT2PH2HF8Zrmbk:
17874 case VCVT2PH2HF8Zrmbkz:
17875 case VCVT2PH2HF8Zrmk:
17876 case VCVT2PH2HF8Zrmkz:
17877 case VCVT2PH2HF8Zrr:
17878 case VCVT2PH2HF8Zrrk:
17879 case VCVT2PH2HF8Zrrkz:
17880 return true;
17881 }
17882 return false;
17883}
17884
17885bool isPINSRW(unsigned Opcode) {
17886 switch (Opcode) {
17887 case MMX_PINSRWrmi:
17888 case MMX_PINSRWrri:
17889 case PINSRWrmi:
17890 case PINSRWrri:
17891 return true;
17892 }
17893 return false;
17894}
17895
17896bool isVCVTSI2SH(unsigned Opcode) {
17897 switch (Opcode) {
17898 case VCVTSI2SHZrm_Int:
17899 case VCVTSI2SHZrr_Int:
17900 case VCVTSI2SHZrrb_Int:
17901 case VCVTSI642SHZrm_Int:
17902 case VCVTSI642SHZrr_Int:
17903 case VCVTSI642SHZrrb_Int:
17904 return true;
17905 }
17906 return false;
17907}
17908
17909bool isVINSERTF32X8(unsigned Opcode) {
17910 switch (Opcode) {
17911 case VINSERTF32X8Zrmi:
17912 case VINSERTF32X8Zrmik:
17913 case VINSERTF32X8Zrmikz:
17914 case VINSERTF32X8Zrri:
17915 case VINSERTF32X8Zrrik:
17916 case VINSERTF32X8Zrrikz:
17917 return true;
17918 }
17919 return false;
17920}
17921
17922bool isKSHIFTLB(unsigned Opcode) {
17923 return Opcode == KSHIFTLBki;
17924}
17925
17926bool isSEAMOPS(unsigned Opcode) {
17927 return Opcode == SEAMOPS;
17928}
17929
17930bool isVPMULUDQ(unsigned Opcode) {
17931 switch (Opcode) {
17932 case VPMULUDQYrm:
17933 case VPMULUDQYrr:
17934 case VPMULUDQZ128rm:
17935 case VPMULUDQZ128rmb:
17936 case VPMULUDQZ128rmbk:
17937 case VPMULUDQZ128rmbkz:
17938 case VPMULUDQZ128rmk:
17939 case VPMULUDQZ128rmkz:
17940 case VPMULUDQZ128rr:
17941 case VPMULUDQZ128rrk:
17942 case VPMULUDQZ128rrkz:
17943 case VPMULUDQZ256rm:
17944 case VPMULUDQZ256rmb:
17945 case VPMULUDQZ256rmbk:
17946 case VPMULUDQZ256rmbkz:
17947 case VPMULUDQZ256rmk:
17948 case VPMULUDQZ256rmkz:
17949 case VPMULUDQZ256rr:
17950 case VPMULUDQZ256rrk:
17951 case VPMULUDQZ256rrkz:
17952 case VPMULUDQZrm:
17953 case VPMULUDQZrmb:
17954 case VPMULUDQZrmbk:
17955 case VPMULUDQZrmbkz:
17956 case VPMULUDQZrmk:
17957 case VPMULUDQZrmkz:
17958 case VPMULUDQZrr:
17959 case VPMULUDQZrrk:
17960 case VPMULUDQZrrkz:
17961 case VPMULUDQrm:
17962 case VPMULUDQrr:
17963 return true;
17964 }
17965 return false;
17966}
17967
17968bool isVPMOVSQB(unsigned Opcode) {
17969 switch (Opcode) {
17970 case VPMOVSQBZ128mr:
17971 case VPMOVSQBZ128mrk:
17972 case VPMOVSQBZ128rr:
17973 case VPMOVSQBZ128rrk:
17974 case VPMOVSQBZ128rrkz:
17975 case VPMOVSQBZ256mr:
17976 case VPMOVSQBZ256mrk:
17977 case VPMOVSQBZ256rr:
17978 case VPMOVSQBZ256rrk:
17979 case VPMOVSQBZ256rrkz:
17980 case VPMOVSQBZmr:
17981 case VPMOVSQBZmrk:
17982 case VPMOVSQBZrr:
17983 case VPMOVSQBZrrk:
17984 case VPMOVSQBZrrkz:
17985 return true;
17986 }
17987 return false;
17988}
17989
17990bool isVPTESTMD(unsigned Opcode) {
17991 switch (Opcode) {
17992 case VPTESTMDZ128rm:
17993 case VPTESTMDZ128rmb:
17994 case VPTESTMDZ128rmbk:
17995 case VPTESTMDZ128rmk:
17996 case VPTESTMDZ128rr:
17997 case VPTESTMDZ128rrk:
17998 case VPTESTMDZ256rm:
17999 case VPTESTMDZ256rmb:
18000 case VPTESTMDZ256rmbk:
18001 case VPTESTMDZ256rmk:
18002 case VPTESTMDZ256rr:
18003 case VPTESTMDZ256rrk:
18004 case VPTESTMDZrm:
18005 case VPTESTMDZrmb:
18006 case VPTESTMDZrmbk:
18007 case VPTESTMDZrmk:
18008 case VPTESTMDZrr:
18009 case VPTESTMDZrrk:
18010 return true;
18011 }
18012 return false;
18013}
18014
18015bool isVPHADDDQ(unsigned Opcode) {
18016 switch (Opcode) {
18017 case VPHADDDQrm:
18018 case VPHADDDQrr:
18019 return true;
18020 }
18021 return false;
18022}
18023
18024bool isKUNPCKDQ(unsigned Opcode) {
18025 return Opcode == KUNPCKDQkk;
18026}
18027
18028bool isT1MSKC(unsigned Opcode) {
18029 switch (Opcode) {
18030 case T1MSKC32rm:
18031 case T1MSKC32rr:
18032 case T1MSKC64rm:
18033 case T1MSKC64rr:
18034 return true;
18035 }
18036 return false;
18037}
18038
18039bool isVPCOMB(unsigned Opcode) {
18040 switch (Opcode) {
18041 case VPCOMBmi:
18042 case VPCOMBri:
18043 return true;
18044 }
18045 return false;
18046}
18047
18048bool isVBLENDPS(unsigned Opcode) {
18049 switch (Opcode) {
18050 case VBLENDPSYrmi:
18051 case VBLENDPSYrri:
18052 case VBLENDPSrmi:
18053 case VBLENDPSrri:
18054 return true;
18055 }
18056 return false;
18057}
18058
18059bool isPTWRITE(unsigned Opcode) {
18060 switch (Opcode) {
18061 case PTWRITE64m:
18062 case PTWRITE64r:
18063 case PTWRITEm:
18064 case PTWRITEr:
18065 return true;
18066 }
18067 return false;
18068}
18069
18070bool isVCVTPH2BF8S(unsigned Opcode) {
18071 switch (Opcode) {
18072 case VCVTPH2BF8SZ128rm:
18073 case VCVTPH2BF8SZ128rmb:
18074 case VCVTPH2BF8SZ128rmbk:
18075 case VCVTPH2BF8SZ128rmbkz:
18076 case VCVTPH2BF8SZ128rmk:
18077 case VCVTPH2BF8SZ128rmkz:
18078 case VCVTPH2BF8SZ128rr:
18079 case VCVTPH2BF8SZ128rrk:
18080 case VCVTPH2BF8SZ128rrkz:
18081 case VCVTPH2BF8SZ256rm:
18082 case VCVTPH2BF8SZ256rmb:
18083 case VCVTPH2BF8SZ256rmbk:
18084 case VCVTPH2BF8SZ256rmbkz:
18085 case VCVTPH2BF8SZ256rmk:
18086 case VCVTPH2BF8SZ256rmkz:
18087 case VCVTPH2BF8SZ256rr:
18088 case VCVTPH2BF8SZ256rrk:
18089 case VCVTPH2BF8SZ256rrkz:
18090 case VCVTPH2BF8SZrm:
18091 case VCVTPH2BF8SZrmb:
18092 case VCVTPH2BF8SZrmbk:
18093 case VCVTPH2BF8SZrmbkz:
18094 case VCVTPH2BF8SZrmk:
18095 case VCVTPH2BF8SZrmkz:
18096 case VCVTPH2BF8SZrr:
18097 case VCVTPH2BF8SZrrk:
18098 case VCVTPH2BF8SZrrkz:
18099 return true;
18100 }
18101 return false;
18102}
18103
18104bool isCVTPS2PI(unsigned Opcode) {
18105 switch (Opcode) {
18106 case MMX_CVTPS2PIrm:
18107 case MMX_CVTPS2PIrr:
18108 return true;
18109 }
18110 return false;
18111}
18112
18113bool isVPROTD(unsigned Opcode) {
18114 switch (Opcode) {
18115 case VPROTDmi:
18116 case VPROTDmr:
18117 case VPROTDri:
18118 case VPROTDrm:
18119 case VPROTDrr:
18120 case VPROTDrr_REV:
18121 return true;
18122 }
18123 return false;
18124}
18125
18126bool isCALL(unsigned Opcode) {
18127 switch (Opcode) {
18128 case CALL16m:
18129 case CALL16r:
18130 case CALL32m:
18131 case CALL32r:
18132 case CALL64m:
18133 case CALL64pcrel32:
18134 case CALL64r:
18135 case CALLpcrel16:
18136 case CALLpcrel32:
18137 case FARCALL32m:
18138 return true;
18139 }
18140 return false;
18141}
18142
18143bool isTILELOADDRST1(unsigned Opcode) {
18144 switch (Opcode) {
18145 case TILELOADDRST1:
18146 case TILELOADDRST1_EVEX:
18147 return true;
18148 }
18149 return false;
18150}
18151
18152bool isVPERMPS(unsigned Opcode) {
18153 switch (Opcode) {
18154 case VPERMPSYrm:
18155 case VPERMPSYrr:
18156 case VPERMPSZ256rm:
18157 case VPERMPSZ256rmb:
18158 case VPERMPSZ256rmbk:
18159 case VPERMPSZ256rmbkz:
18160 case VPERMPSZ256rmk:
18161 case VPERMPSZ256rmkz:
18162 case VPERMPSZ256rr:
18163 case VPERMPSZ256rrk:
18164 case VPERMPSZ256rrkz:
18165 case VPERMPSZrm:
18166 case VPERMPSZrmb:
18167 case VPERMPSZrmbk:
18168 case VPERMPSZrmbkz:
18169 case VPERMPSZrmk:
18170 case VPERMPSZrmkz:
18171 case VPERMPSZrr:
18172 case VPERMPSZrrk:
18173 case VPERMPSZrrkz:
18174 return true;
18175 }
18176 return false;
18177}
18178
18179bool isVPSHUFBITQMB(unsigned Opcode) {
18180 switch (Opcode) {
18181 case VPSHUFBITQMBZ128rm:
18182 case VPSHUFBITQMBZ128rmk:
18183 case VPSHUFBITQMBZ128rr:
18184 case VPSHUFBITQMBZ128rrk:
18185 case VPSHUFBITQMBZ256rm:
18186 case VPSHUFBITQMBZ256rmk:
18187 case VPSHUFBITQMBZ256rr:
18188 case VPSHUFBITQMBZ256rrk:
18189 case VPSHUFBITQMBZrm:
18190 case VPSHUFBITQMBZrmk:
18191 case VPSHUFBITQMBZrr:
18192 case VPSHUFBITQMBZrrk:
18193 return true;
18194 }
18195 return false;
18196}
18197
18198bool isVMOVSLDUP(unsigned Opcode) {
18199 switch (Opcode) {
18200 case VMOVSLDUPYrm:
18201 case VMOVSLDUPYrr:
18202 case VMOVSLDUPZ128rm:
18203 case VMOVSLDUPZ128rmk:
18204 case VMOVSLDUPZ128rmkz:
18205 case VMOVSLDUPZ128rr:
18206 case VMOVSLDUPZ128rrk:
18207 case VMOVSLDUPZ128rrkz:
18208 case VMOVSLDUPZ256rm:
18209 case VMOVSLDUPZ256rmk:
18210 case VMOVSLDUPZ256rmkz:
18211 case VMOVSLDUPZ256rr:
18212 case VMOVSLDUPZ256rrk:
18213 case VMOVSLDUPZ256rrkz:
18214 case VMOVSLDUPZrm:
18215 case VMOVSLDUPZrmk:
18216 case VMOVSLDUPZrmkz:
18217 case VMOVSLDUPZrr:
18218 case VMOVSLDUPZrrk:
18219 case VMOVSLDUPZrrkz:
18220 case VMOVSLDUPrm:
18221 case VMOVSLDUPrr:
18222 return true;
18223 }
18224 return false;
18225}
18226
18227bool isINVLPGA(unsigned Opcode) {
18228 switch (Opcode) {
18229 case INVLPGA32:
18230 case INVLPGA64:
18231 return true;
18232 }
18233 return false;
18234}
18235
18236bool isVCVTPH2QQ(unsigned Opcode) {
18237 switch (Opcode) {
18238 case VCVTPH2QQZ128rm:
18239 case VCVTPH2QQZ128rmb:
18240 case VCVTPH2QQZ128rmbk:
18241 case VCVTPH2QQZ128rmbkz:
18242 case VCVTPH2QQZ128rmk:
18243 case VCVTPH2QQZ128rmkz:
18244 case VCVTPH2QQZ128rr:
18245 case VCVTPH2QQZ128rrk:
18246 case VCVTPH2QQZ128rrkz:
18247 case VCVTPH2QQZ256rm:
18248 case VCVTPH2QQZ256rmb:
18249 case VCVTPH2QQZ256rmbk:
18250 case VCVTPH2QQZ256rmbkz:
18251 case VCVTPH2QQZ256rmk:
18252 case VCVTPH2QQZ256rmkz:
18253 case VCVTPH2QQZ256rr:
18254 case VCVTPH2QQZ256rrk:
18255 case VCVTPH2QQZ256rrkz:
18256 case VCVTPH2QQZrm:
18257 case VCVTPH2QQZrmb:
18258 case VCVTPH2QQZrmbk:
18259 case VCVTPH2QQZrmbkz:
18260 case VCVTPH2QQZrmk:
18261 case VCVTPH2QQZrmkz:
18262 case VCVTPH2QQZrr:
18263 case VCVTPH2QQZrrb:
18264 case VCVTPH2QQZrrbk:
18265 case VCVTPH2QQZrrbkz:
18266 case VCVTPH2QQZrrk:
18267 case VCVTPH2QQZrrkz:
18268 return true;
18269 }
18270 return false;
18271}
18272
18273bool isADD(unsigned Opcode) {
18274 switch (Opcode) {
18275 case ADD16i16:
18276 case ADD16mi:
18277 case ADD16mi8:
18278 case ADD16mi8_EVEX:
18279 case ADD16mi8_ND:
18280 case ADD16mi8_NF:
18281 case ADD16mi8_NF_ND:
18282 case ADD16mi_EVEX:
18283 case ADD16mi_ND:
18284 case ADD16mi_NF:
18285 case ADD16mi_NF_ND:
18286 case ADD16mr:
18287 case ADD16mr_EVEX:
18288 case ADD16mr_ND:
18289 case ADD16mr_NF:
18290 case ADD16mr_NF_ND:
18291 case ADD16ri:
18292 case ADD16ri8:
18293 case ADD16ri8_EVEX:
18294 case ADD16ri8_ND:
18295 case ADD16ri8_NF:
18296 case ADD16ri8_NF_ND:
18297 case ADD16ri_EVEX:
18298 case ADD16ri_ND:
18299 case ADD16ri_NF:
18300 case ADD16ri_NF_ND:
18301 case ADD16rm:
18302 case ADD16rm_EVEX:
18303 case ADD16rm_ND:
18304 case ADD16rm_NF:
18305 case ADD16rm_NF_ND:
18306 case ADD16rr:
18307 case ADD16rr_EVEX:
18308 case ADD16rr_EVEX_REV:
18309 case ADD16rr_ND:
18310 case ADD16rr_ND_REV:
18311 case ADD16rr_NF:
18312 case ADD16rr_NF_ND:
18313 case ADD16rr_NF_ND_REV:
18314 case ADD16rr_NF_REV:
18315 case ADD16rr_REV:
18316 case ADD32i32:
18317 case ADD32mi:
18318 case ADD32mi8:
18319 case ADD32mi8_EVEX:
18320 case ADD32mi8_ND:
18321 case ADD32mi8_NF:
18322 case ADD32mi8_NF_ND:
18323 case ADD32mi_EVEX:
18324 case ADD32mi_ND:
18325 case ADD32mi_NF:
18326 case ADD32mi_NF_ND:
18327 case ADD32mr:
18328 case ADD32mr_EVEX:
18329 case ADD32mr_ND:
18330 case ADD32mr_NF:
18331 case ADD32mr_NF_ND:
18332 case ADD32ri:
18333 case ADD32ri8:
18334 case ADD32ri8_EVEX:
18335 case ADD32ri8_ND:
18336 case ADD32ri8_NF:
18337 case ADD32ri8_NF_ND:
18338 case ADD32ri_EVEX:
18339 case ADD32ri_ND:
18340 case ADD32ri_NF:
18341 case ADD32ri_NF_ND:
18342 case ADD32rm:
18343 case ADD32rm_EVEX:
18344 case ADD32rm_ND:
18345 case ADD32rm_NF:
18346 case ADD32rm_NF_ND:
18347 case ADD32rr:
18348 case ADD32rr_EVEX:
18349 case ADD32rr_EVEX_REV:
18350 case ADD32rr_ND:
18351 case ADD32rr_ND_REV:
18352 case ADD32rr_NF:
18353 case ADD32rr_NF_ND:
18354 case ADD32rr_NF_ND_REV:
18355 case ADD32rr_NF_REV:
18356 case ADD32rr_REV:
18357 case ADD64i32:
18358 case ADD64mi32:
18359 case ADD64mi32_EVEX:
18360 case ADD64mi32_ND:
18361 case ADD64mi32_NF:
18362 case ADD64mi32_NF_ND:
18363 case ADD64mi8:
18364 case ADD64mi8_EVEX:
18365 case ADD64mi8_ND:
18366 case ADD64mi8_NF:
18367 case ADD64mi8_NF_ND:
18368 case ADD64mr:
18369 case ADD64mr_EVEX:
18370 case ADD64mr_ND:
18371 case ADD64mr_NF:
18372 case ADD64mr_NF_ND:
18373 case ADD64ri32:
18374 case ADD64ri32_EVEX:
18375 case ADD64ri32_ND:
18376 case ADD64ri32_NF:
18377 case ADD64ri32_NF_ND:
18378 case ADD64ri8:
18379 case ADD64ri8_EVEX:
18380 case ADD64ri8_ND:
18381 case ADD64ri8_NF:
18382 case ADD64ri8_NF_ND:
18383 case ADD64rm:
18384 case ADD64rm_EVEX:
18385 case ADD64rm_ND:
18386 case ADD64rm_NF:
18387 case ADD64rm_NF_ND:
18388 case ADD64rr:
18389 case ADD64rr_EVEX:
18390 case ADD64rr_EVEX_REV:
18391 case ADD64rr_ND:
18392 case ADD64rr_ND_REV:
18393 case ADD64rr_NF:
18394 case ADD64rr_NF_ND:
18395 case ADD64rr_NF_ND_REV:
18396 case ADD64rr_NF_REV:
18397 case ADD64rr_REV:
18398 case ADD8i8:
18399 case ADD8mi:
18400 case ADD8mi8:
18401 case ADD8mi_EVEX:
18402 case ADD8mi_ND:
18403 case ADD8mi_NF:
18404 case ADD8mi_NF_ND:
18405 case ADD8mr:
18406 case ADD8mr_EVEX:
18407 case ADD8mr_ND:
18408 case ADD8mr_NF:
18409 case ADD8mr_NF_ND:
18410 case ADD8ri:
18411 case ADD8ri8:
18412 case ADD8ri_EVEX:
18413 case ADD8ri_ND:
18414 case ADD8ri_NF:
18415 case ADD8ri_NF_ND:
18416 case ADD8rm:
18417 case ADD8rm_EVEX:
18418 case ADD8rm_ND:
18419 case ADD8rm_NF:
18420 case ADD8rm_NF_ND:
18421 case ADD8rr:
18422 case ADD8rr_EVEX:
18423 case ADD8rr_EVEX_REV:
18424 case ADD8rr_ND:
18425 case ADD8rr_ND_REV:
18426 case ADD8rr_NF:
18427 case ADD8rr_NF_ND:
18428 case ADD8rr_NF_ND_REV:
18429 case ADD8rr_NF_REV:
18430 case ADD8rr_REV:
18431 return true;
18432 }
18433 return false;
18434}
18435
18436bool isPSUBSW(unsigned Opcode) {
18437 switch (Opcode) {
18438 case MMX_PSUBSWrm:
18439 case MMX_PSUBSWrr:
18440 case PSUBSWrm:
18441 case PSUBSWrr:
18442 return true;
18443 }
18444 return false;
18445}
18446
18447bool isSIDTW(unsigned Opcode) {
18448 return Opcode == SIDT16m;
18449}
18450
18451bool isVFNMADD231PH(unsigned Opcode) {
18452 switch (Opcode) {
18453 case VFNMADD231PHZ128m:
18454 case VFNMADD231PHZ128mb:
18455 case VFNMADD231PHZ128mbk:
18456 case VFNMADD231PHZ128mbkz:
18457 case VFNMADD231PHZ128mk:
18458 case VFNMADD231PHZ128mkz:
18459 case VFNMADD231PHZ128r:
18460 case VFNMADD231PHZ128rk:
18461 case VFNMADD231PHZ128rkz:
18462 case VFNMADD231PHZ256m:
18463 case VFNMADD231PHZ256mb:
18464 case VFNMADD231PHZ256mbk:
18465 case VFNMADD231PHZ256mbkz:
18466 case VFNMADD231PHZ256mk:
18467 case VFNMADD231PHZ256mkz:
18468 case VFNMADD231PHZ256r:
18469 case VFNMADD231PHZ256rk:
18470 case VFNMADD231PHZ256rkz:
18471 case VFNMADD231PHZm:
18472 case VFNMADD231PHZmb:
18473 case VFNMADD231PHZmbk:
18474 case VFNMADD231PHZmbkz:
18475 case VFNMADD231PHZmk:
18476 case VFNMADD231PHZmkz:
18477 case VFNMADD231PHZr:
18478 case VFNMADD231PHZrb:
18479 case VFNMADD231PHZrbk:
18480 case VFNMADD231PHZrbkz:
18481 case VFNMADD231PHZrk:
18482 case VFNMADD231PHZrkz:
18483 return true;
18484 }
18485 return false;
18486}
18487
18488bool isVEXTRACTF64X2(unsigned Opcode) {
18489 switch (Opcode) {
18490 case VEXTRACTF64X2Z256mri:
18491 case VEXTRACTF64X2Z256mrik:
18492 case VEXTRACTF64X2Z256rri:
18493 case VEXTRACTF64X2Z256rrik:
18494 case VEXTRACTF64X2Z256rrikz:
18495 case VEXTRACTF64X2Zmri:
18496 case VEXTRACTF64X2Zmrik:
18497 case VEXTRACTF64X2Zrri:
18498 case VEXTRACTF64X2Zrrik:
18499 case VEXTRACTF64X2Zrrikz:
18500 return true;
18501 }
18502 return false;
18503}
18504
18505bool isFCOMI(unsigned Opcode) {
18506 return Opcode == COM_FIr;
18507}
18508
18509bool isRSM(unsigned Opcode) {
18510 return Opcode == RSM;
18511}
18512
18513bool isVPCOMUD(unsigned Opcode) {
18514 switch (Opcode) {
18515 case VPCOMUDmi:
18516 case VPCOMUDri:
18517 return true;
18518 }
18519 return false;
18520}
18521
18522bool isVPMOVZXBQ(unsigned Opcode) {
18523 switch (Opcode) {
18524 case VPMOVZXBQYrm:
18525 case VPMOVZXBQYrr:
18526 case VPMOVZXBQZ128rm:
18527 case VPMOVZXBQZ128rmk:
18528 case VPMOVZXBQZ128rmkz:
18529 case VPMOVZXBQZ128rr:
18530 case VPMOVZXBQZ128rrk:
18531 case VPMOVZXBQZ128rrkz:
18532 case VPMOVZXBQZ256rm:
18533 case VPMOVZXBQZ256rmk:
18534 case VPMOVZXBQZ256rmkz:
18535 case VPMOVZXBQZ256rr:
18536 case VPMOVZXBQZ256rrk:
18537 case VPMOVZXBQZ256rrkz:
18538 case VPMOVZXBQZrm:
18539 case VPMOVZXBQZrmk:
18540 case VPMOVZXBQZrmkz:
18541 case VPMOVZXBQZrr:
18542 case VPMOVZXBQZrrk:
18543 case VPMOVZXBQZrrkz:
18544 case VPMOVZXBQrm:
18545 case VPMOVZXBQrr:
18546 return true;
18547 }
18548 return false;
18549}
18550
18551bool isUWRMSR(unsigned Opcode) {
18552 switch (Opcode) {
18553 case UWRMSRir:
18554 case UWRMSRir_EVEX:
18555 case UWRMSRrr:
18556 case UWRMSRrr_EVEX:
18557 return true;
18558 }
18559 return false;
18560}
18561
18562bool isLGS(unsigned Opcode) {
18563 switch (Opcode) {
18564 case LGS16rm:
18565 case LGS32rm:
18566 case LGS64rm:
18567 return true;
18568 }
18569 return false;
18570}
18571
18572bool isVMOVNTPD(unsigned Opcode) {
18573 switch (Opcode) {
18574 case VMOVNTPDYmr:
18575 case VMOVNTPDZ128mr:
18576 case VMOVNTPDZ256mr:
18577 case VMOVNTPDZmr:
18578 case VMOVNTPDmr:
18579 return true;
18580 }
18581 return false;
18582}
18583
18584bool isPCMPESTRMQ(unsigned Opcode) {
18585 switch (Opcode) {
18586 case PCMPESTRMQrmi:
18587 case PCMPESTRMQrri:
18588 return true;
18589 }
18590 return false;
18591}
18592
18593bool isRDPRU(unsigned Opcode) {
18594 return Opcode == RDPRU;
18595}
18596
18597bool isVPUNPCKHBW(unsigned Opcode) {
18598 switch (Opcode) {
18599 case VPUNPCKHBWYrm:
18600 case VPUNPCKHBWYrr:
18601 case VPUNPCKHBWZ128rm:
18602 case VPUNPCKHBWZ128rmk:
18603 case VPUNPCKHBWZ128rmkz:
18604 case VPUNPCKHBWZ128rr:
18605 case VPUNPCKHBWZ128rrk:
18606 case VPUNPCKHBWZ128rrkz:
18607 case VPUNPCKHBWZ256rm:
18608 case VPUNPCKHBWZ256rmk:
18609 case VPUNPCKHBWZ256rmkz:
18610 case VPUNPCKHBWZ256rr:
18611 case VPUNPCKHBWZ256rrk:
18612 case VPUNPCKHBWZ256rrkz:
18613 case VPUNPCKHBWZrm:
18614 case VPUNPCKHBWZrmk:
18615 case VPUNPCKHBWZrmkz:
18616 case VPUNPCKHBWZrr:
18617 case VPUNPCKHBWZrrk:
18618 case VPUNPCKHBWZrrkz:
18619 case VPUNPCKHBWrm:
18620 case VPUNPCKHBWrr:
18621 return true;
18622 }
18623 return false;
18624}
18625
18626bool isVUCOMXSD(unsigned Opcode) {
18627 switch (Opcode) {
18628 case VUCOMXSDZrm_Int:
18629 case VUCOMXSDZrr_Int:
18630 case VUCOMXSDZrrb_Int:
18631 return true;
18632 }
18633 return false;
18634}
18635
18636bool isANDN(unsigned Opcode) {
18637 switch (Opcode) {
18638 case ANDN32rm:
18639 case ANDN32rm_EVEX:
18640 case ANDN32rm_NF:
18641 case ANDN32rr:
18642 case ANDN32rr_EVEX:
18643 case ANDN32rr_NF:
18644 case ANDN64rm:
18645 case ANDN64rm_EVEX:
18646 case ANDN64rm_NF:
18647 case ANDN64rr:
18648 case ANDN64rr_EVEX:
18649 case ANDN64rr_NF:
18650 return true;
18651 }
18652 return false;
18653}
18654
18655bool isVCVTTPH2UW(unsigned Opcode) {
18656 switch (Opcode) {
18657 case VCVTTPH2UWZ128rm:
18658 case VCVTTPH2UWZ128rmb:
18659 case VCVTTPH2UWZ128rmbk:
18660 case VCVTTPH2UWZ128rmbkz:
18661 case VCVTTPH2UWZ128rmk:
18662 case VCVTTPH2UWZ128rmkz:
18663 case VCVTTPH2UWZ128rr:
18664 case VCVTTPH2UWZ128rrk:
18665 case VCVTTPH2UWZ128rrkz:
18666 case VCVTTPH2UWZ256rm:
18667 case VCVTTPH2UWZ256rmb:
18668 case VCVTTPH2UWZ256rmbk:
18669 case VCVTTPH2UWZ256rmbkz:
18670 case VCVTTPH2UWZ256rmk:
18671 case VCVTTPH2UWZ256rmkz:
18672 case VCVTTPH2UWZ256rr:
18673 case VCVTTPH2UWZ256rrk:
18674 case VCVTTPH2UWZ256rrkz:
18675 case VCVTTPH2UWZrm:
18676 case VCVTTPH2UWZrmb:
18677 case VCVTTPH2UWZrmbk:
18678 case VCVTTPH2UWZrmbkz:
18679 case VCVTTPH2UWZrmk:
18680 case VCVTTPH2UWZrmkz:
18681 case VCVTTPH2UWZrr:
18682 case VCVTTPH2UWZrrb:
18683 case VCVTTPH2UWZrrbk:
18684 case VCVTTPH2UWZrrbkz:
18685 case VCVTTPH2UWZrrk:
18686 case VCVTTPH2UWZrrkz:
18687 return true;
18688 }
18689 return false;
18690}
18691
18692bool isVMFUNC(unsigned Opcode) {
18693 return Opcode == VMFUNC;
18694}
18695
18696bool isFIMUL(unsigned Opcode) {
18697 switch (Opcode) {
18698 case MUL_FI16m:
18699 case MUL_FI32m:
18700 return true;
18701 }
18702 return false;
18703}
18704
18705bool isBLCFILL(unsigned Opcode) {
18706 switch (Opcode) {
18707 case BLCFILL32rm:
18708 case BLCFILL32rr:
18709 case BLCFILL64rm:
18710 case BLCFILL64rr:
18711 return true;
18712 }
18713 return false;
18714}
18715
18716bool isVGATHERPF0DPS(unsigned Opcode) {
18717 return Opcode == VGATHERPF0DPSm;
18718}
18719
18720bool isVFMSUBADD231PS(unsigned Opcode) {
18721 switch (Opcode) {
18722 case VFMSUBADD231PSYm:
18723 case VFMSUBADD231PSYr:
18724 case VFMSUBADD231PSZ128m:
18725 case VFMSUBADD231PSZ128mb:
18726 case VFMSUBADD231PSZ128mbk:
18727 case VFMSUBADD231PSZ128mbkz:
18728 case VFMSUBADD231PSZ128mk:
18729 case VFMSUBADD231PSZ128mkz:
18730 case VFMSUBADD231PSZ128r:
18731 case VFMSUBADD231PSZ128rk:
18732 case VFMSUBADD231PSZ128rkz:
18733 case VFMSUBADD231PSZ256m:
18734 case VFMSUBADD231PSZ256mb:
18735 case VFMSUBADD231PSZ256mbk:
18736 case VFMSUBADD231PSZ256mbkz:
18737 case VFMSUBADD231PSZ256mk:
18738 case VFMSUBADD231PSZ256mkz:
18739 case VFMSUBADD231PSZ256r:
18740 case VFMSUBADD231PSZ256rk:
18741 case VFMSUBADD231PSZ256rkz:
18742 case VFMSUBADD231PSZm:
18743 case VFMSUBADD231PSZmb:
18744 case VFMSUBADD231PSZmbk:
18745 case VFMSUBADD231PSZmbkz:
18746 case VFMSUBADD231PSZmk:
18747 case VFMSUBADD231PSZmkz:
18748 case VFMSUBADD231PSZr:
18749 case VFMSUBADD231PSZrb:
18750 case VFMSUBADD231PSZrbk:
18751 case VFMSUBADD231PSZrbkz:
18752 case VFMSUBADD231PSZrk:
18753 case VFMSUBADD231PSZrkz:
18754 case VFMSUBADD231PSm:
18755 case VFMSUBADD231PSr:
18756 return true;
18757 }
18758 return false;
18759}
18760
18761bool isVREDUCESD(unsigned Opcode) {
18762 switch (Opcode) {
18763 case VREDUCESDZrmi:
18764 case VREDUCESDZrmik:
18765 case VREDUCESDZrmikz:
18766 case VREDUCESDZrri:
18767 case VREDUCESDZrrib:
18768 case VREDUCESDZrribk:
18769 case VREDUCESDZrribkz:
18770 case VREDUCESDZrrik:
18771 case VREDUCESDZrrikz:
18772 return true;
18773 }
18774 return false;
18775}
18776
18777bool isVCOMXSH(unsigned Opcode) {
18778 switch (Opcode) {
18779 case VCOMXSHZrm_Int:
18780 case VCOMXSHZrr_Int:
18781 case VCOMXSHZrrb_Int:
18782 return true;
18783 }
18784 return false;
18785}
18786
18787bool isVXORPS(unsigned Opcode) {
18788 switch (Opcode) {
18789 case VXORPSYrm:
18790 case VXORPSYrr:
18791 case VXORPSZ128rm:
18792 case VXORPSZ128rmb:
18793 case VXORPSZ128rmbk:
18794 case VXORPSZ128rmbkz:
18795 case VXORPSZ128rmk:
18796 case VXORPSZ128rmkz:
18797 case VXORPSZ128rr:
18798 case VXORPSZ128rrk:
18799 case VXORPSZ128rrkz:
18800 case VXORPSZ256rm:
18801 case VXORPSZ256rmb:
18802 case VXORPSZ256rmbk:
18803 case VXORPSZ256rmbkz:
18804 case VXORPSZ256rmk:
18805 case VXORPSZ256rmkz:
18806 case VXORPSZ256rr:
18807 case VXORPSZ256rrk:
18808 case VXORPSZ256rrkz:
18809 case VXORPSZrm:
18810 case VXORPSZrmb:
18811 case VXORPSZrmbk:
18812 case VXORPSZrmbkz:
18813 case VXORPSZrmk:
18814 case VXORPSZrmkz:
18815 case VXORPSZrr:
18816 case VXORPSZrrk:
18817 case VXORPSZrrkz:
18818 case VXORPSrm:
18819 case VXORPSrr:
18820 return true;
18821 }
18822 return false;
18823}
18824
18825bool isPSWAPD(unsigned Opcode) {
18826 switch (Opcode) {
18827 case PSWAPDrm:
18828 case PSWAPDrr:
18829 return true;
18830 }
18831 return false;
18832}
18833
18834bool isPMAXSD(unsigned Opcode) {
18835 switch (Opcode) {
18836 case PMAXSDrm:
18837 case PMAXSDrr:
18838 return true;
18839 }
18840 return false;
18841}
18842
18843bool isVCMPSS(unsigned Opcode) {
18844 switch (Opcode) {
18845 case VCMPSSZrmi_Int:
18846 case VCMPSSZrmik_Int:
18847 case VCMPSSZrri_Int:
18848 case VCMPSSZrrib_Int:
18849 case VCMPSSZrribk_Int:
18850 case VCMPSSZrrik_Int:
18851 case VCMPSSrmi_Int:
18852 case VCMPSSrri_Int:
18853 return true;
18854 }
18855 return false;
18856}
18857
18858bool isEXTRACTPS(unsigned Opcode) {
18859 switch (Opcode) {
18860 case EXTRACTPSmri:
18861 case EXTRACTPSrri:
18862 return true;
18863 }
18864 return false;
18865}
18866
18867bool isVPMOVZXBD(unsigned Opcode) {
18868 switch (Opcode) {
18869 case VPMOVZXBDYrm:
18870 case VPMOVZXBDYrr:
18871 case VPMOVZXBDZ128rm:
18872 case VPMOVZXBDZ128rmk:
18873 case VPMOVZXBDZ128rmkz:
18874 case VPMOVZXBDZ128rr:
18875 case VPMOVZXBDZ128rrk:
18876 case VPMOVZXBDZ128rrkz:
18877 case VPMOVZXBDZ256rm:
18878 case VPMOVZXBDZ256rmk:
18879 case VPMOVZXBDZ256rmkz:
18880 case VPMOVZXBDZ256rr:
18881 case VPMOVZXBDZ256rrk:
18882 case VPMOVZXBDZ256rrkz:
18883 case VPMOVZXBDZrm:
18884 case VPMOVZXBDZrmk:
18885 case VPMOVZXBDZrmkz:
18886 case VPMOVZXBDZrr:
18887 case VPMOVZXBDZrrk:
18888 case VPMOVZXBDZrrkz:
18889 case VPMOVZXBDrm:
18890 case VPMOVZXBDrr:
18891 return true;
18892 }
18893 return false;
18894}
18895
18896bool isOUTSW(unsigned Opcode) {
18897 return Opcode == OUTSW;
18898}
18899
18900bool isKORTESTB(unsigned Opcode) {
18901 return Opcode == KORTESTBkk;
18902}
18903
18904bool isVREDUCEPS(unsigned Opcode) {
18905 switch (Opcode) {
18906 case VREDUCEPSZ128rmbi:
18907 case VREDUCEPSZ128rmbik:
18908 case VREDUCEPSZ128rmbikz:
18909 case VREDUCEPSZ128rmi:
18910 case VREDUCEPSZ128rmik:
18911 case VREDUCEPSZ128rmikz:
18912 case VREDUCEPSZ128rri:
18913 case VREDUCEPSZ128rrik:
18914 case VREDUCEPSZ128rrikz:
18915 case VREDUCEPSZ256rmbi:
18916 case VREDUCEPSZ256rmbik:
18917 case VREDUCEPSZ256rmbikz:
18918 case VREDUCEPSZ256rmi:
18919 case VREDUCEPSZ256rmik:
18920 case VREDUCEPSZ256rmikz:
18921 case VREDUCEPSZ256rri:
18922 case VREDUCEPSZ256rrik:
18923 case VREDUCEPSZ256rrikz:
18924 case VREDUCEPSZrmbi:
18925 case VREDUCEPSZrmbik:
18926 case VREDUCEPSZrmbikz:
18927 case VREDUCEPSZrmi:
18928 case VREDUCEPSZrmik:
18929 case VREDUCEPSZrmikz:
18930 case VREDUCEPSZrri:
18931 case VREDUCEPSZrrib:
18932 case VREDUCEPSZrribk:
18933 case VREDUCEPSZrribkz:
18934 case VREDUCEPSZrrik:
18935 case VREDUCEPSZrrikz:
18936 return true;
18937 }
18938 return false;
18939}
18940
18941bool isPEXTRW(unsigned Opcode) {
18942 switch (Opcode) {
18943 case MMX_PEXTRWrri:
18944 case PEXTRWmri:
18945 case PEXTRWrri:
18946 case PEXTRWrri_REV:
18947 return true;
18948 }
18949 return false;
18950}
18951
18952bool isFNINIT(unsigned Opcode) {
18953 return Opcode == FNINIT;
18954}
18955
18956bool isVCVTPH2IBS(unsigned Opcode) {
18957 switch (Opcode) {
18958 case VCVTPH2IBSZ128rm:
18959 case VCVTPH2IBSZ128rmb:
18960 case VCVTPH2IBSZ128rmbk:
18961 case VCVTPH2IBSZ128rmbkz:
18962 case VCVTPH2IBSZ128rmk:
18963 case VCVTPH2IBSZ128rmkz:
18964 case VCVTPH2IBSZ128rr:
18965 case VCVTPH2IBSZ128rrk:
18966 case VCVTPH2IBSZ128rrkz:
18967 case VCVTPH2IBSZ256rm:
18968 case VCVTPH2IBSZ256rmb:
18969 case VCVTPH2IBSZ256rmbk:
18970 case VCVTPH2IBSZ256rmbkz:
18971 case VCVTPH2IBSZ256rmk:
18972 case VCVTPH2IBSZ256rmkz:
18973 case VCVTPH2IBSZ256rr:
18974 case VCVTPH2IBSZ256rrk:
18975 case VCVTPH2IBSZ256rrkz:
18976 case VCVTPH2IBSZrm:
18977 case VCVTPH2IBSZrmb:
18978 case VCVTPH2IBSZrmbk:
18979 case VCVTPH2IBSZrmbkz:
18980 case VCVTPH2IBSZrmk:
18981 case VCVTPH2IBSZrmkz:
18982 case VCVTPH2IBSZrr:
18983 case VCVTPH2IBSZrrb:
18984 case VCVTPH2IBSZrrbk:
18985 case VCVTPH2IBSZrrbkz:
18986 case VCVTPH2IBSZrrk:
18987 case VCVTPH2IBSZrrkz:
18988 return true;
18989 }
18990 return false;
18991}
18992
18993bool isROL(unsigned Opcode) {
18994 switch (Opcode) {
18995 case ROL16m1:
18996 case ROL16m1_EVEX:
18997 case ROL16m1_ND:
18998 case ROL16m1_NF:
18999 case ROL16m1_NF_ND:
19000 case ROL16mCL:
19001 case ROL16mCL_EVEX:
19002 case ROL16mCL_ND:
19003 case ROL16mCL_NF:
19004 case ROL16mCL_NF_ND:
19005 case ROL16mi:
19006 case ROL16mi_EVEX:
19007 case ROL16mi_ND:
19008 case ROL16mi_NF:
19009 case ROL16mi_NF_ND:
19010 case ROL16r1:
19011 case ROL16r1_EVEX:
19012 case ROL16r1_ND:
19013 case ROL16r1_NF:
19014 case ROL16r1_NF_ND:
19015 case ROL16rCL:
19016 case ROL16rCL_EVEX:
19017 case ROL16rCL_ND:
19018 case ROL16rCL_NF:
19019 case ROL16rCL_NF_ND:
19020 case ROL16ri:
19021 case ROL16ri_EVEX:
19022 case ROL16ri_ND:
19023 case ROL16ri_NF:
19024 case ROL16ri_NF_ND:
19025 case ROL32m1:
19026 case ROL32m1_EVEX:
19027 case ROL32m1_ND:
19028 case ROL32m1_NF:
19029 case ROL32m1_NF_ND:
19030 case ROL32mCL:
19031 case ROL32mCL_EVEX:
19032 case ROL32mCL_ND:
19033 case ROL32mCL_NF:
19034 case ROL32mCL_NF_ND:
19035 case ROL32mi:
19036 case ROL32mi_EVEX:
19037 case ROL32mi_ND:
19038 case ROL32mi_NF:
19039 case ROL32mi_NF_ND:
19040 case ROL32r1:
19041 case ROL32r1_EVEX:
19042 case ROL32r1_ND:
19043 case ROL32r1_NF:
19044 case ROL32r1_NF_ND:
19045 case ROL32rCL:
19046 case ROL32rCL_EVEX:
19047 case ROL32rCL_ND:
19048 case ROL32rCL_NF:
19049 case ROL32rCL_NF_ND:
19050 case ROL32ri:
19051 case ROL32ri_EVEX:
19052 case ROL32ri_ND:
19053 case ROL32ri_NF:
19054 case ROL32ri_NF_ND:
19055 case ROL64m1:
19056 case ROL64m1_EVEX:
19057 case ROL64m1_ND:
19058 case ROL64m1_NF:
19059 case ROL64m1_NF_ND:
19060 case ROL64mCL:
19061 case ROL64mCL_EVEX:
19062 case ROL64mCL_ND:
19063 case ROL64mCL_NF:
19064 case ROL64mCL_NF_ND:
19065 case ROL64mi:
19066 case ROL64mi_EVEX:
19067 case ROL64mi_ND:
19068 case ROL64mi_NF:
19069 case ROL64mi_NF_ND:
19070 case ROL64r1:
19071 case ROL64r1_EVEX:
19072 case ROL64r1_ND:
19073 case ROL64r1_NF:
19074 case ROL64r1_NF_ND:
19075 case ROL64rCL:
19076 case ROL64rCL_EVEX:
19077 case ROL64rCL_ND:
19078 case ROL64rCL_NF:
19079 case ROL64rCL_NF_ND:
19080 case ROL64ri:
19081 case ROL64ri_EVEX:
19082 case ROL64ri_ND:
19083 case ROL64ri_NF:
19084 case ROL64ri_NF_ND:
19085 case ROL8m1:
19086 case ROL8m1_EVEX:
19087 case ROL8m1_ND:
19088 case ROL8m1_NF:
19089 case ROL8m1_NF_ND:
19090 case ROL8mCL:
19091 case ROL8mCL_EVEX:
19092 case ROL8mCL_ND:
19093 case ROL8mCL_NF:
19094 case ROL8mCL_NF_ND:
19095 case ROL8mi:
19096 case ROL8mi_EVEX:
19097 case ROL8mi_ND:
19098 case ROL8mi_NF:
19099 case ROL8mi_NF_ND:
19100 case ROL8r1:
19101 case ROL8r1_EVEX:
19102 case ROL8r1_ND:
19103 case ROL8r1_NF:
19104 case ROL8r1_NF_ND:
19105 case ROL8rCL:
19106 case ROL8rCL_EVEX:
19107 case ROL8rCL_ND:
19108 case ROL8rCL_NF:
19109 case ROL8rCL_NF_ND:
19110 case ROL8ri:
19111 case ROL8ri_EVEX:
19112 case ROL8ri_ND:
19113 case ROL8ri_NF:
19114 case ROL8ri_NF_ND:
19115 return true;
19116 }
19117 return false;
19118}
19119
19120bool isVCVTPS2QQ(unsigned Opcode) {
19121 switch (Opcode) {
19122 case VCVTPS2QQZ128rm:
19123 case VCVTPS2QQZ128rmb:
19124 case VCVTPS2QQZ128rmbk:
19125 case VCVTPS2QQZ128rmbkz:
19126 case VCVTPS2QQZ128rmk:
19127 case VCVTPS2QQZ128rmkz:
19128 case VCVTPS2QQZ128rr:
19129 case VCVTPS2QQZ128rrk:
19130 case VCVTPS2QQZ128rrkz:
19131 case VCVTPS2QQZ256rm:
19132 case VCVTPS2QQZ256rmb:
19133 case VCVTPS2QQZ256rmbk:
19134 case VCVTPS2QQZ256rmbkz:
19135 case VCVTPS2QQZ256rmk:
19136 case VCVTPS2QQZ256rmkz:
19137 case VCVTPS2QQZ256rr:
19138 case VCVTPS2QQZ256rrk:
19139 case VCVTPS2QQZ256rrkz:
19140 case VCVTPS2QQZrm:
19141 case VCVTPS2QQZrmb:
19142 case VCVTPS2QQZrmbk:
19143 case VCVTPS2QQZrmbkz:
19144 case VCVTPS2QQZrmk:
19145 case VCVTPS2QQZrmkz:
19146 case VCVTPS2QQZrr:
19147 case VCVTPS2QQZrrb:
19148 case VCVTPS2QQZrrbk:
19149 case VCVTPS2QQZrrbkz:
19150 case VCVTPS2QQZrrk:
19151 case VCVTPS2QQZrrkz:
19152 return true;
19153 }
19154 return false;
19155}
19156
19157bool isVGETMANTPH(unsigned Opcode) {
19158 switch (Opcode) {
19159 case VGETMANTPHZ128rmbi:
19160 case VGETMANTPHZ128rmbik:
19161 case VGETMANTPHZ128rmbikz:
19162 case VGETMANTPHZ128rmi:
19163 case VGETMANTPHZ128rmik:
19164 case VGETMANTPHZ128rmikz:
19165 case VGETMANTPHZ128rri:
19166 case VGETMANTPHZ128rrik:
19167 case VGETMANTPHZ128rrikz:
19168 case VGETMANTPHZ256rmbi:
19169 case VGETMANTPHZ256rmbik:
19170 case VGETMANTPHZ256rmbikz:
19171 case VGETMANTPHZ256rmi:
19172 case VGETMANTPHZ256rmik:
19173 case VGETMANTPHZ256rmikz:
19174 case VGETMANTPHZ256rri:
19175 case VGETMANTPHZ256rrik:
19176 case VGETMANTPHZ256rrikz:
19177 case VGETMANTPHZrmbi:
19178 case VGETMANTPHZrmbik:
19179 case VGETMANTPHZrmbikz:
19180 case VGETMANTPHZrmi:
19181 case VGETMANTPHZrmik:
19182 case VGETMANTPHZrmikz:
19183 case VGETMANTPHZrri:
19184 case VGETMANTPHZrrib:
19185 case VGETMANTPHZrribk:
19186 case VGETMANTPHZrribkz:
19187 case VGETMANTPHZrrik:
19188 case VGETMANTPHZrrikz:
19189 return true;
19190 }
19191 return false;
19192}
19193
19194bool isPUNPCKLDQ(unsigned Opcode) {
19195 switch (Opcode) {
19196 case MMX_PUNPCKLDQrm:
19197 case MMX_PUNPCKLDQrr:
19198 case PUNPCKLDQrm:
19199 case PUNPCKLDQrr:
19200 return true;
19201 }
19202 return false;
19203}
19204
19205bool isPADDD(unsigned Opcode) {
19206 switch (Opcode) {
19207 case MMX_PADDDrm:
19208 case MMX_PADDDrr:
19209 case PADDDrm:
19210 case PADDDrr:
19211 return true;
19212 }
19213 return false;
19214}
19215
19216bool isVPSLLD(unsigned Opcode) {
19217 switch (Opcode) {
19218 case VPSLLDYri:
19219 case VPSLLDYrm:
19220 case VPSLLDYrr:
19221 case VPSLLDZ128mbi:
19222 case VPSLLDZ128mbik:
19223 case VPSLLDZ128mbikz:
19224 case VPSLLDZ128mi:
19225 case VPSLLDZ128mik:
19226 case VPSLLDZ128mikz:
19227 case VPSLLDZ128ri:
19228 case VPSLLDZ128rik:
19229 case VPSLLDZ128rikz:
19230 case VPSLLDZ128rm:
19231 case VPSLLDZ128rmk:
19232 case VPSLLDZ128rmkz:
19233 case VPSLLDZ128rr:
19234 case VPSLLDZ128rrk:
19235 case VPSLLDZ128rrkz:
19236 case VPSLLDZ256mbi:
19237 case VPSLLDZ256mbik:
19238 case VPSLLDZ256mbikz:
19239 case VPSLLDZ256mi:
19240 case VPSLLDZ256mik:
19241 case VPSLLDZ256mikz:
19242 case VPSLLDZ256ri:
19243 case VPSLLDZ256rik:
19244 case VPSLLDZ256rikz:
19245 case VPSLLDZ256rm:
19246 case VPSLLDZ256rmk:
19247 case VPSLLDZ256rmkz:
19248 case VPSLLDZ256rr:
19249 case VPSLLDZ256rrk:
19250 case VPSLLDZ256rrkz:
19251 case VPSLLDZmbi:
19252 case VPSLLDZmbik:
19253 case VPSLLDZmbikz:
19254 case VPSLLDZmi:
19255 case VPSLLDZmik:
19256 case VPSLLDZmikz:
19257 case VPSLLDZri:
19258 case VPSLLDZrik:
19259 case VPSLLDZrikz:
19260 case VPSLLDZrm:
19261 case VPSLLDZrmk:
19262 case VPSLLDZrmkz:
19263 case VPSLLDZrr:
19264 case VPSLLDZrrk:
19265 case VPSLLDZrrkz:
19266 case VPSLLDri:
19267 case VPSLLDrm:
19268 case VPSLLDrr:
19269 return true;
19270 }
19271 return false;
19272}
19273
19274bool isPFCMPGE(unsigned Opcode) {
19275 switch (Opcode) {
19276 case PFCMPGErm:
19277 case PFCMPGErr:
19278 return true;
19279 }
19280 return false;
19281}
19282
19283bool isVGETMANTBF16(unsigned Opcode) {
19284 switch (Opcode) {
19285 case VGETMANTBF16Z128rmbi:
19286 case VGETMANTBF16Z128rmbik:
19287 case VGETMANTBF16Z128rmbikz:
19288 case VGETMANTBF16Z128rmi:
19289 case VGETMANTBF16Z128rmik:
19290 case VGETMANTBF16Z128rmikz:
19291 case VGETMANTBF16Z128rri:
19292 case VGETMANTBF16Z128rrik:
19293 case VGETMANTBF16Z128rrikz:
19294 case VGETMANTBF16Z256rmbi:
19295 case VGETMANTBF16Z256rmbik:
19296 case VGETMANTBF16Z256rmbikz:
19297 case VGETMANTBF16Z256rmi:
19298 case VGETMANTBF16Z256rmik:
19299 case VGETMANTBF16Z256rmikz:
19300 case VGETMANTBF16Z256rri:
19301 case VGETMANTBF16Z256rrik:
19302 case VGETMANTBF16Z256rrikz:
19303 case VGETMANTBF16Zrmbi:
19304 case VGETMANTBF16Zrmbik:
19305 case VGETMANTBF16Zrmbikz:
19306 case VGETMANTBF16Zrmi:
19307 case VGETMANTBF16Zrmik:
19308 case VGETMANTBF16Zrmikz:
19309 case VGETMANTBF16Zrri:
19310 case VGETMANTBF16Zrrik:
19311 case VGETMANTBF16Zrrikz:
19312 return true;
19313 }
19314 return false;
19315}
19316
19317bool isVSUBBF16(unsigned Opcode) {
19318 switch (Opcode) {
19319 case VSUBBF16Z128rm:
19320 case VSUBBF16Z128rmb:
19321 case VSUBBF16Z128rmbk:
19322 case VSUBBF16Z128rmbkz:
19323 case VSUBBF16Z128rmk:
19324 case VSUBBF16Z128rmkz:
19325 case VSUBBF16Z128rr:
19326 case VSUBBF16Z128rrk:
19327 case VSUBBF16Z128rrkz:
19328 case VSUBBF16Z256rm:
19329 case VSUBBF16Z256rmb:
19330 case VSUBBF16Z256rmbk:
19331 case VSUBBF16Z256rmbkz:
19332 case VSUBBF16Z256rmk:
19333 case VSUBBF16Z256rmkz:
19334 case VSUBBF16Z256rr:
19335 case VSUBBF16Z256rrk:
19336 case VSUBBF16Z256rrkz:
19337 case VSUBBF16Zrm:
19338 case VSUBBF16Zrmb:
19339 case VSUBBF16Zrmbk:
19340 case VSUBBF16Zrmbkz:
19341 case VSUBBF16Zrmk:
19342 case VSUBBF16Zrmkz:
19343 case VSUBBF16Zrr:
19344 case VSUBBF16Zrrk:
19345 case VSUBBF16Zrrkz:
19346 return true;
19347 }
19348 return false;
19349}
19350
19351bool isVPMOVM2D(unsigned Opcode) {
19352 switch (Opcode) {
19353 case VPMOVM2DZ128rk:
19354 case VPMOVM2DZ256rk:
19355 case VPMOVM2DZrk:
19356 return true;
19357 }
19358 return false;
19359}
19360
19361bool isVCVTTSS2USIS(unsigned Opcode) {
19362 switch (Opcode) {
19363 case VCVTTSS2USI64Srm_Int:
19364 case VCVTTSS2USI64Srr_Int:
19365 case VCVTTSS2USI64Srrb_Int:
19366 case VCVTTSS2USISrm_Int:
19367 case VCVTTSS2USISrr_Int:
19368 case VCVTTSS2USISrrb_Int:
19369 return true;
19370 }
19371 return false;
19372}
19373
19374bool isVHSUBPS(unsigned Opcode) {
19375 switch (Opcode) {
19376 case VHSUBPSYrm:
19377 case VHSUBPSYrr:
19378 case VHSUBPSrm:
19379 case VHSUBPSrr:
19380 return true;
19381 }
19382 return false;
19383}
19384
19385bool isENDBR32(unsigned Opcode) {
19386 return Opcode == ENDBR32;
19387}
19388
19389bool isMOVSXD(unsigned Opcode) {
19390 switch (Opcode) {
19391 case MOVSX16rm32:
19392 case MOVSX16rr32:
19393 case MOVSX32rm32:
19394 case MOVSX32rr32:
19395 case MOVSX64rm32:
19396 case MOVSX64rr32:
19397 return true;
19398 }
19399 return false;
19400}
19401
19402bool isPSIGND(unsigned Opcode) {
19403 switch (Opcode) {
19404 case MMX_PSIGNDrm:
19405 case MMX_PSIGNDrr:
19406 case PSIGNDrm:
19407 case PSIGNDrr:
19408 return true;
19409 }
19410 return false;
19411}
19412
19413bool isVPTEST(unsigned Opcode) {
19414 switch (Opcode) {
19415 case VPTESTYrm:
19416 case VPTESTYrr:
19417 case VPTESTrm:
19418 case VPTESTrr:
19419 return true;
19420 }
19421 return false;
19422}
19423
19424bool isVPDPWUSD(unsigned Opcode) {
19425 switch (Opcode) {
19426 case VPDPWUSDYrm:
19427 case VPDPWUSDYrr:
19428 case VPDPWUSDZ128rm:
19429 case VPDPWUSDZ128rmb:
19430 case VPDPWUSDZ128rmbk:
19431 case VPDPWUSDZ128rmbkz:
19432 case VPDPWUSDZ128rmk:
19433 case VPDPWUSDZ128rmkz:
19434 case VPDPWUSDZ128rr:
19435 case VPDPWUSDZ128rrk:
19436 case VPDPWUSDZ128rrkz:
19437 case VPDPWUSDZ256rm:
19438 case VPDPWUSDZ256rmb:
19439 case VPDPWUSDZ256rmbk:
19440 case VPDPWUSDZ256rmbkz:
19441 case VPDPWUSDZ256rmk:
19442 case VPDPWUSDZ256rmkz:
19443 case VPDPWUSDZ256rr:
19444 case VPDPWUSDZ256rrk:
19445 case VPDPWUSDZ256rrkz:
19446 case VPDPWUSDZrm:
19447 case VPDPWUSDZrmb:
19448 case VPDPWUSDZrmbk:
19449 case VPDPWUSDZrmbkz:
19450 case VPDPWUSDZrmk:
19451 case VPDPWUSDZrmkz:
19452 case VPDPWUSDZrr:
19453 case VPDPWUSDZrrk:
19454 case VPDPWUSDZrrkz:
19455 case VPDPWUSDrm:
19456 case VPDPWUSDrr:
19457 return true;
19458 }
19459 return false;
19460}
19461
19462bool isHSUBPD(unsigned Opcode) {
19463 switch (Opcode) {
19464 case HSUBPDrm:
19465 case HSUBPDrr:
19466 return true;
19467 }
19468 return false;
19469}
19470
19471bool isADCX(unsigned Opcode) {
19472 switch (Opcode) {
19473 case ADCX32rm:
19474 case ADCX32rm_EVEX:
19475 case ADCX32rm_ND:
19476 case ADCX32rr:
19477 case ADCX32rr_EVEX:
19478 case ADCX32rr_ND:
19479 case ADCX64rm:
19480 case ADCX64rm_EVEX:
19481 case ADCX64rm_ND:
19482 case ADCX64rr:
19483 case ADCX64rr_EVEX:
19484 case ADCX64rr_ND:
19485 return true;
19486 }
19487 return false;
19488}
19489
19490bool isCVTTPD2PI(unsigned Opcode) {
19491 switch (Opcode) {
19492 case MMX_CVTTPD2PIrm:
19493 case MMX_CVTTPD2PIrr:
19494 return true;
19495 }
19496 return false;
19497}
19498
19499bool isPDEP(unsigned Opcode) {
19500 switch (Opcode) {
19501 case PDEP32rm:
19502 case PDEP32rm_EVEX:
19503 case PDEP32rr:
19504 case PDEP32rr_EVEX:
19505 case PDEP64rm:
19506 case PDEP64rm_EVEX:
19507 case PDEP64rr:
19508 case PDEP64rr_EVEX:
19509 return true;
19510 }
19511 return false;
19512}
19513
19514bool isTDPBUSD(unsigned Opcode) {
19515 return Opcode == TDPBUSD;
19516}
19517
19518bool isVCVTBIASPH2HF8S(unsigned Opcode) {
19519 switch (Opcode) {
19520 case VCVTBIASPH2HF8SZ128rm:
19521 case VCVTBIASPH2HF8SZ128rmb:
19522 case VCVTBIASPH2HF8SZ128rmbk:
19523 case VCVTBIASPH2HF8SZ128rmbkz:
19524 case VCVTBIASPH2HF8SZ128rmk:
19525 case VCVTBIASPH2HF8SZ128rmkz:
19526 case VCVTBIASPH2HF8SZ128rr:
19527 case VCVTBIASPH2HF8SZ128rrk:
19528 case VCVTBIASPH2HF8SZ128rrkz:
19529 case VCVTBIASPH2HF8SZ256rm:
19530 case VCVTBIASPH2HF8SZ256rmb:
19531 case VCVTBIASPH2HF8SZ256rmbk:
19532 case VCVTBIASPH2HF8SZ256rmbkz:
19533 case VCVTBIASPH2HF8SZ256rmk:
19534 case VCVTBIASPH2HF8SZ256rmkz:
19535 case VCVTBIASPH2HF8SZ256rr:
19536 case VCVTBIASPH2HF8SZ256rrk:
19537 case VCVTBIASPH2HF8SZ256rrkz:
19538 case VCVTBIASPH2HF8SZrm:
19539 case VCVTBIASPH2HF8SZrmb:
19540 case VCVTBIASPH2HF8SZrmbk:
19541 case VCVTBIASPH2HF8SZrmbkz:
19542 case VCVTBIASPH2HF8SZrmk:
19543 case VCVTBIASPH2HF8SZrmkz:
19544 case VCVTBIASPH2HF8SZrr:
19545 case VCVTBIASPH2HF8SZrrk:
19546 case VCVTBIASPH2HF8SZrrkz:
19547 return true;
19548 }
19549 return false;
19550}
19551
19552bool isVBROADCASTI32X4(unsigned Opcode) {
19553 switch (Opcode) {
19554 case VBROADCASTI32X4Z256rm:
19555 case VBROADCASTI32X4Z256rmk:
19556 case VBROADCASTI32X4Z256rmkz:
19557 case VBROADCASTI32X4Zrm:
19558 case VBROADCASTI32X4Zrmk:
19559 case VBROADCASTI32X4Zrmkz:
19560 return true;
19561 }
19562 return false;
19563}
19564
19565bool isVCVTPH2UDQ(unsigned Opcode) {
19566 switch (Opcode) {
19567 case VCVTPH2UDQZ128rm:
19568 case VCVTPH2UDQZ128rmb:
19569 case VCVTPH2UDQZ128rmbk:
19570 case VCVTPH2UDQZ128rmbkz:
19571 case VCVTPH2UDQZ128rmk:
19572 case VCVTPH2UDQZ128rmkz:
19573 case VCVTPH2UDQZ128rr:
19574 case VCVTPH2UDQZ128rrk:
19575 case VCVTPH2UDQZ128rrkz:
19576 case VCVTPH2UDQZ256rm:
19577 case VCVTPH2UDQZ256rmb:
19578 case VCVTPH2UDQZ256rmbk:
19579 case VCVTPH2UDQZ256rmbkz:
19580 case VCVTPH2UDQZ256rmk:
19581 case VCVTPH2UDQZ256rmkz:
19582 case VCVTPH2UDQZ256rr:
19583 case VCVTPH2UDQZ256rrk:
19584 case VCVTPH2UDQZ256rrkz:
19585 case VCVTPH2UDQZrm:
19586 case VCVTPH2UDQZrmb:
19587 case VCVTPH2UDQZrmbk:
19588 case VCVTPH2UDQZrmbkz:
19589 case VCVTPH2UDQZrmk:
19590 case VCVTPH2UDQZrmkz:
19591 case VCVTPH2UDQZrr:
19592 case VCVTPH2UDQZrrb:
19593 case VCVTPH2UDQZrrbk:
19594 case VCVTPH2UDQZrrbkz:
19595 case VCVTPH2UDQZrrk:
19596 case VCVTPH2UDQZrrkz:
19597 return true;
19598 }
19599 return false;
19600}
19601
19602bool isVPHADDW(unsigned Opcode) {
19603 switch (Opcode) {
19604 case VPHADDWYrm:
19605 case VPHADDWYrr:
19606 case VPHADDWrm:
19607 case VPHADDWrr:
19608 return true;
19609 }
19610 return false;
19611}
19612
19613bool isFLDL2E(unsigned Opcode) {
19614 return Opcode == FLDL2E;
19615}
19616
19617bool isCLZERO(unsigned Opcode) {
19618 switch (Opcode) {
19619 case CLZERO32r:
19620 case CLZERO64r:
19621 return true;
19622 }
19623 return false;
19624}
19625
19626bool isPBLENDW(unsigned Opcode) {
19627 switch (Opcode) {
19628 case PBLENDWrmi:
19629 case PBLENDWrri:
19630 return true;
19631 }
19632 return false;
19633}
19634
19635bool isVCVTBF162IUBS(unsigned Opcode) {
19636 switch (Opcode) {
19637 case VCVTBF162IUBSZ128rm:
19638 case VCVTBF162IUBSZ128rmb:
19639 case VCVTBF162IUBSZ128rmbk:
19640 case VCVTBF162IUBSZ128rmbkz:
19641 case VCVTBF162IUBSZ128rmk:
19642 case VCVTBF162IUBSZ128rmkz:
19643 case VCVTBF162IUBSZ128rr:
19644 case VCVTBF162IUBSZ128rrk:
19645 case VCVTBF162IUBSZ128rrkz:
19646 case VCVTBF162IUBSZ256rm:
19647 case VCVTBF162IUBSZ256rmb:
19648 case VCVTBF162IUBSZ256rmbk:
19649 case VCVTBF162IUBSZ256rmbkz:
19650 case VCVTBF162IUBSZ256rmk:
19651 case VCVTBF162IUBSZ256rmkz:
19652 case VCVTBF162IUBSZ256rr:
19653 case VCVTBF162IUBSZ256rrk:
19654 case VCVTBF162IUBSZ256rrkz:
19655 case VCVTBF162IUBSZrm:
19656 case VCVTBF162IUBSZrmb:
19657 case VCVTBF162IUBSZrmbk:
19658 case VCVTBF162IUBSZrmbkz:
19659 case VCVTBF162IUBSZrmk:
19660 case VCVTBF162IUBSZrmkz:
19661 case VCVTBF162IUBSZrr:
19662 case VCVTBF162IUBSZrrk:
19663 case VCVTBF162IUBSZrrkz:
19664 return true;
19665 }
19666 return false;
19667}
19668
19669bool isVCVTSH2USI(unsigned Opcode) {
19670 switch (Opcode) {
19671 case VCVTSH2USI64Zrm_Int:
19672 case VCVTSH2USI64Zrr_Int:
19673 case VCVTSH2USI64Zrrb_Int:
19674 case VCVTSH2USIZrm_Int:
19675 case VCVTSH2USIZrr_Int:
19676 case VCVTSH2USIZrrb_Int:
19677 return true;
19678 }
19679 return false;
19680}
19681
19682bool isVANDPD(unsigned Opcode) {
19683 switch (Opcode) {
19684 case VANDPDYrm:
19685 case VANDPDYrr:
19686 case VANDPDZ128rm:
19687 case VANDPDZ128rmb:
19688 case VANDPDZ128rmbk:
19689 case VANDPDZ128rmbkz:
19690 case VANDPDZ128rmk:
19691 case VANDPDZ128rmkz:
19692 case VANDPDZ128rr:
19693 case VANDPDZ128rrk:
19694 case VANDPDZ128rrkz:
19695 case VANDPDZ256rm:
19696 case VANDPDZ256rmb:
19697 case VANDPDZ256rmbk:
19698 case VANDPDZ256rmbkz:
19699 case VANDPDZ256rmk:
19700 case VANDPDZ256rmkz:
19701 case VANDPDZ256rr:
19702 case VANDPDZ256rrk:
19703 case VANDPDZ256rrkz:
19704 case VANDPDZrm:
19705 case VANDPDZrmb:
19706 case VANDPDZrmbk:
19707 case VANDPDZrmbkz:
19708 case VANDPDZrmk:
19709 case VANDPDZrmkz:
19710 case VANDPDZrr:
19711 case VANDPDZrrk:
19712 case VANDPDZrrkz:
19713 case VANDPDrm:
19714 case VANDPDrr:
19715 return true;
19716 }
19717 return false;
19718}
19719
19720bool isBEXTR(unsigned Opcode) {
19721 switch (Opcode) {
19722 case BEXTR32rm:
19723 case BEXTR32rm_EVEX:
19724 case BEXTR32rm_NF:
19725 case BEXTR32rr:
19726 case BEXTR32rr_EVEX:
19727 case BEXTR32rr_NF:
19728 case BEXTR64rm:
19729 case BEXTR64rm_EVEX:
19730 case BEXTR64rm_NF:
19731 case BEXTR64rr:
19732 case BEXTR64rr_EVEX:
19733 case BEXTR64rr_NF:
19734 case BEXTRI32mi:
19735 case BEXTRI32ri:
19736 case BEXTRI64mi:
19737 case BEXTRI64ri:
19738 return true;
19739 }
19740 return false;
19741}
19742
19743bool isSTD(unsigned Opcode) {
19744 return Opcode == STD;
19745}
19746
19747bool isVAESKEYGENASSIST(unsigned Opcode) {
19748 switch (Opcode) {
19749 case VAESKEYGENASSISTrmi:
19750 case VAESKEYGENASSISTrri:
19751 return true;
19752 }
19753 return false;
19754}
19755
19756bool isCMPSD(unsigned Opcode) {
19757 switch (Opcode) {
19758 case CMPSDrmi_Int:
19759 case CMPSDrri_Int:
19760 case CMPSL:
19761 return true;
19762 }
19763 return false;
19764}
19765
19766bool isMOVSS(unsigned Opcode) {
19767 switch (Opcode) {
19768 case MOVSSmr:
19769 case MOVSSrm:
19770 case MOVSSrr:
19771 case MOVSSrr_REV:
19772 return true;
19773 }
19774 return false;
19775}
19776
19777bool isVCVTUQQ2PD(unsigned Opcode) {
19778 switch (Opcode) {
19779 case VCVTUQQ2PDZ128rm:
19780 case VCVTUQQ2PDZ128rmb:
19781 case VCVTUQQ2PDZ128rmbk:
19782 case VCVTUQQ2PDZ128rmbkz:
19783 case VCVTUQQ2PDZ128rmk:
19784 case VCVTUQQ2PDZ128rmkz:
19785 case VCVTUQQ2PDZ128rr:
19786 case VCVTUQQ2PDZ128rrk:
19787 case VCVTUQQ2PDZ128rrkz:
19788 case VCVTUQQ2PDZ256rm:
19789 case VCVTUQQ2PDZ256rmb:
19790 case VCVTUQQ2PDZ256rmbk:
19791 case VCVTUQQ2PDZ256rmbkz:
19792 case VCVTUQQ2PDZ256rmk:
19793 case VCVTUQQ2PDZ256rmkz:
19794 case VCVTUQQ2PDZ256rr:
19795 case VCVTUQQ2PDZ256rrk:
19796 case VCVTUQQ2PDZ256rrkz:
19797 case VCVTUQQ2PDZrm:
19798 case VCVTUQQ2PDZrmb:
19799 case VCVTUQQ2PDZrmbk:
19800 case VCVTUQQ2PDZrmbkz:
19801 case VCVTUQQ2PDZrmk:
19802 case VCVTUQQ2PDZrmkz:
19803 case VCVTUQQ2PDZrr:
19804 case VCVTUQQ2PDZrrb:
19805 case VCVTUQQ2PDZrrbk:
19806 case VCVTUQQ2PDZrrbkz:
19807 case VCVTUQQ2PDZrrk:
19808 case VCVTUQQ2PDZrrkz:
19809 return true;
19810 }
19811 return false;
19812}
19813
19814bool isVEXTRACTI32X4(unsigned Opcode) {
19815 switch (Opcode) {
19816 case VEXTRACTI32X4Z256mri:
19817 case VEXTRACTI32X4Z256mrik:
19818 case VEXTRACTI32X4Z256rri:
19819 case VEXTRACTI32X4Z256rrik:
19820 case VEXTRACTI32X4Z256rrikz:
19821 case VEXTRACTI32X4Zmri:
19822 case VEXTRACTI32X4Zmrik:
19823 case VEXTRACTI32X4Zrri:
19824 case VEXTRACTI32X4Zrrik:
19825 case VEXTRACTI32X4Zrrikz:
19826 return true;
19827 }
19828 return false;
19829}
19830
19831bool isFLDCW(unsigned Opcode) {
19832 return Opcode == FLDCW16m;
19833}
19834
19835bool isINSW(unsigned Opcode) {
19836 return Opcode == INSW;
19837}
19838
19839bool isRDPID(unsigned Opcode) {
19840 switch (Opcode) {
19841 case RDPID32:
19842 case RDPID64:
19843 return true;
19844 }
19845 return false;
19846}
19847
19848bool isVUCOMXSS(unsigned Opcode) {
19849 switch (Opcode) {
19850 case VUCOMXSSZrm_Int:
19851 case VUCOMXSSZrr_Int:
19852 case VUCOMXSSZrrb_Int:
19853 return true;
19854 }
19855 return false;
19856}
19857
19858bool isKANDQ(unsigned Opcode) {
19859 return Opcode == KANDQkk;
19860}
19861
19862bool isV4FMADDPS(unsigned Opcode) {
19863 switch (Opcode) {
19864 case V4FMADDPSrm:
19865 case V4FMADDPSrmk:
19866 case V4FMADDPSrmkz:
19867 return true;
19868 }
19869 return false;
19870}
19871
19872bool isPMOVZXWQ(unsigned Opcode) {
19873 switch (Opcode) {
19874 case PMOVZXWQrm:
19875 case PMOVZXWQrr:
19876 return true;
19877 }
19878 return false;
19879}
19880
19881bool isVFPCLASSSD(unsigned Opcode) {
19882 switch (Opcode) {
19883 case VFPCLASSSDZmi:
19884 case VFPCLASSSDZmik:
19885 case VFPCLASSSDZri:
19886 case VFPCLASSSDZrik:
19887 return true;
19888 }
19889 return false;
19890}
19891
19892bool isBLENDPS(unsigned Opcode) {
19893 switch (Opcode) {
19894 case BLENDPSrmi:
19895 case BLENDPSrri:
19896 return true;
19897 }
19898 return false;
19899}
19900
19901bool isVPACKSSDW(unsigned Opcode) {
19902 switch (Opcode) {
19903 case VPACKSSDWYrm:
19904 case VPACKSSDWYrr:
19905 case VPACKSSDWZ128rm:
19906 case VPACKSSDWZ128rmb:
19907 case VPACKSSDWZ128rmbk:
19908 case VPACKSSDWZ128rmbkz:
19909 case VPACKSSDWZ128rmk:
19910 case VPACKSSDWZ128rmkz:
19911 case VPACKSSDWZ128rr:
19912 case VPACKSSDWZ128rrk:
19913 case VPACKSSDWZ128rrkz:
19914 case VPACKSSDWZ256rm:
19915 case VPACKSSDWZ256rmb:
19916 case VPACKSSDWZ256rmbk:
19917 case VPACKSSDWZ256rmbkz:
19918 case VPACKSSDWZ256rmk:
19919 case VPACKSSDWZ256rmkz:
19920 case VPACKSSDWZ256rr:
19921 case VPACKSSDWZ256rrk:
19922 case VPACKSSDWZ256rrkz:
19923 case VPACKSSDWZrm:
19924 case VPACKSSDWZrmb:
19925 case VPACKSSDWZrmbk:
19926 case VPACKSSDWZrmbkz:
19927 case VPACKSSDWZrmk:
19928 case VPACKSSDWZrmkz:
19929 case VPACKSSDWZrr:
19930 case VPACKSSDWZrrk:
19931 case VPACKSSDWZrrkz:
19932 case VPACKSSDWrm:
19933 case VPACKSSDWrr:
19934 return true;
19935 }
19936 return false;
19937}
19938
19939bool isVPINSRW(unsigned Opcode) {
19940 switch (Opcode) {
19941 case VPINSRWZrmi:
19942 case VPINSRWZrri:
19943 case VPINSRWrmi:
19944 case VPINSRWrri:
19945 return true;
19946 }
19947 return false;
19948}
19949
19950bool isFXAM(unsigned Opcode) {
19951 return Opcode == XAM_F;
19952}
19953
19954bool isVMINMAXBF16(unsigned Opcode) {
19955 switch (Opcode) {
19956 case VMINMAXBF16Z128rmbi:
19957 case VMINMAXBF16Z128rmbik:
19958 case VMINMAXBF16Z128rmbikz:
19959 case VMINMAXBF16Z128rmi:
19960 case VMINMAXBF16Z128rmik:
19961 case VMINMAXBF16Z128rmikz:
19962 case VMINMAXBF16Z128rri:
19963 case VMINMAXBF16Z128rrik:
19964 case VMINMAXBF16Z128rrikz:
19965 case VMINMAXBF16Z256rmbi:
19966 case VMINMAXBF16Z256rmbik:
19967 case VMINMAXBF16Z256rmbikz:
19968 case VMINMAXBF16Z256rmi:
19969 case VMINMAXBF16Z256rmik:
19970 case VMINMAXBF16Z256rmikz:
19971 case VMINMAXBF16Z256rri:
19972 case VMINMAXBF16Z256rrik:
19973 case VMINMAXBF16Z256rrikz:
19974 case VMINMAXBF16Zrmbi:
19975 case VMINMAXBF16Zrmbik:
19976 case VMINMAXBF16Zrmbikz:
19977 case VMINMAXBF16Zrmi:
19978 case VMINMAXBF16Zrmik:
19979 case VMINMAXBF16Zrmikz:
19980 case VMINMAXBF16Zrri:
19981 case VMINMAXBF16Zrrik:
19982 case VMINMAXBF16Zrrikz:
19983 return true;
19984 }
19985 return false;
19986}
19987
19988bool isVSHUFF64X2(unsigned Opcode) {
19989 switch (Opcode) {
19990 case VSHUFF64X2Z256rmbi:
19991 case VSHUFF64X2Z256rmbik:
19992 case VSHUFF64X2Z256rmbikz:
19993 case VSHUFF64X2Z256rmi:
19994 case VSHUFF64X2Z256rmik:
19995 case VSHUFF64X2Z256rmikz:
19996 case VSHUFF64X2Z256rri:
19997 case VSHUFF64X2Z256rrik:
19998 case VSHUFF64X2Z256rrikz:
19999 case VSHUFF64X2Zrmbi:
20000 case VSHUFF64X2Zrmbik:
20001 case VSHUFF64X2Zrmbikz:
20002 case VSHUFF64X2Zrmi:
20003 case VSHUFF64X2Zrmik:
20004 case VSHUFF64X2Zrmikz:
20005 case VSHUFF64X2Zrri:
20006 case VSHUFF64X2Zrrik:
20007 case VSHUFF64X2Zrrikz:
20008 return true;
20009 }
20010 return false;
20011}
20012
20013bool isVPACKUSWB(unsigned Opcode) {
20014 switch (Opcode) {
20015 case VPACKUSWBYrm:
20016 case VPACKUSWBYrr:
20017 case VPACKUSWBZ128rm:
20018 case VPACKUSWBZ128rmk:
20019 case VPACKUSWBZ128rmkz:
20020 case VPACKUSWBZ128rr:
20021 case VPACKUSWBZ128rrk:
20022 case VPACKUSWBZ128rrkz:
20023 case VPACKUSWBZ256rm:
20024 case VPACKUSWBZ256rmk:
20025 case VPACKUSWBZ256rmkz:
20026 case VPACKUSWBZ256rr:
20027 case VPACKUSWBZ256rrk:
20028 case VPACKUSWBZ256rrkz:
20029 case VPACKUSWBZrm:
20030 case VPACKUSWBZrmk:
20031 case VPACKUSWBZrmkz:
20032 case VPACKUSWBZrr:
20033 case VPACKUSWBZrrk:
20034 case VPACKUSWBZrrkz:
20035 case VPACKUSWBrm:
20036 case VPACKUSWBrr:
20037 return true;
20038 }
20039 return false;
20040}
20041
20042bool isVRSQRT28SS(unsigned Opcode) {
20043 switch (Opcode) {
20044 case VRSQRT28SSZm:
20045 case VRSQRT28SSZmk:
20046 case VRSQRT28SSZmkz:
20047 case VRSQRT28SSZr:
20048 case VRSQRT28SSZrb:
20049 case VRSQRT28SSZrbk:
20050 case VRSQRT28SSZrbkz:
20051 case VRSQRT28SSZrk:
20052 case VRSQRT28SSZrkz:
20053 return true;
20054 }
20055 return false;
20056}
20057
20058bool isGETSEC(unsigned Opcode) {
20059 return Opcode == GETSEC;
20060}
20061
20062bool isVEXTRACTF64X4(unsigned Opcode) {
20063 switch (Opcode) {
20064 case VEXTRACTF64X4Zmri:
20065 case VEXTRACTF64X4Zmrik:
20066 case VEXTRACTF64X4Zrri:
20067 case VEXTRACTF64X4Zrrik:
20068 case VEXTRACTF64X4Zrrikz:
20069 return true;
20070 }
20071 return false;
20072}
20073
20074bool isVPHSUBBW(unsigned Opcode) {
20075 switch (Opcode) {
20076 case VPHSUBBWrm:
20077 case VPHSUBBWrr:
20078 return true;
20079 }
20080 return false;
20081}
20082
20083bool isBLSR(unsigned Opcode) {
20084 switch (Opcode) {
20085 case BLSR32rm:
20086 case BLSR32rm_EVEX:
20087 case BLSR32rm_NF:
20088 case BLSR32rr:
20089 case BLSR32rr_EVEX:
20090 case BLSR32rr_NF:
20091 case BLSR64rm:
20092 case BLSR64rm_EVEX:
20093 case BLSR64rm_NF:
20094 case BLSR64rr:
20095 case BLSR64rr_EVEX:
20096 case BLSR64rr_NF:
20097 return true;
20098 }
20099 return false;
20100}
20101
20102bool isFILD(unsigned Opcode) {
20103 switch (Opcode) {
20104 case ILD_F16m:
20105 case ILD_F32m:
20106 case ILD_F64m:
20107 return true;
20108 }
20109 return false;
20110}
20111
20112bool isRETFQ(unsigned Opcode) {
20113 switch (Opcode) {
20114 case LRET64:
20115 case LRETI64:
20116 return true;
20117 }
20118 return false;
20119}
20120
20121bool isVADDSS(unsigned Opcode) {
20122 switch (Opcode) {
20123 case VADDSSZrm_Int:
20124 case VADDSSZrmk_Int:
20125 case VADDSSZrmkz_Int:
20126 case VADDSSZrr_Int:
20127 case VADDSSZrrb_Int:
20128 case VADDSSZrrbk_Int:
20129 case VADDSSZrrbkz_Int:
20130 case VADDSSZrrk_Int:
20131 case VADDSSZrrkz_Int:
20132 case VADDSSrm_Int:
20133 case VADDSSrr_Int:
20134 return true;
20135 }
20136 return false;
20137}
20138
20139bool isCOMISS(unsigned Opcode) {
20140 switch (Opcode) {
20141 case COMISSrm:
20142 case COMISSrr:
20143 return true;
20144 }
20145 return false;
20146}
20147
20148bool isCLI(unsigned Opcode) {
20149 return Opcode == CLI;
20150}
20151
20152bool isVERW(unsigned Opcode) {
20153 switch (Opcode) {
20154 case VERWm:
20155 case VERWr:
20156 return true;
20157 }
20158 return false;
20159}
20160
20161bool isBTC(unsigned Opcode) {
20162 switch (Opcode) {
20163 case BTC16mi8:
20164 case BTC16mr:
20165 case BTC16ri8:
20166 case BTC16rr:
20167 case BTC32mi8:
20168 case BTC32mr:
20169 case BTC32ri8:
20170 case BTC32rr:
20171 case BTC64mi8:
20172 case BTC64mr:
20173 case BTC64ri8:
20174 case BTC64rr:
20175 return true;
20176 }
20177 return false;
20178}
20179
20180bool isVPHADDUBQ(unsigned Opcode) {
20181 switch (Opcode) {
20182 case VPHADDUBQrm:
20183 case VPHADDUBQrr:
20184 return true;
20185 }
20186 return false;
20187}
20188
20189bool isVPORQ(unsigned Opcode) {
20190 switch (Opcode) {
20191 case VPORQZ128rm:
20192 case VPORQZ128rmb:
20193 case VPORQZ128rmbk:
20194 case VPORQZ128rmbkz:
20195 case VPORQZ128rmk:
20196 case VPORQZ128rmkz:
20197 case VPORQZ128rr:
20198 case VPORQZ128rrk:
20199 case VPORQZ128rrkz:
20200 case VPORQZ256rm:
20201 case VPORQZ256rmb:
20202 case VPORQZ256rmbk:
20203 case VPORQZ256rmbkz:
20204 case VPORQZ256rmk:
20205 case VPORQZ256rmkz:
20206 case VPORQZ256rr:
20207 case VPORQZ256rrk:
20208 case VPORQZ256rrkz:
20209 case VPORQZrm:
20210 case VPORQZrmb:
20211 case VPORQZrmbk:
20212 case VPORQZrmbkz:
20213 case VPORQZrmk:
20214 case VPORQZrmkz:
20215 case VPORQZrr:
20216 case VPORQZrrk:
20217 case VPORQZrrkz:
20218 return true;
20219 }
20220 return false;
20221}
20222
20223bool isORPD(unsigned Opcode) {
20224 switch (Opcode) {
20225 case ORPDrm:
20226 case ORPDrr:
20227 return true;
20228 }
20229 return false;
20230}
20231
20232bool isVMOVSS(unsigned Opcode) {
20233 switch (Opcode) {
20234 case VMOVSSZmr:
20235 case VMOVSSZmrk:
20236 case VMOVSSZrm:
20237 case VMOVSSZrmk:
20238 case VMOVSSZrmkz:
20239 case VMOVSSZrr:
20240 case VMOVSSZrr_REV:
20241 case VMOVSSZrrk:
20242 case VMOVSSZrrk_REV:
20243 case VMOVSSZrrkz:
20244 case VMOVSSZrrkz_REV:
20245 case VMOVSSmr:
20246 case VMOVSSrm:
20247 case VMOVSSrr:
20248 case VMOVSSrr_REV:
20249 return true;
20250 }
20251 return false;
20252}
20253
20254bool isVPSUBD(unsigned Opcode) {
20255 switch (Opcode) {
20256 case VPSUBDYrm:
20257 case VPSUBDYrr:
20258 case VPSUBDZ128rm:
20259 case VPSUBDZ128rmb:
20260 case VPSUBDZ128rmbk:
20261 case VPSUBDZ128rmbkz:
20262 case VPSUBDZ128rmk:
20263 case VPSUBDZ128rmkz:
20264 case VPSUBDZ128rr:
20265 case VPSUBDZ128rrk:
20266 case VPSUBDZ128rrkz:
20267 case VPSUBDZ256rm:
20268 case VPSUBDZ256rmb:
20269 case VPSUBDZ256rmbk:
20270 case VPSUBDZ256rmbkz:
20271 case VPSUBDZ256rmk:
20272 case VPSUBDZ256rmkz:
20273 case VPSUBDZ256rr:
20274 case VPSUBDZ256rrk:
20275 case VPSUBDZ256rrkz:
20276 case VPSUBDZrm:
20277 case VPSUBDZrmb:
20278 case VPSUBDZrmbk:
20279 case VPSUBDZrmbkz:
20280 case VPSUBDZrmk:
20281 case VPSUBDZrmkz:
20282 case VPSUBDZrr:
20283 case VPSUBDZrrk:
20284 case VPSUBDZrrkz:
20285 case VPSUBDrm:
20286 case VPSUBDrr:
20287 return true;
20288 }
20289 return false;
20290}
20291
20292bool isVGATHERPF1QPD(unsigned Opcode) {
20293 return Opcode == VGATHERPF1QPDm;
20294}
20295
20296bool isENCODEKEY256(unsigned Opcode) {
20297 return Opcode == ENCODEKEY256;
20298}
20299
20300bool isGF2P8AFFINEINVQB(unsigned Opcode) {
20301 switch (Opcode) {
20302 case GF2P8AFFINEINVQBrmi:
20303 case GF2P8AFFINEINVQBrri:
20304 return true;
20305 }
20306 return false;
20307}
20308
20309bool isXRSTOR64(unsigned Opcode) {
20310 return Opcode == XRSTOR64;
20311}
20312
20313bool isKANDW(unsigned Opcode) {
20314 return Opcode == KANDWkk;
20315}
20316
20317bool isLODSQ(unsigned Opcode) {
20318 return Opcode == LODSQ;
20319}
20320
20321bool isVMOVRSW(unsigned Opcode) {
20322 switch (Opcode) {
20323 case VMOVRSWZ128m:
20324 case VMOVRSWZ128mk:
20325 case VMOVRSWZ128mkz:
20326 case VMOVRSWZ256m:
20327 case VMOVRSWZ256mk:
20328 case VMOVRSWZ256mkz:
20329 case VMOVRSWZm:
20330 case VMOVRSWZmk:
20331 case VMOVRSWZmkz:
20332 return true;
20333 }
20334 return false;
20335}
20336
20337bool isVSUBSH(unsigned Opcode) {
20338 switch (Opcode) {
20339 case VSUBSHZrm_Int:
20340 case VSUBSHZrmk_Int:
20341 case VSUBSHZrmkz_Int:
20342 case VSUBSHZrr_Int:
20343 case VSUBSHZrrb_Int:
20344 case VSUBSHZrrbk_Int:
20345 case VSUBSHZrrbkz_Int:
20346 case VSUBSHZrrk_Int:
20347 case VSUBSHZrrkz_Int:
20348 return true;
20349 }
20350 return false;
20351}
20352
20353bool isLSS(unsigned Opcode) {
20354 switch (Opcode) {
20355 case LSS16rm:
20356 case LSS32rm:
20357 case LSS64rm:
20358 return true;
20359 }
20360 return false;
20361}
20362
20363bool isPMOVSXBQ(unsigned Opcode) {
20364 switch (Opcode) {
20365 case PMOVSXBQrm:
20366 case PMOVSXBQrr:
20367 return true;
20368 }
20369 return false;
20370}
20371
20372bool isVCVTTSD2SIS(unsigned Opcode) {
20373 switch (Opcode) {
20374 case VCVTTSD2SI64Srm_Int:
20375 case VCVTTSD2SI64Srr_Int:
20376 case VCVTTSD2SI64Srrb_Int:
20377 case VCVTTSD2SISrm_Int:
20378 case VCVTTSD2SISrr_Int:
20379 case VCVTTSD2SISrrb_Int:
20380 return true;
20381 }
20382 return false;
20383}
20384
20385bool isVCMPSH(unsigned Opcode) {
20386 switch (Opcode) {
20387 case VCMPSHZrmi_Int:
20388 case VCMPSHZrmik_Int:
20389 case VCMPSHZrri_Int:
20390 case VCMPSHZrrib_Int:
20391 case VCMPSHZrribk_Int:
20392 case VCMPSHZrrik_Int:
20393 return true;
20394 }
20395 return false;
20396}
20397
20398bool isVFMADD132PS(unsigned Opcode) {
20399 switch (Opcode) {
20400 case VFMADD132PSYm:
20401 case VFMADD132PSYr:
20402 case VFMADD132PSZ128m:
20403 case VFMADD132PSZ128mb:
20404 case VFMADD132PSZ128mbk:
20405 case VFMADD132PSZ128mbkz:
20406 case VFMADD132PSZ128mk:
20407 case VFMADD132PSZ128mkz:
20408 case VFMADD132PSZ128r:
20409 case VFMADD132PSZ128rk:
20410 case VFMADD132PSZ128rkz:
20411 case VFMADD132PSZ256m:
20412 case VFMADD132PSZ256mb:
20413 case VFMADD132PSZ256mbk:
20414 case VFMADD132PSZ256mbkz:
20415 case VFMADD132PSZ256mk:
20416 case VFMADD132PSZ256mkz:
20417 case VFMADD132PSZ256r:
20418 case VFMADD132PSZ256rk:
20419 case VFMADD132PSZ256rkz:
20420 case VFMADD132PSZm:
20421 case VFMADD132PSZmb:
20422 case VFMADD132PSZmbk:
20423 case VFMADD132PSZmbkz:
20424 case VFMADD132PSZmk:
20425 case VFMADD132PSZmkz:
20426 case VFMADD132PSZr:
20427 case VFMADD132PSZrb:
20428 case VFMADD132PSZrbk:
20429 case VFMADD132PSZrbkz:
20430 case VFMADD132PSZrk:
20431 case VFMADD132PSZrkz:
20432 case VFMADD132PSm:
20433 case VFMADD132PSr:
20434 return true;
20435 }
20436 return false;
20437}
20438
20439bool isVPACKSSWB(unsigned Opcode) {
20440 switch (Opcode) {
20441 case VPACKSSWBYrm:
20442 case VPACKSSWBYrr:
20443 case VPACKSSWBZ128rm:
20444 case VPACKSSWBZ128rmk:
20445 case VPACKSSWBZ128rmkz:
20446 case VPACKSSWBZ128rr:
20447 case VPACKSSWBZ128rrk:
20448 case VPACKSSWBZ128rrkz:
20449 case VPACKSSWBZ256rm:
20450 case VPACKSSWBZ256rmk:
20451 case VPACKSSWBZ256rmkz:
20452 case VPACKSSWBZ256rr:
20453 case VPACKSSWBZ256rrk:
20454 case VPACKSSWBZ256rrkz:
20455 case VPACKSSWBZrm:
20456 case VPACKSSWBZrmk:
20457 case VPACKSSWBZrmkz:
20458 case VPACKSSWBZrr:
20459 case VPACKSSWBZrrk:
20460 case VPACKSSWBZrrkz:
20461 case VPACKSSWBrm:
20462 case VPACKSSWBrr:
20463 return true;
20464 }
20465 return false;
20466}
20467
20468bool isPCMPGTQ(unsigned Opcode) {
20469 switch (Opcode) {
20470 case PCMPGTQrm:
20471 case PCMPGTQrr:
20472 return true;
20473 }
20474 return false;
20475}
20476
20477bool isVFMADD132SH(unsigned Opcode) {
20478 switch (Opcode) {
20479 case VFMADD132SHZm_Int:
20480 case VFMADD132SHZmk_Int:
20481 case VFMADD132SHZmkz_Int:
20482 case VFMADD132SHZr_Int:
20483 case VFMADD132SHZrb_Int:
20484 case VFMADD132SHZrbk_Int:
20485 case VFMADD132SHZrbkz_Int:
20486 case VFMADD132SHZrk_Int:
20487 case VFMADD132SHZrkz_Int:
20488 return true;
20489 }
20490 return false;
20491}
20492
20493bool isVCVTUQQ2PH(unsigned Opcode) {
20494 switch (Opcode) {
20495 case VCVTUQQ2PHZ128rm:
20496 case VCVTUQQ2PHZ128rmb:
20497 case VCVTUQQ2PHZ128rmbk:
20498 case VCVTUQQ2PHZ128rmbkz:
20499 case VCVTUQQ2PHZ128rmk:
20500 case VCVTUQQ2PHZ128rmkz:
20501 case VCVTUQQ2PHZ128rr:
20502 case VCVTUQQ2PHZ128rrk:
20503 case VCVTUQQ2PHZ128rrkz:
20504 case VCVTUQQ2PHZ256rm:
20505 case VCVTUQQ2PHZ256rmb:
20506 case VCVTUQQ2PHZ256rmbk:
20507 case VCVTUQQ2PHZ256rmbkz:
20508 case VCVTUQQ2PHZ256rmk:
20509 case VCVTUQQ2PHZ256rmkz:
20510 case VCVTUQQ2PHZ256rr:
20511 case VCVTUQQ2PHZ256rrk:
20512 case VCVTUQQ2PHZ256rrkz:
20513 case VCVTUQQ2PHZrm:
20514 case VCVTUQQ2PHZrmb:
20515 case VCVTUQQ2PHZrmbk:
20516 case VCVTUQQ2PHZrmbkz:
20517 case VCVTUQQ2PHZrmk:
20518 case VCVTUQQ2PHZrmkz:
20519 case VCVTUQQ2PHZrr:
20520 case VCVTUQQ2PHZrrb:
20521 case VCVTUQQ2PHZrrbk:
20522 case VCVTUQQ2PHZrrbkz:
20523 case VCVTUQQ2PHZrrk:
20524 case VCVTUQQ2PHZrrkz:
20525 return true;
20526 }
20527 return false;
20528}
20529
20530bool isVCVTQQ2PS(unsigned Opcode) {
20531 switch (Opcode) {
20532 case VCVTQQ2PSZ128rm:
20533 case VCVTQQ2PSZ128rmb:
20534 case VCVTQQ2PSZ128rmbk:
20535 case VCVTQQ2PSZ128rmbkz:
20536 case VCVTQQ2PSZ128rmk:
20537 case VCVTQQ2PSZ128rmkz:
20538 case VCVTQQ2PSZ128rr:
20539 case VCVTQQ2PSZ128rrk:
20540 case VCVTQQ2PSZ128rrkz:
20541 case VCVTQQ2PSZ256rm:
20542 case VCVTQQ2PSZ256rmb:
20543 case VCVTQQ2PSZ256rmbk:
20544 case VCVTQQ2PSZ256rmbkz:
20545 case VCVTQQ2PSZ256rmk:
20546 case VCVTQQ2PSZ256rmkz:
20547 case VCVTQQ2PSZ256rr:
20548 case VCVTQQ2PSZ256rrk:
20549 case VCVTQQ2PSZ256rrkz:
20550 case VCVTQQ2PSZrm:
20551 case VCVTQQ2PSZrmb:
20552 case VCVTQQ2PSZrmbk:
20553 case VCVTQQ2PSZrmbkz:
20554 case VCVTQQ2PSZrmk:
20555 case VCVTQQ2PSZrmkz:
20556 case VCVTQQ2PSZrr:
20557 case VCVTQQ2PSZrrb:
20558 case VCVTQQ2PSZrrbk:
20559 case VCVTQQ2PSZrrbkz:
20560 case VCVTQQ2PSZrrk:
20561 case VCVTQQ2PSZrrkz:
20562 return true;
20563 }
20564 return false;
20565}
20566
20567bool isVCVTTSS2USI(unsigned Opcode) {
20568 switch (Opcode) {
20569 case VCVTTSS2USI64Zrm_Int:
20570 case VCVTTSS2USI64Zrr_Int:
20571 case VCVTTSS2USI64Zrrb_Int:
20572 case VCVTTSS2USIZrm_Int:
20573 case VCVTTSS2USIZrr_Int:
20574 case VCVTTSS2USIZrrb_Int:
20575 return true;
20576 }
20577 return false;
20578}
20579
20580bool isVPMOVM2Q(unsigned Opcode) {
20581 switch (Opcode) {
20582 case VPMOVM2QZ128rk:
20583 case VPMOVM2QZ256rk:
20584 case VPMOVM2QZrk:
20585 return true;
20586 }
20587 return false;
20588}
20589
20590bool isVMOVD(unsigned Opcode) {
20591 switch (Opcode) {
20592 case VMOVDI2PDIZrm:
20593 case VMOVDI2PDIZrr:
20594 case VMOVDI2PDIrm:
20595 case VMOVDI2PDIrr:
20596 case VMOVPDI2DIZmr:
20597 case VMOVPDI2DIZrr:
20598 case VMOVPDI2DImr:
20599 case VMOVPDI2DIrr:
20600 case VMOVZPDILo2PDIZmr:
20601 case VMOVZPDILo2PDIZrm:
20602 case VMOVZPDILo2PDIZrr:
20603 case VMOVZPDILo2PDIZrr2:
20604 return true;
20605 }
20606 return false;
20607}
20608
20609bool isVCVTTPS2QQS(unsigned Opcode) {
20610 switch (Opcode) {
20611 case VCVTTPS2QQSZ128rm:
20612 case VCVTTPS2QQSZ128rmb:
20613 case VCVTTPS2QQSZ128rmbk:
20614 case VCVTTPS2QQSZ128rmbkz:
20615 case VCVTTPS2QQSZ128rmk:
20616 case VCVTTPS2QQSZ128rmkz:
20617 case VCVTTPS2QQSZ128rr:
20618 case VCVTTPS2QQSZ128rrk:
20619 case VCVTTPS2QQSZ128rrkz:
20620 case VCVTTPS2QQSZ256rm:
20621 case VCVTTPS2QQSZ256rmb:
20622 case VCVTTPS2QQSZ256rmbk:
20623 case VCVTTPS2QQSZ256rmbkz:
20624 case VCVTTPS2QQSZ256rmk:
20625 case VCVTTPS2QQSZ256rmkz:
20626 case VCVTTPS2QQSZ256rr:
20627 case VCVTTPS2QQSZ256rrb:
20628 case VCVTTPS2QQSZ256rrbk:
20629 case VCVTTPS2QQSZ256rrbkz:
20630 case VCVTTPS2QQSZ256rrk:
20631 case VCVTTPS2QQSZ256rrkz:
20632 case VCVTTPS2QQSZrm:
20633 case VCVTTPS2QQSZrmb:
20634 case VCVTTPS2QQSZrmbk:
20635 case VCVTTPS2QQSZrmbkz:
20636 case VCVTTPS2QQSZrmk:
20637 case VCVTTPS2QQSZrmkz:
20638 case VCVTTPS2QQSZrr:
20639 case VCVTTPS2QQSZrrb:
20640 case VCVTTPS2QQSZrrbk:
20641 case VCVTTPS2QQSZrrbkz:
20642 case VCVTTPS2QQSZrrk:
20643 case VCVTTPS2QQSZrrkz:
20644 return true;
20645 }
20646 return false;
20647}
20648
20649bool isVSQRTBF16(unsigned Opcode) {
20650 switch (Opcode) {
20651 case VSQRTBF16Z128m:
20652 case VSQRTBF16Z128mb:
20653 case VSQRTBF16Z128mbk:
20654 case VSQRTBF16Z128mbkz:
20655 case VSQRTBF16Z128mk:
20656 case VSQRTBF16Z128mkz:
20657 case VSQRTBF16Z128r:
20658 case VSQRTBF16Z128rk:
20659 case VSQRTBF16Z128rkz:
20660 case VSQRTBF16Z256m:
20661 case VSQRTBF16Z256mb:
20662 case VSQRTBF16Z256mbk:
20663 case VSQRTBF16Z256mbkz:
20664 case VSQRTBF16Z256mk:
20665 case VSQRTBF16Z256mkz:
20666 case VSQRTBF16Z256r:
20667 case VSQRTBF16Z256rk:
20668 case VSQRTBF16Z256rkz:
20669 case VSQRTBF16Zm:
20670 case VSQRTBF16Zmb:
20671 case VSQRTBF16Zmbk:
20672 case VSQRTBF16Zmbkz:
20673 case VSQRTBF16Zmk:
20674 case VSQRTBF16Zmkz:
20675 case VSQRTBF16Zr:
20676 case VSQRTBF16Zrk:
20677 case VSQRTBF16Zrkz:
20678 return true;
20679 }
20680 return false;
20681}
20682
20683bool isVFPCLASSPH(unsigned Opcode) {
20684 switch (Opcode) {
20685 case VFPCLASSPHZ128mbi:
20686 case VFPCLASSPHZ128mbik:
20687 case VFPCLASSPHZ128mi:
20688 case VFPCLASSPHZ128mik:
20689 case VFPCLASSPHZ128ri:
20690 case VFPCLASSPHZ128rik:
20691 case VFPCLASSPHZ256mbi:
20692 case VFPCLASSPHZ256mbik:
20693 case VFPCLASSPHZ256mi:
20694 case VFPCLASSPHZ256mik:
20695 case VFPCLASSPHZ256ri:
20696 case VFPCLASSPHZ256rik:
20697 case VFPCLASSPHZmbi:
20698 case VFPCLASSPHZmbik:
20699 case VFPCLASSPHZmi:
20700 case VFPCLASSPHZmik:
20701 case VFPCLASSPHZri:
20702 case VFPCLASSPHZrik:
20703 return true;
20704 }
20705 return false;
20706}
20707
20708bool isVCVTSS2SH(unsigned Opcode) {
20709 switch (Opcode) {
20710 case VCVTSS2SHZrm_Int:
20711 case VCVTSS2SHZrmk_Int:
20712 case VCVTSS2SHZrmkz_Int:
20713 case VCVTSS2SHZrr_Int:
20714 case VCVTSS2SHZrrb_Int:
20715 case VCVTSS2SHZrrbk_Int:
20716 case VCVTSS2SHZrrbkz_Int:
20717 case VCVTSS2SHZrrk_Int:
20718 case VCVTSS2SHZrrkz_Int:
20719 return true;
20720 }
20721 return false;
20722}
20723
20724bool isSCASB(unsigned Opcode) {
20725 return Opcode == SCASB;
20726}
20727
20728bool isPSRLD(unsigned Opcode) {
20729 switch (Opcode) {
20730 case MMX_PSRLDri:
20731 case MMX_PSRLDrm:
20732 case MMX_PSRLDrr:
20733 case PSRLDri:
20734 case PSRLDrm:
20735 case PSRLDrr:
20736 return true;
20737 }
20738 return false;
20739}
20740
20741bool isVADDPH(unsigned Opcode) {
20742 switch (Opcode) {
20743 case VADDPHZ128rm:
20744 case VADDPHZ128rmb:
20745 case VADDPHZ128rmbk:
20746 case VADDPHZ128rmbkz:
20747 case VADDPHZ128rmk:
20748 case VADDPHZ128rmkz:
20749 case VADDPHZ128rr:
20750 case VADDPHZ128rrk:
20751 case VADDPHZ128rrkz:
20752 case VADDPHZ256rm:
20753 case VADDPHZ256rmb:
20754 case VADDPHZ256rmbk:
20755 case VADDPHZ256rmbkz:
20756 case VADDPHZ256rmk:
20757 case VADDPHZ256rmkz:
20758 case VADDPHZ256rr:
20759 case VADDPHZ256rrk:
20760 case VADDPHZ256rrkz:
20761 case VADDPHZrm:
20762 case VADDPHZrmb:
20763 case VADDPHZrmbk:
20764 case VADDPHZrmbkz:
20765 case VADDPHZrmk:
20766 case VADDPHZrmkz:
20767 case VADDPHZrr:
20768 case VADDPHZrrb:
20769 case VADDPHZrrbk:
20770 case VADDPHZrrbkz:
20771 case VADDPHZrrk:
20772 case VADDPHZrrkz:
20773 return true;
20774 }
20775 return false;
20776}
20777
20778bool isFSUB(unsigned Opcode) {
20779 switch (Opcode) {
20780 case SUB_F32m:
20781 case SUB_F64m:
20782 case SUB_FST0r:
20783 case SUB_FrST0:
20784 return true;
20785 }
20786 return false;
20787}
20788
20789bool isVCVTTPH2IBS(unsigned Opcode) {
20790 switch (Opcode) {
20791 case VCVTTPH2IBSZ128rm:
20792 case VCVTTPH2IBSZ128rmb:
20793 case VCVTTPH2IBSZ128rmbk:
20794 case VCVTTPH2IBSZ128rmbkz:
20795 case VCVTTPH2IBSZ128rmk:
20796 case VCVTTPH2IBSZ128rmkz:
20797 case VCVTTPH2IBSZ128rr:
20798 case VCVTTPH2IBSZ128rrk:
20799 case VCVTTPH2IBSZ128rrkz:
20800 case VCVTTPH2IBSZ256rm:
20801 case VCVTTPH2IBSZ256rmb:
20802 case VCVTTPH2IBSZ256rmbk:
20803 case VCVTTPH2IBSZ256rmbkz:
20804 case VCVTTPH2IBSZ256rmk:
20805 case VCVTTPH2IBSZ256rmkz:
20806 case VCVTTPH2IBSZ256rr:
20807 case VCVTTPH2IBSZ256rrk:
20808 case VCVTTPH2IBSZ256rrkz:
20809 case VCVTTPH2IBSZrm:
20810 case VCVTTPH2IBSZrmb:
20811 case VCVTTPH2IBSZrmbk:
20812 case VCVTTPH2IBSZrmbkz:
20813 case VCVTTPH2IBSZrmk:
20814 case VCVTTPH2IBSZrmkz:
20815 case VCVTTPH2IBSZrr:
20816 case VCVTTPH2IBSZrrb:
20817 case VCVTTPH2IBSZrrbk:
20818 case VCVTTPH2IBSZrrbkz:
20819 case VCVTTPH2IBSZrrk:
20820 case VCVTTPH2IBSZrrkz:
20821 return true;
20822 }
20823 return false;
20824}
20825
20826bool isVEXTRACTI64X2(unsigned Opcode) {
20827 switch (Opcode) {
20828 case VEXTRACTI64X2Z256mri:
20829 case VEXTRACTI64X2Z256mrik:
20830 case VEXTRACTI64X2Z256rri:
20831 case VEXTRACTI64X2Z256rrik:
20832 case VEXTRACTI64X2Z256rrikz:
20833 case VEXTRACTI64X2Zmri:
20834 case VEXTRACTI64X2Zmrik:
20835 case VEXTRACTI64X2Zrri:
20836 case VEXTRACTI64X2Zrrik:
20837 case VEXTRACTI64X2Zrrikz:
20838 return true;
20839 }
20840 return false;
20841}
20842
20843bool isPMINUW(unsigned Opcode) {
20844 switch (Opcode) {
20845 case PMINUWrm:
20846 case PMINUWrr:
20847 return true;
20848 }
20849 return false;
20850}
20851
20852bool isPSUBSB(unsigned Opcode) {
20853 switch (Opcode) {
20854 case MMX_PSUBSBrm:
20855 case MMX_PSUBSBrr:
20856 case PSUBSBrm:
20857 case PSUBSBrr:
20858 return true;
20859 }
20860 return false;
20861}
20862
20863bool isVCVT2PS2PHX(unsigned Opcode) {
20864 switch (Opcode) {
20865 case VCVT2PS2PHXZ128rm:
20866 case VCVT2PS2PHXZ128rmb:
20867 case VCVT2PS2PHXZ128rmbk:
20868 case VCVT2PS2PHXZ128rmbkz:
20869 case VCVT2PS2PHXZ128rmk:
20870 case VCVT2PS2PHXZ128rmkz:
20871 case VCVT2PS2PHXZ128rr:
20872 case VCVT2PS2PHXZ128rrk:
20873 case VCVT2PS2PHXZ128rrkz:
20874 case VCVT2PS2PHXZ256rm:
20875 case VCVT2PS2PHXZ256rmb:
20876 case VCVT2PS2PHXZ256rmbk:
20877 case VCVT2PS2PHXZ256rmbkz:
20878 case VCVT2PS2PHXZ256rmk:
20879 case VCVT2PS2PHXZ256rmkz:
20880 case VCVT2PS2PHXZ256rr:
20881 case VCVT2PS2PHXZ256rrk:
20882 case VCVT2PS2PHXZ256rrkz:
20883 case VCVT2PS2PHXZrm:
20884 case VCVT2PS2PHXZrmb:
20885 case VCVT2PS2PHXZrmbk:
20886 case VCVT2PS2PHXZrmbkz:
20887 case VCVT2PS2PHXZrmk:
20888 case VCVT2PS2PHXZrmkz:
20889 case VCVT2PS2PHXZrr:
20890 case VCVT2PS2PHXZrrb:
20891 case VCVT2PS2PHXZrrbk:
20892 case VCVT2PS2PHXZrrbkz:
20893 case VCVT2PS2PHXZrrk:
20894 case VCVT2PS2PHXZrrkz:
20895 return true;
20896 }
20897 return false;
20898}
20899
20900bool isVPCMPEQD(unsigned Opcode) {
20901 switch (Opcode) {
20902 case VPCMPEQDYrm:
20903 case VPCMPEQDYrr:
20904 case VPCMPEQDZ128rm:
20905 case VPCMPEQDZ128rmb:
20906 case VPCMPEQDZ128rmbk:
20907 case VPCMPEQDZ128rmk:
20908 case VPCMPEQDZ128rr:
20909 case VPCMPEQDZ128rrk:
20910 case VPCMPEQDZ256rm:
20911 case VPCMPEQDZ256rmb:
20912 case VPCMPEQDZ256rmbk:
20913 case VPCMPEQDZ256rmk:
20914 case VPCMPEQDZ256rr:
20915 case VPCMPEQDZ256rrk:
20916 case VPCMPEQDZrm:
20917 case VPCMPEQDZrmb:
20918 case VPCMPEQDZrmbk:
20919 case VPCMPEQDZrmk:
20920 case VPCMPEQDZrr:
20921 case VPCMPEQDZrrk:
20922 case VPCMPEQDrm:
20923 case VPCMPEQDrr:
20924 return true;
20925 }
20926 return false;
20927}
20928
20929bool isVPSCATTERQD(unsigned Opcode) {
20930 switch (Opcode) {
20931 case VPSCATTERQDZ128mr:
20932 case VPSCATTERQDZ256mr:
20933 case VPSCATTERQDZmr:
20934 return true;
20935 }
20936 return false;
20937}
20938
20939bool isVPSHLDD(unsigned Opcode) {
20940 switch (Opcode) {
20941 case VPSHLDDZ128rmbi:
20942 case VPSHLDDZ128rmbik:
20943 case VPSHLDDZ128rmbikz:
20944 case VPSHLDDZ128rmi:
20945 case VPSHLDDZ128rmik:
20946 case VPSHLDDZ128rmikz:
20947 case VPSHLDDZ128rri:
20948 case VPSHLDDZ128rrik:
20949 case VPSHLDDZ128rrikz:
20950 case VPSHLDDZ256rmbi:
20951 case VPSHLDDZ256rmbik:
20952 case VPSHLDDZ256rmbikz:
20953 case VPSHLDDZ256rmi:
20954 case VPSHLDDZ256rmik:
20955 case VPSHLDDZ256rmikz:
20956 case VPSHLDDZ256rri:
20957 case VPSHLDDZ256rrik:
20958 case VPSHLDDZ256rrikz:
20959 case VPSHLDDZrmbi:
20960 case VPSHLDDZrmbik:
20961 case VPSHLDDZrmbikz:
20962 case VPSHLDDZrmi:
20963 case VPSHLDDZrmik:
20964 case VPSHLDDZrmikz:
20965 case VPSHLDDZrri:
20966 case VPSHLDDZrrik:
20967 case VPSHLDDZrrikz:
20968 return true;
20969 }
20970 return false;
20971}
20972
20973bool isKXNORB(unsigned Opcode) {
20974 return Opcode == KXNORBkk;
20975}
20976
20977bool isLDDQU(unsigned Opcode) {
20978 return Opcode == LDDQUrm;
20979}
20980
20981bool isMASKMOVQ(unsigned Opcode) {
20982 switch (Opcode) {
20983 case MMX_MASKMOVQ:
20984 case MMX_MASKMOVQ64:
20985 return true;
20986 }
20987 return false;
20988}
20989
20990bool isPABSW(unsigned Opcode) {
20991 switch (Opcode) {
20992 case MMX_PABSWrm:
20993 case MMX_PABSWrr:
20994 case PABSWrm:
20995 case PABSWrr:
20996 return true;
20997 }
20998 return false;
20999}
21000
21001bool isVPROLD(unsigned Opcode) {
21002 switch (Opcode) {
21003 case VPROLDZ128mbi:
21004 case VPROLDZ128mbik:
21005 case VPROLDZ128mbikz:
21006 case VPROLDZ128mi:
21007 case VPROLDZ128mik:
21008 case VPROLDZ128mikz:
21009 case VPROLDZ128ri:
21010 case VPROLDZ128rik:
21011 case VPROLDZ128rikz:
21012 case VPROLDZ256mbi:
21013 case VPROLDZ256mbik:
21014 case VPROLDZ256mbikz:
21015 case VPROLDZ256mi:
21016 case VPROLDZ256mik:
21017 case VPROLDZ256mikz:
21018 case VPROLDZ256ri:
21019 case VPROLDZ256rik:
21020 case VPROLDZ256rikz:
21021 case VPROLDZmbi:
21022 case VPROLDZmbik:
21023 case VPROLDZmbikz:
21024 case VPROLDZmi:
21025 case VPROLDZmik:
21026 case VPROLDZmikz:
21027 case VPROLDZri:
21028 case VPROLDZrik:
21029 case VPROLDZrikz:
21030 return true;
21031 }
21032 return false;
21033}
21034
21035bool isVPCOMQ(unsigned Opcode) {
21036 switch (Opcode) {
21037 case VPCOMQmi:
21038 case VPCOMQri:
21039 return true;
21040 }
21041 return false;
21042}
21043
21044bool isVSCATTERDPD(unsigned Opcode) {
21045 switch (Opcode) {
21046 case VSCATTERDPDZ128mr:
21047 case VSCATTERDPDZ256mr:
21048 case VSCATTERDPDZmr:
21049 return true;
21050 }
21051 return false;
21052}
21053
21054bool isFXRSTOR(unsigned Opcode) {
21055 return Opcode == FXRSTOR;
21056}
21057
21058bool isVPCMPUW(unsigned Opcode) {
21059 switch (Opcode) {
21060 case VPCMPUWZ128rmi:
21061 case VPCMPUWZ128rmik:
21062 case VPCMPUWZ128rri:
21063 case VPCMPUWZ128rrik:
21064 case VPCMPUWZ256rmi:
21065 case VPCMPUWZ256rmik:
21066 case VPCMPUWZ256rri:
21067 case VPCMPUWZ256rrik:
21068 case VPCMPUWZrmi:
21069 case VPCMPUWZrmik:
21070 case VPCMPUWZrri:
21071 case VPCMPUWZrrik:
21072 return true;
21073 }
21074 return false;
21075}
21076
21077bool isWBINVD(unsigned Opcode) {
21078 return Opcode == WBINVD;
21079}
21080
21081bool isVCVTTPD2UDQ(unsigned Opcode) {
21082 switch (Opcode) {
21083 case VCVTTPD2UDQZ128rm:
21084 case VCVTTPD2UDQZ128rmb:
21085 case VCVTTPD2UDQZ128rmbk:
21086 case VCVTTPD2UDQZ128rmbkz:
21087 case VCVTTPD2UDQZ128rmk:
21088 case VCVTTPD2UDQZ128rmkz:
21089 case VCVTTPD2UDQZ128rr:
21090 case VCVTTPD2UDQZ128rrk:
21091 case VCVTTPD2UDQZ128rrkz:
21092 case VCVTTPD2UDQZ256rm:
21093 case VCVTTPD2UDQZ256rmb:
21094 case VCVTTPD2UDQZ256rmbk:
21095 case VCVTTPD2UDQZ256rmbkz:
21096 case VCVTTPD2UDQZ256rmk:
21097 case VCVTTPD2UDQZ256rmkz:
21098 case VCVTTPD2UDQZ256rr:
21099 case VCVTTPD2UDQZ256rrk:
21100 case VCVTTPD2UDQZ256rrkz:
21101 case VCVTTPD2UDQZrm:
21102 case VCVTTPD2UDQZrmb:
21103 case VCVTTPD2UDQZrmbk:
21104 case VCVTTPD2UDQZrmbkz:
21105 case VCVTTPD2UDQZrmk:
21106 case VCVTTPD2UDQZrmkz:
21107 case VCVTTPD2UDQZrr:
21108 case VCVTTPD2UDQZrrb:
21109 case VCVTTPD2UDQZrrbk:
21110 case VCVTTPD2UDQZrrbkz:
21111 case VCVTTPD2UDQZrrk:
21112 case VCVTTPD2UDQZrrkz:
21113 return true;
21114 }
21115 return false;
21116}
21117
21118bool isERETU(unsigned Opcode) {
21119 return Opcode == ERETU;
21120}
21121
21122bool isPFRCPIT2(unsigned Opcode) {
21123 switch (Opcode) {
21124 case PFRCPIT2rm:
21125 case PFRCPIT2rr:
21126 return true;
21127 }
21128 return false;
21129}
21130
21131bool isVPERMT2W(unsigned Opcode) {
21132 switch (Opcode) {
21133 case VPERMT2WZ128rm:
21134 case VPERMT2WZ128rmk:
21135 case VPERMT2WZ128rmkz:
21136 case VPERMT2WZ128rr:
21137 case VPERMT2WZ128rrk:
21138 case VPERMT2WZ128rrkz:
21139 case VPERMT2WZ256rm:
21140 case VPERMT2WZ256rmk:
21141 case VPERMT2WZ256rmkz:
21142 case VPERMT2WZ256rr:
21143 case VPERMT2WZ256rrk:
21144 case VPERMT2WZ256rrkz:
21145 case VPERMT2WZrm:
21146 case VPERMT2WZrmk:
21147 case VPERMT2WZrmkz:
21148 case VPERMT2WZrr:
21149 case VPERMT2WZrrk:
21150 case VPERMT2WZrrkz:
21151 return true;
21152 }
21153 return false;
21154}
21155
21156bool isVEXTRACTF32X4(unsigned Opcode) {
21157 switch (Opcode) {
21158 case VEXTRACTF32X4Z256mri:
21159 case VEXTRACTF32X4Z256mrik:
21160 case VEXTRACTF32X4Z256rri:
21161 case VEXTRACTF32X4Z256rrik:
21162 case VEXTRACTF32X4Z256rrikz:
21163 case VEXTRACTF32X4Zmri:
21164 case VEXTRACTF32X4Zmrik:
21165 case VEXTRACTF32X4Zrri:
21166 case VEXTRACTF32X4Zrrik:
21167 case VEXTRACTF32X4Zrrikz:
21168 return true;
21169 }
21170 return false;
21171}
21172
21173bool isVGATHERPF0DPD(unsigned Opcode) {
21174 return Opcode == VGATHERPF0DPDm;
21175}
21176
21177bool isVBROADCASTF32X2(unsigned Opcode) {
21178 switch (Opcode) {
21179 case VBROADCASTF32X2Z256rm:
21180 case VBROADCASTF32X2Z256rmk:
21181 case VBROADCASTF32X2Z256rmkz:
21182 case VBROADCASTF32X2Z256rr:
21183 case VBROADCASTF32X2Z256rrk:
21184 case VBROADCASTF32X2Z256rrkz:
21185 case VBROADCASTF32X2Zrm:
21186 case VBROADCASTF32X2Zrmk:
21187 case VBROADCASTF32X2Zrmkz:
21188 case VBROADCASTF32X2Zrr:
21189 case VBROADCASTF32X2Zrrk:
21190 case VBROADCASTF32X2Zrrkz:
21191 return true;
21192 }
21193 return false;
21194}
21195
21196bool isVRCP14SD(unsigned Opcode) {
21197 switch (Opcode) {
21198 case VRCP14SDZrm:
21199 case VRCP14SDZrmk:
21200 case VRCP14SDZrmkz:
21201 case VRCP14SDZrr:
21202 case VRCP14SDZrrk:
21203 case VRCP14SDZrrkz:
21204 return true;
21205 }
21206 return false;
21207}
21208
21209bool isPABSD(unsigned Opcode) {
21210 switch (Opcode) {
21211 case MMX_PABSDrm:
21212 case MMX_PABSDrr:
21213 case PABSDrm:
21214 case PABSDrr:
21215 return true;
21216 }
21217 return false;
21218}
21219
21220bool isLAHF(unsigned Opcode) {
21221 return Opcode == LAHF;
21222}
21223
21224bool isPINSRB(unsigned Opcode) {
21225 switch (Opcode) {
21226 case PINSRBrmi:
21227 case PINSRBrri:
21228 return true;
21229 }
21230 return false;
21231}
21232
21233bool isSKINIT(unsigned Opcode) {
21234 return Opcode == SKINIT;
21235}
21236
21237bool isENTER(unsigned Opcode) {
21238 return Opcode == ENTER;
21239}
21240
21241bool isVCVTSI2SS(unsigned Opcode) {
21242 switch (Opcode) {
21243 case VCVTSI2SSZrm_Int:
21244 case VCVTSI2SSZrr_Int:
21245 case VCVTSI2SSZrrb_Int:
21246 case VCVTSI2SSrm_Int:
21247 case VCVTSI2SSrr_Int:
21248 case VCVTSI642SSZrm_Int:
21249 case VCVTSI642SSZrr_Int:
21250 case VCVTSI642SSZrrb_Int:
21251 case VCVTSI642SSrm_Int:
21252 case VCVTSI642SSrr_Int:
21253 return true;
21254 }
21255 return false;
21256}
21257
21258bool isVFMADD231PD(unsigned Opcode) {
21259 switch (Opcode) {
21260 case VFMADD231PDYm:
21261 case VFMADD231PDYr:
21262 case VFMADD231PDZ128m:
21263 case VFMADD231PDZ128mb:
21264 case VFMADD231PDZ128mbk:
21265 case VFMADD231PDZ128mbkz:
21266 case VFMADD231PDZ128mk:
21267 case VFMADD231PDZ128mkz:
21268 case VFMADD231PDZ128r:
21269 case VFMADD231PDZ128rk:
21270 case VFMADD231PDZ128rkz:
21271 case VFMADD231PDZ256m:
21272 case VFMADD231PDZ256mb:
21273 case VFMADD231PDZ256mbk:
21274 case VFMADD231PDZ256mbkz:
21275 case VFMADD231PDZ256mk:
21276 case VFMADD231PDZ256mkz:
21277 case VFMADD231PDZ256r:
21278 case VFMADD231PDZ256rk:
21279 case VFMADD231PDZ256rkz:
21280 case VFMADD231PDZm:
21281 case VFMADD231PDZmb:
21282 case VFMADD231PDZmbk:
21283 case VFMADD231PDZmbkz:
21284 case VFMADD231PDZmk:
21285 case VFMADD231PDZmkz:
21286 case VFMADD231PDZr:
21287 case VFMADD231PDZrb:
21288 case VFMADD231PDZrbk:
21289 case VFMADD231PDZrbkz:
21290 case VFMADD231PDZrk:
21291 case VFMADD231PDZrkz:
21292 case VFMADD231PDm:
21293 case VFMADD231PDr:
21294 return true;
21295 }
21296 return false;
21297}
21298
21299bool isLOADIWKEY(unsigned Opcode) {
21300 return Opcode == LOADIWKEY;
21301}
21302
21303bool isVMOVNTDQA(unsigned Opcode) {
21304 switch (Opcode) {
21305 case VMOVNTDQAYrm:
21306 case VMOVNTDQAZ128rm:
21307 case VMOVNTDQAZ256rm:
21308 case VMOVNTDQAZrm:
21309 case VMOVNTDQArm:
21310 return true;
21311 }
21312 return false;
21313}
21314
21315bool isVPERMT2PS(unsigned Opcode) {
21316 switch (Opcode) {
21317 case VPERMT2PSZ128rm:
21318 case VPERMT2PSZ128rmb:
21319 case VPERMT2PSZ128rmbk:
21320 case VPERMT2PSZ128rmbkz:
21321 case VPERMT2PSZ128rmk:
21322 case VPERMT2PSZ128rmkz:
21323 case VPERMT2PSZ128rr:
21324 case VPERMT2PSZ128rrk:
21325 case VPERMT2PSZ128rrkz:
21326 case VPERMT2PSZ256rm:
21327 case VPERMT2PSZ256rmb:
21328 case VPERMT2PSZ256rmbk:
21329 case VPERMT2PSZ256rmbkz:
21330 case VPERMT2PSZ256rmk:
21331 case VPERMT2PSZ256rmkz:
21332 case VPERMT2PSZ256rr:
21333 case VPERMT2PSZ256rrk:
21334 case VPERMT2PSZ256rrkz:
21335 case VPERMT2PSZrm:
21336 case VPERMT2PSZrmb:
21337 case VPERMT2PSZrmbk:
21338 case VPERMT2PSZrmbkz:
21339 case VPERMT2PSZrmk:
21340 case VPERMT2PSZrmkz:
21341 case VPERMT2PSZrr:
21342 case VPERMT2PSZrrk:
21343 case VPERMT2PSZrrkz:
21344 return true;
21345 }
21346 return false;
21347}
21348
21349bool isPUSHF(unsigned Opcode) {
21350 return Opcode == PUSHF16;
21351}
21352
21353bool isMPSADBW(unsigned Opcode) {
21354 switch (Opcode) {
21355 case MPSADBWrmi:
21356 case MPSADBWrri:
21357 return true;
21358 }
21359 return false;
21360}
21361
21362bool isVMINMAXSH(unsigned Opcode) {
21363 switch (Opcode) {
21364 case VMINMAXSHrmi_Int:
21365 case VMINMAXSHrmik_Int:
21366 case VMINMAXSHrmikz_Int:
21367 case VMINMAXSHrri_Int:
21368 case VMINMAXSHrrib_Int:
21369 case VMINMAXSHrribk_Int:
21370 case VMINMAXSHrribkz_Int:
21371 case VMINMAXSHrrik_Int:
21372 case VMINMAXSHrrikz_Int:
21373 return true;
21374 }
21375 return false;
21376}
21377
21378bool isVRSQRT14SS(unsigned Opcode) {
21379 switch (Opcode) {
21380 case VRSQRT14SSZrm:
21381 case VRSQRT14SSZrmk:
21382 case VRSQRT14SSZrmkz:
21383 case VRSQRT14SSZrr:
21384 case VRSQRT14SSZrrk:
21385 case VRSQRT14SSZrrkz:
21386 return true;
21387 }
21388 return false;
21389}
21390
21391bool isVCVTDQ2PD(unsigned Opcode) {
21392 switch (Opcode) {
21393 case VCVTDQ2PDYrm:
21394 case VCVTDQ2PDYrr:
21395 case VCVTDQ2PDZ128rm:
21396 case VCVTDQ2PDZ128rmb:
21397 case VCVTDQ2PDZ128rmbk:
21398 case VCVTDQ2PDZ128rmbkz:
21399 case VCVTDQ2PDZ128rmk:
21400 case VCVTDQ2PDZ128rmkz:
21401 case VCVTDQ2PDZ128rr:
21402 case VCVTDQ2PDZ128rrk:
21403 case VCVTDQ2PDZ128rrkz:
21404 case VCVTDQ2PDZ256rm:
21405 case VCVTDQ2PDZ256rmb:
21406 case VCVTDQ2PDZ256rmbk:
21407 case VCVTDQ2PDZ256rmbkz:
21408 case VCVTDQ2PDZ256rmk:
21409 case VCVTDQ2PDZ256rmkz:
21410 case VCVTDQ2PDZ256rr:
21411 case VCVTDQ2PDZ256rrk:
21412 case VCVTDQ2PDZ256rrkz:
21413 case VCVTDQ2PDZrm:
21414 case VCVTDQ2PDZrmb:
21415 case VCVTDQ2PDZrmbk:
21416 case VCVTDQ2PDZrmbkz:
21417 case VCVTDQ2PDZrmk:
21418 case VCVTDQ2PDZrmkz:
21419 case VCVTDQ2PDZrr:
21420 case VCVTDQ2PDZrrk:
21421 case VCVTDQ2PDZrrkz:
21422 case VCVTDQ2PDrm:
21423 case VCVTDQ2PDrr:
21424 return true;
21425 }
21426 return false;
21427}
21428
21429bool isVORPS(unsigned Opcode) {
21430 switch (Opcode) {
21431 case VORPSYrm:
21432 case VORPSYrr:
21433 case VORPSZ128rm:
21434 case VORPSZ128rmb:
21435 case VORPSZ128rmbk:
21436 case VORPSZ128rmbkz:
21437 case VORPSZ128rmk:
21438 case VORPSZ128rmkz:
21439 case VORPSZ128rr:
21440 case VORPSZ128rrk:
21441 case VORPSZ128rrkz:
21442 case VORPSZ256rm:
21443 case VORPSZ256rmb:
21444 case VORPSZ256rmbk:
21445 case VORPSZ256rmbkz:
21446 case VORPSZ256rmk:
21447 case VORPSZ256rmkz:
21448 case VORPSZ256rr:
21449 case VORPSZ256rrk:
21450 case VORPSZ256rrkz:
21451 case VORPSZrm:
21452 case VORPSZrmb:
21453 case VORPSZrmbk:
21454 case VORPSZrmbkz:
21455 case VORPSZrmk:
21456 case VORPSZrmkz:
21457 case VORPSZrr:
21458 case VORPSZrrk:
21459 case VORPSZrrkz:
21460 case VORPSrm:
21461 case VORPSrr:
21462 return true;
21463 }
21464 return false;
21465}
21466
21467bool isVPEXPANDQ(unsigned Opcode) {
21468 switch (Opcode) {
21469 case VPEXPANDQZ128rm:
21470 case VPEXPANDQZ128rmk:
21471 case VPEXPANDQZ128rmkz:
21472 case VPEXPANDQZ128rr:
21473 case VPEXPANDQZ128rrk:
21474 case VPEXPANDQZ128rrkz:
21475 case VPEXPANDQZ256rm:
21476 case VPEXPANDQZ256rmk:
21477 case VPEXPANDQZ256rmkz:
21478 case VPEXPANDQZ256rr:
21479 case VPEXPANDQZ256rrk:
21480 case VPEXPANDQZ256rrkz:
21481 case VPEXPANDQZrm:
21482 case VPEXPANDQZrmk:
21483 case VPEXPANDQZrmkz:
21484 case VPEXPANDQZrr:
21485 case VPEXPANDQZrrk:
21486 case VPEXPANDQZrrkz:
21487 return true;
21488 }
21489 return false;
21490}
21491
21492bool isVPSHRDD(unsigned Opcode) {
21493 switch (Opcode) {
21494 case VPSHRDDZ128rmbi:
21495 case VPSHRDDZ128rmbik:
21496 case VPSHRDDZ128rmbikz:
21497 case VPSHRDDZ128rmi:
21498 case VPSHRDDZ128rmik:
21499 case VPSHRDDZ128rmikz:
21500 case VPSHRDDZ128rri:
21501 case VPSHRDDZ128rrik:
21502 case VPSHRDDZ128rrikz:
21503 case VPSHRDDZ256rmbi:
21504 case VPSHRDDZ256rmbik:
21505 case VPSHRDDZ256rmbikz:
21506 case VPSHRDDZ256rmi:
21507 case VPSHRDDZ256rmik:
21508 case VPSHRDDZ256rmikz:
21509 case VPSHRDDZ256rri:
21510 case VPSHRDDZ256rrik:
21511 case VPSHRDDZ256rrikz:
21512 case VPSHRDDZrmbi:
21513 case VPSHRDDZrmbik:
21514 case VPSHRDDZrmbikz:
21515 case VPSHRDDZrmi:
21516 case VPSHRDDZrmik:
21517 case VPSHRDDZrmikz:
21518 case VPSHRDDZrri:
21519 case VPSHRDDZrrik:
21520 case VPSHRDDZrrikz:
21521 return true;
21522 }
21523 return false;
21524}
21525
21526bool isTDPBSSD(unsigned Opcode) {
21527 return Opcode == TDPBSSD;
21528}
21529
21530bool isTESTUI(unsigned Opcode) {
21531 return Opcode == TESTUI;
21532}
21533
21534bool isVFMADDPD(unsigned Opcode) {
21535 switch (Opcode) {
21536 case VFMADDPD4Ymr:
21537 case VFMADDPD4Yrm:
21538 case VFMADDPD4Yrr:
21539 case VFMADDPD4Yrr_REV:
21540 case VFMADDPD4mr:
21541 case VFMADDPD4rm:
21542 case VFMADDPD4rr:
21543 case VFMADDPD4rr_REV:
21544 return true;
21545 }
21546 return false;
21547}
21548
21549bool isVPANDND(unsigned Opcode) {
21550 switch (Opcode) {
21551 case VPANDNDZ128rm:
21552 case VPANDNDZ128rmb:
21553 case VPANDNDZ128rmbk:
21554 case VPANDNDZ128rmbkz:
21555 case VPANDNDZ128rmk:
21556 case VPANDNDZ128rmkz:
21557 case VPANDNDZ128rr:
21558 case VPANDNDZ128rrk:
21559 case VPANDNDZ128rrkz:
21560 case VPANDNDZ256rm:
21561 case VPANDNDZ256rmb:
21562 case VPANDNDZ256rmbk:
21563 case VPANDNDZ256rmbkz:
21564 case VPANDNDZ256rmk:
21565 case VPANDNDZ256rmkz:
21566 case VPANDNDZ256rr:
21567 case VPANDNDZ256rrk:
21568 case VPANDNDZ256rrkz:
21569 case VPANDNDZrm:
21570 case VPANDNDZrmb:
21571 case VPANDNDZrmbk:
21572 case VPANDNDZrmbkz:
21573 case VPANDNDZrmk:
21574 case VPANDNDZrmkz:
21575 case VPANDNDZrr:
21576 case VPANDNDZrrk:
21577 case VPANDNDZrrkz:
21578 return true;
21579 }
21580 return false;
21581}
21582
21583bool isVPMOVSDB(unsigned Opcode) {
21584 switch (Opcode) {
21585 case VPMOVSDBZ128mr:
21586 case VPMOVSDBZ128mrk:
21587 case VPMOVSDBZ128rr:
21588 case VPMOVSDBZ128rrk:
21589 case VPMOVSDBZ128rrkz:
21590 case VPMOVSDBZ256mr:
21591 case VPMOVSDBZ256mrk:
21592 case VPMOVSDBZ256rr:
21593 case VPMOVSDBZ256rrk:
21594 case VPMOVSDBZ256rrkz:
21595 case VPMOVSDBZmr:
21596 case VPMOVSDBZmrk:
21597 case VPMOVSDBZrr:
21598 case VPMOVSDBZrrk:
21599 case VPMOVSDBZrrkz:
21600 return true;
21601 }
21602 return false;
21603}
21604
21605bool isVPBROADCASTB(unsigned Opcode) {
21606 switch (Opcode) {
21607 case VPBROADCASTBYrm:
21608 case VPBROADCASTBYrr:
21609 case VPBROADCASTBZ128rm:
21610 case VPBROADCASTBZ128rmk:
21611 case VPBROADCASTBZ128rmkz:
21612 case VPBROADCASTBZ128rr:
21613 case VPBROADCASTBZ128rrk:
21614 case VPBROADCASTBZ128rrkz:
21615 case VPBROADCASTBZ256rm:
21616 case VPBROADCASTBZ256rmk:
21617 case VPBROADCASTBZ256rmkz:
21618 case VPBROADCASTBZ256rr:
21619 case VPBROADCASTBZ256rrk:
21620 case VPBROADCASTBZ256rrkz:
21621 case VPBROADCASTBZrm:
21622 case VPBROADCASTBZrmk:
21623 case VPBROADCASTBZrmkz:
21624 case VPBROADCASTBZrr:
21625 case VPBROADCASTBZrrk:
21626 case VPBROADCASTBZrrkz:
21627 case VPBROADCASTBrZ128rr:
21628 case VPBROADCASTBrZ128rrk:
21629 case VPBROADCASTBrZ128rrkz:
21630 case VPBROADCASTBrZ256rr:
21631 case VPBROADCASTBrZ256rrk:
21632 case VPBROADCASTBrZ256rrkz:
21633 case VPBROADCASTBrZrr:
21634 case VPBROADCASTBrZrrk:
21635 case VPBROADCASTBrZrrkz:
21636 case VPBROADCASTBrm:
21637 case VPBROADCASTBrr:
21638 return true;
21639 }
21640 return false;
21641}
21642
21643bool isCVTPI2PD(unsigned Opcode) {
21644 switch (Opcode) {
21645 case MMX_CVTPI2PDrm:
21646 case MMX_CVTPI2PDrr:
21647 return true;
21648 }
21649 return false;
21650}
21651
21652bool isVPERMI2B(unsigned Opcode) {
21653 switch (Opcode) {
21654 case VPERMI2BZ128rm:
21655 case VPERMI2BZ128rmk:
21656 case VPERMI2BZ128rmkz:
21657 case VPERMI2BZ128rr:
21658 case VPERMI2BZ128rrk:
21659 case VPERMI2BZ128rrkz:
21660 case VPERMI2BZ256rm:
21661 case VPERMI2BZ256rmk:
21662 case VPERMI2BZ256rmkz:
21663 case VPERMI2BZ256rr:
21664 case VPERMI2BZ256rrk:
21665 case VPERMI2BZ256rrkz:
21666 case VPERMI2BZrm:
21667 case VPERMI2BZrmk:
21668 case VPERMI2BZrmkz:
21669 case VPERMI2BZrr:
21670 case VPERMI2BZrrk:
21671 case VPERMI2BZrrkz:
21672 return true;
21673 }
21674 return false;
21675}
21676
21677bool isVPMINSB(unsigned Opcode) {
21678 switch (Opcode) {
21679 case VPMINSBYrm:
21680 case VPMINSBYrr:
21681 case VPMINSBZ128rm:
21682 case VPMINSBZ128rmk:
21683 case VPMINSBZ128rmkz:
21684 case VPMINSBZ128rr:
21685 case VPMINSBZ128rrk:
21686 case VPMINSBZ128rrkz:
21687 case VPMINSBZ256rm:
21688 case VPMINSBZ256rmk:
21689 case VPMINSBZ256rmkz:
21690 case VPMINSBZ256rr:
21691 case VPMINSBZ256rrk:
21692 case VPMINSBZ256rrkz:
21693 case VPMINSBZrm:
21694 case VPMINSBZrmk:
21695 case VPMINSBZrmkz:
21696 case VPMINSBZrr:
21697 case VPMINSBZrrk:
21698 case VPMINSBZrrkz:
21699 case VPMINSBrm:
21700 case VPMINSBrr:
21701 return true;
21702 }
21703 return false;
21704}
21705
21706bool isLAR(unsigned Opcode) {
21707 switch (Opcode) {
21708 case LAR16rm:
21709 case LAR16rr:
21710 case LAR32rm:
21711 case LAR32rr:
21712 case LAR64rm:
21713 case LAR64rr:
21714 return true;
21715 }
21716 return false;
21717}
21718
21719bool isINVLPGB(unsigned Opcode) {
21720 switch (Opcode) {
21721 case INVLPGB32:
21722 case INVLPGB64:
21723 return true;
21724 }
21725 return false;
21726}
21727
21728bool isTLBSYNC(unsigned Opcode) {
21729 return Opcode == TLBSYNC;
21730}
21731
21732bool isFDIVP(unsigned Opcode) {
21733 return Opcode == DIV_FPrST0;
21734}
21735
21736bool isVPSRLW(unsigned Opcode) {
21737 switch (Opcode) {
21738 case VPSRLWYri:
21739 case VPSRLWYrm:
21740 case VPSRLWYrr:
21741 case VPSRLWZ128mi:
21742 case VPSRLWZ128mik:
21743 case VPSRLWZ128mikz:
21744 case VPSRLWZ128ri:
21745 case VPSRLWZ128rik:
21746 case VPSRLWZ128rikz:
21747 case VPSRLWZ128rm:
21748 case VPSRLWZ128rmk:
21749 case VPSRLWZ128rmkz:
21750 case VPSRLWZ128rr:
21751 case VPSRLWZ128rrk:
21752 case VPSRLWZ128rrkz:
21753 case VPSRLWZ256mi:
21754 case VPSRLWZ256mik:
21755 case VPSRLWZ256mikz:
21756 case VPSRLWZ256ri:
21757 case VPSRLWZ256rik:
21758 case VPSRLWZ256rikz:
21759 case VPSRLWZ256rm:
21760 case VPSRLWZ256rmk:
21761 case VPSRLWZ256rmkz:
21762 case VPSRLWZ256rr:
21763 case VPSRLWZ256rrk:
21764 case VPSRLWZ256rrkz:
21765 case VPSRLWZmi:
21766 case VPSRLWZmik:
21767 case VPSRLWZmikz:
21768 case VPSRLWZri:
21769 case VPSRLWZrik:
21770 case VPSRLWZrikz:
21771 case VPSRLWZrm:
21772 case VPSRLWZrmk:
21773 case VPSRLWZrmkz:
21774 case VPSRLWZrr:
21775 case VPSRLWZrrk:
21776 case VPSRLWZrrkz:
21777 case VPSRLWri:
21778 case VPSRLWrm:
21779 case VPSRLWrr:
21780 return true;
21781 }
21782 return false;
21783}
21784
21785bool isVRCP28SS(unsigned Opcode) {
21786 switch (Opcode) {
21787 case VRCP28SSZm:
21788 case VRCP28SSZmk:
21789 case VRCP28SSZmkz:
21790 case VRCP28SSZr:
21791 case VRCP28SSZrb:
21792 case VRCP28SSZrbk:
21793 case VRCP28SSZrbkz:
21794 case VRCP28SSZrk:
21795 case VRCP28SSZrkz:
21796 return true;
21797 }
21798 return false;
21799}
21800
21801bool isVMOVHPS(unsigned Opcode) {
21802 switch (Opcode) {
21803 case VMOVHPSZ128mr:
21804 case VMOVHPSZ128rm:
21805 case VMOVHPSmr:
21806 case VMOVHPSrm:
21807 return true;
21808 }
21809 return false;
21810}
21811
21812bool isVPMACSSDD(unsigned Opcode) {
21813 switch (Opcode) {
21814 case VPMACSSDDrm:
21815 case VPMACSSDDrr:
21816 return true;
21817 }
21818 return false;
21819}
21820
21821bool isPEXT(unsigned Opcode) {
21822 switch (Opcode) {
21823 case PEXT32rm:
21824 case PEXT32rm_EVEX:
21825 case PEXT32rr:
21826 case PEXT32rr_EVEX:
21827 case PEXT64rm:
21828 case PEXT64rm_EVEX:
21829 case PEXT64rr:
21830 case PEXT64rr_EVEX:
21831 return true;
21832 }
21833 return false;
21834}
21835
21836bool isVMAXBF16(unsigned Opcode) {
21837 switch (Opcode) {
21838 case VMAXBF16Z128rm:
21839 case VMAXBF16Z128rmb:
21840 case VMAXBF16Z128rmbk:
21841 case VMAXBF16Z128rmbkz:
21842 case VMAXBF16Z128rmk:
21843 case VMAXBF16Z128rmkz:
21844 case VMAXBF16Z128rr:
21845 case VMAXBF16Z128rrk:
21846 case VMAXBF16Z128rrkz:
21847 case VMAXBF16Z256rm:
21848 case VMAXBF16Z256rmb:
21849 case VMAXBF16Z256rmbk:
21850 case VMAXBF16Z256rmbkz:
21851 case VMAXBF16Z256rmk:
21852 case VMAXBF16Z256rmkz:
21853 case VMAXBF16Z256rr:
21854 case VMAXBF16Z256rrk:
21855 case VMAXBF16Z256rrkz:
21856 case VMAXBF16Zrm:
21857 case VMAXBF16Zrmb:
21858 case VMAXBF16Zrmbk:
21859 case VMAXBF16Zrmbkz:
21860 case VMAXBF16Zrmk:
21861 case VMAXBF16Zrmkz:
21862 case VMAXBF16Zrr:
21863 case VMAXBF16Zrrk:
21864 case VMAXBF16Zrrkz:
21865 return true;
21866 }
21867 return false;
21868}
21869
21870bool isVRSQRT14SD(unsigned Opcode) {
21871 switch (Opcode) {
21872 case VRSQRT14SDZrm:
21873 case VRSQRT14SDZrmk:
21874 case VRSQRT14SDZrmkz:
21875 case VRSQRT14SDZrr:
21876 case VRSQRT14SDZrrk:
21877 case VRSQRT14SDZrrkz:
21878 return true;
21879 }
21880 return false;
21881}
21882
21883bool isVPDPWSSD(unsigned Opcode) {
21884 switch (Opcode) {
21885 case VPDPWSSDYrm:
21886 case VPDPWSSDYrr:
21887 case VPDPWSSDZ128rm:
21888 case VPDPWSSDZ128rmb:
21889 case VPDPWSSDZ128rmbk:
21890 case VPDPWSSDZ128rmbkz:
21891 case VPDPWSSDZ128rmk:
21892 case VPDPWSSDZ128rmkz:
21893 case VPDPWSSDZ128rr:
21894 case VPDPWSSDZ128rrk:
21895 case VPDPWSSDZ128rrkz:
21896 case VPDPWSSDZ256rm:
21897 case VPDPWSSDZ256rmb:
21898 case VPDPWSSDZ256rmbk:
21899 case VPDPWSSDZ256rmbkz:
21900 case VPDPWSSDZ256rmk:
21901 case VPDPWSSDZ256rmkz:
21902 case VPDPWSSDZ256rr:
21903 case VPDPWSSDZ256rrk:
21904 case VPDPWSSDZ256rrkz:
21905 case VPDPWSSDZrm:
21906 case VPDPWSSDZrmb:
21907 case VPDPWSSDZrmbk:
21908 case VPDPWSSDZrmbkz:
21909 case VPDPWSSDZrmk:
21910 case VPDPWSSDZrmkz:
21911 case VPDPWSSDZrr:
21912 case VPDPWSSDZrrk:
21913 case VPDPWSSDZrrkz:
21914 case VPDPWSSDrm:
21915 case VPDPWSSDrr:
21916 return true;
21917 }
21918 return false;
21919}
21920
21921bool isVFMSUB231SD(unsigned Opcode) {
21922 switch (Opcode) {
21923 case VFMSUB231SDZm_Int:
21924 case VFMSUB231SDZmk_Int:
21925 case VFMSUB231SDZmkz_Int:
21926 case VFMSUB231SDZr_Int:
21927 case VFMSUB231SDZrb_Int:
21928 case VFMSUB231SDZrbk_Int:
21929 case VFMSUB231SDZrbkz_Int:
21930 case VFMSUB231SDZrk_Int:
21931 case VFMSUB231SDZrkz_Int:
21932 case VFMSUB231SDm_Int:
21933 case VFMSUB231SDr_Int:
21934 return true;
21935 }
21936 return false;
21937}
21938
21939bool isVPMOVZXWQ(unsigned Opcode) {
21940 switch (Opcode) {
21941 case VPMOVZXWQYrm:
21942 case VPMOVZXWQYrr:
21943 case VPMOVZXWQZ128rm:
21944 case VPMOVZXWQZ128rmk:
21945 case VPMOVZXWQZ128rmkz:
21946 case VPMOVZXWQZ128rr:
21947 case VPMOVZXWQZ128rrk:
21948 case VPMOVZXWQZ128rrkz:
21949 case VPMOVZXWQZ256rm:
21950 case VPMOVZXWQZ256rmk:
21951 case VPMOVZXWQZ256rmkz:
21952 case VPMOVZXWQZ256rr:
21953 case VPMOVZXWQZ256rrk:
21954 case VPMOVZXWQZ256rrkz:
21955 case VPMOVZXWQZrm:
21956 case VPMOVZXWQZrmk:
21957 case VPMOVZXWQZrmkz:
21958 case VPMOVZXWQZrr:
21959 case VPMOVZXWQZrrk:
21960 case VPMOVZXWQZrrkz:
21961 case VPMOVZXWQrm:
21962 case VPMOVZXWQrr:
21963 return true;
21964 }
21965 return false;
21966}
21967
21968bool isVMOVDQA(unsigned Opcode) {
21969 switch (Opcode) {
21970 case VMOVDQAYmr:
21971 case VMOVDQAYrm:
21972 case VMOVDQAYrr:
21973 case VMOVDQAYrr_REV:
21974 case VMOVDQAmr:
21975 case VMOVDQArm:
21976 case VMOVDQArr:
21977 case VMOVDQArr_REV:
21978 return true;
21979 }
21980 return false;
21981}
21982
21983bool isVFNMSUB213SD(unsigned Opcode) {
21984 switch (Opcode) {
21985 case VFNMSUB213SDZm_Int:
21986 case VFNMSUB213SDZmk_Int:
21987 case VFNMSUB213SDZmkz_Int:
21988 case VFNMSUB213SDZr_Int:
21989 case VFNMSUB213SDZrb_Int:
21990 case VFNMSUB213SDZrbk_Int:
21991 case VFNMSUB213SDZrbkz_Int:
21992 case VFNMSUB213SDZrk_Int:
21993 case VFNMSUB213SDZrkz_Int:
21994 case VFNMSUB213SDm_Int:
21995 case VFNMSUB213SDr_Int:
21996 return true;
21997 }
21998 return false;
21999}
22000
22001bool isVMINPS(unsigned Opcode) {
22002 switch (Opcode) {
22003 case VMINPSYrm:
22004 case VMINPSYrr:
22005 case VMINPSZ128rm:
22006 case VMINPSZ128rmb:
22007 case VMINPSZ128rmbk:
22008 case VMINPSZ128rmbkz:
22009 case VMINPSZ128rmk:
22010 case VMINPSZ128rmkz:
22011 case VMINPSZ128rr:
22012 case VMINPSZ128rrk:
22013 case VMINPSZ128rrkz:
22014 case VMINPSZ256rm:
22015 case VMINPSZ256rmb:
22016 case VMINPSZ256rmbk:
22017 case VMINPSZ256rmbkz:
22018 case VMINPSZ256rmk:
22019 case VMINPSZ256rmkz:
22020 case VMINPSZ256rr:
22021 case VMINPSZ256rrk:
22022 case VMINPSZ256rrkz:
22023 case VMINPSZrm:
22024 case VMINPSZrmb:
22025 case VMINPSZrmbk:
22026 case VMINPSZrmbkz:
22027 case VMINPSZrmk:
22028 case VMINPSZrmkz:
22029 case VMINPSZrr:
22030 case VMINPSZrrb:
22031 case VMINPSZrrbk:
22032 case VMINPSZrrbkz:
22033 case VMINPSZrrk:
22034 case VMINPSZrrkz:
22035 case VMINPSrm:
22036 case VMINPSrr:
22037 return true;
22038 }
22039 return false;
22040}
22041
22042bool isVFMSUB231PS(unsigned Opcode) {
22043 switch (Opcode) {
22044 case VFMSUB231PSYm:
22045 case VFMSUB231PSYr:
22046 case VFMSUB231PSZ128m:
22047 case VFMSUB231PSZ128mb:
22048 case VFMSUB231PSZ128mbk:
22049 case VFMSUB231PSZ128mbkz:
22050 case VFMSUB231PSZ128mk:
22051 case VFMSUB231PSZ128mkz:
22052 case VFMSUB231PSZ128r:
22053 case VFMSUB231PSZ128rk:
22054 case VFMSUB231PSZ128rkz:
22055 case VFMSUB231PSZ256m:
22056 case VFMSUB231PSZ256mb:
22057 case VFMSUB231PSZ256mbk:
22058 case VFMSUB231PSZ256mbkz:
22059 case VFMSUB231PSZ256mk:
22060 case VFMSUB231PSZ256mkz:
22061 case VFMSUB231PSZ256r:
22062 case VFMSUB231PSZ256rk:
22063 case VFMSUB231PSZ256rkz:
22064 case VFMSUB231PSZm:
22065 case VFMSUB231PSZmb:
22066 case VFMSUB231PSZmbk:
22067 case VFMSUB231PSZmbkz:
22068 case VFMSUB231PSZmk:
22069 case VFMSUB231PSZmkz:
22070 case VFMSUB231PSZr:
22071 case VFMSUB231PSZrb:
22072 case VFMSUB231PSZrbk:
22073 case VFMSUB231PSZrbkz:
22074 case VFMSUB231PSZrk:
22075 case VFMSUB231PSZrkz:
22076 case VFMSUB231PSm:
22077 case VFMSUB231PSr:
22078 return true;
22079 }
22080 return false;
22081}
22082
22083bool isVPCOMPRESSB(unsigned Opcode) {
22084 switch (Opcode) {
22085 case VPCOMPRESSBZ128mr:
22086 case VPCOMPRESSBZ128mrk:
22087 case VPCOMPRESSBZ128rr:
22088 case VPCOMPRESSBZ128rrk:
22089 case VPCOMPRESSBZ128rrkz:
22090 case VPCOMPRESSBZ256mr:
22091 case VPCOMPRESSBZ256mrk:
22092 case VPCOMPRESSBZ256rr:
22093 case VPCOMPRESSBZ256rrk:
22094 case VPCOMPRESSBZ256rrkz:
22095 case VPCOMPRESSBZmr:
22096 case VPCOMPRESSBZmrk:
22097 case VPCOMPRESSBZrr:
22098 case VPCOMPRESSBZrrk:
22099 case VPCOMPRESSBZrrkz:
22100 return true;
22101 }
22102 return false;
22103}
22104
22105bool isVPCMPEQQ(unsigned Opcode) {
22106 switch (Opcode) {
22107 case VPCMPEQQYrm:
22108 case VPCMPEQQYrr:
22109 case VPCMPEQQZ128rm:
22110 case VPCMPEQQZ128rmb:
22111 case VPCMPEQQZ128rmbk:
22112 case VPCMPEQQZ128rmk:
22113 case VPCMPEQQZ128rr:
22114 case VPCMPEQQZ128rrk:
22115 case VPCMPEQQZ256rm:
22116 case VPCMPEQQZ256rmb:
22117 case VPCMPEQQZ256rmbk:
22118 case VPCMPEQQZ256rmk:
22119 case VPCMPEQQZ256rr:
22120 case VPCMPEQQZ256rrk:
22121 case VPCMPEQQZrm:
22122 case VPCMPEQQZrmb:
22123 case VPCMPEQQZrmbk:
22124 case VPCMPEQQZrmk:
22125 case VPCMPEQQZrr:
22126 case VPCMPEQQZrrk:
22127 case VPCMPEQQrm:
22128 case VPCMPEQQrr:
22129 return true;
22130 }
22131 return false;
22132}
22133
22134bool isVRCPSS(unsigned Opcode) {
22135 switch (Opcode) {
22136 case VRCPSSm_Int:
22137 case VRCPSSr_Int:
22138 return true;
22139 }
22140 return false;
22141}
22142
22143bool isVSCATTERPF1DPS(unsigned Opcode) {
22144 return Opcode == VSCATTERPF1DPSm;
22145}
22146
22147bool isVPHADDUBW(unsigned Opcode) {
22148 switch (Opcode) {
22149 case VPHADDUBWrm:
22150 case VPHADDUBWrr:
22151 return true;
22152 }
22153 return false;
22154}
22155
22156bool isXORPD(unsigned Opcode) {
22157 switch (Opcode) {
22158 case XORPDrm:
22159 case XORPDrr:
22160 return true;
22161 }
22162 return false;
22163}
22164
22165bool isVPSCATTERQQ(unsigned Opcode) {
22166 switch (Opcode) {
22167 case VPSCATTERQQZ128mr:
22168 case VPSCATTERQQZ256mr:
22169 case VPSCATTERQQZmr:
22170 return true;
22171 }
22172 return false;
22173}
22174
22175bool isVCVTW2PH(unsigned Opcode) {
22176 switch (Opcode) {
22177 case VCVTW2PHZ128rm:
22178 case VCVTW2PHZ128rmb:
22179 case VCVTW2PHZ128rmbk:
22180 case VCVTW2PHZ128rmbkz:
22181 case VCVTW2PHZ128rmk:
22182 case VCVTW2PHZ128rmkz:
22183 case VCVTW2PHZ128rr:
22184 case VCVTW2PHZ128rrk:
22185 case VCVTW2PHZ128rrkz:
22186 case VCVTW2PHZ256rm:
22187 case VCVTW2PHZ256rmb:
22188 case VCVTW2PHZ256rmbk:
22189 case VCVTW2PHZ256rmbkz:
22190 case VCVTW2PHZ256rmk:
22191 case VCVTW2PHZ256rmkz:
22192 case VCVTW2PHZ256rr:
22193 case VCVTW2PHZ256rrk:
22194 case VCVTW2PHZ256rrkz:
22195 case VCVTW2PHZrm:
22196 case VCVTW2PHZrmb:
22197 case VCVTW2PHZrmbk:
22198 case VCVTW2PHZrmbkz:
22199 case VCVTW2PHZrmk:
22200 case VCVTW2PHZrmkz:
22201 case VCVTW2PHZrr:
22202 case VCVTW2PHZrrb:
22203 case VCVTW2PHZrrbk:
22204 case VCVTW2PHZrrbkz:
22205 case VCVTW2PHZrrk:
22206 case VCVTW2PHZrrkz:
22207 return true;
22208 }
22209 return false;
22210}
22211
22212bool isVFMADDCPH(unsigned Opcode) {
22213 switch (Opcode) {
22214 case VFMADDCPHZ128m:
22215 case VFMADDCPHZ128mb:
22216 case VFMADDCPHZ128mbk:
22217 case VFMADDCPHZ128mbkz:
22218 case VFMADDCPHZ128mk:
22219 case VFMADDCPHZ128mkz:
22220 case VFMADDCPHZ128r:
22221 case VFMADDCPHZ128rk:
22222 case VFMADDCPHZ128rkz:
22223 case VFMADDCPHZ256m:
22224 case VFMADDCPHZ256mb:
22225 case VFMADDCPHZ256mbk:
22226 case VFMADDCPHZ256mbkz:
22227 case VFMADDCPHZ256mk:
22228 case VFMADDCPHZ256mkz:
22229 case VFMADDCPHZ256r:
22230 case VFMADDCPHZ256rk:
22231 case VFMADDCPHZ256rkz:
22232 case VFMADDCPHZm:
22233 case VFMADDCPHZmb:
22234 case VFMADDCPHZmbk:
22235 case VFMADDCPHZmbkz:
22236 case VFMADDCPHZmk:
22237 case VFMADDCPHZmkz:
22238 case VFMADDCPHZr:
22239 case VFMADDCPHZrb:
22240 case VFMADDCPHZrbk:
22241 case VFMADDCPHZrbkz:
22242 case VFMADDCPHZrk:
22243 case VFMADDCPHZrkz:
22244 return true;
22245 }
22246 return false;
22247}
22248
22249bool isVSUBPD(unsigned Opcode) {
22250 switch (Opcode) {
22251 case VSUBPDYrm:
22252 case VSUBPDYrr:
22253 case VSUBPDZ128rm:
22254 case VSUBPDZ128rmb:
22255 case VSUBPDZ128rmbk:
22256 case VSUBPDZ128rmbkz:
22257 case VSUBPDZ128rmk:
22258 case VSUBPDZ128rmkz:
22259 case VSUBPDZ128rr:
22260 case VSUBPDZ128rrk:
22261 case VSUBPDZ128rrkz:
22262 case VSUBPDZ256rm:
22263 case VSUBPDZ256rmb:
22264 case VSUBPDZ256rmbk:
22265 case VSUBPDZ256rmbkz:
22266 case VSUBPDZ256rmk:
22267 case VSUBPDZ256rmkz:
22268 case VSUBPDZ256rr:
22269 case VSUBPDZ256rrk:
22270 case VSUBPDZ256rrkz:
22271 case VSUBPDZrm:
22272 case VSUBPDZrmb:
22273 case VSUBPDZrmbk:
22274 case VSUBPDZrmbkz:
22275 case VSUBPDZrmk:
22276 case VSUBPDZrmkz:
22277 case VSUBPDZrr:
22278 case VSUBPDZrrb:
22279 case VSUBPDZrrbk:
22280 case VSUBPDZrrbkz:
22281 case VSUBPDZrrk:
22282 case VSUBPDZrrkz:
22283 case VSUBPDrm:
22284 case VSUBPDrr:
22285 return true;
22286 }
22287 return false;
22288}
22289
22290bool isVPACKUSDW(unsigned Opcode) {
22291 switch (Opcode) {
22292 case VPACKUSDWYrm:
22293 case VPACKUSDWYrr:
22294 case VPACKUSDWZ128rm:
22295 case VPACKUSDWZ128rmb:
22296 case VPACKUSDWZ128rmbk:
22297 case VPACKUSDWZ128rmbkz:
22298 case VPACKUSDWZ128rmk:
22299 case VPACKUSDWZ128rmkz:
22300 case VPACKUSDWZ128rr:
22301 case VPACKUSDWZ128rrk:
22302 case VPACKUSDWZ128rrkz:
22303 case VPACKUSDWZ256rm:
22304 case VPACKUSDWZ256rmb:
22305 case VPACKUSDWZ256rmbk:
22306 case VPACKUSDWZ256rmbkz:
22307 case VPACKUSDWZ256rmk:
22308 case VPACKUSDWZ256rmkz:
22309 case VPACKUSDWZ256rr:
22310 case VPACKUSDWZ256rrk:
22311 case VPACKUSDWZ256rrkz:
22312 case VPACKUSDWZrm:
22313 case VPACKUSDWZrmb:
22314 case VPACKUSDWZrmbk:
22315 case VPACKUSDWZrmbkz:
22316 case VPACKUSDWZrmk:
22317 case VPACKUSDWZrmkz:
22318 case VPACKUSDWZrr:
22319 case VPACKUSDWZrrk:
22320 case VPACKUSDWZrrkz:
22321 case VPACKUSDWrm:
22322 case VPACKUSDWrr:
22323 return true;
22324 }
22325 return false;
22326}
22327
22328bool isVSCALEFSS(unsigned Opcode) {
22329 switch (Opcode) {
22330 case VSCALEFSSZrm:
22331 case VSCALEFSSZrmk:
22332 case VSCALEFSSZrmkz:
22333 case VSCALEFSSZrr:
22334 case VSCALEFSSZrrb_Int:
22335 case VSCALEFSSZrrbk_Int:
22336 case VSCALEFSSZrrbkz_Int:
22337 case VSCALEFSSZrrk:
22338 case VSCALEFSSZrrkz:
22339 return true;
22340 }
22341 return false;
22342}
22343
22344bool isAESIMC(unsigned Opcode) {
22345 switch (Opcode) {
22346 case AESIMCrm:
22347 case AESIMCrr:
22348 return true;
22349 }
22350 return false;
22351}
22352
22353bool isVRCP28PS(unsigned Opcode) {
22354 switch (Opcode) {
22355 case VRCP28PSZm:
22356 case VRCP28PSZmb:
22357 case VRCP28PSZmbk:
22358 case VRCP28PSZmbkz:
22359 case VRCP28PSZmk:
22360 case VRCP28PSZmkz:
22361 case VRCP28PSZr:
22362 case VRCP28PSZrb:
22363 case VRCP28PSZrbk:
22364 case VRCP28PSZrbkz:
22365 case VRCP28PSZrk:
22366 case VRCP28PSZrkz:
22367 return true;
22368 }
22369 return false;
22370}
22371
22372bool isAAND(unsigned Opcode) {
22373 switch (Opcode) {
22374 case AAND32mr:
22375 case AAND32mr_EVEX:
22376 case AAND64mr:
22377 case AAND64mr_EVEX:
22378 return true;
22379 }
22380 return false;
22381}
22382
22383bool isDAA(unsigned Opcode) {
22384 return Opcode == DAA;
22385}
22386
22387bool isVCVTPD2UDQ(unsigned Opcode) {
22388 switch (Opcode) {
22389 case VCVTPD2UDQZ128rm:
22390 case VCVTPD2UDQZ128rmb:
22391 case VCVTPD2UDQZ128rmbk:
22392 case VCVTPD2UDQZ128rmbkz:
22393 case VCVTPD2UDQZ128rmk:
22394 case VCVTPD2UDQZ128rmkz:
22395 case VCVTPD2UDQZ128rr:
22396 case VCVTPD2UDQZ128rrk:
22397 case VCVTPD2UDQZ128rrkz:
22398 case VCVTPD2UDQZ256rm:
22399 case VCVTPD2UDQZ256rmb:
22400 case VCVTPD2UDQZ256rmbk:
22401 case VCVTPD2UDQZ256rmbkz:
22402 case VCVTPD2UDQZ256rmk:
22403 case VCVTPD2UDQZ256rmkz:
22404 case VCVTPD2UDQZ256rr:
22405 case VCVTPD2UDQZ256rrk:
22406 case VCVTPD2UDQZ256rrkz:
22407 case VCVTPD2UDQZrm:
22408 case VCVTPD2UDQZrmb:
22409 case VCVTPD2UDQZrmbk:
22410 case VCVTPD2UDQZrmbkz:
22411 case VCVTPD2UDQZrmk:
22412 case VCVTPD2UDQZrmkz:
22413 case VCVTPD2UDQZrr:
22414 case VCVTPD2UDQZrrb:
22415 case VCVTPD2UDQZrrbk:
22416 case VCVTPD2UDQZrrbkz:
22417 case VCVTPD2UDQZrrk:
22418 case VCVTPD2UDQZrrkz:
22419 return true;
22420 }
22421 return false;
22422}
22423
22424bool isKTESTW(unsigned Opcode) {
22425 return Opcode == KTESTWkk;
22426}
22427
22428bool isVPADDQ(unsigned Opcode) {
22429 switch (Opcode) {
22430 case VPADDQYrm:
22431 case VPADDQYrr:
22432 case VPADDQZ128rm:
22433 case VPADDQZ128rmb:
22434 case VPADDQZ128rmbk:
22435 case VPADDQZ128rmbkz:
22436 case VPADDQZ128rmk:
22437 case VPADDQZ128rmkz:
22438 case VPADDQZ128rr:
22439 case VPADDQZ128rrk:
22440 case VPADDQZ128rrkz:
22441 case VPADDQZ256rm:
22442 case VPADDQZ256rmb:
22443 case VPADDQZ256rmbk:
22444 case VPADDQZ256rmbkz:
22445 case VPADDQZ256rmk:
22446 case VPADDQZ256rmkz:
22447 case VPADDQZ256rr:
22448 case VPADDQZ256rrk:
22449 case VPADDQZ256rrkz:
22450 case VPADDQZrm:
22451 case VPADDQZrmb:
22452 case VPADDQZrmbk:
22453 case VPADDQZrmbkz:
22454 case VPADDQZrmk:
22455 case VPADDQZrmkz:
22456 case VPADDQZrr:
22457 case VPADDQZrrk:
22458 case VPADDQZrrkz:
22459 case VPADDQrm:
22460 case VPADDQrr:
22461 return true;
22462 }
22463 return false;
22464}
22465
22466bool isPALIGNR(unsigned Opcode) {
22467 switch (Opcode) {
22468 case MMX_PALIGNRrmi:
22469 case MMX_PALIGNRrri:
22470 case PALIGNRrmi:
22471 case PALIGNRrri:
22472 return true;
22473 }
22474 return false;
22475}
22476
22477bool isPMAXUW(unsigned Opcode) {
22478 switch (Opcode) {
22479 case PMAXUWrm:
22480 case PMAXUWrr:
22481 return true;
22482 }
22483 return false;
22484}
22485
22486bool isVFMADDSD(unsigned Opcode) {
22487 switch (Opcode) {
22488 case VFMADDSD4mr:
22489 case VFMADDSD4rm:
22490 case VFMADDSD4rr:
22491 case VFMADDSD4rr_REV:
22492 return true;
22493 }
22494 return false;
22495}
22496
22497bool isPFMAX(unsigned Opcode) {
22498 switch (Opcode) {
22499 case PFMAXrm:
22500 case PFMAXrr:
22501 return true;
22502 }
22503 return false;
22504}
22505
22506bool isVPOR(unsigned Opcode) {
22507 switch (Opcode) {
22508 case VPORYrm:
22509 case VPORYrr:
22510 case VPORrm:
22511 case VPORrr:
22512 return true;
22513 }
22514 return false;
22515}
22516
22517bool isVPSUBB(unsigned Opcode) {
22518 switch (Opcode) {
22519 case VPSUBBYrm:
22520 case VPSUBBYrr:
22521 case VPSUBBZ128rm:
22522 case VPSUBBZ128rmk:
22523 case VPSUBBZ128rmkz:
22524 case VPSUBBZ128rr:
22525 case VPSUBBZ128rrk:
22526 case VPSUBBZ128rrkz:
22527 case VPSUBBZ256rm:
22528 case VPSUBBZ256rmk:
22529 case VPSUBBZ256rmkz:
22530 case VPSUBBZ256rr:
22531 case VPSUBBZ256rrk:
22532 case VPSUBBZ256rrkz:
22533 case VPSUBBZrm:
22534 case VPSUBBZrmk:
22535 case VPSUBBZrmkz:
22536 case VPSUBBZrr:
22537 case VPSUBBZrrk:
22538 case VPSUBBZrrkz:
22539 case VPSUBBrm:
22540 case VPSUBBrr:
22541 return true;
22542 }
22543 return false;
22544}
22545
22546bool isVPAVGB(unsigned Opcode) {
22547 switch (Opcode) {
22548 case VPAVGBYrm:
22549 case VPAVGBYrr:
22550 case VPAVGBZ128rm:
22551 case VPAVGBZ128rmk:
22552 case VPAVGBZ128rmkz:
22553 case VPAVGBZ128rr:
22554 case VPAVGBZ128rrk:
22555 case VPAVGBZ128rrkz:
22556 case VPAVGBZ256rm:
22557 case VPAVGBZ256rmk:
22558 case VPAVGBZ256rmkz:
22559 case VPAVGBZ256rr:
22560 case VPAVGBZ256rrk:
22561 case VPAVGBZ256rrkz:
22562 case VPAVGBZrm:
22563 case VPAVGBZrmk:
22564 case VPAVGBZrmkz:
22565 case VPAVGBZrr:
22566 case VPAVGBZrrk:
22567 case VPAVGBZrrkz:
22568 case VPAVGBrm:
22569 case VPAVGBrr:
22570 return true;
22571 }
22572 return false;
22573}
22574
22575bool isINSB(unsigned Opcode) {
22576 return Opcode == INSB;
22577}
22578
22579bool isFYL2X(unsigned Opcode) {
22580 return Opcode == FYL2X;
22581}
22582
22583bool isVFNMSUB132PD(unsigned Opcode) {
22584 switch (Opcode) {
22585 case VFNMSUB132PDYm:
22586 case VFNMSUB132PDYr:
22587 case VFNMSUB132PDZ128m:
22588 case VFNMSUB132PDZ128mb:
22589 case VFNMSUB132PDZ128mbk:
22590 case VFNMSUB132PDZ128mbkz:
22591 case VFNMSUB132PDZ128mk:
22592 case VFNMSUB132PDZ128mkz:
22593 case VFNMSUB132PDZ128r:
22594 case VFNMSUB132PDZ128rk:
22595 case VFNMSUB132PDZ128rkz:
22596 case VFNMSUB132PDZ256m:
22597 case VFNMSUB132PDZ256mb:
22598 case VFNMSUB132PDZ256mbk:
22599 case VFNMSUB132PDZ256mbkz:
22600 case VFNMSUB132PDZ256mk:
22601 case VFNMSUB132PDZ256mkz:
22602 case VFNMSUB132PDZ256r:
22603 case VFNMSUB132PDZ256rk:
22604 case VFNMSUB132PDZ256rkz:
22605 case VFNMSUB132PDZm:
22606 case VFNMSUB132PDZmb:
22607 case VFNMSUB132PDZmbk:
22608 case VFNMSUB132PDZmbkz:
22609 case VFNMSUB132PDZmk:
22610 case VFNMSUB132PDZmkz:
22611 case VFNMSUB132PDZr:
22612 case VFNMSUB132PDZrb:
22613 case VFNMSUB132PDZrbk:
22614 case VFNMSUB132PDZrbkz:
22615 case VFNMSUB132PDZrk:
22616 case VFNMSUB132PDZrkz:
22617 case VFNMSUB132PDm:
22618 case VFNMSUB132PDr:
22619 return true;
22620 }
22621 return false;
22622}
22623
22624bool isVFNMSUBPS(unsigned Opcode) {
22625 switch (Opcode) {
22626 case VFNMSUBPS4Ymr:
22627 case VFNMSUBPS4Yrm:
22628 case VFNMSUBPS4Yrr:
22629 case VFNMSUBPS4Yrr_REV:
22630 case VFNMSUBPS4mr:
22631 case VFNMSUBPS4rm:
22632 case VFNMSUBPS4rr:
22633 case VFNMSUBPS4rr_REV:
22634 return true;
22635 }
22636 return false;
22637}
22638
22639bool isVFMADD231PS(unsigned Opcode) {
22640 switch (Opcode) {
22641 case VFMADD231PSYm:
22642 case VFMADD231PSYr:
22643 case VFMADD231PSZ128m:
22644 case VFMADD231PSZ128mb:
22645 case VFMADD231PSZ128mbk:
22646 case VFMADD231PSZ128mbkz:
22647 case VFMADD231PSZ128mk:
22648 case VFMADD231PSZ128mkz:
22649 case VFMADD231PSZ128r:
22650 case VFMADD231PSZ128rk:
22651 case VFMADD231PSZ128rkz:
22652 case VFMADD231PSZ256m:
22653 case VFMADD231PSZ256mb:
22654 case VFMADD231PSZ256mbk:
22655 case VFMADD231PSZ256mbkz:
22656 case VFMADD231PSZ256mk:
22657 case VFMADD231PSZ256mkz:
22658 case VFMADD231PSZ256r:
22659 case VFMADD231PSZ256rk:
22660 case VFMADD231PSZ256rkz:
22661 case VFMADD231PSZm:
22662 case VFMADD231PSZmb:
22663 case VFMADD231PSZmbk:
22664 case VFMADD231PSZmbkz:
22665 case VFMADD231PSZmk:
22666 case VFMADD231PSZmkz:
22667 case VFMADD231PSZr:
22668 case VFMADD231PSZrb:
22669 case VFMADD231PSZrbk:
22670 case VFMADD231PSZrbkz:
22671 case VFMADD231PSZrk:
22672 case VFMADD231PSZrkz:
22673 case VFMADD231PSm:
22674 case VFMADD231PSr:
22675 return true;
22676 }
22677 return false;
22678}
22679
22680bool isVCVTTSS2SI(unsigned Opcode) {
22681 switch (Opcode) {
22682 case VCVTTSS2SI64Zrm_Int:
22683 case VCVTTSS2SI64Zrr_Int:
22684 case VCVTTSS2SI64Zrrb_Int:
22685 case VCVTTSS2SI64rm_Int:
22686 case VCVTTSS2SI64rr_Int:
22687 case VCVTTSS2SIZrm_Int:
22688 case VCVTTSS2SIZrr_Int:
22689 case VCVTTSS2SIZrrb_Int:
22690 case VCVTTSS2SIrm_Int:
22691 case VCVTTSS2SIrr_Int:
22692 return true;
22693 }
22694 return false;
22695}
22696
22697bool isTCMMRLFP16PS(unsigned Opcode) {
22698 return Opcode == TCMMRLFP16PS;
22699}
22700
22701bool isFCOMPP(unsigned Opcode) {
22702 return Opcode == FCOMPP;
22703}
22704
22705bool isMOVD(unsigned Opcode) {
22706 switch (Opcode) {
22707 case MMX_MOVD64grr:
22708 case MMX_MOVD64mr:
22709 case MMX_MOVD64rm:
22710 case MMX_MOVD64rr:
22711 case MOVDI2PDIrm:
22712 case MOVDI2PDIrr:
22713 case MOVPDI2DImr:
22714 case MOVPDI2DIrr:
22715 return true;
22716 }
22717 return false;
22718}
22719
22720bool isMOVBE(unsigned Opcode) {
22721 switch (Opcode) {
22722 case MOVBE16mr:
22723 case MOVBE16mr_EVEX:
22724 case MOVBE16rm:
22725 case MOVBE16rm_EVEX:
22726 case MOVBE16rr:
22727 case MOVBE16rr_REV:
22728 case MOVBE32mr:
22729 case MOVBE32mr_EVEX:
22730 case MOVBE32rm:
22731 case MOVBE32rm_EVEX:
22732 case MOVBE32rr:
22733 case MOVBE32rr_REV:
22734 case MOVBE64mr:
22735 case MOVBE64mr_EVEX:
22736 case MOVBE64rm:
22737 case MOVBE64rm_EVEX:
22738 case MOVBE64rr:
22739 case MOVBE64rr_REV:
22740 return true;
22741 }
22742 return false;
22743}
22744
22745bool isVP2INTERSECTD(unsigned Opcode) {
22746 switch (Opcode) {
22747 case VP2INTERSECTDZ128rm:
22748 case VP2INTERSECTDZ128rmb:
22749 case VP2INTERSECTDZ128rr:
22750 case VP2INTERSECTDZ256rm:
22751 case VP2INTERSECTDZ256rmb:
22752 case VP2INTERSECTDZ256rr:
22753 case VP2INTERSECTDZrm:
22754 case VP2INTERSECTDZrmb:
22755 case VP2INTERSECTDZrr:
22756 return true;
22757 }
22758 return false;
22759}
22760
22761bool isVPMULLQ(unsigned Opcode) {
22762 switch (Opcode) {
22763 case VPMULLQZ128rm:
22764 case VPMULLQZ128rmb:
22765 case VPMULLQZ128rmbk:
22766 case VPMULLQZ128rmbkz:
22767 case VPMULLQZ128rmk:
22768 case VPMULLQZ128rmkz:
22769 case VPMULLQZ128rr:
22770 case VPMULLQZ128rrk:
22771 case VPMULLQZ128rrkz:
22772 case VPMULLQZ256rm:
22773 case VPMULLQZ256rmb:
22774 case VPMULLQZ256rmbk:
22775 case VPMULLQZ256rmbkz:
22776 case VPMULLQZ256rmk:
22777 case VPMULLQZ256rmkz:
22778 case VPMULLQZ256rr:
22779 case VPMULLQZ256rrk:
22780 case VPMULLQZ256rrkz:
22781 case VPMULLQZrm:
22782 case VPMULLQZrmb:
22783 case VPMULLQZrmbk:
22784 case VPMULLQZrmbkz:
22785 case VPMULLQZrmk:
22786 case VPMULLQZrmkz:
22787 case VPMULLQZrr:
22788 case VPMULLQZrrk:
22789 case VPMULLQZrrkz:
22790 return true;
22791 }
22792 return false;
22793}
22794
22795bool isVSCALEFPS(unsigned Opcode) {
22796 switch (Opcode) {
22797 case VSCALEFPSZ128rm:
22798 case VSCALEFPSZ128rmb:
22799 case VSCALEFPSZ128rmbk:
22800 case VSCALEFPSZ128rmbkz:
22801 case VSCALEFPSZ128rmk:
22802 case VSCALEFPSZ128rmkz:
22803 case VSCALEFPSZ128rr:
22804 case VSCALEFPSZ128rrk:
22805 case VSCALEFPSZ128rrkz:
22806 case VSCALEFPSZ256rm:
22807 case VSCALEFPSZ256rmb:
22808 case VSCALEFPSZ256rmbk:
22809 case VSCALEFPSZ256rmbkz:
22810 case VSCALEFPSZ256rmk:
22811 case VSCALEFPSZ256rmkz:
22812 case VSCALEFPSZ256rr:
22813 case VSCALEFPSZ256rrk:
22814 case VSCALEFPSZ256rrkz:
22815 case VSCALEFPSZrm:
22816 case VSCALEFPSZrmb:
22817 case VSCALEFPSZrmbk:
22818 case VSCALEFPSZrmbkz:
22819 case VSCALEFPSZrmk:
22820 case VSCALEFPSZrmkz:
22821 case VSCALEFPSZrr:
22822 case VSCALEFPSZrrb:
22823 case VSCALEFPSZrrbk:
22824 case VSCALEFPSZrrbkz:
22825 case VSCALEFPSZrrk:
22826 case VSCALEFPSZrrkz:
22827 return true;
22828 }
22829 return false;
22830}
22831
22832bool isVPMACSDQH(unsigned Opcode) {
22833 switch (Opcode) {
22834 case VPMACSDQHrm:
22835 case VPMACSDQHrr:
22836 return true;
22837 }
22838 return false;
22839}
22840
22841bool isVPTESTNMD(unsigned Opcode) {
22842 switch (Opcode) {
22843 case VPTESTNMDZ128rm:
22844 case VPTESTNMDZ128rmb:
22845 case VPTESTNMDZ128rmbk:
22846 case VPTESTNMDZ128rmk:
22847 case VPTESTNMDZ128rr:
22848 case VPTESTNMDZ128rrk:
22849 case VPTESTNMDZ256rm:
22850 case VPTESTNMDZ256rmb:
22851 case VPTESTNMDZ256rmbk:
22852 case VPTESTNMDZ256rmk:
22853 case VPTESTNMDZ256rr:
22854 case VPTESTNMDZ256rrk:
22855 case VPTESTNMDZrm:
22856 case VPTESTNMDZrmb:
22857 case VPTESTNMDZrmbk:
22858 case VPTESTNMDZrmk:
22859 case VPTESTNMDZrr:
22860 case VPTESTNMDZrrk:
22861 return true;
22862 }
22863 return false;
22864}
22865
22866bool isFCOMP(unsigned Opcode) {
22867 switch (Opcode) {
22868 case COMP_FST0r:
22869 case FCOMP32m:
22870 case FCOMP64m:
22871 return true;
22872 }
22873 return false;
22874}
22875
22876bool isPREFETCHWT1(unsigned Opcode) {
22877 return Opcode == PREFETCHWT1;
22878}
22879
22880bool isVCMPSD(unsigned Opcode) {
22881 switch (Opcode) {
22882 case VCMPSDZrmi_Int:
22883 case VCMPSDZrmik_Int:
22884 case VCMPSDZrri_Int:
22885 case VCMPSDZrrib_Int:
22886 case VCMPSDZrribk_Int:
22887 case VCMPSDZrrik_Int:
22888 case VCMPSDrmi_Int:
22889 case VCMPSDrri_Int:
22890 return true;
22891 }
22892 return false;
22893}
22894
22895bool isSGDTD(unsigned Opcode) {
22896 return Opcode == SGDT32m;
22897}
22898
22899bool isWRUSSD(unsigned Opcode) {
22900 switch (Opcode) {
22901 case WRUSSD:
22902 case WRUSSD_EVEX:
22903 return true;
22904 }
22905 return false;
22906}
22907
22908bool isFSUBP(unsigned Opcode) {
22909 return Opcode == SUB_FPrST0;
22910}
22911
22912bool isVUNPCKLPS(unsigned Opcode) {
22913 switch (Opcode) {
22914 case VUNPCKLPSYrm:
22915 case VUNPCKLPSYrr:
22916 case VUNPCKLPSZ128rm:
22917 case VUNPCKLPSZ128rmb:
22918 case VUNPCKLPSZ128rmbk:
22919 case VUNPCKLPSZ128rmbkz:
22920 case VUNPCKLPSZ128rmk:
22921 case VUNPCKLPSZ128rmkz:
22922 case VUNPCKLPSZ128rr:
22923 case VUNPCKLPSZ128rrk:
22924 case VUNPCKLPSZ128rrkz:
22925 case VUNPCKLPSZ256rm:
22926 case VUNPCKLPSZ256rmb:
22927 case VUNPCKLPSZ256rmbk:
22928 case VUNPCKLPSZ256rmbkz:
22929 case VUNPCKLPSZ256rmk:
22930 case VUNPCKLPSZ256rmkz:
22931 case VUNPCKLPSZ256rr:
22932 case VUNPCKLPSZ256rrk:
22933 case VUNPCKLPSZ256rrkz:
22934 case VUNPCKLPSZrm:
22935 case VUNPCKLPSZrmb:
22936 case VUNPCKLPSZrmbk:
22937 case VUNPCKLPSZrmbkz:
22938 case VUNPCKLPSZrmk:
22939 case VUNPCKLPSZrmkz:
22940 case VUNPCKLPSZrr:
22941 case VUNPCKLPSZrrk:
22942 case VUNPCKLPSZrrkz:
22943 case VUNPCKLPSrm:
22944 case VUNPCKLPSrr:
22945 return true;
22946 }
22947 return false;
22948}
22949
22950bool isVFNMSUB213SS(unsigned Opcode) {
22951 switch (Opcode) {
22952 case VFNMSUB213SSZm_Int:
22953 case VFNMSUB213SSZmk_Int:
22954 case VFNMSUB213SSZmkz_Int:
22955 case VFNMSUB213SSZr_Int:
22956 case VFNMSUB213SSZrb_Int:
22957 case VFNMSUB213SSZrbk_Int:
22958 case VFNMSUB213SSZrbkz_Int:
22959 case VFNMSUB213SSZrk_Int:
22960 case VFNMSUB213SSZrkz_Int:
22961 case VFNMSUB213SSm_Int:
22962 case VFNMSUB213SSr_Int:
22963 return true;
22964 }
22965 return false;
22966}
22967
22968bool isROUNDPD(unsigned Opcode) {
22969 switch (Opcode) {
22970 case ROUNDPDmi:
22971 case ROUNDPDri:
22972 return true;
22973 }
22974 return false;
22975}
22976
22977bool isVPMAXSW(unsigned Opcode) {
22978 switch (Opcode) {
22979 case VPMAXSWYrm:
22980 case VPMAXSWYrr:
22981 case VPMAXSWZ128rm:
22982 case VPMAXSWZ128rmk:
22983 case VPMAXSWZ128rmkz:
22984 case VPMAXSWZ128rr:
22985 case VPMAXSWZ128rrk:
22986 case VPMAXSWZ128rrkz:
22987 case VPMAXSWZ256rm:
22988 case VPMAXSWZ256rmk:
22989 case VPMAXSWZ256rmkz:
22990 case VPMAXSWZ256rr:
22991 case VPMAXSWZ256rrk:
22992 case VPMAXSWZ256rrkz:
22993 case VPMAXSWZrm:
22994 case VPMAXSWZrmk:
22995 case VPMAXSWZrmkz:
22996 case VPMAXSWZrr:
22997 case VPMAXSWZrrk:
22998 case VPMAXSWZrrkz:
22999 case VPMAXSWrm:
23000 case VPMAXSWrr:
23001 return true;
23002 }
23003 return false;
23004}
23005
23006bool isVCVTTPH2DQ(unsigned Opcode) {
23007 switch (Opcode) {
23008 case VCVTTPH2DQZ128rm:
23009 case VCVTTPH2DQZ128rmb:
23010 case VCVTTPH2DQZ128rmbk:
23011 case VCVTTPH2DQZ128rmbkz:
23012 case VCVTTPH2DQZ128rmk:
23013 case VCVTTPH2DQZ128rmkz:
23014 case VCVTTPH2DQZ128rr:
23015 case VCVTTPH2DQZ128rrk:
23016 case VCVTTPH2DQZ128rrkz:
23017 case VCVTTPH2DQZ256rm:
23018 case VCVTTPH2DQZ256rmb:
23019 case VCVTTPH2DQZ256rmbk:
23020 case VCVTTPH2DQZ256rmbkz:
23021 case VCVTTPH2DQZ256rmk:
23022 case VCVTTPH2DQZ256rmkz:
23023 case VCVTTPH2DQZ256rr:
23024 case VCVTTPH2DQZ256rrk:
23025 case VCVTTPH2DQZ256rrkz:
23026 case VCVTTPH2DQZrm:
23027 case VCVTTPH2DQZrmb:
23028 case VCVTTPH2DQZrmbk:
23029 case VCVTTPH2DQZrmbkz:
23030 case VCVTTPH2DQZrmk:
23031 case VCVTTPH2DQZrmkz:
23032 case VCVTTPH2DQZrr:
23033 case VCVTTPH2DQZrrb:
23034 case VCVTTPH2DQZrrbk:
23035 case VCVTTPH2DQZrrbkz:
23036 case VCVTTPH2DQZrrk:
23037 case VCVTTPH2DQZrrkz:
23038 return true;
23039 }
23040 return false;
23041}
23042
23043bool isVPUNPCKLWD(unsigned Opcode) {
23044 switch (Opcode) {
23045 case VPUNPCKLWDYrm:
23046 case VPUNPCKLWDYrr:
23047 case VPUNPCKLWDZ128rm:
23048 case VPUNPCKLWDZ128rmk:
23049 case VPUNPCKLWDZ128rmkz:
23050 case VPUNPCKLWDZ128rr:
23051 case VPUNPCKLWDZ128rrk:
23052 case VPUNPCKLWDZ128rrkz:
23053 case VPUNPCKLWDZ256rm:
23054 case VPUNPCKLWDZ256rmk:
23055 case VPUNPCKLWDZ256rmkz:
23056 case VPUNPCKLWDZ256rr:
23057 case VPUNPCKLWDZ256rrk:
23058 case VPUNPCKLWDZ256rrkz:
23059 case VPUNPCKLWDZrm:
23060 case VPUNPCKLWDZrmk:
23061 case VPUNPCKLWDZrmkz:
23062 case VPUNPCKLWDZrr:
23063 case VPUNPCKLWDZrrk:
23064 case VPUNPCKLWDZrrkz:
23065 case VPUNPCKLWDrm:
23066 case VPUNPCKLWDrr:
23067 return true;
23068 }
23069 return false;
23070}
23071
23072bool isKSHIFTLD(unsigned Opcode) {
23073 return Opcode == KSHIFTLDki;
23074}
23075
23076bool isTCVTROWPS2BF16H(unsigned Opcode) {
23077 switch (Opcode) {
23078 case TCVTROWPS2BF16Hrte:
23079 case TCVTROWPS2BF16Hrti:
23080 return true;
23081 }
23082 return false;
23083}
23084
23085bool isVFMADD231SD(unsigned Opcode) {
23086 switch (Opcode) {
23087 case VFMADD231SDZm_Int:
23088 case VFMADD231SDZmk_Int:
23089 case VFMADD231SDZmkz_Int:
23090 case VFMADD231SDZr_Int:
23091 case VFMADD231SDZrb_Int:
23092 case VFMADD231SDZrbk_Int:
23093 case VFMADD231SDZrbkz_Int:
23094 case VFMADD231SDZrk_Int:
23095 case VFMADD231SDZrkz_Int:
23096 case VFMADD231SDm_Int:
23097 case VFMADD231SDr_Int:
23098 return true;
23099 }
23100 return false;
23101}
23102
23103bool isADDPS(unsigned Opcode) {
23104 switch (Opcode) {
23105 case ADDPSrm:
23106 case ADDPSrr:
23107 return true;
23108 }
23109 return false;
23110}
23111
23112bool isVPSLLVD(unsigned Opcode) {
23113 switch (Opcode) {
23114 case VPSLLVDYrm:
23115 case VPSLLVDYrr:
23116 case VPSLLVDZ128rm:
23117 case VPSLLVDZ128rmb:
23118 case VPSLLVDZ128rmbk:
23119 case VPSLLVDZ128rmbkz:
23120 case VPSLLVDZ128rmk:
23121 case VPSLLVDZ128rmkz:
23122 case VPSLLVDZ128rr:
23123 case VPSLLVDZ128rrk:
23124 case VPSLLVDZ128rrkz:
23125 case VPSLLVDZ256rm:
23126 case VPSLLVDZ256rmb:
23127 case VPSLLVDZ256rmbk:
23128 case VPSLLVDZ256rmbkz:
23129 case VPSLLVDZ256rmk:
23130 case VPSLLVDZ256rmkz:
23131 case VPSLLVDZ256rr:
23132 case VPSLLVDZ256rrk:
23133 case VPSLLVDZ256rrkz:
23134 case VPSLLVDZrm:
23135 case VPSLLVDZrmb:
23136 case VPSLLVDZrmbk:
23137 case VPSLLVDZrmbkz:
23138 case VPSLLVDZrmk:
23139 case VPSLLVDZrmkz:
23140 case VPSLLVDZrr:
23141 case VPSLLVDZrrk:
23142 case VPSLLVDZrrkz:
23143 case VPSLLVDrm:
23144 case VPSLLVDrr:
23145 return true;
23146 }
23147 return false;
23148}
23149
23150bool isVFNMADD132SH(unsigned Opcode) {
23151 switch (Opcode) {
23152 case VFNMADD132SHZm_Int:
23153 case VFNMADD132SHZmk_Int:
23154 case VFNMADD132SHZmkz_Int:
23155 case VFNMADD132SHZr_Int:
23156 case VFNMADD132SHZrb_Int:
23157 case VFNMADD132SHZrbk_Int:
23158 case VFNMADD132SHZrbkz_Int:
23159 case VFNMADD132SHZrk_Int:
23160 case VFNMADD132SHZrkz_Int:
23161 return true;
23162 }
23163 return false;
23164}
23165
23166bool isVMOVNTPS(unsigned Opcode) {
23167 switch (Opcode) {
23168 case VMOVNTPSYmr:
23169 case VMOVNTPSZ128mr:
23170 case VMOVNTPSZ256mr:
23171 case VMOVNTPSZmr:
23172 case VMOVNTPSmr:
23173 return true;
23174 }
23175 return false;
23176}
23177
23178bool isVCVTPD2DQ(unsigned Opcode) {
23179 switch (Opcode) {
23180 case VCVTPD2DQYrm:
23181 case VCVTPD2DQYrr:
23182 case VCVTPD2DQZ128rm:
23183 case VCVTPD2DQZ128rmb:
23184 case VCVTPD2DQZ128rmbk:
23185 case VCVTPD2DQZ128rmbkz:
23186 case VCVTPD2DQZ128rmk:
23187 case VCVTPD2DQZ128rmkz:
23188 case VCVTPD2DQZ128rr:
23189 case VCVTPD2DQZ128rrk:
23190 case VCVTPD2DQZ128rrkz:
23191 case VCVTPD2DQZ256rm:
23192 case VCVTPD2DQZ256rmb:
23193 case VCVTPD2DQZ256rmbk:
23194 case VCVTPD2DQZ256rmbkz:
23195 case VCVTPD2DQZ256rmk:
23196 case VCVTPD2DQZ256rmkz:
23197 case VCVTPD2DQZ256rr:
23198 case VCVTPD2DQZ256rrk:
23199 case VCVTPD2DQZ256rrkz:
23200 case VCVTPD2DQZrm:
23201 case VCVTPD2DQZrmb:
23202 case VCVTPD2DQZrmbk:
23203 case VCVTPD2DQZrmbkz:
23204 case VCVTPD2DQZrmk:
23205 case VCVTPD2DQZrmkz:
23206 case VCVTPD2DQZrr:
23207 case VCVTPD2DQZrrb:
23208 case VCVTPD2DQZrrbk:
23209 case VCVTPD2DQZrrbkz:
23210 case VCVTPD2DQZrrk:
23211 case VCVTPD2DQZrrkz:
23212 case VCVTPD2DQrm:
23213 case VCVTPD2DQrr:
23214 return true;
23215 }
23216 return false;
23217}
23218
23219bool isVPXOR(unsigned Opcode) {
23220 switch (Opcode) {
23221 case VPXORYrm:
23222 case VPXORYrr:
23223 case VPXORrm:
23224 case VPXORrr:
23225 return true;
23226 }
23227 return false;
23228}
23229
23230bool isSTMXCSR(unsigned Opcode) {
23231 return Opcode == STMXCSR;
23232}
23233
23234bool isVRCP14SS(unsigned Opcode) {
23235 switch (Opcode) {
23236 case VRCP14SSZrm:
23237 case VRCP14SSZrmk:
23238 case VRCP14SSZrmkz:
23239 case VRCP14SSZrr:
23240 case VRCP14SSZrrk:
23241 case VRCP14SSZrrkz:
23242 return true;
23243 }
23244 return false;
23245}
23246
23247bool isUD2(unsigned Opcode) {
23248 return Opcode == TRAP;
23249}
23250
23251bool isVPOPCNTW(unsigned Opcode) {
23252 switch (Opcode) {
23253 case VPOPCNTWZ128rm:
23254 case VPOPCNTWZ128rmk:
23255 case VPOPCNTWZ128rmkz:
23256 case VPOPCNTWZ128rr:
23257 case VPOPCNTWZ128rrk:
23258 case VPOPCNTWZ128rrkz:
23259 case VPOPCNTWZ256rm:
23260 case VPOPCNTWZ256rmk:
23261 case VPOPCNTWZ256rmkz:
23262 case VPOPCNTWZ256rr:
23263 case VPOPCNTWZ256rrk:
23264 case VPOPCNTWZ256rrkz:
23265 case VPOPCNTWZrm:
23266 case VPOPCNTWZrmk:
23267 case VPOPCNTWZrmkz:
23268 case VPOPCNTWZrr:
23269 case VPOPCNTWZrrk:
23270 case VPOPCNTWZrrkz:
23271 return true;
23272 }
23273 return false;
23274}
23275
23276bool isVRSQRTSH(unsigned Opcode) {
23277 switch (Opcode) {
23278 case VRSQRTSHZrm:
23279 case VRSQRTSHZrmk:
23280 case VRSQRTSHZrmkz:
23281 case VRSQRTSHZrr:
23282 case VRSQRTSHZrrk:
23283 case VRSQRTSHZrrkz:
23284 return true;
23285 }
23286 return false;
23287}
23288
23289bool isVSCATTERPF0DPD(unsigned Opcode) {
23290 return Opcode == VSCATTERPF0DPDm;
23291}
23292
23293bool isVFMADDPS(unsigned Opcode) {
23294 switch (Opcode) {
23295 case VFMADDPS4Ymr:
23296 case VFMADDPS4Yrm:
23297 case VFMADDPS4Yrr:
23298 case VFMADDPS4Yrr_REV:
23299 case VFMADDPS4mr:
23300 case VFMADDPS4rm:
23301 case VFMADDPS4rr:
23302 case VFMADDPS4rr_REV:
23303 return true;
23304 }
23305 return false;
23306}
23307
23308bool isXSAVEC64(unsigned Opcode) {
23309 return Opcode == XSAVEC64;
23310}
23311
23312bool isVPMADDUBSW(unsigned Opcode) {
23313 switch (Opcode) {
23314 case VPMADDUBSWYrm:
23315 case VPMADDUBSWYrr:
23316 case VPMADDUBSWZ128rm:
23317 case VPMADDUBSWZ128rmk:
23318 case VPMADDUBSWZ128rmkz:
23319 case VPMADDUBSWZ128rr:
23320 case VPMADDUBSWZ128rrk:
23321 case VPMADDUBSWZ128rrkz:
23322 case VPMADDUBSWZ256rm:
23323 case VPMADDUBSWZ256rmk:
23324 case VPMADDUBSWZ256rmkz:
23325 case VPMADDUBSWZ256rr:
23326 case VPMADDUBSWZ256rrk:
23327 case VPMADDUBSWZ256rrkz:
23328 case VPMADDUBSWZrm:
23329 case VPMADDUBSWZrmk:
23330 case VPMADDUBSWZrmkz:
23331 case VPMADDUBSWZrr:
23332 case VPMADDUBSWZrrk:
23333 case VPMADDUBSWZrrkz:
23334 case VPMADDUBSWrm:
23335 case VPMADDUBSWrr:
23336 return true;
23337 }
23338 return false;
23339}
23340
23341bool isVPMOVZXDQ(unsigned Opcode) {
23342 switch (Opcode) {
23343 case VPMOVZXDQYrm:
23344 case VPMOVZXDQYrr:
23345 case VPMOVZXDQZ128rm:
23346 case VPMOVZXDQZ128rmk:
23347 case VPMOVZXDQZ128rmkz:
23348 case VPMOVZXDQZ128rr:
23349 case VPMOVZXDQZ128rrk:
23350 case VPMOVZXDQZ128rrkz:
23351 case VPMOVZXDQZ256rm:
23352 case VPMOVZXDQZ256rmk:
23353 case VPMOVZXDQZ256rmkz:
23354 case VPMOVZXDQZ256rr:
23355 case VPMOVZXDQZ256rrk:
23356 case VPMOVZXDQZ256rrkz:
23357 case VPMOVZXDQZrm:
23358 case VPMOVZXDQZrmk:
23359 case VPMOVZXDQZrmkz:
23360 case VPMOVZXDQZrr:
23361 case VPMOVZXDQZrrk:
23362 case VPMOVZXDQZrrkz:
23363 case VPMOVZXDQrm:
23364 case VPMOVZXDQrr:
23365 return true;
23366 }
23367 return false;
23368}
23369
23370bool isVRCP14PS(unsigned Opcode) {
23371 switch (Opcode) {
23372 case VRCP14PSZ128m:
23373 case VRCP14PSZ128mb:
23374 case VRCP14PSZ128mbk:
23375 case VRCP14PSZ128mbkz:
23376 case VRCP14PSZ128mk:
23377 case VRCP14PSZ128mkz:
23378 case VRCP14PSZ128r:
23379 case VRCP14PSZ128rk:
23380 case VRCP14PSZ128rkz:
23381 case VRCP14PSZ256m:
23382 case VRCP14PSZ256mb:
23383 case VRCP14PSZ256mbk:
23384 case VRCP14PSZ256mbkz:
23385 case VRCP14PSZ256mk:
23386 case VRCP14PSZ256mkz:
23387 case VRCP14PSZ256r:
23388 case VRCP14PSZ256rk:
23389 case VRCP14PSZ256rkz:
23390 case VRCP14PSZm:
23391 case VRCP14PSZmb:
23392 case VRCP14PSZmbk:
23393 case VRCP14PSZmbkz:
23394 case VRCP14PSZmk:
23395 case VRCP14PSZmkz:
23396 case VRCP14PSZr:
23397 case VRCP14PSZrk:
23398 case VRCP14PSZrkz:
23399 return true;
23400 }
23401 return false;
23402}
23403
23404bool isVSQRTSH(unsigned Opcode) {
23405 switch (Opcode) {
23406 case VSQRTSHZm_Int:
23407 case VSQRTSHZmk_Int:
23408 case VSQRTSHZmkz_Int:
23409 case VSQRTSHZr_Int:
23410 case VSQRTSHZrb_Int:
23411 case VSQRTSHZrbk_Int:
23412 case VSQRTSHZrbkz_Int:
23413 case VSQRTSHZrk_Int:
23414 case VSQRTSHZrkz_Int:
23415 return true;
23416 }
23417 return false;
23418}
23419
23420bool isTCVTROWD2PS(unsigned Opcode) {
23421 switch (Opcode) {
23422 case TCVTROWD2PSrte:
23423 case TCVTROWD2PSrti:
23424 return true;
23425 }
23426 return false;
23427}
23428
23429bool isLOOP(unsigned Opcode) {
23430 return Opcode == LOOP;
23431}
23432
23433bool isSTUI(unsigned Opcode) {
23434 return Opcode == STUI;
23435}
23436
23437bool isVCVTTPS2UDQ(unsigned Opcode) {
23438 switch (Opcode) {
23439 case VCVTTPS2UDQZ128rm:
23440 case VCVTTPS2UDQZ128rmb:
23441 case VCVTTPS2UDQZ128rmbk:
23442 case VCVTTPS2UDQZ128rmbkz:
23443 case VCVTTPS2UDQZ128rmk:
23444 case VCVTTPS2UDQZ128rmkz:
23445 case VCVTTPS2UDQZ128rr:
23446 case VCVTTPS2UDQZ128rrk:
23447 case VCVTTPS2UDQZ128rrkz:
23448 case VCVTTPS2UDQZ256rm:
23449 case VCVTTPS2UDQZ256rmb:
23450 case VCVTTPS2UDQZ256rmbk:
23451 case VCVTTPS2UDQZ256rmbkz:
23452 case VCVTTPS2UDQZ256rmk:
23453 case VCVTTPS2UDQZ256rmkz:
23454 case VCVTTPS2UDQZ256rr:
23455 case VCVTTPS2UDQZ256rrk:
23456 case VCVTTPS2UDQZ256rrkz:
23457 case VCVTTPS2UDQZrm:
23458 case VCVTTPS2UDQZrmb:
23459 case VCVTTPS2UDQZrmbk:
23460 case VCVTTPS2UDQZrmbkz:
23461 case VCVTTPS2UDQZrmk:
23462 case VCVTTPS2UDQZrmkz:
23463 case VCVTTPS2UDQZrr:
23464 case VCVTTPS2UDQZrrb:
23465 case VCVTTPS2UDQZrrbk:
23466 case VCVTTPS2UDQZrrbkz:
23467 case VCVTTPS2UDQZrrk:
23468 case VCVTTPS2UDQZrrkz:
23469 return true;
23470 }
23471 return false;
23472}
23473
23474bool isVCOMPRESSPS(unsigned Opcode) {
23475 switch (Opcode) {
23476 case VCOMPRESSPSZ128mr:
23477 case VCOMPRESSPSZ128mrk:
23478 case VCOMPRESSPSZ128rr:
23479 case VCOMPRESSPSZ128rrk:
23480 case VCOMPRESSPSZ128rrkz:
23481 case VCOMPRESSPSZ256mr:
23482 case VCOMPRESSPSZ256mrk:
23483 case VCOMPRESSPSZ256rr:
23484 case VCOMPRESSPSZ256rrk:
23485 case VCOMPRESSPSZ256rrkz:
23486 case VCOMPRESSPSZmr:
23487 case VCOMPRESSPSZmrk:
23488 case VCOMPRESSPSZrr:
23489 case VCOMPRESSPSZrrk:
23490 case VCOMPRESSPSZrrkz:
23491 return true;
23492 }
23493 return false;
23494}
23495
23496bool isXABORT(unsigned Opcode) {
23497 return Opcode == XABORT;
23498}
23499
23500bool isVCVTTBF162IUBS(unsigned Opcode) {
23501 switch (Opcode) {
23502 case VCVTTBF162IUBSZ128rm:
23503 case VCVTTBF162IUBSZ128rmb:
23504 case VCVTTBF162IUBSZ128rmbk:
23505 case VCVTTBF162IUBSZ128rmbkz:
23506 case VCVTTBF162IUBSZ128rmk:
23507 case VCVTTBF162IUBSZ128rmkz:
23508 case VCVTTBF162IUBSZ128rr:
23509 case VCVTTBF162IUBSZ128rrk:
23510 case VCVTTBF162IUBSZ128rrkz:
23511 case VCVTTBF162IUBSZ256rm:
23512 case VCVTTBF162IUBSZ256rmb:
23513 case VCVTTBF162IUBSZ256rmbk:
23514 case VCVTTBF162IUBSZ256rmbkz:
23515 case VCVTTBF162IUBSZ256rmk:
23516 case VCVTTBF162IUBSZ256rmkz:
23517 case VCVTTBF162IUBSZ256rr:
23518 case VCVTTBF162IUBSZ256rrk:
23519 case VCVTTBF162IUBSZ256rrkz:
23520 case VCVTTBF162IUBSZrm:
23521 case VCVTTBF162IUBSZrmb:
23522 case VCVTTBF162IUBSZrmbk:
23523 case VCVTTBF162IUBSZrmbkz:
23524 case VCVTTBF162IUBSZrmk:
23525 case VCVTTBF162IUBSZrmkz:
23526 case VCVTTBF162IUBSZrr:
23527 case VCVTTBF162IUBSZrrk:
23528 case VCVTTBF162IUBSZrrkz:
23529 return true;
23530 }
23531 return false;
23532}
23533
23534bool isVPADDW(unsigned Opcode) {
23535 switch (Opcode) {
23536 case VPADDWYrm:
23537 case VPADDWYrr:
23538 case VPADDWZ128rm:
23539 case VPADDWZ128rmk:
23540 case VPADDWZ128rmkz:
23541 case VPADDWZ128rr:
23542 case VPADDWZ128rrk:
23543 case VPADDWZ128rrkz:
23544 case VPADDWZ256rm:
23545 case VPADDWZ256rmk:
23546 case VPADDWZ256rmkz:
23547 case VPADDWZ256rr:
23548 case VPADDWZ256rrk:
23549 case VPADDWZ256rrkz:
23550 case VPADDWZrm:
23551 case VPADDWZrmk:
23552 case VPADDWZrmkz:
23553 case VPADDWZrr:
23554 case VPADDWZrrk:
23555 case VPADDWZrrkz:
23556 case VPADDWrm:
23557 case VPADDWrr:
23558 return true;
23559 }
23560 return false;
23561}
23562
23563bool isVRNDSCALEPS(unsigned Opcode) {
23564 switch (Opcode) {
23565 case VRNDSCALEPSZ128rmbi:
23566 case VRNDSCALEPSZ128rmbik:
23567 case VRNDSCALEPSZ128rmbikz:
23568 case VRNDSCALEPSZ128rmi:
23569 case VRNDSCALEPSZ128rmik:
23570 case VRNDSCALEPSZ128rmikz:
23571 case VRNDSCALEPSZ128rri:
23572 case VRNDSCALEPSZ128rrik:
23573 case VRNDSCALEPSZ128rrikz:
23574 case VRNDSCALEPSZ256rmbi:
23575 case VRNDSCALEPSZ256rmbik:
23576 case VRNDSCALEPSZ256rmbikz:
23577 case VRNDSCALEPSZ256rmi:
23578 case VRNDSCALEPSZ256rmik:
23579 case VRNDSCALEPSZ256rmikz:
23580 case VRNDSCALEPSZ256rri:
23581 case VRNDSCALEPSZ256rrik:
23582 case VRNDSCALEPSZ256rrikz:
23583 case VRNDSCALEPSZrmbi:
23584 case VRNDSCALEPSZrmbik:
23585 case VRNDSCALEPSZrmbikz:
23586 case VRNDSCALEPSZrmi:
23587 case VRNDSCALEPSZrmik:
23588 case VRNDSCALEPSZrmikz:
23589 case VRNDSCALEPSZrri:
23590 case VRNDSCALEPSZrrib:
23591 case VRNDSCALEPSZrribk:
23592 case VRNDSCALEPSZrribkz:
23593 case VRNDSCALEPSZrrik:
23594 case VRNDSCALEPSZrrikz:
23595 return true;
23596 }
23597 return false;
23598}
23599
23600bool isVPSIGND(unsigned Opcode) {
23601 switch (Opcode) {
23602 case VPSIGNDYrm:
23603 case VPSIGNDYrr:
23604 case VPSIGNDrm:
23605 case VPSIGNDrr:
23606 return true;
23607 }
23608 return false;
23609}
23610
23611bool isVPHADDUWD(unsigned Opcode) {
23612 switch (Opcode) {
23613 case VPHADDUWDrm:
23614 case VPHADDUWDrr:
23615 return true;
23616 }
23617 return false;
23618}
23619
23620bool isVCVT2PH2HF8S(unsigned Opcode) {
23621 switch (Opcode) {
23622 case VCVT2PH2HF8SZ128rm:
23623 case VCVT2PH2HF8SZ128rmb:
23624 case VCVT2PH2HF8SZ128rmbk:
23625 case VCVT2PH2HF8SZ128rmbkz:
23626 case VCVT2PH2HF8SZ128rmk:
23627 case VCVT2PH2HF8SZ128rmkz:
23628 case VCVT2PH2HF8SZ128rr:
23629 case VCVT2PH2HF8SZ128rrk:
23630 case VCVT2PH2HF8SZ128rrkz:
23631 case VCVT2PH2HF8SZ256rm:
23632 case VCVT2PH2HF8SZ256rmb:
23633 case VCVT2PH2HF8SZ256rmbk:
23634 case VCVT2PH2HF8SZ256rmbkz:
23635 case VCVT2PH2HF8SZ256rmk:
23636 case VCVT2PH2HF8SZ256rmkz:
23637 case VCVT2PH2HF8SZ256rr:
23638 case VCVT2PH2HF8SZ256rrk:
23639 case VCVT2PH2HF8SZ256rrkz:
23640 case VCVT2PH2HF8SZrm:
23641 case VCVT2PH2HF8SZrmb:
23642 case VCVT2PH2HF8SZrmbk:
23643 case VCVT2PH2HF8SZrmbkz:
23644 case VCVT2PH2HF8SZrmk:
23645 case VCVT2PH2HF8SZrmkz:
23646 case VCVT2PH2HF8SZrr:
23647 case VCVT2PH2HF8SZrrk:
23648 case VCVT2PH2HF8SZrrkz:
23649 return true;
23650 }
23651 return false;
23652}
23653
23654bool isVDBPSADBW(unsigned Opcode) {
23655 switch (Opcode) {
23656 case VDBPSADBWZ128rmi:
23657 case VDBPSADBWZ128rmik:
23658 case VDBPSADBWZ128rmikz:
23659 case VDBPSADBWZ128rri:
23660 case VDBPSADBWZ128rrik:
23661 case VDBPSADBWZ128rrikz:
23662 case VDBPSADBWZ256rmi:
23663 case VDBPSADBWZ256rmik:
23664 case VDBPSADBWZ256rmikz:
23665 case VDBPSADBWZ256rri:
23666 case VDBPSADBWZ256rrik:
23667 case VDBPSADBWZ256rrikz:
23668 case VDBPSADBWZrmi:
23669 case VDBPSADBWZrmik:
23670 case VDBPSADBWZrmikz:
23671 case VDBPSADBWZrri:
23672 case VDBPSADBWZrrik:
23673 case VDBPSADBWZrrikz:
23674 return true;
23675 }
23676 return false;
23677}
23678
23679bool isPSLLW(unsigned Opcode) {
23680 switch (Opcode) {
23681 case MMX_PSLLWri:
23682 case MMX_PSLLWrm:
23683 case MMX_PSLLWrr:
23684 case PSLLWri:
23685 case PSLLWrm:
23686 case PSLLWrr:
23687 return true;
23688 }
23689 return false;
23690}
23691
23692bool isVPMOVQD(unsigned Opcode) {
23693 switch (Opcode) {
23694 case VPMOVQDZ128mr:
23695 case VPMOVQDZ128mrk:
23696 case VPMOVQDZ128rr:
23697 case VPMOVQDZ128rrk:
23698 case VPMOVQDZ128rrkz:
23699 case VPMOVQDZ256mr:
23700 case VPMOVQDZ256mrk:
23701 case VPMOVQDZ256rr:
23702 case VPMOVQDZ256rrk:
23703 case VPMOVQDZ256rrkz:
23704 case VPMOVQDZmr:
23705 case VPMOVQDZmrk:
23706 case VPMOVQDZrr:
23707 case VPMOVQDZrrk:
23708 case VPMOVQDZrrkz:
23709 return true;
23710 }
23711 return false;
23712}
23713
23714bool isVINSERTI64X4(unsigned Opcode) {
23715 switch (Opcode) {
23716 case VINSERTI64X4Zrmi:
23717 case VINSERTI64X4Zrmik:
23718 case VINSERTI64X4Zrmikz:
23719 case VINSERTI64X4Zrri:
23720 case VINSERTI64X4Zrrik:
23721 case VINSERTI64X4Zrrikz:
23722 return true;
23723 }
23724 return false;
23725}
23726
23727bool isVPERMI2PS(unsigned Opcode) {
23728 switch (Opcode) {
23729 case VPERMI2PSZ128rm:
23730 case VPERMI2PSZ128rmb:
23731 case VPERMI2PSZ128rmbk:
23732 case VPERMI2PSZ128rmbkz:
23733 case VPERMI2PSZ128rmk:
23734 case VPERMI2PSZ128rmkz:
23735 case VPERMI2PSZ128rr:
23736 case VPERMI2PSZ128rrk:
23737 case VPERMI2PSZ128rrkz:
23738 case VPERMI2PSZ256rm:
23739 case VPERMI2PSZ256rmb:
23740 case VPERMI2PSZ256rmbk:
23741 case VPERMI2PSZ256rmbkz:
23742 case VPERMI2PSZ256rmk:
23743 case VPERMI2PSZ256rmkz:
23744 case VPERMI2PSZ256rr:
23745 case VPERMI2PSZ256rrk:
23746 case VPERMI2PSZ256rrkz:
23747 case VPERMI2PSZrm:
23748 case VPERMI2PSZrmb:
23749 case VPERMI2PSZrmbk:
23750 case VPERMI2PSZrmbkz:
23751 case VPERMI2PSZrmk:
23752 case VPERMI2PSZrmkz:
23753 case VPERMI2PSZrr:
23754 case VPERMI2PSZrrk:
23755 case VPERMI2PSZrrkz:
23756 return true;
23757 }
23758 return false;
23759}
23760
23761bool isVMULPH(unsigned Opcode) {
23762 switch (Opcode) {
23763 case VMULPHZ128rm:
23764 case VMULPHZ128rmb:
23765 case VMULPHZ128rmbk:
23766 case VMULPHZ128rmbkz:
23767 case VMULPHZ128rmk:
23768 case VMULPHZ128rmkz:
23769 case VMULPHZ128rr:
23770 case VMULPHZ128rrk:
23771 case VMULPHZ128rrkz:
23772 case VMULPHZ256rm:
23773 case VMULPHZ256rmb:
23774 case VMULPHZ256rmbk:
23775 case VMULPHZ256rmbkz:
23776 case VMULPHZ256rmk:
23777 case VMULPHZ256rmkz:
23778 case VMULPHZ256rr:
23779 case VMULPHZ256rrk:
23780 case VMULPHZ256rrkz:
23781 case VMULPHZrm:
23782 case VMULPHZrmb:
23783 case VMULPHZrmbk:
23784 case VMULPHZrmbkz:
23785 case VMULPHZrmk:
23786 case VMULPHZrmkz:
23787 case VMULPHZrr:
23788 case VMULPHZrrb:
23789 case VMULPHZrrbk:
23790 case VMULPHZrrbkz:
23791 case VMULPHZrrk:
23792 case VMULPHZrrkz:
23793 return true;
23794 }
23795 return false;
23796}
23797
23798bool isVPCMPUQ(unsigned Opcode) {
23799 switch (Opcode) {
23800 case VPCMPUQZ128rmbi:
23801 case VPCMPUQZ128rmbik:
23802 case VPCMPUQZ128rmi:
23803 case VPCMPUQZ128rmik:
23804 case VPCMPUQZ128rri:
23805 case VPCMPUQZ128rrik:
23806 case VPCMPUQZ256rmbi:
23807 case VPCMPUQZ256rmbik:
23808 case VPCMPUQZ256rmi:
23809 case VPCMPUQZ256rmik:
23810 case VPCMPUQZ256rri:
23811 case VPCMPUQZ256rrik:
23812 case VPCMPUQZrmbi:
23813 case VPCMPUQZrmbik:
23814 case VPCMPUQZrmi:
23815 case VPCMPUQZrmik:
23816 case VPCMPUQZrri:
23817 case VPCMPUQZrrik:
23818 return true;
23819 }
23820 return false;
23821}
23822
23823bool isVCVTUSI2SD(unsigned Opcode) {
23824 switch (Opcode) {
23825 case VCVTUSI2SDZrm_Int:
23826 case VCVTUSI2SDZrr_Int:
23827 case VCVTUSI642SDZrm_Int:
23828 case VCVTUSI642SDZrr_Int:
23829 case VCVTUSI642SDZrrb_Int:
23830 return true;
23831 }
23832 return false;
23833}
23834
23835bool isKXNORW(unsigned Opcode) {
23836 return Opcode == KXNORWkk;
23837}
23838
23839bool isBLCIC(unsigned Opcode) {
23840 switch (Opcode) {
23841 case BLCIC32rm:
23842 case BLCIC32rr:
23843 case BLCIC64rm:
23844 case BLCIC64rr:
23845 return true;
23846 }
23847 return false;
23848}
23849
23850bool isVFNMADD213SD(unsigned Opcode) {
23851 switch (Opcode) {
23852 case VFNMADD213SDZm_Int:
23853 case VFNMADD213SDZmk_Int:
23854 case VFNMADD213SDZmkz_Int:
23855 case VFNMADD213SDZr_Int:
23856 case VFNMADD213SDZrb_Int:
23857 case VFNMADD213SDZrbk_Int:
23858 case VFNMADD213SDZrbkz_Int:
23859 case VFNMADD213SDZrk_Int:
23860 case VFNMADD213SDZrkz_Int:
23861 case VFNMADD213SDm_Int:
23862 case VFNMADD213SDr_Int:
23863 return true;
23864 }
23865 return false;
23866}
23867
23868bool isVPMACSWW(unsigned Opcode) {
23869 switch (Opcode) {
23870 case VPMACSWWrm:
23871 case VPMACSWWrr:
23872 return true;
23873 }
23874 return false;
23875}
23876
23877bool isVMOVLPS(unsigned Opcode) {
23878 switch (Opcode) {
23879 case VMOVLPSZ128mr:
23880 case VMOVLPSZ128rm:
23881 case VMOVLPSmr:
23882 case VMOVLPSrm:
23883 return true;
23884 }
23885 return false;
23886}
23887
23888bool isPCONFIG(unsigned Opcode) {
23889 return Opcode == PCONFIG;
23890}
23891
23892bool isPANDN(unsigned Opcode) {
23893 switch (Opcode) {
23894 case MMX_PANDNrm:
23895 case MMX_PANDNrr:
23896 case PANDNrm:
23897 case PANDNrr:
23898 return true;
23899 }
23900 return false;
23901}
23902
23903bool isVGETEXPPD(unsigned Opcode) {
23904 switch (Opcode) {
23905 case VGETEXPPDZ128m:
23906 case VGETEXPPDZ128mb:
23907 case VGETEXPPDZ128mbk:
23908 case VGETEXPPDZ128mbkz:
23909 case VGETEXPPDZ128mk:
23910 case VGETEXPPDZ128mkz:
23911 case VGETEXPPDZ128r:
23912 case VGETEXPPDZ128rk:
23913 case VGETEXPPDZ128rkz:
23914 case VGETEXPPDZ256m:
23915 case VGETEXPPDZ256mb:
23916 case VGETEXPPDZ256mbk:
23917 case VGETEXPPDZ256mbkz:
23918 case VGETEXPPDZ256mk:
23919 case VGETEXPPDZ256mkz:
23920 case VGETEXPPDZ256r:
23921 case VGETEXPPDZ256rk:
23922 case VGETEXPPDZ256rkz:
23923 case VGETEXPPDZm:
23924 case VGETEXPPDZmb:
23925 case VGETEXPPDZmbk:
23926 case VGETEXPPDZmbkz:
23927 case VGETEXPPDZmk:
23928 case VGETEXPPDZmkz:
23929 case VGETEXPPDZr:
23930 case VGETEXPPDZrb:
23931 case VGETEXPPDZrbk:
23932 case VGETEXPPDZrbkz:
23933 case VGETEXPPDZrk:
23934 case VGETEXPPDZrkz:
23935 return true;
23936 }
23937 return false;
23938}
23939
23940bool isVPSRLVQ(unsigned Opcode) {
23941 switch (Opcode) {
23942 case VPSRLVQYrm:
23943 case VPSRLVQYrr:
23944 case VPSRLVQZ128rm:
23945 case VPSRLVQZ128rmb:
23946 case VPSRLVQZ128rmbk:
23947 case VPSRLVQZ128rmbkz:
23948 case VPSRLVQZ128rmk:
23949 case VPSRLVQZ128rmkz:
23950 case VPSRLVQZ128rr:
23951 case VPSRLVQZ128rrk:
23952 case VPSRLVQZ128rrkz:
23953 case VPSRLVQZ256rm:
23954 case VPSRLVQZ256rmb:
23955 case VPSRLVQZ256rmbk:
23956 case VPSRLVQZ256rmbkz:
23957 case VPSRLVQZ256rmk:
23958 case VPSRLVQZ256rmkz:
23959 case VPSRLVQZ256rr:
23960 case VPSRLVQZ256rrk:
23961 case VPSRLVQZ256rrkz:
23962 case VPSRLVQZrm:
23963 case VPSRLVQZrmb:
23964 case VPSRLVQZrmbk:
23965 case VPSRLVQZrmbkz:
23966 case VPSRLVQZrmk:
23967 case VPSRLVQZrmkz:
23968 case VPSRLVQZrr:
23969 case VPSRLVQZrrk:
23970 case VPSRLVQZrrkz:
23971 case VPSRLVQrm:
23972 case VPSRLVQrr:
23973 return true;
23974 }
23975 return false;
23976}
23977
23978bool isUD1(unsigned Opcode) {
23979 switch (Opcode) {
23980 case UD1Lm:
23981 case UD1Lr:
23982 case UD1Qm:
23983 case UD1Qr:
23984 case UD1Wm:
23985 case UD1Wr:
23986 return true;
23987 }
23988 return false;
23989}
23990
23991bool isPMAXSB(unsigned Opcode) {
23992 switch (Opcode) {
23993 case PMAXSBrm:
23994 case PMAXSBrr:
23995 return true;
23996 }
23997 return false;
23998}
23999
24000bool isVPROLQ(unsigned Opcode) {
24001 switch (Opcode) {
24002 case VPROLQZ128mbi:
24003 case VPROLQZ128mbik:
24004 case VPROLQZ128mbikz:
24005 case VPROLQZ128mi:
24006 case VPROLQZ128mik:
24007 case VPROLQZ128mikz:
24008 case VPROLQZ128ri:
24009 case VPROLQZ128rik:
24010 case VPROLQZ128rikz:
24011 case VPROLQZ256mbi:
24012 case VPROLQZ256mbik:
24013 case VPROLQZ256mbikz:
24014 case VPROLQZ256mi:
24015 case VPROLQZ256mik:
24016 case VPROLQZ256mikz:
24017 case VPROLQZ256ri:
24018 case VPROLQZ256rik:
24019 case VPROLQZ256rikz:
24020 case VPROLQZmbi:
24021 case VPROLQZmbik:
24022 case VPROLQZmbikz:
24023 case VPROLQZmi:
24024 case VPROLQZmik:
24025 case VPROLQZmikz:
24026 case VPROLQZri:
24027 case VPROLQZrik:
24028 case VPROLQZrikz:
24029 return true;
24030 }
24031 return false;
24032}
24033
24034bool isVSCATTERPF1QPD(unsigned Opcode) {
24035 return Opcode == VSCATTERPF1QPDm;
24036}
24037
24038bool isVPSRLD(unsigned Opcode) {
24039 switch (Opcode) {
24040 case VPSRLDYri:
24041 case VPSRLDYrm:
24042 case VPSRLDYrr:
24043 case VPSRLDZ128mbi:
24044 case VPSRLDZ128mbik:
24045 case VPSRLDZ128mbikz:
24046 case VPSRLDZ128mi:
24047 case VPSRLDZ128mik:
24048 case VPSRLDZ128mikz:
24049 case VPSRLDZ128ri:
24050 case VPSRLDZ128rik:
24051 case VPSRLDZ128rikz:
24052 case VPSRLDZ128rm:
24053 case VPSRLDZ128rmk:
24054 case VPSRLDZ128rmkz:
24055 case VPSRLDZ128rr:
24056 case VPSRLDZ128rrk:
24057 case VPSRLDZ128rrkz:
24058 case VPSRLDZ256mbi:
24059 case VPSRLDZ256mbik:
24060 case VPSRLDZ256mbikz:
24061 case VPSRLDZ256mi:
24062 case VPSRLDZ256mik:
24063 case VPSRLDZ256mikz:
24064 case VPSRLDZ256ri:
24065 case VPSRLDZ256rik:
24066 case VPSRLDZ256rikz:
24067 case VPSRLDZ256rm:
24068 case VPSRLDZ256rmk:
24069 case VPSRLDZ256rmkz:
24070 case VPSRLDZ256rr:
24071 case VPSRLDZ256rrk:
24072 case VPSRLDZ256rrkz:
24073 case VPSRLDZmbi:
24074 case VPSRLDZmbik:
24075 case VPSRLDZmbikz:
24076 case VPSRLDZmi:
24077 case VPSRLDZmik:
24078 case VPSRLDZmikz:
24079 case VPSRLDZri:
24080 case VPSRLDZrik:
24081 case VPSRLDZrikz:
24082 case VPSRLDZrm:
24083 case VPSRLDZrmk:
24084 case VPSRLDZrmkz:
24085 case VPSRLDZrr:
24086 case VPSRLDZrrk:
24087 case VPSRLDZrrkz:
24088 case VPSRLDri:
24089 case VPSRLDrm:
24090 case VPSRLDrr:
24091 return true;
24092 }
24093 return false;
24094}
24095
24096bool isINT3(unsigned Opcode) {
24097 return Opcode == INT3;
24098}
24099
24100bool isXRSTORS64(unsigned Opcode) {
24101 return Opcode == XRSTORS64;
24102}
24103
24104bool isCVTSD2SI(unsigned Opcode) {
24105 switch (Opcode) {
24106 case CVTSD2SI64rm_Int:
24107 case CVTSD2SI64rr_Int:
24108 case CVTSD2SIrm_Int:
24109 case CVTSD2SIrr_Int:
24110 return true;
24111 }
24112 return false;
24113}
24114
24115bool isVMAXSS(unsigned Opcode) {
24116 switch (Opcode) {
24117 case VMAXSSZrm_Int:
24118 case VMAXSSZrmk_Int:
24119 case VMAXSSZrmkz_Int:
24120 case VMAXSSZrr_Int:
24121 case VMAXSSZrrb_Int:
24122 case VMAXSSZrrbk_Int:
24123 case VMAXSSZrrbkz_Int:
24124 case VMAXSSZrrk_Int:
24125 case VMAXSSZrrkz_Int:
24126 case VMAXSSrm_Int:
24127 case VMAXSSrr_Int:
24128 return true;
24129 }
24130 return false;
24131}
24132
24133bool isVPMINUB(unsigned Opcode) {
24134 switch (Opcode) {
24135 case VPMINUBYrm:
24136 case VPMINUBYrr:
24137 case VPMINUBZ128rm:
24138 case VPMINUBZ128rmk:
24139 case VPMINUBZ128rmkz:
24140 case VPMINUBZ128rr:
24141 case VPMINUBZ128rrk:
24142 case VPMINUBZ128rrkz:
24143 case VPMINUBZ256rm:
24144 case VPMINUBZ256rmk:
24145 case VPMINUBZ256rmkz:
24146 case VPMINUBZ256rr:
24147 case VPMINUBZ256rrk:
24148 case VPMINUBZ256rrkz:
24149 case VPMINUBZrm:
24150 case VPMINUBZrmk:
24151 case VPMINUBZrmkz:
24152 case VPMINUBZrr:
24153 case VPMINUBZrrk:
24154 case VPMINUBZrrkz:
24155 case VPMINUBrm:
24156 case VPMINUBrr:
24157 return true;
24158 }
24159 return false;
24160}
24161
24162bool isKXNORQ(unsigned Opcode) {
24163 return Opcode == KXNORQkk;
24164}
24165
24166bool isFLD(unsigned Opcode) {
24167 switch (Opcode) {
24168 case LD_F32m:
24169 case LD_F64m:
24170 case LD_F80m:
24171 case LD_Frr:
24172 return true;
24173 }
24174 return false;
24175}
24176
24177bool isVSHUFI32X4(unsigned Opcode) {
24178 switch (Opcode) {
24179 case VSHUFI32X4Z256rmbi:
24180 case VSHUFI32X4Z256rmbik:
24181 case VSHUFI32X4Z256rmbikz:
24182 case VSHUFI32X4Z256rmi:
24183 case VSHUFI32X4Z256rmik:
24184 case VSHUFI32X4Z256rmikz:
24185 case VSHUFI32X4Z256rri:
24186 case VSHUFI32X4Z256rrik:
24187 case VSHUFI32X4Z256rrikz:
24188 case VSHUFI32X4Zrmbi:
24189 case VSHUFI32X4Zrmbik:
24190 case VSHUFI32X4Zrmbikz:
24191 case VSHUFI32X4Zrmi:
24192 case VSHUFI32X4Zrmik:
24193 case VSHUFI32X4Zrmikz:
24194 case VSHUFI32X4Zrri:
24195 case VSHUFI32X4Zrrik:
24196 case VSHUFI32X4Zrrikz:
24197 return true;
24198 }
24199 return false;
24200}
24201
24202bool isSAHF(unsigned Opcode) {
24203 return Opcode == SAHF;
24204}
24205
24206bool isPFRSQRT(unsigned Opcode) {
24207 switch (Opcode) {
24208 case PFRSQRTrm:
24209 case PFRSQRTrr:
24210 return true;
24211 }
24212 return false;
24213}
24214
24215bool isSHRD(unsigned Opcode) {
24216 switch (Opcode) {
24217 case SHRD16mrCL:
24218 case SHRD16mrCL_EVEX:
24219 case SHRD16mrCL_ND:
24220 case SHRD16mrCL_NF:
24221 case SHRD16mrCL_NF_ND:
24222 case SHRD16mri8:
24223 case SHRD16mri8_EVEX:
24224 case SHRD16mri8_ND:
24225 case SHRD16mri8_NF:
24226 case SHRD16mri8_NF_ND:
24227 case SHRD16rrCL:
24228 case SHRD16rrCL_EVEX:
24229 case SHRD16rrCL_ND:
24230 case SHRD16rrCL_NF:
24231 case SHRD16rrCL_NF_ND:
24232 case SHRD16rri8:
24233 case SHRD16rri8_EVEX:
24234 case SHRD16rri8_ND:
24235 case SHRD16rri8_NF:
24236 case SHRD16rri8_NF_ND:
24237 case SHRD32mrCL:
24238 case SHRD32mrCL_EVEX:
24239 case SHRD32mrCL_ND:
24240 case SHRD32mrCL_NF:
24241 case SHRD32mrCL_NF_ND:
24242 case SHRD32mri8:
24243 case SHRD32mri8_EVEX:
24244 case SHRD32mri8_ND:
24245 case SHRD32mri8_NF:
24246 case SHRD32mri8_NF_ND:
24247 case SHRD32rrCL:
24248 case SHRD32rrCL_EVEX:
24249 case SHRD32rrCL_ND:
24250 case SHRD32rrCL_NF:
24251 case SHRD32rrCL_NF_ND:
24252 case SHRD32rri8:
24253 case SHRD32rri8_EVEX:
24254 case SHRD32rri8_ND:
24255 case SHRD32rri8_NF:
24256 case SHRD32rri8_NF_ND:
24257 case SHRD64mrCL:
24258 case SHRD64mrCL_EVEX:
24259 case SHRD64mrCL_ND:
24260 case SHRD64mrCL_NF:
24261 case SHRD64mrCL_NF_ND:
24262 case SHRD64mri8:
24263 case SHRD64mri8_EVEX:
24264 case SHRD64mri8_ND:
24265 case SHRD64mri8_NF:
24266 case SHRD64mri8_NF_ND:
24267 case SHRD64rrCL:
24268 case SHRD64rrCL_EVEX:
24269 case SHRD64rrCL_ND:
24270 case SHRD64rrCL_NF:
24271 case SHRD64rrCL_NF_ND:
24272 case SHRD64rri8:
24273 case SHRD64rri8_EVEX:
24274 case SHRD64rri8_ND:
24275 case SHRD64rri8_NF:
24276 case SHRD64rri8_NF_ND:
24277 return true;
24278 }
24279 return false;
24280}
24281
24282bool isSYSEXIT(unsigned Opcode) {
24283 return Opcode == SYSEXIT;
24284}
24285
24286bool isXSAVE64(unsigned Opcode) {
24287 return Opcode == XSAVE64;
24288}
24289
24290bool isVPMAXSD(unsigned Opcode) {
24291 switch (Opcode) {
24292 case VPMAXSDYrm:
24293 case VPMAXSDYrr:
24294 case VPMAXSDZ128rm:
24295 case VPMAXSDZ128rmb:
24296 case VPMAXSDZ128rmbk:
24297 case VPMAXSDZ128rmbkz:
24298 case VPMAXSDZ128rmk:
24299 case VPMAXSDZ128rmkz:
24300 case VPMAXSDZ128rr:
24301 case VPMAXSDZ128rrk:
24302 case VPMAXSDZ128rrkz:
24303 case VPMAXSDZ256rm:
24304 case VPMAXSDZ256rmb:
24305 case VPMAXSDZ256rmbk:
24306 case VPMAXSDZ256rmbkz:
24307 case VPMAXSDZ256rmk:
24308 case VPMAXSDZ256rmkz:
24309 case VPMAXSDZ256rr:
24310 case VPMAXSDZ256rrk:
24311 case VPMAXSDZ256rrkz:
24312 case VPMAXSDZrm:
24313 case VPMAXSDZrmb:
24314 case VPMAXSDZrmbk:
24315 case VPMAXSDZrmbkz:
24316 case VPMAXSDZrmk:
24317 case VPMAXSDZrmkz:
24318 case VPMAXSDZrr:
24319 case VPMAXSDZrrk:
24320 case VPMAXSDZrrkz:
24321 case VPMAXSDrm:
24322 case VPMAXSDrr:
24323 return true;
24324 }
24325 return false;
24326}
24327
24328bool isCVTTSD2SI(unsigned Opcode) {
24329 switch (Opcode) {
24330 case CVTTSD2SI64rm_Int:
24331 case CVTTSD2SI64rr_Int:
24332 case CVTTSD2SIrm_Int:
24333 case CVTTSD2SIrr_Int:
24334 return true;
24335 }
24336 return false;
24337}
24338
24339bool isVCVTTSS2SIS(unsigned Opcode) {
24340 switch (Opcode) {
24341 case VCVTTSS2SI64Srm_Int:
24342 case VCVTTSS2SI64Srr_Int:
24343 case VCVTTSS2SI64Srrb_Int:
24344 case VCVTTSS2SISrm_Int:
24345 case VCVTTSS2SISrr_Int:
24346 case VCVTTSS2SISrrb_Int:
24347 return true;
24348 }
24349 return false;
24350}
24351
24352bool isPMOVMSKB(unsigned Opcode) {
24353 switch (Opcode) {
24354 case MMX_PMOVMSKBrr:
24355 case PMOVMSKBrr:
24356 return true;
24357 }
24358 return false;
24359}
24360
24361bool isVRANGEPS(unsigned Opcode) {
24362 switch (Opcode) {
24363 case VRANGEPSZ128rmbi:
24364 case VRANGEPSZ128rmbik:
24365 case VRANGEPSZ128rmbikz:
24366 case VRANGEPSZ128rmi:
24367 case VRANGEPSZ128rmik:
24368 case VRANGEPSZ128rmikz:
24369 case VRANGEPSZ128rri:
24370 case VRANGEPSZ128rrik:
24371 case VRANGEPSZ128rrikz:
24372 case VRANGEPSZ256rmbi:
24373 case VRANGEPSZ256rmbik:
24374 case VRANGEPSZ256rmbikz:
24375 case VRANGEPSZ256rmi:
24376 case VRANGEPSZ256rmik:
24377 case VRANGEPSZ256rmikz:
24378 case VRANGEPSZ256rri:
24379 case VRANGEPSZ256rrik:
24380 case VRANGEPSZ256rrikz:
24381 case VRANGEPSZrmbi:
24382 case VRANGEPSZrmbik:
24383 case VRANGEPSZrmbikz:
24384 case VRANGEPSZrmi:
24385 case VRANGEPSZrmik:
24386 case VRANGEPSZrmikz:
24387 case VRANGEPSZrri:
24388 case VRANGEPSZrrib:
24389 case VRANGEPSZrribk:
24390 case VRANGEPSZrribkz:
24391 case VRANGEPSZrrik:
24392 case VRANGEPSZrrikz:
24393 return true;
24394 }
24395 return false;
24396}
24397
24398bool isVADDSUBPS(unsigned Opcode) {
24399 switch (Opcode) {
24400 case VADDSUBPSYrm:
24401 case VADDSUBPSYrr:
24402 case VADDSUBPSrm:
24403 case VADDSUBPSrr:
24404 return true;
24405 }
24406 return false;
24407}
24408
24409bool isVBROADCASTI128(unsigned Opcode) {
24410 return Opcode == VBROADCASTI128rm;
24411}
24412
24413bool isPADDUSB(unsigned Opcode) {
24414 switch (Opcode) {
24415 case MMX_PADDUSBrm:
24416 case MMX_PADDUSBrr:
24417 case PADDUSBrm:
24418 case PADDUSBrr:
24419 return true;
24420 }
24421 return false;
24422}
24423
24424bool isENCODEKEY128(unsigned Opcode) {
24425 return Opcode == ENCODEKEY128;
24426}
24427
24428bool isOR(unsigned Opcode) {
24429 switch (Opcode) {
24430 case OR16i16:
24431 case OR16mi:
24432 case OR16mi8:
24433 case OR16mi8_EVEX:
24434 case OR16mi8_ND:
24435 case OR16mi8_NF:
24436 case OR16mi8_NF_ND:
24437 case OR16mi_EVEX:
24438 case OR16mi_ND:
24439 case OR16mi_NF:
24440 case OR16mi_NF_ND:
24441 case OR16mr:
24442 case OR16mr_EVEX:
24443 case OR16mr_ND:
24444 case OR16mr_NF:
24445 case OR16mr_NF_ND:
24446 case OR16ri:
24447 case OR16ri8:
24448 case OR16ri8_EVEX:
24449 case OR16ri8_ND:
24450 case OR16ri8_NF:
24451 case OR16ri8_NF_ND:
24452 case OR16ri_EVEX:
24453 case OR16ri_ND:
24454 case OR16ri_NF:
24455 case OR16ri_NF_ND:
24456 case OR16rm:
24457 case OR16rm_EVEX:
24458 case OR16rm_ND:
24459 case OR16rm_NF:
24460 case OR16rm_NF_ND:
24461 case OR16rr:
24462 case OR16rr_EVEX:
24463 case OR16rr_EVEX_REV:
24464 case OR16rr_ND:
24465 case OR16rr_ND_REV:
24466 case OR16rr_NF:
24467 case OR16rr_NF_ND:
24468 case OR16rr_NF_ND_REV:
24469 case OR16rr_NF_REV:
24470 case OR16rr_REV:
24471 case OR32i32:
24472 case OR32mi:
24473 case OR32mi8:
24474 case OR32mi8_EVEX:
24475 case OR32mi8_ND:
24476 case OR32mi8_NF:
24477 case OR32mi8_NF_ND:
24478 case OR32mi_EVEX:
24479 case OR32mi_ND:
24480 case OR32mi_NF:
24481 case OR32mi_NF_ND:
24482 case OR32mr:
24483 case OR32mr_EVEX:
24484 case OR32mr_ND:
24485 case OR32mr_NF:
24486 case OR32mr_NF_ND:
24487 case OR32ri:
24488 case OR32ri8:
24489 case OR32ri8_EVEX:
24490 case OR32ri8_ND:
24491 case OR32ri8_NF:
24492 case OR32ri8_NF_ND:
24493 case OR32ri_EVEX:
24494 case OR32ri_ND:
24495 case OR32ri_NF:
24496 case OR32ri_NF_ND:
24497 case OR32rm:
24498 case OR32rm_EVEX:
24499 case OR32rm_ND:
24500 case OR32rm_NF:
24501 case OR32rm_NF_ND:
24502 case OR32rr:
24503 case OR32rr_EVEX:
24504 case OR32rr_EVEX_REV:
24505 case OR32rr_ND:
24506 case OR32rr_ND_REV:
24507 case OR32rr_NF:
24508 case OR32rr_NF_ND:
24509 case OR32rr_NF_ND_REV:
24510 case OR32rr_NF_REV:
24511 case OR32rr_REV:
24512 case OR64i32:
24513 case OR64mi32:
24514 case OR64mi32_EVEX:
24515 case OR64mi32_ND:
24516 case OR64mi32_NF:
24517 case OR64mi32_NF_ND:
24518 case OR64mi8:
24519 case OR64mi8_EVEX:
24520 case OR64mi8_ND:
24521 case OR64mi8_NF:
24522 case OR64mi8_NF_ND:
24523 case OR64mr:
24524 case OR64mr_EVEX:
24525 case OR64mr_ND:
24526 case OR64mr_NF:
24527 case OR64mr_NF_ND:
24528 case OR64ri32:
24529 case OR64ri32_EVEX:
24530 case OR64ri32_ND:
24531 case OR64ri32_NF:
24532 case OR64ri32_NF_ND:
24533 case OR64ri8:
24534 case OR64ri8_EVEX:
24535 case OR64ri8_ND:
24536 case OR64ri8_NF:
24537 case OR64ri8_NF_ND:
24538 case OR64rm:
24539 case OR64rm_EVEX:
24540 case OR64rm_ND:
24541 case OR64rm_NF:
24542 case OR64rm_NF_ND:
24543 case OR64rr:
24544 case OR64rr_EVEX:
24545 case OR64rr_EVEX_REV:
24546 case OR64rr_ND:
24547 case OR64rr_ND_REV:
24548 case OR64rr_NF:
24549 case OR64rr_NF_ND:
24550 case OR64rr_NF_ND_REV:
24551 case OR64rr_NF_REV:
24552 case OR64rr_REV:
24553 case OR8i8:
24554 case OR8mi:
24555 case OR8mi8:
24556 case OR8mi_EVEX:
24557 case OR8mi_ND:
24558 case OR8mi_NF:
24559 case OR8mi_NF_ND:
24560 case OR8mr:
24561 case OR8mr_EVEX:
24562 case OR8mr_ND:
24563 case OR8mr_NF:
24564 case OR8mr_NF_ND:
24565 case OR8ri:
24566 case OR8ri8:
24567 case OR8ri_EVEX:
24568 case OR8ri_ND:
24569 case OR8ri_NF:
24570 case OR8ri_NF_ND:
24571 case OR8rm:
24572 case OR8rm_EVEX:
24573 case OR8rm_ND:
24574 case OR8rm_NF:
24575 case OR8rm_NF_ND:
24576 case OR8rr:
24577 case OR8rr_EVEX:
24578 case OR8rr_EVEX_REV:
24579 case OR8rr_ND:
24580 case OR8rr_ND_REV:
24581 case OR8rr_NF:
24582 case OR8rr_NF_ND:
24583 case OR8rr_NF_ND_REV:
24584 case OR8rr_NF_REV:
24585 case OR8rr_REV:
24586 return true;
24587 }
24588 return false;
24589}
24590
24591bool isSTOSW(unsigned Opcode) {
24592 return Opcode == STOSW;
24593}
24594
24595bool isVCVTTPD2UQQS(unsigned Opcode) {
24596 switch (Opcode) {
24597 case VCVTTPD2UQQSZ128rm:
24598 case VCVTTPD2UQQSZ128rmb:
24599 case VCVTTPD2UQQSZ128rmbk:
24600 case VCVTTPD2UQQSZ128rmbkz:
24601 case VCVTTPD2UQQSZ128rmk:
24602 case VCVTTPD2UQQSZ128rmkz:
24603 case VCVTTPD2UQQSZ128rr:
24604 case VCVTTPD2UQQSZ128rrk:
24605 case VCVTTPD2UQQSZ128rrkz:
24606 case VCVTTPD2UQQSZ256rm:
24607 case VCVTTPD2UQQSZ256rmb:
24608 case VCVTTPD2UQQSZ256rmbk:
24609 case VCVTTPD2UQQSZ256rmbkz:
24610 case VCVTTPD2UQQSZ256rmk:
24611 case VCVTTPD2UQQSZ256rmkz:
24612 case VCVTTPD2UQQSZ256rr:
24613 case VCVTTPD2UQQSZ256rrb:
24614 case VCVTTPD2UQQSZ256rrbk:
24615 case VCVTTPD2UQQSZ256rrbkz:
24616 case VCVTTPD2UQQSZ256rrk:
24617 case VCVTTPD2UQQSZ256rrkz:
24618 case VCVTTPD2UQQSZrm:
24619 case VCVTTPD2UQQSZrmb:
24620 case VCVTTPD2UQQSZrmbk:
24621 case VCVTTPD2UQQSZrmbkz:
24622 case VCVTTPD2UQQSZrmk:
24623 case VCVTTPD2UQQSZrmkz:
24624 case VCVTTPD2UQQSZrr:
24625 case VCVTTPD2UQQSZrrb:
24626 case VCVTTPD2UQQSZrrbk:
24627 case VCVTTPD2UQQSZrrbkz:
24628 case VCVTTPD2UQQSZrrk:
24629 case VCVTTPD2UQQSZrrkz:
24630 return true;
24631 }
24632 return false;
24633}
24634
24635bool isPAVGW(unsigned Opcode) {
24636 switch (Opcode) {
24637 case MMX_PAVGWrm:
24638 case MMX_PAVGWrr:
24639 case PAVGWrm:
24640 case PAVGWrr:
24641 return true;
24642 }
24643 return false;
24644}
24645
24646bool isVCVTPD2PH(unsigned Opcode) {
24647 switch (Opcode) {
24648 case VCVTPD2PHZ128rm:
24649 case VCVTPD2PHZ128rmb:
24650 case VCVTPD2PHZ128rmbk:
24651 case VCVTPD2PHZ128rmbkz:
24652 case VCVTPD2PHZ128rmk:
24653 case VCVTPD2PHZ128rmkz:
24654 case VCVTPD2PHZ128rr:
24655 case VCVTPD2PHZ128rrk:
24656 case VCVTPD2PHZ128rrkz:
24657 case VCVTPD2PHZ256rm:
24658 case VCVTPD2PHZ256rmb:
24659 case VCVTPD2PHZ256rmbk:
24660 case VCVTPD2PHZ256rmbkz:
24661 case VCVTPD2PHZ256rmk:
24662 case VCVTPD2PHZ256rmkz:
24663 case VCVTPD2PHZ256rr:
24664 case VCVTPD2PHZ256rrk:
24665 case VCVTPD2PHZ256rrkz:
24666 case VCVTPD2PHZrm:
24667 case VCVTPD2PHZrmb:
24668 case VCVTPD2PHZrmbk:
24669 case VCVTPD2PHZrmbkz:
24670 case VCVTPD2PHZrmk:
24671 case VCVTPD2PHZrmkz:
24672 case VCVTPD2PHZrr:
24673 case VCVTPD2PHZrrb:
24674 case VCVTPD2PHZrrbk:
24675 case VCVTPD2PHZrrbkz:
24676 case VCVTPD2PHZrrk:
24677 case VCVTPD2PHZrrkz:
24678 return true;
24679 }
24680 return false;
24681}
24682
24683bool isSHLX(unsigned Opcode) {
24684 switch (Opcode) {
24685 case SHLX32rm:
24686 case SHLX32rm_EVEX:
24687 case SHLX32rr:
24688 case SHLX32rr_EVEX:
24689 case SHLX64rm:
24690 case SHLX64rm_EVEX:
24691 case SHLX64rr:
24692 case SHLX64rr_EVEX:
24693 return true;
24694 }
24695 return false;
24696}
24697
24698bool isVCVTSH2SD(unsigned Opcode) {
24699 switch (Opcode) {
24700 case VCVTSH2SDZrm_Int:
24701 case VCVTSH2SDZrmk_Int:
24702 case VCVTSH2SDZrmkz_Int:
24703 case VCVTSH2SDZrr_Int:
24704 case VCVTSH2SDZrrb_Int:
24705 case VCVTSH2SDZrrbk_Int:
24706 case VCVTSH2SDZrrbkz_Int:
24707 case VCVTSH2SDZrrk_Int:
24708 case VCVTSH2SDZrrkz_Int:
24709 return true;
24710 }
24711 return false;
24712}
24713
24714bool isVFMADD231SS(unsigned Opcode) {
24715 switch (Opcode) {
24716 case VFMADD231SSZm_Int:
24717 case VFMADD231SSZmk_Int:
24718 case VFMADD231SSZmkz_Int:
24719 case VFMADD231SSZr_Int:
24720 case VFMADD231SSZrb_Int:
24721 case VFMADD231SSZrbk_Int:
24722 case VFMADD231SSZrbkz_Int:
24723 case VFMADD231SSZrk_Int:
24724 case VFMADD231SSZrkz_Int:
24725 case VFMADD231SSm_Int:
24726 case VFMADD231SSr_Int:
24727 return true;
24728 }
24729 return false;
24730}
24731
24732bool isMOVNTSD(unsigned Opcode) {
24733 return Opcode == MOVNTSD;
24734}
24735
24736bool isFLDPI(unsigned Opcode) {
24737 return Opcode == FLDPI;
24738}
24739
24740bool isVCVTUSI2SS(unsigned Opcode) {
24741 switch (Opcode) {
24742 case VCVTUSI2SSZrm_Int:
24743 case VCVTUSI2SSZrr_Int:
24744 case VCVTUSI2SSZrrb_Int:
24745 case VCVTUSI642SSZrm_Int:
24746 case VCVTUSI642SSZrr_Int:
24747 case VCVTUSI642SSZrrb_Int:
24748 return true;
24749 }
24750 return false;
24751}
24752
24753bool isPMOVSXBD(unsigned Opcode) {
24754 switch (Opcode) {
24755 case PMOVSXBDrm:
24756 case PMOVSXBDrr:
24757 return true;
24758 }
24759 return false;
24760}
24761
24762bool isVPRORVQ(unsigned Opcode) {
24763 switch (Opcode) {
24764 case VPRORVQZ128rm:
24765 case VPRORVQZ128rmb:
24766 case VPRORVQZ128rmbk:
24767 case VPRORVQZ128rmbkz:
24768 case VPRORVQZ128rmk:
24769 case VPRORVQZ128rmkz:
24770 case VPRORVQZ128rr:
24771 case VPRORVQZ128rrk:
24772 case VPRORVQZ128rrkz:
24773 case VPRORVQZ256rm:
24774 case VPRORVQZ256rmb:
24775 case VPRORVQZ256rmbk:
24776 case VPRORVQZ256rmbkz:
24777 case VPRORVQZ256rmk:
24778 case VPRORVQZ256rmkz:
24779 case VPRORVQZ256rr:
24780 case VPRORVQZ256rrk:
24781 case VPRORVQZ256rrkz:
24782 case VPRORVQZrm:
24783 case VPRORVQZrmb:
24784 case VPRORVQZrmbk:
24785 case VPRORVQZrmbkz:
24786 case VPRORVQZrmk:
24787 case VPRORVQZrmkz:
24788 case VPRORVQZrr:
24789 case VPRORVQZrrk:
24790 case VPRORVQZrrkz:
24791 return true;
24792 }
24793 return false;
24794}
24795
24796bool isVPERMT2D(unsigned Opcode) {
24797 switch (Opcode) {
24798 case VPERMT2DZ128rm:
24799 case VPERMT2DZ128rmb:
24800 case VPERMT2DZ128rmbk:
24801 case VPERMT2DZ128rmbkz:
24802 case VPERMT2DZ128rmk:
24803 case VPERMT2DZ128rmkz:
24804 case VPERMT2DZ128rr:
24805 case VPERMT2DZ128rrk:
24806 case VPERMT2DZ128rrkz:
24807 case VPERMT2DZ256rm:
24808 case VPERMT2DZ256rmb:
24809 case VPERMT2DZ256rmbk:
24810 case VPERMT2DZ256rmbkz:
24811 case VPERMT2DZ256rmk:
24812 case VPERMT2DZ256rmkz:
24813 case VPERMT2DZ256rr:
24814 case VPERMT2DZ256rrk:
24815 case VPERMT2DZ256rrkz:
24816 case VPERMT2DZrm:
24817 case VPERMT2DZrmb:
24818 case VPERMT2DZrmbk:
24819 case VPERMT2DZrmbkz:
24820 case VPERMT2DZrmk:
24821 case VPERMT2DZrmkz:
24822 case VPERMT2DZrr:
24823 case VPERMT2DZrrk:
24824 case VPERMT2DZrrkz:
24825 return true;
24826 }
24827 return false;
24828}
24829
24830bool isADDSS(unsigned Opcode) {
24831 switch (Opcode) {
24832 case ADDSSrm_Int:
24833 case ADDSSrr_Int:
24834 return true;
24835 }
24836 return false;
24837}
24838
24839bool isAADD(unsigned Opcode) {
24840 switch (Opcode) {
24841 case AADD32mr:
24842 case AADD32mr_EVEX:
24843 case AADD64mr:
24844 case AADD64mr_EVEX:
24845 return true;
24846 }
24847 return false;
24848}
24849
24850bool isVPSRLVW(unsigned Opcode) {
24851 switch (Opcode) {
24852 case VPSRLVWZ128rm:
24853 case VPSRLVWZ128rmk:
24854 case VPSRLVWZ128rmkz:
24855 case VPSRLVWZ128rr:
24856 case VPSRLVWZ128rrk:
24857 case VPSRLVWZ128rrkz:
24858 case VPSRLVWZ256rm:
24859 case VPSRLVWZ256rmk:
24860 case VPSRLVWZ256rmkz:
24861 case VPSRLVWZ256rr:
24862 case VPSRLVWZ256rrk:
24863 case VPSRLVWZ256rrkz:
24864 case VPSRLVWZrm:
24865 case VPSRLVWZrmk:
24866 case VPSRLVWZrmkz:
24867 case VPSRLVWZrr:
24868 case VPSRLVWZrrk:
24869 case VPSRLVWZrrkz:
24870 return true;
24871 }
24872 return false;
24873}
24874
24875bool isVRSQRTPH(unsigned Opcode) {
24876 switch (Opcode) {
24877 case VRSQRTPHZ128m:
24878 case VRSQRTPHZ128mb:
24879 case VRSQRTPHZ128mbk:
24880 case VRSQRTPHZ128mbkz:
24881 case VRSQRTPHZ128mk:
24882 case VRSQRTPHZ128mkz:
24883 case VRSQRTPHZ128r:
24884 case VRSQRTPHZ128rk:
24885 case VRSQRTPHZ128rkz:
24886 case VRSQRTPHZ256m:
24887 case VRSQRTPHZ256mb:
24888 case VRSQRTPHZ256mbk:
24889 case VRSQRTPHZ256mbkz:
24890 case VRSQRTPHZ256mk:
24891 case VRSQRTPHZ256mkz:
24892 case VRSQRTPHZ256r:
24893 case VRSQRTPHZ256rk:
24894 case VRSQRTPHZ256rkz:
24895 case VRSQRTPHZm:
24896 case VRSQRTPHZmb:
24897 case VRSQRTPHZmbk:
24898 case VRSQRTPHZmbkz:
24899 case VRSQRTPHZmk:
24900 case VRSQRTPHZmkz:
24901 case VRSQRTPHZr:
24902 case VRSQRTPHZrk:
24903 case VRSQRTPHZrkz:
24904 return true;
24905 }
24906 return false;
24907}
24908
24909bool isVLDDQU(unsigned Opcode) {
24910 switch (Opcode) {
24911 case VLDDQUYrm:
24912 case VLDDQUrm:
24913 return true;
24914 }
24915 return false;
24916}
24917
24918bool isKMOVD(unsigned Opcode) {
24919 switch (Opcode) {
24920 case KMOVDkk:
24921 case KMOVDkk_EVEX:
24922 case KMOVDkm:
24923 case KMOVDkm_EVEX:
24924 case KMOVDkr:
24925 case KMOVDkr_EVEX:
24926 case KMOVDmk:
24927 case KMOVDmk_EVEX:
24928 case KMOVDrk:
24929 case KMOVDrk_EVEX:
24930 return true;
24931 }
24932 return false;
24933}
24934
24935bool isENCLV(unsigned Opcode) {
24936 return Opcode == ENCLV;
24937}
24938
24939bool isENCLU(unsigned Opcode) {
24940 return Opcode == ENCLU;
24941}
24942
24943bool isPREFETCHT1(unsigned Opcode) {
24944 return Opcode == PREFETCHT1;
24945}
24946
24947bool isRSQRTPS(unsigned Opcode) {
24948 switch (Opcode) {
24949 case RSQRTPSm:
24950 case RSQRTPSr:
24951 return true;
24952 }
24953 return false;
24954}
24955
24956bool isVCVTTSH2USI(unsigned Opcode) {
24957 switch (Opcode) {
24958 case VCVTTSH2USI64Zrm_Int:
24959 case VCVTTSH2USI64Zrr_Int:
24960 case VCVTTSH2USI64Zrrb_Int:
24961 case VCVTTSH2USIZrm_Int:
24962 case VCVTTSH2USIZrr_Int:
24963 case VCVTTSH2USIZrrb_Int:
24964 return true;
24965 }
24966 return false;
24967}
24968
24969bool isPADDB(unsigned Opcode) {
24970 switch (Opcode) {
24971 case MMX_PADDBrm:
24972 case MMX_PADDBrr:
24973 case PADDBrm:
24974 case PADDBrr:
24975 return true;
24976 }
24977 return false;
24978}
24979
24980bool isVMASKMOVDQU(unsigned Opcode) {
24981 return Opcode == VMASKMOVDQU64;
24982}
24983
24984bool isPUNPCKLBW(unsigned Opcode) {
24985 switch (Opcode) {
24986 case MMX_PUNPCKLBWrm:
24987 case MMX_PUNPCKLBWrr:
24988 case PUNPCKLBWrm:
24989 case PUNPCKLBWrr:
24990 return true;
24991 }
24992 return false;
24993}
24994
24995bool isMOV(unsigned Opcode) {
24996 switch (Opcode) {
24997 case MOV16ao16:
24998 case MOV16ao32:
24999 case MOV16mi:
25000 case MOV16mr:
25001 case MOV16ms:
25002 case MOV16o16a:
25003 case MOV16o32a:
25004 case MOV16ri:
25005 case MOV16ri_alt:
25006 case MOV16rm:
25007 case MOV16rr:
25008 case MOV16rr_REV:
25009 case MOV16rs:
25010 case MOV16sm:
25011 case MOV16sr:
25012 case MOV32ao16:
25013 case MOV32ao32:
25014 case MOV32cr:
25015 case MOV32dr:
25016 case MOV32mi:
25017 case MOV32mr:
25018 case MOV32o16a:
25019 case MOV32o32a:
25020 case MOV32rc:
25021 case MOV32rd:
25022 case MOV32ri:
25023 case MOV32ri_alt:
25024 case MOV32rm:
25025 case MOV32rr:
25026 case MOV32rr_REV:
25027 case MOV32rs:
25028 case MOV32sr:
25029 case MOV64ao32:
25030 case MOV64cr:
25031 case MOV64dr:
25032 case MOV64mi32:
25033 case MOV64mr:
25034 case MOV64o32a:
25035 case MOV64rc:
25036 case MOV64rd:
25037 case MOV64ri32:
25038 case MOV64rm:
25039 case MOV64rr:
25040 case MOV64rr_REV:
25041 case MOV64rs:
25042 case MOV64sr:
25043 case MOV8ao16:
25044 case MOV8ao32:
25045 case MOV8mi:
25046 case MOV8mr:
25047 case MOV8o16a:
25048 case MOV8o32a:
25049 case MOV8ri:
25050 case MOV8ri_alt:
25051 case MOV8rm:
25052 case MOV8rr:
25053 case MOV8rr_REV:
25054 return true;
25055 }
25056 return false;
25057}
25058
25059bool isVCVTTPH2IUBS(unsigned Opcode) {
25060 switch (Opcode) {
25061 case VCVTTPH2IUBSZ128rm:
25062 case VCVTTPH2IUBSZ128rmb:
25063 case VCVTTPH2IUBSZ128rmbk:
25064 case VCVTTPH2IUBSZ128rmbkz:
25065 case VCVTTPH2IUBSZ128rmk:
25066 case VCVTTPH2IUBSZ128rmkz:
25067 case VCVTTPH2IUBSZ128rr:
25068 case VCVTTPH2IUBSZ128rrk:
25069 case VCVTTPH2IUBSZ128rrkz:
25070 case VCVTTPH2IUBSZ256rm:
25071 case VCVTTPH2IUBSZ256rmb:
25072 case VCVTTPH2IUBSZ256rmbk:
25073 case VCVTTPH2IUBSZ256rmbkz:
25074 case VCVTTPH2IUBSZ256rmk:
25075 case VCVTTPH2IUBSZ256rmkz:
25076 case VCVTTPH2IUBSZ256rr:
25077 case VCVTTPH2IUBSZ256rrk:
25078 case VCVTTPH2IUBSZ256rrkz:
25079 case VCVTTPH2IUBSZrm:
25080 case VCVTTPH2IUBSZrmb:
25081 case VCVTTPH2IUBSZrmbk:
25082 case VCVTTPH2IUBSZrmbkz:
25083 case VCVTTPH2IUBSZrmk:
25084 case VCVTTPH2IUBSZrmkz:
25085 case VCVTTPH2IUBSZrr:
25086 case VCVTTPH2IUBSZrrb:
25087 case VCVTTPH2IUBSZrrbk:
25088 case VCVTTPH2IUBSZrrbkz:
25089 case VCVTTPH2IUBSZrrk:
25090 case VCVTTPH2IUBSZrrkz:
25091 return true;
25092 }
25093 return false;
25094}
25095
25096bool isMUL(unsigned Opcode) {
25097 switch (Opcode) {
25098 case MUL16m:
25099 case MUL16m_EVEX:
25100 case MUL16m_NF:
25101 case MUL16r:
25102 case MUL16r_EVEX:
25103 case MUL16r_NF:
25104 case MUL32m:
25105 case MUL32m_EVEX:
25106 case MUL32m_NF:
25107 case MUL32r:
25108 case MUL32r_EVEX:
25109 case MUL32r_NF:
25110 case MUL64m:
25111 case MUL64m_EVEX:
25112 case MUL64m_NF:
25113 case MUL64r:
25114 case MUL64r_EVEX:
25115 case MUL64r_NF:
25116 case MUL8m:
25117 case MUL8m_EVEX:
25118 case MUL8m_NF:
25119 case MUL8r:
25120 case MUL8r_EVEX:
25121 case MUL8r_NF:
25122 return true;
25123 }
25124 return false;
25125}
25126
25127bool isRCL(unsigned Opcode) {
25128 switch (Opcode) {
25129 case RCL16m1:
25130 case RCL16m1_EVEX:
25131 case RCL16m1_ND:
25132 case RCL16mCL:
25133 case RCL16mCL_EVEX:
25134 case RCL16mCL_ND:
25135 case RCL16mi:
25136 case RCL16mi_EVEX:
25137 case RCL16mi_ND:
25138 case RCL16r1:
25139 case RCL16r1_EVEX:
25140 case RCL16r1_ND:
25141 case RCL16rCL:
25142 case RCL16rCL_EVEX:
25143 case RCL16rCL_ND:
25144 case RCL16ri:
25145 case RCL16ri_EVEX:
25146 case RCL16ri_ND:
25147 case RCL32m1:
25148 case RCL32m1_EVEX:
25149 case RCL32m1_ND:
25150 case RCL32mCL:
25151 case RCL32mCL_EVEX:
25152 case RCL32mCL_ND:
25153 case RCL32mi:
25154 case RCL32mi_EVEX:
25155 case RCL32mi_ND:
25156 case RCL32r1:
25157 case RCL32r1_EVEX:
25158 case RCL32r1_ND:
25159 case RCL32rCL:
25160 case RCL32rCL_EVEX:
25161 case RCL32rCL_ND:
25162 case RCL32ri:
25163 case RCL32ri_EVEX:
25164 case RCL32ri_ND:
25165 case RCL64m1:
25166 case RCL64m1_EVEX:
25167 case RCL64m1_ND:
25168 case RCL64mCL:
25169 case RCL64mCL_EVEX:
25170 case RCL64mCL_ND:
25171 case RCL64mi:
25172 case RCL64mi_EVEX:
25173 case RCL64mi_ND:
25174 case RCL64r1:
25175 case RCL64r1_EVEX:
25176 case RCL64r1_ND:
25177 case RCL64rCL:
25178 case RCL64rCL_EVEX:
25179 case RCL64rCL_ND:
25180 case RCL64ri:
25181 case RCL64ri_EVEX:
25182 case RCL64ri_ND:
25183 case RCL8m1:
25184 case RCL8m1_EVEX:
25185 case RCL8m1_ND:
25186 case RCL8mCL:
25187 case RCL8mCL_EVEX:
25188 case RCL8mCL_ND:
25189 case RCL8mi:
25190 case RCL8mi_EVEX:
25191 case RCL8mi_ND:
25192 case RCL8r1:
25193 case RCL8r1_EVEX:
25194 case RCL8r1_ND:
25195 case RCL8rCL:
25196 case RCL8rCL_EVEX:
25197 case RCL8rCL_ND:
25198 case RCL8ri:
25199 case RCL8ri_EVEX:
25200 case RCL8ri_ND:
25201 return true;
25202 }
25203 return false;
25204}
25205
25206bool isVRCPSH(unsigned Opcode) {
25207 switch (Opcode) {
25208 case VRCPSHZrm:
25209 case VRCPSHZrmk:
25210 case VRCPSHZrmkz:
25211 case VRCPSHZrr:
25212 case VRCPSHZrrk:
25213 case VRCPSHZrrkz:
25214 return true;
25215 }
25216 return false;
25217}
25218
25219bool isPFCMPEQ(unsigned Opcode) {
25220 switch (Opcode) {
25221 case PFCMPEQrm:
25222 case PFCMPEQrr:
25223 return true;
25224 }
25225 return false;
25226}
25227
25228bool isMONITOR(unsigned Opcode) {
25229 switch (Opcode) {
25230 case MONITOR32rrr:
25231 case MONITOR64rrr:
25232 return true;
25233 }
25234 return false;
25235}
25236
25237bool isFDIVR(unsigned Opcode) {
25238 switch (Opcode) {
25239 case DIVR_F32m:
25240 case DIVR_F64m:
25241 case DIVR_FST0r:
25242 case DIVR_FrST0:
25243 return true;
25244 }
25245 return false;
25246}
25247
25248bool isPMINSD(unsigned Opcode) {
25249 switch (Opcode) {
25250 case PMINSDrm:
25251 case PMINSDrr:
25252 return true;
25253 }
25254 return false;
25255}
25256
25257bool isPFRCP(unsigned Opcode) {
25258 switch (Opcode) {
25259 case PFRCPrm:
25260 case PFRCPrr:
25261 return true;
25262 }
25263 return false;
25264}
25265
25266bool isKTESTQ(unsigned Opcode) {
25267 return Opcode == KTESTQkk;
25268}
25269
25270bool isVCVTTPD2DQ(unsigned Opcode) {
25271 switch (Opcode) {
25272 case VCVTTPD2DQYrm:
25273 case VCVTTPD2DQYrr:
25274 case VCVTTPD2DQZ128rm:
25275 case VCVTTPD2DQZ128rmb:
25276 case VCVTTPD2DQZ128rmbk:
25277 case VCVTTPD2DQZ128rmbkz:
25278 case VCVTTPD2DQZ128rmk:
25279 case VCVTTPD2DQZ128rmkz:
25280 case VCVTTPD2DQZ128rr:
25281 case VCVTTPD2DQZ128rrk:
25282 case VCVTTPD2DQZ128rrkz:
25283 case VCVTTPD2DQZ256rm:
25284 case VCVTTPD2DQZ256rmb:
25285 case VCVTTPD2DQZ256rmbk:
25286 case VCVTTPD2DQZ256rmbkz:
25287 case VCVTTPD2DQZ256rmk:
25288 case VCVTTPD2DQZ256rmkz:
25289 case VCVTTPD2DQZ256rr:
25290 case VCVTTPD2DQZ256rrk:
25291 case VCVTTPD2DQZ256rrkz:
25292 case VCVTTPD2DQZrm:
25293 case VCVTTPD2DQZrmb:
25294 case VCVTTPD2DQZrmbk:
25295 case VCVTTPD2DQZrmbkz:
25296 case VCVTTPD2DQZrmk:
25297 case VCVTTPD2DQZrmkz:
25298 case VCVTTPD2DQZrr:
25299 case VCVTTPD2DQZrrb:
25300 case VCVTTPD2DQZrrbk:
25301 case VCVTTPD2DQZrrbkz:
25302 case VCVTTPD2DQZrrk:
25303 case VCVTTPD2DQZrrkz:
25304 case VCVTTPD2DQrm:
25305 case VCVTTPD2DQrr:
25306 return true;
25307 }
25308 return false;
25309}
25310
25311bool isVSHUFF32X4(unsigned Opcode) {
25312 switch (Opcode) {
25313 case VSHUFF32X4Z256rmbi:
25314 case VSHUFF32X4Z256rmbik:
25315 case VSHUFF32X4Z256rmbikz:
25316 case VSHUFF32X4Z256rmi:
25317 case VSHUFF32X4Z256rmik:
25318 case VSHUFF32X4Z256rmikz:
25319 case VSHUFF32X4Z256rri:
25320 case VSHUFF32X4Z256rrik:
25321 case VSHUFF32X4Z256rrikz:
25322 case VSHUFF32X4Zrmbi:
25323 case VSHUFF32X4Zrmbik:
25324 case VSHUFF32X4Zrmbikz:
25325 case VSHUFF32X4Zrmi:
25326 case VSHUFF32X4Zrmik:
25327 case VSHUFF32X4Zrmikz:
25328 case VSHUFF32X4Zrri:
25329 case VSHUFF32X4Zrrik:
25330 case VSHUFF32X4Zrrikz:
25331 return true;
25332 }
25333 return false;
25334}
25335
25336bool isVPSLLVW(unsigned Opcode) {
25337 switch (Opcode) {
25338 case VPSLLVWZ128rm:
25339 case VPSLLVWZ128rmk:
25340 case VPSLLVWZ128rmkz:
25341 case VPSLLVWZ128rr:
25342 case VPSLLVWZ128rrk:
25343 case VPSLLVWZ128rrkz:
25344 case VPSLLVWZ256rm:
25345 case VPSLLVWZ256rmk:
25346 case VPSLLVWZ256rmkz:
25347 case VPSLLVWZ256rr:
25348 case VPSLLVWZ256rrk:
25349 case VPSLLVWZ256rrkz:
25350 case VPSLLVWZrm:
25351 case VPSLLVWZrmk:
25352 case VPSLLVWZrmkz:
25353 case VPSLLVWZrr:
25354 case VPSLLVWZrrk:
25355 case VPSLLVWZrrkz:
25356 return true;
25357 }
25358 return false;
25359}
25360
25361bool isTDPBSUD(unsigned Opcode) {
25362 return Opcode == TDPBSUD;
25363}
25364
25365bool isVPMINUQ(unsigned Opcode) {
25366 switch (Opcode) {
25367 case VPMINUQZ128rm:
25368 case VPMINUQZ128rmb:
25369 case VPMINUQZ128rmbk:
25370 case VPMINUQZ128rmbkz:
25371 case VPMINUQZ128rmk:
25372 case VPMINUQZ128rmkz:
25373 case VPMINUQZ128rr:
25374 case VPMINUQZ128rrk:
25375 case VPMINUQZ128rrkz:
25376 case VPMINUQZ256rm:
25377 case VPMINUQZ256rmb:
25378 case VPMINUQZ256rmbk:
25379 case VPMINUQZ256rmbkz:
25380 case VPMINUQZ256rmk:
25381 case VPMINUQZ256rmkz:
25382 case VPMINUQZ256rr:
25383 case VPMINUQZ256rrk:
25384 case VPMINUQZ256rrkz:
25385 case VPMINUQZrm:
25386 case VPMINUQZrmb:
25387 case VPMINUQZrmbk:
25388 case VPMINUQZrmbkz:
25389 case VPMINUQZrmk:
25390 case VPMINUQZrmkz:
25391 case VPMINUQZrr:
25392 case VPMINUQZrrk:
25393 case VPMINUQZrrkz:
25394 return true;
25395 }
25396 return false;
25397}
25398
25399bool isFIADD(unsigned Opcode) {
25400 switch (Opcode) {
25401 case ADD_FI16m:
25402 case ADD_FI32m:
25403 return true;
25404 }
25405 return false;
25406}
25407
25408bool isFCMOVNU(unsigned Opcode) {
25409 return Opcode == CMOVNP_F;
25410}
25411
25412bool isVHSUBPD(unsigned Opcode) {
25413 switch (Opcode) {
25414 case VHSUBPDYrm:
25415 case VHSUBPDYrr:
25416 case VHSUBPDrm:
25417 case VHSUBPDrr:
25418 return true;
25419 }
25420 return false;
25421}
25422
25423bool isKSHIFTRQ(unsigned Opcode) {
25424 return Opcode == KSHIFTRQki;
25425}
25426
25427bool isMOVUPS(unsigned Opcode) {
25428 switch (Opcode) {
25429 case MOVUPSmr:
25430 case MOVUPSrm:
25431 case MOVUPSrr:
25432 case MOVUPSrr_REV:
25433 return true;
25434 }
25435 return false;
25436}
25437
25438bool isVMCALL(unsigned Opcode) {
25439 return Opcode == VMCALL;
25440}
25441
25442bool isXADD(unsigned Opcode) {
25443 switch (Opcode) {
25444 case XADD16rm:
25445 case XADD16rr:
25446 case XADD32rm:
25447 case XADD32rr:
25448 case XADD64rm:
25449 case XADD64rr:
25450 case XADD8rm:
25451 case XADD8rr:
25452 return true;
25453 }
25454 return false;
25455}
25456
25457bool isXRSTOR(unsigned Opcode) {
25458 return Opcode == XRSTOR;
25459}
25460
25461bool isVGATHERPF1DPD(unsigned Opcode) {
25462 return Opcode == VGATHERPF1DPDm;
25463}
25464
25465bool isRCR(unsigned Opcode) {
25466 switch (Opcode) {
25467 case RCR16m1:
25468 case RCR16m1_EVEX:
25469 case RCR16m1_ND:
25470 case RCR16mCL:
25471 case RCR16mCL_EVEX:
25472 case RCR16mCL_ND:
25473 case RCR16mi:
25474 case RCR16mi_EVEX:
25475 case RCR16mi_ND:
25476 case RCR16r1:
25477 case RCR16r1_EVEX:
25478 case RCR16r1_ND:
25479 case RCR16rCL:
25480 case RCR16rCL_EVEX:
25481 case RCR16rCL_ND:
25482 case RCR16ri:
25483 case RCR16ri_EVEX:
25484 case RCR16ri_ND:
25485 case RCR32m1:
25486 case RCR32m1_EVEX:
25487 case RCR32m1_ND:
25488 case RCR32mCL:
25489 case RCR32mCL_EVEX:
25490 case RCR32mCL_ND:
25491 case RCR32mi:
25492 case RCR32mi_EVEX:
25493 case RCR32mi_ND:
25494 case RCR32r1:
25495 case RCR32r1_EVEX:
25496 case RCR32r1_ND:
25497 case RCR32rCL:
25498 case RCR32rCL_EVEX:
25499 case RCR32rCL_ND:
25500 case RCR32ri:
25501 case RCR32ri_EVEX:
25502 case RCR32ri_ND:
25503 case RCR64m1:
25504 case RCR64m1_EVEX:
25505 case RCR64m1_ND:
25506 case RCR64mCL:
25507 case RCR64mCL_EVEX:
25508 case RCR64mCL_ND:
25509 case RCR64mi:
25510 case RCR64mi_EVEX:
25511 case RCR64mi_ND:
25512 case RCR64r1:
25513 case RCR64r1_EVEX:
25514 case RCR64r1_ND:
25515 case RCR64rCL:
25516 case RCR64rCL_EVEX:
25517 case RCR64rCL_ND:
25518 case RCR64ri:
25519 case RCR64ri_EVEX:
25520 case RCR64ri_ND:
25521 case RCR8m1:
25522 case RCR8m1_EVEX:
25523 case RCR8m1_ND:
25524 case RCR8mCL:
25525 case RCR8mCL_EVEX:
25526 case RCR8mCL_ND:
25527 case RCR8mi:
25528 case RCR8mi_EVEX:
25529 case RCR8mi_ND:
25530 case RCR8r1:
25531 case RCR8r1_EVEX:
25532 case RCR8r1_ND:
25533 case RCR8rCL:
25534 case RCR8rCL_EVEX:
25535 case RCR8rCL_ND:
25536 case RCR8ri:
25537 case RCR8ri_EVEX:
25538 case RCR8ri_ND:
25539 return true;
25540 }
25541 return false;
25542}
25543
25544bool isFNSTCW(unsigned Opcode) {
25545 return Opcode == FNSTCW16m;
25546}
25547
25548bool isVPMOVSDW(unsigned Opcode) {
25549 switch (Opcode) {
25550 case VPMOVSDWZ128mr:
25551 case VPMOVSDWZ128mrk:
25552 case VPMOVSDWZ128rr:
25553 case VPMOVSDWZ128rrk:
25554 case VPMOVSDWZ128rrkz:
25555 case VPMOVSDWZ256mr:
25556 case VPMOVSDWZ256mrk:
25557 case VPMOVSDWZ256rr:
25558 case VPMOVSDWZ256rrk:
25559 case VPMOVSDWZ256rrkz:
25560 case VPMOVSDWZmr:
25561 case VPMOVSDWZmrk:
25562 case VPMOVSDWZrr:
25563 case VPMOVSDWZrrk:
25564 case VPMOVSDWZrrkz:
25565 return true;
25566 }
25567 return false;
25568}
25569
25570bool isVFMSUB132SH(unsigned Opcode) {
25571 switch (Opcode) {
25572 case VFMSUB132SHZm_Int:
25573 case VFMSUB132SHZmk_Int:
25574 case VFMSUB132SHZmkz_Int:
25575 case VFMSUB132SHZr_Int:
25576 case VFMSUB132SHZrb_Int:
25577 case VFMSUB132SHZrbk_Int:
25578 case VFMSUB132SHZrbkz_Int:
25579 case VFMSUB132SHZrk_Int:
25580 case VFMSUB132SHZrkz_Int:
25581 return true;
25582 }
25583 return false;
25584}
25585
25586bool isVPCONFLICTQ(unsigned Opcode) {
25587 switch (Opcode) {
25588 case VPCONFLICTQZ128rm:
25589 case VPCONFLICTQZ128rmb:
25590 case VPCONFLICTQZ128rmbk:
25591 case VPCONFLICTQZ128rmbkz:
25592 case VPCONFLICTQZ128rmk:
25593 case VPCONFLICTQZ128rmkz:
25594 case VPCONFLICTQZ128rr:
25595 case VPCONFLICTQZ128rrk:
25596 case VPCONFLICTQZ128rrkz:
25597 case VPCONFLICTQZ256rm:
25598 case VPCONFLICTQZ256rmb:
25599 case VPCONFLICTQZ256rmbk:
25600 case VPCONFLICTQZ256rmbkz:
25601 case VPCONFLICTQZ256rmk:
25602 case VPCONFLICTQZ256rmkz:
25603 case VPCONFLICTQZ256rr:
25604 case VPCONFLICTQZ256rrk:
25605 case VPCONFLICTQZ256rrkz:
25606 case VPCONFLICTQZrm:
25607 case VPCONFLICTQZrmb:
25608 case VPCONFLICTQZrmbk:
25609 case VPCONFLICTQZrmbkz:
25610 case VPCONFLICTQZrmk:
25611 case VPCONFLICTQZrmkz:
25612 case VPCONFLICTQZrr:
25613 case VPCONFLICTQZrrk:
25614 case VPCONFLICTQZrrkz:
25615 return true;
25616 }
25617 return false;
25618}
25619
25620bool isSWAPGS(unsigned Opcode) {
25621 return Opcode == SWAPGS;
25622}
25623
25624bool isVPMOVQ2M(unsigned Opcode) {
25625 switch (Opcode) {
25626 case VPMOVQ2MZ128kr:
25627 case VPMOVQ2MZ256kr:
25628 case VPMOVQ2MZkr:
25629 return true;
25630 }
25631 return false;
25632}
25633
25634bool isVPSRAVW(unsigned Opcode) {
25635 switch (Opcode) {
25636 case VPSRAVWZ128rm:
25637 case VPSRAVWZ128rmk:
25638 case VPSRAVWZ128rmkz:
25639 case VPSRAVWZ128rr:
25640 case VPSRAVWZ128rrk:
25641 case VPSRAVWZ128rrkz:
25642 case VPSRAVWZ256rm:
25643 case VPSRAVWZ256rmk:
25644 case VPSRAVWZ256rmkz:
25645 case VPSRAVWZ256rr:
25646 case VPSRAVWZ256rrk:
25647 case VPSRAVWZ256rrkz:
25648 case VPSRAVWZrm:
25649 case VPSRAVWZrmk:
25650 case VPSRAVWZrmkz:
25651 case VPSRAVWZrr:
25652 case VPSRAVWZrrk:
25653 case VPSRAVWZrrkz:
25654 return true;
25655 }
25656 return false;
25657}
25658
25659bool isMOVDQA(unsigned Opcode) {
25660 switch (Opcode) {
25661 case MOVDQAmr:
25662 case MOVDQArm:
25663 case MOVDQArr:
25664 case MOVDQArr_REV:
25665 return true;
25666 }
25667 return false;
25668}
25669
25670bool isDIVSD(unsigned Opcode) {
25671 switch (Opcode) {
25672 case DIVSDrm_Int:
25673 case DIVSDrr_Int:
25674 return true;
25675 }
25676 return false;
25677}
25678
25679bool isPCMPGTB(unsigned Opcode) {
25680 switch (Opcode) {
25681 case MMX_PCMPGTBrm:
25682 case MMX_PCMPGTBrr:
25683 case PCMPGTBrm:
25684 case PCMPGTBrr:
25685 return true;
25686 }
25687 return false;
25688}
25689
25690bool isSHA256MSG2(unsigned Opcode) {
25691 switch (Opcode) {
25692 case SHA256MSG2rm:
25693 case SHA256MSG2rr:
25694 return true;
25695 }
25696 return false;
25697}
25698
25699bool isKXORW(unsigned Opcode) {
25700 return Opcode == KXORWkk;
25701}
25702
25703bool isLIDTW(unsigned Opcode) {
25704 return Opcode == LIDT16m;
25705}
25706
25707bool isPMULHW(unsigned Opcode) {
25708 switch (Opcode) {
25709 case MMX_PMULHWrm:
25710 case MMX_PMULHWrr:
25711 case PMULHWrm:
25712 case PMULHWrr:
25713 return true;
25714 }
25715 return false;
25716}
25717
25718bool isVAESENCLAST(unsigned Opcode) {
25719 switch (Opcode) {
25720 case VAESENCLASTYrm:
25721 case VAESENCLASTYrr:
25722 case VAESENCLASTZ128rm:
25723 case VAESENCLASTZ128rr:
25724 case VAESENCLASTZ256rm:
25725 case VAESENCLASTZ256rr:
25726 case VAESENCLASTZrm:
25727 case VAESENCLASTZrr:
25728 case VAESENCLASTrm:
25729 case VAESENCLASTrr:
25730 return true;
25731 }
25732 return false;
25733}
25734
25735bool isVINSERTI32X8(unsigned Opcode) {
25736 switch (Opcode) {
25737 case VINSERTI32X8Zrmi:
25738 case VINSERTI32X8Zrmik:
25739 case VINSERTI32X8Zrmikz:
25740 case VINSERTI32X8Zrri:
25741 case VINSERTI32X8Zrrik:
25742 case VINSERTI32X8Zrrikz:
25743 return true;
25744 }
25745 return false;
25746}
25747
25748bool isVRCPPS(unsigned Opcode) {
25749 switch (Opcode) {
25750 case VRCPPSYm:
25751 case VRCPPSYr:
25752 case VRCPPSm:
25753 case VRCPPSr:
25754 return true;
25755 }
25756 return false;
25757}
25758
25759bool isVRSQRTBF16(unsigned Opcode) {
25760 switch (Opcode) {
25761 case VRSQRTBF16Z128m:
25762 case VRSQRTBF16Z128mb:
25763 case VRSQRTBF16Z128mbk:
25764 case VRSQRTBF16Z128mbkz:
25765 case VRSQRTBF16Z128mk:
25766 case VRSQRTBF16Z128mkz:
25767 case VRSQRTBF16Z128r:
25768 case VRSQRTBF16Z128rk:
25769 case VRSQRTBF16Z128rkz:
25770 case VRSQRTBF16Z256m:
25771 case VRSQRTBF16Z256mb:
25772 case VRSQRTBF16Z256mbk:
25773 case VRSQRTBF16Z256mbkz:
25774 case VRSQRTBF16Z256mk:
25775 case VRSQRTBF16Z256mkz:
25776 case VRSQRTBF16Z256r:
25777 case VRSQRTBF16Z256rk:
25778 case VRSQRTBF16Z256rkz:
25779 case VRSQRTBF16Zm:
25780 case VRSQRTBF16Zmb:
25781 case VRSQRTBF16Zmbk:
25782 case VRSQRTBF16Zmbkz:
25783 case VRSQRTBF16Zmk:
25784 case VRSQRTBF16Zmkz:
25785 case VRSQRTBF16Zr:
25786 case VRSQRTBF16Zrk:
25787 case VRSQRTBF16Zrkz:
25788 return true;
25789 }
25790 return false;
25791}
25792
25793bool isVGATHERQPS(unsigned Opcode) {
25794 switch (Opcode) {
25795 case VGATHERQPSYrm:
25796 case VGATHERQPSZ128rm:
25797 case VGATHERQPSZ256rm:
25798 case VGATHERQPSZrm:
25799 case VGATHERQPSrm:
25800 return true;
25801 }
25802 return false;
25803}
25804
25805bool isCTESTCC(unsigned Opcode) {
25806 switch (Opcode) {
25807 case CTEST16mi:
25808 case CTEST16mr:
25809 case CTEST16ri:
25810 case CTEST16rr:
25811 case CTEST32mi:
25812 case CTEST32mr:
25813 case CTEST32ri:
25814 case CTEST32rr:
25815 case CTEST64mi32:
25816 case CTEST64mr:
25817 case CTEST64ri32:
25818 case CTEST64rr:
25819 case CTEST8mi:
25820 case CTEST8mr:
25821 case CTEST8ri:
25822 case CTEST8rr:
25823 return true;
25824 }
25825 return false;
25826}
25827
25828bool isPMADDWD(unsigned Opcode) {
25829 switch (Opcode) {
25830 case MMX_PMADDWDrm:
25831 case MMX_PMADDWDrr:
25832 case PMADDWDrm:
25833 case PMADDWDrr:
25834 return true;
25835 }
25836 return false;
25837}
25838
25839bool isUCOMISS(unsigned Opcode) {
25840 switch (Opcode) {
25841 case UCOMISSrm:
25842 case UCOMISSrr:
25843 return true;
25844 }
25845 return false;
25846}
25847
25848bool isXGETBV(unsigned Opcode) {
25849 return Opcode == XGETBV;
25850}
25851
25852bool isVCVTPD2QQ(unsigned Opcode) {
25853 switch (Opcode) {
25854 case VCVTPD2QQZ128rm:
25855 case VCVTPD2QQZ128rmb:
25856 case VCVTPD2QQZ128rmbk:
25857 case VCVTPD2QQZ128rmbkz:
25858 case VCVTPD2QQZ128rmk:
25859 case VCVTPD2QQZ128rmkz:
25860 case VCVTPD2QQZ128rr:
25861 case VCVTPD2QQZ128rrk:
25862 case VCVTPD2QQZ128rrkz:
25863 case VCVTPD2QQZ256rm:
25864 case VCVTPD2QQZ256rmb:
25865 case VCVTPD2QQZ256rmbk:
25866 case VCVTPD2QQZ256rmbkz:
25867 case VCVTPD2QQZ256rmk:
25868 case VCVTPD2QQZ256rmkz:
25869 case VCVTPD2QQZ256rr:
25870 case VCVTPD2QQZ256rrk:
25871 case VCVTPD2QQZ256rrkz:
25872 case VCVTPD2QQZrm:
25873 case VCVTPD2QQZrmb:
25874 case VCVTPD2QQZrmbk:
25875 case VCVTPD2QQZrmbkz:
25876 case VCVTPD2QQZrmk:
25877 case VCVTPD2QQZrmkz:
25878 case VCVTPD2QQZrr:
25879 case VCVTPD2QQZrrb:
25880 case VCVTPD2QQZrrbk:
25881 case VCVTPD2QQZrrbkz:
25882 case VCVTPD2QQZrrk:
25883 case VCVTPD2QQZrrkz:
25884 return true;
25885 }
25886 return false;
25887}
25888
25889bool isVGETEXPPS(unsigned Opcode) {
25890 switch (Opcode) {
25891 case VGETEXPPSZ128m:
25892 case VGETEXPPSZ128mb:
25893 case VGETEXPPSZ128mbk:
25894 case VGETEXPPSZ128mbkz:
25895 case VGETEXPPSZ128mk:
25896 case VGETEXPPSZ128mkz:
25897 case VGETEXPPSZ128r:
25898 case VGETEXPPSZ128rk:
25899 case VGETEXPPSZ128rkz:
25900 case VGETEXPPSZ256m:
25901 case VGETEXPPSZ256mb:
25902 case VGETEXPPSZ256mbk:
25903 case VGETEXPPSZ256mbkz:
25904 case VGETEXPPSZ256mk:
25905 case VGETEXPPSZ256mkz:
25906 case VGETEXPPSZ256r:
25907 case VGETEXPPSZ256rk:
25908 case VGETEXPPSZ256rkz:
25909 case VGETEXPPSZm:
25910 case VGETEXPPSZmb:
25911 case VGETEXPPSZmbk:
25912 case VGETEXPPSZmbkz:
25913 case VGETEXPPSZmk:
25914 case VGETEXPPSZmkz:
25915 case VGETEXPPSZr:
25916 case VGETEXPPSZrb:
25917 case VGETEXPPSZrbk:
25918 case VGETEXPPSZrbkz:
25919 case VGETEXPPSZrk:
25920 case VGETEXPPSZrkz:
25921 return true;
25922 }
25923 return false;
25924}
25925
25926bool isFISTP(unsigned Opcode) {
25927 switch (Opcode) {
25928 case IST_FP16m:
25929 case IST_FP32m:
25930 case IST_FP64m:
25931 return true;
25932 }
25933 return false;
25934}
25935
25936bool isVINSERTF64X4(unsigned Opcode) {
25937 switch (Opcode) {
25938 case VINSERTF64X4Zrmi:
25939 case VINSERTF64X4Zrmik:
25940 case VINSERTF64X4Zrmikz:
25941 case VINSERTF64X4Zrri:
25942 case VINSERTF64X4Zrrik:
25943 case VINSERTF64X4Zrrikz:
25944 return true;
25945 }
25946 return false;
25947}
25948
25949bool isVMOVDQU16(unsigned Opcode) {
25950 switch (Opcode) {
25951 case VMOVDQU16Z128mr:
25952 case VMOVDQU16Z128mrk:
25953 case VMOVDQU16Z128rm:
25954 case VMOVDQU16Z128rmk:
25955 case VMOVDQU16Z128rmkz:
25956 case VMOVDQU16Z128rr:
25957 case VMOVDQU16Z128rr_REV:
25958 case VMOVDQU16Z128rrk:
25959 case VMOVDQU16Z128rrk_REV:
25960 case VMOVDQU16Z128rrkz:
25961 case VMOVDQU16Z128rrkz_REV:
25962 case VMOVDQU16Z256mr:
25963 case VMOVDQU16Z256mrk:
25964 case VMOVDQU16Z256rm:
25965 case VMOVDQU16Z256rmk:
25966 case VMOVDQU16Z256rmkz:
25967 case VMOVDQU16Z256rr:
25968 case VMOVDQU16Z256rr_REV:
25969 case VMOVDQU16Z256rrk:
25970 case VMOVDQU16Z256rrk_REV:
25971 case VMOVDQU16Z256rrkz:
25972 case VMOVDQU16Z256rrkz_REV:
25973 case VMOVDQU16Zmr:
25974 case VMOVDQU16Zmrk:
25975 case VMOVDQU16Zrm:
25976 case VMOVDQU16Zrmk:
25977 case VMOVDQU16Zrmkz:
25978 case VMOVDQU16Zrr:
25979 case VMOVDQU16Zrr_REV:
25980 case VMOVDQU16Zrrk:
25981 case VMOVDQU16Zrrk_REV:
25982 case VMOVDQU16Zrrkz:
25983 case VMOVDQU16Zrrkz_REV:
25984 return true;
25985 }
25986 return false;
25987}
25988
25989bool isVFMADD132PH(unsigned Opcode) {
25990 switch (Opcode) {
25991 case VFMADD132PHZ128m:
25992 case VFMADD132PHZ128mb:
25993 case VFMADD132PHZ128mbk:
25994 case VFMADD132PHZ128mbkz:
25995 case VFMADD132PHZ128mk:
25996 case VFMADD132PHZ128mkz:
25997 case VFMADD132PHZ128r:
25998 case VFMADD132PHZ128rk:
25999 case VFMADD132PHZ128rkz:
26000 case VFMADD132PHZ256m:
26001 case VFMADD132PHZ256mb:
26002 case VFMADD132PHZ256mbk:
26003 case VFMADD132PHZ256mbkz:
26004 case VFMADD132PHZ256mk:
26005 case VFMADD132PHZ256mkz:
26006 case VFMADD132PHZ256r:
26007 case VFMADD132PHZ256rk:
26008 case VFMADD132PHZ256rkz:
26009 case VFMADD132PHZm:
26010 case VFMADD132PHZmb:
26011 case VFMADD132PHZmbk:
26012 case VFMADD132PHZmbkz:
26013 case VFMADD132PHZmk:
26014 case VFMADD132PHZmkz:
26015 case VFMADD132PHZr:
26016 case VFMADD132PHZrb:
26017 case VFMADD132PHZrbk:
26018 case VFMADD132PHZrbkz:
26019 case VFMADD132PHZrk:
26020 case VFMADD132PHZrkz:
26021 return true;
26022 }
26023 return false;
26024}
26025
26026bool isVFMSUBADD213PS(unsigned Opcode) {
26027 switch (Opcode) {
26028 case VFMSUBADD213PSYm:
26029 case VFMSUBADD213PSYr:
26030 case VFMSUBADD213PSZ128m:
26031 case VFMSUBADD213PSZ128mb:
26032 case VFMSUBADD213PSZ128mbk:
26033 case VFMSUBADD213PSZ128mbkz:
26034 case VFMSUBADD213PSZ128mk:
26035 case VFMSUBADD213PSZ128mkz:
26036 case VFMSUBADD213PSZ128r:
26037 case VFMSUBADD213PSZ128rk:
26038 case VFMSUBADD213PSZ128rkz:
26039 case VFMSUBADD213PSZ256m:
26040 case VFMSUBADD213PSZ256mb:
26041 case VFMSUBADD213PSZ256mbk:
26042 case VFMSUBADD213PSZ256mbkz:
26043 case VFMSUBADD213PSZ256mk:
26044 case VFMSUBADD213PSZ256mkz:
26045 case VFMSUBADD213PSZ256r:
26046 case VFMSUBADD213PSZ256rk:
26047 case VFMSUBADD213PSZ256rkz:
26048 case VFMSUBADD213PSZm:
26049 case VFMSUBADD213PSZmb:
26050 case VFMSUBADD213PSZmbk:
26051 case VFMSUBADD213PSZmbkz:
26052 case VFMSUBADD213PSZmk:
26053 case VFMSUBADD213PSZmkz:
26054 case VFMSUBADD213PSZr:
26055 case VFMSUBADD213PSZrb:
26056 case VFMSUBADD213PSZrbk:
26057 case VFMSUBADD213PSZrbkz:
26058 case VFMSUBADD213PSZrk:
26059 case VFMSUBADD213PSZrkz:
26060 case VFMSUBADD213PSm:
26061 case VFMSUBADD213PSr:
26062 return true;
26063 }
26064 return false;
26065}
26066
26067bool isVMOVDQU32(unsigned Opcode) {
26068 switch (Opcode) {
26069 case VMOVDQU32Z128mr:
26070 case VMOVDQU32Z128mrk:
26071 case VMOVDQU32Z128rm:
26072 case VMOVDQU32Z128rmk:
26073 case VMOVDQU32Z128rmkz:
26074 case VMOVDQU32Z128rr:
26075 case VMOVDQU32Z128rr_REV:
26076 case VMOVDQU32Z128rrk:
26077 case VMOVDQU32Z128rrk_REV:
26078 case VMOVDQU32Z128rrkz:
26079 case VMOVDQU32Z128rrkz_REV:
26080 case VMOVDQU32Z256mr:
26081 case VMOVDQU32Z256mrk:
26082 case VMOVDQU32Z256rm:
26083 case VMOVDQU32Z256rmk:
26084 case VMOVDQU32Z256rmkz:
26085 case VMOVDQU32Z256rr:
26086 case VMOVDQU32Z256rr_REV:
26087 case VMOVDQU32Z256rrk:
26088 case VMOVDQU32Z256rrk_REV:
26089 case VMOVDQU32Z256rrkz:
26090 case VMOVDQU32Z256rrkz_REV:
26091 case VMOVDQU32Zmr:
26092 case VMOVDQU32Zmrk:
26093 case VMOVDQU32Zrm:
26094 case VMOVDQU32Zrmk:
26095 case VMOVDQU32Zrmkz:
26096 case VMOVDQU32Zrr:
26097 case VMOVDQU32Zrr_REV:
26098 case VMOVDQU32Zrrk:
26099 case VMOVDQU32Zrrk_REV:
26100 case VMOVDQU32Zrrkz:
26101 case VMOVDQU32Zrrkz_REV:
26102 return true;
26103 }
26104 return false;
26105}
26106
26107bool isFUCOM(unsigned Opcode) {
26108 return Opcode == UCOM_Fr;
26109}
26110
26111bool isVFNMADD213BF16(unsigned Opcode) {
26112 switch (Opcode) {
26113 case VFNMADD213BF16Z128m:
26114 case VFNMADD213BF16Z128mb:
26115 case VFNMADD213BF16Z128mbk:
26116 case VFNMADD213BF16Z128mbkz:
26117 case VFNMADD213BF16Z128mk:
26118 case VFNMADD213BF16Z128mkz:
26119 case VFNMADD213BF16Z128r:
26120 case VFNMADD213BF16Z128rk:
26121 case VFNMADD213BF16Z128rkz:
26122 case VFNMADD213BF16Z256m:
26123 case VFNMADD213BF16Z256mb:
26124 case VFNMADD213BF16Z256mbk:
26125 case VFNMADD213BF16Z256mbkz:
26126 case VFNMADD213BF16Z256mk:
26127 case VFNMADD213BF16Z256mkz:
26128 case VFNMADD213BF16Z256r:
26129 case VFNMADD213BF16Z256rk:
26130 case VFNMADD213BF16Z256rkz:
26131 case VFNMADD213BF16Zm:
26132 case VFNMADD213BF16Zmb:
26133 case VFNMADD213BF16Zmbk:
26134 case VFNMADD213BF16Zmbkz:
26135 case VFNMADD213BF16Zmk:
26136 case VFNMADD213BF16Zmkz:
26137 case VFNMADD213BF16Zr:
26138 case VFNMADD213BF16Zrk:
26139 case VFNMADD213BF16Zrkz:
26140 return true;
26141 }
26142 return false;
26143}
26144
26145bool isHADDPS(unsigned Opcode) {
26146 switch (Opcode) {
26147 case HADDPSrm:
26148 case HADDPSrr:
26149 return true;
26150 }
26151 return false;
26152}
26153
26154bool isCMP(unsigned Opcode) {
26155 switch (Opcode) {
26156 case CMP16i16:
26157 case CMP16mi:
26158 case CMP16mi8:
26159 case CMP16mr:
26160 case CMP16ri:
26161 case CMP16ri8:
26162 case CMP16rm:
26163 case CMP16rr:
26164 case CMP16rr_REV:
26165 case CMP32i32:
26166 case CMP32mi:
26167 case CMP32mi8:
26168 case CMP32mr:
26169 case CMP32ri:
26170 case CMP32ri8:
26171 case CMP32rm:
26172 case CMP32rr:
26173 case CMP32rr_REV:
26174 case CMP64i32:
26175 case CMP64mi32:
26176 case CMP64mi8:
26177 case CMP64mr:
26178 case CMP64ri32:
26179 case CMP64ri8:
26180 case CMP64rm:
26181 case CMP64rr:
26182 case CMP64rr_REV:
26183 case CMP8i8:
26184 case CMP8mi:
26185 case CMP8mi8:
26186 case CMP8mr:
26187 case CMP8ri:
26188 case CMP8ri8:
26189 case CMP8rm:
26190 case CMP8rr:
26191 case CMP8rr_REV:
26192 return true;
26193 }
26194 return false;
26195}
26196
26197bool isCVTTPS2PI(unsigned Opcode) {
26198 switch (Opcode) {
26199 case MMX_CVTTPS2PIrm:
26200 case MMX_CVTTPS2PIrr:
26201 return true;
26202 }
26203 return false;
26204}
26205
26206bool isIRETQ(unsigned Opcode) {
26207 return Opcode == IRET64;
26208}
26209
26210bool isPF2IW(unsigned Opcode) {
26211 switch (Opcode) {
26212 case PF2IWrm:
26213 case PF2IWrr:
26214 return true;
26215 }
26216 return false;
26217}
26218
26219bool isPSHUFD(unsigned Opcode) {
26220 switch (Opcode) {
26221 case PSHUFDmi:
26222 case PSHUFDri:
26223 return true;
26224 }
26225 return false;
26226}
26227
26228bool isVDPPD(unsigned Opcode) {
26229 switch (Opcode) {
26230 case VDPPDrmi:
26231 case VDPPDrri:
26232 return true;
26233 }
26234 return false;
26235}
26236
26237bool isPSHUFHW(unsigned Opcode) {
26238 switch (Opcode) {
26239 case PSHUFHWmi:
26240 case PSHUFHWri:
26241 return true;
26242 }
26243 return false;
26244}
26245
26246bool isRMPADJUST(unsigned Opcode) {
26247 return Opcode == RMPADJUST;
26248}
26249
26250bool isPI2FW(unsigned Opcode) {
26251 switch (Opcode) {
26252 case PI2FWrm:
26253 case PI2FWrr:
26254 return true;
26255 }
26256 return false;
26257}
26258
26259bool isVCVTTPH2QQ(unsigned Opcode) {
26260 switch (Opcode) {
26261 case VCVTTPH2QQZ128rm:
26262 case VCVTTPH2QQZ128rmb:
26263 case VCVTTPH2QQZ128rmbk:
26264 case VCVTTPH2QQZ128rmbkz:
26265 case VCVTTPH2QQZ128rmk:
26266 case VCVTTPH2QQZ128rmkz:
26267 case VCVTTPH2QQZ128rr:
26268 case VCVTTPH2QQZ128rrk:
26269 case VCVTTPH2QQZ128rrkz:
26270 case VCVTTPH2QQZ256rm:
26271 case VCVTTPH2QQZ256rmb:
26272 case VCVTTPH2QQZ256rmbk:
26273 case VCVTTPH2QQZ256rmbkz:
26274 case VCVTTPH2QQZ256rmk:
26275 case VCVTTPH2QQZ256rmkz:
26276 case VCVTTPH2QQZ256rr:
26277 case VCVTTPH2QQZ256rrk:
26278 case VCVTTPH2QQZ256rrkz:
26279 case VCVTTPH2QQZrm:
26280 case VCVTTPH2QQZrmb:
26281 case VCVTTPH2QQZrmbk:
26282 case VCVTTPH2QQZrmbkz:
26283 case VCVTTPH2QQZrmk:
26284 case VCVTTPH2QQZrmkz:
26285 case VCVTTPH2QQZrr:
26286 case VCVTTPH2QQZrrb:
26287 case VCVTTPH2QQZrrbk:
26288 case VCVTTPH2QQZrrbkz:
26289 case VCVTTPH2QQZrrk:
26290 case VCVTTPH2QQZrrkz:
26291 return true;
26292 }
26293 return false;
26294}
26295
26296bool isDIVPD(unsigned Opcode) {
26297 switch (Opcode) {
26298 case DIVPDrm:
26299 case DIVPDrr:
26300 return true;
26301 }
26302 return false;
26303}
26304
26305bool isCLFLUSH(unsigned Opcode) {
26306 return Opcode == CLFLUSH;
26307}
26308
26309bool isVPMINUW(unsigned Opcode) {
26310 switch (Opcode) {
26311 case VPMINUWYrm:
26312 case VPMINUWYrr:
26313 case VPMINUWZ128rm:
26314 case VPMINUWZ128rmk:
26315 case VPMINUWZ128rmkz:
26316 case VPMINUWZ128rr:
26317 case VPMINUWZ128rrk:
26318 case VPMINUWZ128rrkz:
26319 case VPMINUWZ256rm:
26320 case VPMINUWZ256rmk:
26321 case VPMINUWZ256rmkz:
26322 case VPMINUWZ256rr:
26323 case VPMINUWZ256rrk:
26324 case VPMINUWZ256rrkz:
26325 case VPMINUWZrm:
26326 case VPMINUWZrmk:
26327 case VPMINUWZrmkz:
26328 case VPMINUWZrr:
26329 case VPMINUWZrrk:
26330 case VPMINUWZrrkz:
26331 case VPMINUWrm:
26332 case VPMINUWrr:
26333 return true;
26334 }
26335 return false;
26336}
26337
26338bool isIN(unsigned Opcode) {
26339 switch (Opcode) {
26340 case IN16ri:
26341 case IN16rr:
26342 case IN32ri:
26343 case IN32rr:
26344 case IN8ri:
26345 case IN8rr:
26346 return true;
26347 }
26348 return false;
26349}
26350
26351bool isWRPKRU(unsigned Opcode) {
26352 return Opcode == WRPKRUr;
26353}
26354
26355bool isINSERTPS(unsigned Opcode) {
26356 switch (Opcode) {
26357 case INSERTPSrmi:
26358 case INSERTPSrri:
26359 return true;
26360 }
26361 return false;
26362}
26363
26364bool isAAM(unsigned Opcode) {
26365 return Opcode == AAM8i8;
26366}
26367
26368bool isVPHADDUDQ(unsigned Opcode) {
26369 switch (Opcode) {
26370 case VPHADDUDQrm:
26371 case VPHADDUDQrr:
26372 return true;
26373 }
26374 return false;
26375}
26376
26377bool isVSHA512MSG1(unsigned Opcode) {
26378 return Opcode == VSHA512MSG1rr;
26379}
26380
26381bool isDIVPS(unsigned Opcode) {
26382 switch (Opcode) {
26383 case DIVPSrm:
26384 case DIVPSrr:
26385 return true;
26386 }
26387 return false;
26388}
26389
26390bool isKNOTB(unsigned Opcode) {
26391 return Opcode == KNOTBkk;
26392}
26393
26394bool isBLSFILL(unsigned Opcode) {
26395 switch (Opcode) {
26396 case BLSFILL32rm:
26397 case BLSFILL32rr:
26398 case BLSFILL64rm:
26399 case BLSFILL64rr:
26400 return true;
26401 }
26402 return false;
26403}
26404
26405bool isVPCMPGTQ(unsigned Opcode) {
26406 switch (Opcode) {
26407 case VPCMPGTQYrm:
26408 case VPCMPGTQYrr:
26409 case VPCMPGTQZ128rm:
26410 case VPCMPGTQZ128rmb:
26411 case VPCMPGTQZ128rmbk:
26412 case VPCMPGTQZ128rmk:
26413 case VPCMPGTQZ128rr:
26414 case VPCMPGTQZ128rrk:
26415 case VPCMPGTQZ256rm:
26416 case VPCMPGTQZ256rmb:
26417 case VPCMPGTQZ256rmbk:
26418 case VPCMPGTQZ256rmk:
26419 case VPCMPGTQZ256rr:
26420 case VPCMPGTQZ256rrk:
26421 case VPCMPGTQZrm:
26422 case VPCMPGTQZrmb:
26423 case VPCMPGTQZrmbk:
26424 case VPCMPGTQZrmk:
26425 case VPCMPGTQZrr:
26426 case VPCMPGTQZrrk:
26427 case VPCMPGTQrm:
26428 case VPCMPGTQrr:
26429 return true;
26430 }
26431 return false;
26432}
26433
26434bool isMINSD(unsigned Opcode) {
26435 switch (Opcode) {
26436 case MINSDrm_Int:
26437 case MINSDrr_Int:
26438 return true;
26439 }
26440 return false;
26441}
26442
26443bool isFPREM(unsigned Opcode) {
26444 return Opcode == FPREM;
26445}
26446
26447bool isVPUNPCKHQDQ(unsigned Opcode) {
26448 switch (Opcode) {
26449 case VPUNPCKHQDQYrm:
26450 case VPUNPCKHQDQYrr:
26451 case VPUNPCKHQDQZ128rm:
26452 case VPUNPCKHQDQZ128rmb:
26453 case VPUNPCKHQDQZ128rmbk:
26454 case VPUNPCKHQDQZ128rmbkz:
26455 case VPUNPCKHQDQZ128rmk:
26456 case VPUNPCKHQDQZ128rmkz:
26457 case VPUNPCKHQDQZ128rr:
26458 case VPUNPCKHQDQZ128rrk:
26459 case VPUNPCKHQDQZ128rrkz:
26460 case VPUNPCKHQDQZ256rm:
26461 case VPUNPCKHQDQZ256rmb:
26462 case VPUNPCKHQDQZ256rmbk:
26463 case VPUNPCKHQDQZ256rmbkz:
26464 case VPUNPCKHQDQZ256rmk:
26465 case VPUNPCKHQDQZ256rmkz:
26466 case VPUNPCKHQDQZ256rr:
26467 case VPUNPCKHQDQZ256rrk:
26468 case VPUNPCKHQDQZ256rrkz:
26469 case VPUNPCKHQDQZrm:
26470 case VPUNPCKHQDQZrmb:
26471 case VPUNPCKHQDQZrmbk:
26472 case VPUNPCKHQDQZrmbkz:
26473 case VPUNPCKHQDQZrmk:
26474 case VPUNPCKHQDQZrmkz:
26475 case VPUNPCKHQDQZrr:
26476 case VPUNPCKHQDQZrrk:
26477 case VPUNPCKHQDQZrrkz:
26478 case VPUNPCKHQDQrm:
26479 case VPUNPCKHQDQrr:
26480 return true;
26481 }
26482 return false;
26483}
26484
26485bool isMINPD(unsigned Opcode) {
26486 switch (Opcode) {
26487 case MINPDrm:
26488 case MINPDrr:
26489 return true;
26490 }
26491 return false;
26492}
26493
26494bool isVCVTTPD2QQ(unsigned Opcode) {
26495 switch (Opcode) {
26496 case VCVTTPD2QQZ128rm:
26497 case VCVTTPD2QQZ128rmb:
26498 case VCVTTPD2QQZ128rmbk:
26499 case VCVTTPD2QQZ128rmbkz:
26500 case VCVTTPD2QQZ128rmk:
26501 case VCVTTPD2QQZ128rmkz:
26502 case VCVTTPD2QQZ128rr:
26503 case VCVTTPD2QQZ128rrk:
26504 case VCVTTPD2QQZ128rrkz:
26505 case VCVTTPD2QQZ256rm:
26506 case VCVTTPD2QQZ256rmb:
26507 case VCVTTPD2QQZ256rmbk:
26508 case VCVTTPD2QQZ256rmbkz:
26509 case VCVTTPD2QQZ256rmk:
26510 case VCVTTPD2QQZ256rmkz:
26511 case VCVTTPD2QQZ256rr:
26512 case VCVTTPD2QQZ256rrk:
26513 case VCVTTPD2QQZ256rrkz:
26514 case VCVTTPD2QQZrm:
26515 case VCVTTPD2QQZrmb:
26516 case VCVTTPD2QQZrmbk:
26517 case VCVTTPD2QQZrmbkz:
26518 case VCVTTPD2QQZrmk:
26519 case VCVTTPD2QQZrmkz:
26520 case VCVTTPD2QQZrr:
26521 case VCVTTPD2QQZrrb:
26522 case VCVTTPD2QQZrrbk:
26523 case VCVTTPD2QQZrrbkz:
26524 case VCVTTPD2QQZrrk:
26525 case VCVTTPD2QQZrrkz:
26526 return true;
26527 }
26528 return false;
26529}
26530
26531bool isVFMSUBPD(unsigned Opcode) {
26532 switch (Opcode) {
26533 case VFMSUBPD4Ymr:
26534 case VFMSUBPD4Yrm:
26535 case VFMSUBPD4Yrr:
26536 case VFMSUBPD4Yrr_REV:
26537 case VFMSUBPD4mr:
26538 case VFMSUBPD4rm:
26539 case VFMSUBPD4rr:
26540 case VFMSUBPD4rr_REV:
26541 return true;
26542 }
26543 return false;
26544}
26545
26546bool isV4FMADDSS(unsigned Opcode) {
26547 switch (Opcode) {
26548 case V4FMADDSSrm:
26549 case V4FMADDSSrmk:
26550 case V4FMADDSSrmkz:
26551 return true;
26552 }
26553 return false;
26554}
26555
26556bool isCPUID(unsigned Opcode) {
26557 return Opcode == CPUID;
26558}
26559
26560bool isSETCC(unsigned Opcode) {
26561 switch (Opcode) {
26562 case SETCCm:
26563 case SETCCm_EVEX:
26564 case SETCCr:
26565 case SETCCr_EVEX:
26566 return true;
26567 }
26568 return false;
26569}
26570
26571bool isVPDPWUUD(unsigned Opcode) {
26572 switch (Opcode) {
26573 case VPDPWUUDYrm:
26574 case VPDPWUUDYrr:
26575 case VPDPWUUDZ128rm:
26576 case VPDPWUUDZ128rmb:
26577 case VPDPWUUDZ128rmbk:
26578 case VPDPWUUDZ128rmbkz:
26579 case VPDPWUUDZ128rmk:
26580 case VPDPWUUDZ128rmkz:
26581 case VPDPWUUDZ128rr:
26582 case VPDPWUUDZ128rrk:
26583 case VPDPWUUDZ128rrkz:
26584 case VPDPWUUDZ256rm:
26585 case VPDPWUUDZ256rmb:
26586 case VPDPWUUDZ256rmbk:
26587 case VPDPWUUDZ256rmbkz:
26588 case VPDPWUUDZ256rmk:
26589 case VPDPWUUDZ256rmkz:
26590 case VPDPWUUDZ256rr:
26591 case VPDPWUUDZ256rrk:
26592 case VPDPWUUDZ256rrkz:
26593 case VPDPWUUDZrm:
26594 case VPDPWUUDZrmb:
26595 case VPDPWUUDZrmbk:
26596 case VPDPWUUDZrmbkz:
26597 case VPDPWUUDZrmk:
26598 case VPDPWUUDZrmkz:
26599 case VPDPWUUDZrr:
26600 case VPDPWUUDZrrk:
26601 case VPDPWUUDZrrkz:
26602 case VPDPWUUDrm:
26603 case VPDPWUUDrr:
26604 return true;
26605 }
26606 return false;
26607}
26608
26609bool isVCVTTPS2IUBS(unsigned Opcode) {
26610 switch (Opcode) {
26611 case VCVTTPS2IUBSZ128rm:
26612 case VCVTTPS2IUBSZ128rmb:
26613 case VCVTTPS2IUBSZ128rmbk:
26614 case VCVTTPS2IUBSZ128rmbkz:
26615 case VCVTTPS2IUBSZ128rmk:
26616 case VCVTTPS2IUBSZ128rmkz:
26617 case VCVTTPS2IUBSZ128rr:
26618 case VCVTTPS2IUBSZ128rrk:
26619 case VCVTTPS2IUBSZ128rrkz:
26620 case VCVTTPS2IUBSZ256rm:
26621 case VCVTTPS2IUBSZ256rmb:
26622 case VCVTTPS2IUBSZ256rmbk:
26623 case VCVTTPS2IUBSZ256rmbkz:
26624 case VCVTTPS2IUBSZ256rmk:
26625 case VCVTTPS2IUBSZ256rmkz:
26626 case VCVTTPS2IUBSZ256rr:
26627 case VCVTTPS2IUBSZ256rrk:
26628 case VCVTTPS2IUBSZ256rrkz:
26629 case VCVTTPS2IUBSZrm:
26630 case VCVTTPS2IUBSZrmb:
26631 case VCVTTPS2IUBSZrmbk:
26632 case VCVTTPS2IUBSZrmbkz:
26633 case VCVTTPS2IUBSZrmk:
26634 case VCVTTPS2IUBSZrmkz:
26635 case VCVTTPS2IUBSZrr:
26636 case VCVTTPS2IUBSZrrb:
26637 case VCVTTPS2IUBSZrrbk:
26638 case VCVTTPS2IUBSZrrbkz:
26639 case VCVTTPS2IUBSZrrk:
26640 case VCVTTPS2IUBSZrrkz:
26641 return true;
26642 }
26643 return false;
26644}
26645
26646bool isPMOVSXDQ(unsigned Opcode) {
26647 switch (Opcode) {
26648 case PMOVSXDQrm:
26649 case PMOVSXDQrr:
26650 return true;
26651 }
26652 return false;
26653}
26654
26655bool isMWAIT(unsigned Opcode) {
26656 return Opcode == MWAITrr;
26657}
26658
26659bool isVPEXTRB(unsigned Opcode) {
26660 switch (Opcode) {
26661 case VPEXTRBZmri:
26662 case VPEXTRBZrri:
26663 case VPEXTRBmri:
26664 case VPEXTRBrri:
26665 return true;
26666 }
26667 return false;
26668}
26669
26670bool isINVVPID(unsigned Opcode) {
26671 switch (Opcode) {
26672 case INVVPID32:
26673 case INVVPID64:
26674 case INVVPID64_EVEX:
26675 return true;
26676 }
26677 return false;
26678}
26679
26680bool isVPSHUFD(unsigned Opcode) {
26681 switch (Opcode) {
26682 case VPSHUFDYmi:
26683 case VPSHUFDYri:
26684 case VPSHUFDZ128mbi:
26685 case VPSHUFDZ128mbik:
26686 case VPSHUFDZ128mbikz:
26687 case VPSHUFDZ128mi:
26688 case VPSHUFDZ128mik:
26689 case VPSHUFDZ128mikz:
26690 case VPSHUFDZ128ri:
26691 case VPSHUFDZ128rik:
26692 case VPSHUFDZ128rikz:
26693 case VPSHUFDZ256mbi:
26694 case VPSHUFDZ256mbik:
26695 case VPSHUFDZ256mbikz:
26696 case VPSHUFDZ256mi:
26697 case VPSHUFDZ256mik:
26698 case VPSHUFDZ256mikz:
26699 case VPSHUFDZ256ri:
26700 case VPSHUFDZ256rik:
26701 case VPSHUFDZ256rikz:
26702 case VPSHUFDZmbi:
26703 case VPSHUFDZmbik:
26704 case VPSHUFDZmbikz:
26705 case VPSHUFDZmi:
26706 case VPSHUFDZmik:
26707 case VPSHUFDZmikz:
26708 case VPSHUFDZri:
26709 case VPSHUFDZrik:
26710 case VPSHUFDZrikz:
26711 case VPSHUFDmi:
26712 case VPSHUFDri:
26713 return true;
26714 }
26715 return false;
26716}
26717
26718bool isVMINBF16(unsigned Opcode) {
26719 switch (Opcode) {
26720 case VMINBF16Z128rm:
26721 case VMINBF16Z128rmb:
26722 case VMINBF16Z128rmbk:
26723 case VMINBF16Z128rmbkz:
26724 case VMINBF16Z128rmk:
26725 case VMINBF16Z128rmkz:
26726 case VMINBF16Z128rr:
26727 case VMINBF16Z128rrk:
26728 case VMINBF16Z128rrkz:
26729 case VMINBF16Z256rm:
26730 case VMINBF16Z256rmb:
26731 case VMINBF16Z256rmbk:
26732 case VMINBF16Z256rmbkz:
26733 case VMINBF16Z256rmk:
26734 case VMINBF16Z256rmkz:
26735 case VMINBF16Z256rr:
26736 case VMINBF16Z256rrk:
26737 case VMINBF16Z256rrkz:
26738 case VMINBF16Zrm:
26739 case VMINBF16Zrmb:
26740 case VMINBF16Zrmbk:
26741 case VMINBF16Zrmbkz:
26742 case VMINBF16Zrmk:
26743 case VMINBF16Zrmkz:
26744 case VMINBF16Zrr:
26745 case VMINBF16Zrrk:
26746 case VMINBF16Zrrkz:
26747 return true;
26748 }
26749 return false;
26750}
26751
26752bool isMOVLPS(unsigned Opcode) {
26753 switch (Opcode) {
26754 case MOVLPSmr:
26755 case MOVLPSrm:
26756 return true;
26757 }
26758 return false;
26759}
26760
26761bool isVBLENDMPS(unsigned Opcode) {
26762 switch (Opcode) {
26763 case VBLENDMPSZ128rm:
26764 case VBLENDMPSZ128rmb:
26765 case VBLENDMPSZ128rmbk:
26766 case VBLENDMPSZ128rmbkz:
26767 case VBLENDMPSZ128rmk:
26768 case VBLENDMPSZ128rmkz:
26769 case VBLENDMPSZ128rr:
26770 case VBLENDMPSZ128rrk:
26771 case VBLENDMPSZ128rrkz:
26772 case VBLENDMPSZ256rm:
26773 case VBLENDMPSZ256rmb:
26774 case VBLENDMPSZ256rmbk:
26775 case VBLENDMPSZ256rmbkz:
26776 case VBLENDMPSZ256rmk:
26777 case VBLENDMPSZ256rmkz:
26778 case VBLENDMPSZ256rr:
26779 case VBLENDMPSZ256rrk:
26780 case VBLENDMPSZ256rrkz:
26781 case VBLENDMPSZrm:
26782 case VBLENDMPSZrmb:
26783 case VBLENDMPSZrmbk:
26784 case VBLENDMPSZrmbkz:
26785 case VBLENDMPSZrmk:
26786 case VBLENDMPSZrmkz:
26787 case VBLENDMPSZrr:
26788 case VBLENDMPSZrrk:
26789 case VBLENDMPSZrrkz:
26790 return true;
26791 }
26792 return false;
26793}
26794
26795bool isPMULLW(unsigned Opcode) {
26796 switch (Opcode) {
26797 case MMX_PMULLWrm:
26798 case MMX_PMULLWrr:
26799 case PMULLWrm:
26800 case PMULLWrr:
26801 return true;
26802 }
26803 return false;
26804}
26805
26806bool isVCVTSH2SI(unsigned Opcode) {
26807 switch (Opcode) {
26808 case VCVTSH2SI64Zrm_Int:
26809 case VCVTSH2SI64Zrr_Int:
26810 case VCVTSH2SI64Zrrb_Int:
26811 case VCVTSH2SIZrm_Int:
26812 case VCVTSH2SIZrr_Int:
26813 case VCVTSH2SIZrrb_Int:
26814 return true;
26815 }
26816 return false;
26817}
26818
26819bool isVPMOVSXWQ(unsigned Opcode) {
26820 switch (Opcode) {
26821 case VPMOVSXWQYrm:
26822 case VPMOVSXWQYrr:
26823 case VPMOVSXWQZ128rm:
26824 case VPMOVSXWQZ128rmk:
26825 case VPMOVSXWQZ128rmkz:
26826 case VPMOVSXWQZ128rr:
26827 case VPMOVSXWQZ128rrk:
26828 case VPMOVSXWQZ128rrkz:
26829 case VPMOVSXWQZ256rm:
26830 case VPMOVSXWQZ256rmk:
26831 case VPMOVSXWQZ256rmkz:
26832 case VPMOVSXWQZ256rr:
26833 case VPMOVSXWQZ256rrk:
26834 case VPMOVSXWQZ256rrkz:
26835 case VPMOVSXWQZrm:
26836 case VPMOVSXWQZrmk:
26837 case VPMOVSXWQZrmkz:
26838 case VPMOVSXWQZrr:
26839 case VPMOVSXWQZrrk:
26840 case VPMOVSXWQZrrkz:
26841 case VPMOVSXWQrm:
26842 case VPMOVSXWQrr:
26843 return true;
26844 }
26845 return false;
26846}
26847
26848bool isFNSTENV(unsigned Opcode) {
26849 return Opcode == FSTENVm;
26850}
26851
26852bool isVCVT2PH2BF8(unsigned Opcode) {
26853 switch (Opcode) {
26854 case VCVT2PH2BF8Z128rm:
26855 case VCVT2PH2BF8Z128rmb:
26856 case VCVT2PH2BF8Z128rmbk:
26857 case VCVT2PH2BF8Z128rmbkz:
26858 case VCVT2PH2BF8Z128rmk:
26859 case VCVT2PH2BF8Z128rmkz:
26860 case VCVT2PH2BF8Z128rr:
26861 case VCVT2PH2BF8Z128rrk:
26862 case VCVT2PH2BF8Z128rrkz:
26863 case VCVT2PH2BF8Z256rm:
26864 case VCVT2PH2BF8Z256rmb:
26865 case VCVT2PH2BF8Z256rmbk:
26866 case VCVT2PH2BF8Z256rmbkz:
26867 case VCVT2PH2BF8Z256rmk:
26868 case VCVT2PH2BF8Z256rmkz:
26869 case VCVT2PH2BF8Z256rr:
26870 case VCVT2PH2BF8Z256rrk:
26871 case VCVT2PH2BF8Z256rrkz:
26872 case VCVT2PH2BF8Zrm:
26873 case VCVT2PH2BF8Zrmb:
26874 case VCVT2PH2BF8Zrmbk:
26875 case VCVT2PH2BF8Zrmbkz:
26876 case VCVT2PH2BF8Zrmk:
26877 case VCVT2PH2BF8Zrmkz:
26878 case VCVT2PH2BF8Zrr:
26879 case VCVT2PH2BF8Zrrk:
26880 case VCVT2PH2BF8Zrrkz:
26881 return true;
26882 }
26883 return false;
26884}
26885
26886bool isVPERMI2PD(unsigned Opcode) {
26887 switch (Opcode) {
26888 case VPERMI2PDZ128rm:
26889 case VPERMI2PDZ128rmb:
26890 case VPERMI2PDZ128rmbk:
26891 case VPERMI2PDZ128rmbkz:
26892 case VPERMI2PDZ128rmk:
26893 case VPERMI2PDZ128rmkz:
26894 case VPERMI2PDZ128rr:
26895 case VPERMI2PDZ128rrk:
26896 case VPERMI2PDZ128rrkz:
26897 case VPERMI2PDZ256rm:
26898 case VPERMI2PDZ256rmb:
26899 case VPERMI2PDZ256rmbk:
26900 case VPERMI2PDZ256rmbkz:
26901 case VPERMI2PDZ256rmk:
26902 case VPERMI2PDZ256rmkz:
26903 case VPERMI2PDZ256rr:
26904 case VPERMI2PDZ256rrk:
26905 case VPERMI2PDZ256rrkz:
26906 case VPERMI2PDZrm:
26907 case VPERMI2PDZrmb:
26908 case VPERMI2PDZrmbk:
26909 case VPERMI2PDZrmbkz:
26910 case VPERMI2PDZrmk:
26911 case VPERMI2PDZrmkz:
26912 case VPERMI2PDZrr:
26913 case VPERMI2PDZrrk:
26914 case VPERMI2PDZrrkz:
26915 return true;
26916 }
26917 return false;
26918}
26919
26920bool isMAXSS(unsigned Opcode) {
26921 switch (Opcode) {
26922 case MAXSSrm_Int:
26923 case MAXSSrr_Int:
26924 return true;
26925 }
26926 return false;
26927}
26928
26929bool isCWDE(unsigned Opcode) {
26930 return Opcode == CWDE;
26931}
26932
26933bool isVBROADCASTI32X8(unsigned Opcode) {
26934 switch (Opcode) {
26935 case VBROADCASTI32X8Zrm:
26936 case VBROADCASTI32X8Zrmk:
26937 case VBROADCASTI32X8Zrmkz:
26938 return true;
26939 }
26940 return false;
26941}
26942
26943bool isINT(unsigned Opcode) {
26944 return Opcode == INT;
26945}
26946
26947bool isENCLS(unsigned Opcode) {
26948 return Opcode == ENCLS;
26949}
26950
26951bool isMOVNTQ(unsigned Opcode) {
26952 return Opcode == MMX_MOVNTQmr;
26953}
26954
26955bool isVDIVSH(unsigned Opcode) {
26956 switch (Opcode) {
26957 case VDIVSHZrm_Int:
26958 case VDIVSHZrmk_Int:
26959 case VDIVSHZrmkz_Int:
26960 case VDIVSHZrr_Int:
26961 case VDIVSHZrrb_Int:
26962 case VDIVSHZrrbk_Int:
26963 case VDIVSHZrrbkz_Int:
26964 case VDIVSHZrrk_Int:
26965 case VDIVSHZrrkz_Int:
26966 return true;
26967 }
26968 return false;
26969}
26970
26971bool isMOVHLPS(unsigned Opcode) {
26972 return Opcode == MOVHLPSrr;
26973}
26974
26975bool isVPMASKMOVD(unsigned Opcode) {
26976 switch (Opcode) {
26977 case VPMASKMOVDYmr:
26978 case VPMASKMOVDYrm:
26979 case VPMASKMOVDmr:
26980 case VPMASKMOVDrm:
26981 return true;
26982 }
26983 return false;
26984}
26985
26986bool isVMOVSD(unsigned Opcode) {
26987 switch (Opcode) {
26988 case VMOVSDZmr:
26989 case VMOVSDZmrk:
26990 case VMOVSDZrm:
26991 case VMOVSDZrmk:
26992 case VMOVSDZrmkz:
26993 case VMOVSDZrr:
26994 case VMOVSDZrr_REV:
26995 case VMOVSDZrrk:
26996 case VMOVSDZrrk_REV:
26997 case VMOVSDZrrkz:
26998 case VMOVSDZrrkz_REV:
26999 case VMOVSDmr:
27000 case VMOVSDrm:
27001 case VMOVSDrr:
27002 case VMOVSDrr_REV:
27003 return true;
27004 }
27005 return false;
27006}
27007
27008bool isVPMINUD(unsigned Opcode) {
27009 switch (Opcode) {
27010 case VPMINUDYrm:
27011 case VPMINUDYrr:
27012 case VPMINUDZ128rm:
27013 case VPMINUDZ128rmb:
27014 case VPMINUDZ128rmbk:
27015 case VPMINUDZ128rmbkz:
27016 case VPMINUDZ128rmk:
27017 case VPMINUDZ128rmkz:
27018 case VPMINUDZ128rr:
27019 case VPMINUDZ128rrk:
27020 case VPMINUDZ128rrkz:
27021 case VPMINUDZ256rm:
27022 case VPMINUDZ256rmb:
27023 case VPMINUDZ256rmbk:
27024 case VPMINUDZ256rmbkz:
27025 case VPMINUDZ256rmk:
27026 case VPMINUDZ256rmkz:
27027 case VPMINUDZ256rr:
27028 case VPMINUDZ256rrk:
27029 case VPMINUDZ256rrkz:
27030 case VPMINUDZrm:
27031 case VPMINUDZrmb:
27032 case VPMINUDZrmbk:
27033 case VPMINUDZrmbkz:
27034 case VPMINUDZrmk:
27035 case VPMINUDZrmkz:
27036 case VPMINUDZrr:
27037 case VPMINUDZrrk:
27038 case VPMINUDZrrkz:
27039 case VPMINUDrm:
27040 case VPMINUDrr:
27041 return true;
27042 }
27043 return false;
27044}
27045
27046bool isVPCMPISTRM(unsigned Opcode) {
27047 switch (Opcode) {
27048 case VPCMPISTRMrmi:
27049 case VPCMPISTRMrri:
27050 return true;
27051 }
27052 return false;
27053}
27054
27055bool isVGETMANTSD(unsigned Opcode) {
27056 switch (Opcode) {
27057 case VGETMANTSDZrmi:
27058 case VGETMANTSDZrmik:
27059 case VGETMANTSDZrmikz:
27060 case VGETMANTSDZrri:
27061 case VGETMANTSDZrrib:
27062 case VGETMANTSDZrribk:
27063 case VGETMANTSDZrribkz:
27064 case VGETMANTSDZrrik:
27065 case VGETMANTSDZrrikz:
27066 return true;
27067 }
27068 return false;
27069}
27070
27071bool isKSHIFTRW(unsigned Opcode) {
27072 return Opcode == KSHIFTRWki;
27073}
27074
27075bool isAESDECLAST(unsigned Opcode) {
27076 switch (Opcode) {
27077 case AESDECLASTrm:
27078 case AESDECLASTrr:
27079 return true;
27080 }
27081 return false;
27082}
27083
27084bool isVFNMSUB231BF16(unsigned Opcode) {
27085 switch (Opcode) {
27086 case VFNMSUB231BF16Z128m:
27087 case VFNMSUB231BF16Z128mb:
27088 case VFNMSUB231BF16Z128mbk:
27089 case VFNMSUB231BF16Z128mbkz:
27090 case VFNMSUB231BF16Z128mk:
27091 case VFNMSUB231BF16Z128mkz:
27092 case VFNMSUB231BF16Z128r:
27093 case VFNMSUB231BF16Z128rk:
27094 case VFNMSUB231BF16Z128rkz:
27095 case VFNMSUB231BF16Z256m:
27096 case VFNMSUB231BF16Z256mb:
27097 case VFNMSUB231BF16Z256mbk:
27098 case VFNMSUB231BF16Z256mbkz:
27099 case VFNMSUB231BF16Z256mk:
27100 case VFNMSUB231BF16Z256mkz:
27101 case VFNMSUB231BF16Z256r:
27102 case VFNMSUB231BF16Z256rk:
27103 case VFNMSUB231BF16Z256rkz:
27104 case VFNMSUB231BF16Zm:
27105 case VFNMSUB231BF16Zmb:
27106 case VFNMSUB231BF16Zmbk:
27107 case VFNMSUB231BF16Zmbkz:
27108 case VFNMSUB231BF16Zmk:
27109 case VFNMSUB231BF16Zmkz:
27110 case VFNMSUB231BF16Zr:
27111 case VFNMSUB231BF16Zrk:
27112 case VFNMSUB231BF16Zrkz:
27113 return true;
27114 }
27115 return false;
27116}
27117
27118bool isVMPTRST(unsigned Opcode) {
27119 return Opcode == VMPTRSTm;
27120}
27121
27122bool isLLDT(unsigned Opcode) {
27123 switch (Opcode) {
27124 case LLDT16m:
27125 case LLDT16r:
27126 return true;
27127 }
27128 return false;
27129}
27130
27131bool isVPTESTMB(unsigned Opcode) {
27132 switch (Opcode) {
27133 case VPTESTMBZ128rm:
27134 case VPTESTMBZ128rmk:
27135 case VPTESTMBZ128rr:
27136 case VPTESTMBZ128rrk:
27137 case VPTESTMBZ256rm:
27138 case VPTESTMBZ256rmk:
27139 case VPTESTMBZ256rr:
27140 case VPTESTMBZ256rrk:
27141 case VPTESTMBZrm:
27142 case VPTESTMBZrmk:
27143 case VPTESTMBZrr:
27144 case VPTESTMBZrrk:
27145 return true;
27146 }
27147 return false;
27148}
27149
27150bool isMOVSB(unsigned Opcode) {
27151 return Opcode == MOVSB;
27152}
27153
27154bool isTILELOADD(unsigned Opcode) {
27155 switch (Opcode) {
27156 case TILELOADD:
27157 case TILELOADD_EVEX:
27158 return true;
27159 }
27160 return false;
27161}
27162
27163bool isKTESTB(unsigned Opcode) {
27164 return Opcode == KTESTBkk;
27165}
27166
27167bool isMOVUPD(unsigned Opcode) {
27168 switch (Opcode) {
27169 case MOVUPDmr:
27170 case MOVUPDrm:
27171 case MOVUPDrr:
27172 case MOVUPDrr_REV:
27173 return true;
27174 }
27175 return false;
27176}
27177
27178bool isLKGS(unsigned Opcode) {
27179 switch (Opcode) {
27180 case LKGS16m:
27181 case LKGS16r:
27182 return true;
27183 }
27184 return false;
27185}
27186
27187bool isSGDTW(unsigned Opcode) {
27188 return Opcode == SGDT16m;
27189}
27190
27191bool isDIVSS(unsigned Opcode) {
27192 switch (Opcode) {
27193 case DIVSSrm_Int:
27194 case DIVSSrr_Int:
27195 return true;
27196 }
27197 return false;
27198}
27199
27200bool isPUNPCKHQDQ(unsigned Opcode) {
27201 switch (Opcode) {
27202 case PUNPCKHQDQrm:
27203 case PUNPCKHQDQrr:
27204 return true;
27205 }
27206 return false;
27207}
27208
27209bool isVFMADD213SD(unsigned Opcode) {
27210 switch (Opcode) {
27211 case VFMADD213SDZm_Int:
27212 case VFMADD213SDZmk_Int:
27213 case VFMADD213SDZmkz_Int:
27214 case VFMADD213SDZr_Int:
27215 case VFMADD213SDZrb_Int:
27216 case VFMADD213SDZrbk_Int:
27217 case VFMADD213SDZrbkz_Int:
27218 case VFMADD213SDZrk_Int:
27219 case VFMADD213SDZrkz_Int:
27220 case VFMADD213SDm_Int:
27221 case VFMADD213SDr_Int:
27222 return true;
27223 }
27224 return false;
27225}
27226
27227bool isKXORD(unsigned Opcode) {
27228 return Opcode == KXORDkk;
27229}
27230
27231bool isVPMOVB2M(unsigned Opcode) {
27232 switch (Opcode) {
27233 case VPMOVB2MZ128kr:
27234 case VPMOVB2MZ256kr:
27235 case VPMOVB2MZkr:
27236 return true;
27237 }
27238 return false;
27239}
27240
27241bool isVMREAD(unsigned Opcode) {
27242 switch (Opcode) {
27243 case VMREAD32mr:
27244 case VMREAD32rr:
27245 case VMREAD64mr:
27246 case VMREAD64rr:
27247 return true;
27248 }
27249 return false;
27250}
27251
27252bool isVPDPWSSDS(unsigned Opcode) {
27253 switch (Opcode) {
27254 case VPDPWSSDSYrm:
27255 case VPDPWSSDSYrr:
27256 case VPDPWSSDSZ128rm:
27257 case VPDPWSSDSZ128rmb:
27258 case VPDPWSSDSZ128rmbk:
27259 case VPDPWSSDSZ128rmbkz:
27260 case VPDPWSSDSZ128rmk:
27261 case VPDPWSSDSZ128rmkz:
27262 case VPDPWSSDSZ128rr:
27263 case VPDPWSSDSZ128rrk:
27264 case VPDPWSSDSZ128rrkz:
27265 case VPDPWSSDSZ256rm:
27266 case VPDPWSSDSZ256rmb:
27267 case VPDPWSSDSZ256rmbk:
27268 case VPDPWSSDSZ256rmbkz:
27269 case VPDPWSSDSZ256rmk:
27270 case VPDPWSSDSZ256rmkz:
27271 case VPDPWSSDSZ256rr:
27272 case VPDPWSSDSZ256rrk:
27273 case VPDPWSSDSZ256rrkz:
27274 case VPDPWSSDSZrm:
27275 case VPDPWSSDSZrmb:
27276 case VPDPWSSDSZrmbk:
27277 case VPDPWSSDSZrmbkz:
27278 case VPDPWSSDSZrmk:
27279 case VPDPWSSDSZrmkz:
27280 case VPDPWSSDSZrr:
27281 case VPDPWSSDSZrrk:
27282 case VPDPWSSDSZrrkz:
27283 case VPDPWSSDSrm:
27284 case VPDPWSSDSrr:
27285 return true;
27286 }
27287 return false;
27288}
27289
27290bool isTILERELEASE(unsigned Opcode) {
27291 return Opcode == TILERELEASE;
27292}
27293
27294bool isVUCOMXSH(unsigned Opcode) {
27295 switch (Opcode) {
27296 case VUCOMXSHZrm_Int:
27297 case VUCOMXSHZrr_Int:
27298 case VUCOMXSHZrrb_Int:
27299 return true;
27300 }
27301 return false;
27302}
27303
27304bool isCLFLUSHOPT(unsigned Opcode) {
27305 return Opcode == CLFLUSHOPT;
27306}
27307
27308bool isDAS(unsigned Opcode) {
27309 return Opcode == DAS;
27310}
27311
27312bool isVSCALEFPH(unsigned Opcode) {
27313 switch (Opcode) {
27314 case VSCALEFPHZ128rm:
27315 case VSCALEFPHZ128rmb:
27316 case VSCALEFPHZ128rmbk:
27317 case VSCALEFPHZ128rmbkz:
27318 case VSCALEFPHZ128rmk:
27319 case VSCALEFPHZ128rmkz:
27320 case VSCALEFPHZ128rr:
27321 case VSCALEFPHZ128rrk:
27322 case VSCALEFPHZ128rrkz:
27323 case VSCALEFPHZ256rm:
27324 case VSCALEFPHZ256rmb:
27325 case VSCALEFPHZ256rmbk:
27326 case VSCALEFPHZ256rmbkz:
27327 case VSCALEFPHZ256rmk:
27328 case VSCALEFPHZ256rmkz:
27329 case VSCALEFPHZ256rr:
27330 case VSCALEFPHZ256rrk:
27331 case VSCALEFPHZ256rrkz:
27332 case VSCALEFPHZrm:
27333 case VSCALEFPHZrmb:
27334 case VSCALEFPHZrmbk:
27335 case VSCALEFPHZrmbkz:
27336 case VSCALEFPHZrmk:
27337 case VSCALEFPHZrmkz:
27338 case VSCALEFPHZrr:
27339 case VSCALEFPHZrrb:
27340 case VSCALEFPHZrrbk:
27341 case VSCALEFPHZrrbkz:
27342 case VSCALEFPHZrrk:
27343 case VSCALEFPHZrrkz:
27344 return true;
27345 }
27346 return false;
27347}
27348
27349bool isVSUBSD(unsigned Opcode) {
27350 switch (Opcode) {
27351 case VSUBSDZrm_Int:
27352 case VSUBSDZrmk_Int:
27353 case VSUBSDZrmkz_Int:
27354 case VSUBSDZrr_Int:
27355 case VSUBSDZrrb_Int:
27356 case VSUBSDZrrbk_Int:
27357 case VSUBSDZrrbkz_Int:
27358 case VSUBSDZrrk_Int:
27359 case VSUBSDZrrkz_Int:
27360 case VSUBSDrm_Int:
27361 case VSUBSDrr_Int:
27362 return true;
27363 }
27364 return false;
27365}
27366
27367bool isVCOMISS(unsigned Opcode) {
27368 switch (Opcode) {
27369 case VCOMISSZrm:
27370 case VCOMISSZrr:
27371 case VCOMISSZrrb:
27372 case VCOMISSrm:
27373 case VCOMISSrr:
27374 return true;
27375 }
27376 return false;
27377}
27378
27379bool isVMULBF16(unsigned Opcode) {
27380 switch (Opcode) {
27381 case VMULBF16Z128rm:
27382 case VMULBF16Z128rmb:
27383 case VMULBF16Z128rmbk:
27384 case VMULBF16Z128rmbkz:
27385 case VMULBF16Z128rmk:
27386 case VMULBF16Z128rmkz:
27387 case VMULBF16Z128rr:
27388 case VMULBF16Z128rrk:
27389 case VMULBF16Z128rrkz:
27390 case VMULBF16Z256rm:
27391 case VMULBF16Z256rmb:
27392 case VMULBF16Z256rmbk:
27393 case VMULBF16Z256rmbkz:
27394 case VMULBF16Z256rmk:
27395 case VMULBF16Z256rmkz:
27396 case VMULBF16Z256rr:
27397 case VMULBF16Z256rrk:
27398 case VMULBF16Z256rrkz:
27399 case VMULBF16Zrm:
27400 case VMULBF16Zrmb:
27401 case VMULBF16Zrmbk:
27402 case VMULBF16Zrmbkz:
27403 case VMULBF16Zrmk:
27404 case VMULBF16Zrmkz:
27405 case VMULBF16Zrr:
27406 case VMULBF16Zrrk:
27407 case VMULBF16Zrrkz:
27408 return true;
27409 }
27410 return false;
27411}
27412
27413bool isORPS(unsigned Opcode) {
27414 switch (Opcode) {
27415 case ORPSrm:
27416 case ORPSrr:
27417 return true;
27418 }
27419 return false;
27420}
27421
27422bool isTDPFP16PS(unsigned Opcode) {
27423 return Opcode == TDPFP16PS;
27424}
27425
27426bool isVMAXPD(unsigned Opcode) {
27427 switch (Opcode) {
27428 case VMAXPDYrm:
27429 case VMAXPDYrr:
27430 case VMAXPDZ128rm:
27431 case VMAXPDZ128rmb:
27432 case VMAXPDZ128rmbk:
27433 case VMAXPDZ128rmbkz:
27434 case VMAXPDZ128rmk:
27435 case VMAXPDZ128rmkz:
27436 case VMAXPDZ128rr:
27437 case VMAXPDZ128rrk:
27438 case VMAXPDZ128rrkz:
27439 case VMAXPDZ256rm:
27440 case VMAXPDZ256rmb:
27441 case VMAXPDZ256rmbk:
27442 case VMAXPDZ256rmbkz:
27443 case VMAXPDZ256rmk:
27444 case VMAXPDZ256rmkz:
27445 case VMAXPDZ256rr:
27446 case VMAXPDZ256rrk:
27447 case VMAXPDZ256rrkz:
27448 case VMAXPDZrm:
27449 case VMAXPDZrmb:
27450 case VMAXPDZrmbk:
27451 case VMAXPDZrmbkz:
27452 case VMAXPDZrmk:
27453 case VMAXPDZrmkz:
27454 case VMAXPDZrr:
27455 case VMAXPDZrrb:
27456 case VMAXPDZrrbk:
27457 case VMAXPDZrrbkz:
27458 case VMAXPDZrrk:
27459 case VMAXPDZrrkz:
27460 case VMAXPDrm:
27461 case VMAXPDrr:
27462 return true;
27463 }
27464 return false;
27465}
27466
27467bool isVPMOVWB(unsigned Opcode) {
27468 switch (Opcode) {
27469 case VPMOVWBZ128mr:
27470 case VPMOVWBZ128mrk:
27471 case VPMOVWBZ128rr:
27472 case VPMOVWBZ128rrk:
27473 case VPMOVWBZ128rrkz:
27474 case VPMOVWBZ256mr:
27475 case VPMOVWBZ256mrk:
27476 case VPMOVWBZ256rr:
27477 case VPMOVWBZ256rrk:
27478 case VPMOVWBZ256rrkz:
27479 case VPMOVWBZmr:
27480 case VPMOVWBZmrk:
27481 case VPMOVWBZrr:
27482 case VPMOVWBZrrk:
27483 case VPMOVWBZrrkz:
27484 return true;
27485 }
27486 return false;
27487}
27488
27489bool isVEXP2PS(unsigned Opcode) {
27490 switch (Opcode) {
27491 case VEXP2PSZm:
27492 case VEXP2PSZmb:
27493 case VEXP2PSZmbk:
27494 case VEXP2PSZmbkz:
27495 case VEXP2PSZmk:
27496 case VEXP2PSZmkz:
27497 case VEXP2PSZr:
27498 case VEXP2PSZrb:
27499 case VEXP2PSZrbk:
27500 case VEXP2PSZrbkz:
27501 case VEXP2PSZrk:
27502 case VEXP2PSZrkz:
27503 return true;
27504 }
27505 return false;
27506}
27507
27508bool isVPGATHERDQ(unsigned Opcode) {
27509 switch (Opcode) {
27510 case VPGATHERDQYrm:
27511 case VPGATHERDQZ128rm:
27512 case VPGATHERDQZ256rm:
27513 case VPGATHERDQZrm:
27514 case VPGATHERDQrm:
27515 return true;
27516 }
27517 return false;
27518}
27519
27520bool isVPSRAVQ(unsigned Opcode) {
27521 switch (Opcode) {
27522 case VPSRAVQZ128rm:
27523 case VPSRAVQZ128rmb:
27524 case VPSRAVQZ128rmbk:
27525 case VPSRAVQZ128rmbkz:
27526 case VPSRAVQZ128rmk:
27527 case VPSRAVQZ128rmkz:
27528 case VPSRAVQZ128rr:
27529 case VPSRAVQZ128rrk:
27530 case VPSRAVQZ128rrkz:
27531 case VPSRAVQZ256rm:
27532 case VPSRAVQZ256rmb:
27533 case VPSRAVQZ256rmbk:
27534 case VPSRAVQZ256rmbkz:
27535 case VPSRAVQZ256rmk:
27536 case VPSRAVQZ256rmkz:
27537 case VPSRAVQZ256rr:
27538 case VPSRAVQZ256rrk:
27539 case VPSRAVQZ256rrkz:
27540 case VPSRAVQZrm:
27541 case VPSRAVQZrmb:
27542 case VPSRAVQZrmbk:
27543 case VPSRAVQZrmbkz:
27544 case VPSRAVQZrmk:
27545 case VPSRAVQZrmkz:
27546 case VPSRAVQZrr:
27547 case VPSRAVQZrrk:
27548 case VPSRAVQZrrkz:
27549 return true;
27550 }
27551 return false;
27552}
27553
27554bool isPCMPISTRI(unsigned Opcode) {
27555 switch (Opcode) {
27556 case PCMPISTRIrmi:
27557 case PCMPISTRIrri:
27558 return true;
27559 }
27560 return false;
27561}
27562
27563bool isVFMSUB231PD(unsigned Opcode) {
27564 switch (Opcode) {
27565 case VFMSUB231PDYm:
27566 case VFMSUB231PDYr:
27567 case VFMSUB231PDZ128m:
27568 case VFMSUB231PDZ128mb:
27569 case VFMSUB231PDZ128mbk:
27570 case VFMSUB231PDZ128mbkz:
27571 case VFMSUB231PDZ128mk:
27572 case VFMSUB231PDZ128mkz:
27573 case VFMSUB231PDZ128r:
27574 case VFMSUB231PDZ128rk:
27575 case VFMSUB231PDZ128rkz:
27576 case VFMSUB231PDZ256m:
27577 case VFMSUB231PDZ256mb:
27578 case VFMSUB231PDZ256mbk:
27579 case VFMSUB231PDZ256mbkz:
27580 case VFMSUB231PDZ256mk:
27581 case VFMSUB231PDZ256mkz:
27582 case VFMSUB231PDZ256r:
27583 case VFMSUB231PDZ256rk:
27584 case VFMSUB231PDZ256rkz:
27585 case VFMSUB231PDZm:
27586 case VFMSUB231PDZmb:
27587 case VFMSUB231PDZmbk:
27588 case VFMSUB231PDZmbkz:
27589 case VFMSUB231PDZmk:
27590 case VFMSUB231PDZmkz:
27591 case VFMSUB231PDZr:
27592 case VFMSUB231PDZrb:
27593 case VFMSUB231PDZrbk:
27594 case VFMSUB231PDZrbkz:
27595 case VFMSUB231PDZrk:
27596 case VFMSUB231PDZrkz:
27597 case VFMSUB231PDm:
27598 case VFMSUB231PDr:
27599 return true;
27600 }
27601 return false;
27602}
27603
27604bool isRDMSR(unsigned Opcode) {
27605 switch (Opcode) {
27606 case RDMSR:
27607 case RDMSRri:
27608 case RDMSRri_EVEX:
27609 return true;
27610 }
27611 return false;
27612}
27613
27614bool isKORTESTD(unsigned Opcode) {
27615 return Opcode == KORTESTDkk;
27616}
27617
27618bool isVPBLENDMW(unsigned Opcode) {
27619 switch (Opcode) {
27620 case VPBLENDMWZ128rm:
27621 case VPBLENDMWZ128rmk:
27622 case VPBLENDMWZ128rmkz:
27623 case VPBLENDMWZ128rr:
27624 case VPBLENDMWZ128rrk:
27625 case VPBLENDMWZ128rrkz:
27626 case VPBLENDMWZ256rm:
27627 case VPBLENDMWZ256rmk:
27628 case VPBLENDMWZ256rmkz:
27629 case VPBLENDMWZ256rr:
27630 case VPBLENDMWZ256rrk:
27631 case VPBLENDMWZ256rrkz:
27632 case VPBLENDMWZrm:
27633 case VPBLENDMWZrmk:
27634 case VPBLENDMWZrmkz:
27635 case VPBLENDMWZrr:
27636 case VPBLENDMWZrrk:
27637 case VPBLENDMWZrrkz:
27638 return true;
27639 }
27640 return false;
27641}
27642
27643bool isPSHUFB(unsigned Opcode) {
27644 switch (Opcode) {
27645 case MMX_PSHUFBrm:
27646 case MMX_PSHUFBrr:
27647 case PSHUFBrm:
27648 case PSHUFBrr:
27649 return true;
27650 }
27651 return false;
27652}
27653
27654bool isVDPBF16PS(unsigned Opcode) {
27655 switch (Opcode) {
27656 case VDPBF16PSZ128m:
27657 case VDPBF16PSZ128mb:
27658 case VDPBF16PSZ128mbk:
27659 case VDPBF16PSZ128mbkz:
27660 case VDPBF16PSZ128mk:
27661 case VDPBF16PSZ128mkz:
27662 case VDPBF16PSZ128r:
27663 case VDPBF16PSZ128rk:
27664 case VDPBF16PSZ128rkz:
27665 case VDPBF16PSZ256m:
27666 case VDPBF16PSZ256mb:
27667 case VDPBF16PSZ256mbk:
27668 case VDPBF16PSZ256mbkz:
27669 case VDPBF16PSZ256mk:
27670 case VDPBF16PSZ256mkz:
27671 case VDPBF16PSZ256r:
27672 case VDPBF16PSZ256rk:
27673 case VDPBF16PSZ256rkz:
27674 case VDPBF16PSZm:
27675 case VDPBF16PSZmb:
27676 case VDPBF16PSZmbk:
27677 case VDPBF16PSZmbkz:
27678 case VDPBF16PSZmk:
27679 case VDPBF16PSZmkz:
27680 case VDPBF16PSZr:
27681 case VDPBF16PSZrk:
27682 case VDPBF16PSZrkz:
27683 return true;
27684 }
27685 return false;
27686}
27687
27688bool isTDPBF16PS(unsigned Opcode) {
27689 return Opcode == TDPBF16PS;
27690}
27691
27692bool isFCMOVE(unsigned Opcode) {
27693 return Opcode == CMOVE_F;
27694}
27695
27696bool isVFMADD231BF16(unsigned Opcode) {
27697 switch (Opcode) {
27698 case VFMADD231BF16Z128m:
27699 case VFMADD231BF16Z128mb:
27700 case VFMADD231BF16Z128mbk:
27701 case VFMADD231BF16Z128mbkz:
27702 case VFMADD231BF16Z128mk:
27703 case VFMADD231BF16Z128mkz:
27704 case VFMADD231BF16Z128r:
27705 case VFMADD231BF16Z128rk:
27706 case VFMADD231BF16Z128rkz:
27707 case VFMADD231BF16Z256m:
27708 case VFMADD231BF16Z256mb:
27709 case VFMADD231BF16Z256mbk:
27710 case VFMADD231BF16Z256mbkz:
27711 case VFMADD231BF16Z256mk:
27712 case VFMADD231BF16Z256mkz:
27713 case VFMADD231BF16Z256r:
27714 case VFMADD231BF16Z256rk:
27715 case VFMADD231BF16Z256rkz:
27716 case VFMADD231BF16Zm:
27717 case VFMADD231BF16Zmb:
27718 case VFMADD231BF16Zmbk:
27719 case VFMADD231BF16Zmbkz:
27720 case VFMADD231BF16Zmk:
27721 case VFMADD231BF16Zmkz:
27722 case VFMADD231BF16Zr:
27723 case VFMADD231BF16Zrk:
27724 case VFMADD231BF16Zrkz:
27725 return true;
27726 }
27727 return false;
27728}
27729
27730bool isCMPSS(unsigned Opcode) {
27731 switch (Opcode) {
27732 case CMPSSrmi_Int:
27733 case CMPSSrri_Int:
27734 return true;
27735 }
27736 return false;
27737}
27738
27739bool isMASKMOVDQU(unsigned Opcode) {
27740 switch (Opcode) {
27741 case MASKMOVDQU:
27742 case MASKMOVDQU64:
27743 return true;
27744 }
27745 return false;
27746}
27747
27748bool isVPDPWUSDS(unsigned Opcode) {
27749 switch (Opcode) {
27750 case VPDPWUSDSYrm:
27751 case VPDPWUSDSYrr:
27752 case VPDPWUSDSZ128rm:
27753 case VPDPWUSDSZ128rmb:
27754 case VPDPWUSDSZ128rmbk:
27755 case VPDPWUSDSZ128rmbkz:
27756 case VPDPWUSDSZ128rmk:
27757 case VPDPWUSDSZ128rmkz:
27758 case VPDPWUSDSZ128rr:
27759 case VPDPWUSDSZ128rrk:
27760 case VPDPWUSDSZ128rrkz:
27761 case VPDPWUSDSZ256rm:
27762 case VPDPWUSDSZ256rmb:
27763 case VPDPWUSDSZ256rmbk:
27764 case VPDPWUSDSZ256rmbkz:
27765 case VPDPWUSDSZ256rmk:
27766 case VPDPWUSDSZ256rmkz:
27767 case VPDPWUSDSZ256rr:
27768 case VPDPWUSDSZ256rrk:
27769 case VPDPWUSDSZ256rrkz:
27770 case VPDPWUSDSZrm:
27771 case VPDPWUSDSZrmb:
27772 case VPDPWUSDSZrmbk:
27773 case VPDPWUSDSZrmbkz:
27774 case VPDPWUSDSZrmk:
27775 case VPDPWUSDSZrmkz:
27776 case VPDPWUSDSZrr:
27777 case VPDPWUSDSZrrk:
27778 case VPDPWUSDSZrrkz:
27779 case VPDPWUSDSrm:
27780 case VPDPWUSDSrr:
27781 return true;
27782 }
27783 return false;
27784}
27785
27786bool isSARX(unsigned Opcode) {
27787 switch (Opcode) {
27788 case SARX32rm:
27789 case SARX32rm_EVEX:
27790 case SARX32rr:
27791 case SARX32rr_EVEX:
27792 case SARX64rm:
27793 case SARX64rm_EVEX:
27794 case SARX64rr:
27795 case SARX64rr_EVEX:
27796 return true;
27797 }
27798 return false;
27799}
27800
27801bool isSGDT(unsigned Opcode) {
27802 return Opcode == SGDT64m;
27803}
27804
27805bool isVFMULCPH(unsigned Opcode) {
27806 switch (Opcode) {
27807 case VFMULCPHZ128rm:
27808 case VFMULCPHZ128rmb:
27809 case VFMULCPHZ128rmbk:
27810 case VFMULCPHZ128rmbkz:
27811 case VFMULCPHZ128rmk:
27812 case VFMULCPHZ128rmkz:
27813 case VFMULCPHZ128rr:
27814 case VFMULCPHZ128rrk:
27815 case VFMULCPHZ128rrkz:
27816 case VFMULCPHZ256rm:
27817 case VFMULCPHZ256rmb:
27818 case VFMULCPHZ256rmbk:
27819 case VFMULCPHZ256rmbkz:
27820 case VFMULCPHZ256rmk:
27821 case VFMULCPHZ256rmkz:
27822 case VFMULCPHZ256rr:
27823 case VFMULCPHZ256rrk:
27824 case VFMULCPHZ256rrkz:
27825 case VFMULCPHZrm:
27826 case VFMULCPHZrmb:
27827 case VFMULCPHZrmbk:
27828 case VFMULCPHZrmbkz:
27829 case VFMULCPHZrmk:
27830 case VFMULCPHZrmkz:
27831 case VFMULCPHZrr:
27832 case VFMULCPHZrrb:
27833 case VFMULCPHZrrbk:
27834 case VFMULCPHZrrbkz:
27835 case VFMULCPHZrrk:
27836 case VFMULCPHZrrkz:
27837 return true;
27838 }
27839 return false;
27840}
27841
27842bool isURDMSR(unsigned Opcode) {
27843 switch (Opcode) {
27844 case URDMSRri:
27845 case URDMSRri_EVEX:
27846 case URDMSRrr:
27847 case URDMSRrr_EVEX:
27848 return true;
27849 }
27850 return false;
27851}
27852
27853bool isKUNPCKWD(unsigned Opcode) {
27854 return Opcode == KUNPCKWDkk;
27855}
27856
27857bool isVSCALEFBF16(unsigned Opcode) {
27858 switch (Opcode) {
27859 case VSCALEFBF16Z128rm:
27860 case VSCALEFBF16Z128rmb:
27861 case VSCALEFBF16Z128rmbk:
27862 case VSCALEFBF16Z128rmbkz:
27863 case VSCALEFBF16Z128rmk:
27864 case VSCALEFBF16Z128rmkz:
27865 case VSCALEFBF16Z128rr:
27866 case VSCALEFBF16Z128rrk:
27867 case VSCALEFBF16Z128rrkz:
27868 case VSCALEFBF16Z256rm:
27869 case VSCALEFBF16Z256rmb:
27870 case VSCALEFBF16Z256rmbk:
27871 case VSCALEFBF16Z256rmbkz:
27872 case VSCALEFBF16Z256rmk:
27873 case VSCALEFBF16Z256rmkz:
27874 case VSCALEFBF16Z256rr:
27875 case VSCALEFBF16Z256rrk:
27876 case VSCALEFBF16Z256rrkz:
27877 case VSCALEFBF16Zrm:
27878 case VSCALEFBF16Zrmb:
27879 case VSCALEFBF16Zrmbk:
27880 case VSCALEFBF16Zrmbkz:
27881 case VSCALEFBF16Zrmk:
27882 case VSCALEFBF16Zrmkz:
27883 case VSCALEFBF16Zrr:
27884 case VSCALEFBF16Zrrk:
27885 case VSCALEFBF16Zrrkz:
27886 return true;
27887 }
27888 return false;
27889}
27890
27891bool isCVTPS2PD(unsigned Opcode) {
27892 switch (Opcode) {
27893 case CVTPS2PDrm:
27894 case CVTPS2PDrr:
27895 return true;
27896 }
27897 return false;
27898}
27899
27900bool isFBSTP(unsigned Opcode) {
27901 return Opcode == FBSTPm;
27902}
27903
27904bool isPSUBQ(unsigned Opcode) {
27905 switch (Opcode) {
27906 case MMX_PSUBQrm:
27907 case MMX_PSUBQrr:
27908 case PSUBQrm:
27909 case PSUBQrr:
27910 return true;
27911 }
27912 return false;
27913}
27914
27915bool isFXSAVE64(unsigned Opcode) {
27916 return Opcode == FXSAVE64;
27917}
27918
27919bool isKMOVW(unsigned Opcode) {
27920 switch (Opcode) {
27921 case KMOVWkk:
27922 case KMOVWkk_EVEX:
27923 case KMOVWkm:
27924 case KMOVWkm_EVEX:
27925 case KMOVWkr:
27926 case KMOVWkr_EVEX:
27927 case KMOVWmk:
27928 case KMOVWmk_EVEX:
27929 case KMOVWrk:
27930 case KMOVWrk_EVEX:
27931 return true;
27932 }
27933 return false;
27934}
27935
27936bool isBTS(unsigned Opcode) {
27937 switch (Opcode) {
27938 case BTS16mi8:
27939 case BTS16mr:
27940 case BTS16ri8:
27941 case BTS16rr:
27942 case BTS32mi8:
27943 case BTS32mr:
27944 case BTS32ri8:
27945 case BTS32rr:
27946 case BTS64mi8:
27947 case BTS64mr:
27948 case BTS64ri8:
27949 case BTS64rr:
27950 return true;
27951 }
27952 return false;
27953}
27954
27955bool isVPHADDBQ(unsigned Opcode) {
27956 switch (Opcode) {
27957 case VPHADDBQrm:
27958 case VPHADDBQrr:
27959 return true;
27960 }
27961 return false;
27962}
27963
27964bool isFRSTOR(unsigned Opcode) {
27965 return Opcode == FRSTORm;
27966}
27967
27968bool isVFMSUB132PD(unsigned Opcode) {
27969 switch (Opcode) {
27970 case VFMSUB132PDYm:
27971 case VFMSUB132PDYr:
27972 case VFMSUB132PDZ128m:
27973 case VFMSUB132PDZ128mb:
27974 case VFMSUB132PDZ128mbk:
27975 case VFMSUB132PDZ128mbkz:
27976 case VFMSUB132PDZ128mk:
27977 case VFMSUB132PDZ128mkz:
27978 case VFMSUB132PDZ128r:
27979 case VFMSUB132PDZ128rk:
27980 case VFMSUB132PDZ128rkz:
27981 case VFMSUB132PDZ256m:
27982 case VFMSUB132PDZ256mb:
27983 case VFMSUB132PDZ256mbk:
27984 case VFMSUB132PDZ256mbkz:
27985 case VFMSUB132PDZ256mk:
27986 case VFMSUB132PDZ256mkz:
27987 case VFMSUB132PDZ256r:
27988 case VFMSUB132PDZ256rk:
27989 case VFMSUB132PDZ256rkz:
27990 case VFMSUB132PDZm:
27991 case VFMSUB132PDZmb:
27992 case VFMSUB132PDZmbk:
27993 case VFMSUB132PDZmbkz:
27994 case VFMSUB132PDZmk:
27995 case VFMSUB132PDZmkz:
27996 case VFMSUB132PDZr:
27997 case VFMSUB132PDZrb:
27998 case VFMSUB132PDZrbk:
27999 case VFMSUB132PDZrbkz:
28000 case VFMSUB132PDZrk:
28001 case VFMSUB132PDZrkz:
28002 case VFMSUB132PDm:
28003 case VFMSUB132PDr:
28004 return true;
28005 }
28006 return false;
28007}
28008
28009bool isPMULLD(unsigned Opcode) {
28010 switch (Opcode) {
28011 case PMULLDrm:
28012 case PMULLDrr:
28013 return true;
28014 }
28015 return false;
28016}
28017
28018bool isSHA1MSG2(unsigned Opcode) {
28019 switch (Opcode) {
28020 case SHA1MSG2rm:
28021 case SHA1MSG2rr:
28022 return true;
28023 }
28024 return false;
28025}
28026
28027bool isJECXZ(unsigned Opcode) {
28028 return Opcode == JECXZ;
28029}
28030
28031bool isVCVTUDQ2PS(unsigned Opcode) {
28032 switch (Opcode) {
28033 case VCVTUDQ2PSZ128rm:
28034 case VCVTUDQ2PSZ128rmb:
28035 case VCVTUDQ2PSZ128rmbk:
28036 case VCVTUDQ2PSZ128rmbkz:
28037 case VCVTUDQ2PSZ128rmk:
28038 case VCVTUDQ2PSZ128rmkz:
28039 case VCVTUDQ2PSZ128rr:
28040 case VCVTUDQ2PSZ128rrk:
28041 case VCVTUDQ2PSZ128rrkz:
28042 case VCVTUDQ2PSZ256rm:
28043 case VCVTUDQ2PSZ256rmb:
28044 case VCVTUDQ2PSZ256rmbk:
28045 case VCVTUDQ2PSZ256rmbkz:
28046 case VCVTUDQ2PSZ256rmk:
28047 case VCVTUDQ2PSZ256rmkz:
28048 case VCVTUDQ2PSZ256rr:
28049 case VCVTUDQ2PSZ256rrk:
28050 case VCVTUDQ2PSZ256rrkz:
28051 case VCVTUDQ2PSZrm:
28052 case VCVTUDQ2PSZrmb:
28053 case VCVTUDQ2PSZrmbk:
28054 case VCVTUDQ2PSZrmbkz:
28055 case VCVTUDQ2PSZrmk:
28056 case VCVTUDQ2PSZrmkz:
28057 case VCVTUDQ2PSZrr:
28058 case VCVTUDQ2PSZrrb:
28059 case VCVTUDQ2PSZrrbk:
28060 case VCVTUDQ2PSZrrbkz:
28061 case VCVTUDQ2PSZrrk:
28062 case VCVTUDQ2PSZrrkz:
28063 return true;
28064 }
28065 return false;
28066}
28067
28068bool isAESENC(unsigned Opcode) {
28069 switch (Opcode) {
28070 case AESENCrm:
28071 case AESENCrr:
28072 return true;
28073 }
28074 return false;
28075}
28076
28077bool isVMINMAXPS(unsigned Opcode) {
28078 switch (Opcode) {
28079 case VMINMAXPSZ128rmbi:
28080 case VMINMAXPSZ128rmbik:
28081 case VMINMAXPSZ128rmbikz:
28082 case VMINMAXPSZ128rmi:
28083 case VMINMAXPSZ128rmik:
28084 case VMINMAXPSZ128rmikz:
28085 case VMINMAXPSZ128rri:
28086 case VMINMAXPSZ128rrik:
28087 case VMINMAXPSZ128rrikz:
28088 case VMINMAXPSZ256rmbi:
28089 case VMINMAXPSZ256rmbik:
28090 case VMINMAXPSZ256rmbikz:
28091 case VMINMAXPSZ256rmi:
28092 case VMINMAXPSZ256rmik:
28093 case VMINMAXPSZ256rmikz:
28094 case VMINMAXPSZ256rri:
28095 case VMINMAXPSZ256rrik:
28096 case VMINMAXPSZ256rrikz:
28097 case VMINMAXPSZrmbi:
28098 case VMINMAXPSZrmbik:
28099 case VMINMAXPSZrmbikz:
28100 case VMINMAXPSZrmi:
28101 case VMINMAXPSZrmik:
28102 case VMINMAXPSZrmikz:
28103 case VMINMAXPSZrri:
28104 case VMINMAXPSZrrib:
28105 case VMINMAXPSZrribk:
28106 case VMINMAXPSZrribkz:
28107 case VMINMAXPSZrrik:
28108 case VMINMAXPSZrrikz:
28109 return true;
28110 }
28111 return false;
28112}
28113
28114bool isPSIGNW(unsigned Opcode) {
28115 switch (Opcode) {
28116 case MMX_PSIGNWrm:
28117 case MMX_PSIGNWrr:
28118 case PSIGNWrm:
28119 case PSIGNWrr:
28120 return true;
28121 }
28122 return false;
28123}
28124
28125bool isUNPCKLPD(unsigned Opcode) {
28126 switch (Opcode) {
28127 case UNPCKLPDrm:
28128 case UNPCKLPDrr:
28129 return true;
28130 }
28131 return false;
28132}
28133
28134bool isPUSHP(unsigned Opcode) {
28135 return Opcode == PUSHP64r;
28136}
28137
28138bool isBLSI(unsigned Opcode) {
28139 switch (Opcode) {
28140 case BLSI32rm:
28141 case BLSI32rm_EVEX:
28142 case BLSI32rm_NF:
28143 case BLSI32rr:
28144 case BLSI32rr_EVEX:
28145 case BLSI32rr_NF:
28146 case BLSI64rm:
28147 case BLSI64rm_EVEX:
28148 case BLSI64rm_NF:
28149 case BLSI64rr:
28150 case BLSI64rr_EVEX:
28151 case BLSI64rr_NF:
28152 return true;
28153 }
28154 return false;
28155}
28156
28157bool isVPTESTNMB(unsigned Opcode) {
28158 switch (Opcode) {
28159 case VPTESTNMBZ128rm:
28160 case VPTESTNMBZ128rmk:
28161 case VPTESTNMBZ128rr:
28162 case VPTESTNMBZ128rrk:
28163 case VPTESTNMBZ256rm:
28164 case VPTESTNMBZ256rmk:
28165 case VPTESTNMBZ256rr:
28166 case VPTESTNMBZ256rrk:
28167 case VPTESTNMBZrm:
28168 case VPTESTNMBZrmk:
28169 case VPTESTNMBZrr:
28170 case VPTESTNMBZrrk:
28171 return true;
28172 }
28173 return false;
28174}
28175
28176bool isWRUSSQ(unsigned Opcode) {
28177 switch (Opcode) {
28178 case WRUSSQ:
28179 case WRUSSQ_EVEX:
28180 return true;
28181 }
28182 return false;
28183}
28184
28185bool isVGF2P8MULB(unsigned Opcode) {
28186 switch (Opcode) {
28187 case VGF2P8MULBYrm:
28188 case VGF2P8MULBYrr:
28189 case VGF2P8MULBZ128rm:
28190 case VGF2P8MULBZ128rmk:
28191 case VGF2P8MULBZ128rmkz:
28192 case VGF2P8MULBZ128rr:
28193 case VGF2P8MULBZ128rrk:
28194 case VGF2P8MULBZ128rrkz:
28195 case VGF2P8MULBZ256rm:
28196 case VGF2P8MULBZ256rmk:
28197 case VGF2P8MULBZ256rmkz:
28198 case VGF2P8MULBZ256rr:
28199 case VGF2P8MULBZ256rrk:
28200 case VGF2P8MULBZ256rrkz:
28201 case VGF2P8MULBZrm:
28202 case VGF2P8MULBZrmk:
28203 case VGF2P8MULBZrmkz:
28204 case VGF2P8MULBZrr:
28205 case VGF2P8MULBZrrk:
28206 case VGF2P8MULBZrrkz:
28207 case VGF2P8MULBrm:
28208 case VGF2P8MULBrr:
28209 return true;
28210 }
28211 return false;
28212}
28213
28214bool isVPUNPCKLBW(unsigned Opcode) {
28215 switch (Opcode) {
28216 case VPUNPCKLBWYrm:
28217 case VPUNPCKLBWYrr:
28218 case VPUNPCKLBWZ128rm:
28219 case VPUNPCKLBWZ128rmk:
28220 case VPUNPCKLBWZ128rmkz:
28221 case VPUNPCKLBWZ128rr:
28222 case VPUNPCKLBWZ128rrk:
28223 case VPUNPCKLBWZ128rrkz:
28224 case VPUNPCKLBWZ256rm:
28225 case VPUNPCKLBWZ256rmk:
28226 case VPUNPCKLBWZ256rmkz:
28227 case VPUNPCKLBWZ256rr:
28228 case VPUNPCKLBWZ256rrk:
28229 case VPUNPCKLBWZ256rrkz:
28230 case VPUNPCKLBWZrm:
28231 case VPUNPCKLBWZrmk:
28232 case VPUNPCKLBWZrmkz:
28233 case VPUNPCKLBWZrr:
28234 case VPUNPCKLBWZrrk:
28235 case VPUNPCKLBWZrrkz:
28236 case VPUNPCKLBWrm:
28237 case VPUNPCKLBWrr:
28238 return true;
28239 }
28240 return false;
28241}
28242
28243bool isVRANGESD(unsigned Opcode) {
28244 switch (Opcode) {
28245 case VRANGESDZrmi:
28246 case VRANGESDZrmik:
28247 case VRANGESDZrmikz:
28248 case VRANGESDZrri:
28249 case VRANGESDZrrib:
28250 case VRANGESDZrribk:
28251 case VRANGESDZrribkz:
28252 case VRANGESDZrrik:
28253 case VRANGESDZrrikz:
28254 return true;
28255 }
28256 return false;
28257}
28258
28259bool isCLD(unsigned Opcode) {
28260 return Opcode == CLD;
28261}
28262
28263bool isVSCALEFPD(unsigned Opcode) {
28264 switch (Opcode) {
28265 case VSCALEFPDZ128rm:
28266 case VSCALEFPDZ128rmb:
28267 case VSCALEFPDZ128rmbk:
28268 case VSCALEFPDZ128rmbkz:
28269 case VSCALEFPDZ128rmk:
28270 case VSCALEFPDZ128rmkz:
28271 case VSCALEFPDZ128rr:
28272 case VSCALEFPDZ128rrk:
28273 case VSCALEFPDZ128rrkz:
28274 case VSCALEFPDZ256rm:
28275 case VSCALEFPDZ256rmb:
28276 case VSCALEFPDZ256rmbk:
28277 case VSCALEFPDZ256rmbkz:
28278 case VSCALEFPDZ256rmk:
28279 case VSCALEFPDZ256rmkz:
28280 case VSCALEFPDZ256rr:
28281 case VSCALEFPDZ256rrk:
28282 case VSCALEFPDZ256rrkz:
28283 case VSCALEFPDZrm:
28284 case VSCALEFPDZrmb:
28285 case VSCALEFPDZrmbk:
28286 case VSCALEFPDZrmbkz:
28287 case VSCALEFPDZrmk:
28288 case VSCALEFPDZrmkz:
28289 case VSCALEFPDZrr:
28290 case VSCALEFPDZrrb:
28291 case VSCALEFPDZrrbk:
28292 case VSCALEFPDZrrbkz:
28293 case VSCALEFPDZrrk:
28294 case VSCALEFPDZrrkz:
28295 return true;
28296 }
28297 return false;
28298}
28299
28300bool isVCOMXSS(unsigned Opcode) {
28301 switch (Opcode) {
28302 case VCOMXSSZrm_Int:
28303 case VCOMXSSZrr_Int:
28304 case VCOMXSSZrrb_Int:
28305 return true;
28306 }
28307 return false;
28308}
28309
28310bool isVPERMQ(unsigned Opcode) {
28311 switch (Opcode) {
28312 case VPERMQYmi:
28313 case VPERMQYri:
28314 case VPERMQZ256mbi:
28315 case VPERMQZ256mbik:
28316 case VPERMQZ256mbikz:
28317 case VPERMQZ256mi:
28318 case VPERMQZ256mik:
28319 case VPERMQZ256mikz:
28320 case VPERMQZ256ri:
28321 case VPERMQZ256rik:
28322 case VPERMQZ256rikz:
28323 case VPERMQZ256rm:
28324 case VPERMQZ256rmb:
28325 case VPERMQZ256rmbk:
28326 case VPERMQZ256rmbkz:
28327 case VPERMQZ256rmk:
28328 case VPERMQZ256rmkz:
28329 case VPERMQZ256rr:
28330 case VPERMQZ256rrk:
28331 case VPERMQZ256rrkz:
28332 case VPERMQZmbi:
28333 case VPERMQZmbik:
28334 case VPERMQZmbikz:
28335 case VPERMQZmi:
28336 case VPERMQZmik:
28337 case VPERMQZmikz:
28338 case VPERMQZri:
28339 case VPERMQZrik:
28340 case VPERMQZrikz:
28341 case VPERMQZrm:
28342 case VPERMQZrmb:
28343 case VPERMQZrmbk:
28344 case VPERMQZrmbkz:
28345 case VPERMQZrmk:
28346 case VPERMQZrmkz:
28347 case VPERMQZrr:
28348 case VPERMQZrrk:
28349 case VPERMQZrrkz:
28350 return true;
28351 }
28352 return false;
28353}
28354
28355bool isVPSHLDVW(unsigned Opcode) {
28356 switch (Opcode) {
28357 case VPSHLDVWZ128m:
28358 case VPSHLDVWZ128mk:
28359 case VPSHLDVWZ128mkz:
28360 case VPSHLDVWZ128r:
28361 case VPSHLDVWZ128rk:
28362 case VPSHLDVWZ128rkz:
28363 case VPSHLDVWZ256m:
28364 case VPSHLDVWZ256mk:
28365 case VPSHLDVWZ256mkz:
28366 case VPSHLDVWZ256r:
28367 case VPSHLDVWZ256rk:
28368 case VPSHLDVWZ256rkz:
28369 case VPSHLDVWZm:
28370 case VPSHLDVWZmk:
28371 case VPSHLDVWZmkz:
28372 case VPSHLDVWZr:
28373 case VPSHLDVWZrk:
28374 case VPSHLDVWZrkz:
28375 return true;
28376 }
28377 return false;
28378}
28379
28380bool isROR(unsigned Opcode) {
28381 switch (Opcode) {
28382 case ROR16m1:
28383 case ROR16m1_EVEX:
28384 case ROR16m1_ND:
28385 case ROR16m1_NF:
28386 case ROR16m1_NF_ND:
28387 case ROR16mCL:
28388 case ROR16mCL_EVEX:
28389 case ROR16mCL_ND:
28390 case ROR16mCL_NF:
28391 case ROR16mCL_NF_ND:
28392 case ROR16mi:
28393 case ROR16mi_EVEX:
28394 case ROR16mi_ND:
28395 case ROR16mi_NF:
28396 case ROR16mi_NF_ND:
28397 case ROR16r1:
28398 case ROR16r1_EVEX:
28399 case ROR16r1_ND:
28400 case ROR16r1_NF:
28401 case ROR16r1_NF_ND:
28402 case ROR16rCL:
28403 case ROR16rCL_EVEX:
28404 case ROR16rCL_ND:
28405 case ROR16rCL_NF:
28406 case ROR16rCL_NF_ND:
28407 case ROR16ri:
28408 case ROR16ri_EVEX:
28409 case ROR16ri_ND:
28410 case ROR16ri_NF:
28411 case ROR16ri_NF_ND:
28412 case ROR32m1:
28413 case ROR32m1_EVEX:
28414 case ROR32m1_ND:
28415 case ROR32m1_NF:
28416 case ROR32m1_NF_ND:
28417 case ROR32mCL:
28418 case ROR32mCL_EVEX:
28419 case ROR32mCL_ND:
28420 case ROR32mCL_NF:
28421 case ROR32mCL_NF_ND:
28422 case ROR32mi:
28423 case ROR32mi_EVEX:
28424 case ROR32mi_ND:
28425 case ROR32mi_NF:
28426 case ROR32mi_NF_ND:
28427 case ROR32r1:
28428 case ROR32r1_EVEX:
28429 case ROR32r1_ND:
28430 case ROR32r1_NF:
28431 case ROR32r1_NF_ND:
28432 case ROR32rCL:
28433 case ROR32rCL_EVEX:
28434 case ROR32rCL_ND:
28435 case ROR32rCL_NF:
28436 case ROR32rCL_NF_ND:
28437 case ROR32ri:
28438 case ROR32ri_EVEX:
28439 case ROR32ri_ND:
28440 case ROR32ri_NF:
28441 case ROR32ri_NF_ND:
28442 case ROR64m1:
28443 case ROR64m1_EVEX:
28444 case ROR64m1_ND:
28445 case ROR64m1_NF:
28446 case ROR64m1_NF_ND:
28447 case ROR64mCL:
28448 case ROR64mCL_EVEX:
28449 case ROR64mCL_ND:
28450 case ROR64mCL_NF:
28451 case ROR64mCL_NF_ND:
28452 case ROR64mi:
28453 case ROR64mi_EVEX:
28454 case ROR64mi_ND:
28455 case ROR64mi_NF:
28456 case ROR64mi_NF_ND:
28457 case ROR64r1:
28458 case ROR64r1_EVEX:
28459 case ROR64r1_ND:
28460 case ROR64r1_NF:
28461 case ROR64r1_NF_ND:
28462 case ROR64rCL:
28463 case ROR64rCL_EVEX:
28464 case ROR64rCL_ND:
28465 case ROR64rCL_NF:
28466 case ROR64rCL_NF_ND:
28467 case ROR64ri:
28468 case ROR64ri_EVEX:
28469 case ROR64ri_ND:
28470 case ROR64ri_NF:
28471 case ROR64ri_NF_ND:
28472 case ROR8m1:
28473 case ROR8m1_EVEX:
28474 case ROR8m1_ND:
28475 case ROR8m1_NF:
28476 case ROR8m1_NF_ND:
28477 case ROR8mCL:
28478 case ROR8mCL_EVEX:
28479 case ROR8mCL_ND:
28480 case ROR8mCL_NF:
28481 case ROR8mCL_NF_ND:
28482 case ROR8mi:
28483 case ROR8mi_EVEX:
28484 case ROR8mi_ND:
28485 case ROR8mi_NF:
28486 case ROR8mi_NF_ND:
28487 case ROR8r1:
28488 case ROR8r1_EVEX:
28489 case ROR8r1_ND:
28490 case ROR8r1_NF:
28491 case ROR8r1_NF_ND:
28492 case ROR8rCL:
28493 case ROR8rCL_EVEX:
28494 case ROR8rCL_ND:
28495 case ROR8rCL_NF:
28496 case ROR8rCL_NF_ND:
28497 case ROR8ri:
28498 case ROR8ri_EVEX:
28499 case ROR8ri_ND:
28500 case ROR8ri_NF:
28501 case ROR8ri_NF_ND:
28502 return true;
28503 }
28504 return false;
28505}
28506
28507bool isVFMADDSUB132PH(unsigned Opcode) {
28508 switch (Opcode) {
28509 case VFMADDSUB132PHZ128m:
28510 case VFMADDSUB132PHZ128mb:
28511 case VFMADDSUB132PHZ128mbk:
28512 case VFMADDSUB132PHZ128mbkz:
28513 case VFMADDSUB132PHZ128mk:
28514 case VFMADDSUB132PHZ128mkz:
28515 case VFMADDSUB132PHZ128r:
28516 case VFMADDSUB132PHZ128rk:
28517 case VFMADDSUB132PHZ128rkz:
28518 case VFMADDSUB132PHZ256m:
28519 case VFMADDSUB132PHZ256mb:
28520 case VFMADDSUB132PHZ256mbk:
28521 case VFMADDSUB132PHZ256mbkz:
28522 case VFMADDSUB132PHZ256mk:
28523 case VFMADDSUB132PHZ256mkz:
28524 case VFMADDSUB132PHZ256r:
28525 case VFMADDSUB132PHZ256rk:
28526 case VFMADDSUB132PHZ256rkz:
28527 case VFMADDSUB132PHZm:
28528 case VFMADDSUB132PHZmb:
28529 case VFMADDSUB132PHZmbk:
28530 case VFMADDSUB132PHZmbkz:
28531 case VFMADDSUB132PHZmk:
28532 case VFMADDSUB132PHZmkz:
28533 case VFMADDSUB132PHZr:
28534 case VFMADDSUB132PHZrb:
28535 case VFMADDSUB132PHZrbk:
28536 case VFMADDSUB132PHZrbkz:
28537 case VFMADDSUB132PHZrk:
28538 case VFMADDSUB132PHZrkz:
28539 return true;
28540 }
28541 return false;
28542}
28543
28544bool isDEC(unsigned Opcode) {
28545 switch (Opcode) {
28546 case DEC16m:
28547 case DEC16m_EVEX:
28548 case DEC16m_ND:
28549 case DEC16m_NF:
28550 case DEC16m_NF_ND:
28551 case DEC16r:
28552 case DEC16r_EVEX:
28553 case DEC16r_ND:
28554 case DEC16r_NF:
28555 case DEC16r_NF_ND:
28556 case DEC16r_alt:
28557 case DEC32m:
28558 case DEC32m_EVEX:
28559 case DEC32m_ND:
28560 case DEC32m_NF:
28561 case DEC32m_NF_ND:
28562 case DEC32r:
28563 case DEC32r_EVEX:
28564 case DEC32r_ND:
28565 case DEC32r_NF:
28566 case DEC32r_NF_ND:
28567 case DEC32r_alt:
28568 case DEC64m:
28569 case DEC64m_EVEX:
28570 case DEC64m_ND:
28571 case DEC64m_NF:
28572 case DEC64m_NF_ND:
28573 case DEC64r:
28574 case DEC64r_EVEX:
28575 case DEC64r_ND:
28576 case DEC64r_NF:
28577 case DEC64r_NF_ND:
28578 case DEC8m:
28579 case DEC8m_EVEX:
28580 case DEC8m_ND:
28581 case DEC8m_NF:
28582 case DEC8m_NF_ND:
28583 case DEC8r:
28584 case DEC8r_EVEX:
28585 case DEC8r_ND:
28586 case DEC8r_NF:
28587 case DEC8r_NF_ND:
28588 return true;
28589 }
28590 return false;
28591}
28592
28593bool isVGETEXPSH(unsigned Opcode) {
28594 switch (Opcode) {
28595 case VGETEXPSHZm:
28596 case VGETEXPSHZmk:
28597 case VGETEXPSHZmkz:
28598 case VGETEXPSHZr:
28599 case VGETEXPSHZrb:
28600 case VGETEXPSHZrbk:
28601 case VGETEXPSHZrbkz:
28602 case VGETEXPSHZrk:
28603 case VGETEXPSHZrkz:
28604 return true;
28605 }
28606 return false;
28607}
28608
28609bool isAESDEC(unsigned Opcode) {
28610 switch (Opcode) {
28611 case AESDECrm:
28612 case AESDECrr:
28613 return true;
28614 }
28615 return false;
28616}
28617
28618bool isKORD(unsigned Opcode) {
28619 return Opcode == KORDkk;
28620}
28621
28622bool isVPMULHW(unsigned Opcode) {
28623 switch (Opcode) {
28624 case VPMULHWYrm:
28625 case VPMULHWYrr:
28626 case VPMULHWZ128rm:
28627 case VPMULHWZ128rmk:
28628 case VPMULHWZ128rmkz:
28629 case VPMULHWZ128rr:
28630 case VPMULHWZ128rrk:
28631 case VPMULHWZ128rrkz:
28632 case VPMULHWZ256rm:
28633 case VPMULHWZ256rmk:
28634 case VPMULHWZ256rmkz:
28635 case VPMULHWZ256rr:
28636 case VPMULHWZ256rrk:
28637 case VPMULHWZ256rrkz:
28638 case VPMULHWZrm:
28639 case VPMULHWZrmk:
28640 case VPMULHWZrmkz:
28641 case VPMULHWZrr:
28642 case VPMULHWZrrk:
28643 case VPMULHWZrrkz:
28644 case VPMULHWrm:
28645 case VPMULHWrr:
28646 return true;
28647 }
28648 return false;
28649}
28650
28651bool isTILELOADDT1(unsigned Opcode) {
28652 switch (Opcode) {
28653 case TILELOADDT1:
28654 case TILELOADDT1_EVEX:
28655 return true;
28656 }
28657 return false;
28658}
28659
28660bool isVMASKMOVPS(unsigned Opcode) {
28661 switch (Opcode) {
28662 case VMASKMOVPSYmr:
28663 case VMASKMOVPSYrm:
28664 case VMASKMOVPSmr:
28665 case VMASKMOVPSrm:
28666 return true;
28667 }
28668 return false;
28669}
28670
28671bool isPMOVZXDQ(unsigned Opcode) {
28672 switch (Opcode) {
28673 case PMOVZXDQrm:
28674 case PMOVZXDQrr:
28675 return true;
28676 }
28677 return false;
28678}
28679
28680bool isVCVTPS2PH(unsigned Opcode) {
28681 switch (Opcode) {
28682 case VCVTPS2PHYmr:
28683 case VCVTPS2PHYrr:
28684 case VCVTPS2PHZ128mr:
28685 case VCVTPS2PHZ128mrk:
28686 case VCVTPS2PHZ128rr:
28687 case VCVTPS2PHZ128rrk:
28688 case VCVTPS2PHZ128rrkz:
28689 case VCVTPS2PHZ256mr:
28690 case VCVTPS2PHZ256mrk:
28691 case VCVTPS2PHZ256rr:
28692 case VCVTPS2PHZ256rrk:
28693 case VCVTPS2PHZ256rrkz:
28694 case VCVTPS2PHZmr:
28695 case VCVTPS2PHZmrk:
28696 case VCVTPS2PHZrr:
28697 case VCVTPS2PHZrrb:
28698 case VCVTPS2PHZrrbk:
28699 case VCVTPS2PHZrrbkz:
28700 case VCVTPS2PHZrrk:
28701 case VCVTPS2PHZrrkz:
28702 case VCVTPS2PHmr:
28703 case VCVTPS2PHrr:
28704 return true;
28705 }
28706 return false;
28707}
28708
28709bool isCVTDQ2PD(unsigned Opcode) {
28710 switch (Opcode) {
28711 case CVTDQ2PDrm:
28712 case CVTDQ2PDrr:
28713 return true;
28714 }
28715 return false;
28716}
28717
28718bool isVCVTSD2SS(unsigned Opcode) {
28719 switch (Opcode) {
28720 case VCVTSD2SSZrm_Int:
28721 case VCVTSD2SSZrmk_Int:
28722 case VCVTSD2SSZrmkz_Int:
28723 case VCVTSD2SSZrr_Int:
28724 case VCVTSD2SSZrrb_Int:
28725 case VCVTSD2SSZrrbk_Int:
28726 case VCVTSD2SSZrrbkz_Int:
28727 case VCVTSD2SSZrrk_Int:
28728 case VCVTSD2SSZrrkz_Int:
28729 case VCVTSD2SSrm_Int:
28730 case VCVTSD2SSrr_Int:
28731 return true;
28732 }
28733 return false;
28734}
28735
28736bool isVFMSUB213PH(unsigned Opcode) {
28737 switch (Opcode) {
28738 case VFMSUB213PHZ128m:
28739 case VFMSUB213PHZ128mb:
28740 case VFMSUB213PHZ128mbk:
28741 case VFMSUB213PHZ128mbkz:
28742 case VFMSUB213PHZ128mk:
28743 case VFMSUB213PHZ128mkz:
28744 case VFMSUB213PHZ128r:
28745 case VFMSUB213PHZ128rk:
28746 case VFMSUB213PHZ128rkz:
28747 case VFMSUB213PHZ256m:
28748 case VFMSUB213PHZ256mb:
28749 case VFMSUB213PHZ256mbk:
28750 case VFMSUB213PHZ256mbkz:
28751 case VFMSUB213PHZ256mk:
28752 case VFMSUB213PHZ256mkz:
28753 case VFMSUB213PHZ256r:
28754 case VFMSUB213PHZ256rk:
28755 case VFMSUB213PHZ256rkz:
28756 case VFMSUB213PHZm:
28757 case VFMSUB213PHZmb:
28758 case VFMSUB213PHZmbk:
28759 case VFMSUB213PHZmbkz:
28760 case VFMSUB213PHZmk:
28761 case VFMSUB213PHZmkz:
28762 case VFMSUB213PHZr:
28763 case VFMSUB213PHZrb:
28764 case VFMSUB213PHZrbk:
28765 case VFMSUB213PHZrbkz:
28766 case VFMSUB213PHZrk:
28767 case VFMSUB213PHZrkz:
28768 return true;
28769 }
28770 return false;
28771}
28772
28773bool isVPROTB(unsigned Opcode) {
28774 switch (Opcode) {
28775 case VPROTBmi:
28776 case VPROTBmr:
28777 case VPROTBri:
28778 case VPROTBrm:
28779 case VPROTBrr:
28780 case VPROTBrr_REV:
28781 return true;
28782 }
28783 return false;
28784}
28785
28786bool isPINSRD(unsigned Opcode) {
28787 switch (Opcode) {
28788 case PINSRDrmi:
28789 case PINSRDrri:
28790 return true;
28791 }
28792 return false;
28793}
28794
28795bool isVMXON(unsigned Opcode) {
28796 return Opcode == VMXON;
28797}
28798
28799bool isVFCMULCSH(unsigned Opcode) {
28800 switch (Opcode) {
28801 case VFCMULCSHZrm:
28802 case VFCMULCSHZrmk:
28803 case VFCMULCSHZrmkz:
28804 case VFCMULCSHZrr:
28805 case VFCMULCSHZrrb:
28806 case VFCMULCSHZrrbk:
28807 case VFCMULCSHZrrbkz:
28808 case VFCMULCSHZrrk:
28809 case VFCMULCSHZrrkz:
28810 return true;
28811 }
28812 return false;
28813}
28814
28815bool isVFMULCSH(unsigned Opcode) {
28816 switch (Opcode) {
28817 case VFMULCSHZrm:
28818 case VFMULCSHZrmk:
28819 case VFMULCSHZrmkz:
28820 case VFMULCSHZrr:
28821 case VFMULCSHZrrb:
28822 case VFMULCSHZrrbk:
28823 case VFMULCSHZrrbkz:
28824 case VFMULCSHZrrk:
28825 case VFMULCSHZrrkz:
28826 return true;
28827 }
28828 return false;
28829}
28830
28831bool isVRANGEPD(unsigned Opcode) {
28832 switch (Opcode) {
28833 case VRANGEPDZ128rmbi:
28834 case VRANGEPDZ128rmbik:
28835 case VRANGEPDZ128rmbikz:
28836 case VRANGEPDZ128rmi:
28837 case VRANGEPDZ128rmik:
28838 case VRANGEPDZ128rmikz:
28839 case VRANGEPDZ128rri:
28840 case VRANGEPDZ128rrik:
28841 case VRANGEPDZ128rrikz:
28842 case VRANGEPDZ256rmbi:
28843 case VRANGEPDZ256rmbik:
28844 case VRANGEPDZ256rmbikz:
28845 case VRANGEPDZ256rmi:
28846 case VRANGEPDZ256rmik:
28847 case VRANGEPDZ256rmikz:
28848 case VRANGEPDZ256rri:
28849 case VRANGEPDZ256rrik:
28850 case VRANGEPDZ256rrikz:
28851 case VRANGEPDZrmbi:
28852 case VRANGEPDZrmbik:
28853 case VRANGEPDZrmbikz:
28854 case VRANGEPDZrmi:
28855 case VRANGEPDZrmik:
28856 case VRANGEPDZrmikz:
28857 case VRANGEPDZrri:
28858 case VRANGEPDZrrib:
28859 case VRANGEPDZrribk:
28860 case VRANGEPDZrribkz:
28861 case VRANGEPDZrrik:
28862 case VRANGEPDZrrikz:
28863 return true;
28864 }
28865 return false;
28866}
28867
28868bool isCMC(unsigned Opcode) {
28869 return Opcode == CMC;
28870}
28871
28872bool isVFNMADD231BF16(unsigned Opcode) {
28873 switch (Opcode) {
28874 case VFNMADD231BF16Z128m:
28875 case VFNMADD231BF16Z128mb:
28876 case VFNMADD231BF16Z128mbk:
28877 case VFNMADD231BF16Z128mbkz:
28878 case VFNMADD231BF16Z128mk:
28879 case VFNMADD231BF16Z128mkz:
28880 case VFNMADD231BF16Z128r:
28881 case VFNMADD231BF16Z128rk:
28882 case VFNMADD231BF16Z128rkz:
28883 case VFNMADD231BF16Z256m:
28884 case VFNMADD231BF16Z256mb:
28885 case VFNMADD231BF16Z256mbk:
28886 case VFNMADD231BF16Z256mbkz:
28887 case VFNMADD231BF16Z256mk:
28888 case VFNMADD231BF16Z256mkz:
28889 case VFNMADD231BF16Z256r:
28890 case VFNMADD231BF16Z256rk:
28891 case VFNMADD231BF16Z256rkz:
28892 case VFNMADD231BF16Zm:
28893 case VFNMADD231BF16Zmb:
28894 case VFNMADD231BF16Zmbk:
28895 case VFNMADD231BF16Zmbkz:
28896 case VFNMADD231BF16Zmk:
28897 case VFNMADD231BF16Zmkz:
28898 case VFNMADD231BF16Zr:
28899 case VFNMADD231BF16Zrk:
28900 case VFNMADD231BF16Zrkz:
28901 return true;
28902 }
28903 return false;
28904}
28905
28906bool isSHA256MSG1(unsigned Opcode) {
28907 switch (Opcode) {
28908 case SHA256MSG1rm:
28909 case SHA256MSG1rr:
28910 return true;
28911 }
28912 return false;
28913}
28914
28915bool isFLD1(unsigned Opcode) {
28916 return Opcode == LD_F1;
28917}
28918
28919bool isCMPPS(unsigned Opcode) {
28920 switch (Opcode) {
28921 case CMPPSrmi:
28922 case CMPPSrri:
28923 return true;
28924 }
28925 return false;
28926}
28927
28928bool isVPAVGW(unsigned Opcode) {
28929 switch (Opcode) {
28930 case VPAVGWYrm:
28931 case VPAVGWYrr:
28932 case VPAVGWZ128rm:
28933 case VPAVGWZ128rmk:
28934 case VPAVGWZ128rmkz:
28935 case VPAVGWZ128rr:
28936 case VPAVGWZ128rrk:
28937 case VPAVGWZ128rrkz:
28938 case VPAVGWZ256rm:
28939 case VPAVGWZ256rmk:
28940 case VPAVGWZ256rmkz:
28941 case VPAVGWZ256rr:
28942 case VPAVGWZ256rrk:
28943 case VPAVGWZ256rrkz:
28944 case VPAVGWZrm:
28945 case VPAVGWZrmk:
28946 case VPAVGWZrmkz:
28947 case VPAVGWZrr:
28948 case VPAVGWZrrk:
28949 case VPAVGWZrrkz:
28950 case VPAVGWrm:
28951 case VPAVGWrr:
28952 return true;
28953 }
28954 return false;
28955}
28956
28957bool isVFMADD213SH(unsigned Opcode) {
28958 switch (Opcode) {
28959 case VFMADD213SHZm_Int:
28960 case VFMADD213SHZmk_Int:
28961 case VFMADD213SHZmkz_Int:
28962 case VFMADD213SHZr_Int:
28963 case VFMADD213SHZrb_Int:
28964 case VFMADD213SHZrbk_Int:
28965 case VFMADD213SHZrbkz_Int:
28966 case VFMADD213SHZrk_Int:
28967 case VFMADD213SHZrkz_Int:
28968 return true;
28969 }
28970 return false;
28971}
28972
28973bool isVPCMPESTRMQ(unsigned Opcode) {
28974 switch (Opcode) {
28975 case VPCMPESTRMQrmi:
28976 case VPCMPESTRMQrri:
28977 return true;
28978 }
28979 return false;
28980}
28981
28982bool isVPINSRQ(unsigned Opcode) {
28983 switch (Opcode) {
28984 case VPINSRQZrmi:
28985 case VPINSRQZrri:
28986 case VPINSRQrmi:
28987 case VPINSRQrri:
28988 return true;
28989 }
28990 return false;
28991}
28992
28993bool isMOVABS(unsigned Opcode) {
28994 switch (Opcode) {
28995 case MOV16ao64:
28996 case MOV16o64a:
28997 case MOV32ao64:
28998 case MOV32o64a:
28999 case MOV64ao64:
29000 case MOV64o64a:
29001 case MOV64ri:
29002 case MOV8ao64:
29003 case MOV8o64a:
29004 return true;
29005 }
29006 return false;
29007}
29008
29009bool isVPSHAQ(unsigned Opcode) {
29010 switch (Opcode) {
29011 case VPSHAQmr:
29012 case VPSHAQrm:
29013 case VPSHAQrr:
29014 case VPSHAQrr_REV:
29015 return true;
29016 }
29017 return false;
29018}
29019
29020bool isRDTSCP(unsigned Opcode) {
29021 return Opcode == RDTSCP;
29022}
29023
29024bool isVFNMADD231SS(unsigned Opcode) {
29025 switch (Opcode) {
29026 case VFNMADD231SSZm_Int:
29027 case VFNMADD231SSZmk_Int:
29028 case VFNMADD231SSZmkz_Int:
29029 case VFNMADD231SSZr_Int:
29030 case VFNMADD231SSZrb_Int:
29031 case VFNMADD231SSZrbk_Int:
29032 case VFNMADD231SSZrbkz_Int:
29033 case VFNMADD231SSZrk_Int:
29034 case VFNMADD231SSZrkz_Int:
29035 case VFNMADD231SSm_Int:
29036 case VFNMADD231SSr_Int:
29037 return true;
29038 }
29039 return false;
29040}
29041
29042bool isTEST(unsigned Opcode) {
29043 switch (Opcode) {
29044 case TEST16i16:
29045 case TEST16mi:
29046 case TEST16mr:
29047 case TEST16ri:
29048 case TEST16rr:
29049 case TEST32i32:
29050 case TEST32mi:
29051 case TEST32mr:
29052 case TEST32ri:
29053 case TEST32rr:
29054 case TEST64i32:
29055 case TEST64mi32:
29056 case TEST64mr:
29057 case TEST64ri32:
29058 case TEST64rr:
29059 case TEST8i8:
29060 case TEST8mi:
29061 case TEST8mr:
29062 case TEST8ri:
29063 case TEST8rr:
29064 return true;
29065 }
29066 return false;
29067}
29068
29069bool isVPERMD(unsigned Opcode) {
29070 switch (Opcode) {
29071 case VPERMDYrm:
29072 case VPERMDYrr:
29073 case VPERMDZ256rm:
29074 case VPERMDZ256rmb:
29075 case VPERMDZ256rmbk:
29076 case VPERMDZ256rmbkz:
29077 case VPERMDZ256rmk:
29078 case VPERMDZ256rmkz:
29079 case VPERMDZ256rr:
29080 case VPERMDZ256rrk:
29081 case VPERMDZ256rrkz:
29082 case VPERMDZrm:
29083 case VPERMDZrmb:
29084 case VPERMDZrmbk:
29085 case VPERMDZrmbkz:
29086 case VPERMDZrmk:
29087 case VPERMDZrmkz:
29088 case VPERMDZrr:
29089 case VPERMDZrrk:
29090 case VPERMDZrrkz:
29091 return true;
29092 }
29093 return false;
29094}
29095
29096bool isVBCSTNESH2PS(unsigned Opcode) {
29097 switch (Opcode) {
29098 case VBCSTNESH2PSYrm:
29099 case VBCSTNESH2PSrm:
29100 return true;
29101 }
29102 return false;
29103}
29104
29105bool isVGATHERPF0QPD(unsigned Opcode) {
29106 return Opcode == VGATHERPF0QPDm;
29107}
29108
29109bool isVPERM2I128(unsigned Opcode) {
29110 switch (Opcode) {
29111 case VPERM2I128rmi:
29112 case VPERM2I128rri:
29113 return true;
29114 }
29115 return false;
29116}
29117
29118bool isVMPSADBW(unsigned Opcode) {
29119 switch (Opcode) {
29120 case VMPSADBWYrmi:
29121 case VMPSADBWYrri:
29122 case VMPSADBWZ128rmi:
29123 case VMPSADBWZ128rmik:
29124 case VMPSADBWZ128rmikz:
29125 case VMPSADBWZ128rri:
29126 case VMPSADBWZ128rrik:
29127 case VMPSADBWZ128rrikz:
29128 case VMPSADBWZ256rmi:
29129 case VMPSADBWZ256rmik:
29130 case VMPSADBWZ256rmikz:
29131 case VMPSADBWZ256rri:
29132 case VMPSADBWZ256rrik:
29133 case VMPSADBWZ256rrikz:
29134 case VMPSADBWZrmi:
29135 case VMPSADBWZrmik:
29136 case VMPSADBWZrmikz:
29137 case VMPSADBWZrri:
29138 case VMPSADBWZrrik:
29139 case VMPSADBWZrrikz:
29140 case VMPSADBWrmi:
29141 case VMPSADBWrri:
29142 return true;
29143 }
29144 return false;
29145}
29146
29147bool isVFNMSUB231PD(unsigned Opcode) {
29148 switch (Opcode) {
29149 case VFNMSUB231PDYm:
29150 case VFNMSUB231PDYr:
29151 case VFNMSUB231PDZ128m:
29152 case VFNMSUB231PDZ128mb:
29153 case VFNMSUB231PDZ128mbk:
29154 case VFNMSUB231PDZ128mbkz:
29155 case VFNMSUB231PDZ128mk:
29156 case VFNMSUB231PDZ128mkz:
29157 case VFNMSUB231PDZ128r:
29158 case VFNMSUB231PDZ128rk:
29159 case VFNMSUB231PDZ128rkz:
29160 case VFNMSUB231PDZ256m:
29161 case VFNMSUB231PDZ256mb:
29162 case VFNMSUB231PDZ256mbk:
29163 case VFNMSUB231PDZ256mbkz:
29164 case VFNMSUB231PDZ256mk:
29165 case VFNMSUB231PDZ256mkz:
29166 case VFNMSUB231PDZ256r:
29167 case VFNMSUB231PDZ256rk:
29168 case VFNMSUB231PDZ256rkz:
29169 case VFNMSUB231PDZm:
29170 case VFNMSUB231PDZmb:
29171 case VFNMSUB231PDZmbk:
29172 case VFNMSUB231PDZmbkz:
29173 case VFNMSUB231PDZmk:
29174 case VFNMSUB231PDZmkz:
29175 case VFNMSUB231PDZr:
29176 case VFNMSUB231PDZrb:
29177 case VFNMSUB231PDZrbk:
29178 case VFNMSUB231PDZrbkz:
29179 case VFNMSUB231PDZrk:
29180 case VFNMSUB231PDZrkz:
29181 case VFNMSUB231PDm:
29182 case VFNMSUB231PDr:
29183 return true;
29184 }
29185 return false;
29186}
29187
29188bool isPADDSB(unsigned Opcode) {
29189 switch (Opcode) {
29190 case MMX_PADDSBrm:
29191 case MMX_PADDSBrr:
29192 case PADDSBrm:
29193 case PADDSBrr:
29194 return true;
29195 }
29196 return false;
29197}
29198
29199bool isMWAITX(unsigned Opcode) {
29200 return Opcode == MWAITXrrr;
29201}
29202
29203bool isMONITORX(unsigned Opcode) {
29204 switch (Opcode) {
29205 case MONITORX32rrr:
29206 case MONITORX64rrr:
29207 return true;
29208 }
29209 return false;
29210}
29211
29212bool isVPEXPANDD(unsigned Opcode) {
29213 switch (Opcode) {
29214 case VPEXPANDDZ128rm:
29215 case VPEXPANDDZ128rmk:
29216 case VPEXPANDDZ128rmkz:
29217 case VPEXPANDDZ128rr:
29218 case VPEXPANDDZ128rrk:
29219 case VPEXPANDDZ128rrkz:
29220 case VPEXPANDDZ256rm:
29221 case VPEXPANDDZ256rmk:
29222 case VPEXPANDDZ256rmkz:
29223 case VPEXPANDDZ256rr:
29224 case VPEXPANDDZ256rrk:
29225 case VPEXPANDDZ256rrkz:
29226 case VPEXPANDDZrm:
29227 case VPEXPANDDZrmk:
29228 case VPEXPANDDZrmkz:
29229 case VPEXPANDDZrr:
29230 case VPEXPANDDZrrk:
29231 case VPEXPANDDZrrkz:
29232 return true;
29233 }
29234 return false;
29235}
29236
29237bool isVFRCZPD(unsigned Opcode) {
29238 switch (Opcode) {
29239 case VFRCZPDYrm:
29240 case VFRCZPDYrr:
29241 case VFRCZPDrm:
29242 case VFRCZPDrr:
29243 return true;
29244 }
29245 return false;
29246}
29247
29248bool isVRCPPH(unsigned Opcode) {
29249 switch (Opcode) {
29250 case VRCPPHZ128m:
29251 case VRCPPHZ128mb:
29252 case VRCPPHZ128mbk:
29253 case VRCPPHZ128mbkz:
29254 case VRCPPHZ128mk:
29255 case VRCPPHZ128mkz:
29256 case VRCPPHZ128r:
29257 case VRCPPHZ128rk:
29258 case VRCPPHZ128rkz:
29259 case VRCPPHZ256m:
29260 case VRCPPHZ256mb:
29261 case VRCPPHZ256mbk:
29262 case VRCPPHZ256mbkz:
29263 case VRCPPHZ256mk:
29264 case VRCPPHZ256mkz:
29265 case VRCPPHZ256r:
29266 case VRCPPHZ256rk:
29267 case VRCPPHZ256rkz:
29268 case VRCPPHZm:
29269 case VRCPPHZmb:
29270 case VRCPPHZmbk:
29271 case VRCPPHZmbkz:
29272 case VRCPPHZmk:
29273 case VRCPPHZmkz:
29274 case VRCPPHZr:
29275 case VRCPPHZrk:
29276 case VRCPPHZrkz:
29277 return true;
29278 }
29279 return false;
29280}
29281
29282bool isFEMMS(unsigned Opcode) {
29283 return Opcode == FEMMS;
29284}
29285
29286bool isVSCATTERQPD(unsigned Opcode) {
29287 switch (Opcode) {
29288 case VSCATTERQPDZ128mr:
29289 case VSCATTERQPDZ256mr:
29290 case VSCATTERQPDZmr:
29291 return true;
29292 }
29293 return false;
29294}
29295
29296bool isVMOVW(unsigned Opcode) {
29297 switch (Opcode) {
29298 case VMOVSH2Wrr:
29299 case VMOVSHtoW64rr:
29300 case VMOVW2SHrr:
29301 case VMOVW64toSHrr:
29302 case VMOVWmr:
29303 case VMOVWrm:
29304 case VMOVZPWILo2PWIZmr:
29305 case VMOVZPWILo2PWIZrm:
29306 case VMOVZPWILo2PWIZrr:
29307 case VMOVZPWILo2PWIZrr2:
29308 return true;
29309 }
29310 return false;
29311}
29312
29313bool isVPBROADCASTD(unsigned Opcode) {
29314 switch (Opcode) {
29315 case VPBROADCASTDYrm:
29316 case VPBROADCASTDYrr:
29317 case VPBROADCASTDZ128rm:
29318 case VPBROADCASTDZ128rmk:
29319 case VPBROADCASTDZ128rmkz:
29320 case VPBROADCASTDZ128rr:
29321 case VPBROADCASTDZ128rrk:
29322 case VPBROADCASTDZ128rrkz:
29323 case VPBROADCASTDZ256rm:
29324 case VPBROADCASTDZ256rmk:
29325 case VPBROADCASTDZ256rmkz:
29326 case VPBROADCASTDZ256rr:
29327 case VPBROADCASTDZ256rrk:
29328 case VPBROADCASTDZ256rrkz:
29329 case VPBROADCASTDZrm:
29330 case VPBROADCASTDZrmk:
29331 case VPBROADCASTDZrmkz:
29332 case VPBROADCASTDZrr:
29333 case VPBROADCASTDZrrk:
29334 case VPBROADCASTDZrrkz:
29335 case VPBROADCASTDrZ128rr:
29336 case VPBROADCASTDrZ128rrk:
29337 case VPBROADCASTDrZ128rrkz:
29338 case VPBROADCASTDrZ256rr:
29339 case VPBROADCASTDrZ256rrk:
29340 case VPBROADCASTDrZ256rrkz:
29341 case VPBROADCASTDrZrr:
29342 case VPBROADCASTDrZrrk:
29343 case VPBROADCASTDrZrrkz:
29344 case VPBROADCASTDrm:
29345 case VPBROADCASTDrr:
29346 return true;
29347 }
29348 return false;
29349}
29350
29351bool isSTOSB(unsigned Opcode) {
29352 return Opcode == STOSB;
29353}
29354
29355bool isFUCOMI(unsigned Opcode) {
29356 return Opcode == UCOM_FIr;
29357}
29358
29359bool isVBROADCASTI64X4(unsigned Opcode) {
29360 switch (Opcode) {
29361 case VBROADCASTI64X4Zrm:
29362 case VBROADCASTI64X4Zrmk:
29363 case VBROADCASTI64X4Zrmkz:
29364 return true;
29365 }
29366 return false;
29367}
29368
29369bool isFCMOVU(unsigned Opcode) {
29370 return Opcode == CMOVP_F;
29371}
29372
29373bool isPSHUFLW(unsigned Opcode) {
29374 switch (Opcode) {
29375 case PSHUFLWmi:
29376 case PSHUFLWri:
29377 return true;
29378 }
29379 return false;
29380}
29381
29382bool isCVTPI2PS(unsigned Opcode) {
29383 switch (Opcode) {
29384 case MMX_CVTPI2PSrm:
29385 case MMX_CVTPI2PSrr:
29386 return true;
29387 }
29388 return false;
29389}
29390
29391bool isVCVTTPD2UDQS(unsigned Opcode) {
29392 switch (Opcode) {
29393 case VCVTTPD2UDQSZ128rm:
29394 case VCVTTPD2UDQSZ128rmb:
29395 case VCVTTPD2UDQSZ128rmbk:
29396 case VCVTTPD2UDQSZ128rmbkz:
29397 case VCVTTPD2UDQSZ128rmk:
29398 case VCVTTPD2UDQSZ128rmkz:
29399 case VCVTTPD2UDQSZ128rr:
29400 case VCVTTPD2UDQSZ128rrk:
29401 case VCVTTPD2UDQSZ128rrkz:
29402 case VCVTTPD2UDQSZ256rm:
29403 case VCVTTPD2UDQSZ256rmb:
29404 case VCVTTPD2UDQSZ256rmbk:
29405 case VCVTTPD2UDQSZ256rmbkz:
29406 case VCVTTPD2UDQSZ256rmk:
29407 case VCVTTPD2UDQSZ256rmkz:
29408 case VCVTTPD2UDQSZ256rr:
29409 case VCVTTPD2UDQSZ256rrb:
29410 case VCVTTPD2UDQSZ256rrbk:
29411 case VCVTTPD2UDQSZ256rrbkz:
29412 case VCVTTPD2UDQSZ256rrk:
29413 case VCVTTPD2UDQSZ256rrkz:
29414 case VCVTTPD2UDQSZrm:
29415 case VCVTTPD2UDQSZrmb:
29416 case VCVTTPD2UDQSZrmbk:
29417 case VCVTTPD2UDQSZrmbkz:
29418 case VCVTTPD2UDQSZrmk:
29419 case VCVTTPD2UDQSZrmkz:
29420 case VCVTTPD2UDQSZrr:
29421 case VCVTTPD2UDQSZrrb:
29422 case VCVTTPD2UDQSZrrbk:
29423 case VCVTTPD2UDQSZrrbkz:
29424 case VCVTTPD2UDQSZrrk:
29425 case VCVTTPD2UDQSZrrkz:
29426 return true;
29427 }
29428 return false;
29429}
29430
29431bool isSYSCALL(unsigned Opcode) {
29432 return Opcode == SYSCALL;
29433}
29434
29435bool isVFMADD231SH(unsigned Opcode) {
29436 switch (Opcode) {
29437 case VFMADD231SHZm_Int:
29438 case VFMADD231SHZmk_Int:
29439 case VFMADD231SHZmkz_Int:
29440 case VFMADD231SHZr_Int:
29441 case VFMADD231SHZrb_Int:
29442 case VFMADD231SHZrbk_Int:
29443 case VFMADD231SHZrbkz_Int:
29444 case VFMADD231SHZrk_Int:
29445 case VFMADD231SHZrkz_Int:
29446 return true;
29447 }
29448 return false;
29449}
29450
29451bool isPMOVZXBW(unsigned Opcode) {
29452 switch (Opcode) {
29453 case PMOVZXBWrm:
29454 case PMOVZXBWrr:
29455 return true;
29456 }
29457 return false;
29458}
29459
29460bool isVPOPCNTB(unsigned Opcode) {
29461 switch (Opcode) {
29462 case VPOPCNTBZ128rm:
29463 case VPOPCNTBZ128rmk:
29464 case VPOPCNTBZ128rmkz:
29465 case VPOPCNTBZ128rr:
29466 case VPOPCNTBZ128rrk:
29467 case VPOPCNTBZ128rrkz:
29468 case VPOPCNTBZ256rm:
29469 case VPOPCNTBZ256rmk:
29470 case VPOPCNTBZ256rmkz:
29471 case VPOPCNTBZ256rr:
29472 case VPOPCNTBZ256rrk:
29473 case VPOPCNTBZ256rrkz:
29474 case VPOPCNTBZrm:
29475 case VPOPCNTBZrmk:
29476 case VPOPCNTBZrmkz:
29477 case VPOPCNTBZrr:
29478 case VPOPCNTBZrrk:
29479 case VPOPCNTBZrrkz:
29480 return true;
29481 }
29482 return false;
29483}
29484
29485bool isVCVTDQ2PS(unsigned Opcode) {
29486 switch (Opcode) {
29487 case VCVTDQ2PSYrm:
29488 case VCVTDQ2PSYrr:
29489 case VCVTDQ2PSZ128rm:
29490 case VCVTDQ2PSZ128rmb:
29491 case VCVTDQ2PSZ128rmbk:
29492 case VCVTDQ2PSZ128rmbkz:
29493 case VCVTDQ2PSZ128rmk:
29494 case VCVTDQ2PSZ128rmkz:
29495 case VCVTDQ2PSZ128rr:
29496 case VCVTDQ2PSZ128rrk:
29497 case VCVTDQ2PSZ128rrkz:
29498 case VCVTDQ2PSZ256rm:
29499 case VCVTDQ2PSZ256rmb:
29500 case VCVTDQ2PSZ256rmbk:
29501 case VCVTDQ2PSZ256rmbkz:
29502 case VCVTDQ2PSZ256rmk:
29503 case VCVTDQ2PSZ256rmkz:
29504 case VCVTDQ2PSZ256rr:
29505 case VCVTDQ2PSZ256rrk:
29506 case VCVTDQ2PSZ256rrkz:
29507 case VCVTDQ2PSZrm:
29508 case VCVTDQ2PSZrmb:
29509 case VCVTDQ2PSZrmbk:
29510 case VCVTDQ2PSZrmbkz:
29511 case VCVTDQ2PSZrmk:
29512 case VCVTDQ2PSZrmkz:
29513 case VCVTDQ2PSZrr:
29514 case VCVTDQ2PSZrrb:
29515 case VCVTDQ2PSZrrbk:
29516 case VCVTDQ2PSZrrbkz:
29517 case VCVTDQ2PSZrrk:
29518 case VCVTDQ2PSZrrkz:
29519 case VCVTDQ2PSrm:
29520 case VCVTDQ2PSrr:
29521 return true;
29522 }
29523 return false;
29524}
29525
29526bool isPSUBD(unsigned Opcode) {
29527 switch (Opcode) {
29528 case MMX_PSUBDrm:
29529 case MMX_PSUBDrr:
29530 case PSUBDrm:
29531 case PSUBDrr:
29532 return true;
29533 }
29534 return false;
29535}
29536
29537bool isVPCMPEQW(unsigned Opcode) {
29538 switch (Opcode) {
29539 case VPCMPEQWYrm:
29540 case VPCMPEQWYrr:
29541 case VPCMPEQWZ128rm:
29542 case VPCMPEQWZ128rmk:
29543 case VPCMPEQWZ128rr:
29544 case VPCMPEQWZ128rrk:
29545 case VPCMPEQWZ256rm:
29546 case VPCMPEQWZ256rmk:
29547 case VPCMPEQWZ256rr:
29548 case VPCMPEQWZ256rrk:
29549 case VPCMPEQWZrm:
29550 case VPCMPEQWZrmk:
29551 case VPCMPEQWZrr:
29552 case VPCMPEQWZrrk:
29553 case VPCMPEQWrm:
29554 case VPCMPEQWrr:
29555 return true;
29556 }
29557 return false;
29558}
29559
29560bool isMOVSW(unsigned Opcode) {
29561 return Opcode == MOVSW;
29562}
29563
29564bool isVSM3RNDS2(unsigned Opcode) {
29565 switch (Opcode) {
29566 case VSM3RNDS2rmi:
29567 case VSM3RNDS2rri:
29568 return true;
29569 }
29570 return false;
29571}
29572
29573bool isVPMOVUSQD(unsigned Opcode) {
29574 switch (Opcode) {
29575 case VPMOVUSQDZ128mr:
29576 case VPMOVUSQDZ128mrk:
29577 case VPMOVUSQDZ128rr:
29578 case VPMOVUSQDZ128rrk:
29579 case VPMOVUSQDZ128rrkz:
29580 case VPMOVUSQDZ256mr:
29581 case VPMOVUSQDZ256mrk:
29582 case VPMOVUSQDZ256rr:
29583 case VPMOVUSQDZ256rrk:
29584 case VPMOVUSQDZ256rrkz:
29585 case VPMOVUSQDZmr:
29586 case VPMOVUSQDZmrk:
29587 case VPMOVUSQDZrr:
29588 case VPMOVUSQDZrrk:
29589 case VPMOVUSQDZrrkz:
29590 return true;
29591 }
29592 return false;
29593}
29594
29595bool isCVTTPD2DQ(unsigned Opcode) {
29596 switch (Opcode) {
29597 case CVTTPD2DQrm:
29598 case CVTTPD2DQrr:
29599 return true;
29600 }
29601 return false;
29602}
29603
29604bool isVPEXPANDW(unsigned Opcode) {
29605 switch (Opcode) {
29606 case VPEXPANDWZ128rm:
29607 case VPEXPANDWZ128rmk:
29608 case VPEXPANDWZ128rmkz:
29609 case VPEXPANDWZ128rr:
29610 case VPEXPANDWZ128rrk:
29611 case VPEXPANDWZ128rrkz:
29612 case VPEXPANDWZ256rm:
29613 case VPEXPANDWZ256rmk:
29614 case VPEXPANDWZ256rmkz:
29615 case VPEXPANDWZ256rr:
29616 case VPEXPANDWZ256rrk:
29617 case VPEXPANDWZ256rrkz:
29618 case VPEXPANDWZrm:
29619 case VPEXPANDWZrmk:
29620 case VPEXPANDWZrmkz:
29621 case VPEXPANDWZrr:
29622 case VPEXPANDWZrrk:
29623 case VPEXPANDWZrrkz:
29624 return true;
29625 }
29626 return false;
29627}
29628
29629bool isVUCOMISH(unsigned Opcode) {
29630 switch (Opcode) {
29631 case VUCOMISHZrm:
29632 case VUCOMISHZrr:
29633 case VUCOMISHZrrb:
29634 return true;
29635 }
29636 return false;
29637}
29638
29639bool isVZEROALL(unsigned Opcode) {
29640 return Opcode == VZEROALL;
29641}
29642
29643bool isVPAND(unsigned Opcode) {
29644 switch (Opcode) {
29645 case VPANDYrm:
29646 case VPANDYrr:
29647 case VPANDrm:
29648 case VPANDrr:
29649 return true;
29650 }
29651 return false;
29652}
29653
29654bool isPMULDQ(unsigned Opcode) {
29655 switch (Opcode) {
29656 case PMULDQrm:
29657 case PMULDQrr:
29658 return true;
29659 }
29660 return false;
29661}
29662
29663bool isVPSHUFHW(unsigned Opcode) {
29664 switch (Opcode) {
29665 case VPSHUFHWYmi:
29666 case VPSHUFHWYri:
29667 case VPSHUFHWZ128mi:
29668 case VPSHUFHWZ128mik:
29669 case VPSHUFHWZ128mikz:
29670 case VPSHUFHWZ128ri:
29671 case VPSHUFHWZ128rik:
29672 case VPSHUFHWZ128rikz:
29673 case VPSHUFHWZ256mi:
29674 case VPSHUFHWZ256mik:
29675 case VPSHUFHWZ256mikz:
29676 case VPSHUFHWZ256ri:
29677 case VPSHUFHWZ256rik:
29678 case VPSHUFHWZ256rikz:
29679 case VPSHUFHWZmi:
29680 case VPSHUFHWZmik:
29681 case VPSHUFHWZmikz:
29682 case VPSHUFHWZri:
29683 case VPSHUFHWZrik:
29684 case VPSHUFHWZrikz:
29685 case VPSHUFHWmi:
29686 case VPSHUFHWri:
29687 return true;
29688 }
29689 return false;
29690}
29691
29692bool isVPALIGNR(unsigned Opcode) {
29693 switch (Opcode) {
29694 case VPALIGNRYrmi:
29695 case VPALIGNRYrri:
29696 case VPALIGNRZ128rmi:
29697 case VPALIGNRZ128rmik:
29698 case VPALIGNRZ128rmikz:
29699 case VPALIGNRZ128rri:
29700 case VPALIGNRZ128rrik:
29701 case VPALIGNRZ128rrikz:
29702 case VPALIGNRZ256rmi:
29703 case VPALIGNRZ256rmik:
29704 case VPALIGNRZ256rmikz:
29705 case VPALIGNRZ256rri:
29706 case VPALIGNRZ256rrik:
29707 case VPALIGNRZ256rrikz:
29708 case VPALIGNRZrmi:
29709 case VPALIGNRZrmik:
29710 case VPALIGNRZrmikz:
29711 case VPALIGNRZrri:
29712 case VPALIGNRZrrik:
29713 case VPALIGNRZrrikz:
29714 case VPALIGNRrmi:
29715 case VPALIGNRrri:
29716 return true;
29717 }
29718 return false;
29719}
29720
29721bool isSQRTSD(unsigned Opcode) {
29722 switch (Opcode) {
29723 case SQRTSDm_Int:
29724 case SQRTSDr_Int:
29725 return true;
29726 }
29727 return false;
29728}
29729
29730bool isVCVTTPH2UDQ(unsigned Opcode) {
29731 switch (Opcode) {
29732 case VCVTTPH2UDQZ128rm:
29733 case VCVTTPH2UDQZ128rmb:
29734 case VCVTTPH2UDQZ128rmbk:
29735 case VCVTTPH2UDQZ128rmbkz:
29736 case VCVTTPH2UDQZ128rmk:
29737 case VCVTTPH2UDQZ128rmkz:
29738 case VCVTTPH2UDQZ128rr:
29739 case VCVTTPH2UDQZ128rrk:
29740 case VCVTTPH2UDQZ128rrkz:
29741 case VCVTTPH2UDQZ256rm:
29742 case VCVTTPH2UDQZ256rmb:
29743 case VCVTTPH2UDQZ256rmbk:
29744 case VCVTTPH2UDQZ256rmbkz:
29745 case VCVTTPH2UDQZ256rmk:
29746 case VCVTTPH2UDQZ256rmkz:
29747 case VCVTTPH2UDQZ256rr:
29748 case VCVTTPH2UDQZ256rrk:
29749 case VCVTTPH2UDQZ256rrkz:
29750 case VCVTTPH2UDQZrm:
29751 case VCVTTPH2UDQZrmb:
29752 case VCVTTPH2UDQZrmbk:
29753 case VCVTTPH2UDQZrmbkz:
29754 case VCVTTPH2UDQZrmk:
29755 case VCVTTPH2UDQZrmkz:
29756 case VCVTTPH2UDQZrr:
29757 case VCVTTPH2UDQZrrb:
29758 case VCVTTPH2UDQZrrbk:
29759 case VCVTTPH2UDQZrrbkz:
29760 case VCVTTPH2UDQZrrk:
29761 case VCVTTPH2UDQZrrkz:
29762 return true;
29763 }
29764 return false;
29765}
29766
29767bool isVGETEXPPH(unsigned Opcode) {
29768 switch (Opcode) {
29769 case VGETEXPPHZ128m:
29770 case VGETEXPPHZ128mb:
29771 case VGETEXPPHZ128mbk:
29772 case VGETEXPPHZ128mbkz:
29773 case VGETEXPPHZ128mk:
29774 case VGETEXPPHZ128mkz:
29775 case VGETEXPPHZ128r:
29776 case VGETEXPPHZ128rk:
29777 case VGETEXPPHZ128rkz:
29778 case VGETEXPPHZ256m:
29779 case VGETEXPPHZ256mb:
29780 case VGETEXPPHZ256mbk:
29781 case VGETEXPPHZ256mbkz:
29782 case VGETEXPPHZ256mk:
29783 case VGETEXPPHZ256mkz:
29784 case VGETEXPPHZ256r:
29785 case VGETEXPPHZ256rk:
29786 case VGETEXPPHZ256rkz:
29787 case VGETEXPPHZm:
29788 case VGETEXPPHZmb:
29789 case VGETEXPPHZmbk:
29790 case VGETEXPPHZmbkz:
29791 case VGETEXPPHZmk:
29792 case VGETEXPPHZmkz:
29793 case VGETEXPPHZr:
29794 case VGETEXPPHZrb:
29795 case VGETEXPPHZrbk:
29796 case VGETEXPPHZrbkz:
29797 case VGETEXPPHZrk:
29798 case VGETEXPPHZrkz:
29799 return true;
29800 }
29801 return false;
29802}
29803
29804bool isADDPD(unsigned Opcode) {
29805 switch (Opcode) {
29806 case ADDPDrm:
29807 case ADDPDrr:
29808 return true;
29809 }
29810 return false;
29811}
29812
29813bool isVFNMADDPD(unsigned Opcode) {
29814 switch (Opcode) {
29815 case VFNMADDPD4Ymr:
29816 case VFNMADDPD4Yrm:
29817 case VFNMADDPD4Yrr:
29818 case VFNMADDPD4Yrr_REV:
29819 case VFNMADDPD4mr:
29820 case VFNMADDPD4rm:
29821 case VFNMADDPD4rr:
29822 case VFNMADDPD4rr_REV:
29823 return true;
29824 }
29825 return false;
29826}
29827
29828bool isSTTILECFG(unsigned Opcode) {
29829 switch (Opcode) {
29830 case STTILECFG:
29831 case STTILECFG_EVEX:
29832 return true;
29833 }
29834 return false;
29835}
29836
29837bool isVMINPD(unsigned Opcode) {
29838 switch (Opcode) {
29839 case VMINPDYrm:
29840 case VMINPDYrr:
29841 case VMINPDZ128rm:
29842 case VMINPDZ128rmb:
29843 case VMINPDZ128rmbk:
29844 case VMINPDZ128rmbkz:
29845 case VMINPDZ128rmk:
29846 case VMINPDZ128rmkz:
29847 case VMINPDZ128rr:
29848 case VMINPDZ128rrk:
29849 case VMINPDZ128rrkz:
29850 case VMINPDZ256rm:
29851 case VMINPDZ256rmb:
29852 case VMINPDZ256rmbk:
29853 case VMINPDZ256rmbkz:
29854 case VMINPDZ256rmk:
29855 case VMINPDZ256rmkz:
29856 case VMINPDZ256rr:
29857 case VMINPDZ256rrk:
29858 case VMINPDZ256rrkz:
29859 case VMINPDZrm:
29860 case VMINPDZrmb:
29861 case VMINPDZrmbk:
29862 case VMINPDZrmbkz:
29863 case VMINPDZrmk:
29864 case VMINPDZrmkz:
29865 case VMINPDZrr:
29866 case VMINPDZrrb:
29867 case VMINPDZrrbk:
29868 case VMINPDZrrbkz:
29869 case VMINPDZrrk:
29870 case VMINPDZrrkz:
29871 case VMINPDrm:
29872 case VMINPDrr:
29873 return true;
29874 }
29875 return false;
29876}
29877
29878bool isSHA1RNDS4(unsigned Opcode) {
29879 switch (Opcode) {
29880 case SHA1RNDS4rmi:
29881 case SHA1RNDS4rri:
29882 return true;
29883 }
29884 return false;
29885}
29886
29887bool isPBLENDVB(unsigned Opcode) {
29888 switch (Opcode) {
29889 case PBLENDVBrm0:
29890 case PBLENDVBrr0:
29891 return true;
29892 }
29893 return false;
29894}
29895
29896bool isVBROADCASTF128(unsigned Opcode) {
29897 return Opcode == VBROADCASTF128rm;
29898}
29899
29900bool isVPSHRDQ(unsigned Opcode) {
29901 switch (Opcode) {
29902 case VPSHRDQZ128rmbi:
29903 case VPSHRDQZ128rmbik:
29904 case VPSHRDQZ128rmbikz:
29905 case VPSHRDQZ128rmi:
29906 case VPSHRDQZ128rmik:
29907 case VPSHRDQZ128rmikz:
29908 case VPSHRDQZ128rri:
29909 case VPSHRDQZ128rrik:
29910 case VPSHRDQZ128rrikz:
29911 case VPSHRDQZ256rmbi:
29912 case VPSHRDQZ256rmbik:
29913 case VPSHRDQZ256rmbikz:
29914 case VPSHRDQZ256rmi:
29915 case VPSHRDQZ256rmik:
29916 case VPSHRDQZ256rmikz:
29917 case VPSHRDQZ256rri:
29918 case VPSHRDQZ256rrik:
29919 case VPSHRDQZ256rrikz:
29920 case VPSHRDQZrmbi:
29921 case VPSHRDQZrmbik:
29922 case VPSHRDQZrmbikz:
29923 case VPSHRDQZrmi:
29924 case VPSHRDQZrmik:
29925 case VPSHRDQZrmikz:
29926 case VPSHRDQZrri:
29927 case VPSHRDQZrrik:
29928 case VPSHRDQZrrikz:
29929 return true;
29930 }
29931 return false;
29932}
29933
29934bool isVAESIMC(unsigned Opcode) {
29935 switch (Opcode) {
29936 case VAESIMCrm:
29937 case VAESIMCrr:
29938 return true;
29939 }
29940 return false;
29941}
29942
29943bool isCOMISD(unsigned Opcode) {
29944 switch (Opcode) {
29945 case COMISDrm:
29946 case COMISDrr:
29947 return true;
29948 }
29949 return false;
29950}
29951
29952bool isVMOVSH(unsigned Opcode) {
29953 switch (Opcode) {
29954 case VMOVSHZmr:
29955 case VMOVSHZmrk:
29956 case VMOVSHZrm:
29957 case VMOVSHZrmk:
29958 case VMOVSHZrmkz:
29959 case VMOVSHZrr:
29960 case VMOVSHZrr_REV:
29961 case VMOVSHZrrk:
29962 case VMOVSHZrrk_REV:
29963 case VMOVSHZrrkz:
29964 case VMOVSHZrrkz_REV:
29965 return true;
29966 }
29967 return false;
29968}
29969
29970bool isPFSUBR(unsigned Opcode) {
29971 switch (Opcode) {
29972 case PFSUBRrm:
29973 case PFSUBRrr:
29974 return true;
29975 }
29976 return false;
29977}
29978
29979bool isRDSSPD(unsigned Opcode) {
29980 return Opcode == RDSSPD;
29981}
29982
29983bool isWAIT(unsigned Opcode) {
29984 return Opcode == WAIT;
29985}
29986
29987bool isVFPCLASSSS(unsigned Opcode) {
29988 switch (Opcode) {
29989 case VFPCLASSSSZmi:
29990 case VFPCLASSSSZmik:
29991 case VFPCLASSSSZri:
29992 case VFPCLASSSSZrik:
29993 return true;
29994 }
29995 return false;
29996}
29997
29998bool isPCMPGTD(unsigned Opcode) {
29999 switch (Opcode) {
30000 case MMX_PCMPGTDrm:
30001 case MMX_PCMPGTDrr:
30002 case PCMPGTDrm:
30003 case PCMPGTDrr:
30004 return true;
30005 }
30006 return false;
30007}
30008
30009bool isVGATHERPF0QPS(unsigned Opcode) {
30010 return Opcode == VGATHERPF0QPSm;
30011}
30012
30013bool isBLENDVPS(unsigned Opcode) {
30014 switch (Opcode) {
30015 case BLENDVPSrm0:
30016 case BLENDVPSrr0:
30017 return true;
30018 }
30019 return false;
30020}
30021
30022bool isVBROADCASTF32X4(unsigned Opcode) {
30023 switch (Opcode) {
30024 case VBROADCASTF32X4Z256rm:
30025 case VBROADCASTF32X4Z256rmk:
30026 case VBROADCASTF32X4Z256rmkz:
30027 case VBROADCASTF32X4Zrm:
30028 case VBROADCASTF32X4Zrmk:
30029 case VBROADCASTF32X4Zrmkz:
30030 return true;
30031 }
30032 return false;
30033}
30034
30035bool isVPMADD52LUQ(unsigned Opcode) {
30036 switch (Opcode) {
30037 case VPMADD52LUQYrm:
30038 case VPMADD52LUQYrr:
30039 case VPMADD52LUQZ128m:
30040 case VPMADD52LUQZ128mb:
30041 case VPMADD52LUQZ128mbk:
30042 case VPMADD52LUQZ128mbkz:
30043 case VPMADD52LUQZ128mk:
30044 case VPMADD52LUQZ128mkz:
30045 case VPMADD52LUQZ128r:
30046 case VPMADD52LUQZ128rk:
30047 case VPMADD52LUQZ128rkz:
30048 case VPMADD52LUQZ256m:
30049 case VPMADD52LUQZ256mb:
30050 case VPMADD52LUQZ256mbk:
30051 case VPMADD52LUQZ256mbkz:
30052 case VPMADD52LUQZ256mk:
30053 case VPMADD52LUQZ256mkz:
30054 case VPMADD52LUQZ256r:
30055 case VPMADD52LUQZ256rk:
30056 case VPMADD52LUQZ256rkz:
30057 case VPMADD52LUQZm:
30058 case VPMADD52LUQZmb:
30059 case VPMADD52LUQZmbk:
30060 case VPMADD52LUQZmbkz:
30061 case VPMADD52LUQZmk:
30062 case VPMADD52LUQZmkz:
30063 case VPMADD52LUQZr:
30064 case VPMADD52LUQZrk:
30065 case VPMADD52LUQZrkz:
30066 case VPMADD52LUQrm:
30067 case VPMADD52LUQrr:
30068 return true;
30069 }
30070 return false;
30071}
30072
30073bool isVMOVLPD(unsigned Opcode) {
30074 switch (Opcode) {
30075 case VMOVLPDZ128mr:
30076 case VMOVLPDZ128rm:
30077 case VMOVLPDmr:
30078 case VMOVLPDrm:
30079 return true;
30080 }
30081 return false;
30082}
30083
30084bool isVMOVQ(unsigned Opcode) {
30085 switch (Opcode) {
30086 case VMOV64toPQIZrm:
30087 case VMOV64toPQIZrr:
30088 case VMOV64toPQIrm:
30089 case VMOV64toPQIrr:
30090 case VMOVPQI2QIZmr:
30091 case VMOVPQI2QIZrr:
30092 case VMOVPQI2QImr:
30093 case VMOVPQI2QIrr:
30094 case VMOVPQIto64Zmr:
30095 case VMOVPQIto64Zrr:
30096 case VMOVPQIto64mr:
30097 case VMOVPQIto64rr:
30098 case VMOVQI2PQIZrm:
30099 case VMOVQI2PQIrm:
30100 case VMOVZPQILo2PQIZrr:
30101 case VMOVZPQILo2PQIrr:
30102 return true;
30103 }
30104 return false;
30105}
30106
30107bool isVMOVDQU(unsigned Opcode) {
30108 switch (Opcode) {
30109 case VMOVDQUYmr:
30110 case VMOVDQUYrm:
30111 case VMOVDQUYrr:
30112 case VMOVDQUYrr_REV:
30113 case VMOVDQUmr:
30114 case VMOVDQUrm:
30115 case VMOVDQUrr:
30116 case VMOVDQUrr_REV:
30117 return true;
30118 }
30119 return false;
30120}
30121
30122bool isAESENC128KL(unsigned Opcode) {
30123 return Opcode == AESENC128KL;
30124}
30125
30126bool isVFMADDSUB231PS(unsigned Opcode) {
30127 switch (Opcode) {
30128 case VFMADDSUB231PSYm:
30129 case VFMADDSUB231PSYr:
30130 case VFMADDSUB231PSZ128m:
30131 case VFMADDSUB231PSZ128mb:
30132 case VFMADDSUB231PSZ128mbk:
30133 case VFMADDSUB231PSZ128mbkz:
30134 case VFMADDSUB231PSZ128mk:
30135 case VFMADDSUB231PSZ128mkz:
30136 case VFMADDSUB231PSZ128r:
30137 case VFMADDSUB231PSZ128rk:
30138 case VFMADDSUB231PSZ128rkz:
30139 case VFMADDSUB231PSZ256m:
30140 case VFMADDSUB231PSZ256mb:
30141 case VFMADDSUB231PSZ256mbk:
30142 case VFMADDSUB231PSZ256mbkz:
30143 case VFMADDSUB231PSZ256mk:
30144 case VFMADDSUB231PSZ256mkz:
30145 case VFMADDSUB231PSZ256r:
30146 case VFMADDSUB231PSZ256rk:
30147 case VFMADDSUB231PSZ256rkz:
30148 case VFMADDSUB231PSZm:
30149 case VFMADDSUB231PSZmb:
30150 case VFMADDSUB231PSZmbk:
30151 case VFMADDSUB231PSZmbkz:
30152 case VFMADDSUB231PSZmk:
30153 case VFMADDSUB231PSZmkz:
30154 case VFMADDSUB231PSZr:
30155 case VFMADDSUB231PSZrb:
30156 case VFMADDSUB231PSZrbk:
30157 case VFMADDSUB231PSZrbkz:
30158 case VFMADDSUB231PSZrk:
30159 case VFMADDSUB231PSZrkz:
30160 case VFMADDSUB231PSm:
30161 case VFMADDSUB231PSr:
30162 return true;
30163 }
30164 return false;
30165}
30166
30167bool isVFNMSUB213PD(unsigned Opcode) {
30168 switch (Opcode) {
30169 case VFNMSUB213PDYm:
30170 case VFNMSUB213PDYr:
30171 case VFNMSUB213PDZ128m:
30172 case VFNMSUB213PDZ128mb:
30173 case VFNMSUB213PDZ128mbk:
30174 case VFNMSUB213PDZ128mbkz:
30175 case VFNMSUB213PDZ128mk:
30176 case VFNMSUB213PDZ128mkz:
30177 case VFNMSUB213PDZ128r:
30178 case VFNMSUB213PDZ128rk:
30179 case VFNMSUB213PDZ128rkz:
30180 case VFNMSUB213PDZ256m:
30181 case VFNMSUB213PDZ256mb:
30182 case VFNMSUB213PDZ256mbk:
30183 case VFNMSUB213PDZ256mbkz:
30184 case VFNMSUB213PDZ256mk:
30185 case VFNMSUB213PDZ256mkz:
30186 case VFNMSUB213PDZ256r:
30187 case VFNMSUB213PDZ256rk:
30188 case VFNMSUB213PDZ256rkz:
30189 case VFNMSUB213PDZm:
30190 case VFNMSUB213PDZmb:
30191 case VFNMSUB213PDZmbk:
30192 case VFNMSUB213PDZmbkz:
30193 case VFNMSUB213PDZmk:
30194 case VFNMSUB213PDZmkz:
30195 case VFNMSUB213PDZr:
30196 case VFNMSUB213PDZrb:
30197 case VFNMSUB213PDZrbk:
30198 case VFNMSUB213PDZrbkz:
30199 case VFNMSUB213PDZrk:
30200 case VFNMSUB213PDZrkz:
30201 case VFNMSUB213PDm:
30202 case VFNMSUB213PDr:
30203 return true;
30204 }
30205 return false;
30206}
30207
30208bool isVPCONFLICTD(unsigned Opcode) {
30209 switch (Opcode) {
30210 case VPCONFLICTDZ128rm:
30211 case VPCONFLICTDZ128rmb:
30212 case VPCONFLICTDZ128rmbk:
30213 case VPCONFLICTDZ128rmbkz:
30214 case VPCONFLICTDZ128rmk:
30215 case VPCONFLICTDZ128rmkz:
30216 case VPCONFLICTDZ128rr:
30217 case VPCONFLICTDZ128rrk:
30218 case VPCONFLICTDZ128rrkz:
30219 case VPCONFLICTDZ256rm:
30220 case VPCONFLICTDZ256rmb:
30221 case VPCONFLICTDZ256rmbk:
30222 case VPCONFLICTDZ256rmbkz:
30223 case VPCONFLICTDZ256rmk:
30224 case VPCONFLICTDZ256rmkz:
30225 case VPCONFLICTDZ256rr:
30226 case VPCONFLICTDZ256rrk:
30227 case VPCONFLICTDZ256rrkz:
30228 case VPCONFLICTDZrm:
30229 case VPCONFLICTDZrmb:
30230 case VPCONFLICTDZrmbk:
30231 case VPCONFLICTDZrmbkz:
30232 case VPCONFLICTDZrmk:
30233 case VPCONFLICTDZrmkz:
30234 case VPCONFLICTDZrr:
30235 case VPCONFLICTDZrrk:
30236 case VPCONFLICTDZrrkz:
30237 return true;
30238 }
30239 return false;
30240}
30241
30242bool isVFMADDSUB213PH(unsigned Opcode) {
30243 switch (Opcode) {
30244 case VFMADDSUB213PHZ128m:
30245 case VFMADDSUB213PHZ128mb:
30246 case VFMADDSUB213PHZ128mbk:
30247 case VFMADDSUB213PHZ128mbkz:
30248 case VFMADDSUB213PHZ128mk:
30249 case VFMADDSUB213PHZ128mkz:
30250 case VFMADDSUB213PHZ128r:
30251 case VFMADDSUB213PHZ128rk:
30252 case VFMADDSUB213PHZ128rkz:
30253 case VFMADDSUB213PHZ256m:
30254 case VFMADDSUB213PHZ256mb:
30255 case VFMADDSUB213PHZ256mbk:
30256 case VFMADDSUB213PHZ256mbkz:
30257 case VFMADDSUB213PHZ256mk:
30258 case VFMADDSUB213PHZ256mkz:
30259 case VFMADDSUB213PHZ256r:
30260 case VFMADDSUB213PHZ256rk:
30261 case VFMADDSUB213PHZ256rkz:
30262 case VFMADDSUB213PHZm:
30263 case VFMADDSUB213PHZmb:
30264 case VFMADDSUB213PHZmbk:
30265 case VFMADDSUB213PHZmbkz:
30266 case VFMADDSUB213PHZmk:
30267 case VFMADDSUB213PHZmkz:
30268 case VFMADDSUB213PHZr:
30269 case VFMADDSUB213PHZrb:
30270 case VFMADDSUB213PHZrbk:
30271 case VFMADDSUB213PHZrbkz:
30272 case VFMADDSUB213PHZrk:
30273 case VFMADDSUB213PHZrkz:
30274 return true;
30275 }
30276 return false;
30277}
30278
30279bool isVPHSUBSW(unsigned Opcode) {
30280 switch (Opcode) {
30281 case VPHSUBSWYrm:
30282 case VPHSUBSWYrr:
30283 case VPHSUBSWrm:
30284 case VPHSUBSWrr:
30285 return true;
30286 }
30287 return false;
30288}
30289
30290bool isPUNPCKHDQ(unsigned Opcode) {
30291 switch (Opcode) {
30292 case MMX_PUNPCKHDQrm:
30293 case MMX_PUNPCKHDQrr:
30294 case PUNPCKHDQrm:
30295 case PUNPCKHDQrr:
30296 return true;
30297 }
30298 return false;
30299}
30300
30301bool isVSHUFI64X2(unsigned Opcode) {
30302 switch (Opcode) {
30303 case VSHUFI64X2Z256rmbi:
30304 case VSHUFI64X2Z256rmbik:
30305 case VSHUFI64X2Z256rmbikz:
30306 case VSHUFI64X2Z256rmi:
30307 case VSHUFI64X2Z256rmik:
30308 case VSHUFI64X2Z256rmikz:
30309 case VSHUFI64X2Z256rri:
30310 case VSHUFI64X2Z256rrik:
30311 case VSHUFI64X2Z256rrikz:
30312 case VSHUFI64X2Zrmbi:
30313 case VSHUFI64X2Zrmbik:
30314 case VSHUFI64X2Zrmbikz:
30315 case VSHUFI64X2Zrmi:
30316 case VSHUFI64X2Zrmik:
30317 case VSHUFI64X2Zrmikz:
30318 case VSHUFI64X2Zrri:
30319 case VSHUFI64X2Zrrik:
30320 case VSHUFI64X2Zrrikz:
30321 return true;
30322 }
30323 return false;
30324}
30325
30326bool isVFMSUBSD(unsigned Opcode) {
30327 switch (Opcode) {
30328 case VFMSUBSD4mr:
30329 case VFMSUBSD4rm:
30330 case VFMSUBSD4rr:
30331 case VFMSUBSD4rr_REV:
30332 return true;
30333 }
30334 return false;
30335}
30336
30337bool isVPORD(unsigned Opcode) {
30338 switch (Opcode) {
30339 case VPORDZ128rm:
30340 case VPORDZ128rmb:
30341 case VPORDZ128rmbk:
30342 case VPORDZ128rmbkz:
30343 case VPORDZ128rmk:
30344 case VPORDZ128rmkz:
30345 case VPORDZ128rr:
30346 case VPORDZ128rrk:
30347 case VPORDZ128rrkz:
30348 case VPORDZ256rm:
30349 case VPORDZ256rmb:
30350 case VPORDZ256rmbk:
30351 case VPORDZ256rmbkz:
30352 case VPORDZ256rmk:
30353 case VPORDZ256rmkz:
30354 case VPORDZ256rr:
30355 case VPORDZ256rrk:
30356 case VPORDZ256rrkz:
30357 case VPORDZrm:
30358 case VPORDZrmb:
30359 case VPORDZrmbk:
30360 case VPORDZrmbkz:
30361 case VPORDZrmk:
30362 case VPORDZrmkz:
30363 case VPORDZrr:
30364 case VPORDZrrk:
30365 case VPORDZrrkz:
30366 return true;
30367 }
30368 return false;
30369}
30370
30371bool isRCPPS(unsigned Opcode) {
30372 switch (Opcode) {
30373 case RCPPSm:
30374 case RCPPSr:
30375 return true;
30376 }
30377 return false;
30378}
30379
30380bool isVEXTRACTI128(unsigned Opcode) {
30381 switch (Opcode) {
30382 case VEXTRACTI128mri:
30383 case VEXTRACTI128rri:
30384 return true;
30385 }
30386 return false;
30387}
30388
30389bool isVCVT2PH2BF8S(unsigned Opcode) {
30390 switch (Opcode) {
30391 case VCVT2PH2BF8SZ128rm:
30392 case VCVT2PH2BF8SZ128rmb:
30393 case VCVT2PH2BF8SZ128rmbk:
30394 case VCVT2PH2BF8SZ128rmbkz:
30395 case VCVT2PH2BF8SZ128rmk:
30396 case VCVT2PH2BF8SZ128rmkz:
30397 case VCVT2PH2BF8SZ128rr:
30398 case VCVT2PH2BF8SZ128rrk:
30399 case VCVT2PH2BF8SZ128rrkz:
30400 case VCVT2PH2BF8SZ256rm:
30401 case VCVT2PH2BF8SZ256rmb:
30402 case VCVT2PH2BF8SZ256rmbk:
30403 case VCVT2PH2BF8SZ256rmbkz:
30404 case VCVT2PH2BF8SZ256rmk:
30405 case VCVT2PH2BF8SZ256rmkz:
30406 case VCVT2PH2BF8SZ256rr:
30407 case VCVT2PH2BF8SZ256rrk:
30408 case VCVT2PH2BF8SZ256rrkz:
30409 case VCVT2PH2BF8SZrm:
30410 case VCVT2PH2BF8SZrmb:
30411 case VCVT2PH2BF8SZrmbk:
30412 case VCVT2PH2BF8SZrmbkz:
30413 case VCVT2PH2BF8SZrmk:
30414 case VCVT2PH2BF8SZrmkz:
30415 case VCVT2PH2BF8SZrr:
30416 case VCVT2PH2BF8SZrrk:
30417 case VCVT2PH2BF8SZrrkz:
30418 return true;
30419 }
30420 return false;
30421}
30422
30423bool isVPSHRDVW(unsigned Opcode) {
30424 switch (Opcode) {
30425 case VPSHRDVWZ128m:
30426 case VPSHRDVWZ128mk:
30427 case VPSHRDVWZ128mkz:
30428 case VPSHRDVWZ128r:
30429 case VPSHRDVWZ128rk:
30430 case VPSHRDVWZ128rkz:
30431 case VPSHRDVWZ256m:
30432 case VPSHRDVWZ256mk:
30433 case VPSHRDVWZ256mkz:
30434 case VPSHRDVWZ256r:
30435 case VPSHRDVWZ256rk:
30436 case VPSHRDVWZ256rkz:
30437 case VPSHRDVWZm:
30438 case VPSHRDVWZmk:
30439 case VPSHRDVWZmkz:
30440 case VPSHRDVWZr:
30441 case VPSHRDVWZrk:
30442 case VPSHRDVWZrkz:
30443 return true;
30444 }
30445 return false;
30446}
30447
30448bool isVUNPCKLPD(unsigned Opcode) {
30449 switch (Opcode) {
30450 case VUNPCKLPDYrm:
30451 case VUNPCKLPDYrr:
30452 case VUNPCKLPDZ128rm:
30453 case VUNPCKLPDZ128rmb:
30454 case VUNPCKLPDZ128rmbk:
30455 case VUNPCKLPDZ128rmbkz:
30456 case VUNPCKLPDZ128rmk:
30457 case VUNPCKLPDZ128rmkz:
30458 case VUNPCKLPDZ128rr:
30459 case VUNPCKLPDZ128rrk:
30460 case VUNPCKLPDZ128rrkz:
30461 case VUNPCKLPDZ256rm:
30462 case VUNPCKLPDZ256rmb:
30463 case VUNPCKLPDZ256rmbk:
30464 case VUNPCKLPDZ256rmbkz:
30465 case VUNPCKLPDZ256rmk:
30466 case VUNPCKLPDZ256rmkz:
30467 case VUNPCKLPDZ256rr:
30468 case VUNPCKLPDZ256rrk:
30469 case VUNPCKLPDZ256rrkz:
30470 case VUNPCKLPDZrm:
30471 case VUNPCKLPDZrmb:
30472 case VUNPCKLPDZrmbk:
30473 case VUNPCKLPDZrmbkz:
30474 case VUNPCKLPDZrmk:
30475 case VUNPCKLPDZrmkz:
30476 case VUNPCKLPDZrr:
30477 case VUNPCKLPDZrrk:
30478 case VUNPCKLPDZrrkz:
30479 case VUNPCKLPDrm:
30480 case VUNPCKLPDrr:
30481 return true;
30482 }
30483 return false;
30484}
30485
30486bool isVPSRAVD(unsigned Opcode) {
30487 switch (Opcode) {
30488 case VPSRAVDYrm:
30489 case VPSRAVDYrr:
30490 case VPSRAVDZ128rm:
30491 case VPSRAVDZ128rmb:
30492 case VPSRAVDZ128rmbk:
30493 case VPSRAVDZ128rmbkz:
30494 case VPSRAVDZ128rmk:
30495 case VPSRAVDZ128rmkz:
30496 case VPSRAVDZ128rr:
30497 case VPSRAVDZ128rrk:
30498 case VPSRAVDZ128rrkz:
30499 case VPSRAVDZ256rm:
30500 case VPSRAVDZ256rmb:
30501 case VPSRAVDZ256rmbk:
30502 case VPSRAVDZ256rmbkz:
30503 case VPSRAVDZ256rmk:
30504 case VPSRAVDZ256rmkz:
30505 case VPSRAVDZ256rr:
30506 case VPSRAVDZ256rrk:
30507 case VPSRAVDZ256rrkz:
30508 case VPSRAVDZrm:
30509 case VPSRAVDZrmb:
30510 case VPSRAVDZrmbk:
30511 case VPSRAVDZrmbkz:
30512 case VPSRAVDZrmk:
30513 case VPSRAVDZrmkz:
30514 case VPSRAVDZrr:
30515 case VPSRAVDZrrk:
30516 case VPSRAVDZrrkz:
30517 case VPSRAVDrm:
30518 case VPSRAVDrr:
30519 return true;
30520 }
30521 return false;
30522}
30523
30524bool isVMULSH(unsigned Opcode) {
30525 switch (Opcode) {
30526 case VMULSHZrm_Int:
30527 case VMULSHZrmk_Int:
30528 case VMULSHZrmkz_Int:
30529 case VMULSHZrr_Int:
30530 case VMULSHZrrb_Int:
30531 case VMULSHZrrbk_Int:
30532 case VMULSHZrrbkz_Int:
30533 case VMULSHZrrk_Int:
30534 case VMULSHZrrkz_Int:
30535 return true;
30536 }
30537 return false;
30538}
30539
30540bool isMOVNTSS(unsigned Opcode) {
30541 return Opcode == MOVNTSS;
30542}
30543
30544bool isSTI(unsigned Opcode) {
30545 return Opcode == STI;
30546}
30547
30548bool isVSM4RNDS4(unsigned Opcode) {
30549 switch (Opcode) {
30550 case VSM4RNDS4Yrm:
30551 case VSM4RNDS4Yrr:
30552 case VSM4RNDS4Z128rm:
30553 case VSM4RNDS4Z128rr:
30554 case VSM4RNDS4Z256rm:
30555 case VSM4RNDS4Z256rr:
30556 case VSM4RNDS4Zrm:
30557 case VSM4RNDS4Zrr:
30558 case VSM4RNDS4rm:
30559 case VSM4RNDS4rr:
30560 return true;
30561 }
30562 return false;
30563}
30564
30565bool isVMCLEAR(unsigned Opcode) {
30566 return Opcode == VMCLEARm;
30567}
30568
30569bool isVPMADD52HUQ(unsigned Opcode) {
30570 switch (Opcode) {
30571 case VPMADD52HUQYrm:
30572 case VPMADD52HUQYrr:
30573 case VPMADD52HUQZ128m:
30574 case VPMADD52HUQZ128mb:
30575 case VPMADD52HUQZ128mbk:
30576 case VPMADD52HUQZ128mbkz:
30577 case VPMADD52HUQZ128mk:
30578 case VPMADD52HUQZ128mkz:
30579 case VPMADD52HUQZ128r:
30580 case VPMADD52HUQZ128rk:
30581 case VPMADD52HUQZ128rkz:
30582 case VPMADD52HUQZ256m:
30583 case VPMADD52HUQZ256mb:
30584 case VPMADD52HUQZ256mbk:
30585 case VPMADD52HUQZ256mbkz:
30586 case VPMADD52HUQZ256mk:
30587 case VPMADD52HUQZ256mkz:
30588 case VPMADD52HUQZ256r:
30589 case VPMADD52HUQZ256rk:
30590 case VPMADD52HUQZ256rkz:
30591 case VPMADD52HUQZm:
30592 case VPMADD52HUQZmb:
30593 case VPMADD52HUQZmbk:
30594 case VPMADD52HUQZmbkz:
30595 case VPMADD52HUQZmk:
30596 case VPMADD52HUQZmkz:
30597 case VPMADD52HUQZr:
30598 case VPMADD52HUQZrk:
30599 case VPMADD52HUQZrkz:
30600 case VPMADD52HUQrm:
30601 case VPMADD52HUQrr:
30602 return true;
30603 }
30604 return false;
30605}
30606
30607bool isLIDT(unsigned Opcode) {
30608 return Opcode == LIDT64m;
30609}
30610
30611bool isPUSH2(unsigned Opcode) {
30612 return Opcode == PUSH2;
30613}
30614
30615bool isVCVTPS2IUBS(unsigned Opcode) {
30616 switch (Opcode) {
30617 case VCVTPS2IUBSZ128rm:
30618 case VCVTPS2IUBSZ128rmb:
30619 case VCVTPS2IUBSZ128rmbk:
30620 case VCVTPS2IUBSZ128rmbkz:
30621 case VCVTPS2IUBSZ128rmk:
30622 case VCVTPS2IUBSZ128rmkz:
30623 case VCVTPS2IUBSZ128rr:
30624 case VCVTPS2IUBSZ128rrk:
30625 case VCVTPS2IUBSZ128rrkz:
30626 case VCVTPS2IUBSZ256rm:
30627 case VCVTPS2IUBSZ256rmb:
30628 case VCVTPS2IUBSZ256rmbk:
30629 case VCVTPS2IUBSZ256rmbkz:
30630 case VCVTPS2IUBSZ256rmk:
30631 case VCVTPS2IUBSZ256rmkz:
30632 case VCVTPS2IUBSZ256rr:
30633 case VCVTPS2IUBSZ256rrk:
30634 case VCVTPS2IUBSZ256rrkz:
30635 case VCVTPS2IUBSZrm:
30636 case VCVTPS2IUBSZrmb:
30637 case VCVTPS2IUBSZrmbk:
30638 case VCVTPS2IUBSZrmbkz:
30639 case VCVTPS2IUBSZrmk:
30640 case VCVTPS2IUBSZrmkz:
30641 case VCVTPS2IUBSZrr:
30642 case VCVTPS2IUBSZrrb:
30643 case VCVTPS2IUBSZrrbk:
30644 case VCVTPS2IUBSZrrbkz:
30645 case VCVTPS2IUBSZrrk:
30646 case VCVTPS2IUBSZrrkz:
30647 return true;
30648 }
30649 return false;
30650}
30651
30652bool isRDPKRU(unsigned Opcode) {
30653 return Opcode == RDPKRUr;
30654}
30655
30656bool isVPCMPB(unsigned Opcode) {
30657 switch (Opcode) {
30658 case VPCMPBZ128rmi:
30659 case VPCMPBZ128rmik:
30660 case VPCMPBZ128rri:
30661 case VPCMPBZ128rrik:
30662 case VPCMPBZ256rmi:
30663 case VPCMPBZ256rmik:
30664 case VPCMPBZ256rri:
30665 case VPCMPBZ256rrik:
30666 case VPCMPBZrmi:
30667 case VPCMPBZrmik:
30668 case VPCMPBZrri:
30669 case VPCMPBZrrik:
30670 return true;
30671 }
30672 return false;
30673}
30674
30675bool isVFMSUB231BF16(unsigned Opcode) {
30676 switch (Opcode) {
30677 case VFMSUB231BF16Z128m:
30678 case VFMSUB231BF16Z128mb:
30679 case VFMSUB231BF16Z128mbk:
30680 case VFMSUB231BF16Z128mbkz:
30681 case VFMSUB231BF16Z128mk:
30682 case VFMSUB231BF16Z128mkz:
30683 case VFMSUB231BF16Z128r:
30684 case VFMSUB231BF16Z128rk:
30685 case VFMSUB231BF16Z128rkz:
30686 case VFMSUB231BF16Z256m:
30687 case VFMSUB231BF16Z256mb:
30688 case VFMSUB231BF16Z256mbk:
30689 case VFMSUB231BF16Z256mbkz:
30690 case VFMSUB231BF16Z256mk:
30691 case VFMSUB231BF16Z256mkz:
30692 case VFMSUB231BF16Z256r:
30693 case VFMSUB231BF16Z256rk:
30694 case VFMSUB231BF16Z256rkz:
30695 case VFMSUB231BF16Zm:
30696 case VFMSUB231BF16Zmb:
30697 case VFMSUB231BF16Zmbk:
30698 case VFMSUB231BF16Zmbkz:
30699 case VFMSUB231BF16Zmk:
30700 case VFMSUB231BF16Zmkz:
30701 case VFMSUB231BF16Zr:
30702 case VFMSUB231BF16Zrk:
30703 case VFMSUB231BF16Zrkz:
30704 return true;
30705 }
30706 return false;
30707}
30708
30709bool isFINCSTP(unsigned Opcode) {
30710 return Opcode == FINCSTP;
30711}
30712
30713bool isKORQ(unsigned Opcode) {
30714 return Opcode == KORQkk;
30715}
30716
30717bool isXCRYPTCBC(unsigned Opcode) {
30718 return Opcode == XCRYPTCBC;
30719}
30720
30721bool isRDPMC(unsigned Opcode) {
30722 return Opcode == RDPMC;
30723}
30724
30725bool isMOVMSKPD(unsigned Opcode) {
30726 return Opcode == MOVMSKPDrr;
30727}
30728
30729bool isVFMSUB231SH(unsigned Opcode) {
30730 switch (Opcode) {
30731 case VFMSUB231SHZm_Int:
30732 case VFMSUB231SHZmk_Int:
30733 case VFMSUB231SHZmkz_Int:
30734 case VFMSUB231SHZr_Int:
30735 case VFMSUB231SHZrb_Int:
30736 case VFMSUB231SHZrbk_Int:
30737 case VFMSUB231SHZrbkz_Int:
30738 case VFMSUB231SHZrk_Int:
30739 case VFMSUB231SHZrkz_Int:
30740 return true;
30741 }
30742 return false;
30743}
30744
30745bool isVEXTRACTF128(unsigned Opcode) {
30746 switch (Opcode) {
30747 case VEXTRACTF128mri:
30748 case VEXTRACTF128rri:
30749 return true;
30750 }
30751 return false;
30752}
30753
30754bool isVPSHLB(unsigned Opcode) {
30755 switch (Opcode) {
30756 case VPSHLBmr:
30757 case VPSHLBrm:
30758 case VPSHLBrr:
30759 case VPSHLBrr_REV:
30760 return true;
30761 }
30762 return false;
30763}
30764
30765bool isXSAVES64(unsigned Opcode) {
30766 return Opcode == XSAVES64;
30767}
30768
30769bool isSHL(unsigned Opcode) {
30770 switch (Opcode) {
30771 case SHL16m1:
30772 case SHL16m1_EVEX:
30773 case SHL16m1_ND:
30774 case SHL16m1_NF:
30775 case SHL16m1_NF_ND:
30776 case SHL16mCL:
30777 case SHL16mCL_EVEX:
30778 case SHL16mCL_ND:
30779 case SHL16mCL_NF:
30780 case SHL16mCL_NF_ND:
30781 case SHL16mi:
30782 case SHL16mi_EVEX:
30783 case SHL16mi_ND:
30784 case SHL16mi_NF:
30785 case SHL16mi_NF_ND:
30786 case SHL16r1:
30787 case SHL16r1_EVEX:
30788 case SHL16r1_ND:
30789 case SHL16r1_NF:
30790 case SHL16r1_NF_ND:
30791 case SHL16rCL:
30792 case SHL16rCL_EVEX:
30793 case SHL16rCL_ND:
30794 case SHL16rCL_NF:
30795 case SHL16rCL_NF_ND:
30796 case SHL16ri:
30797 case SHL16ri_EVEX:
30798 case SHL16ri_ND:
30799 case SHL16ri_NF:
30800 case SHL16ri_NF_ND:
30801 case SHL32m1:
30802 case SHL32m1_EVEX:
30803 case SHL32m1_ND:
30804 case SHL32m1_NF:
30805 case SHL32m1_NF_ND:
30806 case SHL32mCL:
30807 case SHL32mCL_EVEX:
30808 case SHL32mCL_ND:
30809 case SHL32mCL_NF:
30810 case SHL32mCL_NF_ND:
30811 case SHL32mi:
30812 case SHL32mi_EVEX:
30813 case SHL32mi_ND:
30814 case SHL32mi_NF:
30815 case SHL32mi_NF_ND:
30816 case SHL32r1:
30817 case SHL32r1_EVEX:
30818 case SHL32r1_ND:
30819 case SHL32r1_NF:
30820 case SHL32r1_NF_ND:
30821 case SHL32rCL:
30822 case SHL32rCL_EVEX:
30823 case SHL32rCL_ND:
30824 case SHL32rCL_NF:
30825 case SHL32rCL_NF_ND:
30826 case SHL32ri:
30827 case SHL32ri_EVEX:
30828 case SHL32ri_ND:
30829 case SHL32ri_NF:
30830 case SHL32ri_NF_ND:
30831 case SHL64m1:
30832 case SHL64m1_EVEX:
30833 case SHL64m1_ND:
30834 case SHL64m1_NF:
30835 case SHL64m1_NF_ND:
30836 case SHL64mCL:
30837 case SHL64mCL_EVEX:
30838 case SHL64mCL_ND:
30839 case SHL64mCL_NF:
30840 case SHL64mCL_NF_ND:
30841 case SHL64mi:
30842 case SHL64mi_EVEX:
30843 case SHL64mi_ND:
30844 case SHL64mi_NF:
30845 case SHL64mi_NF_ND:
30846 case SHL64r1:
30847 case SHL64r1_EVEX:
30848 case SHL64r1_ND:
30849 case SHL64r1_NF:
30850 case SHL64r1_NF_ND:
30851 case SHL64rCL:
30852 case SHL64rCL_EVEX:
30853 case SHL64rCL_ND:
30854 case SHL64rCL_NF:
30855 case SHL64rCL_NF_ND:
30856 case SHL64ri:
30857 case SHL64ri_EVEX:
30858 case SHL64ri_ND:
30859 case SHL64ri_NF:
30860 case SHL64ri_NF_ND:
30861 case SHL8m1:
30862 case SHL8m1_EVEX:
30863 case SHL8m1_ND:
30864 case SHL8m1_NF:
30865 case SHL8m1_NF_ND:
30866 case SHL8mCL:
30867 case SHL8mCL_EVEX:
30868 case SHL8mCL_ND:
30869 case SHL8mCL_NF:
30870 case SHL8mCL_NF_ND:
30871 case SHL8mi:
30872 case SHL8mi_EVEX:
30873 case SHL8mi_ND:
30874 case SHL8mi_NF:
30875 case SHL8mi_NF_ND:
30876 case SHL8r1:
30877 case SHL8r1_EVEX:
30878 case SHL8r1_ND:
30879 case SHL8r1_NF:
30880 case SHL8r1_NF_ND:
30881 case SHL8rCL:
30882 case SHL8rCL_EVEX:
30883 case SHL8rCL_ND:
30884 case SHL8rCL_NF:
30885 case SHL8rCL_NF_ND:
30886 case SHL8ri:
30887 case SHL8ri_EVEX:
30888 case SHL8ri_ND:
30889 case SHL8ri_NF:
30890 case SHL8ri_NF_ND:
30891 return true;
30892 }
30893 return false;
30894}
30895
30896bool isAXOR(unsigned Opcode) {
30897 switch (Opcode) {
30898 case AXOR32mr:
30899 case AXOR32mr_EVEX:
30900 case AXOR64mr:
30901 case AXOR64mr_EVEX:
30902 return true;
30903 }
30904 return false;
30905}
30906
30907bool isVINSERTI64X2(unsigned Opcode) {
30908 switch (Opcode) {
30909 case VINSERTI64X2Z256rmi:
30910 case VINSERTI64X2Z256rmik:
30911 case VINSERTI64X2Z256rmikz:
30912 case VINSERTI64X2Z256rri:
30913 case VINSERTI64X2Z256rrik:
30914 case VINSERTI64X2Z256rrikz:
30915 case VINSERTI64X2Zrmi:
30916 case VINSERTI64X2Zrmik:
30917 case VINSERTI64X2Zrmikz:
30918 case VINSERTI64X2Zrri:
30919 case VINSERTI64X2Zrrik:
30920 case VINSERTI64X2Zrrikz:
30921 return true;
30922 }
30923 return false;
30924}
30925
30926bool isSYSRETQ(unsigned Opcode) {
30927 return Opcode == SYSRET64;
30928}
30929
30930bool isVSCATTERPF0QPD(unsigned Opcode) {
30931 return Opcode == VSCATTERPF0QPDm;
30932}
30933
30934bool isVFMSUB213SH(unsigned Opcode) {
30935 switch (Opcode) {
30936 case VFMSUB213SHZm_Int:
30937 case VFMSUB213SHZmk_Int:
30938 case VFMSUB213SHZmkz_Int:
30939 case VFMSUB213SHZr_Int:
30940 case VFMSUB213SHZrb_Int:
30941 case VFMSUB213SHZrbk_Int:
30942 case VFMSUB213SHZrbkz_Int:
30943 case VFMSUB213SHZrk_Int:
30944 case VFMSUB213SHZrkz_Int:
30945 return true;
30946 }
30947 return false;
30948}
30949
30950bool isVPMOVQW(unsigned Opcode) {
30951 switch (Opcode) {
30952 case VPMOVQWZ128mr:
30953 case VPMOVQWZ128mrk:
30954 case VPMOVQWZ128rr:
30955 case VPMOVQWZ128rrk:
30956 case VPMOVQWZ128rrkz:
30957 case VPMOVQWZ256mr:
30958 case VPMOVQWZ256mrk:
30959 case VPMOVQWZ256rr:
30960 case VPMOVQWZ256rrk:
30961 case VPMOVQWZ256rrkz:
30962 case VPMOVQWZmr:
30963 case VPMOVQWZmrk:
30964 case VPMOVQWZrr:
30965 case VPMOVQWZrrk:
30966 case VPMOVQWZrrkz:
30967 return true;
30968 }
30969 return false;
30970}
30971
30972bool isVREDUCEPD(unsigned Opcode) {
30973 switch (Opcode) {
30974 case VREDUCEPDZ128rmbi:
30975 case VREDUCEPDZ128rmbik:
30976 case VREDUCEPDZ128rmbikz:
30977 case VREDUCEPDZ128rmi:
30978 case VREDUCEPDZ128rmik:
30979 case VREDUCEPDZ128rmikz:
30980 case VREDUCEPDZ128rri:
30981 case VREDUCEPDZ128rrik:
30982 case VREDUCEPDZ128rrikz:
30983 case VREDUCEPDZ256rmbi:
30984 case VREDUCEPDZ256rmbik:
30985 case VREDUCEPDZ256rmbikz:
30986 case VREDUCEPDZ256rmi:
30987 case VREDUCEPDZ256rmik:
30988 case VREDUCEPDZ256rmikz:
30989 case VREDUCEPDZ256rri:
30990 case VREDUCEPDZ256rrik:
30991 case VREDUCEPDZ256rrikz:
30992 case VREDUCEPDZrmbi:
30993 case VREDUCEPDZrmbik:
30994 case VREDUCEPDZrmbikz:
30995 case VREDUCEPDZrmi:
30996 case VREDUCEPDZrmik:
30997 case VREDUCEPDZrmikz:
30998 case VREDUCEPDZrri:
30999 case VREDUCEPDZrrib:
31000 case VREDUCEPDZrribk:
31001 case VREDUCEPDZrribkz:
31002 case VREDUCEPDZrrik:
31003 case VREDUCEPDZrrikz:
31004 return true;
31005 }
31006 return false;
31007}
31008
31009bool isNOT(unsigned Opcode) {
31010 switch (Opcode) {
31011 case NOT16m:
31012 case NOT16m_EVEX:
31013 case NOT16m_ND:
31014 case NOT16r:
31015 case NOT16r_EVEX:
31016 case NOT16r_ND:
31017 case NOT32m:
31018 case NOT32m_EVEX:
31019 case NOT32m_ND:
31020 case NOT32r:
31021 case NOT32r_EVEX:
31022 case NOT32r_ND:
31023 case NOT64m:
31024 case NOT64m_EVEX:
31025 case NOT64m_ND:
31026 case NOT64r:
31027 case NOT64r_EVEX:
31028 case NOT64r_ND:
31029 case NOT8m:
31030 case NOT8m_EVEX:
31031 case NOT8m_ND:
31032 case NOT8r:
31033 case NOT8r_EVEX:
31034 case NOT8r_ND:
31035 return true;
31036 }
31037 return false;
31038}
31039
31040bool isLWPINS(unsigned Opcode) {
31041 switch (Opcode) {
31042 case LWPINS32rmi:
31043 case LWPINS32rri:
31044 case LWPINS64rmi:
31045 case LWPINS64rri:
31046 return true;
31047 }
31048 return false;
31049}
31050
31051bool isVSCATTERDPS(unsigned Opcode) {
31052 switch (Opcode) {
31053 case VSCATTERDPSZ128mr:
31054 case VSCATTERDPSZ256mr:
31055 case VSCATTERDPSZmr:
31056 return true;
31057 }
31058 return false;
31059}
31060
31061bool isVPMOVM2W(unsigned Opcode) {
31062 switch (Opcode) {
31063 case VPMOVM2WZ128rk:
31064 case VPMOVM2WZ256rk:
31065 case VPMOVM2WZrk:
31066 return true;
31067 }
31068 return false;
31069}
31070
31071bool isVFNMADD132PS(unsigned Opcode) {
31072 switch (Opcode) {
31073 case VFNMADD132PSYm:
31074 case VFNMADD132PSYr:
31075 case VFNMADD132PSZ128m:
31076 case VFNMADD132PSZ128mb:
31077 case VFNMADD132PSZ128mbk:
31078 case VFNMADD132PSZ128mbkz:
31079 case VFNMADD132PSZ128mk:
31080 case VFNMADD132PSZ128mkz:
31081 case VFNMADD132PSZ128r:
31082 case VFNMADD132PSZ128rk:
31083 case VFNMADD132PSZ128rkz:
31084 case VFNMADD132PSZ256m:
31085 case VFNMADD132PSZ256mb:
31086 case VFNMADD132PSZ256mbk:
31087 case VFNMADD132PSZ256mbkz:
31088 case VFNMADD132PSZ256mk:
31089 case VFNMADD132PSZ256mkz:
31090 case VFNMADD132PSZ256r:
31091 case VFNMADD132PSZ256rk:
31092 case VFNMADD132PSZ256rkz:
31093 case VFNMADD132PSZm:
31094 case VFNMADD132PSZmb:
31095 case VFNMADD132PSZmbk:
31096 case VFNMADD132PSZmbkz:
31097 case VFNMADD132PSZmk:
31098 case VFNMADD132PSZmkz:
31099 case VFNMADD132PSZr:
31100 case VFNMADD132PSZrb:
31101 case VFNMADD132PSZrbk:
31102 case VFNMADD132PSZrbkz:
31103 case VFNMADD132PSZrk:
31104 case VFNMADD132PSZrkz:
31105 case VFNMADD132PSm:
31106 case VFNMADD132PSr:
31107 return true;
31108 }
31109 return false;
31110}
31111
31112bool isMOVNTPS(unsigned Opcode) {
31113 return Opcode == MOVNTPSmr;
31114}
31115
31116bool isVRSQRTSS(unsigned Opcode) {
31117 switch (Opcode) {
31118 case VRSQRTSSm_Int:
31119 case VRSQRTSSr_Int:
31120 return true;
31121 }
31122 return false;
31123}
31124
31125bool isKMOVB(unsigned Opcode) {
31126 switch (Opcode) {
31127 case KMOVBkk:
31128 case KMOVBkk_EVEX:
31129 case KMOVBkm:
31130 case KMOVBkm_EVEX:
31131 case KMOVBkr:
31132 case KMOVBkr_EVEX:
31133 case KMOVBmk:
31134 case KMOVBmk_EVEX:
31135 case KMOVBrk:
31136 case KMOVBrk_EVEX:
31137 return true;
31138 }
31139 return false;
31140}
31141
31142bool isCVTSD2SS(unsigned Opcode) {
31143 switch (Opcode) {
31144 case CVTSD2SSrm_Int:
31145 case CVTSD2SSrr_Int:
31146 return true;
31147 }
31148 return false;
31149}
31150
31151bool isVBROADCASTF64X2(unsigned Opcode) {
31152 switch (Opcode) {
31153 case VBROADCASTF64X2Z256rm:
31154 case VBROADCASTF64X2Z256rmk:
31155 case VBROADCASTF64X2Z256rmkz:
31156 case VBROADCASTF64X2Zrm:
31157 case VBROADCASTF64X2Zrmk:
31158 case VBROADCASTF64X2Zrmkz:
31159 return true;
31160 }
31161 return false;
31162}
31163
31164bool isMOVNTPD(unsigned Opcode) {
31165 return Opcode == MOVNTPDmr;
31166}
31167
31168bool isMAXSD(unsigned Opcode) {
31169 switch (Opcode) {
31170 case MAXSDrm_Int:
31171 case MAXSDrr_Int:
31172 return true;
31173 }
31174 return false;
31175}
31176
31177bool isCMPPD(unsigned Opcode) {
31178 switch (Opcode) {
31179 case CMPPDrmi:
31180 case CMPPDrri:
31181 return true;
31182 }
31183 return false;
31184}
31185
31186bool isVPCMPESTRM(unsigned Opcode) {
31187 switch (Opcode) {
31188 case VPCMPESTRMrmi:
31189 case VPCMPESTRMrri:
31190 return true;
31191 }
31192 return false;
31193}
31194
31195bool isVFMSUB132PS(unsigned Opcode) {
31196 switch (Opcode) {
31197 case VFMSUB132PSYm:
31198 case VFMSUB132PSYr:
31199 case VFMSUB132PSZ128m:
31200 case VFMSUB132PSZ128mb:
31201 case VFMSUB132PSZ128mbk:
31202 case VFMSUB132PSZ128mbkz:
31203 case VFMSUB132PSZ128mk:
31204 case VFMSUB132PSZ128mkz:
31205 case VFMSUB132PSZ128r:
31206 case VFMSUB132PSZ128rk:
31207 case VFMSUB132PSZ128rkz:
31208 case VFMSUB132PSZ256m:
31209 case VFMSUB132PSZ256mb:
31210 case VFMSUB132PSZ256mbk:
31211 case VFMSUB132PSZ256mbkz:
31212 case VFMSUB132PSZ256mk:
31213 case VFMSUB132PSZ256mkz:
31214 case VFMSUB132PSZ256r:
31215 case VFMSUB132PSZ256rk:
31216 case VFMSUB132PSZ256rkz:
31217 case VFMSUB132PSZm:
31218 case VFMSUB132PSZmb:
31219 case VFMSUB132PSZmbk:
31220 case VFMSUB132PSZmbkz:
31221 case VFMSUB132PSZmk:
31222 case VFMSUB132PSZmkz:
31223 case VFMSUB132PSZr:
31224 case VFMSUB132PSZrb:
31225 case VFMSUB132PSZrbk:
31226 case VFMSUB132PSZrbkz:
31227 case VFMSUB132PSZrk:
31228 case VFMSUB132PSZrkz:
31229 case VFMSUB132PSm:
31230 case VFMSUB132PSr:
31231 return true;
31232 }
31233 return false;
31234}
31235
31236bool isVCOMISH(unsigned Opcode) {
31237 switch (Opcode) {
31238 case VCOMISHZrm:
31239 case VCOMISHZrr:
31240 case VCOMISHZrrb:
31241 return true;
31242 }
31243 return false;
31244}
31245
31246bool isF2XM1(unsigned Opcode) {
31247 return Opcode == F2XM1;
31248}
31249
31250bool isVDIVBF16(unsigned Opcode) {
31251 switch (Opcode) {
31252 case VDIVBF16Z128rm:
31253 case VDIVBF16Z128rmb:
31254 case VDIVBF16Z128rmbk:
31255 case VDIVBF16Z128rmbkz:
31256 case VDIVBF16Z128rmk:
31257 case VDIVBF16Z128rmkz:
31258 case VDIVBF16Z128rr:
31259 case VDIVBF16Z128rrk:
31260 case VDIVBF16Z128rrkz:
31261 case VDIVBF16Z256rm:
31262 case VDIVBF16Z256rmb:
31263 case VDIVBF16Z256rmbk:
31264 case VDIVBF16Z256rmbkz:
31265 case VDIVBF16Z256rmk:
31266 case VDIVBF16Z256rmkz:
31267 case VDIVBF16Z256rr:
31268 case VDIVBF16Z256rrk:
31269 case VDIVBF16Z256rrkz:
31270 case VDIVBF16Zrm:
31271 case VDIVBF16Zrmb:
31272 case VDIVBF16Zrmbk:
31273 case VDIVBF16Zrmbkz:
31274 case VDIVBF16Zrmk:
31275 case VDIVBF16Zrmkz:
31276 case VDIVBF16Zrr:
31277 case VDIVBF16Zrrk:
31278 case VDIVBF16Zrrkz:
31279 return true;
31280 }
31281 return false;
31282}
31283
31284bool isSQRTPD(unsigned Opcode) {
31285 switch (Opcode) {
31286 case SQRTPDm:
31287 case SQRTPDr:
31288 return true;
31289 }
31290 return false;
31291}
31292
31293bool isVFMSUBADDPS(unsigned Opcode) {
31294 switch (Opcode) {
31295 case VFMSUBADDPS4Ymr:
31296 case VFMSUBADDPS4Yrm:
31297 case VFMSUBADDPS4Yrr:
31298 case VFMSUBADDPS4Yrr_REV:
31299 case VFMSUBADDPS4mr:
31300 case VFMSUBADDPS4rm:
31301 case VFMSUBADDPS4rr:
31302 case VFMSUBADDPS4rr_REV:
31303 return true;
31304 }
31305 return false;
31306}
31307
31308bool isFXTRACT(unsigned Opcode) {
31309 return Opcode == FXTRACT;
31310}
31311
31312bool isVP4DPWSSD(unsigned Opcode) {
31313 switch (Opcode) {
31314 case VP4DPWSSDrm:
31315 case VP4DPWSSDrmk:
31316 case VP4DPWSSDrmkz:
31317 return true;
31318 }
31319 return false;
31320}
31321
31322bool isTDPBHF8PS(unsigned Opcode) {
31323 return Opcode == TDPBHF8PS;
31324}
31325
31326bool isVFMSUBADDPD(unsigned Opcode) {
31327 switch (Opcode) {
31328 case VFMSUBADDPD4Ymr:
31329 case VFMSUBADDPD4Yrm:
31330 case VFMSUBADDPD4Yrr:
31331 case VFMSUBADDPD4Yrr_REV:
31332 case VFMSUBADDPD4mr:
31333 case VFMSUBADDPD4rm:
31334 case VFMSUBADDPD4rr:
31335 case VFMSUBADDPD4rr_REV:
31336 return true;
31337 }
31338 return false;
31339}
31340
31341bool isVBCSTNEBF162PS(unsigned Opcode) {
31342 switch (Opcode) {
31343 case VBCSTNEBF162PSYrm:
31344 case VBCSTNEBF162PSrm:
31345 return true;
31346 }
31347 return false;
31348}
31349
31350bool isVPGATHERQQ(unsigned Opcode) {
31351 switch (Opcode) {
31352 case VPGATHERQQYrm:
31353 case VPGATHERQQZ128rm:
31354 case VPGATHERQQZ256rm:
31355 case VPGATHERQQZrm:
31356 case VPGATHERQQrm:
31357 return true;
31358 }
31359 return false;
31360}
31361
31362bool isPCMPEQB(unsigned Opcode) {
31363 switch (Opcode) {
31364 case MMX_PCMPEQBrm:
31365 case MMX_PCMPEQBrr:
31366 case PCMPEQBrm:
31367 case PCMPEQBrr:
31368 return true;
31369 }
31370 return false;
31371}
31372
31373bool isTILESTORED(unsigned Opcode) {
31374 switch (Opcode) {
31375 case TILESTORED:
31376 case TILESTORED_EVEX:
31377 return true;
31378 }
31379 return false;
31380}
31381
31382bool isBLSMSK(unsigned Opcode) {
31383 switch (Opcode) {
31384 case BLSMSK32rm:
31385 case BLSMSK32rm_EVEX:
31386 case BLSMSK32rm_NF:
31387 case BLSMSK32rr:
31388 case BLSMSK32rr_EVEX:
31389 case BLSMSK32rr_NF:
31390 case BLSMSK64rm:
31391 case BLSMSK64rm_EVEX:
31392 case BLSMSK64rm_NF:
31393 case BLSMSK64rr:
31394 case BLSMSK64rr_EVEX:
31395 case BLSMSK64rr_NF:
31396 return true;
31397 }
31398 return false;
31399}
31400
31401bool isVCVTTPS2DQ(unsigned Opcode) {
31402 switch (Opcode) {
31403 case VCVTTPS2DQYrm:
31404 case VCVTTPS2DQYrr:
31405 case VCVTTPS2DQZ128rm:
31406 case VCVTTPS2DQZ128rmb:
31407 case VCVTTPS2DQZ128rmbk:
31408 case VCVTTPS2DQZ128rmbkz:
31409 case VCVTTPS2DQZ128rmk:
31410 case VCVTTPS2DQZ128rmkz:
31411 case VCVTTPS2DQZ128rr:
31412 case VCVTTPS2DQZ128rrk:
31413 case VCVTTPS2DQZ128rrkz:
31414 case VCVTTPS2DQZ256rm:
31415 case VCVTTPS2DQZ256rmb:
31416 case VCVTTPS2DQZ256rmbk:
31417 case VCVTTPS2DQZ256rmbkz:
31418 case VCVTTPS2DQZ256rmk:
31419 case VCVTTPS2DQZ256rmkz:
31420 case VCVTTPS2DQZ256rr:
31421 case VCVTTPS2DQZ256rrk:
31422 case VCVTTPS2DQZ256rrkz:
31423 case VCVTTPS2DQZrm:
31424 case VCVTTPS2DQZrmb:
31425 case VCVTTPS2DQZrmbk:
31426 case VCVTTPS2DQZrmbkz:
31427 case VCVTTPS2DQZrmk:
31428 case VCVTTPS2DQZrmkz:
31429 case VCVTTPS2DQZrr:
31430 case VCVTTPS2DQZrrb:
31431 case VCVTTPS2DQZrrbk:
31432 case VCVTTPS2DQZrrbkz:
31433 case VCVTTPS2DQZrrk:
31434 case VCVTTPS2DQZrrkz:
31435 case VCVTTPS2DQrm:
31436 case VCVTTPS2DQrr:
31437 return true;
31438 }
31439 return false;
31440}
31441
31442bool isVRNDSCALEPD(unsigned Opcode) {
31443 switch (Opcode) {
31444 case VRNDSCALEPDZ128rmbi:
31445 case VRNDSCALEPDZ128rmbik:
31446 case VRNDSCALEPDZ128rmbikz:
31447 case VRNDSCALEPDZ128rmi:
31448 case VRNDSCALEPDZ128rmik:
31449 case VRNDSCALEPDZ128rmikz:
31450 case VRNDSCALEPDZ128rri:
31451 case VRNDSCALEPDZ128rrik:
31452 case VRNDSCALEPDZ128rrikz:
31453 case VRNDSCALEPDZ256rmbi:
31454 case VRNDSCALEPDZ256rmbik:
31455 case VRNDSCALEPDZ256rmbikz:
31456 case VRNDSCALEPDZ256rmi:
31457 case VRNDSCALEPDZ256rmik:
31458 case VRNDSCALEPDZ256rmikz:
31459 case VRNDSCALEPDZ256rri:
31460 case VRNDSCALEPDZ256rrik:
31461 case VRNDSCALEPDZ256rrikz:
31462 case VRNDSCALEPDZrmbi:
31463 case VRNDSCALEPDZrmbik:
31464 case VRNDSCALEPDZrmbikz:
31465 case VRNDSCALEPDZrmi:
31466 case VRNDSCALEPDZrmik:
31467 case VRNDSCALEPDZrmikz:
31468 case VRNDSCALEPDZrri:
31469 case VRNDSCALEPDZrrib:
31470 case VRNDSCALEPDZrribk:
31471 case VRNDSCALEPDZrribkz:
31472 case VRNDSCALEPDZrrik:
31473 case VRNDSCALEPDZrrikz:
31474 return true;
31475 }
31476 return false;
31477}
31478
31479bool isVFPCLASSBF16(unsigned Opcode) {
31480 switch (Opcode) {
31481 case VFPCLASSBF16Z128mbi:
31482 case VFPCLASSBF16Z128mbik:
31483 case VFPCLASSBF16Z128mi:
31484 case VFPCLASSBF16Z128mik:
31485 case VFPCLASSBF16Z128ri:
31486 case VFPCLASSBF16Z128rik:
31487 case VFPCLASSBF16Z256mbi:
31488 case VFPCLASSBF16Z256mbik:
31489 case VFPCLASSBF16Z256mi:
31490 case VFPCLASSBF16Z256mik:
31491 case VFPCLASSBF16Z256ri:
31492 case VFPCLASSBF16Z256rik:
31493 case VFPCLASSBF16Zmbi:
31494 case VFPCLASSBF16Zmbik:
31495 case VFPCLASSBF16Zmi:
31496 case VFPCLASSBF16Zmik:
31497 case VFPCLASSBF16Zri:
31498 case VFPCLASSBF16Zrik:
31499 return true;
31500 }
31501 return false;
31502}
31503
31504bool isVMLOAD(unsigned Opcode) {
31505 switch (Opcode) {
31506 case VMLOAD32:
31507 case VMLOAD64:
31508 return true;
31509 }
31510 return false;
31511}
31512
31513bool isVPTERNLOGQ(unsigned Opcode) {
31514 switch (Opcode) {
31515 case VPTERNLOGQZ128rmbi:
31516 case VPTERNLOGQZ128rmbik:
31517 case VPTERNLOGQZ128rmbikz:
31518 case VPTERNLOGQZ128rmi:
31519 case VPTERNLOGQZ128rmik:
31520 case VPTERNLOGQZ128rmikz:
31521 case VPTERNLOGQZ128rri:
31522 case VPTERNLOGQZ128rrik:
31523 case VPTERNLOGQZ128rrikz:
31524 case VPTERNLOGQZ256rmbi:
31525 case VPTERNLOGQZ256rmbik:
31526 case VPTERNLOGQZ256rmbikz:
31527 case VPTERNLOGQZ256rmi:
31528 case VPTERNLOGQZ256rmik:
31529 case VPTERNLOGQZ256rmikz:
31530 case VPTERNLOGQZ256rri:
31531 case VPTERNLOGQZ256rrik:
31532 case VPTERNLOGQZ256rrikz:
31533 case VPTERNLOGQZrmbi:
31534 case VPTERNLOGQZrmbik:
31535 case VPTERNLOGQZrmbikz:
31536 case VPTERNLOGQZrmi:
31537 case VPTERNLOGQZrmik:
31538 case VPTERNLOGQZrmikz:
31539 case VPTERNLOGQZrri:
31540 case VPTERNLOGQZrrik:
31541 case VPTERNLOGQZrrikz:
31542 return true;
31543 }
31544 return false;
31545}
31546
31547bool isKXNORD(unsigned Opcode) {
31548 return Opcode == KXNORDkk;
31549}
31550
31551bool isFXSAVE(unsigned Opcode) {
31552 return Opcode == FXSAVE;
31553}
31554
31555bool isVUNPCKHPD(unsigned Opcode) {
31556 switch (Opcode) {
31557 case VUNPCKHPDYrm:
31558 case VUNPCKHPDYrr:
31559 case VUNPCKHPDZ128rm:
31560 case VUNPCKHPDZ128rmb:
31561 case VUNPCKHPDZ128rmbk:
31562 case VUNPCKHPDZ128rmbkz:
31563 case VUNPCKHPDZ128rmk:
31564 case VUNPCKHPDZ128rmkz:
31565 case VUNPCKHPDZ128rr:
31566 case VUNPCKHPDZ128rrk:
31567 case VUNPCKHPDZ128rrkz:
31568 case VUNPCKHPDZ256rm:
31569 case VUNPCKHPDZ256rmb:
31570 case VUNPCKHPDZ256rmbk:
31571 case VUNPCKHPDZ256rmbkz:
31572 case VUNPCKHPDZ256rmk:
31573 case VUNPCKHPDZ256rmkz:
31574 case VUNPCKHPDZ256rr:
31575 case VUNPCKHPDZ256rrk:
31576 case VUNPCKHPDZ256rrkz:
31577 case VUNPCKHPDZrm:
31578 case VUNPCKHPDZrmb:
31579 case VUNPCKHPDZrmbk:
31580 case VUNPCKHPDZrmbkz:
31581 case VUNPCKHPDZrmk:
31582 case VUNPCKHPDZrmkz:
31583 case VUNPCKHPDZrr:
31584 case VUNPCKHPDZrrk:
31585 case VUNPCKHPDZrrkz:
31586 case VUNPCKHPDrm:
31587 case VUNPCKHPDrr:
31588 return true;
31589 }
31590 return false;
31591}
31592
31593bool isCVTPS2DQ(unsigned Opcode) {
31594 switch (Opcode) {
31595 case CVTPS2DQrm:
31596 case CVTPS2DQrr:
31597 return true;
31598 }
31599 return false;
31600}
31601
31602bool isTMMULTF32PS(unsigned Opcode) {
31603 return Opcode == TMMULTF32PS;
31604}
31605
31606bool isVFMSUB213SS(unsigned Opcode) {
31607 switch (Opcode) {
31608 case VFMSUB213SSZm_Int:
31609 case VFMSUB213SSZmk_Int:
31610 case VFMSUB213SSZmkz_Int:
31611 case VFMSUB213SSZr_Int:
31612 case VFMSUB213SSZrb_Int:
31613 case VFMSUB213SSZrbk_Int:
31614 case VFMSUB213SSZrbkz_Int:
31615 case VFMSUB213SSZrk_Int:
31616 case VFMSUB213SSZrkz_Int:
31617 case VFMSUB213SSm_Int:
31618 case VFMSUB213SSr_Int:
31619 return true;
31620 }
31621 return false;
31622}
31623
31624bool isVPOPCNTD(unsigned Opcode) {
31625 switch (Opcode) {
31626 case VPOPCNTDZ128rm:
31627 case VPOPCNTDZ128rmb:
31628 case VPOPCNTDZ128rmbk:
31629 case VPOPCNTDZ128rmbkz:
31630 case VPOPCNTDZ128rmk:
31631 case VPOPCNTDZ128rmkz:
31632 case VPOPCNTDZ128rr:
31633 case VPOPCNTDZ128rrk:
31634 case VPOPCNTDZ128rrkz:
31635 case VPOPCNTDZ256rm:
31636 case VPOPCNTDZ256rmb:
31637 case VPOPCNTDZ256rmbk:
31638 case VPOPCNTDZ256rmbkz:
31639 case VPOPCNTDZ256rmk:
31640 case VPOPCNTDZ256rmkz:
31641 case VPOPCNTDZ256rr:
31642 case VPOPCNTDZ256rrk:
31643 case VPOPCNTDZ256rrkz:
31644 case VPOPCNTDZrm:
31645 case VPOPCNTDZrmb:
31646 case VPOPCNTDZrmbk:
31647 case VPOPCNTDZrmbkz:
31648 case VPOPCNTDZrmk:
31649 case VPOPCNTDZrmkz:
31650 case VPOPCNTDZrr:
31651 case VPOPCNTDZrrk:
31652 case VPOPCNTDZrrkz:
31653 return true;
31654 }
31655 return false;
31656}
31657
31658bool isSALC(unsigned Opcode) {
31659 return Opcode == SALC;
31660}
31661
31662bool isV4FNMADDSS(unsigned Opcode) {
31663 switch (Opcode) {
31664 case V4FNMADDSSrm:
31665 case V4FNMADDSSrmk:
31666 case V4FNMADDSSrmkz:
31667 return true;
31668 }
31669 return false;
31670}
31671
31672bool isXCRYPTOFB(unsigned Opcode) {
31673 return Opcode == XCRYPTOFB;
31674}
31675
31676bool isVORPD(unsigned Opcode) {
31677 switch (Opcode) {
31678 case VORPDYrm:
31679 case VORPDYrr:
31680 case VORPDZ128rm:
31681 case VORPDZ128rmb:
31682 case VORPDZ128rmbk:
31683 case VORPDZ128rmbkz:
31684 case VORPDZ128rmk:
31685 case VORPDZ128rmkz:
31686 case VORPDZ128rr:
31687 case VORPDZ128rrk:
31688 case VORPDZ128rrkz:
31689 case VORPDZ256rm:
31690 case VORPDZ256rmb:
31691 case VORPDZ256rmbk:
31692 case VORPDZ256rmbkz:
31693 case VORPDZ256rmk:
31694 case VORPDZ256rmkz:
31695 case VORPDZ256rr:
31696 case VORPDZ256rrk:
31697 case VORPDZ256rrkz:
31698 case VORPDZrm:
31699 case VORPDZrmb:
31700 case VORPDZrmbk:
31701 case VORPDZrmbkz:
31702 case VORPDZrmk:
31703 case VORPDZrmkz:
31704 case VORPDZrr:
31705 case VORPDZrrk:
31706 case VORPDZrrkz:
31707 case VORPDrm:
31708 case VORPDrr:
31709 return true;
31710 }
31711 return false;
31712}
31713
31714bool isLSL(unsigned Opcode) {
31715 switch (Opcode) {
31716 case LSL16rm:
31717 case LSL16rr:
31718 case LSL32rm:
31719 case LSL32rr:
31720 case LSL64rm:
31721 case LSL64rr:
31722 return true;
31723 }
31724 return false;
31725}
31726
31727bool isXCRYPTCFB(unsigned Opcode) {
31728 return Opcode == XCRYPTCFB;
31729}
31730
31731bool isVGETEXPSS(unsigned Opcode) {
31732 switch (Opcode) {
31733 case VGETEXPSSZm:
31734 case VGETEXPSSZmk:
31735 case VGETEXPSSZmkz:
31736 case VGETEXPSSZr:
31737 case VGETEXPSSZrb:
31738 case VGETEXPSSZrbk:
31739 case VGETEXPSSZrbkz:
31740 case VGETEXPSSZrk:
31741 case VGETEXPSSZrkz:
31742 return true;
31743 }
31744 return false;
31745}
31746
31747bool isPSLLDQ(unsigned Opcode) {
31748 return Opcode == PSLLDQri;
31749}
31750
31751bool isVPDPBUUD(unsigned Opcode) {
31752 switch (Opcode) {
31753 case VPDPBUUDYrm:
31754 case VPDPBUUDYrr:
31755 case VPDPBUUDZ128rm:
31756 case VPDPBUUDZ128rmb:
31757 case VPDPBUUDZ128rmbk:
31758 case VPDPBUUDZ128rmbkz:
31759 case VPDPBUUDZ128rmk:
31760 case VPDPBUUDZ128rmkz:
31761 case VPDPBUUDZ128rr:
31762 case VPDPBUUDZ128rrk:
31763 case VPDPBUUDZ128rrkz:
31764 case VPDPBUUDZ256rm:
31765 case VPDPBUUDZ256rmb:
31766 case VPDPBUUDZ256rmbk:
31767 case VPDPBUUDZ256rmbkz:
31768 case VPDPBUUDZ256rmk:
31769 case VPDPBUUDZ256rmkz:
31770 case VPDPBUUDZ256rr:
31771 case VPDPBUUDZ256rrk:
31772 case VPDPBUUDZ256rrkz:
31773 case VPDPBUUDZrm:
31774 case VPDPBUUDZrmb:
31775 case VPDPBUUDZrmbk:
31776 case VPDPBUUDZrmbkz:
31777 case VPDPBUUDZrmk:
31778 case VPDPBUUDZrmkz:
31779 case VPDPBUUDZrr:
31780 case VPDPBUUDZrrk:
31781 case VPDPBUUDZrrkz:
31782 case VPDPBUUDrm:
31783 case VPDPBUUDrr:
31784 return true;
31785 }
31786 return false;
31787}
31788
31789bool isVMXOFF(unsigned Opcode) {
31790 return Opcode == VMXOFF;
31791}
31792
31793bool isBLSIC(unsigned Opcode) {
31794 switch (Opcode) {
31795 case BLSIC32rm:
31796 case BLSIC32rr:
31797 case BLSIC64rm:
31798 case BLSIC64rr:
31799 return true;
31800 }
31801 return false;
31802}
31803
31804bool isMOVLHPS(unsigned Opcode) {
31805 return Opcode == MOVLHPSrr;
31806}
31807
31808bool isVMOVRSQ(unsigned Opcode) {
31809 switch (Opcode) {
31810 case VMOVRSQZ128m:
31811 case VMOVRSQZ128mk:
31812 case VMOVRSQZ128mkz:
31813 case VMOVRSQZ256m:
31814 case VMOVRSQZ256mk:
31815 case VMOVRSQZ256mkz:
31816 case VMOVRSQZm:
31817 case VMOVRSQZmk:
31818 case VMOVRSQZmkz:
31819 return true;
31820 }
31821 return false;
31822}
31823
31824bool isVFNMSUBSD(unsigned Opcode) {
31825 switch (Opcode) {
31826 case VFNMSUBSD4mr:
31827 case VFNMSUBSD4rm:
31828 case VFNMSUBSD4rr:
31829 case VFNMSUBSD4rr_REV:
31830 return true;
31831 }
31832 return false;
31833}
31834
31835bool isVCVTPH2IUBS(unsigned Opcode) {
31836 switch (Opcode) {
31837 case VCVTPH2IUBSZ128rm:
31838 case VCVTPH2IUBSZ128rmb:
31839 case VCVTPH2IUBSZ128rmbk:
31840 case VCVTPH2IUBSZ128rmbkz:
31841 case VCVTPH2IUBSZ128rmk:
31842 case VCVTPH2IUBSZ128rmkz:
31843 case VCVTPH2IUBSZ128rr:
31844 case VCVTPH2IUBSZ128rrk:
31845 case VCVTPH2IUBSZ128rrkz:
31846 case VCVTPH2IUBSZ256rm:
31847 case VCVTPH2IUBSZ256rmb:
31848 case VCVTPH2IUBSZ256rmbk:
31849 case VCVTPH2IUBSZ256rmbkz:
31850 case VCVTPH2IUBSZ256rmk:
31851 case VCVTPH2IUBSZ256rmkz:
31852 case VCVTPH2IUBSZ256rr:
31853 case VCVTPH2IUBSZ256rrk:
31854 case VCVTPH2IUBSZ256rrkz:
31855 case VCVTPH2IUBSZrm:
31856 case VCVTPH2IUBSZrmb:
31857 case VCVTPH2IUBSZrmbk:
31858 case VCVTPH2IUBSZrmbkz:
31859 case VCVTPH2IUBSZrmk:
31860 case VCVTPH2IUBSZrmkz:
31861 case VCVTPH2IUBSZrr:
31862 case VCVTPH2IUBSZrrb:
31863 case VCVTPH2IUBSZrrbk:
31864 case VCVTPH2IUBSZrrbkz:
31865 case VCVTPH2IUBSZrrk:
31866 case VCVTPH2IUBSZrrkz:
31867 return true;
31868 }
31869 return false;
31870}
31871
31872bool isVFPCLASSSH(unsigned Opcode) {
31873 switch (Opcode) {
31874 case VFPCLASSSHZmi:
31875 case VFPCLASSSHZmik:
31876 case VFPCLASSSHZri:
31877 case VFPCLASSSHZrik:
31878 return true;
31879 }
31880 return false;
31881}
31882
31883bool isVPSHLQ(unsigned Opcode) {
31884 switch (Opcode) {
31885 case VPSHLQmr:
31886 case VPSHLQrm:
31887 case VPSHLQrr:
31888 case VPSHLQrr_REV:
31889 return true;
31890 }
31891 return false;
31892}
31893
31894bool isVROUNDPS(unsigned Opcode) {
31895 switch (Opcode) {
31896 case VROUNDPSYmi:
31897 case VROUNDPSYri:
31898 case VROUNDPSmi:
31899 case VROUNDPSri:
31900 return true;
31901 }
31902 return false;
31903}
31904
31905bool isVSCATTERPF0QPS(unsigned Opcode) {
31906 return Opcode == VSCATTERPF0QPSm;
31907}
31908
31909bool isERETS(unsigned Opcode) {
31910 return Opcode == ERETS;
31911}
31912
31913bool isVPERMI2D(unsigned Opcode) {
31914 switch (Opcode) {
31915 case VPERMI2DZ128rm:
31916 case VPERMI2DZ128rmb:
31917 case VPERMI2DZ128rmbk:
31918 case VPERMI2DZ128rmbkz:
31919 case VPERMI2DZ128rmk:
31920 case VPERMI2DZ128rmkz:
31921 case VPERMI2DZ128rr:
31922 case VPERMI2DZ128rrk:
31923 case VPERMI2DZ128rrkz:
31924 case VPERMI2DZ256rm:
31925 case VPERMI2DZ256rmb:
31926 case VPERMI2DZ256rmbk:
31927 case VPERMI2DZ256rmbkz:
31928 case VPERMI2DZ256rmk:
31929 case VPERMI2DZ256rmkz:
31930 case VPERMI2DZ256rr:
31931 case VPERMI2DZ256rrk:
31932 case VPERMI2DZ256rrkz:
31933 case VPERMI2DZrm:
31934 case VPERMI2DZrmb:
31935 case VPERMI2DZrmbk:
31936 case VPERMI2DZrmbkz:
31937 case VPERMI2DZrmk:
31938 case VPERMI2DZrmkz:
31939 case VPERMI2DZrr:
31940 case VPERMI2DZrrk:
31941 case VPERMI2DZrrkz:
31942 return true;
31943 }
31944 return false;
31945}
31946
31947bool isFUCOMP(unsigned Opcode) {
31948 return Opcode == UCOM_FPr;
31949}
31950
31951bool isVCVTTPS2QQ(unsigned Opcode) {
31952 switch (Opcode) {
31953 case VCVTTPS2QQZ128rm:
31954 case VCVTTPS2QQZ128rmb:
31955 case VCVTTPS2QQZ128rmbk:
31956 case VCVTTPS2QQZ128rmbkz:
31957 case VCVTTPS2QQZ128rmk:
31958 case VCVTTPS2QQZ128rmkz:
31959 case VCVTTPS2QQZ128rr:
31960 case VCVTTPS2QQZ128rrk:
31961 case VCVTTPS2QQZ128rrkz:
31962 case VCVTTPS2QQZ256rm:
31963 case VCVTTPS2QQZ256rmb:
31964 case VCVTTPS2QQZ256rmbk:
31965 case VCVTTPS2QQZ256rmbkz:
31966 case VCVTTPS2QQZ256rmk:
31967 case VCVTTPS2QQZ256rmkz:
31968 case VCVTTPS2QQZ256rr:
31969 case VCVTTPS2QQZ256rrk:
31970 case VCVTTPS2QQZ256rrkz:
31971 case VCVTTPS2QQZrm:
31972 case VCVTTPS2QQZrmb:
31973 case VCVTTPS2QQZrmbk:
31974 case VCVTTPS2QQZrmbkz:
31975 case VCVTTPS2QQZrmk:
31976 case VCVTTPS2QQZrmkz:
31977 case VCVTTPS2QQZrr:
31978 case VCVTTPS2QQZrrb:
31979 case VCVTTPS2QQZrrbk:
31980 case VCVTTPS2QQZrrbkz:
31981 case VCVTTPS2QQZrrk:
31982 case VCVTTPS2QQZrrkz:
31983 return true;
31984 }
31985 return false;
31986}
31987
31988bool isPUSHFD(unsigned Opcode) {
31989 return Opcode == PUSHF32;
31990}
31991
31992bool isKORB(unsigned Opcode) {
31993 return Opcode == KORBkk;
31994}
31995
31996bool isVRCP28PD(unsigned Opcode) {
31997 switch (Opcode) {
31998 case VRCP28PDZm:
31999 case VRCP28PDZmb:
32000 case VRCP28PDZmbk:
32001 case VRCP28PDZmbkz:
32002 case VRCP28PDZmk:
32003 case VRCP28PDZmkz:
32004 case VRCP28PDZr:
32005 case VRCP28PDZrb:
32006 case VRCP28PDZrbk:
32007 case VRCP28PDZrbkz:
32008 case VRCP28PDZrk:
32009 case VRCP28PDZrkz:
32010 return true;
32011 }
32012 return false;
32013}
32014
32015bool isVPABSD(unsigned Opcode) {
32016 switch (Opcode) {
32017 case VPABSDYrm:
32018 case VPABSDYrr:
32019 case VPABSDZ128rm:
32020 case VPABSDZ128rmb:
32021 case VPABSDZ128rmbk:
32022 case VPABSDZ128rmbkz:
32023 case VPABSDZ128rmk:
32024 case VPABSDZ128rmkz:
32025 case VPABSDZ128rr:
32026 case VPABSDZ128rrk:
32027 case VPABSDZ128rrkz:
32028 case VPABSDZ256rm:
32029 case VPABSDZ256rmb:
32030 case VPABSDZ256rmbk:
32031 case VPABSDZ256rmbkz:
32032 case VPABSDZ256rmk:
32033 case VPABSDZ256rmkz:
32034 case VPABSDZ256rr:
32035 case VPABSDZ256rrk:
32036 case VPABSDZ256rrkz:
32037 case VPABSDZrm:
32038 case VPABSDZrmb:
32039 case VPABSDZrmbk:
32040 case VPABSDZrmbkz:
32041 case VPABSDZrmk:
32042 case VPABSDZrmkz:
32043 case VPABSDZrr:
32044 case VPABSDZrrk:
32045 case VPABSDZrrkz:
32046 case VPABSDrm:
32047 case VPABSDrr:
32048 return true;
32049 }
32050 return false;
32051}
32052
32053bool isVROUNDSS(unsigned Opcode) {
32054 switch (Opcode) {
32055 case VROUNDSSmi_Int:
32056 case VROUNDSSri_Int:
32057 return true;
32058 }
32059 return false;
32060}
32061
32062bool isVCVTSD2USI(unsigned Opcode) {
32063 switch (Opcode) {
32064 case VCVTSD2USI64Zrm_Int:
32065 case VCVTSD2USI64Zrr_Int:
32066 case VCVTSD2USI64Zrrb_Int:
32067 case VCVTSD2USIZrm_Int:
32068 case VCVTSD2USIZrr_Int:
32069 case VCVTSD2USIZrrb_Int:
32070 return true;
32071 }
32072 return false;
32073}
32074
32075bool isVPABSB(unsigned Opcode) {
32076 switch (Opcode) {
32077 case VPABSBYrm:
32078 case VPABSBYrr:
32079 case VPABSBZ128rm:
32080 case VPABSBZ128rmk:
32081 case VPABSBZ128rmkz:
32082 case VPABSBZ128rr:
32083 case VPABSBZ128rrk:
32084 case VPABSBZ128rrkz:
32085 case VPABSBZ256rm:
32086 case VPABSBZ256rmk:
32087 case VPABSBZ256rmkz:
32088 case VPABSBZ256rr:
32089 case VPABSBZ256rrk:
32090 case VPABSBZ256rrkz:
32091 case VPABSBZrm:
32092 case VPABSBZrmk:
32093 case VPABSBZrmkz:
32094 case VPABSBZrr:
32095 case VPABSBZrrk:
32096 case VPABSBZrrkz:
32097 case VPABSBrm:
32098 case VPABSBrr:
32099 return true;
32100 }
32101 return false;
32102}
32103
32104bool isPMAXUD(unsigned Opcode) {
32105 switch (Opcode) {
32106 case PMAXUDrm:
32107 case PMAXUDrr:
32108 return true;
32109 }
32110 return false;
32111}
32112
32113bool isVPMULHUW(unsigned Opcode) {
32114 switch (Opcode) {
32115 case VPMULHUWYrm:
32116 case VPMULHUWYrr:
32117 case VPMULHUWZ128rm:
32118 case VPMULHUWZ128rmk:
32119 case VPMULHUWZ128rmkz:
32120 case VPMULHUWZ128rr:
32121 case VPMULHUWZ128rrk:
32122 case VPMULHUWZ128rrkz:
32123 case VPMULHUWZ256rm:
32124 case VPMULHUWZ256rmk:
32125 case VPMULHUWZ256rmkz:
32126 case VPMULHUWZ256rr:
32127 case VPMULHUWZ256rrk:
32128 case VPMULHUWZ256rrkz:
32129 case VPMULHUWZrm:
32130 case VPMULHUWZrmk:
32131 case VPMULHUWZrmkz:
32132 case VPMULHUWZrr:
32133 case VPMULHUWZrrk:
32134 case VPMULHUWZrrkz:
32135 case VPMULHUWrm:
32136 case VPMULHUWrr:
32137 return true;
32138 }
32139 return false;
32140}
32141
32142bool isVPERMPD(unsigned Opcode) {
32143 switch (Opcode) {
32144 case VPERMPDYmi:
32145 case VPERMPDYri:
32146 case VPERMPDZ256mbi:
32147 case VPERMPDZ256mbik:
32148 case VPERMPDZ256mbikz:
32149 case VPERMPDZ256mi:
32150 case VPERMPDZ256mik:
32151 case VPERMPDZ256mikz:
32152 case VPERMPDZ256ri:
32153 case VPERMPDZ256rik:
32154 case VPERMPDZ256rikz:
32155 case VPERMPDZ256rm:
32156 case VPERMPDZ256rmb:
32157 case VPERMPDZ256rmbk:
32158 case VPERMPDZ256rmbkz:
32159 case VPERMPDZ256rmk:
32160 case VPERMPDZ256rmkz:
32161 case VPERMPDZ256rr:
32162 case VPERMPDZ256rrk:
32163 case VPERMPDZ256rrkz:
32164 case VPERMPDZmbi:
32165 case VPERMPDZmbik:
32166 case VPERMPDZmbikz:
32167 case VPERMPDZmi:
32168 case VPERMPDZmik:
32169 case VPERMPDZmikz:
32170 case VPERMPDZri:
32171 case VPERMPDZrik:
32172 case VPERMPDZrikz:
32173 case VPERMPDZrm:
32174 case VPERMPDZrmb:
32175 case VPERMPDZrmbk:
32176 case VPERMPDZrmbkz:
32177 case VPERMPDZrmk:
32178 case VPERMPDZrmkz:
32179 case VPERMPDZrr:
32180 case VPERMPDZrrk:
32181 case VPERMPDZrrkz:
32182 return true;
32183 }
32184 return false;
32185}
32186
32187bool isFCHS(unsigned Opcode) {
32188 return Opcode == CHS_F;
32189}
32190
32191bool isVPBLENDMB(unsigned Opcode) {
32192 switch (Opcode) {
32193 case VPBLENDMBZ128rm:
32194 case VPBLENDMBZ128rmk:
32195 case VPBLENDMBZ128rmkz:
32196 case VPBLENDMBZ128rr:
32197 case VPBLENDMBZ128rrk:
32198 case VPBLENDMBZ128rrkz:
32199 case VPBLENDMBZ256rm:
32200 case VPBLENDMBZ256rmk:
32201 case VPBLENDMBZ256rmkz:
32202 case VPBLENDMBZ256rr:
32203 case VPBLENDMBZ256rrk:
32204 case VPBLENDMBZ256rrkz:
32205 case VPBLENDMBZrm:
32206 case VPBLENDMBZrmk:
32207 case VPBLENDMBZrmkz:
32208 case VPBLENDMBZrr:
32209 case VPBLENDMBZrrk:
32210 case VPBLENDMBZrrkz:
32211 return true;
32212 }
32213 return false;
32214}
32215
32216bool isVGETMANTSS(unsigned Opcode) {
32217 switch (Opcode) {
32218 case VGETMANTSSZrmi:
32219 case VGETMANTSSZrmik:
32220 case VGETMANTSSZrmikz:
32221 case VGETMANTSSZrri:
32222 case VGETMANTSSZrrib:
32223 case VGETMANTSSZrribk:
32224 case VGETMANTSSZrribkz:
32225 case VGETMANTSSZrrik:
32226 case VGETMANTSSZrrikz:
32227 return true;
32228 }
32229 return false;
32230}
32231
32232bool isVPSLLW(unsigned Opcode) {
32233 switch (Opcode) {
32234 case VPSLLWYri:
32235 case VPSLLWYrm:
32236 case VPSLLWYrr:
32237 case VPSLLWZ128mi:
32238 case VPSLLWZ128mik:
32239 case VPSLLWZ128mikz:
32240 case VPSLLWZ128ri:
32241 case VPSLLWZ128rik:
32242 case VPSLLWZ128rikz:
32243 case VPSLLWZ128rm:
32244 case VPSLLWZ128rmk:
32245 case VPSLLWZ128rmkz:
32246 case VPSLLWZ128rr:
32247 case VPSLLWZ128rrk:
32248 case VPSLLWZ128rrkz:
32249 case VPSLLWZ256mi:
32250 case VPSLLWZ256mik:
32251 case VPSLLWZ256mikz:
32252 case VPSLLWZ256ri:
32253 case VPSLLWZ256rik:
32254 case VPSLLWZ256rikz:
32255 case VPSLLWZ256rm:
32256 case VPSLLWZ256rmk:
32257 case VPSLLWZ256rmkz:
32258 case VPSLLWZ256rr:
32259 case VPSLLWZ256rrk:
32260 case VPSLLWZ256rrkz:
32261 case VPSLLWZmi:
32262 case VPSLLWZmik:
32263 case VPSLLWZmikz:
32264 case VPSLLWZri:
32265 case VPSLLWZrik:
32266 case VPSLLWZrikz:
32267 case VPSLLWZrm:
32268 case VPSLLWZrmk:
32269 case VPSLLWZrmkz:
32270 case VPSLLWZrr:
32271 case VPSLLWZrrk:
32272 case VPSLLWZrrkz:
32273 case VPSLLWri:
32274 case VPSLLWrm:
32275 case VPSLLWrr:
32276 return true;
32277 }
32278 return false;
32279}
32280
32281bool isVDIVPD(unsigned Opcode) {
32282 switch (Opcode) {
32283 case VDIVPDYrm:
32284 case VDIVPDYrr:
32285 case VDIVPDZ128rm:
32286 case VDIVPDZ128rmb:
32287 case VDIVPDZ128rmbk:
32288 case VDIVPDZ128rmbkz:
32289 case VDIVPDZ128rmk:
32290 case VDIVPDZ128rmkz:
32291 case VDIVPDZ128rr:
32292 case VDIVPDZ128rrk:
32293 case VDIVPDZ128rrkz:
32294 case VDIVPDZ256rm:
32295 case VDIVPDZ256rmb:
32296 case VDIVPDZ256rmbk:
32297 case VDIVPDZ256rmbkz:
32298 case VDIVPDZ256rmk:
32299 case VDIVPDZ256rmkz:
32300 case VDIVPDZ256rr:
32301 case VDIVPDZ256rrk:
32302 case VDIVPDZ256rrkz:
32303 case VDIVPDZrm:
32304 case VDIVPDZrmb:
32305 case VDIVPDZrmbk:
32306 case VDIVPDZrmbkz:
32307 case VDIVPDZrmk:
32308 case VDIVPDZrmkz:
32309 case VDIVPDZrr:
32310 case VDIVPDZrrb:
32311 case VDIVPDZrrbk:
32312 case VDIVPDZrrbkz:
32313 case VDIVPDZrrk:
32314 case VDIVPDZrrkz:
32315 case VDIVPDrm:
32316 case VDIVPDrr:
32317 return true;
32318 }
32319 return false;
32320}
32321
32322bool isBLCMSK(unsigned Opcode) {
32323 switch (Opcode) {
32324 case BLCMSK32rm:
32325 case BLCMSK32rr:
32326 case BLCMSK64rm:
32327 case BLCMSK64rr:
32328 return true;
32329 }
32330 return false;
32331}
32332
32333bool isFDIV(unsigned Opcode) {
32334 switch (Opcode) {
32335 case DIV_F32m:
32336 case DIV_F64m:
32337 case DIV_FST0r:
32338 case DIV_FrST0:
32339 return true;
32340 }
32341 return false;
32342}
32343
32344bool isRSQRTSS(unsigned Opcode) {
32345 switch (Opcode) {
32346 case RSQRTSSm_Int:
32347 case RSQRTSSr_Int:
32348 return true;
32349 }
32350 return false;
32351}
32352
32353bool isPOR(unsigned Opcode) {
32354 switch (Opcode) {
32355 case MMX_PORrm:
32356 case MMX_PORrr:
32357 case PORrm:
32358 case PORrr:
32359 return true;
32360 }
32361 return false;
32362}
32363
32364bool isVMOVDQA32(unsigned Opcode) {
32365 switch (Opcode) {
32366 case VMOVDQA32Z128mr:
32367 case VMOVDQA32Z128mrk:
32368 case VMOVDQA32Z128rm:
32369 case VMOVDQA32Z128rmk:
32370 case VMOVDQA32Z128rmkz:
32371 case VMOVDQA32Z128rr:
32372 case VMOVDQA32Z128rr_REV:
32373 case VMOVDQA32Z128rrk:
32374 case VMOVDQA32Z128rrk_REV:
32375 case VMOVDQA32Z128rrkz:
32376 case VMOVDQA32Z128rrkz_REV:
32377 case VMOVDQA32Z256mr:
32378 case VMOVDQA32Z256mrk:
32379 case VMOVDQA32Z256rm:
32380 case VMOVDQA32Z256rmk:
32381 case VMOVDQA32Z256rmkz:
32382 case VMOVDQA32Z256rr:
32383 case VMOVDQA32Z256rr_REV:
32384 case VMOVDQA32Z256rrk:
32385 case VMOVDQA32Z256rrk_REV:
32386 case VMOVDQA32Z256rrkz:
32387 case VMOVDQA32Z256rrkz_REV:
32388 case VMOVDQA32Zmr:
32389 case VMOVDQA32Zmrk:
32390 case VMOVDQA32Zrm:
32391 case VMOVDQA32Zrmk:
32392 case VMOVDQA32Zrmkz:
32393 case VMOVDQA32Zrr:
32394 case VMOVDQA32Zrr_REV:
32395 case VMOVDQA32Zrrk:
32396 case VMOVDQA32Zrrk_REV:
32397 case VMOVDQA32Zrrkz:
32398 case VMOVDQA32Zrrkz_REV:
32399 return true;
32400 }
32401 return false;
32402}
32403
32404bool isVPHADDUWQ(unsigned Opcode) {
32405 switch (Opcode) {
32406 case VPHADDUWQrm:
32407 case VPHADDUWQrr:
32408 return true;
32409 }
32410 return false;
32411}
32412
32413bool isPSRAD(unsigned Opcode) {
32414 switch (Opcode) {
32415 case MMX_PSRADri:
32416 case MMX_PSRADrm:
32417 case MMX_PSRADrr:
32418 case PSRADri:
32419 case PSRADrm:
32420 case PSRADrr:
32421 return true;
32422 }
32423 return false;
32424}
32425
32426bool isPREFETCHW(unsigned Opcode) {
32427 return Opcode == PREFETCHW;
32428}
32429
32430bool isFIDIVR(unsigned Opcode) {
32431 switch (Opcode) {
32432 case DIVR_FI16m:
32433 case DIVR_FI32m:
32434 return true;
32435 }
32436 return false;
32437}
32438
32439bool isMOVHPS(unsigned Opcode) {
32440 switch (Opcode) {
32441 case MOVHPSmr:
32442 case MOVHPSrm:
32443 return true;
32444 }
32445 return false;
32446}
32447
32448bool isVFNMSUB231PH(unsigned Opcode) {
32449 switch (Opcode) {
32450 case VFNMSUB231PHZ128m:
32451 case VFNMSUB231PHZ128mb:
32452 case VFNMSUB231PHZ128mbk:
32453 case VFNMSUB231PHZ128mbkz:
32454 case VFNMSUB231PHZ128mk:
32455 case VFNMSUB231PHZ128mkz:
32456 case VFNMSUB231PHZ128r:
32457 case VFNMSUB231PHZ128rk:
32458 case VFNMSUB231PHZ128rkz:
32459 case VFNMSUB231PHZ256m:
32460 case VFNMSUB231PHZ256mb:
32461 case VFNMSUB231PHZ256mbk:
32462 case VFNMSUB231PHZ256mbkz:
32463 case VFNMSUB231PHZ256mk:
32464 case VFNMSUB231PHZ256mkz:
32465 case VFNMSUB231PHZ256r:
32466 case VFNMSUB231PHZ256rk:
32467 case VFNMSUB231PHZ256rkz:
32468 case VFNMSUB231PHZm:
32469 case VFNMSUB231PHZmb:
32470 case VFNMSUB231PHZmbk:
32471 case VFNMSUB231PHZmbkz:
32472 case VFNMSUB231PHZmk:
32473 case VFNMSUB231PHZmkz:
32474 case VFNMSUB231PHZr:
32475 case VFNMSUB231PHZrb:
32476 case VFNMSUB231PHZrbk:
32477 case VFNMSUB231PHZrbkz:
32478 case VFNMSUB231PHZrk:
32479 case VFNMSUB231PHZrkz:
32480 return true;
32481 }
32482 return false;
32483}
32484
32485bool isUNPCKLPS(unsigned Opcode) {
32486 switch (Opcode) {
32487 case UNPCKLPSrm:
32488 case UNPCKLPSrr:
32489 return true;
32490 }
32491 return false;
32492}
32493
32494bool isVPSIGNB(unsigned Opcode) {
32495 switch (Opcode) {
32496 case VPSIGNBYrm:
32497 case VPSIGNBYrr:
32498 case VPSIGNBrm:
32499 case VPSIGNBrr:
32500 return true;
32501 }
32502 return false;
32503}
32504
32505bool isSAVEPREVSSP(unsigned Opcode) {
32506 return Opcode == SAVEPREVSSP;
32507}
32508
32509bool isVSCALEFSD(unsigned Opcode) {
32510 switch (Opcode) {
32511 case VSCALEFSDZrm:
32512 case VSCALEFSDZrmk:
32513 case VSCALEFSDZrmkz:
32514 case VSCALEFSDZrr:
32515 case VSCALEFSDZrrb_Int:
32516 case VSCALEFSDZrrbk_Int:
32517 case VSCALEFSDZrrbkz_Int:
32518 case VSCALEFSDZrrk:
32519 case VSCALEFSDZrrkz:
32520 return true;
32521 }
32522 return false;
32523}
32524
32525bool isFSIN(unsigned Opcode) {
32526 return Opcode == FSIN;
32527}
32528
32529bool isSCASQ(unsigned Opcode) {
32530 return Opcode == SCASQ;
32531}
32532
32533bool isVCVTTPD2QQS(unsigned Opcode) {
32534 switch (Opcode) {
32535 case VCVTTPD2QQSZ128rm:
32536 case VCVTTPD2QQSZ128rmb:
32537 case VCVTTPD2QQSZ128rmbk:
32538 case VCVTTPD2QQSZ128rmbkz:
32539 case VCVTTPD2QQSZ128rmk:
32540 case VCVTTPD2QQSZ128rmkz:
32541 case VCVTTPD2QQSZ128rr:
32542 case VCVTTPD2QQSZ128rrk:
32543 case VCVTTPD2QQSZ128rrkz:
32544 case VCVTTPD2QQSZ256rm:
32545 case VCVTTPD2QQSZ256rmb:
32546 case VCVTTPD2QQSZ256rmbk:
32547 case VCVTTPD2QQSZ256rmbkz:
32548 case VCVTTPD2QQSZ256rmk:
32549 case VCVTTPD2QQSZ256rmkz:
32550 case VCVTTPD2QQSZ256rr:
32551 case VCVTTPD2QQSZ256rrb:
32552 case VCVTTPD2QQSZ256rrbk:
32553 case VCVTTPD2QQSZ256rrbkz:
32554 case VCVTTPD2QQSZ256rrk:
32555 case VCVTTPD2QQSZ256rrkz:
32556 case VCVTTPD2QQSZrm:
32557 case VCVTTPD2QQSZrmb:
32558 case VCVTTPD2QQSZrmbk:
32559 case VCVTTPD2QQSZrmbkz:
32560 case VCVTTPD2QQSZrmk:
32561 case VCVTTPD2QQSZrmkz:
32562 case VCVTTPD2QQSZrr:
32563 case VCVTTPD2QQSZrrb:
32564 case VCVTTPD2QQSZrrbk:
32565 case VCVTTPD2QQSZrrbkz:
32566 case VCVTTPD2QQSZrrk:
32567 case VCVTTPD2QQSZrrkz:
32568 return true;
32569 }
32570 return false;
32571}
32572
32573bool isPCMPGTW(unsigned Opcode) {
32574 switch (Opcode) {
32575 case MMX_PCMPGTWrm:
32576 case MMX_PCMPGTWrr:
32577 case PCMPGTWrm:
32578 case PCMPGTWrr:
32579 return true;
32580 }
32581 return false;
32582}
32583
32584bool isMULX(unsigned Opcode) {
32585 switch (Opcode) {
32586 case MULX32rm:
32587 case MULX32rm_EVEX:
32588 case MULX32rr:
32589 case MULX32rr_EVEX:
32590 case MULX64rm:
32591 case MULX64rm_EVEX:
32592 case MULX64rr:
32593 case MULX64rr_EVEX:
32594 return true;
32595 }
32596 return false;
32597}
32598
32599bool isVPMAXUW(unsigned Opcode) {
32600 switch (Opcode) {
32601 case VPMAXUWYrm:
32602 case VPMAXUWYrr:
32603 case VPMAXUWZ128rm:
32604 case VPMAXUWZ128rmk:
32605 case VPMAXUWZ128rmkz:
32606 case VPMAXUWZ128rr:
32607 case VPMAXUWZ128rrk:
32608 case VPMAXUWZ128rrkz:
32609 case VPMAXUWZ256rm:
32610 case VPMAXUWZ256rmk:
32611 case VPMAXUWZ256rmkz:
32612 case VPMAXUWZ256rr:
32613 case VPMAXUWZ256rrk:
32614 case VPMAXUWZ256rrkz:
32615 case VPMAXUWZrm:
32616 case VPMAXUWZrmk:
32617 case VPMAXUWZrmkz:
32618 case VPMAXUWZrr:
32619 case VPMAXUWZrrk:
32620 case VPMAXUWZrrkz:
32621 case VPMAXUWrm:
32622 case VPMAXUWrr:
32623 return true;
32624 }
32625 return false;
32626}
32627
32628bool isPAUSE(unsigned Opcode) {
32629 return Opcode == PAUSE;
32630}
32631
32632bool isMOVQ2DQ(unsigned Opcode) {
32633 return Opcode == MMX_MOVQ2DQrr;
32634}
32635
32636bool isVPSUBQ(unsigned Opcode) {
32637 switch (Opcode) {
32638 case VPSUBQYrm:
32639 case VPSUBQYrr:
32640 case VPSUBQZ128rm:
32641 case VPSUBQZ128rmb:
32642 case VPSUBQZ128rmbk:
32643 case VPSUBQZ128rmbkz:
32644 case VPSUBQZ128rmk:
32645 case VPSUBQZ128rmkz:
32646 case VPSUBQZ128rr:
32647 case VPSUBQZ128rrk:
32648 case VPSUBQZ128rrkz:
32649 case VPSUBQZ256rm:
32650 case VPSUBQZ256rmb:
32651 case VPSUBQZ256rmbk:
32652 case VPSUBQZ256rmbkz:
32653 case VPSUBQZ256rmk:
32654 case VPSUBQZ256rmkz:
32655 case VPSUBQZ256rr:
32656 case VPSUBQZ256rrk:
32657 case VPSUBQZ256rrkz:
32658 case VPSUBQZrm:
32659 case VPSUBQZrmb:
32660 case VPSUBQZrmbk:
32661 case VPSUBQZrmbkz:
32662 case VPSUBQZrmk:
32663 case VPSUBQZrmkz:
32664 case VPSUBQZrr:
32665 case VPSUBQZrrk:
32666 case VPSUBQZrrkz:
32667 case VPSUBQrm:
32668 case VPSUBQrr:
32669 return true;
32670 }
32671 return false;
32672}
32673
32674bool isVPABSW(unsigned Opcode) {
32675 switch (Opcode) {
32676 case VPABSWYrm:
32677 case VPABSWYrr:
32678 case VPABSWZ128rm:
32679 case VPABSWZ128rmk:
32680 case VPABSWZ128rmkz:
32681 case VPABSWZ128rr:
32682 case VPABSWZ128rrk:
32683 case VPABSWZ128rrkz:
32684 case VPABSWZ256rm:
32685 case VPABSWZ256rmk:
32686 case VPABSWZ256rmkz:
32687 case VPABSWZ256rr:
32688 case VPABSWZ256rrk:
32689 case VPABSWZ256rrkz:
32690 case VPABSWZrm:
32691 case VPABSWZrmk:
32692 case VPABSWZrmkz:
32693 case VPABSWZrr:
32694 case VPABSWZrrk:
32695 case VPABSWZrrkz:
32696 case VPABSWrm:
32697 case VPABSWrr:
32698 return true;
32699 }
32700 return false;
32701}
32702
32703bool isVPCOMPRESSD(unsigned Opcode) {
32704 switch (Opcode) {
32705 case VPCOMPRESSDZ128mr:
32706 case VPCOMPRESSDZ128mrk:
32707 case VPCOMPRESSDZ128rr:
32708 case VPCOMPRESSDZ128rrk:
32709 case VPCOMPRESSDZ128rrkz:
32710 case VPCOMPRESSDZ256mr:
32711 case VPCOMPRESSDZ256mrk:
32712 case VPCOMPRESSDZ256rr:
32713 case VPCOMPRESSDZ256rrk:
32714 case VPCOMPRESSDZ256rrkz:
32715 case VPCOMPRESSDZmr:
32716 case VPCOMPRESSDZmrk:
32717 case VPCOMPRESSDZrr:
32718 case VPCOMPRESSDZrrk:
32719 case VPCOMPRESSDZrrkz:
32720 return true;
32721 }
32722 return false;
32723}
32724
32725bool isVPMOVUSQW(unsigned Opcode) {
32726 switch (Opcode) {
32727 case VPMOVUSQWZ128mr:
32728 case VPMOVUSQWZ128mrk:
32729 case VPMOVUSQWZ128rr:
32730 case VPMOVUSQWZ128rrk:
32731 case VPMOVUSQWZ128rrkz:
32732 case VPMOVUSQWZ256mr:
32733 case VPMOVUSQWZ256mrk:
32734 case VPMOVUSQWZ256rr:
32735 case VPMOVUSQWZ256rrk:
32736 case VPMOVUSQWZ256rrkz:
32737 case VPMOVUSQWZmr:
32738 case VPMOVUSQWZmrk:
32739 case VPMOVUSQWZrr:
32740 case VPMOVUSQWZrrk:
32741 case VPMOVUSQWZrrkz:
32742 return true;
32743 }
32744 return false;
32745}
32746
32747bool isBLENDVPD(unsigned Opcode) {
32748 switch (Opcode) {
32749 case BLENDVPDrm0:
32750 case BLENDVPDrr0:
32751 return true;
32752 }
32753 return false;
32754}
32755
32756bool isVFNMADD132BF16(unsigned Opcode) {
32757 switch (Opcode) {
32758 case VFNMADD132BF16Z128m:
32759 case VFNMADD132BF16Z128mb:
32760 case VFNMADD132BF16Z128mbk:
32761 case VFNMADD132BF16Z128mbkz:
32762 case VFNMADD132BF16Z128mk:
32763 case VFNMADD132BF16Z128mkz:
32764 case VFNMADD132BF16Z128r:
32765 case VFNMADD132BF16Z128rk:
32766 case VFNMADD132BF16Z128rkz:
32767 case VFNMADD132BF16Z256m:
32768 case VFNMADD132BF16Z256mb:
32769 case VFNMADD132BF16Z256mbk:
32770 case VFNMADD132BF16Z256mbkz:
32771 case VFNMADD132BF16Z256mk:
32772 case VFNMADD132BF16Z256mkz:
32773 case VFNMADD132BF16Z256r:
32774 case VFNMADD132BF16Z256rk:
32775 case VFNMADD132BF16Z256rkz:
32776 case VFNMADD132BF16Zm:
32777 case VFNMADD132BF16Zmb:
32778 case VFNMADD132BF16Zmbk:
32779 case VFNMADD132BF16Zmbkz:
32780 case VFNMADD132BF16Zmk:
32781 case VFNMADD132BF16Zmkz:
32782 case VFNMADD132BF16Zr:
32783 case VFNMADD132BF16Zrk:
32784 case VFNMADD132BF16Zrkz:
32785 return true;
32786 }
32787 return false;
32788}
32789
32790bool isVPMOVQB(unsigned Opcode) {
32791 switch (Opcode) {
32792 case VPMOVQBZ128mr:
32793 case VPMOVQBZ128mrk:
32794 case VPMOVQBZ128rr:
32795 case VPMOVQBZ128rrk:
32796 case VPMOVQBZ128rrkz:
32797 case VPMOVQBZ256mr:
32798 case VPMOVQBZ256mrk:
32799 case VPMOVQBZ256rr:
32800 case VPMOVQBZ256rrk:
32801 case VPMOVQBZ256rrkz:
32802 case VPMOVQBZmr:
32803 case VPMOVQBZmrk:
32804 case VPMOVQBZrr:
32805 case VPMOVQBZrrk:
32806 case VPMOVQBZrrkz:
32807 return true;
32808 }
32809 return false;
32810}
32811
32812bool isVBLENDVPS(unsigned Opcode) {
32813 switch (Opcode) {
32814 case VBLENDVPSYrmr:
32815 case VBLENDVPSYrrr:
32816 case VBLENDVPSrmr:
32817 case VBLENDVPSrrr:
32818 return true;
32819 }
32820 return false;
32821}
32822
32823bool isKSHIFTLQ(unsigned Opcode) {
32824 return Opcode == KSHIFTLQki;
32825}
32826
32827bool isPMOVSXWD(unsigned Opcode) {
32828 switch (Opcode) {
32829 case PMOVSXWDrm:
32830 case PMOVSXWDrr:
32831 return true;
32832 }
32833 return false;
32834}
32835
32836bool isPHSUBSW(unsigned Opcode) {
32837 switch (Opcode) {
32838 case MMX_PHSUBSWrm:
32839 case MMX_PHSUBSWrr:
32840 case PHSUBSWrm:
32841 case PHSUBSWrr:
32842 return true;
32843 }
32844 return false;
32845}
32846
32847bool isPSRLQ(unsigned Opcode) {
32848 switch (Opcode) {
32849 case MMX_PSRLQri:
32850 case MMX_PSRLQrm:
32851 case MMX_PSRLQrr:
32852 case PSRLQri:
32853 case PSRLQrm:
32854 case PSRLQrr:
32855 return true;
32856 }
32857 return false;
32858}
32859
32860bool isVCVTPH2DQ(unsigned Opcode) {
32861 switch (Opcode) {
32862 case VCVTPH2DQZ128rm:
32863 case VCVTPH2DQZ128rmb:
32864 case VCVTPH2DQZ128rmbk:
32865 case VCVTPH2DQZ128rmbkz:
32866 case VCVTPH2DQZ128rmk:
32867 case VCVTPH2DQZ128rmkz:
32868 case VCVTPH2DQZ128rr:
32869 case VCVTPH2DQZ128rrk:
32870 case VCVTPH2DQZ128rrkz:
32871 case VCVTPH2DQZ256rm:
32872 case VCVTPH2DQZ256rmb:
32873 case VCVTPH2DQZ256rmbk:
32874 case VCVTPH2DQZ256rmbkz:
32875 case VCVTPH2DQZ256rmk:
32876 case VCVTPH2DQZ256rmkz:
32877 case VCVTPH2DQZ256rr:
32878 case VCVTPH2DQZ256rrk:
32879 case VCVTPH2DQZ256rrkz:
32880 case VCVTPH2DQZrm:
32881 case VCVTPH2DQZrmb:
32882 case VCVTPH2DQZrmbk:
32883 case VCVTPH2DQZrmbkz:
32884 case VCVTPH2DQZrmk:
32885 case VCVTPH2DQZrmkz:
32886 case VCVTPH2DQZrr:
32887 case VCVTPH2DQZrrb:
32888 case VCVTPH2DQZrrbk:
32889 case VCVTPH2DQZrrbkz:
32890 case VCVTPH2DQZrrk:
32891 case VCVTPH2DQZrrkz:
32892 return true;
32893 }
32894 return false;
32895}
32896
32897bool isPCMPESTRIQ(unsigned Opcode) {
32898 switch (Opcode) {
32899 case PCMPESTRIQrmi:
32900 case PCMPESTRIQrri:
32901 return true;
32902 }
32903 return false;
32904}
32905
32906bool isFISUB(unsigned Opcode) {
32907 switch (Opcode) {
32908 case SUB_FI16m:
32909 case SUB_FI32m:
32910 return true;
32911 }
32912 return false;
32913}
32914
32915bool isVCVTPS2UDQ(unsigned Opcode) {
32916 switch (Opcode) {
32917 case VCVTPS2UDQZ128rm:
32918 case VCVTPS2UDQZ128rmb:
32919 case VCVTPS2UDQZ128rmbk:
32920 case VCVTPS2UDQZ128rmbkz:
32921 case VCVTPS2UDQZ128rmk:
32922 case VCVTPS2UDQZ128rmkz:
32923 case VCVTPS2UDQZ128rr:
32924 case VCVTPS2UDQZ128rrk:
32925 case VCVTPS2UDQZ128rrkz:
32926 case VCVTPS2UDQZ256rm:
32927 case VCVTPS2UDQZ256rmb:
32928 case VCVTPS2UDQZ256rmbk:
32929 case VCVTPS2UDQZ256rmbkz:
32930 case VCVTPS2UDQZ256rmk:
32931 case VCVTPS2UDQZ256rmkz:
32932 case VCVTPS2UDQZ256rr:
32933 case VCVTPS2UDQZ256rrk:
32934 case VCVTPS2UDQZ256rrkz:
32935 case VCVTPS2UDQZrm:
32936 case VCVTPS2UDQZrmb:
32937 case VCVTPS2UDQZrmbk:
32938 case VCVTPS2UDQZrmbkz:
32939 case VCVTPS2UDQZrmk:
32940 case VCVTPS2UDQZrmkz:
32941 case VCVTPS2UDQZrr:
32942 case VCVTPS2UDQZrrb:
32943 case VCVTPS2UDQZrrbk:
32944 case VCVTPS2UDQZrrbkz:
32945 case VCVTPS2UDQZrrk:
32946 case VCVTPS2UDQZrrkz:
32947 return true;
32948 }
32949 return false;
32950}
32951
32952bool isVMOVDDUP(unsigned Opcode) {
32953 switch (Opcode) {
32954 case VMOVDDUPYrm:
32955 case VMOVDDUPYrr:
32956 case VMOVDDUPZ128rm:
32957 case VMOVDDUPZ128rmk:
32958 case VMOVDDUPZ128rmkz:
32959 case VMOVDDUPZ128rr:
32960 case VMOVDDUPZ128rrk:
32961 case VMOVDDUPZ128rrkz:
32962 case VMOVDDUPZ256rm:
32963 case VMOVDDUPZ256rmk:
32964 case VMOVDDUPZ256rmkz:
32965 case VMOVDDUPZ256rr:
32966 case VMOVDDUPZ256rrk:
32967 case VMOVDDUPZ256rrkz:
32968 case VMOVDDUPZrm:
32969 case VMOVDDUPZrmk:
32970 case VMOVDDUPZrmkz:
32971 case VMOVDDUPZrr:
32972 case VMOVDDUPZrrk:
32973 case VMOVDDUPZrrkz:
32974 case VMOVDDUPrm:
32975 case VMOVDDUPrr:
32976 return true;
32977 }
32978 return false;
32979}
32980
32981bool isPCMPEQD(unsigned Opcode) {
32982 switch (Opcode) {
32983 case MMX_PCMPEQDrm:
32984 case MMX_PCMPEQDrr:
32985 case PCMPEQDrm:
32986 case PCMPEQDrr:
32987 return true;
32988 }
32989 return false;
32990}
32991
32992bool isVRSQRT28SD(unsigned Opcode) {
32993 switch (Opcode) {
32994 case VRSQRT28SDZm:
32995 case VRSQRT28SDZmk:
32996 case VRSQRT28SDZmkz:
32997 case VRSQRT28SDZr:
32998 case VRSQRT28SDZrb:
32999 case VRSQRT28SDZrbk:
33000 case VRSQRT28SDZrbkz:
33001 case VRSQRT28SDZrk:
33002 case VRSQRT28SDZrkz:
33003 return true;
33004 }
33005 return false;
33006}
33007
33008bool isTDPHBF8PS(unsigned Opcode) {
33009 return Opcode == TDPHBF8PS;
33010}
33011
33012bool isLODSW(unsigned Opcode) {
33013 return Opcode == LODSW;
33014}
33015
33016bool isVPOPCNTQ(unsigned Opcode) {
33017 switch (Opcode) {
33018 case VPOPCNTQZ128rm:
33019 case VPOPCNTQZ128rmb:
33020 case VPOPCNTQZ128rmbk:
33021 case VPOPCNTQZ128rmbkz:
33022 case VPOPCNTQZ128rmk:
33023 case VPOPCNTQZ128rmkz:
33024 case VPOPCNTQZ128rr:
33025 case VPOPCNTQZ128rrk:
33026 case VPOPCNTQZ128rrkz:
33027 case VPOPCNTQZ256rm:
33028 case VPOPCNTQZ256rmb:
33029 case VPOPCNTQZ256rmbk:
33030 case VPOPCNTQZ256rmbkz:
33031 case VPOPCNTQZ256rmk:
33032 case VPOPCNTQZ256rmkz:
33033 case VPOPCNTQZ256rr:
33034 case VPOPCNTQZ256rrk:
33035 case VPOPCNTQZ256rrkz:
33036 case VPOPCNTQZrm:
33037 case VPOPCNTQZrmb:
33038 case VPOPCNTQZrmbk:
33039 case VPOPCNTQZrmbkz:
33040 case VPOPCNTQZrmk:
33041 case VPOPCNTQZrmkz:
33042 case VPOPCNTQZrr:
33043 case VPOPCNTQZrrk:
33044 case VPOPCNTQZrrkz:
33045 return true;
33046 }
33047 return false;
33048}
33049
33050bool isKSHIFTRB(unsigned Opcode) {
33051 return Opcode == KSHIFTRBki;
33052}
33053
33054bool isVFNMADDPS(unsigned Opcode) {
33055 switch (Opcode) {
33056 case VFNMADDPS4Ymr:
33057 case VFNMADDPS4Yrm:
33058 case VFNMADDPS4Yrr:
33059 case VFNMADDPS4Yrr_REV:
33060 case VFNMADDPS4mr:
33061 case VFNMADDPS4rm:
33062 case VFNMADDPS4rr:
33063 case VFNMADDPS4rr_REV:
33064 return true;
33065 }
33066 return false;
33067}
33068
33069bool isCCMPCC(unsigned Opcode) {
33070 switch (Opcode) {
33071 case CCMP16mi:
33072 case CCMP16mi8:
33073 case CCMP16mr:
33074 case CCMP16ri:
33075 case CCMP16ri8:
33076 case CCMP16rm:
33077 case CCMP16rr:
33078 case CCMP16rr_REV:
33079 case CCMP32mi:
33080 case CCMP32mi8:
33081 case CCMP32mr:
33082 case CCMP32ri:
33083 case CCMP32ri8:
33084 case CCMP32rm:
33085 case CCMP32rr:
33086 case CCMP32rr_REV:
33087 case CCMP64mi32:
33088 case CCMP64mi8:
33089 case CCMP64mr:
33090 case CCMP64ri32:
33091 case CCMP64ri8:
33092 case CCMP64rm:
33093 case CCMP64rr:
33094 case CCMP64rr_REV:
33095 case CCMP8mi:
33096 case CCMP8mr:
33097 case CCMP8ri:
33098 case CCMP8rm:
33099 case CCMP8rr:
33100 case CCMP8rr_REV:
33101 return true;
33102 }
33103 return false;
33104}
33105
33106bool isFXRSTOR64(unsigned Opcode) {
33107 return Opcode == FXRSTOR64;
33108}
33109
33110bool isVFMSUBADD213PD(unsigned Opcode) {
33111 switch (Opcode) {
33112 case VFMSUBADD213PDYm:
33113 case VFMSUBADD213PDYr:
33114 case VFMSUBADD213PDZ128m:
33115 case VFMSUBADD213PDZ128mb:
33116 case VFMSUBADD213PDZ128mbk:
33117 case VFMSUBADD213PDZ128mbkz:
33118 case VFMSUBADD213PDZ128mk:
33119 case VFMSUBADD213PDZ128mkz:
33120 case VFMSUBADD213PDZ128r:
33121 case VFMSUBADD213PDZ128rk:
33122 case VFMSUBADD213PDZ128rkz:
33123 case VFMSUBADD213PDZ256m:
33124 case VFMSUBADD213PDZ256mb:
33125 case VFMSUBADD213PDZ256mbk:
33126 case VFMSUBADD213PDZ256mbkz:
33127 case VFMSUBADD213PDZ256mk:
33128 case VFMSUBADD213PDZ256mkz:
33129 case VFMSUBADD213PDZ256r:
33130 case VFMSUBADD213PDZ256rk:
33131 case VFMSUBADD213PDZ256rkz:
33132 case VFMSUBADD213PDZm:
33133 case VFMSUBADD213PDZmb:
33134 case VFMSUBADD213PDZmbk:
33135 case VFMSUBADD213PDZmbkz:
33136 case VFMSUBADD213PDZmk:
33137 case VFMSUBADD213PDZmkz:
33138 case VFMSUBADD213PDZr:
33139 case VFMSUBADD213PDZrb:
33140 case VFMSUBADD213PDZrbk:
33141 case VFMSUBADD213PDZrbkz:
33142 case VFMSUBADD213PDZrk:
33143 case VFMSUBADD213PDZrkz:
33144 case VFMSUBADD213PDm:
33145 case VFMSUBADD213PDr:
33146 return true;
33147 }
33148 return false;
33149}
33150
33151bool isVSQRTPH(unsigned Opcode) {
33152 switch (Opcode) {
33153 case VSQRTPHZ128m:
33154 case VSQRTPHZ128mb:
33155 case VSQRTPHZ128mbk:
33156 case VSQRTPHZ128mbkz:
33157 case VSQRTPHZ128mk:
33158 case VSQRTPHZ128mkz:
33159 case VSQRTPHZ128r:
33160 case VSQRTPHZ128rk:
33161 case VSQRTPHZ128rkz:
33162 case VSQRTPHZ256m:
33163 case VSQRTPHZ256mb:
33164 case VSQRTPHZ256mbk:
33165 case VSQRTPHZ256mbkz:
33166 case VSQRTPHZ256mk:
33167 case VSQRTPHZ256mkz:
33168 case VSQRTPHZ256r:
33169 case VSQRTPHZ256rk:
33170 case VSQRTPHZ256rkz:
33171 case VSQRTPHZm:
33172 case VSQRTPHZmb:
33173 case VSQRTPHZmbk:
33174 case VSQRTPHZmbkz:
33175 case VSQRTPHZmk:
33176 case VSQRTPHZmkz:
33177 case VSQRTPHZr:
33178 case VSQRTPHZrb:
33179 case VSQRTPHZrbk:
33180 case VSQRTPHZrbkz:
33181 case VSQRTPHZrk:
33182 case VSQRTPHZrkz:
33183 return true;
33184 }
33185 return false;
33186}
33187
33188bool isPOPF(unsigned Opcode) {
33189 return Opcode == POPF16;
33190}
33191
33192bool isVPSUBUSB(unsigned Opcode) {
33193 switch (Opcode) {
33194 case VPSUBUSBYrm:
33195 case VPSUBUSBYrr:
33196 case VPSUBUSBZ128rm:
33197 case VPSUBUSBZ128rmk:
33198 case VPSUBUSBZ128rmkz:
33199 case VPSUBUSBZ128rr:
33200 case VPSUBUSBZ128rrk:
33201 case VPSUBUSBZ128rrkz:
33202 case VPSUBUSBZ256rm:
33203 case VPSUBUSBZ256rmk:
33204 case VPSUBUSBZ256rmkz:
33205 case VPSUBUSBZ256rr:
33206 case VPSUBUSBZ256rrk:
33207 case VPSUBUSBZ256rrkz:
33208 case VPSUBUSBZrm:
33209 case VPSUBUSBZrmk:
33210 case VPSUBUSBZrmkz:
33211 case VPSUBUSBZrr:
33212 case VPSUBUSBZrrk:
33213 case VPSUBUSBZrrkz:
33214 case VPSUBUSBrm:
33215 case VPSUBUSBrr:
33216 return true;
33217 }
33218 return false;
33219}
33220
33221bool isTCVTROWPS2BF16L(unsigned Opcode) {
33222 switch (Opcode) {
33223 case TCVTROWPS2BF16Lrte:
33224 case TCVTROWPS2BF16Lrti:
33225 return true;
33226 }
33227 return false;
33228}
33229
33230bool isPREFETCHIT1(unsigned Opcode) {
33231 return Opcode == PREFETCHIT1;
33232}
33233
33234bool isVPADDSW(unsigned Opcode) {
33235 switch (Opcode) {
33236 case VPADDSWYrm:
33237 case VPADDSWYrr:
33238 case VPADDSWZ128rm:
33239 case VPADDSWZ128rmk:
33240 case VPADDSWZ128rmkz:
33241 case VPADDSWZ128rr:
33242 case VPADDSWZ128rrk:
33243 case VPADDSWZ128rrkz:
33244 case VPADDSWZ256rm:
33245 case VPADDSWZ256rmk:
33246 case VPADDSWZ256rmkz:
33247 case VPADDSWZ256rr:
33248 case VPADDSWZ256rrk:
33249 case VPADDSWZ256rrkz:
33250 case VPADDSWZrm:
33251 case VPADDSWZrmk:
33252 case VPADDSWZrmkz:
33253 case VPADDSWZrr:
33254 case VPADDSWZrrk:
33255 case VPADDSWZrrkz:
33256 case VPADDSWrm:
33257 case VPADDSWrr:
33258 return true;
33259 }
33260 return false;
33261}
33262
33263bool isVADDSUBPD(unsigned Opcode) {
33264 switch (Opcode) {
33265 case VADDSUBPDYrm:
33266 case VADDSUBPDYrr:
33267 case VADDSUBPDrm:
33268 case VADDSUBPDrr:
33269 return true;
33270 }
33271 return false;
33272}
33273
33274bool isKANDD(unsigned Opcode) {
33275 return Opcode == KANDDkk;
33276}
33277
33278bool isOUTSB(unsigned Opcode) {
33279 return Opcode == OUTSB;
33280}
33281
33282bool isPREFETCHRST2(unsigned Opcode) {
33283 return Opcode == PREFETCHRST2;
33284}
33285
33286bool isFNSTSW(unsigned Opcode) {
33287 switch (Opcode) {
33288 case FNSTSW16r:
33289 case FNSTSWm:
33290 return true;
33291 }
33292 return false;
33293}
33294
33295bool isPMINSB(unsigned Opcode) {
33296 switch (Opcode) {
33297 case PMINSBrm:
33298 case PMINSBrr:
33299 return true;
33300 }
33301 return false;
33302}
33303
33304
33305} // namespace llvm::X86
33306
33307#endif // GET_X86_MNEMONIC_TABLES_CPP
33308
33309