1//===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/X86BaseInfo.h"
10#include "MCTargetDesc/X86EncodingOptimization.h"
11#include "MCTargetDesc/X86IntelInstPrinter.h"
12#include "MCTargetDesc/X86MCAsmInfo.h"
13#include "MCTargetDesc/X86MCExpr.h"
14#include "MCTargetDesc/X86MCTargetDesc.h"
15#include "MCTargetDesc/X86TargetStreamer.h"
16#include "TargetInfo/X86TargetInfo.h"
17#include "X86Operand.h"
18#include "X86RegisterInfo.h"
19#include "llvm-c/Visibility.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/SmallString.h"
22#include "llvm/ADT/SmallVector.h"
23#include "llvm/ADT/StringRef.h"
24#include "llvm/ADT/StringSwitch.h"
25#include "llvm/ADT/Twine.h"
26#include "llvm/MC/MCContext.h"
27#include "llvm/MC/MCExpr.h"
28#include "llvm/MC/MCInst.h"
29#include "llvm/MC/MCInstrInfo.h"
30#include "llvm/MC/MCParser/AsmLexer.h"
31#include "llvm/MC/MCParser/MCAsmParser.h"
32#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
33#include "llvm/MC/MCParser/MCTargetAsmParser.h"
34#include "llvm/MC/MCRegister.h"
35#include "llvm/MC/MCRegisterInfo.h"
36#include "llvm/MC/MCSection.h"
37#include "llvm/MC/MCStreamer.h"
38#include "llvm/MC/MCSubtargetInfo.h"
39#include "llvm/MC/MCSymbol.h"
40#include "llvm/MC/TargetRegistry.h"
41#include "llvm/Support/CommandLine.h"
42#include "llvm/Support/Compiler.h"
43#include "llvm/Support/SourceMgr.h"
44#include "llvm/Support/raw_ostream.h"
45#include <algorithm>
46#include <cstdint>
47#include <memory>
48#include <optional>
49
50using namespace llvm;
51
52static cl::opt<bool> LVIInlineAsmHardening(
53 "x86-experimental-lvi-inline-asm-hardening",
54 cl::desc("Harden inline assembly code that may be vulnerable to Load Value"
55 " Injection (LVI). This feature is experimental."), cl::Hidden);
56
57static bool checkScale(unsigned Scale, StringRef &ErrMsg) {
58 if (Scale != 1 && Scale != 2 && Scale != 4 && Scale != 8) {
59 ErrMsg = "scale factor in address must be 1, 2, 4 or 8";
60 return true;
61 }
62 return false;
63}
64
65namespace {
66
67// Including the generated SSE2AVX compression tables.
68#define GET_X86_SSE2AVX_TABLE
69#include "X86GenInstrMapping.inc"
70
71static const char OpPrecedence[] = {
72 0, // IC_OR
73 1, // IC_XOR
74 2, // IC_AND
75 4, // IC_LSHIFT
76 4, // IC_RSHIFT
77 5, // IC_PLUS
78 5, // IC_MINUS
79 6, // IC_MULTIPLY
80 6, // IC_DIVIDE
81 6, // IC_MOD
82 7, // IC_NOT
83 8, // IC_NEG
84 9, // IC_RPAREN
85 10, // IC_LPAREN
86 0, // IC_IMM
87 0, // IC_REGISTER
88 3, // IC_EQ
89 3, // IC_NE
90 3, // IC_LT
91 3, // IC_LE
92 3, // IC_GT
93 3 // IC_GE
94};
95
96class X86AsmParser : public MCTargetAsmParser {
97 ParseInstructionInfo *InstInfo;
98 bool Code16GCC;
99 unsigned ForcedDataPrefix = 0;
100
101 enum OpcodePrefix {
102 OpcodePrefix_Default,
103 OpcodePrefix_REX,
104 OpcodePrefix_REX2,
105 OpcodePrefix_VEX,
106 OpcodePrefix_VEX2,
107 OpcodePrefix_VEX3,
108 OpcodePrefix_EVEX,
109 };
110
111 OpcodePrefix ForcedOpcodePrefix = OpcodePrefix_Default;
112
113 enum DispEncoding {
114 DispEncoding_Default,
115 DispEncoding_Disp8,
116 DispEncoding_Disp32,
117 };
118
119 DispEncoding ForcedDispEncoding = DispEncoding_Default;
120
121 // Does this instruction use apx extended register?
122 bool UseApxExtendedReg = false;
123 // Is this instruction explicitly required not to update flags?
124 bool ForcedNoFlag = false;
125
126private:
127 SMLoc consumeToken() {
128 MCAsmParser &Parser = getParser();
129 SMLoc Result = Parser.getTok().getLoc();
130 Parser.Lex();
131 return Result;
132 }
133
134 bool tokenIsStartOfStatement(AsmToken::TokenKind Token) override {
135 return Token == AsmToken::LCurly;
136 }
137
138 X86TargetStreamer &getTargetStreamer() {
139 assert(getParser().getStreamer().getTargetStreamer() &&
140 "do not have a target streamer");
141 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
142 return static_cast<X86TargetStreamer &>(TS);
143 }
144
145 unsigned MatchInstruction(const OperandVector &Operands, MCInst &Inst,
146 uint64_t &ErrorInfo, FeatureBitset &MissingFeatures,
147 bool matchingInlineAsm, unsigned VariantID = 0) {
148 // In Code16GCC mode, match as 32-bit.
149 if (Code16GCC)
150 SwitchMode(mode: X86::Is32Bit);
151 unsigned rv = MatchInstructionImpl(Operands, Inst, ErrorInfo,
152 MissingFeatures, matchingInlineAsm,
153 VariantID);
154 if (Code16GCC)
155 SwitchMode(mode: X86::Is16Bit);
156 return rv;
157 }
158
159 enum InfixCalculatorTok {
160 IC_OR = 0,
161 IC_XOR,
162 IC_AND,
163 IC_LSHIFT,
164 IC_RSHIFT,
165 IC_PLUS,
166 IC_MINUS,
167 IC_MULTIPLY,
168 IC_DIVIDE,
169 IC_MOD,
170 IC_NOT,
171 IC_NEG,
172 IC_RPAREN,
173 IC_LPAREN,
174 IC_IMM,
175 IC_REGISTER,
176 IC_EQ,
177 IC_NE,
178 IC_LT,
179 IC_LE,
180 IC_GT,
181 IC_GE
182 };
183
184 enum IntelOperatorKind {
185 IOK_INVALID = 0,
186 IOK_LENGTH,
187 IOK_SIZE,
188 IOK_TYPE,
189 };
190
191 enum MasmOperatorKind {
192 MOK_INVALID = 0,
193 MOK_LENGTHOF,
194 MOK_SIZEOF,
195 MOK_TYPE,
196 };
197
198 class InfixCalculator {
199 typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
200 SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
201 SmallVector<ICToken, 4> PostfixStack;
202
203 bool isUnaryOperator(InfixCalculatorTok Op) const {
204 return Op == IC_NEG || Op == IC_NOT;
205 }
206
207 public:
208 int64_t popOperand() {
209 assert (!PostfixStack.empty() && "Poped an empty stack!");
210 ICToken Op = PostfixStack.pop_back_val();
211 if (!(Op.first == IC_IMM || Op.first == IC_REGISTER))
212 return -1; // The invalid Scale value will be caught later by checkScale
213 return Op.second;
214 }
215 void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
216 assert ((Op == IC_IMM || Op == IC_REGISTER) &&
217 "Unexpected operand!");
218 PostfixStack.push_back(Elt: std::make_pair(x&: Op, y&: Val));
219 }
220
221 void popOperator() { InfixOperatorStack.pop_back(); }
222 void pushOperator(InfixCalculatorTok Op) {
223 // Push the new operator if the stack is empty.
224 if (InfixOperatorStack.empty()) {
225 InfixOperatorStack.push_back(Elt: Op);
226 return;
227 }
228
229 // Push the new operator if it has a higher precedence than the operator
230 // on the top of the stack or the operator on the top of the stack is a
231 // left parentheses.
232 unsigned Idx = InfixOperatorStack.size() - 1;
233 InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
234 if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
235 InfixOperatorStack.push_back(Elt: Op);
236 return;
237 }
238
239 // The operator on the top of the stack has higher precedence than the
240 // new operator.
241 unsigned ParenCount = 0;
242 while (true) {
243 // Nothing to process.
244 if (InfixOperatorStack.empty())
245 break;
246
247 Idx = InfixOperatorStack.size() - 1;
248 StackOp = InfixOperatorStack[Idx];
249 if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
250 break;
251
252 // If we have an even parentheses count and we see a left parentheses,
253 // then stop processing.
254 if (!ParenCount && StackOp == IC_LPAREN)
255 break;
256
257 if (StackOp == IC_RPAREN) {
258 ++ParenCount;
259 InfixOperatorStack.pop_back();
260 } else if (StackOp == IC_LPAREN) {
261 --ParenCount;
262 InfixOperatorStack.pop_back();
263 } else {
264 InfixOperatorStack.pop_back();
265 PostfixStack.push_back(Elt: std::make_pair(x&: StackOp, y: 0));
266 }
267 }
268 // Push the new operator.
269 InfixOperatorStack.push_back(Elt: Op);
270 }
271
272 int64_t execute() {
273 // Push any remaining operators onto the postfix stack.
274 while (!InfixOperatorStack.empty()) {
275 InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
276 if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
277 PostfixStack.push_back(Elt: std::make_pair(x&: StackOp, y: 0));
278 }
279
280 if (PostfixStack.empty())
281 return 0;
282
283 SmallVector<ICToken, 16> OperandStack;
284 for (const ICToken &Op : PostfixStack) {
285 if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
286 OperandStack.push_back(Elt: Op);
287 } else if (isUnaryOperator(Op: Op.first)) {
288 assert (OperandStack.size() > 0 && "Too few operands.");
289 ICToken Operand = OperandStack.pop_back_val();
290 assert (Operand.first == IC_IMM &&
291 "Unary operation with a register!");
292 switch (Op.first) {
293 default:
294 report_fatal_error(reason: "Unexpected operator!");
295 break;
296 case IC_NEG:
297 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y: -Operand.second));
298 break;
299 case IC_NOT:
300 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y: ~Operand.second));
301 break;
302 }
303 } else {
304 assert (OperandStack.size() > 1 && "Too few operands.");
305 int64_t Val;
306 ICToken Op2 = OperandStack.pop_back_val();
307 ICToken Op1 = OperandStack.pop_back_val();
308 switch (Op.first) {
309 default:
310 report_fatal_error(reason: "Unexpected operator!");
311 break;
312 case IC_PLUS:
313 Val = Op1.second + Op2.second;
314 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
315 break;
316 case IC_MINUS:
317 Val = Op1.second - Op2.second;
318 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
319 break;
320 case IC_MULTIPLY:
321 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
322 "Multiply operation with an immediate and a register!");
323 Val = Op1.second * Op2.second;
324 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
325 break;
326 case IC_DIVIDE:
327 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
328 "Divide operation with an immediate and a register!");
329 assert (Op2.second != 0 && "Division by zero!");
330 Val = Op1.second / Op2.second;
331 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
332 break;
333 case IC_MOD:
334 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
335 "Modulo operation with an immediate and a register!");
336 Val = Op1.second % Op2.second;
337 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
338 break;
339 case IC_OR:
340 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
341 "Or operation with an immediate and a register!");
342 Val = Op1.second | Op2.second;
343 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
344 break;
345 case IC_XOR:
346 assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
347 "Xor operation with an immediate and a register!");
348 Val = Op1.second ^ Op2.second;
349 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
350 break;
351 case IC_AND:
352 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
353 "And operation with an immediate and a register!");
354 Val = Op1.second & Op2.second;
355 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
356 break;
357 case IC_LSHIFT:
358 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
359 "Left shift operation with an immediate and a register!");
360 Val = Op1.second << Op2.second;
361 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
362 break;
363 case IC_RSHIFT:
364 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
365 "Right shift operation with an immediate and a register!");
366 Val = Op1.second >> Op2.second;
367 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
368 break;
369 case IC_EQ:
370 assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
371 "Equals operation with an immediate and a register!");
372 Val = (Op1.second == Op2.second) ? -1 : 0;
373 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
374 break;
375 case IC_NE:
376 assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
377 "Not-equals operation with an immediate and a register!");
378 Val = (Op1.second != Op2.second) ? -1 : 0;
379 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
380 break;
381 case IC_LT:
382 assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
383 "Less-than operation with an immediate and a register!");
384 Val = (Op1.second < Op2.second) ? -1 : 0;
385 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
386 break;
387 case IC_LE:
388 assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
389 "Less-than-or-equal operation with an immediate and a "
390 "register!");
391 Val = (Op1.second <= Op2.second) ? -1 : 0;
392 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
393 break;
394 case IC_GT:
395 assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
396 "Greater-than operation with an immediate and a register!");
397 Val = (Op1.second > Op2.second) ? -1 : 0;
398 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
399 break;
400 case IC_GE:
401 assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
402 "Greater-than-or-equal operation with an immediate and a "
403 "register!");
404 Val = (Op1.second >= Op2.second) ? -1 : 0;
405 OperandStack.push_back(Elt: std::make_pair(x: IC_IMM, y&: Val));
406 break;
407 }
408 }
409 }
410 assert (OperandStack.size() == 1 && "Expected a single result.");
411 return OperandStack.pop_back_val().second;
412 }
413 };
414
415 enum IntelExprState {
416 IES_INIT,
417 IES_OR,
418 IES_XOR,
419 IES_AND,
420 IES_EQ,
421 IES_NE,
422 IES_LT,
423 IES_LE,
424 IES_GT,
425 IES_GE,
426 IES_LSHIFT,
427 IES_RSHIFT,
428 IES_PLUS,
429 IES_MINUS,
430 IES_OFFSET,
431 IES_CAST,
432 IES_NOT,
433 IES_MULTIPLY,
434 IES_DIVIDE,
435 IES_MOD,
436 IES_LBRAC,
437 IES_RBRAC,
438 IES_LPAREN,
439 IES_RPAREN,
440 IES_REGISTER,
441 IES_INTEGER,
442 IES_ERROR
443 };
444
445 class IntelExprStateMachine {
446 IntelExprState State = IES_INIT, PrevState = IES_ERROR;
447 MCRegister BaseReg, IndexReg, TmpReg;
448 unsigned Scale = 0;
449 std::optional<unsigned> TmpScale = {};
450 int64_t Imm = 0;
451 const MCExpr *Sym = nullptr;
452 StringRef SymName;
453 InfixCalculator IC;
454 InlineAsmIdentifierInfo Info;
455 short BracCount = 0;
456 short ParenCount = 0;
457 SMLoc LParenLoc;
458 bool MemExpr = false;
459 bool BracketUsed = false;
460 bool NegativeAdditiveTerm = false;
461 SMLoc NegativeAdditiveTermLoc;
462 bool OffsetOperator = false;
463 bool AttachToOperandIdx = false;
464 bool IsPIC = false;
465 AsmTypeInfo CurType;
466
467 bool setSymRef(const MCExpr *Val, StringRef ID, StringRef &ErrMsg) {
468 if (Sym) {
469 ErrMsg = "cannot use more than one symbol in memory operand";
470 return true;
471 }
472 Sym = Val;
473 SymName = ID;
474 return false;
475 }
476
477 public:
478 IntelExprStateMachine() = default;
479
480 void addImm(int64_t imm) { Imm += imm; }
481 short getBracCount() const { return BracCount; }
482 bool isMemExpr() const { return MemExpr; }
483 bool isBracketUsed() const { return BracketUsed; }
484 bool isOffsetOperator() const { return OffsetOperator; }
485 MCRegister getBaseReg() const { return BaseReg; }
486 MCRegister getIndexReg() const { return IndexReg; }
487 unsigned getScale() const { return Scale; }
488 const MCExpr *getSym() const { return Sym; }
489 StringRef getSymName() const { return SymName; }
490 StringRef getType() const { return CurType.Name; }
491 unsigned getSize() const { return CurType.Size; }
492 unsigned getElementSize() const { return CurType.ElementSize; }
493 unsigned getLength() const { return CurType.Length; }
494 int64_t getImm() { return Imm + IC.execute(); }
495 bool isValidEndState() const {
496 return State == IES_RBRAC || State == IES_RPAREN ||
497 State == IES_INTEGER || State == IES_REGISTER ||
498 State == IES_OFFSET;
499 }
500 bool hasUnmatchedParen() const { return ParenCount != 0; }
501 SMLoc getLParenLoc() const { return LParenLoc; }
502
503 // Is the intel expression appended after an operand index.
504 // [OperandIdx][Intel Expression]
505 // This is neccessary for checking if it is an independent
506 // intel expression at back end when parse inline asm.
507 void setAppendAfterOperand() { AttachToOperandIdx = true; }
508
509 bool isPIC() const { return IsPIC; }
510 void setPIC() { IsPIC = true; }
511
512 bool hadError() const { return State == IES_ERROR; }
513 SMLoc getErrorLoc(SMLoc DefaultLoc) const {
514 return NegativeAdditiveTerm ? NegativeAdditiveTermLoc : DefaultLoc;
515 }
516 const InlineAsmIdentifierInfo &getIdentifierInfo() const { return Info; }
517
518 bool regsUseUpError(StringRef &ErrMsg) {
519 // This case mostly happen in inline asm, e.g. Arr[BaseReg + IndexReg]
520 // can not intruduce additional register in inline asm in PIC model.
521 if (IsPIC && AttachToOperandIdx)
522 ErrMsg = "Don't use 2 or more regs for mem offset in PIC model!";
523 else
524 ErrMsg = "BaseReg/IndexReg already set!";
525 return true;
526 }
527
528 void onOr() {
529 IntelExprState CurrState = State;
530 switch (State) {
531 default:
532 State = IES_ERROR;
533 break;
534 case IES_INTEGER:
535 case IES_RPAREN:
536 case IES_REGISTER:
537 State = IES_OR;
538 IC.pushOperator(Op: IC_OR);
539 break;
540 }
541 PrevState = CurrState;
542 }
543 void onXor() {
544 IntelExprState CurrState = State;
545 switch (State) {
546 default:
547 State = IES_ERROR;
548 break;
549 case IES_INTEGER:
550 case IES_RPAREN:
551 case IES_REGISTER:
552 State = IES_XOR;
553 IC.pushOperator(Op: IC_XOR);
554 break;
555 }
556 PrevState = CurrState;
557 }
558 void onAnd() {
559 IntelExprState CurrState = State;
560 switch (State) {
561 default:
562 State = IES_ERROR;
563 break;
564 case IES_INTEGER:
565 case IES_RPAREN:
566 case IES_REGISTER:
567 State = IES_AND;
568 IC.pushOperator(Op: IC_AND);
569 break;
570 }
571 PrevState = CurrState;
572 }
573 void onEq() {
574 IntelExprState CurrState = State;
575 switch (State) {
576 default:
577 State = IES_ERROR;
578 break;
579 case IES_INTEGER:
580 case IES_RPAREN:
581 case IES_REGISTER:
582 State = IES_EQ;
583 IC.pushOperator(Op: IC_EQ);
584 break;
585 }
586 PrevState = CurrState;
587 }
588 void onNE() {
589 IntelExprState CurrState = State;
590 switch (State) {
591 default:
592 State = IES_ERROR;
593 break;
594 case IES_INTEGER:
595 case IES_RPAREN:
596 case IES_REGISTER:
597 State = IES_NE;
598 IC.pushOperator(Op: IC_NE);
599 break;
600 }
601 PrevState = CurrState;
602 }
603 void onLT() {
604 IntelExprState CurrState = State;
605 switch (State) {
606 default:
607 State = IES_ERROR;
608 break;
609 case IES_INTEGER:
610 case IES_RPAREN:
611 case IES_REGISTER:
612 State = IES_LT;
613 IC.pushOperator(Op: IC_LT);
614 break;
615 }
616 PrevState = CurrState;
617 }
618 void onLE() {
619 IntelExprState CurrState = State;
620 switch (State) {
621 default:
622 State = IES_ERROR;
623 break;
624 case IES_INTEGER:
625 case IES_RPAREN:
626 case IES_REGISTER:
627 State = IES_LE;
628 IC.pushOperator(Op: IC_LE);
629 break;
630 }
631 PrevState = CurrState;
632 }
633 void onGT() {
634 IntelExprState CurrState = State;
635 switch (State) {
636 default:
637 State = IES_ERROR;
638 break;
639 case IES_INTEGER:
640 case IES_RPAREN:
641 case IES_REGISTER:
642 State = IES_GT;
643 IC.pushOperator(Op: IC_GT);
644 break;
645 }
646 PrevState = CurrState;
647 }
648 void onGE() {
649 IntelExprState CurrState = State;
650 switch (State) {
651 default:
652 State = IES_ERROR;
653 break;
654 case IES_INTEGER:
655 case IES_RPAREN:
656 case IES_REGISTER:
657 State = IES_GE;
658 IC.pushOperator(Op: IC_GE);
659 break;
660 }
661 PrevState = CurrState;
662 }
663 void onLShift() {
664 IntelExprState CurrState = State;
665 switch (State) {
666 default:
667 State = IES_ERROR;
668 break;
669 case IES_INTEGER:
670 case IES_RPAREN:
671 case IES_REGISTER:
672 State = IES_LSHIFT;
673 IC.pushOperator(Op: IC_LSHIFT);
674 break;
675 }
676 PrevState = CurrState;
677 }
678 void onRShift() {
679 IntelExprState CurrState = State;
680 switch (State) {
681 default:
682 State = IES_ERROR;
683 break;
684 case IES_INTEGER:
685 case IES_RPAREN:
686 case IES_REGISTER:
687 State = IES_RSHIFT;
688 IC.pushOperator(Op: IC_RSHIFT);
689 break;
690 }
691 PrevState = CurrState;
692 }
693 bool onPlus(StringRef &ErrMsg) {
694 IntelExprState CurrState = State;
695 switch (State) {
696 default:
697 State = IES_ERROR;
698 break;
699 case IES_INTEGER:
700 case IES_RPAREN:
701 case IES_REGISTER:
702 case IES_OFFSET:
703 State = IES_PLUS;
704 IC.pushOperator(Op: IC_PLUS);
705 if (TmpReg) {
706 // A pending scale forces this to be the IndexReg; otherwise a free
707 // BaseReg takes it as an unscaled base.
708 if (!BaseReg && !TmpScale.has_value()) {
709 BaseReg = TmpReg;
710 TmpReg = MCRegister::NoRegister;
711 } else {
712 if (IndexReg)
713 return regsUseUpError(ErrMsg);
714 IndexReg = TmpReg;
715 TmpReg = MCRegister::NoRegister;
716 if (NegativeAdditiveTerm) {
717 ErrMsg = "Scale can't be negative";
718 return true;
719 }
720 if (TmpScale.has_value() && checkScale(Scale: TmpScale.value(), ErrMsg)) {
721 return true;
722 }
723 Scale = TmpScale.value_or(u: 0);
724 }
725 }
726 break;
727 }
728 NegativeAdditiveTerm = false;
729 NegativeAdditiveTermLoc = SMLoc();
730 // A '+' ends the current additive term, so clear the pending scale.
731 TmpScale.reset();
732 PrevState = CurrState;
733 return false;
734 }
735 bool onMinus(SMLoc MinusLoc, StringRef &ErrMsg) {
736 IntelExprState CurrState = State;
737 switch (State) {
738 default:
739 State = IES_ERROR;
740 break;
741 case IES_OR:
742 case IES_XOR:
743 case IES_AND:
744 case IES_EQ:
745 case IES_NE:
746 case IES_LT:
747 case IES_LE:
748 case IES_GT:
749 case IES_GE:
750 case IES_LSHIFT:
751 case IES_RSHIFT:
752 case IES_PLUS:
753 case IES_NOT:
754 case IES_MULTIPLY:
755 case IES_DIVIDE:
756 case IES_MOD:
757 case IES_LPAREN:
758 case IES_RPAREN:
759 case IES_LBRAC:
760 case IES_RBRAC:
761 case IES_INTEGER:
762 case IES_REGISTER:
763 case IES_INIT:
764 case IES_OFFSET:
765 State = IES_MINUS;
766 NegativeAdditiveTerm = true;
767 NegativeAdditiveTermLoc = MinusLoc;
768 // push minus operator if it is not a negate operator
769 if (CurrState == IES_REGISTER || CurrState == IES_RPAREN ||
770 CurrState == IES_INTEGER || CurrState == IES_RBRAC ||
771 CurrState == IES_OFFSET) {
772 IC.pushOperator(Op: IC_MINUS);
773 if (TmpReg) {
774 // A pending scale forces this to be the IndexReg; otherwise a free
775 // BaseReg takes it as an unscaled base.
776 if (!BaseReg && !TmpScale.has_value()) {
777 BaseReg = TmpReg;
778 TmpReg = MCRegister::NoRegister;
779 } else {
780 if (IndexReg)
781 return regsUseUpError(ErrMsg);
782 IndexReg = TmpReg;
783 TmpReg = MCRegister::NoRegister;
784 if (TmpScale.has_value() &&
785 checkScale(Scale: TmpScale.value(), ErrMsg)) {
786 return true;
787 }
788 Scale = TmpScale.value_or(u: 0);
789 }
790 }
791 } else if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
792 // We have negate operator for Scale: it's illegal
793 ErrMsg = "Scale can't be negative";
794 return true;
795 } else
796 IC.pushOperator(Op: IC_NEG);
797 break;
798 }
799 // A '-' ends the current additive term, so clear the pending scale.
800 TmpScale.reset();
801 PrevState = CurrState;
802 return false;
803 }
804 void onNot() {
805 IntelExprState CurrState = State;
806 switch (State) {
807 default:
808 State = IES_ERROR;
809 break;
810 case IES_OR:
811 case IES_XOR:
812 case IES_AND:
813 case IES_EQ:
814 case IES_NE:
815 case IES_LT:
816 case IES_LE:
817 case IES_GT:
818 case IES_GE:
819 case IES_LSHIFT:
820 case IES_RSHIFT:
821 case IES_PLUS:
822 case IES_MINUS:
823 case IES_NOT:
824 case IES_MULTIPLY:
825 case IES_DIVIDE:
826 case IES_MOD:
827 case IES_LPAREN:
828 case IES_LBRAC:
829 case IES_INIT:
830 State = IES_NOT;
831 IC.pushOperator(Op: IC_NOT);
832 break;
833 }
834 PrevState = CurrState;
835 }
836 bool onRegister(MCRegister Reg, StringRef &ErrMsg) {
837 IntelExprState CurrState = State;
838 switch (State) {
839 default:
840 State = IES_ERROR;
841 break;
842 case IES_PLUS:
843 case IES_MINUS:
844 case IES_LBRAC:
845 State = IES_REGISTER;
846 TmpReg = Reg;
847 IC.pushOperand(Op: IC_REGISTER);
848 if (NegativeAdditiveTerm) {
849 ErrMsg = "Scale can't be negative";
850 return true;
851 }
852 break;
853 case IES_LPAREN:
854 case IES_MULTIPLY:
855 // A register already held in TmpReg means we are multiplying two reg
856 if (TmpReg) {
857 ErrMsg = "Register can't be multiplied with register!";
858 return true;
859 }
860 State = IES_REGISTER;
861 TmpReg = Reg;
862 // Recognize this register as a scaled index register. This covers
863 // 'scale * reg' and 'scale * (reg)', including parenthesized or
864 // multi-factor scales where the accumulated value is held in TmpScale.
865 if (TmpScale.has_value()) {
866 if (IndexReg)
867 return regsUseUpError(ErrMsg);
868 if (NegativeAdditiveTerm) {
869 ErrMsg = "Scale can't be negative";
870 return true;
871 }
872 // Push an immediate, not the register, so the infix calculator
873 // won't evaluate reg * int; this is a scaled index reg.
874 IC.pushOperand(Op: IC_IMM);
875 } else {
876 IC.pushOperand(Op: IC_REGISTER);
877 }
878 break;
879 }
880 PrevState = CurrState;
881 return false;
882 }
883 bool onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName,
884 const InlineAsmIdentifierInfo &IDInfo,
885 const AsmTypeInfo &Type, bool ParsingMSInlineAsm,
886 StringRef &ErrMsg) {
887 // InlineAsm: Treat an enum value as an integer
888 if (ParsingMSInlineAsm)
889 if (IDInfo.isKind(kind: InlineAsmIdentifierInfo::IK_EnumVal))
890 return onInteger(TmpInt: IDInfo.Enum.EnumVal, ErrMsg);
891 // Treat a symbolic constant like an integer
892 if (auto *CE = dyn_cast<MCConstantExpr>(Val: SymRef))
893 return onInteger(TmpInt: CE->getValue(), ErrMsg);
894 PrevState = State;
895 switch (State) {
896 default:
897 State = IES_ERROR;
898 break;
899 case IES_CAST:
900 case IES_PLUS:
901 case IES_MINUS:
902 case IES_NOT:
903 case IES_INIT:
904 case IES_LBRAC:
905 case IES_LPAREN:
906 if (setSymRef(Val: SymRef, ID: SymRefName, ErrMsg))
907 return true;
908 // Mark TmpScale as invalid, in case of multiplying by register
909 TmpScale = 0;
910 MemExpr = true;
911 State = IES_INTEGER;
912 IC.pushOperand(Op: IC_IMM);
913 if (ParsingMSInlineAsm)
914 Info = IDInfo;
915 setTypeInfo(Type);
916 break;
917 }
918 return false;
919 }
920 bool onInteger(int64_t TmpInt, StringRef &ErrMsg) {
921 IntelExprState CurrState = State;
922 switch (State) {
923 default:
924 State = IES_ERROR;
925 break;
926 case IES_DIVIDE:
927 if (TmpInt == 0) {
928 ErrMsg = "division by zero in assembly expression";
929 State = IES_ERROR;
930 return true;
931 }
932 [[fallthrough]];
933 case IES_MOD:
934 if (TmpInt == 0) {
935 ErrMsg = "modulo by zero in assembly expression";
936 State = IES_ERROR;
937 return true;
938 }
939 [[fallthrough]];
940 case IES_PLUS:
941 case IES_MINUS:
942 case IES_NOT:
943 case IES_OR:
944 case IES_XOR:
945 case IES_AND:
946 case IES_EQ:
947 case IES_NE:
948 case IES_LT:
949 case IES_LE:
950 case IES_GT:
951 case IES_GE:
952 case IES_LSHIFT:
953 case IES_RSHIFT:
954 case IES_MULTIPLY:
955 case IES_LPAREN:
956 case IES_INIT:
957 case IES_LBRAC:
958 State = IES_INTEGER;
959 // Accumulate the scale: multiply into a pending scale or seed it.
960 if (TmpScale.has_value()) {
961 TmpScale.value() *= TmpInt;
962 } else {
963 TmpScale = TmpInt;
964 }
965 // Once an index register is pending, check if TmpScale is valid.
966 if (TmpReg && NegativeAdditiveTerm) {
967 ErrMsg = "Scale can't be negative";
968 return true;
969 }
970 if (TmpReg && checkScale(Scale: TmpScale.value(), ErrMsg))
971 return true;
972 IC.pushOperand(Op: IC_IMM, Val: TmpInt);
973 break;
974 }
975 PrevState = CurrState;
976 return false;
977 }
978 void onStar() {
979 PrevState = State;
980 switch (State) {
981 default:
982 State = IES_ERROR;
983 break;
984 case IES_INTEGER:
985 State = IES_MULTIPLY;
986 IC.pushOperator(Op: IC_MULTIPLY);
987 break;
988 case IES_REGISTER:
989 case IES_RPAREN:
990 // A register before '*' is a scaled index register. If no scale is
991 // pending yet, replace its operand-stack entry with an immediate so
992 // the infix calculator does not evaluate a reg * int product.
993 if (TmpReg && (!TmpScale.has_value())) {
994 IC.popOperand();
995 IC.pushOperand(Op: IC_IMM);
996 }
997 State = IES_MULTIPLY;
998 IC.pushOperator(Op: IC_MULTIPLY);
999 break;
1000 }
1001 }
1002 void onDivide() {
1003 PrevState = State;
1004 switch (State) {
1005 default:
1006 State = IES_ERROR;
1007 break;
1008 case IES_INTEGER:
1009 case IES_RPAREN:
1010 State = IES_DIVIDE;
1011 IC.pushOperator(Op: IC_DIVIDE);
1012 break;
1013 }
1014 }
1015 void onMod() {
1016 PrevState = State;
1017 switch (State) {
1018 default:
1019 State = IES_ERROR;
1020 break;
1021 case IES_INTEGER:
1022 case IES_RPAREN:
1023 State = IES_MOD;
1024 IC.pushOperator(Op: IC_MOD);
1025 break;
1026 }
1027 }
1028 bool onLBrac() {
1029 if (BracCount)
1030 return true;
1031 PrevState = State;
1032 switch (State) {
1033 default:
1034 State = IES_ERROR;
1035 break;
1036 case IES_RBRAC:
1037 case IES_INTEGER:
1038 case IES_RPAREN:
1039 State = IES_PLUS;
1040 IC.pushOperator(Op: IC_PLUS);
1041 CurType.Length = 1;
1042 CurType.Size = CurType.ElementSize;
1043 break;
1044 case IES_INIT:
1045 case IES_CAST:
1046 assert(!BracCount && "BracCount should be zero on parsing's start");
1047 State = IES_LBRAC;
1048 break;
1049 }
1050 NegativeAdditiveTerm = false;
1051 NegativeAdditiveTermLoc = SMLoc();
1052 // Entering a new memory expression; clear the pending scale.
1053 TmpScale.reset();
1054 MemExpr = true;
1055 BracketUsed = true;
1056 BracCount++;
1057 return false;
1058 }
1059 bool onRBrac(StringRef &ErrMsg) {
1060 IntelExprState CurrState = State;
1061 switch (State) {
1062 default:
1063 State = IES_ERROR;
1064 break;
1065 case IES_INTEGER:
1066 case IES_OFFSET:
1067 case IES_REGISTER:
1068 case IES_RPAREN:
1069 if (BracCount-- != 1) {
1070 ErrMsg = "unexpected bracket encountered";
1071 return true;
1072 }
1073 State = IES_RBRAC;
1074
1075 if (TmpReg) {
1076 // A pending scale forces this to be the IndexReg; otherwise a free
1077 // BaseReg takes it as an unscaled base.
1078 if (!BaseReg && !TmpScale.has_value()) {
1079 BaseReg = TmpReg;
1080 TmpReg = MCRegister::NoRegister;
1081 } else if (!IndexReg) {
1082 if (NegativeAdditiveTerm) {
1083 ErrMsg = "Scale can't be negative";
1084 return true;
1085 }
1086 IndexReg = TmpReg;
1087 TmpReg = MCRegister::NoRegister;
1088 if (TmpScale.has_value() && checkScale(Scale: TmpScale.value(), ErrMsg)) {
1089 return true;
1090 }
1091 Scale = TmpScale.value_or(u: 0);
1092 } else {
1093 return regsUseUpError(ErrMsg);
1094 }
1095 }
1096 NegativeAdditiveTerm = false;
1097 NegativeAdditiveTermLoc = SMLoc();
1098 break;
1099 }
1100 // Leaving the memory expression; clear the pending scale.
1101 TmpScale.reset();
1102 PrevState = CurrState;
1103 return false;
1104 }
1105 void onLParen(SMLoc Loc) {
1106 IntelExprState CurrState = State;
1107 switch (State) {
1108 default:
1109 State = IES_ERROR;
1110 break;
1111 case IES_PLUS:
1112 case IES_MINUS:
1113 case IES_NOT:
1114 case IES_OR:
1115 case IES_XOR:
1116 case IES_AND:
1117 case IES_EQ:
1118 case IES_NE:
1119 case IES_LT:
1120 case IES_LE:
1121 case IES_GT:
1122 case IES_GE:
1123 case IES_LSHIFT:
1124 case IES_RSHIFT:
1125 case IES_MULTIPLY:
1126 case IES_DIVIDE:
1127 case IES_MOD:
1128 case IES_LPAREN:
1129 case IES_INIT:
1130 case IES_LBRAC:
1131 ParenCount++;
1132 LParenLoc = Loc;
1133 State = IES_LPAREN;
1134 IC.pushOperator(Op: IC_LPAREN);
1135 break;
1136 }
1137 PrevState = CurrState;
1138 }
1139 bool onRParen(StringRef &ErrMsg) {
1140 IntelExprState CurrState = State;
1141 switch (State) {
1142 default:
1143 State = IES_ERROR;
1144 break;
1145 case IES_INTEGER:
1146 case IES_OFFSET:
1147 case IES_REGISTER:
1148 case IES_RBRAC:
1149 case IES_RPAREN:
1150 if (ParenCount == 0) {
1151 ErrMsg = "unmatched parenthesis";
1152 return true;
1153 }
1154 ParenCount--;
1155 State = IES_RPAREN;
1156 IC.pushOperator(Op: IC_RPAREN);
1157 break;
1158 }
1159 PrevState = CurrState;
1160 return false;
1161 }
1162 bool onOffset(const MCExpr *Val, StringRef ID,
1163 const InlineAsmIdentifierInfo &IDInfo,
1164 bool ParsingMSInlineAsm, StringRef &ErrMsg) {
1165 PrevState = State;
1166 switch (State) {
1167 default:
1168 ErrMsg = "unexpected offset operator expression";
1169 return true;
1170 case IES_PLUS:
1171 case IES_INIT:
1172 case IES_LBRAC:
1173 if (setSymRef(Val, ID, ErrMsg))
1174 return true;
1175 OffsetOperator = true;
1176 State = IES_OFFSET;
1177 // As we cannot yet resolve the actual value (offset), we retain
1178 // the requested semantics by pushing a '0' to the operands stack
1179 IC.pushOperand(Op: IC_IMM);
1180 if (ParsingMSInlineAsm) {
1181 Info = IDInfo;
1182 }
1183 break;
1184 }
1185 return false;
1186 }
1187 // Unlike onOffset, we do not set OffsetOperator here. The IMAGEREL
1188 // specifier is already encoded in the MCExpr with VK_COFF_IMGREL32,
1189 // so no additional rewriting is needed for inline asm.
1190 bool onImagerel(const MCExpr *Val, StringRef ID, StringRef &ErrMsg) {
1191 PrevState = State;
1192 switch (State) {
1193 case IES_PLUS:
1194 case IES_INIT:
1195 case IES_LBRAC:
1196 if (setSymRef(Val, ID, ErrMsg))
1197 return true;
1198 State = IES_OFFSET;
1199 IC.pushOperand(Op: IC_IMM);
1200 return false;
1201 default:
1202 ErrMsg = "unexpected imagerel operator expression";
1203 return true;
1204 }
1205 }
1206 void onCast(AsmTypeInfo Info) {
1207 PrevState = State;
1208 switch (State) {
1209 default:
1210 State = IES_ERROR;
1211 break;
1212 case IES_LPAREN:
1213 setTypeInfo(Info);
1214 State = IES_CAST;
1215 break;
1216 }
1217 }
1218 void setTypeInfo(AsmTypeInfo Type) { CurType = Type; }
1219 };
1220
1221 bool Error(SMLoc L, const Twine &Msg, SMRange Range = {},
1222 bool MatchingInlineAsm = false) {
1223 MCAsmParser &Parser = getParser();
1224 if (MatchingInlineAsm) {
1225 return false;
1226 }
1227 return Parser.Error(L, Msg, Range);
1228 }
1229
1230 bool MatchRegisterByName(MCRegister &RegNo, StringRef RegName, SMLoc StartLoc,
1231 SMLoc EndLoc);
1232 bool ParseRegister(MCRegister &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
1233 bool RestoreOnFailure);
1234
1235 std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc);
1236 std::unique_ptr<X86Operand> DefaultMemDIOperand(SMLoc Loc);
1237 bool IsSIReg(MCRegister Reg);
1238 MCRegister GetSIDIForRegClass(unsigned RegClassID, bool IsSIReg);
1239 void
1240 AddDefaultSrcDestOperands(OperandVector &Operands,
1241 std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
1242 std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst);
1243 bool VerifyAndAdjustOperands(OperandVector &OrigOperands,
1244 OperandVector &FinalOperands);
1245 bool parseOperand(OperandVector &Operands, StringRef Name);
1246 bool parseATTOperand(OperandVector &Operands);
1247 bool parseIntelOperand(OperandVector &Operands, StringRef Name);
1248 bool ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID,
1249 InlineAsmIdentifierInfo &Info, SMLoc &End);
1250 bool ParseIntelImagerelOperator(const MCExpr *&Val, StringRef &ID,
1251 InlineAsmIdentifierInfo &Info, SMLoc &End);
1252 bool ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End);
1253 unsigned IdentifyIntelInlineAsmOperator(StringRef Name);
1254 unsigned ParseIntelInlineAsmOperator(unsigned OpKind);
1255 unsigned IdentifyMasmOperator(StringRef Name);
1256 bool ParseMasmOperator(unsigned OpKind, int64_t &Val);
1257 bool ParseRoundingModeOp(SMLoc Start, OperandVector &Operands);
1258 bool parseCFlagsOp(OperandVector &Operands);
1259 bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM,
1260 bool &ParseError, SMLoc &End);
1261 bool ParseMasmNamedOperator(StringRef Name, IntelExprStateMachine &SM,
1262 bool &ParseError, SMLoc &End);
1263 void RewriteIntelExpression(IntelExprStateMachine &SM, SMLoc Start,
1264 SMLoc End);
1265 bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
1266 bool ParseIntelInlineAsmIdentifier(const MCExpr *&Val, StringRef &Identifier,
1267 InlineAsmIdentifierInfo &Info,
1268 bool IsUnevaluatedOperand, SMLoc &End,
1269 bool IsParsingOffsetOperator = false);
1270 void tryParseOperandIdx(AsmToken::TokenKind PrevTK,
1271 IntelExprStateMachine &SM);
1272
1273 bool CheckDispOverflow(MCRegister BaseReg, MCRegister IndexReg,
1274 const MCExpr *Disp, SMLoc Loc);
1275
1276 bool ParseMemOperand(MCRegister SegReg, const MCExpr *Disp, SMLoc StartLoc,
1277 SMLoc EndLoc, OperandVector &Operands);
1278
1279 X86::CondCode ParseConditionCode(StringRef CCode);
1280
1281 bool ParseIntelMemoryOperandSize(unsigned &Size, StringRef *SizeStr);
1282 bool CreateMemForMSInlineAsm(MCRegister SegReg, const MCExpr *Disp,
1283 MCRegister BaseReg, MCRegister IndexReg,
1284 unsigned Scale, bool NonAbsMem, SMLoc Start,
1285 SMLoc End, unsigned Size, StringRef Identifier,
1286 const InlineAsmIdentifierInfo &Info,
1287 OperandVector &Operands);
1288
1289 bool parseDirectiveArch();
1290 bool parseDirectiveNops(SMLoc L);
1291 bool parseDirectiveEven(SMLoc L);
1292 bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
1293
1294 /// CodeView FPO data directives.
1295 bool parseDirectiveFPOProc(SMLoc L);
1296 bool parseDirectiveFPOSetFrame(SMLoc L);
1297 bool parseDirectiveFPOPushReg(SMLoc L);
1298 bool parseDirectiveFPOStackAlloc(SMLoc L);
1299 bool parseDirectiveFPOStackAlign(SMLoc L);
1300 bool parseDirectiveFPOEndPrologue(SMLoc L);
1301 bool parseDirectiveFPOEndProc(SMLoc L);
1302
1303 /// SEH directives.
1304 bool parseSEHRegisterNumber(unsigned RegClassID, MCRegister &RegNo);
1305 bool parseDirectiveSEHPushReg(SMLoc);
1306 bool parseDirectiveSEHPush2Regs(SMLoc, bool SwapRegs = false);
1307 bool parseDirectiveSEHSetFrame(SMLoc);
1308 bool parseDirectiveSEHSaveReg(SMLoc);
1309 bool parseDirectiveSEHSaveXMM(SMLoc);
1310 bool parseDirectiveSEHPushFrame(SMLoc);
1311
1312 bool ensureMasmEpilogContext(SMLoc Loc);
1313 bool ensureMasmPrologContext(SMLoc Loc);
1314
1315 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
1316
1317 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
1318 bool processInstruction(MCInst &Inst, const OperandVector &Ops);
1319
1320 // Load Value Injection (LVI) Mitigations for machine code
1321 void emitWarningForSpecialLVIInstruction(SMLoc Loc);
1322 void applyLVICFIMitigation(MCInst &Inst, MCStreamer &Out);
1323 void applyLVILoadHardeningMitigation(MCInst &Inst, MCStreamer &Out);
1324
1325 /// Wrapper around MCStreamer::emitInstruction(). Possibly adds
1326 /// instrumentation around Inst.
1327 void emitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
1328
1329 bool matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1330 OperandVector &Operands, MCStreamer &Out,
1331 uint64_t &ErrorInfo,
1332 bool MatchingInlineAsm) override;
1333
1334 void MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands,
1335 MCStreamer &Out, bool MatchingInlineAsm);
1336
1337 bool ErrorMissingFeature(SMLoc IDLoc, const FeatureBitset &MissingFeatures,
1338 bool MatchingInlineAsm);
1339
1340 bool matchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, MCInst &Inst,
1341 OperandVector &Operands, MCStreamer &Out,
1342 uint64_t &ErrorInfo, bool MatchingInlineAsm);
1343
1344 bool matchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode, MCInst &Inst,
1345 OperandVector &Operands, MCStreamer &Out,
1346 uint64_t &ErrorInfo,
1347 bool MatchingInlineAsm);
1348
1349 bool omitRegisterFromClobberLists(MCRegister Reg) override;
1350
1351 /// Parses AVX512 specific operand primitives: masked registers ({%k<NUM>}, {z})
1352 /// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
1353 /// return false if no parsing errors occurred, true otherwise.
1354 bool HandleAVX512Operand(OperandVector &Operands);
1355
1356 bool ParseZ(std::unique_ptr<X86Operand> &Z, SMLoc StartLoc);
1357
1358 bool is64BitMode() const {
1359 // FIXME: Can tablegen auto-generate this?
1360 return getSTI().hasFeature(Feature: X86::Is64Bit);
1361 }
1362 bool is32BitMode() const {
1363 // FIXME: Can tablegen auto-generate this?
1364 return getSTI().hasFeature(Feature: X86::Is32Bit);
1365 }
1366 bool is16BitMode() const {
1367 // FIXME: Can tablegen auto-generate this?
1368 return getSTI().hasFeature(Feature: X86::Is16Bit);
1369 }
1370 void SwitchMode(unsigned mode) {
1371 MCSubtargetInfo &STI = copySTI();
1372 FeatureBitset AllModes({X86::Is64Bit, X86::Is32Bit, X86::Is16Bit});
1373 FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
1374 FeatureBitset FB = ComputeAvailableFeatures(
1375 FB: STI.ToggleFeature(FB: OldMode.flip(I: mode)));
1376 setAvailableFeatures(FB);
1377
1378 assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes));
1379 }
1380
1381 unsigned getPointerWidth() {
1382 if (is16BitMode()) return 16;
1383 if (is32BitMode()) return 32;
1384 if (is64BitMode()) return 64;
1385 llvm_unreachable("invalid mode");
1386 }
1387
1388 bool isParsingIntelSyntax() {
1389 return getParser().getAssemblerDialect();
1390 }
1391
1392 /// @name Auto-generated Matcher Functions
1393 /// {
1394
1395#define GET_ASSEMBLER_HEADER
1396#include "X86GenAsmMatcher.inc"
1397
1398 /// }
1399
1400public:
1401 enum X86MatchResultTy {
1402 Match_Unsupported = FIRST_TARGET_MATCH_RESULT_TY,
1403#define GET_OPERAND_DIAGNOSTIC_TYPES
1404#include "X86GenAsmMatcher.inc"
1405 };
1406
1407 X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
1408 const MCInstrInfo &mii)
1409 : MCTargetAsmParser(sti, mii), InstInfo(nullptr), Code16GCC(false) {
1410
1411 Parser.addAliasForDirective(Directive: ".word", Alias: ".2byte");
1412
1413 // Initialize the set of available features.
1414 setAvailableFeatures(ComputeAvailableFeatures(FB: getSTI().getFeatureBits()));
1415 }
1416
1417 bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
1418 ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
1419 SMLoc &EndLoc) override;
1420
1421 bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) override;
1422
1423 bool parseInstruction(ParseInstructionInfo &Info, StringRef Name,
1424 SMLoc NameLoc, OperandVector &Operands) override;
1425
1426 bool ParseDirective(AsmToken DirectiveID) override;
1427};
1428} // end anonymous namespace
1429
1430#define GET_REGISTER_MATCHER
1431#define GET_SUBTARGET_FEATURE_NAME
1432#include "X86GenAsmMatcher.inc"
1433
1434static bool CheckBaseRegAndIndexRegAndScale(MCRegister BaseReg,
1435 MCRegister IndexReg, unsigned Scale,
1436 bool Is64BitMode,
1437 StringRef &ErrMsg) {
1438 // If we have both a base register and an index register make sure they are
1439 // both 64-bit or 32-bit registers.
1440 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
1441
1442 if (BaseReg &&
1443 !(BaseReg == X86::RIP || BaseReg == X86::EIP ||
1444 getX86MCRegisterClass(RC: X86::GR16RegClassID).contains(Reg: BaseReg) ||
1445 getX86MCRegisterClass(RC: X86::GR32RegClassID).contains(Reg: BaseReg) ||
1446 getX86MCRegisterClass(RC: X86::GR64RegClassID).contains(Reg: BaseReg))) {
1447 ErrMsg = "invalid base+index expression";
1448 return true;
1449 }
1450
1451 if (IndexReg &&
1452 !(IndexReg == X86::EIZ || IndexReg == X86::RIZ ||
1453 getX86MCRegisterClass(RC: X86::GR16RegClassID).contains(Reg: IndexReg) ||
1454 getX86MCRegisterClass(RC: X86::GR32RegClassID).contains(Reg: IndexReg) ||
1455 getX86MCRegisterClass(RC: X86::GR64RegClassID).contains(Reg: IndexReg) ||
1456 getX86MCRegisterClass(RC: X86::VR128XRegClassID).contains(Reg: IndexReg) ||
1457 getX86MCRegisterClass(RC: X86::VR256XRegClassID).contains(Reg: IndexReg) ||
1458 getX86MCRegisterClass(RC: X86::VR512RegClassID).contains(Reg: IndexReg))) {
1459 ErrMsg = "invalid base+index expression";
1460 return true;
1461 }
1462
1463 if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg) ||
1464 IndexReg == X86::EIP || IndexReg == X86::RIP || IndexReg == X86::ESP ||
1465 IndexReg == X86::RSP) {
1466 ErrMsg = "invalid base+index expression";
1467 return true;
1468 }
1469
1470 // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed,
1471 // and then only in non-64-bit modes.
1472 if (getX86MCRegisterClass(RC: X86::GR16RegClassID).contains(Reg: BaseReg) &&
1473 (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP &&
1474 BaseReg != X86::SI && BaseReg != X86::DI))) {
1475 ErrMsg = "invalid 16-bit base register";
1476 return true;
1477 }
1478
1479 if (!BaseReg &&
1480 getX86MCRegisterClass(RC: X86::GR16RegClassID).contains(Reg: IndexReg)) {
1481 ErrMsg = "16-bit memory operand may not include only index register";
1482 return true;
1483 }
1484
1485 if (BaseReg && IndexReg) {
1486 if (getX86MCRegisterClass(RC: X86::GR64RegClassID).contains(Reg: BaseReg) &&
1487 (getX86MCRegisterClass(RC: X86::GR16RegClassID).contains(Reg: IndexReg) ||
1488 getX86MCRegisterClass(RC: X86::GR32RegClassID).contains(Reg: IndexReg) ||
1489 IndexReg == X86::EIZ)) {
1490 ErrMsg = "base register is 64-bit, but index register is not";
1491 return true;
1492 }
1493 if (getX86MCRegisterClass(RC: X86::GR32RegClassID).contains(Reg: BaseReg) &&
1494 (getX86MCRegisterClass(RC: X86::GR16RegClassID).contains(Reg: IndexReg) ||
1495 getX86MCRegisterClass(RC: X86::GR64RegClassID).contains(Reg: IndexReg) ||
1496 IndexReg == X86::RIZ)) {
1497 ErrMsg = "base register is 32-bit, but index register is not";
1498 return true;
1499 }
1500 if (getX86MCRegisterClass(RC: X86::GR16RegClassID).contains(Reg: BaseReg)) {
1501 if (getX86MCRegisterClass(RC: X86::GR32RegClassID).contains(Reg: IndexReg) ||
1502 getX86MCRegisterClass(RC: X86::GR64RegClassID).contains(Reg: IndexReg)) {
1503 ErrMsg = "base register is 16-bit, but index register is not";
1504 return true;
1505 }
1506 if ((BaseReg != X86::BX && BaseReg != X86::BP) ||
1507 (IndexReg != X86::SI && IndexReg != X86::DI)) {
1508 ErrMsg = "invalid 16-bit base/index register combination";
1509 return true;
1510 }
1511 }
1512 }
1513
1514 // RIP/EIP-relative addressing is only supported in 64-bit mode.
1515 if (!Is64BitMode && (BaseReg == X86::RIP || BaseReg == X86::EIP)) {
1516 ErrMsg = "IP-relative addressing requires 64-bit mode";
1517 return true;
1518 }
1519
1520 return checkScale(Scale, ErrMsg);
1521}
1522
1523bool X86AsmParser::MatchRegisterByName(MCRegister &RegNo, StringRef RegName,
1524 SMLoc StartLoc, SMLoc EndLoc) {
1525 // If we encounter a %, ignore it. This code handles registers with and
1526 // without the prefix, unprefixed registers can occur in cfi directives.
1527 RegName.consume_front(Prefix: "%");
1528
1529 RegNo = MatchRegisterName(Name: RegName);
1530
1531 // If the match failed, try the register name as lowercase.
1532 if (!RegNo)
1533 RegNo = MatchRegisterName(Name: RegName.lower());
1534
1535 // The "flags" and "mxcsr" registers cannot be referenced directly.
1536 // Treat it as an identifier instead.
1537 if (isParsingMSInlineAsm() && isParsingIntelSyntax() &&
1538 (RegNo == X86::EFLAGS || RegNo == X86::MXCSR))
1539 RegNo = MCRegister();
1540
1541 if (!is64BitMode()) {
1542 // FIXME: This should be done using Requires<Not64BitMode> and
1543 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
1544 // checked.
1545 if (RegNo == X86::RIZ || RegNo == X86::RIP ||
1546 getX86MCRegisterClass(RC: X86::GR64RegClassID).contains(Reg: RegNo) ||
1547 X86II::isX86_64NonExtLowByteReg(Reg: RegNo) ||
1548 X86II::isX86_64ExtendedReg(Reg: RegNo)) {
1549 return Error(L: StartLoc,
1550 Msg: "register %" + RegName + " is only available in 64-bit mode",
1551 Range: SMRange(StartLoc, EndLoc));
1552 }
1553 }
1554
1555 if (X86II::isApxExtendedReg(Reg: RegNo))
1556 UseApxExtendedReg = true;
1557
1558 // If this is "db[0-15]", match it as an alias
1559 // for dr[0-15].
1560 if (!RegNo && RegName.starts_with(Prefix: "db")) {
1561 if (RegName.size() == 3) {
1562 switch (RegName[2]) {
1563 case '0':
1564 RegNo = X86::DR0;
1565 break;
1566 case '1':
1567 RegNo = X86::DR1;
1568 break;
1569 case '2':
1570 RegNo = X86::DR2;
1571 break;
1572 case '3':
1573 RegNo = X86::DR3;
1574 break;
1575 case '4':
1576 RegNo = X86::DR4;
1577 break;
1578 case '5':
1579 RegNo = X86::DR5;
1580 break;
1581 case '6':
1582 RegNo = X86::DR6;
1583 break;
1584 case '7':
1585 RegNo = X86::DR7;
1586 break;
1587 case '8':
1588 RegNo = X86::DR8;
1589 break;
1590 case '9':
1591 RegNo = X86::DR9;
1592 break;
1593 }
1594 } else if (RegName.size() == 4 && RegName[2] == '1') {
1595 switch (RegName[3]) {
1596 case '0':
1597 RegNo = X86::DR10;
1598 break;
1599 case '1':
1600 RegNo = X86::DR11;
1601 break;
1602 case '2':
1603 RegNo = X86::DR12;
1604 break;
1605 case '3':
1606 RegNo = X86::DR13;
1607 break;
1608 case '4':
1609 RegNo = X86::DR14;
1610 break;
1611 case '5':
1612 RegNo = X86::DR15;
1613 break;
1614 }
1615 }
1616 }
1617
1618 if (!RegNo) {
1619 if (isParsingIntelSyntax())
1620 return true;
1621 return Error(L: StartLoc, Msg: "invalid register name", Range: SMRange(StartLoc, EndLoc));
1622 }
1623 return false;
1624}
1625
1626bool X86AsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
1627 SMLoc &EndLoc, bool RestoreOnFailure) {
1628 MCAsmParser &Parser = getParser();
1629 AsmLexer &Lexer = getLexer();
1630 RegNo = MCRegister();
1631
1632 SmallVector<AsmToken, 5> Tokens;
1633 auto OnFailure = [RestoreOnFailure, &Lexer, &Tokens]() {
1634 if (RestoreOnFailure) {
1635 while (!Tokens.empty()) {
1636 Lexer.UnLex(Token: Tokens.pop_back_val());
1637 }
1638 }
1639 };
1640
1641 const AsmToken &PercentTok = Parser.getTok();
1642 StartLoc = PercentTok.getLoc();
1643
1644 // If we encounter a %, ignore it. This code handles registers with and
1645 // without the prefix, unprefixed registers can occur in cfi directives.
1646 if (!isParsingIntelSyntax() && PercentTok.is(K: AsmToken::Percent)) {
1647 Tokens.push_back(Elt: PercentTok);
1648 Parser.Lex(); // Eat percent token.
1649 }
1650
1651 const AsmToken &Tok = Parser.getTok();
1652 EndLoc = Tok.getEndLoc();
1653
1654 if (Tok.isNot(K: AsmToken::Identifier)) {
1655 OnFailure();
1656 if (isParsingIntelSyntax()) return true;
1657 return Error(L: StartLoc, Msg: "invalid register name",
1658 Range: SMRange(StartLoc, EndLoc));
1659 }
1660
1661 if (MatchRegisterByName(RegNo, RegName: Tok.getString(), StartLoc, EndLoc)) {
1662 OnFailure();
1663 return true;
1664 }
1665
1666 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
1667 if (RegNo == X86::ST0) {
1668 Tokens.push_back(Elt: Tok);
1669 Parser.Lex(); // Eat 'st'
1670
1671 // Check to see if we have '(4)' after %st.
1672 if (Lexer.isNot(K: AsmToken::LParen))
1673 return false;
1674 // Lex the paren.
1675 Tokens.push_back(Elt: Parser.getTok());
1676 Parser.Lex();
1677
1678 const AsmToken &IntTok = Parser.getTok();
1679 if (IntTok.isNot(K: AsmToken::Integer)) {
1680 OnFailure();
1681 return Error(L: IntTok.getLoc(), Msg: "expected stack index");
1682 }
1683 switch (IntTok.getIntVal()) {
1684 case 0: RegNo = X86::ST0; break;
1685 case 1: RegNo = X86::ST1; break;
1686 case 2: RegNo = X86::ST2; break;
1687 case 3: RegNo = X86::ST3; break;
1688 case 4: RegNo = X86::ST4; break;
1689 case 5: RegNo = X86::ST5; break;
1690 case 6: RegNo = X86::ST6; break;
1691 case 7: RegNo = X86::ST7; break;
1692 default:
1693 OnFailure();
1694 return Error(L: IntTok.getLoc(), Msg: "invalid stack index");
1695 }
1696
1697 // Lex IntTok
1698 Tokens.push_back(Elt: IntTok);
1699 Parser.Lex();
1700 if (Lexer.isNot(K: AsmToken::RParen)) {
1701 OnFailure();
1702 return Error(L: Parser.getTok().getLoc(), Msg: "expected ')'");
1703 }
1704
1705 EndLoc = Parser.getTok().getEndLoc();
1706 Parser.Lex(); // Eat ')'
1707 return false;
1708 }
1709
1710 EndLoc = Parser.getTok().getEndLoc();
1711
1712 if (!RegNo) {
1713 OnFailure();
1714 if (isParsingIntelSyntax()) return true;
1715 return Error(L: StartLoc, Msg: "invalid register name",
1716 Range: SMRange(StartLoc, EndLoc));
1717 }
1718
1719 Parser.Lex(); // Eat identifier token.
1720 return false;
1721}
1722
1723bool X86AsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
1724 SMLoc &EndLoc) {
1725 return ParseRegister(RegNo&: Reg, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
1726}
1727
1728ParseStatus X86AsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
1729 SMLoc &EndLoc) {
1730 bool Result = ParseRegister(RegNo&: Reg, StartLoc, EndLoc, /*RestoreOnFailure=*/true);
1731 bool PendingErrors = getParser().hasPendingError();
1732 getParser().clearPendingErrors();
1733 if (PendingErrors)
1734 return ParseStatus::Failure;
1735 if (Result)
1736 return ParseStatus::NoMatch;
1737 return ParseStatus::Success;
1738}
1739
1740std::unique_ptr<X86Operand> X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
1741 bool Parse32 = is32BitMode() || Code16GCC;
1742 MCRegister Basereg =
1743 is64BitMode() ? X86::RSI : (Parse32 ? X86::ESI : X86::SI);
1744 const MCExpr *Disp = MCConstantExpr::create(Value: 0, Ctx&: getContext());
1745 return X86Operand::CreateMem(ModeSize: getPointerWidth(), /*SegReg=*/0, Disp,
1746 /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1747 StartLoc: Loc, EndLoc: Loc, Size: 0);
1748}
1749
1750std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
1751 bool Parse32 = is32BitMode() || Code16GCC;
1752 MCRegister Basereg =
1753 is64BitMode() ? X86::RDI : (Parse32 ? X86::EDI : X86::DI);
1754 const MCExpr *Disp = MCConstantExpr::create(Value: 0, Ctx&: getContext());
1755 return X86Operand::CreateMem(ModeSize: getPointerWidth(), /*SegReg=*/0, Disp,
1756 /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1757 StartLoc: Loc, EndLoc: Loc, Size: 0);
1758}
1759
1760bool X86AsmParser::IsSIReg(MCRegister Reg) {
1761 switch (Reg.id()) {
1762 default: llvm_unreachable("Only (R|E)SI and (R|E)DI are expected!");
1763 case X86::RSI:
1764 case X86::ESI:
1765 case X86::SI:
1766 return true;
1767 case X86::RDI:
1768 case X86::EDI:
1769 case X86::DI:
1770 return false;
1771 }
1772}
1773
1774MCRegister X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, bool IsSIReg) {
1775 switch (RegClassID) {
1776 default: llvm_unreachable("Unexpected register class");
1777 case X86::GR64RegClassID:
1778 return IsSIReg ? X86::RSI : X86::RDI;
1779 case X86::GR32RegClassID:
1780 return IsSIReg ? X86::ESI : X86::EDI;
1781 case X86::GR16RegClassID:
1782 return IsSIReg ? X86::SI : X86::DI;
1783 }
1784}
1785
1786void X86AsmParser::AddDefaultSrcDestOperands(
1787 OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
1788 std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst) {
1789 if (isParsingIntelSyntax()) {
1790 Operands.push_back(Elt: std::move(Dst));
1791 Operands.push_back(Elt: std::move(Src));
1792 }
1793 else {
1794 Operands.push_back(Elt: std::move(Src));
1795 Operands.push_back(Elt: std::move(Dst));
1796 }
1797}
1798
1799bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands,
1800 OperandVector &FinalOperands) {
1801
1802 if (OrigOperands.size() > 1) {
1803 // Check if sizes match, OrigOperands also contains the instruction name
1804 assert(OrigOperands.size() == FinalOperands.size() + 1 &&
1805 "Operand size mismatch");
1806
1807 SmallVector<std::pair<SMLoc, std::string>, 2> Warnings;
1808 // Verify types match
1809 int RegClassID = -1;
1810 for (unsigned int i = 0; i < FinalOperands.size(); ++i) {
1811 X86Operand &OrigOp = static_cast<X86Operand &>(*OrigOperands[i + 1]);
1812 X86Operand &FinalOp = static_cast<X86Operand &>(*FinalOperands[i]);
1813
1814 if (FinalOp.isReg() &&
1815 (!OrigOp.isReg() || FinalOp.getReg() != OrigOp.getReg()))
1816 // Return false and let a normal complaint about bogus operands happen
1817 return false;
1818
1819 if (FinalOp.isMem()) {
1820
1821 if (!OrigOp.isMem())
1822 // Return false and let a normal complaint about bogus operands happen
1823 return false;
1824
1825 MCRegister OrigReg = OrigOp.Mem.BaseReg;
1826 MCRegister FinalReg = FinalOp.Mem.BaseReg;
1827
1828 // If we've already encounterd a register class, make sure all register
1829 // bases are of the same register class
1830 if (RegClassID != -1 &&
1831 !getX86MCRegisterClass(RC: RegClassID).contains(Reg: OrigReg)) {
1832 return Error(L: OrigOp.getStartLoc(),
1833 Msg: "mismatching source and destination index registers");
1834 }
1835
1836 if (getX86MCRegisterClass(RC: X86::GR64RegClassID).contains(Reg: OrigReg))
1837 RegClassID = X86::GR64RegClassID;
1838 else if (getX86MCRegisterClass(RC: X86::GR32RegClassID).contains(Reg: OrigReg))
1839 RegClassID = X86::GR32RegClassID;
1840 else if (getX86MCRegisterClass(RC: X86::GR16RegClassID).contains(Reg: OrigReg))
1841 RegClassID = X86::GR16RegClassID;
1842 else
1843 // Unexpected register class type
1844 // Return false and let a normal complaint about bogus operands happen
1845 return false;
1846
1847 bool IsSI = IsSIReg(Reg: FinalReg);
1848 FinalReg = GetSIDIForRegClass(RegClassID, IsSIReg: IsSI);
1849
1850 if (FinalReg != OrigReg) {
1851 std::string RegName = IsSI ? "ES:(R|E)SI" : "ES:(R|E)DI";
1852 Warnings.push_back(Elt: std::make_pair(
1853 x: OrigOp.getStartLoc(),
1854 y: "memory operand is only for determining the size, " + RegName +
1855 " will be used for the location"));
1856 }
1857
1858 FinalOp.Mem.Size = OrigOp.Mem.Size;
1859 FinalOp.Mem.SegReg = OrigOp.Mem.SegReg;
1860 FinalOp.Mem.BaseReg = FinalReg;
1861 }
1862 }
1863
1864 // Produce warnings only if all the operands passed the adjustment - prevent
1865 // legal cases like "movsd (%rax), %xmm0" mistakenly produce warnings
1866 for (auto &WarningMsg : Warnings) {
1867 Warning(L: WarningMsg.first, Msg: WarningMsg.second);
1868 }
1869
1870 // Remove old operands
1871 for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1872 OrigOperands.pop_back();
1873 }
1874 // OrigOperands.append(FinalOperands.begin(), FinalOperands.end());
1875 for (auto &Op : FinalOperands)
1876 OrigOperands.push_back(Elt: std::move(Op));
1877
1878 return false;
1879}
1880
1881bool X86AsmParser::parseOperand(OperandVector &Operands, StringRef Name) {
1882 if (isParsingIntelSyntax())
1883 return parseIntelOperand(Operands, Name);
1884
1885 return parseATTOperand(Operands);
1886}
1887
1888bool X86AsmParser::CreateMemForMSInlineAsm(
1889 MCRegister SegReg, const MCExpr *Disp, MCRegister BaseReg,
1890 MCRegister IndexReg, unsigned Scale, bool NonAbsMem, SMLoc Start, SMLoc End,
1891 unsigned Size, StringRef Identifier, const InlineAsmIdentifierInfo &Info,
1892 OperandVector &Operands) {
1893 // If we found a decl other than a VarDecl, then assume it is a FuncDecl or
1894 // some other label reference.
1895 if (Info.isKind(kind: InlineAsmIdentifierInfo::IK_Label)) {
1896 // Create an absolute memory reference in order to match against
1897 // instructions taking a PC relative operand.
1898 Operands.push_back(Elt: X86Operand::CreateMem(ModeSize: getPointerWidth(), Disp, StartLoc: Start,
1899 EndLoc: End, Size, SymName: Identifier,
1900 OpDecl: Info.Label.Decl));
1901 return false;
1902 }
1903 // We either have a direct symbol reference, or an offset from a symbol. The
1904 // parser always puts the symbol on the LHS, so look there for size
1905 // calculation purposes.
1906 unsigned FrontendSize = 0;
1907 void *Decl = nullptr;
1908 bool IsGlobalLV = false;
1909 if (Info.isKind(kind: InlineAsmIdentifierInfo::IK_Var)) {
1910 // Size is in terms of bits in this context.
1911 FrontendSize = Info.Var.Type * 8;
1912 Decl = Info.Var.Decl;
1913 IsGlobalLV = Info.Var.IsGlobalLV;
1914 }
1915 // It is widely common for MS InlineAsm to use a global variable and one/two
1916 // registers in a mmory expression, and though unaccessible via rip/eip.
1917 if (IsGlobalLV) {
1918 if (BaseReg || IndexReg) {
1919 Operands.push_back(Elt: X86Operand::CreateMem(ModeSize: getPointerWidth(), Disp, StartLoc: Start,
1920 EndLoc: End, Size, SymName: Identifier, OpDecl: Decl, FrontendSize: 0,
1921 UseUpRegs: BaseReg && IndexReg));
1922 return false;
1923 }
1924 if (NonAbsMem)
1925 BaseReg = 1; // Make isAbsMem() false
1926 }
1927 Operands.push_back(Elt: X86Operand::CreateMem(
1928 ModeSize: getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, StartLoc: Start, EndLoc: End,
1929 Size,
1930 /*DefaultBaseReg=*/X86::RIP, SymName: Identifier, OpDecl: Decl, FrontendSize));
1931 return false;
1932}
1933
1934// Some binary bitwise operators have a named synonymous
1935// Query a candidate string for being such a named operator
1936// and if so - invoke the appropriate handler
1937bool X86AsmParser::ParseIntelNamedOperator(StringRef Name,
1938 IntelExprStateMachine &SM,
1939 bool &ParseError, SMLoc &End) {
1940 // A named operator should be either lower or upper case, but not a mix...
1941 // except in MASM, which uses full case-insensitivity.
1942 if (Name != Name.lower() && Name != Name.upper() &&
1943 !getParser().isParsingMasm())
1944 return false;
1945 // Operators like 'offset' and 'imagerel' consume their operand tokens
1946 // internally; other named operators need a trailing consumeToken().
1947 bool AlreadyConsumed = false;
1948 if (Name.equals_insensitive(RHS: "not")) {
1949 SM.onNot();
1950 } else if (Name.equals_insensitive(RHS: "or")) {
1951 SM.onOr();
1952 } else if (Name.equals_insensitive(RHS: "shl")) {
1953 SM.onLShift();
1954 } else if (Name.equals_insensitive(RHS: "shr")) {
1955 SM.onRShift();
1956 } else if (Name.equals_insensitive(RHS: "xor")) {
1957 SM.onXor();
1958 } else if (Name.equals_insensitive(RHS: "and")) {
1959 SM.onAnd();
1960 } else if (Name.equals_insensitive(RHS: "mod")) {
1961 SM.onMod();
1962 } else if (Name.equals_insensitive(RHS: "offset")) {
1963 const MCExpr *Val = nullptr;
1964 StringRef ID;
1965 InlineAsmIdentifierInfo Info;
1966 ParseError = ParseIntelOffsetOperator(Val, ID, Info, End);
1967 if (ParseError)
1968 return true;
1969 StringRef ErrMsg;
1970 ParseError = SM.onOffset(Val, ID, IDInfo: Info, ParsingMSInlineAsm: isParsingMSInlineAsm(), ErrMsg);
1971 if (ParseError)
1972 return Error(L: SMLoc::getFromPointer(Ptr: Name.data()), Msg: ErrMsg);
1973 AlreadyConsumed = true;
1974 } else if (Name.equals_insensitive(RHS: "imagerel")) {
1975 const MCExpr *Val;
1976 StringRef ID;
1977 InlineAsmIdentifierInfo Info;
1978 ParseError = ParseIntelImagerelOperator(Val, ID, Info, End);
1979 if (ParseError)
1980 return true;
1981 StringRef ErrMsg;
1982 ParseError = SM.onImagerel(Val, ID, ErrMsg);
1983 if (ParseError)
1984 return Error(L: SMLoc::getFromPointer(Ptr: Name.data()), Msg: ErrMsg);
1985 AlreadyConsumed = true;
1986 } else {
1987 return false;
1988 }
1989 if (!AlreadyConsumed)
1990 End = consumeToken();
1991 return true;
1992}
1993bool X86AsmParser::ParseMasmNamedOperator(StringRef Name,
1994 IntelExprStateMachine &SM,
1995 bool &ParseError, SMLoc &End) {
1996 if (Name.equals_insensitive(RHS: "eq")) {
1997 SM.onEq();
1998 } else if (Name.equals_insensitive(RHS: "ne")) {
1999 SM.onNE();
2000 } else if (Name.equals_insensitive(RHS: "lt")) {
2001 SM.onLT();
2002 } else if (Name.equals_insensitive(RHS: "le")) {
2003 SM.onLE();
2004 } else if (Name.equals_insensitive(RHS: "gt")) {
2005 SM.onGT();
2006 } else if (Name.equals_insensitive(RHS: "ge")) {
2007 SM.onGE();
2008 } else {
2009 return false;
2010 }
2011 End = consumeToken();
2012 return true;
2013}
2014
2015// Check if current intel expression append after an operand.
2016// Like: [Operand][Intel Expression]
2017void X86AsmParser::tryParseOperandIdx(AsmToken::TokenKind PrevTK,
2018 IntelExprStateMachine &SM) {
2019 if (PrevTK != AsmToken::RBrac)
2020 return;
2021
2022 SM.setAppendAfterOperand();
2023}
2024
2025bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
2026 MCAsmParser &Parser = getParser();
2027 StringRef ErrMsg;
2028
2029 AsmToken::TokenKind PrevTK = AsmToken::Error;
2030
2031 if (getContext().getObjectFileInfo()->isPositionIndependent())
2032 SM.setPIC();
2033
2034 bool Done = false;
2035 while (!Done) {
2036 // Get a fresh reference on each loop iteration in case the previous
2037 // iteration moved the token storage during UnLex().
2038 const AsmToken &Tok = Parser.getTok();
2039
2040 bool UpdateLocLex = true;
2041 AsmToken::TokenKind TK = getLexer().getKind();
2042
2043 switch (TK) {
2044 default:
2045 if ((Done = SM.isValidEndState()))
2046 break;
2047 return Error(L: Tok.getLoc(), Msg: "unknown token in expression");
2048 case AsmToken::Error:
2049 return Error(L: getLexer().getErrLoc(), Msg: getLexer().getErr());
2050 break;
2051 case AsmToken::Real:
2052 // DotOperator: [ebx].0
2053 UpdateLocLex = false;
2054 if (ParseIntelDotOperator(SM, End))
2055 return true;
2056 break;
2057 case AsmToken::Dot:
2058 if (!Parser.isParsingMasm()) {
2059 if ((Done = SM.isValidEndState()))
2060 break;
2061 return Error(L: Tok.getLoc(), Msg: "unknown token in expression");
2062 }
2063 // MASM allows spaces around the dot operator (e.g., "var . x")
2064 Lex();
2065 UpdateLocLex = false;
2066 if (ParseIntelDotOperator(SM, End))
2067 return true;
2068 break;
2069 case AsmToken::Dollar:
2070 if (!Parser.isParsingMasm()) {
2071 if ((Done = SM.isValidEndState()))
2072 break;
2073 return Error(L: Tok.getLoc(), Msg: "unknown token in expression");
2074 }
2075 [[fallthrough]];
2076 case AsmToken::String: {
2077 if (Parser.isParsingMasm()) {
2078 // MASM parsers handle strings in expressions as constants.
2079 SMLoc ValueLoc = Tok.getLoc();
2080 int64_t Res;
2081 const MCExpr *Val;
2082 if (Parser.parsePrimaryExpr(Res&: Val, EndLoc&: End, TypeInfo: nullptr))
2083 return true;
2084 UpdateLocLex = false;
2085 if (!Val->evaluateAsAbsolute(Res, Asm: getStreamer().getAssemblerPtr()))
2086 return Error(L: ValueLoc, Msg: "expected absolute value");
2087 if (SM.onInteger(TmpInt: Res, ErrMsg))
2088 return Error(L: SM.getErrorLoc(DefaultLoc: ValueLoc), Msg: ErrMsg);
2089 break;
2090 }
2091 [[fallthrough]];
2092 }
2093 case AsmToken::At:
2094 case AsmToken::Identifier: {
2095 SMLoc IdentLoc = Tok.getLoc();
2096 StringRef Identifier = Tok.getString();
2097 UpdateLocLex = false;
2098 if (Parser.isParsingMasm()) {
2099 size_t DotOffset = Identifier.find_first_of(C: '.');
2100 if (DotOffset != StringRef::npos) {
2101 consumeToken();
2102 StringRef LHS = Identifier.slice(Start: 0, End: DotOffset);
2103 StringRef Dot = Identifier.substr(Start: DotOffset, N: 1);
2104 StringRef RHS = Identifier.substr(Start: DotOffset + 1);
2105 if (!RHS.empty()) {
2106 getLexer().UnLex(Token: AsmToken(AsmToken::Identifier, RHS));
2107 }
2108 getLexer().UnLex(Token: AsmToken(AsmToken::Dot, Dot));
2109 if (!LHS.empty()) {
2110 getLexer().UnLex(Token: AsmToken(AsmToken::Identifier, LHS));
2111 }
2112 break;
2113 }
2114 }
2115 // (MASM only) <TYPE> PTR operator
2116 if (Parser.isParsingMasm()) {
2117 const AsmToken &NextTok = getLexer().peekTok();
2118 if (NextTok.is(K: AsmToken::Identifier) &&
2119 NextTok.getIdentifier().equals_insensitive(RHS: "ptr")) {
2120 AsmTypeInfo Info;
2121 if (Parser.lookUpType(Name: Identifier, Info))
2122 return Error(L: Tok.getLoc(), Msg: "unknown type");
2123 SM.onCast(Info);
2124 // Eat type and PTR.
2125 consumeToken();
2126 End = consumeToken();
2127 break;
2128 }
2129 }
2130 // Register, or (MASM only) <register>.<field>
2131 MCRegister Reg;
2132 if (Tok.is(K: AsmToken::Identifier)) {
2133 if (!ParseRegister(RegNo&: Reg, StartLoc&: IdentLoc, EndLoc&: End, /*RestoreOnFailure=*/true)) {
2134 if (SM.onRegister(Reg, ErrMsg))
2135 return Error(L: SM.getErrorLoc(DefaultLoc: IdentLoc), Msg: ErrMsg);
2136 break;
2137 }
2138 if (Parser.isParsingMasm()) {
2139 const std::pair<StringRef, StringRef> IDField =
2140 Tok.getString().split(Separator: '.');
2141 const StringRef ID = IDField.first, Field = IDField.second;
2142 SMLoc IDEndLoc = SMLoc::getFromPointer(Ptr: ID.data() + ID.size());
2143 if (!Field.empty() &&
2144 !MatchRegisterByName(RegNo&: Reg, RegName: ID, StartLoc: IdentLoc, EndLoc: IDEndLoc)) {
2145 if (SM.onRegister(Reg, ErrMsg))
2146 return Error(L: SM.getErrorLoc(DefaultLoc: IdentLoc), Msg: ErrMsg);
2147
2148 AsmFieldInfo Info;
2149 SMLoc FieldStartLoc = SMLoc::getFromPointer(Ptr: Field.data());
2150 if (Parser.lookUpField(Name: Field, Info))
2151 return Error(L: FieldStartLoc, Msg: "unknown offset");
2152 else if (SM.onPlus(ErrMsg))
2153 return Error(L: getTok().getLoc(), Msg: ErrMsg);
2154 else if (SM.onInteger(TmpInt: Info.Offset, ErrMsg))
2155 return Error(L: SM.getErrorLoc(DefaultLoc: IdentLoc), Msg: ErrMsg);
2156 SM.setTypeInfo(Info.Type);
2157
2158 End = consumeToken();
2159 break;
2160 }
2161 }
2162 }
2163 // Operator synonymous ("not", "or" etc.)
2164 bool ParseError = false;
2165 if (ParseIntelNamedOperator(Name: Identifier, SM, ParseError, End)) {
2166 if (ParseError)
2167 return true;
2168 break;
2169 }
2170 if (Parser.isParsingMasm() &&
2171 ParseMasmNamedOperator(Name: Identifier, SM, ParseError, End)) {
2172 if (ParseError)
2173 return true;
2174 break;
2175 }
2176 // Symbol reference, when parsing assembly content
2177 InlineAsmIdentifierInfo Info;
2178 AsmFieldInfo FieldInfo;
2179 const MCExpr *Val;
2180 if (isParsingMSInlineAsm() || Parser.isParsingMasm()) {
2181 // MS Dot Operator expression
2182 if (Identifier.contains(C: '.') &&
2183 (PrevTK == AsmToken::RBrac || PrevTK == AsmToken::RParen)) {
2184 if (ParseIntelDotOperator(SM, End))
2185 return true;
2186 break;
2187 }
2188 }
2189 if (isParsingMSInlineAsm()) {
2190 // MS InlineAsm operators (TYPE/LENGTH/SIZE)
2191 if (unsigned OpKind = IdentifyIntelInlineAsmOperator(Name: Identifier)) {
2192 if (int64_t Val = ParseIntelInlineAsmOperator(OpKind)) {
2193 if (SM.onInteger(TmpInt: Val, ErrMsg))
2194 return Error(L: SM.getErrorLoc(DefaultLoc: IdentLoc), Msg: ErrMsg);
2195 } else {
2196 return true;
2197 }
2198 break;
2199 }
2200 // MS InlineAsm identifier
2201 // Call parseIdentifier() to combine @ with the identifier behind it.
2202 if (TK == AsmToken::At && Parser.parseIdentifier(Res&: Identifier))
2203 return Error(L: IdentLoc, Msg: "expected identifier");
2204 if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info, IsUnevaluatedOperand: false, End))
2205 return true;
2206 else if (SM.onIdentifierExpr(SymRef: Val, SymRefName: Identifier, IDInfo: Info, Type: FieldInfo.Type,
2207 ParsingMSInlineAsm: true, ErrMsg))
2208 return Error(L: SM.getErrorLoc(DefaultLoc: IdentLoc), Msg: ErrMsg);
2209 break;
2210 }
2211 if (Parser.isParsingMasm()) {
2212 if (unsigned OpKind = IdentifyMasmOperator(Name: Identifier)) {
2213 int64_t Val;
2214 if (ParseMasmOperator(OpKind, Val))
2215 return true;
2216 if (SM.onInteger(TmpInt: Val, ErrMsg))
2217 return Error(L: SM.getErrorLoc(DefaultLoc: IdentLoc), Msg: ErrMsg);
2218 break;
2219 }
2220 if (!getParser().lookUpType(Name: Identifier, Info&: FieldInfo.Type)) {
2221 // Field offset immediate; <TYPE>.<field specification>
2222 Lex(); // eat type
2223 bool EndDot = parseOptionalToken(T: AsmToken::Dot);
2224 while (EndDot || (getTok().is(K: AsmToken::Identifier) &&
2225 getTok().getString().starts_with(Prefix: "."))) {
2226 getParser().parseIdentifier(Res&: Identifier);
2227 if (!EndDot)
2228 Identifier.consume_front(Prefix: ".");
2229 EndDot = Identifier.consume_back(Suffix: ".");
2230 if (getParser().lookUpField(Base: FieldInfo.Type.Name, Member: Identifier,
2231 Info&: FieldInfo)) {
2232 SMLoc IDEnd =
2233 SMLoc::getFromPointer(Ptr: Identifier.data() + Identifier.size());
2234 return Error(L: IdentLoc, Msg: "Unable to lookup field reference!",
2235 Range: SMRange(IdentLoc, IDEnd));
2236 }
2237 if (!EndDot)
2238 EndDot = parseOptionalToken(T: AsmToken::Dot);
2239 }
2240 if (SM.onInteger(TmpInt: FieldInfo.Offset, ErrMsg))
2241 return Error(L: SM.getErrorLoc(DefaultLoc: IdentLoc), Msg: ErrMsg);
2242 break;
2243 }
2244 }
2245 if (getParser().parsePrimaryExpr(Res&: Val, EndLoc&: End, TypeInfo: &FieldInfo.Type)) {
2246 return Error(L: Tok.getLoc(), Msg: "Unexpected identifier!");
2247 } else if (SM.onIdentifierExpr(SymRef: Val, SymRefName: Identifier, IDInfo: Info, Type: FieldInfo.Type,
2248 ParsingMSInlineAsm: false, ErrMsg)) {
2249 return Error(L: SM.getErrorLoc(DefaultLoc: IdentLoc), Msg: ErrMsg);
2250 }
2251 break;
2252 }
2253 case AsmToken::Integer: {
2254 // Look for 'b' or 'f' following an Integer as a directional label
2255 SMLoc Loc = getTok().getLoc();
2256 int64_t IntVal = getTok().getIntVal();
2257 End = consumeToken();
2258 UpdateLocLex = false;
2259 if (getLexer().getKind() == AsmToken::Identifier) {
2260 StringRef IDVal = getTok().getString();
2261 if (IDVal == "f" || IDVal == "b") {
2262 MCSymbol *Sym =
2263 getContext().getDirectionalLocalSymbol(LocalLabelVal: IntVal, Before: IDVal == "b");
2264 auto Variant = X86::S_None;
2265 const MCExpr *Val =
2266 MCSymbolRefExpr::create(Symbol: Sym, specifier: Variant, Ctx&: getContext());
2267 if (IDVal == "b" && Sym->isUndefined())
2268 return Error(L: Loc, Msg: "invalid reference to undefined symbol");
2269 StringRef Identifier = Sym->getName();
2270 InlineAsmIdentifierInfo Info;
2271 AsmTypeInfo Type;
2272 if (SM.onIdentifierExpr(SymRef: Val, SymRefName: Identifier, IDInfo: Info, Type,
2273 ParsingMSInlineAsm: isParsingMSInlineAsm(), ErrMsg))
2274 return Error(L: SM.getErrorLoc(DefaultLoc: Loc), Msg: ErrMsg);
2275 End = consumeToken();
2276 } else {
2277 if (SM.onInteger(TmpInt: IntVal, ErrMsg))
2278 return Error(L: SM.getErrorLoc(DefaultLoc: Loc), Msg: ErrMsg);
2279 }
2280 } else {
2281 if (SM.onInteger(TmpInt: IntVal, ErrMsg))
2282 return Error(L: SM.getErrorLoc(DefaultLoc: Loc), Msg: ErrMsg);
2283 }
2284 break;
2285 }
2286 case AsmToken::Plus:
2287 if (SM.onPlus(ErrMsg))
2288 return Error(L: getTok().getLoc(), Msg: ErrMsg);
2289 break;
2290 case AsmToken::Minus:
2291 if (SM.onMinus(MinusLoc: getTok().getLoc(), ErrMsg))
2292 return Error(L: SM.getErrorLoc(DefaultLoc: getTok().getLoc()), Msg: ErrMsg);
2293 break;
2294 case AsmToken::Tilde: SM.onNot(); break;
2295 case AsmToken::Star: SM.onStar(); break;
2296 case AsmToken::Slash: SM.onDivide(); break;
2297 case AsmToken::Percent: SM.onMod(); break;
2298 case AsmToken::Pipe: SM.onOr(); break;
2299 case AsmToken::Caret: SM.onXor(); break;
2300 case AsmToken::Amp: SM.onAnd(); break;
2301 case AsmToken::LessLess:
2302 SM.onLShift(); break;
2303 case AsmToken::GreaterGreater:
2304 SM.onRShift(); break;
2305 case AsmToken::LBrac:
2306 if (SM.onLBrac())
2307 return Error(L: Tok.getLoc(), Msg: "unexpected bracket encountered");
2308 tryParseOperandIdx(PrevTK, SM);
2309 break;
2310 case AsmToken::RBrac:
2311 if (SM.onRBrac(ErrMsg)) {
2312 return Error(L: SM.getErrorLoc(DefaultLoc: Tok.getLoc()), Msg: ErrMsg);
2313 }
2314 break;
2315 case AsmToken::LParen:
2316 SM.onLParen(Loc: Tok.getLoc());
2317 break;
2318 case AsmToken::RParen:
2319 if (SM.onRParen(ErrMsg)) {
2320 return Error(L: SM.getErrorLoc(DefaultLoc: Tok.getLoc()), Msg: ErrMsg);
2321 }
2322 break;
2323 }
2324 if (SM.hadError())
2325 return Error(L: Tok.getLoc(), Msg: "unknown token in expression");
2326
2327 if (!Done && UpdateLocLex)
2328 End = consumeToken();
2329
2330 PrevTK = TK;
2331 }
2332 if (SM.hasUnmatchedParen())
2333 return Error(L: SM.getLParenLoc(), Msg: "unmatched parenthesis");
2334 return false;
2335}
2336
2337void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM,
2338 SMLoc Start, SMLoc End) {
2339 SMLoc Loc = Start;
2340 unsigned ExprLen = End.getPointer() - Start.getPointer();
2341 // Skip everything before a symbol displacement (if we have one)
2342 if (SM.getSym() && !SM.isOffsetOperator()) {
2343 StringRef SymName = SM.getSymName();
2344 if (unsigned Len = SymName.data() - Start.getPointer())
2345 InstInfo->AsmRewrites->emplace_back(Args: AOK_Skip, Args&: Start, Args&: Len);
2346 Loc = SMLoc::getFromPointer(Ptr: SymName.data() + SymName.size());
2347 ExprLen = End.getPointer() - (SymName.data() + SymName.size());
2348 // If we have only a symbol than there's no need for complex rewrite,
2349 // simply skip everything after it
2350 if (!(SM.getBaseReg() || SM.getIndexReg() || SM.getImm())) {
2351 if (ExprLen)
2352 InstInfo->AsmRewrites->emplace_back(Args: AOK_Skip, Args&: Loc, Args&: ExprLen);
2353 return;
2354 }
2355 }
2356 // Build an Intel Expression rewrite
2357 StringRef BaseRegStr;
2358 StringRef IndexRegStr;
2359 StringRef OffsetNameStr;
2360 if (SM.getBaseReg())
2361 BaseRegStr = X86IntelInstPrinter::getRegisterName(Reg: SM.getBaseReg());
2362 if (SM.getIndexReg())
2363 IndexRegStr = X86IntelInstPrinter::getRegisterName(Reg: SM.getIndexReg());
2364 if (SM.isOffsetOperator())
2365 OffsetNameStr = SM.getSymName();
2366 // Emit it
2367 IntelExpr Expr(BaseRegStr, IndexRegStr, SM.getScale(), OffsetNameStr,
2368 SM.getImm(), SM.isMemExpr());
2369 InstInfo->AsmRewrites->emplace_back(Args&: Loc, Args&: ExprLen, Args&: Expr);
2370}
2371
2372// Inline assembly may use variable names with namespace alias qualifiers.
2373bool X86AsmParser::ParseIntelInlineAsmIdentifier(
2374 const MCExpr *&Val, StringRef &Identifier, InlineAsmIdentifierInfo &Info,
2375 bool IsUnevaluatedOperand, SMLoc &End, bool IsParsingOffsetOperator) {
2376 MCAsmParser &Parser = getParser();
2377 assert(isParsingMSInlineAsm() && "Expected to be parsing inline assembly.");
2378 Val = nullptr;
2379
2380 StringRef LineBuf(Identifier.data());
2381 SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedContext: IsUnevaluatedOperand);
2382
2383 const AsmToken &Tok = Parser.getTok();
2384 SMLoc Loc = Tok.getLoc();
2385
2386 // Advance the token stream until the end of the current token is
2387 // after the end of what the frontend claimed.
2388 const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
2389 do {
2390 End = Tok.getEndLoc();
2391 getLexer().Lex();
2392 } while (End.getPointer() < EndPtr);
2393 Identifier = LineBuf;
2394
2395 // The frontend should end parsing on an assembler token boundary, unless it
2396 // failed parsing.
2397 assert((End.getPointer() == EndPtr ||
2398 Info.isKind(InlineAsmIdentifierInfo::IK_Invalid)) &&
2399 "frontend claimed part of a token?");
2400
2401 // If the identifier lookup was unsuccessful, assume that we are dealing with
2402 // a label.
2403 if (Info.isKind(kind: InlineAsmIdentifierInfo::IK_Invalid)) {
2404 StringRef InternalName =
2405 SemaCallback->LookupInlineAsmLabel(Identifier, SM&: getSourceManager(),
2406 Location: Loc, Create: false);
2407 assert(InternalName.size() && "We should have an internal name here.");
2408 // Push a rewrite for replacing the identifier name with the internal name,
2409 // unless we are parsing the operand of an offset operator
2410 if (!IsParsingOffsetOperator)
2411 InstInfo->AsmRewrites->emplace_back(Args: AOK_Label, Args&: Loc, Args: Identifier.size(),
2412 Args&: InternalName);
2413 else
2414 Identifier = InternalName;
2415 } else if (Info.isKind(kind: InlineAsmIdentifierInfo::IK_EnumVal))
2416 return false;
2417 // Create the symbol reference.
2418 MCSymbol *Sym = getContext().getOrCreateSymbol(Name: Identifier);
2419 auto Variant = X86::S_None;
2420 Val = MCSymbolRefExpr::create(Symbol: Sym, specifier: Variant, Ctx&: getParser().getContext());
2421 return false;
2422}
2423
2424//ParseRoundingModeOp - Parse AVX-512 rounding mode operand
2425bool X86AsmParser::ParseRoundingModeOp(SMLoc Start, OperandVector &Operands) {
2426 MCAsmParser &Parser = getParser();
2427 const AsmToken &Tok = Parser.getTok();
2428 // Eat "{" and mark the current place.
2429 const SMLoc consumedToken = consumeToken();
2430 if (Tok.isNot(K: AsmToken::Identifier))
2431 return Error(L: Tok.getLoc(), Msg: "Expected an identifier after {");
2432 if (Tok.getIdentifier().starts_with(Prefix: "r")) {
2433 int rndMode = StringSwitch<int>(Tok.getIdentifier())
2434 .Case(S: "rn", Value: X86::STATIC_ROUNDING::TO_NEAREST_INT)
2435 .Case(S: "rd", Value: X86::STATIC_ROUNDING::TO_NEG_INF)
2436 .Case(S: "ru", Value: X86::STATIC_ROUNDING::TO_POS_INF)
2437 .Case(S: "rz", Value: X86::STATIC_ROUNDING::TO_ZERO)
2438 .Default(Value: -1);
2439 if (-1 == rndMode)
2440 return Error(L: Tok.getLoc(), Msg: "Invalid rounding mode.");
2441 Parser.Lex(); // Eat "r*" of r*-sae
2442 if (!getLexer().is(K: AsmToken::Minus))
2443 return Error(L: Tok.getLoc(), Msg: "Expected - at this point");
2444 Parser.Lex(); // Eat "-"
2445 Parser.Lex(); // Eat the sae
2446 if (!getLexer().is(K: AsmToken::RCurly))
2447 return Error(L: Tok.getLoc(), Msg: "Expected } at this point");
2448 SMLoc End = Tok.getEndLoc();
2449 Parser.Lex(); // Eat "}"
2450 const MCExpr *RndModeOp =
2451 MCConstantExpr::create(Value: rndMode, Ctx&: Parser.getContext());
2452 Operands.push_back(Elt: X86Operand::CreateImm(Val: RndModeOp, StartLoc: Start, EndLoc: End));
2453 return false;
2454 }
2455 if (Tok.getIdentifier() == "sae") {
2456 Parser.Lex(); // Eat the sae
2457 if (!getLexer().is(K: AsmToken::RCurly))
2458 return Error(L: Tok.getLoc(), Msg: "Expected } at this point");
2459 Parser.Lex(); // Eat "}"
2460 Operands.push_back(Elt: X86Operand::CreateToken(Str: "{sae}", Loc: consumedToken));
2461 return false;
2462 }
2463 return Error(L: Tok.getLoc(), Msg: "unknown token in expression");
2464}
2465
2466/// Parse condtional flags for CCMP/CTEST, e.g {dfv=of,sf,zf,cf} right after
2467/// mnemonic.
2468bool X86AsmParser::parseCFlagsOp(OperandVector &Operands) {
2469 MCAsmParser &Parser = getParser();
2470 AsmToken Tok = Parser.getTok();
2471 const SMLoc Start = Tok.getLoc();
2472 if (!Tok.is(K: AsmToken::LCurly))
2473 return Error(L: Tok.getLoc(), Msg: "Expected { at this point");
2474 Parser.Lex(); // Eat "{"
2475 Tok = Parser.getTok();
2476 if (Tok.getIdentifier().lower() != "dfv")
2477 return Error(L: Tok.getLoc(), Msg: "Expected dfv at this point");
2478 Parser.Lex(); // Eat "dfv"
2479 Tok = Parser.getTok();
2480 if (!Tok.is(K: AsmToken::Equal))
2481 return Error(L: Tok.getLoc(), Msg: "Expected = at this point");
2482 Parser.Lex(); // Eat "="
2483
2484 Tok = Parser.getTok();
2485 SMLoc End;
2486 if (Tok.is(K: AsmToken::RCurly)) {
2487 End = Tok.getEndLoc();
2488 Operands.push_back(Elt: X86Operand::CreateImm(
2489 Val: MCConstantExpr::create(Value: 0, Ctx&: Parser.getContext()), StartLoc: Start, EndLoc: End));
2490 Parser.Lex(); // Eat "}"
2491 return false;
2492 }
2493 unsigned CFlags = 0;
2494 for (unsigned I = 0; I < 4; ++I) {
2495 Tok = Parser.getTok();
2496 unsigned CFlag = StringSwitch<unsigned>(Tok.getIdentifier().lower())
2497 .Case(S: "of", Value: 0x8)
2498 .Case(S: "sf", Value: 0x4)
2499 .Case(S: "zf", Value: 0x2)
2500 .Case(S: "cf", Value: 0x1)
2501 .Default(Value: ~0U);
2502 if (CFlag == ~0U)
2503 return Error(L: Tok.getLoc(), Msg: "Invalid conditional flags");
2504
2505 if (CFlags & CFlag)
2506 return Error(L: Tok.getLoc(), Msg: "Duplicated conditional flag");
2507 CFlags |= CFlag;
2508
2509 Parser.Lex(); // Eat one conditional flag
2510 Tok = Parser.getTok();
2511 if (Tok.is(K: AsmToken::RCurly)) {
2512 End = Tok.getEndLoc();
2513 Operands.push_back(Elt: X86Operand::CreateImm(
2514 Val: MCConstantExpr::create(Value: CFlags, Ctx&: Parser.getContext()), StartLoc: Start, EndLoc: End));
2515 Parser.Lex(); // Eat "}"
2516 return false;
2517 } else if (I == 3) {
2518 return Error(L: Tok.getLoc(), Msg: "Expected } at this point");
2519 } else if (Tok.isNot(K: AsmToken::Comma)) {
2520 return Error(L: Tok.getLoc(), Msg: "Expected } or , at this point");
2521 }
2522 Parser.Lex(); // Eat ","
2523 }
2524 llvm_unreachable("Unexpected control flow");
2525}
2526
2527/// Parse the '.' operator.
2528bool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM,
2529 SMLoc &End) {
2530 const AsmToken &Tok = getTok();
2531 AsmFieldInfo Info;
2532
2533 // Drop the optional '.'.
2534 StringRef DotDispStr = Tok.getString();
2535 DotDispStr.consume_front(Prefix: ".");
2536 bool TrailingDot = false;
2537
2538 // .Imm gets lexed as a real.
2539 if (Tok.is(K: AsmToken::Real)) {
2540 APInt DotDisp;
2541 if (DotDispStr.getAsInteger(Radix: 10, Result&: DotDisp))
2542 return Error(L: Tok.getLoc(), Msg: "Unexpected offset");
2543 Info.Offset = DotDisp.getZExtValue();
2544 } else if ((isParsingMSInlineAsm() || getParser().isParsingMasm()) &&
2545 Tok.is(K: AsmToken::Identifier)) {
2546 TrailingDot = DotDispStr.consume_back(Suffix: ".");
2547 const std::pair<StringRef, StringRef> BaseMember = DotDispStr.split(Separator: '.');
2548 const StringRef Base = BaseMember.first, Member = BaseMember.second;
2549 if (getParser().lookUpField(Base: SM.getType(), Member: DotDispStr, Info) &&
2550 getParser().lookUpField(Base: SM.getSymName(), Member: DotDispStr, Info) &&
2551 getParser().lookUpField(Name: DotDispStr, Info) &&
2552 (!SemaCallback ||
2553 SemaCallback->LookupInlineAsmField(Base, Member, Offset&: Info.Offset)))
2554 return Error(L: Tok.getLoc(), Msg: "Unable to lookup field reference!");
2555 } else {
2556 return Error(L: Tok.getLoc(), Msg: "Unexpected token type!");
2557 }
2558
2559 // Eat the DotExpression and update End
2560 End = SMLoc::getFromPointer(Ptr: DotDispStr.data());
2561 const char *DotExprEndLoc = DotDispStr.data() + DotDispStr.size();
2562 while (Tok.getLoc().getPointer() < DotExprEndLoc)
2563 Lex();
2564 if (TrailingDot)
2565 getLexer().UnLex(Token: AsmToken(AsmToken::Dot, "."));
2566 SM.addImm(imm: Info.Offset);
2567 SM.setTypeInfo(Info.Type);
2568 return false;
2569}
2570
2571/// Parse the 'offset' operator.
2572/// This operator is used to specify the location of a given operand
2573bool X86AsmParser::ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID,
2574 InlineAsmIdentifierInfo &Info,
2575 SMLoc &End) {
2576 // Eat offset, mark start of identifier.
2577 SMLoc Start = Lex().getLoc();
2578 ID = getTok().getString();
2579 if (!isParsingMSInlineAsm()) {
2580 if ((getTok().isNot(K: AsmToken::Identifier) &&
2581 getTok().isNot(K: AsmToken::String)) ||
2582 getParser().parsePrimaryExpr(Res&: Val, EndLoc&: End, TypeInfo: nullptr))
2583 return Error(L: Start, Msg: "unexpected token!");
2584 } else if (ParseIntelInlineAsmIdentifier(Val, Identifier&: ID, Info, IsUnevaluatedOperand: false, End, IsParsingOffsetOperator: true)) {
2585 return Error(L: Start, Msg: "unable to lookup expression");
2586 } else if (Info.isKind(kind: InlineAsmIdentifierInfo::IK_EnumVal)) {
2587 return Error(L: Start, Msg: "offset operator cannot yet handle constants");
2588 }
2589 return false;
2590}
2591
2592/// Parse the 'imagerel' operator.
2593/// This operator is used to specify an image-relative reference to a symbol.
2594bool X86AsmParser::ParseIntelImagerelOperator(const MCExpr *&Val, StringRef &ID,
2595 InlineAsmIdentifierInfo &Info,
2596 SMLoc &End) {
2597 // Eat imagerel, mark start of identifier.
2598 SMLoc Start = Lex().getLoc();
2599 ID = getTok().getString();
2600 if (!isParsingMSInlineAsm()) {
2601 if ((getTok().isNot(K: AsmToken::Identifier) &&
2602 getTok().isNot(K: AsmToken::String)) ||
2603 getParser().parsePrimaryExpr(Res&: Val, EndLoc&: End, TypeInfo: nullptr))
2604 return Error(L: Start, Msg: "unexpected token!");
2605 } else if (ParseIntelInlineAsmIdentifier(Val, Identifier&: ID, Info, IsUnevaluatedOperand: false, End, IsParsingOffsetOperator: true)) {
2606 return Error(L: Start, Msg: "unable to lookup expression");
2607 } else if (Info.isKind(kind: InlineAsmIdentifierInfo::IK_EnumVal)) {
2608 return Error(L: Start, Msg: "imagerel operator cannot yet handle constants");
2609 }
2610
2611 const MCExpr *ModifiedVal =
2612 getParser().applySpecifier(E: Val, Variant: MCSymbolRefExpr::VK_COFF_IMGREL32);
2613 if (!ModifiedVal)
2614 return Error(L: Start, Msg: "cannot apply 'imagerel' to this expression");
2615 Val = ModifiedVal;
2616 return false;
2617}
2618
2619// Query a candidate string for being an Intel assembly operator
2620// Report back its kind, or IOK_INVALID if does not evaluated as a known one
2621unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) {
2622 return StringSwitch<unsigned>(Name)
2623 .Cases(CaseStrings: {"TYPE", "type"}, Value: IOK_TYPE)
2624 .Cases(CaseStrings: {"SIZE", "size"}, Value: IOK_SIZE)
2625 .Cases(CaseStrings: {"LENGTH", "length"}, Value: IOK_LENGTH)
2626 .Default(Value: IOK_INVALID);
2627}
2628
2629/// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
2630/// returns the number of elements in an array. It returns the value 1 for
2631/// non-array variables. The SIZE operator returns the size of a C or C++
2632/// variable. A variable's size is the product of its LENGTH and TYPE. The
2633/// TYPE operator returns the size of a C or C++ type or variable. If the
2634/// variable is an array, TYPE returns the size of a single element.
2635unsigned X86AsmParser::ParseIntelInlineAsmOperator(unsigned OpKind) {
2636 MCAsmParser &Parser = getParser();
2637 const AsmToken &Tok = Parser.getTok();
2638 Parser.Lex(); // Eat operator.
2639
2640 const MCExpr *Val = nullptr;
2641 InlineAsmIdentifierInfo Info;
2642 SMLoc Start = Tok.getLoc(), End;
2643 StringRef Identifier = Tok.getString();
2644 if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
2645 /*IsUnevaluatedOperand=*/true, End))
2646 return 0;
2647
2648 if (!Info.isKind(kind: InlineAsmIdentifierInfo::IK_Var)) {
2649 Error(L: Start, Msg: "unable to lookup expression");
2650 return 0;
2651 }
2652
2653 unsigned CVal = 0;
2654 switch(OpKind) {
2655 default: llvm_unreachable("Unexpected operand kind!");
2656 case IOK_LENGTH: CVal = Info.Var.Length; break;
2657 case IOK_SIZE: CVal = Info.Var.Size; break;
2658 case IOK_TYPE: CVal = Info.Var.Type; break;
2659 }
2660
2661 return CVal;
2662}
2663
2664// Query a candidate string for being an Intel assembly operator
2665// Report back its kind, or IOK_INVALID if does not evaluated as a known one
2666unsigned X86AsmParser::IdentifyMasmOperator(StringRef Name) {
2667 return StringSwitch<unsigned>(Name.lower())
2668 .Case(S: "type", Value: MOK_TYPE)
2669 .Cases(CaseStrings: {"size", "sizeof"}, Value: MOK_SIZEOF)
2670 .Cases(CaseStrings: {"length", "lengthof"}, Value: MOK_LENGTHOF)
2671 .Default(Value: MOK_INVALID);
2672}
2673
2674/// Parse the 'LENGTHOF', 'SIZEOF', and 'TYPE' operators. The LENGTHOF operator
2675/// returns the number of elements in an array. It returns the value 1 for
2676/// non-array variables. The SIZEOF operator returns the size of a type or
2677/// variable in bytes. A variable's size is the product of its LENGTH and TYPE.
2678/// The TYPE operator returns the size of a variable. If the variable is an
2679/// array, TYPE returns the size of a single element.
2680bool X86AsmParser::ParseMasmOperator(unsigned OpKind, int64_t &Val) {
2681 MCAsmParser &Parser = getParser();
2682 SMLoc OpLoc = Parser.getTok().getLoc();
2683 Parser.Lex(); // Eat operator.
2684
2685 Val = 0;
2686 if (OpKind == MOK_SIZEOF || OpKind == MOK_TYPE) {
2687 // Check for SIZEOF(<type>) and TYPE(<type>).
2688 bool InParens = Parser.getTok().is(K: AsmToken::LParen);
2689 const AsmToken &IDTok = InParens ? getLexer().peekTok() : Parser.getTok();
2690 AsmTypeInfo Type;
2691 if (IDTok.is(K: AsmToken::Identifier) &&
2692 !Parser.lookUpType(Name: IDTok.getIdentifier(), Info&: Type)) {
2693 Val = Type.Size;
2694
2695 // Eat tokens.
2696 if (InParens)
2697 parseToken(T: AsmToken::LParen);
2698 parseToken(T: AsmToken::Identifier);
2699 if (InParens)
2700 parseToken(T: AsmToken::RParen);
2701 }
2702 }
2703
2704 if (!Val) {
2705 IntelExprStateMachine SM;
2706 SMLoc End, Start = Parser.getTok().getLoc();
2707 if (ParseIntelExpression(SM, End))
2708 return true;
2709
2710 switch (OpKind) {
2711 default:
2712 llvm_unreachable("Unexpected operand kind!");
2713 case MOK_SIZEOF:
2714 Val = SM.getSize();
2715 break;
2716 case MOK_LENGTHOF:
2717 Val = SM.getLength();
2718 break;
2719 case MOK_TYPE:
2720 Val = SM.getElementSize();
2721 break;
2722 }
2723
2724 if (!Val)
2725 return Error(L: OpLoc, Msg: "expression has unknown type", Range: SMRange(Start, End));
2726 }
2727
2728 return false;
2729}
2730
2731bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size,
2732 StringRef *SizeStr) {
2733 Size = StringSwitch<unsigned>(getTok().getString())
2734 .Cases(CaseStrings: {"BYTE", "byte"}, Value: 8)
2735 .Cases(CaseStrings: {"WORD", "word"}, Value: 16)
2736 .Cases(CaseStrings: {"DWORD", "dword"}, Value: 32)
2737 .Cases(CaseStrings: {"FLOAT", "float"}, Value: 32)
2738 .Cases(CaseStrings: {"LONG", "long"}, Value: 32)
2739 .Cases(CaseStrings: {"FWORD", "fword"}, Value: 48)
2740 .Cases(CaseStrings: {"DOUBLE", "double"}, Value: 64)
2741 .Cases(CaseStrings: {"QWORD", "qword"}, Value: 64)
2742 .Cases(CaseStrings: {"MMWORD", "mmword"}, Value: 64)
2743 .Cases(CaseStrings: {"XWORD", "xword"}, Value: 80)
2744 .Cases(CaseStrings: {"TBYTE", "tbyte"}, Value: 80)
2745 .Cases(CaseStrings: {"XMMWORD", "xmmword"}, Value: 128)
2746 .Cases(CaseStrings: {"YMMWORD", "ymmword"}, Value: 256)
2747 .Cases(CaseStrings: {"ZMMWORD", "zmmword"}, Value: 512)
2748 .Default(Value: 0);
2749 if (Size) {
2750 if (SizeStr)
2751 *SizeStr = getTok().getString();
2752 const AsmToken &Tok = Lex(); // Eat operand size (e.g., byte, word).
2753 if (!(Tok.getString() == "PTR" || Tok.getString() == "ptr"))
2754 return Error(L: Tok.getLoc(), Msg: "Expected 'PTR' or 'ptr' token!");
2755 Lex(); // Eat ptr.
2756 }
2757 return false;
2758}
2759
2760uint16_t RegSizeInBits(const MCRegisterInfo &MRI, MCRegister RegNo) {
2761 if (getX86MCRegisterClass(RC: X86::GR8RegClassID).contains(Reg: RegNo))
2762 return 8;
2763 if (getX86MCRegisterClass(RC: X86::GR16RegClassID).contains(Reg: RegNo))
2764 return 16;
2765 if (getX86MCRegisterClass(RC: X86::GR32RegClassID).contains(Reg: RegNo))
2766 return 32;
2767 if (getX86MCRegisterClass(RC: X86::GR64RegClassID).contains(Reg: RegNo))
2768 return 64;
2769 // Unknown register size
2770 return 0;
2771}
2772
2773bool X86AsmParser::parseIntelOperand(OperandVector &Operands, StringRef Name) {
2774 MCAsmParser &Parser = getParser();
2775 const AsmToken &Tok = Parser.getTok();
2776 SMLoc Start, End;
2777
2778 // Parse optional Size directive.
2779 unsigned Size;
2780 StringRef SizeStr;
2781 if (ParseIntelMemoryOperandSize(Size, SizeStr: &SizeStr))
2782 return true;
2783 bool PtrInOperand = bool(Size);
2784
2785 Start = Tok.getLoc();
2786
2787 // Rounding mode operand.
2788 if (getLexer().is(K: AsmToken::LCurly))
2789 return ParseRoundingModeOp(Start, Operands);
2790
2791 // Register operand.
2792 MCRegister RegNo;
2793 if (Tok.is(K: AsmToken::Identifier) && !parseRegister(Reg&: RegNo, StartLoc&: Start, EndLoc&: End)) {
2794 if (RegNo == X86::RIP)
2795 return Error(L: Start, Msg: "rip can only be used as a base register");
2796 // A Register followed by ':' is considered a segment override
2797 if (Tok.isNot(K: AsmToken::Colon)) {
2798 if (PtrInOperand) {
2799 if (!Parser.isParsingMasm())
2800 return Error(L: Start, Msg: "expected memory operand after 'ptr', "
2801 "found register operand instead");
2802
2803 // If we are parsing MASM, we are allowed to cast registers to their own
2804 // sizes, but not to other types.
2805 uint16_t RegSize =
2806 RegSizeInBits(MRI: *getContext().getRegisterInfo(), RegNo);
2807 if (RegSize == 0)
2808 return Error(
2809 L: Start,
2810 Msg: "cannot cast register '" +
2811 StringRef(getContext().getRegisterInfo()->getName(RegNo)) +
2812 "'; its size is not easily defined.");
2813 if (RegSize != Size)
2814 return Error(
2815 L: Start,
2816 Msg: std::to_string(val: RegSize) + "-bit register '" +
2817 StringRef(getContext().getRegisterInfo()->getName(RegNo)) +
2818 "' cannot be used as a " + std::to_string(val: Size) + "-bit " +
2819 SizeStr.upper());
2820 }
2821 Operands.push_back(Elt: X86Operand::CreateReg(Reg: RegNo, StartLoc: Start, EndLoc: End));
2822 return false;
2823 }
2824 // An alleged segment override. check if we have a valid segment register
2825 if (!getX86MCRegisterClass(RC: X86::SEGMENT_REGRegClassID).contains(Reg: RegNo))
2826 return Error(L: Start, Msg: "invalid segment register");
2827 // Eat ':' and update Start location
2828 Start = Lex().getLoc();
2829 }
2830
2831 // Immediates and Memory
2832 IntelExprStateMachine SM;
2833 if (ParseIntelExpression(SM, End))
2834 return true;
2835
2836 if (isParsingMSInlineAsm())
2837 RewriteIntelExpression(SM, Start, End: Tok.getLoc());
2838
2839 int64_t Imm = SM.getImm();
2840 const MCExpr *Disp = SM.getSym();
2841 const MCExpr *ImmDisp = MCConstantExpr::create(Value: Imm, Ctx&: getContext());
2842 if (Disp && Imm)
2843 Disp = MCBinaryExpr::createAdd(LHS: Disp, RHS: ImmDisp, Ctx&: getContext());
2844 if (!Disp)
2845 Disp = ImmDisp;
2846
2847 // RegNo != 0 specifies a valid segment register,
2848 // and we are parsing a segment override
2849 if (!SM.isMemExpr() && !RegNo) {
2850 if (isParsingMSInlineAsm() && SM.isOffsetOperator()) {
2851 const InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
2852 if (Info.isKind(kind: InlineAsmIdentifierInfo::IK_Var)) {
2853 // Disp includes the address of a variable; make sure this is recorded
2854 // for later handling.
2855 Operands.push_back(Elt: X86Operand::CreateImm(Val: Disp, StartLoc: Start, EndLoc: End,
2856 SymName: SM.getSymName(), OpDecl: Info.Var.Decl,
2857 GlobalRef: Info.Var.IsGlobalLV));
2858 return false;
2859 }
2860 }
2861
2862 Operands.push_back(Elt: X86Operand::CreateImm(Val: Disp, StartLoc: Start, EndLoc: End));
2863 return false;
2864 }
2865
2866 StringRef ErrMsg;
2867 MCRegister BaseReg = SM.getBaseReg();
2868 MCRegister IndexReg = SM.getIndexReg();
2869 if (IndexReg && BaseReg == X86::RIP)
2870 BaseReg = MCRegister();
2871 unsigned Scale = SM.getScale();
2872 if (!PtrInOperand)
2873 Size = SM.getElementSize() << 3;
2874
2875 if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP &&
2876 (IndexReg == X86::ESP || IndexReg == X86::RSP))
2877 std::swap(a&: BaseReg, b&: IndexReg);
2878
2879 // If BaseReg is a vector register and IndexReg is not, swap them unless
2880 // Scale was specified in which case it would be an error.
2881 if (Scale == 0 &&
2882 !(getX86MCRegisterClass(RC: X86::VR128XRegClassID).contains(Reg: IndexReg) ||
2883 getX86MCRegisterClass(RC: X86::VR256XRegClassID).contains(Reg: IndexReg) ||
2884 getX86MCRegisterClass(RC: X86::VR512RegClassID).contains(Reg: IndexReg)) &&
2885 (getX86MCRegisterClass(RC: X86::VR128XRegClassID).contains(Reg: BaseReg) ||
2886 getX86MCRegisterClass(RC: X86::VR256XRegClassID).contains(Reg: BaseReg) ||
2887 getX86MCRegisterClass(RC: X86::VR512RegClassID).contains(Reg: BaseReg)))
2888 std::swap(a&: BaseReg, b&: IndexReg);
2889
2890 if (Scale != 0 &&
2891 getX86MCRegisterClass(RC: X86::GR16RegClassID).contains(Reg: IndexReg))
2892 return Error(L: Start, Msg: "16-bit addresses cannot have a scale");
2893
2894 // If there was no explicit scale specified, change it to 1.
2895 if (Scale == 0)
2896 Scale = 1;
2897
2898 // If this is a 16-bit addressing mode with the base and index in the wrong
2899 // order, swap them so CheckBaseRegAndIndexRegAndScale doesn't fail. It is
2900 // shared with att syntax where order matters.
2901 if ((BaseReg == X86::SI || BaseReg == X86::DI) &&
2902 (IndexReg == X86::BX || IndexReg == X86::BP))
2903 std::swap(a&: BaseReg, b&: IndexReg);
2904
2905 if ((BaseReg || IndexReg) &&
2906 CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, Is64BitMode: is64BitMode(),
2907 ErrMsg))
2908 return Error(L: Start, Msg: ErrMsg);
2909 bool IsUnconditionalBranch =
2910 Name.equals_insensitive(RHS: "jmp") || Name.equals_insensitive(RHS: "call");
2911 if (isParsingMSInlineAsm())
2912 return CreateMemForMSInlineAsm(SegReg: RegNo, Disp, BaseReg, IndexReg, Scale,
2913 NonAbsMem: IsUnconditionalBranch && is64BitMode(),
2914 Start, End, Size, Identifier: SM.getSymName(),
2915 Info: SM.getIdentifierInfo(), Operands);
2916
2917 // When parsing x64 MS-style assembly, all non-absolute references to a named
2918 // variable default to RIP-relative.
2919 MCRegister DefaultBaseReg;
2920 bool MaybeDirectBranchDest = true;
2921
2922 if (Parser.isParsingMasm()) {
2923 if (is64BitMode() &&
2924 ((PtrInOperand && !IndexReg) || SM.getElementSize() > 0)) {
2925 DefaultBaseReg = X86::RIP;
2926 }
2927 if (IsUnconditionalBranch) {
2928 if (PtrInOperand) {
2929 MaybeDirectBranchDest = false;
2930 if (is64BitMode())
2931 DefaultBaseReg = X86::RIP;
2932 } else if (!BaseReg && !IndexReg && Disp &&
2933 Disp->getKind() == MCExpr::SymbolRef) {
2934 if (is64BitMode()) {
2935 if (SM.getSize() == 8) {
2936 MaybeDirectBranchDest = false;
2937 DefaultBaseReg = X86::RIP;
2938 }
2939 } else {
2940 if (SM.getSize() == 4 || SM.getSize() == 2)
2941 MaybeDirectBranchDest = false;
2942 }
2943 }
2944 }
2945 } else if (IsUnconditionalBranch) {
2946 // Treat `call [offset fn_ref]` (or `jmp`) syntax as an error.
2947 if (!PtrInOperand && SM.isOffsetOperator())
2948 return Error(
2949 L: Start, Msg: "`OFFSET` operator cannot be used in an unconditional branch");
2950 if (PtrInOperand || SM.isBracketUsed())
2951 MaybeDirectBranchDest = false;
2952 }
2953
2954 if (CheckDispOverflow(BaseReg, IndexReg, Disp, Loc: Start))
2955 return true;
2956
2957 if ((BaseReg || IndexReg || RegNo || DefaultBaseReg))
2958 Operands.push_back(Elt: X86Operand::CreateMem(
2959 ModeSize: getPointerWidth(), SegReg: RegNo, Disp, BaseReg, IndexReg, Scale, StartLoc: Start, EndLoc: End,
2960 Size, DefaultBaseReg, /*SymName=*/StringRef(), /*OpDecl=*/nullptr,
2961 /*FrontendSize=*/0, /*UseUpRegs=*/false, MaybeDirectBranchDest));
2962 else
2963 Operands.push_back(Elt: X86Operand::CreateMem(
2964 ModeSize: getPointerWidth(), Disp, StartLoc: Start, EndLoc: End, Size, /*SymName=*/StringRef(),
2965 /*OpDecl=*/nullptr, /*FrontendSize=*/0, /*UseUpRegs=*/false,
2966 MaybeDirectBranchDest));
2967 return false;
2968}
2969
2970bool X86AsmParser::parseATTOperand(OperandVector &Operands) {
2971 MCAsmParser &Parser = getParser();
2972 switch (getLexer().getKind()) {
2973 case AsmToken::Dollar: {
2974 // $42 or $ID -> immediate.
2975 SMLoc Start = Parser.getTok().getLoc(), End;
2976 Parser.Lex();
2977 const MCExpr *Val;
2978 // This is an immediate, so we should not parse a register. Do a precheck
2979 // for '%' to supercede intra-register parse errors.
2980 SMLoc L = Parser.getTok().getLoc();
2981 if (check(P: getLexer().is(K: AsmToken::Percent), Loc: L,
2982 Msg: "expected immediate expression") ||
2983 getParser().parseExpression(Res&: Val, EndLoc&: End) ||
2984 check(P: isa<X86MCExpr>(Val), Loc: L, Msg: "expected immediate expression"))
2985 return true;
2986 Operands.push_back(Elt: X86Operand::CreateImm(Val, StartLoc: Start, EndLoc: End));
2987 return false;
2988 }
2989 case AsmToken::LCurly: {
2990 SMLoc Start = Parser.getTok().getLoc();
2991 return ParseRoundingModeOp(Start, Operands);
2992 }
2993 default: {
2994 // This a memory operand or a register. We have some parsing complications
2995 // as a '(' may be part of an immediate expression or the addressing mode
2996 // block. This is complicated by the fact that an assembler-level variable
2997 // may refer either to a register or an immediate expression.
2998
2999 SMLoc Loc = Parser.getTok().getLoc(), EndLoc;
3000 const MCExpr *Expr = nullptr;
3001 MCRegister Reg;
3002 if (getLexer().isNot(K: AsmToken::LParen)) {
3003 // No '(' so this is either a displacement expression or a register.
3004 if (Parser.parseExpression(Res&: Expr, EndLoc))
3005 return true;
3006 if (auto *RE = dyn_cast<X86MCExpr>(Val: Expr)) {
3007 // Segment Register. Reset Expr and copy value to register.
3008 Expr = nullptr;
3009 Reg = RE->getReg();
3010
3011 // Check the register.
3012 if (Reg == X86::EIZ || Reg == X86::RIZ)
3013 return Error(
3014 L: Loc, Msg: "%eiz and %riz can only be used as index registers",
3015 Range: SMRange(Loc, EndLoc));
3016 if (Reg == X86::RIP)
3017 return Error(L: Loc, Msg: "%rip can only be used as a base register",
3018 Range: SMRange(Loc, EndLoc));
3019 // Return register that are not segment prefixes immediately.
3020 if (!Parser.parseOptionalToken(T: AsmToken::Colon)) {
3021 Operands.push_back(Elt: X86Operand::CreateReg(Reg, StartLoc: Loc, EndLoc));
3022 return false;
3023 }
3024 if (!getX86MCRegisterClass(RC: X86::SEGMENT_REGRegClassID).contains(Reg))
3025 return Error(L: Loc, Msg: "invalid segment register");
3026 // Accept a '*' absolute memory reference after the segment. Place it
3027 // before the full memory operand.
3028 if (getLexer().is(K: AsmToken::Star))
3029 Operands.push_back(Elt: X86Operand::CreateToken(Str: "*", Loc: consumeToken()));
3030 }
3031 }
3032 // This is a Memory operand.
3033 return ParseMemOperand(SegReg: Reg, Disp: Expr, StartLoc: Loc, EndLoc, Operands);
3034 }
3035 }
3036}
3037
3038// X86::COND_INVALID if not a recognized condition code or alternate mnemonic,
3039// otherwise the EFLAGS Condition Code enumerator.
3040X86::CondCode X86AsmParser::ParseConditionCode(StringRef CC) {
3041 return StringSwitch<X86::CondCode>(CC)
3042 .Case(S: "o", Value: X86::COND_O) // Overflow
3043 .Case(S: "no", Value: X86::COND_NO) // No Overflow
3044 .Cases(CaseStrings: {"b", "nae"}, Value: X86::COND_B) // Below/Neither Above nor Equal
3045 .Cases(CaseStrings: {"ae", "nb"}, Value: X86::COND_AE) // Above or Equal/Not Below
3046 .Cases(CaseStrings: {"e", "z"}, Value: X86::COND_E) // Equal/Zero
3047 .Cases(CaseStrings: {"ne", "nz"}, Value: X86::COND_NE) // Not Equal/Not Zero
3048 .Cases(CaseStrings: {"be", "na"}, Value: X86::COND_BE) // Below or Equal/Not Above
3049 .Cases(CaseStrings: {"a", "nbe"}, Value: X86::COND_A) // Above/Neither Below nor Equal
3050 .Case(S: "s", Value: X86::COND_S) // Sign
3051 .Case(S: "ns", Value: X86::COND_NS) // No Sign
3052 .Cases(CaseStrings: {"p", "pe"}, Value: X86::COND_P) // Parity/Parity Even
3053 .Cases(CaseStrings: {"np", "po"}, Value: X86::COND_NP) // No Parity/Parity Odd
3054 .Cases(CaseStrings: {"l", "nge"}, Value: X86::COND_L) // Less/Neither Greater nor Equal
3055 .Cases(CaseStrings: {"ge", "nl"}, Value: X86::COND_GE) // Greater or Equal/Not Less
3056 .Cases(CaseStrings: {"le", "ng"}, Value: X86::COND_LE) // Less or Equal/Not Greater
3057 .Cases(CaseStrings: {"g", "nle"}, Value: X86::COND_G) // Greater/Neither Less nor Equal
3058 .Default(Value: X86::COND_INVALID);
3059}
3060
3061// true on failure, false otherwise
3062// If no {z} mark was found - Parser doesn't advance
3063bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z, SMLoc StartLoc) {
3064 MCAsmParser &Parser = getParser();
3065 // Assuming we are just pass the '{' mark, quering the next token
3066 // Searched for {z}, but none was found. Return false, as no parsing error was
3067 // encountered
3068 if (!(getLexer().is(K: AsmToken::Identifier) &&
3069 (getLexer().getTok().getIdentifier() == "z")))
3070 return false;
3071 Parser.Lex(); // Eat z
3072 // Query and eat the '}' mark
3073 if (!getLexer().is(K: AsmToken::RCurly))
3074 return Error(L: getLexer().getLoc(), Msg: "Expected } at this point");
3075 Parser.Lex(); // Eat '}'
3076 // Assign Z with the {z} mark operand
3077 Z = X86Operand::CreateToken(Str: "{z}", Loc: StartLoc);
3078 return false;
3079}
3080
3081// true on failure, false otherwise
3082bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands) {
3083 MCAsmParser &Parser = getParser();
3084 if (getLexer().is(K: AsmToken::LCurly)) {
3085 // Eat "{" and mark the current place.
3086 const SMLoc consumedToken = consumeToken();
3087 // Distinguish {1to<NUM>} from {%k<NUM>}.
3088 if(getLexer().is(K: AsmToken::Integer)) {
3089 // Parse memory broadcasting ({1to<NUM>}).
3090 if (getLexer().getTok().getIntVal() != 1)
3091 return TokError(Msg: "Expected 1to<NUM> at this point");
3092 StringRef Prefix = getLexer().getTok().getString();
3093 Parser.Lex(); // Eat first token of 1to8
3094 if (!getLexer().is(K: AsmToken::Identifier))
3095 return TokError(Msg: "Expected 1to<NUM> at this point");
3096 // Recognize only reasonable suffixes.
3097 SmallVector<char, 5> BroadcastVector;
3098 StringRef BroadcastString = (Prefix + getLexer().getTok().getIdentifier())
3099 .toStringRef(Out&: BroadcastVector);
3100 if (!BroadcastString.starts_with(Prefix: "1to"))
3101 return TokError(Msg: "Expected 1to<NUM> at this point");
3102 const char *BroadcastPrimitive =
3103 StringSwitch<const char *>(BroadcastString)
3104 .Case(S: "1to2", Value: "{1to2}")
3105 .Case(S: "1to4", Value: "{1to4}")
3106 .Case(S: "1to8", Value: "{1to8}")
3107 .Case(S: "1to16", Value: "{1to16}")
3108 .Case(S: "1to32", Value: "{1to32}")
3109 .Default(Value: nullptr);
3110 if (!BroadcastPrimitive)
3111 return TokError(Msg: "Invalid memory broadcast primitive.");
3112 Parser.Lex(); // Eat trailing token of 1toN
3113 if (!getLexer().is(K: AsmToken::RCurly))
3114 return TokError(Msg: "Expected } at this point");
3115 Parser.Lex(); // Eat "}"
3116 Operands.push_back(Elt: X86Operand::CreateToken(Str: BroadcastPrimitive,
3117 Loc: consumedToken));
3118 // No AVX512 specific primitives can pass
3119 // after memory broadcasting, so return.
3120 return false;
3121 } else {
3122 // Parse either {k}{z}, {z}{k}, {k} or {z}
3123 // last one have no meaning, but GCC accepts it
3124 // Currently, we're just pass a '{' mark
3125 std::unique_ptr<X86Operand> Z;
3126 if (ParseZ(Z, StartLoc: consumedToken))
3127 return true;
3128 // Reaching here means that parsing of the allegadly '{z}' mark yielded
3129 // no errors.
3130 // Query for the need of further parsing for a {%k<NUM>} mark
3131 if (!Z || getLexer().is(K: AsmToken::LCurly)) {
3132 SMLoc StartLoc = Z ? consumeToken() : consumedToken;
3133 // Parse an op-mask register mark ({%k<NUM>}), which is now to be
3134 // expected
3135 MCRegister RegNo;
3136 SMLoc RegLoc;
3137 if (!parseRegister(Reg&: RegNo, StartLoc&: RegLoc, EndLoc&: StartLoc) &&
3138 getX86MCRegisterClass(RC: X86::VK1RegClassID).contains(Reg: RegNo)) {
3139 if (RegNo == X86::K0)
3140 return Error(L: RegLoc, Msg: "Register k0 can't be used as write mask");
3141 if (!getLexer().is(K: AsmToken::RCurly))
3142 return Error(L: getLexer().getLoc(), Msg: "Expected } at this point");
3143 Operands.push_back(Elt: X86Operand::CreateToken(Str: "{", Loc: StartLoc));
3144 Operands.push_back(
3145 Elt: X86Operand::CreateReg(Reg: RegNo, StartLoc, EndLoc: StartLoc));
3146 Operands.push_back(Elt: X86Operand::CreateToken(Str: "}", Loc: consumeToken()));
3147 } else
3148 return Error(L: getLexer().getLoc(),
3149 Msg: "Expected an op-mask register at this point");
3150 // {%k<NUM>} mark is found, inquire for {z}
3151 if (getLexer().is(K: AsmToken::LCurly) && !Z) {
3152 // Have we've found a parsing error, or found no (expected) {z} mark
3153 // - report an error
3154 if (ParseZ(Z, StartLoc: consumeToken()) || !Z)
3155 return Error(L: getLexer().getLoc(),
3156 Msg: "Expected a {z} mark at this point");
3157
3158 }
3159 // '{z}' on its own is meaningless, hence should be ignored.
3160 // on the contrary - have it been accompanied by a K register,
3161 // allow it.
3162 if (Z)
3163 Operands.push_back(Elt: std::move(Z));
3164 }
3165 }
3166 }
3167 return false;
3168}
3169
3170/// Returns false if okay and true if there was an overflow.
3171bool X86AsmParser::CheckDispOverflow(MCRegister BaseReg, MCRegister IndexReg,
3172 const MCExpr *Disp, SMLoc Loc) {
3173 // If the displacement is a constant, check overflows. For 64-bit addressing,
3174 // gas requires isInt<32> and otherwise reports an error. For others, gas
3175 // reports a warning and allows a wider range. E.g. gas allows
3176 // [-0xffffffff,0xffffffff] for 32-bit addressing (e.g. Linux kernel uses
3177 // `leal -__PAGE_OFFSET(%ecx),%esp` where __PAGE_OFFSET is 0xc0000000).
3178 if (BaseReg || IndexReg) {
3179 if (auto CE = dyn_cast<MCConstantExpr>(Val: Disp)) {
3180 auto Imm = CE->getValue();
3181 bool Is64 =
3182 getX86MCRegisterClass(RC: X86::GR64RegClassID).contains(Reg: BaseReg) ||
3183 getX86MCRegisterClass(RC: X86::GR64RegClassID).contains(Reg: IndexReg);
3184 bool Is16 = getX86MCRegisterClass(RC: X86::GR16RegClassID).contains(Reg: BaseReg);
3185 if (Is64) {
3186 if (!isInt<32>(x: Imm))
3187 return Error(L: Loc, Msg: "displacement " + Twine(Imm) +
3188 " is not within [-2147483648, 2147483647]");
3189 } else if (!Is16) {
3190 if (!isUInt<32>(x: Imm < 0 ? -uint64_t(Imm) : uint64_t(Imm))) {
3191 Warning(L: Loc, Msg: "displacement " + Twine(Imm) +
3192 " shortened to 32-bit signed " +
3193 Twine(static_cast<int32_t>(Imm)));
3194 }
3195 } else if (!isUInt<16>(x: Imm < 0 ? -uint64_t(Imm) : uint64_t(Imm))) {
3196 Warning(L: Loc, Msg: "displacement " + Twine(Imm) +
3197 " shortened to 16-bit signed " +
3198 Twine(static_cast<int16_t>(Imm)));
3199 }
3200 }
3201 }
3202 return false;
3203}
3204
3205/// ParseMemOperand: 'seg : disp(basereg, indexreg, scale)'. The '%ds:' prefix
3206/// has already been parsed if present. disp may be provided as well.
3207bool X86AsmParser::ParseMemOperand(MCRegister SegReg, const MCExpr *Disp,
3208 SMLoc StartLoc, SMLoc EndLoc,
3209 OperandVector &Operands) {
3210 MCAsmParser &Parser = getParser();
3211 SMLoc Loc;
3212 // Based on the initial passed values, we may be in any of these cases, we are
3213 // in one of these cases (with current position (*)):
3214
3215 // 1. seg : * disp (base-index-scale-expr)
3216 // 2. seg : *(disp) (base-index-scale-expr)
3217 // 3. seg : *(base-index-scale-expr)
3218 // 4. disp *(base-index-scale-expr)
3219 // 5. *(disp) (base-index-scale-expr)
3220 // 6. *(base-index-scale-expr)
3221 // 7. disp *
3222 // 8. *(disp)
3223
3224 // If we do not have an displacement yet, check if we're in cases 4 or 6 by
3225 // checking if the first object after the parenthesis is a register (or an
3226 // identifier referring to a register) and parse the displacement or default
3227 // to 0 as appropriate.
3228 auto isAtMemOperand = [this]() {
3229 if (this->getLexer().isNot(K: AsmToken::LParen))
3230 return false;
3231 AsmToken Buf[2];
3232 StringRef Id;
3233 auto TokCount = this->getLexer().peekTokens(Buf, ShouldSkipSpace: true);
3234 if (TokCount == 0)
3235 return false;
3236 switch (Buf[0].getKind()) {
3237 case AsmToken::Percent:
3238 case AsmToken::Comma:
3239 return true;
3240 // These lower cases are doing a peekIdentifier.
3241 case AsmToken::At:
3242 case AsmToken::Dollar:
3243 if ((TokCount > 1) &&
3244 (Buf[1].is(K: AsmToken::Identifier) || Buf[1].is(K: AsmToken::String)) &&
3245 (Buf[0].getLoc().getPointer() + 1 == Buf[1].getLoc().getPointer()))
3246 Id = StringRef(Buf[0].getLoc().getPointer(),
3247 Buf[1].getIdentifier().size() + 1);
3248 break;
3249 case AsmToken::Identifier:
3250 case AsmToken::String:
3251 Id = Buf[0].getIdentifier();
3252 break;
3253 default:
3254 return false;
3255 }
3256 // We have an ID. Check if it is bound to a register.
3257 if (!Id.empty()) {
3258 MCSymbol *Sym = this->getContext().getOrCreateSymbol(Name: Id);
3259 if (Sym->isVariable()) {
3260 auto V = Sym->getVariableValue();
3261 return isa<X86MCExpr>(Val: V);
3262 }
3263 }
3264 return false;
3265 };
3266
3267 if (!Disp) {
3268 // Parse immediate if we're not at a mem operand yet.
3269 if (!isAtMemOperand()) {
3270 if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(Res&: Disp, EndLoc))
3271 return true;
3272 assert(!isa<X86MCExpr>(Disp) && "Expected non-register here.");
3273 } else {
3274 // Disp is implicitly zero if we haven't parsed it yet.
3275 Disp = MCConstantExpr::create(Value: 0, Ctx&: Parser.getContext());
3276 }
3277 }
3278
3279 // We are now either at the end of the operand or at the '(' at the start of a
3280 // base-index-scale-expr.
3281
3282 if (!parseOptionalToken(T: AsmToken::LParen)) {
3283 if (!SegReg)
3284 Operands.push_back(
3285 Elt: X86Operand::CreateMem(ModeSize: getPointerWidth(), Disp, StartLoc, EndLoc));
3286 else
3287 Operands.push_back(Elt: X86Operand::CreateMem(ModeSize: getPointerWidth(), SegReg, Disp,
3288 BaseReg: 0, IndexReg: 0, Scale: 1, StartLoc, EndLoc));
3289 return false;
3290 }
3291
3292 // If we reached here, then eat the '(' and Process
3293 // the rest of the memory operand.
3294 MCRegister BaseReg, IndexReg;
3295 unsigned Scale = 1;
3296 SMLoc BaseLoc = getLexer().getLoc();
3297 const MCExpr *E;
3298 StringRef ErrMsg;
3299
3300 // Parse BaseReg if one is provided.
3301 if (getLexer().isNot(K: AsmToken::Comma) && getLexer().isNot(K: AsmToken::RParen)) {
3302 if (Parser.parseExpression(Res&: E, EndLoc) ||
3303 check(P: !isa<X86MCExpr>(Val: E), Loc: BaseLoc, Msg: "expected register here"))
3304 return true;
3305
3306 // Check the register.
3307 BaseReg = cast<X86MCExpr>(Val: E)->getReg();
3308 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ)
3309 return Error(L: BaseLoc, Msg: "eiz and riz can only be used as index registers",
3310 Range: SMRange(BaseLoc, EndLoc));
3311 }
3312
3313 if (parseOptionalToken(T: AsmToken::Comma)) {
3314 // Following the comma we should have either an index register, or a scale
3315 // value. We don't support the later form, but we want to parse it
3316 // correctly.
3317 //
3318 // Even though it would be completely consistent to support syntax like
3319 // "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
3320 if (getLexer().isNot(K: AsmToken::RParen)) {
3321 if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(Res&: E, EndLoc))
3322 return true;
3323
3324 if (!isa<X86MCExpr>(Val: E)) {
3325 // We've parsed an unexpected Scale Value instead of an index
3326 // register. Interpret it as an absolute.
3327 int64_t ScaleVal;
3328 if (!E->evaluateAsAbsolute(Res&: ScaleVal, Asm: getStreamer().getAssemblerPtr()))
3329 return Error(L: Loc, Msg: "expected absolute expression");
3330 if (ScaleVal != 1)
3331 Warning(L: Loc, Msg: "scale factor without index register is ignored");
3332 Scale = 1;
3333 } else { // IndexReg Found.
3334 IndexReg = cast<X86MCExpr>(Val: E)->getReg();
3335
3336 if (BaseReg == X86::RIP)
3337 return Error(L: Loc,
3338 Msg: "%rip as base register can not have an index register");
3339 if (IndexReg == X86::RIP)
3340 return Error(L: Loc, Msg: "%rip is not allowed as an index register");
3341
3342 if (parseOptionalToken(T: AsmToken::Comma)) {
3343 // Parse the scale amount:
3344 // ::= ',' [scale-expression]
3345
3346 // A scale amount without an index is ignored.
3347 if (getLexer().isNot(K: AsmToken::RParen)) {
3348 int64_t ScaleVal;
3349 if (Parser.parseTokenLoc(Loc) ||
3350 Parser.parseAbsoluteExpression(Res&: ScaleVal))
3351 return Error(L: Loc, Msg: "expected scale expression");
3352 Scale = (unsigned)ScaleVal;
3353 // Validate the scale amount.
3354 if (getX86MCRegisterClass(RC: X86::GR16RegClassID).contains(Reg: BaseReg) &&
3355 Scale != 1)
3356 return Error(L: Loc, Msg: "scale factor in 16-bit address must be 1");
3357 if (checkScale(Scale, ErrMsg))
3358 return Error(L: Loc, Msg: ErrMsg);
3359 }
3360 }
3361 }
3362 }
3363 }
3364
3365 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
3366 if (parseToken(T: AsmToken::RParen, Msg: "unexpected token in memory operand"))
3367 return true;
3368
3369 // This is to support otherwise illegal operand (%dx) found in various
3370 // unofficial manuals examples (e.g. "out[s]?[bwl]? %al, (%dx)") and must now
3371 // be supported. Mark such DX variants separately fix only in special cases.
3372 if (BaseReg == X86::DX && !IndexReg && Scale == 1 && !SegReg &&
3373 isa<MCConstantExpr>(Val: Disp) &&
3374 cast<MCConstantExpr>(Val: Disp)->getValue() == 0) {
3375 Operands.push_back(Elt: X86Operand::CreateDXReg(StartLoc: BaseLoc, EndLoc: BaseLoc));
3376 return false;
3377 }
3378
3379 if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, Is64BitMode: is64BitMode(),
3380 ErrMsg))
3381 return Error(L: BaseLoc, Msg: ErrMsg);
3382
3383 if (CheckDispOverflow(BaseReg, IndexReg, Disp, Loc: BaseLoc))
3384 return true;
3385
3386 if (SegReg || BaseReg || IndexReg)
3387 Operands.push_back(Elt: X86Operand::CreateMem(ModeSize: getPointerWidth(), SegReg, Disp,
3388 BaseReg, IndexReg, Scale, StartLoc,
3389 EndLoc));
3390 else
3391 Operands.push_back(
3392 Elt: X86Operand::CreateMem(ModeSize: getPointerWidth(), Disp, StartLoc, EndLoc));
3393 return false;
3394}
3395
3396// Parse either a standard primary expression or a register.
3397bool X86AsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
3398 MCAsmParser &Parser = getParser();
3399 // See if this is a register first.
3400 if (getTok().is(K: AsmToken::Percent) ||
3401 (isParsingIntelSyntax() && getTok().is(K: AsmToken::Identifier) &&
3402 MatchRegisterName(Name: Parser.getTok().getString()))) {
3403 SMLoc StartLoc = Parser.getTok().getLoc();
3404 MCRegister RegNo;
3405 if (parseRegister(Reg&: RegNo, StartLoc, EndLoc))
3406 return true;
3407 Res = X86MCExpr::create(Reg: RegNo, Ctx&: Parser.getContext());
3408 return false;
3409 }
3410 return Parser.parsePrimaryExpr(Res, EndLoc, TypeInfo: nullptr);
3411}
3412
3413bool X86AsmParser::parseInstruction(ParseInstructionInfo &Info, StringRef Name,
3414 SMLoc NameLoc, OperandVector &Operands) {
3415 MCAsmParser &Parser = getParser();
3416 InstInfo = &Info;
3417
3418 // Reset the forced VEX encoding.
3419 ForcedOpcodePrefix = OpcodePrefix_Default;
3420 ForcedDispEncoding = DispEncoding_Default;
3421 UseApxExtendedReg = false;
3422 ForcedNoFlag = false;
3423
3424 // Parse pseudo prefixes.
3425 while (true) {
3426 if (Name == "{") {
3427 if (getLexer().isNot(K: AsmToken::Identifier))
3428 return Error(L: Parser.getTok().getLoc(), Msg: "Unexpected token after '{'");
3429 std::string Prefix = Parser.getTok().getString().lower();
3430 Parser.Lex(); // Eat identifier.
3431 if (getLexer().isNot(K: AsmToken::RCurly))
3432 return Error(L: Parser.getTok().getLoc(), Msg: "Expected '}'");
3433 Parser.Lex(); // Eat curly.
3434
3435 if (Prefix == "rex")
3436 ForcedOpcodePrefix = OpcodePrefix_REX;
3437 else if (Prefix == "rex2")
3438 ForcedOpcodePrefix = OpcodePrefix_REX2;
3439 else if (Prefix == "vex")
3440 ForcedOpcodePrefix = OpcodePrefix_VEX;
3441 else if (Prefix == "vex2")
3442 ForcedOpcodePrefix = OpcodePrefix_VEX2;
3443 else if (Prefix == "vex3")
3444 ForcedOpcodePrefix = OpcodePrefix_VEX3;
3445 else if (Prefix == "evex")
3446 ForcedOpcodePrefix = OpcodePrefix_EVEX;
3447 else if (Prefix == "disp8")
3448 ForcedDispEncoding = DispEncoding_Disp8;
3449 else if (Prefix == "disp32")
3450 ForcedDispEncoding = DispEncoding_Disp32;
3451 else if (Prefix == "nf")
3452 ForcedNoFlag = true;
3453 else
3454 return Error(L: NameLoc, Msg: "unknown prefix");
3455
3456 NameLoc = Parser.getTok().getLoc();
3457 if (getLexer().is(K: AsmToken::LCurly)) {
3458 Parser.Lex();
3459 Name = "{";
3460 } else {
3461 if (getLexer().isNot(K: AsmToken::Identifier))
3462 return Error(L: Parser.getTok().getLoc(), Msg: "Expected identifier");
3463 // FIXME: The mnemonic won't match correctly if its not in lower case.
3464 Name = Parser.getTok().getString();
3465 Parser.Lex();
3466 }
3467 continue;
3468 }
3469 // Parse MASM style pseudo prefixes.
3470 if (isParsingMSInlineAsm()) {
3471 if (Name.equals_insensitive(RHS: "vex"))
3472 ForcedOpcodePrefix = OpcodePrefix_VEX;
3473 else if (Name.equals_insensitive(RHS: "vex2"))
3474 ForcedOpcodePrefix = OpcodePrefix_VEX2;
3475 else if (Name.equals_insensitive(RHS: "vex3"))
3476 ForcedOpcodePrefix = OpcodePrefix_VEX3;
3477 else if (Name.equals_insensitive(RHS: "evex"))
3478 ForcedOpcodePrefix = OpcodePrefix_EVEX;
3479
3480 if (ForcedOpcodePrefix != OpcodePrefix_Default) {
3481 if (getLexer().isNot(K: AsmToken::Identifier))
3482 return Error(L: Parser.getTok().getLoc(), Msg: "Expected identifier");
3483 // FIXME: The mnemonic won't match correctly if its not in lower case.
3484 Name = Parser.getTok().getString();
3485 NameLoc = Parser.getTok().getLoc();
3486 Parser.Lex();
3487 }
3488 }
3489 break;
3490 }
3491
3492 // Support the suffix syntax for overriding displacement size as well.
3493 if (Name.consume_back(Suffix: ".d32")) {
3494 ForcedDispEncoding = DispEncoding_Disp32;
3495 } else if (Name.consume_back(Suffix: ".d8")) {
3496 ForcedDispEncoding = DispEncoding_Disp8;
3497 }
3498
3499 StringRef PatchedName = Name;
3500
3501 // Hack to skip "short" following Jcc.
3502 if (isParsingIntelSyntax() &&
3503 (PatchedName == "jmp" || PatchedName == "jc" || PatchedName == "jnc" ||
3504 PatchedName == "jcxz" || PatchedName == "jecxz" ||
3505 (PatchedName.starts_with(Prefix: "j") &&
3506 ParseConditionCode(CC: PatchedName.substr(Start: 1)) != X86::COND_INVALID))) {
3507 StringRef NextTok = Parser.getTok().getString();
3508 if (Parser.isParsingMasm() ? NextTok.equals_insensitive(RHS: "short")
3509 : NextTok == "short") {
3510 SMLoc NameEndLoc =
3511 NameLoc.getFromPointer(Ptr: NameLoc.getPointer() + Name.size());
3512 // Eat the short keyword.
3513 Parser.Lex();
3514 // MS and GAS ignore the short keyword; they both determine the jmp type
3515 // based on the distance of the label. (NASM does emit different code with
3516 // and without "short," though.)
3517 InstInfo->AsmRewrites->emplace_back(Args: AOK_Skip, Args&: NameEndLoc,
3518 Args: NextTok.size() + 1);
3519 }
3520 }
3521
3522 // FIXME: Hack to recognize setneb as setne.
3523 if (PatchedName.starts_with(Prefix: "set") && PatchedName.ends_with(Suffix: "b") &&
3524 PatchedName != "setzub" && PatchedName != "setzunb" &&
3525 PatchedName != "setb" && PatchedName != "setnb")
3526 PatchedName = PatchedName.substr(Start: 0, N: Name.size()-1);
3527
3528 unsigned ComparisonPredicate = ~0U;
3529
3530 // FIXME: Hack to recognize cmp<comparison code>{sh,ss,sd,ph,ps,pd}.
3531 if ((PatchedName.starts_with(Prefix: "cmp") || PatchedName.starts_with(Prefix: "vcmp")) &&
3532 (PatchedName.ends_with(Suffix: "ss") || PatchedName.ends_with(Suffix: "sd") ||
3533 PatchedName.ends_with(Suffix: "sh") || PatchedName.ends_with(Suffix: "ph") ||
3534 PatchedName.ends_with(Suffix: "bf16") || PatchedName.ends_with(Suffix: "ps") ||
3535 PatchedName.ends_with(Suffix: "pd"))) {
3536 bool IsVCMP = PatchedName[0] == 'v';
3537 unsigned CCIdx = IsVCMP ? 4 : 3;
3538 unsigned suffixLength = PatchedName.ends_with(Suffix: "bf16") ? 5 : 2;
3539 unsigned CC = StringSwitch<unsigned>(
3540 PatchedName.slice(Start: CCIdx, End: PatchedName.size() - suffixLength))
3541 .Case(S: "eq", Value: 0x00)
3542 .Case(S: "eq_oq", Value: 0x00)
3543 .Case(S: "lt", Value: 0x01)
3544 .Case(S: "lt_os", Value: 0x01)
3545 .Case(S: "le", Value: 0x02)
3546 .Case(S: "le_os", Value: 0x02)
3547 .Case(S: "unord", Value: 0x03)
3548 .Case(S: "unord_q", Value: 0x03)
3549 .Case(S: "neq", Value: 0x04)
3550 .Case(S: "neq_uq", Value: 0x04)
3551 .Case(S: "nlt", Value: 0x05)
3552 .Case(S: "nlt_us", Value: 0x05)
3553 .Case(S: "nle", Value: 0x06)
3554 .Case(S: "nle_us", Value: 0x06)
3555 .Case(S: "ord", Value: 0x07)
3556 .Case(S: "ord_q", Value: 0x07)
3557 /* AVX only from here */
3558 .Case(S: "eq_uq", Value: 0x08)
3559 .Case(S: "nge", Value: 0x09)
3560 .Case(S: "nge_us", Value: 0x09)
3561 .Case(S: "ngt", Value: 0x0A)
3562 .Case(S: "ngt_us", Value: 0x0A)
3563 .Case(S: "false", Value: 0x0B)
3564 .Case(S: "false_oq", Value: 0x0B)
3565 .Case(S: "neq_oq", Value: 0x0C)
3566 .Case(S: "ge", Value: 0x0D)
3567 .Case(S: "ge_os", Value: 0x0D)
3568 .Case(S: "gt", Value: 0x0E)
3569 .Case(S: "gt_os", Value: 0x0E)
3570 .Case(S: "true", Value: 0x0F)
3571 .Case(S: "true_uq", Value: 0x0F)
3572 .Case(S: "eq_os", Value: 0x10)
3573 .Case(S: "lt_oq", Value: 0x11)
3574 .Case(S: "le_oq", Value: 0x12)
3575 .Case(S: "unord_s", Value: 0x13)
3576 .Case(S: "neq_us", Value: 0x14)
3577 .Case(S: "nlt_uq", Value: 0x15)
3578 .Case(S: "nle_uq", Value: 0x16)
3579 .Case(S: "ord_s", Value: 0x17)
3580 .Case(S: "eq_us", Value: 0x18)
3581 .Case(S: "nge_uq", Value: 0x19)
3582 .Case(S: "ngt_uq", Value: 0x1A)
3583 .Case(S: "false_os", Value: 0x1B)
3584 .Case(S: "neq_os", Value: 0x1C)
3585 .Case(S: "ge_oq", Value: 0x1D)
3586 .Case(S: "gt_oq", Value: 0x1E)
3587 .Case(S: "true_us", Value: 0x1F)
3588 .Default(Value: ~0U);
3589 if (CC != ~0U && (IsVCMP || CC < 8) &&
3590 (IsVCMP || PatchedName.back() != 'h')) {
3591 if (PatchedName.ends_with(Suffix: "ss"))
3592 PatchedName = IsVCMP ? "vcmpss" : "cmpss";
3593 else if (PatchedName.ends_with(Suffix: "sd"))
3594 PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
3595 else if (PatchedName.ends_with(Suffix: "ps"))
3596 PatchedName = IsVCMP ? "vcmpps" : "cmpps";
3597 else if (PatchedName.ends_with(Suffix: "pd"))
3598 PatchedName = IsVCMP ? "vcmppd" : "cmppd";
3599 else if (PatchedName.ends_with(Suffix: "sh"))
3600 PatchedName = "vcmpsh";
3601 else if (PatchedName.ends_with(Suffix: "ph"))
3602 PatchedName = "vcmpph";
3603 else if (PatchedName.ends_with(Suffix: "bf16"))
3604 PatchedName = "vcmpbf16";
3605 else
3606 llvm_unreachable("Unexpected suffix!");
3607
3608 ComparisonPredicate = CC;
3609 }
3610 }
3611
3612 // FIXME: Hack to recognize vpcmp<comparison code>{ub,uw,ud,uq,b,w,d,q}.
3613 if (PatchedName.starts_with(Prefix: "vpcmp") &&
3614 (PatchedName.back() == 'b' || PatchedName.back() == 'w' ||
3615 PatchedName.back() == 'd' || PatchedName.back() == 'q')) {
3616 unsigned SuffixSize = PatchedName.drop_back().back() == 'u' ? 2 : 1;
3617 unsigned CC = StringSwitch<unsigned>(
3618 PatchedName.slice(Start: 5, End: PatchedName.size() - SuffixSize))
3619 .Case(S: "eq", Value: 0x0) // Only allowed on unsigned. Checked below.
3620 .Case(S: "lt", Value: 0x1)
3621 .Case(S: "le", Value: 0x2)
3622 //.Case("false", 0x3) // Not a documented alias.
3623 .Case(S: "neq", Value: 0x4)
3624 .Case(S: "nlt", Value: 0x5)
3625 .Case(S: "nle", Value: 0x6)
3626 //.Case("true", 0x7) // Not a documented alias.
3627 .Default(Value: ~0U);
3628 if (CC != ~0U && (CC != 0 || SuffixSize == 2)) {
3629 switch (PatchedName.back()) {
3630 default: llvm_unreachable("Unexpected character!");
3631 case 'b': PatchedName = SuffixSize == 2 ? "vpcmpub" : "vpcmpb"; break;
3632 case 'w': PatchedName = SuffixSize == 2 ? "vpcmpuw" : "vpcmpw"; break;
3633 case 'd': PatchedName = SuffixSize == 2 ? "vpcmpud" : "vpcmpd"; break;
3634 case 'q': PatchedName = SuffixSize == 2 ? "vpcmpuq" : "vpcmpq"; break;
3635 }
3636 // Set up the immediate to push into the operands later.
3637 ComparisonPredicate = CC;
3638 }
3639 }
3640
3641 // FIXME: Hack to recognize vpcom<comparison code>{ub,uw,ud,uq,b,w,d,q}.
3642 if (PatchedName.starts_with(Prefix: "vpcom") &&
3643 (PatchedName.back() == 'b' || PatchedName.back() == 'w' ||
3644 PatchedName.back() == 'd' || PatchedName.back() == 'q')) {
3645 unsigned SuffixSize = PatchedName.drop_back().back() == 'u' ? 2 : 1;
3646 unsigned CC = StringSwitch<unsigned>(
3647 PatchedName.slice(Start: 5, End: PatchedName.size() - SuffixSize))
3648 .Case(S: "lt", Value: 0x0)
3649 .Case(S: "le", Value: 0x1)
3650 .Case(S: "gt", Value: 0x2)
3651 .Case(S: "ge", Value: 0x3)
3652 .Case(S: "eq", Value: 0x4)
3653 .Case(S: "neq", Value: 0x5)
3654 .Case(S: "false", Value: 0x6)
3655 .Case(S: "true", Value: 0x7)
3656 .Default(Value: ~0U);
3657 if (CC != ~0U) {
3658 switch (PatchedName.back()) {
3659 default: llvm_unreachable("Unexpected character!");
3660 case 'b': PatchedName = SuffixSize == 2 ? "vpcomub" : "vpcomb"; break;
3661 case 'w': PatchedName = SuffixSize == 2 ? "vpcomuw" : "vpcomw"; break;
3662 case 'd': PatchedName = SuffixSize == 2 ? "vpcomud" : "vpcomd"; break;
3663 case 'q': PatchedName = SuffixSize == 2 ? "vpcomuq" : "vpcomq"; break;
3664 }
3665 // Set up the immediate to push into the operands later.
3666 ComparisonPredicate = CC;
3667 }
3668 }
3669
3670 // Determine whether this is an instruction prefix.
3671 // FIXME:
3672 // Enhance prefixes integrity robustness. for example, following forms
3673 // are currently tolerated:
3674 // repz repnz <insn> ; GAS errors for the use of two similar prefixes
3675 // lock addq %rax, %rbx ; Destination operand must be of memory type
3676 // xacquire <insn> ; xacquire must be accompanied by 'lock'
3677 bool IsPrefix =
3678 StringSwitch<bool>(Name)
3679 .Cases(CaseStrings: {"cs", "ds", "es", "fs", "gs", "ss"}, Value: true)
3680 .Cases(CaseStrings: {"rex64", "data32", "data16", "addr32", "addr16"}, Value: true)
3681 .Cases(CaseStrings: {"xacquire", "xrelease"}, Value: true)
3682 .Cases(CaseStrings: {"acquire", "release"}, Value: isParsingIntelSyntax())
3683 .Default(Value: false);
3684
3685 auto isLockRepeatNtPrefix = [](StringRef N) {
3686 return StringSwitch<bool>(N)
3687 .Cases(CaseStrings: {"lock", "rep", "repe", "repz", "repne", "repnz", "notrack"},
3688 Value: true)
3689 .Default(Value: false);
3690 };
3691
3692 bool CurlyAsEndOfStatement = false;
3693
3694 unsigned Flags = X86::IP_NO_PREFIX;
3695 while (isLockRepeatNtPrefix(Name.lower())) {
3696 unsigned Prefix =
3697 StringSwitch<unsigned>(Name)
3698 .Case(S: "lock", Value: X86::IP_HAS_LOCK)
3699 .Cases(CaseStrings: {"rep", "repe", "repz"}, Value: X86::IP_HAS_REPEAT)
3700 .Cases(CaseStrings: {"repne", "repnz"}, Value: X86::IP_HAS_REPEAT_NE)
3701 .Case(S: "notrack", Value: X86::IP_HAS_NOTRACK)
3702 .Default(Value: X86::IP_NO_PREFIX); // Invalid prefix (impossible)
3703 Flags |= Prefix;
3704 if (getLexer().is(K: AsmToken::EndOfStatement)) {
3705 // We don't have real instr with the given prefix
3706 // let's use the prefix as the instr.
3707 // TODO: there could be several prefixes one after another
3708 Flags = X86::IP_NO_PREFIX;
3709 break;
3710 }
3711 // FIXME: The mnemonic won't match correctly if its not in lower case.
3712 Name = Parser.getTok().getString();
3713 Parser.Lex(); // eat the prefix
3714 // Hack: we could have something like "rep # some comment" or
3715 // "lock; cmpxchg16b $1" or "lock\0A\09incl" or "lock/incl"
3716 while (Name.starts_with(Prefix: ";") || Name.starts_with(Prefix: "\n") ||
3717 Name.starts_with(Prefix: "#") || Name.starts_with(Prefix: "\t") ||
3718 Name.starts_with(Prefix: "/")) {
3719 // FIXME: The mnemonic won't match correctly if its not in lower case.
3720 Name = Parser.getTok().getString();
3721 Parser.Lex(); // go to next prefix or instr
3722 }
3723 }
3724
3725 if (Flags)
3726 PatchedName = Name;
3727
3728 // Hacks to handle 'data16' and 'data32'
3729 if (PatchedName == "data16" && is16BitMode()) {
3730 return Error(L: NameLoc, Msg: "redundant data16 prefix");
3731 }
3732 if (PatchedName == "data32") {
3733 if (is32BitMode())
3734 return Error(L: NameLoc, Msg: "redundant data32 prefix");
3735 if (is64BitMode())
3736 return Error(L: NameLoc, Msg: "'data32' is not supported in 64-bit mode");
3737 // Hack to 'data16' for the table lookup.
3738 PatchedName = "data16";
3739
3740 if (getLexer().isNot(K: AsmToken::EndOfStatement)) {
3741 StringRef Next = Parser.getTok().getString();
3742 getLexer().Lex();
3743 // data32 effectively changes the instruction suffix.
3744 // TODO Generalize.
3745 if (Next == "callw")
3746 Next = "calll";
3747 if (Next == "ljmpw")
3748 Next = "ljmpl";
3749
3750 Name = Next;
3751 PatchedName = Name;
3752 ForcedDataPrefix = X86::Is32Bit;
3753 IsPrefix = false;
3754 }
3755 }
3756
3757 Operands.push_back(Elt: X86Operand::CreateToken(Str: PatchedName, Loc: NameLoc));
3758
3759 // Push the immediate if we extracted one from the mnemonic.
3760 if (ComparisonPredicate != ~0U && !isParsingIntelSyntax()) {
3761 const MCExpr *ImmOp = MCConstantExpr::create(Value: ComparisonPredicate,
3762 Ctx&: getParser().getContext());
3763 Operands.push_back(Elt: X86Operand::CreateImm(Val: ImmOp, StartLoc: NameLoc, EndLoc: NameLoc));
3764 }
3765
3766 // Parse condtional flags after mnemonic.
3767 if ((Name.starts_with(Prefix: "ccmp") || Name.starts_with(Prefix: "ctest")) &&
3768 parseCFlagsOp(Operands))
3769 return true;
3770
3771 // This does the actual operand parsing. Don't parse any more if we have a
3772 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
3773 // just want to parse the "lock" as the first instruction and the "incl" as
3774 // the next one.
3775 if (getLexer().isNot(K: AsmToken::EndOfStatement) && !IsPrefix) {
3776 // Parse '*' modifier.
3777 if (getLexer().is(K: AsmToken::Star))
3778 Operands.push_back(Elt: X86Operand::CreateToken(Str: "*", Loc: consumeToken()));
3779
3780 // Read the operands.
3781 while (true) {
3782 if (parseOperand(Operands, Name))
3783 return true;
3784 if (HandleAVX512Operand(Operands))
3785 return true;
3786
3787 // check for comma and eat it
3788 if (getLexer().is(K: AsmToken::Comma))
3789 Parser.Lex();
3790 else
3791 break;
3792 }
3793
3794 // In MS inline asm curly braces mark the beginning/end of a block,
3795 // therefore they should be interepreted as end of statement
3796 CurlyAsEndOfStatement =
3797 isParsingIntelSyntax() && isParsingMSInlineAsm() &&
3798 (getLexer().is(K: AsmToken::LCurly) || getLexer().is(K: AsmToken::RCurly));
3799 if (getLexer().isNot(K: AsmToken::EndOfStatement) && !CurlyAsEndOfStatement)
3800 return TokError(Msg: "unexpected token in argument list");
3801 }
3802
3803 // Push the immediate if we extracted one from the mnemonic.
3804 if (ComparisonPredicate != ~0U && isParsingIntelSyntax()) {
3805 const MCExpr *ImmOp = MCConstantExpr::create(Value: ComparisonPredicate,
3806 Ctx&: getParser().getContext());
3807 Operands.push_back(Elt: X86Operand::CreateImm(Val: ImmOp, StartLoc: NameLoc, EndLoc: NameLoc));
3808 }
3809
3810 // Consume the EndOfStatement or the prefix separator Slash
3811 if (getLexer().is(K: AsmToken::EndOfStatement) ||
3812 (IsPrefix && getLexer().is(K: AsmToken::Slash)))
3813 Parser.Lex();
3814 else if (CurlyAsEndOfStatement)
3815 // Add an actual EndOfStatement before the curly brace
3816 Info.AsmRewrites->emplace_back(Args: AOK_EndOfStatement,
3817 Args: getLexer().getTok().getLoc(), Args: 0);
3818
3819 // This is for gas compatibility and cannot be done in td.
3820 // Adding "p" for some floating point with no argument.
3821 // For example: fsub --> fsubp
3822 bool IsFp =
3823 Name == "fsub" || Name == "fdiv" || Name == "fsubr" || Name == "fdivr";
3824 if (IsFp && Operands.size() == 1) {
3825 const char *Repl = StringSwitch<const char *>(Name)
3826 .Case(S: "fsub", Value: "fsubp")
3827 .Case(S: "fdiv", Value: "fdivp")
3828 .Case(S: "fsubr", Value: "fsubrp")
3829 .Case(S: "fdivr", Value: "fdivrp");
3830 static_cast<X86Operand &>(*Operands[0]).setTokenValue(Repl);
3831 }
3832
3833 if ((Name == "mov" || Name == "movw" || Name == "movl") &&
3834 (Operands.size() == 3)) {
3835 X86Operand &Op1 = (X86Operand &)*Operands[1];
3836 X86Operand &Op2 = (X86Operand &)*Operands[2];
3837 SMLoc Loc = Op1.getEndLoc();
3838 // Moving a 32 or 16 bit value into a segment register has the same
3839 // behavior. Modify such instructions to always take shorter form.
3840 if (Op1.isReg() && Op2.isReg() &&
3841 getX86MCRegisterClass(RC: X86::SEGMENT_REGRegClassID)
3842 .contains(Reg: Op2.getReg()) &&
3843 (getX86MCRegisterClass(RC: X86::GR16RegClassID).contains(Reg: Op1.getReg()) ||
3844 getX86MCRegisterClass(RC: X86::GR32RegClassID).contains(Reg: Op1.getReg()))) {
3845 // Change instruction name to match new instruction.
3846 if (Name != "mov" && Name[3] == (is16BitMode() ? 'l' : 'w')) {
3847 Name = is16BitMode() ? "movw" : "movl";
3848 Operands[0] = X86Operand::CreateToken(Str: Name, Loc: NameLoc);
3849 }
3850 // Select the correct equivalent 16-/32-bit source register.
3851 MCRegister Reg =
3852 getX86SubSuperRegister(Reg: Op1.getReg(), Size: is16BitMode() ? 16 : 32);
3853 Operands[1] = X86Operand::CreateReg(Reg, StartLoc: Loc, EndLoc: Loc);
3854 }
3855 }
3856
3857 // This is a terrible hack to handle "out[s]?[bwl]? %al, (%dx)" ->
3858 // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
3859 // documented form in various unofficial manuals, so a lot of code uses it.
3860 if ((Name == "outb" || Name == "outsb" || Name == "outw" || Name == "outsw" ||
3861 Name == "outl" || Name == "outsl" || Name == "out" || Name == "outs") &&
3862 Operands.size() == 3) {
3863 X86Operand &Op = (X86Operand &)*Operands.back();
3864 if (Op.isDXReg())
3865 Operands.back() = X86Operand::CreateReg(Reg: X86::DX, StartLoc: Op.getStartLoc(),
3866 EndLoc: Op.getEndLoc());
3867 }
3868 // Same hack for "in[s]?[bwl]? (%dx), %al" -> "inb %dx, %al".
3869 if ((Name == "inb" || Name == "insb" || Name == "inw" || Name == "insw" ||
3870 Name == "inl" || Name == "insl" || Name == "in" || Name == "ins") &&
3871 Operands.size() == 3) {
3872 X86Operand &Op = (X86Operand &)*Operands[1];
3873 if (Op.isDXReg())
3874 Operands[1] = X86Operand::CreateReg(Reg: X86::DX, StartLoc: Op.getStartLoc(),
3875 EndLoc: Op.getEndLoc());
3876 }
3877
3878 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 2> TmpOperands;
3879 bool HadVerifyError = false;
3880
3881 // Append default arguments to "ins[bwld]"
3882 if (Name.starts_with(Prefix: "ins") &&
3883 (Operands.size() == 1 || Operands.size() == 3) &&
3884 (Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd" ||
3885 Name == "ins")) {
3886
3887 AddDefaultSrcDestOperands(Operands&: TmpOperands,
3888 Src: X86Operand::CreateReg(Reg: X86::DX, StartLoc: NameLoc, EndLoc: NameLoc),
3889 Dst: DefaultMemDIOperand(Loc: NameLoc));
3890 HadVerifyError = VerifyAndAdjustOperands(OrigOperands&: Operands, FinalOperands&: TmpOperands);
3891 }
3892
3893 // Append default arguments to "outs[bwld]"
3894 if (Name.starts_with(Prefix: "outs") &&
3895 (Operands.size() == 1 || Operands.size() == 3) &&
3896 (Name == "outsb" || Name == "outsw" || Name == "outsl" ||
3897 Name == "outsd" || Name == "outs")) {
3898 AddDefaultSrcDestOperands(Operands&: TmpOperands, Src: DefaultMemSIOperand(Loc: NameLoc),
3899 Dst: X86Operand::CreateReg(Reg: X86::DX, StartLoc: NameLoc, EndLoc: NameLoc));
3900 HadVerifyError = VerifyAndAdjustOperands(OrigOperands&: Operands, FinalOperands&: TmpOperands);
3901 }
3902
3903 // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
3904 // values of $SIREG according to the mode. It would be nice if this
3905 // could be achieved with InstAlias in the tables.
3906 if (Name.starts_with(Prefix: "lods") &&
3907 (Operands.size() == 1 || Operands.size() == 2) &&
3908 (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
3909 Name == "lodsl" || Name == "lodsd" || Name == "lodsq")) {
3910 TmpOperands.push_back(Elt: DefaultMemSIOperand(Loc: NameLoc));
3911 HadVerifyError = VerifyAndAdjustOperands(OrigOperands&: Operands, FinalOperands&: TmpOperands);
3912 }
3913
3914 // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
3915 // values of $DIREG according to the mode. It would be nice if this
3916 // could be achieved with InstAlias in the tables.
3917 if (Name.starts_with(Prefix: "stos") &&
3918 (Operands.size() == 1 || Operands.size() == 2) &&
3919 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
3920 Name == "stosl" || Name == "stosd" || Name == "stosq")) {
3921 TmpOperands.push_back(Elt: DefaultMemDIOperand(Loc: NameLoc));
3922 HadVerifyError = VerifyAndAdjustOperands(OrigOperands&: Operands, FinalOperands&: TmpOperands);
3923 }
3924
3925 // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
3926 // values of $DIREG according to the mode. It would be nice if this
3927 // could be achieved with InstAlias in the tables.
3928 if (Name.starts_with(Prefix: "scas") &&
3929 (Operands.size() == 1 || Operands.size() == 2) &&
3930 (Name == "scas" || Name == "scasb" || Name == "scasw" ||
3931 Name == "scasl" || Name == "scasd" || Name == "scasq")) {
3932 TmpOperands.push_back(Elt: DefaultMemDIOperand(Loc: NameLoc));
3933 HadVerifyError = VerifyAndAdjustOperands(OrigOperands&: Operands, FinalOperands&: TmpOperands);
3934 }
3935
3936 // Add default SI and DI operands to "cmps[bwlq]".
3937 if (Name.starts_with(Prefix: "cmps") &&
3938 (Operands.size() == 1 || Operands.size() == 3) &&
3939 (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||
3940 Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {
3941 AddDefaultSrcDestOperands(Operands&: TmpOperands, Src: DefaultMemDIOperand(Loc: NameLoc),
3942 Dst: DefaultMemSIOperand(Loc: NameLoc));
3943 HadVerifyError = VerifyAndAdjustOperands(OrigOperands&: Operands, FinalOperands&: TmpOperands);
3944 }
3945
3946 // Add default SI and DI operands to "movs[bwlq]".
3947 if (((Name.starts_with(Prefix: "movs") &&
3948 (Name == "movs" || Name == "movsb" || Name == "movsw" ||
3949 Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
3950 (Name.starts_with(Prefix: "smov") &&
3951 (Name == "smov" || Name == "smovb" || Name == "smovw" ||
3952 Name == "smovl" || Name == "smovd" || Name == "smovq"))) &&
3953 (Operands.size() == 1 || Operands.size() == 3)) {
3954 if (Name == "movsd" && Operands.size() == 1 && !isParsingIntelSyntax())
3955 Operands.back() = X86Operand::CreateToken(Str: "movsl", Loc: NameLoc);
3956 AddDefaultSrcDestOperands(Operands&: TmpOperands, Src: DefaultMemSIOperand(Loc: NameLoc),
3957 Dst: DefaultMemDIOperand(Loc: NameLoc));
3958 HadVerifyError = VerifyAndAdjustOperands(OrigOperands&: Operands, FinalOperands&: TmpOperands);
3959 }
3960
3961 // Check if we encountered an error for one the string insturctions
3962 if (HadVerifyError) {
3963 return HadVerifyError;
3964 }
3965
3966 // Transforms "xlat mem8" into "xlatb"
3967 if ((Name == "xlat" || Name == "xlatb") && Operands.size() == 2) {
3968 X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
3969 if (Op1.isMem8()) {
3970 Warning(L: Op1.getStartLoc(), Msg: "memory operand is only for determining the "
3971 "size, (R|E)BX will be used for the location");
3972 Operands.pop_back();
3973 static_cast<X86Operand &>(*Operands[0]).setTokenValue("xlatb");
3974 }
3975 }
3976
3977 if (Flags)
3978 Operands.push_back(Elt: X86Operand::CreatePrefix(Prefixes: Flags, StartLoc: NameLoc, EndLoc: NameLoc));
3979 return false;
3980}
3981
3982static bool convertSSEToAVX(MCInst &Inst) {
3983 ArrayRef<X86TableEntry> Table{X86SSE2AVXTable};
3984 unsigned Opcode = Inst.getOpcode();
3985 const auto I = llvm::lower_bound(Range&: Table, Value&: Opcode);
3986 if (I == Table.end() || I->OldOpc != Opcode)
3987 return false;
3988
3989 Inst.setOpcode(I->NewOpc);
3990 // AVX variant of BLENDVPD/BLENDVPS/PBLENDVB instructions has more
3991 // operand compare to SSE variant, which is added below
3992 if (X86::isBLENDVPD(Opcode) || X86::isBLENDVPS(Opcode) ||
3993 X86::isPBLENDVB(Opcode))
3994 Inst.addOperand(Op: Inst.getOperand(i: 2));
3995
3996 return true;
3997}
3998
3999bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
4000 if (getTargetOptions().X86Sse2Avx && convertSSEToAVX(Inst))
4001 return true;
4002
4003 if (ForcedOpcodePrefix != OpcodePrefix_VEX3 &&
4004 X86::optimizeInstFromVEX3ToVEX2(MI&: Inst, Desc: MII.get(Opcode: Inst.getOpcode())))
4005 return true;
4006
4007 if (X86::optimizeShiftRotateWithImmediateOne(MI&: Inst))
4008 return true;
4009
4010 auto replaceWithCCMPCTEST = [&](unsigned Opcode) -> bool {
4011 if (ForcedOpcodePrefix == OpcodePrefix_EVEX) {
4012 Inst.setFlags(~(X86::IP_USE_EVEX)&Inst.getFlags());
4013 Inst.setOpcode(Opcode);
4014 Inst.addOperand(Op: MCOperand::createImm(Val: 0));
4015 Inst.addOperand(Op: MCOperand::createImm(Val: 10));
4016 return true;
4017 }
4018 return false;
4019 };
4020
4021 switch (Inst.getOpcode()) {
4022 default: return false;
4023 case X86::JMP_1:
4024 // {disp32} forces a larger displacement as if the instruction was relaxed.
4025 // NOTE: 16-bit mode uses 16-bit displacement even though it says {disp32}.
4026 // This matches GNU assembler.
4027 if (ForcedDispEncoding == DispEncoding_Disp32) {
4028 Inst.setOpcode(is16BitMode() ? X86::JMP_2 : X86::JMP_4);
4029 return true;
4030 }
4031
4032 return false;
4033 case X86::JCC_1:
4034 // {disp32} forces a larger displacement as if the instruction was relaxed.
4035 // NOTE: 16-bit mode uses 16-bit displacement even though it says {disp32}.
4036 // This matches GNU assembler.
4037 if (ForcedDispEncoding == DispEncoding_Disp32) {
4038 Inst.setOpcode(is16BitMode() ? X86::JCC_2 : X86::JCC_4);
4039 return true;
4040 }
4041
4042 return false;
4043 case X86::INT: {
4044 // Transforms "int $3" into "int3" as a size optimization.
4045 // We can't write this as an InstAlias.
4046 if (!Inst.getOperand(i: 0).isImm() || Inst.getOperand(i: 0).getImm() != 3)
4047 return false;
4048 Inst.clear();
4049 Inst.setOpcode(X86::INT3);
4050 return true;
4051 }
4052 // `{evex} cmp <>, <>` is alias of `ccmpt {dfv=} <>, <>`, and
4053 // `{evex} test <>, <>` is alias of `ctest {dfv=} <>, <>`
4054#define FROM_TO(FROM, TO) \
4055 case X86::FROM: \
4056 return replaceWithCCMPCTEST(X86::TO);
4057 FROM_TO(CMP64rr, CCMP64rr)
4058 FROM_TO(CMP64mi32, CCMP64mi32)
4059 FROM_TO(CMP64mi8, CCMP64mi8)
4060 FROM_TO(CMP64mr, CCMP64mr)
4061 FROM_TO(CMP64ri32, CCMP64ri32)
4062 FROM_TO(CMP64ri8, CCMP64ri8)
4063 FROM_TO(CMP64rm, CCMP64rm)
4064
4065 FROM_TO(CMP32rr, CCMP32rr)
4066 FROM_TO(CMP32mi, CCMP32mi)
4067 FROM_TO(CMP32mi8, CCMP32mi8)
4068 FROM_TO(CMP32mr, CCMP32mr)
4069 FROM_TO(CMP32ri, CCMP32ri)
4070 FROM_TO(CMP32ri8, CCMP32ri8)
4071 FROM_TO(CMP32rm, CCMP32rm)
4072
4073 FROM_TO(CMP16rr, CCMP16rr)
4074 FROM_TO(CMP16mi, CCMP16mi)
4075 FROM_TO(CMP16mi8, CCMP16mi8)
4076 FROM_TO(CMP16mr, CCMP16mr)
4077 FROM_TO(CMP16ri, CCMP16ri)
4078 FROM_TO(CMP16ri8, CCMP16ri8)
4079 FROM_TO(CMP16rm, CCMP16rm)
4080
4081 FROM_TO(CMP8rr, CCMP8rr)
4082 FROM_TO(CMP8mi, CCMP8mi)
4083 FROM_TO(CMP8mr, CCMP8mr)
4084 FROM_TO(CMP8ri, CCMP8ri)
4085 FROM_TO(CMP8rm, CCMP8rm)
4086
4087 FROM_TO(TEST64rr, CTEST64rr)
4088 FROM_TO(TEST64mi32, CTEST64mi32)
4089 FROM_TO(TEST64mr, CTEST64mr)
4090 FROM_TO(TEST64ri32, CTEST64ri32)
4091
4092 FROM_TO(TEST32rr, CTEST32rr)
4093 FROM_TO(TEST32mi, CTEST32mi)
4094 FROM_TO(TEST32mr, CTEST32mr)
4095 FROM_TO(TEST32ri, CTEST32ri)
4096
4097 FROM_TO(TEST16rr, CTEST16rr)
4098 FROM_TO(TEST16mi, CTEST16mi)
4099 FROM_TO(TEST16mr, CTEST16mr)
4100 FROM_TO(TEST16ri, CTEST16ri)
4101
4102 FROM_TO(TEST8rr, CTEST8rr)
4103 FROM_TO(TEST8mi, CTEST8mi)
4104 FROM_TO(TEST8mr, CTEST8mr)
4105 FROM_TO(TEST8ri, CTEST8ri)
4106#undef FROM_TO
4107 }
4108}
4109
4110bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
4111 using namespace X86;
4112 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
4113 unsigned Opcode = Inst.getOpcode();
4114 uint64_t TSFlags = MII.get(Opcode).TSFlags;
4115 if (isVFCMADDCPH(Opcode) || isVFCMADDCSH(Opcode) || isVFMADDCPH(Opcode) ||
4116 isVFMADDCSH(Opcode)) {
4117 MCRegister Dest = Inst.getOperand(i: 0).getReg();
4118 for (unsigned i = 2; i < Inst.getNumOperands(); i++)
4119 if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg())
4120 return Warning(L: Ops[0]->getStartLoc(), Msg: "Destination register should be "
4121 "distinct from source registers");
4122 } else if (isVFCMULCPH(Opcode) || isVFCMULCSH(Opcode) || isVFMULCPH(Opcode) ||
4123 isVFMULCSH(Opcode)) {
4124 MCRegister Dest = Inst.getOperand(i: 0).getReg();
4125 // The mask variants have different operand list. Scan from the third
4126 // operand to avoid emitting incorrect warning.
4127 // VFMULCPHZrr Dest, Src1, Src2
4128 // VFMULCPHZrrk Dest, Dest, Mask, Src1, Src2
4129 // VFMULCPHZrrkz Dest, Mask, Src1, Src2
4130 for (unsigned i = ((TSFlags & X86II::EVEX_K) ? 2 : 1);
4131 i < Inst.getNumOperands(); i++)
4132 if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg())
4133 return Warning(L: Ops[0]->getStartLoc(), Msg: "Destination register should be "
4134 "distinct from source registers");
4135 } else if (isV4FMADDPS(Opcode) || isV4FMADDSS(Opcode) ||
4136 isV4FNMADDPS(Opcode) || isV4FNMADDSS(Opcode) ||
4137 isVP4DPWSSDS(Opcode) || isVP4DPWSSD(Opcode)) {
4138 MCRegister Src2 =
4139 Inst.getOperand(i: Inst.getNumOperands() - X86::AddrNumOperands - 1)
4140 .getReg();
4141 unsigned Src2Enc = MRI->getEncodingValue(Reg: Src2);
4142 if (Src2Enc % 4 != 0) {
4143 StringRef RegName = X86IntelInstPrinter::getRegisterName(Reg: Src2);
4144 unsigned GroupStart = (Src2Enc / 4) * 4;
4145 unsigned GroupEnd = GroupStart + 3;
4146 return Warning(L: Ops[0]->getStartLoc(),
4147 Msg: "source register '" + RegName + "' implicitly denotes '" +
4148 RegName.take_front(N: 3) + Twine(GroupStart) + "' to '" +
4149 RegName.take_front(N: 3) + Twine(GroupEnd) +
4150 "' source group");
4151 }
4152 } else if (isVGATHERDPD(Opcode) || isVGATHERDPS(Opcode) ||
4153 isVGATHERQPD(Opcode) || isVGATHERQPS(Opcode) ||
4154 isVPGATHERDD(Opcode) || isVPGATHERDQ(Opcode) ||
4155 isVPGATHERQD(Opcode) || isVPGATHERQQ(Opcode)) {
4156 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
4157 if (HasEVEX) {
4158 unsigned Dest = MRI->getEncodingValue(Reg: Inst.getOperand(i: 0).getReg());
4159 unsigned Index = MRI->getEncodingValue(
4160 Reg: Inst.getOperand(i: 4 + X86::AddrIndexReg).getReg());
4161 if (Dest == Index)
4162 return Warning(L: Ops[0]->getStartLoc(), Msg: "index and destination registers "
4163 "should be distinct");
4164 } else {
4165 unsigned Dest = MRI->getEncodingValue(Reg: Inst.getOperand(i: 0).getReg());
4166 unsigned Mask = MRI->getEncodingValue(Reg: Inst.getOperand(i: 1).getReg());
4167 unsigned Index = MRI->getEncodingValue(
4168 Reg: Inst.getOperand(i: 3 + X86::AddrIndexReg).getReg());
4169 if (Dest == Mask || Dest == Index || Mask == Index)
4170 return Warning(L: Ops[0]->getStartLoc(), Msg: "mask, index, and destination "
4171 "registers should be distinct");
4172 }
4173 } else if (isTCMMIMFP16PS(Opcode) || isTCMMRLFP16PS(Opcode) ||
4174 isTDPBF16PS(Opcode) || isTDPFP16PS(Opcode) || isTDPBSSD(Opcode) ||
4175 isTDPBSUD(Opcode) || isTDPBUSD(Opcode) || isTDPBUUD(Opcode)) {
4176 MCRegister SrcDest = Inst.getOperand(i: 0).getReg();
4177 MCRegister Src1 = Inst.getOperand(i: 2).getReg();
4178 MCRegister Src2 = Inst.getOperand(i: 3).getReg();
4179 if (SrcDest == Src1 || SrcDest == Src2 || Src1 == Src2)
4180 return Error(L: Ops[0]->getStartLoc(), Msg: "all tmm registers must be distinct");
4181 }
4182
4183 // High 8-bit regs (AH/BH/CH/DH) are incompatible with encodings that imply
4184 // extended prefixes:
4185 // * Legacy path that would emit a REX (e.g. uses r8..r15 or sil/dil/bpl/spl)
4186 // * EVEX
4187 // * REX2
4188 // VEX/XOP don't use REX; they are excluded from the legacy check.
4189 const unsigned Enc = TSFlags & X86II::EncodingMask;
4190 if (Enc != X86II::VEX && Enc != X86II::XOP) {
4191 MCRegister HReg;
4192 bool UsesRex = TSFlags & X86II::REX_W;
4193 unsigned NumOps = Inst.getNumOperands();
4194 for (unsigned i = 0; i != NumOps; ++i) {
4195 const MCOperand &MO = Inst.getOperand(i);
4196 if (!MO.isReg())
4197 continue;
4198 MCRegister Reg = MO.getReg();
4199 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
4200 HReg = Reg;
4201 if (X86II::isX86_64NonExtLowByteReg(Reg) ||
4202 X86II::isX86_64ExtendedReg(Reg))
4203 UsesRex = true;
4204 }
4205
4206 if (HReg &&
4207 (Enc == X86II::EVEX || ForcedOpcodePrefix == OpcodePrefix_REX2 ||
4208 ForcedOpcodePrefix == OpcodePrefix_REX || UsesRex)) {
4209 StringRef RegName = X86IntelInstPrinter::getRegisterName(Reg: HReg);
4210 return Error(L: Ops[0]->getStartLoc(),
4211 Msg: "can't encode '" + RegName.str() +
4212 "' in an instruction requiring EVEX/REX2/REX prefix");
4213 }
4214 }
4215
4216 if ((Opcode == X86::PREFETCHIT0 || Opcode == X86::PREFETCHIT1)) {
4217 const MCOperand &MO = Inst.getOperand(i: X86::AddrBaseReg);
4218 if (!MO.isReg() || MO.getReg() != X86::RIP)
4219 return Warning(
4220 L: Ops[0]->getStartLoc(),
4221 Msg: Twine((Inst.getOpcode() == X86::PREFETCHIT0 ? "'prefetchit0'"
4222 : "'prefetchit1'")) +
4223 " only supports RIP-relative address");
4224 }
4225 return false;
4226}
4227
4228void X86AsmParser::emitWarningForSpecialLVIInstruction(SMLoc Loc) {
4229 Warning(L: Loc, Msg: "Instruction may be vulnerable to LVI and "
4230 "requires manual mitigation");
4231 Note(L: SMLoc(), Msg: "See https://software.intel.com/"
4232 "security-software-guidance/insights/"
4233 "deep-dive-load-value-injection#specialinstructions"
4234 " for more information");
4235}
4236
4237/// RET instructions and also instructions that indirect calls/jumps from memory
4238/// combine a load and a branch within a single instruction. To mitigate these
4239/// instructions against LVI, they must be decomposed into separate load and
4240/// branch instructions, with an LFENCE in between. For more details, see:
4241/// - X86LoadValueInjectionRetHardening.cpp
4242/// - X86LoadValueInjectionIndirectThunks.cpp
4243/// - https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection
4244///
4245/// Returns `true` if a mitigation was applied or warning was emitted.
4246void X86AsmParser::applyLVICFIMitigation(MCInst &Inst, MCStreamer &Out) {
4247 // Information on control-flow instructions that require manual mitigation can
4248 // be found here:
4249 // https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions
4250 switch (Inst.getOpcode()) {
4251 case X86::RET16:
4252 case X86::RET32:
4253 case X86::RET64:
4254 case X86::RETI16:
4255 case X86::RETI32:
4256 case X86::RETI64: {
4257 MCInst ShlInst, FenceInst;
4258 bool Parse32 = is32BitMode() || Code16GCC;
4259 MCRegister Basereg =
4260 is64BitMode() ? X86::RSP : (Parse32 ? X86::ESP : X86::SP);
4261 const MCExpr *Disp = MCConstantExpr::create(Value: 0, Ctx&: getContext());
4262 auto ShlMemOp = X86Operand::CreateMem(ModeSize: getPointerWidth(), /*SegReg=*/0, Disp,
4263 /*BaseReg=*/Basereg, /*IndexReg=*/0,
4264 /*Scale=*/1, StartLoc: SMLoc{}, EndLoc: SMLoc{}, Size: 0);
4265 ShlInst.setOpcode(X86::SHL64mi);
4266 ShlMemOp->addMemOperands(Inst&: ShlInst, N: 5);
4267 ShlInst.addOperand(Op: MCOperand::createImm(Val: 0));
4268 FenceInst.setOpcode(X86::LFENCE);
4269 Out.emitInstruction(Inst: ShlInst, STI: getSTI());
4270 Out.emitInstruction(Inst: FenceInst, STI: getSTI());
4271 return;
4272 }
4273 case X86::JMP16m:
4274 case X86::JMP32m:
4275 case X86::JMP64m:
4276 case X86::CALL16m:
4277 case X86::CALL32m:
4278 case X86::CALL64m:
4279 emitWarningForSpecialLVIInstruction(Loc: Inst.getLoc());
4280 return;
4281 }
4282}
4283
4284/// To mitigate LVI, every instruction that performs a load can be followed by
4285/// an LFENCE instruction to squash any potential mis-speculation. There are
4286/// some instructions that require additional considerations, and may requre
4287/// manual mitigation. For more details, see:
4288/// https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection
4289///
4290/// Returns `true` if a mitigation was applied or warning was emitted.
4291void X86AsmParser::applyLVILoadHardeningMitigation(MCInst &Inst,
4292 MCStreamer &Out) {
4293 auto Opcode = Inst.getOpcode();
4294 auto Flags = Inst.getFlags();
4295 if ((Flags & X86::IP_HAS_REPEAT) || (Flags & X86::IP_HAS_REPEAT_NE)) {
4296 // Information on REP string instructions that require manual mitigation can
4297 // be found here:
4298 // https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions
4299 switch (Opcode) {
4300 case X86::CMPSB:
4301 case X86::CMPSW:
4302 case X86::CMPSL:
4303 case X86::CMPSQ:
4304 case X86::SCASB:
4305 case X86::SCASW:
4306 case X86::SCASL:
4307 case X86::SCASQ:
4308 emitWarningForSpecialLVIInstruction(Loc: Inst.getLoc());
4309 return;
4310 }
4311 } else if (Opcode == X86::REP_PREFIX || Opcode == X86::REPNE_PREFIX) {
4312 // If a REP instruction is found on its own line, it may or may not be
4313 // followed by a vulnerable instruction. Emit a warning just in case.
4314 emitWarningForSpecialLVIInstruction(Loc: Inst.getLoc());
4315 return;
4316 }
4317
4318 const MCInstrDesc &MCID = MII.get(Opcode: Inst.getOpcode());
4319
4320 // Can't mitigate after terminators or calls. A control flow change may have
4321 // already occurred.
4322 if (MCID.isTerminator() || MCID.isCall())
4323 return;
4324
4325 // LFENCE has the mayLoad property, don't double fence.
4326 if (MCID.mayLoad() && Inst.getOpcode() != X86::LFENCE) {
4327 MCInst FenceInst;
4328 FenceInst.setOpcode(X86::LFENCE);
4329 Out.emitInstruction(Inst: FenceInst, STI: getSTI());
4330 }
4331}
4332
4333void X86AsmParser::emitInstruction(MCInst &Inst, OperandVector &Operands,
4334 MCStreamer &Out) {
4335 if (LVIInlineAsmHardening &&
4336 getSTI().hasFeature(Feature: X86::FeatureLVIControlFlowIntegrity))
4337 applyLVICFIMitigation(Inst, Out);
4338
4339 Out.emitInstruction(Inst, STI: getSTI());
4340
4341 if (LVIInlineAsmHardening &&
4342 getSTI().hasFeature(Feature: X86::FeatureLVILoadHardening))
4343 applyLVILoadHardeningMitigation(Inst, Out);
4344}
4345
4346static unsigned getPrefixes(OperandVector &Operands) {
4347 unsigned Result = 0;
4348 X86Operand &Prefix = static_cast<X86Operand &>(*Operands.back());
4349 if (Prefix.isPrefix()) {
4350 Result = Prefix.getPrefix();
4351 Operands.pop_back();
4352 }
4353 return Result;
4354}
4355
4356bool X86AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
4357 OperandVector &Operands,
4358 MCStreamer &Out, uint64_t &ErrorInfo,
4359 bool MatchingInlineAsm) {
4360 assert(!Operands.empty() && "Unexpect empty operand list!");
4361 assert((*Operands[0]).isToken() && "Leading operand should always be a mnemonic!");
4362
4363 // First, handle aliases that expand to multiple instructions.
4364 MatchFPUWaitAlias(IDLoc, Op&: static_cast<X86Operand &>(*Operands[0]), Operands,
4365 Out, MatchingInlineAsm);
4366 unsigned Prefixes = getPrefixes(Operands);
4367
4368 MCInst Inst;
4369
4370 // If REX/REX2/VEX/EVEX encoding is forced, we need to pass the USE_* flag to
4371 // the encoder and printer.
4372 if (ForcedOpcodePrefix == OpcodePrefix_REX)
4373 Prefixes |= X86::IP_USE_REX;
4374 else if (ForcedOpcodePrefix == OpcodePrefix_REX2)
4375 Prefixes |= X86::IP_USE_REX2;
4376 else if (ForcedOpcodePrefix == OpcodePrefix_VEX)
4377 Prefixes |= X86::IP_USE_VEX;
4378 else if (ForcedOpcodePrefix == OpcodePrefix_VEX2)
4379 Prefixes |= X86::IP_USE_VEX2;
4380 else if (ForcedOpcodePrefix == OpcodePrefix_VEX3)
4381 Prefixes |= X86::IP_USE_VEX3;
4382 else if (ForcedOpcodePrefix == OpcodePrefix_EVEX)
4383 Prefixes |= X86::IP_USE_EVEX;
4384
4385 // Set encoded flags for {disp8} and {disp32}.
4386 if (ForcedDispEncoding == DispEncoding_Disp8)
4387 Prefixes |= X86::IP_USE_DISP8;
4388 else if (ForcedDispEncoding == DispEncoding_Disp32)
4389 Prefixes |= X86::IP_USE_DISP32;
4390
4391 if (Prefixes)
4392 Inst.setFlags(Prefixes);
4393
4394 return isParsingIntelSyntax()
4395 ? matchAndEmitIntelInstruction(IDLoc, Opcode, Inst, Operands, Out,
4396 ErrorInfo, MatchingInlineAsm)
4397 : matchAndEmitATTInstruction(IDLoc, Opcode, Inst, Operands, Out,
4398 ErrorInfo, MatchingInlineAsm);
4399}
4400
4401void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op,
4402 OperandVector &Operands, MCStreamer &Out,
4403 bool MatchingInlineAsm) {
4404 // FIXME: This should be replaced with a real .td file alias mechanism.
4405 // Also, MatchInstructionImpl should actually *do* the EmitInstruction
4406 // call.
4407 const char *Repl = StringSwitch<const char *>(Op.getToken())
4408 .Case(S: "finit", Value: "fninit")
4409 .Case(S: "fsave", Value: "fnsave")
4410 .Case(S: "fstcw", Value: "fnstcw")
4411 .Case(S: "fstcww", Value: "fnstcw")
4412 .Case(S: "fstenv", Value: "fnstenv")
4413 .Case(S: "fstsw", Value: "fnstsw")
4414 .Case(S: "fstsww", Value: "fnstsw")
4415 .Case(S: "fclex", Value: "fnclex")
4416 .Default(Value: nullptr);
4417 if (Repl) {
4418 MCInst Inst;
4419 Inst.setOpcode(X86::WAIT);
4420 Inst.setLoc(IDLoc);
4421 if (!MatchingInlineAsm)
4422 emitInstruction(Inst, Operands, Out);
4423 Operands[0] = X86Operand::CreateToken(Str: Repl, Loc: IDLoc);
4424 }
4425}
4426
4427bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc,
4428 const FeatureBitset &MissingFeatures,
4429 bool MatchingInlineAsm) {
4430 assert(MissingFeatures.any() && "Unknown missing feature!");
4431 SmallString<126> Msg;
4432 raw_svector_ostream OS(Msg);
4433 OS << "instruction requires:";
4434 for (unsigned Feature : MissingFeatures)
4435 OS << ' ' << getSubtargetFeatureName(Val: Feature);
4436 return Error(L: IDLoc, Msg: OS.str(), Range: SMRange(), MatchingInlineAsm);
4437}
4438
4439unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
4440 unsigned Opc = Inst.getOpcode();
4441 const MCInstrDesc &MCID = MII.get(Opcode: Opc);
4442 uint64_t TSFlags = MCID.TSFlags;
4443
4444 if (UseApxExtendedReg && !X86II::canUseApxExtendedReg(Desc: MCID))
4445 return Match_Unsupported;
4446 if (ForcedNoFlag == !(TSFlags & X86II::EVEX_NF) && !X86::isCFCMOVCC(Opcode: Opc))
4447 return Match_Unsupported;
4448
4449 switch (ForcedOpcodePrefix) {
4450 case OpcodePrefix_Default:
4451 break;
4452 case OpcodePrefix_REX:
4453 case OpcodePrefix_REX2:
4454 if (TSFlags & X86II::EncodingMask)
4455 return Match_Unsupported;
4456 break;
4457 case OpcodePrefix_VEX:
4458 case OpcodePrefix_VEX2:
4459 case OpcodePrefix_VEX3:
4460 if ((TSFlags & X86II::EncodingMask) != X86II::VEX)
4461 return Match_Unsupported;
4462 break;
4463 case OpcodePrefix_EVEX:
4464 if (is64BitMode() && (TSFlags & X86II::EncodingMask) != X86II::EVEX &&
4465 !X86::isCMP(Opcode: Opc) && !X86::isTEST(Opcode: Opc))
4466 return Match_Unsupported;
4467 if (!is64BitMode() && (TSFlags & X86II::EncodingMask) != X86II::EVEX)
4468 return Match_Unsupported;
4469 break;
4470 }
4471
4472 if ((TSFlags & X86II::ExplicitOpPrefixMask) == X86II::ExplicitVEXPrefix &&
4473 (ForcedOpcodePrefix != OpcodePrefix_VEX &&
4474 ForcedOpcodePrefix != OpcodePrefix_VEX2 &&
4475 ForcedOpcodePrefix != OpcodePrefix_VEX3))
4476 return Match_Unsupported;
4477
4478 return Match_Success;
4479}
4480
4481bool X86AsmParser::matchAndEmitATTInstruction(
4482 SMLoc IDLoc, unsigned &Opcode, MCInst &Inst, OperandVector &Operands,
4483 MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) {
4484 X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
4485 SMRange EmptyRange;
4486 // In 16-bit mode, if data32 is specified, temporarily switch to 32-bit mode
4487 // when matching the instruction.
4488 if (ForcedDataPrefix == X86::Is32Bit)
4489 SwitchMode(mode: X86::Is32Bit);
4490 // First, try a direct match.
4491 FeatureBitset MissingFeatures;
4492 unsigned OriginalError = MatchInstruction(Operands, Inst, ErrorInfo,
4493 MissingFeatures, matchingInlineAsm: MatchingInlineAsm,
4494 VariantID: isParsingIntelSyntax());
4495 if (ForcedDataPrefix == X86::Is32Bit) {
4496 SwitchMode(mode: X86::Is16Bit);
4497 ForcedDataPrefix = 0;
4498 }
4499 switch (OriginalError) {
4500 default: llvm_unreachable("Unexpected match result!");
4501 case Match_Success:
4502 if (!MatchingInlineAsm && validateInstruction(Inst, Ops: Operands))
4503 return true;
4504 // Some instructions need post-processing to, for example, tweak which
4505 // encoding is selected. Loop on it while changes happen so the
4506 // individual transformations can chain off each other.
4507 if (!MatchingInlineAsm)
4508 while (processInstruction(Inst, Ops: Operands))
4509 ;
4510
4511 Inst.setLoc(IDLoc);
4512 if (!MatchingInlineAsm)
4513 emitInstruction(Inst, Operands, Out);
4514 Opcode = Inst.getOpcode();
4515 return false;
4516 case Match_InvalidImmUnsignedi4: {
4517 SMLoc ErrorLoc = ((X86Operand &)*Operands[ErrorInfo]).getStartLoc();
4518 if (ErrorLoc == SMLoc())
4519 ErrorLoc = IDLoc;
4520 return Error(L: ErrorLoc, Msg: "immediate must be an integer in range [0, 15]",
4521 Range: EmptyRange, MatchingInlineAsm);
4522 }
4523 case Match_InvalidImmUnsignedi6: {
4524 SMLoc ErrorLoc = ((X86Operand &)*Operands[ErrorInfo]).getStartLoc();
4525 if (ErrorLoc == SMLoc())
4526 ErrorLoc = IDLoc;
4527 return Error(L: ErrorLoc, Msg: "immediate must be an integer in range [0, 63]",
4528 Range: EmptyRange, MatchingInlineAsm);
4529 }
4530 case Match_MissingFeature:
4531 return ErrorMissingFeature(IDLoc, MissingFeatures, MatchingInlineAsm);
4532 case Match_InvalidOperand:
4533 case Match_MnemonicFail:
4534 case Match_Unsupported:
4535 break;
4536 }
4537 if (Op.getToken().empty()) {
4538 Error(L: IDLoc, Msg: "instruction must have size higher than 0", Range: EmptyRange,
4539 MatchingInlineAsm);
4540 return true;
4541 }
4542
4543 // FIXME: Ideally, we would only attempt suffix matches for things which are
4544 // valid prefixes, and we could just infer the right unambiguous
4545 // type. However, that requires substantially more matcher support than the
4546 // following hack.
4547
4548 // Change the operand to point to a temporary token.
4549 StringRef Base = Op.getToken();
4550 SmallString<16> Tmp;
4551 Tmp += Base;
4552 Tmp += ' ';
4553 Op.setTokenValue(Tmp);
4554
4555 // If this instruction starts with an 'f', then it is a floating point stack
4556 // instruction. These come in up to three forms for 32-bit, 64-bit, and
4557 // 80-bit floating point, which use the suffixes s,l,t respectively.
4558 //
4559 // Otherwise, we assume that this may be an integer instruction, which comes
4560 // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
4561 const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
4562 // MemSize corresponding to Suffixes. { 8, 16, 32, 64 } { 32, 64, 80, 0 }
4563 const char *MemSize = Base[0] != 'f' ? "\x08\x10\x20\x40" : "\x20\x40\x50\0";
4564
4565 // Check for the various suffix matches.
4566 uint64_t ErrorInfoIgnore;
4567 FeatureBitset ErrorInfoMissingFeatures; // Init suppresses compiler warnings.
4568 unsigned Match[4];
4569
4570 // Some instruction like VPMULDQ is NOT the variant of VPMULD but a new one.
4571 // So we should make sure the suffix matcher only works for memory variant
4572 // that has the same size with the suffix.
4573 // FIXME: This flag is a workaround for legacy instructions that didn't
4574 // declare non suffix variant assembly.
4575 bool HasVectorReg = false;
4576 X86Operand *MemOp = nullptr;
4577 for (const auto &Op : Operands) {
4578 X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
4579 if (X86Op->isVectorReg())
4580 HasVectorReg = true;
4581 else if (X86Op->isMem()) {
4582 MemOp = X86Op;
4583 assert(MemOp->Mem.Size == 0 && "Memory size always 0 under ATT syntax");
4584 // Have we found an unqualified memory operand,
4585 // break. IA allows only one memory operand.
4586 break;
4587 }
4588 }
4589
4590 for (unsigned I = 0, E = std::size(Match); I != E; ++I) {
4591 Tmp.back() = Suffixes[I];
4592 if (MemOp && HasVectorReg)
4593 MemOp->Mem.Size = MemSize[I];
4594 Match[I] = Match_MnemonicFail;
4595 if (MemOp || !HasVectorReg) {
4596 Match[I] =
4597 MatchInstruction(Operands, Inst, ErrorInfo&: ErrorInfoIgnore, MissingFeatures,
4598 matchingInlineAsm: MatchingInlineAsm, VariantID: isParsingIntelSyntax());
4599 // If this returned as a missing feature failure, remember that.
4600 if (Match[I] == Match_MissingFeature)
4601 ErrorInfoMissingFeatures = MissingFeatures;
4602 }
4603 }
4604
4605 // Restore the old token.
4606 Op.setTokenValue(Base);
4607
4608 // If exactly one matched, then we treat that as a successful match (and the
4609 // instruction will already have been filled in correctly, since the failing
4610 // matches won't have modified it).
4611 unsigned NumSuccessfulMatches = llvm::count(Range&: Match, Element: Match_Success);
4612 if (NumSuccessfulMatches == 1) {
4613 if (!MatchingInlineAsm && validateInstruction(Inst, Ops: Operands))
4614 return true;
4615 // Some instructions need post-processing to, for example, tweak which
4616 // encoding is selected. Loop on it while changes happen so the
4617 // individual transformations can chain off each other.
4618 if (!MatchingInlineAsm)
4619 while (processInstruction(Inst, Ops: Operands))
4620 ;
4621
4622 Inst.setLoc(IDLoc);
4623 if (!MatchingInlineAsm)
4624 emitInstruction(Inst, Operands, Out);
4625 Opcode = Inst.getOpcode();
4626 return false;
4627 }
4628
4629 // Otherwise, the match failed, try to produce a decent error message.
4630
4631 // If we had multiple suffix matches, then identify this as an ambiguous
4632 // match.
4633 if (NumSuccessfulMatches > 1) {
4634 char MatchChars[4];
4635 unsigned NumMatches = 0;
4636 for (unsigned I = 0, E = std::size(Match); I != E; ++I)
4637 if (Match[I] == Match_Success)
4638 MatchChars[NumMatches++] = Suffixes[I];
4639
4640 SmallString<126> Msg;
4641 raw_svector_ostream OS(Msg);
4642 OS << "ambiguous instructions require an explicit suffix (could be ";
4643 for (unsigned i = 0; i != NumMatches; ++i) {
4644 if (i != 0)
4645 OS << ", ";
4646 if (i + 1 == NumMatches)
4647 OS << "or ";
4648 OS << "'" << Base << MatchChars[i] << "'";
4649 }
4650 OS << ")";
4651 Error(L: IDLoc, Msg: OS.str(), Range: EmptyRange, MatchingInlineAsm);
4652 return true;
4653 }
4654
4655 // Okay, we know that none of the variants matched successfully.
4656
4657 // If all of the instructions reported an invalid mnemonic, then the original
4658 // mnemonic was invalid.
4659 if (llvm::count(Range&: Match, Element: Match_MnemonicFail) == 4) {
4660 if (OriginalError == Match_MnemonicFail)
4661 return Error(L: IDLoc, Msg: "invalid instruction mnemonic '" + Base + "'",
4662 Range: Op.getLocRange(), MatchingInlineAsm);
4663
4664 if (OriginalError == Match_Unsupported)
4665 return Error(L: IDLoc, Msg: "unsupported instruction", Range: EmptyRange,
4666 MatchingInlineAsm);
4667
4668 assert(OriginalError == Match_InvalidOperand && "Unexpected error");
4669 // Recover location info for the operand if we know which was the problem.
4670 if (ErrorInfo != ~0ULL) {
4671 if (ErrorInfo >= Operands.size())
4672 return Error(L: IDLoc, Msg: "too few operands for instruction", Range: EmptyRange,
4673 MatchingInlineAsm);
4674
4675 X86Operand &Operand = (X86Operand &)*Operands[ErrorInfo];
4676 if (Operand.getStartLoc().isValid()) {
4677 SMRange OperandRange = Operand.getLocRange();
4678 return Error(L: Operand.getStartLoc(), Msg: "invalid operand for instruction",
4679 Range: OperandRange, MatchingInlineAsm);
4680 }
4681 }
4682
4683 return Error(L: IDLoc, Msg: "invalid operand for instruction", Range: EmptyRange,
4684 MatchingInlineAsm);
4685 }
4686
4687 // If one instruction matched as unsupported, report this as unsupported.
4688 if (llvm::count(Range&: Match, Element: Match_Unsupported) == 1) {
4689 return Error(L: IDLoc, Msg: "unsupported instruction", Range: EmptyRange,
4690 MatchingInlineAsm);
4691 }
4692
4693 // If one instruction matched with a missing feature, report this as a
4694 // missing feature.
4695 if (llvm::count(Range&: Match, Element: Match_MissingFeature) == 1) {
4696 ErrorInfo = Match_MissingFeature;
4697 return ErrorMissingFeature(IDLoc, MissingFeatures: ErrorInfoMissingFeatures,
4698 MatchingInlineAsm);
4699 }
4700
4701 // If one instruction matched with an invalid operand, report this as an
4702 // operand failure.
4703 if (llvm::count(Range&: Match, Element: Match_InvalidOperand) == 1) {
4704 return Error(L: IDLoc, Msg: "invalid operand for instruction", Range: EmptyRange,
4705 MatchingInlineAsm);
4706 }
4707
4708 // If all of these were an outright failure, report it in a useless way.
4709 Error(L: IDLoc, Msg: "unknown use of instruction mnemonic without a size suffix",
4710 Range: EmptyRange, MatchingInlineAsm);
4711 return true;
4712}
4713
4714bool X86AsmParser::matchAndEmitIntelInstruction(
4715 SMLoc IDLoc, unsigned &Opcode, MCInst &Inst, OperandVector &Operands,
4716 MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) {
4717 X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
4718 SMRange EmptyRange;
4719 // In 16-bit mode, if data32 is specified, temporarily switch to 32-bit mode
4720 // when matching the instruction. The mode must be restored before the
4721 // instruction is emitted, or the 32-bit form loses its 0x66 prefix.
4722 const bool ForcedData32 = ForcedDataPrefix == X86::Is32Bit;
4723 auto RestoreMode = [&] {
4724 if (ForcedData32) {
4725 SwitchMode(mode: X86::Is16Bit);
4726 ForcedDataPrefix = 0;
4727 }
4728 };
4729 if (ForcedData32)
4730 SwitchMode(mode: X86::Is32Bit);
4731 // Find one unsized memory operand, if present.
4732 X86Operand *UnsizedMemOp = nullptr;
4733 for (const auto &Op : Operands) {
4734 X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
4735 if (X86Op->isMemUnsized()) {
4736 UnsizedMemOp = X86Op;
4737 // Have we found an unqualified memory operand,
4738 // break. IA allows only one memory operand.
4739 break;
4740 }
4741 }
4742
4743 // Allow some instructions to have implicitly pointer-sized operands. This is
4744 // compatible with gas.
4745 StringRef Mnemonic = (static_cast<X86Operand &>(*Operands[0])).getToken();
4746 if (UnsizedMemOp) {
4747 static const char *const PtrSizedInstrs[] = {"call", "jmp", "push", "pop"};
4748 for (const char *Instr : PtrSizedInstrs) {
4749 if (Mnemonic == Instr) {
4750 UnsizedMemOp->Mem.Size = getPointerWidth();
4751 break;
4752 }
4753 }
4754 }
4755
4756 SmallVector<unsigned, 8> Match;
4757 FeatureBitset ErrorInfoMissingFeatures;
4758 FeatureBitset MissingFeatures;
4759 StringRef Base = (static_cast<X86Operand &>(*Operands[0])).getToken();
4760
4761 // If unsized push has immediate operand we should default the default pointer
4762 // size for the size.
4763 if (Mnemonic == "push" && Operands.size() == 2) {
4764 auto *X86Op = static_cast<X86Operand *>(Operands[1].get());
4765 if (X86Op->isImm()) {
4766 // If it's not a constant fall through and let remainder take care of it.
4767 const auto *CE = dyn_cast<MCConstantExpr>(Val: X86Op->getImm());
4768 unsigned Size = getPointerWidth();
4769 if (CE &&
4770 (isIntN(N: Size, x: CE->getValue()) || isUIntN(N: Size, x: CE->getValue()))) {
4771 SmallString<16> Tmp;
4772 Tmp += Base;
4773 Tmp += (is64BitMode())
4774 ? "q"
4775 : (is32BitMode()) ? "l" : (is16BitMode()) ? "w" : " ";
4776 Op.setTokenValue(Tmp);
4777 // Do match in ATT mode to allow explicit suffix usage.
4778 Match.push_back(Elt: MatchInstruction(Operands, Inst, ErrorInfo,
4779 MissingFeatures, matchingInlineAsm: MatchingInlineAsm,
4780 VariantID: false /*isParsingIntelSyntax()*/));
4781 Op.setTokenValue(Base);
4782 }
4783 }
4784 }
4785
4786 // If an unsized memory operand is present, try to match with each memory
4787 // operand size. In Intel assembly, the size is not part of the instruction
4788 // mnemonic.
4789 if (UnsizedMemOp && UnsizedMemOp->isMemUnsized()) {
4790 static const unsigned MopSizes[] = {8, 16, 32, 64, 80, 128, 256, 512};
4791 for (unsigned Size : MopSizes) {
4792 UnsizedMemOp->Mem.Size = Size;
4793 uint64_t ErrorInfoIgnore;
4794 unsigned LastOpcode = Inst.getOpcode();
4795 unsigned M = MatchInstruction(Operands, Inst, ErrorInfo&: ErrorInfoIgnore,
4796 MissingFeatures, matchingInlineAsm: MatchingInlineAsm,
4797 VariantID: isParsingIntelSyntax());
4798 if (Match.empty() || LastOpcode != Inst.getOpcode())
4799 Match.push_back(Elt: M);
4800
4801 // If this returned as a missing feature failure, remember that.
4802 if (Match.back() == Match_MissingFeature)
4803 ErrorInfoMissingFeatures = MissingFeatures;
4804 }
4805
4806 // Restore the size of the unsized memory operand if we modified it.
4807 UnsizedMemOp->Mem.Size = 0;
4808 }
4809
4810 // If we haven't matched anything yet, this is not a basic integer or FPU
4811 // operation. There shouldn't be any ambiguity in our mnemonic table, so try
4812 // matching with the unsized operand.
4813 if (Match.empty()) {
4814 Match.push_back(Elt: MatchInstruction(
4815 Operands, Inst, ErrorInfo, MissingFeatures, matchingInlineAsm: MatchingInlineAsm,
4816 VariantID: isParsingIntelSyntax()));
4817 // If this returned as a missing feature failure, remember that.
4818 if (Match.back() == Match_MissingFeature)
4819 ErrorInfoMissingFeatures = MissingFeatures;
4820 }
4821
4822 // Restore the size of the unsized memory operand if we modified it.
4823 if (UnsizedMemOp)
4824 UnsizedMemOp->Mem.Size = 0;
4825
4826 // If it's a bad mnemonic, all results will be the same.
4827 if (Match.back() == Match_MnemonicFail) {
4828 RestoreMode();
4829 return Error(L: IDLoc, Msg: "invalid instruction mnemonic '" + Mnemonic + "'",
4830 Range: Op.getLocRange(), MatchingInlineAsm);
4831 }
4832
4833 unsigned NumSuccessfulMatches = llvm::count(Range&: Match, Element: Match_Success);
4834
4835 // If matching was ambiguous and we had size information from the frontend,
4836 // try again with that. This handles cases like "movxz eax, m8/m16".
4837 if (UnsizedMemOp && NumSuccessfulMatches > 1 &&
4838 UnsizedMemOp->getMemFrontendSize()) {
4839 UnsizedMemOp->Mem.Size = UnsizedMemOp->getMemFrontendSize();
4840 unsigned M = MatchInstruction(
4841 Operands, Inst, ErrorInfo, MissingFeatures, matchingInlineAsm: MatchingInlineAsm,
4842 VariantID: isParsingIntelSyntax());
4843 if (M == Match_Success)
4844 NumSuccessfulMatches = 1;
4845
4846 // Add a rewrite that encodes the size information we used from the
4847 // frontend.
4848 InstInfo->AsmRewrites->emplace_back(
4849 Args: AOK_SizeDirective, Args: UnsizedMemOp->getStartLoc(),
4850 /*Len=*/Args: 0, Args: UnsizedMemOp->getMemFrontendSize());
4851 }
4852
4853 // Matching is done, so drop back to 16-bit before anything is emitted.
4854 RestoreMode();
4855
4856 // If exactly one matched, then we treat that as a successful match (and the
4857 // instruction will already have been filled in correctly, since the failing
4858 // matches won't have modified it).
4859 if (NumSuccessfulMatches == 1) {
4860 if (!MatchingInlineAsm && validateInstruction(Inst, Ops: Operands))
4861 return true;
4862 // Some instructions need post-processing to, for example, tweak which
4863 // encoding is selected. Loop on it while changes happen so the individual
4864 // transformations can chain off each other.
4865 if (!MatchingInlineAsm)
4866 while (processInstruction(Inst, Ops: Operands))
4867 ;
4868 Inst.setLoc(IDLoc);
4869 if (!MatchingInlineAsm)
4870 emitInstruction(Inst, Operands, Out);
4871 Opcode = Inst.getOpcode();
4872 return false;
4873 } else if (NumSuccessfulMatches > 1) {
4874 assert(UnsizedMemOp &&
4875 "multiple matches only possible with unsized memory operands");
4876 return Error(L: UnsizedMemOp->getStartLoc(),
4877 Msg: "ambiguous operand size for instruction '" + Mnemonic + "\'",
4878 Range: UnsizedMemOp->getLocRange());
4879 }
4880
4881 // If one instruction matched as unsupported, report this as unsupported.
4882 if (llvm::count(Range&: Match, Element: Match_Unsupported) == 1) {
4883 return Error(L: IDLoc, Msg: "unsupported instruction", Range: EmptyRange,
4884 MatchingInlineAsm);
4885 }
4886
4887 // If one instruction matched with a missing feature, report this as a
4888 // missing feature.
4889 if (llvm::count(Range&: Match, Element: Match_MissingFeature) == 1) {
4890 ErrorInfo = Match_MissingFeature;
4891 return ErrorMissingFeature(IDLoc, MissingFeatures: ErrorInfoMissingFeatures,
4892 MatchingInlineAsm);
4893 }
4894
4895 // If one instruction matched with an invalid operand, report this as an
4896 // operand failure.
4897 if (llvm::count(Range&: Match, Element: Match_InvalidOperand) == 1) {
4898 return Error(L: IDLoc, Msg: "invalid operand for instruction", Range: EmptyRange,
4899 MatchingInlineAsm);
4900 }
4901
4902 if (llvm::count(Range&: Match, Element: Match_InvalidImmUnsignedi4) == 1) {
4903 SMLoc ErrorLoc = ((X86Operand &)*Operands[ErrorInfo]).getStartLoc();
4904 if (ErrorLoc == SMLoc())
4905 ErrorLoc = IDLoc;
4906 return Error(L: ErrorLoc, Msg: "immediate must be an integer in range [0, 15]",
4907 Range: EmptyRange, MatchingInlineAsm);
4908 }
4909
4910 if (llvm::count(Range&: Match, Element: Match_InvalidImmUnsignedi6) == 1) {
4911 SMLoc ErrorLoc = ((X86Operand &)*Operands[ErrorInfo]).getStartLoc();
4912 if (ErrorLoc == SMLoc())
4913 ErrorLoc = IDLoc;
4914 return Error(L: ErrorLoc, Msg: "immediate must be an integer in range [0, 63]",
4915 Range: EmptyRange, MatchingInlineAsm);
4916 }
4917
4918 // If all of these were an outright failure, report it in a useless way.
4919 return Error(L: IDLoc, Msg: "unknown instruction mnemonic", Range: EmptyRange,
4920 MatchingInlineAsm);
4921}
4922
4923bool X86AsmParser::omitRegisterFromClobberLists(MCRegister Reg) {
4924 return getX86MCRegisterClass(RC: X86::SEGMENT_REGRegClassID).contains(Reg);
4925}
4926
4927bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
4928 MCAsmParser &Parser = getParser();
4929 StringRef IDVal = DirectiveID.getIdentifier();
4930 if (IDVal.starts_with(Prefix: ".arch"))
4931 return parseDirectiveArch();
4932 if (IDVal.starts_with(Prefix: ".code"))
4933 return ParseDirectiveCode(IDVal, L: DirectiveID.getLoc());
4934 else if (IDVal.starts_with(Prefix: ".att_syntax")) {
4935 if (getLexer().isNot(K: AsmToken::EndOfStatement)) {
4936 if (Parser.getTok().getString() == "prefix")
4937 Parser.Lex();
4938 else if (Parser.getTok().getString() == "noprefix")
4939 return Error(L: DirectiveID.getLoc(), Msg: "'.att_syntax noprefix' is not "
4940 "supported: registers must have a "
4941 "'%' prefix in .att_syntax");
4942 }
4943 getParser().setAssemblerDialect(0);
4944 return false;
4945 } else if (IDVal.starts_with(Prefix: ".intel_syntax")) {
4946 getParser().setAssemblerDialect(1);
4947 if (getLexer().isNot(K: AsmToken::EndOfStatement)) {
4948 if (Parser.getTok().getString() == "noprefix")
4949 Parser.Lex();
4950 else if (Parser.getTok().getString() == "prefix")
4951 return Error(L: DirectiveID.getLoc(), Msg: "'.intel_syntax prefix' is not "
4952 "supported: registers must not have "
4953 "a '%' prefix in .intel_syntax");
4954 }
4955 return false;
4956 } else if (IDVal == ".nops")
4957 return parseDirectiveNops(L: DirectiveID.getLoc());
4958 else if (IDVal == ".even")
4959 return parseDirectiveEven(L: DirectiveID.getLoc());
4960 else if (IDVal == ".cv_fpo_proc")
4961 return parseDirectiveFPOProc(L: DirectiveID.getLoc());
4962 else if (IDVal == ".cv_fpo_setframe")
4963 return parseDirectiveFPOSetFrame(L: DirectiveID.getLoc());
4964 else if (IDVal == ".cv_fpo_pushreg")
4965 return parseDirectiveFPOPushReg(L: DirectiveID.getLoc());
4966 else if (IDVal == ".cv_fpo_stackalloc")
4967 return parseDirectiveFPOStackAlloc(L: DirectiveID.getLoc());
4968 else if (IDVal == ".cv_fpo_stackalign")
4969 return parseDirectiveFPOStackAlign(L: DirectiveID.getLoc());
4970 else if (IDVal == ".cv_fpo_endprologue")
4971 return parseDirectiveFPOEndPrologue(L: DirectiveID.getLoc());
4972 else if (IDVal == ".cv_fpo_endproc")
4973 return parseDirectiveFPOEndProc(L: DirectiveID.getLoc());
4974 else if (IDVal == ".seh_pushreg")
4975 return parseDirectiveSEHPushReg(DirectiveID.getLoc());
4976 else if (IDVal == ".seh_push2regs")
4977 return parseDirectiveSEHPush2Regs(DirectiveID.getLoc());
4978 else if (IDVal == ".seh_setframe")
4979 return parseDirectiveSEHSetFrame(DirectiveID.getLoc());
4980 else if (IDVal == ".seh_savereg")
4981 return parseDirectiveSEHSaveReg(DirectiveID.getLoc());
4982 else if (IDVal == ".seh_savexmm")
4983 return parseDirectiveSEHSaveXMM(DirectiveID.getLoc());
4984 else if (IDVal == ".seh_pushframe")
4985 return parseDirectiveSEHPushFrame(DirectiveID.getLoc());
4986 else if (Parser.isParsingMasm()) {
4987 // MASM prolog directives.
4988 if (IDVal.equals_insensitive(RHS: ".pushreg")) {
4989 return ensureMasmPrologContext(Loc: DirectiveID.getLoc()) ||
4990 parseDirectiveSEHPushReg(DirectiveID.getLoc());
4991 } else if (IDVal.equals_insensitive(RHS: ".push2reg")) {
4992 return ensureMasmPrologContext(Loc: DirectiveID.getLoc()) ||
4993 parseDirectiveSEHPush2Regs(DirectiveID.getLoc());
4994 } else if (IDVal.equals_insensitive(RHS: ".setframe")) {
4995 return ensureMasmPrologContext(Loc: DirectiveID.getLoc()) ||
4996 parseDirectiveSEHSetFrame(DirectiveID.getLoc());
4997 } else if (IDVal.equals_insensitive(RHS: ".savereg")) {
4998 return ensureMasmPrologContext(Loc: DirectiveID.getLoc()) ||
4999 parseDirectiveSEHSaveReg(DirectiveID.getLoc());
5000 } else if (IDVal.equals_insensitive(RHS: ".savexmm128")) {
5001 return ensureMasmPrologContext(Loc: DirectiveID.getLoc()) ||
5002 parseDirectiveSEHSaveXMM(DirectiveID.getLoc());
5003 } else if (IDVal.equals_insensitive(RHS: ".pushframe")) {
5004 return ensureMasmPrologContext(Loc: DirectiveID.getLoc()) ||
5005 parseDirectiveSEHPushFrame(DirectiveID.getLoc());
5006 }
5007 // MASM epilog directives
5008 if (IDVal.equals_insensitive(RHS: ".popreg")) {
5009 return ensureMasmEpilogContext(Loc: DirectiveID.getLoc()) ||
5010 parseDirectiveSEHPushReg(DirectiveID.getLoc());
5011 } else if (IDVal.equals_insensitive(RHS: ".pop2reg")) {
5012 // .pop2reg args are in the order they are popped, so reverse them to get
5013 // the order they were pushed.
5014 return ensureMasmEpilogContext(Loc: DirectiveID.getLoc()) ||
5015 parseDirectiveSEHPush2Regs(DirectiveID.getLoc(),
5016 /*SwapRegs=*/true);
5017 } else if (IDVal.equals_insensitive(RHS: ".unsetframe")) {
5018 return ensureMasmEpilogContext(Loc: DirectiveID.getLoc()) ||
5019 parseDirectiveSEHSetFrame(DirectiveID.getLoc());
5020 } else if (IDVal.equals_insensitive(RHS: ".restorereg")) {
5021 return ensureMasmEpilogContext(Loc: DirectiveID.getLoc()) ||
5022 parseDirectiveSEHSaveReg(DirectiveID.getLoc());
5023 } else if (IDVal.equals_insensitive(RHS: ".restorexmm128")) {
5024 return ensureMasmEpilogContext(Loc: DirectiveID.getLoc()) ||
5025 parseDirectiveSEHSaveXMM(DirectiveID.getLoc());
5026 }
5027 }
5028
5029 return true;
5030}
5031
5032bool X86AsmParser::parseDirectiveArch() {
5033 // Ignore .arch for now.
5034 getParser().parseStringToEndOfStatement();
5035 return false;
5036}
5037
5038/// parseDirectiveNops
5039/// ::= .nops size[, control]
5040bool X86AsmParser::parseDirectiveNops(SMLoc L) {
5041 int64_t NumBytes = 0, Control = 0;
5042 SMLoc NumBytesLoc, ControlLoc;
5043 const MCSubtargetInfo& STI = getSTI();
5044 NumBytesLoc = getTok().getLoc();
5045 if (getParser().checkForValidSection() ||
5046 getParser().parseAbsoluteExpression(Res&: NumBytes))
5047 return true;
5048
5049 if (parseOptionalToken(T: AsmToken::Comma)) {
5050 ControlLoc = getTok().getLoc();
5051 if (getParser().parseAbsoluteExpression(Res&: Control))
5052 return true;
5053 }
5054 if (getParser().parseEOL())
5055 return true;
5056
5057 if (NumBytes <= 0) {
5058 Error(L: NumBytesLoc, Msg: "'.nops' directive with non-positive size");
5059 return false;
5060 }
5061
5062 if (Control < 0) {
5063 Error(L: ControlLoc, Msg: "'.nops' directive with negative NOP size");
5064 return false;
5065 }
5066
5067 /// Emit nops
5068 getParser().getStreamer().emitNops(NumBytes, ControlledNopLength: Control, Loc: L, STI);
5069
5070 return false;
5071}
5072
5073/// parseDirectiveEven
5074/// ::= .even
5075bool X86AsmParser::parseDirectiveEven(SMLoc L) {
5076 if (parseEOL())
5077 return false;
5078
5079 const MCSection *Section = getStreamer().getCurrentSectionOnly();
5080 if (!Section) {
5081 getStreamer().initSections(STI: getSTI());
5082 Section = getStreamer().getCurrentSectionOnly();
5083 }
5084 if (getContext().getAsmInfo().useCodeAlign(Sec: *Section))
5085 getStreamer().emitCodeAlignment(Alignment: Align(2), STI: getSTI(), MaxBytesToEmit: 0);
5086 else
5087 getStreamer().emitValueToAlignment(Alignment: Align(2), Fill: 0, FillLen: 1, MaxBytesToEmit: 0);
5088 return false;
5089}
5090
5091/// ParseDirectiveCode
5092/// ::= .code16 | .code32 | .code64
5093bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
5094 MCAsmParser &Parser = getParser();
5095 Code16GCC = false;
5096 if (IDVal == ".code16") {
5097 Parser.Lex();
5098 if (!is16BitMode()) {
5099 SwitchMode(mode: X86::Is16Bit);
5100 getTargetStreamer().emitCode16();
5101 }
5102 } else if (IDVal == ".code16gcc") {
5103 // .code16gcc parses as if in 32-bit mode, but emits code in 16-bit mode.
5104 Parser.Lex();
5105 Code16GCC = true;
5106 if (!is16BitMode()) {
5107 SwitchMode(mode: X86::Is16Bit);
5108 getTargetStreamer().emitCode16();
5109 }
5110 } else if (IDVal == ".code32") {
5111 Parser.Lex();
5112 if (!is32BitMode()) {
5113 SwitchMode(mode: X86::Is32Bit);
5114 getTargetStreamer().emitCode32();
5115 }
5116 } else if (IDVal == ".code64") {
5117 Parser.Lex();
5118 if (!is64BitMode()) {
5119 SwitchMode(mode: X86::Is64Bit);
5120 getTargetStreamer().emitCode64();
5121 }
5122 } else {
5123 Error(L, Msg: "unknown directive " + IDVal);
5124 return false;
5125 }
5126
5127 return false;
5128}
5129
5130// .cv_fpo_proc foo
5131bool X86AsmParser::parseDirectiveFPOProc(SMLoc L) {
5132 MCAsmParser &Parser = getParser();
5133 StringRef ProcName;
5134 int64_t ParamsSize;
5135 if (Parser.parseIdentifier(Res&: ProcName))
5136 return Parser.TokError(Msg: "expected symbol name");
5137 if (Parser.parseIntToken(V&: ParamsSize, ErrMsg: "expected parameter byte count"))
5138 return true;
5139 if (!isUIntN(N: 32, x: ParamsSize))
5140 return Parser.TokError(Msg: "parameters size out of range");
5141 if (parseEOL())
5142 return true;
5143 MCSymbol *ProcSym = getContext().getOrCreateSymbol(Name: ProcName);
5144 return getTargetStreamer().emitFPOProc(ProcSym, ParamsSize, L);
5145}
5146
5147// .cv_fpo_setframe ebp
5148bool X86AsmParser::parseDirectiveFPOSetFrame(SMLoc L) {
5149 MCRegister Reg;
5150 SMLoc DummyLoc;
5151 if (parseRegister(Reg, StartLoc&: DummyLoc, EndLoc&: DummyLoc) || parseEOL())
5152 return true;
5153 return getTargetStreamer().emitFPOSetFrame(Reg, L);
5154}
5155
5156// .cv_fpo_pushreg ebx
5157bool X86AsmParser::parseDirectiveFPOPushReg(SMLoc L) {
5158 MCRegister Reg;
5159 SMLoc DummyLoc;
5160 if (parseRegister(Reg, StartLoc&: DummyLoc, EndLoc&: DummyLoc) || parseEOL())
5161 return true;
5162 return getTargetStreamer().emitFPOPushReg(Reg, L);
5163}
5164
5165// .cv_fpo_stackalloc 20
5166bool X86AsmParser::parseDirectiveFPOStackAlloc(SMLoc L) {
5167 MCAsmParser &Parser = getParser();
5168 int64_t Offset;
5169 if (Parser.parseIntToken(V&: Offset, ErrMsg: "expected offset") || parseEOL())
5170 return true;
5171 return getTargetStreamer().emitFPOStackAlloc(StackAlloc: Offset, L);
5172}
5173
5174// .cv_fpo_stackalign 8
5175bool X86AsmParser::parseDirectiveFPOStackAlign(SMLoc L) {
5176 MCAsmParser &Parser = getParser();
5177 int64_t Offset;
5178 if (Parser.parseIntToken(V&: Offset, ErrMsg: "expected offset") || parseEOL())
5179 return true;
5180 return getTargetStreamer().emitFPOStackAlign(Align: Offset, L);
5181}
5182
5183// .cv_fpo_endprologue
5184bool X86AsmParser::parseDirectiveFPOEndPrologue(SMLoc L) {
5185 MCAsmParser &Parser = getParser();
5186 if (Parser.parseEOL())
5187 return true;
5188 return getTargetStreamer().emitFPOEndPrologue(L);
5189}
5190
5191// .cv_fpo_endproc
5192bool X86AsmParser::parseDirectiveFPOEndProc(SMLoc L) {
5193 MCAsmParser &Parser = getParser();
5194 if (Parser.parseEOL())
5195 return true;
5196 return getTargetStreamer().emitFPOEndProc(L);
5197}
5198
5199bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID,
5200 MCRegister &RegNo) {
5201 SMLoc startLoc = getLexer().getLoc();
5202 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
5203
5204 // Try parsing the argument as a register first.
5205 if (getLexer().getTok().isNot(K: AsmToken::Integer)) {
5206 SMLoc endLoc;
5207 if (parseRegister(Reg&: RegNo, StartLoc&: startLoc, EndLoc&: endLoc))
5208 return true;
5209
5210 if (!getX86MCRegisterClass(RC: RegClassID).contains(Reg: RegNo)) {
5211 return Error(L: startLoc,
5212 Msg: "register is not supported for use with this directive");
5213 }
5214 } else {
5215 // Otherwise, an integer number matching the encoding of the desired
5216 // register may appear.
5217 int64_t EncodedReg;
5218 if (getParser().parseAbsoluteExpression(Res&: EncodedReg))
5219 return true;
5220
5221 // The SEH register number is the same as the encoding register number. Map
5222 // from the encoding back to the LLVM register number.
5223 RegNo = MCRegister();
5224 for (MCPhysReg Reg : getX86MCRegisterClass(RC: RegClassID)) {
5225 if (MRI->getEncodingValue(Reg) == EncodedReg) {
5226 RegNo = Reg;
5227 break;
5228 }
5229 }
5230 if (!RegNo) {
5231 return Error(L: startLoc,
5232 Msg: "incorrect register number for use with this directive");
5233 }
5234 }
5235
5236 return false;
5237}
5238
5239bool X86AsmParser::parseDirectiveSEHPushReg(SMLoc Loc) {
5240 MCRegister Reg;
5241 if (parseSEHRegisterNumber(RegClassID: X86::GR64RegClassID, RegNo&: Reg))
5242 return true;
5243
5244 if (getLexer().isNot(K: AsmToken::EndOfStatement))
5245 return TokError(Msg: "expected end of directive");
5246
5247 getParser().Lex();
5248 getStreamer().emitWinCFIPushReg(Register: Reg, Loc);
5249 return false;
5250}
5251
5252bool X86AsmParser::parseDirectiveSEHPush2Regs(SMLoc Loc, bool SwapRegs) {
5253 MCRegister Reg1;
5254 if (parseSEHRegisterNumber(RegClassID: X86::GR64RegClassID, RegNo&: Reg1))
5255 return true;
5256
5257 if (getLexer().isNot(K: AsmToken::Comma))
5258 return TokError(Msg: "expected comma between registers");
5259 getParser().Lex();
5260
5261 MCRegister Reg2;
5262 if (parseSEHRegisterNumber(RegClassID: X86::GR64RegClassID, RegNo&: Reg2))
5263 return true;
5264
5265 if (getLexer().isNot(K: AsmToken::EndOfStatement))
5266 return TokError(Msg: "expected end of directive");
5267
5268 getParser().Lex();
5269 // Swap regs to go from pop order to push order.
5270 if (SwapRegs)
5271 std::swap(a&: Reg1, b&: Reg2);
5272 getStreamer().emitWinCFIPush2Regs(Reg1, Reg2, Loc);
5273 return false;
5274}
5275
5276bool X86AsmParser::parseDirectiveSEHSetFrame(SMLoc Loc) {
5277 MCRegister Reg;
5278 int64_t Off;
5279 if (parseSEHRegisterNumber(RegClassID: X86::GR64RegClassID, RegNo&: Reg))
5280 return true;
5281 if (getLexer().isNot(K: AsmToken::Comma))
5282 return TokError(Msg: "you must specify a stack pointer offset");
5283
5284 getParser().Lex();
5285 if (getParser().parseAbsoluteExpression(Res&: Off))
5286 return true;
5287
5288 if (getLexer().isNot(K: AsmToken::EndOfStatement))
5289 return TokError(Msg: "expected end of directive");
5290
5291 getParser().Lex();
5292 getStreamer().emitWinCFISetFrame(Register: Reg, Offset: Off, Loc);
5293 return false;
5294}
5295
5296bool X86AsmParser::parseDirectiveSEHSaveReg(SMLoc Loc) {
5297 MCRegister Reg;
5298 int64_t Off;
5299 if (parseSEHRegisterNumber(RegClassID: X86::GR64RegClassID, RegNo&: Reg))
5300 return true;
5301 if (getLexer().isNot(K: AsmToken::Comma))
5302 return TokError(Msg: "you must specify an offset on the stack");
5303
5304 getParser().Lex();
5305 if (getParser().parseAbsoluteExpression(Res&: Off))
5306 return true;
5307
5308 if (getLexer().isNot(K: AsmToken::EndOfStatement))
5309 return TokError(Msg: "expected end of directive");
5310
5311 getParser().Lex();
5312 getStreamer().emitWinCFISaveReg(Register: Reg, Offset: Off, Loc);
5313 return false;
5314}
5315
5316bool X86AsmParser::parseDirectiveSEHSaveXMM(SMLoc Loc) {
5317 MCRegister Reg;
5318 int64_t Off;
5319 if (parseSEHRegisterNumber(RegClassID: X86::VR128XRegClassID, RegNo&: Reg))
5320 return true;
5321 if (getLexer().isNot(K: AsmToken::Comma))
5322 return TokError(Msg: "you must specify an offset on the stack");
5323
5324 getParser().Lex();
5325 if (getParser().parseAbsoluteExpression(Res&: Off))
5326 return true;
5327
5328 if (getLexer().isNot(K: AsmToken::EndOfStatement))
5329 return TokError(Msg: "expected end of directive");
5330
5331 getParser().Lex();
5332 getStreamer().emitWinCFISaveXMM(Register: Reg, Offset: Off, Loc);
5333 return false;
5334}
5335
5336bool X86AsmParser::ensureMasmPrologContext(SMLoc Loc) {
5337 if (getStreamer().isWinCFIPrologEnded()) {
5338 return Error(L: Loc, Msg: "prolog directive must be used inside a prolog");
5339 }
5340 return false;
5341}
5342
5343bool X86AsmParser::ensureMasmEpilogContext(SMLoc Loc) {
5344 if (!getStreamer().isInEpilogCFI()) {
5345 return Error(L: Loc, Msg: "epilog directive must be used inside an epilog");
5346 }
5347 return false;
5348}
5349
5350bool X86AsmParser::parseDirectiveSEHPushFrame(SMLoc Loc) {
5351 bool Code = false;
5352 StringRef CodeID;
5353 if (getLexer().is(K: AsmToken::At)) {
5354 SMLoc startLoc = getLexer().getLoc();
5355 getParser().Lex();
5356 if (!getParser().parseIdentifier(Res&: CodeID)) {
5357 if (CodeID != "code")
5358 return Error(L: startLoc, Msg: "expected @code");
5359 Code = true;
5360 }
5361 } else if (getParser().isParsingMasm() &&
5362 getLexer().is(K: AsmToken::Identifier) &&
5363 getTok().getString().equals_insensitive(RHS: "code")) {
5364 getParser().Lex();
5365 Code = true;
5366 }
5367
5368 if (getLexer().isNot(K: AsmToken::EndOfStatement))
5369 return TokError(Msg: "expected end of directive");
5370
5371 getParser().Lex();
5372 getStreamer().emitWinCFIPushFrame(Code, Loc);
5373 return false;
5374}
5375
5376// Force static initialization.
5377extern "C" LLVM_C_ABI void LLVMInitializeX86AsmParser() {
5378 RegisterMCAsmParser<X86AsmParser> X(getTheX86_32Target());
5379 RegisterMCAsmParser<X86AsmParser> Y(getTheX86_64Target());
5380}
5381
5382#define GET_MATCHER_IMPLEMENTATION
5383#include "X86GenAsmMatcher.inc"
5384