1//===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone helper functions and enum definitions for
10// the X86 target useful for the compiler back-end and the MC libraries.
11// As such, it deliberately does not include references to LLVM core
12// code gen types, passes, etc..
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
17#define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
18
19#include "X86MCTargetDesc.h"
20#include "llvm/MC/MCInstrDesc.h"
21#include "llvm/Support/DataTypes.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/MathExtras.h"
24
25namespace llvm {
26namespace X86 {
27// Enums for memory operand decoding. Each memory operand is represented with
28// a 5 operand sequence in the form: [Base, Scale, Index, Disp, Segment]
29enum {
30 AddrBaseReg = 0,
31 AddrScaleAmt = 1,
32 AddrIndexReg = 2,
33 AddrDisp = 3,
34 // The operand # of the segment in the memory operand.
35 AddrSegmentReg = 4,
36 // Total number of operands in a memory reference.
37 AddrNumOperands = 5
38};
39
40/// AVX512 static rounding constants. These need to match the values in
41/// avx512fintrin.h.
42enum STATIC_ROUNDING {
43 TO_NEAREST_INT = 0,
44 TO_NEG_INF = 1,
45 TO_POS_INF = 2,
46 TO_ZERO = 3,
47 CUR_DIRECTION = 4,
48 NO_EXC = 8
49};
50
51/// The constants to describe instr prefixes if there are
52enum IPREFIXES {
53 IP_NO_PREFIX = 0,
54 IP_HAS_OP_SIZE = 1U << 0,
55 IP_HAS_AD_SIZE = 1U << 1,
56 IP_HAS_REPEAT_NE = 1U << 2,
57 IP_HAS_REPEAT = 1U << 3,
58 IP_HAS_LOCK = 1U << 4,
59 IP_HAS_NOTRACK = 1U << 5,
60 IP_USE_REX = 1U << 6,
61 IP_USE_REX2 = 1U << 7,
62 IP_USE_VEX = 1U << 8,
63 IP_USE_VEX2 = 1U << 9,
64 IP_USE_VEX3 = 1U << 10,
65 IP_USE_EVEX = 1U << 11,
66 IP_USE_DISP8 = 1U << 12,
67 IP_USE_DISP32 = 1U << 13,
68};
69
70enum OperandType : unsigned {
71 // AVX512 embedded rounding control. This should only have values 0-3.
72 OPERAND_ROUNDING_CONTROL = MCOI::OPERAND_FIRST_TARGET,
73 OPERAND_COND_CODE,
74};
75
76// X86 specific condition code. These correspond to X86_*_COND in
77// X86InstrInfo.td. They must be kept in synch.
78enum CondCode {
79 COND_O = 0,
80 COND_NO = 1,
81 COND_B = 2,
82 COND_AE = 3,
83 COND_E = 4,
84 COND_NE = 5,
85 COND_BE = 6,
86 COND_A = 7,
87 COND_S = 8,
88 COND_NS = 9,
89 COND_P = 10,
90 COND_NP = 11,
91 COND_L = 12,
92 COND_GE = 13,
93 COND_LE = 14,
94 COND_G = 15,
95 LAST_VALID_COND = COND_G,
96 // Artificial condition codes. These are used by analyzeBranch
97 // to indicate a block terminated with two conditional branches that together
98 // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
99 // which can't be represented on x86 with a single condition. These
100 // are never used in MachineInstrs and are inverses of one another.
101 COND_NE_OR_P,
102 COND_E_AND_NP,
103 COND_INVALID
104};
105
106// The classification for the first instruction in macro fusion.
107// FIXME: Zen 3 support branch fusion for OR/XOR.
108enum class FirstMacroFusionInstKind {
109 Test, // TEST
110 Cmp, // CMP
111 And, // AND
112 AddSub, // ADD, SUB
113 IncDec, // INC, DEC
114 Invalid // Not valid as a first macro fusion instruction
115};
116
117enum class SecondMacroFusionInstKind {
118 AB, // JA, JB and variants
119 ELG, // JE, JL, JG and variants
120 SPO, // JS, JP, JO and variants
121 Invalid, // Not a fusible jump.
122};
123
124/// \returns the type of the first instruction in macro-fusion.
125// FIXME: Zen 3 support branch fusion for OR/XOR.
126inline FirstMacroFusionInstKind
127classifyFirstOpcodeInMacroFusion(unsigned Opcode) {
128 switch (Opcode) {
129 default:
130 return FirstMacroFusionInstKind::Invalid;
131 // TEST
132 case X86::TEST16i16:
133 case X86::TEST16mr:
134 case X86::TEST16ri:
135 case X86::TEST16rr:
136 case X86::TEST32i32:
137 case X86::TEST32mr:
138 case X86::TEST32ri:
139 case X86::TEST32rr:
140 case X86::TEST64i32:
141 case X86::TEST64mr:
142 case X86::TEST64ri32:
143 case X86::TEST64rr:
144 case X86::TEST8i8:
145 case X86::TEST8mr:
146 case X86::TEST8ri:
147 case X86::TEST8rr:
148 return FirstMacroFusionInstKind::Test;
149 case X86::AND16i16:
150 case X86::AND16ri:
151 case X86::AND16ri8:
152 case X86::AND16rm:
153 case X86::AND16rr:
154 case X86::AND32i32:
155 case X86::AND32ri:
156 case X86::AND32ri8:
157 case X86::AND32rm:
158 case X86::AND32rr:
159 case X86::AND64i32:
160 case X86::AND64ri32:
161 case X86::AND64ri8:
162 case X86::AND64rm:
163 case X86::AND64rr:
164 case X86::AND8i8:
165 case X86::AND8ri:
166 case X86::AND8ri8:
167 case X86::AND8rm:
168 case X86::AND8rr:
169 return FirstMacroFusionInstKind::And;
170 // CMP
171 case X86::CMP16i16:
172 case X86::CMP16mr:
173 case X86::CMP16ri:
174 case X86::CMP16ri8:
175 case X86::CMP16rm:
176 case X86::CMP16rr:
177 case X86::CMP32i32:
178 case X86::CMP32mr:
179 case X86::CMP32ri:
180 case X86::CMP32ri8:
181 case X86::CMP32rm:
182 case X86::CMP32rr:
183 case X86::CMP64i32:
184 case X86::CMP64mr:
185 case X86::CMP64ri32:
186 case X86::CMP64ri8:
187 case X86::CMP64rm:
188 case X86::CMP64rr:
189 case X86::CMP8i8:
190 case X86::CMP8mr:
191 case X86::CMP8ri:
192 case X86::CMP8ri8:
193 case X86::CMP8rm:
194 case X86::CMP8rr:
195 return FirstMacroFusionInstKind::Cmp;
196 // ADD
197 case X86::ADD16i16:
198 case X86::ADD16ri:
199 case X86::ADD16ri8:
200 case X86::ADD16rm:
201 case X86::ADD16rr:
202 case X86::ADD32i32:
203 case X86::ADD32ri:
204 case X86::ADD32ri8:
205 case X86::ADD32rm:
206 case X86::ADD32rr:
207 case X86::ADD64i32:
208 case X86::ADD64ri32:
209 case X86::ADD64ri8:
210 case X86::ADD64rm:
211 case X86::ADD64rr:
212 case X86::ADD8i8:
213 case X86::ADD8ri:
214 case X86::ADD8ri8:
215 case X86::ADD8rm:
216 case X86::ADD8rr:
217 // SUB
218 case X86::SUB16i16:
219 case X86::SUB16ri:
220 case X86::SUB16ri8:
221 case X86::SUB16rm:
222 case X86::SUB16rr:
223 case X86::SUB32i32:
224 case X86::SUB32ri:
225 case X86::SUB32ri8:
226 case X86::SUB32rm:
227 case X86::SUB32rr:
228 case X86::SUB64i32:
229 case X86::SUB64ri32:
230 case X86::SUB64ri8:
231 case X86::SUB64rm:
232 case X86::SUB64rr:
233 case X86::SUB8i8:
234 case X86::SUB8ri:
235 case X86::SUB8ri8:
236 case X86::SUB8rm:
237 case X86::SUB8rr:
238 return FirstMacroFusionInstKind::AddSub;
239 // INC
240 case X86::INC16r:
241 case X86::INC16r_alt:
242 case X86::INC32r:
243 case X86::INC32r_alt:
244 case X86::INC64r:
245 case X86::INC8r:
246 // DEC
247 case X86::DEC16r:
248 case X86::DEC16r_alt:
249 case X86::DEC32r:
250 case X86::DEC32r_alt:
251 case X86::DEC64r:
252 case X86::DEC8r:
253 return FirstMacroFusionInstKind::IncDec;
254 }
255}
256
257/// \returns the type of the second instruction in macro-fusion.
258inline SecondMacroFusionInstKind
259classifySecondCondCodeInMacroFusion(X86::CondCode CC) {
260 if (CC == X86::COND_INVALID)
261 return SecondMacroFusionInstKind::Invalid;
262 switch (CC) {
263 default:
264 return SecondMacroFusionInstKind::Invalid;
265 case X86::COND_E: // JE,JZ
266 case X86::COND_NE: // JNE,JNZ
267 case X86::COND_L: // JL,JNGE
268 case X86::COND_LE: // JLE,JNG
269 case X86::COND_G: // JG,JNLE
270 case X86::COND_GE: // JGE,JNL
271 return SecondMacroFusionInstKind::ELG;
272 case X86::COND_B: // JB,JC
273 case X86::COND_BE: // JNA,JBE
274 case X86::COND_A: // JA,JNBE
275 case X86::COND_AE: // JAE,JNC,JNB
276 return SecondMacroFusionInstKind::AB;
277 case X86::COND_S: // JS
278 case X86::COND_NS: // JNS
279 case X86::COND_P: // JP,JPE
280 case X86::COND_NP: // JNP,JPO
281 case X86::COND_O: // JO
282 case X86::COND_NO: // JNO
283 return SecondMacroFusionInstKind::SPO;
284 }
285}
286
287/// \param FirstKind kind of the first instruction in macro fusion.
288/// \param SecondKind kind of the second instruction in macro fusion.
289///
290/// \returns true if the two instruction can be macro fused.
291inline bool isMacroFused(FirstMacroFusionInstKind FirstKind,
292 SecondMacroFusionInstKind SecondKind) {
293 switch (FirstKind) {
294 case X86::FirstMacroFusionInstKind::Test:
295 case X86::FirstMacroFusionInstKind::And:
296 return true;
297 case X86::FirstMacroFusionInstKind::Cmp:
298 case X86::FirstMacroFusionInstKind::AddSub:
299 return SecondKind == X86::SecondMacroFusionInstKind::AB ||
300 SecondKind == X86::SecondMacroFusionInstKind::ELG;
301 case X86::FirstMacroFusionInstKind::IncDec:
302 return SecondKind == X86::SecondMacroFusionInstKind::ELG;
303 case X86::FirstMacroFusionInstKind::Invalid:
304 return false;
305 }
306 llvm_unreachable("unknown fusion type");
307}
308
309/// Defines the possible values of the branch boundary alignment mask.
310enum AlignBranchBoundaryKind : uint8_t {
311 AlignBranchNone = 0,
312 AlignBranchFused = 1U << 0,
313 AlignBranchJcc = 1U << 1,
314 AlignBranchJmp = 1U << 2,
315 AlignBranchCall = 1U << 3,
316 AlignBranchRet = 1U << 4,
317 AlignBranchIndirect = 1U << 5
318};
319
320/// Defines the encoding values for segment override prefix.
321enum EncodingOfSegmentOverridePrefix : uint8_t {
322 CS_Encoding = 0x2E,
323 DS_Encoding = 0x3E,
324 ES_Encoding = 0x26,
325 FS_Encoding = 0x64,
326 GS_Encoding = 0x65,
327 SS_Encoding = 0x36
328};
329
330/// Given a segment register, return the encoding of the segment override
331/// prefix for it.
332inline EncodingOfSegmentOverridePrefix
333getSegmentOverridePrefixForReg(MCRegister Reg) {
334 switch (Reg.id()) {
335 default:
336 llvm_unreachable("Unknown segment register!");
337 case X86::CS:
338 return CS_Encoding;
339 case X86::DS:
340 return DS_Encoding;
341 case X86::ES:
342 return ES_Encoding;
343 case X86::FS:
344 return FS_Encoding;
345 case X86::GS:
346 return GS_Encoding;
347 case X86::SS:
348 return SS_Encoding;
349 }
350}
351
352} // namespace X86
353
354/// X86II - This namespace holds all of the target specific flags that
355/// instruction info tracks.
356///
357namespace X86II {
358/// Target Operand Flag enum.
359enum TOF {
360 //===------------------------------------------------------------------===//
361 // X86 Specific MachineOperand flags.
362 //
363 /// MO_NO_FLAG - No flag for the operand
364 MO_NO_FLAG,
365 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
366 /// relocation of:
367 /// SYMBOL_LABEL + [. - PICBASELABEL]
368 MO_GOT_ABSOLUTE_ADDRESS,
369 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
370 /// immediate should get the value of the symbol minus the PIC base label:
371 /// SYMBOL_LABEL - PICBASELABEL
372 MO_PIC_BASE_OFFSET,
373 /// MO_GOT - On a symbol operand this indicates that the immediate is the
374 /// offset to the GOT entry for the symbol name from the base of the GOT.
375 /// See the X86-64 ELF ABI supplement for more details.
376 /// SYMBOL_LABEL @GOT
377 MO_GOT,
378 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
379 /// the offset to the location of the symbol name from the base of the GOT.
380 /// See the X86-64 ELF ABI supplement for more details.
381 /// SYMBOL_LABEL @GOTOFF
382 MO_GOTOFF,
383 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
384 /// offset to the GOT entry for the symbol name from the current code
385 /// location.
386 /// See the X86-64 ELF ABI supplement for more details.
387 /// SYMBOL_LABEL @GOTPCREL
388 MO_GOTPCREL,
389 /// MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL
390 /// relocations are guaranteed to be emitted by the integrated assembler
391 /// instead of the relaxable R_X86_64[_REX]_GOTPCRELX relocations.
392 MO_GOTPCREL_NORELAX,
393 /// MO_PLT - On a symbol operand this indicates that the immediate is
394 /// offset to the PLT entry of symbol name from the current code location.
395 /// See the X86-64 ELF ABI supplement for more details.
396 /// SYMBOL_LABEL @PLT
397 MO_PLT,
398 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
399 /// the offset of the GOT entry with the TLS index structure that contains
400 /// the module number and variable offset for the symbol. Used in the
401 /// general dynamic TLS access model.
402 /// See 'ELF Handling for Thread-Local Storage' for more details.
403 /// SYMBOL_LABEL @TLSGD
404 MO_TLSGD,
405 /// MO_TLSLD - On a symbol operand this indicates that the immediate is
406 /// the offset of the GOT entry with the TLS index for the module that
407 /// contains the symbol. When this index is passed to a call to
408 /// __tls_get_addr, the function will return the base address of the TLS
409 /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
410 /// See 'ELF Handling for Thread-Local Storage' for more details.
411 /// SYMBOL_LABEL @TLSLD
412 MO_TLSLD,
413 /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
414 /// the offset of the GOT entry with the TLS index for the module that
415 /// contains the symbol. When this index is passed to a call to
416 /// ___tls_get_addr, the function will return the base address of the TLS
417 /// block for the symbol. Used in the IA32 local dynamic TLS access model.
418 /// See 'ELF Handling for Thread-Local Storage' for more details.
419 /// SYMBOL_LABEL @TLSLDM
420 MO_TLSLDM,
421 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
422 /// the offset of the GOT entry with the thread-pointer offset for the
423 /// symbol. Used in the x86-64 initial exec TLS access model.
424 /// See 'ELF Handling for Thread-Local Storage' for more details.
425 /// SYMBOL_LABEL @GOTTPOFF
426 MO_GOTTPOFF,
427 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
428 /// the absolute address of the GOT entry with the negative thread-pointer
429 /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
430 /// model.
431 /// See 'ELF Handling for Thread-Local Storage' for more details.
432 /// SYMBOL_LABEL @INDNTPOFF
433 MO_INDNTPOFF,
434 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
435 /// the thread-pointer offset for the symbol. Used in the x86-64 local
436 /// exec TLS access model.
437 /// See 'ELF Handling for Thread-Local Storage' for more details.
438 /// SYMBOL_LABEL @TPOFF
439 MO_TPOFF,
440 /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
441 /// the offset of the GOT entry with the TLS offset of the symbol. Used
442 /// in the local dynamic TLS access model.
443 /// See 'ELF Handling for Thread-Local Storage' for more details.
444 /// SYMBOL_LABEL @DTPOFF
445 MO_DTPOFF,
446 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
447 /// the negative thread-pointer offset for the symbol. Used in the IA32
448 /// local exec TLS access model.
449 /// See 'ELF Handling for Thread-Local Storage' for more details.
450 /// SYMBOL_LABEL @NTPOFF
451 MO_NTPOFF,
452 /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
453 /// the offset of the GOT entry with the negative thread-pointer offset for
454 /// the symbol. Used in the PIC IA32 initial exec TLS access model.
455 /// See 'ELF Handling for Thread-Local Storage' for more details.
456 /// SYMBOL_LABEL @GOTNTPOFF
457 MO_GOTNTPOFF,
458 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
459 /// reference is actually to the "__imp_FOO" symbol. This is used for
460 /// dllimport linkage on windows.
461 MO_DLLIMPORT,
462 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
463 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
464 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
465 MO_DARWIN_NONLAZY,
466 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
467 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
468 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
469 MO_DARWIN_NONLAZY_PIC_BASE,
470 /// MO_TLVP - On a symbol operand this indicates that the immediate is
471 /// some TLS offset.
472 /// This is the TLS offset for the Darwin TLS mechanism.
473 MO_TLVP,
474 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
475 /// is some TLS offset from the picbase.
476 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
477 MO_TLVP_PIC_BASE,
478 /// MO_SECREL - On a symbol operand this indicates that the immediate is
479 /// the offset from beginning of section.
480 /// This is the TLS offset for the COFF/Windows TLS mechanism.
481 MO_SECREL,
482 /// MO_ABS8 - On a symbol operand this indicates that the symbol is known
483 /// to be an absolute symbol in range [0,128), so we can use the @ABS8
484 /// symbol modifier.
485 MO_ABS8,
486 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
487 /// reference is actually to the ".refptr.FOO" symbol. This is used for
488 /// stub symbols on windows.
489 MO_COFFSTUB,
490};
491
492enum : uint64_t {
493 //===------------------------------------------------------------------===//
494 // Instruction encodings. These are the standard/most common forms for X86
495 // instructions.
496 //
497 /// PseudoFrm - This represents an instruction that is a pseudo instruction
498 /// or one that has not been implemented yet. It is illegal to code generate
499 /// it, but tolerated for intermediate implementation stages.
500 Pseudo = 0,
501 /// Raw - This form is for instructions that don't have any operands, so
502 /// they are just a fixed opcode value, like 'leave'.
503 RawFrm = 1,
504 /// AddRegFrm - This form is used for instructions like 'push r32' that have
505 /// their one register operand added to their opcode.
506 AddRegFrm = 2,
507 /// RawFrmMemOffs - This form is for instructions that store an absolute
508 /// memory offset as an immediate with a possible segment override.
509 RawFrmMemOffs = 3,
510 /// RawFrmSrc - This form is for instructions that use the source index
511 /// register SI/ESI/RSI with a possible segment override.
512 RawFrmSrc = 4,
513 /// RawFrmDst - This form is for instructions that use the destination index
514 /// register DI/EDI/RDI.
515 RawFrmDst = 5,
516 /// RawFrmDstSrc - This form is for instructions that use the source index
517 /// register SI/ESI/RSI with a possible segment override, and also the
518 /// destination index register DI/EDI/RDI.
519 RawFrmDstSrc = 6,
520 /// RawFrmImm8 - This is used for the ENTER instruction, which has two
521 /// immediates, the first of which is a 16-bit immediate (specified by
522 /// the imm encoding) and the second is a 8-bit fixed value.
523 RawFrmImm8 = 7,
524 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
525 /// immediates, the first of which is a 16 or 32-bit immediate (specified by
526 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
527 /// manual, this operand is described as pntr16:32 and pntr16:16
528 RawFrmImm16 = 8,
529 /// AddCCFrm - This form is used for Jcc that encode the condition code
530 /// in the lower 4 bits of the opcode.
531 AddCCFrm = 9,
532 /// PrefixByte - This form is used for instructions that represent a prefix
533 /// byte like data16 or rep.
534 PrefixByte = 10,
535 /// MRMDestRegCC - This form is used for the cfcmov instructions, which use
536 /// the Mod/RM byte to specify the operands reg(r/m) and reg(reg) and also
537 /// encodes a condition code.
538 MRMDestRegCC = 18,
539 /// MRMDestMemCC - This form is used for the cfcmov instructions, which use
540 /// the Mod/RM byte to specify the operands mem(r/m) and reg(reg) and also
541 /// encodes a condition code.
542 MRMDestMemCC = 19,
543 /// MRMDestMem4VOp3CC - This form is used for instructions that use the Mod/RM
544 /// byte to specify a destination which in this case is memory and operand 3
545 /// with VEX.VVVV, and also encodes a condition code.
546 MRMDestMem4VOp3CC = 20,
547 /// Instructions operate on a register Reg/Opcode operand not the r/m field.
548 MRMr0 = 21,
549 /// MRMSrcMem - But force to use the SIB field.
550 MRMSrcMemFSIB = 22,
551 /// MRMDestMem - But force to use the SIB field.
552 MRMDestMemFSIB = 23,
553 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
554 /// to specify a destination, which in this case is memory.
555 MRMDestMem = 24,
556 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
557 /// to specify a source, which in this case is memory.
558 MRMSrcMem = 25,
559 /// MRMSrcMem4VOp3 - This form is used for instructions that encode
560 /// operand 3 with VEX.VVVV and load from memory.
561 MRMSrcMem4VOp3 = 26,
562 /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM
563 /// byte to specify the fourth source, which in this case is memory.
564 MRMSrcMemOp4 = 27,
565 /// MRMSrcMemCC - This form is used for instructions that use the Mod/RM
566 /// byte to specify the operands and also encodes a condition code.
567 MRMSrcMemCC = 28,
568 /// MRMXm - This form is used for instructions that use the Mod/RM byte
569 /// to specify a memory source, but doesn't use the middle field. And has
570 /// a condition code.
571 MRMXmCC = 30,
572 /// MRMXm - This form is used for instructions that use the Mod/RM byte
573 /// to specify a memory source, but doesn't use the middle field.
574 MRMXm = 31,
575 /// MRM0m-MRM7m - Instructions that operate on a memory r/m operand and use
576 /// reg field to hold extended opcode, which is represented as /0, /1, ...
577 MRM0m = 32, // Format /0
578 MRM1m = 33, // Format /1
579 MRM2m = 34, // Format /2
580 MRM3m = 35, // Format /3
581 MRM4m = 36, // Format /4
582 MRM5m = 37, // Format /5
583 MRM6m = 38, // Format /6
584 MRM7m = 39, // Format /7
585 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
586 /// to specify a destination, which in this case is a register.
587 MRMDestReg = 40,
588 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
589 /// to specify a source, which in this case is a register.
590 MRMSrcReg = 41,
591 /// MRMSrcReg4VOp3 - This form is used for instructions that encode
592 /// operand 3 with VEX.VVVV and do not load from memory.
593 MRMSrcReg4VOp3 = 42,
594 /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM
595 /// byte to specify the fourth source, which in this case is a register.
596 MRMSrcRegOp4 = 43,
597 /// MRMSrcRegCC - This form is used for instructions that use the Mod/RM
598 /// byte to specify the operands and also encodes a condition code
599 MRMSrcRegCC = 44,
600 /// MRMXCCr - This form is used for instructions that use the Mod/RM byte
601 /// to specify a register source, but doesn't use the middle field. And has
602 /// a condition code.
603 MRMXrCC = 46,
604 /// MRMXr - This form is used for instructions that use the Mod/RM byte
605 /// to specify a register source, but doesn't use the middle field.
606 MRMXr = 47,
607 /// MRM0r-MRM7r - Instructions that operate on a register r/m operand and use
608 /// reg field to hold extended opcode, which is represented as /0, /1, ...
609 MRM0r = 48, // Format /0
610 MRM1r = 49, // Format /1
611 MRM2r = 50, // Format /2
612 MRM3r = 51, // Format /3
613 MRM4r = 52, // Format /4
614 MRM5r = 53, // Format /5
615 MRM6r = 54, // Format /6
616 MRM7r = 55, // Format /7
617 /// MRM0X-MRM7X - Instructions that operate that have mod=11 and an opcode but
618 /// ignore r/m.
619 MRM0X = 56, // Format /0
620 MRM1X = 57, // Format /1
621 MRM2X = 58, // Format /2
622 MRM3X = 59, // Format /3
623 MRM4X = 60, // Format /4
624 MRM5X = 61, // Format /5
625 MRM6X = 62, // Format /6
626 MRM7X = 63, // Format /7
627 /// MRM_XX (XX: C0-FF)- A mod/rm byte of exactly 0xXX.
628 MRM_C0 = 64,
629 MRM_C1 = 65,
630 MRM_C2 = 66,
631 MRM_C3 = 67,
632 MRM_C4 = 68,
633 MRM_C5 = 69,
634 MRM_C6 = 70,
635 MRM_C7 = 71,
636 MRM_C8 = 72,
637 MRM_C9 = 73,
638 MRM_CA = 74,
639 MRM_CB = 75,
640 MRM_CC = 76,
641 MRM_CD = 77,
642 MRM_CE = 78,
643 MRM_CF = 79,
644 MRM_D0 = 80,
645 MRM_D1 = 81,
646 MRM_D2 = 82,
647 MRM_D3 = 83,
648 MRM_D4 = 84,
649 MRM_D5 = 85,
650 MRM_D6 = 86,
651 MRM_D7 = 87,
652 MRM_D8 = 88,
653 MRM_D9 = 89,
654 MRM_DA = 90,
655 MRM_DB = 91,
656 MRM_DC = 92,
657 MRM_DD = 93,
658 MRM_DE = 94,
659 MRM_DF = 95,
660 MRM_E0 = 96,
661 MRM_E1 = 97,
662 MRM_E2 = 98,
663 MRM_E3 = 99,
664 MRM_E4 = 100,
665 MRM_E5 = 101,
666 MRM_E6 = 102,
667 MRM_E7 = 103,
668 MRM_E8 = 104,
669 MRM_E9 = 105,
670 MRM_EA = 106,
671 MRM_EB = 107,
672 MRM_EC = 108,
673 MRM_ED = 109,
674 MRM_EE = 110,
675 MRM_EF = 111,
676 MRM_F0 = 112,
677 MRM_F1 = 113,
678 MRM_F2 = 114,
679 MRM_F3 = 115,
680 MRM_F4 = 116,
681 MRM_F5 = 117,
682 MRM_F6 = 118,
683 MRM_F7 = 119,
684 MRM_F8 = 120,
685 MRM_F9 = 121,
686 MRM_FA = 122,
687 MRM_FB = 123,
688 MRM_FC = 124,
689 MRM_FD = 125,
690 MRM_FE = 126,
691 MRM_FF = 127,
692 FormMask = 127,
693 //===------------------------------------------------------------------===//
694 // Actual flags...
695 /// OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
696 /// OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
697 /// 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
698 /// prefix in 16-bit mode.
699 OpSizeShift = 7,
700 OpSizeMask = 0x3 << OpSizeShift,
701 OpSizeFixed = 0 << OpSizeShift,
702 OpSize16 = 1 << OpSizeShift,
703 OpSize32 = 2 << OpSizeShift,
704 /// AsSize - AdSizeX implies this instruction determines its need of 0x67
705 /// prefix from a normal ModRM memory operand. The other types indicate that
706 /// an operand is encoded with a specific width and a prefix is needed if
707 /// it differs from the current mode.
708 AdSizeShift = OpSizeShift + 2,
709 AdSizeMask = 0x3 << AdSizeShift,
710 AdSizeX = 0 << AdSizeShift,
711 AdSize16 = 1 << AdSizeShift,
712 AdSize32 = 2 << AdSizeShift,
713 AdSize64 = 3 << AdSizeShift,
714 //===------------------------------------------------------------------===//
715 /// OpPrefix - There are several prefix bytes that are used as opcode
716 /// extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
717 /// no prefix.
718 OpPrefixShift = AdSizeShift + 2,
719 OpPrefixMask = 0x3 << OpPrefixShift,
720 /// PD - Prefix code for packed double precision vector floating point
721 /// operations performed in the SSE registers.
722 PD = 1 << OpPrefixShift,
723 /// XS, XD - These prefix codes are for single and double precision scalar
724 /// floating point operations performed in the SSE registers.
725 XS = 2 << OpPrefixShift,
726 XD = 3 << OpPrefixShift,
727 //===------------------------------------------------------------------===//
728 /// OpMap - This field determines which opcode map this instruction
729 /// belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
730 OpMapShift = OpPrefixShift + 2,
731 OpMapMask = 0xF << OpMapShift,
732 /// OB - OneByte - Set if this instruction has a one byte opcode.
733 OB = 0 << OpMapShift,
734 /// TB - TwoByte - Set if this instruction has a two byte opcode, which
735 /// starts with a 0x0F byte before the real opcode.
736 TB = 1 << OpMapShift,
737 /// T8, TA - Prefix after the 0x0F prefix.
738 T8 = 2 << OpMapShift,
739 TA = 3 << OpMapShift,
740 /// XOP8 - Prefix to include use of imm byte.
741 XOP8 = 4 << OpMapShift,
742 /// XOP9 - Prefix to exclude use of imm byte.
743 XOP9 = 5 << OpMapShift,
744 /// XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
745 XOPA = 6 << OpMapShift,
746 /// ThreeDNow - This indicates that the instruction uses the
747 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
748 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
749 /// storing a classifier in the imm8 field. To simplify our implementation,
750 /// we handle this by storeing the classifier in the opcode field and using
751 /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
752 ThreeDNow = 7 << OpMapShift,
753 /// MAP4, MAP5, MAP6, MAP7 - Prefix after the 0x0F prefix.
754 T_MAP4 = 8 << OpMapShift,
755 T_MAP5 = 9 << OpMapShift,
756 T_MAP6 = 10 << OpMapShift,
757 T_MAP7 = 11 << OpMapShift,
758 //===------------------------------------------------------------------===//
759 /// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
760 /// They are used to specify GPRs and SSE registers, 64-bit operand size,
761 /// etc. We only cares about REX.W and REX.R bits and only the former is
762 /// statically determined.
763 REXShift = OpMapShift + 4,
764 REX_W = 1 << REXShift,
765 //===------------------------------------------------------------------===//
766 // This 4-bit field describes the size of an immediate operand. Zero is
767 // unused so that we can tell if we forgot to set a value.
768 ImmShift = REXShift + 1,
769 Imm8 = 1 << ImmShift,
770 Imm8PCRel = 2 << ImmShift,
771 Imm8Reg = 3 << ImmShift,
772 Imm16 = 4 << ImmShift,
773 Imm16PCRel = 5 << ImmShift,
774 Imm32 = 6 << ImmShift,
775 Imm32PCRel = 7 << ImmShift,
776 Imm32S = 8 << ImmShift,
777 Imm64 = 9 << ImmShift,
778 ImmMask = 15 << ImmShift,
779 //===------------------------------------------------------------------===//
780 /// FP Instruction Classification... Zero is non-fp instruction.
781 /// FPTypeMask - Mask for all of the FP types...
782 FPTypeShift = ImmShift + 4,
783 FPTypeMask = 7 << FPTypeShift,
784 /// NotFP - The default, set for instructions that do not use FP registers.
785 NotFP = 0 << FPTypeShift,
786 /// ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
787 ZeroArgFP = 1 << FPTypeShift,
788 /// OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
789 OneArgFP = 2 << FPTypeShift,
790 /// OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
791 /// result back to ST(0). For example, fcos, fsqrt, etc.
792 OneArgFPRW = 3 << FPTypeShift,
793 /// TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
794 /// explicit argument, storing the result to either ST(0) or the implicit
795 /// argument. For example: fadd, fsub, fmul, etc...
796 TwoArgFP = 4 << FPTypeShift,
797 /// CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
798 /// explicit argument, but have no destination. Example: fucom, fucomi, ...
799 CompareFP = 5 << FPTypeShift,
800 /// CondMovFP - "2 operand" floating point conditional move instructions.
801 CondMovFP = 6 << FPTypeShift,
802 /// SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
803 SpecialFP = 7 << FPTypeShift,
804 /// Lock prefix
805 LOCKShift = FPTypeShift + 3,
806 LOCK = 1 << LOCKShift,
807 /// REP prefix
808 REPShift = LOCKShift + 1,
809 REP = 1 << REPShift,
810 /// Execution domain for SSE instructions.
811 /// 0 means normal, non-SSE instruction.
812 SSEDomainShift = REPShift + 1,
813 /// Encoding
814 EncodingShift = SSEDomainShift + 2,
815 EncodingMask = 0x3 << EncodingShift,
816 /// LEGACY - encoding using REX/REX2 or w/o opcode prefix.
817 LEGACY = 0 << EncodingShift,
818 /// VEX - encoding using 0xC4/0xC5
819 VEX = 1 << EncodingShift,
820 /// XOP - Opcode prefix used by XOP instructions.
821 XOP = 2 << EncodingShift,
822 /// EVEX - Specifies that this instruction use EVEX form which provides
823 /// syntax support up to 32 512-bit register operands and up to 7 16-bit
824 /// mask operands as well as source operand data swizzling/memory operand
825 /// conversion, eviction hint, and rounding mode.
826 EVEX = 3 << EncodingShift,
827 /// Opcode
828 OpcodeShift = EncodingShift + 2,
829 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
830 /// address instructions in SSE are represented as 3 address ones in AVX
831 /// and the additional register is encoded in VEX_VVVV prefix.
832 VEX_4VShift = OpcodeShift + 8,
833 VEX_4V = 1ULL << VEX_4VShift,
834 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
835 /// instruction uses 256-bit wide registers. This is usually auto detected
836 /// if a VR256 register is used, but some AVX instructions also have this
837 /// field marked when using a f256 memory references.
838 VEX_LShift = VEX_4VShift + 1,
839 VEX_L = 1ULL << VEX_LShift,
840 /// EVEX_K - Set if this instruction requires masking
841 EVEX_KShift = VEX_LShift + 1,
842 EVEX_K = 1ULL << EVEX_KShift,
843 /// EVEX_Z - Set if this instruction has EVEX.Z field set.
844 EVEX_ZShift = EVEX_KShift + 1,
845 EVEX_Z = 1ULL << EVEX_ZShift,
846 /// EVEX_L2 - Set if this instruction has EVEX.L' field set.
847 EVEX_L2Shift = EVEX_ZShift + 1,
848 EVEX_L2 = 1ULL << EVEX_L2Shift,
849 /// EVEX_B - Set if this instruction has EVEX.B field set.
850 EVEX_BShift = EVEX_L2Shift + 1,
851 EVEX_B = 1ULL << EVEX_BShift,
852 /// The scaling factor for the AVX512's 8-bit compressed displacement.
853 CD8_Scale_Shift = EVEX_BShift + 1,
854 CD8_Scale_Mask = 7ULL << CD8_Scale_Shift,
855 /// Explicitly specified rounding control
856 EVEX_RCShift = CD8_Scale_Shift + 3,
857 EVEX_RC = 1ULL << EVEX_RCShift,
858 /// NOTRACK prefix
859 NoTrackShift = EVEX_RCShift + 1,
860 NOTRACK = 1ULL << NoTrackShift,
861 /// Force REX2/VEX/EVEX encoding
862 ExplicitOpPrefixShift = NoTrackShift + 1,
863 /// For instructions that require REX2 prefix even if EGPR is not used.
864 ExplicitREX2Prefix = 1ULL << ExplicitOpPrefixShift,
865 /// For instructions that use VEX encoding only when {vex}, {vex2} or {vex3}
866 /// is present.
867 ExplicitVEXPrefix = 2ULL << ExplicitOpPrefixShift,
868 /// For instructions that are promoted to EVEX space for EGPR.
869 ExplicitEVEXPrefix = 3ULL << ExplicitOpPrefixShift,
870 ExplicitOpPrefixMask = 3ULL << ExplicitOpPrefixShift,
871 /// EVEX_NF - Set if this instruction has EVEX.NF field set.
872 EVEX_NFShift = ExplicitOpPrefixShift + 2,
873 EVEX_NF = 1ULL << EVEX_NFShift,
874 // TwoConditionalOps - Set if this instruction has two conditional operands
875 TwoConditionalOps_Shift = EVEX_NFShift + 1,
876 TwoConditionalOps = 1ULL << TwoConditionalOps_Shift,
877 // EVEX_U - Set if this instruction has EVEX.U field set.
878 EVEX_UShift = TwoConditionalOps_Shift + 1,
879 EVEX_U = 1ULL << EVEX_UShift
880};
881
882/// \returns true if the instruction with given opcode is a prefix.
883inline bool isPrefix(uint64_t TSFlags) {
884 return (TSFlags & X86II::FormMask) == PrefixByte;
885}
886
887/// \returns true if the instruction with given opcode is a pseudo.
888inline bool isPseudo(uint64_t TSFlags) {
889 return (TSFlags & X86II::FormMask) == Pseudo;
890}
891
892/// \returns the "base" X86 opcode for the specified machine
893/// instruction.
894inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) {
895 return TSFlags >> X86II::OpcodeShift;
896}
897
898inline bool hasImm(uint64_t TSFlags) { return (TSFlags & X86II::ImmMask) != 0; }
899
900/// Decode the "size of immediate" field from the TSFlags field of the
901/// specified instruction.
902inline unsigned getSizeOfImm(uint64_t TSFlags) {
903 switch (TSFlags & X86II::ImmMask) {
904 default:
905 llvm_unreachable("Unknown immediate size");
906 case X86II::Imm8:
907 case X86II::Imm8PCRel:
908 case X86II::Imm8Reg:
909 return 1;
910 case X86II::Imm16:
911 case X86II::Imm16PCRel:
912 return 2;
913 case X86II::Imm32:
914 case X86II::Imm32S:
915 case X86II::Imm32PCRel:
916 return 4;
917 case X86II::Imm64:
918 return 8;
919 }
920}
921
922/// \returns true if the immediate of the specified instruction's TSFlags
923/// indicates that it is pc relative.
924inline bool isImmPCRel(uint64_t TSFlags) {
925 switch (TSFlags & X86II::ImmMask) {
926 default:
927 llvm_unreachable("Unknown immediate size");
928 case X86II::Imm8PCRel:
929 case X86II::Imm16PCRel:
930 case X86II::Imm32PCRel:
931 return true;
932 case X86II::Imm8:
933 case X86II::Imm8Reg:
934 case X86II::Imm16:
935 case X86II::Imm32:
936 case X86II::Imm32S:
937 case X86II::Imm64:
938 return false;
939 }
940}
941
942/// \returns true if the immediate of the specified instruction's
943/// TSFlags indicates that it is signed.
944inline bool isImmSigned(uint64_t TSFlags) {
945 switch (TSFlags & X86II::ImmMask) {
946 default:
947 llvm_unreachable("Unknown immediate signedness");
948 case X86II::Imm32S:
949 return true;
950 case X86II::Imm8:
951 case X86II::Imm8PCRel:
952 case X86II::Imm8Reg:
953 case X86II::Imm16:
954 case X86II::Imm16PCRel:
955 case X86II::Imm32:
956 case X86II::Imm32PCRel:
957 case X86II::Imm64:
958 return false;
959 }
960}
961
962/// Compute whether all of the def operands are repeated in the uses and
963/// therefore should be skipped.
964/// This determines the start of the unique operand list. We need to determine
965/// if all of the defs have a corresponding tied operand in the uses.
966/// Unfortunately, the tied operand information is encoded in the uses not
967/// the defs so we have to use some heuristics to find which operands to
968/// query.
969inline unsigned getOperandBias(const MCInstrDesc &Desc) {
970 unsigned NumDefs = Desc.getNumDefs();
971 unsigned NumOps = Desc.getNumOperands();
972 switch (NumDefs) {
973 default:
974 llvm_unreachable("Unexpected number of defs");
975 case 0:
976 return 0;
977 case 1:
978 // Common two addr case.
979 if (NumOps > 1 && Desc.getOperandConstraint(OpNum: 1, Constraint: MCOI::TIED_TO) == 0)
980 return 1;
981 // Check for AVX-512 scatter which has a TIED_TO in the second to last
982 // operand.
983 if (NumOps == 8 && Desc.getOperandConstraint(OpNum: 6, Constraint: MCOI::TIED_TO) == 0)
984 return 1;
985 return 0;
986 case 2:
987 // XCHG/XADD have two destinations and two sources.
988 if (NumOps >= 4 && Desc.getOperandConstraint(OpNum: 2, Constraint: MCOI::TIED_TO) == 0 &&
989 Desc.getOperandConstraint(OpNum: 3, Constraint: MCOI::TIED_TO) == 1)
990 return 2;
991 // Check for gather. AVX-512 has the second tied operand early. AVX2
992 // has it as the last op.
993 if (NumOps == 9 && Desc.getOperandConstraint(OpNum: 2, Constraint: MCOI::TIED_TO) == 0 &&
994 (Desc.getOperandConstraint(OpNum: 3, Constraint: MCOI::TIED_TO) == 1 ||
995 Desc.getOperandConstraint(OpNum: 8, Constraint: MCOI::TIED_TO) == 1))
996 return 2;
997 return 0;
998 }
999}
1000
1001/// \returns true if the instruction has a NDD (new data destination).
1002inline bool hasNewDataDest(uint64_t TSFlags) {
1003 return (TSFlags & X86II::OpMapMask) == X86II::T_MAP4 &&
1004 (TSFlags & X86II::EVEX_B) && (TSFlags & X86II::VEX_4V);
1005}
1006
1007/// \returns operand # for the first field of the memory operand or -1 if no
1008/// memory operands.
1009/// NOTE: This ignores tied operands. If there is a tied register which is
1010/// duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only counted
1011/// as one operand.
1012inline int getMemoryOperandNo(uint64_t TSFlags) {
1013 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1014 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1015
1016 switch (TSFlags & X86II::FormMask) {
1017 default:
1018 llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
1019 case X86II::Pseudo:
1020 case X86II::RawFrm:
1021 case X86II::AddRegFrm:
1022 case X86II::RawFrmImm8:
1023 case X86II::RawFrmImm16:
1024 case X86II::RawFrmMemOffs:
1025 case X86II::RawFrmSrc:
1026 case X86II::RawFrmDst:
1027 case X86II::RawFrmDstSrc:
1028 case X86II::AddCCFrm:
1029 case X86II::PrefixByte:
1030 return -1;
1031 case X86II::MRMDestMem:
1032 case X86II::MRMDestMemFSIB:
1033 case X86II::MRMDestMemCC:
1034 return hasNewDataDest(TSFlags);
1035 case X86II::MRMSrcMem:
1036 case X86II::MRMSrcMemFSIB:
1037 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
1038 // mask register.
1039 return 1 + HasVEX_4V + HasEVEX_K;
1040 case X86II::MRMSrcMem4VOp3:
1041 // Skip registers encoded in reg.
1042 return 1 + HasEVEX_K;
1043 case X86II::MRMSrcMemOp4:
1044 // Skip registers encoded in reg, VEX_VVVV, and I8IMM.
1045 return 3;
1046 case X86II::MRMSrcMemCC:
1047 return 1 + hasNewDataDest(TSFlags);
1048 case X86II::MRMDestMem4VOp3CC:
1049 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
1050 // mask register.
1051 return 1;
1052 case X86II::MRMDestReg:
1053 case X86II::MRMDestRegCC:
1054 case X86II::MRMSrcReg:
1055 case X86II::MRMSrcReg4VOp3:
1056 case X86II::MRMSrcRegOp4:
1057 case X86II::MRMSrcRegCC:
1058 case X86II::MRMXrCC:
1059 case X86II::MRMr0:
1060 case X86II::MRMXr:
1061 case X86II::MRM0r:
1062 case X86II::MRM1r:
1063 case X86II::MRM2r:
1064 case X86II::MRM3r:
1065 case X86II::MRM4r:
1066 case X86II::MRM5r:
1067 case X86II::MRM6r:
1068 case X86II::MRM7r:
1069 return -1;
1070 case X86II::MRM0X:
1071 case X86II::MRM1X:
1072 case X86II::MRM2X:
1073 case X86II::MRM3X:
1074 case X86II::MRM4X:
1075 case X86II::MRM5X:
1076 case X86II::MRM6X:
1077 case X86II::MRM7X:
1078 return -1;
1079 case X86II::MRMXmCC:
1080 case X86II::MRMXm:
1081 case X86II::MRM0m:
1082 case X86II::MRM1m:
1083 case X86II::MRM2m:
1084 case X86II::MRM3m:
1085 case X86II::MRM4m:
1086 case X86II::MRM5m:
1087 case X86II::MRM6m:
1088 case X86II::MRM7m:
1089 // Start from 0, skip registers encoded in VEX_VVVV or a mask register.
1090 return 0 + HasVEX_4V + HasEVEX_K;
1091 case X86II::MRM_C0:
1092 case X86II::MRM_C1:
1093 case X86II::MRM_C2:
1094 case X86II::MRM_C3:
1095 case X86II::MRM_C4:
1096 case X86II::MRM_C5:
1097 case X86II::MRM_C6:
1098 case X86II::MRM_C7:
1099 case X86II::MRM_C8:
1100 case X86II::MRM_C9:
1101 case X86II::MRM_CA:
1102 case X86II::MRM_CB:
1103 case X86II::MRM_CC:
1104 case X86II::MRM_CD:
1105 case X86II::MRM_CE:
1106 case X86II::MRM_CF:
1107 case X86II::MRM_D0:
1108 case X86II::MRM_D1:
1109 case X86II::MRM_D2:
1110 case X86II::MRM_D3:
1111 case X86II::MRM_D4:
1112 case X86II::MRM_D5:
1113 case X86II::MRM_D6:
1114 case X86II::MRM_D7:
1115 case X86II::MRM_D8:
1116 case X86II::MRM_D9:
1117 case X86II::MRM_DA:
1118 case X86II::MRM_DB:
1119 case X86II::MRM_DC:
1120 case X86II::MRM_DD:
1121 case X86II::MRM_DE:
1122 case X86II::MRM_DF:
1123 case X86II::MRM_E0:
1124 case X86II::MRM_E1:
1125 case X86II::MRM_E2:
1126 case X86II::MRM_E3:
1127 case X86II::MRM_E4:
1128 case X86II::MRM_E5:
1129 case X86II::MRM_E6:
1130 case X86II::MRM_E7:
1131 case X86II::MRM_E8:
1132 case X86II::MRM_E9:
1133 case X86II::MRM_EA:
1134 case X86II::MRM_EB:
1135 case X86II::MRM_EC:
1136 case X86II::MRM_ED:
1137 case X86II::MRM_EE:
1138 case X86II::MRM_EF:
1139 case X86II::MRM_F0:
1140 case X86II::MRM_F1:
1141 case X86II::MRM_F2:
1142 case X86II::MRM_F3:
1143 case X86II::MRM_F4:
1144 case X86II::MRM_F5:
1145 case X86II::MRM_F6:
1146 case X86II::MRM_F7:
1147 case X86II::MRM_F8:
1148 case X86II::MRM_F9:
1149 case X86II::MRM_FA:
1150 case X86II::MRM_FB:
1151 case X86II::MRM_FC:
1152 case X86II::MRM_FD:
1153 case X86II::MRM_FE:
1154 case X86II::MRM_FF:
1155 return -1;
1156 }
1157}
1158
1159/// \returns the operand index for the first field of the memory operand,
1160/// adjusted with getOperandBias(), or -1 if the instruction has no memory
1161/// operands.
1162inline int getMemoryOperandIdx(const MCInstrDesc &Desc) {
1163 int MemRefIdx = getMemoryOperandNo(TSFlags: Desc.TSFlags);
1164 if (MemRefIdx < 0)
1165 return -1;
1166 return MemRefIdx + getOperandBias(Desc);
1167}
1168
1169/// Determine if this immediate can fit in a disp8 or a compressed disp8 for
1170/// EVEX instructions. \p will be set to the value to pass to the ImmOffset
1171/// parameter of emitImmediate.
1172inline bool isDispOrCDisp8(uint64_t TSFlags, int64_t Value,
1173 int *ImmOffset = nullptr) {
1174 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
1175
1176 unsigned CD8_Scale =
1177 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift;
1178 CD8_Scale = CD8_Scale ? 1U << (CD8_Scale - 1) : 0U;
1179 if (!HasEVEX || !CD8_Scale)
1180 return isInt<8>(x: Value);
1181
1182 assert(isPowerOf2_32(CD8_Scale) && "Unexpected CD8 scale!");
1183 if (Value & (CD8_Scale - 1)) // Unaligned offset
1184 return false;
1185
1186 int64_t CDisp8 = Value / static_cast<int64_t>(CD8_Scale);
1187 if (!isInt<8>(x: CDisp8))
1188 return false;
1189
1190 // ImmOffset will be added to Value in emitImmediate leaving just CDisp8.
1191 if (ImmOffset)
1192 *ImmOffset = CDisp8 - Value;
1193 return true;
1194}
1195
1196/// \returns true if the register is a XMM.
1197inline bool isXMMReg(MCRegister Reg) {
1198 static_assert(X86::XMM15 - X86::XMM0 == 15,
1199 "XMM0-15 registers are not continuous");
1200 static_assert(X86::XMM31 - X86::XMM16 == 15,
1201 "XMM16-31 registers are not continuous");
1202 return (Reg >= X86::XMM0 && Reg <= X86::XMM15) ||
1203 (Reg >= X86::XMM16 && Reg <= X86::XMM31);
1204}
1205
1206/// \returns true if the register is a YMM.
1207inline bool isYMMReg(MCRegister Reg) {
1208 static_assert(X86::YMM15 - X86::YMM0 == 15,
1209 "YMM0-15 registers are not continuous");
1210 static_assert(X86::YMM31 - X86::YMM16 == 15,
1211 "YMM16-31 registers are not continuous");
1212 return (Reg >= X86::YMM0 && Reg <= X86::YMM15) ||
1213 (Reg >= X86::YMM16 && Reg <= X86::YMM31);
1214}
1215
1216/// \returns true if the register is a ZMM.
1217inline bool isZMMReg(MCRegister Reg) {
1218 static_assert(X86::ZMM31 - X86::ZMM0 == 31,
1219 "ZMM registers are not continuous");
1220 return Reg >= X86::ZMM0 && Reg <= X86::ZMM31;
1221}
1222
1223/// \returns true if \p Reg is an apx extended register.
1224inline bool isApxExtendedReg(MCRegister Reg) {
1225 static_assert(X86::R31WH - X86::R16 == 95, "EGPRs are not continuous");
1226 return Reg >= X86::R16 && Reg <= X86::R31WH;
1227}
1228
1229/// \returns true if the MachineOperand is a x86-64 extended (r8 or
1230/// higher) register, e.g. r8, xmm8, xmm13, etc.
1231inline bool isX86_64ExtendedReg(MCRegister Reg) {
1232 if ((Reg >= X86::XMM8 && Reg <= X86::XMM15) ||
1233 (Reg >= X86::XMM16 && Reg <= X86::XMM31) ||
1234 (Reg >= X86::YMM8 && Reg <= X86::YMM15) ||
1235 (Reg >= X86::YMM16 && Reg <= X86::YMM31) ||
1236 (Reg >= X86::ZMM8 && Reg <= X86::ZMM31))
1237 return true;
1238
1239 if (isApxExtendedReg(Reg))
1240 return true;
1241
1242 switch (Reg.id()) {
1243 default:
1244 break;
1245 case X86::R8:
1246 case X86::R9:
1247 case X86::R10:
1248 case X86::R11:
1249 case X86::R12:
1250 case X86::R13:
1251 case X86::R14:
1252 case X86::R15:
1253 case X86::R8D:
1254 case X86::R9D:
1255 case X86::R10D:
1256 case X86::R11D:
1257 case X86::R12D:
1258 case X86::R13D:
1259 case X86::R14D:
1260 case X86::R15D:
1261 case X86::R8W:
1262 case X86::R9W:
1263 case X86::R10W:
1264 case X86::R11W:
1265 case X86::R12W:
1266 case X86::R13W:
1267 case X86::R14W:
1268 case X86::R15W:
1269 case X86::R8B:
1270 case X86::R9B:
1271 case X86::R10B:
1272 case X86::R11B:
1273 case X86::R12B:
1274 case X86::R13B:
1275 case X86::R14B:
1276 case X86::R15B:
1277 case X86::CR8:
1278 case X86::CR9:
1279 case X86::CR10:
1280 case X86::CR11:
1281 case X86::CR12:
1282 case X86::CR13:
1283 case X86::CR14:
1284 case X86::CR15:
1285 case X86::DR8:
1286 case X86::DR9:
1287 case X86::DR10:
1288 case X86::DR11:
1289 case X86::DR12:
1290 case X86::DR13:
1291 case X86::DR14:
1292 case X86::DR15:
1293 return true;
1294 }
1295 return false;
1296}
1297
1298inline bool canUseApxExtendedReg(const MCInstrDesc &Desc) {
1299 uint64_t TSFlags = Desc.TSFlags;
1300 uint64_t Encoding = TSFlags & EncodingMask;
1301 // EVEX can always use egpr.
1302 if (Encoding == X86II::EVEX)
1303 return true;
1304
1305 unsigned Opcode = Desc.Opcode;
1306 if (isPseudo(TSFlags)) {
1307 switch (Opcode) {
1308 default:
1309 // To be conservative, egpr is not used for all pseudo instructions
1310 // because we are not sure what instruction it will become.
1311 // FIXME: Could we improve it in X86ExpandPseudo?
1312 return false;
1313 case X86::MOV32r0:
1314 case X86::MOV32r1:
1315 case X86::MOV32r_1:
1316 // They are always expanded to XOR32rr.
1317 return true;
1318 case X86::MOV32ri64:
1319 // MOV32ri64 is always expanded to MOV32ri.
1320 return true;
1321 case X86::ADD8rr_DB:
1322 case X86::ADD16rr_DB:
1323 case X86::ADD32rr_DB:
1324 case X86::ADD64rr_DB:
1325 // They are always expanded to ORNrr.
1326 return true;
1327 case X86::ADD8ri_DB:
1328 case X86::ADD16ri_DB:
1329 case X86::ADD32ri_DB:
1330 case X86::ADD64ri32_DB:
1331 // They are always expanded to ORNri.
1332 return true;
1333 }
1334 }
1335
1336 // MAP OB/TB in legacy encoding space can always use egpr except
1337 // XSAVE*/XRSTOR*.
1338 switch (Opcode) {
1339 default:
1340 break;
1341 case X86::XSAVE:
1342 case X86::XSAVE64:
1343 case X86::XSAVEOPT:
1344 case X86::XSAVEOPT64:
1345 case X86::XSAVEC:
1346 case X86::XSAVEC64:
1347 case X86::XSAVES:
1348 case X86::XSAVES64:
1349 case X86::XRSTOR:
1350 case X86::XRSTOR64:
1351 case X86::XRSTORS:
1352 case X86::XRSTORS64:
1353 return false;
1354 }
1355 uint64_t OpMap = TSFlags & X86II::OpMapMask;
1356 return !Encoding && (OpMap == X86II::OB || OpMap == X86II::TB);
1357}
1358
1359/// \returns true if the MemoryOperand is a 32 extended (zmm16 or higher)
1360/// registers, e.g. zmm21, etc.
1361static inline bool is32ExtendedReg(MCRegister Reg) {
1362 return ((Reg >= X86::XMM16 && Reg <= X86::XMM31) ||
1363 (Reg >= X86::YMM16 && Reg <= X86::YMM31) ||
1364 (Reg >= X86::ZMM16 && Reg <= X86::ZMM31));
1365}
1366
1367inline bool isX86_64NonExtLowByteReg(MCRegister Reg) {
1368 return (Reg == X86::SPL || Reg == X86::BPL || Reg == X86::SIL ||
1369 Reg == X86::DIL);
1370}
1371
1372/// \returns true if this is a masked instruction.
1373inline bool isKMasked(uint64_t TSFlags) {
1374 return (TSFlags & X86II::EVEX_K) != 0;
1375}
1376
1377/// \returns true if this is a merge masked instruction.
1378inline bool isKMergeMasked(uint64_t TSFlags) {
1379 return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0;
1380}
1381
1382/// \returns true if the intruction needs a SIB.
1383inline bool needSIB(MCRegister BaseReg, MCRegister IndexReg, bool In64BitMode) {
1384 // The SIB byte must be used if there is an index register.
1385 if (IndexReg)
1386 return true;
1387
1388 // The SIB byte must be used if the base is ESP/RSP/R12/R20/R28, all of
1389 // which encode to an R/M value of 4, which indicates that a SIB byte is
1390 // present.
1391 switch (BaseReg.id()) {
1392 default:
1393 // If there is no base register and we're in 64-bit mode, we need a SIB
1394 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
1395 return In64BitMode && !BaseReg;
1396 case X86::ESP:
1397 case X86::RSP:
1398 case X86::R12:
1399 case X86::R12D:
1400 case X86::R20:
1401 case X86::R20D:
1402 case X86::R28:
1403 case X86::R28D:
1404 return true;
1405 }
1406}
1407
1408} // namespace X86II
1409} // namespace llvm
1410#endif
1411