1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Calling Convention Implementation Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_CALLING_CONV_IMPL
10#undef GET_CALLING_CONV_IMPL
11
12static bool CC_XCore(unsigned ValNo, MVT ValVT,
13 MVT LocVT, CCValAssign::LocInfo LocInfo,
14 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
15static bool RetCC_XCore(unsigned ValNo, MVT ValVT,
16 MVT LocVT, CCValAssign::LocInfo LocInfo,
17 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State);
18
19
20static bool CC_XCore(unsigned ValNo, MVT ValVT,
21 MVT LocVT, CCValAssign::LocInfo LocInfo,
22 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
23
24 if (LocVT == MVT::i8 ||
25 LocVT == MVT::i16) {
26 LocVT = MVT::i32;
27 if (ArgFlags.isSExt())
28 LocInfo = CCValAssign::SExt;
29 else if (ArgFlags.isZExt())
30 LocInfo = CCValAssign::ZExt;
31 else
32 LocInfo = CCValAssign::AExt;
33 }
34
35 if (ArgFlags.isNest()) {
36 if (MCRegister Reg = State.AllocateReg(Reg: XCore::R11)) {
37 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
38 return false;
39 }
40 }
41
42 if (LocVT == MVT::i32) {
43 static const MCPhysReg RegList1[] = {
44 XCore::R0, XCore::R1, XCore::R2, XCore::R3
45 };
46 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
47 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
48 return false;
49 }
50 }
51
52 if (LocVT == MVT::i32) {
53 int64_t Offset2 = State.AllocateStack(Size: 4, Alignment: Align(4));
54 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
55 return false;
56 }
57
58 return true; // CC didn't match.
59}
60
61
62static bool RetCC_XCore(unsigned ValNo, MVT ValVT,
63 MVT LocVT, CCValAssign::LocInfo LocInfo,
64 ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State) {
65
66 if (LocVT == MVT::i32) {
67 static const MCPhysReg RegList1[] = {
68 XCore::R0, XCore::R1, XCore::R2, XCore::R3
69 };
70 if (MCRegister Reg = State.AllocateReg(Regs: RegList1)) {
71 State.addLoc(V: CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, HTP: LocInfo));
72 return false;
73 }
74 }
75
76 if (LocVT == MVT::i32) {
77 int64_t Offset2 = State.AllocateStack(Size: 4, Alignment: Align(4));
78 State.addLoc(V: CCValAssign::getMem(ValNo, ValVT, Offset: Offset2, LocVT, HTP: LocInfo));
79 return false;
80 }
81
82 return true; // CC didn't match.
83}
84
85#endif // GET_CALLING_CONV_IMPL
86
87#ifdef GET_CC_REGISTER_LISTS
88#undef GET_CC_REGISTER_LISTS
89
90const MCRegister CC_XCore_ArgRegs[] = { XCore::R0, XCore::R1, XCore::R11, XCore::R2, XCore::R3 };
91const MCRegister RetCC_XCore_ArgRegs[] = { XCore::R0, XCore::R1, XCore::R2, XCore::R3 };
92
93#endif // GET_CC_REGISTER_LISTS
94
95