1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t XCoreRegDiffLists[] = {
12 /* 0 */ 0,
13};
14
15extern const LaneBitmask XCoreLaneMaskLists[] = {
16 /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
17};
18
19extern const uint16_t XCoreSubRegIdxLists[] = {
20 /* 0 */
21 /* dummy */ 0
22};
23
24
25#ifdef __GNUC__
26#pragma GCC diagnostic push
27#pragma GCC diagnostic ignored "-Woverlength-strings"
28#endif
29extern const char XCoreRegStrings[] = {
30 /* 0 */ "R10\000"
31 /* 4 */ "R0\000"
32 /* 7 */ "R11\000"
33 /* 11 */ "R1\000"
34 /* 14 */ "R2\000"
35 /* 17 */ "R3\000"
36 /* 20 */ "R4\000"
37 /* 23 */ "R5\000"
38 /* 26 */ "R6\000"
39 /* 29 */ "R7\000"
40 /* 32 */ "R8\000"
41 /* 35 */ "R9\000"
42 /* 38 */ "CP\000"
43 /* 41 */ "DP\000"
44 /* 44 */ "SP\000"
45 /* 47 */ "LR\000"
46};
47#ifdef __GNUC__
48#pragma GCC diagnostic pop
49#endif
50
51extern const MCRegisterDesc XCoreRegDesc[] = { // Descriptors
52 { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
53 { .Name: 38, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
54 { .Name: 41, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 1, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
55 { .Name: 47, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 2, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
56 { .Name: 44, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 3, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
57 { .Name: 4, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 4, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
58 { .Name: 11, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 5, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
59 { .Name: 14, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 6, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
60 { .Name: 17, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 7, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
61 { .Name: 20, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 8, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
62 { .Name: 23, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 9, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
63 { .Name: 26, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 10, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
64 { .Name: 29, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 11, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
65 { .Name: 32, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 12, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
66 { .Name: 35, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 13, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
67 { .Name: 0, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 14, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
68 { .Name: 7, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 15, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
69};
70
71extern const MCPhysReg XCoreRegUnitRoots[][2] = {
72 { XCore::CP },
73 { XCore::DP },
74 { XCore::LR },
75 { XCore::SP },
76 { XCore::R0 },
77 { XCore::R1 },
78 { XCore::R2 },
79 { XCore::R3 },
80 { XCore::R4 },
81 { XCore::R5 },
82 { XCore::R6 },
83 { XCore::R7 },
84 { XCore::R8 },
85 { XCore::R9 },
86 { XCore::R10 },
87 { XCore::R11 },
88};
89
90namespace { // Register classes...
91 // RRegs Register Class...
92 const MCPhysReg RRegs[] = {
93 XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::R11, XCore::CP, XCore::DP, XCore::SP, XCore::LR,
94 };
95
96 // RRegs Bit set.
97 const uint8_t RRegsBits[] = {
98 0xfe, 0xff, 0x01,
99 };
100
101 // GRRegs Register Class...
102 const MCPhysReg GRRegs[] = {
103 XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::R11,
104 };
105
106 // GRRegs Bit set.
107 const uint8_t GRRegsBits[] = {
108 0xe0, 0xff, 0x01,
109 };
110
111} // end anonymous namespace
112
113
114#ifdef __GNUC__
115#pragma GCC diagnostic push
116#pragma GCC diagnostic ignored "-Woverlength-strings"
117#endif
118extern const char XCoreRegClassStrings[] = {
119 /* 0 */ "GRRegs\000"
120};
121#ifdef __GNUC__
122#pragma GCC diagnostic pop
123#endif
124
125extern const MCRegisterClass XCoreMCRegisterClasses[] = {
126 { .RegsBegin: RRegs, .RegSet: RRegsBits, .NameIdx: 1, .RegsSize: 16, .RegSetSize: sizeof(RRegsBits), .ID: XCore::RRegsRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
127 { .RegsBegin: GRRegs, .RegSet: GRRegsBits, .NameIdx: 0, .RegsSize: 12, .RegSetSize: sizeof(GRRegsBits), .ID: XCore::GRRegsRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
128};
129
130// XCore Dwarf<->LLVM register mappings.
131extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[] = {
132 { .FromReg: 0U, .ToReg: XCore::R0 },
133 { .FromReg: 1U, .ToReg: XCore::R1 },
134 { .FromReg: 2U, .ToReg: XCore::R2 },
135 { .FromReg: 3U, .ToReg: XCore::R3 },
136 { .FromReg: 4U, .ToReg: XCore::R4 },
137 { .FromReg: 5U, .ToReg: XCore::R5 },
138 { .FromReg: 6U, .ToReg: XCore::R6 },
139 { .FromReg: 7U, .ToReg: XCore::R7 },
140 { .FromReg: 8U, .ToReg: XCore::R8 },
141 { .FromReg: 9U, .ToReg: XCore::R9 },
142 { .FromReg: 10U, .ToReg: XCore::R10 },
143 { .FromReg: 11U, .ToReg: XCore::R11 },
144 { .FromReg: 12U, .ToReg: XCore::CP },
145 { .FromReg: 13U, .ToReg: XCore::DP },
146 { .FromReg: 14U, .ToReg: XCore::SP },
147 { .FromReg: 15U, .ToReg: XCore::LR },
148};
149extern const unsigned XCoreDwarfFlavour0Dwarf2LSize = std::size(XCoreDwarfFlavour0Dwarf2L);
150
151extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[] = {
152 { .FromReg: 0U, .ToReg: XCore::R0 },
153 { .FromReg: 1U, .ToReg: XCore::R1 },
154 { .FromReg: 2U, .ToReg: XCore::R2 },
155 { .FromReg: 3U, .ToReg: XCore::R3 },
156 { .FromReg: 4U, .ToReg: XCore::R4 },
157 { .FromReg: 5U, .ToReg: XCore::R5 },
158 { .FromReg: 6U, .ToReg: XCore::R6 },
159 { .FromReg: 7U, .ToReg: XCore::R7 },
160 { .FromReg: 8U, .ToReg: XCore::R8 },
161 { .FromReg: 9U, .ToReg: XCore::R9 },
162 { .FromReg: 10U, .ToReg: XCore::R10 },
163 { .FromReg: 11U, .ToReg: XCore::R11 },
164 { .FromReg: 12U, .ToReg: XCore::CP },
165 { .FromReg: 13U, .ToReg: XCore::DP },
166 { .FromReg: 14U, .ToReg: XCore::SP },
167 { .FromReg: 15U, .ToReg: XCore::LR },
168};
169extern const unsigned XCoreEHFlavour0Dwarf2LSize = std::size(XCoreEHFlavour0Dwarf2L);
170
171extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[] = {
172 { .FromReg: XCore::CP, .ToReg: 12U },
173 { .FromReg: XCore::DP, .ToReg: 13U },
174 { .FromReg: XCore::LR, .ToReg: 15U },
175 { .FromReg: XCore::SP, .ToReg: 14U },
176 { .FromReg: XCore::R0, .ToReg: 0U },
177 { .FromReg: XCore::R1, .ToReg: 1U },
178 { .FromReg: XCore::R2, .ToReg: 2U },
179 { .FromReg: XCore::R3, .ToReg: 3U },
180 { .FromReg: XCore::R4, .ToReg: 4U },
181 { .FromReg: XCore::R5, .ToReg: 5U },
182 { .FromReg: XCore::R6, .ToReg: 6U },
183 { .FromReg: XCore::R7, .ToReg: 7U },
184 { .FromReg: XCore::R8, .ToReg: 8U },
185 { .FromReg: XCore::R9, .ToReg: 9U },
186 { .FromReg: XCore::R10, .ToReg: 10U },
187 { .FromReg: XCore::R11, .ToReg: 11U },
188};
189extern const unsigned XCoreDwarfFlavour0L2DwarfSize = std::size(XCoreDwarfFlavour0L2Dwarf);
190
191extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[] = {
192 { .FromReg: XCore::CP, .ToReg: 12U },
193 { .FromReg: XCore::DP, .ToReg: 13U },
194 { .FromReg: XCore::LR, .ToReg: 15U },
195 { .FromReg: XCore::SP, .ToReg: 14U },
196 { .FromReg: XCore::R0, .ToReg: 0U },
197 { .FromReg: XCore::R1, .ToReg: 1U },
198 { .FromReg: XCore::R2, .ToReg: 2U },
199 { .FromReg: XCore::R3, .ToReg: 3U },
200 { .FromReg: XCore::R4, .ToReg: 4U },
201 { .FromReg: XCore::R5, .ToReg: 5U },
202 { .FromReg: XCore::R6, .ToReg: 6U },
203 { .FromReg: XCore::R7, .ToReg: 7U },
204 { .FromReg: XCore::R8, .ToReg: 8U },
205 { .FromReg: XCore::R9, .ToReg: 9U },
206 { .FromReg: XCore::R10, .ToReg: 10U },
207 { .FromReg: XCore::R11, .ToReg: 11U },
208};
209extern const unsigned XCoreEHFlavour0L2DwarfSize = std::size(XCoreEHFlavour0L2Dwarf);
210
211extern const uint16_t XCoreRegEncodingTable[] = {
212 0,
213 0,
214 0,
215 0,
216 0,
217 0,
218 0,
219 0,
220 0,
221 0,
222 0,
223 0,
224 0,
225 0,
226 0,
227 0,
228 0,
229};
230static inline void InitXCoreMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
231 RI->InitMCRegisterInfo(D: XCoreRegDesc, NR: 17, RA, PC, C: XCoreMCRegisterClasses, NC: 2, RURoots: XCoreRegUnitRoots, NRU: 16, DL: XCoreRegDiffLists, RUMS: XCoreLaneMaskLists, Strings: XCoreRegStrings, ClassStrings: XCoreRegClassStrings, SubIndices: XCoreSubRegIdxLists, NumIndices: 1,
232RET: XCoreRegEncodingTable);
233
234 switch (DwarfFlavour) {
235 default:
236 llvm_unreachable("Unknown DWARF flavour");
237 case 0:
238 RI->mapDwarfRegsToLLVMRegs(Map: XCoreDwarfFlavour0Dwarf2L, Size: XCoreDwarfFlavour0Dwarf2LSize, isEH: false);
239 break;
240 }
241 switch (EHFlavour) {
242 default:
243 llvm_unreachable("Unknown DWARF flavour");
244 case 0:
245 RI->mapDwarfRegsToLLVMRegs(Map: XCoreEHFlavour0Dwarf2L, Size: XCoreEHFlavour0Dwarf2LSize, isEH: true);
246 break;
247 }
248 switch (DwarfFlavour) {
249 default:
250 llvm_unreachable("Unknown DWARF flavour");
251 case 0:
252 RI->mapLLVMRegsToDwarfRegs(Map: XCoreDwarfFlavour0L2Dwarf, Size: XCoreDwarfFlavour0L2DwarfSize, isEH: false);
253 break;
254 }
255 switch (EHFlavour) {
256 default:
257 llvm_unreachable("Unknown DWARF flavour");
258 case 0:
259 RI->mapLLVMRegsToDwarfRegs(Map: XCoreEHFlavour0L2Dwarf, Size: XCoreEHFlavour0L2DwarfSize, isEH: true);
260 break;
261 }
262}
263
264} // end namespace llvm
265
266