1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t XCoreRegDiffLists[] = {
12 /* 0 */ 0,
13};
14
15extern const LaneBitmask XCoreLaneMaskLists[] = {
16 /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
17};
18
19extern const uint16_t XCoreSubRegIdxLists[] = {
20 /* 0 */
21 /* dummy */ 0
22};
23
24
25#ifdef __GNUC__
26#pragma GCC diagnostic push
27#pragma GCC diagnostic ignored "-Woverlength-strings"
28#endif
29extern const char XCoreRegStrings[] = {
30 /* 0 */ "R10\000"
31 /* 4 */ "R0\000"
32 /* 7 */ "R11\000"
33 /* 11 */ "R1\000"
34 /* 14 */ "R2\000"
35 /* 17 */ "R3\000"
36 /* 20 */ "R4\000"
37 /* 23 */ "R5\000"
38 /* 26 */ "R6\000"
39 /* 29 */ "R7\000"
40 /* 32 */ "R8\000"
41 /* 35 */ "R9\000"
42 /* 38 */ "CP\000"
43 /* 41 */ "DP\000"
44 /* 44 */ "SP\000"
45 /* 47 */ "LR\000"
46};
47#ifdef __GNUC__
48#pragma GCC diagnostic pop
49#endif
50
51extern const MCRegisterDesc XCoreRegDesc[] = { // Descriptors
52 { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
53 { .Name: 38, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
54 { .Name: 41, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 1, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
55 { .Name: 47, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 2, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
56 { .Name: 44, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 3, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
57 { .Name: 4, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 4, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
58 { .Name: 11, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 5, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
59 { .Name: 14, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 6, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
60 { .Name: 17, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 7, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
61 { .Name: 20, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 8, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
62 { .Name: 23, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 9, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
63 { .Name: 26, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 10, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
64 { .Name: 29, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 11, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
65 { .Name: 32, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 12, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
66 { .Name: 35, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 13, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
67 { .Name: 0, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 14, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
68 { .Name: 7, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 15, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
69};
70
71extern const MCPhysReg XCoreRegUnitRoots[][2] = {
72 { XCore::CP },
73 { XCore::DP },
74 { XCore::LR },
75 { XCore::SP },
76 { XCore::R0 },
77 { XCore::R1 },
78 { XCore::R2 },
79 { XCore::R3 },
80 { XCore::R4 },
81 { XCore::R5 },
82 { XCore::R6 },
83 { XCore::R7 },
84 { XCore::R8 },
85 { XCore::R9 },
86 { XCore::R10 },
87 { XCore::R11 },
88};
89
90namespace {
91
92// Register classes...
93 // RRegs Register Class...
94 const MCPhysReg RRegs[] = {
95 XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::R11, XCore::CP, XCore::DP, XCore::SP, XCore::LR,
96 };
97
98 // RRegs Bit set.
99 const uint8_t RRegsBits[] = {
100 0xfe, 0xff, 0x01,
101 };
102
103 // GRRegs Register Class...
104 const MCPhysReg GRRegs[] = {
105 XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::R11,
106 };
107
108 // GRRegs Bit set.
109 const uint8_t GRRegsBits[] = {
110 0xe0, 0xff, 0x01,
111 };
112
113} // namespace
114
115#ifdef __GNUC__
116#pragma GCC diagnostic push
117#pragma GCC diagnostic ignored "-Woverlength-strings"
118#endif
119extern const char XCoreRegClassStrings[] = {
120 /* 0 */ "GRRegs\000"
121};
122#ifdef __GNUC__
123#pragma GCC diagnostic pop
124#endif
125
126extern const MCRegisterClass XCoreMCRegisterClasses[] = {
127 { .RegsBegin: RRegs, .RegSet: RRegsBits, .NameIdx: 1, .RegsSize: 16, .RegSetSize: sizeof(RRegsBits), .ID: XCore::RRegsRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: false, .BaseClass: false },
128 { .RegsBegin: GRRegs, .RegSet: GRRegsBits, .NameIdx: 0, .RegsSize: 12, .RegSetSize: sizeof(GRRegsBits), .ID: XCore::GRRegsRegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
129};
130
131// XCore Dwarf<->LLVM register mappings.
132extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[] = {
133 { .FromReg: 0U, .ToReg: XCore::R0 },
134 { .FromReg: 1U, .ToReg: XCore::R1 },
135 { .FromReg: 2U, .ToReg: XCore::R2 },
136 { .FromReg: 3U, .ToReg: XCore::R3 },
137 { .FromReg: 4U, .ToReg: XCore::R4 },
138 { .FromReg: 5U, .ToReg: XCore::R5 },
139 { .FromReg: 6U, .ToReg: XCore::R6 },
140 { .FromReg: 7U, .ToReg: XCore::R7 },
141 { .FromReg: 8U, .ToReg: XCore::R8 },
142 { .FromReg: 9U, .ToReg: XCore::R9 },
143 { .FromReg: 10U, .ToReg: XCore::R10 },
144 { .FromReg: 11U, .ToReg: XCore::R11 },
145 { .FromReg: 12U, .ToReg: XCore::CP },
146 { .FromReg: 13U, .ToReg: XCore::DP },
147 { .FromReg: 14U, .ToReg: XCore::SP },
148 { .FromReg: 15U, .ToReg: XCore::LR },
149};
150extern const unsigned XCoreDwarfFlavour0Dwarf2LSize = std::size(XCoreDwarfFlavour0Dwarf2L);
151
152extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[] = {
153 { .FromReg: 0U, .ToReg: XCore::R0 },
154 { .FromReg: 1U, .ToReg: XCore::R1 },
155 { .FromReg: 2U, .ToReg: XCore::R2 },
156 { .FromReg: 3U, .ToReg: XCore::R3 },
157 { .FromReg: 4U, .ToReg: XCore::R4 },
158 { .FromReg: 5U, .ToReg: XCore::R5 },
159 { .FromReg: 6U, .ToReg: XCore::R6 },
160 { .FromReg: 7U, .ToReg: XCore::R7 },
161 { .FromReg: 8U, .ToReg: XCore::R8 },
162 { .FromReg: 9U, .ToReg: XCore::R9 },
163 { .FromReg: 10U, .ToReg: XCore::R10 },
164 { .FromReg: 11U, .ToReg: XCore::R11 },
165 { .FromReg: 12U, .ToReg: XCore::CP },
166 { .FromReg: 13U, .ToReg: XCore::DP },
167 { .FromReg: 14U, .ToReg: XCore::SP },
168 { .FromReg: 15U, .ToReg: XCore::LR },
169};
170extern const unsigned XCoreEHFlavour0Dwarf2LSize = std::size(XCoreEHFlavour0Dwarf2L);
171
172extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[] = {
173 { .FromReg: XCore::CP, .ToReg: 12U },
174 { .FromReg: XCore::DP, .ToReg: 13U },
175 { .FromReg: XCore::LR, .ToReg: 15U },
176 { .FromReg: XCore::SP, .ToReg: 14U },
177 { .FromReg: XCore::R0, .ToReg: 0U },
178 { .FromReg: XCore::R1, .ToReg: 1U },
179 { .FromReg: XCore::R2, .ToReg: 2U },
180 { .FromReg: XCore::R3, .ToReg: 3U },
181 { .FromReg: XCore::R4, .ToReg: 4U },
182 { .FromReg: XCore::R5, .ToReg: 5U },
183 { .FromReg: XCore::R6, .ToReg: 6U },
184 { .FromReg: XCore::R7, .ToReg: 7U },
185 { .FromReg: XCore::R8, .ToReg: 8U },
186 { .FromReg: XCore::R9, .ToReg: 9U },
187 { .FromReg: XCore::R10, .ToReg: 10U },
188 { .FromReg: XCore::R11, .ToReg: 11U },
189};
190extern const unsigned XCoreDwarfFlavour0L2DwarfSize = std::size(XCoreDwarfFlavour0L2Dwarf);
191
192extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[] = {
193 { .FromReg: XCore::CP, .ToReg: 12U },
194 { .FromReg: XCore::DP, .ToReg: 13U },
195 { .FromReg: XCore::LR, .ToReg: 15U },
196 { .FromReg: XCore::SP, .ToReg: 14U },
197 { .FromReg: XCore::R0, .ToReg: 0U },
198 { .FromReg: XCore::R1, .ToReg: 1U },
199 { .FromReg: XCore::R2, .ToReg: 2U },
200 { .FromReg: XCore::R3, .ToReg: 3U },
201 { .FromReg: XCore::R4, .ToReg: 4U },
202 { .FromReg: XCore::R5, .ToReg: 5U },
203 { .FromReg: XCore::R6, .ToReg: 6U },
204 { .FromReg: XCore::R7, .ToReg: 7U },
205 { .FromReg: XCore::R8, .ToReg: 8U },
206 { .FromReg: XCore::R9, .ToReg: 9U },
207 { .FromReg: XCore::R10, .ToReg: 10U },
208 { .FromReg: XCore::R11, .ToReg: 11U },
209};
210extern const unsigned XCoreEHFlavour0L2DwarfSize = std::size(XCoreEHFlavour0L2Dwarf);
211
212extern const uint16_t XCoreRegEncodingTable[] = {
213 0,
214 0,
215 0,
216 0,
217 0,
218 0,
219 0,
220 0,
221 0,
222 0,
223 0,
224 0,
225 0,
226 0,
227 0,
228 0,
229 0,
230};
231static inline void InitXCoreMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
232 RI->InitMCRegisterInfo(D: XCoreRegDesc, NR: 17, RA, PC, C: XCoreMCRegisterClasses, NC: 2, RURoots: XCoreRegUnitRoots, NRU: 16, DL: XCoreRegDiffLists, RUMS: XCoreLaneMaskLists, Strings: XCoreRegStrings, ClassStrings: XCoreRegClassStrings, SubIndices: XCoreSubRegIdxLists, NumIndices: 1,
233RET: XCoreRegEncodingTable, RUI: nullptr);
234
235 switch (DwarfFlavour) {
236 default:
237 llvm_unreachable("Unknown DWARF flavour");
238 case 0:
239 RI->mapDwarfRegsToLLVMRegs(Map: XCoreDwarfFlavour0Dwarf2L, Size: XCoreDwarfFlavour0Dwarf2LSize, isEH: false);
240 break;
241 }
242 switch (EHFlavour) {
243 default:
244 llvm_unreachable("Unknown DWARF flavour");
245 case 0:
246 RI->mapDwarfRegsToLLVMRegs(Map: XCoreEHFlavour0Dwarf2L, Size: XCoreEHFlavour0Dwarf2LSize, isEH: true);
247 break;
248 }
249 switch (DwarfFlavour) {
250 default:
251 llvm_unreachable("Unknown DWARF flavour");
252 case 0:
253 RI->mapLLVMRegsToDwarfRegs(Map: XCoreDwarfFlavour0L2Dwarf, Size: XCoreDwarfFlavour0L2DwarfSize, isEH: false);
254 break;
255 }
256 switch (EHFlavour) {
257 default:
258 llvm_unreachable("Unknown DWARF flavour");
259 case 0:
260 RI->mapLLVMRegsToDwarfRegs(Map: XCoreEHFlavour0L2Dwarf, Size: XCoreEHFlavour0L2DwarfSize, isEH: true);
261 break;
262 }
263}
264
265
266} // namespace llvm
267