1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t XCoreRegDiffLists[] = {
12 /* 0 */ 0,
13};
14
15extern const LaneBitmask XCoreLaneMaskLists[] = {
16 /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
17};
18
19extern const uint16_t XCoreSubRegIdxLists[] = {
20 /* 0 */
21 /* dummy */ 0
22};
23
24
25#ifdef __GNUC__
26#pragma GCC diagnostic push
27#pragma GCC diagnostic ignored "-Woverlength-strings"
28#endif
29extern const char XCoreRegStrings[] = {
30 /* 0 */ "R10\000"
31 /* 4 */ "R0\000"
32 /* 7 */ "R11\000"
33 /* 11 */ "R1\000"
34 /* 14 */ "R2\000"
35 /* 17 */ "R3\000"
36 /* 20 */ "R4\000"
37 /* 23 */ "R5\000"
38 /* 26 */ "R6\000"
39 /* 29 */ "R7\000"
40 /* 32 */ "R8\000"
41 /* 35 */ "R9\000"
42 /* 38 */ "CP\000"
43 /* 41 */ "DP\000"
44 /* 44 */ "SP\000"
45 /* 47 */ "LR\000"
46};
47#ifdef __GNUC__
48#pragma GCC diagnostic pop
49#endif
50
51extern const MCRegisterDesc XCoreRegDesc[] = { // Descriptors
52 { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
53 { .Name: 38, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
54 { .Name: 41, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 1, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
55 { .Name: 47, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 2, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
56 { .Name: 44, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 3, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
57 { .Name: 4, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 4, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
58 { .Name: 11, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 5, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
59 { .Name: 14, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 6, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
60 { .Name: 17, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 7, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
61 { .Name: 20, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 8, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
62 { .Name: 23, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 9, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
63 { .Name: 26, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 10, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
64 { .Name: 29, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 11, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
65 { .Name: 32, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 12, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
66 { .Name: 35, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 13, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
67 { .Name: 0, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 14, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
68 { .Name: 7, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 15, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
69};
70
71extern const MCPhysReg XCoreRegUnitRoots[][2] = {
72 { XCore::CP },
73 { XCore::DP },
74 { XCore::LR },
75 { XCore::SP },
76 { XCore::R0 },
77 { XCore::R1 },
78 { XCore::R2 },
79 { XCore::R3 },
80 { XCore::R4 },
81 { XCore::R5 },
82 { XCore::R6 },
83 { XCore::R7 },
84 { XCore::R8 },
85 { XCore::R9 },
86 { XCore::R10 },
87 { XCore::R11 },
88};
89
90// Register classes...
91
92#ifdef __GNUC__
93#pragma GCC diagnostic push
94#pragma GCC diagnostic ignored "-Woverlength-strings"
95#endif
96extern const char XCoreRegClassStrings[] = {
97 /* 0 */ "GRRegs\000"
98};
99#ifdef __GNUC__
100#pragma GCC diagnostic pop
101#endif
102
103using XCoreRegisterClassStorage = MCRegisterClassStorage<2, 28, 6, 2, 1, 1>;
104extern const MCRegisterClassStorage<2, 28, 6, 2, 1, 1> XCoreMCRegisterClassStorage = {
105 .Classes: {
106 {
107 offsetof(XCoreRegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass),
108 offsetof(XCoreRegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass),
109 .NameIdx: 1,
110 .RegSizeInBits: 32,
111 .RegsSize: 16,
112 .RegSetSize: 3,
113 .ID: XCore::RRegsRegClassID,
114 .CopyCost: 1, /* CopyCost */
115 .Allocatable: false, /* Allocatable */
116 .BaseClass: false,
117 offsetof(XCoreRegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass),
118 offsetof(XCoreRegisterClassStorage, SuperRegIdxSeqs[0]) - 0 * sizeof(MCRegisterClass),
119 .LaneMask: LaneBitmask(0x0000000000000001),
120 .AllocationPriority: 0,
121 .GlobalPriority: false,
122 .TSFlags: 0x00, /* TSFlags */
123 .SpillStackID: 0, /* SpillStackID */
124 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
125 .CoveredBySubRegs: false, /* CoveredBySubRegs */
126 offsetof(XCoreRegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass),
127 .SuperClassesSize: 0
128 },
129 {
130 offsetof(XCoreRegisterClassStorage, Regs[16]) - 1 * sizeof(MCRegisterClass),
131 offsetof(XCoreRegisterClassStorage, BitSets[3]) - 1 * sizeof(MCRegisterClass),
132 .NameIdx: 0,
133 .RegSizeInBits: 32,
134 .RegsSize: 12,
135 .RegSetSize: 3,
136 .ID: XCore::GRRegsRegClassID,
137 .CopyCost: 1, /* CopyCost */
138 .Allocatable: true, /* Allocatable */
139 .BaseClass: false,
140 offsetof(XCoreRegisterClassStorage, SubClassMasks[1]) - 1 * sizeof(MCRegisterClass),
141 offsetof(XCoreRegisterClassStorage, SuperRegIdxSeqs[0]) - 1 * sizeof(MCRegisterClass),
142 .LaneMask: LaneBitmask(0x0000000000000001),
143 .AllocationPriority: 0,
144 .GlobalPriority: false,
145 .TSFlags: 0x00, /* TSFlags */
146 .SpillStackID: 0, /* SpillStackID */
147 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
148 .CoveredBySubRegs: false, /* CoveredBySubRegs */
149 offsetof(XCoreRegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass),
150 .SuperClassesSize: 1
151 },
152 },
153 .Regs: {
154 /* 0 */ XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::R11, XCore::CP, XCore::DP, XCore::SP, XCore::LR,
155 /* 16 */ XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::R11,
156 },
157 .BitSets: {
158 /* 0 */ 0xfe, 0xff, 0x01,
159 /* 3 */ 0xe0, 0xff, 0x01,
160 },
161 .SubClassMasks: {
162 // 0 RRegs
163 0x00000003,
164 // 1 GRRegs
165 0x00000002,
166 },
167 .SuperRegIdxSeqs: {
168 /* 0 */ 0,
169 },
170 .SuperClasses: {
171 /* 0 RRegs */
172 /* 0 GRRegs */ XCore::RRegsRegClassID,
173 }
174};
175
176const MCRegisterClass &getXCoreMCRegisterClass(unsigned RC) {
177 return XCoreMCRegisterClassStorage.Classes[RC];
178}
179
180// XCore Dwarf<->LLVM register mappings.
181extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[] = {
182 { .FromReg: 0U, .ToReg: XCore::R0 },
183 { .FromReg: 1U, .ToReg: XCore::R1 },
184 { .FromReg: 2U, .ToReg: XCore::R2 },
185 { .FromReg: 3U, .ToReg: XCore::R3 },
186 { .FromReg: 4U, .ToReg: XCore::R4 },
187 { .FromReg: 5U, .ToReg: XCore::R5 },
188 { .FromReg: 6U, .ToReg: XCore::R6 },
189 { .FromReg: 7U, .ToReg: XCore::R7 },
190 { .FromReg: 8U, .ToReg: XCore::R8 },
191 { .FromReg: 9U, .ToReg: XCore::R9 },
192 { .FromReg: 10U, .ToReg: XCore::R10 },
193 { .FromReg: 11U, .ToReg: XCore::R11 },
194 { .FromReg: 12U, .ToReg: XCore::CP },
195 { .FromReg: 13U, .ToReg: XCore::DP },
196 { .FromReg: 14U, .ToReg: XCore::SP },
197 { .FromReg: 15U, .ToReg: XCore::LR },
198};
199extern const unsigned XCoreDwarfFlavour0Dwarf2LSize = std::size(XCoreDwarfFlavour0Dwarf2L);
200
201extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[] = {
202 { .FromReg: 0U, .ToReg: XCore::R0 },
203 { .FromReg: 1U, .ToReg: XCore::R1 },
204 { .FromReg: 2U, .ToReg: XCore::R2 },
205 { .FromReg: 3U, .ToReg: XCore::R3 },
206 { .FromReg: 4U, .ToReg: XCore::R4 },
207 { .FromReg: 5U, .ToReg: XCore::R5 },
208 { .FromReg: 6U, .ToReg: XCore::R6 },
209 { .FromReg: 7U, .ToReg: XCore::R7 },
210 { .FromReg: 8U, .ToReg: XCore::R8 },
211 { .FromReg: 9U, .ToReg: XCore::R9 },
212 { .FromReg: 10U, .ToReg: XCore::R10 },
213 { .FromReg: 11U, .ToReg: XCore::R11 },
214 { .FromReg: 12U, .ToReg: XCore::CP },
215 { .FromReg: 13U, .ToReg: XCore::DP },
216 { .FromReg: 14U, .ToReg: XCore::SP },
217 { .FromReg: 15U, .ToReg: XCore::LR },
218};
219extern const unsigned XCoreEHFlavour0Dwarf2LSize = std::size(XCoreEHFlavour0Dwarf2L);
220
221extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[] = {
222 { .FromReg: XCore::CP, .ToReg: 12U },
223 { .FromReg: XCore::DP, .ToReg: 13U },
224 { .FromReg: XCore::LR, .ToReg: 15U },
225 { .FromReg: XCore::SP, .ToReg: 14U },
226 { .FromReg: XCore::R0, .ToReg: 0U },
227 { .FromReg: XCore::R1, .ToReg: 1U },
228 { .FromReg: XCore::R2, .ToReg: 2U },
229 { .FromReg: XCore::R3, .ToReg: 3U },
230 { .FromReg: XCore::R4, .ToReg: 4U },
231 { .FromReg: XCore::R5, .ToReg: 5U },
232 { .FromReg: XCore::R6, .ToReg: 6U },
233 { .FromReg: XCore::R7, .ToReg: 7U },
234 { .FromReg: XCore::R8, .ToReg: 8U },
235 { .FromReg: XCore::R9, .ToReg: 9U },
236 { .FromReg: XCore::R10, .ToReg: 10U },
237 { .FromReg: XCore::R11, .ToReg: 11U },
238};
239extern const unsigned XCoreDwarfFlavour0L2DwarfSize = std::size(XCoreDwarfFlavour0L2Dwarf);
240
241extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[] = {
242 { .FromReg: XCore::CP, .ToReg: 12U },
243 { .FromReg: XCore::DP, .ToReg: 13U },
244 { .FromReg: XCore::LR, .ToReg: 15U },
245 { .FromReg: XCore::SP, .ToReg: 14U },
246 { .FromReg: XCore::R0, .ToReg: 0U },
247 { .FromReg: XCore::R1, .ToReg: 1U },
248 { .FromReg: XCore::R2, .ToReg: 2U },
249 { .FromReg: XCore::R3, .ToReg: 3U },
250 { .FromReg: XCore::R4, .ToReg: 4U },
251 { .FromReg: XCore::R5, .ToReg: 5U },
252 { .FromReg: XCore::R6, .ToReg: 6U },
253 { .FromReg: XCore::R7, .ToReg: 7U },
254 { .FromReg: XCore::R8, .ToReg: 8U },
255 { .FromReg: XCore::R9, .ToReg: 9U },
256 { .FromReg: XCore::R10, .ToReg: 10U },
257 { .FromReg: XCore::R11, .ToReg: 11U },
258};
259extern const unsigned XCoreEHFlavour0L2DwarfSize = std::size(XCoreEHFlavour0L2Dwarf);
260
261extern const uint16_t XCoreRegEncodingTable[] = {
262 0,
263 0,
264 0,
265 0,
266 0,
267 0,
268 0,
269 0,
270 0,
271 0,
272 0,
273 0,
274 0,
275 0,
276 0,
277 0,
278 0,
279};
280static inline void InitXCoreMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
281 RI->InitMCRegisterInfo(D: XCoreRegDesc, NR: 17, RA, PC, C: XCoreMCRegisterClassStorage.Classes, NC: 2, RURoots: XCoreRegUnitRoots, NRU: 16, DL: XCoreRegDiffLists, RUMS: XCoreLaneMaskLists, Strings: XCoreRegStrings, ClassStrings: XCoreRegClassStrings, SubIndices: XCoreSubRegIdxLists, NumIndices: 1,
282RET: XCoreRegEncodingTable, RUI: nullptr);
283
284 switch (DwarfFlavour) {
285 default:
286 llvm_unreachable("Unknown DWARF flavour");
287 case 0:
288 RI->mapDwarfRegsToLLVMRegs(Map: XCoreDwarfFlavour0Dwarf2L, Size: XCoreDwarfFlavour0Dwarf2LSize, isEH: false);
289 break;
290 }
291 switch (EHFlavour) {
292 default:
293 llvm_unreachable("Unknown DWARF flavour");
294 case 0:
295 RI->mapDwarfRegsToLLVMRegs(Map: XCoreEHFlavour0Dwarf2L, Size: XCoreEHFlavour0Dwarf2LSize, isEH: true);
296 break;
297 }
298 switch (DwarfFlavour) {
299 default:
300 llvm_unreachable("Unknown DWARF flavour");
301 case 0:
302 RI->mapLLVMRegsToDwarfRegs(Map: XCoreDwarfFlavour0L2Dwarf, Size: XCoreDwarfFlavour0L2DwarfSize, isEH: false);
303 break;
304 }
305 switch (EHFlavour) {
306 default:
307 llvm_unreachable("Unknown DWARF flavour");
308 case 0:
309 RI->mapLLVMRegsToDwarfRegs(Map: XCoreEHFlavour0L2Dwarf, Size: XCoreEHFlavour0L2DwarfSize, isEH: true);
310 break;
311 }
312}
313
314
315} // namespace llvm
316