1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t XCoreRegDiffLists[] = {
12 /* 0 */ 0,
13};
14
15extern const LaneBitmask XCoreLaneMaskLists[] = {
16 /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
17};
18
19extern const uint16_t XCoreSubRegIdxLists[] = {
20 /* 0 */
21 /* dummy */ 0
22};
23
24
25#ifdef __GNUC__
26#pragma GCC diagnostic push
27#pragma GCC diagnostic ignored "-Woverlength-strings"
28#endif
29extern const char XCoreRegStrings[] = {
30 /* 0 */ "R10\000"
31 /* 4 */ "R0\000"
32 /* 7 */ "R11\000"
33 /* 11 */ "R1\000"
34 /* 14 */ "R2\000"
35 /* 17 */ "R3\000"
36 /* 20 */ "R4\000"
37 /* 23 */ "R5\000"
38 /* 26 */ "R6\000"
39 /* 29 */ "R7\000"
40 /* 32 */ "R8\000"
41 /* 35 */ "R9\000"
42 /* 38 */ "CP\000"
43 /* 41 */ "DP\000"
44 /* 44 */ "SP\000"
45 /* 47 */ "LR\000"
46};
47#ifdef __GNUC__
48#pragma GCC diagnostic pop
49#endif
50
51extern const MCRegisterDesc XCoreRegDesc[] = { // Descriptors
52 { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
53 { .Name: 38, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
54 { .Name: 41, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 1, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
55 { .Name: 47, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 2, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
56 { .Name: 44, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 3, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
57 { .Name: 4, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 4, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
58 { .Name: 11, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 5, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
59 { .Name: 14, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 6, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
60 { .Name: 17, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 7, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
61 { .Name: 20, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 8, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
62 { .Name: 23, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 9, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
63 { .Name: 26, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 10, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
64 { .Name: 29, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 11, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
65 { .Name: 32, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 12, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
66 { .Name: 35, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 13, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
67 { .Name: 0, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 14, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
68 { .Name: 7, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 15, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
69};
70
71extern const MCPhysReg XCoreRegUnitRoots[][2] = {
72 { XCore::CP },
73 { XCore::DP },
74 { XCore::LR },
75 { XCore::SP },
76 { XCore::R0 },
77 { XCore::R1 },
78 { XCore::R2 },
79 { XCore::R3 },
80 { XCore::R4 },
81 { XCore::R5 },
82 { XCore::R6 },
83 { XCore::R7 },
84 { XCore::R8 },
85 { XCore::R9 },
86 { XCore::R10 },
87 { XCore::R11 },
88};
89
90// Register classes...
91
92#ifdef __GNUC__
93#pragma GCC diagnostic push
94#pragma GCC diagnostic ignored "-Woverlength-strings"
95#endif
96extern const char XCoreRegClassStrings[] = {
97 /* 0 */ "GRRegs\000"
98};
99#ifdef __GNUC__
100#pragma GCC diagnostic pop
101#endif
102
103using XCoreRegisterClassStorage = MCRegisterClassStorage<2, 28, 4, 2, 1, 1>;
104extern const MCRegisterClassStorage<2, 28, 4, 2, 1, 1> XCoreMCRegisterClassStorage = {
105 .Classes: {
106 {
107 offsetof(XCoreRegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass),
108 offsetof(XCoreRegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass),
109 .NameIdx: 1,
110 .RegSizeInBits: 32,
111 .RegsSize: 16,
112 .RegSetBegin: 1, /* MinRegVal */
113 .RegSetSize: 16, /* RegSetSize */
114 .ID: XCore::RRegsRegClassID,
115 .CopyCost: 1, /* CopyCost */
116 .Allocatable: false, /* Allocatable */
117 .BaseClass: false,
118 offsetof(XCoreRegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass),
119 offsetof(XCoreRegisterClassStorage, SuperRegIdxSeqs[0]) - 0 * sizeof(MCRegisterClass),
120 .LaneMask: LaneBitmask(0x0000000000000001),
121 .AllocationPriority: 0,
122 .GlobalPriority: false,
123 .TSFlags: 0x00, /* TSFlags */
124 .SpillStackID: 0, /* SpillStackID */
125 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
126 .CoveredBySubRegs: false, /* CoveredBySubRegs */
127 offsetof(XCoreRegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass),
128 .SuperClassesSize: 0
129 },
130 {
131 offsetof(XCoreRegisterClassStorage, Regs[16]) - 1 * sizeof(MCRegisterClass),
132 offsetof(XCoreRegisterClassStorage, BitSets[2]) - 1 * sizeof(MCRegisterClass),
133 .NameIdx: 0,
134 .RegSizeInBits: 32,
135 .RegsSize: 12,
136 .RegSetBegin: 5, /* MinRegVal */
137 .RegSetSize: 12, /* RegSetSize */
138 .ID: XCore::GRRegsRegClassID,
139 .CopyCost: 1, /* CopyCost */
140 .Allocatable: true, /* Allocatable */
141 .BaseClass: false,
142 offsetof(XCoreRegisterClassStorage, SubClassMasks[1]) - 1 * sizeof(MCRegisterClass),
143 offsetof(XCoreRegisterClassStorage, SuperRegIdxSeqs[0]) - 1 * sizeof(MCRegisterClass),
144 .LaneMask: LaneBitmask(0x0000000000000001),
145 .AllocationPriority: 0,
146 .GlobalPriority: false,
147 .TSFlags: 0x00, /* TSFlags */
148 .SpillStackID: 0, /* SpillStackID */
149 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
150 .CoveredBySubRegs: false, /* CoveredBySubRegs */
151 offsetof(XCoreRegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass),
152 .SuperClassesSize: 1
153 },
154 },
155 .Regs: {
156 /* 0 */ XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::R11, XCore::CP, XCore::DP, XCore::SP, XCore::LR,
157 /* 16 */ XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::R11,
158 },
159 .BitSets: {
160 /* 0 */ 0xff, 0xff,
161 /* 2 */ 0xff, 0x0f,
162 },
163 .SubClassMasks: {
164 // 0 RRegs
165 0x00000003,
166 // 1 GRRegs
167 0x00000002,
168 },
169 .SuperRegIdxSeqs: {
170 /* 0 */ 0,
171 },
172 .SuperClasses: {
173 /* 0 RRegs */
174 /* 0 GRRegs */ XCore::RRegsRegClassID,
175 }
176};
177
178const MCRegisterClass &getXCoreMCRegisterClass(unsigned RC) {
179 return XCoreMCRegisterClassStorage.Classes[RC];
180}
181
182// XCore Dwarf<->LLVM register mappings.
183extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[] = {
184 { .FromReg: 0U, .ToReg: XCore::R0 },
185 { .FromReg: 1U, .ToReg: XCore::R1 },
186 { .FromReg: 2U, .ToReg: XCore::R2 },
187 { .FromReg: 3U, .ToReg: XCore::R3 },
188 { .FromReg: 4U, .ToReg: XCore::R4 },
189 { .FromReg: 5U, .ToReg: XCore::R5 },
190 { .FromReg: 6U, .ToReg: XCore::R6 },
191 { .FromReg: 7U, .ToReg: XCore::R7 },
192 { .FromReg: 8U, .ToReg: XCore::R8 },
193 { .FromReg: 9U, .ToReg: XCore::R9 },
194 { .FromReg: 10U, .ToReg: XCore::R10 },
195 { .FromReg: 11U, .ToReg: XCore::R11 },
196 { .FromReg: 12U, .ToReg: XCore::CP },
197 { .FromReg: 13U, .ToReg: XCore::DP },
198 { .FromReg: 14U, .ToReg: XCore::SP },
199 { .FromReg: 15U, .ToReg: XCore::LR },
200};
201extern const unsigned XCoreDwarfFlavour0Dwarf2LSize = std::size(XCoreDwarfFlavour0Dwarf2L);
202
203extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[] = {
204 { .FromReg: 0U, .ToReg: XCore::R0 },
205 { .FromReg: 1U, .ToReg: XCore::R1 },
206 { .FromReg: 2U, .ToReg: XCore::R2 },
207 { .FromReg: 3U, .ToReg: XCore::R3 },
208 { .FromReg: 4U, .ToReg: XCore::R4 },
209 { .FromReg: 5U, .ToReg: XCore::R5 },
210 { .FromReg: 6U, .ToReg: XCore::R6 },
211 { .FromReg: 7U, .ToReg: XCore::R7 },
212 { .FromReg: 8U, .ToReg: XCore::R8 },
213 { .FromReg: 9U, .ToReg: XCore::R9 },
214 { .FromReg: 10U, .ToReg: XCore::R10 },
215 { .FromReg: 11U, .ToReg: XCore::R11 },
216 { .FromReg: 12U, .ToReg: XCore::CP },
217 { .FromReg: 13U, .ToReg: XCore::DP },
218 { .FromReg: 14U, .ToReg: XCore::SP },
219 { .FromReg: 15U, .ToReg: XCore::LR },
220};
221extern const unsigned XCoreEHFlavour0Dwarf2LSize = std::size(XCoreEHFlavour0Dwarf2L);
222
223extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[] = {
224 { .FromReg: XCore::CP, .ToReg: 12U },
225 { .FromReg: XCore::DP, .ToReg: 13U },
226 { .FromReg: XCore::LR, .ToReg: 15U },
227 { .FromReg: XCore::SP, .ToReg: 14U },
228 { .FromReg: XCore::R0, .ToReg: 0U },
229 { .FromReg: XCore::R1, .ToReg: 1U },
230 { .FromReg: XCore::R2, .ToReg: 2U },
231 { .FromReg: XCore::R3, .ToReg: 3U },
232 { .FromReg: XCore::R4, .ToReg: 4U },
233 { .FromReg: XCore::R5, .ToReg: 5U },
234 { .FromReg: XCore::R6, .ToReg: 6U },
235 { .FromReg: XCore::R7, .ToReg: 7U },
236 { .FromReg: XCore::R8, .ToReg: 8U },
237 { .FromReg: XCore::R9, .ToReg: 9U },
238 { .FromReg: XCore::R10, .ToReg: 10U },
239 { .FromReg: XCore::R11, .ToReg: 11U },
240};
241extern const unsigned XCoreDwarfFlavour0L2DwarfSize = std::size(XCoreDwarfFlavour0L2Dwarf);
242
243extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[] = {
244 { .FromReg: XCore::CP, .ToReg: 12U },
245 { .FromReg: XCore::DP, .ToReg: 13U },
246 { .FromReg: XCore::LR, .ToReg: 15U },
247 { .FromReg: XCore::SP, .ToReg: 14U },
248 { .FromReg: XCore::R0, .ToReg: 0U },
249 { .FromReg: XCore::R1, .ToReg: 1U },
250 { .FromReg: XCore::R2, .ToReg: 2U },
251 { .FromReg: XCore::R3, .ToReg: 3U },
252 { .FromReg: XCore::R4, .ToReg: 4U },
253 { .FromReg: XCore::R5, .ToReg: 5U },
254 { .FromReg: XCore::R6, .ToReg: 6U },
255 { .FromReg: XCore::R7, .ToReg: 7U },
256 { .FromReg: XCore::R8, .ToReg: 8U },
257 { .FromReg: XCore::R9, .ToReg: 9U },
258 { .FromReg: XCore::R10, .ToReg: 10U },
259 { .FromReg: XCore::R11, .ToReg: 11U },
260};
261extern const unsigned XCoreEHFlavour0L2DwarfSize = std::size(XCoreEHFlavour0L2Dwarf);
262
263extern const uint16_t XCoreRegEncodingTable[] = {
264 0,
265 0,
266 0,
267 0,
268 0,
269 0,
270 0,
271 0,
272 0,
273 0,
274 0,
275 0,
276 0,
277 0,
278 0,
279 0,
280 0,
281};
282static inline void InitXCoreMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
283 RI->InitMCRegisterInfo(D: XCoreRegDesc, NR: 17, RA, PC, C: XCoreMCRegisterClassStorage.Classes, NC: 2, RURoots: XCoreRegUnitRoots, NRU: 16, DL: XCoreRegDiffLists, RUMS: XCoreLaneMaskLists, Strings: XCoreRegStrings, ClassStrings: XCoreRegClassStrings, SubIndices: XCoreSubRegIdxLists, NumIndices: 1,
284RET: XCoreRegEncodingTable, RUI: nullptr);
285
286 switch (DwarfFlavour) {
287 default:
288 llvm_unreachable("Unknown DWARF flavour");
289 case 0:
290 RI->mapDwarfRegsToLLVMRegs(Map: XCoreDwarfFlavour0Dwarf2L, Size: XCoreDwarfFlavour0Dwarf2LSize, isEH: false);
291 break;
292 }
293 switch (EHFlavour) {
294 default:
295 llvm_unreachable("Unknown DWARF flavour");
296 case 0:
297 RI->mapDwarfRegsToLLVMRegs(Map: XCoreEHFlavour0Dwarf2L, Size: XCoreEHFlavour0Dwarf2LSize, isEH: true);
298 break;
299 }
300 switch (DwarfFlavour) {
301 default:
302 llvm_unreachable("Unknown DWARF flavour");
303 case 0:
304 RI->mapLLVMRegsToDwarfRegs(Map: XCoreDwarfFlavour0L2Dwarf, Size: XCoreDwarfFlavour0L2DwarfSize, isEH: false);
305 break;
306 }
307 switch (EHFlavour) {
308 default:
309 llvm_unreachable("Unknown DWARF flavour");
310 case 0:
311 RI->mapLLVMRegsToDwarfRegs(Map: XCoreEHFlavour0L2Dwarf, Size: XCoreEHFlavour0L2DwarfSize, isEH: true);
312 break;
313 }
314}
315
316
317} // namespace llvm
318