1//===--- BuiltinsPPC.def - PowerPC Builtin function database ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the PowerPC-specific builtin function database. Users of
10// this file must define the BUILTIN macro or the CUSTOM_BUILTIN macro to
11// make use of this information. The latter is used for builtins requiring
12// custom code generation and checking.
13//
14//===----------------------------------------------------------------------===//
15
16// FIXME: this needs to be the full list supported by GCC. Right now, I'm just
17// adding stuff on demand.
18
19// The format of this database matches clang/Basic/Builtins.def except for the
20// MMA builtins that are using their own format documented below.
21
22#ifndef BUILTIN
23#define BUILTIN(ID, TYPE, ATTRS)
24#endif
25
26#if defined(BUILTIN) && !defined(TARGET_BUILTIN)
27#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
28#endif
29
30// Built-ins requiring custom code generation.
31// Because these built-ins rely on target-dependent types and to avoid pervasive
32// change, they are type checked manually in Sema using custom type descriptors.
33// The first argument of the CUSTOM_BUILTIN macro is the name of the built-in
34// with its prefix, the second argument is the name of the intrinsic this
35// built-in generates, the third argument specifies the type of the function
36// (result value, then each argument) as follows:
37// i -> Unsigned integer followed by the greatest possible value for that
38// argument or 0 if no constraint on the value.
39// (e.g. i15 for a 4-bits value)
40// V -> Vector type used with MMA built-ins (vector unsigned char)
41// W -> PPC Vector type followed by the size of the vector type.
42// (e.g. W512 for __vector_quad)
43// any other descriptor -> Fall back to generic type descriptor decoding.
44// The 'C' suffix can be used as a suffix to specify the const type.
45// The '*' suffix can be used as a suffix to specify a pointer to a type.
46// The fourth argument is set to true if the built-in accumulates its result
47// into its given accumulator.
48
49#ifndef CUSTOM_BUILTIN
50#define CUSTOM_BUILTIN(ID, INTR, TYPES, ACCUMULATE, FEATURE) \
51 TARGET_BUILTIN(__builtin_##ID, "i.", "t", FEATURE)
52#endif
53
54// UNALIASED_CUSTOM_BUILTIN macro is used for built-ins that have
55// the same name as that of the intrinsic they generate, i.e. the
56// ID and INTR are the same.
57// This avoids repeating the ID and INTR in the macro expression.
58#define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE, FEATURE) \
59 CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE, FEATURE)
60
61// UNALIASED_CUSTOM_MMA_BUILTIN macro is used for MMA built-ins and its
62// corresponding 4 positive/negative multiply and positive/negative accumulate
63// built-in with the same ID concated with posfix [nn|np|pn|pp].
64// This avoids repeating the TYPES and FEATURE in the macro expression.
65// eg.
66// UNALIASED_CUSTOM_MMA_BUILTIN(mma_xvf16ger2, "vW512*VV",
67// "mma,paired-vector-memops")
68// Will generate built-ins:
69// * __builtin_mma_xvf16ger2()
70// * __builtin_mma_xvf16ger2nn()
71// * __builtin_mma_xvf16ger2np()
72// * __builtin_mma_xvf16ger2pn()
73// * __builtin_mma_xvf16ger2nn()
74// All with the same TYPES and FEATURE.
75#define UNALIASED_CUSTOM_MMA_BUILTIN(ID, TYPES, FEATURE) \
76 UNALIASED_CUSTOM_BUILTIN(ID, TYPES, false, FEATURE) \
77 UNALIASED_CUSTOM_BUILTIN(ID##nn, TYPES, true, FEATURE) \
78 UNALIASED_CUSTOM_BUILTIN(ID##np, TYPES, true, FEATURE) \
79 UNALIASED_CUSTOM_BUILTIN(ID##pn, TYPES, true, FEATURE) \
80 UNALIASED_CUSTOM_BUILTIN(ID##pp, TYPES, true, FEATURE)
81
82// GCC predefined macros to rename builtins, undef them to keep original names.
83#if defined(__GNUC__) && !defined(__clang__)
84#undef __builtin_vsx_xvnmaddadp
85#undef __builtin_vsx_xvnmaddasp
86#undef __builtin_vsx_xvmsubasp
87#undef __builtin_vsx_xvmsubadp
88#undef __builtin_vsx_xvmaddadp
89#undef __builtin_vsx_xvnmsubasp
90#undef __builtin_vsx_xvnmsubadp
91#undef __builtin_vsx_xvmaddasp
92#endif
93
94// XL Compatibility built-ins
95BUILTIN(__builtin_ppc_popcntb, "ULiULi", "")
96BUILTIN(__builtin_ppc_poppar4, "iUi", "")
97BUILTIN(__builtin_ppc_poppar8, "iULLi", "")
98BUILTIN(__builtin_ppc_eieio, "v", "")
99BUILTIN(__builtin_ppc_iospace_eieio, "v", "")
100BUILTIN(__builtin_ppc_isync, "v", "")
101BUILTIN(__builtin_ppc_lwsync, "v", "")
102BUILTIN(__builtin_ppc_iospace_lwsync, "v", "")
103BUILTIN(__builtin_ppc_sync, "v", "")
104BUILTIN(__builtin_ppc_iospace_sync, "v", "")
105BUILTIN(__builtin_ppc_dcbfl, "vvC*", "")
106BUILTIN(__builtin_ppc_dcbflp, "vvC*", "")
107BUILTIN(__builtin_ppc_dcbst, "vvC*", "")
108BUILTIN(__builtin_ppc_dcbt, "vv*", "")
109BUILTIN(__builtin_ppc_dcbtst, "vv*", "")
110BUILTIN(__builtin_ppc_dcbz, "vv*", "")
111TARGET_BUILTIN(__builtin_ppc_icbt, "vv*", "", "isa-v207-instructions")
112BUILTIN(__builtin_ppc_fric, "dd", "")
113BUILTIN(__builtin_ppc_frim, "dd", "")
114BUILTIN(__builtin_ppc_frims, "ff", "")
115BUILTIN(__builtin_ppc_frin, "dd", "")
116BUILTIN(__builtin_ppc_frins, "ff", "")
117BUILTIN(__builtin_ppc_frip, "dd", "")
118BUILTIN(__builtin_ppc_frips, "ff", "")
119BUILTIN(__builtin_ppc_friz, "dd", "")
120BUILTIN(__builtin_ppc_frizs, "ff", "")
121BUILTIN(__builtin_ppc_fsel, "dddd", "")
122BUILTIN(__builtin_ppc_fsels, "ffff", "")
123BUILTIN(__builtin_ppc_frsqrte, "dd", "")
124BUILTIN(__builtin_ppc_frsqrtes, "ff", "")
125BUILTIN(__builtin_ppc_fsqrt, "dd", "")
126BUILTIN(__builtin_ppc_fsqrts, "ff", "")
127BUILTIN(__builtin_ppc_compare_and_swap, "iiD*i*i", "")
128BUILTIN(__builtin_ppc_compare_and_swaplp, "iLiD*Li*Li", "")
129BUILTIN(__builtin_ppc_fetch_and_add, "iiD*i", "")
130BUILTIN(__builtin_ppc_fetch_and_addlp, "LiLiD*Li", "")
131BUILTIN(__builtin_ppc_fetch_and_and, "UiUiD*Ui", "")
132BUILTIN(__builtin_ppc_fetch_and_andlp, "ULiULiD*ULi", "")
133BUILTIN(__builtin_ppc_fetch_and_or, "UiUiD*Ui", "")
134BUILTIN(__builtin_ppc_fetch_and_orlp, "ULiULiD*ULi", "")
135BUILTIN(__builtin_ppc_fetch_and_swap, "UiUiD*Ui", "")
136BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
137BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
138BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
139TARGET_BUILTIN(__builtin_ppc_lharx, "ssD*", "", "isa-v207-instructions")
140TARGET_BUILTIN(__builtin_ppc_lbarx, "ccD*", "", "isa-v207-instructions")
141BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
142BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
143TARGET_BUILTIN(__builtin_ppc_sthcx, "isD*s", "", "isa-v207-instructions")
144TARGET_BUILTIN(__builtin_ppc_stbcx, "icD*i", "", "isa-v207-instructions")
145BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "")
146BUILTIN(__builtin_ppc_tw, "viiIUi", "")
147BUILTIN(__builtin_ppc_trap, "vi", "")
148BUILTIN(__builtin_ppc_trapd, "vLi", "")
149BUILTIN(__builtin_ppc_fcfid, "dd", "")
150BUILTIN(__builtin_ppc_fcfud, "dd", "")
151BUILTIN(__builtin_ppc_fctid, "dd", "")
152BUILTIN(__builtin_ppc_fctidz, "dd", "")
153BUILTIN(__builtin_ppc_fctiw, "dd", "")
154BUILTIN(__builtin_ppc_fctiwz, "dd", "")
155BUILTIN(__builtin_ppc_fctudz, "dd", "")
156BUILTIN(__builtin_ppc_fctuwz, "dd", "")
157
158// fence builtin prevents all instructions moved across it
159BUILTIN(__builtin_ppc_fence, "v", "")
160
161BUILTIN(__builtin_ppc_swdiv_nochk, "ddd", "")
162BUILTIN(__builtin_ppc_swdivs_nochk, "fff", "")
163BUILTIN(__builtin_ppc_alignx, "vIivC*", "nc")
164BUILTIN(__builtin_ppc_rdlam, "UWiUWiUWiUWIi", "nc")
165TARGET_BUILTIN(__builtin_ppc_compare_exp_uo, "idd", "", "isa-v30-instructions,vsx")
166TARGET_BUILTIN(__builtin_ppc_compare_exp_lt, "idd", "", "isa-v30-instructions,vsx")
167TARGET_BUILTIN(__builtin_ppc_compare_exp_gt, "idd", "", "isa-v30-instructions,vsx")
168TARGET_BUILTIN(__builtin_ppc_compare_exp_eq, "idd", "", "isa-v30-instructions,vsx")
169TARGET_BUILTIN(__builtin_ppc_test_data_class, "idIi", "t", "isa-v30-instructions,vsx")
170BUILTIN(__builtin_ppc_swdiv, "ddd", "")
171BUILTIN(__builtin_ppc_swdivs, "fff", "")
172// Compare
173TARGET_BUILTIN(__builtin_ppc_cmpeqb, "LLiLLiLLi", "", "isa-v30-instructions")
174TARGET_BUILTIN(__builtin_ppc_cmprb, "iCIiii", "", "isa-v30-instructions")
175TARGET_BUILTIN(__builtin_ppc_setb, "LLiLLiLLi", "", "isa-v30-instructions")
176BUILTIN(__builtin_ppc_cmpb, "LLiLLiLLi", "")
177// Multiply
178BUILTIN(__builtin_ppc_mulhd, "LLiLiLi", "")
179BUILTIN(__builtin_ppc_mulhdu, "ULLiULiULi", "")
180BUILTIN(__builtin_ppc_mulhw, "iii", "")
181BUILTIN(__builtin_ppc_mulhwu, "UiUiUi", "")
182TARGET_BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi", "", "isa-v30-instructions")
183TARGET_BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "",
184 "isa-v30-instructions")
185TARGET_BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "", "isa-v30-instructions")
186// Rotate
187BUILTIN(__builtin_ppc_rlwnm, "UiUiUiIUi", "")
188BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
189BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
190// load
191BUILTIN(__builtin_ppc_load2r, "UsUs*", "")
192BUILTIN(__builtin_ppc_load4r, "UiUi*", "")
193TARGET_BUILTIN(__builtin_ppc_load8r, "ULLiULLi*", "", "isa-v206-instructions")
194// store
195BUILTIN(__builtin_ppc_store2r, "vUiUs*", "")
196BUILTIN(__builtin_ppc_store4r, "vUiUi*", "")
197TARGET_BUILTIN(__builtin_ppc_store8r, "vULLiULLi*", "", "isa-v206-instructions")
198TARGET_BUILTIN(__builtin_ppc_extract_exp, "Uid", "", "power9-vector")
199TARGET_BUILTIN(__builtin_ppc_extract_sig, "ULLid", "", "power9-vector")
200BUILTIN(__builtin_ppc_mtfsb0, "vUIi", "")
201BUILTIN(__builtin_ppc_mtfsb1, "vUIi", "")
202BUILTIN(__builtin_ppc_mffs, "d", "")
203TARGET_BUILTIN(__builtin_ppc_mffsl, "d", "", "isa-v30-instructions")
204BUILTIN(__builtin_ppc_mtfsf, "vUIiUi", "")
205BUILTIN(__builtin_ppc_mtfsfi, "vUIiUIi", "")
206BUILTIN(__builtin_ppc_set_fpscr_rn, "di", "")
207TARGET_BUILTIN(__builtin_ppc_insert_exp, "ddULLi", "", "power9-vector")
208BUILTIN(__builtin_ppc_fmsub, "dddd", "")
209BUILTIN(__builtin_ppc_fmsubs, "ffff", "")
210BUILTIN(__builtin_ppc_fnmadd, "dddd", "")
211BUILTIN(__builtin_ppc_fnmadds, "ffff", "")
212BUILTIN(__builtin_ppc_fnmsub, "dddd", "")
213BUILTIN(__builtin_ppc_fnmsubs, "ffff", "")
214BUILTIN(__builtin_ppc_fre, "dd", "")
215BUILTIN(__builtin_ppc_fres, "ff", "")
216BUILTIN(__builtin_ppc_dcbtstt, "vv*", "")
217BUILTIN(__builtin_ppc_dcbtt, "vv*", "")
218BUILTIN(__builtin_ppc_mftbu, "Ui", "")
219BUILTIN(__builtin_ppc_mfmsr, "Ui", "")
220BUILTIN(__builtin_ppc_mfspr, "ULiIi", "")
221BUILTIN(__builtin_ppc_mtmsr, "vUi", "")
222BUILTIN(__builtin_ppc_mtspr, "vIiULi", "")
223BUILTIN(__builtin_ppc_stfiw, "viC*d", "")
224TARGET_BUILTIN(__builtin_ppc_addex, "LLiLLiLLiCIi", "", "isa-v30-instructions")
225// select
226BUILTIN(__builtin_ppc_maxfe, "LdLdLdLd.", "t")
227BUILTIN(__builtin_ppc_maxfl, "dddd.", "t")
228BUILTIN(__builtin_ppc_maxfs, "ffff.", "t")
229BUILTIN(__builtin_ppc_minfe, "LdLdLdLd.", "t")
230BUILTIN(__builtin_ppc_minfl, "dddd.", "t")
231BUILTIN(__builtin_ppc_minfs, "ffff.", "t")
232// Floating Negative Absolute Value
233BUILTIN(__builtin_ppc_fnabs, "dd", "")
234BUILTIN(__builtin_ppc_fnabss, "ff", "")
235
236BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
237
238// This is just a placeholder, the types and attributes are wrong.
239TARGET_BUILTIN(__builtin_altivec_vaddcuw, "V4UiV4UiV4Ui", "", "altivec")
240
241TARGET_BUILTIN(__builtin_altivec_vaddsbs, "V16ScV16ScV16Sc", "", "altivec")
242TARGET_BUILTIN(__builtin_altivec_vaddubs, "V16UcV16UcV16Uc", "", "altivec")
243TARGET_BUILTIN(__builtin_altivec_vaddshs, "V8SsV8SsV8Ss", "", "altivec")
244TARGET_BUILTIN(__builtin_altivec_vadduhs, "V8UsV8UsV8Us", "", "altivec")
245TARGET_BUILTIN(__builtin_altivec_vaddsws, "V4SiV4SiV4Si", "", "altivec")
246TARGET_BUILTIN(__builtin_altivec_vadduws, "V4UiV4UiV4Ui", "", "altivec")
247TARGET_BUILTIN(__builtin_altivec_vaddeuqm, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "",
248 "power8-vector")
249TARGET_BUILTIN(__builtin_altivec_vaddcuq, "V1ULLLiV1ULLLiV1ULLLi", "",
250 "power8-vector")
251TARGET_BUILTIN(__builtin_altivec_vaddecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "",
252 "power8-vector")
253TARGET_BUILTIN(__builtin_altivec_vadduqm, "V1ULLLiV16UcV16Uc", "",
254 "power8-vector")
255TARGET_BUILTIN(__builtin_altivec_vaddeuqm_c, "V16UcV16UcV16UcV16Uc", "",
256 "power8-vector")
257TARGET_BUILTIN(__builtin_altivec_vaddcuq_c, "V16UcV16UcV16Uc", "",
258 "power8-vector")
259TARGET_BUILTIN(__builtin_altivec_vaddecuq_c, "V16UcV16UcV16UcV16Uc", "",
260 "power8-vector")
261
262TARGET_BUILTIN(__builtin_altivec_vsubsbs, "V16ScV16ScV16Sc", "", "altivec")
263TARGET_BUILTIN(__builtin_altivec_vsububs, "V16UcV16UcV16Uc", "", "altivec")
264TARGET_BUILTIN(__builtin_altivec_vsubshs, "V8SsV8SsV8Ss", "", "altivec")
265TARGET_BUILTIN(__builtin_altivec_vsubuhs, "V8UsV8UsV8Us", "", "altivec")
266TARGET_BUILTIN(__builtin_altivec_vsubsws, "V4SiV4SiV4Si", "", "altivec")
267TARGET_BUILTIN(__builtin_altivec_vsubuws, "V4UiV4UiV4Ui", "", "altivec")
268TARGET_BUILTIN(__builtin_altivec_vsubeuqm, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "",
269 "power8-vector")
270TARGET_BUILTIN(__builtin_altivec_vsubcuq, "V1ULLLiV1ULLLiV1ULLLi", "",
271 "power8-vector")
272TARGET_BUILTIN(__builtin_altivec_vsubecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "",
273 "power8-vector")
274TARGET_BUILTIN(__builtin_altivec_vsubuqm, "V1ULLLiV16UcV16Uc", "",
275 "power8-vector")
276TARGET_BUILTIN(__builtin_altivec_vsubeuqm_c, "V16UcV16UcV16UcV16Uc", "",
277 "power8-vector")
278TARGET_BUILTIN(__builtin_altivec_vsubcuq_c, "V16UcV16UcV16Uc", "",
279 "power8-vector")
280TARGET_BUILTIN(__builtin_altivec_vsubecuq_c, "V16UcV16UcV16UcV16Uc", "",
281 "power8-vector")
282
283TARGET_BUILTIN(__builtin_altivec_vavgsb, "V16ScV16ScV16Sc", "", "altivec")
284TARGET_BUILTIN(__builtin_altivec_vavgub, "V16UcV16UcV16Uc", "", "altivec")
285TARGET_BUILTIN(__builtin_altivec_vavgsh, "V8SsV8SsV8Ss", "", "altivec")
286TARGET_BUILTIN(__builtin_altivec_vavguh, "V8UsV8UsV8Us", "", "altivec")
287TARGET_BUILTIN(__builtin_altivec_vavgsw, "V4SiV4SiV4Si", "", "altivec")
288TARGET_BUILTIN(__builtin_altivec_vavguw, "V4UiV4UiV4Ui", "", "altivec")
289
290TARGET_BUILTIN(__builtin_altivec_vrfip, "V4fV4f", "", "altivec")
291
292TARGET_BUILTIN(__builtin_altivec_vcfsx, "V4fV4SiIi", "", "altivec")
293TARGET_BUILTIN(__builtin_altivec_vcfux, "V4fV4UiIi", "", "altivec")
294TARGET_BUILTIN(__builtin_altivec_vctsxs, "V4SiV4fIi", "", "altivec")
295TARGET_BUILTIN(__builtin_altivec_vctuxs, "V4UiV4fIi", "", "altivec")
296
297TARGET_BUILTIN(__builtin_altivec_dss, "vUIi", "", "altivec")
298TARGET_BUILTIN(__builtin_altivec_dssall, "v", "", "altivec")
299TARGET_BUILTIN(__builtin_altivec_dst, "vvC*iUIi", "", "altivec")
300TARGET_BUILTIN(__builtin_altivec_dstt, "vvC*iUIi", "", "altivec")
301TARGET_BUILTIN(__builtin_altivec_dstst, "vvC*iUIi", "", "altivec")
302TARGET_BUILTIN(__builtin_altivec_dststt, "vvC*iUIi", "", "altivec")
303
304TARGET_BUILTIN(__builtin_altivec_vexptefp, "V4fV4f", "", "altivec")
305
306TARGET_BUILTIN(__builtin_altivec_vrfim, "V4fV4f", "", "altivec")
307
308TARGET_BUILTIN(__builtin_altivec_lvx, "V4iLivC*", "", "altivec")
309TARGET_BUILTIN(__builtin_altivec_lvxl, "V4iLivC*", "", "altivec")
310TARGET_BUILTIN(__builtin_altivec_lvebx, "V16cLivC*", "", "altivec")
311TARGET_BUILTIN(__builtin_altivec_lvehx, "V8sLivC*", "", "altivec")
312TARGET_BUILTIN(__builtin_altivec_lvewx, "V4iLivC*", "", "altivec")
313
314TARGET_BUILTIN(__builtin_altivec_vlogefp, "V4fV4f", "", "altivec")
315
316TARGET_BUILTIN(__builtin_altivec_lvsl, "V16cUcvC*", "", "altivec")
317TARGET_BUILTIN(__builtin_altivec_lvsr, "V16cUcvC*", "", "altivec")
318
319TARGET_BUILTIN(__builtin_altivec_vmaddfp, "V4fV4fV4fV4f", "", "altivec")
320TARGET_BUILTIN(__builtin_altivec_vmhaddshs, "V8sV8sV8sV8s", "", "altivec")
321TARGET_BUILTIN(__builtin_altivec_vmhraddshs, "V8sV8sV8sV8s", "", "altivec")
322
323TARGET_BUILTIN(__builtin_altivec_vmsumubm, "V4UiV16UcV16UcV4Ui", "", "altivec")
324TARGET_BUILTIN(__builtin_altivec_vmsummbm, "V4SiV16ScV16UcV4Si", "", "altivec")
325TARGET_BUILTIN(__builtin_altivec_vmsumuhm, "V4UiV8UsV8UsV4Ui", "", "altivec")
326TARGET_BUILTIN(__builtin_altivec_vmsumshm, "V4SiV8SsV8SsV4Si", "", "altivec")
327TARGET_BUILTIN(__builtin_altivec_vmsumuhs, "V4UiV8UsV8UsV4Ui", "", "altivec")
328TARGET_BUILTIN(__builtin_altivec_vmsumshs, "V4SiV8SsV8SsV4Si", "", "altivec")
329
330TARGET_BUILTIN(__builtin_altivec_vmuleub, "V8UsV16UcV16Uc", "", "altivec")
331TARGET_BUILTIN(__builtin_altivec_vmulesb, "V8SsV16ScV16Sc", "", "altivec")
332TARGET_BUILTIN(__builtin_altivec_vmuleuh, "V4UiV8UsV8Us", "", "altivec")
333TARGET_BUILTIN(__builtin_altivec_vmulesh, "V4SiV8SsV8Ss", "", "altivec")
334TARGET_BUILTIN(__builtin_altivec_vmuleuw, "V2ULLiV4UiV4Ui", "", "power8-vector")
335TARGET_BUILTIN(__builtin_altivec_vmulesw, "V2SLLiV4SiV4Si", "", "power8-vector")
336TARGET_BUILTIN(__builtin_altivec_vmuloub, "V8UsV16UcV16Uc", "", "altivec")
337TARGET_BUILTIN(__builtin_altivec_vmulosb, "V8SsV16ScV16Sc", "", "altivec")
338TARGET_BUILTIN(__builtin_altivec_vmulouh, "V4UiV8UsV8Us", "", "altivec")
339TARGET_BUILTIN(__builtin_altivec_vmulosh, "V4SiV8SsV8Ss", "", "altivec")
340TARGET_BUILTIN(__builtin_altivec_vmulouw, "V2ULLiV4UiV4Ui", "", "power8-vector")
341TARGET_BUILTIN(__builtin_altivec_vmulosw, "V2SLLiV4SiV4Si", "", "power8-vector")
342TARGET_BUILTIN(__builtin_altivec_vmuleud, "V1ULLLiV2ULLiV2ULLi", "",
343 "power10-vector")
344TARGET_BUILTIN(__builtin_altivec_vmulesd, "V1SLLLiV2SLLiV2SLLi", "",
345 "power10-vector")
346TARGET_BUILTIN(__builtin_altivec_vmuloud, "V1ULLLiV2ULLiV2ULLi", "",
347 "power10-vector")
348TARGET_BUILTIN(__builtin_altivec_vmulosd, "V1SLLLiV2SLLiV2SLLi", "",
349 "power10-vector")
350TARGET_BUILTIN(__builtin_altivec_vmsumcud, "V1ULLLiV2ULLiV2ULLiV1ULLLi", "",
351 "power10-vector")
352
353TARGET_BUILTIN(__builtin_altivec_vnmsubfp, "V4fV4fV4fV4f", "", "altivec")
354
355TARGET_BUILTIN(__builtin_altivec_vpkpx, "V8sV4UiV4Ui", "", "altivec")
356TARGET_BUILTIN(__builtin_altivec_vpkuhus, "V16UcV8UsV8Us", "", "altivec")
357TARGET_BUILTIN(__builtin_altivec_vpkshss, "V16ScV8SsV8Ss", "", "altivec")
358TARGET_BUILTIN(__builtin_altivec_vpkuwus, "V8UsV4UiV4Ui", "", "altivec")
359TARGET_BUILTIN(__builtin_altivec_vpkswss, "V8SsV4SiV4Si", "", "altivec")
360TARGET_BUILTIN(__builtin_altivec_vpkshus, "V16UcV8SsV8Ss", "", "altivec")
361TARGET_BUILTIN(__builtin_altivec_vpkswus, "V8UsV4SiV4Si", "", "altivec")
362TARGET_BUILTIN(__builtin_altivec_vpksdss, "V4SiV2SLLiV2SLLi", "",
363 "power8-vector")
364TARGET_BUILTIN(__builtin_altivec_vpksdus, "V4UiV2SLLiV2SLLi", "",
365 "power8-vector")
366TARGET_BUILTIN(__builtin_altivec_vpkudus, "V4UiV2ULLiV2ULLi", "",
367 "power8-vector")
368TARGET_BUILTIN(__builtin_altivec_vpkudum, "V4UiV2ULLiV2ULLi", "",
369 "power8-vector")
370
371TARGET_BUILTIN(__builtin_altivec_vperm_4si, "V4iV4iV4iV16Uc", "", "altivec")
372
373TARGET_BUILTIN(__builtin_altivec_stvx, "vV4iLiv*", "", "altivec")
374TARGET_BUILTIN(__builtin_altivec_stvxl, "vV4iLiv*", "", "altivec")
375TARGET_BUILTIN(__builtin_altivec_stvebx, "vV16cLiv*", "", "altivec")
376TARGET_BUILTIN(__builtin_altivec_stvehx, "vV8sLiv*", "", "altivec")
377TARGET_BUILTIN(__builtin_altivec_stvewx, "vV4iLiv*", "", "altivec")
378
379TARGET_BUILTIN(__builtin_altivec_vcmpbfp, "V4iV4fV4f", "", "altivec")
380
381TARGET_BUILTIN(__builtin_altivec_vcmpgefp, "V4iV4fV4f", "", "altivec")
382
383TARGET_BUILTIN(__builtin_altivec_vcmpequb, "V16cV16cV16c", "", "altivec")
384TARGET_BUILTIN(__builtin_altivec_vcmpequh, "V8sV8sV8s", "", "altivec")
385TARGET_BUILTIN(__builtin_altivec_vcmpequw, "V4iV4iV4i", "", "altivec")
386TARGET_BUILTIN(__builtin_altivec_vcmpequd, "V2LLiV2LLiV2LLi", "",
387 "power8-vector")
388TARGET_BUILTIN(__builtin_altivec_vcmpeqfp, "V4iV4fV4f", "", "altivec")
389
390TARGET_BUILTIN(__builtin_altivec_vcmpneb, "V16cV16cV16c", "", "power9-vector")
391TARGET_BUILTIN(__builtin_altivec_vcmpneh, "V8sV8sV8s", "", "power9-vector")
392TARGET_BUILTIN(__builtin_altivec_vcmpnew, "V4iV4iV4i", "", "power9-vector")
393
394TARGET_BUILTIN(__builtin_altivec_vcmpnezb, "V16cV16cV16c", "", "power9-vector")
395TARGET_BUILTIN(__builtin_altivec_vcmpnezh, "V8sV8sV8s", "", "power9-vector")
396TARGET_BUILTIN(__builtin_altivec_vcmpnezw, "V4iV4iV4i", "", "power9-vector")
397
398TARGET_BUILTIN(__builtin_altivec_vcmpgtsb, "V16cV16ScV16Sc", "", "altivec")
399TARGET_BUILTIN(__builtin_altivec_vcmpgtub, "V16cV16UcV16Uc", "", "altivec")
400TARGET_BUILTIN(__builtin_altivec_vcmpgtsh, "V8sV8SsV8Ss", "", "altivec")
401TARGET_BUILTIN(__builtin_altivec_vcmpgtuh, "V8sV8UsV8Us", "", "altivec")
402TARGET_BUILTIN(__builtin_altivec_vcmpgtsw, "V4iV4SiV4Si", "", "altivec")
403TARGET_BUILTIN(__builtin_altivec_vcmpgtuw, "V4iV4UiV4Ui", "", "altivec")
404TARGET_BUILTIN(__builtin_altivec_vcmpgtsd, "V2LLiV2LLiV2LLi", "",
405 "power8-vector")
406TARGET_BUILTIN(__builtin_altivec_vcmpgtud, "V2LLiV2ULLiV2ULLi", "",
407 "power8-vector")
408TARGET_BUILTIN(__builtin_altivec_vcmpgtfp, "V4iV4fV4f", "", "altivec")
409
410// P10 Vector compare builtins.
411TARGET_BUILTIN(__builtin_altivec_vcmpequq, "V1LLLiV1ULLLiV1ULLLi", "",
412 "power10-vector")
413TARGET_BUILTIN(__builtin_altivec_vcmpgtsq, "V1LLLiV1SLLLiV1SLLLi", "",
414 "power10-vector")
415TARGET_BUILTIN(__builtin_altivec_vcmpgtuq, "V1LLLiV1ULLLiV1ULLLi", "",
416 "power10-vector")
417TARGET_BUILTIN(__builtin_altivec_vcmpequq_p, "iiV1ULLLiV1LLLi", "", "altivec")
418TARGET_BUILTIN(__builtin_altivec_vcmpgtsq_p, "iiV1SLLLiV1SLLLi", "",
419 "power10-vector")
420TARGET_BUILTIN(__builtin_altivec_vcmpgtuq_p, "iiV1ULLLiV1ULLLi", "",
421 "power10-vector")
422
423TARGET_BUILTIN(__builtin_altivec_vmaxsb, "V16ScV16ScV16Sc", "", "altivec")
424TARGET_BUILTIN(__builtin_altivec_vmaxub, "V16UcV16UcV16Uc", "", "altivec")
425TARGET_BUILTIN(__builtin_altivec_vmaxsh, "V8SsV8SsV8Ss", "", "altivec")
426TARGET_BUILTIN(__builtin_altivec_vmaxuh, "V8UsV8UsV8Us", "", "altivec")
427TARGET_BUILTIN(__builtin_altivec_vmaxsw, "V4SiV4SiV4Si", "", "altivec")
428TARGET_BUILTIN(__builtin_altivec_vmaxuw, "V4UiV4UiV4Ui", "", "altivec")
429TARGET_BUILTIN(__builtin_altivec_vmaxsd, "V2LLiV2LLiV2LLi", "", "power8-vector")
430TARGET_BUILTIN(__builtin_altivec_vmaxud, "V2ULLiV2ULLiV2ULLi", "",
431 "power8-vector")
432TARGET_BUILTIN(__builtin_altivec_vmaxfp, "V4fV4fV4f", "", "altivec")
433
434TARGET_BUILTIN(__builtin_altivec_mfvscr, "V8Us", "", "altivec")
435
436TARGET_BUILTIN(__builtin_altivec_vminsb, "V16ScV16ScV16Sc", "", "altivec")
437TARGET_BUILTIN(__builtin_altivec_vminub, "V16UcV16UcV16Uc", "", "altivec")
438TARGET_BUILTIN(__builtin_altivec_vminsh, "V8SsV8SsV8Ss", "", "altivec")
439TARGET_BUILTIN(__builtin_altivec_vminuh, "V8UsV8UsV8Us", "", "altivec")
440TARGET_BUILTIN(__builtin_altivec_vminsw, "V4SiV4SiV4Si", "", "altivec")
441TARGET_BUILTIN(__builtin_altivec_vminuw, "V4UiV4UiV4Ui", "", "altivec")
442TARGET_BUILTIN(__builtin_altivec_vminsd, "V2LLiV2LLiV2LLi", "", "power8-vector")
443TARGET_BUILTIN(__builtin_altivec_vminud, "V2ULLiV2ULLiV2ULLi", "",
444 "power8-vector")
445TARGET_BUILTIN(__builtin_altivec_vminfp, "V4fV4fV4f", "", "altivec")
446
447TARGET_BUILTIN(__builtin_altivec_mtvscr, "vV4i", "", "altivec")
448
449TARGET_BUILTIN(__builtin_altivec_vrefp, "V4fV4f", "", "altivec")
450
451TARGET_BUILTIN(__builtin_altivec_vrlb, "V16cV16cV16Uc", "", "altivec")
452TARGET_BUILTIN(__builtin_altivec_vrlh, "V8sV8sV8Us", "", "altivec")
453TARGET_BUILTIN(__builtin_altivec_vrlw, "V4iV4iV4Ui", "", "altivec")
454TARGET_BUILTIN(__builtin_altivec_vrld, "V2LLiV2LLiV2ULLi", "", "power8-vector")
455
456TARGET_BUILTIN(__builtin_altivec_vsel_4si, "V4iV4iV4iV4Ui", "", "altivec")
457
458TARGET_BUILTIN(__builtin_altivec_vsl, "V4iV4iV4i", "", "altivec")
459TARGET_BUILTIN(__builtin_altivec_vslo, "V4iV4iV4i", "", "altivec")
460
461TARGET_BUILTIN(__builtin_altivec_vsrab, "V16cV16cV16Uc", "", "altivec")
462TARGET_BUILTIN(__builtin_altivec_vsrah, "V8sV8sV8Us", "", "altivec")
463TARGET_BUILTIN(__builtin_altivec_vsraw, "V4iV4iV4Ui", "", "altivec")
464
465TARGET_BUILTIN(__builtin_altivec_vsr, "V4iV4iV4i", "", "altivec")
466TARGET_BUILTIN(__builtin_altivec_vsro, "V4iV4iV4i", "", "altivec")
467
468TARGET_BUILTIN(__builtin_altivec_vrfin, "V4fV4f", "", "altivec")
469
470TARGET_BUILTIN(__builtin_altivec_vrsqrtefp, "V4fV4f", "", "altivec")
471
472TARGET_BUILTIN(__builtin_altivec_vsubcuw, "V4UiV4UiV4Ui", "", "altivec")
473
474TARGET_BUILTIN(__builtin_altivec_vsum4sbs, "V4SiV16ScV4Si", "", "altivec")
475TARGET_BUILTIN(__builtin_altivec_vsum4ubs, "V4UiV16UcV4Ui", "", "altivec")
476TARGET_BUILTIN(__builtin_altivec_vsum4shs, "V4SiV8SsV4Si", "", "altivec")
477
478TARGET_BUILTIN(__builtin_altivec_vsum2sws, "V4SiV4SiV4Si", "", "altivec")
479
480TARGET_BUILTIN(__builtin_altivec_vsumsws, "V4SiV4SiV4Si", "", "altivec")
481
482TARGET_BUILTIN(__builtin_altivec_vrfiz, "V4fV4f", "", "altivec")
483
484TARGET_BUILTIN(__builtin_altivec_vupkhsb, "V8sV16c", "", "altivec")
485TARGET_BUILTIN(__builtin_altivec_vupkhpx, "V4UiV8s", "", "altivec")
486TARGET_BUILTIN(__builtin_altivec_vupkhsh, "V4iV8s", "", "altivec")
487TARGET_BUILTIN(__builtin_altivec_vupkhsw, "V2LLiV4i", "", "power8-vector")
488
489TARGET_BUILTIN(__builtin_altivec_vupklsb, "V8sV16c", "", "altivec")
490TARGET_BUILTIN(__builtin_altivec_vupklpx, "V4UiV8s", "", "altivec")
491TARGET_BUILTIN(__builtin_altivec_vupklsh, "V4iV8s", "", "altivec")
492TARGET_BUILTIN(__builtin_altivec_vupklsw, "V2LLiV4i", "", "power8-vector")
493
494TARGET_BUILTIN(__builtin_altivec_vcmpbfp_p, "iiV4fV4f", "", "altivec")
495
496TARGET_BUILTIN(__builtin_altivec_vcmpgefp_p, "iiV4fV4f", "", "altivec")
497
498TARGET_BUILTIN(__builtin_altivec_vcmpequb_p, "iiV16cV16c", "", "altivec")
499TARGET_BUILTIN(__builtin_altivec_vcmpequh_p, "iiV8sV8s", "", "altivec")
500TARGET_BUILTIN(__builtin_altivec_vcmpequw_p, "iiV4iV4i", "", "altivec")
501TARGET_BUILTIN(__builtin_altivec_vcmpequd_p, "iiV2LLiV2LLi", "", "vsx")
502TARGET_BUILTIN(__builtin_altivec_vcmpeqfp_p, "iiV4fV4f", "", "altivec")
503
504TARGET_BUILTIN(__builtin_altivec_vcmpneb_p, "iiV16cV16c", "", "power9-vector")
505TARGET_BUILTIN(__builtin_altivec_vcmpneh_p, "iiV8sV8s", "", "power9-vector")
506TARGET_BUILTIN(__builtin_altivec_vcmpnew_p, "iiV4iV4i", "", "power9-vector")
507TARGET_BUILTIN(__builtin_altivec_vcmpned_p, "iiV2LLiV2LLi", "", "vsx")
508
509TARGET_BUILTIN(__builtin_altivec_vcmpgtsb_p, "iiV16ScV16Sc", "", "altivec")
510TARGET_BUILTIN(__builtin_altivec_vcmpgtub_p, "iiV16UcV16Uc", "", "altivec")
511TARGET_BUILTIN(__builtin_altivec_vcmpgtsh_p, "iiV8SsV8Ss", "", "altivec")
512TARGET_BUILTIN(__builtin_altivec_vcmpgtuh_p, "iiV8UsV8Us", "", "altivec")
513TARGET_BUILTIN(__builtin_altivec_vcmpgtsw_p, "iiV4SiV4Si", "", "altivec")
514TARGET_BUILTIN(__builtin_altivec_vcmpgtuw_p, "iiV4UiV4Ui", "", "altivec")
515TARGET_BUILTIN(__builtin_altivec_vcmpgtsd_p, "iiV2LLiV2LLi", "", "vsx")
516TARGET_BUILTIN(__builtin_altivec_vcmpgtud_p, "iiV2ULLiV2ULLi", "", "vsx")
517TARGET_BUILTIN(__builtin_altivec_vcmpgtfp_p, "iiV4fV4f", "", "altivec")
518
519TARGET_BUILTIN(__builtin_altivec_vgbbd, "V16UcV16Uc", "", "power8-vector")
520TARGET_BUILTIN(__builtin_altivec_vbpermq, "V2ULLiV16UcV16Uc", "",
521 "power8-vector")
522TARGET_BUILTIN(__builtin_altivec_vbpermd, "V2ULLiV2ULLiV16Uc", "",
523 "power9-vector")
524
525// P8 Crypto built-ins.
526TARGET_BUILTIN(__builtin_altivec_crypto_vsbox, "V16UcV16Uc", "",
527 "power8-vector")
528TARGET_BUILTIN(__builtin_altivec_crypto_vpermxor, "V16UcV16UcV16UcV16Uc", "",
529 "power8-vector")
530TARGET_BUILTIN(__builtin_altivec_crypto_vpermxor_be, "V16UcV16UcV16UcV16Uc", "",
531 "power8-vector")
532TARGET_BUILTIN(__builtin_altivec_crypto_vshasigmaw, "V4UiV4UiIiIi", "",
533 "power8-vector")
534TARGET_BUILTIN(__builtin_altivec_crypto_vshasigmad, "V2ULLiV2ULLiIiIi", "",
535 "power8-vector")
536TARGET_BUILTIN(__builtin_altivec_crypto_vcipher, "V16UcV16UcV16Uc", "",
537 "power8-vector")
538TARGET_BUILTIN(__builtin_altivec_crypto_vcipherlast, "V16UcV16UcV16Uc", "",
539 "power8-vector")
540TARGET_BUILTIN(__builtin_altivec_crypto_vncipher, "V16UcV16UcV16Uc", "",
541 "power8-vector")
542TARGET_BUILTIN(__builtin_altivec_crypto_vncipherlast, "V16UcV16UcV16Uc", "",
543 "power8-vector")
544TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumb, "V16UcV16UcV16Uc", "",
545 "power8-vector")
546TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumh, "V8UsV8UsV8Us", "",
547 "power8-vector")
548TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumw, "V4UiV4UiV4Ui", "",
549 "power8-vector")
550TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumd, "V2ULLiV2ULLiV2ULLi", "",
551 "power8-vector")
552
553TARGET_BUILTIN(__builtin_altivec_vclzb, "V16UcV16Uc", "", "power8-vector")
554TARGET_BUILTIN(__builtin_altivec_vclzh, "V8UsV8Us", "", "power8-vector")
555TARGET_BUILTIN(__builtin_altivec_vclzw, "V4UiV4Ui", "", "power8-vector")
556TARGET_BUILTIN(__builtin_altivec_vclzd, "V2ULLiV2ULLi", "", "power8-vector")
557TARGET_BUILTIN(__builtin_altivec_vctzb, "V16UcV16Uc", "", "power9-vector")
558TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "", "power9-vector")
559TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "", "power9-vector")
560TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "", "power9-vector")
561
562// P7 BCD builtins.
563TARGET_BUILTIN(__builtin_cdtbcd, "UiUi", "", "isa-v206-instructions")
564TARGET_BUILTIN(__builtin_cbcdtd, "UiUi", "", "isa-v206-instructions")
565TARGET_BUILTIN(__builtin_addg6s, "UiUiUi", "", "isa-v206-instructions")
566
567// P7 XL Compat BCD builtins.
568TARGET_BUILTIN(__builtin_ppc_cdtbcd, "LLiLLi", "", "isa-v206-instructions")
569TARGET_BUILTIN(__builtin_ppc_cbcdtd, "LLiLLi", "", "isa-v206-instructions")
570TARGET_BUILTIN(__builtin_ppc_addg6s, "LLiLLiLLi", "", "isa-v206-instructions")
571
572// P8 BCD builtins.
573TARGET_BUILTIN(__builtin_ppc_bcdadd, "V16UcV16UcV16UcIi", "",
574 "isa-v207-instructions")
575TARGET_BUILTIN(__builtin_ppc_bcdsub, "V16UcV16UcV16UcIi", "",
576 "isa-v207-instructions")
577TARGET_BUILTIN(__builtin_ppc_bcdadd_p, "iiV16UcV16Uc", "",
578 "isa-v207-instructions")
579TARGET_BUILTIN(__builtin_ppc_bcdsub_p, "iiV16UcV16Uc", "",
580 "isa-v207-instructions")
581
582// P9 Binary-coded decimal (BCD) builtins.
583TARGET_BUILTIN(__builtin_ppc_bcdcopysign, "V16UcV16UcV16Uc", "", "power9-vector")
584TARGET_BUILTIN(__builtin_ppc_bcdsetsign, "V16UcV16UcUc", "t", "power9-vector")
585TARGET_BUILTIN(__builtin_ppc_bcdshift, "V16UcV16UciUc", "t", "power9-vector")
586TARGET_BUILTIN(__builtin_ppc_bcdshiftround, "V16UcV16UciUc", "t", "power9-vector")
587TARGET_BUILTIN(__builtin_ppc_bcdtruncate, "V16UcV16UciUc", "t", "power9-vector")
588TARGET_BUILTIN(__builtin_ppc_bcdunsignedtruncate, "V16UcV16Uci", "", "power9-vector")
589TARGET_BUILTIN(__builtin_ppc_bcdunsignedshift, "V16UcV16Uci", "", "power9-vector")
590TARGET_BUILTIN(__builtin_ppc_national2packed, "V16UcV16UcUc", "t", "power9-vector")
591TARGET_BUILTIN(__builtin_ppc_packed2national, "V16UcV16Uc", "", "power9-vector")
592TARGET_BUILTIN(__builtin_ppc_packed2zoned, "V16UcV16UcUc", "t", "power9-vector")
593TARGET_BUILTIN(__builtin_ppc_zoned2packed, "V16UcV16UcUc", "t", "power9-vector")
594
595TARGET_BUILTIN(__builtin_altivec_vclzlsbb, "SiV16Uc", "", "power9-vector")
596TARGET_BUILTIN(__builtin_altivec_vctzlsbb, "SiV16Uc", "", "power9-vector")
597TARGET_BUILTIN(__builtin_altivec_vprtybw, "V4UiV4Ui", "", "power9-vector")
598TARGET_BUILTIN(__builtin_altivec_vprtybd, "V2ULLiV2ULLi", "", "power9-vector")
599TARGET_BUILTIN(__builtin_altivec_vprtybq, "V1ULLLiV1ULLLi", "", "power9-vector")
600
601// Absolute difference built-ins
602TARGET_BUILTIN(__builtin_altivec_vabsdub, "V16UcV16UcV16Uc", "",
603 "power9-vector")
604TARGET_BUILTIN(__builtin_altivec_vabsduh, "V8UsV8UsV8Us", "", "power9-vector")
605TARGET_BUILTIN(__builtin_altivec_vabsduw, "V4UiV4UiV4Ui", "", "power9-vector")
606
607// P9 Shift built-ins.
608TARGET_BUILTIN(__builtin_altivec_vslv, "V16UcV16UcV16Uc", "", "power9-vector")
609TARGET_BUILTIN(__builtin_altivec_vsrv, "V16UcV16UcV16Uc", "", "power9-vector")
610
611// P9 Vector rotate built-ins
612TARGET_BUILTIN(__builtin_altivec_vrlwmi, "V4UiV4UiV4UiV4Ui", "",
613 "power9-vector")
614TARGET_BUILTIN(__builtin_altivec_vrldmi, "V2ULLiV2ULLiV2ULLiV2ULLi", "",
615 "power9-vector")
616TARGET_BUILTIN(__builtin_altivec_vrlwnm, "V4UiV4UiV4Ui", "", "power9-vector")
617TARGET_BUILTIN(__builtin_altivec_vrldnm, "V2ULLiV2ULLiV2ULLi", "",
618 "power9-vector")
619
620// P9 Vector extend sign builtins.
621TARGET_BUILTIN(__builtin_altivec_vextsb2w, "V4SiV16Sc", "", "power9-vector")
622TARGET_BUILTIN(__builtin_altivec_vextsb2d, "V2SLLiV16Sc", "", "power9-vector")
623TARGET_BUILTIN(__builtin_altivec_vextsh2w, "V4SiV8Ss", "", "power9-vector")
624TARGET_BUILTIN(__builtin_altivec_vextsh2d, "V2SLLiV8Ss", "", "power9-vector")
625TARGET_BUILTIN(__builtin_altivec_vextsw2d, "V2SLLiV4Si", "", "power9-vector")
626
627// P10 Vector extend sign builtins.
628TARGET_BUILTIN(__builtin_altivec_vextsd2q, "V1SLLLiV2SLLi", "",
629 "power10-vector")
630
631// P10 Vector Extract with Mask built-ins.
632TARGET_BUILTIN(__builtin_altivec_vextractbm, "UiV16Uc", "", "power10-vector")
633TARGET_BUILTIN(__builtin_altivec_vextracthm, "UiV8Us", "", "power10-vector")
634TARGET_BUILTIN(__builtin_altivec_vextractwm, "UiV4Ui", "", "power10-vector")
635TARGET_BUILTIN(__builtin_altivec_vextractdm, "UiV2ULLi", "", "power10-vector")
636TARGET_BUILTIN(__builtin_altivec_vextractqm, "UiV1ULLLi", "", "power10-vector")
637
638// P10 Vector Divide Extended built-ins.
639TARGET_BUILTIN(__builtin_altivec_vdivesw, "V4SiV4SiV4Si", "", "power10-vector")
640TARGET_BUILTIN(__builtin_altivec_vdiveuw, "V4UiV4UiV4Ui", "", "power10-vector")
641TARGET_BUILTIN(__builtin_altivec_vdivesd, "V2LLiV2LLiV2LLi", "",
642 "power10-vector")
643TARGET_BUILTIN(__builtin_altivec_vdiveud, "V2ULLiV2ULLiV2ULLi", "",
644 "power10-vector")
645TARGET_BUILTIN(__builtin_altivec_vdivesq, "V1SLLLiV1SLLLiV1SLLLi", "",
646 "power10-vector")
647TARGET_BUILTIN(__builtin_altivec_vdiveuq, "V1ULLLiV1ULLLiV1ULLLi", "",
648 "power10-vector")
649
650// P10 Vector Multiply High built-ins.
651TARGET_BUILTIN(__builtin_altivec_vmulhsw, "V4SiV4SiV4Si", "", "power10-vector")
652TARGET_BUILTIN(__builtin_altivec_vmulhuw, "V4UiV4UiV4Ui", "", "power10-vector")
653TARGET_BUILTIN(__builtin_altivec_vmulhsd, "V2LLiV2LLiV2LLi", "",
654 "power10-vector")
655TARGET_BUILTIN(__builtin_altivec_vmulhud, "V2ULLiV2ULLiV2ULLi", "",
656 "power10-vector")
657
658// P10 Vector Expand with Mask built-ins.
659TARGET_BUILTIN(__builtin_altivec_vexpandbm, "V16UcV16Uc", "", "power10-vector")
660TARGET_BUILTIN(__builtin_altivec_vexpandhm, "V8UsV8Us", "", "power10-vector")
661TARGET_BUILTIN(__builtin_altivec_vexpandwm, "V4UiV4Ui", "", "power10-vector")
662TARGET_BUILTIN(__builtin_altivec_vexpanddm, "V2ULLiV2ULLi", "",
663 "power10-vector")
664TARGET_BUILTIN(__builtin_altivec_vexpandqm, "V1ULLLiV1ULLLi", "",
665 "power10-vector")
666
667// P10 Vector Count with Mask built-ins.
668TARGET_BUILTIN(__builtin_altivec_vcntmbb, "ULLiV16UcUi", "", "power10-vector")
669TARGET_BUILTIN(__builtin_altivec_vcntmbh, "ULLiV8UsUi", "", "power10-vector")
670TARGET_BUILTIN(__builtin_altivec_vcntmbw, "ULLiV4UiUi", "", "power10-vector")
671TARGET_BUILTIN(__builtin_altivec_vcntmbd, "ULLiV2ULLiUi", "", "power10-vector")
672
673// P10 Move to VSR with Mask built-ins.
674TARGET_BUILTIN(__builtin_altivec_mtvsrbm, "V16UcULLi", "", "power10-vector")
675TARGET_BUILTIN(__builtin_altivec_mtvsrhm, "V8UsULLi", "", "power10-vector")
676TARGET_BUILTIN(__builtin_altivec_mtvsrwm, "V4UiULLi", "", "power10-vector")
677TARGET_BUILTIN(__builtin_altivec_mtvsrdm, "V2ULLiULLi", "", "power10-vector")
678TARGET_BUILTIN(__builtin_altivec_mtvsrqm, "V1ULLLiULLi", "", "power10-vector")
679
680// P10 Vector Parallel Bits built-ins.
681TARGET_BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "",
682 "power10-vector")
683TARGET_BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "",
684 "power10-vector")
685
686// P10 Vector String Isolate Built-ins.
687TARGET_BUILTIN(__builtin_altivec_vstribr, "V16UcV16Uc", "", "power10-vector")
688TARGET_BUILTIN(__builtin_altivec_vstribl, "V16UcV16Uc", "", "power10-vector")
689TARGET_BUILTIN(__builtin_altivec_vstrihr, "V8sV8s", "", "power10-vector")
690TARGET_BUILTIN(__builtin_altivec_vstrihl, "V8sV8s", "", "power10-vector")
691TARGET_BUILTIN(__builtin_altivec_vstribr_p, "iiV16Uc", "", "power10-vector")
692TARGET_BUILTIN(__builtin_altivec_vstribl_p, "iiV16Uc", "", "power10-vector")
693TARGET_BUILTIN(__builtin_altivec_vstrihr_p, "iiV8s", "", "power10-vector")
694TARGET_BUILTIN(__builtin_altivec_vstrihl_p, "iiV8s", "", "power10-vector")
695
696// P10 Vector Centrifuge built-in.
697TARGET_BUILTIN(__builtin_altivec_vcfuged, "V2ULLiV2ULLiV2ULLi", "",
698 "power10-vector")
699
700// P10 Vector Gather Every N-th Bit built-in.
701TARGET_BUILTIN(__builtin_altivec_vgnb, "ULLiV1ULLLiIi", "", "power10-vector")
702
703// P10 Vector Clear Bytes built-ins.
704TARGET_BUILTIN(__builtin_altivec_vclrlb, "V16UcV16UcUi", "", "power10-vector")
705TARGET_BUILTIN(__builtin_altivec_vclrrb, "V16UcV16UcUi", "", "power10-vector")
706
707// P10 Vector Count Leading / Trailing Zeroes under bit Mask built-ins.
708TARGET_BUILTIN(__builtin_altivec_vclzdm, "V2ULLiV2ULLiV2ULLi", "",
709 "power10-vector")
710TARGET_BUILTIN(__builtin_altivec_vctzdm, "V2ULLiV2ULLiV2ULLi", "",
711 "power10-vector")
712
713// P10 Vector Shift built-ins.
714TARGET_BUILTIN(__builtin_altivec_vsldbi, "V16UcV16UcV16UcIi", "",
715 "power10-vector")
716TARGET_BUILTIN(__builtin_altivec_vsrdbi, "V16UcV16UcV16UcIi", "",
717 "power10-vector")
718
719// P10 Vector Insert built-ins.
720TARGET_BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcUiUi", "",
721 "power10-vector")
722TARGET_BUILTIN(__builtin_altivec_vinsbrx, "V16UcV16UcUiUi", "",
723 "power10-vector")
724TARGET_BUILTIN(__builtin_altivec_vinshlx, "V8UsV8UsUiUi", "", "power10-vector")
725TARGET_BUILTIN(__builtin_altivec_vinshrx, "V8UsV8UsUiUi", "", "power10-vector")
726TARGET_BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiUiUi", "", "power10-vector")
727TARGET_BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiUiUi", "", "power10-vector")
728TARGET_BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiV2ULLiULLiULLi", "",
729 "power10-vector")
730TARGET_BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiV2ULLiULLiULLi", "",
731 "power10-vector")
732TARGET_BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcUiV16Uc", "",
733 "power10-vector")
734TARGET_BUILTIN(__builtin_altivec_vinsbvrx, "V16UcV16UcUiV16Uc", "",
735 "power10-vector")
736TARGET_BUILTIN(__builtin_altivec_vinshvlx, "V8UsV8UsUiV8Us", "",
737 "power10-vector")
738TARGET_BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsUiV8Us", "",
739 "power10-vector")
740TARGET_BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiUiV4Ui", "",
741 "power10-vector")
742TARGET_BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiUiV4Ui", "",
743 "power10-vector")
744TARGET_BUILTIN(__builtin_altivec_vinsw, "V16UcV16UcUiIi", "", "power10-vector")
745TARGET_BUILTIN(__builtin_altivec_vinsd, "V16UcV16UcULLiIi", "",
746 "power10-vector")
747TARGET_BUILTIN(__builtin_altivec_vinsw_elt, "V16UcV16UcUiiC", "",
748 "power10-vector")
749TARGET_BUILTIN(__builtin_altivec_vinsd_elt, "V16UcV16UcULLiiC", "",
750 "power10-vector")
751
752// P10 Vector Extract built-ins.
753TARGET_BUILTIN(__builtin_altivec_vextdubvlx, "V2ULLiV16UcV16UcUi", "",
754 "power10-vector")
755TARGET_BUILTIN(__builtin_altivec_vextdubvrx, "V2ULLiV16UcV16UcUi", "",
756 "power10-vector")
757TARGET_BUILTIN(__builtin_altivec_vextduhvlx, "V2ULLiV8UsV8UsUi", "",
758 "power10-vector")
759TARGET_BUILTIN(__builtin_altivec_vextduhvrx, "V2ULLiV8UsV8UsUi", "",
760 "power10-vector")
761TARGET_BUILTIN(__builtin_altivec_vextduwvlx, "V2ULLiV4UiV4UiUi", "",
762 "power10-vector")
763TARGET_BUILTIN(__builtin_altivec_vextduwvrx, "V2ULLiV4UiV4UiUi", "",
764 "power10-vector")
765TARGET_BUILTIN(__builtin_altivec_vextddvlx, "V2ULLiV2ULLiV2ULLiUi", "",
766 "power10-vector")
767TARGET_BUILTIN(__builtin_altivec_vextddvrx, "V2ULLiV2ULLiV2ULLiUi", "",
768 "power10-vector")
769
770// P10 Vector rotate built-ins.
771TARGET_BUILTIN(__builtin_altivec_vrlqmi, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "",
772 "power10-vector")
773TARGET_BUILTIN(__builtin_altivec_vrlqnm, "V1ULLLiV1ULLLiV1ULLLi", "",
774 "power10-vector")
775
776// VSX built-ins.
777
778TARGET_BUILTIN(__builtin_vsx_lxvd2x, "V2dLivC*", "", "vsx")
779TARGET_BUILTIN(__builtin_vsx_lxvw4x, "V4iLivC*", "", "vsx")
780TARGET_BUILTIN(__builtin_vsx_lxvd2x_be, "V2dSLLivC*", "", "vsx")
781TARGET_BUILTIN(__builtin_vsx_lxvw4x_be, "V4iSLLivC*", "", "vsx")
782
783TARGET_BUILTIN(__builtin_vsx_stxvd2x, "vV2dLiv*", "", "vsx")
784TARGET_BUILTIN(__builtin_vsx_stxvw4x, "vV4iLiv*", "", "vsx")
785TARGET_BUILTIN(__builtin_vsx_stxvd2x_be, "vV2dSLLivC*", "", "vsx")
786TARGET_BUILTIN(__builtin_vsx_stxvw4x_be, "vV4iSLLivC*", "", "vsx")
787
788TARGET_BUILTIN(__builtin_vsx_lxvl, "V4ivC*ULLi", "", "power9-vector")
789TARGET_BUILTIN(__builtin_vsx_lxvll, "V4ivC*ULLi", "", "power9-vector")
790TARGET_BUILTIN(__builtin_vsx_stxvl, "vV4iv*ULLi", "", "power9-vector")
791TARGET_BUILTIN(__builtin_vsx_stxvll, "vV4iv*ULLi", "", "power9-vector")
792TARGET_BUILTIN(__builtin_vsx_ldrmb, "V16UcCc*Ii", "", "isa-v207-instructions")
793TARGET_BUILTIN(__builtin_vsx_strmb, "vCc*IiV16Uc", "", "isa-v207-instructions")
794
795TARGET_BUILTIN(__builtin_vsx_xvmaxdp, "V2dV2dV2d", "", "vsx")
796TARGET_BUILTIN(__builtin_vsx_xvmaxsp, "V4fV4fV4f", "", "vsx")
797TARGET_BUILTIN(__builtin_vsx_xsmaxdp, "ddd", "", "vsx")
798
799TARGET_BUILTIN(__builtin_vsx_xvmindp, "V2dV2dV2d", "", "vsx")
800TARGET_BUILTIN(__builtin_vsx_xvminsp, "V4fV4fV4f", "", "vsx")
801TARGET_BUILTIN(__builtin_vsx_xsmindp, "ddd", "", "vsx")
802
803TARGET_BUILTIN(__builtin_vsx_xvdivdp, "V2dV2dV2d", "", "vsx")
804TARGET_BUILTIN(__builtin_vsx_xvdivsp, "V4fV4fV4f", "", "vsx")
805
806TARGET_BUILTIN(__builtin_vsx_xvrdpip, "V2dV2d", "", "vsx")
807TARGET_BUILTIN(__builtin_vsx_xvrspip, "V4fV4f", "", "vsx")
808
809TARGET_BUILTIN(__builtin_vsx_xvcmpeqdp, "V2ULLiV2dV2d", "", "vsx")
810TARGET_BUILTIN(__builtin_vsx_xvcmpeqsp, "V4UiV4fV4f", "", "vsx")
811
812TARGET_BUILTIN(__builtin_vsx_xvcmpeqdp_p, "iiV2dV2d", "", "vsx")
813TARGET_BUILTIN(__builtin_vsx_xvcmpeqsp_p, "iiV4fV4f", "", "vsx")
814
815TARGET_BUILTIN(__builtin_vsx_xvcmpgedp, "V2ULLiV2dV2d", "", "vsx")
816TARGET_BUILTIN(__builtin_vsx_xvcmpgesp, "V4UiV4fV4f", "", "vsx")
817
818TARGET_BUILTIN(__builtin_vsx_xvcmpgedp_p, "iiV2dV2d", "", "vsx")
819TARGET_BUILTIN(__builtin_vsx_xvcmpgesp_p, "iiV4fV4f", "", "vsx")
820
821TARGET_BUILTIN(__builtin_vsx_xvcmpgtdp, "V2ULLiV2dV2d", "", "vsx")
822TARGET_BUILTIN(__builtin_vsx_xvcmpgtsp, "V4UiV4fV4f", "", "vsx")
823
824TARGET_BUILTIN(__builtin_vsx_xvcmpgtdp_p, "iiV2dV2d", "", "vsx")
825TARGET_BUILTIN(__builtin_vsx_xvcmpgtsp_p, "iiV4fV4f", "", "vsx")
826
827TARGET_BUILTIN(__builtin_vsx_xvrdpim, "V2dV2d", "", "vsx")
828TARGET_BUILTIN(__builtin_vsx_xvrspim, "V4fV4f", "", "vsx")
829
830TARGET_BUILTIN(__builtin_vsx_xvrdpi, "V2dV2d", "", "vsx")
831TARGET_BUILTIN(__builtin_vsx_xvrspi, "V4fV4f", "", "vsx")
832
833TARGET_BUILTIN(__builtin_vsx_xvrdpic, "V2dV2d", "", "vsx")
834TARGET_BUILTIN(__builtin_vsx_xvrspic, "V4fV4f", "", "vsx")
835
836TARGET_BUILTIN(__builtin_vsx_xvrdpiz, "V2dV2d", "", "vsx")
837TARGET_BUILTIN(__builtin_vsx_xvrspiz, "V4fV4f", "", "vsx")
838
839TARGET_BUILTIN(__builtin_vsx_xvmaddadp, "V2dV2dV2dV2d", "", "vsx")
840TARGET_BUILTIN(__builtin_vsx_xvmaddasp, "V4fV4fV4fV4f", "", "vsx")
841
842TARGET_BUILTIN(__builtin_vsx_xvmsubadp, "V2dV2dV2dV2d", "", "vsx")
843TARGET_BUILTIN(__builtin_vsx_xvmsubasp, "V4fV4fV4fV4f", "", "vsx")
844
845TARGET_BUILTIN(__builtin_vsx_xvmuldp, "V2dV2dV2d", "", "vsx")
846TARGET_BUILTIN(__builtin_vsx_xvmulsp, "V4fV4fV4f", "", "vsx")
847
848TARGET_BUILTIN(__builtin_vsx_xvnmaddadp, "V2dV2dV2dV2d", "", "vsx")
849TARGET_BUILTIN(__builtin_vsx_xvnmaddasp, "V4fV4fV4fV4f", "", "vsx")
850
851TARGET_BUILTIN(__builtin_vsx_xvnmsubadp, "V2dV2dV2dV2d", "", "vsx")
852TARGET_BUILTIN(__builtin_vsx_xvnmsubasp, "V4fV4fV4fV4f", "", "vsx")
853
854TARGET_BUILTIN(__builtin_vsx_xvredp, "V2dV2d", "", "vsx")
855TARGET_BUILTIN(__builtin_vsx_xvresp, "V4fV4f", "", "vsx")
856
857TARGET_BUILTIN(__builtin_vsx_xvrsqrtedp, "V2dV2d", "", "vsx")
858TARGET_BUILTIN(__builtin_vsx_xvrsqrtesp, "V4fV4f", "", "vsx")
859
860TARGET_BUILTIN(__builtin_vsx_xvsqrtdp, "V2dV2d", "", "vsx")
861TARGET_BUILTIN(__builtin_vsx_xvsqrtsp, "V4fV4f", "", "vsx")
862
863TARGET_BUILTIN(__builtin_vsx_xxleqv, "V4UiV4UiV4Ui", "", "power8-vector")
864
865TARGET_BUILTIN(__builtin_vsx_xvcpsgndp, "V2dV2dV2d", "", "vsx")
866TARGET_BUILTIN(__builtin_vsx_xvcpsgnsp, "V4fV4fV4f", "", "vsx")
867
868TARGET_BUILTIN(__builtin_vsx_xvabssp, "V4fV4f", "", "vsx")
869TARGET_BUILTIN(__builtin_vsx_xvabsdp, "V2dV2d", "", "vsx")
870
871TARGET_BUILTIN(__builtin_vsx_xxgenpcvbm, "V16UcV16Uci", "", "power10-vector")
872TARGET_BUILTIN(__builtin_vsx_xxgenpcvhm, "V8UsV8Usi", "", "power10-vector")
873TARGET_BUILTIN(__builtin_vsx_xxgenpcvwm, "V4UiV4Uii", "", "power10-vector")
874TARGET_BUILTIN(__builtin_vsx_xxgenpcvdm, "V2ULLiV2ULLii", "", "power10-vector")
875
876// vector Insert/Extract exponent/significand builtins
877TARGET_BUILTIN(__builtin_vsx_xviexpdp, "V2dV2ULLiV2ULLi", "", "power9-vector")
878TARGET_BUILTIN(__builtin_vsx_xviexpsp, "V4fV4UiV4Ui", "", "power9-vector")
879TARGET_BUILTIN(__builtin_vsx_xvxexpdp, "V2ULLiV2d", "", "power9-vector")
880TARGET_BUILTIN(__builtin_vsx_xvxexpsp, "V4UiV4f", "", "power9-vector")
881TARGET_BUILTIN(__builtin_vsx_xvxsigdp, "V2ULLiV2d", "", "power9-vector")
882TARGET_BUILTIN(__builtin_vsx_xvxsigsp, "V4UiV4f", "", "power9-vector")
883
884// Conversion builtins
885TARGET_BUILTIN(__builtin_vsx_xvcvdpsxws, "V4SiV2d", "", "vsx")
886TARGET_BUILTIN(__builtin_vsx_xvcvdpuxws, "V4UiV2d", "", "vsx")
887TARGET_BUILTIN(__builtin_vsx_xvcvspsxds, "V2SLLiV4f", "", "vsx")
888TARGET_BUILTIN(__builtin_vsx_xvcvspuxds, "V2ULLiV4f", "", "vsx")
889TARGET_BUILTIN(__builtin_vsx_xvcvsxwdp, "V2dV4Si", "", "vsx")
890TARGET_BUILTIN(__builtin_vsx_xvcvuxwdp, "V2dV4Ui", "", "vsx")
891TARGET_BUILTIN(__builtin_vsx_xvcvspdp, "V2dV4f", "", "vsx")
892TARGET_BUILTIN(__builtin_vsx_xvcvsxdsp, "V4fV2SLLi", "", "vsx")
893TARGET_BUILTIN(__builtin_vsx_xvcvuxdsp, "V4fV2ULLi", "", "vsx")
894TARGET_BUILTIN(__builtin_vsx_xvcvdpsp, "V4fV2d", "", "vsx")
895
896TARGET_BUILTIN(__builtin_vsx_xvcvsphp, "V4fV4f", "", "power9-vector")
897TARGET_BUILTIN(__builtin_vsx_xvcvhpsp, "V4fV8Us", "", "power9-vector")
898
899TARGET_BUILTIN(__builtin_vsx_xvcvspbf16, "V16UcV16Uc", "", "power10-vector")
900TARGET_BUILTIN(__builtin_vsx_xvcvbf16spn, "V16UcV16Uc", "", "power10-vector")
901
902// Vector Test Data Class builtins
903TARGET_BUILTIN(__builtin_vsx_xvtstdcdp, "V2ULLiV2dIi", "", "power9-vector")
904TARGET_BUILTIN(__builtin_vsx_xvtstdcsp, "V4UiV4fIi", "", "power9-vector")
905
906TARGET_BUILTIN(__builtin_vsx_insertword, "V16UcV4UiV16UcIi", "", "vsx")
907TARGET_BUILTIN(__builtin_vsx_extractuword, "V2ULLiV16UcIi", "", "vsx")
908
909TARGET_BUILTIN(__builtin_vsx_xxpermdi, "v.", "t", "vsx")
910TARGET_BUILTIN(__builtin_vsx_xxsldwi, "v.", "t", "vsx")
911
912TARGET_BUILTIN(__builtin_vsx_xxeval, "V2ULLiV2ULLiV2ULLiV2ULLiIi", "",
913 "power10-vector")
914
915TARGET_BUILTIN(__builtin_vsx_xvtlsbb, "iV16UcUi", "", "power10-vector")
916
917TARGET_BUILTIN(__builtin_vsx_xvtdivdp, "iV2dV2d", "", "vsx")
918TARGET_BUILTIN(__builtin_vsx_xvtdivsp, "iV4fV4f", "", "vsx")
919TARGET_BUILTIN(__builtin_vsx_xvtsqrtdp, "iV2d", "", "vsx")
920TARGET_BUILTIN(__builtin_vsx_xvtsqrtsp, "iV4f", "", "vsx")
921
922// P10 Vector Permute Extended built-in.
923TARGET_BUILTIN(__builtin_vsx_xxpermx, "V16UcV16UcV16UcV16UcIi", "",
924 "power10-vector")
925
926// P10 Vector Blend built-ins.
927TARGET_BUILTIN(__builtin_vsx_xxblendvb, "V16UcV16UcV16UcV16Uc", "",
928 "power10-vector")
929TARGET_BUILTIN(__builtin_vsx_xxblendvh, "V8UsV8UsV8UsV8Us", "",
930 "power10-vector")
931TARGET_BUILTIN(__builtin_vsx_xxblendvw, "V4UiV4UiV4UiV4Ui", "",
932 "power10-vector")
933TARGET_BUILTIN(__builtin_vsx_xxblendvd, "V2ULLiV2ULLiV2ULLiV2ULLi", "",
934 "power10-vector")
935
936// Float 128 built-ins
937TARGET_BUILTIN(__builtin_sqrtf128_round_to_odd, "LLdLLd", "", "float128")
938TARGET_BUILTIN(__builtin_addf128_round_to_odd, "LLdLLdLLd", "", "float128")
939TARGET_BUILTIN(__builtin_subf128_round_to_odd, "LLdLLdLLd", "", "float128")
940TARGET_BUILTIN(__builtin_mulf128_round_to_odd, "LLdLLdLLd", "", "float128")
941TARGET_BUILTIN(__builtin_divf128_round_to_odd, "LLdLLdLLd", "", "float128")
942TARGET_BUILTIN(__builtin_fmaf128_round_to_odd, "LLdLLdLLdLLd", "", "float128")
943TARGET_BUILTIN(__builtin_truncf128_round_to_odd, "dLLd", "", "float128")
944TARGET_BUILTIN(__builtin_vsx_scalar_extract_expq, "ULLiLLd", "", "float128")
945TARGET_BUILTIN(__builtin_vsx_scalar_insert_exp_qp, "LLdLLdULLi", "", "float128")
946
947// Fastmath by default builtins
948BUILTIN(__builtin_ppc_rsqrtf, "V4fV4f", "")
949BUILTIN(__builtin_ppc_rsqrtd, "V2dV2d", "")
950BUILTIN(__builtin_ppc_recipdivf, "V4fV4fV4f", "")
951BUILTIN(__builtin_ppc_recipdivd, "V2dV2dV2d", "")
952
953// HTM builtins
954TARGET_BUILTIN(__builtin_tbegin, "UiUIi", "", "htm")
955TARGET_BUILTIN(__builtin_tend, "UiUIi", "", "htm")
956
957TARGET_BUILTIN(__builtin_tabort, "UiUi", "", "htm")
958TARGET_BUILTIN(__builtin_tabortdc, "UiUiUiUi", "", "htm")
959TARGET_BUILTIN(__builtin_tabortdci, "UiUiUii", "", "htm")
960TARGET_BUILTIN(__builtin_tabortwc, "UiUiUiUi", "", "htm")
961TARGET_BUILTIN(__builtin_tabortwci, "UiUiUii", "", "htm")
962
963TARGET_BUILTIN(__builtin_tcheck, "Ui", "", "htm")
964TARGET_BUILTIN(__builtin_treclaim, "UiUi", "", "htm")
965TARGET_BUILTIN(__builtin_trechkpt, "Ui", "", "htm")
966TARGET_BUILTIN(__builtin_tsr, "UiUi", "", "htm")
967
968TARGET_BUILTIN(__builtin_tendall, "Ui", "", "htm")
969TARGET_BUILTIN(__builtin_tresume, "Ui", "", "htm")
970TARGET_BUILTIN(__builtin_tsuspend, "Ui", "", "htm")
971
972TARGET_BUILTIN(__builtin_get_texasr, "LUi", "c", "htm")
973TARGET_BUILTIN(__builtin_get_texasru, "LUi", "c", "htm")
974TARGET_BUILTIN(__builtin_get_tfhar, "LUi", "c", "htm")
975TARGET_BUILTIN(__builtin_get_tfiar, "LUi", "c", "htm")
976
977TARGET_BUILTIN(__builtin_set_texasr, "vLUi", "c", "htm")
978TARGET_BUILTIN(__builtin_set_texasru, "vLUi", "c", "htm")
979TARGET_BUILTIN(__builtin_set_tfhar, "vLUi", "c", "htm")
980TARGET_BUILTIN(__builtin_set_tfiar, "vLUi", "c", "htm")
981
982TARGET_BUILTIN(__builtin_ttest, "LUi", "", "htm")
983
984// Scalar built-ins
985TARGET_BUILTIN(__builtin_divwe, "SiSiSi", "", "extdiv")
986TARGET_BUILTIN(__builtin_divweu, "UiUiUi", "", "extdiv")
987TARGET_BUILTIN(__builtin_divde, "SLLiSLLiSLLi", "", "extdiv")
988TARGET_BUILTIN(__builtin_divdeu, "ULLiULLiULLi", "", "extdiv")
989TARGET_BUILTIN(__builtin_bpermd, "SLLiSLLiSLLi", "", "bpermd")
990TARGET_BUILTIN(__builtin_pdepd, "ULLiULLiULLi", "", "isa-v31-instructions")
991TARGET_BUILTIN(__builtin_pextd, "ULLiULLiULLi", "", "isa-v31-instructions")
992TARGET_BUILTIN(__builtin_cfuged, "ULLiULLiULLi", "", "isa-v31-instructions")
993TARGET_BUILTIN(__builtin_cntlzdm, "ULLiULLiULLi", "", "isa-v31-instructions")
994TARGET_BUILTIN(__builtin_cnttzdm, "ULLiULLiULLi", "", "isa-v31-instructions")
995
996// Double-double (un)pack
997BUILTIN(__builtin_unpack_longdouble, "dLdIi", "")
998BUILTIN(__builtin_pack_longdouble, "Lddd", "")
999
1000// Generate random number
1001TARGET_BUILTIN(__builtin_darn, "LLi", "", "isa-v30-instructions")
1002TARGET_BUILTIN(__builtin_darn_raw, "LLi", "", "isa-v30-instructions")
1003TARGET_BUILTIN(__builtin_darn_32, "i", "", "isa-v30-instructions")
1004
1005// Vector int128 (un)pack
1006TARGET_BUILTIN(__builtin_unpack_vector_int128, "ULLiV1LLLii", "", "vsx")
1007TARGET_BUILTIN(__builtin_pack_vector_int128, "V1LLLiULLiULLi", "", "vsx")
1008
1009// AMO builtins
1010TARGET_BUILTIN(__builtin_amo_lwat, "UiUi*UiIi", "", "isa-v30-instructions")
1011TARGET_BUILTIN(__builtin_amo_ldat, "ULiULi*ULiIi", "", "isa-v30-instructions")
1012TARGET_BUILTIN(__builtin_amo_lwat_s, "SiSi*SiIi", "", "isa-v30-instructions")
1013TARGET_BUILTIN(__builtin_amo_ldat_s, "SLiSLi*SLiIi", "", "isa-v30-instructions")
1014TARGET_BUILTIN(__builtin_amo_lwat_cond, "UiUi*Ii", "", "isa-v30-instructions")
1015TARGET_BUILTIN(__builtin_amo_ldat_cond, "ULiULi*Ii", "", "isa-v30-instructions")
1016TARGET_BUILTIN(__builtin_amo_lwat_cond_s, "SiSi*Ii", "", "isa-v30-instructions")
1017TARGET_BUILTIN(__builtin_amo_ldat_cond_s, "SLiSLi*Ii", "", "isa-v30-instructions")
1018TARGET_BUILTIN(__builtin_amo_stwat, "vUi*UiIi", "", "isa-v30-instructions")
1019TARGET_BUILTIN(__builtin_amo_stdat, "vULi*ULiIi", "", "isa-v30-instructions")
1020TARGET_BUILTIN(__builtin_amo_stwat_s, "vSi*SiIi", "", "isa-v30-instructions")
1021TARGET_BUILTIN(__builtin_amo_stdat_s, "vSLi*SLiIi", "", "isa-v30-instructions")
1022
1023
1024// Set the floating point rounding mode
1025BUILTIN(__builtin_setrnd, "di", "")
1026
1027// Get content from current FPSCR
1028BUILTIN(__builtin_readflm, "d", "")
1029
1030// Set content of FPSCR, and return its content before update
1031BUILTIN(__builtin_setflm, "dd", "")
1032
1033// Cache built-ins
1034BUILTIN(__builtin_dcbf, "vvC*", "")
1035
1036// Provided builtins with _mma_ prefix for compatibility.
1037CUSTOM_BUILTIN(mma_lxvp, vsx_lxvp, "W256SLiW256C*", false,
1038 "paired-vector-memops")
1039CUSTOM_BUILTIN(mma_stxvp, vsx_stxvp, "vW256SLiW256*", false,
1040 "paired-vector-memops")
1041CUSTOM_BUILTIN(mma_assemble_pair, vsx_assemble_pair, "vW256*VV", false,
1042 "paired-vector-memops")
1043CUSTOM_BUILTIN(mma_disassemble_pair, vsx_disassemble_pair, "vv*W256*", false,
1044 "paired-vector-memops")
1045CUSTOM_BUILTIN(vsx_build_pair, vsx_assemble_pair, "vW256*VV", false,
1046 "paired-vector-memops")
1047CUSTOM_BUILTIN(mma_build_acc, mma_assemble_acc, "vW512*VVVV", false, "mma")
1048
1049UNALIASED_CUSTOM_BUILTIN(vsx_lxvp, "W256SLiW256C*", false,
1050 "paired-vector-memops")
1051UNALIASED_CUSTOM_BUILTIN(vsx_stxvp, "vW256SLiW256*", false,
1052 "paired-vector-memops")
1053UNALIASED_CUSTOM_BUILTIN(vsx_assemble_pair, "vW256*VV", false,
1054 "paired-vector-memops")
1055UNALIASED_CUSTOM_BUILTIN(vsx_disassemble_pair, "vv*W256*", false,
1056 "paired-vector-memops")
1057
1058// TODO: Require only mma after backend supports these without paired memops
1059UNALIASED_CUSTOM_BUILTIN(mma_assemble_acc, "vW512*VVVV", false,
1060 "mma,paired-vector-memops")
1061UNALIASED_CUSTOM_BUILTIN(mma_disassemble_acc, "vv*W512*", false,
1062 "mma,paired-vector-memops")
1063UNALIASED_CUSTOM_BUILTIN(mma_xxmtacc, "vW512*", true,
1064 "mma,paired-vector-memops")
1065UNALIASED_CUSTOM_BUILTIN(mma_xxmfacc, "vW512*", true,
1066 "mma,paired-vector-memops")
1067UNALIASED_CUSTOM_BUILTIN(mma_xxsetaccz, "vW512*", false,
1068 "mma,paired-vector-memops")
1069UNALIASED_CUSTOM_BUILTIN(mma_xvi4ger8, "vW512*VV", false,
1070 "mma,paired-vector-memops")
1071UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4, "vW512*VV", false,
1072 "mma,paired-vector-memops")
1073UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2, "vW512*VV", false,
1074 "mma,paired-vector-memops")
1075UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2s, "vW512*VV", false,
1076 "mma,paired-vector-memops")
1077UNALIASED_CUSTOM_BUILTIN(mma_pmxvi4ger8, "vW512*VVi15i15i255", false,
1078 "mma,paired-vector-memops")
1079UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4, "vW512*VVi15i15i15", false,
1080 "mma,paired-vector-memops")
1081UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2, "vW512*VVi15i15i3", false,
1082 "mma,paired-vector-memops")
1083UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2s, "vW512*VVi15i15i3", false,
1084 "mma,paired-vector-memops")
1085UNALIASED_CUSTOM_BUILTIN(mma_xvi4ger8pp, "vW512*VV", true,
1086 "mma,paired-vector-memops")
1087UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4pp, "vW512*VV", true,
1088 "mma,paired-vector-memops")
1089UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4spp, "vW512*VV", true,
1090 "mma,paired-vector-memops")
1091UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2pp, "vW512*VV", true,
1092 "mma,paired-vector-memops")
1093UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2spp, "vW512*VV", true,
1094 "mma,paired-vector-memops")
1095UNALIASED_CUSTOM_BUILTIN(mma_pmxvi4ger8pp, "vW512*VVi15i15i255", true,
1096 "mma,paired-vector-memops")
1097UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4pp, "vW512*VVi15i15i15", true,
1098 "mma,paired-vector-memops")
1099UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4spp, "vW512*VVi15i15i15", true,
1100 "mma,paired-vector-memops")
1101UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2pp, "vW512*VVi15i15i3", true,
1102 "mma,paired-vector-memops")
1103UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2spp, "vW512*VVi15i15i3", true,
1104 "mma,paired-vector-memops")
1105UNALIASED_CUSTOM_BUILTIN(mma_dmxvi8gerx4, "vW1024*W256V", false,
1106 "mma,paired-vector-memops")
1107UNALIASED_CUSTOM_BUILTIN(mma_pmdmxvi8gerx4, "vW1024*W256Vi255i15i15", false,
1108 "mma,paired-vector-memops")
1109UNALIASED_CUSTOM_BUILTIN(mma_dmxvi8gerx4pp, "vW1024*W256V", true,
1110 "mma,paired-vector-memops")
1111UNALIASED_CUSTOM_BUILTIN(mma_pmdmxvi8gerx4pp, "vW1024*W256Vi255i15i15", true,
1112 "mma,paired-vector-memops")
1113UNALIASED_CUSTOM_BUILTIN(mma_dmxvi8gerx4spp, "vW1024*W256V", true,
1114 "mma,paired-vector-memops")
1115UNALIASED_CUSTOM_BUILTIN(mma_pmdmxvi8gerx4spp, "vW1024*W256Vi255i15i15", true,
1116 "mma,paired-vector-memops")
1117UNALIASED_CUSTOM_BUILTIN(mma_dmsetdmrz, "vW1024*", false,
1118 "mma,isa-future-instructions")
1119UNALIASED_CUSTOM_BUILTIN(mma_dmmr, "vW1024*W1024*", false,
1120 "mma,isa-future-instructions")
1121UNALIASED_CUSTOM_BUILTIN(mma_dmxor, "vW1024*W1024*", true,
1122 "mma,isa-future-instructions")
1123UNALIASED_CUSTOM_BUILTIN(mma_disassemble_dmr, "vv*W1024*", false,
1124 "mma,isa-future-instructions")
1125UNALIASED_CUSTOM_BUILTIN(mma_build_dmr, "vW1024*VVVVVVVV", false,
1126 "mma,isa-future-instructions")
1127
1128UNALIASED_CUSTOM_BUILTIN(mma_dmsha2hash, "vW1024*W1024*Ii", true,
1129 "mma,isa-future-instructions")
1130UNALIASED_CUSTOM_BUILTIN(mma_dmsha3hash, "vW2048*Ii", true,
1131 "mma,isa-future-instructions")
1132UNALIASED_CUSTOM_BUILTIN(mma_dmxxshapad, "vW1024*VIiIiIi", true,
1133 "mma,isa-future-instructions")
1134
1135// MMA builtins with positive/negative multiply/accumulate.
1136UNALIASED_CUSTOM_MMA_BUILTIN(mma_xvf16ger2, "vW512*VV",
1137 "mma,paired-vector-memops")
1138UNALIASED_CUSTOM_MMA_BUILTIN(mma_xvf32ger, "vW512*VV",
1139 "mma,paired-vector-memops")
1140UNALIASED_CUSTOM_MMA_BUILTIN(mma_xvf64ger, "vW512*W256V",
1141 "mma,paired-vector-memops")
1142UNALIASED_CUSTOM_MMA_BUILTIN(mma_pmxvf16ger2, "vW512*VVi15i15i3",
1143 "mma,paired-vector-memops")
1144UNALIASED_CUSTOM_MMA_BUILTIN(mma_pmxvf32ger, "vW512*VVi15i15",
1145 "mma,paired-vector-memops")
1146UNALIASED_CUSTOM_MMA_BUILTIN(mma_pmxvf64ger, "vW512*W256Vi15i3",
1147 "mma,paired-vector-memops")
1148UNALIASED_CUSTOM_MMA_BUILTIN(mma_xvbf16ger2, "vW512*VV",
1149 "mma,paired-vector-memops")
1150UNALIASED_CUSTOM_MMA_BUILTIN(mma_pmxvbf16ger2, "vW512*VVi15i15i3",
1151 "mma,paired-vector-memops")
1152UNALIASED_CUSTOM_MMA_BUILTIN(mma_dmxvbf16gerx2, "vW1024*W256V",
1153 "mma,isa-future-instructions")
1154UNALIASED_CUSTOM_MMA_BUILTIN(mma_pmdmxvbf16gerx2, "vW1024*W256Vi255i15i3",
1155 "mma,isa-future-instructions")
1156UNALIASED_CUSTOM_MMA_BUILTIN(mma_dmxvf16gerx2, "vW1024*W256V",
1157 "mma,isa-future-instructions")
1158UNALIASED_CUSTOM_MMA_BUILTIN(mma_pmdmxvf16gerx2, "vW1024*W256Vi255i15i3",
1159 "mma,isa-future-instructions")
1160
1161// FIXME: Obviously incomplete.
1162
1163#undef BUILTIN
1164#undef TARGET_BUILTIN
1165#undef CUSTOM_BUILTIN
1166#undef UNALIASED_CUSTOM_BUILTIN
1167#undef UNALIASED_CUSTOM_MMA_BUILTIN
1168