1//===--- Mips.cpp - Implement Mips target feature support -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements Mips TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "Mips.h"
14#include "clang/Basic/Diagnostic.h"
15#include "clang/Basic/MacroBuilder.h"
16#include "clang/Basic/TargetBuiltins.h"
17#include "llvm/ADT/StringSwitch.h"
18
19using namespace clang;
20using namespace clang::targets;
21
22static constexpr int NumBuiltins =
23 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
24
25static constexpr llvm::StringTable BuiltinStrings =
26 CLANG_BUILTIN_STR_TABLE_START
27#define BUILTIN CLANG_BUILTIN_STR_TABLE
28#include "clang/Basic/BuiltinsMips.def"
29 ;
30
31static constexpr auto BuiltinInfos = Builtin::MakeInfos<NumBuiltins>(Infos: {
32#define BUILTIN CLANG_BUILTIN_ENTRY
33#define LIBBUILTIN CLANG_LIBBUILTIN_ENTRY
34#include "clang/Basic/BuiltinsMips.def"
35});
36
37bool MipsTargetInfo::processorSupportsGPR64() const {
38 return llvm::StringSwitch<bool>(CPU)
39 .Case(S: "mips3", Value: true)
40 .Case(S: "mips4", Value: true)
41 .Case(S: "mips5", Value: true)
42 .Case(S: "mips64", Value: true)
43 .Case(S: "mips64r2", Value: true)
44 .Case(S: "mips64r3", Value: true)
45 .Case(S: "mips64r5", Value: true)
46 .Case(S: "mips64r6", Value: true)
47 .Case(S: "octeon", Value: true)
48 .Case(S: "octeon+", Value: true)
49 .Case(S: "r5900", Value: true)
50 .Case(S: "i6400", Value: true)
51 .Case(S: "i6500", Value: true)
52 .Default(Value: false);
53}
54
55static constexpr llvm::StringLiteral ValidCPUNames[] = {
56 {"mips1"}, {"mips2"}, {"mips3"}, {"mips4"}, {"mips5"},
57 {"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"},
58 {"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"},
59 {"octeon"}, {"octeon+"}, {"p5600"}, {"r5900"}, {"i6400"},
60 {"i6500"}};
61
62bool MipsTargetInfo::isValidCPUName(StringRef Name) const {
63 return llvm::is_contained(Range: ValidCPUNames, Element: Name);
64}
65
66void MipsTargetInfo::fillValidCPUList(
67 SmallVectorImpl<StringRef> &Values) const {
68 Values.append(in_start: std::begin(arr: ValidCPUNames), in_end: std::end(arr: ValidCPUNames));
69}
70
71unsigned MipsTargetInfo::getISARev() const {
72 return llvm::StringSwitch<unsigned>(getCPU())
73 .Cases(CaseStrings: {"mips32", "mips64"}, Value: 1)
74 .Cases(CaseStrings: {"mips32r2", "mips64r2", "octeon", "octeon+"}, Value: 2)
75 .Cases(CaseStrings: {"mips32r3", "mips64r3"}, Value: 3)
76 .Cases(CaseStrings: {"mips32r5", "mips64r5", "p5600"}, Value: 5)
77 .Cases(CaseStrings: {"mips32r6", "mips64r6", "i6400", "i6500"}, Value: 6)
78 .Default(Value: 0);
79}
80
81void MipsTargetInfo::getTargetDefines(const LangOptions &Opts,
82 MacroBuilder &Builder) const {
83 if (BigEndian) {
84 DefineStd(Builder, MacroName: "MIPSEB", Opts);
85 Builder.defineMacro(Name: "_MIPSEB");
86 } else {
87 DefineStd(Builder, MacroName: "MIPSEL", Opts);
88 Builder.defineMacro(Name: "_MIPSEL");
89 }
90
91 Builder.defineMacro(Name: "__mips__");
92 Builder.defineMacro(Name: "_mips");
93 if (Opts.GNUMode)
94 Builder.defineMacro(Name: "mips");
95
96 if (ABI == "o32") {
97 Builder.defineMacro(Name: "__mips", Value: "32");
98 Builder.defineMacro(Name: "_MIPS_ISA", Value: "_MIPS_ISA_MIPS32");
99 } else {
100 Builder.defineMacro(Name: "__mips", Value: "64");
101 Builder.defineMacro(Name: "__mips64");
102 Builder.defineMacro(Name: "__mips64__");
103 Builder.defineMacro(Name: "_MIPS_ISA", Value: "_MIPS_ISA_MIPS64");
104 }
105
106 const std::string ISARev = std::to_string(val: getISARev());
107
108 if (!ISARev.empty())
109 Builder.defineMacro(Name: "__mips_isa_rev", Value: ISARev);
110
111 if (ABI == "o32") {
112 Builder.defineMacro(Name: "__mips_o32");
113 Builder.defineMacro(Name: "_ABIO32", Value: "1");
114 Builder.defineMacro(Name: "_MIPS_SIM", Value: "_ABIO32");
115 } else if (ABI == "n32") {
116 Builder.defineMacro(Name: "__mips_n32");
117 Builder.defineMacro(Name: "_ABIN32", Value: "2");
118 Builder.defineMacro(Name: "_MIPS_SIM", Value: "_ABIN32");
119 } else if (ABI == "n64") {
120 Builder.defineMacro(Name: "__mips_n64");
121 Builder.defineMacro(Name: "_ABI64", Value: "3");
122 Builder.defineMacro(Name: "_MIPS_SIM", Value: "_ABI64");
123 } else
124 llvm_unreachable("Invalid ABI.");
125
126 if (!IsNoABICalls) {
127 Builder.defineMacro(Name: "__mips_abicalls");
128 if (CanUseBSDABICalls)
129 Builder.defineMacro(Name: "__ABICALLS__");
130 }
131
132 Builder.defineMacro(Name: "__REGISTER_PREFIX__", Value: "");
133
134 switch (FloatABI) {
135 case HardFloat:
136 Builder.defineMacro(Name: "__mips_hard_float", Value: Twine(1));
137 break;
138 case SoftFloat:
139 Builder.defineMacro(Name: "__mips_soft_float", Value: Twine(1));
140 break;
141 }
142
143 if (IsSingleFloat)
144 Builder.defineMacro(Name: "__mips_single_float", Value: Twine(1));
145
146 switch (FPMode) {
147 case FPXX:
148 Builder.defineMacro(Name: "__mips_fpr", Value: Twine(0));
149 break;
150 case FP32:
151 Builder.defineMacro(Name: "__mips_fpr", Value: Twine(32));
152 break;
153 case FP64:
154 Builder.defineMacro(Name: "__mips_fpr", Value: Twine(64));
155 break;
156}
157
158 if (FPMode == FP64 || IsSingleFloat)
159 Builder.defineMacro(Name: "_MIPS_FPSET", Value: Twine(32));
160 else
161 Builder.defineMacro(Name: "_MIPS_FPSET", Value: Twine(16));
162 if (NoOddSpreg)
163 Builder.defineMacro(Name: "_MIPS_SPFPSET", Value: Twine(16));
164 else
165 Builder.defineMacro(Name: "_MIPS_SPFPSET", Value: Twine(32));
166
167 if (IsMips16)
168 Builder.defineMacro(Name: "__mips16", Value: Twine(1));
169
170 if (IsMicromips)
171 Builder.defineMacro(Name: "__mips_micromips", Value: Twine(1));
172
173 if (IsNan2008)
174 Builder.defineMacro(Name: "__mips_nan2008", Value: Twine(1));
175
176 if (IsAbs2008)
177 Builder.defineMacro(Name: "__mips_abs2008", Value: Twine(1));
178
179 switch (DspRev) {
180 default:
181 break;
182 case DSP1:
183 Builder.defineMacro(Name: "__mips_dsp_rev", Value: Twine(1));
184 Builder.defineMacro(Name: "__mips_dsp", Value: Twine(1));
185 break;
186 case DSP2:
187 Builder.defineMacro(Name: "__mips_dsp_rev", Value: Twine(2));
188 Builder.defineMacro(Name: "__mips_dspr2", Value: Twine(1));
189 Builder.defineMacro(Name: "__mips_dsp", Value: Twine(1));
190 break;
191 }
192
193 if (HasMSA)
194 Builder.defineMacro(Name: "__mips_msa", Value: Twine(1));
195
196 if (DisableMadd4)
197 Builder.defineMacro(Name: "__mips_no_madd4", Value: Twine(1));
198
199 Builder.defineMacro(Name: "_MIPS_SZPTR", Value: Twine(getPointerWidth(AddrSpace: LangAS::Default)));
200 Builder.defineMacro(Name: "_MIPS_SZINT", Value: Twine(getIntWidth()));
201 Builder.defineMacro(Name: "_MIPS_SZLONG", Value: Twine(getLongWidth()));
202
203 Builder.defineMacro(Name: "_MIPS_ARCH", Value: "\"" + CPU + "\"");
204 if (CPU == "octeon+")
205 Builder.defineMacro(Name: "_MIPS_ARCH_OCTEONP");
206 else
207 Builder.defineMacro(Name: "_MIPS_ARCH_" + StringRef(CPU).upper());
208
209 if (StringRef(CPU).starts_with(Prefix: "octeon"))
210 Builder.defineMacro(Name: "__OCTEON__");
211
212 if (CPU != "mips1") {
213 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
214 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
215 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
216 }
217
218 // 32-bit MIPS processors don't have the necessary lld/scd instructions
219 // found in 64-bit processors. In the case of O32 on a 64-bit processor,
220 // the instructions exist but using them violates the ABI since they
221 // require 64-bit GPRs and O32 only supports 32-bit GPRs.
222 if (ABI == "n32" || ABI == "n64")
223 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
224}
225
226bool MipsTargetInfo::hasFeature(StringRef Feature) const {
227 return llvm::StringSwitch<bool>(Feature)
228 .Case(S: "mips", Value: true)
229 .Case(S: "dsp", Value: DspRev >= DSP1)
230 .Case(S: "dspr2", Value: DspRev >= DSP2)
231 .Case(S: "fp64", Value: FPMode == FP64)
232 .Case(S: "msa", Value: HasMSA)
233 .Default(Value: false);
234}
235
236llvm::SmallVector<Builtin::InfosShard>
237MipsTargetInfo::getTargetBuiltins() const {
238 return {{.Strings: &BuiltinStrings, .Infos: BuiltinInfos}};
239}
240
241unsigned MipsTargetInfo::getUnwindWordWidth() const {
242 return llvm::StringSwitch<unsigned>(ABI)
243 .Case(S: "o32", Value: 32)
244 .Case(S: "n32", Value: 64)
245 .Case(S: "n64", Value: 64)
246 .Default(Value: getPointerWidth(AddrSpace: LangAS::Default));
247}
248
249bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
250 // microMIPS64R6 backend was removed.
251 if (getTriple().isMIPS64() && IsMicromips && (ABI == "n32" || ABI == "n64")) {
252 Diags.Report(DiagID: diag::err_target_unsupported_cpu_for_micromips) << CPU;
253 return false;
254 }
255
256 // 64-bit ABI's require 64-bit CPU's.
257 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
258 Diags.Report(DiagID: diag::err_target_unsupported_abi) << ABI << CPU;
259 return false;
260 }
261
262 // -fpxx is valid only for the o32 ABI
263 if (FPMode == FPXX && (ABI == "n32" || ABI == "n64")) {
264 Diags.Report(DiagID: diag::err_unsupported_abi_for_opt) << "-mfpxx" << "o32";
265 return false;
266 }
267
268 // -mfp32 and n32/n64 ABIs are incompatible
269 if (FPMode != FP64 && FPMode != FPXX && !IsSingleFloat &&
270 (ABI == "n32" || ABI == "n64")) {
271 Diags.Report(DiagID: diag::err_opt_not_valid_with_opt) << "-mfpxx" << CPU;
272 return false;
273 }
274 // Mips revision 6 and -mfp32 are incompatible
275 if (FPMode != FP64 && FPMode != FPXX &&
276 (CPU == "mips32r6" || CPU == "mips64r6" || CPU == "i6400" ||
277 CPU == "i6500")) {
278 Diags.Report(DiagID: diag::err_opt_not_valid_with_opt) << "-mfp32" << CPU;
279 return false;
280 }
281 // Option -mfp64 permitted on Mips32 iff revision 2 or higher is present
282 if (FPMode == FP64 && (CPU == "mips1" || CPU == "mips2" ||
283 getISARev() < 2) && ABI == "o32") {
284 Diags.Report(DiagID: diag::err_mips_fp64_req) << "-mfp64";
285 return false;
286 }
287 // FPXX requires mips2+
288 if (FPMode == FPXX && CPU == "mips1") {
289 Diags.Report(DiagID: diag::err_opt_not_valid_with_opt) << "-mfpxx" << CPU;
290 return false;
291 }
292 // -mmsa with -msoft-float makes nonsense
293 if (FloatABI == SoftFloat && HasMSA) {
294 Diags.Report(DiagID: diag::err_opt_not_valid_with_opt) << "-msoft-float"
295 << "-mmsa";
296 return false;
297 }
298 // Option -mmsa permitted on Mips32 iff revision 2 or higher is present
299 if (HasMSA && (CPU == "mips1" || CPU == "mips2" || getISARev() < 2) &&
300 ABI == "o32") {
301 Diags.Report(DiagID: diag::err_mips_fp64_req) << "-mmsa";
302 return false;
303 }
304 // MSA requires FP64
305 if (FPMode == FPXX && HasMSA) {
306 Diags.Report(DiagID: diag::err_opt_not_valid_with_opt) << "-mfpxx"
307 << "-mmsa";
308 return false;
309 }
310 if (FPMode == FP32 && HasMSA) {
311 Diags.Report(DiagID: diag::err_opt_not_valid_with_opt) << "-mfp32"
312 << "-mmsa";
313 return false;
314 }
315
316 return true;
317}
318
319WindowsMipsTargetInfo::WindowsMipsTargetInfo(const llvm::Triple &Triple,
320 const TargetOptions &Opts)
321 : WindowsTargetInfo<MipsTargetInfo>(Triple, Opts), Triple(Triple) {}
322
323void WindowsMipsTargetInfo::getVisualStudioDefines(
324 const LangOptions &Opts, MacroBuilder &Builder) const {
325 Builder.defineMacro(Name: "_M_MRX000", Value: "4000");
326}
327
328TargetInfo::BuiltinVaListKind
329WindowsMipsTargetInfo::getBuiltinVaListKind() const {
330 return TargetInfo::CharPtrBuiltinVaList;
331}
332
333TargetInfo::CallingConvCheckResult
334WindowsMipsTargetInfo::checkCallingConvention(CallingConv CC) const {
335 switch (CC) {
336 case CC_X86StdCall:
337 case CC_X86ThisCall:
338 case CC_X86FastCall:
339 case CC_X86VectorCall:
340 return CCCR_Ignore;
341 case CC_C:
342 case CC_DeviceKernel:
343 case CC_PreserveMost:
344 case CC_PreserveAll:
345 case CC_Swift:
346 case CC_SwiftAsync:
347 return CCCR_OK;
348 default:
349 return CCCR_Warning;
350 }
351}
352
353// Windows MIPS, MS (C++) ABI
354MicrosoftMipsTargetInfo::MicrosoftMipsTargetInfo(const llvm::Triple &Triple,
355 const TargetOptions &Opts)
356 : WindowsMipsTargetInfo(Triple, Opts) {
357 TheCXXABI.set(TargetCXXABI::Microsoft);
358}
359
360void MicrosoftMipsTargetInfo::getTargetDefines(const LangOptions &Opts,
361 MacroBuilder &Builder) const {
362 WindowsMipsTargetInfo::getTargetDefines(Opts, Builder);
363 WindowsMipsTargetInfo::getVisualStudioDefines(Opts, Builder);
364}
365
366MinGWMipsTargetInfo::MinGWMipsTargetInfo(const llvm::Triple &Triple,
367 const TargetOptions &Opts)
368 : WindowsMipsTargetInfo(Triple, Opts) {
369 TheCXXABI.set(TargetCXXABI::GenericMIPS);
370}
371
372void MinGWMipsTargetInfo::getTargetDefines(const LangOptions &Opts,
373 MacroBuilder &Builder) const {
374 WindowsMipsTargetInfo::getTargetDefines(Opts, Builder);
375 Builder.defineMacro(Name: "_MIPS_");
376}
377