1//===--- NVPTX.cpp - Implement NVPTX target feature support ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements NVPTX TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "NVPTX.h"
14#include "clang/Basic/Builtins.h"
15#include "clang/Basic/MacroBuilder.h"
16#include "clang/Basic/TargetBuiltins.h"
17#include "llvm/ADT/StringSwitch.h"
18
19using namespace clang;
20using namespace clang::targets;
21
22static constexpr int NumBuiltins =
23 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin;
24
25#define GET_BUILTIN_STR_TABLE
26#include "clang/Basic/BuiltinsNVPTX.inc"
27#undef GET_BUILTIN_STR_TABLE
28
29static constexpr Builtin::Info BuiltinInfos[] = {
30#define GET_BUILTIN_INFOS
31#include "clang/Basic/BuiltinsNVPTX.inc"
32#undef GET_BUILTIN_INFOS
33};
34static_assert(std::size(BuiltinInfos) == NumBuiltins);
35
36const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
37
38NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple,
39 const TargetOptions &Opts,
40 unsigned TargetPointerWidth)
41 : TargetInfo(Triple) {
42 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) &&
43 "NVPTX only supports 32- and 64-bit modes.");
44
45 // PTXVersion is 0 by default, meaning "use the minimum for the SM target".
46 // Only set it if the user explicitly requested a PTX version.
47 PTXVersion = 0;
48 for (const StringRef Feature : Opts.FeaturesAsWritten) {
49 int PTXV;
50 if (!Feature.starts_with(Prefix: "+ptx") ||
51 Feature.drop_front(N: 4).getAsInteger(Radix: 10, Result&: PTXV))
52 continue;
53 PTXVersion = PTXV; // TODO: should it be max(PTXVersion, PTXV)?
54 }
55
56 TLSSupported = false;
57 VLASupported = false;
58 AddrSpaceMap = &NVPTXAddrSpaceMap;
59 UseAddrSpaceMapMangling = true;
60 // __bf16 is always available as a load/store only type.
61 BFloat16Width = BFloat16Align = 16;
62 BFloat16Format = &llvm::APFloat::BFloat();
63
64 // Define available target features
65 // These must be defined in sorted order!
66 NoAsmVariants = true;
67 GPU = OffloadArch::UNUSED;
68
69 // PTX supports f16 as a fundamental type.
70 HasFastHalfType = true;
71 HasFloat16 = true;
72
73 // TODO: Make shortptr a proper ABI?
74 DataLayoutString =
75 Triple.computeDataLayout(ABIName: Opts.NVPTXUseShortPointers ? "shortptr" : "");
76
77 // If possible, get a TargetInfo for our host triple, so we can match its
78 // types.
79 llvm::Triple HostTriple(Opts.HostTriple);
80 if (!HostTriple.isNVPTX())
81 HostTarget = AllocateTarget(Triple: llvm::Triple(Opts.HostTriple), Opts);
82
83 // If no host target, make some guesses about the data layout and return.
84 if (!HostTarget) {
85 LongWidth = LongAlign = TargetPointerWidth;
86 PointerWidth = PointerAlign = TargetPointerWidth;
87 switch (TargetPointerWidth) {
88 case 32:
89 SizeType = TargetInfo::UnsignedInt;
90 PtrDiffType = TargetInfo::SignedInt;
91 IntPtrType = TargetInfo::SignedInt;
92 break;
93 case 64:
94 SizeType = TargetInfo::UnsignedLong;
95 PtrDiffType = TargetInfo::SignedLong;
96 IntPtrType = TargetInfo::SignedLong;
97 break;
98 default:
99 llvm_unreachable("TargetPointerWidth must be 32 or 64");
100 }
101
102 MaxAtomicInlineWidth = TargetPointerWidth;
103 return;
104 }
105
106 // Copy properties from host target.
107 PointerWidth = HostTarget->getPointerWidth(AddrSpace: LangAS::Default);
108 PointerAlign = HostTarget->getPointerAlign(AddrSpace: LangAS::Default);
109 BoolWidth = HostTarget->getBoolWidth();
110 BoolAlign = HostTarget->getBoolAlign();
111 IntWidth = HostTarget->getIntWidth();
112 IntAlign = HostTarget->getIntAlign();
113 HalfWidth = HostTarget->getHalfWidth();
114 HalfAlign = HostTarget->getHalfAlign();
115 FloatWidth = HostTarget->getFloatWidth();
116 FloatAlign = HostTarget->getFloatAlign();
117 DoubleWidth = HostTarget->getDoubleWidth();
118 DoubleAlign = HostTarget->getDoubleAlign();
119 LongWidth = HostTarget->getLongWidth();
120 LongAlign = HostTarget->getLongAlign();
121 LongLongWidth = HostTarget->getLongLongWidth();
122 LongLongAlign = HostTarget->getLongLongAlign();
123 MinGlobalAlign = HostTarget->getMinGlobalAlign(/* TypeSize = */ Size: 0,
124 /* HasNonWeakDef = */ true);
125 NewAlign = HostTarget->getNewAlign();
126 DefaultAlignForAttributeAligned =
127 HostTarget->getDefaultAlignForAttributeAligned();
128 SizeType = HostTarget->getSizeType();
129 IntMaxType = HostTarget->getIntMaxType();
130 PtrDiffType = HostTarget->getPtrDiffType(AddrSpace: LangAS::Default);
131 IntPtrType = HostTarget->getIntPtrType();
132 WCharType = HostTarget->getWCharType();
133 WIntType = HostTarget->getWIntType();
134 Char16Type = HostTarget->getChar16Type();
135 Char32Type = HostTarget->getChar32Type();
136 Int64Type = HostTarget->getInt64Type();
137 SigAtomicType = HostTarget->getSigAtomicType();
138 ProcessIDType = HostTarget->getProcessIDType();
139
140 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment();
141 UseZeroLengthBitfieldAlignment = HostTarget->useZeroLengthBitfieldAlignment();
142 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
143 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
144
145 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
146 // we need those macros to be identical on host and device, because (among
147 // other things) they affect which standard library classes are defined, and
148 // we need all classes to be defined on both the host and device.
149 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
150
151 // Properties intentionally not copied from host:
152 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
153 // host/device boundary.
154 // - SuitableAlign: Not visible across the host/device boundary, and may
155 // correctly be different on host/device, e.g. if host has wider vector
156 // types than device.
157 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
158 // as its double type, but that's not necessarily true on the host.
159 // TODO: nvcc emits a warning when using long double on device; we should
160 // do the same.
161}
162
163ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
164 return llvm::ArrayRef(GCCRegNames);
165}
166
167bool NVPTXTargetInfo::hasFeature(StringRef Feature) const {
168 return llvm::StringSwitch<bool>(Feature)
169 .Cases(CaseStrings: {"ptx", "nvptx"}, Value: true)
170 .Default(Value: false);
171}
172
173void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts,
174 MacroBuilder &Builder) const {
175 Builder.defineMacro(Name: "__PTX__");
176 Builder.defineMacro(Name: "__NVPTX__");
177
178 // Skip setting architecture dependent macros if undefined.
179 if (!IsNVIDIAOffloadArch(A: GPU))
180 return;
181
182 if (Opts.CUDAIsDevice || Opts.OpenMPIsTargetDevice || !HostTarget) {
183 // Set __CUDA_ARCH__ for the GPU specified.
184 unsigned ArchID = CudaArchToID(Arch: GPU);
185 Builder.defineMacro(Name: "__CUDA_ARCH__", Value: llvm::Twine(ArchID));
186
187 if (IsNVIDIAAcceleratedOffloadArch(Arch: GPU))
188 Builder.defineMacro(
189 Name: "__CUDA_ARCH_FEAT_SM" + llvm::Twine(ArchID / 10) + "_ALL", Value: "1");
190 }
191}
192
193llvm::SmallVector<Builtin::InfosShard>
194NVPTXTargetInfo::getTargetBuiltins() const {
195 return {{.Strings: &BuiltinStrings, .Infos: BuiltinInfos}};
196}
197