1//===--- X86.cpp - Implement X86 target feature support -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements X86 TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86.h"
14#include "clang/Basic/Builtins.h"
15#include "clang/Basic/Diagnostic.h"
16#include "clang/Basic/TargetBuiltins.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/TargetParser/X86TargetParser.h"
20#include <optional>
21
22namespace clang {
23namespace targets {
24
25// The x86-32 builtins are a subset and prefix of the x86-64 builtins.
26static constexpr int NumX86Builtins =
27 X86::LastX86CommonBuiltin - Builtin::FirstTSBuiltin + 1;
28static constexpr int NumX86_64Builtins =
29 X86::LastTSBuiltin - X86::FirstX86_64Builtin;
30static constexpr int NumBuiltins = X86::LastTSBuiltin - Builtin::FirstTSBuiltin;
31static_assert(NumBuiltins == (NumX86Builtins + NumX86_64Builtins));
32
33namespace X86 {
34#define GET_BUILTIN_STR_TABLE
35#include "clang/Basic/BuiltinsX86.inc"
36#undef GET_BUILTIN_STR_TABLE
37
38static constexpr Builtin::Info BuiltinInfos[] = {
39#define GET_BUILTIN_INFOS
40#include "clang/Basic/BuiltinsX86.inc"
41#undef GET_BUILTIN_INFOS
42};
43
44static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
45#define GET_BUILTIN_PREFIXED_INFOS
46#include "clang/Basic/BuiltinsX86.inc"
47#undef GET_BUILTIN_PREFIXED_INFOS
48};
49static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
50 NumX86Builtins);
51} // namespace X86
52
53namespace X86_64 {
54#define GET_BUILTIN_STR_TABLE
55#include "clang/Basic/BuiltinsX86_64.inc"
56#undef GET_BUILTIN_STR_TABLE
57
58static constexpr Builtin::Info BuiltinInfos[] = {
59#define GET_BUILTIN_INFOS
60#include "clang/Basic/BuiltinsX86_64.inc"
61#undef GET_BUILTIN_INFOS
62};
63
64static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
65#define GET_BUILTIN_PREFIXED_INFOS
66#include "clang/Basic/BuiltinsX86_64.inc"
67#undef GET_BUILTIN_PREFIXED_INFOS
68};
69static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
70 NumX86_64Builtins);
71} // namespace X86_64
72
73static const char *const GCCRegNames[] = {
74 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
75 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
76 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
77 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
78 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
79 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
80 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
81 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
82 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
83 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
84 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
85 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
86 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
87 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
88 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
89 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
90 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
91 "k2", "k3", "k4", "k5", "k6", "k7",
92 "cr0", "cr2", "cr3", "cr4", "cr8",
93 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
94 "bnd0", "bnd1", "bnd2", "bnd3",
95 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
96 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
97 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
98};
99
100const TargetInfo::AddlRegName AddlRegNames[] = {
101 {.Names: {"al", "ah", "eax", "rax"}, .RegNum: 0},
102 {.Names: {"bl", "bh", "ebx", "rbx"}, .RegNum: 3},
103 {.Names: {"cl", "ch", "ecx", "rcx"}, .RegNum: 2},
104 {.Names: {"dl", "dh", "edx", "rdx"}, .RegNum: 1},
105 {.Names: {"esi", "rsi"}, .RegNum: 4},
106 {.Names: {"edi", "rdi"}, .RegNum: 5},
107 {.Names: {"esp", "rsp"}, .RegNum: 7},
108 {.Names: {"ebp", "rbp"}, .RegNum: 6},
109 {.Names: {"r8d", "r8w", "r8b"}, .RegNum: 38},
110 {.Names: {"r9d", "r9w", "r9b"}, .RegNum: 39},
111 {.Names: {"r10d", "r10w", "r10b"}, .RegNum: 40},
112 {.Names: {"r11d", "r11w", "r11b"}, .RegNum: 41},
113 {.Names: {"r12d", "r12w", "r12b"}, .RegNum: 42},
114 {.Names: {"r13d", "r13w", "r13b"}, .RegNum: 43},
115 {.Names: {"r14d", "r14w", "r14b"}, .RegNum: 44},
116 {.Names: {"r15d", "r15w", "r15b"}, .RegNum: 45},
117 {.Names: {"r16d", "r16w", "r16b"}, .RegNum: 165},
118 {.Names: {"r17d", "r17w", "r17b"}, .RegNum: 166},
119 {.Names: {"r18d", "r18w", "r18b"}, .RegNum: 167},
120 {.Names: {"r19d", "r19w", "r19b"}, .RegNum: 168},
121 {.Names: {"r20d", "r20w", "r20b"}, .RegNum: 169},
122 {.Names: {"r21d", "r21w", "r21b"}, .RegNum: 170},
123 {.Names: {"r22d", "r22w", "r22b"}, .RegNum: 171},
124 {.Names: {"r23d", "r23w", "r23b"}, .RegNum: 172},
125 {.Names: {"r24d", "r24w", "r24b"}, .RegNum: 173},
126 {.Names: {"r25d", "r25w", "r25b"}, .RegNum: 174},
127 {.Names: {"r26d", "r26w", "r26b"}, .RegNum: 175},
128 {.Names: {"r27d", "r27w", "r27b"}, .RegNum: 176},
129 {.Names: {"r28d", "r28w", "r28b"}, .RegNum: 177},
130 {.Names: {"r29d", "r29w", "r29b"}, .RegNum: 178},
131 {.Names: {"r30d", "r30w", "r30b"}, .RegNum: 179},
132 {.Names: {"r31d", "r31w", "r31b"}, .RegNum: 180},
133};
134} // namespace targets
135} // namespace clang
136
137using namespace clang;
138using namespace clang::targets;
139
140bool X86TargetInfo::setFPMath(StringRef Name) {
141 if (Name == "387") {
142 FPMath = FP_387;
143 return true;
144 }
145 if (Name == "sse") {
146 FPMath = FP_SSE;
147 return true;
148 }
149 return false;
150}
151
152bool X86TargetInfo::initFeatureMap(
153 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
154 const std::vector<std::string> &FeaturesVec) const {
155 // FIXME: This *really* should not be here.
156 // X86_64 always has SSE2.
157 if (getTriple().getArch() == llvm::Triple::x86_64)
158 setFeatureEnabled(Features, Name: "sse2", Enabled: true);
159
160 using namespace llvm::X86;
161
162 SmallVector<StringRef, 16> CPUFeatures;
163 getFeaturesForCPU(CPU, Features&: CPUFeatures);
164 for (auto &F : CPUFeatures)
165 setFeatureEnabled(Features, Name: F, Enabled: true);
166
167 std::vector<std::string> UpdatedFeaturesVec;
168 for (const auto &Feature : FeaturesVec) {
169 // Expand general-regs-only to -x86, -mmx and -sse
170 if (Feature == "+general-regs-only") {
171 UpdatedFeaturesVec.push_back(x: "-x87");
172 UpdatedFeaturesVec.push_back(x: "-mmx");
173 UpdatedFeaturesVec.push_back(x: "-sse");
174 continue;
175 }
176
177 UpdatedFeaturesVec.push_back(x: Feature);
178 }
179
180 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec: UpdatedFeaturesVec))
181 return false;
182
183 // Can't do this earlier because we need to be able to explicitly enable
184 // or disable these features and the things that they depend upon.
185
186 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
187 auto I = Features.find(Key: "sse4.2");
188 if (I != Features.end() && I->getValue() &&
189 !llvm::is_contained(Range&: UpdatedFeaturesVec, Element: "-popcnt"))
190 Features["popcnt"] = true;
191
192 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
193 // then enable MMX.
194 I = Features.find(Key: "sse");
195 if (I != Features.end() && I->getValue() &&
196 !llvm::is_contained(Range&: UpdatedFeaturesVec, Element: "-mmx"))
197 Features["mmx"] = true;
198
199 // Enable xsave if avx is enabled and xsave is not explicitly disabled.
200 I = Features.find(Key: "avx");
201 if (I != Features.end() && I->getValue() &&
202 !llvm::is_contained(Range&: UpdatedFeaturesVec, Element: "-xsave"))
203 Features["xsave"] = true;
204
205 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
206 I = Features.find(Key: "sse4.2");
207 if (I != Features.end() && I->getValue() &&
208 !llvm::is_contained(Range&: UpdatedFeaturesVec, Element: "-crc32"))
209 Features["crc32"] = true;
210
211 return true;
212}
213
214void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
215 StringRef Name, bool Enabled) const {
216 if (Name == "sse4") {
217 // We can get here via the __target__ attribute since that's not controlled
218 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
219 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
220 // disabled.
221 if (Enabled)
222 Name = "sse4.2";
223 else
224 Name = "sse4.1";
225 }
226
227 Features[Name] = Enabled;
228 llvm::X86::updateImpliedFeatures(Feature: Name, Enabled, Features);
229}
230
231/// handleTargetFeatures - Perform initialization based on the user
232/// configured set of features.
233bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
234 DiagnosticsEngine &Diags) {
235 for (const auto &Feature : Features) {
236 if (Feature[0] != '+')
237 continue;
238
239 if (Feature == "+mmx") {
240 HasMMX = true;
241 } else if (Feature == "+aes") {
242 HasAES = true;
243 } else if (Feature == "+vaes") {
244 HasVAES = true;
245 } else if (Feature == "+pclmul") {
246 HasPCLMUL = true;
247 } else if (Feature == "+vpclmulqdq") {
248 HasVPCLMULQDQ = true;
249 } else if (Feature == "+lzcnt") {
250 HasLZCNT = true;
251 } else if (Feature == "+rdrnd") {
252 HasRDRND = true;
253 } else if (Feature == "+fsgsbase") {
254 HasFSGSBASE = true;
255 } else if (Feature == "+bmi") {
256 HasBMI = true;
257 } else if (Feature == "+bmi2") {
258 HasBMI2 = true;
259 } else if (Feature == "+popcnt") {
260 HasPOPCNT = true;
261 } else if (Feature == "+rtm") {
262 HasRTM = true;
263 } else if (Feature == "+prfchw") {
264 HasPRFCHW = true;
265 } else if (Feature == "+rdseed") {
266 HasRDSEED = true;
267 } else if (Feature == "+adx") {
268 HasADX = true;
269 } else if (Feature == "+tbm") {
270 HasTBM = true;
271 } else if (Feature == "+lwp") {
272 HasLWP = true;
273 } else if (Feature == "+fma") {
274 HasFMA = true;
275 } else if (Feature == "+f16c") {
276 HasF16C = true;
277 } else if (Feature == "+gfni") {
278 HasGFNI = true;
279 } else if (Feature == "+avx10.1") {
280 HasAVX10_1 = true;
281 } else if (Feature == "+avx10.2") {
282 HasAVX10_2 = true;
283 HasFullBFloat16 = true;
284 } else if (Feature == "+avx512cd") {
285 HasAVX512CD = true;
286 } else if (Feature == "+avx512vpopcntdq") {
287 HasAVX512VPOPCNTDQ = true;
288 } else if (Feature == "+avx512vnni") {
289 HasAVX512VNNI = true;
290 } else if (Feature == "+avx512bf16") {
291 HasAVX512BF16 = true;
292 } else if (Feature == "+avx512fp16") {
293 HasAVX512FP16 = true;
294 HasFastHalfType = true;
295 } else if (Feature == "+avx512dq") {
296 HasAVX512DQ = true;
297 } else if (Feature == "+avx512bitalg") {
298 HasAVX512BITALG = true;
299 } else if (Feature == "+avx512bw") {
300 HasAVX512BW = true;
301 } else if (Feature == "+avx512vl") {
302 HasAVX512VL = true;
303 } else if (Feature == "+avx512vbmi") {
304 HasAVX512VBMI = true;
305 } else if (Feature == "+avx512vbmi2") {
306 HasAVX512VBMI2 = true;
307 } else if (Feature == "+avx512ifma") {
308 HasAVX512IFMA = true;
309 } else if (Feature == "+avx512vp2intersect") {
310 HasAVX512VP2INTERSECT = true;
311 } else if (Feature == "+sha") {
312 HasSHA = true;
313 } else if (Feature == "+sha512") {
314 HasSHA512 = true;
315 } else if (Feature == "+shstk") {
316 HasSHSTK = true;
317 } else if (Feature == "+sm3") {
318 HasSM3 = true;
319 } else if (Feature == "+sm4") {
320 HasSM4 = true;
321 } else if (Feature == "+movbe") {
322 HasMOVBE = true;
323 } else if (Feature == "+movrs") {
324 HasMOVRS = true;
325 } else if (Feature == "+sgx") {
326 HasSGX = true;
327 } else if (Feature == "+cx8") {
328 HasCX8 = true;
329 } else if (Feature == "+cx16") {
330 HasCX16 = true;
331 } else if (Feature == "+fxsr") {
332 HasFXSR = true;
333 } else if (Feature == "+xsave") {
334 HasXSAVE = true;
335 } else if (Feature == "+xsaveopt") {
336 HasXSAVEOPT = true;
337 } else if (Feature == "+xsavec") {
338 HasXSAVEC = true;
339 } else if (Feature == "+xsaves") {
340 HasXSAVES = true;
341 } else if (Feature == "+mwaitx") {
342 HasMWAITX = true;
343 } else if (Feature == "+pku") {
344 HasPKU = true;
345 } else if (Feature == "+clflushopt") {
346 HasCLFLUSHOPT = true;
347 } else if (Feature == "+clwb") {
348 HasCLWB = true;
349 } else if (Feature == "+wbnoinvd") {
350 HasWBNOINVD = true;
351 } else if (Feature == "+prefetchi") {
352 HasPREFETCHI = true;
353 } else if (Feature == "+clzero") {
354 HasCLZERO = true;
355 } else if (Feature == "+cldemote") {
356 HasCLDEMOTE = true;
357 } else if (Feature == "+rdpid") {
358 HasRDPID = true;
359 } else if (Feature == "+rdpru") {
360 HasRDPRU = true;
361 } else if (Feature == "+kl") {
362 HasKL = true;
363 } else if (Feature == "+widekl") {
364 HasWIDEKL = true;
365 } else if (Feature == "+retpoline-external-thunk") {
366 HasRetpolineExternalThunk = true;
367 } else if (Feature == "+sahf") {
368 HasLAHFSAHF = true;
369 } else if (Feature == "+waitpkg") {
370 HasWAITPKG = true;
371 } else if (Feature == "+movdiri") {
372 HasMOVDIRI = true;
373 } else if (Feature == "+movdir64b") {
374 HasMOVDIR64B = true;
375 } else if (Feature == "+pconfig") {
376 HasPCONFIG = true;
377 } else if (Feature == "+ptwrite") {
378 HasPTWRITE = true;
379 } else if (Feature == "+invpcid") {
380 HasINVPCID = true;
381 } else if (Feature == "+enqcmd") {
382 HasENQCMD = true;
383 } else if (Feature == "+hreset") {
384 HasHRESET = true;
385 } else if (Feature == "+amx-bf16") {
386 HasAMXBF16 = true;
387 } else if (Feature == "+amx-fp16") {
388 HasAMXFP16 = true;
389 } else if (Feature == "+amx-int8") {
390 HasAMXINT8 = true;
391 } else if (Feature == "+amx-tile") {
392 HasAMXTILE = true;
393 } else if (Feature == "+amx-complex") {
394 HasAMXCOMPLEX = true;
395 } else if (Feature == "+amx-fp8") {
396 HasAMXFP8 = true;
397 } else if (Feature == "+amx-movrs") {
398 HasAMXMOVRS = true;
399 } else if (Feature == "+amx-avx512") {
400 HasAMXAVX512 = true;
401 } else if (Feature == "+amx-tf32") {
402 HasAMXTF32 = true;
403 } else if (Feature == "+cmpccxadd") {
404 HasCMPCCXADD = true;
405 } else if (Feature == "+raoint") {
406 HasRAOINT = true;
407 } else if (Feature == "+avxifma") {
408 HasAVXIFMA = true;
409 } else if (Feature == "+avxneconvert") {
410 HasAVXNECONVERT= true;
411 } else if (Feature == "+avxvnni") {
412 HasAVXVNNI = true;
413 } else if (Feature == "+avxvnniint16") {
414 HasAVXVNNIINT16 = true;
415 } else if (Feature == "+avxvnniint8") {
416 HasAVXVNNIINT8 = true;
417 } else if (Feature == "+serialize") {
418 HasSERIALIZE = true;
419 } else if (Feature == "+tsxldtrk") {
420 HasTSXLDTRK = true;
421 } else if (Feature == "+uintr") {
422 HasUINTR = true;
423 } else if (Feature == "+usermsr") {
424 HasUSERMSR = true;
425 } else if (Feature == "+crc32") {
426 HasCRC32 = true;
427 } else if (Feature == "+x87") {
428 HasX87 = true;
429 } else if (Feature == "+fullbf16") {
430 HasFullBFloat16 = true;
431 } else if (Feature == "+egpr") {
432 HasEGPR = true;
433 } else if (Feature == "+inline-asm-use-gpr32") {
434 HasInlineAsmUseGPR32 = true;
435 } else if (Feature == "+push2pop2") {
436 HasPush2Pop2 = true;
437 } else if (Feature == "+ppx") {
438 HasPPX = true;
439 } else if (Feature == "+ndd") {
440 HasNDD = true;
441 } else if (Feature == "+ccmp") {
442 HasCCMP = true;
443 } else if (Feature == "+nf") {
444 HasNF = true;
445 } else if (Feature == "+cf") {
446 HasCF = true;
447 } else if (Feature == "+zu") {
448 HasZU = true;
449 } else if (Feature == "+jmpabs") {
450 HasJMPABS = true;
451 } else if (Feature == "+branch-hint") {
452 HasBranchHint = true;
453 }
454
455 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
456 .Case(S: "+avx512f", Value: AVX512F)
457 .Case(S: "+avx2", Value: AVX2)
458 .Case(S: "+avx", Value: AVX)
459 .Case(S: "+sse4.2", Value: SSE42)
460 .Case(S: "+sse4.1", Value: SSE41)
461 .Case(S: "+ssse3", Value: SSSE3)
462 .Case(S: "+sse3", Value: SSE3)
463 .Case(S: "+sse2", Value: SSE2)
464 .Case(S: "+sse", Value: SSE1)
465 .Default(Value: NoSSE);
466 SSELevel = std::max(a: SSELevel, b: Level);
467
468 HasFloat16 = SSELevel >= SSE2;
469
470 // X86 target has bfloat16 emulation support in the backend, where
471 // bfloat16 is treated as a 32-bit float, arithmetic operations are
472 // performed in 32-bit, and the result is converted back to bfloat16.
473 // Truncation and extension between bfloat16 and 32-bit float are supported
474 // by the compiler-rt library. However, native bfloat16 support is currently
475 // not available in the X86 target. Hence, HasFullBFloat16 will be false
476 // until native bfloat16 support is available. HasFullBFloat16 is used to
477 // determine whether to automatically use excess floating point precision
478 // for bfloat16 arithmetic operations in the front-end.
479 HasBFloat16 = SSELevel >= SSE2;
480
481 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
482 .Case(S: "+xop", Value: XOP)
483 .Case(S: "+fma4", Value: FMA4)
484 .Case(S: "+sse4a", Value: SSE4A)
485 .Default(Value: NoXOP);
486 XOPLevel = std::max(a: XOPLevel, b: XLevel);
487 }
488
489 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
490 // matches the selected sse level.
491 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
492 (FPMath == FP_387 && SSELevel >= SSE1)) {
493 Diags.Report(DiagID: diag::err_target_unsupported_fpmath)
494 << (FPMath == FP_SSE ? "sse" : "387");
495 return false;
496 }
497
498 // FIXME: We should allow long double type on 32-bits to match with GCC.
499 // This requires backend to be able to lower f80 without x87 first.
500 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
501 HasLongDouble = false;
502
503 return true;
504}
505
506/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
507/// definitions for this particular subtarget.
508void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
509 MacroBuilder &Builder) const {
510 // Inline assembly supports X86 flag outputs.
511 Builder.defineMacro(Name: "__GCC_ASM_FLAG_OUTPUTS__");
512
513 std::string CodeModel = getTargetOpts().CodeModel;
514 if (CodeModel == "default")
515 CodeModel = "small";
516 Builder.defineMacro(Name: "__code_model_" + CodeModel + "__");
517
518 // Target identification.
519 if (getTriple().getArch() == llvm::Triple::x86_64) {
520 Builder.defineMacro(Name: "__amd64__");
521 Builder.defineMacro(Name: "__amd64");
522 Builder.defineMacro(Name: "__x86_64");
523 Builder.defineMacro(Name: "__x86_64__");
524 if (getTriple().getArchName() == "x86_64h") {
525 Builder.defineMacro(Name: "__x86_64h");
526 Builder.defineMacro(Name: "__x86_64h__");
527 }
528 } else {
529 DefineStd(Builder, MacroName: "i386", Opts);
530 }
531
532 Builder.defineMacro(Name: "__SEG_GS");
533 Builder.defineMacro(Name: "__SEG_FS");
534 Builder.defineMacro(Name: "__seg_gs", Value: "__attribute__((address_space(256)))");
535 Builder.defineMacro(Name: "__seg_fs", Value: "__attribute__((address_space(257)))");
536
537 // Subtarget options.
538 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
539 // truly should be based on -mtune options.
540 using namespace llvm::X86;
541 switch (CPU) {
542 case CK_None:
543 break;
544 case CK_i386:
545 // The rest are coming from the i386 define above.
546 Builder.defineMacro(Name: "__tune_i386__");
547 break;
548 case CK_i486:
549 case CK_WinChipC6:
550 case CK_WinChip2:
551 case CK_C3:
552 defineCPUMacros(Builder, CPUName: "i486");
553 break;
554 case CK_PentiumMMX:
555 Builder.defineMacro(Name: "__pentium_mmx__");
556 Builder.defineMacro(Name: "__tune_pentium_mmx__");
557 [[fallthrough]];
558 case CK_i586:
559 case CK_Pentium:
560 defineCPUMacros(Builder, CPUName: "i586");
561 defineCPUMacros(Builder, CPUName: "pentium");
562 break;
563 case CK_Pentium3:
564 case CK_PentiumM:
565 Builder.defineMacro(Name: "__tune_pentium3__");
566 [[fallthrough]];
567 case CK_Pentium2:
568 case CK_C3_2:
569 Builder.defineMacro(Name: "__tune_pentium2__");
570 [[fallthrough]];
571 case CK_PentiumPro:
572 case CK_i686:
573 defineCPUMacros(Builder, CPUName: "i686");
574 defineCPUMacros(Builder, CPUName: "pentiumpro");
575 break;
576 case CK_Pentium4:
577 defineCPUMacros(Builder, CPUName: "pentium4");
578 break;
579 case CK_Yonah:
580 case CK_Prescott:
581 case CK_Nocona:
582 defineCPUMacros(Builder, CPUName: "nocona");
583 break;
584 case CK_Core2:
585 case CK_Penryn:
586 defineCPUMacros(Builder, CPUName: "core2");
587 break;
588 case CK_Bonnell:
589 defineCPUMacros(Builder, CPUName: "atom");
590 break;
591 case CK_Silvermont:
592 defineCPUMacros(Builder, CPUName: "slm");
593 break;
594 case CK_Goldmont:
595 defineCPUMacros(Builder, CPUName: "goldmont");
596 break;
597 case CK_GoldmontPlus:
598 defineCPUMacros(Builder, CPUName: "goldmont_plus");
599 break;
600 case CK_Tremont:
601 defineCPUMacros(Builder, CPUName: "tremont");
602 break;
603 // Gracemont and later atom-cores use P-core cpu macros.
604 case CK_Gracemont:
605 case CK_Nehalem:
606 case CK_Westmere:
607 case CK_SandyBridge:
608 case CK_IvyBridge:
609 case CK_Haswell:
610 case CK_Broadwell:
611 case CK_SkylakeClient:
612 case CK_SkylakeServer:
613 case CK_Cascadelake:
614 case CK_Cooperlake:
615 case CK_Cannonlake:
616 case CK_IcelakeClient:
617 case CK_Rocketlake:
618 case CK_IcelakeServer:
619 case CK_Tigerlake:
620 case CK_SapphireRapids:
621 case CK_Alderlake:
622 case CK_Raptorlake:
623 case CK_Meteorlake:
624 case CK_Arrowlake:
625 case CK_ArrowlakeS:
626 case CK_Lunarlake:
627 case CK_Pantherlake:
628 case CK_Wildcatlake:
629 case CK_Novalake:
630 case CK_Sierraforest:
631 case CK_Grandridge:
632 case CK_Graniterapids:
633 case CK_GraniterapidsD:
634 case CK_Emeraldrapids:
635 case CK_Clearwaterforest:
636 case CK_Diamondrapids:
637 // FIXME: Historically, we defined this legacy name, it would be nice to
638 // remove it at some point. We've never exposed fine-grained names for
639 // recent primary x86 CPUs, and we should keep it that way.
640 defineCPUMacros(Builder, CPUName: "corei7");
641 break;
642 case CK_KNL:
643 defineCPUMacros(Builder, CPUName: "knl");
644 break;
645 case CK_KNM:
646 break;
647 case CK_Lakemont:
648 defineCPUMacros(Builder, CPUName: "i586", /*Tuning*/false);
649 defineCPUMacros(Builder, CPUName: "pentium", /*Tuning*/false);
650 Builder.defineMacro(Name: "__tune_lakemont__");
651 break;
652 case CK_K6_2:
653 Builder.defineMacro(Name: "__k6_2__");
654 Builder.defineMacro(Name: "__tune_k6_2__");
655 [[fallthrough]];
656 case CK_K6_3:
657 if (CPU != CK_K6_2) { // In case of fallthrough
658 // FIXME: GCC may be enabling these in cases where some other k6
659 // architecture is specified but -m3dnow is explicitly provided. The
660 // exact semantics need to be determined and emulated here.
661 Builder.defineMacro(Name: "__k6_3__");
662 Builder.defineMacro(Name: "__tune_k6_3__");
663 }
664 [[fallthrough]];
665 case CK_K6:
666 defineCPUMacros(Builder, CPUName: "k6");
667 break;
668 case CK_Athlon:
669 case CK_AthlonXP:
670 defineCPUMacros(Builder, CPUName: "athlon");
671 if (SSELevel != NoSSE) {
672 Builder.defineMacro(Name: "__athlon_sse__");
673 Builder.defineMacro(Name: "__tune_athlon_sse__");
674 }
675 break;
676 case CK_K8:
677 case CK_K8SSE3:
678 case CK_x86_64:
679 defineCPUMacros(Builder, CPUName: "k8");
680 break;
681 case CK_x86_64_v2:
682 case CK_x86_64_v3:
683 case CK_x86_64_v4:
684 break;
685 case CK_AMDFAM10:
686 defineCPUMacros(Builder, CPUName: "amdfam10");
687 break;
688 case CK_BTVER1:
689 defineCPUMacros(Builder, CPUName: "btver1");
690 break;
691 case CK_BTVER2:
692 defineCPUMacros(Builder, CPUName: "btver2");
693 break;
694 case CK_BDVER1:
695 defineCPUMacros(Builder, CPUName: "bdver1");
696 break;
697 case CK_BDVER2:
698 defineCPUMacros(Builder, CPUName: "bdver2");
699 break;
700 case CK_BDVER3:
701 defineCPUMacros(Builder, CPUName: "bdver3");
702 break;
703 case CK_BDVER4:
704 defineCPUMacros(Builder, CPUName: "bdver4");
705 break;
706 case CK_ZNVER1:
707 defineCPUMacros(Builder, CPUName: "znver1");
708 break;
709 case CK_ZNVER2:
710 defineCPUMacros(Builder, CPUName: "znver2");
711 break;
712 case CK_ZNVER3:
713 defineCPUMacros(Builder, CPUName: "znver3");
714 break;
715 case CK_ZNVER4:
716 defineCPUMacros(Builder, CPUName: "znver4");
717 break;
718 case CK_ZNVER5:
719 defineCPUMacros(Builder, CPUName: "znver5");
720 break;
721 case CK_ZNVER6:
722 defineCPUMacros(Builder, CPUName: "znver6");
723 break;
724 case CK_Geode:
725 defineCPUMacros(Builder, CPUName: "geode");
726 break;
727 case CK_C86_4G_M4:
728 defineCPUMacros(Builder, CPUName: "c86_4g_m4");
729 break;
730 case CK_C86_4G_M6:
731 defineCPUMacros(Builder, CPUName: "c86_4g_m6");
732 break;
733 case CK_C86_4G_M7:
734 defineCPUMacros(Builder, CPUName: "c86_4g_m7");
735 break;
736 }
737
738 // Target properties.
739 Builder.defineMacro(Name: "__REGISTER_PREFIX__", Value: "");
740
741 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
742 // functions in glibc header files that use FP Stack inline asm which the
743 // backend can't deal with (PR879).
744 Builder.defineMacro(Name: "__NO_MATH_INLINES");
745
746 if (HasAES)
747 Builder.defineMacro(Name: "__AES__");
748
749 if (HasVAES)
750 Builder.defineMacro(Name: "__VAES__");
751
752 if (HasPCLMUL)
753 Builder.defineMacro(Name: "__PCLMUL__");
754
755 if (HasVPCLMULQDQ)
756 Builder.defineMacro(Name: "__VPCLMULQDQ__");
757
758 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
759 // the feature flag only applies to 64-bit mode.
760 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
761 Builder.defineMacro(Name: "__LAHF_SAHF__");
762
763 if (HasLZCNT)
764 Builder.defineMacro(Name: "__LZCNT__");
765
766 if (HasRDRND)
767 Builder.defineMacro(Name: "__RDRND__");
768
769 if (HasFSGSBASE)
770 Builder.defineMacro(Name: "__FSGSBASE__");
771
772 if (HasBMI)
773 Builder.defineMacro(Name: "__BMI__");
774
775 if (HasBMI2)
776 Builder.defineMacro(Name: "__BMI2__");
777
778 if (HasPOPCNT)
779 Builder.defineMacro(Name: "__POPCNT__");
780
781 if (HasRTM)
782 Builder.defineMacro(Name: "__RTM__");
783
784 if (HasPRFCHW)
785 Builder.defineMacro(Name: "__PRFCHW__");
786
787 if (HasRDSEED)
788 Builder.defineMacro(Name: "__RDSEED__");
789
790 if (HasADX)
791 Builder.defineMacro(Name: "__ADX__");
792
793 if (HasTBM)
794 Builder.defineMacro(Name: "__TBM__");
795
796 if (HasLWP)
797 Builder.defineMacro(Name: "__LWP__");
798
799 if (HasMWAITX)
800 Builder.defineMacro(Name: "__MWAITX__");
801
802 if (HasMOVBE)
803 Builder.defineMacro(Name: "__MOVBE__");
804
805 switch (XOPLevel) {
806 case XOP:
807 Builder.defineMacro(Name: "__XOP__");
808 [[fallthrough]];
809 case FMA4:
810 Builder.defineMacro(Name: "__FMA4__");
811 [[fallthrough]];
812 case SSE4A:
813 Builder.defineMacro(Name: "__SSE4A__");
814 [[fallthrough]];
815 case NoXOP:
816 break;
817 }
818
819 if (HasFMA)
820 Builder.defineMacro(Name: "__FMA__");
821
822 if (HasF16C)
823 Builder.defineMacro(Name: "__F16C__");
824
825 if (HasGFNI)
826 Builder.defineMacro(Name: "__GFNI__");
827
828 if (HasAVX10_1) {
829 Builder.defineMacro(Name: "__AVX10_1__");
830 Builder.defineMacro(Name: "__AVX10_1_512__");
831 }
832 if (HasAVX10_2) {
833 Builder.defineMacro(Name: "__AVX10_2__");
834 Builder.defineMacro(Name: "__AVX10_2_512__");
835 }
836 if (HasAVX512CD)
837 Builder.defineMacro(Name: "__AVX512CD__");
838 if (HasAVX512VPOPCNTDQ)
839 Builder.defineMacro(Name: "__AVX512VPOPCNTDQ__");
840 if (HasAVX512VNNI)
841 Builder.defineMacro(Name: "__AVX512VNNI__");
842 if (HasAVX512BF16)
843 Builder.defineMacro(Name: "__AVX512BF16__");
844 if (HasAVX512FP16)
845 Builder.defineMacro(Name: "__AVX512FP16__");
846 if (HasAVX512DQ)
847 Builder.defineMacro(Name: "__AVX512DQ__");
848 if (HasAVX512BITALG)
849 Builder.defineMacro(Name: "__AVX512BITALG__");
850 if (HasAVX512BW)
851 Builder.defineMacro(Name: "__AVX512BW__");
852 if (HasAVX512VL) {
853 Builder.defineMacro(Name: "__AVX512VL__");
854 }
855 if (HasAVX512VBMI)
856 Builder.defineMacro(Name: "__AVX512VBMI__");
857 if (HasAVX512VBMI2)
858 Builder.defineMacro(Name: "__AVX512VBMI2__");
859 if (HasAVX512IFMA)
860 Builder.defineMacro(Name: "__AVX512IFMA__");
861 if (HasAVX512VP2INTERSECT)
862 Builder.defineMacro(Name: "__AVX512VP2INTERSECT__");
863 if (HasSHA)
864 Builder.defineMacro(Name: "__SHA__");
865 if (HasSHA512)
866 Builder.defineMacro(Name: "__SHA512__");
867
868 if (HasFXSR)
869 Builder.defineMacro(Name: "__FXSR__");
870 if (HasXSAVE)
871 Builder.defineMacro(Name: "__XSAVE__");
872 if (HasXSAVEOPT)
873 Builder.defineMacro(Name: "__XSAVEOPT__");
874 if (HasXSAVEC)
875 Builder.defineMacro(Name: "__XSAVEC__");
876 if (HasXSAVES)
877 Builder.defineMacro(Name: "__XSAVES__");
878 if (HasPKU)
879 Builder.defineMacro(Name: "__PKU__");
880 if (HasCLFLUSHOPT)
881 Builder.defineMacro(Name: "__CLFLUSHOPT__");
882 if (HasCLWB)
883 Builder.defineMacro(Name: "__CLWB__");
884 if (HasWBNOINVD)
885 Builder.defineMacro(Name: "__WBNOINVD__");
886 if (HasSHSTK)
887 Builder.defineMacro(Name: "__SHSTK__");
888 if (HasSGX)
889 Builder.defineMacro(Name: "__SGX__");
890 if (HasSM3)
891 Builder.defineMacro(Name: "__SM3__");
892 if (HasSM4)
893 Builder.defineMacro(Name: "__SM4__");
894 if (HasPREFETCHI)
895 Builder.defineMacro(Name: "__PREFETCHI__");
896 if (HasCLZERO)
897 Builder.defineMacro(Name: "__CLZERO__");
898 if (HasKL)
899 Builder.defineMacro(Name: "__KL__");
900 if (HasWIDEKL)
901 Builder.defineMacro(Name: "__WIDEKL__");
902 if (HasRDPID)
903 Builder.defineMacro(Name: "__RDPID__");
904 if (HasRDPRU)
905 Builder.defineMacro(Name: "__RDPRU__");
906 if (HasCLDEMOTE)
907 Builder.defineMacro(Name: "__CLDEMOTE__");
908 if (HasWAITPKG)
909 Builder.defineMacro(Name: "__WAITPKG__");
910 if (HasMOVDIRI)
911 Builder.defineMacro(Name: "__MOVDIRI__");
912 if (HasMOVDIR64B)
913 Builder.defineMacro(Name: "__MOVDIR64B__");
914 if (HasMOVRS)
915 Builder.defineMacro(Name: "__MOVRS__");
916 if (HasPCONFIG)
917 Builder.defineMacro(Name: "__PCONFIG__");
918 if (HasPTWRITE)
919 Builder.defineMacro(Name: "__PTWRITE__");
920 if (HasINVPCID)
921 Builder.defineMacro(Name: "__INVPCID__");
922 if (HasENQCMD)
923 Builder.defineMacro(Name: "__ENQCMD__");
924 if (HasHRESET)
925 Builder.defineMacro(Name: "__HRESET__");
926 if (HasAMXTILE)
927 Builder.defineMacro(Name: "__AMX_TILE__");
928 if (HasAMXINT8)
929 Builder.defineMacro(Name: "__AMX_INT8__");
930 if (HasAMXBF16)
931 Builder.defineMacro(Name: "__AMX_BF16__");
932 if (HasAMXFP16)
933 Builder.defineMacro(Name: "__AMX_FP16__");
934 if (HasAMXCOMPLEX)
935 Builder.defineMacro(Name: "__AMX_COMPLEX__");
936 if (HasAMXFP8)
937 Builder.defineMacro(Name: "__AMX_FP8__");
938 if (HasAMXMOVRS)
939 Builder.defineMacro(Name: "__AMX_MOVRS__");
940 if (HasAMXAVX512)
941 Builder.defineMacro(Name: "__AMX_AVX512__");
942 if (HasAMXTF32)
943 Builder.defineMacro(Name: "__AMX_TF32__");
944 if (HasCMPCCXADD)
945 Builder.defineMacro(Name: "__CMPCCXADD__");
946 if (HasRAOINT)
947 Builder.defineMacro(Name: "__RAOINT__");
948 if (HasAVXIFMA)
949 Builder.defineMacro(Name: "__AVXIFMA__");
950 if (HasAVXNECONVERT)
951 Builder.defineMacro(Name: "__AVXNECONVERT__");
952 if (HasAVXVNNI)
953 Builder.defineMacro(Name: "__AVXVNNI__");
954 if (HasAVXVNNIINT16)
955 Builder.defineMacro(Name: "__AVXVNNIINT16__");
956 if (HasAVXVNNIINT8)
957 Builder.defineMacro(Name: "__AVXVNNIINT8__");
958 if (HasSERIALIZE)
959 Builder.defineMacro(Name: "__SERIALIZE__");
960 if (HasTSXLDTRK)
961 Builder.defineMacro(Name: "__TSXLDTRK__");
962 if (HasUINTR)
963 Builder.defineMacro(Name: "__UINTR__");
964 if (HasUSERMSR)
965 Builder.defineMacro(Name: "__USERMSR__");
966 if (HasCRC32)
967 Builder.defineMacro(Name: "__CRC32__");
968 if (HasEGPR)
969 Builder.defineMacro(Name: "__EGPR__");
970 if (HasPush2Pop2)
971 Builder.defineMacro(Name: "__PUSH2POP2__");
972 if (HasPPX)
973 Builder.defineMacro(Name: "__PPX__");
974 if (HasNDD)
975 Builder.defineMacro(Name: "__NDD__");
976 if (HasCCMP)
977 Builder.defineMacro(Name: "__CCMP__");
978 if (HasNF)
979 Builder.defineMacro(Name: "__NF__");
980 if (HasCF)
981 Builder.defineMacro(Name: "__CF__");
982 if (HasZU)
983 Builder.defineMacro(Name: "__ZU__");
984 if (HasJMPABS)
985 Builder.defineMacro(Name: "__JMPABS__");
986 if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD && HasCCMP && HasNF &&
987 HasZU && HasJMPABS)
988 Builder.defineMacro(Name: "__APX_F__");
989 if (HasEGPR && HasInlineAsmUseGPR32)
990 Builder.defineMacro(Name: "__APX_INLINE_ASM_USE_GPR32__");
991
992 // Each case falls through to the previous one here.
993 switch (SSELevel) {
994 case AVX512F:
995 Builder.defineMacro(Name: "__AVX512F__");
996 [[fallthrough]];
997 case AVX2:
998 Builder.defineMacro(Name: "__AVX2__");
999 [[fallthrough]];
1000 case AVX:
1001 Builder.defineMacro(Name: "__AVX__");
1002 [[fallthrough]];
1003 case SSE42:
1004 Builder.defineMacro(Name: "__SSE4_2__");
1005 [[fallthrough]];
1006 case SSE41:
1007 Builder.defineMacro(Name: "__SSE4_1__");
1008 [[fallthrough]];
1009 case SSSE3:
1010 Builder.defineMacro(Name: "__SSSE3__");
1011 [[fallthrough]];
1012 case SSE3:
1013 Builder.defineMacro(Name: "__SSE3__");
1014 [[fallthrough]];
1015 case SSE2:
1016 Builder.defineMacro(Name: "__SSE2__");
1017 Builder.defineMacro(Name: "__SSE2_MATH__"); // -mfp-math=sse always implied.
1018 [[fallthrough]];
1019 case SSE1:
1020 Builder.defineMacro(Name: "__SSE__");
1021 Builder.defineMacro(Name: "__SSE_MATH__"); // -mfp-math=sse always implied.
1022 [[fallthrough]];
1023 case NoSSE:
1024 break;
1025 }
1026
1027 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1028 switch (SSELevel) {
1029 case AVX512F:
1030 case AVX2:
1031 case AVX:
1032 case SSE42:
1033 case SSE41:
1034 case SSSE3:
1035 case SSE3:
1036 case SSE2:
1037 Builder.defineMacro(Name: "_M_IX86_FP", Value: Twine(2));
1038 break;
1039 case SSE1:
1040 Builder.defineMacro(Name: "_M_IX86_FP", Value: Twine(1));
1041 break;
1042 default:
1043 Builder.defineMacro(Name: "_M_IX86_FP", Value: Twine(0));
1044 break;
1045 }
1046 }
1047
1048 // Each case falls through to the previous one here.
1049 if (HasMMX) {
1050 Builder.defineMacro(Name: "__MMX__");
1051 }
1052
1053 if (CPU >= CK_i486 || CPU == CK_None) {
1054 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1055 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1056 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1057 }
1058 if (HasCX8)
1059 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1060 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
1061 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1062
1063 if (HasFloat128)
1064 Builder.defineMacro(Name: "__SIZEOF_FLOAT128__", Value: "16");
1065
1066 if (Opts.CFProtectionReturn || Opts.CFProtectionBranch)
1067 Builder.defineMacro(Name: "__CET__", Value: Twine{(Opts.CFProtectionReturn << 1) |
1068 Opts.CFProtectionBranch});
1069}
1070
1071bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1072 return llvm::StringSwitch<bool>(Name)
1073 .Case(S: "adx", Value: true)
1074 .Case(S: "aes", Value: true)
1075 .Case(S: "amx-avx512", Value: true)
1076 .Case(S: "amx-bf16", Value: true)
1077 .Case(S: "amx-complex", Value: true)
1078 .Case(S: "amx-fp16", Value: true)
1079 .Case(S: "amx-fp8", Value: true)
1080 .Case(S: "amx-int8", Value: true)
1081 .Case(S: "amx-movrs", Value: true)
1082 .Case(S: "amx-tf32", Value: true)
1083 .Case(S: "amx-tile", Value: true)
1084 .Case(S: "avx", Value: true)
1085 .Case(S: "avx10.1", Value: true)
1086 .Case(S: "avx10.2", Value: true)
1087 .Case(S: "avx2", Value: true)
1088 .Case(S: "avx512f", Value: true)
1089 .Case(S: "avx512cd", Value: true)
1090 .Case(S: "avx512vpopcntdq", Value: true)
1091 .Case(S: "avx512vnni", Value: true)
1092 .Case(S: "avx512bf16", Value: true)
1093 .Case(S: "avx512fp16", Value: true)
1094 .Case(S: "avx512dq", Value: true)
1095 .Case(S: "avx512bitalg", Value: true)
1096 .Case(S: "avx512bw", Value: true)
1097 .Case(S: "avx512vl", Value: true)
1098 .Case(S: "avx512vbmi", Value: true)
1099 .Case(S: "avx512vbmi2", Value: true)
1100 .Case(S: "avx512ifma", Value: true)
1101 .Case(S: "avx512vp2intersect", Value: true)
1102 .Case(S: "avxifma", Value: true)
1103 .Case(S: "avxneconvert", Value: true)
1104 .Case(S: "avxvnni", Value: true)
1105 .Case(S: "avxvnniint16", Value: true)
1106 .Case(S: "avxvnniint8", Value: true)
1107 .Case(S: "bmi", Value: true)
1108 .Case(S: "bmi2", Value: true)
1109 .Case(S: "cldemote", Value: true)
1110 .Case(S: "clflushopt", Value: true)
1111 .Case(S: "clwb", Value: true)
1112 .Case(S: "clzero", Value: true)
1113 .Case(S: "cmpccxadd", Value: true)
1114 .Case(S: "crc32", Value: true)
1115 .Case(S: "cx16", Value: true)
1116 .Case(S: "enqcmd", Value: true)
1117 .Case(S: "f16c", Value: true)
1118 .Case(S: "fma", Value: true)
1119 .Case(S: "fma4", Value: true)
1120 .Case(S: "fsgsbase", Value: true)
1121 .Case(S: "fxsr", Value: true)
1122 .Case(S: "general-regs-only", Value: true)
1123 .Case(S: "gfni", Value: true)
1124 .Case(S: "hreset", Value: true)
1125 .Case(S: "invpcid", Value: true)
1126 .Case(S: "kl", Value: true)
1127 .Case(S: "widekl", Value: true)
1128 .Case(S: "lwp", Value: true)
1129 .Case(S: "lzcnt", Value: true)
1130 .Case(S: "mmx", Value: true)
1131 .Case(S: "movbe", Value: true)
1132 .Case(S: "movrs", Value: true)
1133 .Case(S: "movdiri", Value: true)
1134 .Case(S: "movdir64b", Value: true)
1135 .Case(S: "mwaitx", Value: true)
1136 .Case(S: "pclmul", Value: true)
1137 .Case(S: "pconfig", Value: true)
1138 .Case(S: "pku", Value: true)
1139 .Case(S: "popcnt", Value: true)
1140 .Case(S: "prefer-256-bit", Value: true)
1141 .Case(S: "prefetchi", Value: true)
1142 .Case(S: "prfchw", Value: true)
1143 .Case(S: "ptwrite", Value: true)
1144 .Case(S: "raoint", Value: true)
1145 .Case(S: "rdpid", Value: true)
1146 .Case(S: "rdpru", Value: true)
1147 .Case(S: "rdrnd", Value: true)
1148 .Case(S: "rdseed", Value: true)
1149 .Case(S: "rtm", Value: true)
1150 .Case(S: "sahf", Value: true)
1151 .Case(S: "serialize", Value: true)
1152 .Case(S: "sgx", Value: true)
1153 .Case(S: "sha", Value: true)
1154 .Case(S: "sha512", Value: true)
1155 .Case(S: "shstk", Value: true)
1156 .Case(S: "sm3", Value: true)
1157 .Case(S: "sm4", Value: true)
1158 .Case(S: "sse", Value: true)
1159 .Case(S: "sse2", Value: true)
1160 .Case(S: "sse3", Value: true)
1161 .Case(S: "ssse3", Value: true)
1162 .Case(S: "sse4", Value: true)
1163 .Case(S: "sse4.1", Value: true)
1164 .Case(S: "sse4.2", Value: true)
1165 .Case(S: "sse4a", Value: true)
1166 .Case(S: "tbm", Value: true)
1167 .Case(S: "tsxldtrk", Value: true)
1168 .Case(S: "uintr", Value: true)
1169 .Case(S: "usermsr", Value: true)
1170 .Case(S: "vaes", Value: true)
1171 .Case(S: "vpclmulqdq", Value: true)
1172 .Case(S: "wbnoinvd", Value: true)
1173 .Case(S: "waitpkg", Value: true)
1174 .Case(S: "x87", Value: true)
1175 .Case(S: "xop", Value: true)
1176 .Case(S: "xsave", Value: true)
1177 .Case(S: "xsavec", Value: true)
1178 .Case(S: "xsaves", Value: true)
1179 .Case(S: "xsaveopt", Value: true)
1180 .Case(S: "egpr", Value: true)
1181 .Case(S: "push2pop2", Value: true)
1182 .Case(S: "ppx", Value: true)
1183 .Case(S: "ndd", Value: true)
1184 .Case(S: "ccmp", Value: true)
1185 .Case(S: "nf", Value: true)
1186 .Case(S: "cf", Value: true)
1187 .Case(S: "zu", Value: true)
1188 .Case(S: "jmpabs", Value: true)
1189 .Default(Value: false);
1190}
1191
1192bool X86TargetInfo::hasFeature(StringRef Feature) const {
1193 return llvm::StringSwitch<bool>(Feature)
1194 .Case(S: "adx", Value: HasADX)
1195 .Case(S: "aes", Value: HasAES)
1196 .Case(S: "amx-avx512", Value: HasAMXAVX512)
1197 .Case(S: "amx-bf16", Value: HasAMXBF16)
1198 .Case(S: "amx-complex", Value: HasAMXCOMPLEX)
1199 .Case(S: "amx-fp16", Value: HasAMXFP16)
1200 .Case(S: "amx-fp8", Value: HasAMXFP8)
1201 .Case(S: "amx-int8", Value: HasAMXINT8)
1202 .Case(S: "amx-movrs", Value: HasAMXMOVRS)
1203 .Case(S: "amx-tf32", Value: HasAMXTF32)
1204 .Case(S: "amx-tile", Value: HasAMXTILE)
1205 .Case(S: "avx", Value: SSELevel >= AVX)
1206 .Case(S: "avx10.1", Value: HasAVX10_1)
1207 .Case(S: "avx10.2", Value: HasAVX10_2)
1208 .Case(S: "avx2", Value: SSELevel >= AVX2)
1209 .Case(S: "avx512f", Value: SSELevel >= AVX512F)
1210 .Case(S: "avx512cd", Value: HasAVX512CD)
1211 .Case(S: "avx512vpopcntdq", Value: HasAVX512VPOPCNTDQ)
1212 .Case(S: "avx512vnni", Value: HasAVX512VNNI)
1213 .Case(S: "avx512bf16", Value: HasAVX512BF16)
1214 .Case(S: "avx512fp16", Value: HasAVX512FP16)
1215 .Case(S: "avx512dq", Value: HasAVX512DQ)
1216 .Case(S: "avx512bitalg", Value: HasAVX512BITALG)
1217 .Case(S: "avx512bw", Value: HasAVX512BW)
1218 .Case(S: "avx512vl", Value: HasAVX512VL)
1219 .Case(S: "avx512vbmi", Value: HasAVX512VBMI)
1220 .Case(S: "avx512vbmi2", Value: HasAVX512VBMI2)
1221 .Case(S: "avx512ifma", Value: HasAVX512IFMA)
1222 .Case(S: "avx512vp2intersect", Value: HasAVX512VP2INTERSECT)
1223 .Case(S: "avxifma", Value: HasAVXIFMA)
1224 .Case(S: "avxneconvert", Value: HasAVXNECONVERT)
1225 .Case(S: "avxvnni", Value: HasAVXVNNI)
1226 .Case(S: "avxvnniint16", Value: HasAVXVNNIINT16)
1227 .Case(S: "avxvnniint8", Value: HasAVXVNNIINT8)
1228 .Case(S: "bmi", Value: HasBMI)
1229 .Case(S: "bmi2", Value: HasBMI2)
1230 .Case(S: "cldemote", Value: HasCLDEMOTE)
1231 .Case(S: "clflushopt", Value: HasCLFLUSHOPT)
1232 .Case(S: "clwb", Value: HasCLWB)
1233 .Case(S: "clzero", Value: HasCLZERO)
1234 .Case(S: "cmpccxadd", Value: HasCMPCCXADD)
1235 .Case(S: "crc32", Value: HasCRC32)
1236 .Case(S: "cx8", Value: HasCX8)
1237 .Case(S: "cx16", Value: HasCX16)
1238 .Case(S: "enqcmd", Value: HasENQCMD)
1239 .Case(S: "f16c", Value: HasF16C)
1240 .Case(S: "fma", Value: HasFMA)
1241 .Case(S: "fma4", Value: XOPLevel >= FMA4)
1242 .Case(S: "fsgsbase", Value: HasFSGSBASE)
1243 .Case(S: "fxsr", Value: HasFXSR)
1244 .Case(S: "gfni", Value: HasGFNI)
1245 .Case(S: "hreset", Value: HasHRESET)
1246 .Case(S: "invpcid", Value: HasINVPCID)
1247 .Case(S: "kl", Value: HasKL)
1248 .Case(S: "widekl", Value: HasWIDEKL)
1249 .Case(S: "lwp", Value: HasLWP)
1250 .Case(S: "lzcnt", Value: HasLZCNT)
1251 .Case(S: "mmx", Value: HasMMX)
1252 .Case(S: "movbe", Value: HasMOVBE)
1253 .Case(S: "movrs", Value: HasMOVRS)
1254 .Case(S: "movdiri", Value: HasMOVDIRI)
1255 .Case(S: "movdir64b", Value: HasMOVDIR64B)
1256 .Case(S: "mwaitx", Value: HasMWAITX)
1257 .Case(S: "pclmul", Value: HasPCLMUL)
1258 .Case(S: "pconfig", Value: HasPCONFIG)
1259 .Case(S: "pku", Value: HasPKU)
1260 .Case(S: "popcnt", Value: HasPOPCNT)
1261 .Case(S: "prefetchi", Value: HasPREFETCHI)
1262 .Case(S: "prfchw", Value: HasPRFCHW)
1263 .Case(S: "ptwrite", Value: HasPTWRITE)
1264 .Case(S: "raoint", Value: HasRAOINT)
1265 .Case(S: "rdpid", Value: HasRDPID)
1266 .Case(S: "rdpru", Value: HasRDPRU)
1267 .Case(S: "rdrnd", Value: HasRDRND)
1268 .Case(S: "rdseed", Value: HasRDSEED)
1269 .Case(S: "retpoline-external-thunk", Value: HasRetpolineExternalThunk)
1270 .Case(S: "rtm", Value: HasRTM)
1271 .Case(S: "sahf", Value: HasLAHFSAHF)
1272 .Case(S: "serialize", Value: HasSERIALIZE)
1273 .Case(S: "sgx", Value: HasSGX)
1274 .Case(S: "sha", Value: HasSHA)
1275 .Case(S: "sha512", Value: HasSHA512)
1276 .Case(S: "shstk", Value: HasSHSTK)
1277 .Case(S: "sm3", Value: HasSM3)
1278 .Case(S: "sm4", Value: HasSM4)
1279 .Case(S: "sse", Value: SSELevel >= SSE1)
1280 .Case(S: "sse2", Value: SSELevel >= SSE2)
1281 .Case(S: "sse3", Value: SSELevel >= SSE3)
1282 .Case(S: "ssse3", Value: SSELevel >= SSSE3)
1283 .Case(S: "sse4.1", Value: SSELevel >= SSE41)
1284 .Case(S: "sse4.2", Value: SSELevel >= SSE42)
1285 .Case(S: "sse4a", Value: XOPLevel >= SSE4A)
1286 .Case(S: "tbm", Value: HasTBM)
1287 .Case(S: "tsxldtrk", Value: HasTSXLDTRK)
1288 .Case(S: "uintr", Value: HasUINTR)
1289 .Case(S: "usermsr", Value: HasUSERMSR)
1290 .Case(S: "vaes", Value: HasVAES)
1291 .Case(S: "vpclmulqdq", Value: HasVPCLMULQDQ)
1292 .Case(S: "wbnoinvd", Value: HasWBNOINVD)
1293 .Case(S: "waitpkg", Value: HasWAITPKG)
1294 .Case(S: "x86", Value: true)
1295 .Case(S: "x86_32", Value: getTriple().getArch() == llvm::Triple::x86)
1296 .Case(S: "x86_64", Value: getTriple().getArch() == llvm::Triple::x86_64)
1297 .Case(S: "x87", Value: HasX87)
1298 .Case(S: "xop", Value: XOPLevel >= XOP)
1299 .Case(S: "xsave", Value: HasXSAVE)
1300 .Case(S: "xsavec", Value: HasXSAVEC)
1301 .Case(S: "xsaves", Value: HasXSAVES)
1302 .Case(S: "xsaveopt", Value: HasXSAVEOPT)
1303 .Case(S: "fullbf16", Value: HasFullBFloat16)
1304 .Case(S: "egpr", Value: HasEGPR)
1305 .Case(S: "push2pop2", Value: HasPush2Pop2)
1306 .Case(S: "ppx", Value: HasPPX)
1307 .Case(S: "ndd", Value: HasNDD)
1308 .Case(S: "ccmp", Value: HasCCMP)
1309 .Case(S: "nf", Value: HasNF)
1310 .Case(S: "cf", Value: HasCF)
1311 .Case(S: "zu", Value: HasZU)
1312 .Case(S: "jmpabs", Value: HasJMPABS)
1313 .Case(S: "branch-hint", Value: HasBranchHint)
1314 .Default(Value: false);
1315}
1316
1317// We can't use a generic validation scheme for the features accepted here
1318// versus subtarget features accepted in the target attribute because the
1319// bitfield structure that's initialized in the runtime only supports the
1320// below currently rather than the full range of subtarget features. (See
1321// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1322bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1323 return llvm::StringSwitch<bool>(FeatureStr)
1324#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1325#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1326#include "llvm/TargetParser/X86TargetParser.def"
1327 .Default(Value: false);
1328}
1329
1330static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1331 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1332#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) \
1333 .Case(STR, llvm::X86::FEATURE_##ENUM)
1334
1335#include "llvm/TargetParser/X86TargetParser.def"
1336 ;
1337 // Note, this function should only be used after ensuring the value is
1338 // correct, so it asserts if the value is out of range.
1339}
1340
1341llvm::APInt X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
1342 auto getPriority = [](StringRef Feature) -> unsigned {
1343 // Valid CPUs have a 'key feature' that compares just better than its key
1344 // feature.
1345 using namespace llvm::X86;
1346 CPUKind Kind = parseArchX86(CPU: Feature);
1347 if (Kind != CK_None) {
1348 ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1349 return (getFeaturePriority(Feat: KeyFeature) << 1) + 1;
1350 }
1351 // Now we know we have a feature, so get its priority and shift it a few so
1352 // that we have sufficient room for the CPUs (above).
1353 return getFeaturePriority(Feat: getFeature(Name: Feature)) << 1;
1354 };
1355
1356 unsigned Priority = 0;
1357 for (StringRef Feature : Features)
1358 if (!Feature.empty())
1359 Priority = std::max(a: Priority, b: getPriority(Feature));
1360 return llvm::APInt(32, Priority);
1361}
1362
1363bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1364 return llvm::X86::validateCPUSpecificCPUDispatch(Name);
1365}
1366
1367char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1368 return llvm::X86::getCPUDispatchMangling(Name);
1369}
1370
1371void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1372 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1373 SmallVector<StringRef, 32> TargetCPUFeatures;
1374 llvm::X86::getFeaturesForCPU(CPU: Name, Features&: TargetCPUFeatures, NeedPlus: true);
1375 for (auto &F : TargetCPUFeatures)
1376 Features.push_back(Elt: F);
1377}
1378
1379// We can't use a generic validation scheme for the cpus accepted here
1380// versus subtarget cpus accepted in the target attribute because the
1381// variables intitialized by the runtime only support the below currently
1382// rather than the full range of cpus.
1383bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1384 return llvm::StringSwitch<bool>(FeatureStr)
1385#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1386#define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1387#define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1388#define X86_CPU_SUBTYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1389#define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1390#include "llvm/TargetParser/X86TargetParser.def"
1391 .Default(Value: false);
1392}
1393
1394static unsigned matchAsmCCConstraint(const char *Name) {
1395 auto RV = llvm::StringSwitch<unsigned>(Name)
1396 .Case(S: "@cca", Value: 4)
1397 .Case(S: "@ccae", Value: 5)
1398 .Case(S: "@ccb", Value: 4)
1399 .Case(S: "@ccbe", Value: 5)
1400 .Case(S: "@ccc", Value: 4)
1401 .Case(S: "@cce", Value: 4)
1402 .Case(S: "@ccz", Value: 4)
1403 .Case(S: "@ccg", Value: 4)
1404 .Case(S: "@ccge", Value: 5)
1405 .Case(S: "@ccl", Value: 4)
1406 .Case(S: "@ccle", Value: 5)
1407 .Case(S: "@ccna", Value: 5)
1408 .Case(S: "@ccnae", Value: 6)
1409 .Case(S: "@ccnb", Value: 5)
1410 .Case(S: "@ccnbe", Value: 6)
1411 .Case(S: "@ccnc", Value: 5)
1412 .Case(S: "@ccne", Value: 5)
1413 .Case(S: "@ccnz", Value: 5)
1414 .Case(S: "@ccng", Value: 5)
1415 .Case(S: "@ccnge", Value: 6)
1416 .Case(S: "@ccnl", Value: 5)
1417 .Case(S: "@ccnle", Value: 6)
1418 .Case(S: "@ccno", Value: 5)
1419 .Case(S: "@ccnp", Value: 5)
1420 .Case(S: "@ccns", Value: 5)
1421 .Case(S: "@cco", Value: 4)
1422 .Case(S: "@ccp", Value: 4)
1423 .Case(S: "@ccs", Value: 4)
1424 .Default(Value: 0);
1425 return RV;
1426}
1427
1428bool X86TargetInfo::validateAsmConstraint(
1429 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1430 switch (*Name) {
1431 default:
1432 return false;
1433 // Constant constraints.
1434 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1435 // instructions.
1436 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1437 // x86_64 instructions.
1438 case 's':
1439 Info.setRequiresImmediate();
1440 return true;
1441 case 'I':
1442 Info.setRequiresImmediate(Min: 0, Max: 31);
1443 return true;
1444 case 'J':
1445 Info.setRequiresImmediate(Min: 0, Max: 63);
1446 return true;
1447 case 'K':
1448 Info.setRequiresImmediate(Min: -128, Max: 127);
1449 return true;
1450 case 'L':
1451 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1452 return true;
1453 case 'M':
1454 Info.setRequiresImmediate(Min: 0, Max: 3);
1455 return true;
1456 case 'N':
1457 Info.setRequiresImmediate(Min: 0, Max: 255);
1458 return true;
1459 case 'O':
1460 Info.setRequiresImmediate(Min: 0, Max: 127);
1461 return true;
1462 case 'W':
1463 switch (*++Name) {
1464 default:
1465 return false;
1466 case 's':
1467 Info.setAllowsRegister();
1468 return true;
1469 }
1470 // Register constraints.
1471 case 'Y': // 'Y' is the first character for several 2-character constraints.
1472 // Shift the pointer to the second character of the constraint.
1473 Name++;
1474 switch (*Name) {
1475 default:
1476 return false;
1477 case 'z': // First SSE register.
1478 case '2':
1479 case 't': // Any SSE register, when SSE2 is enabled.
1480 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1481 case 'm': // Any MMX register, when inter-unit moves enabled.
1482 case 'k': // AVX512 arch mask registers: k1-k7.
1483 Info.setAllowsRegister();
1484 return true;
1485 }
1486 case 'f': // Any x87 floating point stack register.
1487 // Constraint 'f' cannot be used for output operands.
1488 if (Info.ConstraintStr[0] == '=' || Info.ConstraintStr[0] == '+')
1489 return false;
1490 Info.setAllowsRegister();
1491 return true;
1492 case 'a': // eax.
1493 case 'b': // ebx.
1494 case 'c': // ecx.
1495 case 'd': // edx.
1496 case 'S': // esi.
1497 case 'D': // edi.
1498 case 'A': // edx:eax.
1499 case 't': // Top of floating point stack.
1500 case 'u': // Second from top of floating point stack.
1501 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1502 case 'y': // Any MMX register.
1503 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1504 case 'x': // Any SSE register.
1505 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1506 // for intermideate k reg operations).
1507 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1508 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1509 case 'l': // "Index" registers: any general register that can be used as an
1510 // index in a base+index memory access.
1511 Info.setAllowsRegister();
1512 return true;
1513 // Floating point constant constraints.
1514 case 'C': // SSE floating point constant.
1515 case 'G': // x87 floating point constant.
1516 return true;
1517 case 'j':
1518 Name++;
1519 switch (*Name) {
1520 default:
1521 return false;
1522 case 'r':
1523 Info.setAllowsRegister();
1524 return true;
1525 case 'R':
1526 Info.setAllowsRegister();
1527 return true;
1528 }
1529 case '@':
1530 // CC condition changes.
1531 if (auto Len = matchAsmCCConstraint(Name)) {
1532 Name += Len - 1;
1533 Info.setAllowsRegister();
1534 Info.setOutputOperandBounds(Min: 0, Max: 2);
1535 return true;
1536 }
1537 return false;
1538 }
1539}
1540
1541// Below is based on the following information:
1542// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1543// | Processor Name | Cache Line Size (Bytes) | Source |
1544// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1545// | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1546// | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1547// | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1548// | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1549// | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1550// | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1551// | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1552// | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1553// | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1554// | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1555// | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1556// | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1557// | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1558// | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1559// | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1560// | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1561// | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1562// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1563std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1564 using namespace llvm::X86;
1565 switch (CPU) {
1566 // i386
1567 case CK_i386:
1568 // i486
1569 case CK_i486:
1570 case CK_WinChipC6:
1571 case CK_WinChip2:
1572 case CK_C3:
1573 // Lakemont
1574 case CK_Lakemont:
1575 return 16;
1576
1577 // i586
1578 case CK_i586:
1579 case CK_Pentium:
1580 case CK_PentiumMMX:
1581 // i686
1582 case CK_PentiumPro:
1583 case CK_i686:
1584 case CK_Pentium2:
1585 case CK_Pentium3:
1586 case CK_PentiumM:
1587 case CK_C3_2:
1588 // K6
1589 case CK_K6:
1590 case CK_K6_2:
1591 case CK_K6_3:
1592 // Geode
1593 case CK_Geode:
1594 return 32;
1595
1596 // Netburst
1597 case CK_Pentium4:
1598 case CK_Prescott:
1599 case CK_Nocona:
1600 // Atom
1601 case CK_Bonnell:
1602 case CK_Silvermont:
1603 case CK_Goldmont:
1604 case CK_GoldmontPlus:
1605 case CK_Tremont:
1606 case CK_Gracemont:
1607
1608 case CK_Westmere:
1609 case CK_SandyBridge:
1610 case CK_IvyBridge:
1611 case CK_Haswell:
1612 case CK_Broadwell:
1613 case CK_SkylakeClient:
1614 case CK_SkylakeServer:
1615 case CK_Cascadelake:
1616 case CK_Nehalem:
1617 case CK_Cooperlake:
1618 case CK_Cannonlake:
1619 case CK_Tigerlake:
1620 case CK_SapphireRapids:
1621 case CK_IcelakeClient:
1622 case CK_Rocketlake:
1623 case CK_IcelakeServer:
1624 case CK_Alderlake:
1625 case CK_Raptorlake:
1626 case CK_Meteorlake:
1627 case CK_Arrowlake:
1628 case CK_ArrowlakeS:
1629 case CK_Lunarlake:
1630 case CK_Pantherlake:
1631 case CK_Wildcatlake:
1632 case CK_Novalake:
1633 case CK_Sierraforest:
1634 case CK_Grandridge:
1635 case CK_Graniterapids:
1636 case CK_GraniterapidsD:
1637 case CK_Emeraldrapids:
1638 case CK_Clearwaterforest:
1639 case CK_Diamondrapids:
1640 case CK_KNL:
1641 case CK_KNM:
1642 // K7
1643 case CK_Athlon:
1644 case CK_AthlonXP:
1645 // K8
1646 case CK_K8:
1647 case CK_K8SSE3:
1648 case CK_AMDFAM10:
1649 // Bobcat
1650 case CK_BTVER1:
1651 case CK_BTVER2:
1652 // Bulldozer
1653 case CK_BDVER1:
1654 case CK_BDVER2:
1655 case CK_BDVER3:
1656 case CK_BDVER4:
1657 // Zen
1658 case CK_ZNVER1:
1659 case CK_ZNVER2:
1660 case CK_ZNVER3:
1661 case CK_ZNVER4:
1662 case CK_ZNVER5:
1663 case CK_ZNVER6:
1664 // Hygon
1665 case CK_C86_4G_M4:
1666 case CK_C86_4G_M6:
1667 case CK_C86_4G_M7:
1668 // Deprecated
1669 case CK_x86_64:
1670 case CK_x86_64_v2:
1671 case CK_x86_64_v3:
1672 case CK_x86_64_v4:
1673 case CK_Yonah:
1674 case CK_Penryn:
1675 case CK_Core2:
1676 return 64;
1677
1678 // The following currently have unknown cache line sizes (but they are probably all 64):
1679 // Core
1680 case CK_None:
1681 return std::nullopt;
1682 }
1683 llvm_unreachable("Unknown CPU kind");
1684}
1685
1686bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1687 StringRef Constraint,
1688 unsigned Size) const {
1689 // Strip off constraint modifiers.
1690 Constraint = Constraint.ltrim(Chars: "=+&");
1691
1692 return validateOperandSize(FeatureMap, Constraint, Size);
1693}
1694
1695bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1696 StringRef Constraint,
1697 unsigned Size) const {
1698 return validateOperandSize(FeatureMap, Constraint, Size);
1699}
1700
1701bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1702 StringRef Constraint,
1703 unsigned Size) const {
1704 switch (Constraint[0]) {
1705 default:
1706 break;
1707 case 'k':
1708 // Registers k0-k7 (AVX512) size limit is 64 bit.
1709 case 'y':
1710 return Size <= 64;
1711 case 'f':
1712 case 't':
1713 case 'u':
1714 return Size <= 128;
1715 case 'Y':
1716 // 'Y' is the first character for several 2-character constraints.
1717 switch (Constraint[1]) {
1718 default:
1719 return false;
1720 case 'm':
1721 // 'Ym' is synonymous with 'y'.
1722 case 'k':
1723 return Size <= 64;
1724 case 'z':
1725 // XMM0/YMM/ZMM0
1726 if (hasFeatureEnabled(Features: FeatureMap, Name: "avx512f"))
1727 // ZMM0 can be used if target supports AVX512F.
1728 return Size <= 512U;
1729 else if (hasFeatureEnabled(Features: FeatureMap, Name: "avx"))
1730 // YMM0 can be used if target supports AVX.
1731 return Size <= 256U;
1732 else if (hasFeatureEnabled(Features: FeatureMap, Name: "sse"))
1733 return Size <= 128U;
1734 return false;
1735 case 'i':
1736 case 't':
1737 case '2':
1738 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1739 if (SSELevel < SSE2)
1740 return false;
1741 break;
1742 }
1743 break;
1744 case 'v':
1745 case 'x':
1746 if (hasFeatureEnabled(Features: FeatureMap, Name: "avx512f"))
1747 // 512-bit zmm registers can be used if target supports AVX512F.
1748 return Size <= 512U;
1749 else if (hasFeatureEnabled(Features: FeatureMap, Name: "avx"))
1750 // 256-bit ymm registers can be used if target supports AVX.
1751 return Size <= 256U;
1752 return Size <= 128U;
1753
1754 }
1755
1756 return true;
1757}
1758
1759std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1760 switch (*Constraint) {
1761 case '@':
1762 if (auto Len = matchAsmCCConstraint(Name: Constraint)) {
1763 std::string Converted = "{" + std::string(Constraint, Len) + "}";
1764 Constraint += Len - 1;
1765 return Converted;
1766 }
1767 return std::string(1, *Constraint);
1768 case 'a':
1769 return std::string("{ax}");
1770 case 'b':
1771 return std::string("{bx}");
1772 case 'c':
1773 return std::string("{cx}");
1774 case 'd':
1775 return std::string("{dx}");
1776 case 'S':
1777 return std::string("{si}");
1778 case 'D':
1779 return std::string("{di}");
1780 case 'p': // Keep 'p' constraint (address).
1781 return std::string("p");
1782 case 't': // top of floating point stack.
1783 return std::string("{st}");
1784 case 'u': // second from top of floating point stack.
1785 return std::string("{st(1)}"); // second from top of floating point stack.
1786 case 'W':
1787 assert(Constraint[1] == 's');
1788 return '^' + std::string(Constraint++, 2);
1789 case 'Y':
1790 switch (Constraint[1]) {
1791 default:
1792 // Break from inner switch and fall through (copy single char),
1793 // continue parsing after copying the current constraint into
1794 // the return string.
1795 break;
1796 case 'k':
1797 case 'm':
1798 case 'i':
1799 case 't':
1800 case 'z':
1801 case '2':
1802 // "^" hints llvm that this is a 2 letter constraint.
1803 // "Constraint++" is used to promote the string iterator
1804 // to the next constraint.
1805 return std::string("^") + std::string(Constraint++, 2);
1806 }
1807 [[fallthrough]];
1808 case 'j':
1809 switch (Constraint[1]) {
1810 default:
1811 // Break from inner switch and fall through (copy single char),
1812 // continue parsing after copying the current constraint into
1813 // the return string.
1814 break;
1815 case 'r':
1816 case 'R':
1817 // "^" hints llvm that this is a 2 letter constraint.
1818 // "Constraint++" is used to promote the string iterator
1819 // to the next constraint.
1820 return std::string("^") + std::string(Constraint++, 2);
1821 }
1822 [[fallthrough]];
1823 default:
1824 return std::string(1, *Constraint);
1825 }
1826}
1827
1828void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1829 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1830 llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1831}
1832
1833void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1834 llvm::X86::fillValidTuneCPUList(Values);
1835}
1836
1837ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1838 return llvm::ArrayRef(GCCRegNames);
1839}
1840
1841ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1842 return llvm::ArrayRef(AddlRegNames);
1843}
1844
1845llvm::SmallVector<Builtin::InfosShard>
1846X86_32TargetInfo::getTargetBuiltins() const {
1847 return {
1848 {.Strings: &X86::BuiltinStrings, .Infos: X86::BuiltinInfos},
1849 {.Strings: &X86::BuiltinStrings, .Infos: X86::PrefixedBuiltinInfos, .NamePrefix: "__builtin_ia32_"},
1850 };
1851}
1852
1853llvm::SmallVector<Builtin::InfosShard>
1854X86_64TargetInfo::getTargetBuiltins() const {
1855 return {
1856 {.Strings: &X86::BuiltinStrings, .Infos: X86::BuiltinInfos},
1857 {.Strings: &X86::BuiltinStrings, .Infos: X86::PrefixedBuiltinInfos, .NamePrefix: "__builtin_ia32_"},
1858 {.Strings: &X86_64::BuiltinStrings, .Infos: X86_64::BuiltinInfos},
1859 {.Strings: &X86_64::BuiltinStrings, .Infos: X86_64::PrefixedBuiltinInfos,
1860 .NamePrefix: "__builtin_ia32_"},
1861 };
1862}
1863
1864unsigned
1865MicrosoftX86_64TargetInfo::getMinGlobalAlign(uint64_t TypeSize,
1866 bool HasNonWeakDef) const {
1867 unsigned Align =
1868 WindowsX86_64TargetInfo::getMinGlobalAlign(Size: TypeSize, HasNonWeakDef);
1869
1870 return std::max(a: Align, b: Microsoft64BitMinGlobalAlign(TypeSize));
1871}
1872