1//===--- X86.cpp - Implement X86 target feature support -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements X86 TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86.h"
14#include "clang/Basic/Builtins.h"
15#include "clang/Basic/Diagnostic.h"
16#include "clang/Basic/TargetBuiltins.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/TargetParser/X86TargetParser.h"
20#include <optional>
21
22namespace clang {
23namespace targets {
24
25// The x86-32 builtins are a subset and prefix of the x86-64 builtins.
26static constexpr int NumX86Builtins =
27 X86::LastX86CommonBuiltin - Builtin::FirstTSBuiltin + 1;
28static constexpr int NumX86_64Builtins =
29 X86::LastTSBuiltin - X86::FirstX86_64Builtin;
30static constexpr int NumBuiltins = X86::LastTSBuiltin - Builtin::FirstTSBuiltin;
31static_assert(NumBuiltins == (NumX86Builtins + NumX86_64Builtins));
32
33namespace X86 {
34#define GET_BUILTIN_STR_TABLE
35#include "clang/Basic/BuiltinsX86.inc"
36#undef GET_BUILTIN_STR_TABLE
37
38static constexpr Builtin::Info BuiltinInfos[] = {
39#define GET_BUILTIN_INFOS
40#include "clang/Basic/BuiltinsX86.inc"
41#undef GET_BUILTIN_INFOS
42};
43
44static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
45#define GET_BUILTIN_PREFIXED_INFOS
46#include "clang/Basic/BuiltinsX86.inc"
47#undef GET_BUILTIN_PREFIXED_INFOS
48};
49static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
50 NumX86Builtins);
51} // namespace X86
52
53namespace X86_64 {
54#define GET_BUILTIN_STR_TABLE
55#include "clang/Basic/BuiltinsX86_64.inc"
56#undef GET_BUILTIN_STR_TABLE
57
58static constexpr Builtin::Info BuiltinInfos[] = {
59#define GET_BUILTIN_INFOS
60#include "clang/Basic/BuiltinsX86_64.inc"
61#undef GET_BUILTIN_INFOS
62};
63
64static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
65#define GET_BUILTIN_PREFIXED_INFOS
66#include "clang/Basic/BuiltinsX86_64.inc"
67#undef GET_BUILTIN_PREFIXED_INFOS
68};
69static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
70 NumX86_64Builtins);
71} // namespace X86_64
72
73static const char *const GCCRegNames[] = {
74 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
75 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
76 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
77 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
78 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
79 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
80 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
81 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
82 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
83 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
84 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
85 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
86 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
87 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
88 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
89 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
90 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
91 "k2", "k3", "k4", "k5", "k6", "k7",
92 "cr0", "cr2", "cr3", "cr4", "cr8",
93 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
94 "bnd0", "bnd1", "bnd2", "bnd3",
95 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
96 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
97 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
98};
99
100const TargetInfo::AddlRegName AddlRegNames[] = {
101 {.Names: {"al", "ah", "eax", "rax"}, .RegNum: 0},
102 {.Names: {"bl", "bh", "ebx", "rbx"}, .RegNum: 3},
103 {.Names: {"cl", "ch", "ecx", "rcx"}, .RegNum: 2},
104 {.Names: {"dl", "dh", "edx", "rdx"}, .RegNum: 1},
105 {.Names: {"esi", "rsi"}, .RegNum: 4},
106 {.Names: {"edi", "rdi"}, .RegNum: 5},
107 {.Names: {"esp", "rsp"}, .RegNum: 7},
108 {.Names: {"ebp", "rbp"}, .RegNum: 6},
109 {.Names: {"r8d", "r8w", "r8b"}, .RegNum: 38},
110 {.Names: {"r9d", "r9w", "r9b"}, .RegNum: 39},
111 {.Names: {"r10d", "r10w", "r10b"}, .RegNum: 40},
112 {.Names: {"r11d", "r11w", "r11b"}, .RegNum: 41},
113 {.Names: {"r12d", "r12w", "r12b"}, .RegNum: 42},
114 {.Names: {"r13d", "r13w", "r13b"}, .RegNum: 43},
115 {.Names: {"r14d", "r14w", "r14b"}, .RegNum: 44},
116 {.Names: {"r15d", "r15w", "r15b"}, .RegNum: 45},
117 {.Names: {"r16d", "r16w", "r16b"}, .RegNum: 165},
118 {.Names: {"r17d", "r17w", "r17b"}, .RegNum: 166},
119 {.Names: {"r18d", "r18w", "r18b"}, .RegNum: 167},
120 {.Names: {"r19d", "r19w", "r19b"}, .RegNum: 168},
121 {.Names: {"r20d", "r20w", "r20b"}, .RegNum: 169},
122 {.Names: {"r21d", "r21w", "r21b"}, .RegNum: 170},
123 {.Names: {"r22d", "r22w", "r22b"}, .RegNum: 171},
124 {.Names: {"r23d", "r23w", "r23b"}, .RegNum: 172},
125 {.Names: {"r24d", "r24w", "r24b"}, .RegNum: 173},
126 {.Names: {"r25d", "r25w", "r25b"}, .RegNum: 174},
127 {.Names: {"r26d", "r26w", "r26b"}, .RegNum: 175},
128 {.Names: {"r27d", "r27w", "r27b"}, .RegNum: 176},
129 {.Names: {"r28d", "r28w", "r28b"}, .RegNum: 177},
130 {.Names: {"r29d", "r29w", "r29b"}, .RegNum: 178},
131 {.Names: {"r30d", "r30w", "r30b"}, .RegNum: 179},
132 {.Names: {"r31d", "r31w", "r31b"}, .RegNum: 180},
133};
134} // namespace targets
135} // namespace clang
136
137using namespace clang;
138using namespace clang::targets;
139
140bool X86TargetInfo::setFPMath(StringRef Name) {
141 if (Name == "387") {
142 FPMath = FP_387;
143 return true;
144 }
145 if (Name == "sse") {
146 FPMath = FP_SSE;
147 return true;
148 }
149 return false;
150}
151
152bool X86TargetInfo::initFeatureMap(
153 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
154 const std::vector<std::string> &FeaturesVec) const {
155 // FIXME: This *really* should not be here.
156 // X86_64 always has SSE2.
157 if (getTriple().getArch() == llvm::Triple::x86_64)
158 setFeatureEnabled(Features, Name: "sse2", Enabled: true);
159
160 using namespace llvm::X86;
161
162 SmallVector<StringRef, 16> CPUFeatures;
163 getFeaturesForCPU(CPU, Features&: CPUFeatures);
164 for (auto &F : CPUFeatures)
165 setFeatureEnabled(Features, Name: F, Enabled: true);
166
167 if (Features.lookup(Key: "egpr") && getTriple().isOSWindows()) {
168 setFeatureEnabled(Features, Name: "push2pop2", Enabled: false);
169 setFeatureEnabled(Features, Name: "ppx", Enabled: false);
170 }
171
172 std::vector<std::string> UpdatedFeaturesVec;
173 for (const auto &Feature : FeaturesVec) {
174 // Expand general-regs-only to -x86, -mmx and -sse
175 if (Feature == "+general-regs-only") {
176 UpdatedFeaturesVec.push_back(x: "-x87");
177 UpdatedFeaturesVec.push_back(x: "-mmx");
178 UpdatedFeaturesVec.push_back(x: "-sse");
179 continue;
180 }
181
182 UpdatedFeaturesVec.push_back(x: Feature);
183 }
184
185 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec: UpdatedFeaturesVec))
186 return false;
187
188 // Can't do this earlier because we need to be able to explicitly enable
189 // or disable these features and the things that they depend upon.
190
191 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
192 auto I = Features.find(Key: "sse4.2");
193 if (I != Features.end() && I->getValue() &&
194 !llvm::is_contained(Range&: UpdatedFeaturesVec, Element: "-popcnt"))
195 Features["popcnt"] = true;
196
197 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
198 // then enable MMX.
199 I = Features.find(Key: "sse");
200 if (I != Features.end() && I->getValue() &&
201 !llvm::is_contained(Range&: UpdatedFeaturesVec, Element: "-mmx"))
202 Features["mmx"] = true;
203
204 // Enable xsave if avx is enabled and xsave is not explicitly disabled.
205 I = Features.find(Key: "avx");
206 if (I != Features.end() && I->getValue() &&
207 !llvm::is_contained(Range&: UpdatedFeaturesVec, Element: "-xsave"))
208 Features["xsave"] = true;
209
210 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
211 I = Features.find(Key: "sse4.2");
212 if (I != Features.end() && I->getValue() &&
213 !llvm::is_contained(Range&: UpdatedFeaturesVec, Element: "-crc32"))
214 Features["crc32"] = true;
215
216 return true;
217}
218
219void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
220 StringRef Name, bool Enabled) const {
221 if (Name == "sse4") {
222 // We can get here via the __target__ attribute since that's not controlled
223 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
224 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
225 // disabled.
226 if (Enabled)
227 Name = "sse4.2";
228 else
229 Name = "sse4.1";
230 }
231
232 Features[Name] = Enabled;
233 llvm::X86::updateImpliedFeatures(Feature: Name, Enabled, Features);
234}
235
236/// handleTargetFeatures - Perform initialization based on the user
237/// configured set of features.
238bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
239 DiagnosticsEngine &Diags) {
240 for (const auto &Feature : Features) {
241 if (Feature[0] != '+')
242 continue;
243
244 if (Feature == "+mmx") {
245 HasMMX = true;
246 } else if (Feature == "+aes") {
247 HasAES = true;
248 } else if (Feature == "+vaes") {
249 HasVAES = true;
250 } else if (Feature == "+pclmul") {
251 HasPCLMUL = true;
252 } else if (Feature == "+vpclmulqdq") {
253 HasVPCLMULQDQ = true;
254 } else if (Feature == "+lzcnt") {
255 HasLZCNT = true;
256 } else if (Feature == "+rdrnd") {
257 HasRDRND = true;
258 } else if (Feature == "+fsgsbase") {
259 HasFSGSBASE = true;
260 } else if (Feature == "+bmi") {
261 HasBMI = true;
262 } else if (Feature == "+bmi2") {
263 HasBMI2 = true;
264 } else if (Feature == "+popcnt") {
265 HasPOPCNT = true;
266 } else if (Feature == "+rtm") {
267 HasRTM = true;
268 } else if (Feature == "+prfchw") {
269 HasPRFCHW = true;
270 } else if (Feature == "+rdseed") {
271 HasRDSEED = true;
272 } else if (Feature == "+adx") {
273 HasADX = true;
274 } else if (Feature == "+tbm") {
275 HasTBM = true;
276 } else if (Feature == "+lwp") {
277 HasLWP = true;
278 } else if (Feature == "+fma") {
279 HasFMA = true;
280 } else if (Feature == "+f16c") {
281 HasF16C = true;
282 } else if (Feature == "+gfni") {
283 HasGFNI = true;
284 } else if (Feature == "+avx10.1") {
285 HasAVX10_1 = true;
286 } else if (Feature == "+avx10.2") {
287 HasAVX10_2 = true;
288 HasFullBFloat16 = true;
289 } else if (Feature == "+avx512cd") {
290 HasAVX512CD = true;
291 } else if (Feature == "+avx512vpopcntdq") {
292 HasAVX512VPOPCNTDQ = true;
293 } else if (Feature == "+avx512vnni") {
294 HasAVX512VNNI = true;
295 } else if (Feature == "+avx512bf16") {
296 HasAVX512BF16 = true;
297 } else if (Feature == "+avx512fp16") {
298 HasAVX512FP16 = true;
299 HasFastHalfType = true;
300 } else if (Feature == "+avx512dq") {
301 HasAVX512DQ = true;
302 } else if (Feature == "+avx512bitalg") {
303 HasAVX512BITALG = true;
304 } else if (Feature == "+avx512bw") {
305 HasAVX512BW = true;
306 } else if (Feature == "+avx512vl") {
307 HasAVX512VL = true;
308 } else if (Feature == "+avx512vbmi") {
309 HasAVX512VBMI = true;
310 } else if (Feature == "+avx512vbmi2") {
311 HasAVX512VBMI2 = true;
312 } else if (Feature == "+avx512ifma") {
313 HasAVX512IFMA = true;
314 } else if (Feature == "+avx512vp2intersect") {
315 HasAVX512VP2INTERSECT = true;
316 } else if (Feature == "+sha") {
317 HasSHA = true;
318 } else if (Feature == "+sha512") {
319 HasSHA512 = true;
320 } else if (Feature == "+shstk") {
321 HasSHSTK = true;
322 } else if (Feature == "+sm3") {
323 HasSM3 = true;
324 } else if (Feature == "+sm4") {
325 HasSM4 = true;
326 } else if (Feature == "+movbe") {
327 HasMOVBE = true;
328 } else if (Feature == "+movrs") {
329 HasMOVRS = true;
330 } else if (Feature == "+sgx") {
331 HasSGX = true;
332 } else if (Feature == "+cx8") {
333 HasCX8 = true;
334 } else if (Feature == "+cx16") {
335 HasCX16 = true;
336 } else if (Feature == "+fxsr") {
337 HasFXSR = true;
338 } else if (Feature == "+xsave") {
339 HasXSAVE = true;
340 } else if (Feature == "+xsaveopt") {
341 HasXSAVEOPT = true;
342 } else if (Feature == "+xsavec") {
343 HasXSAVEC = true;
344 } else if (Feature == "+xsaves") {
345 HasXSAVES = true;
346 } else if (Feature == "+mwaitx") {
347 HasMWAITX = true;
348 } else if (Feature == "+pku") {
349 HasPKU = true;
350 } else if (Feature == "+clflushopt") {
351 HasCLFLUSHOPT = true;
352 } else if (Feature == "+clwb") {
353 HasCLWB = true;
354 } else if (Feature == "+wbnoinvd") {
355 HasWBNOINVD = true;
356 } else if (Feature == "+prefetchi") {
357 HasPREFETCHI = true;
358 } else if (Feature == "+clzero") {
359 HasCLZERO = true;
360 } else if (Feature == "+cldemote") {
361 HasCLDEMOTE = true;
362 } else if (Feature == "+rdpid") {
363 HasRDPID = true;
364 } else if (Feature == "+rdpru") {
365 HasRDPRU = true;
366 } else if (Feature == "+kl") {
367 HasKL = true;
368 } else if (Feature == "+widekl") {
369 HasWIDEKL = true;
370 } else if (Feature == "+retpoline-external-thunk") {
371 HasRetpolineExternalThunk = true;
372 } else if (Feature == "+sahf") {
373 HasLAHFSAHF = true;
374 } else if (Feature == "+waitpkg") {
375 HasWAITPKG = true;
376 } else if (Feature == "+movdiri") {
377 HasMOVDIRI = true;
378 } else if (Feature == "+movdir64b") {
379 HasMOVDIR64B = true;
380 } else if (Feature == "+pconfig") {
381 HasPCONFIG = true;
382 } else if (Feature == "+ptwrite") {
383 HasPTWRITE = true;
384 } else if (Feature == "+invpcid") {
385 HasINVPCID = true;
386 } else if (Feature == "+enqcmd") {
387 HasENQCMD = true;
388 } else if (Feature == "+hreset") {
389 HasHRESET = true;
390 } else if (Feature == "+amx-bf16") {
391 HasAMXBF16 = true;
392 } else if (Feature == "+amx-fp16") {
393 HasAMXFP16 = true;
394 } else if (Feature == "+amx-int8") {
395 HasAMXINT8 = true;
396 } else if (Feature == "+amx-tile") {
397 HasAMXTILE = true;
398 } else if (Feature == "+amx-complex") {
399 HasAMXCOMPLEX = true;
400 } else if (Feature == "+amx-fp8") {
401 HasAMXFP8 = true;
402 } else if (Feature == "+amx-movrs") {
403 HasAMXMOVRS = true;
404 } else if (Feature == "+amx-avx512") {
405 HasAMXAVX512 = true;
406 } else if (Feature == "+amx-tf32") {
407 HasAMXTF32 = true;
408 } else if (Feature == "+cmpccxadd") {
409 HasCMPCCXADD = true;
410 } else if (Feature == "+raoint") {
411 HasRAOINT = true;
412 } else if (Feature == "+avxifma") {
413 HasAVXIFMA = true;
414 } else if (Feature == "+avxneconvert") {
415 HasAVXNECONVERT= true;
416 } else if (Feature == "+avxvnni") {
417 HasAVXVNNI = true;
418 } else if (Feature == "+avxvnniint16") {
419 HasAVXVNNIINT16 = true;
420 } else if (Feature == "+avxvnniint8") {
421 HasAVXVNNIINT8 = true;
422 } else if (Feature == "+serialize") {
423 HasSERIALIZE = true;
424 } else if (Feature == "+tsxldtrk") {
425 HasTSXLDTRK = true;
426 } else if (Feature == "+uintr") {
427 HasUINTR = true;
428 } else if (Feature == "+usermsr") {
429 HasUSERMSR = true;
430 } else if (Feature == "+crc32") {
431 HasCRC32 = true;
432 } else if (Feature == "+x87") {
433 HasX87 = true;
434 } else if (Feature == "+fullbf16") {
435 HasFullBFloat16 = true;
436 } else if (Feature == "+egpr") {
437 HasEGPR = true;
438 } else if (Feature == "+inline-asm-use-gpr32") {
439 HasInlineAsmUseGPR32 = true;
440 } else if (Feature == "+push2pop2") {
441 HasPush2Pop2 = true;
442 } else if (Feature == "+ppx") {
443 HasPPX = true;
444 } else if (Feature == "+ndd") {
445 HasNDD = true;
446 } else if (Feature == "+ccmp") {
447 HasCCMP = true;
448 } else if (Feature == "+nf") {
449 HasNF = true;
450 } else if (Feature == "+cf") {
451 HasCF = true;
452 } else if (Feature == "+zu") {
453 HasZU = true;
454 } else if (Feature == "+branch-hint") {
455 HasBranchHint = true;
456 }
457
458 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
459 .Case(S: "+avx512f", Value: AVX512F)
460 .Case(S: "+avx2", Value: AVX2)
461 .Case(S: "+avx", Value: AVX)
462 .Case(S: "+sse4.2", Value: SSE42)
463 .Case(S: "+sse4.1", Value: SSE41)
464 .Case(S: "+ssse3", Value: SSSE3)
465 .Case(S: "+sse3", Value: SSE3)
466 .Case(S: "+sse2", Value: SSE2)
467 .Case(S: "+sse", Value: SSE1)
468 .Default(Value: NoSSE);
469 SSELevel = std::max(a: SSELevel, b: Level);
470
471 HasFloat16 = SSELevel >= SSE2;
472
473 // X86 target has bfloat16 emulation support in the backend, where
474 // bfloat16 is treated as a 32-bit float, arithmetic operations are
475 // performed in 32-bit, and the result is converted back to bfloat16.
476 // Truncation and extension between bfloat16 and 32-bit float are supported
477 // by the compiler-rt library. However, native bfloat16 support is currently
478 // not available in the X86 target. Hence, HasFullBFloat16 will be false
479 // until native bfloat16 support is available. HasFullBFloat16 is used to
480 // determine whether to automatically use excess floating point precision
481 // for bfloat16 arithmetic operations in the front-end.
482 HasBFloat16 = SSELevel >= SSE2;
483
484 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
485 .Case(S: "+xop", Value: XOP)
486 .Case(S: "+fma4", Value: FMA4)
487 .Case(S: "+sse4a", Value: SSE4A)
488 .Default(Value: NoXOP);
489 XOPLevel = std::max(a: XOPLevel, b: XLevel);
490 }
491
492 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
493 // matches the selected sse level.
494 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
495 (FPMath == FP_387 && SSELevel >= SSE1)) {
496 Diags.Report(DiagID: diag::err_target_unsupported_fpmath)
497 << (FPMath == FP_SSE ? "sse" : "387");
498 return false;
499 }
500
501 // FIXME: We should allow long double type on 32-bits to match with GCC.
502 // This requires backend to be able to lower f80 without x87 first.
503 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
504 HasLongDouble = false;
505
506 return true;
507}
508
509/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
510/// definitions for this particular subtarget.
511void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
512 MacroBuilder &Builder) const {
513 // Inline assembly supports X86 flag outputs.
514 Builder.defineMacro(Name: "__GCC_ASM_FLAG_OUTPUTS__");
515
516 std::string CodeModel = getTargetOpts().CodeModel;
517 if (CodeModel == "default")
518 CodeModel = "small";
519 Builder.defineMacro(Name: "__code_model_" + CodeModel + "__");
520
521 // Target identification.
522 if (getTriple().getArch() == llvm::Triple::x86_64) {
523 Builder.defineMacro(Name: "__amd64__");
524 Builder.defineMacro(Name: "__amd64");
525 Builder.defineMacro(Name: "__x86_64");
526 Builder.defineMacro(Name: "__x86_64__");
527 if (getTriple().getArchName() == "x86_64h") {
528 Builder.defineMacro(Name: "__x86_64h");
529 Builder.defineMacro(Name: "__x86_64h__");
530 }
531 } else {
532 DefineStd(Builder, MacroName: "i386", Opts);
533 }
534
535 Builder.defineMacro(Name: "__SEG_GS");
536 Builder.defineMacro(Name: "__SEG_FS");
537 Builder.defineMacro(Name: "__seg_gs", Value: "__attribute__((address_space(256)))");
538 Builder.defineMacro(Name: "__seg_fs", Value: "__attribute__((address_space(257)))");
539
540 // Subtarget options.
541 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
542 // truly should be based on -mtune options.
543 using namespace llvm::X86;
544 switch (CPU) {
545 case CK_None:
546 break;
547 case CK_i386:
548 // The rest are coming from the i386 define above.
549 Builder.defineMacro(Name: "__tune_i386__");
550 break;
551 case CK_i486:
552 case CK_WinChipC6:
553 case CK_WinChip2:
554 case CK_C3:
555 defineCPUMacros(Builder, CPUName: "i486");
556 break;
557 case CK_PentiumMMX:
558 Builder.defineMacro(Name: "__pentium_mmx__");
559 Builder.defineMacro(Name: "__tune_pentium_mmx__");
560 [[fallthrough]];
561 case CK_i586:
562 case CK_Pentium:
563 defineCPUMacros(Builder, CPUName: "i586");
564 defineCPUMacros(Builder, CPUName: "pentium");
565 break;
566 case CK_Pentium3:
567 case CK_PentiumM:
568 Builder.defineMacro(Name: "__tune_pentium3__");
569 [[fallthrough]];
570 case CK_Pentium2:
571 case CK_C3_2:
572 Builder.defineMacro(Name: "__tune_pentium2__");
573 [[fallthrough]];
574 case CK_PentiumPro:
575 case CK_i686:
576 defineCPUMacros(Builder, CPUName: "i686");
577 defineCPUMacros(Builder, CPUName: "pentiumpro");
578 break;
579 case CK_Pentium4:
580 defineCPUMacros(Builder, CPUName: "pentium4");
581 break;
582 case CK_Yonah:
583 case CK_Prescott:
584 case CK_Nocona:
585 defineCPUMacros(Builder, CPUName: "nocona");
586 break;
587 case CK_Core2:
588 case CK_Penryn:
589 defineCPUMacros(Builder, CPUName: "core2");
590 break;
591 case CK_Bonnell:
592 defineCPUMacros(Builder, CPUName: "atom");
593 break;
594 case CK_Silvermont:
595 defineCPUMacros(Builder, CPUName: "slm");
596 break;
597 case CK_Goldmont:
598 defineCPUMacros(Builder, CPUName: "goldmont");
599 break;
600 case CK_GoldmontPlus:
601 defineCPUMacros(Builder, CPUName: "goldmont_plus");
602 break;
603 case CK_Tremont:
604 defineCPUMacros(Builder, CPUName: "tremont");
605 break;
606 // Gracemont and later atom-cores use P-core cpu macros.
607 case CK_Gracemont:
608 case CK_Nehalem:
609 case CK_Westmere:
610 case CK_SandyBridge:
611 case CK_IvyBridge:
612 case CK_Haswell:
613 case CK_Broadwell:
614 case CK_SkylakeClient:
615 case CK_SkylakeServer:
616 case CK_Cascadelake:
617 case CK_Cooperlake:
618 case CK_Cannonlake:
619 case CK_IcelakeClient:
620 case CK_Rocketlake:
621 case CK_IcelakeServer:
622 case CK_Tigerlake:
623 case CK_SapphireRapids:
624 case CK_Alderlake:
625 case CK_Raptorlake:
626 case CK_Meteorlake:
627 case CK_Arrowlake:
628 case CK_ArrowlakeS:
629 case CK_Lunarlake:
630 case CK_Pantherlake:
631 case CK_Wildcatlake:
632 case CK_Novalake:
633 case CK_Sierraforest:
634 case CK_Grandridge:
635 case CK_Graniterapids:
636 case CK_GraniterapidsD:
637 case CK_Emeraldrapids:
638 case CK_Clearwaterforest:
639 case CK_Diamondrapids:
640 // FIXME: Historically, we defined this legacy name, it would be nice to
641 // remove it at some point. We've never exposed fine-grained names for
642 // recent primary x86 CPUs, and we should keep it that way.
643 defineCPUMacros(Builder, CPUName: "corei7");
644 break;
645 case CK_KNL:
646 defineCPUMacros(Builder, CPUName: "knl");
647 break;
648 case CK_KNM:
649 break;
650 case CK_Lakemont:
651 defineCPUMacros(Builder, CPUName: "i586", /*Tuning*/false);
652 defineCPUMacros(Builder, CPUName: "pentium", /*Tuning*/false);
653 Builder.defineMacro(Name: "__tune_lakemont__");
654 break;
655 case CK_K6_2:
656 Builder.defineMacro(Name: "__k6_2__");
657 Builder.defineMacro(Name: "__tune_k6_2__");
658 [[fallthrough]];
659 case CK_K6_3:
660 if (CPU != CK_K6_2) { // In case of fallthrough
661 // FIXME: GCC may be enabling these in cases where some other k6
662 // architecture is specified but -m3dnow is explicitly provided. The
663 // exact semantics need to be determined and emulated here.
664 Builder.defineMacro(Name: "__k6_3__");
665 Builder.defineMacro(Name: "__tune_k6_3__");
666 }
667 [[fallthrough]];
668 case CK_K6:
669 defineCPUMacros(Builder, CPUName: "k6");
670 break;
671 case CK_Athlon:
672 case CK_AthlonXP:
673 defineCPUMacros(Builder, CPUName: "athlon");
674 if (SSELevel != NoSSE) {
675 Builder.defineMacro(Name: "__athlon_sse__");
676 Builder.defineMacro(Name: "__tune_athlon_sse__");
677 }
678 break;
679 case CK_K8:
680 case CK_K8SSE3:
681 case CK_x86_64:
682 defineCPUMacros(Builder, CPUName: "k8");
683 break;
684 case CK_x86_64_v2:
685 case CK_x86_64_v3:
686 case CK_x86_64_v4:
687 break;
688 case CK_AMDFAM10:
689 defineCPUMacros(Builder, CPUName: "amdfam10");
690 break;
691 case CK_BTVER1:
692 defineCPUMacros(Builder, CPUName: "btver1");
693 break;
694 case CK_BTVER2:
695 defineCPUMacros(Builder, CPUName: "btver2");
696 break;
697 case CK_BDVER1:
698 defineCPUMacros(Builder, CPUName: "bdver1");
699 break;
700 case CK_BDVER2:
701 defineCPUMacros(Builder, CPUName: "bdver2");
702 break;
703 case CK_BDVER3:
704 defineCPUMacros(Builder, CPUName: "bdver3");
705 break;
706 case CK_BDVER4:
707 defineCPUMacros(Builder, CPUName: "bdver4");
708 break;
709 case CK_ZNVER1:
710 defineCPUMacros(Builder, CPUName: "znver1");
711 break;
712 case CK_ZNVER2:
713 defineCPUMacros(Builder, CPUName: "znver2");
714 break;
715 case CK_ZNVER3:
716 defineCPUMacros(Builder, CPUName: "znver3");
717 break;
718 case CK_ZNVER4:
719 defineCPUMacros(Builder, CPUName: "znver4");
720 break;
721 case CK_ZNVER5:
722 defineCPUMacros(Builder, CPUName: "znver5");
723 break;
724 case CK_Geode:
725 defineCPUMacros(Builder, CPUName: "geode");
726 break;
727 }
728
729 // Target properties.
730 Builder.defineMacro(Name: "__REGISTER_PREFIX__", Value: "");
731
732 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
733 // functions in glibc header files that use FP Stack inline asm which the
734 // backend can't deal with (PR879).
735 Builder.defineMacro(Name: "__NO_MATH_INLINES");
736
737 if (HasAES)
738 Builder.defineMacro(Name: "__AES__");
739
740 if (HasVAES)
741 Builder.defineMacro(Name: "__VAES__");
742
743 if (HasPCLMUL)
744 Builder.defineMacro(Name: "__PCLMUL__");
745
746 if (HasVPCLMULQDQ)
747 Builder.defineMacro(Name: "__VPCLMULQDQ__");
748
749 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
750 // the feature flag only applies to 64-bit mode.
751 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
752 Builder.defineMacro(Name: "__LAHF_SAHF__");
753
754 if (HasLZCNT)
755 Builder.defineMacro(Name: "__LZCNT__");
756
757 if (HasRDRND)
758 Builder.defineMacro(Name: "__RDRND__");
759
760 if (HasFSGSBASE)
761 Builder.defineMacro(Name: "__FSGSBASE__");
762
763 if (HasBMI)
764 Builder.defineMacro(Name: "__BMI__");
765
766 if (HasBMI2)
767 Builder.defineMacro(Name: "__BMI2__");
768
769 if (HasPOPCNT)
770 Builder.defineMacro(Name: "__POPCNT__");
771
772 if (HasRTM)
773 Builder.defineMacro(Name: "__RTM__");
774
775 if (HasPRFCHW)
776 Builder.defineMacro(Name: "__PRFCHW__");
777
778 if (HasRDSEED)
779 Builder.defineMacro(Name: "__RDSEED__");
780
781 if (HasADX)
782 Builder.defineMacro(Name: "__ADX__");
783
784 if (HasTBM)
785 Builder.defineMacro(Name: "__TBM__");
786
787 if (HasLWP)
788 Builder.defineMacro(Name: "__LWP__");
789
790 if (HasMWAITX)
791 Builder.defineMacro(Name: "__MWAITX__");
792
793 if (HasMOVBE)
794 Builder.defineMacro(Name: "__MOVBE__");
795
796 switch (XOPLevel) {
797 case XOP:
798 Builder.defineMacro(Name: "__XOP__");
799 [[fallthrough]];
800 case FMA4:
801 Builder.defineMacro(Name: "__FMA4__");
802 [[fallthrough]];
803 case SSE4A:
804 Builder.defineMacro(Name: "__SSE4A__");
805 [[fallthrough]];
806 case NoXOP:
807 break;
808 }
809
810 if (HasFMA)
811 Builder.defineMacro(Name: "__FMA__");
812
813 if (HasF16C)
814 Builder.defineMacro(Name: "__F16C__");
815
816 if (HasGFNI)
817 Builder.defineMacro(Name: "__GFNI__");
818
819 if (HasAVX10_1) {
820 Builder.defineMacro(Name: "__AVX10_1__");
821 Builder.defineMacro(Name: "__AVX10_1_512__");
822 }
823 if (HasAVX10_2) {
824 Builder.defineMacro(Name: "__AVX10_2__");
825 Builder.defineMacro(Name: "__AVX10_2_512__");
826 }
827 if (HasAVX512CD)
828 Builder.defineMacro(Name: "__AVX512CD__");
829 if (HasAVX512VPOPCNTDQ)
830 Builder.defineMacro(Name: "__AVX512VPOPCNTDQ__");
831 if (HasAVX512VNNI)
832 Builder.defineMacro(Name: "__AVX512VNNI__");
833 if (HasAVX512BF16)
834 Builder.defineMacro(Name: "__AVX512BF16__");
835 if (HasAVX512FP16)
836 Builder.defineMacro(Name: "__AVX512FP16__");
837 if (HasAVX512DQ)
838 Builder.defineMacro(Name: "__AVX512DQ__");
839 if (HasAVX512BITALG)
840 Builder.defineMacro(Name: "__AVX512BITALG__");
841 if (HasAVX512BW)
842 Builder.defineMacro(Name: "__AVX512BW__");
843 if (HasAVX512VL) {
844 Builder.defineMacro(Name: "__AVX512VL__");
845 }
846 if (HasAVX512VBMI)
847 Builder.defineMacro(Name: "__AVX512VBMI__");
848 if (HasAVX512VBMI2)
849 Builder.defineMacro(Name: "__AVX512VBMI2__");
850 if (HasAVX512IFMA)
851 Builder.defineMacro(Name: "__AVX512IFMA__");
852 if (HasAVX512VP2INTERSECT)
853 Builder.defineMacro(Name: "__AVX512VP2INTERSECT__");
854 if (HasSHA)
855 Builder.defineMacro(Name: "__SHA__");
856 if (HasSHA512)
857 Builder.defineMacro(Name: "__SHA512__");
858
859 if (HasFXSR)
860 Builder.defineMacro(Name: "__FXSR__");
861 if (HasXSAVE)
862 Builder.defineMacro(Name: "__XSAVE__");
863 if (HasXSAVEOPT)
864 Builder.defineMacro(Name: "__XSAVEOPT__");
865 if (HasXSAVEC)
866 Builder.defineMacro(Name: "__XSAVEC__");
867 if (HasXSAVES)
868 Builder.defineMacro(Name: "__XSAVES__");
869 if (HasPKU)
870 Builder.defineMacro(Name: "__PKU__");
871 if (HasCLFLUSHOPT)
872 Builder.defineMacro(Name: "__CLFLUSHOPT__");
873 if (HasCLWB)
874 Builder.defineMacro(Name: "__CLWB__");
875 if (HasWBNOINVD)
876 Builder.defineMacro(Name: "__WBNOINVD__");
877 if (HasSHSTK)
878 Builder.defineMacro(Name: "__SHSTK__");
879 if (HasSGX)
880 Builder.defineMacro(Name: "__SGX__");
881 if (HasSM3)
882 Builder.defineMacro(Name: "__SM3__");
883 if (HasSM4)
884 Builder.defineMacro(Name: "__SM4__");
885 if (HasPREFETCHI)
886 Builder.defineMacro(Name: "__PREFETCHI__");
887 if (HasCLZERO)
888 Builder.defineMacro(Name: "__CLZERO__");
889 if (HasKL)
890 Builder.defineMacro(Name: "__KL__");
891 if (HasWIDEKL)
892 Builder.defineMacro(Name: "__WIDEKL__");
893 if (HasRDPID)
894 Builder.defineMacro(Name: "__RDPID__");
895 if (HasRDPRU)
896 Builder.defineMacro(Name: "__RDPRU__");
897 if (HasCLDEMOTE)
898 Builder.defineMacro(Name: "__CLDEMOTE__");
899 if (HasWAITPKG)
900 Builder.defineMacro(Name: "__WAITPKG__");
901 if (HasMOVDIRI)
902 Builder.defineMacro(Name: "__MOVDIRI__");
903 if (HasMOVDIR64B)
904 Builder.defineMacro(Name: "__MOVDIR64B__");
905 if (HasMOVRS)
906 Builder.defineMacro(Name: "__MOVRS__");
907 if (HasPCONFIG)
908 Builder.defineMacro(Name: "__PCONFIG__");
909 if (HasPTWRITE)
910 Builder.defineMacro(Name: "__PTWRITE__");
911 if (HasINVPCID)
912 Builder.defineMacro(Name: "__INVPCID__");
913 if (HasENQCMD)
914 Builder.defineMacro(Name: "__ENQCMD__");
915 if (HasHRESET)
916 Builder.defineMacro(Name: "__HRESET__");
917 if (HasAMXTILE)
918 Builder.defineMacro(Name: "__AMX_TILE__");
919 if (HasAMXINT8)
920 Builder.defineMacro(Name: "__AMX_INT8__");
921 if (HasAMXBF16)
922 Builder.defineMacro(Name: "__AMX_BF16__");
923 if (HasAMXFP16)
924 Builder.defineMacro(Name: "__AMX_FP16__");
925 if (HasAMXCOMPLEX)
926 Builder.defineMacro(Name: "__AMX_COMPLEX__");
927 if (HasAMXFP8)
928 Builder.defineMacro(Name: "__AMX_FP8__");
929 if (HasAMXMOVRS)
930 Builder.defineMacro(Name: "__AMX_MOVRS__");
931 if (HasAMXAVX512)
932 Builder.defineMacro(Name: "__AMX_AVX512__");
933 if (HasAMXTF32)
934 Builder.defineMacro(Name: "__AMX_TF32__");
935 if (HasCMPCCXADD)
936 Builder.defineMacro(Name: "__CMPCCXADD__");
937 if (HasRAOINT)
938 Builder.defineMacro(Name: "__RAOINT__");
939 if (HasAVXIFMA)
940 Builder.defineMacro(Name: "__AVXIFMA__");
941 if (HasAVXNECONVERT)
942 Builder.defineMacro(Name: "__AVXNECONVERT__");
943 if (HasAVXVNNI)
944 Builder.defineMacro(Name: "__AVXVNNI__");
945 if (HasAVXVNNIINT16)
946 Builder.defineMacro(Name: "__AVXVNNIINT16__");
947 if (HasAVXVNNIINT8)
948 Builder.defineMacro(Name: "__AVXVNNIINT8__");
949 if (HasSERIALIZE)
950 Builder.defineMacro(Name: "__SERIALIZE__");
951 if (HasTSXLDTRK)
952 Builder.defineMacro(Name: "__TSXLDTRK__");
953 if (HasUINTR)
954 Builder.defineMacro(Name: "__UINTR__");
955 if (HasUSERMSR)
956 Builder.defineMacro(Name: "__USERMSR__");
957 if (HasCRC32)
958 Builder.defineMacro(Name: "__CRC32__");
959 if (HasEGPR)
960 Builder.defineMacro(Name: "__EGPR__");
961 if (HasPush2Pop2)
962 Builder.defineMacro(Name: "__PUSH2POP2__");
963 if (HasPPX)
964 Builder.defineMacro(Name: "__PPX__");
965 if (HasNDD)
966 Builder.defineMacro(Name: "__NDD__");
967 if (HasCCMP)
968 Builder.defineMacro(Name: "__CCMP__");
969 if (HasNF)
970 Builder.defineMacro(Name: "__NF__");
971 if (HasCF)
972 Builder.defineMacro(Name: "__CF__");
973 if (HasZU)
974 Builder.defineMacro(Name: "__ZU__");
975 if (HasEGPR && HasNDD && HasCCMP && HasNF && HasZU)
976 if (getTriple().isOSWindows() || (HasPush2Pop2 && HasPPX))
977 Builder.defineMacro(Name: "__APX_F__");
978 if (HasEGPR && HasInlineAsmUseGPR32)
979 Builder.defineMacro(Name: "__APX_INLINE_ASM_USE_GPR32__");
980
981 // Each case falls through to the previous one here.
982 switch (SSELevel) {
983 case AVX512F:
984 Builder.defineMacro(Name: "__AVX512F__");
985 [[fallthrough]];
986 case AVX2:
987 Builder.defineMacro(Name: "__AVX2__");
988 [[fallthrough]];
989 case AVX:
990 Builder.defineMacro(Name: "__AVX__");
991 [[fallthrough]];
992 case SSE42:
993 Builder.defineMacro(Name: "__SSE4_2__");
994 [[fallthrough]];
995 case SSE41:
996 Builder.defineMacro(Name: "__SSE4_1__");
997 [[fallthrough]];
998 case SSSE3:
999 Builder.defineMacro(Name: "__SSSE3__");
1000 [[fallthrough]];
1001 case SSE3:
1002 Builder.defineMacro(Name: "__SSE3__");
1003 [[fallthrough]];
1004 case SSE2:
1005 Builder.defineMacro(Name: "__SSE2__");
1006 Builder.defineMacro(Name: "__SSE2_MATH__"); // -mfp-math=sse always implied.
1007 [[fallthrough]];
1008 case SSE1:
1009 Builder.defineMacro(Name: "__SSE__");
1010 Builder.defineMacro(Name: "__SSE_MATH__"); // -mfp-math=sse always implied.
1011 [[fallthrough]];
1012 case NoSSE:
1013 break;
1014 }
1015
1016 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1017 switch (SSELevel) {
1018 case AVX512F:
1019 case AVX2:
1020 case AVX:
1021 case SSE42:
1022 case SSE41:
1023 case SSSE3:
1024 case SSE3:
1025 case SSE2:
1026 Builder.defineMacro(Name: "_M_IX86_FP", Value: Twine(2));
1027 break;
1028 case SSE1:
1029 Builder.defineMacro(Name: "_M_IX86_FP", Value: Twine(1));
1030 break;
1031 default:
1032 Builder.defineMacro(Name: "_M_IX86_FP", Value: Twine(0));
1033 break;
1034 }
1035 }
1036
1037 // Each case falls through to the previous one here.
1038 if (HasMMX) {
1039 Builder.defineMacro(Name: "__MMX__");
1040 }
1041
1042 if (CPU >= CK_i486 || CPU == CK_None) {
1043 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1044 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1045 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1046 }
1047 if (HasCX8)
1048 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1049 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
1050 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1051
1052 if (HasFloat128)
1053 Builder.defineMacro(Name: "__SIZEOF_FLOAT128__", Value: "16");
1054
1055 if (Opts.CFProtectionReturn || Opts.CFProtectionBranch)
1056 Builder.defineMacro(Name: "__CET__", Value: Twine{(Opts.CFProtectionReturn << 1) |
1057 Opts.CFProtectionBranch});
1058}
1059
1060bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1061 return llvm::StringSwitch<bool>(Name)
1062 .Case(S: "adx", Value: true)
1063 .Case(S: "aes", Value: true)
1064 .Case(S: "amx-avx512", Value: true)
1065 .Case(S: "amx-bf16", Value: true)
1066 .Case(S: "amx-complex", Value: true)
1067 .Case(S: "amx-fp16", Value: true)
1068 .Case(S: "amx-fp8", Value: true)
1069 .Case(S: "amx-int8", Value: true)
1070 .Case(S: "amx-movrs", Value: true)
1071 .Case(S: "amx-tf32", Value: true)
1072 .Case(S: "amx-tile", Value: true)
1073 .Case(S: "avx", Value: true)
1074 .Case(S: "avx10.1", Value: true)
1075 .Case(S: "avx10.2", Value: true)
1076 .Case(S: "avx2", Value: true)
1077 .Case(S: "avx512f", Value: true)
1078 .Case(S: "avx512cd", Value: true)
1079 .Case(S: "avx512vpopcntdq", Value: true)
1080 .Case(S: "avx512vnni", Value: true)
1081 .Case(S: "avx512bf16", Value: true)
1082 .Case(S: "avx512fp16", Value: true)
1083 .Case(S: "avx512dq", Value: true)
1084 .Case(S: "avx512bitalg", Value: true)
1085 .Case(S: "avx512bw", Value: true)
1086 .Case(S: "avx512vl", Value: true)
1087 .Case(S: "avx512vbmi", Value: true)
1088 .Case(S: "avx512vbmi2", Value: true)
1089 .Case(S: "avx512ifma", Value: true)
1090 .Case(S: "avx512vp2intersect", Value: true)
1091 .Case(S: "avxifma", Value: true)
1092 .Case(S: "avxneconvert", Value: true)
1093 .Case(S: "avxvnni", Value: true)
1094 .Case(S: "avxvnniint16", Value: true)
1095 .Case(S: "avxvnniint8", Value: true)
1096 .Case(S: "bmi", Value: true)
1097 .Case(S: "bmi2", Value: true)
1098 .Case(S: "cldemote", Value: true)
1099 .Case(S: "clflushopt", Value: true)
1100 .Case(S: "clwb", Value: true)
1101 .Case(S: "clzero", Value: true)
1102 .Case(S: "cmpccxadd", Value: true)
1103 .Case(S: "crc32", Value: true)
1104 .Case(S: "cx16", Value: true)
1105 .Case(S: "enqcmd", Value: true)
1106 .Case(S: "f16c", Value: true)
1107 .Case(S: "fma", Value: true)
1108 .Case(S: "fma4", Value: true)
1109 .Case(S: "fsgsbase", Value: true)
1110 .Case(S: "fxsr", Value: true)
1111 .Case(S: "general-regs-only", Value: true)
1112 .Case(S: "gfni", Value: true)
1113 .Case(S: "hreset", Value: true)
1114 .Case(S: "invpcid", Value: true)
1115 .Case(S: "kl", Value: true)
1116 .Case(S: "widekl", Value: true)
1117 .Case(S: "lwp", Value: true)
1118 .Case(S: "lzcnt", Value: true)
1119 .Case(S: "mmx", Value: true)
1120 .Case(S: "movbe", Value: true)
1121 .Case(S: "movrs", Value: true)
1122 .Case(S: "movdiri", Value: true)
1123 .Case(S: "movdir64b", Value: true)
1124 .Case(S: "mwaitx", Value: true)
1125 .Case(S: "pclmul", Value: true)
1126 .Case(S: "pconfig", Value: true)
1127 .Case(S: "pku", Value: true)
1128 .Case(S: "popcnt", Value: true)
1129 .Case(S: "prefer-256-bit", Value: true)
1130 .Case(S: "prefetchi", Value: true)
1131 .Case(S: "prfchw", Value: true)
1132 .Case(S: "ptwrite", Value: true)
1133 .Case(S: "raoint", Value: true)
1134 .Case(S: "rdpid", Value: true)
1135 .Case(S: "rdpru", Value: true)
1136 .Case(S: "rdrnd", Value: true)
1137 .Case(S: "rdseed", Value: true)
1138 .Case(S: "rtm", Value: true)
1139 .Case(S: "sahf", Value: true)
1140 .Case(S: "serialize", Value: true)
1141 .Case(S: "sgx", Value: true)
1142 .Case(S: "sha", Value: true)
1143 .Case(S: "sha512", Value: true)
1144 .Case(S: "shstk", Value: true)
1145 .Case(S: "sm3", Value: true)
1146 .Case(S: "sm4", Value: true)
1147 .Case(S: "sse", Value: true)
1148 .Case(S: "sse2", Value: true)
1149 .Case(S: "sse3", Value: true)
1150 .Case(S: "ssse3", Value: true)
1151 .Case(S: "sse4", Value: true)
1152 .Case(S: "sse4.1", Value: true)
1153 .Case(S: "sse4.2", Value: true)
1154 .Case(S: "sse4a", Value: true)
1155 .Case(S: "tbm", Value: true)
1156 .Case(S: "tsxldtrk", Value: true)
1157 .Case(S: "uintr", Value: true)
1158 .Case(S: "usermsr", Value: true)
1159 .Case(S: "vaes", Value: true)
1160 .Case(S: "vpclmulqdq", Value: true)
1161 .Case(S: "wbnoinvd", Value: true)
1162 .Case(S: "waitpkg", Value: true)
1163 .Case(S: "x87", Value: true)
1164 .Case(S: "xop", Value: true)
1165 .Case(S: "xsave", Value: true)
1166 .Case(S: "xsavec", Value: true)
1167 .Case(S: "xsaves", Value: true)
1168 .Case(S: "xsaveopt", Value: true)
1169 .Case(S: "egpr", Value: true)
1170 .Case(S: "push2pop2", Value: true)
1171 .Case(S: "ppx", Value: true)
1172 .Case(S: "ndd", Value: true)
1173 .Case(S: "ccmp", Value: true)
1174 .Case(S: "nf", Value: true)
1175 .Case(S: "cf", Value: true)
1176 .Case(S: "zu", Value: true)
1177 .Default(Value: false);
1178}
1179
1180bool X86TargetInfo::hasFeature(StringRef Feature) const {
1181 return llvm::StringSwitch<bool>(Feature)
1182 .Case(S: "adx", Value: HasADX)
1183 .Case(S: "aes", Value: HasAES)
1184 .Case(S: "amx-avx512", Value: HasAMXAVX512)
1185 .Case(S: "amx-bf16", Value: HasAMXBF16)
1186 .Case(S: "amx-complex", Value: HasAMXCOMPLEX)
1187 .Case(S: "amx-fp16", Value: HasAMXFP16)
1188 .Case(S: "amx-fp8", Value: HasAMXFP8)
1189 .Case(S: "amx-int8", Value: HasAMXINT8)
1190 .Case(S: "amx-movrs", Value: HasAMXMOVRS)
1191 .Case(S: "amx-tf32", Value: HasAMXTF32)
1192 .Case(S: "amx-tile", Value: HasAMXTILE)
1193 .Case(S: "avx", Value: SSELevel >= AVX)
1194 .Case(S: "avx10.1", Value: HasAVX10_1)
1195 .Case(S: "avx10.2", Value: HasAVX10_2)
1196 .Case(S: "avx2", Value: SSELevel >= AVX2)
1197 .Case(S: "avx512f", Value: SSELevel >= AVX512F)
1198 .Case(S: "avx512cd", Value: HasAVX512CD)
1199 .Case(S: "avx512vpopcntdq", Value: HasAVX512VPOPCNTDQ)
1200 .Case(S: "avx512vnni", Value: HasAVX512VNNI)
1201 .Case(S: "avx512bf16", Value: HasAVX512BF16)
1202 .Case(S: "avx512fp16", Value: HasAVX512FP16)
1203 .Case(S: "avx512dq", Value: HasAVX512DQ)
1204 .Case(S: "avx512bitalg", Value: HasAVX512BITALG)
1205 .Case(S: "avx512bw", Value: HasAVX512BW)
1206 .Case(S: "avx512vl", Value: HasAVX512VL)
1207 .Case(S: "avx512vbmi", Value: HasAVX512VBMI)
1208 .Case(S: "avx512vbmi2", Value: HasAVX512VBMI2)
1209 .Case(S: "avx512ifma", Value: HasAVX512IFMA)
1210 .Case(S: "avx512vp2intersect", Value: HasAVX512VP2INTERSECT)
1211 .Case(S: "avxifma", Value: HasAVXIFMA)
1212 .Case(S: "avxneconvert", Value: HasAVXNECONVERT)
1213 .Case(S: "avxvnni", Value: HasAVXVNNI)
1214 .Case(S: "avxvnniint16", Value: HasAVXVNNIINT16)
1215 .Case(S: "avxvnniint8", Value: HasAVXVNNIINT8)
1216 .Case(S: "bmi", Value: HasBMI)
1217 .Case(S: "bmi2", Value: HasBMI2)
1218 .Case(S: "cldemote", Value: HasCLDEMOTE)
1219 .Case(S: "clflushopt", Value: HasCLFLUSHOPT)
1220 .Case(S: "clwb", Value: HasCLWB)
1221 .Case(S: "clzero", Value: HasCLZERO)
1222 .Case(S: "cmpccxadd", Value: HasCMPCCXADD)
1223 .Case(S: "crc32", Value: HasCRC32)
1224 .Case(S: "cx8", Value: HasCX8)
1225 .Case(S: "cx16", Value: HasCX16)
1226 .Case(S: "enqcmd", Value: HasENQCMD)
1227 .Case(S: "f16c", Value: HasF16C)
1228 .Case(S: "fma", Value: HasFMA)
1229 .Case(S: "fma4", Value: XOPLevel >= FMA4)
1230 .Case(S: "fsgsbase", Value: HasFSGSBASE)
1231 .Case(S: "fxsr", Value: HasFXSR)
1232 .Case(S: "gfni", Value: HasGFNI)
1233 .Case(S: "hreset", Value: HasHRESET)
1234 .Case(S: "invpcid", Value: HasINVPCID)
1235 .Case(S: "kl", Value: HasKL)
1236 .Case(S: "widekl", Value: HasWIDEKL)
1237 .Case(S: "lwp", Value: HasLWP)
1238 .Case(S: "lzcnt", Value: HasLZCNT)
1239 .Case(S: "mmx", Value: HasMMX)
1240 .Case(S: "movbe", Value: HasMOVBE)
1241 .Case(S: "movrs", Value: HasMOVRS)
1242 .Case(S: "movdiri", Value: HasMOVDIRI)
1243 .Case(S: "movdir64b", Value: HasMOVDIR64B)
1244 .Case(S: "mwaitx", Value: HasMWAITX)
1245 .Case(S: "pclmul", Value: HasPCLMUL)
1246 .Case(S: "pconfig", Value: HasPCONFIG)
1247 .Case(S: "pku", Value: HasPKU)
1248 .Case(S: "popcnt", Value: HasPOPCNT)
1249 .Case(S: "prefetchi", Value: HasPREFETCHI)
1250 .Case(S: "prfchw", Value: HasPRFCHW)
1251 .Case(S: "ptwrite", Value: HasPTWRITE)
1252 .Case(S: "raoint", Value: HasRAOINT)
1253 .Case(S: "rdpid", Value: HasRDPID)
1254 .Case(S: "rdpru", Value: HasRDPRU)
1255 .Case(S: "rdrnd", Value: HasRDRND)
1256 .Case(S: "rdseed", Value: HasRDSEED)
1257 .Case(S: "retpoline-external-thunk", Value: HasRetpolineExternalThunk)
1258 .Case(S: "rtm", Value: HasRTM)
1259 .Case(S: "sahf", Value: HasLAHFSAHF)
1260 .Case(S: "serialize", Value: HasSERIALIZE)
1261 .Case(S: "sgx", Value: HasSGX)
1262 .Case(S: "sha", Value: HasSHA)
1263 .Case(S: "sha512", Value: HasSHA512)
1264 .Case(S: "shstk", Value: HasSHSTK)
1265 .Case(S: "sm3", Value: HasSM3)
1266 .Case(S: "sm4", Value: HasSM4)
1267 .Case(S: "sse", Value: SSELevel >= SSE1)
1268 .Case(S: "sse2", Value: SSELevel >= SSE2)
1269 .Case(S: "sse3", Value: SSELevel >= SSE3)
1270 .Case(S: "ssse3", Value: SSELevel >= SSSE3)
1271 .Case(S: "sse4.1", Value: SSELevel >= SSE41)
1272 .Case(S: "sse4.2", Value: SSELevel >= SSE42)
1273 .Case(S: "sse4a", Value: XOPLevel >= SSE4A)
1274 .Case(S: "tbm", Value: HasTBM)
1275 .Case(S: "tsxldtrk", Value: HasTSXLDTRK)
1276 .Case(S: "uintr", Value: HasUINTR)
1277 .Case(S: "usermsr", Value: HasUSERMSR)
1278 .Case(S: "vaes", Value: HasVAES)
1279 .Case(S: "vpclmulqdq", Value: HasVPCLMULQDQ)
1280 .Case(S: "wbnoinvd", Value: HasWBNOINVD)
1281 .Case(S: "waitpkg", Value: HasWAITPKG)
1282 .Case(S: "x86", Value: true)
1283 .Case(S: "x86_32", Value: getTriple().getArch() == llvm::Triple::x86)
1284 .Case(S: "x86_64", Value: getTriple().getArch() == llvm::Triple::x86_64)
1285 .Case(S: "x87", Value: HasX87)
1286 .Case(S: "xop", Value: XOPLevel >= XOP)
1287 .Case(S: "xsave", Value: HasXSAVE)
1288 .Case(S: "xsavec", Value: HasXSAVEC)
1289 .Case(S: "xsaves", Value: HasXSAVES)
1290 .Case(S: "xsaveopt", Value: HasXSAVEOPT)
1291 .Case(S: "fullbf16", Value: HasFullBFloat16)
1292 .Case(S: "egpr", Value: HasEGPR)
1293 .Case(S: "push2pop2", Value: HasPush2Pop2)
1294 .Case(S: "ppx", Value: HasPPX)
1295 .Case(S: "ndd", Value: HasNDD)
1296 .Case(S: "ccmp", Value: HasCCMP)
1297 .Case(S: "nf", Value: HasNF)
1298 .Case(S: "cf", Value: HasCF)
1299 .Case(S: "zu", Value: HasZU)
1300 .Case(S: "branch-hint", Value: HasBranchHint)
1301 .Default(Value: false);
1302}
1303
1304// We can't use a generic validation scheme for the features accepted here
1305// versus subtarget features accepted in the target attribute because the
1306// bitfield structure that's initialized in the runtime only supports the
1307// below currently rather than the full range of subtarget features. (See
1308// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1309bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1310 return llvm::StringSwitch<bool>(FeatureStr)
1311#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1312#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1313#include "llvm/TargetParser/X86TargetParser.def"
1314 .Default(Value: false);
1315}
1316
1317static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1318 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1319#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) \
1320 .Case(STR, llvm::X86::FEATURE_##ENUM)
1321
1322#include "llvm/TargetParser/X86TargetParser.def"
1323 ;
1324 // Note, this function should only be used after ensuring the value is
1325 // correct, so it asserts if the value is out of range.
1326}
1327
1328llvm::APInt X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
1329 auto getPriority = [](StringRef Feature) -> unsigned {
1330 // Valid CPUs have a 'key feature' that compares just better than its key
1331 // feature.
1332 using namespace llvm::X86;
1333 CPUKind Kind = parseArchX86(CPU: Feature);
1334 if (Kind != CK_None) {
1335 ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1336 return (getFeaturePriority(Feat: KeyFeature) << 1) + 1;
1337 }
1338 // Now we know we have a feature, so get its priority and shift it a few so
1339 // that we have sufficient room for the CPUs (above).
1340 return getFeaturePriority(Feat: getFeature(Name: Feature)) << 1;
1341 };
1342
1343 unsigned Priority = 0;
1344 for (StringRef Feature : Features)
1345 if (!Feature.empty())
1346 Priority = std::max(a: Priority, b: getPriority(Feature));
1347 return llvm::APInt(32, Priority);
1348}
1349
1350bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1351 return llvm::X86::validateCPUSpecificCPUDispatch(Name);
1352}
1353
1354char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1355 return llvm::X86::getCPUDispatchMangling(Name);
1356}
1357
1358void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1359 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1360 SmallVector<StringRef, 32> TargetCPUFeatures;
1361 llvm::X86::getFeaturesForCPU(CPU: Name, Features&: TargetCPUFeatures, NeedPlus: true);
1362 for (auto &F : TargetCPUFeatures)
1363 Features.push_back(Elt: F);
1364}
1365
1366// We can't use a generic validation scheme for the cpus accepted here
1367// versus subtarget cpus accepted in the target attribute because the
1368// variables intitialized by the runtime only support the below currently
1369// rather than the full range of cpus.
1370bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1371 return llvm::StringSwitch<bool>(FeatureStr)
1372#define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1373#define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1374#define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1375#define X86_CPU_SUBTYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1376#define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1377#include "llvm/TargetParser/X86TargetParser.def"
1378 .Default(Value: false);
1379}
1380
1381static unsigned matchAsmCCConstraint(const char *Name) {
1382 auto RV = llvm::StringSwitch<unsigned>(Name)
1383 .Case(S: "@cca", Value: 4)
1384 .Case(S: "@ccae", Value: 5)
1385 .Case(S: "@ccb", Value: 4)
1386 .Case(S: "@ccbe", Value: 5)
1387 .Case(S: "@ccc", Value: 4)
1388 .Case(S: "@cce", Value: 4)
1389 .Case(S: "@ccz", Value: 4)
1390 .Case(S: "@ccg", Value: 4)
1391 .Case(S: "@ccge", Value: 5)
1392 .Case(S: "@ccl", Value: 4)
1393 .Case(S: "@ccle", Value: 5)
1394 .Case(S: "@ccna", Value: 5)
1395 .Case(S: "@ccnae", Value: 6)
1396 .Case(S: "@ccnb", Value: 5)
1397 .Case(S: "@ccnbe", Value: 6)
1398 .Case(S: "@ccnc", Value: 5)
1399 .Case(S: "@ccne", Value: 5)
1400 .Case(S: "@ccnz", Value: 5)
1401 .Case(S: "@ccng", Value: 5)
1402 .Case(S: "@ccnge", Value: 6)
1403 .Case(S: "@ccnl", Value: 5)
1404 .Case(S: "@ccnle", Value: 6)
1405 .Case(S: "@ccno", Value: 5)
1406 .Case(S: "@ccnp", Value: 5)
1407 .Case(S: "@ccns", Value: 5)
1408 .Case(S: "@cco", Value: 4)
1409 .Case(S: "@ccp", Value: 4)
1410 .Case(S: "@ccs", Value: 4)
1411 .Default(Value: 0);
1412 return RV;
1413}
1414
1415bool X86TargetInfo::validateAsmConstraint(
1416 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1417 switch (*Name) {
1418 default:
1419 return false;
1420 // Constant constraints.
1421 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1422 // instructions.
1423 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1424 // x86_64 instructions.
1425 case 's':
1426 Info.setRequiresImmediate();
1427 return true;
1428 case 'I':
1429 Info.setRequiresImmediate(Min: 0, Max: 31);
1430 return true;
1431 case 'J':
1432 Info.setRequiresImmediate(Min: 0, Max: 63);
1433 return true;
1434 case 'K':
1435 Info.setRequiresImmediate(Min: -128, Max: 127);
1436 return true;
1437 case 'L':
1438 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1439 return true;
1440 case 'M':
1441 Info.setRequiresImmediate(Min: 0, Max: 3);
1442 return true;
1443 case 'N':
1444 Info.setRequiresImmediate(Min: 0, Max: 255);
1445 return true;
1446 case 'O':
1447 Info.setRequiresImmediate(Min: 0, Max: 127);
1448 return true;
1449 case 'W':
1450 switch (*++Name) {
1451 default:
1452 return false;
1453 case 's':
1454 Info.setAllowsRegister();
1455 return true;
1456 }
1457 // Register constraints.
1458 case 'Y': // 'Y' is the first character for several 2-character constraints.
1459 // Shift the pointer to the second character of the constraint.
1460 Name++;
1461 switch (*Name) {
1462 default:
1463 return false;
1464 case 'z': // First SSE register.
1465 case '2':
1466 case 't': // Any SSE register, when SSE2 is enabled.
1467 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1468 case 'm': // Any MMX register, when inter-unit moves enabled.
1469 case 'k': // AVX512 arch mask registers: k1-k7.
1470 Info.setAllowsRegister();
1471 return true;
1472 }
1473 case 'f': // Any x87 floating point stack register.
1474 // Constraint 'f' cannot be used for output operands.
1475 if (Info.ConstraintStr[0] == '=' || Info.ConstraintStr[0] == '+')
1476 return false;
1477 Info.setAllowsRegister();
1478 return true;
1479 case 'a': // eax.
1480 case 'b': // ebx.
1481 case 'c': // ecx.
1482 case 'd': // edx.
1483 case 'S': // esi.
1484 case 'D': // edi.
1485 case 'A': // edx:eax.
1486 case 't': // Top of floating point stack.
1487 case 'u': // Second from top of floating point stack.
1488 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1489 case 'y': // Any MMX register.
1490 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1491 case 'x': // Any SSE register.
1492 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1493 // for intermideate k reg operations).
1494 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1495 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1496 case 'l': // "Index" registers: any general register that can be used as an
1497 // index in a base+index memory access.
1498 Info.setAllowsRegister();
1499 return true;
1500 // Floating point constant constraints.
1501 case 'C': // SSE floating point constant.
1502 case 'G': // x87 floating point constant.
1503 return true;
1504 case 'j':
1505 Name++;
1506 switch (*Name) {
1507 default:
1508 return false;
1509 case 'r':
1510 Info.setAllowsRegister();
1511 return true;
1512 case 'R':
1513 Info.setAllowsRegister();
1514 return true;
1515 }
1516 case '@':
1517 // CC condition changes.
1518 if (auto Len = matchAsmCCConstraint(Name)) {
1519 Name += Len - 1;
1520 Info.setAllowsRegister();
1521 Info.setOutputOperandBounds(Min: 0, Max: 2);
1522 return true;
1523 }
1524 return false;
1525 }
1526}
1527
1528// Below is based on the following information:
1529// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1530// | Processor Name | Cache Line Size (Bytes) | Source |
1531// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1532// | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1533// | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1534// | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1535// | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1536// | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1537// | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1538// | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1539// | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1540// | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1541// | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1542// | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1543// | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1544// | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1545// | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1546// | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1547// | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1548// | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1549// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1550std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1551 using namespace llvm::X86;
1552 switch (CPU) {
1553 // i386
1554 case CK_i386:
1555 // i486
1556 case CK_i486:
1557 case CK_WinChipC6:
1558 case CK_WinChip2:
1559 case CK_C3:
1560 // Lakemont
1561 case CK_Lakemont:
1562 return 16;
1563
1564 // i586
1565 case CK_i586:
1566 case CK_Pentium:
1567 case CK_PentiumMMX:
1568 // i686
1569 case CK_PentiumPro:
1570 case CK_i686:
1571 case CK_Pentium2:
1572 case CK_Pentium3:
1573 case CK_PentiumM:
1574 case CK_C3_2:
1575 // K6
1576 case CK_K6:
1577 case CK_K6_2:
1578 case CK_K6_3:
1579 // Geode
1580 case CK_Geode:
1581 return 32;
1582
1583 // Netburst
1584 case CK_Pentium4:
1585 case CK_Prescott:
1586 case CK_Nocona:
1587 // Atom
1588 case CK_Bonnell:
1589 case CK_Silvermont:
1590 case CK_Goldmont:
1591 case CK_GoldmontPlus:
1592 case CK_Tremont:
1593 case CK_Gracemont:
1594
1595 case CK_Westmere:
1596 case CK_SandyBridge:
1597 case CK_IvyBridge:
1598 case CK_Haswell:
1599 case CK_Broadwell:
1600 case CK_SkylakeClient:
1601 case CK_SkylakeServer:
1602 case CK_Cascadelake:
1603 case CK_Nehalem:
1604 case CK_Cooperlake:
1605 case CK_Cannonlake:
1606 case CK_Tigerlake:
1607 case CK_SapphireRapids:
1608 case CK_IcelakeClient:
1609 case CK_Rocketlake:
1610 case CK_IcelakeServer:
1611 case CK_Alderlake:
1612 case CK_Raptorlake:
1613 case CK_Meteorlake:
1614 case CK_Arrowlake:
1615 case CK_ArrowlakeS:
1616 case CK_Lunarlake:
1617 case CK_Pantherlake:
1618 case CK_Wildcatlake:
1619 case CK_Novalake:
1620 case CK_Sierraforest:
1621 case CK_Grandridge:
1622 case CK_Graniterapids:
1623 case CK_GraniterapidsD:
1624 case CK_Emeraldrapids:
1625 case CK_Clearwaterforest:
1626 case CK_Diamondrapids:
1627 case CK_KNL:
1628 case CK_KNM:
1629 // K7
1630 case CK_Athlon:
1631 case CK_AthlonXP:
1632 // K8
1633 case CK_K8:
1634 case CK_K8SSE3:
1635 case CK_AMDFAM10:
1636 // Bobcat
1637 case CK_BTVER1:
1638 case CK_BTVER2:
1639 // Bulldozer
1640 case CK_BDVER1:
1641 case CK_BDVER2:
1642 case CK_BDVER3:
1643 case CK_BDVER4:
1644 // Zen
1645 case CK_ZNVER1:
1646 case CK_ZNVER2:
1647 case CK_ZNVER3:
1648 case CK_ZNVER4:
1649 case CK_ZNVER5:
1650 // Deprecated
1651 case CK_x86_64:
1652 case CK_x86_64_v2:
1653 case CK_x86_64_v3:
1654 case CK_x86_64_v4:
1655 case CK_Yonah:
1656 case CK_Penryn:
1657 case CK_Core2:
1658 return 64;
1659
1660 // The following currently have unknown cache line sizes (but they are probably all 64):
1661 // Core
1662 case CK_None:
1663 return std::nullopt;
1664 }
1665 llvm_unreachable("Unknown CPU kind");
1666}
1667
1668bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1669 StringRef Constraint,
1670 unsigned Size) const {
1671 // Strip off constraint modifiers.
1672 Constraint = Constraint.ltrim(Chars: "=+&");
1673
1674 return validateOperandSize(FeatureMap, Constraint, Size);
1675}
1676
1677bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1678 StringRef Constraint,
1679 unsigned Size) const {
1680 return validateOperandSize(FeatureMap, Constraint, Size);
1681}
1682
1683bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1684 StringRef Constraint,
1685 unsigned Size) const {
1686 switch (Constraint[0]) {
1687 default:
1688 break;
1689 case 'k':
1690 // Registers k0-k7 (AVX512) size limit is 64 bit.
1691 case 'y':
1692 return Size <= 64;
1693 case 'f':
1694 case 't':
1695 case 'u':
1696 return Size <= 128;
1697 case 'Y':
1698 // 'Y' is the first character for several 2-character constraints.
1699 switch (Constraint[1]) {
1700 default:
1701 return false;
1702 case 'm':
1703 // 'Ym' is synonymous with 'y'.
1704 case 'k':
1705 return Size <= 64;
1706 case 'z':
1707 // XMM0/YMM/ZMM0
1708 if (hasFeatureEnabled(Features: FeatureMap, Name: "avx512f"))
1709 // ZMM0 can be used if target supports AVX512F.
1710 return Size <= 512U;
1711 else if (hasFeatureEnabled(Features: FeatureMap, Name: "avx"))
1712 // YMM0 can be used if target supports AVX.
1713 return Size <= 256U;
1714 else if (hasFeatureEnabled(Features: FeatureMap, Name: "sse"))
1715 return Size <= 128U;
1716 return false;
1717 case 'i':
1718 case 't':
1719 case '2':
1720 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1721 if (SSELevel < SSE2)
1722 return false;
1723 break;
1724 }
1725 break;
1726 case 'v':
1727 case 'x':
1728 if (hasFeatureEnabled(Features: FeatureMap, Name: "avx512f"))
1729 // 512-bit zmm registers can be used if target supports AVX512F.
1730 return Size <= 512U;
1731 else if (hasFeatureEnabled(Features: FeatureMap, Name: "avx"))
1732 // 256-bit ymm registers can be used if target supports AVX.
1733 return Size <= 256U;
1734 return Size <= 128U;
1735
1736 }
1737
1738 return true;
1739}
1740
1741std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1742 switch (*Constraint) {
1743 case '@':
1744 if (auto Len = matchAsmCCConstraint(Name: Constraint)) {
1745 std::string Converted = "{" + std::string(Constraint, Len) + "}";
1746 Constraint += Len - 1;
1747 return Converted;
1748 }
1749 return std::string(1, *Constraint);
1750 case 'a':
1751 return std::string("{ax}");
1752 case 'b':
1753 return std::string("{bx}");
1754 case 'c':
1755 return std::string("{cx}");
1756 case 'd':
1757 return std::string("{dx}");
1758 case 'S':
1759 return std::string("{si}");
1760 case 'D':
1761 return std::string("{di}");
1762 case 'p': // Keep 'p' constraint (address).
1763 return std::string("p");
1764 case 't': // top of floating point stack.
1765 return std::string("{st}");
1766 case 'u': // second from top of floating point stack.
1767 return std::string("{st(1)}"); // second from top of floating point stack.
1768 case 'W':
1769 assert(Constraint[1] == 's');
1770 return '^' + std::string(Constraint++, 2);
1771 case 'Y':
1772 switch (Constraint[1]) {
1773 default:
1774 // Break from inner switch and fall through (copy single char),
1775 // continue parsing after copying the current constraint into
1776 // the return string.
1777 break;
1778 case 'k':
1779 case 'm':
1780 case 'i':
1781 case 't':
1782 case 'z':
1783 case '2':
1784 // "^" hints llvm that this is a 2 letter constraint.
1785 // "Constraint++" is used to promote the string iterator
1786 // to the next constraint.
1787 return std::string("^") + std::string(Constraint++, 2);
1788 }
1789 [[fallthrough]];
1790 case 'j':
1791 switch (Constraint[1]) {
1792 default:
1793 // Break from inner switch and fall through (copy single char),
1794 // continue parsing after copying the current constraint into
1795 // the return string.
1796 break;
1797 case 'r':
1798 case 'R':
1799 // "^" hints llvm that this is a 2 letter constraint.
1800 // "Constraint++" is used to promote the string iterator
1801 // to the next constraint.
1802 return std::string("^") + std::string(Constraint++, 2);
1803 }
1804 [[fallthrough]];
1805 default:
1806 return std::string(1, *Constraint);
1807 }
1808}
1809
1810void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1811 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1812 llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1813}
1814
1815void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1816 llvm::X86::fillValidTuneCPUList(Values);
1817}
1818
1819ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1820 return llvm::ArrayRef(GCCRegNames);
1821}
1822
1823ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1824 return llvm::ArrayRef(AddlRegNames);
1825}
1826
1827llvm::SmallVector<Builtin::InfosShard>
1828X86_32TargetInfo::getTargetBuiltins() const {
1829 return {
1830 {.Strings: &X86::BuiltinStrings, .Infos: X86::BuiltinInfos},
1831 {.Strings: &X86::BuiltinStrings, .Infos: X86::PrefixedBuiltinInfos, .NamePrefix: "__builtin_ia32_"},
1832 };
1833}
1834
1835llvm::SmallVector<Builtin::InfosShard>
1836X86_64TargetInfo::getTargetBuiltins() const {
1837 return {
1838 {.Strings: &X86::BuiltinStrings, .Infos: X86::BuiltinInfos},
1839 {.Strings: &X86::BuiltinStrings, .Infos: X86::PrefixedBuiltinInfos, .NamePrefix: "__builtin_ia32_"},
1840 {.Strings: &X86_64::BuiltinStrings, .Infos: X86_64::BuiltinInfos},
1841 {.Strings: &X86_64::BuiltinStrings, .Infos: X86_64::PrefixedBuiltinInfos,
1842 .NamePrefix: "__builtin_ia32_"},
1843 };
1844}
1845