1//===--- X86.cpp - Implement X86 target feature support -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements X86 TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86.h"
14#include "clang/Basic/Builtins.h"
15#include "clang/Basic/Diagnostic.h"
16#include "clang/Basic/TargetBuiltins.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/StringSwitch.h"
19#include "llvm/TargetParser/X86TargetParser.h"
20#include <optional>
21
22namespace clang {
23namespace targets {
24
25// The x86-32 builtins are a subset and prefix of the x86-64 builtins.
26static constexpr int NumX86Builtins =
27 X86::LastX86CommonBuiltin - Builtin::FirstTSBuiltin + 1;
28static constexpr int NumX86_64Builtins =
29 X86::LastTSBuiltin - X86::FirstX86_64Builtin;
30static constexpr int NumBuiltins = X86::LastTSBuiltin - Builtin::FirstTSBuiltin;
31static_assert(NumBuiltins == (NumX86Builtins + NumX86_64Builtins));
32
33namespace X86 {
34#define GET_BUILTIN_STR_TABLE
35#include "clang/Basic/BuiltinsX86.inc"
36#undef GET_BUILTIN_STR_TABLE
37
38static constexpr Builtin::Info BuiltinInfos[] = {
39#define GET_BUILTIN_INFOS
40#include "clang/Basic/BuiltinsX86.inc"
41#undef GET_BUILTIN_INFOS
42};
43
44static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
45#define GET_BUILTIN_PREFIXED_INFOS
46#include "clang/Basic/BuiltinsX86.inc"
47#undef GET_BUILTIN_PREFIXED_INFOS
48};
49static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
50 NumX86Builtins);
51} // namespace X86
52
53namespace X86_64 {
54#define GET_BUILTIN_STR_TABLE
55#include "clang/Basic/BuiltinsX86_64.inc"
56#undef GET_BUILTIN_STR_TABLE
57
58static constexpr Builtin::Info BuiltinInfos[] = {
59#define GET_BUILTIN_INFOS
60#include "clang/Basic/BuiltinsX86_64.inc"
61#undef GET_BUILTIN_INFOS
62};
63
64static constexpr Builtin::Info PrefixedBuiltinInfos[] = {
65#define GET_BUILTIN_PREFIXED_INFOS
66#include "clang/Basic/BuiltinsX86_64.inc"
67#undef GET_BUILTIN_PREFIXED_INFOS
68};
69static_assert((std::size(BuiltinInfos) + std::size(PrefixedBuiltinInfos)) ==
70 NumX86_64Builtins);
71} // namespace X86_64
72
73static const char *const GCCRegNames[] = {
74 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
75 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
76 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
77 "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
78 "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
79 "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
80 "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
81 "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
82 "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
83 "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
84 "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
85 "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
86 "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
87 "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
88 "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
89 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
90 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
91 "k2", "k3", "k4", "k5", "k6", "k7",
92 "cr0", "cr2", "cr3", "cr4", "cr8",
93 "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
94 "bnd0", "bnd1", "bnd2", "bnd3",
95 "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7",
96 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
97 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
98};
99
100const TargetInfo::AddlRegName AddlRegNames[] = {
101 {.Names: {"al", "ah", "eax", "rax"}, .RegNum: 0},
102 {.Names: {"bl", "bh", "ebx", "rbx"}, .RegNum: 3},
103 {.Names: {"cl", "ch", "ecx", "rcx"}, .RegNum: 2},
104 {.Names: {"dl", "dh", "edx", "rdx"}, .RegNum: 1},
105 {.Names: {"esi", "rsi"}, .RegNum: 4},
106 {.Names: {"edi", "rdi"}, .RegNum: 5},
107 {.Names: {"esp", "rsp"}, .RegNum: 7},
108 {.Names: {"ebp", "rbp"}, .RegNum: 6},
109 {.Names: {"r8d", "r8w", "r8b"}, .RegNum: 38},
110 {.Names: {"r9d", "r9w", "r9b"}, .RegNum: 39},
111 {.Names: {"r10d", "r10w", "r10b"}, .RegNum: 40},
112 {.Names: {"r11d", "r11w", "r11b"}, .RegNum: 41},
113 {.Names: {"r12d", "r12w", "r12b"}, .RegNum: 42},
114 {.Names: {"r13d", "r13w", "r13b"}, .RegNum: 43},
115 {.Names: {"r14d", "r14w", "r14b"}, .RegNum: 44},
116 {.Names: {"r15d", "r15w", "r15b"}, .RegNum: 45},
117 {.Names: {"r16d", "r16w", "r16b"}, .RegNum: 165},
118 {.Names: {"r17d", "r17w", "r17b"}, .RegNum: 166},
119 {.Names: {"r18d", "r18w", "r18b"}, .RegNum: 167},
120 {.Names: {"r19d", "r19w", "r19b"}, .RegNum: 168},
121 {.Names: {"r20d", "r20w", "r20b"}, .RegNum: 169},
122 {.Names: {"r21d", "r21w", "r21b"}, .RegNum: 170},
123 {.Names: {"r22d", "r22w", "r22b"}, .RegNum: 171},
124 {.Names: {"r23d", "r23w", "r23b"}, .RegNum: 172},
125 {.Names: {"r24d", "r24w", "r24b"}, .RegNum: 173},
126 {.Names: {"r25d", "r25w", "r25b"}, .RegNum: 174},
127 {.Names: {"r26d", "r26w", "r26b"}, .RegNum: 175},
128 {.Names: {"r27d", "r27w", "r27b"}, .RegNum: 176},
129 {.Names: {"r28d", "r28w", "r28b"}, .RegNum: 177},
130 {.Names: {"r29d", "r29w", "r29b"}, .RegNum: 178},
131 {.Names: {"r30d", "r30w", "r30b"}, .RegNum: 179},
132 {.Names: {"r31d", "r31w", "r31b"}, .RegNum: 180},
133};
134} // namespace targets
135} // namespace clang
136
137using namespace clang;
138using namespace clang::targets;
139
140bool X86TargetInfo::setFPMath(StringRef Name) {
141 if (Name == "387") {
142 FPMath = FP_387;
143 return true;
144 }
145 if (Name == "sse") {
146 FPMath = FP_SSE;
147 return true;
148 }
149 return false;
150}
151
152bool X86TargetInfo::initFeatureMap(
153 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
154 const std::vector<std::string> &FeaturesVec) const {
155 // FIXME: This *really* should not be here.
156 // X86_64 always has SSE2.
157 if (getTriple().getArch() == llvm::Triple::x86_64)
158 setFeatureEnabled(Features, Name: "sse2", Enabled: true);
159
160 using namespace llvm::X86;
161
162 SmallVector<StringRef, 16> CPUFeatures;
163 getFeaturesForCPU(CPU, Features&: CPUFeatures);
164 for (auto &F : CPUFeatures)
165 setFeatureEnabled(Features, Name: F, Enabled: true);
166
167 std::vector<std::string> UpdatedFeaturesVec;
168 for (const auto &Feature : FeaturesVec) {
169 // Expand general-regs-only to -x86, -mmx and -sse
170 if (Feature == "+general-regs-only") {
171 UpdatedFeaturesVec.push_back(x: "-x87");
172 UpdatedFeaturesVec.push_back(x: "-mmx");
173 UpdatedFeaturesVec.push_back(x: "-sse");
174 continue;
175 }
176
177 if (Feature == "+apxf" || Feature == "-apxf") {
178 char Sign = Feature[0];
179 for (const char *Sub :
180 {"egpr", "push2pop2", "ppx", "ndd", "ccmp", "nf", "zu", "jmpabs"})
181 UpdatedFeaturesVec.push_back(x: Sign + std::string(Sub));
182 continue;
183 }
184
185 UpdatedFeaturesVec.push_back(x: Feature);
186 }
187
188 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec: UpdatedFeaturesVec))
189 return false;
190
191 // Can't do this earlier because we need to be able to explicitly enable
192 // or disable these features and the things that they depend upon.
193
194 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
195 auto I = Features.find(Key: "sse4.2");
196 if (I != Features.end() && I->getValue() &&
197 !llvm::is_contained(Range&: UpdatedFeaturesVec, Element: "-popcnt"))
198 Features["popcnt"] = true;
199
200 // Additionally, if SSE is enabled and mmx is not explicitly disabled,
201 // then enable MMX.
202 I = Features.find(Key: "sse");
203 if (I != Features.end() && I->getValue() &&
204 !llvm::is_contained(Range&: UpdatedFeaturesVec, Element: "-mmx"))
205 Features["mmx"] = true;
206
207 // Enable xsave if avx is enabled and xsave is not explicitly disabled.
208 I = Features.find(Key: "avx");
209 if (I != Features.end() && I->getValue() &&
210 !llvm::is_contained(Range&: UpdatedFeaturesVec, Element: "-xsave"))
211 Features["xsave"] = true;
212
213 // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
214 I = Features.find(Key: "sse4.2");
215 if (I != Features.end() && I->getValue() &&
216 !llvm::is_contained(Range&: UpdatedFeaturesVec, Element: "-crc32"))
217 Features["crc32"] = true;
218
219 return true;
220}
221
222void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
223 StringRef Name, bool Enabled) const {
224 if (Name == "sse4") {
225 // We can get here via the __target__ attribute since that's not controlled
226 // via the -msse4/-mno-sse4 command line alias. Handle this the same way
227 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
228 // disabled.
229 if (Enabled)
230 Name = "sse4.2";
231 else
232 Name = "sse4.1";
233 }
234
235 Features[Name] = Enabled;
236 llvm::X86::updateImpliedFeatures(Feature: Name, Enabled, Features);
237}
238
239/// handleTargetFeatures - Perform initialization based on the user
240/// configured set of features.
241bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
242 DiagnosticsEngine &Diags) {
243 for (const auto &Feature : Features) {
244 if (Feature[0] != '+')
245 continue;
246
247 if (Feature == "+mmx") {
248 HasMMX = true;
249 } else if (Feature == "+aes") {
250 HasAES = true;
251 } else if (Feature == "+vaes") {
252 HasVAES = true;
253 } else if (Feature == "+pclmul") {
254 HasPCLMUL = true;
255 } else if (Feature == "+vpclmulqdq") {
256 HasVPCLMULQDQ = true;
257 } else if (Feature == "+lzcnt") {
258 HasLZCNT = true;
259 } else if (Feature == "+rdrnd") {
260 HasRDRND = true;
261 } else if (Feature == "+fsgsbase") {
262 HasFSGSBASE = true;
263 } else if (Feature == "+bmi") {
264 HasBMI = true;
265 } else if (Feature == "+bmi2") {
266 HasBMI2 = true;
267 } else if (Feature == "+popcnt") {
268 HasPOPCNT = true;
269 } else if (Feature == "+rtm") {
270 HasRTM = true;
271 } else if (Feature == "+prfchw") {
272 HasPRFCHW = true;
273 } else if (Feature == "+rdseed") {
274 HasRDSEED = true;
275 } else if (Feature == "+adx") {
276 HasADX = true;
277 } else if (Feature == "+tbm") {
278 HasTBM = true;
279 } else if (Feature == "+lwp") {
280 HasLWP = true;
281 } else if (Feature == "+fma") {
282 HasFMA = true;
283 } else if (Feature == "+f16c") {
284 HasF16C = true;
285 } else if (Feature == "+gfni") {
286 HasGFNI = true;
287 } else if (Feature == "+avx10.1") {
288 HasAVX10_1 = true;
289 } else if (Feature == "+avx10.2") {
290 HasAVX10_2 = true;
291 HasFullBFloat16 = true;
292 } else if (Feature == "+avx10v2aux") {
293 HasAVX10_V2_AUX = true;
294 } else if (Feature == "+avx512cd") {
295 HasAVX512CD = true;
296 } else if (Feature == "+avx512vpopcntdq") {
297 HasAVX512VPOPCNTDQ = true;
298 } else if (Feature == "+avx512vnni") {
299 HasAVX512VNNI = true;
300 } else if (Feature == "+avx512bf16") {
301 HasAVX512BF16 = true;
302 } else if (Feature == "+avx512fp16") {
303 HasAVX512FP16 = true;
304 HasFastHalfType = true;
305 } else if (Feature == "+avx512dq") {
306 HasAVX512DQ = true;
307 } else if (Feature == "+avx512bitalg") {
308 HasAVX512BITALG = true;
309 } else if (Feature == "+avx512bmm") {
310 HasAVX512BMM = true;
311 } else if (Feature == "+avx512bw") {
312 HasAVX512BW = true;
313 } else if (Feature == "+avx512vl") {
314 HasAVX512VL = true;
315 } else if (Feature == "+avx512vbmi") {
316 HasAVX512VBMI = true;
317 } else if (Feature == "+avx512vbmi2") {
318 HasAVX512VBMI2 = true;
319 } else if (Feature == "+avx512ifma") {
320 HasAVX512IFMA = true;
321 } else if (Feature == "+avx512vp2intersect") {
322 HasAVX512VP2INTERSECT = true;
323 } else if (Feature == "+sha") {
324 HasSHA = true;
325 } else if (Feature == "+sha512") {
326 HasSHA512 = true;
327 } else if (Feature == "+shstk") {
328 HasSHSTK = true;
329 } else if (Feature == "+sm3") {
330 HasSM3 = true;
331 } else if (Feature == "+sm4") {
332 HasSM4 = true;
333 } else if (Feature == "+movbe") {
334 HasMOVBE = true;
335 } else if (Feature == "+movrs") {
336 HasMOVRS = true;
337 } else if (Feature == "+sgx") {
338 HasSGX = true;
339 } else if (Feature == "+cx8") {
340 HasCX8 = true;
341 } else if (Feature == "+cx16") {
342 HasCX16 = true;
343 } else if (Feature == "+fxsr") {
344 HasFXSR = true;
345 } else if (Feature == "+xsave") {
346 HasXSAVE = true;
347 } else if (Feature == "+xsaveopt") {
348 HasXSAVEOPT = true;
349 } else if (Feature == "+xsavec") {
350 HasXSAVEC = true;
351 } else if (Feature == "+xsaves") {
352 HasXSAVES = true;
353 } else if (Feature == "+mwaitx") {
354 HasMWAITX = true;
355 } else if (Feature == "+pku") {
356 HasPKU = true;
357 } else if (Feature == "+clflushopt") {
358 HasCLFLUSHOPT = true;
359 } else if (Feature == "+clwb") {
360 HasCLWB = true;
361 } else if (Feature == "+wbnoinvd") {
362 HasWBNOINVD = true;
363 } else if (Feature == "+prefetchi") {
364 HasPREFETCHI = true;
365 } else if (Feature == "+clzero") {
366 HasCLZERO = true;
367 } else if (Feature == "+cldemote") {
368 HasCLDEMOTE = true;
369 } else if (Feature == "+rdpid") {
370 HasRDPID = true;
371 } else if (Feature == "+rdpru") {
372 HasRDPRU = true;
373 } else if (Feature == "+kl") {
374 HasKL = true;
375 } else if (Feature == "+widekl") {
376 HasWIDEKL = true;
377 } else if (Feature == "+retpoline-external-thunk") {
378 HasRetpolineExternalThunk = true;
379 } else if (Feature == "+sahf") {
380 HasLAHFSAHF = true;
381 } else if (Feature == "+waitpkg") {
382 HasWAITPKG = true;
383 } else if (Feature == "+movdiri") {
384 HasMOVDIRI = true;
385 } else if (Feature == "+movdir64b") {
386 HasMOVDIR64B = true;
387 } else if (Feature == "+pconfig") {
388 HasPCONFIG = true;
389 } else if (Feature == "+ptwrite") {
390 HasPTWRITE = true;
391 } else if (Feature == "+invpcid") {
392 HasINVPCID = true;
393 } else if (Feature == "+enqcmd") {
394 HasENQCMD = true;
395 } else if (Feature == "+hreset") {
396 HasHRESET = true;
397 } else if (Feature == "+amx-bf16") {
398 HasAMXBF16 = true;
399 } else if (Feature == "+amx-fp16") {
400 HasAMXFP16 = true;
401 } else if (Feature == "+amx-int8") {
402 HasAMXINT8 = true;
403 } else if (Feature == "+amx-tile") {
404 HasAMXTILE = true;
405 } else if (Feature == "+amx-complex") {
406 HasAMXCOMPLEX = true;
407 } else if (Feature == "+amx-fp8") {
408 HasAMXFP8 = true;
409 } else if (Feature == "+amx-movrs") {
410 HasAMXMOVRS = true;
411 } else if (Feature == "+amx-avx512") {
412 HasAMXAVX512 = true;
413 } else if (Feature == "+cmpccxadd") {
414 HasCMPCCXADD = true;
415 } else if (Feature == "+raoint") {
416 HasRAOINT = true;
417 } else if (Feature == "+avxifma") {
418 HasAVXIFMA = true;
419 } else if (Feature == "+avxneconvert") {
420 HasAVXNECONVERT= true;
421 } else if (Feature == "+avxvnni") {
422 HasAVXVNNI = true;
423 } else if (Feature == "+avxvnniint16") {
424 HasAVXVNNIINT16 = true;
425 } else if (Feature == "+avxvnniint8") {
426 HasAVXVNNIINT8 = true;
427 } else if (Feature == "+serialize") {
428 HasSERIALIZE = true;
429 } else if (Feature == "+tsxldtrk") {
430 HasTSXLDTRK = true;
431 } else if (Feature == "+uintr") {
432 HasUINTR = true;
433 } else if (Feature == "+usermsr") {
434 HasUSERMSR = true;
435 } else if (Feature == "+crc32") {
436 HasCRC32 = true;
437 } else if (Feature == "+x87") {
438 HasX87 = true;
439 } else if (Feature == "+fullbf16") {
440 HasFullBFloat16 = true;
441 } else if (Feature == "+egpr") {
442 HasEGPR = true;
443 } else if (Feature == "+inline-asm-use-gpr32") {
444 HasInlineAsmUseGPR32 = true;
445 } else if (Feature == "+push2pop2") {
446 HasPush2Pop2 = true;
447 } else if (Feature == "+ppx") {
448 HasPPX = true;
449 } else if (Feature == "+ndd") {
450 HasNDD = true;
451 } else if (Feature == "+ccmp") {
452 HasCCMP = true;
453 } else if (Feature == "+nf") {
454 HasNF = true;
455 } else if (Feature == "+cf") {
456 HasCF = true;
457 } else if (Feature == "+zu") {
458 HasZU = true;
459 } else if (Feature == "+jmpabs") {
460 HasJMPABS = true;
461 } else if (Feature == "+branch-hint") {
462 HasBranchHint = true;
463 }
464
465 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
466 .Case(S: "+avx512f", Value: AVX512F)
467 .Case(S: "+avx2", Value: AVX2)
468 .Case(S: "+avx", Value: AVX)
469 .Case(S: "+sse4.2", Value: SSE42)
470 .Case(S: "+sse4.1", Value: SSE41)
471 .Case(S: "+ssse3", Value: SSSE3)
472 .Case(S: "+sse3", Value: SSE3)
473 .Case(S: "+sse2", Value: SSE2)
474 .Case(S: "+sse", Value: SSE1)
475 .Default(Value: NoSSE);
476 SSELevel = std::max(a: SSELevel, b: Level);
477
478 HasFloat16 = SSELevel >= SSE2;
479
480 // X86 target has bfloat16 emulation support in the backend, where
481 // bfloat16 is treated as a 32-bit float, arithmetic operations are
482 // performed in 32-bit, and the result is converted back to bfloat16.
483 // Truncation and extension between bfloat16 and 32-bit float are supported
484 // by the compiler-rt library. However, native bfloat16 support is currently
485 // not available in the X86 target. Hence, HasFullBFloat16 will be false
486 // until native bfloat16 support is available. HasFullBFloat16 is used to
487 // determine whether to automatically use excess floating point precision
488 // for bfloat16 arithmetic operations in the front-end.
489 HasBFloat16 = SSELevel >= SSE2;
490
491 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
492 .Case(S: "+xop", Value: XOP)
493 .Case(S: "+fma4", Value: FMA4)
494 .Case(S: "+sse4a", Value: SSE4A)
495 .Default(Value: NoXOP);
496 XOPLevel = std::max(a: XOPLevel, b: XLevel);
497 }
498
499 // LLVM doesn't have a separate switch for fpmath, so only accept it if it
500 // matches the selected sse level.
501 if ((FPMath == FP_SSE && SSELevel < SSE1) ||
502 (FPMath == FP_387 && SSELevel >= SSE1)) {
503 Diags.Report(DiagID: diag::err_target_unsupported_fpmath)
504 << (FPMath == FP_SSE ? "sse" : "387");
505 return false;
506 }
507
508 // FIXME: We should allow long double type on 32-bits to match with GCC.
509 // This requires backend to be able to lower f80 without x87 first.
510 if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
511 HasLongDouble = false;
512
513 return true;
514}
515
516/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
517/// definitions for this particular subtarget.
518void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
519 MacroBuilder &Builder) const {
520 // Inline assembly supports X86 flag outputs.
521 Builder.defineMacro(Name: "__GCC_ASM_FLAG_OUTPUTS__");
522
523 std::string CodeModel = getTargetOpts().CodeModel;
524 if (CodeModel == "default")
525 CodeModel = "small";
526 Builder.defineMacro(Name: "__code_model_" + CodeModel + "__");
527
528 // Target identification.
529 if (getTriple().getArch() == llvm::Triple::x86_64) {
530 Builder.defineMacro(Name: "__amd64__");
531 Builder.defineMacro(Name: "__amd64");
532 Builder.defineMacro(Name: "__x86_64");
533 Builder.defineMacro(Name: "__x86_64__");
534 if (getTriple().getArchName() == "x86_64h") {
535 Builder.defineMacro(Name: "__x86_64h");
536 Builder.defineMacro(Name: "__x86_64h__");
537 }
538 } else {
539 DefineStd(Builder, MacroName: "i386", Opts);
540 }
541
542 if (getTriple().isLFI()) {
543 Builder.defineMacro(Name: "__LFI__");
544 }
545
546 Builder.defineMacro(Name: "__SEG_GS");
547 Builder.defineMacro(Name: "__SEG_FS");
548 Builder.defineMacro(Name: "__seg_gs", Value: "__attribute__((address_space(256)))");
549 Builder.defineMacro(Name: "__seg_fs", Value: "__attribute__((address_space(257)))");
550
551 // Subtarget options.
552 // FIXME: We are hard-coding the tune parameters based on the CPU, but they
553 // truly should be based on -mtune options.
554 using namespace llvm::X86;
555 switch (CPU) {
556 case CK_None:
557 break;
558 case CK_i386:
559 // The rest are coming from the i386 define above.
560 Builder.defineMacro(Name: "__tune_i386__");
561 break;
562 case CK_i486:
563 case CK_WinChipC6:
564 case CK_WinChip2:
565 case CK_C3:
566 defineCPUMacros(Builder, CPUName: "i486");
567 break;
568 case CK_PentiumMMX:
569 Builder.defineMacro(Name: "__pentium_mmx__");
570 Builder.defineMacro(Name: "__tune_pentium_mmx__");
571 [[fallthrough]];
572 case CK_i586:
573 case CK_Pentium:
574 defineCPUMacros(Builder, CPUName: "i586");
575 defineCPUMacros(Builder, CPUName: "pentium");
576 break;
577 case CK_Pentium3:
578 case CK_PentiumM:
579 Builder.defineMacro(Name: "__tune_pentium3__");
580 [[fallthrough]];
581 case CK_Pentium2:
582 case CK_C3_2:
583 Builder.defineMacro(Name: "__tune_pentium2__");
584 [[fallthrough]];
585 case CK_PentiumPro:
586 case CK_i686:
587 defineCPUMacros(Builder, CPUName: "i686");
588 defineCPUMacros(Builder, CPUName: "pentiumpro");
589 break;
590 case CK_Pentium4:
591 defineCPUMacros(Builder, CPUName: "pentium4");
592 break;
593 case CK_Yonah:
594 case CK_Prescott:
595 case CK_Nocona:
596 defineCPUMacros(Builder, CPUName: "nocona");
597 break;
598 case CK_Core2:
599 case CK_Penryn:
600 defineCPUMacros(Builder, CPUName: "core2");
601 break;
602 case CK_Bonnell:
603 defineCPUMacros(Builder, CPUName: "atom");
604 break;
605 case CK_Silvermont:
606 defineCPUMacros(Builder, CPUName: "slm");
607 break;
608 case CK_Goldmont:
609 defineCPUMacros(Builder, CPUName: "goldmont");
610 break;
611 case CK_GoldmontPlus:
612 defineCPUMacros(Builder, CPUName: "goldmont_plus");
613 break;
614 case CK_Tremont:
615 defineCPUMacros(Builder, CPUName: "tremont");
616 break;
617 // Gracemont and later atom-cores use P-core cpu macros.
618 case CK_Gracemont:
619 case CK_Nehalem:
620 case CK_Westmere:
621 case CK_SandyBridge:
622 case CK_IvyBridge:
623 case CK_Haswell:
624 case CK_Broadwell:
625 case CK_SkylakeClient:
626 case CK_SkylakeServer:
627 case CK_Cascadelake:
628 case CK_Cooperlake:
629 case CK_Cannonlake:
630 case CK_IcelakeClient:
631 case CK_Rocketlake:
632 case CK_IcelakeServer:
633 case CK_Tigerlake:
634 case CK_SapphireRapids:
635 case CK_Alderlake:
636 case CK_Raptorlake:
637 case CK_Meteorlake:
638 case CK_Arrowlake:
639 case CK_ArrowlakeS:
640 case CK_Lunarlake:
641 case CK_Pantherlake:
642 case CK_Wildcatlake:
643 case CK_Novalake:
644 case CK_Sierraforest:
645 case CK_Grandridge:
646 case CK_Graniterapids:
647 case CK_GraniterapidsD:
648 case CK_Emeraldrapids:
649 case CK_Clearwaterforest:
650 case CK_Diamondrapids:
651 // FIXME: Historically, we defined this legacy name, it would be nice to
652 // remove it at some point. We've never exposed fine-grained names for
653 // recent primary x86 CPUs, and we should keep it that way.
654 defineCPUMacros(Builder, CPUName: "corei7");
655 break;
656 case CK_KNL:
657 defineCPUMacros(Builder, CPUName: "knl");
658 break;
659 case CK_KNM:
660 break;
661 case CK_Lakemont:
662 defineCPUMacros(Builder, CPUName: "i586", /*Tuning*/false);
663 defineCPUMacros(Builder, CPUName: "pentium", /*Tuning*/false);
664 Builder.defineMacro(Name: "__tune_lakemont__");
665 break;
666 case CK_K6_2:
667 Builder.defineMacro(Name: "__k6_2__");
668 Builder.defineMacro(Name: "__tune_k6_2__");
669 [[fallthrough]];
670 case CK_K6_3:
671 if (CPU != CK_K6_2) { // In case of fallthrough
672 // FIXME: GCC may be enabling these in cases where some other k6
673 // architecture is specified but -m3dnow is explicitly provided. The
674 // exact semantics need to be determined and emulated here.
675 Builder.defineMacro(Name: "__k6_3__");
676 Builder.defineMacro(Name: "__tune_k6_3__");
677 }
678 [[fallthrough]];
679 case CK_K6:
680 defineCPUMacros(Builder, CPUName: "k6");
681 break;
682 case CK_Athlon:
683 case CK_AthlonXP:
684 defineCPUMacros(Builder, CPUName: "athlon");
685 if (SSELevel != NoSSE) {
686 Builder.defineMacro(Name: "__athlon_sse__");
687 Builder.defineMacro(Name: "__tune_athlon_sse__");
688 }
689 break;
690 case CK_K8:
691 case CK_K8SSE3:
692 case CK_x86_64:
693 defineCPUMacros(Builder, CPUName: "k8");
694 break;
695 case CK_x86_64_v2:
696 case CK_x86_64_v3:
697 case CK_x86_64_v4:
698 break;
699 case CK_AMDFAM10:
700 defineCPUMacros(Builder, CPUName: "amdfam10");
701 break;
702 case CK_BTVER1:
703 defineCPUMacros(Builder, CPUName: "btver1");
704 break;
705 case CK_BTVER2:
706 defineCPUMacros(Builder, CPUName: "btver2");
707 break;
708 case CK_BDVER1:
709 defineCPUMacros(Builder, CPUName: "bdver1");
710 break;
711 case CK_BDVER2:
712 defineCPUMacros(Builder, CPUName: "bdver2");
713 break;
714 case CK_BDVER3:
715 defineCPUMacros(Builder, CPUName: "bdver3");
716 break;
717 case CK_BDVER4:
718 defineCPUMacros(Builder, CPUName: "bdver4");
719 break;
720 case CK_ZNVER1:
721 defineCPUMacros(Builder, CPUName: "znver1");
722 break;
723 case CK_ZNVER2:
724 defineCPUMacros(Builder, CPUName: "znver2");
725 break;
726 case CK_ZNVER3:
727 defineCPUMacros(Builder, CPUName: "znver3");
728 break;
729 case CK_ZNVER4:
730 defineCPUMacros(Builder, CPUName: "znver4");
731 break;
732 case CK_ZNVER5:
733 defineCPUMacros(Builder, CPUName: "znver5");
734 break;
735 case CK_ZNVER6:
736 defineCPUMacros(Builder, CPUName: "znver6");
737 break;
738 case CK_Geode:
739 defineCPUMacros(Builder, CPUName: "geode");
740 break;
741 case CK_C86_4G_M4:
742 defineCPUMacros(Builder, CPUName: "c86_4g_m4");
743 break;
744 case CK_C86_4G_M6:
745 defineCPUMacros(Builder, CPUName: "c86_4g_m6");
746 break;
747 case CK_C86_4G_M7:
748 defineCPUMacros(Builder, CPUName: "c86_4g_m7");
749 break;
750 case CK_C86_4G_M8:
751 defineCPUMacros(Builder, CPUName: "c86_4g_m8");
752 break;
753 }
754
755 // Target properties.
756 Builder.defineMacro(Name: "__REGISTER_PREFIX__", Value: "");
757
758 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
759 // functions in glibc header files that use FP Stack inline asm which the
760 // backend can't deal with (PR879).
761 Builder.defineMacro(Name: "__NO_MATH_INLINES");
762
763 if (HasAES)
764 Builder.defineMacro(Name: "__AES__");
765
766 if (HasVAES)
767 Builder.defineMacro(Name: "__VAES__");
768
769 if (HasPCLMUL)
770 Builder.defineMacro(Name: "__PCLMUL__");
771
772 if (HasVPCLMULQDQ)
773 Builder.defineMacro(Name: "__VPCLMULQDQ__");
774
775 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
776 // the feature flag only applies to 64-bit mode.
777 if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
778 Builder.defineMacro(Name: "__LAHF_SAHF__");
779
780 if (HasLZCNT)
781 Builder.defineMacro(Name: "__LZCNT__");
782
783 if (HasRDRND)
784 Builder.defineMacro(Name: "__RDRND__");
785
786 if (HasFSGSBASE)
787 Builder.defineMacro(Name: "__FSGSBASE__");
788
789 if (HasBMI)
790 Builder.defineMacro(Name: "__BMI__");
791
792 if (HasBMI2)
793 Builder.defineMacro(Name: "__BMI2__");
794
795 if (HasPOPCNT)
796 Builder.defineMacro(Name: "__POPCNT__");
797
798 if (HasRTM)
799 Builder.defineMacro(Name: "__RTM__");
800
801 if (HasPRFCHW)
802 Builder.defineMacro(Name: "__PRFCHW__");
803
804 if (HasRDSEED)
805 Builder.defineMacro(Name: "__RDSEED__");
806
807 if (HasADX)
808 Builder.defineMacro(Name: "__ADX__");
809
810 if (HasTBM)
811 Builder.defineMacro(Name: "__TBM__");
812
813 if (HasLWP)
814 Builder.defineMacro(Name: "__LWP__");
815
816 if (HasMWAITX)
817 Builder.defineMacro(Name: "__MWAITX__");
818
819 if (HasMOVBE)
820 Builder.defineMacro(Name: "__MOVBE__");
821
822 switch (XOPLevel) {
823 case XOP:
824 Builder.defineMacro(Name: "__XOP__");
825 [[fallthrough]];
826 case FMA4:
827 Builder.defineMacro(Name: "__FMA4__");
828 [[fallthrough]];
829 case SSE4A:
830 Builder.defineMacro(Name: "__SSE4A__");
831 [[fallthrough]];
832 case NoXOP:
833 break;
834 }
835
836 if (HasFMA)
837 Builder.defineMacro(Name: "__FMA__");
838
839 if (HasF16C)
840 Builder.defineMacro(Name: "__F16C__");
841
842 if (HasGFNI)
843 Builder.defineMacro(Name: "__GFNI__");
844
845 if (HasAVX10_1) {
846 Builder.defineMacro(Name: "__AVX10_1__");
847 Builder.defineMacro(Name: "__AVX10_1_512__");
848 }
849 if (HasAVX10_2) {
850 Builder.defineMacro(Name: "__AVX10_2__");
851 Builder.defineMacro(Name: "__AVX10_2_512__");
852 }
853 if (HasAVX10_V2_AUX)
854 Builder.defineMacro(Name: "__AVX10_V2_AUX__");
855 if (HasAVX512CD)
856 Builder.defineMacro(Name: "__AVX512CD__");
857 if (HasAVX512VPOPCNTDQ)
858 Builder.defineMacro(Name: "__AVX512VPOPCNTDQ__");
859 if (HasAVX512VNNI)
860 Builder.defineMacro(Name: "__AVX512VNNI__");
861 if (HasAVX512BF16)
862 Builder.defineMacro(Name: "__AVX512BF16__");
863 if (HasAVX512FP16)
864 Builder.defineMacro(Name: "__AVX512FP16__");
865 if (HasAVX512DQ)
866 Builder.defineMacro(Name: "__AVX512DQ__");
867 if (HasAVX512BITALG)
868 Builder.defineMacro(Name: "__AVX512BITALG__");
869 if (HasAVX512BMM)
870 Builder.defineMacro(Name: "__AVX512BMM__");
871 if (HasAVX512BW)
872 Builder.defineMacro(Name: "__AVX512BW__");
873 if (HasAVX512VL) {
874 Builder.defineMacro(Name: "__AVX512VL__");
875 }
876 if (HasAVX512VBMI)
877 Builder.defineMacro(Name: "__AVX512VBMI__");
878 if (HasAVX512VBMI2)
879 Builder.defineMacro(Name: "__AVX512VBMI2__");
880 if (HasAVX512IFMA)
881 Builder.defineMacro(Name: "__AVX512IFMA__");
882 if (HasAVX512VP2INTERSECT)
883 Builder.defineMacro(Name: "__AVX512VP2INTERSECT__");
884 if (HasSHA)
885 Builder.defineMacro(Name: "__SHA__");
886 if (HasSHA512)
887 Builder.defineMacro(Name: "__SHA512__");
888
889 if (HasFXSR)
890 Builder.defineMacro(Name: "__FXSR__");
891 if (HasXSAVE)
892 Builder.defineMacro(Name: "__XSAVE__");
893 if (HasXSAVEOPT)
894 Builder.defineMacro(Name: "__XSAVEOPT__");
895 if (HasXSAVEC)
896 Builder.defineMacro(Name: "__XSAVEC__");
897 if (HasXSAVES)
898 Builder.defineMacro(Name: "__XSAVES__");
899 if (HasPKU)
900 Builder.defineMacro(Name: "__PKU__");
901 if (HasCLFLUSHOPT)
902 Builder.defineMacro(Name: "__CLFLUSHOPT__");
903 if (HasCLWB)
904 Builder.defineMacro(Name: "__CLWB__");
905 if (HasWBNOINVD)
906 Builder.defineMacro(Name: "__WBNOINVD__");
907 if (HasSHSTK)
908 Builder.defineMacro(Name: "__SHSTK__");
909 if (HasSGX)
910 Builder.defineMacro(Name: "__SGX__");
911 if (HasSM3)
912 Builder.defineMacro(Name: "__SM3__");
913 if (HasSM4)
914 Builder.defineMacro(Name: "__SM4__");
915 if (HasPREFETCHI)
916 Builder.defineMacro(Name: "__PREFETCHI__");
917 if (HasCLZERO)
918 Builder.defineMacro(Name: "__CLZERO__");
919 if (HasKL)
920 Builder.defineMacro(Name: "__KL__");
921 if (HasWIDEKL)
922 Builder.defineMacro(Name: "__WIDEKL__");
923 if (HasRDPID)
924 Builder.defineMacro(Name: "__RDPID__");
925 if (HasRDPRU)
926 Builder.defineMacro(Name: "__RDPRU__");
927 if (HasCLDEMOTE)
928 Builder.defineMacro(Name: "__CLDEMOTE__");
929 if (HasWAITPKG)
930 Builder.defineMacro(Name: "__WAITPKG__");
931 if (HasMOVDIRI)
932 Builder.defineMacro(Name: "__MOVDIRI__");
933 if (HasMOVDIR64B)
934 Builder.defineMacro(Name: "__MOVDIR64B__");
935 if (HasMOVRS)
936 Builder.defineMacro(Name: "__MOVRS__");
937 if (HasPCONFIG)
938 Builder.defineMacro(Name: "__PCONFIG__");
939 if (HasPTWRITE)
940 Builder.defineMacro(Name: "__PTWRITE__");
941 if (HasINVPCID)
942 Builder.defineMacro(Name: "__INVPCID__");
943 if (HasENQCMD)
944 Builder.defineMacro(Name: "__ENQCMD__");
945 if (HasHRESET)
946 Builder.defineMacro(Name: "__HRESET__");
947 if (HasAMXTILE)
948 Builder.defineMacro(Name: "__AMX_TILE__");
949 if (HasAMXINT8)
950 Builder.defineMacro(Name: "__AMX_INT8__");
951 if (HasAMXBF16)
952 Builder.defineMacro(Name: "__AMX_BF16__");
953 if (HasAMXFP16)
954 Builder.defineMacro(Name: "__AMX_FP16__");
955 if (HasAMXCOMPLEX)
956 Builder.defineMacro(Name: "__AMX_COMPLEX__");
957 if (HasAMXFP8)
958 Builder.defineMacro(Name: "__AMX_FP8__");
959 if (HasAMXMOVRS)
960 Builder.defineMacro(Name: "__AMX_MOVRS__");
961 if (HasAMXAVX512)
962 Builder.defineMacro(Name: "__AMX_AVX512__");
963 if (HasCMPCCXADD)
964 Builder.defineMacro(Name: "__CMPCCXADD__");
965 if (HasRAOINT)
966 Builder.defineMacro(Name: "__RAOINT__");
967 if (HasAVXIFMA)
968 Builder.defineMacro(Name: "__AVXIFMA__");
969 if (HasAVXNECONVERT)
970 Builder.defineMacro(Name: "__AVXNECONVERT__");
971 if (HasAVXVNNI)
972 Builder.defineMacro(Name: "__AVXVNNI__");
973 if (HasAVXVNNIINT16)
974 Builder.defineMacro(Name: "__AVXVNNIINT16__");
975 if (HasAVXVNNIINT8)
976 Builder.defineMacro(Name: "__AVXVNNIINT8__");
977 if (HasSERIALIZE)
978 Builder.defineMacro(Name: "__SERIALIZE__");
979 if (HasTSXLDTRK)
980 Builder.defineMacro(Name: "__TSXLDTRK__");
981 if (HasUINTR)
982 Builder.defineMacro(Name: "__UINTR__");
983 if (HasUSERMSR)
984 Builder.defineMacro(Name: "__USERMSR__");
985 if (HasCRC32)
986 Builder.defineMacro(Name: "__CRC32__");
987 if (HasEGPR)
988 Builder.defineMacro(Name: "__EGPR__");
989 if (HasPush2Pop2)
990 Builder.defineMacro(Name: "__PUSH2POP2__");
991 if (HasPPX)
992 Builder.defineMacro(Name: "__PPX__");
993 if (HasNDD)
994 Builder.defineMacro(Name: "__NDD__");
995 if (HasCCMP)
996 Builder.defineMacro(Name: "__CCMP__");
997 if (HasNF)
998 Builder.defineMacro(Name: "__NF__");
999 if (HasCF)
1000 Builder.defineMacro(Name: "__CF__");
1001 if (HasZU)
1002 Builder.defineMacro(Name: "__ZU__");
1003 if (HasJMPABS)
1004 Builder.defineMacro(Name: "__JMPABS__");
1005 if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD && HasCCMP && HasNF &&
1006 HasZU && HasJMPABS)
1007 Builder.defineMacro(Name: "__APX_F__");
1008 if (HasEGPR && HasInlineAsmUseGPR32)
1009 Builder.defineMacro(Name: "__APX_INLINE_ASM_USE_GPR32__");
1010
1011 // Each case falls through to the previous one here.
1012 switch (SSELevel) {
1013 case AVX512F:
1014 Builder.defineMacro(Name: "__AVX512F__");
1015 [[fallthrough]];
1016 case AVX2:
1017 Builder.defineMacro(Name: "__AVX2__");
1018 [[fallthrough]];
1019 case AVX:
1020 Builder.defineMacro(Name: "__AVX__");
1021 [[fallthrough]];
1022 case SSE42:
1023 Builder.defineMacro(Name: "__SSE4_2__");
1024 [[fallthrough]];
1025 case SSE41:
1026 Builder.defineMacro(Name: "__SSE4_1__");
1027 [[fallthrough]];
1028 case SSSE3:
1029 Builder.defineMacro(Name: "__SSSE3__");
1030 [[fallthrough]];
1031 case SSE3:
1032 Builder.defineMacro(Name: "__SSE3__");
1033 [[fallthrough]];
1034 case SSE2:
1035 Builder.defineMacro(Name: "__SSE2__");
1036 Builder.defineMacro(Name: "__SSE2_MATH__"); // -mfp-math=sse always implied.
1037 [[fallthrough]];
1038 case SSE1:
1039 Builder.defineMacro(Name: "__SSE__");
1040 Builder.defineMacro(Name: "__SSE_MATH__"); // -mfp-math=sse always implied.
1041 [[fallthrough]];
1042 case NoSSE:
1043 break;
1044 }
1045
1046 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1047 switch (SSELevel) {
1048 case AVX512F:
1049 case AVX2:
1050 case AVX:
1051 case SSE42:
1052 case SSE41:
1053 case SSSE3:
1054 case SSE3:
1055 case SSE2:
1056 Builder.defineMacro(Name: "_M_IX86_FP", Value: Twine(2));
1057 break;
1058 case SSE1:
1059 Builder.defineMacro(Name: "_M_IX86_FP", Value: Twine(1));
1060 break;
1061 default:
1062 Builder.defineMacro(Name: "_M_IX86_FP", Value: Twine(0));
1063 break;
1064 }
1065 }
1066
1067 // Each case falls through to the previous one here.
1068 if (HasMMX) {
1069 Builder.defineMacro(Name: "__MMX__");
1070 }
1071
1072 if (CPU >= CK_i486 || CPU == CK_None) {
1073 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1074 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1075 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1076 }
1077 if (HasCX8)
1078 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1079 if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
1080 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1081
1082 if (HasFloat128)
1083 Builder.defineMacro(Name: "__SIZEOF_FLOAT128__", Value: "16");
1084
1085 if (Opts.CFProtectionReturn || Opts.CFProtectionBranch)
1086 Builder.defineMacro(Name: "__CET__", Value: Twine{(Opts.CFProtectionReturn << 1) |
1087 Opts.CFProtectionBranch});
1088}
1089
1090bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1091 return llvm::StringSwitch<bool>(Name)
1092 .Case(S: "adx", Value: true)
1093 .Case(S: "aes", Value: true)
1094 .Case(S: "amx-avx512", Value: true)
1095 .Case(S: "amx-bf16", Value: true)
1096 .Case(S: "amx-complex", Value: true)
1097 .Case(S: "amx-fp16", Value: true)
1098 .Case(S: "amx-fp8", Value: true)
1099 .Case(S: "amx-int8", Value: true)
1100 .Case(S: "amx-movrs", Value: true)
1101 .Case(S: "amx-tile", Value: true)
1102 .Case(S: "avx", Value: true)
1103 .Case(S: "avx10.1", Value: true)
1104 .Case(S: "avx10.2", Value: true)
1105 .Case(S: "avx10v2aux", Value: true)
1106 .Case(S: "avx2", Value: true)
1107 .Case(S: "avx512f", Value: true)
1108 .Case(S: "avx512cd", Value: true)
1109 .Case(S: "avx512vpopcntdq", Value: true)
1110 .Case(S: "avx512vnni", Value: true)
1111 .Case(S: "avx512bf16", Value: true)
1112 .Case(S: "avx512fp16", Value: true)
1113 .Case(S: "avx512dq", Value: true)
1114 .Case(S: "avx512bitalg", Value: true)
1115 .Case(S: "avx512bmm", Value: true)
1116 .Case(S: "avx512bw", Value: true)
1117 .Case(S: "avx512vl", Value: true)
1118 .Case(S: "avx512vbmi", Value: true)
1119 .Case(S: "avx512vbmi2", Value: true)
1120 .Case(S: "avx512ifma", Value: true)
1121 .Case(S: "avx512vp2intersect", Value: true)
1122 .Case(S: "avxifma", Value: true)
1123 .Case(S: "avxneconvert", Value: true)
1124 .Case(S: "avxvnni", Value: true)
1125 .Case(S: "avxvnniint16", Value: true)
1126 .Case(S: "avxvnniint8", Value: true)
1127 .Case(S: "bmi", Value: true)
1128 .Case(S: "bmi2", Value: true)
1129 .Case(S: "cldemote", Value: true)
1130 .Case(S: "clflushopt", Value: true)
1131 .Case(S: "clwb", Value: true)
1132 .Case(S: "clzero", Value: true)
1133 .Case(S: "cmpccxadd", Value: true)
1134 .Case(S: "crc32", Value: true)
1135 .Case(S: "cx16", Value: true)
1136 .Case(S: "enqcmd", Value: true)
1137 .Case(S: "f16c", Value: true)
1138 .Case(S: "fma", Value: true)
1139 .Case(S: "fma4", Value: true)
1140 .Case(S: "fsgsbase", Value: true)
1141 .Case(S: "fxsr", Value: true)
1142 .Case(S: "general-regs-only", Value: true)
1143 .Case(S: "gfni", Value: true)
1144 .Case(S: "hreset", Value: true)
1145 .Case(S: "invpcid", Value: true)
1146 .Case(S: "kl", Value: true)
1147 .Case(S: "widekl", Value: true)
1148 .Case(S: "lwp", Value: true)
1149 .Case(S: "lzcnt", Value: true)
1150 .Case(S: "mmx", Value: true)
1151 .Case(S: "movbe", Value: true)
1152 .Case(S: "movrs", Value: true)
1153 .Case(S: "movdiri", Value: true)
1154 .Case(S: "movdir64b", Value: true)
1155 .Case(S: "mwaitx", Value: true)
1156 .Case(S: "pclmul", Value: true)
1157 .Case(S: "pconfig", Value: true)
1158 .Case(S: "pku", Value: true)
1159 .Case(S: "popcnt", Value: true)
1160 .Case(S: "prefer-256-bit", Value: true)
1161 .Case(S: "prefetchi", Value: true)
1162 .Case(S: "prfchw", Value: true)
1163 .Case(S: "ptwrite", Value: true)
1164 .Case(S: "raoint", Value: true)
1165 .Case(S: "rdpid", Value: true)
1166 .Case(S: "rdpru", Value: true)
1167 .Case(S: "rdrnd", Value: true)
1168 .Case(S: "rdseed", Value: true)
1169 .Case(S: "rtm", Value: true)
1170 .Case(S: "sahf", Value: true)
1171 .Case(S: "serialize", Value: true)
1172 .Case(S: "sgx", Value: true)
1173 .Case(S: "sha", Value: true)
1174 .Case(S: "sha512", Value: true)
1175 .Case(S: "shstk", Value: true)
1176 .Case(S: "sm3", Value: true)
1177 .Case(S: "sm4", Value: true)
1178 .Case(S: "sse", Value: true)
1179 .Case(S: "sse2", Value: true)
1180 .Case(S: "sse3", Value: true)
1181 .Case(S: "ssse3", Value: true)
1182 .Case(S: "sse4", Value: true)
1183 .Case(S: "sse4.1", Value: true)
1184 .Case(S: "sse4.2", Value: true)
1185 .Case(S: "sse4a", Value: true)
1186 .Case(S: "tbm", Value: true)
1187 .Case(S: "tsxldtrk", Value: true)
1188 .Case(S: "uintr", Value: true)
1189 .Case(S: "usermsr", Value: true)
1190 .Case(S: "vaes", Value: true)
1191 .Case(S: "vpclmulqdq", Value: true)
1192 .Case(S: "wbnoinvd", Value: true)
1193 .Case(S: "waitpkg", Value: true)
1194 .Case(S: "x87", Value: true)
1195 .Case(S: "xop", Value: true)
1196 .Case(S: "xsave", Value: true)
1197 .Case(S: "xsavec", Value: true)
1198 .Case(S: "xsaves", Value: true)
1199 .Case(S: "xsaveopt", Value: true)
1200 .Case(S: "apxf", Value: true)
1201 .Case(S: "egpr", Value: true)
1202 .Case(S: "push2pop2", Value: true)
1203 .Case(S: "ppx", Value: true)
1204 .Case(S: "ndd", Value: true)
1205 .Case(S: "ccmp", Value: true)
1206 .Case(S: "nf", Value: true)
1207 .Case(S: "cf", Value: true)
1208 .Case(S: "zu", Value: true)
1209 .Case(S: "jmpabs", Value: true)
1210 .Default(Value: false);
1211}
1212
1213bool X86TargetInfo::hasFeature(StringRef Feature) const {
1214 return llvm::StringSwitch<bool>(Feature)
1215 .Case(S: "adx", Value: HasADX)
1216 .Case(S: "aes", Value: HasAES)
1217 .Case(S: "amx-avx512", Value: HasAMXAVX512)
1218 .Case(S: "amx-bf16", Value: HasAMXBF16)
1219 .Case(S: "amx-complex", Value: HasAMXCOMPLEX)
1220 .Case(S: "amx-fp16", Value: HasAMXFP16)
1221 .Case(S: "amx-fp8", Value: HasAMXFP8)
1222 .Case(S: "amx-int8", Value: HasAMXINT8)
1223 .Case(S: "amx-movrs", Value: HasAMXMOVRS)
1224 .Case(S: "amx-tile", Value: HasAMXTILE)
1225 .Case(S: "avx", Value: SSELevel >= AVX)
1226 .Case(S: "avx10.1", Value: HasAVX10_1)
1227 .Case(S: "avx10.2", Value: HasAVX10_2)
1228 .Case(S: "avx10v2aux", Value: HasAVX10_V2_AUX)
1229 .Case(S: "avx2", Value: SSELevel >= AVX2)
1230 .Case(S: "avx512f", Value: SSELevel >= AVX512F)
1231 .Case(S: "avx512cd", Value: HasAVX512CD)
1232 .Case(S: "avx512vpopcntdq", Value: HasAVX512VPOPCNTDQ)
1233 .Case(S: "avx512vnni", Value: HasAVX512VNNI)
1234 .Case(S: "avx512bf16", Value: HasAVX512BF16)
1235 .Case(S: "avx512fp16", Value: HasAVX512FP16)
1236 .Case(S: "avx512dq", Value: HasAVX512DQ)
1237 .Case(S: "avx512bitalg", Value: HasAVX512BITALG)
1238 .Case(S: "avx512bmm", Value: HasAVX512BMM)
1239 .Case(S: "avx512bw", Value: HasAVX512BW)
1240 .Case(S: "avx512vl", Value: HasAVX512VL)
1241 .Case(S: "avx512vbmi", Value: HasAVX512VBMI)
1242 .Case(S: "avx512vbmi2", Value: HasAVX512VBMI2)
1243 .Case(S: "avx512ifma", Value: HasAVX512IFMA)
1244 .Case(S: "avx512vp2intersect", Value: HasAVX512VP2INTERSECT)
1245 .Case(S: "avxifma", Value: HasAVXIFMA)
1246 .Case(S: "avxneconvert", Value: HasAVXNECONVERT)
1247 .Case(S: "avxvnni", Value: HasAVXVNNI)
1248 .Case(S: "avxvnniint16", Value: HasAVXVNNIINT16)
1249 .Case(S: "avxvnniint8", Value: HasAVXVNNIINT8)
1250 .Case(S: "bmi", Value: HasBMI)
1251 .Case(S: "bmi2", Value: HasBMI2)
1252 .Case(S: "cldemote", Value: HasCLDEMOTE)
1253 .Case(S: "clflushopt", Value: HasCLFLUSHOPT)
1254 .Case(S: "clwb", Value: HasCLWB)
1255 .Case(S: "clzero", Value: HasCLZERO)
1256 .Case(S: "cmpccxadd", Value: HasCMPCCXADD)
1257 .Case(S: "crc32", Value: HasCRC32)
1258 .Case(S: "cx8", Value: HasCX8)
1259 .Case(S: "cx16", Value: HasCX16)
1260 .Case(S: "enqcmd", Value: HasENQCMD)
1261 .Case(S: "f16c", Value: HasF16C)
1262 .Case(S: "fma", Value: HasFMA)
1263 .Case(S: "fma4", Value: XOPLevel >= FMA4)
1264 .Case(S: "fsgsbase", Value: HasFSGSBASE)
1265 .Case(S: "fxsr", Value: HasFXSR)
1266 .Case(S: "gfni", Value: HasGFNI)
1267 .Case(S: "hreset", Value: HasHRESET)
1268 .Case(S: "invpcid", Value: HasINVPCID)
1269 .Case(S: "kl", Value: HasKL)
1270 .Case(S: "widekl", Value: HasWIDEKL)
1271 .Case(S: "lwp", Value: HasLWP)
1272 .Case(S: "lzcnt", Value: HasLZCNT)
1273 .Case(S: "mmx", Value: HasMMX)
1274 .Case(S: "movbe", Value: HasMOVBE)
1275 .Case(S: "movrs", Value: HasMOVRS)
1276 .Case(S: "movdiri", Value: HasMOVDIRI)
1277 .Case(S: "movdir64b", Value: HasMOVDIR64B)
1278 .Case(S: "mwaitx", Value: HasMWAITX)
1279 .Case(S: "pclmul", Value: HasPCLMUL)
1280 .Case(S: "pconfig", Value: HasPCONFIG)
1281 .Case(S: "pku", Value: HasPKU)
1282 .Case(S: "popcnt", Value: HasPOPCNT)
1283 .Case(S: "prefetchi", Value: HasPREFETCHI)
1284 .Case(S: "prfchw", Value: HasPRFCHW)
1285 .Case(S: "ptwrite", Value: HasPTWRITE)
1286 .Case(S: "raoint", Value: HasRAOINT)
1287 .Case(S: "rdpid", Value: HasRDPID)
1288 .Case(S: "rdpru", Value: HasRDPRU)
1289 .Case(S: "rdrnd", Value: HasRDRND)
1290 .Case(S: "rdseed", Value: HasRDSEED)
1291 .Case(S: "retpoline-external-thunk", Value: HasRetpolineExternalThunk)
1292 .Case(S: "rtm", Value: HasRTM)
1293 .Case(S: "sahf", Value: HasLAHFSAHF)
1294 .Case(S: "serialize", Value: HasSERIALIZE)
1295 .Case(S: "sgx", Value: HasSGX)
1296 .Case(S: "sha", Value: HasSHA)
1297 .Case(S: "sha512", Value: HasSHA512)
1298 .Case(S: "shstk", Value: HasSHSTK)
1299 .Case(S: "sm3", Value: HasSM3)
1300 .Case(S: "sm4", Value: HasSM4)
1301 .Case(S: "sse", Value: SSELevel >= SSE1)
1302 .Case(S: "sse2", Value: SSELevel >= SSE2)
1303 .Case(S: "sse3", Value: SSELevel >= SSE3)
1304 .Case(S: "ssse3", Value: SSELevel >= SSSE3)
1305 .Case(S: "sse4.1", Value: SSELevel >= SSE41)
1306 .Case(S: "sse4.2", Value: SSELevel >= SSE42)
1307 .Case(S: "sse4a", Value: XOPLevel >= SSE4A)
1308 .Case(S: "tbm", Value: HasTBM)
1309 .Case(S: "tsxldtrk", Value: HasTSXLDTRK)
1310 .Case(S: "uintr", Value: HasUINTR)
1311 .Case(S: "usermsr", Value: HasUSERMSR)
1312 .Case(S: "vaes", Value: HasVAES)
1313 .Case(S: "vpclmulqdq", Value: HasVPCLMULQDQ)
1314 .Case(S: "wbnoinvd", Value: HasWBNOINVD)
1315 .Case(S: "waitpkg", Value: HasWAITPKG)
1316 .Case(S: "x86", Value: true)
1317 .Case(S: "x86_32", Value: getTriple().getArch() == llvm::Triple::x86)
1318 .Case(S: "x86_64", Value: getTriple().getArch() == llvm::Triple::x86_64)
1319 .Case(S: "x87", Value: HasX87)
1320 .Case(S: "xop", Value: XOPLevel >= XOP)
1321 .Case(S: "xsave", Value: HasXSAVE)
1322 .Case(S: "xsavec", Value: HasXSAVEC)
1323 .Case(S: "xsaves", Value: HasXSAVES)
1324 .Case(S: "xsaveopt", Value: HasXSAVEOPT)
1325 .Case(S: "fullbf16", Value: HasFullBFloat16)
1326 .Case(S: "egpr", Value: HasEGPR)
1327 .Case(S: "push2pop2", Value: HasPush2Pop2)
1328 .Case(S: "ppx", Value: HasPPX)
1329 .Case(S: "ndd", Value: HasNDD)
1330 .Case(S: "ccmp", Value: HasCCMP)
1331 .Case(S: "nf", Value: HasNF)
1332 .Case(S: "cf", Value: HasCF)
1333 .Case(S: "zu", Value: HasZU)
1334 .Case(S: "jmpabs", Value: HasJMPABS)
1335 .Case(S: "branch-hint", Value: HasBranchHint)
1336 .Default(Value: false);
1337}
1338
1339// We can't use a generic validation scheme for the features accepted here
1340// versus subtarget features accepted in the target attribute because the
1341// bitfield structure that's initialized in the runtime only supports the
1342// below currently rather than the full range of subtarget features. (See
1343// X86TargetInfo::hasFeature for a somewhat comprehensive list).
1344bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1345 return llvm::StringSwitch<bool>(FeatureStr)
1346#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1347#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, true)
1348#include "llvm/TargetParser/X86TargetParser.def"
1349 .Default(Value: false);
1350}
1351
1352static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1353 return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1354#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) \
1355 .Case(STR, llvm::X86::FEATURE_##ENUM)
1356
1357#include "llvm/TargetParser/X86TargetParser.def"
1358 ;
1359 // Note, this function should only be used after ensuring the value is
1360 // correct, so it asserts if the value is out of range.
1361}
1362
1363llvm::APInt X86TargetInfo::getFMVPriority(ArrayRef<StringRef> Features) const {
1364 auto getPriority = [](StringRef Feature) -> unsigned {
1365 // Valid CPUs have a 'key feature' that compares just better than its key
1366 // feature.
1367 using namespace llvm::X86;
1368 CPUKind Kind = parseArchX86(CPU: Feature);
1369 if (Kind != CK_None) {
1370 ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1371 return (getFeaturePriority(Feat: KeyFeature) << 1) + 1;
1372 }
1373 // Now we know we have a feature, so get its priority and shift it a few so
1374 // that we have sufficient room for the CPUs (above).
1375 return getFeaturePriority(Feat: getFeature(Name: Feature)) << 1;
1376 };
1377
1378 unsigned Priority = 0;
1379 for (StringRef Feature : Features)
1380 if (!Feature.empty())
1381 Priority = std::max(a: Priority, b: getPriority(Feature));
1382 return llvm::APInt(32, Priority);
1383}
1384
1385bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1386 return llvm::X86::validateCPUSpecificCPUDispatch(Name);
1387}
1388
1389char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1390 return llvm::X86::getCPUDispatchMangling(Name);
1391}
1392
1393void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1394 StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1395 SmallVector<StringRef, 32> TargetCPUFeatures;
1396 llvm::X86::getFeaturesForCPU(CPU: Name, Features&: TargetCPUFeatures, NeedPlus: true);
1397 for (auto &F : TargetCPUFeatures)
1398 Features.push_back(Elt: F);
1399}
1400
1401// We can't use a generic validation scheme for the cpus accepted here
1402// versus subtarget cpus accepted in the target attribute because the
1403// variables intitialized by the runtime only support the below currently
1404// rather than the full range of cpus.
1405bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1406 return llvm::StringSwitch<bool>(FeatureStr)
1407#define X86_VENDOR(ENUM, STRING, ABI_VALUE) .Case(STRING, true)
1408#define X86_CPU_TYPE(ENUM, STR, ABI_VALUE) .Case(STR, true)
1409#define X86_CPU_SUBTYPE(ENUM, STR, ABI_VALUE) .Case(STR, true)
1410#include "llvm/TargetParser/X86TargetParser.def"
1411 .Default(Value: false);
1412}
1413
1414static unsigned matchAsmCCConstraint(const char *Name) {
1415 auto RV = llvm::StringSwitch<unsigned>(Name)
1416 .Case(S: "@cca", Value: 4)
1417 .Case(S: "@ccae", Value: 5)
1418 .Case(S: "@ccb", Value: 4)
1419 .Case(S: "@ccbe", Value: 5)
1420 .Case(S: "@ccc", Value: 4)
1421 .Case(S: "@cce", Value: 4)
1422 .Case(S: "@ccz", Value: 4)
1423 .Case(S: "@ccg", Value: 4)
1424 .Case(S: "@ccge", Value: 5)
1425 .Case(S: "@ccl", Value: 4)
1426 .Case(S: "@ccle", Value: 5)
1427 .Case(S: "@ccna", Value: 5)
1428 .Case(S: "@ccnae", Value: 6)
1429 .Case(S: "@ccnb", Value: 5)
1430 .Case(S: "@ccnbe", Value: 6)
1431 .Case(S: "@ccnc", Value: 5)
1432 .Case(S: "@ccne", Value: 5)
1433 .Case(S: "@ccnz", Value: 5)
1434 .Case(S: "@ccng", Value: 5)
1435 .Case(S: "@ccnge", Value: 6)
1436 .Case(S: "@ccnl", Value: 5)
1437 .Case(S: "@ccnle", Value: 6)
1438 .Case(S: "@ccno", Value: 5)
1439 .Case(S: "@ccnp", Value: 5)
1440 .Case(S: "@ccns", Value: 5)
1441 .Case(S: "@cco", Value: 4)
1442 .Case(S: "@ccp", Value: 4)
1443 .Case(S: "@ccs", Value: 4)
1444 .Default(Value: 0);
1445 return RV;
1446}
1447
1448bool X86TargetInfo::validateAsmConstraint(
1449 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1450 switch (*Name) {
1451 default:
1452 return false;
1453 // Constant constraints.
1454 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1455 // instructions.
1456 case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1457 // x86_64 instructions.
1458 case 's':
1459 Info.setRequiresImmediate();
1460 return true;
1461 case 'I':
1462 Info.setRequiresImmediate(Min: 0, Max: 31);
1463 return true;
1464 case 'J':
1465 Info.setRequiresImmediate(Min: 0, Max: 63);
1466 return true;
1467 case 'K':
1468 Info.setRequiresImmediate(Min: -128, Max: 127);
1469 return true;
1470 case 'L':
1471 Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1472 return true;
1473 case 'M':
1474 Info.setRequiresImmediate(Min: 0, Max: 3);
1475 return true;
1476 case 'N':
1477 Info.setRequiresImmediate(Min: 0, Max: 255);
1478 return true;
1479 case 'O':
1480 Info.setRequiresImmediate(Min: 0, Max: 127);
1481 return true;
1482 case 'W':
1483 switch (*++Name) {
1484 default:
1485 return false;
1486 case 's':
1487 Info.setAllowsRegister();
1488 return true;
1489 }
1490 // Register constraints.
1491 case 'Y': // 'Y' is the first character for several 2-character constraints.
1492 // Shift the pointer to the second character of the constraint.
1493 Name++;
1494 switch (*Name) {
1495 default:
1496 return false;
1497 case 'z': // First SSE register.
1498 case '2':
1499 case 't': // Any SSE register, when SSE2 is enabled.
1500 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1501 case 'm': // Any MMX register, when inter-unit moves enabled.
1502 case 'k': // AVX512 arch mask registers: k1-k7.
1503 Info.setAllowsRegister();
1504 return true;
1505 }
1506 case 'f': // Any x87 floating point stack register.
1507 // Constraint 'f' cannot be used for output operands.
1508 if (Info.ConstraintStr[0] == '=' || Info.ConstraintStr[0] == '+')
1509 return false;
1510 Info.setAllowsRegister();
1511 return true;
1512 case 'a': // eax.
1513 case 'b': // ebx.
1514 case 'c': // ecx.
1515 case 'd': // edx.
1516 case 'S': // esi.
1517 case 'D': // edi.
1518 case 'A': // edx:eax.
1519 case 't': // Top of floating point stack.
1520 case 'u': // Second from top of floating point stack.
1521 case 'q': // Any register accessible as [r]l: a, b, c, and d.
1522 case 'y': // Any MMX register.
1523 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1524 case 'x': // Any SSE register.
1525 case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1526 // for intermideate k reg operations).
1527 case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1528 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1529 case 'l': // "Index" registers: any general register that can be used as an
1530 // index in a base+index memory access.
1531 Info.setAllowsRegister();
1532 return true;
1533 // Floating point constant constraints.
1534 case 'C': // SSE floating point constant.
1535 case 'G': // x87 floating point constant.
1536 return true;
1537 case 'j':
1538 Name++;
1539 switch (*Name) {
1540 default:
1541 return false;
1542 case 'r':
1543 Info.setAllowsRegister();
1544 return true;
1545 case 'R':
1546 Info.setAllowsRegister();
1547 return true;
1548 }
1549 case '@':
1550 // CC condition changes.
1551 if (auto Len = matchAsmCCConstraint(Name)) {
1552 Name += Len - 1;
1553 Info.setAllowsRegister();
1554 Info.setOutputOperandBounds(Min: 0, Max: 2);
1555 return true;
1556 }
1557 return false;
1558 }
1559}
1560
1561// Below is based on the following information:
1562// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1563// | Processor Name | Cache Line Size (Bytes) | Source |
1564// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1565// | i386 | 64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf |
1566// | i486 | 16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1567// | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX.html |
1568// | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.html |
1569// | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-180.html |
1570// | Atom | 64 | https://www.7-cpu.com/cpu/Atom.html |
1571// | Westmere | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture" |
1572// | Sandy Bridge | 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html |
1573// | Ivy Bridge | 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html |
1574// | Haswell | 64 | https://www.7-cpu.com/cpu/Haswell.html |
1575// | Broadwell | 64 | https://www.7-cpu.com/cpu/Broadwell.html |
1576// | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy" |
1577// | Cascade Lake | 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy" |
1578// | Skylake | 64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy" |
1579// | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_Lake.html |
1580// | Knights Landing | 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1581// | Knights Mill | 64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache " |
1582// +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1583std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1584 using namespace llvm::X86;
1585 switch (CPU) {
1586 // i386
1587 case CK_i386:
1588 // i486
1589 case CK_i486:
1590 case CK_WinChipC6:
1591 case CK_WinChip2:
1592 case CK_C3:
1593 // Lakemont
1594 case CK_Lakemont:
1595 return 16;
1596
1597 // i586
1598 case CK_i586:
1599 case CK_Pentium:
1600 case CK_PentiumMMX:
1601 // i686
1602 case CK_PentiumPro:
1603 case CK_i686:
1604 case CK_Pentium2:
1605 case CK_Pentium3:
1606 case CK_PentiumM:
1607 case CK_C3_2:
1608 // K6
1609 case CK_K6:
1610 case CK_K6_2:
1611 case CK_K6_3:
1612 // Geode
1613 case CK_Geode:
1614 return 32;
1615
1616 // Netburst
1617 case CK_Pentium4:
1618 case CK_Prescott:
1619 case CK_Nocona:
1620 // Atom
1621 case CK_Bonnell:
1622 case CK_Silvermont:
1623 case CK_Goldmont:
1624 case CK_GoldmontPlus:
1625 case CK_Tremont:
1626 case CK_Gracemont:
1627
1628 case CK_Westmere:
1629 case CK_SandyBridge:
1630 case CK_IvyBridge:
1631 case CK_Haswell:
1632 case CK_Broadwell:
1633 case CK_SkylakeClient:
1634 case CK_SkylakeServer:
1635 case CK_Cascadelake:
1636 case CK_Nehalem:
1637 case CK_Cooperlake:
1638 case CK_Cannonlake:
1639 case CK_Tigerlake:
1640 case CK_SapphireRapids:
1641 case CK_IcelakeClient:
1642 case CK_Rocketlake:
1643 case CK_IcelakeServer:
1644 case CK_Alderlake:
1645 case CK_Raptorlake:
1646 case CK_Meteorlake:
1647 case CK_Arrowlake:
1648 case CK_ArrowlakeS:
1649 case CK_Lunarlake:
1650 case CK_Pantherlake:
1651 case CK_Wildcatlake:
1652 case CK_Novalake:
1653 case CK_Sierraforest:
1654 case CK_Grandridge:
1655 case CK_Graniterapids:
1656 case CK_GraniterapidsD:
1657 case CK_Emeraldrapids:
1658 case CK_Clearwaterforest:
1659 case CK_Diamondrapids:
1660 case CK_KNL:
1661 case CK_KNM:
1662 // K7
1663 case CK_Athlon:
1664 case CK_AthlonXP:
1665 // K8
1666 case CK_K8:
1667 case CK_K8SSE3:
1668 case CK_AMDFAM10:
1669 // Bobcat
1670 case CK_BTVER1:
1671 case CK_BTVER2:
1672 // Bulldozer
1673 case CK_BDVER1:
1674 case CK_BDVER2:
1675 case CK_BDVER3:
1676 case CK_BDVER4:
1677 // Zen
1678 case CK_ZNVER1:
1679 case CK_ZNVER2:
1680 case CK_ZNVER3:
1681 case CK_ZNVER4:
1682 case CK_ZNVER5:
1683 case CK_ZNVER6:
1684 // Hygon
1685 case CK_C86_4G_M4:
1686 case CK_C86_4G_M6:
1687 case CK_C86_4G_M7:
1688 case CK_C86_4G_M8:
1689 // Deprecated
1690 case CK_x86_64:
1691 case CK_x86_64_v2:
1692 case CK_x86_64_v3:
1693 case CK_x86_64_v4:
1694 case CK_Yonah:
1695 case CK_Penryn:
1696 case CK_Core2:
1697 return 64;
1698
1699 // The following currently have unknown cache line sizes (but they are probably all 64):
1700 // Core
1701 case CK_None:
1702 return std::nullopt;
1703 }
1704 llvm_unreachable("Unknown CPU kind");
1705}
1706
1707bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1708 StringRef Constraint,
1709 unsigned Size) const {
1710 // Strip off constraint modifiers.
1711 Constraint = Constraint.ltrim(Chars: "=+&");
1712
1713 return validateOperandSize(FeatureMap, Constraint, Size);
1714}
1715
1716bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1717 StringRef Constraint,
1718 unsigned Size) const {
1719 return validateOperandSize(FeatureMap, Constraint, Size);
1720}
1721
1722bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1723 StringRef Constraint,
1724 unsigned Size) const {
1725 switch (Constraint[0]) {
1726 default:
1727 break;
1728 case 'k':
1729 // Registers k0-k7 (AVX512) size limit is 64 bit.
1730 case 'y':
1731 return Size <= 64;
1732 case 'f':
1733 case 't':
1734 case 'u':
1735 return Size <= 128;
1736 case 'Y':
1737 // 'Y' is the first character for several 2-character constraints.
1738 switch (Constraint[1]) {
1739 default:
1740 return false;
1741 case 'm':
1742 // 'Ym' is synonymous with 'y'.
1743 case 'k':
1744 return Size <= 64;
1745 case 'z':
1746 // XMM0/YMM/ZMM0
1747 if (hasFeatureEnabled(Features: FeatureMap, Name: "avx512f"))
1748 // ZMM0 can be used if target supports AVX512F.
1749 return Size <= 512U;
1750 else if (hasFeatureEnabled(Features: FeatureMap, Name: "avx"))
1751 // YMM0 can be used if target supports AVX.
1752 return Size <= 256U;
1753 else if (hasFeatureEnabled(Features: FeatureMap, Name: "sse"))
1754 return Size <= 128U;
1755 return false;
1756 case 'i':
1757 case 't':
1758 case '2':
1759 // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1760 if (SSELevel < SSE2)
1761 return false;
1762 break;
1763 }
1764 break;
1765 case 'v':
1766 case 'x':
1767 if (hasFeatureEnabled(Features: FeatureMap, Name: "avx512f"))
1768 // 512-bit zmm registers can be used if target supports AVX512F.
1769 return Size <= 512U;
1770 else if (hasFeatureEnabled(Features: FeatureMap, Name: "avx"))
1771 // 256-bit ymm registers can be used if target supports AVX.
1772 return Size <= 256U;
1773 return Size <= 128U;
1774
1775 }
1776
1777 return true;
1778}
1779
1780std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1781 switch (*Constraint) {
1782 case '@':
1783 if (auto Len = matchAsmCCConstraint(Name: Constraint)) {
1784 std::string Converted = "{" + std::string(Constraint, Len) + "}";
1785 Constraint += Len - 1;
1786 return Converted;
1787 }
1788 return std::string(1, *Constraint);
1789 case 'a':
1790 return std::string("{ax}");
1791 case 'b':
1792 return std::string("{bx}");
1793 case 'c':
1794 return std::string("{cx}");
1795 case 'd':
1796 return std::string("{dx}");
1797 case 'S':
1798 return std::string("{si}");
1799 case 'D':
1800 return std::string("{di}");
1801 case 'p': // Keep 'p' constraint (address).
1802 return std::string("p");
1803 case 't': // top of floating point stack.
1804 return std::string("{st}");
1805 case 'u': // second from top of floating point stack.
1806 return std::string("{st(1)}"); // second from top of floating point stack.
1807 case 'W':
1808 assert(Constraint[1] == 's');
1809 return '^' + std::string(Constraint++, 2);
1810 case 'Y':
1811 switch (Constraint[1]) {
1812 default:
1813 // Break from inner switch and fall through (copy single char),
1814 // continue parsing after copying the current constraint into
1815 // the return string.
1816 break;
1817 case 'k':
1818 case 'm':
1819 case 'i':
1820 case 't':
1821 case 'z':
1822 case '2':
1823 // "^" hints llvm that this is a 2 letter constraint.
1824 // "Constraint++" is used to promote the string iterator
1825 // to the next constraint.
1826 return std::string("^") + std::string(Constraint++, 2);
1827 }
1828 [[fallthrough]];
1829 case 'j':
1830 switch (Constraint[1]) {
1831 default:
1832 // Break from inner switch and fall through (copy single char),
1833 // continue parsing after copying the current constraint into
1834 // the return string.
1835 break;
1836 case 'r':
1837 case 'R':
1838 // "^" hints llvm that this is a 2 letter constraint.
1839 // "Constraint++" is used to promote the string iterator
1840 // to the next constraint.
1841 return std::string("^") + std::string(Constraint++, 2);
1842 }
1843 [[fallthrough]];
1844 default:
1845 return std::string(1, *Constraint);
1846 }
1847}
1848
1849void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1850 bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1851 llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1852}
1853
1854void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1855 llvm::X86::fillValidTuneCPUList(Values);
1856}
1857
1858ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1859 return llvm::ArrayRef(GCCRegNames);
1860}
1861
1862ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1863 return llvm::ArrayRef(AddlRegNames);
1864}
1865
1866llvm::SmallVector<Builtin::InfosShard>
1867X86_32TargetInfo::getTargetBuiltins() const {
1868 return {
1869 {.Strings: &X86::BuiltinStrings, .Infos: X86::BuiltinInfos},
1870 {.Strings: &X86::BuiltinStrings, .Infos: X86::PrefixedBuiltinInfos, .NamePrefix: "__builtin_ia32_"},
1871 };
1872}
1873
1874llvm::SmallVector<Builtin::InfosShard>
1875X86_64TargetInfo::getTargetBuiltins() const {
1876 return {
1877 {.Strings: &X86::BuiltinStrings, .Infos: X86::BuiltinInfos},
1878 {.Strings: &X86::BuiltinStrings, .Infos: X86::PrefixedBuiltinInfos, .NamePrefix: "__builtin_ia32_"},
1879 {.Strings: &X86_64::BuiltinStrings, .Infos: X86_64::BuiltinInfos},
1880 {.Strings: &X86_64::BuiltinStrings, .Infos: X86_64::PrefixedBuiltinInfos,
1881 .NamePrefix: "__builtin_ia32_"},
1882 };
1883}
1884
1885unsigned
1886MicrosoftX86_64TargetInfo::getMinGlobalAlign(uint64_t TypeSize,
1887 bool HasNonWeakDef) const {
1888 unsigned Align =
1889 WindowsX86_64TargetInfo::getMinGlobalAlign(Size: TypeSize, HasNonWeakDef);
1890
1891 // Skip the MSVC size-based global-alignment increase under
1892 // -fclang-abi-compat<=22.
1893 if (!UseMSVCCompatGlobalAlign)
1894 return Align;
1895
1896 return std::max(a: Align, b: Microsoft64BitMinGlobalAlign(TypeSize));
1897}
1898
1899void MicrosoftX86_64TargetInfo::adjust(DiagnosticsEngine &Diags,
1900 LangOptions &Opts,
1901 const TargetInfo *Aux) {
1902 WindowsX86_64TargetInfo::adjust(Diags, Opts, Aux);
1903 // Under -fclang-abi-compat<=22, restore the prior x86_64-windows-msvc
1904 // behavior: apply the Sys V "large array" alignment increase and skip the
1905 // MSVC size-based global-alignment increase.
1906 if (Opts.isCompatibleWith(Version: LangOptions::ClangABI::Ver22)) {
1907 UseMSVCCompatGlobalAlign = false;
1908 LargeArrayMinWidth = 128;
1909 LargeArrayAlign = 128;
1910 }
1911}
1912