1//===-------- NVPTX.cpp - Emit LLVM Code for builtins ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This contains code to emit Builtin calls as LLVM code.
10//
11//===----------------------------------------------------------------------===//
12
13#include "CGBuiltin.h"
14#include "clang/Basic/TargetBuiltins.h"
15#include "llvm/IR/IntrinsicsNVPTX.h"
16#include "llvm/TargetParser/AtomicScope.h"
17
18using namespace clang;
19using namespace CodeGen;
20using namespace llvm;
21
22namespace {
23// Helper classes for mapping MMA builtins to particular LLVM intrinsic variant.
24struct NVPTXMmaLdstInfo {
25 unsigned NumResults; // Number of elements to load/store
26 // Intrinsic IDs for row/col variants. 0 if particular layout is unsupported.
27 unsigned IID_col;
28 unsigned IID_row;
29};
30
31#define MMA_INTR(geom_op_type, layout) \
32 Intrinsic::nvvm_wmma_##geom_op_type##_##layout##_stride
33#define MMA_LDST(n, geom_op_type) \
34 { n, MMA_INTR(geom_op_type, col), MMA_INTR(geom_op_type, row) }
35
36static NVPTXMmaLdstInfo getNVPTXMmaLdstInfo(unsigned BuiltinID) {
37 switch (BuiltinID) {
38 // FP MMA loads
39 case NVPTX::BI__hmma_m16n16k16_ld_a:
40 return MMA_LDST(8, m16n16k16_load_a_f16);
41 case NVPTX::BI__hmma_m16n16k16_ld_b:
42 return MMA_LDST(8, m16n16k16_load_b_f16);
43 case NVPTX::BI__hmma_m16n16k16_ld_c_f16:
44 return MMA_LDST(4, m16n16k16_load_c_f16);
45 case NVPTX::BI__hmma_m16n16k16_ld_c_f32:
46 return MMA_LDST(8, m16n16k16_load_c_f32);
47 case NVPTX::BI__hmma_m32n8k16_ld_a:
48 return MMA_LDST(8, m32n8k16_load_a_f16);
49 case NVPTX::BI__hmma_m32n8k16_ld_b:
50 return MMA_LDST(8, m32n8k16_load_b_f16);
51 case NVPTX::BI__hmma_m32n8k16_ld_c_f16:
52 return MMA_LDST(4, m32n8k16_load_c_f16);
53 case NVPTX::BI__hmma_m32n8k16_ld_c_f32:
54 return MMA_LDST(8, m32n8k16_load_c_f32);
55 case NVPTX::BI__hmma_m8n32k16_ld_a:
56 return MMA_LDST(8, m8n32k16_load_a_f16);
57 case NVPTX::BI__hmma_m8n32k16_ld_b:
58 return MMA_LDST(8, m8n32k16_load_b_f16);
59 case NVPTX::BI__hmma_m8n32k16_ld_c_f16:
60 return MMA_LDST(4, m8n32k16_load_c_f16);
61 case NVPTX::BI__hmma_m8n32k16_ld_c_f32:
62 return MMA_LDST(8, m8n32k16_load_c_f32);
63
64 // Integer MMA loads
65 case NVPTX::BI__imma_m16n16k16_ld_a_s8:
66 return MMA_LDST(2, m16n16k16_load_a_s8);
67 case NVPTX::BI__imma_m16n16k16_ld_a_u8:
68 return MMA_LDST(2, m16n16k16_load_a_u8);
69 case NVPTX::BI__imma_m16n16k16_ld_b_s8:
70 return MMA_LDST(2, m16n16k16_load_b_s8);
71 case NVPTX::BI__imma_m16n16k16_ld_b_u8:
72 return MMA_LDST(2, m16n16k16_load_b_u8);
73 case NVPTX::BI__imma_m16n16k16_ld_c:
74 return MMA_LDST(8, m16n16k16_load_c_s32);
75 case NVPTX::BI__imma_m32n8k16_ld_a_s8:
76 return MMA_LDST(4, m32n8k16_load_a_s8);
77 case NVPTX::BI__imma_m32n8k16_ld_a_u8:
78 return MMA_LDST(4, m32n8k16_load_a_u8);
79 case NVPTX::BI__imma_m32n8k16_ld_b_s8:
80 return MMA_LDST(1, m32n8k16_load_b_s8);
81 case NVPTX::BI__imma_m32n8k16_ld_b_u8:
82 return MMA_LDST(1, m32n8k16_load_b_u8);
83 case NVPTX::BI__imma_m32n8k16_ld_c:
84 return MMA_LDST(8, m32n8k16_load_c_s32);
85 case NVPTX::BI__imma_m8n32k16_ld_a_s8:
86 return MMA_LDST(1, m8n32k16_load_a_s8);
87 case NVPTX::BI__imma_m8n32k16_ld_a_u8:
88 return MMA_LDST(1, m8n32k16_load_a_u8);
89 case NVPTX::BI__imma_m8n32k16_ld_b_s8:
90 return MMA_LDST(4, m8n32k16_load_b_s8);
91 case NVPTX::BI__imma_m8n32k16_ld_b_u8:
92 return MMA_LDST(4, m8n32k16_load_b_u8);
93 case NVPTX::BI__imma_m8n32k16_ld_c:
94 return MMA_LDST(8, m8n32k16_load_c_s32);
95
96 // Sub-integer MMA loads.
97 // Only row/col layout is supported by A/B fragments.
98 case NVPTX::BI__imma_m8n8k32_ld_a_s4:
99 return {.NumResults: 1, .IID_col: 0, MMA_INTR(m8n8k32_load_a_s4, row)};
100 case NVPTX::BI__imma_m8n8k32_ld_a_u4:
101 return {.NumResults: 1, .IID_col: 0, MMA_INTR(m8n8k32_load_a_u4, row)};
102 case NVPTX::BI__imma_m8n8k32_ld_b_s4:
103 return {.NumResults: 1, MMA_INTR(m8n8k32_load_b_s4, col), .IID_row: 0};
104 case NVPTX::BI__imma_m8n8k32_ld_b_u4:
105 return {.NumResults: 1, MMA_INTR(m8n8k32_load_b_u4, col), .IID_row: 0};
106 case NVPTX::BI__imma_m8n8k32_ld_c:
107 return MMA_LDST(2, m8n8k32_load_c_s32);
108 case NVPTX::BI__bmma_m8n8k128_ld_a_b1:
109 return {.NumResults: 1, .IID_col: 0, MMA_INTR(m8n8k128_load_a_b1, row)};
110 case NVPTX::BI__bmma_m8n8k128_ld_b_b1:
111 return {.NumResults: 1, MMA_INTR(m8n8k128_load_b_b1, col), .IID_row: 0};
112 case NVPTX::BI__bmma_m8n8k128_ld_c:
113 return MMA_LDST(2, m8n8k128_load_c_s32);
114
115 // Double MMA loads
116 case NVPTX::BI__dmma_m8n8k4_ld_a:
117 return MMA_LDST(1, m8n8k4_load_a_f64);
118 case NVPTX::BI__dmma_m8n8k4_ld_b:
119 return MMA_LDST(1, m8n8k4_load_b_f64);
120 case NVPTX::BI__dmma_m8n8k4_ld_c:
121 return MMA_LDST(2, m8n8k4_load_c_f64);
122
123 // Alternate float MMA loads
124 case NVPTX::BI__mma_bf16_m16n16k16_ld_a:
125 return MMA_LDST(4, m16n16k16_load_a_bf16);
126 case NVPTX::BI__mma_bf16_m16n16k16_ld_b:
127 return MMA_LDST(4, m16n16k16_load_b_bf16);
128 case NVPTX::BI__mma_bf16_m8n32k16_ld_a:
129 return MMA_LDST(2, m8n32k16_load_a_bf16);
130 case NVPTX::BI__mma_bf16_m8n32k16_ld_b:
131 return MMA_LDST(8, m8n32k16_load_b_bf16);
132 case NVPTX::BI__mma_bf16_m32n8k16_ld_a:
133 return MMA_LDST(8, m32n8k16_load_a_bf16);
134 case NVPTX::BI__mma_bf16_m32n8k16_ld_b:
135 return MMA_LDST(2, m32n8k16_load_b_bf16);
136 case NVPTX::BI__mma_tf32_m16n16k8_ld_a:
137 return MMA_LDST(4, m16n16k8_load_a_tf32);
138 case NVPTX::BI__mma_tf32_m16n16k8_ld_b:
139 return MMA_LDST(4, m16n16k8_load_b_tf32);
140 case NVPTX::BI__mma_tf32_m16n16k8_ld_c:
141 return MMA_LDST(8, m16n16k8_load_c_f32);
142
143 // NOTE: We need to follow inconsitent naming scheme used by NVCC. Unlike
144 // PTX and LLVM IR where stores always use fragment D, NVCC builtins always
145 // use fragment C for both loads and stores.
146 // FP MMA stores.
147 case NVPTX::BI__hmma_m16n16k16_st_c_f16:
148 return MMA_LDST(4, m16n16k16_store_d_f16);
149 case NVPTX::BI__hmma_m16n16k16_st_c_f32:
150 return MMA_LDST(8, m16n16k16_store_d_f32);
151 case NVPTX::BI__hmma_m32n8k16_st_c_f16:
152 return MMA_LDST(4, m32n8k16_store_d_f16);
153 case NVPTX::BI__hmma_m32n8k16_st_c_f32:
154 return MMA_LDST(8, m32n8k16_store_d_f32);
155 case NVPTX::BI__hmma_m8n32k16_st_c_f16:
156 return MMA_LDST(4, m8n32k16_store_d_f16);
157 case NVPTX::BI__hmma_m8n32k16_st_c_f32:
158 return MMA_LDST(8, m8n32k16_store_d_f32);
159
160 // Integer and sub-integer MMA stores.
161 // Another naming quirk. Unlike other MMA builtins that use PTX types in the
162 // name, integer loads/stores use LLVM's i32.
163 case NVPTX::BI__imma_m16n16k16_st_c_i32:
164 return MMA_LDST(8, m16n16k16_store_d_s32);
165 case NVPTX::BI__imma_m32n8k16_st_c_i32:
166 return MMA_LDST(8, m32n8k16_store_d_s32);
167 case NVPTX::BI__imma_m8n32k16_st_c_i32:
168 return MMA_LDST(8, m8n32k16_store_d_s32);
169 case NVPTX::BI__imma_m8n8k32_st_c_i32:
170 return MMA_LDST(2, m8n8k32_store_d_s32);
171 case NVPTX::BI__bmma_m8n8k128_st_c_i32:
172 return MMA_LDST(2, m8n8k128_store_d_s32);
173
174 // Double MMA store
175 case NVPTX::BI__dmma_m8n8k4_st_c_f64:
176 return MMA_LDST(2, m8n8k4_store_d_f64);
177
178 // Alternate float MMA store
179 case NVPTX::BI__mma_m16n16k8_st_c_f32:
180 return MMA_LDST(8, m16n16k8_store_d_f32);
181
182 default:
183 llvm_unreachable("Unknown MMA builtin");
184 }
185}
186#undef MMA_LDST
187#undef MMA_INTR
188
189
190struct NVPTXMmaInfo {
191 unsigned NumEltsA;
192 unsigned NumEltsB;
193 unsigned NumEltsC;
194 unsigned NumEltsD;
195
196 // Variants are ordered by layout-A/layout-B/satf, where 'row' has priority
197 // over 'col' for layout. The index of non-satf variants is expected to match
198 // the undocumented layout constants used by CUDA's mma.hpp.
199 std::array<unsigned, 8> Variants;
200
201 unsigned getMMAIntrinsic(int Layout, bool Satf) {
202 unsigned Index = Layout + 4 * Satf;
203 if (Index >= Variants.size())
204 return 0;
205 return Variants[Index];
206 }
207};
208
209 // Returns an intrinsic that matches Layout and Satf for valid combinations of
210 // Layout and Satf, 0 otherwise.
211static NVPTXMmaInfo getNVPTXMmaInfo(unsigned BuiltinID) {
212 // clang-format off
213#define MMA_VARIANTS(geom, type) \
214 Intrinsic::nvvm_wmma_##geom##_mma_row_row_##type, \
215 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type, \
216 Intrinsic::nvvm_wmma_##geom##_mma_col_row_##type, \
217 Intrinsic::nvvm_wmma_##geom##_mma_col_col_##type
218#define MMA_SATF_VARIANTS(geom, type) \
219 MMA_VARIANTS(geom, type), \
220 Intrinsic::nvvm_wmma_##geom##_mma_row_row_##type##_satfinite, \
221 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type##_satfinite, \
222 Intrinsic::nvvm_wmma_##geom##_mma_col_row_##type##_satfinite, \
223 Intrinsic::nvvm_wmma_##geom##_mma_col_col_##type##_satfinite
224// Sub-integer MMA only supports row.col layout.
225#define MMA_VARIANTS_I4(geom, type) \
226 0, \
227 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type, \
228 0, \
229 0, \
230 0, \
231 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type##_satfinite, \
232 0, \
233 0
234// b1 MMA does not support .satfinite.
235#define MMA_VARIANTS_B1_XOR(geom, type) \
236 0, \
237 Intrinsic::nvvm_wmma_##geom##_mma_xor_popc_row_col_##type, \
238 0, \
239 0, \
240 0, \
241 0, \
242 0, \
243 0
244#define MMA_VARIANTS_B1_AND(geom, type) \
245 0, \
246 Intrinsic::nvvm_wmma_##geom##_mma_and_popc_row_col_##type, \
247 0, \
248 0, \
249 0, \
250 0, \
251 0, \
252 0
253 // clang-format on
254 switch (BuiltinID) {
255 // FP MMA
256 // Note that 'type' argument of MMA_SATF_VARIANTS uses D_C notation, while
257 // NumEltsN of return value are ordered as A,B,C,D.
258 case NVPTX::BI__hmma_m16n16k16_mma_f16f16:
259 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 4, .NumEltsD: 4, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m16n16k16, f16_f16)}}};
260 case NVPTX::BI__hmma_m16n16k16_mma_f32f16:
261 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 4, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m16n16k16, f32_f16)}}};
262 case NVPTX::BI__hmma_m16n16k16_mma_f16f32:
263 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 8, .NumEltsD: 4, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m16n16k16, f16_f32)}}};
264 case NVPTX::BI__hmma_m16n16k16_mma_f32f32:
265 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m16n16k16, f32_f32)}}};
266 case NVPTX::BI__hmma_m32n8k16_mma_f16f16:
267 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 4, .NumEltsD: 4, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m32n8k16, f16_f16)}}};
268 case NVPTX::BI__hmma_m32n8k16_mma_f32f16:
269 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 4, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m32n8k16, f32_f16)}}};
270 case NVPTX::BI__hmma_m32n8k16_mma_f16f32:
271 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 8, .NumEltsD: 4, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m32n8k16, f16_f32)}}};
272 case NVPTX::BI__hmma_m32n8k16_mma_f32f32:
273 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m32n8k16, f32_f32)}}};
274 case NVPTX::BI__hmma_m8n32k16_mma_f16f16:
275 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 4, .NumEltsD: 4, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m8n32k16, f16_f16)}}};
276 case NVPTX::BI__hmma_m8n32k16_mma_f32f16:
277 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 4, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m8n32k16, f32_f16)}}};
278 case NVPTX::BI__hmma_m8n32k16_mma_f16f32:
279 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 8, .NumEltsD: 4, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m8n32k16, f16_f32)}}};
280 case NVPTX::BI__hmma_m8n32k16_mma_f32f32:
281 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m8n32k16, f32_f32)}}};
282
283 // Integer MMA
284 case NVPTX::BI__imma_m16n16k16_mma_s8:
285 return {.NumEltsA: 2, .NumEltsB: 2, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m16n16k16, s8)}}};
286 case NVPTX::BI__imma_m16n16k16_mma_u8:
287 return {.NumEltsA: 2, .NumEltsB: 2, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m16n16k16, u8)}}};
288 case NVPTX::BI__imma_m32n8k16_mma_s8:
289 return {.NumEltsA: 4, .NumEltsB: 1, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m32n8k16, s8)}}};
290 case NVPTX::BI__imma_m32n8k16_mma_u8:
291 return {.NumEltsA: 4, .NumEltsB: 1, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m32n8k16, u8)}}};
292 case NVPTX::BI__imma_m8n32k16_mma_s8:
293 return {.NumEltsA: 1, .NumEltsB: 4, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m8n32k16, s8)}}};
294 case NVPTX::BI__imma_m8n32k16_mma_u8:
295 return {.NumEltsA: 1, .NumEltsB: 4, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m8n32k16, u8)}}};
296
297 // Sub-integer MMA
298 case NVPTX::BI__imma_m8n8k32_mma_s4:
299 return {.NumEltsA: 1, .NumEltsB: 1, .NumEltsC: 2, .NumEltsD: 2, .Variants: {._M_elems: {MMA_VARIANTS_I4(m8n8k32, s4)}}};
300 case NVPTX::BI__imma_m8n8k32_mma_u4:
301 return {.NumEltsA: 1, .NumEltsB: 1, .NumEltsC: 2, .NumEltsD: 2, .Variants: {._M_elems: {MMA_VARIANTS_I4(m8n8k32, u4)}}};
302 case NVPTX::BI__bmma_m8n8k128_mma_xor_popc_b1:
303 return {.NumEltsA: 1, .NumEltsB: 1, .NumEltsC: 2, .NumEltsD: 2, .Variants: {._M_elems: {MMA_VARIANTS_B1_XOR(m8n8k128, b1)}}};
304 case NVPTX::BI__bmma_m8n8k128_mma_and_popc_b1:
305 return {.NumEltsA: 1, .NumEltsB: 1, .NumEltsC: 2, .NumEltsD: 2, .Variants: {._M_elems: {MMA_VARIANTS_B1_AND(m8n8k128, b1)}}};
306
307 // Double MMA
308 case NVPTX::BI__dmma_m8n8k4_mma_f64:
309 return {.NumEltsA: 1, .NumEltsB: 1, .NumEltsC: 2, .NumEltsD: 2, .Variants: {._M_elems: {MMA_VARIANTS(m8n8k4, f64)}}};
310
311 // Alternate FP MMA
312 case NVPTX::BI__mma_bf16_m16n16k16_mma_f32:
313 return {.NumEltsA: 4, .NumEltsB: 4, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_VARIANTS(m16n16k16, bf16)}}};
314 case NVPTX::BI__mma_bf16_m8n32k16_mma_f32:
315 return {.NumEltsA: 2, .NumEltsB: 8, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_VARIANTS(m8n32k16, bf16)}}};
316 case NVPTX::BI__mma_bf16_m32n8k16_mma_f32:
317 return {.NumEltsA: 8, .NumEltsB: 2, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_VARIANTS(m32n8k16, bf16)}}};
318 case NVPTX::BI__mma_tf32_m16n16k8_mma_f32:
319 return {.NumEltsA: 4, .NumEltsB: 4, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_VARIANTS(m16n16k8, tf32)}}};
320 default:
321 llvm_unreachable("Unexpected builtin ID.");
322 }
323#undef MMA_VARIANTS
324#undef MMA_SATF_VARIANTS
325#undef MMA_VARIANTS_I4
326#undef MMA_VARIANTS_B1_AND
327#undef MMA_VARIANTS_B1_XOR
328}
329
330static Value *MakeLdu(unsigned IntrinsicID, CodeGenFunction &CGF,
331 const CallExpr *E) {
332 Value *Ptr = CGF.EmitScalarExpr(E: E->getArg(Arg: 0));
333 QualType ArgType = E->getArg(Arg: 0)->getType();
334 clang::CharUnits Align = CGF.CGM.getNaturalPointeeTypeAlignment(T: ArgType);
335 llvm::Type *ElemTy = CGF.ConvertTypeForMem(T: ArgType->getPointeeType());
336 return CGF.Builder.CreateCall(
337 Callee: CGF.CGM.getIntrinsic(IID: IntrinsicID, Tys: {ElemTy, Ptr->getType()}),
338 Args: {Ptr, ConstantInt::get(Ty: CGF.Builder.getInt32Ty(), V: Align.getQuantity())});
339}
340
341static Value *MakeLdg(CodeGenFunction &CGF, const CallExpr *E) {
342 Value *Ptr = CGF.EmitScalarExpr(E: E->getArg(Arg: 0));
343 QualType ArgType = E->getArg(Arg: 0)->getType();
344 clang::CharUnits AlignV = CGF.CGM.getNaturalPointeeTypeAlignment(T: ArgType);
345 llvm::Type *ElemTy = CGF.ConvertTypeForMem(T: ArgType->getPointeeType());
346
347 // Use addrspace(1) for NVPTX ADDRESS_SPACE_GLOBAL
348 auto *ASC = CGF.Builder.CreateAddrSpaceCast(V: Ptr, DestTy: CGF.Builder.getPtrTy(AddrSpace: 1));
349 auto *LD = CGF.Builder.CreateAlignedLoad(Ty: ElemTy, Ptr: ASC, Align: AlignV.getAsAlign());
350 MDNode *MD = MDNode::get(Context&: CGF.Builder.getContext(), MDs: {});
351 LD->setMetadata(KindID: LLVMContext::MD_invariant_load, Node: MD);
352
353 return LD;
354}
355
356// `Scope` is AtomicScope::Workgroup for _cta builtins and AtomicScope::System
357// for _sys builtins.
358static Value *MakeScopedAtomicRMW(CodeGenFunction &CGF, const CallExpr *E,
359 llvm::AtomicRMWInst::BinOp Kind,
360 llvm::AtomicScope Scope) {
361 Address Ptr = CGF.EmitPointerWithAlignment(Addr: E->getArg(Arg: 0));
362 Value *Val = CGF.EmitScalarExpr(E: E->getArg(Arg: 1));
363 llvm::SyncScope::ID SSID = CGF.getLLVMContext().getOrInsertSyncScopeID(
364 SSN: *llvm::getAtomicScopeIRString(T: CGF.getTarget().getTriple(), S: Scope));
365 return CGF.Builder.CreateAtomicRMW(Op: Kind, Addr: Ptr, Val,
366 Ordering: llvm::AtomicOrdering::Monotonic, SSID);
367}
368
369// `Scope` is AtomicScope::Workgroup for _cta builtins and AtomicScope::System
370// for _sys builtins.
371static Value *MakeScopedAtomicCAS(CodeGenFunction &CGF, const CallExpr *E,
372 llvm::AtomicScope Scope) {
373 Address Ptr = CGF.EmitPointerWithAlignment(Addr: E->getArg(Arg: 0));
374 Value *Cmp = CGF.EmitScalarExpr(E: E->getArg(Arg: 1));
375 Value *New = CGF.EmitScalarExpr(E: E->getArg(Arg: 2));
376 llvm::SyncScope::ID SSID = CGF.getLLVMContext().getOrInsertSyncScopeID(
377 SSN: *llvm::getAtomicScopeIRString(T: CGF.getTarget().getTriple(), S: Scope));
378 Value *Pair = CGF.Builder.CreateAtomicCmpXchg(
379 Addr: Ptr, Cmp, New, SuccessOrdering: llvm::AtomicOrdering::Monotonic,
380 FailureOrdering: llvm::AtomicOrdering::Monotonic, SSID);
381 return CGF.Builder.CreateExtractValue(Agg: Pair, Idxs: 0);
382}
383
384static Value *MakeCpAsync(unsigned IntrinsicID, unsigned IntrinsicIDS,
385 CodeGenFunction &CGF, const CallExpr *E,
386 int SrcSize) {
387 return E->getNumArgs() == 3
388 ? CGF.Builder.CreateCall(Callee: CGF.CGM.getIntrinsic(IID: IntrinsicIDS),
389 Args: {CGF.EmitScalarExpr(E: E->getArg(Arg: 0)),
390 CGF.EmitScalarExpr(E: E->getArg(Arg: 1)),
391 CGF.EmitScalarExpr(E: E->getArg(Arg: 2))})
392 : CGF.Builder.CreateCall(Callee: CGF.CGM.getIntrinsic(IID: IntrinsicID),
393 Args: {CGF.EmitScalarExpr(E: E->getArg(Arg: 0)),
394 CGF.EmitScalarExpr(E: E->getArg(Arg: 1))});
395}
396
397static Value *MakeHalfType(Function *Intrinsic, unsigned BuiltinID,
398 const CallExpr *E, CodeGenFunction &CGF,
399 ArrayRef<Value *> TrailingArgs = {}) {
400 SmallVector<Value *, 16> Args;
401 auto *FTy = Intrinsic->getFunctionType();
402 unsigned ICEArguments = 0;
403 ASTContext::GetBuiltinTypeError Error;
404 CGF.CGM.getContext().GetBuiltinType(ID: BuiltinID, Error, IntegerConstantArgs: &ICEArguments);
405 assert(Error == ASTContext::GE_None && "Should not codegen an error");
406 for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
407 assert((ICEArguments & (1 << i)) == 0);
408 auto *ArgValue = CGF.EmitScalarExpr(E: E->getArg(Arg: i));
409 auto *PTy = FTy->getParamType(i);
410 if (PTy != ArgValue->getType())
411 ArgValue = CGF.Builder.CreateBitCast(V: ArgValue, DestTy: PTy);
412 Args.push_back(Elt: ArgValue);
413 }
414
415 llvm::append_range(C&: Args, R&: TrailingArgs);
416 appendDefaultIntrinsicArgs(Args, F: Intrinsic);
417
418 return CGF.Builder.CreateCall(Callee: Intrinsic, Args);
419}
420
421static Value *MakeHalfType(unsigned IntrinsicID, unsigned BuiltinID,
422 const CallExpr *E, CodeGenFunction &CGF,
423 ArrayRef<Value *> TrailingArgs = {}) {
424 return MakeHalfType(Intrinsic: CGF.CGM.getIntrinsic(IID: IntrinsicID), BuiltinID, E, CGF,
425 TrailingArgs);
426}
427
428static Value *MakeFMAOOB(unsigned IntrinsicID, llvm::Type *Ty,
429 const CallExpr *E, CodeGenFunction &CGF) {
430 return CGF.Builder.CreateCall(Callee: CGF.CGM.getIntrinsic(IID: IntrinsicID, Tys: {Ty}),
431 Args: {CGF.EmitScalarExpr(E: E->getArg(Arg: 0)),
432 CGF.EmitScalarExpr(E: E->getArg(Arg: 1)),
433 CGF.EmitScalarExpr(E: E->getArg(Arg: 2))});
434}
435
436static Value *MakeFAdd(unsigned IntrinsicID, APFloat::roundingMode RM,
437 unsigned BuiltinID, const CallExpr *E,
438 CodeGenFunction &CGF) {
439 llvm::Type *Ty = CGF.ConvertType(T: E->getType());
440 return MakeHalfType(Intrinsic: CGF.CGM.getIntrinsic(IID: IntrinsicID, Tys: Ty), BuiltinID, E, CGF,
441 TrailingArgs: {CGF.Builder.getInt32(C: static_cast<int>(RM))});
442}
443
444} // namespace
445
446Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
447 const CallExpr *E) {
448 switch (BuiltinID) {
449 case NVPTX::BI__nvvm_atom_add_gen_i:
450 case NVPTX::BI__nvvm_atom_add_gen_l:
451 case NVPTX::BI__nvvm_atom_add_gen_ll:
452 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::Add, E,
453 Ordering: AtomicOrdering::Monotonic);
454
455 case NVPTX::BI__nvvm_atom_sub_gen_i:
456 case NVPTX::BI__nvvm_atom_sub_gen_l:
457 case NVPTX::BI__nvvm_atom_sub_gen_ll:
458 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::Sub, E,
459 Ordering: AtomicOrdering::Monotonic);
460
461 case NVPTX::BI__nvvm_atom_and_gen_i:
462 case NVPTX::BI__nvvm_atom_and_gen_l:
463 case NVPTX::BI__nvvm_atom_and_gen_ll:
464 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::And, E,
465 Ordering: AtomicOrdering::Monotonic);
466
467 case NVPTX::BI__nvvm_atom_or_gen_i:
468 case NVPTX::BI__nvvm_atom_or_gen_l:
469 case NVPTX::BI__nvvm_atom_or_gen_ll:
470 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::Or, E,
471 Ordering: AtomicOrdering::Monotonic);
472
473 case NVPTX::BI__nvvm_atom_xor_gen_i:
474 case NVPTX::BI__nvvm_atom_xor_gen_l:
475 case NVPTX::BI__nvvm_atom_xor_gen_ll:
476 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::Xor, E,
477 Ordering: AtomicOrdering::Monotonic);
478
479 case NVPTX::BI__nvvm_atom_xchg_gen_i:
480 case NVPTX::BI__nvvm_atom_xchg_gen_l:
481 case NVPTX::BI__nvvm_atom_xchg_gen_ll:
482 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::Xchg, E,
483 Ordering: AtomicOrdering::Monotonic);
484
485 case NVPTX::BI__nvvm_atom_max_gen_i:
486 case NVPTX::BI__nvvm_atom_max_gen_l:
487 case NVPTX::BI__nvvm_atom_max_gen_ll:
488 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::Max, E,
489 Ordering: AtomicOrdering::Monotonic);
490
491 case NVPTX::BI__nvvm_atom_max_gen_ui:
492 case NVPTX::BI__nvvm_atom_max_gen_ul:
493 case NVPTX::BI__nvvm_atom_max_gen_ull:
494 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::UMax, E,
495 Ordering: AtomicOrdering::Monotonic);
496
497 case NVPTX::BI__nvvm_atom_min_gen_i:
498 case NVPTX::BI__nvvm_atom_min_gen_l:
499 case NVPTX::BI__nvvm_atom_min_gen_ll:
500 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::Min, E,
501 Ordering: AtomicOrdering::Monotonic);
502
503 case NVPTX::BI__nvvm_atom_min_gen_ui:
504 case NVPTX::BI__nvvm_atom_min_gen_ul:
505 case NVPTX::BI__nvvm_atom_min_gen_ull:
506 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::UMin, E,
507 Ordering: AtomicOrdering::Monotonic);
508
509 case NVPTX::BI__nvvm_atom_cas_gen_us:
510 case NVPTX::BI__nvvm_atom_cas_gen_i:
511 case NVPTX::BI__nvvm_atom_cas_gen_l:
512 case NVPTX::BI__nvvm_atom_cas_gen_ll:
513 // __nvvm_atom_cas_gen_* should return the old value rather than the
514 // success flag.
515 return MakeAtomicCmpXchgValue(CGF&: *this, E, /*ReturnBool=*/false,
516 SuccessOrdering: AtomicOrdering::Monotonic,
517 FailureOrdering: AtomicOrdering::Monotonic);
518
519 case NVPTX::BI__nvvm_atom_add_gen_f:
520 case NVPTX::BI__nvvm_atom_add_gen_d: {
521 Address DestAddr = EmitPointerWithAlignment(Addr: E->getArg(Arg: 0));
522 Value *Val = EmitScalarExpr(E: E->getArg(Arg: 1));
523
524 return Builder.CreateAtomicRMW(Op: llvm::AtomicRMWInst::FAdd, Addr: DestAddr, Val,
525 Ordering: AtomicOrdering::Monotonic);
526 }
527
528 case NVPTX::BI__nvvm_atom_inc_gen_ui:
529 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::UIncWrap, E,
530 Ordering: AtomicOrdering::Monotonic);
531
532 case NVPTX::BI__nvvm_atom_dec_gen_ui:
533 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::UDecWrap, E,
534 Ordering: AtomicOrdering::Monotonic);
535
536 case NVPTX::BI__nvvm_ldg_c:
537 case NVPTX::BI__nvvm_ldg_sc:
538 case NVPTX::BI__nvvm_ldg_c2:
539 case NVPTX::BI__nvvm_ldg_sc2:
540 case NVPTX::BI__nvvm_ldg_c4:
541 case NVPTX::BI__nvvm_ldg_sc4:
542 case NVPTX::BI__nvvm_ldg_s:
543 case NVPTX::BI__nvvm_ldg_s2:
544 case NVPTX::BI__nvvm_ldg_s4:
545 case NVPTX::BI__nvvm_ldg_i:
546 case NVPTX::BI__nvvm_ldg_i2:
547 case NVPTX::BI__nvvm_ldg_i4:
548 case NVPTX::BI__nvvm_ldg_l:
549 case NVPTX::BI__nvvm_ldg_l2:
550 case NVPTX::BI__nvvm_ldg_ll:
551 case NVPTX::BI__nvvm_ldg_ll2:
552 case NVPTX::BI__nvvm_ldg_uc:
553 case NVPTX::BI__nvvm_ldg_uc2:
554 case NVPTX::BI__nvvm_ldg_uc4:
555 case NVPTX::BI__nvvm_ldg_us:
556 case NVPTX::BI__nvvm_ldg_us2:
557 case NVPTX::BI__nvvm_ldg_us4:
558 case NVPTX::BI__nvvm_ldg_ui:
559 case NVPTX::BI__nvvm_ldg_ui2:
560 case NVPTX::BI__nvvm_ldg_ui4:
561 case NVPTX::BI__nvvm_ldg_ul:
562 case NVPTX::BI__nvvm_ldg_ul2:
563 case NVPTX::BI__nvvm_ldg_ull:
564 case NVPTX::BI__nvvm_ldg_ull2:
565 case NVPTX::BI__nvvm_ldg_f:
566 case NVPTX::BI__nvvm_ldg_f2:
567 case NVPTX::BI__nvvm_ldg_f4:
568 case NVPTX::BI__nvvm_ldg_d:
569 case NVPTX::BI__nvvm_ldg_d2:
570 // PTX Interoperability section 2.2: "For a vector with an even number of
571 // elements, its alignment is set to number of elements times the alignment
572 // of its member: n*alignof(t)."
573 return MakeLdg(CGF&: *this, E);
574
575 case NVPTX::BI__nvvm_ldu_c:
576 case NVPTX::BI__nvvm_ldu_sc:
577 case NVPTX::BI__nvvm_ldu_c2:
578 case NVPTX::BI__nvvm_ldu_sc2:
579 case NVPTX::BI__nvvm_ldu_c4:
580 case NVPTX::BI__nvvm_ldu_sc4:
581 case NVPTX::BI__nvvm_ldu_s:
582 case NVPTX::BI__nvvm_ldu_s2:
583 case NVPTX::BI__nvvm_ldu_s4:
584 case NVPTX::BI__nvvm_ldu_i:
585 case NVPTX::BI__nvvm_ldu_i2:
586 case NVPTX::BI__nvvm_ldu_i4:
587 case NVPTX::BI__nvvm_ldu_l:
588 case NVPTX::BI__nvvm_ldu_l2:
589 case NVPTX::BI__nvvm_ldu_ll:
590 case NVPTX::BI__nvvm_ldu_ll2:
591 case NVPTX::BI__nvvm_ldu_uc:
592 case NVPTX::BI__nvvm_ldu_uc2:
593 case NVPTX::BI__nvvm_ldu_uc4:
594 case NVPTX::BI__nvvm_ldu_us:
595 case NVPTX::BI__nvvm_ldu_us2:
596 case NVPTX::BI__nvvm_ldu_us4:
597 case NVPTX::BI__nvvm_ldu_ui:
598 case NVPTX::BI__nvvm_ldu_ui2:
599 case NVPTX::BI__nvvm_ldu_ui4:
600 case NVPTX::BI__nvvm_ldu_ul:
601 case NVPTX::BI__nvvm_ldu_ul2:
602 case NVPTX::BI__nvvm_ldu_ull:
603 case NVPTX::BI__nvvm_ldu_ull2:
604 return MakeLdu(IntrinsicID: Intrinsic::nvvm_ldu_global_i, CGF&: *this, E);
605 case NVPTX::BI__nvvm_ldu_f:
606 case NVPTX::BI__nvvm_ldu_f2:
607 case NVPTX::BI__nvvm_ldu_f4:
608 case NVPTX::BI__nvvm_ldu_d:
609 case NVPTX::BI__nvvm_ldu_d2:
610 return MakeLdu(IntrinsicID: Intrinsic::nvvm_ldu_global_f, CGF&: *this, E);
611
612 case NVPTX::BI__nvvm_atom_cta_add_gen_i:
613 case NVPTX::BI__nvvm_atom_cta_add_gen_l:
614 case NVPTX::BI__nvvm_atom_cta_add_gen_ll:
615 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Add,
616 Scope: llvm::AtomicScope::Workgroup);
617 case NVPTX::BI__nvvm_atom_sys_add_gen_i:
618 case NVPTX::BI__nvvm_atom_sys_add_gen_l:
619 case NVPTX::BI__nvvm_atom_sys_add_gen_ll:
620 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Add,
621 Scope: llvm::AtomicScope::System);
622 case NVPTX::BI__nvvm_atom_cta_add_gen_f:
623 case NVPTX::BI__nvvm_atom_cta_add_gen_d:
624 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::FAdd,
625 Scope: llvm::AtomicScope::Workgroup);
626 case NVPTX::BI__nvvm_atom_sys_add_gen_f:
627 case NVPTX::BI__nvvm_atom_sys_add_gen_d:
628 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::FAdd,
629 Scope: llvm::AtomicScope::System);
630 case NVPTX::BI__nvvm_atom_cta_xchg_gen_i:
631 case NVPTX::BI__nvvm_atom_cta_xchg_gen_l:
632 case NVPTX::BI__nvvm_atom_cta_xchg_gen_ll:
633 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Xchg,
634 Scope: llvm::AtomicScope::Workgroup);
635 case NVPTX::BI__nvvm_atom_sys_xchg_gen_i:
636 case NVPTX::BI__nvvm_atom_sys_xchg_gen_l:
637 case NVPTX::BI__nvvm_atom_sys_xchg_gen_ll:
638 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Xchg,
639 Scope: llvm::AtomicScope::System);
640 case NVPTX::BI__nvvm_atom_cta_max_gen_i:
641 case NVPTX::BI__nvvm_atom_cta_max_gen_l:
642 case NVPTX::BI__nvvm_atom_cta_max_gen_ll:
643 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Max,
644 Scope: llvm::AtomicScope::Workgroup);
645 case NVPTX::BI__nvvm_atom_cta_max_gen_ui:
646 case NVPTX::BI__nvvm_atom_cta_max_gen_ul:
647 case NVPTX::BI__nvvm_atom_cta_max_gen_ull:
648 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::UMax,
649 Scope: llvm::AtomicScope::Workgroup);
650 case NVPTX::BI__nvvm_atom_sys_max_gen_i:
651 case NVPTX::BI__nvvm_atom_sys_max_gen_l:
652 case NVPTX::BI__nvvm_atom_sys_max_gen_ll:
653 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Max,
654 Scope: llvm::AtomicScope::System);
655 case NVPTX::BI__nvvm_atom_sys_max_gen_ui:
656 case NVPTX::BI__nvvm_atom_sys_max_gen_ul:
657 case NVPTX::BI__nvvm_atom_sys_max_gen_ull:
658 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::UMax,
659 Scope: llvm::AtomicScope::System);
660 case NVPTX::BI__nvvm_atom_cta_min_gen_i:
661 case NVPTX::BI__nvvm_atom_cta_min_gen_l:
662 case NVPTX::BI__nvvm_atom_cta_min_gen_ll:
663 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Min,
664 Scope: llvm::AtomicScope::Workgroup);
665 case NVPTX::BI__nvvm_atom_cta_min_gen_ui:
666 case NVPTX::BI__nvvm_atom_cta_min_gen_ul:
667 case NVPTX::BI__nvvm_atom_cta_min_gen_ull:
668 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::UMin,
669 Scope: llvm::AtomicScope::Workgroup);
670 case NVPTX::BI__nvvm_atom_sys_min_gen_i:
671 case NVPTX::BI__nvvm_atom_sys_min_gen_l:
672 case NVPTX::BI__nvvm_atom_sys_min_gen_ll:
673 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Min,
674 Scope: llvm::AtomicScope::System);
675 case NVPTX::BI__nvvm_atom_sys_min_gen_ui:
676 case NVPTX::BI__nvvm_atom_sys_min_gen_ul:
677 case NVPTX::BI__nvvm_atom_sys_min_gen_ull:
678 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::UMin,
679 Scope: llvm::AtomicScope::System);
680 case NVPTX::BI__nvvm_atom_cta_inc_gen_ui:
681 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::UIncWrap,
682 Scope: llvm::AtomicScope::Workgroup);
683 case NVPTX::BI__nvvm_atom_cta_dec_gen_ui:
684 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::UDecWrap,
685 Scope: llvm::AtomicScope::Workgroup);
686 case NVPTX::BI__nvvm_atom_sys_inc_gen_ui:
687 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::UIncWrap,
688 Scope: llvm::AtomicScope::System);
689 case NVPTX::BI__nvvm_atom_sys_dec_gen_ui:
690 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::UDecWrap,
691 Scope: llvm::AtomicScope::System);
692 case NVPTX::BI__nvvm_atom_cta_and_gen_i:
693 case NVPTX::BI__nvvm_atom_cta_and_gen_l:
694 case NVPTX::BI__nvvm_atom_cta_and_gen_ll:
695 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::And,
696 Scope: llvm::AtomicScope::Workgroup);
697 case NVPTX::BI__nvvm_atom_sys_and_gen_i:
698 case NVPTX::BI__nvvm_atom_sys_and_gen_l:
699 case NVPTX::BI__nvvm_atom_sys_and_gen_ll:
700 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::And,
701 Scope: llvm::AtomicScope::System);
702 case NVPTX::BI__nvvm_atom_cta_or_gen_i:
703 case NVPTX::BI__nvvm_atom_cta_or_gen_l:
704 case NVPTX::BI__nvvm_atom_cta_or_gen_ll:
705 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Or,
706 Scope: llvm::AtomicScope::Workgroup);
707 case NVPTX::BI__nvvm_atom_sys_or_gen_i:
708 case NVPTX::BI__nvvm_atom_sys_or_gen_l:
709 case NVPTX::BI__nvvm_atom_sys_or_gen_ll:
710 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Or,
711 Scope: llvm::AtomicScope::System);
712 case NVPTX::BI__nvvm_atom_cta_xor_gen_i:
713 case NVPTX::BI__nvvm_atom_cta_xor_gen_l:
714 case NVPTX::BI__nvvm_atom_cta_xor_gen_ll:
715 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Xor,
716 Scope: llvm::AtomicScope::Workgroup);
717 case NVPTX::BI__nvvm_atom_sys_xor_gen_i:
718 case NVPTX::BI__nvvm_atom_sys_xor_gen_l:
719 case NVPTX::BI__nvvm_atom_sys_xor_gen_ll:
720 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Xor,
721 Scope: llvm::AtomicScope::System);
722 case NVPTX::BI__nvvm_atom_cta_cas_gen_us:
723 case NVPTX::BI__nvvm_atom_cta_cas_gen_i:
724 case NVPTX::BI__nvvm_atom_cta_cas_gen_l:
725 case NVPTX::BI__nvvm_atom_cta_cas_gen_ll:
726 return MakeScopedAtomicCAS(CGF&: *this, E, Scope: llvm::AtomicScope::Workgroup);
727 case NVPTX::BI__nvvm_atom_sys_cas_gen_us:
728 case NVPTX::BI__nvvm_atom_sys_cas_gen_i:
729 case NVPTX::BI__nvvm_atom_sys_cas_gen_l:
730 case NVPTX::BI__nvvm_atom_sys_cas_gen_ll:
731 return MakeScopedAtomicCAS(CGF&: *this, E, Scope: llvm::AtomicScope::System);
732 case NVPTX::BI__nvvm_match_all_sync_i32p:
733 case NVPTX::BI__nvvm_match_all_sync_i64p: {
734 Value *Mask = EmitScalarExpr(E: E->getArg(Arg: 0));
735 Value *Val = EmitScalarExpr(E: E->getArg(Arg: 1));
736 Address PredOutPtr = EmitPointerWithAlignment(Addr: E->getArg(Arg: 2));
737 Value *ResultPair = Builder.CreateCall(
738 Callee: CGM.getIntrinsic(IID: BuiltinID == NVPTX::BI__nvvm_match_all_sync_i32p
739 ? Intrinsic::nvvm_match_all_sync_i32p
740 : Intrinsic::nvvm_match_all_sync_i64p),
741 Args: {Mask, Val});
742 Value *Pred = Builder.CreateZExt(V: Builder.CreateExtractValue(Agg: ResultPair, Idxs: 1),
743 DestTy: PredOutPtr.getElementType());
744 Builder.CreateStore(Val: Pred, Addr: PredOutPtr);
745 return Builder.CreateExtractValue(Agg: ResultPair, Idxs: 0);
746 }
747
748 // FP MMA loads
749 case NVPTX::BI__hmma_m16n16k16_ld_a:
750 case NVPTX::BI__hmma_m16n16k16_ld_b:
751 case NVPTX::BI__hmma_m16n16k16_ld_c_f16:
752 case NVPTX::BI__hmma_m16n16k16_ld_c_f32:
753 case NVPTX::BI__hmma_m32n8k16_ld_a:
754 case NVPTX::BI__hmma_m32n8k16_ld_b:
755 case NVPTX::BI__hmma_m32n8k16_ld_c_f16:
756 case NVPTX::BI__hmma_m32n8k16_ld_c_f32:
757 case NVPTX::BI__hmma_m8n32k16_ld_a:
758 case NVPTX::BI__hmma_m8n32k16_ld_b:
759 case NVPTX::BI__hmma_m8n32k16_ld_c_f16:
760 case NVPTX::BI__hmma_m8n32k16_ld_c_f32:
761 // Integer MMA loads.
762 case NVPTX::BI__imma_m16n16k16_ld_a_s8:
763 case NVPTX::BI__imma_m16n16k16_ld_a_u8:
764 case NVPTX::BI__imma_m16n16k16_ld_b_s8:
765 case NVPTX::BI__imma_m16n16k16_ld_b_u8:
766 case NVPTX::BI__imma_m16n16k16_ld_c:
767 case NVPTX::BI__imma_m32n8k16_ld_a_s8:
768 case NVPTX::BI__imma_m32n8k16_ld_a_u8:
769 case NVPTX::BI__imma_m32n8k16_ld_b_s8:
770 case NVPTX::BI__imma_m32n8k16_ld_b_u8:
771 case NVPTX::BI__imma_m32n8k16_ld_c:
772 case NVPTX::BI__imma_m8n32k16_ld_a_s8:
773 case NVPTX::BI__imma_m8n32k16_ld_a_u8:
774 case NVPTX::BI__imma_m8n32k16_ld_b_s8:
775 case NVPTX::BI__imma_m8n32k16_ld_b_u8:
776 case NVPTX::BI__imma_m8n32k16_ld_c:
777 // Sub-integer MMA loads.
778 case NVPTX::BI__imma_m8n8k32_ld_a_s4:
779 case NVPTX::BI__imma_m8n8k32_ld_a_u4:
780 case NVPTX::BI__imma_m8n8k32_ld_b_s4:
781 case NVPTX::BI__imma_m8n8k32_ld_b_u4:
782 case NVPTX::BI__imma_m8n8k32_ld_c:
783 case NVPTX::BI__bmma_m8n8k128_ld_a_b1:
784 case NVPTX::BI__bmma_m8n8k128_ld_b_b1:
785 case NVPTX::BI__bmma_m8n8k128_ld_c:
786 // Double MMA loads.
787 case NVPTX::BI__dmma_m8n8k4_ld_a:
788 case NVPTX::BI__dmma_m8n8k4_ld_b:
789 case NVPTX::BI__dmma_m8n8k4_ld_c:
790 // Alternate float MMA loads.
791 case NVPTX::BI__mma_bf16_m16n16k16_ld_a:
792 case NVPTX::BI__mma_bf16_m16n16k16_ld_b:
793 case NVPTX::BI__mma_bf16_m8n32k16_ld_a:
794 case NVPTX::BI__mma_bf16_m8n32k16_ld_b:
795 case NVPTX::BI__mma_bf16_m32n8k16_ld_a:
796 case NVPTX::BI__mma_bf16_m32n8k16_ld_b:
797 case NVPTX::BI__mma_tf32_m16n16k8_ld_a:
798 case NVPTX::BI__mma_tf32_m16n16k8_ld_b:
799 case NVPTX::BI__mma_tf32_m16n16k8_ld_c: {
800 Address Dst = EmitPointerWithAlignment(Addr: E->getArg(Arg: 0));
801 Value *Src = EmitScalarExpr(E: E->getArg(Arg: 1));
802 Value *Ldm = EmitScalarExpr(E: E->getArg(Arg: 2));
803 std::optional<llvm::APSInt> isColMajorArg =
804 E->getArg(Arg: 3)->getIntegerConstantExpr(Ctx: getContext());
805 if (!isColMajorArg)
806 return nullptr;
807 bool isColMajor = isColMajorArg->getSExtValue();
808 NVPTXMmaLdstInfo II = getNVPTXMmaLdstInfo(BuiltinID);
809 unsigned IID = isColMajor ? II.IID_col : II.IID_row;
810 if (IID == 0)
811 return nullptr;
812
813 Value *Result =
814 Builder.CreateCall(Callee: CGM.getIntrinsic(IID, Tys: Src->getType()), Args: {Src, Ldm});
815
816 // Save returned values.
817 assert(II.NumResults);
818 if (II.NumResults == 1) {
819 Builder.CreateAlignedStore(Val: Result, Addr: Dst.emitRawPointer(CGF&: *this),
820 Align: CharUnits::fromQuantity(Quantity: 4));
821 } else {
822 for (unsigned i = 0; i < II.NumResults; ++i) {
823 Builder.CreateAlignedStore(
824 Val: Builder.CreateBitCast(V: Builder.CreateExtractValue(Agg: Result, Idxs: i),
825 DestTy: Dst.getElementType()),
826 Addr: Builder.CreateGEP(Ty: Dst.getElementType(), Ptr: Dst.emitRawPointer(CGF&: *this),
827 IdxList: llvm::ConstantInt::get(Ty: IntTy, V: i)),
828 Align: CharUnits::fromQuantity(Quantity: 4));
829 }
830 }
831 return Result;
832 }
833
834 case NVPTX::BI__hmma_m16n16k16_st_c_f16:
835 case NVPTX::BI__hmma_m16n16k16_st_c_f32:
836 case NVPTX::BI__hmma_m32n8k16_st_c_f16:
837 case NVPTX::BI__hmma_m32n8k16_st_c_f32:
838 case NVPTX::BI__hmma_m8n32k16_st_c_f16:
839 case NVPTX::BI__hmma_m8n32k16_st_c_f32:
840 case NVPTX::BI__imma_m16n16k16_st_c_i32:
841 case NVPTX::BI__imma_m32n8k16_st_c_i32:
842 case NVPTX::BI__imma_m8n32k16_st_c_i32:
843 case NVPTX::BI__imma_m8n8k32_st_c_i32:
844 case NVPTX::BI__bmma_m8n8k128_st_c_i32:
845 case NVPTX::BI__dmma_m8n8k4_st_c_f64:
846 case NVPTX::BI__mma_m16n16k8_st_c_f32: {
847 Value *Dst = EmitScalarExpr(E: E->getArg(Arg: 0));
848 Address Src = EmitPointerWithAlignment(Addr: E->getArg(Arg: 1));
849 Value *Ldm = EmitScalarExpr(E: E->getArg(Arg: 2));
850 std::optional<llvm::APSInt> isColMajorArg =
851 E->getArg(Arg: 3)->getIntegerConstantExpr(Ctx: getContext());
852 if (!isColMajorArg)
853 return nullptr;
854 bool isColMajor = isColMajorArg->getSExtValue();
855 NVPTXMmaLdstInfo II = getNVPTXMmaLdstInfo(BuiltinID);
856 unsigned IID = isColMajor ? II.IID_col : II.IID_row;
857 if (IID == 0)
858 return nullptr;
859 Function *Intrinsic =
860 CGM.getIntrinsic(IID, Tys: Dst->getType());
861 llvm::Type *ParamType = Intrinsic->getFunctionType()->getParamType(i: 1);
862 SmallVector<Value *, 10> Values = {Dst};
863 for (unsigned i = 0; i < II.NumResults; ++i) {
864 Value *V = Builder.CreateAlignedLoad(
865 Ty: Src.getElementType(),
866 Addr: Builder.CreateGEP(Ty: Src.getElementType(), Ptr: Src.emitRawPointer(CGF&: *this),
867 IdxList: llvm::ConstantInt::get(Ty: IntTy, V: i)),
868 Align: CharUnits::fromQuantity(Quantity: 4));
869 Values.push_back(Elt: Builder.CreateBitCast(V, DestTy: ParamType));
870 }
871 Values.push_back(Elt: Ldm);
872 Value *Result = Builder.CreateCall(Callee: Intrinsic, Args: Values);
873 return Result;
874 }
875
876 // BI__hmma_m16n16k16_mma_<Dtype><CType>(d, a, b, c, layout, satf) -->
877 // Intrinsic::nvvm_wmma_m16n16k16_mma_sync<layout A,B><DType><CType><Satf>
878 case NVPTX::BI__hmma_m16n16k16_mma_f16f16:
879 case NVPTX::BI__hmma_m16n16k16_mma_f32f16:
880 case NVPTX::BI__hmma_m16n16k16_mma_f32f32:
881 case NVPTX::BI__hmma_m16n16k16_mma_f16f32:
882 case NVPTX::BI__hmma_m32n8k16_mma_f16f16:
883 case NVPTX::BI__hmma_m32n8k16_mma_f32f16:
884 case NVPTX::BI__hmma_m32n8k16_mma_f32f32:
885 case NVPTX::BI__hmma_m32n8k16_mma_f16f32:
886 case NVPTX::BI__hmma_m8n32k16_mma_f16f16:
887 case NVPTX::BI__hmma_m8n32k16_mma_f32f16:
888 case NVPTX::BI__hmma_m8n32k16_mma_f32f32:
889 case NVPTX::BI__hmma_m8n32k16_mma_f16f32:
890 case NVPTX::BI__imma_m16n16k16_mma_s8:
891 case NVPTX::BI__imma_m16n16k16_mma_u8:
892 case NVPTX::BI__imma_m32n8k16_mma_s8:
893 case NVPTX::BI__imma_m32n8k16_mma_u8:
894 case NVPTX::BI__imma_m8n32k16_mma_s8:
895 case NVPTX::BI__imma_m8n32k16_mma_u8:
896 case NVPTX::BI__imma_m8n8k32_mma_s4:
897 case NVPTX::BI__imma_m8n8k32_mma_u4:
898 case NVPTX::BI__bmma_m8n8k128_mma_xor_popc_b1:
899 case NVPTX::BI__bmma_m8n8k128_mma_and_popc_b1:
900 case NVPTX::BI__dmma_m8n8k4_mma_f64:
901 case NVPTX::BI__mma_bf16_m16n16k16_mma_f32:
902 case NVPTX::BI__mma_bf16_m8n32k16_mma_f32:
903 case NVPTX::BI__mma_bf16_m32n8k16_mma_f32:
904 case NVPTX::BI__mma_tf32_m16n16k8_mma_f32: {
905 Address Dst = EmitPointerWithAlignment(Addr: E->getArg(Arg: 0));
906 Address SrcA = EmitPointerWithAlignment(Addr: E->getArg(Arg: 1));
907 Address SrcB = EmitPointerWithAlignment(Addr: E->getArg(Arg: 2));
908 Address SrcC = EmitPointerWithAlignment(Addr: E->getArg(Arg: 3));
909 std::optional<llvm::APSInt> LayoutArg =
910 E->getArg(Arg: 4)->getIntegerConstantExpr(Ctx: getContext());
911 if (!LayoutArg)
912 return nullptr;
913 int Layout = LayoutArg->getSExtValue();
914 if (Layout < 0 || Layout > 3)
915 return nullptr;
916 llvm::APSInt SatfArg;
917 if (BuiltinID == NVPTX::BI__bmma_m8n8k128_mma_xor_popc_b1 ||
918 BuiltinID == NVPTX::BI__bmma_m8n8k128_mma_and_popc_b1)
919 SatfArg = 0; // .b1 does not have satf argument.
920 else if (std::optional<llvm::APSInt> OptSatfArg =
921 E->getArg(Arg: 5)->getIntegerConstantExpr(Ctx: getContext()))
922 SatfArg = *OptSatfArg;
923 else
924 return nullptr;
925 bool Satf = SatfArg.getSExtValue();
926 NVPTXMmaInfo MI = getNVPTXMmaInfo(BuiltinID);
927 unsigned IID = MI.getMMAIntrinsic(Layout, Satf);
928 if (IID == 0) // Unsupported combination of Layout/Satf.
929 return nullptr;
930
931 SmallVector<Value *, 24> Values;
932 Function *Intrinsic = CGM.getIntrinsic(IID);
933 llvm::Type *AType = Intrinsic->getFunctionType()->getParamType(i: 0);
934 // Load A
935 for (unsigned i = 0; i < MI.NumEltsA; ++i) {
936 Value *V = Builder.CreateAlignedLoad(
937 Ty: SrcA.getElementType(),
938 Addr: Builder.CreateGEP(Ty: SrcA.getElementType(), Ptr: SrcA.emitRawPointer(CGF&: *this),
939 IdxList: llvm::ConstantInt::get(Ty: IntTy, V: i)),
940 Align: CharUnits::fromQuantity(Quantity: 4));
941 Values.push_back(Elt: Builder.CreateBitCast(V, DestTy: AType));
942 }
943 // Load B
944 llvm::Type *BType = Intrinsic->getFunctionType()->getParamType(i: MI.NumEltsA);
945 for (unsigned i = 0; i < MI.NumEltsB; ++i) {
946 Value *V = Builder.CreateAlignedLoad(
947 Ty: SrcB.getElementType(),
948 Addr: Builder.CreateGEP(Ty: SrcB.getElementType(), Ptr: SrcB.emitRawPointer(CGF&: *this),
949 IdxList: llvm::ConstantInt::get(Ty: IntTy, V: i)),
950 Align: CharUnits::fromQuantity(Quantity: 4));
951 Values.push_back(Elt: Builder.CreateBitCast(V, DestTy: BType));
952 }
953 // Load C
954 llvm::Type *CType =
955 Intrinsic->getFunctionType()->getParamType(i: MI.NumEltsA + MI.NumEltsB);
956 for (unsigned i = 0; i < MI.NumEltsC; ++i) {
957 Value *V = Builder.CreateAlignedLoad(
958 Ty: SrcC.getElementType(),
959 Addr: Builder.CreateGEP(Ty: SrcC.getElementType(), Ptr: SrcC.emitRawPointer(CGF&: *this),
960 IdxList: llvm::ConstantInt::get(Ty: IntTy, V: i)),
961 Align: CharUnits::fromQuantity(Quantity: 4));
962 Values.push_back(Elt: Builder.CreateBitCast(V, DestTy: CType));
963 }
964 Value *Result = Builder.CreateCall(Callee: Intrinsic, Args: Values);
965 llvm::Type *DType = Dst.getElementType();
966 for (unsigned i = 0; i < MI.NumEltsD; ++i)
967 Builder.CreateAlignedStore(
968 Val: Builder.CreateBitCast(V: Builder.CreateExtractValue(Agg: Result, Idxs: i), DestTy: DType),
969 Addr: Builder.CreateGEP(Ty: Dst.getElementType(), Ptr: Dst.emitRawPointer(CGF&: *this),
970 IdxList: llvm::ConstantInt::get(Ty: IntTy, V: i)),
971 Align: CharUnits::fromQuantity(Quantity: 4));
972 return Result;
973 }
974 // The following builtins require half type support
975 case NVPTX::BI__nvvm_ex2_approx_f16:
976 return MakeHalfType(
977 Intrinsic: CGM.getIntrinsic(IID: Intrinsic::nvvm_ex2_approx, Tys: Builder.getHalfTy()),
978 BuiltinID, E, CGF&: *this);
979 case NVPTX::BI__nvvm_ex2_approx_f16x2:
980 return MakeHalfType(
981 Intrinsic: CGM.getIntrinsic(IID: Intrinsic::nvvm_ex2_approx,
982 Tys: FixedVectorType::get(ElementType: Builder.getHalfTy(), NumElts: 2)),
983 BuiltinID, E, CGF&: *this);
984 case NVPTX::BI__nvvm_ff2f16x2_rn:
985 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_ff2f16x2_rn, BuiltinID, E, CGF&: *this);
986 case NVPTX::BI__nvvm_ff2f16x2_rn_relu:
987 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_ff2f16x2_rn_relu, BuiltinID, E, CGF&: *this);
988 case NVPTX::BI__nvvm_ff2f16x2_rz:
989 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_ff2f16x2_rz, BuiltinID, E, CGF&: *this);
990 case NVPTX::BI__nvvm_ff2f16x2_rz_relu:
991 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_ff2f16x2_rz_relu, BuiltinID, E, CGF&: *this);
992
993#define PZO_CVT(cvt) \
994 case NVPTX::BI__nvvm_##cvt##_pzo: \
995 return MakeHalfType(Intrinsic::nvvm_##cvt, BuiltinID, E, *this, \
996 {Builder.getTrue()})
997
998 PZO_CVT(ff2f16x2_rn);
999 PZO_CVT(ff2f16x2_rn_relu);
1000 PZO_CVT(ff2f16x2_rz);
1001 PZO_CVT(ff2f16x2_rz_relu);
1002 PZO_CVT(ff2f16x2_rn_satfinite);
1003 PZO_CVT(ff2f16x2_rn_relu_satfinite);
1004 PZO_CVT(ff2f16x2_rz_satfinite);
1005 PZO_CVT(ff2f16x2_rz_relu_satfinite);
1006 PZO_CVT(ff2bf16x2_rn);
1007 PZO_CVT(ff2bf16x2_rn_relu);
1008 PZO_CVT(ff2bf16x2_rz);
1009 PZO_CVT(ff2bf16x2_rz_relu);
1010 PZO_CVT(ff2bf16x2_rn_satfinite);
1011 PZO_CVT(ff2bf16x2_rn_relu_satfinite);
1012 PZO_CVT(ff2bf16x2_rz_satfinite);
1013 PZO_CVT(ff2bf16x2_rz_relu_satfinite);
1014 PZO_CVT(f2f16_rn);
1015 PZO_CVT(f2f16_rn_relu);
1016 PZO_CVT(f2f16_rz);
1017 PZO_CVT(f2f16_rz_relu);
1018 PZO_CVT(f2f16_rn_satfinite);
1019 PZO_CVT(f2f16_rn_relu_satfinite);
1020 PZO_CVT(f2f16_rz_satfinite);
1021 PZO_CVT(f2f16_rz_relu_satfinite);
1022 PZO_CVT(f2bf16_rn);
1023 PZO_CVT(f2bf16_rn_relu);
1024 PZO_CVT(f2bf16_rz);
1025 PZO_CVT(f2bf16_rz_relu);
1026 PZO_CVT(f2bf16_rn_satfinite);
1027 PZO_CVT(f2bf16_rn_relu_satfinite);
1028 PZO_CVT(f2bf16_rz_satfinite);
1029 PZO_CVT(f2bf16_rz_relu_satfinite);
1030
1031 PZO_CVT(ff_to_e4m3x2_rn);
1032 PZO_CVT(ff_to_e4m3x2_rn_relu);
1033 PZO_CVT(ff_to_e4m3x2_rz);
1034 PZO_CVT(ff_to_e4m3x2_rz_relu);
1035 PZO_CVT(ff_to_e5m2x2_rn);
1036 PZO_CVT(ff_to_e5m2x2_rn_relu);
1037 PZO_CVT(ff_to_e5m2x2_rz);
1038 PZO_CVT(ff_to_e5m2x2_rz_relu);
1039 PZO_CVT(f16x2_to_e4m3x2_rn);
1040 PZO_CVT(f16x2_to_e4m3x2_rn_relu);
1041 PZO_CVT(f16x2_to_e4m3x2_rz);
1042 PZO_CVT(f16x2_to_e4m3x2_rz_relu);
1043 PZO_CVT(f16x2_to_e5m2x2_rn);
1044 PZO_CVT(f16x2_to_e5m2x2_rn_relu);
1045 PZO_CVT(f16x2_to_e5m2x2_rz);
1046 PZO_CVT(f16x2_to_e5m2x2_rz_relu);
1047 PZO_CVT(bf16x2_to_e4m3x2_rn_satfinite);
1048 PZO_CVT(bf16x2_to_e4m3x2_rn_relu_satfinite);
1049 PZO_CVT(bf16x2_to_e4m3x2_rz_satfinite);
1050 PZO_CVT(bf16x2_to_e4m3x2_rz_relu_satfinite);
1051 PZO_CVT(bf16x2_to_e5m2x2_rn_satfinite);
1052 PZO_CVT(bf16x2_to_e5m2x2_rn_relu_satfinite);
1053 PZO_CVT(bf16x2_to_e5m2x2_rz_satfinite);
1054 PZO_CVT(bf16x2_to_e5m2x2_rz_relu_satfinite);
1055
1056 PZO_CVT(ff_to_e2m3x2_rn_satfinite);
1057 PZO_CVT(ff_to_e2m3x2_rn_relu_satfinite);
1058 PZO_CVT(ff_to_e2m3x2_rz_satfinite);
1059 PZO_CVT(ff_to_e2m3x2_rz_relu_satfinite);
1060 PZO_CVT(ff_to_e3m2x2_rn_satfinite);
1061 PZO_CVT(ff_to_e3m2x2_rn_relu_satfinite);
1062 PZO_CVT(ff_to_e3m2x2_rz_satfinite);
1063 PZO_CVT(ff_to_e3m2x2_rz_relu_satfinite);
1064 PZO_CVT(f16x2_to_e2m3x2_rn_satfinite);
1065 PZO_CVT(f16x2_to_e2m3x2_rn_relu_satfinite);
1066 PZO_CVT(f16x2_to_e2m3x2_rz_satfinite);
1067 PZO_CVT(f16x2_to_e2m3x2_rz_relu_satfinite);
1068 PZO_CVT(f16x2_to_e3m2x2_rn_satfinite);
1069 PZO_CVT(f16x2_to_e3m2x2_rn_relu_satfinite);
1070 PZO_CVT(f16x2_to_e3m2x2_rz_satfinite);
1071 PZO_CVT(f16x2_to_e3m2x2_rz_relu_satfinite);
1072 PZO_CVT(bf16x2_to_e2m3x2_rn_satfinite);
1073 PZO_CVT(bf16x2_to_e2m3x2_rn_relu_satfinite);
1074 PZO_CVT(bf16x2_to_e2m3x2_rz_satfinite);
1075 PZO_CVT(bf16x2_to_e2m3x2_rz_relu_satfinite);
1076 PZO_CVT(bf16x2_to_e3m2x2_rn_satfinite);
1077 PZO_CVT(bf16x2_to_e3m2x2_rn_relu_satfinite);
1078 PZO_CVT(bf16x2_to_e3m2x2_rz_satfinite);
1079 PZO_CVT(bf16x2_to_e3m2x2_rz_relu_satfinite);
1080
1081#undef PZO_CVT
1082
1083 case NVPTX::BI__nvvm_fma_rn_f16:
1084 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_f16, BuiltinID, E, CGF&: *this);
1085 case NVPTX::BI__nvvm_fma_rn_f16x2:
1086 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_f16x2, BuiltinID, E, CGF&: *this);
1087 case NVPTX::BI__nvvm_fma_rn_ftz_f16:
1088 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_ftz_f16, BuiltinID, E, CGF&: *this);
1089 case NVPTX::BI__nvvm_fma_rn_ftz_f16x2:
1090 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_ftz_f16x2, BuiltinID, E, CGF&: *this);
1091 case NVPTX::BI__nvvm_fma_rn_ftz_relu_f16:
1092 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_ftz_relu_f16, BuiltinID, E,
1093 CGF&: *this);
1094 case NVPTX::BI__nvvm_fma_rn_ftz_relu_f16x2:
1095 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_ftz_relu_f16x2, BuiltinID, E,
1096 CGF&: *this);
1097 case NVPTX::BI__nvvm_fma_rn_ftz_sat_f16:
1098 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_ftz_sat_f16, BuiltinID, E,
1099 CGF&: *this);
1100 case NVPTX::BI__nvvm_fma_rn_ftz_sat_f16x2:
1101 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_ftz_sat_f16x2, BuiltinID, E,
1102 CGF&: *this);
1103 case NVPTX::BI__nvvm_fma_rn_relu_f16:
1104 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_relu_f16, BuiltinID, E, CGF&: *this);
1105 case NVPTX::BI__nvvm_fma_rn_relu_f16x2:
1106 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_relu_f16x2, BuiltinID, E, CGF&: *this);
1107 case NVPTX::BI__nvvm_fma_rn_sat_f16:
1108 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_sat_f16, BuiltinID, E, CGF&: *this);
1109 case NVPTX::BI__nvvm_fma_rn_sat_f16x2:
1110 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_sat_f16x2, BuiltinID, E, CGF&: *this);
1111 case NVPTX::BI__nvvm_fma_rn_oob_f16:
1112 return MakeFMAOOB(IntrinsicID: Intrinsic::nvvm_fma_rn_oob, Ty: Builder.getHalfTy(), E,
1113 CGF&: *this);
1114 case NVPTX::BI__nvvm_fma_rn_oob_f16x2:
1115 return MakeFMAOOB(IntrinsicID: Intrinsic::nvvm_fma_rn_oob,
1116 Ty: llvm::FixedVectorType::get(ElementType: Builder.getHalfTy(), NumElts: 2), E,
1117 CGF&: *this);
1118 case NVPTX::BI__nvvm_fma_rn_oob_bf16:
1119 return MakeFMAOOB(IntrinsicID: Intrinsic::nvvm_fma_rn_oob, Ty: Builder.getBFloatTy(), E,
1120 CGF&: *this);
1121 case NVPTX::BI__nvvm_fma_rn_oob_bf16x2:
1122 return MakeFMAOOB(IntrinsicID: Intrinsic::nvvm_fma_rn_oob,
1123 Ty: llvm::FixedVectorType::get(ElementType: Builder.getBFloatTy(), NumElts: 2), E,
1124 CGF&: *this);
1125 case NVPTX::BI__nvvm_fma_rn_oob_relu_f16:
1126 return MakeFMAOOB(IntrinsicID: Intrinsic::nvvm_fma_rn_oob_relu, Ty: Builder.getHalfTy(), E,
1127 CGF&: *this);
1128 case NVPTX::BI__nvvm_fma_rn_oob_relu_f16x2:
1129 return MakeFMAOOB(IntrinsicID: Intrinsic::nvvm_fma_rn_oob_relu,
1130 Ty: llvm::FixedVectorType::get(ElementType: Builder.getHalfTy(), NumElts: 2), E,
1131 CGF&: *this);
1132 case NVPTX::BI__nvvm_fma_rn_oob_relu_bf16:
1133 return MakeFMAOOB(IntrinsicID: Intrinsic::nvvm_fma_rn_oob_relu, Ty: Builder.getBFloatTy(), E,
1134 CGF&: *this);
1135 case NVPTX::BI__nvvm_fma_rn_oob_relu_bf16x2:
1136 return MakeFMAOOB(IntrinsicID: Intrinsic::nvvm_fma_rn_oob_relu,
1137 Ty: llvm::FixedVectorType::get(ElementType: Builder.getBFloatTy(), NumElts: 2), E,
1138 CGF&: *this);
1139 case NVPTX::BI__nvvm_fmax_f16:
1140 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_f16, BuiltinID, E, CGF&: *this);
1141 case NVPTX::BI__nvvm_fmax_f16x2:
1142 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_f16x2, BuiltinID, E, CGF&: *this);
1143 case NVPTX::BI__nvvm_fmax_ftz_f16:
1144 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_ftz_f16, BuiltinID, E, CGF&: *this);
1145 case NVPTX::BI__nvvm_fmax_ftz_f16x2:
1146 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_ftz_f16x2, BuiltinID, E, CGF&: *this);
1147 case NVPTX::BI__nvvm_fmax_ftz_nan_f16:
1148 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_ftz_nan_f16, BuiltinID, E, CGF&: *this);
1149 case NVPTX::BI__nvvm_fmax_ftz_nan_f16x2:
1150 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_ftz_nan_f16x2, BuiltinID, E,
1151 CGF&: *this);
1152 case NVPTX::BI__nvvm_fmax_ftz_nan_xorsign_abs_f16:
1153 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f16, BuiltinID,
1154 E, CGF&: *this);
1155 case NVPTX::BI__nvvm_fmax_ftz_nan_xorsign_abs_f16x2:
1156 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f16x2,
1157 BuiltinID, E, CGF&: *this);
1158 case NVPTX::BI__nvvm_fmax_ftz_xorsign_abs_f16:
1159 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_ftz_xorsign_abs_f16, BuiltinID, E,
1160 CGF&: *this);
1161 case NVPTX::BI__nvvm_fmax_ftz_xorsign_abs_f16x2:
1162 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_ftz_xorsign_abs_f16x2, BuiltinID,
1163 E, CGF&: *this);
1164 case NVPTX::BI__nvvm_fmax_nan_f16:
1165 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_nan_f16, BuiltinID, E, CGF&: *this);
1166 case NVPTX::BI__nvvm_fmax_nan_f16x2:
1167 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_nan_f16x2, BuiltinID, E, CGF&: *this);
1168 case NVPTX::BI__nvvm_fmax_nan_xorsign_abs_f16:
1169 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_nan_xorsign_abs_f16, BuiltinID, E,
1170 CGF&: *this);
1171 case NVPTX::BI__nvvm_fmax_nan_xorsign_abs_f16x2:
1172 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_nan_xorsign_abs_f16x2, BuiltinID,
1173 E, CGF&: *this);
1174 case NVPTX::BI__nvvm_fmax_xorsign_abs_f16:
1175 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_xorsign_abs_f16, BuiltinID, E,
1176 CGF&: *this);
1177 case NVPTX::BI__nvvm_fmax_xorsign_abs_f16x2:
1178 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_xorsign_abs_f16x2, BuiltinID, E,
1179 CGF&: *this);
1180 case NVPTX::BI__nvvm_fmin_f16:
1181 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_f16, BuiltinID, E, CGF&: *this);
1182 case NVPTX::BI__nvvm_fmin_f16x2:
1183 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_f16x2, BuiltinID, E, CGF&: *this);
1184 case NVPTX::BI__nvvm_fmin_ftz_f16:
1185 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_ftz_f16, BuiltinID, E, CGF&: *this);
1186 case NVPTX::BI__nvvm_fmin_ftz_f16x2:
1187 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_ftz_f16x2, BuiltinID, E, CGF&: *this);
1188 case NVPTX::BI__nvvm_fmin_ftz_nan_f16:
1189 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_ftz_nan_f16, BuiltinID, E, CGF&: *this);
1190 case NVPTX::BI__nvvm_fmin_ftz_nan_f16x2:
1191 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_ftz_nan_f16x2, BuiltinID, E,
1192 CGF&: *this);
1193 case NVPTX::BI__nvvm_fmin_ftz_nan_xorsign_abs_f16:
1194 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f16, BuiltinID,
1195 E, CGF&: *this);
1196 case NVPTX::BI__nvvm_fmin_ftz_nan_xorsign_abs_f16x2:
1197 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f16x2,
1198 BuiltinID, E, CGF&: *this);
1199 case NVPTX::BI__nvvm_fmin_ftz_xorsign_abs_f16:
1200 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_ftz_xorsign_abs_f16, BuiltinID, E,
1201 CGF&: *this);
1202 case NVPTX::BI__nvvm_fmin_ftz_xorsign_abs_f16x2:
1203 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_ftz_xorsign_abs_f16x2, BuiltinID,
1204 E, CGF&: *this);
1205 case NVPTX::BI__nvvm_fmin_nan_f16:
1206 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_nan_f16, BuiltinID, E, CGF&: *this);
1207 case NVPTX::BI__nvvm_fmin_nan_f16x2:
1208 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_nan_f16x2, BuiltinID, E, CGF&: *this);
1209 case NVPTX::BI__nvvm_fmin_nan_xorsign_abs_f16:
1210 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_nan_xorsign_abs_f16, BuiltinID, E,
1211 CGF&: *this);
1212 case NVPTX::BI__nvvm_fmin_nan_xorsign_abs_f16x2:
1213 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_nan_xorsign_abs_f16x2, BuiltinID,
1214 E, CGF&: *this);
1215 case NVPTX::BI__nvvm_fmin_xorsign_abs_f16:
1216 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_xorsign_abs_f16, BuiltinID, E,
1217 CGF&: *this);
1218 case NVPTX::BI__nvvm_fmin_xorsign_abs_f16x2:
1219 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_xorsign_abs_f16x2, BuiltinID, E,
1220 CGF&: *this);
1221 case NVPTX::BI__nvvm_fabs_f:
1222 case NVPTX::BI__nvvm_abs_bf16:
1223 case NVPTX::BI__nvvm_abs_bf16x2:
1224 case NVPTX::BI__nvvm_fabs_f16:
1225 case NVPTX::BI__nvvm_fabs_f16x2:
1226 return Builder.CreateUnaryIntrinsic(ID: Intrinsic::nvvm_fabs,
1227 Op: EmitScalarExpr(E: E->getArg(Arg: 0)));
1228 case NVPTX::BI__nvvm_fabs_ftz_f:
1229 case NVPTX::BI__nvvm_fabs_ftz_f16:
1230 case NVPTX::BI__nvvm_fabs_ftz_f16x2:
1231 return Builder.CreateUnaryIntrinsic(ID: Intrinsic::nvvm_fabs_ftz,
1232 Op: EmitScalarExpr(E: E->getArg(Arg: 0)));
1233 case NVPTX::BI__nvvm_fabs_d:
1234 return Builder.CreateFAbs(V: EmitScalarExpr(E: E->getArg(Arg: 0)));
1235 case NVPTX::BI__nvvm_ex2_approx_d:
1236 case NVPTX::BI__nvvm_ex2_approx_f:
1237 return Builder.CreateUnaryIntrinsic(ID: Intrinsic::nvvm_ex2_approx,
1238 Op: EmitScalarExpr(E: E->getArg(Arg: 0)));
1239 case NVPTX::BI__nvvm_ex2_approx_ftz_f:
1240 return Builder.CreateUnaryIntrinsic(ID: Intrinsic::nvvm_ex2_approx_ftz,
1241 Op: EmitScalarExpr(E: E->getArg(Arg: 0)));
1242 case NVPTX::BI__nvvm_add_rn_f:
1243 case NVPTX::BI__nvvm_add_rn_d:
1244 return MakeFAdd(IntrinsicID: Intrinsic::nvvm_fadd, RM: APFloat::rmNearestTiesToEven,
1245 BuiltinID, E, CGF&: *this);
1246 case NVPTX::BI__nvvm_add_rz_f:
1247 case NVPTX::BI__nvvm_add_rz_d:
1248 return MakeFAdd(IntrinsicID: Intrinsic::nvvm_fadd, RM: APFloat::rmTowardZero, BuiltinID, E,
1249 CGF&: *this);
1250 case NVPTX::BI__nvvm_add_rm_f:
1251 case NVPTX::BI__nvvm_add_rm_d:
1252 return MakeFAdd(IntrinsicID: Intrinsic::nvvm_fadd, RM: APFloat::rmTowardNegative, BuiltinID,
1253 E, CGF&: *this);
1254 case NVPTX::BI__nvvm_add_rp_f:
1255 case NVPTX::BI__nvvm_add_rp_d:
1256 return MakeFAdd(IntrinsicID: Intrinsic::nvvm_fadd, RM: APFloat::rmTowardPositive, BuiltinID,
1257 E, CGF&: *this);
1258 case NVPTX::BI__nvvm_add_rn_ftz_f:
1259 return MakeFAdd(IntrinsicID: Intrinsic::nvvm_fadd_ftz, RM: APFloat::rmNearestTiesToEven,
1260 BuiltinID, E, CGF&: *this);
1261 case NVPTX::BI__nvvm_add_rz_ftz_f:
1262 return MakeFAdd(IntrinsicID: Intrinsic::nvvm_fadd_ftz, RM: APFloat::rmTowardZero, BuiltinID,
1263 E, CGF&: *this);
1264 case NVPTX::BI__nvvm_add_rm_ftz_f:
1265 return MakeFAdd(IntrinsicID: Intrinsic::nvvm_fadd_ftz, RM: APFloat::rmTowardNegative,
1266 BuiltinID, E, CGF&: *this);
1267 case NVPTX::BI__nvvm_add_rp_ftz_f:
1268 return MakeFAdd(IntrinsicID: Intrinsic::nvvm_fadd_ftz, RM: APFloat::rmTowardPositive,
1269 BuiltinID, E, CGF&: *this);
1270 case NVPTX::BI__nvvm_add_rn_sat_f:
1271 case NVPTX::BI__nvvm_add_rn_sat_f16:
1272 case NVPTX::BI__nvvm_add_rn_sat_v2f16:
1273 return MakeFAdd(IntrinsicID: Intrinsic::nvvm_fadd_sat, RM: APFloat::rmNearestTiesToEven,
1274 BuiltinID, E, CGF&: *this);
1275 case NVPTX::BI__nvvm_add_rz_sat_f:
1276 return MakeFAdd(IntrinsicID: Intrinsic::nvvm_fadd_sat, RM: APFloat::rmTowardZero, BuiltinID,
1277 E, CGF&: *this);
1278 case NVPTX::BI__nvvm_add_rm_sat_f:
1279 return MakeFAdd(IntrinsicID: Intrinsic::nvvm_fadd_sat, RM: APFloat::rmTowardNegative,
1280 BuiltinID, E, CGF&: *this);
1281 case NVPTX::BI__nvvm_add_rp_sat_f:
1282 return MakeFAdd(IntrinsicID: Intrinsic::nvvm_fadd_sat, RM: APFloat::rmTowardPositive,
1283 BuiltinID, E, CGF&: *this);
1284 case NVPTX::BI__nvvm_add_rn_ftz_sat_f:
1285 case NVPTX::BI__nvvm_add_rn_ftz_sat_f16:
1286 case NVPTX::BI__nvvm_add_rn_ftz_sat_v2f16:
1287 return MakeFAdd(IntrinsicID: Intrinsic::nvvm_fadd_ftz_sat, RM: APFloat::rmNearestTiesToEven,
1288 BuiltinID, E, CGF&: *this);
1289 case NVPTX::BI__nvvm_add_rz_ftz_sat_f:
1290 return MakeFAdd(IntrinsicID: Intrinsic::nvvm_fadd_ftz_sat, RM: APFloat::rmTowardZero,
1291 BuiltinID, E, CGF&: *this);
1292 case NVPTX::BI__nvvm_add_rm_ftz_sat_f:
1293 return MakeFAdd(IntrinsicID: Intrinsic::nvvm_fadd_ftz_sat, RM: APFloat::rmTowardNegative,
1294 BuiltinID, E, CGF&: *this);
1295 case NVPTX::BI__nvvm_add_rp_ftz_sat_f:
1296 return MakeFAdd(IntrinsicID: Intrinsic::nvvm_fadd_ftz_sat, RM: APFloat::rmTowardPositive,
1297 BuiltinID, E, CGF&: *this);
1298 case NVPTX::BI__nvvm_ldg_h:
1299 case NVPTX::BI__nvvm_ldg_h2:
1300 return MakeLdg(CGF&: *this, E);
1301 case NVPTX::BI__nvvm_ldu_h:
1302 case NVPTX::BI__nvvm_ldu_h2:
1303 return MakeLdu(IntrinsicID: Intrinsic::nvvm_ldu_global_f, CGF&: *this, E);
1304 case NVPTX::BI__nvvm_cp_async_ca_shared_global_4:
1305 return MakeCpAsync(IntrinsicID: Intrinsic::nvvm_cp_async_ca_shared_global_4,
1306 IntrinsicIDS: Intrinsic::nvvm_cp_async_ca_shared_global_4_s, CGF&: *this, E,
1307 SrcSize: 4);
1308 case NVPTX::BI__nvvm_cp_async_ca_shared_global_8:
1309 return MakeCpAsync(IntrinsicID: Intrinsic::nvvm_cp_async_ca_shared_global_8,
1310 IntrinsicIDS: Intrinsic::nvvm_cp_async_ca_shared_global_8_s, CGF&: *this, E,
1311 SrcSize: 8);
1312 case NVPTX::BI__nvvm_cp_async_ca_shared_global_16:
1313 return MakeCpAsync(IntrinsicID: Intrinsic::nvvm_cp_async_ca_shared_global_16,
1314 IntrinsicIDS: Intrinsic::nvvm_cp_async_ca_shared_global_16_s, CGF&: *this, E,
1315 SrcSize: 16);
1316 case NVPTX::BI__nvvm_cp_async_cg_shared_global_16:
1317 return MakeCpAsync(IntrinsicID: Intrinsic::nvvm_cp_async_cg_shared_global_16,
1318 IntrinsicIDS: Intrinsic::nvvm_cp_async_cg_shared_global_16_s, CGF&: *this, E,
1319 SrcSize: 16);
1320 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_x:
1321 return Builder.CreateCall(
1322 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_clusterid_x));
1323 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_y:
1324 return Builder.CreateCall(
1325 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_clusterid_y));
1326 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_z:
1327 return Builder.CreateCall(
1328 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_clusterid_z));
1329 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_w:
1330 return Builder.CreateCall(
1331 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_clusterid_w));
1332 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_x:
1333 return Builder.CreateCall(
1334 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_nclusterid_x));
1335 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_y:
1336 return Builder.CreateCall(
1337 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_nclusterid_y));
1338 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_z:
1339 return Builder.CreateCall(
1340 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_nclusterid_z));
1341 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_w:
1342 return Builder.CreateCall(
1343 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_nclusterid_w));
1344 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_x:
1345 return Builder.CreateCall(
1346 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_x));
1347 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_y:
1348 return Builder.CreateCall(
1349 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_y));
1350 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_z:
1351 return Builder.CreateCall(
1352 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_z));
1353 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_w:
1354 return Builder.CreateCall(
1355 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_w));
1356 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_x:
1357 return Builder.CreateCall(
1358 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_x));
1359 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_y:
1360 return Builder.CreateCall(
1361 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_y));
1362 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_z:
1363 return Builder.CreateCall(
1364 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_z));
1365 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_w:
1366 return Builder.CreateCall(
1367 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_w));
1368 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctarank:
1369 return Builder.CreateCall(
1370 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_ctarank));
1371 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctarank:
1372 return Builder.CreateCall(
1373 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_nctarank));
1374 case NVPTX::BI__nvvm_is_explicit_cluster:
1375 return Builder.CreateCall(
1376 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_is_explicit_cluster));
1377 case NVPTX::BI__nvvm_isspacep_shared_cluster:
1378 return Builder.CreateCall(
1379 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_isspacep_shared_cluster),
1380 Args: EmitScalarExpr(E: E->getArg(Arg: 0)));
1381 case NVPTX::BI__nvvm_mapa:
1382 return Builder.CreateCall(
1383 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_mapa),
1384 Args: {EmitScalarExpr(E: E->getArg(Arg: 0)), EmitScalarExpr(E: E->getArg(Arg: 1))});
1385 case NVPTX::BI__nvvm_mapa_shared_cluster:
1386 return Builder.CreateCall(
1387 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_mapa_shared_cluster),
1388 Args: {EmitScalarExpr(E: E->getArg(Arg: 0)), EmitScalarExpr(E: E->getArg(Arg: 1))});
1389 case NVPTX::BI__nvvm_getctarank:
1390 return Builder.CreateCall(
1391 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_getctarank),
1392 Args: EmitScalarExpr(E: E->getArg(Arg: 0)));
1393 case NVPTX::BI__nvvm_getctarank_shared_cluster:
1394 return Builder.CreateCall(
1395 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_getctarank_shared_cluster),
1396 Args: EmitScalarExpr(E: E->getArg(Arg: 0)));
1397 case NVPTX::BI__nvvm_barrier_cluster_arrive:
1398 return Builder.CreateCall(
1399 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_barrier_cluster_arrive));
1400 case NVPTX::BI__nvvm_barrier_cluster_arrive_relaxed:
1401 return Builder.CreateCall(
1402 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_barrier_cluster_arrive_relaxed));
1403 case NVPTX::BI__nvvm_barrier_cluster_wait:
1404 return Builder.CreateCall(
1405 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_barrier_cluster_wait));
1406 case NVPTX::BI__nvvm_fence_sc_cluster:
1407 return Builder.CreateCall(
1408 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_fence_sc_cluster));
1409 case NVPTX::BI__nvvm_bar_sync:
1410 return Builder.CreateCall(
1411 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_barrier_cta_sync_aligned_all),
1412 Args: EmitScalarExpr(E: E->getArg(Arg: 0)));
1413 case NVPTX::BI__syncthreads:
1414 return Builder.CreateCall(
1415 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_barrier_cta_sync_aligned_all),
1416 Args: Builder.getInt32(C: 0));
1417 case NVPTX::BI__nvvm_barrier_sync:
1418 return Builder.CreateCall(
1419 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_barrier_cta_sync_all),
1420 Args: EmitScalarExpr(E: E->getArg(Arg: 0)));
1421 case NVPTX::BI__nvvm_barrier_sync_cnt:
1422 return Builder.CreateCall(
1423 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_barrier_cta_sync_count),
1424 Args: {EmitScalarExpr(E: E->getArg(Arg: 0)), EmitScalarExpr(E: E->getArg(Arg: 1))});
1425 case NVPTX::BI__nvvm_bar0_and:
1426 return Builder.CreateZExt(
1427 V: Builder.CreateIntrinsic(
1428 ID: Intrinsic::nvvm_barrier_cta_red_and_aligned_all, OverloadTypes: {},
1429 Args: {Builder.getInt32(C: 0),
1430 Builder.CreateICmpNE(LHS: EmitScalarExpr(E: E->getArg(Arg: 0)),
1431 RHS: Builder.getInt32(C: 0))}),
1432 DestTy: Builder.getInt32Ty());
1433 case NVPTX::BI__nvvm_bar0_or:
1434 return Builder.CreateZExt(
1435 V: Builder.CreateIntrinsic(
1436 ID: Intrinsic::nvvm_barrier_cta_red_or_aligned_all, OverloadTypes: {},
1437 Args: {Builder.getInt32(C: 0),
1438 Builder.CreateICmpNE(LHS: EmitScalarExpr(E: E->getArg(Arg: 0)),
1439 RHS: Builder.getInt32(C: 0))}),
1440 DestTy: Builder.getInt32Ty());
1441 case NVPTX::BI__nvvm_bar0_popc:
1442 return Builder.CreateIntrinsic(
1443 ID: Intrinsic::nvvm_barrier_cta_red_popc_aligned_all, OverloadTypes: {},
1444 Args: {Builder.getInt32(C: 0), Builder.CreateICmpNE(LHS: EmitScalarExpr(E: E->getArg(Arg: 0)),
1445 RHS: Builder.getInt32(C: 0))});
1446 case NVPTX::BI__nvvm_mbarrier_init:
1447 case NVPTX::BI__nvvm_mbarrier_init_shared: {
1448 // The intrinsic is overloaded on the pointer, so the two builtins differ
1449 // only in the address space of their first argument.
1450 Value *Ptr = EmitScalarExpr(E: E->getArg(Arg: 0));
1451 return Builder.CreateIntrinsic(
1452 ID: Intrinsic::nvvm_mbarrier_init, OverloadTypes: {Ptr->getType()},
1453 Args: {Ptr, EmitScalarExpr(E: E->getArg(Arg: 1)), Builder.getInt32(C: 0)});
1454 }
1455 default:
1456 return nullptr;
1457 }
1458}
1459