1//===-------- NVPTX.cpp - Emit LLVM Code for builtins ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This contains code to emit Builtin calls as LLVM code.
10//
11//===----------------------------------------------------------------------===//
12
13#include "CGBuiltin.h"
14#include "clang/Basic/TargetBuiltins.h"
15#include "llvm/IR/IntrinsicsNVPTX.h"
16
17using namespace clang;
18using namespace CodeGen;
19using namespace llvm;
20
21namespace {
22// Helper classes for mapping MMA builtins to particular LLVM intrinsic variant.
23struct NVPTXMmaLdstInfo {
24 unsigned NumResults; // Number of elements to load/store
25 // Intrinsic IDs for row/col variants. 0 if particular layout is unsupported.
26 unsigned IID_col;
27 unsigned IID_row;
28};
29
30#define MMA_INTR(geom_op_type, layout) \
31 Intrinsic::nvvm_wmma_##geom_op_type##_##layout##_stride
32#define MMA_LDST(n, geom_op_type) \
33 { n, MMA_INTR(geom_op_type, col), MMA_INTR(geom_op_type, row) }
34
35static NVPTXMmaLdstInfo getNVPTXMmaLdstInfo(unsigned BuiltinID) {
36 switch (BuiltinID) {
37 // FP MMA loads
38 case NVPTX::BI__hmma_m16n16k16_ld_a:
39 return MMA_LDST(8, m16n16k16_load_a_f16);
40 case NVPTX::BI__hmma_m16n16k16_ld_b:
41 return MMA_LDST(8, m16n16k16_load_b_f16);
42 case NVPTX::BI__hmma_m16n16k16_ld_c_f16:
43 return MMA_LDST(4, m16n16k16_load_c_f16);
44 case NVPTX::BI__hmma_m16n16k16_ld_c_f32:
45 return MMA_LDST(8, m16n16k16_load_c_f32);
46 case NVPTX::BI__hmma_m32n8k16_ld_a:
47 return MMA_LDST(8, m32n8k16_load_a_f16);
48 case NVPTX::BI__hmma_m32n8k16_ld_b:
49 return MMA_LDST(8, m32n8k16_load_b_f16);
50 case NVPTX::BI__hmma_m32n8k16_ld_c_f16:
51 return MMA_LDST(4, m32n8k16_load_c_f16);
52 case NVPTX::BI__hmma_m32n8k16_ld_c_f32:
53 return MMA_LDST(8, m32n8k16_load_c_f32);
54 case NVPTX::BI__hmma_m8n32k16_ld_a:
55 return MMA_LDST(8, m8n32k16_load_a_f16);
56 case NVPTX::BI__hmma_m8n32k16_ld_b:
57 return MMA_LDST(8, m8n32k16_load_b_f16);
58 case NVPTX::BI__hmma_m8n32k16_ld_c_f16:
59 return MMA_LDST(4, m8n32k16_load_c_f16);
60 case NVPTX::BI__hmma_m8n32k16_ld_c_f32:
61 return MMA_LDST(8, m8n32k16_load_c_f32);
62
63 // Integer MMA loads
64 case NVPTX::BI__imma_m16n16k16_ld_a_s8:
65 return MMA_LDST(2, m16n16k16_load_a_s8);
66 case NVPTX::BI__imma_m16n16k16_ld_a_u8:
67 return MMA_LDST(2, m16n16k16_load_a_u8);
68 case NVPTX::BI__imma_m16n16k16_ld_b_s8:
69 return MMA_LDST(2, m16n16k16_load_b_s8);
70 case NVPTX::BI__imma_m16n16k16_ld_b_u8:
71 return MMA_LDST(2, m16n16k16_load_b_u8);
72 case NVPTX::BI__imma_m16n16k16_ld_c:
73 return MMA_LDST(8, m16n16k16_load_c_s32);
74 case NVPTX::BI__imma_m32n8k16_ld_a_s8:
75 return MMA_LDST(4, m32n8k16_load_a_s8);
76 case NVPTX::BI__imma_m32n8k16_ld_a_u8:
77 return MMA_LDST(4, m32n8k16_load_a_u8);
78 case NVPTX::BI__imma_m32n8k16_ld_b_s8:
79 return MMA_LDST(1, m32n8k16_load_b_s8);
80 case NVPTX::BI__imma_m32n8k16_ld_b_u8:
81 return MMA_LDST(1, m32n8k16_load_b_u8);
82 case NVPTX::BI__imma_m32n8k16_ld_c:
83 return MMA_LDST(8, m32n8k16_load_c_s32);
84 case NVPTX::BI__imma_m8n32k16_ld_a_s8:
85 return MMA_LDST(1, m8n32k16_load_a_s8);
86 case NVPTX::BI__imma_m8n32k16_ld_a_u8:
87 return MMA_LDST(1, m8n32k16_load_a_u8);
88 case NVPTX::BI__imma_m8n32k16_ld_b_s8:
89 return MMA_LDST(4, m8n32k16_load_b_s8);
90 case NVPTX::BI__imma_m8n32k16_ld_b_u8:
91 return MMA_LDST(4, m8n32k16_load_b_u8);
92 case NVPTX::BI__imma_m8n32k16_ld_c:
93 return MMA_LDST(8, m8n32k16_load_c_s32);
94
95 // Sub-integer MMA loads.
96 // Only row/col layout is supported by A/B fragments.
97 case NVPTX::BI__imma_m8n8k32_ld_a_s4:
98 return {.NumResults: 1, .IID_col: 0, MMA_INTR(m8n8k32_load_a_s4, row)};
99 case NVPTX::BI__imma_m8n8k32_ld_a_u4:
100 return {.NumResults: 1, .IID_col: 0, MMA_INTR(m8n8k32_load_a_u4, row)};
101 case NVPTX::BI__imma_m8n8k32_ld_b_s4:
102 return {.NumResults: 1, MMA_INTR(m8n8k32_load_b_s4, col), .IID_row: 0};
103 case NVPTX::BI__imma_m8n8k32_ld_b_u4:
104 return {.NumResults: 1, MMA_INTR(m8n8k32_load_b_u4, col), .IID_row: 0};
105 case NVPTX::BI__imma_m8n8k32_ld_c:
106 return MMA_LDST(2, m8n8k32_load_c_s32);
107 case NVPTX::BI__bmma_m8n8k128_ld_a_b1:
108 return {.NumResults: 1, .IID_col: 0, MMA_INTR(m8n8k128_load_a_b1, row)};
109 case NVPTX::BI__bmma_m8n8k128_ld_b_b1:
110 return {.NumResults: 1, MMA_INTR(m8n8k128_load_b_b1, col), .IID_row: 0};
111 case NVPTX::BI__bmma_m8n8k128_ld_c:
112 return MMA_LDST(2, m8n8k128_load_c_s32);
113
114 // Double MMA loads
115 case NVPTX::BI__dmma_m8n8k4_ld_a:
116 return MMA_LDST(1, m8n8k4_load_a_f64);
117 case NVPTX::BI__dmma_m8n8k4_ld_b:
118 return MMA_LDST(1, m8n8k4_load_b_f64);
119 case NVPTX::BI__dmma_m8n8k4_ld_c:
120 return MMA_LDST(2, m8n8k4_load_c_f64);
121
122 // Alternate float MMA loads
123 case NVPTX::BI__mma_bf16_m16n16k16_ld_a:
124 return MMA_LDST(4, m16n16k16_load_a_bf16);
125 case NVPTX::BI__mma_bf16_m16n16k16_ld_b:
126 return MMA_LDST(4, m16n16k16_load_b_bf16);
127 case NVPTX::BI__mma_bf16_m8n32k16_ld_a:
128 return MMA_LDST(2, m8n32k16_load_a_bf16);
129 case NVPTX::BI__mma_bf16_m8n32k16_ld_b:
130 return MMA_LDST(8, m8n32k16_load_b_bf16);
131 case NVPTX::BI__mma_bf16_m32n8k16_ld_a:
132 return MMA_LDST(8, m32n8k16_load_a_bf16);
133 case NVPTX::BI__mma_bf16_m32n8k16_ld_b:
134 return MMA_LDST(2, m32n8k16_load_b_bf16);
135 case NVPTX::BI__mma_tf32_m16n16k8_ld_a:
136 return MMA_LDST(4, m16n16k8_load_a_tf32);
137 case NVPTX::BI__mma_tf32_m16n16k8_ld_b:
138 return MMA_LDST(4, m16n16k8_load_b_tf32);
139 case NVPTX::BI__mma_tf32_m16n16k8_ld_c:
140 return MMA_LDST(8, m16n16k8_load_c_f32);
141
142 // NOTE: We need to follow inconsitent naming scheme used by NVCC. Unlike
143 // PTX and LLVM IR where stores always use fragment D, NVCC builtins always
144 // use fragment C for both loads and stores.
145 // FP MMA stores.
146 case NVPTX::BI__hmma_m16n16k16_st_c_f16:
147 return MMA_LDST(4, m16n16k16_store_d_f16);
148 case NVPTX::BI__hmma_m16n16k16_st_c_f32:
149 return MMA_LDST(8, m16n16k16_store_d_f32);
150 case NVPTX::BI__hmma_m32n8k16_st_c_f16:
151 return MMA_LDST(4, m32n8k16_store_d_f16);
152 case NVPTX::BI__hmma_m32n8k16_st_c_f32:
153 return MMA_LDST(8, m32n8k16_store_d_f32);
154 case NVPTX::BI__hmma_m8n32k16_st_c_f16:
155 return MMA_LDST(4, m8n32k16_store_d_f16);
156 case NVPTX::BI__hmma_m8n32k16_st_c_f32:
157 return MMA_LDST(8, m8n32k16_store_d_f32);
158
159 // Integer and sub-integer MMA stores.
160 // Another naming quirk. Unlike other MMA builtins that use PTX types in the
161 // name, integer loads/stores use LLVM's i32.
162 case NVPTX::BI__imma_m16n16k16_st_c_i32:
163 return MMA_LDST(8, m16n16k16_store_d_s32);
164 case NVPTX::BI__imma_m32n8k16_st_c_i32:
165 return MMA_LDST(8, m32n8k16_store_d_s32);
166 case NVPTX::BI__imma_m8n32k16_st_c_i32:
167 return MMA_LDST(8, m8n32k16_store_d_s32);
168 case NVPTX::BI__imma_m8n8k32_st_c_i32:
169 return MMA_LDST(2, m8n8k32_store_d_s32);
170 case NVPTX::BI__bmma_m8n8k128_st_c_i32:
171 return MMA_LDST(2, m8n8k128_store_d_s32);
172
173 // Double MMA store
174 case NVPTX::BI__dmma_m8n8k4_st_c_f64:
175 return MMA_LDST(2, m8n8k4_store_d_f64);
176
177 // Alternate float MMA store
178 case NVPTX::BI__mma_m16n16k8_st_c_f32:
179 return MMA_LDST(8, m16n16k8_store_d_f32);
180
181 default:
182 llvm_unreachable("Unknown MMA builtin");
183 }
184}
185#undef MMA_LDST
186#undef MMA_INTR
187
188
189struct NVPTXMmaInfo {
190 unsigned NumEltsA;
191 unsigned NumEltsB;
192 unsigned NumEltsC;
193 unsigned NumEltsD;
194
195 // Variants are ordered by layout-A/layout-B/satf, where 'row' has priority
196 // over 'col' for layout. The index of non-satf variants is expected to match
197 // the undocumented layout constants used by CUDA's mma.hpp.
198 std::array<unsigned, 8> Variants;
199
200 unsigned getMMAIntrinsic(int Layout, bool Satf) {
201 unsigned Index = Layout + 4 * Satf;
202 if (Index >= Variants.size())
203 return 0;
204 return Variants[Index];
205 }
206};
207
208 // Returns an intrinsic that matches Layout and Satf for valid combinations of
209 // Layout and Satf, 0 otherwise.
210static NVPTXMmaInfo getNVPTXMmaInfo(unsigned BuiltinID) {
211 // clang-format off
212#define MMA_VARIANTS(geom, type) \
213 Intrinsic::nvvm_wmma_##geom##_mma_row_row_##type, \
214 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type, \
215 Intrinsic::nvvm_wmma_##geom##_mma_col_row_##type, \
216 Intrinsic::nvvm_wmma_##geom##_mma_col_col_##type
217#define MMA_SATF_VARIANTS(geom, type) \
218 MMA_VARIANTS(geom, type), \
219 Intrinsic::nvvm_wmma_##geom##_mma_row_row_##type##_satfinite, \
220 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type##_satfinite, \
221 Intrinsic::nvvm_wmma_##geom##_mma_col_row_##type##_satfinite, \
222 Intrinsic::nvvm_wmma_##geom##_mma_col_col_##type##_satfinite
223// Sub-integer MMA only supports row.col layout.
224#define MMA_VARIANTS_I4(geom, type) \
225 0, \
226 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type, \
227 0, \
228 0, \
229 0, \
230 Intrinsic::nvvm_wmma_##geom##_mma_row_col_##type##_satfinite, \
231 0, \
232 0
233// b1 MMA does not support .satfinite.
234#define MMA_VARIANTS_B1_XOR(geom, type) \
235 0, \
236 Intrinsic::nvvm_wmma_##geom##_mma_xor_popc_row_col_##type, \
237 0, \
238 0, \
239 0, \
240 0, \
241 0, \
242 0
243#define MMA_VARIANTS_B1_AND(geom, type) \
244 0, \
245 Intrinsic::nvvm_wmma_##geom##_mma_and_popc_row_col_##type, \
246 0, \
247 0, \
248 0, \
249 0, \
250 0, \
251 0
252 // clang-format on
253 switch (BuiltinID) {
254 // FP MMA
255 // Note that 'type' argument of MMA_SATF_VARIANTS uses D_C notation, while
256 // NumEltsN of return value are ordered as A,B,C,D.
257 case NVPTX::BI__hmma_m16n16k16_mma_f16f16:
258 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 4, .NumEltsD: 4, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m16n16k16, f16_f16)}}};
259 case NVPTX::BI__hmma_m16n16k16_mma_f32f16:
260 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 4, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m16n16k16, f32_f16)}}};
261 case NVPTX::BI__hmma_m16n16k16_mma_f16f32:
262 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 8, .NumEltsD: 4, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m16n16k16, f16_f32)}}};
263 case NVPTX::BI__hmma_m16n16k16_mma_f32f32:
264 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m16n16k16, f32_f32)}}};
265 case NVPTX::BI__hmma_m32n8k16_mma_f16f16:
266 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 4, .NumEltsD: 4, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m32n8k16, f16_f16)}}};
267 case NVPTX::BI__hmma_m32n8k16_mma_f32f16:
268 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 4, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m32n8k16, f32_f16)}}};
269 case NVPTX::BI__hmma_m32n8k16_mma_f16f32:
270 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 8, .NumEltsD: 4, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m32n8k16, f16_f32)}}};
271 case NVPTX::BI__hmma_m32n8k16_mma_f32f32:
272 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m32n8k16, f32_f32)}}};
273 case NVPTX::BI__hmma_m8n32k16_mma_f16f16:
274 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 4, .NumEltsD: 4, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m8n32k16, f16_f16)}}};
275 case NVPTX::BI__hmma_m8n32k16_mma_f32f16:
276 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 4, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m8n32k16, f32_f16)}}};
277 case NVPTX::BI__hmma_m8n32k16_mma_f16f32:
278 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 8, .NumEltsD: 4, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m8n32k16, f16_f32)}}};
279 case NVPTX::BI__hmma_m8n32k16_mma_f32f32:
280 return {.NumEltsA: 8, .NumEltsB: 8, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m8n32k16, f32_f32)}}};
281
282 // Integer MMA
283 case NVPTX::BI__imma_m16n16k16_mma_s8:
284 return {.NumEltsA: 2, .NumEltsB: 2, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m16n16k16, s8)}}};
285 case NVPTX::BI__imma_m16n16k16_mma_u8:
286 return {.NumEltsA: 2, .NumEltsB: 2, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m16n16k16, u8)}}};
287 case NVPTX::BI__imma_m32n8k16_mma_s8:
288 return {.NumEltsA: 4, .NumEltsB: 1, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m32n8k16, s8)}}};
289 case NVPTX::BI__imma_m32n8k16_mma_u8:
290 return {.NumEltsA: 4, .NumEltsB: 1, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m32n8k16, u8)}}};
291 case NVPTX::BI__imma_m8n32k16_mma_s8:
292 return {.NumEltsA: 1, .NumEltsB: 4, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m8n32k16, s8)}}};
293 case NVPTX::BI__imma_m8n32k16_mma_u8:
294 return {.NumEltsA: 1, .NumEltsB: 4, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_SATF_VARIANTS(m8n32k16, u8)}}};
295
296 // Sub-integer MMA
297 case NVPTX::BI__imma_m8n8k32_mma_s4:
298 return {.NumEltsA: 1, .NumEltsB: 1, .NumEltsC: 2, .NumEltsD: 2, .Variants: {._M_elems: {MMA_VARIANTS_I4(m8n8k32, s4)}}};
299 case NVPTX::BI__imma_m8n8k32_mma_u4:
300 return {.NumEltsA: 1, .NumEltsB: 1, .NumEltsC: 2, .NumEltsD: 2, .Variants: {._M_elems: {MMA_VARIANTS_I4(m8n8k32, u4)}}};
301 case NVPTX::BI__bmma_m8n8k128_mma_xor_popc_b1:
302 return {.NumEltsA: 1, .NumEltsB: 1, .NumEltsC: 2, .NumEltsD: 2, .Variants: {._M_elems: {MMA_VARIANTS_B1_XOR(m8n8k128, b1)}}};
303 case NVPTX::BI__bmma_m8n8k128_mma_and_popc_b1:
304 return {.NumEltsA: 1, .NumEltsB: 1, .NumEltsC: 2, .NumEltsD: 2, .Variants: {._M_elems: {MMA_VARIANTS_B1_AND(m8n8k128, b1)}}};
305
306 // Double MMA
307 case NVPTX::BI__dmma_m8n8k4_mma_f64:
308 return {.NumEltsA: 1, .NumEltsB: 1, .NumEltsC: 2, .NumEltsD: 2, .Variants: {._M_elems: {MMA_VARIANTS(m8n8k4, f64)}}};
309
310 // Alternate FP MMA
311 case NVPTX::BI__mma_bf16_m16n16k16_mma_f32:
312 return {.NumEltsA: 4, .NumEltsB: 4, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_VARIANTS(m16n16k16, bf16)}}};
313 case NVPTX::BI__mma_bf16_m8n32k16_mma_f32:
314 return {.NumEltsA: 2, .NumEltsB: 8, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_VARIANTS(m8n32k16, bf16)}}};
315 case NVPTX::BI__mma_bf16_m32n8k16_mma_f32:
316 return {.NumEltsA: 8, .NumEltsB: 2, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_VARIANTS(m32n8k16, bf16)}}};
317 case NVPTX::BI__mma_tf32_m16n16k8_mma_f32:
318 return {.NumEltsA: 4, .NumEltsB: 4, .NumEltsC: 8, .NumEltsD: 8, .Variants: {._M_elems: {MMA_VARIANTS(m16n16k8, tf32)}}};
319 default:
320 llvm_unreachable("Unexpected builtin ID.");
321 }
322#undef MMA_VARIANTS
323#undef MMA_SATF_VARIANTS
324#undef MMA_VARIANTS_I4
325#undef MMA_VARIANTS_B1_AND
326#undef MMA_VARIANTS_B1_XOR
327}
328
329static Value *MakeLdu(unsigned IntrinsicID, CodeGenFunction &CGF,
330 const CallExpr *E) {
331 Value *Ptr = CGF.EmitScalarExpr(E: E->getArg(Arg: 0));
332 QualType ArgType = E->getArg(Arg: 0)->getType();
333 clang::CharUnits Align = CGF.CGM.getNaturalPointeeTypeAlignment(T: ArgType);
334 llvm::Type *ElemTy = CGF.ConvertTypeForMem(T: ArgType->getPointeeType());
335 return CGF.Builder.CreateCall(
336 Callee: CGF.CGM.getIntrinsic(IID: IntrinsicID, Tys: {ElemTy, Ptr->getType()}),
337 Args: {Ptr, ConstantInt::get(Ty: CGF.Builder.getInt32Ty(), V: Align.getQuantity())});
338}
339
340static Value *MakeLdg(CodeGenFunction &CGF, const CallExpr *E) {
341 Value *Ptr = CGF.EmitScalarExpr(E: E->getArg(Arg: 0));
342 QualType ArgType = E->getArg(Arg: 0)->getType();
343 clang::CharUnits AlignV = CGF.CGM.getNaturalPointeeTypeAlignment(T: ArgType);
344 llvm::Type *ElemTy = CGF.ConvertTypeForMem(T: ArgType->getPointeeType());
345
346 // Use addrspace(1) for NVPTX ADDRESS_SPACE_GLOBAL
347 auto *ASC = CGF.Builder.CreateAddrSpaceCast(V: Ptr, DestTy: CGF.Builder.getPtrTy(AddrSpace: 1));
348 auto *LD = CGF.Builder.CreateAlignedLoad(Ty: ElemTy, Ptr: ASC, Align: AlignV.getAsAlign());
349 MDNode *MD = MDNode::get(Context&: CGF.Builder.getContext(), MDs: {});
350 LD->setMetadata(KindID: LLVMContext::MD_invariant_load, Node: MD);
351
352 return LD;
353}
354
355// Set `Scope` to:
356// - "block" for _cta builtins, and
357// - "" for _sys builtins.
358static Value *MakeScopedAtomicRMW(CodeGenFunction &CGF, const CallExpr *E,
359 llvm::AtomicRMWInst::BinOp Kind,
360 StringRef Scope) {
361 Address Ptr = CGF.EmitPointerWithAlignment(Addr: E->getArg(Arg: 0));
362 Value *Val = CGF.EmitScalarExpr(E: E->getArg(Arg: 1));
363 llvm::SyncScope::ID SSID = CGF.getLLVMContext().getOrInsertSyncScopeID(SSN: Scope);
364 return CGF.Builder.CreateAtomicRMW(Op: Kind, Addr: Ptr, Val,
365 Ordering: llvm::AtomicOrdering::Monotonic, SSID);
366}
367
368// Set `Scope` to:
369// - "block" for _cta builtins, and
370// - "" for _sys builtins.
371static Value *MakeScopedAtomicCAS(CodeGenFunction &CGF, const CallExpr *E,
372 StringRef Scope) {
373 Address Ptr = CGF.EmitPointerWithAlignment(Addr: E->getArg(Arg: 0));
374 Value *Cmp = CGF.EmitScalarExpr(E: E->getArg(Arg: 1));
375 Value *New = CGF.EmitScalarExpr(E: E->getArg(Arg: 2));
376 llvm::SyncScope::ID SSID = CGF.getLLVMContext().getOrInsertSyncScopeID(SSN: Scope);
377 Value *Pair = CGF.Builder.CreateAtomicCmpXchg(
378 Addr: Ptr, Cmp, New, SuccessOrdering: llvm::AtomicOrdering::Monotonic,
379 FailureOrdering: llvm::AtomicOrdering::Monotonic, SSID);
380 return CGF.Builder.CreateExtractValue(Agg: Pair, Idxs: 0);
381}
382
383static Value *MakeCpAsync(unsigned IntrinsicID, unsigned IntrinsicIDS,
384 CodeGenFunction &CGF, const CallExpr *E,
385 int SrcSize) {
386 return E->getNumArgs() == 3
387 ? CGF.Builder.CreateCall(Callee: CGF.CGM.getIntrinsic(IID: IntrinsicIDS),
388 Args: {CGF.EmitScalarExpr(E: E->getArg(Arg: 0)),
389 CGF.EmitScalarExpr(E: E->getArg(Arg: 1)),
390 CGF.EmitScalarExpr(E: E->getArg(Arg: 2))})
391 : CGF.Builder.CreateCall(Callee: CGF.CGM.getIntrinsic(IID: IntrinsicID),
392 Args: {CGF.EmitScalarExpr(E: E->getArg(Arg: 0)),
393 CGF.EmitScalarExpr(E: E->getArg(Arg: 1))});
394}
395
396static Value *MakeHalfType(Function *Intrinsic, unsigned BuiltinID,
397 const CallExpr *E, CodeGenFunction &CGF) {
398 SmallVector<Value *, 16> Args;
399 auto *FTy = Intrinsic->getFunctionType();
400 unsigned ICEArguments = 0;
401 ASTContext::GetBuiltinTypeError Error;
402 CGF.CGM.getContext().GetBuiltinType(ID: BuiltinID, Error, IntegerConstantArgs: &ICEArguments);
403 assert(Error == ASTContext::GE_None && "Should not codegen an error");
404 for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
405 assert((ICEArguments & (1 << i)) == 0);
406 auto *ArgValue = CGF.EmitScalarExpr(E: E->getArg(Arg: i));
407 auto *PTy = FTy->getParamType(i);
408 if (PTy != ArgValue->getType())
409 ArgValue = CGF.Builder.CreateBitCast(V: ArgValue, DestTy: PTy);
410 Args.push_back(Elt: ArgValue);
411 }
412
413 return CGF.Builder.CreateCall(Callee: Intrinsic, Args);
414}
415
416static Value *MakeHalfType(unsigned IntrinsicID, unsigned BuiltinID,
417 const CallExpr *E, CodeGenFunction &CGF) {
418 return MakeHalfType(Intrinsic: CGF.CGM.getIntrinsic(IID: IntrinsicID), BuiltinID, E, CGF);
419}
420
421static Value *MakeFMAOOB(unsigned IntrinsicID, llvm::Type *Ty,
422 const CallExpr *E, CodeGenFunction &CGF) {
423 return CGF.Builder.CreateCall(Callee: CGF.CGM.getIntrinsic(IID: IntrinsicID, Tys: {Ty}),
424 Args: {CGF.EmitScalarExpr(E: E->getArg(Arg: 0)),
425 CGF.EmitScalarExpr(E: E->getArg(Arg: 1)),
426 CGF.EmitScalarExpr(E: E->getArg(Arg: 2))});
427}
428
429} // namespace
430
431Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
432 const CallExpr *E) {
433 switch (BuiltinID) {
434 case NVPTX::BI__nvvm_atom_add_gen_i:
435 case NVPTX::BI__nvvm_atom_add_gen_l:
436 case NVPTX::BI__nvvm_atom_add_gen_ll:
437 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::Add, E,
438 Ordering: AtomicOrdering::Monotonic);
439
440 case NVPTX::BI__nvvm_atom_sub_gen_i:
441 case NVPTX::BI__nvvm_atom_sub_gen_l:
442 case NVPTX::BI__nvvm_atom_sub_gen_ll:
443 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::Sub, E,
444 Ordering: AtomicOrdering::Monotonic);
445
446 case NVPTX::BI__nvvm_atom_and_gen_i:
447 case NVPTX::BI__nvvm_atom_and_gen_l:
448 case NVPTX::BI__nvvm_atom_and_gen_ll:
449 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::And, E,
450 Ordering: AtomicOrdering::Monotonic);
451
452 case NVPTX::BI__nvvm_atom_or_gen_i:
453 case NVPTX::BI__nvvm_atom_or_gen_l:
454 case NVPTX::BI__nvvm_atom_or_gen_ll:
455 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::Or, E,
456 Ordering: AtomicOrdering::Monotonic);
457
458 case NVPTX::BI__nvvm_atom_xor_gen_i:
459 case NVPTX::BI__nvvm_atom_xor_gen_l:
460 case NVPTX::BI__nvvm_atom_xor_gen_ll:
461 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::Xor, E,
462 Ordering: AtomicOrdering::Monotonic);
463
464 case NVPTX::BI__nvvm_atom_xchg_gen_i:
465 case NVPTX::BI__nvvm_atom_xchg_gen_l:
466 case NVPTX::BI__nvvm_atom_xchg_gen_ll:
467 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::Xchg, E,
468 Ordering: AtomicOrdering::Monotonic);
469
470 case NVPTX::BI__nvvm_atom_max_gen_i:
471 case NVPTX::BI__nvvm_atom_max_gen_l:
472 case NVPTX::BI__nvvm_atom_max_gen_ll:
473 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::Max, E,
474 Ordering: AtomicOrdering::Monotonic);
475
476 case NVPTX::BI__nvvm_atom_max_gen_ui:
477 case NVPTX::BI__nvvm_atom_max_gen_ul:
478 case NVPTX::BI__nvvm_atom_max_gen_ull:
479 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::UMax, E,
480 Ordering: AtomicOrdering::Monotonic);
481
482 case NVPTX::BI__nvvm_atom_min_gen_i:
483 case NVPTX::BI__nvvm_atom_min_gen_l:
484 case NVPTX::BI__nvvm_atom_min_gen_ll:
485 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::Min, E,
486 Ordering: AtomicOrdering::Monotonic);
487
488 case NVPTX::BI__nvvm_atom_min_gen_ui:
489 case NVPTX::BI__nvvm_atom_min_gen_ul:
490 case NVPTX::BI__nvvm_atom_min_gen_ull:
491 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::UMin, E,
492 Ordering: AtomicOrdering::Monotonic);
493
494 case NVPTX::BI__nvvm_atom_cas_gen_us:
495 case NVPTX::BI__nvvm_atom_cas_gen_i:
496 case NVPTX::BI__nvvm_atom_cas_gen_l:
497 case NVPTX::BI__nvvm_atom_cas_gen_ll:
498 // __nvvm_atom_cas_gen_* should return the old value rather than the
499 // success flag.
500 return MakeAtomicCmpXchgValue(CGF&: *this, E, /*ReturnBool=*/false,
501 SuccessOrdering: AtomicOrdering::Monotonic,
502 FailureOrdering: AtomicOrdering::Monotonic);
503
504 case NVPTX::BI__nvvm_atom_add_gen_f:
505 case NVPTX::BI__nvvm_atom_add_gen_d: {
506 Address DestAddr = EmitPointerWithAlignment(Addr: E->getArg(Arg: 0));
507 Value *Val = EmitScalarExpr(E: E->getArg(Arg: 1));
508
509 return Builder.CreateAtomicRMW(Op: llvm::AtomicRMWInst::FAdd, Addr: DestAddr, Val,
510 Ordering: AtomicOrdering::Monotonic);
511 }
512
513 case NVPTX::BI__nvvm_atom_inc_gen_ui:
514 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::UIncWrap, E,
515 Ordering: AtomicOrdering::Monotonic);
516
517 case NVPTX::BI__nvvm_atom_dec_gen_ui:
518 return MakeBinaryAtomicValue(CGF&: *this, Kind: llvm::AtomicRMWInst::UDecWrap, E,
519 Ordering: AtomicOrdering::Monotonic);
520
521 case NVPTX::BI__nvvm_ldg_c:
522 case NVPTX::BI__nvvm_ldg_sc:
523 case NVPTX::BI__nvvm_ldg_c2:
524 case NVPTX::BI__nvvm_ldg_sc2:
525 case NVPTX::BI__nvvm_ldg_c4:
526 case NVPTX::BI__nvvm_ldg_sc4:
527 case NVPTX::BI__nvvm_ldg_s:
528 case NVPTX::BI__nvvm_ldg_s2:
529 case NVPTX::BI__nvvm_ldg_s4:
530 case NVPTX::BI__nvvm_ldg_i:
531 case NVPTX::BI__nvvm_ldg_i2:
532 case NVPTX::BI__nvvm_ldg_i4:
533 case NVPTX::BI__nvvm_ldg_l:
534 case NVPTX::BI__nvvm_ldg_l2:
535 case NVPTX::BI__nvvm_ldg_ll:
536 case NVPTX::BI__nvvm_ldg_ll2:
537 case NVPTX::BI__nvvm_ldg_uc:
538 case NVPTX::BI__nvvm_ldg_uc2:
539 case NVPTX::BI__nvvm_ldg_uc4:
540 case NVPTX::BI__nvvm_ldg_us:
541 case NVPTX::BI__nvvm_ldg_us2:
542 case NVPTX::BI__nvvm_ldg_us4:
543 case NVPTX::BI__nvvm_ldg_ui:
544 case NVPTX::BI__nvvm_ldg_ui2:
545 case NVPTX::BI__nvvm_ldg_ui4:
546 case NVPTX::BI__nvvm_ldg_ul:
547 case NVPTX::BI__nvvm_ldg_ul2:
548 case NVPTX::BI__nvvm_ldg_ull:
549 case NVPTX::BI__nvvm_ldg_ull2:
550 case NVPTX::BI__nvvm_ldg_f:
551 case NVPTX::BI__nvvm_ldg_f2:
552 case NVPTX::BI__nvvm_ldg_f4:
553 case NVPTX::BI__nvvm_ldg_d:
554 case NVPTX::BI__nvvm_ldg_d2:
555 // PTX Interoperability section 2.2: "For a vector with an even number of
556 // elements, its alignment is set to number of elements times the alignment
557 // of its member: n*alignof(t)."
558 return MakeLdg(CGF&: *this, E);
559
560 case NVPTX::BI__nvvm_ldu_c:
561 case NVPTX::BI__nvvm_ldu_sc:
562 case NVPTX::BI__nvvm_ldu_c2:
563 case NVPTX::BI__nvvm_ldu_sc2:
564 case NVPTX::BI__nvvm_ldu_c4:
565 case NVPTX::BI__nvvm_ldu_sc4:
566 case NVPTX::BI__nvvm_ldu_s:
567 case NVPTX::BI__nvvm_ldu_s2:
568 case NVPTX::BI__nvvm_ldu_s4:
569 case NVPTX::BI__nvvm_ldu_i:
570 case NVPTX::BI__nvvm_ldu_i2:
571 case NVPTX::BI__nvvm_ldu_i4:
572 case NVPTX::BI__nvvm_ldu_l:
573 case NVPTX::BI__nvvm_ldu_l2:
574 case NVPTX::BI__nvvm_ldu_ll:
575 case NVPTX::BI__nvvm_ldu_ll2:
576 case NVPTX::BI__nvvm_ldu_uc:
577 case NVPTX::BI__nvvm_ldu_uc2:
578 case NVPTX::BI__nvvm_ldu_uc4:
579 case NVPTX::BI__nvvm_ldu_us:
580 case NVPTX::BI__nvvm_ldu_us2:
581 case NVPTX::BI__nvvm_ldu_us4:
582 case NVPTX::BI__nvvm_ldu_ui:
583 case NVPTX::BI__nvvm_ldu_ui2:
584 case NVPTX::BI__nvvm_ldu_ui4:
585 case NVPTX::BI__nvvm_ldu_ul:
586 case NVPTX::BI__nvvm_ldu_ul2:
587 case NVPTX::BI__nvvm_ldu_ull:
588 case NVPTX::BI__nvvm_ldu_ull2:
589 return MakeLdu(IntrinsicID: Intrinsic::nvvm_ldu_global_i, CGF&: *this, E);
590 case NVPTX::BI__nvvm_ldu_f:
591 case NVPTX::BI__nvvm_ldu_f2:
592 case NVPTX::BI__nvvm_ldu_f4:
593 case NVPTX::BI__nvvm_ldu_d:
594 case NVPTX::BI__nvvm_ldu_d2:
595 return MakeLdu(IntrinsicID: Intrinsic::nvvm_ldu_global_f, CGF&: *this, E);
596
597 case NVPTX::BI__nvvm_atom_cta_add_gen_i:
598 case NVPTX::BI__nvvm_atom_cta_add_gen_l:
599 case NVPTX::BI__nvvm_atom_cta_add_gen_ll:
600 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Add, Scope: "block");
601 case NVPTX::BI__nvvm_atom_sys_add_gen_i:
602 case NVPTX::BI__nvvm_atom_sys_add_gen_l:
603 case NVPTX::BI__nvvm_atom_sys_add_gen_ll:
604 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Add, Scope: "");
605 case NVPTX::BI__nvvm_atom_cta_add_gen_f:
606 case NVPTX::BI__nvvm_atom_cta_add_gen_d:
607 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::FAdd, Scope: "block");
608 case NVPTX::BI__nvvm_atom_sys_add_gen_f:
609 case NVPTX::BI__nvvm_atom_sys_add_gen_d:
610 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::FAdd, Scope: "");
611 case NVPTX::BI__nvvm_atom_cta_xchg_gen_i:
612 case NVPTX::BI__nvvm_atom_cta_xchg_gen_l:
613 case NVPTX::BI__nvvm_atom_cta_xchg_gen_ll:
614 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Xchg, Scope: "block");
615 case NVPTX::BI__nvvm_atom_sys_xchg_gen_i:
616 case NVPTX::BI__nvvm_atom_sys_xchg_gen_l:
617 case NVPTX::BI__nvvm_atom_sys_xchg_gen_ll:
618 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Xchg, Scope: "");
619 case NVPTX::BI__nvvm_atom_cta_max_gen_i:
620 case NVPTX::BI__nvvm_atom_cta_max_gen_l:
621 case NVPTX::BI__nvvm_atom_cta_max_gen_ll:
622 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Max, Scope: "block");
623 case NVPTX::BI__nvvm_atom_cta_max_gen_ui:
624 case NVPTX::BI__nvvm_atom_cta_max_gen_ul:
625 case NVPTX::BI__nvvm_atom_cta_max_gen_ull:
626 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::UMax, Scope: "block");
627 case NVPTX::BI__nvvm_atom_sys_max_gen_i:
628 case NVPTX::BI__nvvm_atom_sys_max_gen_l:
629 case NVPTX::BI__nvvm_atom_sys_max_gen_ll:
630 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Max, Scope: "");
631 case NVPTX::BI__nvvm_atom_sys_max_gen_ui:
632 case NVPTX::BI__nvvm_atom_sys_max_gen_ul:
633 case NVPTX::BI__nvvm_atom_sys_max_gen_ull:
634 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::UMax, Scope: "");
635 case NVPTX::BI__nvvm_atom_cta_min_gen_i:
636 case NVPTX::BI__nvvm_atom_cta_min_gen_l:
637 case NVPTX::BI__nvvm_atom_cta_min_gen_ll:
638 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Min, Scope: "block");
639 case NVPTX::BI__nvvm_atom_cta_min_gen_ui:
640 case NVPTX::BI__nvvm_atom_cta_min_gen_ul:
641 case NVPTX::BI__nvvm_atom_cta_min_gen_ull:
642 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::UMin, Scope: "block");
643 case NVPTX::BI__nvvm_atom_sys_min_gen_i:
644 case NVPTX::BI__nvvm_atom_sys_min_gen_l:
645 case NVPTX::BI__nvvm_atom_sys_min_gen_ll:
646 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Min, Scope: "");
647 case NVPTX::BI__nvvm_atom_sys_min_gen_ui:
648 case NVPTX::BI__nvvm_atom_sys_min_gen_ul:
649 case NVPTX::BI__nvvm_atom_sys_min_gen_ull:
650 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::UMin, Scope: "");
651 case NVPTX::BI__nvvm_atom_cta_inc_gen_ui:
652 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::UIncWrap,
653 Scope: "block");
654 case NVPTX::BI__nvvm_atom_cta_dec_gen_ui:
655 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::UDecWrap,
656 Scope: "block");
657 case NVPTX::BI__nvvm_atom_sys_inc_gen_ui:
658 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::UIncWrap, Scope: "");
659 case NVPTX::BI__nvvm_atom_sys_dec_gen_ui:
660 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::UDecWrap, Scope: "");
661 case NVPTX::BI__nvvm_atom_cta_and_gen_i:
662 case NVPTX::BI__nvvm_atom_cta_and_gen_l:
663 case NVPTX::BI__nvvm_atom_cta_and_gen_ll:
664 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::And, Scope: "block");
665 case NVPTX::BI__nvvm_atom_sys_and_gen_i:
666 case NVPTX::BI__nvvm_atom_sys_and_gen_l:
667 case NVPTX::BI__nvvm_atom_sys_and_gen_ll:
668 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::And, Scope: "");
669 case NVPTX::BI__nvvm_atom_cta_or_gen_i:
670 case NVPTX::BI__nvvm_atom_cta_or_gen_l:
671 case NVPTX::BI__nvvm_atom_cta_or_gen_ll:
672 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Or, Scope: "block");
673 case NVPTX::BI__nvvm_atom_sys_or_gen_i:
674 case NVPTX::BI__nvvm_atom_sys_or_gen_l:
675 case NVPTX::BI__nvvm_atom_sys_or_gen_ll:
676 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Or, Scope: "");
677 case NVPTX::BI__nvvm_atom_cta_xor_gen_i:
678 case NVPTX::BI__nvvm_atom_cta_xor_gen_l:
679 case NVPTX::BI__nvvm_atom_cta_xor_gen_ll:
680 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Xor, Scope: "block");
681 case NVPTX::BI__nvvm_atom_sys_xor_gen_i:
682 case NVPTX::BI__nvvm_atom_sys_xor_gen_l:
683 case NVPTX::BI__nvvm_atom_sys_xor_gen_ll:
684 return MakeScopedAtomicRMW(CGF&: *this, E, Kind: llvm::AtomicRMWInst::Xor, Scope: "");
685 case NVPTX::BI__nvvm_atom_cta_cas_gen_us:
686 case NVPTX::BI__nvvm_atom_cta_cas_gen_i:
687 case NVPTX::BI__nvvm_atom_cta_cas_gen_l:
688 case NVPTX::BI__nvvm_atom_cta_cas_gen_ll:
689 return MakeScopedAtomicCAS(CGF&: *this, E, Scope: "block");
690 case NVPTX::BI__nvvm_atom_sys_cas_gen_us:
691 case NVPTX::BI__nvvm_atom_sys_cas_gen_i:
692 case NVPTX::BI__nvvm_atom_sys_cas_gen_l:
693 case NVPTX::BI__nvvm_atom_sys_cas_gen_ll:
694 return MakeScopedAtomicCAS(CGF&: *this, E, Scope: "");
695 case NVPTX::BI__nvvm_match_all_sync_i32p:
696 case NVPTX::BI__nvvm_match_all_sync_i64p: {
697 Value *Mask = EmitScalarExpr(E: E->getArg(Arg: 0));
698 Value *Val = EmitScalarExpr(E: E->getArg(Arg: 1));
699 Address PredOutPtr = EmitPointerWithAlignment(Addr: E->getArg(Arg: 2));
700 Value *ResultPair = Builder.CreateCall(
701 Callee: CGM.getIntrinsic(IID: BuiltinID == NVPTX::BI__nvvm_match_all_sync_i32p
702 ? Intrinsic::nvvm_match_all_sync_i32p
703 : Intrinsic::nvvm_match_all_sync_i64p),
704 Args: {Mask, Val});
705 Value *Pred = Builder.CreateZExt(V: Builder.CreateExtractValue(Agg: ResultPair, Idxs: 1),
706 DestTy: PredOutPtr.getElementType());
707 Builder.CreateStore(Val: Pred, Addr: PredOutPtr);
708 return Builder.CreateExtractValue(Agg: ResultPair, Idxs: 0);
709 }
710
711 // FP MMA loads
712 case NVPTX::BI__hmma_m16n16k16_ld_a:
713 case NVPTX::BI__hmma_m16n16k16_ld_b:
714 case NVPTX::BI__hmma_m16n16k16_ld_c_f16:
715 case NVPTX::BI__hmma_m16n16k16_ld_c_f32:
716 case NVPTX::BI__hmma_m32n8k16_ld_a:
717 case NVPTX::BI__hmma_m32n8k16_ld_b:
718 case NVPTX::BI__hmma_m32n8k16_ld_c_f16:
719 case NVPTX::BI__hmma_m32n8k16_ld_c_f32:
720 case NVPTX::BI__hmma_m8n32k16_ld_a:
721 case NVPTX::BI__hmma_m8n32k16_ld_b:
722 case NVPTX::BI__hmma_m8n32k16_ld_c_f16:
723 case NVPTX::BI__hmma_m8n32k16_ld_c_f32:
724 // Integer MMA loads.
725 case NVPTX::BI__imma_m16n16k16_ld_a_s8:
726 case NVPTX::BI__imma_m16n16k16_ld_a_u8:
727 case NVPTX::BI__imma_m16n16k16_ld_b_s8:
728 case NVPTX::BI__imma_m16n16k16_ld_b_u8:
729 case NVPTX::BI__imma_m16n16k16_ld_c:
730 case NVPTX::BI__imma_m32n8k16_ld_a_s8:
731 case NVPTX::BI__imma_m32n8k16_ld_a_u8:
732 case NVPTX::BI__imma_m32n8k16_ld_b_s8:
733 case NVPTX::BI__imma_m32n8k16_ld_b_u8:
734 case NVPTX::BI__imma_m32n8k16_ld_c:
735 case NVPTX::BI__imma_m8n32k16_ld_a_s8:
736 case NVPTX::BI__imma_m8n32k16_ld_a_u8:
737 case NVPTX::BI__imma_m8n32k16_ld_b_s8:
738 case NVPTX::BI__imma_m8n32k16_ld_b_u8:
739 case NVPTX::BI__imma_m8n32k16_ld_c:
740 // Sub-integer MMA loads.
741 case NVPTX::BI__imma_m8n8k32_ld_a_s4:
742 case NVPTX::BI__imma_m8n8k32_ld_a_u4:
743 case NVPTX::BI__imma_m8n8k32_ld_b_s4:
744 case NVPTX::BI__imma_m8n8k32_ld_b_u4:
745 case NVPTX::BI__imma_m8n8k32_ld_c:
746 case NVPTX::BI__bmma_m8n8k128_ld_a_b1:
747 case NVPTX::BI__bmma_m8n8k128_ld_b_b1:
748 case NVPTX::BI__bmma_m8n8k128_ld_c:
749 // Double MMA loads.
750 case NVPTX::BI__dmma_m8n8k4_ld_a:
751 case NVPTX::BI__dmma_m8n8k4_ld_b:
752 case NVPTX::BI__dmma_m8n8k4_ld_c:
753 // Alternate float MMA loads.
754 case NVPTX::BI__mma_bf16_m16n16k16_ld_a:
755 case NVPTX::BI__mma_bf16_m16n16k16_ld_b:
756 case NVPTX::BI__mma_bf16_m8n32k16_ld_a:
757 case NVPTX::BI__mma_bf16_m8n32k16_ld_b:
758 case NVPTX::BI__mma_bf16_m32n8k16_ld_a:
759 case NVPTX::BI__mma_bf16_m32n8k16_ld_b:
760 case NVPTX::BI__mma_tf32_m16n16k8_ld_a:
761 case NVPTX::BI__mma_tf32_m16n16k8_ld_b:
762 case NVPTX::BI__mma_tf32_m16n16k8_ld_c: {
763 Address Dst = EmitPointerWithAlignment(Addr: E->getArg(Arg: 0));
764 Value *Src = EmitScalarExpr(E: E->getArg(Arg: 1));
765 Value *Ldm = EmitScalarExpr(E: E->getArg(Arg: 2));
766 std::optional<llvm::APSInt> isColMajorArg =
767 E->getArg(Arg: 3)->getIntegerConstantExpr(Ctx: getContext());
768 if (!isColMajorArg)
769 return nullptr;
770 bool isColMajor = isColMajorArg->getSExtValue();
771 NVPTXMmaLdstInfo II = getNVPTXMmaLdstInfo(BuiltinID);
772 unsigned IID = isColMajor ? II.IID_col : II.IID_row;
773 if (IID == 0)
774 return nullptr;
775
776 Value *Result =
777 Builder.CreateCall(Callee: CGM.getIntrinsic(IID, Tys: Src->getType()), Args: {Src, Ldm});
778
779 // Save returned values.
780 assert(II.NumResults);
781 if (II.NumResults == 1) {
782 Builder.CreateAlignedStore(Val: Result, Addr: Dst.emitRawPointer(CGF&: *this),
783 Align: CharUnits::fromQuantity(Quantity: 4));
784 } else {
785 for (unsigned i = 0; i < II.NumResults; ++i) {
786 Builder.CreateAlignedStore(
787 Val: Builder.CreateBitCast(V: Builder.CreateExtractValue(Agg: Result, Idxs: i),
788 DestTy: Dst.getElementType()),
789 Addr: Builder.CreateGEP(Ty: Dst.getElementType(), Ptr: Dst.emitRawPointer(CGF&: *this),
790 IdxList: llvm::ConstantInt::get(Ty: IntTy, V: i)),
791 Align: CharUnits::fromQuantity(Quantity: 4));
792 }
793 }
794 return Result;
795 }
796
797 case NVPTX::BI__hmma_m16n16k16_st_c_f16:
798 case NVPTX::BI__hmma_m16n16k16_st_c_f32:
799 case NVPTX::BI__hmma_m32n8k16_st_c_f16:
800 case NVPTX::BI__hmma_m32n8k16_st_c_f32:
801 case NVPTX::BI__hmma_m8n32k16_st_c_f16:
802 case NVPTX::BI__hmma_m8n32k16_st_c_f32:
803 case NVPTX::BI__imma_m16n16k16_st_c_i32:
804 case NVPTX::BI__imma_m32n8k16_st_c_i32:
805 case NVPTX::BI__imma_m8n32k16_st_c_i32:
806 case NVPTX::BI__imma_m8n8k32_st_c_i32:
807 case NVPTX::BI__bmma_m8n8k128_st_c_i32:
808 case NVPTX::BI__dmma_m8n8k4_st_c_f64:
809 case NVPTX::BI__mma_m16n16k8_st_c_f32: {
810 Value *Dst = EmitScalarExpr(E: E->getArg(Arg: 0));
811 Address Src = EmitPointerWithAlignment(Addr: E->getArg(Arg: 1));
812 Value *Ldm = EmitScalarExpr(E: E->getArg(Arg: 2));
813 std::optional<llvm::APSInt> isColMajorArg =
814 E->getArg(Arg: 3)->getIntegerConstantExpr(Ctx: getContext());
815 if (!isColMajorArg)
816 return nullptr;
817 bool isColMajor = isColMajorArg->getSExtValue();
818 NVPTXMmaLdstInfo II = getNVPTXMmaLdstInfo(BuiltinID);
819 unsigned IID = isColMajor ? II.IID_col : II.IID_row;
820 if (IID == 0)
821 return nullptr;
822 Function *Intrinsic =
823 CGM.getIntrinsic(IID, Tys: Dst->getType());
824 llvm::Type *ParamType = Intrinsic->getFunctionType()->getParamType(i: 1);
825 SmallVector<Value *, 10> Values = {Dst};
826 for (unsigned i = 0; i < II.NumResults; ++i) {
827 Value *V = Builder.CreateAlignedLoad(
828 Ty: Src.getElementType(),
829 Addr: Builder.CreateGEP(Ty: Src.getElementType(), Ptr: Src.emitRawPointer(CGF&: *this),
830 IdxList: llvm::ConstantInt::get(Ty: IntTy, V: i)),
831 Align: CharUnits::fromQuantity(Quantity: 4));
832 Values.push_back(Elt: Builder.CreateBitCast(V, DestTy: ParamType));
833 }
834 Values.push_back(Elt: Ldm);
835 Value *Result = Builder.CreateCall(Callee: Intrinsic, Args: Values);
836 return Result;
837 }
838
839 // BI__hmma_m16n16k16_mma_<Dtype><CType>(d, a, b, c, layout, satf) -->
840 // Intrinsic::nvvm_wmma_m16n16k16_mma_sync<layout A,B><DType><CType><Satf>
841 case NVPTX::BI__hmma_m16n16k16_mma_f16f16:
842 case NVPTX::BI__hmma_m16n16k16_mma_f32f16:
843 case NVPTX::BI__hmma_m16n16k16_mma_f32f32:
844 case NVPTX::BI__hmma_m16n16k16_mma_f16f32:
845 case NVPTX::BI__hmma_m32n8k16_mma_f16f16:
846 case NVPTX::BI__hmma_m32n8k16_mma_f32f16:
847 case NVPTX::BI__hmma_m32n8k16_mma_f32f32:
848 case NVPTX::BI__hmma_m32n8k16_mma_f16f32:
849 case NVPTX::BI__hmma_m8n32k16_mma_f16f16:
850 case NVPTX::BI__hmma_m8n32k16_mma_f32f16:
851 case NVPTX::BI__hmma_m8n32k16_mma_f32f32:
852 case NVPTX::BI__hmma_m8n32k16_mma_f16f32:
853 case NVPTX::BI__imma_m16n16k16_mma_s8:
854 case NVPTX::BI__imma_m16n16k16_mma_u8:
855 case NVPTX::BI__imma_m32n8k16_mma_s8:
856 case NVPTX::BI__imma_m32n8k16_mma_u8:
857 case NVPTX::BI__imma_m8n32k16_mma_s8:
858 case NVPTX::BI__imma_m8n32k16_mma_u8:
859 case NVPTX::BI__imma_m8n8k32_mma_s4:
860 case NVPTX::BI__imma_m8n8k32_mma_u4:
861 case NVPTX::BI__bmma_m8n8k128_mma_xor_popc_b1:
862 case NVPTX::BI__bmma_m8n8k128_mma_and_popc_b1:
863 case NVPTX::BI__dmma_m8n8k4_mma_f64:
864 case NVPTX::BI__mma_bf16_m16n16k16_mma_f32:
865 case NVPTX::BI__mma_bf16_m8n32k16_mma_f32:
866 case NVPTX::BI__mma_bf16_m32n8k16_mma_f32:
867 case NVPTX::BI__mma_tf32_m16n16k8_mma_f32: {
868 Address Dst = EmitPointerWithAlignment(Addr: E->getArg(Arg: 0));
869 Address SrcA = EmitPointerWithAlignment(Addr: E->getArg(Arg: 1));
870 Address SrcB = EmitPointerWithAlignment(Addr: E->getArg(Arg: 2));
871 Address SrcC = EmitPointerWithAlignment(Addr: E->getArg(Arg: 3));
872 std::optional<llvm::APSInt> LayoutArg =
873 E->getArg(Arg: 4)->getIntegerConstantExpr(Ctx: getContext());
874 if (!LayoutArg)
875 return nullptr;
876 int Layout = LayoutArg->getSExtValue();
877 if (Layout < 0 || Layout > 3)
878 return nullptr;
879 llvm::APSInt SatfArg;
880 if (BuiltinID == NVPTX::BI__bmma_m8n8k128_mma_xor_popc_b1 ||
881 BuiltinID == NVPTX::BI__bmma_m8n8k128_mma_and_popc_b1)
882 SatfArg = 0; // .b1 does not have satf argument.
883 else if (std::optional<llvm::APSInt> OptSatfArg =
884 E->getArg(Arg: 5)->getIntegerConstantExpr(Ctx: getContext()))
885 SatfArg = *OptSatfArg;
886 else
887 return nullptr;
888 bool Satf = SatfArg.getSExtValue();
889 NVPTXMmaInfo MI = getNVPTXMmaInfo(BuiltinID);
890 unsigned IID = MI.getMMAIntrinsic(Layout, Satf);
891 if (IID == 0) // Unsupported combination of Layout/Satf.
892 return nullptr;
893
894 SmallVector<Value *, 24> Values;
895 Function *Intrinsic = CGM.getIntrinsic(IID);
896 llvm::Type *AType = Intrinsic->getFunctionType()->getParamType(i: 0);
897 // Load A
898 for (unsigned i = 0; i < MI.NumEltsA; ++i) {
899 Value *V = Builder.CreateAlignedLoad(
900 Ty: SrcA.getElementType(),
901 Addr: Builder.CreateGEP(Ty: SrcA.getElementType(), Ptr: SrcA.emitRawPointer(CGF&: *this),
902 IdxList: llvm::ConstantInt::get(Ty: IntTy, V: i)),
903 Align: CharUnits::fromQuantity(Quantity: 4));
904 Values.push_back(Elt: Builder.CreateBitCast(V, DestTy: AType));
905 }
906 // Load B
907 llvm::Type *BType = Intrinsic->getFunctionType()->getParamType(i: MI.NumEltsA);
908 for (unsigned i = 0; i < MI.NumEltsB; ++i) {
909 Value *V = Builder.CreateAlignedLoad(
910 Ty: SrcB.getElementType(),
911 Addr: Builder.CreateGEP(Ty: SrcB.getElementType(), Ptr: SrcB.emitRawPointer(CGF&: *this),
912 IdxList: llvm::ConstantInt::get(Ty: IntTy, V: i)),
913 Align: CharUnits::fromQuantity(Quantity: 4));
914 Values.push_back(Elt: Builder.CreateBitCast(V, DestTy: BType));
915 }
916 // Load C
917 llvm::Type *CType =
918 Intrinsic->getFunctionType()->getParamType(i: MI.NumEltsA + MI.NumEltsB);
919 for (unsigned i = 0; i < MI.NumEltsC; ++i) {
920 Value *V = Builder.CreateAlignedLoad(
921 Ty: SrcC.getElementType(),
922 Addr: Builder.CreateGEP(Ty: SrcC.getElementType(), Ptr: SrcC.emitRawPointer(CGF&: *this),
923 IdxList: llvm::ConstantInt::get(Ty: IntTy, V: i)),
924 Align: CharUnits::fromQuantity(Quantity: 4));
925 Values.push_back(Elt: Builder.CreateBitCast(V, DestTy: CType));
926 }
927 Value *Result = Builder.CreateCall(Callee: Intrinsic, Args: Values);
928 llvm::Type *DType = Dst.getElementType();
929 for (unsigned i = 0; i < MI.NumEltsD; ++i)
930 Builder.CreateAlignedStore(
931 Val: Builder.CreateBitCast(V: Builder.CreateExtractValue(Agg: Result, Idxs: i), DestTy: DType),
932 Addr: Builder.CreateGEP(Ty: Dst.getElementType(), Ptr: Dst.emitRawPointer(CGF&: *this),
933 IdxList: llvm::ConstantInt::get(Ty: IntTy, V: i)),
934 Align: CharUnits::fromQuantity(Quantity: 4));
935 return Result;
936 }
937 // The following builtins require half type support
938 case NVPTX::BI__nvvm_ex2_approx_f16:
939 return MakeHalfType(
940 Intrinsic: CGM.getIntrinsic(IID: Intrinsic::nvvm_ex2_approx, Tys: Builder.getHalfTy()),
941 BuiltinID, E, CGF&: *this);
942 case NVPTX::BI__nvvm_ex2_approx_f16x2:
943 return MakeHalfType(
944 Intrinsic: CGM.getIntrinsic(IID: Intrinsic::nvvm_ex2_approx,
945 Tys: FixedVectorType::get(ElementType: Builder.getHalfTy(), NumElts: 2)),
946 BuiltinID, E, CGF&: *this);
947 case NVPTX::BI__nvvm_ff2f16x2_rn:
948 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_ff2f16x2_rn, BuiltinID, E, CGF&: *this);
949 case NVPTX::BI__nvvm_ff2f16x2_rn_relu:
950 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_ff2f16x2_rn_relu, BuiltinID, E, CGF&: *this);
951 case NVPTX::BI__nvvm_ff2f16x2_rz:
952 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_ff2f16x2_rz, BuiltinID, E, CGF&: *this);
953 case NVPTX::BI__nvvm_ff2f16x2_rz_relu:
954 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_ff2f16x2_rz_relu, BuiltinID, E, CGF&: *this);
955 case NVPTX::BI__nvvm_fma_rn_f16:
956 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_f16, BuiltinID, E, CGF&: *this);
957 case NVPTX::BI__nvvm_fma_rn_f16x2:
958 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_f16x2, BuiltinID, E, CGF&: *this);
959 case NVPTX::BI__nvvm_fma_rn_ftz_f16:
960 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_ftz_f16, BuiltinID, E, CGF&: *this);
961 case NVPTX::BI__nvvm_fma_rn_ftz_f16x2:
962 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_ftz_f16x2, BuiltinID, E, CGF&: *this);
963 case NVPTX::BI__nvvm_fma_rn_ftz_relu_f16:
964 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_ftz_relu_f16, BuiltinID, E,
965 CGF&: *this);
966 case NVPTX::BI__nvvm_fma_rn_ftz_relu_f16x2:
967 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_ftz_relu_f16x2, BuiltinID, E,
968 CGF&: *this);
969 case NVPTX::BI__nvvm_fma_rn_ftz_sat_f16:
970 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_ftz_sat_f16, BuiltinID, E,
971 CGF&: *this);
972 case NVPTX::BI__nvvm_fma_rn_ftz_sat_f16x2:
973 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_ftz_sat_f16x2, BuiltinID, E,
974 CGF&: *this);
975 case NVPTX::BI__nvvm_fma_rn_relu_f16:
976 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_relu_f16, BuiltinID, E, CGF&: *this);
977 case NVPTX::BI__nvvm_fma_rn_relu_f16x2:
978 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_relu_f16x2, BuiltinID, E, CGF&: *this);
979 case NVPTX::BI__nvvm_fma_rn_sat_f16:
980 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_sat_f16, BuiltinID, E, CGF&: *this);
981 case NVPTX::BI__nvvm_fma_rn_sat_f16x2:
982 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fma_rn_sat_f16x2, BuiltinID, E, CGF&: *this);
983 case NVPTX::BI__nvvm_fma_rn_oob_f16:
984 return MakeFMAOOB(IntrinsicID: Intrinsic::nvvm_fma_rn_oob, Ty: Builder.getHalfTy(), E,
985 CGF&: *this);
986 case NVPTX::BI__nvvm_fma_rn_oob_f16x2:
987 return MakeFMAOOB(IntrinsicID: Intrinsic::nvvm_fma_rn_oob,
988 Ty: llvm::FixedVectorType::get(ElementType: Builder.getHalfTy(), NumElts: 2), E,
989 CGF&: *this);
990 case NVPTX::BI__nvvm_fma_rn_oob_bf16:
991 return MakeFMAOOB(IntrinsicID: Intrinsic::nvvm_fma_rn_oob, Ty: Builder.getBFloatTy(), E,
992 CGF&: *this);
993 case NVPTX::BI__nvvm_fma_rn_oob_bf16x2:
994 return MakeFMAOOB(IntrinsicID: Intrinsic::nvvm_fma_rn_oob,
995 Ty: llvm::FixedVectorType::get(ElementType: Builder.getBFloatTy(), NumElts: 2), E,
996 CGF&: *this);
997 case NVPTX::BI__nvvm_fma_rn_oob_relu_f16:
998 return MakeFMAOOB(IntrinsicID: Intrinsic::nvvm_fma_rn_oob_relu, Ty: Builder.getHalfTy(), E,
999 CGF&: *this);
1000 case NVPTX::BI__nvvm_fma_rn_oob_relu_f16x2:
1001 return MakeFMAOOB(IntrinsicID: Intrinsic::nvvm_fma_rn_oob_relu,
1002 Ty: llvm::FixedVectorType::get(ElementType: Builder.getHalfTy(), NumElts: 2), E,
1003 CGF&: *this);
1004 case NVPTX::BI__nvvm_fma_rn_oob_relu_bf16:
1005 return MakeFMAOOB(IntrinsicID: Intrinsic::nvvm_fma_rn_oob_relu, Ty: Builder.getBFloatTy(), E,
1006 CGF&: *this);
1007 case NVPTX::BI__nvvm_fma_rn_oob_relu_bf16x2:
1008 return MakeFMAOOB(IntrinsicID: Intrinsic::nvvm_fma_rn_oob_relu,
1009 Ty: llvm::FixedVectorType::get(ElementType: Builder.getBFloatTy(), NumElts: 2), E,
1010 CGF&: *this);
1011 case NVPTX::BI__nvvm_fmax_f16:
1012 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_f16, BuiltinID, E, CGF&: *this);
1013 case NVPTX::BI__nvvm_fmax_f16x2:
1014 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_f16x2, BuiltinID, E, CGF&: *this);
1015 case NVPTX::BI__nvvm_fmax_ftz_f16:
1016 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_ftz_f16, BuiltinID, E, CGF&: *this);
1017 case NVPTX::BI__nvvm_fmax_ftz_f16x2:
1018 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_ftz_f16x2, BuiltinID, E, CGF&: *this);
1019 case NVPTX::BI__nvvm_fmax_ftz_nan_f16:
1020 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_ftz_nan_f16, BuiltinID, E, CGF&: *this);
1021 case NVPTX::BI__nvvm_fmax_ftz_nan_f16x2:
1022 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_ftz_nan_f16x2, BuiltinID, E,
1023 CGF&: *this);
1024 case NVPTX::BI__nvvm_fmax_ftz_nan_xorsign_abs_f16:
1025 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f16, BuiltinID,
1026 E, CGF&: *this);
1027 case NVPTX::BI__nvvm_fmax_ftz_nan_xorsign_abs_f16x2:
1028 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_ftz_nan_xorsign_abs_f16x2,
1029 BuiltinID, E, CGF&: *this);
1030 case NVPTX::BI__nvvm_fmax_ftz_xorsign_abs_f16:
1031 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_ftz_xorsign_abs_f16, BuiltinID, E,
1032 CGF&: *this);
1033 case NVPTX::BI__nvvm_fmax_ftz_xorsign_abs_f16x2:
1034 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_ftz_xorsign_abs_f16x2, BuiltinID,
1035 E, CGF&: *this);
1036 case NVPTX::BI__nvvm_fmax_nan_f16:
1037 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_nan_f16, BuiltinID, E, CGF&: *this);
1038 case NVPTX::BI__nvvm_fmax_nan_f16x2:
1039 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_nan_f16x2, BuiltinID, E, CGF&: *this);
1040 case NVPTX::BI__nvvm_fmax_nan_xorsign_abs_f16:
1041 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_nan_xorsign_abs_f16, BuiltinID, E,
1042 CGF&: *this);
1043 case NVPTX::BI__nvvm_fmax_nan_xorsign_abs_f16x2:
1044 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_nan_xorsign_abs_f16x2, BuiltinID,
1045 E, CGF&: *this);
1046 case NVPTX::BI__nvvm_fmax_xorsign_abs_f16:
1047 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_xorsign_abs_f16, BuiltinID, E,
1048 CGF&: *this);
1049 case NVPTX::BI__nvvm_fmax_xorsign_abs_f16x2:
1050 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmax_xorsign_abs_f16x2, BuiltinID, E,
1051 CGF&: *this);
1052 case NVPTX::BI__nvvm_fmin_f16:
1053 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_f16, BuiltinID, E, CGF&: *this);
1054 case NVPTX::BI__nvvm_fmin_f16x2:
1055 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_f16x2, BuiltinID, E, CGF&: *this);
1056 case NVPTX::BI__nvvm_fmin_ftz_f16:
1057 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_ftz_f16, BuiltinID, E, CGF&: *this);
1058 case NVPTX::BI__nvvm_fmin_ftz_f16x2:
1059 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_ftz_f16x2, BuiltinID, E, CGF&: *this);
1060 case NVPTX::BI__nvvm_fmin_ftz_nan_f16:
1061 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_ftz_nan_f16, BuiltinID, E, CGF&: *this);
1062 case NVPTX::BI__nvvm_fmin_ftz_nan_f16x2:
1063 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_ftz_nan_f16x2, BuiltinID, E,
1064 CGF&: *this);
1065 case NVPTX::BI__nvvm_fmin_ftz_nan_xorsign_abs_f16:
1066 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f16, BuiltinID,
1067 E, CGF&: *this);
1068 case NVPTX::BI__nvvm_fmin_ftz_nan_xorsign_abs_f16x2:
1069 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_ftz_nan_xorsign_abs_f16x2,
1070 BuiltinID, E, CGF&: *this);
1071 case NVPTX::BI__nvvm_fmin_ftz_xorsign_abs_f16:
1072 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_ftz_xorsign_abs_f16, BuiltinID, E,
1073 CGF&: *this);
1074 case NVPTX::BI__nvvm_fmin_ftz_xorsign_abs_f16x2:
1075 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_ftz_xorsign_abs_f16x2, BuiltinID,
1076 E, CGF&: *this);
1077 case NVPTX::BI__nvvm_fmin_nan_f16:
1078 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_nan_f16, BuiltinID, E, CGF&: *this);
1079 case NVPTX::BI__nvvm_fmin_nan_f16x2:
1080 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_nan_f16x2, BuiltinID, E, CGF&: *this);
1081 case NVPTX::BI__nvvm_fmin_nan_xorsign_abs_f16:
1082 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_nan_xorsign_abs_f16, BuiltinID, E,
1083 CGF&: *this);
1084 case NVPTX::BI__nvvm_fmin_nan_xorsign_abs_f16x2:
1085 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_nan_xorsign_abs_f16x2, BuiltinID,
1086 E, CGF&: *this);
1087 case NVPTX::BI__nvvm_fmin_xorsign_abs_f16:
1088 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_xorsign_abs_f16, BuiltinID, E,
1089 CGF&: *this);
1090 case NVPTX::BI__nvvm_fmin_xorsign_abs_f16x2:
1091 return MakeHalfType(IntrinsicID: Intrinsic::nvvm_fmin_xorsign_abs_f16x2, BuiltinID, E,
1092 CGF&: *this);
1093 case NVPTX::BI__nvvm_fabs_f:
1094 case NVPTX::BI__nvvm_abs_bf16:
1095 case NVPTX::BI__nvvm_abs_bf16x2:
1096 case NVPTX::BI__nvvm_fabs_f16:
1097 case NVPTX::BI__nvvm_fabs_f16x2:
1098 return Builder.CreateUnaryIntrinsic(ID: Intrinsic::nvvm_fabs,
1099 Op: EmitScalarExpr(E: E->getArg(Arg: 0)));
1100 case NVPTX::BI__nvvm_fabs_ftz_f:
1101 case NVPTX::BI__nvvm_fabs_ftz_f16:
1102 case NVPTX::BI__nvvm_fabs_ftz_f16x2:
1103 return Builder.CreateUnaryIntrinsic(ID: Intrinsic::nvvm_fabs_ftz,
1104 Op: EmitScalarExpr(E: E->getArg(Arg: 0)));
1105 case NVPTX::BI__nvvm_fabs_d:
1106 return Builder.CreateFAbs(V: EmitScalarExpr(E: E->getArg(Arg: 0)));
1107 case NVPTX::BI__nvvm_ex2_approx_d:
1108 case NVPTX::BI__nvvm_ex2_approx_f:
1109 return Builder.CreateUnaryIntrinsic(ID: Intrinsic::nvvm_ex2_approx,
1110 Op: EmitScalarExpr(E: E->getArg(Arg: 0)));
1111 case NVPTX::BI__nvvm_ex2_approx_ftz_f:
1112 return Builder.CreateUnaryIntrinsic(ID: Intrinsic::nvvm_ex2_approx_ftz,
1113 Op: EmitScalarExpr(E: E->getArg(Arg: 0)));
1114 case NVPTX::BI__nvvm_ldg_h:
1115 case NVPTX::BI__nvvm_ldg_h2:
1116 return MakeLdg(CGF&: *this, E);
1117 case NVPTX::BI__nvvm_ldu_h:
1118 case NVPTX::BI__nvvm_ldu_h2:
1119 return MakeLdu(IntrinsicID: Intrinsic::nvvm_ldu_global_f, CGF&: *this, E);
1120 case NVPTX::BI__nvvm_cp_async_ca_shared_global_4:
1121 return MakeCpAsync(IntrinsicID: Intrinsic::nvvm_cp_async_ca_shared_global_4,
1122 IntrinsicIDS: Intrinsic::nvvm_cp_async_ca_shared_global_4_s, CGF&: *this, E,
1123 SrcSize: 4);
1124 case NVPTX::BI__nvvm_cp_async_ca_shared_global_8:
1125 return MakeCpAsync(IntrinsicID: Intrinsic::nvvm_cp_async_ca_shared_global_8,
1126 IntrinsicIDS: Intrinsic::nvvm_cp_async_ca_shared_global_8_s, CGF&: *this, E,
1127 SrcSize: 8);
1128 case NVPTX::BI__nvvm_cp_async_ca_shared_global_16:
1129 return MakeCpAsync(IntrinsicID: Intrinsic::nvvm_cp_async_ca_shared_global_16,
1130 IntrinsicIDS: Intrinsic::nvvm_cp_async_ca_shared_global_16_s, CGF&: *this, E,
1131 SrcSize: 16);
1132 case NVPTX::BI__nvvm_cp_async_cg_shared_global_16:
1133 return MakeCpAsync(IntrinsicID: Intrinsic::nvvm_cp_async_cg_shared_global_16,
1134 IntrinsicIDS: Intrinsic::nvvm_cp_async_cg_shared_global_16_s, CGF&: *this, E,
1135 SrcSize: 16);
1136 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_x:
1137 return Builder.CreateCall(
1138 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_clusterid_x));
1139 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_y:
1140 return Builder.CreateCall(
1141 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_clusterid_y));
1142 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_z:
1143 return Builder.CreateCall(
1144 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_clusterid_z));
1145 case NVPTX::BI__nvvm_read_ptx_sreg_clusterid_w:
1146 return Builder.CreateCall(
1147 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_clusterid_w));
1148 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_x:
1149 return Builder.CreateCall(
1150 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_nclusterid_x));
1151 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_y:
1152 return Builder.CreateCall(
1153 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_nclusterid_y));
1154 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_z:
1155 return Builder.CreateCall(
1156 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_nclusterid_z));
1157 case NVPTX::BI__nvvm_read_ptx_sreg_nclusterid_w:
1158 return Builder.CreateCall(
1159 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_nclusterid_w));
1160 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_x:
1161 return Builder.CreateCall(
1162 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_x));
1163 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_y:
1164 return Builder.CreateCall(
1165 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_y));
1166 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_z:
1167 return Builder.CreateCall(
1168 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_z));
1169 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctaid_w:
1170 return Builder.CreateCall(
1171 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_ctaid_w));
1172 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_x:
1173 return Builder.CreateCall(
1174 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_x));
1175 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_y:
1176 return Builder.CreateCall(
1177 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_y));
1178 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_z:
1179 return Builder.CreateCall(
1180 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_z));
1181 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctaid_w:
1182 return Builder.CreateCall(
1183 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_nctaid_w));
1184 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_ctarank:
1185 return Builder.CreateCall(
1186 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_ctarank));
1187 case NVPTX::BI__nvvm_read_ptx_sreg_cluster_nctarank:
1188 return Builder.CreateCall(
1189 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_read_ptx_sreg_cluster_nctarank));
1190 case NVPTX::BI__nvvm_is_explicit_cluster:
1191 return Builder.CreateCall(
1192 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_is_explicit_cluster));
1193 case NVPTX::BI__nvvm_isspacep_shared_cluster:
1194 return Builder.CreateCall(
1195 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_isspacep_shared_cluster),
1196 Args: EmitScalarExpr(E: E->getArg(Arg: 0)));
1197 case NVPTX::BI__nvvm_mapa:
1198 return Builder.CreateCall(
1199 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_mapa),
1200 Args: {EmitScalarExpr(E: E->getArg(Arg: 0)), EmitScalarExpr(E: E->getArg(Arg: 1))});
1201 case NVPTX::BI__nvvm_mapa_shared_cluster:
1202 return Builder.CreateCall(
1203 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_mapa_shared_cluster),
1204 Args: {EmitScalarExpr(E: E->getArg(Arg: 0)), EmitScalarExpr(E: E->getArg(Arg: 1))});
1205 case NVPTX::BI__nvvm_getctarank:
1206 return Builder.CreateCall(
1207 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_getctarank),
1208 Args: EmitScalarExpr(E: E->getArg(Arg: 0)));
1209 case NVPTX::BI__nvvm_getctarank_shared_cluster:
1210 return Builder.CreateCall(
1211 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_getctarank_shared_cluster),
1212 Args: EmitScalarExpr(E: E->getArg(Arg: 0)));
1213 case NVPTX::BI__nvvm_barrier_cluster_arrive:
1214 return Builder.CreateCall(
1215 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_barrier_cluster_arrive));
1216 case NVPTX::BI__nvvm_barrier_cluster_arrive_relaxed:
1217 return Builder.CreateCall(
1218 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_barrier_cluster_arrive_relaxed));
1219 case NVPTX::BI__nvvm_barrier_cluster_wait:
1220 return Builder.CreateCall(
1221 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_barrier_cluster_wait));
1222 case NVPTX::BI__nvvm_fence_sc_cluster:
1223 return Builder.CreateCall(
1224 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_fence_sc_cluster));
1225 case NVPTX::BI__nvvm_bar_sync:
1226 return Builder.CreateCall(
1227 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_barrier_cta_sync_aligned_all),
1228 Args: EmitScalarExpr(E: E->getArg(Arg: 0)));
1229 case NVPTX::BI__syncthreads:
1230 return Builder.CreateCall(
1231 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_barrier_cta_sync_aligned_all),
1232 Args: Builder.getInt32(C: 0));
1233 case NVPTX::BI__nvvm_barrier_sync:
1234 return Builder.CreateCall(
1235 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_barrier_cta_sync_all),
1236 Args: EmitScalarExpr(E: E->getArg(Arg: 0)));
1237 case NVPTX::BI__nvvm_barrier_sync_cnt:
1238 return Builder.CreateCall(
1239 Callee: CGM.getIntrinsic(IID: Intrinsic::nvvm_barrier_cta_sync_count),
1240 Args: {EmitScalarExpr(E: E->getArg(Arg: 0)), EmitScalarExpr(E: E->getArg(Arg: 1))});
1241 case NVPTX::BI__nvvm_bar0_and:
1242 return Builder.CreateZExt(
1243 V: Builder.CreateIntrinsic(
1244 ID: Intrinsic::nvvm_barrier_cta_red_and_aligned_all, OverloadTypes: {},
1245 Args: {Builder.getInt32(C: 0),
1246 Builder.CreateICmpNE(LHS: EmitScalarExpr(E: E->getArg(Arg: 0)),
1247 RHS: Builder.getInt32(C: 0))}),
1248 DestTy: Builder.getInt32Ty());
1249 case NVPTX::BI__nvvm_bar0_or:
1250 return Builder.CreateZExt(
1251 V: Builder.CreateIntrinsic(
1252 ID: Intrinsic::nvvm_barrier_cta_red_or_aligned_all, OverloadTypes: {},
1253 Args: {Builder.getInt32(C: 0),
1254 Builder.CreateICmpNE(LHS: EmitScalarExpr(E: E->getArg(Arg: 0)),
1255 RHS: Builder.getInt32(C: 0))}),
1256 DestTy: Builder.getInt32Ty());
1257 case NVPTX::BI__nvvm_bar0_popc:
1258 return Builder.CreateIntrinsic(
1259 ID: Intrinsic::nvvm_barrier_cta_red_popc_aligned_all, OverloadTypes: {},
1260 Args: {Builder.getInt32(C: 0), Builder.CreateICmpNE(LHS: EmitScalarExpr(E: E->getArg(Arg: 0)),
1261 RHS: Builder.getInt32(C: 0))});
1262 default:
1263 return nullptr;
1264 }
1265}
1266