1//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the SelectionDAGISel class, which is used as the common
10// base class for SelectionDAG-based instruction selectors.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
15#define LLVM_CODEGEN_SELECTIONDAGISEL_H
16
17#include "llvm/Analysis/AliasAnalysis.h"
18#include "llvm/CodeGen/MachineFunctionPass.h"
19#include "llvm/CodeGen/MachinePassManager.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/IR/BasicBlock.h"
22#include <memory>
23
24namespace llvm {
25class AAResults;
26class AssumptionCache;
27class TargetInstrInfo;
28class TargetMachine;
29class SSPLayoutInfo;
30class SelectionDAGBuilder;
31class SDValue;
32class MachineRegisterInfo;
33class MachineFunction;
34class OptimizationRemarkEmitter;
35class TargetLowering;
36class TargetLibraryInfo;
37class TargetTransformInfo;
38class FunctionLoweringInfo;
39class SwiftErrorValueTracking;
40class GCFunctionInfo;
41class ScheduleDAGSDNodes;
42
43/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
44/// pattern-matching instruction selectors.
45class SelectionDAGISel {
46public:
47 TargetMachine &TM;
48 const TargetLibraryInfo *LibInfo;
49 const LibcallLoweringInfo *LibcallLowering;
50
51 std::unique_ptr<FunctionLoweringInfo> FuncInfo;
52 std::unique_ptr<SwiftErrorValueTracking> SwiftError;
53 MachineFunction *MF;
54 MachineModuleInfo *MMI;
55 MachineRegisterInfo *RegInfo;
56 SelectionDAG *CurDAG;
57 std::unique_ptr<SelectionDAGBuilder> SDB;
58 mutable std::optional<BatchAAResults> BatchAA;
59 AssumptionCache *AC = nullptr;
60 GCFunctionInfo *GFI = nullptr;
61 SSPLayoutInfo *SP = nullptr;
62 const TargetTransformInfo *TTI = nullptr;
63 CodeGenOptLevel OptLevel;
64 const TargetInstrInfo *TII;
65 const TargetLowering *TLI;
66 bool FastISelFailed;
67 SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs;
68
69 /// Current optimization remark emitter.
70 /// Used to report things like combines and FastISel failures.
71 std::unique_ptr<OptimizationRemarkEmitter> ORE;
72
73 /// True if the function currently processing is in the function printing list
74 /// (i.e. `-filter-print-funcs`).
75 /// This is primarily used by ISEL_DUMP, which spans in multiple member
76 /// functions. Storing the filter result here so that we only need to do the
77 /// filtering once.
78 bool MatchFilterFuncName = false;
79 StringRef FuncName;
80
81 // HwMode to be used by getValueTypeForHwMode. This will be initialized
82 // based on the subtarget used by the MachineFunction.
83 unsigned HwMode;
84
85 explicit SelectionDAGISel(TargetMachine &tm,
86 CodeGenOptLevel OL = CodeGenOptLevel::Default);
87 virtual ~SelectionDAGISel();
88
89 /// Returns a (possibly null) pointer to the current BatchAAResults.
90 BatchAAResults *getBatchAA() const {
91 if (BatchAA.has_value())
92 return &BatchAA.value();
93 return nullptr;
94 }
95
96 const TargetLowering *getTargetLowering() const { return TLI; }
97
98 void initializeAnalysisResults(MachineFunctionAnalysisManager &MFAM);
99 void initializeAnalysisResults(MachineFunctionPass &MFP);
100
101 virtual bool runOnMachineFunction(MachineFunction &mf);
102
103 virtual void emitFunctionEntryCode() {}
104
105 /// PreprocessISelDAG - This hook allows targets to hack on the graph before
106 /// instruction selection starts.
107 virtual void PreprocessISelDAG() {}
108
109 /// PostprocessISelDAG() - This hook allows the target to hack on the graph
110 /// right after selection.
111 virtual void PostprocessISelDAG() {}
112
113 /// Main hook for targets to transform nodes into machine nodes.
114 virtual void Select(SDNode *N) = 0;
115
116 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
117 /// addressing mode, according to the specified constraint. If this does
118 /// not match or is not implemented, return true. The resultant operands
119 /// (which will appear in the machine instruction) should be added to the
120 /// OutOps vector.
121 virtual bool
122 SelectInlineAsmMemoryOperand(const SDValue &Op,
123 InlineAsm::ConstraintCode ConstraintID,
124 std::vector<SDValue> &OutOps) {
125 return true;
126 }
127
128 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
129 /// operand node N of U during instruction selection that starts at Root.
130 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
131
132 /// IsLegalToFold - Returns true if the specific operand node N of
133 /// U can be folded during instruction selection that starts at Root.
134 /// FIXME: This is a static member function because the MSP430/X86
135 /// targets, which uses it during isel. This could become a proper member.
136 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
137 CodeGenOptLevel OptLevel,
138 bool IgnoreChains = false);
139
140 static void InvalidateNodeId(SDNode *N);
141 static int getUninvalidatedNodeId(SDNode *N);
142
143 static void EnforceNodeIdInvariant(SDNode *N);
144
145 // Opcodes used by the DAG state machine:
146 enum BuiltinOpcodes {
147 OPC_Scope,
148 OPC_RecordNode,
149 OPC_RecordChild0,
150 OPC_RecordChild1,
151 OPC_RecordChild2,
152 OPC_RecordChild3,
153 OPC_RecordChild4,
154 OPC_RecordChild5,
155 OPC_RecordChild6,
156 OPC_RecordChild7,
157 OPC_RecordMemRef,
158 OPC_CaptureGlueInput,
159 OPC_CaptureDeactivationSymbol,
160 OPC_MoveChild,
161 OPC_MoveChild0,
162 OPC_MoveChild1,
163 OPC_MoveChild2,
164 OPC_MoveChild3,
165 OPC_MoveChild4,
166 OPC_MoveChild5,
167 OPC_MoveChild6,
168 OPC_MoveChild7,
169 OPC_MoveSibling,
170 OPC_MoveSibling0,
171 OPC_MoveSibling1,
172 OPC_MoveSibling2,
173 OPC_MoveSibling3,
174 OPC_MoveSibling4,
175 OPC_MoveSibling5,
176 OPC_MoveSibling6,
177 OPC_MoveSibling7,
178 OPC_MoveParent,
179 OPC_CheckSame,
180 OPC_CheckChild0Same,
181 OPC_CheckChild1Same,
182 OPC_CheckChild2Same,
183 OPC_CheckChild3Same,
184 OPC_CheckPatternPredicate,
185 OPC_CheckPatternPredicate0,
186 OPC_CheckPatternPredicate1,
187 OPC_CheckPatternPredicate2,
188 OPC_CheckPatternPredicate3,
189 OPC_CheckPatternPredicate4,
190 OPC_CheckPatternPredicate5,
191 OPC_CheckPatternPredicate6,
192 OPC_CheckPatternPredicate7,
193 OPC_CheckPatternPredicateTwoByte,
194 OPC_CheckPredicate,
195 OPC_CheckPredicate0,
196 OPC_CheckPredicate1,
197 OPC_CheckPredicate2,
198 OPC_CheckPredicate3,
199 OPC_CheckPredicate4,
200 OPC_CheckPredicate5,
201 OPC_CheckPredicate6,
202 OPC_CheckPredicate7,
203 OPC_CheckPredicateWithOperands,
204 OPC_CheckOpcode,
205 OPC_SwitchOpcode,
206 OPC_CheckType,
207 // Space-optimized forms that implicitly encode VT.
208 OPC_CheckTypeI32,
209 OPC_CheckTypeI64,
210 OPC_CheckTypeByHwMode,
211 // Space-optimized form that implicitly encodes index 0.
212 OPC_CheckTypeByHwMode0,
213 OPC_CheckTypeRes,
214 OPC_CheckTypeResByHwMode,
215 OPC_SwitchType,
216 OPC_CheckChild0Type,
217 OPC_CheckChild1Type,
218 OPC_CheckChild2Type,
219 OPC_CheckChild3Type,
220 OPC_CheckChild4Type,
221 OPC_CheckChild5Type,
222 OPC_CheckChild6Type,
223 OPC_CheckChild7Type,
224
225 OPC_CheckChild0TypeI32,
226 OPC_CheckChild1TypeI32,
227 OPC_CheckChild2TypeI32,
228 OPC_CheckChild3TypeI32,
229 OPC_CheckChild4TypeI32,
230 OPC_CheckChild5TypeI32,
231 OPC_CheckChild6TypeI32,
232 OPC_CheckChild7TypeI32,
233
234 OPC_CheckChild0TypeI64,
235 OPC_CheckChild1TypeI64,
236 OPC_CheckChild2TypeI64,
237 OPC_CheckChild3TypeI64,
238 OPC_CheckChild4TypeI64,
239 OPC_CheckChild5TypeI64,
240 OPC_CheckChild6TypeI64,
241 OPC_CheckChild7TypeI64,
242
243 OPC_CheckChild0TypeByHwMode,
244 OPC_CheckChild1TypeByHwMode,
245 OPC_CheckChild2TypeByHwMode,
246 OPC_CheckChild3TypeByHwMode,
247 OPC_CheckChild4TypeByHwMode,
248 OPC_CheckChild5TypeByHwMode,
249 OPC_CheckChild6TypeByHwMode,
250 OPC_CheckChild7TypeByHwMode,
251
252 OPC_CheckChild0TypeByHwMode0,
253 OPC_CheckChild1TypeByHwMode0,
254 OPC_CheckChild2TypeByHwMode0,
255 OPC_CheckChild3TypeByHwMode0,
256 OPC_CheckChild4TypeByHwMode0,
257 OPC_CheckChild5TypeByHwMode0,
258 OPC_CheckChild6TypeByHwMode0,
259 OPC_CheckChild7TypeByHwMode0,
260
261 OPC_CheckInteger,
262 OPC_CheckChild0Integer,
263 OPC_CheckChild1Integer,
264 OPC_CheckChild2Integer,
265 OPC_CheckChild3Integer,
266 OPC_CheckChild4Integer,
267 OPC_CheckCondCode,
268 OPC_CheckChild2CondCode,
269 OPC_CheckValueType,
270 OPC_CheckComplexPat,
271 OPC_CheckComplexPat0,
272 OPC_CheckComplexPat1,
273 OPC_CheckComplexPat2,
274 OPC_CheckComplexPat3,
275 OPC_CheckComplexPat4,
276 OPC_CheckComplexPat5,
277 OPC_CheckComplexPat6,
278 OPC_CheckComplexPat7,
279 OPC_CheckAndImm,
280 OPC_CheckOrImm,
281 OPC_CheckImmAllOnesV,
282 OPC_CheckImmAllZerosV,
283 OPC_CheckFoldableChainNode,
284
285 OPC_EmitInteger,
286 // Space-optimized forms that implicitly encode integer VT.
287 OPC_EmitIntegerI8,
288 OPC_EmitIntegerI16,
289 OPC_EmitIntegerI32,
290 OPC_EmitIntegerI64,
291 OPC_EmitIntegerByHwMode,
292 OPC_EmitIntegerByHwMode0,
293 OPC_EmitRegister,
294 OPC_EmitRegisterI32,
295 OPC_EmitRegisterI64,
296 OPC_EmitRegisterByHwMode,
297 OPC_EmitRegister2,
298 OPC_EmitRegisterByHwMode2,
299 OPC_EmitConvertToTarget,
300 OPC_EmitConvertToTarget0,
301 OPC_EmitConvertToTarget1,
302 OPC_EmitConvertToTarget2,
303 OPC_EmitConvertToTarget3,
304 OPC_EmitConvertToTarget4,
305 OPC_EmitConvertToTarget5,
306 OPC_EmitConvertToTarget6,
307 OPC_EmitConvertToTarget7,
308 OPC_EmitMergeInputChains,
309 OPC_EmitMergeInputChains1_0,
310 OPC_EmitMergeInputChains1_1,
311 OPC_EmitMergeInputChains1_2,
312 OPC_EmitCopyToReg,
313 OPC_EmitCopyToReg0,
314 OPC_EmitCopyToReg1,
315 OPC_EmitCopyToReg2,
316 OPC_EmitCopyToReg3,
317 OPC_EmitCopyToReg4,
318 OPC_EmitCopyToReg5,
319 OPC_EmitCopyToReg6,
320 OPC_EmitCopyToReg7,
321 OPC_EmitCopyToRegTwoByte,
322 OPC_EmitNodeXForm,
323 OPC_EmitNode,
324 OPC_EmitNodeByHwMode,
325 // Space-optimized forms that implicitly encode number of result VTs.
326 OPC_EmitNode0,
327 OPC_EmitNode1,
328 OPC_EmitNode2,
329 // Space-optimized forms that implicitly encode EmitNodeInfo.
330 OPC_EmitNode1None,
331 OPC_EmitNode2None,
332 OPC_EmitNode0Chain,
333 OPC_EmitNode1Chain,
334 OPC_EmitNode2Chain,
335 OPC_MorphNodeTo,
336 OPC_MorphNodeToByHwMode,
337 // Space-optimized forms that implicitly encode number of result VTs.
338 OPC_MorphNodeTo0,
339 OPC_MorphNodeTo1,
340 OPC_MorphNodeTo2,
341 // Space-optimized forms that implicitly encode EmitNodeInfo.
342 OPC_MorphNodeTo1None,
343 OPC_MorphNodeTo2None,
344 OPC_MorphNodeTo0Chain,
345 OPC_MorphNodeTo1Chain,
346 OPC_MorphNodeTo2Chain,
347 OPC_MorphNodeTo1GlueInput,
348 OPC_MorphNodeTo2GlueInput,
349 OPC_MorphNodeTo1GlueOutput,
350 OPC_MorphNodeTo2GlueOutput,
351 OPC_CompleteMatch,
352 // Contains 32-bit offset in table for pattern being selected
353 OPC_Coverage
354 };
355
356 enum {
357 OPFL_None = 0, // Node has no chain or glue input and isn't variadic.
358 OPFL_Chain = 1, // Node has a chain input.
359 OPFL_GlueInput = 2, // Node has a glue input.
360 OPFL_GlueOutput = 4, // Node has a glue output.
361 OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
362 OPFL_Variadic0 = 1 << 4, // Node is variadic, root has 0 fixed inputs.
363 OPFL_Variadic1 = 2 << 4, // Node is variadic, root has 1 fixed inputs.
364 OPFL_Variadic2 = 3 << 4, // Node is variadic, root has 2 fixed inputs.
365 OPFL_Variadic3 = 4 << 4, // Node is variadic, root has 3 fixed inputs.
366 OPFL_Variadic4 = 5 << 4, // Node is variadic, root has 4 fixed inputs.
367 OPFL_Variadic5 = 6 << 4, // Node is variadic, root has 5 fixed inputs.
368 OPFL_Variadic6 = 7 << 4, // Node is variadic, root has 6 fixed inputs.
369 OPFL_Variadic7 = 8 << 4, // Node is variadic, root has 7 fixed inputs.
370
371 OPFL_VariadicInfo = 15 << 4 // Mask for extracting the OPFL_VariadicN bits.
372 };
373
374 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
375 /// number of fixed arity values that should be skipped when copying from the
376 /// root.
377 static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
378 return ((Flags&OPFL_VariadicInfo) >> 4)-1;
379 }
380
381
382protected:
383 /// DAGSize - Size of DAG being instruction selected.
384 ///
385 unsigned DAGSize = 0;
386
387 /// ReplaceUses - replace all uses of the old node F with the use
388 /// of the new node T.
389 void ReplaceUses(SDValue F, SDValue T) {
390 CurDAG->ReplaceAllUsesOfValueWith(From: F, To: T);
391 EnforceNodeIdInvariant(N: T.getNode());
392 }
393
394 /// ReplaceUses - replace all uses of the old nodes F with the use
395 /// of the new nodes T.
396 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
397 CurDAG->ReplaceAllUsesOfValuesWith(From: F, To: T, Num);
398 for (unsigned i = 0; i < Num; ++i)
399 EnforceNodeIdInvariant(N: T[i].getNode());
400 }
401
402 /// ReplaceUses - replace all uses of the old node F with the use
403 /// of the new node T.
404 void ReplaceUses(SDNode *F, SDNode *T) {
405 CurDAG->ReplaceAllUsesWith(From: F, To: T);
406 EnforceNodeIdInvariant(N: T);
407 }
408
409 /// Replace all uses of \c F with \c T, then remove \c F from the DAG.
410 void ReplaceNode(SDNode *F, SDNode *T) {
411 CurDAG->ReplaceAllUsesWith(From: F, To: T);
412 EnforceNodeIdInvariant(N: T);
413 CurDAG->RemoveDeadNode(N: F);
414 }
415
416 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
417 /// by tblgen. Others should not call it.
418 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
419 const SDLoc &DL);
420
421 /// getPatternForIndex - Patterns selected by tablegen during ISEL
422 virtual StringRef getPatternForIndex(unsigned index) {
423 llvm_unreachable("Tblgen should generate the implementation of this!");
424 }
425
426 /// getIncludePathForIndex - get the td source location of pattern instantiation
427 virtual StringRef getIncludePathForIndex(unsigned index) {
428 llvm_unreachable("Tblgen should generate the implementation of this!");
429 }
430
431 bool shouldOptForSize(const MachineFunction *MF) const {
432 return CurDAG->shouldOptForSize();
433 }
434
435public:
436 // Calls to these predicates are generated by tblgen.
437 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
438 int64_t DesiredMaskS) const;
439 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
440 int64_t DesiredMaskS) const;
441
442
443 /// CheckPatternPredicate - This function is generated by tblgen in the
444 /// target. It runs the specified pattern predicate and returns true if it
445 /// succeeds or false if it fails. The number is a private implementation
446 /// detail to the code tblgen produces.
447 virtual bool CheckPatternPredicate(unsigned PredNo) const {
448 llvm_unreachable("Tblgen should generate the implementation of this!");
449 }
450
451 /// CheckNodePredicate - This function is generated by tblgen in the target.
452 /// It runs node predicate number PredNo and returns true if it succeeds or
453 /// false if it fails. The number is a private implementation
454 /// detail to the code tblgen produces.
455 virtual bool CheckNodePredicate(SDValue Op, unsigned PredNo) const {
456 llvm_unreachable("Tblgen should generate the implementation of this!");
457 }
458
459 /// CheckNodePredicateWithOperands - This function is generated by tblgen in
460 /// the target.
461 /// It runs node predicate number PredNo and returns true if it succeeds or
462 /// false if it fails. The number is a private implementation detail to the
463 /// code tblgen produces.
464 virtual bool
465 CheckNodePredicateWithOperands(SDValue Op, unsigned PredNo,
466 ArrayRef<SDValue> Operands) const {
467 llvm_unreachable("Tblgen should generate the implementation of this!");
468 }
469
470 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
471 unsigned PatternNo,
472 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
473 llvm_unreachable("Tblgen should generate the implementation of this!");
474 }
475
476 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
477 llvm_unreachable("Tblgen should generate this!");
478 }
479
480 virtual MVT getValueTypeForHwMode(unsigned Index) const {
481 llvm_unreachable("Tblgen should generate the implementation of this!");
482 }
483
484 void SelectCodeCommon(SDNode *NodeToMatch, const uint8_t *MatcherTable,
485 unsigned TableSize, const uint8_t *OperandLists);
486
487 /// Return true if complex patterns for this target can mutate the
488 /// DAG.
489 virtual bool ComplexPatternFuncMutatesDAG() const {
490 return false;
491 }
492
493 /// Return whether the node may raise an FP exception.
494 bool mayRaiseFPException(SDNode *Node) const;
495
496 bool isOrEquivalentToAdd(const SDNode *N) const;
497
498private:
499
500 // Calls to these functions are generated by tblgen.
501 void Select_INLINEASM(SDNode *N);
502 void Select_READ_REGISTER(SDNode *Op);
503 void Select_WRITE_REGISTER(SDNode *Op);
504 void Select_UNDEF(SDNode *N);
505 void Select_FAKE_USE(SDNode *N);
506 void Select_RELOC_NONE(SDNode *N);
507 void CannotYetSelect(SDNode *N);
508
509 void Select_FREEZE(SDNode *N);
510 void Select_ARITH_FENCE(SDNode *N);
511 void Select_MEMBARRIER(SDNode *N);
512
513 void Select_CONVERGENCECTRL_ANCHOR(SDNode *N);
514 void Select_CONVERGENCECTRL_ENTRY(SDNode *N);
515 void Select_CONVERGENCECTRL_LOOP(SDNode *N);
516
517 void pushStackMapLiveVariable(SmallVectorImpl<SDValue> &Ops, SDValue Operand,
518 SDLoc DL);
519 void Select_STACKMAP(SDNode *N);
520 void Select_PATCHPOINT(SDNode *N);
521
522 void Select_JUMP_TABLE_DEBUG_INFO(SDNode *N);
523
524private:
525 void DoInstructionSelection();
526 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
527 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
528
529 /// Prepares the landing pad to take incoming values or do other EH
530 /// personality specific tasks. Returns true if the block should be
531 /// instruction selected, false if no code should be emitted for it.
532 bool PrepareEHLandingPad();
533
534 // Mark and Report IPToState for each Block under AsynchEH
535 void reportIPToStateForBlocks(MachineFunction *Fn);
536
537 /// Perform instruction selection on all basic blocks in the function.
538 void SelectAllBasicBlocks(const Function &Fn);
539
540 /// Perform instruction selection on a single basic block, for
541 /// instructions between \p Begin and \p End. \p HadTailCall will be set
542 /// to true if a call in the block was translated as a tail call.
543 void SelectBasicBlock(BasicBlock::const_iterator Begin,
544 BasicBlock::const_iterator End,
545 bool &HadTailCall);
546 void FinishBasicBlock();
547
548 void CodeGenAndEmitDAG();
549
550 /// Generate instructions for lowering the incoming arguments of the
551 /// given function.
552 void LowerArguments(const Function &F);
553
554 void ComputeLiveOutVRegInfo();
555
556 /// Create the scheduler. If a specific scheduler was specified
557 /// via the SchedulerRegistry, use it, otherwise select the
558 /// one preferred by the target.
559 ///
560 ScheduleDAGSDNodes *CreateScheduler();
561
562 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
563 /// state machines that start with a OPC_SwitchOpcode node.
564 std::vector<unsigned> OpcodeOffset;
565
566 void UpdateChains(SDNode *NodeToMatch, SDValue InputChain,
567 SmallVectorImpl<SDNode *> &ChainNodesMatched,
568 bool isMorphNodeTo);
569};
570
571class SelectionDAGISelLegacy : public MachineFunctionPass {
572 std::unique_ptr<SelectionDAGISel> Selector;
573
574public:
575 SelectionDAGISelLegacy(char &ID, std::unique_ptr<SelectionDAGISel> S);
576
577 ~SelectionDAGISelLegacy() override = default;
578
579 void getAnalysisUsage(AnalysisUsage &AU) const override;
580
581 bool runOnMachineFunction(MachineFunction &MF) override;
582};
583
584class SelectionDAGISelPass : public PassInfoMixin<SelectionDAGISelPass> {
585 std::unique_ptr<SelectionDAGISel> Selector;
586
587protected:
588 SelectionDAGISelPass(std::unique_ptr<SelectionDAGISel> Selector)
589 : Selector(std::move(Selector)) {}
590
591public:
592 PreservedAnalyses run(MachineFunction &MF,
593 MachineFunctionAnalysisManager &MFAM);
594 static bool isRequired() { return true; }
595};
596}
597
598#endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */
599