1//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the SelectionDAGISel class, which is used as the common
10// base class for SelectionDAG-based instruction selectors.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
15#define LLVM_CODEGEN_SELECTIONDAGISEL_H
16
17#include "llvm/Analysis/AliasAnalysis.h"
18#include "llvm/CodeGen/MachineFunctionPass.h"
19#include "llvm/CodeGen/MachinePassManager.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/IR/BasicBlock.h"
22#include <memory>
23
24namespace llvm {
25class AAResults;
26class AssumptionCache;
27class TargetInstrInfo;
28class TargetMachine;
29class SSPLayoutInfo;
30class SelectionDAGBuilder;
31class SDValue;
32class MachineRegisterInfo;
33class MachineFunction;
34class OptimizationRemarkEmitter;
35class TargetLowering;
36class TargetLibraryInfo;
37class TargetTransformInfo;
38class FunctionLoweringInfo;
39class SwiftErrorValueTracking;
40class GCFunctionInfo;
41class ScheduleDAGSDNodes;
42
43/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
44/// pattern-matching instruction selectors.
45class SelectionDAGISel {
46public:
47 TargetMachine &TM;
48 const TargetLibraryInfo *LibInfo;
49 const LibcallLoweringInfo *LibcallLowering;
50
51 std::unique_ptr<FunctionLoweringInfo> FuncInfo;
52 std::unique_ptr<SwiftErrorValueTracking> SwiftError;
53 MachineFunction *MF;
54 MachineModuleInfo *MMI;
55 MachineRegisterInfo *RegInfo;
56 SelectionDAG *CurDAG;
57 std::unique_ptr<SelectionDAGBuilder> SDB;
58 mutable std::optional<BatchAAResults> BatchAA;
59 AssumptionCache *AC = nullptr;
60 GCFunctionInfo *GFI = nullptr;
61 SSPLayoutInfo *SP = nullptr;
62 const TargetTransformInfo *TTI = nullptr;
63 CodeGenOptLevel OptLevel;
64 const TargetInstrInfo *TII;
65 const TargetLowering *TLI;
66 bool FastISelFailed;
67 SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs;
68
69 /// Current optimization remark emitter.
70 /// Used to report things like combines and FastISel failures.
71 std::unique_ptr<OptimizationRemarkEmitter> ORE;
72
73 /// True if the function currently processing is in the function printing list
74 /// (i.e. `-filter-print-funcs`).
75 /// This is primarily used by ISEL_DUMP, which spans in multiple member
76 /// functions. Storing the filter result here so that we only need to do the
77 /// filtering once.
78 bool MatchFilterFuncName = false;
79 StringRef FuncName;
80
81 // HwMode to be used by getValueTypeForHwMode. This will be initialized
82 // based on the subtarget used by the MachineFunction.
83 unsigned HwMode;
84
85 explicit SelectionDAGISel(TargetMachine &tm,
86 CodeGenOptLevel OL = CodeGenOptLevel::Default);
87 virtual ~SelectionDAGISel();
88
89 /// Returns a (possibly null) pointer to the current BatchAAResults.
90 BatchAAResults *getBatchAA() const {
91 if (BatchAA.has_value())
92 return &BatchAA.value();
93 return nullptr;
94 }
95
96 const TargetLowering *getTargetLowering() const { return TLI; }
97
98 void initializeAnalysisResults(MachineFunctionAnalysisManager &MFAM);
99 void initializeAnalysisResults(MachineFunctionPass &MFP);
100
101 virtual bool runOnMachineFunction(MachineFunction &mf);
102
103 virtual void emitFunctionEntryCode() {}
104
105 /// PreprocessISelDAG - This hook allows targets to hack on the graph before
106 /// instruction selection starts.
107 virtual void PreprocessISelDAG() {}
108
109 /// PostprocessISelDAG() - This hook allows the target to hack on the graph
110 /// right after selection.
111 virtual void PostprocessISelDAG() {}
112
113 /// Main hook for targets to transform nodes into machine nodes.
114 virtual void Select(SDNode *N) = 0;
115
116 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
117 /// addressing mode, according to the specified constraint. If this does
118 /// not match or is not implemented, return true. The resultant operands
119 /// (which will appear in the machine instruction) should be added to the
120 /// OutOps vector.
121 virtual bool
122 SelectInlineAsmMemoryOperand(const SDValue &Op,
123 InlineAsm::ConstraintCode ConstraintID,
124 std::vector<SDValue> &OutOps) {
125 return true;
126 }
127
128 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
129 /// operand node N of U during instruction selection that starts at Root.
130 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
131
132 /// IsLegalToFold - Returns true if the specific operand node N of
133 /// U can be folded during instruction selection that starts at Root.
134 /// FIXME: This is a static member function because the MSP430/X86
135 /// targets, which uses it during isel. This could become a proper member.
136 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
137 CodeGenOptLevel OptLevel,
138 bool IgnoreChains = false);
139
140 static void InvalidateNodeId(SDNode *N);
141 static int getUninvalidatedNodeId(SDNode *N);
142
143 static void EnforceNodeIdInvariant(SDNode *N);
144
145 // Opcodes used by the DAG state machine:
146 enum BuiltinOpcodes {
147 OPC_Scope,
148 OPC_RecordNode,
149 OPC_RecordChild0,
150 OPC_RecordChild1,
151 OPC_RecordChild2,
152 OPC_RecordChild3,
153 OPC_RecordChild4,
154 OPC_RecordChild5,
155 OPC_RecordChild6,
156 OPC_RecordChild7,
157 OPC_RecordMemRef,
158 OPC_CaptureGlueInput,
159 OPC_CaptureDeactivationSymbol,
160 OPC_MoveChild,
161 OPC_MoveChild0,
162 OPC_MoveChild1,
163 OPC_MoveChild2,
164 OPC_MoveChild3,
165 OPC_MoveChild4,
166 OPC_MoveChild5,
167 OPC_MoveChild6,
168 OPC_MoveChild7,
169 OPC_MoveSibling,
170 OPC_MoveSibling0,
171 OPC_MoveSibling1,
172 OPC_MoveSibling2,
173 OPC_MoveSibling3,
174 OPC_MoveSibling4,
175 OPC_MoveSibling5,
176 OPC_MoveSibling6,
177 OPC_MoveSibling7,
178 OPC_MoveParent,
179 OPC_CheckSame,
180 OPC_CheckChild0Same,
181 OPC_CheckChild1Same,
182 OPC_CheckChild2Same,
183 OPC_CheckChild3Same,
184 OPC_CheckPatternPredicate,
185 OPC_CheckPatternPredicate0,
186 OPC_CheckPatternPredicate1,
187 OPC_CheckPatternPredicate2,
188 OPC_CheckPatternPredicate3,
189 OPC_CheckPatternPredicate4,
190 OPC_CheckPatternPredicate5,
191 OPC_CheckPatternPredicate6,
192 OPC_CheckPatternPredicate7,
193 OPC_CheckPatternPredicateTwoByte,
194 OPC_CheckPredicate,
195 OPC_CheckPredicate0,
196 OPC_CheckPredicate1,
197 OPC_CheckPredicate2,
198 OPC_CheckPredicate3,
199 OPC_CheckPredicate4,
200 OPC_CheckPredicate5,
201 OPC_CheckPredicate6,
202 OPC_CheckPredicate7,
203 OPC_CheckPredicateWithOperands,
204 OPC_CheckOpcode,
205 OPC_SwitchOpcode,
206 OPC_CheckType,
207 // Space-optimized forms that implicitly encode VT.
208 OPC_CheckTypeI32,
209 OPC_CheckTypeI64,
210 OPC_CheckTypeByHwMode,
211 OPC_CheckTypeRes,
212 OPC_CheckTypeResByHwMode,
213 OPC_SwitchType,
214 OPC_CheckChild0Type,
215 OPC_CheckChild1Type,
216 OPC_CheckChild2Type,
217 OPC_CheckChild3Type,
218 OPC_CheckChild4Type,
219 OPC_CheckChild5Type,
220 OPC_CheckChild6Type,
221 OPC_CheckChild7Type,
222
223 OPC_CheckChild0TypeI32,
224 OPC_CheckChild1TypeI32,
225 OPC_CheckChild2TypeI32,
226 OPC_CheckChild3TypeI32,
227 OPC_CheckChild4TypeI32,
228 OPC_CheckChild5TypeI32,
229 OPC_CheckChild6TypeI32,
230 OPC_CheckChild7TypeI32,
231
232 OPC_CheckChild0TypeI64,
233 OPC_CheckChild1TypeI64,
234 OPC_CheckChild2TypeI64,
235 OPC_CheckChild3TypeI64,
236 OPC_CheckChild4TypeI64,
237 OPC_CheckChild5TypeI64,
238 OPC_CheckChild6TypeI64,
239 OPC_CheckChild7TypeI64,
240
241 OPC_CheckChild0TypeByHwMode,
242 OPC_CheckChild1TypeByHwMode,
243 OPC_CheckChild2TypeByHwMode,
244 OPC_CheckChild3TypeByHwMode,
245 OPC_CheckChild4TypeByHwMode,
246 OPC_CheckChild5TypeByHwMode,
247 OPC_CheckChild6TypeByHwMode,
248 OPC_CheckChild7TypeByHwMode,
249
250 OPC_CheckInteger,
251 OPC_CheckChild0Integer,
252 OPC_CheckChild1Integer,
253 OPC_CheckChild2Integer,
254 OPC_CheckChild3Integer,
255 OPC_CheckChild4Integer,
256 OPC_CheckCondCode,
257 OPC_CheckChild2CondCode,
258 OPC_CheckValueType,
259 OPC_CheckComplexPat,
260 OPC_CheckComplexPat0,
261 OPC_CheckComplexPat1,
262 OPC_CheckComplexPat2,
263 OPC_CheckComplexPat3,
264 OPC_CheckComplexPat4,
265 OPC_CheckComplexPat5,
266 OPC_CheckComplexPat6,
267 OPC_CheckComplexPat7,
268 OPC_CheckAndImm,
269 OPC_CheckOrImm,
270 OPC_CheckImmAllOnesV,
271 OPC_CheckImmAllZerosV,
272 OPC_CheckFoldableChainNode,
273
274 OPC_EmitInteger,
275 // Space-optimized forms that implicitly encode integer VT.
276 OPC_EmitIntegerI8,
277 OPC_EmitIntegerI16,
278 OPC_EmitIntegerI32,
279 OPC_EmitIntegerI64,
280 OPC_EmitIntegerByHwMode,
281 OPC_EmitRegister,
282 OPC_EmitRegisterI32,
283 OPC_EmitRegisterI64,
284 OPC_EmitRegisterByHwMode,
285 OPC_EmitRegister2,
286 OPC_EmitRegisterByHwMode2,
287 OPC_EmitConvertToTarget,
288 OPC_EmitConvertToTarget0,
289 OPC_EmitConvertToTarget1,
290 OPC_EmitConvertToTarget2,
291 OPC_EmitConvertToTarget3,
292 OPC_EmitConvertToTarget4,
293 OPC_EmitConvertToTarget5,
294 OPC_EmitConvertToTarget6,
295 OPC_EmitConvertToTarget7,
296 OPC_EmitMergeInputChains,
297 OPC_EmitMergeInputChains1_0,
298 OPC_EmitMergeInputChains1_1,
299 OPC_EmitMergeInputChains1_2,
300 OPC_EmitCopyToReg,
301 OPC_EmitCopyToReg0,
302 OPC_EmitCopyToReg1,
303 OPC_EmitCopyToReg2,
304 OPC_EmitCopyToReg3,
305 OPC_EmitCopyToReg4,
306 OPC_EmitCopyToReg5,
307 OPC_EmitCopyToReg6,
308 OPC_EmitCopyToReg7,
309 OPC_EmitCopyToRegTwoByte,
310 OPC_EmitNodeXForm,
311 OPC_EmitNode,
312 OPC_EmitNodeByHwMode,
313 // Space-optimized forms that implicitly encode number of result VTs.
314 OPC_EmitNode0,
315 OPC_EmitNode1,
316 OPC_EmitNode2,
317 // Space-optimized forms that implicitly encode EmitNodeInfo.
318 OPC_EmitNode1None,
319 OPC_EmitNode2None,
320 OPC_EmitNode0Chain,
321 OPC_EmitNode1Chain,
322 OPC_EmitNode2Chain,
323 OPC_MorphNodeTo,
324 OPC_MorphNodeToByHwMode,
325 // Space-optimized forms that implicitly encode number of result VTs.
326 OPC_MorphNodeTo0,
327 OPC_MorphNodeTo1,
328 OPC_MorphNodeTo2,
329 // Space-optimized forms that implicitly encode EmitNodeInfo.
330 OPC_MorphNodeTo1None,
331 OPC_MorphNodeTo2None,
332 OPC_MorphNodeTo0Chain,
333 OPC_MorphNodeTo1Chain,
334 OPC_MorphNodeTo2Chain,
335 OPC_MorphNodeTo1GlueInput,
336 OPC_MorphNodeTo2GlueInput,
337 OPC_MorphNodeTo1GlueOutput,
338 OPC_MorphNodeTo2GlueOutput,
339 OPC_CompleteMatch,
340 // Contains 32-bit offset in table for pattern being selected
341 OPC_Coverage
342 };
343
344 enum {
345 OPFL_None = 0, // Node has no chain or glue input and isn't variadic.
346 OPFL_Chain = 1, // Node has a chain input.
347 OPFL_GlueInput = 2, // Node has a glue input.
348 OPFL_GlueOutput = 4, // Node has a glue output.
349 OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
350 OPFL_Variadic0 = 1 << 4, // Node is variadic, root has 0 fixed inputs.
351 OPFL_Variadic1 = 2 << 4, // Node is variadic, root has 1 fixed inputs.
352 OPFL_Variadic2 = 3 << 4, // Node is variadic, root has 2 fixed inputs.
353 OPFL_Variadic3 = 4 << 4, // Node is variadic, root has 3 fixed inputs.
354 OPFL_Variadic4 = 5 << 4, // Node is variadic, root has 4 fixed inputs.
355 OPFL_Variadic5 = 6 << 4, // Node is variadic, root has 5 fixed inputs.
356 OPFL_Variadic6 = 7 << 4, // Node is variadic, root has 6 fixed inputs.
357 OPFL_Variadic7 = 8 << 4, // Node is variadic, root has 7 fixed inputs.
358
359 OPFL_VariadicInfo = 15 << 4 // Mask for extracting the OPFL_VariadicN bits.
360 };
361
362 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
363 /// number of fixed arity values that should be skipped when copying from the
364 /// root.
365 static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
366 return ((Flags&OPFL_VariadicInfo) >> 4)-1;
367 }
368
369
370protected:
371 /// DAGSize - Size of DAG being instruction selected.
372 ///
373 unsigned DAGSize = 0;
374
375 /// ReplaceUses - replace all uses of the old node F with the use
376 /// of the new node T.
377 void ReplaceUses(SDValue F, SDValue T) {
378 CurDAG->ReplaceAllUsesOfValueWith(From: F, To: T);
379 EnforceNodeIdInvariant(N: T.getNode());
380 }
381
382 /// ReplaceUses - replace all uses of the old nodes F with the use
383 /// of the new nodes T.
384 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
385 CurDAG->ReplaceAllUsesOfValuesWith(From: F, To: T, Num);
386 for (unsigned i = 0; i < Num; ++i)
387 EnforceNodeIdInvariant(N: T[i].getNode());
388 }
389
390 /// ReplaceUses - replace all uses of the old node F with the use
391 /// of the new node T.
392 void ReplaceUses(SDNode *F, SDNode *T) {
393 CurDAG->ReplaceAllUsesWith(From: F, To: T);
394 EnforceNodeIdInvariant(N: T);
395 }
396
397 /// Replace all uses of \c F with \c T, then remove \c F from the DAG.
398 void ReplaceNode(SDNode *F, SDNode *T) {
399 CurDAG->ReplaceAllUsesWith(From: F, To: T);
400 EnforceNodeIdInvariant(N: T);
401 CurDAG->RemoveDeadNode(N: F);
402 }
403
404 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
405 /// by tblgen. Others should not call it.
406 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
407 const SDLoc &DL);
408
409 /// getPatternForIndex - Patterns selected by tablegen during ISEL
410 virtual StringRef getPatternForIndex(unsigned index) {
411 llvm_unreachable("Tblgen should generate the implementation of this!");
412 }
413
414 /// getIncludePathForIndex - get the td source location of pattern instantiation
415 virtual StringRef getIncludePathForIndex(unsigned index) {
416 llvm_unreachable("Tblgen should generate the implementation of this!");
417 }
418
419 bool shouldOptForSize(const MachineFunction *MF) const {
420 return CurDAG->shouldOptForSize();
421 }
422
423public:
424 // Calls to these predicates are generated by tblgen.
425 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
426 int64_t DesiredMaskS) const;
427 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
428 int64_t DesiredMaskS) const;
429
430
431 /// CheckPatternPredicate - This function is generated by tblgen in the
432 /// target. It runs the specified pattern predicate and returns true if it
433 /// succeeds or false if it fails. The number is a private implementation
434 /// detail to the code tblgen produces.
435 virtual bool CheckPatternPredicate(unsigned PredNo) const {
436 llvm_unreachable("Tblgen should generate the implementation of this!");
437 }
438
439 /// CheckNodePredicate - This function is generated by tblgen in the target.
440 /// It runs node predicate number PredNo and returns true if it succeeds or
441 /// false if it fails. The number is a private implementation
442 /// detail to the code tblgen produces.
443 virtual bool CheckNodePredicate(SDValue Op, unsigned PredNo) const {
444 llvm_unreachable("Tblgen should generate the implementation of this!");
445 }
446
447 /// CheckNodePredicateWithOperands - This function is generated by tblgen in
448 /// the target.
449 /// It runs node predicate number PredNo and returns true if it succeeds or
450 /// false if it fails. The number is a private implementation detail to the
451 /// code tblgen produces.
452 virtual bool
453 CheckNodePredicateWithOperands(SDValue Op, unsigned PredNo,
454 ArrayRef<SDValue> Operands) const {
455 llvm_unreachable("Tblgen should generate the implementation of this!");
456 }
457
458 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
459 unsigned PatternNo,
460 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
461 llvm_unreachable("Tblgen should generate the implementation of this!");
462 }
463
464 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
465 llvm_unreachable("Tblgen should generate this!");
466 }
467
468 virtual MVT getValueTypeForHwMode(unsigned Index) const {
469 llvm_unreachable("Tblgen should generate the implementation of this!");
470 }
471
472 void SelectCodeCommon(SDNode *NodeToMatch, const uint8_t *MatcherTable,
473 unsigned TableSize);
474
475 /// Return true if complex patterns for this target can mutate the
476 /// DAG.
477 virtual bool ComplexPatternFuncMutatesDAG() const {
478 return false;
479 }
480
481 /// Return whether the node may raise an FP exception.
482 bool mayRaiseFPException(SDNode *Node) const;
483
484 bool isOrEquivalentToAdd(const SDNode *N) const;
485
486private:
487
488 // Calls to these functions are generated by tblgen.
489 void Select_INLINEASM(SDNode *N);
490 void Select_READ_REGISTER(SDNode *Op);
491 void Select_WRITE_REGISTER(SDNode *Op);
492 void Select_UNDEF(SDNode *N);
493 void Select_FAKE_USE(SDNode *N);
494 void Select_RELOC_NONE(SDNode *N);
495 void CannotYetSelect(SDNode *N);
496
497 void Select_FREEZE(SDNode *N);
498 void Select_ARITH_FENCE(SDNode *N);
499 void Select_MEMBARRIER(SDNode *N);
500
501 void Select_CONVERGENCECTRL_ANCHOR(SDNode *N);
502 void Select_CONVERGENCECTRL_ENTRY(SDNode *N);
503 void Select_CONVERGENCECTRL_LOOP(SDNode *N);
504
505 void pushStackMapLiveVariable(SmallVectorImpl<SDValue> &Ops, SDValue Operand,
506 SDLoc DL);
507 void Select_STACKMAP(SDNode *N);
508 void Select_PATCHPOINT(SDNode *N);
509
510 void Select_JUMP_TABLE_DEBUG_INFO(SDNode *N);
511
512private:
513 void DoInstructionSelection();
514 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
515 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
516
517 /// Prepares the landing pad to take incoming values or do other EH
518 /// personality specific tasks. Returns true if the block should be
519 /// instruction selected, false if no code should be emitted for it.
520 bool PrepareEHLandingPad();
521
522 // Mark and Report IPToState for each Block under AsynchEH
523 void reportIPToStateForBlocks(MachineFunction *Fn);
524
525 /// Perform instruction selection on all basic blocks in the function.
526 void SelectAllBasicBlocks(const Function &Fn);
527
528 /// Perform instruction selection on a single basic block, for
529 /// instructions between \p Begin and \p End. \p HadTailCall will be set
530 /// to true if a call in the block was translated as a tail call.
531 void SelectBasicBlock(BasicBlock::const_iterator Begin,
532 BasicBlock::const_iterator End,
533 bool &HadTailCall);
534 void FinishBasicBlock();
535
536 void CodeGenAndEmitDAG();
537
538 /// Generate instructions for lowering the incoming arguments of the
539 /// given function.
540 void LowerArguments(const Function &F);
541
542 void ComputeLiveOutVRegInfo();
543
544 /// Create the scheduler. If a specific scheduler was specified
545 /// via the SchedulerRegistry, use it, otherwise select the
546 /// one preferred by the target.
547 ///
548 ScheduleDAGSDNodes *CreateScheduler();
549
550 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
551 /// state machines that start with a OPC_SwitchOpcode node.
552 std::vector<unsigned> OpcodeOffset;
553
554 void UpdateChains(SDNode *NodeToMatch, SDValue InputChain,
555 SmallVectorImpl<SDNode *> &ChainNodesMatched,
556 bool isMorphNodeTo);
557};
558
559class SelectionDAGISelLegacy : public MachineFunctionPass {
560 std::unique_ptr<SelectionDAGISel> Selector;
561
562public:
563 SelectionDAGISelLegacy(char &ID, std::unique_ptr<SelectionDAGISel> S);
564
565 ~SelectionDAGISelLegacy() override = default;
566
567 void getAnalysisUsage(AnalysisUsage &AU) const override;
568
569 bool runOnMachineFunction(MachineFunction &MF) override;
570};
571
572class SelectionDAGISelPass : public PassInfoMixin<SelectionDAGISelPass> {
573 std::unique_ptr<SelectionDAGISel> Selector;
574
575protected:
576 SelectionDAGISelPass(std::unique_ptr<SelectionDAGISel> Selector)
577 : Selector(std::move(Selector)) {}
578
579public:
580 PreservedAnalyses run(MachineFunction &MF,
581 MachineFunctionAnalysisManager &MFAM);
582 static bool isRequired() { return true; }
583};
584}
585
586#endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */
587