1//===-- CodeGenCommonISel.cpp ---------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines common utilies that are shared between SelectionDAG and
10// GlobalISel frameworks.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/CodeGenCommonISel.h"
15#include "llvm/Analysis/BranchProbabilityInfo.h"
16#include "llvm/CodeGen/MachineBasicBlock.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/TargetInstrInfo.h"
19#include "llvm/CodeGen/TargetOpcodes.h"
20#include "llvm/IR/Constants.h"
21#include "llvm/IR/DebugInfoMetadata.h"
22#include "llvm/IR/Instruction.h"
23#include "llvm/IR/LLVMContext.h"
24#include "llvm/IR/Metadata.h"
25#include "llvm/Support/Casting.h"
26
27#define DEBUG_TYPE "codegen-common"
28
29using namespace llvm;
30
31const MDNode *llvm::getMemCacheHintMetadata(const Instruction &I,
32 unsigned OperandNo) {
33 const MDNode *MD = I.getMetadata(KindID: LLVMContext::MD_mem_cache_hint);
34 if (!MD)
35 return nullptr;
36
37 for (unsigned Idx = 0; Idx + 1 < MD->getNumOperands(); Idx += 2) {
38 const auto *OpNoCI = mdconst::extract<ConstantInt>(MD: MD->getOperand(I: Idx));
39 const auto *Hint = cast<MDNode>(Val: MD->getOperand(I: Idx + 1));
40 if (OpNoCI->getZExtValue() == OperandNo)
41 return Hint;
42 }
43
44 return nullptr;
45}
46
47/// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
48/// is 0.
49MachineBasicBlock *
50StackProtectorDescriptor::addSuccessorMBB(
51 const BasicBlock *BB, MachineBasicBlock *ParentMBB, bool IsLikely,
52 MachineBasicBlock *SuccMBB) {
53 // If SuccBB has not been created yet, create it.
54 if (!SuccMBB) {
55 MachineFunction *MF = ParentMBB->getParent();
56 MachineFunction::iterator BBI(ParentMBB);
57 SuccMBB = MF->CreateMachineBasicBlock(BB);
58 MF->insert(MBBI: ++BBI, MBB: SuccMBB);
59 }
60 // Add it as a successor of ParentMBB.
61 ParentMBB->addSuccessor(
62 Succ: SuccMBB, Prob: BranchProbabilityInfo::getBranchProbStackProtector(IsLikely));
63 return SuccMBB;
64}
65
66/// Given that the input MI is before a partial terminator sequence TSeq, return
67/// true if M + TSeq also a partial terminator sequence.
68///
69/// A Terminator sequence is a sequence of MachineInstrs which at this point in
70/// lowering copy vregs into physical registers, which are then passed into
71/// terminator instructors so we can satisfy ABI constraints. A partial
72/// terminator sequence is an improper subset of a terminator sequence (i.e. it
73/// may be the whole terminator sequence).
74static bool MIIsInTerminatorSequence(const MachineInstr &MI) {
75 // If we do not have a copy or an implicit def, we return true if and only if
76 // MI is a debug value.
77 if (!MI.isCopy() && !MI.isImplicitDef()) {
78 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
79 // physical registers if there is debug info associated with the terminator
80 // of our mbb. We want to include said debug info in our terminator
81 // sequence, so we return true in that case.
82 if (MI.isDebugInstr())
83 return true;
84
85 // For GlobalISel, we may have extension instructions for arguments within
86 // copy sequences. Allow these.
87 switch (MI.getOpcode()) {
88 case TargetOpcode::G_TRUNC:
89 case TargetOpcode::G_ZEXT:
90 case TargetOpcode::G_ANYEXT:
91 case TargetOpcode::G_SEXT:
92 case TargetOpcode::G_MERGE_VALUES:
93 case TargetOpcode::G_UNMERGE_VALUES:
94 case TargetOpcode::G_CONCAT_VECTORS:
95 case TargetOpcode::G_BUILD_VECTOR:
96 case TargetOpcode::G_EXTRACT:
97 return true;
98 default:
99 return false;
100 }
101 }
102
103 // We have left the terminator sequence if we are not doing one of the
104 // following:
105 //
106 // 1. Copying a vreg into a physical register.
107 // 2. Copying a vreg into a vreg.
108 // 3. Defining a register via an implicit def.
109
110 // OPI should always be a register definition...
111 MachineInstr::const_mop_iterator OPI = MI.operands_begin();
112 if (!OPI->isReg() || !OPI->isDef())
113 return false;
114
115 // Defining any register via an implicit def is always ok.
116 if (MI.isImplicitDef())
117 return true;
118
119 // Grab the copy source...
120 MachineInstr::const_mop_iterator OPI2 = OPI;
121 ++OPI2;
122 assert(OPI2 != MI.operands_end()
123 && "Should have a copy implying we should have 2 arguments.");
124
125 // Make sure that the copy dest is not a vreg when the copy source is a
126 // physical register.
127 if (!OPI2->isReg() ||
128 (!OPI->getReg().isPhysical() && OPI2->getReg().isPhysical()))
129 return false;
130
131 return true;
132}
133
134/// Find the split point at which to splice the end of BB into its success stack
135/// protector check machine basic block.
136///
137/// On many platforms, due to ABI constraints, terminators, even before register
138/// allocation, use physical registers. This creates an issue for us since
139/// physical registers at this point can not travel across basic
140/// blocks. Luckily, selectiondag always moves physical registers into vregs
141/// when they enter functions and moves them through a sequence of copies back
142/// into the physical registers right before the terminator creating a
143/// ``Terminator Sequence''. This function is searching for the beginning of the
144/// terminator sequence so that we can ensure that we splice off not just the
145/// terminator, but additionally the copies that move the vregs into the
146/// physical registers.
147MachineBasicBlock::iterator
148llvm::findSplitPointForStackProtector(MachineBasicBlock *BB,
149 const TargetInstrInfo &TII) {
150 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
151 if (SplitPoint == BB->begin())
152 return SplitPoint;
153
154 MachineBasicBlock::iterator Start = BB->begin();
155 MachineBasicBlock::iterator Previous = SplitPoint;
156 do {
157 --Previous;
158 } while (Previous != Start && Previous->isDebugInstr());
159
160 if (TII.isTailCall(Inst: *SplitPoint) &&
161 Previous->getOpcode() == TII.getCallFrameDestroyOpcode()) {
162 // Call frames cannot be nested, so if this frame is describing the tail
163 // call itself, then we must insert before the sequence even starts. For
164 // example:
165 // <split point>
166 // ADJCALLSTACKDOWN ...
167 // <Moves>
168 // ADJCALLSTACKUP ...
169 // TAILJMP somewhere
170 // On the other hand, it could be an unrelated call in which case this tail
171 // call has no register moves of its own and should be the split point. For
172 // example:
173 // ADJCALLSTACKDOWN
174 // CALL something_else
175 // ADJCALLSTACKUP
176 // <split point>
177 // TAILJMP somewhere
178 do {
179 --Previous;
180 if (Previous->isCall())
181 return SplitPoint;
182 } while(Previous->getOpcode() != TII.getCallFrameSetupOpcode());
183
184 return Previous;
185 }
186
187 while (MIIsInTerminatorSequence(MI: *Previous)) {
188 SplitPoint = Previous;
189 if (Previous == Start)
190 break;
191 --Previous;
192 }
193
194 return SplitPoint;
195}
196
197FPClassTest llvm::invertFPClassTestIfSimpler(FPClassTest Test, bool UseFCmp) {
198 FPClassTest InvertedTest = ~Test;
199
200 // Pick the direction with fewer tests
201 // TODO: Handle more combinations of cases that can be handled together
202 switch (static_cast<unsigned>(InvertedTest)) {
203 case fcNan:
204 case fcSNan:
205 case fcQNan:
206 case fcInf:
207 case fcPosInf:
208 case fcNegInf:
209 case fcNormal:
210 case fcPosNormal:
211 case fcNegNormal:
212 case fcSubnormal:
213 case fcPosSubnormal:
214 case fcNegSubnormal:
215 case fcZero:
216 case fcPosZero:
217 case fcNegZero:
218 case fcFinite:
219 case fcPosFinite:
220 case fcNegFinite:
221 case fcZero | fcNan:
222 case fcSubnormal | fcZero:
223 case fcSubnormal | fcZero | fcNan:
224 return InvertedTest;
225 case fcInf | fcNan:
226 case fcPosInf | fcNan:
227 case fcNegInf | fcNan:
228 // If we're trying to use fcmp, we can take advantage of the nan check
229 // behavior of the compare (but this is more instructions in the integer
230 // expansion).
231 return UseFCmp ? InvertedTest : fcNone;
232 default:
233 return fcNone;
234 }
235
236 llvm_unreachable("covered FPClassTest");
237}
238
239static MachineOperand *getSalvageOpsForCopy(const MachineRegisterInfo &MRI,
240 MachineInstr &Copy) {
241 assert(Copy.getOpcode() == TargetOpcode::COPY && "Must be a COPY");
242
243 return &Copy.getOperand(i: 1);
244}
245
246static MachineOperand *getSalvageOpsForTrunc(const MachineRegisterInfo &MRI,
247 MachineInstr &Trunc,
248 SmallVectorImpl<uint64_t> &Ops) {
249 assert(Trunc.getOpcode() == TargetOpcode::G_TRUNC && "Must be a G_TRUNC");
250
251 const auto FromLLT = MRI.getType(Reg: Trunc.getOperand(i: 1).getReg());
252 const auto ToLLT = MRI.getType(Reg: Trunc.defs().begin()->getReg());
253
254 // TODO: Support non-scalar types.
255 if (!FromLLT.isScalar()) {
256 return nullptr;
257 }
258
259 auto ExtOps = DIExpression::getExtOps(FromSize: FromLLT.getSizeInBits(),
260 ToSize: ToLLT.getSizeInBits(), Signed: false);
261 Ops.append(in_start: ExtOps.begin(), in_end: ExtOps.end());
262 return &Trunc.getOperand(i: 1);
263}
264
265static MachineOperand *salvageDebugInfoImpl(const MachineRegisterInfo &MRI,
266 MachineInstr &MI,
267 SmallVectorImpl<uint64_t> &Ops) {
268 switch (MI.getOpcode()) {
269 case TargetOpcode::G_TRUNC:
270 return getSalvageOpsForTrunc(MRI, Trunc&: MI, Ops);
271 case TargetOpcode::COPY:
272 return getSalvageOpsForCopy(MRI, Copy&: MI);
273 default:
274 return nullptr;
275 }
276}
277
278void llvm::salvageDebugInfoForDbgValue(const MachineRegisterInfo &MRI,
279 MachineInstr &MI,
280 ArrayRef<MachineOperand *> DbgUsers) {
281 // These are arbitrary chosen limits on the maximum number of values and the
282 // maximum size of a debug expression we can salvage up to, used for
283 // performance reasons.
284 const unsigned MaxExpressionSize = 128;
285
286 for (auto *DefMO : DbgUsers) {
287 MachineInstr *DbgMI = DefMO->getParent();
288 if (DbgMI->isIndirectDebugValue()) {
289 continue;
290 }
291
292 int UseMOIdx =
293 DbgMI->findRegisterUseOperandIdx(Reg: DefMO->getReg(), /*TRI=*/nullptr);
294 assert(UseMOIdx != -1 && DbgMI->hasDebugOperandForReg(DefMO->getReg()) &&
295 "Must use salvaged instruction as its location");
296
297 // TODO: Support DBG_VALUE_LIST.
298 if (DbgMI->getOpcode() != TargetOpcode::DBG_VALUE) {
299 assert(DbgMI->getOpcode() == TargetOpcode::DBG_VALUE_LIST &&
300 "Must be either DBG_VALUE or DBG_VALUE_LIST");
301 continue;
302 }
303
304 const DIExpression *SalvagedExpr = DbgMI->getDebugExpression();
305
306 SmallVector<uint64_t, 16> Ops;
307 auto Op0 = salvageDebugInfoImpl(MRI, MI, Ops);
308 if (!Op0)
309 continue;
310 SalvagedExpr = DIExpression::appendOpsToArg(Expr: SalvagedExpr, Ops, ArgNo: 0, StackValue: true);
311
312 bool IsValidSalvageExpr =
313 SalvagedExpr->getNumElements() <= MaxExpressionSize;
314 if (IsValidSalvageExpr) {
315 auto &UseMO = DbgMI->getOperand(i: UseMOIdx);
316 UseMO.setReg(Op0->getReg());
317 UseMO.setSubReg(Op0->getSubReg());
318 DbgMI->getDebugExpressionOp().setMetadata(SalvagedExpr);
319
320 LLVM_DEBUG(dbgs() << "SALVAGE: " << *DbgMI << '\n');
321 }
322 }
323}
324