1//===-- EarlyIfConversion.cpp - If-conversion on SSA form machine code ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Early if-conversion is for out-of-order CPUs that don't have a lot of
10// predicable instructions. The goal is to eliminate conditional branches that
11// may mispredict.
12//
13// Instructions from both sides of the branch are executed specutatively, and a
14// cmov instruction selects the result.
15//
16//===----------------------------------------------------------------------===//
17
18#include "llvm/CodeGen/EarlyIfConversion.h"
19#include "llvm/ADT/BitVector.h"
20#include "llvm/ADT/DenseSet.h"
21#include "llvm/ADT/PostOrderIterator.h"
22#include "llvm/ADT/SmallPtrSet.h"
23#include "llvm/ADT/SparseSet.h"
24#include "llvm/ADT/Statistic.h"
25#include "llvm/Analysis/OptimizationRemarkEmitter.h"
26#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
27#include "llvm/CodeGen/MachineDominators.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineLoopInfo.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
34#include "llvm/CodeGen/MachineRegisterInfo.h"
35#include "llvm/CodeGen/MachineTraceMetrics.h"
36#include "llvm/CodeGen/PseudoSourceValue.h"
37#include "llvm/CodeGen/Register.h"
38#include "llvm/CodeGen/TargetInstrInfo.h"
39#include "llvm/CodeGen/TargetRegisterInfo.h"
40#include "llvm/CodeGen/TargetSubtargetInfo.h"
41#include "llvm/InitializePasses.h"
42#include "llvm/Support/CommandLine.h"
43#include "llvm/Support/Debug.h"
44#include "llvm/Support/raw_ostream.h"
45
46using namespace llvm;
47
48#define DEBUG_TYPE "early-ifcvt"
49
50// Absolute maximum number of instructions allowed per speculated block.
51// This bypasses all other heuristics, so it should be set fairly high.
52static cl::opt<unsigned>
53BlockInstrLimit("early-ifcvt-limit", cl::init(Val: 30), cl::Hidden,
54 cl::desc("Maximum number of instructions per speculated block."));
55
56// Stress testing mode - disable heuristics.
57static cl::opt<bool> Stress("stress-early-ifcvt", cl::Hidden,
58 cl::desc("Turn all knobs to 11"));
59
60// Enable analysis of data dependent branches (conditions derived from loads).
61static cl::opt<bool> EnableDataDependentBranchAnalysis(
62 "enable-early-ifcvt-data-dependent", cl::Hidden, cl::init(Val: false),
63 cl::desc("Enable hard-to-predict branch analysis for if-conversion"));
64
65// Limit the number steps we take when searching conditions that depend on
66// values recently loaded from memory.
67static cl::opt<unsigned>
68 MaxNumSteps("early-ifcvt-max-steps", cl::Hidden, cl::init(Val: 16),
69 cl::desc("Limit the number of steps taken when searching for a "
70 "recently loaded value"));
71
72STATISTIC(NumDiamondsSeen, "Number of diamonds");
73STATISTIC(NumDiamondsConv, "Number of diamonds converted");
74STATISTIC(NumTrianglesSeen, "Number of triangles");
75STATISTIC(NumTrianglesConv, "Number of triangles converted");
76STATISTIC(NumDataDependant,
77 "Number of data dependent conditional branches encountered");
78STATISTIC(NumLikelyBiased, "Number of branches with a hot path encountered");
79
80//===----------------------------------------------------------------------===//
81// SSAIfConv
82//===----------------------------------------------------------------------===//
83//
84// The SSAIfConv class performs if-conversion on SSA form machine code after
85// determining if it is possible. The class contains no heuristics; external
86// code should be used to determine when if-conversion is a good idea.
87//
88// SSAIfConv can convert both triangles and diamonds:
89//
90// Triangle: Head Diamond: Head
91// | \ / \_
92// | \ / |
93// | [TF]BB FBB TBB
94// | / \ /
95// | / \ /
96// Tail Tail
97//
98// Instructions in the conditional blocks TBB and/or FBB are spliced into the
99// Head block, and phis in the Tail block are converted to select instructions.
100//
101namespace {
102class SSAIfConv {
103 const TargetInstrInfo *TII;
104 const TargetRegisterInfo *TRI;
105 MachineRegisterInfo *MRI;
106
107public:
108 /// The block containing the conditional branch.
109 MachineBasicBlock *Head;
110
111 /// The block containing phis after the if-then-else.
112 MachineBasicBlock *Tail;
113
114 /// The 'true' conditional block as determined by analyzeBranch.
115 MachineBasicBlock *TBB;
116
117 /// The 'false' conditional block as determined by analyzeBranch.
118 MachineBasicBlock *FBB;
119
120 /// isTriangle - When there is no 'else' block, either TBB or FBB will be
121 /// equal to Tail.
122 bool isTriangle() const { return TBB == Tail || FBB == Tail; }
123
124 /// Returns the Tail predecessor for the True side.
125 MachineBasicBlock *getTPred() const { return TBB == Tail ? Head : TBB; }
126
127 /// Returns the Tail predecessor for the False side.
128 MachineBasicBlock *getFPred() const { return FBB == Tail ? Head : FBB; }
129
130 /// Information about each phi in the Tail block.
131 struct PHIInfo {
132 MachineInstr *PHI;
133 Register TReg, FReg;
134 // Latencies from Cond+Branch, TReg, and FReg to DstReg.
135 int CondCycles = 0, TCycles = 0, FCycles = 0;
136
137 PHIInfo(MachineInstr *phi) : PHI(phi) {}
138 };
139
140 SmallVector<PHIInfo, 8> PHIs;
141
142 /// The branch condition determined by analyzeBranch.
143 SmallVector<MachineOperand, 4> Cond;
144
145private:
146 /// Instructions in Head that define values used by the conditional blocks.
147 /// The hoisted instructions must be inserted after these instructions.
148 SmallPtrSet<MachineInstr*, 8> InsertAfter;
149
150 /// Register units clobbered by the conditional blocks.
151 BitVector ClobberedRegUnits;
152
153 // Scratch pad for findInsertionPoint.
154 SparseSet<MCRegUnit, MCRegUnit, MCRegUnitToIndex> LiveRegUnits;
155
156 /// Insertion point in Head for speculatively executed instructions form TBB
157 /// and FBB.
158 MachineBasicBlock::iterator InsertionPoint;
159
160 /// Return true if all non-terminator instructions in MBB can be safely
161 /// speculated.
162 bool canSpeculateInstrs(MachineBasicBlock *MBB);
163
164 /// Return true if all non-terminator instructions in MBB can be safely
165 /// predicated.
166 bool canPredicateInstrs(MachineBasicBlock *MBB);
167
168 /// Scan through instruction dependencies and update InsertAfter array.
169 /// Return false if any dependency is incompatible with if conversion.
170 bool InstrDependenciesAllowIfConv(MachineInstr *I);
171
172 /// Predicate all instructions of the basic block with current condition
173 /// except for terminators. Reverse the condition if ReversePredicate is set.
174 void PredicateBlock(MachineBasicBlock *MBB, bool ReversePredicate);
175
176 /// Find a valid insertion point in Head.
177 bool findInsertionPoint();
178
179 /// Replace PHI instructions in Tail with selects.
180 void replacePHIInstrs();
181
182 /// Insert selects and rewrite PHI operands to use them.
183 void rewritePHIOperands();
184
185 /// If virtual register has "killed" flag in TBB and FBB basic blocks, remove
186 /// the flag in TBB instruction.
187 void clearRepeatedKillFlagsFromTBB(MachineBasicBlock *TBB,
188 MachineBasicBlock *FBB);
189
190public:
191 /// init - Initialize per-function data structures.
192 void init(MachineFunction &MF) {
193 TII = MF.getSubtarget().getInstrInfo();
194 TRI = MF.getSubtarget().getRegisterInfo();
195 MRI = &MF.getRegInfo();
196 LiveRegUnits.clear();
197 LiveRegUnits.setUniverse(TRI->getNumRegUnits());
198 ClobberedRegUnits.clear();
199 ClobberedRegUnits.resize(N: TRI->getNumRegUnits());
200 }
201
202 /// canConvertIf - If the sub-CFG headed by MBB can be if-converted,
203 /// initialize the internal state, and return true.
204 /// If predicate is set try to predicate the block otherwise try to
205 /// speculatively execute it.
206 bool canConvertIf(MachineBasicBlock *MBB, bool Predicate = false);
207
208 /// convertIf - If-convert the last block passed to canConvertIf(), assuming
209 /// it is possible. Add any blocks that are to be erased to RemoveBlocks.
210 void convertIf(SmallVectorImpl<MachineBasicBlock *> &RemoveBlocks,
211 bool Predicate = false);
212};
213} // end anonymous namespace
214
215/// canSpeculateInstrs - Returns true if all the instructions in MBB can safely
216/// be speculated. The terminators are not considered.
217///
218/// If instructions use any values that are defined in the head basic block,
219/// the defining instructions are added to InsertAfter.
220///
221/// Any clobbered regunits are added to ClobberedRegUnits.
222///
223bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) {
224 // Reject any live-in physregs. It's probably CPSR/EFLAGS, and very hard to
225 // get right.
226 if (!MBB->livein_empty()) {
227 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n");
228 return false;
229 }
230
231 unsigned InstrCount = 0;
232
233 // Check all instructions, except the terminators. It is assumed that
234 // terminators never have side effects or define any used register values.
235 for (MachineInstr &MI :
236 llvm::make_range(x: MBB->begin(), y: MBB->getFirstTerminator())) {
237 if (MI.isDebugInstr())
238 continue;
239
240 if (++InstrCount > BlockInstrLimit && !Stress) {
241 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has more than "
242 << BlockInstrLimit << " instructions.\n");
243 return false;
244 }
245
246 // There shouldn't normally be any phis in a single-predecessor block.
247 if (MI.isPHI()) {
248 LLVM_DEBUG(dbgs() << "Can't hoist: " << MI);
249 return false;
250 }
251
252 // Don't speculate loads. Note that it may be possible and desirable to
253 // speculate GOT or constant pool loads that are guaranteed not to trap,
254 // but we don't support that for now.
255 if (MI.mayLoad()) {
256 LLVM_DEBUG(dbgs() << "Won't speculate load: " << MI);
257 return false;
258 }
259
260 // We never speculate stores, so an AA pointer isn't necessary.
261 bool DontMoveAcrossStore = true;
262 if (!MI.isSafeToMove(SawStore&: DontMoveAcrossStore)) {
263 LLVM_DEBUG(dbgs() << "Can't speculate: " << MI);
264 return false;
265 }
266
267 // Check for any dependencies on Head instructions.
268 if (!InstrDependenciesAllowIfConv(I: &MI))
269 return false;
270 }
271 return true;
272}
273
274/// Check that there is no dependencies preventing if conversion.
275///
276/// If instruction uses any values that are defined in the head basic block,
277/// the defining instructions are added to InsertAfter.
278bool SSAIfConv::InstrDependenciesAllowIfConv(MachineInstr *I) {
279 for (const MachineOperand &MO : I->operands()) {
280 if (MO.isRegMask()) {
281 LLVM_DEBUG(dbgs() << "Won't speculate regmask: " << *I);
282 return false;
283 }
284 if (!MO.isReg())
285 continue;
286 Register Reg = MO.getReg();
287
288 // Remember clobbered regunits.
289 if (MO.isDef() && Reg.isPhysical())
290 for (MCRegUnit Unit : TRI->regunits(Reg: Reg.asMCReg()))
291 ClobberedRegUnits.set(static_cast<unsigned>(Unit));
292
293 if (!MO.readsReg() || !Reg.isVirtual())
294 continue;
295 MachineInstr *DefMI = MRI->getVRegDef(Reg);
296 if (!DefMI || DefMI->getParent() != Head)
297 continue;
298 if (InsertAfter.insert(Ptr: DefMI).second)
299 LLVM_DEBUG(dbgs() << printMBBReference(*I->getParent()) << " depends on "
300 << *DefMI);
301 if (DefMI->isTerminator()) {
302 LLVM_DEBUG(dbgs() << "Can't insert instructions below terminator.\n");
303 return false;
304 }
305 }
306 return true;
307}
308
309/// canPredicateInstrs - Returns true if all the instructions in MBB can safely
310/// be predicates. The terminators are not considered.
311///
312/// If instructions use any values that are defined in the head basic block,
313/// the defining instructions are added to InsertAfter.
314///
315/// Any clobbered regunits are added to ClobberedRegUnits.
316///
317bool SSAIfConv::canPredicateInstrs(MachineBasicBlock *MBB) {
318 // Reject any live-in physregs. It's probably CPSR/EFLAGS, and very hard to
319 // get right.
320 if (!MBB->livein_empty()) {
321 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n");
322 return false;
323 }
324
325 unsigned InstrCount = 0;
326
327 // Check all instructions, except the terminators. It is assumed that
328 // terminators never have side effects or define any used register values.
329 for (MachineBasicBlock::iterator I = MBB->begin(),
330 E = MBB->getFirstTerminator();
331 I != E; ++I) {
332 if (I->isDebugInstr())
333 continue;
334
335 if (++InstrCount > BlockInstrLimit && !Stress) {
336 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has more than "
337 << BlockInstrLimit << " instructions.\n");
338 return false;
339 }
340
341 // There shouldn't normally be any phis in a single-predecessor block.
342 if (I->isPHI()) {
343 LLVM_DEBUG(dbgs() << "Can't predicate: " << *I);
344 return false;
345 }
346
347 // Check that instruction is predicable
348 if (!TII->isPredicable(MI: *I)) {
349 LLVM_DEBUG(dbgs() << "Isn't predicable: " << *I);
350 return false;
351 }
352
353 // Check that instruction is not already predicated.
354 if (TII->isPredicated(MI: *I) && !TII->canPredicatePredicatedInstr(MI: *I)) {
355 LLVM_DEBUG(dbgs() << "Is already predicated: " << *I);
356 return false;
357 }
358
359 // Check for any dependencies on Head instructions.
360 if (!InstrDependenciesAllowIfConv(I: &(*I)))
361 return false;
362 }
363 return true;
364}
365
366// Apply predicate to all instructions in the machine block.
367void SSAIfConv::PredicateBlock(MachineBasicBlock *MBB, bool ReversePredicate) {
368 auto Condition = Cond;
369 if (ReversePredicate) {
370 bool CanRevCond = !TII->reverseBranchCondition(Cond&: Condition);
371 assert(CanRevCond && "Reversed predicate is not supported");
372 (void)CanRevCond;
373 }
374 // Terminators don't need to be predicated as they will be removed.
375 for (MachineBasicBlock::iterator I = MBB->begin(),
376 E = MBB->getFirstTerminator();
377 I != E; ++I) {
378 if (I->isDebugInstr())
379 continue;
380 TII->PredicateInstruction(MI&: *I, Pred: Condition);
381 }
382}
383
384/// Find an insertion point in Head for the speculated instructions. The
385/// insertion point must be:
386///
387/// 1. Before any terminators.
388/// 2. After any instructions in InsertAfter.
389/// 3. Not have any clobbered regunits live.
390///
391/// This function sets InsertionPoint and returns true when successful, it
392/// returns false if no valid insertion point could be found.
393///
394bool SSAIfConv::findInsertionPoint() {
395 // Keep track of live regunits before the current position.
396 // Only track RegUnits that are also in ClobberedRegUnits.
397 LiveRegUnits.clear();
398 SmallVector<MCRegister, 8> Reads;
399 MachineBasicBlock::iterator FirstTerm = Head->getFirstTerminator();
400 MachineBasicBlock::iterator I = Head->end();
401 MachineBasicBlock::iterator B = Head->begin();
402 while (I != B) {
403 --I;
404 // Some of the conditional code depends in I.
405 if (InsertAfter.count(Ptr: &*I)) {
406 LLVM_DEBUG(dbgs() << "Can't insert code after " << *I);
407 return false;
408 }
409
410 // Update live regunits.
411 for (const MachineOperand &MO : I->operands()) {
412 // We're ignoring regmask operands. That is conservatively correct.
413 if (!MO.isReg())
414 continue;
415 Register Reg = MO.getReg();
416 if (!Reg.isPhysical())
417 continue;
418 // I clobbers Reg, so it isn't live before I.
419 if (MO.isDef())
420 for (MCRegUnit Unit : TRI->regunits(Reg: Reg.asMCReg()))
421 LiveRegUnits.erase(Key: Unit);
422 // Unless I reads Reg.
423 if (MO.readsReg())
424 Reads.push_back(Elt: Reg.asMCReg());
425 }
426 // Anything read by I is live before I.
427 while (!Reads.empty())
428 for (MCRegUnit Unit : TRI->regunits(Reg: Reads.pop_back_val()))
429 if (ClobberedRegUnits.test(Idx: static_cast<unsigned>(Unit)))
430 LiveRegUnits.insert(Val: Unit);
431
432 // We can't insert before a terminator.
433 if (I != FirstTerm && I->isTerminator())
434 continue;
435
436 // Some of the clobbered registers are live before I, not a valid insertion
437 // point.
438 if (!LiveRegUnits.empty()) {
439 LLVM_DEBUG({
440 dbgs() << "Would clobber";
441 for (MCRegUnit LRU : LiveRegUnits)
442 dbgs() << ' ' << printRegUnit(LRU, TRI);
443 dbgs() << " live before " << *I;
444 });
445 continue;
446 }
447
448 // This is a valid insertion point.
449 InsertionPoint = I;
450 LLVM_DEBUG(dbgs() << "Can insert before " << *I);
451 return true;
452 }
453 LLVM_DEBUG(dbgs() << "No legal insertion point found.\n");
454 return false;
455}
456
457
458
459/// canConvertIf - analyze the sub-cfg rooted in MBB, and return true if it is
460/// a potential candidate for if-conversion. Fill out the internal state.
461///
462bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB, bool Predicate) {
463 Head = MBB;
464 TBB = FBB = Tail = nullptr;
465
466 if (Head->succ_size() != 2)
467 return false;
468 MachineBasicBlock *Succ0 = Head->succ_begin()[0];
469 MachineBasicBlock *Succ1 = Head->succ_begin()[1];
470
471 // Canonicalize so Succ0 has MBB as its single predecessor.
472 if (Succ0->pred_size() != 1)
473 std::swap(a&: Succ0, b&: Succ1);
474
475 if (Succ0->pred_size() != 1 || Succ0->succ_size() != 1)
476 return false;
477
478 Tail = Succ0->succ_begin()[0];
479
480 // This is not a triangle.
481 if (Tail != Succ1) {
482 // Check for a diamond. We won't deal with any critical edges.
483 if (Succ1->pred_size() != 1 || Succ1->succ_size() != 1 ||
484 Succ1->succ_begin()[0] != Tail)
485 return false;
486 LLVM_DEBUG(dbgs() << "\nDiamond: " << printMBBReference(*Head) << " -> "
487 << printMBBReference(*Succ0) << "/"
488 << printMBBReference(*Succ1) << " -> "
489 << printMBBReference(*Tail) << '\n');
490
491 // Live-in physregs are tricky to get right when speculating code.
492 if (!Tail->livein_empty()) {
493 LLVM_DEBUG(dbgs() << "Tail has live-ins.\n");
494 return false;
495 }
496 } else {
497 LLVM_DEBUG(dbgs() << "\nTriangle: " << printMBBReference(*Head) << " -> "
498 << printMBBReference(*Succ0) << " -> "
499 << printMBBReference(*Tail) << '\n');
500 }
501
502 // This is a triangle or a diamond.
503 // Skip if we cannot predicate and there are no phis skip as there must be
504 // side effects that can only be handled with predication.
505 if (!Predicate && (Tail->empty() || !Tail->front().isPHI())) {
506 LLVM_DEBUG(dbgs() << "No phis in tail.\n");
507 return false;
508 }
509
510 // The branch we're looking to eliminate must be analyzable.
511 Cond.clear();
512 if (TII->analyzeBranch(MBB&: *Head, TBB, FBB, Cond)) {
513 LLVM_DEBUG(dbgs() << "Branch not analyzable.\n");
514 return false;
515 }
516
517 // This is weird, probably some sort of degenerate CFG.
518 if (!TBB) {
519 LLVM_DEBUG(dbgs() << "analyzeBranch didn't find conditional branch.\n");
520 return false;
521 }
522
523 // Make sure the analyzed branch is conditional; one of the successors
524 // could be a landing pad. (Empty landing pads can be generated on Windows.)
525 if (Cond.empty()) {
526 LLVM_DEBUG(dbgs() << "analyzeBranch found an unconditional branch.\n");
527 return false;
528 }
529
530 // analyzeBranch doesn't set FBB on a fall-through branch.
531 // Make sure it is always set.
532 FBB = TBB == Succ0 ? Succ1 : Succ0;
533
534 // Any phis in the tail block must be convertible to selects.
535 PHIs.clear();
536 MachineBasicBlock *TPred = getTPred();
537 MachineBasicBlock *FPred = getFPred();
538 for (MachineBasicBlock::iterator I = Tail->begin(), E = Tail->end();
539 I != E && I->isPHI(); ++I) {
540 PHIs.push_back(Elt: &*I);
541 PHIInfo &PI = PHIs.back();
542 // Find PHI operands corresponding to TPred and FPred.
543 for (unsigned i = 1; i != PI.PHI->getNumOperands(); i += 2) {
544 if (PI.PHI->getOperand(i: i+1).getMBB() == TPred)
545 PI.TReg = PI.PHI->getOperand(i).getReg();
546 if (PI.PHI->getOperand(i: i+1).getMBB() == FPred)
547 PI.FReg = PI.PHI->getOperand(i).getReg();
548 }
549 assert(PI.TReg.isVirtual() && "Bad PHI");
550 assert(PI.FReg.isVirtual() && "Bad PHI");
551
552 // Get target information.
553 if (!TII->canInsertSelect(MBB: *Head, Cond, DstReg: PI.PHI->getOperand(i: 0).getReg(),
554 TrueReg: PI.TReg, FalseReg: PI.FReg, CondCycles&: PI.CondCycles, TrueCycles&: PI.TCycles,
555 FalseCycles&: PI.FCycles)) {
556 LLVM_DEBUG(dbgs() << "Can't convert: " << *PI.PHI);
557 return false;
558 }
559 }
560
561 // Check that the conditional instructions can be speculated.
562 InsertAfter.clear();
563 ClobberedRegUnits.reset();
564 if (Predicate) {
565 if (TBB != Tail && !canPredicateInstrs(MBB: TBB))
566 return false;
567 if (FBB != Tail && !canPredicateInstrs(MBB: FBB))
568 return false;
569 } else {
570 if (TBB != Tail && !canSpeculateInstrs(MBB: TBB))
571 return false;
572 if (FBB != Tail && !canSpeculateInstrs(MBB: FBB))
573 return false;
574 }
575
576 // Try to find a valid insertion point for the speculated instructions in the
577 // head basic block.
578 if (!findInsertionPoint())
579 return false;
580
581 if (isTriangle())
582 ++NumTrianglesSeen;
583 else
584 ++NumDiamondsSeen;
585 return true;
586}
587
588/// \return true iff the two registers are known to have the same value.
589static bool hasSameValue(const MachineRegisterInfo &MRI,
590 const TargetInstrInfo *TII, Register TReg,
591 Register FReg) {
592 if (TReg == FReg)
593 return true;
594
595 if (!TReg.isVirtual() || !FReg.isVirtual())
596 return false;
597
598 const MachineInstr *TDef = MRI.getUniqueVRegDef(Reg: TReg);
599 const MachineInstr *FDef = MRI.getUniqueVRegDef(Reg: FReg);
600 if (!TDef || !FDef)
601 return false;
602
603 // If there are side-effects, all bets are off.
604 if (TDef->hasUnmodeledSideEffects())
605 return false;
606
607 // If the instruction could modify memory, or there may be some intervening
608 // store between the two, we can't consider them to be equal.
609 if (TDef->mayLoadOrStore() && !TDef->isDereferenceableInvariantLoad())
610 return false;
611
612 // We also can't guarantee that they are the same if, for example, the
613 // instructions are both a copy from a physical reg, because some other
614 // instruction may have modified the value in that reg between the two
615 // defining insts.
616 if (any_of(Range: TDef->uses(), P: [](const MachineOperand &MO) {
617 return MO.isReg() && MO.getReg().isPhysical();
618 }))
619 return false;
620
621 // Check whether the two defining instructions produce the same value(s).
622 if (!TII->produceSameValue(MI0: *TDef, MI1: *FDef, MRI: &MRI))
623 return false;
624
625 // Further, check that the two defs come from corresponding operands.
626 int TIdx = TDef->findRegisterDefOperandIdx(Reg: TReg, /*TRI=*/nullptr);
627 int FIdx = FDef->findRegisterDefOperandIdx(Reg: FReg, /*TRI=*/nullptr);
628 if (TIdx == -1 || FIdx == -1)
629 return false;
630
631 return TIdx == FIdx;
632}
633
634/// replacePHIInstrs - Completely replace PHI instructions with selects.
635/// This is possible when the only Tail predecessors are the if-converted
636/// blocks.
637void SSAIfConv::replacePHIInstrs() {
638 assert(Tail->pred_size() == 2 && "Cannot replace PHIs");
639 MachineBasicBlock::iterator FirstTerm = Head->getFirstTerminator();
640 assert(FirstTerm != Head->end() && "No terminators");
641 DebugLoc HeadDL = FirstTerm->getDebugLoc();
642
643 // Convert all PHIs to select instructions inserted before FirstTerm.
644 for (PHIInfo &PI : PHIs) {
645 LLVM_DEBUG(dbgs() << "If-converting " << *PI.PHI);
646 Register DstReg = PI.PHI->getOperand(i: 0).getReg();
647 if (hasSameValue(MRI: *MRI, TII, TReg: PI.TReg, FReg: PI.FReg)) {
648 // We do not need the select instruction if both incoming values are
649 // equal, but we do need a COPY.
650 BuildMI(BB&: *Head, I: FirstTerm, MIMD: HeadDL, MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: DstReg)
651 .addReg(RegNo: PI.TReg);
652 } else {
653 TII->insertSelect(MBB&: *Head, I: FirstTerm, DL: HeadDL, DstReg, Cond, TrueReg: PI.TReg,
654 FalseReg: PI.FReg);
655 }
656 LLVM_DEBUG(dbgs() << " --> " << *std::prev(FirstTerm));
657 PI.PHI->eraseFromParent();
658 PI.PHI = nullptr;
659 }
660}
661
662/// rewritePHIOperands - When there are additional Tail predecessors, insert
663/// select instructions in Head and rewrite PHI operands to use the selects.
664/// Keep the PHI instructions in Tail to handle the other predecessors.
665void SSAIfConv::rewritePHIOperands() {
666 MachineBasicBlock::iterator FirstTerm = Head->getFirstTerminator();
667 assert(FirstTerm != Head->end() && "No terminators");
668 DebugLoc HeadDL = FirstTerm->getDebugLoc();
669
670 // Convert all PHIs to select instructions inserted before FirstTerm.
671 for (PHIInfo &PI : PHIs) {
672 Register DstReg;
673
674 LLVM_DEBUG(dbgs() << "If-converting " << *PI.PHI);
675 if (hasSameValue(MRI: *MRI, TII, TReg: PI.TReg, FReg: PI.FReg)) {
676 // We do not need the select instruction if both incoming values are
677 // equal.
678 DstReg = PI.TReg;
679 } else {
680 Register PHIDst = PI.PHI->getOperand(i: 0).getReg();
681 DstReg = MRI->createVirtualRegister(RegClass: MRI->getRegClass(Reg: PHIDst));
682 TII->insertSelect(MBB&: *Head, I: FirstTerm, DL: HeadDL,
683 DstReg, Cond, TrueReg: PI.TReg, FalseReg: PI.FReg);
684 LLVM_DEBUG(dbgs() << " --> " << *std::prev(FirstTerm));
685 }
686
687 // Rewrite PHI operands TPred -> (DstReg, Head), remove FPred.
688 for (unsigned i = PI.PHI->getNumOperands(); i != 1; i -= 2) {
689 MachineBasicBlock *MBB = PI.PHI->getOperand(i: i-1).getMBB();
690 if (MBB == getTPred()) {
691 PI.PHI->getOperand(i: i-1).setMBB(Head);
692 PI.PHI->getOperand(i: i-2).setReg(DstReg);
693 } else if (MBB == getFPred()) {
694 PI.PHI->removeOperand(OpNo: i-1);
695 PI.PHI->removeOperand(OpNo: i-2);
696 }
697 }
698 LLVM_DEBUG(dbgs() << " --> " << *PI.PHI);
699 }
700}
701
702void SSAIfConv::clearRepeatedKillFlagsFromTBB(MachineBasicBlock *TBB,
703 MachineBasicBlock *FBB) {
704 assert(TBB != FBB);
705
706 // Collect virtual registers killed in FBB.
707 SmallDenseSet<Register> FBBKilledRegs;
708 for (MachineInstr &MI : FBB->instrs()) {
709 for (MachineOperand &MO : MI.operands()) {
710 if (MO.isReg() && MO.isKill() && MO.getReg().isVirtual())
711 FBBKilledRegs.insert(V: MO.getReg());
712 }
713 }
714
715 if (FBBKilledRegs.empty())
716 return;
717
718 // Find the same killed registers in TBB and clear kill flags for them.
719 for (MachineInstr &MI : TBB->instrs()) {
720 for (MachineOperand &MO : MI.operands()) {
721 if (MO.isReg() && MO.isKill() && FBBKilledRegs.contains(V: MO.getReg()))
722 MO.setIsKill(false);
723 }
724 }
725}
726
727/// convertIf - Execute the if conversion after canConvertIf has determined the
728/// feasibility.
729///
730/// Any basic blocks that need to be erased will be added to RemoveBlocks.
731///
732void SSAIfConv::convertIf(SmallVectorImpl<MachineBasicBlock *> &RemoveBlocks,
733 bool Predicate) {
734 assert(Head && Tail && TBB && FBB && "Call canConvertIf first.");
735
736 // Update statistics.
737 if (isTriangle())
738 ++NumTrianglesConv;
739 else
740 ++NumDiamondsConv;
741
742 // If both blocks are going to be merged into Head, remove "killed" flag in
743 // TBB for registers, which are killed in TBB and FBB. Otherwise, register
744 // will be killed twice in Head after splice. Register killed twice is an
745 // incorrect MIR.
746 if (TBB != Tail && FBB != Tail)
747 clearRepeatedKillFlagsFromTBB(TBB, FBB);
748
749 // Move all instructions into Head, except for the terminators.
750 if (TBB != Tail) {
751 if (Predicate)
752 PredicateBlock(MBB: TBB, /*ReversePredicate=*/false);
753 Head->splice(Where: InsertionPoint, Other: TBB, From: TBB->begin(), To: TBB->getFirstTerminator());
754 }
755 if (FBB != Tail) {
756 if (Predicate)
757 PredicateBlock(MBB: FBB, /*ReversePredicate=*/true);
758 Head->splice(Where: InsertionPoint, Other: FBB, From: FBB->begin(), To: FBB->getFirstTerminator());
759 }
760 // Are there extra Tail predecessors?
761 bool ExtraPreds = Tail->pred_size() != 2;
762 if (ExtraPreds)
763 rewritePHIOperands();
764 else
765 replacePHIInstrs();
766
767 // Fix up the CFG, temporarily leave Head without any successors.
768 Head->removeSuccessor(Succ: TBB);
769 Head->removeSuccessor(Succ: FBB, NormalizeSuccProbs: true);
770 if (TBB != Tail)
771 TBB->removeSuccessor(Succ: Tail, NormalizeSuccProbs: true);
772 if (FBB != Tail)
773 FBB->removeSuccessor(Succ: Tail, NormalizeSuccProbs: true);
774
775 // Fix up Head's terminators.
776 // It should become a single branch or a fallthrough.
777 DebugLoc HeadDL = Head->getFirstTerminator()->getDebugLoc();
778 TII->removeBranch(MBB&: *Head);
779
780 // Mark the now empty conditional blocks for removal and move them to the end.
781 // It is likely that Head can fall
782 // through to Tail, and we can join the two blocks.
783 if (TBB != Tail) {
784 RemoveBlocks.push_back(Elt: TBB);
785 if (TBB != &TBB->getParent()->back())
786 TBB->moveAfter(NewBefore: &TBB->getParent()->back());
787 }
788 if (FBB != Tail) {
789 RemoveBlocks.push_back(Elt: FBB);
790 if (FBB != &FBB->getParent()->back())
791 FBB->moveAfter(NewBefore: &FBB->getParent()->back());
792 }
793
794 assert(Head->succ_empty() && "Additional head successors?");
795 if (!ExtraPreds && Head->isLayoutSuccessor(MBB: Tail)) {
796 // Splice Tail onto the end of Head.
797 LLVM_DEBUG(dbgs() << "Joining tail " << printMBBReference(*Tail)
798 << " into head " << printMBBReference(*Head) << '\n');
799 Head->splice(Where: Head->end(), Other: Tail,
800 From: Tail->begin(), To: Tail->end());
801 Head->transferSuccessorsAndUpdatePHIs(FromMBB: Tail);
802 RemoveBlocks.push_back(Elt: Tail);
803 if (Tail != &Tail->getParent()->back())
804 Tail->moveAfter(NewBefore: &Tail->getParent()->back());
805 } else {
806 // We need a branch to Tail, let code placement work it out later.
807 LLVM_DEBUG(dbgs() << "Converting to unconditional branch.\n");
808 SmallVector<MachineOperand, 0> EmptyCond;
809 TII->insertBranch(MBB&: *Head, TBB: Tail, FBB: nullptr, Cond: EmptyCond, DL: HeadDL);
810 Head->addSuccessor(Succ: Tail);
811 }
812 LLVM_DEBUG(dbgs() << *Head);
813}
814
815//===----------------------------------------------------------------------===//
816// EarlyIfConverter Pass
817//===----------------------------------------------------------------------===//
818
819namespace {
820class EarlyIfConverter {
821 const TargetInstrInfo *TII = nullptr;
822 const TargetRegisterInfo *TRI = nullptr;
823 MCSchedModel SchedModel;
824 MachineRegisterInfo *MRI = nullptr;
825 MachineDominatorTree *DomTree = nullptr;
826 MachineLoopInfo *Loops = nullptr;
827 MachineTraceMetrics *Traces = nullptr;
828 MachineTraceMetrics::Ensemble *MinInstr = nullptr;
829 MachineBranchProbabilityInfo *MBPI = nullptr;
830 SSAIfConv IfConv;
831
832public:
833 EarlyIfConverter(MachineDominatorTree &DT, MachineLoopInfo &LI,
834 MachineTraceMetrics &MTM, MachineBranchProbabilityInfo *MBPI)
835 : DomTree(&DT), Loops(&LI), Traces(&MTM), MBPI(MBPI) {}
836 EarlyIfConverter() = delete;
837
838 bool run(MachineFunction &MF);
839
840private:
841 bool tryConvertIf(MachineBasicBlock *);
842 void invalidateTraces();
843 bool shouldConvertIf();
844 bool isConditionDataDependent();
845 bool doOperandsComeFromMemory(Register Reg);
846};
847
848class EarlyIfConverterLegacy : public MachineFunctionPass {
849public:
850 static char ID;
851 EarlyIfConverterLegacy() : MachineFunctionPass(ID) {}
852 void getAnalysisUsage(AnalysisUsage &AU) const override;
853 bool runOnMachineFunction(MachineFunction &MF) override;
854 StringRef getPassName() const override { return "Early If-Conversion"; }
855};
856} // end anonymous namespace
857
858char EarlyIfConverterLegacy::ID = 0;
859char &llvm::EarlyIfConverterLegacyID = EarlyIfConverterLegacy::ID;
860
861INITIALIZE_PASS_BEGIN(EarlyIfConverterLegacy, DEBUG_TYPE, "Early If Converter",
862 false, false)
863INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfoWrapperPass)
864INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
865INITIALIZE_PASS_DEPENDENCY(MachineTraceMetricsWrapperPass)
866INITIALIZE_PASS_END(EarlyIfConverterLegacy, DEBUG_TYPE, "Early If Converter",
867 false, false)
868
869void EarlyIfConverterLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
870 AU.addRequired<MachineBranchProbabilityInfoWrapperPass>();
871 AU.addRequired<MachineDominatorTreeWrapperPass>();
872 AU.addPreserved<MachineDominatorTreeWrapperPass>();
873 AU.addRequired<MachineLoopInfoWrapperPass>();
874 AU.addPreserved<MachineLoopInfoWrapperPass>();
875 AU.addRequired<MachineTraceMetricsWrapperPass>();
876 AU.addPreserved<MachineTraceMetricsWrapperPass>();
877 MachineFunctionPass::getAnalysisUsage(AU);
878}
879
880namespace {
881/// Update the dominator tree after if-conversion erased some blocks.
882void updateDomTree(MachineDominatorTree *DomTree, const SSAIfConv &IfConv,
883 ArrayRef<MachineBasicBlock *> Removed) {
884 // convertIf can remove TBB, FBB, and Tail can be merged into Head.
885 // TBB and FBB should not dominate any blocks.
886 // Tail children should be transferred to Head.
887 MachineDomTreeNode *HeadNode = DomTree->getNode(BB: IfConv.Head);
888 for (auto *B : Removed) {
889 MachineDomTreeNode *Node = DomTree->getNode(BB: B);
890 assert(Node != HeadNode && "Cannot erase the head node");
891 while (!Node->isLeaf()) {
892 assert(Node->getBlock() == IfConv.Tail && "Unexpected children");
893 DomTree->changeImmediateDominator(N: *Node->begin(), NewIDom: HeadNode);
894 }
895 DomTree->eraseNode(BB: B);
896 }
897}
898
899/// Update LoopInfo after if-conversion.
900void updateLoops(MachineLoopInfo *Loops,
901 ArrayRef<MachineBasicBlock *> Removed) {
902 // If-conversion doesn't change loop structure, and it doesn't mess with back
903 // edges, so updating LoopInfo is simply removing the dead blocks.
904 for (auto *B : Removed)
905 Loops->removeBlock(BB: B);
906}
907} // namespace
908
909/// Invalidate MachineTraceMetrics before if-conversion.
910void EarlyIfConverter::invalidateTraces() {
911 Traces->verifyAnalysis();
912 Traces->invalidate(MBB: IfConv.Head);
913 Traces->invalidate(MBB: IfConv.Tail);
914 Traces->invalidate(MBB: IfConv.TBB);
915 Traces->invalidate(MBB: IfConv.FBB);
916 Traces->verifyAnalysis();
917}
918
919static bool isConstantPoolLoad(const MachineInstr *MI) {
920 return MI->mayLoad() && any_of(Range: MI->memoperands(), P: [](MachineMemOperand *MOp) {
921 const PseudoSourceValue *PSV = MOp->getPseudoValue();
922 return PSV && PSV->isConstantPool();
923 });
924}
925
926/// Check if there are any calls in the range (From, To].
927static bool callInRange(const MachineInstr *From, const MachineInstr *To) {
928 constexpr int MaxInstructionsToCheck = 64;
929 int Count = 0;
930 auto InstrRange =
931 make_range(x: std::next(x: From->getIterator()), y: To->getIterator());
932 return any_of(Range&: InstrRange, P: [&](const MachineInstr &MI) {
933 return ++Count > MaxInstructionsToCheck || MI.isCall();
934 });
935}
936
937/// Check if a register's value comes from a memory load by walking the
938/// def-use chain. We want to prioritize converting branches which
939/// depend on values loaded from memory (unless they are loop invariant,
940/// or come from a constant pool). Only consider loads that are in the
941/// same basic block as the branch to ensure the load is "immediately"
942/// before the branch in program time.
943bool EarlyIfConverter::doOperandsComeFromMemory(Register Reg) {
944 if (!Reg.isVirtual())
945 return false;
946
947 // Walk the def-use chain.
948 SmallPtrSet<const MachineInstr *, 8> VisitedInstrs;
949 SmallVector<const MachineInstr *> Worklist;
950 SmallVector<Register, 16> VisitedRegs;
951
952 MachineInstr *DefMI = MRI->getVRegDef(Reg);
953 // The operand is defined outside of the function - it does not
954 // come from memory access.
955 if (!DefMI)
956 return false;
957
958 Worklist.push_back(Elt: DefMI);
959 VisitedRegs.push_back(Elt: Reg);
960
961 while (!Worklist.empty() && VisitedInstrs.size() < MaxNumSteps) {
962 const MachineInstr *MI = Worklist.pop_back_val();
963 if (!VisitedInstrs.insert(Ptr: MI).second)
964 continue;
965
966 // Stop walking if we encounter an instruction outside the head block.
967 if (MI->getParent() != IfConv.Head)
968 break;
969
970 // Check if this instruction is a load, and there are no calls between
971 // the load and the branch (which would break the "close in time"
972 // assumption).
973 if (MI->mayLoad() && !isConstantPoolLoad(MI) &&
974 !MI->isDereferenceableInvariantLoad() &&
975 !callInRange(From: MI, To: &*IfConv.Head->getFirstTerminator()))
976 return true;
977
978 // Walk through all register use operands and find their definitions.
979 for (const MachineOperand &MO : MI->operands()) {
980 if (!MO.isReg() || !MO.isUse())
981 continue;
982 Register UseReg = MO.getReg();
983 if (!UseReg.isVirtual())
984 continue;
985
986 if (MachineInstr *UseDef = MRI->getVRegDef(Reg: UseReg)) {
987 if (!VisitedInstrs.count(Ptr: UseDef)) {
988 Worklist.push_back(Elt: UseDef);
989 VisitedRegs.push_back(Elt: UseReg);
990 }
991 }
992 }
993 }
994
995 return false;
996}
997
998/// Check if the branch condition is data-dependent (comes from memory loads).
999bool EarlyIfConverter::isConditionDataDependent() {
1000 TargetInstrInfo::MachineBranchPredicate MBP;
1001 if (TII->analyzeBranchPredicate(MBB&: *IfConv.Head, MBP, /*AllowModify=*/false))
1002 return false;
1003
1004 if (!MBP.ConditionDef)
1005 return false;
1006
1007 // If the branch is biased (not 50/50), don't consider it data dependent.
1008 // This is to prevent converting unprofitable checks such as
1009 // `x[i] != 0;`
1010 auto TBBProb = MBPI->getEdgeProbability(Src: IfConv.Head, Dst: IfConv.TBB);
1011 auto FBBProb = MBPI->getEdgeProbability(Src: IfConv.Head, Dst: IfConv.FBB);
1012 if (TBBProb != FBBProb) {
1013 ++NumLikelyBiased;
1014 return false;
1015 }
1016
1017 // Check if operands used to compute the branch condition were loaded recently
1018 // from memory, starting by the ConditionDef itself and walking up the use-def
1019 // chain.
1020 if (doOperandsComeFromMemory(Reg: MBP.ConditionDef->getOperand(i: 0).getReg())) {
1021 ++NumDataDependant;
1022 return true;
1023 }
1024
1025 return false;
1026}
1027
1028// Adjust cycles with downward saturation.
1029static unsigned adjCycles(unsigned Cyc, int Delta) {
1030 if (Delta < 0 && Cyc + Delta > Cyc)
1031 return 0;
1032 return Cyc + Delta;
1033}
1034
1035namespace {
1036/// Helper class to simplify emission of cycle counts into optimization remarks.
1037struct Cycles {
1038 const char *Key;
1039 unsigned Value;
1040};
1041template <typename Remark> Remark &operator<<(Remark &R, Cycles C) {
1042 return R << ore::NV(C.Key, C.Value) << (C.Value == 1 ? " cycle" : " cycles");
1043}
1044} // anonymous namespace
1045
1046/// Apply cost model and heuristics to the if-conversion in IfConv.
1047/// Return true if the conversion is a good idea.
1048///
1049bool EarlyIfConverter::shouldConvertIf() {
1050 // Stress testing mode disables all cost considerations.
1051 if (Stress)
1052 return true;
1053
1054 // Do not try to if-convert if the condition has a high chance of being
1055 // predictable.
1056 MachineLoop *CurrentLoop = Loops->getLoopFor(BB: IfConv.Head);
1057 // If the condition is in a loop, consider it predictable if the condition
1058 // itself or all its operands are loop-invariant. E.g. this considers a load
1059 // from a loop-invariant address predictable; we were unable to prove that it
1060 // doesn't alias any of the memory-writes in the loop, but it is likely to
1061 // read to same value multiple times.
1062 if (CurrentLoop && any_of(Range&: IfConv.Cond, P: [&](MachineOperand &MO) {
1063 if (!MO.isReg() || !MO.isUse())
1064 return false;
1065 Register Reg = MO.getReg();
1066 if (Reg.isPhysical())
1067 return false;
1068
1069 MachineInstr *Def = MRI->getVRegDef(Reg);
1070 return CurrentLoop->isLoopInvariant(I&: *Def) ||
1071 all_of(Range: Def->operands(), P: [&](MachineOperand &Op) {
1072 if (Op.isImm())
1073 return true;
1074 if (!Op.isReg() || !Op.isUse())
1075 return true;
1076 Register Reg = Op.getReg();
1077 if (Reg.isPhysical())
1078 return false;
1079
1080 MachineInstr *Def = MRI->getVRegDef(Reg);
1081 return CurrentLoop->isLoopInvariant(I&: *Def);
1082 });
1083 }))
1084 return false;
1085
1086 if (!MinInstr)
1087 MinInstr = Traces->getEnsemble(MachineTraceStrategy::TS_MinInstrCount);
1088
1089 MachineTraceMetrics::Trace TBBTrace = MinInstr->getTrace(MBB: IfConv.getTPred());
1090 MachineTraceMetrics::Trace FBBTrace = MinInstr->getTrace(MBB: IfConv.getFPred());
1091 LLVM_DEBUG(dbgs() << "TBB: " << TBBTrace << "FBB: " << FBBTrace);
1092 unsigned MinCrit = std::min(a: TBBTrace.getCriticalPath(),
1093 b: FBBTrace.getCriticalPath());
1094
1095 // Set a somewhat arbitrary limit on the critical path extension we accept.
1096 // When hard-to-predict analysis is enabled, use full MispredictPenalty for
1097 // hard-to-predict branches, half for others. Otherwise use half for all.
1098 bool DataDependent = false;
1099 if (EnableDataDependentBranchAnalysis)
1100 DataDependent = isConditionDataDependent();
1101
1102 unsigned CritLimit = DataDependent ? SchedModel.MispredictPenalty
1103 : SchedModel.MispredictPenalty / 2;
1104
1105 MachineBasicBlock &MBB = *IfConv.Head;
1106 MachineOptimizationRemarkEmitter MORE(*MBB.getParent(), nullptr);
1107
1108 // Emit analysis remark about data-dependent condition.
1109 if (DataDependent) {
1110 MORE.emit(RemarkBuilder: [&]() {
1111 return MachineOptimizationRemarkAnalysis(DEBUG_TYPE,
1112 "DataDependentCondition",
1113 MBB.back().getDebugLoc(), &MBB)
1114 << "branch condition is data-dependent (from memory load), "
1115 << "using higher CritLimit of " << ore::NV("CritLimit", CritLimit)
1116 << " cycles";
1117 });
1118 }
1119
1120 // If-conversion only makes sense when there is unexploited ILP. Compute the
1121 // maximum-ILP resource length of the trace after if-conversion. Compare it
1122 // to the shortest critical path.
1123 SmallVector<const MachineBasicBlock*, 1> ExtraBlocks;
1124 if (IfConv.TBB != IfConv.Tail)
1125 ExtraBlocks.push_back(Elt: IfConv.TBB);
1126 unsigned ResLength = FBBTrace.getResourceLength(Extrablocks: ExtraBlocks);
1127 LLVM_DEBUG(dbgs() << "Resource length " << ResLength
1128 << ", minimal critical path " << MinCrit << '\n');
1129 if (ResLength > MinCrit + CritLimit) {
1130 LLVM_DEBUG(dbgs() << "Not enough available ILP.\n");
1131 MORE.emit(RemarkBuilder: [&]() {
1132 MachineOptimizationRemarkMissed R(DEBUG_TYPE, "IfConversion",
1133 MBB.findDebugLoc(MBBI: MBB.back()), &MBB);
1134 R << "did not if-convert branch: the resulting critical path ("
1135 << Cycles{.Key: "ResLength", .Value: ResLength}
1136 << ") would extend the shorter leg's critical path ("
1137 << Cycles{.Key: "MinCrit", .Value: MinCrit} << ") by more than the threshold of "
1138 << Cycles{.Key: "CritLimit", .Value: CritLimit}
1139 << ", which cannot be hidden by available ILP.";
1140 return R;
1141 });
1142 return false;
1143 }
1144
1145 // Assume that the depth of the first head terminator will also be the depth
1146 // of the select instruction inserted, as determined by the flag dependency.
1147 // TBB / FBB data dependencies may delay the select even more.
1148 MachineTraceMetrics::Trace HeadTrace = MinInstr->getTrace(MBB: IfConv.Head);
1149 unsigned BranchDepth =
1150 HeadTrace.getInstrCycles(MI: *IfConv.Head->getFirstTerminator()).Depth;
1151 LLVM_DEBUG(dbgs() << "Branch depth: " << BranchDepth << '\n');
1152
1153 // Look at all the tail phis, and compute the critical path extension caused
1154 // by inserting select instructions.
1155 MachineTraceMetrics::Trace TailTrace = MinInstr->getTrace(MBB: IfConv.Tail);
1156 struct CriticalPathInfo {
1157 unsigned Extra; // Count of extra cycles that the component adds.
1158 unsigned Depth; // Absolute depth of the component in cycles.
1159 };
1160 CriticalPathInfo Cond{};
1161 CriticalPathInfo TBlock{};
1162 CriticalPathInfo FBlock{};
1163 bool ShouldConvert = true;
1164 for (SSAIfConv::PHIInfo &PI : IfConv.PHIs) {
1165 unsigned Slack = TailTrace.getInstrSlack(MI: *PI.PHI);
1166 unsigned MaxDepth = Slack + TailTrace.getInstrCycles(MI: *PI.PHI).Depth;
1167 LLVM_DEBUG(dbgs() << "Slack " << Slack << ":\t" << *PI.PHI);
1168
1169 // The condition is pulled into the critical path.
1170 unsigned CondDepth = adjCycles(Cyc: BranchDepth, Delta: PI.CondCycles);
1171 if (CondDepth > MaxDepth) {
1172 unsigned Extra = CondDepth - MaxDepth;
1173 LLVM_DEBUG(dbgs() << "Condition adds " << Extra << " cycles.\n");
1174 if (Extra > Cond.Extra)
1175 Cond = {.Extra: Extra, .Depth: CondDepth};
1176 if (Extra > CritLimit) {
1177 LLVM_DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n');
1178 ShouldConvert = false;
1179 }
1180 }
1181
1182 // The TBB value is pulled into the critical path.
1183 unsigned TDepth = adjCycles(Cyc: TBBTrace.getPHIDepth(PHI: *PI.PHI), Delta: PI.TCycles);
1184 if (TDepth > MaxDepth) {
1185 unsigned Extra = TDepth - MaxDepth;
1186 LLVM_DEBUG(dbgs() << "TBB data adds " << Extra << " cycles.\n");
1187 if (Extra > TBlock.Extra)
1188 TBlock = {.Extra: Extra, .Depth: TDepth};
1189 if (Extra > CritLimit) {
1190 LLVM_DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n');
1191 ShouldConvert = false;
1192 }
1193 }
1194
1195 // The FBB value is pulled into the critical path.
1196 unsigned FDepth = adjCycles(Cyc: FBBTrace.getPHIDepth(PHI: *PI.PHI), Delta: PI.FCycles);
1197 if (FDepth > MaxDepth) {
1198 unsigned Extra = FDepth - MaxDepth;
1199 LLVM_DEBUG(dbgs() << "FBB data adds " << Extra << " cycles.\n");
1200 if (Extra > FBlock.Extra)
1201 FBlock = {.Extra: Extra, .Depth: FDepth};
1202 if (Extra > CritLimit) {
1203 LLVM_DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n');
1204 ShouldConvert = false;
1205 }
1206 }
1207 }
1208
1209 // Organize by "short" and "long" legs, since the diagnostics get confusing
1210 // when referring to the "true" and "false" sides of the branch, given that
1211 // those don't always correlate with what the user wrote in source-terms.
1212 const CriticalPathInfo Short = TBlock.Extra > FBlock.Extra ? FBlock : TBlock;
1213 const CriticalPathInfo Long = TBlock.Extra > FBlock.Extra ? TBlock : FBlock;
1214
1215 if (ShouldConvert) {
1216 MORE.emit(RemarkBuilder: [&]() {
1217 MachineOptimizationRemark R(DEBUG_TYPE, "IfConversion",
1218 MBB.back().getDebugLoc(), &MBB);
1219 R << "performing if-conversion on branch: the condition adds "
1220 << Cycles{.Key: "CondCycles", .Value: Cond.Extra} << " to the critical path";
1221 if (Short.Extra > 0)
1222 R << ", and the short leg adds another "
1223 << Cycles{.Key: "ShortCycles", .Value: Short.Extra};
1224 if (Long.Extra > 0)
1225 R << ", and the long leg adds another "
1226 << Cycles{.Key: "LongCycles", .Value: Long.Extra};
1227 R << ", each staying under the threshold of "
1228 << Cycles{.Key: "CritLimit", .Value: CritLimit} << ".";
1229 return R;
1230 });
1231 } else {
1232 MORE.emit(RemarkBuilder: [&]() {
1233 MachineOptimizationRemarkMissed R(DEBUG_TYPE, "IfConversion",
1234 MBB.back().getDebugLoc(), &MBB);
1235 R << "did not if-convert branch: the condition would add "
1236 << Cycles{.Key: "CondCycles", .Value: Cond.Extra} << " to the critical path";
1237 if (Cond.Extra > CritLimit)
1238 R << " exceeding the limit of " << Cycles{.Key: "CritLimit", .Value: CritLimit};
1239 if (Short.Extra > 0) {
1240 R << ", and the short leg would add another "
1241 << Cycles{.Key: "ShortCycles", .Value: Short.Extra};
1242 if (Short.Extra > CritLimit)
1243 R << " exceeding the limit of " << Cycles{.Key: "CritLimit", .Value: CritLimit};
1244 }
1245 if (Long.Extra > 0) {
1246 R << ", and the long leg would add another "
1247 << Cycles{.Key: "LongCycles", .Value: Long.Extra};
1248 if (Long.Extra > CritLimit)
1249 R << " exceeding the limit of " << Cycles{.Key: "CritLimit", .Value: CritLimit};
1250 }
1251 R << ".";
1252 return R;
1253 });
1254 }
1255
1256 return ShouldConvert;
1257}
1258
1259/// Attempt repeated if-conversion on MBB, return true if successful.
1260///
1261bool EarlyIfConverter::tryConvertIf(MachineBasicBlock *MBB) {
1262 bool Changed = false;
1263 while (IfConv.canConvertIf(MBB) && shouldConvertIf()) {
1264 // If-convert MBB and update analyses.
1265 invalidateTraces();
1266 SmallVector<MachineBasicBlock *, 4> RemoveBlocks;
1267 IfConv.convertIf(RemoveBlocks);
1268 Changed = true;
1269 updateDomTree(DomTree, IfConv, Removed: RemoveBlocks);
1270 for (MachineBasicBlock *MBB : RemoveBlocks)
1271 MBB->eraseFromParent();
1272 updateLoops(Loops, Removed: RemoveBlocks);
1273 }
1274 return Changed;
1275}
1276
1277bool EarlyIfConverter::run(MachineFunction &MF) {
1278 LLVM_DEBUG(dbgs() << "********** EARLY IF-CONVERSION **********\n"
1279 << "********** Function: " << MF.getName() << '\n');
1280
1281 // Only run if conversion if the target wants it.
1282 const TargetSubtargetInfo &STI = MF.getSubtarget();
1283 if (!STI.enableEarlyIfConversion())
1284 return false;
1285
1286 TII = STI.getInstrInfo();
1287 TRI = STI.getRegisterInfo();
1288 SchedModel = STI.getSchedModel();
1289 MRI = &MF.getRegInfo();
1290 MinInstr = nullptr;
1291
1292 bool Changed = false;
1293 IfConv.init(MF);
1294
1295 // Visit blocks in dominator tree post-order. The post-order enables nested
1296 // if-conversion in a single pass. The tryConvertIf() function may erase
1297 // blocks, but only blocks dominated by the head block. This makes it safe to
1298 // update the dominator tree while the post-order iterator is still active.
1299 for (auto *DomNode : post_order(G: DomTree))
1300 if (tryConvertIf(MBB: DomNode->getBlock()))
1301 Changed = true;
1302
1303 return Changed;
1304}
1305
1306PreservedAnalyses
1307EarlyIfConverterPass::run(MachineFunction &MF,
1308 MachineFunctionAnalysisManager &MFAM) {
1309 MachineDominatorTree &MDT = MFAM.getResult<MachineDominatorTreeAnalysis>(IR&: MF);
1310 MachineLoopInfo &LI = MFAM.getResult<MachineLoopAnalysis>(IR&: MF);
1311 MachineTraceMetrics &MTM = MFAM.getResult<MachineTraceMetricsAnalysis>(IR&: MF);
1312 MachineBranchProbabilityInfo *MBPI = nullptr;
1313 if (EnableDataDependentBranchAnalysis)
1314 MBPI = &MFAM.getResult<MachineBranchProbabilityAnalysis>(IR&: MF);
1315
1316 EarlyIfConverter Impl(MDT, LI, MTM, MBPI);
1317 bool Changed = Impl.run(MF);
1318 if (!Changed)
1319 return PreservedAnalyses::all();
1320
1321 auto PA = getMachineFunctionPassPreservedAnalyses();
1322 PA.preserve<MachineDominatorTreeAnalysis>();
1323 PA.preserve<MachineLoopAnalysis>();
1324 PA.preserve<MachineTraceMetricsAnalysis>();
1325 return PA;
1326}
1327
1328bool EarlyIfConverterLegacy::runOnMachineFunction(MachineFunction &MF) {
1329 if (skipFunction(F: MF.getFunction()))
1330 return false;
1331
1332 MachineDominatorTree &MDT =
1333 getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
1334 MachineLoopInfo &LI = getAnalysis<MachineLoopInfoWrapperPass>().getLI();
1335 MachineTraceMetrics &MTM =
1336 getAnalysis<MachineTraceMetricsWrapperPass>().getMTM();
1337 MachineBranchProbabilityInfo *MBPI = nullptr;
1338 if (EnableDataDependentBranchAnalysis)
1339 MBPI = &getAnalysis<MachineBranchProbabilityInfoWrapperPass>().getMBPI();
1340
1341 return EarlyIfConverter(MDT, LI, MTM, MBPI).run(MF);
1342}
1343
1344//===----------------------------------------------------------------------===//
1345// EarlyIfPredicator Pass
1346//===----------------------------------------------------------------------===//
1347
1348namespace {
1349class EarlyIfPredicator : public MachineFunctionPass {
1350 const TargetInstrInfo *TII = nullptr;
1351 const TargetRegisterInfo *TRI = nullptr;
1352 TargetSchedModel SchedModel;
1353 MachineRegisterInfo *MRI = nullptr;
1354 MachineDominatorTree *DomTree = nullptr;
1355 MachineBranchProbabilityInfo *MBPI = nullptr;
1356 MachineLoopInfo *Loops = nullptr;
1357 SSAIfConv IfConv;
1358
1359public:
1360 static char ID;
1361 EarlyIfPredicator() : MachineFunctionPass(ID) {}
1362 void getAnalysisUsage(AnalysisUsage &AU) const override;
1363 bool runOnMachineFunction(MachineFunction &MF) override;
1364 StringRef getPassName() const override { return "Early If-predicator"; }
1365
1366protected:
1367 bool tryConvertIf(MachineBasicBlock *);
1368 bool shouldConvertIf();
1369};
1370} // end anonymous namespace
1371
1372#undef DEBUG_TYPE
1373#define DEBUG_TYPE "early-if-predicator"
1374
1375char EarlyIfPredicator::ID = 0;
1376char &llvm::EarlyIfPredicatorID = EarlyIfPredicator::ID;
1377
1378INITIALIZE_PASS_BEGIN(EarlyIfPredicator, DEBUG_TYPE, "Early If Predicator",
1379 false, false)
1380INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
1381INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfoWrapperPass)
1382INITIALIZE_PASS_END(EarlyIfPredicator, DEBUG_TYPE, "Early If Predicator", false,
1383 false)
1384
1385void EarlyIfPredicator::getAnalysisUsage(AnalysisUsage &AU) const {
1386 AU.addRequired<MachineBranchProbabilityInfoWrapperPass>();
1387 AU.addRequired<MachineDominatorTreeWrapperPass>();
1388 AU.addPreserved<MachineDominatorTreeWrapperPass>();
1389 AU.addRequired<MachineLoopInfoWrapperPass>();
1390 AU.addPreserved<MachineLoopInfoWrapperPass>();
1391 MachineFunctionPass::getAnalysisUsage(AU);
1392}
1393
1394/// Apply the target heuristic to decide if the transformation is profitable.
1395bool EarlyIfPredicator::shouldConvertIf() {
1396 auto TrueProbability = MBPI->getEdgeProbability(Src: IfConv.Head, Dst: IfConv.TBB);
1397 if (IfConv.isTriangle()) {
1398 MachineBasicBlock &IfBlock =
1399 (IfConv.TBB == IfConv.Tail) ? *IfConv.FBB : *IfConv.TBB;
1400
1401 unsigned ExtraPredCost = 0;
1402 unsigned Cycles = 0;
1403 for (MachineInstr &I : IfBlock) {
1404 unsigned NumCycles = SchedModel.computeInstrLatency(MI: &I, UseDefaultDefLatency: false);
1405 if (NumCycles > 1)
1406 Cycles += NumCycles - 1;
1407 ExtraPredCost += TII->getPredicationCost(MI: I);
1408 }
1409
1410 return TII->isProfitableToIfCvt(MBB&: IfBlock, NumCycles: Cycles, ExtraPredCycles: ExtraPredCost,
1411 Probability: TrueProbability);
1412 }
1413 unsigned TExtra = 0;
1414 unsigned FExtra = 0;
1415 unsigned TCycle = 0;
1416 unsigned FCycle = 0;
1417 for (MachineInstr &I : *IfConv.TBB) {
1418 unsigned NumCycles = SchedModel.computeInstrLatency(MI: &I, UseDefaultDefLatency: false);
1419 if (NumCycles > 1)
1420 TCycle += NumCycles - 1;
1421 TExtra += TII->getPredicationCost(MI: I);
1422 }
1423 for (MachineInstr &I : *IfConv.FBB) {
1424 unsigned NumCycles = SchedModel.computeInstrLatency(MI: &I, UseDefaultDefLatency: false);
1425 if (NumCycles > 1)
1426 FCycle += NumCycles - 1;
1427 FExtra += TII->getPredicationCost(MI: I);
1428 }
1429 return TII->isProfitableToIfCvt(TMBB&: *IfConv.TBB, NumTCycles: TCycle, ExtraTCycles: TExtra, FMBB&: *IfConv.FBB,
1430 NumFCycles: FCycle, ExtraFCycles: FExtra, Probability: TrueProbability);
1431}
1432
1433/// Attempt repeated if-conversion on MBB, return true if successful.
1434///
1435bool EarlyIfPredicator::tryConvertIf(MachineBasicBlock *MBB) {
1436 bool Changed = false;
1437 while (IfConv.canConvertIf(MBB, /*Predicate*/ true) && shouldConvertIf()) {
1438 // If-convert MBB and update analyses.
1439 SmallVector<MachineBasicBlock *, 4> RemoveBlocks;
1440 IfConv.convertIf(RemoveBlocks, /*Predicate*/ true);
1441 Changed = true;
1442 updateDomTree(DomTree, IfConv, Removed: RemoveBlocks);
1443 for (MachineBasicBlock *MBB : RemoveBlocks)
1444 MBB->eraseFromParent();
1445 updateLoops(Loops, Removed: RemoveBlocks);
1446 }
1447 return Changed;
1448}
1449
1450bool EarlyIfPredicator::runOnMachineFunction(MachineFunction &MF) {
1451 LLVM_DEBUG(dbgs() << "********** EARLY IF-PREDICATOR **********\n"
1452 << "********** Function: " << MF.getName() << '\n');
1453 if (skipFunction(F: MF.getFunction()))
1454 return false;
1455
1456 const TargetSubtargetInfo &STI = MF.getSubtarget();
1457 TII = STI.getInstrInfo();
1458 TRI = STI.getRegisterInfo();
1459 MRI = &MF.getRegInfo();
1460 SchedModel.init(TSInfo: &STI);
1461 DomTree = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
1462 Loops = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
1463 MBPI = &getAnalysis<MachineBranchProbabilityInfoWrapperPass>().getMBPI();
1464
1465 bool Changed = false;
1466 IfConv.init(MF);
1467
1468 // Visit blocks in dominator tree post-order. The post-order enables nested
1469 // if-conversion in a single pass. The tryConvertIf() function may erase
1470 // blocks, but only blocks dominated by the head block. This makes it safe to
1471 // update the dominator tree while the post-order iterator is still active.
1472 for (auto *DomNode : post_order(G: DomTree))
1473 if (tryConvertIf(MBB: DomNode->getBlock()))
1474 Changed = true;
1475
1476 return Changed;
1477}
1478