1//===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
10// instructions after register allocation.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/ExpandPostRAPseudos.h"
15#include "llvm/CodeGen/MachineDominators.h"
16#include "llvm/CodeGen/MachineFunctionPass.h"
17#include "llvm/CodeGen/MachineInstr.h"
18#include "llvm/CodeGen/MachineLoopInfo.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/CodeGen/TargetInstrInfo.h"
21#include "llvm/CodeGen/TargetRegisterInfo.h"
22#include "llvm/CodeGen/TargetSubtargetInfo.h"
23#include "llvm/InitializePasses.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/raw_ostream.h"
26
27using namespace llvm;
28
29#define DEBUG_TYPE "postrapseudos"
30
31namespace {
32struct ExpandPostRA {
33 bool run(MachineFunction &);
34
35private:
36 const TargetRegisterInfo *TRI = nullptr;
37 const TargetInstrInfo *TII = nullptr;
38
39 bool LowerSubregToReg(MachineInstr *MI);
40};
41
42struct ExpandPostRALegacy : public MachineFunctionPass {
43 static char ID;
44 ExpandPostRALegacy() : MachineFunctionPass(ID) {}
45
46 void getAnalysisUsage(AnalysisUsage &AU) const override {
47 AU.setPreservesCFG();
48 AU.addPreservedID(ID&: MachineLoopInfoID);
49 AU.addPreservedID(ID&: MachineDominatorsID);
50 MachineFunctionPass::getAnalysisUsage(AU);
51 }
52
53 /// runOnMachineFunction - pass entry point
54 bool runOnMachineFunction(MachineFunction &) override;
55};
56} // end anonymous namespace
57
58PreservedAnalyses
59ExpandPostRAPseudosPass::run(MachineFunction &MF,
60 MachineFunctionAnalysisManager &MFAM) {
61 if (!ExpandPostRA().run(MF))
62 return PreservedAnalyses::all();
63
64 return getMachineFunctionPassPreservedAnalyses()
65 .preserveSet<CFGAnalyses>()
66 .preserve<MachineLoopAnalysis>()
67 .preserve<MachineDominatorTreeAnalysis>();
68}
69
70char ExpandPostRALegacy::ID = 0;
71char &llvm::ExpandPostRAPseudosID = ExpandPostRALegacy::ID;
72
73INITIALIZE_PASS(ExpandPostRALegacy, DEBUG_TYPE,
74 "Post-RA pseudo instruction expansion pass", false, false)
75
76bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
77 MachineBasicBlock *MBB = MI->getParent();
78 assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
79 MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
80 MI->getOperand(2).isImm() && "Invalid subreg_to_reg");
81
82 Register DstReg = MI->getOperand(i: 0).getReg();
83 Register InsReg = MI->getOperand(i: 1).getReg();
84 assert(!MI->getOperand(1).getSubReg() && "SubIdx on physreg?");
85 unsigned SubIdx = MI->getOperand(i: 2).getImm();
86
87 assert(SubIdx != 0 && "Invalid index for insert_subreg");
88 Register DstSubReg = TRI->getSubReg(Reg: DstReg, Idx: SubIdx);
89
90 assert(DstReg.isPhysical() &&
91 "Insert destination must be in a physical register");
92 assert(InsReg.isPhysical() &&
93 "Inserted value must be in a physical register");
94
95 LLVM_DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
96
97 if (MI->allDefsAreDead() || DstSubReg == InsReg) {
98 // No need to insert an identity copy instruction.
99 // Watch out for case like this:
100 // %rax = SUBREG_TO_REG killed %eax, 3
101 // We must leave %rax live.
102 MI->setDesc(TII->get(Opcode: TargetOpcode::KILL));
103 MI->removeOperand(OpNo: 2); // SubIdx
104 LLVM_DEBUG(dbgs() << "subreg: replaced by: " << *MI);
105 return true;
106 }
107
108 TII->copyPhysReg(MBB&: *MBB, MI, DL: MI->getDebugLoc(), DestReg: DstSubReg, SrcReg: InsReg,
109 KillSrc: MI->getOperand(i: 1).isKill());
110
111 // Implicitly define DstReg for subsequent uses.
112 MachineBasicBlock::iterator CopyMI = MI;
113 --CopyMI;
114 CopyMI->addRegisterDefined(Reg: DstReg);
115 LLVM_DEBUG(dbgs() << "subreg: " << *CopyMI);
116
117 MBB->erase(I: MI);
118 return true;
119}
120
121bool ExpandPostRALegacy::runOnMachineFunction(MachineFunction &MF) {
122 return ExpandPostRA().run(MF);
123}
124
125/// runOnMachineFunction - Reduce subregister inserts and extracts to register
126/// copies.
127///
128bool ExpandPostRA::run(MachineFunction &MF) {
129 LLVM_DEBUG(dbgs() << "Machine Function\n"
130 << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
131 << "********** Function: " << MF.getName() << '\n');
132 TRI = MF.getSubtarget().getRegisterInfo();
133 TII = MF.getSubtarget().getInstrInfo();
134
135 bool MadeChange = false;
136
137 for (MachineBasicBlock &MBB : MF) {
138 for (MachineInstr &MI : llvm::make_early_inc_range(Range&: MBB)) {
139 // Only expand pseudos.
140 if (!MI.isPseudo())
141 continue;
142
143 // Give targets a chance to expand even standard pseudos.
144 if (TII->expandPostRAPseudo(MI)) {
145 MadeChange = true;
146 continue;
147 }
148
149 // Expand standard pseudos.
150 switch (MI.getOpcode()) {
151 case TargetOpcode::SUBREG_TO_REG:
152 MadeChange |= LowerSubregToReg(MI: &MI);
153 break;
154 case TargetOpcode::COPY:
155 TII->lowerCopy(MI: &MI, TRI);
156 MadeChange = true;
157 break;
158 case TargetOpcode::DBG_VALUE:
159 continue;
160 case TargetOpcode::INSERT_SUBREG:
161 case TargetOpcode::EXTRACT_SUBREG:
162 llvm_unreachable("Sub-register pseudos should have been eliminated.");
163 }
164 }
165 }
166
167 return MadeChange;
168}
169