1//===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
10// instructions after register allocation.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/ExpandPostRAPseudos.h"
15#include "llvm/CodeGen/MachineDominators.h"
16#include "llvm/CodeGen/MachineFunctionPass.h"
17#include "llvm/CodeGen/MachineInstr.h"
18#include "llvm/CodeGen/MachineLoopInfo.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/CodeGen/TargetInstrInfo.h"
21#include "llvm/CodeGen/TargetRegisterInfo.h"
22#include "llvm/CodeGen/TargetSubtargetInfo.h"
23#include "llvm/InitializePasses.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/raw_ostream.h"
26
27using namespace llvm;
28
29#define DEBUG_TYPE "postrapseudos"
30
31namespace {
32struct ExpandPostRA {
33 bool run(MachineFunction &);
34
35private:
36 const TargetRegisterInfo *TRI = nullptr;
37 const TargetInstrInfo *TII = nullptr;
38
39 bool LowerSubregToReg(MachineInstr *MI);
40};
41
42struct ExpandPostRALegacy : public MachineFunctionPass {
43 static char ID;
44 ExpandPostRALegacy() : MachineFunctionPass(ID) {}
45
46 void getAnalysisUsage(AnalysisUsage &AU) const override {
47 AU.setPreservesCFG();
48 AU.addPreservedID(ID&: MachineLoopInfoID);
49 AU.addPreservedID(ID&: MachineDominatorsID);
50 MachineFunctionPass::getAnalysisUsage(AU);
51 }
52
53 /// runOnMachineFunction - pass entry point
54 bool runOnMachineFunction(MachineFunction &) override;
55};
56} // end anonymous namespace
57
58PreservedAnalyses
59ExpandPostRAPseudosPass::run(MachineFunction &MF,
60 MachineFunctionAnalysisManager &MFAM) {
61 if (!ExpandPostRA().run(MF))
62 return PreservedAnalyses::all();
63
64 return getMachineFunctionPassPreservedAnalyses()
65 .preserveSet<CFGAnalyses>()
66 .preserve<MachineLoopAnalysis>()
67 .preserve<MachineDominatorTreeAnalysis>();
68}
69
70char ExpandPostRALegacy::ID = 0;
71char &llvm::ExpandPostRAPseudosID = ExpandPostRALegacy::ID;
72
73INITIALIZE_PASS(ExpandPostRALegacy, DEBUG_TYPE,
74 "Post-RA pseudo instruction expansion pass", false, false)
75
76bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
77 MachineBasicBlock *MBB = MI->getParent();
78 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
79 MI->getOperand(1).isImm() &&
80 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
81 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
82
83 Register DstReg = MI->getOperand(i: 0).getReg();
84 Register InsReg = MI->getOperand(i: 2).getReg();
85 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
86 unsigned SubIdx = MI->getOperand(i: 3).getImm();
87
88 assert(SubIdx != 0 && "Invalid index for insert_subreg");
89 Register DstSubReg = TRI->getSubReg(Reg: DstReg, Idx: SubIdx);
90
91 assert(DstReg.isPhysical() &&
92 "Insert destination must be in a physical register");
93 assert(InsReg.isPhysical() &&
94 "Inserted value must be in a physical register");
95
96 LLVM_DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
97
98 if (MI->allDefsAreDead()) {
99 MI->setDesc(TII->get(Opcode: TargetOpcode::KILL));
100 MI->removeOperand(OpNo: 3); // SubIdx
101 MI->removeOperand(OpNo: 1); // Imm
102 LLVM_DEBUG(dbgs() << "subreg: replaced by: " << *MI);
103 return true;
104 }
105
106 if (DstSubReg == InsReg) {
107 // No need to insert an identity copy instruction.
108 // Watch out for case like this:
109 // %rax = SUBREG_TO_REG 0, killed %eax, 3
110 // We must leave %rax live.
111 if (DstReg != InsReg) {
112 MI->setDesc(TII->get(Opcode: TargetOpcode::KILL));
113 MI->removeOperand(OpNo: 3); // SubIdx
114 MI->removeOperand(OpNo: 1); // Imm
115 LLVM_DEBUG(dbgs() << "subreg: replace by: " << *MI);
116 return true;
117 }
118 LLVM_DEBUG(dbgs() << "subreg: eliminated!");
119 } else {
120 TII->copyPhysReg(MBB&: *MBB, MI, DL: MI->getDebugLoc(), DestReg: DstSubReg, SrcReg: InsReg,
121 KillSrc: MI->getOperand(i: 2).isKill());
122
123 // Implicitly define DstReg for subsequent uses.
124 MachineBasicBlock::iterator CopyMI = MI;
125 --CopyMI;
126 CopyMI->addRegisterDefined(Reg: DstReg);
127 LLVM_DEBUG(dbgs() << "subreg: " << *CopyMI);
128 }
129
130 LLVM_DEBUG(dbgs() << '\n');
131 MBB->erase(I: MI);
132 return true;
133}
134
135bool ExpandPostRALegacy::runOnMachineFunction(MachineFunction &MF) {
136 return ExpandPostRA().run(MF);
137}
138
139/// runOnMachineFunction - Reduce subregister inserts and extracts to register
140/// copies.
141///
142bool ExpandPostRA::run(MachineFunction &MF) {
143 LLVM_DEBUG(dbgs() << "Machine Function\n"
144 << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
145 << "********** Function: " << MF.getName() << '\n');
146 TRI = MF.getSubtarget().getRegisterInfo();
147 TII = MF.getSubtarget().getInstrInfo();
148
149 bool MadeChange = false;
150
151 for (MachineBasicBlock &MBB : MF) {
152 for (MachineInstr &MI : llvm::make_early_inc_range(Range&: MBB)) {
153 // Only expand pseudos.
154 if (!MI.isPseudo())
155 continue;
156
157 // Give targets a chance to expand even standard pseudos.
158 if (TII->expandPostRAPseudo(MI)) {
159 MadeChange = true;
160 continue;
161 }
162
163 // Expand standard pseudos.
164 switch (MI.getOpcode()) {
165 case TargetOpcode::SUBREG_TO_REG:
166 MadeChange |= LowerSubregToReg(MI: &MI);
167 break;
168 case TargetOpcode::COPY:
169 TII->lowerCopy(MI: &MI, TRI);
170 MadeChange = true;
171 break;
172 case TargetOpcode::DBG_VALUE:
173 continue;
174 case TargetOpcode::INSERT_SUBREG:
175 case TargetOpcode::EXTRACT_SUBREG:
176 llvm_unreachable("Sub-register pseudos should have been eliminated.");
177 }
178 }
179 }
180
181 return MadeChange;
182}
183