1//===-- lib/CodeGen/GlobalISel/CallLowering.cpp - Call lowering -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements some simple delegations needed for call lowering.
11///
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/GlobalISel/CallLowering.h"
15#include "llvm/CodeGen/Analysis.h"
16#include "llvm/CodeGen/CallingConvLower.h"
17#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
18#include "llvm/CodeGen/GlobalISel/Utils.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineOperand.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/TargetLowering.h"
23#include "llvm/IR/DataLayout.h"
24#include "llvm/IR/LLVMContext.h"
25#include "llvm/IR/Module.h"
26#include "llvm/Target/TargetMachine.h"
27
28#define DEBUG_TYPE "call-lowering"
29
30using namespace llvm;
31
32void CallLowering::anchor() {}
33
34/// Helper function which updates \p Flags when \p AttrFn returns true.
35static void
36addFlagsUsingAttrFn(ISD::ArgFlagsTy &Flags,
37 const std::function<bool(Attribute::AttrKind)> &AttrFn) {
38 // TODO: There are missing flags. Add them here.
39 if (AttrFn(Attribute::SExt))
40 Flags.setSExt();
41 if (AttrFn(Attribute::ZExt))
42 Flags.setZExt();
43 if (AttrFn(Attribute::InReg))
44 Flags.setInReg();
45 if (AttrFn(Attribute::StructRet))
46 Flags.setSRet();
47 if (AttrFn(Attribute::Nest))
48 Flags.setNest();
49 if (AttrFn(Attribute::ByVal))
50 Flags.setByVal();
51 if (AttrFn(Attribute::ByRef))
52 Flags.setByRef();
53 if (AttrFn(Attribute::Preallocated))
54 Flags.setPreallocated();
55 if (AttrFn(Attribute::InAlloca))
56 Flags.setInAlloca();
57 if (AttrFn(Attribute::Returned))
58 Flags.setReturned();
59 if (AttrFn(Attribute::SwiftSelf))
60 Flags.setSwiftSelf();
61 if (AttrFn(Attribute::SwiftAsync))
62 Flags.setSwiftAsync();
63 if (AttrFn(Attribute::SwiftError))
64 Flags.setSwiftError();
65}
66
67ISD::ArgFlagsTy CallLowering::getAttributesForArgIdx(const CallBase &Call,
68 unsigned ArgIdx) const {
69 ISD::ArgFlagsTy Flags;
70 addFlagsUsingAttrFn(Flags, AttrFn: [&Call, &ArgIdx](Attribute::AttrKind Attr) {
71 return Call.paramHasAttr(ArgNo: ArgIdx, Kind: Attr);
72 });
73 return Flags;
74}
75
76ISD::ArgFlagsTy
77CallLowering::getAttributesForReturn(const CallBase &Call) const {
78 ISD::ArgFlagsTy Flags;
79 addFlagsUsingAttrFn(Flags, AttrFn: [&Call](Attribute::AttrKind Attr) {
80 return Call.hasRetAttr(Kind: Attr);
81 });
82 return Flags;
83}
84
85void CallLowering::addArgFlagsFromAttributes(ISD::ArgFlagsTy &Flags,
86 const AttributeList &Attrs,
87 unsigned OpIdx) const {
88 addFlagsUsingAttrFn(Flags, AttrFn: [&Attrs, &OpIdx](Attribute::AttrKind Attr) {
89 return Attrs.hasAttributeAtIndex(Index: OpIdx, Kind: Attr);
90 });
91}
92
93bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB,
94 ArrayRef<Register> ResRegs,
95 ArrayRef<ArrayRef<Register>> ArgRegs,
96 Register SwiftErrorVReg,
97 std::optional<PtrAuthInfo> PAI,
98 Register ConvergenceCtrlToken,
99 std::function<Register()> GetCalleeReg) const {
100 CallLoweringInfo Info;
101 const DataLayout &DL = MIRBuilder.getDataLayout();
102 MachineFunction &MF = MIRBuilder.getMF();
103 MachineRegisterInfo &MRI = MF.getRegInfo();
104 bool CanBeTailCalled = CB.isTailCall() &&
105 isInTailCallPosition(Call: CB, TM: MF.getTarget()) &&
106 (MF.getFunction()
107 .getFnAttribute(Kind: "disable-tail-calls")
108 .getValueAsString() != "true");
109
110 CallingConv::ID CallConv = CB.getCallingConv();
111 Type *RetTy = CB.getType();
112 bool IsVarArg = CB.getFunctionType()->isVarArg();
113
114 SmallVector<BaseArgInfo, 4> SplitArgs;
115 getReturnInfo(CallConv, RetTy, Attrs: CB.getAttributes(), Outs&: SplitArgs, DL);
116 Info.CanLowerReturn = canLowerReturn(MF, CallConv, Outs&: SplitArgs, IsVarArg);
117
118 Info.IsConvergent = CB.isConvergent();
119
120 if (!Info.CanLowerReturn) {
121 // Callee requires sret demotion.
122 insertSRetOutgoingArgument(MIRBuilder, CB, Info);
123
124 // The sret demotion isn't compatible with tail-calls, since the sret
125 // argument points into the caller's stack frame.
126 CanBeTailCalled = false;
127 }
128
129 // First step is to marshall all the function's parameters into the correct
130 // physregs and memory locations. Gather the sequence of argument types that
131 // we'll pass to the assigner function.
132 unsigned i = 0;
133 unsigned NumFixedArgs = CB.getFunctionType()->getNumParams();
134 for (const auto &Arg : CB.args()) {
135 ArgInfo OrigArg{ArgRegs[i], *Arg.get(), i, getAttributesForArgIdx(Call: CB, ArgIdx: i)};
136 setArgFlags(Arg&: OrigArg, OpIdx: i + AttributeList::FirstArgIndex, DL, FuncInfo: CB);
137 if (i >= NumFixedArgs)
138 OrigArg.Flags[0].setVarArg();
139
140 // If we have an explicit sret argument that is an Instruction, (i.e., it
141 // might point to function-local memory), we can't meaningfully tail-call.
142 if (OrigArg.Flags[0].isSRet() && isa<Instruction>(Val: &Arg))
143 CanBeTailCalled = false;
144
145 Info.OrigArgs.push_back(Elt: OrigArg);
146 ++i;
147 }
148
149 // Try looking through a bitcast from one function type to another.
150 // Commonly happens with calls to objc_msgSend().
151 const Value *CalleeV = CB.getCalledOperand()->stripPointerCasts();
152
153 // If IRTranslator chose to drop the ptrauth info, we can turn this into
154 // a direct call.
155 if (!PAI && CB.countOperandBundlesOfType(ID: LLVMContext::OB_ptrauth)) {
156 CalleeV = cast<ConstantPtrAuth>(Val: CalleeV)->getPointer();
157 assert(isa<Function>(CalleeV));
158 }
159
160 if (const Function *F = dyn_cast<Function>(Val: CalleeV)) {
161 if (F->hasFnAttribute(Kind: Attribute::NonLazyBind)) {
162 LLT Ty = getLLTForType(Ty&: *F->getType(), DL);
163 Register Reg = MIRBuilder.buildGlobalValue(Res: Ty, GV: F).getReg(Idx: 0);
164 Info.Callee = MachineOperand::CreateReg(Reg, isDef: false);
165 } else {
166 Info.Callee = MachineOperand::CreateGA(GV: F, Offset: 0);
167 }
168 } else if (isa<GlobalIFunc>(Val: CalleeV) || isa<GlobalAlias>(Val: CalleeV)) {
169 // IR IFuncs and Aliases can't be forward declared (only defined), so the
170 // callee must be in the same TU and therefore we can direct-call it without
171 // worrying about it being out of range.
172 Info.Callee = MachineOperand::CreateGA(GV: cast<GlobalValue>(Val: CalleeV), Offset: 0);
173 } else
174 Info.Callee = MachineOperand::CreateReg(Reg: GetCalleeReg(), isDef: false);
175
176 Register ReturnHintAlignReg;
177 Align ReturnHintAlign;
178
179 Info.OrigRet = ArgInfo{ResRegs, RetTy, 0, getAttributesForReturn(Call: CB)};
180
181 if (!Info.OrigRet.Ty->isVoidTy()) {
182 setArgFlags(Arg&: Info.OrigRet, OpIdx: AttributeList::ReturnIndex, DL, FuncInfo: CB);
183
184 if (MaybeAlign Alignment = CB.getRetAlign()) {
185 if (*Alignment > Align(1)) {
186 ReturnHintAlignReg = MRI.cloneVirtualRegister(VReg: ResRegs[0]);
187 Info.OrigRet.Regs[0] = ReturnHintAlignReg;
188 ReturnHintAlign = *Alignment;
189 }
190 }
191 }
192
193 auto Bundle = CB.getOperandBundle(ID: LLVMContext::OB_kcfi);
194 if (Bundle && CB.isIndirectCall()) {
195 Info.CFIType = cast<ConstantInt>(Val: Bundle->Inputs[0]);
196 assert(Info.CFIType->getType()->isIntegerTy(32) && "Invalid CFI type");
197 }
198
199 if (auto Bundle = CB.getOperandBundle(ID: LLVMContext::OB_deactivation_symbol)) {
200 Info.DeactivationSymbol = cast<GlobalValue>(Val: Bundle->Inputs[0]);
201 }
202
203 Info.CB = &CB;
204 Info.KnownCallees = CB.getMetadata(KindID: LLVMContext::MD_callees);
205 Info.CallConv = CallConv;
206 Info.SwiftErrorVReg = SwiftErrorVReg;
207 Info.PAI = PAI;
208 Info.ConvergenceCtrlToken = ConvergenceCtrlToken;
209 Info.IsMustTailCall = CB.isMustTailCall();
210 Info.IsTailCall = CanBeTailCalled;
211 Info.IsVarArg = IsVarArg;
212 if (!lowerCall(MIRBuilder, Info))
213 return false;
214
215 if (ReturnHintAlignReg && !Info.LoweredTailCall) {
216 MIRBuilder.buildAssertAlign(Res: ResRegs[0], Op: ReturnHintAlignReg,
217 AlignVal: ReturnHintAlign);
218 }
219
220 return true;
221}
222
223template <typename FuncInfoTy>
224void CallLowering::setArgFlags(CallLowering::ArgInfo &Arg, unsigned OpIdx,
225 const DataLayout &DL,
226 const FuncInfoTy &FuncInfo) const {
227 auto &Flags = Arg.Flags[0];
228 const AttributeList &Attrs = FuncInfo.getAttributes();
229 addArgFlagsFromAttributes(Flags, Attrs, OpIdx);
230
231 PointerType *PtrTy = dyn_cast<PointerType>(Val: Arg.Ty->getScalarType());
232 if (PtrTy) {
233 Flags.setPointer();
234 Flags.setPointerAddrSpace(PtrTy->getPointerAddressSpace());
235 }
236
237 Align MemAlign = DL.getABITypeAlign(Ty: Arg.Ty);
238 if (Flags.isByVal() || Flags.isInAlloca() || Flags.isPreallocated() ||
239 Flags.isByRef()) {
240 assert(OpIdx >= AttributeList::FirstArgIndex);
241 unsigned ParamIdx = OpIdx - AttributeList::FirstArgIndex;
242
243 Type *ElementTy = FuncInfo.getParamByValType(ParamIdx);
244 if (!ElementTy)
245 ElementTy = FuncInfo.getParamByRefType(ParamIdx);
246 if (!ElementTy)
247 ElementTy = FuncInfo.getParamInAllocaType(ParamIdx);
248 if (!ElementTy)
249 ElementTy = FuncInfo.getParamPreallocatedType(ParamIdx);
250
251 assert(ElementTy && "Must have byval, inalloca or preallocated type");
252
253 uint64_t MemSize = DL.getTypeAllocSize(Ty: ElementTy);
254 if (Flags.isByRef())
255 Flags.setByRefSize(MemSize);
256 else
257 Flags.setByValSize(MemSize);
258
259 // For ByVal, alignment should be passed from FE. BE will guess if
260 // this info is not there but there are cases it cannot get right.
261 if (auto ParamAlign = FuncInfo.getParamStackAlign(ParamIdx))
262 MemAlign = *ParamAlign;
263 else if ((ParamAlign = FuncInfo.getParamAlign(ParamIdx)))
264 MemAlign = *ParamAlign;
265 else
266 MemAlign = getTLI()->getByValTypeAlignment(Ty: ElementTy, DL);
267 } else if (OpIdx >= AttributeList::FirstArgIndex) {
268 if (auto ParamAlign =
269 FuncInfo.getParamStackAlign(OpIdx - AttributeList::FirstArgIndex))
270 MemAlign = *ParamAlign;
271 }
272 Flags.setMemAlign(MemAlign);
273 Flags.setOrigAlign(DL.getABITypeAlign(Ty: Arg.Ty));
274
275 // Don't try to use the returned attribute if the argument is marked as
276 // swiftself, since it won't be passed in x0.
277 if (Flags.isSwiftSelf())
278 Flags.setReturned(false);
279}
280
281template void
282CallLowering::setArgFlags<Function>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
283 const DataLayout &DL,
284 const Function &FuncInfo) const;
285
286template void
287CallLowering::setArgFlags<CallBase>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
288 const DataLayout &DL,
289 const CallBase &FuncInfo) const;
290
291void CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
292 SmallVectorImpl<ArgInfo> &SplitArgs,
293 const DataLayout &DL,
294 CallingConv::ID CallConv,
295 SmallVectorImpl<TypeSize> *Offsets) const {
296 SmallVector<Type *, 4> SplitTys;
297 ComputeValueTypes(DL, Ty: OrigArg.Ty, Types&: SplitTys, Offsets);
298
299 if (SplitTys.size() == 0)
300 return;
301
302 if (SplitTys.size() == 1) {
303 // No splitting to do, but we want to replace the original type (e.g. [1 x
304 // double] -> double).
305 SplitArgs.emplace_back(Args: OrigArg.Regs[0], Args&: SplitTys[0], Args: OrigArg.OrigArgIndex,
306 Args: OrigArg.Flags[0], Args: OrigArg.OrigValue);
307 return;
308 }
309
310 // Create one ArgInfo for each virtual register in the original ArgInfo.
311 assert(OrigArg.Regs.size() == SplitTys.size() && "Regs / types mismatch");
312
313 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
314 Ty: OrigArg.Ty, CallConv, isVarArg: false, DL);
315 for (unsigned i = 0, e = SplitTys.size(); i < e; ++i) {
316 SplitArgs.emplace_back(Args: OrigArg.Regs[i], Args&: SplitTys[i], Args: OrigArg.OrigArgIndex,
317 Args: OrigArg.Flags[0]);
318 if (NeedsRegBlock)
319 SplitArgs.back().Flags[0].setInConsecutiveRegs();
320 }
321
322 SplitArgs.back().Flags[0].setInConsecutiveRegsLast();
323}
324
325/// Pack values \p SrcRegs to cover the vector type result \p DstRegs.
326static MachineInstrBuilder
327mergeVectorRegsToResultRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs,
328 ArrayRef<Register> SrcRegs) {
329 MachineRegisterInfo &MRI = *B.getMRI();
330 LLT LLTy = MRI.getType(Reg: DstRegs[0]);
331 LLT PartLLT = MRI.getType(Reg: SrcRegs[0]);
332
333 // Deal with v3s16 split into v2s16
334 LLT LCMTy = getCoverTy(OrigTy: LLTy, TargetTy: PartLLT);
335 if (LCMTy == LLTy) {
336 // Common case where no padding is needed.
337 assert(DstRegs.size() == 1);
338 return B.buildConcatVectors(Res: DstRegs[0], Ops: SrcRegs);
339 }
340
341 // We need to create an unmerge to the result registers, which may require
342 // widening the original value.
343 Register UnmergeSrcReg;
344 if (LCMTy != PartLLT) {
345 assert(DstRegs.size() == 1);
346 return B.buildDeleteTrailingVectorElements(
347 Res: DstRegs[0], Op0: B.buildMergeLikeInstr(Res: LCMTy, Ops: SrcRegs));
348 } else {
349 // We don't need to widen anything if we're extracting a scalar which was
350 // promoted to a vector e.g. s8 -> v4s8 -> s8
351 assert(SrcRegs.size() == 1);
352 UnmergeSrcReg = SrcRegs[0];
353 }
354
355 int NumDst = LCMTy.getSizeInBits() / LLTy.getSizeInBits();
356
357 SmallVector<Register, 8> PadDstRegs(NumDst);
358 llvm::copy(Range&: DstRegs, Out: PadDstRegs.begin());
359
360 // Create the excess dead defs for the unmerge.
361 for (int I = DstRegs.size(); I != NumDst; ++I)
362 PadDstRegs[I] = MRI.createGenericVirtualRegister(Ty: LLTy);
363
364 if (PadDstRegs.size() == 1)
365 return B.buildDeleteTrailingVectorElements(Res: DstRegs[0], Op0: UnmergeSrcReg);
366 return B.buildUnmerge(Res: PadDstRegs, Op: UnmergeSrcReg);
367}
368
369void CallLowering::buildCopyFromRegs(MachineIRBuilder &B,
370 ArrayRef<Register> OrigRegs,
371 ArrayRef<Register> Regs, LLT LLTy,
372 LLT PartLLT, const ISD::ArgFlagsTy Flags) {
373 MachineRegisterInfo &MRI = *B.getMRI();
374
375 if (PartLLT == LLTy) {
376 // We should have avoided introducing a new virtual register, and just
377 // directly assigned here.
378 assert(OrigRegs[0] == Regs[0]);
379 return;
380 }
381
382 if (PartLLT.getSizeInBits() == LLTy.getSizeInBits() && OrigRegs.size() == 1 &&
383 Regs.size() == 1) {
384 B.buildBitcast(Dst: OrigRegs[0], Src: Regs[0]);
385 return;
386 }
387
388 // A vector PartLLT needs extending to LLTy's element size.
389 // E.g. <2 x s64> = G_SEXT <2 x s32>.
390 if (PartLLT.isVector() == LLTy.isVector() &&
391 PartLLT.getScalarSizeInBits() > LLTy.getScalarSizeInBits() &&
392 (!PartLLT.isVector() ||
393 PartLLT.getElementCount() == LLTy.getElementCount()) &&
394 OrigRegs.size() == 1 && Regs.size() == 1) {
395 Register SrcReg = Regs[0];
396
397 LLT LocTy = MRI.getType(Reg: SrcReg);
398
399 if (Flags.isSExt()) {
400 SrcReg = B.buildAssertSExt(Res: LocTy, Op: SrcReg, Size: LLTy.getScalarSizeInBits())
401 .getReg(Idx: 0);
402 } else if (Flags.isZExt()) {
403 SrcReg = B.buildAssertZExt(Res: LocTy, Op: SrcReg, Size: LLTy.getScalarSizeInBits())
404 .getReg(Idx: 0);
405 }
406
407 // Sometimes pointers are passed zero extended.
408 LLT OrigTy = MRI.getType(Reg: OrigRegs[0]);
409 if (OrigTy.isPointer()) {
410 LLT IntPtrTy = LLT::scalar(SizeInBits: OrigTy.getSizeInBits());
411 B.buildIntToPtr(Dst: OrigRegs[0], Src: B.buildTrunc(Res: IntPtrTy, Op: SrcReg));
412 return;
413 }
414
415 B.buildTrunc(Res: OrigRegs[0], Op: SrcReg);
416 return;
417 }
418
419 if (!LLTy.isVector() && !PartLLT.isVector()) {
420 assert(OrigRegs.size() == 1);
421 LLT OrigTy = MRI.getType(Reg: OrigRegs[0]);
422
423 unsigned SrcSize = PartLLT.getSizeInBits().getFixedValue() * Regs.size();
424 if (SrcSize == OrigTy.getSizeInBits())
425 B.buildMergeValues(Res: OrigRegs[0], Ops: Regs);
426 else {
427 auto Widened = B.buildMergeLikeInstr(Res: LLT::scalar(SizeInBits: SrcSize), Ops: Regs);
428 B.buildTrunc(Res: OrigRegs[0], Op: Widened);
429 }
430
431 return;
432 }
433
434 if (PartLLT.isVector()) {
435 assert(OrigRegs.size() == 1);
436 SmallVector<Register> CastRegs(Regs);
437
438 // If PartLLT is a mismatched vector in both number of elements and element
439 // size, e.g. PartLLT == v2s64 and LLTy is v3s32, then first coerce it to
440 // have the same elt type, i.e. v4s32.
441 // TODO: Extend this coersion to element multiples other than just 2.
442 if (TypeSize::isKnownGT(LHS: PartLLT.getSizeInBits(), RHS: LLTy.getSizeInBits()) &&
443 PartLLT.getScalarSizeInBits() == LLTy.getScalarSizeInBits() * 2 &&
444 Regs.size() == 1) {
445 LLT NewTy = PartLLT.changeElementType(NewEltTy: LLTy.getElementType())
446 .changeElementCount(EC: PartLLT.getElementCount() * 2);
447 CastRegs[0] = B.buildBitcast(Dst: NewTy, Src: Regs[0]).getReg(Idx: 0);
448 PartLLT = NewTy;
449 }
450
451 if (LLTy.getScalarType() == PartLLT.getElementType()) {
452 mergeVectorRegsToResultRegs(B, DstRegs: OrigRegs, SrcRegs: CastRegs);
453 } else {
454 unsigned I = 0;
455 LLT GCDTy = getGCDType(OrigTy: LLTy, TargetTy: PartLLT);
456
457 // We are both splitting a vector, and bitcasting its element types. Cast
458 // the source pieces into the appropriate number of pieces with the result
459 // element type.
460 for (Register SrcReg : CastRegs)
461 CastRegs[I++] = B.buildBitcast(Dst: GCDTy, Src: SrcReg).getReg(Idx: 0);
462 mergeVectorRegsToResultRegs(B, DstRegs: OrigRegs, SrcRegs: CastRegs);
463 }
464
465 return;
466 }
467
468 assert(LLTy.isVector() && !PartLLT.isVector());
469
470 LLT DstEltTy = LLTy.getElementType();
471
472 // Pointer information was discarded. We'll need to coerce some register types
473 // to avoid violating type constraints.
474 LLT RealDstEltTy = MRI.getType(Reg: OrigRegs[0]).getElementType();
475
476 assert(DstEltTy.getSizeInBits() == RealDstEltTy.getSizeInBits());
477
478 if (DstEltTy == PartLLT) {
479 // Vector was trivially scalarized.
480
481 if (RealDstEltTy.isPointer()) {
482 for (Register Reg : Regs)
483 MRI.setType(VReg: Reg, Ty: RealDstEltTy);
484 }
485
486 B.buildBuildVector(Res: OrigRegs[0], Ops: Regs);
487 } else if (DstEltTy.getSizeInBits() > PartLLT.getSizeInBits()) {
488 // Deal with vector with 64-bit elements decomposed to 32-bit
489 // registers. Need to create intermediate 64-bit elements.
490 SmallVector<Register, 8> EltMerges;
491 int PartsPerElt =
492 divideCeil(Numerator: DstEltTy.getSizeInBits(), Denominator: PartLLT.getSizeInBits());
493 LLT ExtendedPartTy = LLT::scalar(SizeInBits: PartLLT.getSizeInBits() * PartsPerElt);
494
495 for (int I = 0, NumElts = LLTy.getNumElements(); I != NumElts; ++I) {
496 auto Merge =
497 B.buildMergeLikeInstr(Res: ExtendedPartTy, Ops: Regs.take_front(N: PartsPerElt));
498 if (ExtendedPartTy.getSizeInBits() > RealDstEltTy.getSizeInBits())
499 Merge = B.buildTrunc(Res: RealDstEltTy, Op: Merge);
500 // Fix the type in case this is really a vector of pointers.
501 MRI.setType(VReg: Merge.getReg(Idx: 0), Ty: RealDstEltTy);
502 EltMerges.push_back(Elt: Merge.getReg(Idx: 0));
503 Regs = Regs.drop_front(N: PartsPerElt);
504 }
505
506 B.buildBuildVector(Res: OrigRegs[0], Ops: EltMerges);
507 } else {
508 // Vector was split, and elements promoted to a wider type.
509 // FIXME: Should handle floating point promotions.
510 unsigned NumElts = LLTy.getNumElements();
511 LLT BVType = LLT::fixed_vector(NumElements: NumElts, ScalarTy: PartLLT);
512
513 Register BuildVec;
514 if (NumElts == Regs.size())
515 BuildVec = B.buildBuildVector(Res: BVType, Ops: Regs).getReg(Idx: 0);
516 else {
517 // Vector elements are packed in the inputs.
518 // e.g. we have a <4 x s16> but 2 x s32 in regs.
519 assert(NumElts > Regs.size());
520 LLT SrcEltTy = MRI.getType(Reg: Regs[0]);
521
522 LLT OriginalEltTy = MRI.getType(Reg: OrigRegs[0]).getElementType();
523
524 // Input registers contain packed elements.
525 // Determine how many elements per reg.
526 assert((SrcEltTy.getSizeInBits() % OriginalEltTy.getSizeInBits()) == 0);
527 unsigned EltPerReg =
528 (SrcEltTy.getSizeInBits() / OriginalEltTy.getSizeInBits());
529
530 SmallVector<Register, 0> BVRegs;
531 BVRegs.reserve(N: Regs.size() * EltPerReg);
532 for (Register R : Regs) {
533 auto Unmerge = B.buildUnmerge(Res: OriginalEltTy, Op: R);
534 for (unsigned K = 0; K < EltPerReg; ++K)
535 BVRegs.push_back(Elt: B.buildAnyExt(Res: PartLLT, Op: Unmerge.getReg(Idx: K)).getReg(Idx: 0));
536 }
537
538 // We may have some more elements in BVRegs, e.g. if we have 2 s32 pieces
539 // for a <3 x s16> vector. We should have less than EltPerReg extra items.
540 if (BVRegs.size() > NumElts) {
541 assert((BVRegs.size() - NumElts) < EltPerReg);
542 BVRegs.truncate(N: NumElts);
543 }
544 BuildVec = B.buildBuildVector(Res: BVType, Ops: BVRegs).getReg(Idx: 0);
545 }
546 B.buildTrunc(Res: OrigRegs[0], Op: BuildVec);
547 }
548}
549
550void CallLowering::buildCopyToRegs(MachineIRBuilder &B,
551 ArrayRef<Register> DstRegs, Register SrcReg,
552 LLT SrcTy, LLT PartTy, unsigned ExtendOp) {
553 // We could just insert a regular copy, but this is unreachable at the moment.
554 assert(SrcTy != PartTy && "identical part types shouldn't reach here");
555
556 const TypeSize PartSize = PartTy.getSizeInBits();
557
558 if (PartSize == SrcTy.getSizeInBits() && DstRegs.size() == 1) {
559 // TODO: Handle int<->ptr casts. It just happens the ABI lowering
560 // assignments are not pointer aware.
561 B.buildBitcast(Dst: DstRegs[0], Src: SrcReg);
562 return;
563 }
564
565 if (PartTy.isVector() == SrcTy.isVector() &&
566 PartTy.getScalarSizeInBits() > SrcTy.getScalarSizeInBits()) {
567 assert(DstRegs.size() == 1);
568 B.buildInstr(Opc: ExtendOp, DstOps: {DstRegs[0]}, SrcOps: {SrcReg});
569 return;
570 }
571
572 if (SrcTy.isVector() && !PartTy.isVector() &&
573 TypeSize::isKnownGT(LHS: PartSize, RHS: SrcTy.getElementType().getSizeInBits()) &&
574 SrcTy.getElementCount() == ElementCount::getFixed(MinVal: DstRegs.size())) {
575 // Vector was scalarized, and the elements extended.
576 auto UnmergeToEltTy = B.buildUnmerge(Res: SrcTy.getElementType(), Op: SrcReg);
577 for (int i = 0, e = DstRegs.size(); i != e; ++i)
578 B.buildAnyExt(Res: DstRegs[i], Op: UnmergeToEltTy.getReg(Idx: i));
579 return;
580 }
581
582 if (SrcTy.isVector() && PartTy.isVector() &&
583 PartTy.getSizeInBits() == SrcTy.getSizeInBits() &&
584 ElementCount::isKnownLT(LHS: SrcTy.getElementCount(),
585 RHS: PartTy.getElementCount())) {
586 // A coercion like: v2f32 -> v4f32 or nxv2f32 -> nxv4f32
587 Register DstReg = DstRegs.front();
588 B.buildPadVectorWithUndefElements(Res: DstReg, Op0: SrcReg);
589 return;
590 }
591
592 LLT GCDTy = getGCDType(OrigTy: SrcTy, TargetTy: PartTy);
593 if (GCDTy == PartTy) {
594 // If this already evenly divisible, we can create a simple unmerge.
595 B.buildUnmerge(Res: DstRegs, Op: SrcReg);
596 return;
597 }
598
599 if (SrcTy.isVector() && !PartTy.isVector() &&
600 SrcTy.getScalarSizeInBits() > PartTy.getSizeInBits()) {
601 LLT ExtTy =
602 LLT::vector(EC: SrcTy.getElementCount(),
603 ScalarTy: LLT::scalar(SizeInBits: PartTy.getScalarSizeInBits() * DstRegs.size() /
604 SrcTy.getNumElements()));
605 auto Ext = B.buildAnyExt(Res: ExtTy, Op: SrcReg);
606 B.buildUnmerge(Res: DstRegs, Op: Ext);
607 return;
608 }
609
610 MachineRegisterInfo &MRI = *B.getMRI();
611 LLT DstTy = MRI.getType(Reg: DstRegs[0]);
612 LLT CoverTy = getCoverTy(OrigTy: SrcTy, TargetTy: PartTy);
613 if (SrcTy.isVector() && DstRegs.size() > 1) {
614 TypeSize FullCoverSize =
615 DstTy.getSizeInBits().multiplyCoefficientBy(RHS: DstRegs.size());
616
617 LLT EltTy = SrcTy.getElementType();
618 TypeSize EltSize = EltTy.getSizeInBits();
619 if (FullCoverSize.isKnownMultipleOf(RHS: EltSize)) {
620 TypeSize VecSize = FullCoverSize.divideCoefficientBy(RHS: EltSize);
621 CoverTy =
622 LLT::vector(EC: ElementCount::get(MinVal: VecSize, Scalable: VecSize.isScalable()), ScalarTy: EltTy);
623 }
624 }
625
626 if (PartTy.isVector() && CoverTy == PartTy) {
627 assert(DstRegs.size() == 1);
628 B.buildPadVectorWithUndefElements(Res: DstRegs[0], Op0: SrcReg);
629 return;
630 }
631
632 const unsigned DstSize = DstTy.getSizeInBits();
633 const unsigned SrcSize = SrcTy.getSizeInBits();
634 unsigned CoveringSize = CoverTy.getSizeInBits();
635
636 Register UnmergeSrc = SrcReg;
637
638 if (!CoverTy.isVector() && CoveringSize != SrcSize) {
639 // For scalars, it's common to be able to use a simple extension.
640 if (SrcTy.isScalar() && DstTy.isScalar()) {
641 CoveringSize = alignTo(Value: SrcSize, Align: DstSize);
642 LLT CoverTy = LLT::scalar(SizeInBits: CoveringSize);
643 UnmergeSrc = B.buildInstr(Opc: ExtendOp, DstOps: {CoverTy}, SrcOps: {SrcReg}).getReg(Idx: 0);
644 } else {
645 // Widen to the common type.
646 // FIXME: This should respect the extend type
647 Register Undef = B.buildUndef(Res: SrcTy).getReg(Idx: 0);
648 SmallVector<Register, 8> MergeParts(1, SrcReg);
649 for (unsigned Size = SrcSize; Size != CoveringSize; Size += SrcSize)
650 MergeParts.push_back(Elt: Undef);
651 UnmergeSrc = B.buildMergeLikeInstr(Res: CoverTy, Ops: MergeParts).getReg(Idx: 0);
652 }
653 }
654
655 if (CoverTy.isVector() && CoveringSize != SrcSize)
656 UnmergeSrc = B.buildPadVectorWithUndefElements(Res: CoverTy, Op0: SrcReg).getReg(Idx: 0);
657
658 B.buildUnmerge(Res: DstRegs, Op: UnmergeSrc);
659}
660
661bool CallLowering::determineAndHandleAssignments(
662 ValueHandler &Handler, ValueAssigner &Assigner,
663 SmallVectorImpl<ArgInfo> &Args, MachineIRBuilder &MIRBuilder,
664 CallingConv::ID CallConv, bool IsVarArg,
665 ArrayRef<Register> ThisReturnRegs) const {
666 MachineFunction &MF = MIRBuilder.getMF();
667 const Function &F = MF.getFunction();
668 SmallVector<CCValAssign, 16> ArgLocs;
669
670 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, F.getContext());
671 if (!determineAssignments(Assigner, Args, CCInfo))
672 return false;
673
674 return handleAssignments(Handler, Args, CCState&: CCInfo, ArgLocs, MIRBuilder,
675 ThisReturnRegs);
676}
677
678static unsigned extendOpFromFlags(llvm::ISD::ArgFlagsTy Flags) {
679 if (Flags.isSExt())
680 return TargetOpcode::G_SEXT;
681 if (Flags.isZExt())
682 return TargetOpcode::G_ZEXT;
683 return TargetOpcode::G_ANYEXT;
684}
685
686bool CallLowering::determineAssignments(ValueAssigner &Assigner,
687 SmallVectorImpl<ArgInfo> &Args,
688 CCState &CCInfo) const {
689 LLVMContext &Ctx = CCInfo.getContext();
690 const DataLayout &DL = CCInfo.getMachineFunction().getDataLayout();
691 const CallingConv::ID CallConv = CCInfo.getCallingConv();
692
693 unsigned NumArgs = Args.size();
694 for (unsigned i = 0; i != NumArgs; ++i) {
695 EVT CurVT = TLI->getValueType(DL, Ty: Args[i].Ty);
696
697 MVT NewVT = TLI->getRegisterTypeForCallingConv(Context&: Ctx, CC: CallConv, VT: CurVT);
698
699 // If we need to split the type over multiple regs, check it's a scenario
700 // we currently support.
701 unsigned NumParts =
702 TLI->getNumRegistersForCallingConv(Context&: Ctx, CC: CallConv, VT: CurVT);
703
704 if (NumParts == 1) {
705 // Try to use the register type if we couldn't assign the VT.
706 if (Assigner.assignArg(ValNo: i, OrigVT: CurVT, ValVT: NewVT, LocVT: NewVT, LocInfo: CCValAssign::Full, Info: Args[i],
707 Flags: Args[i].Flags[0], State&: CCInfo))
708 return false;
709 continue;
710 }
711
712 // For incoming arguments (physregs to vregs), we could have values in
713 // physregs (or memlocs) which we want to extract and copy to vregs.
714 // During this, we might have to deal with the LLT being split across
715 // multiple regs, so we have to record this information for later.
716 //
717 // If we have outgoing args, then we have the opposite case. We have a
718 // vreg with an LLT which we want to assign to a physical location, and
719 // we might have to record that the value has to be split later.
720
721 // We're handling an incoming arg which is split over multiple regs.
722 // E.g. passing an s128 on AArch64.
723 ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0];
724 Args[i].Flags.clear();
725
726 for (unsigned Part = 0; Part < NumParts; ++Part) {
727 ISD::ArgFlagsTy Flags = OrigFlags;
728 if (Part == 0) {
729 Flags.setSplit();
730 } else {
731 Flags.setOrigAlign(Align(1));
732 if (Part == NumParts - 1)
733 Flags.setSplitEnd();
734 }
735
736 Args[i].Flags.push_back(Elt: Flags);
737 if (Assigner.assignArg(ValNo: i, OrigVT: CurVT, ValVT: NewVT, LocVT: NewVT, LocInfo: CCValAssign::Full, Info: Args[i],
738 Flags: Args[i].Flags[Part], State&: CCInfo)) {
739 // Still couldn't assign this smaller part type for some reason.
740 return false;
741 }
742 }
743 }
744
745 return true;
746}
747
748bool CallLowering::handleAssignments(ValueHandler &Handler,
749 SmallVectorImpl<ArgInfo> &Args,
750 CCState &CCInfo,
751 SmallVectorImpl<CCValAssign> &ArgLocs,
752 MachineIRBuilder &MIRBuilder,
753 ArrayRef<Register> ThisReturnRegs) const {
754 MachineFunction &MF = MIRBuilder.getMF();
755 MachineRegisterInfo &MRI = MF.getRegInfo();
756 const Function &F = MF.getFunction();
757 const DataLayout &DL = F.getDataLayout();
758
759 const unsigned NumArgs = Args.size();
760
761 // Stores thunks for outgoing register assignments. This is used so we delay
762 // generating register copies until mem loc assignments are done. We do this
763 // so that if the target is using the delayed stack protector feature, we can
764 // find the split point of the block accurately. E.g. if we have:
765 // G_STORE %val, %memloc
766 // $x0 = COPY %foo
767 // $x1 = COPY %bar
768 // CALL func
769 // ... then the split point for the block will correctly be at, and including,
770 // the copy to $x0. If instead the G_STORE instruction immediately precedes
771 // the CALL, then we'd prematurely choose the CALL as the split point, thus
772 // generating a split block with a CALL that uses undefined physregs.
773 SmallVector<std::function<void()>> DelayedOutgoingRegAssignments;
774
775 for (unsigned i = 0, j = 0; i != NumArgs; ++i, ++j) {
776 assert(j < ArgLocs.size() && "Skipped too many arg locs");
777 CCValAssign &VA = ArgLocs[j];
778 assert(VA.getValNo() == i && "Location doesn't correspond to current arg");
779
780 if (VA.needsCustom()) {
781 std::function<void()> Thunk;
782 unsigned NumArgRegs = Handler.assignCustomValue(
783 Arg&: Args[i], VAs: ArrayRef(ArgLocs).slice(N: j), Thunk: &Thunk);
784 if (Thunk)
785 DelayedOutgoingRegAssignments.emplace_back(Args&: Thunk);
786 if (!NumArgRegs)
787 return false;
788 j += (NumArgRegs - 1);
789 continue;
790 }
791
792 auto AllocaAddressSpace = MF.getDataLayout().getAllocaAddrSpace();
793
794 const MVT ValVT = VA.getValVT();
795 const MVT LocVT = VA.getLocVT();
796
797 const LLT LocTy(LocVT);
798 const LLT ValTy(ValVT);
799 const LLT NewLLT = Handler.isIncomingArgumentHandler() ? LocTy : ValTy;
800 const EVT OrigVT = TLI->getValueType(DL, Ty: Args[i].Ty);
801 // Use the EVT here to strip pointerness.
802 const LLT OrigTy = getLLTForType(Ty&: *OrigVT.getTypeForEVT(Context&: F.getContext()), DL);
803 const LLT PointerTy = LLT::pointer(
804 AddressSpace: AllocaAddressSpace, SizeInBits: DL.getPointerSizeInBits(AS: AllocaAddressSpace));
805
806 // Expected to be multiple regs for a single incoming arg.
807 // There should be Regs.size() ArgLocs per argument.
808 // This should be the same as getNumRegistersForCallingConv
809 const unsigned NumParts = Args[i].Flags.size();
810
811 // Now split the registers into the assigned types.
812 Args[i].OrigRegs.assign(in_start: Args[i].Regs.begin(), in_end: Args[i].Regs.end());
813
814 if (NumParts != 1 || NewLLT != OrigTy) {
815 // If we can't directly assign the register, we need one or more
816 // intermediate values.
817 Args[i].Regs.resize(N: NumParts);
818
819 // When we have indirect parameter passing we are receiving a pointer,
820 // that points to the actual value, so we need one "temporary" pointer.
821 if (VA.getLocInfo() == CCValAssign::Indirect) {
822 if (Handler.isIncomingArgumentHandler())
823 Args[i].Regs[0] = MRI.createGenericVirtualRegister(Ty: PointerTy);
824 } else {
825 // For each split register, create and assign a vreg that will store
826 // the incoming component of the larger value. These will later be
827 // merged to form the final vreg.
828 for (unsigned Part = 0; Part < NumParts; ++Part)
829 Args[i].Regs[Part] = MRI.createGenericVirtualRegister(Ty: NewLLT);
830 }
831 }
832
833 assert((j + (NumParts - 1)) < ArgLocs.size() &&
834 "Too many regs for number of args");
835
836 // Coerce into outgoing value types before register assignment.
837 if (!Handler.isIncomingArgumentHandler() && OrigTy != ValTy &&
838 VA.getLocInfo() != CCValAssign::Indirect) {
839 assert(Args[i].OrigRegs.size() == 1);
840 buildCopyToRegs(B&: MIRBuilder, DstRegs: Args[i].Regs, SrcReg: Args[i].OrigRegs[0], SrcTy: OrigTy,
841 PartTy: ValTy, ExtendOp: extendOpFromFlags(Flags: Args[i].Flags[0]));
842 }
843
844 bool IndirectParameterPassingHandled = false;
845 bool BigEndianPartOrdering = TLI->hasBigEndianPartOrdering(VT: OrigVT, DL);
846 for (unsigned Part = 0; Part < NumParts; ++Part) {
847 assert((VA.getLocInfo() != CCValAssign::Indirect || Part == 0) &&
848 "Only the first parameter should be processed when "
849 "handling indirect passing!");
850 Register ArgReg = Args[i].Regs[Part];
851 // There should be Regs.size() ArgLocs per argument.
852 unsigned Idx = BigEndianPartOrdering ? NumParts - 1 - Part : Part;
853 CCValAssign &VA = ArgLocs[j + Idx];
854 const ISD::ArgFlagsTy Flags = Args[i].Flags[Part];
855
856 // We found an indirect parameter passing, and we have an
857 // OutgoingValueHandler as our handler (so we are at the call site or the
858 // return value). In this case, start the construction of the following
859 // GMIR, that is responsible for the preparation of indirect parameter
860 // passing:
861 //
862 // %1(indirectly passed type) = The value to pass
863 // %3(pointer) = G_FRAME_INDEX %stack.0
864 // G_STORE %1, %3 :: (store (s128), align 8)
865 //
866 // After this GMIR, the remaining part of the loop body will decide how
867 // to get the value to the caller and we break out of the loop.
868 if (VA.getLocInfo() == CCValAssign::Indirect &&
869 !Handler.isIncomingArgumentHandler()) {
870 Align AlignmentForStored = DL.getPrefTypeAlign(Ty: Args[i].Ty);
871 MachineFrameInfo &MFI = MF.getFrameInfo();
872 // Get some space on the stack for the value, so later we can pass it
873 // as a reference.
874 int FrameIdx = MFI.CreateStackObject(Size: OrigTy.getScalarSizeInBits(),
875 Alignment: AlignmentForStored, isSpillSlot: false);
876 Register PointerToStackReg =
877 MIRBuilder.buildFrameIndex(Res: PointerTy, Idx: FrameIdx).getReg(Idx: 0);
878 MachinePointerInfo StackPointerMPO =
879 MachinePointerInfo::getFixedStack(MF, FI: FrameIdx);
880 // Store the value in the previously created stack space.
881 MIRBuilder.buildStore(Val: Args[i].OrigRegs[Part], Addr: PointerToStackReg,
882 PtrInfo: StackPointerMPO,
883 Alignment: inferAlignFromPtrInfo(MF, MPO: StackPointerMPO));
884
885 ArgReg = PointerToStackReg;
886 IndirectParameterPassingHandled = true;
887 }
888
889 if (VA.isMemLoc() && !Flags.isByVal()) {
890 // Individual pieces may have been spilled to the stack and others
891 // passed in registers.
892
893 // TODO: The memory size may be larger than the value we need to
894 // store. We may need to adjust the offset for big endian targets.
895 LLT MemTy = Handler.getStackValueStoreType(DL, VA, Flags);
896
897 MachinePointerInfo MPO;
898 Register StackAddr =
899 Handler.getStackAddress(MemSize: VA.getLocInfo() == CCValAssign::Indirect
900 ? PointerTy.getSizeInBytes()
901 : MemTy.getSizeInBytes(),
902 Offset: VA.getLocMemOffset(), MPO, Flags);
903
904 // Finish the handling of indirect passing from the passers
905 // (OutgoingParameterHandler) side.
906 // This branch is needed, so the pointer to the value is loaded onto the
907 // stack.
908 if (VA.getLocInfo() == CCValAssign::Indirect)
909 Handler.assignValueToAddress(ValVReg: ArgReg, Addr: StackAddr, MemTy: PointerTy, MPO, VA);
910 else
911 Handler.assignValueToAddress(Arg: Args[i], ValRegIndex: Part, Addr: StackAddr, MemTy, MPO,
912 VA);
913 } else if (VA.isMemLoc() && Flags.isByVal()) {
914 assert(Args[i].Regs.size() == 1 && "didn't expect split byval pointer");
915
916 if (Handler.isIncomingArgumentHandler()) {
917 // We just need to copy the frame index value to the pointer.
918 MachinePointerInfo MPO;
919 Register StackAddr = Handler.getStackAddress(
920 MemSize: Flags.getByValSize(), Offset: VA.getLocMemOffset(), MPO, Flags);
921 MIRBuilder.buildCopy(Res: Args[i].Regs[0], Op: StackAddr);
922 } else {
923 // For outgoing byval arguments, insert the implicit copy byval
924 // implies, such that writes in the callee do not modify the caller's
925 // value.
926 uint64_t MemSize = Flags.getByValSize();
927 int64_t Offset = VA.getLocMemOffset();
928
929 MachinePointerInfo DstMPO;
930 Register StackAddr =
931 Handler.getStackAddress(MemSize, Offset, MPO&: DstMPO, Flags);
932
933 MachinePointerInfo SrcMPO(Args[i].OrigValue);
934 if (!Args[i].OrigValue) {
935 // We still need to accurately track the stack address space if we
936 // don't know the underlying value.
937 const LLT PtrTy = MRI.getType(Reg: StackAddr);
938 SrcMPO = MachinePointerInfo(PtrTy.getAddressSpace());
939 }
940
941 Align DstAlign = std::max(a: Flags.getNonZeroByValAlign(),
942 b: inferAlignFromPtrInfo(MF, MPO: DstMPO));
943
944 Align SrcAlign = std::max(a: Flags.getNonZeroByValAlign(),
945 b: inferAlignFromPtrInfo(MF, MPO: SrcMPO));
946
947 Handler.copyArgumentMemory(Arg: Args[i], DstPtr: StackAddr, SrcPtr: Args[i].Regs[0],
948 DstPtrInfo: DstMPO, DstAlign, SrcPtrInfo: SrcMPO, SrcAlign,
949 MemSize, VA);
950 }
951 } else if (i == 0 && !ThisReturnRegs.empty() &&
952 Handler.isIncomingArgumentHandler() &&
953 isTypeIsValidForThisReturn(Ty: ValVT)) {
954 Handler.assignValueToReg(ValVReg: ArgReg, PhysReg: ThisReturnRegs[Part], VA);
955 } else if (Handler.isIncomingArgumentHandler()) {
956 Handler.assignValueToReg(ValVReg: ArgReg, PhysReg: VA.getLocReg(), VA);
957 } else {
958 DelayedOutgoingRegAssignments.emplace_back(Args: [=, &Handler]() {
959 Handler.assignValueToReg(ValVReg: ArgReg, PhysReg: VA.getLocReg(), VA);
960 });
961 }
962
963 // Finish the handling of indirect parameter passing when receiving
964 // the value (we are in the called function or the caller when receiving
965 // the return value).
966 if (VA.getLocInfo() == CCValAssign::Indirect &&
967 Handler.isIncomingArgumentHandler()) {
968 Align Alignment = DL.getABITypeAlign(Ty: Args[i].Ty);
969 MachinePointerInfo MPO = MachinePointerInfo::getUnknownStack(MF);
970
971 // Since we are doing indirect parameter passing, we know that the value
972 // in the temporary register is not the value passed to the function,
973 // but rather a pointer to that value. Let's load that value into the
974 // virtual register where the parameter should go.
975 MIRBuilder.buildLoad(Res: Args[i].OrigRegs[0], Addr: Args[i].Regs[0], PtrInfo: MPO,
976 Alignment);
977
978 IndirectParameterPassingHandled = true;
979 }
980
981 if (IndirectParameterPassingHandled)
982 break;
983 }
984
985 // Now that all pieces have been assigned, re-pack the register typed values
986 // into the original value typed registers. This is only necessary, when
987 // the value was passed in multiple registers, not indirectly.
988 if (Handler.isIncomingArgumentHandler() && OrigVT != LocVT &&
989 !IndirectParameterPassingHandled) {
990 // Merge the split registers into the expected larger result vregs of
991 // the original call.
992 buildCopyFromRegs(B&: MIRBuilder, OrigRegs: Args[i].OrigRegs, Regs: Args[i].Regs, LLTy: OrigTy,
993 PartLLT: LocTy, Flags: Args[i].Flags[0]);
994 }
995
996 j += NumParts - 1;
997 }
998 for (auto &Fn : DelayedOutgoingRegAssignments)
999 Fn();
1000
1001 return true;
1002}
1003
1004void CallLowering::insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy,
1005 ArrayRef<Register> VRegs, Register DemoteReg,
1006 int FI) const {
1007 MachineFunction &MF = MIRBuilder.getMF();
1008 MachineRegisterInfo &MRI = MF.getRegInfo();
1009 const DataLayout &DL = MF.getDataLayout();
1010
1011 SmallVector<EVT, 4> SplitVTs;
1012 SmallVector<uint64_t, 4> Offsets;
1013 ComputeValueVTs(TLI: *TLI, DL, Ty: RetTy, ValueVTs&: SplitVTs, /*MemVTs=*/nullptr, FixedOffsets: &Offsets, StartingOffset: 0);
1014
1015 assert(VRegs.size() == SplitVTs.size());
1016
1017 unsigned NumValues = SplitVTs.size();
1018 Align BaseAlign = DL.getPrefTypeAlign(Ty: RetTy);
1019 Type *RetPtrTy =
1020 PointerType::get(C&: RetTy->getContext(), AddressSpace: DL.getAllocaAddrSpace());
1021 LLT OffsetLLTy = getLLTForType(Ty&: *DL.getIndexType(PtrTy: RetPtrTy), DL);
1022
1023 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
1024
1025 for (unsigned I = 0; I < NumValues; ++I) {
1026 Register Addr;
1027 MIRBuilder.materializeObjectPtrOffset(Res&: Addr, Op0: DemoteReg, ValueTy: OffsetLLTy,
1028 Value: Offsets[I]);
1029 auto *MMO = MF.getMachineMemOperand(PtrInfo, f: MachineMemOperand::MOLoad,
1030 MemTy: MRI.getType(Reg: VRegs[I]),
1031 base_alignment: commonAlignment(A: BaseAlign, Offset: Offsets[I]));
1032 MIRBuilder.buildLoad(Res: VRegs[I], Addr, MMO&: *MMO);
1033 }
1034}
1035
1036void CallLowering::insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy,
1037 ArrayRef<Register> VRegs,
1038 Register DemoteReg) const {
1039 MachineFunction &MF = MIRBuilder.getMF();
1040 MachineRegisterInfo &MRI = MF.getRegInfo();
1041 const DataLayout &DL = MF.getDataLayout();
1042
1043 SmallVector<EVT, 4> SplitVTs;
1044 SmallVector<uint64_t, 4> Offsets;
1045 ComputeValueVTs(TLI: *TLI, DL, Ty: RetTy, ValueVTs&: SplitVTs, /*MemVTs=*/nullptr, FixedOffsets: &Offsets, StartingOffset: 0);
1046
1047 assert(VRegs.size() == SplitVTs.size());
1048
1049 unsigned NumValues = SplitVTs.size();
1050 Align BaseAlign = DL.getPrefTypeAlign(Ty: RetTy);
1051 unsigned AS = DL.getAllocaAddrSpace();
1052 LLT OffsetLLTy = getLLTForType(Ty&: *DL.getIndexType(C&: RetTy->getContext(), AddressSpace: AS), DL);
1053
1054 MachinePointerInfo PtrInfo(AS);
1055
1056 for (unsigned I = 0; I < NumValues; ++I) {
1057 Register Addr;
1058 MIRBuilder.materializeObjectPtrOffset(Res&: Addr, Op0: DemoteReg, ValueTy: OffsetLLTy,
1059 Value: Offsets[I]);
1060 auto *MMO = MF.getMachineMemOperand(PtrInfo, f: MachineMemOperand::MOStore,
1061 MemTy: MRI.getType(Reg: VRegs[I]),
1062 base_alignment: commonAlignment(A: BaseAlign, Offset: Offsets[I]));
1063 MIRBuilder.buildStore(Val: VRegs[I], Addr, MMO&: *MMO);
1064 }
1065}
1066
1067void CallLowering::insertSRetIncomingArgument(
1068 const Function &F, SmallVectorImpl<ArgInfo> &SplitArgs, Register &DemoteReg,
1069 MachineRegisterInfo &MRI, const DataLayout &DL) const {
1070 unsigned AS = DL.getAllocaAddrSpace();
1071 DemoteReg = MRI.createGenericVirtualRegister(
1072 Ty: LLT::pointer(AddressSpace: AS, SizeInBits: DL.getPointerSizeInBits(AS)));
1073
1074 Type *PtrTy = PointerType::get(C&: F.getContext(), AddressSpace: AS);
1075
1076 SmallVector<EVT, 1> ValueVTs;
1077 ComputeValueVTs(TLI: *TLI, DL, Ty: PtrTy, ValueVTs);
1078
1079 // NOTE: Assume that a pointer won't get split into more than one VT.
1080 assert(ValueVTs.size() == 1);
1081
1082 ArgInfo DemoteArg(DemoteReg, ValueVTs[0].getTypeForEVT(Context&: PtrTy->getContext()),
1083 ArgInfo::NoArgIndex);
1084 setArgFlags(Arg&: DemoteArg, OpIdx: AttributeList::ReturnIndex, DL, FuncInfo: F);
1085 DemoteArg.Flags[0].setSRet();
1086 SplitArgs.insert(I: SplitArgs.begin(), Elt: DemoteArg);
1087}
1088
1089void CallLowering::insertSRetOutgoingArgument(MachineIRBuilder &MIRBuilder,
1090 const CallBase &CB,
1091 CallLoweringInfo &Info) const {
1092 const DataLayout &DL = MIRBuilder.getDataLayout();
1093 Type *RetTy = CB.getType();
1094 unsigned AS = DL.getAllocaAddrSpace();
1095 LLT FramePtrTy = LLT::pointer(AddressSpace: AS, SizeInBits: DL.getPointerSizeInBits(AS));
1096
1097 int FI = MIRBuilder.getMF().getFrameInfo().CreateStackObject(
1098 Size: DL.getTypeAllocSize(Ty: RetTy), Alignment: DL.getPrefTypeAlign(Ty: RetTy), isSpillSlot: false);
1099
1100 Register DemoteReg = MIRBuilder.buildFrameIndex(Res: FramePtrTy, Idx: FI).getReg(Idx: 0);
1101 ArgInfo DemoteArg(DemoteReg, PointerType::get(C&: RetTy->getContext(), AddressSpace: AS),
1102 ArgInfo::NoArgIndex);
1103 setArgFlags(Arg&: DemoteArg, OpIdx: AttributeList::ReturnIndex, DL, FuncInfo: CB);
1104 DemoteArg.Flags[0].setSRet();
1105
1106 Info.OrigArgs.insert(I: Info.OrigArgs.begin(), Elt: DemoteArg);
1107 Info.DemoteStackIndex = FI;
1108 Info.DemoteRegister = DemoteReg;
1109}
1110
1111bool CallLowering::checkReturn(CCState &CCInfo,
1112 SmallVectorImpl<BaseArgInfo> &Outs,
1113 CCAssignFn *Fn) const {
1114 for (unsigned I = 0, E = Outs.size(); I < E; ++I) {
1115 MVT VT = MVT::getVT(Ty: Outs[I].Ty);
1116 if (Fn(I, VT, VT, CCValAssign::Full, Outs[I].Flags[0], Outs[I].Ty, CCInfo))
1117 return false;
1118 }
1119 return true;
1120}
1121
1122void CallLowering::getReturnInfo(CallingConv::ID CallConv, Type *RetTy,
1123 AttributeList Attrs,
1124 SmallVectorImpl<BaseArgInfo> &Outs,
1125 const DataLayout &DL) const {
1126 LLVMContext &Context = RetTy->getContext();
1127 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1128
1129 SmallVector<EVT, 4> SplitVTs;
1130 ComputeValueVTs(TLI: *TLI, DL, Ty: RetTy, ValueVTs&: SplitVTs);
1131 addArgFlagsFromAttributes(Flags, Attrs, OpIdx: AttributeList::ReturnIndex);
1132
1133 for (EVT VT : SplitVTs) {
1134 unsigned NumParts =
1135 TLI->getNumRegistersForCallingConv(Context, CC: CallConv, VT);
1136 MVT RegVT = TLI->getRegisterTypeForCallingConv(Context, CC: CallConv, VT);
1137 Type *PartTy = EVT(RegVT).getTypeForEVT(Context);
1138
1139 for (unsigned I = 0; I < NumParts; ++I) {
1140 Outs.emplace_back(Args&: PartTy, Args&: Flags);
1141 }
1142 }
1143}
1144
1145bool CallLowering::checkReturnTypeForCallConv(MachineFunction &MF) const {
1146 const auto &F = MF.getFunction();
1147 Type *ReturnType = F.getReturnType();
1148 CallingConv::ID CallConv = F.getCallingConv();
1149
1150 SmallVector<BaseArgInfo, 4> SplitArgs;
1151 getReturnInfo(CallConv, RetTy: ReturnType, Attrs: F.getAttributes(), Outs&: SplitArgs,
1152 DL: MF.getDataLayout());
1153 return canLowerReturn(MF, CallConv, Outs&: SplitArgs, IsVarArg: F.isVarArg());
1154}
1155
1156bool CallLowering::parametersInCSRMatch(
1157 const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask,
1158 const SmallVectorImpl<CCValAssign> &OutLocs,
1159 const SmallVectorImpl<ArgInfo> &OutArgs) const {
1160 for (unsigned i = 0; i < OutLocs.size(); ++i) {
1161 const auto &ArgLoc = OutLocs[i];
1162 // If it's not a register, it's fine.
1163 if (!ArgLoc.isRegLoc())
1164 continue;
1165
1166 MCRegister PhysReg = ArgLoc.getLocReg();
1167
1168 // Only look at callee-saved registers.
1169 if (MachineOperand::clobbersPhysReg(RegMask: CallerPreservedMask, PhysReg))
1170 continue;
1171
1172 LLVM_DEBUG(
1173 dbgs()
1174 << "... Call has an argument passed in a callee-saved register.\n");
1175
1176 // Check if it was copied from.
1177 const ArgInfo &OutInfo = OutArgs[i];
1178
1179 if (OutInfo.Regs.size() > 1) {
1180 LLVM_DEBUG(
1181 dbgs() << "... Cannot handle arguments in multiple registers.\n");
1182 return false;
1183 }
1184
1185 // Check if we copy the register, walking through copies from virtual
1186 // registers. Note that getDefIgnoringCopies does not ignore copies from
1187 // physical registers.
1188 MachineInstr *RegDef = getDefIgnoringCopies(Reg: OutInfo.Regs[0], MRI);
1189 if (!RegDef || RegDef->getOpcode() != TargetOpcode::COPY) {
1190 LLVM_DEBUG(
1191 dbgs()
1192 << "... Parameter was not copied into a VReg, cannot tail call.\n");
1193 return false;
1194 }
1195
1196 // Got a copy. Verify that it's the same as the register we want.
1197 Register CopyRHS = RegDef->getOperand(i: 1).getReg();
1198 if (CopyRHS != PhysReg) {
1199 LLVM_DEBUG(dbgs() << "... Callee-saved register was not copied into "
1200 "VReg, cannot tail call.\n");
1201 return false;
1202 }
1203 }
1204
1205 return true;
1206}
1207
1208bool CallLowering::resultsCompatible(CallLoweringInfo &Info,
1209 MachineFunction &MF,
1210 SmallVectorImpl<ArgInfo> &InArgs,
1211 ValueAssigner &CalleeAssigner,
1212 ValueAssigner &CallerAssigner) const {
1213 const Function &F = MF.getFunction();
1214 CallingConv::ID CalleeCC = Info.CallConv;
1215 CallingConv::ID CallerCC = F.getCallingConv();
1216
1217 if (CallerCC == CalleeCC)
1218 return true;
1219
1220 SmallVector<CCValAssign, 16> ArgLocs1;
1221 CCState CCInfo1(CalleeCC, Info.IsVarArg, MF, ArgLocs1, F.getContext());
1222 if (!determineAssignments(Assigner&: CalleeAssigner, Args&: InArgs, CCInfo&: CCInfo1))
1223 return false;
1224
1225 SmallVector<CCValAssign, 16> ArgLocs2;
1226 CCState CCInfo2(CallerCC, F.isVarArg(), MF, ArgLocs2, F.getContext());
1227 if (!determineAssignments(Assigner&: CallerAssigner, Args&: InArgs, CCInfo&: CCInfo2))
1228 return false;
1229
1230 // We need the argument locations to match up exactly. If there's more in
1231 // one than the other, then we are done.
1232 if (ArgLocs1.size() != ArgLocs2.size())
1233 return false;
1234
1235 // Make sure that each location is passed in exactly the same way.
1236 for (unsigned i = 0, e = ArgLocs1.size(); i < e; ++i) {
1237 const CCValAssign &Loc1 = ArgLocs1[i];
1238 const CCValAssign &Loc2 = ArgLocs2[i];
1239
1240 // We need both of them to be the same. So if one is a register and one
1241 // isn't, we're done.
1242 if (Loc1.isRegLoc() != Loc2.isRegLoc())
1243 return false;
1244
1245 if (Loc1.isRegLoc()) {
1246 // If they don't have the same register location, we're done.
1247 if (Loc1.getLocReg() != Loc2.getLocReg())
1248 return false;
1249
1250 // They matched, so we can move to the next ArgLoc.
1251 continue;
1252 }
1253
1254 // Loc1 wasn't a RegLoc, so they both must be MemLocs. Check if they match.
1255 if (Loc1.getLocMemOffset() != Loc2.getLocMemOffset())
1256 return false;
1257 }
1258
1259 return true;
1260}
1261
1262LLT CallLowering::ValueHandler::getStackValueStoreType(
1263 const DataLayout &DL, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const {
1264 const MVT ValVT = VA.getValVT();
1265 if (ValVT != MVT::iPTR) {
1266 LLT ValTy(ValVT);
1267
1268 // We lost the pointeriness going through CCValAssign, so try to restore it
1269 // based on the flags.
1270 if (Flags.isPointer()) {
1271 LLT PtrTy = LLT::pointer(AddressSpace: Flags.getPointerAddrSpace(),
1272 SizeInBits: ValTy.getScalarSizeInBits());
1273 if (ValVT.isVector() && ValVT.getVectorNumElements() != 1)
1274 return LLT::vector(EC: ValTy.getElementCount(), ScalarTy: PtrTy);
1275 return PtrTy;
1276 }
1277
1278 return ValTy;
1279 }
1280
1281 unsigned AddrSpace = Flags.getPointerAddrSpace();
1282 return LLT::pointer(AddressSpace: AddrSpace, SizeInBits: DL.getPointerSize(AS: AddrSpace));
1283}
1284
1285void CallLowering::ValueHandler::copyArgumentMemory(
1286 const ArgInfo &Arg, Register DstPtr, Register SrcPtr,
1287 const MachinePointerInfo &DstPtrInfo, Align DstAlign,
1288 const MachinePointerInfo &SrcPtrInfo, Align SrcAlign, uint64_t MemSize,
1289 CCValAssign &VA) const {
1290 MachineFunction &MF = MIRBuilder.getMF();
1291 MachineMemOperand *SrcMMO = MF.getMachineMemOperand(
1292 PtrInfo: SrcPtrInfo,
1293 F: MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable, Size: MemSize,
1294 BaseAlignment: SrcAlign);
1295
1296 MachineMemOperand *DstMMO = MF.getMachineMemOperand(
1297 PtrInfo: DstPtrInfo,
1298 F: MachineMemOperand::MOStore | MachineMemOperand::MODereferenceable,
1299 Size: MemSize, BaseAlignment: DstAlign);
1300
1301 const LLT PtrTy = MRI.getType(Reg: DstPtr);
1302 const LLT SizeTy = LLT::scalar(SizeInBits: PtrTy.getSizeInBits());
1303
1304 auto SizeConst = MIRBuilder.buildConstant(Res: SizeTy, Val: MemSize);
1305 MIRBuilder.buildMemCpy(DstPtr, SrcPtr, Size: SizeConst, DstMMO&: *DstMMO, SrcMMO&: *SrcMMO);
1306}
1307
1308Register CallLowering::ValueHandler::extendRegister(Register ValReg,
1309 const CCValAssign &VA,
1310 unsigned MaxSizeBits) {
1311 LLT LocTy{VA.getLocVT()};
1312 LLT ValTy{VA.getValVT()};
1313
1314 if (LocTy.getSizeInBits() == ValTy.getSizeInBits())
1315 return ValReg;
1316
1317 if (LocTy.isScalar() && MaxSizeBits && MaxSizeBits < LocTy.getSizeInBits()) {
1318 if (MaxSizeBits <= ValTy.getSizeInBits())
1319 return ValReg;
1320 LocTy = LLT::scalar(SizeInBits: MaxSizeBits);
1321 }
1322
1323 const LLT ValRegTy = MRI.getType(Reg: ValReg);
1324 if (ValRegTy.isPointer()) {
1325 // The x32 ABI wants to zero extend 32-bit pointers to 64-bit registers, so
1326 // we have to cast to do the extension.
1327 LLT IntPtrTy = LLT::scalar(SizeInBits: ValRegTy.getSizeInBits());
1328 ValReg = MIRBuilder.buildPtrToInt(Dst: IntPtrTy, Src: ValReg).getReg(Idx: 0);
1329 }
1330
1331 switch (VA.getLocInfo()) {
1332 default:
1333 break;
1334 case CCValAssign::Full:
1335 case CCValAssign::BCvt:
1336 // FIXME: bitconverting between vector types may or may not be a
1337 // nop in big-endian situations.
1338 return ValReg;
1339 case CCValAssign::AExt: {
1340 auto MIB = MIRBuilder.buildAnyExt(Res: LocTy, Op: ValReg);
1341 return MIB.getReg(Idx: 0);
1342 }
1343 case CCValAssign::SExt: {
1344 Register NewReg = MRI.createGenericVirtualRegister(Ty: LocTy);
1345 MIRBuilder.buildSExt(Res: NewReg, Op: ValReg);
1346 return NewReg;
1347 }
1348 case CCValAssign::ZExt: {
1349 Register NewReg = MRI.createGenericVirtualRegister(Ty: LocTy);
1350 MIRBuilder.buildZExt(Res: NewReg, Op: ValReg);
1351 return NewReg;
1352 }
1353 }
1354 llvm_unreachable("unable to extend register");
1355}
1356
1357void CallLowering::ValueAssigner::anchor() {}
1358
1359Register CallLowering::IncomingValueHandler::buildExtensionHint(
1360 const CCValAssign &VA, Register SrcReg, LLT NarrowTy) {
1361 switch (VA.getLocInfo()) {
1362 case CCValAssign::LocInfo::ZExt: {
1363 return MIRBuilder
1364 .buildAssertZExt(Res: MRI.cloneVirtualRegister(VReg: SrcReg), Op: SrcReg,
1365 Size: NarrowTy.getScalarSizeInBits())
1366 .getReg(Idx: 0);
1367 }
1368 case CCValAssign::LocInfo::SExt: {
1369 return MIRBuilder
1370 .buildAssertSExt(Res: MRI.cloneVirtualRegister(VReg: SrcReg), Op: SrcReg,
1371 Size: NarrowTy.getScalarSizeInBits())
1372 .getReg(Idx: 0);
1373 break;
1374 }
1375 default:
1376 return SrcReg;
1377 }
1378}
1379
1380/// Check if we can use a basic COPY instruction between the two types.
1381///
1382/// We're currently building on top of the infrastructure using MVT, which loses
1383/// pointer information in the CCValAssign. We accept copies from physical
1384/// registers that have been reported as integers if it's to an equivalent sized
1385/// pointer LLT.
1386static bool isCopyCompatibleType(LLT SrcTy, LLT DstTy) {
1387 if (SrcTy == DstTy)
1388 return true;
1389
1390 if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1391 return false;
1392
1393 SrcTy = SrcTy.getScalarType();
1394 DstTy = DstTy.getScalarType();
1395
1396 return (SrcTy.isPointer() && DstTy.isScalar()) ||
1397 (DstTy.isPointer() && SrcTy.isScalar());
1398}
1399
1400void CallLowering::IncomingValueHandler::assignValueToReg(
1401 Register ValVReg, Register PhysReg, const CCValAssign &VA) {
1402 const MVT LocVT = VA.getLocVT();
1403 const LLT LocTy(LocVT);
1404 const LLT RegTy = MRI.getType(Reg: ValVReg);
1405
1406 if (isCopyCompatibleType(SrcTy: RegTy, DstTy: LocTy)) {
1407 MIRBuilder.buildCopy(Res: ValVReg, Op: PhysReg);
1408 return;
1409 }
1410
1411 auto Copy = MIRBuilder.buildCopy(Res: LocTy, Op: PhysReg);
1412 auto Hint = buildExtensionHint(VA, SrcReg: Copy.getReg(Idx: 0), NarrowTy: RegTy);
1413 MIRBuilder.buildTrunc(Res: ValVReg, Op: Hint);
1414}
1415