1//===- lib/CodeGen/GlobalISel/GISelValueTracking.cpp --------------*- C++
2//*-===//
3//
4// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5// See https://llvm.org/LICENSE.txt for license information.
6// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7//
8//===----------------------------------------------------------------------===//
9//
10/// Provides analysis for querying information about KnownBits during GISel
11/// passes.
12//
13//===----------------------------------------------------------------------===//
14#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"
15#include "llvm/ADT/APFloat.h"
16#include "llvm/ADT/FloatingPointMode.h"
17#include "llvm/ADT/ScopeExit.h"
18#include "llvm/ADT/StringExtras.h"
19#include "llvm/Analysis/ValueTracking.h"
20#include "llvm/Analysis/VectorUtils.h"
21#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
22#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
23#include "llvm/CodeGen/GlobalISel/MachineFloatingPointPredicateUtils.h"
24#include "llvm/CodeGen/GlobalISel/Utils.h"
25#include "llvm/CodeGen/LowLevelTypeUtils.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineInstr.h"
28#include "llvm/CodeGen/MachineOperand.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/Register.h"
31#include "llvm/CodeGen/TargetLowering.h"
32#include "llvm/CodeGen/TargetOpcodes.h"
33#include "llvm/IR/ConstantRange.h"
34#include "llvm/IR/DerivedTypes.h"
35#include "llvm/IR/FMF.h"
36#include "llvm/InitializePasses.h"
37#include "llvm/MC/TargetRegistry.h"
38#include "llvm/Support/KnownBits.h"
39#include "llvm/Support/KnownFPClass.h"
40#include "llvm/Target/TargetMachine.h"
41
42#define DEBUG_TYPE "gisel-known-bits"
43
44using namespace llvm;
45using namespace MIPatternMatch;
46
47char llvm::GISelValueTrackingAnalysisLegacy::ID = 0;
48
49INITIALIZE_PASS(GISelValueTrackingAnalysisLegacy, DEBUG_TYPE,
50 "Analysis for ComputingKnownBits", false, true)
51
52GISelValueTracking::GISelValueTracking(MachineFunction &MF, unsigned MaxDepth)
53 : MF(MF), MRI(MF.getRegInfo()), TL(*MF.getSubtarget().getTargetLowering()),
54 DL(MF.getFunction().getDataLayout()), MaxDepth(MaxDepth) {}
55
56Align GISelValueTracking::computeKnownAlignment(Register R, unsigned Depth) {
57 const MachineInstr *MI = MRI.getVRegDef(Reg: R);
58 switch (MI->getOpcode()) {
59 case TargetOpcode::COPY:
60 return computeKnownAlignment(R: MI->getOperand(i: 1).getReg(), Depth);
61 case TargetOpcode::G_ASSERT_ALIGN: {
62 // TODO: Min with source
63 return Align(MI->getOperand(i: 2).getImm());
64 }
65 case TargetOpcode::G_FRAME_INDEX: {
66 int FrameIdx = MI->getOperand(i: 1).getIndex();
67 return MF.getFrameInfo().getObjectAlign(ObjectIdx: FrameIdx);
68 }
69 case TargetOpcode::G_INTRINSIC:
70 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
71 case TargetOpcode::G_INTRINSIC_CONVERGENT:
72 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
73 default:
74 return TL.computeKnownAlignForTargetInstr(Analysis&: *this, R, MRI, Depth: Depth + 1);
75 }
76}
77
78KnownBits GISelValueTracking::getKnownBits(Register R) {
79 const LLT Ty = MRI.getType(Reg: R);
80 // Since the number of lanes in a scalable vector is unknown at compile time,
81 // we track one bit which is implicitly broadcast to all lanes. This means
82 // that all lanes in a scalable vector are considered demanded.
83 APInt DemandedElts =
84 Ty.isFixedVector() ? APInt::getAllOnes(numBits: Ty.getNumElements()) : APInt(1, 1);
85 return getKnownBits(R, DemandedElts);
86}
87
88KnownBits GISelValueTracking::getKnownBits(Register R,
89 const APInt &DemandedElts,
90 unsigned Depth) {
91 KnownBits Known;
92 computeKnownBitsImpl(R, Known, DemandedElts, Depth);
93 return Known;
94}
95
96bool GISelValueTracking::signBitIsZero(Register R) {
97 LLT Ty = MRI.getType(Reg: R);
98 unsigned BitWidth = Ty.getScalarSizeInBits();
99 return maskedValueIsZero(Val: R, Mask: APInt::getSignMask(BitWidth));
100}
101
102bool GISelValueTracking::isKnownNeverZero(Register R, unsigned Depth) {
103 LLT Ty = MRI.getType(Reg: R);
104 const APInt ScalarDemandedElts(1, 1);
105 APInt DemandedElts = Ty.isFixedVector()
106 ? APInt::getAllOnes(numBits: Ty.getNumElements())
107 : ScalarDemandedElts;
108 return isKnownNeverZero(R, DemandedElts, Depth);
109}
110
111bool GISelValueTracking::isKnownNeverZero(Register R, const APInt &DemandedElts,
112 unsigned Depth) {
113 if (Depth >= getMaxDepth())
114 return false;
115
116 const APInt ScalarDemandedElts(1, 1);
117 MachineInstr &MI = *MRI.getVRegDef(Reg: R);
118
119 switch (MI.getOpcode()) {
120 default:
121 break;
122
123 case TargetOpcode::G_BUILD_VECTOR: {
124 for (const auto &[I, MO] : enumerate(First: drop_begin(RangeOrContainer: MI.operands()))) {
125 if (!DemandedElts[I])
126 continue;
127 if (!isKnownNeverZero(R: MO.getReg(), DemandedElts: ScalarDemandedElts, Depth: Depth + 1))
128 return false;
129 }
130 return true;
131 }
132
133 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
134 GExtractVectorElement &Extract = cast<GExtractVectorElement>(Val&: MI);
135 Register InVec = Extract.getVectorReg();
136 LLT VecTy = MRI.getType(Reg: InVec);
137 if (VecTy.isScalableVector())
138 break;
139 unsigned NumSrcElts = VecTy.getNumElements();
140 // An out-of-range constant index produces poison. Keep all lanes demanded,
141 // which is poison-safe and matches SelectionDAG's conservative behavior.
142 APInt DemandedSrcElts = APInt::getAllOnes(numBits: NumSrcElts);
143 if (auto Idx = getIConstantVRegVal(VReg: Extract.getIndexReg(), MRI)) {
144 if (Idx->ult(RHS: NumSrcElts))
145 DemandedSrcElts = APInt::getOneBitSet(numBits: NumSrcElts, BitNo: Idx->getZExtValue());
146 }
147 return isKnownNeverZero(R: InVec, DemandedElts: DemandedSrcElts, Depth: Depth + 1);
148 }
149
150 case TargetOpcode::G_SHUFFLE_VECTOR: {
151 GShuffleVector &Shuf = cast<GShuffleVector>(Val&: MI);
152 LLT SrcTy = MRI.getType(Reg: Shuf.getSrc1Reg());
153 if (SrcTy.isScalableVector())
154 break;
155 APInt DemandedLHS, DemandedRHS;
156 if (!getShuffleDemandedElts(SrcWidth: SrcTy.getNumElements(), Mask: Shuf.getMask(),
157 DemandedElts, DemandedLHS, DemandedRHS))
158 break;
159 if (!DemandedLHS.isZero() &&
160 !isKnownNeverZero(R: Shuf.getSrc1Reg(), DemandedElts: DemandedLHS, Depth: Depth + 1))
161 return false;
162 if (!DemandedRHS.isZero() &&
163 !isKnownNeverZero(R: Shuf.getSrc2Reg(), DemandedElts: DemandedRHS, Depth: Depth + 1))
164 return false;
165 return true;
166 }
167
168 case TargetOpcode::G_OR:
169 return isKnownNeverZero(R: MI.getOperand(i: 1).getReg(), DemandedElts,
170 Depth: Depth + 1) ||
171 isKnownNeverZero(R: MI.getOperand(i: 2).getReg(), DemandedElts, Depth: Depth + 1);
172
173 case TargetOpcode::G_SELECT:
174 return isKnownNeverZero(R: MI.getOperand(i: 2).getReg(), DemandedElts,
175 Depth: Depth + 1) &&
176 isKnownNeverZero(R: MI.getOperand(i: 3).getReg(), DemandedElts, Depth: Depth + 1);
177
178 case TargetOpcode::G_SHL: {
179 Register LHSReg = MI.getOperand(i: 1).getReg();
180 if (MI.getFlag(Flag: MachineInstr::NoSWrap) || MI.getFlag(Flag: MachineInstr::NoUWrap))
181 return isKnownNeverZero(R: LHSReg, DemandedElts, Depth: Depth + 1);
182 KnownBits ValKnown = getKnownBits(R: LHSReg, DemandedElts, Depth: Depth + 1);
183 if (ValKnown.One[0])
184 return true;
185 APInt MaxCnt =
186 getKnownBits(R: MI.getOperand(i: 2).getReg(), DemandedElts, Depth: Depth + 1)
187 .getMaxValue();
188 if (MaxCnt.ult(RHS: ValKnown.getBitWidth()) &&
189 !ValKnown.One.shl(ShiftAmt: MaxCnt).isZero())
190 return true;
191 break;
192 }
193 }
194
195 // Pass through this frame's Depth (not Depth+1) because we have not recursed
196 // into a child MI here: the fallback queries KnownBits for the same R.
197 return getKnownBits(R, DemandedElts, Depth).isNonZero();
198}
199
200APInt GISelValueTracking::getKnownZeroes(Register R) {
201 return getKnownBits(R).Zero;
202}
203
204APInt GISelValueTracking::getKnownOnes(Register R) {
205 return getKnownBits(R).One;
206}
207
208[[maybe_unused]] static void
209dumpResult(const MachineInstr &MI, const KnownBits &Known, unsigned Depth) {
210 dbgs() << "[" << Depth << "] Compute known bits: " << MI << "[" << Depth
211 << "] Computed for: " << MI << "[" << Depth << "] Known: 0x"
212 << toString(I: Known.Zero | Known.One, Radix: 16, Signed: false) << "\n"
213 << "[" << Depth << "] Zero: 0x" << toString(I: Known.Zero, Radix: 16, Signed: false)
214 << "\n"
215 << "[" << Depth << "] One: 0x" << toString(I: Known.One, Radix: 16, Signed: false)
216 << "\n";
217}
218
219/// Compute known bits for the intersection of \p Src0 and \p Src1
220void GISelValueTracking::computeKnownBitsMin(Register Src0, Register Src1,
221 KnownBits &Known,
222 const APInt &DemandedElts,
223 unsigned Depth) {
224 // Test src1 first, since we canonicalize simpler expressions to the RHS.
225 computeKnownBitsImpl(R: Src1, Known, DemandedElts, Depth);
226
227 // If we don't know any bits, early out.
228 if (Known.isUnknown())
229 return;
230
231 KnownBits Known2;
232 computeKnownBitsImpl(R: Src0, Known&: Known2, DemandedElts, Depth);
233
234 // Only known if known in both the LHS and RHS.
235 Known = Known.intersectWith(RHS: Known2);
236}
237
238// Bitfield extract is computed as (Src >> Offset) & Mask, where Mask is
239// created using Width. Use this function when the inputs are KnownBits
240// objects. TODO: Move this KnownBits.h if this is usable in more cases.
241static KnownBits extractBits(unsigned BitWidth, const KnownBits &SrcOpKnown,
242 const KnownBits &OffsetKnown,
243 const KnownBits &WidthKnown) {
244 KnownBits Mask(BitWidth);
245 Mask.Zero = APInt::getBitsSetFrom(
246 numBits: BitWidth, loBit: WidthKnown.getMaxValue().getLimitedValue(Limit: BitWidth));
247 Mask.One = APInt::getLowBitsSet(
248 numBits: BitWidth, loBitsSet: WidthKnown.getMinValue().getLimitedValue(Limit: BitWidth));
249 return KnownBits::lshr(LHS: SrcOpKnown, RHS: OffsetKnown) & Mask;
250}
251
252void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
253 const APInt &DemandedElts,
254 unsigned Depth) {
255 MachineInstr &MI = *MRI.getVRegDef(Reg: R);
256 unsigned Opcode = MI.getOpcode();
257 LLT DstTy = MRI.getType(Reg: R);
258
259 // Handle the case where this is called on a register that does not have a
260 // type constraint. For example, it may be post-ISel or this target might not
261 // preserve the type when early-selecting instructions.
262 if (!DstTy.isValid()) {
263 Known = KnownBits();
264 return;
265 }
266
267#ifndef NDEBUG
268 if (DstTy.isFixedVector()) {
269 assert(
270 DstTy.getNumElements() == DemandedElts.getBitWidth() &&
271 "DemandedElt width should equal the fixed vector number of elements");
272 } else {
273 assert(DemandedElts.getBitWidth() == 1 && DemandedElts == APInt(1, 1) &&
274 "DemandedElt width should be 1 for scalars or scalable vectors");
275 }
276#endif
277
278 unsigned BitWidth = DstTy.getScalarSizeInBits();
279 Known = KnownBits(BitWidth); // Don't know anything
280
281 // Depth may get bigger than max depth if it gets passed to a different
282 // GISelValueTracking object.
283 // This may happen when say a generic part uses a GISelValueTracking object
284 // with some max depth, but then we hit TL.computeKnownBitsForTargetInstr
285 // which creates a new GISelValueTracking object with a different and smaller
286 // depth. If we just check for equality, we would never exit if the depth
287 // that is passed down to the target specific GISelValueTracking object is
288 // already bigger than its max depth.
289 if (Depth >= getMaxDepth())
290 return;
291
292 if (!DemandedElts)
293 return; // No demanded elts, better to assume we don't know anything.
294
295 KnownBits Known2;
296
297 switch (Opcode) {
298 default:
299 TL.computeKnownBitsForTargetInstr(Analysis&: *this, R, Known, DemandedElts, MRI,
300 Depth);
301 break;
302 case TargetOpcode::G_BUILD_VECTOR: {
303 // Collect the known bits that are shared by every demanded vector element.
304 Known.Zero.setAllBits();
305 Known.One.setAllBits();
306 for (const auto &[I, MO] : enumerate(First: drop_begin(RangeOrContainer: MI.operands()))) {
307 if (!DemandedElts[I])
308 continue;
309
310 computeKnownBitsImpl(R: MO.getReg(), Known&: Known2, DemandedElts: APInt(1, 1), Depth: Depth + 1);
311
312 // Known bits are the values that are shared by every demanded element.
313 Known = Known.intersectWith(RHS: Known2);
314
315 // If we don't know any bits, early out.
316 if (Known.isUnknown())
317 break;
318 }
319 break;
320 }
321 case TargetOpcode::G_SPLAT_VECTOR: {
322 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts: APInt(1, 1),
323 Depth: Depth + 1);
324 // Implicitly truncate the bits to match the official semantics of
325 // G_SPLAT_VECTOR.
326 Known = Known.trunc(BitWidth);
327 break;
328 }
329 case TargetOpcode::COPY:
330 case TargetOpcode::G_PHI:
331 case TargetOpcode::PHI: {
332 Known.One = APInt::getAllOnes(numBits: BitWidth);
333 Known.Zero = APInt::getAllOnes(numBits: BitWidth);
334 // Destination registers should not have subregisters at this
335 // point of the pipeline, otherwise the main live-range will be
336 // defined more than once, which is against SSA.
337 assert(MI.getOperand(0).getSubReg() == 0 && "Is this code in SSA?");
338 // PHI's operand are a mix of registers and basic blocks interleaved.
339 // We only care about the register ones.
340 for (unsigned Idx = 1; Idx < MI.getNumOperands(); Idx += 2) {
341 const MachineOperand &Src = MI.getOperand(i: Idx);
342 Register SrcReg = Src.getReg();
343 LLT SrcTy = MRI.getType(Reg: SrcReg);
344 // Look through trivial copies and phis but don't look through trivial
345 // copies or phis of the form `%1:(s32) = OP %0:gpr32`, known-bits
346 // analysis is currently unable to determine the bit width of a
347 // register class.
348 //
349 // We can't use NoSubRegister by name as it's defined by each target but
350 // it's always defined to be 0 by tablegen.
351 if (SrcReg.isVirtual() && Src.getSubReg() == 0 /*NoSubRegister*/ &&
352 SrcTy.isValid()) {
353 APInt NowDemandedElts;
354 if (!SrcTy.isFixedVector()) {
355 NowDemandedElts = APInt(1, 1);
356 } else if (DstTy.isFixedVector() &&
357 SrcTy.getNumElements() == DstTy.getNumElements()) {
358 NowDemandedElts = DemandedElts;
359 } else {
360 NowDemandedElts = APInt::getAllOnes(numBits: SrcTy.getNumElements());
361 }
362
363 // For COPYs we don't do anything, don't increase the depth.
364 computeKnownBitsImpl(R: SrcReg, Known&: Known2, DemandedElts: NowDemandedElts,
365 Depth: Depth + (Opcode != TargetOpcode::COPY));
366 Known2 = Known2.anyextOrTrunc(BitWidth);
367 Known = Known.intersectWith(RHS: Known2);
368 // If we reach a point where we don't know anything
369 // just stop looking through the operands.
370 if (Known.isUnknown())
371 break;
372 } else {
373 // We know nothing.
374 Known = KnownBits(BitWidth);
375 break;
376 }
377 }
378 break;
379 }
380 case TargetOpcode::G_STEP_VECTOR: {
381 APInt Step = MI.getOperand(i: 1).getCImm()->getValue();
382
383 if (Step.isPowerOf2())
384 Known.Zero.setLowBits(Step.logBase2());
385
386 if (!isUIntN(N: BitWidth, x: DstTy.getElementCount().getKnownMinValue()))
387 break;
388
389 const APInt MinNumElts =
390 APInt(BitWidth, DstTy.getElementCount().getKnownMinValue());
391 const Function &F = getMachineFunction().getFunction();
392 bool Overflow;
393 const APInt MaxNumElts = getVScaleRange(F: &F, BitWidth)
394 .getUnsignedMax()
395 .umul_ov(RHS: MinNumElts, Overflow);
396 if (Overflow)
397 break;
398 const APInt MaxValue = (MaxNumElts - 1).umul_ov(RHS: Step, Overflow);
399 if (Overflow)
400 break;
401 Known.Zero.setHighBits(MaxValue.countl_zero());
402 break;
403 }
404 case TargetOpcode::G_VSCALE: {
405 const Function &F = getMachineFunction().getFunction();
406 const APInt &Multiplier = MI.getOperand(i: 1).getCImm()->getValue();
407 Known = getVScaleRange(F: &F, BitWidth).multiply(Other: Multiplier).toKnownBits();
408 break;
409 }
410 case TargetOpcode::G_CONSTANT: {
411 Known = KnownBits::makeConstant(C: MI.getOperand(i: 1).getCImm()->getValue());
412 break;
413 }
414 case TargetOpcode::G_FRAME_INDEX: {
415 int FrameIdx = MI.getOperand(i: 1).getIndex();
416 TL.computeKnownBitsForStackObjectPointer(
417 Known, MF, Alignment: MF.getFrameInfo().getObjectAlign(ObjectIdx: FrameIdx));
418 break;
419 }
420 case TargetOpcode::G_SUB: {
421 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
422 Depth: Depth + 1);
423 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: Known2, DemandedElts,
424 Depth: Depth + 1);
425 Known = KnownBits::sub(LHS: Known, RHS: Known2, NSW: MI.getFlag(Flag: MachineInstr::NoSWrap),
426 NUW: MI.getFlag(Flag: MachineInstr::NoUWrap));
427 break;
428 }
429 case TargetOpcode::G_XOR: {
430 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known, DemandedElts,
431 Depth: Depth + 1);
432 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: Known2, DemandedElts,
433 Depth: Depth + 1);
434
435 Known ^= Known2;
436 break;
437 }
438 case TargetOpcode::G_PTR_ADD: {
439 if (DstTy.isVector())
440 break;
441 // G_PTR_ADD is like G_ADD. FIXME: Is this true for all targets?
442 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 1).getReg());
443 if (DL.isNonIntegralAddressSpace(AddrSpace: Ty.getAddressSpace()))
444 break;
445 [[fallthrough]];
446 }
447 case TargetOpcode::G_ADD: {
448 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
449 Depth: Depth + 1);
450 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: Known2, DemandedElts,
451 Depth: Depth + 1);
452 Known = KnownBits::add(LHS: Known, RHS: Known2);
453 break;
454 }
455 case TargetOpcode::G_AND: {
456 // If either the LHS or the RHS are Zero, the result is zero.
457 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known, DemandedElts,
458 Depth: Depth + 1);
459 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: Known2, DemandedElts,
460 Depth: Depth + 1);
461
462 Known &= Known2;
463 break;
464 }
465 case TargetOpcode::G_OR: {
466 // If either the LHS or the RHS are Zero, the result is zero.
467 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known, DemandedElts,
468 Depth: Depth + 1);
469 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: Known2, DemandedElts,
470 Depth: Depth + 1);
471
472 Known |= Known2;
473 break;
474 }
475 case TargetOpcode::G_MUL: {
476 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known, DemandedElts,
477 Depth: Depth + 1);
478 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: Known2, DemandedElts,
479 Depth: Depth + 1);
480 Known = KnownBits::mul(LHS: Known, RHS: Known2);
481 break;
482 }
483 case TargetOpcode::G_UMULH: {
484 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known, DemandedElts,
485 Depth: Depth + 1);
486 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: Known2, DemandedElts,
487 Depth: Depth + 1);
488 Known = KnownBits::mulhu(LHS: Known, RHS: Known2);
489 break;
490 }
491 case TargetOpcode::G_SMULH: {
492 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known, DemandedElts,
493 Depth: Depth + 1);
494 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: Known2, DemandedElts,
495 Depth: Depth + 1);
496 Known = KnownBits::mulhs(LHS: Known, RHS: Known2);
497 break;
498 }
499 case TargetOpcode::G_CLMUL: {
500 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known, DemandedElts,
501 Depth: Depth + 1);
502 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: Known2, DemandedElts,
503 Depth: Depth + 1);
504 Known = KnownBits::clmul(LHS: Known, RHS: Known2);
505 break;
506 }
507 case TargetOpcode::G_UAVGFLOOR: {
508 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
509 Depth: Depth + 1);
510 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: Known2, DemandedElts,
511 Depth: Depth + 1);
512 Known = KnownBits::avgFloorU(LHS: Known, RHS: Known2);
513 break;
514 }
515 case TargetOpcode::G_UAVGCEIL: {
516 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
517 Depth: Depth + 1);
518 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: Known2, DemandedElts,
519 Depth: Depth + 1);
520 Known = KnownBits::avgCeilU(LHS: Known, RHS: Known2);
521 break;
522 }
523 case TargetOpcode::G_SAVGFLOOR: {
524 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
525 Depth: Depth + 1);
526 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: Known2, DemandedElts,
527 Depth: Depth + 1);
528 Known = KnownBits::avgFloorS(LHS: Known, RHS: Known2);
529 break;
530 }
531 case TargetOpcode::G_SAVGCEIL: {
532 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
533 Depth: Depth + 1);
534 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: Known2, DemandedElts,
535 Depth: Depth + 1);
536 Known = KnownBits::avgCeilS(LHS: Known, RHS: Known2);
537 break;
538 }
539 case TargetOpcode::G_ABDU: {
540 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known, DemandedElts,
541 Depth: Depth + 1);
542 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: Known2, DemandedElts,
543 Depth: Depth + 1);
544 Known = KnownBits::abdu(LHS: Known, RHS: Known2);
545 break;
546 }
547 case TargetOpcode::G_ABDS: {
548 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known, DemandedElts,
549 Depth: Depth + 1);
550 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: Known2, DemandedElts,
551 Depth: Depth + 1);
552 Known = KnownBits::abds(LHS: Known, RHS: Known2);
553
554 unsigned SignBits1 =
555 computeNumSignBits(R: MI.getOperand(i: 2).getReg(), DemandedElts, Depth: Depth + 1);
556 if (SignBits1 == 1) {
557 break;
558 }
559 unsigned SignBits0 =
560 computeNumSignBits(R: MI.getOperand(i: 1).getReg(), DemandedElts, Depth: Depth + 1);
561
562 Known.Zero.setHighBits(std::min(a: SignBits0, b: SignBits1) - 1);
563 break;
564 }
565 case TargetOpcode::G_SADDSAT: {
566 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
567 Depth: Depth + 1);
568 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: Known2, DemandedElts,
569 Depth: Depth + 1);
570 Known = KnownBits::sadd_sat(LHS: Known, RHS: Known2);
571 break;
572 }
573 case TargetOpcode::G_UADDSAT: {
574 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
575 Depth: Depth + 1);
576 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: Known2, DemandedElts,
577 Depth: Depth + 1);
578 Known = KnownBits::uadd_sat(LHS: Known, RHS: Known2);
579 break;
580 }
581 case TargetOpcode::G_SSUBSAT: {
582 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
583 Depth: Depth + 1);
584 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: Known2, DemandedElts,
585 Depth: Depth + 1);
586 Known = KnownBits::ssub_sat(LHS: Known, RHS: Known2);
587 break;
588 }
589 case TargetOpcode::G_USUBSAT: {
590 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
591 Depth: Depth + 1);
592 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: Known2, DemandedElts,
593 Depth: Depth + 1);
594 Known = KnownBits::usub_sat(LHS: Known, RHS: Known2);
595 break;
596 }
597 case TargetOpcode::G_UDIV: {
598 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
599 Depth: Depth + 1);
600 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: Known2, DemandedElts,
601 Depth: Depth + 1);
602 Known = KnownBits::udiv(LHS: Known, RHS: Known2,
603 Exact: MI.getFlag(Flag: MachineInstr::MIFlag::IsExact));
604 break;
605 }
606 case TargetOpcode::G_SDIV: {
607 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
608 Depth: Depth + 1);
609 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: Known2, DemandedElts,
610 Depth: Depth + 1);
611 Known = KnownBits::sdiv(LHS: Known, RHS: Known2,
612 Exact: MI.getFlag(Flag: MachineInstr::MIFlag::IsExact));
613 break;
614 }
615 case TargetOpcode::G_UREM: {
616 KnownBits LHSKnown(Known.getBitWidth());
617 KnownBits RHSKnown(Known.getBitWidth());
618
619 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: LHSKnown, DemandedElts,
620 Depth: Depth + 1);
621 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: RHSKnown, DemandedElts,
622 Depth: Depth + 1);
623
624 Known = KnownBits::urem(LHS: LHSKnown, RHS: RHSKnown);
625 break;
626 }
627 case TargetOpcode::G_SREM: {
628 KnownBits LHSKnown(Known.getBitWidth());
629 KnownBits RHSKnown(Known.getBitWidth());
630
631 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: LHSKnown, DemandedElts,
632 Depth: Depth + 1);
633 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: RHSKnown, DemandedElts,
634 Depth: Depth + 1);
635
636 Known = KnownBits::srem(LHS: LHSKnown, RHS: RHSKnown);
637 break;
638 }
639 case TargetOpcode::G_SELECT: {
640 computeKnownBitsMin(Src0: MI.getOperand(i: 2).getReg(), Src1: MI.getOperand(i: 3).getReg(),
641 Known, DemandedElts, Depth: Depth + 1);
642 break;
643 }
644 case TargetOpcode::G_SMIN: {
645 // TODO: Handle clamp pattern with number of sign bits
646 KnownBits KnownRHS;
647 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
648 Depth: Depth + 1);
649 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: KnownRHS, DemandedElts,
650 Depth: Depth + 1);
651 Known = KnownBits::smin(LHS: Known, RHS: KnownRHS);
652 break;
653 }
654 case TargetOpcode::G_SMAX: {
655 // TODO: Handle clamp pattern with number of sign bits
656 KnownBits KnownRHS;
657 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
658 Depth: Depth + 1);
659 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: KnownRHS, DemandedElts,
660 Depth: Depth + 1);
661 Known = KnownBits::smax(LHS: Known, RHS: KnownRHS);
662 break;
663 }
664 case TargetOpcode::G_UMIN: {
665 KnownBits KnownRHS;
666 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
667 Depth: Depth + 1);
668 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: KnownRHS, DemandedElts,
669 Depth: Depth + 1);
670 Known = KnownBits::umin(LHS: Known, RHS: KnownRHS);
671 break;
672 }
673 case TargetOpcode::G_UMAX: {
674 KnownBits KnownRHS;
675 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
676 Depth: Depth + 1);
677 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: KnownRHS, DemandedElts,
678 Depth: Depth + 1);
679 Known = KnownBits::umax(LHS: Known, RHS: KnownRHS);
680 break;
681 }
682 case TargetOpcode::G_FCMP:
683 case TargetOpcode::G_ICMP: {
684 if (DstTy.isVector())
685 break;
686 if (TL.getBooleanContents(isVec: DstTy.isVector(),
687 isFloat: Opcode == TargetOpcode::G_FCMP) ==
688 TargetLowering::ZeroOrOneBooleanContent &&
689 BitWidth > 1)
690 Known.Zero.setBitsFrom(1);
691 break;
692 }
693 case TargetOpcode::G_SEXT: {
694 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
695 Depth: Depth + 1);
696 // If the sign bit is known to be zero or one, then sext will extend
697 // it to the top bits, else it will just zext.
698 Known = Known.sext(BitWidth);
699 break;
700 }
701 case TargetOpcode::G_ASSERT_SEXT:
702 case TargetOpcode::G_SEXT_INREG: {
703 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
704 Depth: Depth + 1);
705 Known = Known.sextInReg(SrcBitWidth: MI.getOperand(i: 2).getImm());
706 break;
707 }
708 case TargetOpcode::G_ANYEXT: {
709 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
710 Depth: Depth + 1);
711 Known = Known.anyext(BitWidth);
712 break;
713 }
714 case TargetOpcode::G_LOAD: {
715 const MachineMemOperand *MMO = *MI.memoperands_begin();
716 KnownBits KnownRange(MMO->getMemoryType().getScalarSizeInBits());
717 if (const MDNode *Ranges = MMO->getRanges())
718 computeKnownBitsFromRangeMetadata(Ranges: *Ranges, Known&: KnownRange);
719 Known = KnownRange.anyext(BitWidth: Known.getBitWidth());
720 break;
721 }
722 case TargetOpcode::G_SEXTLOAD:
723 case TargetOpcode::G_ZEXTLOAD: {
724 if (DstTy.isVector())
725 break;
726 const MachineMemOperand *MMO = *MI.memoperands_begin();
727 KnownBits KnownRange(MMO->getMemoryType().getScalarSizeInBits());
728 if (const MDNode *Ranges = MMO->getRanges())
729 computeKnownBitsFromRangeMetadata(Ranges: *Ranges, Known&: KnownRange);
730 Known = Opcode == TargetOpcode::G_SEXTLOAD
731 ? KnownRange.sext(BitWidth: Known.getBitWidth())
732 : KnownRange.zext(BitWidth: Known.getBitWidth());
733 break;
734 }
735 case TargetOpcode::G_ASHR: {
736 KnownBits LHSKnown, RHSKnown;
737 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: LHSKnown, DemandedElts,
738 Depth: Depth + 1);
739 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: RHSKnown, DemandedElts,
740 Depth: Depth + 1);
741 Known = KnownBits::ashr(LHS: LHSKnown, RHS: RHSKnown);
742 break;
743 }
744 case TargetOpcode::G_LSHR: {
745 KnownBits LHSKnown, RHSKnown;
746 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: LHSKnown, DemandedElts,
747 Depth: Depth + 1);
748 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: RHSKnown, DemandedElts,
749 Depth: Depth + 1);
750 Known = KnownBits::lshr(LHS: LHSKnown, RHS: RHSKnown);
751 break;
752 }
753 case TargetOpcode::G_SHL: {
754 KnownBits LHSKnown, RHSKnown;
755 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: LHSKnown, DemandedElts,
756 Depth: Depth + 1);
757 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: RHSKnown, DemandedElts,
758 Depth: Depth + 1);
759 Known = KnownBits::shl(LHS: LHSKnown, RHS: RHSKnown);
760 break;
761 }
762 case TargetOpcode::G_ROTL:
763 case TargetOpcode::G_ROTR: {
764 auto MaybeAmtOp =
765 isConstantOrConstantSplatVector(Def: MI.getOperand(i: 2).getReg(), MRI);
766 if (!MaybeAmtOp)
767 break;
768
769 Register SrcReg = MI.getOperand(i: 1).getReg();
770 computeKnownBitsImpl(R: SrcReg, Known, DemandedElts, Depth: Depth + 1);
771
772 unsigned Amt = MaybeAmtOp->urem(RHS: BitWidth);
773
774 // Canonicalize to ROTR.
775 if (Opcode == TargetOpcode::G_ROTL)
776 Amt = BitWidth - Amt;
777
778 Known.Zero = Known.Zero.rotr(rotateAmt: Amt);
779 Known.One = Known.One.rotr(rotateAmt: Amt);
780 break;
781 }
782 case TargetOpcode::G_FSHL:
783 case TargetOpcode::G_FSHR: {
784 auto MaybeAmtOp =
785 isConstantOrConstantSplatVector(Def: MI.getOperand(i: 3).getReg(), MRI);
786 if (!MaybeAmtOp)
787 break;
788
789 const APInt Amt = *MaybeAmtOp;
790 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known, DemandedElts,
791 Depth: Depth + 1);
792 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: Known2, DemandedElts,
793 Depth: Depth + 1);
794 Known = Opcode == TargetOpcode::G_FSHL
795 ? KnownBits::fshl(LHS: Known, RHS: Known2, Amt)
796 : KnownBits::fshr(LHS: Known, RHS: Known2, Amt);
797 break;
798 }
799 case TargetOpcode::G_INTTOPTR:
800 case TargetOpcode::G_PTRTOINT:
801 if (DstTy.isVector())
802 break;
803 // Fall through and handle them the same as zext/trunc.
804 [[fallthrough]];
805 case TargetOpcode::G_ZEXT:
806 case TargetOpcode::G_TRUNC: {
807 Register SrcReg = MI.getOperand(i: 1).getReg();
808 computeKnownBitsImpl(R: SrcReg, Known, DemandedElts, Depth: Depth + 1);
809 Known = Known.zextOrTrunc(BitWidth);
810 break;
811 }
812 case TargetOpcode::G_TRUNC_SSAT_S: {
813 Register SrcReg = MI.getOperand(i: 1).getReg();
814 computeKnownBitsImpl(R: SrcReg, Known, DemandedElts, Depth: Depth + 1);
815 Known = Known.truncSSat(BitWidth);
816 break;
817 }
818 case TargetOpcode::G_TRUNC_SSAT_U: {
819 Register SrcReg = MI.getOperand(i: 1).getReg();
820 computeKnownBitsImpl(R: SrcReg, Known, DemandedElts, Depth: Depth + 1);
821 Known = Known.truncSSatU(BitWidth);
822 break;
823 }
824 case TargetOpcode::G_TRUNC_USAT_U: {
825 Register SrcReg = MI.getOperand(i: 1).getReg();
826 computeKnownBitsImpl(R: SrcReg, Known, DemandedElts, Depth: Depth + 1);
827 Known = Known.truncUSat(BitWidth);
828 break;
829 }
830 case TargetOpcode::G_ASSERT_ZEXT: {
831 Register SrcReg = MI.getOperand(i: 1).getReg();
832 computeKnownBitsImpl(R: SrcReg, Known, DemandedElts, Depth: Depth + 1);
833
834 unsigned SrcBitWidth = MI.getOperand(i: 2).getImm();
835 assert(SrcBitWidth && "SrcBitWidth can't be zero");
836 APInt InMask = APInt::getLowBitsSet(numBits: BitWidth, loBitsSet: SrcBitWidth);
837 Known.Zero |= (~InMask);
838 Known.One &= (~Known.Zero);
839 break;
840 }
841 case TargetOpcode::G_ASSERT_ALIGN: {
842 int64_t LogOfAlign = Log2_64(Value: MI.getOperand(i: 2).getImm());
843
844 // TODO: Should use maximum with source
845 // If a node is guaranteed to be aligned, set low zero bits accordingly as
846 // well as clearing one bits.
847 Known.Zero.setLowBits(LogOfAlign);
848 Known.One.clearLowBits(loBits: LogOfAlign);
849 break;
850 }
851 case TargetOpcode::G_MERGE_VALUES: {
852 unsigned NumOps = MI.getNumOperands();
853 unsigned OpSize = MRI.getType(Reg: MI.getOperand(i: 1).getReg()).getSizeInBits();
854
855 for (unsigned I = 0; I != NumOps - 1; ++I) {
856 KnownBits SrcOpKnown;
857 computeKnownBitsImpl(R: MI.getOperand(i: I + 1).getReg(), Known&: SrcOpKnown,
858 DemandedElts, Depth: Depth + 1);
859 Known.insertBits(SubBits: SrcOpKnown, BitPosition: I * OpSize);
860 }
861 break;
862 }
863 case TargetOpcode::G_UNMERGE_VALUES: {
864 unsigned NumOps = MI.getNumOperands();
865 Register SrcReg = MI.getOperand(i: NumOps - 1).getReg();
866 LLT SrcTy = MRI.getType(Reg: SrcReg);
867
868 if (SrcTy.isVector() && SrcTy.getScalarType() != DstTy.getScalarType())
869 return; // TODO: Handle vector->subelement unmerges
870
871 // Figure out the result operand index
872 unsigned DstIdx = MI.findRegisterDefOperandIdx(Reg: R, TRI: nullptr);
873
874 APInt SubDemandedElts = DemandedElts;
875 if (SrcTy.isVector()) {
876 unsigned DstLanes = DstTy.isVector() ? DstTy.getNumElements() : 1;
877 SubDemandedElts =
878 DemandedElts.zext(width: SrcTy.getNumElements()).shl(shiftAmt: DstIdx * DstLanes);
879 }
880
881 KnownBits SrcOpKnown;
882 computeKnownBitsImpl(R: SrcReg, Known&: SrcOpKnown, DemandedElts: SubDemandedElts, Depth: Depth + 1);
883
884 if (SrcTy.isVector())
885 Known = std::move(SrcOpKnown);
886 else
887 Known = SrcOpKnown.extractBits(NumBits: BitWidth, BitPosition: BitWidth * DstIdx);
888 break;
889 }
890 case TargetOpcode::G_BSWAP: {
891 Register SrcReg = MI.getOperand(i: 1).getReg();
892 computeKnownBitsImpl(R: SrcReg, Known, DemandedElts, Depth: Depth + 1);
893 Known = Known.byteSwap();
894 break;
895 }
896 case TargetOpcode::G_BITREVERSE: {
897 Register SrcReg = MI.getOperand(i: 1).getReg();
898 computeKnownBitsImpl(R: SrcReg, Known, DemandedElts, Depth: Depth + 1);
899 Known = Known.reverseBits();
900 break;
901 }
902 case TargetOpcode::G_CTPOP: {
903 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: Known2, DemandedElts,
904 Depth: Depth + 1);
905 // We can bound the space the count needs. Also, bits known to be zero
906 // can't contribute to the population.
907 unsigned BitsPossiblySet = Known2.countMaxPopulation();
908 unsigned LowBits = llvm::bit_width(Value: BitsPossiblySet);
909 Known.Zero.setBitsFrom(LowBits);
910 // TODO: we could bound Known.One using the lower bound on the number of
911 // bits which might be set provided by popcnt KnownOne2.
912 break;
913 }
914 case TargetOpcode::G_UBFX: {
915 KnownBits SrcOpKnown, OffsetKnown, WidthKnown;
916 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: SrcOpKnown, DemandedElts,
917 Depth: Depth + 1);
918 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: OffsetKnown, DemandedElts,
919 Depth: Depth + 1);
920 computeKnownBitsImpl(R: MI.getOperand(i: 3).getReg(), Known&: WidthKnown, DemandedElts,
921 Depth: Depth + 1);
922 Known = extractBits(BitWidth, SrcOpKnown, OffsetKnown, WidthKnown);
923 break;
924 }
925 case TargetOpcode::G_SBFX: {
926 KnownBits SrcOpKnown, OffsetKnown, WidthKnown;
927 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: SrcOpKnown, DemandedElts,
928 Depth: Depth + 1);
929 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: OffsetKnown, DemandedElts,
930 Depth: Depth + 1);
931 computeKnownBitsImpl(R: MI.getOperand(i: 3).getReg(), Known&: WidthKnown, DemandedElts,
932 Depth: Depth + 1);
933 OffsetKnown = OffsetKnown.sext(BitWidth);
934 WidthKnown = WidthKnown.sext(BitWidth);
935 Known = extractBits(BitWidth, SrcOpKnown, OffsetKnown, WidthKnown);
936 // Sign extend the extracted value using shift left and arithmetic shift
937 // right.
938 KnownBits ExtKnown = KnownBits::makeConstant(C: APInt(BitWidth, BitWidth));
939 KnownBits ShiftKnown = KnownBits::sub(LHS: ExtKnown, RHS: WidthKnown);
940 Known = KnownBits::ashr(LHS: KnownBits::shl(LHS: Known, RHS: ShiftKnown), RHS: ShiftKnown);
941 break;
942 }
943 case TargetOpcode::G_UADDO:
944 case TargetOpcode::G_UADDE:
945 case TargetOpcode::G_SADDO:
946 case TargetOpcode::G_SADDE: {
947 if (MI.getOperand(i: 1).getReg() == R) {
948 // If we know the result of a compare has the top bits zero, use this
949 // info.
950 if (TL.getBooleanContents(isVec: DstTy.isVector(), isFloat: false) ==
951 TargetLowering::ZeroOrOneBooleanContent &&
952 BitWidth > 1)
953 Known.Zero.setBitsFrom(1);
954 break;
955 }
956
957 assert(MI.getOperand(0).getReg() == R &&
958 "We only compute knownbits for the sum here.");
959 // With [US]ADDE, a carry bit may be added in.
960 KnownBits Carry(1);
961 if (Opcode == TargetOpcode::G_UADDE || Opcode == TargetOpcode::G_SADDE) {
962 computeKnownBitsImpl(R: MI.getOperand(i: 4).getReg(), Known&: Carry, DemandedElts,
963 Depth: Depth + 1);
964 // Carry has bit width 1
965 Carry = Carry.trunc(BitWidth: 1);
966 } else {
967 Carry.setAllZero();
968 }
969
970 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known, DemandedElts,
971 Depth: Depth + 1);
972 computeKnownBitsImpl(R: MI.getOperand(i: 3).getReg(), Known&: Known2, DemandedElts,
973 Depth: Depth + 1);
974 Known = KnownBits::computeForAddCarry(LHS: Known, RHS: Known2, Carry);
975 break;
976 }
977 case TargetOpcode::G_USUBO:
978 case TargetOpcode::G_USUBE:
979 case TargetOpcode::G_SSUBO:
980 case TargetOpcode::G_SSUBE:
981 case TargetOpcode::G_UMULO:
982 case TargetOpcode::G_SMULO: {
983 if (MI.getOperand(i: 1).getReg() == R) {
984 // If we know the result of a compare has the top bits zero, use this
985 // info.
986 if (TL.getBooleanContents(isVec: DstTy.isVector(), isFloat: false) ==
987 TargetLowering::ZeroOrOneBooleanContent &&
988 BitWidth > 1)
989 Known.Zero.setBitsFrom(1);
990 }
991 break;
992 }
993 case TargetOpcode::G_CTTZ:
994 case TargetOpcode::G_CTTZ_ZERO_POISON: {
995 KnownBits SrcOpKnown;
996 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: SrcOpKnown, DemandedElts,
997 Depth: Depth + 1);
998 // If we have a known 1, its position is our upper bound
999 unsigned PossibleTZ = SrcOpKnown.countMaxTrailingZeros();
1000 unsigned LowBits = llvm::bit_width(Value: PossibleTZ);
1001 Known.Zero.setBitsFrom(LowBits);
1002 break;
1003 }
1004 case TargetOpcode::G_CTLZ:
1005 case TargetOpcode::G_CTLZ_ZERO_POISON: {
1006 KnownBits SrcOpKnown;
1007 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: SrcOpKnown, DemandedElts,
1008 Depth: Depth + 1);
1009 // If we have a known 1, its position is our upper bound.
1010 unsigned PossibleLZ = SrcOpKnown.countMaxLeadingZeros();
1011 unsigned LowBits = llvm::bit_width(Value: PossibleLZ);
1012 Known.Zero.setBitsFrom(LowBits);
1013 break;
1014 }
1015 case TargetOpcode::G_CTLS: {
1016 Register Reg = MI.getOperand(i: 1).getReg();
1017 unsigned MinRedundantSignBits = computeNumSignBits(R: Reg, Depth: Depth + 1) - 1;
1018
1019 unsigned MaxUpperRedundantSignBits = MRI.getType(Reg).getScalarSizeInBits();
1020
1021 ConstantRange Range(APInt(BitWidth, MinRedundantSignBits),
1022 APInt(BitWidth, MaxUpperRedundantSignBits));
1023
1024 Known = Range.toKnownBits();
1025 break;
1026 }
1027 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1028 GExtractVectorElement &Extract = cast<GExtractVectorElement>(Val&: MI);
1029 Register InVec = Extract.getVectorReg();
1030 Register EltNo = Extract.getIndexReg();
1031
1032 auto ConstEltNo = getIConstantVRegVal(VReg: EltNo, MRI);
1033
1034 LLT VecVT = MRI.getType(Reg: InVec);
1035 // computeKnownBits not yet implemented for scalable vectors.
1036 if (VecVT.isScalableVector())
1037 break;
1038
1039 const unsigned EltBitWidth = VecVT.getScalarSizeInBits();
1040 const unsigned NumSrcElts = VecVT.getNumElements();
1041 // A return type different from the vector's element type may lead to
1042 // issues with pattern selection. Bail out to avoid that.
1043 if (BitWidth > EltBitWidth)
1044 break;
1045
1046 Known.Zero.setAllBits();
1047 Known.One.setAllBits();
1048
1049 // If we know the element index, just demand that vector element, else for
1050 // an unknown element index, ignore DemandedElts and demand them all.
1051 APInt DemandedSrcElts = APInt::getAllOnes(numBits: NumSrcElts);
1052 if (ConstEltNo && ConstEltNo->ult(RHS: NumSrcElts))
1053 DemandedSrcElts =
1054 APInt::getOneBitSet(numBits: NumSrcElts, BitNo: ConstEltNo->getZExtValue());
1055
1056 computeKnownBitsImpl(R: InVec, Known, DemandedElts: DemandedSrcElts, Depth: Depth + 1);
1057 break;
1058 }
1059 case TargetOpcode::G_INSERT_VECTOR_ELT: {
1060 GInsertVectorElement &Insert = cast<GInsertVectorElement>(Val&: MI);
1061 Register InVec = Insert.getVectorReg();
1062 Register InVal = Insert.getElementReg();
1063 Register EltNo = Insert.getIndexReg();
1064 LLT VecVT = MRI.getType(Reg: InVec);
1065
1066 if (VecVT.isScalableVector())
1067 break;
1068
1069 auto ConstEltNo = getIConstantVRegVal(VReg: EltNo, MRI);
1070 unsigned NumElts = VecVT.getNumElements();
1071
1072 bool DemandedVal = true;
1073 APInt DemandedVecElts = DemandedElts;
1074 if (ConstEltNo && ConstEltNo->ult(RHS: NumElts)) {
1075 unsigned EltIdx = ConstEltNo->getZExtValue();
1076 DemandedVal = !!DemandedElts[EltIdx];
1077 DemandedVecElts.clearBit(BitPosition: EltIdx);
1078 }
1079 Known.setAllConflict();
1080 if (DemandedVal) {
1081 computeKnownBitsImpl(R: InVal, Known&: Known2, DemandedElts: APInt(1, 1), Depth: Depth + 1);
1082 Known = Known.intersectWith(RHS: Known2.zextOrTrunc(BitWidth));
1083 }
1084 if (!!DemandedVecElts) {
1085 computeKnownBitsImpl(R: InVec, Known&: Known2, DemandedElts: DemandedVecElts, Depth: Depth + 1);
1086 Known = Known.intersectWith(RHS: Known2);
1087 }
1088 break;
1089 }
1090 case TargetOpcode::G_INSERT_SUBVECTOR: {
1091 GInsertSubvector &Insert = cast<GInsertSubvector>(Val&: MI);
1092 Register Src = Insert.getBigVec();
1093 Register Sub = Insert.getSubVec();
1094 uint64_t Idx = Insert.getIndexImm();
1095 LLT SrcTy = MRI.getType(Reg: Src);
1096 LLT SubTy = MRI.getType(Reg: Sub);
1097 APInt DemandedSubElts;
1098 APInt DemandedSrcElts;
1099
1100 if (SrcTy.isScalableVector()) {
1101 DemandedSubElts = SubTy.isScalableVector()
1102 ? APInt(1, 1)
1103 : APInt::getAllOnes(numBits: SubTy.getNumElements());
1104 DemandedSrcElts = APInt(1, 1);
1105 } else {
1106 unsigned NumSubElts = SubTy.getNumElements();
1107 DemandedSubElts = DemandedElts.extractBits(numBits: NumSubElts, bitPosition: Idx);
1108 DemandedSrcElts = DemandedElts;
1109 DemandedSrcElts.clearBits(LoBit: Idx, HiBit: Idx + NumSubElts);
1110 }
1111
1112 Known.setAllConflict();
1113 if (!!DemandedSubElts) {
1114 computeKnownBitsImpl(R: Sub, Known&: Known2, DemandedElts: DemandedSubElts, Depth: Depth + 1);
1115 Known = Known.intersectWith(RHS: Known2);
1116 if (Known.isUnknown())
1117 break;
1118 }
1119
1120 if (!!DemandedSrcElts) {
1121 computeKnownBitsImpl(R: Src, Known&: Known2, DemandedElts: DemandedSrcElts, Depth: Depth + 1);
1122 Known = Known.intersectWith(RHS: Known2);
1123 }
1124
1125 break;
1126 }
1127 case TargetOpcode::G_EXTRACT_SUBVECTOR: {
1128 Register SrcReg = MI.getOperand(i: 1).getReg();
1129 LLT SrcTy = MRI.getType(Reg: SrcReg);
1130 APInt DemandedSrcElts;
1131 if (SrcTy.isScalableVector()) {
1132 DemandedSrcElts = APInt(1, 1);
1133 } else {
1134 uint64_t Idx = MI.getOperand(i: 2).getImm();
1135 unsigned NumSrcElts = SrcTy.getNumElements();
1136 DemandedSrcElts = DemandedElts.zext(width: NumSrcElts).shl(shiftAmt: Idx);
1137 }
1138 computeKnownBitsImpl(R: SrcReg, Known, DemandedElts: DemandedSrcElts, Depth: Depth + 1);
1139 break;
1140 }
1141 case TargetOpcode::G_SHUFFLE_VECTOR: {
1142 APInt DemandedLHS, DemandedRHS;
1143 // Collect the known bits that are shared by every vector element referenced
1144 // by the shuffle.
1145 unsigned NumElts = MRI.getType(Reg: MI.getOperand(i: 1).getReg()).getNumElements();
1146 if (!getShuffleDemandedElts(SrcWidth: NumElts, Mask: MI.getOperand(i: 3).getShuffleMask(),
1147 DemandedElts, DemandedLHS, DemandedRHS))
1148 break;
1149
1150 // Known bits are the values that are shared by every demanded element.
1151 Known.Zero.setAllBits();
1152 Known.One.setAllBits();
1153 if (!!DemandedLHS) {
1154 computeKnownBitsImpl(R: MI.getOperand(i: 1).getReg(), Known&: Known2, DemandedElts: DemandedLHS,
1155 Depth: Depth + 1);
1156 Known = Known.intersectWith(RHS: Known2);
1157 }
1158 // If we don't know any bits, early out.
1159 if (Known.isUnknown())
1160 break;
1161 if (!!DemandedRHS) {
1162 computeKnownBitsImpl(R: MI.getOperand(i: 2).getReg(), Known&: Known2, DemandedElts: DemandedRHS,
1163 Depth: Depth + 1);
1164 Known = Known.intersectWith(RHS: Known2);
1165 }
1166 break;
1167 }
1168 case TargetOpcode::G_CONCAT_VECTORS: {
1169 if (MRI.getType(Reg: MI.getOperand(i: 0).getReg()).isScalableVector())
1170 break;
1171 // Split DemandedElts and test each of the demanded subvectors.
1172 Known.Zero.setAllBits();
1173 Known.One.setAllBits();
1174 unsigned NumSubVectorElts =
1175 MRI.getType(Reg: MI.getOperand(i: 1).getReg()).getNumElements();
1176
1177 for (const auto &[I, MO] : enumerate(First: drop_begin(RangeOrContainer: MI.operands()))) {
1178 APInt DemandedSub =
1179 DemandedElts.extractBits(numBits: NumSubVectorElts, bitPosition: I * NumSubVectorElts);
1180 if (!!DemandedSub) {
1181 computeKnownBitsImpl(R: MO.getReg(), Known&: Known2, DemandedElts: DemandedSub, Depth: Depth + 1);
1182
1183 Known = Known.intersectWith(RHS: Known2);
1184 }
1185 // If we don't know any bits, early out.
1186 if (Known.isUnknown())
1187 break;
1188 }
1189 break;
1190 }
1191 case TargetOpcode::G_ABS: {
1192 Register SrcReg = MI.getOperand(i: 1).getReg();
1193 computeKnownBitsImpl(R: SrcReg, Known, DemandedElts, Depth: Depth + 1);
1194 Known = Known.abs();
1195 Known.Zero.setHighBits(computeNumSignBits(R: SrcReg, DemandedElts, Depth: Depth + 1) -
1196 1);
1197 break;
1198 }
1199 }
1200
1201 LLVM_DEBUG(dumpResult(MI, Known, Depth));
1202}
1203
1204void GISelValueTracking::computeKnownFPClass(Register R, KnownFPClass &Known,
1205 FPClassTest InterestedClasses,
1206 unsigned Depth) {
1207 LLT Ty = MRI.getType(Reg: R);
1208 APInt DemandedElts =
1209 Ty.isFixedVector() ? APInt::getAllOnes(numBits: Ty.getNumElements()) : APInt(1, 1);
1210 computeKnownFPClass(R, DemandedElts, InterestedClasses, Known, Depth);
1211}
1212
1213/// Return true if this value is known to be the fractional part x - floor(x),
1214/// which lies in [0, 1). This implies the value cannot introduce overflow in a
1215/// fmul when the other operand is known finite.
1216static bool isAbsoluteValueULEOne(Register R, const MachineRegisterInfo &MRI) {
1217 using namespace MIPatternMatch;
1218 Register SubX;
1219 return mi_match(R, MRI, P: m_GFSub(L: m_Reg(R&: SubX), R: m_GFFloor(Src: m_DeferredReg(R&: SubX))));
1220}
1221
1222void GISelValueTracking::computeKnownFPClassForFPTrunc(
1223 const MachineInstr &MI, const APInt &DemandedElts,
1224 FPClassTest InterestedClasses, KnownFPClass &Known, unsigned Depth) {
1225 if ((InterestedClasses & (KnownFPClass::OrderedLessThanZeroMask | fcNan)) ==
1226 fcNone)
1227 return;
1228
1229 Register Val = MI.getOperand(i: 1).getReg();
1230 KnownFPClass KnownSrc;
1231 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses, Known&: KnownSrc,
1232 Depth: Depth + 1);
1233 Known = KnownFPClass::fptrunc(KnownSrc);
1234}
1235
1236void GISelValueTracking::computeKnownFPClass(Register R,
1237 const APInt &DemandedElts,
1238 FPClassTest InterestedClasses,
1239 KnownFPClass &Known,
1240 unsigned Depth) {
1241 assert(Known.isUnknown() && "should not be called with known information");
1242
1243 if (!DemandedElts) {
1244 // No demanded elts, better to assume we don't know anything.
1245 Known.resetAll();
1246 return;
1247 }
1248
1249 assert(Depth <= MaxAnalysisRecursionDepth && "Limit Search Depth");
1250
1251 MachineInstr &MI = *MRI.getVRegDef(Reg: R);
1252 unsigned Opcode = MI.getOpcode();
1253 LLT DstTy = MRI.getType(Reg: R);
1254
1255 if (!DstTy.isValid()) {
1256 Known.resetAll();
1257 return;
1258 }
1259
1260 if (auto Cst = GFConstant::getConstant(Const: R, MRI)) {
1261 switch (Cst->getKind()) {
1262 case GFConstant::GFConstantKind::Scalar: {
1263 auto APF = Cst->getScalarValue();
1264 Known.setKnownFPClasses(APF.classify());
1265 Known.setSignBit(APF.isNegative());
1266 break;
1267 }
1268 case GFConstant::GFConstantKind::FixedVector: {
1269 Known.setKnownFPClasses(fcNone);
1270 bool SignBitAllZero = true;
1271 bool SignBitAllOne = true;
1272
1273 for (auto C : *Cst) {
1274 Known.setKnownFPClasses(Known.getKnownFPClasses() | C.classify());
1275 if (C.isNegative())
1276 SignBitAllZero = false;
1277 else
1278 SignBitAllOne = false;
1279 }
1280
1281 if (SignBitAllOne != SignBitAllZero)
1282 Known.setSignBit(SignBitAllOne);
1283
1284 break;
1285 }
1286 case GFConstant::GFConstantKind::ScalableVector: {
1287 Known.resetAll();
1288 break;
1289 }
1290 }
1291
1292 return;
1293 }
1294
1295 FPClassTest KnownNotFromFlags = fcNone;
1296 if (MI.getFlag(Flag: MachineInstr::MIFlag::FmNoNans))
1297 KnownNotFromFlags |= fcNan;
1298 if (MI.getFlag(Flag: MachineInstr::MIFlag::FmNoInfs))
1299 KnownNotFromFlags |= fcInf;
1300
1301 // We no longer need to find out about these bits from inputs if we can
1302 // assume this from flags/attributes.
1303 InterestedClasses &= ~KnownNotFromFlags;
1304
1305 llvm::scope_exit ClearClassesFromFlags(
1306 [=, &Known] { Known.knownNot(RuleOut: KnownNotFromFlags); });
1307
1308 // All recursive calls that increase depth must come after this.
1309 if (Depth == MaxAnalysisRecursionDepth)
1310 return;
1311
1312 const MachineFunction *MF = MI.getMF();
1313
1314 switch (Opcode) {
1315 default:
1316 TL.computeKnownFPClassForTargetInstr(Analysis&: *this, R, Known, DemandedElts, MRI,
1317 Depth);
1318 break;
1319 case TargetOpcode::G_FNEG: {
1320 Register Val = MI.getOperand(i: 1).getReg();
1321 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses, Known, Depth: Depth + 1);
1322 Known.fneg();
1323 break;
1324 }
1325 case TargetOpcode::G_SELECT: {
1326 GSelect &SelMI = cast<GSelect>(Val&: MI);
1327 Register Cond = SelMI.getCondReg();
1328 Register LHS = SelMI.getTrueReg();
1329 Register RHS = SelMI.getFalseReg();
1330
1331 FPClassTest FilterLHS = fcAllFlags;
1332 FPClassTest FilterRHS = fcAllFlags;
1333
1334 Register TestedValue;
1335 FPClassTest MaskIfTrue = fcAllFlags;
1336 FPClassTest MaskIfFalse = fcAllFlags;
1337 FPClassTest ClassVal = fcNone;
1338
1339 CmpInst::Predicate Pred;
1340 Register CmpLHS, CmpRHS;
1341 if (mi_match(R: Cond, MRI,
1342 P: m_GFCmp(P: m_Pred(P&: Pred), L: m_Reg(R&: CmpLHS), R: m_Reg(R&: CmpRHS)))) {
1343 // If the select filters out a value based on the class, it no longer
1344 // participates in the class of the result
1345
1346 // TODO: In some degenerate cases we can infer something if we try again
1347 // without looking through sign operations.
1348 bool LookThroughFAbsFNeg = CmpLHS != LHS && CmpLHS != RHS;
1349 std::tie(args&: TestedValue, args&: MaskIfTrue, args&: MaskIfFalse) =
1350 fcmpImpliesClass(Pred, MF: *MF, LHS: CmpLHS, RHS: CmpRHS, LookThroughSrc: LookThroughFAbsFNeg);
1351 } else if (mi_match(
1352 R: Cond, MRI,
1353 P: m_GIsFPClass(L: m_Reg(R&: TestedValue), T: m_FPClassTest(T&: ClassVal)))) {
1354 FPClassTest TestedMask = ClassVal;
1355 MaskIfTrue = TestedMask;
1356 MaskIfFalse = ~TestedMask;
1357 }
1358
1359 if (TestedValue == LHS) {
1360 // match !isnan(x) ? x : y
1361 FilterLHS = MaskIfTrue;
1362 } else if (TestedValue == RHS) { // && IsExactClass
1363 // match !isnan(x) ? y : x
1364 FilterRHS = MaskIfFalse;
1365 }
1366
1367 KnownFPClass Known2;
1368 computeKnownFPClass(R: LHS, DemandedElts, InterestedClasses: InterestedClasses & FilterLHS, Known,
1369 Depth: Depth + 1);
1370 Known.setKnownFPClasses(Known.getKnownFPClasses() & FilterLHS);
1371
1372 computeKnownFPClass(R: RHS, DemandedElts, InterestedClasses: InterestedClasses & FilterRHS,
1373 Known&: Known2, Depth: Depth + 1);
1374 Known2.setKnownFPClasses(Known2.getKnownFPClasses() & FilterRHS);
1375
1376 Known |= Known2;
1377 break;
1378 }
1379 case TargetOpcode::G_FCOPYSIGN: {
1380 Register Magnitude = MI.getOperand(i: 1).getReg();
1381 Register Sign = MI.getOperand(i: 2).getReg();
1382
1383 KnownFPClass KnownSign;
1384
1385 computeKnownFPClass(R: Magnitude, DemandedElts, InterestedClasses, Known,
1386 Depth: Depth + 1);
1387 computeKnownFPClass(R: Sign, DemandedElts, InterestedClasses, Known&: KnownSign,
1388 Depth: Depth + 1);
1389 Known.copysign(Sign: KnownSign);
1390 break;
1391 }
1392 case TargetOpcode::G_FMA:
1393 case TargetOpcode::G_STRICT_FMA:
1394 case TargetOpcode::G_FMAD: {
1395 if ((InterestedClasses & fcNegative) == fcNone)
1396 break;
1397
1398 Register A = MI.getOperand(i: 1).getReg();
1399 Register B = MI.getOperand(i: 2).getReg();
1400 Register C = MI.getOperand(i: 3).getReg();
1401
1402 DenormalMode Mode =
1403 MF->getDenormalMode(FPType: getFltSemanticForLLT(Ty: DstTy.getScalarType()));
1404
1405 if (A == B && isGuaranteedNotToBeUndef(Reg: A, MRI, Depth: Depth + 1)) {
1406 // x * x + y
1407 KnownFPClass KnownSrc, KnownAddend;
1408 computeKnownFPClass(R: C, DemandedElts, InterestedClasses, Known&: KnownAddend,
1409 Depth: Depth + 1);
1410 computeKnownFPClass(R: A, DemandedElts, InterestedClasses, Known&: KnownSrc,
1411 Depth: Depth + 1);
1412 if (KnownNotFromFlags) {
1413 KnownSrc.knownNot(RuleOut: KnownNotFromFlags);
1414 KnownAddend.knownNot(RuleOut: KnownNotFromFlags);
1415 }
1416 Known = KnownFPClass::fma_square(Squared: KnownSrc, Addend: KnownAddend, Mode);
1417 } else {
1418 KnownFPClass KnownSrc[3];
1419 computeKnownFPClass(R: A, DemandedElts, InterestedClasses, Known&: KnownSrc[0],
1420 Depth: Depth + 1);
1421 if (KnownSrc[0].isUnknown())
1422 break;
1423 computeKnownFPClass(R: B, DemandedElts, InterestedClasses, Known&: KnownSrc[1],
1424 Depth: Depth + 1);
1425 if (KnownSrc[1].isUnknown())
1426 break;
1427 computeKnownFPClass(R: C, DemandedElts, InterestedClasses, Known&: KnownSrc[2],
1428 Depth: Depth + 1);
1429 if (KnownSrc[2].isUnknown())
1430 break;
1431 if (KnownNotFromFlags) {
1432 KnownSrc[0].knownNot(RuleOut: KnownNotFromFlags);
1433 KnownSrc[1].knownNot(RuleOut: KnownNotFromFlags);
1434 KnownSrc[2].knownNot(RuleOut: KnownNotFromFlags);
1435 }
1436 Known = KnownFPClass::fma(LHS: KnownSrc[0], RHS: KnownSrc[1], Addend: KnownSrc[2], Mode);
1437 }
1438 break;
1439 }
1440 case TargetOpcode::G_FSQRT:
1441 case TargetOpcode::G_STRICT_FSQRT: {
1442 KnownFPClass KnownSrc;
1443 FPClassTest InterestedSrcs = InterestedClasses;
1444 if (InterestedClasses & fcNan)
1445 InterestedSrcs |= KnownFPClass::OrderedLessThanZeroMask;
1446
1447 Register Val = MI.getOperand(i: 1).getReg();
1448 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses: InterestedSrcs, Known&: KnownSrc, Depth: Depth + 1);
1449
1450 DenormalMode Mode =
1451 MF->getDenormalMode(FPType: getFltSemanticForLLT(Ty: DstTy.getScalarType()));
1452 Known = KnownFPClass::sqrt(Src: KnownSrc, Mode);
1453 if (MI.getFlag(Flag: MachineInstr::MIFlag::FmNsz))
1454 Known.knownNot(RuleOut: fcNegZero);
1455 break;
1456 }
1457 case TargetOpcode::G_FABS: {
1458 if ((InterestedClasses & (fcNan | fcPositive)) != fcNone) {
1459 Register Val = MI.getOperand(i: 1).getReg();
1460 // If we only care about the sign bit we don't need to inspect the
1461 // operand.
1462 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses, Known,
1463 Depth: Depth + 1);
1464 }
1465 Known.fabs();
1466 break;
1467 }
1468 case TargetOpcode::G_FATAN2: {
1469 FPClassTest InterestedY = InterestedClasses;
1470 FPClassTest InterestedX = InterestedClasses;
1471
1472 // We can rule out negative values if y cannot have a negative value.
1473 if ((InterestedClasses & fcNegFinite) != fcNone)
1474 InterestedY |= fcNegative;
1475
1476 // We can rule out positive values if y cannot have a positive value.
1477 if ((InterestedClasses & fcPosFinite) != fcNone)
1478 InterestedY |= fcPositive | fcNegSubnormal;
1479
1480 // We can rule out zero and subnormal if x cannot have a positive value.
1481 if ((InterestedClasses & (fcZero | fcSubnormal)) != fcNone)
1482 InterestedX |= fcPositive | fcNegSubnormal;
1483
1484 Register Y = MI.getOperand(i: 1).getReg();
1485 Register X = MI.getOperand(i: 2).getReg();
1486 KnownFPClass KnownY, KnownX;
1487 computeKnownFPClass(R: Y, DemandedElts, InterestedClasses: InterestedY, Known&: KnownY, Depth: Depth + 1);
1488 computeKnownFPClass(R: X, DemandedElts, InterestedClasses: InterestedX, Known&: KnownX, Depth: Depth + 1);
1489 DenormalMode Mode =
1490 MF->getDenormalMode(FPType: getFltSemanticForLLT(Ty: DstTy.getScalarType()));
1491 Known = KnownFPClass::atan2(LHS: KnownY, RHS: KnownX, Mode);
1492 break;
1493 }
1494 case TargetOpcode::G_FSINH: {
1495 Register Val = MI.getOperand(i: 1).getReg();
1496 KnownFPClass KnownSrc;
1497 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses, Known&: KnownSrc,
1498 Depth: Depth + 1);
1499 Known = KnownFPClass::sinh(Src: KnownSrc);
1500 break;
1501 }
1502 case TargetOpcode::G_FCOSH: {
1503 Register Val = MI.getOperand(i: 1).getReg();
1504 KnownFPClass KnownSrc;
1505 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses, Known&: KnownSrc,
1506 Depth: Depth + 1);
1507 Known = KnownFPClass::cosh(Src: KnownSrc);
1508 break;
1509 }
1510 case TargetOpcode::G_FTANH: {
1511 Register Val = MI.getOperand(i: 1).getReg();
1512 KnownFPClass KnownSrc;
1513 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses, Known&: KnownSrc,
1514 Depth: Depth + 1);
1515 Known = KnownFPClass::tanh(Src: KnownSrc);
1516 break;
1517 }
1518 case TargetOpcode::G_FASIN: {
1519 Register Val = MI.getOperand(i: 1).getReg();
1520 KnownFPClass KnownSrc;
1521 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses, Known&: KnownSrc,
1522 Depth: Depth + 1);
1523 Known = KnownFPClass::asin(Src: KnownSrc);
1524 break;
1525 }
1526 case TargetOpcode::G_FACOS: {
1527 Register Val = MI.getOperand(i: 1).getReg();
1528 KnownFPClass KnownSrc;
1529 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses, Known&: KnownSrc,
1530 Depth: Depth + 1);
1531 Known = KnownFPClass::acos(Src: KnownSrc);
1532 break;
1533 }
1534 case TargetOpcode::G_FATAN: {
1535 Register Val = MI.getOperand(i: 1).getReg();
1536 KnownFPClass KnownSrc;
1537 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses, Known&: KnownSrc,
1538 Depth: Depth + 1);
1539 Known = KnownFPClass::atan(Src: KnownSrc);
1540 break;
1541 }
1542 case TargetOpcode::G_FTAN: {
1543 Register Val = MI.getOperand(i: 1).getReg();
1544 KnownFPClass KnownSrc;
1545 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses, Known&: KnownSrc,
1546 Depth: Depth + 1);
1547 Known = KnownFPClass::tan(Src: KnownSrc);
1548 break;
1549 }
1550 case TargetOpcode::G_FSIN:
1551 case TargetOpcode::G_FCOS: {
1552 // Return NaN on infinite inputs.
1553 Register Val = MI.getOperand(i: 1).getReg();
1554 KnownFPClass KnownSrc;
1555 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses, Known&: KnownSrc,
1556 Depth: Depth + 1);
1557 Known = Opcode == TargetOpcode::G_FCOS ? KnownFPClass::cos(Src: KnownSrc)
1558 : KnownFPClass::sin(Src: KnownSrc);
1559 break;
1560 }
1561 case TargetOpcode::G_FSINCOS: {
1562 // Operand layout: (sin_dst, cos_dst, src)
1563 Register Src = MI.getOperand(i: 2).getReg();
1564 KnownFPClass KnownSrc;
1565 computeKnownFPClass(R: Src, DemandedElts, InterestedClasses, Known&: KnownSrc,
1566 Depth: Depth + 1);
1567 if (R == MI.getOperand(i: 0).getReg())
1568 Known = KnownFPClass::sin(Src: KnownSrc);
1569 else
1570 Known = KnownFPClass::cos(Src: KnownSrc);
1571 break;
1572 }
1573 case TargetOpcode::G_FMAXNUM:
1574 case TargetOpcode::G_FMINNUM:
1575 case TargetOpcode::G_FMINNUM_IEEE:
1576 case TargetOpcode::G_FMAXIMUM:
1577 case TargetOpcode::G_FMINIMUM:
1578 case TargetOpcode::G_FMAXNUM_IEEE:
1579 case TargetOpcode::G_FMAXIMUMNUM:
1580 case TargetOpcode::G_FMINIMUMNUM: {
1581 Register LHS = MI.getOperand(i: 1).getReg();
1582 Register RHS = MI.getOperand(i: 2).getReg();
1583 KnownFPClass KnownLHS, KnownRHS;
1584
1585 computeKnownFPClass(R: LHS, DemandedElts, InterestedClasses, Known&: KnownLHS,
1586 Depth: Depth + 1);
1587 computeKnownFPClass(R: RHS, DemandedElts, InterestedClasses, Known&: KnownRHS,
1588 Depth: Depth + 1);
1589
1590 KnownFPClass::MinMaxKind Kind;
1591 switch (Opcode) {
1592 case TargetOpcode::G_FMINIMUM:
1593 Kind = KnownFPClass::MinMaxKind::minimum;
1594 break;
1595 case TargetOpcode::G_FMAXIMUM:
1596 Kind = KnownFPClass::MinMaxKind::maximum;
1597 break;
1598 case TargetOpcode::G_FMINIMUMNUM:
1599 Kind = KnownFPClass::MinMaxKind::minimumnum;
1600 break;
1601 case TargetOpcode::G_FMAXIMUMNUM:
1602 Kind = KnownFPClass::MinMaxKind::maximumnum;
1603 break;
1604 case TargetOpcode::G_FMINNUM:
1605 case TargetOpcode::G_FMINNUM_IEEE:
1606 Kind = KnownFPClass::MinMaxKind::minnum;
1607 break;
1608 case TargetOpcode::G_FMAXNUM:
1609 case TargetOpcode::G_FMAXNUM_IEEE:
1610 Kind = KnownFPClass::MinMaxKind::maxnum;
1611 break;
1612 default:
1613 llvm_unreachable("unhandled min/max opcode");
1614 }
1615
1616 DenormalMode Mode =
1617 MF->getDenormalMode(FPType: getFltSemanticForLLT(Ty: DstTy.getScalarType()));
1618 Known = KnownFPClass::minMaxLike(LHS: KnownLHS, RHS: KnownRHS, Kind, DenormMode: Mode);
1619 break;
1620 }
1621 case TargetOpcode::G_FCANONICALIZE: {
1622 Register Val = MI.getOperand(i: 1).getReg();
1623 KnownFPClass KnownSrc;
1624 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses, Known&: KnownSrc,
1625 Depth: Depth + 1);
1626
1627 LLT Ty = MRI.getType(Reg: Val).getScalarType();
1628 const fltSemantics &FPType = getFltSemanticForLLT(Ty);
1629 DenormalMode DenormMode = MF->getDenormalMode(FPType);
1630 Known = KnownFPClass::canonicalize(Src: KnownSrc, DenormMode);
1631 break;
1632 }
1633 case TargetOpcode::G_VECREDUCE_FMAX:
1634 case TargetOpcode::G_VECREDUCE_FMIN:
1635 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
1636 case TargetOpcode::G_VECREDUCE_FMINIMUM:
1637 case TargetOpcode::G_VECREDUCE_FMAXIMUMNUM:
1638 case TargetOpcode::G_VECREDUCE_FMINIMUMNUM: {
1639 Register Val = MI.getOperand(i: 1).getReg();
1640 // reduce min/max will choose an element from one of the vector elements,
1641 // so we can infer and class information that is common to all elements.
1642
1643 Known =
1644 computeKnownFPClass(R: Val, Flags: MI.getFlags(), InterestedClasses, Depth: Depth + 1);
1645 // Can only propagate sign if output is never NaN.
1646 if (!Known.isKnownNeverNaN())
1647 Known.setSignBit(std::nullopt);
1648 break;
1649 }
1650 case TargetOpcode::G_FFLOOR:
1651 case TargetOpcode::G_FCEIL:
1652 case TargetOpcode::G_FRINT:
1653 case TargetOpcode::G_FNEARBYINT:
1654 case TargetOpcode::G_INTRINSIC_FPTRUNC_ROUND:
1655 case TargetOpcode::G_INTRINSIC_ROUND:
1656 case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
1657 case TargetOpcode::G_INTRINSIC_TRUNC: {
1658 Register Val = MI.getOperand(i: 1).getReg();
1659 KnownFPClass KnownSrc;
1660 FPClassTest InterestedSrcs = InterestedClasses;
1661 if (InterestedSrcs & fcPosFinite)
1662 InterestedSrcs |= fcPosFinite;
1663 if (InterestedSrcs & fcNegFinite)
1664 InterestedSrcs |= fcNegFinite;
1665 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses: InterestedSrcs, Known&: KnownSrc, Depth: Depth + 1);
1666
1667 // TODO: handle multi unit FPTypes once LLT FPInfo lands
1668 bool IsTrunc = Opcode == TargetOpcode::G_INTRINSIC_TRUNC;
1669 Known = KnownFPClass::roundToIntegral(Src: KnownSrc, IsTrunc,
1670 /*IsMultiUnitFPType=*/false);
1671 break;
1672 }
1673 case TargetOpcode::G_FEXP:
1674 case TargetOpcode::G_FEXP2:
1675 case TargetOpcode::G_FEXP10: {
1676 Register Val = MI.getOperand(i: 1).getReg();
1677 KnownFPClass KnownSrc;
1678 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses, Known&: KnownSrc,
1679 Depth: Depth + 1);
1680 Known = KnownFPClass::exp(Src: KnownSrc);
1681 break;
1682 }
1683 case TargetOpcode::G_FLOG:
1684 case TargetOpcode::G_FLOG2:
1685 case TargetOpcode::G_FLOG10: {
1686 FPClassTest InterestedSrcs = fcNone;
1687
1688 // log(negative) produces NaN.
1689 if ((InterestedClasses & fcNan) != fcNone)
1690 InterestedSrcs |= fcNan | fcNegative;
1691
1692 // log(logical-zero) produces negative infinity.
1693 if ((InterestedClasses & fcNegInf) != fcNone)
1694 InterestedSrcs |= fcZero | fcSubnormal;
1695
1696 // log(x) < -0.0 if x < +1.0
1697 if ((InterestedClasses & fcNegNormal) != fcNone)
1698 InterestedSrcs |= fcPosSubnormal | fcPosNormal;
1699
1700 // log(x) >= +0.0 if x >= +1.0
1701 if ((InterestedClasses & (fcPosZero | fcPosNormal)) != fcNone)
1702 InterestedSrcs |= fcPosNormal;
1703
1704 // log(x) is positive infinity iff x is positive infinity.
1705 if ((InterestedClasses & fcPosInf) != fcNone)
1706 InterestedSrcs |= fcPosInf;
1707
1708 Register Val = MI.getOperand(i: 1).getReg();
1709 KnownFPClass KnownSrc;
1710 if (InterestedSrcs != fcNone)
1711 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses: InterestedSrcs, Known&: KnownSrc,
1712 Depth: Depth + 1);
1713
1714 LLT Ty = MRI.getType(Reg: Val).getScalarType();
1715 const fltSemantics &FltSem = getFltSemanticForLLT(Ty);
1716 DenormalMode Mode = MF->getDenormalMode(FPType: FltSem);
1717 Known = KnownFPClass::log(Src: KnownSrc, Mode);
1718 break;
1719 }
1720 case TargetOpcode::G_FPOW: {
1721 const bool WantNaN = (InterestedClasses & fcNan) != fcNone;
1722 const bool WantNegative = (InterestedClasses & fcNegative) != fcNone;
1723 if (!WantNaN && !WantNegative)
1724 break;
1725
1726 FPClassTest InterestedLHS = fcNone;
1727 FPClassTest InterestedRHS = fcNone;
1728 if (WantNaN) {
1729 // pow may return NaN if one of the arguments is NaN. NaN may be produced
1730 // from a non-zero-finite-negative base and a non-integer exponent.
1731 InterestedLHS |= fcNan | fcNegNormal | fcNegSubnormal;
1732 InterestedRHS |= fcNan;
1733 }
1734 if (WantNegative) {
1735 // A negative value is returned when a negative base is raised to an odd
1736 // integer power. Only normal values can be odd integers.
1737 InterestedLHS |= fcNegative;
1738 InterestedRHS |= fcNormal;
1739 }
1740
1741 KnownFPClass KnownLHS;
1742 computeKnownFPClass(R: MI.getOperand(i: 1).getReg(), DemandedElts, InterestedClasses: InterestedLHS,
1743 Known&: KnownLHS, Depth: Depth + 1);
1744
1745 // If the LHS is unknown, then querying the RHS is only useful for rare edge
1746 // cases.
1747 if (KnownLHS.isUnknown())
1748 break;
1749
1750 KnownFPClass KnownRHS;
1751 computeKnownFPClass(R: MI.getOperand(i: 2).getReg(), DemandedElts, InterestedClasses: InterestedRHS,
1752 Known&: KnownRHS, Depth: Depth + 1);
1753 Known = KnownFPClass::pow(LHS: KnownLHS, RHS: KnownRHS);
1754 break;
1755 }
1756 case TargetOpcode::G_FPOWI: {
1757 if ((InterestedClasses & (fcNan | fcInf | fcNegative)) == fcNone)
1758 break;
1759
1760 Register Exp = MI.getOperand(i: 2).getReg();
1761 LLT ExpTy = MRI.getType(Reg: Exp);
1762 KnownBits ExponentKnownBits = getKnownBits(
1763 R: Exp, DemandedElts: ExpTy.isVector() ? DemandedElts : APInt(1, 1), Depth: Depth + 1);
1764
1765 FPClassTest InterestedSrcs = fcNone;
1766 if (InterestedClasses & fcNan)
1767 InterestedSrcs |= fcNan;
1768 if (!ExponentKnownBits.isZero()) {
1769 if (InterestedClasses & fcInf)
1770 InterestedSrcs |= fcFinite | fcInf;
1771 if ((InterestedClasses & fcNegative) && !ExponentKnownBits.isEven())
1772 InterestedSrcs |= fcNegative;
1773 }
1774
1775 KnownFPClass KnownSrc;
1776 if (InterestedSrcs != fcNone) {
1777 Register Val = MI.getOperand(i: 1).getReg();
1778 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses: InterestedSrcs, Known&: KnownSrc,
1779 Depth: Depth + 1);
1780 }
1781
1782 Known = KnownFPClass::powi(Src: KnownSrc, N: ExponentKnownBits);
1783 break;
1784 }
1785 case TargetOpcode::G_FLDEXP:
1786 case TargetOpcode::G_STRICT_FLDEXP: {
1787 Register Val = MI.getOperand(i: 1).getReg();
1788 KnownFPClass KnownSrc;
1789 computeKnownFPClass(R: Val, DemandedElts, InterestedClasses, Known&: KnownSrc,
1790 Depth: Depth + 1);
1791
1792 // Can refine inf/zero handling based on the exponent operand.
1793 const FPClassTest ExpInfoMask = fcZero | fcSubnormal | fcInf;
1794 KnownBits ExpBits;
1795 if ((KnownSrc.getKnownFPClasses() & ExpInfoMask) != fcNone) {
1796 Register ExpReg = MI.getOperand(i: 2).getReg();
1797 LLT ExpTy = MRI.getType(Reg: ExpReg);
1798 ExpBits = getKnownBits(
1799 R: ExpReg, DemandedElts: ExpTy.isVector() ? DemandedElts : APInt(1, 1), Depth: Depth + 1);
1800 }
1801
1802 LLT ScalarTy = DstTy.getScalarType();
1803 const fltSemantics &Flt = getFltSemanticForLLT(Ty: ScalarTy);
1804 DenormalMode Mode = MF->getDenormalMode(FPType: Flt);
1805 Known = KnownFPClass::ldexp(Src: KnownSrc, ExpBits, Flt, Mode);
1806 break;
1807 }
1808 case TargetOpcode::G_FADD:
1809 case TargetOpcode::G_STRICT_FADD:
1810 case TargetOpcode::G_FSUB:
1811 case TargetOpcode::G_STRICT_FSUB: {
1812 Register LHS = MI.getOperand(i: 1).getReg();
1813 Register RHS = MI.getOperand(i: 2).getReg();
1814 bool IsAdd = (Opcode == TargetOpcode::G_FADD ||
1815 Opcode == TargetOpcode::G_STRICT_FADD);
1816 bool WantNegative =
1817 IsAdd &&
1818 (InterestedClasses & KnownFPClass::OrderedLessThanZeroMask) != fcNone;
1819 bool WantNaN = (InterestedClasses & fcNan) != fcNone;
1820 bool WantNegZero = (InterestedClasses & fcNegZero) != fcNone;
1821
1822 if (!WantNaN && !WantNegative && !WantNegZero) {
1823 break;
1824 }
1825
1826 DenormalMode Mode =
1827 MF->getDenormalMode(FPType: getFltSemanticForLLT(Ty: DstTy.getScalarType()));
1828
1829 FPClassTest InterestedSrcs = InterestedClasses;
1830 if (WantNegative)
1831 InterestedSrcs |= KnownFPClass::OrderedLessThanZeroMask;
1832 if (InterestedClasses & fcNan)
1833 InterestedSrcs |= fcInf;
1834
1835 // Special case fadd x, x (canonical form of fmul x, 2).
1836 if (IsAdd && LHS == RHS && isGuaranteedNotToBeUndef(Reg: LHS, MRI, Depth: Depth + 1)) {
1837 KnownFPClass KnownSelf;
1838 computeKnownFPClass(R: LHS, DemandedElts, InterestedClasses: InterestedSrcs, Known&: KnownSelf,
1839 Depth: Depth + 1);
1840 Known = KnownFPClass::fadd_self(Src: KnownSelf, Mode);
1841 break;
1842 }
1843
1844 KnownFPClass KnownLHS, KnownRHS;
1845 computeKnownFPClass(R: RHS, DemandedElts, InterestedClasses: InterestedSrcs, Known&: KnownRHS, Depth: Depth + 1);
1846
1847 if ((WantNaN && KnownRHS.isKnownNeverNaN()) ||
1848 (WantNegative && KnownRHS.cannotBeOrderedLessThanZero()) ||
1849 WantNegZero || !IsAdd) {
1850 // RHS is canonically cheaper to compute. Skip inspecting the LHS if
1851 // there's no point.
1852 computeKnownFPClass(R: LHS, DemandedElts, InterestedClasses: InterestedSrcs, Known&: KnownLHS,
1853 Depth: Depth + 1);
1854 }
1855
1856 if (IsAdd)
1857 Known = KnownFPClass::fadd(LHS: KnownLHS, RHS: KnownRHS, Mode);
1858 else
1859 Known = KnownFPClass::fsub(LHS: KnownLHS, RHS: KnownRHS, Mode);
1860 break;
1861 }
1862 case TargetOpcode::G_FMUL:
1863 case TargetOpcode::G_STRICT_FMUL: {
1864 Register LHS = MI.getOperand(i: 1).getReg();
1865 Register RHS = MI.getOperand(i: 2).getReg();
1866 DenormalMode Mode =
1867 MF->getDenormalMode(FPType: getFltSemanticForLLT(Ty: DstTy.getScalarType()));
1868
1869 // X * X is always non-negative or a NaN (use square() for precision).
1870 if (LHS == RHS && isGuaranteedNotToBeUndef(Reg: LHS, MRI, Depth: Depth + 1)) {
1871 KnownFPClass KnownSrc;
1872 computeKnownFPClass(R: LHS, DemandedElts, InterestedClasses: fcAllFlags, Known&: KnownSrc, Depth: Depth + 1);
1873 Known = KnownFPClass::square(Src: KnownSrc, Mode);
1874 } else {
1875 // If RHS is a scalar constant, use the more precise APFloat overload.
1876 auto RHSCst = GFConstant::getConstant(Const: RHS, MRI);
1877 if (RHSCst && RHSCst->getKind() == GFConstant::GFConstantKind::Scalar) {
1878 KnownFPClass KnownLHS;
1879 computeKnownFPClass(R: LHS, DemandedElts, InterestedClasses: fcAllFlags, Known&: KnownLHS, Depth: Depth + 1);
1880 Known = KnownFPClass::fmul(LHS: KnownLHS, RHS: RHSCst->getScalarValue(), Mode);
1881 } else {
1882 KnownFPClass KnownLHS, KnownRHS;
1883 computeKnownFPClass(R: RHS, DemandedElts, InterestedClasses: fcAllFlags, Known&: KnownRHS, Depth: Depth + 1);
1884 computeKnownFPClass(R: LHS, DemandedElts, InterestedClasses: fcAllFlags, Known&: KnownLHS, Depth: Depth + 1);
1885 Known = KnownFPClass::fmul(LHS: KnownLHS, RHS: KnownRHS, Mode);
1886
1887 // If one operand is known |x| <= 1 and the other is finite, the
1888 // product cannot overflow to infinity.
1889 if (KnownLHS.isKnownNever(Mask: fcInf) && isAbsoluteValueULEOne(R: RHS, MRI))
1890 Known.knownNot(RuleOut: fcInf);
1891 else if (KnownRHS.isKnownNever(Mask: fcInf) &&
1892 isAbsoluteValueULEOne(R: LHS, MRI))
1893 Known.knownNot(RuleOut: fcInf);
1894 }
1895 }
1896 break;
1897 }
1898 case TargetOpcode::G_FDIV: {
1899 const bool WantNan = (InterestedClasses & fcNan) != fcNone;
1900
1901 Register LHS = MI.getOperand(i: 1).getReg();
1902 Register RHS = MI.getOperand(i: 2).getReg();
1903
1904 DenormalMode Mode =
1905 MF->getDenormalMode(FPType: getFltSemanticForLLT(Ty: DstTy.getScalarType()));
1906
1907 if (LHS == RHS && isGuaranteedNotToBeUndef(Reg: LHS, MRI, Depth: Depth + 1)) {
1908 // X / X is always exactly 1.0 or a NaN.
1909 Known.setKnownFPClasses(fcPosNormal | fcNan);
1910
1911 if (!WantNan)
1912 break;
1913
1914 KnownFPClass KnownSrc;
1915 computeKnownFPClass(R: LHS, DemandedElts,
1916 InterestedClasses: fcNan | fcInf | fcZero | fcSubnormal, Known&: KnownSrc,
1917 Depth: Depth + 1);
1918 Known = KnownFPClass::fdiv_self(Src: KnownSrc, Mode);
1919 break;
1920 }
1921
1922 const bool WantNegative = (InterestedClasses & fcNegative) != fcNone;
1923 const bool WantPositive = (InterestedClasses & fcPositive) != fcNone;
1924 if (!WantNan && !WantNegative && !WantPositive)
1925 break;
1926
1927 KnownFPClass KnownLHS, KnownRHS;
1928 computeKnownFPClass(R: RHS, DemandedElts, InterestedClasses: fcAllFlags, Known&: KnownRHS, Depth: Depth + 1);
1929
1930 bool KnowSomethingUseful =
1931 KnownRHS.isKnownNeverNaN() ||
1932 KnownRHS.isKnownNever(Mask: fcNegNormal | fcNegSubnormal) ||
1933 KnownRHS.isKnownNever(Mask: fcPosNormal | fcPosSubnormal);
1934
1935 if (KnowSomethingUseful)
1936 computeKnownFPClass(R: LHS, DemandedElts, InterestedClasses: fcAllFlags, Known&: KnownLHS, Depth: Depth + 1);
1937
1938 Known = KnownFPClass::fdiv(LHS: KnownLHS, RHS: KnownRHS, Mode);
1939 break;
1940 }
1941 case TargetOpcode::G_FREM: {
1942 const bool WantNan = (InterestedClasses & fcNan) != fcNone;
1943
1944 Register LHS = MI.getOperand(i: 1).getReg();
1945 Register RHS = MI.getOperand(i: 2).getReg();
1946
1947 Known.knownNot(RuleOut: fcInf);
1948
1949 DenormalMode Mode =
1950 MF->getDenormalMode(FPType: getFltSemanticForLLT(Ty: DstTy.getScalarType()));
1951
1952 if (LHS == RHS && isGuaranteedNotToBeUndef(Reg: LHS, MRI, Depth: Depth + 1)) {
1953 // X % X is always exactly [+-]0.0 or a NaN.
1954 Known.setKnownFPClasses(fcZero | fcNan);
1955
1956 if (!WantNan)
1957 break;
1958
1959 KnownFPClass KnownSrc;
1960 computeKnownFPClass(R: LHS, DemandedElts,
1961 InterestedClasses: fcNan | fcInf | fcZero | fcSubnormal, Known&: KnownSrc,
1962 Depth: Depth + 1);
1963 Known = KnownFPClass::frem_self(Src: KnownSrc, Mode);
1964 break;
1965 }
1966
1967 const bool WantNegative = (InterestedClasses & fcNegative) != fcNone;
1968 const bool WantPositive = (InterestedClasses & fcPositive) != fcNone;
1969 if (!WantNan && !WantNegative && !WantPositive)
1970 break;
1971
1972 KnownFPClass KnownLHS, KnownRHS;
1973 computeKnownFPClass(R: RHS, DemandedElts, InterestedClasses: fcNan | fcInf | fcZero | fcNegative,
1974 Known&: KnownRHS, Depth: Depth + 1);
1975
1976 bool KnowSomethingUseful = KnownRHS.isKnownNeverNaN() ||
1977 KnownRHS.isKnownNever(Mask: fcNegative) ||
1978 KnownRHS.isKnownNever(Mask: fcPositive);
1979
1980 if (KnowSomethingUseful || WantPositive)
1981 computeKnownFPClass(R: LHS, DemandedElts, InterestedClasses: fcAllFlags, Known&: KnownLHS, Depth: Depth + 1);
1982
1983 Known = KnownFPClass::frem(LHS: KnownLHS, RHS: KnownRHS, Mode);
1984
1985 break;
1986 }
1987 case TargetOpcode::G_FFREXP: {
1988 // Only handle the mantissa output (operand 0); the exponent is an integer.
1989 if (R != MI.getOperand(i: 0).getReg())
1990 break;
1991 Register Src = MI.getOperand(i: 2).getReg();
1992 KnownFPClass KnownSrc;
1993 computeKnownFPClass(R: Src, DemandedElts, InterestedClasses, Known&: KnownSrc,
1994 Depth: Depth + 1);
1995 DenormalMode Mode =
1996 MF->getDenormalMode(FPType: getFltSemanticForLLT(Ty: DstTy.getScalarType()));
1997 Known = KnownFPClass::frexp_mant(Src: KnownSrc, Mode);
1998 break;
1999 }
2000 case TargetOpcode::G_FPEXT: {
2001 Register Src = MI.getOperand(i: 1).getReg();
2002 KnownFPClass KnownSrc;
2003 computeKnownFPClass(R: Src, DemandedElts, InterestedClasses, Known&: KnownSrc,
2004 Depth: Depth + 1);
2005
2006 LLT DstScalarTy = DstTy.getScalarType();
2007 const fltSemantics &DstSem = getFltSemanticForLLT(Ty: DstScalarTy);
2008 LLT SrcTy = MRI.getType(Reg: Src).getScalarType();
2009 const fltSemantics &SrcSem = getFltSemanticForLLT(Ty: SrcTy);
2010
2011 Known = KnownFPClass::fpext(KnownSrc, DstTy: DstSem, SrcTy: SrcSem);
2012 break;
2013 }
2014 case TargetOpcode::G_FPTRUNC: {
2015 computeKnownFPClassForFPTrunc(MI, DemandedElts, InterestedClasses, Known,
2016 Depth);
2017 break;
2018 }
2019 case TargetOpcode::G_SITOFP:
2020 case TargetOpcode::G_UITOFP: {
2021 // Cannot produce nan
2022 Known.knownNot(RuleOut: fcNan);
2023
2024 // Integers cannot be subnormal
2025 Known.knownNot(RuleOut: fcSubnormal);
2026
2027 // sitofp and uitofp turn into +0.0 for zero.
2028 Known.knownNot(RuleOut: fcNegZero);
2029
2030 // UIToFP is always non-negative regardless of known bits.
2031 if (Opcode == TargetOpcode::G_UITOFP)
2032 Known.signBitMustBeZero();
2033
2034 // Only compute known bits if we can learn something useful from them.
2035 if (!(InterestedClasses & (fcPosZero | fcNormal | fcInf)))
2036 break;
2037
2038 Register Val = MI.getOperand(i: 1).getReg();
2039 LLT Ty = MRI.getType(Reg: Val);
2040 KnownBits IntKnown = getKnownBits(
2041 R: Val, DemandedElts: Ty.isVector() ? DemandedElts : APInt(1, 1), Depth: Depth + 1);
2042
2043 // If the integer is non-zero, the result cannot be +0.0.
2044 if (IntKnown.isNonZero())
2045 Known.knownNot(RuleOut: fcPosZero);
2046
2047 if (Opcode == TargetOpcode::G_SITOFP) {
2048 // If the signed integer is known non-negative, the result is
2049 // non-negative. If the signed integer is known negative, the result is
2050 // negative.
2051 if (IntKnown.isNonNegative())
2052 Known.signBitMustBeZero();
2053 else if (IntKnown.isNegative())
2054 Known.signBitMustBeOne();
2055 }
2056
2057 if (InterestedClasses & fcInf) {
2058 LLT FPTy = DstTy.getScalarType();
2059 const fltSemantics &FltSem = getFltSemanticForLLT(Ty: FPTy);
2060
2061 // Compute the effective integer width after removing known-zero leading
2062 // bits, to check if the result can overflow to infinity.
2063 int IntSize = IntKnown.getBitWidth();
2064 if (Opcode == TargetOpcode::G_UITOFP)
2065 IntSize -= IntKnown.countMinLeadingZeros();
2066 else
2067 IntSize -= IntKnown.countMinSignBits();
2068
2069 // If the exponent of the largest finite FP value can hold the largest
2070 // integer, the result of the cast must be finite.
2071 if (ilogb(Arg: APFloat::getLargest(Sem: FltSem)) >= IntSize)
2072 Known.knownNot(RuleOut: fcInf);
2073 }
2074
2075 break;
2076 }
2077 // case TargetOpcode::G_MERGE_VALUES:
2078 case TargetOpcode::G_BUILD_VECTOR:
2079 case TargetOpcode::G_CONCAT_VECTORS: {
2080 GMergeLikeInstr &Merge = cast<GMergeLikeInstr>(Val&: MI);
2081
2082 if (!DstTy.isFixedVector())
2083 break;
2084
2085 bool First = true;
2086 for (unsigned Idx = 0; Idx < Merge.getNumSources(); ++Idx) {
2087 // We know the index we are inserting to, so clear it from Vec check.
2088 bool NeedsElt = DemandedElts[Idx];
2089
2090 // Do we demand the inserted element?
2091 if (NeedsElt) {
2092 Register Src = Merge.getSourceReg(I: Idx);
2093 if (First) {
2094 computeKnownFPClass(R: Src, Known, InterestedClasses, Depth: Depth + 1);
2095 First = false;
2096 } else {
2097 KnownFPClass Known2;
2098 computeKnownFPClass(R: Src, Known&: Known2, InterestedClasses, Depth: Depth + 1);
2099 Known |= Known2;
2100 }
2101
2102 // If we don't know any bits, early out.
2103 if (Known.isUnknown())
2104 break;
2105 }
2106 }
2107
2108 break;
2109 }
2110 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
2111 // Look through extract element. If the index is non-constant or
2112 // out-of-range demand all elements, otherwise just the extracted
2113 // element.
2114 GExtractVectorElement &Extract = cast<GExtractVectorElement>(Val&: MI);
2115 Register Vec = Extract.getVectorReg();
2116 Register Idx = Extract.getIndexReg();
2117
2118 auto CIdx = getIConstantVRegVal(VReg: Idx, MRI);
2119
2120 LLT VecTy = MRI.getType(Reg: Vec);
2121
2122 if (VecTy.isFixedVector()) {
2123 unsigned NumElts = VecTy.getNumElements();
2124 APInt DemandedVecElts = APInt::getAllOnes(numBits: NumElts);
2125 if (CIdx && CIdx->ult(RHS: NumElts))
2126 DemandedVecElts = APInt::getOneBitSet(numBits: NumElts, BitNo: CIdx->getZExtValue());
2127 return computeKnownFPClass(R: Vec, DemandedElts: DemandedVecElts, InterestedClasses, Known,
2128 Depth: Depth + 1);
2129 }
2130
2131 break;
2132 }
2133 case TargetOpcode::G_INSERT_VECTOR_ELT: {
2134 GInsertVectorElement &Insert = cast<GInsertVectorElement>(Val&: MI);
2135 Register Vec = Insert.getVectorReg();
2136 Register Elt = Insert.getElementReg();
2137 Register Idx = Insert.getIndexReg();
2138
2139 LLT VecTy = MRI.getType(Reg: Vec);
2140
2141 if (VecTy.isScalableVector())
2142 return;
2143
2144 auto CIdx = getIConstantVRegVal(VReg: Idx, MRI);
2145
2146 unsigned NumElts = DemandedElts.getBitWidth();
2147 APInt DemandedVecElts = DemandedElts;
2148 bool NeedsElt = true;
2149 // If we know the index we are inserting to, clear it from Vec check.
2150 if (CIdx && CIdx->ult(RHS: NumElts)) {
2151 DemandedVecElts.clearBit(BitPosition: CIdx->getZExtValue());
2152 NeedsElt = DemandedElts[CIdx->getZExtValue()];
2153 }
2154
2155 // Do we demand the inserted element?
2156 if (NeedsElt) {
2157 computeKnownFPClass(R: Elt, Known, InterestedClasses, Depth: Depth + 1);
2158 // If we don't know any bits, early out.
2159 if (Known.isUnknown())
2160 break;
2161 } else {
2162 Known.setKnownFPClasses(fcNone);
2163 }
2164
2165 // Do we need anymore elements from Vec?
2166 if (!DemandedVecElts.isZero()) {
2167 KnownFPClass Known2;
2168 computeKnownFPClass(R: Vec, DemandedElts: DemandedVecElts, InterestedClasses, Known&: Known2,
2169 Depth: Depth + 1);
2170 Known |= Known2;
2171 }
2172
2173 break;
2174 }
2175 case TargetOpcode::G_SHUFFLE_VECTOR: {
2176 // For undef elements, we don't know anything about the common state of
2177 // the shuffle result.
2178 GShuffleVector &Shuf = cast<GShuffleVector>(Val&: MI);
2179 APInt DemandedLHS, DemandedRHS;
2180 if (DstTy.isScalableVector()) {
2181 assert(DemandedElts == APInt(1, 1));
2182 DemandedLHS = DemandedRHS = DemandedElts;
2183 } else {
2184 unsigned NumElts = MRI.getType(Reg: Shuf.getSrc1Reg()).getNumElements();
2185 if (!llvm::getShuffleDemandedElts(SrcWidth: NumElts, Mask: Shuf.getMask(), DemandedElts,
2186 DemandedLHS, DemandedRHS)) {
2187 Known.resetAll();
2188 return;
2189 }
2190 }
2191
2192 if (!!DemandedLHS) {
2193 Register LHS = Shuf.getSrc1Reg();
2194 computeKnownFPClass(R: LHS, DemandedElts: DemandedLHS, InterestedClasses, Known,
2195 Depth: Depth + 1);
2196
2197 // If we don't know any bits, early out.
2198 if (Known.isUnknown())
2199 break;
2200 } else {
2201 Known.setKnownFPClasses(fcNone);
2202 }
2203
2204 if (!!DemandedRHS) {
2205 KnownFPClass Known2;
2206 Register RHS = Shuf.getSrc2Reg();
2207 computeKnownFPClass(R: RHS, DemandedElts: DemandedRHS, InterestedClasses, Known&: Known2,
2208 Depth: Depth + 1);
2209 Known |= Known2;
2210 }
2211 break;
2212 }
2213 case TargetOpcode::G_PHI: {
2214 // Cap PHI recursion below the global limit to avoid spending the entire
2215 // budget chasing loop back-edges (matches ValueTracking's
2216 // PhiRecursionLimit).
2217 if (Depth + 2 > MaxAnalysisRecursionDepth)
2218 break;
2219 // PHI's operands are a mix of registers and basic blocks interleaved.
2220 // We only care about the register ones.
2221 bool First = true;
2222 for (unsigned Idx = 1; Idx < MI.getNumOperands(); Idx += 2) {
2223 const MachineOperand &Src = MI.getOperand(i: Idx);
2224 Register SrcReg = Src.getReg();
2225 if (First) {
2226 computeKnownFPClass(R: SrcReg, DemandedElts, InterestedClasses, Known,
2227 Depth: Depth + 1);
2228 First = false;
2229 } else {
2230 KnownFPClass Known2;
2231 computeKnownFPClass(R: SrcReg, DemandedElts, InterestedClasses, Known&: Known2,
2232 Depth: Depth + 1);
2233 Known = Known.intersectWith(RHS: Known2);
2234 }
2235 if (Known.isUnknown())
2236 break;
2237 }
2238 break;
2239 }
2240 case TargetOpcode::COPY: {
2241 Register Src = MI.getOperand(i: 1).getReg();
2242
2243 if (!Src.isVirtual())
2244 return;
2245
2246 computeKnownFPClass(R: Src, DemandedElts, InterestedClasses, Known, Depth: Depth + 1);
2247 break;
2248 }
2249 }
2250}
2251
2252KnownFPClass
2253GISelValueTracking::computeKnownFPClass(Register R, const APInt &DemandedElts,
2254 FPClassTest InterestedClasses,
2255 unsigned Depth) {
2256 KnownFPClass KnownClasses;
2257 computeKnownFPClass(R, DemandedElts, InterestedClasses, Known&: KnownClasses, Depth);
2258 return KnownClasses;
2259}
2260
2261KnownFPClass GISelValueTracking::computeKnownFPClass(
2262 Register R, FPClassTest InterestedClasses, unsigned Depth) {
2263 KnownFPClass Known;
2264 computeKnownFPClass(R, Known, InterestedClasses, Depth);
2265 return Known;
2266}
2267
2268KnownFPClass GISelValueTracking::computeKnownFPClass(
2269 Register R, const APInt &DemandedElts, uint32_t Flags,
2270 FPClassTest InterestedClasses, unsigned Depth) {
2271 if (Flags & MachineInstr::MIFlag::FmNoNans)
2272 InterestedClasses &= ~fcNan;
2273 if (Flags & MachineInstr::MIFlag::FmNoInfs)
2274 InterestedClasses &= ~fcInf;
2275
2276 KnownFPClass Result =
2277 computeKnownFPClass(R, DemandedElts, InterestedClasses, Depth);
2278
2279 if (Flags & MachineInstr::MIFlag::FmNoNans)
2280 Result.setKnownFPClasses(Result.getKnownFPClasses() & ~fcNan);
2281 if (Flags & MachineInstr::MIFlag::FmNoInfs)
2282 Result.setKnownFPClasses(Result.getKnownFPClasses() & ~fcInf);
2283 return Result;
2284}
2285
2286KnownFPClass GISelValueTracking::computeKnownFPClass(
2287 Register R, uint32_t Flags, FPClassTest InterestedClasses, unsigned Depth) {
2288 LLT Ty = MRI.getType(Reg: R);
2289 APInt DemandedElts =
2290 Ty.isFixedVector() ? APInt::getAllOnes(numBits: Ty.getNumElements()) : APInt(1, 1);
2291 return computeKnownFPClass(R, DemandedElts, Flags, InterestedClasses, Depth);
2292}
2293
2294bool GISelValueTracking::isKnownNeverNaN(Register Val, bool SNaN) {
2295 const MachineInstr *DefMI = MRI.getVRegDef(Reg: Val);
2296 if (!DefMI)
2297 return false;
2298
2299 if (DefMI->getFlag(Flag: MachineInstr::FmNoNans))
2300 return true;
2301
2302 // IEEE 754 arithmetic operations always quiet signaling NaNs. Short-circuit
2303 // the value-tracking analysis for the SNaN-only case: if the defining op is
2304 // known to quiet sNaN, the output can never be an sNaN.
2305 if (SNaN) {
2306 switch (DefMI->getOpcode()) {
2307 default:
2308 break;
2309 case TargetOpcode::G_FADD:
2310 case TargetOpcode::G_STRICT_FADD:
2311 case TargetOpcode::G_FSUB:
2312 case TargetOpcode::G_STRICT_FSUB:
2313 case TargetOpcode::G_FMUL:
2314 case TargetOpcode::G_STRICT_FMUL:
2315 case TargetOpcode::G_FDIV:
2316 case TargetOpcode::G_FREM:
2317 case TargetOpcode::G_FMA:
2318 case TargetOpcode::G_STRICT_FMA:
2319 case TargetOpcode::G_FMAD:
2320 case TargetOpcode::G_FSQRT:
2321 case TargetOpcode::G_STRICT_FSQRT:
2322 // Note: G_FABS and G_FNEG are bit-manipulation ops that preserve sNaN
2323 // exactly (LLVM LangRef: "never change anything except possibly the sign
2324 // bit"). They must NOT be listed here.
2325 case TargetOpcode::G_FSIN:
2326 case TargetOpcode::G_FCOS:
2327 case TargetOpcode::G_FSINCOS:
2328 case TargetOpcode::G_FTAN:
2329 case TargetOpcode::G_FASIN:
2330 case TargetOpcode::G_FACOS:
2331 case TargetOpcode::G_FATAN:
2332 case TargetOpcode::G_FATAN2:
2333 case TargetOpcode::G_FSINH:
2334 case TargetOpcode::G_FCOSH:
2335 case TargetOpcode::G_FTANH:
2336 case TargetOpcode::G_FEXP:
2337 case TargetOpcode::G_FEXP2:
2338 case TargetOpcode::G_FEXP10:
2339 case TargetOpcode::G_FLOG:
2340 case TargetOpcode::G_FLOG2:
2341 case TargetOpcode::G_FLOG10:
2342 case TargetOpcode::G_FPOW:
2343 case TargetOpcode::G_FPOWI:
2344 case TargetOpcode::G_FLDEXP:
2345 case TargetOpcode::G_STRICT_FLDEXP:
2346 case TargetOpcode::G_FFREXP:
2347 case TargetOpcode::G_INTRINSIC_TRUNC:
2348 case TargetOpcode::G_INTRINSIC_ROUND:
2349 case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
2350 case TargetOpcode::G_FFLOOR:
2351 case TargetOpcode::G_FCEIL:
2352 case TargetOpcode::G_FRINT:
2353 case TargetOpcode::G_FNEARBYINT:
2354 case TargetOpcode::G_FPEXT:
2355 case TargetOpcode::G_FPTRUNC:
2356 case TargetOpcode::G_FCANONICALIZE:
2357 case TargetOpcode::G_FMINNUM:
2358 case TargetOpcode::G_FMAXNUM:
2359 case TargetOpcode::G_FMINNUM_IEEE:
2360 case TargetOpcode::G_FMAXNUM_IEEE:
2361 case TargetOpcode::G_FMINIMUM:
2362 case TargetOpcode::G_FMAXIMUM:
2363 case TargetOpcode::G_FMINIMUMNUM:
2364 case TargetOpcode::G_FMAXIMUMNUM:
2365 return true;
2366 }
2367 }
2368
2369 KnownFPClass FPClass = computeKnownFPClass(R: Val, InterestedClasses: SNaN ? fcSNan : fcNan);
2370
2371 if (SNaN)
2372 return FPClass.isKnownNever(Mask: fcSNan);
2373
2374 return FPClass.isKnownNeverNaN();
2375}
2376
2377bool GISelValueTracking::isKnownNeverLogicalZero(Register Val, unsigned Depth) {
2378 KnownFPClass Known = computeKnownFPClass(R: Val, InterestedClasses: fcZero | fcSubnormal, Depth);
2379 LLT Ty = MRI.getType(Reg: Val).getScalarType();
2380 return Known.isKnownNeverLogicalZero(
2381 Mode: MF.getDenormalMode(FPType: getFltSemanticForLLT(Ty)));
2382}
2383
2384/// Compute number of sign bits for the intersection of \p Src0 and \p Src1
2385unsigned GISelValueTracking::computeNumSignBitsMin(Register Src0, Register Src1,
2386 const APInt &DemandedElts,
2387 unsigned Depth) {
2388 // Test src1 first, since we canonicalize simpler expressions to the RHS.
2389 unsigned Src1SignBits = computeNumSignBits(R: Src1, DemandedElts, Depth);
2390 if (Src1SignBits == 1)
2391 return 1;
2392 return std::min(a: computeNumSignBits(R: Src0, DemandedElts, Depth), b: Src1SignBits);
2393}
2394
2395/// Compute the known number of sign bits with attached range metadata in the
2396/// memory operand. If this is an extending load, accounts for the behavior of
2397/// the high bits.
2398static unsigned computeNumSignBitsFromRangeMetadata(const GAnyLoad *Ld,
2399 unsigned TyBits) {
2400 const MDNode *Ranges = Ld->getRanges();
2401 if (!Ranges)
2402 return 1;
2403
2404 ConstantRange CR = getConstantRangeFromMetadata(RangeMD: *Ranges);
2405 if (TyBits > CR.getBitWidth()) {
2406 switch (Ld->getOpcode()) {
2407 case TargetOpcode::G_SEXTLOAD:
2408 CR = CR.signExtend(BitWidth: TyBits);
2409 break;
2410 case TargetOpcode::G_ZEXTLOAD:
2411 CR = CR.zeroExtend(BitWidth: TyBits);
2412 break;
2413 default:
2414 break;
2415 }
2416 }
2417
2418 return std::min(a: CR.getSignedMin().getNumSignBits(),
2419 b: CR.getSignedMax().getNumSignBits());
2420}
2421
2422unsigned GISelValueTracking::computeNumSignBits(Register R,
2423 const APInt &DemandedElts,
2424 unsigned Depth) {
2425 MachineInstr &MI = *MRI.getVRegDef(Reg: R);
2426 unsigned Opcode = MI.getOpcode();
2427
2428 if (Opcode == TargetOpcode::G_CONSTANT)
2429 return MI.getOperand(i: 1).getCImm()->getValue().getNumSignBits();
2430
2431 if (Depth == getMaxDepth())
2432 return 1;
2433
2434 if (!DemandedElts)
2435 return 1; // No demanded elts, better to assume we don't know anything.
2436
2437 LLT DstTy = MRI.getType(Reg: R);
2438 const unsigned TyBits = DstTy.getScalarSizeInBits();
2439
2440 // Handle the case where this is called on a register that does not have a
2441 // type constraint. This is unlikely to occur except by looking through copies
2442 // but it is possible for the initial register being queried to be in this
2443 // state.
2444 if (!DstTy.isValid())
2445 return 1;
2446
2447 unsigned FirstAnswer = 1;
2448 switch (Opcode) {
2449 case TargetOpcode::COPY: {
2450 MachineOperand &Src = MI.getOperand(i: 1);
2451 if (Src.getReg().isVirtual() && Src.getSubReg() == 0 &&
2452 MRI.getType(Reg: Src.getReg()).isValid()) {
2453 // Don't increment Depth for this one since we didn't do any work.
2454 return computeNumSignBits(R: Src.getReg(), DemandedElts, Depth);
2455 }
2456
2457 return 1;
2458 }
2459 case TargetOpcode::G_SEXT: {
2460 Register Src = MI.getOperand(i: 1).getReg();
2461 LLT SrcTy = MRI.getType(Reg: Src);
2462 unsigned Tmp = TyBits - SrcTy.getScalarSizeInBits();
2463 return computeNumSignBits(R: Src, DemandedElts, Depth: Depth + 1) + Tmp;
2464 }
2465 case TargetOpcode::G_ASSERT_SEXT:
2466 case TargetOpcode::G_SEXT_INREG: {
2467 // Max of the input and what this extends.
2468 Register Src = MI.getOperand(i: 1).getReg();
2469 unsigned SrcBits = MI.getOperand(i: 2).getImm();
2470 unsigned InRegBits = TyBits - SrcBits + 1;
2471 return std::max(a: computeNumSignBits(R: Src, DemandedElts, Depth: Depth + 1),
2472 b: InRegBits);
2473 }
2474 case TargetOpcode::G_LOAD: {
2475 GLoad *Ld = cast<GLoad>(Val: &MI);
2476 if (DemandedElts != 1 || !getDataLayout().isLittleEndian())
2477 break;
2478
2479 return computeNumSignBitsFromRangeMetadata(Ld, TyBits);
2480 }
2481 case TargetOpcode::G_SEXTLOAD: {
2482 GSExtLoad *Ld = cast<GSExtLoad>(Val: &MI);
2483
2484 // FIXME: We need an in-memory type representation.
2485 if (DstTy.isVector())
2486 return 1;
2487
2488 unsigned NumBits = computeNumSignBitsFromRangeMetadata(Ld, TyBits);
2489 if (NumBits != 1)
2490 return NumBits;
2491
2492 // e.g. i16->i32 = '17' bits known.
2493 const MachineMemOperand *MMO = *MI.memoperands_begin();
2494 return TyBits - MMO->getSizeInBits().getValue() + 1;
2495 }
2496 case TargetOpcode::G_ZEXTLOAD: {
2497 GZExtLoad *Ld = cast<GZExtLoad>(Val: &MI);
2498
2499 // FIXME: We need an in-memory type representation.
2500 if (DstTy.isVector())
2501 return 1;
2502
2503 unsigned NumBits = computeNumSignBitsFromRangeMetadata(Ld, TyBits);
2504 if (NumBits != 1)
2505 return NumBits;
2506
2507 // e.g. i16->i32 = '16' bits known.
2508 const MachineMemOperand *MMO = *MI.memoperands_begin();
2509 return TyBits - MMO->getSizeInBits().getValue();
2510 }
2511 case TargetOpcode::G_AND:
2512 case TargetOpcode::G_OR:
2513 case TargetOpcode::G_XOR: {
2514 Register Src1 = MI.getOperand(i: 1).getReg();
2515 unsigned Src1NumSignBits =
2516 computeNumSignBits(R: Src1, DemandedElts, Depth: Depth + 1);
2517 if (Src1NumSignBits != 1) {
2518 Register Src2 = MI.getOperand(i: 2).getReg();
2519 unsigned Src2NumSignBits =
2520 computeNumSignBits(R: Src2, DemandedElts, Depth: Depth + 1);
2521 FirstAnswer = std::min(a: Src1NumSignBits, b: Src2NumSignBits);
2522 }
2523 break;
2524 }
2525 case TargetOpcode::G_ASHR: {
2526 Register Src1 = MI.getOperand(i: 1).getReg();
2527 Register Src2 = MI.getOperand(i: 2).getReg();
2528 FirstAnswer = computeNumSignBits(R: Src1, DemandedElts, Depth: Depth + 1);
2529 if (auto C = getValidMinimumShiftAmount(R: Src2, DemandedElts, Depth: Depth + 1))
2530 FirstAnswer = std::min<uint64_t>(a: FirstAnswer + *C, b: TyBits);
2531 break;
2532 }
2533 case TargetOpcode::G_SHL: {
2534 Register Src1 = MI.getOperand(i: 1).getReg();
2535 Register Src2 = MI.getOperand(i: 2).getReg();
2536 if (std::optional<ConstantRange> ShAmtRange =
2537 getValidShiftAmountRange(R: Src2, DemandedElts, Depth: Depth + 1)) {
2538 uint64_t MaxShAmt = ShAmtRange->getUnsignedMax().getZExtValue();
2539 uint64_t MinShAmt = ShAmtRange->getUnsignedMin().getZExtValue();
2540
2541 MachineInstr &ExtMI = *MRI.getVRegDef(Reg: Src1);
2542 unsigned ExtOpc = ExtMI.getOpcode();
2543
2544 // Try to look through ZERO/SIGN/ANY_EXTEND. If all extended bits are
2545 // shifted out, then we can compute the number of sign bits for the
2546 // operand being extended. A future improvement could be to pass along the
2547 // "shifted left by" information in the recursive calls to
2548 // ComputeKnownSignBits. Allowing us to handle this more generically.
2549 if (ExtOpc == TargetOpcode::G_SEXT || ExtOpc == TargetOpcode::G_ZEXT ||
2550 ExtOpc == TargetOpcode::G_ANYEXT) {
2551 LLT ExtTy = MRI.getType(Reg: Src1);
2552 Register Extendee = ExtMI.getOperand(i: 1).getReg();
2553 LLT ExtendeeTy = MRI.getType(Reg: Extendee);
2554 uint64_t SizeDiff =
2555 ExtTy.getScalarSizeInBits() - ExtendeeTy.getScalarSizeInBits();
2556
2557 if (SizeDiff <= MinShAmt) {
2558 unsigned Tmp =
2559 SizeDiff + computeNumSignBits(R: Extendee, DemandedElts, Depth: Depth + 1);
2560 if (MaxShAmt < Tmp)
2561 return Tmp - MaxShAmt;
2562 }
2563 }
2564 // shl destroys sign bits, ensure it doesn't shift out all sign bits.
2565 unsigned Tmp = computeNumSignBits(R: Src1, DemandedElts, Depth: Depth + 1);
2566 if (MaxShAmt < Tmp)
2567 return Tmp - MaxShAmt;
2568 }
2569 break;
2570 }
2571 case TargetOpcode::G_ROTL:
2572 case TargetOpcode::G_ROTR: {
2573 Register SrcReg = MI.getOperand(i: 1).getReg();
2574 unsigned Tmp = computeNumSignBits(R: SrcReg, DemandedElts, Depth: Depth + 1);
2575 auto MaybeAmt =
2576 isConstantOrConstantSplatVector(Def: MI.getOperand(i: 2).getReg(), MRI);
2577 FirstAnswer =
2578 SignBitsOps::rot(SrcSignBits: Tmp, BitWidth: TyBits, RotAmt: MaybeAmt, IsRotateRight: Opcode == TargetOpcode::G_ROTR);
2579 break;
2580 }
2581 case TargetOpcode::G_SAVGFLOOR:
2582 case TargetOpcode::G_SAVGCEIL: {
2583 Register Src1 = MI.getOperand(i: 1).getReg();
2584 Register Src2 = MI.getOperand(i: 2).getReg();
2585 FirstAnswer = computeNumSignBitsMin(Src0: Src1, Src1: Src2, DemandedElts, Depth: Depth + 1);
2586 break;
2587 }
2588 case TargetOpcode::G_SREM: {
2589 // The sign bit is the LHS's sign bit, except when the result of the
2590 // remainder is zero. The magnitude of the result should be less than or
2591 // equal to the magnitude of the LHS. Therefore, the result should have
2592 // at least as many sign bits as the left hand side.
2593 Register Src = MI.getOperand(i: 1).getReg();
2594 return computeNumSignBits(R: Src, DemandedElts, Depth: Depth + 1);
2595 }
2596 case TargetOpcode::G_TRUNC: {
2597 Register Src = MI.getOperand(i: 1).getReg();
2598 LLT SrcTy = MRI.getType(Reg: Src);
2599
2600 // Check if the sign bits of source go down as far as the truncated value.
2601 unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
2602 unsigned NumSrcSignBits = computeNumSignBits(R: Src, DemandedElts, Depth: Depth + 1);
2603 if (NumSrcSignBits > (NumSrcBits - TyBits))
2604 return NumSrcSignBits - (NumSrcBits - TyBits);
2605 break;
2606 }
2607 case TargetOpcode::G_SELECT: {
2608 return computeNumSignBitsMin(Src0: MI.getOperand(i: 2).getReg(),
2609 Src1: MI.getOperand(i: 3).getReg(), DemandedElts,
2610 Depth: Depth + 1);
2611 }
2612 case TargetOpcode::G_SMIN:
2613 case TargetOpcode::G_SMAX:
2614 case TargetOpcode::G_UMIN:
2615 case TargetOpcode::G_UMAX:
2616 // TODO: Handle clamp pattern with number of sign bits for SMIN/SMAX.
2617 return computeNumSignBitsMin(Src0: MI.getOperand(i: 1).getReg(),
2618 Src1: MI.getOperand(i: 2).getReg(), DemandedElts,
2619 Depth: Depth + 1);
2620 case TargetOpcode::G_SADDO:
2621 case TargetOpcode::G_SADDE:
2622 case TargetOpcode::G_UADDO:
2623 case TargetOpcode::G_UADDE:
2624 case TargetOpcode::G_SSUBO:
2625 case TargetOpcode::G_SSUBE:
2626 case TargetOpcode::G_USUBO:
2627 case TargetOpcode::G_USUBE:
2628 case TargetOpcode::G_SMULO:
2629 case TargetOpcode::G_UMULO: {
2630 // If compares returns 0/-1, all bits are sign bits.
2631 // We know that we have an integer-based boolean since these operations
2632 // are only available for integer.
2633 if (MI.getOperand(i: 1).getReg() == R) {
2634 if (TL.getBooleanContents(isVec: DstTy.isVector(), isFloat: false) ==
2635 TargetLowering::ZeroOrNegativeOneBooleanContent)
2636 return TyBits;
2637 }
2638
2639 break;
2640 }
2641 case TargetOpcode::G_SUB: {
2642 Register Src2 = MI.getOperand(i: 2).getReg();
2643 unsigned Src2NumSignBits =
2644 computeNumSignBits(R: Src2, DemandedElts, Depth: Depth + 1);
2645 if (Src2NumSignBits == 1)
2646 return 1; // Early out.
2647
2648 // Handle NEG.
2649 Register Src1 = MI.getOperand(i: 1).getReg();
2650 KnownBits Known1 = getKnownBits(R: Src1, DemandedElts, Depth);
2651 if (Known1.isZero()) {
2652 KnownBits Known2 = getKnownBits(R: Src2, DemandedElts, Depth);
2653 // If the input is known to be 0 or 1, the output is 0/-1, which is all
2654 // sign bits set.
2655 if ((Known2.Zero | 1).isAllOnes())
2656 return TyBits;
2657
2658 // If the input is known to be positive (the sign bit is known clear),
2659 // the output of the NEG has, at worst, the same number of sign bits as
2660 // the input.
2661 if (Known2.isNonNegative()) {
2662 FirstAnswer = Src2NumSignBits;
2663 break;
2664 }
2665
2666 // Otherwise, we treat this like a SUB.
2667 }
2668
2669 unsigned Src1NumSignBits =
2670 computeNumSignBits(R: Src1, DemandedElts, Depth: Depth + 1);
2671 if (Src1NumSignBits == 1)
2672 return 1; // Early Out.
2673
2674 // Sub can have at most one carry bit. Thus we know that the output
2675 // is, at worst, one more bit than the inputs.
2676 FirstAnswer = std::min(a: Src1NumSignBits, b: Src2NumSignBits) - 1;
2677 break;
2678 }
2679 case TargetOpcode::G_ADD: {
2680 Register Src2 = MI.getOperand(i: 2).getReg();
2681 unsigned Src2NumSignBits =
2682 computeNumSignBits(R: Src2, DemandedElts, Depth: Depth + 1);
2683 if (Src2NumSignBits <= 2)
2684 return 1; // Early out.
2685
2686 Register Src1 = MI.getOperand(i: 1).getReg();
2687 unsigned Src1NumSignBits =
2688 computeNumSignBits(R: Src1, DemandedElts, Depth: Depth + 1);
2689 if (Src1NumSignBits == 1)
2690 return 1; // Early Out.
2691
2692 // Special case decrementing a value (ADD X, -1):
2693 KnownBits Known2 = getKnownBits(R: Src2, DemandedElts, Depth);
2694 if (Known2.isAllOnes()) {
2695 KnownBits Known1 = getKnownBits(R: Src1, DemandedElts, Depth);
2696 // If the input is known to be 0 or 1, the output is 0/-1, which is all
2697 // sign bits set.
2698 if ((Known1.Zero | 1).isAllOnes())
2699 return TyBits;
2700
2701 // If we are subtracting one from a positive number, there is no carry
2702 // out of the result.
2703 if (Known1.isNonNegative()) {
2704 FirstAnswer = Src1NumSignBits;
2705 break;
2706 }
2707
2708 // Otherwise, we treat this like an ADD.
2709 }
2710
2711 // Add can have at most one carry bit. Thus we know that the output
2712 // is, at worst, one more bit than the inputs.
2713 FirstAnswer = std::min(a: Src1NumSignBits, b: Src2NumSignBits) - 1;
2714 break;
2715 }
2716 case TargetOpcode::G_FCMP:
2717 case TargetOpcode::G_ICMP: {
2718 bool IsFP = Opcode == TargetOpcode::G_FCMP;
2719 if (TyBits == 1)
2720 break;
2721 auto BC = TL.getBooleanContents(isVec: DstTy.isVector(), isFloat: IsFP);
2722 if (BC == TargetLoweringBase::ZeroOrNegativeOneBooleanContent)
2723 return TyBits; // All bits are sign bits.
2724 if (BC == TargetLowering::ZeroOrOneBooleanContent)
2725 return TyBits - 1; // Every always-zero bit is a sign bit.
2726 break;
2727 }
2728 case TargetOpcode::G_UNMERGE_VALUES: {
2729 unsigned NumOps = MI.getNumOperands();
2730 Register SrcReg = MI.getOperand(i: NumOps - 1).getReg();
2731 LLT SrcTy = MRI.getType(Reg: SrcReg);
2732
2733 if ((SrcTy.isVector() && SrcTy.getScalarType() != DstTy.getScalarType()) ||
2734 (SrcTy.isScalar() && DstTy.isVector()))
2735 break;
2736
2737 // Figure out the result operand index
2738 unsigned DstIdx = MI.findRegisterDefOperandIdx(Reg: R, TRI: nullptr);
2739
2740 APInt SubDemandedElts = DemandedElts;
2741 unsigned DstLanes = DstTy.isVector() ? DstTy.getNumElements() : 1;
2742 if (SrcTy.isVector()) {
2743 SubDemandedElts =
2744 DemandedElts.zext(width: SrcTy.getNumElements()).shl(shiftAmt: DstIdx * DstLanes);
2745 }
2746
2747 unsigned SrcOpKnown =
2748 computeNumSignBits(R: SrcReg, DemandedElts: SubDemandedElts, Depth: Depth + 1);
2749 if (SrcTy.isVector()) {
2750 FirstAnswer = SrcOpKnown;
2751 } else if (SrcOpKnown >= (MI.getNumOperands() - DstIdx - 2) * TyBits) {
2752 FirstAnswer = SrcOpKnown >= (MI.getNumOperands() - DstIdx - 1) * TyBits
2753 ? TyBits
2754 : SrcOpKnown % TyBits;
2755 }
2756 break;
2757 }
2758 case TargetOpcode::G_BUILD_VECTOR: {
2759 // Collect the known bits that are shared by every demanded vector element.
2760 FirstAnswer = TyBits;
2761 APInt SingleDemandedElt(1, 1);
2762 for (const auto &[I, MO] : enumerate(First: drop_begin(RangeOrContainer: MI.operands()))) {
2763 if (!DemandedElts[I])
2764 continue;
2765
2766 unsigned Tmp2 =
2767 computeNumSignBits(R: MO.getReg(), DemandedElts: SingleDemandedElt, Depth: Depth + 1);
2768 FirstAnswer = std::min(a: FirstAnswer, b: Tmp2);
2769
2770 // If we don't know any bits, early out.
2771 if (FirstAnswer == 1)
2772 break;
2773 }
2774 break;
2775 }
2776 case TargetOpcode::G_CONCAT_VECTORS: {
2777 if (MRI.getType(Reg: MI.getOperand(i: 0).getReg()).isScalableVector())
2778 break;
2779 FirstAnswer = TyBits;
2780 // Determine the minimum number of sign bits across all demanded
2781 // elts of the input vectors. Early out if the result is already 1.
2782 unsigned NumSubVectorElts =
2783 MRI.getType(Reg: MI.getOperand(i: 1).getReg()).getNumElements();
2784 for (const auto &[I, MO] : enumerate(First: drop_begin(RangeOrContainer: MI.operands()))) {
2785 APInt DemandedSub =
2786 DemandedElts.extractBits(numBits: NumSubVectorElts, bitPosition: I * NumSubVectorElts);
2787 if (!DemandedSub)
2788 continue;
2789 unsigned Tmp2 = computeNumSignBits(R: MO.getReg(), DemandedElts: DemandedSub, Depth: Depth + 1);
2790
2791 FirstAnswer = std::min(a: FirstAnswer, b: Tmp2);
2792
2793 // If we don't know any bits, early out.
2794 if (FirstAnswer == 1)
2795 break;
2796 }
2797 break;
2798 }
2799 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
2800 GExtractVectorElement &Extract = cast<GExtractVectorElement>(Val&: MI);
2801 Register InVec = Extract.getVectorReg();
2802 Register EltNo = Extract.getIndexReg();
2803 LLT VecVT = MRI.getType(Reg: InVec);
2804 if (VecVT.isScalableVector())
2805 return computeNumSignBits(R: InVec, DemandedElts: APInt(1, 1), Depth: Depth + 1);
2806 unsigned NumSrcElts = VecVT.getNumElements();
2807 std::optional<APInt> ConstEltNo = getIConstantVRegVal(VReg: EltNo, MRI);
2808 APInt DemandedSrcElts =
2809 ConstEltNo && ConstEltNo->ult(RHS: NumSrcElts)
2810 ? APInt::getOneBitSet(numBits: NumSrcElts, BitNo: ConstEltNo->getZExtValue())
2811 : APInt::getAllOnes(numBits: NumSrcElts);
2812 return computeNumSignBits(R: InVec, DemandedElts: DemandedSrcElts, Depth: Depth + 1);
2813 }
2814 case TargetOpcode::G_EXTRACT_SUBVECTOR: {
2815 // Offset the demanded elts by the subvector index.
2816 Register SrcReg = MI.getOperand(i: 1).getReg();
2817 LLT SrcTy = MRI.getType(Reg: SrcReg);
2818 APInt DemandedSrcElts;
2819 if (SrcTy.isScalableVector()) {
2820 DemandedSrcElts = APInt(1, 1);
2821 } else {
2822 uint64_t Idx = MI.getOperand(i: 2).getImm();
2823 unsigned NumSrcElts = SrcTy.getNumElements();
2824 DemandedSrcElts = DemandedElts.zext(width: NumSrcElts).shl(shiftAmt: Idx);
2825 }
2826 return computeNumSignBits(R: SrcReg, DemandedElts: DemandedSrcElts, Depth: Depth + 1);
2827 }
2828 case TargetOpcode::G_SHUFFLE_VECTOR: {
2829 // Collect the minimum number of sign bits that are shared by every vector
2830 // element referenced by the shuffle.
2831 APInt DemandedLHS, DemandedRHS;
2832 Register Src1 = MI.getOperand(i: 1).getReg();
2833 unsigned NumElts = MRI.getType(Reg: Src1).getNumElements();
2834 if (!getShuffleDemandedElts(SrcWidth: NumElts, Mask: MI.getOperand(i: 3).getShuffleMask(),
2835 DemandedElts, DemandedLHS, DemandedRHS))
2836 return 1;
2837
2838 if (!!DemandedLHS)
2839 FirstAnswer = computeNumSignBits(R: Src1, DemandedElts: DemandedLHS, Depth: Depth + 1);
2840 // If we don't know anything, early out and try computeKnownBits fall-back.
2841 if (FirstAnswer == 1)
2842 break;
2843 if (!!DemandedRHS) {
2844 unsigned Tmp2 =
2845 computeNumSignBits(R: MI.getOperand(i: 2).getReg(), DemandedElts: DemandedRHS, Depth: Depth + 1);
2846 FirstAnswer = std::min(a: FirstAnswer, b: Tmp2);
2847 }
2848 break;
2849 }
2850 case TargetOpcode::G_SPLAT_VECTOR: {
2851 // Check if the sign bits of source go down as far as the truncated value.
2852 Register Src = MI.getOperand(i: 1).getReg();
2853 unsigned NumSrcSignBits = computeNumSignBits(R: Src, DemandedElts: APInt(1, 1), Depth: Depth + 1);
2854 unsigned NumSrcBits = MRI.getType(Reg: Src).getSizeInBits();
2855 if (NumSrcSignBits > (NumSrcBits - TyBits))
2856 return NumSrcSignBits - (NumSrcBits - TyBits);
2857 break;
2858 }
2859 case TargetOpcode::G_INTRINSIC:
2860 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
2861 case TargetOpcode::G_INTRINSIC_CONVERGENT:
2862 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
2863 default: {
2864 unsigned NumBits =
2865 TL.computeNumSignBitsForTargetInstr(Analysis&: *this, R, DemandedElts, MRI, Depth);
2866 if (NumBits > 1)
2867 FirstAnswer = std::max(a: FirstAnswer, b: NumBits);
2868 break;
2869 }
2870 }
2871
2872 // Finally, if we can prove that the top bits of the result are 0's or 1's,
2873 // use this information.
2874 KnownBits Known = getKnownBits(R, DemandedElts, Depth);
2875 return std::max(a: FirstAnswer, b: Known.countMinSignBits());
2876}
2877
2878unsigned GISelValueTracking::computeNumSignBits(Register R, unsigned Depth) {
2879 LLT Ty = MRI.getType(Reg: R);
2880 APInt DemandedElts =
2881 Ty.isFixedVector() ? APInt::getAllOnes(numBits: Ty.getNumElements()) : APInt(1, 1);
2882 return computeNumSignBits(R, DemandedElts, Depth);
2883}
2884
2885std::optional<ConstantRange> GISelValueTracking::getValidShiftAmountRange(
2886 Register R, const APInt &DemandedElts, unsigned Depth) {
2887 // Shifting more than the bitwidth is not valid.
2888 MachineInstr &MI = *MRI.getVRegDef(Reg: R);
2889 unsigned Opcode = MI.getOpcode();
2890
2891 LLT Ty = MRI.getType(Reg: R);
2892 unsigned BitWidth = Ty.getScalarSizeInBits();
2893
2894 if (Opcode == TargetOpcode::G_CONSTANT) {
2895 const APInt &ShAmt = MI.getOperand(i: 1).getCImm()->getValue();
2896 if (ShAmt.uge(RHS: BitWidth))
2897 return std::nullopt;
2898 return ConstantRange(ShAmt);
2899 }
2900
2901 if (Opcode == TargetOpcode::G_BUILD_VECTOR) {
2902 const APInt *MinAmt = nullptr, *MaxAmt = nullptr;
2903 for (unsigned I = 0, E = MI.getNumOperands() - 1; I != E; ++I) {
2904 if (!DemandedElts[I])
2905 continue;
2906 MachineInstr *Op = MRI.getVRegDef(Reg: MI.getOperand(i: I + 1).getReg());
2907 if (Op->getOpcode() != TargetOpcode::G_CONSTANT) {
2908 MinAmt = MaxAmt = nullptr;
2909 break;
2910 }
2911
2912 const APInt &ShAmt = Op->getOperand(i: 1).getCImm()->getValue();
2913 if (ShAmt.uge(RHS: BitWidth))
2914 return std::nullopt;
2915 if (!MinAmt || MinAmt->ugt(RHS: ShAmt))
2916 MinAmt = &ShAmt;
2917 if (!MaxAmt || MaxAmt->ult(RHS: ShAmt))
2918 MaxAmt = &ShAmt;
2919 }
2920 assert(((!MinAmt && !MaxAmt) || (MinAmt && MaxAmt)) &&
2921 "Failed to find matching min/max shift amounts");
2922 if (MinAmt && MaxAmt)
2923 return ConstantRange(*MinAmt, *MaxAmt + 1);
2924 }
2925
2926 // Use computeKnownBits to find a hidden constant/knownbits (usually type
2927 // legalized). e.g. Hidden behind multiple bitcasts/build_vector/casts etc.
2928 KnownBits KnownAmt = getKnownBits(R, DemandedElts, Depth);
2929 if (KnownAmt.getMaxValue().ult(RHS: BitWidth))
2930 return ConstantRange::fromKnownBits(Known: KnownAmt, /*IsSigned=*/false);
2931
2932 return std::nullopt;
2933}
2934
2935std::optional<uint64_t> GISelValueTracking::getValidMinimumShiftAmount(
2936 Register R, const APInt &DemandedElts, unsigned Depth) {
2937 if (std::optional<ConstantRange> AmtRange =
2938 getValidShiftAmountRange(R, DemandedElts, Depth))
2939 return AmtRange->getUnsignedMin().getZExtValue();
2940 return std::nullopt;
2941}
2942
2943void GISelValueTrackingAnalysisLegacy::getAnalysisUsage(
2944 AnalysisUsage &AU) const {
2945 AU.setPreservesAll();
2946 MachineFunctionPass::getAnalysisUsage(AU);
2947}
2948
2949bool GISelValueTrackingAnalysisLegacy::runOnMachineFunction(
2950 MachineFunction &MF) {
2951 return false;
2952}
2953
2954GISelValueTracking &GISelValueTrackingAnalysisLegacy::get(MachineFunction &MF) {
2955 if (!Info) {
2956 unsigned MaxDepth =
2957 MF.getTarget().getOptLevel() == CodeGenOptLevel::None ? 2 : 6;
2958 Info = std::make_unique<GISelValueTracking>(args&: MF, args&: MaxDepth);
2959 }
2960 return *Info;
2961}
2962
2963AnalysisKey GISelValueTrackingAnalysis::Key;
2964
2965GISelValueTrackingAnalysis::Result
2966GISelValueTrackingAnalysis::run(MachineFunction &MF,
2967 MachineFunctionAnalysisManager &MFAM) {
2968 unsigned MaxDepth =
2969 MF.getTarget().getOptLevel() == CodeGenOptLevel::None ? 2 : 6;
2970 return Result(MF, MaxDepth);
2971}
2972
2973PreservedAnalyses
2974GISelValueTrackingPrinterPass::run(MachineFunction &MF,
2975 MachineFunctionAnalysisManager &MFAM) {
2976 auto &VTA = MFAM.getResult<GISelValueTrackingAnalysis>(IR&: MF);
2977 const auto &MRI = MF.getRegInfo();
2978 OS << "name: ";
2979 MF.getFunction().printAsOperand(O&: OS, /*PrintType=*/false);
2980 OS << '\n';
2981
2982 for (MachineBasicBlock &BB : MF) {
2983 for (MachineInstr &MI : BB) {
2984 for (MachineOperand &MO : MI.defs()) {
2985 if (!MO.isReg() || MO.getReg().isPhysical())
2986 continue;
2987 Register Reg = MO.getReg();
2988 if (!MRI.getType(Reg).isValid())
2989 continue;
2990 KnownBits Known = VTA.getKnownBits(R: Reg);
2991 unsigned SignedBits = VTA.computeNumSignBits(R: Reg);
2992 bool IsKnownNeverZero = VTA.isKnownNeverZero(R: Reg);
2993 OS << " " << MO << " KnownBits:" << Known << " SignBits:" << SignedBits
2994 << " IsKnownNeverZero:" << IsKnownNeverZero << '\n';
2995 };
2996 }
2997 }
2998 return PreservedAnalyses::all();
2999}
3000