1//===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file implements the LegalizerHelper class to legalize
10/// individual instructions and the LegalizeMachineIR wrapper pass for the
11/// primary legalization.
12//
13//===----------------------------------------------------------------------===//
14
15#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16#include "llvm/CodeGen/GlobalISel/CallLowering.h"
17#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"
19#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
20#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
21#include "llvm/CodeGen/GlobalISel/LostDebugLocObserver.h"
22#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
23#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
24#include "llvm/CodeGen/GlobalISel/Utils.h"
25#include "llvm/CodeGen/LowLevelTypeUtils.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/RuntimeLibcallUtil.h"
30#include "llvm/CodeGen/TargetFrameLowering.h"
31#include "llvm/CodeGen/TargetInstrInfo.h"
32#include "llvm/CodeGen/TargetLowering.h"
33#include "llvm/CodeGen/TargetOpcodes.h"
34#include "llvm/CodeGen/TargetSubtargetInfo.h"
35#include "llvm/IR/Instructions.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/MathExtras.h"
38#include "llvm/Support/raw_ostream.h"
39#include "llvm/Target/TargetMachine.h"
40#include <cassert>
41#include <numeric>
42#include <optional>
43
44#define DEBUG_TYPE "legalizer"
45
46using namespace llvm;
47using namespace LegalizeActions;
48using namespace MIPatternMatch;
49
50/// Try to break down \p OrigTy into \p NarrowTy sized pieces.
51///
52/// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
53/// with any leftover piece as type \p LeftoverTy
54///
55/// Returns -1 in the first element of the pair if the breakdown is not
56/// satisfiable.
57static std::pair<int, int>
58getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
59 assert(!LeftoverTy.isValid() && "this is an out argument");
60
61 unsigned Size = OrigTy.getSizeInBits();
62 unsigned NarrowSize = NarrowTy.getSizeInBits();
63 unsigned NumParts = Size / NarrowSize;
64 unsigned LeftoverSize = Size - NumParts * NarrowSize;
65 assert(Size > NarrowSize);
66
67 if (LeftoverSize == 0)
68 return {NumParts, 0};
69
70 if (NarrowTy.isVector()) {
71 unsigned EltSize = OrigTy.getScalarSizeInBits();
72 if (LeftoverSize % EltSize != 0)
73 return {-1, -1};
74 LeftoverTy = OrigTy.changeElementCount(
75 EC: ElementCount::getFixed(MinVal: LeftoverSize / EltSize));
76 } else {
77 LeftoverTy = LLT::integer(SizeInBits: LeftoverSize);
78 }
79
80 int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
81 return std::make_pair(x&: NumParts, y&: NumLeftover);
82}
83
84static Type *getFloatTypeForLLT(LLVMContext &Ctx, LLT Ty) {
85
86 if (!Ty.isScalar())
87 return nullptr;
88
89 switch (Ty.getSizeInBits()) {
90 case 16:
91 return Type::getHalfTy(C&: Ctx);
92 case 32:
93 return Type::getFloatTy(C&: Ctx);
94 case 64:
95 return Type::getDoubleTy(C&: Ctx);
96 case 80:
97 return Type::getX86_FP80Ty(C&: Ctx);
98 case 128:
99 return Type::getFP128Ty(C&: Ctx);
100 default:
101 return nullptr;
102 }
103}
104
105LegalizerHelper::LegalizerHelper(MachineFunction &MF,
106 GISelChangeObserver &Observer,
107 MachineIRBuilder &Builder,
108 const LibcallLoweringInfo *Libcalls)
109 : MIRBuilder(Builder), Observer(Observer), MRI(MF.getRegInfo()),
110 LI(*MF.getSubtarget().getLegalizerInfo()),
111 TLI(*MF.getSubtarget().getTargetLowering()), Libcalls(Libcalls) {}
112
113LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
114 GISelChangeObserver &Observer,
115 MachineIRBuilder &B,
116 const LibcallLoweringInfo *Libcalls,
117 GISelValueTracking *VT)
118 : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI),
119 TLI(*MF.getSubtarget().getTargetLowering()), Libcalls(Libcalls), VT(VT) {}
120
121LegalizerHelper::LegalizeResult
122LegalizerHelper::legalizeInstrStep(MachineInstr &MI,
123 LostDebugLocObserver &LocObserver) {
124 LLVM_DEBUG(dbgs() << "\nLegalizing: " << MI);
125
126 MIRBuilder.setInstrAndDebugLoc(MI);
127
128 if (isa<GIntrinsic>(Val: MI))
129 return LI.legalizeIntrinsic(Helper&: *this, MI) ? Legalized : UnableToLegalize;
130 auto Step = LI.getAction(MI, MRI);
131 switch (Step.Action) {
132 case Legal:
133 LLVM_DEBUG(dbgs() << ".. Already legal\n");
134 return AlreadyLegal;
135 case Libcall:
136 LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
137 return libcall(MI, LocObserver);
138 case NarrowScalar:
139 LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
140 return narrowScalar(MI, TypeIdx: Step.TypeIdx, NarrowTy: Step.NewType);
141 case WidenScalar:
142 LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
143 return widenScalar(MI, TypeIdx: Step.TypeIdx, WideTy: Step.NewType);
144 case Bitcast:
145 LLVM_DEBUG(dbgs() << ".. Bitcast type\n");
146 return bitcast(MI, TypeIdx: Step.TypeIdx, Ty: Step.NewType);
147 case Lower:
148 LLVM_DEBUG(dbgs() << ".. Lower\n");
149 return lower(MI, TypeIdx: Step.TypeIdx, Ty: Step.NewType);
150 case FewerElements:
151 LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
152 return fewerElementsVector(MI, TypeIdx: Step.TypeIdx, NarrowTy: Step.NewType);
153 case MoreElements:
154 LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
155 return moreElementsVector(MI, TypeIdx: Step.TypeIdx, MoreTy: Step.NewType);
156 case Custom:
157 LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
158 return LI.legalizeCustom(Helper&: *this, MI, LocObserver) ? Legalized
159 : UnableToLegalize;
160 default:
161 LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
162 return UnableToLegalize;
163 }
164}
165
166void LegalizerHelper::insertParts(Register DstReg,
167 LLT ResultTy, LLT PartTy,
168 ArrayRef<Register> PartRegs,
169 LLT LeftoverTy,
170 ArrayRef<Register> LeftoverRegs) {
171 if (!LeftoverTy.isValid()) {
172 assert(LeftoverRegs.empty());
173
174 if (!ResultTy.isVector()) {
175 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: PartRegs);
176 return;
177 }
178
179 if (PartTy.isVector())
180 MIRBuilder.buildConcatVectors(Res: DstReg, Ops: PartRegs);
181 else
182 MIRBuilder.buildBuildVector(Res: DstReg, Ops: PartRegs);
183 return;
184 }
185
186 // Merge sub-vectors with different number of elements and insert into DstReg.
187 if (ResultTy.isVector()) {
188 assert(LeftoverRegs.size() == 1 && "Expected one leftover register");
189 SmallVector<Register, 8> AllRegs(PartRegs);
190 AllRegs.append(in_start: LeftoverRegs.begin(), in_end: LeftoverRegs.end());
191 return mergeMixedSubvectors(DstReg, PartRegs: AllRegs);
192 }
193
194 SmallVector<Register> GCDRegs;
195 LLT GCDTy = getGCDType(OrigTy: getGCDType(OrigTy: ResultTy, TargetTy: LeftoverTy), TargetTy: PartTy);
196 for (auto PartReg : concat<const Register>(Ranges&: PartRegs, Ranges&: LeftoverRegs))
197 extractGCDType(Parts&: GCDRegs, GCDTy, SrcReg: PartReg);
198 LLT ResultLCMTy = buildLCMMergePieces(DstTy: ResultTy, NarrowTy: LeftoverTy, GCDTy, VRegs&: GCDRegs);
199 buildWidenedRemergeToDst(DstReg, LCMTy: ResultLCMTy, RemergeRegs: GCDRegs);
200}
201
202void LegalizerHelper::appendVectorElts(SmallVectorImpl<Register> &Elts,
203 Register Reg) {
204 LLT Ty = MRI.getType(Reg);
205 SmallVector<Register, 8> RegElts;
206 extractParts(Reg, Ty: Ty.getScalarType(), NumParts: Ty.getNumElements(), VRegs&: RegElts,
207 MIRBuilder, MRI);
208 Elts.append(RHS: RegElts);
209}
210
211/// Merge \p PartRegs with different types into \p DstReg.
212void LegalizerHelper::mergeMixedSubvectors(Register DstReg,
213 ArrayRef<Register> PartRegs) {
214 SmallVector<Register, 8> AllElts;
215 for (unsigned i = 0; i < PartRegs.size() - 1; ++i)
216 appendVectorElts(Elts&: AllElts, Reg: PartRegs[i]);
217
218 Register Leftover = PartRegs[PartRegs.size() - 1];
219 if (!MRI.getType(Reg: Leftover).isVector())
220 AllElts.push_back(Elt: Leftover);
221 else
222 appendVectorElts(Elts&: AllElts, Reg: Leftover);
223
224 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: AllElts);
225}
226
227/// Append the result registers of G_UNMERGE_VALUES \p MI to \p Regs.
228static void getUnmergeResults(SmallVectorImpl<Register> &Regs,
229 const MachineInstr &MI) {
230 assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES);
231
232 const int StartIdx = Regs.size();
233 const int NumResults = MI.getNumOperands() - 1;
234 Regs.resize(N: Regs.size() + NumResults);
235 for (int I = 0; I != NumResults; ++I)
236 Regs[StartIdx + I] = MI.getOperand(i: I).getReg();
237}
238
239void LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts,
240 LLT GCDTy, Register SrcReg) {
241 LLT SrcTy = MRI.getType(Reg: SrcReg);
242 if (SrcTy == GCDTy) {
243 // If the source already evenly divides the result type, we don't need to do
244 // anything.
245 Parts.push_back(Elt: SrcReg);
246 } else {
247 // Need to split into common type sized pieces.
248 auto Unmerge = MIRBuilder.buildUnmerge(Res: GCDTy, Op: SrcReg);
249 getUnmergeResults(Regs&: Parts, MI: *Unmerge);
250 }
251}
252
253LLT LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, LLT DstTy,
254 LLT NarrowTy, Register SrcReg) {
255 LLT SrcTy = MRI.getType(Reg: SrcReg);
256 LLT GCDTy = getGCDType(OrigTy: getGCDType(OrigTy: SrcTy, TargetTy: NarrowTy), TargetTy: DstTy);
257 extractGCDType(Parts, GCDTy, SrcReg);
258 return GCDTy;
259}
260
261LLT LegalizerHelper::buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy,
262 SmallVectorImpl<Register> &VRegs,
263 unsigned PadStrategy) {
264 LLT LCMTy = getLCMType(OrigTy: DstTy, TargetTy: NarrowTy);
265
266 int NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits();
267 int NumSubParts = NarrowTy.getSizeInBits() / GCDTy.getSizeInBits();
268 int NumOrigSrc = VRegs.size();
269
270 Register PadReg;
271
272 // Get a value we can use to pad the source value if the sources won't evenly
273 // cover the result type.
274 if (NumOrigSrc < NumParts * NumSubParts) {
275 if (PadStrategy == TargetOpcode::G_ZEXT)
276 PadReg = MIRBuilder.buildConstant(Res: GCDTy, Val: 0).getReg(Idx: 0);
277 else if (PadStrategy == TargetOpcode::G_ANYEXT)
278 PadReg = MIRBuilder.buildUndef(Res: GCDTy).getReg(Idx: 0);
279 else {
280 assert(PadStrategy == TargetOpcode::G_SEXT);
281
282 // Shift the sign bit of the low register through the high register.
283 auto ShiftAmt =
284 MIRBuilder.buildConstant(Res: LLT::integer(SizeInBits: 64), Val: GCDTy.getSizeInBits() - 1);
285 PadReg = MIRBuilder.buildAShr(Dst: GCDTy, Src0: VRegs.back(), Src1: ShiftAmt).getReg(Idx: 0);
286 }
287 }
288
289 // Registers for the final merge to be produced.
290 SmallVector<Register, 4> Remerge(NumParts);
291
292 // Registers needed for intermediate merges, which will be merged into a
293 // source for Remerge.
294 SmallVector<Register, 4> SubMerge(NumSubParts);
295
296 // Once we've fully read off the end of the original source bits, we can reuse
297 // the same high bits for remaining padding elements.
298 Register AllPadReg;
299
300 // Build merges to the LCM type to cover the original result type.
301 for (int I = 0; I != NumParts; ++I) {
302 bool AllMergePartsArePadding = true;
303
304 // Build the requested merges to the requested type.
305 for (int J = 0; J != NumSubParts; ++J) {
306 int Idx = I * NumSubParts + J;
307 if (Idx >= NumOrigSrc) {
308 SubMerge[J] = PadReg;
309 continue;
310 }
311
312 SubMerge[J] = VRegs[Idx];
313
314 // There are meaningful bits here we can't reuse later.
315 AllMergePartsArePadding = false;
316 }
317
318 // If we've filled up a complete piece with padding bits, we can directly
319 // emit the natural sized constant if applicable, rather than a merge of
320 // smaller constants.
321 if (AllMergePartsArePadding && !AllPadReg) {
322 if (PadStrategy == TargetOpcode::G_ANYEXT)
323 AllPadReg = MIRBuilder.buildUndef(Res: NarrowTy).getReg(Idx: 0);
324 else if (PadStrategy == TargetOpcode::G_ZEXT)
325 AllPadReg = MIRBuilder.buildConstant(Res: NarrowTy, Val: 0).getReg(Idx: 0);
326
327 // If this is a sign extension, we can't materialize a trivial constant
328 // with the right type and have to produce a merge.
329 }
330
331 if (AllPadReg) {
332 // Avoid creating additional instructions if we're just adding additional
333 // copies of padding bits.
334 Remerge[I] = AllPadReg;
335 continue;
336 }
337
338 if (NumSubParts == 1)
339 Remerge[I] = SubMerge[0];
340 else
341 Remerge[I] = MIRBuilder.buildMergeLikeInstr(Res: NarrowTy, Ops: SubMerge).getReg(Idx: 0);
342
343 // In the sign extend padding case, re-use the first all-signbit merge.
344 if (AllMergePartsArePadding && !AllPadReg)
345 AllPadReg = Remerge[I];
346 }
347
348 VRegs = std::move(Remerge);
349 return LCMTy;
350}
351
352void LegalizerHelper::buildWidenedRemergeToDst(Register DstReg, LLT LCMTy,
353 ArrayRef<Register> RemergeRegs) {
354 LLT DstTy = MRI.getType(Reg: DstReg);
355
356 // Create the merge to the widened source, and extract the relevant bits into
357 // the result.
358
359 if (DstTy == LCMTy) {
360 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: RemergeRegs);
361 return;
362 }
363
364 auto Remerge = MIRBuilder.buildMergeLikeInstr(Res: LCMTy, Ops: RemergeRegs);
365 if (DstTy.isScalar() && LCMTy.isScalar()) {
366 MIRBuilder.buildTrunc(Res: DstReg, Op: Remerge);
367 return;
368 }
369
370 if (LCMTy.isVector()) {
371 unsigned NumDefs = LCMTy.getSizeInBits() / DstTy.getSizeInBits();
372 SmallVector<Register, 8> UnmergeDefs(NumDefs);
373 UnmergeDefs[0] = DstReg;
374 for (unsigned I = 1; I != NumDefs; ++I)
375 UnmergeDefs[I] = MRI.createGenericVirtualRegister(Ty: DstTy);
376
377 MIRBuilder.buildUnmerge(Res: UnmergeDefs,
378 Op: MIRBuilder.buildMergeLikeInstr(Res: LCMTy, Ops: RemergeRegs));
379 return;
380 }
381
382 llvm_unreachable("unhandled case");
383}
384
385static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
386#define RTLIBCASE_INT(LibcallPrefix) \
387 do { \
388 switch (Size) { \
389 case 32: \
390 return RTLIB::LibcallPrefix##32; \
391 case 64: \
392 return RTLIB::LibcallPrefix##64; \
393 case 128: \
394 return RTLIB::LibcallPrefix##128; \
395 default: \
396 llvm_unreachable("unexpected size"); \
397 } \
398 } while (0)
399
400#define RTLIBCASE(LibcallPrefix) \
401 do { \
402 switch (Size) { \
403 case 32: \
404 return RTLIB::LibcallPrefix##32; \
405 case 64: \
406 return RTLIB::LibcallPrefix##64; \
407 case 80: \
408 return RTLIB::LibcallPrefix##80; \
409 case 128: \
410 return RTLIB::LibcallPrefix##128; \
411 default: \
412 llvm_unreachable("unexpected size"); \
413 } \
414 } while (0)
415
416 switch (Opcode) {
417 case TargetOpcode::G_LROUND:
418 RTLIBCASE(LROUND_F);
419 case TargetOpcode::G_LLROUND:
420 RTLIBCASE(LLROUND_F);
421 case TargetOpcode::G_MUL:
422 RTLIBCASE_INT(MUL_I);
423 case TargetOpcode::G_SDIV:
424 RTLIBCASE_INT(SDIV_I);
425 case TargetOpcode::G_UDIV:
426 RTLIBCASE_INT(UDIV_I);
427 case TargetOpcode::G_SREM:
428 RTLIBCASE_INT(SREM_I);
429 case TargetOpcode::G_UREM:
430 RTLIBCASE_INT(UREM_I);
431 case TargetOpcode::G_CTLZ_ZERO_POISON:
432 RTLIBCASE_INT(CTLZ_I);
433 case TargetOpcode::G_FADD:
434 RTLIBCASE(ADD_F);
435 case TargetOpcode::G_FSUB:
436 RTLIBCASE(SUB_F);
437 case TargetOpcode::G_FMUL:
438 RTLIBCASE(MUL_F);
439 case TargetOpcode::G_FDIV:
440 RTLIBCASE(DIV_F);
441 case TargetOpcode::G_FEXP:
442 RTLIBCASE(EXP_F);
443 case TargetOpcode::G_FEXP2:
444 RTLIBCASE(EXP2_F);
445 case TargetOpcode::G_FEXP10:
446 RTLIBCASE(EXP10_F);
447 case TargetOpcode::G_FREM:
448 RTLIBCASE(REM_F);
449 case TargetOpcode::G_FPOW:
450 RTLIBCASE(POW_F);
451 case TargetOpcode::G_FPOWI:
452 RTLIBCASE(POWI_F);
453 case TargetOpcode::G_FMA:
454 RTLIBCASE(FMA_F);
455 case TargetOpcode::G_FSIN:
456 RTLIBCASE(SIN_F);
457 case TargetOpcode::G_FCOS:
458 RTLIBCASE(COS_F);
459 case TargetOpcode::G_FTAN:
460 RTLIBCASE(TAN_F);
461 case TargetOpcode::G_FASIN:
462 RTLIBCASE(ASIN_F);
463 case TargetOpcode::G_FACOS:
464 RTLIBCASE(ACOS_F);
465 case TargetOpcode::G_FATAN:
466 RTLIBCASE(ATAN_F);
467 case TargetOpcode::G_FATAN2:
468 RTLIBCASE(ATAN2_F);
469 case TargetOpcode::G_FSINH:
470 RTLIBCASE(SINH_F);
471 case TargetOpcode::G_FCOSH:
472 RTLIBCASE(COSH_F);
473 case TargetOpcode::G_FTANH:
474 RTLIBCASE(TANH_F);
475 case TargetOpcode::G_FSINCOS:
476 RTLIBCASE(SINCOS_F);
477 case TargetOpcode::G_FMODF:
478 RTLIBCASE(MODF_F);
479 case TargetOpcode::G_FLOG10:
480 RTLIBCASE(LOG10_F);
481 case TargetOpcode::G_FLOG:
482 RTLIBCASE(LOG_F);
483 case TargetOpcode::G_FLOG2:
484 RTLIBCASE(LOG2_F);
485 case TargetOpcode::G_FLDEXP:
486 RTLIBCASE(LDEXP_F);
487 case TargetOpcode::G_FCEIL:
488 RTLIBCASE(CEIL_F);
489 case TargetOpcode::G_FFLOOR:
490 RTLIBCASE(FLOOR_F);
491 case TargetOpcode::G_FMINNUM:
492 RTLIBCASE(FMIN_F);
493 case TargetOpcode::G_FMAXNUM:
494 RTLIBCASE(FMAX_F);
495 case TargetOpcode::G_FMINIMUMNUM:
496 RTLIBCASE(FMINIMUM_NUM_F);
497 case TargetOpcode::G_FMAXIMUMNUM:
498 RTLIBCASE(FMAXIMUM_NUM_F);
499 case TargetOpcode::G_FSQRT:
500 RTLIBCASE(SQRT_F);
501 case TargetOpcode::G_FRINT:
502 RTLIBCASE(RINT_F);
503 case TargetOpcode::G_FNEARBYINT:
504 RTLIBCASE(NEARBYINT_F);
505 case TargetOpcode::G_INTRINSIC_TRUNC:
506 RTLIBCASE(TRUNC_F);
507 case TargetOpcode::G_INTRINSIC_ROUND:
508 RTLIBCASE(ROUND_F);
509 case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
510 RTLIBCASE(ROUNDEVEN_F);
511 case TargetOpcode::G_INTRINSIC_LRINT:
512 RTLIBCASE(LRINT_F);
513 case TargetOpcode::G_INTRINSIC_LLRINT:
514 RTLIBCASE(LLRINT_F);
515 }
516 llvm_unreachable("Unknown libcall function");
517#undef RTLIBCASE_INT
518#undef RTLIBCASE
519}
520
521static bool hasSwiftErrorArg(MachineFunction &MF) {
522 const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
523 return TLI.supportSwiftError() &&
524 MF.getFunction().getAttributes().hasAttrSomewhere(
525 Kind: Attribute::SwiftError);
526}
527
528/// True if an instruction is in tail position in its caller. Intended for
529/// legalizing libcalls as tail calls when possible.
530static bool isLibCallInTailPosition(const CallLowering::ArgInfo &Result,
531 MachineInstr &MI,
532 const TargetInstrInfo &TII,
533 MachineRegisterInfo &MRI) {
534 MachineBasicBlock &MBB = *MI.getParent();
535 const Function &F = MBB.getParent()->getFunction();
536
537 // Conservatively require the attributes of the call to match those of
538 // the return. Ignore NoAlias and NonNull because they don't affect the
539 // call sequence.
540 AttributeList CallerAttrs = F.getAttributes();
541 if (AttrBuilder(F.getContext(), CallerAttrs.getRetAttrs())
542 .removeAttribute(Val: Attribute::NoAlias)
543 .removeAttribute(Val: Attribute::NonNull)
544 .hasAttributes())
545 return false;
546
547 // It's not safe to eliminate the sign / zero extension of the return value.
548 if (CallerAttrs.hasRetAttr(Kind: Attribute::ZExt) ||
549 CallerAttrs.hasRetAttr(Kind: Attribute::SExt))
550 return false;
551
552 // Only tail call if the following instruction is a standard return or if we
553 // have a `thisreturn` callee, and a sequence like:
554 //
555 // G_MEMCPY %0, %1, %2
556 // $x0 = COPY %0
557 // RET_ReallyLR implicit $x0
558 auto Next = next_nodbg(It: MI.getIterator(), End: MBB.instr_end());
559 if (Next != MBB.instr_end() && Next->isCopy()) {
560 if (MI.getOpcode() == TargetOpcode::G_BZERO)
561 return false;
562
563 // For MEMCPY/MOMMOVE/MEMSET these will be the first use (the dst), as the
564 // mempy/etc routines return the same parameter. For other it will be the
565 // returned value.
566 Register VReg = MI.getOperand(i: 0).getReg();
567 if (!VReg.isVirtual() || VReg != Next->getOperand(i: 1).getReg())
568 return false;
569
570 Register PReg = Next->getOperand(i: 0).getReg();
571 if (!PReg.isPhysical())
572 return false;
573
574 auto Ret = next_nodbg(It: Next, End: MBB.instr_end());
575 if (Ret == MBB.instr_end() || !Ret->isReturn())
576 return false;
577
578 if (Ret->getNumImplicitOperands() != 1)
579 return false;
580
581 if (!Ret->getOperand(i: 0).isReg() || PReg != Ret->getOperand(i: 0).getReg())
582 return false;
583
584 // Skip over the COPY that we just validated.
585 Next = Ret;
586 }
587
588 if (Next == MBB.instr_end() || TII.isTailCall(Inst: *Next) || !Next->isReturn())
589 return false;
590
591 return true;
592}
593
594LegalizerHelper::LegalizeResult LegalizerHelper::createLibcall(
595 const char *Name, const CallLowering::ArgInfo &Result,
596 ArrayRef<CallLowering::ArgInfo> Args, const CallingConv::ID CC,
597 LostDebugLocObserver &LocObserver, MachineInstr *MI) const {
598 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
599
600 CallLowering::CallLoweringInfo Info;
601 Info.CallConv = CC;
602 Info.Callee = MachineOperand::CreateES(SymName: Name);
603 Info.OrigRet = Result;
604 if (MI)
605 Info.IsTailCall =
606 (Result.Ty->isVoidTy() ||
607 Result.Ty == MIRBuilder.getMF().getFunction().getReturnType()) &&
608 isLibCallInTailPosition(Result, MI&: *MI, TII: MIRBuilder.getTII(),
609 MRI&: *MIRBuilder.getMRI()) &&
610 // Lowering doesn't support tail calling inside a function with
611 // a swifterror argument yet.
612 !hasSwiftErrorArg(MF&: MIRBuilder.getMF());
613
614 llvm::append_range(C&: Info.OrigArgs, R&: Args);
615 if (!CLI.lowerCall(MIRBuilder, Info))
616 return LegalizerHelper::UnableToLegalize;
617
618 if (MI && Info.LoweredTailCall) {
619 assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?");
620
621 // Check debug locations before removing the return.
622 LocObserver.checkpoint(CheckDebugLocs: true);
623
624 // We must have a return following the call (or debug insts) to get past
625 // isLibCallInTailPosition.
626 do {
627 MachineInstr *Next = MI->getNextNode();
628 assert(Next &&
629 (Next->isCopy() || Next->isReturn() || Next->isDebugInstr()) &&
630 "Expected instr following MI to be return or debug inst?");
631 // We lowered a tail call, so the call is now the return from the block.
632 // Delete the old return.
633 Next->eraseFromParent();
634 } while (MI->getNextNode());
635
636 // We expect to lose the debug location from the return.
637 LocObserver.checkpoint(CheckDebugLocs: false);
638 }
639 return LegalizerHelper::Legalized;
640}
641
642LegalizerHelper::LegalizeResult LegalizerHelper::createLibcall(
643 RTLIB::Libcall Libcall, const CallLowering::ArgInfo &Result,
644 ArrayRef<CallLowering::ArgInfo> Args, LostDebugLocObserver &LocObserver,
645 MachineInstr *MI) const {
646 if (!Libcalls)
647 return LegalizerHelper::UnableToLegalize;
648
649 RTLIB::LibcallImpl LibcallImpl = Libcalls->getLibcallImpl(Call: Libcall);
650 if (LibcallImpl == RTLIB::Unsupported)
651 return LegalizerHelper::UnableToLegalize;
652
653 StringRef Name = RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: LibcallImpl);
654 const CallingConv::ID CC = Libcalls->getLibcallImplCallingConv(Call: LibcallImpl);
655 return createLibcall(Name: Name.data(), Result, Args, CC, LocObserver, MI);
656}
657
658// Useful for libcalls where all operands have the same type.
659LegalizerHelper::LegalizeResult
660LegalizerHelper::simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
661 unsigned Size, Type *OpType,
662 LostDebugLocObserver &LocObserver) const {
663 auto Libcall = getRTLibDesc(Opcode: MI.getOpcode(), Size);
664
665 // FIXME: What does the original arg index mean here?
666 SmallVector<CallLowering::ArgInfo, 3> Args;
667 for (const MachineOperand &MO : llvm::drop_begin(RangeOrContainer: MI.operands()))
668 Args.push_back(Elt: {MO.getReg(), OpType, 0});
669 return createLibcall(Libcall, Result: {MI.getOperand(i: 0).getReg(), OpType, 0}, Args,
670 LocObserver, MI: &MI);
671}
672
673LegalizerHelper::LegalizeResult LegalizerHelper::emitSincosLibcall(
674 MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size, Type *OpType,
675 LostDebugLocObserver &LocObserver) {
676 MachineFunction &MF = *MI.getMF();
677 MachineRegisterInfo &MRI = MF.getRegInfo();
678
679 Register DstSin = MI.getOperand(i: 0).getReg();
680 Register DstCos = MI.getOperand(i: 1).getReg();
681 Register Src = MI.getOperand(i: 2).getReg();
682 LLT DstTy = MRI.getType(Reg: DstSin);
683
684 int MemSize = DstTy.getSizeInBytes();
685 Align Alignment = getStackTemporaryAlignment(Type: DstTy);
686 const DataLayout &DL = MIRBuilder.getDataLayout();
687 unsigned AddrSpace = DL.getAllocaAddrSpace();
688 MachinePointerInfo PtrInfo;
689
690 Register StackPtrSin =
691 createStackTemporary(Bytes: TypeSize::getFixed(ExactSize: MemSize), Alignment, PtrInfo)
692 .getReg(Idx: 0);
693 Register StackPtrCos =
694 createStackTemporary(Bytes: TypeSize::getFixed(ExactSize: MemSize), Alignment, PtrInfo)
695 .getReg(Idx: 0);
696
697 auto &Ctx = MF.getFunction().getContext();
698 auto LibcallResult = createLibcall(
699 Libcall: getRTLibDesc(Opcode: MI.getOpcode(), Size), Result: {{0}, Type::getVoidTy(C&: Ctx), 0},
700 Args: {{Src, OpType, 0},
701 {StackPtrSin, PointerType::get(C&: Ctx, AddressSpace: AddrSpace), 1},
702 {StackPtrCos, PointerType::get(C&: Ctx, AddressSpace: AddrSpace), 2}},
703 LocObserver, MI: &MI);
704
705 if (LibcallResult != LegalizeResult::Legalized)
706 return LegalizerHelper::UnableToLegalize;
707
708 MachineMemOperand *LoadMMOSin = MF.getMachineMemOperand(
709 PtrInfo, F: MachineMemOperand::MOLoad, Size: MemSize, BaseAlignment: Alignment);
710 MachineMemOperand *LoadMMOCos = MF.getMachineMemOperand(
711 PtrInfo, F: MachineMemOperand::MOLoad, Size: MemSize, BaseAlignment: Alignment);
712
713 MIRBuilder.buildLoad(Res: DstSin, Addr: StackPtrSin, MMO&: *LoadMMOSin);
714 MIRBuilder.buildLoad(Res: DstCos, Addr: StackPtrCos, MMO&: *LoadMMOCos);
715 MI.eraseFromParent();
716
717 return LegalizerHelper::Legalized;
718}
719
720LegalizerHelper::LegalizeResult
721LegalizerHelper::emitModfLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
722 unsigned Size, Type *OpType,
723 LostDebugLocObserver &LocObserver) {
724 MachineFunction &MF = MIRBuilder.getMF();
725 MachineRegisterInfo &MRI = MF.getRegInfo();
726
727 Register DstFrac = MI.getOperand(i: 0).getReg();
728 Register DstInt = MI.getOperand(i: 1).getReg();
729 Register Src = MI.getOperand(i: 2).getReg();
730 LLT DstTy = MRI.getType(Reg: DstFrac);
731
732 int MemSize = DstTy.getSizeInBytes();
733 Align Alignment = getStackTemporaryAlignment(Type: DstTy);
734 const DataLayout &DL = MIRBuilder.getDataLayout();
735 unsigned AddrSpace = DL.getAllocaAddrSpace();
736 MachinePointerInfo PtrInfo;
737
738 Register StackPtrInt =
739 createStackTemporary(Bytes: TypeSize::getFixed(ExactSize: MemSize), Alignment, PtrInfo)
740 .getReg(Idx: 0);
741
742 auto &Ctx = MF.getFunction().getContext();
743 auto LibcallResult = createLibcall(
744 Libcall: getRTLibDesc(Opcode: MI.getOpcode(), Size), Result: {DstFrac, OpType, 0},
745 Args: {{Src, OpType, 0}, {StackPtrInt, PointerType::get(C&: Ctx, AddressSpace: AddrSpace), 1}},
746 LocObserver, MI: &MI);
747
748 if (LibcallResult != LegalizeResult::Legalized)
749 return LegalizerHelper::UnableToLegalize;
750
751 MachineMemOperand *LoadMMOInt = MF.getMachineMemOperand(
752 PtrInfo, F: MachineMemOperand::MOLoad, Size: MemSize, BaseAlignment: Alignment);
753
754 MIRBuilder.buildLoad(Res: DstInt, Addr: StackPtrInt, MMO&: *LoadMMOInt);
755 MI.eraseFromParent();
756
757 return LegalizerHelper::Legalized;
758}
759
760static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
761 Type *FromType) {
762 auto ToMVT = MVT::getVT(Ty: ToType);
763 auto FromMVT = MVT::getVT(Ty: FromType);
764
765 switch (Opcode) {
766 case TargetOpcode::G_FPEXT:
767 return RTLIB::getFPEXT(OpVT: FromMVT, RetVT: ToMVT);
768 case TargetOpcode::G_FPTRUNC:
769 return RTLIB::getFPROUND(OpVT: FromMVT, RetVT: ToMVT);
770 case TargetOpcode::G_FPTOSI:
771 return RTLIB::getFPTOSINT(OpVT: FromMVT, RetVT: ToMVT);
772 case TargetOpcode::G_FPTOUI:
773 return RTLIB::getFPTOUINT(OpVT: FromMVT, RetVT: ToMVT);
774 case TargetOpcode::G_SITOFP:
775 return RTLIB::getSINTTOFP(OpVT: FromMVT, RetVT: ToMVT);
776 case TargetOpcode::G_UITOFP:
777 return RTLIB::getUINTTOFP(OpVT: FromMVT, RetVT: ToMVT);
778 }
779 llvm_unreachable("Unsupported libcall function");
780}
781
782LegalizerHelper::LegalizeResult LegalizerHelper::conversionLibcall(
783 MachineInstr &MI, Type *ToType, Type *FromType,
784 LostDebugLocObserver &LocObserver, bool IsSigned) const {
785 CallLowering::ArgInfo Arg = {MI.getOperand(i: 1).getReg(), FromType, 0};
786 if (FromType->isIntegerTy()) {
787 if (TLI.shouldSignExtendTypeInLibCall(Ty: FromType, IsSigned))
788 Arg.Flags[0].setSExt();
789 else
790 Arg.Flags[0].setZExt();
791 }
792
793 RTLIB::Libcall Libcall = getConvRTLibDesc(Opcode: MI.getOpcode(), ToType, FromType);
794 return createLibcall(Libcall, Result: {MI.getOperand(i: 0).getReg(), ToType, 0}, Args: Arg,
795 LocObserver, MI: &MI);
796}
797
798LegalizerHelper::LegalizeResult
799LegalizerHelper::createMemLibcall(MachineRegisterInfo &MRI, MachineInstr &MI,
800 LostDebugLocObserver &LocObserver) const {
801 auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
802
803 SmallVector<CallLowering::ArgInfo, 3> Args;
804 // Add all the args, except for the last which is an imm denoting 'tail'.
805 for (unsigned i = 0; i < MI.getNumOperands() - 1; ++i) {
806 Register Reg = MI.getOperand(i).getReg();
807
808 // Need derive an IR type for call lowering.
809 LLT OpLLT = MRI.getType(Reg);
810 Type *OpTy = nullptr;
811 if (OpLLT.isPointer())
812 OpTy = PointerType::get(C&: Ctx, AddressSpace: OpLLT.getAddressSpace());
813 else
814 OpTy = IntegerType::get(C&: Ctx, NumBits: OpLLT.getSizeInBits());
815 Args.push_back(Elt: {Reg, OpTy, 0});
816 }
817
818 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
819 RTLIB::Libcall RTLibcall;
820 unsigned Opc = MI.getOpcode();
821 switch (Opc) {
822 case TargetOpcode::G_BZERO:
823 RTLibcall = RTLIB::BZERO;
824 break;
825 case TargetOpcode::G_MEMCPY:
826 RTLibcall = RTLIB::MEMCPY;
827 Args[0].Flags[0].setReturned();
828 break;
829 case TargetOpcode::G_MEMMOVE:
830 RTLibcall = RTLIB::MEMMOVE;
831 Args[0].Flags[0].setReturned();
832 break;
833 case TargetOpcode::G_MEMSET:
834 RTLibcall = RTLIB::MEMSET;
835 Args[0].Flags[0].setReturned();
836 break;
837 default:
838 llvm_unreachable("unsupported opcode");
839 }
840
841 if (!Libcalls) // FIXME: Should be mandatory
842 return LegalizerHelper::UnableToLegalize;
843
844 RTLIB::LibcallImpl RTLibcallImpl = Libcalls->getLibcallImpl(Call: RTLibcall);
845
846 // Unsupported libcall on the target.
847 if (RTLibcallImpl == RTLIB::Unsupported) {
848 LLVM_DEBUG(dbgs() << ".. .. Could not find libcall name for "
849 << MIRBuilder.getTII().getName(Opc) << "\n");
850 return LegalizerHelper::UnableToLegalize;
851 }
852
853 CallLowering::CallLoweringInfo Info;
854 Info.CallConv = Libcalls->getLibcallImplCallingConv(Call: RTLibcallImpl);
855
856 StringRef LibcallName =
857 RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: RTLibcallImpl);
858 Info.Callee = MachineOperand::CreateES(SymName: LibcallName.data());
859 Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(C&: Ctx), 0);
860 Info.IsTailCall =
861 MI.getOperand(i: MI.getNumOperands() - 1).getImm() &&
862 isLibCallInTailPosition(Result: Info.OrigRet, MI, TII: MIRBuilder.getTII(), MRI) &&
863 // Lowering doesn't support tail calling inside a function with
864 // a swifterror argument yet.
865 !hasSwiftErrorArg(MF&: MIRBuilder.getMF());
866
867 llvm::append_range(C&: Info.OrigArgs, R&: Args);
868 if (!CLI.lowerCall(MIRBuilder, Info))
869 return LegalizerHelper::UnableToLegalize;
870
871 if (Info.LoweredTailCall) {
872 assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?");
873
874 // Check debug locations before removing the return.
875 LocObserver.checkpoint(CheckDebugLocs: true);
876
877 // We must have a return following the call (or debug insts) to get past
878 // isLibCallInTailPosition.
879 do {
880 MachineInstr *Next = MI.getNextNode();
881 assert(Next &&
882 (Next->isCopy() || Next->isReturn() || Next->isDebugInstr()) &&
883 "Expected instr following MI to be return or debug inst?");
884 // We lowered a tail call, so the call is now the return from the block.
885 // Delete the old return.
886 Next->eraseFromParent();
887 } while (MI.getNextNode());
888
889 // We expect to lose the debug location from the return.
890 LocObserver.checkpoint(CheckDebugLocs: false);
891 }
892
893 return LegalizerHelper::Legalized;
894}
895
896static RTLIB::Libcall getOutlineAtomicLibcall(MachineInstr &MI) {
897 unsigned Opc = MI.getOpcode();
898 auto &AtomicMI = cast<GMemOperation>(Val&: MI);
899 auto &MMO = AtomicMI.getMMO();
900 auto Ordering = MMO.getMergedOrdering();
901 LLT MemType = MMO.getMemoryType();
902 uint64_t MemSize = MemType.getSizeInBytes();
903 if (MemType.isVector())
904 return RTLIB::UNKNOWN_LIBCALL;
905
906#define LCALLS(A, B) {A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL}
907#define LCALL5(A) \
908 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
909 switch (Opc) {
910 case TargetOpcode::G_ATOMIC_CMPXCHG:
911 case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
912 const RTLIB::Libcall LC[5][4] = {LCALL5(RTLIB::OUTLINE_ATOMIC_CAS)};
913 return getOutlineAtomicHelper(LC, Order: Ordering, MemSize);
914 }
915 case TargetOpcode::G_ATOMICRMW_XCHG: {
916 const RTLIB::Libcall LC[5][4] = {LCALL5(RTLIB::OUTLINE_ATOMIC_SWP)};
917 return getOutlineAtomicHelper(LC, Order: Ordering, MemSize);
918 }
919 case TargetOpcode::G_ATOMICRMW_ADD:
920 case TargetOpcode::G_ATOMICRMW_SUB: {
921 const RTLIB::Libcall LC[5][4] = {LCALL5(RTLIB::OUTLINE_ATOMIC_LDADD)};
922 return getOutlineAtomicHelper(LC, Order: Ordering, MemSize);
923 }
924 case TargetOpcode::G_ATOMICRMW_AND: {
925 const RTLIB::Libcall LC[5][4] = {LCALL5(RTLIB::OUTLINE_ATOMIC_LDCLR)};
926 return getOutlineAtomicHelper(LC, Order: Ordering, MemSize);
927 }
928 case TargetOpcode::G_ATOMICRMW_OR: {
929 const RTLIB::Libcall LC[5][4] = {LCALL5(RTLIB::OUTLINE_ATOMIC_LDSET)};
930 return getOutlineAtomicHelper(LC, Order: Ordering, MemSize);
931 }
932 case TargetOpcode::G_ATOMICRMW_XOR: {
933 const RTLIB::Libcall LC[5][4] = {LCALL5(RTLIB::OUTLINE_ATOMIC_LDEOR)};
934 return getOutlineAtomicHelper(LC, Order: Ordering, MemSize);
935 }
936 default:
937 return RTLIB::UNKNOWN_LIBCALL;
938 }
939#undef LCALLS
940#undef LCALL5
941}
942
943LegalizerHelper::LegalizeResult
944LegalizerHelper::createAtomicLibcall(MachineInstr &MI) const {
945 auto &Ctx = MIRBuilder.getContext();
946
947 Type *RetTy;
948 SmallVector<Register> RetRegs;
949 SmallVector<CallLowering::ArgInfo, 3> Args;
950 unsigned Opc = MI.getOpcode();
951 switch (Opc) {
952 case TargetOpcode::G_ATOMIC_CMPXCHG:
953 case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
954 Register Success;
955 LLT SuccessLLT;
956 auto [Ret, RetLLT, Mem, MemLLT, Cmp, CmpLLT, New, NewLLT] =
957 MI.getFirst4RegLLTs();
958 RetRegs.push_back(Elt: Ret);
959 RetTy = IntegerType::get(C&: Ctx, NumBits: RetLLT.getSizeInBits());
960 if (Opc == TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS) {
961 std::tie(args&: Ret, args&: RetLLT, args&: Success, args&: SuccessLLT, args&: Mem, args&: MemLLT, args&: Cmp, args&: CmpLLT, args&: New,
962 args&: NewLLT) = MI.getFirst5RegLLTs();
963 RetRegs.push_back(Elt: Success);
964 RetTy = StructType::get(
965 Context&: Ctx, Elements: {RetTy, IntegerType::get(C&: Ctx, NumBits: SuccessLLT.getSizeInBits())});
966 }
967 Args.push_back(Elt: {Cmp, IntegerType::get(C&: Ctx, NumBits: CmpLLT.getSizeInBits()), 0});
968 Args.push_back(Elt: {New, IntegerType::get(C&: Ctx, NumBits: NewLLT.getSizeInBits()), 0});
969 Args.push_back(Elt: {Mem, PointerType::get(C&: Ctx, AddressSpace: MemLLT.getAddressSpace()), 0});
970 break;
971 }
972 case TargetOpcode::G_ATOMICRMW_XCHG:
973 case TargetOpcode::G_ATOMICRMW_ADD:
974 case TargetOpcode::G_ATOMICRMW_SUB:
975 case TargetOpcode::G_ATOMICRMW_AND:
976 case TargetOpcode::G_ATOMICRMW_OR:
977 case TargetOpcode::G_ATOMICRMW_XOR: {
978 auto [Ret, RetLLT, Mem, MemLLT, Val, ValLLT] = MI.getFirst3RegLLTs();
979 RetRegs.push_back(Elt: Ret);
980 RetTy = IntegerType::get(C&: Ctx, NumBits: RetLLT.getSizeInBits());
981 if (Opc == TargetOpcode::G_ATOMICRMW_AND)
982 Val =
983 MIRBuilder.buildXor(Dst: ValLLT, Src0: MIRBuilder.buildConstant(Res: ValLLT, Val: -1), Src1: Val)
984 .getReg(Idx: 0);
985 else if (Opc == TargetOpcode::G_ATOMICRMW_SUB)
986 Val =
987 MIRBuilder.buildSub(Dst: ValLLT, Src0: MIRBuilder.buildConstant(Res: ValLLT, Val: 0), Src1: Val)
988 .getReg(Idx: 0);
989 Args.push_back(Elt: {Val, IntegerType::get(C&: Ctx, NumBits: ValLLT.getSizeInBits()), 0});
990 Args.push_back(Elt: {Mem, PointerType::get(C&: Ctx, AddressSpace: MemLLT.getAddressSpace()), 0});
991 break;
992 }
993 default:
994 llvm_unreachable("unsupported opcode");
995 }
996
997 if (!Libcalls) // FIXME: Should be mandatory
998 return LegalizerHelper::UnableToLegalize;
999
1000 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
1001 RTLIB::Libcall RTLibcall = getOutlineAtomicLibcall(MI);
1002 RTLIB::LibcallImpl RTLibcallImpl = Libcalls->getLibcallImpl(Call: RTLibcall);
1003
1004 // Unsupported libcall on the target.
1005 if (RTLibcallImpl == RTLIB::Unsupported) {
1006 LLVM_DEBUG(dbgs() << ".. .. Could not find libcall name for "
1007 << MIRBuilder.getTII().getName(Opc) << "\n");
1008 return LegalizerHelper::UnableToLegalize;
1009 }
1010
1011 CallLowering::CallLoweringInfo Info;
1012 Info.CallConv = Libcalls->getLibcallImplCallingConv(Call: RTLibcallImpl);
1013
1014 StringRef LibcallName =
1015 RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: RTLibcallImpl);
1016 Info.Callee = MachineOperand::CreateES(SymName: LibcallName.data());
1017 Info.OrigRet = CallLowering::ArgInfo(RetRegs, RetTy, 0);
1018
1019 llvm::append_range(C&: Info.OrigArgs, R&: Args);
1020 if (!CLI.lowerCall(MIRBuilder, Info))
1021 return LegalizerHelper::UnableToLegalize;
1022
1023 return LegalizerHelper::Legalized;
1024}
1025
1026static RTLIB::Libcall
1027getStateLibraryFunctionFor(MachineInstr &MI, const TargetLowering &TLI) {
1028 RTLIB::Libcall RTLibcall;
1029 switch (MI.getOpcode()) {
1030 case TargetOpcode::G_GET_FPENV:
1031 RTLibcall = RTLIB::FEGETENV;
1032 break;
1033 case TargetOpcode::G_SET_FPENV:
1034 case TargetOpcode::G_RESET_FPENV:
1035 RTLibcall = RTLIB::FESETENV;
1036 break;
1037 case TargetOpcode::G_GET_FPMODE:
1038 RTLibcall = RTLIB::FEGETMODE;
1039 break;
1040 case TargetOpcode::G_SET_FPMODE:
1041 case TargetOpcode::G_RESET_FPMODE:
1042 RTLibcall = RTLIB::FESETMODE;
1043 break;
1044 default:
1045 llvm_unreachable("Unexpected opcode");
1046 }
1047 return RTLibcall;
1048}
1049
1050// Some library functions that read FP state (fegetmode, fegetenv) write the
1051// state into a region in memory. IR intrinsics that do the same operations
1052// (get_fpmode, get_fpenv) return the state as integer value. To implement these
1053// intrinsics via the library functions, we need to use temporary variable,
1054// for example:
1055//
1056// %0:_(s32) = G_GET_FPMODE
1057//
1058// is transformed to:
1059//
1060// %1:_(p0) = G_FRAME_INDEX %stack.0
1061// BL &fegetmode
1062// %0:_(s32) = G_LOAD % 1
1063//
1064LegalizerHelper::LegalizeResult
1065LegalizerHelper::createGetStateLibcall(MachineInstr &MI,
1066 LostDebugLocObserver &LocObserver) {
1067 const DataLayout &DL = MIRBuilder.getDataLayout();
1068 auto &MF = MIRBuilder.getMF();
1069 auto &MRI = *MIRBuilder.getMRI();
1070 auto &Ctx = MF.getFunction().getContext();
1071
1072 // Create temporary, where library function will put the read state.
1073 Register Dst = MI.getOperand(i: 0).getReg();
1074 LLT StateTy = MRI.getType(Reg: Dst);
1075 TypeSize StateSize = StateTy.getSizeInBytes();
1076 Align TempAlign = getStackTemporaryAlignment(Type: StateTy);
1077 MachinePointerInfo TempPtrInfo;
1078 auto Temp = createStackTemporary(Bytes: StateSize, Alignment: TempAlign, PtrInfo&: TempPtrInfo);
1079
1080 // Create a call to library function, with the temporary as an argument.
1081 unsigned TempAddrSpace = DL.getAllocaAddrSpace();
1082 Type *StatePtrTy = PointerType::get(C&: Ctx, AddressSpace: TempAddrSpace);
1083 RTLIB::Libcall RTLibcall = getStateLibraryFunctionFor(MI, TLI);
1084 auto Res = createLibcall(
1085 Libcall: RTLibcall, Result: CallLowering::ArgInfo({0}, Type::getVoidTy(C&: Ctx), 0),
1086 Args: CallLowering::ArgInfo({Temp.getReg(Idx: 0), StatePtrTy, 0}), LocObserver,
1087 MI: nullptr);
1088 if (Res != LegalizerHelper::Legalized)
1089 return Res;
1090
1091 // Create a load from the temporary.
1092 MachineMemOperand *MMO = MF.getMachineMemOperand(
1093 PtrInfo: TempPtrInfo, F: MachineMemOperand::MOLoad, MemTy: StateTy, BaseAlignment: TempAlign);
1094 MIRBuilder.buildLoadInstr(Opcode: TargetOpcode::G_LOAD, Res: Dst, Addr: Temp, MMO&: *MMO);
1095
1096 return LegalizerHelper::Legalized;
1097}
1098
1099// Similar to `createGetStateLibcall` the function calls a library function
1100// using transient space in stack. In this case the library function reads
1101// content of memory region.
1102LegalizerHelper::LegalizeResult
1103LegalizerHelper::createSetStateLibcall(MachineInstr &MI,
1104 LostDebugLocObserver &LocObserver) {
1105 const DataLayout &DL = MIRBuilder.getDataLayout();
1106 auto &MF = MIRBuilder.getMF();
1107 auto &MRI = *MIRBuilder.getMRI();
1108 auto &Ctx = MF.getFunction().getContext();
1109
1110 // Create temporary, where library function will get the new state.
1111 Register Src = MI.getOperand(i: 0).getReg();
1112 LLT StateTy = MRI.getType(Reg: Src);
1113 TypeSize StateSize = StateTy.getSizeInBytes();
1114 Align TempAlign = getStackTemporaryAlignment(Type: StateTy);
1115 MachinePointerInfo TempPtrInfo;
1116 auto Temp = createStackTemporary(Bytes: StateSize, Alignment: TempAlign, PtrInfo&: TempPtrInfo);
1117
1118 // Put the new state into the temporary.
1119 MachineMemOperand *MMO = MF.getMachineMemOperand(
1120 PtrInfo: TempPtrInfo, F: MachineMemOperand::MOStore, MemTy: StateTy, BaseAlignment: TempAlign);
1121 MIRBuilder.buildStore(Val: Src, Addr: Temp, MMO&: *MMO);
1122
1123 // Create a call to library function, with the temporary as an argument.
1124 unsigned TempAddrSpace = DL.getAllocaAddrSpace();
1125 Type *StatePtrTy = PointerType::get(C&: Ctx, AddressSpace: TempAddrSpace);
1126 RTLIB::Libcall RTLibcall = getStateLibraryFunctionFor(MI, TLI);
1127 return createLibcall(Libcall: RTLibcall,
1128 Result: CallLowering::ArgInfo({0}, Type::getVoidTy(C&: Ctx), 0),
1129 Args: CallLowering::ArgInfo({Temp.getReg(Idx: 0), StatePtrTy, 0}),
1130 LocObserver, MI: nullptr);
1131}
1132
1133/// Returns the corresponding libcall for the given Pred and
1134/// the ICMP predicate that should be generated to compare with #0
1135/// after the libcall.
1136static std::pair<RTLIB::Libcall, CmpInst::Predicate>
1137getFCMPLibcallDesc(const CmpInst::Predicate Pred, unsigned Size) {
1138#define RTLIBCASE_CMP(LibcallPrefix, ICmpPred) \
1139 do { \
1140 switch (Size) { \
1141 case 32: \
1142 return {RTLIB::LibcallPrefix##32, ICmpPred}; \
1143 case 64: \
1144 return {RTLIB::LibcallPrefix##64, ICmpPred}; \
1145 case 128: \
1146 return {RTLIB::LibcallPrefix##128, ICmpPred}; \
1147 default: \
1148 llvm_unreachable("unexpected size"); \
1149 } \
1150 } while (0)
1151
1152 // These use the three-way (-1/0/1) compare libcalls, whose result is tested
1153 // against 0 with a signed integer predicate. Unordered (UO) is a boolean.
1154 switch (Pred) {
1155 case CmpInst::FCMP_OEQ:
1156 RTLIBCASE_CMP(FCMP3_PRED_OEQ_F, CmpInst::ICMP_EQ);
1157 case CmpInst::FCMP_UNE:
1158 RTLIBCASE_CMP(FCMP3_PRED_UNE_F, CmpInst::ICMP_NE);
1159 case CmpInst::FCMP_OGE:
1160 RTLIBCASE_CMP(FCMP3_PRED_OGE_F, CmpInst::ICMP_SGE);
1161 case CmpInst::FCMP_OLT:
1162 RTLIBCASE_CMP(FCMP3_PRED_OLT_F, CmpInst::ICMP_SLT);
1163 case CmpInst::FCMP_OLE:
1164 RTLIBCASE_CMP(FCMP3_PRED_OLE_F, CmpInst::ICMP_SLE);
1165 case CmpInst::FCMP_OGT:
1166 RTLIBCASE_CMP(FCMP3_PRED_OGT_F, CmpInst::ICMP_SGT);
1167 case CmpInst::FCMP_UNO:
1168 RTLIBCASE_CMP(UO_F, CmpInst::ICMP_NE);
1169 default:
1170 return {RTLIB::UNKNOWN_LIBCALL, CmpInst::BAD_ICMP_PREDICATE};
1171 }
1172}
1173
1174LegalizerHelper::LegalizeResult
1175LegalizerHelper::createFCMPLibcall(MachineInstr &MI,
1176 LostDebugLocObserver &LocObserver) {
1177 auto &MF = MIRBuilder.getMF();
1178 auto &Ctx = MF.getFunction().getContext();
1179 const GFCmp *Cmp = cast<GFCmp>(Val: &MI);
1180
1181 LLT OpLLT = MRI.getType(Reg: Cmp->getLHSReg());
1182 unsigned Size = OpLLT.getSizeInBits();
1183 if ((Size != 32 && Size != 64 && Size != 128) ||
1184 OpLLT != MRI.getType(Reg: Cmp->getRHSReg()))
1185 return UnableToLegalize;
1186
1187 Type *OpType = getFloatTypeForLLT(Ctx, Ty: OpLLT);
1188
1189 // DstReg type is s32
1190 const Register DstReg = Cmp->getReg(Idx: 0);
1191 LLT DstTy = MRI.getType(Reg: DstReg);
1192 const auto Cond = Cmp->getCond();
1193
1194 // Reference:
1195 // https://gcc.gnu.org/onlinedocs/gccint/Soft-float-library-routines.html#Comparison-functions-1
1196 // Generates a libcall followed by ICMP.
1197 const auto BuildLibcall = [&](const RTLIB::Libcall Libcall,
1198 const CmpInst::Predicate ICmpPred,
1199 const DstOp &Res) -> Register {
1200 // FCMP libcall always returns an i32, and needs an ICMP with #0.
1201 LLT TempLLT = LLT::integer(SizeInBits: 32);
1202 Register Temp = MRI.createGenericVirtualRegister(Ty: TempLLT);
1203 // Generate libcall, holding result in Temp
1204 const auto Status = createLibcall(
1205 Libcall, Result: {Temp, Type::getInt32Ty(C&: Ctx), 0},
1206 Args: {{Cmp->getLHSReg(), OpType, 0}, {Cmp->getRHSReg(), OpType, 1}},
1207 LocObserver, MI: &MI);
1208 if (Status != Legalized)
1209 return {};
1210
1211 // Compare temp with #0 to get the final result.
1212 return MIRBuilder
1213 .buildICmp(Pred: ICmpPred, Res, Op0: Temp, Op1: MIRBuilder.buildConstant(Res: TempLLT, Val: 0))
1214 .getReg(Idx: 0);
1215 };
1216
1217 // Simple case if we have a direct mapping from predicate to libcall
1218 if (const auto [Libcall, ICmpPred] = getFCMPLibcallDesc(Pred: Cond, Size);
1219 Libcall != RTLIB::UNKNOWN_LIBCALL &&
1220 ICmpPred != CmpInst::BAD_ICMP_PREDICATE) {
1221 if (BuildLibcall(Libcall, ICmpPred, DstReg)) {
1222 return Legalized;
1223 }
1224 return UnableToLegalize;
1225 }
1226
1227 // No direct mapping found, should be generated as combination of libcalls.
1228
1229 switch (Cond) {
1230 case CmpInst::FCMP_UEQ: {
1231 // FCMP_UEQ: unordered or equal
1232 // Convert into (FCMP_OEQ || FCMP_UNO).
1233
1234 const auto [OeqLibcall, OeqPred] =
1235 getFCMPLibcallDesc(Pred: CmpInst::FCMP_OEQ, Size);
1236 const auto Oeq = BuildLibcall(OeqLibcall, OeqPred, DstTy);
1237
1238 const auto [UnoLibcall, UnoPred] =
1239 getFCMPLibcallDesc(Pred: CmpInst::FCMP_UNO, Size);
1240 const auto Uno = BuildLibcall(UnoLibcall, UnoPred, DstTy);
1241 if (Oeq && Uno)
1242 MIRBuilder.buildOr(Dst: DstReg, Src0: Oeq, Src1: Uno);
1243 else
1244 return UnableToLegalize;
1245
1246 break;
1247 }
1248 case CmpInst::FCMP_ONE: {
1249 // FCMP_ONE: ordered and operands are unequal
1250 // Convert into (!FCMP_OEQ && !FCMP_UNO).
1251
1252 // We inverse the predicate instead of generating a NOT
1253 // to save one instruction.
1254 // On AArch64 isel can even select two cmp into a single ccmp.
1255 const auto [OeqLibcall, OeqPred] =
1256 getFCMPLibcallDesc(Pred: CmpInst::FCMP_OEQ, Size);
1257 const auto NotOeq =
1258 BuildLibcall(OeqLibcall, CmpInst::getInversePredicate(pred: OeqPred), DstTy);
1259
1260 const auto [UnoLibcall, UnoPred] =
1261 getFCMPLibcallDesc(Pred: CmpInst::FCMP_UNO, Size);
1262 const auto NotUno =
1263 BuildLibcall(UnoLibcall, CmpInst::getInversePredicate(pred: UnoPred), DstTy);
1264
1265 if (NotOeq && NotUno)
1266 MIRBuilder.buildAnd(Dst: DstReg, Src0: NotOeq, Src1: NotUno);
1267 else
1268 return UnableToLegalize;
1269
1270 break;
1271 }
1272 case CmpInst::FCMP_ULT:
1273 case CmpInst::FCMP_UGE:
1274 case CmpInst::FCMP_UGT:
1275 case CmpInst::FCMP_ULE:
1276 case CmpInst::FCMP_ORD: {
1277 // Convert into: !(inverse(Pred))
1278 // E.g. FCMP_ULT becomes !FCMP_OGE
1279 // This is equivalent to the following, but saves some instructions.
1280 // MIRBuilder.buildNot(
1281 // PredTy,
1282 // MIRBuilder.buildFCmp(CmpInst::getInversePredicate(Pred), PredTy,
1283 // Op1, Op2));
1284 const auto [InversedLibcall, InversedPred] =
1285 getFCMPLibcallDesc(Pred: CmpInst::getInversePredicate(pred: Cond), Size);
1286 if (!BuildLibcall(InversedLibcall,
1287 CmpInst::getInversePredicate(pred: InversedPred), DstReg))
1288 return UnableToLegalize;
1289 break;
1290 }
1291 default:
1292 return UnableToLegalize;
1293 }
1294
1295 return Legalized;
1296}
1297
1298// The function is used to legalize operations that set default environment
1299// state. In C library a call like `fesetmode(FE_DFL_MODE)` is used for that.
1300// On most targets supported in glibc FE_DFL_MODE is defined as
1301// `((const femode_t *) -1)`. Such assumption is used here. If for some target
1302// it is not true, the target must provide custom lowering.
1303LegalizerHelper::LegalizeResult
1304LegalizerHelper::createResetStateLibcall(MachineInstr &MI,
1305 LostDebugLocObserver &LocObserver) {
1306 const DataLayout &DL = MIRBuilder.getDataLayout();
1307 auto &MF = MIRBuilder.getMF();
1308 auto &Ctx = MF.getFunction().getContext();
1309
1310 // Create an argument for the library function.
1311 unsigned AddrSpace = DL.getDefaultGlobalsAddressSpace();
1312 Type *StatePtrTy = PointerType::get(C&: Ctx, AddressSpace: AddrSpace);
1313 unsigned PtrSize = DL.getPointerSizeInBits(AS: AddrSpace);
1314 LLT MemTy = LLT::pointer(AddressSpace: AddrSpace, SizeInBits: PtrSize);
1315 auto DefValue = MIRBuilder.buildConstant(Res: LLT::integer(SizeInBits: PtrSize), Val: -1LL);
1316 DstOp Dest(MRI.createGenericVirtualRegister(Ty: MemTy));
1317 MIRBuilder.buildIntToPtr(Dst: Dest, Src: DefValue);
1318
1319 RTLIB::Libcall RTLibcall = getStateLibraryFunctionFor(MI, TLI);
1320 return createLibcall(
1321 Libcall: RTLibcall, Result: CallLowering::ArgInfo({0}, Type::getVoidTy(C&: Ctx), 0),
1322 Args: CallLowering::ArgInfo({Dest.getReg(), StatePtrTy, 0}), LocObserver, MI: &MI);
1323}
1324
1325LegalizerHelper::LegalizeResult
1326LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
1327 auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
1328
1329 switch (MI.getOpcode()) {
1330 default:
1331 return UnableToLegalize;
1332 case TargetOpcode::G_MUL:
1333 case TargetOpcode::G_SDIV:
1334 case TargetOpcode::G_UDIV:
1335 case TargetOpcode::G_SREM:
1336 case TargetOpcode::G_UREM:
1337 case TargetOpcode::G_CTLZ_ZERO_POISON: {
1338 LLT LLTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
1339 unsigned Size = LLTy.getSizeInBits();
1340 Type *HLTy = IntegerType::get(C&: Ctx, NumBits: Size);
1341 auto Status = simpleLibcall(MI, MIRBuilder, Size, OpType: HLTy, LocObserver);
1342 if (Status != Legalized)
1343 return Status;
1344 break;
1345 }
1346 case TargetOpcode::G_FADD:
1347 case TargetOpcode::G_FSUB:
1348 case TargetOpcode::G_FMUL:
1349 case TargetOpcode::G_FDIV:
1350 case TargetOpcode::G_FMA:
1351 case TargetOpcode::G_FPOW:
1352 case TargetOpcode::G_FREM:
1353 case TargetOpcode::G_FCOS:
1354 case TargetOpcode::G_FSIN:
1355 case TargetOpcode::G_FTAN:
1356 case TargetOpcode::G_FACOS:
1357 case TargetOpcode::G_FASIN:
1358 case TargetOpcode::G_FATAN:
1359 case TargetOpcode::G_FATAN2:
1360 case TargetOpcode::G_FCOSH:
1361 case TargetOpcode::G_FSINH:
1362 case TargetOpcode::G_FTANH:
1363 case TargetOpcode::G_FLOG10:
1364 case TargetOpcode::G_FLOG:
1365 case TargetOpcode::G_FLOG2:
1366 case TargetOpcode::G_FEXP:
1367 case TargetOpcode::G_FEXP2:
1368 case TargetOpcode::G_FEXP10:
1369 case TargetOpcode::G_FCEIL:
1370 case TargetOpcode::G_FFLOOR:
1371 case TargetOpcode::G_FMINNUM:
1372 case TargetOpcode::G_FMAXNUM:
1373 case TargetOpcode::G_FMINIMUMNUM:
1374 case TargetOpcode::G_FMAXIMUMNUM:
1375 case TargetOpcode::G_FSQRT:
1376 case TargetOpcode::G_FRINT:
1377 case TargetOpcode::G_FNEARBYINT:
1378 case TargetOpcode::G_INTRINSIC_TRUNC:
1379 case TargetOpcode::G_INTRINSIC_ROUND:
1380 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: {
1381 LLT LLTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
1382 unsigned Size = LLTy.getSizeInBits();
1383 Type *HLTy = getFloatTypeForLLT(Ctx, Ty: LLTy);
1384 if (!HLTy || (Size != 32 && Size != 64 && Size != 80 && Size != 128)) {
1385 LLVM_DEBUG(dbgs() << "No libcall available for type " << LLTy << ".\n");
1386 return UnableToLegalize;
1387 }
1388 auto Status = simpleLibcall(MI, MIRBuilder, Size, OpType: HLTy, LocObserver);
1389 if (Status != Legalized)
1390 return Status;
1391 break;
1392 }
1393 case TargetOpcode::G_FSINCOS: {
1394 LLT LLTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
1395 unsigned Size = LLTy.getSizeInBits();
1396 Type *HLTy = getFloatTypeForLLT(Ctx, Ty: LLTy);
1397 if (!HLTy || (Size != 32 && Size != 64 && Size != 80 && Size != 128)) {
1398 LLVM_DEBUG(dbgs() << "No libcall available for type " << LLTy << ".\n");
1399 return UnableToLegalize;
1400 }
1401 return emitSincosLibcall(MI, MIRBuilder, Size, OpType: HLTy, LocObserver);
1402 }
1403 case TargetOpcode::G_FMODF: {
1404 LLT LLTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
1405 unsigned Size = LLTy.getSizeInBits();
1406 Type *HLTy = getFloatTypeForLLT(Ctx, Ty: LLTy);
1407 if (!HLTy || (Size != 32 && Size != 64 && Size != 80 && Size != 128)) {
1408 LLVM_DEBUG(dbgs() << "No libcall available for type " << LLTy << ".\n");
1409 return UnableToLegalize;
1410 }
1411 return emitModfLibcall(MI, MIRBuilder, Size, OpType: HLTy, LocObserver);
1412 }
1413 case TargetOpcode::G_LROUND:
1414 case TargetOpcode::G_LLROUND:
1415 case TargetOpcode::G_INTRINSIC_LRINT:
1416 case TargetOpcode::G_INTRINSIC_LLRINT: {
1417 LLT LLTy = MRI.getType(Reg: MI.getOperand(i: 1).getReg());
1418 unsigned Size = LLTy.getSizeInBits();
1419 Type *HLTy = getFloatTypeForLLT(Ctx, Ty: LLTy);
1420 Type *ITy = IntegerType::get(
1421 C&: Ctx, NumBits: MRI.getType(Reg: MI.getOperand(i: 0).getReg()).getSizeInBits());
1422 if (!HLTy || (Size != 32 && Size != 64 && Size != 80 && Size != 128)) {
1423 LLVM_DEBUG(dbgs() << "No libcall available for type " << LLTy << ".\n");
1424 return UnableToLegalize;
1425 }
1426 auto Libcall = getRTLibDesc(Opcode: MI.getOpcode(), Size);
1427 LegalizeResult Status =
1428 createLibcall(Libcall, Result: {MI.getOperand(i: 0).getReg(), ITy, 0},
1429 Args: {{MI.getOperand(i: 1).getReg(), HLTy, 0}}, LocObserver, MI: &MI);
1430 if (Status != Legalized)
1431 return Status;
1432 MI.eraseFromParent();
1433 return Legalized;
1434 }
1435 case TargetOpcode::G_FPOWI:
1436 case TargetOpcode::G_FLDEXP: {
1437 LLT LLTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
1438 unsigned Size = LLTy.getSizeInBits();
1439 Type *HLTy = getFloatTypeForLLT(Ctx, Ty: LLTy);
1440 Type *ITy = IntegerType::get(
1441 C&: Ctx, NumBits: MRI.getType(Reg: MI.getOperand(i: 2).getReg()).getSizeInBits());
1442 if (!HLTy || (Size != 32 && Size != 64 && Size != 80 && Size != 128)) {
1443 LLVM_DEBUG(dbgs() << "No libcall available for type " << LLTy << ".\n");
1444 return UnableToLegalize;
1445 }
1446 auto Libcall = getRTLibDesc(Opcode: MI.getOpcode(), Size);
1447 SmallVector<CallLowering::ArgInfo, 2> Args = {
1448 {MI.getOperand(i: 1).getReg(), HLTy, 0},
1449 {MI.getOperand(i: 2).getReg(), ITy, 1}};
1450 Args[1].Flags[0].setSExt();
1451 LegalizeResult Status = createLibcall(
1452 Libcall, Result: {MI.getOperand(i: 0).getReg(), HLTy, 0}, Args, LocObserver, MI: &MI);
1453 if (Status != Legalized)
1454 return Status;
1455 break;
1456 }
1457 case TargetOpcode::G_FPEXT:
1458 case TargetOpcode::G_FPTRUNC: {
1459 Type *FromTy = getFloatTypeForLLT(Ctx, Ty: MRI.getType(Reg: MI.getOperand(i: 1).getReg()));
1460 Type *ToTy = getFloatTypeForLLT(Ctx, Ty: MRI.getType(Reg: MI.getOperand(i: 0).getReg()));
1461 if (!FromTy || !ToTy)
1462 return UnableToLegalize;
1463 LegalizeResult Status = conversionLibcall(MI, ToType: ToTy, FromType: FromTy, LocObserver);
1464 if (Status != Legalized)
1465 return Status;
1466 break;
1467 }
1468 case TargetOpcode::G_FCMP: {
1469 LegalizeResult Status = createFCMPLibcall(MI, LocObserver);
1470 if (Status != Legalized)
1471 return Status;
1472 MI.eraseFromParent();
1473 return Status;
1474 }
1475 case TargetOpcode::G_FPTOSI:
1476 case TargetOpcode::G_FPTOUI: {
1477 // FIXME: Support other types
1478 Type *FromTy =
1479 getFloatTypeForLLT(Ctx, Ty: MRI.getType(Reg: MI.getOperand(i: 1).getReg()));
1480 unsigned ToSize = MRI.getType(Reg: MI.getOperand(i: 0).getReg()).getSizeInBits();
1481 if ((ToSize != 32 && ToSize != 64 && ToSize != 128) || !FromTy)
1482 return UnableToLegalize;
1483 LegalizeResult Status = conversionLibcall(MI, ToType: Type::getIntNTy(C&: Ctx, N: ToSize),
1484 FromType: FromTy, LocObserver);
1485 if (Status != Legalized)
1486 return Status;
1487 break;
1488 }
1489 case TargetOpcode::G_SITOFP:
1490 case TargetOpcode::G_UITOFP: {
1491 unsigned FromSize = MRI.getType(Reg: MI.getOperand(i: 1).getReg()).getSizeInBits();
1492 Type *ToTy =
1493 getFloatTypeForLLT(Ctx, Ty: MRI.getType(Reg: MI.getOperand(i: 0).getReg()));
1494 if ((FromSize != 32 && FromSize != 64 && FromSize != 128) || !ToTy)
1495 return UnableToLegalize;
1496 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SITOFP;
1497 LegalizeResult Status = conversionLibcall(
1498 MI, ToType: ToTy, FromType: Type::getIntNTy(C&: Ctx, N: FromSize), LocObserver, IsSigned);
1499 if (Status != Legalized)
1500 return Status;
1501 break;
1502 }
1503 case TargetOpcode::G_ATOMICRMW_XCHG:
1504 case TargetOpcode::G_ATOMICRMW_ADD:
1505 case TargetOpcode::G_ATOMICRMW_SUB:
1506 case TargetOpcode::G_ATOMICRMW_AND:
1507 case TargetOpcode::G_ATOMICRMW_OR:
1508 case TargetOpcode::G_ATOMICRMW_XOR:
1509 case TargetOpcode::G_ATOMIC_CMPXCHG:
1510 case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
1511 auto Status = createAtomicLibcall(MI);
1512 if (Status != Legalized)
1513 return Status;
1514 break;
1515 }
1516 case TargetOpcode::G_BZERO:
1517 case TargetOpcode::G_MEMCPY:
1518 case TargetOpcode::G_MEMMOVE:
1519 case TargetOpcode::G_MEMSET: {
1520 LegalizeResult Result =
1521 createMemLibcall(MRI&: *MIRBuilder.getMRI(), MI, LocObserver);
1522 if (Result != Legalized)
1523 return Result;
1524 MI.eraseFromParent();
1525 return Result;
1526 }
1527 case TargetOpcode::G_GET_FPENV:
1528 case TargetOpcode::G_GET_FPMODE: {
1529 LegalizeResult Result = createGetStateLibcall(MI, LocObserver);
1530 if (Result != Legalized)
1531 return Result;
1532 break;
1533 }
1534 case TargetOpcode::G_SET_FPENV:
1535 case TargetOpcode::G_SET_FPMODE: {
1536 LegalizeResult Result = createSetStateLibcall(MI, LocObserver);
1537 if (Result != Legalized)
1538 return Result;
1539 break;
1540 }
1541 case TargetOpcode::G_RESET_FPENV:
1542 case TargetOpcode::G_RESET_FPMODE: {
1543 LegalizeResult Result = createResetStateLibcall(MI, LocObserver);
1544 if (Result != Legalized)
1545 return Result;
1546 break;
1547 }
1548 }
1549
1550 MI.eraseFromParent();
1551 return Legalized;
1552}
1553
1554LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
1555 unsigned TypeIdx,
1556 LLT NarrowTy) {
1557 uint64_t SizeOp0 = MRI.getType(Reg: MI.getOperand(i: 0).getReg()).getSizeInBits();
1558 uint64_t NarrowSize = NarrowTy.getSizeInBits();
1559
1560 switch (MI.getOpcode()) {
1561 default:
1562 return UnableToLegalize;
1563 case TargetOpcode::G_IMPLICIT_DEF: {
1564 Register DstReg = MI.getOperand(i: 0).getReg();
1565 LLT DstTy = MRI.getType(Reg: DstReg);
1566
1567 // If SizeOp0 is not an exact multiple of NarrowSize, emit
1568 // G_ANYEXT(G_IMPLICIT_DEF). Cast result to vector if needed.
1569 // FIXME: Although this would also be legal for the general case, it causes
1570 // a lot of regressions in the emitted code (superfluous COPYs, artifact
1571 // combines not being hit). This seems to be a problem related to the
1572 // artifact combiner.
1573 if (SizeOp0 % NarrowSize != 0) {
1574 LLT ImplicitTy = DstTy.changeElementType(NewEltTy: NarrowTy);
1575 Register ImplicitReg = MIRBuilder.buildUndef(Res: ImplicitTy).getReg(Idx: 0);
1576 MIRBuilder.buildAnyExt(Res: DstReg, Op: ImplicitReg);
1577
1578 MI.eraseFromParent();
1579 return Legalized;
1580 }
1581
1582 int NumParts = SizeOp0 / NarrowSize;
1583
1584 SmallVector<Register, 2> DstRegs;
1585 for (int i = 0; i < NumParts; ++i)
1586 DstRegs.push_back(Elt: MIRBuilder.buildUndef(Res: NarrowTy).getReg(Idx: 0));
1587
1588 if (DstTy.isVector())
1589 MIRBuilder.buildBuildVector(Res: DstReg, Ops: DstRegs);
1590 else
1591 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: DstRegs);
1592 MI.eraseFromParent();
1593 return Legalized;
1594 }
1595 case TargetOpcode::G_CONSTANT: {
1596 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
1597 const APInt &Val = MI.getOperand(i: 1).getCImm()->getValue();
1598 unsigned TotalSize = Ty.getSizeInBits();
1599 unsigned NarrowSize = NarrowTy.getSizeInBits();
1600 int NumParts = TotalSize / NarrowSize;
1601
1602 SmallVector<Register, 4> PartRegs;
1603 for (int I = 0; I != NumParts; ++I) {
1604 unsigned Offset = I * NarrowSize;
1605 auto K = MIRBuilder.buildConstant(Res: NarrowTy,
1606 Val: Val.lshr(shiftAmt: Offset).trunc(width: NarrowSize));
1607 PartRegs.push_back(Elt: K.getReg(Idx: 0));
1608 }
1609
1610 LLT LeftoverTy;
1611 unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
1612 SmallVector<Register, 1> LeftoverRegs;
1613 if (LeftoverBits != 0) {
1614 LeftoverTy = LLT::scalar(SizeInBits: LeftoverBits);
1615 auto K = MIRBuilder.buildConstant(
1616 Res: LeftoverTy,
1617 Val: Val.lshr(shiftAmt: NumParts * NarrowSize).trunc(width: LeftoverBits));
1618 LeftoverRegs.push_back(Elt: K.getReg(Idx: 0));
1619 }
1620
1621 insertParts(DstReg: MI.getOperand(i: 0).getReg(),
1622 ResultTy: Ty, PartTy: NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
1623
1624 MI.eraseFromParent();
1625 return Legalized;
1626 }
1627 case TargetOpcode::G_SEXT:
1628 case TargetOpcode::G_ZEXT:
1629 case TargetOpcode::G_ANYEXT:
1630 return narrowScalarExt(MI, TypeIdx, Ty: NarrowTy);
1631 case TargetOpcode::G_TRUNC: {
1632 if (TypeIdx != 1)
1633 return UnableToLegalize;
1634
1635 uint64_t SizeOp1 = MRI.getType(Reg: MI.getOperand(i: 1).getReg()).getSizeInBits();
1636 if (NarrowTy.getSizeInBits() * 2 != SizeOp1) {
1637 LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n");
1638 return UnableToLegalize;
1639 }
1640
1641 auto Unmerge = MIRBuilder.buildUnmerge(Res: NarrowTy, Op: MI.getOperand(i: 1));
1642 MIRBuilder.buildCopy(Res: MI.getOperand(i: 0), Op: Unmerge.getReg(Idx: 0));
1643 MI.eraseFromParent();
1644 return Legalized;
1645 }
1646 case TargetOpcode::G_CONSTANT_FOLD_BARRIER:
1647 case TargetOpcode::G_FREEZE: {
1648 if (TypeIdx != 0)
1649 return UnableToLegalize;
1650
1651 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
1652 // Should widen scalar first
1653 if (Ty.getSizeInBits() % NarrowTy.getSizeInBits() != 0)
1654 return UnableToLegalize;
1655
1656 auto Unmerge = MIRBuilder.buildUnmerge(Res: NarrowTy, Op: MI.getOperand(i: 1).getReg());
1657 SmallVector<Register, 8> Parts;
1658 for (unsigned i = 0; i < Unmerge->getNumDefs(); ++i) {
1659 Parts.push_back(
1660 Elt: MIRBuilder.buildInstr(Opc: MI.getOpcode(), DstOps: {NarrowTy}, SrcOps: {Unmerge.getReg(Idx: i)})
1661 .getReg(Idx: 0));
1662 }
1663
1664 MIRBuilder.buildMergeLikeInstr(Res: MI.getOperand(i: 0).getReg(), Ops: Parts);
1665 MI.eraseFromParent();
1666 return Legalized;
1667 }
1668 case TargetOpcode::G_ADD:
1669 case TargetOpcode::G_SUB:
1670 case TargetOpcode::G_SADDO:
1671 case TargetOpcode::G_SSUBO:
1672 case TargetOpcode::G_SADDE:
1673 case TargetOpcode::G_SSUBE:
1674 case TargetOpcode::G_UADDO:
1675 case TargetOpcode::G_USUBO:
1676 case TargetOpcode::G_UADDE:
1677 case TargetOpcode::G_USUBE:
1678 return narrowScalarAddSub(MI, TypeIdx, NarrowTy);
1679 case TargetOpcode::G_MUL:
1680 case TargetOpcode::G_UMULH:
1681 return narrowScalarMul(MI, Ty: NarrowTy);
1682 case TargetOpcode::G_EXTRACT:
1683 return narrowScalarExtract(MI, TypeIdx, Ty: NarrowTy);
1684 case TargetOpcode::G_INSERT:
1685 return narrowScalarInsert(MI, TypeIdx, Ty: NarrowTy);
1686 case TargetOpcode::G_LOAD: {
1687 auto &LoadMI = cast<GLoad>(Val&: MI);
1688 Register DstReg = LoadMI.getDstReg();
1689 LLT DstTy = MRI.getType(Reg: DstReg);
1690 if (DstTy.isVector())
1691 return UnableToLegalize;
1692
1693 if (8 * LoadMI.getMemSize().getValue() != DstTy.getSizeInBits()) {
1694 Register TmpReg = MRI.createGenericVirtualRegister(Ty: NarrowTy);
1695 MIRBuilder.buildLoad(Res: TmpReg, Addr: LoadMI.getPointerReg(), MMO&: LoadMI.getMMO());
1696 MIRBuilder.buildAnyExt(Res: DstReg, Op: TmpReg);
1697 LoadMI.eraseFromParent();
1698 return Legalized;
1699 }
1700
1701 return reduceLoadStoreWidth(MI&: LoadMI, TypeIdx, NarrowTy);
1702 }
1703 case TargetOpcode::G_ZEXTLOAD:
1704 case TargetOpcode::G_SEXTLOAD:
1705 case TargetOpcode::G_FPEXTLOAD: {
1706 auto &LoadMI = cast<GExtLoad>(Val&: MI);
1707 Register DstReg = LoadMI.getDstReg();
1708 Register PtrReg = LoadMI.getPointerReg();
1709
1710 Register TmpReg = MRI.createGenericVirtualRegister(Ty: NarrowTy);
1711 auto &MMO = LoadMI.getMMO();
1712 unsigned MemSize = MMO.getSizeInBits().getValue();
1713
1714 if (MemSize == NarrowSize) {
1715 MIRBuilder.buildLoad(Res: TmpReg, Addr: PtrReg, MMO);
1716 } else if (MemSize < NarrowSize) {
1717 MIRBuilder.buildLoadInstr(Opcode: LoadMI.getOpcode(), Res: TmpReg, Addr: PtrReg, MMO);
1718 } else if (MemSize > NarrowSize) {
1719 // FIXME: Need to split the load.
1720 return UnableToLegalize;
1721 }
1722
1723 if (isa<GZExtLoad>(Val: LoadMI))
1724 MIRBuilder.buildZExt(Res: DstReg, Op: TmpReg);
1725 else if (isa<GSExtLoad>(Val: LoadMI))
1726 MIRBuilder.buildSExt(Res: DstReg, Op: TmpReg);
1727 else
1728 MIRBuilder.buildFPExt(Res: DstReg, Op: TmpReg);
1729
1730 LoadMI.eraseFromParent();
1731 return Legalized;
1732 }
1733 case TargetOpcode::G_STORE: {
1734 auto &StoreMI = cast<GStore>(Val&: MI);
1735
1736 Register SrcReg = StoreMI.getValueReg();
1737 LLT SrcTy = MRI.getType(Reg: SrcReg);
1738 if (SrcTy.isVector())
1739 return UnableToLegalize;
1740
1741 int NumParts = SizeOp0 / NarrowSize;
1742 unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
1743 unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
1744 if (SrcTy.isVector() && LeftoverBits != 0)
1745 return UnableToLegalize;
1746
1747 if (8 * StoreMI.getMemSize().getValue() != SrcTy.getSizeInBits()) {
1748 Register TmpReg = MRI.createGenericVirtualRegister(Ty: NarrowTy);
1749 MIRBuilder.buildTrunc(Res: TmpReg, Op: SrcReg);
1750 MIRBuilder.buildStore(Val: TmpReg, Addr: StoreMI.getPointerReg(), MMO&: StoreMI.getMMO());
1751 StoreMI.eraseFromParent();
1752 return Legalized;
1753 }
1754
1755 return reduceLoadStoreWidth(MI&: StoreMI, TypeIdx: 0, NarrowTy);
1756 }
1757 case TargetOpcode::G_FPTRUNCSTORE: {
1758 auto &StoreMI = cast<GFPTruncStore>(Val&: MI);
1759 Register SrcReg = StoreMI.getValueReg();
1760 Register PtrReg = StoreMI.getPointerReg();
1761
1762 auto &MMO = StoreMI.getMMO();
1763 unsigned MemSize = MMO.getSizeInBits().getValue();
1764 if (MemSize > NarrowSize) {
1765 return UnableToLegalize;
1766 }
1767
1768 auto TmpReg = MIRBuilder.buildFPTrunc(Res: NarrowTy, Op: SrcReg);
1769 if (MemSize == NarrowSize) {
1770 MIRBuilder.buildStore(Val: TmpReg, Addr: PtrReg, MMO);
1771 } else if (MemSize < NarrowSize) {
1772 MIRBuilder.buildStoreInstr(Opcode: TargetOpcode::G_FPTRUNCSTORE, Val: TmpReg, Addr: PtrReg,
1773 MMO);
1774 }
1775
1776 StoreMI.eraseFromParent();
1777 return Legalized;
1778 }
1779 case TargetOpcode::G_SELECT:
1780 return narrowScalarSelect(MI, TypeIdx, Ty: NarrowTy);
1781 case TargetOpcode::G_AND:
1782 case TargetOpcode::G_OR:
1783 case TargetOpcode::G_XOR: {
1784 // Legalize bitwise operation:
1785 // A = BinOp<Ty> B, C
1786 // into:
1787 // B1, ..., BN = G_UNMERGE_VALUES B
1788 // C1, ..., CN = G_UNMERGE_VALUES C
1789 // A1 = BinOp<Ty/N> B1, C2
1790 // ...
1791 // AN = BinOp<Ty/N> BN, CN
1792 // A = G_MERGE_VALUES A1, ..., AN
1793 return narrowScalarBasic(MI, TypeIdx, Ty: NarrowTy);
1794 }
1795 case TargetOpcode::G_SHL:
1796 case TargetOpcode::G_LSHR:
1797 case TargetOpcode::G_ASHR:
1798 return narrowScalarShift(MI, TypeIdx, Ty: NarrowTy);
1799 case TargetOpcode::G_CTLZ:
1800 case TargetOpcode::G_CTLZ_ZERO_POISON:
1801 case TargetOpcode::G_CTTZ:
1802 case TargetOpcode::G_CTTZ_ZERO_POISON:
1803 case TargetOpcode::G_CTLS:
1804 case TargetOpcode::G_CTPOP:
1805 if (TypeIdx == 1)
1806 switch (MI.getOpcode()) {
1807 case TargetOpcode::G_CTLZ:
1808 case TargetOpcode::G_CTLZ_ZERO_POISON:
1809 return narrowScalarCTLZ(MI, TypeIdx, Ty: NarrowTy);
1810 case TargetOpcode::G_CTTZ:
1811 case TargetOpcode::G_CTTZ_ZERO_POISON:
1812 return narrowScalarCTTZ(MI, TypeIdx, Ty: NarrowTy);
1813 case TargetOpcode::G_CTPOP:
1814 return narrowScalarCTPOP(MI, TypeIdx, Ty: NarrowTy);
1815 case TargetOpcode::G_CTLS:
1816 return narrowScalarCTLS(MI, TypeIdx, Ty: NarrowTy);
1817 default:
1818 return UnableToLegalize;
1819 }
1820
1821 Observer.changingInstr(MI);
1822 narrowScalarDst(MI, NarrowTy, OpIdx: 0, ExtOpcode: TargetOpcode::G_ZEXT);
1823 Observer.changedInstr(MI);
1824 return Legalized;
1825 case TargetOpcode::G_INTTOPTR:
1826 if (TypeIdx != 1)
1827 return UnableToLegalize;
1828
1829 Observer.changingInstr(MI);
1830 narrowScalarSrc(MI, NarrowTy, OpIdx: 1);
1831 Observer.changedInstr(MI);
1832 return Legalized;
1833 case TargetOpcode::G_PTRTOINT:
1834 if (TypeIdx != 0)
1835 return UnableToLegalize;
1836
1837 Observer.changingInstr(MI);
1838 narrowScalarDst(MI, NarrowTy, OpIdx: 0, ExtOpcode: TargetOpcode::G_ZEXT);
1839 Observer.changedInstr(MI);
1840 return Legalized;
1841 case TargetOpcode::G_PHI: {
1842 // FIXME: add support for when SizeOp0 isn't an exact multiple of
1843 // NarrowSize.
1844 if (SizeOp0 % NarrowSize != 0)
1845 return UnableToLegalize;
1846
1847 unsigned NumParts = SizeOp0 / NarrowSize;
1848 SmallVector<Register, 2> DstRegs(NumParts);
1849 SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2);
1850 Observer.changingInstr(MI);
1851 for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
1852 MachineBasicBlock &OpMBB = *MI.getOperand(i: i + 1).getMBB();
1853 MIRBuilder.setInsertPt(MBB&: OpMBB, II: OpMBB.getFirstTerminatorForward());
1854 extractParts(Reg: MI.getOperand(i).getReg(), Ty: NarrowTy, NumParts,
1855 VRegs&: SrcRegs[i / 2], MIRBuilder, MRI);
1856 }
1857 MachineBasicBlock &MBB = *MI.getParent();
1858 MIRBuilder.setInsertPt(MBB, II: MI);
1859 for (unsigned i = 0; i < NumParts; ++i) {
1860 DstRegs[i] = MRI.createGenericVirtualRegister(Ty: NarrowTy);
1861 MachineInstrBuilder MIB =
1862 MIRBuilder.buildInstr(Opcode: TargetOpcode::G_PHI).addDef(RegNo: DstRegs[i]);
1863 for (unsigned j = 1; j < MI.getNumOperands(); j += 2)
1864 MIB.addUse(RegNo: SrcRegs[j / 2][i]).add(MO: MI.getOperand(i: j + 1));
1865 }
1866 MIRBuilder.setInsertPt(MBB, II: MBB.getFirstNonPHI());
1867 MIRBuilder.buildMergeLikeInstr(Res: MI.getOperand(i: 0), Ops: DstRegs);
1868 Observer.changedInstr(MI);
1869 MI.eraseFromParent();
1870 return Legalized;
1871 }
1872 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
1873 case TargetOpcode::G_INSERT_VECTOR_ELT: {
1874 if (TypeIdx != 2)
1875 return UnableToLegalize;
1876
1877 int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3;
1878 Observer.changingInstr(MI);
1879 narrowScalarSrc(MI, NarrowTy, OpIdx);
1880 Observer.changedInstr(MI);
1881 return Legalized;
1882 }
1883 case TargetOpcode::G_ICMP: {
1884 Register LHS = MI.getOperand(i: 2).getReg();
1885 LLT SrcTy = MRI.getType(Reg: LHS);
1886 CmpInst::Predicate Pred =
1887 static_cast<CmpInst::Predicate>(MI.getOperand(i: 1).getPredicate());
1888
1889 LLT LeftoverTy; // Example: s88 -> s64 (NarrowTy) + s24 (leftover)
1890 SmallVector<Register, 4> LHSPartRegs, LHSLeftoverRegs;
1891 if (!extractParts(Reg: LHS, RegTy: SrcTy, MainTy: NarrowTy, LeftoverTy, VRegs&: LHSPartRegs,
1892 LeftoverVRegs&: LHSLeftoverRegs, MIRBuilder, MRI))
1893 return UnableToLegalize;
1894
1895 LLT Unused; // Matches LeftoverTy; G_ICMP LHS and RHS are the same type.
1896 SmallVector<Register, 4> RHSPartRegs, RHSLeftoverRegs;
1897 if (!extractParts(Reg: MI.getOperand(i: 3).getReg(), RegTy: SrcTy, MainTy: NarrowTy, LeftoverTy&: Unused,
1898 VRegs&: RHSPartRegs, LeftoverVRegs&: RHSLeftoverRegs, MIRBuilder, MRI))
1899 return UnableToLegalize;
1900
1901 // We now have the LHS and RHS of the compare split into narrow-type
1902 // registers, plus potentially some leftover type.
1903 Register Dst = MI.getOperand(i: 0).getReg();
1904 LLT ResTy = MRI.getType(Reg: Dst);
1905 if (ICmpInst::isEquality(P: Pred)) {
1906 // For each part on the LHS and RHS, keep track of the result of XOR-ing
1907 // them together. For each equal part, the result should be all 0s. For
1908 // each non-equal part, we'll get at least one 1.
1909 auto Zero = MIRBuilder.buildConstant(Res: NarrowTy, Val: 0);
1910 SmallVector<Register, 4> Xors;
1911 for (auto LHSAndRHS : zip(t&: LHSPartRegs, u&: RHSPartRegs)) {
1912 auto LHS = std::get<0>(t&: LHSAndRHS);
1913 auto RHS = std::get<1>(t&: LHSAndRHS);
1914 auto Xor = MIRBuilder.buildXor(Dst: NarrowTy, Src0: LHS, Src1: RHS).getReg(Idx: 0);
1915 Xors.push_back(Elt: Xor);
1916 }
1917
1918 // Build a G_XOR for each leftover register. Each G_XOR must be widened
1919 // to the desired narrow type so that we can OR them together later.
1920 SmallVector<Register, 4> WidenedXors;
1921 for (auto LHSAndRHS : zip(t&: LHSLeftoverRegs, u&: RHSLeftoverRegs)) {
1922 auto LHS = std::get<0>(t&: LHSAndRHS);
1923 auto RHS = std::get<1>(t&: LHSAndRHS);
1924 auto Xor = MIRBuilder.buildXor(Dst: LeftoverTy, Src0: LHS, Src1: RHS).getReg(Idx: 0);
1925 LLT GCDTy = extractGCDType(Parts&: WidenedXors, DstTy: NarrowTy, NarrowTy: LeftoverTy, SrcReg: Xor);
1926 buildLCMMergePieces(DstTy: LeftoverTy, NarrowTy, GCDTy, VRegs&: WidenedXors,
1927 /* PadStrategy = */ TargetOpcode::G_ZEXT);
1928 llvm::append_range(C&: Xors, R&: WidenedXors);
1929 }
1930
1931 // Now, for each part we broke up, we know if they are equal/not equal
1932 // based off the G_XOR. We can OR these all together and compare against
1933 // 0 to get the result.
1934 assert(Xors.size() >= 2 && "Should have gotten at least two Xors?");
1935 auto Or = MIRBuilder.buildOr(Dst: NarrowTy, Src0: Xors[0], Src1: Xors[1]);
1936 for (unsigned I = 2, E = Xors.size(); I < E; ++I)
1937 Or = MIRBuilder.buildOr(Dst: NarrowTy, Src0: Or, Src1: Xors[I]);
1938 MIRBuilder.buildICmp(Pred, Res: Dst, Op0: Or, Op1: Zero);
1939 } else {
1940 Register CmpIn;
1941 for (unsigned I = 0, E = LHSPartRegs.size(); I != E; ++I) {
1942 Register CmpOut;
1943 CmpInst::Predicate PartPred;
1944
1945 if (I == E - 1 && LHSLeftoverRegs.empty()) {
1946 PartPred = Pred;
1947 CmpOut = Dst;
1948 } else {
1949 PartPred = ICmpInst::getUnsignedPredicate(Pred);
1950 CmpOut = MRI.createGenericVirtualRegister(Ty: ResTy);
1951 }
1952
1953 if (!CmpIn) {
1954 MIRBuilder.buildICmp(Pred: PartPred, Res: CmpOut, Op0: LHSPartRegs[I],
1955 Op1: RHSPartRegs[I]);
1956 } else {
1957 auto Cmp = MIRBuilder.buildICmp(Pred: PartPred, Res: ResTy, Op0: LHSPartRegs[I],
1958 Op1: RHSPartRegs[I]);
1959 auto CmpEq = MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_EQ, Res: ResTy,
1960 Op0: LHSPartRegs[I], Op1: RHSPartRegs[I]);
1961 MIRBuilder.buildSelect(Res: CmpOut, Tst: CmpEq, Op0: CmpIn, Op1: Cmp);
1962 }
1963
1964 CmpIn = CmpOut;
1965 }
1966
1967 for (unsigned I = 0, E = LHSLeftoverRegs.size(); I != E; ++I) {
1968 Register CmpOut;
1969 CmpInst::Predicate PartPred;
1970
1971 if (I == E - 1) {
1972 PartPred = Pred;
1973 CmpOut = Dst;
1974 } else {
1975 PartPred = ICmpInst::getUnsignedPredicate(Pred);
1976 CmpOut = MRI.createGenericVirtualRegister(Ty: ResTy);
1977 }
1978
1979 if (!CmpIn) {
1980 MIRBuilder.buildICmp(Pred: PartPred, Res: CmpOut, Op0: LHSLeftoverRegs[I],
1981 Op1: RHSLeftoverRegs[I]);
1982 } else {
1983 auto Cmp = MIRBuilder.buildICmp(Pred: PartPred, Res: ResTy, Op0: LHSLeftoverRegs[I],
1984 Op1: RHSLeftoverRegs[I]);
1985 auto CmpEq =
1986 MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_EQ, Res: ResTy,
1987 Op0: LHSLeftoverRegs[I], Op1: RHSLeftoverRegs[I]);
1988 MIRBuilder.buildSelect(Res: CmpOut, Tst: CmpEq, Op0: CmpIn, Op1: Cmp);
1989 }
1990
1991 CmpIn = CmpOut;
1992 }
1993 }
1994 MI.eraseFromParent();
1995 return Legalized;
1996 }
1997 case TargetOpcode::G_FCMP:
1998 if (TypeIdx != 0)
1999 return UnableToLegalize;
2000
2001 Observer.changingInstr(MI);
2002 narrowScalarDst(MI, NarrowTy, OpIdx: 0, ExtOpcode: TargetOpcode::G_ZEXT);
2003 Observer.changedInstr(MI);
2004 return Legalized;
2005
2006 case TargetOpcode::G_SEXT_INREG: {
2007 if (TypeIdx != 0)
2008 return UnableToLegalize;
2009
2010 int64_t SizeInBits = MI.getOperand(i: 2).getImm();
2011
2012 // So long as the new type has more bits than the bits we're extending we
2013 // don't need to break it apart.
2014 if (NarrowTy.getScalarSizeInBits() > SizeInBits) {
2015 Observer.changingInstr(MI);
2016 // We don't lose any non-extension bits by truncating the src and
2017 // sign-extending the dst.
2018 MachineOperand &MO1 = MI.getOperand(i: 1);
2019 auto TruncMIB = MIRBuilder.buildTrunc(Res: NarrowTy, Op: MO1);
2020 MO1.setReg(TruncMIB.getReg(Idx: 0));
2021
2022 MachineOperand &MO2 = MI.getOperand(i: 0);
2023 Register DstExt = MRI.createGenericVirtualRegister(Ty: NarrowTy);
2024 MIRBuilder.setInsertPt(MBB&: MIRBuilder.getMBB(), II: ++MIRBuilder.getInsertPt());
2025 MIRBuilder.buildSExt(Res: MO2, Op: DstExt);
2026 MO2.setReg(DstExt);
2027 Observer.changedInstr(MI);
2028 return Legalized;
2029 }
2030
2031 // Break it apart. Components below the extension point are unmodified. The
2032 // component containing the extension point becomes a narrower SEXT_INREG.
2033 // Components above it are ashr'd from the component containing the
2034 // extension point.
2035 if (SizeOp0 % NarrowSize != 0)
2036 return UnableToLegalize;
2037 int NumParts = SizeOp0 / NarrowSize;
2038
2039 // List the registers where the destination will be scattered.
2040 SmallVector<Register, 2> DstRegs;
2041 // List the registers where the source will be split.
2042 SmallVector<Register, 2> SrcRegs;
2043
2044 // Create all the temporary registers.
2045 for (int i = 0; i < NumParts; ++i) {
2046 Register SrcReg = MRI.createGenericVirtualRegister(Ty: NarrowTy);
2047
2048 SrcRegs.push_back(Elt: SrcReg);
2049 }
2050
2051 // Explode the big arguments into smaller chunks.
2052 MIRBuilder.buildUnmerge(Res: SrcRegs, Op: MI.getOperand(i: 1));
2053
2054 Register AshrCstReg =
2055 MIRBuilder.buildConstant(Res: NarrowTy, Val: NarrowTy.getScalarSizeInBits() - 1)
2056 .getReg(Idx: 0);
2057 Register FullExtensionReg;
2058 Register PartialExtensionReg;
2059
2060 // Do the operation on each small part.
2061 for (int i = 0; i < NumParts; ++i) {
2062 if ((i + 1) * NarrowTy.getScalarSizeInBits() <= SizeInBits) {
2063 DstRegs.push_back(Elt: SrcRegs[i]);
2064 PartialExtensionReg = DstRegs.back();
2065 } else if (i * NarrowTy.getScalarSizeInBits() >= SizeInBits) {
2066 assert(PartialExtensionReg &&
2067 "Expected to visit partial extension before full");
2068 if (FullExtensionReg) {
2069 DstRegs.push_back(Elt: FullExtensionReg);
2070 continue;
2071 }
2072 DstRegs.push_back(
2073 Elt: MIRBuilder.buildAShr(Dst: NarrowTy, Src0: PartialExtensionReg, Src1: AshrCstReg)
2074 .getReg(Idx: 0));
2075 FullExtensionReg = DstRegs.back();
2076 } else {
2077 DstRegs.push_back(
2078 Elt: MIRBuilder
2079 .buildInstr(
2080 Opc: TargetOpcode::G_SEXT_INREG, DstOps: {NarrowTy},
2081 SrcOps: {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()})
2082 .getReg(Idx: 0));
2083 PartialExtensionReg = DstRegs.back();
2084 }
2085 }
2086
2087 // Gather the destination registers into the final destination.
2088 Register DstReg = MI.getOperand(i: 0).getReg();
2089 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: DstRegs);
2090 MI.eraseFromParent();
2091 return Legalized;
2092 }
2093 case TargetOpcode::G_BSWAP:
2094 case TargetOpcode::G_BITREVERSE: {
2095 if (SizeOp0 % NarrowSize != 0)
2096 return UnableToLegalize;
2097
2098 Observer.changingInstr(MI);
2099 SmallVector<Register, 2> SrcRegs, DstRegs;
2100 unsigned NumParts = SizeOp0 / NarrowSize;
2101 extractParts(Reg: MI.getOperand(i: 1).getReg(), Ty: NarrowTy, NumParts, VRegs&: SrcRegs,
2102 MIRBuilder, MRI);
2103
2104 for (unsigned i = 0; i < NumParts; ++i) {
2105 auto DstPart = MIRBuilder.buildInstr(Opc: MI.getOpcode(), DstOps: {NarrowTy},
2106 SrcOps: {SrcRegs[NumParts - 1 - i]});
2107 DstRegs.push_back(Elt: DstPart.getReg(Idx: 0));
2108 }
2109
2110 MIRBuilder.buildMergeLikeInstr(Res: MI.getOperand(i: 0), Ops: DstRegs);
2111
2112 Observer.changedInstr(MI);
2113 MI.eraseFromParent();
2114 return Legalized;
2115 }
2116 case TargetOpcode::G_PTR_ADD:
2117 case TargetOpcode::G_PTRMASK: {
2118 if (TypeIdx != 1)
2119 return UnableToLegalize;
2120 Observer.changingInstr(MI);
2121 narrowScalarSrc(MI, NarrowTy, OpIdx: 2);
2122 Observer.changedInstr(MI);
2123 return Legalized;
2124 }
2125 case TargetOpcode::G_FPTOUI:
2126 case TargetOpcode::G_FPTOSI:
2127 case TargetOpcode::G_FPTOUI_SAT:
2128 case TargetOpcode::G_FPTOSI_SAT:
2129 return narrowScalarFPTOI(MI, TypeIdx, Ty: NarrowTy);
2130 case TargetOpcode::G_FPEXT:
2131 if (TypeIdx != 0)
2132 return UnableToLegalize;
2133 Observer.changingInstr(MI);
2134 narrowScalarDst(MI, NarrowTy, OpIdx: 0, ExtOpcode: TargetOpcode::G_FPEXT);
2135 Observer.changedInstr(MI);
2136 return Legalized;
2137 case TargetOpcode::G_FLDEXP:
2138 case TargetOpcode::G_STRICT_FLDEXP:
2139 return narrowScalarFLDEXP(MI, TypeIdx, Ty: NarrowTy);
2140 case TargetOpcode::G_VSCALE: {
2141 Register Dst = MI.getOperand(i: 0).getReg();
2142 LLT Ty = MRI.getType(Reg: Dst);
2143
2144 // Assume VSCALE(1) fits into a legal integer
2145 const APInt One(NarrowTy.getSizeInBits(), 1);
2146 auto VScaleBase = MIRBuilder.buildVScale(Res: NarrowTy, MinElts: One);
2147 auto ZExt = MIRBuilder.buildZExt(Res: Ty, Op: VScaleBase);
2148 auto C = MIRBuilder.buildConstant(Res: Ty, Val: *MI.getOperand(i: 1).getCImm());
2149 MIRBuilder.buildMul(Dst, Src0: ZExt, Src1: C);
2150
2151 MI.eraseFromParent();
2152 return Legalized;
2153 }
2154 }
2155}
2156
2157Register LegalizerHelper::coerceToInteger(Register Val) {
2158 LLT Ty = MRI.getType(Reg: Val);
2159 if (Ty.isScalar() && !Ty.isFloat())
2160 return Val;
2161
2162 const DataLayout &DL = MIRBuilder.getDataLayout();
2163 LLT NewTy = LLT::integer(SizeInBits: Ty.getSizeInBits());
2164
2165 if (Ty.isFloat())
2166 return MIRBuilder.buildBitcast(Dst: NewTy, Src: Val).getReg(Idx: 0);
2167
2168 if (Ty.isPointer()) {
2169 if (DL.isNonIntegralAddressSpace(AddrSpace: Ty.getAddressSpace()))
2170 return Register();
2171 return MIRBuilder.buildPtrToInt(Dst: NewTy, Src: Val).getReg(Idx: 0);
2172 }
2173
2174 Register NewVal = Val;
2175
2176 assert(Ty.isVector());
2177 if (Ty.isPointerVector())
2178 NewVal = MIRBuilder.buildPtrToInt(Dst: NewTy, Src: NewVal).getReg(Idx: 0);
2179 return MIRBuilder.buildBitcast(Dst: NewTy, Src: NewVal).getReg(Idx: 0);
2180}
2181
2182void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
2183 unsigned OpIdx, unsigned ExtOpcode) {
2184 MachineOperand &MO = MI.getOperand(i: OpIdx);
2185 auto ExtB = MIRBuilder.buildInstr(Opc: ExtOpcode, DstOps: {WideTy}, SrcOps: {MO});
2186 MO.setReg(ExtB.getReg(Idx: 0));
2187}
2188
2189void LegalizerHelper::widenScalarSrcUsingFPExt(MachineInstr &MI, LLT WideTy,
2190 unsigned OpIdx) {
2191 MachineOperand &MO = MI.getOperand(i: OpIdx);
2192 auto ExtB = MIRBuilder.buildInstr(Opc: TargetOpcode::G_FPEXT, DstOps: {WideTy}, SrcOps: {MO},
2193 Flags: MI.getFlags());
2194 MO.setReg(ExtB.getReg(Idx: 0));
2195}
2196
2197void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
2198 unsigned OpIdx) {
2199 MachineOperand &MO = MI.getOperand(i: OpIdx);
2200 auto ExtB = MIRBuilder.buildTrunc(Res: NarrowTy, Op: MO);
2201 MO.setReg(ExtB.getReg(Idx: 0));
2202}
2203
2204void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
2205 unsigned OpIdx, unsigned TruncOpcode) {
2206 MachineOperand &MO = MI.getOperand(i: OpIdx);
2207 Register DstExt = MRI.createGenericVirtualRegister(Ty: WideTy);
2208 MIRBuilder.setInsertPt(MBB&: MIRBuilder.getMBB(), II: ++MIRBuilder.getInsertPt());
2209 MIRBuilder.buildInstr(Opc: TruncOpcode, DstOps: {MO}, SrcOps: {DstExt});
2210 MO.setReg(DstExt);
2211}
2212
2213void LegalizerHelper::widenScalarDstUsingFPTrunc(MachineInstr &MI, LLT WideTy,
2214 unsigned OpIdx) {
2215 MachineOperand &MO = MI.getOperand(i: OpIdx);
2216 Register DstExt = MRI.createGenericVirtualRegister(Ty: WideTy);
2217 MIRBuilder.setInsertPt(MBB&: MIRBuilder.getMBB(), II: ++MIRBuilder.getInsertPt());
2218 MIRBuilder.buildInstr(Opc: TargetOpcode::G_FPTRUNC, DstOps: {MO}, SrcOps: {DstExt}, Flags: MI.getFlags());
2219 MO.setReg(DstExt);
2220}
2221
2222void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
2223 unsigned OpIdx, unsigned ExtOpcode) {
2224 MachineOperand &MO = MI.getOperand(i: OpIdx);
2225 Register DstTrunc = MRI.createGenericVirtualRegister(Ty: NarrowTy);
2226 MIRBuilder.setInsertPt(MBB&: MIRBuilder.getMBB(), II: ++MIRBuilder.getInsertPt());
2227 MIRBuilder.buildInstr(Opc: ExtOpcode, DstOps: {MO}, SrcOps: {DstTrunc});
2228 MO.setReg(DstTrunc);
2229}
2230
2231void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
2232 unsigned OpIdx) {
2233 MachineOperand &MO = MI.getOperand(i: OpIdx);
2234 MIRBuilder.setInsertPt(MBB&: MIRBuilder.getMBB(), II: ++MIRBuilder.getInsertPt());
2235 Register Dst = MO.getReg();
2236 Register DstExt = MRI.createGenericVirtualRegister(Ty: WideTy);
2237 MO.setReg(DstExt);
2238 MIRBuilder.buildDeleteTrailingVectorElements(Res: Dst, Op0: DstExt);
2239}
2240
2241void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
2242 unsigned OpIdx) {
2243 MachineOperand &MO = MI.getOperand(i: OpIdx);
2244 MO.setReg(MIRBuilder.buildPadVectorWithUndefElements(Res: MoreTy, Op0: MO).getReg(Idx: 0));
2245}
2246
2247void LegalizerHelper::bitcastSrc(MachineInstr &MI, LLT CastTy, unsigned OpIdx) {
2248 MachineOperand &Op = MI.getOperand(i: OpIdx);
2249 Op.setReg(MIRBuilder.buildBitcast(Dst: CastTy, Src: Op).getReg(Idx: 0));
2250}
2251
2252void LegalizerHelper::bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx) {
2253 MachineOperand &MO = MI.getOperand(i: OpIdx);
2254 Register CastDst = MRI.createGenericVirtualRegister(Ty: CastTy);
2255 MIRBuilder.setInsertPt(MBB&: MIRBuilder.getMBB(), II: ++MIRBuilder.getInsertPt());
2256 MIRBuilder.buildBitcast(Dst: MO, Src: CastDst);
2257 MO.setReg(CastDst);
2258}
2259
2260LegalizerHelper::LegalizeResult
2261LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
2262 LLT WideTy) {
2263 if (TypeIdx != 1)
2264 return UnableToLegalize;
2265
2266 auto [DstReg, DstTy, Src1Reg, Src1Ty] = MI.getFirst2RegLLTs();
2267 if (DstTy.isVector())
2268 return UnableToLegalize;
2269
2270 LLT SrcTy = MRI.getType(Reg: Src1Reg);
2271 const int DstSize = DstTy.getSizeInBits();
2272 const int SrcSize = SrcTy.getSizeInBits();
2273 const int WideSize = WideTy.getSizeInBits();
2274 const int NumMerge = (DstSize + WideSize - 1) / WideSize;
2275
2276 unsigned NumOps = MI.getNumOperands();
2277 unsigned NumSrc = MI.getNumOperands() - 1;
2278 unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
2279
2280 if (WideSize >= DstSize) {
2281 // Directly pack the bits in the target type.
2282 Register ResultReg = MIRBuilder.buildZExt(Res: WideTy, Op: Src1Reg).getReg(Idx: 0);
2283
2284 for (unsigned I = 2; I != NumOps; ++I) {
2285 const unsigned Offset = (I - 1) * PartSize;
2286
2287 Register SrcReg = MI.getOperand(i: I).getReg();
2288 assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
2289
2290 auto ZextInput = MIRBuilder.buildZExt(Res: WideTy, Op: SrcReg);
2291
2292 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg :
2293 MRI.createGenericVirtualRegister(Ty: WideTy);
2294
2295 auto ShiftAmt = MIRBuilder.buildConstant(Res: WideTy, Val: Offset);
2296 auto Shl = MIRBuilder.buildShl(Dst: WideTy, Src0: ZextInput, Src1: ShiftAmt);
2297 MIRBuilder.buildOr(Dst: NextResult, Src0: ResultReg, Src1: Shl);
2298 ResultReg = NextResult;
2299 }
2300
2301 if (WideSize > DstSize)
2302 MIRBuilder.buildTrunc(Res: DstReg, Op: ResultReg);
2303 else if (DstTy.isPointer())
2304 MIRBuilder.buildIntToPtr(Dst: DstReg, Src: ResultReg);
2305 else if (DstTy != WideTy)
2306 MIRBuilder.buildBitcast(Dst: DstReg, Src: ResultReg);
2307
2308 MI.eraseFromParent();
2309 return Legalized;
2310 }
2311
2312 // Unmerge the original values to the GCD type, and recombine to the next
2313 // multiple greater than the original type.
2314 //
2315 // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6
2316 // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0
2317 // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1
2318 // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2
2319 // %10:_(s6) = G_MERGE_VALUES %4, %5, %6
2320 // %11:_(s6) = G_MERGE_VALUES %7, %8, %9
2321 // %12:_(s12) = G_MERGE_VALUES %10, %11
2322 //
2323 // Padding with undef if necessary:
2324 //
2325 // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6
2326 // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0
2327 // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1
2328 // %7:_(s2) = G_IMPLICIT_DEF
2329 // %8:_(s6) = G_MERGE_VALUES %3, %4, %5
2330 // %9:_(s6) = G_MERGE_VALUES %6, %7, %7
2331 // %10:_(s12) = G_MERGE_VALUES %8, %9
2332
2333 const int GCD = std::gcd(m: SrcSize, n: WideSize);
2334 LLT GCDTy = WideTy.changeElementSize(NewEltSize: GCD);
2335
2336 SmallVector<Register, 8> NewMergeRegs;
2337 SmallVector<Register, 8> Unmerges;
2338 LLT WideDstTy = WideTy.changeElementSize(NewEltSize: NumMerge * WideSize);
2339
2340 // Decompose the original operands if they don't evenly divide.
2341 for (const MachineOperand &MO : llvm::drop_begin(RangeOrContainer: MI.operands())) {
2342 Register SrcReg = MO.getReg();
2343 if (GCD == SrcSize) {
2344 Unmerges.push_back(Elt: SrcReg);
2345 } else {
2346 auto Unmerge = MIRBuilder.buildUnmerge(Res: GCDTy, Op: SrcReg);
2347 for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J)
2348 Unmerges.push_back(Elt: Unmerge.getReg(Idx: J));
2349 }
2350 }
2351
2352 // Pad with undef to the next size that is a multiple of the requested size.
2353 if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) {
2354 Register UndefReg = MIRBuilder.buildUndef(Res: GCDTy).getReg(Idx: 0);
2355 for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I)
2356 Unmerges.push_back(Elt: UndefReg);
2357 }
2358
2359 const int PartsPerGCD = WideSize / GCD;
2360
2361 // Build merges of each piece.
2362 ArrayRef<Register> Slicer(Unmerges);
2363 for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(N: PartsPerGCD)) {
2364 auto Merge =
2365 MIRBuilder.buildMergeLikeInstr(Res: WideTy, Ops: Slicer.take_front(N: PartsPerGCD));
2366 NewMergeRegs.push_back(Elt: Merge.getReg(Idx: 0));
2367 }
2368
2369 // A truncate may be necessary if the requested type doesn't evenly divide the
2370 // original result type.
2371 if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) {
2372 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: NewMergeRegs);
2373 } else {
2374 auto FinalMerge = MIRBuilder.buildMergeLikeInstr(Res: WideDstTy, Ops: NewMergeRegs);
2375 MIRBuilder.buildTrunc(Res: DstReg, Op: FinalMerge.getReg(Idx: 0));
2376 }
2377
2378 MI.eraseFromParent();
2379 return Legalized;
2380}
2381
2382LegalizerHelper::LegalizeResult
2383LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
2384 LLT WideTy) {
2385 if (TypeIdx != 0)
2386 return UnableToLegalize;
2387
2388 int NumDst = MI.getNumOperands() - 1;
2389 Register SrcReg = MI.getOperand(i: NumDst).getReg();
2390 LLT SrcTy = MRI.getType(Reg: SrcReg);
2391 if (SrcTy.isVector())
2392 return UnableToLegalize;
2393
2394 Register Dst0Reg = MI.getOperand(i: 0).getReg();
2395 LLT DstTy = MRI.getType(Reg: Dst0Reg);
2396 if (!DstTy.isScalar())
2397 return UnableToLegalize;
2398
2399 if (WideTy.getSizeInBits() >= SrcTy.getSizeInBits()) {
2400 if (SrcTy.isPointer()) {
2401 const DataLayout &DL = MIRBuilder.getDataLayout();
2402 if (DL.isNonIntegralAddressSpace(AddrSpace: SrcTy.getAddressSpace())) {
2403 LLVM_DEBUG(
2404 dbgs() << "Not casting non-integral address space integer\n");
2405 return UnableToLegalize;
2406 }
2407
2408 SrcTy = LLT::scalar(SizeInBits: SrcTy.getSizeInBits());
2409 SrcReg = MIRBuilder.buildPtrToInt(Dst: SrcTy, Src: SrcReg).getReg(Idx: 0);
2410 }
2411
2412 // Widen SrcTy to WideTy. This does not affect the result, but since the
2413 // user requested this size, it is probably better handled than SrcTy and
2414 // should reduce the total number of legalization artifacts.
2415 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
2416 SrcTy = WideTy;
2417 SrcReg = MIRBuilder.buildAnyExt(Res: WideTy, Op: SrcReg).getReg(Idx: 0);
2418 }
2419
2420 // Theres no unmerge type to target. Directly extract the bits from the
2421 // source type
2422 unsigned DstSize = DstTy.getSizeInBits();
2423
2424 if (SrcTy.isFloat()) {
2425 SrcReg = coerceToInteger(Val: SrcReg);
2426 SrcTy = MRI.getType(Reg: SrcReg);
2427 }
2428
2429 MIRBuilder.buildTrunc(Res: Dst0Reg, Op: SrcReg);
2430 for (int I = 1; I != NumDst; ++I) {
2431 auto ShiftAmt = MIRBuilder.buildConstant(Res: SrcTy, Val: DstSize * I);
2432 auto Shr = MIRBuilder.buildLShr(Dst: SrcTy, Src0: SrcReg, Src1: ShiftAmt);
2433 MIRBuilder.buildTrunc(Res: MI.getOperand(i: I), Op: Shr);
2434 }
2435
2436 MI.eraseFromParent();
2437 return Legalized;
2438 }
2439
2440 // Extend the source to a wider type.
2441 LLT LCMTy = getLCMType(OrigTy: SrcTy, TargetTy: WideTy);
2442
2443 Register WideSrc = SrcReg;
2444 if (LCMTy.getSizeInBits() != SrcTy.getSizeInBits()) {
2445 // TODO: If this is an integral address space, cast to integer and anyext.
2446 if (SrcTy.isPointer()) {
2447 LLVM_DEBUG(dbgs() << "Widening pointer source types not implemented\n");
2448 return UnableToLegalize;
2449 }
2450
2451 WideSrc = MIRBuilder.buildAnyExt(Res: LCMTy, Op: WideSrc).getReg(Idx: 0);
2452 }
2453
2454 auto Unmerge = MIRBuilder.buildUnmerge(Res: WideTy, Op: WideSrc);
2455
2456 // Create a sequence of unmerges and merges to the original results. Since we
2457 // may have widened the source, we will need to pad the results with dead defs
2458 // to cover the source register.
2459 // e.g. widen s48 to s64:
2460 // %1:_(s48), %2:_(s48) = G_UNMERGE_VALUES %0:_(s96)
2461 //
2462 // =>
2463 // %4:_(s192) = G_ANYEXT %0:_(s96)
2464 // %5:_(s64), %6, %7 = G_UNMERGE_VALUES %4 ; Requested unmerge
2465 // ; unpack to GCD type, with extra dead defs
2466 // %8:_(s16), %9, %10, %11 = G_UNMERGE_VALUES %5:_(s64)
2467 // %12:_(s16), %13, dead %14, dead %15 = G_UNMERGE_VALUES %6:_(s64)
2468 // dead %16:_(s16), dead %17, dead %18, dead %18 = G_UNMERGE_VALUES %7:_(s64)
2469 // %1:_(s48) = G_MERGE_VALUES %8:_(s16), %9, %10 ; Remerge to destination
2470 // %2:_(s48) = G_MERGE_VALUES %11:_(s16), %12, %13 ; Remerge to destination
2471 const LLT GCDTy = getGCDType(OrigTy: WideTy, TargetTy: DstTy);
2472 const int NumUnmerge = Unmerge->getNumOperands() - 1;
2473 const int PartsPerRemerge = DstTy.getSizeInBits() / GCDTy.getSizeInBits();
2474
2475 // Directly unmerge to the destination without going through a GCD type
2476 // if possible
2477 if (PartsPerRemerge == 1) {
2478 const int PartsPerUnmerge = WideTy.getSizeInBits() / DstTy.getSizeInBits();
2479
2480 for (int I = 0; I != NumUnmerge; ++I) {
2481 auto MIB = MIRBuilder.buildInstr(Opcode: TargetOpcode::G_UNMERGE_VALUES);
2482
2483 for (int J = 0; J != PartsPerUnmerge; ++J) {
2484 int Idx = I * PartsPerUnmerge + J;
2485 if (Idx < NumDst)
2486 MIB.addDef(RegNo: MI.getOperand(i: Idx).getReg());
2487 else {
2488 // Create dead def for excess components.
2489 MIB.addDef(RegNo: MRI.createGenericVirtualRegister(Ty: DstTy));
2490 }
2491 }
2492
2493 MIB.addUse(RegNo: Unmerge.getReg(Idx: I));
2494 }
2495 } else {
2496 SmallVector<Register, 16> Parts;
2497 for (int J = 0; J != NumUnmerge; ++J)
2498 extractGCDType(Parts, GCDTy, SrcReg: Unmerge.getReg(Idx: J));
2499
2500 SmallVector<Register, 8> RemergeParts;
2501 for (int I = 0; I != NumDst; ++I) {
2502 for (int J = 0; J < PartsPerRemerge; ++J) {
2503 const int Idx = I * PartsPerRemerge + J;
2504 RemergeParts.emplace_back(Args&: Parts[Idx]);
2505 }
2506
2507 MIRBuilder.buildMergeLikeInstr(Res: MI.getOperand(i: I).getReg(), Ops: RemergeParts);
2508 RemergeParts.clear();
2509 }
2510 }
2511
2512 MI.eraseFromParent();
2513 return Legalized;
2514}
2515
2516LegalizerHelper::LegalizeResult
2517LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
2518 LLT WideTy) {
2519 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
2520 unsigned Offset = MI.getOperand(i: 2).getImm();
2521
2522 if (TypeIdx == 0) {
2523 if (SrcTy.isVector() || DstTy.isVector())
2524 return UnableToLegalize;
2525
2526 SrcOp Src(SrcReg);
2527 if (SrcTy.isPointer()) {
2528 // Extracts from pointers can be handled only if they are really just
2529 // simple integers.
2530 const DataLayout &DL = MIRBuilder.getDataLayout();
2531 if (DL.isNonIntegralAddressSpace(AddrSpace: SrcTy.getAddressSpace()))
2532 return UnableToLegalize;
2533
2534 LLT SrcAsIntTy = LLT::scalar(SizeInBits: SrcTy.getSizeInBits());
2535 Src = MIRBuilder.buildPtrToInt(Dst: SrcAsIntTy, Src);
2536 SrcTy = SrcAsIntTy;
2537 }
2538
2539 if (DstTy.isPointer())
2540 return UnableToLegalize;
2541
2542 if (Offset == 0) {
2543 // Avoid a shift in the degenerate case.
2544 MIRBuilder.buildTrunc(Res: DstReg,
2545 Op: MIRBuilder.buildAnyExtOrTrunc(Res: WideTy, Op: Src));
2546 MI.eraseFromParent();
2547 return Legalized;
2548 }
2549
2550 // Do a shift in the source type.
2551 LLT ShiftTy = SrcTy;
2552 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
2553 Src = MIRBuilder.buildAnyExt(Res: WideTy, Op: Src);
2554 ShiftTy = WideTy;
2555 }
2556
2557 auto LShr = MIRBuilder.buildLShr(
2558 Dst: ShiftTy, Src0: Src, Src1: MIRBuilder.buildConstant(Res: ShiftTy, Val: Offset));
2559 MIRBuilder.buildTrunc(Res: DstReg, Op: LShr);
2560 MI.eraseFromParent();
2561 return Legalized;
2562 }
2563
2564 if (SrcTy.isScalar()) {
2565 Observer.changingInstr(MI);
2566 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ANYEXT);
2567 Observer.changedInstr(MI);
2568 return Legalized;
2569 }
2570
2571 if (!SrcTy.isVector())
2572 return UnableToLegalize;
2573
2574 if (DstTy != SrcTy.getElementType())
2575 return UnableToLegalize;
2576
2577 if (Offset % SrcTy.getScalarSizeInBits() != 0)
2578 return UnableToLegalize;
2579
2580 Observer.changingInstr(MI);
2581 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ANYEXT);
2582
2583 MI.getOperand(i: 2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
2584 Offset);
2585 widenScalarDst(MI, WideTy: WideTy.getScalarType(), OpIdx: 0);
2586 Observer.changedInstr(MI);
2587 return Legalized;
2588}
2589
2590LegalizerHelper::LegalizeResult
2591LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
2592 LLT WideTy) {
2593 if (TypeIdx != 0 || WideTy.isVector())
2594 return UnableToLegalize;
2595 Observer.changingInstr(MI);
2596 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ANYEXT);
2597 widenScalarDst(MI, WideTy);
2598 Observer.changedInstr(MI);
2599 return Legalized;
2600}
2601
2602LegalizerHelper::LegalizeResult
2603LegalizerHelper::widenScalarAddSubOverflow(MachineInstr &MI, unsigned TypeIdx,
2604 LLT WideTy) {
2605 unsigned Opcode;
2606 unsigned ExtOpcode;
2607 std::optional<Register> CarryIn;
2608 switch (MI.getOpcode()) {
2609 default:
2610 llvm_unreachable("Unexpected opcode!");
2611 case TargetOpcode::G_SADDO:
2612 Opcode = TargetOpcode::G_ADD;
2613 ExtOpcode = TargetOpcode::G_SEXT;
2614 break;
2615 case TargetOpcode::G_SSUBO:
2616 Opcode = TargetOpcode::G_SUB;
2617 ExtOpcode = TargetOpcode::G_SEXT;
2618 break;
2619 case TargetOpcode::G_UADDO:
2620 Opcode = TargetOpcode::G_ADD;
2621 ExtOpcode = TargetOpcode::G_ZEXT;
2622 break;
2623 case TargetOpcode::G_USUBO:
2624 Opcode = TargetOpcode::G_SUB;
2625 ExtOpcode = TargetOpcode::G_ZEXT;
2626 break;
2627 case TargetOpcode::G_SADDE:
2628 Opcode = TargetOpcode::G_UADDE;
2629 ExtOpcode = TargetOpcode::G_SEXT;
2630 CarryIn = MI.getOperand(i: 4).getReg();
2631 break;
2632 case TargetOpcode::G_SSUBE:
2633 Opcode = TargetOpcode::G_USUBE;
2634 ExtOpcode = TargetOpcode::G_SEXT;
2635 CarryIn = MI.getOperand(i: 4).getReg();
2636 break;
2637 case TargetOpcode::G_UADDE:
2638 Opcode = TargetOpcode::G_UADDE;
2639 ExtOpcode = TargetOpcode::G_ZEXT;
2640 CarryIn = MI.getOperand(i: 4).getReg();
2641 break;
2642 case TargetOpcode::G_USUBE:
2643 Opcode = TargetOpcode::G_USUBE;
2644 ExtOpcode = TargetOpcode::G_ZEXT;
2645 CarryIn = MI.getOperand(i: 4).getReg();
2646 break;
2647 }
2648
2649 if (TypeIdx == 1) {
2650 unsigned BoolExtOp = MIRBuilder.getBoolExtOp(IsVec: WideTy.isVector(), IsFP: false);
2651
2652 Observer.changingInstr(MI);
2653 if (CarryIn)
2654 widenScalarSrc(MI, WideTy, OpIdx: 4, ExtOpcode: BoolExtOp);
2655 widenScalarDst(MI, WideTy, OpIdx: 1);
2656
2657 Observer.changedInstr(MI);
2658 return Legalized;
2659 }
2660
2661 auto LHSExt = MIRBuilder.buildInstr(Opc: ExtOpcode, DstOps: {WideTy}, SrcOps: {MI.getOperand(i: 2)});
2662 auto RHSExt = MIRBuilder.buildInstr(Opc: ExtOpcode, DstOps: {WideTy}, SrcOps: {MI.getOperand(i: 3)});
2663 // Do the arithmetic in the larger type.
2664 Register NewOp;
2665 if (CarryIn) {
2666 LLT CarryOutTy = MRI.getType(Reg: MI.getOperand(i: 1).getReg());
2667 NewOp = MIRBuilder
2668 .buildInstr(Opc: Opcode, DstOps: {WideTy, CarryOutTy},
2669 SrcOps: {LHSExt, RHSExt, *CarryIn})
2670 .getReg(Idx: 0);
2671 } else {
2672 NewOp = MIRBuilder.buildInstr(Opc: Opcode, DstOps: {WideTy}, SrcOps: {LHSExt, RHSExt}).getReg(Idx: 0);
2673 }
2674 LLT OrigTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
2675 auto TruncOp = MIRBuilder.buildTrunc(Res: OrigTy, Op: NewOp);
2676 auto ExtOp = MIRBuilder.buildInstr(Opc: ExtOpcode, DstOps: {WideTy}, SrcOps: {TruncOp});
2677 // There is no overflow if the ExtOp is the same as NewOp.
2678 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_NE, Res: MI.getOperand(i: 1), Op0: NewOp, Op1: ExtOp);
2679 // Now trunc the NewOp to the original result.
2680 MIRBuilder.buildTrunc(Res: MI.getOperand(i: 0), Op: NewOp);
2681 MI.eraseFromParent();
2682 return Legalized;
2683}
2684
2685LegalizerHelper::LegalizeResult
2686LegalizerHelper::widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx,
2687 LLT WideTy) {
2688 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SADDSAT ||
2689 MI.getOpcode() == TargetOpcode::G_SSUBSAT ||
2690 MI.getOpcode() == TargetOpcode::G_SSHLSAT;
2691 bool IsShift = MI.getOpcode() == TargetOpcode::G_SSHLSAT ||
2692 MI.getOpcode() == TargetOpcode::G_USHLSAT;
2693 // We can convert this to:
2694 // 1. Any extend iN to iM
2695 // 2. SHL by M-N
2696 // 3. [US][ADD|SUB|SHL]SAT
2697 // 4. L/ASHR by M-N
2698 //
2699 // It may be more efficient to lower this to a min and a max operation in
2700 // the higher precision arithmetic if the promoted operation isn't legal,
2701 // but this decision is up to the target's lowering request.
2702 Register DstReg = MI.getOperand(i: 0).getReg();
2703
2704 unsigned NewBits = WideTy.getScalarSizeInBits();
2705 unsigned SHLAmount = NewBits - MRI.getType(Reg: DstReg).getScalarSizeInBits();
2706
2707 // Shifts must zero-extend the RHS to preserve the unsigned quantity, and
2708 // must not left shift the RHS to preserve the shift amount.
2709 auto LHS = MIRBuilder.buildAnyExt(Res: WideTy, Op: MI.getOperand(i: 1));
2710 auto RHS = IsShift ? MIRBuilder.buildZExt(Res: WideTy, Op: MI.getOperand(i: 2))
2711 : MIRBuilder.buildAnyExt(Res: WideTy, Op: MI.getOperand(i: 2));
2712 auto ShiftK = MIRBuilder.buildConstant(Res: WideTy, Val: SHLAmount);
2713 auto ShiftL = MIRBuilder.buildShl(Dst: WideTy, Src0: LHS, Src1: ShiftK);
2714 auto ShiftR = IsShift ? RHS : MIRBuilder.buildShl(Dst: WideTy, Src0: RHS, Src1: ShiftK);
2715
2716 auto WideInst = MIRBuilder.buildInstr(Opc: MI.getOpcode(), DstOps: {WideTy},
2717 SrcOps: {ShiftL, ShiftR}, Flags: MI.getFlags());
2718
2719 // Use a shift that will preserve the number of sign bits when the trunc is
2720 // folded away.
2721 auto Result = IsSigned ? MIRBuilder.buildAShr(Dst: WideTy, Src0: WideInst, Src1: ShiftK)
2722 : MIRBuilder.buildLShr(Dst: WideTy, Src0: WideInst, Src1: ShiftK);
2723
2724 MIRBuilder.buildTrunc(Res: DstReg, Op: Result);
2725 MI.eraseFromParent();
2726 return Legalized;
2727}
2728
2729LegalizerHelper::LegalizeResult
2730LegalizerHelper::widenScalarMulo(MachineInstr &MI, unsigned TypeIdx,
2731 LLT WideTy) {
2732 if (TypeIdx == 1) {
2733 Observer.changingInstr(MI);
2734 widenScalarDst(MI, WideTy, OpIdx: 1);
2735 Observer.changedInstr(MI);
2736 return Legalized;
2737 }
2738
2739 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULO;
2740 auto [Result, OriginalOverflow, LHS, RHS] = MI.getFirst4Regs();
2741 LLT SrcTy = MRI.getType(Reg: LHS);
2742 LLT OverflowTy = MRI.getType(Reg: OriginalOverflow);
2743 unsigned SrcBitWidth = SrcTy.getScalarSizeInBits();
2744
2745 // To determine if the result overflowed in the larger type, we extend the
2746 // input to the larger type, do the multiply (checking if it overflows),
2747 // then also check the high bits of the result to see if overflow happened
2748 // there.
2749 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
2750 auto LeftOperand = MIRBuilder.buildInstr(Opc: ExtOp, DstOps: {WideTy}, SrcOps: {LHS});
2751 auto RightOperand = MIRBuilder.buildInstr(Opc: ExtOp, DstOps: {WideTy}, SrcOps: {RHS});
2752
2753 // Multiplication cannot overflow if the WideTy is >= 2 * original width,
2754 // so we don't need to check the overflow result of larger type Mulo.
2755 bool WideMulCanOverflow = WideTy.getScalarSizeInBits() < 2 * SrcBitWidth;
2756
2757 unsigned MulOpc =
2758 WideMulCanOverflow ? MI.getOpcode() : (unsigned)TargetOpcode::G_MUL;
2759
2760 MachineInstrBuilder Mulo;
2761 if (WideMulCanOverflow)
2762 Mulo = MIRBuilder.buildInstr(Opc: MulOpc, DstOps: {WideTy, OverflowTy},
2763 SrcOps: {LeftOperand, RightOperand});
2764 else
2765 Mulo = MIRBuilder.buildInstr(Opc: MulOpc, DstOps: {WideTy}, SrcOps: {LeftOperand, RightOperand});
2766
2767 auto Mul = Mulo->getOperand(i: 0);
2768 MIRBuilder.buildTrunc(Res: Result, Op: Mul);
2769
2770 MachineInstrBuilder ExtResult;
2771 // Overflow occurred if it occurred in the larger type, or if the high part
2772 // of the result does not zero/sign-extend the low part. Check this second
2773 // possibility first.
2774 if (IsSigned) {
2775 // For signed, overflow occurred when the high part does not sign-extend
2776 // the low part.
2777 ExtResult = MIRBuilder.buildSExtInReg(Res: WideTy, Op: Mul, ImmOp: SrcBitWidth);
2778 } else {
2779 // Unsigned overflow occurred when the high part does not zero-extend the
2780 // low part.
2781 ExtResult = MIRBuilder.buildZExtInReg(Res: WideTy, Op: Mul, ImmOp: SrcBitWidth);
2782 }
2783
2784 if (WideMulCanOverflow) {
2785 auto Overflow =
2786 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_NE, Res: OverflowTy, Op0: Mul, Op1: ExtResult);
2787 // Finally check if the multiplication in the larger type itself overflowed.
2788 MIRBuilder.buildOr(Dst: OriginalOverflow, Src0: Mulo->getOperand(i: 1), Src1: Overflow);
2789 } else {
2790 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_NE, Res: OriginalOverflow, Op0: Mul, Op1: ExtResult);
2791 }
2792 MI.eraseFromParent();
2793 return Legalized;
2794}
2795
2796LegalizerHelper::LegalizeResult
2797LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
2798 unsigned Opcode = MI.getOpcode();
2799 switch (Opcode) {
2800 default:
2801 return UnableToLegalize;
2802 case TargetOpcode::G_ATOMICRMW_XCHG:
2803 case TargetOpcode::G_ATOMICRMW_ADD:
2804 case TargetOpcode::G_ATOMICRMW_SUB:
2805 case TargetOpcode::G_ATOMICRMW_AND:
2806 case TargetOpcode::G_ATOMICRMW_OR:
2807 case TargetOpcode::G_ATOMICRMW_XOR:
2808 case TargetOpcode::G_ATOMICRMW_MIN:
2809 case TargetOpcode::G_ATOMICRMW_MAX:
2810 case TargetOpcode::G_ATOMICRMW_UMIN:
2811 case TargetOpcode::G_ATOMICRMW_UMAX:
2812 assert(TypeIdx == 0 && "atomicrmw with second scalar type");
2813 Observer.changingInstr(MI);
2814 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_ANYEXT);
2815 widenScalarDst(MI, WideTy, OpIdx: 0);
2816 Observer.changedInstr(MI);
2817 return Legalized;
2818 case TargetOpcode::G_ATOMIC_CMPXCHG:
2819 assert(TypeIdx == 0 && "G_ATOMIC_CMPXCHG with second scalar type");
2820 Observer.changingInstr(MI);
2821 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_ANYEXT);
2822 widenScalarSrc(MI, WideTy, OpIdx: 3, ExtOpcode: TargetOpcode::G_ANYEXT);
2823 widenScalarDst(MI, WideTy, OpIdx: 0);
2824 Observer.changedInstr(MI);
2825 return Legalized;
2826 case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS:
2827 if (TypeIdx == 0) {
2828 Observer.changingInstr(MI);
2829 widenScalarSrc(MI, WideTy, OpIdx: 3, ExtOpcode: TargetOpcode::G_ANYEXT);
2830 widenScalarSrc(MI, WideTy, OpIdx: 4, ExtOpcode: TargetOpcode::G_ANYEXT);
2831 widenScalarDst(MI, WideTy, OpIdx: 0);
2832 Observer.changedInstr(MI);
2833 return Legalized;
2834 }
2835 assert(TypeIdx == 1 &&
2836 "G_ATOMIC_CMPXCHG_WITH_SUCCESS with third scalar type");
2837 Observer.changingInstr(MI);
2838 widenScalarDst(MI, WideTy, OpIdx: 1);
2839 Observer.changedInstr(MI);
2840 return Legalized;
2841 case TargetOpcode::G_EXTRACT:
2842 return widenScalarExtract(MI, TypeIdx, WideTy);
2843 case TargetOpcode::G_INSERT:
2844 return widenScalarInsert(MI, TypeIdx, WideTy);
2845 case TargetOpcode::G_MERGE_VALUES:
2846 return widenScalarMergeValues(MI, TypeIdx, WideTy);
2847 case TargetOpcode::G_UNMERGE_VALUES:
2848 return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
2849 case TargetOpcode::G_SADDO:
2850 case TargetOpcode::G_SSUBO:
2851 case TargetOpcode::G_UADDO:
2852 case TargetOpcode::G_USUBO:
2853 case TargetOpcode::G_SADDE:
2854 case TargetOpcode::G_SSUBE:
2855 case TargetOpcode::G_UADDE:
2856 case TargetOpcode::G_USUBE:
2857 return widenScalarAddSubOverflow(MI, TypeIdx, WideTy);
2858 case TargetOpcode::G_UMULO:
2859 case TargetOpcode::G_SMULO:
2860 return widenScalarMulo(MI, TypeIdx, WideTy);
2861 case TargetOpcode::G_SADDSAT:
2862 case TargetOpcode::G_SSUBSAT:
2863 case TargetOpcode::G_SSHLSAT:
2864 case TargetOpcode::G_UADDSAT:
2865 case TargetOpcode::G_USUBSAT:
2866 case TargetOpcode::G_USHLSAT:
2867 return widenScalarAddSubShlSat(MI, TypeIdx, WideTy);
2868 case TargetOpcode::G_CTTZ:
2869 case TargetOpcode::G_CTTZ_ZERO_POISON:
2870 case TargetOpcode::G_CTLZ:
2871 case TargetOpcode::G_CTLZ_ZERO_POISON:
2872 case TargetOpcode::G_CTLS:
2873 case TargetOpcode::G_CTPOP: {
2874 if (TypeIdx == 0) {
2875 Observer.changingInstr(MI);
2876 widenScalarDst(MI, WideTy, OpIdx: 0);
2877 Observer.changedInstr(MI);
2878 return Legalized;
2879 }
2880
2881 Register SrcReg = MI.getOperand(i: 1).getReg();
2882
2883 // First extend the input.
2884 unsigned ExtOpc;
2885 switch (Opcode) {
2886 case TargetOpcode::G_CTTZ:
2887 case TargetOpcode::G_CTTZ_ZERO_POISON:
2888 case TargetOpcode::G_CTLZ_ZERO_POISON: // poison shifted out below
2889 ExtOpc = TargetOpcode::G_ANYEXT;
2890 break;
2891 case TargetOpcode::G_CTLS:
2892 ExtOpc = TargetOpcode::G_SEXT;
2893 break;
2894 default:
2895 ExtOpc = TargetOpcode::G_ZEXT;
2896 }
2897
2898 auto MIBSrc = MIRBuilder.buildInstr(Opc: ExtOpc, DstOps: {WideTy}, SrcOps: {SrcReg});
2899 LLT CurTy = MRI.getType(Reg: SrcReg);
2900 unsigned NewOpc = Opcode;
2901 if (NewOpc == TargetOpcode::G_CTTZ) {
2902 // The count is the same in the larger type except if the original
2903 // value was zero. This can be handled by setting the bit just off
2904 // the top of the original type.
2905 auto TopBit = APInt::getOneBitSet(numBits: WideTy.getScalarSizeInBits(),
2906 BitNo: CurTy.getScalarSizeInBits());
2907 MIBSrc = MIRBuilder.buildOr(
2908 Dst: WideTy, Src0: MIBSrc, Src1: MIRBuilder.buildConstant(Res: WideTy, Val: TopBit));
2909 // Now we know the operand is non-zero, use the more relaxed opcode.
2910 NewOpc = TargetOpcode::G_CTTZ_ZERO_POISON;
2911 }
2912
2913 unsigned SizeDiff =
2914 WideTy.getScalarSizeInBits() - CurTy.getScalarSizeInBits();
2915
2916 if (Opcode == TargetOpcode::G_CTLZ_ZERO_POISON) {
2917 // An optimization where the result is the CTLZ after the left shift by
2918 // (Difference in widety and current ty), that is,
2919 // MIBSrc = MIBSrc << (sizeinbits(WideTy) - sizeinbits(CurTy))
2920 // Result = ctlz MIBSrc
2921 MIBSrc = MIRBuilder.buildShl(Dst: WideTy, Src0: MIBSrc,
2922 Src1: MIRBuilder.buildConstant(Res: WideTy, Val: SizeDiff));
2923 }
2924
2925 // Perform the operation at the larger size.
2926 auto MIBNewOp = MIRBuilder.buildInstr(Opc: NewOpc, DstOps: {WideTy}, SrcOps: {MIBSrc});
2927 // This is already the correct result for CTPOP and CTTZs
2928 if (Opcode == TargetOpcode::G_CTLZ || Opcode == TargetOpcode::G_CTLS) {
2929 // The correct result is NewOp - (Difference in widety and current ty).
2930 // At this stage SUB is guaranteed to be positive no-wrap,
2931 // that to be used in further KnownBits optimizations for CTLZ.
2932 MIBNewOp = MIRBuilder.buildSub(
2933 Dst: WideTy, Src0: MIBNewOp, Src1: MIRBuilder.buildConstant(Res: WideTy, Val: SizeDiff),
2934 Flags: Opcode == TargetOpcode::G_CTLZ
2935 ? std::optional<unsigned>(MachineInstr::NoUWrap)
2936 : std::nullopt);
2937 }
2938
2939 MIRBuilder.buildZExtOrTrunc(Res: MI.getOperand(i: 0), Op: MIBNewOp);
2940 MI.eraseFromParent();
2941 return Legalized;
2942 }
2943 case TargetOpcode::G_BSWAP: {
2944 Observer.changingInstr(MI);
2945 Register DstReg = MI.getOperand(i: 0).getReg();
2946
2947 Register ShrReg = MRI.createGenericVirtualRegister(Ty: WideTy);
2948 Register DstExt = MRI.createGenericVirtualRegister(Ty: WideTy);
2949 Register ShiftAmtReg = MRI.createGenericVirtualRegister(Ty: WideTy);
2950 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ANYEXT);
2951
2952 MI.getOperand(i: 0).setReg(DstExt);
2953
2954 MIRBuilder.setInsertPt(MBB&: MIRBuilder.getMBB(), II: ++MIRBuilder.getInsertPt());
2955
2956 LLT Ty = MRI.getType(Reg: DstReg);
2957 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
2958 MIRBuilder.buildConstant(Res: ShiftAmtReg, Val: DiffBits);
2959 MIRBuilder.buildLShr(Dst: ShrReg, Src0: DstExt, Src1: ShiftAmtReg);
2960
2961 MIRBuilder.buildTrunc(Res: DstReg, Op: ShrReg);
2962 Observer.changedInstr(MI);
2963 return Legalized;
2964 }
2965 case TargetOpcode::G_BITREVERSE: {
2966 Observer.changingInstr(MI);
2967
2968 Register DstReg = MI.getOperand(i: 0).getReg();
2969 LLT Ty = MRI.getType(Reg: DstReg);
2970 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
2971
2972 Register DstExt = MRI.createGenericVirtualRegister(Ty: WideTy);
2973 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ANYEXT);
2974 MI.getOperand(i: 0).setReg(DstExt);
2975 MIRBuilder.setInsertPt(MBB&: MIRBuilder.getMBB(), II: ++MIRBuilder.getInsertPt());
2976
2977 auto ShiftAmt = MIRBuilder.buildConstant(Res: WideTy, Val: DiffBits);
2978 auto Shift = MIRBuilder.buildLShr(Dst: WideTy, Src0: DstExt, Src1: ShiftAmt);
2979 MIRBuilder.buildTrunc(Res: DstReg, Op: Shift);
2980 Observer.changedInstr(MI);
2981 return Legalized;
2982 }
2983 case TargetOpcode::G_FREEZE:
2984 case TargetOpcode::G_CONSTANT_FOLD_BARRIER:
2985 Observer.changingInstr(MI);
2986 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ANYEXT);
2987 widenScalarDst(MI, WideTy);
2988 Observer.changedInstr(MI);
2989 return Legalized;
2990
2991 case TargetOpcode::G_ABS:
2992 Observer.changingInstr(MI);
2993 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_SEXT);
2994 widenScalarDst(MI, WideTy);
2995 Observer.changedInstr(MI);
2996 return Legalized;
2997
2998 case TargetOpcode::G_ADD:
2999 case TargetOpcode::G_AND:
3000 case TargetOpcode::G_MUL:
3001 case TargetOpcode::G_OR:
3002 case TargetOpcode::G_XOR:
3003 case TargetOpcode::G_SUB:
3004 case TargetOpcode::G_SHUFFLE_VECTOR:
3005 // Perform operation at larger width (any extension is fines here, high bits
3006 // don't affect the result) and then truncate the result back to the
3007 // original type.
3008 Observer.changingInstr(MI);
3009 // The G_ANYEXTs below leave the new high bits unconstrained, so no-wrap and
3010 // disjoint claims proved at the narrow width no longer hold. Paths that
3011 // widen with value-preserving G_ZEXT/G_SEXT keep their flags.
3012 MI.clearFlags(flags: MachineInstr::NoUWrap | MachineInstr::NoSWrap |
3013 MachineInstr::Disjoint);
3014 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ANYEXT);
3015 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_ANYEXT);
3016 widenScalarDst(MI, WideTy);
3017 Observer.changedInstr(MI);
3018 return Legalized;
3019
3020 case TargetOpcode::G_SBFX:
3021 case TargetOpcode::G_UBFX:
3022 Observer.changingInstr(MI);
3023
3024 if (TypeIdx == 0) {
3025 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ANYEXT);
3026 widenScalarDst(MI, WideTy);
3027 } else {
3028 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_ZEXT);
3029 widenScalarSrc(MI, WideTy, OpIdx: 3, ExtOpcode: TargetOpcode::G_ZEXT);
3030 }
3031
3032 Observer.changedInstr(MI);
3033 return Legalized;
3034
3035 case TargetOpcode::G_SHL:
3036 Observer.changingInstr(MI);
3037
3038 if (TypeIdx == 0) {
3039 // Widening the result with G_ANYEXT invalidates the no-wrap flags, as in
3040 // the G_ADD/G_SUB/G_MUL case above. TypeIdx 1 widens only the shift
3041 // amount, which is value-preserving, so it keeps them.
3042 MI.clearFlags(flags: MachineInstr::NoUWrap | MachineInstr::NoSWrap);
3043 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ANYEXT);
3044 widenScalarDst(MI, WideTy);
3045 } else {
3046 assert(TypeIdx == 1);
3047 // The "number of bits to shift" operand must preserve its value as an
3048 // unsigned integer:
3049 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_ZEXT);
3050 }
3051
3052 Observer.changedInstr(MI);
3053 return Legalized;
3054
3055 case TargetOpcode::G_ROTR:
3056 case TargetOpcode::G_ROTL:
3057 if (TypeIdx != 1)
3058 return UnableToLegalize;
3059
3060 Observer.changingInstr(MI);
3061 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_ZEXT);
3062 Observer.changedInstr(MI);
3063 return Legalized;
3064
3065 case TargetOpcode::G_SDIV:
3066 case TargetOpcode::G_SREM:
3067 case TargetOpcode::G_SMIN:
3068 case TargetOpcode::G_SMAX:
3069 case TargetOpcode::G_ABDS:
3070 Observer.changingInstr(MI);
3071 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_SEXT);
3072 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_SEXT);
3073 widenScalarDst(MI, WideTy);
3074 Observer.changedInstr(MI);
3075 return Legalized;
3076
3077 case TargetOpcode::G_SDIVREM:
3078 Observer.changingInstr(MI);
3079 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_SEXT);
3080 widenScalarSrc(MI, WideTy, OpIdx: 3, ExtOpcode: TargetOpcode::G_SEXT);
3081 widenScalarDst(MI, WideTy);
3082 MIRBuilder.setInsertPt(MBB&: MIRBuilder.getMBB(), II: --MIRBuilder.getInsertPt());
3083 widenScalarDst(MI, WideTy, OpIdx: 1);
3084 Observer.changedInstr(MI);
3085 return Legalized;
3086
3087 case TargetOpcode::G_ASHR:
3088 case TargetOpcode::G_LSHR:
3089 Observer.changingInstr(MI);
3090
3091 if (TypeIdx == 0) {
3092 unsigned CvtOp = Opcode == TargetOpcode::G_ASHR ? TargetOpcode::G_SEXT
3093 : TargetOpcode::G_ZEXT;
3094
3095 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: CvtOp);
3096 widenScalarDst(MI, WideTy);
3097 } else {
3098 assert(TypeIdx == 1);
3099 // The "number of bits to shift" operand must preserve its value as an
3100 // unsigned integer:
3101 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_ZEXT);
3102 }
3103
3104 Observer.changedInstr(MI);
3105 return Legalized;
3106 case TargetOpcode::G_UDIV:
3107 case TargetOpcode::G_UREM:
3108 case TargetOpcode::G_ABDU:
3109 Observer.changingInstr(MI);
3110 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ZEXT);
3111 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_ZEXT);
3112 widenScalarDst(MI, WideTy);
3113 Observer.changedInstr(MI);
3114 return Legalized;
3115 case TargetOpcode::G_UDIVREM:
3116 Observer.changingInstr(MI);
3117 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_ZEXT);
3118 widenScalarSrc(MI, WideTy, OpIdx: 3, ExtOpcode: TargetOpcode::G_ZEXT);
3119 widenScalarDst(MI, WideTy);
3120 MIRBuilder.setInsertPt(MBB&: MIRBuilder.getMBB(), II: --MIRBuilder.getInsertPt());
3121 widenScalarDst(MI, WideTy, OpIdx: 1);
3122 Observer.changedInstr(MI);
3123 return Legalized;
3124 case TargetOpcode::G_UMIN:
3125 case TargetOpcode::G_UMAX: {
3126 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
3127
3128 auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
3129 unsigned ExtOpc =
3130 TLI.isSExtCheaperThanZExt(FromTy: getApproximateEVTForLLT(Ty, Ctx),
3131 ToTy: getApproximateEVTForLLT(Ty: WideTy, Ctx))
3132 ? TargetOpcode::G_SEXT
3133 : TargetOpcode::G_ZEXT;
3134
3135 Observer.changingInstr(MI);
3136 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: ExtOpc);
3137 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: ExtOpc);
3138 widenScalarDst(MI, WideTy);
3139 Observer.changedInstr(MI);
3140 return Legalized;
3141 }
3142
3143 case TargetOpcode::G_SELECT:
3144 Observer.changingInstr(MI);
3145 if (TypeIdx == 0) {
3146 // Perform operation at larger width (any extension is fine here, high
3147 // bits don't affect the result) and then truncate the result back to the
3148 // original type.
3149 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_ANYEXT);
3150 widenScalarSrc(MI, WideTy, OpIdx: 3, ExtOpcode: TargetOpcode::G_ANYEXT);
3151 widenScalarDst(MI, WideTy);
3152 } else {
3153 bool IsVec = MRI.getType(Reg: MI.getOperand(i: 1).getReg()).isVector();
3154 // Explicit extension is required here since high bits affect the result.
3155 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: MIRBuilder.getBoolExtOp(IsVec, IsFP: false));
3156 }
3157 Observer.changedInstr(MI);
3158 return Legalized;
3159
3160 case TargetOpcode::G_FPEXT:
3161 if (TypeIdx != 1)
3162 return UnableToLegalize;
3163
3164 Observer.changingInstr(MI);
3165 widenScalarSrcUsingFPExt(MI, WideTy, OpIdx: 1);
3166 Observer.changedInstr(MI);
3167 return Legalized;
3168 case TargetOpcode::G_FPTOSI:
3169 case TargetOpcode::G_FPTOUI:
3170 case TargetOpcode::G_INTRINSIC_LRINT:
3171 case TargetOpcode::G_INTRINSIC_LLRINT:
3172 case TargetOpcode::G_IS_FPCLASS:
3173 Observer.changingInstr(MI);
3174
3175 if (TypeIdx == 0)
3176 widenScalarDst(MI, WideTy);
3177 else
3178 widenScalarSrcUsingFPExt(MI, WideTy, OpIdx: 1);
3179
3180 Observer.changedInstr(MI);
3181 return Legalized;
3182 case TargetOpcode::G_SITOFP:
3183 Observer.changingInstr(MI);
3184
3185 if (TypeIdx == 0)
3186 widenScalarDstUsingFPTrunc(MI, WideTy, OpIdx: 0);
3187 else
3188 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_SEXT);
3189
3190 Observer.changedInstr(MI);
3191 return Legalized;
3192 case TargetOpcode::G_UITOFP:
3193 Observer.changingInstr(MI);
3194
3195 if (TypeIdx == 0)
3196 widenScalarDstUsingFPTrunc(MI, WideTy, OpIdx: 0);
3197 else
3198 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ZEXT);
3199
3200 Observer.changedInstr(MI);
3201 return Legalized;
3202 case TargetOpcode::G_FPTOSI_SAT:
3203 case TargetOpcode::G_FPTOUI_SAT:
3204 Observer.changingInstr(MI);
3205
3206 if (TypeIdx == 0) {
3207 Register OldDst = MI.getOperand(i: 0).getReg();
3208 LLT Ty = MRI.getType(Reg: OldDst);
3209 Register ExtReg = MRI.createGenericVirtualRegister(Ty: WideTy);
3210 Register NewDst;
3211 MI.getOperand(i: 0).setReg(ExtReg);
3212 uint64_t ShortBits = Ty.getScalarSizeInBits();
3213 uint64_t WideBits = WideTy.getScalarSizeInBits();
3214 MIRBuilder.setInsertPt(MBB&: MIRBuilder.getMBB(), II: ++MIRBuilder.getInsertPt());
3215 if (Opcode == TargetOpcode::G_FPTOSI_SAT) {
3216 // z = i16 fptosi_sat(a)
3217 // ->
3218 // x = i32 fptosi_sat(a)
3219 // y = smin(x, 32767)
3220 // z = smax(y, -32768)
3221 auto MaxVal = MIRBuilder.buildConstant(
3222 Res: WideTy, Val: APInt::getSignedMaxValue(numBits: ShortBits).sext(width: WideBits));
3223 auto MinVal = MIRBuilder.buildConstant(
3224 Res: WideTy, Val: APInt::getSignedMinValue(numBits: ShortBits).sext(width: WideBits));
3225 Register MidReg =
3226 MIRBuilder.buildSMin(Dst: WideTy, Src0: ExtReg, Src1: MaxVal).getReg(Idx: 0);
3227 NewDst = MIRBuilder.buildSMax(Dst: WideTy, Src0: MidReg, Src1: MinVal).getReg(Idx: 0);
3228 } else {
3229 // z = i16 fptoui_sat(a)
3230 // ->
3231 // x = i32 fptoui_sat(a)
3232 // y = smin(x, 65535)
3233 auto MaxVal = MIRBuilder.buildConstant(
3234 Res: WideTy, Val: APInt::getAllOnes(numBits: ShortBits).zext(width: WideBits));
3235 NewDst = MIRBuilder.buildUMin(Dst: WideTy, Src0: ExtReg, Src1: MaxVal).getReg(Idx: 0);
3236 }
3237 MIRBuilder.buildTrunc(Res: OldDst, Op: NewDst);
3238 } else
3239 widenScalarSrcUsingFPExt(MI, WideTy, OpIdx: 1);
3240
3241 Observer.changedInstr(MI);
3242 return Legalized;
3243 case TargetOpcode::G_LOAD:
3244 case TargetOpcode::G_SEXTLOAD:
3245 case TargetOpcode::G_ZEXTLOAD:
3246 case TargetOpcode::G_FPEXTLOAD:
3247 Observer.changingInstr(MI);
3248 widenScalarDst(MI, WideTy);
3249 Observer.changedInstr(MI);
3250 return Legalized;
3251
3252 case TargetOpcode::G_STORE: {
3253 if (TypeIdx != 0)
3254 return UnableToLegalize;
3255
3256 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
3257 assert(!Ty.isPointerOrPointerVector() && "Can't widen type");
3258 if (!Ty.isScalar()) {
3259 // We need to widen the vector element type.
3260 Observer.changingInstr(MI);
3261 widenScalarSrc(MI, WideTy, OpIdx: 0, ExtOpcode: TargetOpcode::G_ANYEXT);
3262 // We also need to adjust the MMO to turn this into a truncating store.
3263 MachineMemOperand &MMO = **MI.memoperands_begin();
3264 MachineFunction &MF = MIRBuilder.getMF();
3265 auto *NewMMO = MF.getMachineMemOperand(MMO: &MMO, PtrInfo: MMO.getPointerInfo(), Ty);
3266 MI.setMemRefs(MF, MemRefs: {NewMMO});
3267 Observer.changedInstr(MI);
3268 return Legalized;
3269 }
3270
3271 Observer.changingInstr(MI);
3272
3273 unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
3274 TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
3275 widenScalarSrc(MI, WideTy, OpIdx: 0, ExtOpcode: ExtType);
3276
3277 Observer.changedInstr(MI);
3278 return Legalized;
3279 }
3280 case TargetOpcode::G_FPTRUNCSTORE:
3281 if (TypeIdx != 0)
3282 return UnableToLegalize;
3283 Observer.changingInstr(MI);
3284 widenScalarSrc(MI, WideTy, OpIdx: 0, ExtOpcode: TargetOpcode::G_FPEXT);
3285 Observer.changedInstr(MI);
3286 return Legalized;
3287 case TargetOpcode::G_CONSTANT: {
3288 MachineOperand &SrcMO = MI.getOperand(i: 1);
3289 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
3290 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant(
3291 SmallTy: MRI.getType(Reg: MI.getOperand(i: 0).getReg()));
3292 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT ||
3293 ExtOpc == TargetOpcode::G_ANYEXT) &&
3294 "Illegal Extend");
3295 const APInt &SrcVal = SrcMO.getCImm()->getValue();
3296 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT)
3297 ? SrcVal.sext(width: WideTy.getSizeInBits())
3298 : SrcVal.zext(width: WideTy.getSizeInBits());
3299 Observer.changingInstr(MI);
3300 SrcMO.setCImm(ConstantInt::get(Context&: Ctx, V: Val));
3301
3302 widenScalarDst(MI, WideTy);
3303 Observer.changedInstr(MI);
3304 return Legalized;
3305 }
3306 case TargetOpcode::G_FCONSTANT: {
3307 // To avoid changing the bits of the constant due to extension to a larger
3308 // type and then using G_FPTRUNC, we simply convert to a G_CONSTANT.
3309 MachineOperand &SrcMO = MI.getOperand(i: 1);
3310 APInt Val = SrcMO.getFPImm()->getValueAPF().bitcastToAPInt();
3311 MIRBuilder.setInstrAndDebugLoc(MI);
3312 auto IntCst = MIRBuilder.buildConstant(Res: MI.getOperand(i: 0).getReg(), Val);
3313 widenScalarDst(MI&: *IntCst, WideTy, OpIdx: 0, TruncOpcode: TargetOpcode::G_TRUNC);
3314 MI.eraseFromParent();
3315 return Legalized;
3316 }
3317 case TargetOpcode::G_IMPLICIT_DEF: {
3318 Observer.changingInstr(MI);
3319 widenScalarDst(MI, WideTy);
3320 Observer.changedInstr(MI);
3321 return Legalized;
3322 }
3323 case TargetOpcode::G_BRCOND:
3324 Observer.changingInstr(MI);
3325 widenScalarSrc(MI, WideTy, OpIdx: 0, ExtOpcode: MIRBuilder.getBoolExtOp(IsVec: false, IsFP: false));
3326 Observer.changedInstr(MI);
3327 return Legalized;
3328
3329 case TargetOpcode::G_FCMP:
3330 Observer.changingInstr(MI);
3331 if (TypeIdx == 0)
3332 widenScalarDst(MI, WideTy);
3333 else {
3334 widenScalarSrcUsingFPExt(MI, WideTy, OpIdx: 2);
3335 widenScalarSrcUsingFPExt(MI, WideTy, OpIdx: 3);
3336 }
3337 Observer.changedInstr(MI);
3338 return Legalized;
3339
3340 case TargetOpcode::G_ICMP:
3341 Observer.changingInstr(MI);
3342 if (TypeIdx == 0)
3343 widenScalarDst(MI, WideTy);
3344 else {
3345 LLT SrcTy = MRI.getType(Reg: MI.getOperand(i: 2).getReg());
3346 CmpInst::Predicate Pred =
3347 static_cast<CmpInst::Predicate>(MI.getOperand(i: 1).getPredicate());
3348
3349 auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
3350 unsigned ExtOpcode =
3351 (CmpInst::isSigned(Pred) ||
3352 TLI.isSExtCheaperThanZExt(FromTy: getApproximateEVTForLLT(Ty: SrcTy, Ctx),
3353 ToTy: getApproximateEVTForLLT(Ty: WideTy, Ctx)))
3354 ? TargetOpcode::G_SEXT
3355 : TargetOpcode::G_ZEXT;
3356 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode);
3357 widenScalarSrc(MI, WideTy, OpIdx: 3, ExtOpcode);
3358 }
3359 Observer.changedInstr(MI);
3360 return Legalized;
3361
3362 case TargetOpcode::G_PTR_ADD:
3363 assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD");
3364 Observer.changingInstr(MI);
3365 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_SEXT);
3366 Observer.changedInstr(MI);
3367 return Legalized;
3368
3369 case TargetOpcode::G_PHI: {
3370 assert(TypeIdx == 0 && "Expecting only Idx 0");
3371
3372 Observer.changingInstr(MI);
3373 for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
3374 MachineBasicBlock &OpMBB = *MI.getOperand(i: I + 1).getMBB();
3375 MIRBuilder.setInsertPt(MBB&: OpMBB, II: OpMBB.getFirstTerminatorForward());
3376 widenScalarSrc(MI, WideTy, OpIdx: I, ExtOpcode: TargetOpcode::G_ANYEXT);
3377 }
3378
3379 MachineBasicBlock &MBB = *MI.getParent();
3380 MIRBuilder.setInsertPt(MBB, II: --MBB.getFirstNonPHI());
3381 widenScalarDst(MI, WideTy);
3382 Observer.changedInstr(MI);
3383 return Legalized;
3384 }
3385 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
3386 if (TypeIdx == 0) {
3387 Register VecReg = MI.getOperand(i: 1).getReg();
3388 LLT VecTy = MRI.getType(Reg: VecReg);
3389 Observer.changingInstr(MI);
3390
3391 widenScalarSrc(MI, WideTy: LLT::vector(EC: VecTy.getElementCount(), ScalarTy: WideTy), OpIdx: 1,
3392 ExtOpcode: TargetOpcode::G_ANYEXT);
3393
3394 widenScalarDst(MI, WideTy, OpIdx: 0);
3395 Observer.changedInstr(MI);
3396 return Legalized;
3397 }
3398
3399 if (TypeIdx != 2)
3400 return UnableToLegalize;
3401 Observer.changingInstr(MI);
3402 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_ZEXT);
3403 Observer.changedInstr(MI);
3404 return Legalized;
3405 }
3406 case TargetOpcode::G_INSERT_VECTOR_ELT: {
3407 if (TypeIdx == 0) {
3408 Observer.changingInstr(MI);
3409 const LLT WideEltTy = WideTy.getElementType();
3410
3411 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ANYEXT);
3412 widenScalarSrc(MI, WideTy: WideEltTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_ANYEXT);
3413 widenScalarDst(MI, WideTy, OpIdx: 0);
3414 Observer.changedInstr(MI);
3415 return Legalized;
3416 }
3417
3418 if (TypeIdx == 1) {
3419 Observer.changingInstr(MI);
3420
3421 Register VecReg = MI.getOperand(i: 1).getReg();
3422 LLT VecTy = MRI.getType(Reg: VecReg);
3423 LLT WideVecTy = VecTy.changeVectorElementType(NewEltTy: WideTy);
3424
3425 widenScalarSrc(MI, WideTy: WideVecTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ANYEXT);
3426 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_ANYEXT);
3427 widenScalarDst(MI, WideTy: WideVecTy, OpIdx: 0);
3428 Observer.changedInstr(MI);
3429 return Legalized;
3430 }
3431
3432 if (TypeIdx == 2) {
3433 Observer.changingInstr(MI);
3434 widenScalarSrc(MI, WideTy, OpIdx: 3, ExtOpcode: TargetOpcode::G_ZEXT);
3435 Observer.changedInstr(MI);
3436 return Legalized;
3437 }
3438
3439 return UnableToLegalize;
3440 }
3441 case TargetOpcode::G_FADD:
3442 case TargetOpcode::G_FMUL:
3443 case TargetOpcode::G_FSUB:
3444 case TargetOpcode::G_FMA:
3445 case TargetOpcode::G_FMAD:
3446 case TargetOpcode::G_FNEG:
3447 case TargetOpcode::G_FABS:
3448 case TargetOpcode::G_FCANONICALIZE:
3449 case TargetOpcode::G_FMINNUM:
3450 case TargetOpcode::G_FMAXNUM:
3451 case TargetOpcode::G_FMINNUM_IEEE:
3452 case TargetOpcode::G_FMAXNUM_IEEE:
3453 case TargetOpcode::G_FMINIMUM:
3454 case TargetOpcode::G_FMAXIMUM:
3455 case TargetOpcode::G_FMINIMUMNUM:
3456 case TargetOpcode::G_FMAXIMUMNUM:
3457 case TargetOpcode::G_FDIV:
3458 case TargetOpcode::G_FREM:
3459 case TargetOpcode::G_FCEIL:
3460 case TargetOpcode::G_FFLOOR:
3461 case TargetOpcode::G_FCOS:
3462 case TargetOpcode::G_FSIN:
3463 case TargetOpcode::G_FTAN:
3464 case TargetOpcode::G_FACOS:
3465 case TargetOpcode::G_FASIN:
3466 case TargetOpcode::G_FATAN:
3467 case TargetOpcode::G_FATAN2:
3468 case TargetOpcode::G_FCOSH:
3469 case TargetOpcode::G_FSINH:
3470 case TargetOpcode::G_FTANH:
3471 case TargetOpcode::G_FLOG10:
3472 case TargetOpcode::G_FLOG:
3473 case TargetOpcode::G_FLOG2:
3474 case TargetOpcode::G_FRINT:
3475 case TargetOpcode::G_FNEARBYINT:
3476 case TargetOpcode::G_FSQRT:
3477 case TargetOpcode::G_FEXP:
3478 case TargetOpcode::G_FEXP2:
3479 case TargetOpcode::G_FEXP10:
3480 case TargetOpcode::G_FPOW:
3481 case TargetOpcode::G_INTRINSIC_TRUNC:
3482 case TargetOpcode::G_INTRINSIC_ROUND:
3483 case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
3484 assert(TypeIdx == 0);
3485 Observer.changingInstr(MI);
3486
3487 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
3488 widenScalarSrcUsingFPExt(MI, WideTy, OpIdx: I);
3489
3490 widenScalarDstUsingFPTrunc(MI, WideTy, OpIdx: 0);
3491 Observer.changedInstr(MI);
3492 return Legalized;
3493 case TargetOpcode::G_FMODF: {
3494 Observer.changingInstr(MI);
3495 widenScalarSrcUsingFPExt(MI, WideTy, OpIdx: 2);
3496
3497 widenScalarDstUsingFPTrunc(MI, WideTy, OpIdx: 1);
3498 MIRBuilder.setInsertPt(MBB&: MIRBuilder.getMBB(), II: --MIRBuilder.getInsertPt());
3499 widenScalarDstUsingFPTrunc(MI, WideTy, OpIdx: 0);
3500 Observer.changedInstr(MI);
3501 return Legalized;
3502 }
3503 case TargetOpcode::G_FPOWI:
3504 case TargetOpcode::G_FLDEXP:
3505 case TargetOpcode::G_STRICT_FLDEXP: {
3506 if (TypeIdx == 0) {
3507 if (Opcode == TargetOpcode::G_STRICT_FLDEXP)
3508 return UnableToLegalize;
3509
3510 Observer.changingInstr(MI);
3511 widenScalarSrcUsingFPExt(MI, WideTy, OpIdx: 1);
3512 widenScalarDstUsingFPTrunc(MI, WideTy, OpIdx: 0);
3513 Observer.changedInstr(MI);
3514 return Legalized;
3515 }
3516
3517 if (TypeIdx == 1) {
3518 // For some reason SelectionDAG tries to promote to a libcall without
3519 // actually changing the integer type for promotion.
3520 Observer.changingInstr(MI);
3521 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_SEXT);
3522 Observer.changedInstr(MI);
3523 return Legalized;
3524 }
3525
3526 return UnableToLegalize;
3527 }
3528 case TargetOpcode::G_FFREXP: {
3529 Observer.changingInstr(MI);
3530
3531 if (TypeIdx == 0) {
3532 widenScalarSrcUsingFPExt(MI, WideTy, OpIdx: 2);
3533 widenScalarDstUsingFPTrunc(MI, WideTy, OpIdx: 0);
3534 } else {
3535 widenScalarDst(MI, WideTy, OpIdx: 1);
3536 }
3537
3538 Observer.changedInstr(MI);
3539 return Legalized;
3540 }
3541 case TargetOpcode::G_LROUND:
3542 case TargetOpcode::G_LLROUND:
3543 Observer.changingInstr(MI);
3544
3545 if (TypeIdx == 0)
3546 widenScalarDst(MI, WideTy);
3547 else
3548 widenScalarSrcUsingFPExt(MI, WideTy, OpIdx: 1);
3549
3550 Observer.changedInstr(MI);
3551 return Legalized;
3552
3553 case TargetOpcode::G_INTTOPTR:
3554 if (TypeIdx != 1)
3555 return UnableToLegalize;
3556
3557 Observer.changingInstr(MI);
3558 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ZEXT);
3559 Observer.changedInstr(MI);
3560 return Legalized;
3561 case TargetOpcode::G_PTRTOINT:
3562 if (TypeIdx != 0)
3563 return UnableToLegalize;
3564
3565 Observer.changingInstr(MI);
3566 widenScalarDst(MI, WideTy, OpIdx: 0);
3567 Observer.changedInstr(MI);
3568 return Legalized;
3569 case TargetOpcode::G_BUILD_VECTOR: {
3570 Observer.changingInstr(MI);
3571
3572 const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType();
3573 for (int I = 1, E = MI.getNumOperands(); I != E; ++I)
3574 widenScalarSrc(MI, WideTy: WideEltTy, OpIdx: I, ExtOpcode: TargetOpcode::G_ANYEXT);
3575
3576 // Avoid changing the result vector type if the source element type was
3577 // requested.
3578 if (TypeIdx == 1) {
3579 MI.setDesc(MIRBuilder.getTII().get(Opcode: TargetOpcode::G_BUILD_VECTOR_TRUNC));
3580 } else {
3581 widenScalarDst(MI, WideTy, OpIdx: 0);
3582 }
3583
3584 Observer.changedInstr(MI);
3585 return Legalized;
3586 }
3587 case TargetOpcode::G_SEXT_INREG:
3588 if (TypeIdx != 0)
3589 return UnableToLegalize;
3590
3591 Observer.changingInstr(MI);
3592 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ANYEXT);
3593 widenScalarDst(MI, WideTy, OpIdx: 0, TruncOpcode: TargetOpcode::G_TRUNC);
3594 Observer.changedInstr(MI);
3595 return Legalized;
3596 case TargetOpcode::G_PTRMASK: {
3597 if (TypeIdx != 1)
3598 return UnableToLegalize;
3599 Observer.changingInstr(MI);
3600 widenScalarSrc(MI, WideTy, OpIdx: 2, ExtOpcode: TargetOpcode::G_ZEXT);
3601 Observer.changedInstr(MI);
3602 return Legalized;
3603 }
3604 case TargetOpcode::G_VECREDUCE_ADD: {
3605 if (TypeIdx != 1)
3606 return UnableToLegalize;
3607 Observer.changingInstr(MI);
3608 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ANYEXT);
3609 widenScalarDst(MI, WideTy: WideTy.getScalarType(), OpIdx: 0, TruncOpcode: TargetOpcode::G_TRUNC);
3610 Observer.changedInstr(MI);
3611 return Legalized;
3612 }
3613 case TargetOpcode::G_VECREDUCE_FADD:
3614 case TargetOpcode::G_VECREDUCE_FMUL:
3615 case TargetOpcode::G_VECREDUCE_FMIN:
3616 case TargetOpcode::G_VECREDUCE_FMAX:
3617 case TargetOpcode::G_VECREDUCE_FMINIMUM:
3618 case TargetOpcode::G_VECREDUCE_FMAXIMUM: {
3619 if (TypeIdx != 0)
3620 return UnableToLegalize;
3621 Observer.changingInstr(MI);
3622 Register VecReg = MI.getOperand(i: 1).getReg();
3623 LLT VecTy = MRI.getType(Reg: VecReg);
3624 LLT WideVecTy = VecTy.changeElementType(NewEltTy: WideTy);
3625 widenScalarSrcUsingFPExt(MI, WideTy: WideVecTy, OpIdx: 1);
3626 widenScalarDstUsingFPTrunc(MI, WideTy, OpIdx: 0);
3627 Observer.changedInstr(MI);
3628 return Legalized;
3629 }
3630 case TargetOpcode::G_VSCALE: {
3631 MachineOperand &SrcMO = MI.getOperand(i: 1);
3632 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
3633 const APInt &SrcVal = SrcMO.getCImm()->getValue();
3634 // The CImm is always a signed value
3635 const APInt Val = SrcVal.sext(width: WideTy.getSizeInBits());
3636 Observer.changingInstr(MI);
3637 SrcMO.setCImm(ConstantInt::get(Context&: Ctx, V: Val));
3638 widenScalarDst(MI, WideTy);
3639 Observer.changedInstr(MI);
3640 return Legalized;
3641 }
3642 case TargetOpcode::G_SPLAT_VECTOR: {
3643 if (TypeIdx != 1)
3644 return UnableToLegalize;
3645
3646 Observer.changingInstr(MI);
3647 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ANYEXT);
3648 Observer.changedInstr(MI);
3649 return Legalized;
3650 }
3651 case TargetOpcode::G_INSERT_SUBVECTOR: {
3652 if (TypeIdx != 0)
3653 return UnableToLegalize;
3654
3655 GInsertSubvector &IS = cast<GInsertSubvector>(Val&: MI);
3656 Register BigVec = IS.getBigVec();
3657 Register SubVec = IS.getSubVec();
3658
3659 LLT SubVecTy = MRI.getType(Reg: SubVec);
3660 LLT SubVecWideTy = SubVecTy.changeElementType(NewEltTy: WideTy.getElementType());
3661
3662 // Widen the G_INSERT_SUBVECTOR
3663 auto BigZExt = MIRBuilder.buildZExt(Res: WideTy, Op: BigVec);
3664 auto SubZExt = MIRBuilder.buildZExt(Res: SubVecWideTy, Op: SubVec);
3665 auto WideInsert = MIRBuilder.buildInsertSubvector(Res: WideTy, Src0: BigZExt, Src1: SubZExt,
3666 Index: IS.getIndexImm());
3667
3668 // Truncate back down
3669 auto SplatZero = MIRBuilder.buildSplatVector(
3670 Res: WideTy, Val: MIRBuilder.buildConstant(Res: WideTy.getElementType(), Val: 0));
3671 MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_NE, Res: IS.getReg(Idx: 0), Op0: WideInsert,
3672 Op1: SplatZero);
3673
3674 MI.eraseFromParent();
3675
3676 return Legalized;
3677 }
3678 case TargetOpcode::G_BITCAST:
3679 if (WideTy.isVector())
3680 return UnableToLegalize;
3681 Observer.changingInstr(MI);
3682 if (TypeIdx == 0)
3683 widenScalarDst(MI, WideTy, OpIdx: 0, TruncOpcode: TargetOpcode::G_TRUNC);
3684 else
3685 widenScalarSrc(MI, WideTy, OpIdx: 1, ExtOpcode: TargetOpcode::G_ANYEXT);
3686 Observer.changedInstr(MI);
3687
3688 Register Dst = MI.getOperand(i: 0).getReg();
3689 Register Src = MI.getOperand(i: 1).getReg();
3690 if (MRI.getType(Reg: Dst) == MRI.getType(Reg: Src)) {
3691 Observer.changingAllUsesOfReg(MRI, Reg: Dst);
3692 MRI.replaceRegWith(FromReg: Dst, ToReg: Src);
3693 Observer.finishedChangingAllUsesOfReg();
3694 MI.eraseFromParent();
3695 }
3696
3697 return Legalized;
3698 }
3699}
3700
3701static void getUnmergePieces(SmallVectorImpl<Register> &Pieces,
3702 MachineIRBuilder &B, Register Src, LLT Ty) {
3703 auto Unmerge = B.buildUnmerge(Res: Ty, Op: Src);
3704 for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I)
3705 Pieces.push_back(Elt: Unmerge.getReg(Idx: I));
3706}
3707
3708static void emitLoadFromConstantPool(Register DstReg, const Constant *ConstVal,
3709 MachineIRBuilder &MIRBuilder) {
3710 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
3711 MachineFunction &MF = MIRBuilder.getMF();
3712 const DataLayout &DL = MIRBuilder.getDataLayout();
3713 unsigned AddrSpace = DL.getDefaultGlobalsAddressSpace();
3714 LLT AddrPtrTy = LLT::pointer(AddressSpace: AddrSpace, SizeInBits: DL.getPointerSizeInBits(AS: AddrSpace));
3715 LLT DstLLT = MRI.getType(Reg: DstReg);
3716
3717 Align Alignment(DL.getABITypeAlign(Ty: ConstVal->getType()));
3718
3719 auto Addr = MIRBuilder.buildConstantPool(
3720 Res: AddrPtrTy,
3721 Idx: MF.getConstantPool()->getConstantPoolIndex(C: ConstVal, Alignment));
3722
3723 MachineMemOperand *MMO =
3724 MF.getMachineMemOperand(PtrInfo: MachinePointerInfo::getConstantPool(MF),
3725 F: MachineMemOperand::MOLoad, MemTy: DstLLT, BaseAlignment: Alignment);
3726
3727 MIRBuilder.buildLoadInstr(Opcode: TargetOpcode::G_LOAD, Res: DstReg, Addr, MMO&: *MMO);
3728}
3729
3730LegalizerHelper::LegalizeResult
3731LegalizerHelper::lowerConstant(MachineInstr &MI) {
3732 const MachineOperand &ConstOperand = MI.getOperand(i: 1);
3733 const Constant *ConstantVal = ConstOperand.getCImm();
3734
3735 emitLoadFromConstantPool(DstReg: MI.getOperand(i: 0).getReg(), ConstVal: ConstantVal, MIRBuilder);
3736 MI.eraseFromParent();
3737
3738 return Legalized;
3739}
3740
3741LegalizerHelper::LegalizeResult
3742LegalizerHelper::lowerFConstant(MachineInstr &MI) {
3743 const MachineOperand &ConstOperand = MI.getOperand(i: 1);
3744 const Constant *ConstantVal = ConstOperand.getFPImm();
3745
3746 emitLoadFromConstantPool(DstReg: MI.getOperand(i: 0).getReg(), ConstVal: ConstantVal, MIRBuilder);
3747 MI.eraseFromParent();
3748
3749 return Legalized;
3750}
3751
3752LegalizerHelper::LegalizeResult
3753LegalizerHelper::lowerBitcast(MachineInstr &MI) {
3754 auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
3755 if (SrcTy.isVector()) {
3756 LLT SrcEltTy = SrcTy.getElementType();
3757 SmallVector<Register, 8> SrcRegs;
3758
3759 if (DstTy.isVector()) {
3760 int NumDstElt = DstTy.getNumElements();
3761 int NumSrcElt = SrcTy.getNumElements();
3762
3763 LLT DstEltTy = DstTy.getElementType();
3764 LLT DstCastTy = DstEltTy; // Intermediate bitcast result type
3765 LLT SrcPartTy = SrcEltTy; // Original unmerge result type.
3766
3767 // If there's an element size mismatch, insert intermediate casts to match
3768 // the result element type.
3769 if (NumSrcElt < NumDstElt) { // Source element type is larger.
3770 // %1:_(<4 x s8>) = G_BITCAST %0:_(<2 x s16>)
3771 //
3772 // =>
3773 //
3774 // %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0
3775 // %3:_(<2 x s8>) = G_BITCAST %2
3776 // %4:_(<2 x s8>) = G_BITCAST %3
3777 // %1:_(<4 x s16>) = G_CONCAT_VECTORS %3, %4
3778 DstCastTy = DstTy.changeVectorElementCount(
3779 EC: ElementCount::getFixed(MinVal: NumDstElt / NumSrcElt));
3780 SrcPartTy = SrcEltTy;
3781 } else if (NumSrcElt > NumDstElt) { // Source element type is smaller.
3782 //
3783 // %1:_(<2 x s16>) = G_BITCAST %0:_(<4 x s8>)
3784 //
3785 // =>
3786 //
3787 // %2:_(<2 x s8>), %3:_(<2 x s8>) = G_UNMERGE_VALUES %0
3788 // %3:_(s16) = G_BITCAST %2
3789 // %4:_(s16) = G_BITCAST %3
3790 // %1:_(<2 x s16>) = G_BUILD_VECTOR %3, %4
3791 SrcPartTy = SrcTy.changeVectorElementCount(
3792 EC: ElementCount::getFixed(MinVal: NumSrcElt / NumDstElt));
3793 DstCastTy = DstEltTy;
3794 }
3795
3796 getUnmergePieces(Pieces&: SrcRegs, B&: MIRBuilder, Src, Ty: SrcPartTy);
3797 for (Register &SrcReg : SrcRegs)
3798 SrcReg = MIRBuilder.buildBitcast(Dst: DstCastTy, Src: SrcReg).getReg(Idx: 0);
3799 } else
3800 getUnmergePieces(Pieces&: SrcRegs, B&: MIRBuilder, Src, Ty: SrcEltTy);
3801
3802 MIRBuilder.buildMergeLikeInstr(Res: Dst, Ops: SrcRegs);
3803 MI.eraseFromParent();
3804 return Legalized;
3805 }
3806
3807 if (DstTy.isVector()) {
3808 SmallVector<Register, 8> SrcRegs;
3809 getUnmergePieces(Pieces&: SrcRegs, B&: MIRBuilder, Src, Ty: DstTy.getElementType());
3810 MIRBuilder.buildMergeLikeInstr(Res: Dst, Ops: SrcRegs);
3811 MI.eraseFromParent();
3812 return Legalized;
3813 }
3814
3815 return UnableToLegalize;
3816}
3817
3818/// Figure out the bit offset into a register when coercing a vector index for
3819/// the wide element type. This is only for the case when promoting vector to
3820/// one with larger elements.
3821//
3822///
3823/// %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize))
3824/// %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize)
3825static Register getBitcastWiderVectorElementOffset(MachineIRBuilder &B,
3826 Register Idx,
3827 unsigned NewEltSize,
3828 unsigned OldEltSize) {
3829 const unsigned Log2EltRatio = Log2_32(Value: NewEltSize / OldEltSize);
3830 LLT IdxTy = B.getMRI()->getType(Reg: Idx);
3831
3832 // Now figure out the amount we need to shift to get the target bits.
3833 auto OffsetMask = B.buildConstant(
3834 Res: IdxTy, Val: ~(APInt::getAllOnes(numBits: IdxTy.getSizeInBits()) << Log2EltRatio));
3835 auto OffsetIdx = B.buildAnd(Dst: IdxTy, Src0: Idx, Src1: OffsetMask);
3836 return B.buildShl(Dst: IdxTy, Src0: OffsetIdx,
3837 Src1: B.buildConstant(Res: IdxTy, Val: Log2_32(Value: OldEltSize))).getReg(Idx: 0);
3838}
3839
3840/// Perform a G_EXTRACT_VECTOR_ELT in a different sized vector element. If this
3841/// is casting to a vector with a smaller element size, perform multiple element
3842/// extracts and merge the results. If this is coercing to a vector with larger
3843/// elements, index the bitcasted vector and extract the target element with bit
3844/// operations. This is intended to force the indexing in the native register
3845/// size for architectures that can dynamically index the register file.
3846LegalizerHelper::LegalizeResult
3847LegalizerHelper::bitcastExtractVectorElt(MachineInstr &MI, unsigned TypeIdx,
3848 LLT CastTy) {
3849 if (TypeIdx != 1)
3850 return UnableToLegalize;
3851
3852 auto [Dst, DstTy, SrcVec, SrcVecTy, Idx, IdxTy] = MI.getFirst3RegLLTs();
3853
3854 LLT SrcEltTy = SrcVecTy.getElementType();
3855 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1;
3856 unsigned OldNumElts = SrcVecTy.getNumElements();
3857
3858 LLT NewEltTy = CastTy.getScalarType();
3859 Register CastVec = MIRBuilder.buildBitcast(Dst: CastTy, Src: SrcVec).getReg(Idx: 0);
3860
3861 const unsigned NewEltSize = NewEltTy.getSizeInBits();
3862 const unsigned OldEltSize = SrcEltTy.getSizeInBits();
3863 if (NewNumElts > OldNumElts) {
3864 // Decreasing the vector element size
3865 //
3866 // e.g. i64 = extract_vector_elt x:v2i64, y:i32
3867 // =>
3868 // v4i32:castx = bitcast x:v2i64
3869 //
3870 // i64 = bitcast
3871 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
3872 // (i32 (extract_vector_elt castx, (2 * y + 1)))
3873 //
3874 if (NewNumElts % OldNumElts != 0)
3875 return UnableToLegalize;
3876
3877 // Type of the intermediate result vector.
3878 const unsigned NewEltsPerOldElt = NewNumElts / OldNumElts;
3879 LLT MidTy =
3880 CastTy.changeElementCount(EC: ElementCount::getFixed(MinVal: NewEltsPerOldElt));
3881
3882 auto NewEltsPerOldEltK = MIRBuilder.buildConstant(Res: IdxTy, Val: NewEltsPerOldElt);
3883
3884 SmallVector<Register, 8> NewOps(NewEltsPerOldElt);
3885 auto NewBaseIdx = MIRBuilder.buildMul(Dst: IdxTy, Src0: Idx, Src1: NewEltsPerOldEltK);
3886
3887 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
3888 auto IdxOffset = MIRBuilder.buildConstant(Res: IdxTy, Val: I);
3889 auto TmpIdx = MIRBuilder.buildAdd(Dst: IdxTy, Src0: NewBaseIdx, Src1: IdxOffset);
3890 auto Elt = MIRBuilder.buildExtractVectorElement(Res: NewEltTy, Val: CastVec, Idx: TmpIdx);
3891 NewOps[I] = Elt.getReg(Idx: 0);
3892 }
3893
3894 auto NewVec = MIRBuilder.buildBuildVector(Res: MidTy, Ops: NewOps);
3895 MIRBuilder.buildBitcast(Dst, Src: NewVec);
3896 MI.eraseFromParent();
3897 return Legalized;
3898 }
3899
3900 if (NewNumElts < OldNumElts) {
3901 if (NewEltSize % OldEltSize != 0)
3902 return UnableToLegalize;
3903
3904 // This only depends on powers of 2 because we use bit tricks to figure out
3905 // the bit offset we need to shift to get the target element. A general
3906 // expansion could emit division/multiply.
3907 if (!isPowerOf2_32(Value: NewEltSize / OldEltSize))
3908 return UnableToLegalize;
3909
3910 // Increasing the vector element size.
3911 // %elt:_(small_elt) = G_EXTRACT_VECTOR_ELT %vec:_(<N x small_elt>), %idx
3912 //
3913 // =>
3914 //
3915 // %cast = G_BITCAST %vec
3916 // %scaled_idx = G_LSHR %idx, Log2(DstEltSize / SrcEltSize)
3917 // %wide_elt = G_EXTRACT_VECTOR_ELT %cast, %scaled_idx
3918 // %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize))
3919 // %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize)
3920 // %elt_bits = G_LSHR %wide_elt, %offset_bits
3921 // %elt = G_TRUNC %elt_bits
3922
3923 const unsigned Log2EltRatio = Log2_32(Value: NewEltSize / OldEltSize);
3924 auto Log2Ratio = MIRBuilder.buildConstant(Res: IdxTy, Val: Log2EltRatio);
3925
3926 // Divide to get the index in the wider element type.
3927 auto ScaledIdx = MIRBuilder.buildLShr(Dst: IdxTy, Src0: Idx, Src1: Log2Ratio);
3928
3929 Register WideElt = CastVec;
3930 if (CastTy.isVector()) {
3931 WideElt = MIRBuilder.buildExtractVectorElement(Res: NewEltTy, Val: CastVec,
3932 Idx: ScaledIdx).getReg(Idx: 0);
3933 }
3934
3935 // Compute the bit offset into the register of the target element.
3936 Register OffsetBits = getBitcastWiderVectorElementOffset(
3937 B&: MIRBuilder, Idx, NewEltSize, OldEltSize);
3938
3939 // Shift the wide element to get the target element.
3940 auto ExtractedBits = MIRBuilder.buildLShr(Dst: NewEltTy, Src0: WideElt, Src1: OffsetBits);
3941 MIRBuilder.buildTrunc(Res: Dst, Op: ExtractedBits);
3942 MI.eraseFromParent();
3943 return Legalized;
3944 }
3945
3946 return UnableToLegalize;
3947}
3948
3949/// Emit code to insert \p InsertReg into \p TargetRet at \p OffsetBits in \p
3950/// TargetReg, while preserving other bits in \p TargetReg.
3951///
3952/// (InsertReg << Offset) | (TargetReg & ~(-1 >> InsertReg.size()) << Offset)
3953static Register buildBitFieldInsert(MachineIRBuilder &B,
3954 Register TargetReg, Register InsertReg,
3955 Register OffsetBits) {
3956 LLT TargetTy = B.getMRI()->getType(Reg: TargetReg);
3957 LLT InsertTy = B.getMRI()->getType(Reg: InsertReg);
3958 auto ZextVal = B.buildZExt(Res: TargetTy, Op: InsertReg);
3959 auto ShiftedInsertVal = B.buildShl(Dst: TargetTy, Src0: ZextVal, Src1: OffsetBits);
3960
3961 // Produce a bitmask of the value to insert
3962 auto EltMask = B.buildConstant(
3963 Res: TargetTy, Val: APInt::getLowBitsSet(numBits: TargetTy.getSizeInBits(),
3964 loBitsSet: InsertTy.getSizeInBits()));
3965 // Shift it into position
3966 auto ShiftedMask = B.buildShl(Dst: TargetTy, Src0: EltMask, Src1: OffsetBits);
3967 auto InvShiftedMask = B.buildNot(Dst: TargetTy, Src0: ShiftedMask);
3968
3969 // Clear out the bits in the wide element
3970 auto MaskedOldElt = B.buildAnd(Dst: TargetTy, Src0: TargetReg, Src1: InvShiftedMask);
3971
3972 // The value to insert has all zeros already, so stick it into the masked
3973 // wide element.
3974 return B.buildOr(Dst: TargetTy, Src0: MaskedOldElt, Src1: ShiftedInsertVal).getReg(Idx: 0);
3975}
3976
3977/// Perform a G_INSERT_VECTOR_ELT in a different sized vector element. If this
3978/// is increasing the element size, perform the indexing in the target element
3979/// type, and use bit operations to insert at the element position. This is
3980/// intended for architectures that can dynamically index the register file and
3981/// want to force indexing in the native register size.
3982LegalizerHelper::LegalizeResult
3983LegalizerHelper::bitcastInsertVectorElt(MachineInstr &MI, unsigned TypeIdx,
3984 LLT CastTy) {
3985 if (TypeIdx != 0)
3986 return UnableToLegalize;
3987
3988 auto [Dst, DstTy, SrcVec, SrcVecTy, Val, ValTy, Idx, IdxTy] =
3989 MI.getFirst4RegLLTs();
3990 LLT VecTy = DstTy;
3991
3992 LLT VecEltTy = VecTy.getElementType();
3993 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy;
3994 const unsigned NewEltSize = NewEltTy.getSizeInBits();
3995 const unsigned OldEltSize = VecEltTy.getSizeInBits();
3996
3997 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1;
3998 unsigned OldNumElts = VecTy.getNumElements();
3999
4000 Register CastVec = MIRBuilder.buildBitcast(Dst: CastTy, Src: SrcVec).getReg(Idx: 0);
4001 if (NewNumElts < OldNumElts) {
4002 if (NewEltSize % OldEltSize != 0)
4003 return UnableToLegalize;
4004
4005 // This only depends on powers of 2 because we use bit tricks to figure out
4006 // the bit offset we need to shift to get the target element. A general
4007 // expansion could emit division/multiply.
4008 if (!isPowerOf2_32(Value: NewEltSize / OldEltSize))
4009 return UnableToLegalize;
4010
4011 const unsigned Log2EltRatio = Log2_32(Value: NewEltSize / OldEltSize);
4012 auto Log2Ratio = MIRBuilder.buildConstant(Res: IdxTy, Val: Log2EltRatio);
4013
4014 // Divide to get the index in the wider element type.
4015 auto ScaledIdx = MIRBuilder.buildLShr(Dst: IdxTy, Src0: Idx, Src1: Log2Ratio);
4016
4017 Register ExtractedElt = CastVec;
4018 if (CastTy.isVector()) {
4019 ExtractedElt = MIRBuilder.buildExtractVectorElement(Res: NewEltTy, Val: CastVec,
4020 Idx: ScaledIdx).getReg(Idx: 0);
4021 }
4022
4023 // Compute the bit offset into the register of the target element.
4024 Register OffsetBits = getBitcastWiderVectorElementOffset(
4025 B&: MIRBuilder, Idx, NewEltSize, OldEltSize);
4026
4027 Register InsertedElt = buildBitFieldInsert(B&: MIRBuilder, TargetReg: ExtractedElt,
4028 InsertReg: Val, OffsetBits);
4029 if (CastTy.isVector()) {
4030 InsertedElt = MIRBuilder.buildInsertVectorElement(
4031 Res: CastTy, Val: CastVec, Elt: InsertedElt, Idx: ScaledIdx).getReg(Idx: 0);
4032 }
4033
4034 MIRBuilder.buildBitcast(Dst, Src: InsertedElt);
4035 MI.eraseFromParent();
4036 return Legalized;
4037 }
4038
4039 return UnableToLegalize;
4040}
4041
4042// This attempts to handle G_CONCAT_VECTORS with illegal operands, particularly
4043// those that have smaller than legal operands.
4044//
4045// <16 x s8> = G_CONCAT_VECTORS <4 x s8>, <4 x s8>, <4 x s8>, <4 x s8>
4046//
4047// ===>
4048//
4049// s32 = G_BITCAST <4 x s8>
4050// s32 = G_BITCAST <4 x s8>
4051// s32 = G_BITCAST <4 x s8>
4052// s32 = G_BITCAST <4 x s8>
4053// <4 x s32> = G_BUILD_VECTOR s32, s32, s32, s32
4054// <16 x s8> = G_BITCAST <4 x s32>
4055LegalizerHelper::LegalizeResult
4056LegalizerHelper::bitcastConcatVector(MachineInstr &MI, unsigned TypeIdx,
4057 LLT CastTy) {
4058 // Convert it to CONCAT instruction
4059 auto ConcatMI = dyn_cast<GConcatVectors>(Val: &MI);
4060 if (!ConcatMI) {
4061 return UnableToLegalize;
4062 }
4063
4064 // Check if bitcast is Legal
4065 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
4066 LLT SrcScalTy = CastTy.getScalarType();
4067
4068 // Check if the build vector is Legal
4069 if (!LI.isLegal(Query: {TargetOpcode::G_BUILD_VECTOR, {CastTy, SrcScalTy}})) {
4070 return UnableToLegalize;
4071 }
4072
4073 // Bitcast the sources
4074 SmallVector<Register> BitcastRegs;
4075 for (unsigned i = 0; i < ConcatMI->getNumSources(); i++) {
4076 BitcastRegs.push_back(
4077 Elt: MIRBuilder.buildBitcast(Dst: SrcScalTy, Src: ConcatMI->getSourceReg(I: i))
4078 .getReg(Idx: 0));
4079 }
4080
4081 // Build the scalar values into a vector
4082 Register BuildReg =
4083 MIRBuilder.buildBuildVector(Res: CastTy, Ops: BitcastRegs).getReg(Idx: 0);
4084 MIRBuilder.buildBitcast(Dst: DstReg, Src: BuildReg);
4085
4086 MI.eraseFromParent();
4087 return Legalized;
4088}
4089
4090// This bitcasts a shuffle vector to a different type currently of the same
4091// element size. Mostly used to legalize ptr vectors, where ptrtoint/inttoptr
4092// will be used instead.
4093//
4094// <16 x p0> = G_CONCAT_VECTORS <4 x p0>, <4 x p0>, mask
4095// ===>
4096// <4 x s64> = G_PTRTOINT <4 x p0>
4097// <4 x s64> = G_PTRTOINT <4 x p0>
4098// <16 x s64> = G_CONCAT_VECTORS <4 x s64>, <4 x s64>, mask
4099// <16 x p0> = G_INTTOPTR <16 x s64>
4100LegalizerHelper::LegalizeResult
4101LegalizerHelper::bitcastShuffleVector(MachineInstr &MI, unsigned TypeIdx,
4102 LLT CastTy) {
4103 auto ShuffleMI = cast<GShuffleVector>(Val: &MI);
4104 LLT DstTy = MRI.getType(Reg: ShuffleMI->getReg(Idx: 0));
4105 LLT SrcTy = MRI.getType(Reg: ShuffleMI->getReg(Idx: 1));
4106
4107 // We currently only handle vectors of the same size.
4108 if (TypeIdx != 0 ||
4109 CastTy.getScalarSizeInBits() != DstTy.getScalarSizeInBits() ||
4110 CastTy.getElementCount() != DstTy.getElementCount())
4111 return UnableToLegalize;
4112
4113 LLT NewSrcTy = SrcTy.changeElementType(NewEltTy: CastTy.getScalarType());
4114
4115 auto Inp1 = MIRBuilder.buildCast(Dst: NewSrcTy, Src: ShuffleMI->getReg(Idx: 1));
4116 auto Inp2 = MIRBuilder.buildCast(Dst: NewSrcTy, Src: ShuffleMI->getReg(Idx: 2));
4117 auto Shuf =
4118 MIRBuilder.buildShuffleVector(Res: CastTy, Src1: Inp1, Src2: Inp2, Mask: ShuffleMI->getMask());
4119 MIRBuilder.buildCast(Dst: ShuffleMI->getReg(Idx: 0), Src: Shuf);
4120
4121 MI.eraseFromParent();
4122 return Legalized;
4123}
4124
4125/// This attempts to bitcast G_EXTRACT_SUBVECTOR to CastTy.
4126///
4127/// <vscale x 8 x i1> = G_EXTRACT_SUBVECTOR <vscale x 16 x i1>, N
4128///
4129/// ===>
4130///
4131/// <vscale x 2 x i1> = G_BITCAST <vscale x 16 x i1>
4132/// <vscale x 1 x i8> = G_EXTRACT_SUBVECTOR <vscale x 2 x i1>, N / 8
4133/// <vscale x 8 x i1> = G_BITCAST <vscale x 1 x i8>
4134LegalizerHelper::LegalizeResult
4135LegalizerHelper::bitcastExtractSubvector(MachineInstr &MI, unsigned TypeIdx,
4136 LLT CastTy) {
4137 auto ES = cast<GExtractSubvector>(Val: &MI);
4138
4139 if (!CastTy.isVector())
4140 return UnableToLegalize;
4141
4142 if (TypeIdx != 0)
4143 return UnableToLegalize;
4144
4145 Register Dst = ES->getReg(Idx: 0);
4146 Register Src = ES->getSrcVec();
4147 uint64_t Idx = ES->getIndexImm();
4148
4149 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
4150
4151 LLT DstTy = MRI.getType(Reg: Dst);
4152 LLT SrcTy = MRI.getType(Reg: Src);
4153 ElementCount DstTyEC = DstTy.getElementCount();
4154 ElementCount SrcTyEC = SrcTy.getElementCount();
4155 auto DstTyMinElts = DstTyEC.getKnownMinValue();
4156 auto SrcTyMinElts = SrcTyEC.getKnownMinValue();
4157
4158 if (DstTy == CastTy)
4159 return Legalized;
4160
4161 if (DstTy.getSizeInBits() != CastTy.getSizeInBits())
4162 return UnableToLegalize;
4163
4164 unsigned CastEltSize = CastTy.getElementType().getSizeInBits();
4165 unsigned DstEltSize = DstTy.getElementType().getSizeInBits();
4166 if (CastEltSize < DstEltSize)
4167 return UnableToLegalize;
4168
4169 auto AdjustAmt = CastEltSize / DstEltSize;
4170 if (Idx % AdjustAmt != 0 || DstTyMinElts % AdjustAmt != 0 ||
4171 SrcTyMinElts % AdjustAmt != 0)
4172 return UnableToLegalize;
4173
4174 Idx /= AdjustAmt;
4175 SrcTy = LLT::vector(EC: SrcTyEC.divideCoefficientBy(RHS: AdjustAmt), ScalarSizeInBits: AdjustAmt);
4176 auto CastVec = MIRBuilder.buildBitcast(Dst: SrcTy, Src);
4177 auto PromotedES = MIRBuilder.buildExtractSubvector(Res: CastTy, Src: CastVec, Index: Idx);
4178 MIRBuilder.buildBitcast(Dst, Src: PromotedES);
4179
4180 ES->eraseFromParent();
4181 return Legalized;
4182}
4183
4184/// This attempts to bitcast G_INSERT_SUBVECTOR to CastTy.
4185///
4186/// <vscale x 16 x i1> = G_INSERT_SUBVECTOR <vscale x 16 x i1>,
4187/// <vscale x 8 x i1>,
4188/// N
4189///
4190/// ===>
4191///
4192/// <vscale x 2 x i8> = G_BITCAST <vscale x 16 x i1>
4193/// <vscale x 1 x i8> = G_BITCAST <vscale x 8 x i1>
4194/// <vscale x 2 x i8> = G_INSERT_SUBVECTOR <vscale x 2 x i8>,
4195/// <vscale x 1 x i8>, N / 8
4196/// <vscale x 16 x i1> = G_BITCAST <vscale x 2 x i8>
4197LegalizerHelper::LegalizeResult
4198LegalizerHelper::bitcastInsertSubvector(MachineInstr &MI, unsigned TypeIdx,
4199 LLT CastTy) {
4200 auto ES = cast<GInsertSubvector>(Val: &MI);
4201
4202 if (!CastTy.isVector())
4203 return UnableToLegalize;
4204
4205 if (TypeIdx != 0)
4206 return UnableToLegalize;
4207
4208 Register Dst = ES->getReg(Idx: 0);
4209 Register BigVec = ES->getBigVec();
4210 Register SubVec = ES->getSubVec();
4211 uint64_t Idx = ES->getIndexImm();
4212
4213 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
4214
4215 LLT DstTy = MRI.getType(Reg: Dst);
4216 LLT BigVecTy = MRI.getType(Reg: BigVec);
4217 LLT SubVecTy = MRI.getType(Reg: SubVec);
4218
4219 if (DstTy == CastTy)
4220 return Legalized;
4221
4222 if (DstTy.getSizeInBits() != CastTy.getSizeInBits())
4223 return UnableToLegalize;
4224
4225 ElementCount DstTyEC = DstTy.getElementCount();
4226 ElementCount BigVecTyEC = BigVecTy.getElementCount();
4227 ElementCount SubVecTyEC = SubVecTy.getElementCount();
4228 auto DstTyMinElts = DstTyEC.getKnownMinValue();
4229 auto BigVecTyMinElts = BigVecTyEC.getKnownMinValue();
4230 auto SubVecTyMinElts = SubVecTyEC.getKnownMinValue();
4231
4232 unsigned CastEltSize = CastTy.getElementType().getSizeInBits();
4233 unsigned DstEltSize = DstTy.getElementType().getSizeInBits();
4234 if (CastEltSize < DstEltSize)
4235 return UnableToLegalize;
4236
4237 auto AdjustAmt = CastEltSize / DstEltSize;
4238 if (Idx % AdjustAmt != 0 || DstTyMinElts % AdjustAmt != 0 ||
4239 BigVecTyMinElts % AdjustAmt != 0 || SubVecTyMinElts % AdjustAmt != 0)
4240 return UnableToLegalize;
4241
4242 Idx /= AdjustAmt;
4243 BigVecTy = LLT::vector(EC: BigVecTyEC.divideCoefficientBy(RHS: AdjustAmt), ScalarSizeInBits: AdjustAmt);
4244 SubVecTy = LLT::vector(EC: SubVecTyEC.divideCoefficientBy(RHS: AdjustAmt), ScalarSizeInBits: AdjustAmt);
4245 auto CastBigVec = MIRBuilder.buildBitcast(Dst: BigVecTy, Src: BigVec);
4246 auto CastSubVec = MIRBuilder.buildBitcast(Dst: SubVecTy, Src: SubVec);
4247 auto PromotedIS =
4248 MIRBuilder.buildInsertSubvector(Res: CastTy, Src0: CastBigVec, Src1: CastSubVec, Index: Idx);
4249 MIRBuilder.buildBitcast(Dst, Src: PromotedIS);
4250
4251 ES->eraseFromParent();
4252 return Legalized;
4253}
4254
4255LegalizerHelper::LegalizeResult LegalizerHelper::lowerLoad(GAnyLoad &LoadMI) {
4256 // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
4257 Register DstReg = LoadMI.getDstReg();
4258 Register PtrReg = LoadMI.getPointerReg();
4259 LLT DstTy = MRI.getType(Reg: DstReg);
4260 MachineMemOperand &MMO = LoadMI.getMMO();
4261 LLT MemTy = MMO.getMemoryType();
4262 MachineFunction &MF = MIRBuilder.getMF();
4263
4264 LLT EltTy = MemTy.getScalarType();
4265
4266 unsigned MemSizeInBits = MemTy.getSizeInBits();
4267 unsigned MemStoreSizeInBits = 8 * MemTy.getSizeInBytes();
4268
4269 if (MemSizeInBits != MemStoreSizeInBits) {
4270 if (MemTy.isVector())
4271 return UnableToLegalize;
4272
4273 // Promote to a byte-sized load if not loading an integral number of
4274 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
4275 LLT WideMemTy = EltTy.changeElementSize(NewEltSize: MemStoreSizeInBits);
4276 MachineMemOperand *NewMMO =
4277 MF.getMachineMemOperand(MMO: &MMO, PtrInfo: MMO.getPointerInfo(), Ty: WideMemTy);
4278
4279 Register LoadReg = DstReg;
4280 LLT LoadTy = DstTy;
4281
4282 // If this wasn't already an extending load, we need to widen the result
4283 // register to avoid creating a load with a narrower result than the source.
4284 if (MemStoreSizeInBits > DstTy.getSizeInBits()) {
4285 LoadTy = WideMemTy;
4286 LoadReg = MRI.createGenericVirtualRegister(Ty: WideMemTy);
4287 }
4288
4289 if (isa<GSExtLoad>(Val: LoadMI)) {
4290 auto NewLoad = MIRBuilder.buildLoad(Res: LoadTy, Addr: PtrReg, MMO&: *NewMMO);
4291 MIRBuilder.buildSExtInReg(Res: LoadReg, Op: NewLoad, ImmOp: MemSizeInBits);
4292 } else if (isa<GZExtLoad>(Val: LoadMI) || WideMemTy == LoadTy) {
4293 auto NewLoad = MIRBuilder.buildLoad(Res: LoadTy, Addr: PtrReg, MMO&: *NewMMO);
4294 // The extra bits are guaranteed to be zero, since we stored them that
4295 // way. A zext load from Wide thus automatically gives zext from MemVT.
4296 MIRBuilder.buildAssertZExt(Res: LoadReg, Op: NewLoad, Size: MemSizeInBits);
4297 } else {
4298 MIRBuilder.buildLoad(Res: LoadReg, Addr: PtrReg, MMO&: *NewMMO);
4299 }
4300
4301 if (DstTy != LoadTy)
4302 MIRBuilder.buildTrunc(Res: DstReg, Op: LoadReg);
4303
4304 LoadMI.eraseFromParent();
4305 return Legalized;
4306 }
4307
4308 // Big endian lowering not implemented.
4309 if (MIRBuilder.getDataLayout().isBigEndian())
4310 return UnableToLegalize;
4311
4312 // This load needs splitting into power of 2 sized loads.
4313 //
4314 // Our strategy here is to generate anyextending loads for the smaller
4315 // types up to next power-2 result type, and then combine the two larger
4316 // result values together, before truncating back down to the non-pow-2
4317 // type.
4318 // E.g. v1 = i24 load =>
4319 // v2 = i32 zextload (2 byte)
4320 // v3 = i32 load (1 byte)
4321 // v4 = i32 shl v3, 16
4322 // v5 = i32 or v4, v2
4323 // v1 = i24 trunc v5
4324 // By doing this we generate the correct truncate which should get
4325 // combined away as an artifact with a matching extend.
4326
4327 uint64_t LargeSplitSize, SmallSplitSize;
4328
4329 if (!isPowerOf2_32(Value: MemSizeInBits)) {
4330 // This load needs splitting into power of 2 sized loads.
4331 LargeSplitSize = llvm::bit_floor(Value: MemSizeInBits);
4332 SmallSplitSize = MemSizeInBits - LargeSplitSize;
4333 } else {
4334 // This is already a power of 2, but we still need to split this in half.
4335 //
4336 // Assume we're being asked to decompose an unaligned load.
4337 // TODO: If this requires multiple splits, handle them all at once.
4338 auto &Ctx = MF.getFunction().getContext();
4339 if (TLI.allowsMemoryAccess(Context&: Ctx, DL: MIRBuilder.getDataLayout(), Ty: MemTy, MMO))
4340 return UnableToLegalize;
4341
4342 SmallSplitSize = LargeSplitSize = MemSizeInBits / 2;
4343 }
4344
4345 if (MemTy.isVector()) {
4346 // TODO: Handle vector extloads
4347 if (MemTy != DstTy)
4348 return UnableToLegalize;
4349
4350 Align Alignment = LoadMI.getAlign();
4351 // Given an alignment larger than the size of the memory, we can increase
4352 // the size of the load without needing to scalarize it.
4353 if (Alignment.value() * 8 > MemSizeInBits &&
4354 isPowerOf2_64(Value: DstTy.getScalarSizeInBits())) {
4355 LLT MoreTy = DstTy.changeVectorElementCount(
4356 EC: ElementCount::getFixed(MinVal: NextPowerOf2(A: DstTy.getNumElements())));
4357 MachineMemOperand *NewMMO = MF.getMachineMemOperand(MMO: &MMO, Offset: 0, Ty: MoreTy);
4358 auto NewLoad = MIRBuilder.buildLoad(Res: MoreTy, Addr: PtrReg, MMO&: *NewMMO);
4359 MIRBuilder.buildDeleteTrailingVectorElements(Res: LoadMI.getReg(Idx: 0),
4360 Op0: NewLoad.getReg(Idx: 0));
4361 LoadMI.eraseFromParent();
4362 return Legalized;
4363 }
4364
4365 // TODO: We can do better than scalarizing the vector and at least split it
4366 // in half.
4367 return reduceLoadStoreWidth(MI&: LoadMI, TypeIdx: 0, NarrowTy: DstTy.getElementType());
4368 }
4369
4370 MachineMemOperand *LargeMMO =
4371 MF.getMachineMemOperand(MMO: &MMO, Offset: 0, Size: LargeSplitSize / 8);
4372 MachineMemOperand *SmallMMO =
4373 MF.getMachineMemOperand(MMO: &MMO, Offset: LargeSplitSize / 8, Size: SmallSplitSize / 8);
4374
4375 LLT PtrTy = MRI.getType(Reg: PtrReg);
4376 unsigned AnyExtSize = PowerOf2Ceil(A: DstTy.getSizeInBits());
4377
4378 LLT AnyExtTy;
4379 LLT OffsetCstRes;
4380 if (EltTy.isPointer()) {
4381 AnyExtTy = LLT::scalar(SizeInBits: AnyExtSize);
4382 OffsetCstRes = LLT::scalar(SizeInBits: PtrTy.getSizeInBits());
4383 } else {
4384 AnyExtTy = DstTy.changeElementSize(NewEltSize: AnyExtSize);
4385 OffsetCstRes = DstTy.changeElementSize(NewEltSize: PtrTy.getSizeInBits());
4386 }
4387
4388 auto LargeLoad = MIRBuilder.buildLoadInstr(Opcode: TargetOpcode::G_ZEXTLOAD, Res: AnyExtTy,
4389 Addr: PtrReg, MMO&: *LargeMMO);
4390
4391 auto OffsetCst = MIRBuilder.buildConstant(Res: OffsetCstRes, Val: LargeSplitSize / 8);
4392 Register PtrAddReg = MRI.createGenericVirtualRegister(Ty: PtrTy);
4393 auto SmallPtr = MIRBuilder.buildObjectPtrOffset(Res: PtrAddReg, Op0: PtrReg, Op1: OffsetCst);
4394 auto SmallLoad = MIRBuilder.buildLoadInstr(Opcode: LoadMI.getOpcode(), Res: AnyExtTy,
4395 Addr: SmallPtr, MMO&: *SmallMMO);
4396
4397 auto ShiftAmt = MIRBuilder.buildConstant(Res: AnyExtTy, Val: LargeSplitSize);
4398 auto Shift = MIRBuilder.buildShl(Dst: AnyExtTy, Src0: SmallLoad, Src1: ShiftAmt);
4399
4400 if (AnyExtTy == DstTy)
4401 MIRBuilder.buildOr(Dst: DstReg, Src0: Shift, Src1: LargeLoad);
4402 else if (AnyExtTy.getSizeInBits() != DstTy.getSizeInBits()) {
4403 auto Or = MIRBuilder.buildOr(Dst: AnyExtTy, Src0: Shift, Src1: LargeLoad);
4404 MIRBuilder.buildTrunc(Res: DstReg, Op: {Or});
4405 } else {
4406 assert(DstTy.isPointer() && "expected pointer");
4407 auto Or = MIRBuilder.buildOr(Dst: AnyExtTy, Src0: Shift, Src1: LargeLoad);
4408
4409 // FIXME: We currently consider this to be illegal for non-integral address
4410 // spaces, but we need still need a way to reinterpret the bits.
4411 MIRBuilder.buildIntToPtr(Dst: DstReg, Src: Or);
4412 }
4413
4414 LoadMI.eraseFromParent();
4415 return Legalized;
4416}
4417
4418LegalizerHelper::LegalizeResult LegalizerHelper::lowerStore(GStore &StoreMI) {
4419 // Lower a non-power of 2 store into multiple pow-2 stores.
4420 // E.g. split an i24 store into an i16 store + i8 store.
4421 // We do this by first extending the stored value to the next largest power
4422 // of 2 type, and then using truncating stores to store the components.
4423 // By doing this, likewise with G_LOAD, generate an extend that can be
4424 // artifact-combined away instead of leaving behind extracts.
4425 Register SrcReg = StoreMI.getValueReg();
4426 Register PtrReg = StoreMI.getPointerReg();
4427 LLT SrcTy = MRI.getType(Reg: SrcReg);
4428 MachineFunction &MF = MIRBuilder.getMF();
4429 MachineMemOperand &MMO = **StoreMI.memoperands_begin();
4430 LLT MemTy = MMO.getMemoryType();
4431
4432 unsigned StoreWidth = MemTy.getSizeInBits();
4433 unsigned StoreSizeInBits = 8 * MemTy.getSizeInBytes();
4434
4435 if (StoreWidth != StoreSizeInBits && !SrcTy.isVector()) {
4436 // Promote to a byte-sized store with upper bits zero if not
4437 // storing an integral number of bytes. For example, promote
4438 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
4439 LLT WideTy = LLT::integer(SizeInBits: StoreSizeInBits);
4440
4441 if (StoreSizeInBits > SrcTy.getSizeInBits()) {
4442 // Avoid creating a store with a narrower source than result.
4443 SrcReg = MIRBuilder.buildAnyExt(Res: WideTy, Op: SrcReg).getReg(Idx: 0);
4444 SrcTy = WideTy;
4445 }
4446
4447 auto ZextInReg = MIRBuilder.buildZExtInReg(Res: SrcTy, Op: SrcReg, ImmOp: StoreWidth);
4448
4449 MachineMemOperand *NewMMO =
4450 MF.getMachineMemOperand(MMO: &MMO, PtrInfo: MMO.getPointerInfo(), Ty: WideTy);
4451 MIRBuilder.buildStore(Val: ZextInReg, Addr: PtrReg, MMO&: *NewMMO);
4452 StoreMI.eraseFromParent();
4453 return Legalized;
4454 }
4455
4456 if (MemTy.isVector()) {
4457 if (MemTy != SrcTy)
4458 return scalarizeVectorBooleanStore(MI&: StoreMI);
4459
4460 // TODO: We can do better than scalarizing the vector and at least split it
4461 // in half.
4462 return reduceLoadStoreWidth(MI&: StoreMI, TypeIdx: 0, NarrowTy: SrcTy.getElementType());
4463 }
4464
4465 unsigned MemSizeInBits = MemTy.getSizeInBits();
4466 uint64_t LargeSplitSize, SmallSplitSize;
4467
4468 if (!isPowerOf2_32(Value: MemSizeInBits)) {
4469 LargeSplitSize = llvm::bit_floor<uint64_t>(Value: MemTy.getSizeInBits());
4470 SmallSplitSize = MemTy.getSizeInBits() - LargeSplitSize;
4471 } else {
4472 auto &Ctx = MF.getFunction().getContext();
4473 if (TLI.allowsMemoryAccess(Context&: Ctx, DL: MIRBuilder.getDataLayout(), Ty: MemTy, MMO))
4474 return UnableToLegalize; // Don't know what we're being asked to do.
4475
4476 SmallSplitSize = LargeSplitSize = MemSizeInBits / 2;
4477 }
4478
4479 // Extend to the next pow-2. If this store was itself the result of lowering,
4480 // e.g. an s56 store being broken into s32 + s24, we might have a stored type
4481 // that's wider than the stored size.
4482 unsigned AnyExtSize = PowerOf2Ceil(A: MemTy.getSizeInBits());
4483 const LLT NewSrcTy = LLT::integer(SizeInBits: AnyExtSize);
4484
4485 if (SrcTy.isPointer()) {
4486 const LLT IntPtrTy = LLT::integer(SizeInBits: SrcTy.getSizeInBits());
4487 SrcReg = MIRBuilder.buildPtrToInt(Dst: IntPtrTy, Src: SrcReg).getReg(Idx: 0);
4488 }
4489
4490 auto ExtVal = MIRBuilder.buildAnyExtOrTrunc(Res: NewSrcTy, Op: SrcReg);
4491
4492 // Obtain the smaller value by shifting away the larger value.
4493 auto ShiftAmt = MIRBuilder.buildConstant(Res: NewSrcTy, Val: LargeSplitSize);
4494 auto SmallVal = MIRBuilder.buildLShr(Dst: NewSrcTy, Src0: ExtVal, Src1: ShiftAmt);
4495
4496 // Generate the PtrAdd and truncating stores.
4497 LLT PtrTy = MRI.getType(Reg: PtrReg);
4498 auto OffsetCst = MIRBuilder.buildConstant(Res: LLT::integer(SizeInBits: PtrTy.getSizeInBits()),
4499 Val: LargeSplitSize / 8);
4500 auto SmallPtr = MIRBuilder.buildObjectPtrOffset(Res: PtrTy, Op0: PtrReg, Op1: OffsetCst);
4501
4502 MachineMemOperand *LargeMMO =
4503 MF.getMachineMemOperand(MMO: &MMO, Offset: 0, Size: LargeSplitSize / 8);
4504 MachineMemOperand *SmallMMO =
4505 MF.getMachineMemOperand(MMO: &MMO, Offset: LargeSplitSize / 8, Size: SmallSplitSize / 8);
4506 MIRBuilder.buildStore(Val: ExtVal, Addr: PtrReg, MMO&: *LargeMMO);
4507 MIRBuilder.buildStore(Val: SmallVal, Addr: SmallPtr, MMO&: *SmallMMO);
4508 StoreMI.eraseFromParent();
4509 return Legalized;
4510}
4511
4512LegalizerHelper::LegalizeResult
4513LegalizerHelper::scalarizeVectorBooleanStore(GStore &StoreMI) {
4514 Register SrcReg = StoreMI.getValueReg();
4515 Register PtrReg = StoreMI.getPointerReg();
4516 LLT SrcTy = MRI.getType(Reg: SrcReg);
4517 MachineMemOperand &MMO = **StoreMI.memoperands_begin();
4518 LLT MemTy = MMO.getMemoryType();
4519 LLT MemScalarTy = MemTy.getElementType();
4520 MachineFunction &MF = MIRBuilder.getMF();
4521
4522 assert(SrcTy.isVector() && "Expect a vector store type");
4523
4524 if (!MemScalarTy.isByteSized()) {
4525 // We need to build an integer scalar of the vector bit pattern.
4526 // It's not legal for us to add padding when storing a vector.
4527 unsigned NumBits = MemTy.getSizeInBits();
4528 LLT IntTy = LLT::integer(SizeInBits: NumBits);
4529 auto CurrVal = MIRBuilder.buildConstant(Res: IntTy, Val: 0);
4530 LLT IdxTy = TLI.getVectorIdxLLT(DL: MF.getDataLayout());
4531
4532 for (unsigned I = 0, E = MemTy.getNumElements(); I < E; ++I) {
4533 auto Elt = MIRBuilder.buildExtractVectorElement(
4534 Res: SrcTy.getElementType(), Val: SrcReg, Idx: MIRBuilder.buildConstant(Res: IdxTy, Val: I));
4535 auto Trunc = MIRBuilder.buildTrunc(Res: MemScalarTy, Op: Elt);
4536 auto ZExt = MIRBuilder.buildZExt(Res: IntTy, Op: Trunc);
4537 unsigned ShiftIntoIdx = MF.getDataLayout().isBigEndian()
4538 ? (MemTy.getNumElements() - 1) - I
4539 : I;
4540 auto ShiftAmt = MIRBuilder.buildConstant(
4541 Res: IntTy, Val: ShiftIntoIdx * MemScalarTy.getSizeInBits());
4542 auto Shifted = MIRBuilder.buildShl(Dst: IntTy, Src0: ZExt, Src1: ShiftAmt);
4543 CurrVal = MIRBuilder.buildOr(Dst: IntTy, Src0: CurrVal, Src1: Shifted);
4544 }
4545 auto PtrInfo = MMO.getPointerInfo();
4546 auto *NewMMO = MF.getMachineMemOperand(MMO: &MMO, PtrInfo, Ty: IntTy);
4547 MIRBuilder.buildStore(Val: CurrVal, Addr: PtrReg, MMO&: *NewMMO);
4548 StoreMI.eraseFromParent();
4549 return Legalized;
4550 }
4551
4552 // TODO: implement simple scalarization.
4553 return UnableToLegalize;
4554}
4555
4556LegalizerHelper::LegalizeResult
4557LegalizerHelper::bitcast(MachineInstr &MI, unsigned TypeIdx, LLT CastTy) {
4558 switch (MI.getOpcode()) {
4559 case TargetOpcode::G_LOAD: {
4560 if (TypeIdx != 0)
4561 return UnableToLegalize;
4562 MachineMemOperand &MMO = **MI.memoperands_begin();
4563
4564 // Not sure how to interpret a bitcast of an extending load.
4565 if (MMO.getMemoryType().getSizeInBits() != CastTy.getSizeInBits())
4566 return UnableToLegalize;
4567
4568 Observer.changingInstr(MI);
4569 bitcastDst(MI, CastTy, OpIdx: 0);
4570 MMO.setType(CastTy);
4571 // The range metadata is no longer valid when reinterpreted as a different
4572 // type.
4573 MMO.clearRanges();
4574 Observer.changedInstr(MI);
4575 return Legalized;
4576 }
4577 case TargetOpcode::G_STORE: {
4578 if (TypeIdx != 0)
4579 return UnableToLegalize;
4580
4581 MachineMemOperand &MMO = **MI.memoperands_begin();
4582
4583 // Not sure how to interpret a bitcast of a truncating store.
4584 if (MMO.getMemoryType().getSizeInBits() != CastTy.getSizeInBits())
4585 return UnableToLegalize;
4586
4587 Observer.changingInstr(MI);
4588 bitcastSrc(MI, CastTy, OpIdx: 0);
4589 MMO.setType(CastTy);
4590 Observer.changedInstr(MI);
4591 return Legalized;
4592 }
4593 case TargetOpcode::G_SELECT: {
4594 if (TypeIdx != 0)
4595 return UnableToLegalize;
4596
4597 if (MRI.getType(Reg: MI.getOperand(i: 1).getReg()).isVector()) {
4598 LLVM_DEBUG(
4599 dbgs() << "bitcast action not implemented for vector select\n");
4600 return UnableToLegalize;
4601 }
4602
4603 Observer.changingInstr(MI);
4604 bitcastSrc(MI, CastTy, OpIdx: 2);
4605 bitcastSrc(MI, CastTy, OpIdx: 3);
4606 bitcastDst(MI, CastTy, OpIdx: 0);
4607 Observer.changedInstr(MI);
4608 return Legalized;
4609 }
4610 case TargetOpcode::G_AND:
4611 case TargetOpcode::G_OR:
4612 case TargetOpcode::G_XOR: {
4613 Observer.changingInstr(MI);
4614 bitcastSrc(MI, CastTy, OpIdx: 1);
4615 bitcastSrc(MI, CastTy, OpIdx: 2);
4616 bitcastDst(MI, CastTy, OpIdx: 0);
4617 Observer.changedInstr(MI);
4618 return Legalized;
4619 }
4620 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
4621 return bitcastExtractVectorElt(MI, TypeIdx, CastTy);
4622 case TargetOpcode::G_INSERT_VECTOR_ELT:
4623 return bitcastInsertVectorElt(MI, TypeIdx, CastTy);
4624 case TargetOpcode::G_CONCAT_VECTORS:
4625 return bitcastConcatVector(MI, TypeIdx, CastTy);
4626 case TargetOpcode::G_SHUFFLE_VECTOR:
4627 return bitcastShuffleVector(MI, TypeIdx, CastTy);
4628 case TargetOpcode::G_EXTRACT_SUBVECTOR:
4629 return bitcastExtractSubvector(MI, TypeIdx, CastTy);
4630 case TargetOpcode::G_INSERT_SUBVECTOR:
4631 return bitcastInsertSubvector(MI, TypeIdx, CastTy);
4632 default:
4633 return UnableToLegalize;
4634 }
4635}
4636
4637// Legalize an instruction by changing the opcode in place.
4638void LegalizerHelper::changeOpcode(MachineInstr &MI, unsigned NewOpcode) {
4639 Observer.changingInstr(MI);
4640 MI.setDesc(MIRBuilder.getTII().get(Opcode: NewOpcode));
4641 Observer.changedInstr(MI);
4642}
4643
4644LegalizerHelper::LegalizeResult
4645LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
4646 using namespace TargetOpcode;
4647 switch(MI.getOpcode()) {
4648 default:
4649 return UnableToLegalize;
4650 case TargetOpcode::G_FCONSTANT:
4651 return lowerFConstant(MI);
4652 case TargetOpcode::G_BITCAST:
4653 return lowerBitcast(MI);
4654 case TargetOpcode::G_SREM:
4655 case TargetOpcode::G_UREM: {
4656 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
4657 auto Quot =
4658 MIRBuilder.buildInstr(Opc: MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, DstOps: {Ty},
4659 SrcOps: {MI.getOperand(i: 1), MI.getOperand(i: 2)});
4660
4661 auto Prod = MIRBuilder.buildMul(Dst: Ty, Src0: Quot, Src1: MI.getOperand(i: 2));
4662 MIRBuilder.buildSub(Dst: MI.getOperand(i: 0), Src0: MI.getOperand(i: 1), Src1: Prod);
4663 MI.eraseFromParent();
4664 return Legalized;
4665 }
4666 case TargetOpcode::G_SADDO:
4667 case TargetOpcode::G_SSUBO:
4668 return lowerSADDO_SSUBO(MI);
4669 case TargetOpcode::G_SADDE:
4670 return lowerSADDE(MI);
4671 case TargetOpcode::G_SSUBE:
4672 return lowerSSUBE(MI);
4673 case TargetOpcode::G_UMULH:
4674 case TargetOpcode::G_SMULH:
4675 return lowerSMULH_UMULH(MI);
4676 case TargetOpcode::G_SMULO:
4677 case TargetOpcode::G_UMULO: {
4678 // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
4679 // result.
4680 auto [Res, Overflow, LHS, RHS] = MI.getFirst4Regs();
4681 LLT Ty = MRI.getType(Reg: Res);
4682
4683 unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
4684 ? TargetOpcode::G_SMULH
4685 : TargetOpcode::G_UMULH;
4686
4687 Observer.changingInstr(MI);
4688 const auto &TII = MIRBuilder.getTII();
4689 MI.setDesc(TII.get(Opcode: TargetOpcode::G_MUL));
4690 MI.removeOperand(OpNo: 1);
4691 Observer.changedInstr(MI);
4692
4693 auto HiPart = MIRBuilder.buildInstr(Opc: Opcode, DstOps: {Ty}, SrcOps: {LHS, RHS});
4694 auto Zero = MIRBuilder.buildConstant(Res: Ty, Val: 0);
4695
4696 // Move insert point forward so we can use the Res register if needed.
4697 MIRBuilder.setInsertPt(MBB&: MIRBuilder.getMBB(), II: ++MIRBuilder.getInsertPt());
4698
4699 // For *signed* multiply, overflow is detected by checking:
4700 // (hi != (lo >> bitwidth-1))
4701 if (Opcode == TargetOpcode::G_SMULH) {
4702 auto ShiftAmt = MIRBuilder.buildConstant(Res: Ty, Val: Ty.getSizeInBits() - 1);
4703 auto Shifted = MIRBuilder.buildAShr(Dst: Ty, Src0: Res, Src1: ShiftAmt);
4704 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_NE, Res: Overflow, Op0: HiPart, Op1: Shifted);
4705 } else {
4706 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_NE, Res: Overflow, Op0: HiPart, Op1: Zero);
4707 }
4708 return Legalized;
4709 }
4710 case TargetOpcode::G_FNEG: {
4711 auto [Res, ResTy, SubByReg, SubByRegTy] = MI.getFirst2RegLLTs();
4712 LLT TyInt =
4713 ResTy.changeElementType(NewEltTy: LLT::integer(SizeInBits: ResTy.getScalarSizeInBits()));
4714 Register CastedSubByReg = SubByReg;
4715
4716 if (!SubByRegTy.getScalarType().isAnyScalar() &&
4717 !SubByRegTy.getScalarType().isInteger()) {
4718 auto BitcastDst = SubByRegTy.changeElementType(
4719 NewEltTy: LLT::integer(SizeInBits: SubByRegTy.getScalarSizeInBits()));
4720 CastedSubByReg = MIRBuilder.buildBitcast(Dst: BitcastDst, Src: SubByReg).getReg(Idx: 0);
4721 }
4722
4723 auto SignMask = MIRBuilder.buildConstant(
4724 Res: TyInt, Val: APInt::getSignMask(BitWidth: TyInt.getScalarSizeInBits()));
4725
4726 if (ResTy != TyInt) {
4727 Register NewDst =
4728 MIRBuilder.buildXor(Dst: TyInt, Src0: CastedSubByReg, Src1: SignMask).getReg(Idx: 0);
4729 MIRBuilder.buildBitcast(Dst: Res, Src: NewDst);
4730 } else
4731 MIRBuilder.buildXor(Dst: Res, Src0: CastedSubByReg, Src1: SignMask).getReg(Idx: 0);
4732
4733 MI.eraseFromParent();
4734 return Legalized;
4735 }
4736 case TargetOpcode::G_FSUB:
4737 case TargetOpcode::G_STRICT_FSUB: {
4738 auto [Res, LHS, RHS] = MI.getFirst3Regs();
4739 LLT Ty = MRI.getType(Reg: Res);
4740
4741 // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
4742 auto Neg = MIRBuilder.buildFNeg(Dst: Ty, Src0: RHS);
4743
4744 if (MI.getOpcode() == TargetOpcode::G_STRICT_FSUB)
4745 MIRBuilder.buildStrictFAdd(Dst: Res, Src0: LHS, Src1: Neg, Flags: MI.getFlags());
4746 else
4747 MIRBuilder.buildFAdd(Dst: Res, Src0: LHS, Src1: Neg, Flags: MI.getFlags());
4748
4749 MI.eraseFromParent();
4750 return Legalized;
4751 }
4752 case TargetOpcode::G_FMAD:
4753 return lowerFMad(MI);
4754 case TargetOpcode::G_FFLOOR:
4755 return lowerFFloor(MI);
4756 case TargetOpcode::G_LROUND:
4757 case TargetOpcode::G_LLROUND: {
4758 Register DstReg = MI.getOperand(i: 0).getReg();
4759 Register SrcReg = MI.getOperand(i: 1).getReg();
4760 LLT SrcTy = MRI.getType(Reg: SrcReg);
4761 auto Round = MIRBuilder.buildInstr(Opc: TargetOpcode::G_INTRINSIC_ROUND, DstOps: {SrcTy},
4762 SrcOps: {SrcReg});
4763 MIRBuilder.buildFPTOSI(Dst: DstReg, Src0: Round);
4764 MI.eraseFromParent();
4765 return Legalized;
4766 }
4767 case TargetOpcode::G_INTRINSIC_ROUND:
4768 return lowerIntrinsicRound(MI);
4769 case TargetOpcode::G_FRINT: {
4770 // Since round even is the assumed rounding mode for unconstrained FP
4771 // operations, rint and roundeven are the same operation.
4772 changeOpcode(MI, NewOpcode: TargetOpcode::G_INTRINSIC_ROUNDEVEN);
4773 return Legalized;
4774 }
4775 case TargetOpcode::G_INTRINSIC_LRINT:
4776 case TargetOpcode::G_INTRINSIC_LLRINT: {
4777 Register DstReg = MI.getOperand(i: 0).getReg();
4778 Register SrcReg = MI.getOperand(i: 1).getReg();
4779 LLT SrcTy = MRI.getType(Reg: SrcReg);
4780 auto Round =
4781 MIRBuilder.buildInstr(Opc: TargetOpcode::G_FRINT, DstOps: {SrcTy}, SrcOps: {SrcReg});
4782 MIRBuilder.buildFPTOSI(Dst: DstReg, Src0: Round);
4783 MI.eraseFromParent();
4784 return Legalized;
4785 }
4786 case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
4787 auto [OldValRes, SuccessRes, Addr, CmpVal, NewVal] = MI.getFirst5Regs();
4788 Register NewOldValRes = MRI.cloneVirtualRegister(VReg: OldValRes);
4789 MIRBuilder.buildAtomicCmpXchg(OldValRes: NewOldValRes, Addr, CmpVal, NewVal,
4790 MMO&: **MI.memoperands_begin());
4791 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_EQ, Res: SuccessRes, Op0: NewOldValRes, Op1: CmpVal);
4792 MIRBuilder.buildCopy(Res: OldValRes, Op: NewOldValRes);
4793 MI.eraseFromParent();
4794 return Legalized;
4795 }
4796 case TargetOpcode::G_LOAD:
4797 case TargetOpcode::G_SEXTLOAD:
4798 case TargetOpcode::G_ZEXTLOAD:
4799 return lowerLoad(LoadMI&: cast<GAnyLoad>(Val&: MI));
4800 case TargetOpcode::G_STORE:
4801 return lowerStore(StoreMI&: cast<GStore>(Val&: MI));
4802 case TargetOpcode::G_CTLZ_ZERO_POISON:
4803 case TargetOpcode::G_CTTZ_ZERO_POISON:
4804 case TargetOpcode::G_CTLZ:
4805 case TargetOpcode::G_CTTZ:
4806 case TargetOpcode::G_CTPOP:
4807 case TargetOpcode::G_CTLS:
4808 return lowerBitCount(MI);
4809 case G_UADDO: {
4810 auto [Res, CarryOut, LHS, RHS] = MI.getFirst4Regs();
4811
4812 Register NewRes = MRI.cloneVirtualRegister(VReg: Res);
4813
4814 MIRBuilder.buildAdd(Dst: NewRes, Src0: LHS, Src1: RHS);
4815 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_ULT, Res: CarryOut, Op0: NewRes, Op1: RHS);
4816
4817 MIRBuilder.buildCopy(Res, Op: NewRes);
4818
4819 MI.eraseFromParent();
4820 return Legalized;
4821 }
4822 case G_UADDE: {
4823 auto [Res, CarryOut, LHS, RHS, CarryIn] = MI.getFirst5Regs();
4824 const LLT CondTy = MRI.getType(Reg: CarryOut);
4825 const LLT Ty = MRI.getType(Reg: Res);
4826
4827 Register NewRes = MRI.cloneVirtualRegister(VReg: Res);
4828
4829 // Initial add of the two operands.
4830 auto TmpRes = MIRBuilder.buildAdd(Dst: Ty, Src0: LHS, Src1: RHS);
4831
4832 // Initial check for carry.
4833 auto Carry = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_ULT, Res: CondTy, Op0: TmpRes, Op1: LHS);
4834
4835 // Add the sum and the carry.
4836 auto ZExtCarryIn = MIRBuilder.buildZExt(Res: Ty, Op: CarryIn);
4837 MIRBuilder.buildAdd(Dst: NewRes, Src0: TmpRes, Src1: ZExtCarryIn);
4838
4839 // Second check for carry. We can only carry if the initial sum is all 1s
4840 // and the carry is set, resulting in a new sum of 0.
4841 auto Zero = MIRBuilder.buildConstant(Res: Ty, Val: 0);
4842 auto ResEqZero =
4843 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_EQ, Res: CondTy, Op0: NewRes, Op1: Zero);
4844 auto Carry2 = MIRBuilder.buildAnd(Dst: CondTy, Src0: ResEqZero, Src1: CarryIn);
4845 MIRBuilder.buildOr(Dst: CarryOut, Src0: Carry, Src1: Carry2);
4846
4847 MIRBuilder.buildCopy(Res, Op: NewRes);
4848
4849 MI.eraseFromParent();
4850 return Legalized;
4851 }
4852 case G_USUBO: {
4853 auto [Res, BorrowOut, LHS, RHS] = MI.getFirst4Regs();
4854
4855 MIRBuilder.buildSub(Dst: Res, Src0: LHS, Src1: RHS);
4856 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_ULT, Res: BorrowOut, Op0: LHS, Op1: RHS);
4857
4858 MI.eraseFromParent();
4859 return Legalized;
4860 }
4861 case G_USUBE: {
4862 auto [Res, BorrowOut, LHS, RHS, BorrowIn] = MI.getFirst5Regs();
4863 const LLT CondTy = MRI.getType(Reg: BorrowOut);
4864 const LLT Ty = MRI.getType(Reg: Res);
4865
4866 // Initial subtract of the two operands.
4867 auto TmpRes = MIRBuilder.buildSub(Dst: Ty, Src0: LHS, Src1: RHS);
4868
4869 // Initial check for borrow.
4870 auto Borrow = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_UGT, Res: CondTy, Op0: TmpRes, Op1: LHS);
4871
4872 // Subtract the borrow from the first subtract.
4873 auto ZExtBorrowIn = MIRBuilder.buildZExt(Res: Ty, Op: BorrowIn);
4874 MIRBuilder.buildSub(Dst: Res, Src0: TmpRes, Src1: ZExtBorrowIn);
4875
4876 // Second check for borrow. We can only borrow if the initial difference is
4877 // 0 and the borrow is set, resulting in a new difference of all 1s.
4878 auto Zero = MIRBuilder.buildConstant(Res: Ty, Val: 0);
4879 auto TmpResEqZero =
4880 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_EQ, Res: CondTy, Op0: TmpRes, Op1: Zero);
4881 auto Borrow2 = MIRBuilder.buildAnd(Dst: CondTy, Src0: TmpResEqZero, Src1: BorrowIn);
4882 MIRBuilder.buildOr(Dst: BorrowOut, Src0: Borrow, Src1: Borrow2);
4883
4884 MI.eraseFromParent();
4885 return Legalized;
4886 }
4887 case G_UITOFP:
4888 return lowerUITOFP(MI);
4889 case G_SITOFP:
4890 return lowerSITOFP(MI);
4891 case G_FPTOUI:
4892 return lowerFPTOUI(MI);
4893 case G_FPTOSI:
4894 return lowerFPTOSI(MI);
4895 case G_FPTOUI_SAT:
4896 case G_FPTOSI_SAT:
4897 return lowerFPTOINT_SAT(MI);
4898 case G_FPEXT:
4899 return lowerFPEXT(MI);
4900 case G_FPTRUNC:
4901 return lowerFPTRUNC(MI);
4902 case G_FPOWI:
4903 return lowerFPOWI(MI);
4904 case G_FMODF:
4905 return lowerFMODF(MI);
4906 case G_SMIN:
4907 case G_SMAX:
4908 case G_UMIN:
4909 case G_UMAX:
4910 return lowerMinMax(MI);
4911 case G_SCMP:
4912 case G_UCMP:
4913 return lowerThreewayCompare(MI);
4914 case G_FCOPYSIGN:
4915 return lowerFCopySign(MI);
4916 case G_FMINNUM:
4917 case G_FMAXNUM:
4918 case G_FMINIMUMNUM:
4919 case G_FMAXIMUMNUM:
4920 return lowerFMinNumMaxNum(MI);
4921 case G_FMINIMUM:
4922 case G_FMAXIMUM:
4923 return lowerFMinimumMaximum(MI);
4924 case G_MERGE_VALUES:
4925 return lowerMergeValues(MI);
4926 case G_UNMERGE_VALUES:
4927 return lowerUnmergeValues(MI);
4928 case TargetOpcode::G_SEXT_INREG: {
4929 assert(MI.getOperand(2).isImm() && "Expected immediate");
4930 int64_t SizeInBits = MI.getOperand(i: 2).getImm();
4931
4932 auto [DstReg, SrcReg] = MI.getFirst2Regs();
4933 LLT DstTy = MRI.getType(Reg: DstReg);
4934 Register TmpRes = MRI.createGenericVirtualRegister(Ty: DstTy);
4935
4936 auto MIBSz = MIRBuilder.buildConstant(Res: DstTy, Val: DstTy.getScalarSizeInBits() - SizeInBits);
4937 MIRBuilder.buildShl(Dst: TmpRes, Src0: SrcReg, Src1: MIBSz->getOperand(i: 0));
4938 MIRBuilder.buildAShr(Dst: DstReg, Src0: TmpRes, Src1: MIBSz->getOperand(i: 0));
4939 MI.eraseFromParent();
4940 return Legalized;
4941 }
4942 case G_EXTRACT_VECTOR_ELT:
4943 case G_INSERT_VECTOR_ELT:
4944 return lowerExtractInsertVectorElt(MI);
4945 case G_SHUFFLE_VECTOR:
4946 return lowerShuffleVector(MI);
4947 case G_VECTOR_COMPRESS:
4948 return lowerVECTOR_COMPRESS(MI);
4949 case G_DYN_STACKALLOC:
4950 return lowerDynStackAlloc(MI);
4951 case G_INSERT_SUBVECTOR: {
4952 if (MRI.getType(Reg: MI.getOperand(i: 1).getReg()).isScalable() ||
4953 MRI.getType(Reg: MI.getOperand(i: 2).getReg()).isScalable())
4954 return UnableToLegalize;
4955
4956 // Check that subvector is half size of main vector
4957 Register Vector = MI.getOperand(i: 1).getReg();
4958 Register Subvector = MI.getOperand(i: 2).getReg();
4959 auto InsertionPointImm = MI.getOperand(i: 3).getImm();
4960
4961 LLT VectorTy = MRI.getType(Reg: Vector);
4962 LLT DstTy = MRI.getType(Reg: Subvector);
4963 // If so, -> concat(subvector, extract(half of vector))
4964 // (Operands can be either way round depending on insertion point
4965 if (VectorTy.getSizeInBits() == DstTy.getSizeInBits() * 2) {
4966 bool InsertInLowHalf = InsertionPointImm == 0;
4967 auto Extract = MIRBuilder.buildExtractSubvector(
4968 Res: DstTy, Src: Vector,
4969 Index: (uint64_t)(InsertInLowHalf ? VectorTy.getNumElements() / 2 : 0));
4970
4971 auto LowHalf = InsertInLowHalf ? Subvector : Extract.getReg(Idx: 0);
4972 auto HighHalf = InsertInLowHalf ? Extract.getReg(Idx: 0) : Subvector;
4973
4974 MIRBuilder.buildInstr(Opc: TargetOpcode::G_CONCAT_VECTORS, DstOps: {MI.getOperand(i: 0)},
4975 SrcOps: {LowHalf, HighHalf});
4976 MI.eraseFromParent();
4977 return Legalized;
4978 }
4979 // Else -> shuffle(vector, extend(subvector, size(vector)), mask)
4980 else {
4981 // Extend subvector to same size as vector
4982 Register ExtendedSubvector = MRI.createGenericVirtualRegister(Ty: VectorTy);
4983 MIRBuilder.buildPadVectorWithUndefElements(Res: ExtendedSubvector, Op0: Subvector);
4984
4985 // Calculate mask required for this shuffle
4986 SmallVector<int> Mask;
4987 for (int i = 0; i < VectorTy.getNumElements(); i++) {
4988 // If this index is within bounds, put subvector's index into mask
4989 if (i >= InsertionPointImm &&
4990 i < InsertionPointImm + DstTy.getNumElements())
4991 Mask.push_back(Elt: VectorTy.getNumElements() + i - InsertionPointImm);
4992 else
4993 Mask.push_back(Elt: i);
4994 }
4995
4996 // Build shuffle
4997 MIRBuilder.buildShuffleVector(Res: MI.getOperand(i: 0), Src1: Vector, Src2: ExtendedSubvector,
4998 Mask);
4999 MI.eraseFromParent();
5000 return Legalized;
5001 }
5002 }
5003 case G_EXTRACT_SUBVECTOR: {
5004 Register DstReg = MI.getOperand(i: 0).getReg();
5005 Register SrcReg = MI.getOperand(i: 1).getReg();
5006 uint64_t ExtractionPointImm = MI.getOperand(i: 2).getImm();
5007
5008 LLT SrcTy = MRI.getType(Reg: SrcReg);
5009 LLT DstTy = MRI.getType(Reg: DstReg);
5010
5011 if (SrcTy.isScalable() || DstTy.isScalable())
5012 return UnableToLegalize;
5013
5014 if (SrcTy.getScalarType() != DstTy.getScalarType())
5015 return UnableToLegalize;
5016
5017 // extract_subvector = build_vector(extract_element, extract_element, ...)
5018 SmallVector<Register> ExtractedElements;
5019 for (uint64_t i = 0; i < DstTy.getNumElements(); i++) {
5020 ExtractedElements.push_back(
5021 Elt: MIRBuilder
5022 .buildExtractVectorElementConstant(Res: SrcTy.getScalarType(), Val: SrcReg,
5023 Idx: ExtractionPointImm + i)
5024 .getReg(Idx: 0));
5025 }
5026
5027 MIRBuilder.buildBuildVector(Res: DstReg, Ops: ExtractedElements);
5028 MI.eraseFromParent();
5029 return Legalized;
5030 }
5031 case G_STACKSAVE:
5032 return lowerStackSave(MI);
5033 case G_STACKRESTORE:
5034 return lowerStackRestore(MI);
5035 case G_EXTRACT:
5036 return lowerExtract(MI);
5037 case G_INSERT:
5038 return lowerInsert(MI);
5039 case G_BSWAP:
5040 return lowerBswap(MI);
5041 case G_BITREVERSE:
5042 return lowerBitreverse(MI);
5043 case G_READ_REGISTER:
5044 case G_WRITE_REGISTER:
5045 return lowerReadWriteRegister(MI);
5046 case G_UADDSAT:
5047 case G_USUBSAT: {
5048 // Try to make a reasonable guess about which lowering strategy to use. The
5049 // target can override this with custom lowering and calling the
5050 // implementation functions.
5051 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
5052 if (LI.isLegalOrCustom(Query: {G_UMIN, Ty}))
5053 return lowerAddSubSatToMinMax(MI);
5054 return lowerAddSubSatToAddoSubo(MI);
5055 }
5056 case G_SADDSAT:
5057 case G_SSUBSAT: {
5058 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
5059
5060 // FIXME: It would probably make more sense to see if G_SADDO is preferred,
5061 // since it's a shorter expansion. However, we would need to figure out the
5062 // preferred boolean type for the carry out for the query.
5063 if (LI.isLegalOrCustom(Query: {G_SMIN, Ty}) && LI.isLegalOrCustom(Query: {G_SMAX, Ty}))
5064 return lowerAddSubSatToMinMax(MI);
5065 return lowerAddSubSatToAddoSubo(MI);
5066 }
5067 case G_SSHLSAT:
5068 case G_USHLSAT:
5069 return lowerShlSat(MI);
5070 case G_TRUNC_SSAT_S:
5071 case G_TRUNC_USAT_U:
5072 case G_TRUNC_SSAT_U:
5073 return lowerTruncSat(MI);
5074 case G_ABS:
5075 return lowerAbsToAddXor(MI);
5076 case G_ABDS:
5077 case G_ABDU: {
5078 bool IsSigned = MI.getOpcode() == G_ABDS;
5079 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
5080 if ((IsSigned && LI.isLegal(Query: {G_SMIN, Ty}) && LI.isLegal(Query: {G_SMAX, Ty})) ||
5081 (!IsSigned && LI.isLegal(Query: {G_UMIN, Ty}) && LI.isLegal(Query: {G_UMAX, Ty}))) {
5082 return lowerAbsDiffToMinMax(MI);
5083 }
5084 return lowerAbsDiffToSelect(MI);
5085 }
5086 case G_FABS:
5087 return lowerFAbs(MI);
5088 case G_SELECT:
5089 return lowerSelect(MI);
5090 case G_IS_FPCLASS:
5091 return lowerISFPCLASS(MI);
5092 case G_SDIVREM:
5093 case G_UDIVREM:
5094 return lowerDIVREM(MI);
5095 case G_FSHL:
5096 case G_FSHR:
5097 return lowerFunnelShift(MI);
5098 case G_ROTL:
5099 case G_ROTR:
5100 return lowerRotate(MI);
5101 case G_MEMSET:
5102 case G_MEMCPY:
5103 case G_MEMMOVE:
5104 case G_MEMCPY_INLINE:
5105 case G_MEMSET_INLINE:
5106 return lowerMemCpyFamily(MI);
5107 case G_ZEXT:
5108 case G_SEXT:
5109 case G_ANYEXT:
5110 return lowerEXT(MI);
5111 case G_TRUNC:
5112 return lowerTRUNC(MI);
5113 GISEL_VECREDUCE_CASES_NONSEQ
5114 return lowerVectorReduction(MI);
5115 case G_VAARG:
5116 return lowerVAArg(MI);
5117 case G_ATOMICRMW_SUB: {
5118 auto [Ret, Mem, Val] = MI.getFirst3Regs();
5119 const LLT ValTy = MRI.getType(Reg: Val);
5120 MachineMemOperand *MMO = *MI.memoperands_begin();
5121
5122 auto VNeg = MIRBuilder.buildNeg(Dst: ValTy, Src0: Val);
5123 MIRBuilder.buildAtomicRMW(Opcode: G_ATOMICRMW_ADD, OldValRes: Ret, Addr: Mem, Val: VNeg, MMO&: *MMO);
5124 MI.eraseFromParent();
5125 return Legalized;
5126 }
5127 case G_SMULFIX:
5128 case G_UMULFIX:
5129 case G_SMULFIXSAT:
5130 case G_UMULFIXSAT:
5131 return lowerMulfix(MI);
5132 }
5133}
5134
5135Align LegalizerHelper::getStackTemporaryAlignment(LLT Ty,
5136 Align MinAlign) const {
5137 // FIXME: We're missing a way to go back from LLT to llvm::Type to query the
5138 // datalayout for the preferred alignment. Also there should be a target hook
5139 // for this to allow targets to reduce the alignment and ignore the
5140 // datalayout. e.g. AMDGPU should always use a 4-byte alignment, regardless of
5141 // the type.
5142 return std::max(a: Align(PowerOf2Ceil(A: Ty.getSizeInBytes())), b: MinAlign);
5143}
5144
5145MachineInstrBuilder
5146LegalizerHelper::createStackTemporary(TypeSize Bytes, Align Alignment,
5147 MachinePointerInfo &PtrInfo) {
5148 MachineFunction &MF = MIRBuilder.getMF();
5149 const DataLayout &DL = MIRBuilder.getDataLayout();
5150 int FrameIdx = MF.getFrameInfo().CreateStackObject(Size: Bytes, Alignment, isSpillSlot: false);
5151
5152 unsigned AddrSpace = DL.getAllocaAddrSpace();
5153 LLT FramePtrTy = LLT::pointer(AddressSpace: AddrSpace, SizeInBits: DL.getPointerSizeInBits(AS: AddrSpace));
5154
5155 PtrInfo = MachinePointerInfo::getFixedStack(MF, FI: FrameIdx);
5156 return MIRBuilder.buildFrameIndex(Res: FramePtrTy, Idx: FrameIdx);
5157}
5158
5159MachineInstrBuilder LegalizerHelper::createStackStoreLoad(const DstOp &Res,
5160 const SrcOp &Val) {
5161 LLT SrcTy = Val.getLLTTy(MRI);
5162 Align StackTypeAlign =
5163 std::max(a: getStackTemporaryAlignment(Ty: SrcTy),
5164 b: getStackTemporaryAlignment(Ty: Res.getLLTTy(MRI)));
5165 MachinePointerInfo PtrInfo;
5166 auto StackTemp =
5167 createStackTemporary(Bytes: SrcTy.getSizeInBytes(), Alignment: StackTypeAlign, PtrInfo);
5168
5169 MIRBuilder.buildStore(Val, Addr: StackTemp, PtrInfo, Alignment: StackTypeAlign);
5170 return MIRBuilder.buildLoad(Res, Addr: StackTemp, PtrInfo, Alignment: StackTypeAlign);
5171}
5172
5173static Register clampVectorIndex(MachineIRBuilder &B, Register IdxReg,
5174 LLT VecTy) {
5175 LLT IdxTy = B.getMRI()->getType(Reg: IdxReg);
5176 unsigned NElts = VecTy.getNumElements();
5177
5178 int64_t IdxVal;
5179 if (mi_match(R: IdxReg, MRI: *B.getMRI(), P: m_ICst(Cst&: IdxVal))) {
5180 if (IdxVal < VecTy.getNumElements())
5181 return IdxReg;
5182 // If a constant index would be out of bounds, clamp it as well.
5183 }
5184
5185 if (isPowerOf2_32(Value: NElts)) {
5186 APInt Imm = APInt::getLowBitsSet(numBits: IdxTy.getSizeInBits(), loBitsSet: Log2_32(Value: NElts));
5187 return B.buildAnd(Dst: IdxTy, Src0: IdxReg, Src1: B.buildConstant(Res: IdxTy, Val: Imm)).getReg(Idx: 0);
5188 }
5189
5190 return B.buildUMin(Dst: IdxTy, Src0: IdxReg, Src1: B.buildConstant(Res: IdxTy, Val: NElts - 1))
5191 .getReg(Idx: 0);
5192}
5193
5194Register LegalizerHelper::getVectorElementPointer(Register VecPtr, LLT VecTy,
5195 Register Index) {
5196 LLT EltTy = VecTy.getElementType();
5197
5198 // Calculate the element offset and add it to the pointer.
5199 unsigned EltSize = EltTy.getSizeInBits() / 8; // FIXME: should be ABI size.
5200 assert(EltSize * 8 == EltTy.getSizeInBits() &&
5201 "Converting bits to bytes lost precision");
5202
5203 Index = clampVectorIndex(B&: MIRBuilder, IdxReg: Index, VecTy);
5204
5205 // Convert index to the correct size for the address space.
5206 const DataLayout &DL = MIRBuilder.getDataLayout();
5207 unsigned AS = MRI.getType(Reg: VecPtr).getAddressSpace();
5208 unsigned IndexSizeInBits = DL.getIndexSize(AS) * 8;
5209 LLT IdxTy = MRI.getType(Reg: Index).changeElementSize(NewEltSize: IndexSizeInBits);
5210 if (IdxTy != MRI.getType(Reg: Index))
5211 Index = MIRBuilder.buildSExtOrTrunc(Res: IdxTy, Op: Index).getReg(Idx: 0);
5212
5213 auto Mul = MIRBuilder.buildMul(Dst: IdxTy, Src0: Index,
5214 Src1: MIRBuilder.buildConstant(Res: IdxTy, Val: EltSize));
5215
5216 LLT PtrTy = MRI.getType(Reg: VecPtr);
5217 return MIRBuilder.buildPtrAdd(Res: PtrTy, Op0: VecPtr, Op1: Mul).getReg(Idx: 0);
5218}
5219
5220#ifndef NDEBUG
5221/// Check that all vector operands have same number of elements. Other operands
5222/// should be listed in NonVecOp.
5223static bool hasSameNumEltsOnAllVectorOperands(
5224 GenericMachineInstr &MI, MachineRegisterInfo &MRI,
5225 std::initializer_list<unsigned> NonVecOpIndices) {
5226 if (MI.getNumMemOperands() != 0)
5227 return false;
5228
5229 LLT VecTy = MRI.getType(MI.getReg(0));
5230 if (!VecTy.isVector())
5231 return false;
5232 unsigned NumElts = VecTy.getNumElements();
5233
5234 for (unsigned OpIdx = 1; OpIdx < MI.getNumOperands(); ++OpIdx) {
5235 MachineOperand &Op = MI.getOperand(OpIdx);
5236 if (!Op.isReg()) {
5237 if (!is_contained(NonVecOpIndices, OpIdx))
5238 return false;
5239 continue;
5240 }
5241
5242 LLT Ty = MRI.getType(Op.getReg());
5243 if (!Ty.isVector()) {
5244 if (!is_contained(NonVecOpIndices, OpIdx))
5245 return false;
5246 continue;
5247 }
5248
5249 if (Ty.getNumElements() != NumElts)
5250 return false;
5251 }
5252
5253 return true;
5254}
5255#endif
5256
5257/// Fill \p DstOps with DstOps that have same number of elements combined as
5258/// the Ty. These DstOps have either scalar type when \p NumElts = 1 or are
5259/// vectors with \p NumElts elements. When Ty.getNumElements() is not multiple
5260/// of \p NumElts last DstOp (leftover) has fewer then \p NumElts elements.
5261static void makeDstOps(SmallVectorImpl<DstOp> &DstOps, LLT Ty,
5262 unsigned NumElts) {
5263 LLT LeftoverTy;
5264 assert(Ty.isVector() && "Expected vector type");
5265 LLT NarrowTy = Ty.changeElementCount(EC: ElementCount::getFixed(MinVal: NumElts));
5266 int NumParts, NumLeftover;
5267 std::tie(args&: NumParts, args&: NumLeftover) =
5268 getNarrowTypeBreakDown(OrigTy: Ty, NarrowTy, LeftoverTy);
5269
5270 assert(NumParts > 0 && "Error in getNarrowTypeBreakDown");
5271 for (int i = 0; i < NumParts; ++i) {
5272 DstOps.push_back(Elt: NarrowTy);
5273 }
5274
5275 if (LeftoverTy.isValid()) {
5276 assert(NumLeftover == 1 && "expected exactly one leftover");
5277 DstOps.push_back(Elt: LeftoverTy);
5278 }
5279}
5280
5281/// Operand \p Op is used on \p N sub-instructions. Fill \p Ops with \p N SrcOps
5282/// made from \p Op depending on operand type.
5283static void broadcastSrcOp(SmallVectorImpl<SrcOp> &Ops, unsigned N,
5284 MachineOperand &Op) {
5285 for (unsigned i = 0; i < N; ++i) {
5286 if (Op.isReg())
5287 Ops.push_back(Elt: Op.getReg());
5288 else if (Op.isImm())
5289 Ops.push_back(Elt: Op.getImm());
5290 else if (Op.isPredicate())
5291 Ops.push_back(Elt: static_cast<CmpInst::Predicate>(Op.getPredicate()));
5292 else
5293 llvm_unreachable("Unsupported type");
5294 }
5295}
5296
5297// Handle splitting vector operations which need to have the same number of
5298// elements in each type index, but each type index may have a different element
5299// type.
5300//
5301// e.g. <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
5302// <2 x s64> = G_SHL <2 x s64>, <2 x s32>
5303// <2 x s64> = G_SHL <2 x s64>, <2 x s32>
5304//
5305// Also handles some irregular breakdown cases, e.g.
5306// e.g. <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
5307// <2 x s64> = G_SHL <2 x s64>, <2 x s32>
5308// s64 = G_SHL s64, s32
5309LegalizerHelper::LegalizeResult
5310LegalizerHelper::fewerElementsVectorMultiEltType(
5311 GenericMachineInstr &MI, unsigned NumElts,
5312 std::initializer_list<unsigned> NonVecOpIndices) {
5313 assert(hasSameNumEltsOnAllVectorOperands(MI, MRI, NonVecOpIndices) &&
5314 "Non-compatible opcode or not specified non-vector operands");
5315 unsigned OrigNumElts = MRI.getType(Reg: MI.getReg(Idx: 0)).getNumElements();
5316
5317 unsigned NumInputs = MI.getNumOperands() - MI.getNumDefs();
5318 unsigned NumDefs = MI.getNumDefs();
5319
5320 // Create DstOps (sub-vectors with NumElts elts + Leftover) for each output.
5321 // Build instructions with DstOps to use instruction found by CSE directly.
5322 // CSE copies found instruction into given vreg when building with vreg dest.
5323 SmallVector<SmallVector<DstOp, 8>, 2> OutputOpsPieces(NumDefs);
5324 // Output registers will be taken from created instructions.
5325 SmallVector<SmallVector<Register, 8>, 2> OutputRegs(NumDefs);
5326 for (unsigned i = 0; i < NumDefs; ++i) {
5327 makeDstOps(DstOps&: OutputOpsPieces[i], Ty: MRI.getType(Reg: MI.getReg(Idx: i)), NumElts);
5328 }
5329
5330 // Split vector input operands into sub-vectors with NumElts elts + Leftover.
5331 // Operands listed in NonVecOpIndices will be used as is without splitting;
5332 // examples: compare predicate in icmp and fcmp (op 1), vector select with i1
5333 // scalar condition (op 1), immediate in sext_inreg (op 2).
5334 SmallVector<SmallVector<SrcOp, 8>, 3> InputOpsPieces(NumInputs);
5335 for (unsigned UseIdx = NumDefs, UseNo = 0; UseIdx < MI.getNumOperands();
5336 ++UseIdx, ++UseNo) {
5337 if (is_contained(Set: NonVecOpIndices, Element: UseIdx)) {
5338 broadcastSrcOp(Ops&: InputOpsPieces[UseNo], N: OutputOpsPieces[0].size(),
5339 Op&: MI.getOperand(i: UseIdx));
5340 } else {
5341 SmallVector<Register, 8> SplitPieces;
5342 extractVectorParts(Reg: MI.getReg(Idx: UseIdx), NumElts, VRegs&: SplitPieces, MIRBuilder,
5343 MRI);
5344 llvm::append_range(C&: InputOpsPieces[UseNo], R&: SplitPieces);
5345 }
5346 }
5347
5348 unsigned NumLeftovers = OrigNumElts % NumElts ? 1 : 0;
5349
5350 // Take i-th piece of each input operand split and build sub-vector/scalar
5351 // instruction. Set i-th DstOp(s) from OutputOpsPieces as destination(s).
5352 for (unsigned i = 0; i < OrigNumElts / NumElts + NumLeftovers; ++i) {
5353 SmallVector<DstOp, 2> Defs;
5354 for (unsigned DstNo = 0; DstNo < NumDefs; ++DstNo)
5355 Defs.push_back(Elt: OutputOpsPieces[DstNo][i]);
5356
5357 SmallVector<SrcOp, 3> Uses;
5358 for (unsigned InputNo = 0; InputNo < NumInputs; ++InputNo)
5359 Uses.push_back(Elt: InputOpsPieces[InputNo][i]);
5360
5361 auto I = MIRBuilder.buildInstr(Opc: MI.getOpcode(), DstOps: Defs, SrcOps: Uses, Flags: MI.getFlags());
5362 for (unsigned DstNo = 0; DstNo < NumDefs; ++DstNo)
5363 OutputRegs[DstNo].push_back(Elt: I.getReg(Idx: DstNo));
5364 }
5365
5366 // Merge small outputs into MI's output for each def operand.
5367 if (NumLeftovers) {
5368 for (unsigned i = 0; i < NumDefs; ++i)
5369 mergeMixedSubvectors(DstReg: MI.getReg(Idx: i), PartRegs: OutputRegs[i]);
5370 } else {
5371 for (unsigned i = 0; i < NumDefs; ++i)
5372 MIRBuilder.buildMergeLikeInstr(Res: MI.getReg(Idx: i), Ops: OutputRegs[i]);
5373 }
5374
5375 MI.eraseFromParent();
5376 return Legalized;
5377}
5378
5379LegalizerHelper::LegalizeResult
5380LegalizerHelper::fewerElementsVectorPhi(GenericMachineInstr &MI,
5381 unsigned NumElts) {
5382 unsigned OrigNumElts = MRI.getType(Reg: MI.getReg(Idx: 0)).getNumElements();
5383
5384 unsigned NumInputs = MI.getNumOperands() - MI.getNumDefs();
5385 unsigned NumDefs = MI.getNumDefs();
5386
5387 SmallVector<DstOp, 8> OutputOpsPieces;
5388 SmallVector<Register, 8> OutputRegs;
5389 makeDstOps(DstOps&: OutputOpsPieces, Ty: MRI.getType(Reg: MI.getReg(Idx: 0)), NumElts);
5390
5391 // Instructions that perform register split will be inserted in basic block
5392 // where register is defined (basic block is in the next operand).
5393 SmallVector<SmallVector<Register, 8>, 3> InputOpsPieces(NumInputs / 2);
5394 for (unsigned UseIdx = NumDefs, UseNo = 0; UseIdx < MI.getNumOperands();
5395 UseIdx += 2, ++UseNo) {
5396 MachineBasicBlock &OpMBB = *MI.getOperand(i: UseIdx + 1).getMBB();
5397 MIRBuilder.setInsertPt(MBB&: OpMBB, II: OpMBB.getFirstTerminatorForward());
5398 extractVectorParts(Reg: MI.getReg(Idx: UseIdx), NumElts, VRegs&: InputOpsPieces[UseNo],
5399 MIRBuilder, MRI);
5400 }
5401
5402 // Build PHIs with fewer elements.
5403 unsigned NumLeftovers = OrigNumElts % NumElts ? 1 : 0;
5404 MIRBuilder.setInsertPt(MBB&: *MI.getParent(), II: MI);
5405 for (unsigned i = 0; i < OrigNumElts / NumElts + NumLeftovers; ++i) {
5406 auto Phi = MIRBuilder.buildInstr(Opcode: TargetOpcode::G_PHI);
5407 Phi.addDef(
5408 RegNo: MRI.createGenericVirtualRegister(Ty: OutputOpsPieces[i].getLLTTy(MRI)));
5409 OutputRegs.push_back(Elt: Phi.getReg(Idx: 0));
5410
5411 for (unsigned j = 0; j < NumInputs / 2; ++j) {
5412 Phi.addUse(RegNo: InputOpsPieces[j][i]);
5413 Phi.add(MO: MI.getOperand(i: 1 + j * 2 + 1));
5414 }
5415 }
5416
5417 // Set the insert point after the existing PHIs
5418 MachineBasicBlock &MBB = *MI.getParent();
5419 MIRBuilder.setInsertPt(MBB, II: MBB.getFirstNonPHI());
5420
5421 // Merge small outputs into MI's def.
5422 if (NumLeftovers) {
5423 mergeMixedSubvectors(DstReg: MI.getReg(Idx: 0), PartRegs: OutputRegs);
5424 } else {
5425 MIRBuilder.buildMergeLikeInstr(Res: MI.getReg(Idx: 0), Ops: OutputRegs);
5426 }
5427
5428 MI.eraseFromParent();
5429 return Legalized;
5430}
5431
5432LegalizerHelper::LegalizeResult
5433LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI,
5434 unsigned TypeIdx,
5435 LLT NarrowTy) {
5436 const int NumDst = MI.getNumOperands() - 1;
5437 const Register SrcReg = MI.getOperand(i: NumDst).getReg();
5438 LLT DstTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
5439 LLT SrcTy = MRI.getType(Reg: SrcReg);
5440
5441 if (TypeIdx != 1 || NarrowTy == DstTy)
5442 return UnableToLegalize;
5443
5444 // Requires compatible types. Otherwise SrcReg should have been defined by
5445 // merge-like instruction that would get artifact combined. Most likely
5446 // instruction that defines SrcReg has to perform more/fewer elements
5447 // legalization compatible with NarrowTy.
5448 assert(SrcTy.isVector() && NarrowTy.isVector() && "Expected vector types");
5449 assert((SrcTy.getScalarType() == NarrowTy.getScalarType()) && "bad type");
5450
5451 if ((SrcTy.getSizeInBits() % NarrowTy.getSizeInBits() != 0) ||
5452 (NarrowTy.getSizeInBits() % DstTy.getSizeInBits() != 0))
5453 return UnableToLegalize;
5454
5455 // This is most likely DstTy (smaller then register size) packed in SrcTy
5456 // (larger then register size) and since unmerge was not combined it will be
5457 // lowered to bit sequence extracts from register. Unpack SrcTy to NarrowTy
5458 // (register size) pieces first. Then unpack each of NarrowTy pieces to DstTy.
5459
5460 // %1:_(DstTy), %2, %3, %4 = G_UNMERGE_VALUES %0:_(SrcTy)
5461 //
5462 // %5:_(NarrowTy), %6 = G_UNMERGE_VALUES %0:_(SrcTy) - reg sequence
5463 // %1:_(DstTy), %2 = G_UNMERGE_VALUES %5:_(NarrowTy) - sequence of bits in reg
5464 // %3:_(DstTy), %4 = G_UNMERGE_VALUES %6:_(NarrowTy)
5465 auto Unmerge = MIRBuilder.buildUnmerge(Res: NarrowTy, Op: SrcReg);
5466 const int NumUnmerge = Unmerge->getNumOperands() - 1;
5467 const int PartsPerUnmerge = NumDst / NumUnmerge;
5468
5469 for (int I = 0; I != NumUnmerge; ++I) {
5470 auto MIB = MIRBuilder.buildInstr(Opcode: TargetOpcode::G_UNMERGE_VALUES);
5471
5472 for (int J = 0; J != PartsPerUnmerge; ++J)
5473 MIB.addDef(RegNo: MI.getOperand(i: I * PartsPerUnmerge + J).getReg());
5474 MIB.addUse(RegNo: Unmerge.getReg(Idx: I));
5475 }
5476
5477 MI.eraseFromParent();
5478 return Legalized;
5479}
5480
5481LegalizerHelper::LegalizeResult
5482LegalizerHelper::fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx,
5483 LLT NarrowTy) {
5484 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
5485 // Requires compatible types. Otherwise user of DstReg did not perform unmerge
5486 // that should have been artifact combined. Most likely instruction that uses
5487 // DstReg has to do more/fewer elements legalization compatible with NarrowTy.
5488 assert(DstTy.isVector() && NarrowTy.isVector() && "Expected vector types");
5489 assert((DstTy.getScalarType() == NarrowTy.getScalarType()) && "bad type");
5490 if (NarrowTy == SrcTy)
5491 return UnableToLegalize;
5492
5493 // This attempts to lower part of LCMTy merge/unmerge sequence. Intended use
5494 // is for old mir tests. Since the changes to more/fewer elements it should no
5495 // longer be possible to generate MIR like this when starting from llvm-ir
5496 // because LCMTy approach was replaced with merge/unmerge to vector elements.
5497 if (TypeIdx == 1) {
5498 assert(SrcTy.isVector() && "Expected vector types");
5499 assert((SrcTy.getScalarType() == NarrowTy.getScalarType()) && "bad type");
5500 if ((DstTy.getSizeInBits() % NarrowTy.getSizeInBits() != 0) ||
5501 (NarrowTy.getNumElements() >= SrcTy.getNumElements()))
5502 return UnableToLegalize;
5503 // %2:_(DstTy) = G_CONCAT_VECTORS %0:_(SrcTy), %1:_(SrcTy)
5504 //
5505 // %3:_(EltTy), %4, %5 = G_UNMERGE_VALUES %0:_(SrcTy)
5506 // %6:_(EltTy), %7, %8 = G_UNMERGE_VALUES %1:_(SrcTy)
5507 // %9:_(NarrowTy) = G_BUILD_VECTOR %3:_(EltTy), %4
5508 // %10:_(NarrowTy) = G_BUILD_VECTOR %5:_(EltTy), %6
5509 // %11:_(NarrowTy) = G_BUILD_VECTOR %7:_(EltTy), %8
5510 // %2:_(DstTy) = G_CONCAT_VECTORS %9:_(NarrowTy), %10, %11
5511
5512 SmallVector<Register, 8> Elts;
5513 LLT EltTy = MRI.getType(Reg: MI.getOperand(i: 1).getReg()).getScalarType();
5514 for (unsigned i = 1; i < MI.getNumOperands(); ++i) {
5515 auto Unmerge = MIRBuilder.buildUnmerge(Res: EltTy, Op: MI.getOperand(i).getReg());
5516 for (unsigned j = 0; j < Unmerge->getNumDefs(); ++j)
5517 Elts.push_back(Elt: Unmerge.getReg(Idx: j));
5518 }
5519
5520 SmallVector<Register, 8> NarrowTyElts;
5521 unsigned NumNarrowTyElts = NarrowTy.getNumElements();
5522 unsigned NumNarrowTyPieces = DstTy.getNumElements() / NumNarrowTyElts;
5523 for (unsigned i = 0, Offset = 0; i < NumNarrowTyPieces;
5524 ++i, Offset += NumNarrowTyElts) {
5525 ArrayRef<Register> Pieces(&Elts[Offset], NumNarrowTyElts);
5526 NarrowTyElts.push_back(
5527 Elt: MIRBuilder.buildMergeLikeInstr(Res: NarrowTy, Ops: Pieces).getReg(Idx: 0));
5528 }
5529
5530 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: NarrowTyElts);
5531 MI.eraseFromParent();
5532 return Legalized;
5533 }
5534
5535 assert(TypeIdx == 0 && "Bad type index");
5536 if ((NarrowTy.getSizeInBits() % SrcTy.getSizeInBits() != 0) ||
5537 (DstTy.getSizeInBits() % NarrowTy.getSizeInBits() != 0))
5538 return UnableToLegalize;
5539
5540 // This is most likely SrcTy (smaller then register size) packed in DstTy
5541 // (larger then register size) and since merge was not combined it will be
5542 // lowered to bit sequence packing into register. Merge SrcTy to NarrowTy
5543 // (register size) pieces first. Then merge each of NarrowTy pieces to DstTy.
5544
5545 // %0:_(DstTy) = G_MERGE_VALUES %1:_(SrcTy), %2, %3, %4
5546 //
5547 // %5:_(NarrowTy) = G_MERGE_VALUES %1:_(SrcTy), %2 - sequence of bits in reg
5548 // %6:_(NarrowTy) = G_MERGE_VALUES %3:_(SrcTy), %4
5549 // %0:_(DstTy) = G_MERGE_VALUES %5:_(NarrowTy), %6 - reg sequence
5550 SmallVector<Register, 8> NarrowTyElts;
5551 unsigned NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
5552 unsigned NumSrcElts = SrcTy.isVector() ? SrcTy.getNumElements() : 1;
5553 unsigned NumElts = NarrowTy.getNumElements() / NumSrcElts;
5554 for (unsigned i = 0; i < NumParts; ++i) {
5555 SmallVector<Register, 8> Sources;
5556 for (unsigned j = 0; j < NumElts; ++j)
5557 Sources.push_back(Elt: MI.getOperand(i: 1 + i * NumElts + j).getReg());
5558 NarrowTyElts.push_back(
5559 Elt: MIRBuilder.buildMergeLikeInstr(Res: NarrowTy, Ops: Sources).getReg(Idx: 0));
5560 }
5561
5562 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: NarrowTyElts);
5563 MI.eraseFromParent();
5564 return Legalized;
5565}
5566
5567LegalizerHelper::LegalizeResult
5568LegalizerHelper::fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI,
5569 unsigned TypeIdx,
5570 LLT NarrowVecTy) {
5571 auto [DstReg, SrcVec] = MI.getFirst2Regs();
5572 Register InsertVal;
5573 bool IsInsert = MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT;
5574
5575 assert((IsInsert ? TypeIdx == 0 : TypeIdx == 1) && "not a vector type index");
5576 if (IsInsert)
5577 InsertVal = MI.getOperand(i: 2).getReg();
5578
5579 Register Idx = MI.getOperand(i: MI.getNumOperands() - 1).getReg();
5580 LLT VecTy = MRI.getType(Reg: SrcVec);
5581
5582 // If the index is a constant, we can really break this down as you would
5583 // expect, and index into the target size pieces.
5584 auto MaybeCst = getIConstantVRegValWithLookThrough(VReg: Idx, MRI);
5585 if (MaybeCst) {
5586 uint64_t IdxVal = MaybeCst->Value.getZExtValue();
5587 // Avoid out of bounds indexing the pieces.
5588 if (IdxVal >= VecTy.getNumElements()) {
5589 MIRBuilder.buildUndef(Res: DstReg);
5590 MI.eraseFromParent();
5591 return Legalized;
5592 }
5593
5594 if (!NarrowVecTy.isVector()) {
5595 SmallVector<Register, 8> SplitPieces;
5596 extractParts(Reg: MI.getOperand(i: 1).getReg(), Ty: NarrowVecTy,
5597 NumParts: VecTy.getNumElements(), VRegs&: SplitPieces, MIRBuilder, MRI);
5598 if (IsInsert) {
5599 SplitPieces[IdxVal] = InsertVal;
5600 MIRBuilder.buildMergeLikeInstr(Res: MI.getOperand(i: 0).getReg(), Ops: SplitPieces);
5601 } else {
5602 MIRBuilder.buildCopy(Res: MI.getOperand(i: 0).getReg(), Op: SplitPieces[IdxVal]);
5603 }
5604 } else {
5605 SmallVector<Register, 8> VecParts;
5606 LLT GCDTy = extractGCDType(Parts&: VecParts, DstTy: VecTy, NarrowTy: NarrowVecTy, SrcReg: SrcVec);
5607
5608 // Build a sequence of NarrowTy pieces in VecParts for this operand.
5609 LLT LCMTy = buildLCMMergePieces(DstTy: VecTy, NarrowTy: NarrowVecTy, GCDTy, VRegs&: VecParts,
5610 PadStrategy: TargetOpcode::G_ANYEXT);
5611
5612 unsigned NewNumElts = NarrowVecTy.getNumElements();
5613
5614 LLT IdxTy = MRI.getType(Reg: Idx);
5615 int64_t PartIdx = IdxVal / NewNumElts;
5616 auto NewIdx =
5617 MIRBuilder.buildConstant(Res: IdxTy, Val: IdxVal - NewNumElts * PartIdx);
5618
5619 if (IsInsert) {
5620 LLT PartTy = MRI.getType(Reg: VecParts[PartIdx]);
5621
5622 // Use the adjusted index to insert into one of the subvectors.
5623 auto InsertPart = MIRBuilder.buildInsertVectorElement(
5624 Res: PartTy, Val: VecParts[PartIdx], Elt: InsertVal, Idx: NewIdx);
5625 VecParts[PartIdx] = InsertPart.getReg(Idx: 0);
5626
5627 // Recombine the inserted subvector with the others to reform the result
5628 // vector.
5629 buildWidenedRemergeToDst(DstReg, LCMTy, RemergeRegs: VecParts);
5630 } else {
5631 MIRBuilder.buildExtractVectorElement(Res: DstReg, Val: VecParts[PartIdx], Idx: NewIdx);
5632 }
5633 }
5634
5635 MI.eraseFromParent();
5636 return Legalized;
5637 }
5638
5639 // With a variable index, we can't perform the operation in a smaller type, so
5640 // we're forced to expand this.
5641 //
5642 // TODO: We could emit a chain of compare/select to figure out which piece to
5643 // index.
5644 return lowerExtractInsertVectorElt(MI);
5645}
5646
5647LegalizerHelper::LegalizeResult
5648LegalizerHelper::reduceLoadStoreWidth(GLoadStore &LdStMI, unsigned TypeIdx,
5649 LLT NarrowTy) {
5650 // FIXME: Don't know how to handle secondary types yet.
5651 if (TypeIdx != 0)
5652 return UnableToLegalize;
5653
5654 if (!NarrowTy.isByteSized()) {
5655 LLVM_DEBUG(dbgs() << "Can't narrow load/store to non-byte-sized type\n");
5656 return UnableToLegalize;
5657 }
5658
5659 // This implementation doesn't work for atomics. Give up instead of doing
5660 // something invalid.
5661 if (LdStMI.isAtomic())
5662 return UnableToLegalize;
5663
5664 bool IsLoad = isa<GLoad>(Val: LdStMI);
5665 Register ValReg = LdStMI.getReg(Idx: 0);
5666 Register AddrReg = LdStMI.getPointerReg();
5667 LLT ValTy = MRI.getType(Reg: ValReg);
5668
5669 // FIXME: Do we need a distinct NarrowMemory legalize action?
5670 if (ValTy.getSizeInBits() != 8 * LdStMI.getMemSize().getValue()) {
5671 LLVM_DEBUG(dbgs() << "Can't narrow extload/truncstore\n");
5672 return UnableToLegalize;
5673 }
5674
5675 int NumParts = -1;
5676 int NumLeftover = -1;
5677 LLT LeftoverTy;
5678 SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs;
5679 if (IsLoad) {
5680 std::tie(args&: NumParts, args&: NumLeftover) = getNarrowTypeBreakDown(OrigTy: ValTy, NarrowTy, LeftoverTy);
5681 } else {
5682 if (extractParts(Reg: ValReg, RegTy: ValTy, MainTy: NarrowTy, LeftoverTy, VRegs&: NarrowRegs,
5683 LeftoverVRegs&: NarrowLeftoverRegs, MIRBuilder, MRI)) {
5684 NumParts = NarrowRegs.size();
5685 NumLeftover = NarrowLeftoverRegs.size();
5686 }
5687 }
5688
5689 if (NumParts == -1)
5690 return UnableToLegalize;
5691
5692 LLT PtrTy = MRI.getType(Reg: AddrReg);
5693 const LLT OffsetTy = LLT::integer(SizeInBits: PtrTy.getSizeInBits());
5694
5695 unsigned TotalSize = ValTy.getSizeInBits();
5696
5697 // Split the load/store into PartTy sized pieces starting at Offset. If this
5698 // is a load, return the new registers in ValRegs. For a store, each elements
5699 // of ValRegs should be PartTy. Returns the next offset that needs to be
5700 // handled.
5701 bool isBigEndian = MIRBuilder.getDataLayout().isBigEndian();
5702 auto MMO = LdStMI.getMMO();
5703 auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
5704 unsigned NumParts, unsigned Offset) -> unsigned {
5705 MachineFunction &MF = MIRBuilder.getMF();
5706 unsigned PartSize = PartTy.getSizeInBits();
5707 for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
5708 ++Idx) {
5709 unsigned ByteOffset = Offset / 8;
5710 Register NewAddrReg;
5711
5712 MIRBuilder.materializeObjectPtrOffset(Res&: NewAddrReg, Op0: AddrReg, ValueTy: OffsetTy,
5713 Value: ByteOffset);
5714
5715 MachineMemOperand *NewMMO =
5716 MF.getMachineMemOperand(MMO: &MMO, Offset: ByteOffset, Ty: PartTy);
5717
5718 if (IsLoad) {
5719 Register Dst = MRI.createGenericVirtualRegister(Ty: PartTy);
5720 ValRegs.push_back(Elt: Dst);
5721 MIRBuilder.buildLoad(Res: Dst, Addr: NewAddrReg, MMO&: *NewMMO);
5722 } else {
5723 MIRBuilder.buildStore(Val: ValRegs[Idx], Addr: NewAddrReg, MMO&: *NewMMO);
5724 }
5725 Offset = isBigEndian ? Offset - PartSize : Offset + PartSize;
5726 }
5727
5728 return Offset;
5729 };
5730
5731 unsigned Offset = isBigEndian ? TotalSize - NarrowTy.getSizeInBits() : 0;
5732 unsigned HandledOffset =
5733 splitTypePieces(NarrowTy, NarrowRegs, NumParts, Offset);
5734
5735 // Handle the rest of the register if this isn't an even type breakdown.
5736 if (LeftoverTy.isValid())
5737 splitTypePieces(LeftoverTy, NarrowLeftoverRegs, NumLeftover, HandledOffset);
5738
5739 if (IsLoad) {
5740 insertParts(DstReg: ValReg, ResultTy: ValTy, PartTy: NarrowTy, PartRegs: NarrowRegs,
5741 LeftoverTy, LeftoverRegs: NarrowLeftoverRegs);
5742 }
5743
5744 LdStMI.eraseFromParent();
5745 return Legalized;
5746}
5747
5748LegalizerHelper::LegalizeResult
5749LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
5750 LLT NarrowTy) {
5751 using namespace TargetOpcode;
5752 GenericMachineInstr &GMI = cast<GenericMachineInstr>(Val&: MI);
5753 unsigned NumElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
5754
5755 switch (MI.getOpcode()) {
5756 case G_IMPLICIT_DEF:
5757 case G_TRUNC:
5758 case G_AND:
5759 case G_OR:
5760 case G_XOR:
5761 case G_ADD:
5762 case G_SUB:
5763 case G_MUL:
5764 case G_PTR_ADD:
5765 case G_SMULH:
5766 case G_UMULH:
5767 case G_FADD:
5768 case G_FMUL:
5769 case G_FSUB:
5770 case G_FNEG:
5771 case G_FABS:
5772 case G_FCANONICALIZE:
5773 case G_FDIV:
5774 case G_FREM:
5775 case G_FMA:
5776 case G_FMAD:
5777 case G_FPOW:
5778 case G_FEXP:
5779 case G_FEXP2:
5780 case G_FEXP10:
5781 case G_FLOG:
5782 case G_FLOG2:
5783 case G_FLOG10:
5784 case G_FLDEXP:
5785 case G_FNEARBYINT:
5786 case G_FCEIL:
5787 case G_FFLOOR:
5788 case G_FRINT:
5789 case G_INTRINSIC_LRINT:
5790 case G_INTRINSIC_LLRINT:
5791 case G_INTRINSIC_ROUND:
5792 case G_INTRINSIC_ROUNDEVEN:
5793 case G_LROUND:
5794 case G_LLROUND:
5795 case G_INTRINSIC_TRUNC:
5796 case G_FMODF:
5797 case G_FCOS:
5798 case G_FSIN:
5799 case G_FTAN:
5800 case G_FACOS:
5801 case G_FASIN:
5802 case G_FATAN:
5803 case G_FATAN2:
5804 case G_FCOSH:
5805 case G_FSINH:
5806 case G_FTANH:
5807 case G_FSQRT:
5808 case G_BSWAP:
5809 case G_BITREVERSE:
5810 case G_SDIV:
5811 case G_UDIV:
5812 case G_SREM:
5813 case G_UREM:
5814 case G_SDIVREM:
5815 case G_UDIVREM:
5816 case G_SMIN:
5817 case G_SMAX:
5818 case G_UMIN:
5819 case G_UMAX:
5820 case G_ABS:
5821 case G_FMINNUM:
5822 case G_FMAXNUM:
5823 case G_FMINNUM_IEEE:
5824 case G_FMAXNUM_IEEE:
5825 case G_FMINIMUM:
5826 case G_FMAXIMUM:
5827 case G_FMINIMUMNUM:
5828 case G_FMAXIMUMNUM:
5829 case G_FSHL:
5830 case G_FSHR:
5831 case G_ROTL:
5832 case G_ROTR:
5833 case G_FREEZE:
5834 case G_SADDSAT:
5835 case G_SSUBSAT:
5836 case G_UADDSAT:
5837 case G_USUBSAT:
5838 case G_UMULO:
5839 case G_SMULO:
5840 case G_SHL:
5841 case G_LSHR:
5842 case G_ASHR:
5843 case G_SSHLSAT:
5844 case G_USHLSAT:
5845 case G_CTLZ:
5846 case G_CTLZ_ZERO_POISON:
5847 case G_CTTZ:
5848 case G_CTTZ_ZERO_POISON:
5849 case G_CTPOP:
5850 case G_CTLS:
5851 case G_FCOPYSIGN:
5852 case G_ZEXT:
5853 case G_SEXT:
5854 case G_ANYEXT:
5855 case G_FPEXT:
5856 case G_FPTRUNC:
5857 case G_SITOFP:
5858 case G_UITOFP:
5859 case G_FPTOSI:
5860 case G_FPTOUI:
5861 case G_FPTOSI_SAT:
5862 case G_FPTOUI_SAT:
5863 case G_INTTOPTR:
5864 case G_PTRTOINT:
5865 case G_ADDRSPACE_CAST:
5866 case G_UADDO:
5867 case G_USUBO:
5868 case G_UADDE:
5869 case G_USUBE:
5870 case G_SADDO:
5871 case G_SSUBO:
5872 case G_SADDE:
5873 case G_SSUBE:
5874 case G_STRICT_FADD:
5875 case G_STRICT_FSUB:
5876 case G_STRICT_FMUL:
5877 case G_STRICT_FMA:
5878 case G_STRICT_FLDEXP:
5879 case G_FFREXP:
5880 case G_TRUNC_SSAT_S:
5881 case G_TRUNC_SSAT_U:
5882 case G_TRUNC_USAT_U:
5883 return fewerElementsVectorMultiEltType(MI&: GMI, NumElts);
5884 case G_ICMP:
5885 case G_FCMP:
5886 return fewerElementsVectorMultiEltType(MI&: GMI, NumElts, NonVecOpIndices: {1 /*cpm predicate*/});
5887 case G_IS_FPCLASS:
5888 return fewerElementsVectorMultiEltType(MI&: GMI, NumElts, NonVecOpIndices: {2, 3 /*mask,fpsem*/});
5889 case G_SELECT:
5890 if (MRI.getType(Reg: MI.getOperand(i: 1).getReg()).isVector())
5891 return fewerElementsVectorMultiEltType(MI&: GMI, NumElts);
5892 return fewerElementsVectorMultiEltType(MI&: GMI, NumElts, NonVecOpIndices: {1 /*scalar cond*/});
5893 case G_PHI:
5894 return fewerElementsVectorPhi(MI&: GMI, NumElts);
5895 case G_UNMERGE_VALUES:
5896 return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy);
5897 case G_BUILD_VECTOR:
5898 assert(TypeIdx == 0 && "not a vector type index");
5899 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy);
5900 case G_CONCAT_VECTORS:
5901 if (TypeIdx != 1) // TODO: This probably does work as expected already.
5902 return UnableToLegalize;
5903 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy);
5904 case G_EXTRACT_SUBVECTOR: {
5905 Register DstReg = MI.getOperand(i: 0).getReg();
5906 LLT DstTy = MRI.getType(Reg: DstReg);
5907 Register SrcReg = MI.getOperand(i: 1).getReg();
5908 uint64_t InsertionPointImm = MI.getOperand(i: 2).getImm();
5909
5910 // If Dst > NarrowTy bits, then cannot legalize
5911 if (DstTy.getSizeInBits() > NarrowTy.getSizeInBits())
5912 return UnableToLegalize;
5913
5914 // If DstTy's size is not a multiple of NarrowTy's, then cannot legalize
5915 if (!DstTy.getElementCount().isKnownMultipleOf(RHS: NarrowTy.getElementCount()))
5916 return UnableToLegalize;
5917
5918 auto Unmerge = MIRBuilder.buildUnmerge(Res: NarrowTy, Op: SrcReg);
5919 uint64_t RequiredSubvectorIndex =
5920 InsertionPointImm / NarrowTy.getNumElements();
5921 // If Dst and Narrow are both same size, convert to a copy
5922 if (DstTy.getNumElements() == NarrowTy.getNumElements())
5923 MIRBuilder.buildCopy(Res: DstReg, Op: Unmerge.getReg(Idx: RequiredSubvectorIndex));
5924 else
5925 MIRBuilder.buildExtractSubvector(
5926 Res: DstReg, Src: Unmerge.getReg(Idx: RequiredSubvectorIndex),
5927 Index: InsertionPointImm % NarrowTy.getNumElements());
5928
5929 MI.eraseFromParent();
5930 return Legalized;
5931 }
5932 case G_EXTRACT_VECTOR_ELT:
5933 case G_INSERT_VECTOR_ELT:
5934 return fewerElementsVectorExtractInsertVectorElt(MI, TypeIdx, NarrowVecTy: NarrowTy);
5935 case G_LOAD:
5936 case G_STORE:
5937 return reduceLoadStoreWidth(LdStMI&: cast<GLoadStore>(Val&: MI), TypeIdx, NarrowTy);
5938 case G_SEXT_INREG:
5939 return fewerElementsVectorMultiEltType(MI&: GMI, NumElts, NonVecOpIndices: {2 /*imm*/});
5940 GISEL_VECREDUCE_CASES_NONSEQ
5941 return fewerElementsVectorReductions(MI, TypeIdx, NarrowTy);
5942 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
5943 case TargetOpcode::G_VECREDUCE_SEQ_FMUL:
5944 return fewerElementsVectorSeqReductions(MI, TypeIdx, NarrowTy);
5945 case G_SHUFFLE_VECTOR:
5946 return fewerElementsVectorShuffle(MI, TypeIdx, NarrowTy);
5947 case G_FPOWI:
5948 return fewerElementsVectorMultiEltType(MI&: GMI, NumElts, NonVecOpIndices: {2 /*pow*/});
5949 case G_BITCAST:
5950 return fewerElementsBitcast(MI, TypeIdx, NarrowTy);
5951 case G_INTRINSIC_FPTRUNC_ROUND:
5952 return fewerElementsVectorMultiEltType(MI&: GMI, NumElts, NonVecOpIndices: {2});
5953 default:
5954 return UnableToLegalize;
5955 }
5956}
5957
5958LegalizerHelper::LegalizeResult
5959LegalizerHelper::fewerElementsBitcast(MachineInstr &MI, unsigned int TypeIdx,
5960 LLT NarrowTy) {
5961 assert(MI.getOpcode() == TargetOpcode::G_BITCAST &&
5962 "Not a bitcast operation");
5963
5964 if (TypeIdx != 0)
5965 return UnableToLegalize;
5966
5967 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
5968
5969 unsigned NewElemCount =
5970 NarrowTy.getSizeInBits() / SrcTy.getScalarSizeInBits();
5971 SmallVector<Register> SrcVRegs, BitcastVRegs;
5972 if (NewElemCount == 1) {
5973 LLT SrcNarrowTy = SrcTy.getElementType();
5974
5975 auto Unmerge = MIRBuilder.buildUnmerge(Res: SrcNarrowTy, Op: SrcReg);
5976 getUnmergeResults(Regs&: SrcVRegs, MI: *Unmerge);
5977 } else {
5978 LLT SrcNarrowTy =
5979 SrcTy.changeVectorElementCount(EC: ElementCount::getFixed(MinVal: NewElemCount));
5980
5981 // Split the Src and Dst Reg into smaller registers
5982 if (extractGCDType(Parts&: SrcVRegs, DstTy, NarrowTy: SrcNarrowTy, SrcReg) != SrcNarrowTy)
5983 return UnableToLegalize;
5984 }
5985
5986 // Build new smaller bitcast instructions
5987 // Not supporting Leftover types for now but will have to
5988 for (Register Reg : SrcVRegs)
5989 BitcastVRegs.push_back(Elt: MIRBuilder.buildBitcast(Dst: NarrowTy, Src: Reg).getReg(Idx: 0));
5990
5991 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: BitcastVRegs);
5992 MI.eraseFromParent();
5993 return Legalized;
5994}
5995
5996LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorShuffle(
5997 MachineInstr &MI, unsigned int TypeIdx, LLT NarrowTy) {
5998 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR);
5999 if (TypeIdx != 0)
6000 return UnableToLegalize;
6001
6002 auto [DstReg, DstTy, Src1Reg, Src1Ty, Src2Reg, Src2Ty] =
6003 MI.getFirst3RegLLTs();
6004 ArrayRef<int> Mask = MI.getOperand(i: 3).getShuffleMask();
6005 // The shuffle should be canonicalized by now.
6006 if (DstTy != Src1Ty)
6007 return UnableToLegalize;
6008 if (DstTy != Src2Ty)
6009 return UnableToLegalize;
6010
6011 if (!isPowerOf2_32(Value: DstTy.getNumElements()))
6012 return UnableToLegalize;
6013
6014 // We only support splitting a shuffle into 2, so adjust NarrowTy accordingly.
6015 // Further legalization attempts will be needed to do split further.
6016 NarrowTy =
6017 DstTy.changeElementCount(EC: DstTy.getElementCount().divideCoefficientBy(RHS: 2));
6018 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
6019
6020 SmallVector<Register> SplitSrc1Regs, SplitSrc2Regs;
6021 extractParts(Reg: Src1Reg, Ty: NarrowTy, NumParts: 2, VRegs&: SplitSrc1Regs, MIRBuilder, MRI);
6022 extractParts(Reg: Src2Reg, Ty: NarrowTy, NumParts: 2, VRegs&: SplitSrc2Regs, MIRBuilder, MRI);
6023 Register Inputs[4] = {SplitSrc1Regs[0], SplitSrc1Regs[1], SplitSrc2Regs[0],
6024 SplitSrc2Regs[1]};
6025
6026 Register Hi, Lo;
6027
6028 // If Lo or Hi uses elements from at most two of the four input vectors, then
6029 // express it as a vector shuffle of those two inputs. Otherwise extract the
6030 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
6031 SmallVector<int, 16> Ops;
6032 for (unsigned High = 0; High < 2; ++High) {
6033 Register &Output = High ? Hi : Lo;
6034
6035 // Build a shuffle mask for the output, discovering on the fly which
6036 // input vectors to use as shuffle operands (recorded in InputUsed).
6037 // If building a suitable shuffle vector proves too hard, then bail
6038 // out with useBuildVector set.
6039 unsigned InputUsed[2] = {-1U, -1U}; // Not yet discovered.
6040 unsigned FirstMaskIdx = High * NewElts;
6041 bool UseBuildVector = false;
6042 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
6043 // The mask element. This indexes into the input.
6044 int Idx = Mask[FirstMaskIdx + MaskOffset];
6045
6046 // The input vector this mask element indexes into.
6047 unsigned Input = (unsigned)Idx / NewElts;
6048
6049 if (Input >= std::size(Inputs)) {
6050 // The mask element does not index into any input vector.
6051 Ops.push_back(Elt: -1);
6052 continue;
6053 }
6054
6055 // Turn the index into an offset from the start of the input vector.
6056 Idx -= Input * NewElts;
6057
6058 // Find or create a shuffle vector operand to hold this input.
6059 unsigned OpNo;
6060 for (OpNo = 0; OpNo < std::size(InputUsed); ++OpNo) {
6061 if (InputUsed[OpNo] == Input) {
6062 // This input vector is already an operand.
6063 break;
6064 } else if (InputUsed[OpNo] == -1U) {
6065 // Create a new operand for this input vector.
6066 InputUsed[OpNo] = Input;
6067 break;
6068 }
6069 }
6070
6071 if (OpNo >= std::size(InputUsed)) {
6072 // More than two input vectors used! Give up on trying to create a
6073 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6074 UseBuildVector = true;
6075 break;
6076 }
6077
6078 // Add the mask index for the new shuffle vector.
6079 Ops.push_back(Elt: Idx + OpNo * NewElts);
6080 }
6081
6082 if (UseBuildVector) {
6083 LLT EltTy = NarrowTy.getElementType();
6084 SmallVector<Register, 16> SVOps;
6085
6086 // Extract the input elements by hand.
6087 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
6088 // The mask element. This indexes into the input.
6089 int Idx = Mask[FirstMaskIdx + MaskOffset];
6090
6091 // The input vector this mask element indexes into.
6092 unsigned Input = (unsigned)Idx / NewElts;
6093
6094 if (Input >= std::size(Inputs)) {
6095 // The mask element is "undef" or indexes off the end of the input.
6096 SVOps.push_back(Elt: MIRBuilder.buildUndef(Res: EltTy).getReg(Idx: 0));
6097 continue;
6098 }
6099
6100 // Turn the index into an offset from the start of the input vector.
6101 Idx -= Input * NewElts;
6102
6103 // Extract the vector element by hand.
6104 SVOps.push_back(Elt: MIRBuilder
6105 .buildExtractVectorElement(
6106 Res: EltTy, Val: Inputs[Input],
6107 Idx: MIRBuilder.buildConstant(Res: LLT::integer(SizeInBits: 32), Val: Idx))
6108 .getReg(Idx: 0));
6109 }
6110
6111 // Construct the Lo/Hi output using a G_BUILD_VECTOR.
6112 Output = MIRBuilder.buildBuildVector(Res: NarrowTy, Ops: SVOps).getReg(Idx: 0);
6113 } else if (InputUsed[0] == -1U) {
6114 // No input vectors were used! The result is undefined.
6115 Output = MIRBuilder.buildUndef(Res: NarrowTy).getReg(Idx: 0);
6116 } else if (NewElts == 1) {
6117 Output = MIRBuilder.buildCopy(Res: NarrowTy, Op: Inputs[InputUsed[0]]).getReg(Idx: 0);
6118 } else {
6119 Register Op0 = Inputs[InputUsed[0]];
6120 // If only one input was used, use an undefined vector for the other.
6121 Register Op1 = InputUsed[1] == -1U
6122 ? MIRBuilder.buildUndef(Res: NarrowTy).getReg(Idx: 0)
6123 : Inputs[InputUsed[1]];
6124 // At least one input vector was used. Create a new shuffle vector.
6125 Output = MIRBuilder.buildShuffleVector(Res: NarrowTy, Src1: Op0, Src2: Op1, Mask: Ops).getReg(Idx: 0);
6126 }
6127
6128 Ops.clear();
6129 }
6130
6131 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: {Lo, Hi});
6132 MI.eraseFromParent();
6133 return Legalized;
6134}
6135
6136LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorReductions(
6137 MachineInstr &MI, unsigned int TypeIdx, LLT NarrowTy) {
6138 auto &RdxMI = cast<GVecReduce>(Val&: MI);
6139
6140 if (TypeIdx != 1)
6141 return UnableToLegalize;
6142
6143 // The semantics of the normal non-sequential reductions allow us to freely
6144 // re-associate the operation.
6145 auto [DstReg, DstTy, SrcReg, SrcTy] = RdxMI.getFirst2RegLLTs();
6146
6147 if (NarrowTy.isVector() &&
6148 (SrcTy.getNumElements() % NarrowTy.getNumElements() != 0))
6149 return UnableToLegalize;
6150
6151 unsigned ScalarOpc = RdxMI.getScalarOpcForReduction();
6152 SmallVector<Register> SplitSrcs;
6153 // If NarrowTy is a scalar then we're being asked to scalarize.
6154 const unsigned NumParts =
6155 NarrowTy.isVector() ? SrcTy.getNumElements() / NarrowTy.getNumElements()
6156 : SrcTy.getNumElements();
6157
6158 extractParts(Reg: SrcReg, Ty: NarrowTy, NumParts, VRegs&: SplitSrcs, MIRBuilder, MRI);
6159 if (NarrowTy.isScalar()) {
6160 if (DstTy != NarrowTy)
6161 return UnableToLegalize; // FIXME: handle implicit extensions.
6162
6163 if (isPowerOf2_32(Value: NumParts)) {
6164 // Generate a tree of scalar operations to reduce the critical path.
6165 SmallVector<Register> PartialResults;
6166 unsigned NumPartsLeft = NumParts;
6167 while (NumPartsLeft > 1) {
6168 for (unsigned Idx = 0; Idx < NumPartsLeft - 1; Idx += 2) {
6169 PartialResults.emplace_back(
6170 Args: MIRBuilder
6171 .buildInstr(Opc: ScalarOpc, DstOps: {NarrowTy},
6172 SrcOps: {SplitSrcs[Idx], SplitSrcs[Idx + 1]})
6173 .getReg(Idx: 0));
6174 }
6175 SplitSrcs = PartialResults;
6176 PartialResults.clear();
6177 NumPartsLeft = SplitSrcs.size();
6178 }
6179 assert(SplitSrcs.size() == 1);
6180 MIRBuilder.buildCopy(Res: DstReg, Op: SplitSrcs[0]);
6181 MI.eraseFromParent();
6182 return Legalized;
6183 }
6184 // If we can't generate a tree, then just do sequential operations.
6185 Register Acc = SplitSrcs[0];
6186 for (unsigned Idx = 1; Idx < NumParts; ++Idx)
6187 Acc = MIRBuilder.buildInstr(Opc: ScalarOpc, DstOps: {NarrowTy}, SrcOps: {Acc, SplitSrcs[Idx]})
6188 .getReg(Idx: 0);
6189 MIRBuilder.buildCopy(Res: DstReg, Op: Acc);
6190 MI.eraseFromParent();
6191 return Legalized;
6192 }
6193 SmallVector<Register> PartialReductions;
6194 for (unsigned Part = 0; Part < NumParts; ++Part) {
6195 PartialReductions.push_back(
6196 Elt: MIRBuilder.buildInstr(Opc: RdxMI.getOpcode(), DstOps: {DstTy}, SrcOps: {SplitSrcs[Part]})
6197 .getReg(Idx: 0));
6198 }
6199
6200 // If the types involved are powers of 2, we can generate intermediate vector
6201 // ops, before generating a final reduction operation.
6202 if (isPowerOf2_32(Value: SrcTy.getNumElements()) &&
6203 isPowerOf2_32(Value: NarrowTy.getNumElements())) {
6204 return tryNarrowPow2Reduction(MI, SrcReg, SrcTy, NarrowTy, ScalarOpc);
6205 }
6206
6207 Register Acc = PartialReductions[0];
6208 for (unsigned Part = 1; Part < NumParts; ++Part) {
6209 if (Part == NumParts - 1) {
6210 MIRBuilder.buildInstr(Opc: ScalarOpc, DstOps: {DstReg},
6211 SrcOps: {Acc, PartialReductions[Part]});
6212 } else {
6213 Acc = MIRBuilder
6214 .buildInstr(Opc: ScalarOpc, DstOps: {DstTy}, SrcOps: {Acc, PartialReductions[Part]})
6215 .getReg(Idx: 0);
6216 }
6217 }
6218 MI.eraseFromParent();
6219 return Legalized;
6220}
6221
6222LegalizerHelper::LegalizeResult
6223LegalizerHelper::fewerElementsVectorSeqReductions(MachineInstr &MI,
6224 unsigned int TypeIdx,
6225 LLT NarrowTy) {
6226 auto [DstReg, DstTy, ScalarReg, ScalarTy, SrcReg, SrcTy] =
6227 MI.getFirst3RegLLTs();
6228 if (!NarrowTy.isScalar() || TypeIdx != 2 || DstTy != ScalarTy ||
6229 DstTy != NarrowTy)
6230 return UnableToLegalize;
6231
6232 assert((MI.getOpcode() == TargetOpcode::G_VECREDUCE_SEQ_FADD ||
6233 MI.getOpcode() == TargetOpcode::G_VECREDUCE_SEQ_FMUL) &&
6234 "Unexpected vecreduce opcode");
6235 unsigned ScalarOpc = MI.getOpcode() == TargetOpcode::G_VECREDUCE_SEQ_FADD
6236 ? TargetOpcode::G_FADD
6237 : TargetOpcode::G_FMUL;
6238
6239 SmallVector<Register> SplitSrcs;
6240 unsigned NumParts = SrcTy.getNumElements();
6241 extractParts(Reg: SrcReg, Ty: NarrowTy, NumParts, VRegs&: SplitSrcs, MIRBuilder, MRI);
6242 Register Acc = ScalarReg;
6243 for (unsigned i = 0; i < NumParts; i++)
6244 Acc = MIRBuilder.buildInstr(Opc: ScalarOpc, DstOps: {NarrowTy}, SrcOps: {Acc, SplitSrcs[i]})
6245 .getReg(Idx: 0);
6246
6247 MIRBuilder.buildCopy(Res: DstReg, Op: Acc);
6248 MI.eraseFromParent();
6249 return Legalized;
6250}
6251
6252LegalizerHelper::LegalizeResult
6253LegalizerHelper::tryNarrowPow2Reduction(MachineInstr &MI, Register SrcReg,
6254 LLT SrcTy, LLT NarrowTy,
6255 unsigned ScalarOpc) {
6256 SmallVector<Register> SplitSrcs;
6257 // Split the sources into NarrowTy size pieces.
6258 extractParts(Reg: SrcReg, Ty: NarrowTy,
6259 NumParts: SrcTy.getNumElements() / NarrowTy.getNumElements(), VRegs&: SplitSrcs,
6260 MIRBuilder, MRI);
6261 // We're going to do a tree reduction using vector operations until we have
6262 // one NarrowTy size value left.
6263 while (SplitSrcs.size() > 1) {
6264 SmallVector<Register> PartialRdxs;
6265 for (unsigned Idx = 0; Idx < SplitSrcs.size()-1; Idx += 2) {
6266 Register LHS = SplitSrcs[Idx];
6267 Register RHS = SplitSrcs[Idx + 1];
6268 // Create the intermediate vector op.
6269 Register Res =
6270 MIRBuilder.buildInstr(Opc: ScalarOpc, DstOps: {NarrowTy}, SrcOps: {LHS, RHS}).getReg(Idx: 0);
6271 PartialRdxs.push_back(Elt: Res);
6272 }
6273 SplitSrcs = std::move(PartialRdxs);
6274 }
6275 // Finally generate the requested NarrowTy based reduction.
6276 Observer.changingInstr(MI);
6277 MI.getOperand(i: 1).setReg(SplitSrcs[0]);
6278 Observer.changedInstr(MI);
6279 return Legalized;
6280}
6281
6282LegalizerHelper::LegalizeResult
6283LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
6284 const LLT HalfTy, const LLT AmtTy) {
6285
6286 Register InL = MRI.createGenericVirtualRegister(Ty: HalfTy);
6287 Register InH = MRI.createGenericVirtualRegister(Ty: HalfTy);
6288 MIRBuilder.buildUnmerge(Res: {InL, InH}, Op: MI.getOperand(i: 1));
6289
6290 if (Amt.isZero()) {
6291 MIRBuilder.buildMergeLikeInstr(Res: MI.getOperand(i: 0), Ops: {InL, InH});
6292 MI.eraseFromParent();
6293 return Legalized;
6294 }
6295
6296 LLT NVT = HalfTy;
6297 unsigned NVTBits = HalfTy.getSizeInBits();
6298 unsigned VTBits = 2 * NVTBits;
6299
6300 SrcOp Lo(Register(0)), Hi(Register(0));
6301 if (MI.getOpcode() == TargetOpcode::G_SHL) {
6302 if (Amt.ugt(RHS: VTBits)) {
6303 Lo = Hi = MIRBuilder.buildConstant(Res: NVT, Val: 0);
6304 } else if (Amt.ugt(RHS: NVTBits)) {
6305 Lo = MIRBuilder.buildConstant(Res: NVT, Val: 0);
6306 Hi = MIRBuilder.buildShl(Dst: NVT, Src0: InL,
6307 Src1: MIRBuilder.buildConstant(Res: AmtTy, Val: Amt - NVTBits));
6308 } else if (Amt == NVTBits) {
6309 Lo = MIRBuilder.buildConstant(Res: NVT, Val: 0);
6310 Hi = InL;
6311 } else {
6312 Lo = MIRBuilder.buildShl(Dst: NVT, Src0: InL, Src1: MIRBuilder.buildConstant(Res: AmtTy, Val: Amt));
6313 auto OrLHS =
6314 MIRBuilder.buildShl(Dst: NVT, Src0: InH, Src1: MIRBuilder.buildConstant(Res: AmtTy, Val: Amt));
6315 auto OrRHS = MIRBuilder.buildLShr(
6316 Dst: NVT, Src0: InL, Src1: MIRBuilder.buildConstant(Res: AmtTy, Val: -Amt + NVTBits));
6317 Hi = MIRBuilder.buildOr(Dst: NVT, Src0: OrLHS, Src1: OrRHS);
6318 }
6319 } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
6320 if (Amt.ugt(RHS: VTBits)) {
6321 Lo = Hi = MIRBuilder.buildConstant(Res: NVT, Val: 0);
6322 } else if (Amt.ugt(RHS: NVTBits)) {
6323 Lo = MIRBuilder.buildLShr(Dst: NVT, Src0: InH,
6324 Src1: MIRBuilder.buildConstant(Res: AmtTy, Val: Amt - NVTBits));
6325 Hi = MIRBuilder.buildConstant(Res: NVT, Val: 0);
6326 } else if (Amt == NVTBits) {
6327 Lo = InH;
6328 Hi = MIRBuilder.buildConstant(Res: NVT, Val: 0);
6329 } else {
6330 auto ShiftAmtConst = MIRBuilder.buildConstant(Res: AmtTy, Val: Amt);
6331
6332 auto OrLHS = MIRBuilder.buildLShr(Dst: NVT, Src0: InL, Src1: ShiftAmtConst);
6333 auto OrRHS = MIRBuilder.buildShl(
6334 Dst: NVT, Src0: InH, Src1: MIRBuilder.buildConstant(Res: AmtTy, Val: -Amt + NVTBits));
6335
6336 Lo = MIRBuilder.buildOr(Dst: NVT, Src0: OrLHS, Src1: OrRHS);
6337 Hi = MIRBuilder.buildLShr(Dst: NVT, Src0: InH, Src1: ShiftAmtConst);
6338 }
6339 } else {
6340 if (Amt.ugt(RHS: VTBits)) {
6341 Hi = Lo = MIRBuilder.buildAShr(
6342 Dst: NVT, Src0: InH, Src1: MIRBuilder.buildConstant(Res: AmtTy, Val: NVTBits - 1));
6343 } else if (Amt.ugt(RHS: NVTBits)) {
6344 Lo = MIRBuilder.buildAShr(Dst: NVT, Src0: InH,
6345 Src1: MIRBuilder.buildConstant(Res: AmtTy, Val: Amt - NVTBits));
6346 Hi = MIRBuilder.buildAShr(Dst: NVT, Src0: InH,
6347 Src1: MIRBuilder.buildConstant(Res: AmtTy, Val: NVTBits - 1));
6348 } else if (Amt == NVTBits) {
6349 Lo = InH;
6350 Hi = MIRBuilder.buildAShr(Dst: NVT, Src0: InH,
6351 Src1: MIRBuilder.buildConstant(Res: AmtTy, Val: NVTBits - 1));
6352 } else {
6353 auto ShiftAmtConst = MIRBuilder.buildConstant(Res: AmtTy, Val: Amt);
6354
6355 auto OrLHS = MIRBuilder.buildLShr(Dst: NVT, Src0: InL, Src1: ShiftAmtConst);
6356 auto OrRHS = MIRBuilder.buildShl(
6357 Dst: NVT, Src0: InH, Src1: MIRBuilder.buildConstant(Res: AmtTy, Val: -Amt + NVTBits));
6358
6359 Lo = MIRBuilder.buildOr(Dst: NVT, Src0: OrLHS, Src1: OrRHS);
6360 Hi = MIRBuilder.buildAShr(Dst: NVT, Src0: InH, Src1: ShiftAmtConst);
6361 }
6362 }
6363
6364 MIRBuilder.buildMergeLikeInstr(Res: MI.getOperand(i: 0), Ops: {Lo, Hi});
6365 MI.eraseFromParent();
6366
6367 return Legalized;
6368}
6369
6370LegalizerHelper::LegalizeResult
6371LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
6372 LLT RequestedTy) {
6373 if (TypeIdx == 1) {
6374 Observer.changingInstr(MI);
6375 narrowScalarSrc(MI, NarrowTy: RequestedTy, OpIdx: 2);
6376 Observer.changedInstr(MI);
6377 return Legalized;
6378 }
6379
6380 Register DstReg = MI.getOperand(i: 0).getReg();
6381 LLT DstTy = MRI.getType(Reg: DstReg);
6382 if (DstTy.isVector())
6383 return UnableToLegalize;
6384
6385 Register Amt = MI.getOperand(i: 2).getReg();
6386 LLT ShiftAmtTy = MRI.getType(Reg: Amt);
6387 const unsigned DstEltSize = DstTy.getScalarSizeInBits();
6388 if (DstEltSize % 2 != 0)
6389 return UnableToLegalize;
6390
6391 // Check if we should use multi-way splitting instead of recursive binary
6392 // splitting.
6393 //
6394 // Multi-way splitting directly decomposes wide shifts (e.g., 128-bit ->
6395 // 4×32-bit) in a single legalization step, avoiding the recursive overhead
6396 // and dependency chains created by usual binary splitting approach
6397 // (128->64->32).
6398 //
6399 // The >= 8 parts threshold ensures we only use this optimization when binary
6400 // splitting would require multiple recursive passes, avoiding overhead for
6401 // simple 2-way splits where binary approach is sufficient.
6402 if (RequestedTy.isValid() && RequestedTy.isScalar() &&
6403 DstEltSize % RequestedTy.getSizeInBits() == 0) {
6404 const unsigned NumParts = DstEltSize / RequestedTy.getSizeInBits();
6405 // Use multiway if we have 8 or more parts (i.e., would need 3+ recursive
6406 // steps).
6407 if (NumParts >= 8)
6408 return narrowScalarShiftMultiway(MI, TargetTy: RequestedTy);
6409 }
6410
6411 // Fall back to binary splitting:
6412 // Ignore the input type. We can only go to exactly half the size of the
6413 // input. If that isn't small enough, the resulting pieces will be further
6414 // legalized.
6415 const unsigned NewBitSize = DstEltSize / 2;
6416 const LLT HalfTy = DstTy.getScalarType().changeElementSize(NewEltSize: NewBitSize);
6417 const LLT CondTy = LLT::integer(SizeInBits: 1);
6418
6419 if (auto VRegAndVal = getIConstantVRegValWithLookThrough(VReg: Amt, MRI)) {
6420 return narrowScalarShiftByConstant(MI, Amt: VRegAndVal->Value, HalfTy,
6421 AmtTy: ShiftAmtTy);
6422 }
6423
6424 // TODO: Expand with known bits.
6425
6426 // Handle the fully general expansion by an unknown amount.
6427 auto NewBits = MIRBuilder.buildConstant(Res: ShiftAmtTy, Val: NewBitSize);
6428
6429 Register InL = MRI.createGenericVirtualRegister(Ty: HalfTy);
6430 Register InH = MRI.createGenericVirtualRegister(Ty: HalfTy);
6431 MIRBuilder.buildUnmerge(Res: {InL, InH}, Op: MI.getOperand(i: 1));
6432
6433 auto AmtExcess = MIRBuilder.buildSub(Dst: ShiftAmtTy, Src0: Amt, Src1: NewBits);
6434 auto AmtLack = MIRBuilder.buildSub(Dst: ShiftAmtTy, Src0: NewBits, Src1: Amt);
6435
6436 auto Zero = MIRBuilder.buildConstant(Res: ShiftAmtTy, Val: 0);
6437 auto IsShort = MIRBuilder.buildICmp(Pred: ICmpInst::ICMP_ULT, Res: CondTy, Op0: Amt, Op1: NewBits);
6438 auto IsZero = MIRBuilder.buildICmp(Pred: ICmpInst::ICMP_EQ, Res: CondTy, Op0: Amt, Op1: Zero);
6439
6440 Register ResultRegs[2];
6441 switch (MI.getOpcode()) {
6442 case TargetOpcode::G_SHL: {
6443 // Short: ShAmt < NewBitSize
6444 auto LoS = MIRBuilder.buildShl(Dst: HalfTy, Src0: InL, Src1: Amt);
6445
6446 auto LoOr = MIRBuilder.buildLShr(Dst: HalfTy, Src0: InL, Src1: AmtLack);
6447 auto HiOr = MIRBuilder.buildShl(Dst: HalfTy, Src0: InH, Src1: Amt);
6448 auto HiS = MIRBuilder.buildOr(Dst: HalfTy, Src0: LoOr, Src1: HiOr);
6449
6450 // Long: ShAmt >= NewBitSize
6451 auto LoL = MIRBuilder.buildConstant(Res: HalfTy, Val: 0); // Lo part is zero.
6452 auto HiL = MIRBuilder.buildShl(Dst: HalfTy, Src0: InL, Src1: AmtExcess); // Hi from Lo part.
6453
6454 auto Lo = MIRBuilder.buildSelect(Res: HalfTy, Tst: IsShort, Op0: LoS, Op1: LoL);
6455 auto Hi = MIRBuilder.buildSelect(
6456 Res: HalfTy, Tst: IsZero, Op0: InH, Op1: MIRBuilder.buildSelect(Res: HalfTy, Tst: IsShort, Op0: HiS, Op1: HiL));
6457
6458 ResultRegs[0] = Lo.getReg(Idx: 0);
6459 ResultRegs[1] = Hi.getReg(Idx: 0);
6460 break;
6461 }
6462 case TargetOpcode::G_LSHR:
6463 case TargetOpcode::G_ASHR: {
6464 // Short: ShAmt < NewBitSize
6465 auto HiS = MIRBuilder.buildInstr(Opc: MI.getOpcode(), DstOps: {HalfTy}, SrcOps: {InH, Amt});
6466
6467 auto LoOr = MIRBuilder.buildLShr(Dst: HalfTy, Src0: InL, Src1: Amt);
6468 auto HiOr = MIRBuilder.buildShl(Dst: HalfTy, Src0: InH, Src1: AmtLack);
6469 auto LoS = MIRBuilder.buildOr(Dst: HalfTy, Src0: LoOr, Src1: HiOr);
6470
6471 // Long: ShAmt >= NewBitSize
6472 MachineInstrBuilder HiL;
6473 if (MI.getOpcode() == TargetOpcode::G_LSHR) {
6474 HiL = MIRBuilder.buildConstant(Res: HalfTy, Val: 0); // Hi part is zero.
6475 } else {
6476 auto ShiftAmt = MIRBuilder.buildConstant(Res: ShiftAmtTy, Val: NewBitSize - 1);
6477 HiL = MIRBuilder.buildAShr(Dst: HalfTy, Src0: InH, Src1: ShiftAmt); // Sign of Hi part.
6478 }
6479 auto LoL = MIRBuilder.buildInstr(Opc: MI.getOpcode(), DstOps: {HalfTy},
6480 SrcOps: {InH, AmtExcess}); // Lo from Hi part.
6481
6482 auto Lo = MIRBuilder.buildSelect(
6483 Res: HalfTy, Tst: IsZero, Op0: InL, Op1: MIRBuilder.buildSelect(Res: HalfTy, Tst: IsShort, Op0: LoS, Op1: LoL));
6484
6485 auto Hi = MIRBuilder.buildSelect(Res: HalfTy, Tst: IsShort, Op0: HiS, Op1: HiL);
6486
6487 ResultRegs[0] = Lo.getReg(Idx: 0);
6488 ResultRegs[1] = Hi.getReg(Idx: 0);
6489 break;
6490 }
6491 default:
6492 llvm_unreachable("not a shift");
6493 }
6494
6495 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: ResultRegs);
6496 MI.eraseFromParent();
6497 return Legalized;
6498}
6499
6500Register LegalizerHelper::buildConstantShiftPart(unsigned Opcode,
6501 unsigned PartIdx,
6502 unsigned NumParts,
6503 ArrayRef<Register> SrcParts,
6504 const ShiftParams &Params,
6505 LLT TargetTy, LLT ShiftAmtTy) {
6506 auto WordShiftConst = getIConstantVRegVal(VReg: Params.WordShift, MRI);
6507 auto BitShiftConst = getIConstantVRegVal(VReg: Params.BitShift, MRI);
6508 assert(WordShiftConst && BitShiftConst && "Expected constants");
6509
6510 const unsigned ShiftWords = WordShiftConst->getZExtValue();
6511 const unsigned ShiftBits = BitShiftConst->getZExtValue();
6512 const bool NeedsInterWordShift = ShiftBits != 0;
6513
6514 switch (Opcode) {
6515 case TargetOpcode::G_SHL: {
6516 // Data moves from lower indices to higher indices
6517 // If this part would come from a source beyond our range, it's zero
6518 if (PartIdx < ShiftWords)
6519 return Params.Zero;
6520
6521 unsigned SrcIdx = PartIdx - ShiftWords;
6522 if (!NeedsInterWordShift)
6523 return SrcParts[SrcIdx];
6524
6525 // Combine shifted main part with carry from previous part
6526 auto Hi = MIRBuilder.buildShl(Dst: TargetTy, Src0: SrcParts[SrcIdx], Src1: Params.BitShift);
6527 if (SrcIdx > 0) {
6528 auto Lo = MIRBuilder.buildLShr(Dst: TargetTy, Src0: SrcParts[SrcIdx - 1],
6529 Src1: Params.InvBitShift);
6530 return MIRBuilder.buildOr(Dst: TargetTy, Src0: Hi, Src1: Lo).getReg(Idx: 0);
6531 }
6532 return Hi.getReg(Idx: 0);
6533 }
6534
6535 case TargetOpcode::G_LSHR: {
6536 unsigned SrcIdx = PartIdx + ShiftWords;
6537 if (SrcIdx >= NumParts)
6538 return Params.Zero;
6539 if (!NeedsInterWordShift)
6540 return SrcParts[SrcIdx];
6541
6542 // Combine shifted main part with carry from next part
6543 auto Lo = MIRBuilder.buildLShr(Dst: TargetTy, Src0: SrcParts[SrcIdx], Src1: Params.BitShift);
6544 if (SrcIdx + 1 < NumParts) {
6545 auto Hi = MIRBuilder.buildShl(Dst: TargetTy, Src0: SrcParts[SrcIdx + 1],
6546 Src1: Params.InvBitShift);
6547 return MIRBuilder.buildOr(Dst: TargetTy, Src0: Lo, Src1: Hi).getReg(Idx: 0);
6548 }
6549 return Lo.getReg(Idx: 0);
6550 }
6551
6552 case TargetOpcode::G_ASHR: {
6553 // Like LSHR but preserves sign bit
6554 unsigned SrcIdx = PartIdx + ShiftWords;
6555 if (SrcIdx >= NumParts)
6556 return Params.SignBit;
6557 if (!NeedsInterWordShift)
6558 return SrcParts[SrcIdx];
6559
6560 // Only the original MSB part uses arithmetic shift to preserve sign. All
6561 // other parts use logical shift since they're just moving data bits.
6562 auto Lo =
6563 (SrcIdx == NumParts - 1)
6564 ? MIRBuilder.buildAShr(Dst: TargetTy, Src0: SrcParts[SrcIdx], Src1: Params.BitShift)
6565 : MIRBuilder.buildLShr(Dst: TargetTy, Src0: SrcParts[SrcIdx], Src1: Params.BitShift);
6566 Register HiSrc =
6567 (SrcIdx + 1 < NumParts) ? SrcParts[SrcIdx + 1] : Params.SignBit;
6568 auto Hi = MIRBuilder.buildShl(Dst: TargetTy, Src0: HiSrc, Src1: Params.InvBitShift);
6569 return MIRBuilder.buildOr(Dst: TargetTy, Src0: Lo, Src1: Hi).getReg(Idx: 0);
6570 }
6571
6572 default:
6573 llvm_unreachable("not a shift");
6574 }
6575}
6576
6577Register LegalizerHelper::buildVariableShiftPart(unsigned Opcode,
6578 Register MainOperand,
6579 Register ShiftAmt,
6580 LLT TargetTy,
6581 Register CarryOperand) {
6582 // This helper generates a single output part for variable shifts by combining
6583 // the main operand (shifted by BitShift) with carry bits from an adjacent
6584 // part.
6585
6586 // For G_ASHR, individual parts don't have their own sign bit, only the
6587 // complete value does. So we use LSHR for the main operand shift in ASHR
6588 // context.
6589 unsigned MainOpcode = (Opcode == TargetOpcode::G_ASHR)
6590 ? static_cast<unsigned>(TargetOpcode::G_LSHR)
6591 : Opcode;
6592
6593 // Perform the primary shift on the main operand
6594 Register MainShifted =
6595 MIRBuilder.buildInstr(Opc: MainOpcode, DstOps: {TargetTy}, SrcOps: {MainOperand, ShiftAmt})
6596 .getReg(Idx: 0);
6597
6598 // No carry operand available
6599 if (!CarryOperand.isValid())
6600 return MainShifted;
6601
6602 // If BitShift is 0 (word-aligned shift), no inter-word bit movement occurs,
6603 // so carry bits aren't needed.
6604 LLT ShiftAmtTy = MRI.getType(Reg: ShiftAmt);
6605 auto ZeroConst = MIRBuilder.buildConstant(Res: ShiftAmtTy, Val: 0);
6606 LLT BoolTy = LLT::scalar(SizeInBits: 1);
6607 auto IsZeroBitShift =
6608 MIRBuilder.buildICmp(Pred: ICmpInst::ICMP_EQ, Res: BoolTy, Op0: ShiftAmt, Op1: ZeroConst);
6609
6610 // Extract bits from the adjacent part that will "carry over" into this part.
6611 // The carry direction is opposite to the main shift direction, so we can
6612 // align the two shifted values before combining them with OR.
6613
6614 // Determine the carry shift opcode (opposite direction)
6615 unsigned CarryOpcode = (Opcode == TargetOpcode::G_SHL) ? TargetOpcode::G_LSHR
6616 : TargetOpcode::G_SHL;
6617
6618 // Calculate inverse shift amount: BitWidth - ShiftAmt
6619 auto TargetBitsConst =
6620 MIRBuilder.buildConstant(Res: ShiftAmtTy, Val: TargetTy.getScalarSizeInBits());
6621 auto InvShiftAmt = MIRBuilder.buildSub(Dst: ShiftAmtTy, Src0: TargetBitsConst, Src1: ShiftAmt);
6622
6623 // Shift the carry operand
6624 Register CarryBits =
6625 MIRBuilder
6626 .buildInstr(Opc: CarryOpcode, DstOps: {TargetTy}, SrcOps: {CarryOperand, InvShiftAmt})
6627 .getReg(Idx: 0);
6628
6629 // If BitShift is 0, don't include carry bits (InvShiftAmt would equal
6630 // TargetBits which would be poison for the individual carry shift operation).
6631 auto ZeroReg = MIRBuilder.buildConstant(Res: TargetTy, Val: 0);
6632 Register SafeCarryBits =
6633 MIRBuilder.buildSelect(Res: TargetTy, Tst: IsZeroBitShift, Op0: ZeroReg, Op1: CarryBits)
6634 .getReg(Idx: 0);
6635
6636 // Combine the main shifted part with the carry bits
6637 return MIRBuilder.buildOr(Dst: TargetTy, Src0: MainShifted, Src1: SafeCarryBits).getReg(Idx: 0);
6638}
6639
6640LegalizerHelper::LegalizeResult
6641LegalizerHelper::narrowScalarShiftByConstantMultiway(MachineInstr &MI,
6642 const APInt &Amt,
6643 LLT TargetTy,
6644 LLT ShiftAmtTy) {
6645 // Any wide shift can be decomposed into WordShift + BitShift components.
6646 // When shift amount is known constant, directly compute the decomposition
6647 // values and generate constant registers.
6648 Register DstReg = MI.getOperand(i: 0).getReg();
6649 Register SrcReg = MI.getOperand(i: 1).getReg();
6650 LLT DstTy = MRI.getType(Reg: DstReg);
6651
6652 const unsigned DstBits = DstTy.getScalarSizeInBits();
6653 const unsigned TargetBits = TargetTy.getScalarSizeInBits();
6654 const unsigned NumParts = DstBits / TargetBits;
6655
6656 assert(DstBits % TargetBits == 0 && "Target type must evenly divide source");
6657
6658 // When the shift amount is known at compile time, we just calculate which
6659 // source parts contribute to each output part.
6660
6661 SmallVector<Register, 8> SrcParts;
6662 extractParts(Reg: SrcReg, Ty: TargetTy, NumParts, VRegs&: SrcParts, MIRBuilder, MRI);
6663
6664 if (Amt.isZero()) {
6665 // No shift needed, just copy
6666 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: SrcParts);
6667 MI.eraseFromParent();
6668 return Legalized;
6669 }
6670
6671 ShiftParams Params;
6672 const unsigned ShiftWords = Amt.getZExtValue() / TargetBits;
6673 const unsigned ShiftBits = Amt.getZExtValue() % TargetBits;
6674
6675 // Generate constants and values needed by all shift types
6676 Params.WordShift = MIRBuilder.buildConstant(Res: ShiftAmtTy, Val: ShiftWords).getReg(Idx: 0);
6677 Params.BitShift = MIRBuilder.buildConstant(Res: ShiftAmtTy, Val: ShiftBits).getReg(Idx: 0);
6678 Params.InvBitShift =
6679 MIRBuilder.buildConstant(Res: ShiftAmtTy, Val: TargetBits - ShiftBits).getReg(Idx: 0);
6680 Params.Zero = MIRBuilder.buildConstant(Res: TargetTy, Val: 0).getReg(Idx: 0);
6681
6682 // For ASHR, we need the sign-extended value to fill shifted-out positions
6683 if (MI.getOpcode() == TargetOpcode::G_ASHR)
6684 Params.SignBit =
6685 MIRBuilder
6686 .buildAShr(Dst: TargetTy, Src0: SrcParts[SrcParts.size() - 1],
6687 Src1: MIRBuilder.buildConstant(Res: ShiftAmtTy, Val: TargetBits - 1))
6688 .getReg(Idx: 0);
6689
6690 SmallVector<Register, 8> DstParts(NumParts);
6691 for (unsigned I = 0; I < NumParts; ++I)
6692 DstParts[I] = buildConstantShiftPart(Opcode: MI.getOpcode(), PartIdx: I, NumParts, SrcParts,
6693 Params, TargetTy, ShiftAmtTy);
6694
6695 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: DstParts);
6696 MI.eraseFromParent();
6697 return Legalized;
6698}
6699
6700LegalizerHelper::LegalizeResult
6701LegalizerHelper::narrowScalarShiftMultiway(MachineInstr &MI, LLT TargetTy) {
6702 Register DstReg = MI.getOperand(i: 0).getReg();
6703 Register SrcReg = MI.getOperand(i: 1).getReg();
6704 Register AmtReg = MI.getOperand(i: 2).getReg();
6705 LLT DstTy = MRI.getType(Reg: DstReg);
6706 LLT ShiftAmtTy = MRI.getType(Reg: AmtReg);
6707
6708 const unsigned DstBits = DstTy.getScalarSizeInBits();
6709 const unsigned TargetBits = TargetTy.getScalarSizeInBits();
6710 const unsigned NumParts = DstBits / TargetBits;
6711
6712 assert(DstBits % TargetBits == 0 && "Target type must evenly divide source");
6713 assert(isPowerOf2_32(TargetBits) && "Target bit width must be power of 2");
6714
6715 // If the shift amount is known at compile time, we can use direct indexing
6716 // instead of generating select chains in the general case.
6717 if (auto VRegAndVal = getIConstantVRegValWithLookThrough(VReg: AmtReg, MRI))
6718 return narrowScalarShiftByConstantMultiway(MI, Amt: VRegAndVal->Value, TargetTy,
6719 ShiftAmtTy);
6720
6721 // For runtime-variable shift amounts, we must generate a more complex
6722 // sequence that handles all possible shift values using select chains.
6723
6724 // Split the input into target-sized pieces
6725 SmallVector<Register, 8> SrcParts;
6726 extractParts(Reg: SrcReg, Ty: TargetTy, NumParts, VRegs&: SrcParts, MIRBuilder, MRI);
6727
6728 // Shifting by zero should be a no-op.
6729 auto ZeroAmtConst = MIRBuilder.buildConstant(Res: ShiftAmtTy, Val: 0);
6730 LLT BoolTy = LLT::scalar(SizeInBits: 1);
6731 auto IsZeroShift =
6732 MIRBuilder.buildICmp(Pred: ICmpInst::ICMP_EQ, Res: BoolTy, Op0: AmtReg, Op1: ZeroAmtConst);
6733
6734 // Any wide shift can be decomposed into two components:
6735 // 1. WordShift: number of complete target-sized words to shift
6736 // 2. BitShift: number of bits to shift within each word
6737 //
6738 // Example: 128-bit >> 50 with 32-bit target:
6739 // WordShift = 50 / 32 = 1 (shift right by 1 complete word)
6740 // BitShift = 50 % 32 = 18 (shift each word right by 18 bits)
6741 unsigned TargetBitsLog2 = Log2_32(Value: TargetBits);
6742 auto TargetBitsLog2Const =
6743 MIRBuilder.buildConstant(Res: ShiftAmtTy, Val: TargetBitsLog2);
6744 auto TargetBitsMask = MIRBuilder.buildConstant(Res: ShiftAmtTy, Val: TargetBits - 1);
6745
6746 Register WordShift =
6747 MIRBuilder.buildLShr(Dst: ShiftAmtTy, Src0: AmtReg, Src1: TargetBitsLog2Const).getReg(Idx: 0);
6748 Register BitShift =
6749 MIRBuilder.buildAnd(Dst: ShiftAmtTy, Src0: AmtReg, Src1: TargetBitsMask).getReg(Idx: 0);
6750
6751 // Fill values:
6752 // - SHL/LSHR: fill with zeros
6753 // - ASHR: fill with sign-extended MSB
6754 Register ZeroReg = MIRBuilder.buildConstant(Res: TargetTy, Val: 0).getReg(Idx: 0);
6755
6756 Register FillValue;
6757 if (MI.getOpcode() == TargetOpcode::G_ASHR) {
6758 auto TargetBitsMinusOneConst =
6759 MIRBuilder.buildConstant(Res: ShiftAmtTy, Val: TargetBits - 1);
6760 FillValue = MIRBuilder
6761 .buildAShr(Dst: TargetTy, Src0: SrcParts[NumParts - 1],
6762 Src1: TargetBitsMinusOneConst)
6763 .getReg(Idx: 0);
6764 } else {
6765 FillValue = ZeroReg;
6766 }
6767
6768 SmallVector<Register, 8> DstParts(NumParts);
6769
6770 // For each output part, generate a select chain that chooses the correct
6771 // result based on the runtime WordShift value. This handles all possible
6772 // word shift amounts by pre-calculating what each would produce.
6773 for (unsigned I = 0; I < NumParts; ++I) {
6774 // Initialize with appropriate default value for this shift type
6775 Register InBoundsResult = FillValue;
6776
6777 // clang-format off
6778 // Build a branchless select chain by pre-computing results for all possible
6779 // WordShift values (0 to NumParts-1). Each iteration nests a new select:
6780 //
6781 // K=0: select(WordShift==0, result0, FillValue)
6782 // K=1: select(WordShift==1, result1, select(WordShift==0, result0, FillValue))
6783 // K=2: select(WordShift==2, result2, select(WordShift==1, result1, select(...)))
6784 // clang-format on
6785 for (unsigned K = 0; K < NumParts; ++K) {
6786 auto WordShiftKConst = MIRBuilder.buildConstant(Res: ShiftAmtTy, Val: K);
6787 auto IsWordShiftK = MIRBuilder.buildICmp(Pred: ICmpInst::ICMP_EQ, Res: BoolTy,
6788 Op0: WordShift, Op1: WordShiftKConst);
6789
6790 // Calculate source indices for this word shift
6791 //
6792 // For 4-part 128-bit value with K=1 word shift:
6793 // SHL: [3][2][1][0] << K => [2][1][0][Z]
6794 // -> (MainIdx = I-K, CarryIdx = I-K-1)
6795 // LSHR: [3][2][1][0] >> K => [Z][3][2][1]
6796 // -> (MainIdx = I+K, CarryIdx = I+K+1)
6797 int MainSrcIdx;
6798 int CarrySrcIdx; // Index for the word that provides the carried-in bits.
6799
6800 switch (MI.getOpcode()) {
6801 case TargetOpcode::G_SHL:
6802 MainSrcIdx = (int)I - (int)K;
6803 CarrySrcIdx = MainSrcIdx - 1;
6804 break;
6805 case TargetOpcode::G_LSHR:
6806 case TargetOpcode::G_ASHR:
6807 MainSrcIdx = (int)I + (int)K;
6808 CarrySrcIdx = MainSrcIdx + 1;
6809 break;
6810 default:
6811 llvm_unreachable("Not a shift");
6812 }
6813
6814 // Check bounds and build the result for this word shift
6815 Register ResultForK;
6816 if (MainSrcIdx >= 0 && MainSrcIdx < (int)NumParts) {
6817 Register MainOp = SrcParts[MainSrcIdx];
6818 Register CarryOp;
6819
6820 // Determine carry operand with bounds checking
6821 if (CarrySrcIdx >= 0 && CarrySrcIdx < (int)NumParts)
6822 CarryOp = SrcParts[CarrySrcIdx];
6823 else if (MI.getOpcode() == TargetOpcode::G_ASHR &&
6824 CarrySrcIdx >= (int)NumParts)
6825 CarryOp = FillValue; // Use sign extension
6826
6827 ResultForK = buildVariableShiftPart(Opcode: MI.getOpcode(), MainOperand: MainOp, ShiftAmt: BitShift,
6828 TargetTy, CarryOperand: CarryOp);
6829 } else {
6830 // Out of bounds - use fill value for this k
6831 ResultForK = FillValue;
6832 }
6833
6834 // Select this result if WordShift equals k
6835 InBoundsResult =
6836 MIRBuilder
6837 .buildSelect(Res: TargetTy, Tst: IsWordShiftK, Op0: ResultForK, Op1: InBoundsResult)
6838 .getReg(Idx: 0);
6839 }
6840
6841 // Handle zero-shift special case: if shift is 0, use original input
6842 DstParts[I] =
6843 MIRBuilder
6844 .buildSelect(Res: TargetTy, Tst: IsZeroShift, Op0: SrcParts[I], Op1: InBoundsResult)
6845 .getReg(Idx: 0);
6846 }
6847
6848 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: DstParts);
6849 MI.eraseFromParent();
6850 return Legalized;
6851}
6852
6853LegalizerHelper::LegalizeResult
6854LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
6855 LLT MoreTy) {
6856 assert(TypeIdx == 0 && "Expecting only Idx 0");
6857
6858 Observer.changingInstr(MI);
6859 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
6860 MachineBasicBlock &OpMBB = *MI.getOperand(i: I + 1).getMBB();
6861 MIRBuilder.setInsertPt(MBB&: OpMBB, II: OpMBB.getFirstTerminator());
6862 moreElementsVectorSrc(MI, MoreTy, OpIdx: I);
6863 }
6864
6865 MachineBasicBlock &MBB = *MI.getParent();
6866 MIRBuilder.setInsertPt(MBB, II: --MBB.getFirstNonPHI());
6867 moreElementsVectorDst(MI, WideTy: MoreTy, OpIdx: 0);
6868 Observer.changedInstr(MI);
6869 return Legalized;
6870}
6871
6872MachineInstrBuilder LegalizerHelper::getNeutralElementForVecReduce(
6873 unsigned Opcode, MachineIRBuilder &MIRBuilder, LLT Ty) {
6874 assert(Ty.isScalar() && "Expected scalar type to make neutral element for");
6875
6876 switch (Opcode) {
6877 default:
6878 llvm_unreachable(
6879 "getNeutralElementForVecReduce called with invalid opcode!");
6880 case TargetOpcode::G_VECREDUCE_ADD:
6881 case TargetOpcode::G_VECREDUCE_OR:
6882 case TargetOpcode::G_VECREDUCE_XOR:
6883 case TargetOpcode::G_VECREDUCE_UMAX:
6884 return MIRBuilder.buildConstant(Res: Ty, Val: 0);
6885 case TargetOpcode::G_VECREDUCE_MUL:
6886 return MIRBuilder.buildConstant(Res: Ty, Val: 1);
6887 case TargetOpcode::G_VECREDUCE_AND:
6888 case TargetOpcode::G_VECREDUCE_UMIN:
6889 return MIRBuilder.buildConstant(
6890 Res: Ty, Val: APInt::getAllOnes(numBits: Ty.getScalarSizeInBits()));
6891 case TargetOpcode::G_VECREDUCE_SMAX:
6892 return MIRBuilder.buildConstant(
6893 Res: Ty, Val: APInt::getSignedMinValue(numBits: Ty.getSizeInBits()));
6894 case TargetOpcode::G_VECREDUCE_SMIN:
6895 return MIRBuilder.buildConstant(
6896 Res: Ty, Val: APInt::getSignedMaxValue(numBits: Ty.getSizeInBits()));
6897 case TargetOpcode::G_VECREDUCE_FADD:
6898 return MIRBuilder.buildFConstant(Res: Ty, Val: -0.0);
6899 case TargetOpcode::G_VECREDUCE_FMUL:
6900 return MIRBuilder.buildFConstant(Res: Ty, Val: 1.0);
6901 case TargetOpcode::G_VECREDUCE_FMINIMUM:
6902 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
6903 assert(false && "getNeutralElementForVecReduce unimplemented for "
6904 "G_VECREDUCE_FMINIMUM and G_VECREDUCE_FMAXIMUM!");
6905 }
6906 llvm_unreachable("switch expected to return!");
6907}
6908
6909LegalizerHelper::LegalizeResult
6910LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
6911 LLT MoreTy) {
6912 unsigned Opc = MI.getOpcode();
6913 switch (Opc) {
6914 case TargetOpcode::G_IMPLICIT_DEF:
6915 case TargetOpcode::G_LOAD: {
6916 if (TypeIdx != 0)
6917 return UnableToLegalize;
6918 Observer.changingInstr(MI);
6919 moreElementsVectorDst(MI, WideTy: MoreTy, OpIdx: 0);
6920 Observer.changedInstr(MI);
6921 return Legalized;
6922 }
6923 case TargetOpcode::G_STORE:
6924 if (TypeIdx != 0)
6925 return UnableToLegalize;
6926 Observer.changingInstr(MI);
6927 moreElementsVectorSrc(MI, MoreTy, OpIdx: 0);
6928 Observer.changedInstr(MI);
6929 return Legalized;
6930 case TargetOpcode::G_AND:
6931 case TargetOpcode::G_OR:
6932 case TargetOpcode::G_XOR:
6933 case TargetOpcode::G_ADD:
6934 case TargetOpcode::G_SUB:
6935 case TargetOpcode::G_MUL:
6936 case TargetOpcode::G_FADD:
6937 case TargetOpcode::G_FSUB:
6938 case TargetOpcode::G_FMUL:
6939 case TargetOpcode::G_FDIV:
6940 case TargetOpcode::G_FCOPYSIGN:
6941 case TargetOpcode::G_UADDSAT:
6942 case TargetOpcode::G_USUBSAT:
6943 case TargetOpcode::G_SADDSAT:
6944 case TargetOpcode::G_SSUBSAT:
6945 case TargetOpcode::G_SMIN:
6946 case TargetOpcode::G_SMAX:
6947 case TargetOpcode::G_UMIN:
6948 case TargetOpcode::G_UMAX:
6949 case TargetOpcode::G_FMINNUM:
6950 case TargetOpcode::G_FMAXNUM:
6951 case TargetOpcode::G_FMINNUM_IEEE:
6952 case TargetOpcode::G_FMAXNUM_IEEE:
6953 case TargetOpcode::G_FMINIMUM:
6954 case TargetOpcode::G_FMAXIMUM:
6955 case TargetOpcode::G_FMINIMUMNUM:
6956 case TargetOpcode::G_FMAXIMUMNUM:
6957 case TargetOpcode::G_STRICT_FADD:
6958 case TargetOpcode::G_STRICT_FSUB:
6959 case TargetOpcode::G_STRICT_FMUL: {
6960 Observer.changingInstr(MI);
6961 moreElementsVectorSrc(MI, MoreTy, OpIdx: 1);
6962 moreElementsVectorSrc(MI, MoreTy, OpIdx: 2);
6963 moreElementsVectorDst(MI, WideTy: MoreTy, OpIdx: 0);
6964 Observer.changedInstr(MI);
6965 return Legalized;
6966 }
6967 case TargetOpcode::G_SHL:
6968 case TargetOpcode::G_ASHR:
6969 case TargetOpcode::G_LSHR: {
6970 Observer.changingInstr(MI);
6971 moreElementsVectorSrc(MI, MoreTy, OpIdx: 1);
6972 // The shift operand may have a different scalar type from the source and
6973 // destination operands.
6974 LLT ShiftMoreTy = MoreTy.changeElementType(
6975 NewEltTy: MRI.getType(Reg: MI.getOperand(i: 2).getReg()).getElementType());
6976 moreElementsVectorSrc(MI, MoreTy: ShiftMoreTy, OpIdx: 2);
6977 moreElementsVectorDst(MI, WideTy: MoreTy, OpIdx: 0);
6978 Observer.changedInstr(MI);
6979 return Legalized;
6980 }
6981 case TargetOpcode::G_FMA:
6982 case TargetOpcode::G_STRICT_FMA:
6983 case TargetOpcode::G_FSHR:
6984 case TargetOpcode::G_FSHL: {
6985 Observer.changingInstr(MI);
6986 moreElementsVectorSrc(MI, MoreTy, OpIdx: 1);
6987 moreElementsVectorSrc(MI, MoreTy, OpIdx: 2);
6988 moreElementsVectorSrc(MI, MoreTy, OpIdx: 3);
6989 moreElementsVectorDst(MI, WideTy: MoreTy, OpIdx: 0);
6990 Observer.changedInstr(MI);
6991 return Legalized;
6992 }
6993 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
6994 case TargetOpcode::G_EXTRACT:
6995 if (TypeIdx != 1)
6996 return UnableToLegalize;
6997 Observer.changingInstr(MI);
6998 moreElementsVectorSrc(MI, MoreTy, OpIdx: 1);
6999 Observer.changedInstr(MI);
7000 return Legalized;
7001 case TargetOpcode::G_INSERT:
7002 case TargetOpcode::G_INSERT_VECTOR_ELT:
7003 case TargetOpcode::G_FREEZE:
7004 case TargetOpcode::G_FNEG:
7005 case TargetOpcode::G_FABS:
7006 case TargetOpcode::G_FSQRT:
7007 case TargetOpcode::G_FCEIL:
7008 case TargetOpcode::G_FFLOOR:
7009 case TargetOpcode::G_FNEARBYINT:
7010 case TargetOpcode::G_FRINT:
7011 case TargetOpcode::G_INTRINSIC_ROUND:
7012 case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
7013 case TargetOpcode::G_INTRINSIC_TRUNC:
7014 case TargetOpcode::G_BITREVERSE:
7015 case TargetOpcode::G_BSWAP:
7016 case TargetOpcode::G_FCANONICALIZE:
7017 case TargetOpcode::G_SEXT_INREG:
7018 case TargetOpcode::G_ABS:
7019 case TargetOpcode::G_CTLZ:
7020 case TargetOpcode::G_CTPOP:
7021 if (TypeIdx != 0)
7022 return UnableToLegalize;
7023 Observer.changingInstr(MI);
7024 moreElementsVectorSrc(MI, MoreTy, OpIdx: 1);
7025 moreElementsVectorDst(MI, WideTy: MoreTy, OpIdx: 0);
7026 Observer.changedInstr(MI);
7027 return Legalized;
7028 case TargetOpcode::G_SELECT: {
7029 auto [DstReg, DstTy, CondReg, CondTy] = MI.getFirst2RegLLTs();
7030 if (TypeIdx == 1) {
7031 if (!CondTy.isScalar() ||
7032 DstTy.getElementCount() != MoreTy.getElementCount())
7033 return UnableToLegalize;
7034
7035 // This is turning a scalar select of vectors into a vector
7036 // select. Broadcast the select condition.
7037 auto ShufSplat = MIRBuilder.buildShuffleSplat(Res: MoreTy, Src: CondReg);
7038 Observer.changingInstr(MI);
7039 MI.getOperand(i: 1).setReg(ShufSplat.getReg(Idx: 0));
7040 Observer.changedInstr(MI);
7041 return Legalized;
7042 }
7043
7044 if (CondTy.isVector())
7045 return UnableToLegalize;
7046
7047 Observer.changingInstr(MI);
7048 moreElementsVectorSrc(MI, MoreTy, OpIdx: 2);
7049 moreElementsVectorSrc(MI, MoreTy, OpIdx: 3);
7050 moreElementsVectorDst(MI, WideTy: MoreTy, OpIdx: 0);
7051 Observer.changedInstr(MI);
7052 return Legalized;
7053 }
7054 case TargetOpcode::G_UNMERGE_VALUES:
7055 return UnableToLegalize;
7056 case TargetOpcode::G_PHI:
7057 return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
7058 case TargetOpcode::G_SHUFFLE_VECTOR:
7059 return moreElementsVectorShuffle(MI, TypeIdx, MoreTy);
7060 case TargetOpcode::G_BUILD_VECTOR: {
7061 SmallVector<SrcOp, 8> Elts;
7062 for (auto Op : MI.uses()) {
7063 Elts.push_back(Elt: Op.getReg());
7064 }
7065
7066 for (unsigned i = Elts.size(); i < MoreTy.getNumElements(); ++i) {
7067 Elts.push_back(Elt: MIRBuilder.buildUndef(Res: MoreTy.getScalarType()));
7068 }
7069
7070 MIRBuilder.buildDeleteTrailingVectorElements(
7071 Res: MI.getOperand(i: 0).getReg(), Op0: MIRBuilder.buildInstr(Opc, DstOps: {MoreTy}, SrcOps: Elts));
7072 MI.eraseFromParent();
7073 return Legalized;
7074 }
7075 case TargetOpcode::G_SEXT:
7076 case TargetOpcode::G_ZEXT:
7077 case TargetOpcode::G_ANYEXT:
7078 case TargetOpcode::G_TRUNC:
7079 case TargetOpcode::G_FPTRUNC:
7080 case TargetOpcode::G_FPEXT:
7081 case TargetOpcode::G_FPTOSI:
7082 case TargetOpcode::G_FPTOUI:
7083 case TargetOpcode::G_FPTOSI_SAT:
7084 case TargetOpcode::G_FPTOUI_SAT:
7085 case TargetOpcode::G_SITOFP:
7086 case TargetOpcode::G_UITOFP:
7087 case TargetOpcode::G_TRUNC_SSAT_S:
7088 case TargetOpcode::G_TRUNC_SSAT_U:
7089 case TargetOpcode::G_TRUNC_USAT_U: {
7090 Observer.changingInstr(MI);
7091 LLT SrcExtTy;
7092 LLT DstExtTy;
7093 if (TypeIdx == 0) {
7094 DstExtTy = MoreTy;
7095 SrcExtTy = MoreTy.changeElementType(
7096 NewEltTy: MRI.getType(Reg: MI.getOperand(i: 1).getReg()).getElementType());
7097 } else {
7098 DstExtTy = MoreTy.changeElementType(
7099 NewEltTy: MRI.getType(Reg: MI.getOperand(i: 0).getReg()).getElementType());
7100 SrcExtTy = MoreTy;
7101 }
7102 moreElementsVectorSrc(MI, MoreTy: SrcExtTy, OpIdx: 1);
7103 moreElementsVectorDst(MI, WideTy: DstExtTy, OpIdx: 0);
7104 Observer.changedInstr(MI);
7105 return Legalized;
7106 }
7107 case TargetOpcode::G_ICMP:
7108 case TargetOpcode::G_FCMP: {
7109 if (TypeIdx != 1)
7110 return UnableToLegalize;
7111
7112 Observer.changingInstr(MI);
7113 moreElementsVectorSrc(MI, MoreTy, OpIdx: 2);
7114 moreElementsVectorSrc(MI, MoreTy, OpIdx: 3);
7115 LLT CondTy = MoreTy.changeVectorElementType(
7116 NewEltTy: MRI.getType(Reg: MI.getOperand(i: 0).getReg()).getElementType());
7117 moreElementsVectorDst(MI, WideTy: CondTy, OpIdx: 0);
7118 Observer.changedInstr(MI);
7119 return Legalized;
7120 }
7121 case TargetOpcode::G_BITCAST: {
7122 if (TypeIdx != 0)
7123 return UnableToLegalize;
7124
7125 LLT SrcTy = MRI.getType(Reg: MI.getOperand(i: 1).getReg());
7126 LLT DstTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
7127
7128 unsigned coefficient = SrcTy.getNumElements() * MoreTy.getNumElements();
7129 if (coefficient % DstTy.getNumElements() != 0)
7130 return UnableToLegalize;
7131
7132 coefficient = coefficient / DstTy.getNumElements();
7133
7134 LLT NewTy = SrcTy.changeElementCount(
7135 EC: ElementCount::get(MinVal: coefficient, Scalable: MoreTy.isScalable()));
7136 Observer.changingInstr(MI);
7137 moreElementsVectorSrc(MI, MoreTy: NewTy, OpIdx: 1);
7138 moreElementsVectorDst(MI, WideTy: MoreTy, OpIdx: 0);
7139 Observer.changedInstr(MI);
7140 return Legalized;
7141 }
7142 case TargetOpcode::G_VECREDUCE_FADD:
7143 case TargetOpcode::G_VECREDUCE_FMUL:
7144 case TargetOpcode::G_VECREDUCE_ADD:
7145 case TargetOpcode::G_VECREDUCE_MUL:
7146 case TargetOpcode::G_VECREDUCE_AND:
7147 case TargetOpcode::G_VECREDUCE_OR:
7148 case TargetOpcode::G_VECREDUCE_XOR:
7149 case TargetOpcode::G_VECREDUCE_SMAX:
7150 case TargetOpcode::G_VECREDUCE_SMIN:
7151 case TargetOpcode::G_VECREDUCE_UMAX:
7152 case TargetOpcode::G_VECREDUCE_UMIN: {
7153 LLT OrigTy = MRI.getType(Reg: MI.getOperand(i: 1).getReg());
7154 MachineOperand &MO = MI.getOperand(i: 1);
7155 auto NewVec = MIRBuilder.buildPadVectorWithUndefElements(Res: MoreTy, Op0: MO);
7156 auto NeutralElement = getNeutralElementForVecReduce(
7157 Opcode: MI.getOpcode(), MIRBuilder, Ty: MoreTy.getElementType());
7158
7159 LLT IdxTy(TLI.getVectorIdxLLT(DL: MIRBuilder.getDataLayout()));
7160 for (size_t i = OrigTy.getNumElements(), e = MoreTy.getNumElements();
7161 i != e; i++) {
7162 auto Idx = MIRBuilder.buildConstant(Res: IdxTy, Val: i);
7163 NewVec = MIRBuilder.buildInsertVectorElement(Res: MoreTy, Val: NewVec,
7164 Elt: NeutralElement, Idx);
7165 }
7166
7167 Observer.changingInstr(MI);
7168 MO.setReg(NewVec.getReg(Idx: 0));
7169 Observer.changedInstr(MI);
7170 return Legalized;
7171 }
7172
7173 default:
7174 return UnableToLegalize;
7175 }
7176}
7177
7178LegalizerHelper::LegalizeResult
7179LegalizerHelper::equalizeVectorShuffleLengths(MachineInstr &MI) {
7180 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
7181 ArrayRef<int> Mask = MI.getOperand(i: 3).getShuffleMask();
7182 unsigned MaskNumElts = Mask.size();
7183 unsigned SrcNumElts = SrcTy.getNumElements();
7184 LLT DestEltTy = DstTy.getElementType();
7185
7186 if (MaskNumElts == SrcNumElts)
7187 return Legalized;
7188
7189 if (MaskNumElts < SrcNumElts) {
7190 // Extend mask to match new destination vector size with
7191 // undef values.
7192 SmallVector<int, 16> NewMask(SrcNumElts, -1);
7193 llvm::copy(Range&: Mask, Out: NewMask.begin());
7194
7195 moreElementsVectorDst(MI, WideTy: SrcTy, OpIdx: 0);
7196 MIRBuilder.setInstrAndDebugLoc(MI);
7197 MIRBuilder.buildShuffleVector(Res: MI.getOperand(i: 0).getReg(),
7198 Src1: MI.getOperand(i: 1).getReg(),
7199 Src2: MI.getOperand(i: 2).getReg(), Mask: NewMask);
7200 MI.eraseFromParent();
7201
7202 return Legalized;
7203 }
7204
7205 unsigned PaddedMaskNumElts = alignTo(Value: MaskNumElts, Align: SrcNumElts);
7206 unsigned NumConcat = PaddedMaskNumElts / SrcNumElts;
7207 LLT PaddedTy =
7208 DstTy.changeVectorElementCount(EC: ElementCount::getFixed(MinVal: PaddedMaskNumElts));
7209
7210 // Create new source vectors by concatenating the initial
7211 // source vectors with undefined vectors of the same size.
7212 auto Undef = MIRBuilder.buildUndef(Res: SrcTy);
7213 SmallVector<Register, 8> MOps1(NumConcat, Undef.getReg(Idx: 0));
7214 SmallVector<Register, 8> MOps2(NumConcat, Undef.getReg(Idx: 0));
7215 MOps1[0] = MI.getOperand(i: 1).getReg();
7216 MOps2[0] = MI.getOperand(i: 2).getReg();
7217
7218 auto Src1 = MIRBuilder.buildConcatVectors(Res: PaddedTy, Ops: MOps1);
7219 auto Src2 = MIRBuilder.buildConcatVectors(Res: PaddedTy, Ops: MOps2);
7220
7221 // Readjust mask for new input vector length.
7222 SmallVector<int, 8> MappedOps(PaddedMaskNumElts, -1);
7223 for (unsigned I = 0; I != MaskNumElts; ++I) {
7224 int Idx = Mask[I];
7225 if (Idx >= static_cast<int>(SrcNumElts))
7226 Idx += PaddedMaskNumElts - SrcNumElts;
7227 MappedOps[I] = Idx;
7228 }
7229
7230 // If we got more elements than required, extract subvector.
7231 if (MaskNumElts != PaddedMaskNumElts) {
7232 auto Shuffle =
7233 MIRBuilder.buildShuffleVector(Res: PaddedTy, Src1, Src2, Mask: MappedOps);
7234
7235 SmallVector<Register, 16> Elts(MaskNumElts);
7236 for (unsigned I = 0; I < MaskNumElts; ++I) {
7237 Elts[I] =
7238 MIRBuilder.buildExtractVectorElementConstant(Res: DestEltTy, Val: Shuffle, Idx: I)
7239 .getReg(Idx: 0);
7240 }
7241 MIRBuilder.buildBuildVector(Res: DstReg, Ops: Elts);
7242 } else {
7243 MIRBuilder.buildShuffleVector(Res: DstReg, Src1, Src2, Mask: MappedOps);
7244 }
7245
7246 MI.eraseFromParent();
7247 return LegalizerHelper::LegalizeResult::Legalized;
7248}
7249
7250LegalizerHelper::LegalizeResult
7251LegalizerHelper::moreElementsVectorShuffle(MachineInstr &MI,
7252 unsigned int TypeIdx, LLT MoreTy) {
7253 auto [DstTy, Src1Ty, Src2Ty] = MI.getFirst3LLTs();
7254 ArrayRef<int> Mask = MI.getOperand(i: 3).getShuffleMask();
7255 unsigned NumElts = DstTy.getNumElements();
7256 unsigned WidenNumElts = MoreTy.getNumElements();
7257
7258 if (DstTy.isVector() && Src1Ty.isVector() &&
7259 DstTy.getNumElements() != Src1Ty.getNumElements()) {
7260 return equalizeVectorShuffleLengths(MI);
7261 }
7262
7263 if (TypeIdx != 0)
7264 return UnableToLegalize;
7265
7266 // Expect a canonicalized shuffle.
7267 if (DstTy != Src1Ty || DstTy != Src2Ty)
7268 return UnableToLegalize;
7269
7270 moreElementsVectorSrc(MI, MoreTy, OpIdx: 1);
7271 moreElementsVectorSrc(MI, MoreTy, OpIdx: 2);
7272
7273 // Adjust mask based on new input vector length.
7274 SmallVector<int, 16> NewMask(WidenNumElts, -1);
7275 for (unsigned I = 0; I != NumElts; ++I) {
7276 int Idx = Mask[I];
7277 if (Idx < static_cast<int>(NumElts))
7278 NewMask[I] = Idx;
7279 else
7280 NewMask[I] = Idx - NumElts + WidenNumElts;
7281 }
7282 moreElementsVectorDst(MI, WideTy: MoreTy, OpIdx: 0);
7283 MIRBuilder.setInstrAndDebugLoc(MI);
7284 MIRBuilder.buildShuffleVector(Res: MI.getOperand(i: 0).getReg(),
7285 Src1: MI.getOperand(i: 1).getReg(),
7286 Src2: MI.getOperand(i: 2).getReg(), Mask: NewMask);
7287 MI.eraseFromParent();
7288 return Legalized;
7289}
7290
7291void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
7292 ArrayRef<Register> Src1Regs,
7293 ArrayRef<Register> Src2Regs,
7294 LLT NarrowTy) {
7295 MachineIRBuilder &B = MIRBuilder;
7296 unsigned SrcParts = Src1Regs.size();
7297 unsigned DstParts = DstRegs.size();
7298
7299 unsigned DstIdx = 0; // Low bits of the result.
7300 Register FactorSum =
7301 B.buildMul(Dst: NarrowTy, Src0: Src1Regs[DstIdx], Src1: Src2Regs[DstIdx]).getReg(Idx: 0);
7302 DstRegs[DstIdx] = FactorSum;
7303
7304 Register CarrySumPrevDstIdx;
7305 SmallVector<Register, 4> Factors;
7306
7307 for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
7308 // Collect high parts of muls from previous DstIdx.
7309 for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
7310 i <= std::min(a: DstIdx - 1, b: SrcParts - 1); ++i) {
7311 MachineInstrBuilder Umulh =
7312 B.buildUMulH(Dst: NarrowTy, Src0: Src1Regs[DstIdx - 1 - i], Src1: Src2Regs[i]);
7313 Factors.push_back(Elt: Umulh.getReg(Idx: 0));
7314 }
7315 // Collect low parts of muls for DstIdx. Visit the diagonal starting with
7316 // the low Src1 part, so multiply-add selectors can use it as the first
7317 // accumulated cross product.
7318 unsigned LowStart = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
7319 unsigned LowEnd = std::min(a: DstIdx, b: SrcParts - 1);
7320 for (unsigned RevI = LowEnd + 1; RevI != LowStart; --RevI) {
7321 unsigned i = RevI - 1;
7322 MachineInstrBuilder Mul =
7323 B.buildMul(Dst: NarrowTy, Src0: Src1Regs[DstIdx - i], Src1: Src2Regs[i]);
7324 Factors.push_back(Elt: Mul.getReg(Idx: 0));
7325 }
7326 // Add CarrySum from additions calculated for previous DstIdx.
7327 if (DstIdx != 1) {
7328 Factors.push_back(Elt: CarrySumPrevDstIdx);
7329 }
7330
7331 Register CarrySum;
7332 // Add all factors and accumulate all carries into CarrySum.
7333 if (DstIdx != DstParts - 1) {
7334 MachineInstrBuilder Uaddo =
7335 B.buildUAddo(Res: NarrowTy, CarryOut: LLT::integer(SizeInBits: 1), Op0: Factors[0], Op1: Factors[1]);
7336 FactorSum = Uaddo.getReg(Idx: 0);
7337 CarrySum = B.buildZExt(Res: NarrowTy, Op: Uaddo.getReg(Idx: 1)).getReg(Idx: 0);
7338 for (unsigned i = 2; i < Factors.size(); ++i) {
7339 MachineInstrBuilder Uaddo =
7340 B.buildUAddo(Res: NarrowTy, CarryOut: LLT::integer(SizeInBits: 1), Op0: FactorSum, Op1: Factors[i]);
7341 FactorSum = Uaddo.getReg(Idx: 0);
7342 MachineInstrBuilder Carry = B.buildZExt(Res: NarrowTy, Op: Uaddo.getReg(Idx: 1));
7343 CarrySum = B.buildAdd(Dst: NarrowTy, Src0: CarrySum, Src1: Carry).getReg(Idx: 0);
7344 }
7345 } else {
7346 // Since value for the next index is not calculated, neither is CarrySum.
7347 FactorSum = B.buildAdd(Dst: NarrowTy, Src0: Factors[0], Src1: Factors[1]).getReg(Idx: 0);
7348 for (unsigned i = 2; i < Factors.size(); ++i)
7349 FactorSum = B.buildAdd(Dst: NarrowTy, Src0: FactorSum, Src1: Factors[i]).getReg(Idx: 0);
7350 }
7351
7352 CarrySumPrevDstIdx = CarrySum;
7353 DstRegs[DstIdx] = FactorSum;
7354 Factors.clear();
7355 }
7356}
7357
7358LegalizerHelper::LegalizeResult
7359LegalizerHelper::narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx,
7360 LLT NarrowTy) {
7361 if (TypeIdx != 0)
7362 return UnableToLegalize;
7363
7364 Register DstReg = MI.getOperand(i: 0).getReg();
7365 LLT DstType = MRI.getType(Reg: DstReg);
7366 // FIXME: add support for vector types
7367 if (DstType.isVector())
7368 return UnableToLegalize;
7369
7370 unsigned Opcode = MI.getOpcode();
7371 unsigned OpO, OpE, OpF;
7372 switch (Opcode) {
7373 case TargetOpcode::G_SADDO:
7374 case TargetOpcode::G_SADDE:
7375 case TargetOpcode::G_UADDO:
7376 case TargetOpcode::G_UADDE:
7377 case TargetOpcode::G_ADD:
7378 OpO = TargetOpcode::G_UADDO;
7379 OpE = TargetOpcode::G_UADDE;
7380 OpF = TargetOpcode::G_UADDE;
7381 if (Opcode == TargetOpcode::G_SADDO || Opcode == TargetOpcode::G_SADDE)
7382 OpF = TargetOpcode::G_SADDE;
7383 break;
7384 case TargetOpcode::G_SSUBO:
7385 case TargetOpcode::G_SSUBE:
7386 case TargetOpcode::G_USUBO:
7387 case TargetOpcode::G_USUBE:
7388 case TargetOpcode::G_SUB:
7389 OpO = TargetOpcode::G_USUBO;
7390 OpE = TargetOpcode::G_USUBE;
7391 OpF = TargetOpcode::G_USUBE;
7392 if (Opcode == TargetOpcode::G_SSUBO || Opcode == TargetOpcode::G_SSUBE)
7393 OpF = TargetOpcode::G_SSUBE;
7394 break;
7395 default:
7396 llvm_unreachable("Unexpected add/sub opcode!");
7397 }
7398
7399 // 1 for a plain add/sub, 2 if this is an operation with a carry-out.
7400 unsigned NumDefs = MI.getNumExplicitDefs();
7401 Register Src1 = MI.getOperand(i: NumDefs).getReg();
7402 Register Src2 = MI.getOperand(i: NumDefs + 1).getReg();
7403 Register CarryDst, CarryIn;
7404 if (NumDefs == 2)
7405 CarryDst = MI.getOperand(i: 1).getReg();
7406 if (MI.getNumOperands() == NumDefs + 3)
7407 CarryIn = MI.getOperand(i: NumDefs + 2).getReg();
7408
7409 LLT RegTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
7410 LLT LeftoverTy, DummyTy;
7411 SmallVector<Register, 2> Src1Regs, Src2Regs, Src1Left, Src2Left, DstRegs;
7412 extractParts(Reg: Src1, RegTy, MainTy: NarrowTy, LeftoverTy, VRegs&: Src1Regs, LeftoverVRegs&: Src1Left,
7413 MIRBuilder, MRI);
7414 extractParts(Reg: Src2, RegTy, MainTy: NarrowTy, LeftoverTy&: DummyTy, VRegs&: Src2Regs, LeftoverVRegs&: Src2Left, MIRBuilder,
7415 MRI);
7416
7417 int NarrowParts = Src1Regs.size();
7418 Src1Regs.append(RHS: Src1Left);
7419 Src2Regs.append(RHS: Src2Left);
7420 DstRegs.reserve(N: Src1Regs.size());
7421
7422 for (int i = 0, e = Src1Regs.size(); i != e; ++i) {
7423 Register DstReg =
7424 MRI.createGenericVirtualRegister(Ty: MRI.getType(Reg: Src1Regs[i]));
7425 Register CarryOut;
7426 // Forward the final carry-out to the destination register
7427 if (i == e - 1 && CarryDst)
7428 CarryOut = CarryDst;
7429 else
7430 CarryOut = MRI.createGenericVirtualRegister(Ty: LLT::integer(SizeInBits: 1));
7431
7432 if (!CarryIn) {
7433 MIRBuilder.buildInstr(Opc: OpO, DstOps: {DstReg, CarryOut},
7434 SrcOps: {Src1Regs[i], Src2Regs[i]});
7435 } else if (i == e - 1) {
7436 MIRBuilder.buildInstr(Opc: OpF, DstOps: {DstReg, CarryOut},
7437 SrcOps: {Src1Regs[i], Src2Regs[i], CarryIn});
7438 } else {
7439 MIRBuilder.buildInstr(Opc: OpE, DstOps: {DstReg, CarryOut},
7440 SrcOps: {Src1Regs[i], Src2Regs[i], CarryIn});
7441 }
7442
7443 DstRegs.push_back(Elt: DstReg);
7444 CarryIn = CarryOut;
7445 }
7446 insertParts(DstReg: MI.getOperand(i: 0).getReg(), ResultTy: RegTy, PartTy: NarrowTy,
7447 PartRegs: ArrayRef(DstRegs).take_front(N: NarrowParts), LeftoverTy,
7448 LeftoverRegs: ArrayRef(DstRegs).drop_front(N: NarrowParts));
7449
7450 MI.eraseFromParent();
7451 return Legalized;
7452}
7453
7454LegalizerHelper::LegalizeResult
7455LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
7456 auto [DstReg, Src1, Src2] = MI.getFirst3Regs();
7457
7458 LLT Ty = MRI.getType(Reg: DstReg);
7459 if (Ty.isVector())
7460 return UnableToLegalize;
7461
7462 unsigned Size = Ty.getSizeInBits();
7463 unsigned NarrowSize = NarrowTy.getSizeInBits();
7464 if (Size % NarrowSize != 0)
7465 return UnableToLegalize;
7466
7467 unsigned NumParts = Size / NarrowSize;
7468 bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
7469 unsigned DstTmpParts = NumParts * (IsMulHigh ? 2 : 1);
7470
7471 SmallVector<Register, 2> Src1Parts, Src2Parts;
7472 SmallVector<Register, 2> DstTmpRegs(DstTmpParts);
7473 extractParts(Reg: Src1, Ty: NarrowTy, NumParts, VRegs&: Src1Parts, MIRBuilder, MRI);
7474 extractParts(Reg: Src2, Ty: NarrowTy, NumParts, VRegs&: Src2Parts, MIRBuilder, MRI);
7475 multiplyRegisters(DstRegs&: DstTmpRegs, Src1Regs: Src1Parts, Src2Regs: Src2Parts, NarrowTy);
7476
7477 // Take only high half of registers if this is high mul.
7478 ArrayRef<Register> DstRegs(&DstTmpRegs[DstTmpParts - NumParts], NumParts);
7479 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: DstRegs);
7480 MI.eraseFromParent();
7481 return Legalized;
7482}
7483
7484LegalizerHelper::LegalizeResult
7485LegalizerHelper::narrowScalarFPTOI(MachineInstr &MI, unsigned TypeIdx,
7486 LLT NarrowTy) {
7487 if (TypeIdx != 0)
7488 return UnableToLegalize;
7489
7490 bool IsSigned = MI.getOpcode() == TargetOpcode::G_FPTOSI;
7491
7492 Register Src = MI.getOperand(i: 1).getReg();
7493 LLT SrcTy = MRI.getType(Reg: Src);
7494
7495 // If all finite floats fit into the narrowed integer type, we can just swap
7496 // out the result type. This is practically only useful for conversions from
7497 // half to at least 16-bits, so just handle the one case.
7498 if (SrcTy.getScalarType() != LLT::scalar(SizeInBits: 16) ||
7499 NarrowTy.getScalarSizeInBits() < (IsSigned ? 17u : 16u))
7500 return UnableToLegalize;
7501
7502 Observer.changingInstr(MI);
7503 narrowScalarDst(MI, NarrowTy, OpIdx: 0,
7504 ExtOpcode: IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT);
7505 Observer.changedInstr(MI);
7506 return Legalized;
7507}
7508
7509LegalizerHelper::LegalizeResult
7510LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
7511 LLT NarrowTy) {
7512 if (TypeIdx != 1)
7513 return UnableToLegalize;
7514
7515 uint64_t NarrowSize = NarrowTy.getSizeInBits();
7516
7517 int64_t SizeOp1 = MRI.getType(Reg: MI.getOperand(i: 1).getReg()).getSizeInBits();
7518 // FIXME: add support for when SizeOp1 isn't an exact multiple of
7519 // NarrowSize.
7520 if (SizeOp1 % NarrowSize != 0)
7521 return UnableToLegalize;
7522 int NumParts = SizeOp1 / NarrowSize;
7523
7524 SmallVector<Register, 2> SrcRegs, DstRegs;
7525 extractParts(Reg: MI.getOperand(i: 1).getReg(), Ty: NarrowTy, NumParts, VRegs&: SrcRegs,
7526 MIRBuilder, MRI);
7527
7528 Register OpReg = MI.getOperand(i: 0).getReg();
7529 uint64_t OpStart = MI.getOperand(i: 2).getImm();
7530 uint64_t OpSize = MRI.getType(Reg: OpReg).getSizeInBits();
7531 for (int i = 0; i < NumParts; ++i) {
7532 unsigned SrcStart = i * NarrowSize;
7533
7534 if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
7535 // No part of the extract uses this subregister, ignore it.
7536 continue;
7537 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(Reg: OpReg)) {
7538 // The entire subregister is extracted, forward the value.
7539 DstRegs.push_back(Elt: SrcRegs[i]);
7540 continue;
7541 }
7542
7543 // OpSegStart is where this destination segment would start in OpReg if it
7544 // extended infinitely in both directions.
7545 int64_t ExtractOffset;
7546 uint64_t SegSize;
7547 if (OpStart < SrcStart) {
7548 ExtractOffset = 0;
7549 SegSize = std::min(a: NarrowSize, b: OpStart + OpSize - SrcStart);
7550 } else {
7551 ExtractOffset = OpStart - SrcStart;
7552 SegSize = std::min(a: SrcStart + NarrowSize - OpStart, b: OpSize);
7553 }
7554
7555 Register SegReg = SrcRegs[i];
7556 if (ExtractOffset != 0 || SegSize != NarrowSize) {
7557 // A genuine extract is needed.
7558 SegReg = MRI.createGenericVirtualRegister(Ty: LLT::integer(SizeInBits: SegSize));
7559 MIRBuilder.buildExtract(Res: SegReg, Src: SrcRegs[i], Index: ExtractOffset);
7560 }
7561
7562 DstRegs.push_back(Elt: SegReg);
7563 }
7564
7565 Register DstReg = MI.getOperand(i: 0).getReg();
7566 if (MRI.getType(Reg: DstReg).isVector())
7567 MIRBuilder.buildBuildVector(Res: DstReg, Ops: DstRegs);
7568 else if (DstRegs.size() > 1)
7569 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: DstRegs);
7570 else
7571 MIRBuilder.buildCopy(Res: DstReg, Op: DstRegs[0]);
7572 MI.eraseFromParent();
7573 return Legalized;
7574}
7575
7576LegalizerHelper::LegalizeResult
7577LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
7578 LLT NarrowTy) {
7579 // FIXME: Don't know how to handle secondary types yet.
7580 if (TypeIdx != 0)
7581 return UnableToLegalize;
7582
7583 SmallVector<Register, 2> SrcRegs, LeftoverRegs, DstRegs;
7584 LLT RegTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
7585 LLT LeftoverTy;
7586 extractParts(Reg: MI.getOperand(i: 1).getReg(), RegTy, MainTy: NarrowTy, LeftoverTy, VRegs&: SrcRegs,
7587 LeftoverVRegs&: LeftoverRegs, MIRBuilder, MRI);
7588
7589 SrcRegs.append(RHS: LeftoverRegs);
7590
7591 uint64_t NarrowSize = NarrowTy.getSizeInBits();
7592 Register OpReg = MI.getOperand(i: 2).getReg();
7593 uint64_t OpStart = MI.getOperand(i: 3).getImm();
7594 uint64_t OpSize = MRI.getType(Reg: OpReg).getSizeInBits();
7595 for (int I = 0, E = SrcRegs.size(); I != E; ++I) {
7596 unsigned DstStart = I * NarrowSize;
7597
7598 if (DstStart == OpStart && NarrowTy == MRI.getType(Reg: OpReg)) {
7599 // The entire subregister is defined by this insert, forward the new
7600 // value.
7601 DstRegs.push_back(Elt: OpReg);
7602 continue;
7603 }
7604
7605 Register SrcReg = SrcRegs[I];
7606 if (MRI.getType(Reg: SrcRegs[I]) == LeftoverTy) {
7607 // The leftover reg is smaller than NarrowTy, so we need to extend it.
7608 SrcReg = MRI.createGenericVirtualRegister(Ty: NarrowTy);
7609 MIRBuilder.buildAnyExt(Res: SrcReg, Op: SrcRegs[I]);
7610 }
7611
7612 if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
7613 // No part of the insert affects this subregister, forward the original.
7614 DstRegs.push_back(Elt: SrcReg);
7615 continue;
7616 }
7617
7618 // OpSegStart is where this destination segment would start in OpReg if it
7619 // extended infinitely in both directions.
7620 int64_t ExtractOffset, InsertOffset;
7621 uint64_t SegSize;
7622 if (OpStart < DstStart) {
7623 InsertOffset = 0;
7624 ExtractOffset = DstStart - OpStart;
7625 SegSize = std::min(a: NarrowSize, b: OpStart + OpSize - DstStart);
7626 } else {
7627 InsertOffset = OpStart - DstStart;
7628 ExtractOffset = 0;
7629 SegSize =
7630 std::min(a: NarrowSize - InsertOffset, b: OpStart + OpSize - DstStart);
7631 }
7632
7633 Register SegReg = OpReg;
7634 if (ExtractOffset != 0 || SegSize != OpSize) {
7635 // A genuine extract is needed.
7636 SegReg = MRI.createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: SegSize));
7637 MIRBuilder.buildExtract(Res: SegReg, Src: OpReg, Index: ExtractOffset);
7638 }
7639
7640 Register DstReg = MRI.createGenericVirtualRegister(Ty: NarrowTy);
7641 MIRBuilder.buildInsert(Res: DstReg, Src: SrcReg, Op: SegReg, Index: InsertOffset);
7642 DstRegs.push_back(Elt: DstReg);
7643 }
7644
7645 uint64_t WideSize = DstRegs.size() * NarrowSize;
7646 Register DstReg = MI.getOperand(i: 0).getReg();
7647 if (WideSize > RegTy.getSizeInBits()) {
7648 Register MergeReg = MRI.createGenericVirtualRegister(Ty: LLT::scalar(SizeInBits: WideSize));
7649 MIRBuilder.buildMergeLikeInstr(Res: MergeReg, Ops: DstRegs);
7650 MIRBuilder.buildTrunc(Res: DstReg, Op: MergeReg);
7651 } else
7652 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: DstRegs);
7653
7654 MI.eraseFromParent();
7655 return Legalized;
7656}
7657
7658LegalizerHelper::LegalizeResult
7659LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
7660 LLT NarrowTy) {
7661 Register DstReg = MI.getOperand(i: 0).getReg();
7662 LLT DstTy = MRI.getType(Reg: DstReg);
7663
7664 assert(MI.getNumOperands() == 3 && TypeIdx == 0);
7665
7666 SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
7667 SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs;
7668 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
7669 LLT LeftoverTy;
7670 if (!extractParts(Reg: MI.getOperand(i: 1).getReg(), RegTy: DstTy, MainTy: NarrowTy, LeftoverTy,
7671 VRegs&: Src0Regs, LeftoverVRegs&: Src0LeftoverRegs, MIRBuilder, MRI))
7672 return UnableToLegalize;
7673
7674 LLT Unused;
7675 if (!extractParts(Reg: MI.getOperand(i: 2).getReg(), RegTy: DstTy, MainTy: NarrowTy, LeftoverTy&: Unused,
7676 VRegs&: Src1Regs, LeftoverVRegs&: Src1LeftoverRegs, MIRBuilder, MRI))
7677 llvm_unreachable("inconsistent extractParts result");
7678
7679 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
7680 auto Inst = MIRBuilder.buildInstr(Opc: MI.getOpcode(), DstOps: {NarrowTy},
7681 SrcOps: {Src0Regs[I], Src1Regs[I]});
7682 DstRegs.push_back(Elt: Inst.getReg(Idx: 0));
7683 }
7684
7685 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
7686 auto Inst = MIRBuilder.buildInstr(
7687 Opc: MI.getOpcode(),
7688 DstOps: {LeftoverTy}, SrcOps: {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
7689 DstLeftoverRegs.push_back(Elt: Inst.getReg(Idx: 0));
7690 }
7691
7692 insertParts(DstReg, ResultTy: DstTy, PartTy: NarrowTy, PartRegs: DstRegs,
7693 LeftoverTy, LeftoverRegs: DstLeftoverRegs);
7694
7695 MI.eraseFromParent();
7696 return Legalized;
7697}
7698
7699LegalizerHelper::LegalizeResult
7700LegalizerHelper::narrowScalarExt(MachineInstr &MI, unsigned TypeIdx,
7701 LLT NarrowTy) {
7702 if (TypeIdx != 0)
7703 return UnableToLegalize;
7704
7705 auto [DstReg, SrcReg] = MI.getFirst2Regs();
7706
7707 LLT DstTy = MRI.getType(Reg: DstReg);
7708 if (DstTy.isVector())
7709 return UnableToLegalize;
7710
7711 SmallVector<Register, 8> Parts;
7712 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg);
7713 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, VRegs&: Parts, PadStrategy: MI.getOpcode());
7714 buildWidenedRemergeToDst(DstReg, LCMTy, RemergeRegs: Parts);
7715
7716 MI.eraseFromParent();
7717 return Legalized;
7718}
7719
7720LegalizerHelper::LegalizeResult
7721LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
7722 LLT NarrowTy) {
7723 if (TypeIdx != 0)
7724 return UnableToLegalize;
7725
7726 Register CondReg = MI.getOperand(i: 1).getReg();
7727 LLT CondTy = MRI.getType(Reg: CondReg);
7728 if (CondTy.isVector()) // TODO: Handle vselect
7729 return UnableToLegalize;
7730
7731 Register DstReg = MI.getOperand(i: 0).getReg();
7732 LLT DstTy = MRI.getType(Reg: DstReg);
7733
7734 SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
7735 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
7736 SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs;
7737 LLT LeftoverTy;
7738 if (!extractParts(Reg: MI.getOperand(i: 2).getReg(), RegTy: DstTy, MainTy: NarrowTy, LeftoverTy,
7739 VRegs&: Src1Regs, LeftoverVRegs&: Src1LeftoverRegs, MIRBuilder, MRI))
7740 return UnableToLegalize;
7741
7742 LLT Unused;
7743 if (!extractParts(Reg: MI.getOperand(i: 3).getReg(), RegTy: DstTy, MainTy: NarrowTy, LeftoverTy&: Unused,
7744 VRegs&: Src2Regs, LeftoverVRegs&: Src2LeftoverRegs, MIRBuilder, MRI))
7745 llvm_unreachable("inconsistent extractParts result");
7746
7747 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
7748 auto Select = MIRBuilder.buildSelect(Res: NarrowTy,
7749 Tst: CondReg, Op0: Src1Regs[I], Op1: Src2Regs[I]);
7750 DstRegs.push_back(Elt: Select.getReg(Idx: 0));
7751 }
7752
7753 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
7754 auto Select = MIRBuilder.buildSelect(
7755 Res: LeftoverTy, Tst: CondReg, Op0: Src1LeftoverRegs[I], Op1: Src2LeftoverRegs[I]);
7756 DstLeftoverRegs.push_back(Elt: Select.getReg(Idx: 0));
7757 }
7758
7759 insertParts(DstReg, ResultTy: DstTy, PartTy: NarrowTy, PartRegs: DstRegs,
7760 LeftoverTy, LeftoverRegs: DstLeftoverRegs);
7761
7762 MI.eraseFromParent();
7763 return Legalized;
7764}
7765
7766LegalizerHelper::LegalizeResult
7767LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx,
7768 LLT NarrowTy) {
7769 if (TypeIdx != 1)
7770 return UnableToLegalize;
7771
7772 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
7773 unsigned NarrowSize = NarrowTy.getSizeInBits();
7774
7775 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
7776 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_POISON;
7777
7778 MachineIRBuilder &B = MIRBuilder;
7779 auto UnmergeSrc = B.buildUnmerge(Res: NarrowTy, Op: SrcReg);
7780 // ctlz(Hi:Lo) -> Hi == 0 ? (NarrowSize + ctlz(Lo)) : ctlz(Hi)
7781 auto C_0 = B.buildConstant(Res: NarrowTy, Val: 0);
7782 auto HiIsZero = B.buildICmp(Pred: CmpInst::ICMP_EQ, Res: LLT::integer(SizeInBits: 1),
7783 Op0: UnmergeSrc.getReg(Idx: 1), Op1: C_0);
7784 auto LoCTLZ = IsUndef ? B.buildCTLZ_ZERO_POISON(Dst: DstTy, Src0: UnmergeSrc.getReg(Idx: 0))
7785 : B.buildCTLZ(Dst: DstTy, Src0: UnmergeSrc.getReg(Idx: 0));
7786 auto C_NarrowSize = B.buildConstant(Res: DstTy, Val: NarrowSize);
7787 auto HiIsZeroCTLZ = B.buildAdd(Dst: DstTy, Src0: LoCTLZ, Src1: C_NarrowSize);
7788 auto HiCTLZ = B.buildCTLZ_ZERO_POISON(Dst: DstTy, Src0: UnmergeSrc.getReg(Idx: 1));
7789 B.buildSelect(Res: DstReg, Tst: HiIsZero, Op0: HiIsZeroCTLZ, Op1: HiCTLZ);
7790
7791 MI.eraseFromParent();
7792 return Legalized;
7793 }
7794
7795 return UnableToLegalize;
7796}
7797
7798LegalizerHelper::LegalizeResult
7799LegalizerHelper::narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx,
7800 LLT NarrowTy) {
7801 if (TypeIdx != 1)
7802 return UnableToLegalize;
7803
7804 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
7805 unsigned NarrowSize = NarrowTy.getSizeInBits();
7806
7807 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
7808 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTTZ_ZERO_POISON;
7809
7810 MachineIRBuilder &B = MIRBuilder;
7811 auto UnmergeSrc = B.buildUnmerge(Res: NarrowTy, Op: SrcReg);
7812 // cttz(Hi:Lo) -> Lo == 0 ? (cttz(Hi) + NarrowSize) : cttz(Lo)
7813 auto C_0 = B.buildConstant(Res: NarrowTy, Val: 0);
7814 auto LoIsZero = B.buildICmp(Pred: CmpInst::ICMP_EQ, Res: LLT::integer(SizeInBits: 1),
7815 Op0: UnmergeSrc.getReg(Idx: 0), Op1: C_0);
7816 auto HiCTTZ = IsUndef ? B.buildCTTZ_ZERO_POISON(Dst: DstTy, Src0: UnmergeSrc.getReg(Idx: 1))
7817 : B.buildCTTZ(Dst: DstTy, Src0: UnmergeSrc.getReg(Idx: 1));
7818 auto C_NarrowSize = B.buildConstant(Res: DstTy, Val: NarrowSize);
7819 auto LoIsZeroCTTZ = B.buildAdd(Dst: DstTy, Src0: HiCTTZ, Src1: C_NarrowSize);
7820 auto LoCTTZ = B.buildCTTZ_ZERO_POISON(Dst: DstTy, Src0: UnmergeSrc.getReg(Idx: 0));
7821 B.buildSelect(Res: DstReg, Tst: LoIsZero, Op0: LoIsZeroCTTZ, Op1: LoCTTZ);
7822
7823 MI.eraseFromParent();
7824 return Legalized;
7825 }
7826
7827 return UnableToLegalize;
7828}
7829
7830LegalizerHelper::LegalizeResult
7831LegalizerHelper::narrowScalarCTLS(MachineInstr &MI, unsigned TypeIdx,
7832 LLT NarrowTy) {
7833 if (TypeIdx != 1)
7834 return UnableToLegalize;
7835
7836 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
7837 unsigned NarrowSize = NarrowTy.getSizeInBits();
7838
7839 if (!SrcTy.isScalar() || SrcTy.getSizeInBits() != 2 * NarrowSize)
7840 return UnableToLegalize;
7841
7842 MachineIRBuilder &B = MIRBuilder;
7843
7844 auto UnmergeSrc = B.buildUnmerge(Res: NarrowTy, Op: SrcReg);
7845 Register Lo = UnmergeSrc.getReg(Idx: 0);
7846 Register Hi = UnmergeSrc.getReg(Idx: 1);
7847
7848 auto ShAmt = B.buildConstant(Res: NarrowTy, Val: NarrowSize - 1);
7849 auto Sign = B.buildAShr(Dst: NarrowTy, Src0: Hi, Src1: ShAmt);
7850
7851 auto HiIsSign = B.buildICmp(Pred: CmpInst::ICMP_EQ, Res: LLT::scalar(SizeInBits: 1), Op0: Hi, Op1: Sign);
7852
7853 // Invert Lo if Hi is negative. Then count the leading zeros. If there are no
7854 // leading zeros, then the MSB of Lo is different than the MSB of Hi.
7855 // Otherwise the leading zeros represent additional sign bits of the original
7856 // value.
7857 auto LoInv = B.buildXor(Dst: DstTy, Src0: Lo, Src1: Sign);
7858 auto LoCTLZ = B.buildCTLZ(Dst: DstTy, Src0: LoInv);
7859
7860 // Add NarrowSize-1 to LoCTLZ. This is the full CTLS if Hi is all sign bits.
7861 auto C_NarrowSizeM1 = B.buildConstant(Res: DstTy, Val: NarrowSize - 1);
7862 auto HiIsSignCTLS = B.buildAdd(Dst: DstTy, Src0: LoCTLZ, Src1: C_NarrowSizeM1);
7863
7864 auto HiCTLS = B.buildCTLS(Dst: DstTy, Src0: Hi);
7865
7866 B.buildSelect(Res: DstReg, Tst: HiIsSign, Op0: HiIsSignCTLS, Op1: HiCTLS);
7867
7868 MI.eraseFromParent();
7869 return Legalized;
7870}
7871
7872LegalizerHelper::LegalizeResult
7873LegalizerHelper::narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx,
7874 LLT NarrowTy) {
7875 if (TypeIdx != 1)
7876 return UnableToLegalize;
7877
7878 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
7879 unsigned NarrowSize = NarrowTy.getSizeInBits();
7880
7881 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
7882 auto UnmergeSrc = MIRBuilder.buildUnmerge(Res: NarrowTy, Op: MI.getOperand(i: 1));
7883
7884 auto LoCTPOP = MIRBuilder.buildCTPOP(Dst: DstTy, Src0: UnmergeSrc.getReg(Idx: 0));
7885 auto HiCTPOP = MIRBuilder.buildCTPOP(Dst: DstTy, Src0: UnmergeSrc.getReg(Idx: 1));
7886 MIRBuilder.buildAdd(Dst: DstReg, Src0: HiCTPOP, Src1: LoCTPOP);
7887
7888 MI.eraseFromParent();
7889 return Legalized;
7890 }
7891
7892 return UnableToLegalize;
7893}
7894
7895LegalizerHelper::LegalizeResult
7896LegalizerHelper::narrowScalarFLDEXP(MachineInstr &MI, unsigned TypeIdx,
7897 LLT NarrowTy) {
7898 if (TypeIdx != 1)
7899 return UnableToLegalize;
7900
7901 MachineIRBuilder &B = MIRBuilder;
7902 Register ExpReg = MI.getOperand(i: 2).getReg();
7903 LLT ExpTy = MRI.getType(Reg: ExpReg);
7904
7905 unsigned ClampSize = NarrowTy.getScalarSizeInBits();
7906
7907 // Clamp the exponent to the range of the target type.
7908 auto MinExp = B.buildConstant(Res: ExpTy, Val: minIntN(N: ClampSize));
7909 auto ClampMin = B.buildSMax(Dst: ExpTy, Src0: ExpReg, Src1: MinExp);
7910 auto MaxExp = B.buildConstant(Res: ExpTy, Val: maxIntN(N: ClampSize));
7911 auto Clamp = B.buildSMin(Dst: ExpTy, Src0: ClampMin, Src1: MaxExp);
7912
7913 auto Trunc = B.buildTrunc(Res: NarrowTy, Op: Clamp);
7914 Observer.changingInstr(MI);
7915 MI.getOperand(i: 2).setReg(Trunc.getReg(Idx: 0));
7916 Observer.changedInstr(MI);
7917 return Legalized;
7918}
7919
7920LegalizerHelper::LegalizeResult
7921LegalizerHelper::lowerBitCount(MachineInstr &MI) {
7922 unsigned Opc = MI.getOpcode();
7923 const auto &TII = MIRBuilder.getTII();
7924 auto isSupported = [this](const LegalityQuery &Q) {
7925 auto QAction = LI.getAction(Query: Q).Action;
7926 return QAction == Legal || QAction == Libcall || QAction == Custom;
7927 };
7928 switch (Opc) {
7929 default:
7930 return UnableToLegalize;
7931 case TargetOpcode::G_CTLZ_ZERO_POISON: {
7932 // This trivially expands to CTLZ.
7933 Observer.changingInstr(MI);
7934 MI.setDesc(TII.get(Opcode: TargetOpcode::G_CTLZ));
7935 Observer.changedInstr(MI);
7936 return Legalized;
7937 }
7938 case TargetOpcode::G_CTLZ: {
7939 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
7940 unsigned Len = SrcTy.getScalarSizeInBits();
7941
7942 if (isSupported({TargetOpcode::G_CTLZ_ZERO_POISON, {DstTy, SrcTy}})) {
7943 // If CTLZ_ZERO_POISON is supported, emit that and a select for zero.
7944 auto CtlzZU = MIRBuilder.buildCTLZ_ZERO_POISON(Dst: DstTy, Src0: SrcReg);
7945 auto ZeroSrc = MIRBuilder.buildConstant(Res: SrcTy, Val: 0);
7946 auto ICmp = MIRBuilder.buildICmp(
7947 Pred: CmpInst::ICMP_EQ, Res: SrcTy.changeElementSize(NewEltSize: 1), Op0: SrcReg, Op1: ZeroSrc);
7948 auto LenConst = MIRBuilder.buildConstant(Res: DstTy, Val: Len);
7949 MIRBuilder.buildSelect(Res: DstReg, Tst: ICmp, Op0: LenConst, Op1: CtlzZU);
7950 MI.eraseFromParent();
7951 return Legalized;
7952 }
7953 // for now, we do this:
7954 // NewLen = NextPowerOf2(Len);
7955 // x = x | (x >> 1);
7956 // x = x | (x >> 2);
7957 // ...
7958 // x = x | (x >>16);
7959 // x = x | (x >>32); // for 64-bit input
7960 // Upto NewLen/2
7961 // return Len - popcount(x);
7962 //
7963 // Ref: "Hacker's Delight" by Henry Warren
7964 Register Op = SrcReg;
7965 unsigned NewLen = PowerOf2Ceil(A: Len);
7966 for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
7967 auto MIBShiftAmt = MIRBuilder.buildConstant(Res: SrcTy, Val: 1ULL << i);
7968 auto MIBOp = MIRBuilder.buildOr(
7969 Dst: SrcTy, Src0: Op, Src1: MIRBuilder.buildLShr(Dst: SrcTy, Src0: Op, Src1: MIBShiftAmt));
7970 Op = MIBOp.getReg(Idx: 0);
7971 }
7972 auto MIBPop = MIRBuilder.buildCTPOP(Dst: DstTy, Src0: Op);
7973 MIRBuilder.buildSub(Dst: MI.getOperand(i: 0), Src0: MIRBuilder.buildConstant(Res: DstTy, Val: Len),
7974 Src1: MIBPop);
7975 MI.eraseFromParent();
7976 return Legalized;
7977 }
7978 case TargetOpcode::G_CTTZ_ZERO_POISON: {
7979 // This trivially expands to CTTZ.
7980 Observer.changingInstr(MI);
7981 MI.setDesc(TII.get(Opcode: TargetOpcode::G_CTTZ));
7982 Observer.changedInstr(MI);
7983 return Legalized;
7984 }
7985 case TargetOpcode::G_CTTZ: {
7986 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
7987
7988 unsigned Len = SrcTy.getScalarSizeInBits();
7989 if (isSupported({TargetOpcode::G_CTTZ_ZERO_POISON, {DstTy, SrcTy}})) {
7990 // If CTTZ_ZERO_POISON is legal or custom, emit that and a select with
7991 // zero.
7992 auto CttzZU = MIRBuilder.buildCTTZ_ZERO_POISON(Dst: DstTy, Src0: SrcReg);
7993 auto Zero = MIRBuilder.buildConstant(Res: SrcTy, Val: 0);
7994 auto ICmp = MIRBuilder.buildICmp(
7995 Pred: CmpInst::ICMP_EQ, Res: DstTy.changeElementSize(NewEltSize: 1), Op0: SrcReg, Op1: Zero);
7996 auto LenConst = MIRBuilder.buildConstant(Res: DstTy, Val: Len);
7997 MIRBuilder.buildSelect(Res: DstReg, Tst: ICmp, Op0: LenConst, Op1: CttzZU);
7998 MI.eraseFromParent();
7999 return Legalized;
8000 }
8001 // for now, we use: { return popcount(~x & (x - 1)); }
8002 // unless the target has ctlz but not ctpop, in which case we use:
8003 // { return 32 - nlz(~x & (x-1)); }
8004 // Ref: "Hacker's Delight" by Henry Warren
8005 auto MIBCstNeg1 = MIRBuilder.buildConstant(Res: SrcTy, Val: -1);
8006 auto MIBNot = MIRBuilder.buildXor(Dst: SrcTy, Src0: SrcReg, Src1: MIBCstNeg1);
8007 auto MIBTmp = MIRBuilder.buildAnd(
8008 Dst: SrcTy, Src0: MIBNot, Src1: MIRBuilder.buildAdd(Dst: SrcTy, Src0: SrcReg, Src1: MIBCstNeg1));
8009 if (!isSupported({TargetOpcode::G_CTPOP, {SrcTy, SrcTy}}) &&
8010 isSupported({TargetOpcode::G_CTLZ, {SrcTy, SrcTy}})) {
8011 auto MIBCstLen = MIRBuilder.buildConstant(Res: SrcTy, Val: Len);
8012 MIRBuilder.buildSub(Dst: MI.getOperand(i: 0), Src0: MIBCstLen,
8013 Src1: MIRBuilder.buildCTLZ(Dst: SrcTy, Src0: MIBTmp));
8014 MI.eraseFromParent();
8015 return Legalized;
8016 }
8017 Observer.changingInstr(MI);
8018 MI.setDesc(TII.get(Opcode: TargetOpcode::G_CTPOP));
8019 MI.getOperand(i: 1).setReg(MIBTmp.getReg(Idx: 0));
8020 Observer.changedInstr(MI);
8021 return Legalized;
8022 }
8023 case TargetOpcode::G_CTPOP: {
8024 Register SrcReg = MI.getOperand(i: 1).getReg();
8025 LLT Ty = MRI.getType(Reg: SrcReg);
8026 unsigned Size = Ty.getScalarSizeInBits();
8027 MachineIRBuilder &B = MIRBuilder;
8028
8029 // Bail out on irregular type lengths.
8030 if (Size > 128 || Size % 8 != 0)
8031 return UnableToLegalize;
8032
8033 // Count set bits in blocks of 2 bits. Default approach would be
8034 // B2Count = { val & 0x55555555 } + { (val >> 1) & 0x55555555 }
8035 // We use following formula instead:
8036 // B2Count = val - { (val >> 1) & 0x55555555 }
8037 // since it gives same result in blocks of 2 with one instruction less.
8038 auto C_1 = B.buildConstant(Res: Ty, Val: 1);
8039 auto B2Set1LoTo1Hi = B.buildLShr(Dst: Ty, Src0: SrcReg, Src1: C_1);
8040 APInt B2Mask1HiTo0 = APInt::getSplat(NewLen: Size, V: APInt(8, 0x55));
8041 auto C_B2Mask1HiTo0 = B.buildConstant(Res: Ty, Val: B2Mask1HiTo0);
8042 auto B2Count1Hi = B.buildAnd(Dst: Ty, Src0: B2Set1LoTo1Hi, Src1: C_B2Mask1HiTo0);
8043 auto B2Count = B.buildSub(Dst: Ty, Src0: SrcReg, Src1: B2Count1Hi);
8044
8045 // In order to get count in blocks of 4 add values from adjacent block of 2.
8046 // B4Count = { B2Count & 0x33333333 } + { (B2Count >> 2) & 0x33333333 }
8047 auto C_2 = B.buildConstant(Res: Ty, Val: 2);
8048 auto B4Set2LoTo2Hi = B.buildLShr(Dst: Ty, Src0: B2Count, Src1: C_2);
8049 APInt B4Mask2HiTo0 = APInt::getSplat(NewLen: Size, V: APInt(8, 0x33));
8050 auto C_B4Mask2HiTo0 = B.buildConstant(Res: Ty, Val: B4Mask2HiTo0);
8051 auto B4HiB2Count = B.buildAnd(Dst: Ty, Src0: B4Set2LoTo2Hi, Src1: C_B4Mask2HiTo0);
8052 auto B4LoB2Count = B.buildAnd(Dst: Ty, Src0: B2Count, Src1: C_B4Mask2HiTo0);
8053 auto B4Count = B.buildAdd(Dst: Ty, Src0: B4HiB2Count, Src1: B4LoB2Count);
8054
8055 // For count in blocks of 8 bits we don't have to mask high 4 bits before
8056 // addition since count value sits in range {0,...,8} and 4 bits are enough
8057 // to hold such binary values. After addition high 4 bits still hold count
8058 // of set bits in high 4 bit block, set them to zero and get 8 bit result.
8059 // B8Count = { B4Count + (B4Count >> 4) } & 0x0F0F0F0F
8060 auto C_4 = B.buildConstant(Res: Ty, Val: 4);
8061 auto B8HiB4Count = B.buildLShr(Dst: Ty, Src0: B4Count, Src1: C_4);
8062 auto B8CountDirty4Hi = B.buildAdd(Dst: Ty, Src0: B8HiB4Count, Src1: B4Count);
8063 APInt B8Mask4HiTo0 = APInt::getSplat(NewLen: Size, V: APInt(8, 0x0F));
8064 auto C_B8Mask4HiTo0 = B.buildConstant(Res: Ty, Val: B8Mask4HiTo0);
8065 auto B8Count = B.buildAnd(Dst: Ty, Src0: B8CountDirty4Hi, Src1: C_B8Mask4HiTo0);
8066
8067 assert(Size <= 128 && "Scalar size is too large for CTPOP lower algorithm");
8068
8069 // Avoid the multiply when shift-add is cheaper.
8070 if (Size == 16 && !Ty.isVector()) {
8071 // v = (v + (v >> 8)) & 0xFF;
8072 auto C_8 = B.buildConstant(Res: Ty, Val: 8);
8073 auto HighSum = B.buildLShr(Dst: Ty, Src0: B8Count, Src1: C_8);
8074 auto Res = B.buildAdd(Dst: Ty, Src0: B8Count, Src1: HighSum);
8075 B.buildAnd(Dst: MI.getOperand(i: 0).getReg(), Src0: Res, Src1: B.buildConstant(Res: Ty, Val: 0xFF));
8076 MI.eraseFromParent();
8077 return Legalized;
8078 }
8079
8080 // 8 bits can hold CTPOP result of 128 bit int or smaller. Mul with this
8081 // bitmask will set 8 msb in ResTmp to sum of all B8Counts in 8 bit blocks.
8082 auto MulMask = B.buildConstant(Res: Ty, Val: APInt::getSplat(NewLen: Size, V: APInt(8, 0x01)));
8083
8084 // Shift count result from 8 high bits to low bits.
8085 auto C_SizeM8 = B.buildConstant(Res: Ty, Val: Size - 8);
8086
8087 auto IsMulSupported = [this](const LLT Ty) {
8088 auto Action = LI.getAction(Query: {TargetOpcode::G_MUL, {Ty}}).Action;
8089 return Action == Legal || Action == WidenScalar || Action == Custom;
8090 };
8091 if (IsMulSupported(Ty)) {
8092 auto ResTmp = B.buildMul(Dst: Ty, Src0: B8Count, Src1: MulMask);
8093 B.buildLShr(Dst: MI.getOperand(i: 0).getReg(), Src0: ResTmp, Src1: C_SizeM8);
8094 } else {
8095 auto ResTmp = B8Count;
8096 for (unsigned Shift = 8; Shift < Size; Shift *= 2) {
8097 auto ShiftC = B.buildConstant(Res: Ty, Val: Shift);
8098 auto Shl = B.buildShl(Dst: Ty, Src0: ResTmp, Src1: ShiftC);
8099 ResTmp = B.buildAdd(Dst: Ty, Src0: ResTmp, Src1: Shl);
8100 }
8101 B.buildLShr(Dst: MI.getOperand(i: 0).getReg(), Src0: ResTmp, Src1: C_SizeM8);
8102 }
8103 MI.eraseFromParent();
8104 return Legalized;
8105 }
8106 case TargetOpcode::G_CTLS: {
8107 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
8108
8109 // ctls(x) -> ctlz(x ^ (x >> (N - 1))) - 1
8110 auto SignIdxC =
8111 MIRBuilder.buildConstant(Res: SrcTy, Val: SrcTy.getScalarSizeInBits() - 1);
8112 auto OneC = MIRBuilder.buildConstant(Res: DstTy, Val: 1);
8113
8114 auto Shr = MIRBuilder.buildAShr(Dst: SrcTy, Src0: SrcReg, Src1: SignIdxC);
8115
8116 auto Xor = MIRBuilder.buildXor(Dst: SrcTy, Src0: SrcReg, Src1: Shr);
8117 auto Ctlz = MIRBuilder.buildCTLZ(Dst: DstTy, Src0: Xor);
8118
8119 MIRBuilder.buildSub(Dst: DstReg, Src0: Ctlz, Src1: OneC);
8120 MI.eraseFromParent();
8121 return Legalized;
8122 }
8123 }
8124}
8125
8126// Check that (every element of) Reg is undef or not an exact multiple of BW.
8127static bool isNonZeroModBitWidthOrUndef(const MachineRegisterInfo &MRI,
8128 Register Reg, unsigned BW) {
8129 return matchUnaryPredicate(
8130 MRI, Reg,
8131 Match: [=](const Constant *C) {
8132 // Null constant here means an undef.
8133 const ConstantInt *CI = dyn_cast_or_null<ConstantInt>(Val: C);
8134 return !CI || CI->getValue().urem(RHS: BW) != 0;
8135 },
8136 /*AllowUndefs*/ true);
8137}
8138
8139LegalizerHelper::LegalizeResult
8140LegalizerHelper::lowerFunnelShiftWithInverse(MachineInstr &MI) {
8141 auto [Dst, X, Y, Z] = MI.getFirst4Regs();
8142 LLT Ty = MRI.getType(Reg: Dst);
8143 LLT ShTy = MRI.getType(Reg: Z);
8144
8145 unsigned BW = Ty.getScalarSizeInBits();
8146
8147 if (!isPowerOf2_32(Value: BW))
8148 return UnableToLegalize;
8149
8150 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL;
8151 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL;
8152
8153 if (isNonZeroModBitWidthOrUndef(MRI, Reg: Z, BW)) {
8154 // fshl X, Y, Z -> fshr X, Y, -Z
8155 // fshr X, Y, Z -> fshl X, Y, -Z
8156 auto Zero = MIRBuilder.buildConstant(Res: ShTy, Val: 0);
8157 Z = MIRBuilder.buildSub(Dst: Ty, Src0: Zero, Src1: Z).getReg(Idx: 0);
8158 } else {
8159 // fshl X, Y, Z -> fshr (srl X, 1), (fshr X, Y, 1), ~Z
8160 // fshr X, Y, Z -> fshl (fshl X, Y, 1), (shl Y, 1), ~Z
8161 auto One = MIRBuilder.buildConstant(Res: ShTy, Val: 1);
8162 if (IsFSHL) {
8163 Y = MIRBuilder.buildInstr(Opc: RevOpcode, DstOps: {Ty}, SrcOps: {X, Y, One}).getReg(Idx: 0);
8164 X = MIRBuilder.buildLShr(Dst: Ty, Src0: X, Src1: One).getReg(Idx: 0);
8165 } else {
8166 X = MIRBuilder.buildInstr(Opc: RevOpcode, DstOps: {Ty}, SrcOps: {X, Y, One}).getReg(Idx: 0);
8167 Y = MIRBuilder.buildShl(Dst: Ty, Src0: Y, Src1: One).getReg(Idx: 0);
8168 }
8169
8170 Z = MIRBuilder.buildNot(Dst: ShTy, Src0: Z).getReg(Idx: 0);
8171 }
8172
8173 MIRBuilder.buildInstr(Opc: RevOpcode, DstOps: {Dst}, SrcOps: {X, Y, Z});
8174 MI.eraseFromParent();
8175 return Legalized;
8176}
8177
8178LegalizerHelper::LegalizeResult
8179LegalizerHelper::lowerFunnelShiftAsShifts(MachineInstr &MI) {
8180 auto [Dst, X, Y, Z] = MI.getFirst4Regs();
8181 LLT Ty = MRI.getType(Reg: Dst);
8182 LLT ShTy = MRI.getType(Reg: Z);
8183
8184 const unsigned BW = Ty.getScalarSizeInBits();
8185 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL;
8186
8187 Register ShX, ShY;
8188 Register ShAmt, InvShAmt;
8189
8190 // FIXME: Emit optimized urem by constant instead of letting it expand later.
8191 if (isNonZeroModBitWidthOrUndef(MRI, Reg: Z, BW)) {
8192 // fshl: X << C | Y >> (BW - C)
8193 // fshr: X << (BW - C) | Y >> C
8194 // where C = Z % BW is not zero
8195 auto BitWidthC = MIRBuilder.buildConstant(Res: ShTy, Val: BW);
8196 ShAmt = MIRBuilder.buildURem(Dst: ShTy, Src0: Z, Src1: BitWidthC).getReg(Idx: 0);
8197 InvShAmt = MIRBuilder.buildSub(Dst: ShTy, Src0: BitWidthC, Src1: ShAmt).getReg(Idx: 0);
8198 ShX = MIRBuilder.buildShl(Dst: Ty, Src0: X, Src1: IsFSHL ? ShAmt : InvShAmt).getReg(Idx: 0);
8199 ShY = MIRBuilder.buildLShr(Dst: Ty, Src0: Y, Src1: IsFSHL ? InvShAmt : ShAmt).getReg(Idx: 0);
8200 } else {
8201 // fshl: X << (Z % BW) | Y >> 1 >> (BW - 1 - (Z % BW))
8202 // fshr: X << 1 << (BW - 1 - (Z % BW)) | Y >> (Z % BW)
8203 auto Mask = MIRBuilder.buildConstant(Res: ShTy, Val: BW - 1);
8204 if (isPowerOf2_32(Value: BW)) {
8205 // Z % BW -> Z & (BW - 1)
8206 ShAmt = MIRBuilder.buildAnd(Dst: ShTy, Src0: Z, Src1: Mask).getReg(Idx: 0);
8207 // (BW - 1) - (Z % BW) -> ~Z & (BW - 1)
8208 auto NotZ = MIRBuilder.buildNot(Dst: ShTy, Src0: Z);
8209 InvShAmt = MIRBuilder.buildAnd(Dst: ShTy, Src0: NotZ, Src1: Mask).getReg(Idx: 0);
8210 } else {
8211 auto BitWidthC = MIRBuilder.buildConstant(Res: ShTy, Val: BW);
8212 ShAmt = MIRBuilder.buildURem(Dst: ShTy, Src0: Z, Src1: BitWidthC).getReg(Idx: 0);
8213 InvShAmt = MIRBuilder.buildSub(Dst: ShTy, Src0: Mask, Src1: ShAmt).getReg(Idx: 0);
8214 }
8215
8216 auto One = MIRBuilder.buildConstant(Res: ShTy, Val: 1);
8217 if (IsFSHL) {
8218 ShX = MIRBuilder.buildShl(Dst: Ty, Src0: X, Src1: ShAmt).getReg(Idx: 0);
8219 auto ShY1 = MIRBuilder.buildLShr(Dst: Ty, Src0: Y, Src1: One);
8220 ShY = MIRBuilder.buildLShr(Dst: Ty, Src0: ShY1, Src1: InvShAmt).getReg(Idx: 0);
8221 } else {
8222 auto ShX1 = MIRBuilder.buildShl(Dst: Ty, Src0: X, Src1: One);
8223 ShX = MIRBuilder.buildShl(Dst: Ty, Src0: ShX1, Src1: InvShAmt).getReg(Idx: 0);
8224 ShY = MIRBuilder.buildLShr(Dst: Ty, Src0: Y, Src1: ShAmt).getReg(Idx: 0);
8225 }
8226 }
8227
8228 MIRBuilder.buildOr(Dst, Src0: ShX, Src1: ShY, Flags: MachineInstr::Disjoint);
8229 MI.eraseFromParent();
8230 return Legalized;
8231}
8232
8233LegalizerHelper::LegalizeResult
8234LegalizerHelper::lowerFunnelShift(MachineInstr &MI) {
8235 // These operations approximately do the following (while avoiding undefined
8236 // shifts by BW):
8237 // G_FSHL: (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
8238 // G_FSHR: (X << (BW - (Z % BW))) | (Y >> (Z % BW))
8239 Register Dst = MI.getOperand(i: 0).getReg();
8240 LLT Ty = MRI.getType(Reg: Dst);
8241 LLT ShTy = MRI.getType(Reg: MI.getOperand(i: 3).getReg());
8242
8243 bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL;
8244 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL;
8245
8246 // TODO: Use smarter heuristic that accounts for vector legalization.
8247 if (LI.getAction(Query: {RevOpcode, {Ty, ShTy}}).Action == Lower)
8248 return lowerFunnelShiftAsShifts(MI);
8249
8250 // This only works for powers of 2, fallback to shifts if it fails.
8251 LegalizerHelper::LegalizeResult Result = lowerFunnelShiftWithInverse(MI);
8252 if (Result == UnableToLegalize)
8253 return lowerFunnelShiftAsShifts(MI);
8254 return Result;
8255}
8256
8257LegalizerHelper::LegalizeResult LegalizerHelper::lowerEXT(MachineInstr &MI) {
8258 auto [Dst, Src] = MI.getFirst2Regs();
8259 LLT DstTy = MRI.getType(Reg: Dst);
8260 LLT SrcTy = MRI.getType(Reg: Src);
8261
8262 uint32_t DstTySize = DstTy.getSizeInBits();
8263 uint32_t DstTyScalarSize = DstTy.getScalarSizeInBits();
8264 uint32_t SrcTyScalarSize = SrcTy.getScalarSizeInBits();
8265
8266 if (!isPowerOf2_32(Value: DstTySize) || !isPowerOf2_32(Value: DstTyScalarSize) ||
8267 !isPowerOf2_32(Value: SrcTyScalarSize))
8268 return UnableToLegalize;
8269
8270 // The step between extend is too large, split it by creating an intermediate
8271 // extend instruction
8272 if (SrcTyScalarSize * 2 < DstTyScalarSize) {
8273 LLT MidTy = SrcTy.changeElementSize(NewEltSize: SrcTyScalarSize * 2);
8274 // If the destination type is illegal, split it into multiple statements
8275 // zext x -> zext(merge(zext(unmerge), zext(unmerge)))
8276 auto NewExt = MIRBuilder.buildInstr(Opc: MI.getOpcode(), DstOps: {MidTy}, SrcOps: {Src});
8277 // Unmerge the vector
8278 LLT EltTy = MidTy.changeElementCount(
8279 EC: MidTy.getElementCount().divideCoefficientBy(RHS: 2));
8280 auto UnmergeSrc = MIRBuilder.buildUnmerge(Res: EltTy, Op: NewExt);
8281
8282 // ZExt the vectors
8283 LLT ZExtResTy = DstTy.changeElementCount(
8284 EC: DstTy.getElementCount().divideCoefficientBy(RHS: 2));
8285 auto ZExtRes1 = MIRBuilder.buildInstr(Opc: MI.getOpcode(), DstOps: {ZExtResTy},
8286 SrcOps: {UnmergeSrc.getReg(Idx: 0)});
8287 auto ZExtRes2 = MIRBuilder.buildInstr(Opc: MI.getOpcode(), DstOps: {ZExtResTy},
8288 SrcOps: {UnmergeSrc.getReg(Idx: 1)});
8289
8290 // Merge the ending vectors
8291 MIRBuilder.buildMergeLikeInstr(Res: Dst, Ops: {ZExtRes1, ZExtRes2});
8292
8293 MI.eraseFromParent();
8294 return Legalized;
8295 }
8296 return UnableToLegalize;
8297}
8298
8299LegalizerHelper::LegalizeResult LegalizerHelper::lowerTRUNC(MachineInstr &MI) {
8300 // MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
8301 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
8302 // Similar to how operand splitting is done in SelectiondDAG, we can handle
8303 // %res(v8s8) = G_TRUNC %in(v8s32) by generating:
8304 // %inlo(<4x s32>), %inhi(<4 x s32>) = G_UNMERGE %in(<8 x s32>)
8305 // %lo16(<4 x s16>) = G_TRUNC %inlo
8306 // %hi16(<4 x s16>) = G_TRUNC %inhi
8307 // %in16(<8 x s16>) = G_CONCAT_VECTORS %lo16, %hi16
8308 // %res(<8 x s8>) = G_TRUNC %in16
8309
8310 assert(MI.getOpcode() == TargetOpcode::G_TRUNC);
8311
8312 Register DstReg = MI.getOperand(i: 0).getReg();
8313 Register SrcReg = MI.getOperand(i: 1).getReg();
8314 LLT DstTy = MRI.getType(Reg: DstReg);
8315 LLT SrcTy = MRI.getType(Reg: SrcReg);
8316
8317 if (DstTy.isVector() && isPowerOf2_32(Value: DstTy.getNumElements()) &&
8318 isPowerOf2_32(Value: DstTy.getScalarSizeInBits()) &&
8319 isPowerOf2_32(Value: SrcTy.getNumElements()) &&
8320 isPowerOf2_32(Value: SrcTy.getScalarSizeInBits())) {
8321 // Split input type.
8322 LLT SplitSrcTy = SrcTy.changeElementCount(
8323 EC: SrcTy.getElementCount().divideCoefficientBy(RHS: 2));
8324
8325 // First, split the source into two smaller vectors.
8326 SmallVector<Register, 2> SplitSrcs;
8327 extractParts(Reg: SrcReg, Ty: SplitSrcTy, NumParts: 2, VRegs&: SplitSrcs, MIRBuilder, MRI);
8328
8329 // Truncate the splits into intermediate narrower elements.
8330 LLT InterTy;
8331 if (DstTy.getScalarSizeInBits() * 2 < SrcTy.getScalarSizeInBits())
8332 InterTy = SplitSrcTy.changeElementSize(NewEltSize: DstTy.getScalarSizeInBits() * 2);
8333 else
8334 InterTy = SplitSrcTy.changeElementSize(NewEltSize: DstTy.getScalarSizeInBits());
8335 for (Register &Src : SplitSrcs)
8336 Src = MIRBuilder.buildTrunc(Res: InterTy, Op: Src).getReg(Idx: 0);
8337
8338 // Combine the new truncates into one vector
8339 auto Merge = MIRBuilder.buildMergeLikeInstr(
8340 Res: DstTy.changeElementSize(NewEltSize: InterTy.getScalarSizeInBits()), Ops: SplitSrcs);
8341
8342 // Truncate the new vector to the final result type
8343 if (DstTy.getScalarSizeInBits() * 2 < SrcTy.getScalarSizeInBits())
8344 MIRBuilder.buildTrunc(Res: MI.getOperand(i: 0).getReg(), Op: Merge.getReg(Idx: 0));
8345 else
8346 MIRBuilder.buildCopy(Res: MI.getOperand(i: 0).getReg(), Op: Merge.getReg(Idx: 0));
8347
8348 MI.eraseFromParent();
8349
8350 return Legalized;
8351 }
8352 return UnableToLegalize;
8353}
8354
8355LegalizerHelper::LegalizeResult
8356LegalizerHelper::lowerRotateWithReverseRotate(MachineInstr &MI) {
8357 auto [Dst, DstTy, Src, SrcTy, Amt, AmtTy] = MI.getFirst3RegLLTs();
8358 auto Zero = MIRBuilder.buildConstant(Res: AmtTy, Val: 0);
8359 bool IsLeft = MI.getOpcode() == TargetOpcode::G_ROTL;
8360 unsigned RevRot = IsLeft ? TargetOpcode::G_ROTR : TargetOpcode::G_ROTL;
8361 auto Neg = MIRBuilder.buildSub(Dst: AmtTy, Src0: Zero, Src1: Amt);
8362 MIRBuilder.buildInstr(Opc: RevRot, DstOps: {Dst}, SrcOps: {Src, Neg});
8363 MI.eraseFromParent();
8364 return Legalized;
8365}
8366
8367LegalizerHelper::LegalizeResult LegalizerHelper::lowerRotate(MachineInstr &MI) {
8368 auto [Dst, DstTy, Src, SrcTy, Amt, AmtTy] = MI.getFirst3RegLLTs();
8369
8370 unsigned EltSizeInBits = DstTy.getScalarSizeInBits();
8371 bool IsLeft = MI.getOpcode() == TargetOpcode::G_ROTL;
8372
8373 MIRBuilder.setInstrAndDebugLoc(MI);
8374
8375 // If a rotate in the other direction is supported, use it.
8376 unsigned RevRot = IsLeft ? TargetOpcode::G_ROTR : TargetOpcode::G_ROTL;
8377 if (LI.isLegalOrCustom(Query: {RevRot, {DstTy, SrcTy}}) &&
8378 isPowerOf2_32(Value: EltSizeInBits))
8379 return lowerRotateWithReverseRotate(MI);
8380
8381 // If a funnel shift is supported, use it.
8382 unsigned FShOpc = IsLeft ? TargetOpcode::G_FSHL : TargetOpcode::G_FSHR;
8383 unsigned RevFsh = !IsLeft ? TargetOpcode::G_FSHL : TargetOpcode::G_FSHR;
8384 bool IsFShLegal = false;
8385 if ((IsFShLegal = LI.isLegalOrCustom(Query: {FShOpc, {DstTy, AmtTy}})) ||
8386 LI.isLegalOrCustom(Query: {RevFsh, {DstTy, AmtTy}})) {
8387 auto buildFunnelShift = [&](unsigned Opc, Register R1, Register R2,
8388 Register R3) {
8389 MIRBuilder.buildInstr(Opc, DstOps: {R1}, SrcOps: {R2, R2, R3});
8390 MI.eraseFromParent();
8391 return Legalized;
8392 };
8393 // If a funnel shift in the other direction is supported, use it.
8394 if (IsFShLegal) {
8395 return buildFunnelShift(FShOpc, Dst, Src, Amt);
8396 } else if (isPowerOf2_32(Value: EltSizeInBits)) {
8397 Amt = MIRBuilder.buildNeg(Dst: DstTy, Src0: Amt).getReg(Idx: 0);
8398 return buildFunnelShift(RevFsh, Dst, Src, Amt);
8399 }
8400 }
8401
8402 auto Zero = MIRBuilder.buildConstant(Res: AmtTy, Val: 0);
8403 unsigned ShOpc = IsLeft ? TargetOpcode::G_SHL : TargetOpcode::G_LSHR;
8404 unsigned RevShiftOpc = IsLeft ? TargetOpcode::G_LSHR : TargetOpcode::G_SHL;
8405 auto BitWidthMinusOneC = MIRBuilder.buildConstant(Res: AmtTy, Val: EltSizeInBits - 1);
8406 Register ShVal;
8407 Register RevShiftVal;
8408 if (isPowerOf2_32(Value: EltSizeInBits)) {
8409 // (rotl x, c) -> x << (c & (w - 1)) | x >> (-c & (w - 1))
8410 // (rotr x, c) -> x >> (c & (w - 1)) | x << (-c & (w - 1))
8411 auto NegAmt = MIRBuilder.buildSub(Dst: AmtTy, Src0: Zero, Src1: Amt);
8412 auto ShAmt = MIRBuilder.buildAnd(Dst: AmtTy, Src0: Amt, Src1: BitWidthMinusOneC);
8413 ShVal = MIRBuilder.buildInstr(Opc: ShOpc, DstOps: {DstTy}, SrcOps: {Src, ShAmt}).getReg(Idx: 0);
8414 auto RevAmt = MIRBuilder.buildAnd(Dst: AmtTy, Src0: NegAmt, Src1: BitWidthMinusOneC);
8415 RevShiftVal =
8416 MIRBuilder.buildInstr(Opc: RevShiftOpc, DstOps: {DstTy}, SrcOps: {Src, RevAmt}).getReg(Idx: 0);
8417 } else {
8418 // (rotl x, c) -> x << (c % w) | x >> 1 >> (w - 1 - (c % w))
8419 // (rotr x, c) -> x >> (c % w) | x << 1 << (w - 1 - (c % w))
8420 auto BitWidthC = MIRBuilder.buildConstant(Res: AmtTy, Val: EltSizeInBits);
8421 auto ShAmt = MIRBuilder.buildURem(Dst: AmtTy, Src0: Amt, Src1: BitWidthC);
8422 ShVal = MIRBuilder.buildInstr(Opc: ShOpc, DstOps: {DstTy}, SrcOps: {Src, ShAmt}).getReg(Idx: 0);
8423 auto RevAmt = MIRBuilder.buildSub(Dst: AmtTy, Src0: BitWidthMinusOneC, Src1: ShAmt);
8424 auto One = MIRBuilder.buildConstant(Res: AmtTy, Val: 1);
8425 auto Inner = MIRBuilder.buildInstr(Opc: RevShiftOpc, DstOps: {DstTy}, SrcOps: {Src, One});
8426 RevShiftVal =
8427 MIRBuilder.buildInstr(Opc: RevShiftOpc, DstOps: {DstTy}, SrcOps: {Inner, RevAmt}).getReg(Idx: 0);
8428 }
8429 MIRBuilder.buildOr(Dst, Src0: ShVal, Src1: RevShiftVal, Flags: MachineInstr::Disjoint);
8430 MI.eraseFromParent();
8431 return Legalized;
8432}
8433
8434// Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
8435// representation.
8436LegalizerHelper::LegalizeResult
8437LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
8438 auto [Dst, Src] = MI.getFirst2Regs();
8439 const LLT S64 = LLT::scalar(SizeInBits: 64);
8440 const LLT S32 = LLT::scalar(SizeInBits: 32);
8441 const LLT S1 = LLT::scalar(SizeInBits: 1);
8442
8443 assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
8444
8445 // unsigned cul2f(ulong u) {
8446 // uint lz = clz(u);
8447 // uint e = (u != 0) ? 127U + 63U - lz : 0;
8448 // u = (u << lz) & 0x7fffffffffffffffUL;
8449 // ulong t = u & 0xffffffffffUL;
8450 // uint v = (e << 23) | (uint)(u >> 40);
8451 // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
8452 // return as_float(v + r);
8453 // }
8454
8455 auto Zero32 = MIRBuilder.buildConstant(Res: S32, Val: 0);
8456 auto Zero64 = MIRBuilder.buildConstant(Res: S64, Val: 0);
8457
8458 auto LZ = MIRBuilder.buildCTLZ_ZERO_POISON(Dst: S32, Src0: Src);
8459
8460 auto K = MIRBuilder.buildConstant(Res: S32, Val: 127U + 63U);
8461 auto Sub = MIRBuilder.buildSub(Dst: S32, Src0: K, Src1: LZ);
8462
8463 auto NotZero = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_NE, Res: S1, Op0: Src, Op1: Zero64);
8464 auto E = MIRBuilder.buildSelect(Res: S32, Tst: NotZero, Op0: Sub, Op1: Zero32);
8465
8466 auto Mask0 = MIRBuilder.buildConstant(Res: S64, Val: (-1ULL) >> 1);
8467 auto ShlLZ = MIRBuilder.buildShl(Dst: S64, Src0: Src, Src1: LZ);
8468
8469 auto U = MIRBuilder.buildAnd(Dst: S64, Src0: ShlLZ, Src1: Mask0);
8470
8471 auto Mask1 = MIRBuilder.buildConstant(Res: S64, Val: 0xffffffffffULL);
8472 auto T = MIRBuilder.buildAnd(Dst: S64, Src0: U, Src1: Mask1);
8473
8474 auto UShl = MIRBuilder.buildLShr(Dst: S64, Src0: U, Src1: MIRBuilder.buildConstant(Res: S64, Val: 40));
8475 auto ShlE = MIRBuilder.buildShl(Dst: S32, Src0: E, Src1: MIRBuilder.buildConstant(Res: S32, Val: 23));
8476 auto V = MIRBuilder.buildOr(Dst: S32, Src0: ShlE, Src1: MIRBuilder.buildTrunc(Res: S32, Op: UShl));
8477
8478 auto C = MIRBuilder.buildConstant(Res: S64, Val: 0x8000000000ULL);
8479 auto RCmp = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_UGT, Res: S1, Op0: T, Op1: C);
8480 auto TCmp = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_EQ, Res: S1, Op0: T, Op1: C);
8481 auto One = MIRBuilder.buildConstant(Res: S32, Val: 1);
8482
8483 auto VTrunc1 = MIRBuilder.buildAnd(Dst: S32, Src0: V, Src1: One);
8484 auto Select0 = MIRBuilder.buildSelect(Res: S32, Tst: TCmp, Op0: VTrunc1, Op1: Zero32);
8485 auto R = MIRBuilder.buildSelect(Res: S32, Tst: RCmp, Op0: One, Op1: Select0);
8486 MIRBuilder.buildAdd(Dst, Src0: V, Src1: R);
8487
8488 MI.eraseFromParent();
8489 return Legalized;
8490}
8491
8492// Expand s32 = G_UITOFP s64 to an IEEE float representation using bit
8493// operations and G_SITOFP
8494LegalizerHelper::LegalizeResult
8495LegalizerHelper::lowerU64ToF32WithSITOFP(MachineInstr &MI) {
8496 auto [Dst, Src] = MI.getFirst2Regs();
8497 const LLT S64 = LLT::scalar(SizeInBits: 64);
8498 const LLT S32 = LLT::scalar(SizeInBits: 32);
8499 const LLT S1 = LLT::scalar(SizeInBits: 1);
8500
8501 assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
8502
8503 // For i64 < INT_MAX we simply reuse SITOFP.
8504 // Otherwise, divide i64 by 2, round result by ORing with the lowest bit
8505 // saved before division, convert to float by SITOFP, multiply the result
8506 // by 2.
8507 auto One = MIRBuilder.buildConstant(Res: S64, Val: 1);
8508 auto Zero = MIRBuilder.buildConstant(Res: S64, Val: 0);
8509 // Result if Src < INT_MAX
8510 auto SmallResult = MIRBuilder.buildSITOFP(Dst: S32, Src0: Src);
8511 // Result if Src >= INT_MAX
8512 auto Halved = MIRBuilder.buildLShr(Dst: S64, Src0: Src, Src1: One);
8513 auto LowerBit = MIRBuilder.buildAnd(Dst: S64, Src0: Src, Src1: One);
8514 auto RoundedHalved = MIRBuilder.buildOr(Dst: S64, Src0: Halved, Src1: LowerBit);
8515 auto HalvedFP = MIRBuilder.buildSITOFP(Dst: S32, Src0: RoundedHalved);
8516 auto LargeResult = MIRBuilder.buildFAdd(Dst: S32, Src0: HalvedFP, Src1: HalvedFP);
8517 // Check if the original value is larger than INT_MAX by comparing with
8518 // zero to pick one of the two conversions.
8519 auto IsLarge =
8520 MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_SLT, Res: S1, Op0: Src, Op1: Zero);
8521 MIRBuilder.buildSelect(Res: Dst, Tst: IsLarge, Op0: LargeResult, Op1: SmallResult);
8522
8523 MI.eraseFromParent();
8524 return Legalized;
8525}
8526
8527// Expand s64 = G_UITOFP s64 using bit and float arithmetic operations to an
8528// IEEE double representation.
8529LegalizerHelper::LegalizeResult
8530LegalizerHelper::lowerU64ToF64BitFloatOps(MachineInstr &MI) {
8531 auto [Dst, Src] = MI.getFirst2Regs();
8532 const LLT S64 = LLT::scalar(SizeInBits: 64);
8533 const LLT S32 = LLT::scalar(SizeInBits: 32);
8534
8535 assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S64);
8536
8537 // We create double value from 32 bit parts with 32 exponent difference.
8538 // Note that + and - are float operations that adjust the implicit leading
8539 // one, the bases 2^52 and 2^84 are for illustrative purposes.
8540 //
8541 // X = 2^52 * 1.0...LowBits
8542 // Y = 2^84 * 1.0...HighBits
8543 // Scratch = 2^84 * 1.0...HighBits - 2^84 * 1.0 - 2^52 * 1.0
8544 // = - 2^52 * 1.0...HighBits
8545 // Result = - 2^52 * 1.0...HighBits + 2^52 * 1.0...LowBits
8546 auto TwoP52 = MIRBuilder.buildConstant(Res: S64, UINT64_C(0x4330000000000000));
8547 auto TwoP84 = MIRBuilder.buildConstant(Res: S64, UINT64_C(0x4530000000000000));
8548 auto TwoP52P84 = llvm::bit_cast<double>(UINT64_C(0x4530000000100000));
8549 auto TwoP52P84FP = MIRBuilder.buildFConstant(Res: S64, Val: TwoP52P84);
8550 auto HalfWidth = MIRBuilder.buildConstant(Res: S64, Val: 32);
8551
8552 auto LowBits = MIRBuilder.buildTrunc(Res: S32, Op: Src);
8553 LowBits = MIRBuilder.buildZExt(Res: S64, Op: LowBits);
8554 auto LowBitsFP = MIRBuilder.buildOr(Dst: S64, Src0: TwoP52, Src1: LowBits);
8555 auto HighBits = MIRBuilder.buildLShr(Dst: S64, Src0: Src, Src1: HalfWidth);
8556 auto HighBitsFP = MIRBuilder.buildOr(Dst: S64, Src0: TwoP84, Src1: HighBits);
8557 auto Scratch = MIRBuilder.buildFSub(Dst: S64, Src0: HighBitsFP, Src1: TwoP52P84FP);
8558 MIRBuilder.buildFAdd(Dst, Src0: Scratch, Src1: LowBitsFP);
8559
8560 MI.eraseFromParent();
8561 return Legalized;
8562}
8563
8564/// i64->fp16 itofp can be lowered to i64->f64,f64->f32,f32->f16. We cannot
8565/// convert fpround f64->f16 without double-rounding, so we manually perform the
8566/// lowering here where we know it is valid.
8567static LegalizerHelper::LegalizeResult
8568loweri64tof16ITOFP(MachineInstr &MI, Register Dst, LLT DstTy, Register Src,
8569 LLT SrcTy, MachineIRBuilder &MIRBuilder) {
8570 auto DstFpTy =
8571 SrcTy.changeElementType(NewEltTy: LLT::floatIEEE(SizeInBits: SrcTy.getScalarSizeInBits()));
8572 auto M1 = MI.getOpcode() == TargetOpcode::G_UITOFP
8573 ? MIRBuilder.buildUITOFP(Dst: DstFpTy, Src0: Src)
8574 : MIRBuilder.buildSITOFP(Dst: DstFpTy, Src0: Src);
8575 LLT F32Ty = DstFpTy.changeElementSize(NewEltSize: 32);
8576 auto M2 = MIRBuilder.buildFPTrunc(Res: F32Ty, Op: M1);
8577 MIRBuilder.buildFPTrunc(Res: Dst, Op: M2);
8578 MI.eraseFromParent();
8579 return LegalizerHelper::Legalized;
8580}
8581
8582LegalizerHelper::LegalizeResult LegalizerHelper::lowerUITOFP(MachineInstr &MI) {
8583 auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
8584
8585 if (SrcTy == LLT::scalar(SizeInBits: 1)) {
8586 auto True = MIRBuilder.buildFConstant(Res: DstTy, Val: 1.0);
8587 auto False = MIRBuilder.buildFConstant(Res: DstTy, Val: 0.0);
8588 MIRBuilder.buildSelect(Res: Dst, Tst: Src, Op0: True, Op1: False);
8589 MI.eraseFromParent();
8590 return Legalized;
8591 }
8592
8593 if (DstTy.getScalarSizeInBits() == 16 && SrcTy.getScalarSizeInBits() == 64)
8594 return loweri64tof16ITOFP(MI, Dst, DstTy, Src, SrcTy, MIRBuilder);
8595
8596 if (SrcTy != LLT::scalar(SizeInBits: 64))
8597 return UnableToLegalize;
8598
8599 if (DstTy == LLT::scalar(SizeInBits: 32))
8600 // TODO: SelectionDAG has several alternative expansions to port which may
8601 // be more reasonable depending on the available instructions. We also need
8602 // a more advanced mechanism to choose an optimal version depending on
8603 // target features such as sitofp or CTLZ availability.
8604 return lowerU64ToF32WithSITOFP(MI);
8605
8606 if (DstTy == LLT::scalar(SizeInBits: 64))
8607 return lowerU64ToF64BitFloatOps(MI);
8608
8609 return UnableToLegalize;
8610}
8611
8612LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) {
8613 auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
8614
8615 const LLT I64 = LLT::integer(SizeInBits: 64);
8616 const LLT I32 = LLT::integer(SizeInBits: 32);
8617 const LLT I1 = LLT::integer(SizeInBits: 1);
8618
8619 if (SrcTy == I1) {
8620 auto True = MIRBuilder.buildFConstant(Res: DstTy, Val: -1.0);
8621 auto False = MIRBuilder.buildFConstant(Res: DstTy, Val: 0.0);
8622 MIRBuilder.buildSelect(Res: Dst, Tst: Src, Op0: True, Op1: False);
8623 MI.eraseFromParent();
8624 return Legalized;
8625 }
8626
8627 if (DstTy.getScalarSizeInBits() == 16 && SrcTy.getScalarSizeInBits() == 64)
8628 return loweri64tof16ITOFP(MI, Dst, DstTy, Src, SrcTy, MIRBuilder);
8629
8630 if (SrcTy != I64)
8631 return UnableToLegalize;
8632
8633 if (DstTy.getScalarSizeInBits() == 32) {
8634 // signed cl2f(long l) {
8635 // long s = l >> 63;
8636 // float r = cul2f((l + s) ^ s);
8637 // return s ? -r : r;
8638 // }
8639 Register L = Src;
8640 auto SignBit = MIRBuilder.buildConstant(Res: I64, Val: 63);
8641 auto S = MIRBuilder.buildAShr(Dst: I64, Src0: L, Src1: SignBit);
8642
8643 auto LPlusS = MIRBuilder.buildAdd(Dst: I64, Src0: L, Src1: S);
8644 auto Xor = MIRBuilder.buildXor(Dst: I64, Src0: LPlusS, Src1: S);
8645 auto R = MIRBuilder.buildUITOFP(Dst: I32, Src0: Xor);
8646
8647 auto RNeg = MIRBuilder.buildFNeg(Dst: I32, Src0: R);
8648 auto SignNotZero = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_NE, Res: I1, Op0: S,
8649 Op1: MIRBuilder.buildConstant(Res: I64, Val: 0));
8650 MIRBuilder.buildSelect(Res: Dst, Tst: SignNotZero, Op0: RNeg, Op1: R);
8651 MI.eraseFromParent();
8652 return Legalized;
8653 }
8654
8655 return UnableToLegalize;
8656}
8657
8658LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOUI(MachineInstr &MI) {
8659 auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
8660 const LLT S64 = LLT::scalar(SizeInBits: 64);
8661 const LLT S32 = LLT::scalar(SizeInBits: 32);
8662
8663 if (SrcTy != S64 && SrcTy != S32)
8664 return UnableToLegalize;
8665 if (DstTy != S32 && DstTy != S64)
8666 return UnableToLegalize;
8667
8668 // FPTOSI gives same result as FPTOUI for positive signed integers.
8669 // FPTOUI needs to deal with fp values that convert to unsigned integers
8670 // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp.
8671
8672 APInt TwoPExpInt = APInt::getSignMask(BitWidth: DstTy.getSizeInBits());
8673 APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle()
8674 : APFloat::IEEEdouble(),
8675 APInt::getZero(numBits: SrcTy.getSizeInBits()));
8676 TwoPExpFP.convertFromAPInt(Input: TwoPExpInt, IsSigned: false, RM: APFloat::rmNearestTiesToEven);
8677
8678 MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(Dst: DstTy, Src0: Src);
8679
8680 MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(Res: SrcTy, Val: TwoPExpFP);
8681 // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on
8682 // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1.
8683 MachineInstrBuilder FSub = MIRBuilder.buildFSub(Dst: SrcTy, Src0: Src, Src1: Threshold);
8684 MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(Dst: DstTy, Src0: FSub);
8685 MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(Res: DstTy, Val: TwoPExpInt);
8686 MachineInstrBuilder Res = MIRBuilder.buildXor(Dst: DstTy, Src0: ResLowBits, Src1: ResHighBit);
8687
8688 const LLT S1 = LLT::scalar(SizeInBits: 1);
8689
8690 MachineInstrBuilder FCMP =
8691 MIRBuilder.buildFCmp(Pred: CmpInst::FCMP_ULT, Res: S1, Op0: Src, Op1: Threshold);
8692 MIRBuilder.buildSelect(Res: Dst, Tst: FCMP, Op0: FPTOSI, Op1: Res);
8693
8694 MI.eraseFromParent();
8695 return Legalized;
8696}
8697
8698LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) {
8699 auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
8700 const LLT S64 = LLT::scalar(SizeInBits: 64);
8701 const LLT S32 = LLT::scalar(SizeInBits: 32);
8702
8703 // FIXME: Only f32 to i64 conversions are supported.
8704 if (SrcTy.getScalarType() != S32 || DstTy.getScalarType() != S64)
8705 return UnableToLegalize;
8706
8707 // Expand f32 -> i64 conversion
8708 // This algorithm comes from compiler-rt's implementation of fixsfdi:
8709 // https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/fixsfdi.c
8710
8711 unsigned SrcEltBits = SrcTy.getScalarSizeInBits();
8712
8713 auto ExponentMask = MIRBuilder.buildConstant(Res: SrcTy, Val: 0x7F800000);
8714 auto ExponentLoBit = MIRBuilder.buildConstant(Res: SrcTy, Val: 23);
8715
8716 auto AndExpMask = MIRBuilder.buildAnd(Dst: SrcTy, Src0: Src, Src1: ExponentMask);
8717 auto ExponentBits = MIRBuilder.buildLShr(Dst: SrcTy, Src0: AndExpMask, Src1: ExponentLoBit);
8718
8719 auto SignMask = MIRBuilder.buildConstant(Res: SrcTy,
8720 Val: APInt::getSignMask(BitWidth: SrcEltBits));
8721 auto AndSignMask = MIRBuilder.buildAnd(Dst: SrcTy, Src0: Src, Src1: SignMask);
8722 auto SignLowBit = MIRBuilder.buildConstant(Res: SrcTy, Val: SrcEltBits - 1);
8723 auto Sign = MIRBuilder.buildAShr(Dst: SrcTy, Src0: AndSignMask, Src1: SignLowBit);
8724 Sign = MIRBuilder.buildSExt(Res: DstTy, Op: Sign);
8725
8726 auto MantissaMask = MIRBuilder.buildConstant(Res: SrcTy, Val: 0x007FFFFF);
8727 auto AndMantissaMask = MIRBuilder.buildAnd(Dst: SrcTy, Src0: Src, Src1: MantissaMask);
8728 auto K = MIRBuilder.buildConstant(Res: SrcTy, Val: 0x00800000);
8729
8730 auto R = MIRBuilder.buildOr(Dst: SrcTy, Src0: AndMantissaMask, Src1: K);
8731 R = MIRBuilder.buildZExt(Res: DstTy, Op: R);
8732
8733 auto Bias = MIRBuilder.buildConstant(Res: SrcTy, Val: 127);
8734 auto Exponent = MIRBuilder.buildSub(Dst: SrcTy, Src0: ExponentBits, Src1: Bias);
8735 auto SubExponent = MIRBuilder.buildSub(Dst: SrcTy, Src0: Exponent, Src1: ExponentLoBit);
8736 auto ExponentSub = MIRBuilder.buildSub(Dst: SrcTy, Src0: ExponentLoBit, Src1: Exponent);
8737
8738 auto Shl = MIRBuilder.buildShl(Dst: DstTy, Src0: R, Src1: SubExponent);
8739 auto Srl = MIRBuilder.buildLShr(Dst: DstTy, Src0: R, Src1: ExponentSub);
8740
8741 const LLT S1 = LLT::scalar(SizeInBits: 1);
8742 auto CmpGt = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_SGT,
8743 Res: S1, Op0: Exponent, Op1: ExponentLoBit);
8744
8745 R = MIRBuilder.buildSelect(Res: DstTy, Tst: CmpGt, Op0: Shl, Op1: Srl);
8746
8747 auto XorSign = MIRBuilder.buildXor(Dst: DstTy, Src0: R, Src1: Sign);
8748 auto Ret = MIRBuilder.buildSub(Dst: DstTy, Src0: XorSign, Src1: Sign);
8749
8750 auto ZeroSrcTy = MIRBuilder.buildConstant(Res: SrcTy, Val: 0);
8751
8752 auto ExponentLt0 = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_SLT,
8753 Res: S1, Op0: Exponent, Op1: ZeroSrcTy);
8754
8755 auto ZeroDstTy = MIRBuilder.buildConstant(Res: DstTy, Val: 0);
8756 MIRBuilder.buildSelect(Res: Dst, Tst: ExponentLt0, Op0: ZeroDstTy, Op1: Ret);
8757
8758 MI.eraseFromParent();
8759 return Legalized;
8760}
8761
8762LegalizerHelper::LegalizeResult
8763LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
8764 auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
8765
8766 bool IsSigned = MI.getOpcode() == TargetOpcode::G_FPTOSI_SAT;
8767 unsigned SatWidth = DstTy.getScalarSizeInBits();
8768
8769 // Determine minimum and maximum integer values and their corresponding
8770 // floating-point values.
8771 APInt MinInt, MaxInt;
8772 if (IsSigned) {
8773 MinInt = APInt::getSignedMinValue(numBits: SatWidth);
8774 MaxInt = APInt::getSignedMaxValue(numBits: SatWidth);
8775 } else {
8776 MinInt = APInt::getMinValue(numBits: SatWidth);
8777 MaxInt = APInt::getMaxValue(numBits: SatWidth);
8778 }
8779
8780 const fltSemantics &Semantics = getFltSemanticForLLT(Ty: SrcTy.getScalarType());
8781 APFloat MinFloat(Semantics);
8782 APFloat MaxFloat(Semantics);
8783
8784 APFloat::opStatus MinStatus =
8785 MinFloat.convertFromAPInt(Input: MinInt, IsSigned, RM: APFloat::rmTowardZero);
8786 APFloat::opStatus MaxStatus =
8787 MaxFloat.convertFromAPInt(Input: MaxInt, IsSigned, RM: APFloat::rmTowardZero);
8788 bool AreExactFloatBounds = !(MinStatus & APFloat::opStatus::opInexact) &&
8789 !(MaxStatus & APFloat::opStatus::opInexact);
8790
8791 // If the integer bounds are exactly representable as floats, emit a
8792 // min+max+fptoi sequence. Otherwise we have to use a sequence of comparisons
8793 // and selects.
8794 if (AreExactFloatBounds) {
8795 // Clamp Src by MinFloat from below. If Src is NaN the result is MinFloat.
8796 auto MaxC = MIRBuilder.buildFConstant(Res: SrcTy, Val: MinFloat);
8797 auto MaxP =
8798 MIRBuilder.buildFCmp(Pred: CmpInst::FCMP_OGT, Res: LLT::integer(SizeInBits: 1), Op0: Src, Op1: MaxC);
8799 auto Max = MIRBuilder.buildSelect(Res: SrcTy, Tst: MaxP, Op0: Src, Op1: MaxC);
8800 // Clamp by MaxFloat from above. NaN cannot occur.
8801 auto MinC = MIRBuilder.buildFConstant(Res: SrcTy, Val: MaxFloat);
8802 auto MinP = MIRBuilder.buildFCmp(Pred: CmpInst::FCMP_OLT, Res: LLT::integer(SizeInBits: 1), Op0: Max,
8803 Op1: MinC, Flags: MachineInstr::FmNoNans);
8804 auto Min =
8805 MIRBuilder.buildSelect(Res: SrcTy, Tst: MinP, Op0: Max, Op1: MinC, Flags: MachineInstr::FmNoNans);
8806 // Convert clamped value to integer. In the unsigned case we're done,
8807 // because we mapped NaN to MinFloat, which will cast to zero.
8808 if (!IsSigned) {
8809 MIRBuilder.buildFPTOUI(Dst, Src0: Min);
8810 MI.eraseFromParent();
8811 return Legalized;
8812 }
8813
8814 // Otherwise, select 0 if Src is NaN.
8815 auto FpToInt = MIRBuilder.buildFPTOSI(Dst: DstTy, Src0: Min);
8816 auto IsZero =
8817 MIRBuilder.buildFCmp(Pred: CmpInst::FCMP_UNO, Res: LLT::integer(SizeInBits: 1), Op0: Src, Op1: Src);
8818 MIRBuilder.buildSelect(Res: Dst, Tst: IsZero, Op0: MIRBuilder.buildConstant(Res: DstTy, Val: 0),
8819 Op1: FpToInt);
8820 MI.eraseFromParent();
8821 return Legalized;
8822 }
8823
8824 // Result of direct conversion. The assumption here is that the operation is
8825 // non-trapping and it's fine to apply it to an out-of-range value if we
8826 // select it away later.
8827 auto FpToInt = IsSigned ? MIRBuilder.buildFPTOSI(Dst: DstTy, Src0: Src)
8828 : MIRBuilder.buildFPTOUI(Dst: DstTy, Src0: Src);
8829
8830 // If Src ULT MinFloat, select MinInt. In particular, this also selects
8831 // MinInt if Src is NaN.
8832 auto ULT = MIRBuilder.buildFCmp(Pred: CmpInst::FCMP_ULT, Res: LLT::integer(SizeInBits: 1), Op0: Src,
8833 Op1: MIRBuilder.buildFConstant(Res: SrcTy, Val: MinFloat));
8834 auto Max = MIRBuilder.buildSelect(
8835 Res: DstTy, Tst: ULT, Op0: MIRBuilder.buildConstant(Res: DstTy, Val: MinInt), Op1: FpToInt);
8836 // If Src OGT MaxFloat, select MaxInt.
8837 auto OGT = MIRBuilder.buildFCmp(Pred: CmpInst::FCMP_OGT, Res: LLT::integer(SizeInBits: 1), Op0: Src,
8838 Op1: MIRBuilder.buildFConstant(Res: SrcTy, Val: MaxFloat));
8839
8840 // In the unsigned case we are done, because we mapped NaN to MinInt, which
8841 // is already zero.
8842 if (!IsSigned) {
8843 MIRBuilder.buildSelect(Res: Dst, Tst: OGT, Op0: MIRBuilder.buildConstant(Res: DstTy, Val: MaxInt),
8844 Op1: Max);
8845 MI.eraseFromParent();
8846 return Legalized;
8847 }
8848
8849 // Otherwise, select 0 if Src is NaN.
8850 auto Min = MIRBuilder.buildSelect(
8851 Res: DstTy, Tst: OGT, Op0: MIRBuilder.buildConstant(Res: DstTy, Val: MaxInt), Op1: Max);
8852 auto IsZero =
8853 MIRBuilder.buildFCmp(Pred: CmpInst::FCMP_UNO, Res: LLT::integer(SizeInBits: 1), Op0: Src, Op1: Src);
8854 MIRBuilder.buildSelect(Res: Dst, Tst: IsZero, Op0: MIRBuilder.buildConstant(Res: DstTy, Val: 0), Op1: Min);
8855 MI.eraseFromParent();
8856 return Legalized;
8857}
8858
8859// Floating-point conversions using truncating and extending loads and stores.
8860LegalizerHelper::LegalizeResult
8861LegalizerHelper::lowerFPExtAndTruncMem(MachineInstr &MI) {
8862 assert((MI.getOpcode() == TargetOpcode::G_FPEXT ||
8863 MI.getOpcode() == TargetOpcode::G_FPTRUNC) &&
8864 "Only G_FPEXT and G_FPTRUNC are expected");
8865
8866 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
8867 MachinePointerInfo PtrInfo;
8868 unsigned StoreOpc;
8869 unsigned LoadOpc;
8870 LLT StackTy;
8871 if (MI.getOpcode() == TargetOpcode::G_FPEXT) {
8872 StackTy = SrcTy;
8873 StoreOpc = TargetOpcode::G_STORE;
8874 LoadOpc = TargetOpcode::G_FPEXTLOAD;
8875 } else {
8876 StackTy = DstTy;
8877 StoreOpc = TargetOpcode::G_FPTRUNCSTORE;
8878 LoadOpc = TargetOpcode::G_LOAD;
8879 }
8880
8881 Align StackTyAlign = getStackTemporaryAlignment(Ty: StackTy);
8882 auto StackTemp =
8883 createStackTemporary(Bytes: StackTy.getSizeInBytes(), Alignment: StackTyAlign, PtrInfo);
8884
8885 MachineFunction &MF = MIRBuilder.getMF();
8886 auto *StoreMMO = MF.getMachineMemOperand(PtrInfo, F: MachineMemOperand::MOStore,
8887 MemTy: StackTy, BaseAlignment: StackTyAlign);
8888 MIRBuilder.buildStoreInstr(Opcode: StoreOpc, Val: SrcReg, Addr: StackTemp, MMO&: *StoreMMO);
8889
8890 auto *LoadMMO = MF.getMachineMemOperand(PtrInfo, F: MachineMemOperand::MOLoad,
8891 MemTy: StackTy, BaseAlignment: StackTyAlign);
8892 MIRBuilder.buildLoadInstr(Opcode: LoadOpc, Res: DstReg, Addr: StackTemp, MMO&: *LoadMMO);
8893
8894 MI.eraseFromParent();
8895 return Legalized;
8896}
8897
8898// Expand a bf16 -> f32/f64 fpext with a shift and bitcast. This is based on the
8899// SDAG ISD::BF16_TO_FP lowering.
8900LegalizerHelper::LegalizeResult
8901LegalizerHelper::lowerFPEXT_BF16(MachineInstr &MI) {
8902 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
8903 assert(SrcTy.getScalarType().isBFloat16() &&
8904 "expected a bf16 source for bf16 fpext lowering");
8905
8906 LLT I16Ty = SrcTy.changeElementType(NewEltTy: LLT::integer(SizeInBits: 16));
8907 LLT I32Ty = SrcTy.changeElementType(NewEltTy: LLT::integer(SizeInBits: 32));
8908 LLT F32Ty = SrcTy.changeElementType(NewEltTy: LLT::float32());
8909
8910 auto SrcI =
8911 MIRBuilder.buildAnyExt(Res: I32Ty, Op: MIRBuilder.buildBitcast(Dst: I16Ty, Src: SrcReg));
8912 auto Shl =
8913 MIRBuilder.buildShl(Dst: I32Ty, Src0: SrcI, Src1: MIRBuilder.buildConstant(Res: I32Ty, Val: 16));
8914
8915 if (DstTy.getScalarType().isFloat32())
8916 MIRBuilder.buildBitcast(Dst: DstReg, Src: Shl);
8917 else
8918 MIRBuilder.buildFPExt(Res: DstReg, Op: MIRBuilder.buildBitcast(Dst: F32Ty, Src: Shl));
8919
8920 MI.eraseFromParent();
8921 return Legalized;
8922}
8923
8924LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPEXT(MachineInstr &MI) {
8925 auto [DstTy, SrcTy] = MI.getFirst2LLTs();
8926 if (SrcTy.getScalarType().isBFloat16() &&
8927 (DstTy.getScalarType().isFloat32() || DstTy.getScalarType().isFloat64()))
8928 return lowerFPEXT_BF16(MI);
8929
8930 return lowerFPExtAndTruncMem(MI);
8931}
8932
8933// f64 -> f16 conversion using round-to-nearest-even rounding mode.
8934LegalizerHelper::LegalizeResult
8935LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
8936 const LLT S1 = LLT::scalar(SizeInBits: 1);
8937 const LLT I32 = LLT::integer(SizeInBits: 32);
8938
8939 auto [Dst, Src] = MI.getFirst2Regs();
8940 assert(MRI.getType(Dst).getScalarType() == LLT::float16() &&
8941 MRI.getType(Src).getScalarType() == LLT::float64());
8942
8943 if (MRI.getType(Reg: Src).isVector()) // TODO: Handle vectors directly.
8944 return UnableToLegalize;
8945
8946 if (MI.getFlag(Flag: MachineInstr::FmAfn)) {
8947 unsigned Flags = MI.getFlags();
8948 auto Src32 = MIRBuilder.buildFPTrunc(Res: LLT::float32(), Op: Src, Flags);
8949 MIRBuilder.buildFPTrunc(Res: Dst, Op: Src32, Flags);
8950 MI.eraseFromParent();
8951 return Legalized;
8952 }
8953
8954 const unsigned ExpMask = 0x7ff;
8955 const unsigned ExpBiasf64 = 1023;
8956 const unsigned ExpBiasf16 = 15;
8957
8958 auto Unmerge = MIRBuilder.buildUnmerge(Res: I32, Op: Src);
8959 Register U = Unmerge.getReg(Idx: 0);
8960 Register UH = Unmerge.getReg(Idx: 1);
8961
8962 auto E = MIRBuilder.buildLShr(Dst: I32, Src0: UH, Src1: MIRBuilder.buildConstant(Res: I32, Val: 20));
8963 E = MIRBuilder.buildAnd(Dst: I32, Src0: E, Src1: MIRBuilder.buildConstant(Res: I32, Val: ExpMask));
8964
8965 // Subtract the fp64 exponent bias (1023) to get the real exponent and
8966 // add the f16 bias (15) to get the biased exponent for the f16 format.
8967 E = MIRBuilder.buildAdd(
8968 Dst: I32, Src0: E, Src1: MIRBuilder.buildConstant(Res: I32, Val: -ExpBiasf64 + ExpBiasf16));
8969
8970 auto M = MIRBuilder.buildLShr(Dst: I32, Src0: UH, Src1: MIRBuilder.buildConstant(Res: I32, Val: 8));
8971 M = MIRBuilder.buildAnd(Dst: I32, Src0: M, Src1: MIRBuilder.buildConstant(Res: I32, Val: 0xffe));
8972
8973 auto MaskedSig =
8974 MIRBuilder.buildAnd(Dst: I32, Src0: UH, Src1: MIRBuilder.buildConstant(Res: I32, Val: 0x1ff));
8975 MaskedSig = MIRBuilder.buildOr(Dst: I32, Src0: MaskedSig, Src1: U);
8976
8977 auto Zero = MIRBuilder.buildConstant(Res: I32, Val: 0);
8978 auto SigCmpNE0 = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_NE, Res: S1, Op0: MaskedSig, Op1: Zero);
8979 auto Lo40Set = MIRBuilder.buildZExt(Res: I32, Op: SigCmpNE0);
8980 M = MIRBuilder.buildOr(Dst: I32, Src0: M, Src1: Lo40Set);
8981
8982 // (M != 0 ? 0x0200 : 0) | 0x7c00;
8983 auto Bits0x200 = MIRBuilder.buildConstant(Res: I32, Val: 0x0200);
8984 auto CmpM_NE0 = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_NE, Res: S1, Op0: M, Op1: Zero);
8985 auto SelectCC = MIRBuilder.buildSelect(Res: I32, Tst: CmpM_NE0, Op0: Bits0x200, Op1: Zero);
8986
8987 auto Bits0x7c00 = MIRBuilder.buildConstant(Res: I32, Val: 0x7c00);
8988 auto I = MIRBuilder.buildOr(Dst: I32, Src0: SelectCC, Src1: Bits0x7c00);
8989
8990 // N = M | (E << 12);
8991 auto EShl12 = MIRBuilder.buildShl(Dst: I32, Src0: E, Src1: MIRBuilder.buildConstant(Res: I32, Val: 12));
8992 auto N = MIRBuilder.buildOr(Dst: I32, Src0: M, Src1: EShl12);
8993
8994 // B = clamp(1-E, 0, 13);
8995 auto One = MIRBuilder.buildConstant(Res: I32, Val: 1);
8996 auto OneSubExp = MIRBuilder.buildSub(Dst: I32, Src0: One, Src1: E);
8997 auto B = MIRBuilder.buildSMax(Dst: I32, Src0: OneSubExp, Src1: Zero);
8998 B = MIRBuilder.buildSMin(Dst: I32, Src0: B, Src1: MIRBuilder.buildConstant(Res: I32, Val: 13));
8999
9000 auto SigSetHigh =
9001 MIRBuilder.buildOr(Dst: I32, Src0: M, Src1: MIRBuilder.buildConstant(Res: I32, Val: 0x1000));
9002
9003 auto D = MIRBuilder.buildLShr(Dst: I32, Src0: SigSetHigh, Src1: B);
9004 auto D0 = MIRBuilder.buildShl(Dst: I32, Src0: D, Src1: B);
9005
9006 auto D0_NE_SigSetHigh = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_NE, Res: S1,
9007 Op0: D0, Op1: SigSetHigh);
9008 auto D1 = MIRBuilder.buildZExt(Res: I32, Op: D0_NE_SigSetHigh);
9009 D = MIRBuilder.buildOr(Dst: I32, Src0: D, Src1: D1);
9010
9011 auto CmpELtOne = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_SLT, Res: S1, Op0: E, Op1: One);
9012 auto V = MIRBuilder.buildSelect(Res: I32, Tst: CmpELtOne, Op0: D, Op1: N);
9013
9014 auto VLow3 = MIRBuilder.buildAnd(Dst: I32, Src0: V, Src1: MIRBuilder.buildConstant(Res: I32, Val: 7));
9015 V = MIRBuilder.buildLShr(Dst: I32, Src0: V, Src1: MIRBuilder.buildConstant(Res: I32, Val: 2));
9016
9017 auto VLow3Eq3 = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_EQ, Res: S1, Op0: VLow3,
9018 Op1: MIRBuilder.buildConstant(Res: I32, Val: 3));
9019 auto V0 = MIRBuilder.buildZExt(Res: I32, Op: VLow3Eq3);
9020
9021 auto VLow3Gt5 = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_SGT, Res: S1, Op0: VLow3,
9022 Op1: MIRBuilder.buildConstant(Res: I32, Val: 5));
9023 auto V1 = MIRBuilder.buildZExt(Res: I32, Op: VLow3Gt5);
9024
9025 V1 = MIRBuilder.buildOr(Dst: I32, Src0: V0, Src1: V1);
9026 V = MIRBuilder.buildAdd(Dst: I32, Src0: V, Src1: V1);
9027
9028 auto CmpEGt30 = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_SGT, Res: S1, Op0: E,
9029 Op1: MIRBuilder.buildConstant(Res: I32, Val: 30));
9030 V = MIRBuilder.buildSelect(Res: I32, Tst: CmpEGt30,
9031 Op0: MIRBuilder.buildConstant(Res: I32, Val: 0x7c00), Op1: V);
9032
9033 auto CmpEGt1039 = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_EQ, Res: S1, Op0: E,
9034 Op1: MIRBuilder.buildConstant(Res: I32, Val: 1039));
9035 V = MIRBuilder.buildSelect(Res: I32, Tst: CmpEGt1039, Op0: I, Op1: V);
9036
9037 // Extract the sign bit.
9038 auto Sign = MIRBuilder.buildLShr(Dst: I32, Src0: UH, Src1: MIRBuilder.buildConstant(Res: I32, Val: 16));
9039 Sign = MIRBuilder.buildAnd(Dst: I32, Src0: Sign, Src1: MIRBuilder.buildConstant(Res: I32, Val: 0x8000));
9040
9041 // Insert the sign bit
9042 V = MIRBuilder.buildOr(Dst: I32, Src0: Sign, Src1: V);
9043
9044 MIRBuilder.buildTrunc(Res: Dst, Op: V);
9045 MI.eraseFromParent();
9046 return Legalized;
9047}
9048
9049// f32 -> bf16 conversion using round-to-nearest-even rounding mode.
9050LegalizerHelper::LegalizeResult
9051LegalizerHelper::lowerFPTRUNC_F32_TO_BF16(MachineInstr &MI) {
9052 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
9053 assert(DstTy.getScalarType() == LLT::bfloat16() &&
9054 SrcTy.getScalarType() == LLT::float32());
9055
9056 LLT I1Ty = SrcTy.changeElementType(NewEltTy: LLT::integer(SizeInBits: 1));
9057 LLT I16Ty = SrcTy.changeElementType(NewEltTy: LLT::integer(SizeInBits: 16));
9058 LLT I32Ty = SrcTy.changeElementType(NewEltTy: LLT::integer(SizeInBits: 32));
9059
9060 auto SrcI = MIRBuilder.buildBitcast(Dst: I32Ty, Src: SrcReg);
9061
9062 // Conversions should set NaN's quiet bit. This also prevents NaNs from
9063 // turning into infinities.
9064 auto NaN = MIRBuilder.buildOr(Dst: I32Ty, Src0: SrcI,
9065 Src1: MIRBuilder.buildConstant(Res: I32Ty, Val: 0x400000));
9066
9067 // Factor in the contribution of the low 16 bits.
9068 auto Lsb =
9069 MIRBuilder.buildLShr(Dst: I32Ty, Src0: SrcI, Src1: MIRBuilder.buildConstant(Res: I32Ty, Val: 16));
9070 Lsb = MIRBuilder.buildAnd(Dst: I32Ty, Src0: Lsb, Src1: MIRBuilder.buildConstant(Res: I32Ty, Val: 1));
9071 auto RoundingBias =
9072 MIRBuilder.buildAdd(Dst: I32Ty, Src0: Lsb, Src1: MIRBuilder.buildConstant(Res: I32Ty, Val: 0x7fff));
9073 auto Add = MIRBuilder.buildAdd(Dst: I32Ty, Src0: SrcI, Src1: RoundingBias);
9074
9075 // Don't round if we had a NaN, we don't want to turn 0x7fffffff into
9076 // 0x80000000.
9077 if (!MI.getFlag(Flag: MachineInstr::FmNoNans)) {
9078 auto IsNaN = MIRBuilder.buildFCmp(Pred: CmpInst::FCMP_UNO, Res: I1Ty, Op0: SrcReg,
9079 Op1: MIRBuilder.buildFConstant(Res: SrcTy, Val: 0));
9080 Add = MIRBuilder.buildSelect(Res: I32Ty, Tst: IsNaN, Op0: NaN, Op1: Add);
9081 }
9082
9083 // Now that we have rounded, shift the bits into position.
9084 auto Srl =
9085 MIRBuilder.buildLShr(Dst: I32Ty, Src0: Add, Src1: MIRBuilder.buildConstant(Res: I32Ty, Val: 16));
9086 auto Trunc = MIRBuilder.buildTrunc(Res: I16Ty, Op: Srl);
9087 MIRBuilder.buildBitcast(Dst: DstReg, Src: Trunc);
9088 MI.eraseFromParent();
9089 return Legalized;
9090}
9091
9092// Round a wide fp value to ResultTy's element size, forcing inexact
9093// results to the odd value so a subsequent narrowing round is correct. This
9094// avoids double-rounding when narrowing e.g. f64 -> f32 -> bf16. See Boldo &
9095// Melquiond, "When double rounding is odd" (2005).
9096Register LegalizerHelper::lowerRoundInexactToOdd(LLT ResultTy, Register Op) {
9097 LLT OperandTy = MRI.getType(Reg: Op);
9098 if (OperandTy.getScalarType() == ResultTy.getScalarType())
9099 return Op;
9100
9101 LLT ResultIntTy =
9102 ResultTy.changeElementType(NewEltTy: LLT::integer(SizeInBits: ResultTy.getScalarSizeInBits()));
9103 LLT ResultCCTy = ResultTy.changeElementType(NewEltTy: LLT::integer(SizeInBits: 1));
9104 LLT OperandCCTy = OperandTy.changeElementType(NewEltTy: LLT::integer(SizeInBits: 1));
9105
9106 auto Narrow = MIRBuilder.buildFPTrunc(Res: ResultTy, Op);
9107 auto NarrowAsWide = MIRBuilder.buildFPExt(Res: OperandTy, Op: Narrow);
9108
9109 auto NarrowBits = MIRBuilder.buildBitcast(Dst: ResultIntTy, Src: Narrow);
9110 auto One = MIRBuilder.buildConstant(Res: ResultIntTy, Val: 1);
9111 auto NegativeOne = MIRBuilder.buildConstant(Res: ResultIntTy, Val: -1);
9112 auto Zero = MIRBuilder.buildConstant(Res: ResultIntTy, Val: 0);
9113 auto And = MIRBuilder.buildAnd(Dst: ResultIntTy, Src0: NarrowBits, Src1: One);
9114 // The result is already odd so we don't need to do anything.
9115 auto AlreadyOdd =
9116 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_NE, Res: ResultCCTy, Op0: And, Op1: Zero);
9117
9118 // We keep results which are exact, odd or NaN.
9119 auto KeepNarrow =
9120 MIRBuilder.buildFCmp(Pred: CmpInst::FCMP_UEQ, Res: OperandCCTy, Op0: Op, Op1: NarrowAsWide);
9121 KeepNarrow = MIRBuilder.buildOr(Dst: OperandCCTy, Src0: KeepNarrow, Src1: AlreadyOdd);
9122 // We morally performed a round-down if AbsNarrow is smaller than AbsWide.
9123 auto AbsWide = MIRBuilder.buildFAbs(Dst: OperandTy, Src0: Op);
9124 auto AbsNarrowAsWide = MIRBuilder.buildFAbs(Dst: OperandTy, Src0: NarrowAsWide);
9125 auto NarrowIsRd = MIRBuilder.buildFCmp(Pred: CmpInst::FCMP_OGT, Res: OperandCCTy,
9126 Op0: AbsWide, Op1: AbsNarrowAsWide);
9127 // If narrow is the rounded-down value, pick the rounded-up value as it will
9128 // be odd; otherwise adjust down.
9129 auto Adjust =
9130 MIRBuilder.buildSelect(Res: ResultIntTy, Tst: NarrowIsRd, Op0: One, Op1: NegativeOne);
9131 auto Adjusted = MIRBuilder.buildAdd(Dst: ResultIntTy, Src0: NarrowBits, Src1: Adjust);
9132 auto Res =
9133 MIRBuilder.buildSelect(Res: ResultIntTy, Tst: KeepNarrow, Op0: NarrowBits, Op1: Adjusted);
9134 return MIRBuilder.buildBitcast(Dst: ResultTy, Src: Res).getReg(Idx: 0);
9135}
9136
9137// f64 -> bf16 conversion, correcting for double rounding.
9138LegalizerHelper::LegalizeResult
9139LegalizerHelper::lowerFPTRUNC_F64_TO_BF16(MachineInstr &MI) {
9140 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
9141 assert(DstTy.getScalarType() == LLT::bfloat16() &&
9142 SrcTy.getScalarType() == LLT::float64());
9143
9144 LLT F32Ty = SrcTy.changeElementType(NewEltTy: LLT::float32());
9145 Register OddF32 = lowerRoundInexactToOdd(ResultTy: F32Ty, Op: SrcReg);
9146 MIRBuilder.buildFPTrunc(Res: DstReg, Op: OddF32, Flags: MI.getFlags());
9147 MI.eraseFromParent();
9148 return Legalized;
9149}
9150
9151LegalizerHelper::LegalizeResult
9152LegalizerHelper::lowerFPTRUNC(MachineInstr &MI) {
9153 auto [DstTy, SrcTy] = MI.getFirst2LLTs();
9154 if (DstTy.getScalarType().isFloat16() && SrcTy.getScalarType().isFloat64())
9155 return lowerFPTRUNC_F64_TO_F16(MI);
9156
9157 if (DstTy.getScalarType().isBFloat16() && SrcTy.getScalarType().isFloat32())
9158 return lowerFPTRUNC_F32_TO_BF16(MI);
9159
9160 if (DstTy.getScalarType().isBFloat16() && SrcTy.getScalarType().isFloat64())
9161 return lowerFPTRUNC_F64_TO_BF16(MI);
9162
9163 return lowerFPExtAndTruncMem(MI);
9164}
9165
9166LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPOWI(MachineInstr &MI) {
9167 auto [Dst, Src0, Src1] = MI.getFirst3Regs();
9168 LLT Ty = MRI.getType(Reg: Dst);
9169
9170 auto CvtSrc1 = MIRBuilder.buildSITOFP(Dst: Ty, Src0: Src1);
9171 MIRBuilder.buildFPow(Dst, Src0, Src1: CvtSrc1, Flags: MI.getFlags());
9172 MI.eraseFromParent();
9173 return Legalized;
9174}
9175
9176LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMODF(MachineInstr &MI) {
9177 auto [DstFrac, DstInt, Src] = MI.getFirst3Regs();
9178 LLT Ty = MRI.getType(Reg: Src);
9179 auto Flags = MI.getFlags();
9180 const LLT CondTy = Ty.changeElementType(NewEltTy: LLT::integer(SizeInBits: 1));
9181
9182 auto IntPart = MIRBuilder.buildIntrinsicTrunc(Dst: Ty, Src0: Src, Flags);
9183 auto FracPart = MIRBuilder.buildFSub(Dst: Ty, Src0: Src, Src1: IntPart, Flags);
9184
9185 Register FracToUse;
9186 if (MI.getFlag(Flag: MachineInstr::FmNoInfs)) {
9187 FracToUse = FracPart.getReg(Idx: 0);
9188 } else {
9189 auto Abs = MIRBuilder.buildFAbs(Dst: Ty, Src0: Src, Flags);
9190 const fltSemantics &Semantics = getFltSemanticForLLT(Ty: Ty.getScalarType());
9191 auto Inf = MIRBuilder.buildFConstant(Res: Ty, Val: APFloat::getInf(Sem: Semantics));
9192 auto IsInf = MIRBuilder.buildFCmp(Pred: CmpInst::FCMP_OEQ, Res: CondTy, Op0: Abs, Op1: Inf);
9193 auto Zero = MIRBuilder.buildFConstant(Res: Ty, Val: 0.0);
9194 auto Select = MIRBuilder.buildSelect(Res: Ty, Tst: IsInf, Op0: Zero, Op1: FracPart);
9195 FracToUse = Select.getReg(Idx: 0);
9196 }
9197
9198 MIRBuilder.buildFCopysign(Dst: DstFrac, Src0: FracToUse, Src1: Src, Flags);
9199 MIRBuilder.buildCopy(Res: DstInt, Op: IntPart.getReg(Idx: 0));
9200
9201 MI.eraseFromParent();
9202 return Legalized;
9203}
9204
9205static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
9206 switch (Opc) {
9207 case TargetOpcode::G_SMIN:
9208 return CmpInst::ICMP_SLT;
9209 case TargetOpcode::G_SMAX:
9210 return CmpInst::ICMP_SGT;
9211 case TargetOpcode::G_UMIN:
9212 return CmpInst::ICMP_ULT;
9213 case TargetOpcode::G_UMAX:
9214 return CmpInst::ICMP_UGT;
9215 default:
9216 llvm_unreachable("not in integer min/max");
9217 }
9218}
9219
9220LegalizerHelper::LegalizeResult LegalizerHelper::lowerMinMax(MachineInstr &MI) {
9221 auto [Dst, Src0, Src1] = MI.getFirst3Regs();
9222
9223 const CmpInst::Predicate Pred = minMaxToCompare(Opc: MI.getOpcode());
9224 LLT CmpType = MRI.getType(Reg: Dst).changeElementType(NewEltTy: LLT::integer(SizeInBits: 1));
9225
9226 auto Cmp = MIRBuilder.buildICmp(Pred, Res: CmpType, Op0: Src0, Op1: Src1);
9227 MIRBuilder.buildSelect(Res: Dst, Tst: Cmp, Op0: Src0, Op1: Src1);
9228
9229 MI.eraseFromParent();
9230 return Legalized;
9231}
9232
9233LegalizerHelper::LegalizeResult
9234LegalizerHelper::lowerThreewayCompare(MachineInstr &MI) {
9235 GSUCmp *Cmp = cast<GSUCmp>(Val: &MI);
9236
9237 Register Dst = Cmp->getReg(Idx: 0);
9238 LLT DstTy = MRI.getType(Reg: Dst);
9239 LLT SrcTy = MRI.getType(Reg: Cmp->getReg(Idx: 1));
9240 LLT CmpTy = DstTy.changeElementSize(NewEltSize: 1);
9241
9242 CmpInst::Predicate LTPredicate = Cmp->isSigned()
9243 ? CmpInst::Predicate::ICMP_SLT
9244 : CmpInst::Predicate::ICMP_ULT;
9245 CmpInst::Predicate GTPredicate = Cmp->isSigned()
9246 ? CmpInst::Predicate::ICMP_SGT
9247 : CmpInst::Predicate::ICMP_UGT;
9248
9249 auto Zero = MIRBuilder.buildConstant(Res: DstTy, Val: 0);
9250 auto IsGT = MIRBuilder.buildICmp(Pred: GTPredicate, Res: CmpTy, Op0: Cmp->getLHSReg(),
9251 Op1: Cmp->getRHSReg());
9252 auto IsLT = MIRBuilder.buildICmp(Pred: LTPredicate, Res: CmpTy, Op0: Cmp->getLHSReg(),
9253 Op1: Cmp->getRHSReg());
9254
9255 auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
9256 auto BC = TLI.getBooleanContents(isVec: DstTy.isVector(), /*isFP=*/isFloat: false);
9257 if (TLI.preferSelectsOverBooleanArithmetic(
9258 VT: getApproximateEVTForLLT(Ty: SrcTy, Ctx)) ||
9259 BC == TargetLowering::UndefinedBooleanContent) {
9260 auto One = MIRBuilder.buildConstant(Res: DstTy, Val: 1);
9261 auto SelectZeroOrOne = MIRBuilder.buildSelect(Res: DstTy, Tst: IsGT, Op0: One, Op1: Zero);
9262
9263 auto MinusOne = MIRBuilder.buildConstant(Res: DstTy, Val: -1);
9264 MIRBuilder.buildSelect(Res: Dst, Tst: IsLT, Op0: MinusOne, Op1: SelectZeroOrOne);
9265 } else {
9266 if (BC == TargetLowering::ZeroOrNegativeOneBooleanContent)
9267 std::swap(a&: IsGT, b&: IsLT);
9268 // Extend boolean results to DstTy, which is at least i2, before subtracting
9269 // them.
9270 unsigned BoolExtOp =
9271 MIRBuilder.getBoolExtOp(IsVec: DstTy.isVector(), /*isFP=*/IsFP: false);
9272 IsGT = MIRBuilder.buildInstr(Opc: BoolExtOp, DstOps: {DstTy}, SrcOps: {IsGT});
9273 IsLT = MIRBuilder.buildInstr(Opc: BoolExtOp, DstOps: {DstTy}, SrcOps: {IsLT});
9274 MIRBuilder.buildSub(Dst, Src0: IsGT, Src1: IsLT);
9275 }
9276
9277 MI.eraseFromParent();
9278 return Legalized;
9279}
9280
9281LegalizerHelper::LegalizeResult
9282LegalizerHelper::lowerFCopySign(MachineInstr &MI) {
9283 auto [Dst, DstTy, Src0, Src0Ty, Src1, Src1Ty] = MI.getFirst3RegLLTs();
9284 const int Src0Size = Src0Ty.getScalarSizeInBits();
9285 const int Src1Size = Src1Ty.getScalarSizeInBits();
9286
9287 LLT DstIntTy =
9288 DstTy.changeElementType(NewEltTy: LLT::integer(SizeInBits: DstTy.getScalarSizeInBits()));
9289 LLT Src0IntTy = Src0Ty.changeElementType(NewEltTy: LLT::integer(SizeInBits: Src0Size));
9290 LLT Src1IntTy = Src1Ty.changeElementType(NewEltTy: LLT::integer(SizeInBits: Src1Size));
9291
9292 Register Src0Int = Src0;
9293 Register Src1Int = Src1;
9294
9295 if (!(Src0Ty.getScalarType().isAnyScalar() ||
9296 Src0Ty.getScalarType().isInteger()))
9297 Src0Int = MIRBuilder.buildBitcast(Dst: Src0IntTy, Src: Src0).getReg(Idx: 0);
9298
9299 if (!(Src1Ty.getScalarType().isAnyScalar() ||
9300 Src1Ty.getScalarType().isInteger()))
9301 Src1Int = MIRBuilder.buildBitcast(Dst: Src1IntTy, Src: Src1).getReg(Idx: 0);
9302
9303 auto SignBitMask =
9304 MIRBuilder.buildConstant(Res: Src0IntTy, Val: APInt::getSignMask(BitWidth: Src0Size));
9305
9306 auto NotSignBitMask = MIRBuilder.buildConstant(
9307 Res: Src0IntTy, Val: APInt::getLowBitsSet(numBits: Src0Size, loBitsSet: Src0Size - 1));
9308
9309 Register And0 =
9310 MIRBuilder.buildAnd(Dst: Src0IntTy, Src0: Src0Int, Src1: NotSignBitMask).getReg(Idx: 0);
9311 Register And1;
9312 if (Src0Ty == Src1Ty) {
9313 And1 = MIRBuilder.buildAnd(Dst: Src1IntTy, Src0: Src1Int, Src1: SignBitMask).getReg(Idx: 0);
9314 } else if (Src0Size > Src1Size) {
9315 auto ShiftAmt = MIRBuilder.buildConstant(Res: Src0IntTy, Val: Src0Size - Src1Size);
9316 auto Zext = MIRBuilder.buildZExt(Res: Src0IntTy, Op: Src1Int);
9317 auto Shift = MIRBuilder.buildShl(Dst: Src0IntTy, Src0: Zext, Src1: ShiftAmt);
9318 And1 = MIRBuilder.buildAnd(Dst: Src0IntTy, Src0: Shift, Src1: SignBitMask).getReg(Idx: 0);
9319 } else {
9320 auto ShiftAmt = MIRBuilder.buildConstant(Res: Src1IntTy, Val: Src1Size - Src0Size);
9321 auto Shift = MIRBuilder.buildLShr(Dst: Src1IntTy, Src0: Src1Int, Src1: ShiftAmt);
9322 auto Trunc = MIRBuilder.buildTrunc(Res: Src0IntTy, Op: Shift);
9323 And1 = MIRBuilder.buildAnd(Dst: Src0IntTy, Src0: Trunc, Src1: SignBitMask).getReg(Idx: 0);
9324 }
9325
9326 // Be careful about setting nsz/nnan/ninf on every instruction, since the
9327 // constants are a nan and -0.0, but the final result should preserve
9328 // everything.
9329 unsigned Flags = MI.getFlags();
9330
9331 // We masked the sign bit and the not-sign bit, so these are disjoint.
9332 Flags |= MachineInstr::Disjoint;
9333
9334 if (DstTy == DstIntTy)
9335 MIRBuilder.buildOr(Dst, Src0: And0, Src1: And1, Flags).getReg(Idx: 0);
9336 else {
9337 Register NewDst = MIRBuilder.buildOr(Dst: DstIntTy, Src0: And0, Src1: And1, Flags).getReg(Idx: 0);
9338 MIRBuilder.buildBitcast(Dst, Src: NewDst);
9339 }
9340
9341 MI.eraseFromParent();
9342 return Legalized;
9343}
9344
9345LegalizerHelper::LegalizeResult
9346LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) {
9347 // FIXME: fminnum/fmaxnum and fminimumnum/fmaximumnum should not have
9348 // identical handling. fminimumnum/fmaximumnum also need a path that do not
9349 // depend on fminnum/fmaxnum.
9350
9351 unsigned NewOp;
9352 switch (MI.getOpcode()) {
9353 case TargetOpcode::G_FMINNUM:
9354 NewOp = TargetOpcode::G_FMINNUM_IEEE;
9355 break;
9356 case TargetOpcode::G_FMINIMUMNUM:
9357 NewOp = TargetOpcode::G_FMINNUM;
9358 break;
9359 case TargetOpcode::G_FMAXNUM:
9360 NewOp = TargetOpcode::G_FMAXNUM_IEEE;
9361 break;
9362 case TargetOpcode::G_FMAXIMUMNUM:
9363 NewOp = TargetOpcode::G_FMAXNUM;
9364 break;
9365 default:
9366 llvm_unreachable("unexpected min/max opcode");
9367 }
9368
9369 auto [Dst, Src0, Src1] = MI.getFirst3Regs();
9370 LLT Ty = MRI.getType(Reg: Dst);
9371
9372 if (!MI.getFlag(Flag: MachineInstr::FmNoNans)) {
9373 // Insert canonicalizes if it's possible we need to quiet to get correct
9374 // sNaN behavior.
9375
9376 // Note this must be done here, and not as an optimization combine in the
9377 // absence of a dedicate quiet-snan instruction as we're using an
9378 // omni-purpose G_FCANONICALIZE.
9379 if (!VT->isKnownNeverSNaN(Val: Src0))
9380 Src0 = MIRBuilder.buildFCanonicalize(Dst: Ty, Src0, Flags: MI.getFlags()).getReg(Idx: 0);
9381
9382 if (!VT->isKnownNeverSNaN(Val: Src1))
9383 Src1 = MIRBuilder.buildFCanonicalize(Dst: Ty, Src0: Src1, Flags: MI.getFlags()).getReg(Idx: 0);
9384 }
9385
9386 // If there are no nans, it's safe to simply replace this with the non-IEEE
9387 // version.
9388 MIRBuilder.buildInstr(Opc: NewOp, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags: MI.getFlags());
9389 MI.eraseFromParent();
9390 return Legalized;
9391}
9392
9393LegalizerHelper::LegalizeResult
9394LegalizerHelper::lowerFMinimumMaximum(MachineInstr &MI) {
9395 unsigned Opc = MI.getOpcode();
9396 auto [Dst, Src0, Src1] = MI.getFirst3Regs();
9397 LLT Ty = MRI.getType(Reg: Dst);
9398 const LLT CmpTy = Ty.changeElementType(NewEltTy: LLT::integer(SizeInBits: 1));
9399
9400 bool IsMax = (Opc == TargetOpcode::G_FMAXIMUM);
9401 unsigned OpcIeee =
9402 IsMax ? TargetOpcode::G_FMAXNUM_IEEE : TargetOpcode::G_FMINNUM_IEEE;
9403 unsigned OpcNonIeee =
9404 IsMax ? TargetOpcode::G_FMAXNUM : TargetOpcode::G_FMINNUM;
9405 bool MinMaxMustRespectOrderedZero = false;
9406 Register Res;
9407
9408 // IEEE variants don't need canonicalization
9409 if (LI.isLegalOrCustom(Query: {OpcIeee, Ty})) {
9410 Res = MIRBuilder.buildInstr(Opc: OpcIeee, DstOps: {Ty}, SrcOps: {Src0, Src1}).getReg(Idx: 0);
9411 MinMaxMustRespectOrderedZero = true;
9412 } else if (LI.isLegalOrCustom(Query: {OpcNonIeee, Ty})) {
9413 Res = MIRBuilder.buildInstr(Opc: OpcNonIeee, DstOps: {Ty}, SrcOps: {Src0, Src1}).getReg(Idx: 0);
9414 } else {
9415 auto Compare = MIRBuilder.buildFCmp(
9416 Pred: IsMax ? CmpInst::FCMP_OGT : CmpInst::FCMP_OLT, Res: CmpTy, Op0: Src0, Op1: Src1);
9417 Res = MIRBuilder.buildSelect(Res: Ty, Tst: Compare, Op0: Src0, Op1: Src1).getReg(Idx: 0);
9418 }
9419
9420 // Propagate any NaN of both operands
9421 if (!MI.getFlag(Flag: MachineInstr::FmNoNans) &&
9422 (!VT->isKnownNeverNaN(Val: Src0) || !VT->isKnownNeverNaN(Val: Src1))) {
9423 auto IsOrdered = MIRBuilder.buildFCmp(Pred: CmpInst::FCMP_ORD, Res: CmpTy, Op0: Src0, Op1: Src1);
9424
9425 LLT ElementTy = Ty.isScalar() ? Ty : Ty.getElementType();
9426 APFloat NaNValue = APFloat::getNaN(Sem: getFltSemanticForLLT(Ty: ElementTy));
9427 Register NaN = MIRBuilder.buildFConstant(Res: ElementTy, Val: NaNValue).getReg(Idx: 0);
9428 if (Ty.isVector())
9429 NaN = MIRBuilder.buildSplatBuildVector(Res: Ty, Src: NaN).getReg(Idx: 0);
9430
9431 Res = MIRBuilder.buildSelect(Res: Ty, Tst: IsOrdered, Op0: Res, Op1: NaN).getReg(Idx: 0);
9432 }
9433
9434 // fminimum/fmaximum requires -0.0 less than +0.0
9435 if (!MinMaxMustRespectOrderedZero && !MI.getFlag(Flag: MachineInstr::FmNsz)) {
9436 GISelValueTracking VT(MIRBuilder.getMF());
9437 KnownFPClass Src0Info = VT.computeKnownFPClass(R: Src0, InterestedClasses: fcZero);
9438 KnownFPClass Src1Info = VT.computeKnownFPClass(R: Src1, InterestedClasses: fcZero);
9439
9440 if (!Src0Info.isKnownNeverZero() && !Src1Info.isKnownNeverZero()) {
9441 const unsigned Flags = MI.getFlags();
9442 Register Zero = MIRBuilder.buildFConstant(Res: Ty, Val: 0.0).getReg(Idx: 0);
9443 auto IsZero = MIRBuilder.buildFCmp(Pred: CmpInst::FCMP_OEQ, Res: CmpTy, Op0: Res, Op1: Zero);
9444
9445 unsigned TestClass = IsMax ? fcPosZero : fcNegZero;
9446
9447 auto LHSTestZero = MIRBuilder.buildIsFPClass(Res: CmpTy, Src: Src0, Mask: TestClass);
9448 auto LHSSelect =
9449 MIRBuilder.buildSelect(Res: Ty, Tst: LHSTestZero, Op0: Src0, Op1: Res, Flags);
9450
9451 auto RHSTestZero = MIRBuilder.buildIsFPClass(Res: CmpTy, Src: Src1, Mask: TestClass);
9452 auto RHSSelect =
9453 MIRBuilder.buildSelect(Res: Ty, Tst: RHSTestZero, Op0: Src1, Op1: LHSSelect, Flags);
9454
9455 Res = MIRBuilder.buildSelect(Res: Ty, Tst: IsZero, Op0: RHSSelect, Op1: Res, Flags).getReg(Idx: 0);
9456 }
9457 }
9458
9459 MIRBuilder.buildCopy(Res: Dst, Op: Res);
9460 MI.eraseFromParent();
9461 return Legalized;
9462}
9463
9464LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) {
9465 // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c
9466 Register DstReg = MI.getOperand(i: 0).getReg();
9467 LLT Ty = MRI.getType(Reg: DstReg);
9468 unsigned Flags = MI.getFlags();
9469
9470 auto Mul = MIRBuilder.buildFMul(Dst: Ty, Src0: MI.getOperand(i: 1), Src1: MI.getOperand(i: 2),
9471 Flags);
9472 MIRBuilder.buildFAdd(Dst: DstReg, Src0: Mul, Src1: MI.getOperand(i: 3), Flags);
9473 MI.eraseFromParent();
9474 return Legalized;
9475}
9476
9477LegalizerHelper::LegalizeResult
9478LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) {
9479 auto [DstReg, X] = MI.getFirst2Regs();
9480 const unsigned Flags = MI.getFlags();
9481 const LLT Ty = MRI.getType(Reg: DstReg);
9482 const LLT CondTy = Ty.changeElementType(NewEltTy: LLT::integer(SizeInBits: 1));
9483
9484 // round(x) =>
9485 // t = trunc(x);
9486 // d = fabs(x - t);
9487 // o = copysign(d >= 0.5 ? 1.0 : 0.0, x);
9488 // return t + o;
9489
9490 auto T = MIRBuilder.buildIntrinsicTrunc(Dst: Ty, Src0: X, Flags);
9491
9492 auto Diff = MIRBuilder.buildFSub(Dst: Ty, Src0: X, Src1: T, Flags);
9493 auto AbsDiff = MIRBuilder.buildFAbs(Dst: Ty, Src0: Diff, Flags);
9494
9495 auto Half = MIRBuilder.buildFConstant(Res: Ty, Val: 0.5);
9496 auto Cmp =
9497 MIRBuilder.buildFCmp(Pred: CmpInst::FCMP_OGE, Res: CondTy, Op0: AbsDiff, Op1: Half, Flags);
9498
9499 // Could emit G_UITOFP instead
9500 auto One = MIRBuilder.buildFConstant(Res: Ty, Val: 1.0);
9501 auto Zero = MIRBuilder.buildFConstant(Res: Ty, Val: 0.0);
9502 auto BoolFP = MIRBuilder.buildSelect(Res: Ty, Tst: Cmp, Op0: One, Op1: Zero);
9503 auto SignedOffset = MIRBuilder.buildFCopysign(Dst: Ty, Src0: BoolFP, Src1: X);
9504
9505 MIRBuilder.buildFAdd(Dst: DstReg, Src0: T, Src1: SignedOffset, Flags);
9506
9507 MI.eraseFromParent();
9508 return Legalized;
9509}
9510
9511LegalizerHelper::LegalizeResult LegalizerHelper::lowerFFloor(MachineInstr &MI) {
9512 auto [DstReg, SrcReg] = MI.getFirst2Regs();
9513 unsigned Flags = MI.getFlags();
9514 LLT Ty = MRI.getType(Reg: DstReg);
9515 const LLT CondTy = Ty.changeElementType(NewEltTy: LLT::integer(SizeInBits: 1));
9516
9517 // result = trunc(src);
9518 // if (src < 0.0 && src != result)
9519 // result += -1.0.
9520
9521 auto Trunc = MIRBuilder.buildIntrinsicTrunc(Dst: Ty, Src0: SrcReg, Flags);
9522 auto Zero = MIRBuilder.buildFConstant(Res: Ty, Val: 0.0);
9523
9524 auto Lt0 = MIRBuilder.buildFCmp(Pred: CmpInst::FCMP_OLT, Res: CondTy,
9525 Op0: SrcReg, Op1: Zero, Flags);
9526 auto NeTrunc = MIRBuilder.buildFCmp(Pred: CmpInst::FCMP_ONE, Res: CondTy,
9527 Op0: SrcReg, Op1: Trunc, Flags);
9528 auto And = MIRBuilder.buildAnd(Dst: CondTy, Src0: Lt0, Src1: NeTrunc);
9529 auto AddVal = MIRBuilder.buildSITOFP(Dst: Ty, Src0: And);
9530
9531 MIRBuilder.buildFAdd(Dst: DstReg, Src0: Trunc, Src1: AddVal, Flags);
9532 MI.eraseFromParent();
9533 return Legalized;
9534}
9535
9536LegalizerHelper::LegalizeResult
9537LegalizerHelper::lowerMergeValues(MachineInstr &MI) {
9538 const unsigned NumOps = MI.getNumOperands();
9539 auto [DstReg, DstTy, Src0Reg, Src0Ty] = MI.getFirst2RegLLTs();
9540 unsigned PartSize = Src0Ty.getSizeInBits();
9541
9542 LLT WideTy = LLT::integer(SizeInBits: DstTy.getSizeInBits());
9543 Register ResultReg = MIRBuilder.buildZExt(Res: WideTy, Op: Src0Reg).getReg(Idx: 0);
9544
9545 for (unsigned I = 2; I != NumOps; ++I) {
9546 const unsigned Offset = (I - 1) * PartSize;
9547
9548 Register SrcReg = MI.getOperand(i: I).getReg();
9549 auto ZextInput = MIRBuilder.buildZExt(Res: WideTy, Op: SrcReg);
9550
9551 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg :
9552 MRI.createGenericVirtualRegister(Ty: WideTy);
9553
9554 auto ShiftAmt = MIRBuilder.buildConstant(Res: WideTy, Val: Offset);
9555 auto Shl = MIRBuilder.buildShl(Dst: WideTy, Src0: ZextInput, Src1: ShiftAmt);
9556 MIRBuilder.buildOr(Dst: NextResult, Src0: ResultReg, Src1: Shl);
9557 ResultReg = NextResult;
9558 }
9559
9560 if (DstTy.isPointer()) {
9561 if (MIRBuilder.getDataLayout().isNonIntegralAddressSpace(
9562 AddrSpace: DstTy.getAddressSpace())) {
9563 LLVM_DEBUG(dbgs() << "Not casting nonintegral address space\n");
9564 return UnableToLegalize;
9565 }
9566
9567 MIRBuilder.buildIntToPtr(Dst: DstReg, Src: ResultReg);
9568 } else if (WideTy != DstTy) {
9569 MIRBuilder.buildBitcast(Dst: DstReg, Src: ResultReg);
9570 }
9571
9572 MI.eraseFromParent();
9573 return Legalized;
9574}
9575
9576LegalizerHelper::LegalizeResult
9577LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) {
9578 const unsigned NumDst = MI.getNumOperands() - 1;
9579 Register SrcReg = MI.getOperand(i: NumDst).getReg();
9580 Register Dst0Reg = MI.getOperand(i: 0).getReg();
9581 LLT DstTy = MRI.getType(Reg: Dst0Reg);
9582 if (DstTy.isPointer())
9583 return UnableToLegalize; // TODO
9584
9585 SrcReg = coerceToInteger(Val: SrcReg);
9586 if (!SrcReg)
9587 return UnableToLegalize;
9588
9589 // Expand scalarizing unmerge as bitcast to integer and shift.
9590 LLT IntTy = MRI.getType(Reg: SrcReg);
9591
9592 MIRBuilder.buildTrunc(Res: Dst0Reg, Op: SrcReg);
9593
9594 const unsigned DstSize = DstTy.getSizeInBits();
9595 unsigned Offset = DstSize;
9596 for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) {
9597 auto ShiftAmt = MIRBuilder.buildConstant(Res: IntTy, Val: Offset);
9598 auto Shift = MIRBuilder.buildLShr(Dst: IntTy, Src0: SrcReg, Src1: ShiftAmt);
9599 MIRBuilder.buildTrunc(Res: MI.getOperand(i: I), Op: Shift);
9600 }
9601
9602 MI.eraseFromParent();
9603 return Legalized;
9604}
9605
9606/// Lower a vector extract or insert by writing the vector to a stack temporary
9607/// and reloading the element or vector.
9608///
9609/// %dst = G_EXTRACT_VECTOR_ELT %vec, %idx
9610/// =>
9611/// %stack_temp = G_FRAME_INDEX
9612/// G_STORE %vec, %stack_temp
9613/// %idx = clamp(%idx, %vec.getNumElements())
9614/// %element_ptr = G_PTR_ADD %stack_temp, %idx
9615/// %dst = G_LOAD %element_ptr
9616LegalizerHelper::LegalizeResult
9617LegalizerHelper::lowerExtractInsertVectorElt(MachineInstr &MI) {
9618 Register DstReg = MI.getOperand(i: 0).getReg();
9619 Register SrcVec = MI.getOperand(i: 1).getReg();
9620 Register InsertVal;
9621 if (MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT)
9622 InsertVal = MI.getOperand(i: 2).getReg();
9623
9624 Register Idx = MI.getOperand(i: MI.getNumOperands() - 1).getReg();
9625
9626 LLT VecTy = MRI.getType(Reg: SrcVec);
9627 LLT EltTy = VecTy.getElementType();
9628 unsigned NumElts = VecTy.getNumElements();
9629
9630 int64_t IdxVal;
9631 if (mi_match(R: Idx, MRI, P: m_ICst(Cst&: IdxVal)) && IdxVal <= NumElts) {
9632 SmallVector<Register, 8> SrcRegs;
9633 extractParts(Reg: SrcVec, Ty: EltTy, NumParts: NumElts, VRegs&: SrcRegs, MIRBuilder, MRI);
9634
9635 if (InsertVal) {
9636 SrcRegs[IdxVal] = MI.getOperand(i: 2).getReg();
9637 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: SrcRegs);
9638 } else {
9639 MIRBuilder.buildCopy(Res: DstReg, Op: SrcRegs[IdxVal]);
9640 }
9641
9642 MI.eraseFromParent();
9643 return Legalized;
9644 }
9645
9646 if (!EltTy.isByteSized()) { // Not implemented.
9647 LLVM_DEBUG(dbgs() << "Can't handle non-byte element vectors yet\n");
9648 return UnableToLegalize;
9649 }
9650
9651 unsigned EltBytes = EltTy.getSizeInBytes();
9652 Align VecAlign = getStackTemporaryAlignment(Ty: VecTy);
9653 Align EltAlign;
9654
9655 MachinePointerInfo PtrInfo;
9656 auto StackTemp = createStackTemporary(
9657 Bytes: TypeSize::getFixed(ExactSize: VecTy.getSizeInBytes()), Alignment: VecAlign, PtrInfo);
9658 MIRBuilder.buildStore(Val: SrcVec, Addr: StackTemp, PtrInfo, Alignment: VecAlign);
9659
9660 // Get the pointer to the element, and be sure not to hit undefined behavior
9661 // if the index is out of bounds.
9662 Register EltPtr = getVectorElementPointer(VecPtr: StackTemp.getReg(Idx: 0), VecTy, Index: Idx);
9663
9664 if (mi_match(R: Idx, MRI, P: m_ICst(Cst&: IdxVal))) {
9665 int64_t Offset = IdxVal * EltBytes;
9666 PtrInfo = PtrInfo.getWithOffset(O: Offset);
9667 EltAlign = commonAlignment(A: VecAlign, Offset);
9668 } else {
9669 // We lose information with a variable offset.
9670 EltAlign = getStackTemporaryAlignment(Ty: EltTy);
9671 PtrInfo = MachinePointerInfo(MRI.getType(Reg: EltPtr).getAddressSpace());
9672 }
9673
9674 if (InsertVal) {
9675 // Write the inserted element
9676 MIRBuilder.buildStore(Val: InsertVal, Addr: EltPtr, PtrInfo, Alignment: EltAlign);
9677
9678 // Reload the whole vector.
9679 MIRBuilder.buildLoad(Res: DstReg, Addr: StackTemp, PtrInfo, Alignment: VecAlign);
9680 } else {
9681 MIRBuilder.buildLoad(Res: DstReg, Addr: EltPtr, PtrInfo, Alignment: EltAlign);
9682 }
9683
9684 MI.eraseFromParent();
9685 return Legalized;
9686}
9687
9688LegalizerHelper::LegalizeResult
9689LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
9690 auto [DstReg, DstTy, Src0Reg, Src0Ty, Src1Reg, Src1Ty] =
9691 MI.getFirst3RegLLTs();
9692 LLT IdxTy = LLT::scalar(SizeInBits: 32);
9693
9694 ArrayRef<int> Mask = MI.getOperand(i: 3).getShuffleMask();
9695 Register Undef;
9696 SmallVector<Register, 32> BuildVec;
9697 LLT EltTy = DstTy.getScalarType();
9698
9699 DenseMap<unsigned, Register> CachedExtract;
9700
9701 for (int Idx : Mask) {
9702 if (Idx < 0) {
9703 if (!Undef.isValid())
9704 Undef = MIRBuilder.buildUndef(Res: EltTy).getReg(Idx: 0);
9705 BuildVec.push_back(Elt: Undef);
9706 continue;
9707 }
9708
9709 assert(!Src0Ty.isScalar() && "Unexpected scalar G_SHUFFLE_VECTOR");
9710
9711 int NumElts = Src0Ty.getNumElements();
9712 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
9713 int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts;
9714 auto [It, Inserted] = CachedExtract.try_emplace(Key: Idx);
9715 if (Inserted) {
9716 auto IdxK = MIRBuilder.buildConstant(Res: IdxTy, Val: ExtractIdx);
9717 It->second =
9718 MIRBuilder.buildExtractVectorElement(Res: EltTy, Val: SrcVec, Idx: IdxK).getReg(Idx: 0);
9719 }
9720 BuildVec.push_back(Elt: It->second);
9721 }
9722
9723 assert(DstTy.isVector() && "Unexpected scalar G_SHUFFLE_VECTOR");
9724 MIRBuilder.buildBuildVector(Res: DstReg, Ops: BuildVec);
9725 MI.eraseFromParent();
9726 return Legalized;
9727}
9728
9729LegalizerHelper::LegalizeResult
9730LegalizerHelper::lowerVECTOR_COMPRESS(llvm::MachineInstr &MI) {
9731 auto [Dst, DstTy, Vec, VecTy, Mask, MaskTy, Passthru, PassthruTy] =
9732 MI.getFirst4RegLLTs();
9733
9734 if (VecTy.isScalableVector())
9735 report_fatal_error(reason: "Cannot expand masked_compress for scalable vectors.");
9736
9737 Align VecAlign = getStackTemporaryAlignment(Ty: VecTy);
9738 MachinePointerInfo PtrInfo;
9739 Register StackPtr =
9740 createStackTemporary(Bytes: TypeSize::getFixed(ExactSize: VecTy.getSizeInBytes()), Alignment: VecAlign,
9741 PtrInfo)
9742 .getReg(Idx: 0);
9743 MachinePointerInfo ValPtrInfo =
9744 MachinePointerInfo::getUnknownStack(MF&: *MI.getMF());
9745
9746 LLT IdxTy = LLT::integer(SizeInBits: 32);
9747 LLT ValTy = VecTy.getElementType();
9748 Align ValAlign = getStackTemporaryAlignment(Ty: ValTy);
9749
9750 auto OutPos = MIRBuilder.buildConstant(Res: IdxTy, Val: 0);
9751
9752 bool HasPassthru = !mi_match(R: Passthru, MRI, P: m_GImplicitDef());
9753
9754 if (HasPassthru)
9755 MIRBuilder.buildStore(Val: Passthru, Addr: StackPtr, PtrInfo, Alignment: VecAlign);
9756
9757 Register LastWriteVal;
9758 std::optional<APInt> PassthruSplatVal =
9759 isConstantOrConstantSplatVector(Def: Passthru, MRI);
9760
9761 if (PassthruSplatVal.has_value()) {
9762 LastWriteVal =
9763 MIRBuilder.buildConstant(Res: ValTy, Val: PassthruSplatVal.value()).getReg(Idx: 0);
9764 } else if (HasPassthru) {
9765 auto Popcount = MIRBuilder.buildZExt(Res: MaskTy.changeElementSize(NewEltSize: 32), Op: Mask);
9766 Popcount = MIRBuilder.buildInstr(Opc: TargetOpcode::G_VECREDUCE_ADD,
9767 DstOps: {LLT::integer(SizeInBits: 32)}, SrcOps: {Popcount});
9768
9769 Register LastElmtPtr =
9770 getVectorElementPointer(VecPtr: StackPtr, VecTy, Index: Popcount.getReg(Idx: 0));
9771 LastWriteVal =
9772 MIRBuilder.buildLoad(Res: ValTy, Addr: LastElmtPtr, PtrInfo: ValPtrInfo, Alignment: ValAlign)
9773 .getReg(Idx: 0);
9774 }
9775
9776 unsigned NumElmts = VecTy.getNumElements();
9777 for (unsigned I = 0; I < NumElmts; ++I) {
9778 auto Idx = MIRBuilder.buildConstant(Res: IdxTy, Val: I);
9779 auto Val = MIRBuilder.buildExtractVectorElement(Res: ValTy, Val: Vec, Idx);
9780 Register ElmtPtr =
9781 getVectorElementPointer(VecPtr: StackPtr, VecTy, Index: OutPos.getReg(Idx: 0));
9782 MIRBuilder.buildStore(Val, Addr: ElmtPtr, PtrInfo: ValPtrInfo, Alignment: ValAlign);
9783
9784 LLT MaskITy = MaskTy.getElementType();
9785 auto MaskI = MIRBuilder.buildExtractVectorElement(Res: MaskITy, Val: Mask, Idx);
9786 if (MaskITy.getSizeInBits() > 1)
9787 MaskI = MIRBuilder.buildTrunc(Res: LLT::integer(SizeInBits: 1), Op: MaskI);
9788
9789 MaskI = MIRBuilder.buildZExt(Res: IdxTy, Op: MaskI);
9790 OutPos = MIRBuilder.buildAdd(Dst: IdxTy, Src0: OutPos, Src1: MaskI);
9791
9792 if (HasPassthru && I == NumElmts - 1) {
9793 auto EndOfVector =
9794 MIRBuilder.buildConstant(Res: IdxTy, Val: VecTy.getNumElements() - 1);
9795 auto AllLanesSelected = MIRBuilder.buildICmp(
9796 Pred: CmpInst::ICMP_UGT, Res: LLT::integer(SizeInBits: 1), Op0: OutPos, Op1: EndOfVector);
9797 OutPos = MIRBuilder.buildInstr(Opc: TargetOpcode::G_UMIN, DstOps: {IdxTy},
9798 SrcOps: {OutPos, EndOfVector});
9799 ElmtPtr = getVectorElementPointer(VecPtr: StackPtr, VecTy, Index: OutPos.getReg(Idx: 0));
9800
9801 LastWriteVal =
9802 MIRBuilder.buildSelect(Res: ValTy, Tst: AllLanesSelected, Op0: Val, Op1: LastWriteVal)
9803 .getReg(Idx: 0);
9804 MIRBuilder.buildStore(Val: LastWriteVal, Addr: ElmtPtr, PtrInfo: ValPtrInfo, Alignment: ValAlign);
9805 }
9806 }
9807
9808 // TODO: Use StackPtr's FrameIndex alignment.
9809 MIRBuilder.buildLoad(Res: Dst, Addr: StackPtr, PtrInfo, Alignment: VecAlign);
9810
9811 MI.eraseFromParent();
9812 return Legalized;
9813}
9814
9815Register LegalizerHelper::getDynStackAllocTargetPtr(Register SPReg,
9816 Register AllocSize,
9817 Align Alignment,
9818 LLT PtrTy) {
9819 LLT IntPtrTy = LLT::integer(SizeInBits: PtrTy.getSizeInBits());
9820
9821 auto SPTmp = MIRBuilder.buildCopy(Res: PtrTy, Op: SPReg);
9822 SPTmp = MIRBuilder.buildCast(Dst: IntPtrTy, Src: SPTmp);
9823
9824 // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't
9825 // have to generate an extra instruction to negate the alloc and then use
9826 // G_PTR_ADD to add the negative offset.
9827 auto Alloc = MIRBuilder.buildSub(Dst: IntPtrTy, Src0: SPTmp, Src1: AllocSize);
9828 if (Alignment > Align(1)) {
9829 APInt AlignMask(IntPtrTy.getSizeInBits(), Alignment.value(), true);
9830 AlignMask.negate();
9831 auto AlignCst = MIRBuilder.buildConstant(Res: IntPtrTy, Val: AlignMask);
9832 Alloc = MIRBuilder.buildAnd(Dst: IntPtrTy, Src0: Alloc, Src1: AlignCst);
9833 }
9834
9835 return MIRBuilder.buildCast(Dst: PtrTy, Src: Alloc).getReg(Idx: 0);
9836}
9837
9838LegalizerHelper::LegalizeResult
9839LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) {
9840 const auto &MF = *MI.getMF();
9841 const auto &TFI = *MF.getSubtarget().getFrameLowering();
9842 if (TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp)
9843 return UnableToLegalize;
9844
9845 Register Dst = MI.getOperand(i: 0).getReg();
9846 Register AllocSize = MI.getOperand(i: 1).getReg();
9847 Align Alignment = assumeAligned(Value: MI.getOperand(i: 2).getImm());
9848
9849 LLT PtrTy = MRI.getType(Reg: Dst);
9850 Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
9851 Register SPTmp =
9852 getDynStackAllocTargetPtr(SPReg, AllocSize, Alignment, PtrTy);
9853
9854 MIRBuilder.buildCopy(Res: SPReg, Op: SPTmp);
9855 MIRBuilder.buildCopy(Res: Dst, Op: SPTmp);
9856
9857 MI.eraseFromParent();
9858 return Legalized;
9859}
9860
9861LegalizerHelper::LegalizeResult
9862LegalizerHelper::lowerStackSave(MachineInstr &MI) {
9863 Register StackPtr = TLI.getStackPointerRegisterToSaveRestore();
9864 if (!StackPtr)
9865 return UnableToLegalize;
9866
9867 MIRBuilder.buildCopy(Res: MI.getOperand(i: 0), Op: StackPtr);
9868 MI.eraseFromParent();
9869 return Legalized;
9870}
9871
9872LegalizerHelper::LegalizeResult
9873LegalizerHelper::lowerStackRestore(MachineInstr &MI) {
9874 Register StackPtr = TLI.getStackPointerRegisterToSaveRestore();
9875 if (!StackPtr)
9876 return UnableToLegalize;
9877
9878 MIRBuilder.buildCopy(Res: StackPtr, Op: MI.getOperand(i: 0));
9879 MI.eraseFromParent();
9880 return Legalized;
9881}
9882
9883LegalizerHelper::LegalizeResult
9884LegalizerHelper::lowerExtract(MachineInstr &MI) {
9885 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
9886 unsigned Offset = MI.getOperand(i: 2).getImm();
9887
9888 // Extract sub-vector or one element
9889 if (SrcTy.isVector()) {
9890 unsigned SrcEltSize = SrcTy.getElementType().getSizeInBits();
9891 unsigned DstSize = DstTy.getSizeInBits();
9892
9893 if ((Offset % SrcEltSize == 0) && (DstSize % SrcEltSize == 0) &&
9894 (Offset + DstSize <= SrcTy.getSizeInBits())) {
9895 // Unmerge and allow access to each Src element for the artifact combiner.
9896 auto Unmerge = MIRBuilder.buildUnmerge(Res: SrcTy.getElementType(), Op: SrcReg);
9897
9898 // Take element(s) we need to extract and copy it (merge them).
9899 SmallVector<Register, 8> SubVectorElts;
9900 for (unsigned Idx = Offset / SrcEltSize;
9901 Idx < (Offset + DstSize) / SrcEltSize; ++Idx) {
9902 SubVectorElts.push_back(Elt: Unmerge.getReg(Idx));
9903 }
9904 if (SubVectorElts.size() == 1)
9905 MIRBuilder.buildCopy(Res: DstReg, Op: SubVectorElts[0]);
9906 else
9907 MIRBuilder.buildMergeLikeInstr(Res: DstReg, Ops: SubVectorElts);
9908
9909 MI.eraseFromParent();
9910 return Legalized;
9911 }
9912 }
9913
9914 const DataLayout &DL = MIRBuilder.getDataLayout();
9915 if ((SrcTy.isPointer() &&
9916 DL.isNonIntegralAddressSpace(AddrSpace: SrcTy.getAddressSpace())) ||
9917 (DstTy.isPointer() &&
9918 DL.isNonIntegralAddressSpace(AddrSpace: DstTy.getAddressSpace()))) {
9919 LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n");
9920 return UnableToLegalize;
9921 }
9922
9923 if ((DstTy.isScalar() || DstTy.isPointer()) &&
9924 (SrcTy.isScalar() || SrcTy.isPointer() ||
9925 (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) {
9926 LLT SrcIntTy = SrcTy;
9927 if (!SrcTy.isScalar()) {
9928 SrcIntTy = LLT::integer(SizeInBits: SrcTy.getSizeInBits());
9929 SrcReg = MIRBuilder.buildCast(Dst: SrcIntTy, Src: SrcReg).getReg(Idx: 0);
9930 }
9931
9932 Register ResultReg = DstReg;
9933 if (DstTy.isPointer())
9934 ResultReg =
9935 MRI.createGenericVirtualRegister(Ty: LLT::integer(SizeInBits: DstTy.getSizeInBits()));
9936
9937 if (Offset == 0)
9938 MIRBuilder.buildTrunc(Res: ResultReg, Op: SrcReg);
9939 else {
9940 auto ShiftAmt = MIRBuilder.buildConstant(Res: SrcIntTy, Val: Offset);
9941 auto Shr = MIRBuilder.buildLShr(Dst: SrcIntTy, Src0: SrcReg, Src1: ShiftAmt);
9942 MIRBuilder.buildTrunc(Res: ResultReg, Op: Shr);
9943 }
9944
9945 if (DstTy.isPointer())
9946 MIRBuilder.buildIntToPtr(Dst: DstReg, Src: ResultReg);
9947
9948 MI.eraseFromParent();
9949 return Legalized;
9950 }
9951
9952 return UnableToLegalize;
9953}
9954
9955LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) {
9956 auto [Dst, Src, InsertSrc] = MI.getFirst3Regs();
9957 uint64_t Offset = MI.getOperand(i: 3).getImm();
9958
9959 LLT DstTy = MRI.getType(Reg: Src);
9960 LLT InsertTy = MRI.getType(Reg: InsertSrc);
9961
9962 const DataLayout &DL = MIRBuilder.getDataLayout();
9963 bool IsNonIntegralInsert =
9964 InsertTy.isPointerOrPointerVector() &&
9965 DL.isNonIntegralAddressSpace(AddrSpace: InsertTy.getAddressSpace());
9966 bool IsNonIntegralDst = DstTy.isPointerOrPointerVector() &&
9967 DL.isNonIntegralAddressSpace(AddrSpace: DstTy.getAddressSpace());
9968
9969 // Insert sub-vector or one element
9970 if (DstTy.isVector()) {
9971 LLT EltTy = DstTy.getElementType();
9972
9973 if ((IsNonIntegralInsert || IsNonIntegralDst) && InsertTy != EltTy) {
9974 LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n");
9975 return UnableToLegalize;
9976 }
9977
9978 unsigned EltSize = EltTy.getSizeInBits();
9979 unsigned InsertSize = InsertTy.getSizeInBits();
9980
9981 if ((Offset % EltSize == 0) && (InsertSize % EltSize == 0) &&
9982 (Offset + InsertSize <= DstTy.getSizeInBits())) {
9983 auto UnmergeSrc = MIRBuilder.buildUnmerge(Res: EltTy, Op: Src);
9984 SmallVector<Register, 8> DstElts;
9985 unsigned Idx = 0;
9986 // Elements from Src before insert start Offset
9987 for (; Idx < Offset / EltSize; ++Idx) {
9988 DstElts.push_back(Elt: UnmergeSrc.getReg(Idx));
9989 }
9990
9991 // Replace elements in Src with elements from InsertSrc
9992 if (InsertTy.getSizeInBits() > EltSize) {
9993 auto UnmergeInsertSrc = MIRBuilder.buildUnmerge(Res: EltTy, Op: InsertSrc);
9994 for (unsigned i = 0; Idx < (Offset + InsertSize) / EltSize;
9995 ++Idx, ++i) {
9996 DstElts.push_back(Elt: UnmergeInsertSrc.getReg(Idx: i));
9997 }
9998 } else {
9999 if (InsertTy.isPointer() && !EltTy.isPointer())
10000 InsertSrc = MIRBuilder.buildPtrToInt(Dst: EltTy, Src: InsertSrc).getReg(Idx: 0);
10001 else if (!InsertTy.isPointer() && EltTy.isPointer())
10002 InsertSrc = MIRBuilder.buildIntToPtr(Dst: EltTy, Src: InsertSrc).getReg(Idx: 0);
10003 DstElts.push_back(Elt: InsertSrc);
10004 ++Idx;
10005 }
10006
10007 // Remaining elements from Src after insert
10008 for (; Idx < DstTy.getNumElements(); ++Idx) {
10009 DstElts.push_back(Elt: UnmergeSrc.getReg(Idx));
10010 }
10011
10012 MIRBuilder.buildMergeLikeInstr(Res: Dst, Ops: DstElts);
10013 MI.eraseFromParent();
10014 return Legalized;
10015 }
10016 }
10017
10018 if (InsertTy.isVector() ||
10019 (DstTy.isVector() && DstTy.getElementType() != InsertTy))
10020 return UnableToLegalize;
10021
10022 if (IsNonIntegralDst || IsNonIntegralInsert) {
10023 LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n");
10024 return UnableToLegalize;
10025 }
10026
10027 LLT IntDstTy = DstTy;
10028
10029 if (!DstTy.isScalar()) {
10030 IntDstTy = LLT::scalar(SizeInBits: DstTy.getSizeInBits());
10031 Src = MIRBuilder.buildCast(Dst: IntDstTy, Src).getReg(Idx: 0);
10032 }
10033
10034 if (!InsertTy.isScalar()) {
10035 const LLT IntInsertTy = LLT::scalar(SizeInBits: InsertTy.getSizeInBits());
10036 InsertSrc = MIRBuilder.buildPtrToInt(Dst: IntInsertTy, Src: InsertSrc).getReg(Idx: 0);
10037 }
10038
10039 Register ExtInsSrc = MIRBuilder.buildZExt(Res: IntDstTy, Op: InsertSrc).getReg(Idx: 0);
10040 if (Offset != 0) {
10041 auto ShiftAmt = MIRBuilder.buildConstant(Res: IntDstTy, Val: Offset);
10042 ExtInsSrc = MIRBuilder.buildShl(Dst: IntDstTy, Src0: ExtInsSrc, Src1: ShiftAmt).getReg(Idx: 0);
10043 }
10044
10045 APInt MaskVal = APInt::getBitsSetWithWrap(
10046 numBits: DstTy.getSizeInBits(), loBit: Offset + InsertTy.getSizeInBits(), hiBit: Offset);
10047
10048 auto Mask = MIRBuilder.buildConstant(Res: IntDstTy, Val: MaskVal);
10049 auto MaskedSrc = MIRBuilder.buildAnd(Dst: IntDstTy, Src0: Src, Src1: Mask);
10050 auto Or = MIRBuilder.buildOr(Dst: IntDstTy, Src0: MaskedSrc, Src1: ExtInsSrc);
10051
10052 MIRBuilder.buildCast(Dst, Src: Or);
10053 MI.eraseFromParent();
10054 return Legalized;
10055}
10056
10057LegalizerHelper::LegalizeResult
10058LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) {
10059 auto [Dst0, Dst0Ty, Dst1, Dst1Ty, LHS, LHSTy, RHS, RHSTy] =
10060 MI.getFirst4RegLLTs();
10061 const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO;
10062
10063 LLT Ty = Dst0Ty;
10064 LLT BoolTy = Dst1Ty;
10065
10066 Register NewDst0 = MRI.cloneVirtualRegister(VReg: Dst0);
10067
10068 if (IsAdd)
10069 MIRBuilder.buildAdd(Dst: NewDst0, Src0: LHS, Src1: RHS);
10070 else
10071 MIRBuilder.buildSub(Dst: NewDst0, Src0: LHS, Src1: RHS);
10072
10073 // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow.
10074
10075 auto Zero = MIRBuilder.buildConstant(Res: Ty, Val: 0);
10076
10077 if (IsAdd) {
10078 // For an addition, the result should be less than one of the operands (LHS)
10079 // if and only if the other operand (RHS) is negative, otherwise there will
10080 // be overflow.
10081 auto ResultLowerThanLHS =
10082 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_SLT, Res: BoolTy, Op0: NewDst0, Op1: LHS);
10083 auto RHSNegative =
10084 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_SLT, Res: BoolTy, Op0: RHS, Op1: Zero);
10085 MIRBuilder.buildXor(Dst: Dst1, Src0: RHSNegative, Src1: ResultLowerThanLHS);
10086 } else {
10087 // For subtraction, overflow occurs when the signed comparison of operands
10088 // doesn't match the sign of the result.
10089 auto LHSLessThanRHS =
10090 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_SLT, Res: BoolTy, Op0: LHS, Op1: RHS);
10091 auto ResultNegative =
10092 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_SLT, Res: BoolTy, Op0: NewDst0, Op1: Zero);
10093 MIRBuilder.buildXor(Dst: Dst1, Src0: LHSLessThanRHS, Src1: ResultNegative);
10094 }
10095
10096 MIRBuilder.buildCopy(Res: Dst0, Op: NewDst0);
10097 MI.eraseFromParent();
10098
10099 return Legalized;
10100}
10101
10102LegalizerHelper::LegalizeResult LegalizerHelper::lowerSADDE(MachineInstr &MI) {
10103 auto [Res, OvOut, LHS, RHS, CarryIn] = MI.getFirst5Regs();
10104 const LLT Ty = MRI.getType(Reg: Res);
10105
10106 // sum = LHS + RHS + zext(CarryIn)
10107 auto Tmp = MIRBuilder.buildAdd(Dst: Ty, Src0: LHS, Src1: RHS);
10108 auto CarryZ = MIRBuilder.buildZExt(Res: Ty, Op: CarryIn);
10109 auto Sum = MIRBuilder.buildAdd(Dst: Ty, Src0: Tmp, Src1: CarryZ);
10110 MIRBuilder.buildCopy(Res, Op: Sum);
10111
10112 // OvOut = icmp slt ((sum ^ lhs) & (sum ^ rhs)), 0
10113 auto AX = MIRBuilder.buildXor(Dst: Ty, Src0: Sum, Src1: LHS);
10114 auto BX = MIRBuilder.buildXor(Dst: Ty, Src0: Sum, Src1: RHS);
10115 auto T = MIRBuilder.buildAnd(Dst: Ty, Src0: AX, Src1: BX);
10116
10117 auto Zero = MIRBuilder.buildConstant(Res: Ty, Val: 0);
10118 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_SLT, Res: OvOut, Op0: T, Op1: Zero);
10119
10120 MI.eraseFromParent();
10121 return Legalized;
10122}
10123
10124LegalizerHelper::LegalizeResult LegalizerHelper::lowerSSUBE(MachineInstr &MI) {
10125 auto [Res, OvOut, LHS, RHS, CarryIn] = MI.getFirst5Regs();
10126 const LLT Ty = MRI.getType(Reg: Res);
10127
10128 // Diff = LHS - (RHS + zext(CarryIn))
10129 auto CarryZ = MIRBuilder.buildZExt(Res: Ty, Op: CarryIn);
10130 auto RHSPlusCI = MIRBuilder.buildAdd(Dst: Ty, Src0: RHS, Src1: CarryZ);
10131 auto Diff = MIRBuilder.buildSub(Dst: Ty, Src0: LHS, Src1: RHSPlusCI);
10132 MIRBuilder.buildCopy(Res, Op: Diff);
10133
10134 // ov = msb((LHS ^ RHS) & (LHS ^ Diff))
10135 auto X1 = MIRBuilder.buildXor(Dst: Ty, Src0: LHS, Src1: RHS);
10136 auto X2 = MIRBuilder.buildXor(Dst: Ty, Src0: LHS, Src1: Diff);
10137 auto T = MIRBuilder.buildAnd(Dst: Ty, Src0: X1, Src1: X2);
10138 auto Zero = MIRBuilder.buildConstant(Res: Ty, Val: 0);
10139 MIRBuilder.buildICmp(Pred: CmpInst::ICMP_SLT, Res: OvOut, Op0: T, Op1: Zero);
10140
10141 MI.eraseFromParent();
10142 return Legalized;
10143}
10144
10145LegalizerHelper::LegalizeResult
10146LegalizerHelper::lowerAddSubSatToMinMax(MachineInstr &MI) {
10147 auto [Res, LHS, RHS] = MI.getFirst3Regs();
10148 LLT Ty = MRI.getType(Reg: Res);
10149 bool IsSigned;
10150 bool IsAdd;
10151 unsigned BaseOp;
10152 switch (MI.getOpcode()) {
10153 default:
10154 llvm_unreachable("unexpected addsat/subsat opcode");
10155 case TargetOpcode::G_UADDSAT:
10156 IsSigned = false;
10157 IsAdd = true;
10158 BaseOp = TargetOpcode::G_ADD;
10159 break;
10160 case TargetOpcode::G_SADDSAT:
10161 IsSigned = true;
10162 IsAdd = true;
10163 BaseOp = TargetOpcode::G_ADD;
10164 break;
10165 case TargetOpcode::G_USUBSAT:
10166 IsSigned = false;
10167 IsAdd = false;
10168 BaseOp = TargetOpcode::G_SUB;
10169 break;
10170 case TargetOpcode::G_SSUBSAT:
10171 IsSigned = true;
10172 IsAdd = false;
10173 BaseOp = TargetOpcode::G_SUB;
10174 break;
10175 }
10176
10177 if (IsSigned) {
10178 // sadd.sat(a, b) ->
10179 // hi = 0x7fffffff - smax(a, 0)
10180 // lo = 0x80000000 - smin(a, 0)
10181 // a + smin(smax(lo, b), hi)
10182 // ssub.sat(a, b) ->
10183 // lo = smax(a, -1) - 0x7fffffff
10184 // hi = smin(a, -1) - 0x80000000
10185 // a - smin(smax(lo, b), hi)
10186 // TODO: AMDGPU can use a "median of 3" instruction here:
10187 // a +/- med3(lo, b, hi)
10188 uint64_t NumBits = Ty.getScalarSizeInBits();
10189 auto MaxVal =
10190 MIRBuilder.buildConstant(Res: Ty, Val: APInt::getSignedMaxValue(numBits: NumBits));
10191 auto MinVal =
10192 MIRBuilder.buildConstant(Res: Ty, Val: APInt::getSignedMinValue(numBits: NumBits));
10193 MachineInstrBuilder Hi, Lo;
10194 if (IsAdd) {
10195 auto Zero = MIRBuilder.buildConstant(Res: Ty, Val: 0);
10196 Hi = MIRBuilder.buildSub(Dst: Ty, Src0: MaxVal, Src1: MIRBuilder.buildSMax(Dst: Ty, Src0: LHS, Src1: Zero));
10197 Lo = MIRBuilder.buildSub(Dst: Ty, Src0: MinVal, Src1: MIRBuilder.buildSMin(Dst: Ty, Src0: LHS, Src1: Zero));
10198 } else {
10199 auto NegOne = MIRBuilder.buildConstant(Res: Ty, Val: -1);
10200 Lo = MIRBuilder.buildSub(Dst: Ty, Src0: MIRBuilder.buildSMax(Dst: Ty, Src0: LHS, Src1: NegOne),
10201 Src1: MaxVal);
10202 Hi = MIRBuilder.buildSub(Dst: Ty, Src0: MIRBuilder.buildSMin(Dst: Ty, Src0: LHS, Src1: NegOne),
10203 Src1: MinVal);
10204 }
10205 auto RHSClamped =
10206 MIRBuilder.buildSMin(Dst: Ty, Src0: MIRBuilder.buildSMax(Dst: Ty, Src0: Lo, Src1: RHS), Src1: Hi);
10207 MIRBuilder.buildInstr(Opc: BaseOp, DstOps: {Res}, SrcOps: {LHS, RHSClamped});
10208 } else {
10209 // uadd.sat(a, b) -> a + umin(~a, b)
10210 // usub.sat(a, b) -> a - umin(a, b)
10211 Register Not = IsAdd ? MIRBuilder.buildNot(Dst: Ty, Src0: LHS).getReg(Idx: 0) : LHS;
10212 auto Min = MIRBuilder.buildUMin(Dst: Ty, Src0: Not, Src1: RHS);
10213 MIRBuilder.buildInstr(Opc: BaseOp, DstOps: {Res}, SrcOps: {LHS, Min});
10214 }
10215
10216 MI.eraseFromParent();
10217 return Legalized;
10218}
10219
10220LegalizerHelper::LegalizeResult
10221LegalizerHelper::lowerAddSubSatToAddoSubo(MachineInstr &MI) {
10222 auto [Res, LHS, RHS] = MI.getFirst3Regs();
10223 LLT Ty = MRI.getType(Reg: Res);
10224 LLT BoolTy = Ty.changeElementSize(NewEltSize: 1);
10225 bool IsSigned;
10226 bool IsAdd;
10227 unsigned OverflowOp;
10228 switch (MI.getOpcode()) {
10229 default:
10230 llvm_unreachable("unexpected addsat/subsat opcode");
10231 case TargetOpcode::G_UADDSAT:
10232 IsSigned = false;
10233 IsAdd = true;
10234 OverflowOp = TargetOpcode::G_UADDO;
10235 break;
10236 case TargetOpcode::G_SADDSAT:
10237 IsSigned = true;
10238 IsAdd = true;
10239 OverflowOp = TargetOpcode::G_SADDO;
10240 break;
10241 case TargetOpcode::G_USUBSAT:
10242 IsSigned = false;
10243 IsAdd = false;
10244 OverflowOp = TargetOpcode::G_USUBO;
10245 break;
10246 case TargetOpcode::G_SSUBSAT:
10247 IsSigned = true;
10248 IsAdd = false;
10249 OverflowOp = TargetOpcode::G_SSUBO;
10250 break;
10251 }
10252
10253 auto OverflowRes =
10254 MIRBuilder.buildInstr(Opc: OverflowOp, DstOps: {Ty, BoolTy}, SrcOps: {LHS, RHS});
10255 Register Tmp = OverflowRes.getReg(Idx: 0);
10256 Register Ov = OverflowRes.getReg(Idx: 1);
10257 MachineInstrBuilder Clamp;
10258 if (IsSigned) {
10259 // sadd.sat(a, b) ->
10260 // {tmp, ov} = saddo(a, b)
10261 // ov ? (tmp >>s 31) + 0x80000000 : r
10262 // ssub.sat(a, b) ->
10263 // {tmp, ov} = ssubo(a, b)
10264 // ov ? (tmp >>s 31) + 0x80000000 : r
10265 uint64_t NumBits = Ty.getScalarSizeInBits();
10266 auto ShiftAmount = MIRBuilder.buildConstant(Res: Ty, Val: NumBits - 1);
10267 auto Sign = MIRBuilder.buildAShr(Dst: Ty, Src0: Tmp, Src1: ShiftAmount);
10268 auto MinVal =
10269 MIRBuilder.buildConstant(Res: Ty, Val: APInt::getSignedMinValue(numBits: NumBits));
10270 Clamp = MIRBuilder.buildAdd(Dst: Ty, Src0: Sign, Src1: MinVal);
10271 } else {
10272 // uadd.sat(a, b) ->
10273 // {tmp, ov} = uaddo(a, b)
10274 // ov ? 0xffffffff : tmp
10275 // usub.sat(a, b) ->
10276 // {tmp, ov} = usubo(a, b)
10277 // ov ? 0 : tmp
10278 Clamp = MIRBuilder.buildConstant(Res: Ty, Val: IsAdd ? -1 : 0);
10279 }
10280 MIRBuilder.buildSelect(Res, Tst: Ov, Op0: Clamp, Op1: Tmp);
10281
10282 MI.eraseFromParent();
10283 return Legalized;
10284}
10285
10286LegalizerHelper::LegalizeResult
10287LegalizerHelper::lowerShlSat(MachineInstr &MI) {
10288 assert((MI.getOpcode() == TargetOpcode::G_SSHLSAT ||
10289 MI.getOpcode() == TargetOpcode::G_USHLSAT) &&
10290 "Expected shlsat opcode!");
10291 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SSHLSAT;
10292 auto [Res, LHS, RHS] = MI.getFirst3Regs();
10293 LLT Ty = MRI.getType(Reg: Res);
10294 LLT BoolTy = Ty.changeElementSize(NewEltSize: 1);
10295
10296 unsigned BW = Ty.getScalarSizeInBits();
10297 auto Result = MIRBuilder.buildShl(Dst: Ty, Src0: LHS, Src1: RHS);
10298 auto Orig = IsSigned ? MIRBuilder.buildAShr(Dst: Ty, Src0: Result, Src1: RHS)
10299 : MIRBuilder.buildLShr(Dst: Ty, Src0: Result, Src1: RHS);
10300
10301 MachineInstrBuilder SatVal;
10302 if (IsSigned) {
10303 auto SatMin = MIRBuilder.buildConstant(Res: Ty, Val: APInt::getSignedMinValue(numBits: BW));
10304 auto SatMax = MIRBuilder.buildConstant(Res: Ty, Val: APInt::getSignedMaxValue(numBits: BW));
10305 auto Cmp = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_SLT, Res: BoolTy, Op0: LHS,
10306 Op1: MIRBuilder.buildConstant(Res: Ty, Val: 0));
10307 SatVal = MIRBuilder.buildSelect(Res: Ty, Tst: Cmp, Op0: SatMin, Op1: SatMax);
10308 } else {
10309 SatVal = MIRBuilder.buildConstant(Res: Ty, Val: APInt::getMaxValue(numBits: BW));
10310 }
10311 auto Ov = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_NE, Res: BoolTy, Op0: LHS, Op1: Orig);
10312 MIRBuilder.buildSelect(Res, Tst: Ov, Op0: SatVal, Op1: Result);
10313
10314 MI.eraseFromParent();
10315 return Legalized;
10316}
10317
10318LegalizerHelper::LegalizeResult
10319LegalizerHelper::lowerTruncSat(MachineInstr &MI) {
10320 unsigned Opc = MI.getOpcode();
10321 auto [Dst, DstTy, Src, SrcTy] = MI.getFirst2RegLLTs();
10322 unsigned DstSize = DstTy.getScalarSizeInBits();
10323 unsigned SrcSize = SrcTy.getScalarSizeInBits();
10324
10325 if (Opc == TargetOpcode::G_TRUNC_SSAT_S) {
10326 auto Max = MIRBuilder.buildConstant(
10327 Res: SrcTy, Val: APInt::getSignedMaxValue(numBits: DstSize).sext(width: SrcSize));
10328 Src = MIRBuilder.buildSMin(Dst: SrcTy, Src0: Src, Src1: Max).getReg(Idx: 0);
10329 auto Min = MIRBuilder.buildConstant(
10330 Res: SrcTy, Val: APInt::getSignedMinValue(numBits: DstSize).sext(width: SrcSize));
10331 Src = MIRBuilder.buildSMax(Dst: SrcTy, Src0: Src, Src1: Min).getReg(Idx: 0);
10332 } else if (Opc == TargetOpcode::G_TRUNC_USAT_U) {
10333 auto Max = MIRBuilder.buildConstant(
10334 Res: SrcTy, Val: APInt::getAllOnes(numBits: DstSize).zext(width: SrcSize));
10335 Src = MIRBuilder.buildUMin(Dst: SrcTy, Src0: Src, Src1: Max).getReg(Idx: 0);
10336 } else if (Opc == TargetOpcode::G_TRUNC_SSAT_U) {
10337 auto Max = MIRBuilder.buildConstant(
10338 Res: SrcTy, Val: APInt::getAllOnes(numBits: DstSize).zext(width: SrcSize));
10339 Src = MIRBuilder.buildSMin(Dst: SrcTy, Src0: Src, Src1: Max).getReg(Idx: 0);
10340 auto Min = MIRBuilder.buildConstant(Res: SrcTy, Val: APInt::getZero(numBits: SrcSize));
10341 Src = MIRBuilder.buildSMax(Dst: SrcTy, Src0: Src, Src1: Min).getReg(Idx: 0);
10342 } else {
10343 llvm_unreachable("Expected truncsat opcode!");
10344 }
10345
10346 MIRBuilder.buildTrunc(Res: Dst, Op: Src);
10347 MI.eraseFromParent();
10348 return Legalized;
10349}
10350
10351LegalizerHelper::LegalizeResult LegalizerHelper::lowerBswap(MachineInstr &MI) {
10352 auto [Dst, Src] = MI.getFirst2Regs();
10353 const LLT Ty = MRI.getType(Reg: Src);
10354 unsigned SizeInBytes = (Ty.getScalarSizeInBits() + 7) / 8;
10355 unsigned BaseShiftAmt = (SizeInBytes - 1) * 8;
10356
10357 // Swap most and least significant byte, set remaining bytes in Res to zero.
10358 auto ShiftAmt = MIRBuilder.buildConstant(Res: Ty, Val: BaseShiftAmt);
10359 auto LSByteShiftedLeft = MIRBuilder.buildShl(Dst: Ty, Src0: Src, Src1: ShiftAmt);
10360 auto MSByteShiftedRight = MIRBuilder.buildLShr(Dst: Ty, Src0: Src, Src1: ShiftAmt);
10361 auto Res = MIRBuilder.buildOr(Dst: Ty, Src0: MSByteShiftedRight, Src1: LSByteShiftedLeft);
10362
10363 // Set i-th high/low byte in Res to i-th low/high byte from Src.
10364 for (unsigned i = 1; i < SizeInBytes / 2; ++i) {
10365 // AND with Mask leaves byte i unchanged and sets remaining bytes to 0.
10366 APInt APMask = APInt::getBitsSet(numBits: SizeInBytes * 8, loBit: i * 8, hiBit: i * 8 + 8);
10367 auto Mask = MIRBuilder.buildConstant(Res: Ty, Val: APMask);
10368 auto ShiftAmt = MIRBuilder.buildConstant(Res: Ty, Val: BaseShiftAmt - 16 * i);
10369 // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt.
10370 auto LoByte = MIRBuilder.buildAnd(Dst: Ty, Src0: Src, Src1: Mask);
10371 auto LoShiftedLeft = MIRBuilder.buildShl(Dst: Ty, Src0: LoByte, Src1: ShiftAmt);
10372 Res = MIRBuilder.buildOr(Dst: Ty, Src0: Res, Src1: LoShiftedLeft);
10373 // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask.
10374 auto SrcShiftedRight = MIRBuilder.buildLShr(Dst: Ty, Src0: Src, Src1: ShiftAmt);
10375 auto HiShiftedRight = MIRBuilder.buildAnd(Dst: Ty, Src0: SrcShiftedRight, Src1: Mask);
10376 Res = MIRBuilder.buildOr(Dst: Ty, Src0: Res, Src1: HiShiftedRight);
10377 }
10378 Res.getInstr()->getOperand(i: 0).setReg(Dst);
10379
10380 MI.eraseFromParent();
10381 return Legalized;
10382}
10383
10384//{ (Src & Mask) >> N } | { (Src << N) & Mask }
10385static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B,
10386 MachineInstrBuilder Src, const APInt &Mask) {
10387 const LLT Ty = Dst.getLLTTy(MRI: *B.getMRI());
10388 MachineInstrBuilder C_N = B.buildConstant(Res: Ty, Val: N);
10389 MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Res: Ty, Val: Mask);
10390 auto LHS = B.buildLShr(Dst: Ty, Src0: B.buildAnd(Dst: Ty, Src0: Src, Src1: MaskLoNTo0), Src1: C_N);
10391 auto RHS = B.buildAnd(Dst: Ty, Src0: B.buildShl(Dst: Ty, Src0: Src, Src1: C_N), Src1: MaskLoNTo0);
10392 return B.buildOr(Dst, Src0: LHS, Src1: RHS);
10393}
10394
10395LegalizerHelper::LegalizeResult
10396LegalizerHelper::lowerBitreverse(MachineInstr &MI) {
10397 auto [Dst, Src] = MI.getFirst2Regs();
10398 const LLT SrcTy = MRI.getType(Reg: Src);
10399 unsigned Size = SrcTy.getScalarSizeInBits();
10400 unsigned VSize = SrcTy.getSizeInBits();
10401
10402 if (Size >= 8) {
10403 if (SrcTy.isVector() && (VSize % 8 == 0) &&
10404 (LI.isLegal(Query: {TargetOpcode::G_BITREVERSE,
10405 {LLT::fixed_vector(NumElements: VSize / 8, ScalarTy: LLT::integer(SizeInBits: 8)),
10406 LLT::fixed_vector(NumElements: VSize / 8, ScalarTy: LLT::integer(SizeInBits: 8))}}))) {
10407 // If bitreverse is legal for i8 vector of the same size, then cast
10408 // to i8 vector type.
10409 // e.g. v4s32 -> v16s8
10410 LLT VTy = LLT::fixed_vector(NumElements: VSize / 8, ScalarTy: LLT::integer(SizeInBits: 8));
10411 auto BSWAP = MIRBuilder.buildBSwap(Dst: SrcTy, Src0: Src);
10412 auto Cast = MIRBuilder.buildBitcast(Dst: VTy, Src: BSWAP);
10413 auto RBIT = MIRBuilder.buildBitReverse(Dst: VTy, Src: Cast);
10414 MIRBuilder.buildBitcast(Dst, Src: RBIT);
10415 } else {
10416 MachineInstrBuilder BSWAP =
10417 MIRBuilder.buildInstr(Opc: TargetOpcode::G_BSWAP, DstOps: {SrcTy}, SrcOps: {Src});
10418
10419 // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654
10420 // [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4]
10421 // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0]
10422 MachineInstrBuilder Swap4 = SwapN(N: 4, Dst: SrcTy, B&: MIRBuilder, Src: BSWAP,
10423 Mask: APInt::getSplat(NewLen: Size, V: APInt(8, 0xF0)));
10424
10425 // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76
10426 // [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2]
10427 // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC]
10428 MachineInstrBuilder Swap2 = SwapN(N: 2, Dst: SrcTy, B&: MIRBuilder, Src: Swap4,
10429 Mask: APInt::getSplat(NewLen: Size, V: APInt(8, 0xCC)));
10430
10431 // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5
10432 // 6|7
10433 // [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1]
10434 // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA]
10435 SwapN(N: 1, Dst, B&: MIRBuilder, Src: Swap2, Mask: APInt::getSplat(NewLen: Size, V: APInt(8, 0xAA)));
10436 }
10437 } else {
10438 // Expand bitreverse for types smaller than 8 bits.
10439 MachineInstrBuilder Tmp;
10440 for (unsigned I = 0, J = Size - 1; I < Size; ++I, --J) {
10441 MachineInstrBuilder Tmp2;
10442 if (I < J) {
10443 auto ShAmt = MIRBuilder.buildConstant(Res: SrcTy, Val: J - I);
10444 Tmp2 = MIRBuilder.buildShl(Dst: SrcTy, Src0: Src, Src1: ShAmt);
10445 } else {
10446 auto ShAmt = MIRBuilder.buildConstant(Res: SrcTy, Val: I - J);
10447 Tmp2 = MIRBuilder.buildLShr(Dst: SrcTy, Src0: Src, Src1: ShAmt);
10448 }
10449
10450 auto Mask = MIRBuilder.buildConstant(Res: SrcTy, Val: 1ULL << J);
10451 Tmp2 = MIRBuilder.buildAnd(Dst: SrcTy, Src0: Tmp2, Src1: Mask);
10452 if (I == 0)
10453 Tmp = Tmp2;
10454 else
10455 Tmp = MIRBuilder.buildOr(Dst: SrcTy, Src0: Tmp, Src1: Tmp2);
10456 }
10457 MIRBuilder.buildCopy(Res: Dst, Op: Tmp);
10458 }
10459
10460 MI.eraseFromParent();
10461 return Legalized;
10462}
10463
10464LegalizerHelper::LegalizeResult
10465LegalizerHelper::lowerReadWriteRegister(MachineInstr &MI) {
10466 MachineFunction &MF = MIRBuilder.getMF();
10467
10468 bool IsRead = MI.getOpcode() == TargetOpcode::G_READ_REGISTER;
10469 int NameOpIdx = IsRead ? 1 : 0;
10470 int ValRegIndex = IsRead ? 0 : 1;
10471
10472 Register ValReg = MI.getOperand(i: ValRegIndex).getReg();
10473 const LLT Ty = MRI.getType(Reg: ValReg);
10474 const MDString *RegStr = cast<MDString>(
10475 Val: cast<MDNode>(Val: MI.getOperand(i: NameOpIdx).getMetadata())->getOperand(I: 0));
10476
10477 Register PhysReg = TLI.getRegisterByName(RegName: RegStr->getString().data(), Ty, MF);
10478 if (!PhysReg) {
10479 const Function &Fn = MF.getFunction();
10480 Fn.getContext().diagnose(DI: DiagnosticInfoGenericWithLoc(
10481 "invalid register \"" + Twine(RegStr->getString().data()) + "\" for " +
10482 (IsRead ? "llvm.read_register" : "llvm.write_register"),
10483 Fn, MI.getDebugLoc()));
10484 if (IsRead)
10485 MIRBuilder.buildUndef(Res: ValReg);
10486
10487 MI.eraseFromParent();
10488 return Legalized;
10489 }
10490
10491 if (IsRead)
10492 MIRBuilder.buildCopy(Res: ValReg, Op: PhysReg);
10493 else
10494 MIRBuilder.buildCopy(Res: PhysReg, Op: ValReg);
10495
10496 MI.eraseFromParent();
10497 return Legalized;
10498}
10499
10500LegalizerHelper::LegalizeResult
10501LegalizerHelper::lowerSMULH_UMULH(MachineInstr &MI) {
10502 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULH;
10503 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
10504 Register Result = MI.getOperand(i: 0).getReg();
10505 LLT OrigTy = MRI.getType(Reg: Result);
10506 auto SizeInBits = OrigTy.getScalarSizeInBits();
10507 LLT WideTy = OrigTy.changeElementSize(NewEltSize: SizeInBits * 2);
10508
10509 auto LHS = MIRBuilder.buildInstr(Opc: ExtOp, DstOps: {WideTy}, SrcOps: {MI.getOperand(i: 1)});
10510 auto RHS = MIRBuilder.buildInstr(Opc: ExtOp, DstOps: {WideTy}, SrcOps: {MI.getOperand(i: 2)});
10511 auto Mul = MIRBuilder.buildMul(Dst: WideTy, Src0: LHS, Src1: RHS);
10512 unsigned ShiftOp = IsSigned ? TargetOpcode::G_ASHR : TargetOpcode::G_LSHR;
10513
10514 auto ShiftAmt = MIRBuilder.buildConstant(Res: WideTy, Val: SizeInBits);
10515 auto Shifted = MIRBuilder.buildInstr(Opc: ShiftOp, DstOps: {WideTy}, SrcOps: {Mul, ShiftAmt});
10516 MIRBuilder.buildTrunc(Res: Result, Op: Shifted);
10517
10518 MI.eraseFromParent();
10519 return Legalized;
10520}
10521
10522LegalizerHelper::LegalizeResult
10523LegalizerHelper::lowerISFPCLASS(MachineInstr &MI) {
10524 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
10525 FPClassTest Mask = static_cast<FPClassTest>(MI.getOperand(i: 2).getImm());
10526
10527 if (Mask == fcNone) {
10528 MIRBuilder.buildConstant(Res: DstReg, Val: 0);
10529 MI.eraseFromParent();
10530 return Legalized;
10531 }
10532 if (Mask == fcAllFlags) {
10533 MIRBuilder.buildConstant(Res: DstReg, Val: 1);
10534 MI.eraseFromParent();
10535 return Legalized;
10536 }
10537
10538 // TODO: Try inverting the test with getInvertedFPClassTest like the DAG
10539 // version
10540
10541 unsigned BitSize = SrcTy.getScalarSizeInBits();
10542 const fltSemantics &Semantics = getFltSemanticForLLT(Ty: SrcTy.getScalarType());
10543
10544 LLT IntTy = SrcTy.changeElementType(NewEltTy: LLT::integer(SizeInBits: BitSize));
10545 auto AsInt = SrcTy == IntTy ? MIRBuilder.buildCopy(Res: IntTy, Op: SrcReg)
10546 : MIRBuilder.buildBitcast(Dst: IntTy, Src: SrcReg);
10547
10548 // Various masks.
10549 APInt SignBit = APInt::getSignMask(BitWidth: BitSize);
10550 APInt ValueMask = APInt::getSignedMaxValue(numBits: BitSize); // All bits but sign.
10551 APInt Inf = APFloat::getInf(Sem: Semantics).bitcastToAPInt(); // Exp and int bit.
10552 APInt ExpMask = Inf;
10553 APInt AllOneMantissa = APFloat::getLargest(Sem: Semantics).bitcastToAPInt() & ~Inf;
10554 APInt QNaNBitMask =
10555 APInt::getOneBitSet(numBits: BitSize, BitNo: AllOneMantissa.getActiveBits() - 1);
10556 APInt InversionMask = APInt::getAllOnes(numBits: DstTy.getScalarSizeInBits());
10557
10558 auto SignBitC = MIRBuilder.buildConstant(Res: IntTy, Val: SignBit);
10559 auto ValueMaskC = MIRBuilder.buildConstant(Res: IntTy, Val: ValueMask);
10560 auto InfC = MIRBuilder.buildConstant(Res: IntTy, Val: Inf);
10561 auto ExpMaskC = MIRBuilder.buildConstant(Res: IntTy, Val: ExpMask);
10562 auto ZeroC = MIRBuilder.buildConstant(Res: IntTy, Val: 0);
10563
10564 auto Abs = MIRBuilder.buildAnd(Dst: IntTy, Src0: AsInt, Src1: ValueMaskC);
10565 auto Sign =
10566 MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_NE, Res: DstTy, Op0: AsInt, Op1: Abs);
10567
10568 auto Res = MIRBuilder.buildConstant(Res: DstTy, Val: 0);
10569 // Clang doesn't support capture of structured bindings:
10570 LLT DstTyCopy = DstTy;
10571 const auto appendToRes = [&](MachineInstrBuilder ToAppend) {
10572 Res = MIRBuilder.buildOr(Dst: DstTyCopy, Src0: Res, Src1: ToAppend);
10573 };
10574
10575 // Tests that involve more than one class should be processed first.
10576 if ((Mask & fcFinite) == fcFinite) {
10577 // finite(V) ==> abs(V) u< exp_mask
10578 appendToRes(MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_ULT, Res: DstTy, Op0: Abs,
10579 Op1: ExpMaskC));
10580 Mask &= ~fcFinite;
10581 } else if ((Mask & fcFinite) == fcPosFinite) {
10582 // finite(V) && V > 0 ==> V u< exp_mask
10583 appendToRes(MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_ULT, Res: DstTy, Op0: AsInt,
10584 Op1: ExpMaskC));
10585 Mask &= ~fcPosFinite;
10586 } else if ((Mask & fcFinite) == fcNegFinite) {
10587 // finite(V) && V < 0 ==> abs(V) u< exp_mask && signbit == 1
10588 auto Cmp = MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_ULT, Res: DstTy, Op0: Abs,
10589 Op1: ExpMaskC);
10590 auto And = MIRBuilder.buildAnd(Dst: DstTy, Src0: Cmp, Src1: Sign);
10591 appendToRes(And);
10592 Mask &= ~fcNegFinite;
10593 }
10594
10595 if (FPClassTest PartialCheck = Mask & (fcZero | fcSubnormal)) {
10596 // fcZero | fcSubnormal => test all exponent bits are 0
10597 // TODO: Handle sign bit specific cases
10598 // TODO: Handle inverted case
10599 if (PartialCheck == (fcZero | fcSubnormal)) {
10600 auto ExpBits = MIRBuilder.buildAnd(Dst: IntTy, Src0: AsInt, Src1: ExpMaskC);
10601 appendToRes(MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_EQ, Res: DstTy,
10602 Op0: ExpBits, Op1: ZeroC));
10603 Mask &= ~PartialCheck;
10604 }
10605 }
10606
10607 // Check for individual classes.
10608 if (FPClassTest PartialCheck = Mask & fcZero) {
10609 if (PartialCheck == fcPosZero)
10610 appendToRes(MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_EQ, Res: DstTy,
10611 Op0: AsInt, Op1: ZeroC));
10612 else if (PartialCheck == fcZero)
10613 appendToRes(
10614 MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_EQ, Res: DstTy, Op0: Abs, Op1: ZeroC));
10615 else // fcNegZero
10616 appendToRes(MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_EQ, Res: DstTy,
10617 Op0: AsInt, Op1: SignBitC));
10618 }
10619
10620 if (FPClassTest PartialCheck = Mask & fcSubnormal) {
10621 // issubnormal(V) ==> unsigned(abs(V) - 1) u< (all mantissa bits set)
10622 // issubnormal(V) && V>0 ==> unsigned(V - 1) u< (all mantissa bits set)
10623 auto V = (PartialCheck == fcPosSubnormal) ? AsInt : Abs;
10624 auto OneC = MIRBuilder.buildConstant(Res: IntTy, Val: 1);
10625 auto VMinusOne = MIRBuilder.buildSub(Dst: IntTy, Src0: V, Src1: OneC);
10626 auto SubnormalRes =
10627 MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_ULT, Res: DstTy, Op0: VMinusOne,
10628 Op1: MIRBuilder.buildConstant(Res: IntTy, Val: AllOneMantissa));
10629 if (PartialCheck == fcNegSubnormal)
10630 SubnormalRes = MIRBuilder.buildAnd(Dst: DstTy, Src0: SubnormalRes, Src1: Sign);
10631 appendToRes(SubnormalRes);
10632 }
10633
10634 if (FPClassTest PartialCheck = Mask & fcInf) {
10635 if (PartialCheck == fcPosInf)
10636 appendToRes(MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_EQ, Res: DstTy,
10637 Op0: AsInt, Op1: InfC));
10638 else if (PartialCheck == fcInf)
10639 appendToRes(
10640 MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_EQ, Res: DstTy, Op0: Abs, Op1: InfC));
10641 else { // fcNegInf
10642 APInt NegInf = APFloat::getInf(Sem: Semantics, Negative: true).bitcastToAPInt();
10643 auto NegInfC = MIRBuilder.buildConstant(Res: IntTy, Val: NegInf);
10644 appendToRes(MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_EQ, Res: DstTy,
10645 Op0: AsInt, Op1: NegInfC));
10646 }
10647 }
10648
10649 if (FPClassTest PartialCheck = Mask & fcNan) {
10650 auto InfWithQnanBitC = MIRBuilder.buildConstant(Res: IntTy, Val: Inf | QNaNBitMask);
10651 if (PartialCheck == fcNan) {
10652 // isnan(V) ==> abs(V) u> int(inf)
10653 appendToRes(
10654 MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_UGT, Res: DstTy, Op0: Abs, Op1: InfC));
10655 } else if (PartialCheck == fcQNan) {
10656 // isquiet(V) ==> abs(V) u>= (unsigned(Inf) | quiet_bit)
10657 appendToRes(MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_UGE, Res: DstTy, Op0: Abs,
10658 Op1: InfWithQnanBitC));
10659 } else { // fcSNan
10660 // issignaling(V) ==> abs(V) u> unsigned(Inf) &&
10661 // abs(V) u< (unsigned(Inf) | quiet_bit)
10662 auto IsNan =
10663 MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_UGT, Res: DstTy, Op0: Abs, Op1: InfC);
10664 auto IsNotQnan = MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_ULT, Res: DstTy,
10665 Op0: Abs, Op1: InfWithQnanBitC);
10666 appendToRes(MIRBuilder.buildAnd(Dst: DstTy, Src0: IsNan, Src1: IsNotQnan));
10667 }
10668 }
10669
10670 if (FPClassTest PartialCheck = Mask & fcNormal) {
10671 // isnormal(V) ==> (0 u< exp u< max_exp) ==> (unsigned(exp-1) u<
10672 // (max_exp-1))
10673 APInt ExpLSB = ExpMask & ~(ExpMask.shl(shiftAmt: 1));
10674 auto ExpMinusOne = MIRBuilder.buildSub(
10675 Dst: IntTy, Src0: Abs, Src1: MIRBuilder.buildConstant(Res: IntTy, Val: ExpLSB));
10676 APInt MaxExpMinusOne = ExpMask - ExpLSB;
10677 auto NormalRes =
10678 MIRBuilder.buildICmp(Pred: CmpInst::Predicate::ICMP_ULT, Res: DstTy, Op0: ExpMinusOne,
10679 Op1: MIRBuilder.buildConstant(Res: IntTy, Val: MaxExpMinusOne));
10680 if (PartialCheck == fcNegNormal)
10681 NormalRes = MIRBuilder.buildAnd(Dst: DstTy, Src0: NormalRes, Src1: Sign);
10682 else if (PartialCheck == fcPosNormal) {
10683 auto PosSign = MIRBuilder.buildXor(
10684 Dst: DstTy, Src0: Sign, Src1: MIRBuilder.buildConstant(Res: DstTy, Val: InversionMask));
10685 NormalRes = MIRBuilder.buildAnd(Dst: DstTy, Src0: NormalRes, Src1: PosSign);
10686 }
10687 appendToRes(NormalRes);
10688 }
10689
10690 MIRBuilder.buildCopy(Res: DstReg, Op: Res);
10691 MI.eraseFromParent();
10692 return Legalized;
10693}
10694
10695LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) {
10696 // Implement G_SELECT in terms of XOR, AND, OR.
10697 auto [DstReg, DstTy, MaskReg, MaskTy, Op1Reg, Op1Ty, Op2Reg, Op2Ty] =
10698 MI.getFirst4RegLLTs();
10699
10700 LLT Op1TyInt =
10701 Op1Ty.changeElementType(NewEltTy: LLT::integer(SizeInBits: Op1Ty.getScalarSizeInBits()));
10702
10703 bool IsEltPtr = DstTy.isPointerOrPointerVector();
10704 if (IsEltPtr) {
10705 LLT ScalarPtrTy = LLT::integer(SizeInBits: DstTy.getScalarSizeInBits());
10706 LLT NewTy = DstTy.changeElementType(NewEltTy: ScalarPtrTy);
10707 Op1Reg = MIRBuilder.buildPtrToInt(Dst: NewTy, Src: Op1Reg).getReg(Idx: 0);
10708 Op1Ty = MRI.getType(Reg: Op1Reg);
10709 Op2Reg = MIRBuilder.buildPtrToInt(Dst: NewTy, Src: Op2Reg).getReg(Idx: 0);
10710 Op2Ty = MRI.getType(Reg: Op2Reg);
10711 DstTy = NewTy;
10712 }
10713
10714 if (MaskTy.isScalar()) {
10715 // Turn the scalar condition into a vector condition mask if needed.
10716
10717 Register MaskElt = MaskReg;
10718
10719 // The condition was potentially zero extended before, but we want a sign
10720 // extended boolean.
10721 if (MaskTy != LLT::scalar(SizeInBits: 1))
10722 MaskElt = MIRBuilder.buildSExtInReg(Res: MaskTy, Op: MaskElt, ImmOp: 1).getReg(Idx: 0);
10723
10724 // Continue the sign extension (or truncate) to match the data type.
10725 MaskTy = DstTy.changeElementType(NewEltTy: LLT::integer(SizeInBits: DstTy.getScalarSizeInBits()));
10726 MaskElt =
10727 MIRBuilder.buildSExtOrTrunc(Res: MaskTy.getScalarType(), Op: MaskElt).getReg(Idx: 0);
10728
10729 if (DstTy.isVector()) {
10730 // Generate a vector splat idiom.
10731 auto ShufSplat = MIRBuilder.buildShuffleSplat(Res: MaskTy, Src: MaskElt);
10732 MaskReg = ShufSplat.getReg(Idx: 0);
10733 } else {
10734 MaskReg = MaskElt;
10735 }
10736 } else if (!DstTy.isVector()) {
10737 // Cannot handle the case that mask is a vector and dst is a scalar.
10738 return UnableToLegalize;
10739 }
10740
10741 if (MaskTy.getSizeInBits() != DstTy.getSizeInBits()) {
10742 return UnableToLegalize;
10743 }
10744
10745 if (!Op1Ty.getScalarType().isAnyScalar() &&
10746 !Op1Ty.getScalarType().isInteger())
10747 Op1Reg = MIRBuilder.buildBitcast(Dst: Op1TyInt, Src: Op1Reg).getReg(Idx: 0);
10748
10749 if (!Op2Ty.getScalarType().isAnyScalar() &&
10750 !Op2Ty.getScalarType().isInteger()) {
10751 auto Op2TyInt =
10752 Op2Ty.changeElementType(NewEltTy: LLT::integer(SizeInBits: Op2Ty.getScalarSizeInBits()));
10753 Op2Reg = MIRBuilder.buildBitcast(Dst: Op2TyInt, Src: Op2Reg).getReg(Idx: 0);
10754 }
10755
10756 auto NotMask = MIRBuilder.buildNot(Dst: MaskTy, Src0: MaskReg);
10757 auto NewOp1 = MIRBuilder.buildAnd(Dst: MaskTy, Src0: Op1Reg, Src1: MaskReg);
10758 auto NewOp2 = MIRBuilder.buildAnd(Dst: MaskTy, Src0: Op2Reg, Src1: NotMask);
10759 if (IsEltPtr) {
10760 auto Or = MIRBuilder.buildOr(Dst: DstTy, Src0: NewOp1, Src1: NewOp2);
10761 MIRBuilder.buildIntToPtr(Dst: DstReg, Src: Or);
10762 } else {
10763 if (DstTy == Op1TyInt)
10764 MIRBuilder.buildOr(Dst: DstReg, Src0: NewOp1, Src1: NewOp2);
10765 else {
10766 auto Or = MIRBuilder.buildOr(Dst: Op1TyInt, Src0: NewOp1, Src1: NewOp2);
10767 MIRBuilder.buildBitcast(Dst: DstReg, Src: Or.getReg(Idx: 0));
10768 }
10769 }
10770 MI.eraseFromParent();
10771 return Legalized;
10772}
10773
10774LegalizerHelper::LegalizeResult LegalizerHelper::lowerDIVREM(MachineInstr &MI) {
10775 // Split DIVREM into individual instructions.
10776 unsigned Opcode = MI.getOpcode();
10777
10778 MIRBuilder.buildInstr(
10779 Opc: Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SDIV
10780 : TargetOpcode::G_UDIV,
10781 DstOps: {MI.getOperand(i: 0).getReg()}, SrcOps: {MI.getOperand(i: 2), MI.getOperand(i: 3)});
10782 MIRBuilder.buildInstr(
10783 Opc: Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SREM
10784 : TargetOpcode::G_UREM,
10785 DstOps: {MI.getOperand(i: 1).getReg()}, SrcOps: {MI.getOperand(i: 2), MI.getOperand(i: 3)});
10786 MI.eraseFromParent();
10787 return Legalized;
10788}
10789
10790LegalizerHelper::LegalizeResult
10791LegalizerHelper::lowerAbsToAddXor(MachineInstr &MI) {
10792 // Expand %res = G_ABS %a into:
10793 // %v1 = G_ASHR %a, scalar_size-1
10794 // %v2 = G_ADD %a, %v1
10795 // %res = G_XOR %v2, %v1
10796 LLT DstTy = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
10797 Register OpReg = MI.getOperand(i: 1).getReg();
10798 auto ShiftAmt =
10799 MIRBuilder.buildConstant(Res: DstTy, Val: DstTy.getScalarSizeInBits() - 1);
10800 auto Shift = MIRBuilder.buildAShr(Dst: DstTy, Src0: OpReg, Src1: ShiftAmt);
10801 auto Add = MIRBuilder.buildAdd(Dst: DstTy, Src0: OpReg, Src1: Shift);
10802 MIRBuilder.buildXor(Dst: MI.getOperand(i: 0).getReg(), Src0: Add, Src1: Shift);
10803 MI.eraseFromParent();
10804 return Legalized;
10805}
10806
10807LegalizerHelper::LegalizeResult
10808LegalizerHelper::lowerAbsToMaxNeg(MachineInstr &MI) {
10809 // Expand %res = G_ABS %a into:
10810 // %v1 = G_CONSTANT 0
10811 // %v2 = G_SUB %v1, %a
10812 // %res = G_SMAX %a, %v2
10813 Register SrcReg = MI.getOperand(i: 1).getReg();
10814 LLT Ty = MRI.getType(Reg: SrcReg);
10815 auto Zero = MIRBuilder.buildConstant(Res: Ty, Val: 0);
10816 auto Sub = MIRBuilder.buildSub(Dst: Ty, Src0: Zero, Src1: SrcReg);
10817 MIRBuilder.buildSMax(Dst: MI.getOperand(i: 0), Src0: SrcReg, Src1: Sub);
10818 MI.eraseFromParent();
10819 return Legalized;
10820}
10821
10822LegalizerHelper::LegalizeResult
10823LegalizerHelper::lowerAbsToCNeg(MachineInstr &MI) {
10824 Register SrcReg = MI.getOperand(i: 1).getReg();
10825 Register DestReg = MI.getOperand(i: 0).getReg();
10826 LLT Ty = MRI.getType(Reg: SrcReg), IType = LLT::integer(SizeInBits: 1);
10827 auto Zero = MIRBuilder.buildConstant(Res: Ty, Val: 0).getReg(Idx: 0);
10828 auto Sub = MIRBuilder.buildSub(Dst: Ty, Src0: Zero, Src1: SrcReg).getReg(Idx: 0);
10829 auto ICmp = MIRBuilder.buildICmp(Pred: CmpInst::ICMP_SGT, Res: IType, Op0: SrcReg, Op1: Zero);
10830 MIRBuilder.buildSelect(Res: DestReg, Tst: ICmp, Op0: SrcReg, Op1: Sub);
10831 MI.eraseFromParent();
10832 return Legalized;
10833}
10834
10835LegalizerHelper::LegalizeResult
10836LegalizerHelper::lowerAbsDiffToSelect(MachineInstr &MI) {
10837 assert((MI.getOpcode() == TargetOpcode::G_ABDS ||
10838 MI.getOpcode() == TargetOpcode::G_ABDU) &&
10839 "Expected G_ABDS or G_ABDU instruction");
10840
10841 auto [DstReg, LHS, RHS] = MI.getFirst3Regs();
10842 LLT Ty = MRI.getType(Reg: LHS);
10843
10844 // abds(lhs, rhs) -> select(sgt(lhs,rhs), sub(lhs,rhs), sub(rhs,lhs))
10845 // abdu(lhs, rhs) -> select(ugt(lhs,rhs), sub(lhs,rhs), sub(rhs,lhs))
10846 Register LHSSub = MIRBuilder.buildSub(Dst: Ty, Src0: LHS, Src1: RHS).getReg(Idx: 0);
10847 Register RHSSub = MIRBuilder.buildSub(Dst: Ty, Src0: RHS, Src1: LHS).getReg(Idx: 0);
10848 CmpInst::Predicate Pred = (MI.getOpcode() == TargetOpcode::G_ABDS)
10849 ? CmpInst::ICMP_SGT
10850 : CmpInst::ICMP_UGT;
10851 auto ICmp = MIRBuilder.buildICmp(Pred, Res: LLT::scalar(SizeInBits: 1), Op0: LHS, Op1: RHS);
10852 MIRBuilder.buildSelect(Res: DstReg, Tst: ICmp, Op0: LHSSub, Op1: RHSSub);
10853
10854 MI.eraseFromParent();
10855 return Legalized;
10856}
10857
10858LegalizerHelper::LegalizeResult
10859LegalizerHelper::lowerAbsDiffToMinMax(MachineInstr &MI) {
10860 assert((MI.getOpcode() == TargetOpcode::G_ABDS ||
10861 MI.getOpcode() == TargetOpcode::G_ABDU) &&
10862 "Expected G_ABDS or G_ABDU instruction");
10863
10864 auto [DstReg, LHS, RHS] = MI.getFirst3Regs();
10865 LLT Ty = MRI.getType(Reg: LHS);
10866
10867 // abds(lhs, rhs) -→ sub(smax(lhs, rhs), smin(lhs, rhs))
10868 // abdu(lhs, rhs) -→ sub(umax(lhs, rhs), umin(lhs, rhs))
10869 Register MaxReg, MinReg;
10870 if (MI.getOpcode() == TargetOpcode::G_ABDS) {
10871 MaxReg = MIRBuilder.buildSMax(Dst: Ty, Src0: LHS, Src1: RHS).getReg(Idx: 0);
10872 MinReg = MIRBuilder.buildSMin(Dst: Ty, Src0: LHS, Src1: RHS).getReg(Idx: 0);
10873 } else {
10874 MaxReg = MIRBuilder.buildUMax(Dst: Ty, Src0: LHS, Src1: RHS).getReg(Idx: 0);
10875 MinReg = MIRBuilder.buildUMin(Dst: Ty, Src0: LHS, Src1: RHS).getReg(Idx: 0);
10876 }
10877 MIRBuilder.buildSub(Dst: DstReg, Src0: MaxReg, Src1: MinReg);
10878
10879 MI.eraseFromParent();
10880 return Legalized;
10881}
10882
10883LegalizerHelper::LegalizeResult LegalizerHelper::lowerFAbs(MachineInstr &MI) {
10884 auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
10885 LLT TyInt =
10886 DstTy.changeElementType(NewEltTy: LLT::integer(SizeInBits: DstTy.getScalarSizeInBits()));
10887 Register CastedSrc = SrcReg;
10888
10889 if (!(SrcTy.getScalarType().isAnyScalar() ||
10890 SrcTy.getScalarType().isInteger())) {
10891 auto SrcTyInt =
10892 SrcTy.changeElementType(NewEltTy: LLT::integer(SizeInBits: SrcTy.getScalarSizeInBits()));
10893 CastedSrc = MIRBuilder.buildBitcast(Dst: SrcTyInt, Src: SrcReg).getReg(Idx: 0);
10894 }
10895
10896 if (MRI.getType(Reg: DstReg) != TyInt) {
10897 // Reset sign bit
10898 Register NewDst =
10899 MIRBuilder
10900 .buildAnd(Dst: TyInt, Src0: CastedSrc,
10901 Src1: MIRBuilder.buildConstant(
10902 Res: TyInt, Val: APInt::getSignedMaxValue(
10903 numBits: DstTy.getScalarSizeInBits())))
10904 .getReg(Idx: 0);
10905
10906 MIRBuilder.buildBitcast(Dst: DstReg, Src: NewDst);
10907 } else
10908 MIRBuilder
10909 .buildAnd(
10910 Dst: DstReg, Src0: CastedSrc,
10911 Src1: MIRBuilder.buildConstant(
10912 Res: TyInt, Val: APInt::getSignedMaxValue(numBits: DstTy.getScalarSizeInBits())))
10913 .getReg(Idx: 0);
10914
10915 MI.eraseFromParent();
10916 return Legalized;
10917}
10918
10919LegalizerHelper::LegalizeResult
10920LegalizerHelper::lowerVectorReduction(MachineInstr &MI) {
10921 Register SrcReg = MI.getOperand(i: 1).getReg();
10922 LLT SrcTy = MRI.getType(Reg: SrcReg);
10923 LLT DstTy = MRI.getType(Reg: SrcReg);
10924
10925 // The source could be a scalar if the IR type was <1 x sN>.
10926 if (SrcTy.isScalar()) {
10927 if (DstTy.getSizeInBits() > SrcTy.getSizeInBits())
10928 return UnableToLegalize; // FIXME: handle extension.
10929 // This can be just a plain copy.
10930 Observer.changingInstr(MI);
10931 MI.setDesc(MIRBuilder.getTII().get(Opcode: TargetOpcode::COPY));
10932 Observer.changedInstr(MI);
10933 return Legalized;
10934 }
10935 return UnableToLegalize;
10936}
10937
10938LegalizerHelper::LegalizeResult LegalizerHelper::lowerVAArg(MachineInstr &MI) {
10939 MachineFunction &MF = *MI.getMF();
10940 const DataLayout &DL = MIRBuilder.getDataLayout();
10941 LLVMContext &Ctx = MF.getFunction().getContext();
10942 Register ListPtr = MI.getOperand(i: 1).getReg();
10943 LLT PtrTy = MRI.getType(Reg: ListPtr);
10944
10945 // LstPtr is a pointer to the head of the list. Get the address
10946 // of the head of the list.
10947 Align PtrAlignment = DL.getABITypeAlign(Ty: getTypeForLLT(Ty: PtrTy, C&: Ctx));
10948 MachineMemOperand *PtrLoadMMO = MF.getMachineMemOperand(
10949 PtrInfo: MachinePointerInfo(), F: MachineMemOperand::MOLoad, MemTy: PtrTy, BaseAlignment: PtrAlignment);
10950 auto VAList = MIRBuilder.buildLoad(Res: PtrTy, Addr: ListPtr, MMO&: *PtrLoadMMO).getReg(Idx: 0);
10951
10952 const Align A(MI.getOperand(i: 2).getImm());
10953 LLT PtrTyAsScalarTy = LLT::scalar(SizeInBits: PtrTy.getSizeInBits());
10954 if (A > TLI.getMinStackArgumentAlignment()) {
10955 Register AlignAmt =
10956 MIRBuilder.buildConstant(Res: PtrTyAsScalarTy, Val: A.value() - 1).getReg(Idx: 0);
10957 auto AddDst = MIRBuilder.buildPtrAdd(Res: PtrTy, Op0: VAList, Op1: AlignAmt);
10958 auto AndDst = MIRBuilder.buildMaskLowPtrBits(Res: PtrTy, Op0: AddDst, NumBits: Log2(A));
10959 VAList = AndDst.getReg(Idx: 0);
10960 }
10961
10962 // Increment the pointer, VAList, to the next vaarg
10963 // The list should be bumped by the size of element in the current head of
10964 // list.
10965 Register Dst = MI.getOperand(i: 0).getReg();
10966 LLT LLTTy = MRI.getType(Reg: Dst);
10967 Type *Ty = getTypeForLLT(Ty: LLTTy, C&: Ctx);
10968 auto IncAmt =
10969 MIRBuilder.buildConstant(Res: PtrTyAsScalarTy, Val: DL.getTypeAllocSize(Ty));
10970 auto Succ = MIRBuilder.buildPtrAdd(Res: PtrTy, Op0: VAList, Op1: IncAmt);
10971
10972 // Store the increment VAList to the legalized pointer
10973 MachineMemOperand *StoreMMO = MF.getMachineMemOperand(
10974 PtrInfo: MachinePointerInfo(), F: MachineMemOperand::MOStore, MemTy: PtrTy, BaseAlignment: PtrAlignment);
10975 MIRBuilder.buildStore(Val: Succ, Addr: ListPtr, MMO&: *StoreMMO);
10976 // Load the actual argument out of the pointer VAList
10977 Align EltAlignment = DL.getABITypeAlign(Ty);
10978 MachineMemOperand *EltLoadMMO = MF.getMachineMemOperand(
10979 PtrInfo: MachinePointerInfo(), F: MachineMemOperand::MOLoad, MemTy: LLTTy, BaseAlignment: EltAlignment);
10980 MIRBuilder.buildLoad(Res: Dst, Addr: VAList, MMO&: *EltLoadMMO);
10981
10982 MI.eraseFromParent();
10983 return Legalized;
10984}
10985
10986LegalizerHelper::LegalizeResult LegalizerHelper::lowerMulfix(MachineInstr &MI) {
10987 unsigned OpCode = MI.getOpcode();
10988 assert((OpCode == TargetOpcode::G_SMULFIX ||
10989 OpCode == TargetOpcode::G_UMULFIX ||
10990 OpCode == TargetOpcode::G_SMULFIXSAT ||
10991 OpCode == TargetOpcode::G_UMULFIXSAT) &&
10992 "Operator must be either G_SMULFIX[SAT] or G_UMULFIX[SAT]!");
10993 auto [Dst, LHS, RHS] = MI.getFirst3Regs();
10994 LLT Ty = MRI.getType(Reg: Dst);
10995 unsigned Scale = MI.getOperand(i: 3).getImm();
10996
10997 bool Saturating = (OpCode == TargetOpcode::G_SMULFIXSAT ||
10998 OpCode == TargetOpcode::G_UMULFIXSAT);
10999 bool IsSigned = (OpCode == TargetOpcode::G_SMULFIX ||
11000 OpCode == TargetOpcode::G_SMULFIXSAT);
11001
11002 if (!Saturating && Scale == 0) {
11003 MIRBuilder.buildMul(Dst, Src0: LHS, Src1: RHS);
11004 MI.eraseFromParent();
11005 return Legalized;
11006 }
11007
11008 // TODO: Port other lowering paths from SelectionDAG.
11009 LLT WideTy = Ty.changeElementSize(NewEltSize: Ty.getScalarSizeInBits() * 2);
11010 auto ShiftAmt = MIRBuilder.buildConstant(Res: WideTy, Val: Scale);
11011 MachineInstrBuilder ExtLHS{}, ExtRHS{}, Shift{};
11012 if (IsSigned) {
11013 ExtLHS = MIRBuilder.buildSExt(Res: WideTy, Op: LHS);
11014 ExtRHS = MIRBuilder.buildSExt(Res: WideTy, Op: RHS);
11015 } else {
11016 ExtLHS = MIRBuilder.buildZExt(Res: WideTy, Op: LHS);
11017 ExtRHS = MIRBuilder.buildZExt(Res: WideTy, Op: RHS);
11018 }
11019
11020 auto Mul = MIRBuilder.buildMul(Dst: WideTy, Src0: ExtLHS, Src1: ExtRHS);
11021 if (IsSigned)
11022 Shift = MIRBuilder.buildAShr(Dst: WideTy, Src0: Mul, Src1: ShiftAmt);
11023 else
11024 Shift = MIRBuilder.buildLShr(Dst: WideTy, Src0: Mul, Src1: ShiftAmt);
11025
11026 if (!Saturating)
11027 MIRBuilder.buildTrunc(Res: Dst, Op: Shift);
11028 else if (IsSigned)
11029 MIRBuilder.buildTruncSSatS(Res: Dst, Op: Shift);
11030 else
11031 MIRBuilder.buildTruncUSatU(Res: Dst, Op: Shift);
11032
11033 MI.eraseFromParent();
11034 return Legalized;
11035}
11036
11037// Get a vectorized representation of the memset value operand, GISel edition.
11038static Register getMemsetValue(Register Val, LLT Ty, MachineIRBuilder &MIB) {
11039 MachineRegisterInfo &MRI = *MIB.getMRI();
11040 unsigned NumBits = Ty.getScalarSizeInBits();
11041 auto ValVRegAndVal = getIConstantVRegValWithLookThrough(VReg: Val, MRI);
11042 if (!Ty.isVector() && ValVRegAndVal) {
11043 APInt Scalar = ValVRegAndVal->Value.trunc(width: 8);
11044 APInt SplatVal = APInt::getSplat(NewLen: NumBits, V: Scalar);
11045 return MIB.buildConstant(Res: Ty, Val: SplatVal).getReg(Idx: 0);
11046 }
11047
11048 // Extend the byte value to the larger type, and then multiply by a magic
11049 // value 0x010101... in order to replicate it across every byte.
11050 // Unless it's zero, in which case just emit a larger G_CONSTANT 0.
11051 if (ValVRegAndVal && ValVRegAndVal->Value == 0) {
11052 return MIB.buildConstant(Res: Ty, Val: 0).getReg(Idx: 0);
11053 }
11054
11055 LLT ExtType = Ty.getScalarType();
11056 auto ZExt = MIB.buildZExtOrTrunc(Res: ExtType, Op: Val);
11057 if (NumBits > 8) {
11058 APInt Magic = APInt::getSplat(NewLen: NumBits, V: APInt(8, 0x01));
11059 auto MagicMI = MIB.buildConstant(Res: ExtType, Val: Magic);
11060 Val = MIB.buildMul(Dst: ExtType, Src0: ZExt, Src1: MagicMI).getReg(Idx: 0);
11061 }
11062
11063 // For vector types create a G_BUILD_VECTOR.
11064 if (Ty.isVector())
11065 Val = MIB.buildSplatBuildVector(Res: Ty, Src: Val).getReg(Idx: 0);
11066
11067 return Val;
11068}
11069
11070LegalizerHelper::LegalizeResult
11071LegalizerHelper::lowerMemset(MachineInstr &MI, Register Dst, Register Val,
11072 uint64_t KnownLen, Align Alignment,
11073 bool DstAlignCanChange, ArrayRef<LLT> MemOps) {
11074 auto &MF = *MI.getParent()->getParent();
11075 const auto &TLI = *MF.getSubtarget().getTargetLowering();
11076 auto &DL = MF.getDataLayout();
11077 LLVMContext &C = MF.getFunction().getContext();
11078
11079 assert(KnownLen != 0 && "Have a zero length memset length!");
11080 assert(!MemOps.empty() && "Expected at least one memory op");
11081
11082 MachineFrameInfo &MFI = MF.getFrameInfo();
11083 MachineInstr *FIDef = getOpcodeDef(Opcode: TargetOpcode::G_FRAME_INDEX, Reg: Dst, MRI);
11084 const auto &DstMMO = **MI.memoperands_begin();
11085
11086 if (DstAlignCanChange) {
11087 // Get an estimate of the type from the LLT.
11088 Type *IRTy = getTypeForLLT(Ty: MemOps[0], C);
11089 Align NewAlign = DL.getABITypeAlign(Ty: IRTy);
11090 if (NewAlign > Alignment) {
11091 Alignment = NewAlign;
11092 unsigned FI = FIDef->getOperand(i: 1).getIndex();
11093 // Give the stack frame object a larger alignment if needed.
11094 if (MFI.getObjectAlign(ObjectIdx: FI) < Alignment)
11095 MFI.setObjectAlignment(ObjectIdx: FI, Alignment);
11096 }
11097 }
11098
11099 MachineIRBuilder MIB(MI);
11100 // Find the largest store and generate the bit pattern for it.
11101 LLT LargestTy = MemOps[0];
11102 for (unsigned i = 1; i < MemOps.size(); i++)
11103 if (MemOps[i].getSizeInBits() > LargestTy.getSizeInBits())
11104 LargestTy = MemOps[i];
11105
11106 // The memset stored value is always defined as an s8, so in order to make it
11107 // work with larger store types we need to repeat the bit pattern across the
11108 // wider type.
11109 Register MemSetValue = getMemsetValue(Val, Ty: LargestTy, MIB);
11110
11111 if (!MemSetValue)
11112 return UnableToLegalize;
11113
11114 // Generate the stores. For each store type in the list, we generate the
11115 // matching store of that type to the destination address.
11116 LLT PtrTy = MRI.getType(Reg: Dst);
11117 unsigned DstOff = 0;
11118 unsigned Size = KnownLen;
11119 for (unsigned I = 0; I < MemOps.size(); I++) {
11120 LLT Ty = MemOps[I];
11121 unsigned TySize = Ty.getSizeInBytes();
11122
11123 if (TySize > Size) {
11124 // Issuing a load / store pair that overlaps with the previous pair.
11125 // Adjust the offset accordingly.
11126 assert(I == MemOps.size() - 1 && I != 0);
11127 DstOff -= TySize - Size;
11128 }
11129
11130 // If this store is smaller than the largest store see whether we can get
11131 // the smaller value for free with a truncate.
11132 Register Value = MemSetValue;
11133 if (Ty.getSizeInBits() < LargestTy.getSizeInBits()) {
11134 MVT VT = getMVTForLLT(Ty);
11135 MVT LargestVT = getMVTForLLT(Ty: LargestTy);
11136 if (!LargestTy.isVector() && !Ty.isVector() &&
11137 TLI.isTruncateFree(FromVT: LargestVT, ToVT: VT))
11138 Value = MIB.buildTrunc(Res: Ty, Op: MemSetValue).getReg(Idx: 0);
11139 else
11140 Value = getMemsetValue(Val, Ty, MIB);
11141 if (!Value)
11142 return UnableToLegalize;
11143 }
11144
11145 auto *StoreMMO = MF.getMachineMemOperand(MMO: &DstMMO, Offset: DstOff, Ty);
11146
11147 Register Ptr = Dst;
11148 if (DstOff != 0) {
11149 auto Offset =
11150 MIB.buildConstant(Res: LLT::integer(SizeInBits: PtrTy.getSizeInBits()), Val: DstOff);
11151 Ptr = MIB.buildObjectPtrOffset(Res: PtrTy, Op0: Dst, Op1: Offset).getReg(Idx: 0);
11152 }
11153
11154 MIB.buildStore(Val: Value, Addr: Ptr, MMO&: *StoreMMO);
11155 DstOff += Ty.getSizeInBytes();
11156 Size -= TySize;
11157 }
11158
11159 MI.eraseFromParent();
11160 return Legalized;
11161}
11162
11163LegalizerHelper::LegalizeResult
11164LegalizerHelper::lowerMemcpy(MachineInstr &MI, Register Dst, Register Src,
11165 uint64_t KnownLen, Align Alignment,
11166 bool DstAlignCanChange, ArrayRef<LLT> MemOps) {
11167 auto &MF = *MI.getParent()->getParent();
11168 auto &DL = MF.getDataLayout();
11169 LLVMContext &C = MF.getFunction().getContext();
11170
11171 assert(KnownLen != 0 && "Have a zero length memcpy length!");
11172 assert(!MemOps.empty() && "Expected at least one memory op");
11173
11174 MachineFrameInfo &MFI = MF.getFrameInfo();
11175 MachineInstr *FIDef = getOpcodeDef(Opcode: TargetOpcode::G_FRAME_INDEX, Reg: Dst, MRI);
11176
11177 // FIXME: infer better src pointer alignment like SelectionDAG does here.
11178 // FIXME: also use the equivalent of isMemSrcFromConstant and alwaysinlining
11179 // if the memcpy is in a tail call position.
11180
11181 const auto &DstMMO = **MI.memoperands_begin();
11182 const auto &SrcMMO = **std::next(x: MI.memoperands_begin());
11183
11184 if (DstAlignCanChange) {
11185 // Get an estimate of the type from the LLT.
11186 Type *IRTy = getTypeForLLT(Ty: MemOps[0], C);
11187 Align NewAlign = DL.getABITypeAlign(Ty: IRTy);
11188
11189 // Don't promote to an alignment that would require dynamic stack
11190 // realignment.
11191 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
11192 if (!TRI->hasStackRealignment(MF))
11193 if (MaybeAlign StackAlign = DL.getStackAlignment())
11194 NewAlign = std::min(a: NewAlign, b: *StackAlign);
11195
11196 if (NewAlign > Alignment) {
11197 Alignment = NewAlign;
11198 unsigned FI = FIDef->getOperand(i: 1).getIndex();
11199 // Give the stack frame object a larger alignment if needed.
11200 if (MFI.getObjectAlign(ObjectIdx: FI) < Alignment)
11201 MFI.setObjectAlignment(ObjectIdx: FI, Alignment);
11202 }
11203 }
11204
11205 LLVM_DEBUG(dbgs() << "Inlining memcpy: " << MI << " into loads & stores\n");
11206
11207 MachineIRBuilder MIB(MI);
11208 // Now we need to emit a pair of load and stores for each of the types we've
11209 // collected. I.e. for each type, generate a load from the source pointer of
11210 // that type width, and then generate a corresponding store to the dest buffer
11211 // of that value loaded. This can result in a sequence of loads and stores
11212 // mixed types, depending on what the target specifies as good types to use.
11213 unsigned CurrOffset = 0;
11214 unsigned Size = KnownLen;
11215 for (auto CopyTy : MemOps) {
11216 TypeSize TySize = CopyTy.getSizeInBytes();
11217
11218 // Issuing a load / store pair that overlaps with the previous pair. Adjust
11219 // the offset accordingly.
11220 if (TySize > Size) {
11221 unsigned Overlap = TySize - Size;
11222 assert(Overlap < CurrOffset &&
11223 "overlapping memcpy load/store spans the whole region or more");
11224 CurrOffset -= Overlap;
11225 }
11226
11227 // Construct MMOs for the accesses.
11228 auto *LoadMMO = MF.getMachineMemOperand(MMO: &SrcMMO, Offset: CurrOffset, Size: TySize);
11229 auto *StoreMMO = MF.getMachineMemOperand(MMO: &DstMMO, Offset: CurrOffset, Size: TySize);
11230
11231 // Create the load.
11232 Register LoadPtr = Src;
11233 Register Offset;
11234 if (CurrOffset != 0) {
11235 LLT SrcTy = MRI.getType(Reg: Src);
11236 Offset =
11237 MIB.buildConstant(Res: LLT::integer(SizeInBits: SrcTy.getSizeInBits()), Val: CurrOffset)
11238 .getReg(Idx: 0);
11239 LoadPtr = MIB.buildObjectPtrOffset(Res: SrcTy, Op0: Src, Op1: Offset).getReg(Idx: 0);
11240 }
11241 auto LdVal = MIB.buildLoad(Res: CopyTy, Addr: LoadPtr, MMO&: *LoadMMO);
11242
11243 // Create the store.
11244 Register StorePtr = Dst;
11245 if (CurrOffset != 0) {
11246 LLT DstTy = MRI.getType(Reg: Dst);
11247 StorePtr = MIB.buildObjectPtrOffset(Res: DstTy, Op0: Dst, Op1: Offset).getReg(Idx: 0);
11248 }
11249 MIB.buildStore(Val: LdVal, Addr: StorePtr, MMO&: *StoreMMO);
11250 CurrOffset += TySize;
11251 Size -= TySize;
11252 }
11253
11254 MI.eraseFromParent();
11255 return Legalized;
11256}
11257
11258LegalizerHelper::LegalizeResult
11259LegalizerHelper::lowerMemmove(MachineInstr &MI, Register Dst, Register Src,
11260 uint64_t KnownLen, Align Alignment,
11261 bool DstAlignCanChange, ArrayRef<LLT> MemOps) {
11262 auto &MF = *MI.getParent()->getParent();
11263 auto &DL = MF.getDataLayout();
11264 LLVMContext &C = MF.getFunction().getContext();
11265
11266 assert(KnownLen != 0 && "Have a zero length memmove length!");
11267 assert(!MemOps.empty() && "Expected at least one memory op");
11268
11269 MachineFrameInfo &MFI = MF.getFrameInfo();
11270 MachineInstr *FIDef = getOpcodeDef(Opcode: TargetOpcode::G_FRAME_INDEX, Reg: Dst, MRI);
11271 const auto &DstMMO = **MI.memoperands_begin();
11272 const auto &SrcMMO = **std::next(x: MI.memoperands_begin());
11273
11274 if (DstAlignCanChange) {
11275 // Get an estimate of the type from the LLT.
11276 Type *IRTy = getTypeForLLT(Ty: MemOps[0], C);
11277 Align NewAlign = DL.getABITypeAlign(Ty: IRTy);
11278
11279 // Don't promote to an alignment that would require dynamic stack
11280 // realignment.
11281 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
11282 if (!TRI->hasStackRealignment(MF))
11283 if (MaybeAlign StackAlign = DL.getStackAlignment())
11284 NewAlign = std::min(a: NewAlign, b: *StackAlign);
11285
11286 if (NewAlign > Alignment) {
11287 Alignment = NewAlign;
11288 unsigned FI = FIDef->getOperand(i: 1).getIndex();
11289 // Give the stack frame object a larger alignment if needed.
11290 if (MFI.getObjectAlign(ObjectIdx: FI) < Alignment)
11291 MFI.setObjectAlignment(ObjectIdx: FI, Alignment);
11292 }
11293 }
11294
11295 LLVM_DEBUG(dbgs() << "Inlining memmove: " << MI << " into loads & stores\n");
11296
11297 MachineIRBuilder MIB(MI);
11298 // Memmove requires that we perform the loads first before issuing the stores.
11299 // Apart from that, this loop is pretty much doing the same thing as the
11300 // memcpy codegen function.
11301 unsigned CurrOffset = 0;
11302 unsigned Size = KnownLen;
11303 SmallVector<Register, 16> LoadVals;
11304 for (auto CopyTy : MemOps) {
11305 TypeSize TySize = CopyTy.getSizeInBytes();
11306
11307 // Issuing a load that overlaps with the previous load. Adjust the offset
11308 // accordingly.
11309 if (TySize > Size) {
11310 unsigned Overlap = TySize - Size;
11311 assert(Overlap < CurrOffset &&
11312 "overlapping memmove load spans the whole region or more");
11313 CurrOffset -= Overlap;
11314 }
11315
11316 // Construct MMO for the load.
11317 auto *LoadMMO = MF.getMachineMemOperand(MMO: &SrcMMO, Offset: CurrOffset, Size: TySize);
11318
11319 // Create the load.
11320 Register LoadPtr = Src;
11321 if (CurrOffset != 0) {
11322 LLT SrcTy = MRI.getType(Reg: Src);
11323 auto Offset =
11324 MIB.buildConstant(Res: LLT::integer(SizeInBits: SrcTy.getSizeInBits()), Val: CurrOffset);
11325 LoadPtr = MIB.buildObjectPtrOffset(Res: SrcTy, Op0: Src, Op1: Offset).getReg(Idx: 0);
11326 }
11327 LoadVals.push_back(Elt: MIB.buildLoad(Res: CopyTy, Addr: LoadPtr, MMO&: *LoadMMO).getReg(Idx: 0));
11328 CurrOffset += TySize;
11329 Size -= TySize;
11330 }
11331
11332 CurrOffset = 0;
11333 Size = KnownLen;
11334 for (unsigned I = 0; I < MemOps.size(); ++I) {
11335 LLT CopyTy = MemOps[I];
11336 TypeSize TySize = CopyTy.getSizeInBytes();
11337
11338 // Issuing a store that overlaps with the previous store. Adjust the offset
11339 // accordingly.
11340 if (TySize > Size) {
11341 unsigned Overlap = TySize - Size;
11342 assert(Overlap < CurrOffset &&
11343 "overlapping memmove store spans the whole region or more");
11344 CurrOffset -= Overlap;
11345 }
11346
11347 // Now store the values loaded.
11348 auto *StoreMMO = MF.getMachineMemOperand(MMO: &DstMMO, Offset: CurrOffset, Size: TySize);
11349
11350 Register StorePtr = Dst;
11351 if (CurrOffset != 0) {
11352 LLT DstTy = MRI.getType(Reg: Dst);
11353 auto Offset =
11354 MIB.buildConstant(Res: LLT::integer(SizeInBits: DstTy.getSizeInBits()), Val: CurrOffset);
11355 StorePtr = MIB.buildObjectPtrOffset(Res: DstTy, Op0: Dst, Op1: Offset).getReg(Idx: 0);
11356 }
11357 MIB.buildStore(Val: LoadVals[I], Addr: StorePtr, MMO&: *StoreMMO);
11358 CurrOffset += TySize;
11359 Size -= TySize;
11360 }
11361 MI.eraseFromParent();
11362 return Legalized;
11363}
11364
11365LegalizerHelper::LegalizeResult LegalizerHelper::lowerMemCpyFamily(
11366 MachineInstr &MI, Register Dst, Register Src, uint64_t KnownLen,
11367 Align Alignment, bool DstAlignCanChange, ArrayRef<LLT> MemOps) {
11368 const unsigned Opc = MI.getOpcode();
11369 assert((Opc == TargetOpcode::G_MEMCPY ||
11370 Opc == TargetOpcode::G_MEMCPY_INLINE ||
11371 Opc == TargetOpcode::G_MEMMOVE || Opc == TargetOpcode::G_MEMSET ||
11372 Opc == TargetOpcode::G_MEMSET_INLINE) &&
11373 "Expected memcpy like instruction");
11374
11375 if (KnownLen == 0) {
11376 MI.eraseFromParent();
11377 return Legalized;
11378 }
11379
11380 if (Opc == TargetOpcode::G_MEMCPY || Opc == TargetOpcode::G_MEMCPY_INLINE) {
11381 return lowerMemcpy(MI, Dst, Src, KnownLen, Alignment, DstAlignCanChange,
11382 MemOps);
11383 }
11384 if (Opc == TargetOpcode::G_MEMMOVE)
11385 return lowerMemmove(MI, Dst, Src, KnownLen, Alignment, DstAlignCanChange,
11386 MemOps);
11387 if (Opc == TargetOpcode::G_MEMSET || Opc == TargetOpcode::G_MEMSET_INLINE)
11388 return lowerMemset(MI, Dst, Val: Src, KnownLen, Alignment, DstAlignCanChange,
11389 MemOps);
11390 return UnableToLegalize;
11391}
11392
11393LegalizerHelper::LegalizeResult
11394LegalizerHelper::lowerMemCpyFamily(MachineInstr &MI, unsigned MaxLen) {
11395 Register Dst, Src;
11396 uint64_t KnownLen;
11397 Align Alignment;
11398 bool DstAlignCanChange;
11399 std::vector<LLT> MemOps;
11400 if (!canLowerMemCpyFamily(MI, MRI, MaxLen, Dst, Src, KnownLen, Alignment,
11401 DstAlignCanChange, MemOps))
11402 return UnableToLegalize;
11403 return lowerMemCpyFamily(MI, Dst, Src, KnownLen, Alignment, DstAlignCanChange,
11404 MemOps);
11405}
11406