1//===- InlineSpiller.cpp - Insert spills and restores inline --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// The inline spiller modifies the machine function directly instead of
10// inserting spills and restores in VirtRegMap.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AllocationOrder.h"
15#include "SplitKit.h"
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/DenseMap.h"
18#include "llvm/ADT/MapVector.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/ADT/SetVector.h"
21#include "llvm/ADT/SmallPtrSet.h"
22#include "llvm/ADT/SmallVector.h"
23#include "llvm/ADT/Statistic.h"
24#include "llvm/CodeGen/LiveInterval.h"
25#include "llvm/CodeGen/LiveIntervals.h"
26#include "llvm/CodeGen/LiveRangeEdit.h"
27#include "llvm/CodeGen/LiveRegMatrix.h"
28#include "llvm/CodeGen/LiveStacks.h"
29#include "llvm/CodeGen/MachineBasicBlock.h"
30#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
31#include "llvm/CodeGen/MachineDominators.h"
32#include "llvm/CodeGen/MachineFunction.h"
33#include "llvm/CodeGen/MachineInstr.h"
34#include "llvm/CodeGen/MachineInstrBuilder.h"
35#include "llvm/CodeGen/MachineInstrBundle.h"
36#include "llvm/CodeGen/MachineOperand.h"
37#include "llvm/CodeGen/MachineRegisterInfo.h"
38#include "llvm/CodeGen/SlotIndexes.h"
39#include "llvm/CodeGen/Spiller.h"
40#include "llvm/CodeGen/StackMaps.h"
41#include "llvm/CodeGen/TargetInstrInfo.h"
42#include "llvm/CodeGen/TargetOpcodes.h"
43#include "llvm/CodeGen/TargetRegisterInfo.h"
44#include "llvm/CodeGen/TargetSubtargetInfo.h"
45#include "llvm/CodeGen/VirtRegMap.h"
46#include "llvm/Config/llvm-config.h"
47#include "llvm/Support/BlockFrequency.h"
48#include "llvm/Support/BranchProbability.h"
49#include "llvm/Support/CommandLine.h"
50#include "llvm/Support/Compiler.h"
51#include "llvm/Support/Debug.h"
52#include "llvm/Support/ErrorHandling.h"
53#include "llvm/Support/raw_ostream.h"
54#include <cassert>
55#include <iterator>
56#include <tuple>
57#include <utility>
58
59using namespace llvm;
60
61#define DEBUG_TYPE "regalloc"
62
63STATISTIC(NumSpilledRanges, "Number of spilled live ranges");
64STATISTIC(NumSnippets, "Number of spilled snippets");
65STATISTIC(NumSpills, "Number of spills inserted");
66STATISTIC(NumSpillsRemoved, "Number of spills removed");
67STATISTIC(NumReloads, "Number of reloads inserted");
68STATISTIC(NumReloadsRemoved, "Number of reloads removed");
69STATISTIC(NumFolded, "Number of folded stack accesses");
70STATISTIC(NumFoldedLoads, "Number of folded loads");
71STATISTIC(NumRemats, "Number of rematerialized defs for spilling");
72
73static cl::opt<bool>
74RestrictStatepointRemat("restrict-statepoint-remat",
75 cl::init(Val: false), cl::Hidden,
76 cl::desc("Restrict remat for statepoint operands"));
77
78namespace {
79class HoistSpillHelper : private LiveRangeEdit::Delegate {
80 MachineFunction &MF;
81 LiveIntervals &LIS;
82 LiveStacks &LSS;
83 MachineDominatorTree &MDT;
84 VirtRegMap &VRM;
85 MachineRegisterInfo &MRI;
86 const TargetInstrInfo &TII;
87 const TargetRegisterInfo &TRI;
88 const MachineBlockFrequencyInfo &MBFI;
89 LiveRegMatrix *Matrix;
90
91 InsertPointAnalysis IPA;
92
93 // Map from StackSlot to the LiveInterval of the original register.
94 // Note the LiveInterval of the original register may have been deleted
95 // after it is spilled. We keep a copy here to track the range where
96 // spills can be moved.
97 DenseMap<int, std::unique_ptr<LiveInterval>> StackSlotToOrigLI;
98
99 // Map from pair of (StackSlot and Original VNI) to a set of spills which
100 // have the same stackslot and have equal values defined by Original VNI.
101 // These spills are mergeable and are hoist candidates.
102 using MergeableSpillsMap =
103 MapVector<std::pair<int, VNInfo *>, SmallPtrSet<MachineInstr *, 16>>;
104 MergeableSpillsMap MergeableSpills;
105
106 /// This is the map from original register to a set containing all its
107 /// siblings. To hoist a spill to another BB, we need to find out a live
108 /// sibling there and use it as the source of the new spill.
109 DenseMap<Register, SmallSetVector<Register, 16>> Virt2SiblingsMap;
110
111 bool isSpillCandBB(LiveInterval &OrigLI, VNInfo &OrigVNI,
112 MachineBasicBlock &BB, Register &LiveReg);
113
114 void rmRedundantSpills(
115 SmallPtrSet<MachineInstr *, 16> &Spills,
116 SmallVectorImpl<MachineInstr *> &SpillsToRm,
117 DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill);
118
119 void getVisitOrders(
120 MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
121 SmallVectorImpl<MachineDomTreeNode *> &Orders,
122 SmallVectorImpl<MachineInstr *> &SpillsToRm,
123 DenseMap<MachineDomTreeNode *, Register> &SpillsToKeep,
124 DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill);
125
126 void runHoistSpills(LiveInterval &OrigLI, VNInfo &OrigVNI,
127 SmallPtrSet<MachineInstr *, 16> &Spills,
128 SmallVectorImpl<MachineInstr *> &SpillsToRm,
129 DenseMap<MachineBasicBlock *, Register> &SpillsToIns);
130
131public:
132 HoistSpillHelper(const Spiller::RequiredAnalyses &Analyses,
133 MachineFunction &mf, VirtRegMap &vrm, LiveRegMatrix *matrix)
134 : MF(mf), LIS(Analyses.LIS), LSS(Analyses.LSS), MDT(Analyses.MDT),
135 VRM(vrm), MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
136 TRI(*mf.getSubtarget().getRegisterInfo()), MBFI(Analyses.MBFI),
137 Matrix(matrix), IPA(LIS, mf.getNumBlockIDs()) {}
138
139 void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
140 Register Original);
141 bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
142 void hoistAllSpills();
143 bool LRE_CanEraseVirtReg(Register) override;
144 void LRE_DidCloneVirtReg(Register, Register) override;
145};
146
147class InlineSpiller : public Spiller {
148 MachineFunction &MF;
149 LiveIntervals &LIS;
150 LiveStacks &LSS;
151 VirtRegMap &VRM;
152 MachineRegisterInfo &MRI;
153 const TargetInstrInfo &TII;
154 const TargetRegisterInfo &TRI;
155 LiveRegMatrix *Matrix = nullptr;
156
157 // Variables that are valid during spill(), but used by multiple methods.
158 LiveRangeEdit *Edit = nullptr;
159 LiveInterval *StackInt = nullptr;
160 int StackSlot;
161 Register Original;
162 AllocationOrder *Order = nullptr;
163
164 // All registers to spill to StackSlot, including the main register.
165 SmallVector<Register, 8> RegsToSpill;
166
167 // All registers that were replaced by the spiller through some other method,
168 // e.g. rematerialization.
169 SmallVector<Register, 8> RegsReplaced;
170
171 // All COPY instructions to/from snippets.
172 // They are ignored since both operands refer to the same stack slot.
173 // For bundled copies, this will only include the first header copy.
174 SmallPtrSet<MachineInstr*, 8> SnippetCopies;
175
176 // Values that failed to remat at some point.
177 SmallPtrSet<VNInfo*, 8> UsedValues;
178
179 // Dead defs generated during spilling.
180 SmallVector<MachineInstr*, 8> DeadDefs;
181
182 // Object records spills information and does the hoisting.
183 HoistSpillHelper HSpiller;
184
185 // Live range weight calculator.
186 VirtRegAuxInfo &VRAI;
187
188 ~InlineSpiller() override = default;
189
190public:
191 InlineSpiller(const Spiller::RequiredAnalyses &Analyses, MachineFunction &MF,
192 VirtRegMap &VRM, VirtRegAuxInfo &VRAI, LiveRegMatrix *Matrix)
193 : MF(MF), LIS(Analyses.LIS), LSS(Analyses.LSS), VRM(VRM),
194 MRI(MF.getRegInfo()), TII(*MF.getSubtarget().getInstrInfo()),
195 TRI(*MF.getSubtarget().getRegisterInfo()), Matrix(Matrix),
196 HSpiller(Analyses, MF, VRM, Matrix), VRAI(VRAI) {}
197
198 void spill(LiveRangeEdit &, AllocationOrder *Order = nullptr) override;
199 ArrayRef<Register> getSpilledRegs() override { return RegsToSpill; }
200 ArrayRef<Register> getReplacedRegs() override { return RegsReplaced; }
201 void postOptimization() override;
202
203private:
204 bool isSnippet(const LiveInterval &SnipLI);
205 void collectRegsToSpill();
206
207 bool isRegToSpill(Register Reg) { return is_contained(Range&: RegsToSpill, Element: Reg); }
208
209 bool isSibling(Register Reg);
210 bool hoistSpillInsideBB(LiveInterval &SpillLI, MachineInstr &CopyMI);
211 void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI);
212
213 void markValueUsed(LiveInterval*, VNInfo*);
214 bool canGuaranteeAssignmentAfterRemat(Register VReg, MachineInstr &MI);
215 bool hasPhysRegAvailable(const MachineInstr &MI);
216 bool reMaterializeFor(LiveInterval &, MachineInstr &MI);
217 void reMaterializeAll();
218
219 bool coalesceStackAccess(MachineInstr *MI, Register Reg);
220 bool foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>>,
221 MachineInstr *LoadMI = nullptr);
222 void insertReload(Register VReg, SlotIndex, MachineBasicBlock::iterator MI);
223 void insertSpill(Register VReg, bool isKill, MachineBasicBlock::iterator MI);
224
225 void spillAroundUses(Register Reg);
226 void spillAll();
227};
228
229} // end anonymous namespace
230
231Spiller::~Spiller() = default;
232
233void Spiller::anchor() {}
234
235Spiller *
236llvm::createInlineSpiller(const InlineSpiller::RequiredAnalyses &Analyses,
237 MachineFunction &MF, VirtRegMap &VRM,
238 VirtRegAuxInfo &VRAI, LiveRegMatrix *Matrix) {
239 return new InlineSpiller(Analyses, MF, VRM, VRAI, Matrix);
240}
241
242//===----------------------------------------------------------------------===//
243// Snippets
244//===----------------------------------------------------------------------===//
245
246// When spilling a virtual register, we also spill any snippets it is connected
247// to. The snippets are small live ranges that only have a single real use,
248// leftovers from live range splitting. Spilling them enables memory operand
249// folding or tightens the live range around the single use.
250//
251// This minimizes register pressure and maximizes the store-to-load distance for
252// spill slots which can be important in tight loops.
253
254/// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
255/// otherwise return 0.
256static Register isCopyOf(const MachineInstr &MI, Register Reg,
257 const TargetInstrInfo &TII) {
258 if (!TII.isCopyInstr(MI))
259 return Register();
260
261 const MachineOperand &DstOp = MI.getOperand(i: 0);
262 const MachineOperand &SrcOp = MI.getOperand(i: 1);
263
264 // TODO: Probably only worth allowing subreg copies with undef dests.
265 if (DstOp.getSubReg() != SrcOp.getSubReg())
266 return Register();
267 if (DstOp.getReg() == Reg)
268 return SrcOp.getReg();
269 if (SrcOp.getReg() == Reg)
270 return DstOp.getReg();
271 return Register();
272}
273
274/// Check for a copy bundle as formed by SplitKit.
275static Register isCopyOfBundle(const MachineInstr &FirstMI, Register Reg,
276 const TargetInstrInfo &TII) {
277 if (!FirstMI.isBundled())
278 return isCopyOf(MI: FirstMI, Reg, TII);
279
280 assert(!FirstMI.isBundledWithPred() && FirstMI.isBundledWithSucc() &&
281 "expected to see first instruction in bundle");
282
283 Register SnipReg;
284 MachineBasicBlock::const_instr_iterator I = FirstMI.getIterator();
285 while (I->isBundledWithSucc()) {
286 const MachineInstr &MI = *I;
287 auto CopyInst = TII.isCopyInstr(MI);
288 if (!CopyInst)
289 return Register();
290
291 const MachineOperand &DstOp = *CopyInst->Destination;
292 const MachineOperand &SrcOp = *CopyInst->Source;
293 if (DstOp.getReg() == Reg) {
294 if (!SnipReg)
295 SnipReg = SrcOp.getReg();
296 else if (SnipReg != SrcOp.getReg())
297 return Register();
298 } else if (SrcOp.getReg() == Reg) {
299 if (!SnipReg)
300 SnipReg = DstOp.getReg();
301 else if (SnipReg != DstOp.getReg())
302 return Register();
303 }
304
305 ++I;
306 }
307
308 return Register();
309}
310
311static void getVDefInterval(const MachineInstr &MI, LiveIntervals &LIS) {
312 for (const MachineOperand &MO : MI.all_defs())
313 if (MO.getReg().isVirtual())
314 LIS.getInterval(Reg: MO.getReg());
315}
316
317/// isSnippet - Identify if a live interval is a snippet that should be spilled.
318/// It is assumed that SnipLI is a virtual register with the same original as
319/// Edit->getReg().
320bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
321 Register Reg = Edit->getReg();
322
323 // A snippet is a tiny live range with only a single instruction using it
324 // besides copies to/from Reg or spills/fills.
325 // Exception is done for statepoint instructions which will fold fills
326 // into their operands.
327 // We accept:
328 //
329 // %snip = COPY %Reg / FILL fi#
330 // %snip = USE %snip
331 // %snip = STATEPOINT %snip in var arg area
332 // %Reg = COPY %snip / SPILL %snip, fi#
333 //
334 if (!LIS.intervalIsInOneMBB(LI: SnipLI))
335 return false;
336
337 // Number of defs should not exceed 2 not accounting defs coming from
338 // statepoint instructions.
339 unsigned NumValNums = SnipLI.getNumValNums();
340 for (auto *VNI : SnipLI.vnis()) {
341 MachineInstr *MI = LIS.getInstructionFromIndex(index: VNI->def);
342 if (MI->getOpcode() == TargetOpcode::STATEPOINT)
343 --NumValNums;
344 }
345 if (NumValNums > 2)
346 return false;
347
348 MachineInstr *UseMI = nullptr;
349
350 // Check that all uses satisfy our criteria.
351 for (MachineRegisterInfo::reg_bundle_nodbg_iterator
352 RI = MRI.reg_bundle_nodbg_begin(RegNo: SnipLI.reg()),
353 E = MRI.reg_bundle_nodbg_end();
354 RI != E;) {
355 MachineInstr &MI = *RI++;
356
357 // Allow copies to/from Reg.
358 if (isCopyOfBundle(FirstMI: MI, Reg, TII))
359 continue;
360
361 // Allow stack slot loads.
362 int FI;
363 if (SnipLI.reg() == TII.isLoadFromStackSlot(MI, FrameIndex&: FI) && FI == StackSlot)
364 continue;
365
366 // Allow stack slot stores.
367 if (SnipLI.reg() == TII.isStoreToStackSlot(MI, FrameIndex&: FI) && FI == StackSlot)
368 continue;
369
370 if (StatepointOpers::isFoldableReg(MI: &MI, Reg: SnipLI.reg()))
371 continue;
372
373 // Allow a single additional instruction.
374 if (UseMI && &MI != UseMI)
375 return false;
376 UseMI = &MI;
377 }
378 return true;
379}
380
381/// collectRegsToSpill - Collect live range snippets that only have a single
382/// real use.
383void InlineSpiller::collectRegsToSpill() {
384 Register Reg = Edit->getReg();
385
386 // Main register always spills.
387 RegsToSpill.assign(NumElts: 1, Elt: Reg);
388 SnippetCopies.clear();
389 RegsReplaced.clear();
390
391 // Snippets all have the same original, so there can't be any for an original
392 // register.
393 if (Original == Reg)
394 return;
395
396 for (MachineInstr &MI : llvm::make_early_inc_range(Range: MRI.reg_bundles(Reg))) {
397 Register SnipReg = isCopyOfBundle(FirstMI: MI, Reg, TII);
398 if (!isSibling(Reg: SnipReg))
399 continue;
400 LiveInterval &SnipLI = LIS.getInterval(Reg: SnipReg);
401 if (!isSnippet(SnipLI))
402 continue;
403 SnippetCopies.insert(Ptr: &MI);
404 if (isRegToSpill(Reg: SnipReg))
405 continue;
406 RegsToSpill.push_back(Elt: SnipReg);
407 LLVM_DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n');
408 ++NumSnippets;
409 }
410}
411
412bool InlineSpiller::isSibling(Register Reg) {
413 return Reg.isVirtual() && VRM.getOriginal(VirtReg: Reg) == Original;
414}
415
416/// It is beneficial to spill to earlier place in the same BB in case
417/// as follows:
418/// There is an alternative def earlier in the same MBB.
419/// Hoist the spill as far as possible in SpillMBB. This can ease
420/// register pressure:
421///
422/// x = def
423/// y = use x
424/// s = copy x
425///
426/// Hoisting the spill of s to immediately after the def removes the
427/// interference between x and y:
428///
429/// x = def
430/// spill x
431/// y = use killed x
432///
433/// This hoist only helps when the copy kills its source.
434///
435bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI,
436 MachineInstr &CopyMI) {
437 SlotIndex Idx = LIS.getInstructionIndex(Instr: CopyMI);
438#ifndef NDEBUG
439 VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot());
440 assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy");
441#endif
442
443 Register SrcReg = CopyMI.getOperand(i: 1).getReg();
444 LiveInterval &SrcLI = LIS.getInterval(Reg: SrcReg);
445 VNInfo *SrcVNI = SrcLI.getVNInfoAt(Idx);
446 LiveQueryResult SrcQ = SrcLI.Query(Idx);
447 MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(index: SrcVNI->def);
448 if (DefMBB != CopyMI.getParent() || !SrcQ.isKill())
449 return false;
450
451 // Conservatively extend the stack slot range to the range of the original
452 // value. We may be able to do better with stack slot coloring by being more
453 // careful here.
454 assert(StackInt && "No stack slot assigned yet.");
455 LiveInterval &OrigLI = LIS.getInterval(Reg: Original);
456 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
457 StackInt->MergeValueInAsValue(RHS: OrigLI, RHSValNo: OrigVNI, LHSValNo: StackInt->getValNumInfo(ValNo: 0));
458 LLVM_DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "
459 << *StackInt << '\n');
460
461 // We are going to spill SrcVNI immediately after its def, so clear out
462 // any later spills of the same value.
463 eliminateRedundantSpills(LI&: SrcLI, VNI: SrcVNI);
464
465 MachineBasicBlock *MBB = LIS.getMBBFromIndex(index: SrcVNI->def);
466 MachineBasicBlock::iterator MII;
467 if (SrcVNI->isPHIDef())
468 MII = MBB->SkipPHIsLabelsAndDebug(I: MBB->begin(), Reg: SrcReg);
469 else {
470 MachineInstr *DefMI = LIS.getInstructionFromIndex(index: SrcVNI->def);
471 assert(DefMI && "Defining instruction disappeared");
472 MII = DefMI;
473 ++MII;
474 }
475 MachineInstrSpan MIS(MII, MBB);
476 // Insert spill without kill flag immediately after def.
477 TII.storeRegToStackSlot(MBB&: *MBB, MI: MII, SrcReg, isKill: false, FrameIndex: StackSlot,
478 RC: MRI.getRegClass(Reg: SrcReg), VReg: Register());
479 LIS.InsertMachineInstrRangeInMaps(B: MIS.begin(), E: MII);
480 for (const MachineInstr &MI : make_range(x: MIS.begin(), y: MII))
481 getVDefInterval(MI, LIS);
482 --MII; // Point to store instruction.
483 LLVM_DEBUG(dbgs() << "\thoisted: " << SrcVNI->def << '\t' << *MII);
484
485 // If there is only 1 store instruction is required for spill, add it
486 // to mergeable list. In X86 AMX, 2 intructions are required to store.
487 // We disable the merge for this case.
488 if (MIS.begin() == MII)
489 HSpiller.addToMergeableSpills(Spill&: *MII, StackSlot, Original);
490 ++NumSpills;
491 return true;
492}
493
494/// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any
495/// redundant spills of this value in SLI.reg and sibling copies.
496void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
497 assert(VNI && "Missing value");
498 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
499 WorkList.push_back(Elt: std::make_pair(x: &SLI, y&: VNI));
500 assert(StackInt && "No stack slot assigned yet.");
501
502 do {
503 LiveInterval *LI;
504 std::tie(args&: LI, args&: VNI) = WorkList.pop_back_val();
505 Register Reg = LI->reg();
506 LLVM_DEBUG(dbgs() << "Checking redundant spills for " << VNI->id << '@'
507 << VNI->def << " in " << *LI << '\n');
508
509 // Regs to spill are taken care of.
510 if (isRegToSpill(Reg))
511 continue;
512
513 // Add all of VNI's live range to StackInt.
514 StackInt->MergeValueInAsValue(RHS: *LI, RHSValNo: VNI, LHSValNo: StackInt->getValNumInfo(ValNo: 0));
515 LLVM_DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n');
516
517 // Find all spills and copies of VNI.
518 for (MachineInstr &MI :
519 llvm::make_early_inc_range(Range: MRI.use_nodbg_bundles(Reg))) {
520 if (!MI.mayStore() && !TII.isCopyInstr(MI))
521 continue;
522 SlotIndex Idx = LIS.getInstructionIndex(Instr: MI);
523 if (LI->getVNInfoAt(Idx) != VNI)
524 continue;
525
526 // Follow sibling copies down the dominator tree.
527 if (Register DstReg = isCopyOfBundle(FirstMI: MI, Reg, TII)) {
528 if (isSibling(Reg: DstReg)) {
529 LiveInterval &DstLI = LIS.getInterval(Reg: DstReg);
530 VNInfo *DstVNI = DstLI.getVNInfoAt(Idx: Idx.getRegSlot());
531 assert(DstVNI && "Missing defined value");
532 assert(DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot");
533
534 WorkList.push_back(Elt: std::make_pair(x: &DstLI, y&: DstVNI));
535 }
536 continue;
537 }
538
539 // Erase spills.
540 int FI;
541 if (Reg == TII.isStoreToStackSlot(MI, FrameIndex&: FI) && FI == StackSlot) {
542 LLVM_DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << MI);
543 // eliminateDeadDefs won't normally remove stores, so switch opcode.
544 MI.setDesc(TII.get(Opcode: TargetOpcode::KILL));
545 DeadDefs.push_back(Elt: &MI);
546 ++NumSpillsRemoved;
547 if (HSpiller.rmFromMergeableSpills(Spill&: MI, StackSlot))
548 --NumSpills;
549 }
550 }
551 } while (!WorkList.empty());
552}
553
554//===----------------------------------------------------------------------===//
555// Rematerialization
556//===----------------------------------------------------------------------===//
557
558/// markValueUsed - Remember that VNI failed to rematerialize, so its defining
559/// instruction cannot be eliminated. See through snippet copies
560void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
561 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
562 WorkList.push_back(Elt: std::make_pair(x&: LI, y&: VNI));
563 do {
564 std::tie(args&: LI, args&: VNI) = WorkList.pop_back_val();
565 if (!UsedValues.insert(Ptr: VNI).second)
566 continue;
567
568 if (VNI->isPHIDef()) {
569 MachineBasicBlock *MBB = LIS.getMBBFromIndex(index: VNI->def);
570 for (MachineBasicBlock *P : MBB->predecessors()) {
571 VNInfo *PVNI = LI->getVNInfoBefore(Idx: LIS.getMBBEndIdx(mbb: P));
572 if (PVNI)
573 WorkList.push_back(Elt: std::make_pair(x&: LI, y&: PVNI));
574 }
575 continue;
576 }
577
578 // Follow snippet copies.
579 MachineInstr *MI = LIS.getInstructionFromIndex(index: VNI->def);
580 if (!SnippetCopies.count(Ptr: MI))
581 continue;
582 LiveInterval &SnipLI = LIS.getInterval(Reg: MI->getOperand(i: 1).getReg());
583 assert(isRegToSpill(SnipLI.reg()) && "Unexpected register in copy");
584 VNInfo *SnipVNI = SnipLI.getVNInfoAt(Idx: VNI->def.getRegSlot(EC: true));
585 assert(SnipVNI && "Snippet undefined before copy");
586 WorkList.push_back(Elt: std::make_pair(x: &SnipLI, y&: SnipVNI));
587 } while (!WorkList.empty());
588}
589
590bool InlineSpiller::canGuaranteeAssignmentAfterRemat(Register VReg,
591 MachineInstr &MI) {
592 if (!RestrictStatepointRemat)
593 return true;
594 // Here's a quick explanation of the problem we're trying to handle here:
595 // * There are some pseudo instructions with more vreg uses than there are
596 // physical registers on the machine.
597 // * This is normally handled by spilling the vreg, and folding the reload
598 // into the user instruction. (Thus decreasing the number of used vregs
599 // until the remainder can be assigned to physregs.)
600 // * However, since we may try to spill vregs in any order, we can end up
601 // trying to spill each operand to the instruction, and then rematting it
602 // instead. When that happens, the new live intervals (for the remats) are
603 // expected to be trivially assignable (i.e. RS_Done). However, since we
604 // may have more remats than physregs, we're guaranteed to fail to assign
605 // one.
606 // At the moment, we only handle this for STATEPOINTs since they're the only
607 // pseudo op where we've seen this. If we start seeing other instructions
608 // with the same problem, we need to revisit this.
609 if (MI.getOpcode() != TargetOpcode::STATEPOINT)
610 return true;
611 // For STATEPOINTs we allow re-materialization for fixed arguments only hoping
612 // that number of physical registers is enough to cover all fixed arguments.
613 // If it is not true we need to revisit it.
614 for (unsigned Idx = StatepointOpers(&MI).getVarIdx(),
615 EndIdx = MI.getNumOperands();
616 Idx < EndIdx; ++Idx) {
617 MachineOperand &MO = MI.getOperand(i: Idx);
618 if (MO.isReg() && MO.getReg() == VReg)
619 return false;
620 }
621 return true;
622}
623
624/// hasPhysRegAvailable - Check if there is an available physical register for
625/// rematerialization.
626bool InlineSpiller::hasPhysRegAvailable(const MachineInstr &MI) {
627 if (!Order || !Matrix)
628 return false;
629
630 SlotIndex UseIdx = LIS.getInstructionIndex(Instr: MI).getRegSlot(EC: true);
631 SlotIndex PrevIdx = UseIdx.getPrevSlot();
632
633 for (MCPhysReg PhysReg : *Order) {
634 if (!Matrix->checkInterference(Start: PrevIdx, End: UseIdx, PhysReg))
635 return true;
636 }
637
638 return false;
639}
640
641/// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
642bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
643 // Analyze instruction
644 SmallVector<std::pair<MachineInstr *, unsigned>, 8> Ops;
645 VirtRegInfo RI = AnalyzeVirtRegInBundle(MI, Reg: VirtReg.reg(), Ops: &Ops);
646
647 // Defs without reads will be deleted if unused after remat is
648 // completed for other users of the virtual register.
649 if (!RI.Reads) {
650 LLVM_DEBUG(dbgs() << "\tskipping remat of def " << MI);
651 return false;
652 }
653
654 SlotIndex UseIdx = LIS.getInstructionIndex(Instr: MI).getRegSlot(EC: true);
655 VNInfo *ParentVNI = VirtReg.getVNInfoAt(Idx: UseIdx.getBaseIndex());
656
657 if (!ParentVNI) {
658 LLVM_DEBUG(dbgs() << "\tadding <undef> flags: ");
659 for (MachineOperand &MO : MI.all_uses())
660 if (MO.getReg() == VirtReg.reg())
661 MO.setIsUndef();
662 LLVM_DEBUG(dbgs() << UseIdx << '\t' << MI);
663 return true;
664 }
665
666 // Snippets copies are ignored for remat, and will be deleted if they
667 // don't feed a live user after rematerialization completes.
668 if (SnippetCopies.count(Ptr: &MI)) {
669 LLVM_DEBUG(dbgs() << "\tskipping remat snippet copy for " << UseIdx << '\t'
670 << MI);
671 return false;
672 }
673
674 LiveInterval &OrigLI = LIS.getInterval(Reg: Original);
675 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx: UseIdx);
676 assert(OrigVNI && "corrupted sub-interval");
677 MachineInstr *DefMI = LIS.getInstructionFromIndex(index: OrigVNI->def);
678 // This can happen if for two reasons: 1) This could be a phi valno,
679 // or 2) the remat def has already been removed from the original
680 // live interval; this happens if we rematted to all uses, and
681 // then further split one of those live ranges.
682 if (!DefMI) {
683 markValueUsed(LI: &VirtReg, VNI: ParentVNI);
684 LLVM_DEBUG(dbgs() << "\tcannot remat missing def for " << UseIdx << '\t'
685 << MI);
686 return false;
687 }
688
689 LiveRangeEdit::Remat RM(ParentVNI);
690 RM.OrigMI = DefMI;
691 if (!Edit->canRematerializeAt(RM, UseIdx)) {
692 markValueUsed(LI: &VirtReg, VNI: ParentVNI);
693 LLVM_DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI);
694 return false;
695 }
696
697 // If the instruction also writes VirtReg.reg, it had better not require the
698 // same register for uses and defs.
699 if (RI.Tied) {
700 markValueUsed(LI: &VirtReg, VNI: ParentVNI);
701 LLVM_DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << MI);
702 return false;
703 }
704
705 // Before rematerializing into a register for a single instruction, try to
706 // fold a load into the instruction. That avoids allocating a new register.
707 if (RM.OrigMI->canFoldAsLoad() &&
708 (RM.OrigMI->mayLoad() || !hasPhysRegAvailable(MI)) &&
709 foldMemoryOperand(Ops, LoadMI: RM.OrigMI)) {
710 Edit->markRematerialized(ParentVNI: RM.ParentVNI);
711 ++NumFoldedLoads;
712 return true;
713 }
714
715 // If we can't guarantee that we'll be able to actually assign the new vreg,
716 // we can't remat.
717 if (!canGuaranteeAssignmentAfterRemat(VReg: VirtReg.reg(), MI)) {
718 markValueUsed(LI: &VirtReg, VNI: ParentVNI);
719 LLVM_DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI);
720 return false;
721 }
722
723 // Allocate a new register for the remat.
724 Register NewVReg = Edit->createFrom(OldReg: Original);
725
726 // Constrain it to the register class of MI.
727 MRI.constrainRegClass(Reg: NewVReg, RC: MRI.getRegClass(Reg: VirtReg.reg()));
728
729 // Finally we can rematerialize OrigMI before MI.
730 SlotIndex DefIdx =
731 Edit->rematerializeAt(MBB&: *MI.getParent(), MI, DestReg: NewVReg, RM, TRI);
732
733 // We take the DebugLoc from MI, since OrigMI may be attributed to a
734 // different source location.
735 auto *NewMI = LIS.getInstructionFromIndex(index: DefIdx);
736 NewMI->setDebugLoc(MI.getDebugLoc());
737
738 (void)DefIdx;
739 LLVM_DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
740 << *LIS.getInstructionFromIndex(DefIdx));
741
742 // Replace operands
743 for (const auto &OpPair : Ops) {
744 MachineOperand &MO = OpPair.first->getOperand(i: OpPair.second);
745 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg()) {
746 MO.setReg(NewVReg);
747 MO.setIsKill();
748 }
749 }
750 LLVM_DEBUG(dbgs() << "\t " << UseIdx << '\t' << MI << '\n');
751
752 ++NumRemats;
753 return true;
754}
755
756/// reMaterializeAll - Try to rematerialize as many uses as possible,
757/// and trim the live ranges after.
758void InlineSpiller::reMaterializeAll() {
759 UsedValues.clear();
760
761 // Try to remat before all uses of snippets.
762 bool anyRemat = false;
763 for (Register Reg : RegsToSpill) {
764 LiveInterval &LI = LIS.getInterval(Reg);
765 for (MachineInstr &MI : llvm::make_early_inc_range(Range: MRI.reg_bundles(Reg))) {
766 // Debug values are not allowed to affect codegen.
767 if (MI.isDebugValue())
768 continue;
769
770 assert(!MI.isDebugInstr() && "Did not expect to find a use in debug "
771 "instruction that isn't a DBG_VALUE");
772
773 anyRemat |= reMaterializeFor(VirtReg&: LI, MI);
774 }
775 }
776 if (!anyRemat)
777 return;
778
779 // Remove any values that were completely rematted.
780 for (Register Reg : RegsToSpill) {
781 LiveInterval &LI = LIS.getInterval(Reg);
782 for (VNInfo *VNI : LI.vnis()) {
783 if (VNI->isUnused() || VNI->isPHIDef() || UsedValues.count(Ptr: VNI))
784 continue;
785 MachineInstr *MI = LIS.getInstructionFromIndex(index: VNI->def);
786 MI->addRegisterDead(Reg, RegInfo: &TRI);
787 if (!MI->allDefsAreDead())
788 continue;
789 LLVM_DEBUG(dbgs() << "All defs dead: " << *MI);
790 DeadDefs.push_back(Elt: MI);
791 // If MI is a bundle header, also try removing copies inside the bundle,
792 // otherwise the verifier would complain "live range continues after dead
793 // def flag".
794 if (MI->isBundledWithSucc() && !MI->isBundledWithPred()) {
795 MachineBasicBlock::instr_iterator BeginIt = MI->getIterator(),
796 EndIt = MI->getParent()->instr_end();
797 ++BeginIt; // Skip MI that was already handled.
798
799 bool OnlyDeadCopies = true;
800 for (MachineBasicBlock::instr_iterator It = BeginIt;
801 It != EndIt && It->isBundledWithPred(); ++It) {
802
803 auto DestSrc = TII.isCopyInstr(MI: *It);
804 bool IsCopyToDeadReg =
805 DestSrc && DestSrc->Destination->getReg() == Reg;
806 if (!IsCopyToDeadReg) {
807 OnlyDeadCopies = false;
808 break;
809 }
810 }
811 if (OnlyDeadCopies) {
812 for (MachineBasicBlock::instr_iterator It = BeginIt;
813 It != EndIt && It->isBundledWithPred(); ++It) {
814 It->addRegisterDead(Reg, RegInfo: &TRI);
815 LLVM_DEBUG(dbgs() << "All defs dead: " << *It);
816 DeadDefs.push_back(Elt: &*It);
817 }
818 }
819 }
820 }
821 }
822
823 // Eliminate dead code after remat. Note that some snippet copies may be
824 // deleted here.
825 if (DeadDefs.empty())
826 return;
827 LLVM_DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n");
828 Edit->eliminateDeadDefs(Dead&: DeadDefs, RegsBeingSpilled: RegsToSpill);
829
830 // LiveRangeEdit::eliminateDeadDef is used to remove dead define instructions
831 // after rematerialization. To remove a VNI for a vreg from its LiveInterval,
832 // LiveIntervals::removeVRegDefAt is used. However, after non-PHI VNIs are all
833 // removed, PHI VNI are still left in the LiveInterval.
834 // So to get rid of unused reg, we need to check whether it has non-dbg
835 // reference instead of whether it has non-empty interval.
836 unsigned ResultPos = 0;
837 for (Register Reg : RegsToSpill) {
838 if (MRI.reg_nodbg_empty(RegNo: Reg)) {
839 Edit->eraseVirtReg(Reg);
840 RegsReplaced.push_back(Elt: Reg);
841 continue;
842 }
843
844 assert(LIS.hasInterval(Reg) &&
845 (!LIS.getInterval(Reg).empty() || !MRI.reg_nodbg_empty(Reg)) &&
846 "Empty and not used live-range?!");
847
848 RegsToSpill[ResultPos++] = Reg;
849 }
850 RegsToSpill.erase(CS: RegsToSpill.begin() + ResultPos, CE: RegsToSpill.end());
851 LLVM_DEBUG(dbgs() << RegsToSpill.size()
852 << " registers to spill after remat.\n");
853}
854
855//===----------------------------------------------------------------------===//
856// Spilling
857//===----------------------------------------------------------------------===//
858
859/// If MI is a load or store of StackSlot, it can be removed.
860bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, Register Reg) {
861 int FI = 0;
862 Register InstrReg = TII.isLoadFromStackSlot(MI: *MI, FrameIndex&: FI);
863 bool IsLoad = InstrReg.isValid();
864 if (!IsLoad)
865 InstrReg = TII.isStoreToStackSlot(MI: *MI, FrameIndex&: FI);
866
867 // We have a stack access. Is it the right register and slot?
868 if (InstrReg != Reg || FI != StackSlot)
869 return false;
870
871 if (!IsLoad)
872 HSpiller.rmFromMergeableSpills(Spill&: *MI, StackSlot);
873
874 LLVM_DEBUG(dbgs() << "Coalescing stack access: " << *MI);
875 LIS.RemoveMachineInstrFromMaps(MI&: *MI);
876 MI->eraseFromParent();
877
878 if (IsLoad) {
879 ++NumReloadsRemoved;
880 --NumReloads;
881 } else {
882 ++NumSpillsRemoved;
883 --NumSpills;
884 }
885
886 return true;
887}
888
889#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
890LLVM_DUMP_METHOD
891// Dump the range of instructions from B to E with their slot indexes.
892static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B,
893 MachineBasicBlock::iterator E,
894 LiveIntervals const &LIS,
895 const char *const header,
896 Register VReg = Register()) {
897 char NextLine = '\n';
898 char SlotIndent = '\t';
899
900 if (std::next(B) == E) {
901 NextLine = ' ';
902 SlotIndent = ' ';
903 }
904
905 dbgs() << '\t' << header << ": " << NextLine;
906
907 for (MachineBasicBlock::iterator I = B; I != E; ++I) {
908 SlotIndex Idx = LIS.getInstructionIndex(*I).getRegSlot();
909
910 // If a register was passed in and this instruction has it as a
911 // destination that is marked as an early clobber, print the
912 // early-clobber slot index.
913 if (VReg) {
914 MachineOperand *MO = I->findRegisterDefOperand(VReg, /*TRI=*/nullptr);
915 if (MO && MO->isEarlyClobber())
916 Idx = Idx.getRegSlot(true);
917 }
918
919 dbgs() << SlotIndent << Idx << '\t' << *I;
920 }
921}
922#endif
923
924/// foldMemoryOperand - Try folding stack slot references in Ops into their
925/// instructions.
926///
927/// @param Ops Operand indices from AnalyzeVirtRegInBundle().
928/// @param LoadMI Load instruction to use instead of stack slot when non-null.
929/// @return True on success.
930bool InlineSpiller::
931foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops,
932 MachineInstr *LoadMI) {
933 if (Ops.empty())
934 return false;
935 // Don't attempt folding in bundles.
936 MachineInstr *MI = Ops.front().first;
937 if (Ops.back().first != MI || MI->isBundled())
938 return false;
939
940 bool WasCopy = TII.isCopyInstr(MI: *MI).has_value();
941 Register ImpReg;
942
943 // TII::foldMemoryOperand will do what we need here for statepoint
944 // (fold load into use and remove corresponding def). We will replace
945 // uses of removed def with loads (spillAroundUses).
946 // For that to work we need to untie def and use to pass it through
947 // foldMemoryOperand and signal foldPatchpoint that it is allowed to
948 // fold them.
949 bool UntieRegs = MI->getOpcode() == TargetOpcode::STATEPOINT;
950
951 // Spill subregs if the target allows it.
952 // We always want to spill subregs for stackmap/patchpoint pseudos.
953 bool SpillSubRegs = TII.isSubregFoldable() ||
954 MI->getOpcode() == TargetOpcode::STATEPOINT ||
955 MI->getOpcode() == TargetOpcode::PATCHPOINT ||
956 MI->getOpcode() == TargetOpcode::STACKMAP;
957
958 // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
959 // operands.
960 SmallVector<unsigned, 8> FoldOps;
961 for (const auto &OpPair : Ops) {
962 unsigned Idx = OpPair.second;
963 assert(MI == OpPair.first && "Instruction conflict during operand folding");
964 MachineOperand &MO = MI->getOperand(i: Idx);
965
966 // No point restoring an undef read, and we'll produce an invalid live
967 // interval.
968 // TODO: Is this really the correct way to handle undef tied uses?
969 if (MO.isUse() && !MO.readsReg() && !MO.isTied())
970 continue;
971
972 if (MO.isImplicit()) {
973 ImpReg = MO.getReg();
974 continue;
975 }
976
977 if (!SpillSubRegs && MO.getSubReg())
978 return false;
979 // We cannot fold a load instruction into a def.
980 if (LoadMI && MO.isDef())
981 return false;
982 // Tied use operands should not be passed to foldMemoryOperand.
983 if (UntieRegs || !MI->isRegTiedToDefOperand(UseOpIdx: Idx))
984 FoldOps.push_back(Elt: Idx);
985 }
986
987 // If we only have implicit uses, we won't be able to fold that.
988 // Moreover, TargetInstrInfo::foldMemoryOperand will assert if we try!
989 if (FoldOps.empty())
990 return false;
991
992 MachineInstrSpan MIS(MI, MI->getParent());
993
994 SmallVector<std::pair<unsigned, unsigned> > TiedOps;
995 if (UntieRegs)
996 for (unsigned Idx : FoldOps) {
997 MachineOperand &MO = MI->getOperand(i: Idx);
998 if (!MO.isTied())
999 continue;
1000 unsigned Tied = MI->findTiedOperandIdx(OpIdx: Idx);
1001 if (MO.isUse())
1002 TiedOps.emplace_back(Args&: Tied, Args&: Idx);
1003 else {
1004 assert(MO.isDef() && "Tied to not use and def?");
1005 TiedOps.emplace_back(Args&: Idx, Args&: Tied);
1006 }
1007 MI->untieRegOperand(OpIdx: Idx);
1008 }
1009
1010 MachineInstr *FoldMI =
1011 LoadMI ? TII.foldMemoryOperand(MI&: *MI, Ops: FoldOps, LoadMI&: *LoadMI, LIS: &LIS)
1012 : TII.foldMemoryOperand(MI&: *MI, Ops: FoldOps, FI: StackSlot, LIS: &LIS, VRM: &VRM);
1013 if (!FoldMI) {
1014 // Re-tie operands.
1015 for (auto Tied : TiedOps)
1016 MI->tieOperands(DefIdx: Tied.first, UseIdx: Tied.second);
1017 return false;
1018 }
1019
1020 // Remove LIS for any dead defs in the original MI not in FoldMI.
1021 for (MIBundleOperands MO(*MI); MO.isValid(); ++MO) {
1022 if (!MO->isReg())
1023 continue;
1024 Register Reg = MO->getReg();
1025 if (!Reg || Reg.isVirtual() || MRI.isReserved(PhysReg: Reg)) {
1026 continue;
1027 }
1028 // Skip non-Defs, including undef uses and internal reads.
1029 if (MO->isUse())
1030 continue;
1031 PhysRegInfo RI = AnalyzePhysRegInBundle(MI: *FoldMI, Reg, TRI: &TRI);
1032 if (RI.FullyDefined)
1033 continue;
1034 // FoldMI does not define this physreg. Remove the LI segment.
1035 assert(MO->isDead() && "Cannot fold physreg def");
1036 SlotIndex Idx = LIS.getInstructionIndex(Instr: *MI).getRegSlot();
1037 LIS.removePhysRegDefAt(Reg: Reg.asMCReg(), Pos: Idx);
1038 }
1039
1040 int FI;
1041 if (TII.isStoreToStackSlot(MI: *MI, FrameIndex&: FI) &&
1042 HSpiller.rmFromMergeableSpills(Spill&: *MI, StackSlot: FI))
1043 --NumSpills;
1044 LIS.ReplaceMachineInstrInMaps(MI&: *MI, NewMI&: *FoldMI);
1045 // Update the call info.
1046 if (MI->isCandidateForAdditionalCallInfo())
1047 MI->getMF()->moveAdditionalCallInfo(Old: MI, New: FoldMI);
1048
1049 // If we've folded a store into an instruction labelled with debug-info,
1050 // record a substitution from the old operand to the memory operand. Handle
1051 // the simple common case where operand 0 is the one being folded, plus when
1052 // the destination operand is also a tied def. More values could be
1053 // substituted / preserved with more analysis.
1054 if (MI->peekDebugInstrNum() && Ops[0].second == 0) {
1055 // Helper lambda.
1056 auto MakeSubstitution = [this,FoldMI,MI,&Ops]() {
1057 // Substitute old operand zero to the new instructions memory operand.
1058 unsigned OldOperandNum = Ops[0].second;
1059 unsigned NewNum = FoldMI->getDebugInstrNum();
1060 unsigned OldNum = MI->getDebugInstrNum();
1061 MF.makeDebugValueSubstitution({OldNum, OldOperandNum},
1062 {NewNum, MachineFunction::DebugOperandMemNumber});
1063 };
1064
1065 const MachineOperand &Op0 = MI->getOperand(i: Ops[0].second);
1066 if (Ops.size() == 1 && Op0.isDef()) {
1067 MakeSubstitution();
1068 } else if (Ops.size() == 2 && Op0.isDef() && MI->getOperand(i: 1).isTied() &&
1069 Op0.getReg() == MI->getOperand(i: 1).getReg()) {
1070 MakeSubstitution();
1071 }
1072 } else if (MI->peekDebugInstrNum()) {
1073 // This is a debug-labelled instruction, but the operand being folded isn't
1074 // at operand zero. Most likely this means it's a load being folded in.
1075 // Substitute any register defs from operand zero up to the one being
1076 // folded -- past that point, we don't know what the new operand indexes
1077 // will be.
1078 MF.substituteDebugValuesForInst(Old: *MI, New&: *FoldMI, MaxOperand: Ops[0].second);
1079 }
1080
1081 MI->eraseFromParent();
1082
1083 // Insert any new instructions other than FoldMI into the LIS maps.
1084 assert(!MIS.empty() && "Unexpected empty span of instructions!");
1085 for (MachineInstr &MI : MIS)
1086 if (&MI != FoldMI)
1087 LIS.InsertMachineInstrInMaps(MI);
1088
1089 // TII.foldMemoryOperand may have left some implicit operands on the
1090 // instruction. Strip them.
1091 if (ImpReg)
1092 for (unsigned i = FoldMI->getNumOperands(); i; --i) {
1093 MachineOperand &MO = FoldMI->getOperand(i: i - 1);
1094 if (!MO.isReg() || !MO.isImplicit())
1095 break;
1096 if (MO.getReg() == ImpReg)
1097 FoldMI->removeOperand(OpNo: i - 1);
1098 }
1099
1100 LLVM_DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MIS.end(), LIS,
1101 "folded"));
1102
1103 if (!WasCopy)
1104 ++NumFolded;
1105 else if (Ops.front().second == 0) {
1106 ++NumSpills;
1107 // If there is only 1 store instruction is required for spill, add it
1108 // to mergeable list. In X86 AMX, 2 intructions are required to store.
1109 // We disable the merge for this case.
1110 if (std::distance(first: MIS.begin(), last: MIS.end()) <= 1)
1111 HSpiller.addToMergeableSpills(Spill&: *FoldMI, StackSlot, Original);
1112 } else
1113 ++NumReloads;
1114 return true;
1115}
1116
1117void InlineSpiller::insertReload(Register NewVReg,
1118 SlotIndex Idx,
1119 MachineBasicBlock::iterator MI) {
1120 MachineBasicBlock &MBB = *MI->getParent();
1121
1122 MachineInstrSpan MIS(MI, &MBB);
1123 TII.loadRegFromStackSlot(MBB, MI, DestReg: NewVReg, FrameIndex: StackSlot,
1124 RC: MRI.getRegClass(Reg: NewVReg), VReg: Register());
1125
1126 LIS.InsertMachineInstrRangeInMaps(B: MIS.begin(), E: MI);
1127
1128 LLVM_DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MI, LIS, "reload",
1129 NewVReg));
1130 ++NumReloads;
1131}
1132
1133/// Check if \p Def fully defines a VReg with an undefined value.
1134/// If that's the case, that means the value of VReg is actually
1135/// not relevant.
1136static bool isRealSpill(const MachineInstr &Def) {
1137 if (!Def.isImplicitDef())
1138 return true;
1139
1140 // We can say that the VReg defined by Def is undef, only if it is
1141 // fully defined by Def. Otherwise, some of the lanes may not be
1142 // undef and the value of the VReg matters.
1143 return Def.getOperand(i: 0).getSubReg();
1144}
1145
1146/// insertSpill - Insert a spill of NewVReg after MI.
1147void InlineSpiller::insertSpill(Register NewVReg, bool isKill,
1148 MachineBasicBlock::iterator MI) {
1149 // Spill are not terminators, so inserting spills after terminators will
1150 // violate invariants in MachineVerifier.
1151 assert(!MI->isTerminator() && "Inserting a spill after a terminator");
1152 MachineBasicBlock &MBB = *MI->getParent();
1153
1154 MachineInstrSpan MIS(MI, &MBB);
1155 MachineBasicBlock::iterator SpillBefore = std::next(x: MI);
1156 bool IsRealSpill = isRealSpill(Def: *MI);
1157
1158 if (IsRealSpill)
1159 TII.storeRegToStackSlot(MBB, MI: SpillBefore, SrcReg: NewVReg, isKill, FrameIndex: StackSlot,
1160 RC: MRI.getRegClass(Reg: NewVReg), VReg: Register());
1161 else
1162 // Don't spill undef value.
1163 // Anything works for undef, in particular keeping the memory
1164 // uninitialized is a viable option and it saves code size and
1165 // run time.
1166 BuildMI(BB&: MBB, I: SpillBefore, MIMD: MI->getDebugLoc(), MCID: TII.get(Opcode: TargetOpcode::KILL))
1167 .addReg(RegNo: NewVReg, Flags: getKillRegState(B: isKill));
1168
1169 MachineBasicBlock::iterator Spill = std::next(x: MI);
1170 LIS.InsertMachineInstrRangeInMaps(B: Spill, E: MIS.end());
1171 for (const MachineInstr &MI : make_range(x: Spill, y: MIS.end()))
1172 getVDefInterval(MI, LIS);
1173
1174 LLVM_DEBUG(
1175 dumpMachineInstrRangeWithSlotIndex(Spill, MIS.end(), LIS, "spill"));
1176 ++NumSpills;
1177 // If there is only 1 store instruction is required for spill, add it
1178 // to mergeable list. In X86 AMX, 2 intructions are required to store.
1179 // We disable the merge for this case.
1180 if (IsRealSpill && std::distance(first: Spill, last: MIS.end()) <= 1)
1181 HSpiller.addToMergeableSpills(Spill&: *Spill, StackSlot, Original);
1182}
1183
1184/// spillAroundUses - insert spill code around each use of Reg.
1185void InlineSpiller::spillAroundUses(Register Reg) {
1186 LLVM_DEBUG(dbgs() << "spillAroundUses " << printReg(Reg) << '\n');
1187 LiveInterval &OldLI = LIS.getInterval(Reg);
1188
1189 // Iterate over instructions using Reg.
1190 for (MachineInstr &MI : llvm::make_early_inc_range(Range: MRI.reg_bundles(Reg))) {
1191 // Debug values are not allowed to affect codegen.
1192 if (MI.isDebugValue()) {
1193 // Modify DBG_VALUE now that the value is in a spill slot.
1194 MachineBasicBlock *MBB = MI.getParent();
1195 LLVM_DEBUG(dbgs() << "Modifying debug info due to spill:\t" << MI);
1196 buildDbgValueForSpill(BB&: *MBB, I: &MI, Orig: MI, FrameIndex: StackSlot, SpillReg: Reg);
1197 MBB->erase(I: MI);
1198 continue;
1199 }
1200
1201 assert(!MI.isDebugInstr() && "Did not expect to find a use in debug "
1202 "instruction that isn't a DBG_VALUE");
1203
1204 // Ignore copies to/from snippets. We'll delete them.
1205 if (SnippetCopies.count(Ptr: &MI))
1206 continue;
1207
1208 // Stack slot accesses may coalesce away.
1209 if (coalesceStackAccess(MI: &MI, Reg))
1210 continue;
1211
1212 // Analyze instruction.
1213 SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
1214 VirtRegInfo RI = AnalyzeVirtRegInBundle(MI, Reg, Ops: &Ops);
1215
1216 // Find the slot index where this instruction reads and writes OldLI.
1217 // This is usually the def slot, except for tied early clobbers.
1218 SlotIndex Idx = LIS.getInstructionIndex(Instr: MI).getRegSlot();
1219 if (VNInfo *VNI = OldLI.getVNInfoAt(Idx: Idx.getRegSlot(EC: true)))
1220 if (SlotIndex::isSameInstr(A: Idx, B: VNI->def))
1221 Idx = VNI->def;
1222
1223 // Check for a sibling copy.
1224 Register SibReg = isCopyOfBundle(FirstMI: MI, Reg, TII);
1225 if (SibReg && isSibling(Reg: SibReg)) {
1226 // This may actually be a copy between snippets.
1227 if (isRegToSpill(Reg: SibReg)) {
1228 LLVM_DEBUG(dbgs() << "Found new snippet copy: " << MI);
1229 SnippetCopies.insert(Ptr: &MI);
1230 continue;
1231 }
1232 if (RI.Writes) {
1233 if (hoistSpillInsideBB(SpillLI&: OldLI, CopyMI&: MI)) {
1234 // This COPY is now dead, the value is already in the stack slot.
1235 MI.getOperand(i: 0).setIsDead();
1236 DeadDefs.push_back(Elt: &MI);
1237 continue;
1238 }
1239 } else {
1240 // This is a reload for a sib-reg copy. Drop spills downstream.
1241 LiveInterval &SibLI = LIS.getInterval(Reg: SibReg);
1242 eliminateRedundantSpills(SLI&: SibLI, VNI: SibLI.getVNInfoAt(Idx));
1243 // The COPY will fold to a reload below.
1244 }
1245 }
1246
1247 // Attempt to fold memory ops.
1248 if (foldMemoryOperand(Ops))
1249 continue;
1250
1251 // Create a new virtual register for spill/fill.
1252 // FIXME: Infer regclass from instruction alone.
1253 Register NewVReg = Edit->createFrom(OldReg: Reg);
1254
1255 if (RI.Reads)
1256 insertReload(NewVReg, Idx, MI: &MI);
1257
1258 // Rewrite instruction operands.
1259 bool hasLiveDef = false;
1260 for (const auto &OpPair : Ops) {
1261 MachineOperand &MO = OpPair.first->getOperand(i: OpPair.second);
1262 MO.setReg(NewVReg);
1263 if (MO.isUse()) {
1264 if (!OpPair.first->isRegTiedToDefOperand(UseOpIdx: OpPair.second))
1265 MO.setIsKill();
1266 } else {
1267 if (!MO.isDead())
1268 hasLiveDef = true;
1269 }
1270 }
1271 LLVM_DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << MI << '\n');
1272
1273 // FIXME: Use a second vreg if instruction has no tied ops.
1274 if (RI.Writes)
1275 if (hasLiveDef)
1276 insertSpill(NewVReg, isKill: true, MI: &MI);
1277 }
1278}
1279
1280/// spillAll - Spill all registers remaining after rematerialization.
1281void InlineSpiller::spillAll() {
1282 // Update LiveStacks now that we are committed to spilling.
1283 if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
1284 StackSlot = VRM.assignVirt2StackSlot(virtReg: Original);
1285 StackInt = &LSS.getOrCreateInterval(Slot: StackSlot, RC: MRI.getRegClass(Reg: Original));
1286 StackInt->getNextValue(Def: SlotIndex(), VNInfoAllocator&: LSS.getVNInfoAllocator());
1287 } else
1288 StackInt = &LSS.getInterval(Slot: StackSlot);
1289
1290 if (Original != Edit->getReg())
1291 VRM.assignVirt2StackSlot(virtReg: Edit->getReg(), SS: StackSlot);
1292
1293 assert(StackInt->getNumValNums() == 1 && "Bad stack interval values");
1294 for (Register Reg : RegsToSpill)
1295 StackInt->MergeSegmentsInAsValue(RHS: LIS.getInterval(Reg),
1296 LHSValNo: StackInt->getValNumInfo(ValNo: 0));
1297 LLVM_DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n');
1298
1299 // Spill around uses of all RegsToSpill.
1300 for (Register Reg : RegsToSpill) {
1301 spillAroundUses(Reg);
1302 // Assign all of the spilled registers to the slot so that
1303 // LiveDebugVariables knows about these locations later on.
1304 if (VRM.getStackSlot(virtReg: Reg) == VirtRegMap::NO_STACK_SLOT)
1305 VRM.assignVirt2StackSlot(virtReg: Reg, SS: StackSlot);
1306 }
1307
1308 // Hoisted spills may cause dead code.
1309 if (!DeadDefs.empty()) {
1310 LLVM_DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n");
1311 Edit->eliminateDeadDefs(Dead&: DeadDefs, RegsBeingSpilled: RegsToSpill);
1312 }
1313
1314 // Finally delete the SnippetCopies.
1315 for (Register Reg : RegsToSpill) {
1316 for (MachineInstr &MI :
1317 llvm::make_early_inc_range(Range: MRI.reg_instructions(Reg))) {
1318 assert(SnippetCopies.count(&MI) && "Remaining use wasn't a snippet copy");
1319 // FIXME: Do this with a LiveRangeEdit callback.
1320 LIS.getSlotIndexes()->removeSingleMachineInstrFromMaps(MI);
1321 MI.eraseFromBundle();
1322 }
1323 }
1324
1325 // Delete all spilled registers.
1326 for (Register Reg : RegsToSpill)
1327 Edit->eraseVirtReg(Reg);
1328}
1329
1330void InlineSpiller::spill(LiveRangeEdit &edit, AllocationOrder *order) {
1331 ++NumSpilledRanges;
1332 Edit = &edit;
1333 Order = order;
1334 assert(!edit.getReg().isStack() && "Trying to spill a stack slot.");
1335 // Share a stack slot among all descendants of Original.
1336 Original = VRM.getOriginal(VirtReg: edit.getReg());
1337 StackSlot = VRM.getStackSlot(virtReg: Original);
1338 StackInt = nullptr;
1339
1340 LLVM_DEBUG(dbgs() << "Inline spilling "
1341 << TRI.getRegClassName(MRI.getRegClass(edit.getReg()))
1342 << ':' << edit.getParent() << "\nFrom original "
1343 << printReg(Original) << '\n');
1344 assert(edit.getParent().isSpillable() &&
1345 "Attempting to spill already spilled value.");
1346 assert(DeadDefs.empty() && "Previous spill didn't remove dead defs");
1347
1348 collectRegsToSpill();
1349 reMaterializeAll();
1350
1351 // Remat may handle everything.
1352 if (!RegsToSpill.empty())
1353 spillAll();
1354
1355 Edit->calculateRegClassAndHint(MF, VRAI);
1356}
1357
1358/// Optimizations after all the reg selections and spills are done.
1359void InlineSpiller::postOptimization() { HSpiller.hoistAllSpills(); }
1360
1361/// When a spill is inserted, add the spill to MergeableSpills map.
1362void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot,
1363 Register Original) {
1364 BumpPtrAllocator &Allocator = LIS.getVNInfoAllocator();
1365 LiveInterval &OrigLI = LIS.getInterval(Reg: Original);
1366 // save a copy of LiveInterval in StackSlotToOrigLI because the original
1367 // LiveInterval may be cleared after all its references are spilled.
1368
1369 auto [Place, Inserted] = StackSlotToOrigLI.try_emplace(Key: StackSlot);
1370 if (Inserted) {
1371 auto LI = std::make_unique<LiveInterval>(args: OrigLI.reg(), args: OrigLI.weight());
1372 LI->assign(Other: OrigLI, Allocator);
1373 Place->second = std::move(LI);
1374 }
1375
1376 SlotIndex Idx = LIS.getInstructionIndex(Instr: Spill);
1377 VNInfo *OrigVNI = Place->second->getVNInfoAt(Idx: Idx.getRegSlot());
1378 std::pair<int, VNInfo *> MIdx = std::make_pair(x&: StackSlot, y&: OrigVNI);
1379 MergeableSpills[MIdx].insert(Ptr: &Spill);
1380}
1381
1382/// When a spill is removed, remove the spill from MergeableSpills map.
1383/// Return true if the spill is removed successfully.
1384bool HoistSpillHelper::rmFromMergeableSpills(MachineInstr &Spill,
1385 int StackSlot) {
1386 auto It = StackSlotToOrigLI.find(Val: StackSlot);
1387 if (It == StackSlotToOrigLI.end())
1388 return false;
1389 SlotIndex Idx = LIS.getInstructionIndex(Instr: Spill);
1390 VNInfo *OrigVNI = It->second->getVNInfoAt(Idx: Idx.getRegSlot());
1391 std::pair<int, VNInfo *> MIdx = std::make_pair(x&: StackSlot, y&: OrigVNI);
1392 return MergeableSpills[MIdx].erase(Ptr: &Spill);
1393}
1394
1395/// Check BB to see if it is a possible target BB to place a hoisted spill,
1396/// i.e., there should be a living sibling of OrigReg at the insert point.
1397bool HoistSpillHelper::isSpillCandBB(LiveInterval &OrigLI, VNInfo &OrigVNI,
1398 MachineBasicBlock &BB, Register &LiveReg) {
1399 SlotIndex Idx = IPA.getLastInsertPoint(CurLI: OrigLI, MBB: BB);
1400 // The original def could be after the last insert point in the root block,
1401 // we can't hoist to here.
1402 if (Idx < OrigVNI.def) {
1403 // TODO: We could be better here. If LI is not alive in landing pad
1404 // we could hoist spill after LIP.
1405 LLVM_DEBUG(dbgs() << "can't spill in root block - def after LIP\n");
1406 return false;
1407 }
1408 Register OrigReg = OrigLI.reg();
1409 SmallSetVector<Register, 16> &Siblings = Virt2SiblingsMap[OrigReg];
1410 assert(OrigLI.getVNInfoAt(Idx) == &OrigVNI && "Unexpected VNI");
1411
1412 for (const Register &SibReg : Siblings) {
1413 LiveInterval &LI = LIS.getInterval(Reg: SibReg);
1414 if (!LI.getVNInfoAt(Idx))
1415 continue;
1416 // All of the sub-ranges should be alive at the prospective slot index.
1417 // Otherwise, we might risk storing unrelated / compromised values from some
1418 // sub-registers to the spill slot.
1419 if (all_of(Range: LI.subranges(), P: [&](const LiveInterval::SubRange &SR) {
1420 return SR.getVNInfoAt(Idx) != nullptr;
1421 })) {
1422 LiveReg = SibReg;
1423 return true;
1424 }
1425 }
1426 return false;
1427}
1428
1429/// Remove redundant spills in the same BB. Save those redundant spills in
1430/// SpillsToRm, and save the spill to keep and its BB in SpillBBToSpill map.
1431void HoistSpillHelper::rmRedundantSpills(
1432 SmallPtrSet<MachineInstr *, 16> &Spills,
1433 SmallVectorImpl<MachineInstr *> &SpillsToRm,
1434 DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill) {
1435 // For each spill saw, check SpillBBToSpill[] and see if its BB already has
1436 // another spill inside. If a BB contains more than one spill, only keep the
1437 // earlier spill with smaller SlotIndex.
1438 for (auto *const CurrentSpill : Spills) {
1439 MachineBasicBlock *Block = CurrentSpill->getParent();
1440 MachineDomTreeNode *Node = MDT.getNode(BB: Block);
1441 MachineInstr *PrevSpill = SpillBBToSpill[Node];
1442 if (PrevSpill) {
1443 SlotIndex PIdx = LIS.getInstructionIndex(Instr: *PrevSpill);
1444 SlotIndex CIdx = LIS.getInstructionIndex(Instr: *CurrentSpill);
1445 MachineInstr *SpillToRm = (CIdx > PIdx) ? CurrentSpill : PrevSpill;
1446 MachineInstr *SpillToKeep = (CIdx > PIdx) ? PrevSpill : CurrentSpill;
1447 SpillsToRm.push_back(Elt: SpillToRm);
1448 SpillBBToSpill[MDT.getNode(BB: Block)] = SpillToKeep;
1449 } else {
1450 SpillBBToSpill[MDT.getNode(BB: Block)] = CurrentSpill;
1451 }
1452 }
1453 for (auto *const SpillToRm : SpillsToRm)
1454 Spills.erase(Ptr: SpillToRm);
1455}
1456
1457/// Starting from \p Root find a top-down traversal order of the dominator
1458/// tree to visit all basic blocks containing the elements of \p Spills.
1459/// Redundant spills will be found and put into \p SpillsToRm at the same
1460/// time. \p SpillBBToSpill will be populated as part of the process and
1461/// maps a basic block to the first store occurring in the basic block.
1462/// \post SpillsToRm.union(Spills\@post) == Spills\@pre
1463void HoistSpillHelper::getVisitOrders(
1464 MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
1465 SmallVectorImpl<MachineDomTreeNode *> &Orders,
1466 SmallVectorImpl<MachineInstr *> &SpillsToRm,
1467 DenseMap<MachineDomTreeNode *, Register> &SpillsToKeep,
1468 DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill) {
1469 // The set contains all the possible BB nodes to which we may hoist
1470 // original spills.
1471 SmallPtrSet<MachineDomTreeNode *, 8> WorkSet;
1472 // Save the BB nodes on the path from the first BB node containing
1473 // non-redundant spill to the Root node.
1474 SmallPtrSet<MachineDomTreeNode *, 8> NodesOnPath;
1475 // All the spills to be hoisted must originate from a single def instruction
1476 // to the OrigReg. It means the def instruction should dominate all the spills
1477 // to be hoisted. We choose the BB where the def instruction is located as
1478 // the Root.
1479 MachineDomTreeNode *RootIDomNode = MDT[Root]->getIDom();
1480 // For every node on the dominator tree with spill, walk up on the dominator
1481 // tree towards the Root node until it is reached. If there is other node
1482 // containing spill in the middle of the path, the previous spill saw will
1483 // be redundant and the node containing it will be removed. All the nodes on
1484 // the path starting from the first node with non-redundant spill to the Root
1485 // node will be added to the WorkSet, which will contain all the possible
1486 // locations where spills may be hoisted to after the loop below is done.
1487 for (auto *const Spill : Spills) {
1488 MachineBasicBlock *Block = Spill->getParent();
1489 MachineDomTreeNode *Node = MDT[Block];
1490 MachineInstr *SpillToRm = nullptr;
1491 while (Node != RootIDomNode) {
1492 // If Node dominates Block, and it already contains a spill, the spill in
1493 // Block will be redundant.
1494 if (Node != MDT[Block] && SpillBBToSpill[Node]) {
1495 SpillToRm = SpillBBToSpill[MDT[Block]];
1496 break;
1497 /// If we see the Node already in WorkSet, the path from the Node to
1498 /// the Root node must already be traversed by another spill.
1499 /// Then no need to repeat.
1500 } else if (WorkSet.count(Ptr: Node)) {
1501 break;
1502 } else {
1503 NodesOnPath.insert(Ptr: Node);
1504 }
1505 Node = Node->getIDom();
1506 }
1507 if (SpillToRm) {
1508 SpillsToRm.push_back(Elt: SpillToRm);
1509 } else {
1510 // Add a BB containing the original spills to SpillsToKeep -- i.e.,
1511 // set the initial status before hoisting start. The value of BBs
1512 // containing original spills is set to 0, in order to descriminate
1513 // with BBs containing hoisted spills which will be inserted to
1514 // SpillsToKeep later during hoisting.
1515 SpillsToKeep[MDT[Block]] = Register();
1516 WorkSet.insert_range(R&: NodesOnPath);
1517 }
1518 NodesOnPath.clear();
1519 }
1520
1521 // Sort the nodes in WorkSet in top-down order and save the nodes
1522 // in Orders. Orders will be used for hoisting in runHoistSpills.
1523 unsigned idx = 0;
1524 Orders.push_back(Elt: MDT.getNode(BB: Root));
1525 do {
1526 MachineDomTreeNode *Node = Orders[idx++];
1527 for (MachineDomTreeNode *Child : Node->children()) {
1528 if (WorkSet.count(Ptr: Child))
1529 Orders.push_back(Elt: Child);
1530 }
1531 } while (idx != Orders.size());
1532 assert(Orders.size() == WorkSet.size() &&
1533 "Orders have different size with WorkSet");
1534
1535#ifndef NDEBUG
1536 LLVM_DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n");
1537 SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin();
1538 for (; RIt != Orders.rend(); RIt++)
1539 LLVM_DEBUG(dbgs() << "BB" << (*RIt)->getBlock()->getNumber() << ",");
1540 LLVM_DEBUG(dbgs() << "\n");
1541#endif
1542}
1543
1544/// Try to hoist spills according to BB hotness. The spills to removed will
1545/// be saved in \p SpillsToRm. The spills to be inserted will be saved in
1546/// \p SpillsToIns.
1547void HoistSpillHelper::runHoistSpills(
1548 LiveInterval &OrigLI, VNInfo &OrigVNI,
1549 SmallPtrSet<MachineInstr *, 16> &Spills,
1550 SmallVectorImpl<MachineInstr *> &SpillsToRm,
1551 DenseMap<MachineBasicBlock *, Register> &SpillsToIns) {
1552 // Visit order of dominator tree nodes.
1553 SmallVector<MachineDomTreeNode *, 32> Orders;
1554 // SpillsToKeep contains all the nodes where spills are to be inserted
1555 // during hoisting. If the spill to be inserted is an original spill
1556 // (not a hoisted one), the value of the map entry is 0. If the spill
1557 // is a hoisted spill, the value of the map entry is the VReg to be used
1558 // as the source of the spill.
1559 DenseMap<MachineDomTreeNode *, Register> SpillsToKeep;
1560 // Map from BB to the first spill inside of it.
1561 DenseMap<MachineDomTreeNode *, MachineInstr *> SpillBBToSpill;
1562
1563 rmRedundantSpills(Spills, SpillsToRm, SpillBBToSpill);
1564
1565 MachineBasicBlock *Root = LIS.getMBBFromIndex(index: OrigVNI.def);
1566 getVisitOrders(Root, Spills, Orders, SpillsToRm, SpillsToKeep,
1567 SpillBBToSpill);
1568
1569 // SpillsInSubTreeMap keeps the map from a dom tree node to a pair of
1570 // nodes set and the cost of all the spills inside those nodes.
1571 // The nodes set are the locations where spills are to be inserted
1572 // in the subtree of current node.
1573 using NodesCostPair =
1574 std::pair<SmallPtrSet<MachineDomTreeNode *, 16>, BlockFrequency>;
1575 DenseMap<MachineDomTreeNode *, NodesCostPair> SpillsInSubTreeMap;
1576
1577 // Iterate Orders set in reverse order, which will be a bottom-up order
1578 // in the dominator tree. Once we visit a dom tree node, we know its
1579 // children have already been visited and the spill locations in the
1580 // subtrees of all the children have been determined.
1581 SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin();
1582 for (; RIt != Orders.rend(); RIt++) {
1583 MachineBasicBlock *Block = (*RIt)->getBlock();
1584
1585 // If Block contains an original spill, simply continue.
1586 if (auto It = SpillsToKeep.find(Val: *RIt);
1587 It != SpillsToKeep.end() && !It->second) {
1588 auto &SIt = SpillsInSubTreeMap[*RIt];
1589 SIt.first.insert(Ptr: *RIt);
1590 // Sit.second contains the cost of spill.
1591 SIt.second = MBFI.getBlockFreq(MBB: Block);
1592 continue;
1593 }
1594
1595 // Collect spills in subtree of current node (*RIt) to
1596 // SpillsInSubTreeMap[*RIt].first.
1597 for (MachineDomTreeNode *Child : (*RIt)->children()) {
1598 if (!SpillsInSubTreeMap.contains(Val: Child))
1599 continue;
1600 // The stmt:
1601 // "auto &[SpillsInSubTree, SubTreeCost] = SpillsInSubTreeMap[*RIt]"
1602 // below should be placed before getting the begin and end iterators of
1603 // SpillsInSubTreeMap[Child].first, or else the iterators may be
1604 // invalidated when SpillsInSubTreeMap[*RIt] is seen the first time
1605 // and the map grows and then the original buckets in the map are moved.
1606 auto &[SpillsInSubTree, SubTreeCost] = SpillsInSubTreeMap[*RIt];
1607 auto ChildIt = SpillsInSubTreeMap.find(Val: Child);
1608 SubTreeCost += ChildIt->second.second;
1609 auto BI = ChildIt->second.first.begin();
1610 auto EI = ChildIt->second.first.end();
1611 SpillsInSubTree.insert(I: BI, E: EI);
1612 SpillsInSubTreeMap.erase(I: ChildIt);
1613 }
1614
1615 auto &[SpillsInSubTree, SubTreeCost] = SpillsInSubTreeMap[*RIt];
1616 // No spills in subtree, simply continue.
1617 if (SpillsInSubTree.empty())
1618 continue;
1619
1620 // Check whether Block is a possible candidate to insert spill.
1621 Register LiveReg;
1622 if (!isSpillCandBB(OrigLI, OrigVNI, BB&: *Block, LiveReg))
1623 continue;
1624
1625 // If there are multiple spills that could be merged, bias a little
1626 // to hoist the spill.
1627 BranchProbability MarginProb = (SpillsInSubTree.size() > 1)
1628 ? BranchProbability(9, 10)
1629 : BranchProbability(1, 1);
1630 if (SubTreeCost > MBFI.getBlockFreq(MBB: Block) * MarginProb) {
1631 // Hoist: Move spills to current Block.
1632 for (auto *const SpillBB : SpillsInSubTree) {
1633 // When SpillBB is a BB contains original spill, insert the spill
1634 // to SpillsToRm.
1635 if (auto It = SpillsToKeep.find(Val: SpillBB);
1636 It != SpillsToKeep.end() && !It->second) {
1637 MachineInstr *SpillToRm = SpillBBToSpill[SpillBB];
1638 SpillsToRm.push_back(Elt: SpillToRm);
1639 }
1640 // SpillBB will not contain spill anymore, remove it from SpillsToKeep.
1641 SpillsToKeep.erase(Val: SpillBB);
1642 }
1643 // Current Block is the BB containing the new hoisted spill. Add it to
1644 // SpillsToKeep. LiveReg is the source of the new spill.
1645 SpillsToKeep[*RIt] = LiveReg;
1646 LLVM_DEBUG({
1647 dbgs() << "spills in BB: ";
1648 for (const auto Rspill : SpillsInSubTree)
1649 dbgs() << Rspill->getBlock()->getNumber() << " ";
1650 dbgs() << "were promoted to BB" << (*RIt)->getBlock()->getNumber()
1651 << "\n";
1652 });
1653 SpillsInSubTree.clear();
1654 SpillsInSubTree.insert(Ptr: *RIt);
1655 SubTreeCost = MBFI.getBlockFreq(MBB: Block);
1656 }
1657 }
1658 // For spills in SpillsToKeep with LiveReg set (i.e., not original spill),
1659 // save them to SpillsToIns.
1660 for (const auto &Ent : SpillsToKeep) {
1661 if (Ent.second)
1662 SpillsToIns[Ent.first->getBlock()] = Ent.second;
1663 }
1664}
1665
1666/// For spills with equal values, remove redundant spills and hoist those left
1667/// to less hot spots.
1668///
1669/// Spills with equal values will be collected into the same set in
1670/// MergeableSpills when spill is inserted. These equal spills are originated
1671/// from the same defining instruction and are dominated by the instruction.
1672/// Before hoisting all the equal spills, redundant spills inside in the same
1673/// BB are first marked to be deleted. Then starting from the spills left, walk
1674/// up on the dominator tree towards the Root node where the define instruction
1675/// is located, mark the dominated spills to be deleted along the way and
1676/// collect the BB nodes on the path from non-dominated spills to the define
1677/// instruction into a WorkSet. The nodes in WorkSet are the candidate places
1678/// where we are considering to hoist the spills. We iterate the WorkSet in
1679/// bottom-up order, and for each node, we will decide whether to hoist spills
1680/// inside its subtree to that node. In this way, we can get benefit locally
1681/// even if hoisting all the equal spills to one cold place is impossible.
1682void HoistSpillHelper::hoistAllSpills() {
1683 SmallVector<Register, 4> NewVRegs;
1684 LiveRangeEdit Edit(nullptr, NewVRegs, MF, LIS, &VRM, this);
1685
1686 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
1687 Register Reg = Register::index2VirtReg(Index: i);
1688 Register Original = VRM.getPreSplitReg(virtReg: Reg);
1689 if (!MRI.def_empty(RegNo: Reg) && Original.isValid())
1690 Virt2SiblingsMap[Original].insert(X: Reg);
1691 }
1692
1693 // Each entry in MergeableSpills contains a spill set with equal values.
1694 for (auto &Ent : MergeableSpills) {
1695 int Slot = Ent.first.first;
1696 LiveInterval &OrigLI = *StackSlotToOrigLI[Slot];
1697 VNInfo *OrigVNI = Ent.first.second;
1698 SmallPtrSet<MachineInstr *, 16> &EqValSpills = Ent.second;
1699 if (Ent.second.empty())
1700 continue;
1701
1702 LLVM_DEBUG({
1703 dbgs() << "\nFor Slot" << Slot << " and VN" << OrigVNI->id << ":\n"
1704 << "Equal spills in BB: ";
1705 for (const auto spill : EqValSpills)
1706 dbgs() << spill->getParent()->getNumber() << " ";
1707 dbgs() << "\n";
1708 });
1709
1710 // SpillsToRm is the spill set to be removed from EqValSpills.
1711 SmallVector<MachineInstr *, 16> SpillsToRm;
1712 // SpillsToIns is the spill set to be newly inserted after hoisting.
1713 DenseMap<MachineBasicBlock *, Register> SpillsToIns;
1714
1715 runHoistSpills(OrigLI, OrigVNI&: *OrigVNI, Spills&: EqValSpills, SpillsToRm, SpillsToIns);
1716
1717 LLVM_DEBUG({
1718 dbgs() << "Finally inserted spills in BB: ";
1719 for (const auto &Ispill : SpillsToIns)
1720 dbgs() << Ispill.first->getNumber() << " ";
1721 dbgs() << "\nFinally removed spills in BB: ";
1722 for (const auto Rspill : SpillsToRm)
1723 dbgs() << Rspill->getParent()->getNumber() << " ";
1724 dbgs() << "\n";
1725 });
1726
1727 // Stack live range update.
1728 LiveInterval &StackIntvl = LSS.getInterval(Slot);
1729 if (!SpillsToIns.empty() || !SpillsToRm.empty())
1730 StackIntvl.MergeValueInAsValue(RHS: OrigLI, RHSValNo: OrigVNI,
1731 LHSValNo: StackIntvl.getValNumInfo(ValNo: 0));
1732
1733 // Insert hoisted spills.
1734 for (auto const &Insert : SpillsToIns) {
1735 MachineBasicBlock *BB = Insert.first;
1736 Register LiveReg = Insert.second;
1737 MachineBasicBlock::iterator MII = IPA.getLastInsertPointIter(CurLI: OrigLI, MBB&: *BB);
1738 MachineInstrSpan MIS(MII, BB);
1739 TII.storeRegToStackSlot(MBB&: *BB, MI: MII, SrcReg: LiveReg, isKill: false, FrameIndex: Slot,
1740 RC: MRI.getRegClass(Reg: LiveReg), VReg: Register());
1741 LIS.InsertMachineInstrRangeInMaps(B: MIS.begin(), E: MII);
1742 for (const MachineInstr &MI : make_range(x: MIS.begin(), y: MII))
1743 getVDefInterval(MI, LIS);
1744 ++NumSpills;
1745 }
1746
1747 // Remove redundant spills or change them to dead instructions.
1748 NumSpills -= SpillsToRm.size();
1749 for (auto *const RMEnt : SpillsToRm) {
1750 RMEnt->setDesc(TII.get(Opcode: TargetOpcode::KILL));
1751 for (unsigned i = RMEnt->getNumOperands(); i; --i) {
1752 MachineOperand &MO = RMEnt->getOperand(i: i - 1);
1753 if (MO.isReg() && MO.isImplicit() && MO.isDef() && !MO.isDead())
1754 RMEnt->removeOperand(OpNo: i - 1);
1755 }
1756 }
1757 Edit.eliminateDeadDefs(Dead&: SpillsToRm, RegsBeingSpilled: {});
1758 }
1759}
1760
1761/// Called before a virtual register is erased from LiveIntervals.
1762/// Forcibly remove the register from LiveRegMatrix before it's deleted,
1763/// preventing dangling pointers.
1764bool HoistSpillHelper::LRE_CanEraseVirtReg(Register VirtReg) {
1765 if (Matrix && VRM.hasPhys(virtReg: VirtReg)) {
1766 const LiveInterval &LI = LIS.getInterval(Reg: VirtReg);
1767 Matrix->unassign(VirtReg: LI, /*ClearAllReferencingSegments=*/true);
1768 }
1769 return true; // Allow deletion to proceed
1770}
1771
1772/// For VirtReg clone, the \p New register should have the same physreg or
1773/// stackslot as the \p old register.
1774void HoistSpillHelper::LRE_DidCloneVirtReg(Register New, Register Old) {
1775 if (VRM.hasPhys(virtReg: Old))
1776 VRM.assignVirt2Phys(virtReg: New, physReg: VRM.getPhys(virtReg: Old));
1777 else if (VRM.getStackSlot(virtReg: Old) != VirtRegMap::NO_STACK_SLOT)
1778 VRM.assignVirt2StackSlot(virtReg: New, SS: VRM.getStackSlot(virtReg: Old));
1779 else
1780 llvm_unreachable("VReg should be assigned either physreg or stackslot");
1781 if (VRM.hasShape(virtReg: Old))
1782 VRM.assignVirt2Shape(virtReg: New, shape: VRM.getShape(virtReg: Old));
1783}
1784