1//===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implementation of the MachineRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/MachineRegisterInfo.h"
14#include "llvm/ADT/SmallVector.h"
15#include "llvm/ADT/iterator_range.h"
16#include "llvm/CodeGen/MachineBasicBlock.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineInstr.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineOperand.h"
21#include "llvm/CodeGen/Register.h"
22#include "llvm/CodeGen/TargetInstrInfo.h"
23#include "llvm/CodeGen/TargetRegisterInfo.h"
24#include "llvm/CodeGen/TargetSubtargetInfo.h"
25#include "llvm/Config/llvm-config.h"
26#include "llvm/IR/Attributes.h"
27#include "llvm/IR/DebugLoc.h"
28#include "llvm/IR/Function.h"
29#include "llvm/MC/MCRegisterInfo.h"
30#include "llvm/Support/Casting.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/Compiler.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include <cassert>
36
37using namespace llvm;
38
39static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
40 cl::init(Val: true), cl::desc("Enable subregister liveness tracking."));
41
42// Pin the vtable to this file.
43void MachineRegisterInfo::Delegate::anchor() {}
44
45MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
46 : MF(MF),
47 TracksSubRegLiveness(EnableSubRegLiveness.getNumOccurrences()
48 ? EnableSubRegLiveness
49 : MF->getSubtarget().enableSubRegLiveness()) {
50 unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
51 VRegInfo.reserve(S: 256);
52 UsedPhysRegMask.resize(N: NumRegs);
53 PhysRegUseDefLists.reset(p: new MachineOperand*[NumRegs]());
54 TheDelegates.clear();
55}
56
57/// setRegClass - Set the register class of the specified virtual register.
58///
59void
60MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) {
61 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
62 VRegInfo[Reg].first = RC;
63}
64
65void MachineRegisterInfo::setRegBank(Register Reg,
66 const RegisterBank &RegBank) {
67 VRegInfo[Reg].first = &RegBank;
68}
69
70static const TargetRegisterClass *
71constrainRegClass(MachineRegisterInfo &MRI, Register Reg,
72 const TargetRegisterClass *OldRC,
73 const TargetRegisterClass *RC, unsigned MinNumRegs) {
74 if (OldRC == RC)
75 return RC;
76 const TargetRegisterClass *NewRC =
77 MRI.getTargetRegisterInfo()->getCommonSubClass(A: OldRC, B: RC);
78 if (!NewRC || NewRC == OldRC)
79 return NewRC;
80 if (NewRC->getNumRegs() < MinNumRegs)
81 return nullptr;
82 MRI.setRegClass(Reg, RC: NewRC);
83 return NewRC;
84}
85
86const TargetRegisterClass *MachineRegisterInfo::constrainRegClass(
87 Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) {
88 return ::constrainRegClass(MRI&: *this, Reg, OldRC: getRegClass(Reg), RC, MinNumRegs);
89}
90
91bool
92MachineRegisterInfo::constrainRegAttrs(Register Reg,
93 Register ConstrainingReg,
94 unsigned MinNumRegs) {
95 const LLT RegTy = getType(Reg);
96 const LLT ConstrainingRegTy = getType(Reg: ConstrainingReg);
97 if (RegTy.isValid() && ConstrainingRegTy.isValid() &&
98 RegTy != ConstrainingRegTy)
99 return false;
100 const auto &ConstrainingRegCB = getRegClassOrRegBank(Reg: ConstrainingReg);
101 if (!ConstrainingRegCB.isNull()) {
102 const auto &RegCB = getRegClassOrRegBank(Reg);
103 if (RegCB.isNull())
104 setRegClassOrRegBank(Reg, RCOrRB: ConstrainingRegCB);
105 else if (isa<const TargetRegisterClass *>(Val: RegCB) !=
106 isa<const TargetRegisterClass *>(Val: ConstrainingRegCB))
107 return false;
108 else if (isa<const TargetRegisterClass *>(Val: RegCB)) {
109 if (!::constrainRegClass(
110 MRI&: *this, Reg, OldRC: cast<const TargetRegisterClass *>(Val: RegCB),
111 RC: cast<const TargetRegisterClass *>(Val: ConstrainingRegCB), MinNumRegs))
112 return false;
113 } else if (RegCB != ConstrainingRegCB)
114 return false;
115 }
116 if (ConstrainingRegTy.isValid())
117 setType(VReg: Reg, Ty: ConstrainingRegTy);
118 return true;
119}
120
121bool
122MachineRegisterInfo::recomputeRegClass(Register Reg) {
123 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
124 const TargetRegisterClass *OldRC = getRegClass(Reg);
125 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
126 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(RC: OldRC, *MF);
127
128 // Stop early if there is no room to grow.
129 if (NewRC == OldRC)
130 return false;
131
132 // Accumulate constraints from all uses.
133 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
134 // Apply the effect of the given operand to NewRC.
135 MachineInstr *MI = MO.getParent();
136 unsigned OpNo = &MO - &MI->getOperand(i: 0);
137 NewRC = MI->getRegClassConstraintEffect(OpIdx: OpNo, CurRC: NewRC, TII, TRI);
138 if (!NewRC || NewRC == OldRC)
139 return false;
140 }
141 setRegClass(Reg, RC: NewRC);
142 return true;
143}
144
145Register MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) {
146 Register Reg = Register::index2VirtReg(Index: getNumVirtRegs());
147 VRegInfo.grow(N: Reg);
148 insertVRegByName(Name, Reg);
149 return Reg;
150}
151
152/// createVirtualRegister - Create and return a new virtual register in the
153/// function with the specified register class.
154///
155Register
156MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass,
157 StringRef Name) {
158 assert(RegClass && "Cannot create register without RegClass!");
159 assert(RegClass->isAllocatable() &&
160 "Virtual register RegClass must be allocatable.");
161
162 // New virtual register number.
163 Register Reg = createIncompleteVirtualRegister(Name);
164 VRegInfo[Reg].first = RegClass;
165 noteNewVirtualRegister(Reg);
166 return Reg;
167}
168
169Register MachineRegisterInfo::createVirtualRegister(VRegAttrs RegAttr,
170 StringRef Name) {
171 Register Reg = createIncompleteVirtualRegister(Name);
172 VRegInfo[Reg].first = RegAttr.RCOrRB;
173 setType(VReg: Reg, Ty: RegAttr.Ty);
174 noteNewVirtualRegister(Reg);
175 return Reg;
176}
177
178Register MachineRegisterInfo::cloneVirtualRegister(Register VReg,
179 StringRef Name) {
180 Register Reg = createIncompleteVirtualRegister(Name);
181 VRegInfo[Reg].first = VRegInfo[VReg].first;
182 setType(VReg: Reg, Ty: getType(Reg: VReg));
183 noteCloneVirtualRegister(NewReg: Reg, SrcReg: VReg);
184 return Reg;
185}
186
187void MachineRegisterInfo::setType(Register VReg, LLT Ty) {
188 VRegToType.grow(N: VReg);
189 VRegToType[VReg] = Ty;
190}
191
192Register
193MachineRegisterInfo::createGenericVirtualRegister(LLT Ty, StringRef Name) {
194 // New virtual register number.
195 Register Reg = createIncompleteVirtualRegister(Name);
196 // FIXME: Should we use a dummy register class?
197 VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
198 setType(VReg: Reg, Ty);
199 noteNewVirtualRegister(Reg);
200 return Reg;
201}
202
203void MachineRegisterInfo::clearVirtRegTypes() { VRegToType.clear(); }
204
205/// clearVirtRegs - Remove all virtual registers (after physreg assignment).
206void MachineRegisterInfo::clearVirtRegs() {
207#ifndef NDEBUG
208 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
209 Register Reg = Register::index2VirtReg(i);
210 if (!VRegInfo[Reg].second)
211 continue;
212 verifyUseList(Reg);
213 errs() << "Remaining virtual register "
214 << printReg(Reg, getTargetRegisterInfo()) << "...\n";
215 for (MachineInstr &MI : reg_instructions(Reg))
216 errs() << "...in instruction: " << MI << "\n";
217 std::abort();
218 }
219#endif
220 VRegInfo.clear();
221 for (auto &I : LiveIns)
222 I.second = 0;
223}
224
225void MachineRegisterInfo::verifyUseList(Register Reg) const {
226#ifndef NDEBUG
227 bool Valid = true;
228 for (MachineOperand &M : reg_operands(Reg)) {
229 MachineOperand *MO = &M;
230 MachineInstr *MI = MO->getParent();
231 if (!MI) {
232 errs() << printReg(Reg, getTargetRegisterInfo())
233 << " use list MachineOperand " << MO
234 << " has no parent instruction.\n";
235 Valid = false;
236 continue;
237 }
238 MachineOperand *MO0 = &MI->getOperand(0);
239 unsigned NumOps = MI->getNumOperands();
240 if (!(MO >= MO0 && MO < MO0+NumOps)) {
241 errs() << printReg(Reg, getTargetRegisterInfo())
242 << " use list MachineOperand " << MO
243 << " doesn't belong to parent MI: " << *MI;
244 Valid = false;
245 }
246 if (!MO->isReg()) {
247 errs() << printReg(Reg, getTargetRegisterInfo())
248 << " MachineOperand " << MO << ": " << *MO
249 << " is not a register\n";
250 Valid = false;
251 }
252 if (MO->getReg() != Reg) {
253 errs() << printReg(Reg, getTargetRegisterInfo())
254 << " use-list MachineOperand " << MO << ": "
255 << *MO << " is the wrong register\n";
256 Valid = false;
257 }
258 }
259 assert(Valid && "Invalid use list");
260#endif
261}
262
263void MachineRegisterInfo::verifyUseLists() const {
264#ifndef NDEBUG
265 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
266 verifyUseList(Register::index2VirtReg(i));
267 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
268 verifyUseList(i);
269#endif
270}
271
272/// Add MO to the linked list of operands for its register.
273void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
274 assert(!MO->isOnRegUseList() && "Already on list");
275 MachineOperand *&HeadRef = getRegUseDefListHead(RegNo: MO->getReg());
276 MachineOperand *const Head = HeadRef;
277
278 // Head points to the first list element.
279 // Next is NULL on the last list element.
280 // Prev pointers are circular, so Head->Prev == Last.
281
282 // Head is NULL for an empty list.
283 if (!Head) {
284 MO->Contents.Reg.Prev = MO;
285 MO->Contents.Reg.Next = nullptr;
286 HeadRef = MO;
287 return;
288 }
289 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
290
291 // Insert MO between Last and Head in the circular Prev chain.
292 MachineOperand *Last = Head->Contents.Reg.Prev;
293 assert(Last && "Inconsistent use list");
294 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
295 Head->Contents.Reg.Prev = MO;
296 MO->Contents.Reg.Prev = Last;
297
298 // Def operands always precede uses. This allows def_iterator to stop early.
299 // Insert def operands at the front, and use operands at the back.
300 if (MO->isDef()) {
301 // Insert def at the front.
302 MO->Contents.Reg.Next = Head;
303 HeadRef = MO;
304 } else {
305 // Insert use at the end.
306 MO->Contents.Reg.Next = nullptr;
307 Last->Contents.Reg.Next = MO;
308 }
309}
310
311/// Remove MO from its use-def list.
312void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
313 assert(MO->isOnRegUseList() && "Operand not on use list");
314 MachineOperand *&HeadRef = getRegUseDefListHead(RegNo: MO->getReg());
315 MachineOperand *const Head = HeadRef;
316 assert(Head && "List already empty");
317
318 // Unlink this from the doubly linked list of operands.
319 MachineOperand *Next = MO->Contents.Reg.Next;
320 MachineOperand *Prev = MO->Contents.Reg.Prev;
321
322 // Prev links are circular, next link is NULL instead of looping back to Head.
323 if (MO == Head)
324 HeadRef = Next;
325 else
326 Prev->Contents.Reg.Next = Next;
327
328 (Next ? Next : Head)->Contents.Reg.Prev = Prev;
329
330 MO->Contents.Reg.Prev = nullptr;
331 MO->Contents.Reg.Next = nullptr;
332}
333
334/// Move NumOps operands from Src to Dst, updating use-def lists as needed.
335///
336/// The Dst range is assumed to be uninitialized memory. (Or it may contain
337/// operands that won't be destroyed, which is OK because the MO destructor is
338/// trivial anyway).
339///
340/// The Src and Dst ranges may overlap.
341void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
342 MachineOperand *Src,
343 unsigned NumOps) {
344 assert(Src != Dst && NumOps && "Noop moveOperands");
345
346 // Copy backwards if Dst is within the Src range.
347 int Stride = 1;
348 if (Dst >= Src && Dst < Src + NumOps) {
349 Stride = -1;
350 Dst += NumOps - 1;
351 Src += NumOps - 1;
352 }
353
354 // Copy one operand at a time.
355 do {
356 new (Dst) MachineOperand(*Src);
357
358 // Dst takes Src's place in the use-def chain.
359 if (Src->isReg()) {
360 MachineOperand *&Head = getRegUseDefListHead(RegNo: Src->getReg());
361 MachineOperand *Prev = Src->Contents.Reg.Prev;
362 MachineOperand *Next = Src->Contents.Reg.Next;
363 assert(Head && "List empty, but operand is chained");
364 assert(Prev && "Operand was not on use-def list");
365
366 // Prev links are circular, next link is NULL instead of looping back to
367 // Head.
368 if (Src == Head)
369 Head = Dst;
370 else
371 Prev->Contents.Reg.Next = Dst;
372
373 // Update Prev pointer. This also works when Src was pointing to itself
374 // in a 1-element list. In that case Head == Dst.
375 (Next ? Next : Head)->Contents.Reg.Prev = Dst;
376 }
377
378 Dst += Stride;
379 Src += Stride;
380 } while (--NumOps);
381}
382
383/// replaceRegWith - Replace all instances of FromReg with ToReg in the
384/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
385/// except that it also changes any definitions of the register as well.
386/// If ToReg is a physical register we apply the sub register to obtain the
387/// final/proper physical register.
388void MachineRegisterInfo::replaceRegWith(Register FromReg, Register ToReg) {
389 assert(FromReg != ToReg && "Cannot replace a reg with itself");
390
391 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
392
393 // TODO: This could be more efficient by bulk changing the operands.
394 for (MachineOperand &O : llvm::make_early_inc_range(Range: reg_operands(Reg: FromReg))) {
395 if (ToReg.isPhysical()) {
396 O.substPhysReg(Reg: ToReg, *TRI);
397 } else {
398 O.setReg(ToReg);
399 }
400 }
401}
402
403/// getVRegDef - Return the machine instr that defines the specified virtual
404/// register or null if none is found. This assumes that the code is in SSA
405/// form, so there should only be one definition.
406MachineInstr *MachineRegisterInfo::getVRegDef(Register Reg) const {
407 // Since we are in SSA form, we can use the first definition.
408 def_instr_iterator I = def_instr_begin(RegNo: Reg);
409 if (I == def_instr_end())
410 return nullptr;
411 assert(std::next(I) == def_instr_end() &&
412 "getVRegDef assumes at most one definition");
413 return &*I;
414}
415
416/// getUniqueVRegDef - Return the unique machine instr that defines the
417/// specified virtual register or null if none is found. If there are
418/// multiple definitions or no definition, return null.
419MachineInstr *MachineRegisterInfo::getUniqueVRegDef(Register Reg) const {
420 if (def_empty(RegNo: Reg)) return nullptr;
421 def_instr_iterator I = def_instr_begin(RegNo: Reg);
422 if (std::next(x: I) != def_instr_end())
423 return nullptr;
424 return &*I;
425}
426
427bool MachineRegisterInfo::hasOneNonDBGUse(Register RegNo) const {
428 return hasSingleElement(C: use_nodbg_operands(Reg: RegNo));
429}
430
431bool MachineRegisterInfo::hasOneNonDBGUser(Register RegNo) const {
432 return hasSingleElement(C: use_nodbg_instructions(Reg: RegNo));
433}
434
435MachineOperand *MachineRegisterInfo::getOneNonDBGUse(Register RegNo) const {
436 auto RegNoDbgUses = use_nodbg_operands(Reg: RegNo);
437 return hasSingleElement(C&: RegNoDbgUses) ? &*RegNoDbgUses.begin() : nullptr;
438}
439
440MachineInstr *MachineRegisterInfo::getOneNonDBGUser(Register RegNo) const {
441 auto RegNoDbgUsers = use_nodbg_instructions(Reg: RegNo);
442 return hasSingleElement(C&: RegNoDbgUsers) ? &*RegNoDbgUsers.begin() : nullptr;
443}
444
445bool MachineRegisterInfo::hasAtMostUserInstrs(Register Reg,
446 unsigned MaxUsers) const {
447 return hasNItemsOrLess(Begin: use_instr_nodbg_begin(RegNo: Reg), End: use_instr_nodbg_end(),
448 N: MaxUsers);
449}
450
451/// clearKillFlags - Iterate over all the uses of the given register and
452/// clear the kill flag from the MachineOperand. This function is used by
453/// optimization passes which extend register lifetimes and need only
454/// preserve conservative kill flag information.
455void MachineRegisterInfo::clearKillFlags(Register Reg) const {
456 for (MachineOperand &MO : use_operands(Reg))
457 MO.setIsKill(false);
458}
459
460bool MachineRegisterInfo::isLiveIn(Register Reg) const {
461 for (const std::pair<MCRegister, Register> &LI : liveins())
462 if ((Register)LI.first == Reg || LI.second == Reg)
463 return true;
464 return false;
465}
466
467/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
468/// corresponding live-in physical register.
469MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const {
470 for (const std::pair<MCRegister, Register> &LI : liveins())
471 if (LI.second == VReg)
472 return LI.first;
473 return MCRegister();
474}
475
476/// getLiveInVirtReg - If PReg is a live-in physical register, return the
477/// corresponding live-in physical register.
478Register MachineRegisterInfo::getLiveInVirtReg(MCRegister PReg) const {
479 for (const std::pair<MCRegister, Register> &LI : liveins())
480 if (LI.first == PReg)
481 return LI.second;
482 return Register();
483}
484
485/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
486/// into the given entry block.
487void
488MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
489 const TargetRegisterInfo &TRI,
490 const TargetInstrInfo &TII) {
491 // Emit the copies into the top of the block.
492 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
493 if (LiveIns[i].second) {
494 if (use_nodbg_empty(RegNo: LiveIns[i].second)) {
495 // The livein has no non-dbg uses. Drop it.
496 //
497 // It would be preferable to have isel avoid creating live-in
498 // records for unused arguments in the first place, but it's
499 // complicated by the debug info code for arguments.
500 LiveIns.erase(position: LiveIns.begin() + i);
501 --i; --e;
502 } else {
503 // Emit a copy.
504 BuildMI(BB&: *EntryMBB, I: EntryMBB->begin(), MIMD: DebugLoc(),
505 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: LiveIns[i].second)
506 .addReg(RegNo: LiveIns[i].first);
507
508 // Add the register to the entry block live-in set.
509 EntryMBB->addLiveIn(PhysReg: LiveIns[i].first);
510 }
511 } else {
512 // Add the register to the entry block live-in set.
513 EntryMBB->addLiveIn(PhysReg: LiveIns[i].first);
514 }
515}
516
517LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(Register Reg) const {
518 // Lane masks are only defined for vregs.
519 assert(Reg.isVirtual());
520 const TargetRegisterClass &TRC = *getRegClass(Reg);
521 return TRC.getLaneMask();
522}
523
524#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
525LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(Register Reg) const {
526 for (MachineInstr &I : use_instructions(Reg))
527 I.dump();
528}
529#endif
530
531void MachineRegisterInfo::freezeReservedRegs() {
532 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF: *MF);
533 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
534 "Invalid ReservedRegs vector from target");
535}
536
537bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
538 assert(PhysReg.isPhysical());
539
540 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
541 if (TRI->isConstantPhysReg(PhysReg))
542 return true;
543
544 // Check if any overlapping register is modified, or allocatable so it may be
545 // used later.
546 for (MCRegAliasIterator AI(PhysReg, TRI, true);
547 AI.isValid(); ++AI)
548 if (!def_empty(RegNo: *AI) || isAllocatable(PhysReg: *AI))
549 return false;
550 return true;
551}
552
553/// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
554/// specified register as undefined which causes the DBG_VALUE to be
555/// deleted during LiveDebugVariables analysis.
556void MachineRegisterInfo::markUsesInDebugValueAsUndef(Register Reg) const {
557 // Mark any DBG_VALUE* that uses Reg as undef (but don't delete it.)
558 // We use make_early_inc_range because setReg invalidates the iterator.
559 for (MachineInstr &UseMI : llvm::make_early_inc_range(Range: use_instructions(Reg))) {
560 if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg))
561 UseMI.setDebugValueUndef();
562 }
563}
564
565static const Function *getCalledFunction(const MachineInstr &MI) {
566 for (const MachineOperand &MO : MI.operands()) {
567 if (!MO.isGlobal())
568 continue;
569 const Function *Func = dyn_cast<Function>(Val: MO.getGlobal());
570 if (Func != nullptr)
571 return Func;
572 }
573 return nullptr;
574}
575
576static bool isNoReturnDef(const MachineOperand &MO) {
577 // Anything which is not a noreturn function is a real def.
578 const MachineInstr &MI = *MO.getParent();
579 if (!MI.isCall())
580 return false;
581 const MachineBasicBlock &MBB = *MI.getParent();
582 if (!MBB.succ_empty())
583 return false;
584 const MachineFunction &MF = *MBB.getParent();
585 // We need to keep correct unwind information even if the function will
586 // not return, since the runtime may need it.
587 if (MF.getFunction().hasFnAttribute(Kind: Attribute::UWTable))
588 return false;
589 const Function *Called = getCalledFunction(MI);
590 return !(Called == nullptr || !Called->hasFnAttribute(Kind: Attribute::NoReturn) ||
591 !Called->hasFnAttribute(Kind: Attribute::NoUnwind));
592}
593
594bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg,
595 bool SkipNoReturnDef) const {
596 if (UsedPhysRegMask.test(Idx: PhysReg.id()))
597 return true;
598 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
599 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
600 for (const MachineOperand &MO : make_range(x: def_begin(RegNo: *AI), y: def_end())) {
601 if (!SkipNoReturnDef && isNoReturnDef(MO))
602 continue;
603 return true;
604 }
605 }
606 return false;
607}
608
609bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg,
610 bool SkipRegMaskTest) const {
611 if (!SkipRegMaskTest && UsedPhysRegMask.test(Idx: PhysReg.id()))
612 return true;
613 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
614 for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
615 ++AliasReg) {
616 if (!reg_nodbg_empty(RegNo: *AliasReg))
617 return true;
618 }
619 return false;
620}
621
622void MachineRegisterInfo::disableCalleeSavedRegister(MCRegister Reg) {
623
624 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
625 assert(Reg && (Reg < TRI->getNumRegs()) &&
626 "Trying to disable an invalid register");
627
628 if (!IsUpdatedCSRsInitialized) {
629 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
630 for (const MCPhysReg *I = CSR; *I; ++I)
631 UpdatedCSRs.push_back(Elt: *I);
632
633 // Zero value represents the end of the register list
634 // (no more registers should be pushed).
635 UpdatedCSRs.push_back(Elt: 0);
636
637 IsUpdatedCSRsInitialized = true;
638 }
639
640 // Remove the register (and its aliases from the list).
641 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
642 llvm::erase(C&: UpdatedCSRs, V: *AI);
643}
644
645const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const {
646 if (IsUpdatedCSRsInitialized)
647 return UpdatedCSRs.data();
648
649 const MCPhysReg *Regs = getTargetRegisterInfo()->getCalleeSavedRegs(MF);
650
651 for (unsigned I = 0; Regs[I]; ++I)
652 if (MF->getSubtarget().isRegisterReservedByUser(R: Regs[I]))
653 MF->getRegInfo().disableCalleeSavedRegister(Reg: Regs[I]);
654
655 return Regs;
656}
657
658void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) {
659 if (IsUpdatedCSRsInitialized)
660 UpdatedCSRs.clear();
661
662 append_range(C&: UpdatedCSRs, R&: CSRs);
663
664 // Zero value represents the end of the register list
665 // (no more registers should be pushed).
666 UpdatedCSRs.push_back(Elt: 0);
667 IsUpdatedCSRsInitialized = true;
668}
669
670bool MachineRegisterInfo::isReservedRegUnit(MCRegUnit Unit) const {
671 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
672 for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
673 if (all_of(Range: TRI->superregs_inclusive(Reg: *Root),
674 P: [&](MCPhysReg Super) { return isReserved(PhysReg: Super); }))
675 return true;
676 }
677 return false;
678}
679
680void MachineRegisterInfo::updateDbgUsersToReg(
681 MCRegister OldReg, MCRegister NewReg,
682 ArrayRef<MachineInstr *> Users) const {
683 // If this operand is a register, check whether it overlaps with OldReg.
684 // If it does, replace with NewReg.
685 auto *TRI = getTargetRegisterInfo();
686 auto UpdateOp = [&NewReg, &OldReg, &TRI](MachineOperand &Op) {
687 if (!Op.isReg() || !TRI->regsOverlap(RegA: Op.getReg(), RegB: OldReg))
688 return;
689 if (Op.getReg() == OldReg) {
690 // Registers exactly match; replace OldReg with NewReg.
691 Op.setReg(NewReg);
692 return;
693 }
694 if (unsigned Idx = TRI->getSubRegIndex(RegNo: OldReg, SubRegNo: Op.getReg())) {
695 // Debug user refers to a subregister of OldReg; map to the corresponding
696 // subregister of NewReg.
697 if (MCRegister NewSubReg = TRI->getSubReg(Reg: NewReg, Idx)) {
698 Op.setReg(NewSubReg);
699 return;
700 }
701 }
702 // Registers have some more complicated relationship; discard the use.
703 Op.setReg(MCRegister::NoRegister);
704 };
705
706 // Iterate through (possibly several) operands to DBG_VALUEs and update
707 // each. For DBG_PHIs, only one operand will be present.
708 for (MachineInstr *MI : Users) {
709 if (MI->isDebugValue()) {
710 for (auto &Op : MI->debug_operands())
711 UpdateOp(Op);
712 } else if (MI->isDebugPHI()) {
713 UpdateOp(MI->getOperand(i: 0));
714 } else {
715 llvm_unreachable("Non-DBG_VALUE, Non-DBG_PHI debug instr updated");
716 }
717 }
718}
719