1//===---------------------- ProcessImplicitDefs.cpp -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "llvm/CodeGen/ProcessImplicitDefs.h"
10#include "llvm/ADT/SetVector.h"
11#include "llvm/Analysis/AliasAnalysis.h"
12#include "llvm/CodeGen/MachineFunctionPass.h"
13#include "llvm/CodeGen/MachineInstr.h"
14#include "llvm/CodeGen/MachineRegisterInfo.h"
15#include "llvm/CodeGen/TargetInstrInfo.h"
16#include "llvm/CodeGen/TargetSubtargetInfo.h"
17#include "llvm/InitializePasses.h"
18#include "llvm/Pass.h"
19#include "llvm/PassRegistry.h"
20#include "llvm/Support/Debug.h"
21#include "llvm/Support/raw_ostream.h"
22
23using namespace llvm;
24
25#define DEBUG_TYPE "processimpdefs"
26
27namespace {
28/// Process IMPLICIT_DEF instructions and make sure there is one implicit_def
29/// for each use. Add isUndef marker to implicit_def defs and their uses.
30class ProcessImplicitDefsLegacy : public MachineFunctionPass {
31public:
32 static char ID;
33
34 ProcessImplicitDefsLegacy() : MachineFunctionPass(ID) {}
35
36 void getAnalysisUsage(AnalysisUsage &AU) const override;
37
38 bool runOnMachineFunction(MachineFunction &MF) override;
39
40 MachineFunctionProperties getRequiredProperties() const override {
41 return MachineFunctionProperties().setIsSSA();
42 }
43};
44
45class ProcessImplicitDefs {
46 const TargetInstrInfo *TII = nullptr;
47 const TargetRegisterInfo *TRI = nullptr;
48 MachineRegisterInfo *MRI = nullptr;
49
50 SmallSetVector<MachineInstr *, 16> WorkList;
51
52 void processImplicitDef(MachineInstr *MI);
53 bool canTurnIntoImplicitDef(MachineInstr *MI);
54
55public:
56 bool run(MachineFunction &MF);
57};
58} // end anonymous namespace
59
60char ProcessImplicitDefsLegacy::ID = 0;
61char &llvm::ProcessImplicitDefsID = ProcessImplicitDefsLegacy::ID;
62
63INITIALIZE_PASS(ProcessImplicitDefsLegacy, DEBUG_TYPE,
64 "Process Implicit Definitions", false, false)
65
66void ProcessImplicitDefsLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
67 AU.setPreservesCFG();
68 AU.addPreserved<AAResultsWrapperPass>();
69 MachineFunctionPass::getAnalysisUsage(AU);
70}
71
72bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
73 if (!MI->isCopyLike() &&
74 !MI->isInsertSubreg() &&
75 !MI->isRegSequence() &&
76 !MI->isPHI())
77 return false;
78 for (const MachineOperand &MO : MI->all_uses())
79 if (MO.readsReg())
80 return false;
81 return true;
82}
83
84void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
85 LLVM_DEBUG(dbgs() << "Processing " << *MI);
86 Register Reg = MI->getOperand(i: 0).getReg();
87
88 if (Reg.isVirtual()) {
89 // For virtual registers, mark all uses as <undef>, and convert users to
90 // implicit-def when possible.
91 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
92 MO.setIsUndef();
93 MachineInstr *UserMI = MO.getParent();
94 if (!canTurnIntoImplicitDef(MI: UserMI))
95 continue;
96 LLVM_DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);
97 UserMI->setDesc(TII->get(Opcode: TargetOpcode::IMPLICIT_DEF));
98 WorkList.insert(X: UserMI);
99 }
100 MI->eraseFromParent();
101 return;
102 }
103
104 // This is a physreg implicit-def.
105 // Look for the first instruction to use or define an alias.
106 MachineBasicBlock::instr_iterator UserMI = MI->getIterator();
107 MachineBasicBlock::instr_iterator UserE = MI->getParent()->instr_end();
108 bool Found = false;
109 for (++UserMI; UserMI != UserE; ++UserMI) {
110 for (MachineOperand &MO : UserMI->operands()) {
111 if (!MO.isReg())
112 continue;
113 Register UserReg = MO.getReg();
114 if (!UserReg.isPhysical() || !TRI->regsOverlap(RegA: Reg, RegB: UserReg))
115 continue;
116 // UserMI uses or redefines Reg. Set <undef> flags on all uses.
117 Found = true;
118 if (MO.isUse())
119 MO.setIsUndef();
120 }
121 if (Found)
122 break;
123 }
124
125 // If we found the using MI, we can erase the IMPLICIT_DEF.
126 if (Found) {
127 LLVM_DEBUG(dbgs() << "Physreg user: " << *UserMI);
128 MI->eraseFromParent();
129 return;
130 }
131
132 // Using instr wasn't found, it could be in another block.
133 // Leave the physreg IMPLICIT_DEF, but trim any extra operands.
134 for (unsigned i = MI->getNumOperands() - 1; i; --i)
135 MI->removeOperand(OpNo: i);
136 LLVM_DEBUG(dbgs() << "Keeping physreg: " << *MI);
137}
138
139bool ProcessImplicitDefsLegacy::runOnMachineFunction(MachineFunction &MF) {
140 return ProcessImplicitDefs().run(MF);
141}
142
143PreservedAnalyses
144ProcessImplicitDefsPass::run(MachineFunction &MF,
145 MachineFunctionAnalysisManager &MFAM) {
146 if (!ProcessImplicitDefs().run(MF))
147 return PreservedAnalyses::all();
148
149 return getMachineFunctionPassPreservedAnalyses()
150 .preserveSet<CFGAnalyses>()
151 .preserve<AAManager>();
152}
153
154/// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into
155/// <undef> operands.
156bool ProcessImplicitDefs::run(MachineFunction &MF) {
157
158 LLVM_DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
159 << "********** Function: " << MF.getName() << '\n');
160
161 bool Changed = false;
162
163 TII = MF.getSubtarget().getInstrInfo();
164 TRI = MF.getSubtarget().getRegisterInfo();
165 MRI = &MF.getRegInfo();
166 assert(WorkList.empty() && "Inconsistent worklist state");
167
168 for (MachineBasicBlock &MBB : MF) {
169 // Scan the basic block for implicit defs.
170 for (MachineInstr &MI : MBB)
171 if (MI.isImplicitDef())
172 WorkList.insert(X: &MI);
173
174 if (WorkList.empty())
175 continue;
176
177 LLVM_DEBUG(dbgs() << printMBBReference(MBB) << " has " << WorkList.size()
178 << " implicit defs.\n");
179 Changed = true;
180
181 // Drain the WorkList to recursively process any new implicit defs.
182 do processImplicitDef(MI: WorkList.pop_back_val());
183 while (!WorkList.empty());
184 }
185 return Changed;
186}
187