1//===---------------------- ProcessImplicitDefs.cpp -----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "llvm/CodeGen/ProcessImplicitDefs.h"
10#include "llvm/ADT/SetVector.h"
11#include "llvm/Analysis/AliasAnalysis.h"
12#include "llvm/CodeGen/MachineFunctionPass.h"
13#include "llvm/CodeGen/MachineInstr.h"
14#include "llvm/CodeGen/MachineRegisterInfo.h"
15#include "llvm/CodeGen/TargetInstrInfo.h"
16#include "llvm/CodeGen/TargetSubtargetInfo.h"
17#include "llvm/InitializePasses.h"
18#include "llvm/Pass.h"
19#include "llvm/Support/Debug.h"
20#include "llvm/Support/raw_ostream.h"
21
22using namespace llvm;
23
24#define DEBUG_TYPE "processimpdefs"
25
26namespace {
27/// Process IMPLICIT_DEF instructions and make sure there is one implicit_def
28/// for each use. Add isUndef marker to implicit_def defs and their uses.
29class ProcessImplicitDefsLegacy : public MachineFunctionPass {
30public:
31 static char ID;
32
33 ProcessImplicitDefsLegacy() : MachineFunctionPass(ID) {}
34
35 void getAnalysisUsage(AnalysisUsage &AU) const override;
36
37 bool runOnMachineFunction(MachineFunction &MF) override;
38
39 MachineFunctionProperties getRequiredProperties() const override {
40 return MachineFunctionProperties().setIsSSA();
41 }
42};
43
44class ProcessImplicitDefs {
45 const TargetInstrInfo *TII = nullptr;
46 const TargetRegisterInfo *TRI = nullptr;
47 MachineRegisterInfo *MRI = nullptr;
48
49 SmallSetVector<MachineInstr *, 16> WorkList;
50
51 void processImplicitDef(MachineInstr *MI);
52 bool canTurnIntoImplicitDef(MachineInstr *MI);
53
54public:
55 bool run(MachineFunction &MF);
56};
57} // end anonymous namespace
58
59char ProcessImplicitDefsLegacy::ID = 0;
60char &llvm::ProcessImplicitDefsID = ProcessImplicitDefsLegacy::ID;
61
62INITIALIZE_PASS(ProcessImplicitDefsLegacy, DEBUG_TYPE,
63 "Process Implicit Definitions", false, false)
64
65void ProcessImplicitDefsLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
66 AU.setPreservesCFG();
67 AU.addPreserved<AAResultsWrapperPass>();
68 MachineFunctionPass::getAnalysisUsage(AU);
69}
70
71bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
72 if (!MI->isCopyLike() &&
73 !MI->isInsertSubreg() &&
74 !MI->isRegSequence() &&
75 !MI->isPHI())
76 return false;
77 for (const MachineOperand &MO : MI->all_uses())
78 if (MO.readsReg())
79 return false;
80 return true;
81}
82
83void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
84 LLVM_DEBUG(dbgs() << "Processing " << *MI);
85 Register Reg = MI->getOperand(i: 0).getReg();
86
87 if (Reg.isVirtual()) {
88 // For virtual registers, mark all uses as <undef>, and convert users to
89 // implicit-def when possible.
90 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
91 MO.setIsUndef();
92 MachineInstr *UserMI = MO.getParent();
93 if (!canTurnIntoImplicitDef(MI: UserMI))
94 continue;
95 LLVM_DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);
96 UserMI->setDesc(TII->get(Opcode: TargetOpcode::IMPLICIT_DEF));
97 WorkList.insert(X: UserMI);
98 }
99 MI->eraseFromParent();
100 return;
101 }
102
103 // This is a physreg implicit-def.
104 // Trim any extra operands.
105 for (unsigned i = MI->getNumOperands() - 1; i; --i)
106 MI->removeOperand(OpNo: i);
107
108 // Try to add undef flag to all uses. If all uses are updated remove
109 // implicit-def.
110 MachineBasicBlock::instr_iterator SearchMI = MI->getIterator();
111 MachineBasicBlock::instr_iterator SearchE = MI->getParent()->instr_end();
112 bool ImplicitDefIsDead = false;
113 bool SearchedWholeBlock = true;
114 constexpr unsigned SearchLimit = 35;
115 unsigned Count = 0;
116 for (++SearchMI; SearchMI != SearchE; ++SearchMI) {
117 if (SearchMI->isDebugInstr())
118 continue;
119 if (++Count > SearchLimit) {
120 SearchedWholeBlock = false;
121 break;
122 }
123 for (MachineOperand &MO : SearchMI->operands()) {
124 if (!MO.isReg())
125 continue;
126 Register SearchReg = MO.getReg();
127 if (!SearchReg.isPhysical() || !TRI->regsOverlap(RegA: Reg, RegB: SearchReg))
128 continue;
129 // SearchMI uses or redefines Reg. Set <undef> flags on all uses.
130 if (MO.isUse()) {
131 if (TRI->isSubRegisterEq(RegA: Reg, RegB: SearchReg)) {
132 MO.setIsUndef();
133 } else {
134 // Use is larger than Reg. It is not safe to add undef to this use.
135 return;
136 }
137 }
138 if (MO.isDef()) {
139 if (TRI->isSubRegisterEq(RegA: SearchReg, RegB: Reg)) {
140 ImplicitDefIsDead = true;
141 } else {
142 // Reg is larger than definition. It is not safe to add undef to any
143 // subsequent uses of Reg.
144 return;
145 }
146 }
147 }
148 if (ImplicitDefIsDead) {
149 LLVM_DEBUG(dbgs() << "Physreg redefine: " << *SearchMI);
150 break;
151 }
152 }
153
154 // If we have added an undef flag to all uses (i.e. we have found a redefining
155 // MI or there are no successors), we can erase the IMPLICIT_DEF.
156 if (ImplicitDefIsDead ||
157 (SearchedWholeBlock && MI->getParent()->succ_empty())) {
158 MI->eraseFromParent();
159 LLVM_DEBUG(dbgs() << "Deleting implicit-def: " << *MI);
160 }
161}
162
163bool ProcessImplicitDefsLegacy::runOnMachineFunction(MachineFunction &MF) {
164 return ProcessImplicitDefs().run(MF);
165}
166
167PreservedAnalyses
168ProcessImplicitDefsPass::run(MachineFunction &MF,
169 MachineFunctionAnalysisManager &MFAM) {
170 if (!ProcessImplicitDefs().run(MF))
171 return PreservedAnalyses::all();
172
173 return getMachineFunctionPassPreservedAnalyses()
174 .preserveSet<CFGAnalyses>()
175 .preserve<AAManager>();
176}
177
178/// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into
179/// <undef> operands.
180bool ProcessImplicitDefs::run(MachineFunction &MF) {
181
182 LLVM_DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
183 << "********** Function: " << MF.getName() << '\n');
184
185 bool Changed = false;
186
187 TII = MF.getSubtarget().getInstrInfo();
188 TRI = MF.getSubtarget().getRegisterInfo();
189 MRI = &MF.getRegInfo();
190 assert(WorkList.empty() && "Inconsistent worklist state");
191
192 for (MachineBasicBlock &MBB : MF) {
193 // Scan the basic block for implicit defs.
194 for (MachineInstr &MI : MBB)
195 if (MI.isImplicitDef())
196 WorkList.insert(X: &MI);
197
198 if (WorkList.empty())
199 continue;
200
201 LLVM_DEBUG(dbgs() << printMBBReference(MBB) << " has " << WorkList.size()
202 << " implicit defs.\n");
203 Changed = true;
204
205 // Drain the WorkList to recursively process any new implicit defs.
206 do processImplicitDef(MI: WorkList.pop_back_val());
207 while (!WorkList.empty());
208 }
209 return Changed;
210}
211