1//===- RegisterCoalescer.cpp - Generic Register Coalescing Interface ------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the generic RegisterCoalescer interface which
10// is used as the common interface used by all clients and
11// implementations of register coalescing.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RegisterCoalescer.h"
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/BitVector.h"
18#include "llvm/ADT/DenseSet.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/ADT/SmallPtrSet.h"
21#include "llvm/ADT/SmallVector.h"
22#include "llvm/ADT/Statistic.h"
23#include "llvm/CodeGen/CalcSpillWeights.h"
24#include "llvm/CodeGen/LiveInterval.h"
25#include "llvm/CodeGen/LiveIntervals.h"
26#include "llvm/CodeGen/LiveRangeEdit.h"
27#include "llvm/CodeGen/MachineBasicBlock.h"
28#include "llvm/CodeGen/MachineDominators.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineFunctionPass.h"
31#include "llvm/CodeGen/MachineInstr.h"
32#include "llvm/CodeGen/MachineInstrBuilder.h"
33#include "llvm/CodeGen/MachineLoopInfo.h"
34#include "llvm/CodeGen/MachineOperand.h"
35#include "llvm/CodeGen/MachinePassManager.h"
36#include "llvm/CodeGen/MachineRegisterInfo.h"
37#include "llvm/CodeGen/Passes.h"
38#include "llvm/CodeGen/RegisterClassInfo.h"
39#include "llvm/CodeGen/RegisterCoalescerPass.h"
40#include "llvm/CodeGen/SlotIndexes.h"
41#include "llvm/CodeGen/TargetInstrInfo.h"
42#include "llvm/CodeGen/TargetOpcodes.h"
43#include "llvm/CodeGen/TargetRegisterInfo.h"
44#include "llvm/CodeGen/TargetSubtargetInfo.h"
45#include "llvm/IR/DebugLoc.h"
46#include "llvm/InitializePasses.h"
47#include "llvm/MC/LaneBitmask.h"
48#include "llvm/MC/MCInstrDesc.h"
49#include "llvm/MC/MCRegisterInfo.h"
50#include "llvm/Pass.h"
51#include "llvm/Support/CommandLine.h"
52#include "llvm/Support/Compiler.h"
53#include "llvm/Support/Debug.h"
54#include "llvm/Support/ErrorHandling.h"
55#include "llvm/Support/raw_ostream.h"
56#include <algorithm>
57#include <cassert>
58#include <iterator>
59#include <limits>
60#include <tuple>
61#include <utility>
62#include <vector>
63
64using namespace llvm;
65
66#define DEBUG_TYPE "regalloc"
67
68STATISTIC(numJoins, "Number of interval joins performed");
69STATISTIC(numCrossRCs, "Number of cross class joins performed");
70STATISTIC(numCommutes, "Number of instruction commuting performed");
71STATISTIC(numExtends, "Number of copies extended");
72STATISTIC(NumReMats, "Number of instructions re-materialized");
73STATISTIC(NumInflated, "Number of register classes inflated");
74STATISTIC(NumLaneConflicts, "Number of dead lane conflicts tested");
75STATISTIC(NumLaneResolves, "Number of dead lane conflicts resolved");
76STATISTIC(NumShrinkToUses, "Number of shrinkToUses called");
77
78static cl::opt<bool> EnableJoining("join-liveintervals",
79 cl::desc("Coalesce copies (default=true)"),
80 cl::init(Val: true), cl::Hidden);
81
82static cl::opt<bool> UseTerminalRule("terminal-rule",
83 cl::desc("Apply the terminal rule"),
84 cl::init(Val: true), cl::Hidden);
85
86/// Temporary flag to test critical edge unsplitting.
87static cl::opt<bool> EnableJoinSplits(
88 "join-splitedges",
89 cl::desc("Coalesce copies on split edges (default=subtarget)"), cl::Hidden);
90
91/// Temporary flag to test global copy optimization.
92static cl::opt<cl::boolOrDefault> EnableGlobalCopies(
93 "join-globalcopies",
94 cl::desc("Coalesce copies that span blocks (default=subtarget)"),
95 cl::init(Val: cl::boolOrDefault::BOU_UNSET), cl::Hidden);
96
97static cl::opt<bool> VerifyCoalescing(
98 "verify-coalescing",
99 cl::desc("Verify machine instrs before and after register coalescing"),
100 cl::Hidden);
101
102static cl::opt<unsigned> LateRematUpdateThreshold(
103 "late-remat-update-threshold", cl::Hidden,
104 cl::desc("During rematerialization for a copy, if the def instruction has "
105 "many other copy uses to be rematerialized, delay the multiple "
106 "separate live interval update work and do them all at once after "
107 "all those rematerialization are done. It will save a lot of "
108 "repeated work. "),
109 cl::init(Val: 100));
110
111static cl::opt<unsigned> LargeIntervalSizeThreshold(
112 "large-interval-size-threshold", cl::Hidden,
113 cl::desc("If the valnos size of an interval is larger than the threshold, "
114 "it is regarded as a large interval. "),
115 cl::init(Val: 100));
116
117static cl::opt<unsigned> LargeIntervalFreqThreshold(
118 "large-interval-freq-threshold", cl::Hidden,
119 cl::desc("For a large interval, if it is coalesced with other live "
120 "intervals many times more than the threshold, stop its "
121 "coalescing to control the compile time. "),
122 cl::init(Val: 256));
123
124namespace {
125
126class JoinVals;
127
128class RegisterCoalescer : private LiveRangeEdit::Delegate {
129 MachineFunction *MF = nullptr;
130 MachineRegisterInfo *MRI = nullptr;
131 const TargetRegisterInfo *TRI = nullptr;
132 const TargetInstrInfo *TII = nullptr;
133 LiveIntervals *LIS = nullptr;
134 SlotIndexes *SI = nullptr;
135 const MachineLoopInfo *Loops = nullptr;
136 RegisterClassInfo RegClassInfo;
137
138 /// Position and VReg of a PHI instruction during coalescing.
139 struct PHIValPos {
140 SlotIndex SI; ///< Slot where this PHI occurs.
141 Register Reg; ///< VReg the PHI occurs in.
142 unsigned SubReg; ///< Qualifying subregister for Reg.
143 };
144
145 /// Map from debug instruction number to PHI position during coalescing.
146 DenseMap<unsigned, PHIValPos> PHIValToPos;
147 /// Index of, for each VReg, which debug instruction numbers and
148 /// corresponding PHIs are sensitive to coalescing. Each VReg may have
149 /// multiple PHI defs, at different positions.
150 DenseMap<Register, SmallVector<unsigned, 2>> RegToPHIIdx;
151
152 /// Debug variable location tracking -- for each VReg, maintain an
153 /// ordered-by-slot-index set of DBG_VALUEs, to help quick
154 /// identification of whether coalescing may change location validity.
155 using DbgValueLoc = std::pair<SlotIndex, MachineInstr *>;
156 DenseMap<Register, std::vector<DbgValueLoc>> DbgVRegToValues;
157
158 /// A LaneMask to remember on which subregister live ranges we need to call
159 /// shrinkToUses() later.
160 LaneBitmask ShrinkMask;
161
162 /// True if the main range of the currently coalesced intervals should be
163 /// checked for smaller live intervals.
164 bool ShrinkMainRange = false;
165
166 /// True if the coalescer should aggressively coalesce global copies
167 /// in favor of keeping local copies.
168 bool JoinGlobalCopies = false;
169
170 /// True if the coalescer should aggressively coalesce fall-thru
171 /// blocks exclusively containing copies.
172 bool JoinSplitEdges = false;
173
174 /// Copy instructions yet to be coalesced.
175 SmallVector<MachineInstr *, 8> WorkList;
176 SmallVector<MachineInstr *, 8> LocalWorkList;
177
178 /// Set of instruction pointers that have been erased, and
179 /// that may be present in WorkList.
180 SmallPtrSet<MachineInstr *, 8> ErasedInstrs;
181
182 /// Dead instructions that are about to be deleted.
183 SmallVector<MachineInstr *, 8> DeadDefs;
184
185 /// Virtual registers to be considered for register class inflation.
186 SmallVector<Register, 8> InflateRegs;
187
188 /// The collection of live intervals which should have been updated
189 /// immediately after rematerialiation but delayed until
190 /// lateLiveIntervalUpdate is called.
191 DenseSet<Register> ToBeUpdated;
192
193 /// Record how many times the large live interval with many valnos
194 /// has been tried to join with other live interval.
195 DenseMap<Register, unsigned long> LargeLIVisitCounter;
196
197 /// Recursively eliminate dead defs in DeadDefs.
198 void eliminateDeadDefs(LiveRangeEdit *Edit = nullptr);
199
200 /// LiveRangeEdit callback for eliminateDeadDefs().
201 void LRE_WillEraseInstruction(MachineInstr *MI) override;
202
203 /// Coalesce the LocalWorkList.
204 void coalesceLocals();
205
206 /// Join compatible live intervals
207 void joinAllIntervals();
208
209 /// Coalesce copies in the specified MBB, putting
210 /// copies that cannot yet be coalesced into WorkList.
211 void copyCoalesceInMBB(MachineBasicBlock *MBB);
212
213 /// Tries to coalesce all copies in CurrList. Returns true if any progress
214 /// was made.
215 bool copyCoalesceWorkList(MutableArrayRef<MachineInstr *> CurrList);
216
217 /// If one def has many copy like uses, and those copy uses are all
218 /// rematerialized, the live interval update needed for those
219 /// rematerializations will be delayed and done all at once instead
220 /// of being done multiple times. This is to save compile cost because
221 /// live interval update is costly.
222 void lateLiveIntervalUpdate();
223
224 /// Check if the incoming value defined by a COPY at \p SLRQ in the subrange
225 /// has no value defined in the predecessors. If the incoming value is the
226 /// same as defined by the copy itself, the value is considered undefined.
227 bool copyValueUndefInPredecessors(LiveRange &S, const MachineBasicBlock *MBB,
228 LiveQueryResult SLRQ);
229
230 /// Set necessary undef flags on subregister uses after pruning out undef
231 /// lane segments from the subrange.
232 void setUndefOnPrunedSubRegUses(LiveInterval &LI, Register Reg,
233 LaneBitmask PrunedLanes);
234
235 /// Attempt to join intervals corresponding to SrcReg/DstReg, which are the
236 /// src/dst of the copy instruction CopyMI. This returns true if the copy
237 /// was successfully coalesced away. If it is not currently possible to
238 /// coalesce this interval, but it may be possible if other things get
239 /// coalesced, then it returns true by reference in 'Again'.
240 bool joinCopy(MachineInstr *CopyMI, bool &Again,
241 SmallPtrSetImpl<MachineInstr *> &CurrentErasedInstrs);
242
243 /// Attempt to join these two intervals. On failure, this
244 /// returns false. The output "SrcInt" will not have been modified, so we
245 /// can use this information below to update aliases.
246 bool joinIntervals(CoalescerPair &CP);
247
248 /// Attempt joining two virtual registers. Return true on success.
249 bool joinVirtRegs(CoalescerPair &CP);
250
251 /// If a live interval has many valnos and is coalesced with other
252 /// live intervals many times, we regard such live interval as having
253 /// high compile time cost.
254 bool isHighCostLiveInterval(LiveInterval &LI);
255
256 /// Attempt joining with a reserved physreg.
257 bool joinReservedPhysReg(CoalescerPair &CP);
258
259 /// Add the LiveRange @p ToMerge as a subregister liverange of @p LI.
260 /// Subranges in @p LI which only partially interfere with the desired
261 /// LaneMask are split as necessary. @p LaneMask are the lanes that
262 /// @p ToMerge will occupy in the coalescer register. @p LI has its subrange
263 /// lanemasks already adjusted to the coalesced register.
264 void mergeSubRangeInto(LiveInterval &LI, const LiveRange &ToMerge,
265 LaneBitmask LaneMask, CoalescerPair &CP,
266 unsigned DstIdx);
267
268 /// Join the liveranges of two subregisters. Joins @p RRange into
269 /// @p LRange, @p RRange may be invalid afterwards.
270 void joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
271 LaneBitmask LaneMask, const CoalescerPair &CP);
272
273 /// We found a non-trivially-coalescable copy. If the source value number is
274 /// defined by a copy from the destination reg see if we can merge these two
275 /// destination reg valno# into a single value number, eliminating a copy.
276 /// This returns true if an interval was modified.
277 bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
278
279 /// Return true if there are definitions of IntB
280 /// other than BValNo val# that can reach uses of AValno val# of IntA.
281 bool hasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
282 VNInfo *AValNo, VNInfo *BValNo);
283
284 /// We found a non-trivially-coalescable copy.
285 /// If the source value number is defined by a commutable instruction and
286 /// its other operand is coalesced to the copy dest register, see if we
287 /// can transform the copy into a noop by commuting the definition.
288 /// This returns a pair of two flags:
289 /// - the first element is true if an interval was modified,
290 /// - the second element is true if the destination interval needs
291 /// to be shrunk after deleting the copy.
292 std::pair<bool, bool> removeCopyByCommutingDef(const CoalescerPair &CP,
293 MachineInstr *CopyMI);
294
295 /// We found a copy which can be moved to its less frequent predecessor.
296 bool removePartialRedundancy(const CoalescerPair &CP, MachineInstr &CopyMI);
297
298 /// If the source of a copy is defined by a CheapAsAMove computation,
299 /// replace the copy by rematerialize the definition.
300 bool reMaterializeDef(const CoalescerPair &CP, MachineInstr *CopyMI,
301 bool &IsDefCopy);
302
303 /// Return true if a copy involving a physreg should be joined.
304 bool canJoinPhys(const CoalescerPair &CP);
305
306 /// Replace all defs and uses of SrcReg to DstReg and update the subregister
307 /// number if it is not zero. If DstReg is a physical register and the
308 /// existing subregister number of the def / use being updated is not zero,
309 /// make sure to set it to the correct physical subregister.
310 void updateRegDefsUses(Register SrcReg, Register DstReg, unsigned SubIdx);
311
312 /// If the given machine operand reads only undefined lanes add an undef
313 /// flag.
314 /// This can happen when undef uses were previously concealed by a copy
315 /// which we coalesced. Example:
316 /// %0:sub0<def,read-undef> = ...
317 /// %1 = COPY %0 <-- Coalescing COPY reveals undef
318 /// = use %1:sub1 <-- hidden undef use
319 void addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
320 MachineOperand &MO, unsigned SubRegIdx);
321
322 /// Handle copies of undef values. If the undef value is an incoming
323 /// PHI value, it will convert @p CopyMI to an IMPLICIT_DEF.
324 /// Returns nullptr if @p CopyMI was not in any way eliminable. Otherwise,
325 /// it returns @p CopyMI (which could be an IMPLICIT_DEF at this point).
326 MachineInstr *eliminateUndefCopy(MachineInstr *CopyMI);
327
328 /// Check whether or not we should apply the terminal rule on the
329 /// destination (Dst) of \p Copy.
330 /// When the terminal rule applies, Copy is not profitable to
331 /// coalesce.
332 /// Dst is terminal if it has exactly one affinity (Dst, Src) and
333 /// at least one interference (Dst, Dst2). If Dst is terminal, the
334 /// terminal rule consists in checking that at least one of
335 /// interfering node, say Dst2, has an affinity of equal or greater
336 /// weight with Src.
337 /// In that case, Dst2 and Dst will not be able to be both coalesced
338 /// with Src. Since Dst2 exposes more coalescing opportunities than
339 /// Dst, we can drop \p Copy.
340 bool applyTerminalRule(const MachineInstr &Copy) const;
341
342 /// Wrapper method for \see LiveIntervals::shrinkToUses.
343 /// This method does the proper fixing of the live-ranges when the afore
344 /// mentioned method returns true.
345 void shrinkToUses(LiveInterval *LI,
346 SmallVectorImpl<MachineInstr *> *Dead = nullptr) {
347 NumShrinkToUses++;
348 if (LIS->shrinkToUses(li: LI, dead: Dead)) {
349 /// Check whether or not \p LI is composed by multiple connected
350 /// components and if that is the case, fix that.
351 SmallVector<LiveInterval *, 8> SplitLIs;
352 LIS->splitSeparateComponents(LI&: *LI, SplitLIs);
353 }
354 }
355
356 /// Wrapper Method to do all the necessary work when an Instruction is
357 /// deleted.
358 /// Optimizations should use this to make sure that deleted instructions
359 /// are always accounted for.
360 void deleteInstr(MachineInstr *MI) {
361 ErasedInstrs.insert(Ptr: MI);
362 LIS->RemoveMachineInstrFromMaps(MI&: *MI);
363 MI->eraseFromParent();
364 }
365
366 /// Walk over function and initialize the DbgVRegToValues map.
367 void buildVRegToDbgValueMap(MachineFunction &MF);
368
369 /// Test whether, after merging, any DBG_VALUEs would refer to a
370 /// different value number than before merging, and whether this can
371 /// be resolved. If not, mark the DBG_VALUE as being undef.
372 void checkMergingChangesDbgValues(CoalescerPair &CP, LiveRange &LHS,
373 JoinVals &LHSVals, LiveRange &RHS,
374 JoinVals &RHSVals);
375
376 void checkMergingChangesDbgValuesImpl(Register Reg, LiveRange &OtherRange,
377 LiveRange &RegRange, JoinVals &Vals2);
378
379public:
380 // For legacy pass only.
381 RegisterCoalescer() = default;
382 RegisterCoalescer &operator=(RegisterCoalescer &&Other) = default;
383
384 RegisterCoalescer(LiveIntervals *LIS, SlotIndexes *SI,
385 const MachineLoopInfo *Loops)
386 : LIS(LIS), SI(SI), Loops(Loops) {}
387
388 bool run(MachineFunction &MF);
389};
390
391class RegisterCoalescerLegacy : public MachineFunctionPass {
392public:
393 static char ID; ///< Class identification, replacement for typeinfo
394
395 RegisterCoalescerLegacy() : MachineFunctionPass(ID) {}
396
397 void getAnalysisUsage(AnalysisUsage &AU) const override;
398
399 MachineFunctionProperties getClearedProperties() const override {
400 return MachineFunctionProperties().setIsSSA();
401 }
402
403 /// This is the pass entry point.
404 bool runOnMachineFunction(MachineFunction &) override;
405};
406
407} // end anonymous namespace
408
409char RegisterCoalescerLegacy::ID = 0;
410
411char &llvm::RegisterCoalescerID = RegisterCoalescerLegacy::ID;
412
413INITIALIZE_PASS_BEGIN(RegisterCoalescerLegacy, "register-coalescer",
414 "Register Coalescer", false, false)
415INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
416INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
417INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
418INITIALIZE_PASS_END(RegisterCoalescerLegacy, "register-coalescer",
419 "Register Coalescer", false, false)
420
421[[nodiscard]] static bool isMoveInstr(const TargetRegisterInfo &tri,
422 const MachineInstr *MI, Register &Src,
423 Register &Dst, unsigned &SrcSub,
424 unsigned &DstSub) {
425 if (MI->isCopy()) {
426 Dst = MI->getOperand(i: 0).getReg();
427 DstSub = MI->getOperand(i: 0).getSubReg();
428 Src = MI->getOperand(i: 1).getReg();
429 SrcSub = MI->getOperand(i: 1).getSubReg();
430 } else if (MI->isSubregToReg()) {
431 Dst = MI->getOperand(i: 0).getReg();
432 DstSub = tri.composeSubRegIndices(a: MI->getOperand(i: 0).getSubReg(),
433 b: MI->getOperand(i: 2).getImm());
434 Src = MI->getOperand(i: 1).getReg();
435 SrcSub = MI->getOperand(i: 1).getSubReg();
436 } else
437 return false;
438 return true;
439}
440
441/// Return true if this block should be vacated by the coalescer to eliminate
442/// branches. The important cases to handle in the coalescer are critical edges
443/// split during phi elimination which contain only copies. Simple blocks that
444/// contain non-branches should also be vacated, but this can be handled by an
445/// earlier pass similar to early if-conversion.
446static bool isSplitEdge(const MachineBasicBlock *MBB) {
447 if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
448 return false;
449
450 for (const auto &MI : *MBB) {
451 if (!MI.isCopyLike() && !MI.isUnconditionalBranch())
452 return false;
453 }
454 return true;
455}
456
457bool CoalescerPair::setRegisters(const MachineInstr *MI) {
458 SrcReg = DstReg = Register();
459 SrcIdx = DstIdx = 0;
460 NewRC = nullptr;
461 Flipped = CrossClass = false;
462
463 Register Src, Dst;
464 unsigned SrcSub = 0, DstSub = 0;
465 if (!isMoveInstr(tri: TRI, MI, Src, Dst, SrcSub, DstSub))
466 return false;
467 Partial = SrcSub || DstSub;
468
469 // If one register is a physreg, it must be Dst.
470 if (Src.isPhysical()) {
471 if (Dst.isPhysical())
472 return false;
473 std::swap(a&: Src, b&: Dst);
474 std::swap(a&: SrcSub, b&: DstSub);
475 Flipped = true;
476 }
477
478 const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
479 const TargetRegisterClass *SrcRC = MRI.getRegClass(Reg: Src);
480
481 if (Dst.isPhysical()) {
482 // Eliminate DstSub on a physreg.
483 if (DstSub) {
484 Dst = TRI.getSubReg(Reg: Dst, Idx: DstSub);
485 if (!Dst)
486 return false;
487 DstSub = 0;
488 }
489
490 // Eliminate SrcSub by picking a corresponding Dst superregister.
491 if (SrcSub) {
492 Dst = TRI.getMatchingSuperReg(Reg: Dst, SubIdx: SrcSub, RC: SrcRC);
493 if (!Dst)
494 return false;
495 } else if (!SrcRC->contains(Reg: Dst)) {
496 return false;
497 }
498 } else {
499 // Both registers are virtual.
500 const TargetRegisterClass *DstRC = MRI.getRegClass(Reg: Dst);
501
502 // Both registers have subreg indices.
503 if (SrcSub && DstSub) {
504 // Copies between different sub-registers are never coalescable.
505 if (Src == Dst && SrcSub != DstSub)
506 return false;
507
508 NewRC = TRI.getCommonSuperRegClass(RCA: SrcRC, SubA: SrcSub, RCB: DstRC, SubB: DstSub, PreA&: SrcIdx,
509 PreB&: DstIdx);
510 if (!NewRC)
511 return false;
512 } else if (DstSub) {
513 // SrcReg will be merged with a sub-register of DstReg.
514 SrcIdx = DstSub;
515 NewRC = TRI.getMatchingSuperRegClass(A: DstRC, B: SrcRC, Idx: DstSub);
516 } else if (SrcSub) {
517 // DstReg will be merged with a sub-register of SrcReg.
518 DstIdx = SrcSub;
519 NewRC = TRI.getMatchingSuperRegClass(A: SrcRC, B: DstRC, Idx: SrcSub);
520 } else {
521 // This is a straight copy without sub-registers.
522 NewRC = TRI.getCommonSubClass(A: DstRC, B: SrcRC);
523 }
524
525 // The combined constraint may be impossible to satisfy.
526 if (!NewRC)
527 return false;
528
529 // Prefer SrcReg to be a sub-register of DstReg.
530 // FIXME: Coalescer should support subregs symmetrically.
531 if (DstIdx && !SrcIdx) {
532 std::swap(a&: Src, b&: Dst);
533 std::swap(a&: SrcIdx, b&: DstIdx);
534 Flipped = !Flipped;
535 }
536
537 CrossClass = NewRC != DstRC || NewRC != SrcRC;
538 }
539 // Check our invariants
540 assert(Src.isVirtual() && "Src must be virtual");
541 assert(!(Dst.isPhysical() && DstSub) && "Cannot have a physical SubIdx");
542 SrcReg = Src;
543 DstReg = Dst;
544 return true;
545}
546
547bool CoalescerPair::flip() {
548 if (DstReg.isPhysical())
549 return false;
550 std::swap(a&: SrcReg, b&: DstReg);
551 std::swap(a&: SrcIdx, b&: DstIdx);
552 Flipped = !Flipped;
553 return true;
554}
555
556bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
557 if (!MI)
558 return false;
559 Register Src, Dst;
560 unsigned SrcSub = 0, DstSub = 0;
561 if (!isMoveInstr(tri: TRI, MI, Src, Dst, SrcSub, DstSub))
562 return false;
563
564 // Find the virtual register that is SrcReg.
565 if (Dst == SrcReg) {
566 std::swap(a&: Src, b&: Dst);
567 std::swap(a&: SrcSub, b&: DstSub);
568 } else if (Src != SrcReg) {
569 return false;
570 }
571
572 // Now check that Dst matches DstReg.
573 if (DstReg.isPhysical()) {
574 if (!Dst.isPhysical())
575 return false;
576 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
577 // DstSub could be set for a physreg from INSERT_SUBREG.
578 if (DstSub)
579 Dst = TRI.getSubReg(Reg: Dst, Idx: DstSub);
580 // Full copy of Src.
581 if (!SrcSub)
582 return DstReg == Dst;
583 // This is a partial register copy. Check that the parts match.
584 return Register(TRI.getSubReg(Reg: DstReg, Idx: SrcSub)) == Dst;
585 }
586
587 // DstReg is virtual.
588 if (DstReg != Dst)
589 return false;
590 // Registers match, do the subregisters line up?
591 return TRI.composeSubRegIndices(a: SrcIdx, b: SrcSub) ==
592 TRI.composeSubRegIndices(a: DstIdx, b: DstSub);
593}
594
595void RegisterCoalescerLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
596 AU.setPreservesCFG();
597 AU.addUsedIfAvailable<SlotIndexesWrapperPass>();
598 AU.addRequired<LiveIntervalsWrapperPass>();
599 AU.addPreserved<LiveIntervalsWrapperPass>();
600 AU.addPreserved<SlotIndexesWrapperPass>();
601 AU.addRequired<MachineLoopInfoWrapperPass>();
602 AU.addPreserved<MachineLoopInfoWrapperPass>();
603 AU.addPreservedID(ID&: MachineDominatorsID);
604 MachineFunctionPass::getAnalysisUsage(AU);
605}
606
607void RegisterCoalescer::eliminateDeadDefs(LiveRangeEdit *Edit) {
608 if (Edit) {
609 Edit->eliminateDeadDefs(Dead&: DeadDefs);
610 return;
611 }
612 SmallVector<Register, 8> NewRegs;
613 LiveRangeEdit(nullptr, NewRegs, *MF, *LIS, nullptr, this)
614 .eliminateDeadDefs(Dead&: DeadDefs);
615}
616
617void RegisterCoalescer::LRE_WillEraseInstruction(MachineInstr *MI) {
618 // MI may be in WorkList. Make sure we don't visit it.
619 ErasedInstrs.insert(Ptr: MI);
620}
621
622bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
623 MachineInstr *CopyMI) {
624 assert(!CP.isPartial() && "This doesn't work for partial copies.");
625 assert(!CP.isPhys() && "This doesn't work for physreg copies.");
626
627 LiveInterval &IntA =
628 LIS->getInterval(Reg: CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
629 LiveInterval &IntB =
630 LIS->getInterval(Reg: CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
631 SlotIndex CopyIdx = LIS->getInstructionIndex(Instr: *CopyMI).getRegSlot();
632
633 // We have a non-trivially-coalescable copy with IntA being the source and
634 // IntB being the dest, thus this defines a value number in IntB. If the
635 // source value number (in IntA) is defined by a copy from B, see if we can
636 // merge these two pieces of B into a single value number, eliminating a copy.
637 // For example:
638 //
639 // A3 = B0
640 // ...
641 // B1 = A3 <- this copy
642 //
643 // In this case, B0 can be extended to where the B1 copy lives, allowing the
644 // B1 value number to be replaced with B0 (which simplifies the B
645 // liveinterval).
646
647 // BValNo is a value number in B that is defined by a copy from A. 'B1' in
648 // the example above.
649 LiveInterval::iterator BS = IntB.FindSegmentContaining(Idx: CopyIdx);
650 if (BS == IntB.end())
651 return false;
652 VNInfo *BValNo = BS->valno;
653
654 // Get the location that B is defined at. Two options: either this value has
655 // an unknown definition point or it is defined at CopyIdx. If unknown, we
656 // can't process it.
657 if (BValNo->def != CopyIdx)
658 return false;
659
660 // AValNo is the value number in A that defines the copy, A3 in the example.
661 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(EC: true);
662 LiveInterval::iterator AS = IntA.FindSegmentContaining(Idx: CopyUseIdx);
663 // The live segment might not exist after fun with physreg coalescing.
664 if (AS == IntA.end())
665 return false;
666 VNInfo *AValNo = AS->valno;
667
668 // If AValNo is defined as a copy from IntB, we can potentially process this.
669 // Get the instruction that defines this value number.
670 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(index: AValNo->def);
671 // Don't allow any partial copies, even if isCoalescable() allows them.
672 if (!CP.isCoalescable(MI: ACopyMI) || !ACopyMI->isFullCopy())
673 return false;
674
675 // Get the Segment in IntB that this value number starts with.
676 LiveInterval::iterator ValS =
677 IntB.FindSegmentContaining(Idx: AValNo->def.getPrevSlot());
678 if (ValS == IntB.end())
679 return false;
680
681 // Make sure that the end of the live segment is inside the same block as
682 // CopyMI.
683 MachineInstr *ValSEndInst =
684 LIS->getInstructionFromIndex(index: ValS->end.getPrevSlot());
685 if (!ValSEndInst || ValSEndInst->getParent() != CopyMI->getParent())
686 return false;
687
688 // Okay, we now know that ValS ends in the same block that the CopyMI
689 // live-range starts. If there are no intervening live segments between them
690 // in IntB, we can merge them.
691 if (ValS + 1 != BS)
692 return false;
693
694 LLVM_DEBUG(dbgs() << "Extending: " << printReg(IntB.reg(), TRI));
695
696 SlotIndex FillerStart = ValS->end, FillerEnd = BS->start;
697 // We are about to delete CopyMI, so need to remove it as the 'instruction
698 // that defines this value #'. Update the valnum with the new defining
699 // instruction #.
700 BValNo->def = FillerStart;
701
702 // Okay, we can merge them. We need to insert a new liverange:
703 // [ValS.end, BS.begin) of either value number, then we merge the
704 // two value numbers.
705 IntB.addSegment(S: LiveInterval::Segment(FillerStart, FillerEnd, BValNo));
706
707 // Okay, merge "B1" into the same value number as "B0".
708 if (BValNo != ValS->valno)
709 IntB.MergeValueNumberInto(V1: BValNo, V2: ValS->valno);
710
711 // Do the same for the subregister segments.
712 for (LiveInterval::SubRange &S : IntB.subranges()) {
713 // Check for SubRange Segments of the form [1234r,1234d:0) which can be
714 // removed to prevent creating bogus SubRange Segments.
715 LiveInterval::iterator SS = S.FindSegmentContaining(Idx: CopyIdx);
716 if (SS != S.end() && SlotIndex::isSameInstr(A: SS->start, B: SS->end)) {
717 S.removeSegment(S: *SS, RemoveDeadValNo: true);
718 continue;
719 }
720 // The subrange may have ended before FillerStart. If so, extend it.
721 if (!S.getVNInfoAt(Idx: FillerStart)) {
722 SlotIndex BBStart =
723 LIS->getMBBStartIdx(mbb: LIS->getMBBFromIndex(index: FillerStart));
724 S.extendInBlock(StartIdx: BBStart, Kill: FillerStart);
725 }
726 VNInfo *SubBValNo = S.getVNInfoAt(Idx: CopyIdx);
727 S.addSegment(S: LiveInterval::Segment(FillerStart, FillerEnd, SubBValNo));
728 VNInfo *SubValSNo = S.getVNInfoAt(Idx: AValNo->def.getPrevSlot());
729 if (SubBValNo != SubValSNo)
730 S.MergeValueNumberInto(V1: SubBValNo, V2: SubValSNo);
731 }
732
733 LLVM_DEBUG(dbgs() << " result = " << IntB << '\n');
734
735 // If the source instruction was killing the source register before the
736 // merge, unset the isKill marker given the live range has been extended.
737 int UIdx =
738 ValSEndInst->findRegisterUseOperandIdx(Reg: IntB.reg(), /*TRI=*/nullptr, isKill: true);
739 if (UIdx != -1) {
740 ValSEndInst->getOperand(i: UIdx).setIsKill(false);
741 }
742
743 // Rewrite the copy.
744 CopyMI->substituteRegister(FromReg: IntA.reg(), ToReg: IntB.reg(), SubIdx: 0, RegInfo: *TRI);
745 // If the copy instruction was killing the destination register or any
746 // subrange before the merge trim the live range.
747 bool RecomputeLiveRange = AS->end == CopyIdx;
748 if (!RecomputeLiveRange) {
749 for (LiveInterval::SubRange &S : IntA.subranges()) {
750 LiveInterval::iterator SS = S.FindSegmentContaining(Idx: CopyUseIdx);
751 if (SS != S.end() && SS->end == CopyIdx) {
752 RecomputeLiveRange = true;
753 break;
754 }
755 }
756 }
757 if (RecomputeLiveRange)
758 shrinkToUses(LI: &IntA);
759
760 ++numExtends;
761 return true;
762}
763
764bool RegisterCoalescer::hasOtherReachingDefs(LiveInterval &IntA,
765 LiveInterval &IntB, VNInfo *AValNo,
766 VNInfo *BValNo) {
767 // If AValNo has PHI kills, conservatively assume that IntB defs can reach
768 // the PHI values.
769 if (LIS->hasPHIKill(LI: IntA, VNI: AValNo))
770 return true;
771
772 for (LiveRange::Segment &ASeg : IntA.segments) {
773 if (ASeg.valno != AValNo)
774 continue;
775 LiveInterval::iterator BI = llvm::upper_bound(Range&: IntB, Value&: ASeg.start);
776 if (BI != IntB.begin())
777 --BI;
778 for (; BI != IntB.end() && ASeg.end >= BI->start; ++BI) {
779 if (BI->valno == BValNo)
780 continue;
781 if (BI->start <= ASeg.start && BI->end > ASeg.start)
782 return true;
783 if (BI->start > ASeg.start && BI->start < ASeg.end)
784 return true;
785 }
786 }
787 return false;
788}
789
790/// Copy segments with value number @p SrcValNo from liverange @p Src to live
791/// range @Dst and use value number @p DstValNo there.
792static std::pair<bool, bool> addSegmentsWithValNo(LiveRange &Dst,
793 VNInfo *DstValNo,
794 const LiveRange &Src,
795 const VNInfo *SrcValNo) {
796 bool Changed = false;
797 bool MergedWithDead = false;
798 for (const LiveRange::Segment &S : Src.segments) {
799 if (S.valno != SrcValNo)
800 continue;
801 // This is adding a segment from Src that ends in a copy that is about
802 // to be removed. This segment is going to be merged with a pre-existing
803 // segment in Dst. This works, except in cases when the corresponding
804 // segment in Dst is dead. For example: adding [192r,208r:1) from Src
805 // to [208r,208d:1) in Dst would create [192r,208d:1) in Dst.
806 // Recognized such cases, so that the segments can be shrunk.
807 LiveRange::Segment Added = LiveRange::Segment(S.start, S.end, DstValNo);
808 LiveRange::Segment &Merged = *Dst.addSegment(S: Added);
809 if (Merged.end.isDead())
810 MergedWithDead = true;
811 Changed = true;
812 }
813 return std::make_pair(x&: Changed, y&: MergedWithDead);
814}
815
816std::pair<bool, bool>
817RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
818 MachineInstr *CopyMI) {
819 assert(!CP.isPhys());
820
821 LiveInterval &IntA =
822 LIS->getInterval(Reg: CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
823 LiveInterval &IntB =
824 LIS->getInterval(Reg: CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
825
826 // We found a non-trivially-coalescable copy with IntA being the source and
827 // IntB being the dest, thus this defines a value number in IntB. If the
828 // source value number (in IntA) is defined by a commutable instruction and
829 // its other operand is coalesced to the copy dest register, see if we can
830 // transform the copy into a noop by commuting the definition. For example,
831 //
832 // A3 = op A2 killed B0
833 // ...
834 // B1 = A3 <- this copy
835 // ...
836 // = op A3 <- more uses
837 //
838 // ==>
839 //
840 // B2 = op B0 killed A2
841 // ...
842 // B1 = B2 <- now an identity copy
843 // ...
844 // = op B2 <- more uses
845
846 // BValNo is a value number in B that is defined by a copy from A. 'B1' in
847 // the example above.
848 SlotIndex CopyIdx = LIS->getInstructionIndex(Instr: *CopyMI).getRegSlot();
849 VNInfo *BValNo = IntB.getVNInfoAt(Idx: CopyIdx);
850 assert(BValNo != nullptr && BValNo->def == CopyIdx);
851
852 // AValNo is the value number in A that defines the copy, A3 in the example.
853 VNInfo *AValNo = IntA.getVNInfoAt(Idx: CopyIdx.getRegSlot(EC: true));
854 assert(AValNo && !AValNo->isUnused() && "COPY source not live");
855 if (AValNo->isPHIDef())
856 return {false, false};
857 MachineInstr *DefMI = LIS->getInstructionFromIndex(index: AValNo->def);
858 if (!DefMI)
859 return {false, false};
860 if (!DefMI->isCommutable())
861 return {false, false};
862 // If DefMI is a two-address instruction then commuting it will change the
863 // destination register.
864 int DefIdx = DefMI->findRegisterDefOperandIdx(Reg: IntA.reg(), /*TRI=*/nullptr);
865 assert(DefIdx != -1);
866 unsigned UseOpIdx;
867 if (!DefMI->isRegTiedToUseOperand(DefOpIdx: DefIdx, UseOpIdx: &UseOpIdx))
868 return {false, false};
869
870 // If DefMI only defines the register partially, we can't replace uses of the
871 // full register with the new destination register after commuting it.
872 if (IntA.reg().isVirtual() &&
873 none_of(Range: DefMI->all_defs(), P: [&](const MachineOperand &DefMO) {
874 return DefMO.getReg() == IntA.reg() && !DefMO.getSubReg();
875 }))
876 return {false, false};
877
878 // FIXME: The code below tries to commute 'UseOpIdx' operand with some other
879 // commutable operand which is expressed by 'CommuteAnyOperandIndex'value
880 // passed to the method. That _other_ operand is chosen by
881 // the findCommutedOpIndices() method.
882 //
883 // That is obviously an area for improvement in case of instructions having
884 // more than 2 operands. For example, if some instruction has 3 commutable
885 // operands then all possible variants (i.e. op#1<->op#2, op#1<->op#3,
886 // op#2<->op#3) of commute transformation should be considered/tried here.
887 unsigned NewDstIdx = TargetInstrInfo::CommuteAnyOperandIndex;
888 if (!TII->findCommutedOpIndices(MI: *DefMI, SrcOpIdx1&: UseOpIdx, SrcOpIdx2&: NewDstIdx))
889 return {false, false};
890
891 MachineOperand &NewDstMO = DefMI->getOperand(i: NewDstIdx);
892 Register NewReg = NewDstMO.getReg();
893 if (NewReg != IntB.reg() || !IntB.Query(Idx: AValNo->def).isKill())
894 return {false, false};
895
896 // Make sure there are no other definitions of IntB that would reach the
897 // uses which the new definition can reach.
898 if (hasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
899 return {false, false};
900
901 // If some of the uses of IntA.reg is already coalesced away, return false.
902 // It's not possible to determine whether it's safe to perform the coalescing.
903 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg: IntA.reg())) {
904 MachineInstr *UseMI = MO.getParent();
905 unsigned OpNo = &MO - &UseMI->getOperand(i: 0);
906 SlotIndex UseIdx = LIS->getInstructionIndex(Instr: *UseMI);
907 LiveInterval::iterator US = IntA.FindSegmentContaining(Idx: UseIdx);
908 if (US == IntA.end() || US->valno != AValNo)
909 continue;
910 // If this use is tied to a def, we can't rewrite the register.
911 if (UseMI->isRegTiedToDefOperand(UseOpIdx: OpNo))
912 return {false, false};
913 }
914
915 LLVM_DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t'
916 << *DefMI);
917
918 // At this point we have decided that it is legal to do this
919 // transformation. Start by commuting the instruction.
920 MachineBasicBlock *MBB = DefMI->getParent();
921 MachineInstr *NewMI =
922 TII->commuteInstruction(MI&: *DefMI, NewMI: false, OpIdx1: UseOpIdx, OpIdx2: NewDstIdx);
923 if (!NewMI)
924 return {false, false};
925 if (IntA.reg().isVirtual() && IntB.reg().isVirtual() &&
926 !MRI->constrainRegClass(Reg: IntB.reg(), RC: MRI->getRegClass(Reg: IntA.reg())))
927 return {false, false};
928 if (NewMI != DefMI) {
929 LIS->ReplaceMachineInstrInMaps(MI&: *DefMI, NewMI&: *NewMI);
930 MachineBasicBlock::iterator Pos = DefMI;
931 MBB->insert(I: Pos, MI: NewMI);
932 MBB->erase(I: DefMI);
933 }
934
935 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
936 // A = or A, B
937 // ...
938 // B = A
939 // ...
940 // C = killed A
941 // ...
942 // = B
943
944 // Update uses of IntA of the specific Val# with IntB.
945 for (MachineOperand &UseMO :
946 llvm::make_early_inc_range(Range: MRI->use_operands(Reg: IntA.reg()))) {
947 if (UseMO.isUndef())
948 continue;
949 MachineInstr *UseMI = UseMO.getParent();
950 if (UseMI->isDebugInstr()) {
951 // FIXME These don't have an instruction index. Not clear we have enough
952 // info to decide whether to do this replacement or not. For now do it.
953 UseMO.setReg(NewReg);
954 continue;
955 }
956 SlotIndex UseIdx = LIS->getInstructionIndex(Instr: *UseMI).getRegSlot(EC: true);
957 LiveInterval::iterator US = IntA.FindSegmentContaining(Idx: UseIdx);
958 assert(US != IntA.end() && "Use must be live");
959 if (US->valno != AValNo)
960 continue;
961 // Kill flags are no longer accurate. They are recomputed after RA.
962 UseMO.setIsKill(false);
963 if (NewReg.isPhysical())
964 UseMO.substPhysReg(Reg: NewReg, *TRI);
965 else
966 UseMO.setReg(NewReg);
967 if (UseMI == CopyMI)
968 continue;
969 if (!UseMI->isCopy())
970 continue;
971 if (UseMI->getOperand(i: 0).getReg() != IntB.reg() ||
972 UseMI->getOperand(i: 0).getSubReg())
973 continue;
974
975 // This copy will become a noop. If it's defining a new val#, merge it into
976 // BValNo.
977 SlotIndex DefIdx = UseIdx.getRegSlot();
978 VNInfo *DVNI = IntB.getVNInfoAt(Idx: DefIdx);
979 if (!DVNI)
980 continue;
981 LLVM_DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
982 assert(DVNI->def == DefIdx);
983 BValNo = IntB.MergeValueNumberInto(V1: DVNI, V2: BValNo);
984 for (LiveInterval::SubRange &S : IntB.subranges()) {
985 VNInfo *SubDVNI = S.getVNInfoAt(Idx: DefIdx);
986 if (!SubDVNI)
987 continue;
988 VNInfo *SubBValNo = S.getVNInfoAt(Idx: CopyIdx);
989 assert(SubBValNo->def == CopyIdx);
990 S.MergeValueNumberInto(V1: SubDVNI, V2: SubBValNo);
991 }
992
993 deleteInstr(MI: UseMI);
994 }
995
996 // Extend BValNo by merging in IntA live segments of AValNo. Val# definition
997 // is updated.
998 bool ShrinkB = false;
999 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
1000 if (IntA.hasSubRanges() || IntB.hasSubRanges()) {
1001 if (!IntA.hasSubRanges()) {
1002 LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(Reg: IntA.reg());
1003 IntA.createSubRangeFrom(Allocator, LaneMask: Mask, CopyFrom: IntA);
1004 } else if (!IntB.hasSubRanges()) {
1005 LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(Reg: IntB.reg());
1006 IntB.createSubRangeFrom(Allocator, LaneMask: Mask, CopyFrom: IntB);
1007 }
1008 SlotIndex AIdx = CopyIdx.getRegSlot(EC: true);
1009 LaneBitmask MaskA;
1010 const SlotIndexes &Indexes = *LIS->getSlotIndexes();
1011 for (LiveInterval::SubRange &SA : IntA.subranges()) {
1012 VNInfo *ASubValNo = SA.getVNInfoAt(Idx: AIdx);
1013 // Even if we are dealing with a full copy, some lanes can
1014 // still be undefined.
1015 // E.g.,
1016 // undef A.subLow = ...
1017 // B = COPY A <== A.subHigh is undefined here and does
1018 // not have a value number.
1019 if (!ASubValNo)
1020 continue;
1021 MaskA |= SA.LaneMask;
1022
1023 IntB.refineSubRanges(
1024 Allocator, LaneMask: SA.LaneMask,
1025 Apply: [&Allocator, &SA, CopyIdx, ASubValNo,
1026 &ShrinkB](LiveInterval::SubRange &SR) {
1027 VNInfo *BSubValNo = SR.empty() ? SR.getNextValue(Def: CopyIdx, VNInfoAllocator&: Allocator)
1028 : SR.getVNInfoAt(Idx: CopyIdx);
1029 assert(BSubValNo != nullptr);
1030 auto P = addSegmentsWithValNo(Dst&: SR, DstValNo: BSubValNo, Src: SA, SrcValNo: ASubValNo);
1031 ShrinkB |= P.second;
1032 if (P.first)
1033 BSubValNo->def = ASubValNo->def;
1034 },
1035 Indexes, TRI: *TRI);
1036 }
1037 // Go over all subranges of IntB that have not been covered by IntA,
1038 // and delete the segments starting at CopyIdx. This can happen if
1039 // IntA has undef lanes that are defined in IntB.
1040 for (LiveInterval::SubRange &SB : IntB.subranges()) {
1041 if ((SB.LaneMask & MaskA).any())
1042 continue;
1043 if (LiveRange::Segment *S = SB.getSegmentContaining(Idx: CopyIdx))
1044 if (S->start.getBaseIndex() == CopyIdx.getBaseIndex())
1045 SB.removeSegment(S: *S, RemoveDeadValNo: true);
1046 }
1047 }
1048
1049 BValNo->def = AValNo->def;
1050 auto P = addSegmentsWithValNo(Dst&: IntB, DstValNo: BValNo, Src: IntA, SrcValNo: AValNo);
1051 ShrinkB |= P.second;
1052 LLVM_DEBUG(dbgs() << "\t\textended: " << IntB << '\n');
1053
1054 LIS->removeVRegDefAt(LI&: IntA, Pos: AValNo->def);
1055
1056 LLVM_DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n');
1057 ++numCommutes;
1058 return {true, ShrinkB};
1059}
1060
1061/// For copy B = A in BB2, if A is defined by A = B in BB0 which is a
1062/// predecessor of BB2, and if B is not redefined on the way from A = B
1063/// in BB0 to B = A in BB2, B = A in BB2 is partially redundant if the
1064/// execution goes through the path from BB0 to BB2. We may move B = A
1065/// to the predecessor without such reversed copy.
1066/// So we will transform the program from:
1067/// BB0:
1068/// A = B; BB1:
1069/// ... ...
1070/// / \ /
1071/// BB2:
1072/// ...
1073/// B = A;
1074///
1075/// to:
1076///
1077/// BB0: BB1:
1078/// A = B; ...
1079/// ... B = A;
1080/// / \ /
1081/// BB2:
1082/// ...
1083///
1084/// A special case is when BB0 and BB2 are the same BB which is the only
1085/// BB in a loop:
1086/// BB1:
1087/// ...
1088/// BB0/BB2: ----
1089/// B = A; |
1090/// ... |
1091/// A = B; |
1092/// |-------
1093/// |
1094/// We may hoist B = A from BB0/BB2 to BB1.
1095///
1096/// The major preconditions for correctness to remove such partial
1097/// redundancy include:
1098/// 1. A in B = A in BB2 is defined by a PHI in BB2, and one operand of
1099/// the PHI is defined by the reversed copy A = B in BB0.
1100/// 2. No B is referenced from the start of BB2 to B = A.
1101/// 3. No B is defined from A = B to the end of BB0.
1102/// 4. BB1 has only one successor.
1103///
1104/// 2 and 4 implicitly ensure B is not live at the end of BB1.
1105/// 4 guarantees BB2 is hotter than BB1, so we can only move a copy to a
1106/// colder place, which not only prevent endless loop, but also make sure
1107/// the movement of copy is beneficial.
1108bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP,
1109 MachineInstr &CopyMI) {
1110 assert(!CP.isPhys());
1111 if (!CopyMI.isFullCopy())
1112 return false;
1113
1114 MachineBasicBlock &MBB = *CopyMI.getParent();
1115 // If this block is the target of an invoke/inlineasm_br, moving the copy into
1116 // the predecessor is tricker, and we don't handle it.
1117 if (MBB.isEHPad() || MBB.isInlineAsmBrIndirectTarget())
1118 return false;
1119
1120 if (MBB.pred_size() != 2)
1121 return false;
1122
1123 LiveInterval &IntA =
1124 LIS->getInterval(Reg: CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
1125 LiveInterval &IntB =
1126 LIS->getInterval(Reg: CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
1127
1128 // A is defined by PHI at the entry of MBB.
1129 SlotIndex CopyIdx = LIS->getInstructionIndex(Instr: CopyMI).getRegSlot(EC: true);
1130 VNInfo *AValNo = IntA.getVNInfoAt(Idx: CopyIdx);
1131 assert(AValNo && !AValNo->isUnused() && "COPY source not live");
1132 if (!AValNo->isPHIDef())
1133 return false;
1134
1135 // No B is referenced before CopyMI in MBB.
1136 if (IntB.overlaps(Start: LIS->getMBBStartIdx(mbb: &MBB), End: CopyIdx))
1137 return false;
1138
1139 // MBB has two predecessors: one contains A = B so no copy will be inserted
1140 // for it. The other one will have a copy moved from MBB.
1141 bool FoundReverseCopy = false;
1142 MachineBasicBlock *CopyLeftBB = nullptr;
1143 for (MachineBasicBlock *Pred : MBB.predecessors()) {
1144 VNInfo *PVal = IntA.getVNInfoBefore(Idx: LIS->getMBBEndIdx(mbb: Pred));
1145 MachineInstr *DefMI = LIS->getInstructionFromIndex(index: PVal->def);
1146 if (!DefMI || !DefMI->isFullCopy()) {
1147 CopyLeftBB = Pred;
1148 continue;
1149 }
1150 // Check DefMI is a reverse copy and it is in BB Pred.
1151 if (DefMI->getOperand(i: 0).getReg() != IntA.reg() ||
1152 DefMI->getOperand(i: 1).getReg() != IntB.reg() ||
1153 DefMI->getParent() != Pred) {
1154 CopyLeftBB = Pred;
1155 continue;
1156 }
1157 // If there is any other def of B after DefMI and before the end of Pred,
1158 // we need to keep the copy of B = A at the end of Pred if we remove
1159 // B = A from MBB.
1160 bool ValB_Changed = false;
1161 for (auto *VNI : IntB.valnos) {
1162 if (VNI->isUnused())
1163 continue;
1164 if (PVal->def < VNI->def && VNI->def < LIS->getMBBEndIdx(mbb: Pred)) {
1165 ValB_Changed = true;
1166 break;
1167 }
1168 }
1169 if (ValB_Changed) {
1170 CopyLeftBB = Pred;
1171 continue;
1172 }
1173 FoundReverseCopy = true;
1174 }
1175
1176 // If no reverse copy is found in predecessors, nothing to do.
1177 if (!FoundReverseCopy)
1178 return false;
1179
1180 // If CopyLeftBB is nullptr, it means every predecessor of MBB contains
1181 // reverse copy, CopyMI can be removed trivially if only IntA/IntB is updated.
1182 // If CopyLeftBB is not nullptr, move CopyMI from MBB to CopyLeftBB and
1183 // update IntA/IntB.
1184 //
1185 // If CopyLeftBB is not nullptr, ensure CopyLeftBB has a single succ so
1186 // MBB is hotter than CopyLeftBB.
1187 if (CopyLeftBB && CopyLeftBB->succ_size() > 1)
1188 return false;
1189
1190 // Now (almost sure it's) ok to move copy.
1191 if (CopyLeftBB) {
1192 // Position in CopyLeftBB where we should insert new copy.
1193 auto InsPos = CopyLeftBB->getFirstTerminator();
1194
1195 // Make sure that B isn't referenced in the terminators (if any) at the end
1196 // of the predecessor since we're about to insert a new definition of B
1197 // before them.
1198 if (InsPos != CopyLeftBB->end()) {
1199 SlotIndex InsPosIdx = LIS->getInstructionIndex(Instr: *InsPos).getRegSlot(EC: true);
1200 if (IntB.overlaps(Start: InsPosIdx, End: LIS->getMBBEndIdx(mbb: CopyLeftBB)))
1201 return false;
1202 }
1203
1204 LLVM_DEBUG(dbgs() << "\tremovePartialRedundancy: Move the copy to "
1205 << printMBBReference(*CopyLeftBB) << '\t' << CopyMI);
1206
1207 // Insert new copy to CopyLeftBB.
1208 MachineInstr *NewCopyMI = BuildMI(BB&: *CopyLeftBB, I: InsPos, MIMD: CopyMI.getDebugLoc(),
1209 MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: IntB.reg())
1210 .addReg(RegNo: IntA.reg());
1211 SlotIndex NewCopyIdx =
1212 LIS->InsertMachineInstrInMaps(MI&: *NewCopyMI).getRegSlot();
1213 IntB.createDeadDef(Def: NewCopyIdx, VNIAlloc&: LIS->getVNInfoAllocator());
1214 for (LiveInterval::SubRange &SR : IntB.subranges())
1215 SR.createDeadDef(Def: NewCopyIdx, VNIAlloc&: LIS->getVNInfoAllocator());
1216
1217 // If the newly created Instruction has an address of an instruction that
1218 // was deleted before (object recycled by the allocator) it needs to be
1219 // removed from the deleted list.
1220 ErasedInstrs.erase(Ptr: NewCopyMI);
1221 } else {
1222 LLVM_DEBUG(dbgs() << "\tremovePartialRedundancy: Remove the copy from "
1223 << printMBBReference(MBB) << '\t' << CopyMI);
1224 }
1225
1226 const bool IsUndefCopy = CopyMI.getOperand(i: 1).isUndef();
1227
1228 // Remove CopyMI.
1229 // Note: This is fine to remove the copy before updating the live-ranges.
1230 // While updating the live-ranges, we only look at slot indices and
1231 // never go back to the instruction.
1232 // Mark instructions as deleted.
1233 deleteInstr(MI: &CopyMI);
1234
1235 // Update the liveness.
1236 SmallVector<SlotIndex, 8> EndPoints;
1237 VNInfo *BValNo = IntB.Query(Idx: CopyIdx).valueOutOrDead();
1238 LIS->pruneValue(LR&: *static_cast<LiveRange *>(&IntB), Kill: CopyIdx.getRegSlot(),
1239 EndPoints: &EndPoints);
1240 BValNo->markUnused();
1241
1242 if (IsUndefCopy) {
1243 // We're introducing an undef phi def, and need to set undef on any users of
1244 // the previously local def to avoid artifically extending the lifetime
1245 // through the block.
1246 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg: IntB.reg())) {
1247 const MachineInstr &MI = *MO.getParent();
1248 SlotIndex UseIdx = LIS->getInstructionIndex(Instr: MI);
1249 if (!IntB.liveAt(index: UseIdx))
1250 MO.setIsUndef(true);
1251 }
1252 }
1253
1254 // Extend IntB to the EndPoints of its original live interval.
1255 LIS->extendToIndices(LR&: IntB, Indices: EndPoints);
1256
1257 // Now, do the same for its subranges.
1258 for (LiveInterval::SubRange &SR : IntB.subranges()) {
1259 EndPoints.clear();
1260 VNInfo *BValNo = SR.Query(Idx: CopyIdx).valueOutOrDead();
1261 assert(BValNo && "All sublanes should be live");
1262 LIS->pruneValue(LR&: SR, Kill: CopyIdx.getRegSlot(), EndPoints: &EndPoints);
1263 BValNo->markUnused();
1264 // We can have a situation where the result of the original copy is live,
1265 // but is immediately dead in this subrange, e.g. [336r,336d:0). That makes
1266 // the copy appear as an endpoint from pruneValue(), but we don't want it
1267 // to because the copy has been removed. We can go ahead and remove that
1268 // endpoint; there is no other situation here that there could be a use at
1269 // the same place as we know that the copy is a full copy.
1270 for (unsigned I = 0; I != EndPoints.size();) {
1271 if (SlotIndex::isSameInstr(A: EndPoints[I], B: CopyIdx)) {
1272 EndPoints[I] = EndPoints.back();
1273 EndPoints.pop_back();
1274 continue;
1275 }
1276 ++I;
1277 }
1278 SmallVector<SlotIndex, 8> Undefs;
1279 IntB.computeSubRangeUndefs(Undefs, LaneMask: SR.LaneMask, MRI: *MRI,
1280 Indexes: *LIS->getSlotIndexes());
1281 LIS->extendToIndices(LR&: SR, Indices: EndPoints, Undefs);
1282 }
1283 // If any dead defs were extended, truncate them.
1284 shrinkToUses(LI: &IntB);
1285
1286 // Finally, update the live-range of IntA.
1287 shrinkToUses(LI: &IntA);
1288 return true;
1289}
1290
1291bool RegisterCoalescer::reMaterializeDef(const CoalescerPair &CP,
1292 MachineInstr *CopyMI,
1293 bool &IsDefCopy) {
1294 IsDefCopy = false;
1295 Register SrcReg = CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg();
1296 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx();
1297 Register DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
1298 unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx();
1299 if (SrcReg.isPhysical())
1300 return false;
1301
1302 LiveInterval &SrcInt = LIS->getInterval(Reg: SrcReg);
1303 SlotIndex CopyIdx = LIS->getInstructionIndex(Instr: *CopyMI);
1304 VNInfo *ValNo = SrcInt.Query(Idx: CopyIdx).valueIn();
1305 if (!ValNo)
1306 return false;
1307 if (ValNo->isPHIDef() || ValNo->isUnused())
1308 return false;
1309 MachineInstr *DefMI = LIS->getInstructionFromIndex(index: ValNo->def);
1310 if (!DefMI)
1311 return false;
1312 if (DefMI->isCopyLike()) {
1313 IsDefCopy = true;
1314 return false;
1315 }
1316 if (!TII->isAsCheapAsAMove(MI: *DefMI))
1317 return false;
1318
1319 if (!TII->isReMaterializable(MI: *DefMI))
1320 return false;
1321
1322 bool SawStore = false;
1323 if (!DefMI->isSafeToMove(SawStore))
1324 return false;
1325 const MCInstrDesc &MCID = DefMI->getDesc();
1326 if (MCID.getNumDefs() != 1)
1327 return false;
1328
1329 // If both SrcIdx and DstIdx are set, correct rematerialization would widen
1330 // the register substantially (beyond both source and dest size). This is bad
1331 // for performance since it can cascade through a function, introducing many
1332 // extra spills and fills (e.g. ARM can easily end up copying QQQQPR registers
1333 // around after a few subreg copies).
1334 if (SrcIdx && DstIdx)
1335 return false;
1336
1337 // Only support subregister destinations when the def is read-undef.
1338 MachineOperand &DstOperand = CopyMI->getOperand(i: 0);
1339 Register CopyDstReg = DstOperand.getReg();
1340 if (DstOperand.getSubReg() && !DstOperand.isUndef())
1341 return false;
1342
1343 // In the physical register case, checking that the def is read-undef is not
1344 // enough. We're widening the def and need to avoid clobbering other live
1345 // values in the unused register pieces.
1346 //
1347 // TODO: Targets may support rewriting the rematerialized instruction to only
1348 // touch relevant lanes, in which case we don't need any liveness check.
1349 if (CopyDstReg.isPhysical() && CP.isPartial()) {
1350 for (MCRegUnit Unit : TRI->regunits(Reg: DstReg)) {
1351 // Ignore the register units we are writing anyway.
1352 if (is_contained(Range: TRI->regunits(Reg: CopyDstReg), Element: Unit))
1353 continue;
1354
1355 // Check if the other lanes we are defining are live at the
1356 // rematerialization point.
1357 LiveRange &LR = LIS->getRegUnit(Unit);
1358 if (LR.liveAt(index: CopyIdx))
1359 return false;
1360 }
1361 }
1362
1363 const unsigned DefSubIdx = DefMI->getOperand(i: 0).getSubReg();
1364 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, OpNum: 0);
1365 if (!DefMI->isImplicitDef()) {
1366 if (DstReg.isPhysical()) {
1367 Register NewDstReg = DstReg;
1368
1369 unsigned NewDstIdx = TRI->composeSubRegIndices(a: CP.getSrcIdx(), b: DefSubIdx);
1370 if (NewDstIdx)
1371 NewDstReg = TRI->getSubReg(Reg: DstReg, Idx: NewDstIdx);
1372
1373 // Finally, make sure that the physical subregister that will be
1374 // constructed later is permitted for the instruction.
1375 if (!DefRC->contains(Reg: NewDstReg))
1376 return false;
1377 } else {
1378 // Theoretically, some stack frame reference could exist. Just make sure
1379 // it hasn't actually happened.
1380 assert(DstReg.isVirtual() &&
1381 "Only expect to deal with virtual or physical registers");
1382 }
1383 }
1384
1385 if (!VirtRegAuxInfo::allUsesAvailableAt(MI: DefMI, UseIdx: CopyIdx, LIS: *LIS, MRI: *MRI, TII: *TII))
1386 return false;
1387
1388 DebugLoc DL = CopyMI->getDebugLoc();
1389 MachineBasicBlock *MBB = CopyMI->getParent();
1390 MachineBasicBlock::iterator MII =
1391 std::next(x: MachineBasicBlock::iterator(CopyMI));
1392 LiveRangeEdit::Remat RM(ValNo);
1393 RM.OrigMI = DefMI;
1394 SmallVector<Register, 8> NewRegs;
1395 LiveRangeEdit Edit(&SrcInt, NewRegs, *MF, *LIS, nullptr, this);
1396 Edit.rematerializeAt(MBB&: *MBB, MI: MII, DestReg: DstReg, RM, *TRI, Late: false, SubIdx: SrcIdx, ReplaceIndexMI: CopyMI);
1397 MachineInstr &NewMI = *std::prev(x: MII);
1398 NewMI.setDebugLoc(DL);
1399
1400 // In a situation like the following:
1401 // %0:subreg = instr ; DefMI, subreg = DstIdx
1402 // %1 = copy %0:subreg ; CopyMI, SrcIdx = 0
1403 // instead of widening %1 to the register class of %0 simply do:
1404 // %1 = instr
1405 const TargetRegisterClass *NewRC = CP.getNewRC();
1406 if (DstIdx != 0) {
1407 MachineOperand &DefMO = NewMI.getOperand(i: 0);
1408 if (DefMO.getSubReg() == DstIdx) {
1409 assert(SrcIdx == 0 && CP.isFlipped() &&
1410 "Shouldn't have SrcIdx+DstIdx at this point");
1411 const TargetRegisterClass *DstRC = MRI->getRegClass(Reg: DstReg);
1412 const TargetRegisterClass *CommonRC =
1413 TRI->getCommonSubClass(A: DefRC, B: DstRC);
1414 if (CommonRC != nullptr) {
1415 NewRC = CommonRC;
1416
1417 // Instruction might contain "undef %0:subreg" as use operand:
1418 // %0:subreg = instr op_1, ..., op_N, undef %0:subreg, op_N+2, ...
1419 //
1420 // Need to check all operands.
1421 for (MachineOperand &MO : NewMI.operands()) {
1422 if (MO.isReg() && MO.getReg() == DstReg && MO.getSubReg() == DstIdx) {
1423 MO.setSubReg(0);
1424 }
1425 }
1426
1427 DstIdx = 0;
1428 DefMO.setIsUndef(false); // Only subregs can have def+undef.
1429 }
1430 }
1431 }
1432
1433 // CopyMI may have implicit operands, save them so that we can transfer them
1434 // over to the newly materialized instruction after CopyMI is removed.
1435 SmallVector<MachineOperand, 4> ImplicitOps;
1436 ImplicitOps.reserve(N: CopyMI->getNumOperands() -
1437 CopyMI->getDesc().getNumOperands());
1438 for (unsigned I = CopyMI->getDesc().getNumOperands(),
1439 E = CopyMI->getNumOperands();
1440 I != E; ++I) {
1441 MachineOperand &MO = CopyMI->getOperand(i: I);
1442 if (MO.isReg()) {
1443 assert(MO.isImplicit() &&
1444 "No explicit operands after implicit operands.");
1445 assert((MO.getReg().isPhysical() ||
1446 (MO.getSubReg() == 0 && MO.getReg() == DstOperand.getReg())) &&
1447 "unexpected implicit virtual register def");
1448 ImplicitOps.push_back(Elt: MO);
1449 }
1450 }
1451
1452 CopyMI->eraseFromParent();
1453 ErasedInstrs.insert(Ptr: CopyMI);
1454
1455 // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
1456 // We need to remember these so we can add intervals once we insert
1457 // NewMI into SlotIndexes.
1458 //
1459 // We also expect to have tied implicit-defs of super registers originating
1460 // from SUBREG_TO_REG, such as:
1461 // $edi = MOV32r0 implicit-def dead $eflags, implicit-def $rdi
1462 // undef %0.sub_32bit = MOV32r0 implicit-def dead $eflags, implicit-def %0
1463 //
1464 // The implicit-def of the super register may have been reduced to
1465 // subregisters depending on the uses.
1466 SmallVector<std::pair<unsigned, Register>, 4> NewMIImplDefs;
1467 for (unsigned i = NewMI.getDesc().getNumOperands(),
1468 e = NewMI.getNumOperands();
1469 i != e; ++i) {
1470 MachineOperand &MO = NewMI.getOperand(i);
1471 if (MO.isReg() && MO.isDef()) {
1472 assert(MO.isImplicit());
1473 if (MO.getReg().isPhysical()) {
1474 assert(MO.isImplicit() && MO.getReg().isPhysical() &&
1475 (MO.isDead() ||
1476 (DefSubIdx &&
1477 ((TRI->getSubReg(MO.getReg(), DefSubIdx) ==
1478 MCRegister((unsigned)NewMI.getOperand(0).getReg())) ||
1479 TRI->isSubRegisterEq(NewMI.getOperand(0).getReg(),
1480 MO.getReg())))));
1481 NewMIImplDefs.push_back(Elt: {i, MO.getReg()});
1482 } else {
1483 assert(MO.getReg() == NewMI.getOperand(0).getReg());
1484
1485 // We're only expecting another def of the main output, so the range
1486 // should get updated with the regular output range.
1487 //
1488 // FIXME: The range updating below probably needs updating to look at
1489 // the super register if subranges are tracked.
1490 assert(!MRI->shouldTrackSubRegLiveness(DstReg) &&
1491 "subrange update for implicit-def of super register may not be "
1492 "properly handled");
1493 }
1494 }
1495 }
1496
1497 if (DstReg.isVirtual()) {
1498 unsigned NewIdx = NewMI.getOperand(i: 0).getSubReg();
1499
1500 if (DefRC != nullptr) {
1501 if (NewIdx)
1502 NewRC = TRI->getMatchingSuperRegClass(A: NewRC, B: DefRC, Idx: NewIdx);
1503 else
1504 NewRC = TRI->getCommonSubClass(A: NewRC, B: DefRC);
1505 assert(NewRC && "subreg chosen for remat incompatible with instruction");
1506 }
1507
1508 // Remap subranges to new lanemask and change register class.
1509 LiveInterval &DstInt = LIS->getInterval(Reg: DstReg);
1510 for (LiveInterval::SubRange &SR : DstInt.subranges()) {
1511 SR.LaneMask = TRI->composeSubRegIndexLaneMask(IdxA: DstIdx, Mask: SR.LaneMask);
1512 }
1513 MRI->setRegClass(Reg: DstReg, RC: NewRC);
1514
1515 // Update machine operands and add flags.
1516 updateRegDefsUses(SrcReg: DstReg, DstReg, SubIdx: DstIdx);
1517 NewMI.getOperand(i: 0).setSubReg(NewIdx);
1518 // updateRegDefUses can add an "undef" flag to the definition, since
1519 // it will replace DstReg with DstReg.DstIdx. If NewIdx is 0, make
1520 // sure that "undef" is not set.
1521 if (NewIdx == 0)
1522 NewMI.getOperand(i: 0).setIsUndef(false);
1523
1524 // In a situation like the following:
1525 //
1526 // undef %2.subreg:reg = INST %1:reg ; DefMI (rematerializable),
1527 // ; Defines only some of lanes,
1528 // ; so DefSubIdx = NewIdx = subreg
1529 // %3:reg = COPY %2 ; Copy full reg
1530 // .... = SOMEINSTR %3:reg ; Use full reg
1531 //
1532 // there are no subranges for %3 so after rematerialization we need
1533 // to explicitly create them. Undefined subranges are removed later on.
1534 if (NewIdx && !DstInt.hasSubRanges() &&
1535 MRI->shouldTrackSubRegLiveness(VReg: DstReg)) {
1536 LaneBitmask FullMask = MRI->getMaxLaneMaskForVReg(Reg: DstReg);
1537 LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask(SubIdx: NewIdx);
1538 LaneBitmask UnusedLanes = FullMask & ~UsedLanes;
1539 VNInfo::Allocator &Alloc = LIS->getVNInfoAllocator();
1540 DstInt.createSubRangeFrom(Allocator&: Alloc, LaneMask: UsedLanes, CopyFrom: DstInt);
1541 DstInt.createSubRangeFrom(Allocator&: Alloc, LaneMask: UnusedLanes, CopyFrom: DstInt);
1542 }
1543
1544 // Add dead subregister definitions if we are defining the whole register
1545 // but only part of it is live.
1546 // This could happen if the rematerialization instruction is rematerializing
1547 // more than actually is used in the register.
1548 // An example would be:
1549 // %1 = LOAD CONSTANTS 5, 8 ; Loading both 5 and 8 in different subregs
1550 // ; Copying only part of the register here, but the rest is undef.
1551 // %2:sub_16bit<def, read-undef> = COPY %1:sub_16bit
1552 // ==>
1553 // ; Materialize all the constants but only using one
1554 // %2 = LOAD_CONSTANTS 5, 8
1555 //
1556 // at this point for the part that wasn't defined before we could have
1557 // subranges missing the definition.
1558 if (NewIdx == 0 && DstInt.hasSubRanges()) {
1559 SlotIndex CurrIdx = LIS->getInstructionIndex(Instr: NewMI);
1560 SlotIndex DefIndex =
1561 CurrIdx.getRegSlot(EC: NewMI.getOperand(i: 0).isEarlyClobber());
1562 LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg: DstReg);
1563 VNInfo::Allocator &Alloc = LIS->getVNInfoAllocator();
1564 for (LiveInterval::SubRange &SR : DstInt.subranges()) {
1565 if (!SR.liveAt(index: DefIndex))
1566 SR.createDeadDef(Def: DefIndex, VNIAlloc&: Alloc);
1567 MaxMask &= ~SR.LaneMask;
1568 }
1569 if (MaxMask.any()) {
1570 LiveInterval::SubRange *SR = DstInt.createSubRange(Allocator&: Alloc, LaneMask: MaxMask);
1571 SR->createDeadDef(Def: DefIndex, VNIAlloc&: Alloc);
1572 }
1573 }
1574
1575 // Make sure that the subrange for resultant undef is removed
1576 // For example:
1577 // %1:sub1<def,read-undef> = LOAD CONSTANT 1
1578 // %2 = COPY %1
1579 // ==>
1580 // %2:sub1<def, read-undef> = LOAD CONSTANT 1
1581 // ; Correct but need to remove the subrange for %2:sub0
1582 // ; as it is now undef
1583 if (NewIdx != 0 && DstInt.hasSubRanges()) {
1584 // The affected subregister segments can be removed.
1585 SlotIndex CurrIdx = LIS->getInstructionIndex(Instr: NewMI);
1586 LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(SubIdx: NewIdx);
1587 bool UpdatedSubRanges = false;
1588 SlotIndex DefIndex =
1589 CurrIdx.getRegSlot(EC: NewMI.getOperand(i: 0).isEarlyClobber());
1590 VNInfo::Allocator &Alloc = LIS->getVNInfoAllocator();
1591
1592 // Refine the subranges that are now defined by the remat.
1593 // This will split existing subranges if necessary.
1594 DstInt.refineSubRanges(
1595 Allocator&: Alloc, LaneMask: DstMask,
1596 Apply: [&DefIndex, &Alloc](LiveInterval::SubRange &SR) {
1597 // We know that this lane is defined by this instruction,
1598 // but at this point it might not be live because it was not defined
1599 // by the original instruction. This happens when the
1600 // rematerialization widens the defined register. Assign that lane a
1601 // dead def so that the interferences are properly modeled.
1602 if (!SR.liveAt(index: DefIndex))
1603 SR.createDeadDef(Def: DefIndex, VNIAlloc&: Alloc);
1604 },
1605 Indexes: *LIS->getSlotIndexes(), TRI: *TRI);
1606
1607 for (LiveInterval::SubRange &SR : DstInt.subranges()) {
1608 if ((SR.LaneMask & DstMask).none()) {
1609 LLVM_DEBUG(dbgs()
1610 << "Removing undefined SubRange "
1611 << PrintLaneMask(SR.LaneMask) << " : " << SR << "\n");
1612
1613 if (VNInfo *RmValNo = SR.getVNInfoAt(Idx: CurrIdx.getRegSlot())) {
1614 // VNI is in ValNo - remove any segments in this SubRange that have
1615 // this ValNo
1616 SR.removeValNo(ValNo: RmValNo);
1617 }
1618
1619 // We may not have a defined value at this point, but still need to
1620 // clear out any empty subranges tentatively created by
1621 // updateRegDefUses. The original subrange def may have only undefed
1622 // some lanes.
1623 UpdatedSubRanges = true;
1624 }
1625 }
1626 if (UpdatedSubRanges)
1627 DstInt.removeEmptySubRanges();
1628 }
1629 } else if (NewMI.getOperand(i: 0).getReg() != CopyDstReg) {
1630 // The New instruction may be defining a sub-register of what's actually
1631 // been asked for. If so it must implicitly define the whole thing.
1632 assert(DstReg.isPhysical() &&
1633 "Only expect virtual or physical registers in remat");
1634
1635 // When we're rematerializing into a not-quite-right register we already add
1636 // the real definition as an implicit-def, but we should also be marking the
1637 // "official" register as dead, since nothing else is going to use it as a
1638 // result of this remat. Not doing this can affect pressure tracking.
1639 NewMI.getOperand(i: 0).setIsDead(true);
1640
1641 bool HasDefMatchingCopy = false;
1642 for (auto [OpIndex, Reg] : NewMIImplDefs) {
1643 if (Reg != DstReg)
1644 continue;
1645 // Also, if CopyDstReg is a sub-register of DstReg (and it is defined), we
1646 // must mark DstReg as dead since it is not going to used as a result of
1647 // this remat.
1648 if (DstReg != CopyDstReg)
1649 NewMI.getOperand(i: OpIndex).setIsDead(true);
1650 else
1651 HasDefMatchingCopy = true;
1652 }
1653
1654 // If NewMI does not already have an implicit-def CopyDstReg add one now.
1655 if (!HasDefMatchingCopy)
1656 NewMI.addOperand(Op: MachineOperand::CreateReg(
1657 Reg: CopyDstReg, isDef: true /*IsDef*/, isImp: true /*IsImp*/, isKill: false /*IsKill*/));
1658
1659 // Record small dead def live-ranges for all the subregisters
1660 // of the destination register.
1661 // Otherwise, variables that live through may miss some
1662 // interferences, thus creating invalid allocation.
1663 // E.g., i386 code:
1664 // %1 = somedef ; %1 GR8
1665 // %2 = remat ; %2 GR32
1666 // CL = COPY %2.sub_8bit
1667 // = somedef %1 ; %1 GR8
1668 // =>
1669 // %1 = somedef ; %1 GR8
1670 // dead ECX = remat ; implicit-def CL
1671 // = somedef %1 ; %1 GR8
1672 // %1 will see the interferences with CL but not with CH since
1673 // no live-ranges would have been created for ECX.
1674 // Fix that!
1675 SlotIndex NewMIIdx = LIS->getInstructionIndex(Instr: NewMI);
1676 for (MCRegUnit Unit : TRI->regunits(Reg: NewMI.getOperand(i: 0).getReg()))
1677 if (LiveRange *LR = LIS->getCachedRegUnit(Unit))
1678 LR->createDeadDef(Def: NewMIIdx.getRegSlot(), VNIAlloc&: LIS->getVNInfoAllocator());
1679 }
1680
1681 NewMI.setRegisterDefReadUndef(Reg: NewMI.getOperand(i: 0).getReg());
1682
1683 // Transfer over implicit operands to the rematerialized instruction.
1684 for (MachineOperand &MO : ImplicitOps)
1685 NewMI.addOperand(Op: MO);
1686
1687 SlotIndex NewMIIdx = LIS->getInstructionIndex(Instr: NewMI);
1688 for (Register Reg : make_second_range(c&: NewMIImplDefs)) {
1689 for (MCRegUnit Unit : TRI->regunits(Reg: Reg.asMCReg()))
1690 if (LiveRange *LR = LIS->getCachedRegUnit(Unit))
1691 LR->createDeadDef(Def: NewMIIdx.getRegSlot(), VNIAlloc&: LIS->getVNInfoAllocator());
1692 }
1693
1694 LLVM_DEBUG(dbgs() << "Remat: " << NewMI);
1695 ++NumReMats;
1696
1697 // If the virtual SrcReg is completely eliminated, update all DBG_VALUEs
1698 // to describe DstReg instead.
1699 if (MRI->use_nodbg_empty(RegNo: SrcReg)) {
1700 for (MachineOperand &UseMO :
1701 llvm::make_early_inc_range(Range: MRI->use_operands(Reg: SrcReg))) {
1702 MachineInstr *UseMI = UseMO.getParent();
1703 if (UseMI->isDebugInstr()) {
1704 if (DstReg.isPhysical())
1705 UseMO.substPhysReg(Reg: DstReg, *TRI);
1706 else
1707 UseMO.setReg(DstReg);
1708 // Move the debug value directly after the def of the rematerialized
1709 // value in DstReg.
1710 MBB->splice(Where: std::next(x: NewMI.getIterator()), Other: UseMI->getParent(), From: UseMI);
1711 LLVM_DEBUG(dbgs() << "\t\tupdated: " << *UseMI);
1712 }
1713 }
1714 }
1715
1716 if (ToBeUpdated.count(V: SrcReg))
1717 return true;
1718
1719 unsigned NumCopyUses = 0;
1720 for (MachineOperand &UseMO : MRI->use_nodbg_operands(Reg: SrcReg)) {
1721 if (UseMO.getParent()->isCopyLike())
1722 NumCopyUses++;
1723 }
1724 if (NumCopyUses < LateRematUpdateThreshold) {
1725 // The source interval can become smaller because we removed a use.
1726 shrinkToUses(LI: &SrcInt, Dead: &DeadDefs);
1727 if (!DeadDefs.empty())
1728 eliminateDeadDefs(Edit: &Edit);
1729 } else {
1730 ToBeUpdated.insert(V: SrcReg);
1731 }
1732 return true;
1733}
1734
1735MachineInstr *RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
1736 // ProcessImplicitDefs may leave some copies of <undef> values, it only
1737 // removes local variables. When we have a copy like:
1738 //
1739 // %1 = COPY undef %2
1740 //
1741 // We delete the copy and remove the corresponding value number from %1.
1742 // Any uses of that value number are marked as <undef>.
1743
1744 // Note that we do not query CoalescerPair here but redo isMoveInstr as the
1745 // CoalescerPair may have a new register class with adjusted subreg indices
1746 // at this point.
1747 Register SrcReg, DstReg;
1748 unsigned SrcSubIdx = 0, DstSubIdx = 0;
1749 if (!isMoveInstr(tri: *TRI, MI: CopyMI, Src&: SrcReg, Dst&: DstReg, SrcSub&: SrcSubIdx, DstSub&: DstSubIdx))
1750 return nullptr;
1751
1752 SlotIndex Idx = LIS->getInstructionIndex(Instr: *CopyMI);
1753 const LiveInterval &SrcLI = LIS->getInterval(Reg: SrcReg);
1754 // CopyMI is undef iff SrcReg is not live before the instruction.
1755 if (SrcSubIdx != 0 && SrcLI.hasSubRanges()) {
1756 LaneBitmask SrcMask = TRI->getSubRegIndexLaneMask(SubIdx: SrcSubIdx);
1757 for (const LiveInterval::SubRange &SR : SrcLI.subranges()) {
1758 if ((SR.LaneMask & SrcMask).none())
1759 continue;
1760 if (SR.liveAt(index: Idx))
1761 return nullptr;
1762 }
1763 } else if (SrcLI.liveAt(index: Idx))
1764 return nullptr;
1765
1766 // If the undef copy defines a live-out value (i.e. an input to a PHI def),
1767 // then replace it with an IMPLICIT_DEF.
1768 LiveInterval &DstLI = LIS->getInterval(Reg: DstReg);
1769 SlotIndex RegIndex = Idx.getRegSlot();
1770 LiveRange::Segment *Seg = DstLI.getSegmentContaining(Idx: RegIndex);
1771 assert(Seg != nullptr && "No segment for defining instruction");
1772 VNInfo *V = DstLI.getVNInfoAt(Idx: Seg->end);
1773
1774 // The source interval may also have been on an undef use, in which case the
1775 // copy introduced a live value.
1776 if (((V && V->isPHIDef()) || (!V && !DstLI.liveAt(index: Idx)))) {
1777 for (unsigned i = CopyMI->getNumOperands(); i != 0; --i) {
1778 MachineOperand &MO = CopyMI->getOperand(i: i - 1);
1779 if (MO.isReg()) {
1780 if (MO.isUse())
1781 CopyMI->removeOperand(OpNo: i - 1);
1782 } else {
1783 assert(MO.isImm() &&
1784 CopyMI->getOpcode() == TargetOpcode::SUBREG_TO_REG);
1785 CopyMI->removeOperand(OpNo: i - 1);
1786 }
1787 }
1788
1789 CopyMI->setDesc(TII->get(Opcode: TargetOpcode::IMPLICIT_DEF));
1790 LLVM_DEBUG(dbgs() << "\tReplaced copy of <undef> value with an "
1791 "implicit def\n");
1792 return CopyMI;
1793 }
1794
1795 // Remove any DstReg segments starting at the instruction.
1796 LLVM_DEBUG(dbgs() << "\tEliminating copy of <undef> value\n");
1797
1798 // Remove value or merge with previous one in case of a subregister def.
1799 if (VNInfo *PrevVNI = DstLI.getVNInfoAt(Idx)) {
1800 VNInfo *VNI = DstLI.getVNInfoAt(Idx: RegIndex);
1801 DstLI.MergeValueNumberInto(V1: VNI, V2: PrevVNI);
1802
1803 // The affected subregister segments can be removed.
1804 LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(SubIdx: DstSubIdx);
1805 for (LiveInterval::SubRange &SR : DstLI.subranges()) {
1806 if ((SR.LaneMask & DstMask).none())
1807 continue;
1808
1809 VNInfo *SVNI = SR.getVNInfoAt(Idx: RegIndex);
1810 assert(SVNI != nullptr && SlotIndex::isSameInstr(SVNI->def, RegIndex));
1811 SR.removeValNo(ValNo: SVNI);
1812 }
1813 DstLI.removeEmptySubRanges();
1814 } else
1815 LIS->removeVRegDefAt(LI&: DstLI, Pos: RegIndex);
1816
1817 // Mark uses as undef.
1818 for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg: DstReg)) {
1819 if (MO.isDef() /*|| MO.isUndef()*/)
1820 continue;
1821 const MachineInstr &MI = *MO.getParent();
1822 SlotIndex UseIdx = LIS->getInstructionIndex(Instr: MI);
1823 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubIdx: MO.getSubReg());
1824 bool isLive;
1825 if (!UseMask.all() && DstLI.hasSubRanges()) {
1826 isLive = false;
1827 for (const LiveInterval::SubRange &SR : DstLI.subranges()) {
1828 if ((SR.LaneMask & UseMask).none())
1829 continue;
1830 if (SR.liveAt(index: UseIdx)) {
1831 isLive = true;
1832 break;
1833 }
1834 }
1835 } else
1836 isLive = DstLI.liveAt(index: UseIdx);
1837 if (isLive)
1838 continue;
1839 MO.setIsUndef(true);
1840 LLVM_DEBUG(dbgs() << "\tnew undef: " << UseIdx << '\t' << MI);
1841 }
1842
1843 // A def of a subregister may be a use of the other subregisters, so
1844 // deleting a def of a subregister may also remove uses. Since CopyMI
1845 // is still part of the function (but about to be erased), mark all
1846 // defs of DstReg in it as <undef>, so that shrinkToUses would
1847 // ignore them.
1848 for (MachineOperand &MO : CopyMI->all_defs())
1849 if (MO.getReg() == DstReg)
1850 MO.setIsUndef(true);
1851 LIS->shrinkToUses(li: &DstLI);
1852
1853 return CopyMI;
1854}
1855
1856void RegisterCoalescer::addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
1857 MachineOperand &MO, unsigned SubRegIdx) {
1858 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubIdx: SubRegIdx);
1859 if (MO.isDef())
1860 Mask = ~Mask;
1861 bool IsUndef = true;
1862 for (const LiveInterval::SubRange &S : Int.subranges()) {
1863 if ((S.LaneMask & Mask).none())
1864 continue;
1865 if (S.liveAt(index: UseIdx)) {
1866 IsUndef = false;
1867 break;
1868 }
1869 }
1870 if (IsUndef) {
1871 MO.setIsUndef(true);
1872 // We found out some subregister use is actually reading an undefined
1873 // value. In some cases the whole vreg has become undefined at this
1874 // point so we have to potentially shrink the main range if the
1875 // use was ending a live segment there.
1876 LiveQueryResult Q = Int.Query(Idx: UseIdx);
1877 if (Q.valueOut() == nullptr)
1878 ShrinkMainRange = true;
1879 }
1880}
1881
1882void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg,
1883 unsigned SubIdx) {
1884 bool DstIsPhys = DstReg.isPhysical();
1885 LiveInterval *DstInt = DstIsPhys ? nullptr : &LIS->getInterval(Reg: DstReg);
1886
1887 if (DstInt && DstReg != SrcReg) {
1888 bool HasSubRanges = DstInt->hasSubRanges();
1889 for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg: DstReg)) {
1890 if (MO.isUndef())
1891 continue;
1892 unsigned SubReg = MO.getSubReg();
1893 if (SubReg == 0 && MO.isDef())
1894 continue;
1895
1896 SlotIndex UseIdx =
1897 LIS->getInstructionIndex(Instr: *MO.getParent()).getRegSlot(EC: true);
1898 if (HasSubRanges) {
1899 addUndefFlag(Int: *DstInt, UseIdx, MO, SubRegIdx: SubReg);
1900 } else if (MO.isUse() && SubReg == 0 && !DstInt->liveAt(index: UseIdx)) {
1901 // A full-register use already referencing DstReg (not renamed from
1902 // SrcReg) may have no reaching def after the join if its feeding COPY
1903 // and erasable IMPLICIT_DEF were removed. Mark such uses undef; the
1904 // SrcReg rename loop below only visits SrcReg operands and will miss
1905 // these.
1906 MO.setIsUndef(true);
1907 }
1908 }
1909 }
1910
1911 SmallPtrSet<MachineInstr *, 8> Visited;
1912 for (MachineRegisterInfo::reg_instr_iterator I = MRI->reg_instr_begin(RegNo: SrcReg),
1913 E = MRI->reg_instr_end();
1914 I != E;) {
1915 MachineInstr *UseMI = &*(I++);
1916
1917 // Each instruction can only be rewritten once because sub-register
1918 // composition is not always idempotent. When SrcReg != DstReg, rewriting
1919 // the UseMI operands removes them from the SrcReg use-def chain, but when
1920 // SrcReg is DstReg we could encounter UseMI twice if it has multiple
1921 // operands mentioning the virtual register.
1922 if (SrcReg == DstReg && !Visited.insert(Ptr: UseMI).second)
1923 continue;
1924
1925 SmallVector<unsigned, 8> Ops;
1926 bool Reads, Writes;
1927 std::tie(args&: Reads, args&: Writes) = UseMI->readsWritesVirtualRegister(Reg: SrcReg, Ops: &Ops);
1928
1929 // If SrcReg wasn't read, it may still be the case that DstReg is live-in
1930 // because SrcReg is a sub-register.
1931 if (DstInt && !Reads && SubIdx && !UseMI->isDebugInstr())
1932 Reads = DstInt->liveAt(index: LIS->getInstructionIndex(Instr: *UseMI));
1933
1934 // Replace SrcReg with DstReg in all UseMI operands.
1935 for (unsigned Op : Ops) {
1936 MachineOperand &MO = UseMI->getOperand(i: Op);
1937
1938 // Adjust <undef> flags in case of sub-register joins. We don't want to
1939 // turn a full def into a read-modify-write sub-register def and vice
1940 // versa.
1941 if (SubIdx && MO.isDef())
1942 MO.setIsUndef(!Reads);
1943
1944 // A subreg use of a partially undef (super) register may be a complete
1945 // undef use now and then has to be marked that way.
1946 if (MO.isUse() && !MO.isUndef() && !DstIsPhys) {
1947 unsigned SubUseIdx = TRI->composeSubRegIndices(a: SubIdx, b: MO.getSubReg());
1948 if (SubUseIdx != 0 && MRI->shouldTrackSubRegLiveness(VReg: DstReg)) {
1949 if (!DstInt->hasSubRanges()) {
1950 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
1951 LaneBitmask FullMask = MRI->getMaxLaneMaskForVReg(Reg: DstInt->reg());
1952 LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask(SubIdx);
1953 LaneBitmask UnusedLanes = FullMask & ~UsedLanes;
1954 DstInt->createSubRangeFrom(Allocator, LaneMask: UsedLanes, CopyFrom: *DstInt);
1955 // The unused lanes are just empty live-ranges at this point.
1956 // It is the caller responsibility to set the proper
1957 // dead segments if there is an actual dead def of the
1958 // unused lanes. This may happen with rematerialization.
1959 DstInt->createSubRange(Allocator, LaneMask: UnusedLanes);
1960 }
1961 SlotIndex MIIdx = UseMI->isDebugInstr()
1962 ? LIS->getSlotIndexes()->getIndexBefore(MI: *UseMI)
1963 : LIS->getInstructionIndex(Instr: *UseMI);
1964 SlotIndex UseIdx = MIIdx.getRegSlot(EC: true);
1965 addUndefFlag(Int: *DstInt, UseIdx, MO, SubRegIdx: SubUseIdx);
1966 }
1967 }
1968
1969 if (DstIsPhys)
1970 MO.substPhysReg(Reg: DstReg, *TRI);
1971 else
1972 MO.substVirtReg(Reg: DstReg, SubIdx, *TRI);
1973 }
1974
1975 LLVM_DEBUG({
1976 dbgs() << "\t\tupdated: ";
1977 if (!UseMI->isDebugInstr())
1978 dbgs() << LIS->getInstructionIndex(*UseMI) << "\t";
1979 dbgs() << *UseMI;
1980 });
1981 }
1982}
1983
1984bool RegisterCoalescer::canJoinPhys(const CoalescerPair &CP) {
1985 // Always join simple intervals that are defined by a single copy from a
1986 // reserved register. This doesn't increase register pressure, so it is
1987 // always beneficial.
1988 if (!MRI->isReserved(PhysReg: CP.getDstReg())) {
1989 LLVM_DEBUG(dbgs() << "\tCan only merge into reserved registers.\n");
1990 return false;
1991 }
1992
1993 LiveInterval &JoinVInt = LIS->getInterval(Reg: CP.getSrcReg());
1994 if (JoinVInt.containsOneValue())
1995 return true;
1996
1997 LLVM_DEBUG(
1998 dbgs() << "\tCannot join complex intervals into reserved register.\n");
1999 return false;
2000}
2001
2002bool RegisterCoalescer::copyValueUndefInPredecessors(
2003 LiveRange &S, const MachineBasicBlock *MBB, LiveQueryResult SLRQ) {
2004 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
2005 SlotIndex PredEnd = LIS->getMBBEndIdx(mbb: Pred);
2006 if (VNInfo *V = S.getVNInfoAt(Idx: PredEnd.getPrevSlot())) {
2007 // If this is a self loop, we may be reading the same value.
2008 if (V->id != SLRQ.valueOutOrDead()->id)
2009 return false;
2010 }
2011 }
2012
2013 return true;
2014}
2015
2016void RegisterCoalescer::setUndefOnPrunedSubRegUses(LiveInterval &LI,
2017 Register Reg,
2018 LaneBitmask PrunedLanes) {
2019 // If we had other instructions in the segment reading the undef sublane
2020 // value, we need to mark them with undef.
2021 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
2022 unsigned SubRegIdx = MO.getSubReg();
2023 if (SubRegIdx == 0 || MO.isUndef())
2024 continue;
2025
2026 LaneBitmask SubRegMask = TRI->getSubRegIndexLaneMask(SubIdx: SubRegIdx);
2027 SlotIndex Pos = LIS->getInstructionIndex(Instr: *MO.getParent());
2028 for (LiveInterval::SubRange &S : LI.subranges()) {
2029 if (!S.liveAt(index: Pos) && (PrunedLanes & SubRegMask).any()) {
2030 MO.setIsUndef();
2031 break;
2032 }
2033 }
2034 }
2035
2036 LI.removeEmptySubRanges();
2037
2038 // A def of a subregister may be a use of other register lanes. Replacing
2039 // such a def with a def of a different register will eliminate the use,
2040 // and may cause the recorded live range to be larger than the actual
2041 // liveness in the program IR.
2042 LIS->shrinkToUses(li: &LI);
2043}
2044
2045bool RegisterCoalescer::joinCopy(
2046 MachineInstr *CopyMI, bool &Again,
2047 SmallPtrSetImpl<MachineInstr *> &CurrentErasedInstrs) {
2048 Again = false;
2049 LLVM_DEBUG(dbgs() << LIS->getInstructionIndex(*CopyMI) << '\t' << *CopyMI);
2050
2051 CoalescerPair CP(*TRI);
2052 if (!CP.setRegisters(CopyMI)) {
2053 LLVM_DEBUG(dbgs() << "\tNot coalescable.\n");
2054 return false;
2055 }
2056
2057 if (CP.getNewRC()) {
2058 if (RegClassInfo.getNumAllocatableRegs(RC: CP.getNewRC()) == 0) {
2059 LLVM_DEBUG(dbgs() << "\tNo " << TRI->getRegClassName(CP.getNewRC())
2060 << "are available for allocation\n");
2061 return false;
2062 }
2063
2064 auto SrcRC = MRI->getRegClass(Reg: CP.getSrcReg());
2065 auto DstRC = MRI->getRegClass(Reg: CP.getDstReg());
2066 unsigned SrcIdx = CP.getSrcIdx();
2067 unsigned DstIdx = CP.getDstIdx();
2068 if (CP.isFlipped()) {
2069 std::swap(a&: SrcIdx, b&: DstIdx);
2070 std::swap(a&: SrcRC, b&: DstRC);
2071 }
2072 if (!TRI->shouldCoalesce(MI: CopyMI, SrcRC, SubReg: SrcIdx, DstRC, DstSubReg: DstIdx,
2073 NewRC: CP.getNewRC(), LIS&: *LIS)) {
2074 LLVM_DEBUG(dbgs() << "\tSubtarget bailed on coalescing.\n");
2075 return false;
2076 }
2077 }
2078
2079 // Dead code elimination. This really should be handled by MachineDCE, but
2080 // sometimes dead copies slip through, and we can't generate invalid live
2081 // ranges.
2082 if (!CP.isPhys() && CopyMI->allDefsAreDead()) {
2083 LLVM_DEBUG(dbgs() << "\tCopy is dead.\n");
2084 DeadDefs.push_back(Elt: CopyMI);
2085 eliminateDeadDefs();
2086 return true;
2087 }
2088
2089 // Eliminate undefs.
2090 if (!CP.isPhys()) {
2091 // If this is an IMPLICIT_DEF, leave it alone, but don't try to coalesce.
2092 if (MachineInstr *UndefMI = eliminateUndefCopy(CopyMI)) {
2093 if (UndefMI->isImplicitDef())
2094 return false;
2095 deleteInstr(MI: CopyMI);
2096 return false; // Not coalescable.
2097 }
2098 }
2099
2100 // Coalesced copies are normally removed immediately, but transformations
2101 // like removeCopyByCommutingDef() can inadvertently create identity copies.
2102 // When that happens, just join the values and remove the copy.
2103 if (CP.getSrcReg() == CP.getDstReg()) {
2104 LiveInterval &LI = LIS->getInterval(Reg: CP.getSrcReg());
2105 LLVM_DEBUG(dbgs() << "\tCopy already coalesced: " << LI << '\n');
2106 const SlotIndex CopyIdx = LIS->getInstructionIndex(Instr: *CopyMI);
2107 LiveQueryResult LRQ = LI.Query(Idx: CopyIdx);
2108 if (VNInfo *DefVNI = LRQ.valueDefined()) {
2109 VNInfo *ReadVNI = LRQ.valueIn();
2110 assert(ReadVNI && "No value before copy and no <undef> flag.");
2111 assert(ReadVNI != DefVNI && "Cannot read and define the same value.");
2112
2113 // Track incoming undef lanes we need to eliminate from the subrange.
2114 LaneBitmask PrunedLanes;
2115 MachineBasicBlock *MBB = CopyMI->getParent();
2116
2117 // Process subregister liveranges.
2118 for (LiveInterval::SubRange &S : LI.subranges()) {
2119 LiveQueryResult SLRQ = S.Query(Idx: CopyIdx);
2120 if (VNInfo *SDefVNI = SLRQ.valueDefined()) {
2121 if (VNInfo *SReadVNI = SLRQ.valueIn())
2122 SDefVNI = S.MergeValueNumberInto(V1: SDefVNI, V2: SReadVNI);
2123
2124 // If this copy introduced an undef subrange from an incoming value,
2125 // we need to eliminate the undef live in values from the subrange.
2126 if (copyValueUndefInPredecessors(S, MBB, SLRQ)) {
2127 LLVM_DEBUG(dbgs() << "Incoming sublane value is undef at copy\n");
2128 PrunedLanes |= S.LaneMask;
2129 S.removeValNo(ValNo: SDefVNI);
2130 }
2131 }
2132 }
2133
2134 LI.MergeValueNumberInto(V1: DefVNI, V2: ReadVNI);
2135 if (PrunedLanes.any()) {
2136 LLVM_DEBUG(dbgs() << "Pruning undef incoming lanes: " << PrunedLanes
2137 << '\n');
2138 setUndefOnPrunedSubRegUses(LI, Reg: CP.getSrcReg(), PrunedLanes);
2139 }
2140
2141 LLVM_DEBUG(dbgs() << "\tMerged values: " << LI << '\n');
2142 }
2143 deleteInstr(MI: CopyMI);
2144 return true;
2145 }
2146
2147 // Enforce policies.
2148 if (CP.isPhys()) {
2149 LLVM_DEBUG(dbgs() << "\tConsidering merging "
2150 << printReg(CP.getSrcReg(), TRI) << " with "
2151 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n');
2152 if (!canJoinPhys(CP)) {
2153 // Before giving up coalescing, try rematerializing the source of
2154 // the copy instead if it is cheap.
2155 bool IsDefCopy = false;
2156 if (reMaterializeDef(CP, CopyMI, IsDefCopy))
2157 return true;
2158 if (IsDefCopy)
2159 Again = true; // May be possible to coalesce later.
2160 return false;
2161 }
2162 } else {
2163 // When possible, let DstReg be the larger interval.
2164 if (!CP.isPartial() && LIS->getInterval(Reg: CP.getSrcReg()).size() >
2165 LIS->getInterval(Reg: CP.getDstReg()).size())
2166 CP.flip();
2167
2168 LLVM_DEBUG({
2169 dbgs() << "\tConsidering merging to "
2170 << TRI->getRegClassName(CP.getNewRC()) << " with ";
2171 if (CP.getDstIdx() && CP.getSrcIdx())
2172 dbgs() << printReg(CP.getDstReg()) << " in "
2173 << TRI->getSubRegIndexName(CP.getDstIdx()) << " and "
2174 << printReg(CP.getSrcReg()) << " in "
2175 << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';
2176 else
2177 dbgs() << printReg(CP.getSrcReg(), TRI) << " in "
2178 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
2179 });
2180 }
2181
2182 ShrinkMask = LaneBitmask::getNone();
2183 ShrinkMainRange = false;
2184
2185 // Okay, attempt to join these two intervals. On failure, this returns false.
2186 // Otherwise, if one of the intervals being joined is a physreg, this method
2187 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
2188 // been modified, so we can use this information below to update aliases.
2189 if (!joinIntervals(CP)) {
2190 // Coalescing failed.
2191
2192 // Try rematerializing the definition of the source if it is cheap.
2193 bool IsDefCopy = false;
2194 if (reMaterializeDef(CP, CopyMI, IsDefCopy))
2195 return true;
2196
2197 // If we can eliminate the copy without merging the live segments, do so
2198 // now.
2199 if (!CP.isPartial() && !CP.isPhys()) {
2200 bool Changed = adjustCopiesBackFrom(CP, CopyMI);
2201 bool Shrink = false;
2202 if (!Changed)
2203 std::tie(args&: Changed, args&: Shrink) = removeCopyByCommutingDef(CP, CopyMI);
2204 if (Changed) {
2205 deleteInstr(MI: CopyMI);
2206 if (Shrink) {
2207 Register DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
2208 LiveInterval &DstLI = LIS->getInterval(Reg: DstReg);
2209 shrinkToUses(LI: &DstLI);
2210 LLVM_DEBUG(dbgs() << "\t\tshrunk: " << DstLI << '\n');
2211 }
2212 LLVM_DEBUG(dbgs() << "\tTrivial!\n");
2213 return true;
2214 }
2215 }
2216
2217 // Try and see if we can partially eliminate the copy by moving the copy to
2218 // its predecessor.
2219 if (!CP.isPartial() && !CP.isPhys())
2220 if (removePartialRedundancy(CP, CopyMI&: *CopyMI))
2221 return true;
2222
2223 // Otherwise, we are unable to join the intervals.
2224 LLVM_DEBUG(dbgs() << "\tInterference!\n");
2225 Again = true; // May be possible to coalesce later.
2226 return false;
2227 }
2228
2229 // Coalescing to a virtual register that is of a sub-register class of the
2230 // other. Make sure the resulting register is set to the right register class.
2231 if (CP.isCrossClass()) {
2232 ++numCrossRCs;
2233 MRI->setRegClass(Reg: CP.getDstReg(), RC: CP.getNewRC());
2234 }
2235
2236 // Removing sub-register copies can ease the register class constraints.
2237 // Make sure we attempt to inflate the register class of DstReg.
2238 if (!CP.isPhys() && RegClassInfo.isProperSubClass(RC: CP.getNewRC()))
2239 InflateRegs.push_back(Elt: CP.getDstReg());
2240
2241 // CopyMI has been erased by joinIntervals at this point. Remove it from
2242 // ErasedInstrs since copyCoalesceWorkList() won't add a successful join back
2243 // to the work list. This keeps ErasedInstrs from growing needlessly.
2244 if (ErasedInstrs.erase(Ptr: CopyMI))
2245 // But we may encounter the instruction again in this iteration.
2246 CurrentErasedInstrs.insert(Ptr: CopyMI);
2247
2248 // Rewrite all SrcReg operands to DstReg.
2249 // Also update DstReg operands to include DstIdx if it is set.
2250 if (CP.getDstIdx())
2251 updateRegDefsUses(SrcReg: CP.getDstReg(), DstReg: CP.getDstReg(), SubIdx: CP.getDstIdx());
2252 updateRegDefsUses(SrcReg: CP.getSrcReg(), DstReg: CP.getDstReg(), SubIdx: CP.getSrcIdx());
2253
2254 // Shrink subregister ranges if necessary.
2255 if (ShrinkMask.any()) {
2256 LiveInterval &LI = LIS->getInterval(Reg: CP.getDstReg());
2257 for (LiveInterval::SubRange &S : LI.subranges()) {
2258 if ((S.LaneMask & ShrinkMask).none())
2259 continue;
2260 LLVM_DEBUG(dbgs() << "Shrink LaneUses (Lane " << PrintLaneMask(S.LaneMask)
2261 << ")\n");
2262 LIS->shrinkToUses(SR&: S, Reg: LI.reg());
2263 ShrinkMainRange = true;
2264 }
2265 LI.removeEmptySubRanges();
2266 }
2267
2268 // CP.getSrcReg()'s live interval has been merged into CP.getDstReg's live
2269 // interval. Since CP.getSrcReg() is in ToBeUpdated set and its live interval
2270 // is not up-to-date, need to update the merged live interval here.
2271 if (ToBeUpdated.count(V: CP.getSrcReg()))
2272 ShrinkMainRange = true;
2273
2274 if (ShrinkMainRange) {
2275 LiveInterval &LI = LIS->getInterval(Reg: CP.getDstReg());
2276 shrinkToUses(LI: &LI);
2277 }
2278
2279 // SrcReg is guaranteed to be the register whose live interval that is
2280 // being merged.
2281 LIS->removeInterval(Reg: CP.getSrcReg());
2282
2283 // Update regalloc hint.
2284 TRI->updateRegAllocHint(Reg: CP.getSrcReg(), NewReg: CP.getDstReg(), MF&: *MF);
2285
2286 LLVM_DEBUG({
2287 dbgs() << "\tSuccess: " << printReg(CP.getSrcReg(), TRI, CP.getSrcIdx())
2288 << " -> " << printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
2289 dbgs() << "\tResult = ";
2290 if (CP.isPhys())
2291 dbgs() << printReg(CP.getDstReg(), TRI);
2292 else
2293 dbgs() << LIS->getInterval(CP.getDstReg());
2294 dbgs() << '\n';
2295 });
2296
2297 ++numJoins;
2298 return true;
2299}
2300
2301bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
2302 Register DstReg = CP.getDstReg();
2303 Register SrcReg = CP.getSrcReg();
2304 assert(CP.isPhys() && "Must be a physreg copy");
2305 assert(MRI->isReserved(DstReg) && "Not a reserved register");
2306 LiveInterval &RHS = LIS->getInterval(Reg: SrcReg);
2307 LLVM_DEBUG(dbgs() << "\t\tRHS = " << RHS << '\n');
2308
2309 assert(RHS.containsOneValue() && "Invalid join with reserved register");
2310
2311 // Optimization for reserved registers like ESP. We can only merge with a
2312 // reserved physreg if RHS has a single value that is a copy of DstReg.
2313 // The live range of the reserved register will look like a set of dead defs
2314 // - we don't properly track the live range of reserved registers.
2315
2316 // Deny any overlapping intervals. This depends on all the reserved
2317 // register live ranges to look like dead defs.
2318 if (!MRI->isConstantPhysReg(PhysReg: DstReg)) {
2319 for (MCRegUnit Unit : TRI->regunits(Reg: DstReg)) {
2320 // Abort if not all the regunits are reserved.
2321 for (MCRegUnitRootIterator RI(Unit, TRI); RI.isValid(); ++RI) {
2322 if (!MRI->isReserved(PhysReg: *RI))
2323 return false;
2324 }
2325 if (RHS.overlaps(other: LIS->getRegUnit(Unit))) {
2326 LLVM_DEBUG(dbgs() << "\t\tInterference: " << printRegUnit(Unit, TRI)
2327 << '\n');
2328 return false;
2329 }
2330 }
2331
2332 // We must also check for overlaps with regmask clobbers.
2333 BitVector RegMaskUsable;
2334 if (LIS->checkRegMaskInterference(LI: RHS, UsableRegs&: RegMaskUsable) &&
2335 !RegMaskUsable.test(Idx: DstReg.id())) {
2336 LLVM_DEBUG(dbgs() << "\t\tRegMask interference\n");
2337 return false;
2338 }
2339 }
2340
2341 // Skip any value computations, we are not adding new values to the
2342 // reserved register. Also skip merging the live ranges, the reserved
2343 // register live range doesn't need to be accurate as long as all the
2344 // defs are there.
2345
2346 // Delete the identity copy.
2347 MachineInstr *CopyMI;
2348 if (CP.isFlipped()) {
2349 // Physreg is copied into vreg
2350 // %y = COPY %physreg_x
2351 // ... //< no other def of %physreg_x here
2352 // use %y
2353 // =>
2354 // ...
2355 // use %physreg_x
2356 CopyMI = MRI->getVRegDef(Reg: SrcReg);
2357 deleteInstr(MI: CopyMI);
2358 } else {
2359 // VReg is copied into physreg:
2360 // %y = def
2361 // ... //< no other def or use of %physreg_x here
2362 // %physreg_x = COPY %y
2363 // =>
2364 // %physreg_x = def
2365 // ...
2366 if (!MRI->hasOneNonDBGUse(RegNo: SrcReg)) {
2367 LLVM_DEBUG(dbgs() << "\t\tMultiple vreg uses!\n");
2368 return false;
2369 }
2370
2371 if (!LIS->intervalIsInOneMBB(LI: RHS)) {
2372 LLVM_DEBUG(dbgs() << "\t\tComplex control flow!\n");
2373 return false;
2374 }
2375
2376 MachineInstr &DestMI = *MRI->getVRegDef(Reg: SrcReg);
2377 CopyMI = &*MRI->use_instr_nodbg_begin(RegNo: SrcReg);
2378 SlotIndex CopyRegIdx = LIS->getInstructionIndex(Instr: *CopyMI).getRegSlot();
2379 SlotIndex DestRegIdx = LIS->getInstructionIndex(Instr: DestMI).getRegSlot();
2380
2381 if (!MRI->isConstantPhysReg(PhysReg: DstReg)) {
2382 // We checked above that there are no interfering defs of the physical
2383 // register. However, for this case, where we intend to move up the def of
2384 // the physical register, we also need to check for interfering uses.
2385 SlotIndexes *Indexes = LIS->getSlotIndexes();
2386 for (SlotIndex SI = Indexes->getNextNonNullIndex(Index: DestRegIdx);
2387 SI != CopyRegIdx; SI = Indexes->getNextNonNullIndex(Index: SI)) {
2388 MachineInstr *MI = LIS->getInstructionFromIndex(index: SI);
2389 if (MI->readsRegister(Reg: DstReg, TRI)) {
2390 LLVM_DEBUG(dbgs() << "\t\tInterference (read): " << *MI);
2391 return false;
2392 }
2393 }
2394 }
2395
2396 // We're going to remove the copy which defines a physical reserved
2397 // register, so remove its valno, etc.
2398 LLVM_DEBUG(dbgs() << "\t\tRemoving phys reg def of "
2399 << printReg(DstReg, TRI) << " at " << CopyRegIdx << "\n");
2400
2401 LIS->removePhysRegDefAt(Reg: DstReg.asMCReg(), Pos: CopyRegIdx);
2402 deleteInstr(MI: CopyMI);
2403
2404 // Create a new dead def at the new def location.
2405 for (MCRegUnit Unit : TRI->regunits(Reg: DstReg)) {
2406 LiveRange &LR = LIS->getRegUnit(Unit);
2407 LR.createDeadDef(Def: DestRegIdx, VNIAlloc&: LIS->getVNInfoAllocator());
2408 }
2409 }
2410
2411 // We don't track kills for reserved registers.
2412 MRI->clearKillFlags(Reg: CP.getSrcReg());
2413
2414 return true;
2415}
2416
2417//===----------------------------------------------------------------------===//
2418// Interference checking and interval joining
2419//===----------------------------------------------------------------------===//
2420//
2421// In the easiest case, the two live ranges being joined are disjoint, and
2422// there is no interference to consider. It is quite common, though, to have
2423// overlapping live ranges, and we need to check if the interference can be
2424// resolved.
2425//
2426// The live range of a single SSA value forms a sub-tree of the dominator tree.
2427// This means that two SSA values overlap if and only if the def of one value
2428// is contained in the live range of the other value. As a special case, the
2429// overlapping values can be defined at the same index.
2430//
2431// The interference from an overlapping def can be resolved in these cases:
2432//
2433// 1. Coalescable copies. The value is defined by a copy that would become an
2434// identity copy after joining SrcReg and DstReg. The copy instruction will
2435// be removed, and the value will be merged with the source value.
2436//
2437// There can be several copies back and forth, causing many values to be
2438// merged into one. We compute a list of ultimate values in the joined live
2439// range as well as a mappings from the old value numbers.
2440//
2441// 2. IMPLICIT_DEF. This instruction is only inserted to ensure all PHI
2442// predecessors have a live out value. It doesn't cause real interference,
2443// and can be merged into the value it overlaps. Like a coalescable copy, it
2444// can be erased after joining.
2445//
2446// 3. Copy of external value. The overlapping def may be a copy of a value that
2447// is already in the other register. This is like a coalescable copy, but
2448// the live range of the source register must be trimmed after erasing the
2449// copy instruction:
2450//
2451// %src = COPY %ext
2452// %dst = COPY %ext <-- Remove this COPY, trim the live range of %ext.
2453//
2454// 4. Clobbering undefined lanes. Vector registers are sometimes built by
2455// defining one lane at a time:
2456//
2457// %dst:ssub0<def,read-undef> = FOO
2458// %src = BAR
2459// %dst:ssub1 = COPY %src
2460//
2461// The live range of %src overlaps the %dst value defined by FOO, but
2462// merging %src into %dst:ssub1 is only going to clobber the ssub1 lane
2463// which was undef anyway.
2464//
2465// The value mapping is more complicated in this case. The final live range
2466// will have different value numbers for both FOO and BAR, but there is no
2467// simple mapping from old to new values. It may even be necessary to add
2468// new PHI values.
2469//
2470// 5. Clobbering dead lanes. A def may clobber a lane of a vector register that
2471// is live, but never read. This can happen because we don't compute
2472// individual live ranges per lane.
2473//
2474// %dst = FOO
2475// %src = BAR
2476// %dst:ssub1 = COPY %src
2477//
2478// This kind of interference is only resolved locally. If the clobbered
2479// lane value escapes the block, the join is aborted.
2480
2481namespace {
2482
2483/// Track information about values in a single virtual register about to be
2484/// joined. Objects of this class are always created in pairs - one for each
2485/// side of the CoalescerPair (or one for each lane of a side of the coalescer
2486/// pair)
2487class JoinVals {
2488 /// Live range we work on.
2489 LiveRange &LR;
2490
2491 /// (Main) register we work on.
2492 const Register Reg;
2493
2494 /// Reg (and therefore the values in this liverange) will end up as
2495 /// subregister SubIdx in the coalesced register. Either CP.DstIdx or
2496 /// CP.SrcIdx.
2497 const unsigned SubIdx;
2498
2499 /// The LaneMask that this liverange will occupy the coalesced register. May
2500 /// be smaller than the lanemask produced by SubIdx when merging subranges.
2501 const LaneBitmask LaneMask;
2502
2503 /// This is true when joining sub register ranges, false when joining main
2504 /// ranges.
2505 const bool SubRangeJoin;
2506
2507 /// Whether the current LiveInterval tracks subregister liveness.
2508 const bool TrackSubRegLiveness;
2509
2510 /// Values that will be present in the final live range.
2511 SmallVectorImpl<VNInfo *> &NewVNInfo;
2512
2513 const CoalescerPair &CP;
2514 LiveIntervals *LIS;
2515 SlotIndexes *Indexes;
2516 const TargetRegisterInfo *TRI;
2517
2518 /// Value number assignments. Maps value numbers in LI to entries in
2519 /// NewVNInfo. This is suitable for passing to LiveInterval::join().
2520 SmallVector<int, 8> Assignments;
2521
2522public:
2523 /// Conflict resolution for overlapping values.
2524 enum ConflictResolution {
2525 /// No overlap, simply keep this value.
2526 CR_Keep,
2527
2528 /// Merge this value into OtherVNI and erase the defining instruction.
2529 /// Used for IMPLICIT_DEF, coalescable copies, and copies from external
2530 /// values.
2531 CR_Erase,
2532
2533 /// Merge this value into OtherVNI but keep the defining instruction.
2534 /// This is for the special case where OtherVNI is defined by the same
2535 /// instruction.
2536 CR_Merge,
2537
2538 /// Keep this value, and have it replace OtherVNI where possible. This
2539 /// complicates value mapping since OtherVNI maps to two different values
2540 /// before and after this def.
2541 /// Used when clobbering undefined or dead lanes.
2542 CR_Replace,
2543
2544 /// Unresolved conflict. Visit later when all values have been mapped.
2545 CR_Unresolved,
2546
2547 /// Unresolvable conflict. Abort the join.
2548 CR_Impossible
2549 };
2550
2551private:
2552 /// Per-value info for LI. The lane bit masks are all relative to the final
2553 /// joined register, so they can be compared directly between SrcReg and
2554 /// DstReg.
2555 struct Val {
2556 ConflictResolution Resolution = CR_Keep;
2557
2558 /// Lanes written by this def, 0 for unanalyzed values.
2559 LaneBitmask WriteLanes;
2560
2561 /// Lanes with defined values in this register. Other lanes are undef and
2562 /// safe to clobber.
2563 LaneBitmask ValidLanes;
2564
2565 /// Value in LI being redefined by this def.
2566 VNInfo *RedefVNI = nullptr;
2567
2568 /// Value in the other live range that overlaps this def, if any.
2569 VNInfo *OtherVNI = nullptr;
2570
2571 /// Is this value an IMPLICIT_DEF that can be erased?
2572 ///
2573 /// IMPLICIT_DEF values should only exist at the end of a basic block that
2574 /// is a predecessor to a phi-value. These IMPLICIT_DEF instructions can be
2575 /// safely erased if they are overlapping a live value in the other live
2576 /// interval.
2577 ///
2578 /// Weird control flow graphs and incomplete PHI handling in
2579 /// ProcessImplicitDefs can very rarely create IMPLICIT_DEF values with
2580 /// longer live ranges. Such IMPLICIT_DEF values should be treated like
2581 /// normal values.
2582 bool ErasableImplicitDef = false;
2583
2584 /// True when the live range of this value will be pruned because of an
2585 /// overlapping CR_Replace value in the other live range.
2586 bool Pruned = false;
2587
2588 /// True once Pruned above has been computed.
2589 bool PrunedComputed = false;
2590
2591 /// True if this value is determined to be identical to OtherVNI
2592 /// (in valuesIdentical). This is used with CR_Erase where the erased
2593 /// copy is redundant, i.e. the source value is already the same as
2594 /// the destination. In such cases the subranges need to be updated
2595 /// properly. See comment at pruneSubRegValues for more info.
2596 bool Identical = false;
2597
2598 Val() = default;
2599
2600 bool isAnalyzed() const { return WriteLanes.any(); }
2601
2602 /// Mark this value as an IMPLICIT_DEF which must be kept as if it were an
2603 /// ordinary value.
2604 void mustKeepImplicitDef(const TargetRegisterInfo &TRI,
2605 const MachineInstr &ImpDef) {
2606 assert(ImpDef.isImplicitDef());
2607 ErasableImplicitDef = false;
2608 ValidLanes = TRI.getSubRegIndexLaneMask(SubIdx: ImpDef.getOperand(i: 0).getSubReg());
2609 }
2610 };
2611
2612 /// One entry per value number in LI.
2613 SmallVector<Val, 8> Vals;
2614
2615 /// Compute the bitmask of lanes actually written by DefMI.
2616 /// Set Redef if there are any partial register definitions that depend on the
2617 /// previous value of the register.
2618 LaneBitmask computeWriteLanes(const MachineInstr *DefMI, bool &Redef) const;
2619
2620 /// Find the ultimate value that VNI was copied from.
2621 std::pair<const VNInfo *, Register> followCopyChain(const VNInfo *VNI) const;
2622
2623 bool valuesIdentical(VNInfo *Value0, VNInfo *Value1,
2624 const JoinVals &Other) const;
2625
2626 /// Analyze ValNo in this live range, and set all fields of Vals[ValNo].
2627 /// Return a conflict resolution when possible, but leave the hard cases as
2628 /// CR_Unresolved.
2629 /// Recursively calls computeAssignment() on this and Other, guaranteeing that
2630 /// both OtherVNI and RedefVNI have been analyzed and mapped before returning.
2631 /// The recursion always goes upwards in the dominator tree, making loops
2632 /// impossible.
2633 ConflictResolution analyzeValue(unsigned ValNo, JoinVals &Other);
2634
2635 /// Compute the value assignment for ValNo in RI.
2636 /// This may be called recursively by analyzeValue(), but never for a ValNo on
2637 /// the stack.
2638 void computeAssignment(unsigned ValNo, JoinVals &Other);
2639
2640 /// Assuming ValNo is going to clobber some valid lanes in Other.LR, compute
2641 /// the extent of the tainted lanes in the block.
2642 ///
2643 /// Multiple values in Other.LR can be affected since partial redefinitions
2644 /// can preserve previously tainted lanes.
2645 ///
2646 /// 1 %dst = VLOAD <-- Define all lanes in %dst
2647 /// 2 %src = FOO <-- ValNo to be joined with %dst:ssub0
2648 /// 3 %dst:ssub1 = BAR <-- Partial redef doesn't clear taint in ssub0
2649 /// 4 %dst:ssub0 = COPY %src <-- Conflict resolved, ssub0 wasn't read
2650 ///
2651 /// For each ValNo in Other that is affected, add an (EndIndex, TaintedLanes)
2652 /// entry to TaintedVals.
2653 ///
2654 /// Returns false if the tainted lanes extend beyond the basic block.
2655 bool
2656 taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other,
2657 SmallVectorImpl<std::pair<SlotIndex, LaneBitmask>> &TaintExtent);
2658
2659 /// Return true if MI uses any of the given Lanes from Reg.
2660 /// This does not include partial redefinitions of Reg.
2661 bool usesLanes(const MachineInstr &MI, Register, unsigned, LaneBitmask) const;
2662
2663 /// Determine if ValNo is a copy of a value number in LR or Other.LR that will
2664 /// be pruned:
2665 ///
2666 /// %dst = COPY %src
2667 /// %src = COPY %dst <-- This value to be pruned.
2668 /// %dst = COPY %src <-- This value is a copy of a pruned value.
2669 bool isPrunedValue(unsigned ValNo, JoinVals &Other);
2670
2671public:
2672 JoinVals(LiveRange &LR, Register Reg, unsigned SubIdx, LaneBitmask LaneMask,
2673 SmallVectorImpl<VNInfo *> &newVNInfo, const CoalescerPair &cp,
2674 LiveIntervals *lis, const TargetRegisterInfo *TRI, bool SubRangeJoin,
2675 bool TrackSubRegLiveness)
2676 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask),
2677 SubRangeJoin(SubRangeJoin), TrackSubRegLiveness(TrackSubRegLiveness),
2678 NewVNInfo(newVNInfo), CP(cp), LIS(lis), Indexes(LIS->getSlotIndexes()),
2679 TRI(TRI), Assignments(LR.getNumValNums(), -1),
2680 Vals(LR.getNumValNums()) {}
2681
2682 /// Analyze defs in LR and compute a value mapping in NewVNInfo.
2683 /// Returns false if any conflicts were impossible to resolve.
2684 bool mapValues(JoinVals &Other);
2685
2686 /// Try to resolve conflicts that require all values to be mapped.
2687 /// Returns false if any conflicts were impossible to resolve.
2688 bool resolveConflicts(JoinVals &Other);
2689
2690 /// Prune the live range of values in Other.LR where they would conflict with
2691 /// CR_Replace values in LR. Collect end points for restoring the live range
2692 /// after joining.
2693 void pruneValues(JoinVals &Other, SmallVectorImpl<SlotIndex> &EndPoints,
2694 bool changeInstrs);
2695
2696 /// Removes subranges starting at copies that get removed. This sometimes
2697 /// happens when undefined subranges are copied around. These ranges contain
2698 /// no useful information and can be removed.
2699 void pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask);
2700
2701 /// Pruning values in subranges can lead to removing segments in these
2702 /// subranges started by IMPLICIT_DEFs. The corresponding segments in
2703 /// the main range also need to be removed. This function will mark
2704 /// the corresponding values in the main range as pruned, so that
2705 /// eraseInstrs can do the final cleanup.
2706 /// The parameter @p LI must be the interval whose main range is the
2707 /// live range LR.
2708 void pruneMainSegments(LiveInterval &LI, bool &ShrinkMainRange);
2709
2710 /// Erase any machine instructions that have been coalesced away.
2711 /// Add erased instructions to ErasedInstrs.
2712 /// Add foreign virtual registers to ShrinkRegs if their live range ended at
2713 /// the erased instrs.
2714 void eraseInstrs(SmallPtrSetImpl<MachineInstr *> &ErasedInstrs,
2715 SmallVectorImpl<Register> &ShrinkRegs,
2716 LiveInterval *LI = nullptr);
2717
2718 /// Remove liverange defs at places where implicit defs will be removed.
2719 void removeImplicitDefs();
2720
2721 /// Get the value assignments suitable for passing to LiveInterval::join.
2722 const int *getAssignments() const { return Assignments.data(); }
2723
2724 /// Get the conflict resolution for a value number.
2725 ConflictResolution getResolution(unsigned Num) const {
2726 return Vals[Num].Resolution;
2727 }
2728};
2729
2730} // end anonymous namespace
2731
2732LaneBitmask JoinVals::computeWriteLanes(const MachineInstr *DefMI,
2733 bool &Redef) const {
2734 LaneBitmask L;
2735 for (const MachineOperand &MO : DefMI->all_defs()) {
2736 if (MO.getReg() != Reg)
2737 continue;
2738 L |= TRI->getSubRegIndexLaneMask(
2739 SubIdx: TRI->composeSubRegIndices(a: SubIdx, b: MO.getSubReg()));
2740 if (MO.readsReg())
2741 Redef = true;
2742 }
2743 return L;
2744}
2745
2746std::pair<const VNInfo *, Register>
2747JoinVals::followCopyChain(const VNInfo *VNI) const {
2748 Register TrackReg = Reg;
2749
2750 while (!VNI->isPHIDef()) {
2751 SlotIndex Def = VNI->def;
2752 MachineInstr *MI = Indexes->getInstructionFromIndex(index: Def);
2753 assert(MI && "No defining instruction");
2754 if (!MI->isFullCopy())
2755 return std::make_pair(x&: VNI, y&: TrackReg);
2756 Register SrcReg = MI->getOperand(i: 1).getReg();
2757 if (!SrcReg.isVirtual())
2758 return std::make_pair(x&: VNI, y&: TrackReg);
2759
2760 const LiveInterval &LI = LIS->getInterval(Reg: SrcReg);
2761 const VNInfo *ValueIn;
2762 // No subrange involved.
2763 if (!SubRangeJoin || !LI.hasSubRanges()) {
2764 LiveQueryResult LRQ = LI.Query(Idx: Def);
2765 ValueIn = LRQ.valueIn();
2766 } else {
2767 // Query subranges. Ensure that all matching ones take us to the same def
2768 // (allowing some of them to be undef).
2769 ValueIn = nullptr;
2770 for (const LiveInterval::SubRange &S : LI.subranges()) {
2771 // Transform lanemask to a mask in the joined live interval.
2772 LaneBitmask SMask = TRI->composeSubRegIndexLaneMask(IdxA: SubIdx, Mask: S.LaneMask);
2773 if ((SMask & LaneMask).none())
2774 continue;
2775 LiveQueryResult LRQ = S.Query(Idx: Def);
2776 if (!ValueIn) {
2777 ValueIn = LRQ.valueIn();
2778 continue;
2779 }
2780 if (LRQ.valueIn() && ValueIn != LRQ.valueIn())
2781 return std::make_pair(x&: VNI, y&: TrackReg);
2782 }
2783 }
2784 if (ValueIn == nullptr) {
2785 // Reaching an undefined value is legitimate, for example:
2786 //
2787 // 1 undef %0.sub1 = ... ;; %0.sub0 == undef
2788 // 2 %1 = COPY %0 ;; %1 is defined here.
2789 // 3 %0 = COPY %1 ;; Now %0.sub0 has a definition,
2790 // ;; but it's equivalent to "undef".
2791 return std::make_pair(x: nullptr, y&: SrcReg);
2792 }
2793 VNI = ValueIn;
2794 TrackReg = SrcReg;
2795 }
2796 return std::make_pair(x&: VNI, y&: TrackReg);
2797}
2798
2799bool JoinVals::valuesIdentical(VNInfo *Value0, VNInfo *Value1,
2800 const JoinVals &Other) const {
2801 const VNInfo *Orig0;
2802 Register Reg0;
2803 std::tie(args&: Orig0, args&: Reg0) = followCopyChain(VNI: Value0);
2804 if (Orig0 == Value1 && Reg0 == Other.Reg)
2805 return true;
2806
2807 const VNInfo *Orig1;
2808 Register Reg1;
2809 std::tie(args&: Orig1, args&: Reg1) = Other.followCopyChain(VNI: Value1);
2810 // If both values are undefined, and the source registers are the same
2811 // register, the values are identical. Filter out cases where only one
2812 // value is defined.
2813 if (Orig0 == nullptr || Orig1 == nullptr)
2814 return Orig0 == Orig1 && Reg0 == Reg1;
2815
2816 // The values are equal if they are defined at the same place and use the
2817 // same register. Note that we cannot compare VNInfos directly as some of
2818 // them might be from a copy created in mergeSubRangeInto() while the other
2819 // is from the original LiveInterval.
2820 return Orig0->def == Orig1->def && Reg0 == Reg1;
2821}
2822
2823JoinVals::ConflictResolution JoinVals::analyzeValue(unsigned ValNo,
2824 JoinVals &Other) {
2825 Val &V = Vals[ValNo];
2826 assert(!V.isAnalyzed() && "Value has already been analyzed!");
2827 VNInfo *VNI = LR.getValNumInfo(ValNo);
2828 if (VNI->isUnused()) {
2829 V.WriteLanes = LaneBitmask::getAll();
2830 return CR_Keep;
2831 }
2832
2833 // Get the instruction defining this value, compute the lanes written.
2834 const MachineInstr *DefMI = nullptr;
2835 if (VNI->isPHIDef()) {
2836 // Conservatively assume that all lanes in a PHI are valid.
2837 LaneBitmask Lanes = SubRangeJoin ? LaneBitmask::getLane(Lane: 0)
2838 : TRI->getSubRegIndexLaneMask(SubIdx);
2839 V.ValidLanes = V.WriteLanes = Lanes;
2840 } else {
2841 DefMI = Indexes->getInstructionFromIndex(index: VNI->def);
2842 assert(DefMI != nullptr);
2843 if (SubRangeJoin) {
2844 // We don't care about the lanes when joining subregister ranges.
2845 V.WriteLanes = V.ValidLanes = LaneBitmask::getLane(Lane: 0);
2846 if (DefMI->isImplicitDef()) {
2847 V.ValidLanes = LaneBitmask::getNone();
2848 V.ErasableImplicitDef = true;
2849 }
2850 } else {
2851 bool Redef = false;
2852 V.ValidLanes = V.WriteLanes = computeWriteLanes(DefMI, Redef);
2853
2854 // If this is a read-modify-write instruction, there may be more valid
2855 // lanes than the ones written by this instruction.
2856 // This only covers partial redef operands. DefMI may have normal use
2857 // operands reading the register. They don't contribute valid lanes.
2858 //
2859 // This adds ssub1 to the set of valid lanes in %src:
2860 //
2861 // %src:ssub1 = FOO
2862 //
2863 // This leaves only ssub1 valid, making any other lanes undef:
2864 //
2865 // %src:ssub1<def,read-undef> = FOO %src:ssub2
2866 //
2867 // The <read-undef> flag on the def operand means that old lane values are
2868 // not important.
2869 if (Redef) {
2870 V.RedefVNI = LR.Query(Idx: VNI->def).valueIn();
2871 assert((TrackSubRegLiveness || V.RedefVNI) &&
2872 "Instruction is reading nonexistent value");
2873 if (V.RedefVNI != nullptr) {
2874 computeAssignment(ValNo: V.RedefVNI->id, Other);
2875 V.ValidLanes |= Vals[V.RedefVNI->id].ValidLanes;
2876 }
2877 }
2878
2879 // An IMPLICIT_DEF writes undef values.
2880 if (DefMI->isImplicitDef()) {
2881 // We normally expect IMPLICIT_DEF values to be live only until the end
2882 // of their block. If the value is really live longer and gets pruned in
2883 // another block, this flag is cleared again.
2884 //
2885 // Clearing the valid lanes is deferred until it is sure this can be
2886 // erased.
2887 V.ErasableImplicitDef = true;
2888 }
2889 }
2890 }
2891
2892 // Find the value in Other that overlaps VNI->def, if any.
2893 LiveQueryResult OtherLRQ = Other.LR.Query(Idx: VNI->def);
2894
2895 // It is possible that both values are defined by the same instruction, or
2896 // the values are PHIs defined in the same block. When that happens, the two
2897 // values should be merged into one, but not into any preceding value.
2898 // The first value defined or visited gets CR_Keep, the other gets CR_Merge.
2899 if (VNInfo *OtherVNI = OtherLRQ.valueDefined()) {
2900 assert(SlotIndex::isSameInstr(VNI->def, OtherVNI->def) && "Broken LRQ");
2901
2902 // One value stays, the other is merged. Keep the earlier one, or the first
2903 // one we see.
2904 if (OtherVNI->def < VNI->def)
2905 Other.computeAssignment(ValNo: OtherVNI->id, Other&: *this);
2906 else if (VNI->def < OtherVNI->def && OtherLRQ.valueIn()) {
2907 // This is an early-clobber def overlapping a live-in value in the other
2908 // register. Not mergeable.
2909 V.OtherVNI = OtherLRQ.valueIn();
2910 return CR_Impossible;
2911 }
2912 V.OtherVNI = OtherVNI;
2913 Val &OtherV = Other.Vals[OtherVNI->id];
2914 // Keep this value, check for conflicts when analyzing OtherVNI. Avoid
2915 // revisiting OtherVNI->id in JoinVals::computeAssignment() below before it
2916 // is assigned.
2917 if (!OtherV.isAnalyzed() || Other.Assignments[OtherVNI->id] == -1)
2918 return CR_Keep;
2919 // Both sides have been analyzed now.
2920 // Allow overlapping PHI values. Any real interference would show up in a
2921 // predecessor, the PHI itself can't introduce any conflicts.
2922 if (VNI->isPHIDef())
2923 return CR_Merge;
2924 if ((V.ValidLanes & OtherV.ValidLanes).any())
2925 // Overlapping lanes can't be resolved.
2926 return CR_Impossible;
2927 return CR_Merge;
2928 }
2929
2930 // No simultaneous def. Is Other live at the def?
2931 V.OtherVNI = OtherLRQ.valueIn();
2932 if (!V.OtherVNI)
2933 // No overlap, no conflict.
2934 return CR_Keep;
2935
2936 assert(!SlotIndex::isSameInstr(VNI->def, V.OtherVNI->def) && "Broken LRQ");
2937
2938 // We have overlapping values, or possibly a kill of Other.
2939 // Recursively compute assignments up the dominator tree.
2940 Other.computeAssignment(ValNo: V.OtherVNI->id, Other&: *this);
2941 Val &OtherV = Other.Vals[V.OtherVNI->id];
2942
2943 if (OtherV.ErasableImplicitDef) {
2944 // Check if OtherV is an IMPLICIT_DEF that extends beyond its basic block.
2945 // This shouldn't normally happen, but ProcessImplicitDefs can leave such
2946 // IMPLICIT_DEF instructions behind, and there is nothing wrong with it
2947 // technically.
2948 //
2949 // When it happens, treat that IMPLICIT_DEF as a normal value, and don't try
2950 // to erase the IMPLICIT_DEF instruction.
2951 //
2952 // Additionally we must keep an IMPLICIT_DEF if we're redefining an incoming
2953 // value.
2954
2955 MachineInstr *OtherImpDef =
2956 Indexes->getInstructionFromIndex(index: V.OtherVNI->def);
2957 MachineBasicBlock *OtherMBB = OtherImpDef->getParent();
2958 if (DefMI &&
2959 (DefMI->getParent() != OtherMBB || LIS->isLiveInToMBB(LR, mbb: OtherMBB))) {
2960 LLVM_DEBUG(dbgs() << "IMPLICIT_DEF defined at " << V.OtherVNI->def
2961 << " extends into "
2962 << printMBBReference(*DefMI->getParent())
2963 << ", keeping it.\n");
2964 OtherV.mustKeepImplicitDef(TRI: *TRI, ImpDef: *OtherImpDef);
2965 } else if (OtherMBB->hasEHPadSuccessor()) {
2966 // If OtherV is defined in a basic block that has EH pad successors then
2967 // we get the same problem not just if OtherV is live beyond its basic
2968 // block, but beyond the last call instruction in its basic block. Handle
2969 // this case conservatively.
2970 LLVM_DEBUG(
2971 dbgs() << "IMPLICIT_DEF defined at " << V.OtherVNI->def
2972 << " may be live into EH pad successors, keeping it.\n");
2973 OtherV.mustKeepImplicitDef(TRI: *TRI, ImpDef: *OtherImpDef);
2974 } else {
2975 // We deferred clearing these lanes in case we needed to save them
2976 OtherV.ValidLanes &= ~OtherV.WriteLanes;
2977 }
2978 }
2979
2980 // Allow overlapping PHI values. Any real interference would show up in a
2981 // predecessor, the PHI itself can't introduce any conflicts.
2982 if (VNI->isPHIDef())
2983 return CR_Replace;
2984
2985 // Check for simple erasable conflicts.
2986 if (DefMI->isImplicitDef())
2987 return CR_Erase;
2988
2989 // Include the non-conflict where DefMI is a coalescable copy that kills
2990 // OtherVNI. We still want the copy erased and value numbers merged.
2991 if (CP.isCoalescable(MI: DefMI)) {
2992 // Some of the lanes copied from OtherVNI may be undef, making them undef
2993 // here too.
2994 V.ValidLanes &= ~V.WriteLanes | OtherV.ValidLanes;
2995 return CR_Erase;
2996 }
2997
2998 // This may not be a real conflict if DefMI simply kills Other and defines
2999 // VNI.
3000 if (OtherLRQ.isKill() && OtherLRQ.endPoint() <= VNI->def)
3001 return CR_Keep;
3002
3003 // Handle the case where VNI and OtherVNI can be proven to be identical:
3004 //
3005 // %other = COPY %ext
3006 // %this = COPY %ext <-- Erase this copy
3007 //
3008 if (DefMI->isFullCopy() && !CP.isPartial() &&
3009 valuesIdentical(Value0: VNI, Value1: V.OtherVNI, Other)) {
3010 V.Identical = true;
3011 return CR_Erase;
3012 }
3013
3014 // The remaining checks apply to the lanes, which aren't tracked here. This
3015 // was already decided to be OK via the following CR_Replace condition.
3016 // CR_Replace.
3017 if (SubRangeJoin)
3018 return CR_Replace;
3019
3020 // If the lanes written by this instruction were all undef in OtherVNI, it is
3021 // still safe to join the live ranges. This can't be done with a simple value
3022 // mapping, though - OtherVNI will map to multiple values:
3023 //
3024 // 1 %dst:ssub0 = FOO <-- OtherVNI
3025 // 2 %src = BAR <-- VNI
3026 // 3 %dst:ssub1 = COPY killed %src <-- Eliminate this copy.
3027 // 4 BAZ killed %dst
3028 // 5 QUUX killed %src
3029 //
3030 // Here OtherVNI will map to itself in [1;2), but to VNI in [2;5). CR_Replace
3031 // handles this complex value mapping.
3032 if ((V.WriteLanes & OtherV.ValidLanes).none())
3033 return CR_Replace;
3034
3035 // If the other live range is killed by DefMI and the live ranges are still
3036 // overlapping, it must be because we're looking at an early clobber def:
3037 //
3038 // %dst<def,early-clobber> = ASM killed %src
3039 //
3040 // In this case, it is illegal to merge the two live ranges since the early
3041 // clobber def would clobber %src before it was read.
3042 if (OtherLRQ.isKill()) {
3043 // This case where the def doesn't overlap the kill is handled above.
3044 assert(VNI->def.isEarlyClobber() &&
3045 "Only early clobber defs can overlap a kill");
3046 return CR_Impossible;
3047 }
3048
3049 // VNI is clobbering live lanes in OtherVNI, but there is still the
3050 // possibility that no instructions actually read the clobbered lanes.
3051 // If we're clobbering all the lanes in OtherVNI, at least one must be read.
3052 // Otherwise Other.RI wouldn't be live here.
3053 if ((TRI->getSubRegIndexLaneMask(SubIdx: Other.SubIdx) & ~V.WriteLanes).none())
3054 return CR_Impossible;
3055
3056 if (TrackSubRegLiveness) {
3057 auto &OtherLI = LIS->getInterval(Reg: Other.Reg);
3058 // If OtherVNI does not have subranges, it means all the lanes of OtherVNI
3059 // share the same live range, so we just need to check whether they have
3060 // any conflict bit in their LaneMask.
3061 if (!OtherLI.hasSubRanges()) {
3062 LaneBitmask OtherMask = TRI->getSubRegIndexLaneMask(SubIdx: Other.SubIdx);
3063 return (OtherMask & V.WriteLanes).none() ? CR_Replace : CR_Impossible;
3064 }
3065
3066 // If we are clobbering some active lanes of OtherVNI at VNI->def, it is
3067 // impossible to resolve the conflict. Otherwise, we can just replace
3068 // OtherVNI because of no real conflict.
3069 for (LiveInterval::SubRange &OtherSR : OtherLI.subranges()) {
3070 LaneBitmask OtherMask =
3071 TRI->composeSubRegIndexLaneMask(IdxA: Other.SubIdx, Mask: OtherSR.LaneMask);
3072 if ((OtherMask & V.WriteLanes).none())
3073 continue;
3074
3075 auto OtherSRQ = OtherSR.Query(Idx: VNI->def);
3076 if (OtherSRQ.valueIn() && OtherSRQ.endPoint() > VNI->def) {
3077 // VNI is clobbering some lanes of OtherVNI, they have real conflict.
3078 return CR_Impossible;
3079 }
3080 }
3081
3082 // VNI is NOT clobbering any lane of OtherVNI, just replace OtherVNI.
3083 return CR_Replace;
3084 }
3085
3086 // We need to verify that no instructions are reading the clobbered lanes.
3087 // To save compile time, we'll only check that locally. Don't allow the
3088 // tainted value to escape the basic block.
3089 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(index: VNI->def);
3090 if (OtherLRQ.endPoint() >= Indexes->getMBBEndIdx(mbb: MBB))
3091 return CR_Impossible;
3092
3093 // There are still some things that could go wrong besides clobbered lanes
3094 // being read, for example OtherVNI may be only partially redefined in MBB,
3095 // and some clobbered lanes could escape the block. Save this analysis for
3096 // resolveConflicts() when all values have been mapped. We need to know
3097 // RedefVNI and WriteLanes for any later defs in MBB, and we can't compute
3098 // that now - the recursive analyzeValue() calls must go upwards in the
3099 // dominator tree.
3100 return CR_Unresolved;
3101}
3102
3103void JoinVals::computeAssignment(unsigned ValNo, JoinVals &Other) {
3104 Val &V = Vals[ValNo];
3105 if (V.isAnalyzed()) {
3106 // Recursion should always move up the dominator tree, so ValNo is not
3107 // supposed to reappear before it has been assigned.
3108 assert(Assignments[ValNo] != -1 && "Bad recursion?");
3109 return;
3110 }
3111 switch ((V.Resolution = analyzeValue(ValNo, Other))) {
3112 case CR_Erase:
3113 case CR_Merge:
3114 // Merge this ValNo into OtherVNI.
3115 assert(V.OtherVNI && "OtherVNI not assigned, can't merge.");
3116 assert(Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion");
3117 Assignments[ValNo] = Other.Assignments[V.OtherVNI->id];
3118 LLVM_DEBUG(dbgs() << "\t\tmerge " << printReg(Reg) << ':' << ValNo << '@'
3119 << LR.getValNumInfo(ValNo)->def << " into "
3120 << printReg(Other.Reg) << ':' << V.OtherVNI->id << '@'
3121 << V.OtherVNI->def << " --> @"
3122 << NewVNInfo[Assignments[ValNo]]->def << '\n');
3123 break;
3124 case CR_Replace:
3125 case CR_Unresolved: {
3126 // The other value is going to be pruned if this join is successful.
3127 assert(V.OtherVNI && "OtherVNI not assigned, can't prune");
3128 Val &OtherV = Other.Vals[V.OtherVNI->id];
3129 OtherV.Pruned = true;
3130 [[fallthrough]];
3131 }
3132 default:
3133 // This value number needs to go in the final joined live range.
3134 Assignments[ValNo] = NewVNInfo.size();
3135 NewVNInfo.push_back(Elt: LR.getValNumInfo(ValNo));
3136 break;
3137 }
3138}
3139
3140bool JoinVals::mapValues(JoinVals &Other) {
3141 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
3142 computeAssignment(ValNo: i, Other);
3143 if (Vals[i].Resolution == CR_Impossible) {
3144 LLVM_DEBUG(dbgs() << "\t\tinterference at " << printReg(Reg) << ':' << i
3145 << '@' << LR.getValNumInfo(i)->def << '\n');
3146 return false;
3147 }
3148 }
3149 return true;
3150}
3151
3152bool JoinVals::taintExtent(
3153 unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other,
3154 SmallVectorImpl<std::pair<SlotIndex, LaneBitmask>> &TaintExtent) {
3155 VNInfo *VNI = LR.getValNumInfo(ValNo);
3156 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(index: VNI->def);
3157 SlotIndex MBBEnd = Indexes->getMBBEndIdx(mbb: MBB);
3158
3159 // Scan Other.LR from VNI.def to MBBEnd.
3160 LiveInterval::iterator OtherI = Other.LR.find(Pos: VNI->def);
3161 assert(OtherI != Other.LR.end() && "No conflict?");
3162 do {
3163 // OtherI is pointing to a tainted value. Abort the join if the tainted
3164 // lanes escape the block.
3165 SlotIndex End = OtherI->end;
3166 if (End >= MBBEnd) {
3167 LLVM_DEBUG(dbgs() << "\t\ttaints global " << printReg(Other.Reg) << ':'
3168 << OtherI->valno->id << '@' << OtherI->start << '\n');
3169 return false;
3170 }
3171 LLVM_DEBUG(dbgs() << "\t\ttaints local " << printReg(Other.Reg) << ':'
3172 << OtherI->valno->id << '@' << OtherI->start << " to "
3173 << End << '\n');
3174 // A dead def is not a problem.
3175 if (End.isDead())
3176 break;
3177 TaintExtent.push_back(Elt: std::make_pair(x&: End, y&: TaintedLanes));
3178
3179 // Check for another def in the MBB.
3180 if (++OtherI == Other.LR.end() || OtherI->start >= MBBEnd)
3181 break;
3182
3183 // Lanes written by the new def are no longer tainted.
3184 const Val &OV = Other.Vals[OtherI->valno->id];
3185 TaintedLanes &= ~OV.WriteLanes;
3186 if (!OV.RedefVNI)
3187 break;
3188 } while (TaintedLanes.any());
3189 return true;
3190}
3191
3192bool JoinVals::usesLanes(const MachineInstr &MI, Register Reg, unsigned SubIdx,
3193 LaneBitmask Lanes) const {
3194 if (MI.isDebugOrPseudoInstr())
3195 return false;
3196 for (const MachineOperand &MO : MI.all_uses()) {
3197 if (MO.getReg() != Reg)
3198 continue;
3199 if (!MO.readsReg())
3200 continue;
3201 unsigned S = TRI->composeSubRegIndices(a: SubIdx, b: MO.getSubReg());
3202 if ((Lanes & TRI->getSubRegIndexLaneMask(SubIdx: S)).any())
3203 return true;
3204 }
3205 return false;
3206}
3207
3208bool JoinVals::resolveConflicts(JoinVals &Other) {
3209 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
3210 Val &V = Vals[i];
3211 assert(V.Resolution != CR_Impossible && "Unresolvable conflict");
3212 if (V.Resolution != CR_Unresolved)
3213 continue;
3214 LLVM_DEBUG(dbgs() << "\t\tconflict at " << printReg(Reg) << ':' << i << '@'
3215 << LR.getValNumInfo(i)->def << ' '
3216 << PrintLaneMask(LaneMask) << '\n');
3217 if (SubRangeJoin)
3218 return false;
3219
3220 ++NumLaneConflicts;
3221 assert(V.OtherVNI && "Inconsistent conflict resolution.");
3222 VNInfo *VNI = LR.getValNumInfo(ValNo: i);
3223 const Val &OtherV = Other.Vals[V.OtherVNI->id];
3224
3225 // VNI is known to clobber some lanes in OtherVNI. If we go ahead with the
3226 // join, those lanes will be tainted with a wrong value. Get the extent of
3227 // the tainted lanes.
3228 LaneBitmask TaintedLanes = V.WriteLanes & OtherV.ValidLanes;
3229 SmallVector<std::pair<SlotIndex, LaneBitmask>, 8> TaintExtent;
3230 if (!taintExtent(ValNo: i, TaintedLanes, Other, TaintExtent))
3231 // Tainted lanes would extend beyond the basic block.
3232 return false;
3233
3234 assert(!TaintExtent.empty() && "There should be at least one conflict.");
3235
3236 // Now look at the instructions from VNI->def to TaintExtent (inclusive).
3237 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(index: VNI->def);
3238 MachineBasicBlock::iterator MI = MBB->begin();
3239 if (!VNI->isPHIDef()) {
3240 MI = Indexes->getInstructionFromIndex(index: VNI->def);
3241 if (!VNI->def.isEarlyClobber()) {
3242 // No need to check the instruction defining VNI for reads.
3243 ++MI;
3244 }
3245 }
3246 assert(!SlotIndex::isSameInstr(VNI->def, TaintExtent.front().first) &&
3247 "Interference ends on VNI->def. Should have been handled earlier");
3248 MachineInstr *LastMI =
3249 Indexes->getInstructionFromIndex(index: TaintExtent.front().first);
3250 assert(LastMI && "Range must end at a proper instruction");
3251 unsigned TaintNum = 0;
3252 while (true) {
3253 assert(MI != MBB->end() && "Bad LastMI");
3254 if (usesLanes(MI: *MI, Reg: Other.Reg, SubIdx: Other.SubIdx, Lanes: TaintedLanes)) {
3255 LLVM_DEBUG(dbgs() << "\t\ttainted lanes used by: " << *MI);
3256 return false;
3257 }
3258 // LastMI is the last instruction to use the current value.
3259 if (&*MI == LastMI) {
3260 if (++TaintNum == TaintExtent.size())
3261 break;
3262 LastMI = Indexes->getInstructionFromIndex(index: TaintExtent[TaintNum].first);
3263 assert(LastMI && "Range must end at a proper instruction");
3264 TaintedLanes = TaintExtent[TaintNum].second;
3265 }
3266 ++MI;
3267 }
3268
3269 // The tainted lanes are unused.
3270 V.Resolution = CR_Replace;
3271 ++NumLaneResolves;
3272 }
3273 return true;
3274}
3275
3276bool JoinVals::isPrunedValue(unsigned ValNo, JoinVals &Other) {
3277 Val &V = Vals[ValNo];
3278 if (V.Pruned || V.PrunedComputed)
3279 return V.Pruned;
3280
3281 if (V.Resolution != CR_Erase && V.Resolution != CR_Merge)
3282 return V.Pruned;
3283
3284 // Follow copies up the dominator tree and check if any intermediate value
3285 // has been pruned.
3286 V.PrunedComputed = true;
3287 V.Pruned = Other.isPrunedValue(ValNo: V.OtherVNI->id, Other&: *this);
3288 return V.Pruned;
3289}
3290
3291void JoinVals::pruneValues(JoinVals &Other,
3292 SmallVectorImpl<SlotIndex> &EndPoints,
3293 bool changeInstrs) {
3294 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
3295 SlotIndex Def = LR.getValNumInfo(ValNo: i)->def;
3296 switch (Vals[i].Resolution) {
3297 case CR_Keep:
3298 break;
3299 case CR_Replace: {
3300 // This value takes precedence over the value in Other.LR.
3301 LIS->pruneValue(LR&: Other.LR, Kill: Def, EndPoints: &EndPoints);
3302 // Check if we're replacing an IMPLICIT_DEF value. The IMPLICIT_DEF
3303 // instructions are only inserted to provide a live-out value for PHI
3304 // predecessors, so the instruction should simply go away once its value
3305 // has been replaced.
3306 Val &OtherV = Other.Vals[Vals[i].OtherVNI->id];
3307 bool EraseImpDef =
3308 OtherV.ErasableImplicitDef && OtherV.Resolution == CR_Keep;
3309 if (!Def.isBlock()) {
3310 if (changeInstrs) {
3311 // Remove <def,read-undef> flags. This def is now a partial redef.
3312 // Also remove dead flags since the joined live range will
3313 // continue past this instruction.
3314 for (MachineOperand &MO :
3315 Indexes->getInstructionFromIndex(index: Def)->all_defs()) {
3316 if (MO.getReg() == Reg) {
3317 if (MO.getSubReg() != 0 && MO.isUndef() && !EraseImpDef)
3318 MO.setIsUndef(false);
3319 MO.setIsDead(false);
3320 }
3321 }
3322 }
3323 // This value will reach instructions below, but we need to make sure
3324 // the live range also reaches the instruction at Def.
3325 if (!EraseImpDef)
3326 EndPoints.push_back(Elt: Def);
3327 }
3328 LLVM_DEBUG(dbgs() << "\t\tpruned " << printReg(Other.Reg) << " at " << Def
3329 << ": " << Other.LR << '\n');
3330 break;
3331 }
3332 case CR_Erase:
3333 case CR_Merge:
3334 if (isPrunedValue(ValNo: i, Other)) {
3335 // This value is ultimately a copy of a pruned value in LR or Other.LR.
3336 // We can no longer trust the value mapping computed by
3337 // computeAssignment(), the value that was originally copied could have
3338 // been replaced.
3339 Val &OtherV = Other.Vals[Vals[i].OtherVNI->id];
3340 bool EraseImpDef =
3341 OtherV.ErasableImplicitDef && OtherV.Resolution == CR_Keep;
3342 // If the source is an erasable IMPLICIT_DEF, the pruned endpoint is
3343 // the next def boundary, not a real use — discard it.
3344 LIS->pruneValue(LR, Kill: Def, EndPoints: EraseImpDef ? nullptr : &EndPoints);
3345 LLVM_DEBUG(dbgs() << "\t\tpruned all of " << printReg(Reg) << " at "
3346 << Def << ": " << LR << '\n');
3347 }
3348 break;
3349 case CR_Unresolved:
3350 case CR_Impossible:
3351 llvm_unreachable("Unresolved conflicts");
3352 }
3353 }
3354}
3355
3356// Check if the segment consists of a copied live-through value (i.e. the copy
3357// in the block only extended the liveness, of an undef value which we may need
3358// to handle).
3359static bool isLiveThrough(const LiveQueryResult Q) {
3360 return Q.valueIn() && Q.valueIn()->isPHIDef() && Q.valueIn() == Q.valueOut();
3361}
3362
3363/// Consider the following situation when coalescing the copy between
3364/// %31 and %45 at 800. (The vertical lines represent live range segments.)
3365///
3366/// Main range Subrange 0004 (sub2)
3367/// %31 %45 %31 %45
3368/// 544 %45 = COPY %28 + +
3369/// | v1 | v1
3370/// 560B bb.1: + +
3371/// 624 = %45.sub2 | v2 | v2
3372/// 800 %31 = COPY %45 + + + +
3373/// | v0 | v0
3374/// 816 %31.sub1 = ... + |
3375/// 880 %30 = COPY %31 | v1 +
3376/// 928 %45 = COPY %30 | + +
3377/// | | v0 | v0 <--+
3378/// 992B ; backedge -> bb.1 | + + |
3379/// 1040 = %31.sub0 + |
3380/// This value must remain
3381/// live-out!
3382///
3383/// Assuming that %31 is coalesced into %45, the copy at 928 becomes
3384/// redundant, since it copies the value from %45 back into it. The
3385/// conflict resolution for the main range determines that %45.v0 is
3386/// to be erased, which is ok since %31.v1 is identical to it.
3387/// The problem happens with the subrange for sub2: it has to be live
3388/// on exit from the block, but since 928 was actually a point of
3389/// definition of %45.sub2, %45.sub2 was not live immediately prior
3390/// to that definition. As a result, when 928 was erased, the value v0
3391/// for %45.sub2 was pruned in pruneSubRegValues. Consequently, an
3392/// IMPLICIT_DEF was inserted as a "backedge" definition for %45.sub2,
3393/// providing an incorrect value to the use at 624.
3394///
3395/// Since the main-range values %31.v1 and %45.v0 were proved to be
3396/// identical, the corresponding values in subranges must also be the
3397/// same. A redundant copy is removed because it's not needed, and not
3398/// because it copied an undefined value, so any liveness that originated
3399/// from that copy cannot disappear. When pruning a value that started
3400/// at the removed copy, the corresponding identical value must be
3401/// extended to replace it.
3402void JoinVals::pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask) {
3403 // Look for values being erased.
3404 bool DidPrune = false;
3405 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
3406 Val &V = Vals[i];
3407 // We should trigger in all cases in which eraseInstrs() does something.
3408 // match what eraseInstrs() is doing, print a message so
3409 if (V.Resolution != CR_Erase &&
3410 (V.Resolution != CR_Keep || !V.ErasableImplicitDef || !V.Pruned))
3411 continue;
3412
3413 // Check subranges at the point where the copy will be removed.
3414 SlotIndex Def = LR.getValNumInfo(ValNo: i)->def;
3415 SlotIndex OtherDef;
3416 if (V.Identical)
3417 OtherDef = V.OtherVNI->def;
3418
3419 // Print message so mismatches with eraseInstrs() can be diagnosed.
3420 LLVM_DEBUG(dbgs() << "\t\tExpecting instruction removal at " << Def
3421 << '\n');
3422 for (LiveInterval::SubRange &S : LI.subranges()) {
3423 LiveQueryResult Q = S.Query(Idx: Def);
3424
3425 // If a subrange starts at the copy then an undefined value has been
3426 // copied and we must remove that subrange value as well.
3427 VNInfo *ValueOut = Q.valueOutOrDead();
3428 if (ValueOut != nullptr &&
3429 (Q.valueIn() == nullptr ||
3430 (V.Identical && V.Resolution == CR_Erase && ValueOut->def == Def))) {
3431 LLVM_DEBUG(dbgs() << "\t\tPrune sublane " << PrintLaneMask(S.LaneMask)
3432 << " at " << Def << "\n");
3433 SmallVector<SlotIndex, 8> EndPoints;
3434 LIS->pruneValue(LR&: S, Kill: Def, EndPoints: &EndPoints);
3435 DidPrune = true;
3436 // Mark value number as unused.
3437 if (ValueOut->def == Def)
3438 ValueOut->markUnused();
3439
3440 if (V.Identical && S.Query(Idx: OtherDef).valueOutOrDead()) {
3441 // If V is identical to V.OtherVNI (and S was live at OtherDef),
3442 // then we can't simply prune V from S. V needs to be replaced
3443 // with V.OtherVNI.
3444 LIS->extendToIndices(LR&: S, Indices: EndPoints);
3445 }
3446
3447 // We may need to eliminate the subrange if the copy introduced a live
3448 // out undef value.
3449 if (ValueOut->isPHIDef())
3450 ShrinkMask |= S.LaneMask;
3451 continue;
3452 }
3453
3454 // If a subrange ends at the copy, then a value was copied but only
3455 // partially used later. Shrink the subregister range appropriately.
3456 //
3457 // Ultimately this calls shrinkToUses, so assuming ShrinkMask is
3458 // conservatively correct.
3459 if ((Q.valueIn() != nullptr && Q.valueOut() == nullptr) ||
3460 (V.Resolution == CR_Erase && isLiveThrough(Q))) {
3461 LLVM_DEBUG(dbgs() << "\t\tDead uses at sublane "
3462 << PrintLaneMask(S.LaneMask) << " at " << Def
3463 << "\n");
3464 ShrinkMask |= S.LaneMask;
3465 }
3466 }
3467 }
3468 if (DidPrune)
3469 LI.removeEmptySubRanges();
3470}
3471
3472/// Check if any of the subranges of @p LI contain a definition at @p Def.
3473static bool isDefInSubRange(LiveInterval &LI, SlotIndex Def) {
3474 for (LiveInterval::SubRange &SR : LI.subranges()) {
3475 if (VNInfo *VNI = SR.Query(Idx: Def).valueOutOrDead())
3476 if (VNI->def == Def)
3477 return true;
3478 }
3479 return false;
3480}
3481
3482void JoinVals::pruneMainSegments(LiveInterval &LI, bool &ShrinkMainRange) {
3483 assert(&static_cast<LiveRange &>(LI) == &LR);
3484
3485 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
3486 if (Vals[i].Resolution != CR_Keep)
3487 continue;
3488 VNInfo *VNI = LR.getValNumInfo(ValNo: i);
3489 if (VNI->isUnused() || VNI->isPHIDef() || isDefInSubRange(LI, Def: VNI->def))
3490 continue;
3491 Vals[i].Pruned = true;
3492 ShrinkMainRange = true;
3493 }
3494}
3495
3496void JoinVals::removeImplicitDefs() {
3497 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
3498 Val &V = Vals[i];
3499 if (V.Resolution != CR_Keep || !V.ErasableImplicitDef || !V.Pruned)
3500 continue;
3501
3502 VNInfo *VNI = LR.getValNumInfo(ValNo: i);
3503 VNI->markUnused();
3504 LR.removeValNo(ValNo: VNI);
3505 }
3506}
3507
3508void JoinVals::eraseInstrs(SmallPtrSetImpl<MachineInstr *> &ErasedInstrs,
3509 SmallVectorImpl<Register> &ShrinkRegs,
3510 LiveInterval *LI) {
3511 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
3512 // Get the def location before markUnused() below invalidates it.
3513 VNInfo *VNI = LR.getValNumInfo(ValNo: i);
3514 SlotIndex Def = VNI->def;
3515 switch (Vals[i].Resolution) {
3516 case CR_Keep: {
3517 // If an IMPLICIT_DEF value is pruned, it doesn't serve a purpose any
3518 // longer. The IMPLICIT_DEF instructions are only inserted by
3519 // PHIElimination to guarantee that all PHI predecessors have a value.
3520 if (!Vals[i].ErasableImplicitDef || !Vals[i].Pruned)
3521 break;
3522 // Remove value number i from LR.
3523 // For intervals with subranges, removing a segment from the main range
3524 // may require extending the previous segment: for each definition of
3525 // a subregister, there will be a corresponding def in the main range.
3526 // That def may fall in the middle of a segment from another subrange.
3527 // In such cases, removing this def from the main range must be
3528 // complemented by extending the main range to account for the liveness
3529 // of the other subrange.
3530 // The new end point of the main range segment to be extended.
3531 SlotIndex NewEnd;
3532 if (LI != nullptr) {
3533 LiveRange::iterator I = LR.FindSegmentContaining(Idx: Def);
3534 assert(I != LR.end());
3535 // Do not extend beyond the end of the segment being removed.
3536 // The segment may have been pruned in preparation for joining
3537 // live ranges.
3538 NewEnd = I->end;
3539 }
3540
3541 LR.removeValNo(ValNo: VNI);
3542 // Note that this VNInfo is reused and still referenced in NewVNInfo,
3543 // make it appear like an unused value number.
3544 VNI->markUnused();
3545
3546 if (LI != nullptr && LI->hasSubRanges()) {
3547 assert(static_cast<LiveRange *>(LI) == &LR);
3548 // Determine the end point based on the subrange information:
3549 // minimum of (earliest def of next segment,
3550 // latest end point of containing segment)
3551 SlotIndex ED, LE;
3552 for (LiveInterval::SubRange &SR : LI->subranges()) {
3553 LiveRange::iterator I = SR.find(Pos: Def);
3554 if (I == SR.end())
3555 continue;
3556 if (I->start > Def)
3557 ED = ED.isValid() ? std::min(a: ED, b: I->start) : I->start;
3558 else
3559 LE = LE.isValid() ? std::max(a: LE, b: I->end) : I->end;
3560 }
3561 if (LE.isValid())
3562 NewEnd = std::min(a: NewEnd, b: LE);
3563 if (ED.isValid())
3564 NewEnd = std::min(a: NewEnd, b: ED);
3565
3566 // We only want to do the extension if there was a subrange that
3567 // was live across Def.
3568 if (LE.isValid()) {
3569 LiveRange::iterator S = LR.find(Pos: Def);
3570 if (S != LR.begin())
3571 std::prev(x: S)->end = NewEnd;
3572 }
3573 }
3574 LLVM_DEBUG({
3575 dbgs() << "\t\tremoved " << i << '@' << Def << ": " << LR << '\n';
3576 if (LI != nullptr)
3577 dbgs() << "\t\t LHS = " << *LI << '\n';
3578 });
3579 [[fallthrough]];
3580 }
3581
3582 case CR_Erase: {
3583 MachineInstr *MI = Indexes->getInstructionFromIndex(index: Def);
3584 assert(MI && "No instruction to erase");
3585 if (MI->isCopy()) {
3586 Register Reg = MI->getOperand(i: 1).getReg();
3587 if (Reg.isVirtual() && Reg != CP.getSrcReg() && Reg != CP.getDstReg())
3588 ShrinkRegs.push_back(Elt: Reg);
3589 }
3590 ErasedInstrs.insert(Ptr: MI);
3591 LLVM_DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI);
3592 LIS->RemoveMachineInstrFromMaps(MI&: *MI);
3593 MI->eraseFromParent();
3594 break;
3595 }
3596 default:
3597 break;
3598 }
3599 }
3600}
3601
3602void RegisterCoalescer::joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
3603 LaneBitmask LaneMask,
3604 const CoalescerPair &CP) {
3605 SmallVector<VNInfo *, 16> NewVNInfo;
3606 JoinVals RHSVals(RRange, CP.getSrcReg(), CP.getSrcIdx(), LaneMask, NewVNInfo,
3607 CP, LIS, TRI, true, true);
3608 JoinVals LHSVals(LRange, CP.getDstReg(), CP.getDstIdx(), LaneMask, NewVNInfo,
3609 CP, LIS, TRI, true, true);
3610
3611 // Compute NewVNInfo and resolve conflicts (see also joinVirtRegs())
3612 // We should be able to resolve all conflicts here as we could successfully do
3613 // it on the mainrange already. There is however a problem when multiple
3614 // ranges get mapped to the "overflow" lane mask bit which creates unexpected
3615 // interferences.
3616 if (!LHSVals.mapValues(Other&: RHSVals) || !RHSVals.mapValues(Other&: LHSVals)) {
3617 // We already determined that it is legal to merge the intervals, so this
3618 // should never fail.
3619 llvm_unreachable("*** Couldn't join subrange!\n");
3620 }
3621 if (!LHSVals.resolveConflicts(Other&: RHSVals) ||
3622 !RHSVals.resolveConflicts(Other&: LHSVals)) {
3623 // We already determined that it is legal to merge the intervals, so this
3624 // should never fail.
3625 llvm_unreachable("*** Couldn't join subrange!\n");
3626 }
3627
3628 // The merging algorithm in LiveInterval::join() can't handle conflicting
3629 // value mappings, so we need to remove any live ranges that overlap a
3630 // CR_Replace resolution. Collect a set of end points that can be used to
3631 // restore the live range after joining.
3632 SmallVector<SlotIndex, 8> EndPoints;
3633 LHSVals.pruneValues(Other&: RHSVals, EndPoints, changeInstrs: false);
3634 RHSVals.pruneValues(Other&: LHSVals, EndPoints, changeInstrs: false);
3635
3636 LHSVals.removeImplicitDefs();
3637 RHSVals.removeImplicitDefs();
3638
3639 assert(LRange.verify() && RRange.verify());
3640
3641 // Join RRange into LHS.
3642 LRange.join(Other&: RRange, ValNoAssignments: LHSVals.getAssignments(), RHSValNoAssignments: RHSVals.getAssignments(),
3643 NewVNInfo);
3644
3645 LLVM_DEBUG(dbgs() << "\t\tjoined lanes: " << PrintLaneMask(LaneMask) << ' '
3646 << LRange << "\n");
3647 if (EndPoints.empty())
3648 return;
3649
3650 // Recompute the parts of the live range we had to remove because of
3651 // CR_Replace conflicts.
3652 LLVM_DEBUG({
3653 dbgs() << "\t\trestoring liveness to " << EndPoints.size() << " points: ";
3654 for (unsigned i = 0, n = EndPoints.size(); i != n; ++i) {
3655 dbgs() << EndPoints[i];
3656 if (i != n - 1)
3657 dbgs() << ',';
3658 }
3659 dbgs() << ": " << LRange << '\n';
3660 });
3661 LIS->extendToIndices(LR&: LRange, Indices: EndPoints);
3662}
3663
3664void RegisterCoalescer::mergeSubRangeInto(LiveInterval &LI,
3665 const LiveRange &ToMerge,
3666 LaneBitmask LaneMask,
3667 CoalescerPair &CP,
3668 unsigned ComposeSubRegIdx) {
3669 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
3670 LI.refineSubRanges(
3671 Allocator, LaneMask,
3672 Apply: [this, &Allocator, &ToMerge, &CP](LiveInterval::SubRange &SR) {
3673 if (SR.empty()) {
3674 SR.assign(Other: ToMerge, Allocator);
3675 } else {
3676 // joinSubRegRange() destroys the merged range, so we need a copy.
3677 LiveRange RangeCopy(ToMerge, Allocator);
3678 joinSubRegRanges(LRange&: SR, RRange&: RangeCopy, LaneMask: SR.LaneMask, CP);
3679 }
3680 },
3681 Indexes: *LIS->getSlotIndexes(), TRI: *TRI, ComposeSubRegIdx);
3682}
3683
3684bool RegisterCoalescer::isHighCostLiveInterval(LiveInterval &LI) {
3685 if (LI.valnos.size() < LargeIntervalSizeThreshold)
3686 return false;
3687 auto &Counter = LargeLIVisitCounter[LI.reg()];
3688 if (Counter < LargeIntervalFreqThreshold) {
3689 Counter++;
3690 return false;
3691 }
3692 return true;
3693}
3694
3695bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
3696 SmallVector<VNInfo *, 16> NewVNInfo;
3697 LiveInterval &RHS = LIS->getInterval(Reg: CP.getSrcReg());
3698 LiveInterval &LHS = LIS->getInterval(Reg: CP.getDstReg());
3699 bool TrackSubRegLiveness = MRI->shouldTrackSubRegLiveness(RC: *CP.getNewRC());
3700 JoinVals RHSVals(RHS, CP.getSrcReg(), CP.getSrcIdx(), LaneBitmask::getNone(),
3701 NewVNInfo, CP, LIS, TRI, false, TrackSubRegLiveness);
3702 JoinVals LHSVals(LHS, CP.getDstReg(), CP.getDstIdx(), LaneBitmask::getNone(),
3703 NewVNInfo, CP, LIS, TRI, false, TrackSubRegLiveness);
3704
3705 LLVM_DEBUG(dbgs() << "\t\tRHS = " << RHS << "\n\t\tLHS = " << LHS << '\n');
3706
3707 if (isHighCostLiveInterval(LI&: LHS) || isHighCostLiveInterval(LI&: RHS))
3708 return false;
3709
3710 // First compute NewVNInfo and the simple value mappings.
3711 // Detect impossible conflicts early.
3712 if (!LHSVals.mapValues(Other&: RHSVals) || !RHSVals.mapValues(Other&: LHSVals))
3713 return false;
3714
3715 // Some conflicts can only be resolved after all values have been mapped.
3716 if (!LHSVals.resolveConflicts(Other&: RHSVals) || !RHSVals.resolveConflicts(Other&: LHSVals))
3717 return false;
3718
3719 // All clear, the live ranges can be merged.
3720 if (RHS.hasSubRanges() || LHS.hasSubRanges()) {
3721 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
3722
3723 // Transform lanemasks from the LHS to masks in the coalesced register and
3724 // create initial subranges if necessary.
3725 unsigned DstIdx = CP.getDstIdx();
3726 if (!LHS.hasSubRanges()) {
3727 LaneBitmask Mask = DstIdx == 0 ? CP.getNewRC()->getLaneMask()
3728 : TRI->getSubRegIndexLaneMask(SubIdx: DstIdx);
3729 // LHS must support subregs or we wouldn't be in this codepath.
3730 assert(Mask.any());
3731 LHS.createSubRangeFrom(Allocator, LaneMask: Mask, CopyFrom: LHS);
3732 } else if (DstIdx != 0) {
3733 // Transform LHS lanemasks to new register class if necessary.
3734 for (LiveInterval::SubRange &R : LHS.subranges()) {
3735 LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(IdxA: DstIdx, Mask: R.LaneMask);
3736 R.LaneMask = Mask;
3737 }
3738 }
3739 LLVM_DEBUG(dbgs() << "\t\tLHST = " << printReg(CP.getDstReg()) << ' ' << LHS
3740 << '\n');
3741
3742 // Determine lanemasks of RHS in the coalesced register and merge subranges.
3743 unsigned SrcIdx = CP.getSrcIdx();
3744 if (!RHS.hasSubRanges()) {
3745 LaneBitmask Mask = SrcIdx == 0 ? CP.getNewRC()->getLaneMask()
3746 : TRI->getSubRegIndexLaneMask(SubIdx: SrcIdx);
3747 mergeSubRangeInto(LI&: LHS, ToMerge: RHS, LaneMask: Mask, CP, ComposeSubRegIdx: DstIdx);
3748 } else {
3749 // Pair up subranges and merge.
3750 for (LiveInterval::SubRange &R : RHS.subranges()) {
3751 LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(IdxA: SrcIdx, Mask: R.LaneMask);
3752 mergeSubRangeInto(LI&: LHS, ToMerge: R, LaneMask: Mask, CP, ComposeSubRegIdx: DstIdx);
3753 }
3754 }
3755 LLVM_DEBUG(dbgs() << "\tJoined SubRanges " << LHS << "\n");
3756
3757 // Pruning implicit defs from subranges may result in the main range
3758 // having stale segments.
3759 LHSVals.pruneMainSegments(LI&: LHS, ShrinkMainRange);
3760
3761 LHSVals.pruneSubRegValues(LI&: LHS, ShrinkMask);
3762 RHSVals.pruneSubRegValues(LI&: LHS, ShrinkMask);
3763 } else if (TrackSubRegLiveness && !CP.getDstIdx() && CP.getSrcIdx()) {
3764 LHS.createSubRangeFrom(Allocator&: LIS->getVNInfoAllocator(),
3765 LaneMask: CP.getNewRC()->getLaneMask(), CopyFrom: LHS);
3766 mergeSubRangeInto(LI&: LHS, ToMerge: RHS, LaneMask: TRI->getSubRegIndexLaneMask(SubIdx: CP.getSrcIdx()), CP,
3767 ComposeSubRegIdx: CP.getDstIdx());
3768 LHSVals.pruneMainSegments(LI&: LHS, ShrinkMainRange);
3769 LHSVals.pruneSubRegValues(LI&: LHS, ShrinkMask);
3770 }
3771
3772 // The merging algorithm in LiveInterval::join() can't handle conflicting
3773 // value mappings, so we need to remove any live ranges that overlap a
3774 // CR_Replace resolution. Collect a set of end points that can be used to
3775 // restore the live range after joining.
3776 SmallVector<SlotIndex, 8> EndPoints;
3777 LHSVals.pruneValues(Other&: RHSVals, EndPoints, changeInstrs: true);
3778 RHSVals.pruneValues(Other&: LHSVals, EndPoints, changeInstrs: true);
3779
3780 // Erase COPY and IMPLICIT_DEF instructions. This may cause some external
3781 // registers to require trimming.
3782 SmallVector<Register, 8> ShrinkRegs;
3783 LHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs, LI: &LHS);
3784 RHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
3785 while (!ShrinkRegs.empty())
3786 shrinkToUses(LI: &LIS->getInterval(Reg: ShrinkRegs.pop_back_val()));
3787
3788 // Scan and mark undef any DBG_VALUEs that would refer to a different value.
3789 checkMergingChangesDbgValues(CP, LHS, LHSVals, RHS, RHSVals);
3790
3791 // If the RHS covers any PHI locations that were tracked for debug-info, we
3792 // must update tracking information to reflect the join.
3793 auto RegIt = RegToPHIIdx.find(Val: CP.getSrcReg());
3794 if (RegIt != RegToPHIIdx.end()) {
3795 // Iterate over all the debug instruction numbers assigned this register.
3796 for (unsigned InstID : RegIt->second) {
3797 auto PHIIt = PHIValToPos.find(Val: InstID);
3798 assert(PHIIt != PHIValToPos.end());
3799 const SlotIndex &SI = PHIIt->second.SI;
3800
3801 // Does the RHS cover the position of this PHI?
3802 auto LII = RHS.find(Pos: SI);
3803 if (LII == RHS.end() || LII->start > SI)
3804 continue;
3805
3806 // Accept two kinds of subregister movement:
3807 // * When we merge from one register class into a larger register:
3808 // %1:gr16 = some-inst
3809 // ->
3810 // %2:gr32.sub_16bit = some-inst
3811 // * When the PHI is already in a subregister, and the larger class
3812 // is coalesced:
3813 // %2:gr32.sub_16bit = some-inst
3814 // %3:gr32 = COPY %2
3815 // ->
3816 // %3:gr32.sub_16bit = some-inst
3817 // Test for subregister move:
3818 if (CP.getSrcIdx() != 0 || CP.getDstIdx() != 0)
3819 // If we're moving between different subregisters, ignore this join.
3820 // The PHI will not get a location, dropping variable locations.
3821 if (PHIIt->second.SubReg && PHIIt->second.SubReg != CP.getSrcIdx())
3822 continue;
3823
3824 // Update our tracking of where the PHI is.
3825 PHIIt->second.Reg = CP.getDstReg();
3826
3827 // If we merge into a sub-register of a larger class (test above),
3828 // update SubReg.
3829 if (CP.getSrcIdx() != 0)
3830 PHIIt->second.SubReg = CP.getSrcIdx();
3831 }
3832
3833 // Rebuild the register index in RegToPHIIdx to account for PHIs tracking
3834 // different VRegs now. Copy old collection of debug instruction numbers and
3835 // erase the old one:
3836 auto InstrNums = RegIt->second;
3837 RegToPHIIdx.erase(I: RegIt);
3838
3839 // There might already be PHIs being tracked in the destination VReg. Insert
3840 // into an existing tracking collection, or insert a new one.
3841 RegIt = RegToPHIIdx.find(Val: CP.getDstReg());
3842 if (RegIt != RegToPHIIdx.end())
3843 llvm::append_range(C&: RegIt->second, R&: InstrNums);
3844 else
3845 RegToPHIIdx.insert(KV: {CP.getDstReg(), InstrNums});
3846 }
3847
3848 // Join RHS into LHS.
3849 LHS.join(Other&: RHS, ValNoAssignments: LHSVals.getAssignments(), RHSValNoAssignments: RHSVals.getAssignments(), NewVNInfo);
3850
3851 // Kill flags are going to be wrong if the live ranges were overlapping.
3852 // Eventually, we should simply clear all kill flags when computing live
3853 // ranges. They are reinserted after register allocation.
3854 MRI->clearKillFlags(Reg: LHS.reg());
3855 MRI->clearKillFlags(Reg: RHS.reg());
3856
3857 if (!EndPoints.empty()) {
3858 // Recompute the parts of the live range we had to remove because of
3859 // CR_Replace conflicts.
3860 LLVM_DEBUG({
3861 dbgs() << "\t\trestoring liveness to " << EndPoints.size() << " points: ";
3862 for (unsigned i = 0, n = EndPoints.size(); i != n; ++i) {
3863 dbgs() << EndPoints[i];
3864 if (i != n - 1)
3865 dbgs() << ',';
3866 }
3867 dbgs() << ": " << LHS << '\n';
3868 });
3869 LIS->extendToIndices(LR&: (LiveRange &)LHS, Indices: EndPoints);
3870 }
3871
3872 return true;
3873}
3874
3875bool RegisterCoalescer::joinIntervals(CoalescerPair &CP) {
3876 return CP.isPhys() ? joinReservedPhysReg(CP) : joinVirtRegs(CP);
3877}
3878
3879void RegisterCoalescer::buildVRegToDbgValueMap(MachineFunction &MF) {
3880 const SlotIndexes &Slots = *LIS->getSlotIndexes();
3881 SmallVector<MachineInstr *, 8> ToInsert;
3882
3883 // After collecting a block of DBG_VALUEs into ToInsert, enter them into the
3884 // vreg => DbgValueLoc map.
3885 auto CloseNewDVRange = [this, &ToInsert](SlotIndex Slot) {
3886 for (auto *X : ToInsert) {
3887 for (const auto &Op : X->debug_operands()) {
3888 if (Op.isReg() && Op.getReg().isVirtual())
3889 DbgVRegToValues[Op.getReg()].push_back(x: {Slot, X});
3890 }
3891 }
3892
3893 ToInsert.clear();
3894 };
3895
3896 // Iterate over all instructions, collecting them into the ToInsert vector.
3897 // Once a non-debug instruction is found, record the slot index of the
3898 // collected DBG_VALUEs.
3899 for (auto &MBB : MF) {
3900 SlotIndex CurrentSlot = Slots.getMBBStartIdx(mbb: &MBB);
3901
3902 for (auto &MI : MBB) {
3903 if (MI.isDebugValue()) {
3904 if (any_of(Range: MI.debug_operands(), P: [](const MachineOperand &MO) {
3905 return MO.isReg() && MO.getReg().isVirtual();
3906 }))
3907 ToInsert.push_back(Elt: &MI);
3908 } else if (!MI.isDebugOrPseudoInstr()) {
3909 CurrentSlot = Slots.getInstructionIndex(MI);
3910 CloseNewDVRange(CurrentSlot);
3911 }
3912 }
3913
3914 // Close range of DBG_VALUEs at the end of blocks.
3915 CloseNewDVRange(Slots.getMBBEndIdx(mbb: &MBB));
3916 }
3917
3918 // Sort all DBG_VALUEs we've seen by slot number.
3919 for (auto &Pair : DbgVRegToValues)
3920 llvm::sort(C&: Pair.second);
3921}
3922
3923void RegisterCoalescer::checkMergingChangesDbgValues(CoalescerPair &CP,
3924 LiveRange &LHS,
3925 JoinVals &LHSVals,
3926 LiveRange &RHS,
3927 JoinVals &RHSVals) {
3928 auto ScanForDstReg = [&](Register Reg) {
3929 checkMergingChangesDbgValuesImpl(Reg, OtherRange&: RHS, RegRange&: LHS, Vals2&: LHSVals);
3930 };
3931
3932 auto ScanForSrcReg = [&](Register Reg) {
3933 checkMergingChangesDbgValuesImpl(Reg, OtherRange&: LHS, RegRange&: RHS, Vals2&: RHSVals);
3934 };
3935
3936 // Scan for unsound updates of both the source and destination register.
3937 ScanForSrcReg(CP.getSrcReg());
3938 ScanForDstReg(CP.getDstReg());
3939}
3940
3941void RegisterCoalescer::checkMergingChangesDbgValuesImpl(Register Reg,
3942 LiveRange &OtherLR,
3943 LiveRange &RegLR,
3944 JoinVals &RegVals) {
3945 // Are there any DBG_VALUEs to examine?
3946 auto VRegMapIt = DbgVRegToValues.find(Val: Reg);
3947 if (VRegMapIt == DbgVRegToValues.end())
3948 return;
3949
3950 auto &DbgValueSet = VRegMapIt->second;
3951 auto DbgValueSetIt = DbgValueSet.begin();
3952 auto SegmentIt = OtherLR.begin();
3953
3954 bool LastUndefResult = false;
3955 SlotIndex LastUndefIdx;
3956
3957 // If the "Other" register is live at a slot Idx, test whether Reg can
3958 // safely be merged with it, or should be marked undef.
3959 auto ShouldUndef = [&RegVals, &RegLR, &LastUndefResult,
3960 &LastUndefIdx](SlotIndex Idx) -> bool {
3961 // Our worst-case performance typically happens with asan, causing very
3962 // many DBG_VALUEs of the same location. Cache a copy of the most recent
3963 // result for this edge-case.
3964 if (LastUndefIdx == Idx)
3965 return LastUndefResult;
3966
3967 // If the other range was live, and Reg's was not, the register coalescer
3968 // will not have tried to resolve any conflicts. We don't know whether
3969 // the DBG_VALUE will refer to the same value number, so it must be made
3970 // undef.
3971 auto OtherIt = RegLR.find(Pos: Idx);
3972 if (OtherIt == RegLR.end())
3973 return true;
3974
3975 // Both the registers were live: examine the conflict resolution record for
3976 // the value number Reg refers to. CR_Keep meant that this value number
3977 // "won" and the merged register definitely refers to that value. CR_Erase
3978 // means the value number was a redundant copy of the other value, which
3979 // was coalesced and Reg deleted. It's safe to refer to the other register
3980 // (which will be the source of the copy).
3981 auto Resolution = RegVals.getResolution(Num: OtherIt->valno->id);
3982 LastUndefResult =
3983 Resolution != JoinVals::CR_Keep && Resolution != JoinVals::CR_Erase;
3984 LastUndefIdx = Idx;
3985 return LastUndefResult;
3986 };
3987
3988 // Iterate over both the live-range of the "Other" register, and the set of
3989 // DBG_VALUEs for Reg at the same time. Advance whichever one has the lowest
3990 // slot index. This relies on the DbgValueSet being ordered.
3991 while (DbgValueSetIt != DbgValueSet.end() && SegmentIt != OtherLR.end()) {
3992 if (DbgValueSetIt->first < SegmentIt->end) {
3993 // "Other" is live and there is a DBG_VALUE of Reg: test if we should
3994 // set it undef.
3995 if (DbgValueSetIt->first >= SegmentIt->start) {
3996 bool HasReg = DbgValueSetIt->second->hasDebugOperandForReg(Reg);
3997 bool ShouldUndefReg = ShouldUndef(DbgValueSetIt->first);
3998 if (HasReg && ShouldUndefReg) {
3999 // Mark undef, erase record of this DBG_VALUE to avoid revisiting.
4000 DbgValueSetIt->second->setDebugValueUndef();
4001 continue;
4002 }
4003 }
4004 ++DbgValueSetIt;
4005 } else {
4006 ++SegmentIt;
4007 }
4008 }
4009}
4010
4011namespace {
4012
4013/// Information concerning MBB coalescing priority.
4014struct MBBPriorityInfo {
4015 MachineBasicBlock *MBB;
4016 unsigned Depth;
4017 bool IsSplit;
4018
4019 MBBPriorityInfo(MachineBasicBlock *mbb, unsigned depth, bool issplit)
4020 : MBB(mbb), Depth(depth), IsSplit(issplit) {}
4021};
4022
4023} // end anonymous namespace
4024
4025/// C-style comparator that sorts first based on the loop depth of the basic
4026/// block (the unsigned), and then on the MBB number.
4027///
4028/// EnableGlobalCopies assumes that the primary sort key is loop depth.
4029static int compareMBBPriority(const MBBPriorityInfo *LHS,
4030 const MBBPriorityInfo *RHS) {
4031 // Deeper loops first
4032 if (LHS->Depth != RHS->Depth)
4033 return LHS->Depth > RHS->Depth ? -1 : 1;
4034
4035 // Try to unsplit critical edges next.
4036 if (LHS->IsSplit != RHS->IsSplit)
4037 return LHS->IsSplit ? -1 : 1;
4038
4039 // Prefer blocks that are more connected in the CFG. This takes care of
4040 // the most difficult copies first while intervals are short.
4041 unsigned cl = LHS->MBB->pred_size() + LHS->MBB->succ_size();
4042 unsigned cr = RHS->MBB->pred_size() + RHS->MBB->succ_size();
4043 if (cl != cr)
4044 return cl > cr ? -1 : 1;
4045
4046 // As a last resort, sort by block number.
4047 return LHS->MBB->getNumber() < RHS->MBB->getNumber() ? -1 : 1;
4048}
4049
4050/// \returns true if the given copy uses or defines a local live range.
4051static bool isLocalCopy(MachineInstr *Copy, const LiveIntervals *LIS) {
4052 if (!Copy->isCopy())
4053 return false;
4054
4055 if (Copy->getOperand(i: 1).isUndef())
4056 return false;
4057
4058 Register SrcReg = Copy->getOperand(i: 1).getReg();
4059 Register DstReg = Copy->getOperand(i: 0).getReg();
4060 if (SrcReg.isPhysical() || DstReg.isPhysical())
4061 return false;
4062
4063 return LIS->intervalIsInOneMBB(LI: LIS->getInterval(Reg: SrcReg)) ||
4064 LIS->intervalIsInOneMBB(LI: LIS->getInterval(Reg: DstReg));
4065}
4066
4067void RegisterCoalescer::lateLiveIntervalUpdate() {
4068 for (Register reg : ToBeUpdated) {
4069 if (!LIS->hasInterval(Reg: reg))
4070 continue;
4071 LiveInterval &LI = LIS->getInterval(Reg: reg);
4072 shrinkToUses(LI: &LI, Dead: &DeadDefs);
4073 if (!DeadDefs.empty())
4074 eliminateDeadDefs();
4075 }
4076 ToBeUpdated.clear();
4077}
4078
4079bool RegisterCoalescer::copyCoalesceWorkList(
4080 MutableArrayRef<MachineInstr *> CurrList) {
4081 bool Progress = false;
4082 SmallPtrSet<MachineInstr *, 4> CurrentErasedInstrs;
4083 for (MachineInstr *&MI : CurrList) {
4084 if (!MI)
4085 continue;
4086 // Skip instruction pointers that have already been erased, for example by
4087 // dead code elimination.
4088 if (ErasedInstrs.count(Ptr: MI) || CurrentErasedInstrs.count(Ptr: MI)) {
4089 MI = nullptr;
4090 continue;
4091 }
4092 bool Again = false;
4093 bool Success = joinCopy(CopyMI: MI, Again, CurrentErasedInstrs);
4094 Progress |= Success;
4095 if (Success || !Again)
4096 MI = nullptr;
4097 }
4098 // Clear instructions not recorded in `ErasedInstrs` but erased.
4099 if (!CurrentErasedInstrs.empty()) {
4100 for (MachineInstr *&MI : CurrList) {
4101 if (MI && CurrentErasedInstrs.count(Ptr: MI))
4102 MI = nullptr;
4103 }
4104 for (MachineInstr *&MI : WorkList) {
4105 if (MI && CurrentErasedInstrs.count(Ptr: MI))
4106 MI = nullptr;
4107 }
4108 }
4109 return Progress;
4110}
4111
4112/// Check if DstReg is a terminal node.
4113/// I.e., it does not have any affinity other than \p Copy.
4114static bool isTerminalReg(Register DstReg, const MachineInstr &Copy,
4115 const MachineRegisterInfo *MRI) {
4116 assert(Copy.isCopyLike());
4117 // Check if the destination of this copy as any other affinity.
4118 for (const MachineInstr &MI : MRI->reg_nodbg_instructions(Reg: DstReg))
4119 if (&MI != &Copy && MI.isCopyLike())
4120 return false;
4121 return true;
4122}
4123
4124bool RegisterCoalescer::applyTerminalRule(const MachineInstr &Copy) const {
4125 assert(Copy.isCopyLike());
4126 if (!UseTerminalRule)
4127 return false;
4128 Register SrcReg, DstReg;
4129 unsigned SrcSubReg = 0, DstSubReg = 0;
4130 if (!isMoveInstr(tri: *TRI, MI: &Copy, Src&: SrcReg, Dst&: DstReg, SrcSub&: SrcSubReg, DstSub&: DstSubReg))
4131 return false;
4132 // Check if the destination of this copy has any other affinity.
4133 if (DstReg.isPhysical() ||
4134 // If SrcReg is a physical register, the copy won't be coalesced.
4135 // Ignoring it may have other side effect (like missing
4136 // rematerialization). So keep it.
4137 SrcReg.isPhysical() || !isTerminalReg(DstReg, Copy, MRI))
4138 return false;
4139
4140 // DstReg is a terminal node. Check if it interferes with any other
4141 // copy involving SrcReg.
4142 const MachineBasicBlock *OrigBB = Copy.getParent();
4143 const LiveInterval &DstLI = LIS->getInterval(Reg: DstReg);
4144 for (const MachineInstr &MI : MRI->reg_nodbg_instructions(Reg: SrcReg)) {
4145 // Technically we should check if the weight of the new copy is
4146 // interesting compared to the other one and update the weight
4147 // of the copies accordingly. However, this would only work if
4148 // we would gather all the copies first then coalesce, whereas
4149 // right now we interleave both actions.
4150 // For now, just consider the copies that are in the same block.
4151 if (&MI == &Copy || !MI.isCopyLike() || MI.getParent() != OrigBB)
4152 continue;
4153 Register OtherSrcReg, OtherReg;
4154 unsigned OtherSrcSubReg = 0, OtherSubReg = 0;
4155 if (!isMoveInstr(tri: *TRI, MI: &MI, Src&: OtherSrcReg, Dst&: OtherReg, SrcSub&: OtherSrcSubReg,
4156 DstSub&: OtherSubReg))
4157 return false;
4158 if (OtherReg == SrcReg)
4159 OtherReg = OtherSrcReg;
4160 // Check if OtherReg is a non-terminal.
4161 if (OtherReg.isPhysical() || isTerminalReg(DstReg: OtherReg, Copy: MI, MRI))
4162 continue;
4163 // Check that OtherReg interfere with DstReg.
4164 if (LIS->getInterval(Reg: OtherReg).overlaps(other: DstLI)) {
4165 LLVM_DEBUG(dbgs() << "Apply terminal rule for: " << printReg(DstReg)
4166 << '\n');
4167 return true;
4168 }
4169 }
4170 return false;
4171}
4172
4173void RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
4174 LLVM_DEBUG(dbgs() << MBB->getName() << ":\n");
4175
4176 // Collect all copy-like instructions in MBB. Don't start coalescing anything
4177 // yet, it might invalidate the iterator.
4178 const unsigned PrevSize = WorkList.size();
4179 if (JoinGlobalCopies) {
4180 SmallVector<MachineInstr *, 2> LocalTerminals;
4181 SmallVector<MachineInstr *, 2> GlobalTerminals;
4182 // Coalesce copies top-down to propagate coalescing and rematerialization
4183 // forward.
4184 for (MachineInstr &MI : *MBB) {
4185 if (!MI.isCopyLike())
4186 continue;
4187 bool ApplyTerminalRule = applyTerminalRule(Copy: MI);
4188 if (isLocalCopy(Copy: &MI, LIS)) {
4189 if (ApplyTerminalRule)
4190 LocalTerminals.push_back(Elt: &MI);
4191 else
4192 LocalWorkList.push_back(Elt: &MI);
4193 } else {
4194 if (ApplyTerminalRule)
4195 GlobalTerminals.push_back(Elt: &MI);
4196 else
4197 WorkList.push_back(Elt: &MI);
4198 }
4199 }
4200 // Append the copies evicted by the terminal rule at the end of the list.
4201 LocalWorkList.append(in_start: LocalTerminals.begin(), in_end: LocalTerminals.end());
4202 WorkList.append(in_start: GlobalTerminals.begin(), in_end: GlobalTerminals.end());
4203 } else {
4204 SmallVector<MachineInstr *, 2> Terminals;
4205 // Coalesce copies top-down to propagate coalescing and rematerialization
4206 // forward.
4207 for (MachineInstr &MII : *MBB)
4208 if (MII.isCopyLike()) {
4209 if (applyTerminalRule(Copy: MII))
4210 Terminals.push_back(Elt: &MII);
4211 else
4212 WorkList.push_back(Elt: &MII);
4213 }
4214 // Append the copies evicted by the terminal rule at the end of the list.
4215 WorkList.append(in_start: Terminals.begin(), in_end: Terminals.end());
4216 }
4217 // Try coalescing the collected copies immediately, and remove the nulls.
4218 // This prevents the WorkList from getting too large since most copies are
4219 // joinable on the first attempt.
4220 MutableArrayRef<MachineInstr *> CurrList(WorkList.begin() + PrevSize,
4221 WorkList.end());
4222 if (copyCoalesceWorkList(CurrList))
4223 WorkList.erase(
4224 CS: std::remove(first: WorkList.begin() + PrevSize, last: WorkList.end(), value: nullptr),
4225 CE: WorkList.end());
4226}
4227
4228void RegisterCoalescer::coalesceLocals() {
4229 copyCoalesceWorkList(CurrList: LocalWorkList);
4230 for (MachineInstr *MI : LocalWorkList) {
4231 if (MI)
4232 WorkList.push_back(Elt: MI);
4233 }
4234 LocalWorkList.clear();
4235}
4236
4237void RegisterCoalescer::joinAllIntervals() {
4238 LLVM_DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
4239 assert(WorkList.empty() && LocalWorkList.empty() && "Old data still around.");
4240
4241 std::vector<MBBPriorityInfo> MBBs;
4242 MBBs.reserve(n: MF->size());
4243 for (MachineBasicBlock &MBB : *MF) {
4244 MBBs.push_back(x: MBBPriorityInfo(&MBB, Loops->getLoopDepth(BB: &MBB),
4245 JoinSplitEdges && isSplitEdge(MBB: &MBB)));
4246 }
4247 array_pod_sort(Start: MBBs.begin(), End: MBBs.end(), Compare: compareMBBPriority);
4248
4249 // Coalesce intervals in MBB priority order.
4250 unsigned CurrDepth = std::numeric_limits<unsigned>::max();
4251 for (MBBPriorityInfo &MBB : MBBs) {
4252 // Try coalescing the collected local copies for deeper loops.
4253 if (JoinGlobalCopies && MBB.Depth < CurrDepth) {
4254 coalesceLocals();
4255 CurrDepth = MBB.Depth;
4256 }
4257 copyCoalesceInMBB(MBB: MBB.MBB);
4258 }
4259 lateLiveIntervalUpdate();
4260 coalesceLocals();
4261
4262 // Joining intervals can allow other intervals to be joined. Iteratively join
4263 // until we make no progress.
4264 while (copyCoalesceWorkList(CurrList: WorkList))
4265 /* empty */;
4266 lateLiveIntervalUpdate();
4267}
4268
4269PreservedAnalyses
4270RegisterCoalescerPass::run(MachineFunction &MF,
4271 MachineFunctionAnalysisManager &MFAM) {
4272 MFPropsModifier _(*this, MF);
4273 auto &LIS = MFAM.getResult<LiveIntervalsAnalysis>(IR&: MF);
4274 auto &Loops = MFAM.getResult<MachineLoopAnalysis>(IR&: MF);
4275 auto *SI = MFAM.getCachedResult<SlotIndexesAnalysis>(IR&: MF);
4276 RegisterCoalescer Impl(&LIS, SI, &Loops);
4277 if (!Impl.run(MF))
4278 return PreservedAnalyses::all();
4279 auto PA = getMachineFunctionPassPreservedAnalyses();
4280 PA.preserveSet<CFGAnalyses>();
4281 PA.preserve<LiveIntervalsAnalysis>();
4282 PA.preserve<SlotIndexesAnalysis>();
4283 PA.preserve<MachineLoopAnalysis>();
4284 PA.preserve<MachineDominatorTreeAnalysis>();
4285 return PA;
4286}
4287
4288bool RegisterCoalescerLegacy::runOnMachineFunction(MachineFunction &MF) {
4289 auto *LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
4290 auto *Loops = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
4291 auto *SIWrapper = getAnalysisIfAvailable<SlotIndexesWrapperPass>();
4292 SlotIndexes *SI = SIWrapper ? &SIWrapper->getSI() : nullptr;
4293 RegisterCoalescer Impl(LIS, SI, Loops);
4294 return Impl.run(MF);
4295}
4296
4297bool RegisterCoalescer::run(MachineFunction &fn) {
4298 LLVM_DEBUG(dbgs() << "********** REGISTER COALESCER **********\n"
4299 << "********** Function: " << fn.getName() << '\n');
4300
4301 // Variables changed between a setjmp and a longjump can have undefined value
4302 // after the longjmp. This behaviour can be observed if such a variable is
4303 // spilled, so longjmp won't restore the value in the spill slot.
4304 // RegisterCoalescer should not run in functions with a setjmp to avoid
4305 // merging such undefined variables with predictable ones.
4306 //
4307 // TODO: Could specifically disable coalescing registers live across setjmp
4308 // calls
4309 if (fn.exposesReturnsTwice()) {
4310 LLVM_DEBUG(
4311 dbgs() << "* Skipped as it exposes functions that returns twice.\n");
4312 return false;
4313 }
4314
4315 MF = &fn;
4316 MRI = &fn.getRegInfo();
4317 const TargetSubtargetInfo &STI = fn.getSubtarget();
4318 TRI = STI.getRegisterInfo();
4319 TII = STI.getInstrInfo();
4320 if (EnableGlobalCopies == cl::boolOrDefault::BOU_UNSET)
4321 JoinGlobalCopies = STI.enableJoinGlobalCopies();
4322 else
4323 JoinGlobalCopies = (EnableGlobalCopies == cl::boolOrDefault::BOU_TRUE);
4324
4325 // If there are PHIs tracked by debug-info, they will need updating during
4326 // coalescing. Build an index of those PHIs to ease updating.
4327 SlotIndexes *Slots = LIS->getSlotIndexes();
4328 for (const auto &DebugPHI : MF->DebugPHIPositions) {
4329 MachineBasicBlock *MBB = DebugPHI.second.MBB;
4330 Register Reg = DebugPHI.second.Reg;
4331 unsigned SubReg = DebugPHI.second.SubReg;
4332 SlotIndex SI = Slots->getMBBStartIdx(mbb: MBB);
4333 PHIValPos P = {.SI: SI, .Reg: Reg, .SubReg: SubReg};
4334 PHIValToPos.insert(KV: std::make_pair(x: DebugPHI.first, y&: P));
4335 RegToPHIIdx[Reg].push_back(Elt: DebugPHI.first);
4336 }
4337
4338 // The MachineScheduler does not currently require JoinSplitEdges. This will
4339 // either be enabled unconditionally or replaced by a more general live range
4340 // splitting optimization.
4341 JoinSplitEdges = EnableJoinSplits;
4342
4343 if (VerifyCoalescing)
4344 MF->verify(LiveInts: LIS, Indexes: SI, Banner: "Before register coalescing", OS: &errs());
4345
4346 DbgVRegToValues.clear();
4347 buildVRegToDbgValueMap(MF&: fn);
4348
4349 RegClassInfo.runOnMachineFunction(MF: fn);
4350
4351 // Join (coalesce) intervals if requested.
4352 if (EnableJoining)
4353 joinAllIntervals();
4354
4355 // After deleting a lot of copies, register classes may be less constrained.
4356 // Removing sub-register operands may allow GR32_ABCD -> GR32 and DPR_VFP2 ->
4357 // DPR inflation.
4358 array_pod_sort(Start: InflateRegs.begin(), End: InflateRegs.end());
4359 InflateRegs.erase(CS: llvm::unique(R&: InflateRegs), CE: InflateRegs.end());
4360 LLVM_DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size()
4361 << " regs.\n");
4362 for (Register Reg : InflateRegs) {
4363 if (MRI->reg_nodbg_empty(RegNo: Reg))
4364 continue;
4365 if (MRI->recomputeRegClass(Reg)) {
4366 LLVM_DEBUG(dbgs() << printReg(Reg) << " inflated to "
4367 << TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n');
4368 ++NumInflated;
4369
4370 LiveInterval &LI = LIS->getInterval(Reg);
4371 if (LI.hasSubRanges()) {
4372 // If the inflated register class does not support subregisters anymore
4373 // remove the subranges.
4374 if (!MRI->shouldTrackSubRegLiveness(VReg: Reg)) {
4375 LI.clearSubRanges();
4376 } else {
4377#ifndef NDEBUG
4378 LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
4379 // If subranges are still supported, then the same subregs
4380 // should still be supported.
4381 for (LiveInterval::SubRange &S : LI.subranges()) {
4382 assert((S.LaneMask & ~MaxMask).none());
4383 }
4384#endif
4385 }
4386 }
4387 }
4388 }
4389
4390 // After coalescing, update any PHIs that are being tracked by debug-info
4391 // with their new VReg locations.
4392 for (auto &p : MF->DebugPHIPositions) {
4393 auto it = PHIValToPos.find(Val: p.first);
4394 assert(it != PHIValToPos.end());
4395 p.second.Reg = it->second.Reg;
4396 p.second.SubReg = it->second.SubReg;
4397 }
4398
4399 PHIValToPos.clear();
4400 RegToPHIIdx.clear();
4401
4402 LLVM_DEBUG(LIS->dump());
4403
4404 if (VerifyCoalescing)
4405 MF->verify(LiveInts: LIS, Indexes: SI, Banner: "After register coalescing", OS: &errs());
4406 return true;
4407}
4408