1//===-- FunctionLoweringInfo.cpp ------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements routines for translating functions from LLVM IR into
10// Machine IR.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/FunctionLoweringInfo.h"
15#include "llvm/ADT/APInt.h"
16#include "llvm/Analysis/UniformityAnalysis.h"
17#include "llvm/CodeGen/Analysis.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/TargetFrameLowering.h"
23#include "llvm/CodeGen/TargetInstrInfo.h"
24#include "llvm/CodeGen/TargetLowering.h"
25#include "llvm/CodeGen/TargetRegisterInfo.h"
26#include "llvm/CodeGen/TargetSubtargetInfo.h"
27#include "llvm/CodeGen/WinEHFuncInfo.h"
28#include "llvm/IR/Constants.h"
29#include "llvm/IR/DataLayout.h"
30#include "llvm/IR/DerivedTypes.h"
31#include "llvm/IR/Function.h"
32#include "llvm/IR/Instructions.h"
33#include "llvm/IR/IntrinsicInst.h"
34#include "llvm/IR/Intrinsics.h"
35#include "llvm/IR/Module.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/raw_ostream.h"
39#include "llvm/Target/TargetMachine.h"
40#include <algorithm>
41using namespace llvm;
42
43#define DEBUG_TYPE "function-lowering-info"
44
45/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
46/// PHI nodes or outside of the basic block that defines it, or used by a
47/// switch or atomic instruction, which may expand to multiple basic blocks.
48static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
49 if (I->use_empty()) return false;
50 if (isa<PHINode>(Val: I)) return true;
51 const BasicBlock *BB = I->getParent();
52 for (const User *U : I->users())
53 if (cast<Instruction>(Val: U)->getParent() != BB || isa<PHINode>(Val: U))
54 return true;
55
56 return false;
57}
58
59static ISD::NodeType getPreferredExtendForValue(const Instruction *I) {
60 // For the users of the source value being used for compare instruction, if
61 // the number of signed predicate is greater than unsigned predicate, we
62 // prefer to use SIGN_EXTEND.
63 //
64 // With this optimization, we would be able to reduce some redundant sign or
65 // zero extension instruction, and eventually more machine CSE opportunities
66 // can be exposed.
67 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
68 unsigned NumOfSigned = 0, NumOfUnsigned = 0;
69 for (const Use &U : I->uses()) {
70 if (const auto *CI = dyn_cast<CmpInst>(Val: U.getUser())) {
71 NumOfSigned += CI->isSigned();
72 NumOfUnsigned += CI->isUnsigned();
73 }
74 if (const auto *CallI = dyn_cast<CallBase>(Val: U.getUser())) {
75 if (!CallI->isArgOperand(U: &U))
76 continue;
77 unsigned ArgNo = CallI->getArgOperandNo(U: &U);
78 NumOfUnsigned += CallI->paramHasAttr(ArgNo, Kind: Attribute::ZExt);
79 NumOfSigned += CallI->paramHasAttr(ArgNo, Kind: Attribute::SExt);
80 }
81 }
82 if (NumOfSigned > NumOfUnsigned)
83 ExtendKind = ISD::SIGN_EXTEND;
84
85 return ExtendKind;
86}
87
88void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
89 SelectionDAG *DAG) {
90 Fn = &fn;
91 MF = &mf;
92 TLI = MF->getSubtarget().getTargetLowering();
93 RegInfo = &MF->getRegInfo();
94 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
95 UA = DAG->getUniformityInfo();
96 // Prefer the "exception-model" module flag, else the TargetOptions default.
97 ExceptionModel = Fn->getParent()->getExceptionModel();
98 if (ExceptionModel == ExceptionHandling::Default)
99 ExceptionModel = MF->getTarget().getExceptionModel();
100
101 // Check whether the function can return without sret-demotion.
102 SmallVector<ISD::OutputArg, 4> Outs;
103 CallingConv::ID CC = Fn->getCallingConv();
104
105 GetReturnInfo(CC, ReturnType: Fn->getReturnType(), attr: Fn->getAttributes(), Outs, TLI: *TLI,
106 DL: mf.getDataLayout());
107 CanLowerReturn =
108 TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext(), RetTy: Fn->getReturnType());
109
110 // If this personality uses funclets, we need to do a bit more work.
111 DenseMap<const AllocaInst *, TinyPtrVector<int *>> CatchObjects;
112 EHPersonality Personality = classifyEHPersonality(
113 Pers: Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr);
114 if (isFuncletEHPersonality(Pers: Personality)) {
115 // Calculate state numbers if we haven't already.
116 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
117 if (Personality == EHPersonality::MSVC_CXX)
118 calculateWinCXXEHStateNumbers(ParentFn: &fn, FuncInfo&: EHInfo);
119 else if (isAsynchronousEHPersonality(Pers: Personality))
120 calculateSEHStateNumbers(ParentFn: &fn, FuncInfo&: EHInfo);
121 else if (Personality == EHPersonality::CoreCLR)
122 calculateClrEHStateNumbers(Fn: &fn, FuncInfo&: EHInfo);
123
124 // Map all BB references in the WinEH data to MBBs.
125 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
126 for (WinEHHandlerType &H : TBME.HandlerArray) {
127 if (const AllocaInst *AI = H.CatchObj.Alloca)
128 CatchObjects[AI].push_back(NewVal: &H.CatchObj.FrameIndex);
129 else
130 H.CatchObj.FrameIndex = INT_MAX;
131 }
132 }
133 }
134
135 // Initialize the mapping of values to registers. This is only set up for
136 // instruction values that are used outside of the block that defines
137 // them.
138 const Align StackAlign = TFI->getStackAlign();
139 for (const BasicBlock &BB : *Fn) {
140 for (const Instruction &I : BB) {
141 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Val: &I)) {
142 Align Alignment = AI->getAlign();
143
144 // Static allocas can be folded into the initial stack frame
145 // adjustment. For targets that don't realign the stack, don't
146 // do this if there is an extra alignment requirement.
147 if (AI->isStaticAlloca() &&
148 (TFI->isStackRealignable() || (Alignment <= StackAlign))) {
149 TypeSize AllocaSize = AI->getAllocationSize(DL: MF->getDataLayout())
150 .value_or(u: TypeSize::getZero());
151 uint64_t TySize = AllocaSize.getKnownMinValue();
152 if (TySize == 0)
153 TySize = 1; // Don't create zero-sized stack objects.
154 int FrameIndex = INT_MAX;
155 auto Iter = CatchObjects.find(Val: AI);
156 if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) {
157 FrameIndex = MF->getFrameInfo().CreateFixedObject(
158 Size: TySize, SPOffset: 0, /*IsImmutable=*/false, /*isAliased=*/true);
159 MF->getFrameInfo().setObjectAlignment(ObjectIdx: FrameIndex, Alignment);
160 } else {
161 FrameIndex = MF->getFrameInfo().CreateStackObject(Size: TySize, Alignment,
162 isSpillSlot: false, Alloca: AI);
163 }
164
165 // Scalable vectors and structures that contain scalable vectors may
166 // need a special StackID to distinguish them from other (fixed size)
167 // stack objects.
168 if (AllocaSize.isScalable())
169 MF->getFrameInfo().setStackID(ObjectIdx: FrameIndex,
170 ID: TFI->getStackIDForScalableVectors());
171
172 StaticAllocaMap[AI] = FrameIndex;
173 // Update the catch handler information.
174 if (Iter != CatchObjects.end()) {
175 for (int *CatchObjPtr : Iter->second)
176 *CatchObjPtr = FrameIndex;
177 }
178 } else {
179 // FIXME: Overaligned static allocas should be grouped into
180 // a single dynamic allocation instead of using a separate
181 // stack allocation for each one.
182 // Inform the Frame Information that we have variable-sized objects.
183 MF->getFrameInfo().CreateVariableSizedObject(
184 Alignment: Alignment <= StackAlign ? Align(1) : Alignment, Alloca: AI);
185 }
186 } else if (auto *Call = dyn_cast<CallBase>(Val: &I)) {
187 // Look for inline asm that clobbers the SP register.
188 if (Call->isInlineAsm()) {
189 Register SP = TLI->getStackPointerRegisterToSaveRestore();
190 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
191 std::vector<TargetLowering::AsmOperandInfo> Ops =
192 TLI->ParseConstraints(DL: Fn->getDataLayout(), TRI,
193 Call: *Call);
194 for (TargetLowering::AsmOperandInfo &Op : Ops) {
195 if (Op.Type == InlineAsm::isClobber) {
196 // Clobbers don't have SDValue operands, hence SDValue().
197 TLI->ComputeConstraintToUse(OpInfo&: Op, Op: SDValue(), DAG);
198 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
199 TLI->getRegForInlineAsmConstraint(TRI, Constraint: Op.ConstraintCode,
200 VT: Op.ConstraintVT);
201 if (PhysReg.first == SP)
202 MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
203 }
204 }
205 }
206 if (const auto *II = dyn_cast<IntrinsicInst>(Val: &I)) {
207 switch (II->getIntrinsicID()) {
208 case Intrinsic::vastart:
209 // Look for calls to the @llvm.va_start intrinsic. We can omit
210 // some prologue boilerplate for variadic functions that don't
211 // examine their arguments.
212 MF->getFrameInfo().setHasVAStart(true);
213 break;
214 case Intrinsic::fake_use:
215 // Look for llvm.fake.uses, so that we can remove loads into fake
216 // uses later if necessary.
217 MF->setHasFakeUses(true);
218 break;
219 default:
220 break;
221 }
222 }
223
224 // If we have a musttail call in a variadic function, we need to ensure
225 // we forward implicit register parameters.
226 if (const auto *CI = dyn_cast<CallInst>(Val: &I)) {
227 if (CI->isMustTailCall() && Fn->isVarArg())
228 MF->getFrameInfo().setHasMustTailInVarArgFunc(true);
229 }
230
231 // Determine if there is a call to setjmp in the machine function.
232 if (Call->hasFnAttr(Kind: Attribute::ReturnsTwice))
233 MF->setExposesReturnsTwice(true);
234 }
235
236 // Mark values used outside their block as exported, by allocating
237 // a virtual register for them.
238 if (isUsedOutsideOfDefiningBlock(I: &I))
239 if (!isa<AllocaInst>(Val: I) || !StaticAllocaMap.count(Val: cast<AllocaInst>(Val: &I)))
240 InitializeRegForValue(V: &I);
241
242 // Decide the preferred extend type for a value. This iterates over all
243 // users and therefore isn't cheap, so don't do this at O0.
244 if (DAG->getOptLevel() != CodeGenOptLevel::None)
245 PreferredExtendType[&I] = getPreferredExtendForValue(I: &I);
246 }
247 }
248
249 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
250 // also creates the initial PHI MachineInstrs, though none of the input
251 // operands are populated.
252 MBBMap.resize(N: Fn->getMaxBlockNumber());
253 for (const BasicBlock &BB : *Fn) {
254 // Don't create MachineBasicBlocks for imaginary EH pad blocks. These blocks
255 // are really data, and no instructions can live here.
256 if (BB.isEHPad()) {
257 BasicBlock::const_iterator PadInst = BB.getFirstNonPHIIt();
258 // If this is a non-landingpad EH pad, mark this function as using
259 // funclets.
260 // FIXME: SEH catchpads do not create EH scope/funclets, so we could avoid
261 // setting this in such cases in order to improve frame layout.
262 if (!isa<LandingPadInst>(Val: PadInst)) {
263 MF->setHasEHScopes(true);
264 MF->setHasEHFunclets(true);
265 MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
266 }
267 if (isa<CatchSwitchInst>(Val: PadInst)) {
268 assert(BB.begin() == PadInst &&
269 "WinEHPrepare failed to remove PHIs from imaginary BBs");
270 continue;
271 }
272 if (isa<FuncletPadInst>(Val: PadInst) &&
273 Personality != EHPersonality::Wasm_CXX)
274 assert(BB.begin() == PadInst && "WinEHPrepare failed to demote PHIs");
275 }
276
277 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB: &BB);
278 MBBMap[BB.getNumber()] = MBB;
279 MF->push_back(MBB);
280
281 // Transfer the address-taken flag. This is necessary because there could
282 // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
283 // the first one should be marked.
284 // Only mark the block if the BlockAddress actually has users. The
285 // hasAddressTaken flag may be stale if the BlockAddress was optimized away
286 // but the constant still exists in the uniquing table.
287 if (BB.hasAddressTaken()) {
288 if (BlockAddress *BA = BlockAddress::lookup(BB: &BB))
289 if (!BA->hasZeroLiveUses())
290 MBB->setAddressTakenIRBlock(const_cast<BasicBlock *>(&BB));
291 }
292
293 // Mark landing pad blocks.
294 if (BB.isEHPad())
295 MBB->setIsEHPad();
296
297 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
298 // appropriate.
299 for (const PHINode &PN : BB.phis()) {
300 if (PN.use_empty())
301 continue;
302
303 // Skip empty types
304 if (PN.getType()->isEmptyTy())
305 continue;
306
307 DebugLoc DL = PN.getDebugLoc();
308 Register PHIReg = ValueMap[&PN];
309 assert(PHIReg && "PHI node does not have an assigned virtual register!");
310
311 SmallVector<EVT, 4> ValueVTs;
312 ComputeValueVTs(TLI: *TLI, DL: MF->getDataLayout(), Ty: PN.getType(), ValueVTs);
313 for (EVT VT : ValueVTs) {
314 unsigned NumRegisters = TLI->getNumRegisters(Context&: Fn->getContext(), VT);
315 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
316 for (unsigned i = 0; i != NumRegisters; ++i)
317 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: TargetOpcode::PHI), DestReg: PHIReg + i);
318 PHIReg += NumRegisters;
319 }
320 }
321 }
322
323 if (isFuncletEHPersonality(Pers: Personality)) {
324 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
325
326 // Map all BB references in the WinEH data to MBBs.
327 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
328 for (WinEHHandlerType &H : TBME.HandlerArray) {
329 if (H.Handler)
330 H.Handler = getMBB(BB: cast<const BasicBlock *>(Val&: H.Handler));
331 }
332 }
333 for (CxxUnwindMapEntry &UME : EHInfo.CxxUnwindMap)
334 if (UME.Cleanup)
335 UME.Cleanup = getMBB(BB: cast<const BasicBlock *>(Val&: UME.Cleanup));
336 for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap)
337 UME.Handler = getMBB(BB: cast<const BasicBlock *>(Val&: UME.Handler));
338 for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap)
339 CME.Handler = getMBB(BB: cast<const BasicBlock *>(Val&: CME.Handler));
340 }
341}
342
343/// clear - Clear out all the function-specific state. This returns this
344/// FunctionLoweringInfo to an empty state, ready to be used for a
345/// different function.
346void FunctionLoweringInfo::clear() {
347 MBBMap.clear();
348 ValueMap.clear();
349 VirtReg2Value.clear();
350 StaticAllocaMap.clear();
351 LiveOutRegInfo.clear();
352 VisitedBBs.clear();
353 ArgDbgValues.clear();
354 DescribedArgs.clear();
355 ByValArgFrameIndexMap.clear();
356 RegFixups.clear();
357 RegsWithFixups.clear();
358 StatepointStackSlots.clear();
359 StatepointRelocationMaps.clear();
360 PreferredExtendType.clear();
361 PreprocessedDVRDeclares.clear();
362}
363
364/// CreateReg - Allocate a single virtual register for the given type.
365Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) {
366 return RegInfo->createVirtualRegister(RegClass: TLI->getRegClassFor(VT, isDivergent));
367}
368
369/// CreateRegs - Allocate the appropriate number of virtual registers of
370/// the correctly promoted or expanded types. Assign these registers
371/// consecutive vreg numbers and return the first assigned number.
372///
373/// In the case that the given value has struct or array type, this function
374/// will assign registers for each member or element.
375///
376Register FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) {
377 SmallVector<EVT, 4> ValueVTs;
378 ComputeValueVTs(TLI: *TLI, DL: MF->getDataLayout(), Ty, ValueVTs);
379
380 Register FirstReg;
381 for (EVT ValueVT : ValueVTs) {
382 MVT RegisterVT = TLI->getRegisterType(Context&: Ty->getContext(), VT: ValueVT);
383
384 unsigned NumRegs = TLI->getNumRegisters(Context&: Ty->getContext(), VT: ValueVT);
385 for (unsigned i = 0; i != NumRegs; ++i) {
386 Register R = CreateReg(VT: RegisterVT, isDivergent);
387 if (!FirstReg) FirstReg = R;
388 }
389 }
390 return FirstReg;
391}
392
393Register FunctionLoweringInfo::CreateRegs(const Value *V) {
394 return CreateRegs(Ty: V->getType(), isDivergent: UA && UA->isDivergentAtDef(V) &&
395 !TLI->requiresUniformRegister(MF&: *MF, V));
396}
397
398Register FunctionLoweringInfo::InitializeRegForValue(const Value *V) {
399 // Tokens live in vregs only when used for convergence control.
400 if (V->getType()->isTokenTy() && !isa<ConvergenceControlInst>(Val: V))
401 return 0;
402 Register &R = ValueMap[V];
403 assert(R == Register() && "Already initialized this value register!");
404 assert(VirtReg2Value.empty());
405 return R = CreateRegs(V);
406}
407
408/// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
409/// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
410/// the register's LiveOutInfo is for a smaller bit width, it is extended to
411/// the larger bit width by zero extension. The bit width must be no smaller
412/// than the LiveOutInfo's existing bit width.
413const FunctionLoweringInfo::LiveOutInfo *
414FunctionLoweringInfo::GetLiveOutRegInfo(Register Reg, unsigned BitWidth) {
415 if (!LiveOutRegInfo.inBounds(N: Reg))
416 return nullptr;
417
418 LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
419 if (!LOI->IsValid)
420 return nullptr;
421
422 if (BitWidth > LOI->Known.getBitWidth()) {
423 LOI->NumSignBits = 1;
424 LOI->Known = LOI->Known.anyext(BitWidth);
425 }
426
427 return LOI;
428}
429
430/// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
431/// register based on the LiveOutInfo of its operands.
432void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
433 Type *Ty = PN->getType();
434 if (!Ty->isIntegerTy())
435 return;
436
437 SmallVector<EVT, 1> ValueVTs;
438 ComputeValueVTs(TLI: *TLI, DL: MF->getDataLayout(), Ty, ValueVTs);
439 assert(ValueVTs.size() == 1 &&
440 "PHIs with non-vector integer types should have a single VT.");
441 EVT IntVT = ValueVTs[0];
442
443 unsigned NumRegisters = TLI->getNumRegisters(Context&: PN->getContext(), VT: IntVT);
444 // FIXME: Support multiple registers for big endian targets.
445 if (NumRegisters != 1 && MF->getDataLayout().isBigEndian())
446 return;
447 IntVT = TLI->getRegisterType(Context&: PN->getContext(), VT: IntVT);
448 unsigned BitWidth = IntVT.getSizeInBits();
449
450 auto It = ValueMap.find(Val: PN);
451 if (It == ValueMap.end())
452 return;
453
454 Register BaseReg = It->second;
455 if (!BaseReg)
456 return;
457 assert(BaseReg.isVirtual() && "Expected a virtual reg");
458
459 for (unsigned RegIdx = 0; RegIdx < NumRegisters; ++RegIdx) {
460 // Split registers are assigned sequentially.
461 Register DestReg = BaseReg.id() + RegIdx;
462 LiveOutRegInfo.grow(N: DestReg);
463 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
464
465 Value *V = PN->getIncomingValue(i: 0);
466 if (isa<UndefValue>(Val: V) || isa<ConstantExpr>(Val: V)) {
467 DestLOI.NumSignBits = 1;
468 DestLOI.Known = KnownBits(BitWidth);
469 continue;
470 }
471
472 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val: V)) {
473 APInt Val;
474 if (TLI->signExtendConstant(C: CI))
475 Val = CI->getValue().sext(width: BitWidth * NumRegisters);
476 else
477 Val = CI->getValue().zext(width: BitWidth * NumRegisters);
478 APInt Extracted = Val.extractBits(numBits: BitWidth, bitPosition: BitWidth * RegIdx);
479 DestLOI.NumSignBits = Extracted.getNumSignBits();
480 DestLOI.Known = KnownBits::makeConstant(C: Extracted);
481 } else {
482 assert(ValueMap.count(V) &&
483 "V should have been placed in ValueMap when its"
484 "CopyToReg node was created.");
485 Register SrcReg = ValueMap[V];
486 if (!SrcReg.isVirtual()) {
487 DestLOI.IsValid = false;
488 continue;
489 }
490 // Split registers are assigned sequentially.
491 SrcReg = SrcReg.id() + RegIdx;
492 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(Reg: SrcReg, BitWidth);
493 if (!SrcLOI) {
494 DestLOI.IsValid = false;
495 continue;
496 }
497 DestLOI = *SrcLOI;
498 }
499
500 assert(DestLOI.Known.Zero.getBitWidth() == BitWidth &&
501 DestLOI.Known.One.getBitWidth() == BitWidth &&
502 "Masks should have the same bit width as the type.");
503
504 for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
505 Value *V = PN->getIncomingValue(i);
506 if (isa<UndefValue>(Val: V) || isa<ConstantExpr>(Val: V)) {
507 DestLOI.NumSignBits = 1;
508 DestLOI.Known = KnownBits(BitWidth);
509 break;
510 }
511
512 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val: V)) {
513 APInt Val;
514 if (TLI->signExtendConstant(C: CI))
515 Val = CI->getValue().sext(width: BitWidth * NumRegisters);
516 else
517 Val = CI->getValue().zext(width: BitWidth * NumRegisters);
518 APInt Extracted = Val.extractBits(numBits: BitWidth, bitPosition: BitWidth * RegIdx);
519 DestLOI.NumSignBits =
520 std::min(a: DestLOI.NumSignBits, b: Extracted.getNumSignBits());
521 DestLOI.Known =
522 DestLOI.Known.intersectWith(RHS: KnownBits::makeConstant(C: Extracted));
523 continue;
524 }
525
526 assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
527 "its CopyToReg node was created.");
528 Register SrcReg = ValueMap[V];
529 if (!SrcReg.isVirtual()) {
530 DestLOI.IsValid = false;
531 break;
532 }
533 // Split registers are assigned sequentially.
534 SrcReg = SrcReg.id() + RegIdx;
535 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(Reg: SrcReg, BitWidth);
536 if (!SrcLOI) {
537 DestLOI.IsValid = false;
538 break;
539 }
540 DestLOI.NumSignBits = std::min(a: DestLOI.NumSignBits, b: SrcLOI->NumSignBits);
541 DestLOI.Known = DestLOI.Known.intersectWith(RHS: SrcLOI->Known);
542 }
543 }
544}
545
546/// setArgumentFrameIndex - Record frame index for the byval
547/// argument. This overrides previous frame index entry for this argument,
548/// if any.
549void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
550 int FI) {
551 ByValArgFrameIndexMap[A] = FI;
552}
553
554/// getArgumentFrameIndex - Get frame index for the byval argument.
555/// If the argument does not have any assigned frame index then 0 is
556/// returned.
557int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
558 auto I = ByValArgFrameIndexMap.find(Val: A);
559 if (I != ByValArgFrameIndexMap.end())
560 return I->second;
561 LLVM_DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
562 return INT_MAX;
563}
564
565Register FunctionLoweringInfo::getCatchPadExceptionPointerVReg(
566 const Value *CPI, const TargetRegisterClass *RC) {
567 MachineRegisterInfo &MRI = MF->getRegInfo();
568 auto I = CatchPadExceptionPointers.insert(KV: {CPI, 0});
569 Register &VReg = I.first->second;
570 if (I.second)
571 VReg = MRI.createVirtualRegister(RegClass: RC);
572 assert(VReg && "null vreg in exception pointer table!");
573 return VReg;
574}
575
576const Value *
577FunctionLoweringInfo::getValueFromVirtualReg(Register Vreg) {
578 if (VirtReg2Value.empty()) {
579 SmallVector<EVT, 4> ValueVTs;
580 for (auto &P : ValueMap) {
581 ValueVTs.clear();
582 ComputeValueVTs(TLI: *TLI, DL: Fn->getDataLayout(),
583 Ty: P.first->getType(), ValueVTs);
584 Register Reg = P.second;
585 for (EVT VT : ValueVTs) {
586 unsigned NumRegisters = TLI->getNumRegisters(Context&: Fn->getContext(), VT);
587 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
588 VirtReg2Value[Reg++] = P.first;
589 }
590 }
591 }
592 return VirtReg2Value.lookup(Val: Vreg);
593}
594