1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the Emit routines for the SelectionDAG class, which creates
10// MachineInstrs based on the decisions of the SelectionDAG instruction
11// selection.
12//
13//===----------------------------------------------------------------------===//
14
15#include "InstrEmitter.h"
16#include "SDNodeDbgValue.h"
17#include "llvm/BinaryFormat/Dwarf.h"
18#include "llvm/CodeGen/ISDOpcodes.h"
19#include "llvm/CodeGen/MachineConstantPool.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/SelectionDAGNodes.h"
24#include "llvm/CodeGen/StackMaps.h"
25#include "llvm/CodeGen/TargetInstrInfo.h"
26#include "llvm/CodeGen/TargetLowering.h"
27#include "llvm/CodeGen/TargetSubtargetInfo.h"
28#include "llvm/IR/DebugInfoMetadata.h"
29#include "llvm/IR/PseudoProbe.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/Target/TargetMachine.h"
32using namespace llvm;
33
34#define DEBUG_TYPE "instr-emitter"
35
36/// MinRCSize - Smallest register class we allow when constraining virtual
37/// registers. If satisfying all register class constraints would require
38/// using a smaller register class, emit a COPY to a new virtual register
39/// instead.
40const unsigned MinRCSize = 4;
41
42/// CountResults - The results of target nodes have register or immediate
43/// operands first, then an optional chain, and optional glue operands (which do
44/// not go into the resulting MachineInstr).
45unsigned InstrEmitter::CountResults(SDNode *Node) {
46 unsigned N = Node->getNumValues();
47 while (N && Node->getValueType(ResNo: N - 1) == MVT::Glue)
48 --N;
49 if (N && Node->getValueType(ResNo: N - 1) == MVT::Other)
50 --N; // Skip over chain result.
51 return N;
52}
53
54/// countOperands - The inputs to target nodes have any actual inputs first,
55/// followed by an optional chain operand, then an optional glue operand.
56/// Compute the number of actual operands that will go into the resulting
57/// MachineInstr.
58///
59/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
60/// the chain and glue. These operands may be implicit on the machine instr.
61static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
62 unsigned &NumImpUses) {
63 unsigned N = Node->getNumOperands();
64 while (N && Node->getOperand(Num: N - 1).getValueType() == MVT::Glue)
65 --N;
66 if (N && Node->getOperand(Num: N - 1).getOpcode() == ISD::DEACTIVATION_SYMBOL)
67 --N; // Ignore deactivation symbol if it exists.
68 if (N && Node->getOperand(Num: N - 1).getValueType() == MVT::Other)
69 --N; // Ignore chain if it exists.
70
71 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
72 NumImpUses = N - NumExpUses;
73 for (unsigned I = N; I > NumExpUses; --I) {
74 if (isa<RegisterMaskSDNode>(Val: Node->getOperand(Num: I - 1)))
75 continue;
76 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Val: Node->getOperand(Num: I - 1)))
77 if (RN->getReg().isPhysical())
78 continue;
79 NumImpUses = N - I;
80 break;
81 }
82
83 return N;
84}
85
86/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
87/// implicit physical register output.
88void InstrEmitter::EmitCopyFromReg(SDValue Op, bool IsClone, Register SrcReg,
89 VRBaseMapType &VRBaseMap) {
90 Register VRBase;
91 if (SrcReg.isVirtual()) {
92 // Just use the input register directly!
93 if (IsClone)
94 VRBaseMap.erase(Val: Op);
95 bool isNew = VRBaseMap.insert(KV: std::make_pair(x&: Op, y&: SrcReg)).second;
96 (void)isNew; // Silence compiler warning.
97 assert(isNew && "Node emitted out of order - early");
98 return;
99 }
100
101 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
102 // the CopyToReg'd destination register instead of creating a new vreg.
103 bool MatchReg = true;
104 const TargetRegisterClass *UseRC = nullptr;
105 MVT VT = Op.getSimpleValueType();
106
107 // Stick to the preferred register classes for legal types.
108 if (TLI->isTypeLegal(VT))
109 UseRC = TLI->getRegClassFor(VT, isDivergent: Op->isDivergent());
110
111 for (SDNode *User : Op->users()) {
112 bool Match = true;
113 if (User->getOpcode() == ISD::CopyToReg && User->getOperand(Num: 2) == Op) {
114 Register DestReg = cast<RegisterSDNode>(Val: User->getOperand(Num: 1))->getReg();
115 if (DestReg.isVirtual()) {
116 VRBase = DestReg;
117 Match = false;
118 } else if (DestReg != SrcReg)
119 Match = false;
120 } else {
121 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
122 if (User->getOperand(Num: i) != Op)
123 continue;
124 if (VT == MVT::Other || VT == MVT::Glue)
125 continue;
126 Match = false;
127 if (User->isMachineOpcode()) {
128 const MCInstrDesc &II = TII->get(Opcode: User->getMachineOpcode());
129 const TargetRegisterClass *RC = nullptr;
130 if (i + II.getNumDefs() < II.getNumOperands()) {
131 RC = TRI->getAllocatableClass(
132 RC: TII->getRegClass(MCID: II, OpNum: i + II.getNumDefs()));
133 }
134 if (!UseRC)
135 UseRC = RC;
136 else if (RC) {
137 const TargetRegisterClass *ComRC =
138 TRI->getCommonSubClass(A: UseRC, B: RC);
139 // If multiple uses expect disjoint register classes, we emit
140 // copies in AddRegisterOperand.
141 if (ComRC)
142 UseRC = ComRC;
143 }
144 }
145 }
146 }
147 MatchReg &= Match;
148 if (VRBase)
149 break;
150 }
151
152 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
153 SrcRC = TRI->getMinimalPhysRegClass(Reg: SrcReg, VT);
154
155 // Figure out the register class to create for the destreg.
156 if (VRBase) {
157 DstRC = MRI->getRegClass(Reg: VRBase);
158 } else if (UseRC) {
159 assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
160 "Incompatible phys register def and uses!");
161 DstRC = UseRC;
162 } else
163 DstRC = SrcRC;
164
165 // If all uses are reading from the src physical register and copying the
166 // register is either impossible or very expensive, then don't create a copy.
167 if (MatchReg && SrcRC->expensiveOrImpossibleToCopy()) {
168 VRBase = SrcReg;
169 } else {
170 // Create the reg, emit the copy.
171 VRBase = MRI->createVirtualRegister(RegClass: DstRC);
172 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Op.getDebugLoc(), MCID: TII->get(Opcode: TargetOpcode::COPY),
173 DestReg: VRBase)
174 .addReg(RegNo: SrcReg);
175 }
176
177 if (IsClone)
178 VRBaseMap.erase(Val: Op);
179 bool isNew = VRBaseMap.insert(KV: std::make_pair(x&: Op, y&: VRBase)).second;
180 (void)isNew; // Silence compiler warning.
181 assert(isNew && "Node emitted out of order - early");
182}
183
184void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
185 MachineInstrBuilder &MIB,
186 const MCInstrDesc &II,
187 bool IsClone, bool IsCloned,
188 VRBaseMapType &VRBaseMap) {
189 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
190 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
191
192 unsigned NumResults = CountResults(Node);
193 bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
194 II.isVariadic() && II.variadicOpsAreDefs();
195 unsigned NumVRegs = HasVRegVariadicDefs ? NumResults : II.getNumDefs();
196 if (Node->getMachineOpcode() == TargetOpcode::STATEPOINT)
197 NumVRegs = NumResults;
198 for (unsigned i = 0; i < NumVRegs; ++i) {
199 // If the specific node value is only used by a CopyToReg and the dest reg
200 // is a vreg in the same register class, use the CopyToReg'd destination
201 // register instead of creating a new vreg.
202 Register VRBase;
203 const TargetRegisterClass *RC =
204 TRI->getAllocatableClass(RC: TII->getRegClass(MCID: II, OpNum: i));
205 // Always let the value type influence the used register class. The
206 // constraints on the instruction may be too lax to represent the value
207 // type correctly. For example, a 64-bit float (X86::FR64) can't live in
208 // the 32-bit float super-class (X86::FR32).
209 if (i < NumResults && TLI->isTypeLegal(VT: Node->getSimpleValueType(ResNo: i))) {
210 const TargetRegisterClass *VTRC = TLI->getRegClassFor(
211 VT: Node->getSimpleValueType(ResNo: i),
212 isDivergent: (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));
213 if (RC)
214 VTRC = TRI->getCommonSubClass(A: RC, B: VTRC);
215 if (VTRC)
216 RC = VTRC;
217 }
218
219 if (!II.operands().empty() && II.operands()[i].isOptionalDef()) {
220 // Optional def must be a physical register.
221 VRBase = cast<RegisterSDNode>(Val: Node->getOperand(Num: i-NumResults))->getReg();
222 assert(VRBase.isPhysical());
223 MIB.addReg(RegNo: VRBase, Flags: RegState::Define);
224 }
225
226 if (!VRBase && !IsClone && !IsCloned)
227 for (SDNode *User : Node->users()) {
228 if (User->getOpcode() == ISD::CopyToReg &&
229 User->getOperand(Num: 2).getNode() == Node &&
230 User->getOperand(Num: 2).getResNo() == i) {
231 Register Reg = cast<RegisterSDNode>(Val: User->getOperand(Num: 1))->getReg();
232 if (Reg.isVirtual()) {
233 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
234 if (RegRC == RC) {
235 VRBase = Reg;
236 MIB.addReg(RegNo: VRBase, Flags: RegState::Define);
237 break;
238 }
239 }
240 }
241 }
242
243 // Create the result registers for this node and add the result regs to
244 // the machine instruction.
245 if (!VRBase) {
246 assert(RC && "Isn't a register operand!");
247 VRBase = MRI->createVirtualRegister(RegClass: RC);
248 MIB.addReg(RegNo: VRBase, Flags: RegState::Define);
249 }
250
251 // If this def corresponds to a result of the SDNode insert the VRBase into
252 // the lookup map.
253 if (i < NumResults) {
254 SDValue Op(Node, i);
255 if (IsClone)
256 VRBaseMap.erase(Val: Op);
257 bool isNew = VRBaseMap.insert(KV: std::make_pair(x&: Op, y&: VRBase)).second;
258 (void)isNew; // Silence compiler warning.
259 assert(isNew && "Node emitted out of order - early");
260 }
261 }
262}
263
264/// getVR - Return the virtual register corresponding to the specified result
265/// of the specified node.
266Register InstrEmitter::getVR(SDValue Op, VRBaseMapType &VRBaseMap) {
267 if (Op.isMachineOpcode() &&
268 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
269 // Add an IMPLICIT_DEF instruction before every use.
270 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
271 // does not include operand register class info.
272 const TargetRegisterClass *RC = TLI->getRegClassFor(
273 VT: Op.getSimpleValueType(), isDivergent: Op.getNode()->isDivergent());
274 Register VReg = MRI->createVirtualRegister(RegClass: RC);
275 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Op.getDebugLoc(),
276 MCID: TII->get(Opcode: TargetOpcode::IMPLICIT_DEF), DestReg: VReg);
277 return VReg;
278 }
279
280 VRBaseMapType::iterator I = VRBaseMap.find(Val: Op);
281 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
282 return I->second;
283}
284
285static bool isConvergenceCtrlMachineOp(SDValue Op) {
286 if (Op->isMachineOpcode()) {
287 switch (Op->getMachineOpcode()) {
288 case TargetOpcode::CONVERGENCECTRL_ANCHOR:
289 case TargetOpcode::CONVERGENCECTRL_ENTRY:
290 case TargetOpcode::CONVERGENCECTRL_LOOP:
291 case TargetOpcode::CONVERGENCECTRL_GLUE:
292 return true;
293 }
294 return false;
295 }
296
297 // We can reach here when CopyFromReg is encountered. But rather than making a
298 // special case for that, we just make sure we don't reach here in some
299 // surprising way.
300 switch (Op->getOpcode()) {
301 case ISD::CONVERGENCECTRL_ANCHOR:
302 case ISD::CONVERGENCECTRL_ENTRY:
303 case ISD::CONVERGENCECTRL_LOOP:
304 case ISD::CONVERGENCECTRL_GLUE:
305 llvm_unreachable("Convergence control should have been selected by now.");
306 }
307 return false;
308}
309
310/// AddRegisterOperand - Add the specified register as an operand to the
311/// specified machine instr. Insert register copies if the register is
312/// not in the required register class.
313void
314InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
315 SDValue Op,
316 unsigned IIOpNum,
317 const MCInstrDesc *II,
318 VRBaseMapType &VRBaseMap,
319 bool IsDebug, bool IsClone, bool IsCloned) {
320 assert(Op.getValueType() != MVT::Other &&
321 Op.getValueType() != MVT::Glue &&
322 "Chain and glue operands should occur at end of operand list!");
323 // Get/emit the operand.
324 Register VReg = getVR(Op, VRBaseMap);
325
326 const MCInstrDesc &MCID = MIB->getDesc();
327 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
328 MCID.operands()[IIOpNum].isOptionalDef();
329
330 // If the instruction requires a register in a different class, create
331 // a new virtual register and copy the value into it, but first attempt to
332 // shrink VReg's register class within reason. For example, if VReg == GR32
333 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
334 if (II) {
335 const TargetRegisterClass *OpRC = nullptr;
336 if (IIOpNum < II->getNumOperands())
337 OpRC = TII->getRegClass(MCID: *II, OpNum: IIOpNum);
338
339 if (OpRC) {
340 unsigned MinNumRegs = MinRCSize;
341 // Don't apply any RC size limit for IMPLICIT_DEF. Each use has a unique
342 // virtual register.
343 if (Op.isMachineOpcode() &&
344 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)
345 MinNumRegs = 0;
346
347 const TargetRegisterClass *ConstrainedRC
348 = MRI->constrainRegClass(Reg: VReg, RC: OpRC, MinNumRegs);
349 if (!ConstrainedRC) {
350 OpRC = TRI->getAllocatableClass(RC: OpRC);
351 assert(OpRC && "Constraints cannot be fulfilled for allocation");
352 Register NewVReg = MRI->createVirtualRegister(RegClass: OpRC);
353 BuildMI(BB&: *MBB, I: InsertPos, MIMD: MIB->getDebugLoc(),
354 MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: NewVReg)
355 .addReg(RegNo: VReg);
356 VReg = NewVReg;
357 } else {
358 assert(ConstrainedRC->isAllocatable() &&
359 "Constraining an allocatable VReg produced an unallocatable class?");
360 }
361 }
362 }
363
364 // If this value has only one use, that use is a kill. This is a
365 // conservative approximation. InstrEmitter does trivial coalescing
366 // with CopyFromReg nodes, so don't emit kill flags for them.
367 // Avoid kill flags on Schedule cloned nodes, since there will be
368 // multiple uses.
369 // Tied operands are never killed, so we need to check that. And that
370 // means we need to determine the index of the operand.
371 // Don't kill convergence control tokens. Initially they are only used in glue
372 // nodes, and the InstrEmitter later adds implicit uses on the users of the
373 // glue node. This can sometimes make it seem like there is only one use,
374 // which is the glue node itself.
375 bool isKill = Op.hasOneUse() && !isConvergenceCtrlMachineOp(Op) &&
376 Op.getNode()->getOpcode() != ISD::CopyFromReg && !IsDebug &&
377 !(IsClone || IsCloned);
378 if (isKill) {
379 unsigned Idx = MIB->getNumOperands();
380 while (Idx > 0 &&
381 MIB->getOperand(i: Idx-1).isReg() &&
382 MIB->getOperand(i: Idx-1).isImplicit())
383 --Idx;
384 bool isTied = MCID.getOperandConstraint(OpNum: Idx, Constraint: MCOI::TIED_TO) != -1;
385 if (isTied)
386 isKill = false;
387 }
388
389 MIB.addReg(RegNo: VReg, Flags: getDefRegState(B: isOptDef) | getKillRegState(B: isKill) |
390 getDebugRegState(B: IsDebug));
391}
392
393/// AddOperand - Add the specified operand to the specified machine instr. II
394/// specifies the instruction information for the node, and IIOpNum is the
395/// operand number (in the II) that we are adding.
396void InstrEmitter::AddOperand(MachineInstrBuilder &MIB, SDValue Op,
397 unsigned IIOpNum, const MCInstrDesc *II,
398 VRBaseMapType &VRBaseMap, bool IsDebug,
399 bool IsClone, bool IsCloned) {
400 if (Op.isMachineOpcode()) {
401 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
402 IsDebug, IsClone, IsCloned);
403 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op)) {
404 if (C->getAPIntValue().getSignificantBits() <= 64) {
405 MIB.addImm(Val: C->getSExtValue());
406 } else {
407 MIB.addCImm(
408 Val: ConstantInt::get(Context&: MF->getFunction().getContext(), V: C->getAPIntValue()));
409 }
410 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Val&: Op)) {
411 MIB.addFPImm(Val: F->getConstantFPValue());
412 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Val&: Op)) {
413 Register VReg = R->getReg();
414 MVT OpVT = Op.getSimpleValueType();
415 const TargetRegisterClass *IIRC =
416 II ? TRI->getAllocatableClass(RC: TII->getRegClass(MCID: *II, OpNum: IIOpNum)) : nullptr;
417 const TargetRegisterClass *OpRC =
418 TLI->isTypeLegal(VT: OpVT)
419 ? TLI->getRegClassFor(VT: OpVT,
420 isDivergent: Op.getNode()->isDivergent() ||
421 (IIRC && TRI->isDivergentRegClass(RC: IIRC)))
422 : nullptr;
423
424 if (OpRC && IIRC && OpRC != IIRC && VReg.isVirtual()) {
425 Register NewVReg = MRI->createVirtualRegister(RegClass: IIRC);
426 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Op.getNode()->getDebugLoc(),
427 MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: NewVReg).addReg(RegNo: VReg);
428 VReg = NewVReg;
429 }
430 // Turn additional physreg operands into implicit uses on non-variadic
431 // instructions. This is used by call and return instructions passing
432 // arguments in registers.
433 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
434 MIB.addReg(RegNo: VReg, Flags: getImplRegState(B: Imp));
435 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Val&: Op)) {
436 MIB.addRegMask(Mask: RM->getRegMask());
437 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Val&: Op)) {
438 MIB.addGlobalAddress(GV: TGA->getGlobal(), Offset: TGA->getOffset(),
439 TargetFlags: TGA->getTargetFlags());
440 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Val&: Op)) {
441 MIB.addMBB(MBB: BBNode->getBasicBlock());
442 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Val&: Op)) {
443 MIB.addFrameIndex(Idx: FI->getIndex());
444 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Val&: Op)) {
445 MIB.addJumpTableIndex(Idx: JT->getIndex(), TargetFlags: JT->getTargetFlags());
446 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Val&: Op)) {
447 int Offset = CP->getOffset();
448 Align Alignment = CP->getAlign();
449
450 unsigned Idx;
451 MachineConstantPool *MCP = MF->getConstantPool();
452 if (CP->isMachineConstantPoolEntry())
453 Idx = MCP->getConstantPoolIndex(V: CP->getMachineCPVal(), Alignment);
454 else
455 Idx = MCP->getConstantPoolIndex(C: CP->getConstVal(), Alignment);
456 MIB.addConstantPoolIndex(Idx, Offset, TargetFlags: CP->getTargetFlags());
457 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Val&: Op)) {
458 MIB.addExternalSymbol(FnName: ES->getSymbol(), TargetFlags: ES->getTargetFlags());
459 } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Val&: Op)) {
460 MIB.addSym(Sym: SymNode->getMCSymbol());
461 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Val&: Op)) {
462 MIB.addBlockAddress(BA: BA->getBlockAddress(),
463 Offset: BA->getOffset(),
464 TargetFlags: BA->getTargetFlags());
465 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Val&: Op)) {
466 MIB.addTargetIndex(Idx: TI->getIndex(), Offset: TI->getOffset(), TargetFlags: TI->getTargetFlags());
467 } else {
468 assert(Op.getValueType() != MVT::Other &&
469 Op.getValueType() != MVT::Glue &&
470 "Chain and glue operands should occur at end of operand list!");
471 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
472 IsDebug, IsClone, IsCloned);
473 }
474}
475
476Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
477 MVT VT, bool isDivergent, const DebugLoc &DL) {
478 const TargetRegisterClass *VRC = MRI->getRegClass(Reg: VReg);
479 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(RC: VRC, Idx: SubIdx);
480
481 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
482 // within reason.
483 if (RC && RC != VRC)
484 RC = MRI->constrainRegClass(Reg: VReg, RC, MinNumRegs: MinRCSize);
485
486 // VReg has been adjusted. It can be used with SubIdx operands now.
487 if (RC)
488 return VReg;
489
490 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
491 // register instead.
492 RC = TRI->getSubClassWithSubReg(RC: TLI->getRegClassFor(VT, isDivergent), Idx: SubIdx);
493 assert(RC && "No legal register class for VT supports that SubIdx");
494 Register NewReg = MRI->createVirtualRegister(RegClass: RC);
495 BuildMI(BB&: *MBB, I: InsertPos, MIMD: DL, MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: NewReg)
496 .addReg(RegNo: VReg);
497 return NewReg;
498}
499
500/// EmitSubregNode - Generate machine code for subreg nodes.
501///
502void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap,
503 bool IsClone, bool IsCloned) {
504 Register VRBase;
505 unsigned Opc = Node->getMachineOpcode();
506
507 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
508 // the CopyToReg'd destination register instead of creating a new vreg.
509 for (SDNode *User : Node->users()) {
510 if (User->getOpcode() == ISD::CopyToReg &&
511 User->getOperand(Num: 2).getNode() == Node) {
512 Register DestReg = cast<RegisterSDNode>(Val: User->getOperand(Num: 1))->getReg();
513 if (DestReg.isVirtual()) {
514 VRBase = DestReg;
515 break;
516 }
517 }
518 }
519
520 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
521 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
522 // constraints on the %dst register, COPY can target all legal register
523 // classes.
524 unsigned SubIdx = Node->getConstantOperandVal(Num: 1);
525 const TargetRegisterClass *TRC =
526 TLI->getRegClassFor(VT: Node->getSimpleValueType(ResNo: 0), isDivergent: Node->isDivergent());
527
528 Register Reg;
529 MachineInstr *DefMI;
530 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Val: Node->getOperand(Num: 0));
531 if (R && R->getReg().isPhysical()) {
532 Reg = R->getReg();
533 DefMI = nullptr;
534 } else {
535 Reg = R ? R->getReg() : getVR(Op: Node->getOperand(Num: 0), VRBaseMap);
536 DefMI = MRI->getVRegDef(Reg);
537 }
538
539 Register SrcReg, DstReg;
540 unsigned DefSubIdx;
541 if (DefMI &&
542 TII->isCoalescableExtInstr(MI: *DefMI, SrcReg, DstReg, SubIdx&: DefSubIdx) &&
543 SubIdx == DefSubIdx &&
544 TRC == MRI->getRegClass(Reg: SrcReg)) {
545 // Optimize these:
546 // r1025 = s/zext r1024, 4
547 // r1026 = extract_subreg r1025, 4
548 // to a copy
549 // r1026 = copy r1024
550 VRBase = MRI->createVirtualRegister(RegClass: TRC);
551 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Node->getDebugLoc(),
552 MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: VRBase).addReg(RegNo: SrcReg);
553 MRI->clearKillFlags(Reg: SrcReg);
554 } else {
555 // Reg may not support a SubIdx sub-register, and we may need to
556 // constrain its register class or issue a COPY to a compatible register
557 // class.
558 if (Reg.isVirtual())
559 Reg = ConstrainForSubReg(VReg: Reg, SubIdx,
560 VT: Node->getOperand(Num: 0).getSimpleValueType(),
561 isDivergent: Node->isDivergent(), DL: Node->getDebugLoc());
562 // Create the destreg if it is missing.
563 if (!VRBase)
564 VRBase = MRI->createVirtualRegister(RegClass: TRC);
565
566 // Create the extract_subreg machine instruction.
567 MachineInstrBuilder CopyMI =
568 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Node->getDebugLoc(),
569 MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: VRBase);
570 if (Reg.isVirtual())
571 CopyMI.addReg(RegNo: Reg, Flags: {}, SubReg: SubIdx);
572 else
573 CopyMI.addReg(RegNo: TRI->getSubReg(Reg, Idx: SubIdx));
574 }
575 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
576 Opc == TargetOpcode::SUBREG_TO_REG) {
577 SDValue Reg;
578 SDValue SubReg;
579 unsigned SubIdx;
580 if (Opc == TargetOpcode::INSERT_SUBREG) {
581 Reg = Node->getOperand(Num: 0);
582 SubReg = Node->getOperand(Num: 1);
583 SubIdx = Node->getOperand(Num: 2)->getAsZExtVal();
584 } else {
585 SubReg = Node->getOperand(Num: 0);
586 SubIdx = Node->getOperand(Num: 1)->getAsZExtVal();
587 }
588
589 // Figure out the register class to create for the destreg. It should be
590 // the largest legal register class supporting SubIdx sub-registers.
591 // RegisterCoalescer will constrain it further if it decides to eliminate
592 // the INSERT_SUBREG instruction.
593 //
594 // %dst = INSERT_SUBREG %src, %sub, SubIdx
595 //
596 // is lowered by TwoAddressInstructionPass to:
597 //
598 // %dst = COPY %src
599 // %dst:SubIdx = COPY %sub
600 //
601 // There is no constraint on the %src register class.
602 //
603 const TargetRegisterClass *SRC =
604 TLI->getRegClassFor(VT: Node->getSimpleValueType(ResNo: 0), isDivergent: Node->isDivergent());
605 SRC = TRI->getSubClassWithSubReg(RC: SRC, Idx: SubIdx);
606 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
607
608 if (VRBase == 0 || !SRC->hasSubClassEq(RC: MRI->getRegClass(Reg: VRBase)))
609 VRBase = MRI->createVirtualRegister(RegClass: SRC);
610
611 // Create the insert_subreg or subreg_to_reg machine instruction.
612 MachineInstrBuilder MIB =
613 BuildMI(MF&: *MF, MIMD: Node->getDebugLoc(), MCID: TII->get(Opcode: Opc), DestReg: VRBase);
614
615 // If creating an insert_subreg, then the first input operand
616 // is a register
617 if (Reg) {
618 AddOperand(MIB, Op: Reg, IIOpNum: 0, II: nullptr, VRBaseMap, /*IsDebug=*/false, IsClone,
619 IsCloned);
620 }
621 // Add the subregister being inserted
622 AddOperand(MIB, Op: SubReg, IIOpNum: 0, II: nullptr, VRBaseMap, /*IsDebug=*/false, IsClone,
623 IsCloned);
624 MIB.addImm(Val: SubIdx);
625 MBB->insert(I: InsertPos, MI: MIB);
626 } else
627 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
628
629 SDValue Op(Node, 0);
630 bool isNew = VRBaseMap.insert(KV: std::make_pair(x&: Op, y&: VRBase)).second;
631 (void)isNew; // Silence compiler warning.
632 assert(isNew && "Node emitted out of order - early");
633}
634
635/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
636/// COPY_TO_REGCLASS is just a normal copy, except that the destination
637/// register is constrained to be in a particular register class.
638///
639void
640InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
641 VRBaseMapType &VRBaseMap) {
642 // Create the new VReg in the destination class and emit a copy.
643 unsigned DstRCIdx = Node->getConstantOperandVal(Num: 1);
644 const TargetRegisterClass *DstRC =
645 TRI->getAllocatableClass(RC: TRI->getRegClass(i: DstRCIdx));
646 Register NewVReg = MRI->createVirtualRegister(RegClass: DstRC);
647 const MCInstrDesc &II = TII->get(Opcode: TargetOpcode::COPY);
648 MachineInstrBuilder MIB = BuildMI(MF&: *MF, MIMD: Node->getDebugLoc(), MCID: II, DestReg: NewVReg);
649 AddOperand(MIB, Op: Node->getOperand(Num: 0), IIOpNum: 1, II: &II, VRBaseMap, /*IsDebug=*/false,
650 /*IsClone=*/false, /*IsCloned*/ false);
651
652 MBB->insert(I: InsertPos, MI: MIB);
653 SDValue Op(Node, 0);
654 bool isNew = VRBaseMap.insert(KV: std::make_pair(x&: Op, y&: NewVReg)).second;
655 (void)isNew; // Silence compiler warning.
656 assert(isNew && "Node emitted out of order - early");
657}
658
659/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
660///
661void InstrEmitter::EmitRegSequence(SDNode *Node, VRBaseMapType &VRBaseMap,
662 bool IsClone, bool IsCloned) {
663 unsigned DstRCIdx = Node->getConstantOperandVal(Num: 0);
664 const TargetRegisterClass *RC = TRI->getRegClass(i: DstRCIdx);
665 Register NewVReg = MRI->createVirtualRegister(RegClass: TRI->getAllocatableClass(RC));
666 const MCInstrDesc &II = TII->get(Opcode: TargetOpcode::REG_SEQUENCE);
667 MachineInstrBuilder MIB = BuildMI(MF&: *MF, MIMD: Node->getDebugLoc(), MCID: II, DestReg: NewVReg);
668 unsigned NumOps = Node->getNumOperands();
669 // If the input pattern has a chain, then the root of the corresponding
670 // output pattern will get a chain as well. This can happen to be a
671 // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
672 if (NumOps && Node->getOperand(Num: NumOps-1).getValueType() == MVT::Other)
673 --NumOps; // Ignore chain if it exists.
674
675 assert((NumOps & 1) == 1 &&
676 "REG_SEQUENCE must have an odd number of operands!");
677 for (unsigned i = 1; i != NumOps; ++i) {
678 SDValue Op = Node->getOperand(Num: i);
679 if ((i & 1) == 0) {
680 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Val: Node->getOperand(Num: i-1));
681 // Skip physical registers as they don't have a vreg to get and we'll
682 // insert copies for them in TwoAddressInstructionPass anyway.
683 if (!R || !R->getReg().isPhysical()) {
684 unsigned SubIdx = Op->getAsZExtVal();
685 Register SubReg = getVR(Op: Node->getOperand(Num: i - 1), VRBaseMap);
686 const TargetRegisterClass *TRC = MRI->getRegClass(Reg: SubReg);
687 const TargetRegisterClass *SRC =
688 TRI->getMatchingSuperRegClass(A: RC, B: TRC, Idx: SubIdx);
689 if (SRC && SRC != RC) {
690 MRI->setRegClass(Reg: NewVReg, RC: SRC);
691 RC = SRC;
692 }
693 }
694 }
695 AddOperand(MIB, Op, IIOpNum: i+1, II: &II, VRBaseMap, /*IsDebug=*/false,
696 IsClone, IsCloned);
697 }
698
699 MBB->insert(I: InsertPos, MI: MIB);
700 SDValue Op(Node, 0);
701 bool isNew = VRBaseMap.insert(KV: std::make_pair(x&: Op, y&: NewVReg)).second;
702 (void)isNew; // Silence compiler warning.
703 assert(isNew && "Node emitted out of order - early");
704}
705
706/// EmitDbgValue - Generate machine instruction for a dbg_value node.
707///
708MachineInstr *
709InstrEmitter::EmitDbgValue(SDDbgValue *SD,
710 VRBaseMapType &VRBaseMap) {
711 DebugLoc DL = SD->getDebugLoc();
712 assert(cast<DILocalVariable>(SD->getVariable())
713 ->isValidLocationForIntrinsic(DL) &&
714 "Expected inlined-at fields to agree");
715
716 SD->setIsEmitted();
717
718 assert(!SD->getLocationOps().empty() &&
719 "dbg_value with no location operands?");
720
721 if (SD->isInvalidated())
722 return EmitDbgNoLocation(SD);
723
724 // Attempt to produce a DBG_INSTR_REF if we've been asked to.
725 if (EmitDebugInstrRefs)
726 if (auto *InstrRef = EmitDbgInstrRef(SD, VRBaseMap))
727 return InstrRef;
728
729 // Emit variadic dbg_value nodes as DBG_VALUE_LIST if they have not been
730 // emitted as instruction references.
731 if (SD->isVariadic())
732 return EmitDbgValueList(SD, VRBaseMap);
733
734 // Emit single-location dbg_value nodes as DBG_VALUE if they have not been
735 // emitted as instruction references.
736 return EmitDbgValueFromSingleOp(SD, VRBaseMap);
737}
738
739MachineOperand GetMOForConstDbgOp(const SDDbgOperand &Op) {
740 const Value *V = Op.getConst();
741 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val: V)) {
742 if (CI->getBitWidth() > 64)
743 return MachineOperand::CreateCImm(CI);
744 if (CI->getBitWidth() == 1)
745 return MachineOperand::CreateImm(Val: CI->getZExtValue());
746 return MachineOperand::CreateImm(Val: CI->getSExtValue());
747 }
748 if (const ConstantFP *CF = dyn_cast<ConstantFP>(Val: V))
749 return MachineOperand::CreateFPImm(CFP: CF);
750 // Note: This assumes that all nullptr constants are zero-valued.
751 if (isa<ConstantPointerNull>(Val: V))
752 return MachineOperand::CreateImm(Val: 0);
753 // Undef or unhandled value type, so return an undef operand.
754 return MachineOperand::CreateReg(
755 /* Reg */ 0U, /* isDef */ false, /* isImp */ false,
756 /* isKill */ false, /* isDead */ false,
757 /* isUndef */ false, /* isEarlyClobber */ false,
758 /* SubReg */ 0, /* isDebug */ true);
759}
760
761void InstrEmitter::AddDbgValueLocationOps(
762 MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc,
763 ArrayRef<SDDbgOperand> LocationOps,
764 VRBaseMapType &VRBaseMap) {
765 for (const SDDbgOperand &Op : LocationOps) {
766 switch (Op.getKind()) {
767 case SDDbgOperand::FRAMEIX:
768 MIB.addFrameIndex(Idx: Op.getFrameIx());
769 break;
770 case SDDbgOperand::VREG:
771 MIB.addReg(RegNo: Op.getVReg());
772 break;
773 case SDDbgOperand::SDNODE: {
774 SDValue V = SDValue(Op.getSDNode(), Op.getResNo());
775 // It's possible we replaced this SDNode with other(s) and therefore
776 // didn't generate code for it. It's better to catch these cases where
777 // they happen and transfer the debug info, but trying to guarantee that
778 // in all cases would be very fragile; this is a safeguard for any
779 // that were missed.
780 if (VRBaseMap.count(Val: V) == 0)
781 MIB.addReg(RegNo: 0U); // undef
782 else
783 AddOperand(MIB, Op: V, IIOpNum: (*MIB).getNumOperands(), II: &DbgValDesc, VRBaseMap,
784 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
785 } break;
786 case SDDbgOperand::CONST:
787 MIB.add(MO: GetMOForConstDbgOp(Op));
788 break;
789 }
790 }
791}
792
793MachineInstr *
794InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
795 VRBaseMapType &VRBaseMap) {
796 MDNode *Var = SD->getVariable();
797 const DIExpression *Expr = SD->getExpression();
798 DebugLoc DL = SD->getDebugLoc();
799 const MCInstrDesc &RefII = TII->get(Opcode: TargetOpcode::DBG_INSTR_REF);
800
801 // Returns true if the given operand is not a legal debug operand for a
802 // DBG_INSTR_REF.
803 auto IsInvalidOp = [](SDDbgOperand DbgOp) {
804 return DbgOp.getKind() == SDDbgOperand::FRAMEIX;
805 };
806 // Returns true if the given operand is not itself an instruction reference
807 // but is a legal debug operand for a DBG_INSTR_REF.
808 auto IsNonInstrRefOp = [](SDDbgOperand DbgOp) {
809 return DbgOp.getKind() == SDDbgOperand::CONST;
810 };
811
812 // If this variable location does not depend on any instructions or contains
813 // any stack locations, produce it as a standard debug value instead.
814 if (any_of(Range: SD->getLocationOps(), P: IsInvalidOp) ||
815 all_of(Range: SD->getLocationOps(), P: IsNonInstrRefOp)) {
816 if (SD->isVariadic())
817 return EmitDbgValueList(SD, VRBaseMap);
818 return EmitDbgValueFromSingleOp(SD, VRBaseMap);
819 }
820
821 // Immediately fold any indirectness from the LLVM-IR intrinsic into the
822 // expression:
823 if (SD->isIndirect())
824 Expr = DIExpression::append(Expr, Ops: dwarf::DW_OP_deref);
825 // If this is not already a variadic expression, it must be modified to become
826 // one.
827 if (!SD->isVariadic())
828 Expr = DIExpression::convertToVariadicExpression(Expr);
829
830 SmallVector<MachineOperand> MOs;
831
832 // It may not be immediately possible to identify the MachineInstr that
833 // defines a VReg, it can depend for example on the order blocks are
834 // emitted in. When this happens, or when further analysis is needed later,
835 // produce an instruction like this:
836 //
837 // DBG_INSTR_REF !123, !456, %0:gr64
838 //
839 // i.e., point the instruction at the vreg, and patch it up later in
840 // MachineFunction::finalizeDebugInstrRefs.
841 auto AddVRegOp = [&](Register VReg) {
842 MOs.push_back(Elt: MachineOperand::CreateReg(
843 /* Reg */ VReg, /* isDef */ false, /* isImp */ false,
844 /* isKill */ false, /* isDead */ false,
845 /* isUndef */ false, /* isEarlyClobber */ false,
846 /* SubReg */ 0, /* isDebug */ true));
847 };
848 unsigned OpCount = SD->getLocationOps().size();
849 for (unsigned OpIdx = 0; OpIdx < OpCount; ++OpIdx) {
850 SDDbgOperand DbgOperand = SD->getLocationOps()[OpIdx];
851
852 // Try to find both the defined register and the instruction defining it.
853 MachineInstr *DefMI = nullptr;
854 Register VReg;
855
856 if (DbgOperand.getKind() == SDDbgOperand::VREG) {
857 VReg = DbgOperand.getVReg();
858
859 // No definition means that block hasn't been emitted yet. Leave a vreg
860 // reference to be fixed later.
861 if (!MRI->hasOneDef(RegNo: VReg)) {
862 AddVRegOp(VReg);
863 continue;
864 }
865
866 DefMI = &*MRI->def_instr_begin(RegNo: VReg);
867 } else if (DbgOperand.getKind() == SDDbgOperand::SDNODE) {
868 // Look up the corresponding VReg for the given SDNode, if any.
869 SDNode *Node = DbgOperand.getSDNode();
870 SDValue Op = SDValue(Node, DbgOperand.getResNo());
871 VRBaseMapType::iterator I = VRBaseMap.find(Val: Op);
872 // No VReg -> produce a DBG_VALUE $noreg instead.
873 if (I == VRBaseMap.end())
874 break;
875
876 // Try to pick out a defining instruction at this point.
877 VReg = getVR(Op, VRBaseMap);
878
879 // Again, if there's no instruction defining the VReg right now, fix it up
880 // later.
881 if (!MRI->hasOneDef(RegNo: VReg)) {
882 AddVRegOp(VReg);
883 continue;
884 }
885
886 DefMI = &*MRI->def_instr_begin(RegNo: VReg);
887 } else {
888 assert(DbgOperand.getKind() == SDDbgOperand::CONST);
889 MOs.push_back(Elt: GetMOForConstDbgOp(Op: DbgOperand));
890 continue;
891 }
892
893 // Avoid copy like instructions: they don't define values, only move them.
894 // Leave a virtual-register reference until it can be fixed up later, to
895 // find the underlying value definition.
896 if (DefMI->isCopyLike() || TII->isCopyInstr(MI: *DefMI)) {
897 AddVRegOp(VReg);
898 continue;
899 }
900
901 // Find the operand number which defines the specified VReg.
902 unsigned OperandIdx = 0;
903 for (const auto &MO : DefMI->operands()) {
904 if (MO.isReg() && MO.isDef() && MO.getReg() == VReg)
905 break;
906 ++OperandIdx;
907 }
908 assert(OperandIdx < DefMI->getNumOperands());
909
910 // Make the DBG_INSTR_REF refer to that instruction, and that operand.
911 unsigned InstrNum = DefMI->getDebugInstrNum();
912 MOs.push_back(Elt: MachineOperand::CreateDbgInstrRef(InstrIdx: InstrNum, OpIdx: OperandIdx));
913 }
914
915 // If we haven't created a valid MachineOperand for every DbgOp, abort and
916 // produce an undef DBG_VALUE.
917 if (MOs.size() != OpCount)
918 return EmitDbgNoLocation(SD);
919
920 return BuildMI(MF&: *MF, DL, MCID: RefII, IsIndirect: false, MOs, Variable: Var, Expr);
921}
922
923MachineInstr *InstrEmitter::EmitDbgNoLocation(SDDbgValue *SD) {
924 // An invalidated SDNode must generate an undef DBG_VALUE: although the
925 // original value is no longer computed, earlier DBG_VALUEs live ranges
926 // must not leak into later code.
927 DIVariable *Var = SD->getVariable();
928 const DIExpression *Expr =
929 DIExpression::convertToUndefExpression(Expr: SD->getExpression());
930 DebugLoc DL = SD->getDebugLoc();
931 const MCInstrDesc &Desc = TII->get(Opcode: TargetOpcode::DBG_VALUE);
932 return BuildMI(MF&: *MF, DL, MCID: Desc, IsIndirect: false, Reg: 0U, Variable: Var, Expr);
933}
934
935MachineInstr *
936InstrEmitter::EmitDbgValueList(SDDbgValue *SD,
937 VRBaseMapType &VRBaseMap) {
938 MDNode *Var = SD->getVariable();
939 DIExpression *Expr = SD->getExpression();
940 DebugLoc DL = SD->getDebugLoc();
941 // DBG_VALUE_LIST := "DBG_VALUE_LIST" var, expression, loc (, loc)*
942 const MCInstrDesc &DbgValDesc = TII->get(Opcode: TargetOpcode::DBG_VALUE_LIST);
943 // Build the DBG_VALUE_LIST instruction base.
944 auto MIB = BuildMI(MF&: *MF, MIMD: DL, MCID: DbgValDesc);
945 MIB.addMetadata(MD: Var);
946 MIB.addMetadata(MD: Expr);
947 AddDbgValueLocationOps(MIB, DbgValDesc, LocationOps: SD->getLocationOps(), VRBaseMap);
948 return &*MIB;
949}
950
951MachineInstr *
952InstrEmitter::EmitDbgValueFromSingleOp(SDDbgValue *SD,
953 VRBaseMapType &VRBaseMap) {
954 MDNode *Var = SD->getVariable();
955 DIExpression *Expr = SD->getExpression();
956 DebugLoc DL = SD->getDebugLoc();
957 const MCInstrDesc &II = TII->get(Opcode: TargetOpcode::DBG_VALUE);
958
959 assert(SD->getLocationOps().size() == 1 &&
960 "Non variadic dbg_value should have only one location op");
961
962 // See about constant-folding the expression.
963 // Copy the location operand in case we replace it.
964 SmallVector<SDDbgOperand, 1> LocationOps(1, SD->getLocationOps()[0]);
965 if (Expr && LocationOps[0].getKind() == SDDbgOperand::CONST) {
966 const Value *V = LocationOps[0].getConst();
967 if (auto *C = dyn_cast<ConstantInt>(Val: V)) {
968 std::tie(args&: Expr, args&: C) = Expr->constantFold(CI: C);
969 LocationOps[0] = SDDbgOperand::fromConst(Const: C);
970 }
971 }
972
973 // Emit non-variadic dbg_value nodes as DBG_VALUE.
974 // DBG_VALUE := "DBG_VALUE" loc, isIndirect, var, expr
975 auto MIB = BuildMI(MF&: *MF, MIMD: DL, MCID: II);
976 AddDbgValueLocationOps(MIB, DbgValDesc: II, LocationOps, VRBaseMap);
977
978 if (SD->isIndirect())
979 MIB.addImm(Val: 0U);
980 else
981 MIB.addReg(RegNo: 0U);
982
983 return MIB.addMetadata(MD: Var).addMetadata(MD: Expr);
984}
985
986MachineInstr *
987InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
988 MDNode *Label = SD->getLabel();
989 DebugLoc DL = SD->getDebugLoc();
990 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
991 "Expected inlined-at fields to agree");
992
993 const MCInstrDesc &II = TII->get(Opcode: TargetOpcode::DBG_LABEL);
994 MachineInstrBuilder MIB = BuildMI(MF&: *MF, MIMD: DL, MCID: II);
995 MIB.addMetadata(MD: Label);
996
997 return &*MIB;
998}
999
1000/// EmitMachineNode - Generate machine code for a target-specific node and
1001/// needed dependencies.
1002///
1003void InstrEmitter::
1004EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
1005 VRBaseMapType &VRBaseMap) {
1006 unsigned Opc = Node->getMachineOpcode();
1007
1008 // Handle subreg insert/extract specially
1009 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
1010 Opc == TargetOpcode::INSERT_SUBREG ||
1011 Opc == TargetOpcode::SUBREG_TO_REG) {
1012 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
1013 return;
1014 }
1015
1016 // Handle COPY_TO_REGCLASS specially.
1017 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
1018 EmitCopyToRegClassNode(Node, VRBaseMap);
1019 return;
1020 }
1021
1022 // Handle REG_SEQUENCE specially.
1023 if (Opc == TargetOpcode::REG_SEQUENCE) {
1024 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
1025 return;
1026 }
1027
1028 if (Opc == TargetOpcode::IMPLICIT_DEF)
1029 // We want a unique VR for each IMPLICIT_DEF use.
1030 return;
1031
1032 const MCInstrDesc &II = TII->get(Opcode: Opc);
1033 unsigned NumResults = CountResults(Node);
1034 unsigned NumDefs = II.getNumDefs();
1035 const MCPhysReg *ScratchRegs = nullptr;
1036
1037 // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
1038 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
1039 // Stackmaps do not have arguments and do not preserve their calling
1040 // convention. However, to simplify runtime support, they clobber the same
1041 // scratch registers as AnyRegCC.
1042 unsigned CC = CallingConv::AnyReg;
1043 if (Opc == TargetOpcode::PATCHPOINT) {
1044 CC = Node->getConstantOperandVal(Num: PatchPointOpers::CCPos);
1045 NumDefs = NumResults;
1046 }
1047 ScratchRegs = TLI->getScratchRegisters(CC: (CallingConv::ID) CC);
1048 } else if (Opc == TargetOpcode::STATEPOINT) {
1049 NumDefs = NumResults;
1050 }
1051
1052 unsigned NumImpUses = 0;
1053 unsigned NodeOperands =
1054 countOperands(Node, NumExpUses: II.getNumOperands() - NumDefs, NumImpUses);
1055 bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
1056 II.isVariadic() && II.variadicOpsAreDefs();
1057 bool HasPhysRegOuts = NumResults > NumDefs && !II.implicit_defs().empty() &&
1058 !HasVRegVariadicDefs;
1059#ifndef NDEBUG
1060 unsigned NumMIOperands = NodeOperands + NumResults;
1061 if (II.isVariadic())
1062 assert(NumMIOperands >= II.getNumOperands() &&
1063 "Too few operands for a variadic node!");
1064 else
1065 assert(NumMIOperands >= II.getNumOperands() &&
1066 NumMIOperands <=
1067 II.getNumOperands() + II.implicit_defs().size() + NumImpUses &&
1068 "#operands for dag node doesn't match .td file!");
1069#endif
1070
1071 // Create the new machine instruction.
1072 MachineInstrBuilder MIB = BuildMI(MF&: *MF, MIMD: Node->getDebugLoc(), MCID: II);
1073
1074 // Transfer IR flags from the SDNode to the MachineInstr
1075 MachineInstr *MI = MIB.getInstr();
1076 const SDNodeFlags Flags = Node->getFlags();
1077 if (Flags.hasUnpredictable())
1078 MI->setFlag(MachineInstr::MIFlag::Unpredictable);
1079
1080 // Add result register values for things that are defined by this
1081 // instruction.
1082 if (NumResults) {
1083 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
1084
1085 if (Flags.hasNoSignedZeros())
1086 MI->setFlag(MachineInstr::MIFlag::FmNsz);
1087
1088 if (Flags.hasAllowReciprocal())
1089 MI->setFlag(MachineInstr::MIFlag::FmArcp);
1090
1091 if (Flags.hasNoNaNs())
1092 MI->setFlag(MachineInstr::MIFlag::FmNoNans);
1093
1094 if (Flags.hasNoInfs())
1095 MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
1096
1097 if (Flags.hasAllowContract())
1098 MI->setFlag(MachineInstr::MIFlag::FmContract);
1099
1100 if (Flags.hasApproximateFuncs())
1101 MI->setFlag(MachineInstr::MIFlag::FmAfn);
1102
1103 if (Flags.hasAllowReassociation())
1104 MI->setFlag(MachineInstr::MIFlag::FmReassoc);
1105
1106 if (Flags.hasNoUnsignedWrap())
1107 MI->setFlag(MachineInstr::MIFlag::NoUWrap);
1108
1109 if (Flags.hasNoSignedWrap())
1110 MI->setFlag(MachineInstr::MIFlag::NoSWrap);
1111
1112 if (Flags.hasExact())
1113 MI->setFlag(MachineInstr::MIFlag::IsExact);
1114
1115 if (Flags.hasNoFPExcept())
1116 MI->setFlag(MachineInstr::MIFlag::NoFPExcept);
1117
1118 if (Flags.hasDisjoint())
1119 MI->setFlag(MachineInstr::MIFlag::Disjoint);
1120
1121 if (Flags.hasSameSign())
1122 MI->setFlag(MachineInstr::MIFlag::SameSign);
1123
1124 if (Flags.hasNoConvergent())
1125 MI->setFlag(MachineInstr::MIFlag::NoConvergent);
1126 }
1127
1128 // Emit all of the actual operands of this instruction, adding them to the
1129 // instruction as appropriate.
1130 bool HasOptPRefs = NumDefs > NumResults;
1131 assert((!HasOptPRefs || !HasPhysRegOuts) &&
1132 "Unable to cope with optional defs and phys regs defs!");
1133 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
1134 for (unsigned i = NumSkip; i != NodeOperands; ++i)
1135 AddOperand(MIB, Op: Node->getOperand(Num: i), IIOpNum: i-NumSkip+NumDefs, II: &II,
1136 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
1137
1138 // Add scratch registers as implicit def and early clobber
1139 if (ScratchRegs)
1140 for (unsigned i = 0; ScratchRegs[i]; ++i)
1141 MIB.addReg(RegNo: ScratchRegs[i], Flags: RegState::ImplicitDefine |
1142 RegState::EarlyClobber);
1143
1144 // Set the memory reference descriptions of this instruction now that it is
1145 // part of the function.
1146 MIB.setMemRefs(cast<MachineSDNode>(Val: Node)->memoperands());
1147
1148 // Set the CFI type.
1149 MIB->setCFIType(MF&: *MF, Type: Node->getCFIType());
1150
1151 // Insert the instruction into position in the block. This needs to
1152 // happen before any custom inserter hook is called so that the
1153 // hook knows where in the block to insert the replacement code.
1154 MBB->insert(I: InsertPos, MI: MIB);
1155
1156 // The MachineInstr may also define physregs instead of virtregs. These
1157 // physreg values can reach other instructions in different ways:
1158 //
1159 // 1. When there is a use of a Node value beyond the explicitly defined
1160 // virtual registers, we emit a CopyFromReg for one of the implicitly
1161 // defined physregs. This only happens when HasPhysRegOuts is true.
1162 //
1163 // 2. A CopyFromReg reading a physreg may be glued to this instruction.
1164 //
1165 // 3. A glued instruction may implicitly use a physreg.
1166 //
1167 // 4. A glued instruction may use a RegisterSDNode operand.
1168 //
1169 // Collect all the used physreg defs, and make sure that any unused physreg
1170 // defs are marked as dead.
1171 SmallVector<Register, 8> UsedRegs;
1172
1173 // Additional results must be physical register defs.
1174 if (HasPhysRegOuts) {
1175 for (unsigned i = NumDefs; i < NumResults; ++i) {
1176 Register Reg = II.implicit_defs()[i - NumDefs];
1177 if (!Node->hasAnyUseOfValue(Value: i))
1178 continue;
1179 // This implicitly defined physreg has a use.
1180 UsedRegs.push_back(Elt: Reg);
1181 EmitCopyFromReg(Op: SDValue(Node, i), IsClone, SrcReg: Reg, VRBaseMap);
1182 }
1183 }
1184
1185 // Scan the glue chain for any used physregs.
1186 if (Node->getValueType(ResNo: Node->getNumValues()-1) == MVT::Glue) {
1187 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
1188 if (F->getOpcode() == ISD::CopyFromReg) {
1189 Register Reg = cast<RegisterSDNode>(Val: F->getOperand(Num: 1))->getReg();
1190 if (Reg.isPhysical())
1191 UsedRegs.push_back(Elt: Reg);
1192 continue;
1193 } else if (F->getOpcode() == ISD::CopyToReg) {
1194 // Skip CopyToReg nodes that are internal to the glue chain.
1195 continue;
1196 }
1197 // Collect declared implicit uses.
1198 const MCInstrDesc &MCID = TII->get(Opcode: F->getMachineOpcode());
1199 append_range(C&: UsedRegs, R: MCID.implicit_uses());
1200 // In addition to declared implicit uses, we must also check for
1201 // direct RegisterSDNode operands.
1202 for (const SDValue &Op : F->op_values())
1203 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Val: Op)) {
1204 Register Reg = R->getReg();
1205 if (Reg.isPhysical())
1206 UsedRegs.push_back(Elt: Reg);
1207 }
1208 }
1209 }
1210
1211 // Add rounding control registers as implicit def for function call.
1212 if (II.isCall() && MF->getFunction().hasFnAttribute(Kind: Attribute::StrictFP)) {
1213 ArrayRef<MCPhysReg> RCRegs = TLI->getRoundingControlRegisters();
1214 llvm::append_range(C&: UsedRegs, R&: RCRegs);
1215 }
1216
1217 // Finally mark unused registers as dead.
1218 if (!UsedRegs.empty() || !II.implicit_defs().empty() || II.hasOptionalDef())
1219 MIB->setPhysRegsDeadExcept(UsedRegs, TRI: *TRI);
1220
1221 // STATEPOINT is too 'dynamic' to have meaningful machine description.
1222 // We have to manually tie operands.
1223 if (Opc == TargetOpcode::STATEPOINT && NumDefs > 0) {
1224 assert(!HasPhysRegOuts && "STATEPOINT mishandled");
1225 MachineInstr *MI = MIB;
1226 unsigned Def = 0;
1227 int First = StatepointOpers(MI).getFirstGCPtrIdx();
1228 assert(First > 0 && "Statepoint has Defs but no GC ptr list");
1229 unsigned Use = (unsigned)First;
1230 while (Def < NumDefs) {
1231 if (MI->getOperand(i: Use).isReg())
1232 MI->tieOperands(DefIdx: Def++, UseIdx: Use);
1233 Use = StackMaps::getNextMetaArgIdx(MI, CurIdx: Use);
1234 }
1235 }
1236
1237 unsigned Op = Node->getNumOperands();
1238 if (Op != 0 && Node->getOperand(Num: Op - 1)->getOpcode() ==
1239 ~(unsigned)TargetOpcode::CONVERGENCECTRL_GLUE) {
1240 Register VReg = getVR(Op: Node->getOperand(Num: Op - 1)->getOperand(Num: 0), VRBaseMap);
1241 MachineOperand MO = MachineOperand::CreateReg(Reg: VReg, /*isDef=*/false,
1242 /*isImp=*/true);
1243 MIB->addOperand(Op: MO);
1244 Op--;
1245 }
1246
1247 if (Op != 0 &&
1248 Node->getOperand(Num: Op - 1)->getOpcode() == ISD::DEACTIVATION_SYMBOL) {
1249 MI->setDeactivationSymbol(
1250 MF&: *MF, DS: const_cast<GlobalValue *>(
1251 cast<DeactivationSymbolSDNode>(Val: Node->getOperand(Num: Op - 1))
1252 ->getGlobal()));
1253 Op--;
1254 }
1255
1256 // Run post-isel target hook to adjust this instruction if needed.
1257 if (II.hasPostISelHook())
1258 TLI->AdjustInstrPostInstrSelection(MI&: *MIB, Node);
1259}
1260
1261/// EmitSpecialNode - Generate machine code for a target-independent node and
1262/// needed dependencies.
1263void InstrEmitter::
1264EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
1265 VRBaseMapType &VRBaseMap) {
1266 switch (Node->getOpcode()) {
1267 default:
1268#ifndef NDEBUG
1269 Node->dump();
1270#endif
1271 llvm_unreachable("This target-independent node should have been selected!");
1272 case ISD::EntryToken:
1273 case ISD::MERGE_VALUES:
1274 case ISD::TokenFactor:
1275 case ISD::DEACTIVATION_SYMBOL:
1276 break;
1277 case ISD::CopyToReg: {
1278 Register DestReg = cast<RegisterSDNode>(Val: Node->getOperand(Num: 1))->getReg();
1279 SDValue SrcVal = Node->getOperand(Num: 2);
1280 if (DestReg.isVirtual() && SrcVal.isMachineOpcode() &&
1281 SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
1282 // Instead building a COPY to that vreg destination, build an
1283 // IMPLICIT_DEF instruction instead.
1284 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Node->getDebugLoc(),
1285 MCID: TII->get(Opcode: TargetOpcode::IMPLICIT_DEF), DestReg);
1286 break;
1287 }
1288 Register SrcReg;
1289 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Val&: SrcVal))
1290 SrcReg = R->getReg();
1291 else
1292 SrcReg = getVR(Op: SrcVal, VRBaseMap);
1293
1294 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1295 break;
1296
1297 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Node->getDebugLoc(), MCID: TII->get(Opcode: TargetOpcode::COPY),
1298 DestReg).addReg(RegNo: SrcReg);
1299 break;
1300 }
1301 case ISD::CopyFromReg: {
1302 Register SrcReg = cast<RegisterSDNode>(Val: Node->getOperand(Num: 1))->getReg();
1303 EmitCopyFromReg(Op: SDValue(Node, 0), IsClone, SrcReg, VRBaseMap);
1304 break;
1305 }
1306 case ISD::EH_LABEL:
1307 case ISD::ANNOTATION_LABEL: {
1308 unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1309 ? TargetOpcode::EH_LABEL
1310 : TargetOpcode::ANNOTATION_LABEL;
1311 MCSymbol *S = cast<LabelSDNode>(Val: Node)->getLabel();
1312 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Node->getDebugLoc(),
1313 MCID: TII->get(Opcode: Opc)).addSym(Sym: S);
1314 break;
1315 }
1316
1317 case ISD::LIFETIME_START:
1318 case ISD::LIFETIME_END: {
1319 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START)
1320 ? TargetOpcode::LIFETIME_START
1321 : TargetOpcode::LIFETIME_END;
1322 auto *FI = cast<FrameIndexSDNode>(Val: Node->getOperand(Num: 1));
1323 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Node->getDebugLoc(), MCID: TII->get(Opcode: TarOp))
1324 .addFrameIndex(Idx: FI->getIndex());
1325 break;
1326 }
1327
1328 case ISD::PSEUDO_PROBE: {
1329 unsigned TarOp = TargetOpcode::PSEUDO_PROBE;
1330 auto Guid = cast<PseudoProbeSDNode>(Val: Node)->getGuid();
1331 auto Index = cast<PseudoProbeSDNode>(Val: Node)->getIndex();
1332 auto Attr = cast<PseudoProbeSDNode>(Val: Node)->getAttributes();
1333
1334 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Node->getDebugLoc(), MCID: TII->get(Opcode: TarOp))
1335 .addImm(Val: Guid)
1336 .addImm(Val: Index)
1337 .addImm(Val: (uint8_t)PseudoProbeType::Block)
1338 .addImm(Val: Attr);
1339 break;
1340 }
1341
1342 case ISD::INLINEASM:
1343 case ISD::INLINEASM_BR: {
1344 unsigned NumOps = Node->getNumOperands();
1345 if (Node->getOperand(Num: NumOps-1).getValueType() == MVT::Glue)
1346 --NumOps; // Ignore the glue operand.
1347
1348 // Create the inline asm machine instruction.
1349 unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1350 ? TargetOpcode::INLINEASM_BR
1351 : TargetOpcode::INLINEASM;
1352 MachineInstrBuilder MIB =
1353 BuildMI(MF&: *MF, MIMD: Node->getDebugLoc(), MCID: TII->get(Opcode: TgtOpc));
1354
1355 // Add the asm string as an external symbol operand.
1356 SDValue AsmStrV = Node->getOperand(Num: InlineAsm::Op_AsmString);
1357 const char *AsmStr = cast<ExternalSymbolSDNode>(Val&: AsmStrV)->getSymbol();
1358 MIB.addExternalSymbol(FnName: AsmStr);
1359
1360 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1361 // bits.
1362 int64_t ExtraInfo =
1363 cast<ConstantSDNode>(Val: Node->getOperand(Num: InlineAsm::Op_ExtraInfo))->
1364 getZExtValue();
1365 MIB.addImm(Val: ExtraInfo);
1366
1367 // Remember to operand index of the group flags.
1368 SmallVector<unsigned, 8> GroupIdx;
1369
1370 // Remember registers that are part of early-clobber defs.
1371 SmallVector<Register, 8> ECRegs;
1372
1373 // Add all of the operand registers to the instruction.
1374 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1375 unsigned Flags = Node->getConstantOperandVal(Num: i);
1376 const InlineAsm::Flag F(Flags);
1377 const unsigned NumVals = F.getNumOperandRegisters();
1378
1379 GroupIdx.push_back(Elt: MIB->getNumOperands());
1380 MIB.addImm(Val: Flags);
1381 ++i; // Skip the ID value.
1382
1383 switch (F.getKind()) {
1384 case InlineAsm::Kind::RegDef:
1385 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1386 Register Reg = cast<RegisterSDNode>(Val: Node->getOperand(Num: i))->getReg();
1387 // FIXME: Add dead flags for physical and virtual registers defined.
1388 // For now, mark physical register defs as implicit to help fast
1389 // regalloc. This makes inline asm look a lot like calls.
1390 MIB.addReg(RegNo: Reg, Flags: RegState::Define | getImplRegState(B: Reg.isPhysical()));
1391 }
1392 break;
1393 case InlineAsm::Kind::RegDefEarlyClobber:
1394 case InlineAsm::Kind::Clobber:
1395 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1396 Register Reg = cast<RegisterSDNode>(Val: Node->getOperand(Num: i))->getReg();
1397 MIB.addReg(RegNo: Reg, Flags: RegState::Define | RegState::EarlyClobber |
1398 getImplRegState(B: Reg.isPhysical()));
1399 ECRegs.push_back(Elt: Reg);
1400 }
1401 break;
1402 case InlineAsm::Kind::RegUse: // Use of register.
1403 case InlineAsm::Kind::Imm: // Immediate.
1404 case InlineAsm::Kind::Mem: // Non-function addressing mode.
1405 // The addressing mode has been selected, just add all of the
1406 // operands to the machine instruction.
1407 for (unsigned j = 0; j != NumVals; ++j, ++i)
1408 AddOperand(MIB, Op: Node->getOperand(Num: i), IIOpNum: 0, II: nullptr, VRBaseMap,
1409 /*IsDebug=*/false, IsClone, IsCloned);
1410
1411 // Manually set isTied bits.
1412 if (F.isRegUseKind()) {
1413 unsigned DefGroup;
1414 if (F.isUseOperandTiedToDef(Idx&: DefGroup)) {
1415 unsigned DefIdx = GroupIdx[DefGroup] + 1;
1416 unsigned UseIdx = GroupIdx.back() + 1;
1417 for (unsigned j = 0; j != NumVals; ++j)
1418 MIB->tieOperands(DefIdx: DefIdx + j, UseIdx: UseIdx + j);
1419 }
1420 }
1421 break;
1422 case InlineAsm::Kind::Func: // Function addressing mode.
1423 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1424 SDValue Op = Node->getOperand(Num: i);
1425 AddOperand(MIB, Op, IIOpNum: 0, II: nullptr, VRBaseMap,
1426 /*IsDebug=*/false, IsClone, IsCloned);
1427
1428 // Adjust Target Flags for function reference.
1429 if (auto *TGA = dyn_cast<GlobalAddressSDNode>(Val&: Op)) {
1430 unsigned NewFlags =
1431 MF->getSubtarget().classifyGlobalFunctionReference(
1432 GV: TGA->getGlobal());
1433 unsigned LastIdx = MIB.getInstr()->getNumOperands() - 1;
1434 MIB.getInstr()->getOperand(i: LastIdx).setTargetFlags(NewFlags);
1435 }
1436 }
1437 }
1438 }
1439
1440 // GCC inline assembly allows input operands to also be early-clobber
1441 // output operands (so long as the operand is written only after it's
1442 // used), but this does not match the semantics of our early-clobber flag.
1443 // If an early-clobber operand register is also an input operand register,
1444 // then remove the early-clobber flag.
1445 for (Register Reg : ECRegs) {
1446 if (MIB->readsRegister(Reg, TRI)) {
1447 MachineOperand *MO =
1448 MIB->findRegisterDefOperand(Reg, TRI, isDead: false, Overlap: false);
1449 assert(MO && "No def operand for clobbered register?");
1450 MO->setIsEarlyClobber(false);
1451 }
1452 }
1453
1454 // Get the mdnode from the asm if it exists and add it to the instruction.
1455 SDValue MDV = Node->getOperand(Num: InlineAsm::Op_MDNode);
1456 const MDNode *MD = cast<MDNodeSDNode>(Val&: MDV)->getMD();
1457 if (MD)
1458 MIB.addMetadata(MD);
1459
1460 // Add rounding control registers as implicit def for inline asm.
1461 if (MF->getFunction().hasFnAttribute(Kind: Attribute::StrictFP)) {
1462 ArrayRef<MCPhysReg> RCRegs = TLI->getRoundingControlRegisters();
1463 for (MCPhysReg Reg : RCRegs)
1464 MIB.addReg(RegNo: Reg, Flags: RegState::ImplicitDefine);
1465 }
1466
1467 MBB->insert(I: InsertPos, MI: MIB);
1468 break;
1469 }
1470 }
1471}
1472
1473/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1474/// at the given position in the given block.
1475InstrEmitter::InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb,
1476 MachineBasicBlock::iterator insertpos)
1477 : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1478 TII(MF->getSubtarget().getInstrInfo()),
1479 TRI(MF->getSubtarget().getRegisterInfo()),
1480 TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1481 InsertPos(insertpos) {
1482 EmitDebugInstrRefs = mbb->getParent()->useDebugInstrRef();
1483}
1484