1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the Emit routines for the SelectionDAG class, which creates
10// MachineInstrs based on the decisions of the SelectionDAG instruction
11// selection.
12//
13//===----------------------------------------------------------------------===//
14
15#include "InstrEmitter.h"
16#include "SDNodeDbgValue.h"
17#include "llvm/BinaryFormat/Dwarf.h"
18#include "llvm/CodeGen/ISDOpcodes.h"
19#include "llvm/CodeGen/MachineConstantPool.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/SelectionDAGNodes.h"
24#include "llvm/CodeGen/StackMaps.h"
25#include "llvm/CodeGen/TargetInstrInfo.h"
26#include "llvm/CodeGen/TargetLowering.h"
27#include "llvm/CodeGen/TargetSubtargetInfo.h"
28#include "llvm/IR/DebugInfoMetadata.h"
29#include "llvm/IR/PseudoProbe.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/Target/TargetMachine.h"
32using namespace llvm;
33
34#define DEBUG_TYPE "instr-emitter"
35
36/// MinRCSize - Smallest register class we allow when constraining virtual
37/// registers. If satisfying all register class constraints would require
38/// using a smaller register class, emit a COPY to a new virtual register
39/// instead.
40const unsigned MinRCSize = 4;
41
42/// CountResults - The results of target nodes have register or immediate
43/// operands first, then an optional chain, and optional glue operands (which do
44/// not go into the resulting MachineInstr).
45unsigned InstrEmitter::CountResults(SDNode *Node) {
46 unsigned N = Node->getNumValues();
47 while (N && Node->getValueType(ResNo: N - 1) == MVT::Glue)
48 --N;
49 if (N && Node->getValueType(ResNo: N - 1) == MVT::Other)
50 --N; // Skip over chain result.
51 return N;
52}
53
54/// countOperands - The inputs to target nodes have any actual inputs first,
55/// followed by an optional chain operand, then an optional glue operand.
56/// Compute the number of actual operands that will go into the resulting
57/// MachineInstr.
58///
59/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
60/// the chain and glue. These operands may be implicit on the machine instr.
61static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
62 unsigned &NumImpUses) {
63 unsigned N = Node->getNumOperands();
64 while (N && Node->getOperand(Num: N - 1).getValueType() == MVT::Glue)
65 --N;
66 if (N && Node->getOperand(Num: N - 1).getOpcode() == ISD::DEACTIVATION_SYMBOL)
67 --N; // Ignore deactivation symbol if it exists.
68 if (N && Node->getOperand(Num: N - 1).getValueType() == MVT::Other)
69 --N; // Ignore chain if it exists.
70
71 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
72 NumImpUses = N - NumExpUses;
73 for (unsigned I = N; I > NumExpUses; --I) {
74 if (isa<RegisterMaskSDNode>(Val: Node->getOperand(Num: I - 1)))
75 continue;
76 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Val: Node->getOperand(Num: I - 1)))
77 if (RN->getReg().isPhysical())
78 continue;
79 NumImpUses = N - I;
80 break;
81 }
82
83 return N;
84}
85
86/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
87/// implicit physical register output.
88void InstrEmitter::EmitCopyFromReg(SDValue Op, bool IsClone, Register SrcReg,
89 VRBaseMapType &VRBaseMap) {
90 Register VRBase;
91 if (SrcReg.isVirtual()) {
92 // Just use the input register directly!
93 if (IsClone)
94 VRBaseMap.erase(Val: Op);
95 bool isNew = VRBaseMap.insert(KV: std::make_pair(x&: Op, y&: SrcReg)).second;
96 (void)isNew; // Silence compiler warning.
97 assert(isNew && "Node emitted out of order - early");
98 return;
99 }
100
101 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
102 // the CopyToReg'd destination register instead of creating a new vreg.
103 bool MatchReg = true;
104
105 MVT VT = Op.getSimpleValueType();
106
107 // FIXME: The Untyped check is a workaround for SystemZ i128 inline assembly
108 // using i128, when it should probably be using v2i64.
109 const TargetRegisterClass *UseRC =
110 VT == MVT::Untyped ? nullptr : TLI->getRegClassFor(VT, isDivergent: Op->isDivergent());
111
112 for (SDNode *User : Op->users()) {
113 bool Match = true;
114 if (User->getOpcode() == ISD::CopyToReg && User->getOperand(Num: 2) == Op) {
115 Register DestReg = cast<RegisterSDNode>(Val: User->getOperand(Num: 1))->getReg();
116 if (DestReg.isVirtual()) {
117 VRBase = DestReg;
118 Match = false;
119 } else if (DestReg != SrcReg)
120 Match = false;
121 } else {
122 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
123 if (User->getOperand(Num: i) != Op)
124 continue;
125 if (VT == MVT::Other || VT == MVT::Glue)
126 continue;
127 Match = false;
128 if (User->isMachineOpcode()) {
129 const MCInstrDesc &II = TII->get(Opcode: User->getMachineOpcode());
130 const TargetRegisterClass *RC = nullptr;
131 if (i + II.getNumDefs() < II.getNumOperands()) {
132 RC = TRI->getAllocatableClass(
133 RC: TII->getRegClass(MCID: II, OpNum: i + II.getNumDefs()));
134 }
135 if (!UseRC)
136 UseRC = RC;
137 else if (RC) {
138 const TargetRegisterClass *ComRC =
139 TRI->getCommonSubClass(A: UseRC, B: RC);
140 // If multiple uses expect disjoint register classes, we emit
141 // copies in AddRegisterOperand.
142 if (ComRC)
143 UseRC = ComRC;
144 }
145 }
146 }
147 }
148 MatchReg &= Match;
149 if (VRBase)
150 break;
151 }
152
153 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
154 SrcRC = TRI->getMinimalPhysRegClass(Reg: SrcReg, VT);
155
156 // Figure out the register class to create for the destreg.
157 if (VRBase) {
158 DstRC = MRI->getRegClass(Reg: VRBase);
159 } else if (UseRC) {
160 assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
161 "Incompatible phys register def and uses!");
162 DstRC = UseRC;
163 } else
164 DstRC = SrcRC;
165
166 // If all uses are reading from the src physical register and copying the
167 // register is either impossible or very expensive, then don't create a copy.
168 if (MatchReg && SrcRC->expensiveOrImpossibleToCopy()) {
169 VRBase = SrcReg;
170 } else {
171 // Create the reg, emit the copy.
172 VRBase = MRI->createVirtualRegister(RegClass: DstRC);
173 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Op.getDebugLoc(), MCID: TII->get(Opcode: TargetOpcode::COPY),
174 DestReg: VRBase)
175 .addReg(RegNo: SrcReg);
176 }
177
178 if (IsClone)
179 VRBaseMap.erase(Val: Op);
180 bool isNew = VRBaseMap.insert(KV: std::make_pair(x&: Op, y&: VRBase)).second;
181 (void)isNew; // Silence compiler warning.
182 assert(isNew && "Node emitted out of order - early");
183}
184
185void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
186 MachineInstrBuilder &MIB,
187 const MCInstrDesc &II,
188 bool IsClone, bool IsCloned,
189 VRBaseMapType &VRBaseMap) {
190 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
191 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
192
193 unsigned NumResults = CountResults(Node);
194 bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
195 II.isVariadic() && II.variadicOpsAreDefs();
196 unsigned NumVRegs = HasVRegVariadicDefs ? NumResults : II.getNumDefs();
197 if (Node->getMachineOpcode() == TargetOpcode::STATEPOINT)
198 NumVRegs = NumResults;
199 for (unsigned i = 0; i < NumVRegs; ++i) {
200 // If the specific node value is only used by a CopyToReg and the dest reg
201 // is a vreg in the same register class, use the CopyToReg'd destination
202 // register instead of creating a new vreg.
203 Register VRBase;
204 const TargetRegisterClass *RC =
205 TRI->getAllocatableClass(RC: TII->getRegClass(MCID: II, OpNum: i));
206 // Always let the value type influence the used register class. The
207 // constraints on the instruction may be too lax to represent the value
208 // type correctly. For example, a 64-bit float (X86::FR64) can't live in
209 // the 32-bit float super-class (X86::FR32).
210 if (i < NumResults && TLI->isTypeLegal(VT: Node->getSimpleValueType(ResNo: i))) {
211 const TargetRegisterClass *VTRC = TLI->getRegClassFor(
212 VT: Node->getSimpleValueType(ResNo: i),
213 isDivergent: (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));
214 if (RC)
215 VTRC = TRI->getCommonSubClass(A: RC, B: VTRC);
216 if (VTRC)
217 RC = VTRC;
218 }
219
220 if (!II.operands().empty() && II.operands()[i].isOptionalDef()) {
221 // Optional def must be a physical register.
222 VRBase = cast<RegisterSDNode>(Val: Node->getOperand(Num: i-NumResults))->getReg();
223 assert(VRBase.isPhysical());
224 MIB.addReg(RegNo: VRBase, Flags: RegState::Define);
225 }
226
227 if (!VRBase && !IsClone && !IsCloned)
228 for (SDNode *User : Node->users()) {
229 if (User->getOpcode() == ISD::CopyToReg &&
230 User->getOperand(Num: 2).getNode() == Node &&
231 User->getOperand(Num: 2).getResNo() == i) {
232 Register Reg = cast<RegisterSDNode>(Val: User->getOperand(Num: 1))->getReg();
233 if (Reg.isVirtual()) {
234 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
235 if (RegRC == RC) {
236 VRBase = Reg;
237 MIB.addReg(RegNo: VRBase, Flags: RegState::Define);
238 break;
239 }
240 }
241 }
242 }
243
244 // Create the result registers for this node and add the result regs to
245 // the machine instruction.
246 if (!VRBase) {
247 assert(RC && "Isn't a register operand!");
248 VRBase = MRI->createVirtualRegister(RegClass: RC);
249 MIB.addReg(RegNo: VRBase, Flags: RegState::Define);
250 }
251
252 // If this def corresponds to a result of the SDNode insert the VRBase into
253 // the lookup map.
254 if (i < NumResults) {
255 SDValue Op(Node, i);
256 if (IsClone)
257 VRBaseMap.erase(Val: Op);
258 bool isNew = VRBaseMap.insert(KV: std::make_pair(x&: Op, y&: VRBase)).second;
259 (void)isNew; // Silence compiler warning.
260 assert(isNew && "Node emitted out of order - early");
261 }
262 }
263}
264
265/// getVR - Return the virtual register corresponding to the specified result
266/// of the specified node.
267Register InstrEmitter::getVR(SDValue Op, VRBaseMapType &VRBaseMap) {
268 if (Op.isMachineOpcode() &&
269 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
270 // Add an IMPLICIT_DEF instruction before every use.
271 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
272 // does not include operand register class info.
273 const TargetRegisterClass *RC = TLI->getRegClassFor(
274 VT: Op.getSimpleValueType(), isDivergent: Op.getNode()->isDivergent());
275 Register VReg = MRI->createVirtualRegister(RegClass: RC);
276 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Op.getDebugLoc(),
277 MCID: TII->get(Opcode: TargetOpcode::IMPLICIT_DEF), DestReg: VReg);
278 return VReg;
279 }
280
281 VRBaseMapType::iterator I = VRBaseMap.find(Val: Op);
282 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
283 return I->second;
284}
285
286static bool isConvergenceCtrlMachineOp(SDValue Op) {
287 if (Op->isMachineOpcode()) {
288 switch (Op->getMachineOpcode()) {
289 case TargetOpcode::CONVERGENCECTRL_ANCHOR:
290 case TargetOpcode::CONVERGENCECTRL_ENTRY:
291 case TargetOpcode::CONVERGENCECTRL_LOOP:
292 case TargetOpcode::CONVERGENCECTRL_GLUE:
293 return true;
294 }
295 return false;
296 }
297
298 // We can reach here when CopyFromReg is encountered. But rather than making a
299 // special case for that, we just make sure we don't reach here in some
300 // surprising way.
301 switch (Op->getOpcode()) {
302 case ISD::CONVERGENCECTRL_ANCHOR:
303 case ISD::CONVERGENCECTRL_ENTRY:
304 case ISD::CONVERGENCECTRL_LOOP:
305 case ISD::CONVERGENCECTRL_GLUE:
306 llvm_unreachable("Convergence control should have been selected by now.");
307 }
308 return false;
309}
310
311/// AddRegisterOperand - Add the specified register as an operand to the
312/// specified machine instr. Insert register copies if the register is
313/// not in the required register class.
314void
315InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
316 SDValue Op,
317 unsigned IIOpNum,
318 const MCInstrDesc *II,
319 VRBaseMapType &VRBaseMap,
320 bool IsDebug, bool IsClone, bool IsCloned) {
321 assert(Op.getValueType() != MVT::Other &&
322 Op.getValueType() != MVT::Glue &&
323 "Chain and glue operands should occur at end of operand list!");
324 // Get/emit the operand.
325 Register VReg = getVR(Op, VRBaseMap);
326
327 const MCInstrDesc &MCID = MIB->getDesc();
328 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
329 MCID.operands()[IIOpNum].isOptionalDef();
330
331 // If the instruction requires a register in a different class, create
332 // a new virtual register and copy the value into it, but first attempt to
333 // shrink VReg's register class within reason. For example, if VReg == GR32
334 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
335 if (II) {
336 const TargetRegisterClass *OpRC = nullptr;
337 if (IIOpNum < II->getNumOperands())
338 OpRC = TII->getRegClass(MCID: *II, OpNum: IIOpNum);
339
340 if (OpRC) {
341 unsigned MinNumRegs = MinRCSize;
342 // Don't apply any RC size limit for IMPLICIT_DEF. Each use has a unique
343 // virtual register.
344 if (Op.isMachineOpcode() &&
345 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)
346 MinNumRegs = 0;
347
348 const TargetRegisterClass *ConstrainedRC
349 = MRI->constrainRegClass(Reg: VReg, RC: OpRC, MinNumRegs);
350 if (!ConstrainedRC) {
351 OpRC = TRI->getAllocatableClass(RC: OpRC);
352 assert(OpRC && "Constraints cannot be fulfilled for allocation");
353 Register NewVReg = MRI->createVirtualRegister(RegClass: OpRC);
354 BuildMI(BB&: *MBB, I: InsertPos, MIMD: MIB->getDebugLoc(),
355 MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: NewVReg)
356 .addReg(RegNo: VReg);
357 VReg = NewVReg;
358 } else {
359 assert(ConstrainedRC->isAllocatable() &&
360 "Constraining an allocatable VReg produced an unallocatable class?");
361 }
362 }
363 }
364
365 // If this value has only one use, that use is a kill. This is a
366 // conservative approximation. InstrEmitter does trivial coalescing
367 // with CopyFromReg nodes, so don't emit kill flags for them.
368 // Avoid kill flags on Schedule cloned nodes, since there will be
369 // multiple uses.
370 // Tied operands are never killed, so we need to check that. And that
371 // means we need to determine the index of the operand.
372 // Don't kill convergence control tokens. Initially they are only used in glue
373 // nodes, and the InstrEmitter later adds implicit uses on the users of the
374 // glue node. This can sometimes make it seem like there is only one use,
375 // which is the glue node itself.
376 bool isKill = Op.hasOneUse() && !isConvergenceCtrlMachineOp(Op) &&
377 Op.getNode()->getOpcode() != ISD::CopyFromReg && !IsDebug &&
378 !(IsClone || IsCloned);
379 if (isKill) {
380 unsigned Idx = MIB->getNumOperands();
381 while (Idx > 0 &&
382 MIB->getOperand(i: Idx-1).isReg() &&
383 MIB->getOperand(i: Idx-1).isImplicit())
384 --Idx;
385 bool isTied = MCID.getOperandConstraint(OpNum: Idx, Constraint: MCOI::TIED_TO) != -1;
386 if (isTied)
387 isKill = false;
388 }
389
390 MIB.addReg(RegNo: VReg, Flags: getDefRegState(B: isOptDef) | getKillRegState(B: isKill) |
391 getDebugRegState(B: IsDebug));
392}
393
394/// AddOperand - Add the specified operand to the specified machine instr. II
395/// specifies the instruction information for the node, and IIOpNum is the
396/// operand number (in the II) that we are adding.
397void InstrEmitter::AddOperand(MachineInstrBuilder &MIB, SDValue Op,
398 unsigned IIOpNum, const MCInstrDesc *II,
399 VRBaseMapType &VRBaseMap, bool IsDebug,
400 bool IsClone, bool IsCloned) {
401 if (Op.isMachineOpcode()) {
402 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
403 IsDebug, IsClone, IsCloned);
404 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op)) {
405 if (C->getAPIntValue().getSignificantBits() <= 64) {
406 MIB.addImm(Val: C->getSExtValue());
407 } else {
408 MIB.addCImm(
409 Val: ConstantInt::get(Context&: MF->getFunction().getContext(), V: C->getAPIntValue()));
410 }
411 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Val&: Op)) {
412 MIB.addFPImm(Val: F->getConstantFPValue());
413 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Val&: Op)) {
414 Register VReg = R->getReg();
415 MVT OpVT = Op.getSimpleValueType();
416 const TargetRegisterClass *IIRC =
417 II ? TRI->getAllocatableClass(RC: TII->getRegClass(MCID: *II, OpNum: IIOpNum)) : nullptr;
418 const TargetRegisterClass *OpRC =
419 TLI->isTypeLegal(VT: OpVT)
420 ? TLI->getRegClassFor(VT: OpVT,
421 isDivergent: Op.getNode()->isDivergent() ||
422 (IIRC && TRI->isDivergentRegClass(RC: IIRC)))
423 : nullptr;
424
425 if (OpRC && IIRC && OpRC != IIRC && VReg.isVirtual()) {
426 Register NewVReg = MRI->createVirtualRegister(RegClass: IIRC);
427 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Op.getNode()->getDebugLoc(),
428 MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: NewVReg).addReg(RegNo: VReg);
429 VReg = NewVReg;
430 }
431 // Turn additional physreg operands into implicit uses on non-variadic
432 // instructions. This is used by call and return instructions passing
433 // arguments in registers.
434 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
435 MIB.addReg(RegNo: VReg, Flags: getImplRegState(B: Imp));
436 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Val&: Op)) {
437 MIB.addRegMask(Mask: RM->getRegMask());
438 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Val&: Op)) {
439 MIB.addGlobalAddress(GV: TGA->getGlobal(), Offset: TGA->getOffset(),
440 TargetFlags: TGA->getTargetFlags());
441 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Val&: Op)) {
442 MIB.addMBB(MBB: BBNode->getBasicBlock());
443 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Val&: Op)) {
444 MIB.addFrameIndex(Idx: FI->getIndex());
445 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Val&: Op)) {
446 MIB.addJumpTableIndex(Idx: JT->getIndex(), TargetFlags: JT->getTargetFlags());
447 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Val&: Op)) {
448 int Offset = CP->getOffset();
449 Align Alignment = CP->getAlign();
450
451 unsigned Idx;
452 MachineConstantPool *MCP = MF->getConstantPool();
453 if (CP->isMachineConstantPoolEntry())
454 Idx = MCP->getConstantPoolIndex(V: CP->getMachineCPVal(), Alignment);
455 else
456 Idx = MCP->getConstantPoolIndex(C: CP->getConstVal(), Alignment);
457 MIB.addConstantPoolIndex(Idx, Offset, TargetFlags: CP->getTargetFlags());
458 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Val&: Op)) {
459 MIB.addExternalSymbol(FnName: ES->getSymbol(), TargetFlags: ES->getTargetFlags());
460 } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Val&: Op)) {
461 MIB.addSym(Sym: SymNode->getMCSymbol());
462 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Val&: Op)) {
463 MIB.addBlockAddress(BA: BA->getBlockAddress(),
464 Offset: BA->getOffset(),
465 TargetFlags: BA->getTargetFlags());
466 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Val&: Op)) {
467 MIB.addTargetIndex(Idx: TI->getIndex(), Offset: TI->getOffset(), TargetFlags: TI->getTargetFlags());
468 } else {
469 assert(Op.getValueType() != MVT::Other &&
470 Op.getValueType() != MVT::Glue &&
471 "Chain and glue operands should occur at end of operand list!");
472 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
473 IsDebug, IsClone, IsCloned);
474 }
475}
476
477Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
478 MVT VT, bool isDivergent, const DebugLoc &DL) {
479 const TargetRegisterClass *VRC = MRI->getRegClass(Reg: VReg);
480 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(RC: VRC, Idx: SubIdx);
481
482 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
483 // within reason.
484 if (RC && RC != VRC)
485 RC = MRI->constrainRegClass(Reg: VReg, RC, MinNumRegs: MinRCSize);
486
487 // VReg has been adjusted. It can be used with SubIdx operands now.
488 if (RC)
489 return VReg;
490
491 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
492 // register instead.
493 RC = TRI->getSubClassWithSubReg(RC: TLI->getRegClassFor(VT, isDivergent), Idx: SubIdx);
494 assert(RC && "No legal register class for VT supports that SubIdx");
495 Register NewReg = MRI->createVirtualRegister(RegClass: RC);
496 BuildMI(BB&: *MBB, I: InsertPos, MIMD: DL, MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: NewReg)
497 .addReg(RegNo: VReg);
498 return NewReg;
499}
500
501/// EmitSubregNode - Generate machine code for subreg nodes.
502///
503void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap,
504 bool IsClone, bool IsCloned) {
505 Register VRBase;
506 unsigned Opc = Node->getMachineOpcode();
507
508 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
509 // the CopyToReg'd destination register instead of creating a new vreg.
510 for (SDNode *User : Node->users()) {
511 if (User->getOpcode() == ISD::CopyToReg &&
512 User->getOperand(Num: 2).getNode() == Node) {
513 Register DestReg = cast<RegisterSDNode>(Val: User->getOperand(Num: 1))->getReg();
514 if (DestReg.isVirtual()) {
515 VRBase = DestReg;
516 break;
517 }
518 }
519 }
520
521 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
522 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
523 // constraints on the %dst register, COPY can target all legal register
524 // classes.
525 unsigned SubIdx = Node->getConstantOperandVal(Num: 1);
526 const TargetRegisterClass *TRC =
527 TLI->getRegClassFor(VT: Node->getSimpleValueType(ResNo: 0), isDivergent: Node->isDivergent());
528
529 Register Reg;
530 MachineInstr *DefMI;
531 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Val: Node->getOperand(Num: 0));
532 if (R && R->getReg().isPhysical()) {
533 Reg = R->getReg();
534 DefMI = nullptr;
535 } else {
536 Reg = R ? R->getReg() : getVR(Op: Node->getOperand(Num: 0), VRBaseMap);
537 DefMI = MRI->getVRegDef(Reg);
538 }
539
540 Register SrcReg, DstReg;
541 unsigned DefSubIdx;
542 if (DefMI &&
543 TII->isCoalescableExtInstr(MI: *DefMI, SrcReg, DstReg, SubIdx&: DefSubIdx) &&
544 SubIdx == DefSubIdx &&
545 TRC == MRI->getRegClass(Reg: SrcReg)) {
546 // Optimize these:
547 // r1025 = s/zext r1024, 4
548 // r1026 = extract_subreg r1025, 4
549 // to a copy
550 // r1026 = copy r1024
551 VRBase = MRI->createVirtualRegister(RegClass: TRC);
552 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Node->getDebugLoc(),
553 MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: VRBase).addReg(RegNo: SrcReg);
554 MRI->clearKillFlags(Reg: SrcReg);
555 } else {
556 // Reg may not support a SubIdx sub-register, and we may need to
557 // constrain its register class or issue a COPY to a compatible register
558 // class.
559 if (Reg.isVirtual())
560 Reg = ConstrainForSubReg(VReg: Reg, SubIdx,
561 VT: Node->getOperand(Num: 0).getSimpleValueType(),
562 isDivergent: Node->isDivergent(), DL: Node->getDebugLoc());
563 // Create the destreg if it is missing.
564 if (!VRBase)
565 VRBase = MRI->createVirtualRegister(RegClass: TRC);
566
567 // Create the extract_subreg machine instruction.
568 MachineInstrBuilder CopyMI =
569 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Node->getDebugLoc(),
570 MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: VRBase);
571 if (Reg.isVirtual())
572 CopyMI.addReg(RegNo: Reg, Flags: {}, SubReg: SubIdx);
573 else
574 CopyMI.addReg(RegNo: TRI->getSubReg(Reg, Idx: SubIdx));
575 }
576 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
577 Opc == TargetOpcode::SUBREG_TO_REG) {
578 SDValue Reg;
579 SDValue SubReg;
580 unsigned SubIdx;
581 if (Opc == TargetOpcode::INSERT_SUBREG) {
582 Reg = Node->getOperand(Num: 0);
583 SubReg = Node->getOperand(Num: 1);
584 SubIdx = Node->getOperand(Num: 2)->getAsZExtVal();
585 } else {
586 SubReg = Node->getOperand(Num: 0);
587 SubIdx = Node->getOperand(Num: 1)->getAsZExtVal();
588 }
589
590 // Figure out the register class to create for the destreg. It should be
591 // the largest legal register class supporting SubIdx sub-registers.
592 // RegisterCoalescer will constrain it further if it decides to eliminate
593 // the INSERT_SUBREG instruction.
594 //
595 // %dst = INSERT_SUBREG %src, %sub, SubIdx
596 //
597 // is lowered by TwoAddressInstructionPass to:
598 //
599 // %dst = COPY %src
600 // %dst:SubIdx = COPY %sub
601 //
602 // There is no constraint on the %src register class.
603 //
604 const TargetRegisterClass *SRC =
605 TLI->getRegClassFor(VT: Node->getSimpleValueType(ResNo: 0), isDivergent: Node->isDivergent());
606 SRC = TRI->getSubClassWithSubReg(RC: SRC, Idx: SubIdx);
607 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
608
609 if (VRBase == 0 || !SRC->hasSubClassEq(RC: MRI->getRegClass(Reg: VRBase)))
610 VRBase = MRI->createVirtualRegister(RegClass: SRC);
611
612 // Create the insert_subreg or subreg_to_reg machine instruction.
613 MachineInstrBuilder MIB =
614 BuildMI(MF&: *MF, MIMD: Node->getDebugLoc(), MCID: TII->get(Opcode: Opc), DestReg: VRBase);
615
616 // If creating an insert_subreg, then the first input operand
617 // is a register
618 if (Reg) {
619 AddOperand(MIB, Op: Reg, IIOpNum: 0, II: nullptr, VRBaseMap, /*IsDebug=*/false, IsClone,
620 IsCloned);
621 }
622 // Add the subregister being inserted
623 AddOperand(MIB, Op: SubReg, IIOpNum: 0, II: nullptr, VRBaseMap, /*IsDebug=*/false, IsClone,
624 IsCloned);
625 MIB.addImm(Val: SubIdx);
626 MBB->insert(I: InsertPos, MI: MIB);
627 } else
628 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
629
630 SDValue Op(Node, 0);
631 bool isNew = VRBaseMap.insert(KV: std::make_pair(x&: Op, y&: VRBase)).second;
632 (void)isNew; // Silence compiler warning.
633 assert(isNew && "Node emitted out of order - early");
634}
635
636/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
637/// COPY_TO_REGCLASS is just a normal copy, except that the destination
638/// register is constrained to be in a particular register class.
639///
640void
641InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
642 VRBaseMapType &VRBaseMap) {
643 // Create the new VReg in the destination class and emit a copy.
644 unsigned DstRCIdx = Node->getConstantOperandVal(Num: 1);
645 const TargetRegisterClass *DstRC =
646 TRI->getAllocatableClass(RC: TRI->getRegClass(i: DstRCIdx));
647 Register NewVReg = MRI->createVirtualRegister(RegClass: DstRC);
648 const MCInstrDesc &II = TII->get(Opcode: TargetOpcode::COPY);
649 MachineInstrBuilder MIB = BuildMI(MF&: *MF, MIMD: Node->getDebugLoc(), MCID: II, DestReg: NewVReg);
650 AddOperand(MIB, Op: Node->getOperand(Num: 0), IIOpNum: 1, II: &II, VRBaseMap, /*IsDebug=*/false,
651 /*IsClone=*/false, /*IsCloned*/ false);
652
653 MBB->insert(I: InsertPos, MI: MIB);
654 SDValue Op(Node, 0);
655 bool isNew = VRBaseMap.insert(KV: std::make_pair(x&: Op, y&: NewVReg)).second;
656 (void)isNew; // Silence compiler warning.
657 assert(isNew && "Node emitted out of order - early");
658}
659
660/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
661///
662void InstrEmitter::EmitRegSequence(SDNode *Node, VRBaseMapType &VRBaseMap,
663 bool IsClone, bool IsCloned) {
664 unsigned DstRCIdx = Node->getConstantOperandVal(Num: 0);
665 const TargetRegisterClass *RC = TRI->getRegClass(i: DstRCIdx);
666 Register NewVReg = MRI->createVirtualRegister(RegClass: TRI->getAllocatableClass(RC));
667 const MCInstrDesc &II = TII->get(Opcode: TargetOpcode::REG_SEQUENCE);
668 MachineInstrBuilder MIB = BuildMI(MF&: *MF, MIMD: Node->getDebugLoc(), MCID: II, DestReg: NewVReg);
669 unsigned NumOps = Node->getNumOperands();
670 // If the input pattern has a chain, then the root of the corresponding
671 // output pattern will get a chain as well. This can happen to be a
672 // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
673 if (NumOps && Node->getOperand(Num: NumOps-1).getValueType() == MVT::Other)
674 --NumOps; // Ignore chain if it exists.
675
676 assert((NumOps & 1) == 1 &&
677 "REG_SEQUENCE must have an odd number of operands!");
678 for (unsigned i = 1; i != NumOps; ++i) {
679 SDValue Op = Node->getOperand(Num: i);
680 if ((i & 1) == 0) {
681 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Val: Node->getOperand(Num: i-1));
682 // Skip physical registers as they don't have a vreg to get and we'll
683 // insert copies for them in TwoAddressInstructionPass anyway.
684 if (!R || !R->getReg().isPhysical()) {
685 unsigned SubIdx = Op->getAsZExtVal();
686 Register SubReg = getVR(Op: Node->getOperand(Num: i - 1), VRBaseMap);
687 const TargetRegisterClass *TRC = MRI->getRegClass(Reg: SubReg);
688 const TargetRegisterClass *SRC =
689 TRI->getMatchingSuperRegClass(A: RC, B: TRC, Idx: SubIdx);
690 if (SRC && SRC != RC) {
691 MRI->setRegClass(Reg: NewVReg, RC: SRC);
692 RC = SRC;
693 }
694 }
695 }
696 AddOperand(MIB, Op, IIOpNum: i+1, II: &II, VRBaseMap, /*IsDebug=*/false,
697 IsClone, IsCloned);
698 }
699
700 MBB->insert(I: InsertPos, MI: MIB);
701 SDValue Op(Node, 0);
702 bool isNew = VRBaseMap.insert(KV: std::make_pair(x&: Op, y&: NewVReg)).second;
703 (void)isNew; // Silence compiler warning.
704 assert(isNew && "Node emitted out of order - early");
705}
706
707/// EmitDbgValue - Generate machine instruction for a dbg_value node.
708///
709MachineInstr *
710InstrEmitter::EmitDbgValue(SDDbgValue *SD,
711 VRBaseMapType &VRBaseMap) {
712 DebugLoc DL = SD->getDebugLoc();
713 assert(cast<DILocalVariable>(SD->getVariable())
714 ->isValidLocationForIntrinsic(DL) &&
715 "Expected inlined-at fields to agree");
716
717 SD->setIsEmitted();
718
719 assert(!SD->getLocationOps().empty() &&
720 "dbg_value with no location operands?");
721
722 if (SD->isInvalidated())
723 return EmitDbgNoLocation(SD);
724
725 // Attempt to produce a DBG_INSTR_REF if we've been asked to.
726 if (EmitDebugInstrRefs)
727 if (auto *InstrRef = EmitDbgInstrRef(SD, VRBaseMap))
728 return InstrRef;
729
730 // Emit variadic dbg_value nodes as DBG_VALUE_LIST if they have not been
731 // emitted as instruction references.
732 if (SD->isVariadic())
733 return EmitDbgValueList(SD, VRBaseMap);
734
735 // Emit single-location dbg_value nodes as DBG_VALUE if they have not been
736 // emitted as instruction references.
737 return EmitDbgValueFromSingleOp(SD, VRBaseMap);
738}
739
740MachineOperand GetMOForConstDbgOp(const SDDbgOperand &Op) {
741 const Value *V = Op.getConst();
742 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val: V)) {
743 if (CI->getBitWidth() > 64)
744 return MachineOperand::CreateCImm(CI);
745 if (CI->getBitWidth() == 1)
746 return MachineOperand::CreateImm(Val: CI->getZExtValue());
747 return MachineOperand::CreateImm(Val: CI->getSExtValue());
748 }
749 if (const ConstantFP *CF = dyn_cast<ConstantFP>(Val: V))
750 return MachineOperand::CreateFPImm(CFP: CF);
751 // Note: This assumes that all nullptr constants are zero-valued.
752 if (isa<ConstantPointerNull>(Val: V))
753 return MachineOperand::CreateImm(Val: 0);
754 // Undef or unhandled value type, so return an undef operand.
755 return MachineOperand::CreateReg(
756 /* Reg */ 0U, /* isDef */ false, /* isImp */ false,
757 /* isKill */ false, /* isDead */ false,
758 /* isUndef */ false, /* isEarlyClobber */ false,
759 /* SubReg */ 0, /* isDebug */ true);
760}
761
762void InstrEmitter::AddDbgValueLocationOps(
763 MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc,
764 ArrayRef<SDDbgOperand> LocationOps,
765 VRBaseMapType &VRBaseMap) {
766 for (const SDDbgOperand &Op : LocationOps) {
767 switch (Op.getKind()) {
768 case SDDbgOperand::FRAMEIX:
769 MIB.addFrameIndex(Idx: Op.getFrameIx());
770 break;
771 case SDDbgOperand::VREG:
772 MIB.addReg(RegNo: Op.getVReg());
773 break;
774 case SDDbgOperand::SDNODE: {
775 SDValue V = SDValue(Op.getSDNode(), Op.getResNo());
776 // It's possible we replaced this SDNode with other(s) and therefore
777 // didn't generate code for it. It's better to catch these cases where
778 // they happen and transfer the debug info, but trying to guarantee that
779 // in all cases would be very fragile; this is a safeguard for any
780 // that were missed.
781 if (VRBaseMap.count(Val: V) == 0)
782 MIB.addReg(RegNo: 0U); // undef
783 else
784 AddOperand(MIB, Op: V, IIOpNum: (*MIB).getNumOperands(), II: &DbgValDesc, VRBaseMap,
785 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
786 } break;
787 case SDDbgOperand::CONST:
788 MIB.add(MO: GetMOForConstDbgOp(Op));
789 break;
790 }
791 }
792}
793
794MachineInstr *
795InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
796 VRBaseMapType &VRBaseMap) {
797 MDNode *Var = SD->getVariable();
798 const DIExpression *Expr = SD->getExpression();
799 DebugLoc DL = SD->getDebugLoc();
800 const MCInstrDesc &RefII = TII->get(Opcode: TargetOpcode::DBG_INSTR_REF);
801
802 // Returns true if the given operand is not a legal debug operand for a
803 // DBG_INSTR_REF.
804 auto IsInvalidOp = [](SDDbgOperand DbgOp) {
805 return DbgOp.getKind() == SDDbgOperand::FRAMEIX;
806 };
807 // Returns true if the given operand is not itself an instruction reference
808 // but is a legal debug operand for a DBG_INSTR_REF.
809 auto IsNonInstrRefOp = [](SDDbgOperand DbgOp) {
810 return DbgOp.getKind() == SDDbgOperand::CONST;
811 };
812
813 // If this variable location does not depend on any instructions or contains
814 // any stack locations, produce it as a standard debug value instead.
815 if (any_of(Range: SD->getLocationOps(), P: IsInvalidOp) ||
816 all_of(Range: SD->getLocationOps(), P: IsNonInstrRefOp)) {
817 if (SD->isVariadic())
818 return EmitDbgValueList(SD, VRBaseMap);
819 return EmitDbgValueFromSingleOp(SD, VRBaseMap);
820 }
821
822 // Immediately fold any indirectness from the LLVM-IR intrinsic into the
823 // expression:
824 if (SD->isIndirect())
825 Expr = DIExpression::append(Expr, Ops: dwarf::DW_OP_deref);
826 // If this is not already a variadic expression, it must be modified to become
827 // one.
828 if (!SD->isVariadic())
829 Expr = DIExpression::convertToVariadicExpression(Expr);
830
831 SmallVector<MachineOperand> MOs;
832
833 // It may not be immediately possible to identify the MachineInstr that
834 // defines a VReg, it can depend for example on the order blocks are
835 // emitted in. When this happens, or when further analysis is needed later,
836 // produce an instruction like this:
837 //
838 // DBG_INSTR_REF !123, !456, %0:gr64
839 //
840 // i.e., point the instruction at the vreg, and patch it up later in
841 // MachineFunction::finalizeDebugInstrRefs.
842 auto AddVRegOp = [&](Register VReg) {
843 MOs.push_back(Elt: MachineOperand::CreateReg(
844 /* Reg */ VReg, /* isDef */ false, /* isImp */ false,
845 /* isKill */ false, /* isDead */ false,
846 /* isUndef */ false, /* isEarlyClobber */ false,
847 /* SubReg */ 0, /* isDebug */ true));
848 };
849 unsigned OpCount = SD->getLocationOps().size();
850 for (unsigned OpIdx = 0; OpIdx < OpCount; ++OpIdx) {
851 SDDbgOperand DbgOperand = SD->getLocationOps()[OpIdx];
852
853 // Try to find both the defined register and the instruction defining it.
854 MachineInstr *DefMI = nullptr;
855 Register VReg;
856
857 if (DbgOperand.getKind() == SDDbgOperand::VREG) {
858 VReg = DbgOperand.getVReg();
859
860 // No definition means that block hasn't been emitted yet. Leave a vreg
861 // reference to be fixed later.
862 if (!MRI->hasOneDef(RegNo: VReg)) {
863 AddVRegOp(VReg);
864 continue;
865 }
866
867 DefMI = &*MRI->def_instr_begin(RegNo: VReg);
868 } else if (DbgOperand.getKind() == SDDbgOperand::SDNODE) {
869 // Look up the corresponding VReg for the given SDNode, if any.
870 SDNode *Node = DbgOperand.getSDNode();
871 SDValue Op = SDValue(Node, DbgOperand.getResNo());
872 VRBaseMapType::iterator I = VRBaseMap.find(Val: Op);
873 // No VReg -> produce a DBG_VALUE $noreg instead.
874 if (I == VRBaseMap.end())
875 break;
876
877 // Try to pick out a defining instruction at this point.
878 VReg = getVR(Op, VRBaseMap);
879
880 // Again, if there's no instruction defining the VReg right now, fix it up
881 // later.
882 if (!MRI->hasOneDef(RegNo: VReg)) {
883 AddVRegOp(VReg);
884 continue;
885 }
886
887 DefMI = &*MRI->def_instr_begin(RegNo: VReg);
888 } else {
889 assert(DbgOperand.getKind() == SDDbgOperand::CONST);
890 MOs.push_back(Elt: GetMOForConstDbgOp(Op: DbgOperand));
891 continue;
892 }
893
894 // Avoid copy like instructions: they don't define values, only move them.
895 // Leave a virtual-register reference until it can be fixed up later, to
896 // find the underlying value definition.
897 if (DefMI->isCopyLike() || TII->isCopyInstr(MI: *DefMI)) {
898 AddVRegOp(VReg);
899 continue;
900 }
901
902 // Find the operand number which defines the specified VReg.
903 unsigned OperandIdx = 0;
904 for (const auto &MO : DefMI->operands()) {
905 if (MO.isReg() && MO.isDef() && MO.getReg() == VReg)
906 break;
907 ++OperandIdx;
908 }
909 assert(OperandIdx < DefMI->getNumOperands());
910
911 // Make the DBG_INSTR_REF refer to that instruction, and that operand.
912 unsigned InstrNum = DefMI->getDebugInstrNum();
913 MOs.push_back(Elt: MachineOperand::CreateDbgInstrRef(InstrIdx: InstrNum, OpIdx: OperandIdx));
914 }
915
916 // If we haven't created a valid MachineOperand for every DbgOp, abort and
917 // produce an undef DBG_VALUE.
918 if (MOs.size() != OpCount)
919 return EmitDbgNoLocation(SD);
920
921 return BuildMI(MF&: *MF, DL, MCID: RefII, IsIndirect: false, MOs, Variable: Var, Expr);
922}
923
924MachineInstr *InstrEmitter::EmitDbgNoLocation(SDDbgValue *SD) {
925 // An invalidated SDNode must generate an undef DBG_VALUE: although the
926 // original value is no longer computed, earlier DBG_VALUEs live ranges
927 // must not leak into later code.
928 DIVariable *Var = SD->getVariable();
929 const DIExpression *Expr =
930 DIExpression::convertToUndefExpression(Expr: SD->getExpression());
931 DebugLoc DL = SD->getDebugLoc();
932 const MCInstrDesc &Desc = TII->get(Opcode: TargetOpcode::DBG_VALUE);
933 return BuildMI(MF&: *MF, DL, MCID: Desc, IsIndirect: false, Reg: 0U, Variable: Var, Expr);
934}
935
936MachineInstr *
937InstrEmitter::EmitDbgValueList(SDDbgValue *SD,
938 VRBaseMapType &VRBaseMap) {
939 MDNode *Var = SD->getVariable();
940 DIExpression *Expr = SD->getExpression();
941 DebugLoc DL = SD->getDebugLoc();
942 // DBG_VALUE_LIST := "DBG_VALUE_LIST" var, expression, loc (, loc)*
943 const MCInstrDesc &DbgValDesc = TII->get(Opcode: TargetOpcode::DBG_VALUE_LIST);
944 // Build the DBG_VALUE_LIST instruction base.
945 auto MIB = BuildMI(MF&: *MF, MIMD: DL, MCID: DbgValDesc);
946 MIB.addMetadata(MD: Var);
947 MIB.addMetadata(MD: Expr);
948 AddDbgValueLocationOps(MIB, DbgValDesc, LocationOps: SD->getLocationOps(), VRBaseMap);
949 return &*MIB;
950}
951
952MachineInstr *
953InstrEmitter::EmitDbgValueFromSingleOp(SDDbgValue *SD,
954 VRBaseMapType &VRBaseMap) {
955 MDNode *Var = SD->getVariable();
956 DIExpression *Expr = SD->getExpression();
957 DebugLoc DL = SD->getDebugLoc();
958 const MCInstrDesc &II = TII->get(Opcode: TargetOpcode::DBG_VALUE);
959
960 assert(SD->getLocationOps().size() == 1 &&
961 "Non variadic dbg_value should have only one location op");
962
963 // See about constant-folding the expression.
964 // Copy the location operand in case we replace it.
965 SmallVector<SDDbgOperand, 1> LocationOps(1, SD->getLocationOps()[0]);
966 if (Expr && LocationOps[0].getKind() == SDDbgOperand::CONST) {
967 const Value *V = LocationOps[0].getConst();
968 if (auto *C = dyn_cast<ConstantInt>(Val: V)) {
969 std::tie(args&: Expr, args&: C) = Expr->constantFold(CI: C);
970 LocationOps[0] = SDDbgOperand::fromConst(Const: C);
971 }
972 }
973
974 // Emit non-variadic dbg_value nodes as DBG_VALUE.
975 // DBG_VALUE := "DBG_VALUE" loc, isIndirect, var, expr
976 auto MIB = BuildMI(MF&: *MF, MIMD: DL, MCID: II);
977 AddDbgValueLocationOps(MIB, DbgValDesc: II, LocationOps, VRBaseMap);
978
979 if (SD->isIndirect())
980 MIB.addImm(Val: 0U);
981 else
982 MIB.addReg(RegNo: 0U);
983
984 return MIB.addMetadata(MD: Var).addMetadata(MD: Expr);
985}
986
987MachineInstr *
988InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
989 MDNode *Label = SD->getLabel();
990 DebugLoc DL = SD->getDebugLoc();
991 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
992 "Expected inlined-at fields to agree");
993
994 const MCInstrDesc &II = TII->get(Opcode: TargetOpcode::DBG_LABEL);
995 MachineInstrBuilder MIB = BuildMI(MF&: *MF, MIMD: DL, MCID: II);
996 MIB.addMetadata(MD: Label);
997
998 return &*MIB;
999}
1000
1001/// EmitMachineNode - Generate machine code for a target-specific node and
1002/// needed dependencies.
1003///
1004void InstrEmitter::
1005EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
1006 VRBaseMapType &VRBaseMap) {
1007 unsigned Opc = Node->getMachineOpcode();
1008
1009 // Handle subreg insert/extract specially
1010 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
1011 Opc == TargetOpcode::INSERT_SUBREG ||
1012 Opc == TargetOpcode::SUBREG_TO_REG) {
1013 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
1014 return;
1015 }
1016
1017 // Handle COPY_TO_REGCLASS specially.
1018 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
1019 EmitCopyToRegClassNode(Node, VRBaseMap);
1020 return;
1021 }
1022
1023 // Handle REG_SEQUENCE specially.
1024 if (Opc == TargetOpcode::REG_SEQUENCE) {
1025 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
1026 return;
1027 }
1028
1029 if (Opc == TargetOpcode::IMPLICIT_DEF)
1030 // We want a unique VR for each IMPLICIT_DEF use.
1031 return;
1032
1033 const MCInstrDesc &II = TII->get(Opcode: Opc);
1034 unsigned NumResults = CountResults(Node);
1035 unsigned NumDefs = II.getNumDefs();
1036 const MCPhysReg *ScratchRegs = nullptr;
1037
1038 // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
1039 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
1040 // Stackmaps do not have arguments and do not preserve their calling
1041 // convention. However, to simplify runtime support, they clobber the same
1042 // scratch registers as AnyRegCC.
1043 unsigned CC = CallingConv::AnyReg;
1044 if (Opc == TargetOpcode::PATCHPOINT) {
1045 CC = Node->getConstantOperandVal(Num: PatchPointOpers::CCPos);
1046 NumDefs = NumResults;
1047 }
1048 ScratchRegs = TLI->getScratchRegisters(CC: (CallingConv::ID) CC);
1049 } else if (Opc == TargetOpcode::STATEPOINT) {
1050 NumDefs = NumResults;
1051 }
1052
1053 unsigned NumImpUses = 0;
1054 unsigned NodeOperands =
1055 countOperands(Node, NumExpUses: II.getNumOperands() - NumDefs, NumImpUses);
1056 bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
1057 II.isVariadic() && II.variadicOpsAreDefs();
1058 bool HasPhysRegOuts = NumResults > NumDefs && !II.implicit_defs().empty() &&
1059 !HasVRegVariadicDefs;
1060#ifndef NDEBUG
1061 unsigned NumMIOperands = NodeOperands + NumResults;
1062 if (II.isVariadic())
1063 assert(NumMIOperands >= II.getNumOperands() &&
1064 "Too few operands for a variadic node!");
1065 else
1066 assert(NumMIOperands >= II.getNumOperands() &&
1067 NumMIOperands <=
1068 II.getNumOperands() + II.implicit_defs().size() + NumImpUses &&
1069 "#operands for dag node doesn't match .td file!");
1070#endif
1071
1072 // Create the new machine instruction.
1073 MachineInstrBuilder MIB = BuildMI(MF&: *MF, MIMD: Node->getDebugLoc(), MCID: II);
1074
1075 // Transfer IR flags from the SDNode to the MachineInstr
1076 MachineInstr *MI = MIB.getInstr();
1077 const SDNodeFlags Flags = Node->getFlags();
1078 if (Flags.hasUnpredictable())
1079 MI->setFlag(MachineInstr::MIFlag::Unpredictable);
1080
1081 // Add result register values for things that are defined by this
1082 // instruction.
1083 if (NumResults) {
1084 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
1085
1086 if (Flags.hasNoSignedZeros())
1087 MI->setFlag(MachineInstr::MIFlag::FmNsz);
1088
1089 if (Flags.hasAllowReciprocal())
1090 MI->setFlag(MachineInstr::MIFlag::FmArcp);
1091
1092 if (Flags.hasNoNaNs())
1093 MI->setFlag(MachineInstr::MIFlag::FmNoNans);
1094
1095 if (Flags.hasNoInfs())
1096 MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
1097
1098 if (Flags.hasAllowContract())
1099 MI->setFlag(MachineInstr::MIFlag::FmContract);
1100
1101 if (Flags.hasApproximateFuncs())
1102 MI->setFlag(MachineInstr::MIFlag::FmAfn);
1103
1104 if (Flags.hasAllowReassociation())
1105 MI->setFlag(MachineInstr::MIFlag::FmReassoc);
1106
1107 if (Flags.hasNoUnsignedWrap())
1108 MI->setFlag(MachineInstr::MIFlag::NoUWrap);
1109
1110 if (Flags.hasNoSignedWrap())
1111 MI->setFlag(MachineInstr::MIFlag::NoSWrap);
1112
1113 if (Flags.hasExact())
1114 MI->setFlag(MachineInstr::MIFlag::IsExact);
1115
1116 if (Flags.hasNoFPExcept())
1117 MI->setFlag(MachineInstr::MIFlag::NoFPExcept);
1118
1119 if (Flags.hasDisjoint())
1120 MI->setFlag(MachineInstr::MIFlag::Disjoint);
1121
1122 if (Flags.hasSameSign())
1123 MI->setFlag(MachineInstr::MIFlag::SameSign);
1124
1125 if (Flags.hasNoConvergent())
1126 MI->setFlag(MachineInstr::MIFlag::NoConvergent);
1127 }
1128
1129 // Emit all of the actual operands of this instruction, adding them to the
1130 // instruction as appropriate.
1131 bool HasOptPRefs = NumDefs > NumResults;
1132 assert((!HasOptPRefs || !HasPhysRegOuts) &&
1133 "Unable to cope with optional defs and phys regs defs!");
1134 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
1135 for (unsigned i = NumSkip; i != NodeOperands; ++i)
1136 AddOperand(MIB, Op: Node->getOperand(Num: i), IIOpNum: i-NumSkip+NumDefs, II: &II,
1137 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
1138
1139 // Add scratch registers as implicit def and early clobber
1140 if (ScratchRegs)
1141 for (unsigned i = 0; ScratchRegs[i]; ++i)
1142 MIB.addReg(RegNo: ScratchRegs[i], Flags: RegState::ImplicitDefine |
1143 RegState::EarlyClobber);
1144
1145 // Set the memory reference descriptions of this instruction now that it is
1146 // part of the function.
1147 MIB.setMemRefs(cast<MachineSDNode>(Val: Node)->memoperands());
1148
1149 // Set the CFI type.
1150 MIB->setCFIType(MF&: *MF, Type: Node->getCFIType());
1151
1152 // Insert the instruction into position in the block. This needs to
1153 // happen before any custom inserter hook is called so that the
1154 // hook knows where in the block to insert the replacement code.
1155 MBB->insert(I: InsertPos, MI: MIB);
1156
1157 // The MachineInstr may also define physregs instead of virtregs. These
1158 // physreg values can reach other instructions in different ways:
1159 //
1160 // 1. When there is a use of a Node value beyond the explicitly defined
1161 // virtual registers, we emit a CopyFromReg for one of the implicitly
1162 // defined physregs. This only happens when HasPhysRegOuts is true.
1163 //
1164 // 2. A CopyFromReg reading a physreg may be glued to this instruction.
1165 //
1166 // 3. A glued instruction may implicitly use a physreg.
1167 //
1168 // 4. A glued instruction may use a RegisterSDNode operand.
1169 //
1170 // Collect all the used physreg defs, and make sure that any unused physreg
1171 // defs are marked as dead.
1172 SmallVector<Register, 8> UsedRegs;
1173
1174 // Additional results must be physical register defs.
1175 if (HasPhysRegOuts) {
1176 for (unsigned i = NumDefs; i < NumResults; ++i) {
1177 Register Reg = II.implicit_defs()[i - NumDefs];
1178 if (!Node->hasAnyUseOfValue(Value: i))
1179 continue;
1180 // This implicitly defined physreg has a use.
1181 UsedRegs.push_back(Elt: Reg);
1182 EmitCopyFromReg(Op: SDValue(Node, i), IsClone, SrcReg: Reg, VRBaseMap);
1183 }
1184 }
1185
1186 // Scan the glue chain for any used physregs.
1187 if (Node->getValueType(ResNo: Node->getNumValues()-1) == MVT::Glue) {
1188 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
1189 if (F->getOpcode() == ISD::CopyFromReg) {
1190 Register Reg = cast<RegisterSDNode>(Val: F->getOperand(Num: 1))->getReg();
1191 if (Reg.isPhysical())
1192 UsedRegs.push_back(Elt: Reg);
1193 continue;
1194 } else if (F->getOpcode() == ISD::CopyToReg) {
1195 // Skip CopyToReg nodes that are internal to the glue chain.
1196 continue;
1197 }
1198 // Collect declared implicit uses.
1199 const MCInstrDesc &MCID = TII->get(Opcode: F->getMachineOpcode());
1200 append_range(C&: UsedRegs, R: MCID.implicit_uses());
1201 // In addition to declared implicit uses, we must also check for
1202 // direct RegisterSDNode operands.
1203 for (const SDValue &Op : F->op_values())
1204 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Val: Op)) {
1205 Register Reg = R->getReg();
1206 if (Reg.isPhysical())
1207 UsedRegs.push_back(Elt: Reg);
1208 }
1209 }
1210 }
1211
1212 // Add rounding control registers as implicit def for function call.
1213 if (II.isCall() && MF->getFunction().hasFnAttribute(Kind: Attribute::StrictFP)) {
1214 ArrayRef<MCPhysReg> RCRegs = TLI->getRoundingControlRegisters();
1215 llvm::append_range(C&: UsedRegs, R&: RCRegs);
1216 }
1217
1218 // Finally mark unused registers as dead.
1219 if (!UsedRegs.empty() || !II.implicit_defs().empty() || II.hasOptionalDef())
1220 MIB->setPhysRegsDeadExcept(UsedRegs, TRI: *TRI);
1221
1222 // STATEPOINT is too 'dynamic' to have meaningful machine description.
1223 // We have to manually tie operands.
1224 if (Opc == TargetOpcode::STATEPOINT && NumDefs > 0) {
1225 assert(!HasPhysRegOuts && "STATEPOINT mishandled");
1226 MachineInstr *MI = MIB;
1227 unsigned Def = 0;
1228 int First = StatepointOpers(MI).getFirstGCPtrIdx();
1229 assert(First > 0 && "Statepoint has Defs but no GC ptr list");
1230 unsigned Use = (unsigned)First;
1231 while (Def < NumDefs) {
1232 if (MI->getOperand(i: Use).isReg())
1233 MI->tieOperands(DefIdx: Def++, UseIdx: Use);
1234 Use = StackMaps::getNextMetaArgIdx(MI, CurIdx: Use);
1235 }
1236 }
1237
1238 unsigned Op = Node->getNumOperands();
1239 if (Op != 0 && Node->getOperand(Num: Op - 1)->getOpcode() ==
1240 ~(unsigned)TargetOpcode::CONVERGENCECTRL_GLUE) {
1241 Register VReg = getVR(Op: Node->getOperand(Num: Op - 1)->getOperand(Num: 0), VRBaseMap);
1242 MachineOperand MO = MachineOperand::CreateReg(Reg: VReg, /*isDef=*/false,
1243 /*isImp=*/true);
1244 MIB->addOperand(Op: MO);
1245 Op--;
1246 }
1247
1248 if (Op != 0 &&
1249 Node->getOperand(Num: Op - 1)->getOpcode() == ISD::DEACTIVATION_SYMBOL) {
1250 MI->setDeactivationSymbol(
1251 MF&: *MF, DS: const_cast<GlobalValue *>(
1252 cast<DeactivationSymbolSDNode>(Val: Node->getOperand(Num: Op - 1))
1253 ->getGlobal()));
1254 Op--;
1255 }
1256
1257 // Run post-isel target hook to adjust this instruction if needed.
1258 if (II.hasPostISelHook())
1259 TLI->AdjustInstrPostInstrSelection(MI&: *MIB, Node);
1260}
1261
1262/// EmitSpecialNode - Generate machine code for a target-independent node and
1263/// needed dependencies.
1264void InstrEmitter::
1265EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
1266 VRBaseMapType &VRBaseMap) {
1267 switch (Node->getOpcode()) {
1268 default:
1269#ifndef NDEBUG
1270 Node->dump();
1271#endif
1272 llvm_unreachable("This target-independent node should have been selected!");
1273 case ISD::EntryToken:
1274 case ISD::MERGE_VALUES:
1275 case ISD::TokenFactor:
1276 case ISD::DEACTIVATION_SYMBOL:
1277 break;
1278 case ISD::CopyToReg: {
1279 Register DestReg = cast<RegisterSDNode>(Val: Node->getOperand(Num: 1))->getReg();
1280 SDValue SrcVal = Node->getOperand(Num: 2);
1281 if (DestReg.isVirtual() && SrcVal.isMachineOpcode() &&
1282 SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
1283 // Instead building a COPY to that vreg destination, build an
1284 // IMPLICIT_DEF instruction instead.
1285 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Node->getDebugLoc(),
1286 MCID: TII->get(Opcode: TargetOpcode::IMPLICIT_DEF), DestReg);
1287 break;
1288 }
1289 Register SrcReg;
1290 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Val&: SrcVal))
1291 SrcReg = R->getReg();
1292 else
1293 SrcReg = getVR(Op: SrcVal, VRBaseMap);
1294
1295 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1296 break;
1297
1298 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Node->getDebugLoc(), MCID: TII->get(Opcode: TargetOpcode::COPY),
1299 DestReg).addReg(RegNo: SrcReg);
1300 break;
1301 }
1302 case ISD::CopyFromReg: {
1303 Register SrcReg = cast<RegisterSDNode>(Val: Node->getOperand(Num: 1))->getReg();
1304 EmitCopyFromReg(Op: SDValue(Node, 0), IsClone, SrcReg, VRBaseMap);
1305 break;
1306 }
1307 case ISD::EH_LABEL:
1308 case ISD::ANNOTATION_LABEL: {
1309 unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1310 ? TargetOpcode::EH_LABEL
1311 : TargetOpcode::ANNOTATION_LABEL;
1312 MCSymbol *S = cast<LabelSDNode>(Val: Node)->getLabel();
1313 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Node->getDebugLoc(),
1314 MCID: TII->get(Opcode: Opc)).addSym(Sym: S);
1315 break;
1316 }
1317
1318 case ISD::LIFETIME_START:
1319 case ISD::LIFETIME_END: {
1320 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START)
1321 ? TargetOpcode::LIFETIME_START
1322 : TargetOpcode::LIFETIME_END;
1323 auto *FI = cast<FrameIndexSDNode>(Val: Node->getOperand(Num: 1));
1324 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Node->getDebugLoc(), MCID: TII->get(Opcode: TarOp))
1325 .addFrameIndex(Idx: FI->getIndex());
1326 break;
1327 }
1328
1329 case ISD::PSEUDO_PROBE: {
1330 unsigned TarOp = TargetOpcode::PSEUDO_PROBE;
1331 auto Guid = cast<PseudoProbeSDNode>(Val: Node)->getGuid();
1332 auto Index = cast<PseudoProbeSDNode>(Val: Node)->getIndex();
1333 auto Attr = cast<PseudoProbeSDNode>(Val: Node)->getAttributes();
1334
1335 BuildMI(BB&: *MBB, I: InsertPos, MIMD: Node->getDebugLoc(), MCID: TII->get(Opcode: TarOp))
1336 .addImm(Val: Guid)
1337 .addImm(Val: Index)
1338 .addImm(Val: (uint8_t)PseudoProbeType::Block)
1339 .addImm(Val: Attr);
1340 break;
1341 }
1342
1343 case ISD::INLINEASM:
1344 case ISD::INLINEASM_BR: {
1345 unsigned NumOps = Node->getNumOperands();
1346 if (Node->getOperand(Num: NumOps-1).getValueType() == MVT::Glue)
1347 --NumOps; // Ignore the glue operand.
1348
1349 // Create the inline asm machine instruction.
1350 unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1351 ? TargetOpcode::INLINEASM_BR
1352 : TargetOpcode::INLINEASM;
1353 MachineInstrBuilder MIB =
1354 BuildMI(MF&: *MF, MIMD: Node->getDebugLoc(), MCID: TII->get(Opcode: TgtOpc));
1355
1356 // Add the asm string as an external symbol operand.
1357 SDValue AsmStrV = Node->getOperand(Num: InlineAsm::Op_AsmString);
1358 const char *AsmStr = cast<ExternalSymbolSDNode>(Val&: AsmStrV)->getSymbol();
1359 MIB.addExternalSymbol(FnName: AsmStr);
1360
1361 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1362 // bits.
1363 int64_t ExtraInfo =
1364 cast<ConstantSDNode>(Val: Node->getOperand(Num: InlineAsm::Op_ExtraInfo))->
1365 getZExtValue();
1366 MIB.addImm(Val: ExtraInfo);
1367
1368 // Remember to operand index of the group flags.
1369 SmallVector<unsigned, 8> GroupIdx;
1370
1371 // Remember registers that are part of early-clobber defs.
1372 SmallVector<Register, 8> ECRegs;
1373
1374 // Add all of the operand registers to the instruction.
1375 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1376 unsigned Flags = Node->getConstantOperandVal(Num: i);
1377 const InlineAsm::Flag F(Flags);
1378 const unsigned NumVals = F.getNumOperandRegisters();
1379
1380 GroupIdx.push_back(Elt: MIB->getNumOperands());
1381 MIB.addImm(Val: Flags);
1382 ++i; // Skip the ID value.
1383
1384 switch (F.getKind()) {
1385 case InlineAsm::Kind::RegDef:
1386 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1387 Register Reg = cast<RegisterSDNode>(Val: Node->getOperand(Num: i))->getReg();
1388 // FIXME: Add dead flags for physical and virtual registers defined.
1389 // For now, mark physical register defs as implicit to help fast
1390 // regalloc. This makes inline asm look a lot like calls.
1391 MIB.addReg(RegNo: Reg, Flags: RegState::Define | getImplRegState(B: Reg.isPhysical()));
1392 }
1393 break;
1394 case InlineAsm::Kind::RegDefEarlyClobber:
1395 case InlineAsm::Kind::Clobber:
1396 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1397 Register Reg = cast<RegisterSDNode>(Val: Node->getOperand(Num: i))->getReg();
1398 MIB.addReg(RegNo: Reg, Flags: RegState::Define | RegState::EarlyClobber |
1399 getImplRegState(B: Reg.isPhysical()));
1400 ECRegs.push_back(Elt: Reg);
1401 }
1402 break;
1403 case InlineAsm::Kind::RegUse: // Use of register.
1404 case InlineAsm::Kind::Imm: // Immediate.
1405 case InlineAsm::Kind::Mem: // Non-function addressing mode.
1406 // The addressing mode has been selected, just add all of the
1407 // operands to the machine instruction.
1408 for (unsigned j = 0; j != NumVals; ++j, ++i)
1409 AddOperand(MIB, Op: Node->getOperand(Num: i), IIOpNum: 0, II: nullptr, VRBaseMap,
1410 /*IsDebug=*/false, IsClone, IsCloned);
1411
1412 // Manually set isTied bits.
1413 if (F.isRegUseKind()) {
1414 unsigned DefGroup;
1415 if (F.isUseOperandTiedToDef(Idx&: DefGroup)) {
1416 unsigned DefIdx = GroupIdx[DefGroup] + 1;
1417 unsigned UseIdx = GroupIdx.back() + 1;
1418 for (unsigned j = 0; j != NumVals; ++j)
1419 MIB->tieOperands(DefIdx: DefIdx + j, UseIdx: UseIdx + j);
1420 }
1421 }
1422 break;
1423 case InlineAsm::Kind::Func: // Function addressing mode.
1424 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1425 SDValue Op = Node->getOperand(Num: i);
1426 AddOperand(MIB, Op, IIOpNum: 0, II: nullptr, VRBaseMap,
1427 /*IsDebug=*/false, IsClone, IsCloned);
1428
1429 // Adjust Target Flags for function reference.
1430 if (auto *TGA = dyn_cast<GlobalAddressSDNode>(Val&: Op)) {
1431 unsigned NewFlags =
1432 MF->getSubtarget().classifyGlobalFunctionReference(
1433 GV: TGA->getGlobal());
1434 unsigned LastIdx = MIB.getInstr()->getNumOperands() - 1;
1435 MIB.getInstr()->getOperand(i: LastIdx).setTargetFlags(NewFlags);
1436 }
1437 }
1438 }
1439 }
1440
1441 // GCC inline assembly allows input operands to also be early-clobber
1442 // output operands (so long as the operand is written only after it's
1443 // used), but this does not match the semantics of our early-clobber flag.
1444 // If an early-clobber operand register is also an input operand register,
1445 // then remove the early-clobber flag.
1446 for (Register Reg : ECRegs) {
1447 if (MIB->readsRegister(Reg, TRI)) {
1448 MachineOperand *MO =
1449 MIB->findRegisterDefOperand(Reg, TRI, isDead: false, Overlap: false);
1450 assert(MO && "No def operand for clobbered register?");
1451 MO->setIsEarlyClobber(false);
1452 }
1453 }
1454
1455 // Get the mdnode from the asm if it exists and add it to the instruction.
1456 SDValue MDV = Node->getOperand(Num: InlineAsm::Op_MDNode);
1457 const MDNode *MD = cast<MDNodeSDNode>(Val&: MDV)->getMD();
1458 if (MD)
1459 MIB.addMetadata(MD);
1460
1461 // Add rounding control registers as implicit def for inline asm.
1462 if (MF->getFunction().hasFnAttribute(Kind: Attribute::StrictFP)) {
1463 ArrayRef<MCPhysReg> RCRegs = TLI->getRoundingControlRegisters();
1464 for (MCPhysReg Reg : RCRegs)
1465 MIB.addReg(RegNo: Reg, Flags: RegState::ImplicitDefine);
1466 }
1467
1468 MBB->insert(I: InsertPos, MI: MIB);
1469 break;
1470 }
1471 }
1472}
1473
1474/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1475/// at the given position in the given block.
1476InstrEmitter::InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb,
1477 MachineBasicBlock::iterator insertpos)
1478 : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1479 TII(MF->getSubtarget().getInstrInfo()),
1480 TRI(MF->getSubtarget().getRegisterInfo()),
1481 TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1482 InsertPos(insertpos) {
1483 EmitDebugInstrRefs = mbb->getParent()->useDebugInstrRef();
1484}
1485