1//===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the ScheduleDAG class, which is a base class used by
10// scheduling implementation classes.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ScheduleDAGSDNodes.h"
15#include "InstrEmitter.h"
16#include "SDNodeDbgValue.h"
17#include "llvm/ADT/DenseMap.h"
18#include "llvm/ADT/SmallPtrSet.h"
19#include "llvm/ADT/SmallSet.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/ADT/Statistic.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/SelectionDAG.h"
25#include "llvm/CodeGen/TargetInstrInfo.h"
26#include "llvm/CodeGen/TargetLowering.h"
27#include "llvm/CodeGen/TargetRegisterInfo.h"
28#include "llvm/CodeGen/TargetSubtargetInfo.h"
29#include "llvm/Config/llvm-config.h"
30#include "llvm/IR/MemoryModelRelaxationAnnotations.h"
31#include "llvm/MC/MCInstrItineraries.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetMachine.h"
36using namespace llvm;
37
38#define DEBUG_TYPE "pre-RA-sched"
39
40STATISTIC(LoadsClustered, "Number of loads clustered together");
41
42// This allows the latency-based scheduler to notice high latency instructions
43// without a target itinerary. The choice of number here has more to do with
44// balancing scheduler heuristics than with the actual machine latency.
45static cl::opt<int> HighLatencyCycles(
46 "sched-high-latency-cycles", cl::Hidden, cl::init(Val: 10),
47 cl::desc("Roughly estimate the number of cycles that 'long latency' "
48 "instructions take for targets with no itinerary"));
49
50ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
51 : ScheduleDAG(mf), InstrItins(mf.getSubtarget().getInstrItineraryData()) {}
52
53/// Run - perform scheduling.
54///
55void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb) {
56 BB = bb;
57 DAG = dag;
58
59 // Clear the scheduler's SUnit DAG.
60 ScheduleDAG::clearDAG();
61 Sequence.clear();
62
63 // Invoke the target's selection of scheduler.
64 Schedule();
65}
66
67/// NewSUnit - Creates a new SUnit and return a ptr to it.
68///
69SUnit *ScheduleDAGSDNodes::newSUnit(SDNode *N) {
70#ifndef NDEBUG
71 const SUnit *Addr = nullptr;
72 if (!SUnits.empty())
73 Addr = &SUnits[0];
74#endif
75 SUnits.emplace_back(args&: N, args: (unsigned)SUnits.size());
76 assert((Addr == nullptr || Addr == &SUnits[0]) &&
77 "SUnits std::vector reallocated on the fly!");
78 SUnits.back().OrigNode = &SUnits.back();
79 SUnit *SU = &SUnits.back();
80 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
81 if (!N ||
82 (N->isMachineOpcode() &&
83 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
84 SU->SchedulingPref = Sched::None;
85 else
86 SU->SchedulingPref = TLI.getSchedulingPreference(N);
87 return SU;
88}
89
90SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
91 SUnit *SU = newSUnit(N: Old->getNode());
92 SU->OrigNode = Old->OrigNode;
93 SU->Latency = Old->Latency;
94 SU->isVRegCycle = Old->isVRegCycle;
95 SU->isCall = Old->isCall;
96 SU->isCallOp = Old->isCallOp;
97 SU->isTwoAddress = Old->isTwoAddress;
98 SU->isCommutable = Old->isCommutable;
99 SU->hasPhysRegDefs = Old->hasPhysRegDefs;
100 SU->hasPhysRegClobbers = Old->hasPhysRegClobbers;
101 SU->isScheduleHigh = Old->isScheduleHigh;
102 SU->isScheduleLow = Old->isScheduleLow;
103 SU->SchedulingPref = Old->SchedulingPref;
104 Old->isCloned = true;
105 return SU;
106}
107
108/// CheckForPhysRegDependency - Check if the dependency between def and use of
109/// a specified operand is a physical register dependency. If so, returns the
110/// register and the cost of copying the register.
111static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
112 const TargetRegisterInfo *TRI,
113 const TargetInstrInfo *TII,
114 MCRegister &PhysReg, int &Cost) {
115 if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
116 return;
117
118 Register Reg = cast<RegisterSDNode>(Val: User->getOperand(Num: 1))->getReg();
119 if (Reg.isVirtual())
120 return;
121
122 unsigned ResNo = User->getOperand(Num: 2).getResNo();
123 if (Def->getOpcode() == ISD::CopyFromReg &&
124 cast<RegisterSDNode>(Val: Def->getOperand(Num: 1))->getReg() == Reg) {
125 PhysReg = Reg;
126 } else if (Def->isMachineOpcode()) {
127 const MCInstrDesc &II = TII->get(Opcode: Def->getMachineOpcode());
128 if (ResNo >= II.getNumDefs() && II.hasImplicitDefOfPhysReg(Reg))
129 PhysReg = Reg;
130 }
131
132 if (PhysReg) {
133 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
134 Cost = RC->expensiveOrImpossibleToCopy() ? -1 : RC->getCopyCost();
135 }
136}
137
138// Helper for AddGlue to clone node operands.
139static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef<EVT> VTs,
140 SDValue ExtraOper = SDValue()) {
141 SmallVector<SDValue, 8> Ops(N->ops());
142 if (ExtraOper.getNode())
143 Ops.push_back(Elt: ExtraOper);
144
145 SDVTList VTList = DAG->getVTList(VTs);
146 MachineSDNode *MN = dyn_cast<MachineSDNode>(Val: N);
147
148 // Store memory references.
149 SmallVector<MachineMemOperand *, 2> MMOs;
150 if (MN)
151 MMOs.assign(in_start: MN->memoperands_begin(), in_end: MN->memoperands_end());
152
153 DAG->MorphNodeTo(N, Opc: N->getOpcode(), VTs: VTList, Ops);
154
155 // Reset the memory references
156 if (MN)
157 DAG->setNodeMemRefs(N: MN, NewMemRefs: MMOs);
158}
159
160static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) {
161 SDNode *GlueDestNode = Glue.getNode();
162
163 // Don't add glue from a node to itself.
164 if (GlueDestNode == N) return false;
165
166 // Don't add a glue operand to something that already uses glue.
167 if (GlueDestNode &&
168 N->getOperand(Num: N->getNumOperands()-1).getValueType() == MVT::Glue) {
169 return false;
170 }
171 // Don't add glue to something that already has a glue value.
172 if (N->getValueType(ResNo: N->getNumValues() - 1) == MVT::Glue) return false;
173
174 SmallVector<EVT, 4> VTs(N->values());
175 if (AddGlue)
176 VTs.push_back(Elt: MVT::Glue);
177
178 CloneNodeWithValues(N, DAG, VTs, ExtraOper: Glue);
179
180 return true;
181}
182
183// Cleanup after unsuccessful AddGlue. Use the standard method of morphing the
184// node even though simply shrinking the value list is sufficient.
185static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) {
186 assert((N->getValueType(N->getNumValues() - 1) == MVT::Glue &&
187 !N->hasAnyUseOfValue(N->getNumValues() - 1)) &&
188 "expected an unused glue value");
189
190 CloneNodeWithValues(N, DAG,
191 VTs: ArrayRef(N->value_begin(), N->getNumValues() - 1));
192}
193
194/// ClusterNeighboringLoads - Force nearby loads together by "gluing" them.
195/// This function finds loads of the same base and different offsets. If the
196/// offsets are not far apart (target specific), it add MVT::Glue inputs and
197/// outputs to ensure they are scheduled together and in order. This
198/// optimization may benefit some targets by improving cache locality.
199void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
200 SDValue Chain;
201 unsigned NumOps = Node->getNumOperands();
202 if (Node->getOperand(Num: NumOps-1).getValueType() == MVT::Other)
203 Chain = Node->getOperand(Num: NumOps-1);
204 if (!Chain)
205 return;
206
207 // Skip any load instruction that has a tied input. There may be an additional
208 // dependency requiring a different order than by increasing offsets, and the
209 // added glue may introduce a cycle.
210 auto hasTiedInput = [this](const SDNode *N) {
211 const MCInstrDesc &MCID = TII->get(Opcode: N->getMachineOpcode());
212 for (unsigned I = 0; I != MCID.getNumOperands(); ++I) {
213 if (MCID.getOperandConstraint(OpNum: I, Constraint: MCOI::TIED_TO) != -1)
214 return true;
215 }
216
217 return false;
218 };
219
220 // Look for other loads of the same chain. Find loads that are loading from
221 // the same base pointer and different offsets.
222 SmallPtrSet<SDNode*, 16> Visited;
223 SmallVector<int64_t, 4> Offsets;
224 DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode.
225 bool Cluster = false;
226 SDNode *Base = Node;
227
228 if (hasTiedInput(Base))
229 return;
230
231 // This algorithm requires a reasonably low use count before finding a match
232 // to avoid uselessly blowing up compile time in large blocks.
233 unsigned UseCount = 0;
234 for (SDNode::user_iterator I = Chain->user_begin(), E = Chain->user_end();
235 I != E && UseCount < 100; ++I, ++UseCount) {
236 if (I.getUse().getResNo() != Chain.getResNo())
237 continue;
238
239 SDNode *User = *I;
240 if (User == Node || !Visited.insert(Ptr: User).second)
241 continue;
242 int64_t Offset1, Offset2;
243 if (!TII->areLoadsFromSameBasePtr(Load1: Base, Load2: User, Offset1, Offset2) ||
244 Offset1 == Offset2 ||
245 hasTiedInput(User)) {
246 // FIXME: Should be ok if they addresses are identical. But earlier
247 // optimizations really should have eliminated one of the loads.
248 continue;
249 }
250 if (O2SMap.insert(KV: std::make_pair(x&: Offset1, y&: Base)).second)
251 Offsets.push_back(Elt: Offset1);
252 O2SMap.insert(KV: std::make_pair(x&: Offset2, y&: User));
253 Offsets.push_back(Elt: Offset2);
254 if (Offset2 < Offset1)
255 Base = User;
256 Cluster = true;
257 // Reset UseCount to allow more matches.
258 UseCount = 0;
259 }
260
261 if (!Cluster)
262 return;
263
264 // Sort them in increasing order.
265 llvm::sort(C&: Offsets);
266
267 // Check if the loads are close enough.
268 SmallVector<SDNode*, 4> Loads;
269 unsigned NumLoads = 0;
270 int64_t BaseOff = Offsets[0];
271 SDNode *BaseLoad = O2SMap[BaseOff];
272 Loads.push_back(Elt: BaseLoad);
273 for (unsigned i = 1, e = Offsets.size(); i != e; ++i) {
274 int64_t Offset = Offsets[i];
275 SDNode *Load = O2SMap[Offset];
276 if (!TII->shouldScheduleLoadsNear(Load1: BaseLoad, Load2: Load, Offset1: BaseOff, Offset2: Offset,NumLoads))
277 break; // Stop right here. Ignore loads that are further away.
278 Loads.push_back(Elt: Load);
279 ++NumLoads;
280 }
281
282 if (NumLoads == 0)
283 return;
284
285 // Cluster loads by adding MVT::Glue outputs and inputs. This also
286 // ensure they are scheduled in order of increasing addresses.
287 SDNode *Lead = Loads[0];
288 SDValue InGlue;
289 if (AddGlue(N: Lead, Glue: InGlue, AddGlue: true, DAG))
290 InGlue = SDValue(Lead, Lead->getNumValues() - 1);
291 for (unsigned I = 1, E = Loads.size(); I != E; ++I) {
292 bool OutGlue = I < E - 1;
293 SDNode *Load = Loads[I];
294
295 // If AddGlue fails, we could leave an unsused glue value. This should not
296 // cause any
297 if (AddGlue(N: Load, Glue: InGlue, AddGlue: OutGlue, DAG)) {
298 if (OutGlue)
299 InGlue = SDValue(Load, Load->getNumValues() - 1);
300
301 ++LoadsClustered;
302 }
303 else if (!OutGlue && InGlue.getNode())
304 RemoveUnusedGlue(N: InGlue.getNode(), DAG);
305 }
306}
307
308/// ClusterNodes - Cluster certain nodes which should be scheduled together.
309///
310void ScheduleDAGSDNodes::ClusterNodes() {
311 for (SDNode &NI : DAG->allnodes()) {
312 SDNode *Node = &NI;
313 if (!Node || !Node->isMachineOpcode())
314 continue;
315
316 unsigned Opc = Node->getMachineOpcode();
317 const MCInstrDesc &MCID = TII->get(Opcode: Opc);
318 if (MCID.mayLoad())
319 // Cluster loads from "near" addresses into combined SUnits.
320 ClusterNeighboringLoads(Node);
321 }
322}
323
324void ScheduleDAGSDNodes::BuildSchedUnits() {
325 // During scheduling, the NodeId field of SDNode is used to map SDNodes
326 // to their associated SUnits by holding SUnits table indices. A value
327 // of -1 means the SDNode does not yet have an associated SUnit.
328 unsigned NumNodes = 0;
329 for (SDNode &NI : DAG->allnodes()) {
330 NI.setNodeId(-1);
331 NI.setSchedulerWorklistVisited(false);
332 ++NumNodes;
333 }
334
335 // Reserve entries in the vector for each of the SUnits we are creating. This
336 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
337 // invalidated.
338 // FIXME: Multiply by 2 because we may clone nodes during scheduling.
339 // This is a temporary workaround.
340 SUnits.reserve(n: NumNodes * 2);
341
342 // Add all nodes in depth first order.
343 SmallVector<SDNode*, 64> Worklist;
344 SmallPtrSet<SDNode*, 32> Visited;
345 Worklist.push_back(Elt: DAG->getRoot().getNode());
346 DAG->getRoot().getNode()->setSchedulerWorklistVisited(true);
347
348 SmallVector<SUnit*, 8> CallSUnits;
349 while (!Worklist.empty()) {
350 SDNode *NI = Worklist.pop_back_val();
351
352 // Add all operands to the worklist unless they've already been added.
353 for (const SDValue &Op : NI->op_values()) {
354 if (Op.getNode()->getSchedulerWorklistVisited())
355 continue;
356 Op.getNode()->setSchedulerWorklistVisited(true);
357 Worklist.push_back(Elt: Op.getNode());
358 }
359
360 if (isPassiveNode(Node: NI)) // Leaf node, e.g. a TargetImmediate.
361 continue;
362
363 // If this node has already been processed, stop now.
364 if (NI->getNodeId() != -1) continue;
365
366 SUnit *NodeSUnit = newSUnit(N: NI);
367
368 // See if anything is glued to this node, if so, add them to glued
369 // nodes. Nodes can have at most one glue input and one glue output. Glue
370 // is required to be the last operand and result of a node.
371
372 // Scan up to find glued preds.
373 SDNode *N = NI;
374 while (N->getNumOperands() &&
375 N->getOperand(Num: N->getNumOperands()-1).getValueType() == MVT::Glue) {
376 N = N->getOperand(Num: N->getNumOperands()-1).getNode();
377 assert(N->getNodeId() == -1 && "Node already inserted!");
378 N->setNodeId(NodeSUnit->NodeNum);
379 if (N->isMachineOpcode() && TII->get(Opcode: N->getMachineOpcode()).isCall())
380 NodeSUnit->isCall = true;
381 }
382
383 // Scan down to find any glued succs.
384 N = NI;
385 while (N->getValueType(ResNo: N->getNumValues()-1) == MVT::Glue) {
386 SDValue GlueVal(N, N->getNumValues()-1);
387
388 // There are either zero or one users of the Glue result.
389 bool HasGlueUse = false;
390 for (SDNode *U : N->users())
391 if (GlueVal.isOperandOf(N: U)) {
392 HasGlueUse = true;
393 assert(N->getNodeId() == -1 && "Node already inserted!");
394 N->setNodeId(NodeSUnit->NodeNum);
395 N = U;
396 if (N->isMachineOpcode() && TII->get(Opcode: N->getMachineOpcode()).isCall())
397 NodeSUnit->isCall = true;
398 break;
399 }
400 if (!HasGlueUse) break;
401 }
402
403 if (NodeSUnit->isCall)
404 CallSUnits.push_back(Elt: NodeSUnit);
405
406 // Schedule zero-latency TokenFactor below any nodes that may increase the
407 // schedule height. Otherwise, ancestors of the TokenFactor may appear to
408 // have false stalls.
409 if (NI->getOpcode() == ISD::TokenFactor)
410 NodeSUnit->isScheduleLow = true;
411
412 // If there are glue operands involved, N is now the bottom-most node
413 // of the sequence of nodes that are glued together.
414 // Update the SUnit.
415 NodeSUnit->setNode(N);
416 assert(N->getNodeId() == -1 && "Node already inserted!");
417 N->setNodeId(NodeSUnit->NodeNum);
418
419 // Compute NumRegDefsLeft. This must be done before AddSchedEdges.
420 InitNumRegDefsLeft(SU: NodeSUnit);
421
422 // Assign the Latency field of NodeSUnit using target-provided information.
423 computeLatency(SU: NodeSUnit);
424 }
425
426 // Find all call operands.
427 while (!CallSUnits.empty()) {
428 SUnit *SU = CallSUnits.pop_back_val();
429 for (const SDNode *SUNode = SU->getNode(); SUNode;
430 SUNode = SUNode->getGluedNode()) {
431 if (SUNode->getOpcode() != ISD::CopyToReg)
432 continue;
433 SDNode *SrcN = SUNode->getOperand(Num: 2).getNode();
434 if (isPassiveNode(Node: SrcN)) continue; // Not scheduled.
435 SUnit *SrcSU = &SUnits[SrcN->getNodeId()];
436 SrcSU->isCallOp = true;
437 }
438 }
439}
440
441void ScheduleDAGSDNodes::AddSchedEdges() {
442 const TargetSubtargetInfo &ST = MF.getSubtarget();
443
444 // Check to see if the scheduler cares about latencies.
445 bool UnitLatencies = forceUnitLatencies();
446
447 // Pass 2: add the preds, succs, etc.
448 for (SUnit &SU : SUnits) {
449 SDNode *MainNode = SU.getNode();
450
451 if (MainNode->isMachineOpcode()) {
452 unsigned Opc = MainNode->getMachineOpcode();
453 const MCInstrDesc &MCID = TII->get(Opcode: Opc);
454 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
455 if (MCID.getOperandConstraint(OpNum: i, Constraint: MCOI::TIED_TO) != -1) {
456 SU.isTwoAddress = true;
457 break;
458 }
459 }
460 if (MCID.isCommutable())
461 SU.isCommutable = true;
462 }
463
464 // Find all predecessors and successors of the group.
465 for (SDNode *N = SU.getNode(); N; N = N->getGluedNode()) {
466 if (N->isMachineOpcode() &&
467 !TII->get(Opcode: N->getMachineOpcode()).implicit_defs().empty()) {
468 SU.hasPhysRegClobbers = true;
469 unsigned NumUsed = InstrEmitter::CountResults(Node: N);
470 while (NumUsed != 0 && !N->hasAnyUseOfValue(Value: NumUsed - 1))
471 --NumUsed; // Skip over unused values at the end.
472 if (NumUsed > TII->get(Opcode: N->getMachineOpcode()).getNumDefs())
473 SU.hasPhysRegDefs = true;
474 }
475
476 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
477 SDNode *OpN = N->getOperand(Num: i).getNode();
478 unsigned DefIdx = N->getOperand(Num: i).getResNo();
479 if (isPassiveNode(Node: OpN)) continue; // Not scheduled.
480 SUnit *OpSU = &SUnits[OpN->getNodeId()];
481 assert(OpSU && "Node has no SUnit!");
482 if (OpSU == &SU)
483 continue; // In the same group.
484
485 EVT OpVT = N->getOperand(Num: i).getValueType();
486 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
487 bool isChain = OpVT == MVT::Other;
488
489 MCRegister PhysReg;
490 int Cost = 1;
491 // Determine if this is a physical register dependency.
492 CheckForPhysRegDependency(Def: OpN, User: N, Op: i, TRI, TII, PhysReg, Cost);
493 assert((!PhysReg || !isChain) && "Chain dependence via physreg data?");
494 // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
495 // emits a copy from the physical register to a virtual register unless
496 // it requires a cross class copy (cost < 0). That means we are only
497 // treating "expensive to copy" register dependency as physical register
498 // dependency. This may change in the future though.
499 if (Cost >= 0 && !StressSched)
500 PhysReg = MCRegister();
501
502 // If this is a ctrl dep, latency is 1.
503 unsigned OpLatency = isChain ? 1 : OpSU->Latency;
504 // Special-case TokenFactor chains as zero-latency.
505 if(isChain && OpN->getOpcode() == ISD::TokenFactor)
506 OpLatency = 0;
507
508 SDep Dep = isChain ? SDep(OpSU, SDep::Barrier)
509 : SDep(OpSU, SDep::Data, PhysReg);
510 Dep.setLatency(OpLatency);
511 if (!isChain && !UnitLatencies) {
512 computeOperandLatency(Def: OpN, Use: N, OpIdx: i, dep&: Dep);
513 ST.adjustSchedDependency(Def: OpSU, DefOpIdx: DefIdx, Use: &SU, UseOpIdx: i, Dep, SchedModel: nullptr);
514 }
515
516 if (!SU.addPred(D: Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) {
517 // Multiple register uses are combined in the same SUnit. For example,
518 // we could have a set of glued nodes with all their defs consumed by
519 // another set of glued nodes. Register pressure tracking sees this as
520 // a single use, so to keep pressure balanced we reduce the defs.
521 //
522 // We can't tell (without more book-keeping) if this results from
523 // glued nodes or duplicate operands. As long as we don't reduce
524 // NumRegDefsLeft to zero, we handle the common cases well.
525 --OpSU->NumRegDefsLeft;
526 }
527 }
528 }
529 }
530}
531
532/// BuildSchedGraph - Build the SUnit graph from the selection dag that we
533/// are input. This SUnit graph is similar to the SelectionDAG, but
534/// excludes nodes that aren't interesting to scheduling, and represents
535/// glued together nodes with a single SUnit.
536void ScheduleDAGSDNodes::BuildSchedGraph() {
537 // Cluster certain nodes which should be scheduled together.
538 ClusterNodes();
539 // Populate the SUnits array.
540 BuildSchedUnits();
541 // Compute all the scheduling dependencies between nodes.
542 AddSchedEdges();
543}
544
545// Initialize NumNodeDefs for the current Node's opcode.
546void ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() {
547 // Check for phys reg copy.
548 if (!Node)
549 return;
550
551 if (!Node->isMachineOpcode()) {
552 if (Node->getOpcode() == ISD::CopyFromReg)
553 NodeNumDefs = 1;
554 else
555 NodeNumDefs = 0;
556 return;
557 }
558 unsigned POpc = Node->getMachineOpcode();
559 if (POpc == TargetOpcode::IMPLICIT_DEF) {
560 // No register need be allocated for this.
561 NodeNumDefs = 0;
562 return;
563 }
564 if (POpc == TargetOpcode::PATCHPOINT &&
565 Node->getValueType(ResNo: 0) == MVT::Other) {
566 // PATCHPOINT is defined to have one result, but it might really have none
567 // if we're not using CallingConv::AnyReg. Don't mistake the chain for a
568 // real definition.
569 NodeNumDefs = 0;
570 return;
571 }
572 unsigned NRegDefs = SchedDAG->TII->get(Opcode: Node->getMachineOpcode()).getNumDefs();
573 // Some instructions define regs that are not represented in the selection DAG
574 // (e.g. unused flags). See tMOVi8. Make sure we don't access past NumValues.
575 NodeNumDefs = std::min(a: Node->getNumValues(), b: NRegDefs);
576 DefIdx = 0;
577}
578
579// Construct a RegDefIter for this SUnit and find the first valid value.
580ScheduleDAGSDNodes::RegDefIter::RegDefIter(const SUnit *SU,
581 const ScheduleDAGSDNodes *SD)
582 : SchedDAG(SD), Node(SU->getNode()) {
583 InitNodeNumDefs();
584 Advance();
585}
586
587// Advance to the next valid value defined by the SUnit.
588void ScheduleDAGSDNodes::RegDefIter::Advance() {
589 for (;Node;) { // Visit all glued nodes.
590 for (;DefIdx < NodeNumDefs; ++DefIdx) {
591 if (!Node->hasAnyUseOfValue(Value: DefIdx))
592 continue;
593 ValueType = Node->getSimpleValueType(ResNo: DefIdx);
594 ++DefIdx;
595 return; // Found a normal regdef.
596 }
597 Node = Node->getGluedNode();
598 if (!Node) {
599 return; // No values left to visit.
600 }
601 InitNodeNumDefs();
602 }
603}
604
605void ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) {
606 assert(SU->NumRegDefsLeft == 0 && "expect a new node");
607 for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) {
608 assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected");
609 ++SU->NumRegDefsLeft;
610 }
611}
612
613void ScheduleDAGSDNodes::computeLatency(SUnit *SU) {
614 SDNode *N = SU->getNode();
615
616 // TokenFactor operands are considered zero latency, and some schedulers
617 // (e.g. Top-Down list) may rely on the fact that operand latency is nonzero
618 // whenever node latency is nonzero.
619 if (N && N->getOpcode() == ISD::TokenFactor) {
620 SU->Latency = 0;
621 return;
622 }
623
624 // Check to see if the scheduler cares about latencies.
625 if (forceUnitLatencies()) {
626 SU->Latency = 1;
627 return;
628 }
629
630 if (!InstrItins || InstrItins->isEmpty()) {
631 if (N && N->isMachineOpcode() &&
632 TII->isHighLatencyDef(opc: N->getMachineOpcode()))
633 SU->Latency = HighLatencyCycles;
634 else
635 SU->Latency = 1;
636 return;
637 }
638
639 // Compute the latency for the node. We use the sum of the latencies for
640 // all nodes glued together into this SUnit.
641 SU->Latency = 0;
642 for (SDNode *N = SU->getNode(); N; N = N->getGluedNode())
643 if (N->isMachineOpcode())
644 SU->Latency += TII->getInstrLatency(ItinData: InstrItins, Node: N);
645}
646
647void ScheduleDAGSDNodes::computeOperandLatency(SDNode *Def, SDNode *Use,
648 unsigned OpIdx, SDep& dep) const{
649 // Check to see if the scheduler cares about latencies.
650 if (forceUnitLatencies())
651 return;
652
653 if (dep.getKind() != SDep::Data)
654 return;
655
656 unsigned DefIdx = Use->getOperand(Num: OpIdx).getResNo();
657 if (Use->isMachineOpcode())
658 // Adjust the use operand index by num of defs.
659 OpIdx += TII->get(Opcode: Use->getMachineOpcode()).getNumDefs();
660 std::optional<unsigned> Latency =
661 TII->getOperandLatency(ItinData: InstrItins, DefNode: Def, DefIdx, UseNode: Use, UseIdx: OpIdx);
662 if (Latency > 1U && Use->getOpcode() == ISD::CopyToReg &&
663 !BB->succ_empty()) {
664 Register Reg = cast<RegisterSDNode>(Val: Use->getOperand(Num: 1))->getReg();
665 if (Reg.isVirtual())
666 // This copy is a liveout value. It is likely coalesced, so reduce the
667 // latency so not to penalize the def.
668 // FIXME: need target specific adjustment here?
669 Latency = *Latency - 1;
670 }
671 if (Latency)
672 dep.setLatency(*Latency);
673}
674
675void ScheduleDAGSDNodes::dumpNode(const SUnit &SU) const {
676#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
677 dumpNodeName(SU);
678 dbgs() << ": ";
679
680 if (!SU.getNode()) {
681 dbgs() << "PHYS REG COPY\n";
682 return;
683 }
684
685 SU.getNode()->dump(DAG);
686 dbgs() << "\n";
687 SmallVector<SDNode *, 4> GluedNodes;
688 for (SDNode *N = SU.getNode()->getGluedNode(); N; N = N->getGluedNode())
689 GluedNodes.push_back(N);
690 while (!GluedNodes.empty()) {
691 dbgs() << " ";
692 GluedNodes.back()->dump(DAG);
693 dbgs() << "\n";
694 GluedNodes.pop_back();
695 }
696#endif
697}
698
699void ScheduleDAGSDNodes::dump() const {
700#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
701 if (EntrySU.getNode() != nullptr)
702 dumpNodeAll(EntrySU);
703 for (const SUnit &SU : SUnits)
704 dumpNodeAll(SU);
705 if (ExitSU.getNode() != nullptr)
706 dumpNodeAll(ExitSU);
707#endif
708}
709
710#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
711void ScheduleDAGSDNodes::dumpSchedule() const {
712 for (const SUnit *SU : Sequence) {
713 if (SU)
714 dumpNode(*SU);
715 else
716 dbgs() << "**** NOOP ****\n";
717 }
718}
719#endif
720
721#ifndef NDEBUG
722/// VerifyScheduledSequence - Verify that all SUnits were scheduled and that
723/// their state is consistent with the nodes listed in Sequence.
724///
725void ScheduleDAGSDNodes::VerifyScheduledSequence(bool isBottomUp) {
726 unsigned ScheduledNodes = ScheduleDAG::VerifyScheduledDAG(isBottomUp);
727 unsigned Noops = llvm::count(Sequence, nullptr);
728 assert(Sequence.size() - Noops == ScheduledNodes &&
729 "The number of nodes scheduled doesn't match the expected number!");
730}
731#endif // NDEBUG
732
733/// ProcessSDDbgValues - Process SDDbgValues associated with this node.
734static void
735ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
736 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
737 InstrEmitter::VRBaseMapType &VRBaseMap, unsigned Order) {
738 if (!N->getHasDebugValue())
739 return;
740
741 /// Returns true if \p DV has any VReg operand locations which don't exist in
742 /// VRBaseMap.
743 auto HasUnknownVReg = [&VRBaseMap](SDDbgValue *DV) {
744 for (const SDDbgOperand &L : DV->getLocationOps()) {
745 if (L.getKind() == SDDbgOperand::SDNODE &&
746 VRBaseMap.count(Val: {L.getSDNode(), L.getResNo()}) == 0)
747 return true;
748 }
749 return false;
750 };
751
752 // Opportunistically insert immediate dbg_value uses, i.e. those with the same
753 // source order number as N.
754 MachineBasicBlock *BB = Emitter.getBlock();
755 MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
756 for (auto *DV : DAG->GetDbgValues(SD: N)) {
757 if (DV->isEmitted())
758 continue;
759 unsigned DVOrder = DV->getOrder();
760 if (Order != 0 && DVOrder != Order)
761 continue;
762 // If DV has any VReg location operands which haven't been mapped then
763 // either that node is no longer available or we just haven't visited the
764 // node yet. In the former case we should emit an undef dbg_value, but we
765 // can do it later. And for the latter we'll want to wait until all
766 // dependent nodes have been visited.
767 if (!DV->isInvalidated() && HasUnknownVReg(DV))
768 continue;
769 MachineInstr *DbgMI = Emitter.EmitDbgValue(SD: DV, VRBaseMap);
770 if (!DbgMI)
771 continue;
772 Orders.push_back(Elt: {DVOrder, DbgMI});
773 BB->insert(I: InsertPos, MI: DbgMI);
774 }
775}
776
777// ProcessSourceNode - Process nodes with source order numbers. These are added
778// to a vector which EmitSchedule uses to determine how to insert dbg_value
779// instructions in the right order.
780static void
781ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
782 InstrEmitter::VRBaseMapType &VRBaseMap,
783 SmallVectorImpl<std::pair<unsigned, MachineInstr *>> &Orders,
784 SmallSet<Register, 8> &Seen, MachineInstr *NewInsn) {
785 unsigned Order = N->getIROrder();
786 if (!Order || Seen.count(V: Order)) {
787 // Process any valid SDDbgValues even if node does not have any order
788 // assigned.
789 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order: 0);
790 return;
791 }
792
793 // If a new instruction was generated for this Order number, record it.
794 // Otherwise, leave this order number unseen: we will either find later
795 // instructions for it, or leave it unseen if there were no instructions at
796 // all.
797 if (NewInsn) {
798 Seen.insert(V: Order);
799 Orders.push_back(Elt: {Order, NewInsn});
800 }
801
802 // Even if no instruction was generated, a Value may have become defined via
803 // earlier nodes. Try to process them now.
804 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
805}
806
807void ScheduleDAGSDNodes::
808EmitPhysRegCopy(SUnit *SU, SmallDenseMap<SUnit *, Register, 16> &VRBaseMap,
809 MachineBasicBlock::iterator InsertPos) {
810 for (const SDep &Pred : SU->Preds) {
811 if (Pred.isCtrl())
812 continue; // ignore chain preds
813 if (Pred.getSUnit()->CopyDstRC) {
814 // Copy to physical register.
815 auto VRI = VRBaseMap.find(Val: Pred.getSUnit());
816 assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
817 // Find the destination physical register.
818 Register Reg;
819 for (const SDep &Succ : SU->Succs) {
820 if (Succ.isCtrl())
821 continue; // ignore chain preds
822 if (Succ.getReg()) {
823 Reg = Succ.getReg();
824 break;
825 }
826 }
827 BuildMI(BB&: *BB, I: InsertPos, MIMD: DebugLoc(), MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: Reg)
828 .addReg(RegNo: VRI->second);
829 } else {
830 // Copy from physical register.
831 assert(Pred.getReg() && "Unknown physical register!");
832 Register VRBase = MRI.createVirtualRegister(RegClass: SU->CopyDstRC);
833 bool isNew = VRBaseMap.insert(KV: std::make_pair(x&: SU, y&: VRBase)).second;
834 (void)isNew; // Silence compiler warning.
835 assert(isNew && "Node emitted out of order - early");
836 BuildMI(BB&: *BB, I: InsertPos, MIMD: DebugLoc(), MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: VRBase)
837 .addReg(RegNo: Pred.getReg());
838 }
839 break;
840 }
841}
842
843/// EmitSchedule - Emit the machine code in scheduled order. Return the new
844/// InsertPos and MachineBasicBlock that contains this insertion
845/// point. ScheduleDAGSDNodes holds a BB pointer for convenience, but this does
846/// not necessarily refer to returned BB. The emitter may split blocks.
847MachineBasicBlock *ScheduleDAGSDNodes::
848EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
849 InstrEmitter Emitter(DAG->getTarget(), BB, InsertPos);
850 InstrEmitter::VRBaseMapType VRBaseMap;
851 SmallDenseMap<SUnit *, Register, 16> CopyVRBaseMap;
852 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
853 SmallSet<Register, 8> Seen;
854 bool HasDbg = DAG->hasDebugValues();
855
856 // Emit a node, and determine where its first instruction is for debuginfo.
857 // Zero, one, or multiple instructions can be created when emitting a node.
858 auto EmitNode =
859 [&](SDNode *Node, bool IsClone, bool IsCloned,
860 InstrEmitter::VRBaseMapType &VRBaseMap) -> MachineInstr * {
861 // Fetch instruction prior to this, or end() if nonexistant.
862 auto GetPrevInsn = [&](MachineBasicBlock::iterator I) {
863 if (I == BB->begin())
864 return BB->end();
865 else
866 return std::prev(x: Emitter.getInsertPos());
867 };
868
869 MachineBasicBlock::iterator Before = GetPrevInsn(Emitter.getInsertPos());
870 Emitter.EmitNode(Node, IsClone, IsCloned, VRBaseMap);
871 MachineBasicBlock::iterator After = GetPrevInsn(Emitter.getInsertPos());
872
873 // If the iterator did not change, no instructions were inserted.
874 if (Before == After)
875 return nullptr;
876
877 MachineInstr *MI;
878 if (Before == BB->end()) {
879 // There were no prior instructions; the new ones must start at the
880 // beginning of the block.
881 MI = &Emitter.getBlock()->instr_front();
882 } else {
883 // Return first instruction after the pre-existing instructions.
884 MI = &*std::next(x: Before);
885 }
886
887 if (MI->isCandidateForAdditionalCallInfo()) {
888 if (DAG->getTarget().Options.EmitCallSiteInfo ||
889 DAG->getTarget().Options.EmitCallGraphSection)
890 MF.addCallSiteInfo(CallI: MI, CallInfo: DAG->getCallSiteInfo(Node));
891
892 if (auto CalledGlobal = DAG->getCalledGlobal(Node))
893 if (CalledGlobal->Callee)
894 MF.addCalledGlobal(MI, Details: *CalledGlobal);
895 }
896
897 if (DAG->getNoMergeSiteInfo(Node)) {
898 MI->setFlag(MachineInstr::MIFlag::NoMerge);
899 }
900
901 if (MDNode *MD = DAG->getPCSections(Node))
902 MI->setPCSections(MF, MD);
903
904 // Set MMRAs on _all_ added instructions.
905 if (MDNode *MMRA = DAG->getMMRAMetadata(Node)) {
906 for (MachineBasicBlock::iterator It = MI->getIterator(),
907 End = std::next(x: After);
908 It != End; ++It)
909 It->setMMRAMetadata(MF, MMRAs: MMRA);
910 }
911
912 return MI;
913 };
914
915 // If this is the first BB, emit byval parameter dbg_value's.
916 if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) {
917 SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin();
918 SDDbgInfo::DbgIterator PDE = DAG->ByvalParmDbgEnd();
919 for (; PDI != PDE; ++PDI) {
920 MachineInstr *DbgMI= Emitter.EmitDbgValue(SD: *PDI, VRBaseMap);
921 if (DbgMI) {
922 BB->insert(I: InsertPos, MI: DbgMI);
923 // We re-emit the dbg_value closer to its use, too, after instructions
924 // are emitted to the BB.
925 (*PDI)->clearIsEmitted();
926 }
927 }
928 }
929
930 for (SUnit *SU : Sequence) {
931 if (!SU) {
932 // Null SUnit* is a noop.
933 TII->insertNoop(MBB&: *Emitter.getBlock(), MI: InsertPos);
934 continue;
935 }
936
937 // For pre-regalloc scheduling, create instructions corresponding to the
938 // SDNode and any glued SDNodes and append them to the block.
939 if (!SU->getNode()) {
940 // Emit a copy.
941 EmitPhysRegCopy(SU, VRBaseMap&: CopyVRBaseMap, InsertPos);
942 continue;
943 }
944
945 SmallVector<SDNode *, 4> GluedNodes;
946 for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
947 GluedNodes.push_back(Elt: N);
948 while (!GluedNodes.empty()) {
949 SDNode *N = GluedNodes.back();
950 auto NewInsn = EmitNode(N, SU->OrigNode != SU, SU->isCloned, VRBaseMap);
951 // Remember the source order of the inserted instruction.
952 if (HasDbg)
953 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen, NewInsn);
954
955 if (MDNode *MD = DAG->getHeapAllocSite(Node: N))
956 if (NewInsn && NewInsn->isCall())
957 NewInsn->setHeapAllocMarker(MF, MD);
958
959 GluedNodes.pop_back();
960 }
961 auto NewInsn =
962 EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, VRBaseMap);
963 // Remember the source order of the inserted instruction.
964 if (HasDbg)
965 ProcessSourceNode(N: SU->getNode(), DAG, Emitter, VRBaseMap, Orders, Seen,
966 NewInsn);
967
968 if (MDNode *MD = DAG->getHeapAllocSite(Node: SU->getNode())) {
969 if (NewInsn && NewInsn->isCall())
970 NewInsn->setHeapAllocMarker(MF, MD);
971 }
972 }
973
974 // Insert all the dbg_values which have not already been inserted in source
975 // order sequence.
976 if (HasDbg) {
977 MachineBasicBlock::iterator BBBegin = BB->getFirstNonPHI();
978
979 // Sort the source order instructions and use the order to insert debug
980 // values. Use stable_sort so that DBG_VALUEs are inserted in the same order
981 // regardless of the host's implementation fo std::sort.
982 llvm::stable_sort(Range&: Orders, C: less_first());
983 std::stable_sort(first: DAG->DbgBegin(), last: DAG->DbgEnd(),
984 comp: [](const SDDbgValue *LHS, const SDDbgValue *RHS) {
985 return LHS->getOrder() < RHS->getOrder();
986 });
987
988 SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
989 SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
990 // Now emit the rest according to source order.
991 unsigned LastOrder = 0;
992 for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
993 unsigned Order = Orders[i].first;
994 MachineInstr *MI = Orders[i].second;
995 // Insert all SDDbgValue's whose order(s) are before "Order".
996 assert(MI);
997 for (; DI != DE; ++DI) {
998 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order)
999 break;
1000 if ((*DI)->isEmitted())
1001 continue;
1002
1003 MachineInstr *DbgMI = Emitter.EmitDbgValue(SD: *DI, VRBaseMap);
1004 if (DbgMI) {
1005 if (!LastOrder)
1006 // Insert to start of the BB (after PHIs).
1007 BB->insert(I: BBBegin, MI: DbgMI);
1008 else {
1009 // Insert at the instruction, which may be in a different
1010 // block, if the block was split by a custom inserter.
1011 MachineBasicBlock::iterator Pos = MI;
1012 MI->getParent()->insert(I: Pos, MI: DbgMI);
1013 }
1014 }
1015 }
1016 LastOrder = Order;
1017 }
1018 // Add trailing DbgValue's before the terminator. FIXME: May want to add
1019 // some of them before one or more conditional branches?
1020 SmallVector<MachineInstr*, 8> DbgMIs;
1021 for (; DI != DE; ++DI) {
1022 if ((*DI)->isEmitted())
1023 continue;
1024 assert((*DI)->getOrder() >= LastOrder &&
1025 "emitting DBG_VALUE out of order");
1026 if (MachineInstr *DbgMI = Emitter.EmitDbgValue(SD: *DI, VRBaseMap))
1027 DbgMIs.push_back(Elt: DbgMI);
1028 }
1029
1030 MachineBasicBlock *InsertBB = Emitter.getBlock();
1031 MachineBasicBlock::iterator Pos = InsertBB->getFirstTerminator();
1032 InsertBB->insert(I: Pos, S: DbgMIs.begin(), E: DbgMIs.end());
1033
1034 SDDbgInfo::DbgLabelIterator DLI = DAG->DbgLabelBegin();
1035 SDDbgInfo::DbgLabelIterator DLE = DAG->DbgLabelEnd();
1036 // Now emit the rest according to source order.
1037 LastOrder = 0;
1038 for (const auto &InstrOrder : Orders) {
1039 unsigned Order = InstrOrder.first;
1040 MachineInstr *MI = InstrOrder.second;
1041 if (!MI)
1042 continue;
1043
1044 // Insert all SDDbgLabel's whose order(s) are before "Order".
1045 for (; DLI != DLE &&
1046 (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order;
1047 ++DLI) {
1048 MachineInstr *DbgMI = Emitter.EmitDbgLabel(SD: *DLI);
1049 if (DbgMI) {
1050 if (!LastOrder)
1051 // Insert to start of the BB (after PHIs).
1052 BB->insert(I: BBBegin, MI: DbgMI);
1053 else {
1054 // Insert at the instruction, which may be in a different
1055 // block, if the block was split by a custom inserter.
1056 MachineBasicBlock::iterator Pos = MI;
1057 MI->getParent()->insert(I: Pos, MI: DbgMI);
1058 }
1059 }
1060 }
1061 if (DLI == DLE)
1062 break;
1063
1064 LastOrder = Order;
1065 }
1066 }
1067
1068 InsertPos = Emitter.getInsertPos();
1069 // In some cases, DBG_VALUEs might be inserted after the first terminator,
1070 // which results in an invalid MBB. If that happens, move the DBG_VALUEs
1071 // before the first terminator.
1072 MachineBasicBlock *InsertBB = Emitter.getBlock();
1073 auto FirstTerm = InsertBB->getFirstTerminator();
1074 if (FirstTerm != InsertBB->end()) {
1075 assert(!FirstTerm->isDebugValue() &&
1076 "first terminator cannot be a debug value");
1077 for (MachineInstr &MI : make_early_inc_range(
1078 Range: make_range(x: std::next(x: FirstTerm), y: InsertBB->end()))) {
1079 // Only scan up to insertion point.
1080 if (&MI == InsertPos)
1081 break;
1082
1083 if (!MI.isDebugValue())
1084 continue;
1085
1086 // The DBG_VALUE was referencing a value produced by a terminator. By
1087 // moving the DBG_VALUE, the referenced value also needs invalidating.
1088 MI.getOperand(i: 0).ChangeToRegister(Reg: 0, isDef: false);
1089 MI.moveBefore(MovePos: &*FirstTerm);
1090 }
1091 }
1092 return InsertBB;
1093}
1094
1095/// Return the basic block label.
1096std::string ScheduleDAGSDNodes::getDAGName() const {
1097 return "sunit-dag." + BB->getFullName();
1098}
1099