1//===- SplitKit.cpp - Toolkit for splitting live ranges -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the SplitAnalysis class as well as mutator functions for
10// live range splitting.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SplitKit.h"
15#include "llvm/ADT/STLExtras.h"
16#include "llvm/ADT/Statistic.h"
17#include "llvm/CodeGen/LiveRangeEdit.h"
18#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
19#include "llvm/CodeGen/MachineDominators.h"
20#include "llvm/CodeGen/MachineInstr.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineLoopInfo.h"
23#include "llvm/CodeGen/MachineOperand.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/TargetInstrInfo.h"
26#include "llvm/CodeGen/TargetOpcodes.h"
27#include "llvm/CodeGen/TargetRegisterInfo.h"
28#include "llvm/CodeGen/TargetSubtargetInfo.h"
29#include "llvm/CodeGen/VirtRegMap.h"
30#include "llvm/Config/llvm-config.h"
31#include "llvm/IR/DebugLoc.h"
32#include "llvm/Support/Allocator.h"
33#include "llvm/Support/BlockFrequency.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
37#include <algorithm>
38#include <cassert>
39#include <iterator>
40#include <limits>
41#include <tuple>
42
43using namespace llvm;
44
45#define DEBUG_TYPE "regalloc"
46
47static cl::opt<bool>
48 EnableLoopIVHeuristic("enable-split-loopiv-heuristic",
49 cl::desc("Enable loop iv regalloc heuristic"),
50 cl::init(Val: true));
51
52STATISTIC(NumFinished, "Number of splits finished");
53STATISTIC(NumSimple, "Number of splits that were simple");
54STATISTIC(NumCopies, "Number of copies inserted for splitting");
55STATISTIC(NumRemats, "Number of rematerialized defs for splitting");
56
57//===----------------------------------------------------------------------===//
58// Last Insert Point Analysis
59//===----------------------------------------------------------------------===//
60
61InsertPointAnalysis::InsertPointAnalysis(const LiveIntervals &lis,
62 unsigned BBNum)
63 : LIS(lis), LastInsertPoint(BBNum) {}
64
65SlotIndex
66InsertPointAnalysis::computeLastInsertPoint(const LiveInterval &CurLI,
67 const MachineBasicBlock &MBB) {
68 unsigned Num = MBB.getNumber();
69 std::pair<SlotIndex, SlotIndex> &LIP = LastInsertPoint[Num];
70 SlotIndex MBBEnd = LIS.getMBBEndIdx(mbb: &MBB);
71
72 SmallVector<const MachineBasicBlock *, 1> ExceptionalSuccessors;
73 bool EHPadSuccessor = false;
74 for (const MachineBasicBlock *SMBB : MBB.successors()) {
75 if (SMBB->isEHPad()) {
76 ExceptionalSuccessors.push_back(Elt: SMBB);
77 EHPadSuccessor = true;
78 } else if (SMBB->isInlineAsmBrIndirectTarget())
79 ExceptionalSuccessors.push_back(Elt: SMBB);
80 }
81
82 // Compute insert points on the first call. The pair is independent of the
83 // current live interval.
84 if (!LIP.first.isValid()) {
85 MachineBasicBlock::const_iterator FirstTerm = MBB.getFirstTerminator();
86 if (FirstTerm == MBB.end())
87 LIP.first = MBBEnd;
88 else
89 LIP.first = LIS.getInstructionIndex(Instr: *FirstTerm);
90
91 // If there is a landing pad or inlineasm_br successor, also find the
92 // instruction. If there is no such instruction, we don't need to do
93 // anything special. We assume there cannot be multiple instructions that
94 // are Calls with EHPad successors or INLINEASM_BR in a block. Further, we
95 // assume that if there are any, they will be after any other call
96 // instructions in the block.
97 if (ExceptionalSuccessors.empty())
98 return LIP.first;
99 for (const MachineInstr &MI : llvm::reverse(C: MBB)) {
100 if ((EHPadSuccessor && MI.isCall()) ||
101 MI.getOpcode() == TargetOpcode::INLINEASM_BR) {
102 LIP.second = LIS.getInstructionIndex(Instr: MI);
103 break;
104 }
105 }
106 }
107
108 // If CurLI is live into a landing pad successor, move the last insert point
109 // back to the call that may throw.
110 if (!LIP.second)
111 return LIP.first;
112
113 if (none_of(Range&: ExceptionalSuccessors, P: [&](const MachineBasicBlock *EHPad) {
114 return LIS.isLiveInToMBB(LR: CurLI, mbb: EHPad);
115 }))
116 return LIP.first;
117
118 // Find the value leaving MBB.
119 const VNInfo *VNI = CurLI.getVNInfoBefore(Idx: MBBEnd);
120 if (!VNI)
121 return LIP.first;
122
123 // The def of statepoint instruction is a gc relocation and it should be alive
124 // in landing pad. So we cannot split interval after statepoint instruction.
125 if (SlotIndex::isSameInstr(A: VNI->def, B: LIP.second))
126 if (auto *I = LIS.getInstructionFromIndex(index: LIP.second))
127 if (I->getOpcode() == TargetOpcode::STATEPOINT)
128 return LIP.second;
129
130 // If the value leaving MBB was defined after the call in MBB, it can't
131 // really be live-in to the landing pad. This can happen if the landing pad
132 // has a PHI, and this register is undef on the exceptional edge.
133 if (!SlotIndex::isEarlierInstr(A: VNI->def, B: LIP.second) && VNI->def < MBBEnd)
134 return LIP.first;
135
136 // Value is properly live-in to the landing pad.
137 // Only allow inserts before the call.
138 return LIP.second;
139}
140
141MachineBasicBlock::iterator
142InsertPointAnalysis::getLastInsertPointIter(const LiveInterval &CurLI,
143 MachineBasicBlock &MBB) {
144 SlotIndex LIP = getLastInsertPoint(CurLI, MBB);
145 if (LIP == LIS.getMBBEndIdx(mbb: &MBB))
146 return MBB.end();
147 return LIS.getInstructionFromIndex(index: LIP);
148}
149
150//===----------------------------------------------------------------------===//
151// Split Analysis
152//===----------------------------------------------------------------------===//
153
154SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
155 const MachineLoopInfo &mli)
156 : MF(vrm.getMachineFunction()), VRM(vrm), LIS(lis), Loops(mli),
157 TII(*MF.getSubtarget().getInstrInfo()), IPA(lis, MF.getNumBlockIDs()) {}
158
159void SplitAnalysis::clear() {
160 UseSlots.clear();
161 UseBlocks.clear();
162 ThroughBlocks.clear();
163 CurLI = nullptr;
164}
165
166/// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
167void SplitAnalysis::analyzeUses() {
168 assert(UseSlots.empty() && "Call clear first");
169
170 // First get all the defs from the interval values. This provides the correct
171 // slots for early clobbers.
172 for (const VNInfo *VNI : CurLI->valnos)
173 if (!VNI->isPHIDef() && !VNI->isUnused())
174 UseSlots.push_back(Elt: VNI->def);
175
176 // Get use slots form the use-def chain.
177 const MachineRegisterInfo &MRI = MF.getRegInfo();
178 for (MachineOperand &MO : MRI.use_nodbg_operands(Reg: CurLI->reg()))
179 if (!MO.isUndef())
180 UseSlots.push_back(Elt: LIS.getInstructionIndex(Instr: *MO.getParent()).getRegSlot());
181
182 array_pod_sort(Start: UseSlots.begin(), End: UseSlots.end());
183
184 // Remove duplicates, keeping the smaller slot for each instruction.
185 // That is what we want for early clobbers.
186 UseSlots.erase(CS: llvm::unique(R&: UseSlots, P: SlotIndex::isSameInstr),
187 CE: UseSlots.end());
188
189 // Compute per-live block info.
190 calcLiveBlockInfo();
191
192 LLVM_DEBUG(dbgs() << "Analyze counted " << UseSlots.size() << " instrs in "
193 << UseBlocks.size() << " blocks, through "
194 << NumThroughBlocks << " blocks.\n");
195}
196
197/// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
198/// where CurLI is live.
199void SplitAnalysis::calcLiveBlockInfo() {
200 ThroughBlocks.resize(N: MF.getNumBlockIDs());
201 NumThroughBlocks = NumGapBlocks = 0;
202 if (CurLI->empty())
203 return;
204
205 LiveInterval::const_iterator LVI = CurLI->begin();
206 LiveInterval::const_iterator LVE = CurLI->end();
207
208 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
209 UseI = UseSlots.begin();
210 UseE = UseSlots.end();
211
212 // Loop over basic blocks where CurLI is live.
213 MachineFunction::iterator MFI =
214 LIS.getMBBFromIndex(index: LVI->start)->getIterator();
215 while (true) {
216 BlockInfo BI;
217 BI.MBB = &*MFI;
218 SlotIndex Start, Stop;
219 std::tie(args&: Start, args&: Stop) = LIS.getSlotIndexes()->getMBBRange(MBB: BI.MBB);
220
221 // If the block contains no uses, the range must be live through. At one
222 // point, RegisterCoalescer could create dangling ranges that ended
223 // mid-block.
224 if (UseI == UseE || *UseI >= Stop) {
225 ++NumThroughBlocks;
226 ThroughBlocks.set(BI.MBB->getNumber());
227 // The range shouldn't end mid-block if there are no uses. This shouldn't
228 // happen.
229 assert(LVI->end >= Stop && "range ends mid block with no uses");
230 } else {
231 // This block has uses. Find the first and last uses in the block.
232 BI.FirstInstr = *UseI;
233 assert(BI.FirstInstr >= Start);
234 do ++UseI;
235 while (UseI != UseE && *UseI < Stop);
236 BI.LastInstr = UseI[-1];
237 assert(BI.LastInstr < Stop);
238
239 // LVI is the first live segment overlapping MBB.
240 BI.LiveIn = LVI->start <= Start;
241
242 // When not live in, the first use should be a def.
243 if (!BI.LiveIn) {
244 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
245 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
246 BI.FirstDef = BI.FirstInstr;
247 }
248
249 // Look for gaps in the live range.
250 BI.LiveOut = true;
251 while (LVI->end < Stop) {
252 SlotIndex LastStop = LVI->end;
253 if (++LVI == LVE || LVI->start >= Stop) {
254 BI.LiveOut = false;
255 BI.LastInstr = LastStop;
256 break;
257 }
258
259 if (LastStop < LVI->start) {
260 // There is a gap in the live range. Create duplicate entries for the
261 // live-in snippet and the live-out snippet.
262 ++NumGapBlocks;
263
264 // Push the Live-in part.
265 BI.LiveOut = false;
266 UseBlocks.push_back(Elt: BI);
267 UseBlocks.back().LastInstr = LastStop;
268
269 // Set up BI for the live-out part.
270 BI.LiveIn = false;
271 BI.LiveOut = true;
272 BI.FirstInstr = BI.FirstDef = LVI->start;
273 }
274
275 // A Segment that starts in the middle of the block must be a def.
276 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
277 if (!BI.FirstDef)
278 BI.FirstDef = LVI->start;
279 }
280
281 UseBlocks.push_back(Elt: BI);
282
283 // LVI is now at LVE or LVI->end >= Stop.
284 if (LVI == LVE)
285 break;
286 }
287
288 // Live segment ends exactly at Stop. Move to the next segment.
289 if (LVI->end == Stop && ++LVI == LVE)
290 break;
291
292 // Pick the next basic block.
293 if (LVI->start < Stop)
294 ++MFI;
295 else
296 MFI = LIS.getMBBFromIndex(index: LVI->start)->getIterator();
297 }
298
299 LooksLikeLoopIV = EnableLoopIVHeuristic && UseBlocks.size() == 2 &&
300 any_of(Range&: UseBlocks, P: [this](BlockInfo &BI) {
301 MachineLoop *L = Loops.getLoopFor(BB: BI.MBB);
302 return BI.LiveIn && BI.LiveOut && BI.FirstDef && L &&
303 L->isLoopLatch(BB: BI.MBB);
304 });
305
306 assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
307}
308
309unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
310 if (cli->empty())
311 return 0;
312 LiveInterval *li = const_cast<LiveInterval*>(cli);
313 LiveInterval::iterator LVI = li->begin();
314 LiveInterval::iterator LVE = li->end();
315 unsigned Count = 0;
316
317 // Loop over basic blocks where li is live.
318 MachineFunction::const_iterator MFI =
319 LIS.getMBBFromIndex(index: LVI->start)->getIterator();
320 SlotIndex Stop = LIS.getMBBEndIdx(mbb: &*MFI);
321 while (true) {
322 ++Count;
323 LVI = li->advanceTo(I: LVI, Pos: Stop);
324 if (LVI == LVE)
325 return Count;
326 do {
327 ++MFI;
328 Stop = LIS.getMBBEndIdx(mbb: &*MFI);
329 } while (Stop <= LVI->start);
330 }
331}
332
333bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
334 Register OrigReg = VRM.getOriginal(VirtReg: CurLI->reg());
335 const LiveInterval &Orig = LIS.getInterval(Reg: OrigReg);
336 assert(!Orig.empty() && "Splitting empty interval?");
337 LiveInterval::const_iterator I = Orig.find(Pos: Idx);
338
339 // Range containing Idx should begin at Idx.
340 if (I != Orig.end() && I->start <= Idx)
341 return I->start == Idx;
342
343 // Range does not contain Idx, previous must end at Idx.
344 return I != Orig.begin() && (--I)->end == Idx;
345}
346
347void SplitAnalysis::analyze(const LiveInterval *li) {
348 clear();
349 CurLI = li;
350 analyzeUses();
351}
352
353//===----------------------------------------------------------------------===//
354// Split Editor
355//===----------------------------------------------------------------------===//
356
357/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
358SplitEditor::SplitEditor(SplitAnalysis &SA, LiveIntervals &LIS, VirtRegMap &VRM,
359 MachineDominatorTree &MDT,
360 MachineBlockFrequencyInfo &MBFI, VirtRegAuxInfo &VRAI)
361 : SA(SA), LIS(LIS), VRM(VRM), MRI(VRM.getMachineFunction().getRegInfo()),
362 MDT(MDT), TII(*VRM.getMachineFunction().getSubtarget().getInstrInfo()),
363 TRI(*VRM.getMachineFunction().getSubtarget().getRegisterInfo()),
364 MBFI(MBFI), VRAI(VRAI), RegAssign(Allocator) {}
365
366void SplitEditor::reset(LiveRangeEdit &LRE, ComplementSpillMode SM) {
367 Edit = &LRE;
368 SpillMode = SM;
369 OpenIdx = 0;
370 RegAssign.clear();
371 Values.clear();
372
373 // Reset the LiveIntervalCalc instances needed for this spill mode.
374 LICalc[0].reset(mf: &VRM.getMachineFunction(), SI: LIS.getSlotIndexes(), MDT: &MDT,
375 VNIA: &LIS.getVNInfoAllocator());
376 if (SpillMode)
377 LICalc[1].reset(mf: &VRM.getMachineFunction(), SI: LIS.getSlotIndexes(), MDT: &MDT,
378 VNIA: &LIS.getVNInfoAllocator());
379}
380
381#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
382LLVM_DUMP_METHOD void SplitEditor::dump() const {
383 if (RegAssign.empty()) {
384 dbgs() << " empty\n";
385 return;
386 }
387
388 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
389 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
390 dbgs() << '\n';
391}
392#endif
393
394/// Find a subrange corresponding to the exact lane mask @p LM in the live
395/// interval @p LI. The interval @p LI is assumed to contain such a subrange.
396/// This function is used to find corresponding subranges between the
397/// original interval and the new intervals.
398template <typename T> auto &getSubrangeImpl(LaneBitmask LM, T &LI) {
399 for (auto &S : LI.subranges())
400 if (S.LaneMask == LM)
401 return S;
402 llvm_unreachable("SubRange for this mask not found");
403}
404
405LiveInterval::SubRange &getSubRangeForMaskExact(LaneBitmask LM,
406 LiveInterval &LI) {
407 return getSubrangeImpl(LM, LI);
408}
409
410const LiveInterval::SubRange &getSubRangeForMaskExact(LaneBitmask LM,
411 const LiveInterval &LI) {
412 return getSubrangeImpl(LM, LI);
413}
414
415/// Find a subrange corresponding to the lane mask @p LM, or a superset of it,
416/// in the live interval @p LI. The interval @p LI is assumed to contain such
417/// a subrange. This function is used to find corresponding subranges between
418/// the original interval and the new intervals.
419const LiveInterval::SubRange &getSubRangeForMask(LaneBitmask LM,
420 const LiveInterval &LI) {
421 for (const LiveInterval::SubRange &S : LI.subranges())
422 if ((S.LaneMask & LM) == LM)
423 return S;
424 llvm_unreachable("SubRange for this mask not found");
425}
426
427void SplitEditor::addDeadDef(LiveInterval &LI, VNInfo *VNI, bool Original) {
428 if (!LI.hasSubRanges()) {
429 LI.createDeadDef(VNI);
430 return;
431 }
432
433 SlotIndex Def = VNI->def;
434 if (Original) {
435 // If we are transferring a def from the original interval, make sure
436 // to only update the subranges for which the original subranges had
437 // a def at this location.
438 for (LiveInterval::SubRange &S : LI.subranges()) {
439 auto &PS = getSubRangeForMask(LM: S.LaneMask, LI: Edit->getParent());
440 VNInfo *PV = PS.getVNInfoAt(Idx: Def);
441 if (PV != nullptr && PV->def == Def)
442 S.createDeadDef(Def, VNIAlloc&: LIS.getVNInfoAllocator());
443 }
444 } else {
445 // This is a new def: either from rematerialization, or from an inserted
446 // copy. Since rematerialization can regenerate a definition of a sub-
447 // register, we need to check which subranges need to be updated.
448 const MachineInstr *DefMI = LIS.getInstructionFromIndex(index: Def);
449 assert(DefMI != nullptr);
450 LaneBitmask LM;
451 for (const MachineOperand &DefOp : DefMI->defs()) {
452 Register R = DefOp.getReg();
453 if (R != LI.reg())
454 continue;
455 if (unsigned SR = DefOp.getSubReg())
456 LM |= TRI.getSubRegIndexLaneMask(SubIdx: SR);
457 else {
458 LM = MRI.getMaxLaneMaskForVReg(Reg: R);
459 break;
460 }
461 }
462 for (LiveInterval::SubRange &S : LI.subranges())
463 if ((S.LaneMask & LM).any())
464 S.createDeadDef(Def, VNIAlloc&: LIS.getVNInfoAllocator());
465 }
466}
467
468VNInfo *SplitEditor::defValue(unsigned RegIdx,
469 const VNInfo *ParentVNI,
470 SlotIndex Idx,
471 bool Original) {
472 assert(ParentVNI && "Mapping NULL value");
473 assert(Idx.isValid() && "Invalid SlotIndex");
474 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
475 LiveInterval *LI = &LIS.getInterval(Reg: Edit->get(idx: RegIdx));
476
477 // Create a new value.
478 VNInfo *VNI = LI->getNextValue(Def: Idx, VNInfoAllocator&: LIS.getVNInfoAllocator());
479
480 bool Force = LI->hasSubRanges();
481 ValueForcePair FP(Force ? nullptr : VNI, Force);
482 // Use insert for lookup, so we can add missing values with a second lookup.
483 std::pair<ValueMap::iterator, bool> InsP =
484 Values.insert(KV: std::make_pair(x: std::make_pair(x&: RegIdx, y: ParentVNI->id), y&: FP));
485
486 // This was the first time (RegIdx, ParentVNI) was mapped, and it is not
487 // forced. Keep it as a simple def without any liveness.
488 if (!Force && InsP.second)
489 return VNI;
490
491 // If the previous value was a simple mapping, add liveness for it now.
492 if (VNInfo *OldVNI = InsP.first->second.getPointer()) {
493 addDeadDef(LI&: *LI, VNI: OldVNI, Original);
494
495 // No longer a simple mapping. Switch to a complex mapping. If the
496 // interval has subranges, make it a forced mapping.
497 InsP.first->second = ValueForcePair(nullptr, Force);
498 }
499
500 // This is a complex mapping, add liveness for VNI
501 addDeadDef(LI&: *LI, VNI, Original);
502 return VNI;
503}
504
505void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI) {
506 ValueForcePair &VFP = Values[std::make_pair(x&: RegIdx, y: ParentVNI.id)];
507 VNInfo *VNI = VFP.getPointer();
508
509 // ParentVNI was either unmapped or already complex mapped. Either way, just
510 // set the force bit.
511 if (!VNI) {
512 VFP.setInt(true);
513 return;
514 }
515
516 // This was previously a single mapping. Make sure the old def is represented
517 // by a trivial live range.
518 addDeadDef(LI&: LIS.getInterval(Reg: Edit->get(idx: RegIdx)), VNI, Original: false);
519
520 // Mark as complex mapped, forced.
521 VFP = ValueForcePair(nullptr, true);
522}
523
524SlotIndex SplitEditor::buildSingleSubRegCopy(
525 Register FromReg, Register ToReg, MachineBasicBlock &MBB,
526 MachineBasicBlock::iterator InsertBefore, unsigned SubIdx,
527 LiveInterval &DestLI, bool Late, SlotIndex Def, const MCInstrDesc &Desc) {
528 bool FirstCopy = !Def.isValid();
529 MachineInstr *CopyMI =
530 BuildMI(BB&: MBB, I: InsertBefore, MIMD: DebugLoc(), MCID: Desc)
531 .addReg(RegNo: ToReg,
532 Flags: RegState::Define | getUndefRegState(B: FirstCopy) |
533 getInternalReadRegState(B: !FirstCopy),
534 SubReg: SubIdx)
535 .addReg(RegNo: FromReg, Flags: {}, SubReg: SubIdx);
536
537 CopyMI->setFlag(MachineInstr::LRSplit);
538 SlotIndexes &Indexes = *LIS.getSlotIndexes();
539 if (FirstCopy) {
540 Def = Indexes.insertMachineInstrInMaps(MI&: *CopyMI, Late).getRegSlot();
541 } else {
542 CopyMI->bundleWithPred();
543 }
544 return Def;
545}
546
547SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg,
548 LaneBitmask LaneMask, MachineBasicBlock &MBB,
549 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) {
550 const MCInstrDesc &Desc =
551 TII.get(Opcode: TII.getLiveRangeSplitOpcode(Reg: FromReg, MF: *MBB.getParent()));
552 SlotIndexes &Indexes = *LIS.getSlotIndexes();
553 if (LaneMask.all() || LaneMask == MRI.getMaxLaneMaskForVReg(Reg: FromReg)) {
554 // The full vreg is copied.
555 MachineInstr *CopyMI =
556 BuildMI(BB&: MBB, I: InsertBefore, MIMD: DebugLoc(), MCID: Desc, DestReg: ToReg).addReg(RegNo: FromReg);
557 CopyMI->setFlag(MachineInstr::LRSplit);
558 return Indexes.insertMachineInstrInMaps(MI&: *CopyMI, Late).getRegSlot();
559 }
560
561 // Only a subset of lanes needs to be copied. The following is a simple
562 // heuristic to construct a sequence of COPYs. We could add a target
563 // specific callback if this turns out to be suboptimal.
564 LiveInterval &DestLI = LIS.getInterval(Reg: Edit->get(idx: RegIdx));
565
566 // First pass: Try to find a perfectly matching subregister index. If none
567 // exists find the one covering the most lanemask bits.
568 const TargetRegisterClass *RC = MRI.getRegClass(Reg: FromReg);
569 assert(RC == MRI.getRegClass(ToReg) && "Should have same reg class");
570
571 SmallVector<unsigned, 8> SubIndexes;
572
573 // Abort if we cannot possibly implement the COPY with the given indexes.
574 if (!TRI.getCoveringSubRegIndexes(RC, LaneMask, Indexes&: SubIndexes))
575 report_fatal_error(reason: "Impossible to implement partial COPY");
576
577 SlotIndex Def;
578 for (unsigned BestIdx : SubIndexes) {
579 Def = buildSingleSubRegCopy(FromReg, ToReg, MBB, InsertBefore, SubIdx: BestIdx,
580 DestLI, Late, Def, Desc);
581 }
582
583 BumpPtrAllocator &Allocator = LIS.getVNInfoAllocator();
584 DestLI.refineSubRanges(
585 Allocator, LaneMask,
586 Apply: [Def, &Allocator](LiveInterval::SubRange &SR) {
587 SR.createDeadDef(Def, VNIAlloc&: Allocator);
588 },
589 Indexes, TRI);
590
591 return Def;
592}
593
594bool SplitEditor::rematWillIncreaseRestriction(const MachineInstr *DefMI,
595 MachineBasicBlock &MBB,
596 SlotIndex UseIdx) const {
597 const MachineInstr *UseMI = LIS.getInstructionFromIndex(index: UseIdx);
598 if (!UseMI)
599 return false;
600
601 // Currently code assumes rematerialization only happens for a def at 0.
602 const unsigned DefOperandIdx = 0;
603 // We want to compute the static register class constraint for the instruction
604 // def. If it is a smaller subclass than getLargestLegalSuperClass at the use
605 // site, then rematerializing it will increase the constraints.
606 const TargetRegisterClass *DefConstrainRC =
607 DefMI->getRegClassConstraint(OpIdx: DefOperandIdx, TII: &TII, TRI: &TRI);
608 if (!DefConstrainRC)
609 return false;
610
611 const TargetRegisterClass *RC = MRI.getRegClass(Reg: Edit->getReg());
612
613 // We want to find the register class that can be inflated to after the split
614 // occurs in recomputeRegClass
615 const TargetRegisterClass *SuperRC =
616 TRI.getLargestLegalSuperClass(RC, *MBB.getParent());
617
618 Register DefReg = DefMI->getOperand(i: DefOperandIdx).getReg();
619 const TargetRegisterClass *UseConstrainRC =
620 UseMI->getRegClassConstraintEffectForVReg(Reg: DefReg, CurRC: SuperRC, TII: &TII, TRI: &TRI,
621 /*ExploreBundle=*/true);
622 return UseConstrainRC->hasSubClass(RC: DefConstrainRC);
623}
624
625VNInfo *SplitEditor::defFromParent(unsigned RegIdx, const VNInfo *ParentVNI,
626 SlotIndex UseIdx, MachineBasicBlock &MBB,
627 MachineBasicBlock::iterator I) {
628 LiveInterval *LI = &LIS.getInterval(Reg: Edit->get(idx: RegIdx));
629
630 // We may be trying to avoid interference that ends at a deleted instruction,
631 // so always begin RegIdx 0 early and all others late.
632 bool Late = RegIdx != 0;
633
634 // Attempt cheap-as-a-copy rematerialization.
635 Register Original = VRM.getOriginal(VirtReg: Edit->get(idx: RegIdx));
636 LiveInterval &OrigLI = LIS.getInterval(Reg: Original);
637 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx: UseIdx);
638
639 Register Reg = LI->reg();
640 if (OrigVNI) {
641 LiveRangeEdit::Remat RM(ParentVNI);
642 RM.OrigMI = LIS.getInstructionFromIndex(index: OrigVNI->def);
643 if (RM.OrigMI && TII.isAsCheapAsAMove(MI: *RM.OrigMI) &&
644 Edit->canRematerializeAt(RM, UseIdx)) {
645 if (!rematWillIncreaseRestriction(DefMI: RM.OrigMI, MBB, UseIdx)) {
646 SlotIndex Def = Edit->rematerializeAt(MBB, MI: I, DestReg: Reg, RM, TRI, Late);
647 ++NumRemats;
648 // Define the value in Reg.
649 return defValue(RegIdx, ParentVNI, Idx: Def, Original: false);
650 }
651 LLVM_DEBUG(
652 dbgs() << "skipping rematerialize of " << printReg(Reg) << " at "
653 << UseIdx
654 << " since it will increase register class restrictions\n");
655 }
656 }
657
658 LaneBitmask LaneMask;
659 if (OrigLI.hasSubRanges()) {
660 LaneMask = LaneBitmask::getNone();
661 for (LiveInterval::SubRange &S : OrigLI.subranges()) {
662 if (S.liveAt(index: UseIdx))
663 LaneMask |= S.LaneMask;
664 }
665 } else {
666 LaneMask = LaneBitmask::getAll();
667 }
668
669 SlotIndex Def;
670 if (LaneMask.none()) {
671 const MCInstrDesc &Desc = TII.get(Opcode: TargetOpcode::IMPLICIT_DEF);
672 MachineInstr *ImplicitDef = BuildMI(BB&: MBB, I, MIMD: DebugLoc(), MCID: Desc, DestReg: Reg);
673 SlotIndexes &Indexes = *LIS.getSlotIndexes();
674 Def = Indexes.insertMachineInstrInMaps(MI&: *ImplicitDef, Late).getRegSlot();
675 } else {
676 ++NumCopies;
677 Def = buildCopy(FromReg: Edit->getReg(), ToReg: Reg, LaneMask, MBB, InsertBefore: I, Late, RegIdx);
678 }
679
680 // Define the value in Reg.
681 return defValue(RegIdx, ParentVNI, Idx: Def, Original: false);
682}
683
684/// Create a new virtual register and live interval.
685unsigned SplitEditor::openIntv() {
686 // Create the complement as index 0.
687 if (Edit->empty())
688 Edit->createEmptyInterval();
689
690 // Create the open interval.
691 OpenIdx = Edit->size();
692 Edit->createEmptyInterval();
693 return OpenIdx;
694}
695
696void SplitEditor::selectIntv(unsigned Idx) {
697 assert(Idx != 0 && "Cannot select the complement interval");
698 assert(Idx < Edit->size() && "Can only select previously opened interval");
699 LLVM_DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n');
700 OpenIdx = Idx;
701}
702
703SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
704 assert(OpenIdx && "openIntv not called before enterIntvBefore");
705 LLVM_DEBUG(dbgs() << " enterIntvBefore " << Idx);
706 Idx = Idx.getBaseIndex();
707 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
708 if (!ParentVNI) {
709 LLVM_DEBUG(dbgs() << ": not live\n");
710 return Idx;
711 }
712 LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
713 MachineInstr *MI = LIS.getInstructionFromIndex(index: Idx);
714 assert(MI && "enterIntvBefore called with invalid index");
715
716 VNInfo *VNI = defFromParent(RegIdx: OpenIdx, ParentVNI, UseIdx: Idx, MBB&: *MI->getParent(), I: MI);
717 return VNI->def;
718}
719
720SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
721 assert(OpenIdx && "openIntv not called before enterIntvAfter");
722 LLVM_DEBUG(dbgs() << " enterIntvAfter " << Idx);
723 Idx = Idx.getBoundaryIndex();
724 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
725 if (!ParentVNI) {
726 LLVM_DEBUG(dbgs() << ": not live\n");
727 return Idx;
728 }
729 LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
730 MachineInstr *MI = LIS.getInstructionFromIndex(index: Idx);
731 assert(MI && "enterIntvAfter called with invalid index");
732
733 VNInfo *VNI = defFromParent(RegIdx: OpenIdx, ParentVNI, UseIdx: Idx, MBB&: *MI->getParent(),
734 I: std::next(x: MachineBasicBlock::iterator(MI)));
735 return VNI->def;
736}
737
738SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
739 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
740 SlotIndex End = LIS.getMBBEndIdx(mbb: &MBB);
741 SlotIndex Last = End.getPrevSlot();
742 LLVM_DEBUG(dbgs() << " enterIntvAtEnd " << printMBBReference(MBB) << ", "
743 << Last);
744 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx: Last);
745 if (!ParentVNI) {
746 LLVM_DEBUG(dbgs() << ": not live\n");
747 return End;
748 }
749 SlotIndex LSP = SA.getLastSplitPoint(BB: &MBB);
750 if (LSP < Last) {
751 // It could be that the use after LSP is a def, and thus the ParentVNI
752 // just selected starts at that def. For this case to exist, the def
753 // must be part of a tied def/use pair (as otherwise we'd have split
754 // distinct live ranges into individual live intervals), and thus we
755 // can insert the def into the VNI of the use and the tied def/use
756 // pair can live in the resulting interval.
757 Last = LSP;
758 ParentVNI = Edit->getParent().getVNInfoAt(Idx: Last);
759 if (!ParentVNI) {
760 // undef use --> undef tied def
761 LLVM_DEBUG(dbgs() << ": tied use not live\n");
762 return End;
763 }
764 }
765
766 LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id);
767 VNInfo *VNI = defFromParent(RegIdx: OpenIdx, ParentVNI, UseIdx: Last, MBB,
768 I: SA.getLastSplitPointIter(BB: &MBB));
769 RegAssign.insert(a: VNI->def, b: End, y: OpenIdx);
770 LLVM_DEBUG(dump());
771 return VNI->def;
772}
773
774/// useIntv - indicate that all instructions in MBB should use OpenLI.
775void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
776 useIntv(Start: LIS.getMBBStartIdx(mbb: &MBB), End: LIS.getMBBEndIdx(mbb: &MBB));
777}
778
779void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
780 assert(OpenIdx && "openIntv not called before useIntv");
781 LLVM_DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
782 RegAssign.insert(a: Start, b: End, y: OpenIdx);
783 LLVM_DEBUG(dump());
784}
785
786SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
787 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
788 LLVM_DEBUG(dbgs() << " leaveIntvAfter " << Idx);
789
790 // The interval must be live beyond the instruction at Idx.
791 SlotIndex Boundary = Idx.getBoundaryIndex();
792 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx: Boundary);
793 if (!ParentVNI) {
794 LLVM_DEBUG(dbgs() << ": not live\n");
795 return Boundary.getNextSlot();
796 }
797 LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
798 MachineInstr *MI = LIS.getInstructionFromIndex(index: Boundary);
799 assert(MI && "No instruction at index");
800
801 // In spill mode, make live ranges as short as possible by inserting the copy
802 // before MI. This is only possible if that instruction doesn't redefine the
803 // value. The inserted COPY is not a kill, and we don't need to recompute
804 // the source live range. The spiller also won't try to hoist this copy.
805 if (SpillMode && !SlotIndex::isSameInstr(A: ParentVNI->def, B: Idx) &&
806 MI->readsVirtualRegister(Reg: Edit->getReg())) {
807 forceRecompute(RegIdx: 0, ParentVNI: *ParentVNI);
808 defFromParent(RegIdx: 0, ParentVNI, UseIdx: Idx, MBB&: *MI->getParent(), I: MI);
809 return Idx;
810 }
811
812 VNInfo *VNI = defFromParent(RegIdx: 0, ParentVNI, UseIdx: Boundary, MBB&: *MI->getParent(),
813 I: std::next(x: MachineBasicBlock::iterator(MI)));
814 return VNI->def;
815}
816
817SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
818 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
819 LLVM_DEBUG(dbgs() << " leaveIntvBefore " << Idx);
820
821 // The interval must be live into the instruction at Idx.
822 Idx = Idx.getBaseIndex();
823 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
824 if (!ParentVNI) {
825 LLVM_DEBUG(dbgs() << ": not live\n");
826 return Idx.getNextSlot();
827 }
828 LLVM_DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
829
830 MachineInstr *MI = LIS.getInstructionFromIndex(index: Idx);
831 assert(MI && "No instruction at index");
832 VNInfo *VNI = defFromParent(RegIdx: 0, ParentVNI, UseIdx: Idx, MBB&: *MI->getParent(), I: MI);
833 return VNI->def;
834}
835
836SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
837 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
838 SlotIndex Start = LIS.getMBBStartIdx(mbb: &MBB);
839 LLVM_DEBUG(dbgs() << " leaveIntvAtTop " << printMBBReference(MBB) << ", "
840 << Start);
841
842 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx: Start);
843 if (!ParentVNI) {
844 LLVM_DEBUG(dbgs() << ": not live\n");
845 return Start;
846 }
847
848 unsigned RegIdx = 0;
849 Register Reg = LIS.getInterval(Reg: Edit->get(idx: RegIdx)).reg();
850 VNInfo *VNI = defFromParent(RegIdx, ParentVNI, UseIdx: Start, MBB,
851 I: MBB.SkipPHIsLabelsAndDebug(I: MBB.begin(), Reg));
852 RegAssign.insert(a: Start, b: VNI->def, y: OpenIdx);
853 LLVM_DEBUG(dump());
854 return VNI->def;
855}
856
857static bool hasTiedUseOf(MachineInstr &MI, Register Reg) {
858 return any_of(Range: MI.defs(), P: [Reg](const MachineOperand &MO) {
859 return MO.isReg() && MO.isTied() && MO.getReg() == Reg;
860 });
861}
862
863void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
864 assert(OpenIdx && "openIntv not called before overlapIntv");
865 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx: Start);
866 assert(ParentVNI == Edit->getParent().getVNInfoBefore(End) &&
867 "Parent changes value in extended range");
868 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
869 "Range cannot span basic blocks");
870
871 // The complement interval will be extended as needed by LICalc.extend().
872 if (ParentVNI)
873 forceRecompute(RegIdx: 0, ParentVNI: *ParentVNI);
874
875 // If the last use is tied to a def, we can't mark it as live for the
876 // interval which includes only the use. That would cause the tied pair
877 // to end up in two different intervals.
878 if (auto *MI = LIS.getInstructionFromIndex(index: End))
879 if (hasTiedUseOf(MI&: *MI, Reg: Edit->getReg())) {
880 LLVM_DEBUG(dbgs() << "skip overlap due to tied def at end\n");
881 return;
882 }
883
884 LLVM_DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
885 RegAssign.insert(a: Start, b: End, y: OpenIdx);
886 LLVM_DEBUG(dump());
887}
888
889//===----------------------------------------------------------------------===//
890// Spill modes
891//===----------------------------------------------------------------------===//
892
893void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) {
894 LiveInterval *LI = &LIS.getInterval(Reg: Edit->get(idx: 0));
895 LLVM_DEBUG(dbgs() << "Removing " << Copies.size() << " back-copies.\n");
896 RegAssignMap::iterator AssignI;
897 AssignI.setMap(RegAssign);
898
899 for (const VNInfo *C : Copies) {
900 SlotIndex Def = C->def;
901 MachineInstr *MI = LIS.getInstructionFromIndex(index: Def);
902 assert(MI && "No instruction for back-copy");
903
904 MachineBasicBlock *MBB = MI->getParent();
905 MachineBasicBlock::iterator MBBI(MI);
906 bool AtBegin;
907 do AtBegin = MBBI == MBB->begin();
908 while (!AtBegin && (--MBBI)->isDebugOrPseudoInstr());
909
910 LLVM_DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
911 LIS.removeVRegDefAt(LI&: *LI, Pos: Def);
912 LIS.RemoveMachineInstrFromMaps(MI&: *MI);
913 MI->eraseFromParent();
914
915 // Adjust RegAssign if a register assignment is killed at Def. We want to
916 // avoid calculating the live range of the source register if possible.
917 AssignI.find(x: Def.getPrevSlot());
918 if (!AssignI.valid() || AssignI.start() >= Def)
919 continue;
920 // If MI doesn't kill the assigned register, just leave it.
921 if (AssignI.stop() != Def)
922 continue;
923 unsigned RegIdx = AssignI.value();
924 // We could hoist back-copy right after another back-copy. As a result
925 // MMBI points to copy instruction which is actually dead now.
926 // We cannot set its stop to MBBI which will be the same as start and
927 // interval does not support that.
928 SlotIndex Kill =
929 AtBegin ? SlotIndex() : LIS.getInstructionIndex(Instr: *MBBI).getRegSlot();
930 if (AtBegin || !MBBI->readsVirtualRegister(Reg: Edit->getReg()) ||
931 Kill <= AssignI.start()) {
932 LLVM_DEBUG(dbgs() << " cannot find simple kill of RegIdx " << RegIdx
933 << '\n');
934 forceRecompute(RegIdx, ParentVNI: *Edit->getParent().getVNInfoAt(Idx: Def));
935 } else {
936 LLVM_DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI);
937 AssignI.setStop(Kill);
938 }
939 }
940}
941
942MachineBasicBlock*
943SplitEditor::findShallowDominator(MachineBasicBlock *MBB,
944 MachineBasicBlock *DefMBB) {
945 if (MBB == DefMBB)
946 return MBB;
947 assert(MDT.dominates(DefMBB, MBB) && "MBB must be dominated by the def.");
948
949 const MachineLoopInfo &Loops = SA.Loops;
950 const MachineLoop *DefLoop = Loops.getLoopFor(BB: DefMBB);
951 MachineDomTreeNode *DefDomNode = MDT[DefMBB];
952
953 // Best candidate so far.
954 MachineBasicBlock *BestMBB = MBB;
955 unsigned BestDepth = std::numeric_limits<unsigned>::max();
956
957 while (true) {
958 const MachineLoop *Loop = Loops.getLoopFor(BB: MBB);
959
960 // MBB isn't in a loop, it doesn't get any better. All dominators have a
961 // higher frequency by definition.
962 if (!Loop) {
963 LLVM_DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB)
964 << " dominates " << printMBBReference(*MBB)
965 << " at depth 0\n");
966 return MBB;
967 }
968
969 // We'll never be able to exit the DefLoop.
970 if (Loop == DefLoop) {
971 LLVM_DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB)
972 << " dominates " << printMBBReference(*MBB)
973 << " in the same loop\n");
974 return MBB;
975 }
976
977 // Least busy dominator seen so far.
978 unsigned Depth = Loop->getLoopDepth();
979 if (Depth < BestDepth) {
980 BestMBB = MBB;
981 BestDepth = Depth;
982 LLVM_DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB)
983 << " dominates " << printMBBReference(*MBB)
984 << " at depth " << Depth << '\n');
985 }
986
987 // Leave loop by going to the immediate dominator of the loop header.
988 // This is a bigger stride than simply walking up the dominator tree.
989 MachineDomTreeNode *IDom = MDT[Loop->getHeader()]->getIDom();
990
991 // Too far up the dominator tree?
992 if (!IDom || !MDT.dominates(A: DefDomNode, B: IDom))
993 return BestMBB;
994
995 MBB = IDom->getBlock();
996 }
997}
998
999void SplitEditor::computeRedundantBackCopies(
1000 DenseSet<unsigned> &NotToHoistSet, SmallVectorImpl<VNInfo *> &BackCopies) {
1001 LiveInterval *LI = &LIS.getInterval(Reg: Edit->get(idx: 0));
1002 const LiveInterval *Parent = &Edit->getParent();
1003 SmallVector<SmallPtrSet<VNInfo *, 8>, 8> EqualVNs(Parent->getNumValNums());
1004 SmallPtrSet<VNInfo *, 8> DominatedVNIs;
1005
1006 // Aggregate VNIs having the same value as ParentVNI.
1007 for (VNInfo *VNI : LI->valnos) {
1008 if (VNI->isUnused())
1009 continue;
1010 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx: VNI->def);
1011 EqualVNs[ParentVNI->id].insert(Ptr: VNI);
1012 }
1013
1014 // For VNI aggregation of each ParentVNI, collect dominated, i.e.,
1015 // redundant VNIs to BackCopies.
1016 for (unsigned i = 0, e = Parent->getNumValNums(); i != e; ++i) {
1017 const VNInfo *ParentVNI = Parent->getValNumInfo(ValNo: i);
1018 if (!NotToHoistSet.count(V: ParentVNI->id))
1019 continue;
1020 SmallPtrSetIterator<VNInfo *> It1 = EqualVNs[ParentVNI->id].begin();
1021 SmallPtrSetIterator<VNInfo *> It2 = It1;
1022 for (; It1 != EqualVNs[ParentVNI->id].end(); ++It1) {
1023 It2 = It1;
1024 for (++It2; It2 != EqualVNs[ParentVNI->id].end(); ++It2) {
1025 if (DominatedVNIs.count(Ptr: *It1) || DominatedVNIs.count(Ptr: *It2))
1026 continue;
1027
1028 MachineBasicBlock *MBB1 = LIS.getMBBFromIndex(index: (*It1)->def);
1029 MachineBasicBlock *MBB2 = LIS.getMBBFromIndex(index: (*It2)->def);
1030 if (MBB1 == MBB2) {
1031 DominatedVNIs.insert(Ptr: (*It1)->def < (*It2)->def ? (*It2) : (*It1));
1032 } else if (MDT.dominates(A: MBB1, B: MBB2)) {
1033 DominatedVNIs.insert(Ptr: *It2);
1034 } else if (MDT.dominates(A: MBB2, B: MBB1)) {
1035 DominatedVNIs.insert(Ptr: *It1);
1036 }
1037 }
1038 }
1039 if (!DominatedVNIs.empty()) {
1040 forceRecompute(RegIdx: 0, ParentVNI: *ParentVNI);
1041 append_range(C&: BackCopies, R&: DominatedVNIs);
1042 DominatedVNIs.clear();
1043 }
1044 }
1045}
1046
1047/// For SM_Size mode, find a common dominator for all the back-copies for
1048/// the same ParentVNI and hoist the backcopies to the dominator BB.
1049/// For SM_Speed mode, if the common dominator is hot and it is not beneficial
1050/// to do the hoisting, simply remove the dominated backcopies for the same
1051/// ParentVNI.
1052void SplitEditor::hoistCopies() {
1053 // Get the complement interval, always RegIdx 0.
1054 LiveInterval *LI = &LIS.getInterval(Reg: Edit->get(idx: 0));
1055 const LiveInterval *Parent = &Edit->getParent();
1056
1057 // Track the nearest common dominator for all back-copies for each ParentVNI,
1058 // indexed by ParentVNI->id.
1059 using DomPair = std::pair<MachineBasicBlock *, SlotIndex>;
1060 SmallVector<DomPair, 8> NearestDom(Parent->getNumValNums());
1061 // The total cost of all the back-copies for each ParentVNI.
1062 SmallVector<BlockFrequency, 8> Costs(Parent->getNumValNums());
1063 // The ParentVNI->id set for which hoisting back-copies are not beneficial
1064 // for Speed.
1065 DenseSet<unsigned> NotToHoistSet;
1066
1067 // Find the nearest common dominator for parent values with multiple
1068 // back-copies. If a single back-copy dominates, put it in DomPair.second.
1069 for (VNInfo *VNI : LI->valnos) {
1070 if (VNI->isUnused())
1071 continue;
1072 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx: VNI->def);
1073 assert(ParentVNI && "Parent not live at complement def");
1074
1075 // Don't hoist remats. The complement is probably going to disappear
1076 // completely anyway.
1077 if (Edit->didRematerialize(ParentVNI))
1078 continue;
1079
1080 MachineBasicBlock *ValMBB = LIS.getMBBFromIndex(index: VNI->def);
1081
1082 DomPair &Dom = NearestDom[ParentVNI->id];
1083
1084 // Keep directly defined parent values. This is either a PHI or an
1085 // instruction in the complement range. All other copies of ParentVNI
1086 // should be eliminated.
1087 if (VNI->def == ParentVNI->def) {
1088 LLVM_DEBUG(dbgs() << "Direct complement def at " << VNI->def << '\n');
1089 Dom = DomPair(ValMBB, VNI->def);
1090 continue;
1091 }
1092 // Skip the singly mapped values. There is nothing to gain from hoisting a
1093 // single back-copy.
1094 if (Values.lookup(Val: std::make_pair(x: 0, y&: ParentVNI->id)).getPointer()) {
1095 LLVM_DEBUG(dbgs() << "Single complement def at " << VNI->def << '\n');
1096 continue;
1097 }
1098
1099 if (!Dom.first) {
1100 // First time we see ParentVNI. VNI dominates itself.
1101 Dom = DomPair(ValMBB, VNI->def);
1102 } else if (Dom.first == ValMBB) {
1103 // Two defs in the same block. Pick the earlier def.
1104 if (!Dom.second.isValid() || VNI->def < Dom.second)
1105 Dom.second = VNI->def;
1106 } else {
1107 // Different basic blocks. Check if one dominates.
1108 MachineBasicBlock *Near =
1109 MDT.findNearestCommonDominator(A: Dom.first, B: ValMBB);
1110 if (Near == ValMBB)
1111 // Def ValMBB dominates.
1112 Dom = DomPair(ValMBB, VNI->def);
1113 else if (Near != Dom.first)
1114 // None dominate. Hoist to common dominator, need new def.
1115 Dom = DomPair(Near, SlotIndex());
1116 Costs[ParentVNI->id] += MBFI.getBlockFreq(MBB: ValMBB);
1117 }
1118
1119 LLVM_DEBUG(dbgs() << "Multi-mapped complement " << VNI->id << '@'
1120 << VNI->def << " for parent " << ParentVNI->id << '@'
1121 << ParentVNI->def << " hoist to "
1122 << printMBBReference(*Dom.first) << ' ' << Dom.second
1123 << '\n');
1124 }
1125
1126 // Insert the hoisted copies.
1127 for (unsigned i = 0, e = Parent->getNumValNums(); i != e; ++i) {
1128 DomPair &Dom = NearestDom[i];
1129 if (!Dom.first || Dom.second.isValid())
1130 continue;
1131 // This value needs a hoisted copy inserted at the end of Dom.first.
1132 const VNInfo *ParentVNI = Parent->getValNumInfo(ValNo: i);
1133 MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(index: ParentVNI->def);
1134 // Get a less loopy dominator than Dom.first.
1135 Dom.first = findShallowDominator(MBB: Dom.first, DefMBB);
1136 if (SpillMode == SM_Speed &&
1137 MBFI.getBlockFreq(MBB: Dom.first) > Costs[ParentVNI->id]) {
1138 NotToHoistSet.insert(V: ParentVNI->id);
1139 continue;
1140 }
1141 SlotIndex LSP = SA.getLastSplitPoint(BB: Dom.first);
1142 if (LSP <= ParentVNI->def) {
1143 NotToHoistSet.insert(V: ParentVNI->id);
1144 continue;
1145 }
1146 Dom.second = defFromParent(RegIdx: 0, ParentVNI, UseIdx: LSP, MBB&: *Dom.first,
1147 I: SA.getLastSplitPointIter(BB: Dom.first))->def;
1148 }
1149
1150 // Remove redundant back-copies that are now known to be dominated by another
1151 // def with the same value.
1152 SmallVector<VNInfo*, 8> BackCopies;
1153 for (VNInfo *VNI : LI->valnos) {
1154 if (VNI->isUnused())
1155 continue;
1156 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx: VNI->def);
1157 const DomPair &Dom = NearestDom[ParentVNI->id];
1158 if (!Dom.first || Dom.second == VNI->def ||
1159 NotToHoistSet.count(V: ParentVNI->id))
1160 continue;
1161 BackCopies.push_back(Elt: VNI);
1162 forceRecompute(RegIdx: 0, ParentVNI: *ParentVNI);
1163 }
1164
1165 // If it is not beneficial to hoist all the BackCopies, simply remove
1166 // redundant BackCopies in speed mode.
1167 if (SpillMode == SM_Speed && !NotToHoistSet.empty())
1168 computeRedundantBackCopies(NotToHoistSet, BackCopies);
1169
1170 removeBackCopies(Copies&: BackCopies);
1171}
1172
1173/// transferValues - Transfer all possible values to the new live ranges.
1174/// Values that were rematerialized are left alone, they need LICalc.extend().
1175bool SplitEditor::transferValues() {
1176 bool Skipped = false;
1177 RegAssignMap::const_iterator AssignI = RegAssign.begin();
1178 for (const LiveRange::Segment &S : Edit->getParent()) {
1179 LLVM_DEBUG(dbgs() << " blit " << S << ':');
1180 VNInfo *ParentVNI = S.valno;
1181 // RegAssign has holes where RegIdx 0 should be used.
1182 SlotIndex Start = S.start;
1183 AssignI.advanceTo(x: Start);
1184 do {
1185 unsigned RegIdx;
1186 SlotIndex End = S.end;
1187 if (!AssignI.valid()) {
1188 RegIdx = 0;
1189 } else if (AssignI.start() <= Start) {
1190 RegIdx = AssignI.value();
1191 if (AssignI.stop() < End) {
1192 End = AssignI.stop();
1193 ++AssignI;
1194 }
1195 } else {
1196 RegIdx = 0;
1197 End = std::min(a: End, b: AssignI.start());
1198 }
1199
1200 // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
1201 LLVM_DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx << '('
1202 << printReg(Edit->get(RegIdx)) << ')');
1203 LiveInterval &LI = LIS.getInterval(Reg: Edit->get(idx: RegIdx));
1204
1205 // Check for a simply defined value that can be blitted directly.
1206 ValueForcePair VFP = Values.lookup(Val: std::make_pair(x&: RegIdx, y&: ParentVNI->id));
1207 if (VNInfo *VNI = VFP.getPointer()) {
1208 LLVM_DEBUG(dbgs() << ':' << VNI->id);
1209 LI.addSegment(S: LiveInterval::Segment(Start, End, VNI));
1210 Start = End;
1211 continue;
1212 }
1213
1214 // Skip values with forced recomputation.
1215 if (VFP.getInt()) {
1216 LLVM_DEBUG(dbgs() << "(recalc)");
1217 Skipped = true;
1218 Start = End;
1219 continue;
1220 }
1221
1222 LiveIntervalCalc &LIC = getLICalc(RegIdx);
1223
1224 // This value has multiple defs in RegIdx, but it wasn't rematerialized,
1225 // so the live range is accurate. Add live-in blocks in [Start;End) to the
1226 // LiveInBlocks.
1227 MachineFunction::iterator MBB = LIS.getMBBFromIndex(index: Start)->getIterator();
1228 SlotIndex BlockStart, BlockEnd;
1229 std::tie(args&: BlockStart, args&: BlockEnd) = LIS.getSlotIndexes()->getMBBRange(MBB: &*MBB);
1230
1231 // The first block may be live-in, or it may have its own def.
1232 if (Start != BlockStart) {
1233 VNInfo *VNI = LI.extendInBlock(StartIdx: BlockStart, Kill: std::min(a: BlockEnd, b: End));
1234 assert(VNI && "Missing def for complex mapped value");
1235 LLVM_DEBUG(dbgs() << ':' << VNI->id << "*" << printMBBReference(*MBB));
1236 // MBB has its own def. Is it also live-out?
1237 if (BlockEnd <= End)
1238 LIC.setLiveOutValue(MBB: &*MBB, VNI);
1239
1240 // Skip to the next block for live-in.
1241 ++MBB;
1242 BlockStart = BlockEnd;
1243 }
1244
1245 // Handle the live-in blocks covered by [Start;End).
1246 assert(Start <= BlockStart && "Expected live-in block");
1247 while (BlockStart < End) {
1248 LLVM_DEBUG(dbgs() << ">" << printMBBReference(*MBB));
1249 BlockEnd = LIS.getMBBEndIdx(mbb: &*MBB);
1250 if (BlockStart == ParentVNI->def) {
1251 // This block has the def of a parent PHI, so it isn't live-in.
1252 assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
1253 VNInfo *VNI = LI.extendInBlock(StartIdx: BlockStart, Kill: std::min(a: BlockEnd, b: End));
1254 assert(VNI && "Missing def for complex mapped parent PHI");
1255 if (End >= BlockEnd)
1256 LIC.setLiveOutValue(MBB: &*MBB, VNI); // Live-out as well.
1257 } else {
1258 // This block needs a live-in value. The last block covered may not
1259 // be live-out.
1260 if (End < BlockEnd)
1261 LIC.addLiveInBlock(LR&: LI, DomNode: MDT[&*MBB], Kill: End);
1262 else {
1263 // Live-through, and we don't know the value.
1264 LIC.addLiveInBlock(LR&: LI, DomNode: MDT[&*MBB]);
1265 LIC.setLiveOutValue(MBB: &*MBB, VNI: nullptr);
1266 }
1267 }
1268 BlockStart = BlockEnd;
1269 ++MBB;
1270 }
1271 Start = End;
1272 } while (Start != S.end);
1273 LLVM_DEBUG(dbgs() << '\n');
1274 }
1275
1276 LICalc[0].calculateValues();
1277 if (SpillMode)
1278 LICalc[1].calculateValues();
1279
1280 return Skipped;
1281}
1282
1283static bool removeDeadSegment(SlotIndex Def, LiveRange &LR) {
1284 const LiveRange::Segment *Seg = LR.getSegmentContaining(Idx: Def);
1285 if (Seg == nullptr)
1286 return true;
1287 if (Seg->end != Def.getDeadSlot())
1288 return false;
1289 // This is a dead PHI. Remove it.
1290 LR.removeSegment(S: *Seg, RemoveDeadValNo: true);
1291 return true;
1292}
1293
1294void SplitEditor::extendPHIRange(MachineBasicBlock &B, LiveIntervalCalc &LIC,
1295 LiveRange &LR, LaneBitmask LM,
1296 ArrayRef<SlotIndex> Undefs) {
1297 for (MachineBasicBlock *P : B.predecessors()) {
1298 SlotIndex End = LIS.getMBBEndIdx(mbb: P);
1299 SlotIndex LastUse = End.getPrevSlot();
1300 // The predecessor may not have a live-out value. That is OK, like an
1301 // undef PHI operand.
1302 const LiveInterval &PLI = Edit->getParent();
1303 // Need the cast because the inputs to ?: would otherwise be deemed
1304 // "incompatible": SubRange vs LiveInterval.
1305 const LiveRange &PSR = !LM.all() ? getSubRangeForMaskExact(LM, LI: PLI)
1306 : static_cast<const LiveRange &>(PLI);
1307 if (PSR.liveAt(index: LastUse))
1308 LIC.extend(LR, Use: End, /*PhysReg=*/0, Undefs);
1309 }
1310}
1311
1312void SplitEditor::extendPHIKillRanges() {
1313 // Extend live ranges to be live-out for successor PHI values.
1314
1315 // Visit each PHI def slot in the parent live interval. If the def is dead,
1316 // remove it. Otherwise, extend the live interval to reach the end indexes
1317 // of all predecessor blocks.
1318
1319 const LiveInterval &ParentLI = Edit->getParent();
1320 for (const VNInfo *V : ParentLI.valnos) {
1321 if (V->isUnused() || !V->isPHIDef())
1322 continue;
1323
1324 unsigned RegIdx = RegAssign.lookup(x: V->def);
1325 LiveInterval &LI = LIS.getInterval(Reg: Edit->get(idx: RegIdx));
1326 LiveIntervalCalc &LIC = getLICalc(RegIdx);
1327 MachineBasicBlock &B = *LIS.getMBBFromIndex(index: V->def);
1328 if (!removeDeadSegment(Def: V->def, LR&: LI))
1329 extendPHIRange(B, LIC, LR&: LI, LM: LaneBitmask::getAll(), /*Undefs=*/{});
1330 }
1331
1332 SmallVector<SlotIndex, 4> Undefs;
1333 LiveIntervalCalc SubLIC;
1334
1335 for (const LiveInterval::SubRange &PS : ParentLI.subranges()) {
1336 for (const VNInfo *V : PS.valnos) {
1337 if (V->isUnused() || !V->isPHIDef())
1338 continue;
1339 unsigned RegIdx = RegAssign.lookup(x: V->def);
1340 LiveInterval &LI = LIS.getInterval(Reg: Edit->get(idx: RegIdx));
1341 LiveInterval::SubRange &S = getSubRangeForMaskExact(LM: PS.LaneMask, LI);
1342 if (removeDeadSegment(Def: V->def, LR&: S))
1343 continue;
1344
1345 MachineBasicBlock &B = *LIS.getMBBFromIndex(index: V->def);
1346 SubLIC.reset(mf: &VRM.getMachineFunction(), SI: LIS.getSlotIndexes(), MDT: &MDT,
1347 VNIA: &LIS.getVNInfoAllocator());
1348 Undefs.clear();
1349 LI.computeSubRangeUndefs(Undefs, LaneMask: PS.LaneMask, MRI, Indexes: *LIS.getSlotIndexes());
1350 extendPHIRange(B, LIC&: SubLIC, LR&: S, LM: PS.LaneMask, Undefs);
1351 }
1352 }
1353}
1354
1355/// rewriteAssigned - Rewrite all uses of Edit->getReg().
1356void SplitEditor::rewriteAssigned(bool ExtendRanges) {
1357 struct ExtPoint {
1358 ExtPoint(const MachineOperand &O, unsigned R, SlotIndex N)
1359 : MO(O), RegIdx(R), Next(N) {}
1360
1361 MachineOperand MO;
1362 unsigned RegIdx;
1363 SlotIndex Next;
1364 };
1365
1366 SmallVector<ExtPoint,4> ExtPoints;
1367
1368 for (MachineOperand &MO :
1369 llvm::make_early_inc_range(Range: MRI.reg_operands(Reg: Edit->getReg()))) {
1370 MachineInstr *MI = MO.getParent();
1371 // LiveDebugVariables should have handled all DBG_VALUE instructions.
1372 if (MI->isDebugValue()) {
1373 LLVM_DEBUG(dbgs() << "Zapping " << *MI);
1374 MO.setReg(0);
1375 continue;
1376 }
1377
1378 // <undef> operands don't really read the register, so it doesn't matter
1379 // which register we choose. When the use operand is tied to a def, we must
1380 // use the same register as the def, so just do that always.
1381 SlotIndex Idx = LIS.getInstructionIndex(Instr: *MI);
1382 if (MO.isDef() || MO.isUndef())
1383 Idx = Idx.getRegSlot(EC: MO.isEarlyClobber());
1384
1385 // Rewrite to the mapped register at Idx.
1386 unsigned RegIdx = RegAssign.lookup(x: Idx);
1387 LiveInterval &LI = LIS.getInterval(Reg: Edit->get(idx: RegIdx));
1388 MO.setReg(LI.reg());
1389 LLVM_DEBUG(dbgs() << " rewr " << printMBBReference(*MI->getParent())
1390 << '\t' << Idx << ':' << RegIdx << '\t' << *MI);
1391
1392 // Extend liveness to Idx if the instruction reads reg.
1393 if (!ExtendRanges || MO.isUndef())
1394 continue;
1395
1396 // Skip instructions that don't read Reg.
1397 if (MO.isDef()) {
1398 if (!MO.getSubReg() && !MO.isEarlyClobber())
1399 continue;
1400 // We may want to extend a live range for a partial redef, or for a use
1401 // tied to an early clobber.
1402 if (!Edit->getParent().liveAt(index: Idx.getPrevSlot()))
1403 continue;
1404 } else {
1405 assert(MO.isUse());
1406 bool IsEarlyClobber = false;
1407 if (MO.isTied()) {
1408 // We want to extend a live range into `e` slot rather than `r` slot if
1409 // tied-def is early clobber, because the `e` slot already contained
1410 // in the live range of early-clobber tied-def operand, give an example
1411 // here:
1412 // 0 %0 = ...
1413 // 16 early-clobber %0 = Op %0 (tied-def 0), ...
1414 // 32 ... = Op %0
1415 // Before extend:
1416 // %0 = [0r, 0d) [16e, 32d)
1417 // The point we want to extend is 0d to 16e not 16r in this case, but if
1418 // we use 16r here we will extend nothing because that already contained
1419 // in [16e, 32d).
1420 unsigned OpIdx = MO.getOperandNo();
1421 unsigned DefOpIdx = MI->findTiedOperandIdx(OpIdx);
1422 const MachineOperand &DefOp = MI->getOperand(i: DefOpIdx);
1423 IsEarlyClobber = DefOp.isEarlyClobber();
1424 }
1425
1426 Idx = Idx.getRegSlot(EC: IsEarlyClobber);
1427 }
1428
1429 SlotIndex Next = Idx;
1430 if (LI.hasSubRanges()) {
1431 // We have to delay extending subranges until we have seen all operands
1432 // defining the register. This is because a <def,read-undef> operand
1433 // will create an "undef" point, and we cannot extend any subranges
1434 // until all of them have been accounted for.
1435 if (MO.isUse())
1436 ExtPoints.push_back(Elt: ExtPoint(MO, RegIdx, Next));
1437 } else {
1438 LiveIntervalCalc &LIC = getLICalc(RegIdx);
1439 LIC.extend(LR&: LI, Use: Next, PhysReg: 0, Undefs: ArrayRef<SlotIndex>());
1440 }
1441 }
1442
1443 for (ExtPoint &EP : ExtPoints) {
1444 LiveInterval &LI = LIS.getInterval(Reg: Edit->get(idx: EP.RegIdx));
1445 assert(LI.hasSubRanges());
1446
1447 LiveIntervalCalc SubLIC;
1448 Register Reg = EP.MO.getReg();
1449 unsigned Sub = EP.MO.getSubReg();
1450 LaneBitmask LM = Sub != 0 ? TRI.getSubRegIndexLaneMask(SubIdx: Sub)
1451 : MRI.getMaxLaneMaskForVReg(Reg);
1452 for (LiveInterval::SubRange &S : LI.subranges()) {
1453 if ((S.LaneMask & LM).none())
1454 continue;
1455 // The problem here can be that the new register may have been created
1456 // for a partially defined original register. For example:
1457 // %0:subreg_hireg<def,read-undef> = ...
1458 // ...
1459 // %1 = COPY %0
1460 if (S.empty())
1461 continue;
1462 SubLIC.reset(mf: &VRM.getMachineFunction(), SI: LIS.getSlotIndexes(), MDT: &MDT,
1463 VNIA: &LIS.getVNInfoAllocator());
1464 SmallVector<SlotIndex, 4> Undefs;
1465 LI.computeSubRangeUndefs(Undefs, LaneMask: S.LaneMask, MRI, Indexes: *LIS.getSlotIndexes());
1466 SubLIC.extend(LR&: S, Use: EP.Next, PhysReg: 0, Undefs);
1467 }
1468 }
1469
1470 for (Register R : *Edit) {
1471 LiveInterval &LI = LIS.getInterval(Reg: R);
1472 if (!LI.hasSubRanges())
1473 continue;
1474 LI.clear();
1475 LI.removeEmptySubRanges();
1476 LIS.constructMainRangeFromSubranges(LI);
1477 }
1478}
1479
1480void SplitEditor::deleteRematVictims() {
1481 SmallVector<MachineInstr*, 8> Dead;
1482 for (const Register &R : *Edit) {
1483 LiveInterval *LI = &LIS.getInterval(Reg: R);
1484 for (const LiveRange::Segment &S : LI->segments) {
1485 // Dead defs end at the dead slot.
1486 if (S.end != S.valno->def.getDeadSlot())
1487 continue;
1488 if (S.valno->isPHIDef())
1489 continue;
1490 MachineInstr *MI = LIS.getInstructionFromIndex(index: S.valno->def);
1491 assert(MI && "Missing instruction for dead def");
1492 MI->addRegisterDead(Reg: LI->reg(), RegInfo: &TRI);
1493
1494 if (!MI->allDefsAreDead())
1495 continue;
1496
1497 LLVM_DEBUG(dbgs() << "All defs dead: " << *MI);
1498 Dead.push_back(Elt: MI);
1499 }
1500 }
1501
1502 if (Dead.empty())
1503 return;
1504
1505 Edit->eliminateDeadDefs(Dead, RegsBeingSpilled: {});
1506}
1507
1508void SplitEditor::forceRecomputeVNI(const VNInfo &ParentVNI) {
1509 // Fast-path for common case.
1510 if (!ParentVNI.isPHIDef()) {
1511 for (unsigned I = 0, E = Edit->size(); I != E; ++I)
1512 forceRecompute(RegIdx: I, ParentVNI);
1513 return;
1514 }
1515
1516 // Trace value through phis.
1517 ///< whether VNI was/is in worklist.
1518 SmallPtrSet<const VNInfo *, 8> Visited = {&ParentVNI};
1519 SmallVector<const VNInfo *, 4> WorkList = {&ParentVNI};
1520
1521 const LiveInterval &ParentLI = Edit->getParent();
1522 const SlotIndexes &Indexes = *LIS.getSlotIndexes();
1523 do {
1524 const VNInfo &VNI = *WorkList.pop_back_val();
1525 for (unsigned I = 0, E = Edit->size(); I != E; ++I)
1526 forceRecompute(RegIdx: I, ParentVNI: VNI);
1527 if (!VNI.isPHIDef())
1528 continue;
1529
1530 MachineBasicBlock &MBB = *Indexes.getMBBFromIndex(index: VNI.def);
1531 for (const MachineBasicBlock *Pred : MBB.predecessors()) {
1532 SlotIndex PredEnd = Indexes.getMBBEndIdx(mbb: Pred);
1533 VNInfo *PredVNI = ParentLI.getVNInfoBefore(Idx: PredEnd);
1534 assert(PredVNI && "Value available in PhiVNI predecessor");
1535 if (Visited.insert(Ptr: PredVNI).second)
1536 WorkList.push_back(Elt: PredVNI);
1537 }
1538 } while(!WorkList.empty());
1539}
1540
1541void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
1542 ++NumFinished;
1543
1544 // At this point, the live intervals in Edit contain VNInfos corresponding to
1545 // the inserted copies.
1546
1547 // Add the original defs from the parent interval.
1548 for (const VNInfo *ParentVNI : Edit->getParent().valnos) {
1549 if (ParentVNI->isUnused())
1550 continue;
1551 unsigned RegIdx = RegAssign.lookup(x: ParentVNI->def);
1552 defValue(RegIdx, ParentVNI, Idx: ParentVNI->def, Original: true);
1553
1554 // Force rematted values to be recomputed everywhere.
1555 // The new live ranges may be truncated.
1556 if (Edit->didRematerialize(ParentVNI))
1557 forceRecomputeVNI(ParentVNI: *ParentVNI);
1558 }
1559
1560 // Hoist back-copies to the complement interval when in spill mode.
1561 switch (SpillMode) {
1562 case SM_Partition:
1563 // Leave all back-copies as is.
1564 break;
1565 case SM_Size:
1566 case SM_Speed:
1567 // hoistCopies will behave differently between size and speed.
1568 hoistCopies();
1569 }
1570
1571 // Transfer the simply mapped values, check if any are skipped.
1572 bool Skipped = transferValues();
1573
1574 // Rewrite virtual registers, possibly extending ranges.
1575 rewriteAssigned(ExtendRanges: Skipped);
1576
1577 if (Skipped)
1578 extendPHIKillRanges();
1579 else
1580 ++NumSimple;
1581
1582 // Delete defs that were rematted everywhere.
1583 if (Skipped)
1584 deleteRematVictims();
1585
1586 // Get rid of unused values and set phi-kill flags.
1587 for (Register Reg : *Edit) {
1588 LiveInterval &LI = LIS.getInterval(Reg);
1589 LI.removeEmptySubRanges();
1590 LI.RenumberValues();
1591 }
1592
1593 // Provide a reverse mapping from original indices to Edit ranges.
1594 if (LRMap) {
1595 auto Seq = llvm::seq<unsigned>(Begin: 0, End: Edit->size());
1596 LRMap->assign(in_start: Seq.begin(), in_end: Seq.end());
1597 }
1598
1599 // Now check if any registers were separated into multiple components.
1600 ConnectedVNInfoEqClasses ConEQ(LIS);
1601 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
1602 // Don't use iterators, they are invalidated by create() below.
1603 Register VReg = Edit->get(idx: i);
1604 LiveInterval &LI = LIS.getInterval(Reg: VReg);
1605 SmallVector<LiveInterval*, 8> SplitLIs;
1606 LIS.splitSeparateComponents(LI, SplitLIs);
1607 Register Original = VRM.getOriginal(VirtReg: VReg);
1608 for (LiveInterval *SplitLI : SplitLIs)
1609 VRM.setIsSplitFromReg(virtReg: SplitLI->reg(), SReg: Original);
1610
1611 // The new intervals all map back to i.
1612 if (LRMap)
1613 LRMap->resize(N: Edit->size(), NV: i);
1614 }
1615
1616 // Calculate spill weight and allocation hints for new intervals.
1617 Edit->calculateRegClassAndHint(VRM.getMachineFunction(), VRAI);
1618
1619 assert(!LRMap || LRMap->size() == Edit->size());
1620}
1621
1622//===----------------------------------------------------------------------===//
1623// Single Block Splitting
1624//===----------------------------------------------------------------------===//
1625
1626bool SplitAnalysis::shouldSplitSingleBlock(const BlockInfo &BI,
1627 bool SingleInstrs) const {
1628 // Always split for multiple instructions.
1629 if (!BI.isOneInstr())
1630 return true;
1631 // Don't split for single instructions unless explicitly requested.
1632 if (!SingleInstrs)
1633 return false;
1634 // Splitting a live-through range always makes progress.
1635 if (BI.LiveIn && BI.LiveOut)
1636 return true;
1637 // No point in isolating a copy. It has no register class constraints.
1638 MachineInstr *MI = LIS.getInstructionFromIndex(index: BI.FirstInstr);
1639 bool copyLike = TII.isCopyInstr(MI: *MI) || MI->isSubregToReg();
1640 if (copyLike)
1641 return false;
1642 // Finally, don't isolate an end point that was created by earlier splits.
1643 return isOriginalEndpoint(Idx: BI.FirstInstr);
1644}
1645
1646void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
1647 openIntv();
1648 SlotIndex LastSplitPoint = SA.getLastSplitPoint(BB: BI.MBB);
1649 SlotIndex SegStart = enterIntvBefore(Idx: std::min(a: BI.FirstInstr,
1650 b: LastSplitPoint));
1651 if (!BI.LiveOut || BI.LastInstr < LastSplitPoint) {
1652 useIntv(Start: SegStart, End: leaveIntvAfter(Idx: BI.LastInstr));
1653 } else {
1654 // The last use is after the last valid split point.
1655 SlotIndex SegStop = leaveIntvBefore(Idx: LastSplitPoint);
1656 useIntv(Start: SegStart, End: SegStop);
1657 overlapIntv(Start: SegStop, End: BI.LastInstr);
1658 }
1659}
1660
1661//===----------------------------------------------------------------------===//
1662// Global Live Range Splitting Support
1663//===----------------------------------------------------------------------===//
1664
1665// These methods support a method of global live range splitting that uses a
1666// global algorithm to decide intervals for CFG edges. They will insert split
1667// points and color intervals in basic blocks while avoiding interference.
1668//
1669// Note that splitSingleBlock is also useful for blocks where both CFG edges
1670// are on the stack.
1671
1672void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
1673 unsigned IntvIn, SlotIndex LeaveBefore,
1674 unsigned IntvOut, SlotIndex EnterAfter){
1675 SlotIndex Start, Stop;
1676 std::tie(args&: Start, args&: Stop) = LIS.getSlotIndexes()->getMBBRange(Num: MBBNum);
1677
1678 LLVM_DEBUG(dbgs() << "%bb." << MBBNum << " [" << Start << ';' << Stop
1679 << ") intf " << LeaveBefore << '-' << EnterAfter
1680 << ", live-through " << IntvIn << " -> " << IntvOut);
1681
1682 assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
1683
1684 assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
1685 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
1686 assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
1687
1688 MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(N: MBBNum);
1689
1690 if (!IntvOut) {
1691 LLVM_DEBUG(dbgs() << ", spill on entry.\n");
1692 //
1693 // <<<<<<<<< Possible LeaveBefore interference.
1694 // |-----------| Live through.
1695 // -____________ Spill on entry.
1696 //
1697 selectIntv(Idx: IntvIn);
1698 SlotIndex Idx = leaveIntvAtTop(MBB&: *MBB);
1699 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1700 (void)Idx;
1701 return;
1702 }
1703
1704 if (!IntvIn) {
1705 LLVM_DEBUG(dbgs() << ", reload on exit.\n");
1706 //
1707 // >>>>>>> Possible EnterAfter interference.
1708 // |-----------| Live through.
1709 // ___________-- Reload on exit.
1710 //
1711 selectIntv(Idx: IntvOut);
1712 SlotIndex Idx = enterIntvAtEnd(MBB&: *MBB);
1713 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1714 (void)Idx;
1715 return;
1716 }
1717
1718 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
1719 LLVM_DEBUG(dbgs() << ", straight through.\n");
1720 //
1721 // |-----------| Live through.
1722 // ------------- Straight through, same intv, no interference.
1723 //
1724 selectIntv(Idx: IntvOut);
1725 useIntv(Start, End: Stop);
1726 return;
1727 }
1728
1729 // We cannot legally insert splits after LSP.
1730 SlotIndex LSP = SA.getLastSplitPoint(Num: MBBNum);
1731 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
1732
1733 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
1734 LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
1735 LLVM_DEBUG(dbgs() << ", switch avoiding interference.\n");
1736 //
1737 // >>>> <<<< Non-overlapping EnterAfter/LeaveBefore interference.
1738 // |-----------| Live through.
1739 // ------======= Switch intervals between interference.
1740 //
1741 selectIntv(Idx: IntvOut);
1742 SlotIndex Idx;
1743 if (LeaveBefore && LeaveBefore < LSP) {
1744 Idx = enterIntvBefore(Idx: LeaveBefore);
1745 useIntv(Start: Idx, End: Stop);
1746 } else {
1747 Idx = enterIntvAtEnd(MBB&: *MBB);
1748 }
1749 selectIntv(Idx: IntvIn);
1750 useIntv(Start, End: Idx);
1751 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1752 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1753 return;
1754 }
1755
1756 LLVM_DEBUG(dbgs() << ", create local intv for interference.\n");
1757 //
1758 // >>><><><><<<< Overlapping EnterAfter/LeaveBefore interference.
1759 // |-----------| Live through.
1760 // ==---------== Switch intervals before/after interference.
1761 //
1762 assert(LeaveBefore <= EnterAfter && "Missed case");
1763
1764 selectIntv(Idx: IntvOut);
1765 SlotIndex Idx = enterIntvAfter(Idx: EnterAfter);
1766 useIntv(Start: Idx, End: Stop);
1767 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1768
1769 selectIntv(Idx: IntvIn);
1770 Idx = leaveIntvBefore(Idx: LeaveBefore);
1771 useIntv(Start, End: Idx);
1772 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1773}
1774
1775void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
1776 unsigned IntvIn, SlotIndex LeaveBefore) {
1777 SlotIndex Start, Stop;
1778 std::tie(args&: Start, args&: Stop) = LIS.getSlotIndexes()->getMBBRange(MBB: BI.MBB);
1779
1780 LLVM_DEBUG(dbgs() << printMBBReference(*BI.MBB) << " [" << Start << ';'
1781 << Stop << "), uses " << BI.FirstInstr << '-'
1782 << BI.LastInstr << ", reg-in " << IntvIn
1783 << ", leave before " << LeaveBefore
1784 << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1785
1786 assert(IntvIn && "Must have register in");
1787 assert(BI.LiveIn && "Must be live-in");
1788 assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1789
1790 if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastInstr)) {
1791 LLVM_DEBUG(dbgs() << " before interference.\n");
1792 //
1793 // <<< Interference after kill.
1794 // |---o---x | Killed in block.
1795 // ========= Use IntvIn everywhere.
1796 //
1797 selectIntv(Idx: IntvIn);
1798 useIntv(Start, End: BI.LastInstr);
1799 return;
1800 }
1801
1802 SlotIndex LSP = SA.getLastSplitPoint(BB: BI.MBB);
1803
1804 if (!LeaveBefore || LeaveBefore > BI.LastInstr.getBoundaryIndex()) {
1805 //
1806 // <<< Possible interference after last use.
1807 // |---o---o---| Live-out on stack.
1808 // =========____ Leave IntvIn after last use.
1809 //
1810 // < Interference after last use.
1811 // |---o---o--o| Live-out on stack, late last use.
1812 // ============ Copy to stack after LSP, overlap IntvIn.
1813 // \_____ Stack interval is live-out.
1814 //
1815 if (BI.LastInstr < LSP) {
1816 LLVM_DEBUG(dbgs() << ", spill after last use before interference.\n");
1817 selectIntv(Idx: IntvIn);
1818 SlotIndex Idx = leaveIntvAfter(Idx: BI.LastInstr);
1819 useIntv(Start, End: Idx);
1820 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1821 } else {
1822 LLVM_DEBUG(dbgs() << ", spill before last split point.\n");
1823 selectIntv(Idx: IntvIn);
1824 SlotIndex Idx = leaveIntvBefore(Idx: LSP);
1825 overlapIntv(Start: Idx, End: BI.LastInstr);
1826 useIntv(Start, End: Idx);
1827 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1828 }
1829 return;
1830 }
1831
1832 // The interference is overlapping somewhere we wanted to use IntvIn. That
1833 // means we need to create a local interval that can be allocated a
1834 // different register.
1835 unsigned LocalIntv = openIntv();
1836 (void)LocalIntv;
1837 LLVM_DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1838
1839 if (!BI.LiveOut || BI.LastInstr < LSP) {
1840 //
1841 // <<<<<<< Interference overlapping uses.
1842 // |---o---o---| Live-out on stack.
1843 // =====----____ Leave IntvIn before interference, then spill.
1844 //
1845 SlotIndex To = leaveIntvAfter(Idx: BI.LastInstr);
1846 SlotIndex From = enterIntvBefore(Idx: LeaveBefore);
1847 useIntv(Start: From, End: To);
1848 selectIntv(Idx: IntvIn);
1849 useIntv(Start, End: From);
1850 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1851 return;
1852 }
1853
1854 // <<<<<<< Interference overlapping uses.
1855 // |---o---o--o| Live-out on stack, late last use.
1856 // =====------- Copy to stack before LSP, overlap LocalIntv.
1857 // \_____ Stack interval is live-out.
1858 //
1859 SlotIndex To = leaveIntvBefore(Idx: LSP);
1860 overlapIntv(Start: To, End: BI.LastInstr);
1861 SlotIndex From = enterIntvBefore(Idx: std::min(a: To, b: LeaveBefore));
1862 useIntv(Start: From, End: To);
1863 selectIntv(Idx: IntvIn);
1864 useIntv(Start, End: From);
1865 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1866}
1867
1868void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
1869 unsigned IntvOut, SlotIndex EnterAfter) {
1870 SlotIndex Start, Stop;
1871 std::tie(args&: Start, args&: Stop) = LIS.getSlotIndexes()->getMBBRange(MBB: BI.MBB);
1872
1873 LLVM_DEBUG(dbgs() << printMBBReference(*BI.MBB) << " [" << Start << ';'
1874 << Stop << "), uses " << BI.FirstInstr << '-'
1875 << BI.LastInstr << ", reg-out " << IntvOut
1876 << ", enter after " << EnterAfter
1877 << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1878
1879 SlotIndex LSP = SA.getLastSplitPoint(BB: BI.MBB);
1880
1881 assert(IntvOut && "Must have register out");
1882 assert(BI.LiveOut && "Must be live-out");
1883 assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1884
1885 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
1886 LLVM_DEBUG(dbgs() << " after interference.\n");
1887 //
1888 // >>>> Interference before def.
1889 // | o---o---| Defined in block.
1890 // ========= Use IntvOut everywhere.
1891 //
1892 selectIntv(Idx: IntvOut);
1893 useIntv(Start: BI.FirstInstr, End: Stop);
1894 return;
1895 }
1896
1897 if (!EnterAfter || EnterAfter < BI.FirstInstr.getBaseIndex()) {
1898 LLVM_DEBUG(dbgs() << ", reload after interference.\n");
1899 //
1900 // >>>> Interference before def.
1901 // |---o---o---| Live-through, stack-in.
1902 // ____========= Enter IntvOut before first use.
1903 //
1904 selectIntv(Idx: IntvOut);
1905 SlotIndex Idx = enterIntvBefore(Idx: std::min(a: LSP, b: BI.FirstInstr));
1906 useIntv(Start: Idx, End: Stop);
1907 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1908 return;
1909 }
1910
1911 // The interference is overlapping somewhere we wanted to use IntvOut. That
1912 // means we need to create a local interval that can be allocated a
1913 // different register.
1914 LLVM_DEBUG(dbgs() << ", interference overlaps uses.\n");
1915 //
1916 // >>>>>>> Interference overlapping uses.
1917 // |---o---o---| Live-through, stack-in.
1918 // ____---====== Create local interval for interference range.
1919 //
1920 selectIntv(Idx: IntvOut);
1921 SlotIndex Idx = enterIntvAfter(Idx: EnterAfter);
1922 useIntv(Start: Idx, End: Stop);
1923 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1924
1925 openIntv();
1926 SlotIndex From = enterIntvBefore(Idx: std::min(a: Idx, b: BI.FirstInstr));
1927 useIntv(Start: From, End: Idx);
1928}
1929
1930void SplitAnalysis::BlockInfo::print(raw_ostream &OS) const {
1931 OS << "{" << printMBBReference(MBB: *MBB) << ", "
1932 << "uses " << FirstInstr << " to " << LastInstr << ", "
1933 << "1st def " << FirstDef << ", "
1934 << (LiveIn ? "live in" : "dead in") << ", "
1935 << (LiveOut ? "live out" : "dead out") << "}";
1936}
1937
1938void SplitAnalysis::BlockInfo::dump() const {
1939 print(OS&: dbgs());
1940 dbgs() << "\n";
1941}
1942