1//===- TargetFrameLoweringImpl.cpp - Implement target frame interface ------==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the layout of a stack frame on the target machine.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/ADT/BitVector.h"
14#include "llvm/CodeGen/MachineFrameInfo.h"
15#include "llvm/CodeGen/MachineFunction.h"
16#include "llvm/CodeGen/MachineRegisterInfo.h"
17#include "llvm/CodeGen/TargetFrameLowering.h"
18#include "llvm/CodeGen/TargetInstrInfo.h"
19#include "llvm/CodeGen/TargetSubtargetInfo.h"
20#include "llvm/IR/Attributes.h"
21#include "llvm/IR/Function.h"
22#include "llvm/IR/InstrTypes.h"
23#include "llvm/MC/MCAsmInfo.h"
24#include "llvm/Support/Compiler.h"
25#include "llvm/Target/TargetMachine.h"
26#include "llvm/Target/TargetOptions.h"
27
28using namespace llvm;
29
30TargetFrameLowering::~TargetFrameLowering() = default;
31
32bool TargetFrameLowering::enableCalleeSaveSkip(const MachineFunction &MF) const {
33 assert(MF.getFunction().hasFnAttribute(Attribute::NoReturn) &&
34 MF.getFunction().hasFnAttribute(Attribute::NoUnwind) &&
35 !MF.getFunction().hasFnAttribute(Attribute::UWTable));
36 return false;
37}
38
39bool TargetFrameLowering::enableCFIFixup(const MachineFunction &MF) const {
40 return MF.needsFrameMoves() &&
41 !MF.getTarget().getMCAsmInfo().usesWindowsCFI();
42}
43
44/// Returns the displacement from the frame register to the stack
45/// frame of the specified index, along with the frame register used
46/// (in output arg FrameReg). This is the default implementation which
47/// is overridden for some targets.
48StackOffset
49TargetFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
50 Register &FrameReg) const {
51 const MachineFrameInfo &MFI = MF.getFrameInfo();
52 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
53
54 // By default, assume all frame indices are referenced via whatever
55 // getFrameRegister() says. The target can override this if it's doing
56 // something different.
57 FrameReg = RI->getFrameRegister(MF);
58
59 return StackOffset::getFixed(Fixed: MFI.getObjectOffset(ObjectIdx: FI) + MFI.getStackSize() -
60 getOffsetOfLocalArea() +
61 MFI.getOffsetAdjustment());
62}
63
64/// Returns the offset from the stack pointer to the slot of the specified
65/// index. This function serves to provide a comparable offset from a single
66/// reference point (the value of the stack-pointer at function entry) that can
67/// be used for analysis. This is the default implementation using
68/// MachineFrameInfo offsets.
69StackOffset
70TargetFrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
71 int FI) const {
72 // To display the true offset from SP, we need to subtract the offset to the
73 // local area from MFI's ObjectOffset.
74 return StackOffset::getFixed(Fixed: MF.getFrameInfo().getObjectOffset(ObjectIdx: FI) -
75 getOffsetOfLocalArea());
76}
77
78bool TargetFrameLowering::needsFrameIndexResolution(
79 const MachineFunction &MF) const {
80 return MF.getFrameInfo().hasStackObjects();
81}
82
83void TargetFrameLowering::getCalleeSaves(const MachineFunction &MF,
84 BitVector &CalleeSaves) const {
85 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
86 CalleeSaves.resize(N: TRI.getNumRegs());
87
88 const MachineFrameInfo &MFI = MF.getFrameInfo();
89 if (!MFI.isCalleeSavedInfoValid())
90 return;
91
92 for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
93 CalleeSaves.set(Info.getReg());
94}
95
96const MCPhysReg *
97TargetFrameLowering::getMustPreserveRegisters(const MachineFunction &MF) const {
98 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
99
100 // Get the callee saved register list...
101 const MCPhysReg *CSRegs = nullptr;
102
103 // When interprocedural register allocation is enabled, callee saved register
104 // list should be empty, since caller saved registers are preferred over
105 // callee saved registers. Unless it has some risked CSR to be optimized out.
106 if (MF.getTarget().Options.EnableIPRA &&
107 isSafeForNoCSROpt(F: MF.getFunction()) &&
108 isProfitableForNoCSROpt(F: MF.getFunction()))
109 CSRegs = TRI.getIPRACSRegs(MF: &MF);
110 else
111 CSRegs = MF.getRegInfo().getCalleeSavedRegs();
112
113 // Early exit if there are no callee saved registers.
114 if (!CSRegs || CSRegs[0] == 0)
115 return nullptr;
116
117 // In Naked functions we aren't going to save any registers.
118 if (MF.getFunction().hasFnAttribute(Kind: Attribute::Naked))
119 return nullptr;
120
121 // Noreturn+nounwind functions never restore CSR, so no saves are needed.
122 // Purely noreturn functions may still return through throws, so those must
123 // save CSR for caller exception handlers.
124 //
125 // If the function uses longjmp to break out of its current path of
126 // execution we do not need the CSR spills either: setjmp stores all CSRs
127 // it was called with into the jmp_buf, which longjmp then restores.
128 if (MF.getFunction().hasFnAttribute(Kind: Attribute::NoReturn) &&
129 MF.getFunction().hasFnAttribute(Kind: Attribute::NoUnwind) &&
130 !MF.getFunction().hasFnAttribute(Kind: Attribute::UWTable) &&
131 enableCalleeSaveSkip(MF))
132 return nullptr;
133
134 return CSRegs;
135}
136
137void TargetFrameLowering::determineUncondPrologCalleeSaves(
138 MachineFunction &MF, const MCPhysReg *CSRegs, BitVector &SavedRegs) const {
139 // Functions which call __builtin_unwind_init get all their registers saved.
140 if (!MF.callsUnwindInit())
141 return;
142 for (unsigned i = 0; CSRegs[i]; ++i) {
143 unsigned Reg = CSRegs[i];
144 SavedRegs.set(Reg);
145 }
146}
147
148void TargetFrameLowering::determineCalleeSaves(MachineFunction &MF,
149 BitVector &PrologCSRs,
150 RegScavenger *RS) const {
151 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
152
153 // Resize before the early returns. Some backends expect that
154 // SavedRegs.size() == TRI.getNumRegs() after this call even if there are no
155 // saved registers.
156 PrologCSRs.resize(N: TRI.getNumRegs());
157
158 // Get the callee saved register list...
159 const MCPhysReg *CSRegs = getMustPreserveRegisters(MF);
160 // Early exit if there are no callee saved registers.
161 if (!CSRegs || CSRegs[0] == 0)
162 return;
163
164 determineUncondPrologCalleeSaves(MF, CSRegs, SavedRegs&: PrologCSRs);
165
166 const MachineRegisterInfo &MRI = MF.getRegInfo();
167 for (unsigned i = 0; CSRegs[i]; ++i) {
168 unsigned Reg = CSRegs[i];
169 if (MRI.isPhysRegModified(PhysReg: Reg))
170 PrologCSRs.set(Reg);
171 }
172}
173
174bool TargetFrameLowering::allocateScavengingFrameIndexesNearIncomingSP(
175 const MachineFunction &MF) const {
176 if (!hasFP(MF))
177 return false;
178
179 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
180 return RegInfo->useFPForScavengingIndex(MF) &&
181 !RegInfo->hasStackRealignment(MF);
182}
183
184bool TargetFrameLowering::isSafeForNoCSROpt(const Function &F) {
185 if (!F.hasLocalLinkage() || F.hasAddressTaken() ||
186 !F.hasFnAttribute(Kind: Attribute::NoRecurse))
187 return false;
188 // Function should not be optimized as tail call.
189 for (const User *U : F.users())
190 if (auto *CB = dyn_cast<CallBase>(Val: U))
191 if (CB->isTailCall())
192 return false;
193 return true;
194}
195
196int TargetFrameLowering::getInitialCFAOffset(const MachineFunction &MF) const {
197 llvm_unreachable("getInitialCFAOffset() not implemented!");
198}
199
200Register
201TargetFrameLowering::getInitialCFARegister(const MachineFunction &MF) const {
202 llvm_unreachable("getInitialCFARegister() not implemented!");
203}
204
205TargetFrameLowering::DwarfFrameBase
206TargetFrameLowering::getDwarfFrameBase(const MachineFunction &MF) const {
207 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
208 return DwarfFrameBase{.Kind: DwarfFrameBase::Register, .Location: {.Reg: RI->getFrameRegister(MF).id()}};
209}
210
211void TargetFrameLowering::spillCalleeSavedRegister(
212 MachineBasicBlock &SaveBlock, MachineBasicBlock::iterator MI,
213 const CalleeSavedInfo &CS, const TargetInstrInfo *TII,
214 const TargetRegisterInfo *TRI) const {
215 // Insert the spill to the stack frame.
216 MCRegister Reg = CS.getReg();
217
218 if (CS.isSpilledToReg()) {
219 BuildMI(BB&: SaveBlock, I: MI, MIMD: DebugLoc(), MCID: TII->get(Opcode: TargetOpcode::COPY),
220 DestReg: CS.getDstReg())
221 .addReg(RegNo: Reg, Flags: getKillRegState(B: true));
222 } else {
223 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
224 TII->storeRegToStackSlot(MBB&: SaveBlock, MI, SrcReg: Reg, isKill: true, FrameIndex: CS.getFrameIdx(), RC,
225 VReg: Register());
226 }
227}
228
229void TargetFrameLowering::restoreCalleeSavedRegister(
230 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
231 const CalleeSavedInfo &CS, const TargetInstrInfo *TII,
232 const TargetRegisterInfo *TRI) const {
233 MCRegister Reg = CS.getReg();
234 if (CS.isSpilledToReg()) {
235 BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: Reg)
236 .addReg(RegNo: CS.getDstReg(), Flags: getKillRegState(B: true));
237 } else {
238 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
239 TII->loadRegFromStackSlot(MBB, MI, DestReg: Reg, FrameIndex: CS.getFrameIdx(), RC, VReg: Register());
240 assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!");
241 }
242}
243