1//===- TargetFrameLoweringImpl.cpp - Implement target frame interface ------==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the layout of a stack frame on the target machine.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/ADT/BitVector.h"
14#include "llvm/CodeGen/MachineFrameInfo.h"
15#include "llvm/CodeGen/MachineFunction.h"
16#include "llvm/CodeGen/MachineRegisterInfo.h"
17#include "llvm/CodeGen/TargetFrameLowering.h"
18#include "llvm/CodeGen/TargetInstrInfo.h"
19#include "llvm/CodeGen/TargetSubtargetInfo.h"
20#include "llvm/IR/Attributes.h"
21#include "llvm/IR/Function.h"
22#include "llvm/IR/InstrTypes.h"
23#include "llvm/MC/MCAsmInfo.h"
24#include "llvm/Support/Compiler.h"
25#include "llvm/Target/TargetMachine.h"
26#include "llvm/Target/TargetOptions.h"
27
28using namespace llvm;
29
30TargetFrameLowering::~TargetFrameLowering() = default;
31
32bool TargetFrameLowering::enableCalleeSaveSkip(const MachineFunction &MF) const {
33 assert(MF.getFunction().hasFnAttribute(Attribute::NoReturn) &&
34 MF.getFunction().hasFnAttribute(Attribute::NoUnwind) &&
35 !MF.getFunction().hasFnAttribute(Attribute::UWTable));
36 return false;
37}
38
39bool TargetFrameLowering::enableCFIFixup(const MachineFunction &MF) const {
40 return !MF.usesWindowsUnwindInfo() && MF.needsFrameMoves();
41}
42
43/// Returns the displacement from the frame register to the stack
44/// frame of the specified index, along with the frame register used
45/// (in output arg FrameReg). This is the default implementation which
46/// is overridden for some targets.
47StackOffset
48TargetFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
49 Register &FrameReg) const {
50 const MachineFrameInfo &MFI = MF.getFrameInfo();
51 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
52
53 // By default, assume all frame indices are referenced via whatever
54 // getFrameRegister() says. The target can override this if it's doing
55 // something different.
56 FrameReg = RI->getFrameRegister(MF);
57
58 return StackOffset::getFixed(Fixed: MFI.getObjectOffset(ObjectIdx: FI) + MFI.getStackSize() -
59 getOffsetOfLocalArea() +
60 MFI.getOffsetAdjustment());
61}
62
63/// Returns the offset from the stack pointer to the slot of the specified
64/// index. This function serves to provide a comparable offset from a single
65/// reference point (the value of the stack-pointer at function entry) that can
66/// be used for analysis. This is the default implementation using
67/// MachineFrameInfo offsets.
68StackOffset
69TargetFrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
70 int FI) const {
71 // To display the true offset from SP, we need to subtract the offset to the
72 // local area from MFI's ObjectOffset.
73 return StackOffset::getFixed(Fixed: MF.getFrameInfo().getObjectOffset(ObjectIdx: FI) -
74 getOffsetOfLocalArea());
75}
76
77bool TargetFrameLowering::needsFrameIndexResolution(
78 const MachineFunction &MF) const {
79 return MF.getFrameInfo().hasStackObjects();
80}
81
82void TargetFrameLowering::getCalleeSaves(const MachineFunction &MF,
83 BitVector &CalleeSaves) const {
84 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
85 CalleeSaves.resize(N: TRI.getNumRegs());
86
87 const MachineFrameInfo &MFI = MF.getFrameInfo();
88 if (!MFI.isCalleeSavedInfoValid())
89 return;
90
91 for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
92 CalleeSaves.set(Info.getReg());
93}
94
95const MCPhysReg *
96TargetFrameLowering::getMustPreserveRegisters(const MachineFunction &MF) const {
97 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
98
99 // Get the callee saved register list...
100 const MCPhysReg *CSRegs = nullptr;
101
102 // When interprocedural register allocation is enabled, callee saved register
103 // list should be empty, since caller saved registers are preferred over
104 // callee saved registers. Unless it has some risked CSR to be optimized out.
105 if (MF.getTarget().Options.EnableIPRA &&
106 isSafeForNoCSROpt(F: MF.getFunction()) &&
107 isProfitableForNoCSROpt(F: MF.getFunction()))
108 CSRegs = TRI.getIPRACSRegs(MF: &MF);
109 else
110 CSRegs = MF.getRegInfo().getCalleeSavedRegs();
111
112 // Early exit if there are no callee saved registers.
113 if (!CSRegs || CSRegs[0] == 0)
114 return nullptr;
115
116 // In Naked functions we aren't going to save any registers.
117 if (MF.getFunction().hasFnAttribute(Kind: Attribute::Naked))
118 return nullptr;
119
120 // Noreturn+nounwind functions never restore CSR, so no saves are needed.
121 // Purely noreturn functions may still return through throws, so those must
122 // save CSR for caller exception handlers.
123 //
124 // If the function uses longjmp to break out of its current path of
125 // execution we do not need the CSR spills either: setjmp stores all CSRs
126 // it was called with into the jmp_buf, which longjmp then restores.
127 if (MF.getFunction().hasFnAttribute(Kind: Attribute::NoReturn) &&
128 MF.getFunction().hasFnAttribute(Kind: Attribute::NoUnwind) &&
129 !MF.getFunction().hasFnAttribute(Kind: Attribute::UWTable) &&
130 enableCalleeSaveSkip(MF))
131 return nullptr;
132
133 return CSRegs;
134}
135
136void TargetFrameLowering::determineUncondPrologCalleeSaves(
137 MachineFunction &MF, const MCPhysReg *CSRegs, BitVector &SavedRegs) const {
138 // Functions which call __builtin_unwind_init get all their registers saved.
139 if (!MF.callsUnwindInit())
140 return;
141 for (unsigned i = 0; CSRegs[i]; ++i) {
142 unsigned Reg = CSRegs[i];
143 SavedRegs.set(Reg);
144 }
145}
146
147void TargetFrameLowering::determineCalleeSaves(MachineFunction &MF,
148 BitVector &PrologCSRs,
149 RegScavenger *RS) const {
150 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
151
152 // Resize before the early returns. Some backends expect that
153 // SavedRegs.size() == TRI.getNumRegs() after this call even if there are no
154 // saved registers.
155 PrologCSRs.resize(N: TRI.getNumRegs());
156
157 // Get the callee saved register list...
158 const MCPhysReg *CSRegs = getMustPreserveRegisters(MF);
159 // Early exit if there are no callee saved registers.
160 if (!CSRegs || CSRegs[0] == 0)
161 return;
162
163 determineUncondPrologCalleeSaves(MF, CSRegs, SavedRegs&: PrologCSRs);
164
165 const MachineRegisterInfo &MRI = MF.getRegInfo();
166 for (unsigned i = 0; CSRegs[i]; ++i) {
167 unsigned Reg = CSRegs[i];
168 if (MRI.isPhysRegModified(PhysReg: Reg))
169 PrologCSRs.set(Reg);
170 }
171}
172
173bool TargetFrameLowering::allocateScavengingFrameIndexesNearIncomingSP(
174 const MachineFunction &MF) const {
175 if (!hasFP(MF))
176 return false;
177
178 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
179 return RegInfo->useFPForScavengingIndex(MF) &&
180 !RegInfo->hasStackRealignment(MF);
181}
182
183bool TargetFrameLowering::isSafeForNoCSROpt(const Function &F) {
184 if (!F.hasLocalLinkage() || F.hasAddressTaken() ||
185 !F.hasFnAttribute(Kind: Attribute::NoRecurse))
186 return false;
187 // Function should not be optimized as tail call.
188 for (const User *U : F.users())
189 if (auto *CB = dyn_cast<CallBase>(Val: U))
190 if (CB->isTailCall())
191 return false;
192 return true;
193}
194
195int TargetFrameLowering::getInitialCFAOffset(const MachineFunction &MF) const {
196 llvm_unreachable("getInitialCFAOffset() not implemented!");
197}
198
199Register
200TargetFrameLowering::getInitialCFARegister(const MachineFunction &MF) const {
201 llvm_unreachable("getInitialCFARegister() not implemented!");
202}
203
204TargetFrameLowering::DwarfFrameBase
205TargetFrameLowering::getDwarfFrameBase(const MachineFunction &MF) const {
206 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
207 return DwarfFrameBase{.Kind: DwarfFrameBase::Register, .Location: {.Reg: RI->getFrameRegister(MF).id()}};
208}
209
210void TargetFrameLowering::spillCalleeSavedRegister(
211 MachineBasicBlock &SaveBlock, MachineBasicBlock::iterator MI,
212 const CalleeSavedInfo &CS, const TargetInstrInfo *TII,
213 const TargetRegisterInfo *TRI) const {
214 // Insert the spill to the stack frame.
215 MCRegister Reg = CS.getReg();
216
217 if (CS.isSpilledToReg()) {
218 BuildMI(BB&: SaveBlock, I: MI, MIMD: DebugLoc(), MCID: TII->get(Opcode: TargetOpcode::COPY),
219 DestReg: CS.getDstReg())
220 .addReg(RegNo: Reg, Flags: getKillRegState(B: true));
221 } else {
222 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
223 TII->storeRegToStackSlot(MBB&: SaveBlock, MI, SrcReg: Reg, isKill: true, FrameIndex: CS.getFrameIdx(), RC,
224 VReg: Register());
225 }
226}
227
228void TargetFrameLowering::restoreCalleeSavedRegister(
229 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
230 const CalleeSavedInfo &CS, const TargetInstrInfo *TII,
231 const TargetRegisterInfo *TRI) const {
232 MCRegister Reg = CS.getReg();
233 if (CS.isSpilledToReg()) {
234 BuildMI(BB&: MBB, I: MI, MIMD: DebugLoc(), MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: Reg)
235 .addReg(RegNo: CS.getDstReg(), Flags: getKillRegState(B: true));
236 } else {
237 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
238 TII->loadRegFromStackSlot(MBB, MI, DestReg: Reg, FrameIndex: CS.getFrameIdx(), RC, VReg: Register());
239 assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!");
240 }
241}
242