1//===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the TargetLoweringBase class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/ADT/BitVector.h"
14#include "llvm/ADT/DenseMap.h"
15#include "llvm/ADT/STLExtras.h"
16#include "llvm/ADT/SmallVector.h"
17#include "llvm/ADT/StringExtras.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/ADT/Twine.h"
20#include "llvm/Analysis/Loads.h"
21#include "llvm/Analysis/TargetTransformInfo.h"
22#include "llvm/CodeGen/Analysis.h"
23#include "llvm/CodeGen/ISDOpcodes.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstr.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineMemOperand.h"
30#include "llvm/CodeGen/MachineOperand.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/RuntimeLibcallUtil.h"
33#include "llvm/CodeGen/StackMaps.h"
34#include "llvm/CodeGen/TargetLowering.h"
35#include "llvm/CodeGen/TargetOpcodes.h"
36#include "llvm/CodeGen/TargetRegisterInfo.h"
37#include "llvm/CodeGen/ValueTypes.h"
38#include "llvm/CodeGenTypes/MachineValueType.h"
39#include "llvm/IR/Attributes.h"
40#include "llvm/IR/CallingConv.h"
41#include "llvm/IR/DataLayout.h"
42#include "llvm/IR/DerivedTypes.h"
43#include "llvm/IR/Function.h"
44#include "llvm/IR/GlobalValue.h"
45#include "llvm/IR/GlobalVariable.h"
46#include "llvm/IR/IRBuilder.h"
47#include "llvm/IR/Module.h"
48#include "llvm/IR/Type.h"
49#include "llvm/Support/Casting.h"
50#include "llvm/Support/CommandLine.h"
51#include "llvm/Support/Compiler.h"
52#include "llvm/Support/ErrorHandling.h"
53#include "llvm/Support/MathExtras.h"
54#include "llvm/Target/TargetMachine.h"
55#include "llvm/Target/TargetOptions.h"
56#include "llvm/TargetParser/Triple.h"
57#include "llvm/Transforms/Utils/SizeOpts.h"
58#include <algorithm>
59#include <cassert>
60#include <cstdint>
61#include <cstring>
62#include <string>
63#include <tuple>
64#include <utility>
65
66using namespace llvm;
67
68static cl::opt<bool> JumpIsExpensiveOverride(
69 "jump-is-expensive", cl::init(Val: false),
70 cl::desc("Do not create extra branches to split comparison logic."),
71 cl::Hidden);
72
73static cl::opt<unsigned> MinimumJumpTableEntries
74 ("min-jump-table-entries", cl::init(Val: 4), cl::Hidden,
75 cl::desc("Set minimum number of entries to use a jump table."));
76
77static cl::opt<unsigned> MaximumJumpTableSize
78 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
79 cl::desc("Set maximum size of jump tables."));
80
81/// Minimum jump table density for normal functions.
82static cl::opt<unsigned>
83 JumpTableDensity("jump-table-density", cl::init(Val: 10), cl::Hidden,
84 cl::desc("Minimum density for building a jump table in "
85 "a normal function"));
86
87/// Minimum jump table density for -Os or -Oz functions.
88static cl::opt<unsigned> OptsizeJumpTableDensity(
89 "optsize-jump-table-density", cl::init(Val: 40), cl::Hidden,
90 cl::desc("Minimum density for building a jump table in "
91 "an optsize function"));
92
93static cl::opt<unsigned> MinimumBitTestCmpsOverride(
94 "min-bit-test-cmps", cl::init(Val: 2), cl::Hidden,
95 cl::desc("Set minimum of largest number of comparisons "
96 "to use bit test for switch."));
97
98static cl::opt<unsigned> MaxStoresPerMemsetOverride(
99 "max-store-memset", cl::init(Val: 0), cl::Hidden,
100 cl::desc("Override target's MaxStoresPerMemset and "
101 "MaxStoresPerMemsetOptSize. "
102 "Set to 0 to use the target default."));
103
104static cl::opt<unsigned> MaxStoresPerMemcpyOverride(
105 "max-store-memcpy", cl::init(Val: 0), cl::Hidden,
106 cl::desc("Override target's MaxStoresPerMemcpy and "
107 "MaxStoresPerMemcpyOptSize. "
108 "Set to 0 to use the target default."));
109
110static cl::opt<unsigned> MaxStoresPerMemmoveOverride(
111 "max-store-memmove", cl::init(Val: 0), cl::Hidden,
112 cl::desc("Override target's MaxStoresPerMemmove and "
113 "MaxStoresPerMemmoveOptSize. "
114 "Set to 0 to use the target default."));
115
116// FIXME: This option is only to test if the strict fp operation processed
117// correctly by preventing mutating strict fp operation to normal fp operation
118// during development. When the backend supports strict float operation, this
119// option will be meaningless.
120static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
121 cl::desc("Don't mutate strict-float node to a legalize node"),
122 cl::init(Val: false), cl::Hidden);
123
124LLVM_ABI RTLIB::Libcall RTLIB::getSHL(EVT VT) {
125 if (VT == MVT::i16)
126 return RTLIB::SHL_I16;
127 if (VT == MVT::i32)
128 return RTLIB::SHL_I32;
129 if (VT == MVT::i64)
130 return RTLIB::SHL_I64;
131 if (VT == MVT::i128)
132 return RTLIB::SHL_I128;
133
134 return RTLIB::UNKNOWN_LIBCALL;
135}
136
137LLVM_ABI RTLIB::Libcall RTLIB::getSRL(EVT VT) {
138 if (VT == MVT::i16)
139 return RTLIB::SRL_I16;
140 if (VT == MVT::i32)
141 return RTLIB::SRL_I32;
142 if (VT == MVT::i64)
143 return RTLIB::SRL_I64;
144 if (VT == MVT::i128)
145 return RTLIB::SRL_I128;
146
147 return RTLIB::UNKNOWN_LIBCALL;
148}
149
150LLVM_ABI RTLIB::Libcall RTLIB::getSRA(EVT VT) {
151 if (VT == MVT::i16)
152 return RTLIB::SRA_I16;
153 if (VT == MVT::i32)
154 return RTLIB::SRA_I32;
155 if (VT == MVT::i64)
156 return RTLIB::SRA_I64;
157 if (VT == MVT::i128)
158 return RTLIB::SRA_I128;
159
160 return RTLIB::UNKNOWN_LIBCALL;
161}
162
163LLVM_ABI RTLIB::Libcall RTLIB::getMUL(EVT VT) {
164 if (VT == MVT::i16)
165 return RTLIB::MUL_I16;
166 if (VT == MVT::i32)
167 return RTLIB::MUL_I32;
168 if (VT == MVT::i64)
169 return RTLIB::MUL_I64;
170 if (VT == MVT::i128)
171 return RTLIB::MUL_I128;
172 return RTLIB::UNKNOWN_LIBCALL;
173}
174
175LLVM_ABI RTLIB::Libcall RTLIB::getMULO(EVT VT) {
176 if (VT == MVT::i32)
177 return RTLIB::MULO_I32;
178 if (VT == MVT::i64)
179 return RTLIB::MULO_I64;
180 if (VT == MVT::i128)
181 return RTLIB::MULO_I128;
182 return RTLIB::UNKNOWN_LIBCALL;
183}
184
185LLVM_ABI RTLIB::Libcall RTLIB::getSDIV(EVT VT) {
186 if (VT == MVT::i16)
187 return RTLIB::SDIV_I16;
188 if (VT == MVT::i32)
189 return RTLIB::SDIV_I32;
190 if (VT == MVT::i64)
191 return RTLIB::SDIV_I64;
192 if (VT == MVT::i128)
193 return RTLIB::SDIV_I128;
194 return RTLIB::UNKNOWN_LIBCALL;
195}
196
197LLVM_ABI RTLIB::Libcall RTLIB::getUDIV(EVT VT) {
198 if (VT == MVT::i16)
199 return RTLIB::UDIV_I16;
200 if (VT == MVT::i32)
201 return RTLIB::UDIV_I32;
202 if (VT == MVT::i64)
203 return RTLIB::UDIV_I64;
204 if (VT == MVT::i128)
205 return RTLIB::UDIV_I128;
206 return RTLIB::UNKNOWN_LIBCALL;
207}
208
209LLVM_ABI RTLIB::Libcall RTLIB::getSREM(EVT VT) {
210 if (VT == MVT::i16)
211 return RTLIB::SREM_I16;
212 if (VT == MVT::i32)
213 return RTLIB::SREM_I32;
214 if (VT == MVT::i64)
215 return RTLIB::SREM_I64;
216 if (VT == MVT::i128)
217 return RTLIB::SREM_I128;
218 return RTLIB::UNKNOWN_LIBCALL;
219}
220
221LLVM_ABI RTLIB::Libcall RTLIB::getUREM(EVT VT) {
222 if (VT == MVT::i16)
223 return RTLIB::UREM_I16;
224 if (VT == MVT::i32)
225 return RTLIB::UREM_I32;
226 if (VT == MVT::i64)
227 return RTLIB::UREM_I64;
228 if (VT == MVT::i128)
229 return RTLIB::UREM_I128;
230 return RTLIB::UNKNOWN_LIBCALL;
231}
232
233LLVM_ABI RTLIB::Libcall RTLIB::getCTPOP(EVT VT) {
234 if (VT == MVT::i32)
235 return RTLIB::CTPOP_I32;
236 if (VT == MVT::i64)
237 return RTLIB::CTPOP_I64;
238 if (VT == MVT::i128)
239 return RTLIB::CTPOP_I128;
240 return RTLIB::UNKNOWN_LIBCALL;
241}
242
243/// GetFPLibCall - Helper to return the right libcall for the given floating
244/// point type, or UNKNOWN_LIBCALL if there is none.
245RTLIB::Libcall RTLIB::getFPLibCall(EVT VT,
246 RTLIB::Libcall Call_F32,
247 RTLIB::Libcall Call_F64,
248 RTLIB::Libcall Call_F80,
249 RTLIB::Libcall Call_F128,
250 RTLIB::Libcall Call_PPCF128) {
251 return
252 VT == MVT::f32 ? Call_F32 :
253 VT == MVT::f64 ? Call_F64 :
254 VT == MVT::f80 ? Call_F80 :
255 VT == MVT::f128 ? Call_F128 :
256 VT == MVT::ppcf128 ? Call_PPCF128 :
257 RTLIB::UNKNOWN_LIBCALL;
258}
259
260/// getFPEXT - Return the FPEXT_*_* value for the given types, or
261/// UNKNOWN_LIBCALL if there is none.
262RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
263 if (OpVT == MVT::f16) {
264 if (RetVT == MVT::f32)
265 return FPEXT_F16_F32;
266 if (RetVT == MVT::f64)
267 return FPEXT_F16_F64;
268 if (RetVT == MVT::f80)
269 return FPEXT_F16_F80;
270 if (RetVT == MVT::f128)
271 return FPEXT_F16_F128;
272 } else if (OpVT == MVT::f32) {
273 if (RetVT == MVT::f64)
274 return FPEXT_F32_F64;
275 if (RetVT == MVT::f128)
276 return FPEXT_F32_F128;
277 if (RetVT == MVT::ppcf128)
278 return FPEXT_F32_PPCF128;
279 } else if (OpVT == MVT::f64) {
280 if (RetVT == MVT::f128)
281 return FPEXT_F64_F128;
282 else if (RetVT == MVT::ppcf128)
283 return FPEXT_F64_PPCF128;
284 } else if (OpVT == MVT::f80) {
285 if (RetVT == MVT::f128)
286 return FPEXT_F80_F128;
287 } else if (OpVT == MVT::bf16) {
288 if (RetVT == MVT::f32)
289 return FPEXT_BF16_F32;
290 }
291
292 return UNKNOWN_LIBCALL;
293}
294
295/// getFPROUND - Return the FPROUND_*_* value for the given types, or
296/// UNKNOWN_LIBCALL if there is none.
297RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
298 if (RetVT == MVT::f16) {
299 if (OpVT == MVT::f32)
300 return FPROUND_F32_F16;
301 if (OpVT == MVT::f64)
302 return FPROUND_F64_F16;
303 if (OpVT == MVT::f80)
304 return FPROUND_F80_F16;
305 if (OpVT == MVT::f128)
306 return FPROUND_F128_F16;
307 if (OpVT == MVT::ppcf128)
308 return FPROUND_PPCF128_F16;
309 } else if (RetVT == MVT::bf16) {
310 if (OpVT == MVT::f32)
311 return FPROUND_F32_BF16;
312 if (OpVT == MVT::f64)
313 return FPROUND_F64_BF16;
314 if (OpVT == MVT::f80)
315 return FPROUND_F80_BF16;
316 if (OpVT == MVT::f128)
317 return FPROUND_F128_BF16;
318 } else if (RetVT == MVT::f32) {
319 if (OpVT == MVT::f64)
320 return FPROUND_F64_F32;
321 if (OpVT == MVT::f80)
322 return FPROUND_F80_F32;
323 if (OpVT == MVT::f128)
324 return FPROUND_F128_F32;
325 if (OpVT == MVT::ppcf128)
326 return FPROUND_PPCF128_F32;
327 } else if (RetVT == MVT::f64) {
328 if (OpVT == MVT::f80)
329 return FPROUND_F80_F64;
330 if (OpVT == MVT::f128)
331 return FPROUND_F128_F64;
332 if (OpVT == MVT::ppcf128)
333 return FPROUND_PPCF128_F64;
334 } else if (RetVT == MVT::f80) {
335 if (OpVT == MVT::f128)
336 return FPROUND_F128_F80;
337 }
338
339 return UNKNOWN_LIBCALL;
340}
341
342/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
343/// UNKNOWN_LIBCALL if there is none.
344RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
345 if (OpVT == MVT::f16) {
346 if (RetVT == MVT::i32)
347 return FPTOSINT_F16_I32;
348 if (RetVT == MVT::i64)
349 return FPTOSINT_F16_I64;
350 if (RetVT == MVT::i128)
351 return FPTOSINT_F16_I128;
352 } else if (OpVT == MVT::f32) {
353 if (RetVT == MVT::i32)
354 return FPTOSINT_F32_I32;
355 if (RetVT == MVT::i64)
356 return FPTOSINT_F32_I64;
357 if (RetVT == MVT::i128)
358 return FPTOSINT_F32_I128;
359 } else if (OpVT == MVT::f64) {
360 if (RetVT == MVT::i32)
361 return FPTOSINT_F64_I32;
362 if (RetVT == MVT::i64)
363 return FPTOSINT_F64_I64;
364 if (RetVT == MVT::i128)
365 return FPTOSINT_F64_I128;
366 } else if (OpVT == MVT::f80) {
367 if (RetVT == MVT::i32)
368 return FPTOSINT_F80_I32;
369 if (RetVT == MVT::i64)
370 return FPTOSINT_F80_I64;
371 if (RetVT == MVT::i128)
372 return FPTOSINT_F80_I128;
373 } else if (OpVT == MVT::f128) {
374 if (RetVT == MVT::i32)
375 return FPTOSINT_F128_I32;
376 if (RetVT == MVT::i64)
377 return FPTOSINT_F128_I64;
378 if (RetVT == MVT::i128)
379 return FPTOSINT_F128_I128;
380 } else if (OpVT == MVT::ppcf128) {
381 if (RetVT == MVT::i32)
382 return FPTOSINT_PPCF128_I32;
383 if (RetVT == MVT::i64)
384 return FPTOSINT_PPCF128_I64;
385 if (RetVT == MVT::i128)
386 return FPTOSINT_PPCF128_I128;
387 }
388 return UNKNOWN_LIBCALL;
389}
390
391/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
392/// UNKNOWN_LIBCALL if there is none.
393RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
394 if (OpVT == MVT::f16) {
395 if (RetVT == MVT::i32)
396 return FPTOUINT_F16_I32;
397 if (RetVT == MVT::i64)
398 return FPTOUINT_F16_I64;
399 if (RetVT == MVT::i128)
400 return FPTOUINT_F16_I128;
401 } else if (OpVT == MVT::f32) {
402 if (RetVT == MVT::i32)
403 return FPTOUINT_F32_I32;
404 if (RetVT == MVT::i64)
405 return FPTOUINT_F32_I64;
406 if (RetVT == MVT::i128)
407 return FPTOUINT_F32_I128;
408 } else if (OpVT == MVT::f64) {
409 if (RetVT == MVT::i32)
410 return FPTOUINT_F64_I32;
411 if (RetVT == MVT::i64)
412 return FPTOUINT_F64_I64;
413 if (RetVT == MVT::i128)
414 return FPTOUINT_F64_I128;
415 } else if (OpVT == MVT::f80) {
416 if (RetVT == MVT::i32)
417 return FPTOUINT_F80_I32;
418 if (RetVT == MVT::i64)
419 return FPTOUINT_F80_I64;
420 if (RetVT == MVT::i128)
421 return FPTOUINT_F80_I128;
422 } else if (OpVT == MVT::f128) {
423 if (RetVT == MVT::i32)
424 return FPTOUINT_F128_I32;
425 if (RetVT == MVT::i64)
426 return FPTOUINT_F128_I64;
427 if (RetVT == MVT::i128)
428 return FPTOUINT_F128_I128;
429 } else if (OpVT == MVT::ppcf128) {
430 if (RetVT == MVT::i32)
431 return FPTOUINT_PPCF128_I32;
432 if (RetVT == MVT::i64)
433 return FPTOUINT_PPCF128_I64;
434 if (RetVT == MVT::i128)
435 return FPTOUINT_PPCF128_I128;
436 }
437 return UNKNOWN_LIBCALL;
438}
439
440/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
441/// UNKNOWN_LIBCALL if there is none.
442RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
443 if (OpVT == MVT::i32) {
444 if (RetVT == MVT::f16)
445 return SINTTOFP_I32_F16;
446 if (RetVT == MVT::f32)
447 return SINTTOFP_I32_F32;
448 if (RetVT == MVT::f64)
449 return SINTTOFP_I32_F64;
450 if (RetVT == MVT::f80)
451 return SINTTOFP_I32_F80;
452 if (RetVT == MVT::f128)
453 return SINTTOFP_I32_F128;
454 if (RetVT == MVT::ppcf128)
455 return SINTTOFP_I32_PPCF128;
456 } else if (OpVT == MVT::i64) {
457 if (RetVT == MVT::bf16)
458 return SINTTOFP_I64_BF16;
459 if (RetVT == MVT::f16)
460 return SINTTOFP_I64_F16;
461 if (RetVT == MVT::f32)
462 return SINTTOFP_I64_F32;
463 if (RetVT == MVT::f64)
464 return SINTTOFP_I64_F64;
465 if (RetVT == MVT::f80)
466 return SINTTOFP_I64_F80;
467 if (RetVT == MVT::f128)
468 return SINTTOFP_I64_F128;
469 if (RetVT == MVT::ppcf128)
470 return SINTTOFP_I64_PPCF128;
471 } else if (OpVT == MVT::i128) {
472 if (RetVT == MVT::f16)
473 return SINTTOFP_I128_F16;
474 if (RetVT == MVT::f32)
475 return SINTTOFP_I128_F32;
476 if (RetVT == MVT::f64)
477 return SINTTOFP_I128_F64;
478 if (RetVT == MVT::f80)
479 return SINTTOFP_I128_F80;
480 if (RetVT == MVT::f128)
481 return SINTTOFP_I128_F128;
482 if (RetVT == MVT::ppcf128)
483 return SINTTOFP_I128_PPCF128;
484 }
485 return UNKNOWN_LIBCALL;
486}
487
488/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
489/// UNKNOWN_LIBCALL if there is none.
490RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
491 if (OpVT == MVT::i32) {
492 if (RetVT == MVT::f16)
493 return UINTTOFP_I32_F16;
494 if (RetVT == MVT::f32)
495 return UINTTOFP_I32_F32;
496 if (RetVT == MVT::f64)
497 return UINTTOFP_I32_F64;
498 if (RetVT == MVT::f80)
499 return UINTTOFP_I32_F80;
500 if (RetVT == MVT::f128)
501 return UINTTOFP_I32_F128;
502 if (RetVT == MVT::ppcf128)
503 return UINTTOFP_I32_PPCF128;
504 } else if (OpVT == MVT::i64) {
505 if (RetVT == MVT::bf16)
506 return UINTTOFP_I64_BF16;
507 if (RetVT == MVT::f16)
508 return UINTTOFP_I64_F16;
509 if (RetVT == MVT::f32)
510 return UINTTOFP_I64_F32;
511 if (RetVT == MVT::f64)
512 return UINTTOFP_I64_F64;
513 if (RetVT == MVT::f80)
514 return UINTTOFP_I64_F80;
515 if (RetVT == MVT::f128)
516 return UINTTOFP_I64_F128;
517 if (RetVT == MVT::ppcf128)
518 return UINTTOFP_I64_PPCF128;
519 } else if (OpVT == MVT::i128) {
520 if (RetVT == MVT::f16)
521 return UINTTOFP_I128_F16;
522 if (RetVT == MVT::f32)
523 return UINTTOFP_I128_F32;
524 if (RetVT == MVT::f64)
525 return UINTTOFP_I128_F64;
526 if (RetVT == MVT::f80)
527 return UINTTOFP_I128_F80;
528 if (RetVT == MVT::f128)
529 return UINTTOFP_I128_F128;
530 if (RetVT == MVT::ppcf128)
531 return UINTTOFP_I128_PPCF128;
532 }
533 return UNKNOWN_LIBCALL;
534}
535
536RTLIB::Libcall RTLIB::getPOWI(EVT RetVT) {
537 return getFPLibCall(VT: RetVT, Call_F32: POWI_F32, Call_F64: POWI_F64, Call_F80: POWI_F80, Call_F128: POWI_F128,
538 Call_PPCF128: POWI_PPCF128);
539}
540
541RTLIB::Libcall RTLIB::getPOW(EVT RetVT) {
542 // TODO: Tablegen should generate this function
543 if (RetVT.isVector()) {
544 if (!RetVT.isSimple())
545 return RTLIB::UNKNOWN_LIBCALL;
546 switch (RetVT.getSimpleVT().SimpleTy) {
547 case MVT::v4f32:
548 return RTLIB::POW_V4F32;
549 case MVT::v2f64:
550 return RTLIB::POW_V2F64;
551 case MVT::nxv4f32:
552 return RTLIB::POW_NXV4F32;
553 case MVT::nxv2f64:
554 return RTLIB::POW_NXV2F64;
555 default:
556 return RTLIB::UNKNOWN_LIBCALL;
557 }
558 }
559
560 return getFPLibCall(VT: RetVT, Call_F32: POW_F32, Call_F64: POW_F64, Call_F80: POW_F80, Call_F128: POW_F128, Call_PPCF128: POW_PPCF128);
561}
562
563RTLIB::Libcall RTLIB::getLDEXP(EVT RetVT) {
564 return getFPLibCall(VT: RetVT, Call_F32: LDEXP_F32, Call_F64: LDEXP_F64, Call_F80: LDEXP_F80, Call_F128: LDEXP_F128,
565 Call_PPCF128: LDEXP_PPCF128);
566}
567
568RTLIB::Libcall RTLIB::getFREXP(EVT RetVT) {
569 return getFPLibCall(VT: RetVT, Call_F32: FREXP_F32, Call_F64: FREXP_F64, Call_F80: FREXP_F80, Call_F128: FREXP_F128,
570 Call_PPCF128: FREXP_PPCF128);
571}
572
573RTLIB::Libcall RTLIB::getSIN(EVT RetVT) {
574 return getFPLibCall(VT: RetVT, Call_F32: SIN_F32, Call_F64: SIN_F64, Call_F80: SIN_F80, Call_F128: SIN_F128, Call_PPCF128: SIN_PPCF128);
575}
576
577RTLIB::Libcall RTLIB::getCOS(EVT RetVT) {
578 return getFPLibCall(VT: RetVT, Call_F32: COS_F32, Call_F64: COS_F64, Call_F80: COS_F80, Call_F128: COS_F128, Call_PPCF128: COS_PPCF128);
579}
580
581RTLIB::Libcall RTLIB::getSINCOS(EVT RetVT) {
582 // TODO: Tablegen should generate this function
583 if (RetVT.isVector()) {
584 if (!RetVT.isSimple())
585 return RTLIB::UNKNOWN_LIBCALL;
586 switch (RetVT.getSimpleVT().SimpleTy) {
587 case MVT::v4f32:
588 return RTLIB::SINCOS_V4F32;
589 case MVT::v8f32:
590 return RTLIB::SINCOS_V8F32;
591 case MVT::v16f32:
592 return RTLIB::SINCOS_V16F32;
593 case MVT::v2f64:
594 return RTLIB::SINCOS_V2F64;
595 case MVT::v4f64:
596 return RTLIB::SINCOS_V4F64;
597 case MVT::v8f64:
598 return RTLIB::SINCOS_V8F64;
599 case MVT::nxv4f32:
600 return RTLIB::SINCOS_NXV4F32;
601 case MVT::nxv2f64:
602 return RTLIB::SINCOS_NXV2F64;
603 default:
604 return RTLIB::UNKNOWN_LIBCALL;
605 }
606 }
607
608 return getFPLibCall(VT: RetVT, Call_F32: SINCOS_F32, Call_F64: SINCOS_F64, Call_F80: SINCOS_F80, Call_F128: SINCOS_F128,
609 Call_PPCF128: SINCOS_PPCF128);
610}
611
612RTLIB::Libcall RTLIB::getSINCOSPI(EVT RetVT) {
613 // TODO: Tablegen should generate this function
614 if (RetVT.isVector()) {
615 if (!RetVT.isSimple())
616 return RTLIB::UNKNOWN_LIBCALL;
617 switch (RetVT.getSimpleVT().SimpleTy) {
618 case MVT::v4f32:
619 return RTLIB::SINCOSPI_V4F32;
620 case MVT::v2f64:
621 return RTLIB::SINCOSPI_V2F64;
622 case MVT::nxv4f32:
623 return RTLIB::SINCOSPI_NXV4F32;
624 case MVT::nxv2f64:
625 return RTLIB::SINCOSPI_NXV2F64;
626 default:
627 return RTLIB::UNKNOWN_LIBCALL;
628 }
629 }
630
631 return getFPLibCall(VT: RetVT, Call_F32: SINCOSPI_F32, Call_F64: SINCOSPI_F64, Call_F80: SINCOSPI_F80,
632 Call_F128: SINCOSPI_F128, Call_PPCF128: SINCOSPI_PPCF128);
633}
634
635RTLIB::Libcall RTLIB::getSINCOS_STRET(EVT RetVT) {
636 return getFPLibCall(VT: RetVT, Call_F32: SINCOS_STRET_F32, Call_F64: SINCOS_STRET_F64,
637 Call_F80: UNKNOWN_LIBCALL, Call_F128: UNKNOWN_LIBCALL, Call_PPCF128: UNKNOWN_LIBCALL);
638}
639
640RTLIB::Libcall RTLIB::getREM(EVT VT) {
641 // TODO: Tablegen should generate this function
642 if (VT.isVector()) {
643 if (!VT.isSimple())
644 return RTLIB::UNKNOWN_LIBCALL;
645 switch (VT.getSimpleVT().SimpleTy) {
646 case MVT::v4f32:
647 return RTLIB::REM_V4F32;
648 case MVT::v2f64:
649 return RTLIB::REM_V2F64;
650 case MVT::nxv4f32:
651 return RTLIB::REM_NXV4F32;
652 case MVT::nxv2f64:
653 return RTLIB::REM_NXV2F64;
654 default:
655 return RTLIB::UNKNOWN_LIBCALL;
656 }
657 }
658
659 return getFPLibCall(VT, Call_F32: REM_F32, Call_F64: REM_F64, Call_F80: REM_F80, Call_F128: REM_F128, Call_PPCF128: REM_PPCF128);
660}
661
662RTLIB::Libcall RTLIB::getCBRT(EVT VT) {
663 // TODO: Tablegen should generate this function
664 if (VT.isVector()) {
665 if (!VT.isSimple())
666 return RTLIB::UNKNOWN_LIBCALL;
667 switch (VT.getSimpleVT().SimpleTy) {
668 case MVT::v4f32:
669 return RTLIB::CBRT_V4F32;
670 case MVT::v2f64:
671 return RTLIB::CBRT_V2F64;
672 case MVT::nxv4f32:
673 return RTLIB::CBRT_NXV4F32;
674 case MVT::nxv2f64:
675 return RTLIB::CBRT_NXV2F64;
676 default:
677 return RTLIB::UNKNOWN_LIBCALL;
678 }
679 }
680
681 return getFPLibCall(VT, Call_F32: CBRT_F32, Call_F64: CBRT_F64, Call_F80: CBRT_F80, Call_F128: CBRT_F128,
682 Call_PPCF128: CBRT_PPCF128);
683}
684
685RTLIB::Libcall RTLIB::getMODF(EVT RetVT) {
686 // TODO: Tablegen should generate this function
687 if (RetVT.isVector()) {
688 if (!RetVT.isSimple())
689 return RTLIB::UNKNOWN_LIBCALL;
690 switch (RetVT.getSimpleVT().SimpleTy) {
691 case MVT::v4f32:
692 return RTLIB::MODF_V4F32;
693 case MVT::v2f64:
694 return RTLIB::MODF_V2F64;
695 case MVT::nxv4f32:
696 return RTLIB::MODF_NXV4F32;
697 case MVT::nxv2f64:
698 return RTLIB::MODF_NXV2F64;
699 default:
700 return RTLIB::UNKNOWN_LIBCALL;
701 }
702 }
703
704 return getFPLibCall(VT: RetVT, Call_F32: MODF_F32, Call_F64: MODF_F64, Call_F80: MODF_F80, Call_F128: MODF_F128,
705 Call_PPCF128: MODF_PPCF128);
706}
707
708RTLIB::Libcall RTLIB::getLROUND(EVT VT) {
709 if (VT == MVT::f32)
710 return RTLIB::LROUND_F32;
711 if (VT == MVT::f64)
712 return RTLIB::LROUND_F64;
713 if (VT == MVT::f80)
714 return RTLIB::LROUND_F80;
715 if (VT == MVT::f128)
716 return RTLIB::LROUND_F128;
717 if (VT == MVT::ppcf128)
718 return RTLIB::LROUND_PPCF128;
719
720 return RTLIB::UNKNOWN_LIBCALL;
721}
722
723RTLIB::Libcall RTLIB::getLLROUND(EVT VT) {
724 if (VT == MVT::f32)
725 return RTLIB::LLROUND_F32;
726 if (VT == MVT::f64)
727 return RTLIB::LLROUND_F64;
728 if (VT == MVT::f80)
729 return RTLIB::LLROUND_F80;
730 if (VT == MVT::f128)
731 return RTLIB::LLROUND_F128;
732 if (VT == MVT::ppcf128)
733 return RTLIB::LLROUND_PPCF128;
734
735 return RTLIB::UNKNOWN_LIBCALL;
736}
737
738RTLIB::Libcall RTLIB::getLRINT(EVT VT) {
739 if (VT == MVT::f32)
740 return RTLIB::LRINT_F32;
741 if (VT == MVT::f64)
742 return RTLIB::LRINT_F64;
743 if (VT == MVT::f80)
744 return RTLIB::LRINT_F80;
745 if (VT == MVT::f128)
746 return RTLIB::LRINT_F128;
747 if (VT == MVT::ppcf128)
748 return RTLIB::LRINT_PPCF128;
749 return RTLIB::UNKNOWN_LIBCALL;
750}
751
752RTLIB::Libcall RTLIB::getLLRINT(EVT VT) {
753 if (VT == MVT::f32)
754 return RTLIB::LLRINT_F32;
755 if (VT == MVT::f64)
756 return RTLIB::LLRINT_F64;
757 if (VT == MVT::f80)
758 return RTLIB::LLRINT_F80;
759 if (VT == MVT::f128)
760 return RTLIB::LLRINT_F128;
761 if (VT == MVT::ppcf128)
762 return RTLIB::LLRINT_PPCF128;
763 return RTLIB::UNKNOWN_LIBCALL;
764}
765
766RTLIB::Libcall RTLIB::getOutlineAtomicHelper(const Libcall (&LC)[5][4],
767 AtomicOrdering Order,
768 uint64_t MemSize) {
769 unsigned ModeN, ModelN;
770 switch (MemSize) {
771 case 1:
772 ModeN = 0;
773 break;
774 case 2:
775 ModeN = 1;
776 break;
777 case 4:
778 ModeN = 2;
779 break;
780 case 8:
781 ModeN = 3;
782 break;
783 case 16:
784 ModeN = 4;
785 break;
786 default:
787 return RTLIB::UNKNOWN_LIBCALL;
788 }
789
790 switch (Order) {
791 case AtomicOrdering::Monotonic:
792 ModelN = 0;
793 break;
794 case AtomicOrdering::Acquire:
795 ModelN = 1;
796 break;
797 case AtomicOrdering::Release:
798 ModelN = 2;
799 break;
800 case AtomicOrdering::AcquireRelease:
801 case AtomicOrdering::SequentiallyConsistent:
802 ModelN = 3;
803 break;
804 default:
805 return UNKNOWN_LIBCALL;
806 }
807
808 return LC[ModeN][ModelN];
809}
810
811RTLIB::Libcall RTLIB::getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order,
812 MVT VT) {
813 if (!VT.isScalarInteger())
814 return UNKNOWN_LIBCALL;
815 uint64_t MemSize = VT.getScalarSizeInBits() / 8;
816
817#define LCALLS(A, B) \
818 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
819#define LCALL5(A) \
820 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
821 switch (Opc) {
822 case ISD::ATOMIC_CMP_SWAP: {
823 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
824 return getOutlineAtomicHelper(LC, Order, MemSize);
825 }
826 case ISD::ATOMIC_SWAP: {
827 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};
828 return getOutlineAtomicHelper(LC, Order, MemSize);
829 }
830 case ISD::ATOMIC_LOAD_ADD: {
831 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};
832 return getOutlineAtomicHelper(LC, Order, MemSize);
833 }
834 case ISD::ATOMIC_LOAD_OR: {
835 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};
836 return getOutlineAtomicHelper(LC, Order, MemSize);
837 }
838 case ISD::ATOMIC_LOAD_CLR: {
839 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};
840 return getOutlineAtomicHelper(LC, Order, MemSize);
841 }
842 case ISD::ATOMIC_LOAD_XOR: {
843 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};
844 return getOutlineAtomicHelper(LC, Order, MemSize);
845 }
846 default:
847 return UNKNOWN_LIBCALL;
848 }
849#undef LCALLS
850#undef LCALL5
851}
852
853RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
854#define OP_TO_LIBCALL(Name, Enum) \
855 case Name: \
856 switch (VT.SimpleTy) { \
857 default: \
858 return UNKNOWN_LIBCALL; \
859 case MVT::i8: \
860 return Enum##_1; \
861 case MVT::i16: \
862 return Enum##_2; \
863 case MVT::i32: \
864 return Enum##_4; \
865 case MVT::i64: \
866 return Enum##_8; \
867 case MVT::i128: \
868 return Enum##_16; \
869 }
870
871 switch (Opc) {
872 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
873 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
874 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
875 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
876 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
877 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
878 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
879 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
880 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
881 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
882 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
883 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
884 }
885
886#undef OP_TO_LIBCALL
887
888 return UNKNOWN_LIBCALL;
889}
890
891RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
892 switch (ElementSize) {
893 case 1:
894 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
895 case 2:
896 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
897 case 4:
898 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
899 case 8:
900 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
901 case 16:
902 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
903 default:
904 return UNKNOWN_LIBCALL;
905 }
906}
907
908RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
909 switch (ElementSize) {
910 case 1:
911 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
912 case 2:
913 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
914 case 4:
915 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
916 case 8:
917 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
918 case 16:
919 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
920 default:
921 return UNKNOWN_LIBCALL;
922 }
923}
924
925RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
926 switch (ElementSize) {
927 case 1:
928 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
929 case 2:
930 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
931 case 4:
932 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
933 case 8:
934 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
935 case 16:
936 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
937 default:
938 return UNKNOWN_LIBCALL;
939 }
940}
941
942ISD::CondCode TargetLoweringBase::getSoftFloatCmpLibcallPredicate(
943 RTLIB::LibcallImpl Impl) const {
944 switch (Impl) {
945 case RTLIB::impl___aeabi_dcmpeq__une:
946 case RTLIB::impl___aeabi_fcmpeq__une:
947 // Usage in the eq case, so we have to invert the comparison.
948 return ISD::SETEQ;
949 case RTLIB::impl___aeabi_dcmpeq__oeq:
950 case RTLIB::impl___aeabi_fcmpeq__oeq:
951 // Normal comparison to boolean value.
952 return ISD::SETNE;
953 case RTLIB::impl___aeabi_dcmplt:
954 case RTLIB::impl___aeabi_dcmple:
955 case RTLIB::impl___aeabi_dcmpge:
956 case RTLIB::impl___aeabi_dcmpgt:
957 case RTLIB::impl___aeabi_dcmpun:
958 case RTLIB::impl___aeabi_fcmplt:
959 case RTLIB::impl___aeabi_fcmple:
960 case RTLIB::impl___aeabi_fcmpge:
961 case RTLIB::impl___aeabi_fcmpgt:
962 /// The AEABI versions return a typical boolean value, so we can compare
963 /// against the integer result as simply != 0.
964 return ISD::SETNE;
965 default:
966 break;
967 }
968
969 // Assume libgcc/compiler-rt behavior. Most of the cases are really aliases of
970 // each other, and return a 3-way comparison style result of -1, 0, or 1
971 // depending on lt/eq/gt.
972 //
973 // FIXME: It would be cleaner to directly express this as a 3-way comparison
974 // soft FP libcall instead of individual compares.
975 RTLIB::Libcall LC = RTLIB::RuntimeLibcallsInfo::getLibcallFromImpl(Impl);
976 switch (LC) {
977 case RTLIB::OEQ_F32:
978 case RTLIB::OEQ_F64:
979 case RTLIB::OEQ_F128:
980 case RTLIB::OEQ_PPCF128:
981 return ISD::SETEQ;
982 case RTLIB::UNE_F32:
983 case RTLIB::UNE_F64:
984 case RTLIB::UNE_F128:
985 case RTLIB::UNE_PPCF128:
986 return ISD::SETNE;
987 case RTLIB::OGE_F32:
988 case RTLIB::OGE_F64:
989 case RTLIB::OGE_F128:
990 case RTLIB::OGE_PPCF128:
991 return ISD::SETGE;
992 case RTLIB::OLT_F32:
993 case RTLIB::OLT_F64:
994 case RTLIB::OLT_F128:
995 case RTLIB::OLT_PPCF128:
996 return ISD::SETLT;
997 case RTLIB::OLE_F32:
998 case RTLIB::OLE_F64:
999 case RTLIB::OLE_F128:
1000 case RTLIB::OLE_PPCF128:
1001 return ISD::SETLE;
1002 case RTLIB::OGT_F32:
1003 case RTLIB::OGT_F64:
1004 case RTLIB::OGT_F128:
1005 case RTLIB::OGT_PPCF128:
1006 return ISD::SETGT;
1007 case RTLIB::UO_F32:
1008 case RTLIB::UO_F64:
1009 case RTLIB::UO_F128:
1010 case RTLIB::UO_PPCF128:
1011 return ISD::SETNE;
1012 default:
1013 llvm_unreachable("not a compare libcall");
1014 }
1015}
1016
1017/// NOTE: The TargetMachine owns TLOF.
1018TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
1019 const TargetSubtargetInfo &STI)
1020 : TM(tm),
1021 RuntimeLibcallInfo(TM.getTargetTriple(), TM.Options.ExceptionModel,
1022 TM.Options.FloatABIType, TM.Options.EABIVersion,
1023 TM.Options.MCOptions.getABIName(), TM.Options.VecLib),
1024 Libcalls(RuntimeLibcallInfo, STI) {
1025 initActions();
1026
1027 // Perform these initializations only once.
1028 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove =
1029 MaxLoadsPerMemcmp = 8;
1030 MaxGluedStoresPerMemcpy = 0;
1031 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize =
1032 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4;
1033 HasExtractBitsInsn = false;
1034 JumpIsExpensive = JumpIsExpensiveOverride;
1035 PredictableSelectIsExpensive = false;
1036 EnableExtLdPromotion = false;
1037 StackPointerRegisterToSaveRestore = 0;
1038 BooleanContents = UndefinedBooleanContent;
1039 BooleanFloatContents = UndefinedBooleanContent;
1040 BooleanVectorContents = UndefinedBooleanContent;
1041 SchedPreferenceInfo = Sched::ILP;
1042 GatherAllAliasesMaxDepth = 18;
1043 IsStrictFPEnabled = DisableStrictNodeMutation;
1044 MaxBytesForAlignment = 0;
1045 MaxAtomicSizeInBitsSupported = 0;
1046
1047 // Assume that even with libcalls, no target supports wider than 128 bit
1048 // division.
1049 MaxDivRemBitWidthSupported = 128;
1050
1051 MaxLargeFPConvertBitWidthSupported = 128;
1052
1053 MinCmpXchgSizeInBits = 0;
1054 SupportsUnalignedAtomics = false;
1055
1056 MinimumBitTestCmps = MinimumBitTestCmpsOverride;
1057}
1058
1059// Define the virtual destructor out-of-line to act as a key method to anchor
1060// debug info (see coding standards).
1061TargetLoweringBase::~TargetLoweringBase() = default;
1062
1063void TargetLoweringBase::initActions() {
1064 // All operations default to being supported.
1065 memset(s: OpActions, c: 0, n: sizeof(OpActions));
1066 memset(s: LoadExtActions, c: 0, n: sizeof(LoadExtActions));
1067 memset(s: AtomicLoadExtActions, c: 0, n: sizeof(AtomicLoadExtActions));
1068 memset(s: TruncStoreActions, c: 0, n: sizeof(TruncStoreActions));
1069 memset(s: IndexedModeActions, c: 0, n: sizeof(IndexedModeActions));
1070 memset(s: CondCodeActions, c: 0, n: sizeof(CondCodeActions));
1071 llvm::fill(Range&: RegClassForVT, Value: nullptr);
1072 llvm::fill(Range&: TargetDAGCombineArray, Value: 0);
1073
1074 // Let extending atomic loads be unsupported by default.
1075 for (MVT ValVT : MVT::all_valuetypes())
1076 for (MVT MemVT : MVT::all_valuetypes())
1077 setAtomicLoadExtAction(ExtTypes: {ISD::SEXTLOAD, ISD::ZEXTLOAD}, ValVT, MemVT,
1078 Action: Expand);
1079
1080 // We're somewhat special casing MVT::i2 and MVT::i4. Ideally we want to
1081 // remove this and targets should individually set these types if not legal.
1082 for (ISD::NodeType NT : enum_seq(Begin: ISD::DELETED_NODE, End: ISD::BUILTIN_OP_END,
1083 force_iteration_on_noniterable_enum)) {
1084 for (MVT VT : {MVT::i2, MVT::i4})
1085 OpActions[(unsigned)VT.SimpleTy][NT] = Expand;
1086 }
1087 for (MVT AVT : MVT::all_valuetypes()) {
1088 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {
1089 setTruncStoreAction(ValVT: AVT, MemVT: VT, Action: Expand);
1090 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: AVT, MemVT: VT, Action: Expand);
1091 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: AVT, MemVT: VT, Action: Expand);
1092 }
1093 }
1094 for (unsigned IM = (unsigned)ISD::PRE_INC;
1095 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
1096 for (MVT VT : {MVT::i2, MVT::i4}) {
1097 setIndexedLoadAction(IdxModes: IM, VT, Action: Expand);
1098 setIndexedStoreAction(IdxModes: IM, VT, Action: Expand);
1099 setIndexedMaskedLoadAction(IdxMode: IM, VT, Action: Expand);
1100 setIndexedMaskedStoreAction(IdxMode: IM, VT, Action: Expand);
1101 }
1102 }
1103
1104 for (MVT VT : MVT::fp_valuetypes()) {
1105 MVT IntVT = MVT::getIntegerVT(BitWidth: VT.getFixedSizeInBits());
1106 if (IntVT.isValid()) {
1107 setOperationAction(Op: ISD::ATOMIC_SWAP, VT, Action: Promote);
1108 AddPromotedToType(Opc: ISD::ATOMIC_SWAP, OrigVT: VT, DestVT: IntVT);
1109 }
1110 }
1111
1112 // If f16 fma is not natively supported, the value must be promoted to an f64
1113 // (and not to f32!) to prevent double rounding issues.
1114 AddPromotedToType(Opc: ISD::FMA, OrigVT: MVT::f16, DestVT: MVT::f64);
1115 AddPromotedToType(Opc: ISD::STRICT_FMA, OrigVT: MVT::f16, DestVT: MVT::f64);
1116
1117 // Set default actions for various operations.
1118 for (MVT VT : MVT::all_valuetypes()) {
1119 // Default all indexed load / store to expand.
1120 for (unsigned IM = (unsigned)ISD::PRE_INC;
1121 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
1122 setIndexedLoadAction(IdxModes: IM, VT, Action: Expand);
1123 setIndexedStoreAction(IdxModes: IM, VT, Action: Expand);
1124 setIndexedMaskedLoadAction(IdxMode: IM, VT, Action: Expand);
1125 setIndexedMaskedStoreAction(IdxMode: IM, VT, Action: Expand);
1126 }
1127
1128 // Most backends expect to see the node which just returns the value loaded.
1129 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Action: Expand);
1130
1131 // clang-format off
1132 // These operations default to expand.
1133 setOperationAction(Ops: {ISD::FGETSIGN, ISD::CONCAT_VECTORS,
1134 ISD::FMINNUM, ISD::FMAXNUM,
1135 ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
1136 ISD::FMINIMUM, ISD::FMAXIMUM,
1137 ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM,
1138 ISD::FMAD, ISD::SMIN,
1139 ISD::SMAX, ISD::UMIN,
1140 ISD::UMAX, ISD::ABS,
1141 ISD::FSHL, ISD::FSHR,
1142 ISD::SADDSAT, ISD::UADDSAT,
1143 ISD::SSUBSAT, ISD::USUBSAT,
1144 ISD::SSHLSAT, ISD::USHLSAT,
1145 ISD::SMULFIX, ISD::SMULFIXSAT,
1146 ISD::UMULFIX, ISD::UMULFIXSAT,
1147 ISD::SDIVFIX, ISD::SDIVFIXSAT,
1148 ISD::UDIVFIX, ISD::UDIVFIXSAT,
1149 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT,
1150 ISD::IS_FPCLASS, ISD::FCBRT,
1151 ISD::FLOG, ISD::FLOG2,
1152 ISD::FLOG10, ISD::FEXP,
1153 ISD::FEXP2, ISD::FEXP10,
1154 ISD::FFLOOR, ISD::FNEARBYINT,
1155 ISD::FCEIL, ISD::FRINT,
1156 ISD::FTRUNC, ISD::FROUNDEVEN,
1157 ISD::FTAN, ISD::FACOS,
1158 ISD::FASIN, ISD::FATAN,
1159 ISD::FCOSH, ISD::FSINH,
1160 ISD::FTANH, ISD::FATAN2,
1161 ISD::FMULADD, ISD::CONVERT_FROM_ARBITRARY_FP,
1162 ISD::CONVERT_TO_ARBITRARY_FP,
1163 ISD::PSEUDO_FMIN, ISD::PSEUDO_FMAX},
1164 VT, Action: Expand);
1165 // clang-format on
1166
1167 // Overflow operations default to expand
1168 setOperationAction(Ops: {ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO,
1169 ISD::SMULO, ISD::UMULO},
1170 VT, Action: Expand);
1171
1172 // Carry-using overflow operations default to expand.
1173 setOperationAction(Ops: {ISD::UADDO_CARRY, ISD::USUBO_CARRY, ISD::SETCCCARRY,
1174 ISD::SADDO_CARRY, ISD::SSUBO_CARRY},
1175 VT, Action: Expand);
1176
1177 // ADDC/ADDE/SUBC/SUBE default to expand.
1178 setOperationAction(Ops: {ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT,
1179 Action: Expand);
1180
1181 // [US]CMP default to expand
1182 setOperationAction(Ops: {ISD::UCMP, ISD::SCMP}, VT, Action: Expand);
1183
1184 // Halving adds
1185 setOperationAction(
1186 Ops: {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT,
1187 Action: Expand);
1188
1189 // Absolute difference
1190 setOperationAction(Ops: {ISD::ABDS, ISD::ABDU}, VT, Action: Expand);
1191
1192 // Carry-less multiply
1193 setOperationAction(Ops: {ISD::CLMUL, ISD::CLMULR, ISD::CLMULH}, VT, Action: Expand);
1194
1195 // Bit extract/deposit (compress/expand)
1196 setOperationAction(Ops: {ISD::PEXT, ISD::PDEP}, VT, Action: Expand);
1197
1198 // Saturated trunc
1199 setOperationAction(Op: ISD::TRUNCATE_SSAT_S, VT, Action: Expand);
1200 setOperationAction(Op: ISD::TRUNCATE_SSAT_U, VT, Action: Expand);
1201 setOperationAction(Op: ISD::TRUNCATE_USAT_U, VT, Action: Expand);
1202
1203 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
1204 setOperationAction(Ops: {ISD::CTLZ_ZERO_POISON, ISD::CTTZ_ZERO_POISON}, VT,
1205 Action: Expand);
1206
1207 // This defaults to Expand so it will be expanded to ABS by default.
1208 setOperationAction(Op: ISD::ABS_MIN_POISON, VT, Action: Expand);
1209 setOperationAction(Op: ISD::CTLS, VT, Action: Expand);
1210
1211 setOperationAction(Ops: {ISD::BITREVERSE, ISD::PARITY}, VT, Action: Expand);
1212
1213 // These library functions default to expand.
1214 setOperationAction(Ops: {ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP,
1215 ISD::FSINCOS, ISD::FSINCOSPI, ISD::FMODF},
1216 VT, Action: Expand);
1217
1218 // These operations default to expand for vector types.
1219 if (VT.isVector())
1220 setOperationAction(Ops: {ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG,
1221 ISD::ANY_EXTEND_VECTOR_INREG,
1222 ISD::SIGN_EXTEND_VECTOR_INREG,
1223 ISD::ZERO_EXTEND_VECTOR_INREG, ISD::SPLAT_VECTOR,
1224 ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
1225 VT, Action: Expand);
1226
1227 // Constrained floating-point operations default to expand.
1228#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
1229 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
1230#include "llvm/IR/ConstrainedOps.def"
1231 setOperationAction(Op: ISD::STRICT_PSEUDO_FMIN, VT, Action: Expand);
1232 setOperationAction(Op: ISD::STRICT_PSEUDO_FMAX, VT, Action: Expand);
1233
1234 // For most targets @llvm.get.dynamic.area.offset just returns 0.
1235 setOperationAction(Op: ISD::GET_DYNAMIC_AREA_OFFSET, VT, Action: Expand);
1236
1237 // Vector reduction default to expand.
1238 setOperationAction(
1239 Ops: {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD,
1240 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR,
1241 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN,
1242 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX,
1243 ISD::VECREDUCE_FMIN, ISD::VECREDUCE_FMAXIMUM, ISD::VECREDUCE_FMINIMUM,
1244 ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_SEQ_FMUL},
1245 VT, Action: Expand);
1246
1247 // Named vector shuffles default to expand.
1248 setOperationAction(Ops: {ISD::VECTOR_SPLICE_LEFT, ISD::VECTOR_SPLICE_RIGHT}, VT,
1249 Action: Expand);
1250
1251 // Only some target support this vector operation. Most need to expand it.
1252 setOperationAction(Op: ISD::VECTOR_COMPRESS, VT, Action: Expand);
1253
1254 // cttz.elts defaults to expand.
1255 setOperationAction(Ops: {ISD::CTTZ_ELTS, ISD::CTTZ_ELTS_ZERO_POISON}, VT,
1256 Action: Expand);
1257
1258 // VP operations default to expand.
1259#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \
1260 setOperationAction(ISD::SDOPC, VT, Expand);
1261#include "llvm/IR/VPIntrinsics.def"
1262
1263 // Masked vector extracts default to expand.
1264 setOperationAction(Op: ISD::VECTOR_FIND_LAST_ACTIVE, VT, Action: Expand);
1265
1266 setOperationAction(Op: ISD::LOOP_DEPENDENCE_RAW_MASK, VT, Action: Expand);
1267 setOperationAction(Op: ISD::LOOP_DEPENDENCE_WAR_MASK, VT, Action: Expand);
1268
1269 // FP environment operations default to expand.
1270 setOperationAction(Op: ISD::GET_FPENV, VT, Action: Expand);
1271 setOperationAction(Op: ISD::SET_FPENV, VT, Action: Expand);
1272 setOperationAction(Op: ISD::RESET_FPENV, VT, Action: Expand);
1273
1274 setOperationAction(Op: ISD::MSTORE, VT, Action: Expand);
1275
1276 setOperationAction(Op: ISD::MASKED_UDIV, VT, Action: Expand);
1277 setOperationAction(Op: ISD::MASKED_SDIV, VT, Action: Expand);
1278 setOperationAction(Op: ISD::MASKED_UREM, VT, Action: Expand);
1279 setOperationAction(Op: ISD::MASKED_SREM, VT, Action: Expand);
1280 }
1281
1282 // Most targets ignore the @llvm.prefetch intrinsic.
1283 setOperationAction(Op: ISD::PREFETCH, VT: MVT::Other, Action: Expand);
1284
1285 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
1286 setOperationAction(Op: ISD::READCYCLECOUNTER, VT: MVT::i64, Action: Expand);
1287
1288 // Most targets also ignore the @llvm.readsteadycounter intrinsic.
1289 setOperationAction(Op: ISD::READSTEADYCOUNTER, VT: MVT::i64, Action: Expand);
1290
1291 // ConstantFP nodes default to expand. Targets can either change this to
1292 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
1293 // to optimize expansions for certain constants.
1294 setOperationAction(Ops: ISD::ConstantFP,
1295 VTs: {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},
1296 Action: Expand);
1297
1298 // Insert custom handling default for llvm.canonicalize.*.
1299 setOperationAction(Ops: ISD::FCANONICALIZE,
1300 VTs: {MVT::f16, MVT::f32, MVT::f64, MVT::f128}, Action: Expand);
1301
1302 // FIXME: Query RuntimeLibCalls to make the decision.
1303 setOperationAction(Ops: {ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
1304 VTs: {MVT::f32, MVT::f64, MVT::f128}, Action: LibCall);
1305
1306 setOperationAction(Ops: {ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH,
1307 ISD::FSINH, ISD::FTANH, ISD::FATAN2},
1308 VT: MVT::f16, Action: Promote);
1309 // Default ISD::TRAP to expand (which turns it into abort).
1310 setOperationAction(Op: ISD::TRAP, VT: MVT::Other, Action: Expand);
1311
1312 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
1313 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
1314 setOperationAction(Op: ISD::DEBUGTRAP, VT: MVT::Other, Action: Expand);
1315
1316 setOperationAction(Op: ISD::UBSANTRAP, VT: MVT::Other, Action: Expand);
1317
1318 setOperationAction(Op: ISD::GET_FPENV_MEM, VT: MVT::Other, Action: Expand);
1319 setOperationAction(Op: ISD::SET_FPENV_MEM, VT: MVT::Other, Action: Expand);
1320
1321 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
1322 setOperationAction(Op: ISD::GET_FPMODE, VT, Action: Expand);
1323 setOperationAction(Op: ISD::SET_FPMODE, VT, Action: Expand);
1324 }
1325 setOperationAction(Op: ISD::RESET_FPMODE, VT: MVT::Other, Action: Expand);
1326
1327 // This one by default will call __clear_cache unless the target
1328 // wants something different.
1329 setOperationAction(Op: ISD::CLEAR_CACHE, VT: MVT::Other, Action: LibCall);
1330
1331 // By default, STACKADDRESS nodes are expanded like STACKSAVE nodes.
1332 // On SPARC targets, custom lowering is required.
1333 setOperationAction(Op: ISD::STACKADDRESS, VT: MVT::Other, Action: Expand);
1334}
1335
1336MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
1337 EVT) const {
1338 return MVT::getIntegerVT(BitWidth: DL.getPointerSizeInBits(AS: 0));
1339}
1340
1341EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,
1342 const DataLayout &DL) const {
1343 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
1344 if (LHSTy.isVector())
1345 return LHSTy;
1346 MVT ShiftVT = getScalarShiftAmountTy(DL, LHSTy);
1347 // If any possible shift value won't fit in the prefered type, just use
1348 // something safe. Assume it will be legalized when the shift is expanded.
1349 if (ShiftVT.getSizeInBits() < Log2_32_Ceil(Value: LHSTy.getSizeInBits()))
1350 ShiftVT = MVT::i32;
1351 assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) &&
1352 "ShiftVT is still too small!");
1353 return ShiftVT;
1354}
1355
1356bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
1357 assert(isTypeLegal(VT));
1358 switch (Op) {
1359 default:
1360 return false;
1361 case ISD::SDIV:
1362 case ISD::UDIV:
1363 case ISD::SREM:
1364 case ISD::UREM:
1365 return true;
1366 }
1367}
1368
1369bool TargetLoweringBase::isFreeAddrSpaceCast(unsigned SrcAS,
1370 unsigned DestAS) const {
1371 return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
1372}
1373
1374unsigned TargetLoweringBase::getBitWidthForCttzElements(
1375 EVT RetVT, ElementCount EC, bool ZeroIsPoison,
1376 const ConstantRange *VScaleRange) const {
1377 // Find the smallest "sensible" element type to use for the expansion.
1378 ConstantRange CR(APInt(64, EC.getKnownMinValue()));
1379 if (EC.isScalable())
1380 CR = CR.umul_sat(Other: *VScaleRange);
1381
1382 if (ZeroIsPoison)
1383 CR = CR.subtract(CI: APInt(64, 1));
1384
1385 unsigned EltWidth = RetVT.getScalarSizeInBits();
1386 EltWidth = std::min(a: EltWidth, b: CR.getActiveBits());
1387 EltWidth = std::max(a: llvm::bit_ceil(Value: EltWidth), b: (unsigned)8);
1388
1389 return EltWidth;
1390}
1391
1392void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
1393 // If the command-line option was specified, ignore this request.
1394 if (!JumpIsExpensiveOverride.getNumOccurrences())
1395 JumpIsExpensive = isExpensive;
1396}
1397
1398TargetLoweringBase::LegalizeKind
1399TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
1400 // If this is a simple type, use the ComputeRegisterProp mechanism.
1401 if (VT.isSimple()) {
1402 MVT SVT = VT.getSimpleVT();
1403 assert((unsigned)SVT.SimpleTy < std::size(TransformToType));
1404 MVT NVT = TransformToType[SVT.SimpleTy];
1405 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(VT: SVT);
1406
1407 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
1408 LA == TypeSoftPromoteHalf ||
1409 (NVT.isVector() ||
1410 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
1411 "Promote may not follow Expand or Promote");
1412
1413 if (LA == TypeSplitVector)
1414 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
1415 if (LA == TypeScalarizeVector)
1416 return LegalizeKind(LA, SVT.getVectorElementType());
1417 return LegalizeKind(LA, NVT);
1418 }
1419
1420 // Handle Extended Scalar Types.
1421 if (!VT.isVector()) {
1422 assert(VT.isInteger() && "Float types must be simple");
1423 unsigned BitSize = VT.getSizeInBits();
1424 // First promote to a power-of-two size, then expand if necessary.
1425 if (BitSize < 8 || !isPowerOf2_32(Value: BitSize)) {
1426 EVT NVT = VT.getRoundIntegerType(Context);
1427 assert(NVT != VT && "Unable to round integer VT");
1428 LegalizeKind NextStep = getTypeConversion(Context, VT: NVT);
1429 // Avoid multi-step promotion.
1430 if (NextStep.first == TypePromoteInteger)
1431 return NextStep;
1432 // Return rounded integer type.
1433 return LegalizeKind(TypePromoteInteger, NVT);
1434 }
1435
1436 return LegalizeKind(TypeExpandInteger,
1437 EVT::getIntegerVT(Context, BitWidth: VT.getSizeInBits() / 2));
1438 }
1439
1440 // Handle vector types.
1441 ElementCount NumElts = VT.getVectorElementCount();
1442 EVT EltVT = VT.getVectorElementType();
1443
1444 // Vectors with only one element are always scalarized.
1445 if (NumElts.isScalar())
1446 return LegalizeKind(TypeScalarizeVector, EltVT);
1447
1448 // Try to widen vector elements until the element type is a power of two and
1449 // promote it to a legal type later on, for example:
1450 // <3 x i8> -> <4 x i8> -> <4 x i32>
1451 if (EltVT.isInteger()) {
1452 // Vectors with a number of elements that is not a power of two are always
1453 // widened, for example <3 x i8> -> <4 x i8>.
1454 if (!VT.isPow2VectorType()) {
1455 NumElts = NumElts.coefficientNextPowerOf2();
1456 EVT NVT = EVT::getVectorVT(Context, VT: EltVT, EC: NumElts);
1457 return LegalizeKind(TypeWidenVector, NVT);
1458 }
1459
1460 // Examine the element type.
1461 LegalizeKind LK = getTypeConversion(Context, VT: EltVT);
1462
1463 // If type is to be expanded, split the vector.
1464 // <4 x i140> -> <2 x i140>
1465 if (LK.first == TypeExpandInteger) {
1466 if (NumElts.isScalable() && NumElts.getKnownMinValue() == 1)
1467 return LegalizeKind(TypeScalarizeScalableVector, EltVT);
1468 return LegalizeKind(TypeSplitVector,
1469 VT.getHalfNumVectorElementsVT(Context));
1470 }
1471
1472 // Promote the integer element types until a legal vector type is found
1473 // or until the element integer type is too big. If a legal type was not
1474 // found, fallback to the usual mechanism of widening/splitting the
1475 // vector.
1476 EVT OldEltVT = EltVT;
1477 while (true) {
1478 // Increase the bitwidth of the element to the next pow-of-two
1479 // (which is greater than 8 bits).
1480 EltVT = EVT::getIntegerVT(Context, BitWidth: 1 + EltVT.getSizeInBits())
1481 .getRoundIntegerType(Context);
1482
1483 // Stop trying when getting a non-simple element type.
1484 // Note that vector elements may be greater than legal vector element
1485 // types. Example: X86 XMM registers hold 64bit element on 32bit
1486 // systems.
1487 if (!EltVT.isSimple())
1488 break;
1489
1490 // Build a new vector type and check if it is legal.
1491 MVT NVT = MVT::getVectorVT(VT: EltVT.getSimpleVT(), EC: NumElts);
1492 // Found a legal promoted vector type.
1493 if (NVT != MVT() && ValueTypeActions.getTypeAction(VT: NVT) == TypeLegal)
1494 return LegalizeKind(TypePromoteInteger,
1495 EVT::getVectorVT(Context, VT: EltVT, EC: NumElts));
1496 }
1497
1498 // Reset the type to the unexpanded type if we did not find a legal vector
1499 // type with a promoted vector element type.
1500 EltVT = OldEltVT;
1501 }
1502
1503 // Try to widen the vector until a legal type is found.
1504 // If there is no wider legal type, split the vector.
1505 while (true) {
1506 // Round up to the next power of 2.
1507 NumElts = NumElts.coefficientNextPowerOf2();
1508
1509 // If there is no simple vector type with this many elements then there
1510 // cannot be a larger legal vector type. Note that this assumes that
1511 // there are no skipped intermediate vector types in the simple types.
1512 if (!EltVT.isSimple())
1513 break;
1514 MVT LargerVector = MVT::getVectorVT(VT: EltVT.getSimpleVT(), EC: NumElts);
1515 if (LargerVector == MVT())
1516 break;
1517
1518 // If this type is legal then widen the vector.
1519 if (ValueTypeActions.getTypeAction(VT: LargerVector) == TypeLegal)
1520 return LegalizeKind(TypeWidenVector, LargerVector);
1521 }
1522
1523 // Widen odd vectors to next power of two.
1524 if (!VT.isPow2VectorType()) {
1525 EVT NVT = VT.getPow2VectorType(Context);
1526 return LegalizeKind(TypeWidenVector, NVT);
1527 }
1528
1529 if (VT.getVectorElementCount() == ElementCount::getScalable(MinVal: 1))
1530 return LegalizeKind(TypeScalarizeScalableVector, EltVT);
1531
1532 // Vectors with illegal element types are expanded.
1533 EVT NVT = EVT::getVectorVT(Context, VT: EltVT,
1534 EC: VT.getVectorElementCount().divideCoefficientBy(RHS: 2));
1535 return LegalizeKind(TypeSplitVector, NVT);
1536}
1537
1538static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1539 unsigned &NumIntermediates,
1540 MVT &RegisterVT,
1541 TargetLoweringBase *TLI) {
1542 // Figure out the right, legal destination reg to copy into.
1543 ElementCount EC = VT.getVectorElementCount();
1544 MVT EltTy = VT.getVectorElementType();
1545
1546 unsigned NumVectorRegs = 1;
1547
1548 // Scalable vectors cannot be scalarized, so splitting or widening is
1549 // required.
1550 if (VT.isScalableVector() && !isPowerOf2_32(Value: EC.getKnownMinValue()))
1551 llvm_unreachable(
1552 "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1553
1554 // FIXME: We don't support non-power-of-2-sized vectors for now.
1555 // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1556 if (!isPowerOf2_32(Value: EC.getKnownMinValue())) {
1557 // Split EC to unit size (scalable property is preserved).
1558 NumVectorRegs = EC.getKnownMinValue();
1559 EC = ElementCount::getFixed(MinVal: 1);
1560 }
1561
1562 // Divide the input until we get to a supported size. This will
1563 // always end up with an EC that represent a scalar or a scalable
1564 // scalar.
1565 while (EC.getKnownMinValue() > 1 &&
1566 !TLI->isTypeLegal(VT: MVT::getVectorVT(VT: EltTy, EC))) {
1567 EC = EC.divideCoefficientBy(RHS: 2);
1568 NumVectorRegs <<= 1;
1569 }
1570
1571 NumIntermediates = NumVectorRegs;
1572
1573 MVT NewVT = MVT::getVectorVT(VT: EltTy, EC);
1574 if (!TLI->isTypeLegal(VT: NewVT))
1575 NewVT = EltTy;
1576 IntermediateVT = NewVT;
1577
1578 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
1579
1580 // Convert sizes such as i33 to i64.
1581 LaneSizeInBits = llvm::bit_ceil(Value: LaneSizeInBits);
1582
1583 MVT DestVT = TLI->getRegisterType(VT: NewVT);
1584 RegisterVT = DestVT;
1585 if (EVT(DestVT).bitsLT(VT: NewVT)) // Value is expanded, e.g. i64 -> i16.
1586 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1587
1588 // Otherwise, promotion or legal types use the same number of registers as
1589 // the vector decimated to the appropriate level.
1590 return NumVectorRegs;
1591}
1592
1593/// isLegalRC - Return true if the value types that can be represented by the
1594/// specified register class are all legal.
1595bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
1596 const TargetRegisterClass &RC) const {
1597 for (const auto *I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1598 if (isTypeLegal(VT: *I))
1599 return true;
1600 return false;
1601}
1602
1603/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1604/// sequence of memory operands that is recognized by PrologEpilogInserter.
1605MachineBasicBlock *
1606TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
1607 MachineBasicBlock *MBB) const {
1608 MachineInstr *MI = &InitialMI;
1609 MachineFunction &MF = *MI->getMF();
1610 MachineFrameInfo &MFI = MF.getFrameInfo();
1611
1612 // We're handling multiple types of operands here:
1613 // PATCHPOINT MetaArgs - live-in, read only, direct
1614 // STATEPOINT Deopt Spill - live-through, read only, indirect
1615 // STATEPOINT Deopt Alloca - live-through, read only, direct
1616 // (We're currently conservative and mark the deopt slots read/write in
1617 // practice.)
1618 // STATEPOINT GC Spill - live-through, read/write, indirect
1619 // STATEPOINT GC Alloca - live-through, read/write, direct
1620 // The live-in vs live-through is handled already (the live through ones are
1621 // all stack slots), but we need to handle the different type of stackmap
1622 // operands and memory effects here.
1623
1624 if (llvm::none_of(Range: MI->operands(),
1625 P: [](MachineOperand &Operand) { return Operand.isFI(); }))
1626 return MBB;
1627
1628 MachineInstrBuilder MIB = BuildMI(MF, MIMD: MI->getDebugLoc(), MCID: MI->getDesc());
1629
1630 // Inherit previous memory operands.
1631 MIB.cloneMemRefs(OtherMI: *MI);
1632
1633 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1634 MachineOperand &MO = MI->getOperand(i);
1635 if (!MO.isFI()) {
1636 // Index of Def operand this Use it tied to.
1637 // Since Defs are coming before Uses, if Use is tied, then
1638 // index of Def must be smaller that index of that Use.
1639 // Also, Defs preserve their position in new MI.
1640 unsigned TiedTo = i;
1641 if (MO.isReg() && MO.isTied())
1642 TiedTo = MI->findTiedOperandIdx(OpIdx: i);
1643 MIB.add(MO);
1644 if (TiedTo < i)
1645 MIB->tieOperands(DefIdx: TiedTo, UseIdx: MIB->getNumOperands() - 1);
1646 continue;
1647 }
1648
1649 // foldMemoryOperand builds a new MI after replacing a single FI operand
1650 // with the canonical set of five x86 addressing-mode operands.
1651 int FI = MO.getIndex();
1652
1653 // Add frame index operands recognized by stackmaps.cpp
1654 if (MFI.isStatepointSpillSlotObjectIndex(ObjectIdx: FI)) {
1655 // indirect-mem-ref tag, size, #FI, offset.
1656 // Used for spills inserted by StatepointLowering. This codepath is not
1657 // used for patchpoints/stackmaps at all, for these spilling is done via
1658 // foldMemoryOperand callback only.
1659 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1660 MIB.addImm(Val: StackMaps::IndirectMemRefOp);
1661 MIB.addImm(Val: MFI.getObjectSize(ObjectIdx: FI));
1662 MIB.add(MO);
1663 MIB.addImm(Val: 0);
1664 } else {
1665 // direct-mem-ref tag, #FI, offset.
1666 // Used by patchpoint, and direct alloca arguments to statepoints
1667 MIB.addImm(Val: StackMaps::DirectMemRefOp);
1668 MIB.add(MO);
1669 MIB.addImm(Val: 0);
1670 }
1671
1672 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1673
1674 // Add a new memory operand for this FI.
1675 assert(MFI.getObjectOffset(FI) != -1);
1676
1677 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1678 // PATCHPOINT should be updated to do the same. (TODO)
1679 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1680 auto Flags = MachineMemOperand::MOLoad;
1681 MachineMemOperand *MMO = MF.getMachineMemOperand(
1682 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI), F: Flags,
1683 Size: MF.getDataLayout().getPointerSize(), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
1684 MIB->addMemOperand(MF, MO: MMO);
1685 }
1686 }
1687 MBB->insert(I: MachineBasicBlock::iterator(MI), MI: MIB);
1688 MI->eraseFromParent();
1689 return MBB;
1690}
1691
1692/// findRepresentativeClass - Return the largest legal super-reg register class
1693/// of the register class for the specified type and its associated "cost".
1694// This function is in TargetLowering because it uses RegClassForVT which would
1695// need to be moved to TargetRegisterInfo and would necessitate moving
1696// isTypeLegal over as well - a massive change that would just require
1697// TargetLowering having a TargetRegisterInfo class member that it would use.
1698std::pair<const TargetRegisterClass *, uint8_t>
1699TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1700 MVT VT) const {
1701 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1702 if (!RC)
1703 return std::make_pair(x&: RC, y: 0);
1704
1705 // Compute the set of all super-register classes.
1706 BitVector SuperRegRC(TRI->getNumRegClasses());
1707 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1708 SuperRegRC.setBitsInMask(Mask: RCI.getMask());
1709
1710 // Find the first legal register class with the largest spill size.
1711 const TargetRegisterClass *BestRC = RC;
1712 for (unsigned i : SuperRegRC.set_bits()) {
1713 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1714 // We want the largest possible spill size.
1715 if (TRI->getSpillSize(RC: *SuperRC) <= TRI->getSpillSize(RC: *BestRC))
1716 continue;
1717 if (!isLegalRC(TRI: *TRI, RC: *SuperRC))
1718 continue;
1719 BestRC = SuperRC;
1720 }
1721 return std::make_pair(x&: BestRC, y: 1);
1722}
1723
1724/// computeRegisterProperties - Once all of the register classes are added,
1725/// this allows us to compute derived properties we expose.
1726void TargetLoweringBase::computeRegisterProperties(
1727 const TargetRegisterInfo *TRI) {
1728 // Everything defaults to needing one register.
1729 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1730 NumRegistersForVT[i] = 1;
1731 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1732 }
1733 // ...except isVoid, which doesn't need any registers.
1734 NumRegistersForVT[MVT::isVoid] = 0;
1735
1736 // Find the largest integer register class.
1737 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1738 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1739 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1740
1741 // Every integer value type larger than this largest register takes twice as
1742 // many registers to represent as the previous ValueType.
1743 for (unsigned ExpandedReg = LargestIntReg + 1;
1744 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1745 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1746 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1747 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1748 ValueTypeActions.setTypeAction(VT: (MVT::SimpleValueType)ExpandedReg,
1749 Action: TypeExpandInteger);
1750 }
1751
1752 // Inspect all of the ValueType's smaller than the largest integer
1753 // register to see which ones need promotion.
1754 unsigned LegalIntReg = LargestIntReg;
1755 for (unsigned IntReg = LargestIntReg - 1;
1756 IntReg >= (unsigned)MVT::i1; --IntReg) {
1757 MVT IVT = (MVT::SimpleValueType)IntReg;
1758 if (isTypeLegal(VT: IVT)) {
1759 LegalIntReg = IntReg;
1760 } else {
1761 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1762 (MVT::SimpleValueType)LegalIntReg;
1763 ValueTypeActions.setTypeAction(VT: IVT, Action: TypePromoteInteger);
1764 }
1765 }
1766
1767 // ppcf128 type is really two f64's.
1768 if (!isTypeLegal(VT: MVT::ppcf128)) {
1769 if (isTypeLegal(VT: MVT::f64)) {
1770 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1771 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1772 TransformToType[MVT::ppcf128] = MVT::f64;
1773 ValueTypeActions.setTypeAction(VT: MVT::ppcf128, Action: TypeExpandFloat);
1774 } else {
1775 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1776 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1777 TransformToType[MVT::ppcf128] = MVT::i128;
1778 ValueTypeActions.setTypeAction(VT: MVT::ppcf128, Action: TypeSoftenFloat);
1779 }
1780 }
1781
1782 // Decide how to handle f128. If the target does not have native f128 support,
1783 // expand it to i128 and we will be generating soft float library calls.
1784 if (!isTypeLegal(VT: MVT::f128)) {
1785 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1786 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1787 TransformToType[MVT::f128] = MVT::i128;
1788 ValueTypeActions.setTypeAction(VT: MVT::f128, Action: TypeSoftenFloat);
1789 }
1790
1791 // Decide how to handle f80. If the target does not have native f80 support,
1792 // expand it to i96 and we will be generating soft float library calls.
1793 if (!isTypeLegal(VT: MVT::f80)) {
1794 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];
1795 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];
1796 TransformToType[MVT::f80] = MVT::i32;
1797 ValueTypeActions.setTypeAction(VT: MVT::f80, Action: TypeSoftenFloat);
1798 }
1799
1800 // Decide how to handle f64. If the target does not have native f64 support,
1801 // expand it to i64 and we will be generating soft float library calls.
1802 if (!isTypeLegal(VT: MVT::f64)) {
1803 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1804 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1805 TransformToType[MVT::f64] = MVT::i64;
1806 ValueTypeActions.setTypeAction(VT: MVT::f64, Action: TypeSoftenFloat);
1807 }
1808
1809 // Decide how to handle f32. If the target does not have native f32 support,
1810 // expand it to i32 and we will be generating soft float library calls.
1811 if (!isTypeLegal(VT: MVT::f32)) {
1812 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1813 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1814 TransformToType[MVT::f32] = MVT::i32;
1815 ValueTypeActions.setTypeAction(VT: MVT::f32, Action: TypeSoftenFloat);
1816 }
1817
1818 // Decide how to handle f16. If the target does not have native f16 support,
1819 // promote it to f32, because there are no f16 library calls (except for
1820 // conversions).
1821 if (!isTypeLegal(VT: MVT::f16)) {
1822 // Allow targets to control how we legalize half.
1823 bool UseFPRegsForHalfType = useFPRegsForHalfType();
1824
1825 if (!UseFPRegsForHalfType) {
1826 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1827 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1828 } else {
1829 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1830 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1831 }
1832 TransformToType[MVT::f16] = MVT::f32;
1833 ValueTypeActions.setTypeAction(VT: MVT::f16, Action: TypeSoftPromoteHalf);
1834 }
1835
1836 // Decide how to handle bf16. If the target does not have native bf16 support,
1837 // promote it to f32, because there are no bf16 library calls (except for
1838 // converting from f32 to bf16).
1839 if (!isTypeLegal(VT: MVT::bf16)) {
1840 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];
1841 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];
1842 TransformToType[MVT::bf16] = MVT::f32;
1843 ValueTypeActions.setTypeAction(VT: MVT::bf16, Action: TypeSoftPromoteHalf);
1844 }
1845
1846 // Loop over all of the vector value types to see which need transformations.
1847 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1848 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1849 MVT VT = (MVT::SimpleValueType) i;
1850 if (isTypeLegal(VT))
1851 continue;
1852
1853 MVT EltVT = VT.getVectorElementType();
1854 ElementCount EC = VT.getVectorElementCount();
1855 bool IsLegalWiderType = false;
1856 bool IsScalable = VT.isScalableVector();
1857 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1858 switch (PreferredAction) {
1859 case TypePromoteInteger: {
1860 MVT::SimpleValueType EndVT = IsScalable ?
1861 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :
1862 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;
1863 // Try to promote the elements of integer vectors. If no legal
1864 // promotion was found, fall through to the widen-vector method.
1865 for (unsigned nVT = i + 1;
1866 (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1867 MVT SVT = (MVT::SimpleValueType) nVT;
1868 // Promote vectors of integers to vectors with the same number
1869 // of elements, with a wider element type.
1870 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1871 SVT.getVectorElementCount() == EC && isTypeLegal(VT: SVT)) {
1872 TransformToType[i] = SVT;
1873 RegisterTypeForVT[i] = SVT;
1874 NumRegistersForVT[i] = 1;
1875 ValueTypeActions.setTypeAction(VT, Action: TypePromoteInteger);
1876 IsLegalWiderType = true;
1877 break;
1878 }
1879 }
1880 if (IsLegalWiderType)
1881 break;
1882 [[fallthrough]];
1883 }
1884
1885 case TypeWidenVector:
1886 if (isPowerOf2_32(Value: EC.getKnownMinValue())) {
1887 // Try to widen the vector.
1888 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1889 MVT SVT = (MVT::SimpleValueType) nVT;
1890 if (SVT.getVectorElementType() == EltVT &&
1891 SVT.isScalableVector() == IsScalable &&
1892 SVT.getVectorElementCount().getKnownMinValue() >
1893 EC.getKnownMinValue() &&
1894 isTypeLegal(VT: SVT)) {
1895 TransformToType[i] = SVT;
1896 RegisterTypeForVT[i] = SVT;
1897 NumRegistersForVT[i] = 1;
1898 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1899 IsLegalWiderType = true;
1900 break;
1901 }
1902 }
1903 if (IsLegalWiderType)
1904 break;
1905 } else {
1906 // Only widen to the next power of 2 to keep consistency with EVT.
1907 MVT NVT = VT.getPow2VectorType();
1908 if (isTypeLegal(VT: NVT)) {
1909 TransformToType[i] = NVT;
1910 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1911 RegisterTypeForVT[i] = NVT;
1912 NumRegistersForVT[i] = 1;
1913 break;
1914 }
1915 }
1916 [[fallthrough]];
1917
1918 case TypeSplitVector:
1919 case TypeScalarizeVector: {
1920 MVT IntermediateVT;
1921 MVT RegisterVT;
1922 unsigned NumIntermediates;
1923 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1924 NumIntermediates, RegisterVT, TLI: this);
1925 NumRegistersForVT[i] = NumRegisters;
1926 assert(NumRegistersForVT[i] == NumRegisters &&
1927 "NumRegistersForVT size cannot represent NumRegisters!");
1928 RegisterTypeForVT[i] = RegisterVT;
1929
1930 MVT NVT = VT.getPow2VectorType();
1931 if (NVT == VT) {
1932 // Type is already a power of 2. The default action is to split.
1933 TransformToType[i] = MVT::Other;
1934 if (PreferredAction == TypeScalarizeVector)
1935 ValueTypeActions.setTypeAction(VT, Action: TypeScalarizeVector);
1936 else if (PreferredAction == TypeSplitVector)
1937 ValueTypeActions.setTypeAction(VT, Action: TypeSplitVector);
1938 else if (EC.getKnownMinValue() > 1)
1939 ValueTypeActions.setTypeAction(VT, Action: TypeSplitVector);
1940 else
1941 ValueTypeActions.setTypeAction(VT, Action: EC.isScalable()
1942 ? TypeScalarizeScalableVector
1943 : TypeScalarizeVector);
1944 } else {
1945 TransformToType[i] = NVT;
1946 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1947 }
1948 break;
1949 }
1950 default:
1951 llvm_unreachable("Unknown vector legalization action!");
1952 }
1953 }
1954
1955 // Determine the 'representative' register class for each value type.
1956 // An representative register class is the largest (meaning one which is
1957 // not a sub-register class / subreg register class) legal register class for
1958 // a group of value types. For example, on i386, i8, i16, and i32
1959 // representative would be GR32; while on x86_64 it's GR64.
1960 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1961 const TargetRegisterClass* RRC;
1962 uint8_t Cost;
1963 std::tie(args&: RRC, args&: Cost) = findRepresentativeClass(TRI, VT: (MVT::SimpleValueType)i);
1964 RepRegClassForVT[i] = RRC;
1965 RepRegClassCostForVT[i] = Cost;
1966 }
1967
1968 // Compute minimum known-legal store size.
1969 MaximumLegalStoreInBits = 0;
1970 for (MVT VT : MVT::all_valuetypes())
1971 if (VT != MVT::Other && isTypeLegal(VT) &&
1972 VT.getSizeInBits().getKnownMinValue() >= MaximumLegalStoreInBits)
1973 MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinValue();
1974}
1975
1976EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1977 EVT VT) const {
1978 assert(!VT.isVector() && "No default SetCC type for vectors!");
1979 return getPointerTy(DL).SimpleTy;
1980}
1981
1982/// getVectorTypeBreakdown - Vector types are broken down into some number of
1983/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1984/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1985/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1986///
1987/// This method returns the number of registers needed, and the VT for each
1988/// register. It also returns the VT and quantity of the intermediate values
1989/// before they are promoted/expanded.
1990unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context,
1991 EVT VT, EVT &IntermediateVT,
1992 unsigned &NumIntermediates,
1993 MVT &RegisterVT) const {
1994 ElementCount EltCnt = VT.getVectorElementCount();
1995
1996 // If there is a wider vector type with the same element type as this one,
1997 // or a promoted vector type that has the same number of elements which
1998 // are wider, then we should convert to that legal vector type.
1999 // This handles things like <2 x float> -> <4 x float> and
2000 // <4 x i1> -> <4 x i32>.
2001 LegalizeTypeAction TA = getTypeAction(Context, VT);
2002 if (!EltCnt.isScalar() &&
2003 (TA == TypeWidenVector || TA == TypePromoteInteger)) {
2004 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
2005 if (isTypeLegal(VT: RegisterEVT)) {
2006 IntermediateVT = RegisterEVT;
2007 RegisterVT = RegisterEVT.getSimpleVT();
2008 NumIntermediates = 1;
2009 return 1;
2010 }
2011 }
2012
2013 // Figure out the right, legal destination reg to copy into.
2014 EVT EltTy = VT.getVectorElementType();
2015
2016 unsigned NumVectorRegs = 1;
2017
2018 // Scalable vectors cannot be scalarized, so handle the legalisation of the
2019 // types like done elsewhere in SelectionDAG.
2020 if (EltCnt.isScalable()) {
2021 LegalizeKind LK;
2022 EVT PartVT = VT;
2023 do {
2024 // Iterate until we've found a legal (part) type to hold VT.
2025 LK = getTypeConversion(Context, VT: PartVT);
2026 PartVT = LK.second;
2027 } while (LK.first != TypeLegal);
2028
2029 if (!PartVT.isVector()) {
2030 report_fatal_error(
2031 reason: "Don't know how to legalize this scalable vector type");
2032 }
2033
2034 NumIntermediates =
2035 divideCeil(Numerator: VT.getVectorElementCount().getKnownMinValue(),
2036 Denominator: PartVT.getVectorElementCount().getKnownMinValue());
2037 IntermediateVT = PartVT;
2038 RegisterVT = getRegisterType(Context, VT: IntermediateVT);
2039 return NumIntermediates;
2040 }
2041
2042 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally
2043 // we could break down into LHS/RHS like LegalizeDAG does.
2044 if (!isPowerOf2_32(Value: EltCnt.getKnownMinValue())) {
2045 NumVectorRegs = EltCnt.getKnownMinValue();
2046 EltCnt = ElementCount::getFixed(MinVal: 1);
2047 }
2048
2049 // Divide the input until we get to a supported size. This will always
2050 // end with a scalar if the target doesn't support vectors.
2051 while (EltCnt.getKnownMinValue() > 1 &&
2052 !isTypeLegal(VT: EVT::getVectorVT(Context, VT: EltTy, EC: EltCnt))) {
2053 EltCnt = EltCnt.divideCoefficientBy(RHS: 2);
2054 NumVectorRegs <<= 1;
2055 }
2056
2057 NumIntermediates = NumVectorRegs;
2058
2059 EVT NewVT = EVT::getVectorVT(Context, VT: EltTy, EC: EltCnt);
2060 if (!isTypeLegal(VT: NewVT))
2061 NewVT = EltTy;
2062 IntermediateVT = NewVT;
2063
2064 MVT DestVT = getRegisterType(Context, VT: NewVT);
2065 RegisterVT = DestVT;
2066
2067 if (EVT(DestVT).bitsLT(VT: NewVT)) { // Value is expanded, e.g. i64 -> i16.
2068 TypeSize NewVTSize = NewVT.getSizeInBits();
2069 // Convert sizes such as i33 to i64.
2070 if (!llvm::has_single_bit<uint32_t>(Value: NewVTSize.getKnownMinValue()))
2071 NewVTSize = NewVTSize.coefficientNextPowerOf2();
2072 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
2073 }
2074
2075 // Otherwise, promotion or legal types use the same number of registers as
2076 // the vector decimated to the appropriate level.
2077 return NumVectorRegs;
2078}
2079
2080bool TargetLoweringBase::isSuitableForJumpTable(const SwitchInst *SI,
2081 uint64_t NumCases,
2082 uint64_t Range,
2083 ProfileSummaryInfo *PSI,
2084 BlockFrequencyInfo *BFI) const {
2085 // FIXME: This function check the maximum table size and density, but the
2086 // minimum size is not checked. It would be nice if the minimum size is
2087 // also combined within this function. Currently, the minimum size check is
2088 // performed in findJumpTable() in SelectionDAGBuiler and
2089 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
2090 const bool OptForSize =
2091 llvm::shouldOptimizeForSize(BB: SI->getParent(), PSI, BFI);
2092 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
2093 const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
2094
2095 // Check whether the number of cases is small enough and
2096 // the range is dense enough for a jump table.
2097 return (OptForSize || Range <= MaxJumpTableSize) &&
2098 (NumCases * 100 >= Range * MinDensity);
2099}
2100
2101MVT TargetLoweringBase::getPreferredSwitchConditionType(LLVMContext &Context,
2102 EVT ConditionVT) const {
2103 return getRegisterType(Context, VT: ConditionVT);
2104}
2105
2106/// Get the EVTs and ArgFlags collections that represent the legalized return
2107/// type of the given function. This does not require a DAG or a return value,
2108/// and is suitable for use before any DAGs for the function are constructed.
2109/// TODO: Move this out of TargetLowering.cpp.
2110void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType,
2111 AttributeList attr,
2112 SmallVectorImpl<ISD::OutputArg> &Outs,
2113 const TargetLowering &TLI, const DataLayout &DL) {
2114 SmallVector<Type *, 4> Types;
2115 ComputeValueTypes(DL, Ty: ReturnType, Types);
2116 unsigned NumValues = Types.size();
2117 if (NumValues == 0) return;
2118
2119 for (Type *Ty : Types) {
2120 EVT VT = TLI.getValueType(DL, Ty);
2121 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
2122
2123 if (attr.hasRetAttr(Kind: Attribute::SExt))
2124 ExtendKind = ISD::SIGN_EXTEND;
2125 else if (attr.hasRetAttr(Kind: Attribute::ZExt))
2126 ExtendKind = ISD::ZERO_EXTEND;
2127
2128 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
2129 VT = TLI.getTypeForExtReturn(Context&: ReturnType->getContext(), VT, ExtendKind);
2130
2131 unsigned NumParts =
2132 TLI.getNumRegistersForCallingConv(Context&: ReturnType->getContext(), CC, VT);
2133 MVT PartVT =
2134 TLI.getRegisterTypeForCallingConv(Context&: ReturnType->getContext(), CC, VT);
2135
2136 // 'inreg' on function refers to return value
2137 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
2138 if (attr.hasRetAttr(Kind: Attribute::InReg))
2139 Flags.setInReg();
2140
2141 // Propagate extension type if any
2142 if (attr.hasRetAttr(Kind: Attribute::SExt))
2143 Flags.setSExt();
2144 else if (attr.hasRetAttr(Kind: Attribute::ZExt))
2145 Flags.setZExt();
2146
2147 for (unsigned i = 0; i < NumParts; ++i)
2148 Outs.push_back(Elt: ISD::OutputArg(Flags, PartVT, VT, Ty, 0, 0));
2149 }
2150}
2151
2152Align TargetLoweringBase::getByValTypeAlignment(Type *Ty,
2153 const DataLayout &DL) const {
2154 return DL.getABITypeAlign(Ty);
2155}
2156
2157bool TargetLoweringBase::allowsMemoryAccessForAlignment(
2158 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
2159 Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const {
2160 // Check if the specified alignment is sufficient based on the data layout.
2161 // TODO: While using the data layout works in practice, a better solution
2162 // would be to implement this check directly (make this a virtual function).
2163 // For example, the ABI alignment may change based on software platform while
2164 // this function should only be affected by hardware implementation.
2165 Type *Ty = VT.getTypeForEVT(Context);
2166 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {
2167 // Assume that an access that meets the ABI-specified alignment is fast.
2168 if (Fast != nullptr)
2169 *Fast = 1;
2170 return true;
2171 }
2172
2173 // This is a misaligned access.
2174 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
2175}
2176
2177bool TargetLoweringBase::allowsMemoryAccessForAlignment(
2178 LLVMContext &Context, const DataLayout &DL, EVT VT,
2179 const MachineMemOperand &MMO, unsigned *Fast) const {
2180 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace: MMO.getAddrSpace(),
2181 Alignment: MMO.getAlign(), Flags: MMO.getFlags(), Fast);
2182}
2183
2184bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
2185 const DataLayout &DL, EVT VT,
2186 unsigned AddrSpace, Align Alignment,
2187 MachineMemOperand::Flags Flags,
2188 unsigned *Fast) const {
2189 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
2190 Flags, Fast);
2191}
2192
2193bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
2194 const DataLayout &DL, EVT VT,
2195 const MachineMemOperand &MMO,
2196 unsigned *Fast) const {
2197 return allowsMemoryAccess(Context, DL, VT, AddrSpace: MMO.getAddrSpace(), Alignment: MMO.getAlign(),
2198 Flags: MMO.getFlags(), Fast);
2199}
2200
2201bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
2202 const DataLayout &DL, LLT Ty,
2203 const MachineMemOperand &MMO,
2204 unsigned *Fast) const {
2205 EVT VT = getApproximateEVTForLLT(Ty, Ctx&: Context);
2206 return allowsMemoryAccess(Context, DL, VT, AddrSpace: MMO.getAddrSpace(), Alignment: MMO.getAlign(),
2207 Flags: MMO.getFlags(), Fast);
2208}
2209
2210unsigned TargetLoweringBase::getMaxStoresPerMemset(bool OptSize) const {
2211 if (MaxStoresPerMemsetOverride > 0)
2212 return MaxStoresPerMemsetOverride;
2213
2214 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
2215}
2216
2217unsigned TargetLoweringBase::getMaxStoresPerMemcpy(bool OptSize) const {
2218 if (MaxStoresPerMemcpyOverride > 0)
2219 return MaxStoresPerMemcpyOverride;
2220
2221 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
2222}
2223
2224unsigned TargetLoweringBase::getMaxStoresPerMemmove(bool OptSize) const {
2225 if (MaxStoresPerMemmoveOverride > 0)
2226 return MaxStoresPerMemmoveOverride;
2227
2228 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
2229}
2230
2231//===----------------------------------------------------------------------===//
2232// TargetTransformInfo Helpers
2233//===----------------------------------------------------------------------===//
2234
2235int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
2236 enum InstructionOpcodes {
2237#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
2238#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
2239#include "llvm/IR/Instruction.def"
2240 };
2241 switch (static_cast<InstructionOpcodes>(Opcode)) {
2242 case Ret: return 0;
2243 case UncondBr: return 0;
2244 case CondBr: return 0;
2245 case Switch: return 0;
2246 case IndirectBr: return 0;
2247 case Invoke: return 0;
2248 case CallBr: return 0;
2249 case Resume: return 0;
2250 case Unreachable: return 0;
2251 case CleanupRet: return 0;
2252 case CatchRet: return 0;
2253 case CatchPad: return 0;
2254 case CatchSwitch: return 0;
2255 case CleanupPad: return 0;
2256 case FNeg: return ISD::FNEG;
2257 case Add: return ISD::ADD;
2258 case FAdd: return ISD::FADD;
2259 case Sub: return ISD::SUB;
2260 case FSub: return ISD::FSUB;
2261 case Mul: return ISD::MUL;
2262 case FMul: return ISD::FMUL;
2263 case UDiv: return ISD::UDIV;
2264 case SDiv: return ISD::SDIV;
2265 case FDiv: return ISD::FDIV;
2266 case URem: return ISD::UREM;
2267 case SRem: return ISD::SREM;
2268 case FRem: return ISD::FREM;
2269 case Shl: return ISD::SHL;
2270 case LShr: return ISD::SRL;
2271 case AShr: return ISD::SRA;
2272 case And: return ISD::AND;
2273 case Or: return ISD::OR;
2274 case Xor: return ISD::XOR;
2275 case Alloca: return 0;
2276 case Load: return ISD::LOAD;
2277 case Store: return ISD::STORE;
2278 case GetElementPtr: return 0;
2279 case Fence: return 0;
2280 case AtomicCmpXchg: return 0;
2281 case AtomicRMW: return 0;
2282 case Trunc: return ISD::TRUNCATE;
2283 case ZExt: return ISD::ZERO_EXTEND;
2284 case SExt: return ISD::SIGN_EXTEND;
2285 case FPToUI: return ISD::FP_TO_UINT;
2286 case FPToSI: return ISD::FP_TO_SINT;
2287 case UIToFP: return ISD::UINT_TO_FP;
2288 case SIToFP: return ISD::SINT_TO_FP;
2289 case FPTrunc: return ISD::FP_ROUND;
2290 case FPExt: return ISD::FP_EXTEND;
2291 case PtrToAddr: return ISD::BITCAST;
2292 case PtrToInt: return ISD::BITCAST;
2293 case IntToPtr: return ISD::BITCAST;
2294 case BitCast: return ISD::BITCAST;
2295 case AddrSpaceCast: return ISD::ADDRSPACECAST;
2296 case ICmp: return ISD::SETCC;
2297 case FCmp: return ISD::SETCC;
2298 case PHI: return 0;
2299 case Call: return 0;
2300 case Select: return ISD::SELECT;
2301 case UserOp1: return 0;
2302 case UserOp2: return 0;
2303 case VAArg: return 0;
2304 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
2305 case InsertElement: return ISD::INSERT_VECTOR_ELT;
2306 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
2307 case ExtractValue: return ISD::MERGE_VALUES;
2308 case InsertValue: return ISD::MERGE_VALUES;
2309 case LandingPad: return 0;
2310 case Freeze: return ISD::FREEZE;
2311 }
2312
2313 llvm_unreachable("Unknown instruction type encountered!");
2314}
2315
2316int TargetLoweringBase::IntrinsicIDToISD(Intrinsic::ID ID) const {
2317 switch (ID) {
2318 case Intrinsic::acos:
2319 return ISD::FACOS;
2320 case Intrinsic::asin:
2321 return ISD::FASIN;
2322 case Intrinsic::atan:
2323 return ISD::FATAN;
2324 case Intrinsic::cos:
2325 return ISD::FCOS;
2326 case Intrinsic::cosh:
2327 return ISD::FCOSH;
2328 case Intrinsic::exp:
2329 return ISD::FEXP;
2330 case Intrinsic::exp2:
2331 return ISD::FEXP2;
2332 case Intrinsic::exp10:
2333 return ISD::FEXP10;
2334 case Intrinsic::log:
2335 return ISD::FLOG;
2336 case Intrinsic::log2:
2337 return ISD::FLOG2;
2338 case Intrinsic::log10:
2339 return ISD::FLOG10;
2340 case Intrinsic::sin:
2341 return ISD::FSIN;
2342 case Intrinsic::sinh:
2343 return ISD::FSINH;
2344 case Intrinsic::tan:
2345 return ISD::FTAN;
2346 case Intrinsic::tanh:
2347 return ISD::FTANH;
2348 default:
2349 return ISD::DELETED_NODE;
2350 }
2351}
2352
2353Value *
2354TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilderBase &IRB,
2355 bool UseTLS) const {
2356 // compiler-rt provides a variable with a magic name. Targets that do not
2357 // link with compiler-rt may also provide such a variable.
2358 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2359
2360 RTLIB::LibcallImpl UnsafeStackPtrImpl =
2361 Libcalls.getLibcallImpl(Call: RTLIB::SAFESTACK_UNSAFE_STACK_PTR);
2362 if (UnsafeStackPtrImpl == RTLIB::Unsupported)
2363 return nullptr;
2364
2365 StringRef UnsafeStackPtrVar =
2366 RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: UnsafeStackPtrImpl);
2367 auto UnsafeStackPtr =
2368 dyn_cast_or_null<GlobalVariable>(Val: M->getNamedValue(Name: UnsafeStackPtrVar));
2369
2370 const DataLayout &DL = M->getDataLayout();
2371 PointerType *StackPtrTy = DL.getAllocaPtrType(Ctx&: M->getContext());
2372
2373 if (!UnsafeStackPtr) {
2374 auto TLSModel = UseTLS ?
2375 GlobalValue::InitialExecTLSModel :
2376 GlobalValue::NotThreadLocal;
2377 // The global variable is not defined yet, define it ourselves.
2378 // We use the initial-exec TLS model because we do not support the
2379 // variable living anywhere other than in the main executable.
2380 UnsafeStackPtr = new GlobalVariable(
2381 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
2382 UnsafeStackPtrVar, nullptr, TLSModel);
2383 } else {
2384 // The variable exists, check its type and attributes.
2385 //
2386 // FIXME: Move to IR verifier.
2387 if (UnsafeStackPtr->getValueType() != StackPtrTy)
2388 report_fatal_error(reason: Twine(UnsafeStackPtrVar) + " must have void* type");
2389 if (UseTLS != UnsafeStackPtr->isThreadLocal())
2390 report_fatal_error(reason: Twine(UnsafeStackPtrVar) + " must " +
2391 (UseTLS ? "" : "not ") + "be thread-local");
2392 }
2393 return UnsafeStackPtr;
2394}
2395
2396Value *TargetLoweringBase::getSafeStackPointerLocation(
2397 IRBuilderBase &IRB, const LibcallLoweringInfo &Libcalls) const {
2398 RTLIB::LibcallImpl SafestackPointerAddressImpl =
2399 Libcalls.getLibcallImpl(Call: RTLIB::SAFESTACK_POINTER_ADDRESS);
2400 if (SafestackPointerAddressImpl == RTLIB::Unsupported)
2401 return getDefaultSafeStackPointerLocation(IRB, UseTLS: true);
2402
2403 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2404 auto *PtrTy = PointerType::getUnqual(C&: M->getContext());
2405
2406 // Android provides a libc function to retrieve the address of the current
2407 // thread's unsafe stack pointer.
2408 FunctionCallee Fn =
2409 M->getOrInsertFunction(Name: RTLIB::RuntimeLibcallsInfo::getLibcallImplName(
2410 CallImpl: SafestackPointerAddressImpl),
2411 RetTy: PtrTy);
2412 return IRB.CreateCall(Callee: Fn);
2413}
2414
2415//===----------------------------------------------------------------------===//
2416// Loop Strength Reduction hooks
2417//===----------------------------------------------------------------------===//
2418
2419/// isLegalAddressingMode - Return true if the addressing mode represented
2420/// by AM is legal for this target, for a load/store of the specified type.
2421bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
2422 const AddrMode &AM, Type *Ty,
2423 unsigned AS, Instruction *I) const {
2424 // The default implementation of this implements a conservative RISCy, r+r and
2425 // r+i addr mode.
2426
2427 // Scalable offsets not supported
2428 if (AM.ScalableOffset)
2429 return false;
2430
2431 // Allows a sign-extended 16-bit immediate field.
2432 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2433 return false;
2434
2435 // No global is ever allowed as a base.
2436 if (AM.BaseGV)
2437 return false;
2438
2439 // Only support r+r,
2440 switch (AM.Scale) {
2441 case 0: // "r+i" or just "i", depending on HasBaseReg.
2442 break;
2443 case 1:
2444 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2445 return false;
2446 // Otherwise we have r+r or r+i.
2447 break;
2448 case 2:
2449 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2450 return false;
2451 // Allow 2*r as r+r.
2452 break;
2453 default: // Don't allow n * r
2454 return false;
2455 }
2456
2457 return true;
2458}
2459
2460//===----------------------------------------------------------------------===//
2461// Stack Protector
2462//===----------------------------------------------------------------------===//
2463
2464// For OpenBSD return its special guard variable. Otherwise return nullptr,
2465// so that SelectionDAG handle SSP.
2466Value *
2467TargetLoweringBase::getIRStackGuard(IRBuilderBase &IRB,
2468 const LibcallLoweringInfo &Libcalls) const {
2469 RTLIB::LibcallImpl GuardLocalImpl =
2470 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2471 if (GuardLocalImpl != RTLIB::impl___guard_local)
2472 return nullptr;
2473
2474 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
2475 const DataLayout &DL = M.getDataLayout();
2476 PointerType *PtrTy =
2477 PointerType::get(C&: M.getContext(), AddressSpace: DL.getDefaultGlobalsAddressSpace());
2478 GlobalVariable *G =
2479 M.getOrInsertGlobal(Name: getLibcallImplName(Call: GuardLocalImpl), Ty: PtrTy);
2480 G->setVisibility(GlobalValue::HiddenVisibility);
2481 return G;
2482}
2483
2484// Currently only support "standard" __stack_chk_guard.
2485// TODO: add LOAD_STACK_GUARD support.
2486void TargetLoweringBase::insertSSPDeclarations(
2487 Module &M, const LibcallLoweringInfo &Libcalls) const {
2488 RTLIB::LibcallImpl StackGuardImpl =
2489 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2490 if (StackGuardImpl == RTLIB::Unsupported)
2491 return;
2492
2493 StringRef StackGuardVarName = getLibcallImplName(Call: StackGuardImpl);
2494 M.getOrInsertGlobal(
2495 Name: StackGuardVarName, Ty: PointerType::getUnqual(C&: M.getContext()), CreateGlobalCallback: [=, &M]() {
2496 auto *GV = new GlobalVariable(M, PointerType::getUnqual(C&: M.getContext()),
2497 false, GlobalVariable::ExternalLinkage,
2498 nullptr, StackGuardVarName);
2499
2500 // FreeBSD has "__stack_chk_guard" defined externally on libc.so
2501 if (M.getDirectAccessExternalData() &&
2502 !TM.getTargetTriple().isOSCygMing() &&
2503 !(TM.getTargetTriple().isPPC64() &&
2504 TM.getTargetTriple().isOSFreeBSD()) &&
2505 (!TM.getTargetTriple().isOSDarwin() ||
2506 TM.getRelocationModel() == Reloc::Static))
2507 GV->setDSOLocal(true);
2508
2509 return GV;
2510 });
2511}
2512
2513// Currently only support "standard" __stack_chk_guard.
2514// TODO: add LOAD_STACK_GUARD support.
2515Value *TargetLoweringBase::getSDagStackGuard(
2516 const Module &M, const LibcallLoweringInfo &Libcalls) const {
2517 RTLIB::LibcallImpl GuardVarImpl =
2518 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2519 if (GuardVarImpl == RTLIB::Unsupported)
2520 return nullptr;
2521 return M.getNamedValue(Name: getLibcallImplName(Call: GuardVarImpl));
2522}
2523
2524Function *TargetLoweringBase::getSSPStackGuardCheck(
2525 const Module &M, const LibcallLoweringInfo &Libcalls) const {
2526 // MSVC CRT has a function to validate security cookie.
2527 RTLIB::LibcallImpl SecurityCheckCookieLibcall =
2528 Libcalls.getLibcallImpl(Call: RTLIB::SECURITY_CHECK_COOKIE);
2529 if (SecurityCheckCookieLibcall != RTLIB::Unsupported)
2530 return M.getFunction(Name: getLibcallImplName(Call: SecurityCheckCookieLibcall));
2531 return nullptr;
2532}
2533
2534unsigned TargetLoweringBase::getMinimumJumpTableEntries() const {
2535 return MinimumJumpTableEntries;
2536}
2537
2538void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) {
2539 MinimumJumpTableEntries = Val;
2540}
2541
2542unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
2543 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
2544}
2545
2546unsigned TargetLoweringBase::getMaximumJumpTableSize() const {
2547 return MaximumJumpTableSize;
2548}
2549
2550void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {
2551 MaximumJumpTableSize = Val;
2552}
2553
2554bool TargetLoweringBase::isJumpTableRelative() const {
2555 return getTargetMachine().isPositionIndependent();
2556}
2557
2558unsigned TargetLoweringBase::getMinimumBitTestCmps() const {
2559 return MinimumBitTestCmps;
2560}
2561
2562void TargetLoweringBase::setMinimumBitTestCmps(unsigned Val) {
2563 MinimumBitTestCmps = Val;
2564}
2565
2566Align TargetLoweringBase::getPrefLoopAlignment(MachineLoop *ML) const {
2567 if (TM.Options.LoopAlignment)
2568 return Align(TM.Options.LoopAlignment);
2569 return PrefLoopAlignment;
2570}
2571
2572unsigned TargetLoweringBase::getMaxPermittedBytesForAlignment(
2573 MachineBasicBlock *MBB) const {
2574 return MaxBytesForAlignment;
2575}
2576
2577//===----------------------------------------------------------------------===//
2578// Reciprocal Estimates
2579//===----------------------------------------------------------------------===//
2580
2581/// Get the reciprocal estimate attribute string for a function that will
2582/// override the target defaults.
2583static StringRef getRecipEstimateForFunc(MachineFunction &MF) {
2584 const Function &F = MF.getFunction();
2585 return F.getFnAttribute(Kind: "reciprocal-estimates").getValueAsString();
2586}
2587
2588/// Construct a string for the given reciprocal operation of the given type.
2589/// This string should match the corresponding option to the front-end's
2590/// "-mrecip" flag assuming those strings have been passed through in an
2591/// attribute string. For example, "vec-divf" for a division of a vXf32.
2592static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2593 std::string Name = VT.isVector() ? "vec-" : "";
2594
2595 Name += IsSqrt ? "sqrt" : "div";
2596
2597 // TODO: Handle other float types?
2598 if (VT.getScalarType() == MVT::f64) {
2599 Name += "d";
2600 } else if (VT.getScalarType() == MVT::f16) {
2601 Name += "h";
2602 } else {
2603 assert(VT.getScalarType() == MVT::f32 &&
2604 "Unexpected FP type for reciprocal estimate");
2605 Name += "f";
2606 }
2607
2608 return Name;
2609}
2610
2611/// Return the character position and value (a single numeric character) of a
2612/// customized refinement operation in the input string if it exists. Return
2613/// false if there is no customized refinement step count.
2614static bool parseRefinementStep(StringRef In, size_t &Position,
2615 uint8_t &Value) {
2616 const char RefStepToken = ':';
2617 Position = In.find(C: RefStepToken);
2618 if (Position == StringRef::npos)
2619 return false;
2620
2621 StringRef RefStepString = In.substr(Start: Position + 1);
2622 // Allow exactly one numeric character for the additional refinement
2623 // step parameter.
2624 if (RefStepString.size() == 1) {
2625 char RefStepChar = RefStepString[0];
2626 if (isDigit(C: RefStepChar)) {
2627 Value = RefStepChar - '0';
2628 return true;
2629 }
2630 }
2631 report_fatal_error(reason: "Invalid refinement step for -recip.");
2632}
2633
2634/// For the input attribute string, return one of the ReciprocalEstimate enum
2635/// status values (enabled, disabled, or not specified) for this operation on
2636/// the specified data type.
2637static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2638 if (Override.empty())
2639 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2640
2641 SmallVector<StringRef, 4> OverrideVector;
2642 Override.split(A&: OverrideVector, Separator: ',');
2643 unsigned NumArgs = OverrideVector.size();
2644
2645 // Check if "all", "none", or "default" was specified.
2646 if (NumArgs == 1) {
2647 // Look for an optional setting of the number of refinement steps needed
2648 // for this type of reciprocal operation.
2649 size_t RefPos;
2650 uint8_t RefSteps;
2651 if (parseRefinementStep(In: Override, Position&: RefPos, Value&: RefSteps)) {
2652 // Split the string for further processing.
2653 Override = Override.substr(Start: 0, N: RefPos);
2654 }
2655
2656 // All reciprocal types are enabled.
2657 if (Override == "all")
2658 return TargetLoweringBase::ReciprocalEstimate::Enabled;
2659
2660 // All reciprocal types are disabled.
2661 if (Override == "none")
2662 return TargetLoweringBase::ReciprocalEstimate::Disabled;
2663
2664 // Target defaults for enablement are used.
2665 if (Override == "default")
2666 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2667 }
2668
2669 // The attribute string may omit the size suffix ('f'/'d').
2670 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2671 std::string VTNameNoSize = VTName;
2672 VTNameNoSize.pop_back();
2673 static const char DisabledPrefix = '!';
2674
2675 for (StringRef RecipType : OverrideVector) {
2676 size_t RefPos;
2677 uint8_t RefSteps;
2678 if (parseRefinementStep(In: RecipType, Position&: RefPos, Value&: RefSteps))
2679 RecipType = RecipType.substr(Start: 0, N: RefPos);
2680
2681 // Ignore the disablement token for string matching.
2682 bool IsDisabled = RecipType[0] == DisabledPrefix;
2683 if (IsDisabled)
2684 RecipType = RecipType.substr(Start: 1);
2685
2686 if (RecipType == VTName || RecipType == VTNameNoSize)
2687 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
2688 : TargetLoweringBase::ReciprocalEstimate::Enabled;
2689 }
2690
2691 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2692}
2693
2694/// For the input attribute string, return the customized refinement step count
2695/// for this operation on the specified data type. If the step count does not
2696/// exist, return the ReciprocalEstimate enum value for unspecified.
2697static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2698 if (Override.empty())
2699 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2700
2701 SmallVector<StringRef, 4> OverrideVector;
2702 Override.split(A&: OverrideVector, Separator: ',');
2703 unsigned NumArgs = OverrideVector.size();
2704
2705 // Check if "all", "default", or "none" was specified.
2706 if (NumArgs == 1) {
2707 // Look for an optional setting of the number of refinement steps needed
2708 // for this type of reciprocal operation.
2709 size_t RefPos;
2710 uint8_t RefSteps;
2711 if (!parseRefinementStep(In: Override, Position&: RefPos, Value&: RefSteps))
2712 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2713
2714 // Split the string for further processing.
2715 Override = Override.substr(Start: 0, N: RefPos);
2716 assert(Override != "none" &&
2717 "Disabled reciprocals, but specifed refinement steps?");
2718
2719 // If this is a general override, return the specified number of steps.
2720 if (Override == "all" || Override == "default")
2721 return RefSteps;
2722 }
2723
2724 // The attribute string may omit the size suffix ('f'/'d').
2725 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2726 std::string VTNameNoSize = VTName;
2727 VTNameNoSize.pop_back();
2728
2729 for (StringRef RecipType : OverrideVector) {
2730 size_t RefPos;
2731 uint8_t RefSteps;
2732 if (!parseRefinementStep(In: RecipType, Position&: RefPos, Value&: RefSteps))
2733 continue;
2734
2735 RecipType = RecipType.substr(Start: 0, N: RefPos);
2736 if (RecipType == VTName || RecipType == VTNameNoSize)
2737 return RefSteps;
2738 }
2739
2740 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2741}
2742
2743int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,
2744 MachineFunction &MF) const {
2745 return getOpEnabled(IsSqrt: true, VT, Override: getRecipEstimateForFunc(MF));
2746}
2747
2748int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,
2749 MachineFunction &MF) const {
2750 return getOpEnabled(IsSqrt: false, VT, Override: getRecipEstimateForFunc(MF));
2751}
2752
2753int TargetLoweringBase::getSqrtRefinementSteps(EVT VT,
2754 MachineFunction &MF) const {
2755 return getOpRefinementSteps(IsSqrt: true, VT, Override: getRecipEstimateForFunc(MF));
2756}
2757
2758int TargetLoweringBase::getDivRefinementSteps(EVT VT,
2759 MachineFunction &MF) const {
2760 return getOpRefinementSteps(IsSqrt: false, VT, Override: getRecipEstimateForFunc(MF));
2761}
2762
2763bool TargetLoweringBase::isLoadBitCastBeneficial(
2764 EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG,
2765 const MachineMemOperand &MMO) const {
2766 // Single-element vectors are scalarized, so we should generally avoid having
2767 // any memory operations on such types, as they would get scalarized too.
2768 if (LoadVT.isFixedLengthVector() && BitcastVT.isFixedLengthVector() &&
2769 BitcastVT.getVectorNumElements() == 1)
2770 return false;
2771
2772 // Don't do if we could do an indexed load on the original type, but not on
2773 // the new one.
2774 if (!LoadVT.isSimple() || !BitcastVT.isSimple())
2775 return true;
2776
2777 MVT LoadMVT = LoadVT.getSimpleVT();
2778
2779 // Don't bother doing this if it's just going to be promoted again later, as
2780 // doing so might interfere with other combines.
2781 if (getOperationAction(Op: ISD::LOAD, VT: LoadMVT) == Promote &&
2782 getTypeToPromoteTo(Op: ISD::LOAD, VT: LoadMVT) == BitcastVT.getSimpleVT())
2783 return false;
2784
2785 unsigned Fast = 0;
2786 return allowsMemoryAccess(Context&: *DAG.getContext(), DL: DAG.getDataLayout(), VT: BitcastVT,
2787 MMO, Fast: &Fast) &&
2788 Fast;
2789}
2790
2791void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
2792 MF.getRegInfo().freezeReservedRegs();
2793}
2794
2795MachineMemOperand::Flags TargetLoweringBase::getLoadMemOperandFlags(
2796 const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC,
2797 const TargetLibraryInfo *LibInfo, CodeGenOptLevel OptLevel) const {
2798 MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad;
2799 if (LI.isVolatile())
2800 Flags |= MachineMemOperand::MOVolatile;
2801
2802 if (LI.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2803 Flags |= MachineMemOperand::MONonTemporal;
2804
2805 if (LI.hasMetadata(KindID: LLVMContext::MD_invariant_load))
2806 Flags |= MachineMemOperand::MOInvariant;
2807
2808 // Dereferenceability analysis is expensive, skip at O0.
2809 if (OptLevel != CodeGenOptLevel::None &&
2810 isDereferenceableAndAlignedPointer(
2811 V: LI.getPointerOperand(), Ty: LI.getType(), Alignment: LI.getAlign(),
2812 Q: SimplifyQuery(DL, LibInfo, /*DT=*/nullptr, AC, &LI))) {
2813 Flags |= MachineMemOperand::MODereferenceable;
2814 } else if (LI.hasMetadata(KindID: LLVMContext::MD_dereferenceable)) {
2815 Flags |= MachineMemOperand::MODereferenceable;
2816 }
2817
2818 Flags |= getTargetMMOFlags(I: LI);
2819 return Flags;
2820}
2821
2822MachineMemOperand::Flags
2823TargetLoweringBase::getStoreMemOperandFlags(const StoreInst &SI,
2824 const DataLayout &DL) const {
2825 MachineMemOperand::Flags Flags = MachineMemOperand::MOStore;
2826
2827 if (SI.isVolatile())
2828 Flags |= MachineMemOperand::MOVolatile;
2829
2830 if (SI.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2831 Flags |= MachineMemOperand::MONonTemporal;
2832
2833 // FIXME: Not preserving dereferenceable
2834 Flags |= getTargetMMOFlags(I: SI);
2835 return Flags;
2836}
2837
2838MachineMemOperand::Flags
2839TargetLoweringBase::getAtomicMemOperandFlags(const Instruction &AI,
2840 const DataLayout &DL) const {
2841 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
2842
2843 if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(Val: &AI)) {
2844 if (RMW->isVolatile())
2845 Flags |= MachineMemOperand::MOVolatile;
2846 } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(Val: &AI)) {
2847 if (CmpX->isVolatile())
2848 Flags |= MachineMemOperand::MOVolatile;
2849 } else
2850 llvm_unreachable("not an atomic instruction");
2851
2852 // FIXME: Not preserving dereferenceable
2853 Flags |= getTargetMMOFlags(I: AI);
2854 return Flags;
2855}
2856
2857MachineMemOperand::Flags TargetLoweringBase::getVPIntrinsicMemOperandFlags(
2858 const VPIntrinsic &VPIntrin) const {
2859 MachineMemOperand::Flags Flags = MachineMemOperand::MONone;
2860 Intrinsic::ID IntrinID = VPIntrin.getIntrinsicID();
2861
2862 switch (IntrinID) {
2863 default:
2864 llvm_unreachable("unexpected intrinsic. Existing code may be appropriate "
2865 "for it, but support must be explicitly enabled");
2866 case Intrinsic::vp_load:
2867 case Intrinsic::vp_gather:
2868 case Intrinsic::experimental_vp_strided_load:
2869 Flags = MachineMemOperand::MOLoad;
2870 break;
2871 case Intrinsic::vp_store:
2872 case Intrinsic::vp_scatter:
2873 case Intrinsic::experimental_vp_strided_store:
2874 Flags = MachineMemOperand::MOStore;
2875 break;
2876 }
2877
2878 if (VPIntrin.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2879 Flags |= MachineMemOperand::MONonTemporal;
2880
2881 Flags |= getTargetMMOFlags(I: VPIntrin);
2882 return Flags;
2883}
2884
2885Instruction *TargetLoweringBase::emitLeadingFence(IRBuilderBase &Builder,
2886 Instruction *Inst,
2887 AtomicOrdering Ord) const {
2888 if (isReleaseOrStronger(AO: Ord) && Inst->hasAtomicStore())
2889 return Builder.CreateFence(Ordering: Ord);
2890 else
2891 return nullptr;
2892}
2893
2894Instruction *TargetLoweringBase::emitTrailingFence(IRBuilderBase &Builder,
2895 Instruction *Inst,
2896 AtomicOrdering Ord) const {
2897 if (isAcquireOrStronger(AO: Ord))
2898 return Builder.CreateFence(Ordering: Ord);
2899 else
2900 return nullptr;
2901}
2902
2903//===----------------------------------------------------------------------===//
2904// GlobalISel Hooks
2905//===----------------------------------------------------------------------===//
2906
2907bool TargetLoweringBase::shouldLocalize(const MachineInstr &MI,
2908 const TargetTransformInfo *TTI) const {
2909 auto &MF = *MI.getMF();
2910 auto &MRI = MF.getRegInfo();
2911 // Assuming a spill and reload of a value has a cost of 1 instruction each,
2912 // this helper function computes the maximum number of uses we should consider
2913 // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2914 // break even in terms of code size when the original MI has 2 users vs
2915 // choosing to potentially spill. Any more than 2 users we we have a net code
2916 // size increase. This doesn't take into account register pressure though.
2917 auto maxUses = [](unsigned RematCost) {
2918 // A cost of 1 means remats are basically free.
2919 if (RematCost == 1)
2920 return std::numeric_limits<unsigned>::max();
2921 if (RematCost == 2)
2922 return 2U;
2923
2924 // Remat is too expensive, only sink if there's one user.
2925 if (RematCost > 2)
2926 return 1U;
2927 llvm_unreachable("Unexpected remat cost");
2928 };
2929
2930 switch (MI.getOpcode()) {
2931 default:
2932 return false;
2933 // Constants-like instructions should be close to their users.
2934 // We don't want long live-ranges for them.
2935 case TargetOpcode::G_CONSTANT:
2936 case TargetOpcode::G_FCONSTANT:
2937 case TargetOpcode::G_FRAME_INDEX:
2938 case TargetOpcode::G_INTTOPTR:
2939 return true;
2940 case TargetOpcode::G_GLOBAL_VALUE: {
2941 unsigned RematCost = TTI->getGISelRematGlobalCost();
2942 Register Reg = MI.getOperand(i: 0).getReg();
2943 unsigned MaxUses = maxUses(RematCost);
2944 if (MaxUses == UINT_MAX)
2945 return true; // Remats are "free" so always localize.
2946 return MRI.hasAtMostUserInstrs(Reg, MaxUsers: MaxUses);
2947 }
2948 }
2949}
2950