1//===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the TargetLoweringBase class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/ADT/BitVector.h"
14#include "llvm/ADT/DenseMap.h"
15#include "llvm/ADT/STLExtras.h"
16#include "llvm/ADT/SmallVector.h"
17#include "llvm/ADT/StringExtras.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/ADT/Twine.h"
20#include "llvm/Analysis/Loads.h"
21#include "llvm/Analysis/TargetTransformInfo.h"
22#include "llvm/CodeGen/Analysis.h"
23#include "llvm/CodeGen/ISDOpcodes.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstr.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineMemOperand.h"
30#include "llvm/CodeGen/MachineOperand.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/RuntimeLibcallUtil.h"
33#include "llvm/CodeGen/StackMaps.h"
34#include "llvm/CodeGen/TargetLowering.h"
35#include "llvm/CodeGen/TargetOpcodes.h"
36#include "llvm/CodeGen/TargetRegisterInfo.h"
37#include "llvm/CodeGen/ValueTypes.h"
38#include "llvm/CodeGenTypes/MachineValueType.h"
39#include "llvm/IR/Attributes.h"
40#include "llvm/IR/CallingConv.h"
41#include "llvm/IR/DataLayout.h"
42#include "llvm/IR/DerivedTypes.h"
43#include "llvm/IR/Function.h"
44#include "llvm/IR/GlobalValue.h"
45#include "llvm/IR/GlobalVariable.h"
46#include "llvm/IR/IRBuilder.h"
47#include "llvm/IR/Module.h"
48#include "llvm/IR/Type.h"
49#include "llvm/Support/Casting.h"
50#include "llvm/Support/CommandLine.h"
51#include "llvm/Support/Compiler.h"
52#include "llvm/Support/ErrorHandling.h"
53#include "llvm/Support/MathExtras.h"
54#include "llvm/Target/TargetMachine.h"
55#include "llvm/Target/TargetOptions.h"
56#include "llvm/TargetParser/Triple.h"
57#include "llvm/Transforms/Utils/SizeOpts.h"
58#include <algorithm>
59#include <cassert>
60#include <cstdint>
61#include <cstring>
62#include <string>
63#include <tuple>
64#include <utility>
65
66using namespace llvm;
67
68static cl::opt<bool> JumpIsExpensiveOverride(
69 "jump-is-expensive", cl::init(Val: false),
70 cl::desc("Do not create extra branches to split comparison logic."),
71 cl::Hidden);
72
73static cl::opt<unsigned> MinimumJumpTableEntries
74 ("min-jump-table-entries", cl::init(Val: 4), cl::Hidden,
75 cl::desc("Set minimum number of entries to use a jump table."));
76
77static cl::opt<unsigned> MaximumJumpTableSize
78 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
79 cl::desc("Set maximum size of jump tables."));
80
81/// Minimum jump table density for normal functions.
82static cl::opt<unsigned>
83 JumpTableDensity("jump-table-density", cl::init(Val: 10), cl::Hidden,
84 cl::desc("Minimum density for building a jump table in "
85 "a normal function"));
86
87/// Minimum jump table density for -Os or -Oz functions.
88static cl::opt<unsigned> OptsizeJumpTableDensity(
89 "optsize-jump-table-density", cl::init(Val: 40), cl::Hidden,
90 cl::desc("Minimum density for building a jump table in "
91 "an optsize function"));
92
93static cl::opt<unsigned> MinimumBitTestCmpsOverride(
94 "min-bit-test-cmps", cl::init(Val: 2), cl::Hidden,
95 cl::desc("Set minimum of largest number of comparisons "
96 "to use bit test for switch."));
97
98static cl::opt<unsigned> MaxStoresPerMemsetOverride(
99 "max-store-memset", cl::init(Val: 0), cl::Hidden,
100 cl::desc("Override target's MaxStoresPerMemset and "
101 "MaxStoresPerMemsetOptSize. "
102 "Set to 0 to use the target default."));
103
104static cl::opt<unsigned> MaxStoresPerMemcpyOverride(
105 "max-store-memcpy", cl::init(Val: 0), cl::Hidden,
106 cl::desc("Override target's MaxStoresPerMemcpy and "
107 "MaxStoresPerMemcpyOptSize. "
108 "Set to 0 to use the target default."));
109
110static cl::opt<unsigned> MaxStoresPerMemmoveOverride(
111 "max-store-memmove", cl::init(Val: 0), cl::Hidden,
112 cl::desc("Override target's MaxStoresPerMemmove and "
113 "MaxStoresPerMemmoveOptSize. "
114 "Set to 0 to use the target default."));
115
116// FIXME: This option is only to test if the strict fp operation processed
117// correctly by preventing mutating strict fp operation to normal fp operation
118// during development. When the backend supports strict float operation, this
119// option will be meaningless.
120static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
121 cl::desc("Don't mutate strict-float node to a legalize node"),
122 cl::init(Val: false), cl::Hidden);
123
124LLVM_ABI RTLIB::Libcall RTLIB::getSHL(EVT VT) {
125 if (VT == MVT::i16)
126 return RTLIB::SHL_I16;
127 if (VT == MVT::i32)
128 return RTLIB::SHL_I32;
129 if (VT == MVT::i64)
130 return RTLIB::SHL_I64;
131 if (VT == MVT::i128)
132 return RTLIB::SHL_I128;
133
134 return RTLIB::UNKNOWN_LIBCALL;
135}
136
137LLVM_ABI RTLIB::Libcall RTLIB::getSRL(EVT VT) {
138 if (VT == MVT::i16)
139 return RTLIB::SRL_I16;
140 if (VT == MVT::i32)
141 return RTLIB::SRL_I32;
142 if (VT == MVT::i64)
143 return RTLIB::SRL_I64;
144 if (VT == MVT::i128)
145 return RTLIB::SRL_I128;
146
147 return RTLIB::UNKNOWN_LIBCALL;
148}
149
150LLVM_ABI RTLIB::Libcall RTLIB::getSRA(EVT VT) {
151 if (VT == MVT::i16)
152 return RTLIB::SRA_I16;
153 if (VT == MVT::i32)
154 return RTLIB::SRA_I32;
155 if (VT == MVT::i64)
156 return RTLIB::SRA_I64;
157 if (VT == MVT::i128)
158 return RTLIB::SRA_I128;
159
160 return RTLIB::UNKNOWN_LIBCALL;
161}
162
163LLVM_ABI RTLIB::Libcall RTLIB::getMUL(EVT VT) {
164 if (VT == MVT::i16)
165 return RTLIB::MUL_I16;
166 if (VT == MVT::i32)
167 return RTLIB::MUL_I32;
168 if (VT == MVT::i64)
169 return RTLIB::MUL_I64;
170 if (VT == MVT::i128)
171 return RTLIB::MUL_I128;
172 return RTLIB::UNKNOWN_LIBCALL;
173}
174
175LLVM_ABI RTLIB::Libcall RTLIB::getMULO(EVT VT) {
176 if (VT == MVT::i32)
177 return RTLIB::MULO_I32;
178 if (VT == MVT::i64)
179 return RTLIB::MULO_I64;
180 if (VT == MVT::i128)
181 return RTLIB::MULO_I128;
182 return RTLIB::UNKNOWN_LIBCALL;
183}
184
185LLVM_ABI RTLIB::Libcall RTLIB::getSDIV(EVT VT) {
186 if (VT == MVT::i16)
187 return RTLIB::SDIV_I16;
188 if (VT == MVT::i32)
189 return RTLIB::SDIV_I32;
190 if (VT == MVT::i64)
191 return RTLIB::SDIV_I64;
192 if (VT == MVT::i128)
193 return RTLIB::SDIV_I128;
194 return RTLIB::UNKNOWN_LIBCALL;
195}
196
197LLVM_ABI RTLIB::Libcall RTLIB::getUDIV(EVT VT) {
198 if (VT == MVT::i16)
199 return RTLIB::UDIV_I16;
200 if (VT == MVT::i32)
201 return RTLIB::UDIV_I32;
202 if (VT == MVT::i64)
203 return RTLIB::UDIV_I64;
204 if (VT == MVT::i128)
205 return RTLIB::UDIV_I128;
206 return RTLIB::UNKNOWN_LIBCALL;
207}
208
209LLVM_ABI RTLIB::Libcall RTLIB::getSREM(EVT VT) {
210 if (VT == MVT::i16)
211 return RTLIB::SREM_I16;
212 if (VT == MVT::i32)
213 return RTLIB::SREM_I32;
214 if (VT == MVT::i64)
215 return RTLIB::SREM_I64;
216 if (VT == MVT::i128)
217 return RTLIB::SREM_I128;
218 return RTLIB::UNKNOWN_LIBCALL;
219}
220
221LLVM_ABI RTLIB::Libcall RTLIB::getUREM(EVT VT) {
222 if (VT == MVT::i16)
223 return RTLIB::UREM_I16;
224 if (VT == MVT::i32)
225 return RTLIB::UREM_I32;
226 if (VT == MVT::i64)
227 return RTLIB::UREM_I64;
228 if (VT == MVT::i128)
229 return RTLIB::UREM_I128;
230 return RTLIB::UNKNOWN_LIBCALL;
231}
232
233LLVM_ABI RTLIB::Libcall RTLIB::getCTPOP(EVT VT) {
234 if (VT == MVT::i32)
235 return RTLIB::CTPOP_I32;
236 if (VT == MVT::i64)
237 return RTLIB::CTPOP_I64;
238 if (VT == MVT::i128)
239 return RTLIB::CTPOP_I128;
240 return RTLIB::UNKNOWN_LIBCALL;
241}
242
243/// GetFPLibCall - Helper to return the right libcall for the given floating
244/// point type, or UNKNOWN_LIBCALL if there is none.
245RTLIB::Libcall RTLIB::getFPLibCall(EVT VT,
246 RTLIB::Libcall Call_F32,
247 RTLIB::Libcall Call_F64,
248 RTLIB::Libcall Call_F80,
249 RTLIB::Libcall Call_F128,
250 RTLIB::Libcall Call_PPCF128) {
251 return
252 VT == MVT::f32 ? Call_F32 :
253 VT == MVT::f64 ? Call_F64 :
254 VT == MVT::f80 ? Call_F80 :
255 VT == MVT::f128 ? Call_F128 :
256 VT == MVT::ppcf128 ? Call_PPCF128 :
257 RTLIB::UNKNOWN_LIBCALL;
258}
259
260/// getFPEXT - Return the FPEXT_*_* value for the given types, or
261/// UNKNOWN_LIBCALL if there is none.
262RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
263 if (OpVT == MVT::f16) {
264 if (RetVT == MVT::f32)
265 return FPEXT_F16_F32;
266 if (RetVT == MVT::f64)
267 return FPEXT_F16_F64;
268 if (RetVT == MVT::f80)
269 return FPEXT_F16_F80;
270 if (RetVT == MVT::f128)
271 return FPEXT_F16_F128;
272 } else if (OpVT == MVT::f32) {
273 if (RetVT == MVT::f64)
274 return FPEXT_F32_F64;
275 if (RetVT == MVT::f128)
276 return FPEXT_F32_F128;
277 if (RetVT == MVT::ppcf128)
278 return FPEXT_F32_PPCF128;
279 } else if (OpVT == MVT::f64) {
280 if (RetVT == MVT::f128)
281 return FPEXT_F64_F128;
282 else if (RetVT == MVT::ppcf128)
283 return FPEXT_F64_PPCF128;
284 } else if (OpVT == MVT::f80) {
285 if (RetVT == MVT::f128)
286 return FPEXT_F80_F128;
287 } else if (OpVT == MVT::bf16) {
288 if (RetVT == MVT::f32)
289 return FPEXT_BF16_F32;
290 }
291
292 return UNKNOWN_LIBCALL;
293}
294
295/// getFPROUND - Return the FPROUND_*_* value for the given types, or
296/// UNKNOWN_LIBCALL if there is none.
297RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
298 if (RetVT == MVT::f16) {
299 if (OpVT == MVT::f32)
300 return FPROUND_F32_F16;
301 if (OpVT == MVT::f64)
302 return FPROUND_F64_F16;
303 if (OpVT == MVT::f80)
304 return FPROUND_F80_F16;
305 if (OpVT == MVT::f128)
306 return FPROUND_F128_F16;
307 if (OpVT == MVT::ppcf128)
308 return FPROUND_PPCF128_F16;
309 } else if (RetVT == MVT::bf16) {
310 if (OpVT == MVT::f32)
311 return FPROUND_F32_BF16;
312 if (OpVT == MVT::f64)
313 return FPROUND_F64_BF16;
314 if (OpVT == MVT::f80)
315 return FPROUND_F80_BF16;
316 if (OpVT == MVT::f128)
317 return FPROUND_F128_BF16;
318 } else if (RetVT == MVT::f32) {
319 if (OpVT == MVT::f64)
320 return FPROUND_F64_F32;
321 if (OpVT == MVT::f80)
322 return FPROUND_F80_F32;
323 if (OpVT == MVT::f128)
324 return FPROUND_F128_F32;
325 if (OpVT == MVT::ppcf128)
326 return FPROUND_PPCF128_F32;
327 } else if (RetVT == MVT::f64) {
328 if (OpVT == MVT::f80)
329 return FPROUND_F80_F64;
330 if (OpVT == MVT::f128)
331 return FPROUND_F128_F64;
332 if (OpVT == MVT::ppcf128)
333 return FPROUND_PPCF128_F64;
334 } else if (RetVT == MVT::f80) {
335 if (OpVT == MVT::f128)
336 return FPROUND_F128_F80;
337 }
338
339 return UNKNOWN_LIBCALL;
340}
341
342/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
343/// UNKNOWN_LIBCALL if there is none.
344RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
345 if (OpVT == MVT::f16) {
346 if (RetVT == MVT::i32)
347 return FPTOSINT_F16_I32;
348 if (RetVT == MVT::i64)
349 return FPTOSINT_F16_I64;
350 if (RetVT == MVT::i128)
351 return FPTOSINT_F16_I128;
352 } else if (OpVT == MVT::f32) {
353 if (RetVT == MVT::i32)
354 return FPTOSINT_F32_I32;
355 if (RetVT == MVT::i64)
356 return FPTOSINT_F32_I64;
357 if (RetVT == MVT::i128)
358 return FPTOSINT_F32_I128;
359 } else if (OpVT == MVT::f64) {
360 if (RetVT == MVT::i32)
361 return FPTOSINT_F64_I32;
362 if (RetVT == MVT::i64)
363 return FPTOSINT_F64_I64;
364 if (RetVT == MVT::i128)
365 return FPTOSINT_F64_I128;
366 } else if (OpVT == MVT::f80) {
367 if (RetVT == MVT::i32)
368 return FPTOSINT_F80_I32;
369 if (RetVT == MVT::i64)
370 return FPTOSINT_F80_I64;
371 if (RetVT == MVT::i128)
372 return FPTOSINT_F80_I128;
373 } else if (OpVT == MVT::f128) {
374 if (RetVT == MVT::i32)
375 return FPTOSINT_F128_I32;
376 if (RetVT == MVT::i64)
377 return FPTOSINT_F128_I64;
378 if (RetVT == MVT::i128)
379 return FPTOSINT_F128_I128;
380 } else if (OpVT == MVT::ppcf128) {
381 if (RetVT == MVT::i32)
382 return FPTOSINT_PPCF128_I32;
383 if (RetVT == MVT::i64)
384 return FPTOSINT_PPCF128_I64;
385 if (RetVT == MVT::i128)
386 return FPTOSINT_PPCF128_I128;
387 }
388 return UNKNOWN_LIBCALL;
389}
390
391/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
392/// UNKNOWN_LIBCALL if there is none.
393RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
394 if (OpVT == MVT::f16) {
395 if (RetVT == MVT::i32)
396 return FPTOUINT_F16_I32;
397 if (RetVT == MVT::i64)
398 return FPTOUINT_F16_I64;
399 if (RetVT == MVT::i128)
400 return FPTOUINT_F16_I128;
401 } else if (OpVT == MVT::f32) {
402 if (RetVT == MVT::i32)
403 return FPTOUINT_F32_I32;
404 if (RetVT == MVT::i64)
405 return FPTOUINT_F32_I64;
406 if (RetVT == MVT::i128)
407 return FPTOUINT_F32_I128;
408 } else if (OpVT == MVT::f64) {
409 if (RetVT == MVT::i32)
410 return FPTOUINT_F64_I32;
411 if (RetVT == MVT::i64)
412 return FPTOUINT_F64_I64;
413 if (RetVT == MVT::i128)
414 return FPTOUINT_F64_I128;
415 } else if (OpVT == MVT::f80) {
416 if (RetVT == MVT::i32)
417 return FPTOUINT_F80_I32;
418 if (RetVT == MVT::i64)
419 return FPTOUINT_F80_I64;
420 if (RetVT == MVT::i128)
421 return FPTOUINT_F80_I128;
422 } else if (OpVT == MVT::f128) {
423 if (RetVT == MVT::i32)
424 return FPTOUINT_F128_I32;
425 if (RetVT == MVT::i64)
426 return FPTOUINT_F128_I64;
427 if (RetVT == MVT::i128)
428 return FPTOUINT_F128_I128;
429 } else if (OpVT == MVT::ppcf128) {
430 if (RetVT == MVT::i32)
431 return FPTOUINT_PPCF128_I32;
432 if (RetVT == MVT::i64)
433 return FPTOUINT_PPCF128_I64;
434 if (RetVT == MVT::i128)
435 return FPTOUINT_PPCF128_I128;
436 }
437 return UNKNOWN_LIBCALL;
438}
439
440/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
441/// UNKNOWN_LIBCALL if there is none.
442RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
443 if (OpVT == MVT::i32) {
444 if (RetVT == MVT::f16)
445 return SINTTOFP_I32_F16;
446 if (RetVT == MVT::f32)
447 return SINTTOFP_I32_F32;
448 if (RetVT == MVT::f64)
449 return SINTTOFP_I32_F64;
450 if (RetVT == MVT::f80)
451 return SINTTOFP_I32_F80;
452 if (RetVT == MVT::f128)
453 return SINTTOFP_I32_F128;
454 if (RetVT == MVT::ppcf128)
455 return SINTTOFP_I32_PPCF128;
456 } else if (OpVT == MVT::i64) {
457 if (RetVT == MVT::bf16)
458 return SINTTOFP_I64_BF16;
459 if (RetVT == MVT::f16)
460 return SINTTOFP_I64_F16;
461 if (RetVT == MVT::f32)
462 return SINTTOFP_I64_F32;
463 if (RetVT == MVT::f64)
464 return SINTTOFP_I64_F64;
465 if (RetVT == MVT::f80)
466 return SINTTOFP_I64_F80;
467 if (RetVT == MVT::f128)
468 return SINTTOFP_I64_F128;
469 if (RetVT == MVT::ppcf128)
470 return SINTTOFP_I64_PPCF128;
471 } else if (OpVT == MVT::i128) {
472 if (RetVT == MVT::f16)
473 return SINTTOFP_I128_F16;
474 if (RetVT == MVT::f32)
475 return SINTTOFP_I128_F32;
476 if (RetVT == MVT::f64)
477 return SINTTOFP_I128_F64;
478 if (RetVT == MVT::f80)
479 return SINTTOFP_I128_F80;
480 if (RetVT == MVT::f128)
481 return SINTTOFP_I128_F128;
482 if (RetVT == MVT::ppcf128)
483 return SINTTOFP_I128_PPCF128;
484 }
485 return UNKNOWN_LIBCALL;
486}
487
488/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
489/// UNKNOWN_LIBCALL if there is none.
490RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
491 if (OpVT == MVT::i32) {
492 if (RetVT == MVT::f16)
493 return UINTTOFP_I32_F16;
494 if (RetVT == MVT::f32)
495 return UINTTOFP_I32_F32;
496 if (RetVT == MVT::f64)
497 return UINTTOFP_I32_F64;
498 if (RetVT == MVT::f80)
499 return UINTTOFP_I32_F80;
500 if (RetVT == MVT::f128)
501 return UINTTOFP_I32_F128;
502 if (RetVT == MVT::ppcf128)
503 return UINTTOFP_I32_PPCF128;
504 } else if (OpVT == MVT::i64) {
505 if (RetVT == MVT::bf16)
506 return UINTTOFP_I64_BF16;
507 if (RetVT == MVT::f16)
508 return UINTTOFP_I64_F16;
509 if (RetVT == MVT::f32)
510 return UINTTOFP_I64_F32;
511 if (RetVT == MVT::f64)
512 return UINTTOFP_I64_F64;
513 if (RetVT == MVT::f80)
514 return UINTTOFP_I64_F80;
515 if (RetVT == MVT::f128)
516 return UINTTOFP_I64_F128;
517 if (RetVT == MVT::ppcf128)
518 return UINTTOFP_I64_PPCF128;
519 } else if (OpVT == MVT::i128) {
520 if (RetVT == MVT::f16)
521 return UINTTOFP_I128_F16;
522 if (RetVT == MVT::f32)
523 return UINTTOFP_I128_F32;
524 if (RetVT == MVT::f64)
525 return UINTTOFP_I128_F64;
526 if (RetVT == MVT::f80)
527 return UINTTOFP_I128_F80;
528 if (RetVT == MVT::f128)
529 return UINTTOFP_I128_F128;
530 if (RetVT == MVT::ppcf128)
531 return UINTTOFP_I128_PPCF128;
532 }
533 return UNKNOWN_LIBCALL;
534}
535
536RTLIB::Libcall RTLIB::getPOWI(EVT RetVT) {
537 return getFPLibCall(VT: RetVT, Call_F32: POWI_F32, Call_F64: POWI_F64, Call_F80: POWI_F80, Call_F128: POWI_F128,
538 Call_PPCF128: POWI_PPCF128);
539}
540
541RTLIB::Libcall RTLIB::getPOW(EVT RetVT) {
542 // TODO: Tablegen should generate this function
543 if (RetVT.isVector()) {
544 if (!RetVT.isSimple())
545 return RTLIB::UNKNOWN_LIBCALL;
546 switch (RetVT.getSimpleVT().SimpleTy) {
547 case MVT::v4f32:
548 return RTLIB::POW_V4F32;
549 case MVT::v2f64:
550 return RTLIB::POW_V2F64;
551 case MVT::nxv4f32:
552 return RTLIB::POW_NXV4F32;
553 case MVT::nxv2f64:
554 return RTLIB::POW_NXV2F64;
555 default:
556 return RTLIB::UNKNOWN_LIBCALL;
557 }
558 }
559
560 return getFPLibCall(VT: RetVT, Call_F32: POW_F32, Call_F64: POW_F64, Call_F80: POW_F80, Call_F128: POW_F128, Call_PPCF128: POW_PPCF128);
561}
562
563RTLIB::Libcall RTLIB::getLDEXP(EVT RetVT) {
564 return getFPLibCall(VT: RetVT, Call_F32: LDEXP_F32, Call_F64: LDEXP_F64, Call_F80: LDEXP_F80, Call_F128: LDEXP_F128,
565 Call_PPCF128: LDEXP_PPCF128);
566}
567
568RTLIB::Libcall RTLIB::getFREXP(EVT RetVT) {
569 return getFPLibCall(VT: RetVT, Call_F32: FREXP_F32, Call_F64: FREXP_F64, Call_F80: FREXP_F80, Call_F128: FREXP_F128,
570 Call_PPCF128: FREXP_PPCF128);
571}
572
573RTLIB::Libcall RTLIB::getSIN(EVT RetVT) {
574 return getFPLibCall(VT: RetVT, Call_F32: SIN_F32, Call_F64: SIN_F64, Call_F80: SIN_F80, Call_F128: SIN_F128, Call_PPCF128: SIN_PPCF128);
575}
576
577RTLIB::Libcall RTLIB::getCOS(EVT RetVT) {
578 return getFPLibCall(VT: RetVT, Call_F32: COS_F32, Call_F64: COS_F64, Call_F80: COS_F80, Call_F128: COS_F128, Call_PPCF128: COS_PPCF128);
579}
580
581RTLIB::Libcall RTLIB::getSINCOS(EVT RetVT) {
582 // TODO: Tablegen should generate this function
583 if (RetVT.isVector()) {
584 if (!RetVT.isSimple())
585 return RTLIB::UNKNOWN_LIBCALL;
586 switch (RetVT.getSimpleVT().SimpleTy) {
587 case MVT::v4f32:
588 return RTLIB::SINCOS_V4F32;
589 case MVT::v8f32:
590 return RTLIB::SINCOS_V8F32;
591 case MVT::v16f32:
592 return RTLIB::SINCOS_V16F32;
593 case MVT::v2f64:
594 return RTLIB::SINCOS_V2F64;
595 case MVT::v4f64:
596 return RTLIB::SINCOS_V4F64;
597 case MVT::v8f64:
598 return RTLIB::SINCOS_V8F64;
599 case MVT::nxv4f32:
600 return RTLIB::SINCOS_NXV4F32;
601 case MVT::nxv2f64:
602 return RTLIB::SINCOS_NXV2F64;
603 default:
604 return RTLIB::UNKNOWN_LIBCALL;
605 }
606 }
607
608 return getFPLibCall(VT: RetVT, Call_F32: SINCOS_F32, Call_F64: SINCOS_F64, Call_F80: SINCOS_F80, Call_F128: SINCOS_F128,
609 Call_PPCF128: SINCOS_PPCF128);
610}
611
612RTLIB::Libcall RTLIB::getSINCOSPI(EVT RetVT) {
613 // TODO: Tablegen should generate this function
614 if (RetVT.isVector()) {
615 if (!RetVT.isSimple())
616 return RTLIB::UNKNOWN_LIBCALL;
617 switch (RetVT.getSimpleVT().SimpleTy) {
618 case MVT::v4f32:
619 return RTLIB::SINCOSPI_V4F32;
620 case MVT::v2f64:
621 return RTLIB::SINCOSPI_V2F64;
622 case MVT::nxv4f32:
623 return RTLIB::SINCOSPI_NXV4F32;
624 case MVT::nxv2f64:
625 return RTLIB::SINCOSPI_NXV2F64;
626 default:
627 return RTLIB::UNKNOWN_LIBCALL;
628 }
629 }
630
631 return getFPLibCall(VT: RetVT, Call_F32: SINCOSPI_F32, Call_F64: SINCOSPI_F64, Call_F80: SINCOSPI_F80,
632 Call_F128: SINCOSPI_F128, Call_PPCF128: SINCOSPI_PPCF128);
633}
634
635RTLIB::Libcall RTLIB::getSINCOS_STRET(EVT RetVT) {
636 return getFPLibCall(VT: RetVT, Call_F32: SINCOS_STRET_F32, Call_F64: SINCOS_STRET_F64,
637 Call_F80: UNKNOWN_LIBCALL, Call_F128: UNKNOWN_LIBCALL, Call_PPCF128: UNKNOWN_LIBCALL);
638}
639
640RTLIB::Libcall RTLIB::getREM(EVT VT) {
641 // TODO: Tablegen should generate this function
642 if (VT.isVector()) {
643 if (!VT.isSimple())
644 return RTLIB::UNKNOWN_LIBCALL;
645 switch (VT.getSimpleVT().SimpleTy) {
646 case MVT::v4f32:
647 return RTLIB::REM_V4F32;
648 case MVT::v2f64:
649 return RTLIB::REM_V2F64;
650 case MVT::nxv4f32:
651 return RTLIB::REM_NXV4F32;
652 case MVT::nxv2f64:
653 return RTLIB::REM_NXV2F64;
654 default:
655 return RTLIB::UNKNOWN_LIBCALL;
656 }
657 }
658
659 return getFPLibCall(VT, Call_F32: REM_F32, Call_F64: REM_F64, Call_F80: REM_F80, Call_F128: REM_F128, Call_PPCF128: REM_PPCF128);
660}
661
662RTLIB::Libcall RTLIB::getCBRT(EVT VT) {
663 // TODO: Tablegen should generate this function
664 if (VT.isVector()) {
665 if (!VT.isSimple())
666 return RTLIB::UNKNOWN_LIBCALL;
667 switch (VT.getSimpleVT().SimpleTy) {
668 case MVT::v4f32:
669 return RTLIB::CBRT_V4F32;
670 case MVT::v2f64:
671 return RTLIB::CBRT_V2F64;
672 case MVT::nxv4f32:
673 return RTLIB::CBRT_NXV4F32;
674 case MVT::nxv2f64:
675 return RTLIB::CBRT_NXV2F64;
676 default:
677 return RTLIB::UNKNOWN_LIBCALL;
678 }
679 }
680
681 return getFPLibCall(VT, Call_F32: CBRT_F32, Call_F64: CBRT_F64, Call_F80: CBRT_F80, Call_F128: CBRT_F128,
682 Call_PPCF128: CBRT_PPCF128);
683}
684
685RTLIB::Libcall RTLIB::getMODF(EVT RetVT) {
686 // TODO: Tablegen should generate this function
687 if (RetVT.isVector()) {
688 if (!RetVT.isSimple())
689 return RTLIB::UNKNOWN_LIBCALL;
690 switch (RetVT.getSimpleVT().SimpleTy) {
691 case MVT::v4f32:
692 return RTLIB::MODF_V4F32;
693 case MVT::v2f64:
694 return RTLIB::MODF_V2F64;
695 case MVT::nxv4f32:
696 return RTLIB::MODF_NXV4F32;
697 case MVT::nxv2f64:
698 return RTLIB::MODF_NXV2F64;
699 default:
700 return RTLIB::UNKNOWN_LIBCALL;
701 }
702 }
703
704 return getFPLibCall(VT: RetVT, Call_F32: MODF_F32, Call_F64: MODF_F64, Call_F80: MODF_F80, Call_F128: MODF_F128,
705 Call_PPCF128: MODF_PPCF128);
706}
707
708RTLIB::Libcall RTLIB::getLROUND(EVT VT) {
709 if (VT == MVT::f32)
710 return RTLIB::LROUND_F32;
711 if (VT == MVT::f64)
712 return RTLIB::LROUND_F64;
713 if (VT == MVT::f80)
714 return RTLIB::LROUND_F80;
715 if (VT == MVT::f128)
716 return RTLIB::LROUND_F128;
717 if (VT == MVT::ppcf128)
718 return RTLIB::LROUND_PPCF128;
719
720 return RTLIB::UNKNOWN_LIBCALL;
721}
722
723RTLIB::Libcall RTLIB::getLLROUND(EVT VT) {
724 if (VT == MVT::f32)
725 return RTLIB::LLROUND_F32;
726 if (VT == MVT::f64)
727 return RTLIB::LLROUND_F64;
728 if (VT == MVT::f80)
729 return RTLIB::LLROUND_F80;
730 if (VT == MVT::f128)
731 return RTLIB::LLROUND_F128;
732 if (VT == MVT::ppcf128)
733 return RTLIB::LLROUND_PPCF128;
734
735 return RTLIB::UNKNOWN_LIBCALL;
736}
737
738RTLIB::Libcall RTLIB::getLRINT(EVT VT) {
739 if (VT == MVT::f32)
740 return RTLIB::LRINT_F32;
741 if (VT == MVT::f64)
742 return RTLIB::LRINT_F64;
743 if (VT == MVT::f80)
744 return RTLIB::LRINT_F80;
745 if (VT == MVT::f128)
746 return RTLIB::LRINT_F128;
747 if (VT == MVT::ppcf128)
748 return RTLIB::LRINT_PPCF128;
749 return RTLIB::UNKNOWN_LIBCALL;
750}
751
752RTLIB::Libcall RTLIB::getLLRINT(EVT VT) {
753 if (VT == MVT::f32)
754 return RTLIB::LLRINT_F32;
755 if (VT == MVT::f64)
756 return RTLIB::LLRINT_F64;
757 if (VT == MVT::f80)
758 return RTLIB::LLRINT_F80;
759 if (VT == MVT::f128)
760 return RTLIB::LLRINT_F128;
761 if (VT == MVT::ppcf128)
762 return RTLIB::LLRINT_PPCF128;
763 return RTLIB::UNKNOWN_LIBCALL;
764}
765
766RTLIB::Libcall RTLIB::getOutlineAtomicHelper(const Libcall (&LC)[5][4],
767 AtomicOrdering Order,
768 uint64_t MemSize) {
769 unsigned ModeN, ModelN;
770 switch (MemSize) {
771 case 1:
772 ModeN = 0;
773 break;
774 case 2:
775 ModeN = 1;
776 break;
777 case 4:
778 ModeN = 2;
779 break;
780 case 8:
781 ModeN = 3;
782 break;
783 case 16:
784 ModeN = 4;
785 break;
786 default:
787 return RTLIB::UNKNOWN_LIBCALL;
788 }
789
790 switch (Order) {
791 case AtomicOrdering::Monotonic:
792 ModelN = 0;
793 break;
794 case AtomicOrdering::Acquire:
795 ModelN = 1;
796 break;
797 case AtomicOrdering::Release:
798 ModelN = 2;
799 break;
800 case AtomicOrdering::AcquireRelease:
801 case AtomicOrdering::SequentiallyConsistent:
802 ModelN = 3;
803 break;
804 default:
805 return UNKNOWN_LIBCALL;
806 }
807
808 return LC[ModeN][ModelN];
809}
810
811RTLIB::Libcall RTLIB::getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order,
812 MVT VT) {
813 if (!VT.isScalarInteger())
814 return UNKNOWN_LIBCALL;
815 uint64_t MemSize = VT.getScalarSizeInBits() / 8;
816
817#define LCALLS(A, B) \
818 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
819#define LCALL5(A) \
820 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
821 switch (Opc) {
822 case ISD::ATOMIC_CMP_SWAP: {
823 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
824 return getOutlineAtomicHelper(LC, Order, MemSize);
825 }
826 case ISD::ATOMIC_SWAP: {
827 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};
828 return getOutlineAtomicHelper(LC, Order, MemSize);
829 }
830 case ISD::ATOMIC_LOAD_ADD: {
831 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};
832 return getOutlineAtomicHelper(LC, Order, MemSize);
833 }
834 case ISD::ATOMIC_LOAD_OR: {
835 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};
836 return getOutlineAtomicHelper(LC, Order, MemSize);
837 }
838 case ISD::ATOMIC_LOAD_CLR: {
839 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};
840 return getOutlineAtomicHelper(LC, Order, MemSize);
841 }
842 case ISD::ATOMIC_LOAD_XOR: {
843 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};
844 return getOutlineAtomicHelper(LC, Order, MemSize);
845 }
846 default:
847 return UNKNOWN_LIBCALL;
848 }
849#undef LCALLS
850#undef LCALL5
851}
852
853RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
854#define OP_TO_LIBCALL(Name, Enum) \
855 case Name: \
856 switch (VT.SimpleTy) { \
857 default: \
858 return UNKNOWN_LIBCALL; \
859 case MVT::i8: \
860 return Enum##_1; \
861 case MVT::i16: \
862 return Enum##_2; \
863 case MVT::i32: \
864 return Enum##_4; \
865 case MVT::i64: \
866 return Enum##_8; \
867 case MVT::i128: \
868 return Enum##_16; \
869 }
870
871 switch (Opc) {
872 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
873 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
874 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
875 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
876 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
877 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
878 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
879 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
880 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
881 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
882 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
883 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
884 }
885
886#undef OP_TO_LIBCALL
887
888 return UNKNOWN_LIBCALL;
889}
890
891RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
892 switch (ElementSize) {
893 case 1:
894 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
895 case 2:
896 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
897 case 4:
898 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
899 case 8:
900 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
901 case 16:
902 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
903 default:
904 return UNKNOWN_LIBCALL;
905 }
906}
907
908RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
909 switch (ElementSize) {
910 case 1:
911 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
912 case 2:
913 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
914 case 4:
915 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
916 case 8:
917 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
918 case 16:
919 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
920 default:
921 return UNKNOWN_LIBCALL;
922 }
923}
924
925RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
926 switch (ElementSize) {
927 case 1:
928 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
929 case 2:
930 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
931 case 4:
932 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
933 case 8:
934 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
935 case 16:
936 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
937 default:
938 return UNKNOWN_LIBCALL;
939 }
940}
941
942ISD::CondCode TargetLoweringBase::getSoftFloatCmpLibcallPredicate(
943 RTLIB::LibcallImpl Impl) const {
944 switch (Impl) {
945 case RTLIB::impl___aeabi_dcmpeq__une:
946 case RTLIB::impl___aeabi_fcmpeq__une:
947 // Usage in the eq case, so we have to invert the comparison.
948 return ISD::SETEQ;
949 case RTLIB::impl___aeabi_dcmpeq__oeq:
950 case RTLIB::impl___aeabi_fcmpeq__oeq:
951 // Normal comparison to boolean value.
952 return ISD::SETNE;
953 case RTLIB::impl___aeabi_dcmplt:
954 case RTLIB::impl___aeabi_dcmple:
955 case RTLIB::impl___aeabi_dcmpge:
956 case RTLIB::impl___aeabi_dcmpgt:
957 case RTLIB::impl___aeabi_dcmpun:
958 case RTLIB::impl___aeabi_fcmplt:
959 case RTLIB::impl___aeabi_fcmple:
960 case RTLIB::impl___aeabi_fcmpge:
961 case RTLIB::impl___aeabi_fcmpgt:
962 /// The AEABI versions return a typical boolean value, so we can compare
963 /// against the integer result as simply != 0.
964 return ISD::SETNE;
965 default:
966 break;
967 }
968
969 // Assume libgcc/compiler-rt behavior. Most of the cases are really aliases of
970 // each other, and return a 3-way comparison style result of -1, 0, or 1
971 // depending on lt/eq/gt.
972 //
973 // FIXME: It would be cleaner to directly express this as a 3-way comparison
974 // soft FP libcall instead of individual compares.
975 RTLIB::Libcall LC = RTLIB::RuntimeLibcallsInfo::getLibcallFromImpl(Impl);
976 switch (LC) {
977 case RTLIB::OEQ_F32:
978 case RTLIB::OEQ_F64:
979 case RTLIB::OEQ_F128:
980 case RTLIB::OEQ_PPCF128:
981 return ISD::SETEQ;
982 case RTLIB::UNE_F32:
983 case RTLIB::UNE_F64:
984 case RTLIB::UNE_F128:
985 case RTLIB::UNE_PPCF128:
986 return ISD::SETNE;
987 case RTLIB::OGE_F32:
988 case RTLIB::OGE_F64:
989 case RTLIB::OGE_F128:
990 case RTLIB::OGE_PPCF128:
991 return ISD::SETGE;
992 case RTLIB::OLT_F32:
993 case RTLIB::OLT_F64:
994 case RTLIB::OLT_F128:
995 case RTLIB::OLT_PPCF128:
996 return ISD::SETLT;
997 case RTLIB::OLE_F32:
998 case RTLIB::OLE_F64:
999 case RTLIB::OLE_F128:
1000 case RTLIB::OLE_PPCF128:
1001 return ISD::SETLE;
1002 case RTLIB::OGT_F32:
1003 case RTLIB::OGT_F64:
1004 case RTLIB::OGT_F128:
1005 case RTLIB::OGT_PPCF128:
1006 return ISD::SETGT;
1007 case RTLIB::UO_F32:
1008 case RTLIB::UO_F64:
1009 case RTLIB::UO_F128:
1010 case RTLIB::UO_PPCF128:
1011 return ISD::SETNE;
1012 default:
1013 llvm_unreachable("not a compare libcall");
1014 }
1015}
1016
1017/// NOTE: The TargetMachine owns TLOF.
1018TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
1019 const TargetSubtargetInfo &STI)
1020 : TM(tm),
1021 RuntimeLibcallInfo(TM.getTargetTriple(), TM.Options.ExceptionModel,
1022 TM.Options.FloatABIType, TM.Options.EABIVersion,
1023 TM.Options.MCOptions.getABIName(), TM.Options.VecLib),
1024 Libcalls(RuntimeLibcallInfo, STI) {
1025 initActions();
1026
1027 // Perform these initializations only once.
1028 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove =
1029 MaxLoadsPerMemcmp = 8;
1030 MaxGluedStoresPerMemcpy = 0;
1031 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize =
1032 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4;
1033 HasExtractBitsInsn = false;
1034 JumpIsExpensive = JumpIsExpensiveOverride;
1035 PredictableSelectIsExpensive = false;
1036 EnableExtLdPromotion = false;
1037 StackPointerRegisterToSaveRestore = 0;
1038 BooleanContents = UndefinedBooleanContent;
1039 BooleanFloatContents = UndefinedBooleanContent;
1040 BooleanVectorContents = UndefinedBooleanContent;
1041 SchedPreferenceInfo = Sched::ILP;
1042 GatherAllAliasesMaxDepth = 18;
1043 IsStrictFPEnabled = DisableStrictNodeMutation;
1044 MaxBytesForAlignment = 0;
1045 MaxAtomicSizeInBitsSupported = 0;
1046
1047 // Assume that even with libcalls, no target supports wider than 128 bit
1048 // division.
1049 MaxDivRemBitWidthSupported = 128;
1050
1051 MaxLargeFPConvertBitWidthSupported = 128;
1052
1053 MinCmpXchgSizeInBits = 0;
1054 SupportsUnalignedAtomics = false;
1055
1056 MinimumBitTestCmps = MinimumBitTestCmpsOverride;
1057}
1058
1059// Define the virtual destructor out-of-line to act as a key method to anchor
1060// debug info (see coding standards).
1061TargetLoweringBase::~TargetLoweringBase() = default;
1062
1063void TargetLoweringBase::initActions() {
1064 // All operations default to being supported.
1065 memset(s: OpActions, c: 0, n: sizeof(OpActions));
1066 memset(s: LoadExtActions, c: 0, n: sizeof(LoadExtActions));
1067 memset(s: AtomicLoadExtActions, c: 0, n: sizeof(AtomicLoadExtActions));
1068 memset(s: TruncStoreActions, c: 0, n: sizeof(TruncStoreActions));
1069 memset(s: IndexedModeActions, c: 0, n: sizeof(IndexedModeActions));
1070 memset(s: CondCodeActions, c: 0, n: sizeof(CondCodeActions));
1071 llvm::fill(Range&: RegClassForVT, Value: nullptr);
1072 llvm::fill(Range&: TargetDAGCombineArray, Value: 0);
1073
1074 // Let extending atomic loads be unsupported by default.
1075 for (MVT ValVT : MVT::all_valuetypes())
1076 for (MVT MemVT : MVT::all_valuetypes())
1077 setAtomicLoadExtAction(ExtTypes: {ISD::SEXTLOAD, ISD::ZEXTLOAD}, ValVT, MemVT,
1078 Action: Expand);
1079
1080 // We're somewhat special casing MVT::i2 and MVT::i4. Ideally we want to
1081 // remove this and targets should individually set these types if not legal.
1082 for (ISD::NodeType NT : enum_seq(Begin: ISD::DELETED_NODE, End: ISD::BUILTIN_OP_END,
1083 force_iteration_on_noniterable_enum)) {
1084 for (MVT VT : {MVT::i2, MVT::i4})
1085 OpActions[(unsigned)VT.SimpleTy][NT] = Expand;
1086 }
1087 for (MVT AVT : MVT::all_valuetypes()) {
1088 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {
1089 setTruncStoreAction(ValVT: AVT, MemVT: VT, Action: Expand);
1090 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: AVT, MemVT: VT, Action: Expand);
1091 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: AVT, MemVT: VT, Action: Expand);
1092 }
1093 }
1094 for (unsigned IM = (unsigned)ISD::PRE_INC;
1095 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
1096 for (MVT VT : {MVT::i2, MVT::i4}) {
1097 setIndexedLoadAction(IdxModes: IM, VT, Action: Expand);
1098 setIndexedStoreAction(IdxModes: IM, VT, Action: Expand);
1099 setIndexedMaskedLoadAction(IdxMode: IM, VT, Action: Expand);
1100 setIndexedMaskedStoreAction(IdxMode: IM, VT, Action: Expand);
1101 }
1102 }
1103
1104 for (MVT VT : MVT::fp_valuetypes()) {
1105 MVT IntVT = MVT::getIntegerVT(BitWidth: VT.getFixedSizeInBits());
1106 if (IntVT.isValid()) {
1107 setOperationAction(Op: ISD::ATOMIC_SWAP, VT, Action: Promote);
1108 AddPromotedToType(Opc: ISD::ATOMIC_SWAP, OrigVT: VT, DestVT: IntVT);
1109 }
1110 }
1111
1112 // If f16 fma is not natively supported, the value must be promoted to an f64
1113 // (and not to f32!) to prevent double rounding issues.
1114 AddPromotedToType(Opc: ISD::FMA, OrigVT: MVT::f16, DestVT: MVT::f64);
1115 AddPromotedToType(Opc: ISD::STRICT_FMA, OrigVT: MVT::f16, DestVT: MVT::f64);
1116
1117 // Set default actions for various operations.
1118 for (MVT VT : MVT::all_valuetypes()) {
1119 // Default all indexed load / store to expand.
1120 for (unsigned IM = (unsigned)ISD::PRE_INC;
1121 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
1122 setIndexedLoadAction(IdxModes: IM, VT, Action: Expand);
1123 setIndexedStoreAction(IdxModes: IM, VT, Action: Expand);
1124 setIndexedMaskedLoadAction(IdxMode: IM, VT, Action: Expand);
1125 setIndexedMaskedStoreAction(IdxMode: IM, VT, Action: Expand);
1126 }
1127
1128 // Most backends expect to see the node which just returns the value loaded.
1129 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Action: Expand);
1130
1131 // clang-format off
1132 // These operations default to expand.
1133 setOperationAction(Ops: {ISD::FGETSIGN, ISD::CONCAT_VECTORS,
1134 ISD::FMINNUM, ISD::FMAXNUM,
1135 ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
1136 ISD::FMINIMUM, ISD::FMAXIMUM,
1137 ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM,
1138 ISD::FMAD, ISD::SMIN,
1139 ISD::SMAX, ISD::UMIN,
1140 ISD::UMAX, ISD::ABS,
1141 ISD::FSHL, ISD::FSHR,
1142 ISD::SADDSAT, ISD::UADDSAT,
1143 ISD::SSUBSAT, ISD::USUBSAT,
1144 ISD::SSHLSAT, ISD::USHLSAT,
1145 ISD::SMULFIX, ISD::SMULFIXSAT,
1146 ISD::UMULFIX, ISD::UMULFIXSAT,
1147 ISD::SDIVFIX, ISD::SDIVFIXSAT,
1148 ISD::UDIVFIX, ISD::UDIVFIXSAT,
1149 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT,
1150 ISD::IS_FPCLASS, ISD::FCBRT,
1151 ISD::FLOG, ISD::FLOG2,
1152 ISD::FLOG10, ISD::FEXP,
1153 ISD::FEXP2, ISD::FEXP10,
1154 ISD::FFLOOR, ISD::FNEARBYINT,
1155 ISD::FCEIL, ISD::FRINT,
1156 ISD::FTRUNC, ISD::FROUNDEVEN,
1157 ISD::FTAN, ISD::FACOS,
1158 ISD::FASIN, ISD::FATAN,
1159 ISD::FCOSH, ISD::FSINH,
1160 ISD::FTANH, ISD::FATAN2,
1161 ISD::FMULADD, ISD::CONVERT_FROM_ARBITRARY_FP,
1162 ISD::CONVERT_TO_ARBITRARY_FP},
1163 VT, Action: Expand);
1164 // clang-format on
1165
1166 // Overflow operations default to expand
1167 setOperationAction(Ops: {ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO,
1168 ISD::SMULO, ISD::UMULO},
1169 VT, Action: Expand);
1170
1171 // Carry-using overflow operations default to expand.
1172 setOperationAction(Ops: {ISD::UADDO_CARRY, ISD::USUBO_CARRY, ISD::SETCCCARRY,
1173 ISD::SADDO_CARRY, ISD::SSUBO_CARRY},
1174 VT, Action: Expand);
1175
1176 // ADDC/ADDE/SUBC/SUBE default to expand.
1177 setOperationAction(Ops: {ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT,
1178 Action: Expand);
1179
1180 // [US]CMP default to expand
1181 setOperationAction(Ops: {ISD::UCMP, ISD::SCMP}, VT, Action: Expand);
1182
1183 // Halving adds
1184 setOperationAction(
1185 Ops: {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT,
1186 Action: Expand);
1187
1188 // Absolute difference
1189 setOperationAction(Ops: {ISD::ABDS, ISD::ABDU}, VT, Action: Expand);
1190
1191 // Carry-less multiply
1192 setOperationAction(Ops: {ISD::CLMUL, ISD::CLMULR, ISD::CLMULH}, VT, Action: Expand);
1193
1194 // Bit extract/deposit (compress/expand)
1195 setOperationAction(Ops: {ISD::PEXT, ISD::PDEP}, VT, Action: Expand);
1196
1197 // Saturated trunc
1198 setOperationAction(Op: ISD::TRUNCATE_SSAT_S, VT, Action: Expand);
1199 setOperationAction(Op: ISD::TRUNCATE_SSAT_U, VT, Action: Expand);
1200 setOperationAction(Op: ISD::TRUNCATE_USAT_U, VT, Action: Expand);
1201
1202 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
1203 setOperationAction(Ops: {ISD::CTLZ_ZERO_POISON, ISD::CTTZ_ZERO_POISON}, VT,
1204 Action: Expand);
1205
1206 // This defaults to Expand so it will be expanded to ABS by default.
1207 setOperationAction(Op: ISD::ABS_MIN_POISON, VT, Action: Expand);
1208 setOperationAction(Op: ISD::CTLS, VT, Action: Expand);
1209
1210 setOperationAction(Ops: {ISD::BITREVERSE, ISD::PARITY}, VT, Action: Expand);
1211
1212 // These library functions default to expand.
1213 setOperationAction(Ops: {ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP,
1214 ISD::FSINCOS, ISD::FSINCOSPI, ISD::FMODF},
1215 VT, Action: Expand);
1216
1217 // These operations default to expand for vector types.
1218 if (VT.isVector())
1219 setOperationAction(Ops: {ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG,
1220 ISD::ANY_EXTEND_VECTOR_INREG,
1221 ISD::SIGN_EXTEND_VECTOR_INREG,
1222 ISD::ZERO_EXTEND_VECTOR_INREG, ISD::SPLAT_VECTOR,
1223 ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
1224 VT, Action: Expand);
1225
1226 // Constrained floating-point operations default to expand.
1227#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
1228 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
1229#include "llvm/IR/ConstrainedOps.def"
1230
1231 // For most targets @llvm.get.dynamic.area.offset just returns 0.
1232 setOperationAction(Op: ISD::GET_DYNAMIC_AREA_OFFSET, VT, Action: Expand);
1233
1234 // Vector reduction default to expand.
1235 setOperationAction(
1236 Ops: {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD,
1237 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR,
1238 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN,
1239 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX,
1240 ISD::VECREDUCE_FMIN, ISD::VECREDUCE_FMAXIMUM, ISD::VECREDUCE_FMINIMUM,
1241 ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_SEQ_FMUL},
1242 VT, Action: Expand);
1243
1244 // Named vector shuffles default to expand.
1245 setOperationAction(Ops: {ISD::VECTOR_SPLICE_LEFT, ISD::VECTOR_SPLICE_RIGHT}, VT,
1246 Action: Expand);
1247
1248 // Only some target support this vector operation. Most need to expand it.
1249 setOperationAction(Op: ISD::VECTOR_COMPRESS, VT, Action: Expand);
1250
1251 // cttz.elts defaults to expand.
1252 setOperationAction(Ops: {ISD::CTTZ_ELTS, ISD::CTTZ_ELTS_ZERO_POISON}, VT,
1253 Action: Expand);
1254
1255 // VP operations default to expand.
1256#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \
1257 setOperationAction(ISD::SDOPC, VT, Expand);
1258#include "llvm/IR/VPIntrinsics.def"
1259
1260 // Masked vector extracts default to expand.
1261 setOperationAction(Op: ISD::VECTOR_FIND_LAST_ACTIVE, VT, Action: Expand);
1262
1263 setOperationAction(Op: ISD::LOOP_DEPENDENCE_RAW_MASK, VT, Action: Expand);
1264 setOperationAction(Op: ISD::LOOP_DEPENDENCE_WAR_MASK, VT, Action: Expand);
1265
1266 // FP environment operations default to expand.
1267 setOperationAction(Op: ISD::GET_FPENV, VT, Action: Expand);
1268 setOperationAction(Op: ISD::SET_FPENV, VT, Action: Expand);
1269 setOperationAction(Op: ISD::RESET_FPENV, VT, Action: Expand);
1270
1271 setOperationAction(Op: ISD::MSTORE, VT, Action: Expand);
1272
1273 setOperationAction(Op: ISD::MASKED_UDIV, VT, Action: Expand);
1274 setOperationAction(Op: ISD::MASKED_SDIV, VT, Action: Expand);
1275 setOperationAction(Op: ISD::MASKED_UREM, VT, Action: Expand);
1276 setOperationAction(Op: ISD::MASKED_SREM, VT, Action: Expand);
1277 }
1278
1279 // Most targets ignore the @llvm.prefetch intrinsic.
1280 setOperationAction(Op: ISD::PREFETCH, VT: MVT::Other, Action: Expand);
1281
1282 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
1283 setOperationAction(Op: ISD::READCYCLECOUNTER, VT: MVT::i64, Action: Expand);
1284
1285 // Most targets also ignore the @llvm.readsteadycounter intrinsic.
1286 setOperationAction(Op: ISD::READSTEADYCOUNTER, VT: MVT::i64, Action: Expand);
1287
1288 // ConstantFP nodes default to expand. Targets can either change this to
1289 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
1290 // to optimize expansions for certain constants.
1291 setOperationAction(Ops: ISD::ConstantFP,
1292 VTs: {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},
1293 Action: Expand);
1294
1295 // Insert custom handling default for llvm.canonicalize.*.
1296 setOperationAction(Ops: ISD::FCANONICALIZE,
1297 VTs: {MVT::f16, MVT::f32, MVT::f64, MVT::f128}, Action: Expand);
1298
1299 // FIXME: Query RuntimeLibCalls to make the decision.
1300 setOperationAction(Ops: {ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
1301 VTs: {MVT::f32, MVT::f64, MVT::f128}, Action: LibCall);
1302
1303 setOperationAction(Ops: {ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH,
1304 ISD::FSINH, ISD::FTANH, ISD::FATAN2},
1305 VT: MVT::f16, Action: Promote);
1306 // Default ISD::TRAP to expand (which turns it into abort).
1307 setOperationAction(Op: ISD::TRAP, VT: MVT::Other, Action: Expand);
1308
1309 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
1310 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
1311 setOperationAction(Op: ISD::DEBUGTRAP, VT: MVT::Other, Action: Expand);
1312
1313 setOperationAction(Op: ISD::UBSANTRAP, VT: MVT::Other, Action: Expand);
1314
1315 setOperationAction(Op: ISD::GET_FPENV_MEM, VT: MVT::Other, Action: Expand);
1316 setOperationAction(Op: ISD::SET_FPENV_MEM, VT: MVT::Other, Action: Expand);
1317
1318 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
1319 setOperationAction(Op: ISD::GET_FPMODE, VT, Action: Expand);
1320 setOperationAction(Op: ISD::SET_FPMODE, VT, Action: Expand);
1321 }
1322 setOperationAction(Op: ISD::RESET_FPMODE, VT: MVT::Other, Action: Expand);
1323
1324 // This one by default will call __clear_cache unless the target
1325 // wants something different.
1326 setOperationAction(Op: ISD::CLEAR_CACHE, VT: MVT::Other, Action: LibCall);
1327
1328 // By default, STACKADDRESS nodes are expanded like STACKSAVE nodes.
1329 // On SPARC targets, custom lowering is required.
1330 setOperationAction(Op: ISD::STACKADDRESS, VT: MVT::Other, Action: Expand);
1331}
1332
1333MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
1334 EVT) const {
1335 return MVT::getIntegerVT(BitWidth: DL.getPointerSizeInBits(AS: 0));
1336}
1337
1338EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,
1339 const DataLayout &DL) const {
1340 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
1341 if (LHSTy.isVector())
1342 return LHSTy;
1343 MVT ShiftVT = getScalarShiftAmountTy(DL, LHSTy);
1344 // If any possible shift value won't fit in the prefered type, just use
1345 // something safe. Assume it will be legalized when the shift is expanded.
1346 if (ShiftVT.getSizeInBits() < Log2_32_Ceil(Value: LHSTy.getSizeInBits()))
1347 ShiftVT = MVT::i32;
1348 assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) &&
1349 "ShiftVT is still too small!");
1350 return ShiftVT;
1351}
1352
1353bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
1354 assert(isTypeLegal(VT));
1355 switch (Op) {
1356 default:
1357 return false;
1358 case ISD::SDIV:
1359 case ISD::UDIV:
1360 case ISD::SREM:
1361 case ISD::UREM:
1362 return true;
1363 }
1364}
1365
1366bool TargetLoweringBase::isFreeAddrSpaceCast(unsigned SrcAS,
1367 unsigned DestAS) const {
1368 return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
1369}
1370
1371unsigned TargetLoweringBase::getBitWidthForCttzElements(
1372 EVT RetVT, ElementCount EC, bool ZeroIsPoison,
1373 const ConstantRange *VScaleRange) const {
1374 // Find the smallest "sensible" element type to use for the expansion.
1375 ConstantRange CR(APInt(64, EC.getKnownMinValue()));
1376 if (EC.isScalable())
1377 CR = CR.umul_sat(Other: *VScaleRange);
1378
1379 if (ZeroIsPoison)
1380 CR = CR.subtract(CI: APInt(64, 1));
1381
1382 unsigned EltWidth = RetVT.getScalarSizeInBits();
1383 EltWidth = std::min(a: EltWidth, b: CR.getActiveBits());
1384 EltWidth = std::max(a: llvm::bit_ceil(Value: EltWidth), b: (unsigned)8);
1385
1386 return EltWidth;
1387}
1388
1389void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
1390 // If the command-line option was specified, ignore this request.
1391 if (!JumpIsExpensiveOverride.getNumOccurrences())
1392 JumpIsExpensive = isExpensive;
1393}
1394
1395TargetLoweringBase::LegalizeKind
1396TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
1397 // If this is a simple type, use the ComputeRegisterProp mechanism.
1398 if (VT.isSimple()) {
1399 MVT SVT = VT.getSimpleVT();
1400 assert((unsigned)SVT.SimpleTy < std::size(TransformToType));
1401 MVT NVT = TransformToType[SVT.SimpleTy];
1402 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(VT: SVT);
1403
1404 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
1405 LA == TypeSoftPromoteHalf ||
1406 (NVT.isVector() ||
1407 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
1408 "Promote may not follow Expand or Promote");
1409
1410 if (LA == TypeSplitVector)
1411 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
1412 if (LA == TypeScalarizeVector)
1413 return LegalizeKind(LA, SVT.getVectorElementType());
1414 return LegalizeKind(LA, NVT);
1415 }
1416
1417 // Handle Extended Scalar Types.
1418 if (!VT.isVector()) {
1419 assert(VT.isInteger() && "Float types must be simple");
1420 unsigned BitSize = VT.getSizeInBits();
1421 // First promote to a power-of-two size, then expand if necessary.
1422 if (BitSize < 8 || !isPowerOf2_32(Value: BitSize)) {
1423 EVT NVT = VT.getRoundIntegerType(Context);
1424 assert(NVT != VT && "Unable to round integer VT");
1425 LegalizeKind NextStep = getTypeConversion(Context, VT: NVT);
1426 // Avoid multi-step promotion.
1427 if (NextStep.first == TypePromoteInteger)
1428 return NextStep;
1429 // Return rounded integer type.
1430 return LegalizeKind(TypePromoteInteger, NVT);
1431 }
1432
1433 return LegalizeKind(TypeExpandInteger,
1434 EVT::getIntegerVT(Context, BitWidth: VT.getSizeInBits() / 2));
1435 }
1436
1437 // Handle vector types.
1438 ElementCount NumElts = VT.getVectorElementCount();
1439 EVT EltVT = VT.getVectorElementType();
1440
1441 // Vectors with only one element are always scalarized.
1442 if (NumElts.isScalar())
1443 return LegalizeKind(TypeScalarizeVector, EltVT);
1444
1445 // Try to widen vector elements until the element type is a power of two and
1446 // promote it to a legal type later on, for example:
1447 // <3 x i8> -> <4 x i8> -> <4 x i32>
1448 if (EltVT.isInteger()) {
1449 // Vectors with a number of elements that is not a power of two are always
1450 // widened, for example <3 x i8> -> <4 x i8>.
1451 if (!VT.isPow2VectorType()) {
1452 NumElts = NumElts.coefficientNextPowerOf2();
1453 EVT NVT = EVT::getVectorVT(Context, VT: EltVT, EC: NumElts);
1454 return LegalizeKind(TypeWidenVector, NVT);
1455 }
1456
1457 // Examine the element type.
1458 LegalizeKind LK = getTypeConversion(Context, VT: EltVT);
1459
1460 // If type is to be expanded, split the vector.
1461 // <4 x i140> -> <2 x i140>
1462 if (LK.first == TypeExpandInteger) {
1463 if (NumElts.isScalable() && NumElts.getKnownMinValue() == 1)
1464 return LegalizeKind(TypeScalarizeScalableVector, EltVT);
1465 return LegalizeKind(TypeSplitVector,
1466 VT.getHalfNumVectorElementsVT(Context));
1467 }
1468
1469 // Promote the integer element types until a legal vector type is found
1470 // or until the element integer type is too big. If a legal type was not
1471 // found, fallback to the usual mechanism of widening/splitting the
1472 // vector.
1473 EVT OldEltVT = EltVT;
1474 while (true) {
1475 // Increase the bitwidth of the element to the next pow-of-two
1476 // (which is greater than 8 bits).
1477 EltVT = EVT::getIntegerVT(Context, BitWidth: 1 + EltVT.getSizeInBits())
1478 .getRoundIntegerType(Context);
1479
1480 // Stop trying when getting a non-simple element type.
1481 // Note that vector elements may be greater than legal vector element
1482 // types. Example: X86 XMM registers hold 64bit element on 32bit
1483 // systems.
1484 if (!EltVT.isSimple())
1485 break;
1486
1487 // Build a new vector type and check if it is legal.
1488 MVT NVT = MVT::getVectorVT(VT: EltVT.getSimpleVT(), EC: NumElts);
1489 // Found a legal promoted vector type.
1490 if (NVT != MVT() && ValueTypeActions.getTypeAction(VT: NVT) == TypeLegal)
1491 return LegalizeKind(TypePromoteInteger,
1492 EVT::getVectorVT(Context, VT: EltVT, EC: NumElts));
1493 }
1494
1495 // Reset the type to the unexpanded type if we did not find a legal vector
1496 // type with a promoted vector element type.
1497 EltVT = OldEltVT;
1498 }
1499
1500 // Try to widen the vector until a legal type is found.
1501 // If there is no wider legal type, split the vector.
1502 while (true) {
1503 // Round up to the next power of 2.
1504 NumElts = NumElts.coefficientNextPowerOf2();
1505
1506 // If there is no simple vector type with this many elements then there
1507 // cannot be a larger legal vector type. Note that this assumes that
1508 // there are no skipped intermediate vector types in the simple types.
1509 if (!EltVT.isSimple())
1510 break;
1511 MVT LargerVector = MVT::getVectorVT(VT: EltVT.getSimpleVT(), EC: NumElts);
1512 if (LargerVector == MVT())
1513 break;
1514
1515 // If this type is legal then widen the vector.
1516 if (ValueTypeActions.getTypeAction(VT: LargerVector) == TypeLegal)
1517 return LegalizeKind(TypeWidenVector, LargerVector);
1518 }
1519
1520 // Widen odd vectors to next power of two.
1521 if (!VT.isPow2VectorType()) {
1522 EVT NVT = VT.getPow2VectorType(Context);
1523 return LegalizeKind(TypeWidenVector, NVT);
1524 }
1525
1526 if (VT.getVectorElementCount() == ElementCount::getScalable(MinVal: 1))
1527 return LegalizeKind(TypeScalarizeScalableVector, EltVT);
1528
1529 // Vectors with illegal element types are expanded.
1530 EVT NVT = EVT::getVectorVT(Context, VT: EltVT,
1531 EC: VT.getVectorElementCount().divideCoefficientBy(RHS: 2));
1532 return LegalizeKind(TypeSplitVector, NVT);
1533}
1534
1535static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1536 unsigned &NumIntermediates,
1537 MVT &RegisterVT,
1538 TargetLoweringBase *TLI) {
1539 // Figure out the right, legal destination reg to copy into.
1540 ElementCount EC = VT.getVectorElementCount();
1541 MVT EltTy = VT.getVectorElementType();
1542
1543 unsigned NumVectorRegs = 1;
1544
1545 // Scalable vectors cannot be scalarized, so splitting or widening is
1546 // required.
1547 if (VT.isScalableVector() && !isPowerOf2_32(Value: EC.getKnownMinValue()))
1548 llvm_unreachable(
1549 "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1550
1551 // FIXME: We don't support non-power-of-2-sized vectors for now.
1552 // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1553 if (!isPowerOf2_32(Value: EC.getKnownMinValue())) {
1554 // Split EC to unit size (scalable property is preserved).
1555 NumVectorRegs = EC.getKnownMinValue();
1556 EC = ElementCount::getFixed(MinVal: 1);
1557 }
1558
1559 // Divide the input until we get to a supported size. This will
1560 // always end up with an EC that represent a scalar or a scalable
1561 // scalar.
1562 while (EC.getKnownMinValue() > 1 &&
1563 !TLI->isTypeLegal(VT: MVT::getVectorVT(VT: EltTy, EC))) {
1564 EC = EC.divideCoefficientBy(RHS: 2);
1565 NumVectorRegs <<= 1;
1566 }
1567
1568 NumIntermediates = NumVectorRegs;
1569
1570 MVT NewVT = MVT::getVectorVT(VT: EltTy, EC);
1571 if (!TLI->isTypeLegal(VT: NewVT))
1572 NewVT = EltTy;
1573 IntermediateVT = NewVT;
1574
1575 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
1576
1577 // Convert sizes such as i33 to i64.
1578 LaneSizeInBits = llvm::bit_ceil(Value: LaneSizeInBits);
1579
1580 MVT DestVT = TLI->getRegisterType(VT: NewVT);
1581 RegisterVT = DestVT;
1582 if (EVT(DestVT).bitsLT(VT: NewVT)) // Value is expanded, e.g. i64 -> i16.
1583 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1584
1585 // Otherwise, promotion or legal types use the same number of registers as
1586 // the vector decimated to the appropriate level.
1587 return NumVectorRegs;
1588}
1589
1590/// isLegalRC - Return true if the value types that can be represented by the
1591/// specified register class are all legal.
1592bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
1593 const TargetRegisterClass &RC) const {
1594 for (const auto *I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1595 if (isTypeLegal(VT: *I))
1596 return true;
1597 return false;
1598}
1599
1600/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1601/// sequence of memory operands that is recognized by PrologEpilogInserter.
1602MachineBasicBlock *
1603TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
1604 MachineBasicBlock *MBB) const {
1605 MachineInstr *MI = &InitialMI;
1606 MachineFunction &MF = *MI->getMF();
1607 MachineFrameInfo &MFI = MF.getFrameInfo();
1608
1609 // We're handling multiple types of operands here:
1610 // PATCHPOINT MetaArgs - live-in, read only, direct
1611 // STATEPOINT Deopt Spill - live-through, read only, indirect
1612 // STATEPOINT Deopt Alloca - live-through, read only, direct
1613 // (We're currently conservative and mark the deopt slots read/write in
1614 // practice.)
1615 // STATEPOINT GC Spill - live-through, read/write, indirect
1616 // STATEPOINT GC Alloca - live-through, read/write, direct
1617 // The live-in vs live-through is handled already (the live through ones are
1618 // all stack slots), but we need to handle the different type of stackmap
1619 // operands and memory effects here.
1620
1621 if (llvm::none_of(Range: MI->operands(),
1622 P: [](MachineOperand &Operand) { return Operand.isFI(); }))
1623 return MBB;
1624
1625 MachineInstrBuilder MIB = BuildMI(MF, MIMD: MI->getDebugLoc(), MCID: MI->getDesc());
1626
1627 // Inherit previous memory operands.
1628 MIB.cloneMemRefs(OtherMI: *MI);
1629
1630 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1631 MachineOperand &MO = MI->getOperand(i);
1632 if (!MO.isFI()) {
1633 // Index of Def operand this Use it tied to.
1634 // Since Defs are coming before Uses, if Use is tied, then
1635 // index of Def must be smaller that index of that Use.
1636 // Also, Defs preserve their position in new MI.
1637 unsigned TiedTo = i;
1638 if (MO.isReg() && MO.isTied())
1639 TiedTo = MI->findTiedOperandIdx(OpIdx: i);
1640 MIB.add(MO);
1641 if (TiedTo < i)
1642 MIB->tieOperands(DefIdx: TiedTo, UseIdx: MIB->getNumOperands() - 1);
1643 continue;
1644 }
1645
1646 // foldMemoryOperand builds a new MI after replacing a single FI operand
1647 // with the canonical set of five x86 addressing-mode operands.
1648 int FI = MO.getIndex();
1649
1650 // Add frame index operands recognized by stackmaps.cpp
1651 if (MFI.isStatepointSpillSlotObjectIndex(ObjectIdx: FI)) {
1652 // indirect-mem-ref tag, size, #FI, offset.
1653 // Used for spills inserted by StatepointLowering. This codepath is not
1654 // used for patchpoints/stackmaps at all, for these spilling is done via
1655 // foldMemoryOperand callback only.
1656 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1657 MIB.addImm(Val: StackMaps::IndirectMemRefOp);
1658 MIB.addImm(Val: MFI.getObjectSize(ObjectIdx: FI));
1659 MIB.add(MO);
1660 MIB.addImm(Val: 0);
1661 } else {
1662 // direct-mem-ref tag, #FI, offset.
1663 // Used by patchpoint, and direct alloca arguments to statepoints
1664 MIB.addImm(Val: StackMaps::DirectMemRefOp);
1665 MIB.add(MO);
1666 MIB.addImm(Val: 0);
1667 }
1668
1669 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1670
1671 // Add a new memory operand for this FI.
1672 assert(MFI.getObjectOffset(FI) != -1);
1673
1674 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1675 // PATCHPOINT should be updated to do the same. (TODO)
1676 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1677 auto Flags = MachineMemOperand::MOLoad;
1678 MachineMemOperand *MMO = MF.getMachineMemOperand(
1679 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI), F: Flags,
1680 Size: MF.getDataLayout().getPointerSize(), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
1681 MIB->addMemOperand(MF, MO: MMO);
1682 }
1683 }
1684 MBB->insert(I: MachineBasicBlock::iterator(MI), MI: MIB);
1685 MI->eraseFromParent();
1686 return MBB;
1687}
1688
1689/// findRepresentativeClass - Return the largest legal super-reg register class
1690/// of the register class for the specified type and its associated "cost".
1691// This function is in TargetLowering because it uses RegClassForVT which would
1692// need to be moved to TargetRegisterInfo and would necessitate moving
1693// isTypeLegal over as well - a massive change that would just require
1694// TargetLowering having a TargetRegisterInfo class member that it would use.
1695std::pair<const TargetRegisterClass *, uint8_t>
1696TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1697 MVT VT) const {
1698 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1699 if (!RC)
1700 return std::make_pair(x&: RC, y: 0);
1701
1702 // Compute the set of all super-register classes.
1703 BitVector SuperRegRC(TRI->getNumRegClasses());
1704 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1705 SuperRegRC.setBitsInMask(Mask: RCI.getMask());
1706
1707 // Find the first legal register class with the largest spill size.
1708 const TargetRegisterClass *BestRC = RC;
1709 for (unsigned i : SuperRegRC.set_bits()) {
1710 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1711 // We want the largest possible spill size.
1712 if (TRI->getSpillSize(RC: *SuperRC) <= TRI->getSpillSize(RC: *BestRC))
1713 continue;
1714 if (!isLegalRC(TRI: *TRI, RC: *SuperRC))
1715 continue;
1716 BestRC = SuperRC;
1717 }
1718 return std::make_pair(x&: BestRC, y: 1);
1719}
1720
1721/// computeRegisterProperties - Once all of the register classes are added,
1722/// this allows us to compute derived properties we expose.
1723void TargetLoweringBase::computeRegisterProperties(
1724 const TargetRegisterInfo *TRI) {
1725 // Everything defaults to needing one register.
1726 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1727 NumRegistersForVT[i] = 1;
1728 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1729 }
1730 // ...except isVoid, which doesn't need any registers.
1731 NumRegistersForVT[MVT::isVoid] = 0;
1732
1733 // Find the largest integer register class.
1734 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1735 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1736 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1737
1738 // Every integer value type larger than this largest register takes twice as
1739 // many registers to represent as the previous ValueType.
1740 for (unsigned ExpandedReg = LargestIntReg + 1;
1741 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1742 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1743 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1744 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1745 ValueTypeActions.setTypeAction(VT: (MVT::SimpleValueType)ExpandedReg,
1746 Action: TypeExpandInteger);
1747 }
1748
1749 // Inspect all of the ValueType's smaller than the largest integer
1750 // register to see which ones need promotion.
1751 unsigned LegalIntReg = LargestIntReg;
1752 for (unsigned IntReg = LargestIntReg - 1;
1753 IntReg >= (unsigned)MVT::i1; --IntReg) {
1754 MVT IVT = (MVT::SimpleValueType)IntReg;
1755 if (isTypeLegal(VT: IVT)) {
1756 LegalIntReg = IntReg;
1757 } else {
1758 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1759 (MVT::SimpleValueType)LegalIntReg;
1760 ValueTypeActions.setTypeAction(VT: IVT, Action: TypePromoteInteger);
1761 }
1762 }
1763
1764 // ppcf128 type is really two f64's.
1765 if (!isTypeLegal(VT: MVT::ppcf128)) {
1766 if (isTypeLegal(VT: MVT::f64)) {
1767 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1768 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1769 TransformToType[MVT::ppcf128] = MVT::f64;
1770 ValueTypeActions.setTypeAction(VT: MVT::ppcf128, Action: TypeExpandFloat);
1771 } else {
1772 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1773 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1774 TransformToType[MVT::ppcf128] = MVT::i128;
1775 ValueTypeActions.setTypeAction(VT: MVT::ppcf128, Action: TypeSoftenFloat);
1776 }
1777 }
1778
1779 // Decide how to handle f128. If the target does not have native f128 support,
1780 // expand it to i128 and we will be generating soft float library calls.
1781 if (!isTypeLegal(VT: MVT::f128)) {
1782 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1783 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1784 TransformToType[MVT::f128] = MVT::i128;
1785 ValueTypeActions.setTypeAction(VT: MVT::f128, Action: TypeSoftenFloat);
1786 }
1787
1788 // Decide how to handle f80. If the target does not have native f80 support,
1789 // expand it to i96 and we will be generating soft float library calls.
1790 if (!isTypeLegal(VT: MVT::f80)) {
1791 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];
1792 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];
1793 TransformToType[MVT::f80] = MVT::i32;
1794 ValueTypeActions.setTypeAction(VT: MVT::f80, Action: TypeSoftenFloat);
1795 }
1796
1797 // Decide how to handle f64. If the target does not have native f64 support,
1798 // expand it to i64 and we will be generating soft float library calls.
1799 if (!isTypeLegal(VT: MVT::f64)) {
1800 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1801 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1802 TransformToType[MVT::f64] = MVT::i64;
1803 ValueTypeActions.setTypeAction(VT: MVT::f64, Action: TypeSoftenFloat);
1804 }
1805
1806 // Decide how to handle f32. If the target does not have native f32 support,
1807 // expand it to i32 and we will be generating soft float library calls.
1808 if (!isTypeLegal(VT: MVT::f32)) {
1809 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1810 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1811 TransformToType[MVT::f32] = MVT::i32;
1812 ValueTypeActions.setTypeAction(VT: MVT::f32, Action: TypeSoftenFloat);
1813 }
1814
1815 // Decide how to handle f16. If the target does not have native f16 support,
1816 // promote it to f32, because there are no f16 library calls (except for
1817 // conversions).
1818 if (!isTypeLegal(VT: MVT::f16)) {
1819 // Allow targets to control how we legalize half.
1820 bool UseFPRegsForHalfType = useFPRegsForHalfType();
1821
1822 if (!UseFPRegsForHalfType) {
1823 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1824 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1825 } else {
1826 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1827 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1828 }
1829 TransformToType[MVT::f16] = MVT::f32;
1830 ValueTypeActions.setTypeAction(VT: MVT::f16, Action: TypeSoftPromoteHalf);
1831 }
1832
1833 // Decide how to handle bf16. If the target does not have native bf16 support,
1834 // promote it to f32, because there are no bf16 library calls (except for
1835 // converting from f32 to bf16).
1836 if (!isTypeLegal(VT: MVT::bf16)) {
1837 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];
1838 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];
1839 TransformToType[MVT::bf16] = MVT::f32;
1840 ValueTypeActions.setTypeAction(VT: MVT::bf16, Action: TypeSoftPromoteHalf);
1841 }
1842
1843 // Loop over all of the vector value types to see which need transformations.
1844 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1845 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1846 MVT VT = (MVT::SimpleValueType) i;
1847 if (isTypeLegal(VT))
1848 continue;
1849
1850 MVT EltVT = VT.getVectorElementType();
1851 ElementCount EC = VT.getVectorElementCount();
1852 bool IsLegalWiderType = false;
1853 bool IsScalable = VT.isScalableVector();
1854 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1855 switch (PreferredAction) {
1856 case TypePromoteInteger: {
1857 MVT::SimpleValueType EndVT = IsScalable ?
1858 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :
1859 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;
1860 // Try to promote the elements of integer vectors. If no legal
1861 // promotion was found, fall through to the widen-vector method.
1862 for (unsigned nVT = i + 1;
1863 (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1864 MVT SVT = (MVT::SimpleValueType) nVT;
1865 // Promote vectors of integers to vectors with the same number
1866 // of elements, with a wider element type.
1867 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1868 SVT.getVectorElementCount() == EC && isTypeLegal(VT: SVT)) {
1869 TransformToType[i] = SVT;
1870 RegisterTypeForVT[i] = SVT;
1871 NumRegistersForVT[i] = 1;
1872 ValueTypeActions.setTypeAction(VT, Action: TypePromoteInteger);
1873 IsLegalWiderType = true;
1874 break;
1875 }
1876 }
1877 if (IsLegalWiderType)
1878 break;
1879 [[fallthrough]];
1880 }
1881
1882 case TypeWidenVector:
1883 if (isPowerOf2_32(Value: EC.getKnownMinValue())) {
1884 // Try to widen the vector.
1885 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1886 MVT SVT = (MVT::SimpleValueType) nVT;
1887 if (SVT.getVectorElementType() == EltVT &&
1888 SVT.isScalableVector() == IsScalable &&
1889 SVT.getVectorElementCount().getKnownMinValue() >
1890 EC.getKnownMinValue() &&
1891 isTypeLegal(VT: SVT)) {
1892 TransformToType[i] = SVT;
1893 RegisterTypeForVT[i] = SVT;
1894 NumRegistersForVT[i] = 1;
1895 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1896 IsLegalWiderType = true;
1897 break;
1898 }
1899 }
1900 if (IsLegalWiderType)
1901 break;
1902 } else {
1903 // Only widen to the next power of 2 to keep consistency with EVT.
1904 MVT NVT = VT.getPow2VectorType();
1905 if (isTypeLegal(VT: NVT)) {
1906 TransformToType[i] = NVT;
1907 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1908 RegisterTypeForVT[i] = NVT;
1909 NumRegistersForVT[i] = 1;
1910 break;
1911 }
1912 }
1913 [[fallthrough]];
1914
1915 case TypeSplitVector:
1916 case TypeScalarizeVector: {
1917 MVT IntermediateVT;
1918 MVT RegisterVT;
1919 unsigned NumIntermediates;
1920 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1921 NumIntermediates, RegisterVT, TLI: this);
1922 NumRegistersForVT[i] = NumRegisters;
1923 assert(NumRegistersForVT[i] == NumRegisters &&
1924 "NumRegistersForVT size cannot represent NumRegisters!");
1925 RegisterTypeForVT[i] = RegisterVT;
1926
1927 MVT NVT = VT.getPow2VectorType();
1928 if (NVT == VT) {
1929 // Type is already a power of 2. The default action is to split.
1930 TransformToType[i] = MVT::Other;
1931 if (PreferredAction == TypeScalarizeVector)
1932 ValueTypeActions.setTypeAction(VT, Action: TypeScalarizeVector);
1933 else if (PreferredAction == TypeSplitVector)
1934 ValueTypeActions.setTypeAction(VT, Action: TypeSplitVector);
1935 else if (EC.getKnownMinValue() > 1)
1936 ValueTypeActions.setTypeAction(VT, Action: TypeSplitVector);
1937 else
1938 ValueTypeActions.setTypeAction(VT, Action: EC.isScalable()
1939 ? TypeScalarizeScalableVector
1940 : TypeScalarizeVector);
1941 } else {
1942 TransformToType[i] = NVT;
1943 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1944 }
1945 break;
1946 }
1947 default:
1948 llvm_unreachable("Unknown vector legalization action!");
1949 }
1950 }
1951
1952 // Determine the 'representative' register class for each value type.
1953 // An representative register class is the largest (meaning one which is
1954 // not a sub-register class / subreg register class) legal register class for
1955 // a group of value types. For example, on i386, i8, i16, and i32
1956 // representative would be GR32; while on x86_64 it's GR64.
1957 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1958 const TargetRegisterClass* RRC;
1959 uint8_t Cost;
1960 std::tie(args&: RRC, args&: Cost) = findRepresentativeClass(TRI, VT: (MVT::SimpleValueType)i);
1961 RepRegClassForVT[i] = RRC;
1962 RepRegClassCostForVT[i] = Cost;
1963 }
1964
1965 // Compute minimum known-legal store size.
1966 MaximumLegalStoreInBits = 0;
1967 for (MVT VT : MVT::all_valuetypes())
1968 if (VT != MVT::Other && isTypeLegal(VT) &&
1969 VT.getSizeInBits().getKnownMinValue() >= MaximumLegalStoreInBits)
1970 MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinValue();
1971}
1972
1973EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1974 EVT VT) const {
1975 assert(!VT.isVector() && "No default SetCC type for vectors!");
1976 return getPointerTy(DL).SimpleTy;
1977}
1978
1979/// getVectorTypeBreakdown - Vector types are broken down into some number of
1980/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1981/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1982/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1983///
1984/// This method returns the number of registers needed, and the VT for each
1985/// register. It also returns the VT and quantity of the intermediate values
1986/// before they are promoted/expanded.
1987unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context,
1988 EVT VT, EVT &IntermediateVT,
1989 unsigned &NumIntermediates,
1990 MVT &RegisterVT) const {
1991 ElementCount EltCnt = VT.getVectorElementCount();
1992
1993 // If there is a wider vector type with the same element type as this one,
1994 // or a promoted vector type that has the same number of elements which
1995 // are wider, then we should convert to that legal vector type.
1996 // This handles things like <2 x float> -> <4 x float> and
1997 // <4 x i1> -> <4 x i32>.
1998 LegalizeTypeAction TA = getTypeAction(Context, VT);
1999 if (!EltCnt.isScalar() &&
2000 (TA == TypeWidenVector || TA == TypePromoteInteger)) {
2001 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
2002 if (isTypeLegal(VT: RegisterEVT)) {
2003 IntermediateVT = RegisterEVT;
2004 RegisterVT = RegisterEVT.getSimpleVT();
2005 NumIntermediates = 1;
2006 return 1;
2007 }
2008 }
2009
2010 // Figure out the right, legal destination reg to copy into.
2011 EVT EltTy = VT.getVectorElementType();
2012
2013 unsigned NumVectorRegs = 1;
2014
2015 // Scalable vectors cannot be scalarized, so handle the legalisation of the
2016 // types like done elsewhere in SelectionDAG.
2017 if (EltCnt.isScalable()) {
2018 LegalizeKind LK;
2019 EVT PartVT = VT;
2020 do {
2021 // Iterate until we've found a legal (part) type to hold VT.
2022 LK = getTypeConversion(Context, VT: PartVT);
2023 PartVT = LK.second;
2024 } while (LK.first != TypeLegal);
2025
2026 if (!PartVT.isVector()) {
2027 report_fatal_error(
2028 reason: "Don't know how to legalize this scalable vector type");
2029 }
2030
2031 NumIntermediates =
2032 divideCeil(Numerator: VT.getVectorElementCount().getKnownMinValue(),
2033 Denominator: PartVT.getVectorElementCount().getKnownMinValue());
2034 IntermediateVT = PartVT;
2035 RegisterVT = getRegisterType(Context, VT: IntermediateVT);
2036 return NumIntermediates;
2037 }
2038
2039 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally
2040 // we could break down into LHS/RHS like LegalizeDAG does.
2041 if (!isPowerOf2_32(Value: EltCnt.getKnownMinValue())) {
2042 NumVectorRegs = EltCnt.getKnownMinValue();
2043 EltCnt = ElementCount::getFixed(MinVal: 1);
2044 }
2045
2046 // Divide the input until we get to a supported size. This will always
2047 // end with a scalar if the target doesn't support vectors.
2048 while (EltCnt.getKnownMinValue() > 1 &&
2049 !isTypeLegal(VT: EVT::getVectorVT(Context, VT: EltTy, EC: EltCnt))) {
2050 EltCnt = EltCnt.divideCoefficientBy(RHS: 2);
2051 NumVectorRegs <<= 1;
2052 }
2053
2054 NumIntermediates = NumVectorRegs;
2055
2056 EVT NewVT = EVT::getVectorVT(Context, VT: EltTy, EC: EltCnt);
2057 if (!isTypeLegal(VT: NewVT))
2058 NewVT = EltTy;
2059 IntermediateVT = NewVT;
2060
2061 MVT DestVT = getRegisterType(Context, VT: NewVT);
2062 RegisterVT = DestVT;
2063
2064 if (EVT(DestVT).bitsLT(VT: NewVT)) { // Value is expanded, e.g. i64 -> i16.
2065 TypeSize NewVTSize = NewVT.getSizeInBits();
2066 // Convert sizes such as i33 to i64.
2067 if (!llvm::has_single_bit<uint32_t>(Value: NewVTSize.getKnownMinValue()))
2068 NewVTSize = NewVTSize.coefficientNextPowerOf2();
2069 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
2070 }
2071
2072 // Otherwise, promotion or legal types use the same number of registers as
2073 // the vector decimated to the appropriate level.
2074 return NumVectorRegs;
2075}
2076
2077bool TargetLoweringBase::isSuitableForJumpTable(const SwitchInst *SI,
2078 uint64_t NumCases,
2079 uint64_t Range,
2080 ProfileSummaryInfo *PSI,
2081 BlockFrequencyInfo *BFI) const {
2082 // FIXME: This function check the maximum table size and density, but the
2083 // minimum size is not checked. It would be nice if the minimum size is
2084 // also combined within this function. Currently, the minimum size check is
2085 // performed in findJumpTable() in SelectionDAGBuiler and
2086 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
2087 const bool OptForSize =
2088 llvm::shouldOptimizeForSize(BB: SI->getParent(), PSI, BFI);
2089 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
2090 const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
2091
2092 // Check whether the number of cases is small enough and
2093 // the range is dense enough for a jump table.
2094 return (OptForSize || Range <= MaxJumpTableSize) &&
2095 (NumCases * 100 >= Range * MinDensity);
2096}
2097
2098MVT TargetLoweringBase::getPreferredSwitchConditionType(LLVMContext &Context,
2099 EVT ConditionVT) const {
2100 return getRegisterType(Context, VT: ConditionVT);
2101}
2102
2103/// Get the EVTs and ArgFlags collections that represent the legalized return
2104/// type of the given function. This does not require a DAG or a return value,
2105/// and is suitable for use before any DAGs for the function are constructed.
2106/// TODO: Move this out of TargetLowering.cpp.
2107void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType,
2108 AttributeList attr,
2109 SmallVectorImpl<ISD::OutputArg> &Outs,
2110 const TargetLowering &TLI, const DataLayout &DL) {
2111 SmallVector<Type *, 4> Types;
2112 ComputeValueTypes(DL, Ty: ReturnType, Types);
2113 unsigned NumValues = Types.size();
2114 if (NumValues == 0) return;
2115
2116 for (Type *Ty : Types) {
2117 EVT VT = TLI.getValueType(DL, Ty);
2118 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
2119
2120 if (attr.hasRetAttr(Kind: Attribute::SExt))
2121 ExtendKind = ISD::SIGN_EXTEND;
2122 else if (attr.hasRetAttr(Kind: Attribute::ZExt))
2123 ExtendKind = ISD::ZERO_EXTEND;
2124
2125 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
2126 VT = TLI.getTypeForExtReturn(Context&: ReturnType->getContext(), VT, ExtendKind);
2127
2128 unsigned NumParts =
2129 TLI.getNumRegistersForCallingConv(Context&: ReturnType->getContext(), CC, VT);
2130 MVT PartVT =
2131 TLI.getRegisterTypeForCallingConv(Context&: ReturnType->getContext(), CC, VT);
2132
2133 // 'inreg' on function refers to return value
2134 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
2135 if (attr.hasRetAttr(Kind: Attribute::InReg))
2136 Flags.setInReg();
2137
2138 // Propagate extension type if any
2139 if (attr.hasRetAttr(Kind: Attribute::SExt))
2140 Flags.setSExt();
2141 else if (attr.hasRetAttr(Kind: Attribute::ZExt))
2142 Flags.setZExt();
2143
2144 for (unsigned i = 0; i < NumParts; ++i)
2145 Outs.push_back(Elt: ISD::OutputArg(Flags, PartVT, VT, Ty, 0, 0));
2146 }
2147}
2148
2149Align TargetLoweringBase::getByValTypeAlignment(Type *Ty,
2150 const DataLayout &DL) const {
2151 return DL.getABITypeAlign(Ty);
2152}
2153
2154bool TargetLoweringBase::allowsMemoryAccessForAlignment(
2155 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
2156 Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const {
2157 // Check if the specified alignment is sufficient based on the data layout.
2158 // TODO: While using the data layout works in practice, a better solution
2159 // would be to implement this check directly (make this a virtual function).
2160 // For example, the ABI alignment may change based on software platform while
2161 // this function should only be affected by hardware implementation.
2162 Type *Ty = VT.getTypeForEVT(Context);
2163 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {
2164 // Assume that an access that meets the ABI-specified alignment is fast.
2165 if (Fast != nullptr)
2166 *Fast = 1;
2167 return true;
2168 }
2169
2170 // This is a misaligned access.
2171 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
2172}
2173
2174bool TargetLoweringBase::allowsMemoryAccessForAlignment(
2175 LLVMContext &Context, const DataLayout &DL, EVT VT,
2176 const MachineMemOperand &MMO, unsigned *Fast) const {
2177 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace: MMO.getAddrSpace(),
2178 Alignment: MMO.getAlign(), Flags: MMO.getFlags(), Fast);
2179}
2180
2181bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
2182 const DataLayout &DL, EVT VT,
2183 unsigned AddrSpace, Align Alignment,
2184 MachineMemOperand::Flags Flags,
2185 unsigned *Fast) const {
2186 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
2187 Flags, Fast);
2188}
2189
2190bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
2191 const DataLayout &DL, EVT VT,
2192 const MachineMemOperand &MMO,
2193 unsigned *Fast) const {
2194 return allowsMemoryAccess(Context, DL, VT, AddrSpace: MMO.getAddrSpace(), Alignment: MMO.getAlign(),
2195 Flags: MMO.getFlags(), Fast);
2196}
2197
2198bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
2199 const DataLayout &DL, LLT Ty,
2200 const MachineMemOperand &MMO,
2201 unsigned *Fast) const {
2202 EVT VT = getApproximateEVTForLLT(Ty, Ctx&: Context);
2203 return allowsMemoryAccess(Context, DL, VT, AddrSpace: MMO.getAddrSpace(), Alignment: MMO.getAlign(),
2204 Flags: MMO.getFlags(), Fast);
2205}
2206
2207unsigned TargetLoweringBase::getMaxStoresPerMemset(bool OptSize) const {
2208 if (MaxStoresPerMemsetOverride > 0)
2209 return MaxStoresPerMemsetOverride;
2210
2211 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
2212}
2213
2214unsigned TargetLoweringBase::getMaxStoresPerMemcpy(bool OptSize) const {
2215 if (MaxStoresPerMemcpyOverride > 0)
2216 return MaxStoresPerMemcpyOverride;
2217
2218 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
2219}
2220
2221unsigned TargetLoweringBase::getMaxStoresPerMemmove(bool OptSize) const {
2222 if (MaxStoresPerMemmoveOverride > 0)
2223 return MaxStoresPerMemmoveOverride;
2224
2225 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
2226}
2227
2228//===----------------------------------------------------------------------===//
2229// TargetTransformInfo Helpers
2230//===----------------------------------------------------------------------===//
2231
2232int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
2233 enum InstructionOpcodes {
2234#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
2235#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
2236#include "llvm/IR/Instruction.def"
2237 };
2238 switch (static_cast<InstructionOpcodes>(Opcode)) {
2239 case Ret: return 0;
2240 case UncondBr: return 0;
2241 case CondBr: return 0;
2242 case Switch: return 0;
2243 case IndirectBr: return 0;
2244 case Invoke: return 0;
2245 case CallBr: return 0;
2246 case Resume: return 0;
2247 case Unreachable: return 0;
2248 case CleanupRet: return 0;
2249 case CatchRet: return 0;
2250 case CatchPad: return 0;
2251 case CatchSwitch: return 0;
2252 case CleanupPad: return 0;
2253 case FNeg: return ISD::FNEG;
2254 case Add: return ISD::ADD;
2255 case FAdd: return ISD::FADD;
2256 case Sub: return ISD::SUB;
2257 case FSub: return ISD::FSUB;
2258 case Mul: return ISD::MUL;
2259 case FMul: return ISD::FMUL;
2260 case UDiv: return ISD::UDIV;
2261 case SDiv: return ISD::SDIV;
2262 case FDiv: return ISD::FDIV;
2263 case URem: return ISD::UREM;
2264 case SRem: return ISD::SREM;
2265 case FRem: return ISD::FREM;
2266 case Shl: return ISD::SHL;
2267 case LShr: return ISD::SRL;
2268 case AShr: return ISD::SRA;
2269 case And: return ISD::AND;
2270 case Or: return ISD::OR;
2271 case Xor: return ISD::XOR;
2272 case Alloca: return 0;
2273 case Load: return ISD::LOAD;
2274 case Store: return ISD::STORE;
2275 case GetElementPtr: return 0;
2276 case Fence: return 0;
2277 case AtomicCmpXchg: return 0;
2278 case AtomicRMW: return 0;
2279 case Trunc: return ISD::TRUNCATE;
2280 case ZExt: return ISD::ZERO_EXTEND;
2281 case SExt: return ISD::SIGN_EXTEND;
2282 case FPToUI: return ISD::FP_TO_UINT;
2283 case FPToSI: return ISD::FP_TO_SINT;
2284 case UIToFP: return ISD::UINT_TO_FP;
2285 case SIToFP: return ISD::SINT_TO_FP;
2286 case FPTrunc: return ISD::FP_ROUND;
2287 case FPExt: return ISD::FP_EXTEND;
2288 case PtrToAddr: return ISD::BITCAST;
2289 case PtrToInt: return ISD::BITCAST;
2290 case IntToPtr: return ISD::BITCAST;
2291 case BitCast: return ISD::BITCAST;
2292 case AddrSpaceCast: return ISD::ADDRSPACECAST;
2293 case ICmp: return ISD::SETCC;
2294 case FCmp: return ISD::SETCC;
2295 case PHI: return 0;
2296 case Call: return 0;
2297 case Select: return ISD::SELECT;
2298 case UserOp1: return 0;
2299 case UserOp2: return 0;
2300 case VAArg: return 0;
2301 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
2302 case InsertElement: return ISD::INSERT_VECTOR_ELT;
2303 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
2304 case ExtractValue: return ISD::MERGE_VALUES;
2305 case InsertValue: return ISD::MERGE_VALUES;
2306 case LandingPad: return 0;
2307 case Freeze: return ISD::FREEZE;
2308 }
2309
2310 llvm_unreachable("Unknown instruction type encountered!");
2311}
2312
2313int TargetLoweringBase::IntrinsicIDToISD(Intrinsic::ID ID) const {
2314 switch (ID) {
2315 case Intrinsic::acos:
2316 return ISD::FACOS;
2317 case Intrinsic::asin:
2318 return ISD::FASIN;
2319 case Intrinsic::atan:
2320 return ISD::FATAN;
2321 case Intrinsic::cos:
2322 return ISD::FCOS;
2323 case Intrinsic::cosh:
2324 return ISD::FCOSH;
2325 case Intrinsic::exp:
2326 return ISD::FEXP;
2327 case Intrinsic::exp2:
2328 return ISD::FEXP2;
2329 case Intrinsic::exp10:
2330 return ISD::FEXP10;
2331 case Intrinsic::log:
2332 return ISD::FLOG;
2333 case Intrinsic::log2:
2334 return ISD::FLOG2;
2335 case Intrinsic::log10:
2336 return ISD::FLOG10;
2337 case Intrinsic::sin:
2338 return ISD::FSIN;
2339 case Intrinsic::sinh:
2340 return ISD::FSINH;
2341 case Intrinsic::tan:
2342 return ISD::FTAN;
2343 case Intrinsic::tanh:
2344 return ISD::FTANH;
2345 default:
2346 return ISD::DELETED_NODE;
2347 }
2348}
2349
2350Value *
2351TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilderBase &IRB,
2352 bool UseTLS) const {
2353 // compiler-rt provides a variable with a magic name. Targets that do not
2354 // link with compiler-rt may also provide such a variable.
2355 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2356
2357 RTLIB::LibcallImpl UnsafeStackPtrImpl =
2358 Libcalls.getLibcallImpl(Call: RTLIB::SAFESTACK_UNSAFE_STACK_PTR);
2359 if (UnsafeStackPtrImpl == RTLIB::Unsupported)
2360 return nullptr;
2361
2362 StringRef UnsafeStackPtrVar =
2363 RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: UnsafeStackPtrImpl);
2364 auto UnsafeStackPtr =
2365 dyn_cast_or_null<GlobalVariable>(Val: M->getNamedValue(Name: UnsafeStackPtrVar));
2366
2367 const DataLayout &DL = M->getDataLayout();
2368 PointerType *StackPtrTy = DL.getAllocaPtrType(Ctx&: M->getContext());
2369
2370 if (!UnsafeStackPtr) {
2371 auto TLSModel = UseTLS ?
2372 GlobalValue::InitialExecTLSModel :
2373 GlobalValue::NotThreadLocal;
2374 // The global variable is not defined yet, define it ourselves.
2375 // We use the initial-exec TLS model because we do not support the
2376 // variable living anywhere other than in the main executable.
2377 UnsafeStackPtr = new GlobalVariable(
2378 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
2379 UnsafeStackPtrVar, nullptr, TLSModel);
2380 } else {
2381 // The variable exists, check its type and attributes.
2382 //
2383 // FIXME: Move to IR verifier.
2384 if (UnsafeStackPtr->getValueType() != StackPtrTy)
2385 report_fatal_error(reason: Twine(UnsafeStackPtrVar) + " must have void* type");
2386 if (UseTLS != UnsafeStackPtr->isThreadLocal())
2387 report_fatal_error(reason: Twine(UnsafeStackPtrVar) + " must " +
2388 (UseTLS ? "" : "not ") + "be thread-local");
2389 }
2390 return UnsafeStackPtr;
2391}
2392
2393Value *TargetLoweringBase::getSafeStackPointerLocation(
2394 IRBuilderBase &IRB, const LibcallLoweringInfo &Libcalls) const {
2395 RTLIB::LibcallImpl SafestackPointerAddressImpl =
2396 Libcalls.getLibcallImpl(Call: RTLIB::SAFESTACK_POINTER_ADDRESS);
2397 if (SafestackPointerAddressImpl == RTLIB::Unsupported)
2398 return getDefaultSafeStackPointerLocation(IRB, UseTLS: true);
2399
2400 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2401 auto *PtrTy = PointerType::getUnqual(C&: M->getContext());
2402
2403 // Android provides a libc function to retrieve the address of the current
2404 // thread's unsafe stack pointer.
2405 FunctionCallee Fn =
2406 M->getOrInsertFunction(Name: RTLIB::RuntimeLibcallsInfo::getLibcallImplName(
2407 CallImpl: SafestackPointerAddressImpl),
2408 RetTy: PtrTy);
2409 return IRB.CreateCall(Callee: Fn);
2410}
2411
2412//===----------------------------------------------------------------------===//
2413// Loop Strength Reduction hooks
2414//===----------------------------------------------------------------------===//
2415
2416/// isLegalAddressingMode - Return true if the addressing mode represented
2417/// by AM is legal for this target, for a load/store of the specified type.
2418bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
2419 const AddrMode &AM, Type *Ty,
2420 unsigned AS, Instruction *I) const {
2421 // The default implementation of this implements a conservative RISCy, r+r and
2422 // r+i addr mode.
2423
2424 // Scalable offsets not supported
2425 if (AM.ScalableOffset)
2426 return false;
2427
2428 // Allows a sign-extended 16-bit immediate field.
2429 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2430 return false;
2431
2432 // No global is ever allowed as a base.
2433 if (AM.BaseGV)
2434 return false;
2435
2436 // Only support r+r,
2437 switch (AM.Scale) {
2438 case 0: // "r+i" or just "i", depending on HasBaseReg.
2439 break;
2440 case 1:
2441 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2442 return false;
2443 // Otherwise we have r+r or r+i.
2444 break;
2445 case 2:
2446 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2447 return false;
2448 // Allow 2*r as r+r.
2449 break;
2450 default: // Don't allow n * r
2451 return false;
2452 }
2453
2454 return true;
2455}
2456
2457//===----------------------------------------------------------------------===//
2458// Stack Protector
2459//===----------------------------------------------------------------------===//
2460
2461// For OpenBSD return its special guard variable. Otherwise return nullptr,
2462// so that SelectionDAG handle SSP.
2463Value *
2464TargetLoweringBase::getIRStackGuard(IRBuilderBase &IRB,
2465 const LibcallLoweringInfo &Libcalls) const {
2466 RTLIB::LibcallImpl GuardLocalImpl =
2467 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2468 if (GuardLocalImpl != RTLIB::impl___guard_local)
2469 return nullptr;
2470
2471 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
2472 const DataLayout &DL = M.getDataLayout();
2473 PointerType *PtrTy =
2474 PointerType::get(C&: M.getContext(), AddressSpace: DL.getDefaultGlobalsAddressSpace());
2475 GlobalVariable *G =
2476 M.getOrInsertGlobal(Name: getLibcallImplName(Call: GuardLocalImpl), Ty: PtrTy);
2477 G->setVisibility(GlobalValue::HiddenVisibility);
2478 return G;
2479}
2480
2481// Currently only support "standard" __stack_chk_guard.
2482// TODO: add LOAD_STACK_GUARD support.
2483void TargetLoweringBase::insertSSPDeclarations(
2484 Module &M, const LibcallLoweringInfo &Libcalls) const {
2485 RTLIB::LibcallImpl StackGuardImpl =
2486 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2487 if (StackGuardImpl == RTLIB::Unsupported)
2488 return;
2489
2490 StringRef StackGuardVarName = getLibcallImplName(Call: StackGuardImpl);
2491 M.getOrInsertGlobal(
2492 Name: StackGuardVarName, Ty: PointerType::getUnqual(C&: M.getContext()), CreateGlobalCallback: [=, &M]() {
2493 auto *GV = new GlobalVariable(M, PointerType::getUnqual(C&: M.getContext()),
2494 false, GlobalVariable::ExternalLinkage,
2495 nullptr, StackGuardVarName);
2496
2497 // FreeBSD has "__stack_chk_guard" defined externally on libc.so
2498 if (M.getDirectAccessExternalData() &&
2499 !TM.getTargetTriple().isOSCygMing() &&
2500 !(TM.getTargetTriple().isPPC64() &&
2501 TM.getTargetTriple().isOSFreeBSD()) &&
2502 (!TM.getTargetTriple().isOSDarwin() ||
2503 TM.getRelocationModel() == Reloc::Static))
2504 GV->setDSOLocal(true);
2505
2506 return GV;
2507 });
2508}
2509
2510// Currently only support "standard" __stack_chk_guard.
2511// TODO: add LOAD_STACK_GUARD support.
2512Value *TargetLoweringBase::getSDagStackGuard(
2513 const Module &M, const LibcallLoweringInfo &Libcalls) const {
2514 RTLIB::LibcallImpl GuardVarImpl =
2515 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2516 if (GuardVarImpl == RTLIB::Unsupported)
2517 return nullptr;
2518 return M.getNamedValue(Name: getLibcallImplName(Call: GuardVarImpl));
2519}
2520
2521Function *TargetLoweringBase::getSSPStackGuardCheck(
2522 const Module &M, const LibcallLoweringInfo &Libcalls) const {
2523 // MSVC CRT has a function to validate security cookie.
2524 RTLIB::LibcallImpl SecurityCheckCookieLibcall =
2525 Libcalls.getLibcallImpl(Call: RTLIB::SECURITY_CHECK_COOKIE);
2526 if (SecurityCheckCookieLibcall != RTLIB::Unsupported)
2527 return M.getFunction(Name: getLibcallImplName(Call: SecurityCheckCookieLibcall));
2528 return nullptr;
2529}
2530
2531unsigned TargetLoweringBase::getMinimumJumpTableEntries() const {
2532 return MinimumJumpTableEntries;
2533}
2534
2535void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) {
2536 MinimumJumpTableEntries = Val;
2537}
2538
2539unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
2540 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
2541}
2542
2543unsigned TargetLoweringBase::getMaximumJumpTableSize() const {
2544 return MaximumJumpTableSize;
2545}
2546
2547void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {
2548 MaximumJumpTableSize = Val;
2549}
2550
2551bool TargetLoweringBase::isJumpTableRelative() const {
2552 return getTargetMachine().isPositionIndependent();
2553}
2554
2555unsigned TargetLoweringBase::getMinimumBitTestCmps() const {
2556 return MinimumBitTestCmps;
2557}
2558
2559void TargetLoweringBase::setMinimumBitTestCmps(unsigned Val) {
2560 MinimumBitTestCmps = Val;
2561}
2562
2563Align TargetLoweringBase::getPrefLoopAlignment(MachineLoop *ML) const {
2564 if (TM.Options.LoopAlignment)
2565 return Align(TM.Options.LoopAlignment);
2566 return PrefLoopAlignment;
2567}
2568
2569unsigned TargetLoweringBase::getMaxPermittedBytesForAlignment(
2570 MachineBasicBlock *MBB) const {
2571 return MaxBytesForAlignment;
2572}
2573
2574//===----------------------------------------------------------------------===//
2575// Reciprocal Estimates
2576//===----------------------------------------------------------------------===//
2577
2578/// Get the reciprocal estimate attribute string for a function that will
2579/// override the target defaults.
2580static StringRef getRecipEstimateForFunc(MachineFunction &MF) {
2581 const Function &F = MF.getFunction();
2582 return F.getFnAttribute(Kind: "reciprocal-estimates").getValueAsString();
2583}
2584
2585/// Construct a string for the given reciprocal operation of the given type.
2586/// This string should match the corresponding option to the front-end's
2587/// "-mrecip" flag assuming those strings have been passed through in an
2588/// attribute string. For example, "vec-divf" for a division of a vXf32.
2589static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2590 std::string Name = VT.isVector() ? "vec-" : "";
2591
2592 Name += IsSqrt ? "sqrt" : "div";
2593
2594 // TODO: Handle other float types?
2595 if (VT.getScalarType() == MVT::f64) {
2596 Name += "d";
2597 } else if (VT.getScalarType() == MVT::f16) {
2598 Name += "h";
2599 } else {
2600 assert(VT.getScalarType() == MVT::f32 &&
2601 "Unexpected FP type for reciprocal estimate");
2602 Name += "f";
2603 }
2604
2605 return Name;
2606}
2607
2608/// Return the character position and value (a single numeric character) of a
2609/// customized refinement operation in the input string if it exists. Return
2610/// false if there is no customized refinement step count.
2611static bool parseRefinementStep(StringRef In, size_t &Position,
2612 uint8_t &Value) {
2613 const char RefStepToken = ':';
2614 Position = In.find(C: RefStepToken);
2615 if (Position == StringRef::npos)
2616 return false;
2617
2618 StringRef RefStepString = In.substr(Start: Position + 1);
2619 // Allow exactly one numeric character for the additional refinement
2620 // step parameter.
2621 if (RefStepString.size() == 1) {
2622 char RefStepChar = RefStepString[0];
2623 if (isDigit(C: RefStepChar)) {
2624 Value = RefStepChar - '0';
2625 return true;
2626 }
2627 }
2628 report_fatal_error(reason: "Invalid refinement step for -recip.");
2629}
2630
2631/// For the input attribute string, return one of the ReciprocalEstimate enum
2632/// status values (enabled, disabled, or not specified) for this operation on
2633/// the specified data type.
2634static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2635 if (Override.empty())
2636 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2637
2638 SmallVector<StringRef, 4> OverrideVector;
2639 Override.split(A&: OverrideVector, Separator: ',');
2640 unsigned NumArgs = OverrideVector.size();
2641
2642 // Check if "all", "none", or "default" was specified.
2643 if (NumArgs == 1) {
2644 // Look for an optional setting of the number of refinement steps needed
2645 // for this type of reciprocal operation.
2646 size_t RefPos;
2647 uint8_t RefSteps;
2648 if (parseRefinementStep(In: Override, Position&: RefPos, Value&: RefSteps)) {
2649 // Split the string for further processing.
2650 Override = Override.substr(Start: 0, N: RefPos);
2651 }
2652
2653 // All reciprocal types are enabled.
2654 if (Override == "all")
2655 return TargetLoweringBase::ReciprocalEstimate::Enabled;
2656
2657 // All reciprocal types are disabled.
2658 if (Override == "none")
2659 return TargetLoweringBase::ReciprocalEstimate::Disabled;
2660
2661 // Target defaults for enablement are used.
2662 if (Override == "default")
2663 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2664 }
2665
2666 // The attribute string may omit the size suffix ('f'/'d').
2667 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2668 std::string VTNameNoSize = VTName;
2669 VTNameNoSize.pop_back();
2670 static const char DisabledPrefix = '!';
2671
2672 for (StringRef RecipType : OverrideVector) {
2673 size_t RefPos;
2674 uint8_t RefSteps;
2675 if (parseRefinementStep(In: RecipType, Position&: RefPos, Value&: RefSteps))
2676 RecipType = RecipType.substr(Start: 0, N: RefPos);
2677
2678 // Ignore the disablement token for string matching.
2679 bool IsDisabled = RecipType[0] == DisabledPrefix;
2680 if (IsDisabled)
2681 RecipType = RecipType.substr(Start: 1);
2682
2683 if (RecipType == VTName || RecipType == VTNameNoSize)
2684 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
2685 : TargetLoweringBase::ReciprocalEstimate::Enabled;
2686 }
2687
2688 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2689}
2690
2691/// For the input attribute string, return the customized refinement step count
2692/// for this operation on the specified data type. If the step count does not
2693/// exist, return the ReciprocalEstimate enum value for unspecified.
2694static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2695 if (Override.empty())
2696 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2697
2698 SmallVector<StringRef, 4> OverrideVector;
2699 Override.split(A&: OverrideVector, Separator: ',');
2700 unsigned NumArgs = OverrideVector.size();
2701
2702 // Check if "all", "default", or "none" was specified.
2703 if (NumArgs == 1) {
2704 // Look for an optional setting of the number of refinement steps needed
2705 // for this type of reciprocal operation.
2706 size_t RefPos;
2707 uint8_t RefSteps;
2708 if (!parseRefinementStep(In: Override, Position&: RefPos, Value&: RefSteps))
2709 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2710
2711 // Split the string for further processing.
2712 Override = Override.substr(Start: 0, N: RefPos);
2713 assert(Override != "none" &&
2714 "Disabled reciprocals, but specifed refinement steps?");
2715
2716 // If this is a general override, return the specified number of steps.
2717 if (Override == "all" || Override == "default")
2718 return RefSteps;
2719 }
2720
2721 // The attribute string may omit the size suffix ('f'/'d').
2722 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2723 std::string VTNameNoSize = VTName;
2724 VTNameNoSize.pop_back();
2725
2726 for (StringRef RecipType : OverrideVector) {
2727 size_t RefPos;
2728 uint8_t RefSteps;
2729 if (!parseRefinementStep(In: RecipType, Position&: RefPos, Value&: RefSteps))
2730 continue;
2731
2732 RecipType = RecipType.substr(Start: 0, N: RefPos);
2733 if (RecipType == VTName || RecipType == VTNameNoSize)
2734 return RefSteps;
2735 }
2736
2737 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2738}
2739
2740int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,
2741 MachineFunction &MF) const {
2742 return getOpEnabled(IsSqrt: true, VT, Override: getRecipEstimateForFunc(MF));
2743}
2744
2745int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,
2746 MachineFunction &MF) const {
2747 return getOpEnabled(IsSqrt: false, VT, Override: getRecipEstimateForFunc(MF));
2748}
2749
2750int TargetLoweringBase::getSqrtRefinementSteps(EVT VT,
2751 MachineFunction &MF) const {
2752 return getOpRefinementSteps(IsSqrt: true, VT, Override: getRecipEstimateForFunc(MF));
2753}
2754
2755int TargetLoweringBase::getDivRefinementSteps(EVT VT,
2756 MachineFunction &MF) const {
2757 return getOpRefinementSteps(IsSqrt: false, VT, Override: getRecipEstimateForFunc(MF));
2758}
2759
2760bool TargetLoweringBase::isLoadBitCastBeneficial(
2761 EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG,
2762 const MachineMemOperand &MMO) const {
2763 // Single-element vectors are scalarized, so we should generally avoid having
2764 // any memory operations on such types, as they would get scalarized too.
2765 if (LoadVT.isFixedLengthVector() && BitcastVT.isFixedLengthVector() &&
2766 BitcastVT.getVectorNumElements() == 1)
2767 return false;
2768
2769 // Don't do if we could do an indexed load on the original type, but not on
2770 // the new one.
2771 if (!LoadVT.isSimple() || !BitcastVT.isSimple())
2772 return true;
2773
2774 MVT LoadMVT = LoadVT.getSimpleVT();
2775
2776 // Don't bother doing this if it's just going to be promoted again later, as
2777 // doing so might interfere with other combines.
2778 if (getOperationAction(Op: ISD::LOAD, VT: LoadMVT) == Promote &&
2779 getTypeToPromoteTo(Op: ISD::LOAD, VT: LoadMVT) == BitcastVT.getSimpleVT())
2780 return false;
2781
2782 unsigned Fast = 0;
2783 return allowsMemoryAccess(Context&: *DAG.getContext(), DL: DAG.getDataLayout(), VT: BitcastVT,
2784 MMO, Fast: &Fast) &&
2785 Fast;
2786}
2787
2788void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
2789 MF.getRegInfo().freezeReservedRegs();
2790}
2791
2792MachineMemOperand::Flags TargetLoweringBase::getLoadMemOperandFlags(
2793 const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC,
2794 const TargetLibraryInfo *LibInfo, CodeGenOptLevel OptLevel) const {
2795 MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad;
2796 if (LI.isVolatile())
2797 Flags |= MachineMemOperand::MOVolatile;
2798
2799 if (LI.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2800 Flags |= MachineMemOperand::MONonTemporal;
2801
2802 if (LI.hasMetadata(KindID: LLVMContext::MD_invariant_load))
2803 Flags |= MachineMemOperand::MOInvariant;
2804
2805 // Dereferenceability analysis is expensive, skip at O0.
2806 if (OptLevel != CodeGenOptLevel::None &&
2807 isDereferenceableAndAlignedPointer(
2808 V: LI.getPointerOperand(), Ty: LI.getType(), Alignment: LI.getAlign(),
2809 Q: SimplifyQuery(DL, LibInfo, /*DT=*/nullptr, AC, &LI))) {
2810 Flags |= MachineMemOperand::MODereferenceable;
2811 } else if (LI.hasMetadata(KindID: LLVMContext::MD_dereferenceable)) {
2812 Flags |= MachineMemOperand::MODereferenceable;
2813 }
2814
2815 Flags |= getTargetMMOFlags(I: LI);
2816 return Flags;
2817}
2818
2819MachineMemOperand::Flags
2820TargetLoweringBase::getStoreMemOperandFlags(const StoreInst &SI,
2821 const DataLayout &DL) const {
2822 MachineMemOperand::Flags Flags = MachineMemOperand::MOStore;
2823
2824 if (SI.isVolatile())
2825 Flags |= MachineMemOperand::MOVolatile;
2826
2827 if (SI.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2828 Flags |= MachineMemOperand::MONonTemporal;
2829
2830 // FIXME: Not preserving dereferenceable
2831 Flags |= getTargetMMOFlags(I: SI);
2832 return Flags;
2833}
2834
2835MachineMemOperand::Flags
2836TargetLoweringBase::getAtomicMemOperandFlags(const Instruction &AI,
2837 const DataLayout &DL) const {
2838 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
2839
2840 if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(Val: &AI)) {
2841 if (RMW->isVolatile())
2842 Flags |= MachineMemOperand::MOVolatile;
2843 } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(Val: &AI)) {
2844 if (CmpX->isVolatile())
2845 Flags |= MachineMemOperand::MOVolatile;
2846 } else
2847 llvm_unreachable("not an atomic instruction");
2848
2849 // FIXME: Not preserving dereferenceable
2850 Flags |= getTargetMMOFlags(I: AI);
2851 return Flags;
2852}
2853
2854MachineMemOperand::Flags TargetLoweringBase::getVPIntrinsicMemOperandFlags(
2855 const VPIntrinsic &VPIntrin) const {
2856 MachineMemOperand::Flags Flags = MachineMemOperand::MONone;
2857 Intrinsic::ID IntrinID = VPIntrin.getIntrinsicID();
2858
2859 switch (IntrinID) {
2860 default:
2861 llvm_unreachable("unexpected intrinsic. Existing code may be appropriate "
2862 "for it, but support must be explicitly enabled");
2863 case Intrinsic::vp_load:
2864 case Intrinsic::vp_gather:
2865 case Intrinsic::experimental_vp_strided_load:
2866 Flags = MachineMemOperand::MOLoad;
2867 break;
2868 case Intrinsic::vp_store:
2869 case Intrinsic::vp_scatter:
2870 case Intrinsic::experimental_vp_strided_store:
2871 Flags = MachineMemOperand::MOStore;
2872 break;
2873 }
2874
2875 if (VPIntrin.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2876 Flags |= MachineMemOperand::MONonTemporal;
2877
2878 Flags |= getTargetMMOFlags(I: VPIntrin);
2879 return Flags;
2880}
2881
2882Instruction *TargetLoweringBase::emitLeadingFence(IRBuilderBase &Builder,
2883 Instruction *Inst,
2884 AtomicOrdering Ord) const {
2885 if (isReleaseOrStronger(AO: Ord) && Inst->hasAtomicStore())
2886 return Builder.CreateFence(Ordering: Ord);
2887 else
2888 return nullptr;
2889}
2890
2891Instruction *TargetLoweringBase::emitTrailingFence(IRBuilderBase &Builder,
2892 Instruction *Inst,
2893 AtomicOrdering Ord) const {
2894 if (isAcquireOrStronger(AO: Ord))
2895 return Builder.CreateFence(Ordering: Ord);
2896 else
2897 return nullptr;
2898}
2899
2900//===----------------------------------------------------------------------===//
2901// GlobalISel Hooks
2902//===----------------------------------------------------------------------===//
2903
2904bool TargetLoweringBase::shouldLocalize(const MachineInstr &MI,
2905 const TargetTransformInfo *TTI) const {
2906 auto &MF = *MI.getMF();
2907 auto &MRI = MF.getRegInfo();
2908 // Assuming a spill and reload of a value has a cost of 1 instruction each,
2909 // this helper function computes the maximum number of uses we should consider
2910 // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2911 // break even in terms of code size when the original MI has 2 users vs
2912 // choosing to potentially spill. Any more than 2 users we we have a net code
2913 // size increase. This doesn't take into account register pressure though.
2914 auto maxUses = [](unsigned RematCost) {
2915 // A cost of 1 means remats are basically free.
2916 if (RematCost == 1)
2917 return std::numeric_limits<unsigned>::max();
2918 if (RematCost == 2)
2919 return 2U;
2920
2921 // Remat is too expensive, only sink if there's one user.
2922 if (RematCost > 2)
2923 return 1U;
2924 llvm_unreachable("Unexpected remat cost");
2925 };
2926
2927 switch (MI.getOpcode()) {
2928 default:
2929 return false;
2930 // Constants-like instructions should be close to their users.
2931 // We don't want long live-ranges for them.
2932 case TargetOpcode::G_CONSTANT:
2933 case TargetOpcode::G_FCONSTANT:
2934 case TargetOpcode::G_FRAME_INDEX:
2935 case TargetOpcode::G_INTTOPTR:
2936 return true;
2937 case TargetOpcode::G_GLOBAL_VALUE: {
2938 unsigned RematCost = TTI->getGISelRematGlobalCost();
2939 Register Reg = MI.getOperand(i: 0).getReg();
2940 unsigned MaxUses = maxUses(RematCost);
2941 if (MaxUses == UINT_MAX)
2942 return true; // Remats are "free" so always localize.
2943 return MRI.hasAtMostUserInstrs(Reg, MaxUsers: MaxUses);
2944 }
2945 }
2946}
2947