1//===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the TargetLoweringBase class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/ADT/BitVector.h"
14#include "llvm/ADT/DenseMap.h"
15#include "llvm/ADT/STLExtras.h"
16#include "llvm/ADT/SmallVector.h"
17#include "llvm/ADT/StringExtras.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/ADT/Twine.h"
20#include "llvm/Analysis/Loads.h"
21#include "llvm/Analysis/TargetTransformInfo.h"
22#include "llvm/CodeGen/Analysis.h"
23#include "llvm/CodeGen/ISDOpcodes.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstr.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineMemOperand.h"
30#include "llvm/CodeGen/MachineOperand.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/RuntimeLibcallUtil.h"
33#include "llvm/CodeGen/StackMaps.h"
34#include "llvm/CodeGen/TargetLowering.h"
35#include "llvm/CodeGen/TargetOpcodes.h"
36#include "llvm/CodeGen/TargetRegisterInfo.h"
37#include "llvm/CodeGen/ValueTypes.h"
38#include "llvm/CodeGenTypes/MachineValueType.h"
39#include "llvm/IR/Attributes.h"
40#include "llvm/IR/CallingConv.h"
41#include "llvm/IR/DataLayout.h"
42#include "llvm/IR/DerivedTypes.h"
43#include "llvm/IR/Function.h"
44#include "llvm/IR/GlobalValue.h"
45#include "llvm/IR/GlobalVariable.h"
46#include "llvm/IR/IRBuilder.h"
47#include "llvm/IR/Module.h"
48#include "llvm/IR/Type.h"
49#include "llvm/Support/Casting.h"
50#include "llvm/Support/CommandLine.h"
51#include "llvm/Support/Compiler.h"
52#include "llvm/Support/ErrorHandling.h"
53#include "llvm/Support/MathExtras.h"
54#include "llvm/Target/TargetMachine.h"
55#include "llvm/Target/TargetOptions.h"
56#include "llvm/TargetParser/Triple.h"
57#include "llvm/Transforms/Utils/SizeOpts.h"
58#include <algorithm>
59#include <cassert>
60#include <cstdint>
61#include <cstring>
62#include <string>
63#include <tuple>
64#include <utility>
65
66using namespace llvm;
67
68static cl::opt<bool> JumpIsExpensiveOverride(
69 "jump-is-expensive", cl::init(Val: false),
70 cl::desc("Do not create extra branches to split comparison logic."),
71 cl::Hidden);
72
73static cl::opt<unsigned> MinimumJumpTableEntries
74 ("min-jump-table-entries", cl::init(Val: 4), cl::Hidden,
75 cl::desc("Set minimum number of entries to use a jump table."));
76
77static cl::opt<unsigned> MaximumJumpTableSize
78 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
79 cl::desc("Set maximum size of jump tables."));
80
81/// Minimum jump table density for normal functions.
82static cl::opt<unsigned>
83 JumpTableDensity("jump-table-density", cl::init(Val: 10), cl::Hidden,
84 cl::desc("Minimum density for building a jump table in "
85 "a normal function"));
86
87/// Minimum jump table density for -Os or -Oz functions.
88static cl::opt<unsigned> OptsizeJumpTableDensity(
89 "optsize-jump-table-density", cl::init(Val: 40), cl::Hidden,
90 cl::desc("Minimum density for building a jump table in "
91 "an optsize function"));
92
93static cl::opt<unsigned> MinimumBitTestCmpsOverride(
94 "min-bit-test-cmps", cl::init(Val: 2), cl::Hidden,
95 cl::desc("Set minimum of largest number of comparisons "
96 "to use bit test for switch."));
97
98static cl::opt<unsigned> MaxStoresPerMemsetOverride(
99 "max-store-memset", cl::init(Val: 0), cl::Hidden,
100 cl::desc("Override target's MaxStoresPerMemset and "
101 "MaxStoresPerMemsetOptSize. "
102 "Set to 0 to use the target default."));
103
104static cl::opt<unsigned> MaxStoresPerMemcpyOverride(
105 "max-store-memcpy", cl::init(Val: 0), cl::Hidden,
106 cl::desc("Override target's MaxStoresPerMemcpy and "
107 "MaxStoresPerMemcpyOptSize. "
108 "Set to 0 to use the target default."));
109
110static cl::opt<unsigned> MaxStoresPerMemmoveOverride(
111 "max-store-memmove", cl::init(Val: 0), cl::Hidden,
112 cl::desc("Override target's MaxStoresPerMemmove and "
113 "MaxStoresPerMemmoveOptSize. "
114 "Set to 0 to use the target default."));
115
116// FIXME: This option is only to test if the strict fp operation processed
117// correctly by preventing mutating strict fp operation to normal fp operation
118// during development. When the backend supports strict float operation, this
119// option will be meaningless.
120static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
121 cl::desc("Don't mutate strict-float node to a legalize node"),
122 cl::init(Val: false), cl::Hidden);
123
124LLVM_ABI RTLIB::Libcall RTLIB::getSHL(EVT VT) {
125 if (VT == MVT::i16)
126 return RTLIB::SHL_I16;
127 if (VT == MVT::i32)
128 return RTLIB::SHL_I32;
129 if (VT == MVT::i64)
130 return RTLIB::SHL_I64;
131 if (VT == MVT::i128)
132 return RTLIB::SHL_I128;
133
134 return RTLIB::UNKNOWN_LIBCALL;
135}
136
137LLVM_ABI RTLIB::Libcall RTLIB::getSRL(EVT VT) {
138 if (VT == MVT::i16)
139 return RTLIB::SRL_I16;
140 if (VT == MVT::i32)
141 return RTLIB::SRL_I32;
142 if (VT == MVT::i64)
143 return RTLIB::SRL_I64;
144 if (VT == MVT::i128)
145 return RTLIB::SRL_I128;
146
147 return RTLIB::UNKNOWN_LIBCALL;
148}
149
150LLVM_ABI RTLIB::Libcall RTLIB::getSRA(EVT VT) {
151 if (VT == MVT::i16)
152 return RTLIB::SRA_I16;
153 if (VT == MVT::i32)
154 return RTLIB::SRA_I32;
155 if (VT == MVT::i64)
156 return RTLIB::SRA_I64;
157 if (VT == MVT::i128)
158 return RTLIB::SRA_I128;
159
160 return RTLIB::UNKNOWN_LIBCALL;
161}
162
163LLVM_ABI RTLIB::Libcall RTLIB::getMUL(EVT VT) {
164 if (VT == MVT::i16)
165 return RTLIB::MUL_I16;
166 if (VT == MVT::i32)
167 return RTLIB::MUL_I32;
168 if (VT == MVT::i64)
169 return RTLIB::MUL_I64;
170 if (VT == MVT::i128)
171 return RTLIB::MUL_I128;
172 return RTLIB::UNKNOWN_LIBCALL;
173}
174
175LLVM_ABI RTLIB::Libcall RTLIB::getMULO(EVT VT) {
176 if (VT == MVT::i32)
177 return RTLIB::MULO_I32;
178 if (VT == MVT::i64)
179 return RTLIB::MULO_I64;
180 if (VT == MVT::i128)
181 return RTLIB::MULO_I128;
182 return RTLIB::UNKNOWN_LIBCALL;
183}
184
185LLVM_ABI RTLIB::Libcall RTLIB::getSDIV(EVT VT) {
186 if (VT == MVT::i16)
187 return RTLIB::SDIV_I16;
188 if (VT == MVT::i32)
189 return RTLIB::SDIV_I32;
190 if (VT == MVT::i64)
191 return RTLIB::SDIV_I64;
192 if (VT == MVT::i128)
193 return RTLIB::SDIV_I128;
194 return RTLIB::UNKNOWN_LIBCALL;
195}
196
197LLVM_ABI RTLIB::Libcall RTLIB::getUDIV(EVT VT) {
198 if (VT == MVT::i16)
199 return RTLIB::UDIV_I16;
200 if (VT == MVT::i32)
201 return RTLIB::UDIV_I32;
202 if (VT == MVT::i64)
203 return RTLIB::UDIV_I64;
204 if (VT == MVT::i128)
205 return RTLIB::UDIV_I128;
206 return RTLIB::UNKNOWN_LIBCALL;
207}
208
209LLVM_ABI RTLIB::Libcall RTLIB::getSREM(EVT VT) {
210 if (VT == MVT::i16)
211 return RTLIB::SREM_I16;
212 if (VT == MVT::i32)
213 return RTLIB::SREM_I32;
214 if (VT == MVT::i64)
215 return RTLIB::SREM_I64;
216 if (VT == MVT::i128)
217 return RTLIB::SREM_I128;
218 return RTLIB::UNKNOWN_LIBCALL;
219}
220
221LLVM_ABI RTLIB::Libcall RTLIB::getUREM(EVT VT) {
222 if (VT == MVT::i16)
223 return RTLIB::UREM_I16;
224 if (VT == MVT::i32)
225 return RTLIB::UREM_I32;
226 if (VT == MVT::i64)
227 return RTLIB::UREM_I64;
228 if (VT == MVT::i128)
229 return RTLIB::UREM_I128;
230 return RTLIB::UNKNOWN_LIBCALL;
231}
232
233LLVM_ABI RTLIB::Libcall RTLIB::getCTPOP(EVT VT) {
234 if (VT == MVT::i32)
235 return RTLIB::CTPOP_I32;
236 if (VT == MVT::i64)
237 return RTLIB::CTPOP_I64;
238 if (VT == MVT::i128)
239 return RTLIB::CTPOP_I128;
240 return RTLIB::UNKNOWN_LIBCALL;
241}
242
243/// GetFPLibCall - Helper to return the right libcall for the given floating
244/// point type, or UNKNOWN_LIBCALL if there is none.
245RTLIB::Libcall RTLIB::getFPLibCall(EVT VT,
246 RTLIB::Libcall Call_F32,
247 RTLIB::Libcall Call_F64,
248 RTLIB::Libcall Call_F80,
249 RTLIB::Libcall Call_F128,
250 RTLIB::Libcall Call_PPCF128) {
251 return
252 VT == MVT::f32 ? Call_F32 :
253 VT == MVT::f64 ? Call_F64 :
254 VT == MVT::f80 ? Call_F80 :
255 VT == MVT::f128 ? Call_F128 :
256 VT == MVT::ppcf128 ? Call_PPCF128 :
257 RTLIB::UNKNOWN_LIBCALL;
258}
259
260/// getFPEXT - Return the FPEXT_*_* value for the given types, or
261/// UNKNOWN_LIBCALL if there is none.
262RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
263 if (OpVT == MVT::f16) {
264 if (RetVT == MVT::f32)
265 return FPEXT_F16_F32;
266 if (RetVT == MVT::f64)
267 return FPEXT_F16_F64;
268 if (RetVT == MVT::f80)
269 return FPEXT_F16_F80;
270 if (RetVT == MVT::f128)
271 return FPEXT_F16_F128;
272 } else if (OpVT == MVT::f32) {
273 if (RetVT == MVT::f64)
274 return FPEXT_F32_F64;
275 if (RetVT == MVT::f128)
276 return FPEXT_F32_F128;
277 if (RetVT == MVT::ppcf128)
278 return FPEXT_F32_PPCF128;
279 } else if (OpVT == MVT::f64) {
280 if (RetVT == MVT::f128)
281 return FPEXT_F64_F128;
282 else if (RetVT == MVT::ppcf128)
283 return FPEXT_F64_PPCF128;
284 } else if (OpVT == MVT::f80) {
285 if (RetVT == MVT::f128)
286 return FPEXT_F80_F128;
287 } else if (OpVT == MVT::bf16) {
288 if (RetVT == MVT::f32)
289 return FPEXT_BF16_F32;
290 }
291
292 return UNKNOWN_LIBCALL;
293}
294
295/// getFPROUND - Return the FPROUND_*_* value for the given types, or
296/// UNKNOWN_LIBCALL if there is none.
297RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
298 if (RetVT == MVT::f16) {
299 if (OpVT == MVT::f32)
300 return FPROUND_F32_F16;
301 if (OpVT == MVT::f64)
302 return FPROUND_F64_F16;
303 if (OpVT == MVT::f80)
304 return FPROUND_F80_F16;
305 if (OpVT == MVT::f128)
306 return FPROUND_F128_F16;
307 if (OpVT == MVT::ppcf128)
308 return FPROUND_PPCF128_F16;
309 } else if (RetVT == MVT::bf16) {
310 if (OpVT == MVT::f32)
311 return FPROUND_F32_BF16;
312 if (OpVT == MVT::f64)
313 return FPROUND_F64_BF16;
314 if (OpVT == MVT::f80)
315 return FPROUND_F80_BF16;
316 if (OpVT == MVT::f128)
317 return FPROUND_F128_BF16;
318 } else if (RetVT == MVT::f32) {
319 if (OpVT == MVT::f64)
320 return FPROUND_F64_F32;
321 if (OpVT == MVT::f80)
322 return FPROUND_F80_F32;
323 if (OpVT == MVT::f128)
324 return FPROUND_F128_F32;
325 if (OpVT == MVT::ppcf128)
326 return FPROUND_PPCF128_F32;
327 } else if (RetVT == MVT::f64) {
328 if (OpVT == MVT::f80)
329 return FPROUND_F80_F64;
330 if (OpVT == MVT::f128)
331 return FPROUND_F128_F64;
332 if (OpVT == MVT::ppcf128)
333 return FPROUND_PPCF128_F64;
334 } else if (RetVT == MVT::f80) {
335 if (OpVT == MVT::f128)
336 return FPROUND_F128_F80;
337 }
338
339 return UNKNOWN_LIBCALL;
340}
341
342/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
343/// UNKNOWN_LIBCALL if there is none.
344RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
345 if (OpVT == MVT::f16) {
346 if (RetVT == MVT::i32)
347 return FPTOSINT_F16_I32;
348 if (RetVT == MVT::i64)
349 return FPTOSINT_F16_I64;
350 if (RetVT == MVT::i128)
351 return FPTOSINT_F16_I128;
352 } else if (OpVT == MVT::f32) {
353 if (RetVT == MVT::i32)
354 return FPTOSINT_F32_I32;
355 if (RetVT == MVT::i64)
356 return FPTOSINT_F32_I64;
357 if (RetVT == MVT::i128)
358 return FPTOSINT_F32_I128;
359 } else if (OpVT == MVT::f64) {
360 if (RetVT == MVT::i32)
361 return FPTOSINT_F64_I32;
362 if (RetVT == MVT::i64)
363 return FPTOSINT_F64_I64;
364 if (RetVT == MVT::i128)
365 return FPTOSINT_F64_I128;
366 } else if (OpVT == MVT::f80) {
367 if (RetVT == MVT::i32)
368 return FPTOSINT_F80_I32;
369 if (RetVT == MVT::i64)
370 return FPTOSINT_F80_I64;
371 if (RetVT == MVT::i128)
372 return FPTOSINT_F80_I128;
373 } else if (OpVT == MVT::f128) {
374 if (RetVT == MVT::i32)
375 return FPTOSINT_F128_I32;
376 if (RetVT == MVT::i64)
377 return FPTOSINT_F128_I64;
378 if (RetVT == MVT::i128)
379 return FPTOSINT_F128_I128;
380 } else if (OpVT == MVT::ppcf128) {
381 if (RetVT == MVT::i32)
382 return FPTOSINT_PPCF128_I32;
383 if (RetVT == MVT::i64)
384 return FPTOSINT_PPCF128_I64;
385 if (RetVT == MVT::i128)
386 return FPTOSINT_PPCF128_I128;
387 }
388 return UNKNOWN_LIBCALL;
389}
390
391/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
392/// UNKNOWN_LIBCALL if there is none.
393RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
394 if (OpVT == MVT::f16) {
395 if (RetVT == MVT::i32)
396 return FPTOUINT_F16_I32;
397 if (RetVT == MVT::i64)
398 return FPTOUINT_F16_I64;
399 if (RetVT == MVT::i128)
400 return FPTOUINT_F16_I128;
401 } else if (OpVT == MVT::f32) {
402 if (RetVT == MVT::i32)
403 return FPTOUINT_F32_I32;
404 if (RetVT == MVT::i64)
405 return FPTOUINT_F32_I64;
406 if (RetVT == MVT::i128)
407 return FPTOUINT_F32_I128;
408 } else if (OpVT == MVT::f64) {
409 if (RetVT == MVT::i32)
410 return FPTOUINT_F64_I32;
411 if (RetVT == MVT::i64)
412 return FPTOUINT_F64_I64;
413 if (RetVT == MVT::i128)
414 return FPTOUINT_F64_I128;
415 } else if (OpVT == MVT::f80) {
416 if (RetVT == MVT::i32)
417 return FPTOUINT_F80_I32;
418 if (RetVT == MVT::i64)
419 return FPTOUINT_F80_I64;
420 if (RetVT == MVT::i128)
421 return FPTOUINT_F80_I128;
422 } else if (OpVT == MVT::f128) {
423 if (RetVT == MVT::i32)
424 return FPTOUINT_F128_I32;
425 if (RetVT == MVT::i64)
426 return FPTOUINT_F128_I64;
427 if (RetVT == MVT::i128)
428 return FPTOUINT_F128_I128;
429 } else if (OpVT == MVT::ppcf128) {
430 if (RetVT == MVT::i32)
431 return FPTOUINT_PPCF128_I32;
432 if (RetVT == MVT::i64)
433 return FPTOUINT_PPCF128_I64;
434 if (RetVT == MVT::i128)
435 return FPTOUINT_PPCF128_I128;
436 }
437 return UNKNOWN_LIBCALL;
438}
439
440/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
441/// UNKNOWN_LIBCALL if there is none.
442RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
443 if (OpVT == MVT::i32) {
444 if (RetVT == MVT::f16)
445 return SINTTOFP_I32_F16;
446 if (RetVT == MVT::f32)
447 return SINTTOFP_I32_F32;
448 if (RetVT == MVT::f64)
449 return SINTTOFP_I32_F64;
450 if (RetVT == MVT::f80)
451 return SINTTOFP_I32_F80;
452 if (RetVT == MVT::f128)
453 return SINTTOFP_I32_F128;
454 if (RetVT == MVT::ppcf128)
455 return SINTTOFP_I32_PPCF128;
456 } else if (OpVT == MVT::i64) {
457 if (RetVT == MVT::bf16)
458 return SINTTOFP_I64_BF16;
459 if (RetVT == MVT::f16)
460 return SINTTOFP_I64_F16;
461 if (RetVT == MVT::f32)
462 return SINTTOFP_I64_F32;
463 if (RetVT == MVT::f64)
464 return SINTTOFP_I64_F64;
465 if (RetVT == MVT::f80)
466 return SINTTOFP_I64_F80;
467 if (RetVT == MVT::f128)
468 return SINTTOFP_I64_F128;
469 if (RetVT == MVT::ppcf128)
470 return SINTTOFP_I64_PPCF128;
471 } else if (OpVT == MVT::i128) {
472 if (RetVT == MVT::f16)
473 return SINTTOFP_I128_F16;
474 if (RetVT == MVT::f32)
475 return SINTTOFP_I128_F32;
476 if (RetVT == MVT::f64)
477 return SINTTOFP_I128_F64;
478 if (RetVT == MVT::f80)
479 return SINTTOFP_I128_F80;
480 if (RetVT == MVT::f128)
481 return SINTTOFP_I128_F128;
482 if (RetVT == MVT::ppcf128)
483 return SINTTOFP_I128_PPCF128;
484 }
485 return UNKNOWN_LIBCALL;
486}
487
488/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
489/// UNKNOWN_LIBCALL if there is none.
490RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
491 if (OpVT == MVT::i32) {
492 if (RetVT == MVT::f16)
493 return UINTTOFP_I32_F16;
494 if (RetVT == MVT::f32)
495 return UINTTOFP_I32_F32;
496 if (RetVT == MVT::f64)
497 return UINTTOFP_I32_F64;
498 if (RetVT == MVT::f80)
499 return UINTTOFP_I32_F80;
500 if (RetVT == MVT::f128)
501 return UINTTOFP_I32_F128;
502 if (RetVT == MVT::ppcf128)
503 return UINTTOFP_I32_PPCF128;
504 } else if (OpVT == MVT::i64) {
505 if (RetVT == MVT::bf16)
506 return UINTTOFP_I64_BF16;
507 if (RetVT == MVT::f16)
508 return UINTTOFP_I64_F16;
509 if (RetVT == MVT::f32)
510 return UINTTOFP_I64_F32;
511 if (RetVT == MVT::f64)
512 return UINTTOFP_I64_F64;
513 if (RetVT == MVT::f80)
514 return UINTTOFP_I64_F80;
515 if (RetVT == MVT::f128)
516 return UINTTOFP_I64_F128;
517 if (RetVT == MVT::ppcf128)
518 return UINTTOFP_I64_PPCF128;
519 } else if (OpVT == MVT::i128) {
520 if (RetVT == MVT::f16)
521 return UINTTOFP_I128_F16;
522 if (RetVT == MVT::f32)
523 return UINTTOFP_I128_F32;
524 if (RetVT == MVT::f64)
525 return UINTTOFP_I128_F64;
526 if (RetVT == MVT::f80)
527 return UINTTOFP_I128_F80;
528 if (RetVT == MVT::f128)
529 return UINTTOFP_I128_F128;
530 if (RetVT == MVT::ppcf128)
531 return UINTTOFP_I128_PPCF128;
532 }
533 return UNKNOWN_LIBCALL;
534}
535
536RTLIB::Libcall RTLIB::getPOWI(EVT RetVT) {
537 return getFPLibCall(VT: RetVT, Call_F32: POWI_F32, Call_F64: POWI_F64, Call_F80: POWI_F80, Call_F128: POWI_F128,
538 Call_PPCF128: POWI_PPCF128);
539}
540
541RTLIB::Libcall RTLIB::getPOW(EVT RetVT) {
542 // TODO: Tablegen should generate this function
543 if (RetVT.isVector()) {
544 if (!RetVT.isSimple())
545 return RTLIB::UNKNOWN_LIBCALL;
546 switch (RetVT.getSimpleVT().SimpleTy) {
547 case MVT::v4f32:
548 return RTLIB::POW_V4F32;
549 case MVT::v2f64:
550 return RTLIB::POW_V2F64;
551 case MVT::nxv4f32:
552 return RTLIB::POW_NXV4F32;
553 case MVT::nxv2f64:
554 return RTLIB::POW_NXV2F64;
555 default:
556 return RTLIB::UNKNOWN_LIBCALL;
557 }
558 }
559
560 return getFPLibCall(VT: RetVT, Call_F32: POW_F32, Call_F64: POW_F64, Call_F80: POW_F80, Call_F128: POW_F128, Call_PPCF128: POW_PPCF128);
561}
562
563RTLIB::Libcall RTLIB::getLDEXP(EVT RetVT) {
564 return getFPLibCall(VT: RetVT, Call_F32: LDEXP_F32, Call_F64: LDEXP_F64, Call_F80: LDEXP_F80, Call_F128: LDEXP_F128,
565 Call_PPCF128: LDEXP_PPCF128);
566}
567
568RTLIB::Libcall RTLIB::getFREXP(EVT RetVT) {
569 return getFPLibCall(VT: RetVT, Call_F32: FREXP_F32, Call_F64: FREXP_F64, Call_F80: FREXP_F80, Call_F128: FREXP_F128,
570 Call_PPCF128: FREXP_PPCF128);
571}
572
573RTLIB::Libcall RTLIB::getSIN(EVT RetVT) {
574 return getFPLibCall(VT: RetVT, Call_F32: SIN_F32, Call_F64: SIN_F64, Call_F80: SIN_F80, Call_F128: SIN_F128, Call_PPCF128: SIN_PPCF128);
575}
576
577RTLIB::Libcall RTLIB::getCOS(EVT RetVT) {
578 return getFPLibCall(VT: RetVT, Call_F32: COS_F32, Call_F64: COS_F64, Call_F80: COS_F80, Call_F128: COS_F128, Call_PPCF128: COS_PPCF128);
579}
580
581RTLIB::Libcall RTLIB::getSINCOS(EVT RetVT) {
582 // TODO: Tablegen should generate this function
583 if (RetVT.isVector()) {
584 if (!RetVT.isSimple())
585 return RTLIB::UNKNOWN_LIBCALL;
586 switch (RetVT.getSimpleVT().SimpleTy) {
587 case MVT::v4f32:
588 return RTLIB::SINCOS_V4F32;
589 case MVT::v2f64:
590 return RTLIB::SINCOS_V2F64;
591 case MVT::nxv4f32:
592 return RTLIB::SINCOS_NXV4F32;
593 case MVT::nxv2f64:
594 return RTLIB::SINCOS_NXV2F64;
595 default:
596 return RTLIB::UNKNOWN_LIBCALL;
597 }
598 }
599
600 return getFPLibCall(VT: RetVT, Call_F32: SINCOS_F32, Call_F64: SINCOS_F64, Call_F80: SINCOS_F80, Call_F128: SINCOS_F128,
601 Call_PPCF128: SINCOS_PPCF128);
602}
603
604RTLIB::Libcall RTLIB::getSINCOSPI(EVT RetVT) {
605 // TODO: Tablegen should generate this function
606 if (RetVT.isVector()) {
607 if (!RetVT.isSimple())
608 return RTLIB::UNKNOWN_LIBCALL;
609 switch (RetVT.getSimpleVT().SimpleTy) {
610 case MVT::v4f32:
611 return RTLIB::SINCOSPI_V4F32;
612 case MVT::v2f64:
613 return RTLIB::SINCOSPI_V2F64;
614 case MVT::nxv4f32:
615 return RTLIB::SINCOSPI_NXV4F32;
616 case MVT::nxv2f64:
617 return RTLIB::SINCOSPI_NXV2F64;
618 default:
619 return RTLIB::UNKNOWN_LIBCALL;
620 }
621 }
622
623 return getFPLibCall(VT: RetVT, Call_F32: SINCOSPI_F32, Call_F64: SINCOSPI_F64, Call_F80: SINCOSPI_F80,
624 Call_F128: SINCOSPI_F128, Call_PPCF128: SINCOSPI_PPCF128);
625}
626
627RTLIB::Libcall RTLIB::getSINCOS_STRET(EVT RetVT) {
628 return getFPLibCall(VT: RetVT, Call_F32: SINCOS_STRET_F32, Call_F64: SINCOS_STRET_F64,
629 Call_F80: UNKNOWN_LIBCALL, Call_F128: UNKNOWN_LIBCALL, Call_PPCF128: UNKNOWN_LIBCALL);
630}
631
632RTLIB::Libcall RTLIB::getREM(EVT VT) {
633 // TODO: Tablegen should generate this function
634 if (VT.isVector()) {
635 if (!VT.isSimple())
636 return RTLIB::UNKNOWN_LIBCALL;
637 switch (VT.getSimpleVT().SimpleTy) {
638 case MVT::v4f32:
639 return RTLIB::REM_V4F32;
640 case MVT::v2f64:
641 return RTLIB::REM_V2F64;
642 case MVT::nxv4f32:
643 return RTLIB::REM_NXV4F32;
644 case MVT::nxv2f64:
645 return RTLIB::REM_NXV2F64;
646 default:
647 return RTLIB::UNKNOWN_LIBCALL;
648 }
649 }
650
651 return getFPLibCall(VT, Call_F32: REM_F32, Call_F64: REM_F64, Call_F80: REM_F80, Call_F128: REM_F128, Call_PPCF128: REM_PPCF128);
652}
653
654RTLIB::Libcall RTLIB::getCBRT(EVT VT) {
655 // TODO: Tablegen should generate this function
656 if (VT.isVector()) {
657 if (!VT.isSimple())
658 return RTLIB::UNKNOWN_LIBCALL;
659 switch (VT.getSimpleVT().SimpleTy) {
660 case MVT::v4f32:
661 return RTLIB::CBRT_V4F32;
662 case MVT::v2f64:
663 return RTLIB::CBRT_V2F64;
664 case MVT::nxv4f32:
665 return RTLIB::CBRT_NXV4F32;
666 case MVT::nxv2f64:
667 return RTLIB::CBRT_NXV2F64;
668 default:
669 return RTLIB::UNKNOWN_LIBCALL;
670 }
671 }
672
673 return getFPLibCall(VT, Call_F32: CBRT_F32, Call_F64: CBRT_F64, Call_F80: CBRT_F80, Call_F128: CBRT_F128,
674 Call_PPCF128: CBRT_PPCF128);
675}
676
677RTLIB::Libcall RTLIB::getMODF(EVT RetVT) {
678 // TODO: Tablegen should generate this function
679 if (RetVT.isVector()) {
680 if (!RetVT.isSimple())
681 return RTLIB::UNKNOWN_LIBCALL;
682 switch (RetVT.getSimpleVT().SimpleTy) {
683 case MVT::v4f32:
684 return RTLIB::MODF_V4F32;
685 case MVT::v2f64:
686 return RTLIB::MODF_V2F64;
687 case MVT::nxv4f32:
688 return RTLIB::MODF_NXV4F32;
689 case MVT::nxv2f64:
690 return RTLIB::MODF_NXV2F64;
691 default:
692 return RTLIB::UNKNOWN_LIBCALL;
693 }
694 }
695
696 return getFPLibCall(VT: RetVT, Call_F32: MODF_F32, Call_F64: MODF_F64, Call_F80: MODF_F80, Call_F128: MODF_F128,
697 Call_PPCF128: MODF_PPCF128);
698}
699
700RTLIB::Libcall RTLIB::getLROUND(EVT VT) {
701 if (VT == MVT::f32)
702 return RTLIB::LROUND_F32;
703 if (VT == MVT::f64)
704 return RTLIB::LROUND_F64;
705 if (VT == MVT::f80)
706 return RTLIB::LROUND_F80;
707 if (VT == MVT::f128)
708 return RTLIB::LROUND_F128;
709 if (VT == MVT::ppcf128)
710 return RTLIB::LROUND_PPCF128;
711
712 return RTLIB::UNKNOWN_LIBCALL;
713}
714
715RTLIB::Libcall RTLIB::getLLROUND(EVT VT) {
716 if (VT == MVT::f32)
717 return RTLIB::LLROUND_F32;
718 if (VT == MVT::f64)
719 return RTLIB::LLROUND_F64;
720 if (VT == MVT::f80)
721 return RTLIB::LLROUND_F80;
722 if (VT == MVT::f128)
723 return RTLIB::LLROUND_F128;
724 if (VT == MVT::ppcf128)
725 return RTLIB::LLROUND_PPCF128;
726
727 return RTLIB::UNKNOWN_LIBCALL;
728}
729
730RTLIB::Libcall RTLIB::getLRINT(EVT VT) {
731 if (VT == MVT::f32)
732 return RTLIB::LRINT_F32;
733 if (VT == MVT::f64)
734 return RTLIB::LRINT_F64;
735 if (VT == MVT::f80)
736 return RTLIB::LRINT_F80;
737 if (VT == MVT::f128)
738 return RTLIB::LRINT_F128;
739 if (VT == MVT::ppcf128)
740 return RTLIB::LRINT_PPCF128;
741 return RTLIB::UNKNOWN_LIBCALL;
742}
743
744RTLIB::Libcall RTLIB::getLLRINT(EVT VT) {
745 if (VT == MVT::f32)
746 return RTLIB::LLRINT_F32;
747 if (VT == MVT::f64)
748 return RTLIB::LLRINT_F64;
749 if (VT == MVT::f80)
750 return RTLIB::LLRINT_F80;
751 if (VT == MVT::f128)
752 return RTLIB::LLRINT_F128;
753 if (VT == MVT::ppcf128)
754 return RTLIB::LLRINT_PPCF128;
755 return RTLIB::UNKNOWN_LIBCALL;
756}
757
758RTLIB::Libcall RTLIB::getOutlineAtomicHelper(const Libcall (&LC)[5][4],
759 AtomicOrdering Order,
760 uint64_t MemSize) {
761 unsigned ModeN, ModelN;
762 switch (MemSize) {
763 case 1:
764 ModeN = 0;
765 break;
766 case 2:
767 ModeN = 1;
768 break;
769 case 4:
770 ModeN = 2;
771 break;
772 case 8:
773 ModeN = 3;
774 break;
775 case 16:
776 ModeN = 4;
777 break;
778 default:
779 return RTLIB::UNKNOWN_LIBCALL;
780 }
781
782 switch (Order) {
783 case AtomicOrdering::Monotonic:
784 ModelN = 0;
785 break;
786 case AtomicOrdering::Acquire:
787 ModelN = 1;
788 break;
789 case AtomicOrdering::Release:
790 ModelN = 2;
791 break;
792 case AtomicOrdering::AcquireRelease:
793 case AtomicOrdering::SequentiallyConsistent:
794 ModelN = 3;
795 break;
796 default:
797 return UNKNOWN_LIBCALL;
798 }
799
800 return LC[ModeN][ModelN];
801}
802
803RTLIB::Libcall RTLIB::getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order,
804 MVT VT) {
805 if (!VT.isScalarInteger())
806 return UNKNOWN_LIBCALL;
807 uint64_t MemSize = VT.getScalarSizeInBits() / 8;
808
809#define LCALLS(A, B) \
810 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
811#define LCALL5(A) \
812 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
813 switch (Opc) {
814 case ISD::ATOMIC_CMP_SWAP: {
815 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
816 return getOutlineAtomicHelper(LC, Order, MemSize);
817 }
818 case ISD::ATOMIC_SWAP: {
819 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};
820 return getOutlineAtomicHelper(LC, Order, MemSize);
821 }
822 case ISD::ATOMIC_LOAD_ADD: {
823 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};
824 return getOutlineAtomicHelper(LC, Order, MemSize);
825 }
826 case ISD::ATOMIC_LOAD_OR: {
827 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};
828 return getOutlineAtomicHelper(LC, Order, MemSize);
829 }
830 case ISD::ATOMIC_LOAD_CLR: {
831 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};
832 return getOutlineAtomicHelper(LC, Order, MemSize);
833 }
834 case ISD::ATOMIC_LOAD_XOR: {
835 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};
836 return getOutlineAtomicHelper(LC, Order, MemSize);
837 }
838 default:
839 return UNKNOWN_LIBCALL;
840 }
841#undef LCALLS
842#undef LCALL5
843}
844
845RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
846#define OP_TO_LIBCALL(Name, Enum) \
847 case Name: \
848 switch (VT.SimpleTy) { \
849 default: \
850 return UNKNOWN_LIBCALL; \
851 case MVT::i8: \
852 return Enum##_1; \
853 case MVT::i16: \
854 return Enum##_2; \
855 case MVT::i32: \
856 return Enum##_4; \
857 case MVT::i64: \
858 return Enum##_8; \
859 case MVT::i128: \
860 return Enum##_16; \
861 }
862
863 switch (Opc) {
864 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
865 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
866 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
867 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
868 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
869 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
870 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
871 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
872 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
873 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
874 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
875 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
876 }
877
878#undef OP_TO_LIBCALL
879
880 return UNKNOWN_LIBCALL;
881}
882
883RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
884 switch (ElementSize) {
885 case 1:
886 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
887 case 2:
888 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
889 case 4:
890 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
891 case 8:
892 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
893 case 16:
894 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
895 default:
896 return UNKNOWN_LIBCALL;
897 }
898}
899
900RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
901 switch (ElementSize) {
902 case 1:
903 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
904 case 2:
905 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
906 case 4:
907 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
908 case 8:
909 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
910 case 16:
911 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
912 default:
913 return UNKNOWN_LIBCALL;
914 }
915}
916
917RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
918 switch (ElementSize) {
919 case 1:
920 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
921 case 2:
922 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
923 case 4:
924 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
925 case 8:
926 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
927 case 16:
928 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
929 default:
930 return UNKNOWN_LIBCALL;
931 }
932}
933
934ISD::CondCode TargetLoweringBase::getSoftFloatCmpLibcallPredicate(
935 RTLIB::LibcallImpl Impl) const {
936 switch (Impl) {
937 case RTLIB::impl___aeabi_dcmpeq__une:
938 case RTLIB::impl___aeabi_fcmpeq__une:
939 // Usage in the eq case, so we have to invert the comparison.
940 return ISD::SETEQ;
941 case RTLIB::impl___aeabi_dcmpeq__oeq:
942 case RTLIB::impl___aeabi_fcmpeq__oeq:
943 // Normal comparison to boolean value.
944 return ISD::SETNE;
945 case RTLIB::impl___aeabi_dcmplt:
946 case RTLIB::impl___aeabi_dcmple:
947 case RTLIB::impl___aeabi_dcmpge:
948 case RTLIB::impl___aeabi_dcmpgt:
949 case RTLIB::impl___aeabi_dcmpun:
950 case RTLIB::impl___aeabi_fcmplt:
951 case RTLIB::impl___aeabi_fcmple:
952 case RTLIB::impl___aeabi_fcmpge:
953 case RTLIB::impl___aeabi_fcmpgt:
954 /// The AEABI versions return a typical boolean value, so we can compare
955 /// against the integer result as simply != 0.
956 return ISD::SETNE;
957 default:
958 break;
959 }
960
961 // Assume libgcc/compiler-rt behavior. Most of the cases are really aliases of
962 // each other, and return a 3-way comparison style result of -1, 0, or 1
963 // depending on lt/eq/gt.
964 //
965 // FIXME: It would be cleaner to directly express this as a 3-way comparison
966 // soft FP libcall instead of individual compares.
967 RTLIB::Libcall LC = RTLIB::RuntimeLibcallsInfo::getLibcallFromImpl(Impl);
968 switch (LC) {
969 case RTLIB::OEQ_F32:
970 case RTLIB::OEQ_F64:
971 case RTLIB::OEQ_F128:
972 case RTLIB::OEQ_PPCF128:
973 return ISD::SETEQ;
974 case RTLIB::UNE_F32:
975 case RTLIB::UNE_F64:
976 case RTLIB::UNE_F128:
977 case RTLIB::UNE_PPCF128:
978 return ISD::SETNE;
979 case RTLIB::OGE_F32:
980 case RTLIB::OGE_F64:
981 case RTLIB::OGE_F128:
982 case RTLIB::OGE_PPCF128:
983 return ISD::SETGE;
984 case RTLIB::OLT_F32:
985 case RTLIB::OLT_F64:
986 case RTLIB::OLT_F128:
987 case RTLIB::OLT_PPCF128:
988 return ISD::SETLT;
989 case RTLIB::OLE_F32:
990 case RTLIB::OLE_F64:
991 case RTLIB::OLE_F128:
992 case RTLIB::OLE_PPCF128:
993 return ISD::SETLE;
994 case RTLIB::OGT_F32:
995 case RTLIB::OGT_F64:
996 case RTLIB::OGT_F128:
997 case RTLIB::OGT_PPCF128:
998 return ISD::SETGT;
999 case RTLIB::UO_F32:
1000 case RTLIB::UO_F64:
1001 case RTLIB::UO_F128:
1002 case RTLIB::UO_PPCF128:
1003 return ISD::SETNE;
1004 default:
1005 llvm_unreachable("not a compare libcall");
1006 }
1007}
1008
1009/// NOTE: The TargetMachine owns TLOF.
1010TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
1011 const TargetSubtargetInfo &STI)
1012 : TM(tm),
1013 RuntimeLibcallInfo(TM.getTargetTriple(), TM.Options.ExceptionModel,
1014 TM.Options.FloatABIType, TM.Options.EABIVersion,
1015 TM.Options.MCOptions.getABIName(), TM.Options.VecLib),
1016 Libcalls(RuntimeLibcallInfo, STI) {
1017 initActions();
1018
1019 // Perform these initializations only once.
1020 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove =
1021 MaxLoadsPerMemcmp = 8;
1022 MaxGluedStoresPerMemcpy = 0;
1023 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize =
1024 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4;
1025 HasExtractBitsInsn = false;
1026 JumpIsExpensive = JumpIsExpensiveOverride;
1027 PredictableSelectIsExpensive = false;
1028 EnableExtLdPromotion = false;
1029 StackPointerRegisterToSaveRestore = 0;
1030 BooleanContents = UndefinedBooleanContent;
1031 BooleanFloatContents = UndefinedBooleanContent;
1032 BooleanVectorContents = UndefinedBooleanContent;
1033 SchedPreferenceInfo = Sched::ILP;
1034 GatherAllAliasesMaxDepth = 18;
1035 IsStrictFPEnabled = DisableStrictNodeMutation;
1036 MaxBytesForAlignment = 0;
1037 MaxAtomicSizeInBitsSupported = 0;
1038
1039 // Assume that even with libcalls, no target supports wider than 128 bit
1040 // division.
1041 MaxDivRemBitWidthSupported = 128;
1042
1043 MaxLargeFPConvertBitWidthSupported = 128;
1044
1045 MinCmpXchgSizeInBits = 0;
1046 SupportsUnalignedAtomics = false;
1047
1048 MinimumBitTestCmps = MinimumBitTestCmpsOverride;
1049}
1050
1051// Define the virtual destructor out-of-line to act as a key method to anchor
1052// debug info (see coding standards).
1053TargetLoweringBase::~TargetLoweringBase() = default;
1054
1055void TargetLoweringBase::initActions() {
1056 // All operations default to being supported.
1057 memset(s: OpActions, c: 0, n: sizeof(OpActions));
1058 memset(s: LoadExtActions, c: 0, n: sizeof(LoadExtActions));
1059 memset(s: AtomicLoadExtActions, c: 0, n: sizeof(AtomicLoadExtActions));
1060 memset(s: TruncStoreActions, c: 0, n: sizeof(TruncStoreActions));
1061 memset(s: IndexedModeActions, c: 0, n: sizeof(IndexedModeActions));
1062 memset(s: CondCodeActions, c: 0, n: sizeof(CondCodeActions));
1063 llvm::fill(Range&: RegClassForVT, Value: nullptr);
1064 llvm::fill(Range&: TargetDAGCombineArray, Value: 0);
1065
1066 // Let extending atomic loads be unsupported by default.
1067 for (MVT ValVT : MVT::all_valuetypes())
1068 for (MVT MemVT : MVT::all_valuetypes())
1069 setAtomicLoadExtAction(ExtTypes: {ISD::SEXTLOAD, ISD::ZEXTLOAD}, ValVT, MemVT,
1070 Action: Expand);
1071
1072 // We're somewhat special casing MVT::i2 and MVT::i4. Ideally we want to
1073 // remove this and targets should individually set these types if not legal.
1074 for (ISD::NodeType NT : enum_seq(Begin: ISD::DELETED_NODE, End: ISD::BUILTIN_OP_END,
1075 force_iteration_on_noniterable_enum)) {
1076 for (MVT VT : {MVT::i2, MVT::i4})
1077 OpActions[(unsigned)VT.SimpleTy][NT] = Expand;
1078 }
1079 for (MVT AVT : MVT::all_valuetypes()) {
1080 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {
1081 setTruncStoreAction(ValVT: AVT, MemVT: VT, Action: Expand);
1082 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: AVT, MemVT: VT, Action: Expand);
1083 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: AVT, MemVT: VT, Action: Expand);
1084 }
1085 }
1086 for (unsigned IM = (unsigned)ISD::PRE_INC;
1087 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
1088 for (MVT VT : {MVT::i2, MVT::i4}) {
1089 setIndexedLoadAction(IdxModes: IM, VT, Action: Expand);
1090 setIndexedStoreAction(IdxModes: IM, VT, Action: Expand);
1091 setIndexedMaskedLoadAction(IdxMode: IM, VT, Action: Expand);
1092 setIndexedMaskedStoreAction(IdxMode: IM, VT, Action: Expand);
1093 }
1094 }
1095
1096 for (MVT VT : MVT::fp_valuetypes()) {
1097 MVT IntVT = MVT::getIntegerVT(BitWidth: VT.getFixedSizeInBits());
1098 if (IntVT.isValid()) {
1099 setOperationAction(Op: ISD::ATOMIC_SWAP, VT, Action: Promote);
1100 AddPromotedToType(Opc: ISD::ATOMIC_SWAP, OrigVT: VT, DestVT: IntVT);
1101 }
1102 }
1103
1104 // If f16 fma is not natively supported, the value must be promoted to an f64
1105 // (and not to f32!) to prevent double rounding issues.
1106 AddPromotedToType(Opc: ISD::FMA, OrigVT: MVT::f16, DestVT: MVT::f64);
1107 AddPromotedToType(Opc: ISD::STRICT_FMA, OrigVT: MVT::f16, DestVT: MVT::f64);
1108
1109 // Set default actions for various operations.
1110 for (MVT VT : MVT::all_valuetypes()) {
1111 // Default all indexed load / store to expand.
1112 for (unsigned IM = (unsigned)ISD::PRE_INC;
1113 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
1114 setIndexedLoadAction(IdxModes: IM, VT, Action: Expand);
1115 setIndexedStoreAction(IdxModes: IM, VT, Action: Expand);
1116 setIndexedMaskedLoadAction(IdxMode: IM, VT, Action: Expand);
1117 setIndexedMaskedStoreAction(IdxMode: IM, VT, Action: Expand);
1118 }
1119
1120 // Most backends expect to see the node which just returns the value loaded.
1121 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Action: Expand);
1122
1123 // These operations default to expand.
1124 setOperationAction(Ops: {ISD::FGETSIGN, ISD::CONCAT_VECTORS,
1125 ISD::FMINNUM, ISD::FMAXNUM,
1126 ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
1127 ISD::FMINIMUM, ISD::FMAXIMUM,
1128 ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM,
1129 ISD::FMAD, ISD::SMIN,
1130 ISD::SMAX, ISD::UMIN,
1131 ISD::UMAX, ISD::ABS,
1132 ISD::FSHL, ISD::FSHR,
1133 ISD::SADDSAT, ISD::UADDSAT,
1134 ISD::SSUBSAT, ISD::USUBSAT,
1135 ISD::SSHLSAT, ISD::USHLSAT,
1136 ISD::SMULFIX, ISD::SMULFIXSAT,
1137 ISD::UMULFIX, ISD::UMULFIXSAT,
1138 ISD::SDIVFIX, ISD::SDIVFIXSAT,
1139 ISD::UDIVFIX, ISD::UDIVFIXSAT,
1140 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT,
1141 ISD::IS_FPCLASS, ISD::FCBRT,
1142 ISD::FLOG, ISD::FLOG2,
1143 ISD::FLOG10, ISD::FEXP,
1144 ISD::FEXP2, ISD::FEXP10,
1145 ISD::FFLOOR, ISD::FNEARBYINT,
1146 ISD::FCEIL, ISD::FRINT,
1147 ISD::FTRUNC, ISD::FROUNDEVEN,
1148 ISD::FTAN, ISD::FACOS,
1149 ISD::FASIN, ISD::FATAN,
1150 ISD::FCOSH, ISD::FSINH,
1151 ISD::FTANH, ISD::FATAN2,
1152 ISD::FMULADD, ISD::CONVERT_FROM_ARBITRARY_FP},
1153 VT, Action: Expand);
1154
1155 // Overflow operations default to expand
1156 setOperationAction(Ops: {ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO,
1157 ISD::SMULO, ISD::UMULO},
1158 VT, Action: Expand);
1159
1160 // Carry-using overflow operations default to expand.
1161 setOperationAction(Ops: {ISD::UADDO_CARRY, ISD::USUBO_CARRY, ISD::SETCCCARRY,
1162 ISD::SADDO_CARRY, ISD::SSUBO_CARRY},
1163 VT, Action: Expand);
1164
1165 // ADDC/ADDE/SUBC/SUBE default to expand.
1166 setOperationAction(Ops: {ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT,
1167 Action: Expand);
1168
1169 // [US]CMP default to expand
1170 setOperationAction(Ops: {ISD::UCMP, ISD::SCMP}, VT, Action: Expand);
1171
1172 // Halving adds
1173 setOperationAction(
1174 Ops: {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT,
1175 Action: Expand);
1176
1177 // Absolute difference
1178 setOperationAction(Ops: {ISD::ABDS, ISD::ABDU}, VT, Action: Expand);
1179
1180 // Carry-less multiply
1181 setOperationAction(Ops: {ISD::CLMUL, ISD::CLMULR, ISD::CLMULH}, VT, Action: Expand);
1182
1183 // Saturated trunc
1184 setOperationAction(Op: ISD::TRUNCATE_SSAT_S, VT, Action: Expand);
1185 setOperationAction(Op: ISD::TRUNCATE_SSAT_U, VT, Action: Expand);
1186 setOperationAction(Op: ISD::TRUNCATE_USAT_U, VT, Action: Expand);
1187
1188 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
1189 setOperationAction(Ops: {ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT,
1190 Action: Expand);
1191 setOperationAction(Op: ISD::CTLS, VT, Action: Expand);
1192
1193 setOperationAction(Ops: {ISD::BITREVERSE, ISD::PARITY}, VT, Action: Expand);
1194
1195 // These library functions default to expand.
1196 setOperationAction(Ops: {ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP,
1197 ISD::FSINCOS, ISD::FSINCOSPI, ISD::FMODF},
1198 VT, Action: Expand);
1199
1200 // These operations default to expand for vector types.
1201 if (VT.isVector())
1202 setOperationAction(Ops: {ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG,
1203 ISD::ANY_EXTEND_VECTOR_INREG,
1204 ISD::SIGN_EXTEND_VECTOR_INREG,
1205 ISD::ZERO_EXTEND_VECTOR_INREG, ISD::SPLAT_VECTOR,
1206 ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
1207 VT, Action: Expand);
1208
1209 // Constrained floating-point operations default to expand.
1210#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
1211 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
1212#include "llvm/IR/ConstrainedOps.def"
1213
1214 // For most targets @llvm.get.dynamic.area.offset just returns 0.
1215 setOperationAction(Op: ISD::GET_DYNAMIC_AREA_OFFSET, VT, Action: Expand);
1216
1217 // Vector reduction default to expand.
1218 setOperationAction(
1219 Ops: {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD,
1220 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR,
1221 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN,
1222 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX,
1223 ISD::VECREDUCE_FMIN, ISD::VECREDUCE_FMAXIMUM, ISD::VECREDUCE_FMINIMUM,
1224 ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_SEQ_FMUL},
1225 VT, Action: Expand);
1226
1227 // Named vector shuffles default to expand.
1228 setOperationAction(Ops: {ISD::VECTOR_SPLICE_LEFT, ISD::VECTOR_SPLICE_RIGHT}, VT,
1229 Action: Expand);
1230
1231 // Only some target support this vector operation. Most need to expand it.
1232 setOperationAction(Op: ISD::VECTOR_COMPRESS, VT, Action: Expand);
1233
1234 // cttz.elts defaults to expand.
1235 setOperationAction(Ops: {ISD::CTTZ_ELTS, ISD::CTTZ_ELTS_ZERO_POISON}, VT,
1236 Action: Expand);
1237
1238 // VP operations default to expand.
1239#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \
1240 setOperationAction(ISD::SDOPC, VT, Expand);
1241#include "llvm/IR/VPIntrinsics.def"
1242
1243 // Masked vector extracts default to expand.
1244 setOperationAction(Op: ISD::VECTOR_FIND_LAST_ACTIVE, VT, Action: Expand);
1245
1246 setOperationAction(Op: ISD::LOOP_DEPENDENCE_RAW_MASK, VT, Action: Expand);
1247 setOperationAction(Op: ISD::LOOP_DEPENDENCE_WAR_MASK, VT, Action: Expand);
1248
1249 // FP environment operations default to expand.
1250 setOperationAction(Op: ISD::GET_FPENV, VT, Action: Expand);
1251 setOperationAction(Op: ISD::SET_FPENV, VT, Action: Expand);
1252 setOperationAction(Op: ISD::RESET_FPENV, VT, Action: Expand);
1253
1254 setOperationAction(Op: ISD::MSTORE, VT, Action: Expand);
1255 }
1256
1257 // Most targets ignore the @llvm.prefetch intrinsic.
1258 setOperationAction(Op: ISD::PREFETCH, VT: MVT::Other, Action: Expand);
1259
1260 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
1261 setOperationAction(Op: ISD::READCYCLECOUNTER, VT: MVT::i64, Action: Expand);
1262
1263 // Most targets also ignore the @llvm.readsteadycounter intrinsic.
1264 setOperationAction(Op: ISD::READSTEADYCOUNTER, VT: MVT::i64, Action: Expand);
1265
1266 // ConstantFP nodes default to expand. Targets can either change this to
1267 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
1268 // to optimize expansions for certain constants.
1269 setOperationAction(Ops: ISD::ConstantFP,
1270 VTs: {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},
1271 Action: Expand);
1272
1273 // Insert custom handling default for llvm.canonicalize.*.
1274 setOperationAction(Ops: ISD::FCANONICALIZE,
1275 VTs: {MVT::f16, MVT::f32, MVT::f64, MVT::f128}, Action: Expand);
1276
1277 // FIXME: Query RuntimeLibCalls to make the decision.
1278 setOperationAction(Ops: {ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
1279 VTs: {MVT::f32, MVT::f64, MVT::f128}, Action: LibCall);
1280
1281 setOperationAction(Ops: {ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH,
1282 ISD::FSINH, ISD::FTANH, ISD::FATAN2},
1283 VT: MVT::f16, Action: Promote);
1284 // Default ISD::TRAP to expand (which turns it into abort).
1285 setOperationAction(Op: ISD::TRAP, VT: MVT::Other, Action: Expand);
1286
1287 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
1288 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
1289 setOperationAction(Op: ISD::DEBUGTRAP, VT: MVT::Other, Action: Expand);
1290
1291 setOperationAction(Op: ISD::UBSANTRAP, VT: MVT::Other, Action: Expand);
1292
1293 setOperationAction(Op: ISD::GET_FPENV_MEM, VT: MVT::Other, Action: Expand);
1294 setOperationAction(Op: ISD::SET_FPENV_MEM, VT: MVT::Other, Action: Expand);
1295
1296 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
1297 setOperationAction(Op: ISD::GET_FPMODE, VT, Action: Expand);
1298 setOperationAction(Op: ISD::SET_FPMODE, VT, Action: Expand);
1299 }
1300 setOperationAction(Op: ISD::RESET_FPMODE, VT: MVT::Other, Action: Expand);
1301
1302 // This one by default will call __clear_cache unless the target
1303 // wants something different.
1304 setOperationAction(Op: ISD::CLEAR_CACHE, VT: MVT::Other, Action: LibCall);
1305
1306 // By default, STACKADDRESS nodes are expanded like STACKSAVE nodes.
1307 // On SPARC targets, custom lowering is required.
1308 setOperationAction(Op: ISD::STACKADDRESS, VT: MVT::Other, Action: Expand);
1309}
1310
1311MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
1312 EVT) const {
1313 return MVT::getIntegerVT(BitWidth: DL.getPointerSizeInBits(AS: 0));
1314}
1315
1316EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,
1317 const DataLayout &DL) const {
1318 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
1319 if (LHSTy.isVector())
1320 return LHSTy;
1321 MVT ShiftVT = getScalarShiftAmountTy(DL, LHSTy);
1322 // If any possible shift value won't fit in the prefered type, just use
1323 // something safe. Assume it will be legalized when the shift is expanded.
1324 if (ShiftVT.getSizeInBits() < Log2_32_Ceil(Value: LHSTy.getSizeInBits()))
1325 ShiftVT = MVT::i32;
1326 assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) &&
1327 "ShiftVT is still too small!");
1328 return ShiftVT;
1329}
1330
1331bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
1332 assert(isTypeLegal(VT));
1333 switch (Op) {
1334 default:
1335 return false;
1336 case ISD::SDIV:
1337 case ISD::UDIV:
1338 case ISD::SREM:
1339 case ISD::UREM:
1340 return true;
1341 }
1342}
1343
1344bool TargetLoweringBase::isFreeAddrSpaceCast(unsigned SrcAS,
1345 unsigned DestAS) const {
1346 return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
1347}
1348
1349unsigned TargetLoweringBase::getBitWidthForCttzElements(
1350 Type *RetTy, ElementCount EC, bool ZeroIsPoison,
1351 const ConstantRange *VScaleRange) const {
1352 // Find the smallest "sensible" element type to use for the expansion.
1353 ConstantRange CR(APInt(64, EC.getKnownMinValue()));
1354 if (EC.isScalable())
1355 CR = CR.umul_sat(Other: *VScaleRange);
1356
1357 if (ZeroIsPoison)
1358 CR = CR.subtract(CI: APInt(64, 1));
1359
1360 unsigned EltWidth = RetTy->getScalarSizeInBits();
1361 EltWidth = std::min(a: EltWidth, b: CR.getActiveBits());
1362 EltWidth = std::max(a: llvm::bit_ceil(Value: EltWidth), b: (unsigned)8);
1363
1364 return EltWidth;
1365}
1366
1367void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
1368 // If the command-line option was specified, ignore this request.
1369 if (!JumpIsExpensiveOverride.getNumOccurrences())
1370 JumpIsExpensive = isExpensive;
1371}
1372
1373TargetLoweringBase::LegalizeKind
1374TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
1375 // If this is a simple type, use the ComputeRegisterProp mechanism.
1376 if (VT.isSimple()) {
1377 MVT SVT = VT.getSimpleVT();
1378 assert((unsigned)SVT.SimpleTy < std::size(TransformToType));
1379 MVT NVT = TransformToType[SVT.SimpleTy];
1380 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(VT: SVT);
1381
1382 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
1383 LA == TypeSoftPromoteHalf ||
1384 (NVT.isVector() ||
1385 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
1386 "Promote may not follow Expand or Promote");
1387
1388 if (LA == TypeSplitVector)
1389 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
1390 if (LA == TypeScalarizeVector)
1391 return LegalizeKind(LA, SVT.getVectorElementType());
1392 return LegalizeKind(LA, NVT);
1393 }
1394
1395 // Handle Extended Scalar Types.
1396 if (!VT.isVector()) {
1397 assert(VT.isInteger() && "Float types must be simple");
1398 unsigned BitSize = VT.getSizeInBits();
1399 // First promote to a power-of-two size, then expand if necessary.
1400 if (BitSize < 8 || !isPowerOf2_32(Value: BitSize)) {
1401 EVT NVT = VT.getRoundIntegerType(Context);
1402 assert(NVT != VT && "Unable to round integer VT");
1403 LegalizeKind NextStep = getTypeConversion(Context, VT: NVT);
1404 // Avoid multi-step promotion.
1405 if (NextStep.first == TypePromoteInteger)
1406 return NextStep;
1407 // Return rounded integer type.
1408 return LegalizeKind(TypePromoteInteger, NVT);
1409 }
1410
1411 return LegalizeKind(TypeExpandInteger,
1412 EVT::getIntegerVT(Context, BitWidth: VT.getSizeInBits() / 2));
1413 }
1414
1415 // Handle vector types.
1416 ElementCount NumElts = VT.getVectorElementCount();
1417 EVT EltVT = VT.getVectorElementType();
1418
1419 // Vectors with only one element are always scalarized.
1420 if (NumElts.isScalar())
1421 return LegalizeKind(TypeScalarizeVector, EltVT);
1422
1423 // Try to widen vector elements until the element type is a power of two and
1424 // promote it to a legal type later on, for example:
1425 // <3 x i8> -> <4 x i8> -> <4 x i32>
1426 if (EltVT.isInteger()) {
1427 // Vectors with a number of elements that is not a power of two are always
1428 // widened, for example <3 x i8> -> <4 x i8>.
1429 if (!VT.isPow2VectorType()) {
1430 NumElts = NumElts.coefficientNextPowerOf2();
1431 EVT NVT = EVT::getVectorVT(Context, VT: EltVT, EC: NumElts);
1432 return LegalizeKind(TypeWidenVector, NVT);
1433 }
1434
1435 // Examine the element type.
1436 LegalizeKind LK = getTypeConversion(Context, VT: EltVT);
1437
1438 // If type is to be expanded, split the vector.
1439 // <4 x i140> -> <2 x i140>
1440 if (LK.first == TypeExpandInteger) {
1441 if (NumElts.isScalable() && NumElts.getKnownMinValue() == 1)
1442 return LegalizeKind(TypeScalarizeScalableVector, EltVT);
1443 return LegalizeKind(TypeSplitVector,
1444 VT.getHalfNumVectorElementsVT(Context));
1445 }
1446
1447 // Promote the integer element types until a legal vector type is found
1448 // or until the element integer type is too big. If a legal type was not
1449 // found, fallback to the usual mechanism of widening/splitting the
1450 // vector.
1451 EVT OldEltVT = EltVT;
1452 while (true) {
1453 // Increase the bitwidth of the element to the next pow-of-two
1454 // (which is greater than 8 bits).
1455 EltVT = EVT::getIntegerVT(Context, BitWidth: 1 + EltVT.getSizeInBits())
1456 .getRoundIntegerType(Context);
1457
1458 // Stop trying when getting a non-simple element type.
1459 // Note that vector elements may be greater than legal vector element
1460 // types. Example: X86 XMM registers hold 64bit element on 32bit
1461 // systems.
1462 if (!EltVT.isSimple())
1463 break;
1464
1465 // Build a new vector type and check if it is legal.
1466 MVT NVT = MVT::getVectorVT(VT: EltVT.getSimpleVT(), EC: NumElts);
1467 // Found a legal promoted vector type.
1468 if (NVT != MVT() && ValueTypeActions.getTypeAction(VT: NVT) == TypeLegal)
1469 return LegalizeKind(TypePromoteInteger,
1470 EVT::getVectorVT(Context, VT: EltVT, EC: NumElts));
1471 }
1472
1473 // Reset the type to the unexpanded type if we did not find a legal vector
1474 // type with a promoted vector element type.
1475 EltVT = OldEltVT;
1476 }
1477
1478 // Try to widen the vector until a legal type is found.
1479 // If there is no wider legal type, split the vector.
1480 while (true) {
1481 // Round up to the next power of 2.
1482 NumElts = NumElts.coefficientNextPowerOf2();
1483
1484 // If there is no simple vector type with this many elements then there
1485 // cannot be a larger legal vector type. Note that this assumes that
1486 // there are no skipped intermediate vector types in the simple types.
1487 if (!EltVT.isSimple())
1488 break;
1489 MVT LargerVector = MVT::getVectorVT(VT: EltVT.getSimpleVT(), EC: NumElts);
1490 if (LargerVector == MVT())
1491 break;
1492
1493 // If this type is legal then widen the vector.
1494 if (ValueTypeActions.getTypeAction(VT: LargerVector) == TypeLegal)
1495 return LegalizeKind(TypeWidenVector, LargerVector);
1496 }
1497
1498 // Widen odd vectors to next power of two.
1499 if (!VT.isPow2VectorType()) {
1500 EVT NVT = VT.getPow2VectorType(Context);
1501 return LegalizeKind(TypeWidenVector, NVT);
1502 }
1503
1504 if (VT.getVectorElementCount() == ElementCount::getScalable(MinVal: 1))
1505 return LegalizeKind(TypeScalarizeScalableVector, EltVT);
1506
1507 // Vectors with illegal element types are expanded.
1508 EVT NVT = EVT::getVectorVT(Context, VT: EltVT,
1509 EC: VT.getVectorElementCount().divideCoefficientBy(RHS: 2));
1510 return LegalizeKind(TypeSplitVector, NVT);
1511}
1512
1513static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1514 unsigned &NumIntermediates,
1515 MVT &RegisterVT,
1516 TargetLoweringBase *TLI) {
1517 // Figure out the right, legal destination reg to copy into.
1518 ElementCount EC = VT.getVectorElementCount();
1519 MVT EltTy = VT.getVectorElementType();
1520
1521 unsigned NumVectorRegs = 1;
1522
1523 // Scalable vectors cannot be scalarized, so splitting or widening is
1524 // required.
1525 if (VT.isScalableVector() && !isPowerOf2_32(Value: EC.getKnownMinValue()))
1526 llvm_unreachable(
1527 "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1528
1529 // FIXME: We don't support non-power-of-2-sized vectors for now.
1530 // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1531 if (!isPowerOf2_32(Value: EC.getKnownMinValue())) {
1532 // Split EC to unit size (scalable property is preserved).
1533 NumVectorRegs = EC.getKnownMinValue();
1534 EC = ElementCount::getFixed(MinVal: 1);
1535 }
1536
1537 // Divide the input until we get to a supported size. This will
1538 // always end up with an EC that represent a scalar or a scalable
1539 // scalar.
1540 while (EC.getKnownMinValue() > 1 &&
1541 !TLI->isTypeLegal(VT: MVT::getVectorVT(VT: EltTy, EC))) {
1542 EC = EC.divideCoefficientBy(RHS: 2);
1543 NumVectorRegs <<= 1;
1544 }
1545
1546 NumIntermediates = NumVectorRegs;
1547
1548 MVT NewVT = MVT::getVectorVT(VT: EltTy, EC);
1549 if (!TLI->isTypeLegal(VT: NewVT))
1550 NewVT = EltTy;
1551 IntermediateVT = NewVT;
1552
1553 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
1554
1555 // Convert sizes such as i33 to i64.
1556 LaneSizeInBits = llvm::bit_ceil(Value: LaneSizeInBits);
1557
1558 MVT DestVT = TLI->getRegisterType(VT: NewVT);
1559 RegisterVT = DestVT;
1560 if (EVT(DestVT).bitsLT(VT: NewVT)) // Value is expanded, e.g. i64 -> i16.
1561 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1562
1563 // Otherwise, promotion or legal types use the same number of registers as
1564 // the vector decimated to the appropriate level.
1565 return NumVectorRegs;
1566}
1567
1568/// isLegalRC - Return true if the value types that can be represented by the
1569/// specified register class are all legal.
1570bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
1571 const TargetRegisterClass &RC) const {
1572 for (const auto *I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1573 if (isTypeLegal(VT: *I))
1574 return true;
1575 return false;
1576}
1577
1578/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1579/// sequence of memory operands that is recognized by PrologEpilogInserter.
1580MachineBasicBlock *
1581TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
1582 MachineBasicBlock *MBB) const {
1583 MachineInstr *MI = &InitialMI;
1584 MachineFunction &MF = *MI->getMF();
1585 MachineFrameInfo &MFI = MF.getFrameInfo();
1586
1587 // We're handling multiple types of operands here:
1588 // PATCHPOINT MetaArgs - live-in, read only, direct
1589 // STATEPOINT Deopt Spill - live-through, read only, indirect
1590 // STATEPOINT Deopt Alloca - live-through, read only, direct
1591 // (We're currently conservative and mark the deopt slots read/write in
1592 // practice.)
1593 // STATEPOINT GC Spill - live-through, read/write, indirect
1594 // STATEPOINT GC Alloca - live-through, read/write, direct
1595 // The live-in vs live-through is handled already (the live through ones are
1596 // all stack slots), but we need to handle the different type of stackmap
1597 // operands and memory effects here.
1598
1599 if (llvm::none_of(Range: MI->operands(),
1600 P: [](MachineOperand &Operand) { return Operand.isFI(); }))
1601 return MBB;
1602
1603 MachineInstrBuilder MIB = BuildMI(MF, MIMD: MI->getDebugLoc(), MCID: MI->getDesc());
1604
1605 // Inherit previous memory operands.
1606 MIB.cloneMemRefs(OtherMI: *MI);
1607
1608 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1609 MachineOperand &MO = MI->getOperand(i);
1610 if (!MO.isFI()) {
1611 // Index of Def operand this Use it tied to.
1612 // Since Defs are coming before Uses, if Use is tied, then
1613 // index of Def must be smaller that index of that Use.
1614 // Also, Defs preserve their position in new MI.
1615 unsigned TiedTo = i;
1616 if (MO.isReg() && MO.isTied())
1617 TiedTo = MI->findTiedOperandIdx(OpIdx: i);
1618 MIB.add(MO);
1619 if (TiedTo < i)
1620 MIB->tieOperands(DefIdx: TiedTo, UseIdx: MIB->getNumOperands() - 1);
1621 continue;
1622 }
1623
1624 // foldMemoryOperand builds a new MI after replacing a single FI operand
1625 // with the canonical set of five x86 addressing-mode operands.
1626 int FI = MO.getIndex();
1627
1628 // Add frame index operands recognized by stackmaps.cpp
1629 if (MFI.isStatepointSpillSlotObjectIndex(ObjectIdx: FI)) {
1630 // indirect-mem-ref tag, size, #FI, offset.
1631 // Used for spills inserted by StatepointLowering. This codepath is not
1632 // used for patchpoints/stackmaps at all, for these spilling is done via
1633 // foldMemoryOperand callback only.
1634 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1635 MIB.addImm(Val: StackMaps::IndirectMemRefOp);
1636 MIB.addImm(Val: MFI.getObjectSize(ObjectIdx: FI));
1637 MIB.add(MO);
1638 MIB.addImm(Val: 0);
1639 } else {
1640 // direct-mem-ref tag, #FI, offset.
1641 // Used by patchpoint, and direct alloca arguments to statepoints
1642 MIB.addImm(Val: StackMaps::DirectMemRefOp);
1643 MIB.add(MO);
1644 MIB.addImm(Val: 0);
1645 }
1646
1647 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1648
1649 // Add a new memory operand for this FI.
1650 assert(MFI.getObjectOffset(FI) != -1);
1651
1652 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1653 // PATCHPOINT should be updated to do the same. (TODO)
1654 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1655 auto Flags = MachineMemOperand::MOLoad;
1656 MachineMemOperand *MMO = MF.getMachineMemOperand(
1657 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI), F: Flags,
1658 Size: MF.getDataLayout().getPointerSize(), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
1659 MIB->addMemOperand(MF, MO: MMO);
1660 }
1661 }
1662 MBB->insert(I: MachineBasicBlock::iterator(MI), MI: MIB);
1663 MI->eraseFromParent();
1664 return MBB;
1665}
1666
1667/// findRepresentativeClass - Return the largest legal super-reg register class
1668/// of the register class for the specified type and its associated "cost".
1669// This function is in TargetLowering because it uses RegClassForVT which would
1670// need to be moved to TargetRegisterInfo and would necessitate moving
1671// isTypeLegal over as well - a massive change that would just require
1672// TargetLowering having a TargetRegisterInfo class member that it would use.
1673std::pair<const TargetRegisterClass *, uint8_t>
1674TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1675 MVT VT) const {
1676 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1677 if (!RC)
1678 return std::make_pair(x&: RC, y: 0);
1679
1680 // Compute the set of all super-register classes.
1681 BitVector SuperRegRC(TRI->getNumRegClasses());
1682 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1683 SuperRegRC.setBitsInMask(Mask: RCI.getMask());
1684
1685 // Find the first legal register class with the largest spill size.
1686 const TargetRegisterClass *BestRC = RC;
1687 for (unsigned i : SuperRegRC.set_bits()) {
1688 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1689 // We want the largest possible spill size.
1690 if (TRI->getSpillSize(RC: *SuperRC) <= TRI->getSpillSize(RC: *BestRC))
1691 continue;
1692 if (!isLegalRC(TRI: *TRI, RC: *SuperRC))
1693 continue;
1694 BestRC = SuperRC;
1695 }
1696 return std::make_pair(x&: BestRC, y: 1);
1697}
1698
1699/// computeRegisterProperties - Once all of the register classes are added,
1700/// this allows us to compute derived properties we expose.
1701void TargetLoweringBase::computeRegisterProperties(
1702 const TargetRegisterInfo *TRI) {
1703 // Everything defaults to needing one register.
1704 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1705 NumRegistersForVT[i] = 1;
1706 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1707 }
1708 // ...except isVoid, which doesn't need any registers.
1709 NumRegistersForVT[MVT::isVoid] = 0;
1710
1711 // Find the largest integer register class.
1712 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1713 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1714 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1715
1716 // Every integer value type larger than this largest register takes twice as
1717 // many registers to represent as the previous ValueType.
1718 for (unsigned ExpandedReg = LargestIntReg + 1;
1719 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1720 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1721 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1722 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1723 ValueTypeActions.setTypeAction(VT: (MVT::SimpleValueType)ExpandedReg,
1724 Action: TypeExpandInteger);
1725 }
1726
1727 // Inspect all of the ValueType's smaller than the largest integer
1728 // register to see which ones need promotion.
1729 unsigned LegalIntReg = LargestIntReg;
1730 for (unsigned IntReg = LargestIntReg - 1;
1731 IntReg >= (unsigned)MVT::i1; --IntReg) {
1732 MVT IVT = (MVT::SimpleValueType)IntReg;
1733 if (isTypeLegal(VT: IVT)) {
1734 LegalIntReg = IntReg;
1735 } else {
1736 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1737 (MVT::SimpleValueType)LegalIntReg;
1738 ValueTypeActions.setTypeAction(VT: IVT, Action: TypePromoteInteger);
1739 }
1740 }
1741
1742 // ppcf128 type is really two f64's.
1743 if (!isTypeLegal(VT: MVT::ppcf128)) {
1744 if (isTypeLegal(VT: MVT::f64)) {
1745 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1746 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1747 TransformToType[MVT::ppcf128] = MVT::f64;
1748 ValueTypeActions.setTypeAction(VT: MVT::ppcf128, Action: TypeExpandFloat);
1749 } else {
1750 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1751 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1752 TransformToType[MVT::ppcf128] = MVT::i128;
1753 ValueTypeActions.setTypeAction(VT: MVT::ppcf128, Action: TypeSoftenFloat);
1754 }
1755 }
1756
1757 // Decide how to handle f128. If the target does not have native f128 support,
1758 // expand it to i128 and we will be generating soft float library calls.
1759 if (!isTypeLegal(VT: MVT::f128)) {
1760 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1761 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1762 TransformToType[MVT::f128] = MVT::i128;
1763 ValueTypeActions.setTypeAction(VT: MVT::f128, Action: TypeSoftenFloat);
1764 }
1765
1766 // Decide how to handle f80. If the target does not have native f80 support,
1767 // expand it to i96 and we will be generating soft float library calls.
1768 if (!isTypeLegal(VT: MVT::f80)) {
1769 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];
1770 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];
1771 TransformToType[MVT::f80] = MVT::i32;
1772 ValueTypeActions.setTypeAction(VT: MVT::f80, Action: TypeSoftenFloat);
1773 }
1774
1775 // Decide how to handle f64. If the target does not have native f64 support,
1776 // expand it to i64 and we will be generating soft float library calls.
1777 if (!isTypeLegal(VT: MVT::f64)) {
1778 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1779 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1780 TransformToType[MVT::f64] = MVT::i64;
1781 ValueTypeActions.setTypeAction(VT: MVT::f64, Action: TypeSoftenFloat);
1782 }
1783
1784 // Decide how to handle f32. If the target does not have native f32 support,
1785 // expand it to i32 and we will be generating soft float library calls.
1786 if (!isTypeLegal(VT: MVT::f32)) {
1787 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1788 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1789 TransformToType[MVT::f32] = MVT::i32;
1790 ValueTypeActions.setTypeAction(VT: MVT::f32, Action: TypeSoftenFloat);
1791 }
1792
1793 // Decide how to handle f16. If the target does not have native f16 support,
1794 // promote it to f32, because there are no f16 library calls (except for
1795 // conversions).
1796 if (!isTypeLegal(VT: MVT::f16)) {
1797 // Allow targets to control how we legalize half.
1798 bool UseFPRegsForHalfType = useFPRegsForHalfType();
1799
1800 if (!UseFPRegsForHalfType) {
1801 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1802 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1803 } else {
1804 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1805 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1806 }
1807 TransformToType[MVT::f16] = MVT::f32;
1808 ValueTypeActions.setTypeAction(VT: MVT::f16, Action: TypeSoftPromoteHalf);
1809 }
1810
1811 // Decide how to handle bf16. If the target does not have native bf16 support,
1812 // promote it to f32, because there are no bf16 library calls (except for
1813 // converting from f32 to bf16).
1814 if (!isTypeLegal(VT: MVT::bf16)) {
1815 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];
1816 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];
1817 TransformToType[MVT::bf16] = MVT::f32;
1818 ValueTypeActions.setTypeAction(VT: MVT::bf16, Action: TypeSoftPromoteHalf);
1819 }
1820
1821 // Loop over all of the vector value types to see which need transformations.
1822 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1823 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1824 MVT VT = (MVT::SimpleValueType) i;
1825 if (isTypeLegal(VT))
1826 continue;
1827
1828 MVT EltVT = VT.getVectorElementType();
1829 ElementCount EC = VT.getVectorElementCount();
1830 bool IsLegalWiderType = false;
1831 bool IsScalable = VT.isScalableVector();
1832 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1833 switch (PreferredAction) {
1834 case TypePromoteInteger: {
1835 MVT::SimpleValueType EndVT = IsScalable ?
1836 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :
1837 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;
1838 // Try to promote the elements of integer vectors. If no legal
1839 // promotion was found, fall through to the widen-vector method.
1840 for (unsigned nVT = i + 1;
1841 (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1842 MVT SVT = (MVT::SimpleValueType) nVT;
1843 // Promote vectors of integers to vectors with the same number
1844 // of elements, with a wider element type.
1845 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1846 SVT.getVectorElementCount() == EC && isTypeLegal(VT: SVT)) {
1847 TransformToType[i] = SVT;
1848 RegisterTypeForVT[i] = SVT;
1849 NumRegistersForVT[i] = 1;
1850 ValueTypeActions.setTypeAction(VT, Action: TypePromoteInteger);
1851 IsLegalWiderType = true;
1852 break;
1853 }
1854 }
1855 if (IsLegalWiderType)
1856 break;
1857 [[fallthrough]];
1858 }
1859
1860 case TypeWidenVector:
1861 if (isPowerOf2_32(Value: EC.getKnownMinValue())) {
1862 // Try to widen the vector.
1863 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1864 MVT SVT = (MVT::SimpleValueType) nVT;
1865 if (SVT.getVectorElementType() == EltVT &&
1866 SVT.isScalableVector() == IsScalable &&
1867 SVT.getVectorElementCount().getKnownMinValue() >
1868 EC.getKnownMinValue() &&
1869 isTypeLegal(VT: SVT)) {
1870 TransformToType[i] = SVT;
1871 RegisterTypeForVT[i] = SVT;
1872 NumRegistersForVT[i] = 1;
1873 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1874 IsLegalWiderType = true;
1875 break;
1876 }
1877 }
1878 if (IsLegalWiderType)
1879 break;
1880 } else {
1881 // Only widen to the next power of 2 to keep consistency with EVT.
1882 MVT NVT = VT.getPow2VectorType();
1883 if (isTypeLegal(VT: NVT)) {
1884 TransformToType[i] = NVT;
1885 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1886 RegisterTypeForVT[i] = NVT;
1887 NumRegistersForVT[i] = 1;
1888 break;
1889 }
1890 }
1891 [[fallthrough]];
1892
1893 case TypeSplitVector:
1894 case TypeScalarizeVector: {
1895 MVT IntermediateVT;
1896 MVT RegisterVT;
1897 unsigned NumIntermediates;
1898 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1899 NumIntermediates, RegisterVT, TLI: this);
1900 NumRegistersForVT[i] = NumRegisters;
1901 assert(NumRegistersForVT[i] == NumRegisters &&
1902 "NumRegistersForVT size cannot represent NumRegisters!");
1903 RegisterTypeForVT[i] = RegisterVT;
1904
1905 MVT NVT = VT.getPow2VectorType();
1906 if (NVT == VT) {
1907 // Type is already a power of 2. The default action is to split.
1908 TransformToType[i] = MVT::Other;
1909 if (PreferredAction == TypeScalarizeVector)
1910 ValueTypeActions.setTypeAction(VT, Action: TypeScalarizeVector);
1911 else if (PreferredAction == TypeSplitVector)
1912 ValueTypeActions.setTypeAction(VT, Action: TypeSplitVector);
1913 else if (EC.getKnownMinValue() > 1)
1914 ValueTypeActions.setTypeAction(VT, Action: TypeSplitVector);
1915 else
1916 ValueTypeActions.setTypeAction(VT, Action: EC.isScalable()
1917 ? TypeScalarizeScalableVector
1918 : TypeScalarizeVector);
1919 } else {
1920 TransformToType[i] = NVT;
1921 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1922 }
1923 break;
1924 }
1925 default:
1926 llvm_unreachable("Unknown vector legalization action!");
1927 }
1928 }
1929
1930 // Determine the 'representative' register class for each value type.
1931 // An representative register class is the largest (meaning one which is
1932 // not a sub-register class / subreg register class) legal register class for
1933 // a group of value types. For example, on i386, i8, i16, and i32
1934 // representative would be GR32; while on x86_64 it's GR64.
1935 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1936 const TargetRegisterClass* RRC;
1937 uint8_t Cost;
1938 std::tie(args&: RRC, args&: Cost) = findRepresentativeClass(TRI, VT: (MVT::SimpleValueType)i);
1939 RepRegClassForVT[i] = RRC;
1940 RepRegClassCostForVT[i] = Cost;
1941 }
1942}
1943
1944EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1945 EVT VT) const {
1946 assert(!VT.isVector() && "No default SetCC type for vectors!");
1947 return getPointerTy(DL).SimpleTy;
1948}
1949
1950MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1951 return MVT::i32; // return the default value
1952}
1953
1954/// getVectorTypeBreakdown - Vector types are broken down into some number of
1955/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1956/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1957/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1958///
1959/// This method returns the number of registers needed, and the VT for each
1960/// register. It also returns the VT and quantity of the intermediate values
1961/// before they are promoted/expanded.
1962unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context,
1963 EVT VT, EVT &IntermediateVT,
1964 unsigned &NumIntermediates,
1965 MVT &RegisterVT) const {
1966 ElementCount EltCnt = VT.getVectorElementCount();
1967
1968 // If there is a wider vector type with the same element type as this one,
1969 // or a promoted vector type that has the same number of elements which
1970 // are wider, then we should convert to that legal vector type.
1971 // This handles things like <2 x float> -> <4 x float> and
1972 // <4 x i1> -> <4 x i32>.
1973 LegalizeTypeAction TA = getTypeAction(Context, VT);
1974 if (!EltCnt.isScalar() &&
1975 (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1976 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1977 if (isTypeLegal(VT: RegisterEVT)) {
1978 IntermediateVT = RegisterEVT;
1979 RegisterVT = RegisterEVT.getSimpleVT();
1980 NumIntermediates = 1;
1981 return 1;
1982 }
1983 }
1984
1985 // Figure out the right, legal destination reg to copy into.
1986 EVT EltTy = VT.getVectorElementType();
1987
1988 unsigned NumVectorRegs = 1;
1989
1990 // Scalable vectors cannot be scalarized, so handle the legalisation of the
1991 // types like done elsewhere in SelectionDAG.
1992 if (EltCnt.isScalable()) {
1993 LegalizeKind LK;
1994 EVT PartVT = VT;
1995 do {
1996 // Iterate until we've found a legal (part) type to hold VT.
1997 LK = getTypeConversion(Context, VT: PartVT);
1998 PartVT = LK.second;
1999 } while (LK.first != TypeLegal);
2000
2001 if (!PartVT.isVector()) {
2002 report_fatal_error(
2003 reason: "Don't know how to legalize this scalable vector type");
2004 }
2005
2006 NumIntermediates =
2007 divideCeil(Numerator: VT.getVectorElementCount().getKnownMinValue(),
2008 Denominator: PartVT.getVectorElementCount().getKnownMinValue());
2009 IntermediateVT = PartVT;
2010 RegisterVT = getRegisterType(Context, VT: IntermediateVT);
2011 return NumIntermediates;
2012 }
2013
2014 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally
2015 // we could break down into LHS/RHS like LegalizeDAG does.
2016 if (!isPowerOf2_32(Value: EltCnt.getKnownMinValue())) {
2017 NumVectorRegs = EltCnt.getKnownMinValue();
2018 EltCnt = ElementCount::getFixed(MinVal: 1);
2019 }
2020
2021 // Divide the input until we get to a supported size. This will always
2022 // end with a scalar if the target doesn't support vectors.
2023 while (EltCnt.getKnownMinValue() > 1 &&
2024 !isTypeLegal(VT: EVT::getVectorVT(Context, VT: EltTy, EC: EltCnt))) {
2025 EltCnt = EltCnt.divideCoefficientBy(RHS: 2);
2026 NumVectorRegs <<= 1;
2027 }
2028
2029 NumIntermediates = NumVectorRegs;
2030
2031 EVT NewVT = EVT::getVectorVT(Context, VT: EltTy, EC: EltCnt);
2032 if (!isTypeLegal(VT: NewVT))
2033 NewVT = EltTy;
2034 IntermediateVT = NewVT;
2035
2036 MVT DestVT = getRegisterType(Context, VT: NewVT);
2037 RegisterVT = DestVT;
2038
2039 if (EVT(DestVT).bitsLT(VT: NewVT)) { // Value is expanded, e.g. i64 -> i16.
2040 TypeSize NewVTSize = NewVT.getSizeInBits();
2041 // Convert sizes such as i33 to i64.
2042 if (!llvm::has_single_bit<uint32_t>(Value: NewVTSize.getKnownMinValue()))
2043 NewVTSize = NewVTSize.coefficientNextPowerOf2();
2044 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
2045 }
2046
2047 // Otherwise, promotion or legal types use the same number of registers as
2048 // the vector decimated to the appropriate level.
2049 return NumVectorRegs;
2050}
2051
2052bool TargetLoweringBase::isSuitableForJumpTable(const SwitchInst *SI,
2053 uint64_t NumCases,
2054 uint64_t Range,
2055 ProfileSummaryInfo *PSI,
2056 BlockFrequencyInfo *BFI) const {
2057 // FIXME: This function check the maximum table size and density, but the
2058 // minimum size is not checked. It would be nice if the minimum size is
2059 // also combined within this function. Currently, the minimum size check is
2060 // performed in findJumpTable() in SelectionDAGBuiler and
2061 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
2062 const bool OptForSize =
2063 llvm::shouldOptimizeForSize(BB: SI->getParent(), PSI, BFI);
2064 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
2065 const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
2066
2067 // Check whether the number of cases is small enough and
2068 // the range is dense enough for a jump table.
2069 return (OptForSize || Range <= MaxJumpTableSize) &&
2070 (NumCases * 100 >= Range * MinDensity);
2071}
2072
2073MVT TargetLoweringBase::getPreferredSwitchConditionType(LLVMContext &Context,
2074 EVT ConditionVT) const {
2075 return getRegisterType(Context, VT: ConditionVT);
2076}
2077
2078/// Get the EVTs and ArgFlags collections that represent the legalized return
2079/// type of the given function. This does not require a DAG or a return value,
2080/// and is suitable for use before any DAGs for the function are constructed.
2081/// TODO: Move this out of TargetLowering.cpp.
2082void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType,
2083 AttributeList attr,
2084 SmallVectorImpl<ISD::OutputArg> &Outs,
2085 const TargetLowering &TLI, const DataLayout &DL) {
2086 SmallVector<Type *, 4> Types;
2087 ComputeValueTypes(DL, Ty: ReturnType, Types);
2088 unsigned NumValues = Types.size();
2089 if (NumValues == 0) return;
2090
2091 for (Type *Ty : Types) {
2092 EVT VT = TLI.getValueType(DL, Ty);
2093 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
2094
2095 if (attr.hasRetAttr(Kind: Attribute::SExt))
2096 ExtendKind = ISD::SIGN_EXTEND;
2097 else if (attr.hasRetAttr(Kind: Attribute::ZExt))
2098 ExtendKind = ISD::ZERO_EXTEND;
2099
2100 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
2101 VT = TLI.getTypeForExtReturn(Context&: ReturnType->getContext(), VT, ExtendKind);
2102
2103 unsigned NumParts =
2104 TLI.getNumRegistersForCallingConv(Context&: ReturnType->getContext(), CC, VT);
2105 MVT PartVT =
2106 TLI.getRegisterTypeForCallingConv(Context&: ReturnType->getContext(), CC, VT);
2107
2108 // 'inreg' on function refers to return value
2109 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
2110 if (attr.hasRetAttr(Kind: Attribute::InReg))
2111 Flags.setInReg();
2112
2113 // Propagate extension type if any
2114 if (attr.hasRetAttr(Kind: Attribute::SExt))
2115 Flags.setSExt();
2116 else if (attr.hasRetAttr(Kind: Attribute::ZExt))
2117 Flags.setZExt();
2118
2119 for (unsigned i = 0; i < NumParts; ++i)
2120 Outs.push_back(Elt: ISD::OutputArg(Flags, PartVT, VT, Ty, 0, 0));
2121 }
2122}
2123
2124Align TargetLoweringBase::getByValTypeAlignment(Type *Ty,
2125 const DataLayout &DL) const {
2126 return DL.getABITypeAlign(Ty);
2127}
2128
2129bool TargetLoweringBase::allowsMemoryAccessForAlignment(
2130 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
2131 Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const {
2132 // Check if the specified alignment is sufficient based on the data layout.
2133 // TODO: While using the data layout works in practice, a better solution
2134 // would be to implement this check directly (make this a virtual function).
2135 // For example, the ABI alignment may change based on software platform while
2136 // this function should only be affected by hardware implementation.
2137 Type *Ty = VT.getTypeForEVT(Context);
2138 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {
2139 // Assume that an access that meets the ABI-specified alignment is fast.
2140 if (Fast != nullptr)
2141 *Fast = 1;
2142 return true;
2143 }
2144
2145 // This is a misaligned access.
2146 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
2147}
2148
2149bool TargetLoweringBase::allowsMemoryAccessForAlignment(
2150 LLVMContext &Context, const DataLayout &DL, EVT VT,
2151 const MachineMemOperand &MMO, unsigned *Fast) const {
2152 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace: MMO.getAddrSpace(),
2153 Alignment: MMO.getAlign(), Flags: MMO.getFlags(), Fast);
2154}
2155
2156bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
2157 const DataLayout &DL, EVT VT,
2158 unsigned AddrSpace, Align Alignment,
2159 MachineMemOperand::Flags Flags,
2160 unsigned *Fast) const {
2161 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
2162 Flags, Fast);
2163}
2164
2165bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
2166 const DataLayout &DL, EVT VT,
2167 const MachineMemOperand &MMO,
2168 unsigned *Fast) const {
2169 return allowsMemoryAccess(Context, DL, VT, AddrSpace: MMO.getAddrSpace(), Alignment: MMO.getAlign(),
2170 Flags: MMO.getFlags(), Fast);
2171}
2172
2173bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
2174 const DataLayout &DL, LLT Ty,
2175 const MachineMemOperand &MMO,
2176 unsigned *Fast) const {
2177 EVT VT = getApproximateEVTForLLT(Ty, Ctx&: Context);
2178 return allowsMemoryAccess(Context, DL, VT, AddrSpace: MMO.getAddrSpace(), Alignment: MMO.getAlign(),
2179 Flags: MMO.getFlags(), Fast);
2180}
2181
2182unsigned TargetLoweringBase::getMaxStoresPerMemset(bool OptSize) const {
2183 if (MaxStoresPerMemsetOverride > 0)
2184 return MaxStoresPerMemsetOverride;
2185
2186 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
2187}
2188
2189unsigned TargetLoweringBase::getMaxStoresPerMemcpy(bool OptSize) const {
2190 if (MaxStoresPerMemcpyOverride > 0)
2191 return MaxStoresPerMemcpyOverride;
2192
2193 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
2194}
2195
2196unsigned TargetLoweringBase::getMaxStoresPerMemmove(bool OptSize) const {
2197 if (MaxStoresPerMemmoveOverride > 0)
2198 return MaxStoresPerMemmoveOverride;
2199
2200 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
2201}
2202
2203//===----------------------------------------------------------------------===//
2204// TargetTransformInfo Helpers
2205//===----------------------------------------------------------------------===//
2206
2207int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
2208 enum InstructionOpcodes {
2209#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
2210#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
2211#include "llvm/IR/Instruction.def"
2212 };
2213 switch (static_cast<InstructionOpcodes>(Opcode)) {
2214 case Ret: return 0;
2215 case UncondBr: return 0;
2216 case CondBr: return 0;
2217 case Switch: return 0;
2218 case IndirectBr: return 0;
2219 case Invoke: return 0;
2220 case CallBr: return 0;
2221 case Resume: return 0;
2222 case Unreachable: return 0;
2223 case CleanupRet: return 0;
2224 case CatchRet: return 0;
2225 case CatchPad: return 0;
2226 case CatchSwitch: return 0;
2227 case CleanupPad: return 0;
2228 case FNeg: return ISD::FNEG;
2229 case Add: return ISD::ADD;
2230 case FAdd: return ISD::FADD;
2231 case Sub: return ISD::SUB;
2232 case FSub: return ISD::FSUB;
2233 case Mul: return ISD::MUL;
2234 case FMul: return ISD::FMUL;
2235 case UDiv: return ISD::UDIV;
2236 case SDiv: return ISD::SDIV;
2237 case FDiv: return ISD::FDIV;
2238 case URem: return ISD::UREM;
2239 case SRem: return ISD::SREM;
2240 case FRem: return ISD::FREM;
2241 case Shl: return ISD::SHL;
2242 case LShr: return ISD::SRL;
2243 case AShr: return ISD::SRA;
2244 case And: return ISD::AND;
2245 case Or: return ISD::OR;
2246 case Xor: return ISD::XOR;
2247 case Alloca: return 0;
2248 case Load: return ISD::LOAD;
2249 case Store: return ISD::STORE;
2250 case GetElementPtr: return 0;
2251 case Fence: return 0;
2252 case AtomicCmpXchg: return 0;
2253 case AtomicRMW: return 0;
2254 case Trunc: return ISD::TRUNCATE;
2255 case ZExt: return ISD::ZERO_EXTEND;
2256 case SExt: return ISD::SIGN_EXTEND;
2257 case FPToUI: return ISD::FP_TO_UINT;
2258 case FPToSI: return ISD::FP_TO_SINT;
2259 case UIToFP: return ISD::UINT_TO_FP;
2260 case SIToFP: return ISD::SINT_TO_FP;
2261 case FPTrunc: return ISD::FP_ROUND;
2262 case FPExt: return ISD::FP_EXTEND;
2263 case PtrToAddr: return ISD::BITCAST;
2264 case PtrToInt: return ISD::BITCAST;
2265 case IntToPtr: return ISD::BITCAST;
2266 case BitCast: return ISD::BITCAST;
2267 case AddrSpaceCast: return ISD::ADDRSPACECAST;
2268 case ICmp: return ISD::SETCC;
2269 case FCmp: return ISD::SETCC;
2270 case PHI: return 0;
2271 case Call: return 0;
2272 case Select: return ISD::SELECT;
2273 case UserOp1: return 0;
2274 case UserOp2: return 0;
2275 case VAArg: return 0;
2276 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
2277 case InsertElement: return ISD::INSERT_VECTOR_ELT;
2278 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
2279 case ExtractValue: return ISD::MERGE_VALUES;
2280 case InsertValue: return ISD::MERGE_VALUES;
2281 case LandingPad: return 0;
2282 case Freeze: return ISD::FREEZE;
2283 }
2284
2285 llvm_unreachable("Unknown instruction type encountered!");
2286}
2287
2288int TargetLoweringBase::IntrinsicIDToISD(Intrinsic::ID ID) const {
2289 switch (ID) {
2290 case Intrinsic::exp:
2291 return ISD::FEXP;
2292 case Intrinsic::exp2:
2293 return ISD::FEXP2;
2294 case Intrinsic::log:
2295 return ISD::FLOG;
2296 default:
2297 return ISD::DELETED_NODE;
2298 }
2299}
2300
2301Value *
2302TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilderBase &IRB,
2303 bool UseTLS) const {
2304 // compiler-rt provides a variable with a magic name. Targets that do not
2305 // link with compiler-rt may also provide such a variable.
2306 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2307
2308 RTLIB::LibcallImpl UnsafeStackPtrImpl =
2309 Libcalls.getLibcallImpl(Call: RTLIB::SAFESTACK_UNSAFE_STACK_PTR);
2310 if (UnsafeStackPtrImpl == RTLIB::Unsupported)
2311 return nullptr;
2312
2313 StringRef UnsafeStackPtrVar =
2314 RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: UnsafeStackPtrImpl);
2315 auto UnsafeStackPtr =
2316 dyn_cast_or_null<GlobalVariable>(Val: M->getNamedValue(Name: UnsafeStackPtrVar));
2317
2318 const DataLayout &DL = M->getDataLayout();
2319 PointerType *StackPtrTy = DL.getAllocaPtrType(Ctx&: M->getContext());
2320
2321 if (!UnsafeStackPtr) {
2322 auto TLSModel = UseTLS ?
2323 GlobalValue::InitialExecTLSModel :
2324 GlobalValue::NotThreadLocal;
2325 // The global variable is not defined yet, define it ourselves.
2326 // We use the initial-exec TLS model because we do not support the
2327 // variable living anywhere other than in the main executable.
2328 UnsafeStackPtr = new GlobalVariable(
2329 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
2330 UnsafeStackPtrVar, nullptr, TLSModel);
2331 } else {
2332 // The variable exists, check its type and attributes.
2333 //
2334 // FIXME: Move to IR verifier.
2335 if (UnsafeStackPtr->getValueType() != StackPtrTy)
2336 report_fatal_error(reason: Twine(UnsafeStackPtrVar) + " must have void* type");
2337 if (UseTLS != UnsafeStackPtr->isThreadLocal())
2338 report_fatal_error(reason: Twine(UnsafeStackPtrVar) + " must " +
2339 (UseTLS ? "" : "not ") + "be thread-local");
2340 }
2341 return UnsafeStackPtr;
2342}
2343
2344Value *TargetLoweringBase::getSafeStackPointerLocation(
2345 IRBuilderBase &IRB, const LibcallLoweringInfo &Libcalls) const {
2346 RTLIB::LibcallImpl SafestackPointerAddressImpl =
2347 Libcalls.getLibcallImpl(Call: RTLIB::SAFESTACK_POINTER_ADDRESS);
2348 if (SafestackPointerAddressImpl == RTLIB::Unsupported)
2349 return getDefaultSafeStackPointerLocation(IRB, UseTLS: true);
2350
2351 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2352 auto *PtrTy = PointerType::getUnqual(C&: M->getContext());
2353
2354 // Android provides a libc function to retrieve the address of the current
2355 // thread's unsafe stack pointer.
2356 FunctionCallee Fn =
2357 M->getOrInsertFunction(Name: RTLIB::RuntimeLibcallsInfo::getLibcallImplName(
2358 CallImpl: SafestackPointerAddressImpl),
2359 RetTy: PtrTy);
2360 return IRB.CreateCall(Callee: Fn);
2361}
2362
2363//===----------------------------------------------------------------------===//
2364// Loop Strength Reduction hooks
2365//===----------------------------------------------------------------------===//
2366
2367/// isLegalAddressingMode - Return true if the addressing mode represented
2368/// by AM is legal for this target, for a load/store of the specified type.
2369bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
2370 const AddrMode &AM, Type *Ty,
2371 unsigned AS, Instruction *I) const {
2372 // The default implementation of this implements a conservative RISCy, r+r and
2373 // r+i addr mode.
2374
2375 // Scalable offsets not supported
2376 if (AM.ScalableOffset)
2377 return false;
2378
2379 // Allows a sign-extended 16-bit immediate field.
2380 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2381 return false;
2382
2383 // No global is ever allowed as a base.
2384 if (AM.BaseGV)
2385 return false;
2386
2387 // Only support r+r,
2388 switch (AM.Scale) {
2389 case 0: // "r+i" or just "i", depending on HasBaseReg.
2390 break;
2391 case 1:
2392 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2393 return false;
2394 // Otherwise we have r+r or r+i.
2395 break;
2396 case 2:
2397 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2398 return false;
2399 // Allow 2*r as r+r.
2400 break;
2401 default: // Don't allow n * r
2402 return false;
2403 }
2404
2405 return true;
2406}
2407
2408//===----------------------------------------------------------------------===//
2409// Stack Protector
2410//===----------------------------------------------------------------------===//
2411
2412// For OpenBSD return its special guard variable. Otherwise return nullptr,
2413// so that SelectionDAG handle SSP.
2414Value *
2415TargetLoweringBase::getIRStackGuard(IRBuilderBase &IRB,
2416 const LibcallLoweringInfo &Libcalls) const {
2417 RTLIB::LibcallImpl GuardLocalImpl =
2418 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2419 if (GuardLocalImpl != RTLIB::impl___guard_local)
2420 return nullptr;
2421
2422 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
2423 const DataLayout &DL = M.getDataLayout();
2424 PointerType *PtrTy =
2425 PointerType::get(C&: M.getContext(), AddressSpace: DL.getDefaultGlobalsAddressSpace());
2426 GlobalVariable *G =
2427 M.getOrInsertGlobal(Name: getLibcallImplName(Call: GuardLocalImpl), Ty: PtrTy);
2428 G->setVisibility(GlobalValue::HiddenVisibility);
2429 return G;
2430}
2431
2432// Currently only support "standard" __stack_chk_guard.
2433// TODO: add LOAD_STACK_GUARD support.
2434void TargetLoweringBase::insertSSPDeclarations(
2435 Module &M, const LibcallLoweringInfo &Libcalls) const {
2436 RTLIB::LibcallImpl StackGuardImpl =
2437 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2438 if (StackGuardImpl == RTLIB::Unsupported)
2439 return;
2440
2441 StringRef StackGuardVarName = getLibcallImplName(Call: StackGuardImpl);
2442 M.getOrInsertGlobal(
2443 Name: StackGuardVarName, Ty: PointerType::getUnqual(C&: M.getContext()), CreateGlobalCallback: [=, &M]() {
2444 auto *GV = new GlobalVariable(M, PointerType::getUnqual(C&: M.getContext()),
2445 false, GlobalVariable::ExternalLinkage,
2446 nullptr, StackGuardVarName);
2447
2448 // FreeBSD has "__stack_chk_guard" defined externally on libc.so
2449 if (M.getDirectAccessExternalData() &&
2450 !TM.getTargetTriple().isOSCygMing() &&
2451 !(TM.getTargetTriple().isPPC64() &&
2452 TM.getTargetTriple().isOSFreeBSD()) &&
2453 (!TM.getTargetTriple().isOSDarwin() ||
2454 TM.getRelocationModel() == Reloc::Static))
2455 GV->setDSOLocal(true);
2456
2457 return GV;
2458 });
2459}
2460
2461// Currently only support "standard" __stack_chk_guard.
2462// TODO: add LOAD_STACK_GUARD support.
2463Value *TargetLoweringBase::getSDagStackGuard(
2464 const Module &M, const LibcallLoweringInfo &Libcalls) const {
2465 RTLIB::LibcallImpl GuardVarImpl =
2466 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2467 if (GuardVarImpl == RTLIB::Unsupported)
2468 return nullptr;
2469 return M.getNamedValue(Name: getLibcallImplName(Call: GuardVarImpl));
2470}
2471
2472Function *TargetLoweringBase::getSSPStackGuardCheck(
2473 const Module &M, const LibcallLoweringInfo &Libcalls) const {
2474 // MSVC CRT has a function to validate security cookie.
2475 RTLIB::LibcallImpl SecurityCheckCookieLibcall =
2476 Libcalls.getLibcallImpl(Call: RTLIB::SECURITY_CHECK_COOKIE);
2477 if (SecurityCheckCookieLibcall != RTLIB::Unsupported)
2478 return M.getFunction(Name: getLibcallImplName(Call: SecurityCheckCookieLibcall));
2479 return nullptr;
2480}
2481
2482unsigned TargetLoweringBase::getMinimumJumpTableEntries() const {
2483 return MinimumJumpTableEntries;
2484}
2485
2486void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) {
2487 MinimumJumpTableEntries = Val;
2488}
2489
2490unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
2491 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
2492}
2493
2494unsigned TargetLoweringBase::getMaximumJumpTableSize() const {
2495 return MaximumJumpTableSize;
2496}
2497
2498void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {
2499 MaximumJumpTableSize = Val;
2500}
2501
2502bool TargetLoweringBase::isJumpTableRelative() const {
2503 return getTargetMachine().isPositionIndependent();
2504}
2505
2506unsigned TargetLoweringBase::getMinimumBitTestCmps() const {
2507 return MinimumBitTestCmps;
2508}
2509
2510void TargetLoweringBase::setMinimumBitTestCmps(unsigned Val) {
2511 MinimumBitTestCmps = Val;
2512}
2513
2514Align TargetLoweringBase::getPrefLoopAlignment(MachineLoop *ML) const {
2515 if (TM.Options.LoopAlignment)
2516 return Align(TM.Options.LoopAlignment);
2517 return PrefLoopAlignment;
2518}
2519
2520unsigned TargetLoweringBase::getMaxPermittedBytesForAlignment(
2521 MachineBasicBlock *MBB) const {
2522 return MaxBytesForAlignment;
2523}
2524
2525//===----------------------------------------------------------------------===//
2526// Reciprocal Estimates
2527//===----------------------------------------------------------------------===//
2528
2529/// Get the reciprocal estimate attribute string for a function that will
2530/// override the target defaults.
2531static StringRef getRecipEstimateForFunc(MachineFunction &MF) {
2532 const Function &F = MF.getFunction();
2533 return F.getFnAttribute(Kind: "reciprocal-estimates").getValueAsString();
2534}
2535
2536/// Construct a string for the given reciprocal operation of the given type.
2537/// This string should match the corresponding option to the front-end's
2538/// "-mrecip" flag assuming those strings have been passed through in an
2539/// attribute string. For example, "vec-divf" for a division of a vXf32.
2540static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2541 std::string Name = VT.isVector() ? "vec-" : "";
2542
2543 Name += IsSqrt ? "sqrt" : "div";
2544
2545 // TODO: Handle other float types?
2546 if (VT.getScalarType() == MVT::f64) {
2547 Name += "d";
2548 } else if (VT.getScalarType() == MVT::f16) {
2549 Name += "h";
2550 } else {
2551 assert(VT.getScalarType() == MVT::f32 &&
2552 "Unexpected FP type for reciprocal estimate");
2553 Name += "f";
2554 }
2555
2556 return Name;
2557}
2558
2559/// Return the character position and value (a single numeric character) of a
2560/// customized refinement operation in the input string if it exists. Return
2561/// false if there is no customized refinement step count.
2562static bool parseRefinementStep(StringRef In, size_t &Position,
2563 uint8_t &Value) {
2564 const char RefStepToken = ':';
2565 Position = In.find(C: RefStepToken);
2566 if (Position == StringRef::npos)
2567 return false;
2568
2569 StringRef RefStepString = In.substr(Start: Position + 1);
2570 // Allow exactly one numeric character for the additional refinement
2571 // step parameter.
2572 if (RefStepString.size() == 1) {
2573 char RefStepChar = RefStepString[0];
2574 if (isDigit(C: RefStepChar)) {
2575 Value = RefStepChar - '0';
2576 return true;
2577 }
2578 }
2579 report_fatal_error(reason: "Invalid refinement step for -recip.");
2580}
2581
2582/// For the input attribute string, return one of the ReciprocalEstimate enum
2583/// status values (enabled, disabled, or not specified) for this operation on
2584/// the specified data type.
2585static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2586 if (Override.empty())
2587 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2588
2589 SmallVector<StringRef, 4> OverrideVector;
2590 Override.split(A&: OverrideVector, Separator: ',');
2591 unsigned NumArgs = OverrideVector.size();
2592
2593 // Check if "all", "none", or "default" was specified.
2594 if (NumArgs == 1) {
2595 // Look for an optional setting of the number of refinement steps needed
2596 // for this type of reciprocal operation.
2597 size_t RefPos;
2598 uint8_t RefSteps;
2599 if (parseRefinementStep(In: Override, Position&: RefPos, Value&: RefSteps)) {
2600 // Split the string for further processing.
2601 Override = Override.substr(Start: 0, N: RefPos);
2602 }
2603
2604 // All reciprocal types are enabled.
2605 if (Override == "all")
2606 return TargetLoweringBase::ReciprocalEstimate::Enabled;
2607
2608 // All reciprocal types are disabled.
2609 if (Override == "none")
2610 return TargetLoweringBase::ReciprocalEstimate::Disabled;
2611
2612 // Target defaults for enablement are used.
2613 if (Override == "default")
2614 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2615 }
2616
2617 // The attribute string may omit the size suffix ('f'/'d').
2618 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2619 std::string VTNameNoSize = VTName;
2620 VTNameNoSize.pop_back();
2621 static const char DisabledPrefix = '!';
2622
2623 for (StringRef RecipType : OverrideVector) {
2624 size_t RefPos;
2625 uint8_t RefSteps;
2626 if (parseRefinementStep(In: RecipType, Position&: RefPos, Value&: RefSteps))
2627 RecipType = RecipType.substr(Start: 0, N: RefPos);
2628
2629 // Ignore the disablement token for string matching.
2630 bool IsDisabled = RecipType[0] == DisabledPrefix;
2631 if (IsDisabled)
2632 RecipType = RecipType.substr(Start: 1);
2633
2634 if (RecipType == VTName || RecipType == VTNameNoSize)
2635 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
2636 : TargetLoweringBase::ReciprocalEstimate::Enabled;
2637 }
2638
2639 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2640}
2641
2642/// For the input attribute string, return the customized refinement step count
2643/// for this operation on the specified data type. If the step count does not
2644/// exist, return the ReciprocalEstimate enum value for unspecified.
2645static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2646 if (Override.empty())
2647 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2648
2649 SmallVector<StringRef, 4> OverrideVector;
2650 Override.split(A&: OverrideVector, Separator: ',');
2651 unsigned NumArgs = OverrideVector.size();
2652
2653 // Check if "all", "default", or "none" was specified.
2654 if (NumArgs == 1) {
2655 // Look for an optional setting of the number of refinement steps needed
2656 // for this type of reciprocal operation.
2657 size_t RefPos;
2658 uint8_t RefSteps;
2659 if (!parseRefinementStep(In: Override, Position&: RefPos, Value&: RefSteps))
2660 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2661
2662 // Split the string for further processing.
2663 Override = Override.substr(Start: 0, N: RefPos);
2664 assert(Override != "none" &&
2665 "Disabled reciprocals, but specifed refinement steps?");
2666
2667 // If this is a general override, return the specified number of steps.
2668 if (Override == "all" || Override == "default")
2669 return RefSteps;
2670 }
2671
2672 // The attribute string may omit the size suffix ('f'/'d').
2673 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2674 std::string VTNameNoSize = VTName;
2675 VTNameNoSize.pop_back();
2676
2677 for (StringRef RecipType : OverrideVector) {
2678 size_t RefPos;
2679 uint8_t RefSteps;
2680 if (!parseRefinementStep(In: RecipType, Position&: RefPos, Value&: RefSteps))
2681 continue;
2682
2683 RecipType = RecipType.substr(Start: 0, N: RefPos);
2684 if (RecipType == VTName || RecipType == VTNameNoSize)
2685 return RefSteps;
2686 }
2687
2688 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2689}
2690
2691int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,
2692 MachineFunction &MF) const {
2693 return getOpEnabled(IsSqrt: true, VT, Override: getRecipEstimateForFunc(MF));
2694}
2695
2696int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,
2697 MachineFunction &MF) const {
2698 return getOpEnabled(IsSqrt: false, VT, Override: getRecipEstimateForFunc(MF));
2699}
2700
2701int TargetLoweringBase::getSqrtRefinementSteps(EVT VT,
2702 MachineFunction &MF) const {
2703 return getOpRefinementSteps(IsSqrt: true, VT, Override: getRecipEstimateForFunc(MF));
2704}
2705
2706int TargetLoweringBase::getDivRefinementSteps(EVT VT,
2707 MachineFunction &MF) const {
2708 return getOpRefinementSteps(IsSqrt: false, VT, Override: getRecipEstimateForFunc(MF));
2709}
2710
2711bool TargetLoweringBase::isLoadBitCastBeneficial(
2712 EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG,
2713 const MachineMemOperand &MMO) const {
2714 // Single-element vectors are scalarized, so we should generally avoid having
2715 // any memory operations on such types, as they would get scalarized too.
2716 if (LoadVT.isFixedLengthVector() && BitcastVT.isFixedLengthVector() &&
2717 BitcastVT.getVectorNumElements() == 1)
2718 return false;
2719
2720 // Don't do if we could do an indexed load on the original type, but not on
2721 // the new one.
2722 if (!LoadVT.isSimple() || !BitcastVT.isSimple())
2723 return true;
2724
2725 MVT LoadMVT = LoadVT.getSimpleVT();
2726
2727 // Don't bother doing this if it's just going to be promoted again later, as
2728 // doing so might interfere with other combines.
2729 if (getOperationAction(Op: ISD::LOAD, VT: LoadMVT) == Promote &&
2730 getTypeToPromoteTo(Op: ISD::LOAD, VT: LoadMVT) == BitcastVT.getSimpleVT())
2731 return false;
2732
2733 unsigned Fast = 0;
2734 return allowsMemoryAccess(Context&: *DAG.getContext(), DL: DAG.getDataLayout(), VT: BitcastVT,
2735 MMO, Fast: &Fast) &&
2736 Fast;
2737}
2738
2739void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
2740 MF.getRegInfo().freezeReservedRegs();
2741}
2742
2743MachineMemOperand::Flags TargetLoweringBase::getLoadMemOperandFlags(
2744 const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC,
2745 const TargetLibraryInfo *LibInfo) const {
2746 MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad;
2747 if (LI.isVolatile())
2748 Flags |= MachineMemOperand::MOVolatile;
2749
2750 if (LI.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2751 Flags |= MachineMemOperand::MONonTemporal;
2752
2753 if (LI.hasMetadata(KindID: LLVMContext::MD_invariant_load))
2754 Flags |= MachineMemOperand::MOInvariant;
2755
2756 if (isDereferenceableAndAlignedPointer(V: LI.getPointerOperand(), Ty: LI.getType(),
2757 Alignment: LI.getAlign(), DL, CtxI: &LI, AC,
2758 /*DT=*/nullptr, TLI: LibInfo))
2759 Flags |= MachineMemOperand::MODereferenceable;
2760
2761 Flags |= getTargetMMOFlags(I: LI);
2762 return Flags;
2763}
2764
2765MachineMemOperand::Flags
2766TargetLoweringBase::getStoreMemOperandFlags(const StoreInst &SI,
2767 const DataLayout &DL) const {
2768 MachineMemOperand::Flags Flags = MachineMemOperand::MOStore;
2769
2770 if (SI.isVolatile())
2771 Flags |= MachineMemOperand::MOVolatile;
2772
2773 if (SI.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2774 Flags |= MachineMemOperand::MONonTemporal;
2775
2776 // FIXME: Not preserving dereferenceable
2777 Flags |= getTargetMMOFlags(I: SI);
2778 return Flags;
2779}
2780
2781MachineMemOperand::Flags
2782TargetLoweringBase::getAtomicMemOperandFlags(const Instruction &AI,
2783 const DataLayout &DL) const {
2784 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
2785
2786 if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(Val: &AI)) {
2787 if (RMW->isVolatile())
2788 Flags |= MachineMemOperand::MOVolatile;
2789 } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(Val: &AI)) {
2790 if (CmpX->isVolatile())
2791 Flags |= MachineMemOperand::MOVolatile;
2792 } else
2793 llvm_unreachable("not an atomic instruction");
2794
2795 // FIXME: Not preserving dereferenceable
2796 Flags |= getTargetMMOFlags(I: AI);
2797 return Flags;
2798}
2799
2800MachineMemOperand::Flags TargetLoweringBase::getVPIntrinsicMemOperandFlags(
2801 const VPIntrinsic &VPIntrin) const {
2802 MachineMemOperand::Flags Flags = MachineMemOperand::MONone;
2803 Intrinsic::ID IntrinID = VPIntrin.getIntrinsicID();
2804
2805 switch (IntrinID) {
2806 default:
2807 llvm_unreachable("unexpected intrinsic. Existing code may be appropriate "
2808 "for it, but support must be explicitly enabled");
2809 case Intrinsic::vp_load:
2810 case Intrinsic::vp_gather:
2811 case Intrinsic::experimental_vp_strided_load:
2812 Flags = MachineMemOperand::MOLoad;
2813 break;
2814 case Intrinsic::vp_store:
2815 case Intrinsic::vp_scatter:
2816 case Intrinsic::experimental_vp_strided_store:
2817 Flags = MachineMemOperand::MOStore;
2818 break;
2819 }
2820
2821 if (VPIntrin.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2822 Flags |= MachineMemOperand::MONonTemporal;
2823
2824 Flags |= getTargetMMOFlags(I: VPIntrin);
2825 return Flags;
2826}
2827
2828Instruction *TargetLoweringBase::emitLeadingFence(IRBuilderBase &Builder,
2829 Instruction *Inst,
2830 AtomicOrdering Ord) const {
2831 if (isReleaseOrStronger(AO: Ord) && Inst->hasAtomicStore())
2832 return Builder.CreateFence(Ordering: Ord);
2833 else
2834 return nullptr;
2835}
2836
2837Instruction *TargetLoweringBase::emitTrailingFence(IRBuilderBase &Builder,
2838 Instruction *Inst,
2839 AtomicOrdering Ord) const {
2840 if (isAcquireOrStronger(AO: Ord))
2841 return Builder.CreateFence(Ordering: Ord);
2842 else
2843 return nullptr;
2844}
2845
2846//===----------------------------------------------------------------------===//
2847// GlobalISel Hooks
2848//===----------------------------------------------------------------------===//
2849
2850bool TargetLoweringBase::shouldLocalize(const MachineInstr &MI,
2851 const TargetTransformInfo *TTI) const {
2852 auto &MF = *MI.getMF();
2853 auto &MRI = MF.getRegInfo();
2854 // Assuming a spill and reload of a value has a cost of 1 instruction each,
2855 // this helper function computes the maximum number of uses we should consider
2856 // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2857 // break even in terms of code size when the original MI has 2 users vs
2858 // choosing to potentially spill. Any more than 2 users we we have a net code
2859 // size increase. This doesn't take into account register pressure though.
2860 auto maxUses = [](unsigned RematCost) {
2861 // A cost of 1 means remats are basically free.
2862 if (RematCost == 1)
2863 return std::numeric_limits<unsigned>::max();
2864 if (RematCost == 2)
2865 return 2U;
2866
2867 // Remat is too expensive, only sink if there's one user.
2868 if (RematCost > 2)
2869 return 1U;
2870 llvm_unreachable("Unexpected remat cost");
2871 };
2872
2873 switch (MI.getOpcode()) {
2874 default:
2875 return false;
2876 // Constants-like instructions should be close to their users.
2877 // We don't want long live-ranges for them.
2878 case TargetOpcode::G_CONSTANT:
2879 case TargetOpcode::G_FCONSTANT:
2880 case TargetOpcode::G_FRAME_INDEX:
2881 case TargetOpcode::G_INTTOPTR:
2882 return true;
2883 case TargetOpcode::G_GLOBAL_VALUE: {
2884 unsigned RematCost = TTI->getGISelRematGlobalCost();
2885 Register Reg = MI.getOperand(i: 0).getReg();
2886 unsigned MaxUses = maxUses(RematCost);
2887 if (MaxUses == UINT_MAX)
2888 return true; // Remats are "free" so always localize.
2889 return MRI.hasAtMostUserInstrs(Reg, MaxUsers: MaxUses);
2890 }
2891 }
2892}
2893