1//===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the TargetLoweringBase class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/ADT/BitVector.h"
14#include "llvm/ADT/STLExtras.h"
15#include "llvm/ADT/SmallVector.h"
16#include "llvm/ADT/StringExtras.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/Twine.h"
19#include "llvm/Analysis/Loads.h"
20#include "llvm/Analysis/TargetTransformInfo.h"
21#include "llvm/CodeGen/Analysis.h"
22#include "llvm/CodeGen/ISDOpcodes.h"
23#include "llvm/CodeGen/MachineBasicBlock.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineMemOperand.h"
29#include "llvm/CodeGen/MachineOperand.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RuntimeLibcallUtil.h"
32#include "llvm/CodeGen/StackMaps.h"
33#include "llvm/CodeGen/TargetLowering.h"
34#include "llvm/CodeGen/TargetOpcodes.h"
35#include "llvm/CodeGen/TargetRegisterInfo.h"
36#include "llvm/CodeGen/ValueTypes.h"
37#include "llvm/CodeGenTypes/MachineValueType.h"
38#include "llvm/IR/Attributes.h"
39#include "llvm/IR/CallingConv.h"
40#include "llvm/IR/DataLayout.h"
41#include "llvm/IR/DerivedTypes.h"
42#include "llvm/IR/Function.h"
43#include "llvm/IR/GlobalValue.h"
44#include "llvm/IR/GlobalVariable.h"
45#include "llvm/IR/IRBuilder.h"
46#include "llvm/IR/Module.h"
47#include "llvm/IR/Type.h"
48#include "llvm/Support/Casting.h"
49#include "llvm/Support/CommandLine.h"
50#include "llvm/Support/Compiler.h"
51#include "llvm/Support/ErrorHandling.h"
52#include "llvm/Support/MathExtras.h"
53#include "llvm/Target/TargetMachine.h"
54#include "llvm/Target/TargetOptions.h"
55#include "llvm/TargetParser/Triple.h"
56#include "llvm/Transforms/Utils/SizeOpts.h"
57#include <algorithm>
58#include <cassert>
59#include <cstdint>
60#include <cstring>
61#include <string>
62#include <tuple>
63#include <utility>
64
65using namespace llvm;
66
67static cl::opt<bool> JumpIsExpensiveOverride(
68 "jump-is-expensive", cl::init(Val: false),
69 cl::desc("Do not create extra branches to split comparison logic."),
70 cl::Hidden);
71
72static cl::opt<unsigned> MinimumJumpTableEntries
73 ("min-jump-table-entries", cl::init(Val: 4), cl::Hidden,
74 cl::desc("Set minimum number of entries to use a jump table."));
75
76static cl::opt<unsigned> MaximumJumpTableSize
77 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
78 cl::desc("Set maximum size of jump tables."));
79
80/// Minimum jump table density for normal functions.
81static cl::opt<unsigned>
82 JumpTableDensity("jump-table-density", cl::init(Val: 10), cl::Hidden,
83 cl::desc("Minimum density for building a jump table in "
84 "a normal function"));
85
86/// Minimum jump table density for -Os or -Oz functions.
87static cl::opt<unsigned> OptsizeJumpTableDensity(
88 "optsize-jump-table-density", cl::init(Val: 40), cl::Hidden,
89 cl::desc("Minimum density for building a jump table in "
90 "an optsize function"));
91
92static cl::opt<unsigned> MinimumBitTestCmpsOverride(
93 "min-bit-test-cmps", cl::init(Val: 2), cl::Hidden,
94 cl::desc("Set minimum of largest number of comparisons "
95 "to use bit test for switch."));
96
97static cl::opt<unsigned> MaxStoresPerMemsetOverride(
98 "max-store-memset", cl::init(Val: 0), cl::Hidden,
99 cl::desc("Override target's MaxStoresPerMemset and "
100 "MaxStoresPerMemsetOptSize. "
101 "Set to 0 to use the target default."));
102
103static cl::opt<unsigned> MaxStoresPerMemcpyOverride(
104 "max-store-memcpy", cl::init(Val: 0), cl::Hidden,
105 cl::desc("Override target's MaxStoresPerMemcpy and "
106 "MaxStoresPerMemcpyOptSize. "
107 "Set to 0 to use the target default."));
108
109static cl::opt<unsigned> MaxStoresPerMemmoveOverride(
110 "max-store-memmove", cl::init(Val: 0), cl::Hidden,
111 cl::desc("Override target's MaxStoresPerMemmove and "
112 "MaxStoresPerMemmoveOptSize. "
113 "Set to 0 to use the target default."));
114
115// FIXME: This option is only to test if the strict fp operation processed
116// correctly by preventing mutating strict fp operation to normal fp operation
117// during development. When the backend supports strict float operation, this
118// option will be meaningless.
119static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
120 cl::desc("Don't mutate strict-float node to a legalize node"),
121 cl::init(Val: false), cl::Hidden);
122
123LLVM_ABI RTLIB::Libcall RTLIB::getSHL(EVT VT) {
124 if (VT == MVT::i16)
125 return RTLIB::SHL_I16;
126 if (VT == MVT::i32)
127 return RTLIB::SHL_I32;
128 if (VT == MVT::i64)
129 return RTLIB::SHL_I64;
130 if (VT == MVT::i128)
131 return RTLIB::SHL_I128;
132
133 return RTLIB::UNKNOWN_LIBCALL;
134}
135
136LLVM_ABI RTLIB::Libcall RTLIB::getSRL(EVT VT) {
137 if (VT == MVT::i16)
138 return RTLIB::SRL_I16;
139 if (VT == MVT::i32)
140 return RTLIB::SRL_I32;
141 if (VT == MVT::i64)
142 return RTLIB::SRL_I64;
143 if (VT == MVT::i128)
144 return RTLIB::SRL_I128;
145
146 return RTLIB::UNKNOWN_LIBCALL;
147}
148
149LLVM_ABI RTLIB::Libcall RTLIB::getSRA(EVT VT) {
150 if (VT == MVT::i16)
151 return RTLIB::SRA_I16;
152 if (VT == MVT::i32)
153 return RTLIB::SRA_I32;
154 if (VT == MVT::i64)
155 return RTLIB::SRA_I64;
156 if (VT == MVT::i128)
157 return RTLIB::SRA_I128;
158
159 return RTLIB::UNKNOWN_LIBCALL;
160}
161
162LLVM_ABI RTLIB::Libcall RTLIB::getMUL(EVT VT) {
163 if (VT == MVT::i16)
164 return RTLIB::MUL_I16;
165 if (VT == MVT::i32)
166 return RTLIB::MUL_I32;
167 if (VT == MVT::i64)
168 return RTLIB::MUL_I64;
169 if (VT == MVT::i128)
170 return RTLIB::MUL_I128;
171 return RTLIB::UNKNOWN_LIBCALL;
172}
173
174LLVM_ABI RTLIB::Libcall RTLIB::getMULO(EVT VT) {
175 if (VT == MVT::i32)
176 return RTLIB::MULO_I32;
177 if (VT == MVT::i64)
178 return RTLIB::MULO_I64;
179 if (VT == MVT::i128)
180 return RTLIB::MULO_I128;
181 return RTLIB::UNKNOWN_LIBCALL;
182}
183
184LLVM_ABI RTLIB::Libcall RTLIB::getSDIV(EVT VT) {
185 if (VT == MVT::i16)
186 return RTLIB::SDIV_I16;
187 if (VT == MVT::i32)
188 return RTLIB::SDIV_I32;
189 if (VT == MVT::i64)
190 return RTLIB::SDIV_I64;
191 if (VT == MVT::i128)
192 return RTLIB::SDIV_I128;
193 return RTLIB::UNKNOWN_LIBCALL;
194}
195
196LLVM_ABI RTLIB::Libcall RTLIB::getUDIV(EVT VT) {
197 if (VT == MVT::i16)
198 return RTLIB::UDIV_I16;
199 if (VT == MVT::i32)
200 return RTLIB::UDIV_I32;
201 if (VT == MVT::i64)
202 return RTLIB::UDIV_I64;
203 if (VT == MVT::i128)
204 return RTLIB::UDIV_I128;
205 return RTLIB::UNKNOWN_LIBCALL;
206}
207
208LLVM_ABI RTLIB::Libcall RTLIB::getSREM(EVT VT) {
209 if (VT == MVT::i16)
210 return RTLIB::SREM_I16;
211 if (VT == MVT::i32)
212 return RTLIB::SREM_I32;
213 if (VT == MVT::i64)
214 return RTLIB::SREM_I64;
215 if (VT == MVT::i128)
216 return RTLIB::SREM_I128;
217 return RTLIB::UNKNOWN_LIBCALL;
218}
219
220LLVM_ABI RTLIB::Libcall RTLIB::getUREM(EVT VT) {
221 if (VT == MVT::i16)
222 return RTLIB::UREM_I16;
223 if (VT == MVT::i32)
224 return RTLIB::UREM_I32;
225 if (VT == MVT::i64)
226 return RTLIB::UREM_I64;
227 if (VT == MVT::i128)
228 return RTLIB::UREM_I128;
229 return RTLIB::UNKNOWN_LIBCALL;
230}
231
232LLVM_ABI RTLIB::Libcall RTLIB::getCTPOP(EVT VT) {
233 if (VT == MVT::i32)
234 return RTLIB::CTPOP_I32;
235 if (VT == MVT::i64)
236 return RTLIB::CTPOP_I64;
237 if (VT == MVT::i128)
238 return RTLIB::CTPOP_I128;
239 return RTLIB::UNKNOWN_LIBCALL;
240}
241
242/// GetFPLibCall - Helper to return the right libcall for the given floating
243/// point type, or UNKNOWN_LIBCALL if there is none.
244RTLIB::Libcall RTLIB::getFPLibCall(EVT VT,
245 RTLIB::Libcall Call_F32,
246 RTLIB::Libcall Call_F64,
247 RTLIB::Libcall Call_F80,
248 RTLIB::Libcall Call_F128,
249 RTLIB::Libcall Call_PPCF128) {
250 return
251 VT == MVT::f32 ? Call_F32 :
252 VT == MVT::f64 ? Call_F64 :
253 VT == MVT::f80 ? Call_F80 :
254 VT == MVT::f128 ? Call_F128 :
255 VT == MVT::ppcf128 ? Call_PPCF128 :
256 RTLIB::UNKNOWN_LIBCALL;
257}
258
259/// getFPEXT - Return the FPEXT_*_* value for the given types, or
260/// UNKNOWN_LIBCALL if there is none.
261RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
262 if (OpVT == MVT::f16) {
263 if (RetVT == MVT::f32)
264 return FPEXT_F16_F32;
265 if (RetVT == MVT::f64)
266 return FPEXT_F16_F64;
267 if (RetVT == MVT::f80)
268 return FPEXT_F16_F80;
269 if (RetVT == MVT::f128)
270 return FPEXT_F16_F128;
271 } else if (OpVT == MVT::f32) {
272 if (RetVT == MVT::f64)
273 return FPEXT_F32_F64;
274 if (RetVT == MVT::f128)
275 return FPEXT_F32_F128;
276 if (RetVT == MVT::ppcf128)
277 return FPEXT_F32_PPCF128;
278 } else if (OpVT == MVT::f64) {
279 if (RetVT == MVT::f128)
280 return FPEXT_F64_F128;
281 else if (RetVT == MVT::ppcf128)
282 return FPEXT_F64_PPCF128;
283 } else if (OpVT == MVT::f80) {
284 if (RetVT == MVT::f128)
285 return FPEXT_F80_F128;
286 } else if (OpVT == MVT::bf16) {
287 if (RetVT == MVT::f32)
288 return FPEXT_BF16_F32;
289 }
290
291 return UNKNOWN_LIBCALL;
292}
293
294/// getFPROUND - Return the FPROUND_*_* value for the given types, or
295/// UNKNOWN_LIBCALL if there is none.
296RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
297 if (RetVT == MVT::f16) {
298 if (OpVT == MVT::f32)
299 return FPROUND_F32_F16;
300 if (OpVT == MVT::f64)
301 return FPROUND_F64_F16;
302 if (OpVT == MVT::f80)
303 return FPROUND_F80_F16;
304 if (OpVT == MVT::f128)
305 return FPROUND_F128_F16;
306 if (OpVT == MVT::ppcf128)
307 return FPROUND_PPCF128_F16;
308 } else if (RetVT == MVT::bf16) {
309 if (OpVT == MVT::f32)
310 return FPROUND_F32_BF16;
311 if (OpVT == MVT::f64)
312 return FPROUND_F64_BF16;
313 if (OpVT == MVT::f80)
314 return FPROUND_F80_BF16;
315 if (OpVT == MVT::f128)
316 return FPROUND_F128_BF16;
317 } else if (RetVT == MVT::f32) {
318 if (OpVT == MVT::f64)
319 return FPROUND_F64_F32;
320 if (OpVT == MVT::f80)
321 return FPROUND_F80_F32;
322 if (OpVT == MVT::f128)
323 return FPROUND_F128_F32;
324 if (OpVT == MVT::ppcf128)
325 return FPROUND_PPCF128_F32;
326 } else if (RetVT == MVT::f64) {
327 if (OpVT == MVT::f80)
328 return FPROUND_F80_F64;
329 if (OpVT == MVT::f128)
330 return FPROUND_F128_F64;
331 if (OpVT == MVT::ppcf128)
332 return FPROUND_PPCF128_F64;
333 } else if (RetVT == MVT::f80) {
334 if (OpVT == MVT::f128)
335 return FPROUND_F128_F80;
336 }
337
338 return UNKNOWN_LIBCALL;
339}
340
341/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
342/// UNKNOWN_LIBCALL if there is none.
343RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
344 if (OpVT == MVT::f16) {
345 if (RetVT == MVT::i32)
346 return FPTOSINT_F16_I32;
347 if (RetVT == MVT::i64)
348 return FPTOSINT_F16_I64;
349 if (RetVT == MVT::i128)
350 return FPTOSINT_F16_I128;
351 } else if (OpVT == MVT::f32) {
352 if (RetVT == MVT::i32)
353 return FPTOSINT_F32_I32;
354 if (RetVT == MVT::i64)
355 return FPTOSINT_F32_I64;
356 if (RetVT == MVT::i128)
357 return FPTOSINT_F32_I128;
358 } else if (OpVT == MVT::f64) {
359 if (RetVT == MVT::i32)
360 return FPTOSINT_F64_I32;
361 if (RetVT == MVT::i64)
362 return FPTOSINT_F64_I64;
363 if (RetVT == MVT::i128)
364 return FPTOSINT_F64_I128;
365 } else if (OpVT == MVT::f80) {
366 if (RetVT == MVT::i32)
367 return FPTOSINT_F80_I32;
368 if (RetVT == MVT::i64)
369 return FPTOSINT_F80_I64;
370 if (RetVT == MVT::i128)
371 return FPTOSINT_F80_I128;
372 } else if (OpVT == MVT::f128) {
373 if (RetVT == MVT::i32)
374 return FPTOSINT_F128_I32;
375 if (RetVT == MVT::i64)
376 return FPTOSINT_F128_I64;
377 if (RetVT == MVT::i128)
378 return FPTOSINT_F128_I128;
379 } else if (OpVT == MVT::ppcf128) {
380 if (RetVT == MVT::i32)
381 return FPTOSINT_PPCF128_I32;
382 if (RetVT == MVT::i64)
383 return FPTOSINT_PPCF128_I64;
384 if (RetVT == MVT::i128)
385 return FPTOSINT_PPCF128_I128;
386 }
387 return UNKNOWN_LIBCALL;
388}
389
390/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
391/// UNKNOWN_LIBCALL if there is none.
392RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
393 if (OpVT == MVT::f16) {
394 if (RetVT == MVT::i32)
395 return FPTOUINT_F16_I32;
396 if (RetVT == MVT::i64)
397 return FPTOUINT_F16_I64;
398 if (RetVT == MVT::i128)
399 return FPTOUINT_F16_I128;
400 } else if (OpVT == MVT::f32) {
401 if (RetVT == MVT::i32)
402 return FPTOUINT_F32_I32;
403 if (RetVT == MVT::i64)
404 return FPTOUINT_F32_I64;
405 if (RetVT == MVT::i128)
406 return FPTOUINT_F32_I128;
407 } else if (OpVT == MVT::f64) {
408 if (RetVT == MVT::i32)
409 return FPTOUINT_F64_I32;
410 if (RetVT == MVT::i64)
411 return FPTOUINT_F64_I64;
412 if (RetVT == MVT::i128)
413 return FPTOUINT_F64_I128;
414 } else if (OpVT == MVT::f80) {
415 if (RetVT == MVT::i32)
416 return FPTOUINT_F80_I32;
417 if (RetVT == MVT::i64)
418 return FPTOUINT_F80_I64;
419 if (RetVT == MVT::i128)
420 return FPTOUINT_F80_I128;
421 } else if (OpVT == MVT::f128) {
422 if (RetVT == MVT::i32)
423 return FPTOUINT_F128_I32;
424 if (RetVT == MVT::i64)
425 return FPTOUINT_F128_I64;
426 if (RetVT == MVT::i128)
427 return FPTOUINT_F128_I128;
428 } else if (OpVT == MVT::ppcf128) {
429 if (RetVT == MVT::i32)
430 return FPTOUINT_PPCF128_I32;
431 if (RetVT == MVT::i64)
432 return FPTOUINT_PPCF128_I64;
433 if (RetVT == MVT::i128)
434 return FPTOUINT_PPCF128_I128;
435 }
436 return UNKNOWN_LIBCALL;
437}
438
439/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
440/// UNKNOWN_LIBCALL if there is none.
441RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
442 if (OpVT == MVT::i32) {
443 if (RetVT == MVT::f16)
444 return SINTTOFP_I32_F16;
445 if (RetVT == MVT::f32)
446 return SINTTOFP_I32_F32;
447 if (RetVT == MVT::f64)
448 return SINTTOFP_I32_F64;
449 if (RetVT == MVT::f80)
450 return SINTTOFP_I32_F80;
451 if (RetVT == MVT::f128)
452 return SINTTOFP_I32_F128;
453 if (RetVT == MVT::ppcf128)
454 return SINTTOFP_I32_PPCF128;
455 } else if (OpVT == MVT::i64) {
456 if (RetVT == MVT::bf16)
457 return SINTTOFP_I64_BF16;
458 if (RetVT == MVT::f16)
459 return SINTTOFP_I64_F16;
460 if (RetVT == MVT::f32)
461 return SINTTOFP_I64_F32;
462 if (RetVT == MVT::f64)
463 return SINTTOFP_I64_F64;
464 if (RetVT == MVT::f80)
465 return SINTTOFP_I64_F80;
466 if (RetVT == MVT::f128)
467 return SINTTOFP_I64_F128;
468 if (RetVT == MVT::ppcf128)
469 return SINTTOFP_I64_PPCF128;
470 } else if (OpVT == MVT::i128) {
471 if (RetVT == MVT::f16)
472 return SINTTOFP_I128_F16;
473 if (RetVT == MVT::f32)
474 return SINTTOFP_I128_F32;
475 if (RetVT == MVT::f64)
476 return SINTTOFP_I128_F64;
477 if (RetVT == MVT::f80)
478 return SINTTOFP_I128_F80;
479 if (RetVT == MVT::f128)
480 return SINTTOFP_I128_F128;
481 if (RetVT == MVT::ppcf128)
482 return SINTTOFP_I128_PPCF128;
483 }
484 return UNKNOWN_LIBCALL;
485}
486
487/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
488/// UNKNOWN_LIBCALL if there is none.
489RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
490 if (OpVT == MVT::i32) {
491 if (RetVT == MVT::f16)
492 return UINTTOFP_I32_F16;
493 if (RetVT == MVT::f32)
494 return UINTTOFP_I32_F32;
495 if (RetVT == MVT::f64)
496 return UINTTOFP_I32_F64;
497 if (RetVT == MVT::f80)
498 return UINTTOFP_I32_F80;
499 if (RetVT == MVT::f128)
500 return UINTTOFP_I32_F128;
501 if (RetVT == MVT::ppcf128)
502 return UINTTOFP_I32_PPCF128;
503 } else if (OpVT == MVT::i64) {
504 if (RetVT == MVT::bf16)
505 return UINTTOFP_I64_BF16;
506 if (RetVT == MVT::f16)
507 return UINTTOFP_I64_F16;
508 if (RetVT == MVT::f32)
509 return UINTTOFP_I64_F32;
510 if (RetVT == MVT::f64)
511 return UINTTOFP_I64_F64;
512 if (RetVT == MVT::f80)
513 return UINTTOFP_I64_F80;
514 if (RetVT == MVT::f128)
515 return UINTTOFP_I64_F128;
516 if (RetVT == MVT::ppcf128)
517 return UINTTOFP_I64_PPCF128;
518 } else if (OpVT == MVT::i128) {
519 if (RetVT == MVT::f16)
520 return UINTTOFP_I128_F16;
521 if (RetVT == MVT::f32)
522 return UINTTOFP_I128_F32;
523 if (RetVT == MVT::f64)
524 return UINTTOFP_I128_F64;
525 if (RetVT == MVT::f80)
526 return UINTTOFP_I128_F80;
527 if (RetVT == MVT::f128)
528 return UINTTOFP_I128_F128;
529 if (RetVT == MVT::ppcf128)
530 return UINTTOFP_I128_PPCF128;
531 }
532 return UNKNOWN_LIBCALL;
533}
534
535// The floating-point RTLIB::getXXX(EVT) selectors are generated from the
536// RuntimeLibcallFamily table in RuntimeLibcalls.td.
537#define GET_RUNTIME_LIBCALL_FP_SELECTORS
538#include "llvm/IR/RuntimeLibcalls.inc"
539
540RTLIB::Libcall RTLIB::getOutlineAtomicHelper(const Libcall (&LC)[5][4],
541 AtomicOrdering Order,
542 uint64_t MemSize) {
543 unsigned ModeN, ModelN;
544 switch (MemSize) {
545 case 1:
546 ModeN = 0;
547 break;
548 case 2:
549 ModeN = 1;
550 break;
551 case 4:
552 ModeN = 2;
553 break;
554 case 8:
555 ModeN = 3;
556 break;
557 case 16:
558 ModeN = 4;
559 break;
560 default:
561 return RTLIB::UNKNOWN_LIBCALL;
562 }
563
564 switch (Order) {
565 case AtomicOrdering::Monotonic:
566 ModelN = 0;
567 break;
568 case AtomicOrdering::Acquire:
569 ModelN = 1;
570 break;
571 case AtomicOrdering::Release:
572 ModelN = 2;
573 break;
574 case AtomicOrdering::AcquireRelease:
575 case AtomicOrdering::SequentiallyConsistent:
576 ModelN = 3;
577 break;
578 default:
579 return UNKNOWN_LIBCALL;
580 }
581
582 return LC[ModeN][ModelN];
583}
584
585RTLIB::Libcall RTLIB::getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order,
586 MVT VT) {
587 if (!VT.isScalarInteger())
588 return UNKNOWN_LIBCALL;
589 uint64_t MemSize = VT.getScalarSizeInBits() / 8;
590
591#define LCALLS(A, B) \
592 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
593#define LCALL5(A) \
594 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
595 switch (Opc) {
596 case ISD::ATOMIC_CMP_SWAP: {
597 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
598 return getOutlineAtomicHelper(LC, Order, MemSize);
599 }
600 case ISD::ATOMIC_SWAP: {
601 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};
602 return getOutlineAtomicHelper(LC, Order, MemSize);
603 }
604 case ISD::ATOMIC_LOAD_ADD: {
605 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};
606 return getOutlineAtomicHelper(LC, Order, MemSize);
607 }
608 case ISD::ATOMIC_LOAD_OR: {
609 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};
610 return getOutlineAtomicHelper(LC, Order, MemSize);
611 }
612 case ISD::ATOMIC_LOAD_CLR: {
613 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};
614 return getOutlineAtomicHelper(LC, Order, MemSize);
615 }
616 case ISD::ATOMIC_LOAD_XOR: {
617 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};
618 return getOutlineAtomicHelper(LC, Order, MemSize);
619 }
620 default:
621 return UNKNOWN_LIBCALL;
622 }
623#undef LCALLS
624#undef LCALL5
625}
626
627RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
628#define OP_TO_LIBCALL(Name, Enum) \
629 case Name: \
630 switch (VT.SimpleTy) { \
631 default: \
632 return UNKNOWN_LIBCALL; \
633 case MVT::i8: \
634 return Enum##_1; \
635 case MVT::i16: \
636 return Enum##_2; \
637 case MVT::i32: \
638 return Enum##_4; \
639 case MVT::i64: \
640 return Enum##_8; \
641 case MVT::i128: \
642 return Enum##_16; \
643 }
644
645 switch (Opc) {
646 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
647 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
648 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
649 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
650 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
651 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
652 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
653 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
654 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
655 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
656 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
657 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
658 }
659
660#undef OP_TO_LIBCALL
661
662 return UNKNOWN_LIBCALL;
663}
664
665RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
666 switch (ElementSize) {
667 case 1:
668 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
669 case 2:
670 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
671 case 4:
672 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
673 case 8:
674 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
675 case 16:
676 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
677 default:
678 return UNKNOWN_LIBCALL;
679 }
680}
681
682RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
683 switch (ElementSize) {
684 case 1:
685 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
686 case 2:
687 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
688 case 4:
689 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
690 case 8:
691 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
692 case 16:
693 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
694 default:
695 return UNKNOWN_LIBCALL;
696 }
697}
698
699RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
700 switch (ElementSize) {
701 case 1:
702 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
703 case 2:
704 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
705 case 4:
706 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
707 case 8:
708 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
709 case 16:
710 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
711 default:
712 return UNKNOWN_LIBCALL;
713 }
714}
715
716/// NOTE: The TargetMachine owns TLOF.
717TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
718 const TargetSubtargetInfo &STI)
719 : TM(tm),
720 RuntimeLibcallInfo(TM.getTargetTriple(), TM.Options.ExceptionModel,
721 TM.getTargetTriple().getDefaultFloatABI(),
722 TM.Options.EABIVersion,
723 TM.Options.MCOptions.getABIName(), TM.Options.VecLib),
724 Libcalls(RuntimeLibcallInfo, [&STI](LibcallLoweringInfo &Info) {
725 STI.initLibcallLoweringInfo(Info);
726 }) {
727 initActions();
728
729 // Perform these initializations only once.
730 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove =
731 MaxLoadsPerMemcmp = 8;
732 MaxGluedStoresPerMemcpy = 0;
733 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize =
734 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4;
735 HasExtractBitsInsn = false;
736 JumpIsExpensive = JumpIsExpensiveOverride;
737 PredictableSelectIsExpensive = false;
738 EnableExtLdPromotion = false;
739 StackPointerRegisterToSaveRestore = 0;
740 BooleanContents = UndefinedBooleanContent;
741 BooleanFloatContents = UndefinedBooleanContent;
742 BooleanVectorContents = UndefinedBooleanContent;
743 SchedPreferenceInfo = Sched::ILP;
744 GatherAllAliasesMaxDepth = 18;
745 IsStrictFPEnabled = DisableStrictNodeMutation;
746 MaxBytesForAlignment = 0;
747 MaxAtomicSizeInBitsSupported = 0;
748
749 // Assume that even with libcalls, no target supports wider than 128 bit
750 // division.
751 MaxDivRemBitWidthSupported = 128;
752
753 MaxLargeFPConvertBitWidthSupported = 128;
754
755 MinCmpXchgSizeInBits = 0;
756 SupportsUnalignedAtomics = false;
757
758 MinimumBitTestCmps = MinimumBitTestCmpsOverride;
759}
760
761// Define the virtual destructor out-of-line to act as a key method to anchor
762// debug info (see coding standards).
763TargetLoweringBase::~TargetLoweringBase() = default;
764
765void TargetLoweringBase::initActions() {
766 // All operations default to being supported.
767 memset(s: OpActions, c: 0, n: sizeof(OpActions));
768 memset(s: LoadExtActions, c: 0, n: sizeof(LoadExtActions));
769 memset(s: AtomicLoadExtActions, c: 0, n: sizeof(AtomicLoadExtActions));
770 memset(s: TruncStoreActions, c: 0, n: sizeof(TruncStoreActions));
771 memset(s: IndexedModeActions, c: 0, n: sizeof(IndexedModeActions));
772 memset(s: CondCodeActions, c: 0, n: sizeof(CondCodeActions));
773 llvm::fill(Range&: RegClassForVT, Value: nullptr);
774 llvm::fill(Range&: TargetDAGCombineArray, Value: 0);
775
776 // Let extending atomic loads be unsupported by default.
777 for (MVT ValVT : MVT::all_valuetypes())
778 for (MVT MemVT : MVT::all_valuetypes())
779 setAtomicLoadExtAction(ExtTypes: {ISD::SEXTLOAD, ISD::ZEXTLOAD}, ValVT, MemVT,
780 Action: Expand);
781
782 // We're somewhat special casing MVT::i2 and MVT::i4. Ideally we want to
783 // remove this and targets should individually set these types if not legal.
784 for (ISD::NodeType NT : enum_seq(Begin: ISD::DELETED_NODE, End: ISD::BUILTIN_OP_END,
785 force_iteration_on_noniterable_enum)) {
786 for (MVT VT : {MVT::i2, MVT::i4})
787 OpActions[(unsigned)VT.SimpleTy][NT] = Expand;
788 }
789 for (MVT AVT : MVT::all_valuetypes()) {
790 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {
791 setTruncStoreAction(ValVT: AVT, MemVT: VT, Action: Expand);
792 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: AVT, MemVT: VT, Action: Expand);
793 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: AVT, MemVT: VT, Action: Expand);
794 }
795 }
796 for (unsigned IM = (unsigned)ISD::PRE_INC;
797 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
798 for (MVT VT : {MVT::i2, MVT::i4}) {
799 setIndexedLoadAction(IdxModes: IM, VT, Action: Expand);
800 setIndexedStoreAction(IdxModes: IM, VT, Action: Expand);
801 setIndexedMaskedLoadAction(IdxMode: IM, VT, Action: Expand);
802 setIndexedMaskedStoreAction(IdxMode: IM, VT, Action: Expand);
803 }
804 }
805
806 for (MVT VT : MVT::fp_valuetypes()) {
807 MVT IntVT = MVT::getIntegerVT(BitWidth: VT.getFixedSizeInBits());
808 if (IntVT.isValid()) {
809 setOperationAction(Op: ISD::ATOMIC_SWAP, VT, Action: Promote);
810 AddPromotedToType(Opc: ISD::ATOMIC_SWAP, OrigVT: VT, DestVT: IntVT);
811 }
812 }
813
814 // If f16 fma is not natively supported, the value must be promoted to an f64
815 // (and not to f32!) to prevent double rounding issues.
816 AddPromotedToType(Opc: ISD::FMA, OrigVT: MVT::f16, DestVT: MVT::f64);
817 AddPromotedToType(Opc: ISD::STRICT_FMA, OrigVT: MVT::f16, DestVT: MVT::f64);
818
819 // Set default actions for various operations.
820 for (MVT VT : MVT::all_valuetypes()) {
821 // Default all indexed load / store to expand.
822 for (unsigned IM = (unsigned)ISD::PRE_INC;
823 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
824 setIndexedLoadAction(IdxModes: IM, VT, Action: Expand);
825 setIndexedStoreAction(IdxModes: IM, VT, Action: Expand);
826 setIndexedMaskedLoadAction(IdxMode: IM, VT, Action: Expand);
827 setIndexedMaskedStoreAction(IdxMode: IM, VT, Action: Expand);
828 }
829
830 // Most backends expect to see the node which just returns the value loaded.
831 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Action: Expand);
832
833 // clang-format off
834 // These operations default to expand.
835 setOperationAction(Ops: {ISD::FGETSIGN, ISD::CONCAT_VECTORS,
836 ISD::FMINNUM, ISD::FMAXNUM,
837 ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
838 ISD::FMINIMUM, ISD::FMAXIMUM,
839 ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM,
840 ISD::FMAD, ISD::SMIN,
841 ISD::SMAX, ISD::UMIN,
842 ISD::UMAX, ISD::ABS,
843 ISD::FSHL, ISD::FSHR,
844 ISD::SADDSAT, ISD::UADDSAT,
845 ISD::SSUBSAT, ISD::USUBSAT,
846 ISD::SSHLSAT, ISD::USHLSAT,
847 ISD::SMULFIX, ISD::SMULFIXSAT,
848 ISD::UMULFIX, ISD::UMULFIXSAT,
849 ISD::SDIVFIX, ISD::SDIVFIXSAT,
850 ISD::UDIVFIX, ISD::UDIVFIXSAT,
851 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT,
852 ISD::IS_FPCLASS, ISD::FCBRT,
853 ISD::FLOG, ISD::FLOG2,
854 ISD::FLOG10, ISD::FEXP,
855 ISD::FEXP2, ISD::FEXP10,
856 ISD::FFLOOR, ISD::FNEARBYINT,
857 ISD::FCEIL, ISD::FRINT,
858 ISD::FTRUNC, ISD::FROUNDEVEN,
859 ISD::FTAN, ISD::FACOS,
860 ISD::FASIN, ISD::FATAN,
861 ISD::FCOSH, ISD::FSINH,
862 ISD::FTANH, ISD::FATAN2,
863 ISD::FMULADD, ISD::CONVERT_FROM_ARBITRARY_FP,
864 ISD::CONVERT_TO_ARBITRARY_FP,
865 ISD::PSEUDO_FMIN, ISD::PSEUDO_FMAX},
866 VT, Action: Expand);
867 // clang-format on
868
869 // Overflow operations default to expand
870 setOperationAction(Ops: {ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO,
871 ISD::SMULO, ISD::UMULO},
872 VT, Action: Expand);
873
874 // Carry-using overflow operations default to expand.
875 setOperationAction(Ops: {ISD::UADDO_CARRY, ISD::USUBO_CARRY, ISD::SETCCCARRY,
876 ISD::SADDO_CARRY, ISD::SSUBO_CARRY},
877 VT, Action: Expand);
878
879 // ADDC/ADDE/SUBC/SUBE default to expand.
880 setOperationAction(Ops: {ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT,
881 Action: Expand);
882
883 // [US]CMP default to expand
884 setOperationAction(Ops: {ISD::UCMP, ISD::SCMP}, VT, Action: Expand);
885
886 // Halving adds
887 setOperationAction(
888 Ops: {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT,
889 Action: Expand);
890
891 // Absolute difference
892 setOperationAction(Ops: {ISD::ABDS, ISD::ABDU}, VT, Action: Expand);
893
894 // Carry-less multiply
895 setOperationAction(Ops: {ISD::CLMUL, ISD::CLMULR, ISD::CLMULH}, VT, Action: Expand);
896
897 // Bit extract/deposit (compress/expand)
898 setOperationAction(Ops: {ISD::PEXT, ISD::PDEP}, VT, Action: Expand);
899
900 // Saturated trunc
901 setOperationAction(Op: ISD::TRUNCATE_SSAT_S, VT, Action: Expand);
902 setOperationAction(Op: ISD::TRUNCATE_SSAT_U, VT, Action: Expand);
903 setOperationAction(Op: ISD::TRUNCATE_USAT_U, VT, Action: Expand);
904
905 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
906 setOperationAction(Ops: {ISD::CTLZ_ZERO_POISON, ISD::CTTZ_ZERO_POISON}, VT,
907 Action: Expand);
908
909 // This defaults to Expand so it will be expanded to ABS by default.
910 setOperationAction(Op: ISD::ABS_MIN_POISON, VT, Action: Expand);
911 setOperationAction(Op: ISD::CTLS, VT, Action: Expand);
912
913 setOperationAction(Ops: {ISD::BITREVERSE, ISD::PARITY}, VT, Action: Expand);
914
915 // These library functions default to expand.
916 setOperationAction(Ops: {ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP,
917 ISD::FSINCOS, ISD::FSINCOSPI, ISD::FMODF},
918 VT, Action: Expand);
919
920 // These operations default to expand for vector types.
921 if (VT.isVector())
922 setOperationAction(Ops: {ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG,
923 ISD::ANY_EXTEND_VECTOR_INREG,
924 ISD::SIGN_EXTEND_VECTOR_INREG,
925 ISD::ZERO_EXTEND_VECTOR_INREG, ISD::SPLAT_VECTOR,
926 ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
927 VT, Action: Expand);
928
929 // Constrained floating-point operations default to expand.
930#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
931 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
932#include "llvm/IR/ConstrainedOps.def"
933 setOperationAction(Op: ISD::STRICT_PSEUDO_FMIN, VT, Action: Expand);
934 setOperationAction(Op: ISD::STRICT_PSEUDO_FMAX, VT, Action: Expand);
935
936 // For most targets @llvm.get.dynamic.area.offset just returns 0.
937 setOperationAction(Op: ISD::GET_DYNAMIC_AREA_OFFSET, VT, Action: Expand);
938
939 // Vector reduction default to expand.
940 setOperationAction(
941 Ops: {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD,
942 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR,
943 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN,
944 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX,
945 ISD::VECREDUCE_FMIN, ISD::VECREDUCE_FMAXIMUM, ISD::VECREDUCE_FMINIMUM,
946 ISD::VECREDUCE_FMAXIMUMNUM, ISD::VECREDUCE_FMINIMUMNUM,
947 ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_SEQ_FMUL},
948 VT, Action: Expand);
949
950 // Named vector shuffles default to expand.
951 setOperationAction(Ops: {ISD::VECTOR_SPLICE_LEFT, ISD::VECTOR_SPLICE_RIGHT}, VT,
952 Action: Expand);
953
954 // Only some target support these vector operations. Default them to Expand.
955 setOperationAction(Ops: {ISD::VECTOR_COMPRESS, ISD::VECTOR_MATCH}, VT, Action: Expand);
956
957 // cttz.elts defaults to expand.
958 setOperationAction(Ops: {ISD::CTTZ_ELTS, ISD::CTTZ_ELTS_ZERO_POISON}, VT,
959 Action: Expand);
960
961 // VP operations default to expand.
962#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \
963 setOperationAction(ISD::SDOPC, VT, Expand);
964#include "llvm/IR/VPIntrinsics.def"
965
966 // Masked vector extracts default to expand.
967 setOperationAction(Op: ISD::VECTOR_FIND_LAST_ACTIVE, VT, Action: Expand);
968
969 setOperationAction(Op: ISD::LOOP_DEPENDENCE_RAW_MASK, VT, Action: Expand);
970 setOperationAction(Op: ISD::LOOP_DEPENDENCE_WAR_MASK, VT, Action: Expand);
971
972 // FP environment operations default to expand.
973 setOperationAction(Op: ISD::GET_FPENV, VT, Action: Expand);
974 setOperationAction(Op: ISD::SET_FPENV, VT, Action: Expand);
975 setOperationAction(Op: ISD::RESET_FPENV, VT, Action: Expand);
976
977 setOperationAction(Op: ISD::MSTORE, VT, Action: Expand);
978
979 setOperationAction(Op: ISD::MASKED_UDIV, VT, Action: Expand);
980 setOperationAction(Op: ISD::MASKED_SDIV, VT, Action: Expand);
981 setOperationAction(Op: ISD::MASKED_UREM, VT, Action: Expand);
982 setOperationAction(Op: ISD::MASKED_SREM, VT, Action: Expand);
983 }
984
985 // Most targets ignore the @llvm.prefetch intrinsic.
986 setOperationAction(Op: ISD::PREFETCH, VT: MVT::Other, Action: Expand);
987
988 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
989 setOperationAction(Op: ISD::READCYCLECOUNTER, VT: MVT::i64, Action: Expand);
990
991 // Most targets also ignore the @llvm.readsteadycounter intrinsic.
992 setOperationAction(Op: ISD::READSTEADYCOUNTER, VT: MVT::i64, Action: Expand);
993
994 // ConstantFP nodes default to expand. Targets can either change this to
995 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
996 // to optimize expansions for certain constants.
997 setOperationAction(Ops: ISD::ConstantFP,
998 VTs: {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},
999 Action: Expand);
1000
1001 // Insert custom handling default for llvm.canonicalize.*.
1002 setOperationAction(Ops: ISD::FCANONICALIZE,
1003 VTs: {MVT::f16, MVT::f32, MVT::f64, MVT::f128}, Action: Expand);
1004
1005 // FIXME: Query RuntimeLibCalls to make the decision.
1006 setOperationAction(Ops: {ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
1007 VTs: {MVT::f32, MVT::f64, MVT::f128}, Action: LibCall);
1008
1009 setOperationAction(Ops: {ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH,
1010 ISD::FSINH, ISD::FTANH, ISD::FATAN2},
1011 VT: MVT::f16, Action: Promote);
1012 // Default ISD::TRAP to expand (which turns it into abort).
1013 setOperationAction(Op: ISD::TRAP, VT: MVT::Other, Action: Expand);
1014
1015 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
1016 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
1017 setOperationAction(Op: ISD::DEBUGTRAP, VT: MVT::Other, Action: Expand);
1018
1019 setOperationAction(Op: ISD::UBSANTRAP, VT: MVT::Other, Action: Expand);
1020
1021 setOperationAction(Op: ISD::GET_FPENV_MEM, VT: MVT::Other, Action: Expand);
1022 setOperationAction(Op: ISD::SET_FPENV_MEM, VT: MVT::Other, Action: Expand);
1023
1024 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
1025 setOperationAction(Op: ISD::GET_FPMODE, VT, Action: Expand);
1026 setOperationAction(Op: ISD::SET_FPMODE, VT, Action: Expand);
1027 }
1028 setOperationAction(Op: ISD::RESET_FPMODE, VT: MVT::Other, Action: Expand);
1029
1030 // This one by default will call __clear_cache unless the target
1031 // wants something different.
1032 setOperationAction(Op: ISD::CLEAR_CACHE, VT: MVT::Other, Action: LibCall);
1033
1034 // By default, STACKADDRESS nodes are expanded like STACKSAVE nodes.
1035 // On SPARC targets, custom lowering is required.
1036 setOperationAction(Op: ISD::STACKADDRESS, VT: MVT::Other, Action: Expand);
1037}
1038
1039MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
1040 EVT) const {
1041 return MVT::getIntegerVT(BitWidth: DL.getPointerSizeInBits(AS: 0));
1042}
1043
1044EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,
1045 const DataLayout &DL) const {
1046 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
1047 if (LHSTy.isVector())
1048 return LHSTy;
1049 MVT ShiftVT = getScalarShiftAmountTy(DL, LHSTy);
1050 // If any possible shift value won't fit in the prefered type, just use
1051 // something safe. Assume it will be legalized when the shift is expanded.
1052 if (ShiftVT.getSizeInBits() < Log2_32_Ceil(Value: LHSTy.getSizeInBits()))
1053 ShiftVT = MVT::i32;
1054 assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) &&
1055 "ShiftVT is still too small!");
1056 return ShiftVT;
1057}
1058
1059bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
1060 assert(isTypeLegal(VT));
1061 switch (Op) {
1062 default:
1063 return false;
1064 case ISD::SDIV:
1065 case ISD::UDIV:
1066 case ISD::SREM:
1067 case ISD::UREM:
1068 return true;
1069 }
1070}
1071
1072bool TargetLoweringBase::isFreeAddrSpaceCast(unsigned SrcAS,
1073 unsigned DestAS) const {
1074 return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
1075}
1076
1077unsigned TargetLoweringBase::getBitWidthForCttzElements(
1078 EVT RetVT, ElementCount EC, bool ZeroIsPoison,
1079 const ConstantRange *VScaleRange) const {
1080 // Find the smallest "sensible" element type to use for the expansion.
1081 ConstantRange CR(APInt(64, EC.getKnownMinValue()));
1082 if (EC.isScalable())
1083 CR = CR.umul_sat(Other: *VScaleRange);
1084
1085 if (ZeroIsPoison)
1086 CR = CR.subtract(CI: APInt(64, 1));
1087
1088 unsigned EltWidth = RetVT.getScalarSizeInBits();
1089 EltWidth = std::min(a: EltWidth, b: CR.getActiveBits());
1090 EltWidth = std::max(a: llvm::bit_ceil(Value: EltWidth), b: (unsigned)8);
1091
1092 return EltWidth;
1093}
1094
1095void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
1096 // If the command-line option was specified, ignore this request.
1097 if (!JumpIsExpensiveOverride.getNumOccurrences())
1098 JumpIsExpensive = isExpensive;
1099}
1100
1101TargetLoweringBase::LegalizeKind
1102TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
1103 // If this is a simple type, use the ComputeRegisterProp mechanism.
1104 if (VT.isSimple()) {
1105 MVT SVT = VT.getSimpleVT();
1106 assert((unsigned)SVT.SimpleTy < std::size(TransformToType));
1107 MVT NVT = TransformToType[SVT.SimpleTy];
1108 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(VT: SVT);
1109
1110 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
1111 LA == TypeSoftPromoteHalf ||
1112 (NVT.isVector() ||
1113 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
1114 "Promote may not follow Expand or Promote");
1115
1116 if (LA == TypeSplitVector)
1117 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
1118 if (LA == TypeScalarizeVector)
1119 return LegalizeKind(LA, SVT.getVectorElementType());
1120 return LegalizeKind(LA, NVT);
1121 }
1122
1123 // Handle Extended Scalar Types.
1124 if (!VT.isVector()) {
1125 assert(VT.isInteger() && "Float types must be simple");
1126 unsigned BitSize = VT.getSizeInBits();
1127 // First promote to a power-of-two size, then expand if necessary.
1128 if (BitSize < 8 || !isPowerOf2_32(Value: BitSize)) {
1129 EVT NVT = VT.getRoundIntegerType(Context);
1130 assert(NVT != VT && "Unable to round integer VT");
1131 LegalizeKind NextStep = getTypeConversion(Context, VT: NVT);
1132 // Avoid multi-step promotion.
1133 if (NextStep.first == TypePromoteInteger)
1134 return NextStep;
1135 // Return rounded integer type.
1136 return LegalizeKind(TypePromoteInteger, NVT);
1137 }
1138
1139 return LegalizeKind(TypeExpandInteger,
1140 EVT::getIntegerVT(Context, BitWidth: VT.getSizeInBits() / 2));
1141 }
1142
1143 // Handle vector types.
1144 ElementCount NumElts = VT.getVectorElementCount();
1145 EVT EltVT = VT.getVectorElementType();
1146
1147 // Vectors with only one element are always scalarized.
1148 if (NumElts.isScalar())
1149 return LegalizeKind(TypeScalarizeVector, EltVT);
1150
1151 // Try to widen vector elements until the element type is a power of two and
1152 // promote it to a legal type later on, for example:
1153 // <3 x i8> -> <4 x i8> -> <4 x i32>
1154 if (EltVT.isInteger()) {
1155 // Vectors with a number of elements that is not a power of two are always
1156 // widened, for example <3 x i8> -> <4 x i8>.
1157 if (!VT.isPow2VectorType()) {
1158 NumElts = NumElts.coefficientNextPowerOf2();
1159 EVT NVT = EVT::getVectorVT(Context, VT: EltVT, EC: NumElts);
1160 return LegalizeKind(TypeWidenVector, NVT);
1161 }
1162
1163 // Examine the element type.
1164 LegalizeKind LK = getTypeConversion(Context, VT: EltVT);
1165
1166 // If type is to be expanded, split the vector.
1167 // <4 x i140> -> <2 x i140>
1168 if (LK.first == TypeExpandInteger) {
1169 if (NumElts.isScalable() && NumElts.getKnownMinValue() == 1)
1170 return LegalizeKind(TypeScalarizeScalableVector, EltVT);
1171 return LegalizeKind(TypeSplitVector,
1172 VT.getHalfNumVectorElementsVT(Context));
1173 }
1174
1175 // Promote the integer element types until a legal vector type is found
1176 // or until the element integer type is too big. If a legal type was not
1177 // found, fallback to the usual mechanism of widening/splitting the
1178 // vector.
1179 EVT OldEltVT = EltVT;
1180 while (true) {
1181 // Increase the bitwidth of the element to the next pow-of-two
1182 // (which is greater than 8 bits).
1183 EltVT = EVT::getIntegerVT(Context, BitWidth: 1 + EltVT.getSizeInBits())
1184 .getRoundIntegerType(Context);
1185
1186 // Stop trying when getting a non-simple element type.
1187 // Note that vector elements may be greater than legal vector element
1188 // types. Example: X86 XMM registers hold 64bit element on 32bit
1189 // systems.
1190 if (!EltVT.isSimple())
1191 break;
1192
1193 // Build a new vector type and check if it is legal.
1194 MVT NVT = MVT::getVectorVT(VT: EltVT.getSimpleVT(), EC: NumElts);
1195 // Found a legal promoted vector type.
1196 if (NVT != MVT() && ValueTypeActions.getTypeAction(VT: NVT) == TypeLegal)
1197 return LegalizeKind(TypePromoteInteger,
1198 EVT::getVectorVT(Context, VT: EltVT, EC: NumElts));
1199 }
1200
1201 // Reset the type to the unexpanded type if we did not find a legal vector
1202 // type with a promoted vector element type.
1203 EltVT = OldEltVT;
1204 }
1205
1206 // Try to widen the vector until a legal type is found.
1207 // If there is no wider legal type, split the vector.
1208 while (true) {
1209 // Round up to the next power of 2.
1210 NumElts = NumElts.coefficientNextPowerOf2();
1211
1212 // If there is no simple vector type with this many elements then there
1213 // cannot be a larger legal vector type. Note that this assumes that
1214 // there are no skipped intermediate vector types in the simple types.
1215 if (!EltVT.isSimple())
1216 break;
1217 MVT LargerVector = MVT::getVectorVT(VT: EltVT.getSimpleVT(), EC: NumElts);
1218 if (LargerVector == MVT())
1219 break;
1220
1221 // If this type is legal then widen the vector.
1222 if (ValueTypeActions.getTypeAction(VT: LargerVector) == TypeLegal)
1223 return LegalizeKind(TypeWidenVector, LargerVector);
1224 }
1225
1226 // Widen odd vectors to next power of two.
1227 if (!VT.isPow2VectorType()) {
1228 EVT NVT = VT.getPow2VectorType(Context);
1229 return LegalizeKind(TypeWidenVector, NVT);
1230 }
1231
1232 if (VT.getVectorElementCount() == ElementCount::getScalable(MinVal: 1))
1233 return LegalizeKind(TypeScalarizeScalableVector, EltVT);
1234
1235 // Vectors with illegal element types are expanded.
1236 EVT NVT = EVT::getVectorVT(Context, VT: EltVT,
1237 EC: VT.getVectorElementCount().divideCoefficientBy(RHS: 2));
1238 return LegalizeKind(TypeSplitVector, NVT);
1239}
1240
1241unsigned TargetLoweringBase::getVectorTypeBreakdownMVT(
1242 MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) {
1243 // Figure out the right, legal destination reg to copy into.
1244 ElementCount EC = VT.getVectorElementCount();
1245 MVT EltTy = VT.getVectorElementType();
1246
1247 unsigned NumVectorRegs = 1;
1248
1249 // Scalable vectors cannot be scalarized, so splitting or widening is
1250 // required.
1251 if (VT.isScalableVector() && !isPowerOf2_32(Value: EC.getKnownMinValue()))
1252 llvm_unreachable(
1253 "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1254
1255 // FIXME: We don't support non-power-of-2-sized vectors for now.
1256 // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1257 if (!isPowerOf2_32(Value: EC.getKnownMinValue())) {
1258 // Split EC to unit size (scalable property is preserved).
1259 NumVectorRegs = EC.getKnownMinValue();
1260 EC = ElementCount::getFixed(MinVal: 1);
1261 }
1262
1263 // Divide the input until we get to a supported size. This will
1264 // always end up with an EC that represent a scalar or a scalable
1265 // scalar.
1266 while (EC.getKnownMinValue() > 1 &&
1267 !isTypeLegal(VT: MVT::getVectorVT(VT: EltTy, EC))) {
1268 EC = EC.divideCoefficientBy(RHS: 2);
1269 NumVectorRegs <<= 1;
1270 }
1271
1272 NumIntermediates = NumVectorRegs;
1273
1274 MVT NewVT = MVT::getVectorVT(VT: EltTy, EC);
1275 if (!isTypeLegal(VT: NewVT))
1276 NewVT = EltTy;
1277 IntermediateVT = NewVT;
1278
1279 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
1280
1281 // Convert sizes such as i33 to i64.
1282 LaneSizeInBits = llvm::bit_ceil(Value: LaneSizeInBits);
1283
1284 MVT DestVT = getCachedRegisterType(VT: NewVT);
1285 RegisterVT = DestVT;
1286 if (EVT(DestVT).bitsLT(VT: NewVT)) // Value is expanded, e.g. i64 -> i16.
1287 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1288
1289 // Otherwise, promotion or legal types use the same number of registers as
1290 // the vector decimated to the appropriate level.
1291 return NumVectorRegs;
1292}
1293
1294/// isLegalRC - Return true if the value types that can be represented by the
1295/// specified register class are all legal.
1296bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
1297 const TargetRegisterClass &RC) const {
1298 for (const auto *I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1299 if (isTypeLegal(VT: *I))
1300 return true;
1301 return false;
1302}
1303
1304/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1305/// sequence of memory operands that is recognized by PrologEpilogInserter.
1306MachineBasicBlock *
1307TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
1308 MachineBasicBlock *MBB) const {
1309 MachineInstr *MI = &InitialMI;
1310 MachineFunction &MF = *MI->getMF();
1311 MachineFrameInfo &MFI = MF.getFrameInfo();
1312
1313 // We're handling multiple types of operands here:
1314 // PATCHPOINT MetaArgs - live-in, read only, direct
1315 // STATEPOINT Deopt Spill - live-through, read only, indirect
1316 // STATEPOINT Deopt Alloca - live-through, read only, direct
1317 // (We're currently conservative and mark the deopt slots read/write in
1318 // practice.)
1319 // STATEPOINT GC Spill - live-through, read/write, indirect
1320 // STATEPOINT GC Alloca - live-through, read/write, direct
1321 // The live-in vs live-through is handled already (the live through ones are
1322 // all stack slots), but we need to handle the different type of stackmap
1323 // operands and memory effects here.
1324
1325 if (llvm::none_of(Range: MI->operands(),
1326 P: [](MachineOperand &Operand) { return Operand.isFI(); }))
1327 return MBB;
1328
1329 MachineInstrBuilder MIB = BuildMI(MF, MIMD: MI->getDebugLoc(), MCID: MI->getDesc());
1330
1331 // Inherit previous memory operands.
1332 MIB.cloneMemRefs(OtherMI: *MI);
1333
1334 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1335 MachineOperand &MO = MI->getOperand(i);
1336 if (!MO.isFI()) {
1337 // Index of Def operand this Use it tied to.
1338 // Since Defs are coming before Uses, if Use is tied, then
1339 // index of Def must be smaller that index of that Use.
1340 // Also, Defs preserve their position in new MI.
1341 unsigned TiedTo = i;
1342 if (MO.isReg() && MO.isTied())
1343 TiedTo = MI->findTiedOperandIdx(OpIdx: i);
1344 MIB.add(MO);
1345 if (TiedTo < i)
1346 MIB->tieOperands(DefIdx: TiedTo, UseIdx: MIB->getNumOperands() - 1);
1347 continue;
1348 }
1349
1350 // foldMemoryOperand builds a new MI after replacing a single FI operand
1351 // with the canonical set of five x86 addressing-mode operands.
1352 int FI = MO.getIndex();
1353
1354 // Add frame index operands recognized by stackmaps.cpp
1355 if (MFI.isStatepointSpillSlotObjectIndex(ObjectIdx: FI)) {
1356 // indirect-mem-ref tag, size, #FI, offset.
1357 // Used for spills inserted by StatepointLowering. This codepath is not
1358 // used for patchpoints/stackmaps at all, for these spilling is done via
1359 // foldMemoryOperand callback only.
1360 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1361 MIB.addImm(Val: StackMaps::IndirectMemRefOp);
1362 MIB.addImm(Val: MFI.getObjectSize(ObjectIdx: FI));
1363 MIB.add(MO);
1364 MIB.addImm(Val: 0);
1365 } else {
1366 // direct-mem-ref tag, #FI, offset.
1367 // Used by patchpoint, and direct alloca arguments to statepoints
1368 MIB.addImm(Val: StackMaps::DirectMemRefOp);
1369 MIB.add(MO);
1370 MIB.addImm(Val: 0);
1371 }
1372
1373 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1374
1375 // Add a new memory operand for this FI.
1376 assert(MFI.getObjectOffset(FI) != -1);
1377
1378 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1379 // PATCHPOINT should be updated to do the same. (TODO)
1380 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1381 auto Flags = MachineMemOperand::MOLoad;
1382 MachineMemOperand *MMO = MF.getMachineMemOperand(
1383 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI), F: Flags,
1384 Size: MF.getDataLayout().getPointerSize(), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
1385 MIB->addMemOperand(MF, MO: MMO);
1386 }
1387 }
1388 MBB->insert(I: MachineBasicBlock::iterator(MI), MI: MIB);
1389 MI->eraseFromParent();
1390 return MBB;
1391}
1392
1393/// findRepresentativeClass - Return the largest legal super-reg register class
1394/// of the register class for the specified type and its associated "cost".
1395// This function is in TargetLowering because it uses RegClassForVT which would
1396// need to be moved to TargetRegisterInfo and would necessitate moving
1397// isTypeLegal over as well - a massive change that would just require
1398// TargetLowering having a TargetRegisterInfo class member that it would use.
1399std::pair<const TargetRegisterClass *, uint8_t>
1400TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1401 MVT VT) const {
1402 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1403 if (!RC)
1404 return std::make_pair(x&: RC, y: 0);
1405
1406 // Compute the set of all super-register classes.
1407 BitVector SuperRegRC(TRI->getNumRegClasses());
1408 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1409 SuperRegRC.setBitsInMask(Mask: RCI.getMask());
1410
1411 // Find the first legal register class with the largest spill size.
1412 const TargetRegisterClass *BestRC = RC;
1413 for (unsigned i : SuperRegRC.set_bits()) {
1414 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1415 // We want the largest possible spill size.
1416 if (TRI->getSpillSize(RC: *SuperRC) <= TRI->getSpillSize(RC: *BestRC))
1417 continue;
1418 if (!isLegalRC(TRI: *TRI, RC: *SuperRC))
1419 continue;
1420 BestRC = SuperRC;
1421 }
1422 return std::make_pair(x&: BestRC, y: 1);
1423}
1424
1425/// computeRegisterProperties - Once all of the register classes are added,
1426/// this allows us to compute derived properties we expose.
1427void TargetLoweringBase::computeRegisterProperties(
1428 const TargetRegisterInfo *TRI) {
1429 // Everything defaults to needing one register.
1430 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1431 NumRegistersForVT[i] = 1;
1432 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1433 }
1434 // ...except isVoid, which doesn't need any registers.
1435 NumRegistersForVT[MVT::isVoid] = 0;
1436
1437 // Find the largest integer register class.
1438 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1439 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1440 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1441
1442 // Every integer value type larger than this largest register takes twice as
1443 // many registers to represent as the previous ValueType.
1444 for (unsigned ExpandedReg = LargestIntReg + 1;
1445 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1446 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1447 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1448 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1449 ValueTypeActions.setTypeAction(VT: (MVT::SimpleValueType)ExpandedReg,
1450 Action: TypeExpandInteger);
1451 }
1452
1453 // Inspect all of the ValueType's smaller than the largest integer
1454 // register to see which ones need promotion.
1455 unsigned LegalIntReg = LargestIntReg;
1456 for (unsigned IntReg = LargestIntReg - 1;
1457 IntReg >= (unsigned)MVT::i1; --IntReg) {
1458 MVT IVT = (MVT::SimpleValueType)IntReg;
1459 if (isTypeLegal(VT: IVT)) {
1460 LegalIntReg = IntReg;
1461 } else {
1462 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1463 (MVT::SimpleValueType)LegalIntReg;
1464 ValueTypeActions.setTypeAction(VT: IVT, Action: TypePromoteInteger);
1465 }
1466 }
1467
1468 // ppcf128 type is really two f64's.
1469 if (!isTypeLegal(VT: MVT::ppcf128)) {
1470 if (isTypeLegal(VT: MVT::f64)) {
1471 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1472 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1473 TransformToType[MVT::ppcf128] = MVT::f64;
1474 ValueTypeActions.setTypeAction(VT: MVT::ppcf128, Action: TypeExpandFloat);
1475 } else {
1476 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1477 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1478 TransformToType[MVT::ppcf128] = MVT::i128;
1479 ValueTypeActions.setTypeAction(VT: MVT::ppcf128, Action: TypeSoftenFloat);
1480 }
1481 }
1482
1483 // Decide how to handle f128. If the target does not have native f128 support,
1484 // expand it to i128 and we will be generating soft float library calls.
1485 if (!isTypeLegal(VT: MVT::f128)) {
1486 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1487 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1488 TransformToType[MVT::f128] = MVT::i128;
1489 ValueTypeActions.setTypeAction(VT: MVT::f128, Action: TypeSoftenFloat);
1490 }
1491
1492 // Decide how to handle f80. If the target does not have native f80 support,
1493 // expand it to i96 and we will be generating soft float library calls.
1494 if (!isTypeLegal(VT: MVT::f80)) {
1495 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];
1496 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];
1497 TransformToType[MVT::f80] = MVT::i32;
1498 ValueTypeActions.setTypeAction(VT: MVT::f80, Action: TypeSoftenFloat);
1499 }
1500
1501 // Decide how to handle f64. If the target does not have native f64 support,
1502 // expand it to i64 and we will be generating soft float library calls.
1503 if (!isTypeLegal(VT: MVT::f64)) {
1504 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1505 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1506 TransformToType[MVT::f64] = MVT::i64;
1507 ValueTypeActions.setTypeAction(VT: MVT::f64, Action: TypeSoftenFloat);
1508 }
1509
1510 // Decide how to handle f32. If the target does not have native f32 support,
1511 // expand it to i32 and we will be generating soft float library calls.
1512 if (!isTypeLegal(VT: MVT::f32)) {
1513 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1514 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1515 TransformToType[MVT::f32] = MVT::i32;
1516 ValueTypeActions.setTypeAction(VT: MVT::f32, Action: TypeSoftenFloat);
1517 }
1518
1519 // Decide how to handle f16. If the target does not have native f16 support,
1520 // promote it to f32, because there are no f16 library calls (except for
1521 // conversions).
1522 if (!isTypeLegal(VT: MVT::f16)) {
1523 // Allow targets to control how we legalize half.
1524 bool UseFPRegsForHalfType = useFPRegsForHalfType();
1525
1526 if (!UseFPRegsForHalfType) {
1527 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1528 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1529 } else {
1530 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1531 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1532 }
1533 TransformToType[MVT::f16] = MVT::f32;
1534 ValueTypeActions.setTypeAction(VT: MVT::f16, Action: TypeSoftPromoteHalf);
1535 }
1536
1537 // Decide how to handle bf16. If the target does not have native bf16 support,
1538 // promote it to f32, because there are no bf16 library calls (except for
1539 // converting from f32 to bf16).
1540 if (!isTypeLegal(VT: MVT::bf16)) {
1541 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];
1542 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];
1543 TransformToType[MVT::bf16] = MVT::f32;
1544 ValueTypeActions.setTypeAction(VT: MVT::bf16, Action: TypeSoftPromoteHalf);
1545 }
1546
1547 // Loop over all of the vector value types to see which need transformations.
1548 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1549 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1550 MVT VT = (MVT::SimpleValueType) i;
1551 if (isTypeLegal(VT))
1552 continue;
1553
1554 MVT EltVT = VT.getVectorElementType();
1555 ElementCount EC = VT.getVectorElementCount();
1556 bool IsLegalWiderType = false;
1557 bool IsScalable = VT.isScalableVector();
1558 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1559 switch (PreferredAction) {
1560 case TypePromoteInteger: {
1561 MVT::SimpleValueType EndVT = IsScalable ?
1562 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :
1563 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;
1564 // Try to promote the elements of integer vectors. If no legal
1565 // promotion was found, fall through to the widen-vector method.
1566 for (unsigned nVT = i + 1;
1567 (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1568 MVT SVT = (MVT::SimpleValueType) nVT;
1569 // Promote vectors of integers to vectors with the same number
1570 // of elements, with a wider element type.
1571 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1572 SVT.getVectorElementCount() == EC && isTypeLegal(VT: SVT)) {
1573 TransformToType[i] = SVT;
1574 RegisterTypeForVT[i] = SVT;
1575 NumRegistersForVT[i] = 1;
1576 ValueTypeActions.setTypeAction(VT, Action: TypePromoteInteger);
1577 IsLegalWiderType = true;
1578 break;
1579 }
1580 }
1581 if (IsLegalWiderType)
1582 break;
1583 [[fallthrough]];
1584 }
1585
1586 case TypeWidenVector:
1587 if (isPowerOf2_32(Value: EC.getKnownMinValue())) {
1588 // Try to widen the vector.
1589 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1590 MVT SVT = (MVT::SimpleValueType) nVT;
1591 if (SVT.getVectorElementType() == EltVT &&
1592 SVT.isScalableVector() == IsScalable &&
1593 SVT.getVectorElementCount().getKnownMinValue() >
1594 EC.getKnownMinValue() &&
1595 isTypeLegal(VT: SVT)) {
1596 TransformToType[i] = SVT;
1597 RegisterTypeForVT[i] = SVT;
1598 NumRegistersForVT[i] = 1;
1599 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1600 IsLegalWiderType = true;
1601 break;
1602 }
1603 }
1604 if (IsLegalWiderType)
1605 break;
1606 } else {
1607 // Only widen to the next power of 2 to keep consistency with EVT.
1608 MVT NVT = VT.getPow2VectorType();
1609 if (isTypeLegal(VT: NVT)) {
1610 TransformToType[i] = NVT;
1611 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1612 RegisterTypeForVT[i] = NVT;
1613 NumRegistersForVT[i] = 1;
1614 break;
1615 }
1616 }
1617 [[fallthrough]];
1618
1619 case TypeSplitVector:
1620 case TypeScalarizeVector: {
1621 MVT IntermediateVT;
1622 MVT RegisterVT;
1623 unsigned NumIntermediates;
1624 unsigned NumRegisters = getVectorTypeBreakdownMVT(
1625 VT, IntermediateVT, NumIntermediates, RegisterVT);
1626 NumRegistersForVT[i] = NumRegisters;
1627 assert(NumRegistersForVT[i] == NumRegisters &&
1628 "NumRegistersForVT size cannot represent NumRegisters!");
1629 RegisterTypeForVT[i] = RegisterVT;
1630
1631 MVT NVT = VT.getPow2VectorType();
1632 if (NVT == VT) {
1633 // Type is already a power of 2. The default action is to split.
1634 TransformToType[i] = MVT::Other;
1635 if (PreferredAction == TypeScalarizeVector)
1636 ValueTypeActions.setTypeAction(VT, Action: TypeScalarizeVector);
1637 else if (PreferredAction == TypeSplitVector)
1638 ValueTypeActions.setTypeAction(VT, Action: TypeSplitVector);
1639 else if (EC.getKnownMinValue() > 1)
1640 ValueTypeActions.setTypeAction(VT, Action: TypeSplitVector);
1641 else
1642 ValueTypeActions.setTypeAction(VT, Action: EC.isScalable()
1643 ? TypeScalarizeScalableVector
1644 : TypeScalarizeVector);
1645 } else {
1646 TransformToType[i] = NVT;
1647 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1648 }
1649 break;
1650 }
1651 default:
1652 llvm_unreachable("Unknown vector legalization action!");
1653 }
1654 }
1655
1656 // Determine the 'representative' register class for each value type.
1657 // An representative register class is the largest (meaning one which is
1658 // not a sub-register class / subreg register class) legal register class for
1659 // a group of value types. For example, on i386, i8, i16, and i32
1660 // representative would be GR32; while on x86_64 it's GR64.
1661 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1662 const TargetRegisterClass* RRC;
1663 uint8_t Cost;
1664 std::tie(args&: RRC, args&: Cost) = findRepresentativeClass(TRI, VT: (MVT::SimpleValueType)i);
1665 RepRegClassForVT[i] = RRC;
1666 RepRegClassCostForVT[i] = Cost;
1667 }
1668
1669 // Compute minimum known-legal store size.
1670 MaximumLegalStoreInBits = 0;
1671 for (MVT VT : MVT::all_valuetypes())
1672 if (VT != MVT::Other && isTypeLegal(VT) &&
1673 VT.getSizeInBits().getKnownMinValue() >= MaximumLegalStoreInBits)
1674 MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinValue();
1675}
1676
1677EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1678 EVT VT) const {
1679 assert(!VT.isVector() && "No default SetCC type for vectors!");
1680 return getPointerTy(DL).SimpleTy;
1681}
1682
1683/// getVectorTypeBreakdown - Vector types are broken down into some number of
1684/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1685/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1686/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1687///
1688/// This method returns the number of registers needed, and the VT for each
1689/// register. It also returns the VT and quantity of the intermediate values
1690/// before they are promoted/expanded.
1691unsigned TargetLoweringBase::getVectorTypeBreakdownImpl(
1692 LLVMContext &Context, EVT VT, EVT &IntermediateVT,
1693 unsigned &NumIntermediates, MVT &RegisterVT, bool ForCallingConv) const {
1694 ElementCount EltCnt = VT.getVectorElementCount();
1695
1696 // If there is a wider vector type with the same element type as this one,
1697 // or a promoted vector type that has the same number of elements which
1698 // are wider, then we should convert to that legal vector type.
1699 // This handles things like <2 x float> -> <4 x float> and
1700 // <4 x i1> -> <4 x i32>.
1701 LegalizeTypeAction TA = getTypeAction(Context, VT);
1702 if (!EltCnt.isScalar() &&
1703 (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1704 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1705 if (isTypeLegal(VT: RegisterEVT)) {
1706 IntermediateVT = RegisterEVT;
1707 RegisterVT = RegisterEVT.getSimpleVT();
1708 NumIntermediates = 1;
1709 return 1;
1710 }
1711 }
1712
1713 // Figure out the right, legal destination reg to copy into.
1714 EVT EltTy = VT.getVectorElementType();
1715
1716 unsigned NumVectorRegs = 1;
1717
1718 auto GetLegalVectorBreakdown = [&]() -> std::optional<unsigned> {
1719 LegalizeKind LK;
1720 EVT PartVT = VT;
1721 do {
1722 // Iterate until we've found a legal (part) type to hold VT.
1723 LK = getTypeConversion(Context, VT: PartVT);
1724 PartVT = LK.second;
1725 } while (LK.first != TypeLegal);
1726
1727 if (!PartVT.isVector())
1728 return std::nullopt;
1729
1730 assert(PartVT.isScalableVector() == VT.isScalableVector() &&
1731 "Vector legalization changed scalability");
1732 NumIntermediates =
1733 divideCeil(Numerator: VT.getVectorElementCount().getKnownMinValue(),
1734 Denominator: PartVT.getVectorElementCount().getKnownMinValue());
1735 IntermediateVT = PartVT;
1736 RegisterVT = getRegisterType(Context, VT: IntermediateVT);
1737 return NumIntermediates;
1738 };
1739
1740 // Scalable vectors cannot be scalarized, so handle the legalisation of the
1741 // types like done elsewhere in SelectionDAG.
1742 if (EltCnt.isScalable()) {
1743 if (std::optional<unsigned> NumRegs = GetLegalVectorBreakdown())
1744 return *NumRegs;
1745 report_fatal_error(reason: "Don't know how to legalize this scalable vector type");
1746 }
1747
1748 // FIXME: We don't generically support non-power-of-2-sized vectors for now.
1749 // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1750 if (!isPowerOf2_32(Value: EltCnt.getKnownMinValue())) {
1751 assert(VT.isFixedLengthVector() && "Expected a fixed-length vector VT");
1752 unsigned NumElts = EltCnt.getKnownMinValue();
1753
1754 if (!ForCallingConv && preferVectorizedNonPowerOfTwoTypeBreakdown())
1755 if (std::optional<unsigned> NumRegs = GetLegalVectorBreakdown())
1756 return *NumRegs;
1757
1758 // Fall back to scalars if there is no legal vector decomposition.
1759 NumVectorRegs = NumElts;
1760 EltCnt = ElementCount::getFixed(MinVal: 1);
1761 }
1762
1763 // Divide the input until we get to a supported size. This will always
1764 // end with a scalar if the target doesn't support vectors.
1765 while (EltCnt.getKnownMinValue() > 1 &&
1766 !isTypeLegal(VT: EVT::getVectorVT(Context, VT: EltTy, EC: EltCnt))) {
1767 EltCnt = EltCnt.divideCoefficientBy(RHS: 2);
1768 NumVectorRegs <<= 1;
1769 }
1770
1771 NumIntermediates = NumVectorRegs;
1772
1773 EVT NewVT = EVT::getVectorVT(Context, VT: EltTy, EC: EltCnt);
1774 if (!isTypeLegal(VT: NewVT))
1775 NewVT = EltTy;
1776 IntermediateVT = NewVT;
1777
1778 MVT DestVT = getRegisterType(Context, VT: NewVT);
1779 RegisterVT = DestVT;
1780
1781 if (EVT(DestVT).bitsLT(VT: NewVT)) { // Value is expanded, e.g. i64 -> i16.
1782 TypeSize NewVTSize = NewVT.getSizeInBits();
1783 // Convert sizes such as i33 to i64.
1784 if (!llvm::has_single_bit<uint32_t>(Value: NewVTSize.getKnownMinValue()))
1785 NewVTSize = NewVTSize.coefficientNextPowerOf2();
1786 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1787 }
1788
1789 // Otherwise, promotion or legal types use the same number of registers as
1790 // the vector decimated to the appropriate level.
1791 return NumVectorRegs;
1792}
1793
1794bool TargetLoweringBase::isSuitableForJumpTable(const SwitchInst *SI,
1795 uint64_t NumCases,
1796 uint64_t Range,
1797 ProfileSummaryInfo *PSI,
1798 BlockFrequencyInfo *BFI) const {
1799 // FIXME: This function check the maximum table size and density, but the
1800 // minimum size is not checked. It would be nice if the minimum size is
1801 // also combined within this function. Currently, the minimum size check is
1802 // performed in findJumpTable() in SelectionDAGBuiler and
1803 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1804 const bool OptForSize =
1805 llvm::shouldOptimizeForSize(BB: SI->getParent(), PSI, BFI);
1806 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1807 const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1808
1809 // Check whether the number of cases is small enough and
1810 // the range is dense enough for a jump table.
1811 return (OptForSize || Range <= MaxJumpTableSize) &&
1812 (NumCases * 100 >= Range * MinDensity);
1813}
1814
1815MVT TargetLoweringBase::getPreferredSwitchConditionType(LLVMContext &Context,
1816 EVT ConditionVT) const {
1817 return getRegisterType(Context, VT: ConditionVT);
1818}
1819
1820/// Get the EVTs and ArgFlags collections that represent the legalized return
1821/// type of the given function. This does not require a DAG or a return value,
1822/// and is suitable for use before any DAGs for the function are constructed.
1823/// TODO: Move this out of TargetLowering.cpp.
1824void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType,
1825 AttributeList attr,
1826 SmallVectorImpl<ISD::OutputArg> &Outs,
1827 const TargetLowering &TLI, const DataLayout &DL) {
1828 SmallVector<Type *, 4> Types;
1829 ComputeValueTypes(DL, Ty: ReturnType, Types);
1830 unsigned NumValues = Types.size();
1831 if (NumValues == 0) return;
1832
1833 for (Type *Ty : Types) {
1834 EVT VT = TLI.getValueType(DL, Ty);
1835 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1836
1837 if (attr.hasRetAttr(Kind: Attribute::SExt))
1838 ExtendKind = ISD::SIGN_EXTEND;
1839 else if (attr.hasRetAttr(Kind: Attribute::ZExt))
1840 ExtendKind = ISD::ZERO_EXTEND;
1841
1842 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1843 VT = TLI.getTypeForExtReturn(Context&: ReturnType->getContext(), VT, ExtendKind);
1844
1845 unsigned NumParts =
1846 TLI.getNumRegistersForCallingConv(Context&: ReturnType->getContext(), CC, VT);
1847 MVT PartVT =
1848 TLI.getRegisterTypeForCallingConv(Context&: ReturnType->getContext(), CC, VT);
1849
1850 // 'inreg' on function refers to return value
1851 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1852 if (attr.hasRetAttr(Kind: Attribute::InReg))
1853 Flags.setInReg();
1854
1855 // Propagate extension type if any
1856 if (attr.hasRetAttr(Kind: Attribute::SExt))
1857 Flags.setSExt();
1858 else if (attr.hasRetAttr(Kind: Attribute::ZExt))
1859 Flags.setZExt();
1860
1861 for (unsigned i = 0; i < NumParts; ++i)
1862 Outs.push_back(Elt: ISD::OutputArg(Flags, PartVT, VT, Ty, 0, 0));
1863 }
1864}
1865
1866Align TargetLoweringBase::getByValTypeAlignment(Type *Ty,
1867 const DataLayout &DL) const {
1868 return DL.getABITypeAlign(Ty);
1869}
1870
1871bool TargetLoweringBase::allowsMemoryAccessForAlignment(
1872 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1873 Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const {
1874 // Check if the specified alignment is sufficient based on the data layout.
1875 // TODO: While using the data layout works in practice, a better solution
1876 // would be to implement this check directly (make this a virtual function).
1877 // For example, the ABI alignment may change based on software platform while
1878 // this function should only be affected by hardware implementation.
1879 Type *Ty = VT.getTypeForEVT(Context);
1880 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {
1881 // Assume that an access that meets the ABI-specified alignment is fast.
1882 if (Fast != nullptr)
1883 *Fast = 1;
1884 return true;
1885 }
1886
1887 // This is a misaligned access.
1888 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1889}
1890
1891bool TargetLoweringBase::allowsMemoryAccessForAlignment(
1892 LLVMContext &Context, const DataLayout &DL, EVT VT,
1893 const MachineMemOperand &MMO, unsigned *Fast) const {
1894 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace: MMO.getAddrSpace(),
1895 Alignment: MMO.getAlign(), Flags: MMO.getFlags(), Fast);
1896}
1897
1898bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1899 const DataLayout &DL, EVT VT,
1900 unsigned AddrSpace, Align Alignment,
1901 MachineMemOperand::Flags Flags,
1902 unsigned *Fast) const {
1903 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1904 Flags, Fast);
1905}
1906
1907bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1908 const DataLayout &DL, EVT VT,
1909 const MachineMemOperand &MMO,
1910 unsigned *Fast) const {
1911 return allowsMemoryAccess(Context, DL, VT, AddrSpace: MMO.getAddrSpace(), Alignment: MMO.getAlign(),
1912 Flags: MMO.getFlags(), Fast);
1913}
1914
1915bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1916 const DataLayout &DL, LLT Ty,
1917 const MachineMemOperand &MMO,
1918 unsigned *Fast) const {
1919 EVT VT = getApproximateEVTForLLT(Ty, Ctx&: Context);
1920 return allowsMemoryAccess(Context, DL, VT, AddrSpace: MMO.getAddrSpace(), Alignment: MMO.getAlign(),
1921 Flags: MMO.getFlags(), Fast);
1922}
1923
1924unsigned TargetLoweringBase::getMaxStoresPerMemset(bool OptSize) const {
1925 if (MaxStoresPerMemsetOverride > 0)
1926 return MaxStoresPerMemsetOverride;
1927
1928 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1929}
1930
1931unsigned TargetLoweringBase::getMaxStoresPerMemcpy(bool OptSize) const {
1932 if (MaxStoresPerMemcpyOverride > 0)
1933 return MaxStoresPerMemcpyOverride;
1934
1935 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1936}
1937
1938unsigned TargetLoweringBase::getMaxStoresPerMemmove(bool OptSize) const {
1939 if (MaxStoresPerMemmoveOverride > 0)
1940 return MaxStoresPerMemmoveOverride;
1941
1942 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1943}
1944
1945//===----------------------------------------------------------------------===//
1946// TargetTransformInfo Helpers
1947//===----------------------------------------------------------------------===//
1948
1949int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1950 enum InstructionOpcodes {
1951#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1952#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1953#include "llvm/IR/Instruction.def"
1954 };
1955 switch (static_cast<InstructionOpcodes>(Opcode)) {
1956 case Ret: return 0;
1957 case UncondBr: return 0;
1958 case CondBr: return 0;
1959 case Switch: return 0;
1960 case IndirectBr: return 0;
1961 case Invoke: return 0;
1962 case CallBr: return 0;
1963 case Resume: return 0;
1964 case Unreachable: return 0;
1965 case CleanupRet: return 0;
1966 case CatchRet: return 0;
1967 case CatchPad: return 0;
1968 case CatchSwitch: return 0;
1969 case CleanupPad: return 0;
1970 case FNeg: return ISD::FNEG;
1971 case Add: return ISD::ADD;
1972 case FAdd: return ISD::FADD;
1973 case Sub: return ISD::SUB;
1974 case FSub: return ISD::FSUB;
1975 case Mul: return ISD::MUL;
1976 case FMul: return ISD::FMUL;
1977 case UDiv: return ISD::UDIV;
1978 case SDiv: return ISD::SDIV;
1979 case FDiv: return ISD::FDIV;
1980 case URem: return ISD::UREM;
1981 case SRem: return ISD::SREM;
1982 case FRem: return ISD::FREM;
1983 case Shl: return ISD::SHL;
1984 case LShr: return ISD::SRL;
1985 case AShr: return ISD::SRA;
1986 case And: return ISD::AND;
1987 case Or: return ISD::OR;
1988 case Xor: return ISD::XOR;
1989 case Alloca: return 0;
1990 case Load: return ISD::LOAD;
1991 case Store: return ISD::STORE;
1992 case GetElementPtr: return 0;
1993 case Fence: return 0;
1994 case AtomicCmpXchg: return 0;
1995 case AtomicRMW: return 0;
1996 case Trunc: return ISD::TRUNCATE;
1997 case ZExt: return ISD::ZERO_EXTEND;
1998 case SExt: return ISD::SIGN_EXTEND;
1999 case FPToUI: return ISD::FP_TO_UINT;
2000 case FPToSI: return ISD::FP_TO_SINT;
2001 case UIToFP: return ISD::UINT_TO_FP;
2002 case SIToFP: return ISD::SINT_TO_FP;
2003 case FPTrunc: return ISD::FP_ROUND;
2004 case FPExt: return ISD::FP_EXTEND;
2005 case PtrToAddr: return ISD::BITCAST;
2006 case PtrToInt: return ISD::BITCAST;
2007 case IntToPtr: return ISD::BITCAST;
2008 case BitCast: return ISD::BITCAST;
2009 case AddrSpaceCast: return ISD::ADDRSPACECAST;
2010 case ICmp: return ISD::SETCC;
2011 case FCmp: return ISD::SETCC;
2012 case PHI: return 0;
2013 case Call: return 0;
2014 case Select: return ISD::SELECT;
2015 case UserOp1: return 0;
2016 case UserOp2: return 0;
2017 case VAArg: return 0;
2018 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
2019 case InsertElement: return ISD::INSERT_VECTOR_ELT;
2020 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
2021 case ExtractValue: return ISD::MERGE_VALUES;
2022 case InsertValue: return ISD::MERGE_VALUES;
2023 case LandingPad: return 0;
2024 case Freeze: return ISD::FREEZE;
2025 }
2026
2027 llvm_unreachable("Unknown instruction type encountered!");
2028}
2029
2030int TargetLoweringBase::IntrinsicIDToISD(Intrinsic::ID ID) const {
2031 switch (ID) {
2032 case Intrinsic::acos:
2033 return ISD::FACOS;
2034 case Intrinsic::asin:
2035 return ISD::FASIN;
2036 case Intrinsic::atan:
2037 return ISD::FATAN;
2038 case Intrinsic::cos:
2039 return ISD::FCOS;
2040 case Intrinsic::cosh:
2041 return ISD::FCOSH;
2042 case Intrinsic::exp:
2043 return ISD::FEXP;
2044 case Intrinsic::exp2:
2045 return ISD::FEXP2;
2046 case Intrinsic::exp10:
2047 return ISD::FEXP10;
2048 case Intrinsic::log:
2049 return ISD::FLOG;
2050 case Intrinsic::log2:
2051 return ISD::FLOG2;
2052 case Intrinsic::log10:
2053 return ISD::FLOG10;
2054 case Intrinsic::sin:
2055 return ISD::FSIN;
2056 case Intrinsic::sinh:
2057 return ISD::FSINH;
2058 case Intrinsic::tan:
2059 return ISD::FTAN;
2060 case Intrinsic::tanh:
2061 return ISD::FTANH;
2062 default:
2063 return ISD::DELETED_NODE;
2064 }
2065}
2066
2067Value *
2068TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilderBase &IRB,
2069 bool UseTLS) const {
2070 // compiler-rt provides a variable with a magic name. Targets that do not
2071 // link with compiler-rt may also provide such a variable.
2072 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2073
2074 RTLIB::LibcallImpl UnsafeStackPtrImpl =
2075 Libcalls.getLibcallImpl(Call: RTLIB::SAFESTACK_UNSAFE_STACK_PTR);
2076 if (UnsafeStackPtrImpl == RTLIB::Unsupported)
2077 return nullptr;
2078
2079 StringRef UnsafeStackPtrVar =
2080 RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: UnsafeStackPtrImpl);
2081 auto UnsafeStackPtr =
2082 dyn_cast_or_null<GlobalVariable>(Val: M->getNamedValue(Name: UnsafeStackPtrVar));
2083
2084 const DataLayout &DL = M->getDataLayout();
2085 PointerType *StackPtrTy = DL.getAllocaPtrType(Ctx&: M->getContext());
2086
2087 if (!UnsafeStackPtr) {
2088 auto TLSModel = UseTLS ?
2089 GlobalValue::InitialExecTLSModel :
2090 GlobalValue::NotThreadLocal;
2091 // The global variable is not defined yet, define it ourselves.
2092 // We use the initial-exec TLS model because we do not support the
2093 // variable living anywhere other than in the main executable.
2094 UnsafeStackPtr = new GlobalVariable(
2095 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
2096 UnsafeStackPtrVar, nullptr, TLSModel);
2097 } else {
2098 // The variable exists, check its type and attributes.
2099 //
2100 // FIXME: Move to IR verifier.
2101 if (UnsafeStackPtr->getValueType() != StackPtrTy)
2102 report_fatal_error(reason: Twine(UnsafeStackPtrVar) + " must have void* type");
2103 if (UseTLS != UnsafeStackPtr->isThreadLocal())
2104 report_fatal_error(reason: Twine(UnsafeStackPtrVar) + " must " +
2105 (UseTLS ? "" : "not ") + "be thread-local");
2106 }
2107 return UnsafeStackPtr;
2108}
2109
2110Value *TargetLoweringBase::getSafeStackPointerLocation(
2111 IRBuilderBase &IRB, const LibcallLoweringInfo &Libcalls) const {
2112 RTLIB::LibcallImpl SafestackPointerAddressImpl =
2113 Libcalls.getLibcallImpl(Call: RTLIB::SAFESTACK_POINTER_ADDRESS);
2114 if (SafestackPointerAddressImpl == RTLIB::Unsupported)
2115 return getDefaultSafeStackPointerLocation(IRB, UseTLS: true);
2116
2117 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2118 auto *PtrTy = PointerType::getUnqual(C&: M->getContext());
2119
2120 // Android provides a libc function to retrieve the address of the current
2121 // thread's unsafe stack pointer.
2122 FunctionCallee Fn =
2123 M->getOrInsertFunction(Name: RTLIB::RuntimeLibcallsInfo::getLibcallImplName(
2124 CallImpl: SafestackPointerAddressImpl),
2125 RetTy: PtrTy);
2126 return IRB.CreateCall(Callee: Fn);
2127}
2128
2129//===----------------------------------------------------------------------===//
2130// Loop Strength Reduction hooks
2131//===----------------------------------------------------------------------===//
2132
2133/// isLegalAddressingMode - Return true if the addressing mode represented
2134/// by AM is legal for this target, for a load/store of the specified type.
2135bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
2136 const AddrMode &AM, Type *Ty,
2137 unsigned AS, Instruction *I) const {
2138 // The default implementation of this implements a conservative RISCy, r+r and
2139 // r+i addr mode.
2140
2141 // Scalable offsets not supported
2142 if (AM.ScalableOffset)
2143 return false;
2144
2145 // Allows a sign-extended 16-bit immediate field.
2146 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2147 return false;
2148
2149 // No global is ever allowed as a base.
2150 if (AM.BaseGV)
2151 return false;
2152
2153 // Only support r+r,
2154 switch (AM.Scale) {
2155 case 0: // "r+i" or just "i", depending on HasBaseReg.
2156 break;
2157 case 1:
2158 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2159 return false;
2160 // Otherwise we have r+r or r+i.
2161 break;
2162 case 2:
2163 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2164 return false;
2165 // Allow 2*r as r+r.
2166 break;
2167 default: // Don't allow n * r
2168 return false;
2169 }
2170
2171 return true;
2172}
2173
2174//===----------------------------------------------------------------------===//
2175// Stack Protector
2176//===----------------------------------------------------------------------===//
2177
2178// For OpenBSD return its special guard variable. Otherwise return nullptr,
2179// so that SelectionDAG handle SSP.
2180Value *
2181TargetLoweringBase::getIRStackGuard(IRBuilderBase &IRB,
2182 const LibcallLoweringInfo &Libcalls) const {
2183 RTLIB::LibcallImpl GuardLocalImpl =
2184 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2185 if (GuardLocalImpl != RTLIB::impl___guard_local)
2186 return nullptr;
2187
2188 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
2189 const DataLayout &DL = M.getDataLayout();
2190 PointerType *PtrTy =
2191 PointerType::get(C&: M.getContext(), AddressSpace: DL.getDefaultGlobalsAddressSpace());
2192 GlobalVariable *G =
2193 M.getOrInsertGlobal(Name: getLibcallImplName(Call: GuardLocalImpl), Ty: PtrTy);
2194 G->setVisibility(GlobalValue::HiddenVisibility);
2195 return G;
2196}
2197
2198// Currently only support "standard" __stack_chk_guard.
2199// TODO: add LOAD_STACK_GUARD support.
2200void TargetLoweringBase::insertSSPDeclarations(
2201 Module &M, const LibcallLoweringInfo &Libcalls) const {
2202 RTLIB::LibcallImpl StackGuardImpl =
2203 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2204 if (StackGuardImpl == RTLIB::Unsupported)
2205 return;
2206
2207 StringRef StackGuardVarName = getLibcallImplName(Call: StackGuardImpl);
2208 M.getOrInsertGlobal(
2209 Name: StackGuardVarName, Ty: PointerType::getUnqual(C&: M.getContext()), CreateGlobalCallback: [=, &M]() {
2210 auto *GV = new GlobalVariable(M, PointerType::getUnqual(C&: M.getContext()),
2211 false, GlobalVariable::ExternalLinkage,
2212 nullptr, StackGuardVarName);
2213
2214 // FreeBSD has "__stack_chk_guard" defined externally on libc.so
2215 if (M.getDirectAccessExternalData() &&
2216 !TM.getTargetTriple().isOSCygMing() &&
2217 !(TM.getTargetTriple().isPPC64() &&
2218 TM.getTargetTriple().isOSFreeBSD()) &&
2219 (!TM.getTargetTriple().isOSDarwin() ||
2220 TM.getRelocationModel() == Reloc::Static))
2221 GV->setDSOLocal(true);
2222
2223 return GV;
2224 });
2225}
2226
2227// Currently only support "standard" __stack_chk_guard.
2228// TODO: add LOAD_STACK_GUARD support.
2229Value *TargetLoweringBase::getSDagStackGuard(
2230 const Module &M, const LibcallLoweringInfo &Libcalls) const {
2231 RTLIB::LibcallImpl GuardVarImpl =
2232 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2233 if (GuardVarImpl == RTLIB::Unsupported)
2234 return nullptr;
2235 return M.getNamedValue(Name: getLibcallImplName(Call: GuardVarImpl));
2236}
2237
2238Function *TargetLoweringBase::getSSPStackGuardCheck(
2239 const Module &M, const LibcallLoweringInfo &Libcalls) const {
2240 // MSVC CRT has a function to validate security cookie.
2241 RTLIB::LibcallImpl SecurityCheckCookieLibcall =
2242 Libcalls.getLibcallImpl(Call: RTLIB::SECURITY_CHECK_COOKIE);
2243 if (SecurityCheckCookieLibcall != RTLIB::Unsupported)
2244 return M.getFunction(Name: getLibcallImplName(Call: SecurityCheckCookieLibcall));
2245 return nullptr;
2246}
2247
2248unsigned TargetLoweringBase::getMinimumJumpTableEntries() const {
2249 return MinimumJumpTableEntries;
2250}
2251
2252void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) {
2253 MinimumJumpTableEntries = Val;
2254}
2255
2256unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
2257 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
2258}
2259
2260unsigned TargetLoweringBase::getMaximumJumpTableSize() const {
2261 return MaximumJumpTableSize;
2262}
2263
2264void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {
2265 MaximumJumpTableSize = Val;
2266}
2267
2268bool TargetLoweringBase::isJumpTableRelative() const {
2269 return getTargetMachine().isPositionIndependent();
2270}
2271
2272unsigned TargetLoweringBase::getMinimumBitTestCmps() const {
2273 return MinimumBitTestCmps;
2274}
2275
2276void TargetLoweringBase::setMinimumBitTestCmps(unsigned Val) {
2277 MinimumBitTestCmps = Val;
2278}
2279
2280Align TargetLoweringBase::getPrefLoopAlignment(MachineLoop *ML) const {
2281 if (TM.Options.LoopAlignment)
2282 return Align(TM.Options.LoopAlignment);
2283 return PrefLoopAlignment;
2284}
2285
2286unsigned TargetLoweringBase::getMaxPermittedBytesForAlignment(
2287 MachineBasicBlock *MBB) const {
2288 return MaxBytesForAlignment;
2289}
2290
2291//===----------------------------------------------------------------------===//
2292// Reciprocal Estimates
2293//===----------------------------------------------------------------------===//
2294
2295/// Get the reciprocal estimate attribute string for a function that will
2296/// override the target defaults.
2297static StringRef getRecipEstimateForFunc(MachineFunction &MF) {
2298 const Function &F = MF.getFunction();
2299 return F.getFnAttribute(Kind: "reciprocal-estimates").getValueAsString();
2300}
2301
2302/// Construct a string for the given reciprocal operation of the given type.
2303/// This string should match the corresponding option to the front-end's
2304/// "-mrecip" flag assuming those strings have been passed through in an
2305/// attribute string. For example, "vec-divf" for a division of a vXf32.
2306static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2307 std::string Name = VT.isVector() ? "vec-" : "";
2308
2309 Name += IsSqrt ? "sqrt" : "div";
2310
2311 // TODO: Handle other float types?
2312 if (VT.getScalarType() == MVT::f64) {
2313 Name += "d";
2314 } else if (VT.getScalarType() == MVT::f16) {
2315 Name += "h";
2316 } else {
2317 assert(VT.getScalarType() == MVT::f32 &&
2318 "Unexpected FP type for reciprocal estimate");
2319 Name += "f";
2320 }
2321
2322 return Name;
2323}
2324
2325/// Return the character position and value (a single numeric character) of a
2326/// customized refinement operation in the input string if it exists. Return
2327/// false if there is no customized refinement step count.
2328static bool parseRefinementStep(StringRef In, size_t &Position,
2329 uint8_t &Value) {
2330 const char RefStepToken = ':';
2331 Position = In.find(C: RefStepToken);
2332 if (Position == StringRef::npos)
2333 return false;
2334
2335 StringRef RefStepString = In.substr(Start: Position + 1);
2336 // Allow exactly one numeric character for the additional refinement
2337 // step parameter.
2338 if (RefStepString.size() == 1) {
2339 char RefStepChar = RefStepString[0];
2340 if (isDigit(C: RefStepChar)) {
2341 Value = RefStepChar - '0';
2342 return true;
2343 }
2344 }
2345 report_fatal_error(reason: "Invalid refinement step for -recip.");
2346}
2347
2348/// For the input attribute string, return one of the ReciprocalEstimate enum
2349/// status values (enabled, disabled, or not specified) for this operation on
2350/// the specified data type.
2351static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2352 if (Override.empty())
2353 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2354
2355 SmallVector<StringRef, 4> OverrideVector;
2356 Override.split(A&: OverrideVector, Separator: ',');
2357 unsigned NumArgs = OverrideVector.size();
2358
2359 // Check if "all", "none", or "default" was specified.
2360 if (NumArgs == 1) {
2361 // Look for an optional setting of the number of refinement steps needed
2362 // for this type of reciprocal operation.
2363 size_t RefPos;
2364 uint8_t RefSteps;
2365 if (parseRefinementStep(In: Override, Position&: RefPos, Value&: RefSteps)) {
2366 // Split the string for further processing.
2367 Override = Override.substr(Start: 0, N: RefPos);
2368 }
2369
2370 // All reciprocal types are enabled.
2371 if (Override == "all")
2372 return TargetLoweringBase::ReciprocalEstimate::Enabled;
2373
2374 // All reciprocal types are disabled.
2375 if (Override == "none")
2376 return TargetLoweringBase::ReciprocalEstimate::Disabled;
2377
2378 // Target defaults for enablement are used.
2379 if (Override == "default")
2380 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2381 }
2382
2383 // The attribute string may omit the size suffix ('f'/'d').
2384 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2385 std::string VTNameNoSize = VTName;
2386 VTNameNoSize.pop_back();
2387 static const char DisabledPrefix = '!';
2388
2389 for (StringRef RecipType : OverrideVector) {
2390 size_t RefPos;
2391 uint8_t RefSteps;
2392 if (parseRefinementStep(In: RecipType, Position&: RefPos, Value&: RefSteps))
2393 RecipType = RecipType.substr(Start: 0, N: RefPos);
2394
2395 // Ignore the disablement token for string matching.
2396 bool IsDisabled = RecipType[0] == DisabledPrefix;
2397 if (IsDisabled)
2398 RecipType = RecipType.substr(Start: 1);
2399
2400 if (RecipType == VTName || RecipType == VTNameNoSize)
2401 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
2402 : TargetLoweringBase::ReciprocalEstimate::Enabled;
2403 }
2404
2405 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2406}
2407
2408/// For the input attribute string, return the customized refinement step count
2409/// for this operation on the specified data type. If the step count does not
2410/// exist, return the ReciprocalEstimate enum value for unspecified.
2411static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2412 if (Override.empty())
2413 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2414
2415 SmallVector<StringRef, 4> OverrideVector;
2416 Override.split(A&: OverrideVector, Separator: ',');
2417 unsigned NumArgs = OverrideVector.size();
2418
2419 // Check if "all", "default", or "none" was specified.
2420 if (NumArgs == 1) {
2421 // Look for an optional setting of the number of refinement steps needed
2422 // for this type of reciprocal operation.
2423 size_t RefPos;
2424 uint8_t RefSteps;
2425 if (!parseRefinementStep(In: Override, Position&: RefPos, Value&: RefSteps))
2426 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2427
2428 // Split the string for further processing.
2429 Override = Override.substr(Start: 0, N: RefPos);
2430 assert(Override != "none" &&
2431 "Disabled reciprocals, but specifed refinement steps?");
2432
2433 // If this is a general override, return the specified number of steps.
2434 if (Override == "all" || Override == "default")
2435 return RefSteps;
2436 }
2437
2438 // The attribute string may omit the size suffix ('f'/'d').
2439 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2440 std::string VTNameNoSize = VTName;
2441 VTNameNoSize.pop_back();
2442
2443 for (StringRef RecipType : OverrideVector) {
2444 size_t RefPos;
2445 uint8_t RefSteps;
2446 if (!parseRefinementStep(In: RecipType, Position&: RefPos, Value&: RefSteps))
2447 continue;
2448
2449 RecipType = RecipType.substr(Start: 0, N: RefPos);
2450 if (RecipType == VTName || RecipType == VTNameNoSize)
2451 return RefSteps;
2452 }
2453
2454 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2455}
2456
2457int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,
2458 MachineFunction &MF) const {
2459 return getOpEnabled(IsSqrt: true, VT, Override: getRecipEstimateForFunc(MF));
2460}
2461
2462int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,
2463 MachineFunction &MF) const {
2464 return getOpEnabled(IsSqrt: false, VT, Override: getRecipEstimateForFunc(MF));
2465}
2466
2467int TargetLoweringBase::getSqrtRefinementSteps(EVT VT,
2468 MachineFunction &MF) const {
2469 return getOpRefinementSteps(IsSqrt: true, VT, Override: getRecipEstimateForFunc(MF));
2470}
2471
2472int TargetLoweringBase::getDivRefinementSteps(EVT VT,
2473 MachineFunction &MF) const {
2474 return getOpRefinementSteps(IsSqrt: false, VT, Override: getRecipEstimateForFunc(MF));
2475}
2476
2477bool TargetLoweringBase::isLoadBitCastBeneficial(
2478 EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG,
2479 const MachineMemOperand &MMO) const {
2480 // Single-element vectors are scalarized, so we should generally avoid having
2481 // any memory operations on such types, as they would get scalarized too.
2482 if (LoadVT.isFixedLengthVector() && BitcastVT.isFixedLengthVector() &&
2483 BitcastVT.getVectorNumElements() == 1)
2484 return false;
2485
2486 // Don't do if we could do an indexed load on the original type, but not on
2487 // the new one.
2488 if (!LoadVT.isSimple() || !BitcastVT.isSimple())
2489 return true;
2490
2491 MVT LoadMVT = LoadVT.getSimpleVT();
2492
2493 // Don't bother doing this if it's just going to be promoted again later, as
2494 // doing so might interfere with other combines.
2495 if (getOperationAction(Op: ISD::LOAD, VT: LoadMVT) == Promote &&
2496 getTypeToPromoteTo(Op: ISD::LOAD, VT: LoadMVT) == BitcastVT.getSimpleVT())
2497 return false;
2498
2499 unsigned Fast = 0;
2500 return allowsMemoryAccess(Context&: *DAG.getContext(), DL: DAG.getDataLayout(), VT: BitcastVT,
2501 MMO, Fast: &Fast) &&
2502 Fast;
2503}
2504
2505void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
2506 MF.getRegInfo().freezeReservedRegs();
2507}
2508
2509MachineMemOperand::Flags TargetLoweringBase::getLoadMemOperandFlags(
2510 const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC,
2511 const TargetLibraryInfo *LibInfo, CodeGenOptLevel OptLevel) const {
2512 MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad;
2513 if (LI.isVolatile())
2514 Flags |= MachineMemOperand::MOVolatile;
2515
2516 if (LI.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2517 Flags |= MachineMemOperand::MONonTemporal;
2518
2519 if (LI.hasMetadata(KindID: LLVMContext::MD_invariant_load))
2520 Flags |= MachineMemOperand::MOInvariant;
2521
2522 // Dereferenceability analysis is expensive, skip at O0.
2523 if (OptLevel != CodeGenOptLevel::None &&
2524 isDereferenceableAndAlignedPointer(
2525 V: LI.getPointerOperand(), Ty: LI.getType(), Alignment: LI.getAlign(),
2526 Q: SimplifyQuery(DL, LibInfo, /*DT=*/nullptr, AC, &LI))) {
2527 Flags |= MachineMemOperand::MODereferenceable;
2528 } else if (LI.hasMetadata(KindID: LLVMContext::MD_dereferenceable)) {
2529 Flags |= MachineMemOperand::MODereferenceable;
2530 }
2531
2532 Flags |= getTargetMMOFlags(I: LI);
2533 return Flags;
2534}
2535
2536MachineMemOperand::Flags
2537TargetLoweringBase::getStoreMemOperandFlags(const StoreInst &SI,
2538 const DataLayout &DL) const {
2539 MachineMemOperand::Flags Flags = MachineMemOperand::MOStore;
2540
2541 if (SI.isVolatile())
2542 Flags |= MachineMemOperand::MOVolatile;
2543
2544 if (SI.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2545 Flags |= MachineMemOperand::MONonTemporal;
2546
2547 // FIXME: Not preserving dereferenceable
2548 Flags |= getTargetMMOFlags(I: SI);
2549 return Flags;
2550}
2551
2552MachineMemOperand::Flags
2553TargetLoweringBase::getAtomicMemOperandFlags(const Instruction &AI,
2554 const DataLayout &DL) const {
2555 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
2556
2557 if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(Val: &AI)) {
2558 if (RMW->isVolatile())
2559 Flags |= MachineMemOperand::MOVolatile;
2560 } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(Val: &AI)) {
2561 if (CmpX->isVolatile())
2562 Flags |= MachineMemOperand::MOVolatile;
2563 } else
2564 llvm_unreachable("not an atomic instruction");
2565
2566 // FIXME: Not preserving dereferenceable
2567 Flags |= getTargetMMOFlags(I: AI);
2568 return Flags;
2569}
2570
2571MachineMemOperand::Flags TargetLoweringBase::getVPIntrinsicMemOperandFlags(
2572 const VPIntrinsic &VPIntrin) const {
2573 MachineMemOperand::Flags Flags = MachineMemOperand::MONone;
2574 Intrinsic::ID IntrinID = VPIntrin.getIntrinsicID();
2575
2576 switch (IntrinID) {
2577 default:
2578 llvm_unreachable("unexpected intrinsic. Existing code may be appropriate "
2579 "for it, but support must be explicitly enabled");
2580 case Intrinsic::vp_load:
2581 case Intrinsic::vp_gather:
2582 case Intrinsic::experimental_vp_strided_load:
2583 Flags = MachineMemOperand::MOLoad;
2584 break;
2585 case Intrinsic::vp_store:
2586 case Intrinsic::vp_scatter:
2587 case Intrinsic::experimental_vp_strided_store:
2588 Flags = MachineMemOperand::MOStore;
2589 break;
2590 }
2591
2592 if (VPIntrin.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2593 Flags |= MachineMemOperand::MONonTemporal;
2594
2595 Flags |= getTargetMMOFlags(I: VPIntrin);
2596 return Flags;
2597}
2598
2599Instruction *TargetLoweringBase::emitLeadingFence(IRBuilderBase &Builder,
2600 Instruction *Inst,
2601 AtomicOrdering Ord) const {
2602 if (isReleaseOrStronger(AO: Ord) && Inst->hasAtomicStore())
2603 return Builder.CreateFence(Ordering: Ord);
2604 else
2605 return nullptr;
2606}
2607
2608Instruction *TargetLoweringBase::emitTrailingFence(IRBuilderBase &Builder,
2609 Instruction *Inst,
2610 AtomicOrdering Ord) const {
2611 if (isAcquireOrStronger(AO: Ord))
2612 return Builder.CreateFence(Ordering: Ord);
2613 else
2614 return nullptr;
2615}
2616
2617//===----------------------------------------------------------------------===//
2618// GlobalISel Hooks
2619//===----------------------------------------------------------------------===//
2620
2621bool TargetLoweringBase::shouldLocalize(const MachineInstr &MI,
2622 const TargetTransformInfo *TTI) const {
2623 auto &MF = *MI.getMF();
2624 auto &MRI = MF.getRegInfo();
2625 // Assuming a spill and reload of a value has a cost of 1 instruction each,
2626 // this helper function computes the maximum number of uses we should consider
2627 // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2628 // break even in terms of code size when the original MI has 2 users vs
2629 // choosing to potentially spill. Any more than 2 users we we have a net code
2630 // size increase. This doesn't take into account register pressure though.
2631 auto maxUses = [](unsigned RematCost) {
2632 // A cost of 1 means remats are basically free.
2633 if (RematCost == 1)
2634 return std::numeric_limits<unsigned>::max();
2635 if (RematCost == 2)
2636 return 2U;
2637
2638 // Remat is too expensive, only sink if there's one user.
2639 if (RematCost > 2)
2640 return 1U;
2641 llvm_unreachable("Unexpected remat cost");
2642 };
2643
2644 switch (MI.getOpcode()) {
2645 default:
2646 return false;
2647 // Constants-like instructions should be close to their users.
2648 // We don't want long live-ranges for them.
2649 case TargetOpcode::G_CONSTANT:
2650 case TargetOpcode::G_FCONSTANT:
2651 case TargetOpcode::G_FRAME_INDEX:
2652 case TargetOpcode::G_INTTOPTR:
2653 return true;
2654 case TargetOpcode::G_GLOBAL_VALUE: {
2655 unsigned RematCost = TTI->getGISelRematGlobalCost();
2656 Register Reg = MI.getOperand(i: 0).getReg();
2657 unsigned MaxUses = maxUses(RematCost);
2658 if (MaxUses == UINT_MAX)
2659 return true; // Remats are "free" so always localize.
2660 return MRI.hasAtMostUserInstrs(Reg, MaxUsers: MaxUses);
2661 }
2662 }
2663}
2664