1//===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the TargetLoweringBase class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/ADT/BitVector.h"
14#include "llvm/ADT/STLExtras.h"
15#include "llvm/ADT/SmallVector.h"
16#include "llvm/ADT/StringExtras.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/Twine.h"
19#include "llvm/Analysis/Loads.h"
20#include "llvm/Analysis/TargetTransformInfo.h"
21#include "llvm/CodeGen/Analysis.h"
22#include "llvm/CodeGen/ISDOpcodes.h"
23#include "llvm/CodeGen/MachineBasicBlock.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineMemOperand.h"
29#include "llvm/CodeGen/MachineOperand.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RuntimeLibcallUtil.h"
32#include "llvm/CodeGen/StackMaps.h"
33#include "llvm/CodeGen/TargetLowering.h"
34#include "llvm/CodeGen/TargetOpcodes.h"
35#include "llvm/CodeGen/TargetRegisterInfo.h"
36#include "llvm/CodeGen/ValueTypes.h"
37#include "llvm/CodeGenTypes/MachineValueType.h"
38#include "llvm/IR/Attributes.h"
39#include "llvm/IR/CallingConv.h"
40#include "llvm/IR/DataLayout.h"
41#include "llvm/IR/DerivedTypes.h"
42#include "llvm/IR/Function.h"
43#include "llvm/IR/GlobalValue.h"
44#include "llvm/IR/GlobalVariable.h"
45#include "llvm/IR/IRBuilder.h"
46#include "llvm/IR/Module.h"
47#include "llvm/IR/Type.h"
48#include "llvm/Support/Casting.h"
49#include "llvm/Support/CommandLine.h"
50#include "llvm/Support/Compiler.h"
51#include "llvm/Support/ErrorHandling.h"
52#include "llvm/Support/MathExtras.h"
53#include "llvm/Target/TargetMachine.h"
54#include "llvm/Target/TargetOptions.h"
55#include "llvm/TargetParser/Triple.h"
56#include "llvm/Transforms/Utils/SizeOpts.h"
57#include <algorithm>
58#include <cassert>
59#include <cstdint>
60#include <cstring>
61#include <string>
62#include <tuple>
63#include <utility>
64
65using namespace llvm;
66
67static cl::opt<bool> JumpIsExpensiveOverride(
68 "jump-is-expensive", cl::init(Val: false),
69 cl::desc("Do not create extra branches to split comparison logic."),
70 cl::Hidden);
71
72static cl::opt<unsigned> MinimumJumpTableEntries
73 ("min-jump-table-entries", cl::init(Val: 4), cl::Hidden,
74 cl::desc("Set minimum number of entries to use a jump table."));
75
76static cl::opt<unsigned> MaximumJumpTableSize
77 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
78 cl::desc("Set maximum size of jump tables."));
79
80/// Minimum jump table density for normal functions.
81static cl::opt<unsigned>
82 JumpTableDensity("jump-table-density", cl::init(Val: 10), cl::Hidden,
83 cl::desc("Minimum density for building a jump table in "
84 "a normal function"));
85
86/// Minimum jump table density for -Os or -Oz functions.
87static cl::opt<unsigned> OptsizeJumpTableDensity(
88 "optsize-jump-table-density", cl::init(Val: 40), cl::Hidden,
89 cl::desc("Minimum density for building a jump table in "
90 "an optsize function"));
91
92static cl::opt<unsigned> MinimumBitTestCmpsOverride(
93 "min-bit-test-cmps", cl::init(Val: 2), cl::Hidden,
94 cl::desc("Set minimum of largest number of comparisons "
95 "to use bit test for switch."));
96
97static cl::opt<unsigned> MaxStoresPerMemsetOverride(
98 "max-store-memset", cl::init(Val: 0), cl::Hidden,
99 cl::desc("Override target's MaxStoresPerMemset and "
100 "MaxStoresPerMemsetOptSize. "
101 "Set to 0 to use the target default."));
102
103static cl::opt<unsigned> MaxStoresPerMemcpyOverride(
104 "max-store-memcpy", cl::init(Val: 0), cl::Hidden,
105 cl::desc("Override target's MaxStoresPerMemcpy and "
106 "MaxStoresPerMemcpyOptSize. "
107 "Set to 0 to use the target default."));
108
109static cl::opt<unsigned> MaxStoresPerMemmoveOverride(
110 "max-store-memmove", cl::init(Val: 0), cl::Hidden,
111 cl::desc("Override target's MaxStoresPerMemmove and "
112 "MaxStoresPerMemmoveOptSize. "
113 "Set to 0 to use the target default."));
114
115// FIXME: This option is only to test if the strict fp operation processed
116// correctly by preventing mutating strict fp operation to normal fp operation
117// during development. When the backend supports strict float operation, this
118// option will be meaningless.
119static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
120 cl::desc("Don't mutate strict-float node to a legalize node"),
121 cl::init(Val: false), cl::Hidden);
122
123LLVM_ABI RTLIB::Libcall RTLIB::getSHL(EVT VT) {
124 if (VT == MVT::i16)
125 return RTLIB::SHL_I16;
126 if (VT == MVT::i32)
127 return RTLIB::SHL_I32;
128 if (VT == MVT::i64)
129 return RTLIB::SHL_I64;
130 if (VT == MVT::i128)
131 return RTLIB::SHL_I128;
132
133 return RTLIB::UNKNOWN_LIBCALL;
134}
135
136LLVM_ABI RTLIB::Libcall RTLIB::getSRL(EVT VT) {
137 if (VT == MVT::i16)
138 return RTLIB::SRL_I16;
139 if (VT == MVT::i32)
140 return RTLIB::SRL_I32;
141 if (VT == MVT::i64)
142 return RTLIB::SRL_I64;
143 if (VT == MVT::i128)
144 return RTLIB::SRL_I128;
145
146 return RTLIB::UNKNOWN_LIBCALL;
147}
148
149LLVM_ABI RTLIB::Libcall RTLIB::getSRA(EVT VT) {
150 if (VT == MVT::i16)
151 return RTLIB::SRA_I16;
152 if (VT == MVT::i32)
153 return RTLIB::SRA_I32;
154 if (VT == MVT::i64)
155 return RTLIB::SRA_I64;
156 if (VT == MVT::i128)
157 return RTLIB::SRA_I128;
158
159 return RTLIB::UNKNOWN_LIBCALL;
160}
161
162LLVM_ABI RTLIB::Libcall RTLIB::getMUL(EVT VT) {
163 if (VT == MVT::i16)
164 return RTLIB::MUL_I16;
165 if (VT == MVT::i32)
166 return RTLIB::MUL_I32;
167 if (VT == MVT::i64)
168 return RTLIB::MUL_I64;
169 if (VT == MVT::i128)
170 return RTLIB::MUL_I128;
171 return RTLIB::UNKNOWN_LIBCALL;
172}
173
174LLVM_ABI RTLIB::Libcall RTLIB::getMULO(EVT VT) {
175 if (VT == MVT::i32)
176 return RTLIB::MULO_I32;
177 if (VT == MVT::i64)
178 return RTLIB::MULO_I64;
179 if (VT == MVT::i128)
180 return RTLIB::MULO_I128;
181 return RTLIB::UNKNOWN_LIBCALL;
182}
183
184LLVM_ABI RTLIB::Libcall RTLIB::getSDIV(EVT VT) {
185 if (VT == MVT::i16)
186 return RTLIB::SDIV_I16;
187 if (VT == MVT::i32)
188 return RTLIB::SDIV_I32;
189 if (VT == MVT::i64)
190 return RTLIB::SDIV_I64;
191 if (VT == MVT::i128)
192 return RTLIB::SDIV_I128;
193 return RTLIB::UNKNOWN_LIBCALL;
194}
195
196LLVM_ABI RTLIB::Libcall RTLIB::getUDIV(EVT VT) {
197 if (VT == MVT::i16)
198 return RTLIB::UDIV_I16;
199 if (VT == MVT::i32)
200 return RTLIB::UDIV_I32;
201 if (VT == MVT::i64)
202 return RTLIB::UDIV_I64;
203 if (VT == MVT::i128)
204 return RTLIB::UDIV_I128;
205 return RTLIB::UNKNOWN_LIBCALL;
206}
207
208LLVM_ABI RTLIB::Libcall RTLIB::getSREM(EVT VT) {
209 if (VT == MVT::i16)
210 return RTLIB::SREM_I16;
211 if (VT == MVT::i32)
212 return RTLIB::SREM_I32;
213 if (VT == MVT::i64)
214 return RTLIB::SREM_I64;
215 if (VT == MVT::i128)
216 return RTLIB::SREM_I128;
217 return RTLIB::UNKNOWN_LIBCALL;
218}
219
220LLVM_ABI RTLIB::Libcall RTLIB::getUREM(EVT VT) {
221 if (VT == MVT::i16)
222 return RTLIB::UREM_I16;
223 if (VT == MVT::i32)
224 return RTLIB::UREM_I32;
225 if (VT == MVT::i64)
226 return RTLIB::UREM_I64;
227 if (VT == MVT::i128)
228 return RTLIB::UREM_I128;
229 return RTLIB::UNKNOWN_LIBCALL;
230}
231
232LLVM_ABI RTLIB::Libcall RTLIB::getCTPOP(EVT VT) {
233 if (VT == MVT::i32)
234 return RTLIB::CTPOP_I32;
235 if (VT == MVT::i64)
236 return RTLIB::CTPOP_I64;
237 if (VT == MVT::i128)
238 return RTLIB::CTPOP_I128;
239 return RTLIB::UNKNOWN_LIBCALL;
240}
241
242/// GetFPLibCall - Helper to return the right libcall for the given floating
243/// point type, or UNKNOWN_LIBCALL if there is none.
244RTLIB::Libcall RTLIB::getFPLibCall(EVT VT,
245 RTLIB::Libcall Call_F32,
246 RTLIB::Libcall Call_F64,
247 RTLIB::Libcall Call_F80,
248 RTLIB::Libcall Call_F128,
249 RTLIB::Libcall Call_PPCF128) {
250 return
251 VT == MVT::f32 ? Call_F32 :
252 VT == MVT::f64 ? Call_F64 :
253 VT == MVT::f80 ? Call_F80 :
254 VT == MVT::f128 ? Call_F128 :
255 VT == MVT::ppcf128 ? Call_PPCF128 :
256 RTLIB::UNKNOWN_LIBCALL;
257}
258
259/// getFPEXT - Return the FPEXT_*_* value for the given types, or
260/// UNKNOWN_LIBCALL if there is none.
261RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
262 if (OpVT == MVT::f16) {
263 if (RetVT == MVT::f32)
264 return FPEXT_F16_F32;
265 if (RetVT == MVT::f64)
266 return FPEXT_F16_F64;
267 if (RetVT == MVT::f80)
268 return FPEXT_F16_F80;
269 if (RetVT == MVT::f128)
270 return FPEXT_F16_F128;
271 } else if (OpVT == MVT::f32) {
272 if (RetVT == MVT::f64)
273 return FPEXT_F32_F64;
274 if (RetVT == MVT::f128)
275 return FPEXT_F32_F128;
276 if (RetVT == MVT::ppcf128)
277 return FPEXT_F32_PPCF128;
278 } else if (OpVT == MVT::f64) {
279 if (RetVT == MVT::f128)
280 return FPEXT_F64_F128;
281 else if (RetVT == MVT::ppcf128)
282 return FPEXT_F64_PPCF128;
283 } else if (OpVT == MVT::f80) {
284 if (RetVT == MVT::f128)
285 return FPEXT_F80_F128;
286 } else if (OpVT == MVT::bf16) {
287 if (RetVT == MVT::f32)
288 return FPEXT_BF16_F32;
289 }
290
291 return UNKNOWN_LIBCALL;
292}
293
294/// getFPROUND - Return the FPROUND_*_* value for the given types, or
295/// UNKNOWN_LIBCALL if there is none.
296RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
297 if (RetVT == MVT::f16) {
298 if (OpVT == MVT::f32)
299 return FPROUND_F32_F16;
300 if (OpVT == MVT::f64)
301 return FPROUND_F64_F16;
302 if (OpVT == MVT::f80)
303 return FPROUND_F80_F16;
304 if (OpVT == MVT::f128)
305 return FPROUND_F128_F16;
306 if (OpVT == MVT::ppcf128)
307 return FPROUND_PPCF128_F16;
308 } else if (RetVT == MVT::bf16) {
309 if (OpVT == MVT::f32)
310 return FPROUND_F32_BF16;
311 if (OpVT == MVT::f64)
312 return FPROUND_F64_BF16;
313 if (OpVT == MVT::f80)
314 return FPROUND_F80_BF16;
315 if (OpVT == MVT::f128)
316 return FPROUND_F128_BF16;
317 } else if (RetVT == MVT::f32) {
318 if (OpVT == MVT::f64)
319 return FPROUND_F64_F32;
320 if (OpVT == MVT::f80)
321 return FPROUND_F80_F32;
322 if (OpVT == MVT::f128)
323 return FPROUND_F128_F32;
324 if (OpVT == MVT::ppcf128)
325 return FPROUND_PPCF128_F32;
326 } else if (RetVT == MVT::f64) {
327 if (OpVT == MVT::f80)
328 return FPROUND_F80_F64;
329 if (OpVT == MVT::f128)
330 return FPROUND_F128_F64;
331 if (OpVT == MVT::ppcf128)
332 return FPROUND_PPCF128_F64;
333 } else if (RetVT == MVT::f80) {
334 if (OpVT == MVT::f128)
335 return FPROUND_F128_F80;
336 }
337
338 return UNKNOWN_LIBCALL;
339}
340
341/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
342/// UNKNOWN_LIBCALL if there is none.
343RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
344 if (OpVT == MVT::f16) {
345 if (RetVT == MVT::i32)
346 return FPTOSINT_F16_I32;
347 if (RetVT == MVT::i64)
348 return FPTOSINT_F16_I64;
349 if (RetVT == MVT::i128)
350 return FPTOSINT_F16_I128;
351 } else if (OpVT == MVT::f32) {
352 if (RetVT == MVT::i32)
353 return FPTOSINT_F32_I32;
354 if (RetVT == MVT::i64)
355 return FPTOSINT_F32_I64;
356 if (RetVT == MVT::i128)
357 return FPTOSINT_F32_I128;
358 } else if (OpVT == MVT::f64) {
359 if (RetVT == MVT::i32)
360 return FPTOSINT_F64_I32;
361 if (RetVT == MVT::i64)
362 return FPTOSINT_F64_I64;
363 if (RetVT == MVT::i128)
364 return FPTOSINT_F64_I128;
365 } else if (OpVT == MVT::f80) {
366 if (RetVT == MVT::i32)
367 return FPTOSINT_F80_I32;
368 if (RetVT == MVT::i64)
369 return FPTOSINT_F80_I64;
370 if (RetVT == MVT::i128)
371 return FPTOSINT_F80_I128;
372 } else if (OpVT == MVT::f128) {
373 if (RetVT == MVT::i32)
374 return FPTOSINT_F128_I32;
375 if (RetVT == MVT::i64)
376 return FPTOSINT_F128_I64;
377 if (RetVT == MVT::i128)
378 return FPTOSINT_F128_I128;
379 } else if (OpVT == MVT::ppcf128) {
380 if (RetVT == MVT::i32)
381 return FPTOSINT_PPCF128_I32;
382 if (RetVT == MVT::i64)
383 return FPTOSINT_PPCF128_I64;
384 if (RetVT == MVT::i128)
385 return FPTOSINT_PPCF128_I128;
386 }
387 return UNKNOWN_LIBCALL;
388}
389
390/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
391/// UNKNOWN_LIBCALL if there is none.
392RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
393 if (OpVT == MVT::f16) {
394 if (RetVT == MVT::i32)
395 return FPTOUINT_F16_I32;
396 if (RetVT == MVT::i64)
397 return FPTOUINT_F16_I64;
398 if (RetVT == MVT::i128)
399 return FPTOUINT_F16_I128;
400 } else if (OpVT == MVT::f32) {
401 if (RetVT == MVT::i32)
402 return FPTOUINT_F32_I32;
403 if (RetVT == MVT::i64)
404 return FPTOUINT_F32_I64;
405 if (RetVT == MVT::i128)
406 return FPTOUINT_F32_I128;
407 } else if (OpVT == MVT::f64) {
408 if (RetVT == MVT::i32)
409 return FPTOUINT_F64_I32;
410 if (RetVT == MVT::i64)
411 return FPTOUINT_F64_I64;
412 if (RetVT == MVT::i128)
413 return FPTOUINT_F64_I128;
414 } else if (OpVT == MVT::f80) {
415 if (RetVT == MVT::i32)
416 return FPTOUINT_F80_I32;
417 if (RetVT == MVT::i64)
418 return FPTOUINT_F80_I64;
419 if (RetVT == MVT::i128)
420 return FPTOUINT_F80_I128;
421 } else if (OpVT == MVT::f128) {
422 if (RetVT == MVT::i32)
423 return FPTOUINT_F128_I32;
424 if (RetVT == MVT::i64)
425 return FPTOUINT_F128_I64;
426 if (RetVT == MVT::i128)
427 return FPTOUINT_F128_I128;
428 } else if (OpVT == MVT::ppcf128) {
429 if (RetVT == MVT::i32)
430 return FPTOUINT_PPCF128_I32;
431 if (RetVT == MVT::i64)
432 return FPTOUINT_PPCF128_I64;
433 if (RetVT == MVT::i128)
434 return FPTOUINT_PPCF128_I128;
435 }
436 return UNKNOWN_LIBCALL;
437}
438
439/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
440/// UNKNOWN_LIBCALL if there is none.
441RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
442 if (OpVT == MVT::i32) {
443 if (RetVT == MVT::f16)
444 return SINTTOFP_I32_F16;
445 if (RetVT == MVT::f32)
446 return SINTTOFP_I32_F32;
447 if (RetVT == MVT::f64)
448 return SINTTOFP_I32_F64;
449 if (RetVT == MVT::f80)
450 return SINTTOFP_I32_F80;
451 if (RetVT == MVT::f128)
452 return SINTTOFP_I32_F128;
453 if (RetVT == MVT::ppcf128)
454 return SINTTOFP_I32_PPCF128;
455 } else if (OpVT == MVT::i64) {
456 if (RetVT == MVT::bf16)
457 return SINTTOFP_I64_BF16;
458 if (RetVT == MVT::f16)
459 return SINTTOFP_I64_F16;
460 if (RetVT == MVT::f32)
461 return SINTTOFP_I64_F32;
462 if (RetVT == MVT::f64)
463 return SINTTOFP_I64_F64;
464 if (RetVT == MVT::f80)
465 return SINTTOFP_I64_F80;
466 if (RetVT == MVT::f128)
467 return SINTTOFP_I64_F128;
468 if (RetVT == MVT::ppcf128)
469 return SINTTOFP_I64_PPCF128;
470 } else if (OpVT == MVT::i128) {
471 if (RetVT == MVT::f16)
472 return SINTTOFP_I128_F16;
473 if (RetVT == MVT::f32)
474 return SINTTOFP_I128_F32;
475 if (RetVT == MVT::f64)
476 return SINTTOFP_I128_F64;
477 if (RetVT == MVT::f80)
478 return SINTTOFP_I128_F80;
479 if (RetVT == MVT::f128)
480 return SINTTOFP_I128_F128;
481 if (RetVT == MVT::ppcf128)
482 return SINTTOFP_I128_PPCF128;
483 }
484 return UNKNOWN_LIBCALL;
485}
486
487/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
488/// UNKNOWN_LIBCALL if there is none.
489RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
490 if (OpVT == MVT::i32) {
491 if (RetVT == MVT::f16)
492 return UINTTOFP_I32_F16;
493 if (RetVT == MVT::f32)
494 return UINTTOFP_I32_F32;
495 if (RetVT == MVT::f64)
496 return UINTTOFP_I32_F64;
497 if (RetVT == MVT::f80)
498 return UINTTOFP_I32_F80;
499 if (RetVT == MVT::f128)
500 return UINTTOFP_I32_F128;
501 if (RetVT == MVT::ppcf128)
502 return UINTTOFP_I32_PPCF128;
503 } else if (OpVT == MVT::i64) {
504 if (RetVT == MVT::bf16)
505 return UINTTOFP_I64_BF16;
506 if (RetVT == MVT::f16)
507 return UINTTOFP_I64_F16;
508 if (RetVT == MVT::f32)
509 return UINTTOFP_I64_F32;
510 if (RetVT == MVT::f64)
511 return UINTTOFP_I64_F64;
512 if (RetVT == MVT::f80)
513 return UINTTOFP_I64_F80;
514 if (RetVT == MVT::f128)
515 return UINTTOFP_I64_F128;
516 if (RetVT == MVT::ppcf128)
517 return UINTTOFP_I64_PPCF128;
518 } else if (OpVT == MVT::i128) {
519 if (RetVT == MVT::f16)
520 return UINTTOFP_I128_F16;
521 if (RetVT == MVT::f32)
522 return UINTTOFP_I128_F32;
523 if (RetVT == MVT::f64)
524 return UINTTOFP_I128_F64;
525 if (RetVT == MVT::f80)
526 return UINTTOFP_I128_F80;
527 if (RetVT == MVT::f128)
528 return UINTTOFP_I128_F128;
529 if (RetVT == MVT::ppcf128)
530 return UINTTOFP_I128_PPCF128;
531 }
532 return UNKNOWN_LIBCALL;
533}
534
535// The floating-point RTLIB::getXXX(EVT) selectors are generated from the
536// RuntimeLibcallFamily table in RuntimeLibcalls.td.
537#define GET_RUNTIME_LIBCALL_FP_SELECTORS
538#include "llvm/IR/RuntimeLibcalls.inc"
539
540RTLIB::Libcall RTLIB::getOutlineAtomicHelper(const Libcall (&LC)[5][4],
541 AtomicOrdering Order,
542 uint64_t MemSize) {
543 unsigned ModeN, ModelN;
544 switch (MemSize) {
545 case 1:
546 ModeN = 0;
547 break;
548 case 2:
549 ModeN = 1;
550 break;
551 case 4:
552 ModeN = 2;
553 break;
554 case 8:
555 ModeN = 3;
556 break;
557 case 16:
558 ModeN = 4;
559 break;
560 default:
561 return RTLIB::UNKNOWN_LIBCALL;
562 }
563
564 switch (Order) {
565 case AtomicOrdering::Monotonic:
566 ModelN = 0;
567 break;
568 case AtomicOrdering::Acquire:
569 ModelN = 1;
570 break;
571 case AtomicOrdering::Release:
572 ModelN = 2;
573 break;
574 case AtomicOrdering::AcquireRelease:
575 case AtomicOrdering::SequentiallyConsistent:
576 ModelN = 3;
577 break;
578 default:
579 return UNKNOWN_LIBCALL;
580 }
581
582 return LC[ModeN][ModelN];
583}
584
585RTLIB::Libcall RTLIB::getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order,
586 MVT VT) {
587 if (!VT.isScalarInteger())
588 return UNKNOWN_LIBCALL;
589 uint64_t MemSize = VT.getScalarSizeInBits() / 8;
590
591#define LCALLS(A, B) \
592 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
593#define LCALL5(A) \
594 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
595 switch (Opc) {
596 case ISD::ATOMIC_CMP_SWAP: {
597 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
598 return getOutlineAtomicHelper(LC, Order, MemSize);
599 }
600 case ISD::ATOMIC_SWAP: {
601 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};
602 return getOutlineAtomicHelper(LC, Order, MemSize);
603 }
604 case ISD::ATOMIC_LOAD_ADD: {
605 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};
606 return getOutlineAtomicHelper(LC, Order, MemSize);
607 }
608 case ISD::ATOMIC_LOAD_OR: {
609 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};
610 return getOutlineAtomicHelper(LC, Order, MemSize);
611 }
612 case ISD::ATOMIC_LOAD_CLR: {
613 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};
614 return getOutlineAtomicHelper(LC, Order, MemSize);
615 }
616 case ISD::ATOMIC_LOAD_XOR: {
617 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};
618 return getOutlineAtomicHelper(LC, Order, MemSize);
619 }
620 default:
621 return UNKNOWN_LIBCALL;
622 }
623#undef LCALLS
624#undef LCALL5
625}
626
627RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
628#define OP_TO_LIBCALL(Name, Enum) \
629 case Name: \
630 switch (VT.SimpleTy) { \
631 default: \
632 return UNKNOWN_LIBCALL; \
633 case MVT::i8: \
634 return Enum##_1; \
635 case MVT::i16: \
636 return Enum##_2; \
637 case MVT::i32: \
638 return Enum##_4; \
639 case MVT::i64: \
640 return Enum##_8; \
641 case MVT::i128: \
642 return Enum##_16; \
643 }
644
645 switch (Opc) {
646 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
647 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
648 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
649 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
650 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
651 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
652 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
653 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
654 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
655 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
656 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
657 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
658 }
659
660#undef OP_TO_LIBCALL
661
662 return UNKNOWN_LIBCALL;
663}
664
665RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
666 switch (ElementSize) {
667 case 1:
668 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
669 case 2:
670 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
671 case 4:
672 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
673 case 8:
674 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
675 case 16:
676 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
677 default:
678 return UNKNOWN_LIBCALL;
679 }
680}
681
682RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
683 switch (ElementSize) {
684 case 1:
685 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
686 case 2:
687 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
688 case 4:
689 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
690 case 8:
691 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
692 case 16:
693 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
694 default:
695 return UNKNOWN_LIBCALL;
696 }
697}
698
699RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
700 switch (ElementSize) {
701 case 1:
702 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
703 case 2:
704 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
705 case 4:
706 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
707 case 8:
708 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
709 case 16:
710 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
711 default:
712 return UNKNOWN_LIBCALL;
713 }
714}
715
716/// NOTE: The TargetMachine owns TLOF.
717TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
718 const TargetSubtargetInfo &STI)
719 : TM(tm),
720 RuntimeLibcallInfo(TM.getTargetTriple(), TM.Options.ExceptionModel,
721 TM.getTargetTriple().getDefaultFloatABI(),
722 TM.Options.MCOptions.getABIName(), TM.Options.VecLib),
723 Libcalls(RuntimeLibcallInfo, [&STI](LibcallLoweringInfo &Info) {
724 STI.initLibcallLoweringInfo(Info);
725 }) {
726 initActions();
727
728 // Perform these initializations only once.
729 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove =
730 MaxLoadsPerMemcmp = 8;
731 MaxGluedStoresPerMemcpy = 0;
732 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize =
733 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4;
734 HasExtractBitsInsn = false;
735 JumpIsExpensive = JumpIsExpensiveOverride;
736 PredictableSelectIsExpensive = false;
737 EnableExtLdPromotion = false;
738 StackPointerRegisterToSaveRestore = 0;
739 BooleanContents = UndefinedBooleanContent;
740 BooleanFloatContents = UndefinedBooleanContent;
741 BooleanVectorContents = UndefinedBooleanContent;
742 SchedPreferenceInfo = Sched::ILP;
743 GatherAllAliasesMaxDepth = 18;
744 IsStrictFPEnabled = DisableStrictNodeMutation;
745 MaxBytesForAlignment = 0;
746 MaxAtomicSizeInBitsSupported = 0;
747
748 // Assume that even with libcalls, no target supports wider than 128 bit
749 // division.
750 MaxDivRemBitWidthSupported = 128;
751
752 MaxLargeFPConvertBitWidthSupported = 128;
753
754 MinCmpXchgSizeInBits = 0;
755 SupportsUnalignedAtomics = false;
756
757 MinimumBitTestCmps = MinimumBitTestCmpsOverride;
758}
759
760// Define the virtual destructor out-of-line to act as a key method to anchor
761// debug info (see coding standards).
762TargetLoweringBase::~TargetLoweringBase() = default;
763
764void TargetLoweringBase::initActions() {
765 // All operations default to being supported.
766 memset(s: OpActions, c: 0, n: sizeof(OpActions));
767 memset(s: LoadExtActions, c: 0, n: sizeof(LoadExtActions));
768 memset(s: AtomicLoadExtActions, c: 0, n: sizeof(AtomicLoadExtActions));
769 memset(s: TruncStoreActions, c: 0, n: sizeof(TruncStoreActions));
770 memset(s: IndexedModeActions, c: 0, n: sizeof(IndexedModeActions));
771 memset(s: CondCodeActions, c: 0, n: sizeof(CondCodeActions));
772 llvm::fill(Range&: RegClassForVT, Value: nullptr);
773 llvm::fill(Range&: TargetDAGCombineArray, Value: 0);
774
775 // Let extending atomic loads be unsupported by default.
776 for (MVT ValVT : MVT::all_valuetypes())
777 for (MVT MemVT : MVT::all_valuetypes())
778 setAtomicLoadExtAction(ExtTypes: {ISD::SEXTLOAD, ISD::ZEXTLOAD}, ValVT, MemVT,
779 Action: Expand);
780
781 // We're somewhat special casing MVT::i2 and MVT::i4. Ideally we want to
782 // remove this and targets should individually set these types if not legal.
783 for (ISD::NodeType NT : enum_seq(Begin: ISD::DELETED_NODE, End: ISD::BUILTIN_OP_END,
784 force_iteration_on_noniterable_enum)) {
785 for (MVT VT : {MVT::i2, MVT::i4})
786 OpActions[(unsigned)VT.SimpleTy][NT] = Expand;
787 }
788 for (MVT AVT : MVT::all_valuetypes()) {
789 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {
790 setTruncStoreAction(ValVT: AVT, MemVT: VT, Action: Expand);
791 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: AVT, MemVT: VT, Action: Expand);
792 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: AVT, MemVT: VT, Action: Expand);
793 }
794 }
795 for (unsigned IM = (unsigned)ISD::PRE_INC;
796 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
797 for (MVT VT : {MVT::i2, MVT::i4}) {
798 setIndexedLoadAction(IdxModes: IM, VT, Action: Expand);
799 setIndexedStoreAction(IdxModes: IM, VT, Action: Expand);
800 setIndexedMaskedLoadAction(IdxMode: IM, VT, Action: Expand);
801 setIndexedMaskedStoreAction(IdxMode: IM, VT, Action: Expand);
802 }
803 }
804
805 for (MVT VT : MVT::fp_valuetypes()) {
806 MVT IntVT = MVT::getIntegerVT(BitWidth: VT.getFixedSizeInBits());
807 if (IntVT.isValid()) {
808 setOperationAction(Op: ISD::ATOMIC_SWAP, VT, Action: Promote);
809 AddPromotedToType(Opc: ISD::ATOMIC_SWAP, OrigVT: VT, DestVT: IntVT);
810 }
811 }
812
813 // If f16 fma is not natively supported, the value must be promoted to an f64
814 // (and not to f32!) to prevent double rounding issues.
815 AddPromotedToType(Opc: ISD::FMA, OrigVT: MVT::f16, DestVT: MVT::f64);
816 AddPromotedToType(Opc: ISD::STRICT_FMA, OrigVT: MVT::f16, DestVT: MVT::f64);
817
818 // Set default actions for various operations.
819 for (MVT VT : MVT::all_valuetypes()) {
820 // Default all indexed load / store to expand.
821 for (unsigned IM = (unsigned)ISD::PRE_INC;
822 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
823 setIndexedLoadAction(IdxModes: IM, VT, Action: Expand);
824 setIndexedStoreAction(IdxModes: IM, VT, Action: Expand);
825 setIndexedMaskedLoadAction(IdxMode: IM, VT, Action: Expand);
826 setIndexedMaskedStoreAction(IdxMode: IM, VT, Action: Expand);
827 }
828
829 // Most backends expect to see the node which just returns the value loaded.
830 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Action: Expand);
831
832 // clang-format off
833 // These operations default to expand.
834 setOperationAction(Ops: {ISD::FGETSIGN, ISD::CONCAT_VECTORS,
835 ISD::FMINNUM, ISD::FMAXNUM,
836 ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
837 ISD::FMINIMUM, ISD::FMAXIMUM,
838 ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM,
839 ISD::FMAD, ISD::SMIN,
840 ISD::SMAX, ISD::UMIN,
841 ISD::UMAX, ISD::ABS,
842 ISD::FSHL, ISD::FSHR,
843 ISD::SADDSAT, ISD::UADDSAT,
844 ISD::SSUBSAT, ISD::USUBSAT,
845 ISD::SSHLSAT, ISD::USHLSAT,
846 ISD::SMULFIX, ISD::SMULFIXSAT,
847 ISD::UMULFIX, ISD::UMULFIXSAT,
848 ISD::SDIVFIX, ISD::SDIVFIXSAT,
849 ISD::UDIVFIX, ISD::UDIVFIXSAT,
850 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT,
851 ISD::IS_FPCLASS, ISD::FCBRT,
852 ISD::FLOG, ISD::FLOG2,
853 ISD::FLOG10, ISD::FEXP,
854 ISD::FEXP2, ISD::FEXP10,
855 ISD::FFLOOR, ISD::FNEARBYINT,
856 ISD::FCEIL, ISD::FRINT,
857 ISD::FTRUNC, ISD::FROUNDEVEN,
858 ISD::FTAN, ISD::FACOS,
859 ISD::FASIN, ISD::FATAN,
860 ISD::FCOSH, ISD::FSINH,
861 ISD::FTANH, ISD::FATAN2,
862 ISD::FMULADD, ISD::CONVERT_FROM_ARBITRARY_FP,
863 ISD::CONVERT_TO_ARBITRARY_FP,
864 ISD::PSEUDO_FMIN, ISD::PSEUDO_FMAX},
865 VT, Action: Expand);
866 // clang-format on
867
868 // Overflow operations default to expand
869 setOperationAction(Ops: {ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO,
870 ISD::SMULO, ISD::UMULO},
871 VT, Action: Expand);
872
873 // Carry-using overflow operations default to expand.
874 setOperationAction(Ops: {ISD::UADDO_CARRY, ISD::USUBO_CARRY, ISD::SETCCCARRY,
875 ISD::SADDO_CARRY, ISD::SSUBO_CARRY},
876 VT, Action: Expand);
877
878 // ADDC/ADDE/SUBC/SUBE default to expand.
879 setOperationAction(Ops: {ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT,
880 Action: Expand);
881
882 // [US]CMP default to expand
883 setOperationAction(Ops: {ISD::UCMP, ISD::SCMP}, VT, Action: Expand);
884
885 // Halving adds
886 setOperationAction(
887 Ops: {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT,
888 Action: Expand);
889
890 // Absolute difference
891 setOperationAction(Ops: {ISD::ABDS, ISD::ABDU}, VT, Action: Expand);
892
893 // Carry-less multiply
894 setOperationAction(Ops: {ISD::CLMUL, ISD::CLMULR, ISD::CLMULH}, VT, Action: Expand);
895
896 // Bit extract/deposit (compress/expand)
897 setOperationAction(Ops: {ISD::PEXT, ISD::PDEP}, VT, Action: Expand);
898
899 // Saturated trunc
900 setOperationAction(Op: ISD::TRUNCATE_SSAT_S, VT, Action: Expand);
901 setOperationAction(Op: ISD::TRUNCATE_SSAT_U, VT, Action: Expand);
902 setOperationAction(Op: ISD::TRUNCATE_USAT_U, VT, Action: Expand);
903
904 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
905 setOperationAction(Ops: {ISD::CTLZ_ZERO_POISON, ISD::CTTZ_ZERO_POISON}, VT,
906 Action: Expand);
907
908 // This defaults to Expand so it will be expanded to ABS by default.
909 setOperationAction(Op: ISD::ABS_MIN_POISON, VT, Action: Expand);
910 setOperationAction(Op: ISD::CTLS, VT, Action: Expand);
911
912 setOperationAction(Ops: {ISD::BITREVERSE, ISD::PARITY}, VT, Action: Expand);
913
914 // These library functions default to expand.
915 setOperationAction(Ops: {ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP,
916 ISD::FSINCOS, ISD::FSINCOSPI, ISD::FMODF},
917 VT, Action: Expand);
918
919 // These operations default to expand for vector types.
920 if (VT.isVector())
921 setOperationAction(Ops: {ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG,
922 ISD::ANY_EXTEND_VECTOR_INREG,
923 ISD::SIGN_EXTEND_VECTOR_INREG,
924 ISD::ZERO_EXTEND_VECTOR_INREG, ISD::SPLAT_VECTOR,
925 ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
926 VT, Action: Expand);
927
928 // Constrained floating-point operations default to expand.
929#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
930 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
931#include "llvm/IR/ConstrainedOps.def"
932 setOperationAction(Op: ISD::STRICT_PSEUDO_FMIN, VT, Action: Expand);
933 setOperationAction(Op: ISD::STRICT_PSEUDO_FMAX, VT, Action: Expand);
934
935 // For most targets @llvm.get.dynamic.area.offset just returns 0.
936 setOperationAction(Op: ISD::GET_DYNAMIC_AREA_OFFSET, VT, Action: Expand);
937
938 // Vector reduction default to expand.
939 setOperationAction(
940 Ops: {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD,
941 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR,
942 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN,
943 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX,
944 ISD::VECREDUCE_FMIN, ISD::VECREDUCE_FMAXIMUM, ISD::VECREDUCE_FMINIMUM,
945 ISD::VECREDUCE_FMAXIMUMNUM, ISD::VECREDUCE_FMINIMUMNUM,
946 ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_SEQ_FMUL},
947 VT, Action: Expand);
948
949 // Named vector shuffles default to expand.
950 setOperationAction(Ops: {ISD::VECTOR_SPLICE_LEFT, ISD::VECTOR_SPLICE_RIGHT}, VT,
951 Action: Expand);
952
953 // Only some target support these vector operations. Default them to Expand.
954 setOperationAction(Ops: {ISD::VECTOR_COMPRESS, ISD::VECTOR_MATCH}, VT, Action: Expand);
955
956 // cttz.elts defaults to expand.
957 setOperationAction(Ops: {ISD::CTTZ_ELTS, ISD::CTTZ_ELTS_ZERO_POISON}, VT,
958 Action: Expand);
959
960 // VP operations default to expand.
961#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \
962 setOperationAction(ISD::SDOPC, VT, Expand);
963#include "llvm/IR/VPIntrinsics.def"
964
965 // Masked vector extracts default to expand.
966 setOperationAction(Op: ISD::VECTOR_FIND_LAST_ACTIVE, VT, Action: Expand);
967
968 setOperationAction(Op: ISD::LOOP_DEPENDENCE_RAW_MASK, VT, Action: Expand);
969 setOperationAction(Op: ISD::LOOP_DEPENDENCE_WAR_MASK, VT, Action: Expand);
970
971 // FP environment operations default to expand.
972 setOperationAction(Op: ISD::GET_FPENV, VT, Action: Expand);
973 setOperationAction(Op: ISD::SET_FPENV, VT, Action: Expand);
974 setOperationAction(Op: ISD::RESET_FPENV, VT, Action: Expand);
975
976 setOperationAction(Op: ISD::MSTORE, VT, Action: Expand);
977
978 setOperationAction(Op: ISD::MASKED_UDIV, VT, Action: Expand);
979 setOperationAction(Op: ISD::MASKED_SDIV, VT, Action: Expand);
980 setOperationAction(Op: ISD::MASKED_UREM, VT, Action: Expand);
981 setOperationAction(Op: ISD::MASKED_SREM, VT, Action: Expand);
982 }
983
984 // Most targets ignore the @llvm.prefetch intrinsic.
985 setOperationAction(Op: ISD::PREFETCH, VT: MVT::Other, Action: Expand);
986
987 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
988 setOperationAction(Op: ISD::READCYCLECOUNTER, VT: MVT::i64, Action: Expand);
989
990 // Most targets also ignore the @llvm.readsteadycounter intrinsic.
991 setOperationAction(Op: ISD::READSTEADYCOUNTER, VT: MVT::i64, Action: Expand);
992
993 // ConstantFP nodes default to expand. Targets can either change this to
994 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
995 // to optimize expansions for certain constants.
996 setOperationAction(Ops: ISD::ConstantFP,
997 VTs: {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},
998 Action: Expand);
999
1000 // Insert custom handling default for llvm.canonicalize.*.
1001 setOperationAction(Ops: ISD::FCANONICALIZE,
1002 VTs: {MVT::f16, MVT::f32, MVT::f64, MVT::f128}, Action: Expand);
1003
1004 // FIXME: Query RuntimeLibCalls to make the decision.
1005 setOperationAction(Ops: {ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
1006 VTs: {MVT::f32, MVT::f64, MVT::f128}, Action: LibCall);
1007
1008 setOperationAction(Ops: {ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH,
1009 ISD::FSINH, ISD::FTANH, ISD::FATAN2},
1010 VT: MVT::f16, Action: Promote);
1011 // Default ISD::TRAP to expand (which turns it into abort).
1012 setOperationAction(Op: ISD::TRAP, VT: MVT::Other, Action: Expand);
1013
1014 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
1015 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
1016 setOperationAction(Op: ISD::DEBUGTRAP, VT: MVT::Other, Action: Expand);
1017
1018 setOperationAction(Op: ISD::UBSANTRAP, VT: MVT::Other, Action: Expand);
1019
1020 setOperationAction(Op: ISD::GET_FPENV_MEM, VT: MVT::Other, Action: Expand);
1021 setOperationAction(Op: ISD::SET_FPENV_MEM, VT: MVT::Other, Action: Expand);
1022
1023 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
1024 setOperationAction(Op: ISD::GET_FPMODE, VT, Action: Expand);
1025 setOperationAction(Op: ISD::SET_FPMODE, VT, Action: Expand);
1026 }
1027 setOperationAction(Op: ISD::RESET_FPMODE, VT: MVT::Other, Action: Expand);
1028
1029 // This one by default will call __clear_cache unless the target
1030 // wants something different.
1031 setOperationAction(Op: ISD::CLEAR_CACHE, VT: MVT::Other, Action: LibCall);
1032
1033 // By default, STACKADDRESS nodes are expanded like STACKSAVE nodes.
1034 // On SPARC targets, custom lowering is required.
1035 setOperationAction(Op: ISD::STACKADDRESS, VT: MVT::Other, Action: Expand);
1036}
1037
1038MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
1039 EVT) const {
1040 return MVT::getIntegerVT(BitWidth: DL.getPointerSizeInBits(AS: 0));
1041}
1042
1043EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,
1044 const DataLayout &DL) const {
1045 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
1046 if (LHSTy.isVector())
1047 return LHSTy;
1048 MVT ShiftVT = getScalarShiftAmountTy(DL, LHSTy);
1049 // If any possible shift value won't fit in the prefered type, just use
1050 // something safe. Assume it will be legalized when the shift is expanded.
1051 if (ShiftVT.getSizeInBits() < Log2_32_Ceil(Value: LHSTy.getSizeInBits()))
1052 ShiftVT = MVT::i32;
1053 assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) &&
1054 "ShiftVT is still too small!");
1055 return ShiftVT;
1056}
1057
1058bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
1059 assert(isTypeLegal(VT));
1060 switch (Op) {
1061 default:
1062 return false;
1063 case ISD::SDIV:
1064 case ISD::UDIV:
1065 case ISD::SREM:
1066 case ISD::UREM:
1067 return true;
1068 }
1069}
1070
1071bool TargetLoweringBase::isFreeAddrSpaceCast(unsigned SrcAS,
1072 unsigned DestAS) const {
1073 return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
1074}
1075
1076unsigned TargetLoweringBase::getBitWidthForCttzElements(
1077 EVT RetVT, ElementCount EC, bool ZeroIsPoison,
1078 const ConstantRange *VScaleRange) const {
1079 // Find the smallest "sensible" element type to use for the expansion.
1080 ConstantRange CR(APInt(64, EC.getKnownMinValue()));
1081 if (EC.isScalable())
1082 CR = CR.umul_sat(Other: *VScaleRange);
1083
1084 if (ZeroIsPoison)
1085 CR = CR.subtract(CI: APInt(64, 1));
1086
1087 unsigned EltWidth = RetVT.getScalarSizeInBits();
1088 EltWidth = std::min(a: EltWidth, b: CR.getActiveBits());
1089 EltWidth = std::max(a: llvm::bit_ceil(Value: EltWidth), b: (unsigned)8);
1090
1091 return EltWidth;
1092}
1093
1094void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
1095 // If the command-line option was specified, ignore this request.
1096 if (!JumpIsExpensiveOverride.getNumOccurrences())
1097 JumpIsExpensive = isExpensive;
1098}
1099
1100TargetLoweringBase::LegalizeKind
1101TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
1102 // If this is a simple type, use the ComputeRegisterProp mechanism.
1103 if (VT.isSimple()) {
1104 MVT SVT = VT.getSimpleVT();
1105 assert((unsigned)SVT.SimpleTy < std::size(TransformToType));
1106 MVT NVT = TransformToType[SVT.SimpleTy];
1107 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(VT: SVT);
1108
1109 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
1110 LA == TypeSoftPromoteHalf ||
1111 (NVT.isVector() ||
1112 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
1113 "Promote may not follow Expand or Promote");
1114
1115 if (LA == TypeSplitVector)
1116 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
1117 if (LA == TypeScalarizeVector)
1118 return LegalizeKind(LA, SVT.getVectorElementType());
1119 return LegalizeKind(LA, NVT);
1120 }
1121
1122 // Handle Extended Scalar Types.
1123 if (!VT.isVector()) {
1124 assert(VT.isInteger() && "Float types must be simple");
1125 unsigned BitSize = VT.getSizeInBits();
1126 // First promote to a power-of-two size, then expand if necessary.
1127 if (BitSize < 8 || !isPowerOf2_32(Value: BitSize)) {
1128 EVT NVT = VT.getRoundIntegerType(Context);
1129 assert(NVT != VT && "Unable to round integer VT");
1130 LegalizeKind NextStep = getTypeConversion(Context, VT: NVT);
1131 // Avoid multi-step promotion.
1132 if (NextStep.first == TypePromoteInteger)
1133 return NextStep;
1134 // Return rounded integer type.
1135 return LegalizeKind(TypePromoteInteger, NVT);
1136 }
1137
1138 return LegalizeKind(TypeExpandInteger,
1139 EVT::getIntegerVT(Context, BitWidth: VT.getSizeInBits() / 2));
1140 }
1141
1142 // Handle vector types.
1143 ElementCount NumElts = VT.getVectorElementCount();
1144 EVT EltVT = VT.getVectorElementType();
1145
1146 // Vectors with only one element are always scalarized.
1147 if (NumElts.isScalar())
1148 return LegalizeKind(TypeScalarizeVector, EltVT);
1149
1150 // Try to widen vector elements until the element type is a power of two and
1151 // promote it to a legal type later on, for example:
1152 // <3 x i8> -> <4 x i8> -> <4 x i32>
1153 if (EltVT.isInteger()) {
1154 // Vectors with a number of elements that is not a power of two are always
1155 // widened, for example <3 x i8> -> <4 x i8>.
1156 if (!VT.isPow2VectorType()) {
1157 NumElts = NumElts.coefficientNextPowerOf2();
1158 EVT NVT = EVT::getVectorVT(Context, VT: EltVT, EC: NumElts);
1159 return LegalizeKind(TypeWidenVector, NVT);
1160 }
1161
1162 // Examine the element type.
1163 LegalizeKind LK = getTypeConversion(Context, VT: EltVT);
1164
1165 // If type is to be expanded, split the vector.
1166 // <4 x i140> -> <2 x i140>
1167 if (LK.first == TypeExpandInteger) {
1168 if (NumElts.isScalable() && NumElts.getKnownMinValue() == 1)
1169 return LegalizeKind(TypeScalarizeScalableVector, EltVT);
1170 return LegalizeKind(TypeSplitVector,
1171 VT.getHalfNumVectorElementsVT(Context));
1172 }
1173
1174 // Promote the integer element types until a legal vector type is found
1175 // or until the element integer type is too big. If a legal type was not
1176 // found, fallback to the usual mechanism of widening/splitting the
1177 // vector.
1178 EVT OldEltVT = EltVT;
1179 while (true) {
1180 // Increase the bitwidth of the element to the next pow-of-two
1181 // (which is greater than 8 bits).
1182 EltVT = EVT::getIntegerVT(Context, BitWidth: 1 + EltVT.getSizeInBits())
1183 .getRoundIntegerType(Context);
1184
1185 // Stop trying when getting a non-simple element type.
1186 // Note that vector elements may be greater than legal vector element
1187 // types. Example: X86 XMM registers hold 64bit element on 32bit
1188 // systems.
1189 if (!EltVT.isSimple())
1190 break;
1191
1192 // Build a new vector type and check if it is legal.
1193 MVT NVT = MVT::getVectorVT(VT: EltVT.getSimpleVT(), EC: NumElts);
1194 // Found a legal promoted vector type.
1195 if (NVT != MVT() && ValueTypeActions.getTypeAction(VT: NVT) == TypeLegal)
1196 return LegalizeKind(TypePromoteInteger,
1197 EVT::getVectorVT(Context, VT: EltVT, EC: NumElts));
1198 }
1199
1200 // Reset the type to the unexpanded type if we did not find a legal vector
1201 // type with a promoted vector element type.
1202 EltVT = OldEltVT;
1203 }
1204
1205 // Try to widen the vector until a legal type is found.
1206 // If there is no wider legal type, split the vector.
1207 while (true) {
1208 // Round up to the next power of 2.
1209 NumElts = NumElts.coefficientNextPowerOf2();
1210
1211 // If there is no simple vector type with this many elements then there
1212 // cannot be a larger legal vector type. Note that this assumes that
1213 // there are no skipped intermediate vector types in the simple types.
1214 if (!EltVT.isSimple())
1215 break;
1216 MVT LargerVector = MVT::getVectorVT(VT: EltVT.getSimpleVT(), EC: NumElts);
1217 if (LargerVector == MVT())
1218 break;
1219
1220 // If this type is legal then widen the vector.
1221 if (ValueTypeActions.getTypeAction(VT: LargerVector) == TypeLegal)
1222 return LegalizeKind(TypeWidenVector, LargerVector);
1223 }
1224
1225 // Widen odd vectors to next power of two.
1226 if (!VT.isPow2VectorType()) {
1227 EVT NVT = VT.getPow2VectorType(Context);
1228 return LegalizeKind(TypeWidenVector, NVT);
1229 }
1230
1231 if (VT.getVectorElementCount() == ElementCount::getScalable(MinVal: 1))
1232 return LegalizeKind(TypeScalarizeScalableVector, EltVT);
1233
1234 // Vectors with illegal element types are expanded.
1235 EVT NVT = EVT::getVectorVT(Context, VT: EltVT,
1236 EC: VT.getVectorElementCount().divideCoefficientBy(RHS: 2));
1237 return LegalizeKind(TypeSplitVector, NVT);
1238}
1239
1240unsigned TargetLoweringBase::getVectorTypeBreakdownMVT(
1241 MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) {
1242 // Figure out the right, legal destination reg to copy into.
1243 ElementCount EC = VT.getVectorElementCount();
1244 MVT EltTy = VT.getVectorElementType();
1245
1246 unsigned NumVectorRegs = 1;
1247
1248 // Scalable vectors cannot be scalarized, so splitting or widening is
1249 // required.
1250 if (VT.isScalableVector() && !isPowerOf2_32(Value: EC.getKnownMinValue()))
1251 llvm_unreachable(
1252 "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1253
1254 // FIXME: We don't support non-power-of-2-sized vectors for now.
1255 // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1256 if (!isPowerOf2_32(Value: EC.getKnownMinValue())) {
1257 // Split EC to unit size (scalable property is preserved).
1258 NumVectorRegs = EC.getKnownMinValue();
1259 EC = ElementCount::getFixed(MinVal: 1);
1260 }
1261
1262 // Divide the input until we get to a supported size. This will
1263 // always end up with an EC that represent a scalar or a scalable
1264 // scalar.
1265 while (EC.getKnownMinValue() > 1 &&
1266 !isTypeLegal(VT: MVT::getVectorVT(VT: EltTy, EC))) {
1267 EC = EC.divideCoefficientBy(RHS: 2);
1268 NumVectorRegs <<= 1;
1269 }
1270
1271 NumIntermediates = NumVectorRegs;
1272
1273 MVT NewVT = MVT::getVectorVT(VT: EltTy, EC);
1274 if (!isTypeLegal(VT: NewVT))
1275 NewVT = EltTy;
1276 IntermediateVT = NewVT;
1277
1278 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
1279
1280 // Convert sizes such as i33 to i64.
1281 LaneSizeInBits = llvm::bit_ceil(Value: LaneSizeInBits);
1282
1283 MVT DestVT = getCachedRegisterType(VT: NewVT);
1284 RegisterVT = DestVT;
1285 if (EVT(DestVT).bitsLT(VT: NewVT)) // Value is expanded, e.g. i64 -> i16.
1286 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1287
1288 // Otherwise, promotion or legal types use the same number of registers as
1289 // the vector decimated to the appropriate level.
1290 return NumVectorRegs;
1291}
1292
1293/// isLegalRC - Return true if the value types that can be represented by the
1294/// specified register class are all legal.
1295bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
1296 const TargetRegisterClass &RC) const {
1297 for (const auto *I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1298 if (isTypeLegal(VT: *I))
1299 return true;
1300 return false;
1301}
1302
1303/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1304/// sequence of memory operands that is recognized by PrologEpilogInserter.
1305MachineBasicBlock *
1306TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
1307 MachineBasicBlock *MBB) const {
1308 MachineInstr *MI = &InitialMI;
1309 MachineFunction &MF = *MI->getMF();
1310 MachineFrameInfo &MFI = MF.getFrameInfo();
1311
1312 // We're handling multiple types of operands here:
1313 // PATCHPOINT MetaArgs - live-in, read only, direct
1314 // STATEPOINT Deopt Spill - live-through, read only, indirect
1315 // STATEPOINT Deopt Alloca - live-through, read only, direct
1316 // (We're currently conservative and mark the deopt slots read/write in
1317 // practice.)
1318 // STATEPOINT GC Spill - live-through, read/write, indirect
1319 // STATEPOINT GC Alloca - live-through, read/write, direct
1320 // The live-in vs live-through is handled already (the live through ones are
1321 // all stack slots), but we need to handle the different type of stackmap
1322 // operands and memory effects here.
1323
1324 if (llvm::none_of(Range: MI->operands(),
1325 P: [](MachineOperand &Operand) { return Operand.isFI(); }))
1326 return MBB;
1327
1328 MachineInstrBuilder MIB = BuildMI(MF, MIMD: MI->getDebugLoc(), MCID: MI->getDesc());
1329
1330 // Inherit previous memory operands.
1331 MIB.cloneMemRefs(OtherMI: *MI);
1332
1333 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1334 MachineOperand &MO = MI->getOperand(i);
1335 if (!MO.isFI()) {
1336 // Index of Def operand this Use it tied to.
1337 // Since Defs are coming before Uses, if Use is tied, then
1338 // index of Def must be smaller that index of that Use.
1339 // Also, Defs preserve their position in new MI.
1340 unsigned TiedTo = i;
1341 if (MO.isReg() && MO.isTied())
1342 TiedTo = MI->findTiedOperandIdx(OpIdx: i);
1343 MIB.add(MO);
1344 if (TiedTo < i)
1345 MIB->tieOperands(DefIdx: TiedTo, UseIdx: MIB->getNumOperands() - 1);
1346 continue;
1347 }
1348
1349 // foldMemoryOperand builds a new MI after replacing a single FI operand
1350 // with the canonical set of five x86 addressing-mode operands.
1351 int FI = MO.getIndex();
1352
1353 // Add frame index operands recognized by stackmaps.cpp
1354 if (MFI.isStatepointSpillSlotObjectIndex(ObjectIdx: FI)) {
1355 // indirect-mem-ref tag, size, #FI, offset.
1356 // Used for spills inserted by StatepointLowering. This codepath is not
1357 // used for patchpoints/stackmaps at all, for these spilling is done via
1358 // foldMemoryOperand callback only.
1359 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1360 MIB.addImm(Val: StackMaps::IndirectMemRefOp);
1361 MIB.addImm(Val: MFI.getObjectSize(ObjectIdx: FI));
1362 MIB.add(MO);
1363 MIB.addImm(Val: 0);
1364 } else {
1365 // direct-mem-ref tag, #FI, offset.
1366 // Used by patchpoint, and direct alloca arguments to statepoints
1367 MIB.addImm(Val: StackMaps::DirectMemRefOp);
1368 MIB.add(MO);
1369 MIB.addImm(Val: 0);
1370 }
1371
1372 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1373
1374 // Add a new memory operand for this FI.
1375 assert(MFI.getObjectOffset(FI) != -1);
1376
1377 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1378 // PATCHPOINT should be updated to do the same. (TODO)
1379 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1380 auto Flags = MachineMemOperand::MOLoad;
1381 MachineMemOperand *MMO = MF.getMachineMemOperand(
1382 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI), F: Flags,
1383 Size: MF.getDataLayout().getPointerSize(), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
1384 MIB->addMemOperand(MF, MO: MMO);
1385 }
1386 }
1387 MBB->insert(I: MachineBasicBlock::iterator(MI), MI: MIB);
1388 MI->eraseFromParent();
1389 return MBB;
1390}
1391
1392/// findRepresentativeClass - Return the largest legal super-reg register class
1393/// of the register class for the specified type and its associated "cost".
1394// This function is in TargetLowering because it uses RegClassForVT which would
1395// need to be moved to TargetRegisterInfo and would necessitate moving
1396// isTypeLegal over as well - a massive change that would just require
1397// TargetLowering having a TargetRegisterInfo class member that it would use.
1398std::pair<const TargetRegisterClass *, uint8_t>
1399TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1400 MVT VT) const {
1401 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1402 if (!RC)
1403 return std::make_pair(x&: RC, y: 0);
1404
1405 // Compute the set of all super-register classes.
1406 BitVector SuperRegRC(TRI->getNumRegClasses());
1407 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1408 SuperRegRC.setBitsInMask(Mask: RCI.getMask());
1409
1410 // Find the first legal register class with the largest spill size.
1411 const TargetRegisterClass *BestRC = RC;
1412 for (unsigned i : SuperRegRC.set_bits()) {
1413 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1414 // We want the largest possible spill size.
1415 if (TRI->getSpillSize(RC: *SuperRC) <= TRI->getSpillSize(RC: *BestRC))
1416 continue;
1417 if (!isLegalRC(TRI: *TRI, RC: *SuperRC))
1418 continue;
1419 BestRC = SuperRC;
1420 }
1421 return std::make_pair(x&: BestRC, y: 1);
1422}
1423
1424/// computeRegisterProperties - Once all of the register classes are added,
1425/// this allows us to compute derived properties we expose.
1426void TargetLoweringBase::computeRegisterProperties(
1427 const TargetRegisterInfo *TRI) {
1428 // Everything defaults to needing one register.
1429 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1430 NumRegistersForVT[i] = 1;
1431 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1432 }
1433 // ...except isVoid, which doesn't need any registers.
1434 NumRegistersForVT[MVT::isVoid] = 0;
1435
1436 // Find the largest integer register class.
1437 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1438 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1439 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1440
1441 // Every integer value type larger than this largest register takes twice as
1442 // many registers to represent as the previous ValueType.
1443 for (unsigned ExpandedReg = LargestIntReg + 1;
1444 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1445 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1446 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1447 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1448 ValueTypeActions.setTypeAction(VT: (MVT::SimpleValueType)ExpandedReg,
1449 Action: TypeExpandInteger);
1450 }
1451
1452 // Inspect all of the ValueType's smaller than the largest integer
1453 // register to see which ones need promotion.
1454 unsigned LegalIntReg = LargestIntReg;
1455 for (unsigned IntReg = LargestIntReg - 1;
1456 IntReg >= (unsigned)MVT::i1; --IntReg) {
1457 MVT IVT = (MVT::SimpleValueType)IntReg;
1458 if (isTypeLegal(VT: IVT)) {
1459 LegalIntReg = IntReg;
1460 } else {
1461 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1462 (MVT::SimpleValueType)LegalIntReg;
1463 ValueTypeActions.setTypeAction(VT: IVT, Action: TypePromoteInteger);
1464 }
1465 }
1466
1467 // ppcf128 type is really two f64's.
1468 if (!isTypeLegal(VT: MVT::ppcf128)) {
1469 if (isTypeLegal(VT: MVT::f64)) {
1470 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1471 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1472 TransformToType[MVT::ppcf128] = MVT::f64;
1473 ValueTypeActions.setTypeAction(VT: MVT::ppcf128, Action: TypeExpandFloat);
1474 } else {
1475 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1476 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1477 TransformToType[MVT::ppcf128] = MVT::i128;
1478 ValueTypeActions.setTypeAction(VT: MVT::ppcf128, Action: TypeSoftenFloat);
1479 }
1480 }
1481
1482 // Decide how to handle f128. If the target does not have native f128 support,
1483 // expand it to i128 and we will be generating soft float library calls.
1484 if (!isTypeLegal(VT: MVT::f128)) {
1485 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1486 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1487 TransformToType[MVT::f128] = MVT::i128;
1488 ValueTypeActions.setTypeAction(VT: MVT::f128, Action: TypeSoftenFloat);
1489 }
1490
1491 // Decide how to handle f80. If the target does not have native f80 support,
1492 // expand it to i96 and we will be generating soft float library calls.
1493 if (!isTypeLegal(VT: MVT::f80)) {
1494 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];
1495 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];
1496 TransformToType[MVT::f80] = MVT::i32;
1497 ValueTypeActions.setTypeAction(VT: MVT::f80, Action: TypeSoftenFloat);
1498 }
1499
1500 // Decide how to handle f64. If the target does not have native f64 support,
1501 // expand it to i64 and we will be generating soft float library calls.
1502 if (!isTypeLegal(VT: MVT::f64)) {
1503 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1504 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1505 TransformToType[MVT::f64] = MVT::i64;
1506 ValueTypeActions.setTypeAction(VT: MVT::f64, Action: TypeSoftenFloat);
1507 }
1508
1509 // Decide how to handle f32. If the target does not have native f32 support,
1510 // expand it to i32 and we will be generating soft float library calls.
1511 if (!isTypeLegal(VT: MVT::f32)) {
1512 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1513 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1514 TransformToType[MVT::f32] = MVT::i32;
1515 ValueTypeActions.setTypeAction(VT: MVT::f32, Action: TypeSoftenFloat);
1516 }
1517
1518 // Decide how to handle f16. If the target does not have native f16 support,
1519 // promote it to f32, because there are no f16 library calls (except for
1520 // conversions).
1521 if (!isTypeLegal(VT: MVT::f16)) {
1522 // Allow targets to control how we legalize half.
1523 bool UseFPRegsForHalfType = useFPRegsForHalfType();
1524
1525 if (!UseFPRegsForHalfType) {
1526 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1527 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1528 } else {
1529 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1530 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1531 }
1532 TransformToType[MVT::f16] = MVT::f32;
1533 ValueTypeActions.setTypeAction(VT: MVT::f16, Action: TypeSoftPromoteHalf);
1534 }
1535
1536 // Decide how to handle bf16. If the target does not have native bf16 support,
1537 // promote it to f32, because there are no bf16 library calls (except for
1538 // converting from f32 to bf16).
1539 if (!isTypeLegal(VT: MVT::bf16)) {
1540 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];
1541 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];
1542 TransformToType[MVT::bf16] = MVT::f32;
1543 ValueTypeActions.setTypeAction(VT: MVT::bf16, Action: TypeSoftPromoteHalf);
1544 }
1545
1546 // Loop over all of the vector value types to see which need transformations.
1547 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1548 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1549 MVT VT = (MVT::SimpleValueType) i;
1550 if (isTypeLegal(VT))
1551 continue;
1552
1553 MVT EltVT = VT.getVectorElementType();
1554 ElementCount EC = VT.getVectorElementCount();
1555 bool IsLegalWiderType = false;
1556 bool IsScalable = VT.isScalableVector();
1557 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1558 switch (PreferredAction) {
1559 case TypePromoteInteger: {
1560 MVT::SimpleValueType EndVT = IsScalable ?
1561 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :
1562 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;
1563 // Try to promote the elements of integer vectors. If no legal
1564 // promotion was found, fall through to the widen-vector method.
1565 for (unsigned nVT = i + 1;
1566 (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1567 MVT SVT = (MVT::SimpleValueType) nVT;
1568 // Promote vectors of integers to vectors with the same number
1569 // of elements, with a wider element type.
1570 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1571 SVT.getVectorElementCount() == EC && isTypeLegal(VT: SVT)) {
1572 TransformToType[i] = SVT;
1573 RegisterTypeForVT[i] = SVT;
1574 NumRegistersForVT[i] = 1;
1575 ValueTypeActions.setTypeAction(VT, Action: TypePromoteInteger);
1576 IsLegalWiderType = true;
1577 break;
1578 }
1579 }
1580 if (IsLegalWiderType)
1581 break;
1582 [[fallthrough]];
1583 }
1584
1585 case TypeWidenVector:
1586 if (isPowerOf2_32(Value: EC.getKnownMinValue())) {
1587 // Try to widen the vector.
1588 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1589 MVT SVT = (MVT::SimpleValueType) nVT;
1590 if (SVT.getVectorElementType() == EltVT &&
1591 SVT.isScalableVector() == IsScalable &&
1592 SVT.getVectorElementCount().getKnownMinValue() >
1593 EC.getKnownMinValue() &&
1594 isTypeLegal(VT: SVT)) {
1595 TransformToType[i] = SVT;
1596 RegisterTypeForVT[i] = SVT;
1597 NumRegistersForVT[i] = 1;
1598 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1599 IsLegalWiderType = true;
1600 break;
1601 }
1602 }
1603 if (IsLegalWiderType)
1604 break;
1605 } else {
1606 // Only widen to the next power of 2 to keep consistency with EVT.
1607 MVT NVT = VT.getPow2VectorType();
1608 if (isTypeLegal(VT: NVT)) {
1609 TransformToType[i] = NVT;
1610 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1611 RegisterTypeForVT[i] = NVT;
1612 NumRegistersForVT[i] = 1;
1613 break;
1614 }
1615 }
1616 [[fallthrough]];
1617
1618 case TypeSplitVector:
1619 case TypeScalarizeVector: {
1620 MVT IntermediateVT;
1621 MVT RegisterVT;
1622 unsigned NumIntermediates;
1623 unsigned NumRegisters = getVectorTypeBreakdownMVT(
1624 VT, IntermediateVT, NumIntermediates, RegisterVT);
1625 NumRegistersForVT[i] = NumRegisters;
1626 assert(NumRegistersForVT[i] == NumRegisters &&
1627 "NumRegistersForVT size cannot represent NumRegisters!");
1628 RegisterTypeForVT[i] = RegisterVT;
1629
1630 MVT NVT = VT.getPow2VectorType();
1631 if (NVT == VT) {
1632 // Type is already a power of 2. The default action is to split.
1633 TransformToType[i] = MVT::Other;
1634 if (PreferredAction == TypeScalarizeVector)
1635 ValueTypeActions.setTypeAction(VT, Action: TypeScalarizeVector);
1636 else if (PreferredAction == TypeSplitVector)
1637 ValueTypeActions.setTypeAction(VT, Action: TypeSplitVector);
1638 else if (EC.getKnownMinValue() > 1)
1639 ValueTypeActions.setTypeAction(VT, Action: TypeSplitVector);
1640 else
1641 ValueTypeActions.setTypeAction(VT, Action: EC.isScalable()
1642 ? TypeScalarizeScalableVector
1643 : TypeScalarizeVector);
1644 } else {
1645 TransformToType[i] = NVT;
1646 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1647 }
1648 break;
1649 }
1650 default:
1651 llvm_unreachable("Unknown vector legalization action!");
1652 }
1653 }
1654
1655 // Determine the 'representative' register class for each value type.
1656 // An representative register class is the largest (meaning one which is
1657 // not a sub-register class / subreg register class) legal register class for
1658 // a group of value types. For example, on i386, i8, i16, and i32
1659 // representative would be GR32; while on x86_64 it's GR64.
1660 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1661 const TargetRegisterClass* RRC;
1662 uint8_t Cost;
1663 std::tie(args&: RRC, args&: Cost) = findRepresentativeClass(TRI, VT: (MVT::SimpleValueType)i);
1664 RepRegClassForVT[i] = RRC;
1665 RepRegClassCostForVT[i] = Cost;
1666 }
1667
1668 // Compute minimum known-legal store size.
1669 MaximumLegalStoreInBits = 0;
1670 for (MVT VT : MVT::all_valuetypes())
1671 if (VT != MVT::Other && isTypeLegal(VT) &&
1672 VT.getSizeInBits().getKnownMinValue() >= MaximumLegalStoreInBits)
1673 MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinValue();
1674}
1675
1676EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1677 EVT VT) const {
1678 assert(!VT.isVector() && "No default SetCC type for vectors!");
1679 return getPointerTy(DL).SimpleTy;
1680}
1681
1682/// getVectorTypeBreakdown - Vector types are broken down into some number of
1683/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1684/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1685/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1686///
1687/// This method returns the number of registers needed, and the VT for each
1688/// register. It also returns the VT and quantity of the intermediate values
1689/// before they are promoted/expanded.
1690unsigned TargetLoweringBase::getVectorTypeBreakdownImpl(
1691 LLVMContext &Context, EVT VT, EVT &IntermediateVT,
1692 unsigned &NumIntermediates, MVT &RegisterVT, bool ForCallingConv) const {
1693 ElementCount EltCnt = VT.getVectorElementCount();
1694
1695 // If there is a wider vector type with the same element type as this one,
1696 // or a promoted vector type that has the same number of elements which
1697 // are wider, then we should convert to that legal vector type.
1698 // This handles things like <2 x float> -> <4 x float> and
1699 // <4 x i1> -> <4 x i32>.
1700 LegalizeTypeAction TA = getTypeAction(Context, VT);
1701 if (!EltCnt.isScalar() &&
1702 (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1703 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1704 if (isTypeLegal(VT: RegisterEVT)) {
1705 IntermediateVT = RegisterEVT;
1706 RegisterVT = RegisterEVT.getSimpleVT();
1707 NumIntermediates = 1;
1708 return 1;
1709 }
1710 }
1711
1712 // Figure out the right, legal destination reg to copy into.
1713 EVT EltTy = VT.getVectorElementType();
1714
1715 unsigned NumVectorRegs = 1;
1716
1717 auto GetLegalVectorBreakdown = [&]() -> std::optional<unsigned> {
1718 LegalizeKind LK;
1719 EVT PartVT = VT;
1720 do {
1721 // Iterate until we've found a legal (part) type to hold VT.
1722 LK = getTypeConversion(Context, VT: PartVT);
1723 PartVT = LK.second;
1724 } while (LK.first != TypeLegal);
1725
1726 if (!PartVT.isVector())
1727 return std::nullopt;
1728
1729 assert(PartVT.isScalableVector() == VT.isScalableVector() &&
1730 "Vector legalization changed scalability");
1731 NumIntermediates =
1732 divideCeil(Numerator: VT.getVectorElementCount().getKnownMinValue(),
1733 Denominator: PartVT.getVectorElementCount().getKnownMinValue());
1734 IntermediateVT = PartVT;
1735 RegisterVT = getRegisterType(Context, VT: IntermediateVT);
1736 return NumIntermediates;
1737 };
1738
1739 // Scalable vectors cannot be scalarized, so handle the legalisation of the
1740 // types like done elsewhere in SelectionDAG.
1741 if (EltCnt.isScalable()) {
1742 if (std::optional<unsigned> NumRegs = GetLegalVectorBreakdown())
1743 return *NumRegs;
1744 report_fatal_error(reason: "Don't know how to legalize this scalable vector type");
1745 }
1746
1747 // FIXME: We don't generically support non-power-of-2-sized vectors for now.
1748 // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1749 if (!isPowerOf2_32(Value: EltCnt.getKnownMinValue())) {
1750 assert(VT.isFixedLengthVector() && "Expected a fixed-length vector VT");
1751 unsigned NumElts = EltCnt.getKnownMinValue();
1752
1753 if (!ForCallingConv && preferVectorizedNonPowerOfTwoTypeBreakdown())
1754 if (std::optional<unsigned> NumRegs = GetLegalVectorBreakdown())
1755 return *NumRegs;
1756
1757 // Fall back to scalars if there is no legal vector decomposition.
1758 NumVectorRegs = NumElts;
1759 EltCnt = ElementCount::getFixed(MinVal: 1);
1760 }
1761
1762 // Divide the input until we get to a supported size. This will always
1763 // end with a scalar if the target doesn't support vectors.
1764 while (EltCnt.getKnownMinValue() > 1 &&
1765 !isTypeLegal(VT: EVT::getVectorVT(Context, VT: EltTy, EC: EltCnt))) {
1766 EltCnt = EltCnt.divideCoefficientBy(RHS: 2);
1767 NumVectorRegs <<= 1;
1768 }
1769
1770 NumIntermediates = NumVectorRegs;
1771
1772 EVT NewVT = EVT::getVectorVT(Context, VT: EltTy, EC: EltCnt);
1773 if (!isTypeLegal(VT: NewVT))
1774 NewVT = EltTy;
1775 IntermediateVT = NewVT;
1776
1777 MVT DestVT = getRegisterType(Context, VT: NewVT);
1778 RegisterVT = DestVT;
1779
1780 if (EVT(DestVT).bitsLT(VT: NewVT)) { // Value is expanded, e.g. i64 -> i16.
1781 TypeSize NewVTSize = NewVT.getSizeInBits();
1782 // Convert sizes such as i33 to i64.
1783 if (!llvm::has_single_bit<uint32_t>(Value: NewVTSize.getKnownMinValue()))
1784 NewVTSize = NewVTSize.coefficientNextPowerOf2();
1785 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1786 }
1787
1788 // Otherwise, promotion or legal types use the same number of registers as
1789 // the vector decimated to the appropriate level.
1790 return NumVectorRegs;
1791}
1792
1793bool TargetLoweringBase::isSuitableForJumpTable(const SwitchInst *SI,
1794 uint64_t NumCases,
1795 uint64_t Range,
1796 ProfileSummaryInfo *PSI,
1797 BlockFrequencyInfo *BFI) const {
1798 // FIXME: This function check the maximum table size and density, but the
1799 // minimum size is not checked. It would be nice if the minimum size is
1800 // also combined within this function. Currently, the minimum size check is
1801 // performed in findJumpTable() in SelectionDAGBuiler and
1802 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1803 const bool OptForSize =
1804 llvm::shouldOptimizeForSize(BB: SI->getParent(), PSI, BFI);
1805 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1806 const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1807
1808 // Check whether the number of cases is small enough and
1809 // the range is dense enough for a jump table.
1810 return (OptForSize || Range <= MaxJumpTableSize) &&
1811 (NumCases * 100 >= Range * MinDensity);
1812}
1813
1814MVT TargetLoweringBase::getPreferredSwitchConditionType(LLVMContext &Context,
1815 EVT ConditionVT) const {
1816 return getRegisterType(Context, VT: ConditionVT);
1817}
1818
1819/// Get the EVTs and ArgFlags collections that represent the legalized return
1820/// type of the given function. This does not require a DAG or a return value,
1821/// and is suitable for use before any DAGs for the function are constructed.
1822/// TODO: Move this out of TargetLowering.cpp.
1823void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType,
1824 AttributeList attr,
1825 SmallVectorImpl<ISD::OutputArg> &Outs,
1826 const TargetLowering &TLI, const DataLayout &DL) {
1827 SmallVector<Type *, 4> Types;
1828 ComputeValueTypes(DL, Ty: ReturnType, Types);
1829 unsigned NumValues = Types.size();
1830 if (NumValues == 0) return;
1831
1832 for (Type *Ty : Types) {
1833 EVT VT = TLI.getValueType(DL, Ty);
1834 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1835
1836 if (attr.hasRetAttr(Kind: Attribute::SExt))
1837 ExtendKind = ISD::SIGN_EXTEND;
1838 else if (attr.hasRetAttr(Kind: Attribute::ZExt))
1839 ExtendKind = ISD::ZERO_EXTEND;
1840
1841 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1842 VT = TLI.getTypeForExtReturn(Context&: ReturnType->getContext(), VT, ExtendKind);
1843
1844 unsigned NumParts =
1845 TLI.getNumRegistersForCallingConv(Context&: ReturnType->getContext(), CC, VT);
1846 MVT PartVT =
1847 TLI.getRegisterTypeForCallingConv(Context&: ReturnType->getContext(), CC, VT);
1848
1849 // 'inreg' on function refers to return value
1850 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1851 if (attr.hasRetAttr(Kind: Attribute::InReg))
1852 Flags.setInReg();
1853
1854 // Propagate extension type if any
1855 if (attr.hasRetAttr(Kind: Attribute::SExt))
1856 Flags.setSExt();
1857 else if (attr.hasRetAttr(Kind: Attribute::ZExt))
1858 Flags.setZExt();
1859
1860 for (unsigned i = 0; i < NumParts; ++i)
1861 Outs.push_back(Elt: ISD::OutputArg(Flags, PartVT, VT, Ty, 0, 0));
1862 }
1863}
1864
1865Align TargetLoweringBase::getByValTypeAlignment(Type *Ty,
1866 const DataLayout &DL) const {
1867 return DL.getABITypeAlign(Ty);
1868}
1869
1870bool TargetLoweringBase::allowsMemoryAccessForAlignment(
1871 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1872 Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const {
1873 // Check if the specified alignment is sufficient based on the data layout.
1874 // TODO: While using the data layout works in practice, a better solution
1875 // would be to implement this check directly (make this a virtual function).
1876 // For example, the ABI alignment may change based on software platform while
1877 // this function should only be affected by hardware implementation.
1878 Type *Ty = VT.getTypeForEVT(Context);
1879 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {
1880 // Assume that an access that meets the ABI-specified alignment is fast.
1881 if (Fast != nullptr)
1882 *Fast = 1;
1883 return true;
1884 }
1885
1886 // This is a misaligned access.
1887 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1888}
1889
1890bool TargetLoweringBase::allowsMemoryAccessForAlignment(
1891 LLVMContext &Context, const DataLayout &DL, EVT VT,
1892 const MachineMemOperand &MMO, unsigned *Fast) const {
1893 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace: MMO.getAddrSpace(),
1894 Alignment: MMO.getAlign(), Flags: MMO.getFlags(), Fast);
1895}
1896
1897bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1898 const DataLayout &DL, EVT VT,
1899 unsigned AddrSpace, Align Alignment,
1900 MachineMemOperand::Flags Flags,
1901 unsigned *Fast) const {
1902 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1903 Flags, Fast);
1904}
1905
1906bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1907 const DataLayout &DL, EVT VT,
1908 const MachineMemOperand &MMO,
1909 unsigned *Fast) const {
1910 return allowsMemoryAccess(Context, DL, VT, AddrSpace: MMO.getAddrSpace(), Alignment: MMO.getAlign(),
1911 Flags: MMO.getFlags(), Fast);
1912}
1913
1914bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1915 const DataLayout &DL, LLT Ty,
1916 const MachineMemOperand &MMO,
1917 unsigned *Fast) const {
1918 EVT VT = getApproximateEVTForLLT(Ty, Ctx&: Context);
1919 return allowsMemoryAccess(Context, DL, VT, AddrSpace: MMO.getAddrSpace(), Alignment: MMO.getAlign(),
1920 Flags: MMO.getFlags(), Fast);
1921}
1922
1923unsigned TargetLoweringBase::getMaxStoresPerMemset(bool OptSize) const {
1924 if (MaxStoresPerMemsetOverride > 0)
1925 return MaxStoresPerMemsetOverride;
1926
1927 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1928}
1929
1930unsigned TargetLoweringBase::getMaxStoresPerMemcpy(bool OptSize) const {
1931 if (MaxStoresPerMemcpyOverride > 0)
1932 return MaxStoresPerMemcpyOverride;
1933
1934 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1935}
1936
1937unsigned TargetLoweringBase::getMaxStoresPerMemmove(bool OptSize) const {
1938 if (MaxStoresPerMemmoveOverride > 0)
1939 return MaxStoresPerMemmoveOverride;
1940
1941 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1942}
1943
1944//===----------------------------------------------------------------------===//
1945// TargetTransformInfo Helpers
1946//===----------------------------------------------------------------------===//
1947
1948int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1949 enum InstructionOpcodes {
1950#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1951#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1952#include "llvm/IR/Instruction.def"
1953 };
1954 switch (static_cast<InstructionOpcodes>(Opcode)) {
1955 case Ret: return 0;
1956 case UncondBr: return 0;
1957 case CondBr: return 0;
1958 case Switch: return 0;
1959 case IndirectBr: return 0;
1960 case Invoke: return 0;
1961 case CallBr: return 0;
1962 case Resume: return 0;
1963 case Unreachable: return 0;
1964 case CleanupRet: return 0;
1965 case CatchRet: return 0;
1966 case CatchPad: return 0;
1967 case CatchSwitch: return 0;
1968 case CleanupPad: return 0;
1969 case FNeg: return ISD::FNEG;
1970 case Add: return ISD::ADD;
1971 case FAdd: return ISD::FADD;
1972 case Sub: return ISD::SUB;
1973 case FSub: return ISD::FSUB;
1974 case Mul: return ISD::MUL;
1975 case FMul: return ISD::FMUL;
1976 case UDiv: return ISD::UDIV;
1977 case SDiv: return ISD::SDIV;
1978 case FDiv: return ISD::FDIV;
1979 case URem: return ISD::UREM;
1980 case SRem: return ISD::SREM;
1981 case FRem: return ISD::FREM;
1982 case Shl: return ISD::SHL;
1983 case LShr: return ISD::SRL;
1984 case AShr: return ISD::SRA;
1985 case And: return ISD::AND;
1986 case Or: return ISD::OR;
1987 case Xor: return ISD::XOR;
1988 case Alloca: return 0;
1989 case Load: return ISD::LOAD;
1990 case Store: return ISD::STORE;
1991 case GetElementPtr: return 0;
1992 case Fence: return 0;
1993 case AtomicCmpXchg: return 0;
1994 case AtomicRMW: return 0;
1995 case Trunc: return ISD::TRUNCATE;
1996 case ZExt: return ISD::ZERO_EXTEND;
1997 case SExt: return ISD::SIGN_EXTEND;
1998 case FPToUI: return ISD::FP_TO_UINT;
1999 case FPToSI: return ISD::FP_TO_SINT;
2000 case UIToFP: return ISD::UINT_TO_FP;
2001 case SIToFP: return ISD::SINT_TO_FP;
2002 case FPTrunc: return ISD::FP_ROUND;
2003 case FPExt: return ISD::FP_EXTEND;
2004 case PtrToAddr: return ISD::BITCAST;
2005 case PtrToInt: return ISD::BITCAST;
2006 case IntToPtr: return ISD::BITCAST;
2007 case BitCast: return ISD::BITCAST;
2008 case AddrSpaceCast: return ISD::ADDRSPACECAST;
2009 case ICmp: return ISD::SETCC;
2010 case FCmp: return ISD::SETCC;
2011 case PHI: return 0;
2012 case Call: return 0;
2013 case Select: return ISD::SELECT;
2014 case UserOp1: return 0;
2015 case UserOp2: return 0;
2016 case VAArg: return 0;
2017 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
2018 case InsertElement: return ISD::INSERT_VECTOR_ELT;
2019 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
2020 case ExtractValue: return ISD::MERGE_VALUES;
2021 case InsertValue: return ISD::MERGE_VALUES;
2022 case LandingPad: return 0;
2023 case Freeze: return ISD::FREEZE;
2024 }
2025
2026 llvm_unreachable("Unknown instruction type encountered!");
2027}
2028
2029int TargetLoweringBase::IntrinsicIDToISD(Intrinsic::ID ID) const {
2030 switch (ID) {
2031 case Intrinsic::acos:
2032 return ISD::FACOS;
2033 case Intrinsic::asin:
2034 return ISD::FASIN;
2035 case Intrinsic::atan:
2036 return ISD::FATAN;
2037 case Intrinsic::cos:
2038 return ISD::FCOS;
2039 case Intrinsic::cosh:
2040 return ISD::FCOSH;
2041 case Intrinsic::exp:
2042 return ISD::FEXP;
2043 case Intrinsic::exp2:
2044 return ISD::FEXP2;
2045 case Intrinsic::exp10:
2046 return ISD::FEXP10;
2047 case Intrinsic::log:
2048 return ISD::FLOG;
2049 case Intrinsic::log2:
2050 return ISD::FLOG2;
2051 case Intrinsic::log10:
2052 return ISD::FLOG10;
2053 case Intrinsic::modf:
2054 return ISD::FMODF;
2055 case Intrinsic::sin:
2056 return ISD::FSIN;
2057 case Intrinsic::sincos:
2058 return ISD::FSINCOS;
2059 case Intrinsic::sincospi:
2060 return ISD::FSINCOSPI;
2061 case Intrinsic::sinh:
2062 return ISD::FSINH;
2063 case Intrinsic::tan:
2064 return ISD::FTAN;
2065 case Intrinsic::tanh:
2066 return ISD::FTANH;
2067 default:
2068 return ISD::DELETED_NODE;
2069 }
2070}
2071
2072Value *
2073TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilderBase &IRB,
2074 bool UseTLS) const {
2075 // compiler-rt provides a variable with a magic name. Targets that do not
2076 // link with compiler-rt may also provide such a variable.
2077 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2078
2079 RTLIB::LibcallImpl UnsafeStackPtrImpl =
2080 Libcalls.getLibcallImpl(Call: RTLIB::SAFESTACK_UNSAFE_STACK_PTR);
2081 if (UnsafeStackPtrImpl == RTLIB::Unsupported)
2082 return nullptr;
2083
2084 StringRef UnsafeStackPtrVar =
2085 RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: UnsafeStackPtrImpl);
2086 auto UnsafeStackPtr =
2087 dyn_cast_or_null<GlobalVariable>(Val: M->getNamedValue(Name: UnsafeStackPtrVar));
2088
2089 const DataLayout &DL = M->getDataLayout();
2090 PointerType *StackPtrTy = DL.getAllocaPtrType(Ctx&: M->getContext());
2091
2092 if (!UnsafeStackPtr) {
2093 auto TLSModel = UseTLS ?
2094 GlobalValue::InitialExecTLSModel :
2095 GlobalValue::NotThreadLocal;
2096 // The global variable is not defined yet, define it ourselves.
2097 // We use the initial-exec TLS model because we do not support the
2098 // variable living anywhere other than in the main executable.
2099 UnsafeStackPtr = new GlobalVariable(
2100 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
2101 UnsafeStackPtrVar, nullptr, TLSModel);
2102 } else {
2103 // The variable exists, check its type and attributes.
2104 //
2105 // FIXME: Move to IR verifier.
2106 if (UnsafeStackPtr->getValueType() != StackPtrTy)
2107 report_fatal_error(reason: Twine(UnsafeStackPtrVar) + " must have void* type");
2108 if (UseTLS != UnsafeStackPtr->isThreadLocal())
2109 report_fatal_error(reason: Twine(UnsafeStackPtrVar) + " must " +
2110 (UseTLS ? "" : "not ") + "be thread-local");
2111 }
2112 return UnsafeStackPtr;
2113}
2114
2115Value *TargetLoweringBase::getSafeStackPointerLocation(
2116 IRBuilderBase &IRB, const LibcallLoweringInfo &Libcalls) const {
2117 RTLIB::LibcallImpl SafestackPointerAddressImpl =
2118 Libcalls.getLibcallImpl(Call: RTLIB::SAFESTACK_POINTER_ADDRESS);
2119 if (SafestackPointerAddressImpl == RTLIB::Unsupported)
2120 return getDefaultSafeStackPointerLocation(IRB, UseTLS: true);
2121
2122 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2123 auto *PtrTy = PointerType::getUnqual(C&: M->getContext());
2124
2125 // Android provides a libc function to retrieve the address of the current
2126 // thread's unsafe stack pointer.
2127 FunctionCallee Fn =
2128 M->getOrInsertFunction(Name: RTLIB::RuntimeLibcallsInfo::getLibcallImplName(
2129 CallImpl: SafestackPointerAddressImpl),
2130 RetTy: PtrTy);
2131 return IRB.CreateCall(Callee: Fn);
2132}
2133
2134//===----------------------------------------------------------------------===//
2135// Loop Strength Reduction hooks
2136//===----------------------------------------------------------------------===//
2137
2138/// isLegalAddressingMode - Return true if the addressing mode represented
2139/// by AM is legal for this target, for a load/store of the specified type.
2140bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
2141 const AddrMode &AM, Type *Ty,
2142 unsigned AS, Instruction *I) const {
2143 // The default implementation of this implements a conservative RISCy, r+r and
2144 // r+i addr mode.
2145
2146 // Scalable offsets not supported
2147 if (AM.ScalableOffset)
2148 return false;
2149
2150 // Allows a sign-extended 16-bit immediate field.
2151 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2152 return false;
2153
2154 // No global is ever allowed as a base.
2155 if (AM.BaseGV)
2156 return false;
2157
2158 // Only support r+r,
2159 switch (AM.Scale) {
2160 case 0: // "r+i" or just "i", depending on HasBaseReg.
2161 break;
2162 case 1:
2163 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2164 return false;
2165 // Otherwise we have r+r or r+i.
2166 break;
2167 case 2:
2168 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2169 return false;
2170 // Allow 2*r as r+r.
2171 break;
2172 default: // Don't allow n * r
2173 return false;
2174 }
2175
2176 return true;
2177}
2178
2179//===----------------------------------------------------------------------===//
2180// Stack Protector
2181//===----------------------------------------------------------------------===//
2182
2183// For OpenBSD return its special guard variable. Otherwise return nullptr,
2184// so that SelectionDAG handle SSP.
2185Value *
2186TargetLoweringBase::getIRStackGuard(IRBuilderBase &IRB,
2187 const LibcallLoweringInfo &Libcalls) const {
2188 RTLIB::LibcallImpl GuardLocalImpl =
2189 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2190 if (GuardLocalImpl != RTLIB::impl___guard_local)
2191 return nullptr;
2192
2193 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
2194 const DataLayout &DL = M.getDataLayout();
2195 PointerType *PtrTy =
2196 PointerType::get(C&: M.getContext(), AddressSpace: DL.getDefaultGlobalsAddressSpace());
2197 GlobalVariable *G =
2198 M.getOrInsertGlobal(Name: getLibcallImplName(Call: GuardLocalImpl), Ty: PtrTy);
2199 G->setVisibility(GlobalValue::HiddenVisibility);
2200 return G;
2201}
2202
2203// Currently only support "standard" __stack_chk_guard.
2204// TODO: add LOAD_STACK_GUARD support.
2205void TargetLoweringBase::insertSSPDeclarations(
2206 Module &M, const LibcallLoweringInfo &Libcalls) const {
2207 RTLIB::LibcallImpl StackGuardImpl =
2208 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2209 if (StackGuardImpl == RTLIB::Unsupported)
2210 return;
2211
2212 StringRef StackGuardVarName = getLibcallImplName(Call: StackGuardImpl);
2213 M.getOrInsertGlobal(
2214 Name: StackGuardVarName, Ty: PointerType::getUnqual(C&: M.getContext()), CreateGlobalCallback: [=, &M]() {
2215 auto *GV = new GlobalVariable(M, PointerType::getUnqual(C&: M.getContext()),
2216 false, GlobalVariable::ExternalLinkage,
2217 nullptr, StackGuardVarName);
2218
2219 // FreeBSD has "__stack_chk_guard" defined externally on libc.so
2220 if (M.getDirectAccessExternalData() &&
2221 !TM.getTargetTriple().isOSCygMing() &&
2222 !(TM.getTargetTriple().isPPC64() &&
2223 TM.getTargetTriple().isOSFreeBSD()) &&
2224 (!TM.getTargetTriple().isOSDarwin() ||
2225 TM.getRelocationModel() == Reloc::Static))
2226 GV->setDSOLocal(true);
2227
2228 return GV;
2229 });
2230}
2231
2232// Currently only support "standard" __stack_chk_guard.
2233// TODO: add LOAD_STACK_GUARD support.
2234Value *TargetLoweringBase::getSDagStackGuard(
2235 const Module &M, const LibcallLoweringInfo &Libcalls) const {
2236 RTLIB::LibcallImpl GuardVarImpl =
2237 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2238 if (GuardVarImpl == RTLIB::Unsupported)
2239 return nullptr;
2240 return M.getNamedValue(Name: getLibcallImplName(Call: GuardVarImpl));
2241}
2242
2243Function *TargetLoweringBase::getSSPStackGuardCheck(
2244 const Module &M, const LibcallLoweringInfo &Libcalls) const {
2245 // MSVC CRT has a function to validate security cookie.
2246 RTLIB::LibcallImpl SecurityCheckCookieLibcall =
2247 Libcalls.getLibcallImpl(Call: RTLIB::SECURITY_CHECK_COOKIE);
2248 if (SecurityCheckCookieLibcall != RTLIB::Unsupported)
2249 return M.getFunction(Name: getLibcallImplName(Call: SecurityCheckCookieLibcall));
2250 return nullptr;
2251}
2252
2253unsigned TargetLoweringBase::getMinimumJumpTableEntries() const {
2254 return MinimumJumpTableEntries;
2255}
2256
2257void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) {
2258 MinimumJumpTableEntries = Val;
2259}
2260
2261unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
2262 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
2263}
2264
2265unsigned TargetLoweringBase::getMaximumJumpTableSize() const {
2266 return MaximumJumpTableSize;
2267}
2268
2269void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {
2270 MaximumJumpTableSize = Val;
2271}
2272
2273bool TargetLoweringBase::isJumpTableRelative() const {
2274 return getTargetMachine().isPositionIndependent();
2275}
2276
2277unsigned TargetLoweringBase::getMinimumBitTestCmps() const {
2278 return MinimumBitTestCmps;
2279}
2280
2281void TargetLoweringBase::setMinimumBitTestCmps(unsigned Val) {
2282 MinimumBitTestCmps = Val;
2283}
2284
2285Align TargetLoweringBase::getPrefLoopAlignment(MachineLoop *ML) const {
2286 if (TM.Options.LoopAlignment)
2287 return Align(TM.Options.LoopAlignment);
2288 return PrefLoopAlignment;
2289}
2290
2291unsigned TargetLoweringBase::getMaxPermittedBytesForAlignment(
2292 MachineBasicBlock *MBB) const {
2293 return MaxBytesForAlignment;
2294}
2295
2296//===----------------------------------------------------------------------===//
2297// Reciprocal Estimates
2298//===----------------------------------------------------------------------===//
2299
2300/// Get the reciprocal estimate attribute string for a function that will
2301/// override the target defaults.
2302static StringRef getRecipEstimateForFunc(MachineFunction &MF) {
2303 const Function &F = MF.getFunction();
2304 return F.getFnAttribute(Kind: "reciprocal-estimates").getValueAsString();
2305}
2306
2307/// Construct a string for the given reciprocal operation of the given type.
2308/// This string should match the corresponding option to the front-end's
2309/// "-mrecip" flag assuming those strings have been passed through in an
2310/// attribute string. For example, "vec-divf" for a division of a vXf32.
2311static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2312 std::string Name = VT.isVector() ? "vec-" : "";
2313
2314 Name += IsSqrt ? "sqrt" : "div";
2315
2316 // TODO: Handle other float types?
2317 if (VT.getScalarType() == MVT::f64) {
2318 Name += "d";
2319 } else if (VT.getScalarType() == MVT::f16) {
2320 Name += "h";
2321 } else {
2322 assert(VT.getScalarType() == MVT::f32 &&
2323 "Unexpected FP type for reciprocal estimate");
2324 Name += "f";
2325 }
2326
2327 return Name;
2328}
2329
2330/// Return the character position and value (a single numeric character) of a
2331/// customized refinement operation in the input string if it exists. Return
2332/// false if there is no customized refinement step count.
2333static bool parseRefinementStep(StringRef In, size_t &Position,
2334 uint8_t &Value) {
2335 const char RefStepToken = ':';
2336 Position = In.find(C: RefStepToken);
2337 if (Position == StringRef::npos)
2338 return false;
2339
2340 StringRef RefStepString = In.substr(Start: Position + 1);
2341 // Allow exactly one numeric character for the additional refinement
2342 // step parameter.
2343 if (RefStepString.size() == 1) {
2344 char RefStepChar = RefStepString[0];
2345 if (isDigit(C: RefStepChar)) {
2346 Value = RefStepChar - '0';
2347 return true;
2348 }
2349 }
2350 report_fatal_error(reason: "Invalid refinement step for -recip.");
2351}
2352
2353/// For the input attribute string, return one of the ReciprocalEstimate enum
2354/// status values (enabled, disabled, or not specified) for this operation on
2355/// the specified data type.
2356static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2357 if (Override.empty())
2358 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2359
2360 SmallVector<StringRef, 4> OverrideVector;
2361 Override.split(A&: OverrideVector, Separator: ',');
2362 unsigned NumArgs = OverrideVector.size();
2363
2364 // Check if "all", "none", or "default" was specified.
2365 if (NumArgs == 1) {
2366 // Look for an optional setting of the number of refinement steps needed
2367 // for this type of reciprocal operation.
2368 size_t RefPos;
2369 uint8_t RefSteps;
2370 if (parseRefinementStep(In: Override, Position&: RefPos, Value&: RefSteps)) {
2371 // Split the string for further processing.
2372 Override = Override.substr(Start: 0, N: RefPos);
2373 }
2374
2375 // All reciprocal types are enabled.
2376 if (Override == "all")
2377 return TargetLoweringBase::ReciprocalEstimate::Enabled;
2378
2379 // All reciprocal types are disabled.
2380 if (Override == "none")
2381 return TargetLoweringBase::ReciprocalEstimate::Disabled;
2382
2383 // Target defaults for enablement are used.
2384 if (Override == "default")
2385 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2386 }
2387
2388 // The attribute string may omit the size suffix ('f'/'d').
2389 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2390 std::string VTNameNoSize = VTName;
2391 VTNameNoSize.pop_back();
2392 static const char DisabledPrefix = '!';
2393
2394 for (StringRef RecipType : OverrideVector) {
2395 size_t RefPos;
2396 uint8_t RefSteps;
2397 if (parseRefinementStep(In: RecipType, Position&: RefPos, Value&: RefSteps))
2398 RecipType = RecipType.substr(Start: 0, N: RefPos);
2399
2400 // Ignore the disablement token for string matching.
2401 bool IsDisabled = RecipType[0] == DisabledPrefix;
2402 if (IsDisabled)
2403 RecipType = RecipType.substr(Start: 1);
2404
2405 if (RecipType == VTName || RecipType == VTNameNoSize)
2406 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
2407 : TargetLoweringBase::ReciprocalEstimate::Enabled;
2408 }
2409
2410 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2411}
2412
2413/// For the input attribute string, return the customized refinement step count
2414/// for this operation on the specified data type. If the step count does not
2415/// exist, return the ReciprocalEstimate enum value for unspecified.
2416static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2417 if (Override.empty())
2418 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2419
2420 SmallVector<StringRef, 4> OverrideVector;
2421 Override.split(A&: OverrideVector, Separator: ',');
2422 unsigned NumArgs = OverrideVector.size();
2423
2424 // Check if "all", "default", or "none" was specified.
2425 if (NumArgs == 1) {
2426 // Look for an optional setting of the number of refinement steps needed
2427 // for this type of reciprocal operation.
2428 size_t RefPos;
2429 uint8_t RefSteps;
2430 if (!parseRefinementStep(In: Override, Position&: RefPos, Value&: RefSteps))
2431 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2432
2433 // Split the string for further processing.
2434 Override = Override.substr(Start: 0, N: RefPos);
2435 assert(Override != "none" &&
2436 "Disabled reciprocals, but specifed refinement steps?");
2437
2438 // If this is a general override, return the specified number of steps.
2439 if (Override == "all" || Override == "default")
2440 return RefSteps;
2441 }
2442
2443 // The attribute string may omit the size suffix ('f'/'d').
2444 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2445 std::string VTNameNoSize = VTName;
2446 VTNameNoSize.pop_back();
2447
2448 for (StringRef RecipType : OverrideVector) {
2449 size_t RefPos;
2450 uint8_t RefSteps;
2451 if (!parseRefinementStep(In: RecipType, Position&: RefPos, Value&: RefSteps))
2452 continue;
2453
2454 RecipType = RecipType.substr(Start: 0, N: RefPos);
2455 if (RecipType == VTName || RecipType == VTNameNoSize)
2456 return RefSteps;
2457 }
2458
2459 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2460}
2461
2462int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,
2463 MachineFunction &MF) const {
2464 return getOpEnabled(IsSqrt: true, VT, Override: getRecipEstimateForFunc(MF));
2465}
2466
2467int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,
2468 MachineFunction &MF) const {
2469 return getOpEnabled(IsSqrt: false, VT, Override: getRecipEstimateForFunc(MF));
2470}
2471
2472int TargetLoweringBase::getSqrtRefinementSteps(EVT VT,
2473 MachineFunction &MF) const {
2474 return getOpRefinementSteps(IsSqrt: true, VT, Override: getRecipEstimateForFunc(MF));
2475}
2476
2477int TargetLoweringBase::getDivRefinementSteps(EVT VT,
2478 MachineFunction &MF) const {
2479 return getOpRefinementSteps(IsSqrt: false, VT, Override: getRecipEstimateForFunc(MF));
2480}
2481
2482bool TargetLoweringBase::isLoadBitCastBeneficial(
2483 EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG,
2484 const MachineMemOperand &MMO) const {
2485 // Single-element vectors are scalarized, so we should generally avoid having
2486 // any memory operations on such types, as they would get scalarized too.
2487 if (LoadVT.isFixedLengthVector() && BitcastVT.isFixedLengthVector() &&
2488 BitcastVT.getVectorNumElements() == 1)
2489 return false;
2490
2491 // Don't do if we could do an indexed load on the original type, but not on
2492 // the new one.
2493 if (!LoadVT.isSimple() || !BitcastVT.isSimple())
2494 return true;
2495
2496 MVT LoadMVT = LoadVT.getSimpleVT();
2497
2498 // Don't bother doing this if it's just going to be promoted again later, as
2499 // doing so might interfere with other combines.
2500 if (getOperationAction(Op: ISD::LOAD, VT: LoadMVT) == Promote &&
2501 getTypeToPromoteTo(Op: ISD::LOAD, VT: LoadMVT) == BitcastVT.getSimpleVT())
2502 return false;
2503
2504 unsigned Fast = 0;
2505 return allowsMemoryAccess(Context&: *DAG.getContext(), DL: DAG.getDataLayout(), VT: BitcastVT,
2506 MMO, Fast: &Fast) &&
2507 Fast;
2508}
2509
2510void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
2511 MF.getRegInfo().freezeReservedRegs();
2512}
2513
2514MachineMemOperand::Flags TargetLoweringBase::getLoadMemOperandFlags(
2515 const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC,
2516 const TargetLibraryInfo *LibInfo, CodeGenOptLevel OptLevel) const {
2517 MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad;
2518 if (LI.isVolatile())
2519 Flags |= MachineMemOperand::MOVolatile;
2520
2521 if (LI.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2522 Flags |= MachineMemOperand::MONonTemporal;
2523
2524 if (LI.hasMetadata(KindID: LLVMContext::MD_invariant_load))
2525 Flags |= MachineMemOperand::MOInvariant;
2526
2527 // Dereferenceability analysis is expensive, skip at O0.
2528 if (OptLevel != CodeGenOptLevel::None &&
2529 isDereferenceableAndAlignedPointer(
2530 V: LI.getPointerOperand(), Ty: LI.getType(), Alignment: LI.getAlign(),
2531 Q: SimplifyQuery(DL, LibInfo, /*DT=*/nullptr, AC, &LI)))
2532 Flags |= MachineMemOperand::MODereferenceable;
2533
2534 Flags |= getTargetMMOFlags(I: LI);
2535 return Flags;
2536}
2537
2538MachineMemOperand::Flags
2539TargetLoweringBase::getStoreMemOperandFlags(const StoreInst &SI,
2540 const DataLayout &DL) const {
2541 MachineMemOperand::Flags Flags = MachineMemOperand::MOStore;
2542
2543 if (SI.isVolatile())
2544 Flags |= MachineMemOperand::MOVolatile;
2545
2546 if (SI.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2547 Flags |= MachineMemOperand::MONonTemporal;
2548
2549 // FIXME: Not preserving dereferenceable
2550 Flags |= getTargetMMOFlags(I: SI);
2551 return Flags;
2552}
2553
2554MachineMemOperand::Flags
2555TargetLoweringBase::getAtomicMemOperandFlags(const Instruction &AI,
2556 const DataLayout &DL) const {
2557 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
2558
2559 if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(Val: &AI)) {
2560 if (RMW->isVolatile())
2561 Flags |= MachineMemOperand::MOVolatile;
2562 } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(Val: &AI)) {
2563 if (CmpX->isVolatile())
2564 Flags |= MachineMemOperand::MOVolatile;
2565 } else
2566 llvm_unreachable("not an atomic instruction");
2567
2568 // FIXME: Not preserving dereferenceable
2569 Flags |= getTargetMMOFlags(I: AI);
2570 return Flags;
2571}
2572
2573MachineMemOperand::Flags TargetLoweringBase::getVPIntrinsicMemOperandFlags(
2574 const VPIntrinsic &VPIntrin) const {
2575 MachineMemOperand::Flags Flags = MachineMemOperand::MONone;
2576 Intrinsic::ID IntrinID = VPIntrin.getIntrinsicID();
2577
2578 switch (IntrinID) {
2579 default:
2580 llvm_unreachable("unexpected intrinsic. Existing code may be appropriate "
2581 "for it, but support must be explicitly enabled");
2582 case Intrinsic::vp_load:
2583 case Intrinsic::vp_gather:
2584 case Intrinsic::experimental_vp_strided_load:
2585 Flags = MachineMemOperand::MOLoad;
2586 break;
2587 case Intrinsic::vp_store:
2588 case Intrinsic::vp_scatter:
2589 case Intrinsic::experimental_vp_strided_store:
2590 Flags = MachineMemOperand::MOStore;
2591 break;
2592 }
2593
2594 if (VPIntrin.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2595 Flags |= MachineMemOperand::MONonTemporal;
2596
2597 Flags |= getTargetMMOFlags(I: VPIntrin);
2598 return Flags;
2599}
2600
2601Instruction *TargetLoweringBase::emitLeadingFence(IRBuilderBase &Builder,
2602 Instruction *Inst,
2603 AtomicOrdering Ord) const {
2604 if (isReleaseOrStronger(AO: Ord) && Inst->hasAtomicStore())
2605 return Builder.CreateFence(Ordering: Ord);
2606 else
2607 return nullptr;
2608}
2609
2610Instruction *TargetLoweringBase::emitTrailingFence(IRBuilderBase &Builder,
2611 Instruction *Inst,
2612 AtomicOrdering Ord) const {
2613 if (isAcquireOrStronger(AO: Ord))
2614 return Builder.CreateFence(Ordering: Ord);
2615 else
2616 return nullptr;
2617}
2618
2619//===----------------------------------------------------------------------===//
2620// GlobalISel Hooks
2621//===----------------------------------------------------------------------===//
2622
2623bool TargetLoweringBase::shouldLocalize(const MachineInstr &MI,
2624 const TargetTransformInfo *TTI) const {
2625 auto &MF = *MI.getMF();
2626 auto &MRI = MF.getRegInfo();
2627 // Assuming a spill and reload of a value has a cost of 1 instruction each,
2628 // this helper function computes the maximum number of uses we should consider
2629 // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2630 // break even in terms of code size when the original MI has 2 users vs
2631 // choosing to potentially spill. Any more than 2 users we we have a net code
2632 // size increase. This doesn't take into account register pressure though.
2633 auto maxUses = [](unsigned RematCost) {
2634 // A cost of 1 means remats are basically free.
2635 if (RematCost == 1)
2636 return std::numeric_limits<unsigned>::max();
2637 if (RematCost == 2)
2638 return 2U;
2639
2640 // Remat is too expensive, only sink if there's one user.
2641 if (RematCost > 2)
2642 return 1U;
2643 llvm_unreachable("Unexpected remat cost");
2644 };
2645
2646 switch (MI.getOpcode()) {
2647 default:
2648 return false;
2649 // Constants-like instructions should be close to their users.
2650 // We don't want long live-ranges for them.
2651 case TargetOpcode::G_CONSTANT:
2652 case TargetOpcode::G_FCONSTANT:
2653 case TargetOpcode::G_FRAME_INDEX:
2654 case TargetOpcode::G_INTTOPTR:
2655 return true;
2656 case TargetOpcode::G_GLOBAL_VALUE: {
2657 unsigned RematCost = TTI->getGISelRematGlobalCost();
2658 Register Reg = MI.getOperand(i: 0).getReg();
2659 unsigned MaxUses = maxUses(RematCost);
2660 if (MaxUses == UINT_MAX)
2661 return true; // Remats are "free" so always localize.
2662 return MRI.hasAtMostUserInstrs(Reg, MaxUsers: MaxUses);
2663 }
2664 }
2665}
2666