1//===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the TargetLoweringBase class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/ADT/BitVector.h"
14#include "llvm/ADT/STLExtras.h"
15#include "llvm/ADT/SmallVector.h"
16#include "llvm/ADT/StringExtras.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/Twine.h"
19#include "llvm/Analysis/Loads.h"
20#include "llvm/Analysis/TargetTransformInfo.h"
21#include "llvm/CodeGen/Analysis.h"
22#include "llvm/CodeGen/ISDOpcodes.h"
23#include "llvm/CodeGen/MachineBasicBlock.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineMemOperand.h"
29#include "llvm/CodeGen/MachineOperand.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RuntimeLibcallUtil.h"
32#include "llvm/CodeGen/StackMaps.h"
33#include "llvm/CodeGen/TargetLowering.h"
34#include "llvm/CodeGen/TargetOpcodes.h"
35#include "llvm/CodeGen/TargetRegisterInfo.h"
36#include "llvm/CodeGen/ValueTypes.h"
37#include "llvm/CodeGenTypes/MachineValueType.h"
38#include "llvm/IR/Attributes.h"
39#include "llvm/IR/CallingConv.h"
40#include "llvm/IR/DataLayout.h"
41#include "llvm/IR/DerivedTypes.h"
42#include "llvm/IR/Function.h"
43#include "llvm/IR/GlobalValue.h"
44#include "llvm/IR/GlobalVariable.h"
45#include "llvm/IR/IRBuilder.h"
46#include "llvm/IR/Module.h"
47#include "llvm/IR/Type.h"
48#include "llvm/Support/Casting.h"
49#include "llvm/Support/CommandLine.h"
50#include "llvm/Support/Compiler.h"
51#include "llvm/Support/ErrorHandling.h"
52#include "llvm/Support/MathExtras.h"
53#include "llvm/Target/TargetMachine.h"
54#include "llvm/Target/TargetOptions.h"
55#include "llvm/TargetParser/Triple.h"
56#include "llvm/Transforms/Utils/SizeOpts.h"
57#include <algorithm>
58#include <cassert>
59#include <cstdint>
60#include <cstring>
61#include <string>
62#include <tuple>
63#include <utility>
64
65using namespace llvm;
66
67static cl::opt<bool> JumpIsExpensiveOverride(
68 "jump-is-expensive", cl::init(Val: false),
69 cl::desc("Do not create extra branches to split comparison logic."),
70 cl::Hidden);
71
72static cl::opt<unsigned> MinimumJumpTableEntries
73 ("min-jump-table-entries", cl::init(Val: 4), cl::Hidden,
74 cl::desc("Set minimum number of entries to use a jump table."));
75
76static cl::opt<unsigned> MaximumJumpTableSize
77 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
78 cl::desc("Set maximum size of jump tables."));
79
80/// Minimum jump table density for normal functions.
81static cl::opt<unsigned>
82 JumpTableDensity("jump-table-density", cl::init(Val: 10), cl::Hidden,
83 cl::desc("Minimum density for building a jump table in "
84 "a normal function"));
85
86/// Minimum jump table density for -Os or -Oz functions.
87static cl::opt<unsigned> OptsizeJumpTableDensity(
88 "optsize-jump-table-density", cl::init(Val: 40), cl::Hidden,
89 cl::desc("Minimum density for building a jump table in "
90 "an optsize function"));
91
92static cl::opt<unsigned> MinimumBitTestCmpsOverride(
93 "min-bit-test-cmps", cl::init(Val: 2), cl::Hidden,
94 cl::desc("Set minimum of largest number of comparisons "
95 "to use bit test for switch."));
96
97static cl::opt<unsigned> MaxStoresPerMemsetOverride(
98 "max-store-memset", cl::init(Val: 0), cl::Hidden,
99 cl::desc("Override target's MaxStoresPerMemset and "
100 "MaxStoresPerMemsetOptSize. "
101 "Set to 0 to use the target default."));
102
103static cl::opt<unsigned> MaxStoresPerMemcpyOverride(
104 "max-store-memcpy", cl::init(Val: 0), cl::Hidden,
105 cl::desc("Override target's MaxStoresPerMemcpy and "
106 "MaxStoresPerMemcpyOptSize. "
107 "Set to 0 to use the target default."));
108
109static cl::opt<unsigned> MaxStoresPerMemmoveOverride(
110 "max-store-memmove", cl::init(Val: 0), cl::Hidden,
111 cl::desc("Override target's MaxStoresPerMemmove and "
112 "MaxStoresPerMemmoveOptSize. "
113 "Set to 0 to use the target default."));
114
115// FIXME: This option is only to test if the strict fp operation processed
116// correctly by preventing mutating strict fp operation to normal fp operation
117// during development. When the backend supports strict float operation, this
118// option will be meaningless.
119static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
120 cl::desc("Don't mutate strict-float node to a legalize node"),
121 cl::init(Val: false), cl::Hidden);
122
123LLVM_ABI RTLIB::Libcall RTLIB::getSHL(EVT VT) {
124 if (VT == MVT::i16)
125 return RTLIB::SHL_I16;
126 if (VT == MVT::i32)
127 return RTLIB::SHL_I32;
128 if (VT == MVT::i64)
129 return RTLIB::SHL_I64;
130 if (VT == MVT::i128)
131 return RTLIB::SHL_I128;
132
133 return RTLIB::UNKNOWN_LIBCALL;
134}
135
136LLVM_ABI RTLIB::Libcall RTLIB::getSRL(EVT VT) {
137 if (VT == MVT::i16)
138 return RTLIB::SRL_I16;
139 if (VT == MVT::i32)
140 return RTLIB::SRL_I32;
141 if (VT == MVT::i64)
142 return RTLIB::SRL_I64;
143 if (VT == MVT::i128)
144 return RTLIB::SRL_I128;
145
146 return RTLIB::UNKNOWN_LIBCALL;
147}
148
149LLVM_ABI RTLIB::Libcall RTLIB::getSRA(EVT VT) {
150 if (VT == MVT::i16)
151 return RTLIB::SRA_I16;
152 if (VT == MVT::i32)
153 return RTLIB::SRA_I32;
154 if (VT == MVT::i64)
155 return RTLIB::SRA_I64;
156 if (VT == MVT::i128)
157 return RTLIB::SRA_I128;
158
159 return RTLIB::UNKNOWN_LIBCALL;
160}
161
162LLVM_ABI RTLIB::Libcall RTLIB::getMUL(EVT VT) {
163 if (VT == MVT::i16)
164 return RTLIB::MUL_I16;
165 if (VT == MVT::i32)
166 return RTLIB::MUL_I32;
167 if (VT == MVT::i64)
168 return RTLIB::MUL_I64;
169 if (VT == MVT::i128)
170 return RTLIB::MUL_I128;
171 return RTLIB::UNKNOWN_LIBCALL;
172}
173
174LLVM_ABI RTLIB::Libcall RTLIB::getMULO(EVT VT) {
175 if (VT == MVT::i32)
176 return RTLIB::MULO_I32;
177 if (VT == MVT::i64)
178 return RTLIB::MULO_I64;
179 if (VT == MVT::i128)
180 return RTLIB::MULO_I128;
181 return RTLIB::UNKNOWN_LIBCALL;
182}
183
184LLVM_ABI RTLIB::Libcall RTLIB::getSDIV(EVT VT) {
185 if (VT == MVT::i16)
186 return RTLIB::SDIV_I16;
187 if (VT == MVT::i32)
188 return RTLIB::SDIV_I32;
189 if (VT == MVT::i64)
190 return RTLIB::SDIV_I64;
191 if (VT == MVT::i128)
192 return RTLIB::SDIV_I128;
193 return RTLIB::UNKNOWN_LIBCALL;
194}
195
196LLVM_ABI RTLIB::Libcall RTLIB::getUDIV(EVT VT) {
197 if (VT == MVT::i16)
198 return RTLIB::UDIV_I16;
199 if (VT == MVT::i32)
200 return RTLIB::UDIV_I32;
201 if (VT == MVT::i64)
202 return RTLIB::UDIV_I64;
203 if (VT == MVT::i128)
204 return RTLIB::UDIV_I128;
205 return RTLIB::UNKNOWN_LIBCALL;
206}
207
208LLVM_ABI RTLIB::Libcall RTLIB::getSREM(EVT VT) {
209 if (VT == MVT::i16)
210 return RTLIB::SREM_I16;
211 if (VT == MVT::i32)
212 return RTLIB::SREM_I32;
213 if (VT == MVT::i64)
214 return RTLIB::SREM_I64;
215 if (VT == MVT::i128)
216 return RTLIB::SREM_I128;
217 return RTLIB::UNKNOWN_LIBCALL;
218}
219
220LLVM_ABI RTLIB::Libcall RTLIB::getUREM(EVT VT) {
221 if (VT == MVT::i16)
222 return RTLIB::UREM_I16;
223 if (VT == MVT::i32)
224 return RTLIB::UREM_I32;
225 if (VT == MVT::i64)
226 return RTLIB::UREM_I64;
227 if (VT == MVT::i128)
228 return RTLIB::UREM_I128;
229 return RTLIB::UNKNOWN_LIBCALL;
230}
231
232LLVM_ABI RTLIB::Libcall RTLIB::getCTPOP(EVT VT) {
233 if (VT == MVT::i32)
234 return RTLIB::CTPOP_I32;
235 if (VT == MVT::i64)
236 return RTLIB::CTPOP_I64;
237 if (VT == MVT::i128)
238 return RTLIB::CTPOP_I128;
239 return RTLIB::UNKNOWN_LIBCALL;
240}
241
242/// GetFPLibCall - Helper to return the right libcall for the given floating
243/// point type, or UNKNOWN_LIBCALL if there is none.
244RTLIB::Libcall RTLIB::getFPLibCall(EVT VT,
245 RTLIB::Libcall Call_F32,
246 RTLIB::Libcall Call_F64,
247 RTLIB::Libcall Call_F80,
248 RTLIB::Libcall Call_F128,
249 RTLIB::Libcall Call_PPCF128) {
250 return
251 VT == MVT::f32 ? Call_F32 :
252 VT == MVT::f64 ? Call_F64 :
253 VT == MVT::f80 ? Call_F80 :
254 VT == MVT::f128 ? Call_F128 :
255 VT == MVT::ppcf128 ? Call_PPCF128 :
256 RTLIB::UNKNOWN_LIBCALL;
257}
258
259/// getFPEXT - Return the FPEXT_*_* value for the given types, or
260/// UNKNOWN_LIBCALL if there is none.
261RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
262 if (OpVT == MVT::f16) {
263 if (RetVT == MVT::f32)
264 return FPEXT_F16_F32;
265 if (RetVT == MVT::f64)
266 return FPEXT_F16_F64;
267 if (RetVT == MVT::f80)
268 return FPEXT_F16_F80;
269 if (RetVT == MVT::f128)
270 return FPEXT_F16_F128;
271 } else if (OpVT == MVT::f32) {
272 if (RetVT == MVT::f64)
273 return FPEXT_F32_F64;
274 if (RetVT == MVT::f128)
275 return FPEXT_F32_F128;
276 if (RetVT == MVT::ppcf128)
277 return FPEXT_F32_PPCF128;
278 } else if (OpVT == MVT::f64) {
279 if (RetVT == MVT::f128)
280 return FPEXT_F64_F128;
281 else if (RetVT == MVT::ppcf128)
282 return FPEXT_F64_PPCF128;
283 } else if (OpVT == MVT::f80) {
284 if (RetVT == MVT::f128)
285 return FPEXT_F80_F128;
286 } else if (OpVT == MVT::bf16) {
287 if (RetVT == MVT::f32)
288 return FPEXT_BF16_F32;
289 }
290
291 return UNKNOWN_LIBCALL;
292}
293
294/// getFPROUND - Return the FPROUND_*_* value for the given types, or
295/// UNKNOWN_LIBCALL if there is none.
296RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
297 if (RetVT == MVT::f16) {
298 if (OpVT == MVT::f32)
299 return FPROUND_F32_F16;
300 if (OpVT == MVT::f64)
301 return FPROUND_F64_F16;
302 if (OpVT == MVT::f80)
303 return FPROUND_F80_F16;
304 if (OpVT == MVT::f128)
305 return FPROUND_F128_F16;
306 if (OpVT == MVT::ppcf128)
307 return FPROUND_PPCF128_F16;
308 } else if (RetVT == MVT::bf16) {
309 if (OpVT == MVT::f32)
310 return FPROUND_F32_BF16;
311 if (OpVT == MVT::f64)
312 return FPROUND_F64_BF16;
313 if (OpVT == MVT::f80)
314 return FPROUND_F80_BF16;
315 if (OpVT == MVT::f128)
316 return FPROUND_F128_BF16;
317 } else if (RetVT == MVT::f32) {
318 if (OpVT == MVT::f64)
319 return FPROUND_F64_F32;
320 if (OpVT == MVT::f80)
321 return FPROUND_F80_F32;
322 if (OpVT == MVT::f128)
323 return FPROUND_F128_F32;
324 if (OpVT == MVT::ppcf128)
325 return FPROUND_PPCF128_F32;
326 } else if (RetVT == MVT::f64) {
327 if (OpVT == MVT::f80)
328 return FPROUND_F80_F64;
329 if (OpVT == MVT::f128)
330 return FPROUND_F128_F64;
331 if (OpVT == MVT::ppcf128)
332 return FPROUND_PPCF128_F64;
333 } else if (RetVT == MVT::f80) {
334 if (OpVT == MVT::f128)
335 return FPROUND_F128_F80;
336 }
337
338 return UNKNOWN_LIBCALL;
339}
340
341/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
342/// UNKNOWN_LIBCALL if there is none.
343RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
344 if (OpVT == MVT::f16) {
345 if (RetVT == MVT::i32)
346 return FPTOSINT_F16_I32;
347 if (RetVT == MVT::i64)
348 return FPTOSINT_F16_I64;
349 if (RetVT == MVT::i128)
350 return FPTOSINT_F16_I128;
351 } else if (OpVT == MVT::f32) {
352 if (RetVT == MVT::i32)
353 return FPTOSINT_F32_I32;
354 if (RetVT == MVT::i64)
355 return FPTOSINT_F32_I64;
356 if (RetVT == MVT::i128)
357 return FPTOSINT_F32_I128;
358 } else if (OpVT == MVT::f64) {
359 if (RetVT == MVT::i32)
360 return FPTOSINT_F64_I32;
361 if (RetVT == MVT::i64)
362 return FPTOSINT_F64_I64;
363 if (RetVT == MVT::i128)
364 return FPTOSINT_F64_I128;
365 } else if (OpVT == MVT::f80) {
366 if (RetVT == MVT::i32)
367 return FPTOSINT_F80_I32;
368 if (RetVT == MVT::i64)
369 return FPTOSINT_F80_I64;
370 if (RetVT == MVT::i128)
371 return FPTOSINT_F80_I128;
372 } else if (OpVT == MVT::f128) {
373 if (RetVT == MVT::i32)
374 return FPTOSINT_F128_I32;
375 if (RetVT == MVT::i64)
376 return FPTOSINT_F128_I64;
377 if (RetVT == MVT::i128)
378 return FPTOSINT_F128_I128;
379 } else if (OpVT == MVT::ppcf128) {
380 if (RetVT == MVT::i32)
381 return FPTOSINT_PPCF128_I32;
382 if (RetVT == MVT::i64)
383 return FPTOSINT_PPCF128_I64;
384 if (RetVT == MVT::i128)
385 return FPTOSINT_PPCF128_I128;
386 }
387 return UNKNOWN_LIBCALL;
388}
389
390/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
391/// UNKNOWN_LIBCALL if there is none.
392RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
393 if (OpVT == MVT::f16) {
394 if (RetVT == MVT::i32)
395 return FPTOUINT_F16_I32;
396 if (RetVT == MVT::i64)
397 return FPTOUINT_F16_I64;
398 if (RetVT == MVT::i128)
399 return FPTOUINT_F16_I128;
400 } else if (OpVT == MVT::f32) {
401 if (RetVT == MVT::i32)
402 return FPTOUINT_F32_I32;
403 if (RetVT == MVT::i64)
404 return FPTOUINT_F32_I64;
405 if (RetVT == MVT::i128)
406 return FPTOUINT_F32_I128;
407 } else if (OpVT == MVT::f64) {
408 if (RetVT == MVT::i32)
409 return FPTOUINT_F64_I32;
410 if (RetVT == MVT::i64)
411 return FPTOUINT_F64_I64;
412 if (RetVT == MVT::i128)
413 return FPTOUINT_F64_I128;
414 } else if (OpVT == MVT::f80) {
415 if (RetVT == MVT::i32)
416 return FPTOUINT_F80_I32;
417 if (RetVT == MVT::i64)
418 return FPTOUINT_F80_I64;
419 if (RetVT == MVT::i128)
420 return FPTOUINT_F80_I128;
421 } else if (OpVT == MVT::f128) {
422 if (RetVT == MVT::i32)
423 return FPTOUINT_F128_I32;
424 if (RetVT == MVT::i64)
425 return FPTOUINT_F128_I64;
426 if (RetVT == MVT::i128)
427 return FPTOUINT_F128_I128;
428 } else if (OpVT == MVT::ppcf128) {
429 if (RetVT == MVT::i32)
430 return FPTOUINT_PPCF128_I32;
431 if (RetVT == MVT::i64)
432 return FPTOUINT_PPCF128_I64;
433 if (RetVT == MVT::i128)
434 return FPTOUINT_PPCF128_I128;
435 }
436 return UNKNOWN_LIBCALL;
437}
438
439/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
440/// UNKNOWN_LIBCALL if there is none.
441RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
442 if (OpVT == MVT::i32) {
443 if (RetVT == MVT::f16)
444 return SINTTOFP_I32_F16;
445 if (RetVT == MVT::f32)
446 return SINTTOFP_I32_F32;
447 if (RetVT == MVT::f64)
448 return SINTTOFP_I32_F64;
449 if (RetVT == MVT::f80)
450 return SINTTOFP_I32_F80;
451 if (RetVT == MVT::f128)
452 return SINTTOFP_I32_F128;
453 if (RetVT == MVT::ppcf128)
454 return SINTTOFP_I32_PPCF128;
455 } else if (OpVT == MVT::i64) {
456 if (RetVT == MVT::bf16)
457 return SINTTOFP_I64_BF16;
458 if (RetVT == MVT::f16)
459 return SINTTOFP_I64_F16;
460 if (RetVT == MVT::f32)
461 return SINTTOFP_I64_F32;
462 if (RetVT == MVT::f64)
463 return SINTTOFP_I64_F64;
464 if (RetVT == MVT::f80)
465 return SINTTOFP_I64_F80;
466 if (RetVT == MVT::f128)
467 return SINTTOFP_I64_F128;
468 if (RetVT == MVT::ppcf128)
469 return SINTTOFP_I64_PPCF128;
470 } else if (OpVT == MVT::i128) {
471 if (RetVT == MVT::f16)
472 return SINTTOFP_I128_F16;
473 if (RetVT == MVT::f32)
474 return SINTTOFP_I128_F32;
475 if (RetVT == MVT::f64)
476 return SINTTOFP_I128_F64;
477 if (RetVT == MVT::f80)
478 return SINTTOFP_I128_F80;
479 if (RetVT == MVT::f128)
480 return SINTTOFP_I128_F128;
481 if (RetVT == MVT::ppcf128)
482 return SINTTOFP_I128_PPCF128;
483 }
484 return UNKNOWN_LIBCALL;
485}
486
487/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
488/// UNKNOWN_LIBCALL if there is none.
489RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
490 if (OpVT == MVT::i32) {
491 if (RetVT == MVT::f16)
492 return UINTTOFP_I32_F16;
493 if (RetVT == MVT::f32)
494 return UINTTOFP_I32_F32;
495 if (RetVT == MVT::f64)
496 return UINTTOFP_I32_F64;
497 if (RetVT == MVT::f80)
498 return UINTTOFP_I32_F80;
499 if (RetVT == MVT::f128)
500 return UINTTOFP_I32_F128;
501 if (RetVT == MVT::ppcf128)
502 return UINTTOFP_I32_PPCF128;
503 } else if (OpVT == MVT::i64) {
504 if (RetVT == MVT::bf16)
505 return UINTTOFP_I64_BF16;
506 if (RetVT == MVT::f16)
507 return UINTTOFP_I64_F16;
508 if (RetVT == MVT::f32)
509 return UINTTOFP_I64_F32;
510 if (RetVT == MVT::f64)
511 return UINTTOFP_I64_F64;
512 if (RetVT == MVT::f80)
513 return UINTTOFP_I64_F80;
514 if (RetVT == MVT::f128)
515 return UINTTOFP_I64_F128;
516 if (RetVT == MVT::ppcf128)
517 return UINTTOFP_I64_PPCF128;
518 } else if (OpVT == MVT::i128) {
519 if (RetVT == MVT::f16)
520 return UINTTOFP_I128_F16;
521 if (RetVT == MVT::f32)
522 return UINTTOFP_I128_F32;
523 if (RetVT == MVT::f64)
524 return UINTTOFP_I128_F64;
525 if (RetVT == MVT::f80)
526 return UINTTOFP_I128_F80;
527 if (RetVT == MVT::f128)
528 return UINTTOFP_I128_F128;
529 if (RetVT == MVT::ppcf128)
530 return UINTTOFP_I128_PPCF128;
531 }
532 return UNKNOWN_LIBCALL;
533}
534
535// The floating-point RTLIB::getXXX(EVT) selectors are generated from the
536// RuntimeLibcallFamily table in RuntimeLibcalls.td.
537#define GET_RUNTIME_LIBCALL_FP_SELECTORS
538#include "llvm/IR/RuntimeLibcalls.inc"
539
540RTLIB::Libcall RTLIB::getOutlineAtomicHelper(const Libcall (&LC)[5][4],
541 AtomicOrdering Order,
542 uint64_t MemSize) {
543 unsigned ModeN, ModelN;
544 switch (MemSize) {
545 case 1:
546 ModeN = 0;
547 break;
548 case 2:
549 ModeN = 1;
550 break;
551 case 4:
552 ModeN = 2;
553 break;
554 case 8:
555 ModeN = 3;
556 break;
557 case 16:
558 ModeN = 4;
559 break;
560 default:
561 return RTLIB::UNKNOWN_LIBCALL;
562 }
563
564 switch (Order) {
565 case AtomicOrdering::Monotonic:
566 ModelN = 0;
567 break;
568 case AtomicOrdering::Acquire:
569 ModelN = 1;
570 break;
571 case AtomicOrdering::Release:
572 ModelN = 2;
573 break;
574 case AtomicOrdering::AcquireRelease:
575 case AtomicOrdering::SequentiallyConsistent:
576 ModelN = 3;
577 break;
578 default:
579 return UNKNOWN_LIBCALL;
580 }
581
582 return LC[ModeN][ModelN];
583}
584
585RTLIB::Libcall RTLIB::getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order,
586 MVT VT) {
587 if (!VT.isScalarInteger())
588 return UNKNOWN_LIBCALL;
589 uint64_t MemSize = VT.getScalarSizeInBits() / 8;
590
591#define LCALLS(A, B) \
592 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
593#define LCALL5(A) \
594 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
595 switch (Opc) {
596 case ISD::ATOMIC_CMP_SWAP: {
597 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
598 return getOutlineAtomicHelper(LC, Order, MemSize);
599 }
600 case ISD::ATOMIC_SWAP: {
601 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};
602 return getOutlineAtomicHelper(LC, Order, MemSize);
603 }
604 case ISD::ATOMIC_LOAD_ADD: {
605 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};
606 return getOutlineAtomicHelper(LC, Order, MemSize);
607 }
608 case ISD::ATOMIC_LOAD_OR: {
609 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};
610 return getOutlineAtomicHelper(LC, Order, MemSize);
611 }
612 case ISD::ATOMIC_LOAD_CLR: {
613 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};
614 return getOutlineAtomicHelper(LC, Order, MemSize);
615 }
616 case ISD::ATOMIC_LOAD_XOR: {
617 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};
618 return getOutlineAtomicHelper(LC, Order, MemSize);
619 }
620 default:
621 return UNKNOWN_LIBCALL;
622 }
623#undef LCALLS
624#undef LCALL5
625}
626
627RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
628#define OP_TO_LIBCALL(Name, Enum) \
629 case Name: \
630 switch (VT.SimpleTy) { \
631 default: \
632 return UNKNOWN_LIBCALL; \
633 case MVT::i8: \
634 return Enum##_1; \
635 case MVT::i16: \
636 return Enum##_2; \
637 case MVT::i32: \
638 return Enum##_4; \
639 case MVT::i64: \
640 return Enum##_8; \
641 case MVT::i128: \
642 return Enum##_16; \
643 }
644
645 switch (Opc) {
646 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
647 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
648 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
649 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
650 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
651 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
652 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
653 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
654 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
655 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
656 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
657 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
658 }
659
660#undef OP_TO_LIBCALL
661
662 return UNKNOWN_LIBCALL;
663}
664
665RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
666 switch (ElementSize) {
667 case 1:
668 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
669 case 2:
670 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
671 case 4:
672 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
673 case 8:
674 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
675 case 16:
676 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
677 default:
678 return UNKNOWN_LIBCALL;
679 }
680}
681
682RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
683 switch (ElementSize) {
684 case 1:
685 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
686 case 2:
687 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
688 case 4:
689 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
690 case 8:
691 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
692 case 16:
693 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
694 default:
695 return UNKNOWN_LIBCALL;
696 }
697}
698
699RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
700 switch (ElementSize) {
701 case 1:
702 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
703 case 2:
704 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
705 case 4:
706 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
707 case 8:
708 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
709 case 16:
710 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
711 default:
712 return UNKNOWN_LIBCALL;
713 }
714}
715
716/// NOTE: The TargetMachine owns TLOF.
717TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
718 const TargetSubtargetInfo &STI)
719 : TM(tm),
720 RuntimeLibcallInfo(TM.getTargetTriple(), TM.Options.ExceptionModel,
721 TM.getTargetTriple().getDefaultFloatABI(),
722 TM.Options.MCOptions.getABIName(), TM.Options.VecLib),
723 Libcalls(RuntimeLibcallInfo, [&STI](LibcallLoweringInfo &Info) {
724 STI.initLibcallLoweringInfo(Info);
725 }) {
726 initActions();
727
728 // Perform these initializations only once.
729 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove =
730 MaxLoadsPerMemcmp = 8;
731 MaxGluedStoresPerMemcpy = 0;
732 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize =
733 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4;
734 HasExtractBitsInsn = false;
735 JumpIsExpensive = JumpIsExpensiveOverride;
736 PredictableSelectIsExpensive = false;
737 EnableExtLdPromotion = false;
738 StackPointerRegisterToSaveRestore = 0;
739 BooleanContents = UndefinedBooleanContent;
740 BooleanFloatContents = UndefinedBooleanContent;
741 BooleanVectorContents = UndefinedBooleanContent;
742 SchedPreferenceInfo = Sched::ILP;
743 GatherAllAliasesMaxDepth = 18;
744 IsStrictFPEnabled = DisableStrictNodeMutation;
745 MaxBytesForAlignment = 0;
746 MaxAtomicSizeInBitsSupported = 0;
747
748 // Assume that even with libcalls, no target supports wider than 128 bit
749 // division.
750 MaxDivRemBitWidthSupported = 128;
751
752 MaxLargeFPConvertBitWidthSupported = 128;
753
754 MinCmpXchgSizeInBits = 0;
755 SupportsUnalignedAtomics = false;
756
757 MinimumBitTestCmps = MinimumBitTestCmpsOverride;
758}
759
760// Define the virtual destructor out-of-line to act as a key method to anchor
761// debug info (see coding standards).
762TargetLoweringBase::~TargetLoweringBase() = default;
763
764void TargetLoweringBase::initActions() {
765 // All operations default to being supported.
766 memset(s: OpActions, c: 0, n: sizeof(OpActions));
767 memset(s: LoadExtActions, c: 0, n: sizeof(LoadExtActions));
768 memset(s: AtomicLoadExtActions, c: 0, n: sizeof(AtomicLoadExtActions));
769 memset(s: TruncStoreActions, c: 0, n: sizeof(TruncStoreActions));
770 memset(s: IndexedModeActions, c: 0, n: sizeof(IndexedModeActions));
771 memset(s: CondCodeActions, c: 0, n: sizeof(CondCodeActions));
772 llvm::fill(Range&: RegClassForVT, Value: nullptr);
773 llvm::fill(Range&: TargetDAGCombineArray, Value: 0);
774
775 // Let extending atomic loads be unsupported by default.
776 for (MVT ValVT : MVT::all_valuetypes())
777 for (MVT MemVT : MVT::all_valuetypes())
778 setAtomicLoadExtAction(ExtTypes: {ISD::SEXTLOAD, ISD::ZEXTLOAD}, ValVT, MemVT,
779 Action: Expand);
780
781 // We're somewhat special casing MVT::i2 and MVT::i4. Ideally we want to
782 // remove this and targets should individually set these types if not legal.
783 for (ISD::NodeType NT : enum_seq(Begin: ISD::DELETED_NODE, End: ISD::BUILTIN_OP_END,
784 force_iteration_on_noniterable_enum)) {
785 for (MVT VT : {MVT::i2, MVT::i4})
786 OpActions[(unsigned)VT.SimpleTy][NT] = Expand;
787 }
788 for (MVT AVT : MVT::all_valuetypes()) {
789 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {
790 setTruncStoreAction(ValVT: AVT, MemVT: VT, Action: Expand);
791 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: AVT, MemVT: VT, Action: Expand);
792 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: AVT, MemVT: VT, Action: Expand);
793 }
794 }
795 for (unsigned IM = (unsigned)ISD::PRE_INC;
796 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
797 for (MVT VT : {MVT::i2, MVT::i4}) {
798 setIndexedLoadAction(IdxModes: IM, VT, Action: Expand);
799 setIndexedStoreAction(IdxModes: IM, VT, Action: Expand);
800 setIndexedMaskedLoadAction(IdxMode: IM, VT, Action: Expand);
801 setIndexedMaskedStoreAction(IdxMode: IM, VT, Action: Expand);
802 }
803 }
804
805 for (MVT VT : MVT::fp_valuetypes()) {
806 MVT IntVT = MVT::getIntegerVT(BitWidth: VT.getFixedSizeInBits());
807 if (IntVT.isValid()) {
808 setOperationAction(Op: ISD::ATOMIC_SWAP, VT, Action: Promote);
809 AddPromotedToType(Opc: ISD::ATOMIC_SWAP, OrigVT: VT, DestVT: IntVT);
810 }
811 }
812
813 // If f16 fma is not natively supported, the value must be promoted to an f64
814 // (and not to f32!) to prevent double rounding issues.
815 AddPromotedToType(Opc: ISD::FMA, OrigVT: MVT::f16, DestVT: MVT::f64);
816 AddPromotedToType(Opc: ISD::STRICT_FMA, OrigVT: MVT::f16, DestVT: MVT::f64);
817
818 // Set default actions for various operations.
819 for (MVT VT : MVT::all_valuetypes()) {
820 // Default all indexed load / store to expand.
821 for (unsigned IM = (unsigned)ISD::PRE_INC;
822 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
823 setIndexedLoadAction(IdxModes: IM, VT, Action: Expand);
824 setIndexedStoreAction(IdxModes: IM, VT, Action: Expand);
825 setIndexedMaskedLoadAction(IdxMode: IM, VT, Action: Expand);
826 setIndexedMaskedStoreAction(IdxMode: IM, VT, Action: Expand);
827 }
828
829 // Most backends expect to see the node which just returns the value loaded.
830 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Action: Expand);
831
832 // clang-format off
833 // These operations default to expand.
834 setOperationAction(Ops: {ISD::FGETSIGN, ISD::CONCAT_VECTORS,
835 ISD::FMINNUM, ISD::FMAXNUM,
836 ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
837 ISD::FMINIMUM, ISD::FMAXIMUM,
838 ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM,
839 ISD::FMAD, ISD::SMIN,
840 ISD::SMAX, ISD::UMIN,
841 ISD::UMAX, ISD::ABS,
842 ISD::FSHL, ISD::FSHR,
843 ISD::SADDSAT, ISD::UADDSAT,
844 ISD::SSUBSAT, ISD::USUBSAT,
845 ISD::SSHLSAT, ISD::USHLSAT,
846 ISD::SMULFIX, ISD::SMULFIXSAT,
847 ISD::UMULFIX, ISD::UMULFIXSAT,
848 ISD::SDIVFIX, ISD::SDIVFIXSAT,
849 ISD::UDIVFIX, ISD::UDIVFIXSAT,
850 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT,
851 ISD::IS_FPCLASS, ISD::FCBRT,
852 ISD::FLOG, ISD::FLOG2,
853 ISD::FLOG10, ISD::FEXP,
854 ISD::FEXP2, ISD::FEXP10,
855 ISD::FFLOOR, ISD::FNEARBYINT,
856 ISD::FCEIL, ISD::FRINT,
857 ISD::FTRUNC, ISD::FROUNDEVEN,
858 ISD::FTAN, ISD::FACOS,
859 ISD::FASIN, ISD::FATAN,
860 ISD::FCOSH, ISD::FSINH,
861 ISD::FTANH, ISD::FATAN2,
862 ISD::FMULADD, ISD::CONVERT_FROM_ARBITRARY_FP,
863 ISD::CONVERT_TO_ARBITRARY_FP,
864 ISD::PSEUDO_FMIN, ISD::PSEUDO_FMAX},
865 VT, Action: Expand);
866 // clang-format on
867
868 // Overflow operations default to expand
869 setOperationAction(Ops: {ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO,
870 ISD::SMULO, ISD::UMULO},
871 VT, Action: Expand);
872
873 // Carry-using overflow operations default to expand.
874 setOperationAction(Ops: {ISD::UADDO_CARRY, ISD::USUBO_CARRY, ISD::SETCCCARRY,
875 ISD::SADDO_CARRY, ISD::SSUBO_CARRY},
876 VT, Action: Expand);
877
878 // ADDC/ADDE/SUBC/SUBE default to expand.
879 setOperationAction(Ops: {ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT,
880 Action: Expand);
881
882 // [US]CMP default to expand
883 setOperationAction(Ops: {ISD::UCMP, ISD::SCMP}, VT, Action: Expand);
884
885 // Halving adds
886 setOperationAction(
887 Ops: {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT,
888 Action: Expand);
889
890 // Absolute difference
891 setOperationAction(Ops: {ISD::ABDS, ISD::ABDU}, VT, Action: Expand);
892
893 // Carry-less multiply
894 setOperationAction(Ops: {ISD::CLMUL, ISD::CLMULR, ISD::CLMULH}, VT, Action: Expand);
895
896 // Bit extract/deposit (compress/expand)
897 setOperationAction(Ops: {ISD::PEXT, ISD::PDEP}, VT, Action: Expand);
898
899 // Saturated trunc
900 setOperationAction(Op: ISD::TRUNCATE_SSAT_S, VT, Action: Expand);
901 setOperationAction(Op: ISD::TRUNCATE_SSAT_U, VT, Action: Expand);
902 setOperationAction(Op: ISD::TRUNCATE_USAT_U, VT, Action: Expand);
903
904 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
905 setOperationAction(Ops: {ISD::CTLZ_ZERO_POISON, ISD::CTTZ_ZERO_POISON}, VT,
906 Action: Expand);
907
908 // This defaults to Expand so it will be expanded to ABS by default.
909 setOperationAction(Op: ISD::ABS_MIN_POISON, VT, Action: Expand);
910 setOperationAction(Op: ISD::CTLS, VT, Action: Expand);
911
912 setOperationAction(Ops: {ISD::BITREVERSE, ISD::PARITY}, VT, Action: Expand);
913
914 // These library functions default to expand.
915 setOperationAction(Ops: {ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP,
916 ISD::FSINCOS, ISD::FSINCOSPI, ISD::FMODF},
917 VT, Action: Expand);
918
919 // These operations default to expand for vector types.
920 if (VT.isVector())
921 setOperationAction(Ops: {ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG,
922 ISD::ANY_EXTEND_VECTOR_INREG,
923 ISD::SIGN_EXTEND_VECTOR_INREG,
924 ISD::ZERO_EXTEND_VECTOR_INREG, ISD::SPLAT_VECTOR,
925 ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
926 VT, Action: Expand);
927
928 // Constrained floating-point operations default to expand.
929#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
930 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
931#include "llvm/IR/ConstrainedOps.def"
932 setOperationAction(Op: ISD::STRICT_PSEUDO_FMIN, VT, Action: Expand);
933 setOperationAction(Op: ISD::STRICT_PSEUDO_FMAX, VT, Action: Expand);
934
935 // For most targets @llvm.get.dynamic.area.offset just returns 0.
936 setOperationAction(Op: ISD::GET_DYNAMIC_AREA_OFFSET, VT, Action: Expand);
937
938 // Vector reduction default to expand.
939 setOperationAction(
940 Ops: {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD,
941 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR,
942 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN,
943 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX,
944 ISD::VECREDUCE_FMIN, ISD::VECREDUCE_FMAXIMUM, ISD::VECREDUCE_FMINIMUM,
945 ISD::VECREDUCE_FMAXIMUMNUM, ISD::VECREDUCE_FMINIMUMNUM,
946 ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_SEQ_FMUL},
947 VT, Action: Expand);
948
949 // Named vector shuffles default to expand.
950 setOperationAction(Ops: {ISD::VECTOR_SPLICE_LEFT, ISD::VECTOR_SPLICE_RIGHT}, VT,
951 Action: Expand);
952
953 // Only some target support these vector operations. Default them to Expand.
954 setOperationAction(Ops: {ISD::VECTOR_COMPRESS, ISD::VECTOR_MATCH}, VT, Action: Expand);
955 setOperationAction(Ops: {ISD::CTTZ_ELTS, ISD::CTTZ_ELTS_ZERO_POISON}, VT,
956 Action: Expand);
957 setOperationAction(Op: ISD::GET_ACTIVE_LANE_MASK, VT, Action: Expand);
958
959 // VP operations default to expand.
960#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \
961 setOperationAction(ISD::SDOPC, VT, Expand);
962#include "llvm/IR/VPIntrinsics.def"
963
964 // Masked vector extracts default to expand.
965 setOperationAction(Op: ISD::VECTOR_FIND_LAST_ACTIVE, VT, Action: Expand);
966
967 setOperationAction(Op: ISD::LOOP_DEPENDENCE_RAW_MASK, VT, Action: Expand);
968 setOperationAction(Op: ISD::LOOP_DEPENDENCE_WAR_MASK, VT, Action: Expand);
969
970 setOperationAction(Op: ISD::MASK_BEFOREFIRST, VT, Action: Expand);
971
972 // FP environment operations default to expand.
973 setOperationAction(Op: ISD::GET_FPENV, VT, Action: Expand);
974 setOperationAction(Op: ISD::SET_FPENV, VT, Action: Expand);
975 setOperationAction(Op: ISD::RESET_FPENV, VT, Action: Expand);
976
977 setOperationAction(Op: ISD::MSTORE, VT, Action: Expand);
978
979 setOperationAction(Op: ISD::MASKED_UDIV, VT, Action: Expand);
980 setOperationAction(Op: ISD::MASKED_SDIV, VT, Action: Expand);
981 setOperationAction(Op: ISD::MASKED_UREM, VT, Action: Expand);
982 setOperationAction(Op: ISD::MASKED_SREM, VT, Action: Expand);
983 }
984
985 // Most targets ignore the @llvm.prefetch intrinsic.
986 setOperationAction(Op: ISD::PREFETCH, VT: MVT::Other, Action: Expand);
987
988 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
989 setOperationAction(Op: ISD::READCYCLECOUNTER, VT: MVT::i64, Action: Expand);
990
991 // Most targets also ignore the @llvm.readsteadycounter intrinsic.
992 setOperationAction(Op: ISD::READSTEADYCOUNTER, VT: MVT::i64, Action: Expand);
993
994 // ConstantFP nodes default to expand. Targets can either change this to
995 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
996 // to optimize expansions for certain constants.
997 setOperationAction(Ops: ISD::ConstantFP,
998 VTs: {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},
999 Action: Expand);
1000
1001 // Insert custom handling default for llvm.canonicalize.*.
1002 setOperationAction(Ops: ISD::FCANONICALIZE,
1003 VTs: {MVT::f16, MVT::f32, MVT::f64, MVT::f128}, Action: Expand);
1004
1005 // FIXME: Query RuntimeLibCalls to make the decision.
1006 setOperationAction(Ops: {ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
1007 VTs: {MVT::f32, MVT::f64, MVT::f128}, Action: LibCall);
1008
1009 setOperationAction(Ops: {ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH,
1010 ISD::FSINH, ISD::FTANH, ISD::FATAN2},
1011 VT: MVT::f16, Action: Promote);
1012 // Default ISD::TRAP to expand (which turns it into abort).
1013 setOperationAction(Op: ISD::TRAP, VT: MVT::Other, Action: Expand);
1014
1015 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
1016 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
1017 setOperationAction(Op: ISD::DEBUGTRAP, VT: MVT::Other, Action: Expand);
1018
1019 setOperationAction(Op: ISD::UBSANTRAP, VT: MVT::Other, Action: Expand);
1020
1021 setOperationAction(Op: ISD::GET_FPENV_MEM, VT: MVT::Other, Action: Expand);
1022 setOperationAction(Op: ISD::SET_FPENV_MEM, VT: MVT::Other, Action: Expand);
1023
1024 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
1025 setOperationAction(Op: ISD::GET_FPMODE, VT, Action: Expand);
1026 setOperationAction(Op: ISD::SET_FPMODE, VT, Action: Expand);
1027 }
1028 setOperationAction(Op: ISD::RESET_FPMODE, VT: MVT::Other, Action: Expand);
1029
1030 // This one by default will call __clear_cache unless the target
1031 // wants something different.
1032 setOperationAction(Op: ISD::CLEAR_CACHE, VT: MVT::Other, Action: LibCall);
1033
1034 // By default, STACKADDRESS nodes are expanded like STACKSAVE nodes.
1035 // On SPARC targets, custom lowering is required.
1036 setOperationAction(Op: ISD::STACKADDRESS, VT: MVT::Other, Action: Expand);
1037}
1038
1039MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
1040 EVT) const {
1041 return MVT::getIntegerVT(BitWidth: DL.getPointerSizeInBits(AS: 0));
1042}
1043
1044EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,
1045 const DataLayout &DL) const {
1046 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
1047 if (LHSTy.isVector())
1048 return LHSTy;
1049 MVT ShiftVT = getScalarShiftAmountTy(DL, LHSTy);
1050 // If any possible shift value won't fit in the prefered type, just use
1051 // something safe. Assume it will be legalized when the shift is expanded.
1052 if (ShiftVT.getSizeInBits() < Log2_32_Ceil(Value: LHSTy.getSizeInBits()))
1053 ShiftVT = MVT::i32;
1054 assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) &&
1055 "ShiftVT is still too small!");
1056 return ShiftVT;
1057}
1058
1059bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
1060 assert(isTypeLegal(VT));
1061 switch (Op) {
1062 default:
1063 return false;
1064 case ISD::SDIV:
1065 case ISD::UDIV:
1066 case ISD::SREM:
1067 case ISD::UREM:
1068 return true;
1069 }
1070}
1071
1072bool TargetLoweringBase::isFreeAddrSpaceCast(const DataLayout &DL,
1073 unsigned SrcAS,
1074 unsigned DestAS) const {
1075 return TM.isNoopAddrSpaceCast(DL, SrcAS, DestAS);
1076}
1077
1078unsigned TargetLoweringBase::getBitWidthForCttzElements(
1079 EVT RetVT, ElementCount EC, bool ZeroIsPoison,
1080 const ConstantRange *VScaleRange) const {
1081 // Find the smallest "sensible" element type to use for the expansion.
1082 ConstantRange CR(APInt(64, EC.getKnownMinValue()));
1083 if (EC.isScalable())
1084 CR = CR.umul_sat(Other: *VScaleRange);
1085
1086 if (ZeroIsPoison)
1087 CR = CR.subtract(CI: APInt(64, 1));
1088
1089 unsigned EltWidth = RetVT.getScalarSizeInBits();
1090 EltWidth = std::min(a: EltWidth, b: CR.getActiveBits());
1091 EltWidth = std::max(a: llvm::bit_ceil(Value: EltWidth), b: (unsigned)8);
1092
1093 return EltWidth;
1094}
1095
1096void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
1097 // If the command-line option was specified, ignore this request.
1098 if (!JumpIsExpensiveOverride.getNumOccurrences())
1099 JumpIsExpensive = isExpensive;
1100}
1101
1102TargetLoweringBase::LegalizeKind
1103TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
1104 // If this is a simple type, use the ComputeRegisterProp mechanism.
1105 if (VT.isSimple()) {
1106 MVT SVT = VT.getSimpleVT();
1107 assert((unsigned)SVT.SimpleTy < std::size(TransformToType));
1108 MVT NVT = TransformToType[SVT.SimpleTy];
1109 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(VT: SVT);
1110
1111 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
1112 LA == TypeSoftPromoteHalf ||
1113 (NVT.isVector() ||
1114 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
1115 "Promote may not follow Expand or Promote");
1116
1117 if (LA == TypeSplitVector)
1118 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
1119 if (LA == TypeScalarizeVector)
1120 return LegalizeKind(LA, SVT.getVectorElementType());
1121 return LegalizeKind(LA, NVT);
1122 }
1123
1124 // Handle Extended Scalar Types.
1125 if (!VT.isVector()) {
1126 assert(VT.isInteger() && "Float types must be simple");
1127 unsigned BitSize = VT.getSizeInBits();
1128 // First promote to a power-of-two size, then expand if necessary.
1129 if (BitSize < 8 || !isPowerOf2_32(Value: BitSize)) {
1130 EVT NVT = VT.getRoundIntegerType(Context);
1131 assert(NVT != VT && "Unable to round integer VT");
1132 LegalizeKind NextStep = getTypeConversion(Context, VT: NVT);
1133 // Avoid multi-step promotion.
1134 if (NextStep.first == TypePromoteInteger)
1135 return NextStep;
1136 // Return rounded integer type.
1137 return LegalizeKind(TypePromoteInteger, NVT);
1138 }
1139
1140 return LegalizeKind(TypeExpandInteger,
1141 EVT::getIntegerVT(Context, BitWidth: VT.getSizeInBits() / 2));
1142 }
1143
1144 // Handle vector types.
1145 ElementCount NumElts = VT.getVectorElementCount();
1146 EVT EltVT = VT.getVectorElementType();
1147
1148 // Vectors with only one element are always scalarized.
1149 if (NumElts.isScalar())
1150 return LegalizeKind(TypeScalarizeVector, EltVT);
1151
1152 // Try to widen vector elements until the element type is a power of two and
1153 // promote it to a legal type later on, for example:
1154 // <3 x i8> -> <4 x i8> -> <4 x i32>
1155 if (EltVT.isInteger()) {
1156 // Vectors with a number of elements that is not a power of two are always
1157 // widened, for example <3 x i8> -> <4 x i8>.
1158 if (!VT.isPow2VectorType()) {
1159 NumElts = NumElts.coefficientNextPowerOf2();
1160 EVT NVT = EVT::getVectorVT(Context, VT: EltVT, EC: NumElts);
1161 return LegalizeKind(TypeWidenVector, NVT);
1162 }
1163
1164 // Examine the element type.
1165 LegalizeKind LK = getTypeConversion(Context, VT: EltVT);
1166
1167 // If type is to be expanded, split the vector.
1168 // <4 x i140> -> <2 x i140>
1169 if (LK.first == TypeExpandInteger) {
1170 if (NumElts.isScalable() && NumElts.getKnownMinValue() == 1)
1171 return LegalizeKind(TypeScalarizeScalableVector, EltVT);
1172 return LegalizeKind(TypeSplitVector,
1173 VT.getHalfNumVectorElementsVT(Context));
1174 }
1175
1176 // Promote the integer element types until a legal vector type is found
1177 // or until the element integer type is too big. If a legal type was not
1178 // found, fallback to the usual mechanism of widening/splitting the
1179 // vector.
1180 EVT OldEltVT = EltVT;
1181 while (true) {
1182 // Increase the bitwidth of the element to the next pow-of-two
1183 // (which is greater than 8 bits).
1184 EltVT = EVT::getIntegerVT(Context, BitWidth: 1 + EltVT.getSizeInBits())
1185 .getRoundIntegerType(Context);
1186
1187 // Stop trying when getting a non-simple element type.
1188 // Note that vector elements may be greater than legal vector element
1189 // types. Example: X86 XMM registers hold 64bit element on 32bit
1190 // systems.
1191 if (!EltVT.isSimple())
1192 break;
1193
1194 // Build a new vector type and check if it is legal.
1195 MVT NVT = MVT::getVectorVT(VT: EltVT.getSimpleVT(), EC: NumElts);
1196 // Found a legal promoted vector type.
1197 if (NVT != MVT() && ValueTypeActions.getTypeAction(VT: NVT) == TypeLegal)
1198 return LegalizeKind(TypePromoteInteger,
1199 EVT::getVectorVT(Context, VT: EltVT, EC: NumElts));
1200 }
1201
1202 // Reset the type to the unexpanded type if we did not find a legal vector
1203 // type with a promoted vector element type.
1204 EltVT = OldEltVT;
1205 }
1206
1207 // Try to widen the vector until a legal type is found.
1208 // If there is no wider legal type, split the vector.
1209 while (true) {
1210 // Round up to the next power of 2.
1211 NumElts = NumElts.coefficientNextPowerOf2();
1212
1213 // If there is no simple vector type with this many elements then there
1214 // cannot be a larger legal vector type. Note that this assumes that
1215 // there are no skipped intermediate vector types in the simple types.
1216 if (!EltVT.isSimple())
1217 break;
1218 MVT LargerVector = MVT::getVectorVT(VT: EltVT.getSimpleVT(), EC: NumElts);
1219 if (LargerVector == MVT())
1220 break;
1221
1222 // If this type is legal then widen the vector.
1223 if (ValueTypeActions.getTypeAction(VT: LargerVector) == TypeLegal)
1224 return LegalizeKind(TypeWidenVector, LargerVector);
1225 }
1226
1227 // Widen odd vectors to next power of two.
1228 if (!VT.isPow2VectorType()) {
1229 EVT NVT = VT.getPow2VectorType(Context);
1230 return LegalizeKind(TypeWidenVector, NVT);
1231 }
1232
1233 if (VT.getVectorElementCount() == ElementCount::getScalable(MinVal: 1))
1234 return LegalizeKind(TypeScalarizeScalableVector, EltVT);
1235
1236 // Vectors with illegal element types are expanded.
1237 EVT NVT = EVT::getVectorVT(Context, VT: EltVT,
1238 EC: VT.getVectorElementCount().divideCoefficientBy(RHS: 2));
1239 return LegalizeKind(TypeSplitVector, NVT);
1240}
1241
1242unsigned TargetLoweringBase::getVectorTypeBreakdownMVT(
1243 MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) {
1244 // Figure out the right, legal destination reg to copy into.
1245 ElementCount EC = VT.getVectorElementCount();
1246 MVT EltTy = VT.getVectorElementType();
1247
1248 unsigned NumVectorRegs = 1;
1249
1250 // Scalable vectors cannot be scalarized, so splitting or widening is
1251 // required.
1252 if (VT.isScalableVector() && !isPowerOf2_32(Value: EC.getKnownMinValue()))
1253 llvm_unreachable(
1254 "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1255
1256 // FIXME: We don't support non-power-of-2-sized vectors for now.
1257 // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1258 if (!isPowerOf2_32(Value: EC.getKnownMinValue())) {
1259 // Split EC to unit size (scalable property is preserved).
1260 NumVectorRegs = EC.getKnownMinValue();
1261 EC = ElementCount::getFixed(MinVal: 1);
1262 }
1263
1264 // Divide the input until we get to a supported size. This will
1265 // always end up with an EC that represent a scalar or a scalable
1266 // scalar.
1267 while (EC.getKnownMinValue() > 1 &&
1268 !isTypeLegal(VT: MVT::getVectorVT(VT: EltTy, EC))) {
1269 EC = EC.divideCoefficientBy(RHS: 2);
1270 NumVectorRegs <<= 1;
1271 }
1272
1273 NumIntermediates = NumVectorRegs;
1274
1275 MVT NewVT = MVT::getVectorVT(VT: EltTy, EC);
1276 if (!isTypeLegal(VT: NewVT))
1277 NewVT = EltTy;
1278 IntermediateVT = NewVT;
1279
1280 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
1281
1282 // Convert sizes such as i33 to i64.
1283 LaneSizeInBits = llvm::bit_ceil(Value: LaneSizeInBits);
1284
1285 MVT DestVT = getCachedRegisterType(VT: NewVT);
1286 RegisterVT = DestVT;
1287 if (EVT(DestVT).bitsLT(VT: NewVT)) // Value is expanded, e.g. i64 -> i16.
1288 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1289
1290 // Otherwise, promotion or legal types use the same number of registers as
1291 // the vector decimated to the appropriate level.
1292 return NumVectorRegs;
1293}
1294
1295/// isLegalRC - Return true if the value types that can be represented by the
1296/// specified register class are all legal.
1297bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
1298 const TargetRegisterClass &RC) const {
1299 for (const auto *I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1300 if (isTypeLegal(VT: *I))
1301 return true;
1302 return false;
1303}
1304
1305/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1306/// sequence of memory operands that is recognized by PrologEpilogInserter.
1307MachineBasicBlock *
1308TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
1309 MachineBasicBlock *MBB) const {
1310 MachineInstr *MI = &InitialMI;
1311 MachineFunction &MF = *MI->getMF();
1312 MachineFrameInfo &MFI = MF.getFrameInfo();
1313
1314 // We're handling multiple types of operands here:
1315 // PATCHPOINT MetaArgs - live-in, read only, direct
1316 // STATEPOINT Deopt Spill - live-through, read only, indirect
1317 // STATEPOINT Deopt Alloca - live-through, read only, direct
1318 // (We're currently conservative and mark the deopt slots read/write in
1319 // practice.)
1320 // STATEPOINT GC Spill - live-through, read/write, indirect
1321 // STATEPOINT GC Alloca - live-through, read/write, direct
1322 // The live-in vs live-through is handled already (the live through ones are
1323 // all stack slots), but we need to handle the different type of stackmap
1324 // operands and memory effects here.
1325
1326 if (llvm::none_of(Range: MI->operands(),
1327 P: [](MachineOperand &Operand) { return Operand.isFI(); }))
1328 return MBB;
1329
1330 MachineInstrBuilder MIB = BuildMI(MF, MIMD: MI->getDebugLoc(), MCID: MI->getDesc());
1331
1332 // Inherit previous memory operands.
1333 MIB.cloneMemRefs(OtherMI: *MI);
1334
1335 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1336 MachineOperand &MO = MI->getOperand(i);
1337 if (!MO.isFI()) {
1338 // Index of Def operand this Use it tied to.
1339 // Since Defs are coming before Uses, if Use is tied, then
1340 // index of Def must be smaller that index of that Use.
1341 // Also, Defs preserve their position in new MI.
1342 unsigned TiedTo = i;
1343 if (MO.isReg() && MO.isTied())
1344 TiedTo = MI->findTiedOperandIdx(OpIdx: i);
1345 MIB.add(MO);
1346 if (TiedTo < i)
1347 MIB->tieOperands(DefIdx: TiedTo, UseIdx: MIB->getNumOperands() - 1);
1348 continue;
1349 }
1350
1351 // foldMemoryOperand builds a new MI after replacing a single FI operand
1352 // with the canonical set of five x86 addressing-mode operands.
1353 int FI = MO.getIndex();
1354
1355 // Add frame index operands recognized by stackmaps.cpp
1356 if (MFI.isStatepointSpillSlotObjectIndex(ObjectIdx: FI)) {
1357 // indirect-mem-ref tag, size, #FI, offset.
1358 // Used for spills inserted by StatepointLowering. This codepath is not
1359 // used for patchpoints/stackmaps at all, for these spilling is done via
1360 // foldMemoryOperand callback only.
1361 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1362 MIB.addImm(Val: StackMaps::IndirectMemRefOp);
1363 MIB.addImm(Val: MFI.getObjectSize(ObjectIdx: FI));
1364 MIB.add(MO);
1365 MIB.addImm(Val: 0);
1366 } else {
1367 // direct-mem-ref tag, #FI, offset.
1368 // Used by patchpoint, and direct alloca arguments to statepoints
1369 MIB.addImm(Val: StackMaps::DirectMemRefOp);
1370 MIB.add(MO);
1371 MIB.addImm(Val: 0);
1372 }
1373
1374 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1375
1376 // Add a new memory operand for this FI.
1377 assert(MFI.getObjectOffset(FI) != -1);
1378
1379 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1380 // PATCHPOINT should be updated to do the same. (TODO)
1381 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1382 auto Flags = MachineMemOperand::MOLoad;
1383 MachineMemOperand *MMO = MF.getMachineMemOperand(
1384 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI), F: Flags,
1385 Size: MF.getDataLayout().getPointerSize(), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
1386 MIB->addMemOperand(MF, MO: MMO);
1387 }
1388 }
1389 MBB->insert(I: MachineBasicBlock::iterator(MI), MI: MIB);
1390 MI->eraseFromParent();
1391 return MBB;
1392}
1393
1394/// findRepresentativeClass - Return the largest legal super-reg register class
1395/// of the register class for the specified type and its associated "cost".
1396// This function is in TargetLowering because it uses RegClassForVT which would
1397// need to be moved to TargetRegisterInfo and would necessitate moving
1398// isTypeLegal over as well - a massive change that would just require
1399// TargetLowering having a TargetRegisterInfo class member that it would use.
1400std::pair<const TargetRegisterClass *, uint8_t>
1401TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1402 MVT VT) const {
1403 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1404 if (!RC)
1405 return std::make_pair(x&: RC, y: 0);
1406
1407 // Compute the set of all super-register classes.
1408 BitVector SuperRegRC(TRI->getNumRegClasses());
1409 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1410 SuperRegRC.setBitsInMask(Mask: RCI.getMask());
1411
1412 // Find the first legal register class with the largest spill size.
1413 const TargetRegisterClass *BestRC = RC;
1414 for (unsigned i : SuperRegRC.set_bits()) {
1415 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1416 // We want the largest possible spill size.
1417 if (TRI->getSpillSize(RC: *SuperRC) <= TRI->getSpillSize(RC: *BestRC))
1418 continue;
1419 if (!isLegalRC(TRI: *TRI, RC: *SuperRC))
1420 continue;
1421 BestRC = SuperRC;
1422 }
1423 return std::make_pair(x&: BestRC, y: 1);
1424}
1425
1426/// computeRegisterProperties - Once all of the register classes are added,
1427/// this allows us to compute derived properties we expose.
1428void TargetLoweringBase::computeRegisterProperties(
1429 const TargetRegisterInfo *TRI) {
1430 // Everything defaults to needing one register.
1431 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1432 NumRegistersForVT[i] = 1;
1433 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1434 }
1435 // ...except isVoid, which doesn't need any registers.
1436 NumRegistersForVT[MVT::isVoid] = 0;
1437
1438 // Find the largest integer register class.
1439 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1440 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1441 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1442
1443 // Every integer value type larger than this largest register takes twice as
1444 // many registers to represent as the previous ValueType.
1445 for (unsigned ExpandedReg = LargestIntReg + 1;
1446 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1447 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1448 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1449 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1450 ValueTypeActions.setTypeAction(VT: (MVT::SimpleValueType)ExpandedReg,
1451 Action: TypeExpandInteger);
1452 }
1453
1454 // Inspect all of the ValueType's smaller than the largest integer
1455 // register to see which ones need promotion.
1456 unsigned LegalIntReg = LargestIntReg;
1457 for (unsigned IntReg = LargestIntReg - 1;
1458 IntReg >= (unsigned)MVT::i1; --IntReg) {
1459 MVT IVT = (MVT::SimpleValueType)IntReg;
1460 if (isTypeLegal(VT: IVT)) {
1461 LegalIntReg = IntReg;
1462 } else {
1463 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1464 (MVT::SimpleValueType)LegalIntReg;
1465 ValueTypeActions.setTypeAction(VT: IVT, Action: TypePromoteInteger);
1466 }
1467 }
1468
1469 // ppcf128 type is really two f64's.
1470 if (!isTypeLegal(VT: MVT::ppcf128)) {
1471 if (isTypeLegal(VT: MVT::f64)) {
1472 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1473 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1474 TransformToType[MVT::ppcf128] = MVT::f64;
1475 ValueTypeActions.setTypeAction(VT: MVT::ppcf128, Action: TypeExpandFloat);
1476 } else {
1477 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1478 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1479 TransformToType[MVT::ppcf128] = MVT::i128;
1480 ValueTypeActions.setTypeAction(VT: MVT::ppcf128, Action: TypeSoftenFloat);
1481 }
1482 }
1483
1484 // Decide how to handle f128. If the target does not have native f128 support,
1485 // expand it to i128 and we will be generating soft float library calls.
1486 if (!isTypeLegal(VT: MVT::f128)) {
1487 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1488 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1489 TransformToType[MVT::f128] = MVT::i128;
1490 ValueTypeActions.setTypeAction(VT: MVT::f128, Action: TypeSoftenFloat);
1491 }
1492
1493 // Decide how to handle f80. If the target does not have native f80 support,
1494 // expand it to i96 and we will be generating soft float library calls.
1495 if (!isTypeLegal(VT: MVT::f80)) {
1496 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];
1497 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];
1498 TransformToType[MVT::f80] = MVT::i32;
1499 ValueTypeActions.setTypeAction(VT: MVT::f80, Action: TypeSoftenFloat);
1500 }
1501
1502 // Decide how to handle f64. If the target does not have native f64 support,
1503 // expand it to i64 and we will be generating soft float library calls.
1504 if (!isTypeLegal(VT: MVT::f64)) {
1505 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1506 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1507 TransformToType[MVT::f64] = MVT::i64;
1508 ValueTypeActions.setTypeAction(VT: MVT::f64, Action: TypeSoftenFloat);
1509 }
1510
1511 // Decide how to handle f32. If the target does not have native f32 support,
1512 // expand it to i32 and we will be generating soft float library calls.
1513 if (!isTypeLegal(VT: MVT::f32)) {
1514 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1515 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1516 TransformToType[MVT::f32] = MVT::i32;
1517 ValueTypeActions.setTypeAction(VT: MVT::f32, Action: TypeSoftenFloat);
1518 }
1519
1520 // Decide how to handle f16. If the target does not have native f16 support,
1521 // promote it to f32, because there are no f16 library calls (except for
1522 // conversions).
1523 if (!isTypeLegal(VT: MVT::f16)) {
1524 // Allow targets to control how we legalize half.
1525 bool UseFPRegsForHalfType = useFPRegsForHalfType();
1526
1527 if (!UseFPRegsForHalfType) {
1528 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1529 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1530 } else {
1531 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1532 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1533 }
1534 TransformToType[MVT::f16] = MVT::f32;
1535 ValueTypeActions.setTypeAction(VT: MVT::f16, Action: TypeSoftPromoteHalf);
1536 }
1537
1538 // Decide how to handle bf16. If the target does not have native bf16 support,
1539 // promote it to f32, because there are no bf16 library calls (except for
1540 // converting from f32 to bf16).
1541 if (!isTypeLegal(VT: MVT::bf16)) {
1542 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];
1543 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];
1544 TransformToType[MVT::bf16] = MVT::f32;
1545 ValueTypeActions.setTypeAction(VT: MVT::bf16, Action: TypeSoftPromoteHalf);
1546 }
1547
1548 // Loop over all of the vector value types to see which need transformations.
1549 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1550 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1551 MVT VT = (MVT::SimpleValueType) i;
1552 if (isTypeLegal(VT))
1553 continue;
1554
1555 MVT EltVT = VT.getVectorElementType();
1556 ElementCount EC = VT.getVectorElementCount();
1557 bool IsLegalWiderType = false;
1558 bool IsScalable = VT.isScalableVector();
1559 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1560 switch (PreferredAction) {
1561 case TypePromoteInteger: {
1562 MVT::SimpleValueType EndVT = IsScalable ?
1563 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :
1564 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;
1565 // Try to promote the elements of integer vectors. If no legal
1566 // promotion was found, fall through to the widen-vector method.
1567 for (unsigned nVT = i + 1;
1568 (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1569 MVT SVT = (MVT::SimpleValueType) nVT;
1570 // Promote vectors of integers to vectors with the same number
1571 // of elements, with a wider element type.
1572 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1573 SVT.getVectorElementCount() == EC && isTypeLegal(VT: SVT)) {
1574 TransformToType[i] = SVT;
1575 RegisterTypeForVT[i] = SVT;
1576 NumRegistersForVT[i] = 1;
1577 ValueTypeActions.setTypeAction(VT, Action: TypePromoteInteger);
1578 IsLegalWiderType = true;
1579 break;
1580 }
1581 }
1582 if (IsLegalWiderType)
1583 break;
1584 [[fallthrough]];
1585 }
1586
1587 case TypeWidenVector:
1588 if (isPowerOf2_32(Value: EC.getKnownMinValue())) {
1589 // Try to widen the vector.
1590 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1591 MVT SVT = (MVT::SimpleValueType) nVT;
1592 if (SVT.getVectorElementType() == EltVT &&
1593 SVT.isScalableVector() == IsScalable &&
1594 SVT.getVectorElementCount().getKnownMinValue() >
1595 EC.getKnownMinValue() &&
1596 isTypeLegal(VT: SVT)) {
1597 TransformToType[i] = SVT;
1598 RegisterTypeForVT[i] = SVT;
1599 NumRegistersForVT[i] = 1;
1600 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1601 IsLegalWiderType = true;
1602 break;
1603 }
1604 }
1605 if (IsLegalWiderType)
1606 break;
1607 } else {
1608 // Only widen to the next power of 2 to keep consistency with EVT.
1609 MVT NVT = VT.getPow2VectorType();
1610 if (isTypeLegal(VT: NVT)) {
1611 TransformToType[i] = NVT;
1612 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1613 RegisterTypeForVT[i] = NVT;
1614 NumRegistersForVT[i] = 1;
1615 break;
1616 }
1617 }
1618 [[fallthrough]];
1619
1620 case TypeSplitVector:
1621 case TypeScalarizeVector: {
1622 MVT IntermediateVT;
1623 MVT RegisterVT;
1624 unsigned NumIntermediates;
1625 unsigned NumRegisters = getVectorTypeBreakdownMVT(
1626 VT, IntermediateVT, NumIntermediates, RegisterVT);
1627 NumRegistersForVT[i] = NumRegisters;
1628 assert(NumRegistersForVT[i] == NumRegisters &&
1629 "NumRegistersForVT size cannot represent NumRegisters!");
1630 RegisterTypeForVT[i] = RegisterVT;
1631
1632 MVT NVT = VT.getPow2VectorType();
1633 if (NVT == VT) {
1634 // Type is already a power of 2. The default action is to split.
1635 TransformToType[i] = MVT::Other;
1636 if (PreferredAction == TypeScalarizeVector)
1637 ValueTypeActions.setTypeAction(VT, Action: TypeScalarizeVector);
1638 else if (PreferredAction == TypeSplitVector)
1639 ValueTypeActions.setTypeAction(VT, Action: TypeSplitVector);
1640 else if (EC.getKnownMinValue() > 1)
1641 ValueTypeActions.setTypeAction(VT, Action: TypeSplitVector);
1642 else
1643 ValueTypeActions.setTypeAction(VT, Action: EC.isScalable()
1644 ? TypeScalarizeScalableVector
1645 : TypeScalarizeVector);
1646 } else {
1647 TransformToType[i] = NVT;
1648 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1649 }
1650 break;
1651 }
1652 default:
1653 llvm_unreachable("Unknown vector legalization action!");
1654 }
1655 }
1656
1657 // Determine the 'representative' register class for each value type.
1658 // An representative register class is the largest (meaning one which is
1659 // not a sub-register class / subreg register class) legal register class for
1660 // a group of value types. For example, on i386, i8, i16, and i32
1661 // representative would be GR32; while on x86_64 it's GR64.
1662 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1663 const TargetRegisterClass* RRC;
1664 uint8_t Cost;
1665 std::tie(args&: RRC, args&: Cost) = findRepresentativeClass(TRI, VT: (MVT::SimpleValueType)i);
1666 RepRegClassForVT[i] = RRC;
1667 RepRegClassCostForVT[i] = Cost;
1668 }
1669
1670 // Compute minimum known-legal store size.
1671 MaximumLegalStoreInBits = 0;
1672 for (MVT VT : MVT::all_valuetypes())
1673 if (VT != MVT::Other && isTypeLegal(VT) &&
1674 VT.getSizeInBits().getKnownMinValue() >= MaximumLegalStoreInBits)
1675 MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinValue();
1676}
1677
1678EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1679 EVT VT) const {
1680 assert(!VT.isVector() && "No default SetCC type for vectors!");
1681 return getPointerTy(DL).SimpleTy;
1682}
1683
1684/// getVectorTypeBreakdown - Vector types are broken down into some number of
1685/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1686/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1687/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1688///
1689/// This method returns the number of registers needed, and the VT for each
1690/// register. It also returns the VT and quantity of the intermediate values
1691/// before they are promoted/expanded.
1692unsigned TargetLoweringBase::getVectorTypeBreakdownImpl(
1693 LLVMContext &Context, EVT VT, EVT &IntermediateVT,
1694 unsigned &NumIntermediates, MVT &RegisterVT, bool ForCallingConv) const {
1695 ElementCount EltCnt = VT.getVectorElementCount();
1696
1697 // If there is a wider vector type with the same element type as this one,
1698 // or a promoted vector type that has the same number of elements which
1699 // are wider, then we should convert to that legal vector type.
1700 // This handles things like <2 x float> -> <4 x float> and
1701 // <4 x i1> -> <4 x i32>.
1702 LegalizeTypeAction TA = getTypeAction(Context, VT);
1703 if (!EltCnt.isScalar() &&
1704 (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1705 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1706 if (isTypeLegal(VT: RegisterEVT)) {
1707 IntermediateVT = RegisterEVT;
1708 RegisterVT = RegisterEVT.getSimpleVT();
1709 NumIntermediates = 1;
1710 return 1;
1711 }
1712 }
1713
1714 // Figure out the right, legal destination reg to copy into.
1715 EVT EltTy = VT.getVectorElementType();
1716
1717 unsigned NumVectorRegs = 1;
1718
1719 auto GetLegalVectorBreakdown = [&]() -> std::optional<unsigned> {
1720 LegalizeKind LK;
1721 EVT PartVT = VT;
1722 do {
1723 // Iterate until we've found a legal (part) type to hold VT.
1724 LK = getTypeConversion(Context, VT: PartVT);
1725 PartVT = LK.second;
1726 } while (LK.first != TypeLegal);
1727
1728 if (!PartVT.isVector())
1729 return std::nullopt;
1730
1731 assert(PartVT.isScalableVector() == VT.isScalableVector() &&
1732 "Vector legalization changed scalability");
1733 NumIntermediates =
1734 divideCeil(Numerator: VT.getVectorElementCount().getKnownMinValue(),
1735 Denominator: PartVT.getVectorElementCount().getKnownMinValue());
1736 IntermediateVT = PartVT;
1737 RegisterVT = getRegisterType(Context, VT: IntermediateVT);
1738 return NumIntermediates;
1739 };
1740
1741 // Scalable vectors cannot be scalarized, so handle the legalisation of the
1742 // types like done elsewhere in SelectionDAG.
1743 if (EltCnt.isScalable()) {
1744 if (std::optional<unsigned> NumRegs = GetLegalVectorBreakdown())
1745 return *NumRegs;
1746 report_fatal_error(reason: "Don't know how to legalize this scalable vector type");
1747 }
1748
1749 // FIXME: We don't generically support non-power-of-2-sized vectors for now.
1750 // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1751 if (!isPowerOf2_32(Value: EltCnt.getKnownMinValue())) {
1752 assert(VT.isFixedLengthVector() && "Expected a fixed-length vector VT");
1753 unsigned NumElts = EltCnt.getKnownMinValue();
1754
1755 if (!ForCallingConv && preferVectorizedNonPowerOfTwoTypeBreakdown())
1756 if (std::optional<unsigned> NumRegs = GetLegalVectorBreakdown())
1757 return *NumRegs;
1758
1759 // Fall back to scalars if there is no legal vector decomposition.
1760 NumVectorRegs = NumElts;
1761 EltCnt = ElementCount::getFixed(MinVal: 1);
1762 }
1763
1764 // Divide the input until we get to a supported size. This will always
1765 // end with a scalar if the target doesn't support vectors.
1766 while (EltCnt.getKnownMinValue() > 1 &&
1767 !isTypeLegal(VT: EVT::getVectorVT(Context, VT: EltTy, EC: EltCnt))) {
1768 EltCnt = EltCnt.divideCoefficientBy(RHS: 2);
1769 NumVectorRegs <<= 1;
1770 }
1771
1772 NumIntermediates = NumVectorRegs;
1773
1774 EVT NewVT = EVT::getVectorVT(Context, VT: EltTy, EC: EltCnt);
1775 if (!isTypeLegal(VT: NewVT))
1776 NewVT = EltTy;
1777 IntermediateVT = NewVT;
1778
1779 MVT DestVT = getRegisterType(Context, VT: NewVT);
1780 RegisterVT = DestVT;
1781
1782 if (EVT(DestVT).bitsLT(VT: NewVT)) { // Value is expanded, e.g. i64 -> i16.
1783 TypeSize NewVTSize = NewVT.getSizeInBits();
1784 // Convert sizes such as i33 to i64.
1785 if (!llvm::has_single_bit<uint32_t>(Value: NewVTSize.getKnownMinValue()))
1786 NewVTSize = NewVTSize.coefficientNextPowerOf2();
1787 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1788 }
1789
1790 // Otherwise, promotion or legal types use the same number of registers as
1791 // the vector decimated to the appropriate level.
1792 return NumVectorRegs;
1793}
1794
1795bool TargetLoweringBase::isSuitableForJumpTable(const SwitchInst *SI,
1796 uint64_t NumCases,
1797 uint64_t Range,
1798 ProfileSummaryInfo *PSI,
1799 BlockFrequencyInfo *BFI) const {
1800 // FIXME: This function check the maximum table size and density, but the
1801 // minimum size is not checked. It would be nice if the minimum size is
1802 // also combined within this function. Currently, the minimum size check is
1803 // performed in findJumpTable() in SelectionDAGBuiler and
1804 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1805 const bool OptForSize =
1806 llvm::shouldOptimizeForSize(BB: SI->getParent(), PSI, BFI);
1807 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1808 const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1809
1810 // Check whether the number of cases is small enough and
1811 // the range is dense enough for a jump table.
1812 return (OptForSize || Range <= MaxJumpTableSize) &&
1813 (NumCases * 100 >= Range * MinDensity);
1814}
1815
1816MVT TargetLoweringBase::getPreferredSwitchConditionType(LLVMContext &Context,
1817 EVT ConditionVT) const {
1818 return getRegisterType(Context, VT: ConditionVT);
1819}
1820
1821/// Get the EVTs and ArgFlags collections that represent the legalized return
1822/// type of the given function. This does not require a DAG or a return value,
1823/// and is suitable for use before any DAGs for the function are constructed.
1824/// TODO: Move this out of TargetLowering.cpp.
1825void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType,
1826 AttributeList attr,
1827 SmallVectorImpl<ISD::OutputArg> &Outs,
1828 const TargetLowering &TLI, const DataLayout &DL) {
1829 SmallVector<Type *, 4> Types;
1830 ComputeValueTypes(DL, Ty: ReturnType, Types);
1831 unsigned NumValues = Types.size();
1832 if (NumValues == 0) return;
1833
1834 for (Type *Ty : Types) {
1835 EVT VT = TLI.getValueType(DL, Ty);
1836 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1837
1838 if (attr.hasRetAttr(Kind: Attribute::SExt))
1839 ExtendKind = ISD::SIGN_EXTEND;
1840 else if (attr.hasRetAttr(Kind: Attribute::ZExt))
1841 ExtendKind = ISD::ZERO_EXTEND;
1842
1843 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1844 VT = TLI.getTypeForExtReturn(Context&: ReturnType->getContext(), VT, ExtendKind);
1845
1846 unsigned NumParts =
1847 TLI.getNumRegistersForCallingConv(Context&: ReturnType->getContext(), CC, VT);
1848 MVT PartVT =
1849 TLI.getRegisterTypeForCallingConv(Context&: ReturnType->getContext(), CC, VT);
1850
1851 // 'inreg' on function refers to return value
1852 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1853 if (attr.hasRetAttr(Kind: Attribute::InReg))
1854 Flags.setInReg();
1855
1856 // Propagate extension type if any
1857 if (attr.hasRetAttr(Kind: Attribute::SExt))
1858 Flags.setSExt();
1859 else if (attr.hasRetAttr(Kind: Attribute::ZExt))
1860 Flags.setZExt();
1861
1862 for (unsigned i = 0; i < NumParts; ++i)
1863 Outs.push_back(Elt: ISD::OutputArg(Flags, PartVT, VT, Ty, 0, 0));
1864 }
1865}
1866
1867Align TargetLoweringBase::getByValTypeAlignment(Type *Ty,
1868 const DataLayout &DL) const {
1869 return DL.getABITypeAlign(Ty);
1870}
1871
1872bool TargetLoweringBase::allowsMemoryAccessForAlignment(
1873 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1874 Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const {
1875 // Check if the specified alignment is sufficient based on the data layout.
1876 // TODO: While using the data layout works in practice, a better solution
1877 // would be to implement this check directly (make this a virtual function).
1878 // For example, the ABI alignment may change based on software platform while
1879 // this function should only be affected by hardware implementation.
1880 Type *Ty = VT.getTypeForEVT(Context);
1881 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {
1882 // Assume that an access that meets the ABI-specified alignment is fast.
1883 if (Fast != nullptr)
1884 *Fast = 1;
1885 return true;
1886 }
1887
1888 // This is a misaligned access.
1889 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1890}
1891
1892bool TargetLoweringBase::allowsMemoryAccessForAlignment(
1893 LLVMContext &Context, const DataLayout &DL, EVT VT,
1894 const MachineMemOperand &MMO, unsigned *Fast) const {
1895 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace: MMO.getAddrSpace(),
1896 Alignment: MMO.getAlign(), Flags: MMO.getFlags(), Fast);
1897}
1898
1899bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1900 const DataLayout &DL, EVT VT,
1901 unsigned AddrSpace, Align Alignment,
1902 MachineMemOperand::Flags Flags,
1903 unsigned *Fast) const {
1904 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1905 Flags, Fast);
1906}
1907
1908bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1909 const DataLayout &DL, EVT VT,
1910 const MachineMemOperand &MMO,
1911 unsigned *Fast) const {
1912 return allowsMemoryAccess(Context, DL, VT, AddrSpace: MMO.getAddrSpace(), Alignment: MMO.getAlign(),
1913 Flags: MMO.getFlags(), Fast);
1914}
1915
1916bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1917 const DataLayout &DL, LLT Ty,
1918 const MachineMemOperand &MMO,
1919 unsigned *Fast) const {
1920 EVT VT = getApproximateEVTForLLT(Ty, Ctx&: Context);
1921 return allowsMemoryAccess(Context, DL, VT, AddrSpace: MMO.getAddrSpace(), Alignment: MMO.getAlign(),
1922 Flags: MMO.getFlags(), Fast);
1923}
1924
1925unsigned TargetLoweringBase::getMaxStoresPerMemset(bool OptSize) const {
1926 if (MaxStoresPerMemsetOverride > 0)
1927 return MaxStoresPerMemsetOverride;
1928
1929 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1930}
1931
1932unsigned TargetLoweringBase::getMaxStoresPerMemcpy(bool OptSize) const {
1933 if (MaxStoresPerMemcpyOverride > 0)
1934 return MaxStoresPerMemcpyOverride;
1935
1936 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1937}
1938
1939unsigned TargetLoweringBase::getMaxStoresPerMemmove(bool OptSize) const {
1940 if (MaxStoresPerMemmoveOverride > 0)
1941 return MaxStoresPerMemmoveOverride;
1942
1943 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1944}
1945
1946//===----------------------------------------------------------------------===//
1947// TargetTransformInfo Helpers
1948//===----------------------------------------------------------------------===//
1949
1950int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1951 enum InstructionOpcodes {
1952#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1953#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1954#include "llvm/IR/Instruction.def"
1955 };
1956 // clang-format off
1957 switch (static_cast<InstructionOpcodes>(Opcode)) {
1958 case Ret: return 0;
1959 case UncondBr: return 0;
1960 case CondBr: return 0;
1961 case Switch: return 0;
1962 case IndirectBr: return 0;
1963 case Invoke: return 0;
1964 case CallBr: return 0;
1965 case Resume: return 0;
1966 case Unreachable: return 0;
1967 case CleanupRet: return 0;
1968 case CatchRet: return 0;
1969 case CatchPad: return 0;
1970 case CatchSwitch: return 0;
1971 case CleanupPad: return 0;
1972 case FNeg: return ISD::FNEG;
1973 case Add: return ISD::ADD;
1974 case FAdd: return ISD::FADD;
1975 case Sub: return ISD::SUB;
1976 case FSub: return ISD::FSUB;
1977 case Mul: return ISD::MUL;
1978 case FMul: return ISD::FMUL;
1979 case UDiv: return ISD::UDIV;
1980 case SDiv: return ISD::SDIV;
1981 case FDiv: return ISD::FDIV;
1982 case URem: return ISD::UREM;
1983 case SRem: return ISD::SREM;
1984 case FRem: return ISD::FREM;
1985 case Shl: return ISD::SHL;
1986 case LShr: return ISD::SRL;
1987 case AShr: return ISD::SRA;
1988 case And: return ISD::AND;
1989 case Or: return ISD::OR;
1990 case Xor: return ISD::XOR;
1991 case Alloca: return 0;
1992 case Load: return ISD::LOAD;
1993 case Store: return ISD::STORE;
1994 case GetElementPtr: return 0;
1995 case Fence: return 0;
1996 case AtomicCmpXchg: return 0;
1997 case AtomicRMW: return 0;
1998 case Trunc: return ISD::TRUNCATE;
1999 case ZExt: return ISD::ZERO_EXTEND;
2000 case SExt: return ISD::SIGN_EXTEND;
2001 case FPToUI: return ISD::FP_TO_UINT;
2002 case FPToSI: return ISD::FP_TO_SINT;
2003 case UIToFP: return ISD::UINT_TO_FP;
2004 case SIToFP: return ISD::SINT_TO_FP;
2005 case FPTrunc: return ISD::FP_ROUND;
2006 case FPExt: return ISD::FP_EXTEND;
2007 case PtrToAddr: return ISD::BITCAST;
2008 case PtrToInt: return ISD::BITCAST;
2009 case IntToPtr: return ISD::BITCAST;
2010 case BitCast: return ISD::BITCAST;
2011 case AddrSpaceCast: return ISD::ADDRSPACECAST;
2012 case ICmp: return ISD::SETCC;
2013 case FCmp: return ISD::SETCC;
2014 case PHI: return 0;
2015 case Call: return 0;
2016 case Select: return ISD::SELECT;
2017 case UserOp1: return 0;
2018 case UserOp2: return 0;
2019 case VAArg: return 0;
2020 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
2021 case InsertElement: return ISD::INSERT_VECTOR_ELT;
2022 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
2023 case ExtractValue: return ISD::MERGE_VALUES;
2024 case InsertValue: return ISD::MERGE_VALUES;
2025 case LandingPad: return 0;
2026 case Freeze: return ISD::FREEZE;
2027 case BitInsert: return 0;
2028 case BitExtract: return 0;
2029 }
2030 // clang-format on
2031 llvm_unreachable("Unknown instruction type encountered!");
2032}
2033
2034int TargetLoweringBase::IntrinsicIDToISD(Intrinsic::ID ID) const {
2035 switch (ID) {
2036 case Intrinsic::acos:
2037 return ISD::FACOS;
2038 case Intrinsic::asin:
2039 return ISD::FASIN;
2040 case Intrinsic::atan:
2041 return ISD::FATAN;
2042 case Intrinsic::cos:
2043 return ISD::FCOS;
2044 case Intrinsic::cosh:
2045 return ISD::FCOSH;
2046 case Intrinsic::exp:
2047 return ISD::FEXP;
2048 case Intrinsic::exp2:
2049 return ISD::FEXP2;
2050 case Intrinsic::exp10:
2051 return ISD::FEXP10;
2052 case Intrinsic::log:
2053 return ISD::FLOG;
2054 case Intrinsic::log2:
2055 return ISD::FLOG2;
2056 case Intrinsic::log10:
2057 return ISD::FLOG10;
2058 case Intrinsic::modf:
2059 return ISD::FMODF;
2060 case Intrinsic::sin:
2061 return ISD::FSIN;
2062 case Intrinsic::sincos:
2063 return ISD::FSINCOS;
2064 case Intrinsic::sincospi:
2065 return ISD::FSINCOSPI;
2066 case Intrinsic::sinh:
2067 return ISD::FSINH;
2068 case Intrinsic::tan:
2069 return ISD::FTAN;
2070 case Intrinsic::tanh:
2071 return ISD::FTANH;
2072 default:
2073 return ISD::DELETED_NODE;
2074 }
2075}
2076
2077Value *
2078TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilderBase &IRB,
2079 bool UseTLS) const {
2080 // compiler-rt provides a variable with a magic name. Targets that do not
2081 // link with compiler-rt may also provide such a variable.
2082 Module *M = IRB.getModule();
2083
2084 RTLIB::LibcallImpl UnsafeStackPtrImpl =
2085 Libcalls.getLibcallImpl(Call: RTLIB::SAFESTACK_UNSAFE_STACK_PTR);
2086 if (UnsafeStackPtrImpl == RTLIB::Unsupported)
2087 return nullptr;
2088
2089 StringRef UnsafeStackPtrVar =
2090 RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: UnsafeStackPtrImpl);
2091 auto UnsafeStackPtr =
2092 dyn_cast_or_null<GlobalVariable>(Val: M->getNamedValue(Name: UnsafeStackPtrVar));
2093
2094 const DataLayout &DL = M->getDataLayout();
2095 PointerType *StackPtrTy = DL.getAllocaPtrType(Ctx&: M->getContext());
2096
2097 if (!UnsafeStackPtr) {
2098 auto TLSModel = UseTLS ?
2099 GlobalValue::InitialExecTLSModel :
2100 GlobalValue::NotThreadLocal;
2101 // The global variable is not defined yet, define it ourselves.
2102 // We use the initial-exec TLS model because we do not support the
2103 // variable living anywhere other than in the main executable.
2104 UnsafeStackPtr = new GlobalVariable(
2105 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
2106 UnsafeStackPtrVar, nullptr, TLSModel);
2107 } else {
2108 // The variable exists, check its type and attributes.
2109 //
2110 // FIXME: Move to IR verifier.
2111 if (UnsafeStackPtr->getValueType() != StackPtrTy)
2112 report_fatal_error(reason: Twine(UnsafeStackPtrVar) + " must have void* type");
2113 if (UseTLS != UnsafeStackPtr->isThreadLocal())
2114 report_fatal_error(reason: Twine(UnsafeStackPtrVar) + " must " +
2115 (UseTLS ? "" : "not ") + "be thread-local");
2116 }
2117 return UnsafeStackPtr;
2118}
2119
2120Value *TargetLoweringBase::getSafeStackPointerLocation(
2121 IRBuilderBase &IRB, const LibcallLoweringInfo &Libcalls) const {
2122 RTLIB::LibcallImpl SafestackPointerAddressImpl =
2123 Libcalls.getLibcallImpl(Call: RTLIB::SAFESTACK_POINTER_ADDRESS);
2124 if (SafestackPointerAddressImpl == RTLIB::Unsupported)
2125 return getDefaultSafeStackPointerLocation(IRB, UseTLS: true);
2126
2127 Module *M = IRB.getModule();
2128 auto *PtrTy = PointerType::getUnqual(C&: M->getContext());
2129
2130 // Android provides a libc function to retrieve the address of the current
2131 // thread's unsafe stack pointer.
2132 FunctionCallee Fn =
2133 M->getOrInsertFunction(Name: RTLIB::RuntimeLibcallsInfo::getLibcallImplName(
2134 CallImpl: SafestackPointerAddressImpl),
2135 RetTy: PtrTy);
2136 return IRB.CreateCall(Callee: Fn);
2137}
2138
2139//===----------------------------------------------------------------------===//
2140// Loop Strength Reduction hooks
2141//===----------------------------------------------------------------------===//
2142
2143/// isLegalAddressingMode - Return true if the addressing mode represented
2144/// by AM is legal for this target, for a load/store of the specified type.
2145bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
2146 const AddrMode &AM, Type *Ty,
2147 unsigned AS, Instruction *I) const {
2148 // The default implementation of this implements a conservative RISCy, r+r and
2149 // r+i addr mode.
2150
2151 // Scalable offsets not supported
2152 if (AM.ScalableOffset)
2153 return false;
2154
2155 // Allows a sign-extended 16-bit immediate field.
2156 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2157 return false;
2158
2159 // No global is ever allowed as a base.
2160 if (AM.BaseGV)
2161 return false;
2162
2163 // Only support r+r,
2164 switch (AM.Scale) {
2165 case 0: // "r+i" or just "i", depending on HasBaseReg.
2166 break;
2167 case 1:
2168 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2169 return false;
2170 // Otherwise we have r+r or r+i.
2171 break;
2172 case 2:
2173 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2174 return false;
2175 // Allow 2*r as r+r.
2176 break;
2177 default: // Don't allow n * r
2178 return false;
2179 }
2180
2181 return true;
2182}
2183
2184//===----------------------------------------------------------------------===//
2185// Stack Protector
2186//===----------------------------------------------------------------------===//
2187
2188// For OpenBSD return its special guard variable. Otherwise return nullptr,
2189// so that SelectionDAG handle SSP.
2190Value *
2191TargetLoweringBase::getIRStackGuard(IRBuilderBase &IRB,
2192 const LibcallLoweringInfo &Libcalls) const {
2193 RTLIB::LibcallImpl GuardLocalImpl =
2194 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2195 if (GuardLocalImpl != RTLIB::impl___guard_local)
2196 return nullptr;
2197
2198 Module &M = *IRB.getModule();
2199 const DataLayout &DL = M.getDataLayout();
2200 PointerType *PtrTy =
2201 PointerType::get(C&: M.getContext(), AddressSpace: DL.getDefaultGlobalsAddressSpace());
2202 GlobalVariable *G =
2203 M.getOrInsertGlobal(Name: getLibcallImplName(Call: GuardLocalImpl), Ty: PtrTy);
2204 G->setVisibility(GlobalValue::HiddenVisibility);
2205 return G;
2206}
2207
2208// Currently only support "standard" __stack_chk_guard.
2209// TODO: add LOAD_STACK_GUARD support.
2210void TargetLoweringBase::insertSSPDeclarations(
2211 Module &M, const LibcallLoweringInfo &Libcalls) const {
2212 RTLIB::LibcallImpl StackGuardImpl =
2213 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2214 if (StackGuardImpl == RTLIB::Unsupported)
2215 return;
2216
2217 StringRef StackGuardVarName = getLibcallImplName(Call: StackGuardImpl);
2218 M.getOrInsertGlobal(
2219 Name: StackGuardVarName, Ty: PointerType::getUnqual(C&: M.getContext()), CreateGlobalCallback: [=, &M]() {
2220 auto *GV = new GlobalVariable(M, PointerType::getUnqual(C&: M.getContext()),
2221 false, GlobalVariable::ExternalLinkage,
2222 nullptr, StackGuardVarName);
2223
2224 // FreeBSD has "__stack_chk_guard" defined externally on libc.so
2225 if (M.getDirectAccessExternalData() &&
2226 !M.getTargetTriple().isOSCygMing() &&
2227 !(M.getTargetTriple().isPPC64() &&
2228 M.getTargetTriple().isOSFreeBSD()) &&
2229 (!M.getTargetTriple().isOSDarwin() ||
2230 TM.getRelocationModel() == Reloc::Static))
2231 GV->setDSOLocal(true);
2232
2233 return GV;
2234 });
2235}
2236
2237// Currently only support "standard" __stack_chk_guard.
2238// TODO: add LOAD_STACK_GUARD support.
2239Value *TargetLoweringBase::getSDagStackGuard(
2240 const Module &M, const LibcallLoweringInfo &Libcalls) const {
2241 RTLIB::LibcallImpl GuardVarImpl =
2242 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2243 if (GuardVarImpl == RTLIB::Unsupported)
2244 return nullptr;
2245 return M.getNamedValue(Name: getLibcallImplName(Call: GuardVarImpl));
2246}
2247
2248Function *TargetLoweringBase::getSSPStackGuardCheck(
2249 const Module &M, const LibcallLoweringInfo &Libcalls) const {
2250 // MSVC CRT has a function to validate security cookie.
2251 RTLIB::LibcallImpl SecurityCheckCookieLibcall =
2252 Libcalls.getLibcallImpl(Call: RTLIB::SECURITY_CHECK_COOKIE);
2253 if (SecurityCheckCookieLibcall != RTLIB::Unsupported)
2254 return M.getFunction(Name: getLibcallImplName(Call: SecurityCheckCookieLibcall));
2255 return nullptr;
2256}
2257
2258unsigned TargetLoweringBase::getMinimumJumpTableEntries() const {
2259 return MinimumJumpTableEntries;
2260}
2261
2262void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) {
2263 MinimumJumpTableEntries = Val;
2264}
2265
2266unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
2267 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
2268}
2269
2270unsigned TargetLoweringBase::getMaximumJumpTableSize() const {
2271 return MaximumJumpTableSize;
2272}
2273
2274void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {
2275 MaximumJumpTableSize = Val;
2276}
2277
2278bool TargetLoweringBase::isJumpTableRelative() const {
2279 return getTargetMachine().isPositionIndependent();
2280}
2281
2282unsigned TargetLoweringBase::getMinimumBitTestCmps() const {
2283 return MinimumBitTestCmps;
2284}
2285
2286void TargetLoweringBase::setMinimumBitTestCmps(unsigned Val) {
2287 MinimumBitTestCmps = Val;
2288}
2289
2290Align TargetLoweringBase::getPrefLoopAlignment(
2291 MachineLoop *ML, const MachineBasicBlock *BlockToAlign) const {
2292 if (TM.Options.LoopAlignment)
2293 return Align(TM.Options.LoopAlignment);
2294 return PrefLoopAlignment;
2295}
2296
2297unsigned TargetLoweringBase::getMaxPermittedBytesForAlignment(
2298 MachineBasicBlock *MBB) const {
2299 return MaxBytesForAlignment;
2300}
2301
2302//===----------------------------------------------------------------------===//
2303// Reciprocal Estimates
2304//===----------------------------------------------------------------------===//
2305
2306/// Get the reciprocal estimate attribute string for a function that will
2307/// override the target defaults.
2308static StringRef getRecipEstimateForFunc(const Function &F) {
2309 return F.getFnAttribute(Kind: "reciprocal-estimates").getValueAsString();
2310}
2311
2312/// Construct a string for the given reciprocal operation of the given type.
2313/// This string should match the corresponding option to the front-end's
2314/// "-mrecip" flag assuming those strings have been passed through in an
2315/// attribute string. For example, "vec-divf" for a division of a vXf32.
2316static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2317 std::string Name = VT.isVector() ? "vec-" : "";
2318
2319 Name += IsSqrt ? "sqrt" : "div";
2320
2321 // TODO: Handle other float types?
2322 if (VT.getScalarType() == MVT::f64) {
2323 Name += "d";
2324 } else if (VT.getScalarType() == MVT::f16) {
2325 Name += "h";
2326 } else {
2327 assert(VT.getScalarType() == MVT::f32 &&
2328 "Unexpected FP type for reciprocal estimate");
2329 Name += "f";
2330 }
2331
2332 return Name;
2333}
2334
2335/// Return the character position and value (a single numeric character) of a
2336/// customized refinement operation in the input string if it exists. Return
2337/// false if there is no customized refinement step count.
2338static bool parseRefinementStep(StringRef In, size_t &Position,
2339 uint8_t &Value) {
2340 const char RefStepToken = ':';
2341 Position = In.find(C: RefStepToken);
2342 if (Position == StringRef::npos)
2343 return false;
2344
2345 StringRef RefStepString = In.substr(Start: Position + 1);
2346 // Allow exactly one numeric character for the additional refinement
2347 // step parameter.
2348 if (RefStepString.size() == 1) {
2349 char RefStepChar = RefStepString[0];
2350 if (isDigit(C: RefStepChar)) {
2351 Value = RefStepChar - '0';
2352 return true;
2353 }
2354 }
2355 report_fatal_error(reason: "Invalid refinement step for -recip.");
2356}
2357
2358/// For the input attribute string, return one of the ReciprocalEstimate enum
2359/// status values (enabled, disabled, or not specified) for this operation on
2360/// the specified data type.
2361static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2362 if (Override.empty())
2363 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2364
2365 SmallVector<StringRef, 4> OverrideVector;
2366 Override.split(A&: OverrideVector, Separator: ',');
2367 unsigned NumArgs = OverrideVector.size();
2368
2369 // Check if "all", "none", or "default" was specified.
2370 if (NumArgs == 1) {
2371 // Look for an optional setting of the number of refinement steps needed
2372 // for this type of reciprocal operation.
2373 size_t RefPos;
2374 uint8_t RefSteps;
2375 if (parseRefinementStep(In: Override, Position&: RefPos, Value&: RefSteps)) {
2376 // Split the string for further processing.
2377 Override = Override.substr(Start: 0, N: RefPos);
2378 }
2379
2380 // All reciprocal types are enabled.
2381 if (Override == "all")
2382 return TargetLoweringBase::ReciprocalEstimate::Enabled;
2383
2384 // All reciprocal types are disabled.
2385 if (Override == "none")
2386 return TargetLoweringBase::ReciprocalEstimate::Disabled;
2387
2388 // Target defaults for enablement are used.
2389 if (Override == "default")
2390 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2391 }
2392
2393 // The attribute string may omit the size suffix ('f'/'d').
2394 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2395 std::string VTNameNoSize = VTName;
2396 VTNameNoSize.pop_back();
2397 static const char DisabledPrefix = '!';
2398
2399 for (StringRef RecipType : OverrideVector) {
2400 size_t RefPos;
2401 uint8_t RefSteps;
2402 if (parseRefinementStep(In: RecipType, Position&: RefPos, Value&: RefSteps))
2403 RecipType = RecipType.substr(Start: 0, N: RefPos);
2404
2405 // Ignore the disablement token for string matching.
2406 bool IsDisabled = RecipType[0] == DisabledPrefix;
2407 if (IsDisabled)
2408 RecipType = RecipType.substr(Start: 1);
2409
2410 if (RecipType == VTName || RecipType == VTNameNoSize)
2411 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
2412 : TargetLoweringBase::ReciprocalEstimate::Enabled;
2413 }
2414
2415 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2416}
2417
2418/// For the input attribute string, return the customized refinement step count
2419/// for this operation on the specified data type. If the step count does not
2420/// exist, return the ReciprocalEstimate enum value for unspecified.
2421static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2422 if (Override.empty())
2423 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2424
2425 SmallVector<StringRef, 4> OverrideVector;
2426 Override.split(A&: OverrideVector, Separator: ',');
2427 unsigned NumArgs = OverrideVector.size();
2428
2429 // Check if "all", "default", or "none" was specified.
2430 if (NumArgs == 1) {
2431 // Look for an optional setting of the number of refinement steps needed
2432 // for this type of reciprocal operation.
2433 size_t RefPos;
2434 uint8_t RefSteps;
2435 if (!parseRefinementStep(In: Override, Position&: RefPos, Value&: RefSteps))
2436 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2437
2438 // Split the string for further processing.
2439 Override = Override.substr(Start: 0, N: RefPos);
2440 assert(Override != "none" &&
2441 "Disabled reciprocals, but specifed refinement steps?");
2442
2443 // If this is a general override, return the specified number of steps.
2444 if (Override == "all" || Override == "default")
2445 return RefSteps;
2446 }
2447
2448 // The attribute string may omit the size suffix ('f'/'d').
2449 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2450 std::string VTNameNoSize = VTName;
2451 VTNameNoSize.pop_back();
2452
2453 for (StringRef RecipType : OverrideVector) {
2454 size_t RefPos;
2455 uint8_t RefSteps;
2456 if (!parseRefinementStep(In: RecipType, Position&: RefPos, Value&: RefSteps))
2457 continue;
2458
2459 RecipType = RecipType.substr(Start: 0, N: RefPos);
2460 if (RecipType == VTName || RecipType == VTNameNoSize)
2461 return RefSteps;
2462 }
2463
2464 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2465}
2466
2467int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,
2468 const Function &F) const {
2469 return getOpEnabled(IsSqrt: true, VT, Override: getRecipEstimateForFunc(F));
2470}
2471
2472int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,
2473 const Function &F) const {
2474 return getOpEnabled(IsSqrt: false, VT, Override: getRecipEstimateForFunc(F));
2475}
2476
2477int TargetLoweringBase::getSqrtRefinementSteps(EVT VT,
2478 const Function &F) const {
2479 return getOpRefinementSteps(IsSqrt: true, VT, Override: getRecipEstimateForFunc(F));
2480}
2481
2482int TargetLoweringBase::getDivRefinementSteps(EVT VT, const Function &F) const {
2483 return getOpRefinementSteps(IsSqrt: false, VT, Override: getRecipEstimateForFunc(F));
2484}
2485
2486bool TargetLoweringBase::isLoadBitCastBeneficial(
2487 EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG,
2488 const MachineMemOperand &MMO) const {
2489 // Single-element vectors are scalarized, so we should generally avoid having
2490 // any memory operations on such types, as they would get scalarized too.
2491 if (LoadVT.isFixedLengthVector() && BitcastVT.isFixedLengthVector() &&
2492 BitcastVT.getVectorNumElements() == 1)
2493 return false;
2494
2495 // Don't do if we could do an indexed load on the original type, but not on
2496 // the new one.
2497 if (!LoadVT.isSimple() || !BitcastVT.isSimple())
2498 return true;
2499
2500 MVT LoadMVT = LoadVT.getSimpleVT();
2501
2502 // Don't bother doing this if it's just going to be promoted again later, as
2503 // doing so might interfere with other combines.
2504 if (getOperationAction(Op: ISD::LOAD, VT: LoadMVT) == Promote &&
2505 getTypeToPromoteTo(Op: ISD::LOAD, VT: LoadMVT) == BitcastVT.getSimpleVT())
2506 return false;
2507
2508 unsigned Fast = 0;
2509 return allowsMemoryAccess(Context&: *DAG.getContext(), DL: DAG.getDataLayout(), VT: BitcastVT,
2510 MMO, Fast: &Fast) &&
2511 Fast;
2512}
2513
2514void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
2515 MF.getRegInfo().freezeReservedRegs();
2516}
2517
2518MachineMemOperand::Flags TargetLoweringBase::getLoadMemOperandFlags(
2519 const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC,
2520 const TargetLibraryInfo *LibInfo, CodeGenOptLevel OptLevel) const {
2521 MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad;
2522 if (LI.isVolatile())
2523 Flags |= MachineMemOperand::MOVolatile;
2524
2525 if (LI.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2526 Flags |= MachineMemOperand::MONonTemporal;
2527
2528 if (LI.hasMetadata(KindID: LLVMContext::MD_invariant_load))
2529 Flags |= MachineMemOperand::MOInvariant;
2530
2531 // Dereferenceability analysis is expensive, skip at O0.
2532 if (OptLevel != CodeGenOptLevel::None &&
2533 isDereferenceableAndAlignedPointer(
2534 V: LI.getPointerOperand(), Ty: LI.getType(), Alignment: LI.getAlign(),
2535 Q: SimplifyQuery(DL, LibInfo, /*DT=*/nullptr, AC, &LI)))
2536 Flags |= MachineMemOperand::MODereferenceable;
2537
2538 Flags |= getTargetMMOFlags(I: LI);
2539 return Flags;
2540}
2541
2542MachineMemOperand::Flags
2543TargetLoweringBase::getStoreMemOperandFlags(const StoreInst &SI,
2544 const DataLayout &DL) const {
2545 MachineMemOperand::Flags Flags = MachineMemOperand::MOStore;
2546
2547 if (SI.isVolatile())
2548 Flags |= MachineMemOperand::MOVolatile;
2549
2550 if (SI.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2551 Flags |= MachineMemOperand::MONonTemporal;
2552
2553 // FIXME: Not preserving dereferenceable
2554 Flags |= getTargetMMOFlags(I: SI);
2555 return Flags;
2556}
2557
2558MachineMemOperand::Flags
2559TargetLoweringBase::getAtomicMemOperandFlags(const Instruction &AI,
2560 const DataLayout &DL) const {
2561 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
2562
2563 if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(Val: &AI)) {
2564 if (RMW->isVolatile())
2565 Flags |= MachineMemOperand::MOVolatile;
2566 } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(Val: &AI)) {
2567 if (CmpX->isVolatile())
2568 Flags |= MachineMemOperand::MOVolatile;
2569 } else
2570 llvm_unreachable("not an atomic instruction");
2571
2572 // FIXME: Not preserving dereferenceable
2573 Flags |= getTargetMMOFlags(I: AI);
2574 return Flags;
2575}
2576
2577MachineMemOperand::Flags TargetLoweringBase::getVPIntrinsicMemOperandFlags(
2578 const VPIntrinsic &VPIntrin) const {
2579 MachineMemOperand::Flags Flags = MachineMemOperand::MONone;
2580 Intrinsic::ID IntrinID = VPIntrin.getIntrinsicID();
2581
2582 switch (IntrinID) {
2583 default:
2584 llvm_unreachable("unexpected intrinsic. Existing code may be appropriate "
2585 "for it, but support must be explicitly enabled");
2586 case Intrinsic::vp_load:
2587 case Intrinsic::vp_gather:
2588 case Intrinsic::experimental_vp_strided_load:
2589 Flags = MachineMemOperand::MOLoad;
2590 break;
2591 case Intrinsic::vp_store:
2592 case Intrinsic::vp_scatter:
2593 case Intrinsic::experimental_vp_strided_store:
2594 Flags = MachineMemOperand::MOStore;
2595 break;
2596 }
2597
2598 if (VPIntrin.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2599 Flags |= MachineMemOperand::MONonTemporal;
2600
2601 Flags |= getTargetMMOFlags(I: VPIntrin);
2602 return Flags;
2603}
2604
2605Instruction *TargetLoweringBase::emitLeadingFence(IRBuilderBase &Builder,
2606 Instruction *Inst,
2607 AtomicOrdering Ord) const {
2608 if (isReleaseOrStronger(AO: Ord) && Inst->hasAtomicStore())
2609 return Builder.CreateFence(Ordering: Ord);
2610 else
2611 return nullptr;
2612}
2613
2614Instruction *TargetLoweringBase::emitTrailingFence(IRBuilderBase &Builder,
2615 Instruction *Inst,
2616 AtomicOrdering Ord) const {
2617 if (isAcquireOrStronger(AO: Ord))
2618 return Builder.CreateFence(Ordering: Ord);
2619 else
2620 return nullptr;
2621}
2622
2623//===----------------------------------------------------------------------===//
2624// GlobalISel Hooks
2625//===----------------------------------------------------------------------===//
2626
2627bool TargetLoweringBase::shouldLocalize(const MachineInstr &MI,
2628 const TargetTransformInfo *TTI) const {
2629 auto &MF = *MI.getMF();
2630 auto &MRI = MF.getRegInfo();
2631 // Assuming a spill and reload of a value has a cost of 1 instruction each,
2632 // this helper function computes the maximum number of uses we should consider
2633 // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2634 // break even in terms of code size when the original MI has 2 users vs
2635 // choosing to potentially spill. Any more than 2 users we we have a net code
2636 // size increase. This doesn't take into account register pressure though.
2637 auto maxUses = [](unsigned RematCost) {
2638 // A cost of 1 means remats are basically free.
2639 if (RematCost == 1)
2640 return std::numeric_limits<unsigned>::max();
2641 if (RematCost == 2)
2642 return 2U;
2643
2644 // Remat is too expensive, only sink if there's one user.
2645 if (RematCost > 2)
2646 return 1U;
2647 llvm_unreachable("Unexpected remat cost");
2648 };
2649
2650 switch (MI.getOpcode()) {
2651 default:
2652 return false;
2653 // Constants-like instructions should be close to their users.
2654 // We don't want long live-ranges for them.
2655 case TargetOpcode::G_CONSTANT:
2656 case TargetOpcode::G_FCONSTANT:
2657 case TargetOpcode::G_FRAME_INDEX:
2658 case TargetOpcode::G_INTTOPTR:
2659 return true;
2660 case TargetOpcode::G_GLOBAL_VALUE: {
2661 unsigned RematCost = TTI->getGISelRematGlobalCost();
2662 Register Reg = MI.getOperand(i: 0).getReg();
2663 unsigned MaxUses = maxUses(RematCost);
2664 if (MaxUses == UINT_MAX)
2665 return true; // Remats are "free" so always localize.
2666 return MRI.hasAtMostUserInstrs(Reg, MaxUsers: MaxUses);
2667 }
2668 }
2669}
2670