1//===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the TargetLoweringBase class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/ADT/BitVector.h"
14#include "llvm/ADT/STLExtras.h"
15#include "llvm/ADT/SmallVector.h"
16#include "llvm/ADT/StringExtras.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/Twine.h"
19#include "llvm/Analysis/Loads.h"
20#include "llvm/Analysis/TargetTransformInfo.h"
21#include "llvm/CodeGen/Analysis.h"
22#include "llvm/CodeGen/ISDOpcodes.h"
23#include "llvm/CodeGen/MachineBasicBlock.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineMemOperand.h"
29#include "llvm/CodeGen/MachineOperand.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RuntimeLibcallUtil.h"
32#include "llvm/CodeGen/StackMaps.h"
33#include "llvm/CodeGen/TargetLowering.h"
34#include "llvm/CodeGen/TargetOpcodes.h"
35#include "llvm/CodeGen/TargetRegisterInfo.h"
36#include "llvm/CodeGen/ValueTypes.h"
37#include "llvm/CodeGenTypes/MachineValueType.h"
38#include "llvm/IR/Attributes.h"
39#include "llvm/IR/CallingConv.h"
40#include "llvm/IR/DataLayout.h"
41#include "llvm/IR/DerivedTypes.h"
42#include "llvm/IR/Function.h"
43#include "llvm/IR/GlobalValue.h"
44#include "llvm/IR/GlobalVariable.h"
45#include "llvm/IR/IRBuilder.h"
46#include "llvm/IR/Module.h"
47#include "llvm/IR/Type.h"
48#include "llvm/Support/Casting.h"
49#include "llvm/Support/CommandLine.h"
50#include "llvm/Support/Compiler.h"
51#include "llvm/Support/ErrorHandling.h"
52#include "llvm/Support/MathExtras.h"
53#include "llvm/Target/TargetMachine.h"
54#include "llvm/Target/TargetOptions.h"
55#include "llvm/TargetParser/Triple.h"
56#include "llvm/Transforms/Utils/SizeOpts.h"
57#include <algorithm>
58#include <cassert>
59#include <cstdint>
60#include <cstring>
61#include <string>
62#include <tuple>
63#include <utility>
64
65using namespace llvm;
66
67static cl::opt<bool> JumpIsExpensiveOverride(
68 "jump-is-expensive", cl::init(Val: false),
69 cl::desc("Do not create extra branches to split comparison logic."),
70 cl::Hidden);
71
72static cl::opt<unsigned> MinimumJumpTableEntries
73 ("min-jump-table-entries", cl::init(Val: 4), cl::Hidden,
74 cl::desc("Set minimum number of entries to use a jump table."));
75
76static cl::opt<unsigned> MaximumJumpTableSize
77 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
78 cl::desc("Set maximum size of jump tables."));
79
80/// Minimum jump table density for normal functions.
81static cl::opt<unsigned>
82 JumpTableDensity("jump-table-density", cl::init(Val: 10), cl::Hidden,
83 cl::desc("Minimum density for building a jump table in "
84 "a normal function"));
85
86/// Minimum jump table density for -Os or -Oz functions.
87static cl::opt<unsigned> OptsizeJumpTableDensity(
88 "optsize-jump-table-density", cl::init(Val: 40), cl::Hidden,
89 cl::desc("Minimum density for building a jump table in "
90 "an optsize function"));
91
92static cl::opt<unsigned> MinimumBitTestCmpsOverride(
93 "min-bit-test-cmps", cl::init(Val: 2), cl::Hidden,
94 cl::desc("Set minimum of largest number of comparisons "
95 "to use bit test for switch."));
96
97static cl::opt<unsigned> MaxStoresPerMemsetOverride(
98 "max-store-memset", cl::init(Val: 0), cl::Hidden,
99 cl::desc("Override target's MaxStoresPerMemset and "
100 "MaxStoresPerMemsetOptSize. "
101 "Set to 0 to use the target default."));
102
103static cl::opt<unsigned> MaxStoresPerMemcpyOverride(
104 "max-store-memcpy", cl::init(Val: 0), cl::Hidden,
105 cl::desc("Override target's MaxStoresPerMemcpy and "
106 "MaxStoresPerMemcpyOptSize. "
107 "Set to 0 to use the target default."));
108
109static cl::opt<unsigned> MaxStoresPerMemmoveOverride(
110 "max-store-memmove", cl::init(Val: 0), cl::Hidden,
111 cl::desc("Override target's MaxStoresPerMemmove and "
112 "MaxStoresPerMemmoveOptSize. "
113 "Set to 0 to use the target default."));
114
115// FIXME: This option is only to test if the strict fp operation processed
116// correctly by preventing mutating strict fp operation to normal fp operation
117// during development. When the backend supports strict float operation, this
118// option will be meaningless.
119static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
120 cl::desc("Don't mutate strict-float node to a legalize node"),
121 cl::init(Val: false), cl::Hidden);
122
123LLVM_ABI RTLIB::Libcall RTLIB::getSHL(EVT VT) {
124 if (VT == MVT::i16)
125 return RTLIB::SHL_I16;
126 if (VT == MVT::i32)
127 return RTLIB::SHL_I32;
128 if (VT == MVT::i64)
129 return RTLIB::SHL_I64;
130 if (VT == MVT::i128)
131 return RTLIB::SHL_I128;
132
133 return RTLIB::UNKNOWN_LIBCALL;
134}
135
136LLVM_ABI RTLIB::Libcall RTLIB::getSRL(EVT VT) {
137 if (VT == MVT::i16)
138 return RTLIB::SRL_I16;
139 if (VT == MVT::i32)
140 return RTLIB::SRL_I32;
141 if (VT == MVT::i64)
142 return RTLIB::SRL_I64;
143 if (VT == MVT::i128)
144 return RTLIB::SRL_I128;
145
146 return RTLIB::UNKNOWN_LIBCALL;
147}
148
149LLVM_ABI RTLIB::Libcall RTLIB::getSRA(EVT VT) {
150 if (VT == MVT::i16)
151 return RTLIB::SRA_I16;
152 if (VT == MVT::i32)
153 return RTLIB::SRA_I32;
154 if (VT == MVT::i64)
155 return RTLIB::SRA_I64;
156 if (VT == MVT::i128)
157 return RTLIB::SRA_I128;
158
159 return RTLIB::UNKNOWN_LIBCALL;
160}
161
162LLVM_ABI RTLIB::Libcall RTLIB::getMUL(EVT VT) {
163 if (VT == MVT::i16)
164 return RTLIB::MUL_I16;
165 if (VT == MVT::i32)
166 return RTLIB::MUL_I32;
167 if (VT == MVT::i64)
168 return RTLIB::MUL_I64;
169 if (VT == MVT::i128)
170 return RTLIB::MUL_I128;
171 return RTLIB::UNKNOWN_LIBCALL;
172}
173
174LLVM_ABI RTLIB::Libcall RTLIB::getMULO(EVT VT) {
175 if (VT == MVT::i32)
176 return RTLIB::MULO_I32;
177 if (VT == MVT::i64)
178 return RTLIB::MULO_I64;
179 if (VT == MVT::i128)
180 return RTLIB::MULO_I128;
181 return RTLIB::UNKNOWN_LIBCALL;
182}
183
184LLVM_ABI RTLIB::Libcall RTLIB::getSDIV(EVT VT) {
185 if (VT == MVT::i16)
186 return RTLIB::SDIV_I16;
187 if (VT == MVT::i32)
188 return RTLIB::SDIV_I32;
189 if (VT == MVT::i64)
190 return RTLIB::SDIV_I64;
191 if (VT == MVT::i128)
192 return RTLIB::SDIV_I128;
193 return RTLIB::UNKNOWN_LIBCALL;
194}
195
196LLVM_ABI RTLIB::Libcall RTLIB::getUDIV(EVT VT) {
197 if (VT == MVT::i16)
198 return RTLIB::UDIV_I16;
199 if (VT == MVT::i32)
200 return RTLIB::UDIV_I32;
201 if (VT == MVT::i64)
202 return RTLIB::UDIV_I64;
203 if (VT == MVT::i128)
204 return RTLIB::UDIV_I128;
205 return RTLIB::UNKNOWN_LIBCALL;
206}
207
208LLVM_ABI RTLIB::Libcall RTLIB::getSREM(EVT VT) {
209 if (VT == MVT::i16)
210 return RTLIB::SREM_I16;
211 if (VT == MVT::i32)
212 return RTLIB::SREM_I32;
213 if (VT == MVT::i64)
214 return RTLIB::SREM_I64;
215 if (VT == MVT::i128)
216 return RTLIB::SREM_I128;
217 return RTLIB::UNKNOWN_LIBCALL;
218}
219
220LLVM_ABI RTLIB::Libcall RTLIB::getUREM(EVT VT) {
221 if (VT == MVT::i16)
222 return RTLIB::UREM_I16;
223 if (VT == MVT::i32)
224 return RTLIB::UREM_I32;
225 if (VT == MVT::i64)
226 return RTLIB::UREM_I64;
227 if (VT == MVT::i128)
228 return RTLIB::UREM_I128;
229 return RTLIB::UNKNOWN_LIBCALL;
230}
231
232LLVM_ABI RTLIB::Libcall RTLIB::getCTPOP(EVT VT) {
233 if (VT == MVT::i32)
234 return RTLIB::CTPOP_I32;
235 if (VT == MVT::i64)
236 return RTLIB::CTPOP_I64;
237 if (VT == MVT::i128)
238 return RTLIB::CTPOP_I128;
239 return RTLIB::UNKNOWN_LIBCALL;
240}
241
242/// GetFPLibCall - Helper to return the right libcall for the given floating
243/// point type, or UNKNOWN_LIBCALL if there is none.
244RTLIB::Libcall RTLIB::getFPLibCall(EVT VT,
245 RTLIB::Libcall Call_F32,
246 RTLIB::Libcall Call_F64,
247 RTLIB::Libcall Call_F80,
248 RTLIB::Libcall Call_F128,
249 RTLIB::Libcall Call_PPCF128) {
250 return
251 VT == MVT::f32 ? Call_F32 :
252 VT == MVT::f64 ? Call_F64 :
253 VT == MVT::f80 ? Call_F80 :
254 VT == MVT::f128 ? Call_F128 :
255 VT == MVT::ppcf128 ? Call_PPCF128 :
256 RTLIB::UNKNOWN_LIBCALL;
257}
258
259/// getFPEXT - Return the FPEXT_*_* value for the given types, or
260/// UNKNOWN_LIBCALL if there is none.
261RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
262 if (OpVT == MVT::f16) {
263 if (RetVT == MVT::f32)
264 return FPEXT_F16_F32;
265 if (RetVT == MVT::f64)
266 return FPEXT_F16_F64;
267 if (RetVT == MVT::f80)
268 return FPEXT_F16_F80;
269 if (RetVT == MVT::f128)
270 return FPEXT_F16_F128;
271 } else if (OpVT == MVT::f32) {
272 if (RetVT == MVT::f64)
273 return FPEXT_F32_F64;
274 if (RetVT == MVT::f128)
275 return FPEXT_F32_F128;
276 if (RetVT == MVT::ppcf128)
277 return FPEXT_F32_PPCF128;
278 } else if (OpVT == MVT::f64) {
279 if (RetVT == MVT::f128)
280 return FPEXT_F64_F128;
281 else if (RetVT == MVT::ppcf128)
282 return FPEXT_F64_PPCF128;
283 } else if (OpVT == MVT::f80) {
284 if (RetVT == MVT::f128)
285 return FPEXT_F80_F128;
286 } else if (OpVT == MVT::bf16) {
287 if (RetVT == MVT::f32)
288 return FPEXT_BF16_F32;
289 }
290
291 return UNKNOWN_LIBCALL;
292}
293
294/// getFPROUND - Return the FPROUND_*_* value for the given types, or
295/// UNKNOWN_LIBCALL if there is none.
296RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
297 if (RetVT == MVT::f16) {
298 if (OpVT == MVT::f32)
299 return FPROUND_F32_F16;
300 if (OpVT == MVT::f64)
301 return FPROUND_F64_F16;
302 if (OpVT == MVT::f80)
303 return FPROUND_F80_F16;
304 if (OpVT == MVT::f128)
305 return FPROUND_F128_F16;
306 if (OpVT == MVT::ppcf128)
307 return FPROUND_PPCF128_F16;
308 } else if (RetVT == MVT::bf16) {
309 if (OpVT == MVT::f32)
310 return FPROUND_F32_BF16;
311 if (OpVT == MVT::f64)
312 return FPROUND_F64_BF16;
313 if (OpVT == MVT::f80)
314 return FPROUND_F80_BF16;
315 if (OpVT == MVT::f128)
316 return FPROUND_F128_BF16;
317 } else if (RetVT == MVT::f32) {
318 if (OpVT == MVT::f64)
319 return FPROUND_F64_F32;
320 if (OpVT == MVT::f80)
321 return FPROUND_F80_F32;
322 if (OpVT == MVT::f128)
323 return FPROUND_F128_F32;
324 if (OpVT == MVT::ppcf128)
325 return FPROUND_PPCF128_F32;
326 } else if (RetVT == MVT::f64) {
327 if (OpVT == MVT::f80)
328 return FPROUND_F80_F64;
329 if (OpVT == MVT::f128)
330 return FPROUND_F128_F64;
331 if (OpVT == MVT::ppcf128)
332 return FPROUND_PPCF128_F64;
333 } else if (RetVT == MVT::f80) {
334 if (OpVT == MVT::f128)
335 return FPROUND_F128_F80;
336 }
337
338 return UNKNOWN_LIBCALL;
339}
340
341/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
342/// UNKNOWN_LIBCALL if there is none.
343RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
344 if (OpVT == MVT::f16) {
345 if (RetVT == MVT::i32)
346 return FPTOSINT_F16_I32;
347 if (RetVT == MVT::i64)
348 return FPTOSINT_F16_I64;
349 if (RetVT == MVT::i128)
350 return FPTOSINT_F16_I128;
351 } else if (OpVT == MVT::f32) {
352 if (RetVT == MVT::i32)
353 return FPTOSINT_F32_I32;
354 if (RetVT == MVT::i64)
355 return FPTOSINT_F32_I64;
356 if (RetVT == MVT::i128)
357 return FPTOSINT_F32_I128;
358 } else if (OpVT == MVT::f64) {
359 if (RetVT == MVT::i32)
360 return FPTOSINT_F64_I32;
361 if (RetVT == MVT::i64)
362 return FPTOSINT_F64_I64;
363 if (RetVT == MVT::i128)
364 return FPTOSINT_F64_I128;
365 } else if (OpVT == MVT::f80) {
366 if (RetVT == MVT::i32)
367 return FPTOSINT_F80_I32;
368 if (RetVT == MVT::i64)
369 return FPTOSINT_F80_I64;
370 if (RetVT == MVT::i128)
371 return FPTOSINT_F80_I128;
372 } else if (OpVT == MVT::f128) {
373 if (RetVT == MVT::i32)
374 return FPTOSINT_F128_I32;
375 if (RetVT == MVT::i64)
376 return FPTOSINT_F128_I64;
377 if (RetVT == MVT::i128)
378 return FPTOSINT_F128_I128;
379 } else if (OpVT == MVT::ppcf128) {
380 if (RetVT == MVT::i32)
381 return FPTOSINT_PPCF128_I32;
382 if (RetVT == MVT::i64)
383 return FPTOSINT_PPCF128_I64;
384 if (RetVT == MVT::i128)
385 return FPTOSINT_PPCF128_I128;
386 }
387 return UNKNOWN_LIBCALL;
388}
389
390/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
391/// UNKNOWN_LIBCALL if there is none.
392RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
393 if (OpVT == MVT::f16) {
394 if (RetVT == MVT::i32)
395 return FPTOUINT_F16_I32;
396 if (RetVT == MVT::i64)
397 return FPTOUINT_F16_I64;
398 if (RetVT == MVT::i128)
399 return FPTOUINT_F16_I128;
400 } else if (OpVT == MVT::f32) {
401 if (RetVT == MVT::i32)
402 return FPTOUINT_F32_I32;
403 if (RetVT == MVT::i64)
404 return FPTOUINT_F32_I64;
405 if (RetVT == MVT::i128)
406 return FPTOUINT_F32_I128;
407 } else if (OpVT == MVT::f64) {
408 if (RetVT == MVT::i32)
409 return FPTOUINT_F64_I32;
410 if (RetVT == MVT::i64)
411 return FPTOUINT_F64_I64;
412 if (RetVT == MVT::i128)
413 return FPTOUINT_F64_I128;
414 } else if (OpVT == MVT::f80) {
415 if (RetVT == MVT::i32)
416 return FPTOUINT_F80_I32;
417 if (RetVT == MVT::i64)
418 return FPTOUINT_F80_I64;
419 if (RetVT == MVT::i128)
420 return FPTOUINT_F80_I128;
421 } else if (OpVT == MVT::f128) {
422 if (RetVT == MVT::i32)
423 return FPTOUINT_F128_I32;
424 if (RetVT == MVT::i64)
425 return FPTOUINT_F128_I64;
426 if (RetVT == MVT::i128)
427 return FPTOUINT_F128_I128;
428 } else if (OpVT == MVT::ppcf128) {
429 if (RetVT == MVT::i32)
430 return FPTOUINT_PPCF128_I32;
431 if (RetVT == MVT::i64)
432 return FPTOUINT_PPCF128_I64;
433 if (RetVT == MVT::i128)
434 return FPTOUINT_PPCF128_I128;
435 }
436 return UNKNOWN_LIBCALL;
437}
438
439/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
440/// UNKNOWN_LIBCALL if there is none.
441RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
442 if (OpVT == MVT::i32) {
443 if (RetVT == MVT::f16)
444 return SINTTOFP_I32_F16;
445 if (RetVT == MVT::f32)
446 return SINTTOFP_I32_F32;
447 if (RetVT == MVT::f64)
448 return SINTTOFP_I32_F64;
449 if (RetVT == MVT::f80)
450 return SINTTOFP_I32_F80;
451 if (RetVT == MVT::f128)
452 return SINTTOFP_I32_F128;
453 if (RetVT == MVT::ppcf128)
454 return SINTTOFP_I32_PPCF128;
455 } else if (OpVT == MVT::i64) {
456 if (RetVT == MVT::bf16)
457 return SINTTOFP_I64_BF16;
458 if (RetVT == MVT::f16)
459 return SINTTOFP_I64_F16;
460 if (RetVT == MVT::f32)
461 return SINTTOFP_I64_F32;
462 if (RetVT == MVT::f64)
463 return SINTTOFP_I64_F64;
464 if (RetVT == MVT::f80)
465 return SINTTOFP_I64_F80;
466 if (RetVT == MVT::f128)
467 return SINTTOFP_I64_F128;
468 if (RetVT == MVT::ppcf128)
469 return SINTTOFP_I64_PPCF128;
470 } else if (OpVT == MVT::i128) {
471 if (RetVT == MVT::f16)
472 return SINTTOFP_I128_F16;
473 if (RetVT == MVT::f32)
474 return SINTTOFP_I128_F32;
475 if (RetVT == MVT::f64)
476 return SINTTOFP_I128_F64;
477 if (RetVT == MVT::f80)
478 return SINTTOFP_I128_F80;
479 if (RetVT == MVT::f128)
480 return SINTTOFP_I128_F128;
481 if (RetVT == MVT::ppcf128)
482 return SINTTOFP_I128_PPCF128;
483 }
484 return UNKNOWN_LIBCALL;
485}
486
487/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
488/// UNKNOWN_LIBCALL if there is none.
489RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
490 if (OpVT == MVT::i32) {
491 if (RetVT == MVT::f16)
492 return UINTTOFP_I32_F16;
493 if (RetVT == MVT::f32)
494 return UINTTOFP_I32_F32;
495 if (RetVT == MVT::f64)
496 return UINTTOFP_I32_F64;
497 if (RetVT == MVT::f80)
498 return UINTTOFP_I32_F80;
499 if (RetVT == MVT::f128)
500 return UINTTOFP_I32_F128;
501 if (RetVT == MVT::ppcf128)
502 return UINTTOFP_I32_PPCF128;
503 } else if (OpVT == MVT::i64) {
504 if (RetVT == MVT::bf16)
505 return UINTTOFP_I64_BF16;
506 if (RetVT == MVT::f16)
507 return UINTTOFP_I64_F16;
508 if (RetVT == MVT::f32)
509 return UINTTOFP_I64_F32;
510 if (RetVT == MVT::f64)
511 return UINTTOFP_I64_F64;
512 if (RetVT == MVT::f80)
513 return UINTTOFP_I64_F80;
514 if (RetVT == MVT::f128)
515 return UINTTOFP_I64_F128;
516 if (RetVT == MVT::ppcf128)
517 return UINTTOFP_I64_PPCF128;
518 } else if (OpVT == MVT::i128) {
519 if (RetVT == MVT::f16)
520 return UINTTOFP_I128_F16;
521 if (RetVT == MVT::f32)
522 return UINTTOFP_I128_F32;
523 if (RetVT == MVT::f64)
524 return UINTTOFP_I128_F64;
525 if (RetVT == MVT::f80)
526 return UINTTOFP_I128_F80;
527 if (RetVT == MVT::f128)
528 return UINTTOFP_I128_F128;
529 if (RetVT == MVT::ppcf128)
530 return UINTTOFP_I128_PPCF128;
531 }
532 return UNKNOWN_LIBCALL;
533}
534
535// The floating-point RTLIB::getXXX(EVT) selectors are generated from the
536// RuntimeLibcallFamily table in RuntimeLibcalls.td.
537#define GET_RUNTIME_LIBCALL_FP_SELECTORS
538#include "llvm/IR/RuntimeLibcalls.inc"
539
540RTLIB::Libcall RTLIB::getOutlineAtomicHelper(const Libcall (&LC)[5][4],
541 AtomicOrdering Order,
542 uint64_t MemSize) {
543 unsigned ModeN, ModelN;
544 switch (MemSize) {
545 case 1:
546 ModeN = 0;
547 break;
548 case 2:
549 ModeN = 1;
550 break;
551 case 4:
552 ModeN = 2;
553 break;
554 case 8:
555 ModeN = 3;
556 break;
557 case 16:
558 ModeN = 4;
559 break;
560 default:
561 return RTLIB::UNKNOWN_LIBCALL;
562 }
563
564 switch (Order) {
565 case AtomicOrdering::Monotonic:
566 ModelN = 0;
567 break;
568 case AtomicOrdering::Acquire:
569 ModelN = 1;
570 break;
571 case AtomicOrdering::Release:
572 ModelN = 2;
573 break;
574 case AtomicOrdering::AcquireRelease:
575 case AtomicOrdering::SequentiallyConsistent:
576 ModelN = 3;
577 break;
578 default:
579 return UNKNOWN_LIBCALL;
580 }
581
582 return LC[ModeN][ModelN];
583}
584
585RTLIB::Libcall RTLIB::getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order,
586 MVT VT) {
587 if (!VT.isScalarInteger())
588 return UNKNOWN_LIBCALL;
589 uint64_t MemSize = VT.getScalarSizeInBits() / 8;
590
591#define LCALLS(A, B) \
592 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
593#define LCALL5(A) \
594 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
595 switch (Opc) {
596 case ISD::ATOMIC_CMP_SWAP: {
597 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
598 return getOutlineAtomicHelper(LC, Order, MemSize);
599 }
600 case ISD::ATOMIC_SWAP: {
601 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};
602 return getOutlineAtomicHelper(LC, Order, MemSize);
603 }
604 case ISD::ATOMIC_LOAD_ADD: {
605 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};
606 return getOutlineAtomicHelper(LC, Order, MemSize);
607 }
608 case ISD::ATOMIC_LOAD_OR: {
609 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};
610 return getOutlineAtomicHelper(LC, Order, MemSize);
611 }
612 case ISD::ATOMIC_LOAD_CLR: {
613 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};
614 return getOutlineAtomicHelper(LC, Order, MemSize);
615 }
616 case ISD::ATOMIC_LOAD_XOR: {
617 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};
618 return getOutlineAtomicHelper(LC, Order, MemSize);
619 }
620 default:
621 return UNKNOWN_LIBCALL;
622 }
623#undef LCALLS
624#undef LCALL5
625}
626
627RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
628#define OP_TO_LIBCALL(Name, Enum) \
629 case Name: \
630 switch (VT.SimpleTy) { \
631 default: \
632 return UNKNOWN_LIBCALL; \
633 case MVT::i8: \
634 return Enum##_1; \
635 case MVT::i16: \
636 return Enum##_2; \
637 case MVT::i32: \
638 return Enum##_4; \
639 case MVT::i64: \
640 return Enum##_8; \
641 case MVT::i128: \
642 return Enum##_16; \
643 }
644
645 switch (Opc) {
646 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
647 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
648 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
649 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
650 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
651 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
652 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
653 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
654 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
655 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
656 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
657 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
658 }
659
660#undef OP_TO_LIBCALL
661
662 return UNKNOWN_LIBCALL;
663}
664
665RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
666 switch (ElementSize) {
667 case 1:
668 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
669 case 2:
670 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
671 case 4:
672 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
673 case 8:
674 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
675 case 16:
676 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
677 default:
678 return UNKNOWN_LIBCALL;
679 }
680}
681
682RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
683 switch (ElementSize) {
684 case 1:
685 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
686 case 2:
687 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
688 case 4:
689 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
690 case 8:
691 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
692 case 16:
693 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
694 default:
695 return UNKNOWN_LIBCALL;
696 }
697}
698
699RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {
700 switch (ElementSize) {
701 case 1:
702 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
703 case 2:
704 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
705 case 4:
706 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
707 case 8:
708 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
709 case 16:
710 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
711 default:
712 return UNKNOWN_LIBCALL;
713 }
714}
715
716/// NOTE: The TargetMachine owns TLOF.
717TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm,
718 const TargetSubtargetInfo &STI)
719 : TM(tm),
720 RuntimeLibcallInfo(TM.getTargetTriple(), TM.Options.ExceptionModel,
721 TM.getTargetTriple().getDefaultFloatABI(),
722 TM.getTargetTriple().getDefaultLongDoubleFormat(),
723 TM.Options.MCOptions.getABIName(), TM.Options.VecLib),
724 Libcalls(RuntimeLibcallInfo, [&STI](LibcallLoweringInfo &Info) {
725 STI.initLibcallLoweringInfo(Info);
726 }) {
727 initActions();
728
729 // Perform these initializations only once.
730 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove =
731 MaxLoadsPerMemcmp = 8;
732 MaxGluedStoresPerMemcpy = 0;
733 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize =
734 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4;
735 HasExtractBitsInsn = false;
736 JumpIsExpensive = JumpIsExpensiveOverride;
737 PredictableSelectIsExpensive = false;
738 EnableExtLdPromotion = false;
739 StackPointerRegisterToSaveRestore = 0;
740 BooleanContents = UndefinedBooleanContent;
741 BooleanFloatContents = UndefinedBooleanContent;
742 BooleanVectorContents = UndefinedBooleanContent;
743 SchedPreferenceInfo = Sched::ILP;
744 GatherAllAliasesMaxDepth = 18;
745 IsStrictFPEnabled = DisableStrictNodeMutation;
746 MaxBytesForAlignment = 0;
747 MaxAtomicSizeInBitsSupported = 0;
748
749 // Assume that even with libcalls, no target supports wider than 128 bit
750 // division.
751 MaxDivRemBitWidthSupported = 128;
752
753 MaxLargeFPConvertBitWidthSupported = 128;
754
755 MinCmpXchgSizeInBits = 0;
756 SupportsUnalignedAtomics = false;
757
758 MinimumBitTestCmps = MinimumBitTestCmpsOverride;
759}
760
761// Define the virtual destructor out-of-line to act as a key method to anchor
762// debug info (see coding standards).
763TargetLoweringBase::~TargetLoweringBase() = default;
764
765void TargetLoweringBase::initActions() {
766 // All operations default to being supported.
767 memset(s: OpActions, c: 0, n: sizeof(OpActions));
768 memset(s: LoadExtActions, c: 0, n: sizeof(LoadExtActions));
769 memset(s: AtomicLoadExtActions, c: 0, n: sizeof(AtomicLoadExtActions));
770 memset(s: TruncStoreActions, c: 0, n: sizeof(TruncStoreActions));
771 memset(s: IndexedModeActions, c: 0, n: sizeof(IndexedModeActions));
772 memset(s: CondCodeActions, c: 0, n: sizeof(CondCodeActions));
773 llvm::fill(Range&: RegClassForVT, Value: nullptr);
774 llvm::fill(Range&: TargetDAGCombineArray, Value: 0);
775
776 // Let extending atomic loads be unsupported by default.
777 for (MVT ValVT : MVT::all_valuetypes())
778 for (MVT MemVT : MVT::all_valuetypes())
779 setAtomicLoadExtAction(ExtTypes: {ISD::SEXTLOAD, ISD::ZEXTLOAD}, ValVT, MemVT,
780 Action: Expand);
781
782 // We're somewhat special casing MVT::i2 and MVT::i4. Ideally we want to
783 // remove this and targets should individually set these types if not legal.
784 for (ISD::NodeType NT : enum_seq(Begin: ISD::DELETED_NODE, End: ISD::BUILTIN_OP_END,
785 force_iteration_on_noniterable_enum)) {
786 for (MVT VT : {MVT::i2, MVT::i4})
787 OpActions[(unsigned)VT.SimpleTy][NT] = Expand;
788 }
789 for (MVT AVT : MVT::all_valuetypes()) {
790 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {
791 setTruncStoreAction(ValVT: AVT, MemVT: VT, Action: Expand);
792 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: AVT, MemVT: VT, Action: Expand);
793 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: AVT, MemVT: VT, Action: Expand);
794 }
795 }
796 for (unsigned IM = (unsigned)ISD::PRE_INC;
797 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
798 for (MVT VT : {MVT::i2, MVT::i4}) {
799 setIndexedLoadAction(IdxModes: IM, VT, Action: Expand);
800 setIndexedStoreAction(IdxModes: IM, VT, Action: Expand);
801 setIndexedMaskedLoadAction(IdxMode: IM, VT, Action: Expand);
802 setIndexedMaskedStoreAction(IdxMode: IM, VT, Action: Expand);
803 }
804 }
805
806 for (MVT VT : MVT::fp_valuetypes()) {
807 MVT IntVT = MVT::getIntegerVT(BitWidth: VT.getFixedSizeInBits());
808 if (IntVT.isValid()) {
809 setOperationAction(Op: ISD::ATOMIC_SWAP, VT, Action: Promote);
810 AddPromotedToType(Opc: ISD::ATOMIC_SWAP, OrigVT: VT, DestVT: IntVT);
811 }
812 }
813
814 // If f16 fma is not natively supported, the value must be promoted to an f64
815 // (and not to f32!) to prevent double rounding issues.
816 AddPromotedToType(Opc: ISD::FMA, OrigVT: MVT::f16, DestVT: MVT::f64);
817 AddPromotedToType(Opc: ISD::STRICT_FMA, OrigVT: MVT::f16, DestVT: MVT::f64);
818
819 // Set default actions for various operations.
820 for (MVT VT : MVT::all_valuetypes()) {
821 // Default all indexed load / store to expand.
822 for (unsigned IM = (unsigned)ISD::PRE_INC;
823 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
824 setIndexedLoadAction(IdxModes: IM, VT, Action: Expand);
825 setIndexedStoreAction(IdxModes: IM, VT, Action: Expand);
826 setIndexedMaskedLoadAction(IdxMode: IM, VT, Action: Expand);
827 setIndexedMaskedStoreAction(IdxMode: IM, VT, Action: Expand);
828 }
829
830 // Most backends expect to see the node which just returns the value loaded.
831 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Action: Expand);
832
833 // clang-format off
834 // These operations default to expand.
835 setOperationAction(Ops: {ISD::FGETSIGN, ISD::CONCAT_VECTORS,
836 ISD::FMINNUM, ISD::FMAXNUM,
837 ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
838 ISD::FMINIMUM, ISD::FMAXIMUM,
839 ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM,
840 ISD::FMAD, ISD::SMIN,
841 ISD::SMAX, ISD::UMIN,
842 ISD::UMAX, ISD::ABS,
843 ISD::FSHL, ISD::FSHR,
844 ISD::SADDSAT, ISD::UADDSAT,
845 ISD::SSUBSAT, ISD::USUBSAT,
846 ISD::SSHLSAT, ISD::USHLSAT,
847 ISD::SMULFIX, ISD::SMULFIXSAT,
848 ISD::UMULFIX, ISD::UMULFIXSAT,
849 ISD::SDIVFIX, ISD::SDIVFIXSAT,
850 ISD::UDIVFIX, ISD::UDIVFIXSAT,
851 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT,
852 ISD::IS_FPCLASS, ISD::FCBRT,
853 ISD::FLOG, ISD::FLOG2,
854 ISD::FLOG10, ISD::FEXP,
855 ISD::FEXP2, ISD::FEXP10,
856 ISD::FFLOOR, ISD::FNEARBYINT,
857 ISD::FCEIL, ISD::FRINT,
858 ISD::FTRUNC, ISD::FROUNDEVEN,
859 ISD::FTAN, ISD::FACOS,
860 ISD::FASIN, ISD::FATAN,
861 ISD::FCOSH, ISD::FSINH,
862 ISD::FTANH, ISD::FATAN2,
863 ISD::FMULADD, ISD::CONVERT_FROM_ARBITRARY_FP,
864 ISD::CONVERT_TO_ARBITRARY_FP,
865 ISD::PSEUDO_FMIN, ISD::PSEUDO_FMAX},
866 VT, Action: Expand);
867 // clang-format on
868
869 // Overflow operations default to expand
870 setOperationAction(Ops: {ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO,
871 ISD::SMULO, ISD::UMULO},
872 VT, Action: Expand);
873
874 // Carry-using overflow operations default to expand.
875 setOperationAction(Ops: {ISD::UADDO_CARRY, ISD::USUBO_CARRY, ISD::SETCCCARRY,
876 ISD::SADDO_CARRY, ISD::SSUBO_CARRY},
877 VT, Action: Expand);
878
879 // ADDC/ADDE/SUBC/SUBE default to expand.
880 setOperationAction(Ops: {ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT,
881 Action: Expand);
882
883 // [US]CMP default to expand
884 setOperationAction(Ops: {ISD::UCMP, ISD::SCMP}, VT, Action: Expand);
885
886 // Halving adds and subtracts
887 setOperationAction(Ops: {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS,
888 ISD::AVGCEILU, ISD::AVGSUBFLOORS, ISD::AVGSUBFLOORU},
889 VT, Action: Expand);
890
891 // Absolute difference
892 setOperationAction(Ops: {ISD::ABDS, ISD::ABDU}, VT, Action: Expand);
893
894 // Carry-less multiply
895 setOperationAction(Ops: {ISD::CLMUL, ISD::CLMULR, ISD::CLMULH}, VT, Action: Expand);
896
897 // Bit extract/deposit (compress/expand)
898 setOperationAction(Ops: {ISD::PEXT, ISD::PDEP}, VT, Action: Expand);
899
900 // Saturated trunc
901 setOperationAction(Op: ISD::TRUNCATE_SSAT_S, VT, Action: Expand);
902 setOperationAction(Op: ISD::TRUNCATE_SSAT_U, VT, Action: Expand);
903 setOperationAction(Op: ISD::TRUNCATE_USAT_U, VT, Action: Expand);
904
905 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
906 setOperationAction(Ops: {ISD::CTLZ_ZERO_POISON, ISD::CTTZ_ZERO_POISON}, VT,
907 Action: Expand);
908
909 // This defaults to Expand so it will be expanded to ABS by default.
910 setOperationAction(Op: ISD::ABS_MIN_POISON, VT, Action: Expand);
911 setOperationAction(Op: ISD::CTLS, VT, Action: Expand);
912
913 setOperationAction(Ops: {ISD::BITREVERSE, ISD::PARITY}, VT, Action: Expand);
914
915 // These library functions default to expand.
916 setOperationAction(Ops: {ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP,
917 ISD::FSINCOS, ISD::FSINCOSPI, ISD::FMODF},
918 VT, Action: Expand);
919
920 // These operations default to expand for vector types.
921 if (VT.isVector())
922 setOperationAction(Ops: {ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG,
923 ISD::ANY_EXTEND_VECTOR_INREG,
924 ISD::SIGN_EXTEND_VECTOR_INREG,
925 ISD::ZERO_EXTEND_VECTOR_INREG, ISD::SPLAT_VECTOR,
926 ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
927 VT, Action: Expand);
928
929 // Constrained floating-point operations default to expand.
930#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
931 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
932#include "llvm/IR/ConstrainedOps.def"
933 setOperationAction(Op: ISD::STRICT_PSEUDO_FMIN, VT, Action: Expand);
934 setOperationAction(Op: ISD::STRICT_PSEUDO_FMAX, VT, Action: Expand);
935
936 // For most targets @llvm.get.dynamic.area.offset just returns 0.
937 setOperationAction(Op: ISD::GET_DYNAMIC_AREA_OFFSET, VT, Action: Expand);
938
939 // Vector reduction default to expand.
940 setOperationAction(
941 Ops: {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD,
942 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR,
943 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN,
944 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX,
945 ISD::VECREDUCE_FMIN, ISD::VECREDUCE_FMAXIMUM, ISD::VECREDUCE_FMINIMUM,
946 ISD::VECREDUCE_FMAXIMUMNUM, ISD::VECREDUCE_FMINIMUMNUM,
947 ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_SEQ_FMUL},
948 VT, Action: Expand);
949
950 // Named vector shuffles default to expand.
951 setOperationAction(Ops: {ISD::VECTOR_SPLICE_LEFT, ISD::VECTOR_SPLICE_RIGHT}, VT,
952 Action: Expand);
953
954 // Only some target support these vector operations. Default them to Expand.
955 setOperationAction(Ops: {ISD::VECTOR_COMPRESS, ISD::VECTOR_MATCH}, VT, Action: Expand);
956 setOperationAction(Ops: {ISD::CTTZ_ELTS, ISD::CTTZ_ELTS_ZERO_POISON}, VT,
957 Action: Expand);
958 setOperationAction(Op: ISD::GET_ACTIVE_LANE_MASK, VT, Action: Expand);
959
960 // VP operations default to expand.
961#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \
962 setOperationAction(ISD::SDOPC, VT, Expand);
963#include "llvm/IR/VPIntrinsics.def"
964
965 // Masked vector extracts default to expand.
966 setOperationAction(Op: ISD::VECTOR_FIND_LAST_ACTIVE, VT, Action: Expand);
967
968 setOperationAction(Op: ISD::LOOP_DEPENDENCE_RAW_MASK, VT, Action: Expand);
969 setOperationAction(Op: ISD::LOOP_DEPENDENCE_WAR_MASK, VT, Action: Expand);
970
971 setOperationAction(Op: ISD::MASK_BEFOREFIRST, VT, Action: Expand);
972
973 // FP environment operations default to expand.
974 setOperationAction(Op: ISD::GET_FPENV, VT, Action: Expand);
975 setOperationAction(Op: ISD::SET_FPENV, VT, Action: Expand);
976 setOperationAction(Op: ISD::RESET_FPENV, VT, Action: Expand);
977
978 setOperationAction(Op: ISD::MSTORE, VT, Action: Expand);
979
980 setOperationAction(Op: ISD::MASKED_UDIV, VT, Action: Expand);
981 setOperationAction(Op: ISD::MASKED_SDIV, VT, Action: Expand);
982 setOperationAction(Op: ISD::MASKED_UREM, VT, Action: Expand);
983 setOperationAction(Op: ISD::MASKED_SREM, VT, Action: Expand);
984 }
985
986 // Most targets ignore the @llvm.prefetch intrinsic.
987 setOperationAction(Op: ISD::PREFETCH, VT: MVT::Other, Action: Expand);
988
989 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
990 setOperationAction(Op: ISD::READCYCLECOUNTER, VT: MVT::i64, Action: Expand);
991
992 // Most targets also ignore the @llvm.readsteadycounter intrinsic.
993 setOperationAction(Op: ISD::READSTEADYCOUNTER, VT: MVT::i64, Action: Expand);
994
995 // ConstantFP nodes default to expand. Targets can either change this to
996 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
997 // to optimize expansions for certain constants.
998 setOperationAction(Ops: ISD::ConstantFP,
999 VTs: {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},
1000 Action: Expand);
1001
1002 // Insert custom handling default for llvm.canonicalize.*.
1003 setOperationAction(Ops: ISD::FCANONICALIZE,
1004 VTs: {MVT::f16, MVT::f32, MVT::f64, MVT::f128}, Action: Expand);
1005
1006 // FIXME: Query RuntimeLibCalls to make the decision.
1007 setOperationAction(Ops: {ISD::LRINT, ISD::LLRINT, ISD::LROUND, ISD::LLROUND},
1008 VTs: {MVT::f32, MVT::f64, MVT::f128}, Action: LibCall);
1009
1010 setOperationAction(Ops: {ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH,
1011 ISD::FSINH, ISD::FTANH, ISD::FATAN2},
1012 VT: MVT::f16, Action: Promote);
1013 // Default ISD::TRAP to expand (which turns it into abort).
1014 setOperationAction(Op: ISD::TRAP, VT: MVT::Other, Action: Expand);
1015
1016 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
1017 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
1018 setOperationAction(Op: ISD::DEBUGTRAP, VT: MVT::Other, Action: Expand);
1019
1020 setOperationAction(Op: ISD::UBSANTRAP, VT: MVT::Other, Action: Expand);
1021
1022 setOperationAction(Op: ISD::GET_FPENV_MEM, VT: MVT::Other, Action: Expand);
1023 setOperationAction(Op: ISD::SET_FPENV_MEM, VT: MVT::Other, Action: Expand);
1024
1025 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
1026 setOperationAction(Op: ISD::GET_FPMODE, VT, Action: Expand);
1027 setOperationAction(Op: ISD::SET_FPMODE, VT, Action: Expand);
1028 }
1029 setOperationAction(Op: ISD::RESET_FPMODE, VT: MVT::Other, Action: Expand);
1030
1031 // This one by default will call __clear_cache unless the target
1032 // wants something different.
1033 setOperationAction(Op: ISD::CLEAR_CACHE, VT: MVT::Other, Action: LibCall);
1034
1035 // By default, STACKADDRESS nodes are expanded like STACKSAVE nodes.
1036 // On SPARC targets, custom lowering is required.
1037 setOperationAction(Op: ISD::STACKADDRESS, VT: MVT::Other, Action: Expand);
1038}
1039
1040MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL,
1041 EVT) const {
1042 return MVT::getIntegerVT(BitWidth: DL.getPointerSizeInBits(AS: 0));
1043}
1044
1045EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,
1046 const DataLayout &DL) const {
1047 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
1048 if (LHSTy.isVector())
1049 return LHSTy;
1050 MVT ShiftVT = getScalarShiftAmountTy(DL, LHSTy);
1051 // If any possible shift value won't fit in the prefered type, just use
1052 // something safe. Assume it will be legalized when the shift is expanded.
1053 if (ShiftVT.getSizeInBits() < Log2_32_Ceil(Value: LHSTy.getSizeInBits()))
1054 ShiftVT = MVT::i32;
1055 assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) &&
1056 "ShiftVT is still too small!");
1057 return ShiftVT;
1058}
1059
1060bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
1061 assert(isTypeLegal(VT));
1062 switch (Op) {
1063 default:
1064 return false;
1065 case ISD::SDIV:
1066 case ISD::UDIV:
1067 case ISD::SREM:
1068 case ISD::UREM:
1069 return true;
1070 }
1071}
1072
1073bool TargetLoweringBase::isFreeAddrSpaceCast(const DataLayout &DL,
1074 unsigned SrcAS,
1075 unsigned DestAS) const {
1076 return TM.isNoopAddrSpaceCast(DL, SrcAS, DestAS);
1077}
1078
1079unsigned TargetLoweringBase::getBitWidthForCttzElements(
1080 EVT RetVT, ElementCount EC, bool ZeroIsPoison,
1081 const ConstantRange *VScaleRange) const {
1082 // Find the smallest "sensible" element type to use for the expansion.
1083 ConstantRange CR(APInt(64, EC.getKnownMinValue()));
1084 if (EC.isScalable())
1085 CR = CR.umul_sat(Other: *VScaleRange);
1086
1087 if (ZeroIsPoison)
1088 CR = CR.subtract(CI: APInt(64, 1));
1089
1090 unsigned EltWidth = RetVT.getScalarSizeInBits();
1091 EltWidth = std::min(a: EltWidth, b: CR.getActiveBits());
1092 EltWidth = std::max(a: llvm::bit_ceil(Value: EltWidth), b: (unsigned)8);
1093
1094 return EltWidth;
1095}
1096
1097void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
1098 // If the command-line option was specified, ignore this request.
1099 if (!JumpIsExpensiveOverride.getNumOccurrences())
1100 JumpIsExpensive = isExpensive;
1101}
1102
1103TargetLoweringBase::LegalizeKind
1104TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
1105 // If this is a simple type, use the ComputeRegisterProp mechanism.
1106 if (VT.isSimple()) {
1107 MVT SVT = VT.getSimpleVT();
1108 assert((unsigned)SVT.SimpleTy < std::size(TransformToType));
1109 MVT NVT = TransformToType[SVT.SimpleTy];
1110 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(VT: SVT);
1111
1112 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
1113 LA == TypeSoftPromoteHalf ||
1114 (NVT.isVector() ||
1115 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
1116 "Promote may not follow Expand or Promote");
1117
1118 if (LA == TypeSplitVector)
1119 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
1120 if (LA == TypeScalarizeVector)
1121 return LegalizeKind(LA, SVT.getVectorElementType());
1122 return LegalizeKind(LA, NVT);
1123 }
1124
1125 // Handle Extended Scalar Types.
1126 if (!VT.isVector()) {
1127 assert(VT.isInteger() && "Float types must be simple");
1128 unsigned BitSize = VT.getSizeInBits();
1129 // First promote to a power-of-two size, then expand if necessary.
1130 if (BitSize < 8 || !isPowerOf2_32(Value: BitSize)) {
1131 EVT NVT = VT.getRoundIntegerType(Context);
1132 assert(NVT != VT && "Unable to round integer VT");
1133 LegalizeKind NextStep = getTypeConversion(Context, VT: NVT);
1134 // Avoid multi-step promotion.
1135 if (NextStep.first == TypePromoteInteger)
1136 return NextStep;
1137 // Return rounded integer type.
1138 return LegalizeKind(TypePromoteInteger, NVT);
1139 }
1140
1141 return LegalizeKind(TypeExpandInteger,
1142 EVT::getIntegerVT(Context, BitWidth: VT.getSizeInBits() / 2));
1143 }
1144
1145 // Handle vector types.
1146 ElementCount NumElts = VT.getVectorElementCount();
1147 EVT EltVT = VT.getVectorElementType();
1148
1149 // Vectors with only one element are always scalarized.
1150 if (NumElts.isScalar())
1151 return LegalizeKind(TypeScalarizeVector, EltVT);
1152
1153 // Try to widen vector elements until the element type is a power of two and
1154 // promote it to a legal type later on, for example:
1155 // <3 x i8> -> <4 x i8> -> <4 x i32>
1156 if (EltVT.isInteger()) {
1157 // Vectors with a number of elements that is not a power of two are always
1158 // widened, for example <3 x i8> -> <4 x i8>.
1159 if (!VT.isPow2VectorType()) {
1160 NumElts = NumElts.coefficientNextPowerOf2();
1161 EVT NVT = EVT::getVectorVT(Context, VT: EltVT, EC: NumElts);
1162 return LegalizeKind(TypeWidenVector, NVT);
1163 }
1164
1165 // Examine the element type.
1166 LegalizeKind LK = getTypeConversion(Context, VT: EltVT);
1167
1168 // If type is to be expanded, split the vector.
1169 // <4 x i140> -> <2 x i140>
1170 if (LK.first == TypeExpandInteger) {
1171 if (NumElts.isScalable() && NumElts.getKnownMinValue() == 1)
1172 return LegalizeKind(TypeScalarizeScalableVector, EltVT);
1173 return LegalizeKind(TypeSplitVector,
1174 VT.getHalfNumVectorElementsVT(Context));
1175 }
1176
1177 // Promote the integer element types until a legal vector type is found
1178 // or until the element integer type is too big. If a legal type was not
1179 // found, fallback to the usual mechanism of widening/splitting the
1180 // vector.
1181 EVT OldEltVT = EltVT;
1182 while (true) {
1183 // Increase the bitwidth of the element to the next pow-of-two
1184 // (which is greater than 8 bits).
1185 EltVT = EVT::getIntegerVT(Context, BitWidth: 1 + EltVT.getSizeInBits())
1186 .getRoundIntegerType(Context);
1187
1188 // Stop trying when getting a non-simple element type.
1189 // Note that vector elements may be greater than legal vector element
1190 // types. Example: X86 XMM registers hold 64bit element on 32bit
1191 // systems.
1192 if (!EltVT.isSimple())
1193 break;
1194
1195 // Build a new vector type and check if it is legal.
1196 MVT NVT = MVT::getVectorVT(VT: EltVT.getSimpleVT(), EC: NumElts);
1197 // Found a legal promoted vector type.
1198 if (NVT != MVT() && ValueTypeActions.getTypeAction(VT: NVT) == TypeLegal)
1199 return LegalizeKind(TypePromoteInteger,
1200 EVT::getVectorVT(Context, VT: EltVT, EC: NumElts));
1201 }
1202
1203 // Reset the type to the unexpanded type if we did not find a legal vector
1204 // type with a promoted vector element type.
1205 EltVT = OldEltVT;
1206 }
1207
1208 // Try to widen the vector until a legal type is found.
1209 // If there is no wider legal type, split the vector.
1210 while (true) {
1211 // Round up to the next power of 2.
1212 NumElts = NumElts.coefficientNextPowerOf2();
1213
1214 // If there is no simple vector type with this many elements then there
1215 // cannot be a larger legal vector type. Note that this assumes that
1216 // there are no skipped intermediate vector types in the simple types.
1217 if (!EltVT.isSimple())
1218 break;
1219 MVT LargerVector = MVT::getVectorVT(VT: EltVT.getSimpleVT(), EC: NumElts);
1220 if (LargerVector == MVT())
1221 break;
1222
1223 // If this type is legal then widen the vector.
1224 if (ValueTypeActions.getTypeAction(VT: LargerVector) == TypeLegal)
1225 return LegalizeKind(TypeWidenVector, LargerVector);
1226 }
1227
1228 // Widen odd vectors to next power of two.
1229 if (!VT.isPow2VectorType()) {
1230 EVT NVT = VT.getPow2VectorType(Context);
1231 return LegalizeKind(TypeWidenVector, NVT);
1232 }
1233
1234 if (VT.getVectorElementCount() == ElementCount::getScalable(MinVal: 1))
1235 return LegalizeKind(TypeScalarizeScalableVector, EltVT);
1236
1237 // Vectors with illegal element types are expanded.
1238 EVT NVT = EVT::getVectorVT(Context, VT: EltVT,
1239 EC: VT.getVectorElementCount().divideCoefficientBy(RHS: 2));
1240 return LegalizeKind(TypeSplitVector, NVT);
1241}
1242
1243unsigned TargetLoweringBase::getVectorTypeBreakdownMVT(
1244 MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) {
1245 // Figure out the right, legal destination reg to copy into.
1246 ElementCount EC = VT.getVectorElementCount();
1247 MVT EltTy = VT.getVectorElementType();
1248
1249 unsigned NumVectorRegs = 1;
1250
1251 // Scalable vectors cannot be scalarized, so splitting or widening is
1252 // required.
1253 if (VT.isScalableVector() && !isPowerOf2_32(Value: EC.getKnownMinValue()))
1254 llvm_unreachable(
1255 "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1256
1257 // FIXME: We don't support non-power-of-2-sized vectors for now.
1258 // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1259 if (!isPowerOf2_32(Value: EC.getKnownMinValue())) {
1260 // Split EC to unit size (scalable property is preserved).
1261 NumVectorRegs = EC.getKnownMinValue();
1262 EC = ElementCount::getFixed(MinVal: 1);
1263 }
1264
1265 // Divide the input until we get to a supported size. This will
1266 // always end up with an EC that represent a scalar or a scalable
1267 // scalar.
1268 while (EC.getKnownMinValue() > 1 &&
1269 !isTypeLegal(VT: MVT::getVectorVT(VT: EltTy, EC))) {
1270 EC = EC.divideCoefficientBy(RHS: 2);
1271 NumVectorRegs <<= 1;
1272 }
1273
1274 NumIntermediates = NumVectorRegs;
1275
1276 MVT NewVT = MVT::getVectorVT(VT: EltTy, EC);
1277 if (!isTypeLegal(VT: NewVT))
1278 NewVT = EltTy;
1279 IntermediateVT = NewVT;
1280
1281 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
1282
1283 // Convert sizes such as i33 to i64.
1284 LaneSizeInBits = llvm::bit_ceil(Value: LaneSizeInBits);
1285
1286 MVT DestVT = getCachedRegisterType(VT: NewVT);
1287 RegisterVT = DestVT;
1288 if (EVT(DestVT).bitsLT(VT: NewVT)) // Value is expanded, e.g. i64 -> i16.
1289 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1290
1291 // Otherwise, promotion or legal types use the same number of registers as
1292 // the vector decimated to the appropriate level.
1293 return NumVectorRegs;
1294}
1295
1296/// isLegalRC - Return true if the value types that can be represented by the
1297/// specified register class are all legal.
1298bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
1299 const TargetRegisterClass &RC) const {
1300 for (const auto *I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1301 if (isTypeLegal(VT: *I))
1302 return true;
1303 return false;
1304}
1305
1306/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1307/// sequence of memory operands that is recognized by PrologEpilogInserter.
1308MachineBasicBlock *
1309TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,
1310 MachineBasicBlock *MBB) const {
1311 MachineInstr *MI = &InitialMI;
1312 MachineFunction &MF = *MI->getMF();
1313 MachineFrameInfo &MFI = MF.getFrameInfo();
1314
1315 // We're handling multiple types of operands here:
1316 // PATCHPOINT MetaArgs - live-in, read only, direct
1317 // STATEPOINT Deopt Spill - live-through, read only, indirect
1318 // STATEPOINT Deopt Alloca - live-through, read only, direct
1319 // (We're currently conservative and mark the deopt slots read/write in
1320 // practice.)
1321 // STATEPOINT GC Spill - live-through, read/write, indirect
1322 // STATEPOINT GC Alloca - live-through, read/write, direct
1323 // The live-in vs live-through is handled already (the live through ones are
1324 // all stack slots), but we need to handle the different type of stackmap
1325 // operands and memory effects here.
1326
1327 if (llvm::none_of(Range: MI->operands(),
1328 P: [](MachineOperand &Operand) { return Operand.isFI(); }))
1329 return MBB;
1330
1331 MachineInstrBuilder MIB = BuildMI(MF, MIMD: MI->getDebugLoc(), MCID: MI->getDesc());
1332
1333 // Inherit previous memory operands.
1334 MIB.cloneMemRefs(OtherMI: *MI);
1335
1336 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1337 MachineOperand &MO = MI->getOperand(i);
1338 if (!MO.isFI()) {
1339 // Index of Def operand this Use it tied to.
1340 // Since Defs are coming before Uses, if Use is tied, then
1341 // index of Def must be smaller that index of that Use.
1342 // Also, Defs preserve their position in new MI.
1343 unsigned TiedTo = i;
1344 if (MO.isReg() && MO.isTied())
1345 TiedTo = MI->findTiedOperandIdx(OpIdx: i);
1346 MIB.add(MO);
1347 if (TiedTo < i)
1348 MIB->tieOperands(DefIdx: TiedTo, UseIdx: MIB->getNumOperands() - 1);
1349 continue;
1350 }
1351
1352 // foldMemoryOperand builds a new MI after replacing a single FI operand
1353 // with the canonical set of five x86 addressing-mode operands.
1354 int FI = MO.getIndex();
1355
1356 // Add frame index operands recognized by stackmaps.cpp
1357 if (MFI.isStatepointSpillSlotObjectIndex(ObjectIdx: FI)) {
1358 // indirect-mem-ref tag, size, #FI, offset.
1359 // Used for spills inserted by StatepointLowering. This codepath is not
1360 // used for patchpoints/stackmaps at all, for these spilling is done via
1361 // foldMemoryOperand callback only.
1362 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1363 MIB.addImm(Val: StackMaps::IndirectMemRefOp);
1364 MIB.addImm(Val: MFI.getObjectSize(ObjectIdx: FI));
1365 MIB.add(MO);
1366 MIB.addImm(Val: 0);
1367 } else {
1368 // direct-mem-ref tag, #FI, offset.
1369 // Used by patchpoint, and direct alloca arguments to statepoints
1370 MIB.addImm(Val: StackMaps::DirectMemRefOp);
1371 MIB.add(MO);
1372 MIB.addImm(Val: 0);
1373 }
1374
1375 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1376
1377 // Add a new memory operand for this FI.
1378 assert(MFI.getObjectOffset(FI) != -1);
1379
1380 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1381 // PATCHPOINT should be updated to do the same. (TODO)
1382 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1383 auto Flags = MachineMemOperand::MOLoad;
1384 MachineMemOperand *MMO = MF.getMachineMemOperand(
1385 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI), F: Flags,
1386 Size: MF.getDataLayout().getPointerSize(), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
1387 MIB->addMemOperand(MF, MO: MMO);
1388 }
1389 }
1390 MBB->insert(I: MachineBasicBlock::iterator(MI), MI: MIB);
1391 MI->eraseFromParent();
1392 return MBB;
1393}
1394
1395/// findRepresentativeClass - Return the largest legal super-reg register class
1396/// of the register class for the specified type and its associated "cost".
1397// This function is in TargetLowering because it uses RegClassForVT which would
1398// need to be moved to TargetRegisterInfo and would necessitate moving
1399// isTypeLegal over as well - a massive change that would just require
1400// TargetLowering having a TargetRegisterInfo class member that it would use.
1401std::pair<const TargetRegisterClass *, uint8_t>
1402TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1403 MVT VT) const {
1404 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1405 if (!RC)
1406 return std::make_pair(x&: RC, y: 0);
1407
1408 // Compute the set of all super-register classes.
1409 BitVector SuperRegRC(TRI->getNumRegClasses());
1410 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1411 SuperRegRC.setBitsInMask(Mask: RCI.getMask());
1412
1413 // Find the first legal register class with the largest spill size.
1414 const TargetRegisterClass *BestRC = RC;
1415 for (unsigned i : SuperRegRC.set_bits()) {
1416 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1417 // We want the largest possible spill size.
1418 if (TRI->getSpillSize(RC: *SuperRC) <= TRI->getSpillSize(RC: *BestRC))
1419 continue;
1420 if (!isLegalRC(TRI: *TRI, RC: *SuperRC))
1421 continue;
1422 BestRC = SuperRC;
1423 }
1424 return std::make_pair(x&: BestRC, y: 1);
1425}
1426
1427/// computeRegisterProperties - Once all of the register classes are added,
1428/// this allows us to compute derived properties we expose.
1429void TargetLoweringBase::computeRegisterProperties(
1430 const TargetRegisterInfo *TRI) {
1431 // Everything defaults to needing one register.
1432 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1433 NumRegistersForVT[i] = 1;
1434 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1435 }
1436 // ...except isVoid, which doesn't need any registers.
1437 NumRegistersForVT[MVT::isVoid] = 0;
1438
1439 // Find the largest integer register class.
1440 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1441 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1442 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1443
1444 // Every integer value type larger than this largest register takes twice as
1445 // many registers to represent as the previous ValueType.
1446 for (unsigned ExpandedReg = LargestIntReg + 1;
1447 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1448 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1449 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1450 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1451 ValueTypeActions.setTypeAction(VT: (MVT::SimpleValueType)ExpandedReg,
1452 Action: TypeExpandInteger);
1453 }
1454
1455 // Inspect all of the ValueType's smaller than the largest integer
1456 // register to see which ones need promotion.
1457 unsigned LegalIntReg = LargestIntReg;
1458 for (unsigned IntReg = LargestIntReg - 1;
1459 IntReg >= (unsigned)MVT::i1; --IntReg) {
1460 MVT IVT = (MVT::SimpleValueType)IntReg;
1461 if (isTypeLegal(VT: IVT)) {
1462 LegalIntReg = IntReg;
1463 } else {
1464 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1465 (MVT::SimpleValueType)LegalIntReg;
1466 ValueTypeActions.setTypeAction(VT: IVT, Action: TypePromoteInteger);
1467 }
1468 }
1469
1470 // ppcf128 type is really two f64's.
1471 if (!isTypeLegal(VT: MVT::ppcf128)) {
1472 if (isTypeLegal(VT: MVT::f64)) {
1473 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1474 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1475 TransformToType[MVT::ppcf128] = MVT::f64;
1476 ValueTypeActions.setTypeAction(VT: MVT::ppcf128, Action: TypeExpandFloat);
1477 } else {
1478 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1479 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1480 TransformToType[MVT::ppcf128] = MVT::i128;
1481 ValueTypeActions.setTypeAction(VT: MVT::ppcf128, Action: TypeSoftenFloat);
1482 }
1483 }
1484
1485 // Decide how to handle f128. If the target does not have native f128 support,
1486 // expand it to i128 and we will be generating soft float library calls.
1487 if (!isTypeLegal(VT: MVT::f128)) {
1488 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1489 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1490 TransformToType[MVT::f128] = MVT::i128;
1491 ValueTypeActions.setTypeAction(VT: MVT::f128, Action: TypeSoftenFloat);
1492 }
1493
1494 // Decide how to handle f80. If the target does not have native f80 support,
1495 // expand it to i96 and we will be generating soft float library calls.
1496 if (!isTypeLegal(VT: MVT::f80)) {
1497 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];
1498 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];
1499 TransformToType[MVT::f80] = MVT::i32;
1500 ValueTypeActions.setTypeAction(VT: MVT::f80, Action: TypeSoftenFloat);
1501 }
1502
1503 // Decide how to handle f64. If the target does not have native f64 support,
1504 // expand it to i64 and we will be generating soft float library calls.
1505 if (!isTypeLegal(VT: MVT::f64)) {
1506 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1507 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1508 TransformToType[MVT::f64] = MVT::i64;
1509 ValueTypeActions.setTypeAction(VT: MVT::f64, Action: TypeSoftenFloat);
1510 }
1511
1512 // Decide how to handle f32. If the target does not have native f32 support,
1513 // expand it to i32 and we will be generating soft float library calls.
1514 if (!isTypeLegal(VT: MVT::f32)) {
1515 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1516 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1517 TransformToType[MVT::f32] = MVT::i32;
1518 ValueTypeActions.setTypeAction(VT: MVT::f32, Action: TypeSoftenFloat);
1519 }
1520
1521 // Decide how to handle f16. If the target does not have native f16 support,
1522 // promote it to f32, because there are no f16 library calls (except for
1523 // conversions).
1524 if (!isTypeLegal(VT: MVT::f16)) {
1525 // Allow targets to control how we legalize half.
1526 bool UseFPRegsForHalfType = useFPRegsForHalfType();
1527
1528 if (!UseFPRegsForHalfType) {
1529 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1530 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1531 } else {
1532 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1533 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1534 }
1535 TransformToType[MVT::f16] = MVT::f32;
1536 ValueTypeActions.setTypeAction(VT: MVT::f16, Action: TypeSoftPromoteHalf);
1537 }
1538
1539 // Decide how to handle bf16. If the target does not have native bf16 support,
1540 // promote it to f32, because there are no bf16 library calls (except for
1541 // converting from f32 to bf16).
1542 if (!isTypeLegal(VT: MVT::bf16)) {
1543 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];
1544 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];
1545 TransformToType[MVT::bf16] = MVT::f32;
1546 ValueTypeActions.setTypeAction(VT: MVT::bf16, Action: TypeSoftPromoteHalf);
1547 }
1548
1549 // Loop over all of the vector value types to see which need transformations.
1550 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1551 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1552 MVT VT = (MVT::SimpleValueType) i;
1553 if (isTypeLegal(VT))
1554 continue;
1555
1556 MVT EltVT = VT.getVectorElementType();
1557 ElementCount EC = VT.getVectorElementCount();
1558 bool IsLegalWiderType = false;
1559 bool IsScalable = VT.isScalableVector();
1560 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1561 switch (PreferredAction) {
1562 case TypePromoteInteger: {
1563 MVT::SimpleValueType EndVT = IsScalable ?
1564 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :
1565 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;
1566 // Try to promote the elements of integer vectors. If no legal
1567 // promotion was found, fall through to the widen-vector method.
1568 for (unsigned nVT = i + 1;
1569 (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1570 MVT SVT = (MVT::SimpleValueType) nVT;
1571 // Promote vectors of integers to vectors with the same number
1572 // of elements, with a wider element type.
1573 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1574 SVT.getVectorElementCount() == EC && isTypeLegal(VT: SVT)) {
1575 TransformToType[i] = SVT;
1576 RegisterTypeForVT[i] = SVT;
1577 NumRegistersForVT[i] = 1;
1578 ValueTypeActions.setTypeAction(VT, Action: TypePromoteInteger);
1579 IsLegalWiderType = true;
1580 break;
1581 }
1582 }
1583 if (IsLegalWiderType)
1584 break;
1585 [[fallthrough]];
1586 }
1587
1588 case TypeWidenVector:
1589 if (isPowerOf2_32(Value: EC.getKnownMinValue())) {
1590 // Try to widen the vector.
1591 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1592 MVT SVT = (MVT::SimpleValueType) nVT;
1593 if (SVT.getVectorElementType() == EltVT &&
1594 SVT.isScalableVector() == IsScalable &&
1595 SVT.getVectorElementCount().getKnownMinValue() >
1596 EC.getKnownMinValue() &&
1597 isTypeLegal(VT: SVT)) {
1598 TransformToType[i] = SVT;
1599 RegisterTypeForVT[i] = SVT;
1600 NumRegistersForVT[i] = 1;
1601 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1602 IsLegalWiderType = true;
1603 break;
1604 }
1605 }
1606 if (IsLegalWiderType)
1607 break;
1608 } else {
1609 // Only widen to the next power of 2 to keep consistency with EVT.
1610 MVT NVT = VT.getPow2VectorType();
1611 if (isTypeLegal(VT: NVT)) {
1612 TransformToType[i] = NVT;
1613 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1614 RegisterTypeForVT[i] = NVT;
1615 NumRegistersForVT[i] = 1;
1616 break;
1617 }
1618 }
1619 [[fallthrough]];
1620
1621 case TypeSplitVector:
1622 case TypeScalarizeVector: {
1623 MVT IntermediateVT;
1624 MVT RegisterVT;
1625 unsigned NumIntermediates;
1626 unsigned NumRegisters = getVectorTypeBreakdownMVT(
1627 VT, IntermediateVT, NumIntermediates, RegisterVT);
1628 NumRegistersForVT[i] = NumRegisters;
1629 assert(NumRegistersForVT[i] == NumRegisters &&
1630 "NumRegistersForVT size cannot represent NumRegisters!");
1631 RegisterTypeForVT[i] = RegisterVT;
1632
1633 MVT NVT = VT.getPow2VectorType();
1634 if (NVT == VT) {
1635 // Type is already a power of 2. The default action is to split.
1636 TransformToType[i] = MVT::Other;
1637 if (PreferredAction == TypeScalarizeVector)
1638 ValueTypeActions.setTypeAction(VT, Action: TypeScalarizeVector);
1639 else if (PreferredAction == TypeSplitVector)
1640 ValueTypeActions.setTypeAction(VT, Action: TypeSplitVector);
1641 else if (EC.getKnownMinValue() > 1)
1642 ValueTypeActions.setTypeAction(VT, Action: TypeSplitVector);
1643 else
1644 ValueTypeActions.setTypeAction(VT, Action: EC.isScalable()
1645 ? TypeScalarizeScalableVector
1646 : TypeScalarizeVector);
1647 } else {
1648 TransformToType[i] = NVT;
1649 ValueTypeActions.setTypeAction(VT, Action: TypeWidenVector);
1650 }
1651 break;
1652 }
1653 default:
1654 llvm_unreachable("Unknown vector legalization action!");
1655 }
1656 }
1657
1658 // Determine the 'representative' register class for each value type.
1659 // An representative register class is the largest (meaning one which is
1660 // not a sub-register class / subreg register class) legal register class for
1661 // a group of value types. For example, on i386, i8, i16, and i32
1662 // representative would be GR32; while on x86_64 it's GR64.
1663 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1664 const TargetRegisterClass* RRC;
1665 uint8_t Cost;
1666 std::tie(args&: RRC, args&: Cost) = findRepresentativeClass(TRI, VT: (MVT::SimpleValueType)i);
1667 RepRegClassForVT[i] = RRC;
1668 RepRegClassCostForVT[i] = Cost;
1669 }
1670
1671 // Compute minimum known-legal store size.
1672 MaximumLegalStoreInBits = 0;
1673 for (MVT VT : MVT::all_valuetypes())
1674 if (VT != MVT::Other && isTypeLegal(VT) &&
1675 VT.getSizeInBits().getKnownMinValue() >= MaximumLegalStoreInBits)
1676 MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinValue();
1677}
1678
1679EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1680 EVT VT) const {
1681 assert(!VT.isVector() && "No default SetCC type for vectors!");
1682 return getPointerTy(DL).SimpleTy;
1683}
1684
1685/// getVectorTypeBreakdown - Vector types are broken down into some number of
1686/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1687/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1688/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1689///
1690/// This method returns the number of registers needed, and the VT for each
1691/// register. It also returns the VT and quantity of the intermediate values
1692/// before they are promoted/expanded.
1693unsigned TargetLoweringBase::getVectorTypeBreakdownImpl(
1694 LLVMContext &Context, EVT VT, EVT &IntermediateVT,
1695 unsigned &NumIntermediates, MVT &RegisterVT, bool ForCallingConv) const {
1696 ElementCount EltCnt = VT.getVectorElementCount();
1697
1698 // If there is a wider vector type with the same element type as this one,
1699 // or a promoted vector type that has the same number of elements which
1700 // are wider, then we should convert to that legal vector type.
1701 // This handles things like <2 x float> -> <4 x float> and
1702 // <4 x i1> -> <4 x i32>.
1703 LegalizeTypeAction TA = getTypeAction(Context, VT);
1704 if (!EltCnt.isScalar() &&
1705 (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1706 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1707 if (isTypeLegal(VT: RegisterEVT)) {
1708 IntermediateVT = RegisterEVT;
1709 RegisterVT = RegisterEVT.getSimpleVT();
1710 NumIntermediates = 1;
1711 return 1;
1712 }
1713 }
1714
1715 // Figure out the right, legal destination reg to copy into.
1716 EVT EltTy = VT.getVectorElementType();
1717
1718 unsigned NumVectorRegs = 1;
1719
1720 auto GetLegalVectorBreakdown = [&]() -> std::optional<unsigned> {
1721 LegalizeKind LK;
1722 EVT PartVT = VT;
1723 do {
1724 // Iterate until we've found a legal (part) type to hold VT.
1725 LK = getTypeConversion(Context, VT: PartVT);
1726 PartVT = LK.second;
1727 } while (LK.first != TypeLegal);
1728
1729 if (!PartVT.isVector())
1730 return std::nullopt;
1731
1732 assert(PartVT.isScalableVector() == VT.isScalableVector() &&
1733 "Vector legalization changed scalability");
1734 NumIntermediates =
1735 divideCeil(Numerator: VT.getVectorElementCount().getKnownMinValue(),
1736 Denominator: PartVT.getVectorElementCount().getKnownMinValue());
1737 IntermediateVT = PartVT;
1738 RegisterVT = getRegisterType(Context, VT: IntermediateVT);
1739 return NumIntermediates;
1740 };
1741
1742 // Scalable vectors cannot be scalarized, so handle the legalisation of the
1743 // types like done elsewhere in SelectionDAG.
1744 if (EltCnt.isScalable()) {
1745 if (std::optional<unsigned> NumRegs = GetLegalVectorBreakdown())
1746 return *NumRegs;
1747 report_fatal_error(reason: "Don't know how to legalize this scalable vector type");
1748 }
1749
1750 // FIXME: We don't generically support non-power-of-2-sized vectors for now.
1751 // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1752 if (!isPowerOf2_32(Value: EltCnt.getKnownMinValue())) {
1753 assert(VT.isFixedLengthVector() && "Expected a fixed-length vector VT");
1754 unsigned NumElts = EltCnt.getKnownMinValue();
1755
1756 if (!ForCallingConv && preferVectorizedNonPowerOfTwoTypeBreakdown())
1757 if (std::optional<unsigned> NumRegs = GetLegalVectorBreakdown())
1758 return *NumRegs;
1759
1760 // Fall back to scalars if there is no legal vector decomposition.
1761 NumVectorRegs = NumElts;
1762 EltCnt = ElementCount::getFixed(MinVal: 1);
1763 }
1764
1765 // Divide the input until we get to a supported size. This will always
1766 // end with a scalar if the target doesn't support vectors.
1767 while (EltCnt.getKnownMinValue() > 1 &&
1768 !isTypeLegal(VT: EVT::getVectorVT(Context, VT: EltTy, EC: EltCnt))) {
1769 EltCnt = EltCnt.divideCoefficientBy(RHS: 2);
1770 NumVectorRegs <<= 1;
1771 }
1772
1773 NumIntermediates = NumVectorRegs;
1774
1775 EVT NewVT = EVT::getVectorVT(Context, VT: EltTy, EC: EltCnt);
1776 if (!isTypeLegal(VT: NewVT))
1777 NewVT = EltTy;
1778 IntermediateVT = NewVT;
1779
1780 MVT DestVT = getRegisterType(Context, VT: NewVT);
1781 RegisterVT = DestVT;
1782
1783 if (EVT(DestVT).bitsLT(VT: NewVT)) { // Value is expanded, e.g. i64 -> i16.
1784 TypeSize NewVTSize = NewVT.getSizeInBits();
1785 // Convert sizes such as i33 to i64.
1786 if (!llvm::has_single_bit<uint32_t>(Value: NewVTSize.getKnownMinValue()))
1787 NewVTSize = NewVTSize.coefficientNextPowerOf2();
1788 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1789 }
1790
1791 // Otherwise, promotion or legal types use the same number of registers as
1792 // the vector decimated to the appropriate level.
1793 return NumVectorRegs;
1794}
1795
1796bool TargetLoweringBase::isSuitableForJumpTable(const SwitchInst *SI,
1797 uint64_t NumCases,
1798 uint64_t Range,
1799 ProfileSummaryInfo *PSI,
1800 BlockFrequencyInfo *BFI) const {
1801 // FIXME: This function check the maximum table size and density, but the
1802 // minimum size is not checked. It would be nice if the minimum size is
1803 // also combined within this function. Currently, the minimum size check is
1804 // performed in findJumpTable() in SelectionDAGBuiler and
1805 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1806 const bool OptForSize =
1807 llvm::shouldOptimizeForSize(BB: SI->getParent(), PSI, BFI);
1808 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1809 const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1810
1811 // Check whether the number of cases is small enough and
1812 // the range is dense enough for a jump table.
1813 return (OptForSize || Range <= MaxJumpTableSize) &&
1814 (NumCases * 100 >= Range * MinDensity);
1815}
1816
1817MVT TargetLoweringBase::getPreferredSwitchConditionType(LLVMContext &Context,
1818 EVT ConditionVT) const {
1819 return getRegisterType(Context, VT: ConditionVT);
1820}
1821
1822/// Get the EVTs and ArgFlags collections that represent the legalized return
1823/// type of the given function. This does not require a DAG or a return value,
1824/// and is suitable for use before any DAGs for the function are constructed.
1825/// TODO: Move this out of TargetLowering.cpp.
1826void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType,
1827 AttributeList attr,
1828 SmallVectorImpl<ISD::OutputArg> &Outs,
1829 const TargetLowering &TLI, const DataLayout &DL) {
1830 SmallVector<Type *, 4> Types;
1831 ComputeValueTypes(DL, Ty: ReturnType, Types);
1832 unsigned NumValues = Types.size();
1833 if (NumValues == 0) return;
1834
1835 for (Type *Ty : Types) {
1836 EVT VT = TLI.getValueType(DL, Ty);
1837 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1838
1839 if (attr.hasRetAttr(Kind: Attribute::SExt))
1840 ExtendKind = ISD::SIGN_EXTEND;
1841 else if (attr.hasRetAttr(Kind: Attribute::ZExt))
1842 ExtendKind = ISD::ZERO_EXTEND;
1843
1844 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1845 VT = TLI.getTypeForExtReturn(Context&: ReturnType->getContext(), VT, ExtendKind);
1846
1847 unsigned NumParts =
1848 TLI.getNumRegistersForCallingConv(Context&: ReturnType->getContext(), CC, VT);
1849 MVT PartVT =
1850 TLI.getRegisterTypeForCallingConv(Context&: ReturnType->getContext(), CC, VT);
1851
1852 // 'inreg' on function refers to return value
1853 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1854 if (attr.hasRetAttr(Kind: Attribute::InReg))
1855 Flags.setInReg();
1856
1857 // Propagate extension type if any
1858 if (attr.hasRetAttr(Kind: Attribute::SExt))
1859 Flags.setSExt();
1860 else if (attr.hasRetAttr(Kind: Attribute::ZExt))
1861 Flags.setZExt();
1862
1863 for (unsigned i = 0; i < NumParts; ++i)
1864 Outs.push_back(Elt: ISD::OutputArg(Flags, PartVT, VT, Ty, 0, 0));
1865 }
1866}
1867
1868Align TargetLoweringBase::getByValTypeAlignment(Type *Ty,
1869 const DataLayout &DL) const {
1870 return DL.getABITypeAlign(Ty);
1871}
1872
1873bool TargetLoweringBase::allowsMemoryAccessForAlignment(
1874 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1875 Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const {
1876 // Check if the specified alignment is sufficient based on the data layout.
1877 // TODO: While using the data layout works in practice, a better solution
1878 // would be to implement this check directly (make this a virtual function).
1879 // For example, the ABI alignment may change based on software platform while
1880 // this function should only be affected by hardware implementation.
1881 Type *Ty = VT.getTypeForEVT(Context);
1882 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {
1883 // Assume that an access that meets the ABI-specified alignment is fast.
1884 if (Fast != nullptr)
1885 *Fast = 1;
1886 return true;
1887 }
1888
1889 // This is a misaligned access.
1890 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1891}
1892
1893bool TargetLoweringBase::allowsMemoryAccessForAlignment(
1894 LLVMContext &Context, const DataLayout &DL, EVT VT,
1895 const MachineMemOperand &MMO, unsigned *Fast) const {
1896 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace: MMO.getAddrSpace(),
1897 Alignment: MMO.getAlign(), Flags: MMO.getFlags(), Fast);
1898}
1899
1900bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1901 const DataLayout &DL, EVT VT,
1902 unsigned AddrSpace, Align Alignment,
1903 MachineMemOperand::Flags Flags,
1904 unsigned *Fast) const {
1905 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1906 Flags, Fast);
1907}
1908
1909bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1910 const DataLayout &DL, EVT VT,
1911 const MachineMemOperand &MMO,
1912 unsigned *Fast) const {
1913 return allowsMemoryAccess(Context, DL, VT, AddrSpace: MMO.getAddrSpace(), Alignment: MMO.getAlign(),
1914 Flags: MMO.getFlags(), Fast);
1915}
1916
1917bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,
1918 const DataLayout &DL, LLT Ty,
1919 const MachineMemOperand &MMO,
1920 unsigned *Fast) const {
1921 EVT VT = getApproximateEVTForLLT(Ty, Ctx&: Context);
1922 return allowsMemoryAccess(Context, DL, VT, AddrSpace: MMO.getAddrSpace(), Alignment: MMO.getAlign(),
1923 Flags: MMO.getFlags(), Fast);
1924}
1925
1926unsigned TargetLoweringBase::getMaxStoresPerMemset(bool OptSize) const {
1927 if (MaxStoresPerMemsetOverride > 0)
1928 return MaxStoresPerMemsetOverride;
1929
1930 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1931}
1932
1933unsigned TargetLoweringBase::getMaxStoresPerMemcpy(bool OptSize) const {
1934 if (MaxStoresPerMemcpyOverride > 0)
1935 return MaxStoresPerMemcpyOverride;
1936
1937 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1938}
1939
1940unsigned TargetLoweringBase::getMaxStoresPerMemmove(bool OptSize) const {
1941 if (MaxStoresPerMemmoveOverride > 0)
1942 return MaxStoresPerMemmoveOverride;
1943
1944 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1945}
1946
1947//===----------------------------------------------------------------------===//
1948// TargetTransformInfo Helpers
1949//===----------------------------------------------------------------------===//
1950
1951int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1952 enum InstructionOpcodes {
1953#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1954#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1955#include "llvm/IR/Instruction.def"
1956 };
1957 // clang-format off
1958 switch (static_cast<InstructionOpcodes>(Opcode)) {
1959 case Ret: return 0;
1960 case UncondBr: return 0;
1961 case CondBr: return 0;
1962 case Switch: return 0;
1963 case IndirectBr: return 0;
1964 case Invoke: return 0;
1965 case CallBr: return 0;
1966 case Resume: return 0;
1967 case Unreachable: return 0;
1968 case CleanupRet: return 0;
1969 case CatchRet: return 0;
1970 case CatchPad: return 0;
1971 case CatchSwitch: return 0;
1972 case CleanupPad: return 0;
1973 case FNeg: return ISD::FNEG;
1974 case Add: return ISD::ADD;
1975 case FAdd: return ISD::FADD;
1976 case Sub: return ISD::SUB;
1977 case FSub: return ISD::FSUB;
1978 case Mul: return ISD::MUL;
1979 case FMul: return ISD::FMUL;
1980 case UDiv: return ISD::UDIV;
1981 case SDiv: return ISD::SDIV;
1982 case FDiv: return ISD::FDIV;
1983 case URem: return ISD::UREM;
1984 case SRem: return ISD::SREM;
1985 case FRem: return ISD::FREM;
1986 case Shl: return ISD::SHL;
1987 case LShr: return ISD::SRL;
1988 case AShr: return ISD::SRA;
1989 case And: return ISD::AND;
1990 case Or: return ISD::OR;
1991 case Xor: return ISD::XOR;
1992 case Alloca: return 0;
1993 case Load: return ISD::LOAD;
1994 case Store: return ISD::STORE;
1995 case GetElementPtr: return 0;
1996 case Fence: return 0;
1997 case AtomicCmpXchg: return 0;
1998 case AtomicRMW: return 0;
1999 case Trunc: return ISD::TRUNCATE;
2000 case ZExt: return ISD::ZERO_EXTEND;
2001 case SExt: return ISD::SIGN_EXTEND;
2002 case FPToUI: return ISD::FP_TO_UINT;
2003 case FPToSI: return ISD::FP_TO_SINT;
2004 case UIToFP: return ISD::UINT_TO_FP;
2005 case SIToFP: return ISD::SINT_TO_FP;
2006 case FPTrunc: return ISD::FP_ROUND;
2007 case FPExt: return ISD::FP_EXTEND;
2008 case PtrToAddr: return ISD::BITCAST;
2009 case PtrToInt: return ISD::BITCAST;
2010 case IntToPtr: return ISD::BITCAST;
2011 case BitCast: return ISD::BITCAST;
2012 case AddrSpaceCast: return ISD::ADDRSPACECAST;
2013 case ICmp: return ISD::SETCC;
2014 case FCmp: return ISD::SETCC;
2015 case PHI: return 0;
2016 case Call: return 0;
2017 case Select: return ISD::SELECT;
2018 case UserOp1: return 0;
2019 case UserOp2: return 0;
2020 case VAArg: return 0;
2021 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
2022 case InsertElement: return ISD::INSERT_VECTOR_ELT;
2023 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
2024 case ExtractValue: return ISD::MERGE_VALUES;
2025 case InsertValue: return ISD::MERGE_VALUES;
2026 case LandingPad: return 0;
2027 case Freeze: return ISD::FREEZE;
2028 case BitInsert: return 0;
2029 case BitExtract: return 0;
2030 }
2031 // clang-format on
2032 llvm_unreachable("Unknown instruction type encountered!");
2033}
2034
2035int TargetLoweringBase::IntrinsicIDToISD(Intrinsic::ID ID) const {
2036 switch (ID) {
2037 case Intrinsic::acos:
2038 return ISD::FACOS;
2039 case Intrinsic::asin:
2040 return ISD::FASIN;
2041 case Intrinsic::atan:
2042 return ISD::FATAN;
2043 case Intrinsic::cos:
2044 return ISD::FCOS;
2045 case Intrinsic::cosh:
2046 return ISD::FCOSH;
2047 case Intrinsic::exp:
2048 return ISD::FEXP;
2049 case Intrinsic::exp2:
2050 return ISD::FEXP2;
2051 case Intrinsic::exp10:
2052 return ISD::FEXP10;
2053 case Intrinsic::log:
2054 return ISD::FLOG;
2055 case Intrinsic::log2:
2056 return ISD::FLOG2;
2057 case Intrinsic::log10:
2058 return ISD::FLOG10;
2059 case Intrinsic::modf:
2060 return ISD::FMODF;
2061 case Intrinsic::sin:
2062 return ISD::FSIN;
2063 case Intrinsic::sincos:
2064 return ISD::FSINCOS;
2065 case Intrinsic::sincospi:
2066 return ISD::FSINCOSPI;
2067 case Intrinsic::sinh:
2068 return ISD::FSINH;
2069 case Intrinsic::tan:
2070 return ISD::FTAN;
2071 case Intrinsic::tanh:
2072 return ISD::FTANH;
2073 default:
2074 return ISD::DELETED_NODE;
2075 }
2076}
2077
2078Value *
2079TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilderBase &IRB,
2080 bool UseTLS) const {
2081 // compiler-rt provides a variable with a magic name. Targets that do not
2082 // link with compiler-rt may also provide such a variable.
2083 Module *M = IRB.getModule();
2084
2085 RTLIB::LibcallImpl UnsafeStackPtrImpl =
2086 Libcalls.getLibcallImpl(Call: RTLIB::SAFESTACK_UNSAFE_STACK_PTR);
2087 if (UnsafeStackPtrImpl == RTLIB::Unsupported)
2088 return nullptr;
2089
2090 StringRef UnsafeStackPtrVar =
2091 RTLIB::RuntimeLibcallsInfo::getLibcallImplName(CallImpl: UnsafeStackPtrImpl);
2092 auto UnsafeStackPtr =
2093 dyn_cast_or_null<GlobalVariable>(Val: M->getNamedValue(Name: UnsafeStackPtrVar));
2094
2095 const DataLayout &DL = M->getDataLayout();
2096 PointerType *StackPtrTy = DL.getAllocaPtrType(Ctx&: M->getContext());
2097
2098 if (!UnsafeStackPtr) {
2099 auto TLSModel = UseTLS ?
2100 GlobalValue::InitialExecTLSModel :
2101 GlobalValue::NotThreadLocal;
2102 // The global variable is not defined yet, define it ourselves.
2103 // We use the initial-exec TLS model because we do not support the
2104 // variable living anywhere other than in the main executable.
2105 UnsafeStackPtr = new GlobalVariable(
2106 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
2107 UnsafeStackPtrVar, nullptr, TLSModel);
2108 } else {
2109 // The variable exists, check its type and attributes.
2110 //
2111 // FIXME: Move to IR verifier.
2112 if (UnsafeStackPtr->getValueType() != StackPtrTy)
2113 report_fatal_error(reason: Twine(UnsafeStackPtrVar) + " must have void* type");
2114 if (UseTLS != UnsafeStackPtr->isThreadLocal())
2115 report_fatal_error(reason: Twine(UnsafeStackPtrVar) + " must " +
2116 (UseTLS ? "" : "not ") + "be thread-local");
2117 }
2118 return UnsafeStackPtr;
2119}
2120
2121Value *TargetLoweringBase::getSafeStackPointerLocation(
2122 IRBuilderBase &IRB, const LibcallLoweringInfo &Libcalls) const {
2123 RTLIB::LibcallImpl SafestackPointerAddressImpl =
2124 Libcalls.getLibcallImpl(Call: RTLIB::SAFESTACK_POINTER_ADDRESS);
2125 if (SafestackPointerAddressImpl == RTLIB::Unsupported)
2126 return getDefaultSafeStackPointerLocation(IRB, UseTLS: true);
2127
2128 Module *M = IRB.getModule();
2129 auto *PtrTy = PointerType::getUnqual(C&: M->getContext());
2130
2131 // Android provides a libc function to retrieve the address of the current
2132 // thread's unsafe stack pointer.
2133 FunctionCallee Fn =
2134 M->getOrInsertFunction(Name: RTLIB::RuntimeLibcallsInfo::getLibcallImplName(
2135 CallImpl: SafestackPointerAddressImpl),
2136 RetTy: PtrTy);
2137 return IRB.CreateCall(Callee: Fn);
2138}
2139
2140//===----------------------------------------------------------------------===//
2141// Loop Strength Reduction hooks
2142//===----------------------------------------------------------------------===//
2143
2144/// isLegalAddressingMode - Return true if the addressing mode represented
2145/// by AM is legal for this target, for a load/store of the specified type.
2146bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
2147 const AddrMode &AM, Type *Ty,
2148 unsigned AS, Instruction *I) const {
2149 // The default implementation of this implements a conservative RISCy, r+r and
2150 // r+i addr mode.
2151
2152 // Scalable offsets not supported
2153 if (AM.ScalableOffset)
2154 return false;
2155
2156 // Allows a sign-extended 16-bit immediate field.
2157 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2158 return false;
2159
2160 // No global is ever allowed as a base.
2161 if (AM.BaseGV)
2162 return false;
2163
2164 // Only support r+r,
2165 switch (AM.Scale) {
2166 case 0: // "r+i" or just "i", depending on HasBaseReg.
2167 break;
2168 case 1:
2169 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2170 return false;
2171 // Otherwise we have r+r or r+i.
2172 break;
2173 case 2:
2174 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2175 return false;
2176 // Allow 2*r as r+r.
2177 break;
2178 default: // Don't allow n * r
2179 return false;
2180 }
2181
2182 return true;
2183}
2184
2185//===----------------------------------------------------------------------===//
2186// Stack Protector
2187//===----------------------------------------------------------------------===//
2188
2189// For OpenBSD return its special guard variable. Otherwise return nullptr,
2190// so that SelectionDAG handle SSP.
2191Value *
2192TargetLoweringBase::getIRStackGuard(IRBuilderBase &IRB,
2193 const LibcallLoweringInfo &Libcalls) const {
2194 RTLIB::LibcallImpl GuardLocalImpl =
2195 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2196 if (GuardLocalImpl != RTLIB::impl___guard_local)
2197 return nullptr;
2198
2199 Module &M = *IRB.getModule();
2200 const DataLayout &DL = M.getDataLayout();
2201 PointerType *PtrTy =
2202 PointerType::get(C&: M.getContext(), AddressSpace: DL.getDefaultGlobalsAddressSpace());
2203 GlobalVariable *G =
2204 M.getOrInsertGlobal(Name: getLibcallImplName(Call: GuardLocalImpl), Ty: PtrTy);
2205 G->setVisibility(GlobalValue::HiddenVisibility);
2206 return G;
2207}
2208
2209// Currently only support "standard" __stack_chk_guard.
2210// TODO: add LOAD_STACK_GUARD support.
2211void TargetLoweringBase::insertSSPDeclarations(
2212 Module &M, const LibcallLoweringInfo &Libcalls) const {
2213 RTLIB::LibcallImpl StackGuardImpl =
2214 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2215 if (StackGuardImpl == RTLIB::Unsupported)
2216 return;
2217
2218 StringRef StackGuardVarName = getLibcallImplName(Call: StackGuardImpl);
2219 M.getOrInsertGlobal(
2220 Name: StackGuardVarName, Ty: PointerType::getUnqual(C&: M.getContext()), CreateGlobalCallback: [=, &M]() {
2221 auto *GV = new GlobalVariable(M, PointerType::getUnqual(C&: M.getContext()),
2222 false, GlobalVariable::ExternalLinkage,
2223 nullptr, StackGuardVarName);
2224
2225 // FreeBSD has "__stack_chk_guard" defined externally on libc.so
2226 if (M.getDirectAccessExternalData() &&
2227 !M.getTargetTriple().isOSCygMing() &&
2228 !(M.getTargetTriple().isPPC64() &&
2229 M.getTargetTriple().isOSFreeBSD()) &&
2230 (!M.getTargetTriple().isOSDarwin() ||
2231 TM.getRelocationModel() == Reloc::Static))
2232 GV->setDSOLocal(true);
2233
2234 return GV;
2235 });
2236}
2237
2238// Currently only support "standard" __stack_chk_guard.
2239// TODO: add LOAD_STACK_GUARD support.
2240Value *TargetLoweringBase::getSDagStackGuard(
2241 const Module &M, const LibcallLoweringInfo &Libcalls) const {
2242 RTLIB::LibcallImpl GuardVarImpl =
2243 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
2244 if (GuardVarImpl == RTLIB::Unsupported)
2245 return nullptr;
2246 return M.getNamedValue(Name: getLibcallImplName(Call: GuardVarImpl));
2247}
2248
2249Function *TargetLoweringBase::getSSPStackGuardCheck(
2250 const Module &M, const LibcallLoweringInfo &Libcalls) const {
2251 // MSVC CRT has a function to validate security cookie.
2252 RTLIB::LibcallImpl SecurityCheckCookieLibcall =
2253 Libcalls.getLibcallImpl(Call: RTLIB::SECURITY_CHECK_COOKIE);
2254 if (SecurityCheckCookieLibcall != RTLIB::Unsupported)
2255 return M.getFunction(Name: getLibcallImplName(Call: SecurityCheckCookieLibcall));
2256 return nullptr;
2257}
2258
2259unsigned TargetLoweringBase::getMinimumJumpTableEntries() const {
2260 return MinimumJumpTableEntries;
2261}
2262
2263void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) {
2264 MinimumJumpTableEntries = Val;
2265}
2266
2267unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
2268 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
2269}
2270
2271unsigned TargetLoweringBase::getMaximumJumpTableSize() const {
2272 return MaximumJumpTableSize;
2273}
2274
2275void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {
2276 MaximumJumpTableSize = Val;
2277}
2278
2279bool TargetLoweringBase::isJumpTableRelative() const {
2280 return getTargetMachine().isPositionIndependent();
2281}
2282
2283unsigned TargetLoweringBase::getMinimumBitTestCmps() const {
2284 return MinimumBitTestCmps;
2285}
2286
2287void TargetLoweringBase::setMinimumBitTestCmps(unsigned Val) {
2288 MinimumBitTestCmps = Val;
2289}
2290
2291Align TargetLoweringBase::getPrefLoopAlignment(
2292 MachineLoop *ML, const MachineBasicBlock *BlockToAlign) const {
2293 if (TM.Options.LoopAlignment)
2294 return Align(TM.Options.LoopAlignment);
2295 return PrefLoopAlignment;
2296}
2297
2298unsigned TargetLoweringBase::getMaxPermittedBytesForAlignment(
2299 MachineBasicBlock *MBB) const {
2300 return MaxBytesForAlignment;
2301}
2302
2303//===----------------------------------------------------------------------===//
2304// Reciprocal Estimates
2305//===----------------------------------------------------------------------===//
2306
2307/// Get the reciprocal estimate attribute string for a function that will
2308/// override the target defaults.
2309static StringRef getRecipEstimateForFunc(const Function &F) {
2310 return F.getFnAttribute(Kind: "reciprocal-estimates").getValueAsString();
2311}
2312
2313/// Construct a string for the given reciprocal operation of the given type.
2314/// This string should match the corresponding option to the front-end's
2315/// "-mrecip" flag assuming those strings have been passed through in an
2316/// attribute string. For example, "vec-divf" for a division of a vXf32.
2317static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2318 std::string Name = VT.isVector() ? "vec-" : "";
2319
2320 Name += IsSqrt ? "sqrt" : "div";
2321
2322 // TODO: Handle other float types?
2323 if (VT.getScalarType() == MVT::f64) {
2324 Name += "d";
2325 } else if (VT.getScalarType() == MVT::f16) {
2326 Name += "h";
2327 } else {
2328 assert(VT.getScalarType() == MVT::f32 &&
2329 "Unexpected FP type for reciprocal estimate");
2330 Name += "f";
2331 }
2332
2333 return Name;
2334}
2335
2336/// Return the character position and value (a single numeric character) of a
2337/// customized refinement operation in the input string if it exists. Return
2338/// false if there is no customized refinement step count.
2339static bool parseRefinementStep(StringRef In, size_t &Position,
2340 uint8_t &Value) {
2341 const char RefStepToken = ':';
2342 Position = In.find(C: RefStepToken);
2343 if (Position == StringRef::npos)
2344 return false;
2345
2346 StringRef RefStepString = In.substr(Start: Position + 1);
2347 // Allow exactly one numeric character for the additional refinement
2348 // step parameter.
2349 if (RefStepString.size() == 1) {
2350 char RefStepChar = RefStepString[0];
2351 if (isDigit(C: RefStepChar)) {
2352 Value = RefStepChar - '0';
2353 return true;
2354 }
2355 }
2356 report_fatal_error(reason: "Invalid refinement step for -recip.");
2357}
2358
2359/// For the input attribute string, return one of the ReciprocalEstimate enum
2360/// status values (enabled, disabled, or not specified) for this operation on
2361/// the specified data type.
2362static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2363 if (Override.empty())
2364 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2365
2366 SmallVector<StringRef, 4> OverrideVector;
2367 Override.split(A&: OverrideVector, Separator: ',');
2368 unsigned NumArgs = OverrideVector.size();
2369
2370 // Check if "all", "none", or "default" was specified.
2371 if (NumArgs == 1) {
2372 // Look for an optional setting of the number of refinement steps needed
2373 // for this type of reciprocal operation.
2374 size_t RefPos;
2375 uint8_t RefSteps;
2376 if (parseRefinementStep(In: Override, Position&: RefPos, Value&: RefSteps)) {
2377 // Split the string for further processing.
2378 Override = Override.substr(Start: 0, N: RefPos);
2379 }
2380
2381 // All reciprocal types are enabled.
2382 if (Override == "all")
2383 return TargetLoweringBase::ReciprocalEstimate::Enabled;
2384
2385 // All reciprocal types are disabled.
2386 if (Override == "none")
2387 return TargetLoweringBase::ReciprocalEstimate::Disabled;
2388
2389 // Target defaults for enablement are used.
2390 if (Override == "default")
2391 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2392 }
2393
2394 // The attribute string may omit the size suffix ('f'/'d').
2395 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2396 std::string VTNameNoSize = VTName;
2397 VTNameNoSize.pop_back();
2398 static const char DisabledPrefix = '!';
2399
2400 for (StringRef RecipType : OverrideVector) {
2401 size_t RefPos;
2402 uint8_t RefSteps;
2403 if (parseRefinementStep(In: RecipType, Position&: RefPos, Value&: RefSteps))
2404 RecipType = RecipType.substr(Start: 0, N: RefPos);
2405
2406 // Ignore the disablement token for string matching.
2407 bool IsDisabled = RecipType[0] == DisabledPrefix;
2408 if (IsDisabled)
2409 RecipType = RecipType.substr(Start: 1);
2410
2411 if (RecipType == VTName || RecipType == VTNameNoSize)
2412 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
2413 : TargetLoweringBase::ReciprocalEstimate::Enabled;
2414 }
2415
2416 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2417}
2418
2419/// For the input attribute string, return the customized refinement step count
2420/// for this operation on the specified data type. If the step count does not
2421/// exist, return the ReciprocalEstimate enum value for unspecified.
2422static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2423 if (Override.empty())
2424 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2425
2426 SmallVector<StringRef, 4> OverrideVector;
2427 Override.split(A&: OverrideVector, Separator: ',');
2428 unsigned NumArgs = OverrideVector.size();
2429
2430 // Check if "all", "default", or "none" was specified.
2431 if (NumArgs == 1) {
2432 // Look for an optional setting of the number of refinement steps needed
2433 // for this type of reciprocal operation.
2434 size_t RefPos;
2435 uint8_t RefSteps;
2436 if (!parseRefinementStep(In: Override, Position&: RefPos, Value&: RefSteps))
2437 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2438
2439 // Split the string for further processing.
2440 Override = Override.substr(Start: 0, N: RefPos);
2441 assert(Override != "none" &&
2442 "Disabled reciprocals, but specifed refinement steps?");
2443
2444 // If this is a general override, return the specified number of steps.
2445 if (Override == "all" || Override == "default")
2446 return RefSteps;
2447 }
2448
2449 // The attribute string may omit the size suffix ('f'/'d').
2450 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2451 std::string VTNameNoSize = VTName;
2452 VTNameNoSize.pop_back();
2453
2454 for (StringRef RecipType : OverrideVector) {
2455 size_t RefPos;
2456 uint8_t RefSteps;
2457 if (!parseRefinementStep(In: RecipType, Position&: RefPos, Value&: RefSteps))
2458 continue;
2459
2460 RecipType = RecipType.substr(Start: 0, N: RefPos);
2461 if (RecipType == VTName || RecipType == VTNameNoSize)
2462 return RefSteps;
2463 }
2464
2465 return TargetLoweringBase::ReciprocalEstimate::Unspecified;
2466}
2467
2468int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,
2469 const Function &F) const {
2470 return getOpEnabled(IsSqrt: true, VT, Override: getRecipEstimateForFunc(F));
2471}
2472
2473int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,
2474 const Function &F) const {
2475 return getOpEnabled(IsSqrt: false, VT, Override: getRecipEstimateForFunc(F));
2476}
2477
2478int TargetLoweringBase::getSqrtRefinementSteps(EVT VT,
2479 const Function &F) const {
2480 return getOpRefinementSteps(IsSqrt: true, VT, Override: getRecipEstimateForFunc(F));
2481}
2482
2483int TargetLoweringBase::getDivRefinementSteps(EVT VT, const Function &F) const {
2484 return getOpRefinementSteps(IsSqrt: false, VT, Override: getRecipEstimateForFunc(F));
2485}
2486
2487bool TargetLoweringBase::isLoadBitCastBeneficial(
2488 EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG,
2489 const MachineMemOperand &MMO) const {
2490 // Single-element vectors are scalarized, so we should generally avoid having
2491 // any memory operations on such types, as they would get scalarized too.
2492 if (LoadVT.isFixedLengthVector() && BitcastVT.isFixedLengthVector() &&
2493 BitcastVT.getVectorNumElements() == 1)
2494 return false;
2495
2496 // Don't do if we could do an indexed load on the original type, but not on
2497 // the new one.
2498 if (!LoadVT.isSimple() || !BitcastVT.isSimple())
2499 return true;
2500
2501 MVT LoadMVT = LoadVT.getSimpleVT();
2502
2503 // Don't bother doing this if it's just going to be promoted again later, as
2504 // doing so might interfere with other combines.
2505 if (getOperationAction(Op: ISD::LOAD, VT: LoadMVT) == Promote &&
2506 getTypeToPromoteTo(Op: ISD::LOAD, VT: LoadMVT) == BitcastVT.getSimpleVT())
2507 return false;
2508
2509 unsigned Fast = 0;
2510 return allowsMemoryAccess(Context&: *DAG.getContext(), DL: DAG.getDataLayout(), VT: BitcastVT,
2511 MMO, Fast: &Fast) &&
2512 Fast;
2513}
2514
2515void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const {
2516 MF.getRegInfo().freezeReservedRegs();
2517}
2518
2519MachineMemOperand::Flags TargetLoweringBase::getLoadMemOperandFlags(
2520 const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC,
2521 const TargetLibraryInfo *LibInfo, CodeGenOptLevel OptLevel) const {
2522 MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad;
2523 if (LI.isVolatile())
2524 Flags |= MachineMemOperand::MOVolatile;
2525
2526 if (LI.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2527 Flags |= MachineMemOperand::MONonTemporal;
2528
2529 if (LI.hasMetadata(KindID: LLVMContext::MD_invariant_load))
2530 Flags |= MachineMemOperand::MOInvariant;
2531
2532 // Dereferenceability analysis is expensive, skip at O0.
2533 if (OptLevel != CodeGenOptLevel::None &&
2534 isDereferenceableAndAlignedPointer(
2535 V: LI.getPointerOperand(), Ty: LI.getType(), Alignment: LI.getAlign(),
2536 Q: SimplifyQuery(DL, LibInfo, /*DT=*/nullptr, AC, &LI)))
2537 Flags |= MachineMemOperand::MODereferenceable;
2538
2539 Flags |= getTargetMMOFlags(I: LI);
2540 return Flags;
2541}
2542
2543MachineMemOperand::Flags
2544TargetLoweringBase::getStoreMemOperandFlags(const StoreInst &SI,
2545 const DataLayout &DL) const {
2546 MachineMemOperand::Flags Flags = MachineMemOperand::MOStore;
2547
2548 if (SI.isVolatile())
2549 Flags |= MachineMemOperand::MOVolatile;
2550
2551 if (SI.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2552 Flags |= MachineMemOperand::MONonTemporal;
2553
2554 // FIXME: Not preserving dereferenceable
2555 Flags |= getTargetMMOFlags(I: SI);
2556 return Flags;
2557}
2558
2559MachineMemOperand::Flags
2560TargetLoweringBase::getAtomicMemOperandFlags(const Instruction &AI,
2561 const DataLayout &DL) const {
2562 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
2563
2564 if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(Val: &AI)) {
2565 if (RMW->isVolatile())
2566 Flags |= MachineMemOperand::MOVolatile;
2567 } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(Val: &AI)) {
2568 if (CmpX->isVolatile())
2569 Flags |= MachineMemOperand::MOVolatile;
2570 } else
2571 llvm_unreachable("not an atomic instruction");
2572
2573 // FIXME: Not preserving dereferenceable
2574 Flags |= getTargetMMOFlags(I: AI);
2575 return Flags;
2576}
2577
2578MachineMemOperand::Flags TargetLoweringBase::getVPIntrinsicMemOperandFlags(
2579 const VPIntrinsic &VPIntrin) const {
2580 MachineMemOperand::Flags Flags = MachineMemOperand::MONone;
2581 Intrinsic::ID IntrinID = VPIntrin.getIntrinsicID();
2582
2583 switch (IntrinID) {
2584 default:
2585 llvm_unreachable("unexpected intrinsic. Existing code may be appropriate "
2586 "for it, but support must be explicitly enabled");
2587 case Intrinsic::vp_load:
2588 case Intrinsic::vp_gather:
2589 case Intrinsic::experimental_vp_strided_load:
2590 Flags = MachineMemOperand::MOLoad;
2591 break;
2592 case Intrinsic::vp_store:
2593 case Intrinsic::vp_scatter:
2594 case Intrinsic::experimental_vp_strided_store:
2595 Flags = MachineMemOperand::MOStore;
2596 break;
2597 }
2598
2599 if (VPIntrin.hasMetadata(KindID: LLVMContext::MD_nontemporal))
2600 Flags |= MachineMemOperand::MONonTemporal;
2601
2602 Flags |= getTargetMMOFlags(I: VPIntrin);
2603 return Flags;
2604}
2605
2606Instruction *TargetLoweringBase::emitLeadingFence(IRBuilderBase &Builder,
2607 Instruction *Inst,
2608 AtomicOrdering Ord) const {
2609 if (isReleaseOrStronger(AO: Ord) && Inst->hasAtomicStore())
2610 return Builder.CreateFence(Ordering: Ord);
2611 else
2612 return nullptr;
2613}
2614
2615Instruction *TargetLoweringBase::emitTrailingFence(IRBuilderBase &Builder,
2616 Instruction *Inst,
2617 AtomicOrdering Ord) const {
2618 if (isAcquireOrStronger(AO: Ord))
2619 return Builder.CreateFence(Ordering: Ord);
2620 else
2621 return nullptr;
2622}
2623
2624//===----------------------------------------------------------------------===//
2625// GlobalISel Hooks
2626//===----------------------------------------------------------------------===//
2627
2628bool TargetLoweringBase::shouldLocalize(const MachineInstr &MI,
2629 const TargetTransformInfo *TTI) const {
2630 auto &MF = *MI.getMF();
2631 auto &MRI = MF.getRegInfo();
2632 // Assuming a spill and reload of a value has a cost of 1 instruction each,
2633 // this helper function computes the maximum number of uses we should consider
2634 // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2635 // break even in terms of code size when the original MI has 2 users vs
2636 // choosing to potentially spill. Any more than 2 users we we have a net code
2637 // size increase. This doesn't take into account register pressure though.
2638 auto maxUses = [](unsigned RematCost) {
2639 // A cost of 1 means remats are basically free.
2640 if (RematCost == 1)
2641 return std::numeric_limits<unsigned>::max();
2642 if (RematCost == 2)
2643 return 2U;
2644
2645 // Remat is too expensive, only sink if there's one user.
2646 if (RematCost > 2)
2647 return 1U;
2648 llvm_unreachable("Unexpected remat cost");
2649 };
2650
2651 switch (MI.getOpcode()) {
2652 default:
2653 return false;
2654 // Constants-like instructions should be close to their users.
2655 // We don't want long live-ranges for them.
2656 case TargetOpcode::G_CONSTANT:
2657 case TargetOpcode::G_FCONSTANT:
2658 case TargetOpcode::G_FRAME_INDEX:
2659 case TargetOpcode::G_INTTOPTR:
2660 return true;
2661 case TargetOpcode::G_GLOBAL_VALUE: {
2662 unsigned RematCost = TTI->getGISelRematGlobalCost();
2663 Register Reg = MI.getOperand(i: 0).getReg();
2664 unsigned MaxUses = maxUses(RematCost);
2665 if (MaxUses == UINT_MAX)
2666 return true; // Remats are "free" so always localize.
2667 return MRI.hasAtMostUserInstrs(Reg, MaxUsers: MaxUses);
2668 }
2669 }
2670}
2671