1//===- TwoAddressInstructionPass.cpp - Two-Address instruction pass -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the TwoAddress instruction pass which is used
10// by most register allocators. Two-Address instructions are rewritten
11// from:
12//
13// A = B op C
14//
15// to:
16//
17// A = B
18// A op= C
19//
20// Note that if a register allocator chooses to use this pass, that it
21// has to be capable of handling the non-SSA nature of these rewritten
22// virtual registers.
23//
24// It is also worth noting that the duplicate operand of the two
25// address instruction is removed.
26//
27//===----------------------------------------------------------------------===//
28
29#include "llvm/CodeGen/TwoAddressInstructionPass.h"
30#include "llvm/ADT/DenseMap.h"
31#include "llvm/ADT/SmallPtrSet.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/Statistic.h"
34#include "llvm/ADT/iterator_range.h"
35#include "llvm/Analysis/AliasAnalysis.h"
36#include "llvm/CodeGen/LiveInterval.h"
37#include "llvm/CodeGen/LiveIntervals.h"
38#include "llvm/CodeGen/LiveVariables.h"
39#include "llvm/CodeGen/MachineBasicBlock.h"
40#include "llvm/CodeGen/MachineDominators.h"
41#include "llvm/CodeGen/MachineFunction.h"
42#include "llvm/CodeGen/MachineFunctionPass.h"
43#include "llvm/CodeGen/MachineInstr.h"
44#include "llvm/CodeGen/MachineInstrBuilder.h"
45#include "llvm/CodeGen/MachineLoopInfo.h"
46#include "llvm/CodeGen/MachineOperand.h"
47#include "llvm/CodeGen/MachineRegisterInfo.h"
48#include "llvm/CodeGen/Passes.h"
49#include "llvm/CodeGen/SlotIndexes.h"
50#include "llvm/CodeGen/TargetInstrInfo.h"
51#include "llvm/CodeGen/TargetOpcodes.h"
52#include "llvm/CodeGen/TargetRegisterInfo.h"
53#include "llvm/CodeGen/TargetSubtargetInfo.h"
54#include "llvm/InitializePasses.h"
55#include "llvm/MC/MCInstrDesc.h"
56#include "llvm/Pass.h"
57#include "llvm/Support/CodeGen.h"
58#include "llvm/Support/CommandLine.h"
59#include "llvm/Support/Debug.h"
60#include "llvm/Support/ErrorHandling.h"
61#include "llvm/Support/raw_ostream.h"
62#include "llvm/Target/TargetMachine.h"
63#include <cassert>
64#include <iterator>
65#include <utility>
66
67using namespace llvm;
68
69#define DEBUG_TYPE "twoaddressinstruction"
70
71STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
72STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
73STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
74STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
75STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
76STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
77
78// Temporary flag to disable rescheduling.
79static cl::opt<bool>
80EnableRescheduling("twoaddr-reschedule",
81 cl::desc("Coalesce copies by rescheduling (default=true)"),
82 cl::init(Val: true), cl::Hidden);
83
84// Limit the number of dataflow edges to traverse when evaluating the benefit
85// of commuting operands.
86static cl::opt<unsigned> MaxDataFlowEdge(
87 "dataflow-edge-limit", cl::Hidden, cl::init(Val: 3),
88 cl::desc("Maximum number of dataflow edges to traverse when evaluating "
89 "the benefit of commuting operands"));
90
91namespace {
92
93class TwoAddressInstructionImpl {
94 MachineFunction *MF = nullptr;
95 const TargetInstrInfo *TII = nullptr;
96 const TargetRegisterInfo *TRI = nullptr;
97 const InstrItineraryData *InstrItins = nullptr;
98 MachineRegisterInfo *MRI = nullptr;
99 LiveVariables *LV = nullptr;
100 LiveIntervals *LIS = nullptr;
101 CodeGenOptLevel OptLevel = CodeGenOptLevel::None;
102
103 // The current basic block being processed.
104 MachineBasicBlock *MBB = nullptr;
105
106 // Keep track the distance of a MI from the start of the current basic block.
107 DenseMap<MachineInstr*, unsigned> DistanceMap;
108
109 // Set of already processed instructions in the current block.
110 SmallPtrSet<MachineInstr*, 8> Processed;
111
112 // A map from virtual registers to physical registers which are likely targets
113 // to be coalesced to due to copies from physical registers to virtual
114 // registers. e.g. v1024 = move r0.
115 DenseMap<Register, Register> SrcRegMap;
116
117 // A map from virtual registers to physical registers which are likely targets
118 // to be coalesced to due to copies to physical registers from virtual
119 // registers. e.g. r1 = move v1024.
120 DenseMap<Register, Register> DstRegMap;
121
122 MachineInstr *getSingleDef(Register Reg, MachineBasicBlock *BB) const;
123
124 bool isRevCopyChain(Register FromReg, Register ToReg, int Maxlen);
125
126 bool noUseAfterLastDef(Register Reg, unsigned Dist, unsigned &LastDef);
127
128 bool isCopyToReg(MachineInstr &MI, Register &SrcReg, Register &DstReg,
129 bool &IsSrcPhys, bool &IsDstPhys) const;
130
131 bool isPlainlyKilled(const MachineInstr *MI, LiveRange &LR) const;
132 bool isPlainlyKilled(const MachineInstr *MI, Register Reg) const;
133 bool isPlainlyKilled(const MachineOperand &MO) const;
134
135 bool isKilled(MachineInstr &MI, Register Reg, bool allowFalsePositives) const;
136
137 MachineInstr *findOnlyInterestingUse(Register Reg, MachineBasicBlock *MBB,
138 bool &IsCopy, Register &DstReg,
139 bool &IsDstPhys) const;
140
141 bool regsAreCompatible(Register RegA, Register RegB) const;
142
143 void removeMapRegEntry(const MachineOperand &MO,
144 DenseMap<Register, Register> &RegMap) const;
145
146 void removeClobberedSrcRegMap(MachineInstr *MI);
147
148 bool regOverlapsSet(const SmallVectorImpl<Register> &Set, Register Reg) const;
149
150 bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
151 MachineInstr *MI, unsigned Dist);
152
153 bool commuteInstruction(MachineInstr *MI, unsigned DstIdx,
154 unsigned RegBIdx, unsigned RegCIdx, unsigned Dist);
155
156 bool isProfitableToConv3Addr(Register RegA, Register RegB);
157
158 bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
159 MachineBasicBlock::iterator &nmi, Register RegA,
160 Register RegB, unsigned &Dist);
161
162 bool isDefTooClose(Register Reg, unsigned Dist, MachineInstr *MI);
163
164 bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
165 MachineBasicBlock::iterator &nmi, Register Reg);
166 bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
167 MachineBasicBlock::iterator &nmi, Register Reg);
168
169 bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
170 MachineBasicBlock::iterator &nmi,
171 unsigned SrcIdx, unsigned DstIdx,
172 unsigned &Dist, bool shouldOnlyCommute);
173
174 bool tryInstructionCommute(MachineInstr *MI,
175 unsigned DstOpIdx,
176 unsigned BaseOpIdx,
177 bool BaseOpKilled,
178 unsigned Dist);
179 void scanUses(Register DstReg);
180
181 void processCopy(MachineInstr *MI);
182
183 using TiedPairList = SmallVector<std::pair<unsigned, unsigned>, 4>;
184 using TiedOperandMap = SmallDenseMap<Register, TiedPairList>;
185
186 bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
187 void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
188 void eliminateRegSequence(MachineBasicBlock::iterator&);
189 bool processStatepoint(MachineInstr *MI, TiedOperandMap &TiedOperands);
190
191public:
192 TwoAddressInstructionImpl(MachineFunction &MF, MachineFunctionPass *P);
193 TwoAddressInstructionImpl(MachineFunction &MF,
194 MachineFunctionAnalysisManager &MFAM,
195 LiveIntervals *LIS);
196 void setOptLevel(CodeGenOptLevel Level) { OptLevel = Level; }
197 bool run();
198};
199
200class TwoAddressInstructionLegacyPass : public MachineFunctionPass {
201public:
202 static char ID; // Pass identification, replacement for typeid
203
204 TwoAddressInstructionLegacyPass() : MachineFunctionPass(ID) {}
205
206 /// Pass entry point.
207 bool runOnMachineFunction(MachineFunction &MF) override {
208 TwoAddressInstructionImpl Impl(MF, this);
209 // Disable optimizations if requested. We cannot skip the whole pass as some
210 // fixups are necessary for correctness.
211 if (skipFunction(F: MF.getFunction()))
212 Impl.setOptLevel(CodeGenOptLevel::None);
213 return Impl.run();
214 }
215
216 void getAnalysisUsage(AnalysisUsage &AU) const override {
217 AU.setPreservesCFG();
218 AU.addUsedIfAvailable<LiveVariablesWrapperPass>();
219 AU.addPreserved<LiveVariablesWrapperPass>();
220 AU.addPreserved<SlotIndexesWrapperPass>();
221 AU.addPreserved<LiveIntervalsWrapperPass>();
222 AU.addPreservedID(ID&: MachineLoopInfoID);
223 AU.addPreservedID(ID&: MachineDominatorsID);
224 MachineFunctionPass::getAnalysisUsage(AU);
225 }
226};
227
228} // end anonymous namespace
229
230PreservedAnalyses
231TwoAddressInstructionPass::run(MachineFunction &MF,
232 MachineFunctionAnalysisManager &MFAM) {
233 // Disable optimizations if requested. We cannot skip the whole pass as some
234 // fixups are necessary for correctness.
235 LiveIntervals *LIS = MFAM.getCachedResult<LiveIntervalsAnalysis>(IR&: MF);
236
237 TwoAddressInstructionImpl Impl(MF, MFAM, LIS);
238 if (MF.getFunction().hasOptNone())
239 Impl.setOptLevel(CodeGenOptLevel::None);
240
241 MFPropsModifier _(*this, MF);
242 bool Changed = Impl.run();
243 if (!Changed)
244 return PreservedAnalyses::all();
245 auto PA = getMachineFunctionPassPreservedAnalyses();
246
247 // SlotIndexes are only maintained when LiveIntervals is available. Only
248 // preserve SlotIndexes if we had LiveIntervals available and updated them.
249 if (LIS)
250 PA.preserve<SlotIndexesAnalysis>();
251
252 PA.preserve<LiveVariablesAnalysis>();
253 PA.preserve<LiveIntervalsAnalysis>();
254 PA.preserve<MachineDominatorTreeAnalysis>();
255 PA.preserve<MachineLoopAnalysis>();
256 PA.preserveSet<CFGAnalyses>();
257 return PA;
258}
259
260char TwoAddressInstructionLegacyPass::ID = 0;
261
262char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionLegacyPass::ID;
263
264INITIALIZE_PASS(TwoAddressInstructionLegacyPass, DEBUG_TYPE,
265 "Two-Address instruction pass", false, false)
266
267TwoAddressInstructionImpl::TwoAddressInstructionImpl(
268 MachineFunction &Func, MachineFunctionAnalysisManager &MFAM,
269 LiveIntervals *LIS)
270 : MF(&Func), TII(Func.getSubtarget().getInstrInfo()),
271 TRI(Func.getSubtarget().getRegisterInfo()),
272 InstrItins(Func.getSubtarget().getInstrItineraryData()),
273 MRI(&Func.getRegInfo()),
274 LV(MFAM.getCachedResult<LiveVariablesAnalysis>(IR&: Func)), LIS(LIS),
275 OptLevel(Func.getTarget().getOptLevel()) {}
276
277TwoAddressInstructionImpl::TwoAddressInstructionImpl(MachineFunction &Func,
278 MachineFunctionPass *P)
279 : MF(&Func), TII(Func.getSubtarget().getInstrInfo()),
280 TRI(Func.getSubtarget().getRegisterInfo()),
281 InstrItins(Func.getSubtarget().getInstrItineraryData()),
282 MRI(&Func.getRegInfo()), OptLevel(Func.getTarget().getOptLevel()) {
283 auto *LVWrapper = P->getAnalysisIfAvailable<LiveVariablesWrapperPass>();
284 LV = LVWrapper ? &LVWrapper->getLV() : nullptr;
285 auto *LISWrapper = P->getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
286 LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
287}
288
289/// Return the MachineInstr* if it is the single def of the Reg in current BB.
290MachineInstr *
291TwoAddressInstructionImpl::getSingleDef(Register Reg,
292 MachineBasicBlock *BB) const {
293 MachineInstr *Ret = nullptr;
294 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
295 if (DefMI.getParent() != BB || DefMI.isDebugValue())
296 continue;
297 if (!Ret)
298 Ret = &DefMI;
299 else if (Ret != &DefMI)
300 return nullptr;
301 }
302 return Ret;
303}
304
305/// Check if there is a reversed copy chain from FromReg to ToReg:
306/// %Tmp1 = copy %Tmp2;
307/// %FromReg = copy %Tmp1;
308/// %ToReg = add %FromReg ...
309/// %Tmp2 = copy %ToReg;
310/// MaxLen specifies the maximum length of the copy chain the func
311/// can walk through.
312bool TwoAddressInstructionImpl::isRevCopyChain(Register FromReg, Register ToReg,
313 int Maxlen) {
314 Register TmpReg = FromReg;
315 for (int i = 0; i < Maxlen; i++) {
316 MachineInstr *Def = getSingleDef(Reg: TmpReg, BB: MBB);
317 if (!Def || !Def->isCopy())
318 return false;
319
320 TmpReg = Def->getOperand(i: 1).getReg();
321
322 if (TmpReg == ToReg)
323 return true;
324 }
325 return false;
326}
327
328/// Return true if there are no intervening uses between the last instruction
329/// in the MBB that defines the specified register and the two-address
330/// instruction which is being processed. It also returns the last def location
331/// by reference.
332bool TwoAddressInstructionImpl::noUseAfterLastDef(Register Reg, unsigned Dist,
333 unsigned &LastDef) {
334 LastDef = 0;
335 unsigned LastUse = Dist;
336 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
337 MachineInstr *MI = MO.getParent();
338 if (MI->getParent() != MBB || MI->isDebugValue())
339 continue;
340 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(Val: MI);
341 if (DI == DistanceMap.end())
342 continue;
343 if (MO.isUse() && DI->second < LastUse)
344 LastUse = DI->second;
345 if (MO.isDef() && DI->second > LastDef)
346 LastDef = DI->second;
347 }
348
349 return !(LastUse > LastDef && LastUse < Dist);
350}
351
352/// Return true if the specified MI is a copy instruction or an extract_subreg
353/// instruction. It also returns the source and destination registers and
354/// whether they are physical registers by reference.
355bool TwoAddressInstructionImpl::isCopyToReg(MachineInstr &MI, Register &SrcReg,
356 Register &DstReg, bool &IsSrcPhys,
357 bool &IsDstPhys) const {
358 SrcReg = 0;
359 DstReg = 0;
360 if (MI.isCopy()) {
361 DstReg = MI.getOperand(i: 0).getReg();
362 SrcReg = MI.getOperand(i: 1).getReg();
363 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
364 DstReg = MI.getOperand(i: 0).getReg();
365 SrcReg = MI.getOperand(i: 2).getReg();
366 } else {
367 return false;
368 }
369
370 IsSrcPhys = SrcReg.isPhysical();
371 IsDstPhys = DstReg.isPhysical();
372 return true;
373}
374
375bool TwoAddressInstructionImpl::isPlainlyKilled(const MachineInstr *MI,
376 LiveRange &LR) const {
377 // This is to match the kill flag version where undefs don't have kill flags.
378 if (!LR.hasAtLeastOneValue())
379 return false;
380
381 SlotIndex useIdx = LIS->getInstructionIndex(Instr: *MI);
382 LiveInterval::const_iterator I = LR.find(Pos: useIdx);
383 assert(I != LR.end() && "Reg must be live-in to use.");
384 return !I->end.isBlock() && SlotIndex::isSameInstr(A: I->end, B: useIdx);
385}
386
387/// Test if the given register value, which is used by the
388/// given instruction, is killed by the given instruction.
389bool TwoAddressInstructionImpl::isPlainlyKilled(const MachineInstr *MI,
390 Register Reg) const {
391 // FIXME: Sometimes tryInstructionTransform() will add instructions and
392 // test whether they can be folded before keeping them. In this case it
393 // sets a kill before recursively calling tryInstructionTransform() again.
394 // If there is no interval available, we assume that this instruction is
395 // one of those. A kill flag is manually inserted on the operand so the
396 // check below will handle it.
397 if (LIS && !LIS->isNotInMIMap(Instr: *MI)) {
398 if (Reg.isVirtual())
399 return isPlainlyKilled(MI, LR&: LIS->getInterval(Reg));
400 // Reserved registers are considered always live.
401 if (MRI->isReserved(PhysReg: Reg))
402 return false;
403 return all_of(Range: TRI->regunits(Reg), P: [&](MCRegUnit U) {
404 return isPlainlyKilled(MI, LR&: LIS->getRegUnit(Unit: U));
405 });
406 }
407
408 return MI->killsRegister(Reg, /*TRI=*/nullptr);
409}
410
411/// Test if the register used by the given operand is killed by the operand's
412/// instruction.
413bool TwoAddressInstructionImpl::isPlainlyKilled(
414 const MachineOperand &MO) const {
415 return MO.isKill() || isPlainlyKilled(MI: MO.getParent(), Reg: MO.getReg());
416}
417
418/// Test if the given register value, which is used by the given
419/// instruction, is killed by the given instruction. This looks through
420/// coalescable copies to see if the original value is potentially not killed.
421///
422/// For example, in this code:
423///
424/// %reg1034 = copy %reg1024
425/// %reg1035 = copy killed %reg1025
426/// %reg1036 = add killed %reg1034, killed %reg1035
427///
428/// %reg1034 is not considered to be killed, since it is copied from a
429/// register which is not killed. Treating it as not killed lets the
430/// normal heuristics commute the (two-address) add, which lets
431/// coalescing eliminate the extra copy.
432///
433/// If allowFalsePositives is true then likely kills are treated as kills even
434/// if it can't be proven that they are kills.
435bool TwoAddressInstructionImpl::isKilled(MachineInstr &MI, Register Reg,
436 bool allowFalsePositives) const {
437 MachineInstr *DefMI = &MI;
438 while (true) {
439 // All uses of physical registers are likely to be kills.
440 if (Reg.isPhysical() && (allowFalsePositives || MRI->hasOneUse(RegNo: Reg)))
441 return true;
442 if (!isPlainlyKilled(MI: DefMI, Reg))
443 return false;
444 if (Reg.isPhysical())
445 return true;
446 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(RegNo: Reg);
447 // If there are multiple defs, we can't do a simple analysis, so just
448 // go with what the kill flag says.
449 if (std::next(x: Begin) != MRI->def_end())
450 return true;
451 DefMI = Begin->getParent();
452 bool IsSrcPhys, IsDstPhys;
453 Register SrcReg, DstReg;
454 // If the def is something other than a copy, then it isn't going to
455 // be coalesced, so follow the kill flag.
456 if (!isCopyToReg(MI&: *DefMI, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
457 return true;
458 Reg = SrcReg;
459 }
460}
461
462/// Return true if the specified MI uses the specified register as a two-address
463/// use. If so, return the destination register by reference.
464static bool isTwoAddrUse(MachineInstr &MI, Register Reg, Register &DstReg) {
465 for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
466 const MachineOperand &MO = MI.getOperand(i);
467 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
468 continue;
469 unsigned ti;
470 if (MI.isRegTiedToDefOperand(UseOpIdx: i, DefOpIdx: &ti)) {
471 DstReg = MI.getOperand(i: ti).getReg();
472 return true;
473 }
474 }
475 return false;
476}
477
478/// Given a register, if all its uses are in the same basic block, return the
479/// last use instruction if it's a copy or a two-address use.
480MachineInstr *TwoAddressInstructionImpl::findOnlyInterestingUse(
481 Register Reg, MachineBasicBlock *MBB, bool &IsCopy, Register &DstReg,
482 bool &IsDstPhys) const {
483 MachineOperand *UseOp = nullptr;
484 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
485 if (MO.isUndef())
486 continue;
487
488 MachineInstr *MI = MO.getParent();
489 if (MI->getParent() != MBB)
490 return nullptr;
491 if (isPlainlyKilled(MI, Reg))
492 UseOp = &MO;
493 }
494 if (!UseOp)
495 return nullptr;
496 MachineInstr &UseMI = *UseOp->getParent();
497
498 Register SrcReg;
499 bool IsSrcPhys;
500 if (isCopyToReg(MI&: UseMI, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
501 IsCopy = true;
502 return &UseMI;
503 }
504 IsDstPhys = false;
505 if (isTwoAddrUse(MI&: UseMI, Reg, DstReg)) {
506 IsDstPhys = DstReg.isPhysical();
507 return &UseMI;
508 }
509 if (UseMI.isCommutable()) {
510 unsigned Src1 = TargetInstrInfo::CommuteAnyOperandIndex;
511 unsigned Src2 = UseOp->getOperandNo();
512 if (TII->findCommutedOpIndices(MI: UseMI, SrcOpIdx1&: Src1, SrcOpIdx2&: Src2)) {
513 MachineOperand &MO = UseMI.getOperand(i: Src1);
514 if (MO.isReg() && MO.isUse() &&
515 isTwoAddrUse(MI&: UseMI, Reg: MO.getReg(), DstReg)) {
516 IsDstPhys = DstReg.isPhysical();
517 return &UseMI;
518 }
519 }
520 }
521 return nullptr;
522}
523
524/// Return the physical register the specified virtual register might be mapped
525/// to.
526static MCRegister getMappedReg(Register Reg,
527 DenseMap<Register, Register> &RegMap) {
528 while (Reg.isVirtual()) {
529 DenseMap<Register, Register>::iterator SI = RegMap.find(Val: Reg);
530 if (SI == RegMap.end())
531 return 0;
532 Reg = SI->second;
533 }
534 if (Reg.isPhysical())
535 return Reg;
536 return 0;
537}
538
539/// Return true if the two registers are equal or aliased.
540bool TwoAddressInstructionImpl::regsAreCompatible(Register RegA,
541 Register RegB) const {
542 if (RegA == RegB)
543 return true;
544 if (!RegA || !RegB)
545 return false;
546 return TRI->regsOverlap(RegA, RegB);
547}
548
549/// From RegMap remove entries mapped to a physical register which overlaps MO.
550void TwoAddressInstructionImpl::removeMapRegEntry(
551 const MachineOperand &MO, DenseMap<Register, Register> &RegMap) const {
552 assert(
553 (MO.isReg() || MO.isRegMask()) &&
554 "removeMapRegEntry must be called with a register or regmask operand.");
555
556 SmallVector<Register, 2> Srcs;
557 for (auto SI : RegMap) {
558 Register ToReg = SI.second;
559 if (ToReg.isVirtual())
560 continue;
561
562 if (MO.isReg()) {
563 Register Reg = MO.getReg();
564 if (TRI->regsOverlap(RegA: ToReg, RegB: Reg))
565 Srcs.push_back(Elt: SI.first);
566 } else if (MO.clobbersPhysReg(PhysReg: ToReg))
567 Srcs.push_back(Elt: SI.first);
568 }
569
570 for (auto SrcReg : Srcs)
571 RegMap.erase(Val: SrcReg);
572}
573
574/// If a physical register is clobbered, old entries mapped to it should be
575/// deleted. For example
576///
577/// %2:gr64 = COPY killed $rdx
578/// MUL64r %3:gr64, implicit-def $rax, implicit-def $rdx
579///
580/// After the MUL instruction, $rdx contains different value than in the COPY
581/// instruction. So %2 should not map to $rdx after MUL.
582void TwoAddressInstructionImpl::removeClobberedSrcRegMap(MachineInstr *MI) {
583 if (MI->isCopy()) {
584 // If a virtual register is copied to its mapped physical register, it
585 // doesn't change the potential coalescing between them, so we don't remove
586 // entries mapped to the physical register. For example
587 //
588 // %100 = COPY $r8
589 // ...
590 // $r8 = COPY %100
591 //
592 // The first copy constructs SrcRegMap[%100] = $r8, the second copy doesn't
593 // destroy the content of $r8, and should not impact SrcRegMap.
594 Register Dst = MI->getOperand(i: 0).getReg();
595 if (!Dst || Dst.isVirtual())
596 return;
597
598 Register Src = MI->getOperand(i: 1).getReg();
599 if (regsAreCompatible(RegA: Dst, RegB: getMappedReg(Reg: Src, RegMap&: SrcRegMap)))
600 return;
601 }
602
603 for (const MachineOperand &MO : MI->operands()) {
604 if (MO.isRegMask()) {
605 removeMapRegEntry(MO, RegMap&: SrcRegMap);
606 continue;
607 }
608 if (!MO.isReg() || !MO.isDef())
609 continue;
610 Register Reg = MO.getReg();
611 if (!Reg || Reg.isVirtual())
612 continue;
613 removeMapRegEntry(MO, RegMap&: SrcRegMap);
614 }
615}
616
617// Returns true if Reg is equal or aliased to at least one register in Set.
618bool TwoAddressInstructionImpl::regOverlapsSet(
619 const SmallVectorImpl<Register> &Set, Register Reg) const {
620 for (Register R : Set)
621 if (TRI->regsOverlap(RegA: R, RegB: Reg))
622 return true;
623
624 return false;
625}
626
627/// Return true if it's potentially profitable to commute the two-address
628/// instruction that's being processed.
629bool TwoAddressInstructionImpl::isProfitableToCommute(Register RegA,
630 Register RegB,
631 Register RegC,
632 MachineInstr *MI,
633 unsigned Dist) {
634 if (OptLevel == CodeGenOptLevel::None)
635 return false;
636
637 // Determine if it's profitable to commute this two address instruction. In
638 // general, we want no uses between this instruction and the definition of
639 // the two-address register.
640 // e.g.
641 // %reg1028 = EXTRACT_SUBREG killed %reg1027, 1
642 // %reg1029 = COPY %reg1028
643 // %reg1029 = SHR8ri %reg1029, 7, implicit dead %eflags
644 // insert => %reg1030 = COPY %reg1028
645 // %reg1030 = ADD8rr killed %reg1028, killed %reg1029, implicit dead %eflags
646 // In this case, it might not be possible to coalesce the second COPY
647 // instruction if the first one is coalesced. So it would be profitable to
648 // commute it:
649 // %reg1028 = EXTRACT_SUBREG killed %reg1027, 1
650 // %reg1029 = COPY %reg1028
651 // %reg1029 = SHR8ri %reg1029, 7, implicit dead %eflags
652 // insert => %reg1030 = COPY %reg1029
653 // %reg1030 = ADD8rr killed %reg1029, killed %reg1028, implicit dead %eflags
654
655 if (!isPlainlyKilled(MI, Reg: RegC))
656 return false;
657
658 // Ok, we have something like:
659 // %reg1030 = ADD8rr killed %reg1028, killed %reg1029, implicit dead %eflags
660 // let's see if it's worth commuting it.
661
662 // Look for situations like this:
663 // %reg1024 = MOV r1
664 // %reg1025 = MOV r0
665 // %reg1026 = ADD %reg1024, %reg1025
666 // r0 = MOV %reg1026
667 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
668 MCRegister ToRegA = getMappedReg(Reg: RegA, RegMap&: DstRegMap);
669 if (ToRegA) {
670 MCRegister FromRegB = getMappedReg(Reg: RegB, RegMap&: SrcRegMap);
671 MCRegister FromRegC = getMappedReg(Reg: RegC, RegMap&: SrcRegMap);
672 bool CompB = FromRegB && regsAreCompatible(RegA: FromRegB, RegB: ToRegA);
673 bool CompC = FromRegC && regsAreCompatible(RegA: FromRegC, RegB: ToRegA);
674
675 // Compute if any of the following are true:
676 // -RegB is not tied to a register and RegC is compatible with RegA.
677 // -RegB is tied to the wrong physical register, but RegC is.
678 // -RegB is tied to the wrong physical register, and RegC isn't tied.
679 if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
680 return true;
681 // Don't compute if any of the following are true:
682 // -RegC is not tied to a register and RegB is compatible with RegA.
683 // -RegC is tied to the wrong physical register, but RegB is.
684 // -RegC is tied to the wrong physical register, and RegB isn't tied.
685 if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
686 return false;
687 }
688
689 // If there is a use of RegC between its last def (could be livein) and this
690 // instruction, then bail.
691 unsigned LastDefC = 0;
692 if (!noUseAfterLastDef(Reg: RegC, Dist, LastDef&: LastDefC))
693 return false;
694
695 // If there is a use of RegB between its last def (could be livein) and this
696 // instruction, then go ahead and make this transformation.
697 unsigned LastDefB = 0;
698 if (!noUseAfterLastDef(Reg: RegB, Dist, LastDef&: LastDefB))
699 return true;
700
701 // Look for situation like this:
702 // %reg101 = MOV %reg100
703 // %reg102 = ...
704 // %reg103 = ADD %reg102, %reg101
705 // ... = %reg103 ...
706 // %reg100 = MOV %reg103
707 // If there is a reversed copy chain from reg101 to reg103, commute the ADD
708 // to eliminate an otherwise unavoidable copy.
709 // FIXME:
710 // We can extend the logic further: If an pair of operands in an insn has
711 // been merged, the insn could be regarded as a virtual copy, and the virtual
712 // copy could also be used to construct a copy chain.
713 // To more generally minimize register copies, ideally the logic of two addr
714 // instruction pass should be integrated with register allocation pass where
715 // interference graph is available.
716 if (isRevCopyChain(FromReg: RegC, ToReg: RegA, Maxlen: MaxDataFlowEdge))
717 return true;
718
719 if (isRevCopyChain(FromReg: RegB, ToReg: RegA, Maxlen: MaxDataFlowEdge))
720 return false;
721
722 // Look for other target specific commute preference.
723 bool Commute;
724 if (TII->hasCommutePreference(MI&: *MI, Commute))
725 return Commute;
726
727 // Since there are no intervening uses for both registers, then commute
728 // if the def of RegC is closer. Its live interval is shorter.
729 return LastDefB && LastDefC && LastDefC > LastDefB;
730}
731
732/// Commute a two-address instruction and update the basic block, distance map,
733/// and live variables if needed. Return true if it is successful.
734bool TwoAddressInstructionImpl::commuteInstruction(MachineInstr *MI,
735 unsigned DstIdx,
736 unsigned RegBIdx,
737 unsigned RegCIdx,
738 unsigned Dist) {
739 Register RegC = MI->getOperand(i: RegCIdx).getReg();
740 LLVM_DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
741 MachineInstr *NewMI = TII->commuteInstruction(MI&: *MI, NewMI: false, OpIdx1: RegBIdx, OpIdx2: RegCIdx);
742
743 if (NewMI == nullptr) {
744 LLVM_DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
745 return false;
746 }
747
748 LLVM_DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
749 assert(NewMI == MI &&
750 "TargetInstrInfo::commuteInstruction() should not return a new "
751 "instruction unless it was requested.");
752
753 // Update source register map.
754 MCRegister FromRegC = getMappedReg(Reg: RegC, RegMap&: SrcRegMap);
755 if (FromRegC) {
756 Register RegA = MI->getOperand(i: DstIdx).getReg();
757 SrcRegMap[RegA] = FromRegC;
758 }
759
760 return true;
761}
762
763/// Return true if it is profitable to convert the given 2-address instruction
764/// to a 3-address one.
765bool TwoAddressInstructionImpl::isProfitableToConv3Addr(Register RegA,
766 Register RegB) {
767 // Look for situations like this:
768 // %reg1024 = MOV r1
769 // %reg1025 = MOV r0
770 // %reg1026 = ADD %reg1024, %reg1025
771 // r2 = MOV %reg1026
772 // Turn ADD into a 3-address instruction to avoid a copy.
773 MCRegister FromRegB = getMappedReg(Reg: RegB, RegMap&: SrcRegMap);
774 if (!FromRegB)
775 return false;
776 MCRegister ToRegA = getMappedReg(Reg: RegA, RegMap&: DstRegMap);
777 return (ToRegA && !regsAreCompatible(RegA: FromRegB, RegB: ToRegA));
778}
779
780/// Convert the specified two-address instruction into a three address one.
781/// Return true if this transformation was successful.
782bool TwoAddressInstructionImpl::convertInstTo3Addr(
783 MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi,
784 Register RegA, Register RegB, unsigned &Dist) {
785 MachineInstrSpan MIS(mi, MBB);
786 MachineInstr *NewMI = TII->convertToThreeAddress(MI&: *mi, LV, LIS);
787 if (!NewMI)
788 return false;
789
790 for (MachineInstr &MI : MIS)
791 DistanceMap.insert(KV: std::make_pair(x: &MI, y: Dist++));
792
793 if (&*mi == NewMI) {
794 LLVM_DEBUG(dbgs() << "2addr: CONVERTED IN-PLACE TO 3-ADDR: " << *mi);
795 } else {
796 LLVM_DEBUG({
797 dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi;
798 dbgs() << "2addr: TO 3-ADDR: " << *NewMI;
799 });
800
801 // If the old instruction is debug value tracked, an update is required.
802 if (auto OldInstrNum = mi->peekDebugInstrNum()) {
803 assert(mi->getNumExplicitDefs() == 1);
804 assert(NewMI->getNumExplicitDefs() == 1);
805
806 // Find the old and new def location.
807 unsigned OldIdx = mi->defs().begin()->getOperandNo();
808 unsigned NewIdx = NewMI->defs().begin()->getOperandNo();
809
810 // Record that one def has been replaced by the other.
811 unsigned NewInstrNum = NewMI->getDebugInstrNum();
812 MF->makeDebugValueSubstitution(std::make_pair(x&: OldInstrNum, y&: OldIdx),
813 std::make_pair(x&: NewInstrNum, y&: NewIdx));
814 }
815
816 MBB->erase(I: mi); // Nuke the old inst.
817 Dist--;
818 }
819
820 mi = NewMI;
821 nmi = std::next(x: mi);
822
823 // Update source and destination register maps.
824 SrcRegMap.erase(Val: RegA);
825 DstRegMap.erase(Val: RegB);
826 return true;
827}
828
829/// Scan forward recursively for only uses, update maps if the use is a copy or
830/// a two-address instruction.
831void TwoAddressInstructionImpl::scanUses(Register DstReg) {
832 SmallVector<Register, 4> VirtRegPairs;
833 bool IsDstPhys;
834 bool IsCopy = false;
835 Register NewReg;
836 Register Reg = DstReg;
837 while (MachineInstr *UseMI =
838 findOnlyInterestingUse(Reg, MBB, IsCopy, DstReg&: NewReg, IsDstPhys)) {
839 if (IsCopy && !Processed.insert(Ptr: UseMI).second)
840 break;
841
842 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(Val: UseMI);
843 if (DI != DistanceMap.end())
844 // Earlier in the same MBB.Reached via a back edge.
845 break;
846
847 if (IsDstPhys) {
848 VirtRegPairs.push_back(Elt: NewReg);
849 break;
850 }
851 SrcRegMap[NewReg] = Reg;
852 VirtRegPairs.push_back(Elt: NewReg);
853 Reg = NewReg;
854 }
855
856 if (!VirtRegPairs.empty()) {
857 Register ToReg = VirtRegPairs.pop_back_val();
858 while (!VirtRegPairs.empty()) {
859 Register FromReg = VirtRegPairs.pop_back_val();
860 bool isNew = DstRegMap.insert(KV: std::make_pair(x&: FromReg, y&: ToReg)).second;
861 if (!isNew)
862 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
863 ToReg = FromReg;
864 }
865 bool isNew = DstRegMap.insert(KV: std::make_pair(x&: DstReg, y&: ToReg)).second;
866 if (!isNew)
867 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
868 }
869}
870
871/// If the specified instruction is not yet processed, process it if it's a
872/// copy. For a copy instruction, we find the physical registers the
873/// source and destination registers might be mapped to. These are kept in
874/// point-to maps used to determine future optimizations. e.g.
875/// v1024 = mov r0
876/// v1025 = mov r1
877/// v1026 = add v1024, v1025
878/// r1 = mov r1026
879/// If 'add' is a two-address instruction, v1024, v1026 are both potentially
880/// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
881/// potentially joined with r1 on the output side. It's worthwhile to commute
882/// 'add' to eliminate a copy.
883void TwoAddressInstructionImpl::processCopy(MachineInstr *MI) {
884 if (Processed.count(Ptr: MI))
885 return;
886
887 bool IsSrcPhys, IsDstPhys;
888 Register SrcReg, DstReg;
889 if (!isCopyToReg(MI&: *MI, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
890 return;
891
892 if (IsDstPhys && !IsSrcPhys) {
893 DstRegMap.insert(KV: std::make_pair(x&: SrcReg, y&: DstReg));
894 } else if (!IsDstPhys && IsSrcPhys) {
895 bool isNew = SrcRegMap.insert(KV: std::make_pair(x&: DstReg, y&: SrcReg)).second;
896 if (!isNew)
897 assert(SrcRegMap[DstReg] == SrcReg &&
898 "Can't map to two src physical registers!");
899
900 scanUses(DstReg);
901 }
902
903 Processed.insert(Ptr: MI);
904}
905
906/// If there is one more local instruction that reads 'Reg' and it kills 'Reg,
907/// consider moving the instruction below the kill instruction in order to
908/// eliminate the need for the copy.
909bool TwoAddressInstructionImpl::rescheduleMIBelowKill(
910 MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi,
911 Register Reg) {
912 // Bail immediately if we don't have LV or LIS available. We use them to find
913 // kills efficiently.
914 if (!LV && !LIS)
915 return false;
916
917 MachineInstr *MI = &*mi;
918 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(Val: MI);
919 if (DI == DistanceMap.end())
920 // Must be created from unfolded load. Don't waste time trying this.
921 return false;
922
923 MachineInstr *KillMI = nullptr;
924 if (LIS) {
925 LiveInterval &LI = LIS->getInterval(Reg);
926 assert(LI.end() != LI.begin() &&
927 "Reg should not have empty live interval.");
928
929 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(mbb: MBB).getPrevSlot();
930 LiveInterval::const_iterator I = LI.find(Pos: MBBEndIdx);
931 if (I != LI.end() && I->start < MBBEndIdx)
932 return false;
933
934 --I;
935 KillMI = LIS->getInstructionFromIndex(index: I->end);
936 } else {
937 KillMI = LV->getVarInfo(Reg).findKill(MBB);
938 }
939 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
940 // Don't mess with copies, they may be coalesced later.
941 return false;
942
943 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
944 KillMI->isBranch() || KillMI->isTerminator())
945 // Don't move pass calls, etc.
946 return false;
947
948 Register DstReg;
949 if (isTwoAddrUse(MI&: *KillMI, Reg, DstReg))
950 return false;
951
952 bool SeenStore = true;
953 if (!MI->isSafeToMove(SawStore&: SeenStore))
954 return false;
955
956 if (TII->getInstrLatency(ItinData: InstrItins, MI: *MI) > 1)
957 // FIXME: Needs more sophisticated heuristics.
958 return false;
959
960 SmallVector<Register, 2> Uses;
961 SmallVector<Register, 2> Kills;
962 SmallVector<Register, 2> Defs;
963 for (const MachineOperand &MO : MI->operands()) {
964 if (!MO.isReg())
965 continue;
966 Register MOReg = MO.getReg();
967 if (!MOReg)
968 continue;
969 if (MO.isDef())
970 Defs.push_back(Elt: MOReg);
971 else {
972 Uses.push_back(Elt: MOReg);
973 if (MOReg != Reg && isPlainlyKilled(MO))
974 Kills.push_back(Elt: MOReg);
975 }
976 }
977
978 // Move the copies connected to MI down as well.
979 MachineBasicBlock::iterator Begin = MI;
980 MachineBasicBlock::iterator AfterMI = std::next(x: Begin);
981 MachineBasicBlock::iterator End = AfterMI;
982 while (End != MBB->end()) {
983 End = skipDebugInstructionsForward(It: End, End: MBB->end());
984 if (End->isCopy() && regOverlapsSet(Set: Defs, Reg: End->getOperand(i: 1).getReg()))
985 Defs.push_back(Elt: End->getOperand(i: 0).getReg());
986 else
987 break;
988 ++End;
989 }
990
991 // Check if the reschedule will not break dependencies.
992 unsigned NumVisited = 0;
993 MachineBasicBlock::iterator KillPos = KillMI;
994 ++KillPos;
995 for (MachineInstr &OtherMI : make_range(x: End, y: KillPos)) {
996 // Debug or pseudo instructions cannot be counted against the limit.
997 if (OtherMI.isDebugOrPseudoInstr())
998 continue;
999 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
1000 return false;
1001 ++NumVisited;
1002 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
1003 OtherMI.isBranch() || OtherMI.isTerminator())
1004 // Don't move pass calls, etc.
1005 return false;
1006 for (const MachineOperand &MO : OtherMI.operands()) {
1007 if (!MO.isReg())
1008 continue;
1009 Register MOReg = MO.getReg();
1010 if (!MOReg)
1011 continue;
1012 if (MO.isDef()) {
1013 if (regOverlapsSet(Set: Uses, Reg: MOReg))
1014 // Physical register use would be clobbered.
1015 return false;
1016 if (!MO.isDead() && regOverlapsSet(Set: Defs, Reg: MOReg))
1017 // May clobber a physical register def.
1018 // FIXME: This may be too conservative. It's ok if the instruction
1019 // is sunken completely below the use.
1020 return false;
1021 } else {
1022 if (regOverlapsSet(Set: Defs, Reg: MOReg))
1023 return false;
1024 bool isKill = isPlainlyKilled(MO);
1025 if (MOReg != Reg && ((isKill && regOverlapsSet(Set: Uses, Reg: MOReg)) ||
1026 regOverlapsSet(Set: Kills, Reg: MOReg)))
1027 // Don't want to extend other live ranges and update kills.
1028 return false;
1029 if (MOReg == Reg && !isKill)
1030 // We can't schedule across a use of the register in question.
1031 return false;
1032 // Ensure that if this is register in question, its the kill we expect.
1033 assert((MOReg != Reg || &OtherMI == KillMI) &&
1034 "Found multiple kills of a register in a basic block");
1035 }
1036 }
1037 }
1038
1039 // Move debug info as well.
1040 while (Begin != MBB->begin() && std::prev(x: Begin)->isDebugInstr())
1041 --Begin;
1042
1043 nmi = End;
1044 MachineBasicBlock::iterator InsertPos = KillPos;
1045 if (LIS) {
1046 // We have to move the copies (and any interleaved debug instructions)
1047 // first so that the MBB is still well-formed when calling handleMove().
1048 for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
1049 auto CopyMI = MBBI++;
1050 MBB->splice(Where: InsertPos, Other: MBB, From: CopyMI);
1051 if (!CopyMI->isDebugOrPseudoInstr())
1052 LIS->handleMove(MI&: *CopyMI);
1053 InsertPos = CopyMI;
1054 }
1055 End = std::next(x: MachineBasicBlock::iterator(MI));
1056 }
1057
1058 // Copies following MI may have been moved as well.
1059 MBB->splice(Where: InsertPos, Other: MBB, From: Begin, To: End);
1060 DistanceMap.erase(I: DI);
1061
1062 // Update live variables
1063 if (LIS) {
1064 LIS->handleMove(MI&: *MI);
1065 } else {
1066 LV->removeVirtualRegisterKilled(Reg, MI&: *KillMI);
1067 LV->addVirtualRegisterKilled(IncomingReg: Reg, MI&: *MI);
1068 }
1069
1070 LLVM_DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
1071 return true;
1072}
1073
1074/// Return true if the re-scheduling will put the given instruction too close
1075/// to the defs of its register dependencies.
1076bool TwoAddressInstructionImpl::isDefTooClose(Register Reg, unsigned Dist,
1077 MachineInstr *MI) {
1078 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
1079 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())
1080 continue;
1081 if (&DefMI == MI)
1082 return true; // MI is defining something KillMI uses
1083 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(Val: &DefMI);
1084 if (DDI == DistanceMap.end())
1085 return true; // Below MI
1086 unsigned DefDist = DDI->second;
1087 assert(Dist > DefDist && "Visited def already?");
1088 if (TII->getInstrLatency(ItinData: InstrItins, MI: DefMI) > (Dist - DefDist))
1089 return true;
1090 }
1091 return false;
1092}
1093
1094/// If there is one more local instruction that reads 'Reg' and it kills 'Reg,
1095/// consider moving the kill instruction above the current two-address
1096/// instruction in order to eliminate the need for the copy.
1097bool TwoAddressInstructionImpl::rescheduleKillAboveMI(
1098 MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi,
1099 Register Reg) {
1100 // Bail immediately if we don't have LV or LIS available. We use them to find
1101 // kills efficiently.
1102 if (!LV && !LIS)
1103 return false;
1104
1105 MachineInstr *MI = &*mi;
1106 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(Val: MI);
1107 if (DI == DistanceMap.end())
1108 // Must be created from unfolded load. Don't waste time trying this.
1109 return false;
1110
1111 MachineInstr *KillMI = nullptr;
1112 if (LIS) {
1113 LiveInterval &LI = LIS->getInterval(Reg);
1114 assert(LI.end() != LI.begin() &&
1115 "Reg should not have empty live interval.");
1116
1117 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(mbb: MBB).getPrevSlot();
1118 LiveInterval::const_iterator I = LI.find(Pos: MBBEndIdx);
1119 if (I != LI.end() && I->start < MBBEndIdx)
1120 return false;
1121
1122 --I;
1123 KillMI = LIS->getInstructionFromIndex(index: I->end);
1124 } else {
1125 KillMI = LV->getVarInfo(Reg).findKill(MBB);
1126 }
1127 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
1128 // Don't mess with copies, they may be coalesced later.
1129 return false;
1130
1131 Register DstReg;
1132 if (isTwoAddrUse(MI&: *KillMI, Reg, DstReg))
1133 return false;
1134
1135 bool SeenStore = true;
1136 if (!KillMI->isSafeToMove(SawStore&: SeenStore))
1137 return false;
1138
1139 SmallVector<Register, 2> Uses;
1140 SmallVector<Register, 2> Kills;
1141 SmallVector<Register, 2> Defs;
1142 SmallVector<Register, 2> LiveDefs;
1143 for (const MachineOperand &MO : KillMI->operands()) {
1144 if (!MO.isReg())
1145 continue;
1146 Register MOReg = MO.getReg();
1147 if (MO.isUse()) {
1148 if (!MOReg)
1149 continue;
1150 if (isDefTooClose(Reg: MOReg, Dist: DI->second, MI))
1151 return false;
1152 bool isKill = isPlainlyKilled(MO);
1153 if (MOReg == Reg && !isKill)
1154 return false;
1155 Uses.push_back(Elt: MOReg);
1156 if (isKill && MOReg != Reg)
1157 Kills.push_back(Elt: MOReg);
1158 } else if (MOReg.isPhysical()) {
1159 Defs.push_back(Elt: MOReg);
1160 if (!MO.isDead())
1161 LiveDefs.push_back(Elt: MOReg);
1162 }
1163 }
1164
1165 // Check if the reschedule will not break dependencies.
1166 unsigned NumVisited = 0;
1167 for (MachineInstr &OtherMI :
1168 make_range(x: mi, y: MachineBasicBlock::iterator(KillMI))) {
1169 // Debug or pseudo instructions cannot be counted against the limit.
1170 if (OtherMI.isDebugOrPseudoInstr())
1171 continue;
1172 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
1173 return false;
1174 ++NumVisited;
1175 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
1176 OtherMI.isBranch() || OtherMI.isTerminator())
1177 // Don't move pass calls, etc.
1178 return false;
1179 SmallVector<Register, 2> OtherDefs;
1180 for (const MachineOperand &MO : OtherMI.operands()) {
1181 if (!MO.isReg())
1182 continue;
1183 Register MOReg = MO.getReg();
1184 if (!MOReg)
1185 continue;
1186 if (MO.isUse()) {
1187 if (regOverlapsSet(Set: Defs, Reg: MOReg))
1188 // Moving KillMI can clobber the physical register if the def has
1189 // not been seen.
1190 return false;
1191 if (regOverlapsSet(Set: Kills, Reg: MOReg))
1192 // Don't want to extend other live ranges and update kills.
1193 return false;
1194 if (&OtherMI != MI && MOReg == Reg && !isPlainlyKilled(MO))
1195 // We can't schedule across a use of the register in question.
1196 return false;
1197 } else {
1198 OtherDefs.push_back(Elt: MOReg);
1199 }
1200 }
1201
1202 for (Register MOReg : OtherDefs) {
1203 if (regOverlapsSet(Set: Uses, Reg: MOReg))
1204 return false;
1205 if (MOReg.isPhysical() && regOverlapsSet(Set: LiveDefs, Reg: MOReg))
1206 return false;
1207 // Physical register def is seen.
1208 llvm::erase(C&: Defs, V: MOReg);
1209 }
1210 }
1211
1212 // Move the old kill above MI, don't forget to move debug info as well.
1213 MachineBasicBlock::iterator InsertPos = mi;
1214 while (InsertPos != MBB->begin() && std::prev(x: InsertPos)->isDebugInstr())
1215 --InsertPos;
1216 MachineBasicBlock::iterator From = KillMI;
1217 MachineBasicBlock::iterator To = std::next(x: From);
1218 while (std::prev(x: From)->isDebugInstr())
1219 --From;
1220 MBB->splice(Where: InsertPos, Other: MBB, From, To);
1221
1222 nmi = std::prev(x: InsertPos); // Backtrack so we process the moved instr.
1223 DistanceMap.erase(I: DI);
1224
1225 // Update live variables
1226 if (LIS) {
1227 LIS->handleMove(MI&: *KillMI);
1228 } else {
1229 LV->removeVirtualRegisterKilled(Reg, MI&: *KillMI);
1230 LV->addVirtualRegisterKilled(IncomingReg: Reg, MI&: *MI);
1231 }
1232
1233 LLVM_DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
1234 return true;
1235}
1236
1237/// Tries to commute the operand 'BaseOpIdx' and some other operand in the
1238/// given machine instruction to improve opportunities for coalescing and
1239/// elimination of a register to register copy.
1240///
1241/// 'DstOpIdx' specifies the index of MI def operand.
1242/// 'BaseOpKilled' specifies if the register associated with 'BaseOpIdx'
1243/// operand is killed by the given instruction.
1244/// The 'Dist' arguments provides the distance of MI from the start of the
1245/// current basic block and it is used to determine if it is profitable
1246/// to commute operands in the instruction.
1247///
1248/// Returns true if the transformation happened. Otherwise, returns false.
1249bool TwoAddressInstructionImpl::tryInstructionCommute(MachineInstr *MI,
1250 unsigned DstOpIdx,
1251 unsigned BaseOpIdx,
1252 bool BaseOpKilled,
1253 unsigned Dist) {
1254 if (!MI->isCommutable())
1255 return false;
1256
1257 bool MadeChange = false;
1258 Register DstOpReg = MI->getOperand(i: DstOpIdx).getReg();
1259 Register BaseOpReg = MI->getOperand(i: BaseOpIdx).getReg();
1260 unsigned OpsNum = MI->getDesc().getNumOperands();
1261 unsigned OtherOpIdx = MI->getDesc().getNumDefs();
1262 for (; OtherOpIdx < OpsNum; OtherOpIdx++) {
1263 // The call of findCommutedOpIndices below only checks if BaseOpIdx
1264 // and OtherOpIdx are commutable, it does not really search for
1265 // other commutable operands and does not change the values of passed
1266 // variables.
1267 if (OtherOpIdx == BaseOpIdx || !MI->getOperand(i: OtherOpIdx).isReg() ||
1268 !TII->findCommutedOpIndices(MI: *MI, SrcOpIdx1&: BaseOpIdx, SrcOpIdx2&: OtherOpIdx))
1269 continue;
1270
1271 Register OtherOpReg = MI->getOperand(i: OtherOpIdx).getReg();
1272 bool AggressiveCommute = false;
1273
1274 // If OtherOp dies but BaseOp does not, swap the OtherOp and BaseOp
1275 // operands. This makes the live ranges of DstOp and OtherOp joinable.
1276 bool OtherOpKilled = isKilled(MI&: *MI, Reg: OtherOpReg, allowFalsePositives: false);
1277 bool DoCommute = !BaseOpKilled && OtherOpKilled;
1278
1279 if (!DoCommute &&
1280 isProfitableToCommute(RegA: DstOpReg, RegB: BaseOpReg, RegC: OtherOpReg, MI, Dist)) {
1281 DoCommute = true;
1282 AggressiveCommute = true;
1283 }
1284
1285 // If it's profitable to commute, try to do so.
1286 if (DoCommute && commuteInstruction(MI, DstIdx: DstOpIdx, RegBIdx: BaseOpIdx, RegCIdx: OtherOpIdx,
1287 Dist)) {
1288 MadeChange = true;
1289 ++NumCommuted;
1290 if (AggressiveCommute)
1291 ++NumAggrCommuted;
1292
1293 // There might be more than two commutable operands, update BaseOp and
1294 // continue scanning.
1295 // FIXME: This assumes that the new instruction's operands are in the
1296 // same positions and were simply swapped.
1297 BaseOpReg = OtherOpReg;
1298 BaseOpKilled = OtherOpKilled;
1299 // Resamples OpsNum in case the number of operands was reduced. This
1300 // happens with X86.
1301 OpsNum = MI->getDesc().getNumOperands();
1302 }
1303 }
1304 return MadeChange;
1305}
1306
1307/// For the case where an instruction has a single pair of tied register
1308/// operands, attempt some transformations that may either eliminate the tied
1309/// operands or improve the opportunities for coalescing away the register copy.
1310/// Returns true if no copy needs to be inserted to untie mi's operands
1311/// (either because they were untied, or because mi was rescheduled, and will
1312/// be visited again later). If the shouldOnlyCommute flag is true, only
1313/// instruction commutation is attempted.
1314bool TwoAddressInstructionImpl::tryInstructionTransform(
1315 MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi,
1316 unsigned SrcIdx, unsigned DstIdx, unsigned &Dist, bool shouldOnlyCommute) {
1317 if (OptLevel == CodeGenOptLevel::None)
1318 return false;
1319
1320 MachineInstr &MI = *mi;
1321 Register regA = MI.getOperand(i: DstIdx).getReg();
1322 Register regB = MI.getOperand(i: SrcIdx).getReg();
1323
1324 assert(regB.isVirtual() && "cannot make instruction into two-address form");
1325 bool regBKilled = isKilled(MI, Reg: regB, allowFalsePositives: true);
1326
1327 if (regA.isVirtual())
1328 scanUses(DstReg: regA);
1329
1330 bool Commuted = tryInstructionCommute(MI: &MI, DstOpIdx: DstIdx, BaseOpIdx: SrcIdx, BaseOpKilled: regBKilled, Dist);
1331
1332 // Give targets a chance to convert bundled instructions.
1333 bool ConvertibleTo3Addr = MI.isConvertibleTo3Addr(Type: MachineInstr::AnyInBundle);
1334
1335 // If the instruction is convertible to 3 Addr, instead
1336 // of returning try 3 Addr transformation aggressively and
1337 // use this variable to check later. Because it might be better.
1338 // For example, we can just use `leal (%rsi,%rdi), %eax` and `ret`
1339 // instead of the following code.
1340 // addl %esi, %edi
1341 // movl %edi, %eax
1342 // ret
1343 if (Commuted && !ConvertibleTo3Addr)
1344 return false;
1345
1346 if (shouldOnlyCommute)
1347 return false;
1348
1349 // If there is one more use of regB later in the same MBB, consider
1350 // re-schedule this MI below it.
1351 if (!Commuted && EnableRescheduling && rescheduleMIBelowKill(mi, nmi, Reg: regB)) {
1352 ++NumReSchedDowns;
1353 return true;
1354 }
1355
1356 // If we commuted, regB may have changed so we should re-sample it to avoid
1357 // confusing the three address conversion below.
1358 if (Commuted) {
1359 regB = MI.getOperand(i: SrcIdx).getReg();
1360 regBKilled = isKilled(MI, Reg: regB, allowFalsePositives: true);
1361 }
1362
1363 if (ConvertibleTo3Addr) {
1364 // This instruction is potentially convertible to a true
1365 // three-address instruction. Check if it is profitable.
1366 if (!regBKilled || isProfitableToConv3Addr(RegA: regA, RegB: regB)) {
1367 // Try to convert it.
1368 if (convertInstTo3Addr(mi, nmi, RegA: regA, RegB: regB, Dist)) {
1369 ++NumConvertedTo3Addr;
1370 return true; // Done with this instruction.
1371 }
1372 }
1373 }
1374
1375 // Return if it is commuted but 3 addr conversion is failed.
1376 if (Commuted)
1377 return false;
1378
1379 // If there is one more use of regB later in the same MBB, consider
1380 // re-schedule it before this MI if it's legal.
1381 if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, Reg: regB)) {
1382 ++NumReSchedUps;
1383 return true;
1384 }
1385
1386 // If this is an instruction with a load folded into it, try unfolding
1387 // the load, e.g. avoid this:
1388 // movq %rdx, %rcx
1389 // addq (%rax), %rcx
1390 // in favor of this:
1391 // movq (%rax), %rcx
1392 // addq %rdx, %rcx
1393 // because it's preferable to schedule a load than a register copy.
1394 if (MI.mayLoad() && !regBKilled) {
1395 // Determine if a load can be unfolded.
1396 unsigned LoadRegIndex;
1397 unsigned NewOpc =
1398 TII->getOpcodeAfterMemoryUnfold(Opc: MI.getOpcode(),
1399 /*UnfoldLoad=*/true,
1400 /*UnfoldStore=*/false,
1401 LoadRegIndex: &LoadRegIndex);
1402 if (NewOpc != 0) {
1403 const MCInstrDesc &UnfoldMCID = TII->get(Opcode: NewOpc);
1404 if (UnfoldMCID.getNumDefs() == 1) {
1405 // Unfold the load.
1406 LLVM_DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
1407 const TargetRegisterClass *RC = TRI->getAllocatableClass(
1408 RC: TII->getRegClass(MCID: UnfoldMCID, OpNum: LoadRegIndex));
1409 Register Reg = MRI->createVirtualRegister(RegClass: RC);
1410 SmallVector<MachineInstr *, 2> NewMIs;
1411 if (!TII->unfoldMemoryOperand(MF&: *MF, MI, Reg,
1412 /*UnfoldLoad=*/true,
1413 /*UnfoldStore=*/false, NewMIs)) {
1414 LLVM_DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1415 return false;
1416 }
1417 assert(NewMIs.size() == 2 &&
1418 "Unfolded a load into multiple instructions!");
1419 // The load was previously folded, so this is the only use.
1420 NewMIs[1]->addRegisterKilled(IncomingReg: Reg, RegInfo: TRI);
1421
1422 // Tentatively insert the instructions into the block so that they
1423 // look "normal" to the transformation logic.
1424 MBB->insert(I: mi, MI: NewMIs[0]);
1425 MBB->insert(I: mi, MI: NewMIs[1]);
1426 DistanceMap.insert(KV: std::make_pair(x&: NewMIs[0], y: Dist++));
1427 DistanceMap.insert(KV: std::make_pair(x&: NewMIs[1], y&: Dist));
1428
1429 LLVM_DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1430 << "2addr: NEW INST: " << *NewMIs[1]);
1431
1432 // Transform the instruction, now that it no longer has a load.
1433 unsigned NewDstIdx =
1434 NewMIs[1]->findRegisterDefOperandIdx(Reg: regA, /*TRI=*/nullptr);
1435 unsigned NewSrcIdx =
1436 NewMIs[1]->findRegisterUseOperandIdx(Reg: regB, /*TRI=*/nullptr);
1437 MachineBasicBlock::iterator NewMI = NewMIs[1];
1438 bool TransformResult =
1439 tryInstructionTransform(mi&: NewMI, nmi&: mi, SrcIdx: NewSrcIdx, DstIdx: NewDstIdx, Dist, shouldOnlyCommute: true);
1440 (void)TransformResult;
1441 assert(!TransformResult &&
1442 "tryInstructionTransform() should return false.");
1443 if (NewMIs[1]->getOperand(i: NewSrcIdx).isKill()) {
1444 // Success, or at least we made an improvement. Keep the unfolded
1445 // instructions and discard the original.
1446 if (LV) {
1447 for (const MachineOperand &MO : MI.operands()) {
1448 if (MO.isReg() && MO.getReg().isVirtual()) {
1449 if (MO.isUse()) {
1450 if (MO.isKill()) {
1451 if (NewMIs[0]->killsRegister(Reg: MO.getReg(), /*TRI=*/nullptr))
1452 LV->replaceKillInstruction(Reg: MO.getReg(), OldMI&: MI, NewMI&: *NewMIs[0]);
1453 else {
1454 assert(NewMIs[1]->killsRegister(MO.getReg(),
1455 /*TRI=*/nullptr) &&
1456 "Kill missing after load unfold!");
1457 LV->replaceKillInstruction(Reg: MO.getReg(), OldMI&: MI, NewMI&: *NewMIs[1]);
1458 }
1459 }
1460 } else if (LV->removeVirtualRegisterDead(Reg: MO.getReg(), MI)) {
1461 if (NewMIs[1]->registerDefIsDead(Reg: MO.getReg(),
1462 /*TRI=*/nullptr))
1463 LV->addVirtualRegisterDead(IncomingReg: MO.getReg(), MI&: *NewMIs[1]);
1464 else {
1465 assert(NewMIs[0]->registerDefIsDead(MO.getReg(),
1466 /*TRI=*/nullptr) &&
1467 "Dead flag missing after load unfold!");
1468 LV->addVirtualRegisterDead(IncomingReg: MO.getReg(), MI&: *NewMIs[0]);
1469 }
1470 }
1471 }
1472 }
1473 LV->addVirtualRegisterKilled(IncomingReg: Reg, MI&: *NewMIs[1]);
1474 }
1475
1476 SmallVector<Register, 4> OrigRegs;
1477 if (LIS) {
1478 for (const MachineOperand &MO : MI.operands()) {
1479 if (MO.isReg())
1480 OrigRegs.push_back(Elt: MO.getReg());
1481 }
1482
1483 LIS->RemoveMachineInstrFromMaps(MI);
1484 }
1485
1486 MI.eraseFromParent();
1487 DistanceMap.erase(Val: &MI);
1488
1489 // Update LiveIntervals.
1490 if (LIS) {
1491 MachineBasicBlock::iterator Begin(NewMIs[0]);
1492 MachineBasicBlock::iterator End(NewMIs[1]);
1493 LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);
1494 }
1495
1496 mi = NewMIs[1];
1497 } else {
1498 // Transforming didn't eliminate the tie and didn't lead to an
1499 // improvement. Clean up the unfolded instructions and keep the
1500 // original.
1501 LLVM_DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1502 NewMIs[0]->eraseFromParent();
1503 NewMIs[1]->eraseFromParent();
1504 DistanceMap.erase(Val: NewMIs[0]);
1505 DistanceMap.erase(Val: NewMIs[1]);
1506 Dist--;
1507 }
1508 }
1509 }
1510 }
1511
1512 return false;
1513}
1514
1515// Collect tied operands of MI that need to be handled.
1516// Rewrite trivial cases immediately.
1517// Return true if any tied operands where found, including the trivial ones.
1518bool TwoAddressInstructionImpl::collectTiedOperands(
1519 MachineInstr *MI, TiedOperandMap &TiedOperands) {
1520 bool AnyOps = false;
1521 unsigned NumOps = MI->getNumOperands();
1522
1523 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1524 unsigned DstIdx = 0;
1525 if (!MI->isRegTiedToDefOperand(UseOpIdx: SrcIdx, DefOpIdx: &DstIdx))
1526 continue;
1527 AnyOps = true;
1528 MachineOperand &SrcMO = MI->getOperand(i: SrcIdx);
1529 MachineOperand &DstMO = MI->getOperand(i: DstIdx);
1530 Register SrcReg = SrcMO.getReg();
1531 Register DstReg = DstMO.getReg();
1532 // Tied constraint already satisfied?
1533 if (SrcReg == DstReg)
1534 continue;
1535
1536 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
1537
1538 // Deal with undef uses immediately - simply rewrite the src operand.
1539 if (SrcMO.isUndef() && !DstMO.getSubReg()) {
1540 // Constrain the DstReg register class if required.
1541 if (DstReg.isVirtual()) {
1542 const TargetRegisterClass *RC = MRI->getRegClass(Reg: SrcReg);
1543 MRI->constrainRegClass(Reg: DstReg, RC);
1544 }
1545 SrcMO.setReg(DstReg);
1546 SrcMO.setSubReg(0);
1547 LLVM_DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
1548 continue;
1549 }
1550 TiedOperands[SrcReg].push_back(Elt: std::make_pair(x&: SrcIdx, y&: DstIdx));
1551 }
1552 return AnyOps;
1553}
1554
1555// Process a list of tied MI operands that all use the same source register.
1556// The tied pairs are of the form (SrcIdx, DstIdx).
1557void TwoAddressInstructionImpl::processTiedPairs(MachineInstr *MI,
1558 TiedPairList &TiedPairs,
1559 unsigned &Dist) {
1560 bool IsEarlyClobber = llvm::any_of(Range&: TiedPairs, P: [MI](auto const &TP) {
1561 return MI->getOperand(TP.second).isEarlyClobber();
1562 });
1563
1564 bool RemovedKillFlag = false;
1565 bool AllUsesCopied = true;
1566 Register LastCopiedReg;
1567 SlotIndex LastCopyIdx;
1568 Register RegB = 0;
1569 unsigned SubRegB = 0;
1570 for (auto &TP : TiedPairs) {
1571 unsigned SrcIdx = TP.first;
1572 unsigned DstIdx = TP.second;
1573
1574 const MachineOperand &DstMO = MI->getOperand(i: DstIdx);
1575 Register RegA = DstMO.getReg();
1576
1577 // Grab RegB from the instruction because it may have changed if the
1578 // instruction was commuted.
1579 RegB = MI->getOperand(i: SrcIdx).getReg();
1580 SubRegB = MI->getOperand(i: SrcIdx).getSubReg();
1581
1582 if (RegA == RegB) {
1583 // The register is tied to multiple destinations (or else we would
1584 // not have continued this far), but this use of the register
1585 // already matches the tied destination. Leave it.
1586 AllUsesCopied = false;
1587 continue;
1588 }
1589 LastCopiedReg = RegA;
1590
1591 assert(RegB.isVirtual() && "cannot make instruction into two-address form");
1592
1593#ifndef NDEBUG
1594 // First, verify that we don't have a use of "a" in the instruction
1595 // (a = b + a for example) because our transformation will not
1596 // work. This should never occur because we are in SSA form.
1597 for (unsigned i = 0; i != MI->getNumOperands(); ++i)
1598 assert(i == DstIdx ||
1599 !MI->getOperand(i).isReg() ||
1600 MI->getOperand(i).getReg() != RegA);
1601#endif
1602
1603 // Emit a copy.
1604 MachineInstrBuilder MIB = BuildMI(BB&: *MI->getParent(), I: MI, MIMD: MI->getDebugLoc(),
1605 MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: RegA);
1606 // If this operand is folding a truncation, the truncation now moves to the
1607 // copy so that the register classes remain valid for the operands.
1608 MIB.addReg(RegNo: RegB, Flags: {}, SubReg: SubRegB);
1609 const TargetRegisterClass *RC = MRI->getRegClass(Reg: RegB);
1610 if (SubRegB) {
1611 if (RegA.isVirtual()) {
1612 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1613 SubRegB) &&
1614 "tied subregister must be a truncation");
1615 // The superreg class will not be used to constrain the subreg class.
1616 RC = nullptr;
1617 } else {
1618 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
1619 && "tied subregister must be a truncation");
1620 }
1621 }
1622
1623 // Update DistanceMap.
1624 MachineBasicBlock::iterator PrevMI = MI;
1625 --PrevMI;
1626 DistanceMap.insert(KV: std::make_pair(x: &*PrevMI, y&: Dist));
1627 DistanceMap[MI] = ++Dist;
1628
1629 if (LIS) {
1630 LastCopyIdx = LIS->InsertMachineInstrInMaps(MI&: *PrevMI).getRegSlot();
1631
1632 SlotIndex endIdx =
1633 LIS->getInstructionIndex(Instr: *MI).getRegSlot(EC: IsEarlyClobber);
1634 if (RegA.isVirtual()) {
1635 LiveInterval &LI = LIS->getInterval(Reg: RegA);
1636 VNInfo *VNI = LI.getNextValue(Def: LastCopyIdx, VNInfoAllocator&: LIS->getVNInfoAllocator());
1637 LI.addSegment(S: LiveRange::Segment(LastCopyIdx, endIdx, VNI));
1638 for (auto &S : LI.subranges()) {
1639 VNI = S.getNextValue(Def: LastCopyIdx, VNInfoAllocator&: LIS->getVNInfoAllocator());
1640 S.addSegment(S: LiveRange::Segment(LastCopyIdx, endIdx, VNI));
1641 }
1642 } else {
1643 for (MCRegUnit Unit : TRI->regunits(Reg: RegA)) {
1644 if (LiveRange *LR = LIS->getCachedRegUnit(Unit)) {
1645 VNInfo *VNI =
1646 LR->getNextValue(Def: LastCopyIdx, VNInfoAllocator&: LIS->getVNInfoAllocator());
1647 LR->addSegment(S: LiveRange::Segment(LastCopyIdx, endIdx, VNI));
1648 }
1649 }
1650 }
1651 }
1652
1653 LLVM_DEBUG(dbgs() << "\t\tprepend:\t" << *MIB);
1654
1655 MachineOperand &MO = MI->getOperand(i: SrcIdx);
1656 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1657 "inconsistent operand info for 2-reg pass");
1658 if (isPlainlyKilled(MO)) {
1659 MO.setIsKill(false);
1660 RemovedKillFlag = true;
1661 }
1662
1663 // Make sure regA is a legal regclass for the SrcIdx operand.
1664 if (RegA.isVirtual() && RegB.isVirtual())
1665 MRI->constrainRegClass(Reg: RegA, RC);
1666 MO.setReg(RegA);
1667 // The getMatchingSuper asserts guarantee that the register class projected
1668 // by SubRegB is compatible with RegA with no subregister. So regardless of
1669 // whether the dest oper writes a subreg, the source oper should not.
1670 MO.setSubReg(0);
1671
1672 // Update uses of RegB to uses of RegA inside the bundle.
1673 if (MI->isBundle()) {
1674 for (MachineOperand &MO : mi_bundle_ops(MI&: *MI)) {
1675 if (MO.isReg() && MO.getReg() == RegB) {
1676 assert(MO.getSubReg() == 0 && SubRegB == 0 &&
1677 "tied subregister uses in bundled instructions not supported");
1678 MO.setReg(RegA);
1679 }
1680 }
1681 }
1682 }
1683
1684 if (AllUsesCopied) {
1685 LaneBitmask RemainingUses = LaneBitmask::getNone();
1686 // Replace other (un-tied) uses of regB with LastCopiedReg.
1687 for (MachineOperand &MO : MI->all_uses()) {
1688 if (MO.getReg() == RegB) {
1689 if (MO.getSubReg() == SubRegB && !IsEarlyClobber) {
1690 if (isPlainlyKilled(MO)) {
1691 MO.setIsKill(false);
1692 RemovedKillFlag = true;
1693 }
1694 MO.setReg(LastCopiedReg);
1695 MO.setSubReg(0);
1696 } else {
1697 RemainingUses |= TRI->getSubRegIndexLaneMask(SubIdx: MO.getSubReg());
1698 }
1699 }
1700 }
1701
1702 // Update live variables for regB.
1703 if (RemovedKillFlag && RemainingUses.none() && LV &&
1704 LV->getVarInfo(Reg: RegB).removeKill(MI&: *MI)) {
1705 MachineBasicBlock::iterator PrevMI = MI;
1706 --PrevMI;
1707 LV->addVirtualRegisterKilled(IncomingReg: RegB, MI&: *PrevMI);
1708 }
1709
1710 if (RemovedKillFlag && RemainingUses.none())
1711 SrcRegMap[LastCopiedReg] = RegB;
1712
1713 // Update LiveIntervals.
1714 if (LIS) {
1715 SlotIndex UseIdx = LIS->getInstructionIndex(Instr: *MI);
1716 auto Shrink = [=](LiveRange &LR, LaneBitmask LaneMask) {
1717 LiveRange::Segment *S = LR.getSegmentContaining(Idx: LastCopyIdx);
1718 if (!S)
1719 return true;
1720 if ((LaneMask & RemainingUses).any())
1721 return false;
1722 if (S->end.getBaseIndex() != UseIdx)
1723 return false;
1724 S->end = LastCopyIdx;
1725 return true;
1726 };
1727
1728 LiveInterval &LI = LIS->getInterval(Reg: RegB);
1729 bool ShrinkLI = true;
1730 for (auto &S : LI.subranges())
1731 ShrinkLI &= Shrink(S, S.LaneMask);
1732 if (ShrinkLI)
1733 Shrink(LI, LaneBitmask::getAll());
1734 }
1735 } else if (RemovedKillFlag) {
1736 // Some tied uses of regB matched their destination registers, so
1737 // regB is still used in this instruction, but a kill flag was
1738 // removed from a different tied use of regB, so now we need to add
1739 // a kill flag to one of the remaining uses of regB.
1740 for (MachineOperand &MO : MI->all_uses()) {
1741 if (MO.getReg() == RegB) {
1742 MO.setIsKill(true);
1743 break;
1744 }
1745 }
1746 }
1747}
1748
1749// For every tied operand pair this function transforms statepoint from
1750// RegA = STATEPOINT ... RegB(tied-def N)
1751// to
1752// RegB = STATEPOINT ... RegB(tied-def N)
1753// and replaces all uses of RegA with RegB.
1754// No extra COPY instruction is necessary because tied use is killed at
1755// STATEPOINT.
1756bool TwoAddressInstructionImpl::processStatepoint(
1757 MachineInstr *MI, TiedOperandMap &TiedOperands) {
1758
1759 bool NeedCopy = false;
1760 for (auto &TO : TiedOperands) {
1761 Register RegB = TO.first;
1762 if (TO.second.size() != 1) {
1763 NeedCopy = true;
1764 continue;
1765 }
1766
1767 unsigned SrcIdx = TO.second[0].first;
1768 unsigned DstIdx = TO.second[0].second;
1769
1770 MachineOperand &DstMO = MI->getOperand(i: DstIdx);
1771 Register RegA = DstMO.getReg();
1772
1773 assert(RegB == MI->getOperand(SrcIdx).getReg());
1774
1775 if (RegA == RegB)
1776 continue;
1777
1778 // CodeGenPrepare can sink pointer compare past statepoint, which
1779 // breaks assumption that statepoint kills tied-use register when
1780 // in SSA form (see note in IR/SafepointIRVerifier.cpp). Fall back
1781 // to generic tied register handling to avoid assertion failures.
1782 // TODO: Recompute LIS/LV information for new range here.
1783 if (LIS) {
1784 const auto &UseLI = LIS->getInterval(Reg: RegB);
1785 const auto &DefLI = LIS->getInterval(Reg: RegA);
1786 if (DefLI.overlaps(other: UseLI)) {
1787 LLVM_DEBUG(dbgs() << "LIS: " << printReg(RegB, TRI, 0)
1788 << " UseLI overlaps with DefLI\n");
1789 NeedCopy = true;
1790 continue;
1791 }
1792 } else if (LV && LV->getVarInfo(Reg: RegB).findKill(MBB: MI->getParent()) != MI) {
1793 // Note that MachineOperand::isKill does not work here, because it
1794 // is set only on first register use in instruction and for statepoint
1795 // tied-use register will usually be found in preceeding deopt bundle.
1796 LLVM_DEBUG(dbgs() << "LV: " << printReg(RegB, TRI, 0)
1797 << " not killed by statepoint\n");
1798 NeedCopy = true;
1799 continue;
1800 }
1801
1802 if (!MRI->constrainRegClass(Reg: RegB, RC: MRI->getRegClass(Reg: RegA))) {
1803 LLVM_DEBUG(dbgs() << "MRI: couldn't constrain" << printReg(RegB, TRI, 0)
1804 << " to register class of " << printReg(RegA, TRI, 0)
1805 << '\n');
1806 NeedCopy = true;
1807 continue;
1808 }
1809 MRI->replaceRegWith(FromReg: RegA, ToReg: RegB);
1810
1811 if (LIS) {
1812 VNInfo::Allocator &A = LIS->getVNInfoAllocator();
1813 LiveInterval &LI = LIS->getInterval(Reg: RegB);
1814 LiveInterval &Other = LIS->getInterval(Reg: RegA);
1815 SmallVector<VNInfo *> NewVNIs;
1816 for (const VNInfo *VNI : Other.valnos) {
1817 assert(VNI->id == NewVNIs.size() && "assumed");
1818 NewVNIs.push_back(Elt: LI.createValueCopy(orig: VNI, VNInfoAllocator&: A));
1819 }
1820 for (auto &S : Other) {
1821 VNInfo *VNI = NewVNIs[S.valno->id];
1822 LiveRange::Segment NewSeg(S.start, S.end, VNI);
1823 LI.addSegment(S: NewSeg);
1824 }
1825 LIS->removeInterval(Reg: RegA);
1826 }
1827
1828 if (LV) {
1829 if (MI->getOperand(i: SrcIdx).isKill())
1830 LV->removeVirtualRegisterKilled(Reg: RegB, MI&: *MI);
1831 LiveVariables::VarInfo &SrcInfo = LV->getVarInfo(Reg: RegB);
1832 LiveVariables::VarInfo &DstInfo = LV->getVarInfo(Reg: RegA);
1833 SrcInfo.AliveBlocks |= DstInfo.AliveBlocks;
1834 DstInfo.AliveBlocks.clear();
1835 for (auto *KillMI : DstInfo.Kills)
1836 LV->addVirtualRegisterKilled(IncomingReg: RegB, MI&: *KillMI, AddIfNotFound: false);
1837 }
1838 }
1839 return !NeedCopy;
1840}
1841
1842/// Reduce two-address instructions to two operands.
1843bool TwoAddressInstructionImpl::run() {
1844 bool MadeChange = false;
1845
1846 LLVM_DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1847 LLVM_DEBUG(dbgs() << "********** Function: " << MF->getName() << '\n');
1848
1849 // This pass takes the function out of SSA form.
1850 MRI->leaveSSA();
1851
1852 // This pass will rewrite the tied-def to meet the RegConstraint.
1853 MF->getProperties().setTiedOpsRewritten();
1854
1855 TiedOperandMap TiedOperands;
1856 for (MachineBasicBlock &MBBI : *MF) {
1857 MBB = &MBBI;
1858 unsigned Dist = 0;
1859 DistanceMap.clear();
1860 SrcRegMap.clear();
1861 DstRegMap.clear();
1862 Processed.clear();
1863 for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
1864 mi != me; ) {
1865 MachineBasicBlock::iterator nmi = std::next(x: mi);
1866 // Skip debug instructions.
1867 if (mi->isDebugInstr()) {
1868 mi = nmi;
1869 continue;
1870 }
1871
1872 // Expand REG_SEQUENCE instructions. This will position mi at the first
1873 // expanded instruction.
1874 if (mi->isRegSequence()) {
1875 eliminateRegSequence(mi);
1876 MadeChange = true;
1877 }
1878
1879 DistanceMap.insert(KV: std::make_pair(x: &*mi, y&: ++Dist));
1880
1881 processCopy(MI: &*mi);
1882
1883 // First scan through all the tied register uses in this instruction
1884 // and record a list of pairs of tied operands for each register.
1885 if (!collectTiedOperands(MI: &*mi, TiedOperands)) {
1886 removeClobberedSrcRegMap(MI: &*mi);
1887 mi = nmi;
1888 continue;
1889 }
1890
1891 ++NumTwoAddressInstrs;
1892 MadeChange = true;
1893 LLVM_DEBUG(dbgs() << '\t' << *mi);
1894
1895 // If the instruction has a single pair of tied operands, try some
1896 // transformations that may either eliminate the tied operands or
1897 // improve the opportunities for coalescing away the register copy.
1898 if (TiedOperands.size() == 1) {
1899 SmallVectorImpl<std::pair<unsigned, unsigned>> &TiedPairs
1900 = TiedOperands.begin()->second;
1901 if (TiedPairs.size() == 1) {
1902 unsigned SrcIdx = TiedPairs[0].first;
1903 unsigned DstIdx = TiedPairs[0].second;
1904 Register SrcReg = mi->getOperand(i: SrcIdx).getReg();
1905 Register DstReg = mi->getOperand(i: DstIdx).getReg();
1906 if (SrcReg != DstReg &&
1907 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, shouldOnlyCommute: false)) {
1908 // The tied operands have been eliminated or shifted further down
1909 // the block to ease elimination. Continue processing with 'nmi'.
1910 TiedOperands.clear();
1911 removeClobberedSrcRegMap(MI: &*mi);
1912 mi = nmi;
1913 continue;
1914 }
1915 }
1916 }
1917
1918 if (mi->getOpcode() == TargetOpcode::STATEPOINT &&
1919 processStatepoint(MI: &*mi, TiedOperands)) {
1920 TiedOperands.clear();
1921 LLVM_DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1922 mi = nmi;
1923 continue;
1924 }
1925
1926 // Now iterate over the information collected above.
1927 for (auto &TO : TiedOperands) {
1928 processTiedPairs(MI: &*mi, TiedPairs&: TO.second, Dist);
1929 LLVM_DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1930 }
1931
1932 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1933 if (mi->isInsertSubreg()) {
1934 // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1935 // To %reg:subidx = COPY %subreg
1936 unsigned SubIdx = mi->getOperand(i: 3).getImm();
1937 mi->removeOperand(OpNo: 3);
1938 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1939 mi->getOperand(i: 0).setSubReg(SubIdx);
1940 mi->getOperand(i: 0).setIsUndef(mi->getOperand(i: 1).isUndef());
1941 mi->removeOperand(OpNo: 1);
1942 mi->setDesc(TII->get(Opcode: TargetOpcode::COPY));
1943 LLVM_DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1944
1945 // Update LiveIntervals.
1946 if (LIS) {
1947 Register Reg = mi->getOperand(i: 0).getReg();
1948 LiveInterval &LI = LIS->getInterval(Reg);
1949 if (LI.hasSubRanges()) {
1950 // The COPY no longer defines subregs of %reg except for
1951 // %reg.subidx.
1952 LaneBitmask LaneMask =
1953 TRI->getSubRegIndexLaneMask(SubIdx: mi->getOperand(i: 0).getSubReg());
1954 SlotIndex Idx = LIS->getInstructionIndex(Instr: *mi).getRegSlot();
1955 for (auto &S : LI.subranges()) {
1956 if ((S.LaneMask & LaneMask).none()) {
1957 LiveRange::iterator DefSeg = S.FindSegmentContaining(Idx);
1958 if (mi->getOperand(i: 0).isUndef()) {
1959 S.removeValNo(ValNo: DefSeg->valno);
1960 } else {
1961 LiveRange::iterator UseSeg = std::prev(x: DefSeg);
1962 S.MergeValueNumberInto(V1: DefSeg->valno, V2: UseSeg->valno);
1963 }
1964 }
1965 }
1966
1967 // The COPY no longer has a use of %reg.
1968 LIS->shrinkToUses(li: &LI);
1969 } else {
1970 // The live interval for Reg did not have subranges but now it needs
1971 // them because we have introduced a subreg def. Recompute it.
1972 LIS->removeInterval(Reg);
1973 LIS->createAndComputeVirtRegInterval(Reg);
1974 }
1975 }
1976 }
1977
1978 // Clear TiedOperands here instead of at the top of the loop
1979 // since most instructions do not have tied operands.
1980 TiedOperands.clear();
1981 removeClobberedSrcRegMap(MI: &*mi);
1982 mi = nmi;
1983 }
1984 }
1985
1986 return MadeChange;
1987}
1988
1989/// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process.
1990///
1991/// The instruction is turned into a sequence of sub-register copies:
1992///
1993/// %dst = REG_SEQUENCE %v1, ssub0, %v2, ssub1
1994///
1995/// Becomes:
1996///
1997/// undef %dst:ssub0 = COPY %v1
1998/// %dst:ssub1 = COPY %v2
1999void TwoAddressInstructionImpl::eliminateRegSequence(
2000 MachineBasicBlock::iterator &MBBI) {
2001 MachineInstr &MI = *MBBI;
2002 Register DstReg = MI.getOperand(i: 0).getReg();
2003
2004 SmallVector<Register, 4> OrigRegs;
2005 VNInfo *DefVN = nullptr;
2006 if (LIS) {
2007 OrigRegs.push_back(Elt: MI.getOperand(i: 0).getReg());
2008 for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2)
2009 OrigRegs.push_back(Elt: MI.getOperand(i).getReg());
2010 if (LIS->hasInterval(Reg: DstReg)) {
2011 DefVN = LIS->getInterval(Reg: DstReg)
2012 .Query(Idx: LIS->getInstructionIndex(Instr: MI))
2013 .valueOut();
2014 }
2015 }
2016
2017 LaneBitmask UndefLanes = LaneBitmask::getNone();
2018 bool DefEmitted = false;
2019 for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) {
2020 MachineOperand &UseMO = MI.getOperand(i);
2021 Register SrcReg = UseMO.getReg();
2022 unsigned SubIdx = MI.getOperand(i: i+1).getImm();
2023 // Nothing needs to be inserted for undef operands.
2024 if (UseMO.isUndef()) {
2025 UndefLanes |= TRI->getSubRegIndexLaneMask(SubIdx);
2026 continue;
2027 }
2028
2029 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
2030 // might insert a COPY that uses SrcReg after is was killed.
2031 bool isKill = UseMO.isKill();
2032 if (isKill)
2033 for (unsigned j = i + 2; j < e; j += 2)
2034 if (MI.getOperand(i: j).getReg() == SrcReg) {
2035 MI.getOperand(i: j).setIsKill();
2036 UseMO.setIsKill(false);
2037 isKill = false;
2038 break;
2039 }
2040
2041 // Insert the sub-register copy.
2042 MachineInstr *CopyMI = BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(),
2043 MCID: TII->get(Opcode: TargetOpcode::COPY))
2044 .addReg(RegNo: DstReg, Flags: RegState::Define, SubReg: SubIdx)
2045 .add(MO: UseMO);
2046
2047 // The first def needs an undef flag because there is no live register
2048 // before it.
2049 if (!DefEmitted) {
2050 CopyMI->getOperand(i: 0).setIsUndef(true);
2051 // Return an iterator pointing to the first inserted instr.
2052 MBBI = CopyMI;
2053 }
2054 DefEmitted = true;
2055
2056 // Update LiveVariables' kill info.
2057 if (LV && isKill && !SrcReg.isPhysical())
2058 LV->replaceKillInstruction(Reg: SrcReg, OldMI&: MI, NewMI&: *CopyMI);
2059
2060 LLVM_DEBUG(dbgs() << "Inserted: " << *CopyMI);
2061 }
2062
2063 MachineBasicBlock::iterator EndMBBI =
2064 std::next(x: MachineBasicBlock::iterator(MI));
2065
2066 if (!DefEmitted) {
2067 LLVM_DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF");
2068 MI.setDesc(TII->get(Opcode: TargetOpcode::IMPLICIT_DEF));
2069 for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j)
2070 MI.removeOperand(OpNo: j);
2071 } else {
2072 if (LIS) {
2073 // Force live interval recomputation if we moved to a partial definition
2074 // of the register. Undef flags must be propagate to uses of undefined
2075 // subregister for accurate interval computation.
2076 if (UndefLanes.any() && DefVN && MRI->shouldTrackSubRegLiveness(VReg: DstReg)) {
2077 auto &LI = LIS->getInterval(Reg: DstReg);
2078 for (MachineOperand &UseOp : MRI->use_operands(Reg: DstReg)) {
2079 unsigned SubReg = UseOp.getSubReg();
2080 if (UseOp.isUndef() || !SubReg)
2081 continue;
2082 auto *VN =
2083 LI.getVNInfoAt(Idx: LIS->getInstructionIndex(Instr: *UseOp.getParent()));
2084 if (DefVN != VN)
2085 continue;
2086 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubIdx: SubReg);
2087 if ((UndefLanes & LaneMask).any())
2088 UseOp.setIsUndef(true);
2089 }
2090 LIS->removeInterval(Reg: DstReg);
2091 }
2092 LIS->RemoveMachineInstrFromMaps(MI);
2093 }
2094
2095 LLVM_DEBUG(dbgs() << "Eliminated: " << MI);
2096 MI.eraseFromParent();
2097 }
2098
2099 // Udpate LiveIntervals.
2100 if (LIS)
2101 LIS->repairIntervalsInRange(MBB, Begin: MBBI, End: EndMBBI, OrigRegs);
2102}
2103