1//=- AArch64MachineFunctionInfo.h - AArch64 machine function info -*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares AArch64-specific per-machine-function information.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MACHINEFUNCTIONINFO_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64MACHINEFUNCTIONINFO_H
15
16#include "AArch64SMEAttributes.h"
17#include "AArch64Subtarget.h"
18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/ADT/SmallPtrSet.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/CodeGen/CallingConvLower.h"
22#include "llvm/CodeGen/MIRYamlMapping.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/IR/Function.h"
26#include "llvm/MC/MCLinkerOptimizationHint.h"
27#include "llvm/MC/MCSymbol.h"
28#include <cassert>
29#include <optional>
30
31namespace llvm {
32
33namespace yaml {
34struct AArch64FunctionInfo;
35} // end namespace yaml
36
37class AArch64Subtarget;
38class MachineInstr;
39
40/// Condition of signing the return address in a function.
41///
42/// Corresponds to possible values of "sign-return-address" function attribute.
43enum class SignReturnAddress {
44 None,
45 NonLeaf,
46 All,
47};
48
49/// AArch64FunctionInfo - This class is derived from MachineFunctionInfo and
50/// contains private AArch64-specific information for each MachineFunction.
51class AArch64FunctionInfo final : public MachineFunctionInfo {
52 /// Number of bytes of arguments this function has on the stack. If the callee
53 /// is expected to restore the argument stack this should be a multiple of 16,
54 /// all usable during a tail call.
55 ///
56 /// The alternative would forbid tail call optimisation in some cases: if we
57 /// want to transfer control from a function with 8-bytes of stack-argument
58 /// space to a function with 16-bytes then misalignment of this value would
59 /// make a stack adjustment necessary, which could not be undone by the
60 /// callee.
61 unsigned BytesInStackArgArea = 0;
62
63 /// The number of bytes to restore to deallocate space for incoming
64 /// arguments. Canonically 0 in the C calling convention, but non-zero when
65 /// callee is expected to pop the args.
66 unsigned ArgumentStackToRestore = 0;
67
68 /// Space just below incoming stack pointer reserved for arguments being
69 /// passed on the stack during a tail call. This will be the difference
70 /// between the largest tail call argument space needed in this function and
71 /// what's already available by reusing space of incoming arguments.
72 unsigned TailCallReservedStack = 0;
73
74 /// HasStackFrame - True if this function has a stack frame. Set by
75 /// determineCalleeSaves().
76 bool HasStackFrame = false;
77
78 /// Amount of stack frame size, not including callee-saved registers.
79 uint64_t LocalStackSize = 0;
80
81 /// Amount of stack frame size used for saving callee-saved registers.
82 unsigned CalleeSavedStackSize = 0;
83 unsigned ZPRCalleeSavedStackSize = 0;
84 unsigned PPRCalleeSavedStackSize = 0;
85 bool HasCalleeSavedStackSize = false;
86 bool HasSVECalleeSavedStackSize = false;
87
88 /// Number of TLS accesses using the special (combinable)
89 /// _TLS_MODULE_BASE_ symbol.
90 unsigned NumLocalDynamicTLSAccesses = 0;
91
92 /// FrameIndex for start of varargs area for arguments passed on the
93 /// stack.
94 int VarArgsStackIndex = 0;
95
96 /// Offset of start of varargs area for arguments passed on the stack.
97 unsigned VarArgsStackOffset = 0;
98
99 /// FrameIndex for start of varargs area for arguments passed in
100 /// general purpose registers.
101 int VarArgsGPRIndex = 0;
102
103 /// Size of the varargs area for arguments passed in general purpose
104 /// registers.
105 unsigned VarArgsGPRSize = 0;
106
107 /// FrameIndex for start of varargs area for arguments passed in
108 /// floating-point registers.
109 int VarArgsFPRIndex = 0;
110
111 /// Size of the varargs area for arguments passed in floating-point
112 /// registers.
113 unsigned VarArgsFPRSize = 0;
114
115 /// The stack slots used to add space between FPR and GPR accesses when using
116 /// hazard padding. StackHazardCSRSlotIndex is added between GPR and FPR CSRs.
117 /// StackHazardSlotIndex is added between (sorted) stack objects.
118 int StackHazardSlotIndex = std::numeric_limits<int>::max();
119 int StackHazardCSRSlotIndex = std::numeric_limits<int>::max();
120
121 /// True if this function has a subset of CSRs that is handled explicitly via
122 /// copies.
123 bool IsSplitCSR = false;
124
125 /// True when the stack gets realigned dynamically because the size of stack
126 /// frame is unknown at compile time. e.g., in case of VLAs.
127 bool StackRealigned = false;
128
129 /// True when the callee-save stack area has unused gaps that may be used for
130 /// other stack allocations.
131 bool CalleeSaveStackHasFreeSpace = false;
132
133 /// SRetReturnReg - sret lowering includes returning the value of the
134 /// returned struct in a register. This field holds the virtual register into
135 /// which the sret argument is passed.
136 Register SRetReturnReg;
137
138 /// SVE stack size (for predicates and data vectors) are maintained here
139 /// rather than in FrameInfo, as the placement and Stack IDs are target
140 /// specific.
141 uint64_t StackSizeZPR = 0;
142 uint64_t StackSizePPR = 0;
143
144 /// Are SVE objects (vectors and predicates) split into separate regions on
145 /// the stack.
146 bool SplitSVEObjects = false;
147
148 /// HasCalculatedStackSizeSVE indicates whether StackSizeZPR/PPR is valid.
149 bool HasCalculatedStackSizeSVE = false;
150
151 /// Has a value when it is known whether or not the function uses a
152 /// redzone, and no value otherwise.
153 /// Initialized during frame lowering, unless the function has the noredzone
154 /// attribute, in which case it is set to false at construction.
155 std::optional<bool> HasRedZone;
156
157 /// ForwardedMustTailRegParms - A list of virtual and physical registers
158 /// that must be forwarded to every musttail call.
159 SmallVector<ForwardedRegister, 1> ForwardedMustTailRegParms;
160
161 /// FrameIndex for the tagged base pointer.
162 std::optional<int> TaggedBasePointerIndex;
163
164 /// Offset from SP-at-entry to the tagged base pointer.
165 /// Tagged base pointer is set up to point to the first (lowest address)
166 /// tagged stack slot.
167 unsigned TaggedBasePointerOffset;
168
169 /// OutliningStyle denotes, if a function was outined, how it was outlined,
170 /// e.g. Tail Call, Thunk, or Function if none apply.
171 std::optional<std::string> OutliningStyle;
172
173 // Offset from SP-after-callee-saved-spills (i.e. SP-at-entry minus
174 // CalleeSavedStackSize) to the address of the frame record.
175 int CalleeSaveBaseToFrameRecordOffset = 0;
176
177 /// SignCondition controls when PAC-RET protection should be used.
178 SignReturnAddress SignCondition = SignReturnAddress::None;
179
180 /// SignWithBKey modifies the default PAC-RET mode to signing with the B key.
181 bool SignWithBKey = false;
182
183 /// HasELFSignedGOT is true if the target binary format is ELF and the IR
184 /// module containing the corresponding function has "ptrauth-elf-got" flag
185 /// set to 1.
186 bool HasELFSignedGOT = false;
187
188 /// SigningInstrOffset captures the offset of the PAC-RET signing instruction
189 /// within the prologue, so it can be re-used for authentication in the
190 /// epilogue when using PC as a second salt (FEAT_PAuth_LR)
191 MCSymbol *SignInstrLabel = nullptr;
192
193 /// SignReturnAddressHardening specifies the PAC-RET hardening scheme.
194 enum class SignReturnAddressHardeningKind { None, LoadReturnAddress };
195
196 SignReturnAddressHardeningKind SignReturnAddressHardening =
197 SignReturnAddressHardeningKind::None;
198
199 /// BranchTargetEnforcement enables placing BTI instructions at potential
200 /// indirect branch destinations.
201 bool BranchTargetEnforcement = false;
202
203 /// Indicates that SP signing should be diversified with PC as-per PAuthLR.
204 /// This is set by -mbranch-protection and will emit NOP instructions unless
205 /// the subtarget feature +pauthlr is also used (in which case non-NOP
206 /// instructions are emitted).
207 bool BranchProtectionPAuthLR = false;
208
209 /// Whether this function has an extended frame record [Ctx, FP, LR]. If so,
210 /// bit 60 of the in-memory FP will be 1 to enable other tools to detect the
211 /// extended record.
212 bool HasSwiftAsyncContext = false;
213
214 /// The stack slot where the Swift asynchronous context is stored.
215 int SwiftAsyncContextFrameIdx = std::numeric_limits<int>::max();
216
217 bool IsMTETagged = false;
218
219 /// The function has Scalable Vector or Scalable Predicate register argument
220 /// or return type
221 bool IsSVECC = false;
222
223 /// Whether this function changes streaming mode within the function.
224 bool HasStreamingModeChanges = false;
225
226 /// True if the function need unwind information.
227 mutable std::optional<bool> NeedsDwarfUnwindInfo;
228
229 /// True if the function need asynchronous unwind information.
230 mutable std::optional<bool> NeedsAsyncDwarfUnwindInfo;
231
232 int64_t StackProbeSize = 0;
233
234 // Holds a register containing pstate.sm. This is set
235 // on function entry to record the initial pstate of a function.
236 Register PStateSMReg = Register();
237
238 // Has the PNReg used to build PTRUE instruction.
239 // The PTRUE is used for the LD/ST of ZReg pairs in save and restore.
240 unsigned PredicateRegForFillSpill = 0;
241
242 // Holds the SME function attributes (streaming mode, ZA/ZT0 state).
243 SMEAttrs SMEFnAttrs;
244
245 // Holds the TPIDR2 block if allocated early (for Windows/stack probes
246 // support).
247 Register EarlyAllocSMESaveBuffer = Register();
248
249public:
250 AArch64FunctionInfo(const Function &F, const AArch64Subtarget *STI);
251
252 MachineFunctionInfo *
253 clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
254 const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
255 const override;
256
257 void setEarlyAllocSMESaveBuffer(Register Ptr) {
258 EarlyAllocSMESaveBuffer = Ptr;
259 }
260
261 Register getEarlyAllocSMESaveBuffer() const {
262 return EarlyAllocSMESaveBuffer;
263 }
264
265 void setPredicateRegForFillSpill(unsigned Reg) {
266 PredicateRegForFillSpill = Reg;
267 }
268 unsigned getPredicateRegForFillSpill() const {
269 return PredicateRegForFillSpill;
270 }
271
272 Register getPStateSMReg() const { return PStateSMReg; };
273 void setPStateSMReg(Register Reg) { PStateSMReg = Reg; };
274
275 bool isSVECC() const { return IsSVECC; };
276 void setIsSVECC(bool s) { IsSVECC = s; };
277
278 void initializeBaseYamlFields(const yaml::AArch64FunctionInfo &YamlMFI);
279
280 unsigned getBytesInStackArgArea() const { return BytesInStackArgArea; }
281 void setBytesInStackArgArea(unsigned bytes) { BytesInStackArgArea = bytes; }
282
283 unsigned getArgumentStackToRestore() const { return ArgumentStackToRestore; }
284 void setArgumentStackToRestore(unsigned bytes) {
285 ArgumentStackToRestore = bytes;
286 }
287
288 unsigned getTailCallReservedStack() const { return TailCallReservedStack; }
289 void setTailCallReservedStack(unsigned bytes) {
290 TailCallReservedStack = bytes;
291 }
292
293 void setStackSizeSVE(uint64_t ZPR, uint64_t PPR) {
294 assert(isAligned(Align(16), ZPR) && isAligned(Align(16), PPR) &&
295 "expected SVE stack sizes to be aligned to 16-bytes");
296 StackSizeZPR = ZPR;
297 StackSizePPR = PPR;
298 HasCalculatedStackSizeSVE = true;
299 }
300
301 uint64_t getStackSizeZPR() const {
302 assert(hasCalculatedStackSizeSVE());
303 return StackSizeZPR;
304 }
305 uint64_t getStackSizePPR() const {
306 assert(hasCalculatedStackSizeSVE());
307 return StackSizePPR;
308 }
309
310 bool hasCalculatedStackSizeSVE() const { return HasCalculatedStackSizeSVE; }
311
312 bool hasSVEStackSize() const {
313 return getStackSizeZPR() > 0 || getStackSizePPR() > 0;
314 }
315
316 bool hasStackFrame() const { return HasStackFrame; }
317 void setHasStackFrame(bool s) { HasStackFrame = s; }
318
319 bool isStackRealigned() const { return StackRealigned; }
320 void setStackRealigned(bool s) { StackRealigned = s; }
321 bool hasCalleeSaveStackFreeSpace() const {
322 return CalleeSaveStackHasFreeSpace;
323 }
324 void setCalleeSaveStackHasFreeSpace(bool s) {
325 CalleeSaveStackHasFreeSpace = s;
326 }
327 bool isSplitCSR() const { return IsSplitCSR; }
328 void setIsSplitCSR(bool s) { IsSplitCSR = s; }
329
330 void setLocalStackSize(uint64_t Size) { LocalStackSize = Size; }
331 uint64_t getLocalStackSize() const { return LocalStackSize; }
332
333 void setOutliningStyle(const std::string &Style) { OutliningStyle = Style; }
334 std::optional<std::string> getOutliningStyle() const {
335 return OutliningStyle;
336 }
337
338 void setCalleeSavedStackSize(unsigned Size) {
339 CalleeSavedStackSize = Size;
340 HasCalleeSavedStackSize = true;
341 }
342
343 // When CalleeSavedStackSize has not been set (for example when
344 // some MachineIR pass is run in isolation), then recalculate
345 // the CalleeSavedStackSize directly from the CalleeSavedInfo.
346 // Note: This information can only be recalculated after PEI
347 // has assigned offsets to the callee save objects.
348 unsigned getCalleeSavedStackSize(const MachineFrameInfo &MFI) const {
349 bool ValidateCalleeSavedStackSize = false;
350
351#ifndef NDEBUG
352 // Make sure the calculated size derived from the CalleeSavedInfo
353 // equals the cached size that was calculated elsewhere (e.g. in
354 // determineCalleeSaves).
355 ValidateCalleeSavedStackSize = HasCalleeSavedStackSize;
356#endif
357
358 if (!HasCalleeSavedStackSize || ValidateCalleeSavedStackSize) {
359 assert(MFI.isCalleeSavedInfoValid() && "CalleeSavedInfo not calculated");
360 if (MFI.getCalleeSavedInfo().empty())
361 return 0;
362
363 int64_t MinOffset = std::numeric_limits<int64_t>::max();
364 int64_t MaxOffset = std::numeric_limits<int64_t>::min();
365 for (const auto &Info : MFI.getCalleeSavedInfo()) {
366 int FrameIdx = Info.getFrameIdx();
367 if (MFI.getStackID(ObjectIdx: FrameIdx) != TargetStackID::Default)
368 continue;
369 int64_t Offset = MFI.getObjectOffset(ObjectIdx: FrameIdx);
370 int64_t ObjSize = MFI.getObjectSize(ObjectIdx: FrameIdx);
371 MinOffset = std::min<int64_t>(a: Offset, b: MinOffset);
372 MaxOffset = std::max<int64_t>(a: Offset + ObjSize, b: MaxOffset);
373 }
374
375 if (SwiftAsyncContextFrameIdx != std::numeric_limits<int>::max()) {
376 int64_t Offset = MFI.getObjectOffset(ObjectIdx: getSwiftAsyncContextFrameIdx());
377 int64_t ObjSize = MFI.getObjectSize(ObjectIdx: getSwiftAsyncContextFrameIdx());
378 MinOffset = std::min<int64_t>(a: Offset, b: MinOffset);
379 MaxOffset = std::max<int64_t>(a: Offset + ObjSize, b: MaxOffset);
380 }
381
382 if (StackHazardCSRSlotIndex != std::numeric_limits<int>::max()) {
383 int64_t Offset = MFI.getObjectOffset(ObjectIdx: StackHazardCSRSlotIndex);
384 int64_t ObjSize = MFI.getObjectSize(ObjectIdx: StackHazardCSRSlotIndex);
385 MinOffset = std::min<int64_t>(a: Offset, b: MinOffset);
386 MaxOffset = std::max<int64_t>(a: Offset + ObjSize, b: MaxOffset);
387 }
388
389 unsigned Size = alignTo(Value: MaxOffset - MinOffset, Align: 16);
390 assert((!HasCalleeSavedStackSize || getCalleeSavedStackSize() == Size) &&
391 "Invalid size calculated for callee saves");
392 return Size;
393 }
394
395 return getCalleeSavedStackSize();
396 }
397
398 unsigned getCalleeSavedStackSize() const {
399 assert(HasCalleeSavedStackSize &&
400 "CalleeSavedStackSize has not been calculated");
401 return CalleeSavedStackSize;
402 }
403
404 // Saves the CalleeSavedStackSize for SVE vectors in 'scalable bytes'
405 void setSVECalleeSavedStackSize(unsigned ZPR, unsigned PPR) {
406 assert(isAligned(Align(16), ZPR) && isAligned(Align(16), PPR) &&
407 "expected SVE callee-save sizes to be aligned to 16-bytes");
408 ZPRCalleeSavedStackSize = ZPR;
409 PPRCalleeSavedStackSize = PPR;
410 HasSVECalleeSavedStackSize = true;
411 }
412 unsigned getZPRCalleeSavedStackSize() const {
413 assert(HasSVECalleeSavedStackSize &&
414 "ZPRCalleeSavedStackSize has not been calculated");
415 return ZPRCalleeSavedStackSize;
416 }
417 unsigned getPPRCalleeSavedStackSize() const {
418 assert(HasSVECalleeSavedStackSize &&
419 "PPRCalleeSavedStackSize has not been calculated");
420 return PPRCalleeSavedStackSize;
421 }
422
423 unsigned getSVECalleeSavedStackSize() const {
424 assert(!hasSplitSVEObjects() &&
425 "ZPRs and PPRs are split. Use get[ZPR|PPR]CalleeSavedStackSize()");
426 return getZPRCalleeSavedStackSize() + getPPRCalleeSavedStackSize();
427 }
428
429 void incNumLocalDynamicTLSAccesses() { ++NumLocalDynamicTLSAccesses; }
430 unsigned getNumLocalDynamicTLSAccesses() const {
431 return NumLocalDynamicTLSAccesses;
432 }
433
434 bool isStackHazardIncludedInCalleeSaveArea() const {
435 return hasStackHazardSlotIndex() && !hasSplitSVEObjects();
436 }
437
438 std::optional<bool> hasRedZone() const { return HasRedZone; }
439 void setHasRedZone(bool s) { HasRedZone = s; }
440
441 int getVarArgsStackIndex() const { return VarArgsStackIndex; }
442 void setVarArgsStackIndex(int Index) { VarArgsStackIndex = Index; }
443
444 unsigned getVarArgsStackOffset() const { return VarArgsStackOffset; }
445 void setVarArgsStackOffset(unsigned Offset) { VarArgsStackOffset = Offset; }
446
447 int getVarArgsGPRIndex() const { return VarArgsGPRIndex; }
448 void setVarArgsGPRIndex(int Index) { VarArgsGPRIndex = Index; }
449
450 unsigned getVarArgsGPRSize() const { return VarArgsGPRSize; }
451 void setVarArgsGPRSize(unsigned Size) { VarArgsGPRSize = Size; }
452
453 int getVarArgsFPRIndex() const { return VarArgsFPRIndex; }
454 void setVarArgsFPRIndex(int Index) { VarArgsFPRIndex = Index; }
455
456 unsigned getVarArgsFPRSize() const { return VarArgsFPRSize; }
457 void setVarArgsFPRSize(unsigned Size) { VarArgsFPRSize = Size; }
458
459 bool hasStackHazardSlotIndex() const {
460 return StackHazardSlotIndex != std::numeric_limits<int>::max();
461 }
462 int getStackHazardSlotIndex() const { return StackHazardSlotIndex; }
463 void setStackHazardSlotIndex(int Index) {
464 assert(StackHazardSlotIndex == std::numeric_limits<int>::max());
465 StackHazardSlotIndex = Index;
466 }
467 int getStackHazardCSRSlotIndex() const { return StackHazardCSRSlotIndex; }
468 void setStackHazardCSRSlotIndex(int Index) {
469 assert(StackHazardCSRSlotIndex == std::numeric_limits<int>::max());
470 StackHazardCSRSlotIndex = Index;
471 }
472
473 bool hasSplitSVEObjects() const { return SplitSVEObjects; }
474 void setSplitSVEObjects(bool s) { SplitSVEObjects = s; }
475
476 bool hasSVE_AAPCS(const MachineFunction &MF) const {
477 return hasSplitSVEObjects() || isSVECC() ||
478 MF.getFunction().getCallingConv() ==
479 CallingConv::AArch64_SVE_VectorCall;
480 }
481
482 SMEAttrs getSMEFnAttrs() const { return SMEFnAttrs; }
483
484 unsigned getSRetReturnReg() const { return SRetReturnReg; }
485 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
486
487 unsigned getJumpTableEntrySize(int Idx) const {
488 return JumpTableEntryInfo[Idx].first;
489 }
490 MCSymbol *getJumpTableEntryPCRelSymbol(int Idx) const {
491 return JumpTableEntryInfo[Idx].second;
492 }
493 void setJumpTableEntryInfo(int Idx, unsigned Size, MCSymbol *PCRelSym) {
494 if ((unsigned)Idx >= JumpTableEntryInfo.size())
495 JumpTableEntryInfo.resize(N: Idx+1);
496 JumpTableEntryInfo[Idx] = std::make_pair(x&: Size, y&: PCRelSym);
497 }
498
499 using SetOfInstructions = SmallPtrSet<const MachineInstr *, 16>;
500
501 const SetOfInstructions &getLOHRelated() const { return LOHRelated; }
502
503 // Shortcuts for LOH related types.
504 class MILOHDirective {
505 MCLOHType Kind;
506
507 /// Arguments of this directive. Order matters.
508 SmallVector<const MachineInstr *, 3> Args;
509
510 public:
511 using LOHArgs = ArrayRef<const MachineInstr *>;
512
513 MILOHDirective(MCLOHType Kind, LOHArgs Args)
514 : Kind(Kind), Args(Args.begin(), Args.end()) {
515 assert(isValidMCLOHType(Kind) && "Invalid LOH directive type!");
516 }
517
518 MCLOHType getKind() const { return Kind; }
519 LOHArgs getArgs() const { return Args; }
520 };
521
522 using MILOHArgs = MILOHDirective::LOHArgs;
523 using MILOHContainer = SmallVector<MILOHDirective, 32>;
524
525 const MILOHContainer &getLOHContainer() const { return LOHContainerSet; }
526
527 /// Add a LOH directive of this @p Kind and this @p Args.
528 void addLOHDirective(MCLOHType Kind, MILOHArgs Args) {
529 LOHContainerSet.push_back(Elt: MILOHDirective(Kind, Args));
530 LOHRelated.insert_range(R&: Args);
531 }
532
533 size_t
534 clearLinkerOptimizationHints(const SmallPtrSetImpl<MachineInstr *> &MIs) {
535 size_t InitialSize = LOHContainerSet.size();
536 erase_if(C&: LOHContainerSet, P: [&](const auto &D) {
537 return any_of(D.getArgs(), [&](auto *Arg) { return MIs.contains(Ptr: Arg); });
538 });
539 // In theory there could be an LOH with one label in MIs and another label
540 // outside MIs, however we don't know if the label outside MIs is used in
541 // any other LOHs, so we can't remove them from LOHRelated. In that case, we
542 // might produce a few extra labels, but it won't break anything.
543 LOHRelated.remove_if(P: [&](auto *MI) { return MIs.contains(Ptr: MI); });
544 return InitialSize - LOHContainerSet.size();
545 };
546
547 SmallVectorImpl<ForwardedRegister> &getForwardedMustTailRegParms() {
548 return ForwardedMustTailRegParms;
549 }
550
551 std::optional<int> getTaggedBasePointerIndex() const {
552 return TaggedBasePointerIndex;
553 }
554 void setTaggedBasePointerIndex(int Index) { TaggedBasePointerIndex = Index; }
555
556 unsigned getTaggedBasePointerOffset() const {
557 return TaggedBasePointerOffset;
558 }
559 void setTaggedBasePointerOffset(unsigned Offset) {
560 TaggedBasePointerOffset = Offset;
561 }
562
563 int getCalleeSaveBaseToFrameRecordOffset() const {
564 return CalleeSaveBaseToFrameRecordOffset;
565 }
566 void setCalleeSaveBaseToFrameRecordOffset(int Offset) {
567 CalleeSaveBaseToFrameRecordOffset = Offset;
568 }
569
570 static bool shouldSignReturnAddress(SignReturnAddress Condition,
571 bool IsLRSpilled);
572
573 bool shouldSignReturnAddress(const MachineFunction &MF) const;
574
575 SignReturnAddress getSignReturnAddressCondition() const {
576 return SignCondition;
577 }
578
579 bool needsShadowCallStackPrologueEpilogue(MachineFunction &MF) const;
580
581 bool shouldSignWithBKey() const { return SignWithBKey; }
582
583 bool hasELFSignedGOT() const { return HasELFSignedGOT; }
584
585 MCSymbol *getSigningInstrLabel() const { return SignInstrLabel; }
586 void setSigningInstrLabel(MCSymbol *Label) { SignInstrLabel = Label; }
587
588 bool isMTETagged() const { return IsMTETagged; }
589
590 bool shouldHardenSignReturnAddress() const {
591 return SignReturnAddressHardening != SignReturnAddressHardeningKind::None;
592 }
593
594 bool branchTargetEnforcement() const { return BranchTargetEnforcement; }
595
596 bool branchProtectionPAuthLR() const { return BranchProtectionPAuthLR; }
597
598 void setHasSwiftAsyncContext(bool HasContext) {
599 HasSwiftAsyncContext = HasContext;
600 }
601 bool hasSwiftAsyncContext() const { return HasSwiftAsyncContext; }
602
603 void setSwiftAsyncContextFrameIdx(int FI) {
604 SwiftAsyncContextFrameIdx = FI;
605 }
606 int getSwiftAsyncContextFrameIdx() const { return SwiftAsyncContextFrameIdx; }
607
608 bool needsDwarfUnwindInfo(const MachineFunction &MF) const;
609 bool needsAsyncDwarfUnwindInfo(const MachineFunction &MF) const;
610
611 bool hasStreamingModeChanges() const { return HasStreamingModeChanges; }
612 void setHasStreamingModeChanges(bool HasChanges) {
613 HasStreamingModeChanges = HasChanges;
614 }
615
616 bool hasStackProbing() const { return StackProbeSize != 0; }
617
618 int64_t getStackProbeSize() const { return StackProbeSize; }
619
620private:
621 // Hold the lists of LOHs.
622 MILOHContainer LOHContainerSet;
623 SetOfInstructions LOHRelated;
624
625 SmallVector<std::pair<unsigned, MCSymbol *>, 2> JumpTableEntryInfo;
626};
627
628namespace yaml {
629struct AArch64FunctionInfo final : public yaml::MachineFunctionInfo {
630 std::optional<bool> HasRedZone;
631 std::optional<uint64_t> StackSizeZPR;
632 std::optional<uint64_t> StackSizePPR;
633 std::optional<bool> HasStackFrame;
634 std::optional<bool> HasStreamingModeChanges;
635
636 AArch64FunctionInfo() = default;
637 AArch64FunctionInfo(const llvm::AArch64FunctionInfo &MFI);
638
639 void mappingImpl(yaml::IO &YamlIO) override;
640 ~AArch64FunctionInfo() override = default;
641};
642
643template <> struct MappingTraits<AArch64FunctionInfo> {
644 static void mapping(IO &YamlIO, AArch64FunctionInfo &MFI) {
645 YamlIO.mapOptional(Key: "hasRedZone", Val&: MFI.HasRedZone);
646 YamlIO.mapOptional(Key: "stackSizeZPR", Val&: MFI.StackSizeZPR);
647 YamlIO.mapOptional(Key: "stackSizePPR", Val&: MFI.StackSizePPR);
648 YamlIO.mapOptional(Key: "hasStackFrame", Val&: MFI.HasStackFrame);
649 YamlIO.mapOptional(Key: "hasStreamingModeChanges", Val&: MFI.HasStreamingModeChanges);
650 }
651};
652
653} // end namespace yaml
654
655} // end namespace llvm
656
657#endif // LLVM_LIB_TARGET_AARCH64_AARCH64MACHINEFUNCTIONINFO_H
658