1//=- AArch64MachineFunctionInfo.h - AArch64 machine function info -*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares AArch64-specific per-machine-function information.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MACHINEFUNCTIONINFO_H
14#define LLVM_LIB_TARGET_AARCH64_AARCH64MACHINEFUNCTIONINFO_H
15
16#include "AArch64SMEAttributes.h"
17#include "AArch64Subtarget.h"
18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/ADT/SmallPtrSet.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/CodeGen/CallingConvLower.h"
22#include "llvm/CodeGen/MIRYamlMapping.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/IR/Function.h"
26#include "llvm/MC/MCLinkerOptimizationHint.h"
27#include "llvm/MC/MCSymbol.h"
28#include <cassert>
29#include <optional>
30
31namespace llvm {
32
33namespace yaml {
34struct AArch64FunctionInfo;
35} // end namespace yaml
36
37class AArch64Subtarget;
38class MachineInstr;
39
40/// Condition of signing the return address in a function.
41///
42/// Corresponds to possible values of "sign-return-address" function attribute.
43enum class SignReturnAddress {
44 None,
45 NonLeaf,
46 All,
47};
48
49/// AArch64FunctionInfo - This class is derived from MachineFunctionInfo and
50/// contains private AArch64-specific information for each MachineFunction.
51class AArch64FunctionInfo final : public MachineFunctionInfo {
52 /// Number of bytes of arguments this function has on the stack. If the callee
53 /// is expected to restore the argument stack this should be a multiple of 16,
54 /// all usable during a tail call.
55 ///
56 /// The alternative would forbid tail call optimisation in some cases: if we
57 /// want to transfer control from a function with 8-bytes of stack-argument
58 /// space to a function with 16-bytes then misalignment of this value would
59 /// make a stack adjustment necessary, which could not be undone by the
60 /// callee.
61 unsigned BytesInStackArgArea = 0;
62
63 /// The number of bytes to restore to deallocate space for incoming
64 /// arguments. Canonically 0 in the C calling convention, but non-zero when
65 /// callee is expected to pop the args.
66 unsigned ArgumentStackToRestore = 0;
67
68 /// Space just below incoming stack pointer reserved for arguments being
69 /// passed on the stack during a tail call. This will be the difference
70 /// between the largest tail call argument space needed in this function and
71 /// what's already available by reusing space of incoming arguments.
72 unsigned TailCallReservedStack = 0;
73
74 /// HasStackFrame - True if this function has a stack frame. Set by
75 /// determineCalleeSaves().
76 bool HasStackFrame = false;
77
78 /// Amount of stack frame size, not including callee-saved registers.
79 uint64_t LocalStackSize = 0;
80
81 /// Amount of stack frame size used for saving callee-saved registers.
82 unsigned CalleeSavedStackSize = 0;
83 unsigned ZPRCalleeSavedStackSize = 0;
84 unsigned PPRCalleeSavedStackSize = 0;
85 bool HasCalleeSavedStackSize = false;
86 bool HasSVECalleeSavedStackSize = false;
87
88 /// Number of TLS accesses using the special (combinable)
89 /// _TLS_MODULE_BASE_ symbol.
90 unsigned NumLocalDynamicTLSAccesses = 0;
91
92 /// FrameIndex for start of varargs area for arguments passed on the
93 /// stack.
94 int VarArgsStackIndex = 0;
95
96 /// Offset of start of varargs area for arguments passed on the stack.
97 unsigned VarArgsStackOffset = 0;
98
99 /// FrameIndex for start of varargs area for arguments passed in
100 /// general purpose registers.
101 int VarArgsGPRIndex = 0;
102
103 /// Size of the varargs area for arguments passed in general purpose
104 /// registers.
105 unsigned VarArgsGPRSize = 0;
106
107 /// FrameIndex for start of varargs area for arguments passed in
108 /// floating-point registers.
109 int VarArgsFPRIndex = 0;
110
111 /// Size of the varargs area for arguments passed in floating-point
112 /// registers.
113 unsigned VarArgsFPRSize = 0;
114
115 /// The stack slots used to add space between FPR and GPR accesses when using
116 /// hazard padding. StackHazardCSRSlotIndex is added between GPR and FPR CSRs.
117 /// StackHazardSlotIndex is added between (sorted) stack objects.
118 int StackHazardSlotIndex = std::numeric_limits<int>::max();
119 int StackHazardCSRSlotIndex = std::numeric_limits<int>::max();
120
121 /// True if this function has a subset of CSRs that is handled explicitly via
122 /// copies.
123 bool IsSplitCSR = false;
124
125 /// True when the stack gets realigned dynamically because the size of stack
126 /// frame is unknown at compile time. e.g., in case of VLAs.
127 bool StackRealigned = false;
128
129 /// True when the callee-save stack area has unused gaps that may be used for
130 /// other stack allocations.
131 bool CalleeSaveStackHasFreeSpace = false;
132
133 /// SRetReturnReg - sret lowering includes returning the value of the
134 /// returned struct in a register. This field holds the virtual register into
135 /// which the sret argument is passed.
136 Register SRetReturnReg;
137
138 /// SVE stack size (for predicates and data vectors) are maintained here
139 /// rather than in FrameInfo, as the placement and Stack IDs are target
140 /// specific.
141 uint64_t StackSizeZPR = 0;
142 uint64_t StackSizePPR = 0;
143
144 /// Are SVE objects (vectors and predicates) split into separate regions on
145 /// the stack.
146 bool SplitSVEObjects = false;
147
148 /// HasCalculatedStackSizeSVE indicates whether StackSizeZPR/PPR is valid.
149 bool HasCalculatedStackSizeSVE = false;
150
151 /// Has a value when it is known whether or not the function uses a
152 /// redzone, and no value otherwise.
153 /// Initialized during frame lowering, unless the function has the noredzone
154 /// attribute, in which case it is set to false at construction.
155 std::optional<bool> HasRedZone;
156
157 /// ForwardedMustTailRegParms - A list of virtual and physical registers
158 /// that must be forwarded to every musttail call.
159 SmallVector<ForwardedRegister, 1> ForwardedMustTailRegParms;
160
161 /// FrameIndex for the tagged base pointer.
162 std::optional<int> TaggedBasePointerIndex;
163
164 /// Offset from SP-at-entry to the tagged base pointer.
165 /// Tagged base pointer is set up to point to the first (lowest address)
166 /// tagged stack slot.
167 unsigned TaggedBasePointerOffset;
168
169 /// OutliningStyle denotes, if a function was outined, how it was outlined,
170 /// e.g. Tail Call, Thunk, or Function if none apply.
171 std::optional<std::string> OutliningStyle;
172
173 // Offset from SP-after-callee-saved-spills (i.e. SP-at-entry minus
174 // CalleeSavedStackSize) to the address of the frame record.
175 int CalleeSaveBaseToFrameRecordOffset = 0;
176
177 /// SignCondition controls when PAC-RET protection should be used.
178 SignReturnAddress SignCondition = SignReturnAddress::None;
179
180 /// SignWithBKey modifies the default PAC-RET mode to signing with the B key.
181 bool SignWithBKey = false;
182
183 /// HasELFSignedGOT is true if the target binary format is ELF and the IR
184 /// module containing the corresponding function has "ptrauth-elf-got" flag
185 /// set to 1.
186 bool HasELFSignedGOT = false;
187
188 /// SigningInstrOffset captures the offset of the PAC-RET signing instruction
189 /// within the prologue, so it can be re-used for authentication in the
190 /// epilogue when using PC as a second salt (FEAT_PAuth_LR)
191 MCSymbol *SignInstrLabel = nullptr;
192
193 /// BranchTargetEnforcement enables placing BTI instructions at potential
194 /// indirect branch destinations.
195 bool BranchTargetEnforcement = false;
196
197 /// Indicates that SP signing should be diversified with PC as-per PAuthLR.
198 /// This is set by -mbranch-protection and will emit NOP instructions unless
199 /// the subtarget feature +pauthlr is also used (in which case non-NOP
200 /// instructions are emitted).
201 bool BranchProtectionPAuthLR = false;
202
203 /// Whether this function has an extended frame record [Ctx, FP, LR]. If so,
204 /// bit 60 of the in-memory FP will be 1 to enable other tools to detect the
205 /// extended record.
206 bool HasSwiftAsyncContext = false;
207
208 /// The stack slot where the Swift asynchronous context is stored.
209 int SwiftAsyncContextFrameIdx = std::numeric_limits<int>::max();
210
211 bool IsMTETagged = false;
212
213 /// The function has Scalable Vector or Scalable Predicate register argument
214 /// or return type
215 bool IsSVECC = false;
216
217 /// Whether this function changes streaming mode within the function.
218 bool HasStreamingModeChanges = false;
219
220 /// True if the function need unwind information.
221 mutable std::optional<bool> NeedsDwarfUnwindInfo;
222
223 /// True if the function need asynchronous unwind information.
224 mutable std::optional<bool> NeedsAsyncDwarfUnwindInfo;
225
226 int64_t StackProbeSize = 0;
227
228 // Holds a register containing pstate.sm. This is set
229 // on function entry to record the initial pstate of a function.
230 Register PStateSMReg = MCRegister::NoRegister;
231
232 // Has the PNReg used to build PTRUE instruction.
233 // The PTRUE is used for the LD/ST of ZReg pairs in save and restore.
234 unsigned PredicateRegForFillSpill = 0;
235
236 // Holds the SME function attributes (streaming mode, ZA/ZT0 state).
237 SMEAttrs SMEFnAttrs;
238
239 // Holds the TPIDR2 block if allocated early (for Windows/stack probes
240 // support).
241 Register EarlyAllocSMESaveBuffer = AArch64::NoRegister;
242
243public:
244 AArch64FunctionInfo(const Function &F, const AArch64Subtarget *STI);
245
246 MachineFunctionInfo *
247 clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
248 const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
249 const override;
250
251 void setEarlyAllocSMESaveBuffer(Register Ptr) {
252 EarlyAllocSMESaveBuffer = Ptr;
253 }
254
255 Register getEarlyAllocSMESaveBuffer() const {
256 return EarlyAllocSMESaveBuffer;
257 }
258
259 void setPredicateRegForFillSpill(unsigned Reg) {
260 PredicateRegForFillSpill = Reg;
261 }
262 unsigned getPredicateRegForFillSpill() const {
263 return PredicateRegForFillSpill;
264 }
265
266 Register getPStateSMReg() const { return PStateSMReg; };
267 void setPStateSMReg(Register Reg) { PStateSMReg = Reg; };
268
269 bool isSVECC() const { return IsSVECC; };
270 void setIsSVECC(bool s) { IsSVECC = s; };
271
272 void initializeBaseYamlFields(const yaml::AArch64FunctionInfo &YamlMFI);
273
274 unsigned getBytesInStackArgArea() const { return BytesInStackArgArea; }
275 void setBytesInStackArgArea(unsigned bytes) { BytesInStackArgArea = bytes; }
276
277 unsigned getArgumentStackToRestore() const { return ArgumentStackToRestore; }
278 void setArgumentStackToRestore(unsigned bytes) {
279 ArgumentStackToRestore = bytes;
280 }
281
282 unsigned getTailCallReservedStack() const { return TailCallReservedStack; }
283 void setTailCallReservedStack(unsigned bytes) {
284 TailCallReservedStack = bytes;
285 }
286
287 void setStackSizeSVE(uint64_t ZPR, uint64_t PPR) {
288 assert(isAligned(Align(16), ZPR) && isAligned(Align(16), PPR) &&
289 "expected SVE stack sizes to be aligned to 16-bytes");
290 StackSizeZPR = ZPR;
291 StackSizePPR = PPR;
292 HasCalculatedStackSizeSVE = true;
293 }
294
295 uint64_t getStackSizeZPR() const {
296 assert(hasCalculatedStackSizeSVE());
297 return StackSizeZPR;
298 }
299 uint64_t getStackSizePPR() const {
300 assert(hasCalculatedStackSizeSVE());
301 return StackSizePPR;
302 }
303
304 bool hasCalculatedStackSizeSVE() const { return HasCalculatedStackSizeSVE; }
305
306 bool hasSVEStackSize() const {
307 return getStackSizeZPR() > 0 || getStackSizePPR() > 0;
308 }
309
310 bool hasStackFrame() const { return HasStackFrame; }
311 void setHasStackFrame(bool s) { HasStackFrame = s; }
312
313 bool isStackRealigned() const { return StackRealigned; }
314 void setStackRealigned(bool s) { StackRealigned = s; }
315 bool hasCalleeSaveStackFreeSpace() const {
316 return CalleeSaveStackHasFreeSpace;
317 }
318 void setCalleeSaveStackHasFreeSpace(bool s) {
319 CalleeSaveStackHasFreeSpace = s;
320 }
321 bool isSplitCSR() const { return IsSplitCSR; }
322 void setIsSplitCSR(bool s) { IsSplitCSR = s; }
323
324 void setLocalStackSize(uint64_t Size) { LocalStackSize = Size; }
325 uint64_t getLocalStackSize() const { return LocalStackSize; }
326
327 void setOutliningStyle(const std::string &Style) { OutliningStyle = Style; }
328 std::optional<std::string> getOutliningStyle() const {
329 return OutliningStyle;
330 }
331
332 void setCalleeSavedStackSize(unsigned Size) {
333 CalleeSavedStackSize = Size;
334 HasCalleeSavedStackSize = true;
335 }
336
337 // When CalleeSavedStackSize has not been set (for example when
338 // some MachineIR pass is run in isolation), then recalculate
339 // the CalleeSavedStackSize directly from the CalleeSavedInfo.
340 // Note: This information can only be recalculated after PEI
341 // has assigned offsets to the callee save objects.
342 unsigned getCalleeSavedStackSize(const MachineFrameInfo &MFI) const {
343 bool ValidateCalleeSavedStackSize = false;
344
345#ifndef NDEBUG
346 // Make sure the calculated size derived from the CalleeSavedInfo
347 // equals the cached size that was calculated elsewhere (e.g. in
348 // determineCalleeSaves).
349 ValidateCalleeSavedStackSize = HasCalleeSavedStackSize;
350#endif
351
352 if (!HasCalleeSavedStackSize || ValidateCalleeSavedStackSize) {
353 assert(MFI.isCalleeSavedInfoValid() && "CalleeSavedInfo not calculated");
354 if (MFI.getCalleeSavedInfo().empty())
355 return 0;
356
357 int64_t MinOffset = std::numeric_limits<int64_t>::max();
358 int64_t MaxOffset = std::numeric_limits<int64_t>::min();
359 for (const auto &Info : MFI.getCalleeSavedInfo()) {
360 int FrameIdx = Info.getFrameIdx();
361 if (MFI.getStackID(ObjectIdx: FrameIdx) != TargetStackID::Default)
362 continue;
363 int64_t Offset = MFI.getObjectOffset(ObjectIdx: FrameIdx);
364 int64_t ObjSize = MFI.getObjectSize(ObjectIdx: FrameIdx);
365 MinOffset = std::min<int64_t>(a: Offset, b: MinOffset);
366 MaxOffset = std::max<int64_t>(a: Offset + ObjSize, b: MaxOffset);
367 }
368
369 if (SwiftAsyncContextFrameIdx != std::numeric_limits<int>::max()) {
370 int64_t Offset = MFI.getObjectOffset(ObjectIdx: getSwiftAsyncContextFrameIdx());
371 int64_t ObjSize = MFI.getObjectSize(ObjectIdx: getSwiftAsyncContextFrameIdx());
372 MinOffset = std::min<int64_t>(a: Offset, b: MinOffset);
373 MaxOffset = std::max<int64_t>(a: Offset + ObjSize, b: MaxOffset);
374 }
375
376 if (StackHazardCSRSlotIndex != std::numeric_limits<int>::max()) {
377 int64_t Offset = MFI.getObjectOffset(ObjectIdx: StackHazardCSRSlotIndex);
378 int64_t ObjSize = MFI.getObjectSize(ObjectIdx: StackHazardCSRSlotIndex);
379 MinOffset = std::min<int64_t>(a: Offset, b: MinOffset);
380 MaxOffset = std::max<int64_t>(a: Offset + ObjSize, b: MaxOffset);
381 }
382
383 unsigned Size = alignTo(Value: MaxOffset - MinOffset, Align: 16);
384 assert((!HasCalleeSavedStackSize || getCalleeSavedStackSize() == Size) &&
385 "Invalid size calculated for callee saves");
386 return Size;
387 }
388
389 return getCalleeSavedStackSize();
390 }
391
392 unsigned getCalleeSavedStackSize() const {
393 assert(HasCalleeSavedStackSize &&
394 "CalleeSavedStackSize has not been calculated");
395 return CalleeSavedStackSize;
396 }
397
398 // Saves the CalleeSavedStackSize for SVE vectors in 'scalable bytes'
399 void setSVECalleeSavedStackSize(unsigned ZPR, unsigned PPR) {
400 assert(isAligned(Align(16), ZPR) && isAligned(Align(16), PPR) &&
401 "expected SVE callee-save sizes to be aligned to 16-bytes");
402 ZPRCalleeSavedStackSize = ZPR;
403 PPRCalleeSavedStackSize = PPR;
404 HasSVECalleeSavedStackSize = true;
405 }
406 unsigned getZPRCalleeSavedStackSize() const {
407 assert(HasSVECalleeSavedStackSize &&
408 "ZPRCalleeSavedStackSize has not been calculated");
409 return ZPRCalleeSavedStackSize;
410 }
411 unsigned getPPRCalleeSavedStackSize() const {
412 assert(HasSVECalleeSavedStackSize &&
413 "PPRCalleeSavedStackSize has not been calculated");
414 return PPRCalleeSavedStackSize;
415 }
416
417 unsigned getSVECalleeSavedStackSize() const {
418 assert(!hasSplitSVEObjects() &&
419 "ZPRs and PPRs are split. Use get[ZPR|PPR]CalleeSavedStackSize()");
420 return getZPRCalleeSavedStackSize() + getPPRCalleeSavedStackSize();
421 }
422
423 void incNumLocalDynamicTLSAccesses() { ++NumLocalDynamicTLSAccesses; }
424 unsigned getNumLocalDynamicTLSAccesses() const {
425 return NumLocalDynamicTLSAccesses;
426 }
427
428 bool isStackHazardIncludedInCalleeSaveArea() const {
429 return hasStackHazardSlotIndex() && !hasSplitSVEObjects();
430 }
431
432 std::optional<bool> hasRedZone() const { return HasRedZone; }
433 void setHasRedZone(bool s) { HasRedZone = s; }
434
435 int getVarArgsStackIndex() const { return VarArgsStackIndex; }
436 void setVarArgsStackIndex(int Index) { VarArgsStackIndex = Index; }
437
438 unsigned getVarArgsStackOffset() const { return VarArgsStackOffset; }
439 void setVarArgsStackOffset(unsigned Offset) { VarArgsStackOffset = Offset; }
440
441 int getVarArgsGPRIndex() const { return VarArgsGPRIndex; }
442 void setVarArgsGPRIndex(int Index) { VarArgsGPRIndex = Index; }
443
444 unsigned getVarArgsGPRSize() const { return VarArgsGPRSize; }
445 void setVarArgsGPRSize(unsigned Size) { VarArgsGPRSize = Size; }
446
447 int getVarArgsFPRIndex() const { return VarArgsFPRIndex; }
448 void setVarArgsFPRIndex(int Index) { VarArgsFPRIndex = Index; }
449
450 unsigned getVarArgsFPRSize() const { return VarArgsFPRSize; }
451 void setVarArgsFPRSize(unsigned Size) { VarArgsFPRSize = Size; }
452
453 bool hasStackHazardSlotIndex() const {
454 return StackHazardSlotIndex != std::numeric_limits<int>::max();
455 }
456 int getStackHazardSlotIndex() const { return StackHazardSlotIndex; }
457 void setStackHazardSlotIndex(int Index) {
458 assert(StackHazardSlotIndex == std::numeric_limits<int>::max());
459 StackHazardSlotIndex = Index;
460 }
461 int getStackHazardCSRSlotIndex() const { return StackHazardCSRSlotIndex; }
462 void setStackHazardCSRSlotIndex(int Index) {
463 assert(StackHazardCSRSlotIndex == std::numeric_limits<int>::max());
464 StackHazardCSRSlotIndex = Index;
465 }
466
467 bool hasSplitSVEObjects() const { return SplitSVEObjects; }
468 void setSplitSVEObjects(bool s) { SplitSVEObjects = s; }
469
470 bool hasSVE_AAPCS(const MachineFunction &MF) const {
471 return hasSplitSVEObjects() || isSVECC() ||
472 MF.getFunction().getCallingConv() ==
473 CallingConv::AArch64_SVE_VectorCall;
474 }
475
476 SMEAttrs getSMEFnAttrs() const { return SMEFnAttrs; }
477
478 unsigned getSRetReturnReg() const { return SRetReturnReg; }
479 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
480
481 unsigned getJumpTableEntrySize(int Idx) const {
482 return JumpTableEntryInfo[Idx].first;
483 }
484 MCSymbol *getJumpTableEntryPCRelSymbol(int Idx) const {
485 return JumpTableEntryInfo[Idx].second;
486 }
487 void setJumpTableEntryInfo(int Idx, unsigned Size, MCSymbol *PCRelSym) {
488 if ((unsigned)Idx >= JumpTableEntryInfo.size())
489 JumpTableEntryInfo.resize(N: Idx+1);
490 JumpTableEntryInfo[Idx] = std::make_pair(x&: Size, y&: PCRelSym);
491 }
492
493 using SetOfInstructions = SmallPtrSet<const MachineInstr *, 16>;
494
495 const SetOfInstructions &getLOHRelated() const { return LOHRelated; }
496
497 // Shortcuts for LOH related types.
498 class MILOHDirective {
499 MCLOHType Kind;
500
501 /// Arguments of this directive. Order matters.
502 SmallVector<const MachineInstr *, 3> Args;
503
504 public:
505 using LOHArgs = ArrayRef<const MachineInstr *>;
506
507 MILOHDirective(MCLOHType Kind, LOHArgs Args)
508 : Kind(Kind), Args(Args.begin(), Args.end()) {
509 assert(isValidMCLOHType(Kind) && "Invalid LOH directive type!");
510 }
511
512 MCLOHType getKind() const { return Kind; }
513 LOHArgs getArgs() const { return Args; }
514 };
515
516 using MILOHArgs = MILOHDirective::LOHArgs;
517 using MILOHContainer = SmallVector<MILOHDirective, 32>;
518
519 const MILOHContainer &getLOHContainer() const { return LOHContainerSet; }
520
521 /// Add a LOH directive of this @p Kind and this @p Args.
522 void addLOHDirective(MCLOHType Kind, MILOHArgs Args) {
523 LOHContainerSet.push_back(Elt: MILOHDirective(Kind, Args));
524 LOHRelated.insert_range(R&: Args);
525 }
526
527 size_t
528 clearLinkerOptimizationHints(const SmallPtrSetImpl<MachineInstr *> &MIs) {
529 size_t InitialSize = LOHContainerSet.size();
530 erase_if(C&: LOHContainerSet, P: [&](const auto &D) {
531 return any_of(D.getArgs(), [&](auto *Arg) { return MIs.contains(Ptr: Arg); });
532 });
533 // In theory there could be an LOH with one label in MIs and another label
534 // outside MIs, however we don't know if the label outside MIs is used in
535 // any other LOHs, so we can't remove them from LOHRelated. In that case, we
536 // might produce a few extra labels, but it won't break anything.
537 LOHRelated.remove_if(P: [&](auto *MI) { return MIs.contains(Ptr: MI); });
538 return InitialSize - LOHContainerSet.size();
539 };
540
541 SmallVectorImpl<ForwardedRegister> &getForwardedMustTailRegParms() {
542 return ForwardedMustTailRegParms;
543 }
544
545 std::optional<int> getTaggedBasePointerIndex() const {
546 return TaggedBasePointerIndex;
547 }
548 void setTaggedBasePointerIndex(int Index) { TaggedBasePointerIndex = Index; }
549
550 unsigned getTaggedBasePointerOffset() const {
551 return TaggedBasePointerOffset;
552 }
553 void setTaggedBasePointerOffset(unsigned Offset) {
554 TaggedBasePointerOffset = Offset;
555 }
556
557 int getCalleeSaveBaseToFrameRecordOffset() const {
558 return CalleeSaveBaseToFrameRecordOffset;
559 }
560 void setCalleeSaveBaseToFrameRecordOffset(int Offset) {
561 CalleeSaveBaseToFrameRecordOffset = Offset;
562 }
563
564 static bool shouldSignReturnAddress(SignReturnAddress Condition,
565 bool IsLRSpilled);
566
567 bool shouldSignReturnAddress(const MachineFunction &MF) const;
568
569 SignReturnAddress getSignReturnAddressCondition() const {
570 return SignCondition;
571 }
572
573 bool needsShadowCallStackPrologueEpilogue(MachineFunction &MF) const;
574
575 bool shouldSignWithBKey() const { return SignWithBKey; }
576
577 bool hasELFSignedGOT() const { return HasELFSignedGOT; }
578
579 MCSymbol *getSigningInstrLabel() const { return SignInstrLabel; }
580 void setSigningInstrLabel(MCSymbol *Label) { SignInstrLabel = Label; }
581
582 bool isMTETagged() const { return IsMTETagged; }
583
584 bool branchTargetEnforcement() const { return BranchTargetEnforcement; }
585
586 bool branchProtectionPAuthLR() const { return BranchProtectionPAuthLR; }
587
588 void setHasSwiftAsyncContext(bool HasContext) {
589 HasSwiftAsyncContext = HasContext;
590 }
591 bool hasSwiftAsyncContext() const { return HasSwiftAsyncContext; }
592
593 void setSwiftAsyncContextFrameIdx(int FI) {
594 SwiftAsyncContextFrameIdx = FI;
595 }
596 int getSwiftAsyncContextFrameIdx() const { return SwiftAsyncContextFrameIdx; }
597
598 bool needsDwarfUnwindInfo(const MachineFunction &MF) const;
599 bool needsAsyncDwarfUnwindInfo(const MachineFunction &MF) const;
600
601 bool hasStreamingModeChanges() const { return HasStreamingModeChanges; }
602 void setHasStreamingModeChanges(bool HasChanges) {
603 HasStreamingModeChanges = HasChanges;
604 }
605
606 bool hasStackProbing() const { return StackProbeSize != 0; }
607
608 int64_t getStackProbeSize() const { return StackProbeSize; }
609
610private:
611 // Hold the lists of LOHs.
612 MILOHContainer LOHContainerSet;
613 SetOfInstructions LOHRelated;
614
615 SmallVector<std::pair<unsigned, MCSymbol *>, 2> JumpTableEntryInfo;
616};
617
618namespace yaml {
619struct AArch64FunctionInfo final : public yaml::MachineFunctionInfo {
620 std::optional<bool> HasRedZone;
621 std::optional<uint64_t> StackSizeZPR;
622 std::optional<uint64_t> StackSizePPR;
623 std::optional<bool> HasStackFrame;
624 std::optional<bool> HasStreamingModeChanges;
625
626 AArch64FunctionInfo() = default;
627 AArch64FunctionInfo(const llvm::AArch64FunctionInfo &MFI);
628
629 void mappingImpl(yaml::IO &YamlIO) override;
630 ~AArch64FunctionInfo() override = default;
631};
632
633template <> struct MappingTraits<AArch64FunctionInfo> {
634 static void mapping(IO &YamlIO, AArch64FunctionInfo &MFI) {
635 YamlIO.mapOptional(Key: "hasRedZone", Val&: MFI.HasRedZone);
636 YamlIO.mapOptional(Key: "stackSizeZPR", Val&: MFI.StackSizeZPR);
637 YamlIO.mapOptional(Key: "stackSizePPR", Val&: MFI.StackSizePPR);
638 YamlIO.mapOptional(Key: "hasStackFrame", Val&: MFI.HasStackFrame);
639 YamlIO.mapOptional(Key: "hasStreamingModeChanges", Val&: MFI.HasStreamingModeChanges);
640 }
641};
642
643} // end namespace yaml
644
645} // end namespace llvm
646
647#endif // LLVM_LIB_TARGET_AARCH64_AARCH64MACHINEFUNCTIONINFO_H
648