1//===--- AArch64StorePairSuppress.cpp --- Suppress store pair formation ---===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass identifies floating point stores that should not be combined into
10// store pairs. Later we may do the same for floating point loads.
11// ===---------------------------------------------------------------------===//
12
13#include "AArch64InstrInfo.h"
14#include "AArch64Subtarget.h"
15#include "llvm/CodeGen/MachineFunction.h"
16#include "llvm/CodeGen/MachineFunctionPass.h"
17#include "llvm/CodeGen/MachineInstr.h"
18#include "llvm/CodeGen/MachineTraceMetrics.h"
19#include "llvm/CodeGen/TargetInstrInfo.h"
20#include "llvm/CodeGen/TargetSchedule.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/raw_ostream.h"
23
24using namespace llvm;
25
26#define DEBUG_TYPE "aarch64-stp-suppress"
27
28#define STPSUPPRESS_PASS_NAME "AArch64 Store Pair Suppression"
29
30namespace {
31class AArch64StorePairSuppress : public MachineFunctionPass {
32 const AArch64InstrInfo *TII;
33 const MachineRegisterInfo *MRI;
34 TargetSchedModel SchedModel;
35 MachineTraceMetrics *Traces;
36 MachineTraceMetrics::Ensemble *MinInstr;
37
38public:
39 static char ID;
40 AArch64StorePairSuppress() : MachineFunctionPass(ID) {}
41
42 StringRef getPassName() const override { return STPSUPPRESS_PASS_NAME; }
43
44 bool runOnMachineFunction(MachineFunction &F) override;
45
46private:
47 bool shouldAddSTPToBlock(const MachineBasicBlock *BB);
48
49 bool isNarrowFPStore(const MachineInstr &MI);
50
51 void getAnalysisUsage(AnalysisUsage &AU) const override {
52 AU.setPreservesCFG();
53 AU.addRequired<MachineTraceMetricsWrapperPass>();
54 AU.addPreserved<MachineTraceMetricsWrapperPass>();
55 MachineFunctionPass::getAnalysisUsage(AU);
56 }
57};
58char AArch64StorePairSuppress::ID = 0;
59} // anonymous
60
61INITIALIZE_PASS(AArch64StorePairSuppress, "aarch64-stp-suppress",
62 STPSUPPRESS_PASS_NAME, false, false)
63
64FunctionPass *llvm::createAArch64StorePairSuppressPass() {
65 return new AArch64StorePairSuppress();
66}
67
68/// Return true if an STP can be added to this block without increasing the
69/// critical resource height. STP is good to form in Ld/St limited blocks and
70/// bad to form in float-point limited blocks. This is true independent of the
71/// critical path. If the critical path is longer than the resource height, the
72/// extra vector ops can limit physreg renaming. Otherwise, it could simply
73/// oversaturate the vector units.
74bool AArch64StorePairSuppress::shouldAddSTPToBlock(const MachineBasicBlock *BB) {
75 if (!MinInstr)
76 MinInstr = Traces->getEnsemble(MachineTraceStrategy::TS_MinInstrCount);
77
78 MachineTraceMetrics::Trace BBTrace = MinInstr->getTrace(MBB: BB);
79 unsigned ResLength = BBTrace.getResourceLength();
80
81 // Get the machine model's scheduling class for STPDi and STRDui.
82 // Bypass TargetSchedule's SchedClass resolution since we only have an opcode.
83 unsigned SCIdx = TII->get(Opcode: AArch64::STPDi).getSchedClass();
84 const MCSchedClassDesc *PairSCDesc =
85 SchedModel.getMCSchedModel()->getSchedClassDesc(SchedClassIdx: SCIdx);
86
87 unsigned SCIdx2 = TII->get(Opcode: AArch64::STRDui).getSchedClass();
88 const MCSchedClassDesc *SingleSCDesc =
89 SchedModel.getMCSchedModel()->getSchedClassDesc(SchedClassIdx: SCIdx2);
90
91 // If a subtarget does not define resources for STPDi, bail here.
92 if (PairSCDesc->isValid() && !PairSCDesc->isVariant() &&
93 SingleSCDesc->isValid() && !SingleSCDesc->isVariant()) {
94 // Compute the new critical resource length after replacing 2 separate
95 // STRDui with one STPDi.
96 unsigned ResLenWithSTP =
97 BBTrace.getResourceLength(Extrablocks: {}, ExtraInstrs: PairSCDesc, RemoveInstrs: {SingleSCDesc, SingleSCDesc});
98 if (ResLenWithSTP > ResLength) {
99 LLVM_DEBUG(dbgs() << " Suppress STP in BB: " << BB->getNumber()
100 << " resources " << ResLength << " -> " << ResLenWithSTP
101 << "\n");
102 return false;
103 }
104 }
105 return true;
106}
107
108/// Return true if this is a floating-point store smaller than the V reg. On
109/// cyclone, these require a vector shuffle before storing a pair.
110/// Ideally we would call getMatchingPairOpcode() and have the machine model
111/// tell us if it's profitable with no cpu knowledge here.
112///
113/// FIXME: We plan to develop a decent Target abstraction for simple loads and
114/// stores. Until then use a nasty switch similar to AArch64LoadStoreOptimizer.
115bool AArch64StorePairSuppress::isNarrowFPStore(const MachineInstr &MI) {
116 switch (MI.getOpcode()) {
117 default:
118 return false;
119 case AArch64::STRSui:
120 case AArch64::STRDui:
121 case AArch64::STURSi:
122 case AArch64::STURDi:
123 return true;
124 }
125}
126
127bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &MF) {
128 if (skipFunction(F: MF.getFunction()) || MF.getFunction().hasOptSize())
129 return false;
130
131 const AArch64Subtarget &ST = MF.getSubtarget<AArch64Subtarget>();
132 if (!ST.enableStorePairSuppress())
133 return false;
134
135 TII = ST.getInstrInfo();
136 MRI = &MF.getRegInfo();
137 SchedModel.init(TSInfo: &ST);
138 Traces = &getAnalysis<MachineTraceMetricsWrapperPass>().getMTM();
139 MinInstr = nullptr;
140
141 LLVM_DEBUG(dbgs() << "*** " << getPassName() << ": " << MF.getName() << '\n');
142
143 if (!SchedModel.hasInstrSchedModel()) {
144 LLVM_DEBUG(dbgs() << " Skipping pass: no machine model present.\n");
145 return false;
146 }
147
148 // Check for a sequence of stores to the same base address. We don't need to
149 // precisely determine whether a store pair can be formed. But we do want to
150 // filter out most situations where we can't form store pairs to avoid
151 // computing trace metrics in those cases.
152 for (auto &MBB : MF) {
153 bool SuppressSTP = false;
154 unsigned PrevBaseReg = 0;
155 for (auto &MI : MBB) {
156 if (!isNarrowFPStore(MI))
157 continue;
158 const MachineOperand *BaseOp;
159 int64_t Offset;
160 bool OffsetIsScalable;
161 if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable) &&
162 BaseOp->isReg()) {
163 Register BaseReg = BaseOp->getReg();
164 if (PrevBaseReg == BaseReg) {
165 // If this block can take STPs, skip ahead to the next block.
166 if (!SuppressSTP && shouldAddSTPToBlock(BB: MI.getParent()))
167 break;
168 // Otherwise, continue unpairing the stores in this block.
169 LLVM_DEBUG(dbgs() << "Unpairing store " << MI << "\n");
170 SuppressSTP = true;
171 TII->suppressLdStPair(MI);
172 }
173 PrevBaseReg = BaseReg;
174 } else
175 PrevBaseReg = 0;
176 }
177 }
178 // This pass just sets some internal MachineMemOperand flags. It can't really
179 // invalidate anything.
180 return false;
181}
182