1//===- AArch64GlobalISelUtils.h ----------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file APIs for AArch64-specific helper functions used in the GlobalISel
9/// pipeline.
10//===----------------------------------------------------------------------===//
11
12#ifndef LLVM_LIB_TARGET_AARCH64_GISEL_AARCH64GLOBALISELUTILS_H
13#define LLVM_LIB_TARGET_AARCH64_GISEL_AARCH64GLOBALISELUTILS_H
14#include "MCTargetDesc/AArch64AddressingModes.h"
15#include "Utils/AArch64BaseInfo.h"
16#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
17#include "llvm/CodeGen/GlobalISel/Utils.h"
18#include "llvm/CodeGen/Register.h"
19#include "llvm/IR/InstrTypes.h"
20#include <cstdint>
21
22namespace llvm {
23
24namespace AArch64GISelUtils {
25
26/// \returns A value when \p MI is a vector splat of a Register or constant.
27/// Checks for generic opcodes and AArch64-specific generic opcodes.
28std::optional<RegOrConstant>
29getAArch64VectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI);
30
31/// \returns A value when \p MI is a constant vector splat.
32/// Checks for generic opcodes and AArch64-specific generic opcodes.
33std::optional<int64_t>
34getAArch64VectorSplatScalar(const MachineInstr &MI,
35 const MachineRegisterInfo &MRI);
36
37/// \returns true if \p MaybeSub and \p Pred are part of a CMN tree for an
38/// integer compare.
39bool isCMN(const MachineInstr *MaybeSub, const CmpInst::Predicate &Pred,
40 const MachineRegisterInfo &MRI);
41
42/// Replace a G_MEMSET with a value of 0 with a G_BZERO instruction if it is
43/// supported and beneficial to do so.
44///
45/// \note This only applies on Darwin.
46///
47/// \returns true if \p MI can be replaced with a G_BZERO.
48bool matchEmitBZero(const MachineInstr &MI, const MachineRegisterInfo &MRI,
49 const LibcallLoweringInfo &Libcalls, bool MinSize);
50///
51/// Replace \p MI with a G_BZERO.
52void applyEmitBZero(MachineInstr &MI, MachineIRBuilder &MIRBuilder);
53
54/// Analyze a ptrauth discriminator value to try to find the constant integer
55/// and address parts, cracking a ptrauth_blend intrinsic if there is one.
56/// \returns integer/address disc. parts, with NoRegister if no address disc.
57std::tuple<uint16_t, Register>
58extractPtrauthBlendDiscriminators(Register Disc, MachineRegisterInfo &MRI);
59
60/// Find the AArch64 condition codes necessary to represent \p P for a scalar
61/// floating point comparison.
62///
63/// \param [out] CondCode is the first condition code.
64/// \param [out] CondCode2 is the second condition code if necessary.
65/// AArch64CC::AL otherwise.
66void changeFCMPPredToAArch64CC(const CmpInst::Predicate P,
67 AArch64CC::CondCode &CondCode,
68 AArch64CC::CondCode &CondCode2);
69
70/// Find the AArch64 condition codes necessary to represent \p P for a vector
71/// floating point comparison.
72///
73/// \param [out] CondCode - The first condition code.
74/// \param [out] CondCode2 - The second condition code if necessary.
75/// AArch64CC::AL otherwise.
76/// \param [out] Invert - True if the comparison must be inverted with a NOT.
77void changeVectorFCMPPredToAArch64CC(const CmpInst::Predicate P,
78 AArch64CC::CondCode &CondCode,
79 AArch64CC::CondCode &CondCode2,
80 bool &Invert);
81
82} // namespace AArch64GISelUtils
83} // namespace llvm
84
85#endif
86