1//===- lib/Target/AMDGPU/AMDGPUCallLowering.h - Call lowering -*- C++ -*---===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file describes how to lower LLVM calls to machine code calls.
11///
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUCALLLOWERING_H
15#define LLVM_LIB_TARGET_AMDGPU_AMDGPUCALLLOWERING_H
16
17#include "llvm/CodeGen/GlobalISel/CallLowering.h"
18
19namespace llvm {
20
21class GCNSubtarget;
22class MachineInstrBuilder;
23class SIMachineFunctionInfo;
24
25class AMDGPUCallLowering final : public CallLowering {
26 void lowerParameterPtr(Register DstReg, MachineIRBuilder &B,
27 uint64_t Offset) const;
28
29 void lowerParameter(MachineIRBuilder &B, ArgInfo &AI, uint64_t Offset,
30 Align Alignment) const;
31
32 bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv,
33 SmallVectorImpl<BaseArgInfo> &Outs,
34 bool IsVarArg) const override;
35
36 bool lowerReturnVal(MachineIRBuilder &B, const Value *Val,
37 ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
38
39 void addOriginalExecToReturn(MachineFunction &MF,
40 MachineInstrBuilder &Ret) const;
41
42public:
43 AMDGPUCallLowering(const TargetLowering &TLI);
44
45 bool lowerReturn(MachineIRBuilder &B, const Value *Val,
46 ArrayRef<Register> VRegs,
47 FunctionLoweringInfo &FLI) const override;
48
49 bool lowerFormalArgumentsKernel(MachineIRBuilder &B, const Function &F,
50 ArrayRef<ArrayRef<Register>> VRegs) const;
51
52 bool lowerFormalArguments(MachineIRBuilder &B, const Function &F,
53 ArrayRef<ArrayRef<Register>> VRegs,
54 FunctionLoweringInfo &FLI) const override;
55
56 bool passSpecialInputs(MachineIRBuilder &MIRBuilder,
57 CCState &CCInfo,
58 SmallVectorImpl<std::pair<MCRegister, Register>> &ArgRegs,
59 CallLoweringInfo &Info) const;
60
61 bool
62 doCallerAndCalleePassArgsTheSameWay(CallLoweringInfo &Info,
63 MachineFunction &MF,
64 SmallVectorImpl<ArgInfo> &InArgs) const;
65
66 bool
67 areCalleeOutgoingArgsTailCallable(CallLoweringInfo &Info, MachineFunction &MF,
68 SmallVectorImpl<ArgInfo> &OutArgs) const;
69
70 /// Returns true if the call can be lowered as a tail call.
71 bool
72 isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder,
73 CallLoweringInfo &Info,
74 SmallVectorImpl<ArgInfo> &InArgs,
75 SmallVectorImpl<ArgInfo> &OutArgs) const;
76
77 void handleImplicitCallArguments(
78 MachineIRBuilder &MIRBuilder, MachineInstrBuilder &CallInst,
79 const GCNSubtarget &ST, const SIMachineFunctionInfo &MFI,
80 CallingConv::ID CalleeCC,
81 ArrayRef<std::pair<MCRegister, Register>> ImplicitArgRegs) const;
82
83 bool lowerTailCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
84 SmallVectorImpl<ArgInfo> &OutArgs) const;
85 bool lowerChainCall(MachineIRBuilder &MIRBuilder,
86 CallLoweringInfo &Info) const;
87 bool lowerCall(MachineIRBuilder &MIRBuilder,
88 CallLoweringInfo &Info) const override;
89
90 static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
91 static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
92};
93} // End of namespace llvm;
94#endif
95