1//=====-- GCNSubtarget.h - Define GCN Subtarget for AMDGPU ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//==-----------------------------------------------------------------------===//
8//
9/// \file
10/// AMD GCN specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_GCNSUBTARGET_H
15#define LLVM_LIB_TARGET_AMDGPU_GCNSUBTARGET_H
16
17#include "AMDGPUCallLowering.h"
18#include "AMDGPURegisterBankInfo.h"
19#include "AMDGPUSubtarget.h"
20#include "SIFrameLowering.h"
21#include "SIISelLowering.h"
22#include "SIInstrInfo.h"
23#include "Utils/AMDGPUBaseInfo.h"
24#include "llvm/Support/AMDHSAKernelDescriptor.h"
25#include "llvm/Support/ErrorHandling.h"
26#include <optional>
27
28#define GET_SUBTARGETINFO_HEADER
29#include "AMDGPUGenSubtargetInfo.inc"
30
31namespace llvm {
32
33class GCNTargetMachine;
34
35/// Module flag names controlling out-of-bounds buffer access semantics.
36/// Each flag is an i32 with Module::Max merge behaviour and tri-state values:
37/// 0 = any (absent/default - backend currently treats as strict)
38/// 1 = relaxed
39/// 2 = strict
40namespace AMDGPUOOBMode {
41inline constexpr StringLiteral BufferFlag("amdgpu.buffer.oob.mode");
42inline constexpr StringLiteral TBufferFlag("amdgpu.tbuffer.oob.mode");
43} // namespace AMDGPUOOBMode
44
45class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
46 public AMDGPUSubtarget {
47public:
48 using AMDGPUSubtarget::getMaxWavesPerEU;
49
50 // Following 2 enums are documented at:
51 // - https://llvm.org/docs/AMDGPUUsage.html#trap-handler-abi
52 enum class TrapHandlerAbi {
53 NONE = 0x00,
54 AMDHSA = 0x01,
55 };
56
57 enum class TrapID {
58 LLVMAMDHSATrap = 0x02,
59 LLVMAMDHSADebugTrap = 0x03,
60 };
61
62private:
63 /// SelectionDAGISel related APIs.
64 std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
65
66 /// GlobalISel related APIs.
67 std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
68 std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
69 std::unique_ptr<InstructionSelector> InstSelector;
70 std::unique_ptr<LegalizerInfo> Legalizer;
71 std::unique_ptr<AMDGPURegisterBankInfo> RegBankInfo;
72
73protected:
74 // Basic subtarget description.
75 AMDGPU::TargetID TargetID;
76 unsigned Gen = INVALID;
77 InstrItineraryData InstrItins;
78 int LDSBankCount = 0;
79 unsigned MaxPrivateElementSize = 0;
80
81 // Instruction cache line size in bytes; set from TableGen subtarget features.
82 unsigned InstCacheLineSize = 0;
83
84 // Data (VMEM) cache line size in bytes; set from TableGen subtarget features.
85 unsigned DataCacheLineSize = 0;
86
87 /// The width, in bits, of the num_records field of a buffer resource (V#),
88 /// set from tablegen subtarget features, 0 is unknown.
89 unsigned BufferResourceNumRecordsWidth = 0;
90
91 // Dynamically set bits that enable features.
92 bool ScalarizeGlobal = false;
93 const bool BufferOOBRelaxed;
94 const bool TBufferOOBRelaxed;
95
96 /// The maximum number of instructions that may be placed within an S_CLAUSE,
97 /// which is one greater than the maximum argument to S_CLAUSE. A value of 0
98 /// indicates a lack of S_CLAUSE support.
99 unsigned MaxHardClauseLength = 0;
100
101#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
102 bool ATTRIBUTE = DEFAULT;
103#include "AMDGPUGenSubtargetInfo.inc"
104
105private:
106 SIInstrInfo InstrInfo;
107 SITargetLowering TLInfo;
108 SIFrameLowering FrameLowering;
109
110 /// Get the register that represents the actual dependency between the
111 /// definition and the use. The definition might only affect a subregister
112 /// that is not actually used. Works for both virtual and physical registers.
113 /// Note: Currently supports VOP3P instructions (without WMMA an SWMMAC).
114 /// Returns the definition register if there is a real dependency and no
115 /// better match is found.
116 Register getRealSchedDependency(const MachineInstr &DefI, int DefOpIdx,
117 const MachineInstr &UseI, int UseOpIdx) const;
118
119public:
120 GCNSubtarget(
121 const Triple &TT, StringRef GPU, StringRef FS, const GCNTargetMachine &TM,
122 bool BufferOOBRelaxed = false, bool TBufferOOBRelaxed = false,
123 AMDGPU::TargetIDSetting XnackSetting = AMDGPU::TargetIDSetting::Any,
124 AMDGPU::TargetIDSetting SramEccSetting = AMDGPU::TargetIDSetting::Any);
125 ~GCNSubtarget() override;
126
127 GCNSubtarget &initializeSubtargetDependencies(const Triple &TT, StringRef GPU,
128 StringRef FS);
129
130 /// Diagnose inconsistent subtarget features before attempting to codegen
131 /// function \p F.
132 void checkSubtargetFeatures(const Function &F) const;
133
134 const SIInstrInfo *getInstrInfo() const override { return &InstrInfo; }
135
136 const SIFrameLowering *getFrameLowering() const override {
137 return &FrameLowering;
138 }
139
140 const SITargetLowering *getTargetLowering() const override { return &TLInfo; }
141
142 const SIRegisterInfo *getRegisterInfo() const override {
143 return &InstrInfo.getRegisterInfo();
144 }
145
146 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
147
148 const CallLowering *getCallLowering() const override {
149 return CallLoweringInfo.get();
150 }
151
152 const InlineAsmLowering *getInlineAsmLowering() const override {
153 return InlineAsmLoweringInfo.get();
154 }
155
156 InstructionSelector *getInstructionSelector() const override {
157 return InstSelector.get();
158 }
159
160 const LegalizerInfo *getLegalizerInfo() const override {
161 return Legalizer.get();
162 }
163
164 const AMDGPURegisterBankInfo *getRegBankInfo() const override {
165 return RegBankInfo.get();
166 }
167
168 const AMDGPU::TargetID &getTargetID() const { return TargetID; }
169
170 const InstrItineraryData *getInstrItineraryData() const override {
171 return &InstrItins;
172 }
173
174 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
175
176 Generation getGeneration() const { return (Generation)Gen; }
177
178 bool isGFX11Plus() const { return getGeneration() >= GFX11; }
179
180#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
181 bool GETTER() const override { return ATTRIBUTE; }
182#include "AMDGPUGenSubtargetInfo.inc"
183
184 unsigned getMaxWaveScratchSize() const {
185 // See COMPUTE_TMPRING_SIZE.WAVESIZE.
186 if (getGeneration() >= GFX12) {
187 // 18-bit field in units of 64-dword.
188 return (64 * 4) * ((1 << 18) - 1);
189 }
190 if (getGeneration() == GFX11) {
191 // 15-bit field in units of 64-dword.
192 return (64 * 4) * ((1 << 15) - 1);
193 }
194 // 13-bit field in units of 256-dword.
195 return (256 * 4) * ((1 << 13) - 1);
196 }
197
198 /// Return the number of high bits known to be zero for a frame index.
199 unsigned getKnownHighZeroBitsForFrameIndex() const {
200 return llvm::countl_zero(Val: getMaxWaveScratchSize()) + getWavefrontSizeLog2();
201 }
202
203 int getLDSBankCount() const { return LDSBankCount; }
204
205 /// Instruction cache line size in bytes (64 for pre-GFX11, 128 for GFX11+).
206 unsigned getInstCacheLineSize() const { return InstCacheLineSize; }
207
208 /// Data (VMEM) cache line size in bytes (128 for gfx12), has no use before
209 /// GFX12.
210 unsigned getDataCacheLineSize() const { return DataCacheLineSize; }
211
212 unsigned getMaxPrivateElementSize(bool ForBufferRSrc = false) const {
213 return (ForBufferRSrc || !hasFlatScratchEnabled()) ? MaxPrivateElementSize
214 : 16;
215 }
216
217 unsigned getConstantBusLimit(unsigned Opcode) const;
218
219 /// Returns if the result of this instruction with a 16-bit result returned in
220 /// a 32-bit register implicitly zeroes the high 16-bits, rather than preserve
221 /// the original value.
222 bool zeroesHigh16BitsOfDest(unsigned Opcode) const;
223
224 bool hasHWFP64() const { return HasFP64; }
225
226 bool hasAddr64() const {
227 return (getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS);
228 }
229
230 bool hasFlat() const {
231 return (getGeneration() > AMDGPUSubtarget::SOUTHERN_ISLANDS);
232 }
233
234 // Return true if the target only has the reverse operand versions of VALU
235 // shift instructions (e.g. v_lshrrev_b32, and no v_lshr_b32).
236 bool hasOnlyRevVALUShifts() const {
237 return getGeneration() >= VOLCANIC_ISLANDS;
238 }
239
240 bool hasFractBug() const { return getGeneration() == SOUTHERN_ISLANDS; }
241
242 bool hasMed3_16() const { return getGeneration() >= AMDGPUSubtarget::GFX9; }
243
244 bool hasMin3Max3_16() const {
245 return getGeneration() >= AMDGPUSubtarget::GFX9;
246 }
247
248 bool hasSwap() const { return HasGFX9Insts; }
249
250 bool hasScalarPackInsts() const { return HasGFX9Insts; }
251
252 bool hasScalarMulHiInsts() const { return HasGFX9Insts; }
253
254 bool hasScalarSubwordLoads() const { return getGeneration() >= GFX12; }
255
256 bool hasAsyncMark() const { return hasVMemToLDSLoad() || HasAsynccnt; }
257
258 TrapHandlerAbi getTrapHandlerAbi() const {
259 return isAmdHsaOS() ? TrapHandlerAbi::AMDHSA : TrapHandlerAbi::NONE;
260 }
261
262 bool supportsGetDoorbellID() const {
263 // The S_GETREG DOORBELL_ID is supported by all GFX9 onward targets.
264 return getGeneration() >= GFX9;
265 }
266
267 /// True if the offset field of DS instructions works as expected. On SI, the
268 /// offset uses a 16-bit adder and does not always wrap properly.
269 bool hasUsableDSOffset() const { return getGeneration() >= SEA_ISLANDS; }
270
271 bool unsafeDSOffsetFoldingEnabled() const {
272 return EnableUnsafeDSOffsetFolding;
273 }
274
275 /// Condition output from div_scale is usable.
276 bool hasUsableDivScaleConditionOutput() const {
277 return getGeneration() != SOUTHERN_ISLANDS;
278 }
279
280 /// Extra wait hazard is needed in some cases before
281 /// s_cbranch_vccnz/s_cbranch_vccz.
282 bool hasReadVCCZBug() const { return getGeneration() <= SEA_ISLANDS; }
283
284 /// Writes to VCC_LO/VCC_HI update the VCCZ flag.
285 bool partialVCCWritesUpdateVCCZ() const { return getGeneration() >= GFX10; }
286
287 /// A read of an SGPR by SMRD instruction requires 4 wait states when the SGPR
288 /// was written by a VALU instruction.
289 bool hasSMRDReadVALUDefHazard() const {
290 return getGeneration() == SOUTHERN_ISLANDS;
291 }
292
293 /// A read of an SGPR by a VMEM instruction requires 5 wait states when the
294 /// SGPR was written by a VALU Instruction.
295 bool hasVMEMReadSGPRVALUDefHazard() const {
296 return getGeneration() >= VOLCANIC_ISLANDS;
297 }
298
299 bool hasRFEHazards() const { return getGeneration() >= VOLCANIC_ISLANDS; }
300
301 /// Number of hazard wait states for s_setreg_b32/s_setreg_imm32_b32.
302 unsigned getSetRegWaitStates() const {
303 return getGeneration() <= SEA_ISLANDS ? 1 : 2;
304 }
305
306 /// Return the amount of LDS that can be used that will not restrict the
307 /// occupancy lower than WaveCount.
308 unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount,
309 const Function &) const;
310
311 bool supportsMinMaxDenormModes() const {
312 return getGeneration() >= AMDGPUSubtarget::GFX9;
313 }
314
315 /// \returns If target supports S_DENORM_MODE.
316 bool hasDenormModeInst() const {
317 return getGeneration() >= AMDGPUSubtarget::GFX10;
318 }
319
320 /// \returns If target supports ds_read/write_b128 and user enables generation
321 /// of ds_read/write_b128.
322 bool useDS128() const { return HasCIInsts && EnableDS128; }
323
324 /// \return If target supports ds_read/write_b96/128.
325 bool hasDS96AndDS128() const { return HasCIInsts; }
326
327 /// Have v_trunc_f64, v_ceil_f64, v_rndne_f64
328 bool haveRoundOpsF64() const { return HasCIInsts; }
329
330 /// \returns If MUBUF instructions always perform range checking, even for
331 /// buffer resources used for private memory access.
332 bool privateMemoryResourceIsRangeChecked() const {
333 return getGeneration() < AMDGPUSubtarget::GFX9;
334 }
335
336 /// \returns If target requires PRT Struct NULL support (zero result registers
337 /// for sparse texture support).
338 bool usePRTStrictNull() const { return EnablePRTStrictNull; }
339
340 bool hasUnalignedBufferAccessEnabled() const {
341 return HasUnalignedBufferAccess && HasUnalignedAccessMode;
342 }
343
344 bool hasUnalignedDSAccessEnabled() const {
345 return HasUnalignedDSAccess && HasUnalignedAccessMode;
346 }
347
348 bool hasUnalignedScratchAccessEnabled() const {
349 return HasUnalignedScratchAccess && HasUnalignedAccessMode;
350 }
351
352 bool isXNACKEnabled() const {
353 return enableXNACK() || TargetID.isXnackOnOrAny();
354 }
355
356 bool hasRelaxedBufferOOBMode() const { return BufferOOBRelaxed; }
357 bool hasRelaxedTBufferOOBMode() const { return TBufferOOBRelaxed; }
358
359 /// Return the width, in bits, of the num_records field of a buffer resource
360 /// (V#) on this subtarget, or std::nullopt if not yet known.
361 std::optional<unsigned> getBufferResourceNumRecordsWidth() const {
362 if (BufferResourceNumRecordsWidth == 0)
363 return std::nullopt;
364 return BufferResourceNumRecordsWidth;
365 }
366
367 bool isCuModeEnabled() const { return EnableCuMode; }
368
369 bool isPreciseMemoryEnabled() const { return EnablePreciseMemory; }
370
371 bool hasFlatScrRegister() const { return hasFlatAddressSpace(); }
372
373 // Check if target supports ST addressing mode with FLAT scratch instructions.
374 // The ST addressing mode means no registers are used, either VGPR or SGPR,
375 // but only immediate offset is swizzled and added to the FLAT scratch base.
376 bool hasFlatScratchSTMode() const {
377 return hasFlatScratchInsts() && (hasGFX10_3Insts() || hasGFX940Insts());
378 }
379
380 bool hasFlatScratchSVSMode() const { return HasGFX940Insts || HasGFX11Insts; }
381
382 bool hasFlatScratchEnabled() const {
383 return hasArchitectedFlatScratch() ||
384 (EnableFlatScratch && hasFlatScratchInsts());
385 }
386
387 bool hasGlobalAddTidInsts() const { return HasGFX10_BEncoding; }
388
389 bool hasAtomicCSub() const { return HasGFX10_BEncoding; }
390
391 bool hasExportInsts() const {
392 return !hasGFX940Insts() && !hasGFX1250Insts();
393 }
394
395 bool hasVINTERPEncoding() const {
396 return HasGFX11Insts && !hasGFX1250Insts();
397 }
398
399 bool hasMultiDwordFlatScratchAddressing() const {
400 return getGeneration() >= GFX9;
401 }
402
403 bool hasFlatLgkmVMemCountInOrder() const { return getGeneration() > GFX9; }
404
405 bool hasD16LoadStore() const { return getGeneration() >= GFX9; }
406
407 bool d16PreservesUnusedBits() const {
408 return hasD16LoadStore() && !TargetID.isSramEccOnOrAny();
409 }
410
411 bool hasD16Images() const { return getGeneration() >= VOLCANIC_ISLANDS; }
412
413 /// Return if most LDS instructions have an m0 use that require m0 to be
414 /// initialized.
415 bool ldsRequiresM0Init() const { return getGeneration() < GFX9; }
416
417 // True if the hardware rewinds and replays GWS operations if a wave is
418 // preempted.
419 //
420 // If this is false, a GWS operation requires testing if a nack set the
421 // MEM_VIOL bit, and repeating if so.
422 bool hasGWSAutoReplay() const { return getGeneration() >= GFX9; }
423
424 /// \returns if target has ds_gws_sema_release_all instruction.
425 bool hasGWSSemaReleaseAll() const { return HasCIInsts; }
426
427 bool hasScalarAddSub64() const { return getGeneration() >= GFX12; }
428
429 bool hasScalarSMulU64() const { return getGeneration() >= GFX12; }
430
431 // Covers VS/PS/CS graphics shaders
432 bool isMesaGfxShader(const Function &F) const {
433 return isMesa3DOS() && AMDGPU::isShader(CC: F.getCallingConv());
434 }
435
436 bool hasMad64_32() const { return getGeneration() >= SEA_ISLANDS; }
437
438 bool hasAtomicFaddInsts() const {
439 return HasAtomicFaddRtnInsts || HasAtomicFaddNoRtnInsts;
440 }
441
442 bool vmemWriteNeedsExpWaitcnt() const {
443 return getGeneration() < SEA_ISLANDS;
444 }
445
446 bool hasInstPrefetch() const {
447 return getGeneration() == GFX10 || getGeneration() == GFX11;
448 }
449
450 bool hasPrefetch() const { return HasGFX12Insts; }
451
452 bool hasInstPrefSize() const { return isGFX11Plus(); }
453
454 void getInstPrefSizeArgs(uint32_t &Mask, uint32_t &Shift, uint32_t &Width,
455 uint32_t &CacheLineSize) const {
456 assert(isGFX11Plus());
457 CacheLineSize = getInstCacheLineSize();
458 if (getGeneration() == GFX11) {
459 Mask = amdhsa::COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE;
460 Shift = amdhsa::COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE_SHIFT;
461 Width = amdhsa::COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE_WIDTH;
462 } else {
463 Mask = amdhsa::COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE;
464 Shift = amdhsa::COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE_SHIFT;
465 Width = amdhsa::COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE_WIDTH;
466 }
467 }
468
469 // Has s_cmpk_* instructions.
470 bool hasSCmpK() const { return getGeneration() < GFX12; }
471
472 // Scratch is allocated in 256 dword per wave blocks for the entire
473 // wavefront. When viewed from the perspective of an arbitrary workitem, this
474 // is 4-byte aligned.
475 //
476 // Only 4-byte alignment is really needed to access anything. Transformations
477 // on the pointer value itself may rely on the alignment / known low bits of
478 // the pointer. Set this to something above the minimum to avoid needing
479 // dynamic realignment in common cases.
480 Align getStackAlignment() const { return Align(16); }
481
482 bool enableMachineScheduler() const override { return true; }
483
484 bool useAA() const override;
485
486 bool enableSubRegLiveness() const override { return true; }
487
488 void setScalarizeGlobalBehavior(bool b) { ScalarizeGlobal = b; }
489 bool getScalarizeGlobalBehavior() const { return ScalarizeGlobal; }
490
491 // XXX - Why is this here if it isn't in the default pass set?
492 bool enableEarlyIfConversion() const override { return true; }
493
494 void overrideSchedPolicy(MachineSchedPolicy &Policy,
495 const SchedRegion &Region) const override;
496
497 void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
498 const SchedRegion &Region) const override;
499
500 void overridePipelinerPolicy(MachinePipelinerPolicy &Policy) const override;
501
502 void mirFileLoaded(MachineFunction &MF) const override;
503
504 unsigned getMaxNumUserSGPRs() const {
505 return AMDGPU::getMaxNumUserSGPRs(STI: *this);
506 }
507
508 bool useVGPRIndexMode() const;
509
510 bool hasScalarCompareEq64() const {
511 return getGeneration() >= VOLCANIC_ISLANDS;
512 }
513
514 bool hasLDSFPAtomicAddF32() const { return HasGFX8Insts; }
515 bool hasLDSFPAtomicAddF64() const {
516 return HasGFX90AInsts || HasGFX1250Insts;
517 }
518
519 /// \returns true if the subtarget has the v_permlane64_b32 instruction.
520 bool hasPermLane64() const { return getGeneration() >= GFX11; }
521
522 /// \returns true if the subtarget supports the ds_swizzle rotate and FFT
523 /// swizzle modes (GFX9+).
524 bool hasDsSwizzleRotateMode() const { return getGeneration() >= GFX9; }
525
526 bool hasDPPRowShare() const {
527 return HasDPP && (HasGFX90AInsts || getGeneration() >= GFX10);
528 }
529
530 // Has V_PK_MOV_B32 opcode
531 bool hasPkMovB32() const { return HasGFX90AInsts; }
532
533 bool hasFmaakFmamkF32Insts() const {
534 return getGeneration() >= GFX10 || hasGFX940Insts();
535 }
536
537 bool hasFmaakFmamkF64Insts() const { return hasGFX1250Insts(); }
538
539 bool hasNonNSAEncoding() const { return getGeneration() < GFX12; }
540
541 unsigned getNSAMaxSize(bool HasSampler = false) const {
542 return AMDGPU::getNSAMaxSize(STI: *this, HasSampler);
543 }
544
545 bool hasMadF16() const;
546
547 // Scalar and global loads support scale_offset bit.
548 bool hasScaleOffset() const { return HasGFX1250Insts; }
549
550 // FLAT GLOBAL VOffset is signed
551 bool hasSignedGVSOffset() const { return HasGFX1250Insts; }
552
553 bool loadStoreOptEnabled() const { return EnableLoadStoreOpt; }
554
555 bool hasUserSGPRInit16BugInWave32() const {
556 return HasUserSGPRInit16Bug && isWave32();
557 }
558
559 bool has12DWordStoreHazard() const {
560 return getGeneration() != AMDGPUSubtarget::SOUTHERN_ISLANDS;
561 }
562
563 // \returns true if the subtarget supports DWORDX3 load/store instructions.
564 bool hasDwordx3LoadStores() const { return HasCIInsts; }
565
566 bool hasReadM0MovRelInterpHazard() const {
567 return getGeneration() == AMDGPUSubtarget::GFX9;
568 }
569
570 bool hasReadM0SendMsgHazard() const {
571 return getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
572 getGeneration() <= AMDGPUSubtarget::GFX9;
573 }
574
575 bool hasReadM0LdsDmaHazard() const {
576 return getGeneration() == AMDGPUSubtarget::GFX9;
577 }
578
579 bool hasReadM0LdsDirectHazard() const {
580 return getGeneration() == AMDGPUSubtarget::GFX9;
581 }
582
583 bool hasLDSMisalignedBugInWGPMode() const {
584 return HasLDSMisalignedBug && !EnableCuMode;
585 }
586
587 // Shift amount of a 64 bit shift cannot be a highest allocated register
588 // if also at the end of the allocation block.
589 bool hasShift64HighRegBug() const { return HasGFX90AInsts; }
590
591 // v_dot2c_f32_f16 unconditionally flushes f16 subnormal inputs to zero
592 // regardless of the MODE register, unlike v_fma_mix_f32 which respects it.
593 bool dot2UnconditionalFlush() const {
594 return HasGFX90AInsts && !HasGFX940Insts;
595 }
596
597 // Has one cycle hazard on transcendental instruction feeding a
598 // non transcendental VALU.
599 bool hasTransForwardingHazard() const { return HasGFX940Insts; }
600
601 // Has one cycle hazard on a VALU instruction partially writing dst with
602 // a shift of result bits feeding another VALU instruction.
603 bool hasDstSelForwardingHazard() const { return HasGFX940Insts; }
604
605 // Cannot use op_sel with v_dot instructions.
606 bool hasDOTOpSelHazard() const { return HasGFX940Insts || HasGFX11Insts; }
607
608 // Does not have HW interlocs for VALU writing and then reading SGPRs.
609 bool hasVDecCoExecHazard() const { return HasGFX940Insts; }
610
611 bool hasHardClauses() const { return MaxHardClauseLength > 0; }
612
613 bool hasFPAtomicToDenormModeHazard() const {
614 return getGeneration() == GFX10;
615 }
616
617 bool hasVOP3DPP() const { return getGeneration() >= GFX11; }
618
619 bool hasLdsDirect() const { return getGeneration() >= GFX11; }
620
621 bool hasLdsWaitVMSRC() const { return getGeneration() >= GFX12; }
622
623 bool hasVALUPartialForwardingHazard() const {
624 return getGeneration() == GFX11;
625 }
626
627 bool hasCvtScaleForwardingHazard() const { return HasGFX950Insts; }
628
629 // All GFX9 targets experience a fetch delay when an instruction at the start
630 // of a loop header is split by a 32-byte fetch window boundary, but GFX950
631 // is uniquely sensitive to this: the delay triggers further performance
632 // degradation beyond the fetch latency itself.
633 bool hasLoopHeadInstSplitSensitivity() const { return HasGFX950Insts; }
634
635 bool requiresCodeObjectV6() const { return RequiresCOV6; }
636
637 bool useVGPRBlockOpsForCSR() const { return UseBlockVGPROpsForCSR; }
638
639 bool hasVALUMaskWriteHazard() const { return getGeneration() == GFX11; }
640
641 bool hasVALUReadSGPRHazard() const {
642 return HasGFX12Insts && !HasGFX1250Insts;
643 }
644
645 bool setRegModeNeedsVNOPs() const {
646 return HasGFX1250Insts && getGeneration() == GFX12;
647 }
648
649 /// Return if operations acting on VGPR tuples require even alignment.
650 bool needsAlignedVGPRs() const { return RequiresAlignVGPR; }
651
652 /// Return true if the target has the S_PACK_HL_B32_B16 instruction.
653 bool hasSPackHL() const { return HasGFX11Insts; }
654
655 /// Return true if the target has the V_CVT_PK_I16_F32/V_CVT_PK_U16_F32
656 /// instructions.
657 bool hasVCvtPkIU16F32() const { return HasGFX11Insts; }
658
659 /// Return true if the target's EXP instruction supports the NULL export
660 /// target.
661 bool hasNullExportTarget() const { return !HasGFX11Insts; }
662
663 bool hasFlatScratchSVSSwizzleBug() const { return getGeneration() == GFX11; }
664
665 /// Return true if the target has the S_DELAY_ALU instruction.
666 bool hasDelayAlu() const { return HasGFX11Insts; }
667
668 /// Returns true if the target supports
669 /// global_load_lds_dwordx3/global_load_lds_dwordx4 or
670 /// buffer_load_dwordx3/buffer_load_dwordx4 with the lds bit.
671 bool hasLDSLoadB96_B128() const { return hasGFX950Insts(); }
672
673 /// \returns true if the target uses LOADcnt/SAMPLEcnt/BVHcnt, DScnt/KMcnt
674 /// and STOREcnt rather than VMcnt, LGKMcnt and VScnt respectively.
675 bool hasExtendedWaitCounts() const { return getGeneration() >= GFX12; }
676
677 /// \returns true if the target has packed f32 instructions that only read 32
678 /// bits from a scalar operand (SGPR or literal) and replicates the bits to
679 /// both channels.
680 bool hasPKF32InstsReplicatingLower32BitsOfScalarInput() const {
681 return getGeneration() == GFX12 && HasGFX1250Insts;
682 }
683
684 bool hasAddPC64Inst() const { return HasGFX1250Insts; }
685
686 /// \returns true if the target supports expert scheduling mode 2 which relies
687 /// on the compiler to insert waits to avoid hazards between VMEM and VALU
688 /// instructions in some instances.
689 bool hasExpertSchedulingMode() const { return getGeneration() >= GFX12; }
690
691 /// \returns The maximum number of instructions that can be enclosed in an
692 /// S_CLAUSE on the given subtarget, or 0 for targets that do not support that
693 /// instruction.
694 unsigned maxHardClauseLength() const { return MaxHardClauseLength; }
695
696 /// Return the maximum number of waves per SIMD for kernels using \p SGPRs
697 /// SGPRs
698 unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
699
700 /// Return the maximum number of waves per SIMD for kernels using \p VGPRs
701 /// VGPRs
702 unsigned getOccupancyWithNumVGPRs(unsigned VGPRs,
703 unsigned DynamicVGPRBlockSize) const;
704
705 /// Subtarget's minimum/maximum occupancy, in number of waves per EU, that can
706 /// be achieved when the only function running on a CU is \p F, each workgroup
707 /// uses \p LDSSize bytes of LDS, and each wave uses \p NumSGPRs SGPRs and \p
708 /// NumVGPRs VGPRs. The flat workgroup sizes associated to the function are a
709 /// range, so this returns a range as well.
710 ///
711 /// Note that occupancy can be affected by the scratch allocation as well, but
712 /// we do not have enough information to compute it.
713 std::pair<unsigned, unsigned> computeOccupancy(const Function &F,
714 unsigned LDSSize = 0,
715 unsigned NumSGPRs = 0,
716 unsigned NumVGPRs = 0) const;
717
718 /// \returns true if the flat_scratch register should be initialized with the
719 /// pointer to the wave's scratch memory rather than a size and offset.
720 bool flatScratchIsPointer() const {
721 return getGeneration() >= AMDGPUSubtarget::GFX9;
722 }
723
724 /// \returns true if the machine has merged shaders in which s0-s7 are
725 /// reserved by the hardware and user SGPRs start at s8
726 bool hasMergedShaders() const { return getGeneration() >= GFX9; }
727
728 // \returns true if the target supports the pre-NGG legacy geometry path.
729 bool hasLegacyGeometry() const { return getGeneration() < GFX11; }
730
731 // \returns true if the target has split barriers feature
732 bool hasSplitBarriers() const { return getGeneration() >= GFX12; }
733
734 // \returns true if the target has WG_RR_MODE kernel descriptor mode bit
735 bool hasRrWGMode() const { return getGeneration() >= GFX12; }
736
737 /// \returns true if VADDR and SADDR fields in VSCRATCH can use negative
738 /// values.
739 bool hasSignedScratchOffsets() const { return getGeneration() >= GFX12; }
740
741 bool hasINVWBL2WaitCntRequirement() const { return HasGFX1250Insts; }
742
743 bool hasVOPD3() const { return HasGFX1250Insts; }
744
745 // \returns true if the target has V_PK_{MIN|MAX}3_{I|U}16 instructions.
746 bool hasPkMinMax3Insts() const { return HasGFX1250Insts; }
747
748 // \returns ture if target has S_GET_SHADER_CYCLES_U64 instruction.
749 bool hasSGetShaderCyclesInst() const { return HasGFX1250Insts; }
750
751 // \returns true if S_GETPC_B64 zero-extends the result from 48 bits instead
752 // of sign-extending. Note that GFX1250 has not only fixed the bug but also
753 // extended VA to 57 bits.
754 bool hasGetPCZeroExtension() const {
755 return HasGFX12Insts && !HasGFX1250Insts;
756 }
757
758 // \returns true if the target needs to create a prolog for backward
759 // compatibility when preloading kernel arguments.
760 bool needsKernArgPreloadProlog() const {
761 return hasKernargPreload() && !HasGFX1250Insts;
762 }
763
764 bool hasCondSubInsts() const { return HasGFX12Insts; }
765
766 bool hasSubClampInsts() const { return hasGFX10_3Insts(); }
767
768 bool hasAnyPackedFP32Ops() const {
769 return hasPackedFP32Ops() || hasPackedFP32SingleSGPROps();
770 };
771
772 bool hasAnyPackedFP64Ops() const { return hasPackedFP64SingleSGPROps(); };
773
774 bool hasAnyPackedU64Ops() const { return hasPackedU64SingleSGPROps(); };
775
776 /// \returns SGPR allocation granularity supported by the subtarget.
777 unsigned getSGPRAllocGranule() const {
778 return AMDGPU::getSGPRAllocGranule(AK: getTargetID().getGPUKind());
779 }
780
781 /// \returns SGPR encoding granularity supported by the subtarget.
782 unsigned getSGPREncodingGranule() const {
783 return AMDGPU::IsaInfo::getSGPREncodingGranule(STI: *this);
784 }
785
786 /// \returns Total number of SGPRs supported by the subtarget.
787 unsigned getTotalNumSGPRs() const {
788 return AMDGPU::getTotalNumSGPRs(AK: getTargetID().getGPUKind());
789 }
790
791 /// \returns Addressable number of SGPRs supported by the subtarget.
792 unsigned getAddressableNumSGPRs() const {
793 return AMDGPU::getAddressableNumSGPRs(AK: getTargetID().getGPUKind());
794 }
795
796 /// \returns Minimum number of SGPRs that meets the given number of waves per
797 /// execution unit requirement supported by the subtarget.
798 unsigned getMinNumSGPRs(unsigned WavesPerEU) const {
799 return AMDGPU::IsaInfo::getMinNumSGPRs(STI: *this, WavesPerEU);
800 }
801
802 /// \returns Maximum number of SGPRs that meets the given number of waves per
803 /// execution unit requirement supported by the subtarget.
804 unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const {
805 return AMDGPU::IsaInfo::getMaxNumSGPRs(STI: *this, WavesPerEU, Addressable);
806 }
807
808 /// \returns Reserved number of SGPRs. This is common
809 /// utility function called by MachineFunction and
810 /// Function variants of getReservedNumSGPRs.
811 unsigned getBaseReservedNumSGPRs(const bool HasFlatScratch) const;
812 /// \returns Reserved number of SGPRs for given machine function \p MF.
813 unsigned getReservedNumSGPRs(const MachineFunction &MF) const;
814
815 /// \returns Reserved number of SGPRs for given function \p F.
816 unsigned getReservedNumSGPRs(const Function &F) const;
817
818 /// \returns Maximum number of preloaded SGPRs for the subtarget.
819 unsigned getMaxNumPreloadedSGPRs() const;
820
821 /// \returns max num SGPRs. This is the common utility
822 /// function called by MachineFunction and Function
823 /// variants of getMaxNumSGPRs.
824 unsigned getBaseMaxNumSGPRs(const Function &F,
825 std::pair<unsigned, unsigned> WavesPerEU,
826 unsigned PreloadedSGPRs,
827 unsigned ReservedNumSGPRs) const;
828
829 /// \returns Maximum number of SGPRs that meets number of waves per execution
830 /// unit requirement for function \p MF, or number of SGPRs explicitly
831 /// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
832 ///
833 /// \returns Value that meets number of waves per execution unit requirement
834 /// if explicitly requested value cannot be converted to integer, violates
835 /// subtarget's specifications, or does not meet number of waves per execution
836 /// unit requirement.
837 unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
838
839 /// \returns Maximum number of SGPRs that meets number of waves per execution
840 /// unit requirement for function \p F, or number of SGPRs explicitly
841 /// requested using "amdgpu-num-sgpr" attribute attached to function \p F.
842 ///
843 /// \returns Value that meets number of waves per execution unit requirement
844 /// if explicitly requested value cannot be converted to integer, violates
845 /// subtarget's specifications, or does not meet number of waves per execution
846 /// unit requirement.
847 unsigned getMaxNumSGPRs(const Function &F) const;
848
849 /// \returns VGPR allocation granularity supported by the subtarget.
850 unsigned getVGPRAllocGranule(unsigned DynamicVGPRBlockSize) const {
851 return AMDGPU::IsaInfo::getVGPRAllocGranule(STI: *this, DynamicVGPRBlockSize);
852 }
853
854 /// \returns VGPR encoding granularity supported by the subtarget.
855 unsigned getVGPREncodingGranule() const {
856 return AMDGPU::IsaInfo::getVGPREncodingGranule(STI: *this);
857 }
858
859 /// \returns Total number of VGPRs supported by the subtarget.
860 unsigned getTotalNumVGPRs() const {
861 return AMDGPU::IsaInfo::getTotalNumVGPRs(STI: *this);
862 }
863
864 /// \returns Addressable number of architectural VGPRs supported by the
865 /// subtarget.
866 unsigned getAddressableNumArchVGPRs() const {
867 return AMDGPU::IsaInfo::getAddressableNumArchVGPRs(STI: *this);
868 }
869
870 /// \returns Addressable number of VGPRs supported by the subtarget.
871 unsigned getAddressableNumVGPRs(unsigned DynamicVGPRBlockSize) const {
872 return AMDGPU::IsaInfo::getAddressableNumVGPRs(STI: *this, DynamicVGPRBlockSize);
873 }
874
875 /// \returns the minimum number of VGPRs that will prevent achieving more than
876 /// the specified number of waves \p WavesPerEU.
877 unsigned getMinNumVGPRs(unsigned WavesPerEU,
878 unsigned DynamicVGPRBlockSize) const {
879 return AMDGPU::IsaInfo::getMinNumVGPRs(STI: *this, WavesPerEU,
880 DynamicVGPRBlockSize);
881 }
882
883 /// \returns the maximum number of VGPRs that can be used and still achieved
884 /// at least the specified number of waves \p WavesPerEU.
885 unsigned getMaxNumVGPRs(unsigned WavesPerEU,
886 unsigned DynamicVGPRBlockSize) const {
887 return AMDGPU::IsaInfo::getMaxNumVGPRs(STI: *this, WavesPerEU,
888 DynamicVGPRBlockSize);
889 }
890
891 /// \returns max num VGPRs. This is the common utility function
892 /// called by MachineFunction and Function variants of getMaxNumVGPRs.
893 unsigned
894 getBaseMaxNumVGPRs(const Function &F,
895 std::pair<unsigned, unsigned> NumVGPRBounds) const;
896
897 /// \returns Maximum number of VGPRs that meets number of waves per execution
898 /// unit requirement for function \p F, or number of VGPRs explicitly
899 /// requested using "amdgpu-num-vgpr" attribute attached to function \p F.
900 ///
901 /// \returns Value that meets number of waves per execution unit requirement
902 /// if explicitly requested value cannot be converted to integer, violates
903 /// subtarget's specifications, or does not meet number of waves per execution
904 /// unit requirement.
905 unsigned getMaxNumVGPRs(const Function &F) const;
906
907 unsigned getMaxNumAGPRs(const Function &F) const { return getMaxNumVGPRs(F); }
908
909 /// Return a pair of maximum numbers of VGPRs and AGPRs that meet the number
910 /// of waves per execution unit required for the function \p MF.
911 std::pair<unsigned, unsigned> getMaxNumVectorRegs(const Function &F) const;
912
913 /// \returns Maximum number of VGPRs that meets number of waves per execution
914 /// unit requirement for function \p MF, or number of VGPRs explicitly
915 /// requested using "amdgpu-num-vgpr" attribute attached to function \p MF.
916 ///
917 /// \returns Value that meets number of waves per execution unit requirement
918 /// if explicitly requested value cannot be converted to integer, violates
919 /// subtarget's specifications, or does not meet number of waves per execution
920 /// unit requirement.
921 unsigned getMaxNumVGPRs(const MachineFunction &MF) const;
922
923 bool isWave32() const { return getWavefrontSize() == 32; }
924
925 bool isWave64() const { return getWavefrontSize() == 64; }
926
927 /// Returns if the wavesize of this subtarget is known reliable. This is false
928 /// only for the a default target-cpu that does not have an explicit
929 /// +wavefrontsize target feature.
930 bool isWaveSizeKnown() const {
931 return hasFeature(Feature: AMDGPU::FeatureWavefrontSize32) ||
932 hasFeature(Feature: AMDGPU::FeatureWavefrontSize64);
933 }
934
935 const TargetRegisterClass *getBoolRC() const {
936 return getRegisterInfo()->getBoolRC();
937 }
938
939 /// \returns Maximum number of work groups per compute unit supported by the
940 /// subtarget and limited by given \p FlatWorkGroupSize.
941 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override {
942 return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(STI: *this, FlatWorkGroupSize);
943 }
944
945 /// \returns Minimum flat work group size supported by the subtarget.
946 unsigned getMinFlatWorkGroupSize() const override {
947 return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(STI: *this);
948 }
949
950 /// \returns Maximum flat work group size supported by the subtarget.
951 unsigned getMaxFlatWorkGroupSize() const override {
952 return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize();
953 }
954
955 /// \returns Number of waves per execution unit required to support the given
956 /// \p FlatWorkGroupSize.
957 unsigned
958 getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize) const override {
959 return AMDGPU::IsaInfo::getWavesPerEUForWorkGroup(STI: *this, FlatWorkGroupSize);
960 }
961
962 /// \returns Minimum number of waves per execution unit supported by the
963 /// subtarget.
964 unsigned getMinWavesPerEU() const override {
965 return AMDGPU::getMinWavesPerEU();
966 }
967
968 void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
969 SDep &Dep,
970 const TargetSchedModel *SchedModel) const override;
971
972 // \returns true if it's beneficial on this subtarget for the scheduler to
973 // cluster stores as well as loads.
974 bool shouldClusterStores() const { return getGeneration() >= GFX11; }
975
976 // \returns the number of address arguments from which to enable MIMG NSA
977 // on supported architectures.
978 unsigned getNSAThreshold(const MachineFunction &MF) const;
979
980 // \returns true if the subtarget has a hazard requiring an "s_nop 0"
981 // instruction before "s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)".
982 bool requiresNopBeforeDeallocVGPRs() const { return !HasGFX1250Insts; }
983
984 // \returns true if the subtarget needs S_WAIT_ALU 0 before S_GETREG_B32 on
985 // STATUS, STATE_PRIV, EXCP_FLAG_PRIV, or EXCP_FLAG_USER.
986 bool requiresWaitIdleBeforeGetReg() const { return HasGFX1250Insts; }
987
988 bool requiresDisjointEarlyClobberAndUndef() const override {
989 // AMDGPU doesn't care if early-clobber and undef operands are allocated
990 // to the same register.
991 return false;
992 }
993
994 // DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64 shall not be claused with anything
995 // and surronded by S_WAIT_ALU(0xFFE3).
996 bool hasDsAtomicAsyncBarrierArriveB64PipeBug() const {
997 return getGeneration() == GFX12;
998 }
999
1000 // Requires s_wait_alu(0) after s102/s103 write and src_flat_scratch_base
1001 // read.
1002 bool hasScratchBaseForwardingHazard() const {
1003 return HasGFX1250Insts && getGeneration() == GFX12;
1004 }
1005
1006 // src_flat_scratch_hi cannot be used as a source in SALU producing a 64-bit
1007 // result.
1008 bool hasFlatScratchHiInB64InstHazard() const {
1009 return HasGFX1250Insts && getGeneration() == GFX12;
1010 }
1011
1012 /// \returns true if the subtarget requires a wait for xcnt before VMEM
1013 /// accesses that must never be repeated in the event of a page fault/re-try.
1014 /// Atomic stores/rmw and all volatile accesses fall under this criteria.
1015 bool requiresWaitXCntForSingleAccessInstructions() const {
1016 return HasGFX1250Insts;
1017 }
1018
1019 /// \returns the number of significant bits in the immediate field of the
1020 /// S_NOP instruction.
1021 unsigned getSNopBits() const {
1022 if (getGeneration() >= AMDGPUSubtarget::GFX12)
1023 return 7;
1024 if (getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1025 return 4;
1026 return 3;
1027 }
1028
1029 bool supportsBPermute() const {
1030 return getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS;
1031 }
1032
1033 bool supportsWaveWideBPermute() const {
1034 return (getGeneration() <= AMDGPUSubtarget::GFX9 ||
1035 getGeneration() == AMDGPUSubtarget::GFX12) ||
1036 isWave32();
1037 }
1038
1039 /// Return true if real (non-fake) variants of True16 instructions using
1040 /// 16-bit registers should be code-generated. Fake True16 instructions are
1041 /// identical to non-fake ones except that they take 32-bit registers as
1042 /// operands and always use their low halves.
1043 // TODO: Remove and use hasTrue16BitInsts() instead once True16 is fully
1044 // supported and the support for fake True16 instructions is removed.
1045 bool useRealTrue16Insts() const {
1046 return hasTrue16BitInsts() && EnableRealTrue16Insts;
1047 }
1048
1049 bool requiresWaitOnWorkgroupReleaseFence(bool TgSplit) const {
1050 return getGeneration() >= GFX10 || TgSplit;
1051 }
1052
1053 bool useDFAforSMS() const override { return false; }
1054
1055 bool enableWindowScheduler() const override { return false; }
1056};
1057
1058class GCNUserSGPRUsageInfo {
1059public:
1060 bool hasImplicitBufferPtr() const { return ImplicitBufferPtr; }
1061
1062 bool hasPrivateSegmentBuffer() const { return PrivateSegmentBuffer; }
1063
1064 bool hasDispatchPtr() const { return DispatchPtr; }
1065
1066 bool hasQueuePtr() const { return QueuePtr; }
1067
1068 bool hasKernargSegmentPtr() const { return KernargSegmentPtr; }
1069
1070 bool hasDispatchID() const { return DispatchID; }
1071
1072 bool hasFlatScratchInit() const { return FlatScratchInit; }
1073
1074 bool hasPrivateSegmentSize() const { return PrivateSegmentSize; }
1075
1076 unsigned getNumKernargPreloadSGPRs() const { return NumKernargPreloadSGPRs; }
1077
1078 unsigned getNumUsedUserSGPRs() const { return NumUsedUserSGPRs; }
1079
1080 unsigned getNumFreeUserSGPRs();
1081
1082 void allocKernargPreloadSGPRs(unsigned NumSGPRs);
1083
1084 enum UserSGPRID : unsigned {
1085 ImplicitBufferPtrID = 0,
1086 PrivateSegmentBufferID = 1,
1087 DispatchPtrID = 2,
1088 QueuePtrID = 3,
1089 KernargSegmentPtrID = 4,
1090 DispatchIdID = 5,
1091 FlatScratchInitID = 6,
1092 PrivateSegmentSizeID = 7
1093 };
1094
1095 // Returns the size in number of SGPRs for preload user SGPR field.
1096 static unsigned getNumUserSGPRForField(UserSGPRID ID) {
1097 switch (ID) {
1098 case ImplicitBufferPtrID:
1099 return 2;
1100 case PrivateSegmentBufferID:
1101 return 4;
1102 case DispatchPtrID:
1103 return 2;
1104 case QueuePtrID:
1105 return 2;
1106 case KernargSegmentPtrID:
1107 return 2;
1108 case DispatchIdID:
1109 return 2;
1110 case FlatScratchInitID:
1111 return 2;
1112 case PrivateSegmentSizeID:
1113 return 1;
1114 }
1115 llvm_unreachable("Unknown UserSGPRID.");
1116 }
1117
1118 GCNUserSGPRUsageInfo(const Function &F, const GCNSubtarget &ST);
1119
1120private:
1121 const GCNSubtarget &ST;
1122
1123 // Private memory buffer
1124 // Compute directly in sgpr[0:1]
1125 // Other shaders indirect 64-bits at sgpr[0:1]
1126 bool ImplicitBufferPtr = false;
1127
1128 bool PrivateSegmentBuffer = false;
1129
1130 bool DispatchPtr = false;
1131
1132 bool QueuePtr = false;
1133
1134 bool KernargSegmentPtr = false;
1135
1136 bool DispatchID = false;
1137
1138 bool FlatScratchInit = false;
1139
1140 bool PrivateSegmentSize = false;
1141
1142 unsigned NumKernargPreloadSGPRs = 0;
1143
1144 unsigned NumUsedUserSGPRs = 0;
1145};
1146
1147} // end namespace llvm
1148
1149#endif // LLVM_LIB_TARGET_AMDGPU_GCNSUBTARGET_H
1150