1//===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition for SIInstrInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15#define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16
17#include "AMDGPUMIRFormatter.h"
18#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
19#include "SIRegisterInfo.h"
20#include "Utils/AMDGPUBaseInfo.h"
21#include "llvm/ADT/SetVector.h"
22#include "llvm/ADT/SmallPtrSet.h"
23#include "llvm/CodeGen/TargetInstrInfo.h"
24#include "llvm/CodeGen/TargetSchedule.h"
25
26#define GET_INSTRINFO_HEADER
27#include "AMDGPUGenInstrInfo.inc"
28
29namespace llvm {
30
31class APInt;
32class GCNSubtarget;
33class LiveVariables;
34class MachineDominatorTree;
35class MachineRegisterInfo;
36class RegScavenger;
37class SIMachineFunctionInfo;
38class MCRegisterClass;
39using TargetRegisterClass = MCRegisterClass;
40class ScheduleHazardRecognizer;
41
42constexpr unsigned DefaultMemoryClusterDWordsLimit = 8;
43
44/// Mark the MMO of a uniform load if there are no potentially clobbering stores
45/// on any path from the start of an entry function to this load.
46static const MachineMemOperand::Flags MONoClobber =
47 MachineMemOperand::MOTargetFlag1;
48
49/// Mark the MMO of a load as the last use.
50static const MachineMemOperand::Flags MOLastUse =
51 MachineMemOperand::MOTargetFlag2;
52
53/// Mark the MMO of cooperative load/store atomics.
54static const MachineMemOperand::Flags MOCooperative =
55 MachineMemOperand::MOTargetFlag3;
56
57struct V2PhysSCopyInfo {
58 // Operands that need to replaced by waterfall
59 SmallVector<MachineOperand *> MOs;
60 // Target physical registers replacing the MOs
61 SmallVector<Register> SGPRs;
62};
63/// Mark the MMO of accesses to memory locations that are
64/// never written to by other threads.
65static const MachineMemOperand::Flags MOThreadPrivate =
66 MachineMemOperand::MOTargetFlag4;
67
68/// Utility to store machine instructions worklist.
69struct SIInstrWorklist {
70 SIInstrWorklist() = default;
71
72 void insert(MachineInstr *MI);
73
74 MachineInstr *top() const { return InstrList[Front]; }
75
76 void erase_top() {
77 InSet.erase(Ptr: InstrList[Front]);
78 ++Front;
79 }
80
81 bool empty() const { return Front == InstrList.size(); }
82
83 void clear() {
84 InstrList.clear();
85 Front = 0;
86 InSet.clear();
87 DeferredList.clear();
88 }
89
90 bool isDeferred(MachineInstr *MI);
91
92 SetVector<MachineInstr *> &getDeferredList() { return DeferredList; }
93
94private:
95 /// InstrList contains the MachineInstrs.
96 SmallVector<MachineInstr *> InstrList;
97 SmallPtrSet<MachineInstr *, 8> InSet;
98 unsigned Front = 0;
99 /// Deferred instructions are specific MachineInstr
100 /// that will be added by insert method.
101 SetVector<MachineInstr *> DeferredList;
102};
103
104// In namespace llvm so ADL finds it when SIInstrFlags predicates are
105// instantiated with MachineInstr (MachineInstr is in namespace llvm).
106inline uint64_t getTSFlags(const MachineInstr &MI) {
107 return MI.getDesc().TSFlags;
108}
109
110class SIInstrInfo final : public AMDGPUGenInstrInfo {
111 struct ThreeAddressUpdates;
112
113private:
114 const SIRegisterInfo RI;
115 const GCNSubtarget &ST;
116 TargetSchedModel SchedModel;
117 mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
118
119 // The inverse predicate should have the negative value.
120 enum BranchPredicate {
121 INVALID_BR = 0,
122 SCC_TRUE = 1,
123 SCC_FALSE = -1,
124 VCCNZ = 2,
125 VCCZ = -2,
126 EXECNZ = -3,
127 EXECZ = 3
128 };
129
130 using SetVectorType = SmallSetVector<MachineInstr *, 32>;
131
132 static unsigned getBranchOpcode(BranchPredicate Cond);
133 static BranchPredicate getBranchPredicate(unsigned Opcode);
134
135public:
136 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
137 MachineRegisterInfo &MRI,
138 const MachineOperand &SuperReg,
139 const TargetRegisterClass *SuperRC,
140 unsigned SubIdx,
141 const TargetRegisterClass *SubRC) const;
142 MachineOperand buildExtractSubRegOrImm(
143 MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI,
144 const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC,
145 unsigned SubIdx, const TargetRegisterClass *SubRC) const;
146
147private:
148 bool optimizeSCC(MachineInstr *SCCValid, MachineInstr *SCCRedefine,
149 bool NeedInversion) const;
150
151 bool invertSCCUse(MachineInstr *SCCDef) const;
152
153 void swapOperands(MachineInstr &Inst) const;
154
155 std::pair<bool, MachineBasicBlock *>
156 moveScalarAddSub(SIInstrWorklist &Worklist, MachineInstr &Inst,
157 MachineDominatorTree *MDT = nullptr) const;
158
159 void lowerSelect(SIInstrWorklist &Worklist, MachineInstr &Inst,
160 MachineDominatorTree *MDT = nullptr) const;
161
162 void lowerScalarAbs(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
163
164 void lowerScalarAbsDiff(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
165
166 void lowerScalarXnor(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
167
168 void splitScalarNotBinop(SIInstrWorklist &Worklist, MachineInstr &Inst,
169 unsigned Opcode) const;
170
171 void splitScalarBinOpN2(SIInstrWorklist &Worklist, MachineInstr &Inst,
172 unsigned Opcode) const;
173
174 void splitScalar64BitUnaryOp(SIInstrWorklist &Worklist, MachineInstr &Inst,
175 unsigned Opcode, bool Swap = false) const;
176
177 void splitScalar64BitBinaryOp(SIInstrWorklist &Worklist, MachineInstr &Inst,
178 unsigned Opcode,
179 MachineDominatorTree *MDT = nullptr) const;
180
181 void splitScalarSMulU64(SIInstrWorklist &Worklist, MachineInstr &Inst,
182 MachineDominatorTree *MDT) const;
183
184 void splitScalarSMulPseudo(SIInstrWorklist &Worklist, MachineInstr &Inst,
185 MachineDominatorTree *MDT) const;
186
187 void splitScalar64BitXnor(SIInstrWorklist &Worklist, MachineInstr &Inst,
188 MachineDominatorTree *MDT = nullptr) const;
189
190 void splitScalar64BitBCNT(SIInstrWorklist &Worklist,
191 MachineInstr &Inst) const;
192 void splitScalar64BitBFE(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
193 void splitScalar64BitCountOp(SIInstrWorklist &Worklist, MachineInstr &Inst,
194 unsigned Opcode,
195 MachineDominatorTree *MDT = nullptr) const;
196 void movePackToVALU(SIInstrWorklist &Worklist, MachineRegisterInfo &MRI,
197 MachineInstr &Inst) const;
198
199 void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
200 SIInstrWorklist &Worklist) const;
201
202 void addSCCDefUsersToVALUWorklist(const MachineOperand &Op,
203 MachineInstr &SCCDefInst,
204 SIInstrWorklist &Worklist,
205 Register NewCond = Register()) const;
206 void addSCCDefsToVALUWorklist(MachineInstr *SCCUseInst,
207 SIInstrWorklist &Worklist) const;
208
209 const TargetRegisterClass *
210 getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
211
212 bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
213 const MachineInstr &MIb) const;
214
215 Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
216
217 bool verifyCopy(const MachineInstr &MI, const MachineRegisterInfo &MRI,
218 StringRef &ErrInfo) const;
219
220 bool resultDependsOnExec(const MachineInstr &MI) const;
221
222 MachineInstr *convertToThreeAddressImpl(MachineInstr &MI,
223 ThreeAddressUpdates &Updates) const;
224
225protected:
226 /// If the specific machine instruction is a instruction that moves/copies
227 /// value from one register to another register return destination and source
228 /// registers as machine operands.
229 std::optional<DestSourcePair>
230 isCopyInstrImpl(const MachineInstr &MI) const override;
231
232 bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0,
233 AMDGPU::OpName Src0OpName, MachineOperand &Src1,
234 AMDGPU::OpName Src1OpName) const;
235 bool isLegalToSwap(const MachineInstr &MI, unsigned fromIdx,
236 unsigned toIdx) const;
237 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
238 unsigned OpIdx0,
239 unsigned OpIdx1) const override;
240
241public:
242 enum TargetOperandFlags {
243 MO_MASK = 0xf,
244
245 MO_NONE = 0,
246 // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
247 MO_GOTPCREL = 1,
248 // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
249 MO_GOTPCREL32 = 2,
250 MO_GOTPCREL32_LO = 2,
251 // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
252 MO_GOTPCREL32_HI = 3,
253 // MO_GOTPCREL64 -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
254 MO_GOTPCREL64 = 4,
255 // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
256 MO_REL32 = 5,
257 MO_REL32_LO = 5,
258 // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
259 MO_REL32_HI = 6,
260 MO_REL64 = 7,
261
262 MO_FAR_BRANCH_OFFSET = 8,
263
264 MO_ABS32_LO = 9,
265 MO_ABS32_HI = 10,
266 MO_ABS64 = 11,
267 };
268
269 explicit SIInstrInfo(const GCNSubtarget &ST);
270
271 const SIRegisterInfo &getRegisterInfo() const {
272 return RI;
273 }
274
275 const GCNSubtarget &getSubtarget() const {
276 return ST;
277 }
278
279 bool isReMaterializableImpl(const MachineInstr &MI) const override;
280
281 bool isIgnorableUse(const MachineOperand &MO) const override;
282
283 bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo,
284 MachineCycleInfo *CI) const override;
285
286 bool areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0,
287 int64_t &Offset1) const override;
288
289 bool isGlobalMemoryObject(const MachineInstr *MI) const override;
290
291 bool getMemOperandsWithOffsetWidth(
292 const MachineInstr &LdSt,
293 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
294 bool &OffsetIsScalable, LocationSize &Width,
295 const TargetRegisterInfo *TRI) const final;
296
297 bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
298 int64_t Offset1, bool OffsetIsScalable1,
299 ArrayRef<const MachineOperand *> BaseOps2,
300 int64_t Offset2, bool OffsetIsScalable2,
301 unsigned ClusterSize,
302 unsigned NumBytes) const override;
303
304 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
305 int64_t Offset1, unsigned NumLoads) const override;
306
307 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
308 const DebugLoc &DL, Register DestReg, Register SrcReg,
309 bool KillSrc, bool RenamableDest = false,
310 bool RenamableSrc = false) const override;
311
312private:
313 void storeRegToStackSlotImpl(MachineBasicBlock &MBB,
314 MachineBasicBlock::iterator MI, Register SrcReg,
315 bool isKill, int FrameIndex,
316 const TargetRegisterClass *RC, Register VReg,
317 MachineInstr::MIFlag Flags, bool NeedsCFI) const;
318
319public:
320 void storeRegToStackSlotCFI(MachineBasicBlock &MBB,
321 MachineBasicBlock::iterator MI, Register SrcReg,
322 bool isKill, int FrameIndex,
323 const TargetRegisterClass *RC) const;
324
325 bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg,
326 int64_t &ImmVal) const override;
327
328 std::optional<int64_t>
329 getImmOrMaterializedImm(const MachineRegisterInfo &MRI,
330 const MachineOperand &Op,
331 MachineInstr **DefMI = nullptr) const;
332 std::optional<int64_t>
333 getImmOrMaterializedImm(const MachineRegisterInfo &MRI, Register Reg,
334 MachineInstr **DefMI = nullptr) const;
335
336 unsigned getVectorRegSpillSaveOpcode(Register Reg,
337 const TargetRegisterClass *RC,
338 unsigned Size,
339 const SIMachineFunctionInfo &MFI,
340 bool NeedsCFI) const;
341 unsigned
342 getVectorRegSpillRestoreOpcode(Register Reg, const TargetRegisterClass *RC,
343 unsigned Size,
344 const SIMachineFunctionInfo &MFI) const;
345
346 void storeRegToStackSlot(
347 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
348 bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
349 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
350
351 void loadRegFromStackSlot(
352 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
353 int FrameIndex, const TargetRegisterClass *RC, Register VReg,
354 unsigned SubReg = 0,
355 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
356
357 bool expandPostRAPseudo(MachineInstr &MI) const override;
358
359 void
360 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
361 Register DestReg, unsigned SubIdx, const MachineInstr &Orig,
362 LaneBitmask UsedLanes = LaneBitmask::getAll()) const override;
363
364 // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
365 // instructions. Returns a pair of generated instructions.
366 // Can split either post-RA with physical registers or pre-RA with
367 // virtual registers. In latter case IR needs to be in SSA form and
368 // and a REG_SEQUENCE is produced to define original register.
369 std::pair<MachineInstr*, MachineInstr*>
370 expandMovDPP64(MachineInstr &MI) const;
371
372 // Returns an opcode that can be used to move a value to a \p DstRC
373 // register. If there is no hardware instruction that can store to \p
374 // DstRC, then AMDGPU::COPY is returned.
375 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
376
377 const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize,
378 unsigned EltSize,
379 bool IsSGPR) const;
380
381 const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
382 bool IsIndirectSrc) const;
383 LLVM_READONLY
384 int commuteOpcode(unsigned Opc) const;
385
386 LLVM_READONLY
387 inline int commuteOpcode(const MachineInstr &MI) const {
388 return commuteOpcode(Opc: MI.getOpcode());
389 }
390
391 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx0,
392 unsigned &SrcOpIdx1) const override;
393
394 bool findCommutedOpIndices(const MCInstrDesc &Desc, unsigned &SrcOpIdx0,
395 unsigned &SrcOpIdx1) const;
396
397 bool isBranchOffsetInRange(unsigned BranchOpc,
398 int64_t BrOffset) const override;
399
400 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
401
402 /// Return whether the block terminate with divergent branch.
403 /// Note this only work before lowering the pseudo control flow instructions.
404 bool hasDivergentBranch(const MachineBasicBlock *MBB) const;
405
406 void insertIndirectBranch(MachineBasicBlock &MBB,
407 MachineBasicBlock &NewDestBB,
408 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
409 int64_t BrOffset, RegScavenger *RS) const override;
410
411 bool analyzeBranchImpl(MachineBasicBlock &MBB,
412 MachineBasicBlock::iterator I,
413 MachineBasicBlock *&TBB,
414 MachineBasicBlock *&FBB,
415 SmallVectorImpl<MachineOperand> &Cond,
416 bool AllowModify) const;
417
418 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
419 MachineBasicBlock *&FBB,
420 SmallVectorImpl<MachineOperand> &Cond,
421 bool AllowModify = false) const override;
422
423 unsigned removeBranch(MachineBasicBlock &MBB,
424 int *BytesRemoved = nullptr) const override;
425
426 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
427 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
428 const DebugLoc &DL,
429 int *BytesAdded = nullptr) const override;
430
431 bool reverseBranchCondition(
432 SmallVectorImpl<MachineOperand> &Cond) const override;
433
434 std::unique_ptr<PipelinerLoopInfo>
435 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
436
437 bool canInsertSelect(const MachineBasicBlock &MBB,
438 ArrayRef<MachineOperand> Cond, Register DstReg,
439 Register TrueReg, Register FalseReg, int &CondCycles,
440 int &TrueCycles, int &FalseCycles) const override;
441
442 void insertSelect(MachineBasicBlock &MBB,
443 MachineBasicBlock::iterator I, const DebugLoc &DL,
444 Register DstReg, ArrayRef<MachineOperand> Cond,
445 Register TrueReg, Register FalseReg) const override;
446
447 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
448 Register &SrcReg2, int64_t &CmpMask,
449 int64_t &CmpValue) const override;
450
451 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
452 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
453 const MachineRegisterInfo *MRI) const override;
454
455 bool
456 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
457 const MachineInstr &MIb) const override;
458
459 static bool isFoldableCopy(const MachineInstr &MI);
460 static unsigned getFoldableCopySrcIdx(const MachineInstr &MI);
461
462 void removeModOperands(MachineInstr &MI) const;
463
464 void mutateAndCleanupImplicit(MachineInstr &MI,
465 const MCInstrDesc &NewDesc) const;
466
467 /// Return the extracted immediate value in a subregister use from a constant
468 /// materialized in a super register.
469 ///
470 /// e.g. %imm = S_MOV_B64 K[0:63]
471 /// USE %imm.sub1
472 /// This will return K[32:63]
473 static std::optional<int64_t> extractSubregFromImm(int64_t ImmVal,
474 unsigned SubRegIndex);
475
476 bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
477 MachineRegisterInfo *MRI) const final;
478
479 unsigned getMachineCSELookAheadLimit() const override { return 500; }
480
481 MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
482 LiveIntervals *LIS) const override;
483
484 bool isSchedulingBoundary(const MachineInstr &MI,
485 const MachineBasicBlock *MBB,
486 const MachineFunction &MF) const override;
487
488 static bool isSALU(const MachineInstr &MI) {
489 return SIInstrFlags::isSALU(O: MI);
490 }
491
492 bool isSALU(uint32_t Opcode) const {
493 return SIInstrFlags::isSALU(O: get(Opcode));
494 }
495
496 static bool isVALU(const MachineInstr &MI, bool AllowLDSDMA) {
497 if (!AllowLDSDMA && isLDSDMA(MI))
498 return false;
499
500 return SIInstrFlags::isVALU(O: MI);
501 }
502
503 /// LDSDMA instructions act as both VALU and memory instructions, thus
504 /// we also tag them as VALU. However, in many places, we do not actually want
505 /// to include LDSDMA instructions in this query. By setting \p AllowLDSDMA to
506 /// false, this will return false for LDSDMA instructions.
507 bool isVALU(uint32_t Opcode, bool AllowLDSDMA) const {
508 if (!AllowLDSDMA && isLDSDMA(Opcode))
509 return false;
510
511 return SIInstrFlags::isVALU(O: get(Opcode));
512 }
513
514 static bool isImage(const MachineInstr &MI) {
515 return SIInstrFlags::isImage(O: MI);
516 }
517
518 bool isImage(uint32_t Opcode) const {
519 return SIInstrFlags::isImage(O: get(Opcode));
520 }
521
522 static bool isVMEM(const MachineInstr &MI) {
523 return SIInstrFlags::isVMEM(O: MI);
524 }
525
526 bool isVMEM(uint32_t Opcode) const {
527 return SIInstrFlags::isVMEM(O: get(Opcode));
528 }
529
530 /// True if MI implicitly drains XCNT.
531 static bool isXcntDrain(const MachineInstr &MI);
532
533 static bool isSOP1(const MachineInstr &MI) {
534 return SIInstrFlags::isSOP1(O: MI);
535 }
536
537 bool isSOP1(uint32_t Opcode) const {
538 return SIInstrFlags::isSOP1(O: get(Opcode));
539 }
540
541 static bool isSOP2(const MachineInstr &MI) {
542 return SIInstrFlags::isSOP2(O: MI);
543 }
544
545 bool isSOP2(uint32_t Opcode) const {
546 return SIInstrFlags::isSOP2(O: get(Opcode));
547 }
548
549 static bool isSOPC(const MachineInstr &MI) {
550 return SIInstrFlags::isSOPC(O: MI);
551 }
552
553 bool isSOPC(uint32_t Opcode) const {
554 return SIInstrFlags::isSOPC(O: get(Opcode));
555 }
556
557 static bool isSOPK(const MachineInstr &MI) {
558 return SIInstrFlags::isSOPK(O: MI);
559 }
560
561 bool isSOPK(uint32_t Opcode) const {
562 return SIInstrFlags::isSOPK(O: get(Opcode));
563 }
564
565 static bool isSOPP(const MachineInstr &MI) {
566 return SIInstrFlags::isSOPP(O: MI);
567 }
568
569 bool isSOPP(uint32_t Opcode) const {
570 return SIInstrFlags::isSOPP(O: get(Opcode));
571 }
572
573 static bool isPacked(const MachineInstr &MI) {
574 return SIInstrFlags::isPacked(O: MI);
575 }
576
577 bool isPacked(uint32_t Opcode) const {
578 return SIInstrFlags::isPacked(O: get(Opcode));
579 }
580
581 static bool isVOP1(const MachineInstr &MI) {
582 return SIInstrFlags::isVOP1(O: MI);
583 }
584
585 bool isVOP1(uint32_t Opcode) const {
586 return SIInstrFlags::isVOP1(O: get(Opcode));
587 }
588
589 static bool isVOP2(const MachineInstr &MI) {
590 return SIInstrFlags::isVOP2(O: MI);
591 }
592
593 bool isVOP2(uint32_t Opcode) const {
594 return SIInstrFlags::isVOP2(O: get(Opcode));
595 }
596
597 static bool isVOP3(const MCInstrDesc &Desc) {
598 return SIInstrFlags::isVOP3(O: Desc);
599 }
600
601 static bool isVOP3(const MachineInstr &MI) { return isVOP3(Desc: MI.getDesc()); }
602
603 bool isVOP3(uint32_t Opcode) const { return isVOP3(Desc: get(Opcode)); }
604
605 static bool isSDWA(const MachineInstr &MI) {
606 return SIInstrFlags::isSDWA(O: MI);
607 }
608
609 bool isSDWA(uint32_t Opcode) const {
610 return SIInstrFlags::isSDWA(O: get(Opcode));
611 }
612
613 static bool isVOPC(const MachineInstr &MI) {
614 return SIInstrFlags::isVOPC(O: MI);
615 }
616
617 bool isVOPC(uint32_t Opcode) const {
618 return SIInstrFlags::isVOPC(O: get(Opcode));
619 }
620
621 static bool isMUBUF(const MachineInstr &MI) {
622 return SIInstrFlags::isMUBUF(O: MI);
623 }
624
625 bool isMUBUF(uint32_t Opcode) const {
626 return SIInstrFlags::isMUBUF(O: get(Opcode));
627 }
628
629 static bool isMTBUF(const MachineInstr &MI) {
630 return SIInstrFlags::isMTBUF(O: MI);
631 }
632
633 bool isMTBUF(uint32_t Opcode) const {
634 return SIInstrFlags::isMTBUF(O: get(Opcode));
635 }
636
637 static bool isBUF(const MachineInstr &MI) {
638 return isMUBUF(MI) || isMTBUF(MI);
639 }
640
641 static bool isSMRD(const MachineInstr &MI) {
642 return SIInstrFlags::isSMRD(O: MI);
643 }
644
645 bool isSMRD(uint32_t Opcode) const {
646 return SIInstrFlags::isSMRD(O: get(Opcode));
647 }
648
649 bool isBufferSMRD(const MachineInstr &MI) const;
650
651 static bool isDS(const MachineInstr &MI) { return SIInstrFlags::isDS(O: MI); }
652
653 bool isDS(uint32_t Opcode) const { return SIInstrFlags::isDS(O: get(Opcode)); }
654
655 static bool isLDSDMA(const MachineInstr &MI) {
656 return (SIInstrFlags::isVALU(O: MI) && (isMUBUF(MI) || isFLAT(MI))) ||
657 SIInstrFlags::usesTENSOR_CNT(O: MI);
658 }
659
660 bool isLDSDMA(uint32_t Opcode) const {
661 return (SIInstrFlags::isVALU(O: get(Opcode)) &&
662 (isMUBUF(Opcode) || isFLAT(Opcode))) ||
663 SIInstrFlags::usesTENSOR_CNT(O: get(Opcode));
664 }
665
666 static bool isGWS(const MachineInstr &MI) { return SIInstrFlags::isGWS(O: MI); }
667
668 bool isGWS(uint32_t Opcode) const { return SIInstrFlags::isGWS(O: get(Opcode)); }
669
670 bool isAlwaysGDS(uint32_t Opcode) const;
671
672 static bool isMIMG(const MachineInstr &MI) {
673 return SIInstrFlags::isMIMG(O: MI);
674 }
675
676 bool isMIMG(uint32_t Opcode) const {
677 return SIInstrFlags::isMIMG(O: get(Opcode));
678 }
679
680 static bool isVIMAGE(const MachineInstr &MI) {
681 return SIInstrFlags::isVIMAGE(O: MI);
682 }
683
684 bool isVIMAGE(uint32_t Opcode) const {
685 return SIInstrFlags::isVIMAGE(O: get(Opcode));
686 }
687
688 static bool isVSAMPLE(const MachineInstr &MI) {
689 return SIInstrFlags::isVSAMPLE(O: MI);
690 }
691
692 bool isVSAMPLE(uint32_t Opcode) const {
693 return SIInstrFlags::isVSAMPLE(O: get(Opcode));
694 }
695
696 static bool isGather4(const MachineInstr &MI) {
697 return SIInstrFlags::isGather4(O: MI);
698 }
699
700 bool isGather4(uint32_t Opcode) const {
701 return SIInstrFlags::isGather4(O: get(Opcode));
702 }
703
704 static bool isFLAT(const MachineInstr &MI) {
705 return SIInstrFlags::isFLAT(O: MI);
706 }
707
708 // Is a FLAT encoded instruction which accesses a specific segment,
709 // i.e. global_* or scratch_*.
710 static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
711 return SIInstrFlags::isSegmentSpecificFLAT(O: MI);
712 }
713
714 bool isSegmentSpecificFLAT(uint32_t Opcode) const {
715 return SIInstrFlags::isSegmentSpecificFLAT(O: get(Opcode));
716 }
717
718 static bool isFLATGlobal(const MachineInstr &MI) {
719 return SIInstrFlags::isFlatGlobal(O: MI);
720 }
721
722 bool isFLATGlobal(uint32_t Opcode) const {
723 return SIInstrFlags::isFlatGlobal(O: get(Opcode));
724 }
725
726 static bool isFLATScratch(const MachineInstr &MI) {
727 return SIInstrFlags::isFlatScratch(O: MI);
728 }
729
730 bool isFLATScratch(uint32_t Opcode) const {
731 return SIInstrFlags::isFlatScratch(O: get(Opcode));
732 }
733
734 // Any FLAT encoded instruction, including global_* and scratch_*.
735 bool isFLAT(uint32_t Opcode) const {
736 return SIInstrFlags::isFLAT(O: get(Opcode));
737 }
738
739 /// \returns true for SCRATCH_ instructions, or FLAT/BUF instructions unless
740 /// the MMOs do not include scratch.
741 /// Conservatively correct; will return true if \p MI cannot be proven
742 /// to not hit scratch.
743 bool mayAccessScratch(const MachineInstr &MI) const;
744
745 /// \returns true for FLAT instructions that can access VMEM.
746 bool mayAccessVMEMThroughFlat(const MachineInstr &MI) const;
747
748 /// \returns true for FLAT instructions that can access LDS.
749 bool mayAccessLDSThroughFlat(const MachineInstr &MI, bool TgSplit) const;
750
751 static bool isBlockLoadStore(uint32_t Opcode) {
752 switch (Opcode) {
753 case AMDGPU::SI_BLOCK_SPILL_V1024_SAVE:
754 case AMDGPU::SI_BLOCK_SPILL_V1024_CFI_SAVE:
755 case AMDGPU::SI_BLOCK_SPILL_V1024_RESTORE:
756 case AMDGPU::SCRATCH_STORE_BLOCK_SADDR:
757 case AMDGPU::SCRATCH_LOAD_BLOCK_SADDR:
758 case AMDGPU::SCRATCH_STORE_BLOCK_SVS:
759 case AMDGPU::SCRATCH_LOAD_BLOCK_SVS:
760 return true;
761 default:
762 return false;
763 }
764 }
765
766 static bool setsSCCIfResultIsNonZero(const MachineInstr &MI) {
767 switch (MI.getOpcode()) {
768 case AMDGPU::S_ABSDIFF_I32:
769 case AMDGPU::S_ABS_I32:
770 case AMDGPU::S_AND_B32:
771 case AMDGPU::S_AND_B64:
772 case AMDGPU::S_ANDN2_B32:
773 case AMDGPU::S_ANDN2_B64:
774 case AMDGPU::S_ASHR_I32:
775 case AMDGPU::S_ASHR_I64:
776 case AMDGPU::S_BCNT0_I32_B32:
777 case AMDGPU::S_BCNT0_I32_B64:
778 case AMDGPU::S_BCNT1_I32_B32:
779 case AMDGPU::S_BCNT1_I32_B64:
780 case AMDGPU::S_BFE_I32:
781 case AMDGPU::S_BFE_I64:
782 case AMDGPU::S_BFE_U32:
783 case AMDGPU::S_BFE_U64:
784 case AMDGPU::S_LSHL_B32:
785 case AMDGPU::S_LSHL_B64:
786 case AMDGPU::S_LSHR_B32:
787 case AMDGPU::S_LSHR_B64:
788 case AMDGPU::S_NAND_B32:
789 case AMDGPU::S_NAND_B64:
790 case AMDGPU::S_NOR_B32:
791 case AMDGPU::S_NOR_B64:
792 case AMDGPU::S_NOT_B32:
793 case AMDGPU::S_NOT_B64:
794 case AMDGPU::S_OR_B32:
795 case AMDGPU::S_OR_B64:
796 case AMDGPU::S_ORN2_B32:
797 case AMDGPU::S_ORN2_B64:
798 case AMDGPU::S_QUADMASK_B32:
799 case AMDGPU::S_QUADMASK_B64:
800 case AMDGPU::S_WQM_B32:
801 case AMDGPU::S_WQM_B64:
802 case AMDGPU::S_XNOR_B32:
803 case AMDGPU::S_XNOR_B64:
804 case AMDGPU::S_XOR_B32:
805 case AMDGPU::S_XOR_B64:
806 return true;
807 default:
808 return false;
809 }
810 }
811
812 static bool isEXP(const MachineInstr &MI) { return SIInstrFlags::isEXP(O: MI); }
813
814 static bool isDualSourceBlendEXP(const MachineInstr &MI) {
815 if (!isEXP(MI))
816 return false;
817 unsigned Target = MI.getOperand(i: 0).getImm();
818 return Target == AMDGPU::Exp::ET_DUAL_SRC_BLEND0 ||
819 Target == AMDGPU::Exp::ET_DUAL_SRC_BLEND1;
820 }
821
822 bool isEXP(uint32_t Opcode) const { return SIInstrFlags::isEXP(O: get(Opcode)); }
823
824 static bool isAtomicNoRet(const MachineInstr &MI) {
825 return SIInstrFlags::isAtomicNoRet(O: MI);
826 }
827
828 bool isAtomicNoRet(uint32_t Opcode) const {
829 return SIInstrFlags::isAtomicNoRet(O: get(Opcode));
830 }
831
832 static bool isAtomicRet(const MachineInstr &MI) {
833 return SIInstrFlags::isAtomicRet(O: MI);
834 }
835
836 bool isAtomicRet(uint32_t Opcode) const {
837 return SIInstrFlags::isAtomicRet(O: get(Opcode));
838 }
839
840 static bool isAtomic(const MachineInstr &MI) {
841 return SIInstrFlags::isAtomic(O: MI);
842 }
843
844 bool isAtomic(uint32_t Opcode) const {
845 return SIInstrFlags::isAtomic(O: get(Opcode));
846 }
847
848 static bool mayWriteLDSThroughDMA(const MachineInstr &MI) {
849 unsigned Opc = MI.getOpcode();
850 // Exclude instructions that read FROM LDS (not write to it)
851 return isLDSDMA(MI) && Opc != AMDGPU::BUFFER_STORE_LDS_DWORD &&
852 Opc != AMDGPU::TENSOR_STORE_FROM_LDS_d2 &&
853 Opc != AMDGPU::TENSOR_STORE_FROM_LDS_d4;
854 }
855
856 static bool isSBarrierSCCWrite(unsigned Opcode) {
857 return Opcode == AMDGPU::S_BARRIER_LEAVE ||
858 Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_IMM ||
859 Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_M0;
860 }
861
862 static bool isCBranchVCCZRead(const MachineInstr &MI) {
863 unsigned Opc = MI.getOpcode();
864 return (Opc == AMDGPU::S_CBRANCH_VCCNZ || Opc == AMDGPU::S_CBRANCH_VCCZ) &&
865 !MI.getOperand(i: 1).isUndef();
866 }
867
868 static bool isWQM(const MachineInstr &MI) { return SIInstrFlags::isWQM(O: MI); }
869
870 bool isWQM(uint32_t Opcode) const { return SIInstrFlags::isWQM(O: get(Opcode)); }
871
872 static bool isDisableWQM(const MachineInstr &MI) {
873 return SIInstrFlags::isDisableWQM(O: MI);
874 }
875
876 bool isDisableWQM(uint32_t Opcode) const {
877 return SIInstrFlags::isDisableWQM(O: get(Opcode));
878 }
879
880 // SI_SPILL_S32_TO_VGPR and SI_RESTORE_S32_FROM_VGPR form a special case of
881 // SGPRs spilling to VGPRs which are SGPR spills but from VALU instructions
882 // therefore we need an explicit check for them since just checking if the
883 // Spill bit is set and what instruction type it came from misclassifies
884 // them.
885 static bool isVGPRSpill(const MachineInstr &MI) {
886 return MI.getOpcode() != AMDGPU::SI_SPILL_S32_TO_VGPR &&
887 MI.getOpcode() != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
888 (isSpill(MI) && isVALU(MI, /*AllowLDSDMA=*/AllowLDSDMA: true));
889 }
890
891 bool isVGPRSpill(uint32_t Opcode) const {
892 return Opcode != AMDGPU::SI_SPILL_S32_TO_VGPR &&
893 Opcode != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
894 (isSpill(Opcode) && isVALU(Opcode, /*AllowLDSDMA=*/AllowLDSDMA: true));
895 }
896
897 static bool isSGPRSpill(const MachineInstr &MI) {
898 return MI.getOpcode() == AMDGPU::SI_SPILL_S32_TO_VGPR ||
899 MI.getOpcode() == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
900 (isSpill(MI) && isSALU(MI));
901 }
902
903 bool isSGPRSpill(uint32_t Opcode) const {
904 return Opcode == AMDGPU::SI_SPILL_S32_TO_VGPR ||
905 Opcode == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
906 (isSpill(Opcode) && isSALU(Opcode));
907 }
908
909 bool isSpill(uint32_t Opcode) const {
910 return SIInstrFlags::isSpill(O: get(Opcode));
911 }
912
913 static bool isSpill(const MCInstrDesc &Desc) {
914 return SIInstrFlags::isSpill(O: Desc);
915 }
916
917 static bool isSpill(const MachineInstr &MI) { return isSpill(Desc: MI.getDesc()); }
918
919 static bool isWWMRegSpillOpcode(uint32_t Opcode) {
920 return Opcode == AMDGPU::SI_SPILL_WWM_V32_SAVE ||
921 Opcode == AMDGPU::SI_SPILL_WWM_AV32_SAVE ||
922 Opcode == AMDGPU::SI_SPILL_WWM_V32_RESTORE ||
923 Opcode == AMDGPU::SI_SPILL_WWM_AV32_RESTORE;
924 }
925
926 static bool isChainCallOpcode(uint64_t Opcode) {
927 return Opcode == AMDGPU::SI_CS_CHAIN_TC_W32 ||
928 Opcode == AMDGPU::SI_CS_CHAIN_TC_W64;
929 }
930
931 static bool isDPP(const MachineInstr &MI) { return SIInstrFlags::isDPP(O: MI); }
932
933 bool isDPP(uint32_t Opcode) const { return SIInstrFlags::isDPP(O: get(Opcode)); }
934
935 static bool isTRANS(const MachineInstr &MI) {
936 return SIInstrFlags::isTRANS(O: MI);
937 }
938
939 bool isTRANS(uint32_t Opcode) const {
940 return SIInstrFlags::isTRANS(O: get(Opcode));
941 }
942
943 static bool isVOP3P(const MachineInstr &MI) {
944 return SIInstrFlags::isVOP3P(O: MI);
945 }
946
947 bool isVOP3P(uint32_t Opcode) const {
948 return SIInstrFlags::isVOP3P(O: get(Opcode));
949 }
950
951 bool isVOP3PMix(const MachineInstr &MI) const {
952 return isVOP3PMix(Opcode: MI.getOpcode());
953 }
954
955 bool isVOP3PMix(uint16_t Opcode) const {
956 switch (Opcode) {
957 case AMDGPU::V_FMA_MIXHI_F16:
958 case AMDGPU::V_FMA_MIXLO_F16:
959 case AMDGPU::V_FMA_MIX_F32:
960 case AMDGPU::V_MAD_MIXHI_F16:
961 case AMDGPU::V_MAD_MIXLO_F16:
962 case AMDGPU::V_MAD_MIX_F32:
963 return true;
964 default:
965 return false;
966 }
967 }
968
969 static bool isVINTRP(const MachineInstr &MI) {
970 return SIInstrFlags::isVINTRP(O: MI);
971 }
972
973 bool isVINTRP(uint32_t Opcode) const {
974 return SIInstrFlags::isVINTRP(O: get(Opcode));
975 }
976
977 static bool isMAI(const MCInstrDesc &Desc) {
978 return SIInstrFlags::isMAI(O: Desc);
979 }
980
981 static bool isMAI(const MachineInstr &MI) { return isMAI(Desc: MI.getDesc()); }
982
983 bool isMAI(uint32_t Opcode) const { return isMAI(Desc: get(Opcode)); }
984
985 static bool isMFMA(const MachineInstr &MI) {
986 return isMAI(MI) && MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
987 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64;
988 }
989
990 bool isMFMA(uint32_t Opcode) const {
991 return isMAI(Opcode) && Opcode != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
992 Opcode != AMDGPU::V_ACCVGPR_READ_B32_e64;
993 }
994
995 static bool isDOT(const MachineInstr &MI) { return SIInstrFlags::isDOT(O: MI); }
996
997 static bool isWMMA(const MachineInstr &MI) {
998 return SIInstrFlags::isWMMA(O: MI);
999 }
1000
1001 bool isWMMA(uint32_t Opcode) const {
1002 return SIInstrFlags::isWMMA(O: get(Opcode));
1003 }
1004
1005 static bool isMFMAorWMMA(const MachineInstr &MI) {
1006 return isMFMA(MI) || isWMMA(MI) || isSWMMAC(MI);
1007 }
1008
1009 bool isMFMAorWMMA(uint32_t Opcode) const {
1010 return isMFMA(Opcode) || isWMMA(Opcode) || isSWMMAC(Opcode);
1011 }
1012
1013 static bool isSWMMAC(const MachineInstr &MI) {
1014 return SIInstrFlags::isSWMMAC(O: MI);
1015 }
1016
1017 bool isSWMMAC(uint32_t Opcode) const {
1018 return SIInstrFlags::isSWMMAC(O: get(Opcode));
1019 }
1020
1021 bool isDOT(uint32_t Opcode) const { return SIInstrFlags::isDOT(O: get(Opcode)); }
1022
1023 bool isXDLWMMA(const MachineInstr &MI) const;
1024
1025 bool isXDL(const MachineInstr &MI) const;
1026
1027 static bool isDGEMM(unsigned Opcode) { return AMDGPU::getMAIIsDGEMM(Opc: Opcode); }
1028
1029 static bool isLDSDIR(const MachineInstr &MI) {
1030 return SIInstrFlags::isLDSDIR(O: MI);
1031 }
1032
1033 bool isLDSDIR(uint32_t Opcode) const {
1034 return SIInstrFlags::isLDSDIR(O: get(Opcode));
1035 }
1036
1037 static bool isVINTERP(const MachineInstr &MI) {
1038 return SIInstrFlags::isVINTERP(O: MI);
1039 }
1040
1041 bool isVINTERP(uint32_t Opcode) const {
1042 return SIInstrFlags::isVINTERP(O: get(Opcode));
1043 }
1044
1045 static bool isScalarUnit(const MachineInstr &MI) {
1046 return SIInstrFlags::isSALU(O: MI) || SIInstrFlags::isSMRD(O: MI);
1047 }
1048
1049 static bool usesVM_CNT(const MachineInstr &MI) {
1050 return SIInstrFlags::usesVM_CNT(O: MI);
1051 }
1052
1053 static bool usesLGKM_CNT(const MachineInstr &MI) {
1054 return SIInstrFlags::usesLGKM_CNT(O: MI);
1055 }
1056
1057 static bool usesASYNC_CNT(const MachineInstr &MI) {
1058 return SIInstrFlags::usesASYNC_CNT(O: MI);
1059 }
1060
1061 bool usesASYNC_CNT(uint32_t Opcode) const {
1062 return SIInstrFlags::usesASYNC_CNT(O: get(Opcode));
1063 }
1064
1065 static bool usesTENSOR_CNT(const MachineInstr &MI) {
1066 return SIInstrFlags::usesTENSOR_CNT(O: MI);
1067 }
1068
1069 bool usesTENSOR_CNT(uint32_t Opcode) const {
1070 return SIInstrFlags::usesTENSOR_CNT(O: get(Opcode));
1071 }
1072
1073 // Most sopk treat the immediate as a signed 16-bit, however some
1074 // use it as unsigned.
1075 static bool sopkIsZext(unsigned Opcode) {
1076 return Opcode == AMDGPU::S_CMPK_EQ_U32 || Opcode == AMDGPU::S_CMPK_LG_U32 ||
1077 Opcode == AMDGPU::S_CMPK_GT_U32 || Opcode == AMDGPU::S_CMPK_GE_U32 ||
1078 Opcode == AMDGPU::S_CMPK_LT_U32 || Opcode == AMDGPU::S_CMPK_LE_U32 ||
1079 Opcode == AMDGPU::S_GETREG_B32 ||
1080 Opcode == AMDGPU::S_GETREG_B32_const;
1081 }
1082
1083 /// \returns true if this is an s_store_dword* instruction. This is more
1084 /// specific than isSMEM && mayStore.
1085 static bool isScalarStore(const MachineInstr &MI) {
1086 return SIInstrFlags::isScalarStore(O: MI);
1087 }
1088
1089 bool isScalarStore(uint32_t Opcode) const {
1090 return SIInstrFlags::isScalarStore(O: get(Opcode));
1091 }
1092
1093 static bool isFixedSize(const MachineInstr &MI) {
1094 return SIInstrFlags::isFixedSize(O: MI);
1095 }
1096
1097 bool isFixedSize(uint32_t Opcode) const {
1098 return SIInstrFlags::isFixedSize(O: get(Opcode));
1099 }
1100
1101 static bool hasFPClamp(const MachineInstr &MI) {
1102 return SIInstrFlags::hasFPClamp(O: MI);
1103 }
1104
1105 bool hasFPClamp(uint32_t Opcode) const {
1106 return SIInstrFlags::hasFPClamp(O: get(Opcode));
1107 }
1108
1109 static bool hasIntClamp(const MachineInstr &MI) {
1110 return SIInstrFlags::hasIntClamp(O: MI);
1111 }
1112
1113 static bool hasSameClamp(const MachineInstr &A, const MachineInstr &B) {
1114 const MCInstrDesc &DA = A.getDesc(), &DB = B.getDesc();
1115 return SIInstrFlags::hasFPClamp(O: DA) == SIInstrFlags::hasFPClamp(O: DB) &&
1116 SIInstrFlags::hasIntClamp(O: DA) == SIInstrFlags::hasIntClamp(O: DB) &&
1117 SIInstrFlags::hasClampLo(O: DA) == SIInstrFlags::hasClampLo(O: DB) &&
1118 SIInstrFlags::hasClampHi(O: DA) == SIInstrFlags::hasClampHi(O: DB);
1119 }
1120
1121 static bool usesFPDPRounding(const MachineInstr &MI) {
1122 return SIInstrFlags::usesFPDPRounding(O: MI);
1123 }
1124
1125 bool usesFPDPRounding(uint32_t Opcode) const {
1126 return SIInstrFlags::usesFPDPRounding(O: get(Opcode));
1127 }
1128
1129 static bool isFPAtomic(const MachineInstr &MI) {
1130 return SIInstrFlags::isFPAtomic(O: MI);
1131 }
1132
1133 bool isFPAtomic(uint32_t Opcode) const {
1134 return SIInstrFlags::isFPAtomic(O: get(Opcode));
1135 }
1136
1137 static bool isNeverUniform(const MachineInstr &MI) {
1138 return SIInstrFlags::isNeverUniform(O: MI);
1139 }
1140
1141 // Check to see if opcode is for a barrier start. Pre gfx12 this is just the
1142 // S_BARRIER, but after support for S_BARRIER_SIGNAL* / S_BARRIER_WAIT we want
1143 // to check for the barrier start (S_BARRIER_SIGNAL*)
1144 bool isBarrierStart(unsigned Opcode) const {
1145 return Opcode == AMDGPU::S_BARRIER ||
1146 Opcode == AMDGPU::S_BARRIER_SIGNAL_M0 ||
1147 Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_M0 ||
1148 Opcode == AMDGPU::S_BARRIER_SIGNAL_IMM ||
1149 Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_IMM;
1150 }
1151
1152 bool isBarrier(unsigned Opcode) const {
1153 return isBarrierStart(Opcode) || Opcode == AMDGPU::S_BARRIER_WAIT ||
1154 Opcode == AMDGPU::S_BARRIER_INIT_M0 ||
1155 Opcode == AMDGPU::S_BARRIER_INIT_IMM ||
1156 Opcode == AMDGPU::S_BARRIER_JOIN_IMM ||
1157 Opcode == AMDGPU::S_BARRIER_LEAVE || Opcode == AMDGPU::DS_GWS_INIT ||
1158 Opcode == AMDGPU::DS_GWS_BARRIER;
1159 }
1160
1161 static bool isLoadMonitor(unsigned Opc) {
1162 switch (Opc) {
1163 case AMDGPU::GLOBAL_LOAD_MONITOR_B32:
1164 case AMDGPU::GLOBAL_LOAD_MONITOR_B32_SADDR:
1165 case AMDGPU::GLOBAL_LOAD_MONITOR_B64:
1166 case AMDGPU::GLOBAL_LOAD_MONITOR_B64_SADDR:
1167 case AMDGPU::GLOBAL_LOAD_MONITOR_B128:
1168 case AMDGPU::GLOBAL_LOAD_MONITOR_B128_SADDR:
1169 case AMDGPU::FLAT_LOAD_MONITOR_B32:
1170 case AMDGPU::FLAT_LOAD_MONITOR_B64:
1171 case AMDGPU::FLAT_LOAD_MONITOR_B128:
1172 return true;
1173 default:
1174 return false;
1175 }
1176 }
1177
1178 static bool isGFX12CacheInvOrWBInst(unsigned Opc) {
1179 return Opc == AMDGPU::GLOBAL_INV || Opc == AMDGPU::GLOBAL_WB ||
1180 Opc == AMDGPU::GLOBAL_WBINV;
1181 }
1182
1183 static bool isF16PseudoScalarTrans(unsigned Opcode) {
1184 return Opcode == AMDGPU::V_S_EXP_F16_e64 ||
1185 Opcode == AMDGPU::V_S_LOG_F16_e64 ||
1186 Opcode == AMDGPU::V_S_RCP_F16_e64 ||
1187 Opcode == AMDGPU::V_S_RSQ_F16_e64 ||
1188 Opcode == AMDGPU::V_S_SQRT_F16_e64;
1189 }
1190
1191 static bool doesNotReadTiedSource(const MachineInstr &MI) {
1192 return SIInstrFlags::isTiedSourceNotRead(O: MI);
1193 }
1194
1195 bool doesNotReadTiedSource(uint32_t Opcode) const {
1196 return SIInstrFlags::isTiedSourceNotRead(O: get(Opcode));
1197 }
1198
1199 bool isIGLP(unsigned Opcode) const {
1200 return Opcode == AMDGPU::SCHED_BARRIER ||
1201 Opcode == AMDGPU::SCHED_GROUP_BARRIER || Opcode == AMDGPU::IGLP_OPT;
1202 }
1203
1204 bool isIGLP(const MachineInstr &MI) const { return isIGLP(Opcode: MI.getOpcode()); }
1205
1206 // Return true if the instruction is mutually exclusive with all non-IGLP DAG
1207 // mutations, requiring all other mutations to be disabled.
1208 bool isIGLPMutationOnly(unsigned Opcode) const {
1209 return Opcode == AMDGPU::SCHED_GROUP_BARRIER || Opcode == AMDGPU::IGLP_OPT;
1210 }
1211
1212 static unsigned getNonSoftWaitcntOpcode(unsigned Opcode) {
1213 switch (Opcode) {
1214 case AMDGPU::S_WAITCNT_soft:
1215 return AMDGPU::S_WAITCNT;
1216 case AMDGPU::S_WAITCNT_VSCNT_soft:
1217 return AMDGPU::S_WAITCNT_VSCNT;
1218 case AMDGPU::S_WAIT_LOADCNT_soft:
1219 return AMDGPU::S_WAIT_LOADCNT;
1220 case AMDGPU::S_WAIT_STORECNT_soft:
1221 return AMDGPU::S_WAIT_STORECNT;
1222 case AMDGPU::S_WAIT_SAMPLECNT_soft:
1223 return AMDGPU::S_WAIT_SAMPLECNT;
1224 case AMDGPU::S_WAIT_BVHCNT_soft:
1225 return AMDGPU::S_WAIT_BVHCNT;
1226 case AMDGPU::S_WAIT_DSCNT_soft:
1227 return AMDGPU::S_WAIT_DSCNT;
1228 case AMDGPU::S_WAIT_KMCNT_soft:
1229 return AMDGPU::S_WAIT_KMCNT;
1230 case AMDGPU::S_WAIT_XCNT_soft:
1231 return AMDGPU::S_WAIT_XCNT;
1232 default:
1233 return Opcode;
1234 }
1235 }
1236
1237 static bool isWaitcnt(unsigned Opcode) {
1238 switch (getNonSoftWaitcntOpcode(Opcode)) {
1239 case AMDGPU::S_WAITCNT:
1240 case AMDGPU::S_WAITCNT_VSCNT:
1241 case AMDGPU::S_WAITCNT_VMCNT:
1242 case AMDGPU::S_WAITCNT_EXPCNT:
1243 case AMDGPU::S_WAITCNT_LGKMCNT:
1244 case AMDGPU::S_WAIT_LOADCNT:
1245 case AMDGPU::S_WAIT_LOADCNT_DSCNT:
1246 case AMDGPU::S_WAIT_STORECNT:
1247 case AMDGPU::S_WAIT_STORECNT_DSCNT:
1248 case AMDGPU::S_WAIT_SAMPLECNT:
1249 case AMDGPU::S_WAIT_BVHCNT:
1250 case AMDGPU::S_WAIT_EXPCNT:
1251 case AMDGPU::S_WAIT_DSCNT:
1252 case AMDGPU::S_WAIT_KMCNT:
1253 case AMDGPU::S_WAIT_XCNT:
1254 case AMDGPU::S_WAIT_IDLE:
1255 return true;
1256 default:
1257 return false;
1258 }
1259 }
1260
1261 bool isVGPRCopy(const MachineInstr &MI) const {
1262 assert(isCopyInstr(MI));
1263 Register Dest = MI.getOperand(i: 0).getReg();
1264 const MachineFunction &MF = *MI.getMF();
1265 const MachineRegisterInfo &MRI = MF.getRegInfo();
1266 return !RI.isSGPRReg(MRI, Reg: Dest);
1267 }
1268
1269 bool hasVGPRUses(const MachineInstr &MI) const {
1270 const MachineFunction &MF = *MI.getMF();
1271 const MachineRegisterInfo &MRI = MF.getRegInfo();
1272 return llvm::any_of(Range: MI.explicit_uses(),
1273 P: [&MRI, this](const MachineOperand &MO) {
1274 return MO.isReg() && RI.isVGPR(MRI, Reg: MO.getReg());});
1275 }
1276
1277 /// Return true if the instruction modifies the mode register.q
1278 static bool modifiesModeRegister(const MachineInstr &MI);
1279
1280 /// This function is used to determine if an instruction can be safely
1281 /// executed under EXEC = 0 without hardware error, indeterminate results,
1282 /// and/or visible effects on future vector execution or outside the shader.
1283 /// Note: as of 2024 the only use of this is SIPreEmitPeephole where it is
1284 /// used in removing branches over short EXEC = 0 sequences.
1285 /// As such it embeds certain assumptions which may not apply to every case
1286 /// of EXEC = 0 execution.
1287 bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const;
1288
1289 /// Returns true if the instruction could potentially depend on the value of
1290 /// exec. If false, exec dependencies may safely be ignored.
1291 bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
1292
1293 bool isInlineConstant(const APInt &Imm) const;
1294
1295 bool isInlineConstant(const APFloat &Imm) const;
1296
1297 // Returns true if this non-register operand definitely does not need to be
1298 // encoded as a 32-bit literal. Note that this function handles all kinds of
1299 // operands, not just immediates.
1300 //
1301 // Some operands like FrameIndexes could resolve to an inline immediate value
1302 // that will not require an additional 4-bytes; this function assumes that it
1303 // will.
1304 bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const {
1305 if (!MO.isImm())
1306 return false;
1307 return isInlineConstant(ImmVal: MO.getImm(), OperandType);
1308 }
1309 bool isInlineConstant(int64_t ImmVal, uint8_t OperandType) const;
1310
1311 bool isInlineConstant(const MachineOperand &MO,
1312 const MCOperandInfo &OpInfo) const {
1313 return isInlineConstant(MO, OperandType: OpInfo.OperandType);
1314 }
1315
1316 /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
1317 /// be an inline immediate.
1318 bool isInlineConstant(const MachineInstr &MI,
1319 const MachineOperand &UseMO,
1320 const MachineOperand &DefMO) const {
1321 assert(UseMO.getParent() == &MI);
1322 int OpIdx = UseMO.getOperandNo();
1323 if (OpIdx >= MI.getDesc().NumOperands)
1324 return false;
1325
1326 return isInlineConstant(MO: DefMO, OpInfo: MI.getDesc().operands()[OpIdx]);
1327 }
1328
1329 /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
1330 /// immediate.
1331 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
1332 const MachineOperand &MO = MI.getOperand(i: OpIdx);
1333 return isInlineConstant(MO, OperandType: MI.getDesc().operands()[OpIdx].OperandType);
1334 }
1335
1336 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
1337 int64_t ImmVal) const {
1338 if (OpIdx >= MI.getDesc().NumOperands)
1339 return false;
1340
1341 if (isCopyInstr(MI)) {
1342 unsigned Size = getOpSize(MI, OpNo: OpIdx);
1343 assert(Size == 8 || Size == 4);
1344
1345 uint8_t OpType = (Size == 8) ?
1346 AMDGPU::OPERAND_REG_IMM_INT64 : AMDGPU::OPERAND_REG_IMM_INT32;
1347 return isInlineConstant(ImmVal, OperandType: OpType);
1348 }
1349
1350 return isInlineConstant(ImmVal, OperandType: MI.getDesc().operands()[OpIdx].OperandType);
1351 }
1352
1353 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
1354 const MachineOperand &MO) const {
1355 return isInlineConstant(MI, OpIdx, ImmVal: MO.getImm());
1356 }
1357
1358 bool isInlineConstant(const MachineOperand &MO) const {
1359 return isInlineConstant(MI: *MO.getParent(), OpIdx: MO.getOperandNo());
1360 }
1361
1362 bool isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
1363 const MachineOperand &MO) const;
1364
1365 bool isLiteralOperandLegal(const MCInstrDesc &InstDesc,
1366 const MCOperandInfo &OpInfo) const;
1367
1368 bool isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
1369 int64_t ImmVal) const;
1370
1371 bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
1372 const MachineOperand &MO) const {
1373 return isImmOperandLegal(InstDesc: MI.getDesc(), OpNo, MO);
1374 }
1375
1376 bool isNeverCoissue(MachineInstr &MI) const;
1377
1378 /// Check if this immediate value can be used for AV_MOV_B64_IMM_PSEUDO.
1379 bool isLegalAV64PseudoImm(uint64_t Imm) const;
1380
1381 /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
1382 /// This function will return false if you pass it a 32-bit instruction.
1383 bool hasVALU32BitEncoding(unsigned Opcode) const;
1384
1385 bool physRegUsesConstantBus(const MachineOperand &Reg) const;
1386 bool regUsesConstantBus(const MachineOperand &Reg,
1387 const MachineRegisterInfo &MRI) const;
1388
1389 /// Returns true if this operand uses the constant bus.
1390 bool usesConstantBus(const MachineRegisterInfo &MRI,
1391 const MachineOperand &MO,
1392 const MCOperandInfo &OpInfo) const;
1393
1394 bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineInstr &MI,
1395 int OpIdx) const {
1396 return usesConstantBus(MRI, MO: MI.getOperand(i: OpIdx),
1397 OpInfo: MI.getDesc().operands()[OpIdx]);
1398 }
1399
1400 /// Return true if this instruction has any modifiers.
1401 /// e.g. src[012]_mod, omod, clamp.
1402 bool hasModifiers(unsigned Opcode) const;
1403
1404 bool hasModifiersSet(const MachineInstr &MI, AMDGPU::OpName OpName) const;
1405 bool hasAnyModifiersSet(const MachineInstr &MI) const;
1406
1407 bool canShrink(const MachineInstr &MI,
1408 const MachineRegisterInfo &MRI) const;
1409
1410 MachineInstr *buildShrunkInst(MachineInstr &MI,
1411 unsigned NewOpcode) const;
1412
1413 bool verifyInstruction(const MachineInstr &MI,
1414 StringRef &ErrInfo) const override;
1415
1416 unsigned getVALUOp(const MachineInstr &MI) const;
1417 unsigned getVALUOp(unsigned Opc) const;
1418
1419 void insertScratchExecCopy(MachineFunction &MF, MachineBasicBlock &MBB,
1420 MachineBasicBlock::iterator MBBI,
1421 const DebugLoc &DL, Register Reg, bool IsSCCLive,
1422 SlotIndexes *Indexes = nullptr) const;
1423
1424 void restoreExec(MachineFunction &MF, MachineBasicBlock &MBB,
1425 MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
1426 Register Reg, SlotIndexes *Indexes = nullptr) const;
1427
1428 MachineInstr *getWholeWaveFunctionSetup(MachineFunction &MF) const;
1429
1430 /// Return the correct register class for \p OpNo. For target-specific
1431 /// instructions, this will return the register class that has been defined
1432 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
1433 /// the register class of its machine operand.
1434 /// to infer the correct register class base on the other operands.
1435 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
1436 unsigned OpNo) const;
1437
1438 /// Return the size in bytes of the operand OpNo on the given
1439 // instruction opcode.
1440 unsigned getOpSize(uint32_t Opcode, unsigned OpNo) const {
1441 const MCOperandInfo &OpInfo = get(Opcode).operands()[OpNo];
1442
1443 if (OpInfo.RegClass == -1) {
1444 // If this is an immediate operand, this must be a 32-bit literal.
1445 assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
1446 return 4;
1447 }
1448
1449 return RI.getRegSizeInBits(RC: *RI.getRegClass(i: getOpRegClassID(OpInfo))) / 8;
1450 }
1451
1452 /// This form should usually be preferred since it handles operands
1453 /// with unknown register classes.
1454 unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
1455 const MachineOperand &MO = MI.getOperand(i: OpNo);
1456 if (MO.isReg()) {
1457 if (unsigned SubReg = MO.getSubReg()) {
1458 return RI.getSubRegIdxSize(Idx: SubReg) / 8;
1459 }
1460 }
1461 return RI.getRegSizeInBits(RC: *getOpRegClass(MI, OpNo)) / 8;
1462 }
1463
1464 /// Legalize the \p OpIndex operand of this instruction by inserting
1465 /// a MOV. For example:
1466 /// ADD_I32_e32 VGPR0, 15
1467 /// to
1468 /// MOV VGPR1, 15
1469 /// ADD_I32_e32 VGPR0, VGPR1
1470 ///
1471 /// If the operand being legalized is a register, then a COPY will be used
1472 /// instead of MOV.
1473 void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
1474
1475 /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
1476 /// for \p MI.
1477 bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
1478 const MachineOperand *MO = nullptr) const;
1479
1480 /// Check if \p MO would be a valid operand for the given operand
1481 /// definition \p OpInfo. Note this does not attempt to validate constant bus
1482 /// restrictions (e.g. literal constant usage).
1483 bool isLegalVSrcOperand(const MachineRegisterInfo &MRI,
1484 const MCOperandInfo &OpInfo,
1485 const MachineOperand &MO) const;
1486
1487 /// Check if \p MO (a register operand) is a legal register for the
1488 /// given operand description or operand index.
1489 /// The operand index version provide more legality checks
1490 bool isLegalRegOperand(const MachineRegisterInfo &MRI,
1491 const MCOperandInfo &OpInfo,
1492 const MachineOperand &MO) const;
1493 bool isLegalRegOperand(const MachineInstr &MI, unsigned OpIdx,
1494 const MachineOperand &MO) const;
1495
1496 /// Check if \p MO would be a legal operand for a single-SGPR-read
1497 /// instruction.
1498 ///
1499 /// Single-SGPR-read instructions typically accept VGPRs, SGPRs, or immediates
1500 /// as source operands. On gfx12+, if a source operand uses SGPRs, the HW can
1501 /// only read the first SGPR and replicate the value across all lanes. \p SrcN
1502 /// can be 0, 1, or 2, representing src0, src1, and src2, respectively. If \p
1503 /// MO is nullptr, the operand corresponding to \p SrcN will be used. Non-SGPR
1504 /// operands are always considered legal.
1505 bool
1506 isLegalSingleSGPRReadInstOperand(const MachineRegisterInfo &MRI,
1507 const MachineInstr &MI, unsigned SrcN,
1508 const MachineOperand *MO = nullptr) const;
1509
1510 /// Legalize operands in \p MI by either commuting it or inserting a
1511 /// copy of src1.
1512 void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const;
1513
1514 /// Fix operands in \p MI to satisfy constant bus requirements.
1515 void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const;
1516
1517 /// Copy a value from a VGPR (\p SrcReg) to SGPR. The desired register class
1518 /// for the dst register (\p DstRC) can be optionally supplied. This function
1519 /// can only be used when it is know that the value in SrcReg is same across
1520 /// all threads in the wave.
1521 /// \returns The SGPR register that \p SrcReg was copied to.
1522 Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI,
1523 MachineRegisterInfo &MRI,
1524 const TargetRegisterClass *DstRC = nullptr) const;
1525
1526 void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;
1527 void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const;
1528
1529 void legalizeGenericOperand(MachineBasicBlock &InsertMBB,
1530 MachineBasicBlock::iterator I,
1531 const TargetRegisterClass *DstRC,
1532 MachineOperand &Op, MachineRegisterInfo &MRI,
1533 const DebugLoc &DL) const;
1534
1535 /// Legalize all operands in this instruction. This function may create new
1536 /// instructions and control-flow around \p MI. If present, \p MDT is
1537 /// updated.
1538 /// \returns A new basic block that contains \p MI if new blocks were created.
1539 MachineBasicBlock *
1540 legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
1541
1542 /// Change SADDR form of a FLAT \p Inst to its VADDR form if saddr operand
1543 /// was moved to VGPR. \returns true if succeeded.
1544 bool moveFlatAddrToVGPR(MachineInstr &Inst) const;
1545
1546 /// Fix operands in Inst to fix 16bit SALU to VALU lowering.
1547 void legalizeOperandsVALUt16(MachineInstr &Inst,
1548 MachineRegisterInfo &MRI) const;
1549 void legalizeOperandsVALUt16(MachineInstr &Inst, unsigned OpIdx,
1550 MachineRegisterInfo &MRI) const;
1551
1552 /// Replace the instructions opcode with the equivalent VALU
1553 /// opcode. This function will also move the users of MachineInstruntions
1554 /// in the \p WorkList to the VALU if necessary. If present, \p MDT is
1555 /// updated.
1556 void moveToVALU(SIInstrWorklist &Worklist, MachineDominatorTree *MDT) const;
1557
1558 void
1559 moveToVALUImpl(SIInstrWorklist &Worklist, MachineDominatorTree *MDT,
1560 MachineInstr &Inst,
1561 DenseMap<MachineInstr *, V2PhysSCopyInfo> &WaterFalls,
1562 DenseMap<MachineInstr *, bool> &V2SPhyCopiesToErase) const;
1563 /// Wrapper function for generating waterfall for instruction \p MI
1564 /// This function take into consideration of related pre & succ instructions
1565 /// (e.g. calling process) into consideratioin
1566 void createWaterFallForSiCall(MachineInstr *MI, MachineDominatorTree *MDT,
1567 ArrayRef<MachineOperand *> ScalarOps,
1568 ArrayRef<Register> PhySGPRs = {}) const;
1569
1570 void insertNoop(MachineBasicBlock &MBB,
1571 MachineBasicBlock::iterator MI) const override;
1572
1573 void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1574 unsigned Quantity) const override;
1575
1576 /// Build instructions that simulate the behavior of a `s_trap 2` instructions
1577 /// for hardware (namely, gfx11) that runs in PRIV=1 mode. There, s_trap is
1578 /// interpreted as a nop.
1579 MachineBasicBlock *insertSimulatedTrap(MachineRegisterInfo &MRI,
1580 MachineBasicBlock &MBB,
1581 MachineInstr &MI,
1582 const DebugLoc &DL) const;
1583
1584 /// Return the number of wait states that result from executing this
1585 /// instruction.
1586 static unsigned getNumWaitStates(const MachineInstr &MI);
1587
1588 /// Returns the operand named \p Op. If \p MI does not have an
1589 /// operand named \c Op, this function returns nullptr.
1590 LLVM_READONLY
1591 MachineOperand *getNamedOperand(MachineInstr &MI,
1592 AMDGPU::OpName OperandName) const;
1593
1594 LLVM_READONLY
1595 const MachineOperand *getNamedOperand(const MachineInstr &MI,
1596 AMDGPU::OpName OperandName) const {
1597 return getNamedOperand(MI&: const_cast<MachineInstr &>(MI), OperandName);
1598 }
1599
1600 /// Get required immediate operand
1601 int64_t getNamedImmOperand(const MachineInstr &MI,
1602 AMDGPU::OpName OperandName) const {
1603 int Idx = AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(), Name: OperandName);
1604 return MI.getOperand(i: Idx).getImm();
1605 }
1606
1607 uint64_t getDefaultRsrcDataFormat() const;
1608 uint64_t getScratchRsrcWords23() const;
1609
1610 bool isLowLatencyInstruction(const MachineInstr &MI) const;
1611 bool isHighLatencyDef(int Opc) const override;
1612
1613 /// Return the descriptor of the target-specific machine instruction
1614 /// that corresponds to the specified pseudo or native opcode.
1615 const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
1616 return get(Opcode: pseudoToMCOpcode(Opcode));
1617 }
1618
1619 Register isStackAccess(const MachineInstr &MI, int &FrameIndex,
1620 TypeSize &MemBytes) const;
1621 Register isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex,
1622 TypeSize &MemBytes) const;
1623
1624 Register isLoadFromStackSlot(const MachineInstr &MI,
1625 int &FrameIndex) const override {
1626 TypeSize MemBytes = TypeSize::getZero();
1627 return isLoadFromStackSlot(MI, FrameIndex, MemBytes);
1628 }
1629
1630 Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
1631 TypeSize &MemBytes) const override;
1632
1633 Register isStoreToStackSlot(const MachineInstr &MI,
1634 int &FrameIndex) const override {
1635 TypeSize MemBytes = TypeSize::getZero();
1636 return isStoreToStackSlot(MI, FrameIndex, MemBytes);
1637 }
1638
1639 Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
1640 TypeSize &MemBytes) const override;
1641
1642 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1643
1644 InstSizeVerifyMode
1645 getInstSizeVerifyMode(const MachineInstr &MI) const override;
1646
1647 bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
1648
1649 std::pair<unsigned, unsigned>
1650 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
1651
1652 ArrayRef<std::pair<int, const char *>>
1653 getSerializableTargetIndices() const override;
1654
1655 ArrayRef<std::pair<unsigned, const char *>>
1656 getSerializableDirectMachineOperandTargetFlags() const override;
1657
1658 ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
1659 getSerializableMachineMemOperandTargetFlags() const override;
1660
1661 ScheduleHazardRecognizer *
1662 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
1663 const ScheduleDAG *DAG) const override;
1664
1665 ScheduleHazardRecognizer *
1666 CreateTargetPostRAHazardRecognizer(const MachineFunction &MF,
1667 MachineLoopInfo *MLI) const override;
1668
1669 ScheduleHazardRecognizer *
1670 CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
1671 const ScheduleDAGMI *DAG) const override;
1672
1673 unsigned getLiveRangeSplitOpcode(Register Reg,
1674 const MachineFunction &MF) const override;
1675
1676 bool isBasicBlockPrologue(const MachineInstr &MI,
1677 Register Reg = Register()) const override;
1678
1679 bool canAddToBBProlog(const MachineInstr &MI) const;
1680
1681 MachineInstr *createPHIDestinationCopy(MachineBasicBlock &MBB,
1682 MachineBasicBlock::iterator InsPt,
1683 const DebugLoc &DL, Register Src,
1684 Register Dst) const override;
1685
1686 MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,
1687 MachineBasicBlock::iterator InsPt,
1688 const DebugLoc &DL, Register Src,
1689 unsigned SrcSubReg,
1690 Register Dst) const override;
1691
1692 bool isWave32() const;
1693
1694 bool isVOPDAntidependencyAllowed(const MachineInstr &MI) const;
1695
1696 bool hasRAWDependency(const MachineInstr &FirstMI,
1697 const MachineInstr &SecondMI) const;
1698
1699 /// Return a partially built integer add instruction without carry.
1700 /// Caller must add source operands.
1701 /// For pre-GFX9 it will generate unused carry destination operand.
1702 /// TODO: After GFX9 it should return a no-carry operation.
1703 MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
1704 MachineBasicBlock::iterator I,
1705 const DebugLoc &DL,
1706 Register DestReg) const;
1707
1708 MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
1709 MachineBasicBlock::iterator I,
1710 const DebugLoc &DL,
1711 Register DestReg,
1712 RegScavenger &RS) const;
1713
1714 static bool isKillTerminator(unsigned Opcode);
1715 const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1716
1717 bool isLegalMUBUFImmOffset(unsigned Imm) const;
1718
1719 static unsigned getMaxMUBUFImmOffset(const GCNSubtarget &ST);
1720
1721 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
1722 Align Alignment = Align(4)) const;
1723
1724 /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
1725 /// encoded instruction with the given \p FlatVariant.
1726 bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
1727 AMDGPU::FlatAddrSpace FlatVariant) const;
1728
1729 /// Split \p COffsetVal into {immediate offset field, remainder offset}
1730 /// values.
1731 std::pair<int64_t, int64_t>
1732 splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace,
1733 AMDGPU::FlatAddrSpace FlatVariant) const;
1734
1735 /// Returns true if negative offsets are allowed for the given \p FlatVariant.
1736 bool allowNegativeFlatOffset(AMDGPU::FlatAddrSpace FlatVariant) const;
1737
1738 /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1739 /// Return -1 if the target-specific opcode for the pseudo instruction does
1740 /// not exist. If Opcode is not a pseudo instruction, this is identity.
1741 int pseudoToMCOpcode(int Opcode) const;
1742
1743 /// \brief Check if this instruction should only be used by assembler.
1744 /// Return true if this opcode should not be used by codegen.
1745 bool isAsmOnlyOpcode(int MCOp) const;
1746
1747 void fixImplicitOperands(MachineInstr &MI) const;
1748
1749 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
1750 ArrayRef<unsigned> Ops, int FrameIndex,
1751 MachineInstr *&CopyMI,
1752 LiveIntervals *LIS = nullptr,
1753 VirtRegMap *VRM = nullptr) const override;
1754
1755 unsigned getInstrLatency(const InstrItineraryData *ItinData,
1756 const MachineInstr &MI,
1757 unsigned *PredCost = nullptr) const override;
1758
1759 const MachineOperand &getCalleeOperand(const MachineInstr &MI) const override;
1760
1761 ValueUniformity getValueUniformity(const MachineInstr &MI) const final;
1762
1763 ValueUniformity getGenericValueUniformity(const MachineInstr &MI) const;
1764
1765 const MIRFormatter *getMIRFormatter() const override;
1766
1767 static unsigned getDSShaderTypeValue(const MachineFunction &MF);
1768
1769 const TargetSchedModel &getSchedModel() const { return SchedModel; }
1770
1771 void createReadFirstLaneFromCopyToPhysReg(MachineRegisterInfo &MRI,
1772 Register DstReg,
1773 MachineInstr &Inst) const;
1774
1775 void handleCopyToPhysHelper(
1776 SIInstrWorklist &Worklist, Register DstReg, MachineInstr &Inst,
1777 MachineRegisterInfo &MRI,
1778 DenseMap<MachineInstr *, V2PhysSCopyInfo> &WaterFalls,
1779 DenseMap<MachineInstr *, bool> &V2SPhyCopiesToErase) const;
1780
1781 // FIXME: This should be removed
1782 // Enforce operand's \p OpName even alignment if required by target.
1783 // This is used if an operand is a 32 bit register but needs to be aligned
1784 // regardless.
1785 void enforceOperandRCAlignment(MachineInstr &MI, AMDGPU::OpName OpName) const;
1786
1787 /// Get the repeat rate for a VALU instruction from the scheduling model.
1788 /// Returns 1 for regular VALU, >1 for long-latency VALU (packed, F64, etc.)
1789 unsigned getRepeatRate(const MachineInstr &MI) const;
1790};
1791
1792/// \brief Returns true if a reg:subreg pair P has a TRC class
1793inline bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P,
1794 const TargetRegisterClass &TRC,
1795 MachineRegisterInfo &MRI) {
1796 auto *RC = MRI.getRegClass(Reg: P.Reg);
1797 if (!P.SubReg)
1798 return RC == &TRC;
1799 auto *TRI = MRI.getTargetRegisterInfo();
1800 return RC == TRI->getMatchingSuperRegClass(A: RC, B: &TRC, Idx: P.SubReg);
1801}
1802
1803/// \brief Create RegSubRegPair from a register MachineOperand
1804inline
1805TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O) {
1806 assert(O.isReg());
1807 return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
1808}
1809
1810/// \brief Return the SubReg component from REG_SEQUENCE
1811TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI,
1812 unsigned SubReg);
1813
1814/// \brief Return the defining instruction for a given reg:subreg pair
1815/// skipping copy like instructions and subreg-manipulation pseudos.
1816/// Following another subreg of a reg:subreg isn't supported.
1817MachineInstr *getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P,
1818 const MachineRegisterInfo &MRI);
1819
1820/// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1821/// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
1822/// attempt to track between blocks.
1823bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
1824 Register VReg,
1825 const MachineInstr &DefMI,
1826 const MachineInstr &UseMI);
1827
1828/// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1829/// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
1830/// track between blocks.
1831bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
1832 Register VReg,
1833 const MachineInstr &DefMI);
1834
1835namespace AMDGPU {
1836
1837 LLVM_READONLY
1838 int32_t getVOPe64(uint32_t Opcode);
1839
1840 LLVM_READONLY
1841 int32_t getVOPe32(uint32_t Opcode);
1842
1843 LLVM_READONLY
1844 int32_t getSDWAOp(uint32_t Opcode);
1845
1846 LLVM_READONLY
1847 int32_t getDPPOp32(uint32_t Opcode);
1848
1849 LLVM_READONLY
1850 int32_t getDPPOp64(uint32_t Opcode);
1851
1852 LLVM_READONLY
1853 int32_t getBasicFromSDWAOp(uint32_t Opcode);
1854
1855 LLVM_READONLY
1856 int32_t getCommuteRev(uint32_t Opcode);
1857
1858 LLVM_READONLY
1859 int32_t getCommuteOrig(uint32_t Opcode);
1860
1861 LLVM_READONLY
1862 int32_t getAddr64Inst(uint32_t Opcode);
1863
1864 /// Check if \p Opcode is an Addr64 opcode.
1865 ///
1866 /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1867 LLVM_READONLY
1868 int32_t getIfAddr64Inst(uint32_t Opcode);
1869
1870 LLVM_READONLY
1871 int32_t getSOPKOp(uint32_t Opcode);
1872
1873 /// \returns SADDR form of a FLAT Global instruction given an \p Opcode
1874 /// of a VADDR form.
1875 LLVM_READONLY
1876 int32_t getGlobalSaddrOp(uint32_t Opcode);
1877
1878 /// \returns VADDR form of a FLAT Global instruction given an \p Opcode
1879 /// of a SADDR form.
1880 LLVM_READONLY
1881 int32_t getGlobalVaddrOp(uint32_t Opcode);
1882
1883 /// \returns ST form with only immediate offset of a FLAT Scratch instruction
1884 /// given an \p Opcode of an SS (SADDR) form.
1885 LLVM_READONLY
1886 int32_t getFlatScratchInstSTfromSS(uint32_t Opcode);
1887
1888 /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1889 /// of an SVS (SADDR + VADDR) form.
1890 LLVM_READONLY
1891 int32_t getFlatScratchInstSVfromSVS(uint32_t Opcode);
1892
1893 /// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode
1894 /// of an SV (VADDR) form.
1895 LLVM_READONLY
1896 int32_t getFlatScratchInstSSfromSV(uint32_t Opcode);
1897
1898 /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1899 /// of an SS (SADDR) form.
1900 LLVM_READONLY
1901 int32_t getFlatScratchInstSVfromSS(uint32_t Opcode);
1902
1903 /// \returns earlyclobber version of a MAC MFMA is exists.
1904 LLVM_READONLY
1905 int32_t getMFMAEarlyClobberOp(uint32_t Opcode);
1906
1907 /// \returns Version of an instruction which uses AGPRs for coupled operands
1908 /// given an \p Opcode which uses VGPRs for coupled operands.
1909 LLVM_READONLY
1910 int32_t getAGPRFormOp(uint32_t Opcode);
1911
1912 /// \returns v_cmpx version of a v_cmp instruction.
1913 LLVM_READONLY
1914 int32_t getVCMPXOpFromVCMP(uint32_t Opcode);
1915
1916 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1917 const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
1918 const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
1919 const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1920
1921} // end namespace AMDGPU
1922
1923namespace AMDGPU {
1924enum AsmComments : MachineInstr::AsmPrinterFlagTy {
1925 // For sgpr to vgpr spill instructions
1926 SGPR_SPILL = MachineInstr::TAsmComments
1927};
1928} // namespace AMDGPU
1929
1930namespace SI {
1931namespace KernelInputOffsets {
1932
1933/// Offsets in bytes from the start of the input buffer
1934enum Offsets {
1935 NGROUPS_X = 0,
1936 NGROUPS_Y = 4,
1937 NGROUPS_Z = 8,
1938 GLOBAL_SIZE_X = 12,
1939 GLOBAL_SIZE_Y = 16,
1940 GLOBAL_SIZE_Z = 20,
1941 LOCAL_SIZE_X = 24,
1942 LOCAL_SIZE_Y = 28,
1943 LOCAL_SIZE_Z = 32
1944};
1945
1946} // end namespace KernelInputOffsets
1947} // end namespace SI
1948
1949} // end namespace llvm
1950
1951#endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
1952