1//===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11
12#include "AMDGPUSubtarget.h"
13#include "SIDefines.h"
14#include "llvm/ADT/APFloat.h"
15#include "llvm/ADT/StringExtras.h"
16#include "llvm/ADT/StringTable.h"
17#include "llvm/IR/CallingConv.h"
18#include "llvm/IR/InstrTypes.h"
19#include "llvm/IR/Module.h"
20#include "llvm/Support/Alignment.h"
21#include "llvm/TargetParser/AMDGPUTargetParser.h"
22#include <array>
23#include <functional>
24#include <optional>
25#include <utility>
26
27// Pull in OpName enum definition and getNamedOperandIdx() declaration.
28#define GET_INSTRINFO_OPERAND_ENUM
29#include "AMDGPUGenInstrInfo.inc"
30
31struct amd_kernel_code_t;
32
33namespace llvm {
34
35struct Align;
36class Argument;
37class Function;
38class GlobalValue;
39class MachineInstr;
40class MCInstrInfo;
41class MCRegisterClass;
42class MCRegisterInfo;
43class MCSubtargetInfo;
44class MDNode;
45class StringRef;
46class Triple;
47class raw_ostream;
48
49namespace AMDGPU {
50
51struct AMDGPUMCKernelCodeT;
52struct IsaVersion;
53
54/// Generic target versions emitted by this version of LLVM.
55///
56/// These numbers are incremented every time a codegen breaking change occurs
57/// within a generic family.
58namespace GenericVersion {
59static constexpr unsigned GFX9 = 1;
60static constexpr unsigned GFX9_4 = 1;
61static constexpr unsigned GFX10_1 = 1;
62static constexpr unsigned GFX10_3 = 1;
63static constexpr unsigned GFX11 = 1;
64static constexpr unsigned GFX11_7 = 1;
65static constexpr unsigned GFX12 = 1;
66static constexpr unsigned GFX12_5 = 1;
67static constexpr unsigned GFX13 = 1;
68} // namespace GenericVersion
69
70enum { AMDHSA_COV4 = 4, AMDHSA_COV5 = 5, AMDHSA_COV6 = 6 };
71
72enum class FPType { None, FP4, FP8 };
73
74/// \returns True if \p STI is AMDHSA.
75bool isHsaAbi(const MCSubtargetInfo &STI);
76
77/// \returns Code object version from the IR module flag.
78unsigned getAMDHSACodeObjectVersion(const Module &M);
79
80/// \returns Code object version from ELF's e_ident[EI_ABIVERSION].
81unsigned getAMDHSACodeObjectVersion(unsigned ABIVersion);
82
83/// \returns The default HSA code object version. This should only be used when
84/// we lack a more accurate CodeObjectVersion value (e.g. from the IR module
85/// flag or a .amdhsa_code_object_version directive)
86unsigned getDefaultAMDHSACodeObjectVersion();
87
88/// \returns ABIVersion suitable for use in ELF's e_ident[EI_ABIVERSION]. \param
89/// CodeObjectVersion is a value returned by getAMDHSACodeObjectVersion().
90uint8_t getELFABIVersion(const Triple &OS, unsigned CodeObjectVersion);
91
92/// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr
93unsigned getMultigridSyncArgImplicitArgPosition(unsigned COV);
94
95/// \returns The offset of the hostcall pointer argument from implicitarg_ptr
96unsigned getHostcallImplicitArgPosition(unsigned COV);
97
98unsigned getDefaultQueueImplicitArgPosition(unsigned COV);
99unsigned getCompletionActionImplicitArgPosition(unsigned COV);
100
101struct GcnBufferFormatInfo {
102 unsigned Format;
103 unsigned BitsPerComp;
104 unsigned NumComponents;
105 unsigned NumFormat;
106 unsigned DataFormat;
107};
108
109struct MAIInstInfo {
110 uint32_t Opcode;
111 bool is_dgemm;
112 bool is_gfx940_xdl;
113};
114
115struct MFMA_F8F6F4_Info {
116 unsigned Opcode;
117 unsigned F8F8Opcode;
118 uint8_t NumRegsSrcA;
119 uint8_t NumRegsSrcB;
120};
121
122struct CvtScaleF32_F32F16ToF8F4_Info {
123 unsigned Opcode;
124};
125
126struct True16D16Info {
127 unsigned T16Op;
128 unsigned HiOp;
129 unsigned LoOp;
130};
131
132struct WMMAInstInfo {
133 uint32_t Opcode;
134 bool is_wmma_xdl;
135 bool HasMatrixScale;
136};
137
138#define GET_MIMGBaseOpcode_DECL
139#define GET_MIMGDim_DECL
140#define GET_MIMGEncoding_DECL
141#define GET_MIMGLZMapping_DECL
142#define GET_MIMGMIPMapping_DECL
143#define GET_MIMGBiASMapping_DECL
144#define GET_MAIInstInfoTable_DECL
145#define GET_isMFMA_F8F6F4Table_DECL
146#define GET_isCvtScaleF32_F32F16ToF8F4Table_DECL
147#define GET_True16D16Table_DECL
148#define GET_WMMAInstInfoTable_DECL
149#include "AMDGPUGenSearchableTables.inc"
150
151using TargetIDSetting = AMDGPU::TargetIDSetting;
152using TargetID = AMDGPU::TargetID;
153
154/// Construct TargetID from MCSubtargetInfo. \p FeatureString is used to
155/// determine explicitly requested xnack/sramecc settings.
156TargetID createAMDGPUTargetID(const MCSubtargetInfo &STI,
157 StringRef FeatureString);
158
159namespace IsaInfo {
160
161enum {
162 FIXED_NUM_SGPRS_FOR_INIT_BUG = AMDGPU::FIXED_NUM_SGPRS_FOR_INIT_BUG,
163 TRAP_NUM_SGPRS = 16
164};
165
166/// Returns true if \p Lhs and \p Rhs are incompatible (both specific but
167/// different).
168inline bool targetIDSettingsConflict(TargetIDSetting Lhs, TargetIDSetting Rhs) {
169 return Lhs != TargetIDSetting::Any && Rhs != TargetIDSetting::Any &&
170 Lhs != Rhs;
171}
172
173/// \returns Instruction cache line size in bytes for given subtarget \p STI.
174unsigned getInstCacheLineSize(const MCSubtargetInfo &STI);
175
176/// \returns Wavefront size for given subtarget \p STI.
177unsigned getWavefrontSize(const MCSubtargetInfo &STI);
178
179/// \returns Local memory size in bytes for given subtarget \p STI.
180unsigned getLocalMemorySize(const MCSubtargetInfo &STI);
181
182/// \returns Maximum addressable local memory size in bytes for given subtarget
183/// \p STI.
184unsigned getAddressableLocalMemorySize(const MCSubtargetInfo &STI);
185
186/// \returns Maximum number of work groups per compute unit for given subtarget
187/// \p STI and limited by given \p FlatWorkGroupSize.
188unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo &STI,
189 unsigned FlatWorkGroupSize);
190
191/// \returns Number of waves per execution unit required to support the given \p
192/// FlatWorkGroupSize.
193unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo &STI,
194 unsigned FlatWorkGroupSize);
195
196/// \returns Minimum flat work group size for given subtarget \p STI.
197unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo &STI);
198
199/// \returns Maximum flat work group size
200constexpr unsigned getMaxFlatWorkGroupSize() {
201 // Some subtargets allow encoding 2048, but this isn't tested or supported.
202 return 1024;
203}
204
205/// \returns Number of waves per work group for given subtarget \p STI and
206/// \p FlatWorkGroupSize.
207unsigned getWavesPerWorkGroup(const MCSubtargetInfo &STI,
208 unsigned FlatWorkGroupSize);
209
210/// \returns SGPR encoding granularity for given subtarget \p STI.
211unsigned getSGPREncodingGranule(const MCSubtargetInfo &STI);
212
213/// \returns Minimum number of SGPRs that meets the given number of waves per
214/// execution unit requirement for given subtarget \p STI.
215unsigned getMinNumSGPRs(const MCSubtargetInfo &STI, unsigned WavesPerEU);
216
217/// \returns Maximum number of SGPRs that meets the given number of waves per
218/// execution unit requirement for given subtarget \p STI.
219unsigned getMaxNumSGPRs(const MCSubtargetInfo &STI, unsigned WavesPerEU,
220 bool Addressable);
221
222/// \returns Number of extra SGPRs implicitly required by given subtarget \p
223/// STI when the given special registers are used.
224unsigned getNumExtraSGPRs(const MCSubtargetInfo &STI, bool VCCUsed,
225 bool FlatScrUsed, bool XNACKUsed);
226
227/// \returns Number of extra SGPRs implicitly required by given subtarget \p
228/// STI when the given special registers are used. XNACK is inferred from
229/// \p STI.
230unsigned getNumExtraSGPRs(const MCSubtargetInfo &STI, bool VCCUsed,
231 bool FlatScrUsed);
232
233/// \returns Number of SGPR blocks needed for given subtarget \p STI when
234/// \p NumSGPRs are used. \p NumSGPRs should already include any special
235/// register counts.
236unsigned getNumSGPRBlocks(const MCSubtargetInfo &STI, unsigned NumSGPRs);
237
238/// \returns VGPR allocation granularity for given subtarget \p STI.
239///
240/// For subtargets which support it, \p EnableWavefrontSize32 should match
241/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
242unsigned
243getVGPRAllocGranule(const MCSubtargetInfo &STI, unsigned DynamicVGPRBlockSize,
244 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
245
246/// \returns VGPR encoding granularity for given subtarget \p STI.
247///
248/// For subtargets which support it, \p EnableWavefrontSize32 should match
249/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
250unsigned getVGPREncodingGranule(
251 const MCSubtargetInfo &STI,
252 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
253
254/// For subtargets with a unified VGPR file and mixed ArchVGPR/AGPR usage,
255/// returns the allocation granule for ArchVGPRs.
256unsigned getArchVGPRAllocGranule();
257
258/// \returns Total number of VGPRs for given subtarget \p STI.
259unsigned getTotalNumVGPRs(const MCSubtargetInfo &STI);
260
261/// Maximum number of VGPR blocks that can be allocated in dynamic VGPR mode.
262static constexpr unsigned MaxDynamicVGPRBlocks = 8;
263
264/// \returns Addressable number of architectural VGPRs for a given subtarget \p
265/// STI.
266unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo &STI);
267
268/// \returns Addressable number of VGPRs for given subtarget \p STI.
269unsigned getAddressableNumVGPRs(const MCSubtargetInfo &STI,
270 unsigned DynamicVGPRBlockSize);
271
272/// \returns Minimum number of VGPRs that meets given number of waves per
273/// execution unit requirement for given subtarget \p STI.
274unsigned getMinNumVGPRs(const MCSubtargetInfo &STI, unsigned WavesPerEU,
275 unsigned DynamicVGPRBlockSize);
276
277/// \returns Maximum number of VGPRs that meets given number of waves per
278/// execution unit requirement for given subtarget \p STI.
279unsigned getMaxNumVGPRs(const MCSubtargetInfo &STI, unsigned WavesPerEU,
280 unsigned DynamicVGPRBlockSize);
281
282/// \returns Number of waves reachable for a given \p NumVGPRs usage for given
283/// subtarget \p STI.
284unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo &STI,
285 unsigned NumVGPRs,
286 unsigned DynamicVGPRBlockSize);
287
288/// \returns Number of waves reachable for a given \p NumVGPRs usage, \p Granule
289/// size, \p MaxWaves possible, and \p TotalNumVGPRs available.
290unsigned getNumWavesPerEUWithNumVGPRs(unsigned NumVGPRs, unsigned Granule,
291 unsigned MaxWaves,
292 unsigned TotalNumVGPRs);
293
294/// \returns Whether allocated SGPRs can reduce occupancy on subtarget \p STI
295/// (true pre-GFX10). One named capability so callers don't test the version.
296bool isSGPROccupancyLimited(const MCSubtargetInfo &STI);
297
298/// \returns SGPR-limited occupancy (waves per EU) for subtarget \p STI: the
299/// inverse of getMaxNumSGPRs(). Unlike getMaxNumSGPRs() the budget is not
300/// clamped to the addressable count, since the allocated count callers pass in
301/// can exceed it.
302unsigned getOccupancyWithNumSGPRs(const MCSubtargetInfo &STI, unsigned SGPRs);
303
304/// \returns SGPR-limited occupancy computed from explicit budget parameters
305/// (\p MaxWaves, \p TotalNumSGPRs, \p Granule, \p TrapReserve). Subtarget-free
306/// core shared by the overload above and the occupancy MCExpr. Callers must
307/// check isSGPROccupancyLimited() first.
308unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves,
309 unsigned TotalNumSGPRs, unsigned Granule,
310 unsigned TrapReserve);
311
312/// \returns Number of VGPR blocks needed for given subtarget \p STI when
313/// \p NumVGPRs are used. We actually return the number of blocks -1, since
314/// that's what we encode.
315///
316/// For subtargets which support it, \p EnableWavefrontSize32 should match the
317/// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
318unsigned getEncodedNumVGPRBlocks(
319 const MCSubtargetInfo &STI, unsigned NumVGPRs,
320 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
321
322/// \returns Number of VGPR blocks that need to be allocated for the given
323/// subtarget \p STI when \p NumVGPRs are used.
324unsigned getAllocatedNumVGPRBlocks(
325 const MCSubtargetInfo &STI, unsigned NumVGPRs,
326 unsigned DynamicVGPRBlockSize,
327 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
328
329} // end namespace IsaInfo
330
331// Represents a field in an encoded value.
332template <unsigned HighBit, unsigned LowBit, unsigned D = 0>
333struct EncodingField {
334 static_assert(HighBit >= LowBit, "Invalid bit range!");
335 static constexpr unsigned Offset = LowBit;
336 static constexpr unsigned Width = HighBit - LowBit + 1;
337
338 using ValueType = unsigned;
339 static constexpr ValueType Default = D;
340
341 ValueType Value;
342 constexpr EncodingField(ValueType Value) : Value(Value) {}
343
344 constexpr uint64_t encode() const { return Value; }
345 static ValueType decode(uint64_t Encoded) { return Encoded; }
346};
347
348// Represents a single bit in an encoded value.
349template <unsigned Bit, unsigned D = 0>
350using EncodingBit = EncodingField<Bit, Bit, D>;
351
352// A helper for encoding and decoding multiple fields.
353template <typename... Fields> struct EncodingFields {
354 static constexpr uint64_t encode(Fields... Values) {
355 return ((Values.encode() << Values.Offset) | ...);
356 }
357
358 static std::tuple<typename Fields::ValueType...> decode(uint64_t Encoded) {
359 return {Fields::decode((Encoded >> Fields::Offset) &
360 maxUIntN(Fields::Width))...};
361 }
362};
363
364LLVM_READONLY
365inline bool hasNamedOperand(uint64_t Opcode, OpName NamedIdx) {
366 return getNamedOperandIdx(Opcode, Name: NamedIdx) != -1;
367}
368
369LLVM_READONLY
370int32_t getSOPPWithRelaxation(uint32_t Opcode);
371
372struct MIMGBaseOpcodeInfo {
373 MIMGBaseOpcode BaseOpcode;
374 bool Store;
375 bool Atomic;
376 bool AtomicX2;
377 bool Sampler;
378 bool Gather4;
379
380 uint8_t NumExtraArgs;
381 bool Gradients;
382 bool G16;
383 bool Coordinates;
384 bool LodOrClampOrMip;
385 bool HasD16;
386 bool MSAA;
387 bool BVH;
388 bool A16;
389 bool NoReturn;
390 bool PointSampleAccel;
391};
392
393LLVM_READONLY
394const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
395
396LLVM_READONLY
397const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
398
399struct MIMGDimInfo {
400 MIMGDim Dim;
401 MIMGDim NonArrayDim;
402 uint8_t NumCoords;
403 uint8_t NumGradients;
404 bool MSAA;
405 bool DA;
406 uint8_t Encoding;
407 StringTable::Offset AsmSuffix;
408};
409
410LLVM_READONLY
411const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
412
413LLVM_READONLY StringRef getMIMGDimInfoStr(StringTable::Offset);
414
415LLVM_READONLY
416const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
417
418LLVM_READONLY
419const MIMGDimInfo *getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix);
420
421struct MIMGLZMappingInfo {
422 MIMGBaseOpcode L;
423 MIMGBaseOpcode LZ;
424};
425
426struct MIMGMIPMappingInfo {
427 MIMGBaseOpcode MIP;
428 MIMGBaseOpcode NONMIP;
429};
430
431struct MIMGBiasMappingInfo {
432 MIMGBaseOpcode Bias;
433 MIMGBaseOpcode NoBias;
434};
435
436struct MIMGOffsetMappingInfo {
437 MIMGBaseOpcode Offset;
438 MIMGBaseOpcode NoOffset;
439};
440
441struct MIMGG16MappingInfo {
442 MIMGBaseOpcode G;
443 MIMGBaseOpcode G16;
444};
445
446LLVM_READONLY
447const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
448
449struct WMMAOpcodeMappingInfo {
450 unsigned Opcode2Addr;
451 unsigned Opcode3Addr;
452};
453
454LLVM_READONLY
455const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
456
457LLVM_READONLY
458const MIMGBiasMappingInfo *getMIMGBiasMappingInfo(unsigned Bias);
459
460LLVM_READONLY
461const MIMGOffsetMappingInfo *getMIMGOffsetMappingInfo(unsigned Offset);
462
463LLVM_READONLY
464const MIMGG16MappingInfo *getMIMGG16MappingInfo(unsigned G);
465
466LLVM_READONLY
467int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
468 unsigned VDataDwords, unsigned VAddrDwords);
469
470LLVM_READONLY
471int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
472
473LLVM_READONLY
474unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
475 const MIMGDimInfo *Dim, bool IsA16,
476 bool IsG16Supported);
477
478struct MIMGInfo {
479 uint32_t Opcode;
480 uint32_t BaseOpcode;
481 uint8_t MIMGEncoding;
482 uint8_t VDataDwords;
483 uint8_t VAddrDwords;
484 uint8_t VAddrOperands;
485};
486
487LLVM_READONLY
488const MIMGInfo *getMIMGInfo(unsigned Opc);
489
490LLVM_READONLY
491int getMTBUFBaseOpcode(unsigned Opc);
492
493LLVM_READONLY
494int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
495
496LLVM_READONLY
497int getMTBUFElements(unsigned Opc);
498
499LLVM_READONLY
500bool getMTBUFHasVAddr(unsigned Opc);
501
502LLVM_READONLY
503bool getMTBUFHasSrsrc(unsigned Opc);
504
505LLVM_READONLY
506bool getMTBUFHasSoffset(unsigned Opc);
507
508LLVM_READONLY
509int getMUBUFBaseOpcode(unsigned Opc);
510
511LLVM_READONLY
512int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
513
514LLVM_READONLY
515int getMUBUFElements(unsigned Opc);
516
517LLVM_READONLY
518bool getMUBUFHasVAddr(unsigned Opc);
519
520LLVM_READONLY
521bool getMUBUFHasSrsrc(unsigned Opc);
522
523LLVM_READONLY
524bool getMUBUFHasSoffset(unsigned Opc);
525
526LLVM_READONLY
527bool getMUBUFIsBufferInv(unsigned Opc);
528
529LLVM_READONLY
530bool getMUBUFTfe(unsigned Opc);
531
532LLVM_READONLY
533bool getSMEMIsBuffer(unsigned Opc);
534
535LLVM_READONLY
536bool getVOP1IsSingle(unsigned Opc);
537
538LLVM_READONLY
539bool getVOP2IsSingle(unsigned Opc);
540
541LLVM_READONLY
542bool getVOP3IsSingle(unsigned Opc);
543
544LLVM_READONLY
545bool isVOPC64DPP(unsigned Opc);
546
547LLVM_READONLY
548bool isVOPCAsmOnly(unsigned Opc);
549
550/// Returns true if MAI operation is a double precision GEMM.
551LLVM_READONLY
552bool getMAIIsDGEMM(unsigned Opc);
553
554LLVM_READONLY
555bool getMAIIsGFX940XDL(unsigned Opc);
556
557LLVM_READONLY
558bool getWMMAIsXDL(unsigned Opc);
559
560LLVM_READONLY
561bool getHasMatrixScale(unsigned Opc);
562
563// Get an equivalent BitOp3 for a binary logical \p Opc.
564// \returns BitOp3 modifier for the logical operation or zero.
565// Used in VOPD3 conversion.
566unsigned getBitOp2(unsigned Opc);
567
568struct CanBeVOPD {
569 bool X;
570 bool Y;
571};
572
573/// \returns SIEncodingFamily used for VOPD encoding on a \p ST.
574LLVM_READONLY
575unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST);
576
577LLVM_READONLY
578CanBeVOPD getCanBeVOPD(unsigned Opc, unsigned EncodingFamily, bool VOPD3);
579
580LLVM_READNONE
581uint8_t mfmaScaleF8F6F4FormatToNumRegs(unsigned EncodingVal);
582
583LLVM_READONLY
584const MFMA_F8F6F4_Info *getMFMA_F8F6F4_WithFormatArgs(unsigned CBSZ,
585 unsigned BLGP,
586 unsigned F8F8Opcode);
587
588LLVM_READNONE
589uint8_t wmmaScaleF8F6F4FormatToNumRegs(unsigned Fmt);
590
591LLVM_READONLY
592const MFMA_F8F6F4_Info *getWMMA_F8F6F4_WithFormatArgs(unsigned FmtA,
593 unsigned FmtB,
594 unsigned F8F8Opcode);
595
596/// \return true if this combination is listed as valid.
597LLVM_READONLY
598bool isValidWMMAScaleFmtCombination(unsigned AFmt, unsigned AScale,
599 unsigned BFmt, unsigned BScale);
600
601LLVM_READONLY
602const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
603 uint8_t NumComponents,
604 uint8_t NumFormat,
605 const MCSubtargetInfo &STI);
606LLVM_READONLY
607const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
608 const MCSubtargetInfo &STI);
609
610LLVM_READONLY
611int32_t getMCOpcode(uint32_t Opcode, unsigned Gen);
612
613LLVM_READONLY
614unsigned getVOPDOpcode(unsigned Opc, bool VOPD3);
615
616LLVM_READONLY
617int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily,
618 bool VOPD3);
619
620LLVM_READONLY
621bool isVOPD(unsigned Opc);
622
623LLVM_READNONE
624bool isMAC(unsigned Opc);
625
626LLVM_READNONE
627bool isPermlane16(unsigned Opc);
628
629LLVM_READNONE
630bool isGenericAtomic(unsigned Opc);
631
632LLVM_READNONE
633bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc);
634
635namespace VOPD {
636
637enum Component : unsigned {
638 DST = 0,
639 SRC0,
640 SRC1,
641 SRC2,
642
643 DST_NUM = 1,
644 MAX_SRC_NUM = 3,
645 MAX_OPR_NUM = DST_NUM + MAX_SRC_NUM
646};
647
648// LSB mask for VGPR banks per VOPD component operand.
649// 4 banks result in a mask 3, setting 2 lower bits.
650constexpr unsigned VOPD_VGPR_BANK_MASKS[] = {1, 3, 3, 1};
651constexpr unsigned VOPD3_VGPR_BANK_MASKS[] = {1, 3, 3, 3};
652
653enum ComponentIndex : unsigned { X = 0, Y = 1 };
654constexpr unsigned COMPONENTS[] = {ComponentIndex::X, ComponentIndex::Y};
655constexpr unsigned COMPONENTS_NUM = 2;
656
657// Properties of VOPD components.
658class ComponentProps {
659private:
660 unsigned SrcOperandsNum = 0;
661 unsigned MandatoryLiteralIdx = ~0u;
662 bool HasSrc2Acc = false;
663 unsigned NumVOPD3Mods = 0;
664 unsigned Opcode = 0;
665 bool IsVOP3 = false;
666
667public:
668 ComponentProps() = default;
669 ComponentProps(const MCInstrDesc &OpDesc, bool VOP3Layout = false);
670
671 // Return the total number of src operands this component has.
672 unsigned getCompSrcOperandsNum() const { return SrcOperandsNum; }
673
674 // Return the number of src operands of this component visible to the parser.
675 unsigned getCompParsedSrcOperandsNum() const {
676 return SrcOperandsNum - HasSrc2Acc;
677 }
678
679 // Return true iif this component has a mandatory literal.
680 bool hasMandatoryLiteral() const { return MandatoryLiteralIdx != ~0u; }
681
682 // If this component has a mandatory literal, return component operand
683 // index of this literal (i.e. either Component::SRC1 or Component::SRC2).
684 unsigned getMandatoryLiteralCompOperandIndex() const {
685 assert(hasMandatoryLiteral());
686 return MandatoryLiteralIdx;
687 }
688
689 // Return true iif this component has operand
690 // with component index CompSrcIdx and this operand may be a register.
691 bool hasRegSrcOperand(unsigned CompSrcIdx) const {
692 assert(CompSrcIdx < Component::MAX_SRC_NUM);
693 return SrcOperandsNum > CompSrcIdx && !hasMandatoryLiteralAt(CompSrcIdx);
694 }
695
696 // Return true iif this component has tied src2.
697 bool hasSrc2Acc() const { return HasSrc2Acc; }
698
699 // Return a number of source modifiers if instruction is used in VOPD3.
700 unsigned getCompVOPD3ModsNum() const { return NumVOPD3Mods; }
701
702 // Return opcode of the component.
703 unsigned getOpcode() const { return Opcode; }
704
705 // Returns if component opcode is in VOP3 encoding.
706 unsigned isVOP3() const { return IsVOP3; }
707
708 // Return index of BitOp3 operand or -1.
709 int getBitOp3OperandIdx() const;
710
711private:
712 bool hasMandatoryLiteralAt(unsigned CompSrcIdx) const {
713 assert(CompSrcIdx < Component::MAX_SRC_NUM);
714 return MandatoryLiteralIdx == Component::DST_NUM + CompSrcIdx;
715 }
716};
717
718enum ComponentKind : unsigned {
719 SINGLE = 0, // A single VOP1 or VOP2 instruction which may be used in VOPD.
720 COMPONENT_X, // A VOPD instruction, X component.
721 COMPONENT_Y, // A VOPD instruction, Y component.
722 MAX = COMPONENT_Y
723};
724
725// Interface functions of this class map VOPD component operand indices
726// to indices of operands in MachineInstr/MCInst or parsed operands array.
727//
728// Note that this class operates with 3 kinds of indices:
729// - VOPD component operand indices (Component::DST, Component::SRC0, etc.);
730// - MC operand indices (they refer operands in a MachineInstr/MCInst);
731// - parsed operand indices (they refer operands in parsed operands array).
732//
733// For SINGLE components mapping between these indices is trivial.
734// But things get more complicated for COMPONENT_X and
735// COMPONENT_Y because these components share the same
736// MachineInstr/MCInst and the same parsed operands array.
737// Below is an example of component operand to parsed operand
738// mapping for the following instruction:
739//
740// v_dual_add_f32 v255, v4, v5 :: v_dual_mov_b32 v6, v1
741//
742// PARSED COMPONENT PARSED
743// COMPONENT OPERANDS OPERAND INDEX OPERAND INDEX
744// -------------------------------------------------------------------
745// "v_dual_add_f32" 0
746// v_dual_add_f32 v255 0 (DST) --> 1
747// v4 1 (SRC0) --> 2
748// v5 2 (SRC1) --> 3
749// "::" 4
750// "v_dual_mov_b32" 5
751// v_dual_mov_b32 v6 0 (DST) --> 6
752// v1 1 (SRC0) --> 7
753// -------------------------------------------------------------------
754//
755class ComponentLayout {
756private:
757 // Regular MachineInstr/MCInst operands are ordered as follows:
758 // dst, src0 [, other src operands]
759 // VOPD MachineInstr/MCInst operands are ordered as follows:
760 // dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]
761 // Each ComponentKind has operand indices defined below.
762 static constexpr unsigned MC_DST_IDX[] = {0, 0, 1};
763
764 // VOPD3 instructions may have 2 or 3 source modifiers, src2 modifier is not
765 // used if there is tied accumulator. Indexing of this array:
766 // MC_SRC_IDX[VOPD3ModsNum][SrcNo]. This returns an index for a SINGLE
767 // instruction layout, add 1 for COMPONENT_X or COMPONENT_Y. For the second
768 // component add OpX.MCSrcNum + OpX.VOPD3ModsNum.
769 // For VOPD1/VOPD2 use column with zero modifiers.
770 static constexpr unsigned SINGLE_MC_SRC_IDX[4][3] = {
771 {1, 2, 3}, {2, 3, 4}, {2, 4, 5}, {2, 4, 6}};
772
773 // Parsed operands of regular instructions are ordered as follows:
774 // Mnemo dst src0 [vsrc1 ...]
775 // Parsed VOPD operands are ordered as follows:
776 // OpXMnemo dstX src0X [vsrc1X|imm vsrc1X|vsrc1X imm] '::'
777 // OpYMnemo dstY src0Y [vsrc1Y|imm vsrc1Y|vsrc1Y imm]
778 // Each ComponentKind has operand indices defined below.
779 static constexpr unsigned PARSED_DST_IDX[] = {1, 1,
780 4 /* + OpX.ParsedSrcNum */};
781 static constexpr unsigned FIRST_PARSED_SRC_IDX[] = {
782 2, 2, 5 /* + OpX.ParsedSrcNum */};
783
784private:
785 const ComponentKind Kind;
786 const ComponentProps PrevComp;
787 const unsigned VOPD3ModsNum;
788 const int BitOp3Idx; // Index of bitop3 operand or -1
789
790public:
791 // Create layout for COMPONENT_X or SINGLE component.
792 ComponentLayout(ComponentKind Kind, unsigned VOPD3ModsNum, int BitOp3Idx)
793 : Kind(Kind), VOPD3ModsNum(VOPD3ModsNum), BitOp3Idx(BitOp3Idx) {
794 assert(Kind == ComponentKind::SINGLE || Kind == ComponentKind::COMPONENT_X);
795 }
796
797 // Create layout for COMPONENT_Y which depends on COMPONENT_X layout.
798 ComponentLayout(const ComponentProps &OpXProps, unsigned VOPD3ModsNum,
799 int BitOp3Idx)
800 : Kind(ComponentKind::COMPONENT_Y), PrevComp(OpXProps),
801 VOPD3ModsNum(VOPD3ModsNum), BitOp3Idx(BitOp3Idx) {}
802
803public:
804 // Return the index of dst operand in MCInst operands.
805 unsigned getIndexOfDstInMCOperands() const { return MC_DST_IDX[Kind]; }
806
807 // Return the index of the specified src operand in MCInst operands.
808 unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx, bool VOPD3) const {
809 assert(CompSrcIdx < Component::MAX_SRC_NUM);
810
811 if (Kind == SINGLE && CompSrcIdx == 2 && BitOp3Idx != -1)
812 return BitOp3Idx;
813
814 if (VOPD3) {
815 return SINGLE_MC_SRC_IDX[VOPD3ModsNum][CompSrcIdx] + getPrevCompSrcNum() +
816 getPrevCompVOPD3ModsNum() + (Kind != SINGLE ? 1 : 0);
817 }
818
819 return SINGLE_MC_SRC_IDX[0][CompSrcIdx] + getPrevCompSrcNum() +
820 (Kind != SINGLE ? 1 : 0);
821 }
822
823 // Return the index of dst operand in the parsed operands array.
824 unsigned getIndexOfDstInParsedOperands() const {
825 return PARSED_DST_IDX[Kind] + getPrevCompParsedSrcNum();
826 }
827
828 // Return the index of the specified src operand in the parsed operands array.
829 unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const {
830 assert(CompSrcIdx < Component::MAX_SRC_NUM);
831 return FIRST_PARSED_SRC_IDX[Kind] + getPrevCompParsedSrcNum() + CompSrcIdx;
832 }
833
834private:
835 unsigned getPrevCompSrcNum() const {
836 return PrevComp.getCompSrcOperandsNum();
837 }
838 unsigned getPrevCompParsedSrcNum() const {
839 return PrevComp.getCompParsedSrcOperandsNum();
840 }
841 unsigned getPrevCompVOPD3ModsNum() const {
842 return PrevComp.getCompVOPD3ModsNum();
843 }
844};
845
846// Layout and properties of VOPD components.
847class ComponentInfo : public ComponentProps, public ComponentLayout {
848public:
849 // Create ComponentInfo for COMPONENT_X or SINGLE component.
850 ComponentInfo(const MCInstrDesc &OpDesc,
851 ComponentKind Kind = ComponentKind::SINGLE,
852 bool VOP3Layout = false)
853 : ComponentProps(OpDesc, VOP3Layout),
854 ComponentLayout(Kind, getCompVOPD3ModsNum(), getBitOp3OperandIdx()) {}
855
856 // Create ComponentInfo for COMPONENT_Y which depends on COMPONENT_X layout.
857 ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps,
858 bool VOP3Layout = false)
859 : ComponentProps(OpDesc, VOP3Layout),
860 ComponentLayout(OpXProps, getCompVOPD3ModsNum(),
861 getBitOp3OperandIdx()) {}
862
863 // Map component operand index to parsed operand index.
864 // Return 0 if the specified operand does not exist.
865 unsigned getIndexInParsedOperands(unsigned CompOprIdx) const;
866};
867
868// Properties of VOPD instructions.
869class InstInfo {
870private:
871 const ComponentInfo CompInfo[COMPONENTS_NUM];
872
873public:
874 using RegIndices = std::array<MCRegister, Component::MAX_OPR_NUM>;
875
876 InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
877 : CompInfo{OpX, OpY} {}
878
879 InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
880 : CompInfo{OprInfoX, OprInfoY} {}
881
882 const ComponentInfo &operator[](size_t ComponentIdx) const {
883 assert(ComponentIdx < COMPONENTS_NUM);
884 return CompInfo[ComponentIdx];
885 }
886
887 // Check VOPD operands constraints.
888 // GetRegIdx(Component, MCOperandIdx) must return a VGPR register index
889 // for the specified component and MC operand. The callback must return 0
890 // if the operand is not a register or not a VGPR.
891 // If \p SkipSrc is set to true then constraints for source operands are not
892 // checked.
893 // If \p AllowSameVGPR is set then same VGPRs are allowed for X and Y sources
894 // even though it violates requirement to be from different banks.
895 // If \p VOPD3 is set to true both dst registers allowed to be either odd
896 // or even and instruction may have real src2 as opposed to tied accumulator.
897 bool
898 hasInvalidOperand(std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
899 const MCRegisterInfo &MRI, bool SkipSrc = false,
900 bool AllowSameVGPR = false, bool VOPD3 = false) const {
901 return getInvalidCompOperandIndex(GetRegIdx, MRI, SkipSrc, AllowSameVGPR,
902 VOPD3)
903 .has_value();
904 }
905
906 // Check VOPD operands constraints.
907 // Return the index of an invalid component operand, if any.
908 // If \p SkipSrc is set to true then constraints for source operands are not
909 // checked except for being from the same halves of VGPR file on gfx1250.
910 // If \p AllowSameVGPR is set then same VGPRs are allowed for X and Y sources
911 // even though it violates requirement to be from different banks.
912 // If \p VOPD3 is set to true both dst registers allowed to be either odd
913 // or even and instruction may have real src2 as opposed to tied accumulator.
914 std::optional<unsigned> getInvalidCompOperandIndex(
915 std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
916 const MCRegisterInfo &MRI, bool SkipSrc = false,
917 bool AllowSameVGPR = false, bool VOPD3 = false) const;
918
919private:
920 RegIndices
921 getRegIndices(unsigned ComponentIdx,
922 std::function<MCRegister(unsigned, unsigned)> GetRegIdx,
923 bool VOPD3) const;
924};
925
926} // namespace VOPD
927
928LLVM_READONLY
929std::pair<unsigned, unsigned> getVOPDComponents(unsigned VOPDOpcode);
930
931LLVM_READONLY
932// Get properties of 2 single VOP1/VOP2 instructions
933// used as components to create a VOPD instruction.
934VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY);
935
936LLVM_READONLY
937// Get properties of VOPD X and Y components.
938VOPD::InstInfo getVOPDInstInfo(unsigned VOPDOpcode,
939 const MCInstrInfo *InstrInfo);
940
941LLVM_READONLY
942bool isAsyncStore(unsigned Opc);
943LLVM_READONLY
944bool isTensorStore(unsigned Opc);
945LLVM_READONLY
946unsigned getTemporalHintType(const MCInstrDesc TID);
947
948LLVM_READONLY
949bool isTrue16Inst(unsigned Opc);
950
951LLVM_READONLY
952FPType getFPDstSelType(unsigned Opc);
953
954bool isDPMACCInstruction(unsigned Opc);
955
956LLVM_READONLY
957unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc);
958
959LLVM_READONLY
960unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc);
961
962void initDefaultAMDKernelCodeT(AMDGPUMCKernelCodeT &Header,
963 const MCSubtargetInfo &STI);
964
965bool isGroupSegment(const GlobalValue *GV);
966bool isGlobalSegment(const GlobalValue *GV);
967bool isReadOnlySegment(const GlobalValue *GV);
968
969/// \returns True if constants should be emitted to .text section for given
970/// target triple \p TT, false otherwise.
971bool shouldEmitConstantsToTextSection(const Triple &TT);
972
973/// Returns a valid charcode or 0 in the first entry if this is a valid physical
974/// register name. Followed by the start register number, and the register
975/// width. Does not validate the number of registers exists in the class. Unlike
976/// parseAsmConstraintPhysReg, this does not expect the name to be wrapped in
977/// "{}".
978std::tuple<char, unsigned, unsigned> parseAsmPhysRegName(StringRef TupleString);
979
980/// Returns a valid charcode or 0 in the first entry if this is a valid physical
981/// register constraint. Followed by the start register number, and the register
982/// width. Does not validate the number of registers exists in the class.
983std::tuple<char, unsigned, unsigned>
984parseAsmConstraintPhysReg(StringRef Constraint);
985
986/// \returns A pair of integer values requested using \p F's \p Name attribute
987/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
988/// is false).
989///
990/// \returns \p Default if attribute is not present.
991///
992/// \returns \p Default and emits error if one of the requested values cannot be
993/// converted to integer, or \p OnlyFirstRequired is false and "second" value is
994/// not present.
995std::pair<unsigned, unsigned>
996getIntegerPairAttribute(const Function &F, StringRef Name,
997 std::pair<unsigned, unsigned> Default,
998 bool OnlyFirstRequired = false);
999
1000/// \returns A pair of integer values requested using \p F's \p Name attribute
1001/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
1002/// is false).
1003///
1004/// \returns \p std::nullopt if attribute is not present.
1005///
1006/// \returns \p std::nullopt and emits error if one of the requested values
1007/// cannot be converted to integer, or \p OnlyFirstRequired is false and
1008/// "second" value is not present.
1009std::optional<std::pair<unsigned, std::optional<unsigned>>>
1010getIntegerPairAttribute(const Function &F, StringRef Name,
1011 bool OnlyFirstRequired = false);
1012
1013/// \returns Generate a vector of integer values requested using \p F's \p Name
1014/// attribute.
1015/// \returns A vector of size \p Size, with all elements set to \p DefaultVal,
1016/// if any error occurs. The corresponding error will also be emitted.
1017SmallVector<unsigned> getIntegerVecAttribute(const Function &F, StringRef Name,
1018 unsigned Size,
1019 unsigned DefaultVal);
1020/// Similar to the function above, but returns std::nullopt if any error occurs.
1021std::optional<SmallVector<unsigned>>
1022getIntegerVecAttribute(const Function &F, StringRef Name, unsigned Size);
1023
1024/// \returns The maximum number of workgroups for the function.
1025SmallVector<unsigned> getMaxNumWorkGroups(const Function &F);
1026
1027inline bool isTgSplitEnabled(const Function &F) {
1028 return F.hasFnAttribute(Kind: "amdgpu-tg-split");
1029}
1030
1031/// Checks if \p Val is inside \p MD, a !range-like metadata.
1032bool hasValueInRangeLikeMetadata(const MDNode &MD, int64_t Val);
1033
1034// The following methods are only meaningful on targets that support
1035// S_WAITCNT.
1036
1037/// \returns Vmcnt bit mask for given isa \p Version.
1038unsigned getVmcntBitMask(const IsaVersion &Version);
1039
1040/// \returns Expcnt bit mask for given isa \p Version.
1041unsigned getExpcntBitMask(const IsaVersion &Version);
1042
1043/// \returns Lgkmcnt bit mask for given isa \p Version.
1044unsigned getLgkmcntBitMask(const IsaVersion &Version);
1045
1046/// \returns Waitcnt bit mask for given isa \p Version.
1047unsigned getWaitcntBitMask(const IsaVersion &Version);
1048
1049/// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
1050unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
1051
1052/// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
1053unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
1054
1055/// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
1056unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
1057
1058/// \returns Decoded Loadcnt from given \p Waitcnt for given isa \p Version.
1059unsigned decodeLoadcnt(const IsaVersion &Version, unsigned Waitcnt);
1060
1061/// \returns Decoded Storecnt from given \p Waitcnt for given isa \p Version.
1062unsigned decodeStorecnt(const IsaVersion &Version, unsigned Waitcnt);
1063
1064/// \returns Decoded Dscnt from given \p Waitcnt for given isa \p Version.
1065unsigned decodeDscnt(const IsaVersion &Version, unsigned Waitcnt);
1066
1067/// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
1068/// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
1069/// \p Lgkmcnt respectively. Should not be used on gfx12+, the instruction
1070/// which needs it is deprecated
1071///
1072/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
1073/// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9)
1074/// \p Vmcnt = \p Waitcnt[15:14,3:0] (gfx9,10)
1075/// \p Vmcnt = \p Waitcnt[15:10] (gfx11)
1076/// \p Expcnt = \p Waitcnt[6:4] (pre-gfx11)
1077/// \p Expcnt = \p Waitcnt[2:0] (gfx11)
1078/// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10)
1079/// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10)
1080/// \p Lgkmcnt = \p Waitcnt[9:4] (gfx11)
1081///
1082void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt,
1083 unsigned &Expcnt, unsigned &Lgkmcnt);
1084
1085/// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
1086unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
1087 unsigned Vmcnt);
1088
1089/// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
1090unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
1091 unsigned Expcnt);
1092
1093/// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
1094unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
1095 unsigned Lgkmcnt);
1096
1097/// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
1098/// \p Version. Should not be used on gfx12+, the instruction which needs
1099/// it is deprecated
1100///
1101/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
1102/// Waitcnt[2:0] = \p Expcnt (gfx11+)
1103/// Waitcnt[3:0] = \p Vmcnt (pre-gfx9)
1104/// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9,10)
1105/// Waitcnt[6:4] = \p Expcnt (pre-gfx11)
1106/// Waitcnt[9:4] = \p Lgkmcnt (gfx11)
1107/// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10)
1108/// Waitcnt[13:8] = \p Lgkmcnt (gfx10)
1109/// Waitcnt[15:10] = \p Vmcnt (gfx11)
1110/// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9,10)
1111///
1112/// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
1113/// isa \p Version.
1114///
1115unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt,
1116 unsigned Expcnt, unsigned Lgkmcnt);
1117
1118/// \returns Waitcnt with encoded \p Loadcnt and \p Dscnt for given isa \p
1119/// Version.
1120unsigned encodeLoadcntDscnt(const IsaVersion &Version, unsigned Loadcnt,
1121 unsigned Dscnt);
1122
1123/// \returns Waitcnt with encoded \p Storecnt and \p Dscnt for given isa \p
1124/// Version.
1125unsigned encodeStorecntDscnt(const IsaVersion &Version, unsigned Storecnt,
1126 unsigned Dscnt);
1127
1128// The following methods are only meaningful on targets that support
1129// S_WAIT_*CNT, introduced with gfx12.
1130
1131/// \returns Loadcnt bit mask for given isa \p Version.
1132/// Returns 0 for versions that do not support LOADcnt
1133unsigned getLoadcntBitMask(const IsaVersion &Version);
1134
1135/// \returns Samplecnt bit mask for given isa \p Version.
1136/// Returns 0 for versions that do not support SAMPLEcnt
1137unsigned getSamplecntBitMask(const IsaVersion &Version);
1138
1139/// \returns Bvhcnt bit mask for given isa \p Version.
1140/// Returns 0 for versions that do not support BVHcnt
1141unsigned getBvhcntBitMask(const IsaVersion &Version);
1142
1143/// \returns Asynccnt bit mask for given isa \p Version.
1144/// Returns 0 for versions that do not support Asynccnt
1145unsigned getAsynccntBitMask(const IsaVersion &Version);
1146
1147/// \returns Dscnt bit mask for given isa \p Version.
1148/// Returns 0 for versions that do not support DScnt
1149unsigned getDscntBitMask(const IsaVersion &Version);
1150
1151/// \returns Dscnt bit mask for given isa \p Version.
1152/// Returns 0 for versions that do not support KMcnt
1153unsigned getKmcntBitMask(const IsaVersion &Version);
1154
1155/// \returns Xcnt bit mask for given isa \p Version.
1156/// Returns 0 for versions that do not support Xcnt.
1157unsigned getXcntBitMask(const IsaVersion &Version);
1158
1159/// \return STOREcnt or VScnt bit mask for given isa \p Version.
1160/// returns 0 for versions that do not support STOREcnt or VScnt.
1161/// STOREcnt and VScnt are the same counter, the name used
1162/// depends on the ISA version.
1163unsigned getStorecntBitMask(const IsaVersion &Version);
1164
1165namespace Hwreg {
1166
1167using HwregId = EncodingField<5, 0>;
1168using HwregOffset = EncodingField<10, 6>;
1169
1170struct HwregSize : EncodingField<15, 11, 32> {
1171 using EncodingField::EncodingField;
1172 constexpr uint64_t encode() const { return Value - 1; }
1173 static ValueType decode(uint64_t Encoded) { return Encoded + 1; }
1174};
1175
1176using HwregEncoding = EncodingFields<HwregId, HwregOffset, HwregSize>;
1177
1178} // namespace Hwreg
1179
1180namespace DepCtr {
1181
1182int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI);
1183int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
1184 const MCSubtargetInfo &STI);
1185bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
1186 const MCSubtargetInfo &STI);
1187bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
1188 bool &IsDefault, const MCSubtargetInfo &STI);
1189
1190/// \returns Maximum VaVdst value that can be encoded.
1191unsigned getVaVdstBitMask();
1192
1193/// \returns Maximum VaSdst value that can be encoded.
1194unsigned getVaSdstBitMask();
1195
1196/// \returns Maximum VaSsrc value that can be encoded.
1197unsigned getVaSsrcBitMask();
1198
1199/// \returns Maximum HoldCnt value that can be encoded.
1200unsigned getHoldCntBitMask(const IsaVersion &Version);
1201
1202/// \returns Maximum VmVsrc value that can be encoded.
1203unsigned getVmVsrcBitMask();
1204
1205/// \returns Maximum VaVcc value that can be encoded.
1206unsigned getVaVccBitMask();
1207
1208/// \returns Maximum SaSdst value that can be encoded.
1209unsigned getSaSdstBitMask();
1210
1211/// \returns Decoded VaVdst from given immediate \p Encoded.
1212unsigned decodeFieldVaVdst(unsigned Encoded);
1213
1214/// \returns Decoded VmVsrc from given immediate \p Encoded.
1215unsigned decodeFieldVmVsrc(unsigned Encoded);
1216
1217/// \returns Decoded SaSdst from given immediate \p Encoded.
1218unsigned decodeFieldSaSdst(unsigned Encoded);
1219
1220/// \returns Decoded VaSdst from given immediate \p Encoded.
1221unsigned decodeFieldVaSdst(unsigned Encoded);
1222
1223/// \returns Decoded VaVcc from given immediate \p Encoded.
1224unsigned decodeFieldVaVcc(unsigned Encoded);
1225
1226/// \returns Decoded SaSrc from given immediate \p Encoded.
1227unsigned decodeFieldVaSsrc(unsigned Encoded);
1228
1229/// \returns Decoded HoldCnt from given immediate \p Encoded.
1230unsigned decodeFieldHoldCnt(unsigned Encoded, const IsaVersion &Version);
1231
1232/// \returns \p VmVsrc as an encoded Depctr immediate.
1233unsigned encodeFieldVmVsrc(unsigned VmVsrc, const MCSubtargetInfo &STI);
1234
1235/// \returns \p Encoded combined with encoded \p VmVsrc.
1236unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc);
1237
1238/// \returns \p VaVdst as an encoded Depctr immediate.
1239unsigned encodeFieldVaVdst(unsigned VaVdst, const MCSubtargetInfo &STI);
1240
1241/// \returns \p Encoded combined with encoded \p VaVdst.
1242unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst);
1243
1244/// \returns \p SaSdst as an encoded Depctr immediate.
1245unsigned encodeFieldSaSdst(unsigned SaSdst, const MCSubtargetInfo &STI);
1246
1247/// \returns \p Encoded combined with encoded \p SaSdst.
1248unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst);
1249
1250/// \returns \p VaSdst as an encoded Depctr immediate.
1251unsigned encodeFieldVaSdst(unsigned VaSdst, const MCSubtargetInfo &STI);
1252
1253/// \returns \p Encoded combined with encoded \p VaSdst.
1254unsigned encodeFieldVaSdst(unsigned Encoded, unsigned VaSdst);
1255
1256/// \returns \p VaVcc as an encoded Depctr immediate.
1257unsigned encodeFieldVaVcc(unsigned VaVcc, const MCSubtargetInfo &STI);
1258
1259/// \returns \p Encoded combined with encoded \p VaVcc.
1260unsigned encodeFieldVaVcc(unsigned Encoded, unsigned VaVcc);
1261
1262/// \returns \p HoldCnt as an encoded Depctr immediate.
1263unsigned encodeFieldHoldCnt(unsigned HoldCnt, const MCSubtargetInfo &STI);
1264
1265/// \returns \p Encoded combined with encoded \p HoldCnt.
1266unsigned encodeFieldHoldCnt(unsigned Encoded, unsigned HoldCnt,
1267 const IsaVersion &Version);
1268
1269/// \returns \p VaSsrc as an encoded Depctr immediate.
1270unsigned encodeFieldVaSsrc(unsigned VaSsrc, const MCSubtargetInfo &STI);
1271
1272/// \returns \p Encoded combined with encoded \p VaSsrc.
1273unsigned encodeFieldVaSsrc(unsigned Encoded, unsigned VaSsrc);
1274
1275} // namespace DepCtr
1276
1277namespace Exp {
1278
1279bool getTgtName(unsigned Id, StringRef &Name, int &Index);
1280
1281LLVM_READONLY
1282unsigned getTgtId(const StringRef Name);
1283
1284LLVM_READNONE
1285bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
1286
1287} // namespace Exp
1288
1289namespace MTBUFFormat {
1290
1291LLVM_READNONE
1292int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
1293
1294void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
1295
1296int64_t getDfmt(const StringRef Name);
1297
1298StringRef getDfmtName(unsigned Id);
1299
1300int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
1301
1302StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
1303
1304bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
1305
1306bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
1307
1308int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI);
1309
1310StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI);
1311
1312bool isValidUnifiedFormat(unsigned Val, const MCSubtargetInfo &STI);
1313
1314int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
1315 const MCSubtargetInfo &STI);
1316
1317bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
1318
1319unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
1320
1321} // namespace MTBUFFormat
1322
1323namespace SendMsg {
1324
1325LLVM_READNONE
1326bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI);
1327
1328LLVM_READNONE
1329bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1330 bool Strict = true);
1331
1332LLVM_READNONE
1333bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
1334 const MCSubtargetInfo &STI, bool Strict = true);
1335
1336LLVM_READNONE
1337bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI);
1338
1339LLVM_READNONE
1340bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1341
1342void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
1343 uint16_t &StreamId, const MCSubtargetInfo &STI);
1344
1345LLVM_READNONE
1346uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId);
1347
1348/// Returns true if the message does not use the m0 operand.
1349bool msgDoesNotUseM0(int64_t MsgId, const MCSubtargetInfo &STI);
1350
1351} // namespace SendMsg
1352
1353unsigned getInitialPSInputAddr(const Function &F);
1354
1355bool getHasColorExport(const Function &F);
1356
1357bool getHasDepthExport(const Function &F);
1358
1359// Returns the value of the "amdgpu-dynamic-vgpr-block-size" attribute, or 0 if
1360// the attribute is missing or its value is invalid.
1361unsigned getDynamicVGPRBlockSize(const Function &F);
1362
1363LLVM_READNONE
1364constexpr bool isShader(CallingConv::ID CC) {
1365 switch (CC) {
1366 case CallingConv::AMDGPU_VS:
1367 case CallingConv::AMDGPU_LS:
1368 case CallingConv::AMDGPU_HS:
1369 case CallingConv::AMDGPU_ES:
1370 case CallingConv::AMDGPU_GS:
1371 case CallingConv::AMDGPU_PS:
1372 case CallingConv::AMDGPU_CS_Chain:
1373 case CallingConv::AMDGPU_CS_ChainPreserve:
1374 case CallingConv::AMDGPU_CS:
1375 return true;
1376 default:
1377 return false;
1378 }
1379}
1380
1381LLVM_READNONE
1382constexpr bool isGraphics(CallingConv::ID CC) {
1383 return isShader(CC) || CC == CallingConv::AMDGPU_Gfx ||
1384 CC == CallingConv::AMDGPU_Gfx_WholeWave;
1385}
1386
1387LLVM_READNONE
1388constexpr bool isCompute(CallingConv::ID CC) {
1389 return !isGraphics(CC) || CC == CallingConv::AMDGPU_CS;
1390}
1391
1392LLVM_READNONE
1393constexpr bool isEntryFunctionCC(CallingConv::ID CC) {
1394 switch (CC) {
1395 case CallingConv::AMDGPU_KERNEL:
1396 case CallingConv::SPIR_KERNEL:
1397 case CallingConv::AMDGPU_VS:
1398 case CallingConv::AMDGPU_GS:
1399 case CallingConv::AMDGPU_PS:
1400 case CallingConv::AMDGPU_CS:
1401 case CallingConv::AMDGPU_ES:
1402 case CallingConv::AMDGPU_HS:
1403 case CallingConv::AMDGPU_LS:
1404 return true;
1405 default:
1406 return false;
1407 }
1408}
1409
1410LLVM_READNONE
1411constexpr bool isChainCC(CallingConv::ID CC) {
1412 switch (CC) {
1413 case CallingConv::AMDGPU_CS_Chain:
1414 case CallingConv::AMDGPU_CS_ChainPreserve:
1415 return true;
1416 default:
1417 return false;
1418 }
1419}
1420
1421// These functions are considered entrypoints into the current module, i.e. they
1422// are allowed to be called from outside the current module. This is different
1423// from isEntryFunctionCC, which is only true for functions that are entered by
1424// the hardware. Module entry points include all entry functions but also
1425// include functions that can be called from other functions inside or outside
1426// the current module. Module entry functions are allowed to allocate LDS.
1427//
1428// AMDGPU_CS_Chain is intended for externally callable chain functions, so it is
1429// treated as a module entrypoint. AMDGPU_CS_ChainPreserve is used for internal
1430// helper functions (e.g. retry helpers), so it is not a module entrypoint.
1431LLVM_READNONE
1432constexpr bool isModuleEntryFunctionCC(CallingConv::ID CC) {
1433 switch (CC) {
1434 case CallingConv::AMDGPU_Gfx:
1435 case CallingConv::AMDGPU_CS_Chain:
1436 return true;
1437 default:
1438 return isEntryFunctionCC(CC);
1439 }
1440}
1441
1442LLVM_READNONE
1443constexpr inline bool isKernel(CallingConv::ID CC) {
1444 switch (CC) {
1445 case CallingConv::AMDGPU_KERNEL:
1446 case CallingConv::SPIR_KERNEL:
1447 return true;
1448 default:
1449 return false;
1450 }
1451}
1452
1453inline bool isKernel(const Function &F) { return isKernel(CC: F.getCallingConv()); }
1454
1455LLVM_READNONE
1456constexpr bool canGuaranteeTCO(CallingConv::ID CC) {
1457 return CC == CallingConv::Fast;
1458}
1459
1460/// Return true if we might ever do TCO for calls with this calling convention.
1461LLVM_READNONE
1462constexpr bool mayTailCallThisCC(CallingConv::ID CC) {
1463 switch (CC) {
1464 case CallingConv::C:
1465 case CallingConv::AMDGPU_Gfx:
1466 case CallingConv::AMDGPU_Gfx_WholeWave:
1467 return true;
1468 default:
1469 return canGuaranteeTCO(CC);
1470 }
1471}
1472
1473bool hasXNACK(const MCSubtargetInfo &STI);
1474bool hasMIMG_R128(const MCSubtargetInfo &STI);
1475bool hasA16(const MCSubtargetInfo &STI);
1476bool hasG16(const MCSubtargetInfo &STI);
1477bool hasPackedD16(const MCSubtargetInfo &STI);
1478bool hasGDS(const MCSubtargetInfo &STI);
1479unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler = false);
1480unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI);
1481
1482bool isSI(const MCSubtargetInfo &STI);
1483bool isCI(const MCSubtargetInfo &STI);
1484bool isVI(const MCSubtargetInfo &STI);
1485bool isGFX9(const MCSubtargetInfo &STI);
1486bool isGFX9_GFX10(const MCSubtargetInfo &STI);
1487bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI);
1488bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI);
1489bool isGFX8Plus(const MCSubtargetInfo &STI);
1490bool isGFX9Plus(const MCSubtargetInfo &STI);
1491bool isNotGFX9Plus(const MCSubtargetInfo &STI);
1492bool isGFX10(const MCSubtargetInfo &STI);
1493bool isGFX10_GFX11(const MCSubtargetInfo &STI);
1494bool isGFX10Plus(const MCSubtargetInfo &STI);
1495bool isNotGFX10Plus(const MCSubtargetInfo &STI);
1496bool isGFX10Before1030(const MCSubtargetInfo &STI);
1497bool isGFX11(const MCSubtargetInfo &STI);
1498bool isGFX11Plus(const MCSubtargetInfo &STI);
1499bool isGFX12(const MCSubtargetInfo &STI);
1500bool isGFX12Plus(const MCSubtargetInfo &STI);
1501bool isGFX1250(const MCSubtargetInfo &STI);
1502bool isGFX1250Plus(const MCSubtargetInfo &STI);
1503bool isGFX13(const MCSubtargetInfo &STI);
1504bool isGFX13Plus(const MCSubtargetInfo &STI);
1505
1506/// \returns true if a work-group's waves run on all four SIMD32s (one
1507/// contiguous LDS) and not just on two.
1508bool isFullSIMDMode(const MCSubtargetInfo &STI);
1509
1510bool supportsWGP(const MCSubtargetInfo &STI);
1511bool isNotGFX12Plus(const MCSubtargetInfo &STI);
1512bool isNotGFX11Plus(const MCSubtargetInfo &STI);
1513bool isGCN3Encoding(const MCSubtargetInfo &STI);
1514bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
1515bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
1516bool isGFX10_3_GFX11(const MCSubtargetInfo &STI);
1517bool isGFX90A(const MCSubtargetInfo &STI);
1518bool isGFX940(const MCSubtargetInfo &STI);
1519bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI);
1520bool hasMAIInsts(const MCSubtargetInfo &STI);
1521bool hasPopsExitingWaveID(const MCSubtargetInfo &STI);
1522
1523/// \returns true if the src_private_base and src_private_limit aperture
1524/// registers are available on \p STI. Targets with globally addressable
1525/// scratch have no private aperture and expose src_flat_scratch_base instead.
1526bool hasPrivateApertureRegs(const MCSubtargetInfo &STI);
1527
1528bool hasVOPD(const MCSubtargetInfo &STI);
1529bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI);
1530
1531int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
1532unsigned hasKernargPreload(const MCSubtargetInfo &STI);
1533bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST);
1534
1535/// Is Reg - scalar register
1536bool isSGPR(MCRegister Reg, const MCRegisterInfo *TRI);
1537
1538/// \returns if \p Reg occupies the high 16-bits of a 32-bit register.
1539bool isHi16Reg(MCRegister Reg, const MCRegisterInfo &MRI);
1540
1541/// If \p Reg is a pseudo reg, return the correct hardware register given
1542/// \p STI otherwise return \p Reg.
1543MCRegister getMCReg(MCRegister Reg, const MCSubtargetInfo &STI);
1544
1545/// Convert hardware register \p Reg to a pseudo register
1546LLVM_READNONE
1547MCRegister mc2PseudoReg(MCRegister Reg);
1548
1549LLVM_READNONE
1550bool isInlineValue(MCRegister Reg);
1551
1552/// Is this an AMDGPU specific source operand? These include registers,
1553/// inline constants, literals and mandatory literals (KImm).
1554constexpr bool isSISrcOperand(const MCOperandInfo &OpInfo) {
1555 return OpInfo.OperandType >= AMDGPU::OPERAND_SRC_FIRST &&
1556 OpInfo.OperandType <= AMDGPU::OPERAND_SRC_LAST;
1557}
1558
1559inline bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
1560 return isSISrcOperand(OpInfo: Desc.operands()[OpNo]);
1561}
1562
1563/// Is this a KImm operand?
1564bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);
1565
1566/// Is this floating-point operand?
1567bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
1568
1569/// Does this operand support only inlinable literals?
1570bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
1571
1572/// Get the size in bits of a register from the register class \p RC.
1573unsigned getRegBitWidth(unsigned RCID);
1574
1575/// Get the size in bits of a register from the register class \p RC.
1576unsigned getRegBitWidth(const MCRegisterClass &RC);
1577
1578LLVM_READNONE
1579inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
1580 switch (OpInfo.OperandType) {
1581 case AMDGPU::OPERAND_REG_IMM_INT32:
1582 case AMDGPU::OPERAND_REG_IMM_FP32:
1583 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
1584 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
1585 case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
1586 case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
1587 case AMDGPU::OPERAND_REG_IMM_V2INT32:
1588 case AMDGPU::OPERAND_REG_IMM_V2FP32:
1589 case AMDGPU::OPERAND_KIMM32:
1590 case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
1591 case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
1592 return 4;
1593
1594 case AMDGPU::OPERAND_REG_IMM_INT64:
1595 case AMDGPU::OPERAND_REG_IMM_FP64:
1596 case AMDGPU::OPERAND_REG_INLINE_C_INT64:
1597 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
1598 case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
1599 case AMDGPU::OPERAND_REG_IMM_V2FP64:
1600 case AMDGPU::OPERAND_REG_IMM_V2INT64:
1601 case AMDGPU::OPERAND_KIMM64:
1602 return 8;
1603
1604 case AMDGPU::OPERAND_REG_IMM_INT16:
1605 case AMDGPU::OPERAND_REG_IMM_BF16:
1606 case AMDGPU::OPERAND_REG_IMM_FP16:
1607 case AMDGPU::OPERAND_REG_INLINE_C_INT16:
1608 case AMDGPU::OPERAND_REG_INLINE_C_BF16:
1609 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
1610 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
1611 case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
1612 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
1613 case AMDGPU::OPERAND_REG_IMM_V2INT16:
1614 case AMDGPU::OPERAND_REG_IMM_V2BF16:
1615 case AMDGPU::OPERAND_REG_IMM_V2FP16:
1616 case AMDGPU::OPERAND_REG_IMM_V2FP16_SPLAT:
1617 case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
1618 return 2;
1619
1620 default:
1621 llvm_unreachable("unhandled operand type");
1622 }
1623}
1624
1625LLVM_READNONE
1626inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
1627 return getOperandSize(OpInfo: Desc.operands()[OpNo]);
1628}
1629
1630/// Is this literal inlinable, and not one of the values intended for floating
1631/// point values.
1632LLVM_READNONE
1633inline bool isInlinableIntLiteral(int64_t Literal) {
1634 return Literal >= -16 && Literal <= 64;
1635}
1636
1637/// Is this literal inlinable
1638LLVM_READNONE
1639bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
1640
1641LLVM_READNONE
1642bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
1643
1644LLVM_READNONE
1645bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi);
1646
1647LLVM_READNONE
1648bool isInlinableLiteralFP16(int16_t Literal, bool HasInv2Pi);
1649
1650LLVM_READNONE
1651bool isInlinableLiteralI16(int32_t Literal, bool HasInv2Pi);
1652
1653LLVM_READNONE
1654std::optional<unsigned> getInlineEncodingV2I16(uint32_t Literal);
1655
1656LLVM_READNONE
1657std::optional<unsigned> getInlineEncodingV2BF16(uint32_t Literal);
1658
1659LLVM_READNONE
1660std::optional<unsigned> getInlineEncodingV2F16(uint32_t Literal);
1661
1662LLVM_READNONE
1663std::optional<unsigned> getPKFMACF16InlineEncoding(uint32_t Literal,
1664 bool IsGFX11Plus);
1665
1666LLVM_READNONE
1667bool isInlinableLiteralV216(uint32_t Literal, uint8_t OpType);
1668
1669LLVM_READNONE
1670bool isInlinableLiteralV2I16(uint32_t Literal);
1671
1672LLVM_READNONE
1673bool isInlinableLiteralV2BF16(uint32_t Literal);
1674
1675LLVM_READNONE
1676bool isInlinableLiteralV2F16(uint32_t Literal);
1677
1678LLVM_READNONE
1679bool isPKFMACF16InlineConstant(uint32_t Literal, bool IsGFX11Plus);
1680
1681LLVM_READNONE
1682bool isValid32BitLiteral(uint64_t Val, bool IsFP64);
1683
1684LLVM_READNONE
1685int64_t encode32BitLiteral(int64_t Imm, OperandType Type, bool IsLit);
1686
1687bool isArgPassedInSGPR(const Argument *Arg);
1688
1689bool isArgPassedInSGPR(const CallBase *CB, unsigned ArgNo);
1690
1691/// The opcode is a packed fp32 instruction which only reads low 32 bits of
1692/// a scalar operand and propagates it to high channel.
1693LLVM_READONLY bool isPackedSingleSGPRFP32Inst(unsigned Opc);
1694
1695/// The opcode is a packed 64-bit instruction which only reads low 64 bits of
1696/// a scalar operand and propagates it to high channel.
1697LLVM_READONLY bool isPackedSingleSGPR64BitInst(unsigned Opc);
1698
1699/// Packed instructions that read a single SGPR for SGPR operands, except for
1700/// 64-bit elements which read two SGPRs.
1701LLVM_READONLY bool isSingleSGPRReadInst(unsigned Opc);
1702
1703LLVM_READONLY
1704bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
1705 int64_t EncodedOffset);
1706
1707LLVM_READONLY
1708bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST,
1709 int64_t EncodedOffset, bool IsBuffer);
1710
1711/// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
1712/// offsets.
1713uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
1714
1715/// \returns The encoding that will be used for \p ByteOffset in the
1716/// SMRD offset field, or std::nullopt if it won't fit. On GFX9 and GFX10
1717/// S_LOAD instructions have a signed offset, on other subtargets it is
1718/// unsigned. S_BUFFER has an unsigned offset for all subtargets.
1719std::optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
1720 int64_t ByteOffset, bool IsBuffer,
1721 bool HasSOffset = false);
1722
1723/// \return The encoding that can be used for a 32-bit literal offset in an SMRD
1724/// instruction. This is only useful on CI.s
1725std::optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
1726 int64_t ByteOffset);
1727
1728/// For pre-GFX12 FLAT instructions the offset must be positive;
1729/// MSB is ignored and forced to zero.
1730///
1731/// \return The number of bits available for the signed offset field in flat
1732/// instructions. Note that some forms of the instruction disallow negative
1733/// offsets.
1734unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST);
1735
1736LLVM_READNONE
1737inline bool isLegalDPALU_DPPControl(const MCSubtargetInfo &ST, unsigned DC) {
1738 if (isGFX12(STI: ST))
1739 return DC >= DPP::ROW_SHARE_FIRST && DC <= DPP::ROW_SHARE_LAST;
1740 if (isGFX90A(STI: ST))
1741 return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
1742 return false;
1743}
1744
1745/// \returns true if an instruction may have a 64-bit VGPR operand.
1746bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc,
1747 const MCSubtargetInfo &ST);
1748
1749/// \returns true if an instruction is a DP ALU DPP without any 64-bit operands.
1750bool isDPALU_DPP32BitOpc(unsigned Opc);
1751
1752/// \returns true if an instruction is a DP ALU DPP.
1753bool isDPALU_DPP(const MCInstrDesc &OpDesc, const MCInstrInfo &MII,
1754 const MCSubtargetInfo &ST);
1755
1756/// \returns true if the intrinsic is divergent
1757bool isIntrinsicSourceOfDivergence(unsigned IntrID);
1758
1759/// \returns true if the intrinsic is uniform
1760bool isIntrinsicAlwaysUniform(unsigned IntrID);
1761
1762/// \returns a register class for the physical register \p Reg if it is a VGPR
1763/// or nullptr otherwise.
1764const MCRegisterClass *getVGPRPhysRegClass(MCRegister Reg,
1765 const MCRegisterInfo &MRI);
1766
1767/// \returns the MODE bits which have to be set by the S_SET_VGPR_MSB for the
1768/// physical register \p Reg.
1769unsigned getVGPREncodingMSBs(MCRegister Reg, const MCRegisterInfo &MRI);
1770
1771/// If \p Reg is a low VGPR return a corresponding high VGPR with \p MSBs set.
1772MCRegister getVGPRWithMSBs(MCRegister Reg, unsigned MSBs,
1773 const MCRegisterInfo &MRI);
1774
1775/// \returns VGPR MSBs encoded in a S_SETREG_IMM32_B32 \p MI if it sets
1776/// it. If \p HasSetregVGPRMSBFixup is true then size of the ID_MODE mask is
1777/// ignored.
1778std::optional<unsigned> convertSetRegImmToVgprMSBs(const MachineInstr &MI,
1779 bool HasSetregVGPRMSBFixup);
1780
1781/// \returns VGPR MSBs encoded in a S_SETREG_IMM32_B32 \p MI if it sets
1782/// it. If \p HasSetregVGPRMSBFixup is true then size of the ID_MODE mask is
1783/// ignored.
1784std::optional<unsigned> convertSetRegImmToVgprMSBs(const MCInst &MI,
1785 bool HasSetregVGPRMSBFixup);
1786
1787// Returns a table for the opcode with a given \p Desc to map the VGPR MSB
1788// set by the S_SET_VGPR_MSB to one of 4 sources. In case of VOPD returns 2
1789// maps, one for X and one for Y component.
1790std::pair<const AMDGPU::OpName *, const AMDGPU::OpName *>
1791getVGPRLoweringOperandTables(const MCInstrDesc &Desc);
1792
1793/// \returns true if a memory instruction supports scale_offset modifier.
1794bool supportsScaleOffset(const MCInstrInfo &MII, unsigned Opcode);
1795
1796/// \returns lds block size in terms of dwords. \p
1797/// This is used to calculate the lds size encoded for PAL metadata 3.0+ which
1798/// must be defined in terms of bytes.
1799unsigned getLdsDwGranularity(const MCSubtargetInfo &ST);
1800
1801class ClusterDimsAttr {
1802public:
1803 enum class Kind { Unknown, NoCluster, VariableDims, FixedDims };
1804
1805 ClusterDimsAttr() = default;
1806
1807 Kind getKind() const { return AttrKind; }
1808
1809 bool isUnknown() const { return getKind() == Kind::Unknown; }
1810
1811 bool isNoCluster() const { return getKind() == Kind::NoCluster; }
1812
1813 bool isFixedDims() const { return getKind() == Kind::FixedDims; }
1814
1815 bool isVariableDims() const { return getKind() == Kind::VariableDims; }
1816
1817 void setUnknown() { *this = ClusterDimsAttr(Kind::Unknown); }
1818
1819 void setNoCluster() { *this = ClusterDimsAttr(Kind::NoCluster); }
1820
1821 void setVariableDims() { *this = ClusterDimsAttr(Kind::VariableDims); }
1822
1823 /// \returns the dims stored. Note that this function can only be called if
1824 /// the kind is \p Fixed.
1825 const std::array<unsigned, 3> &getDims() const;
1826
1827 bool operator==(const ClusterDimsAttr &RHS) const {
1828 return AttrKind == RHS.AttrKind && Dims == RHS.Dims;
1829 }
1830
1831 std::string to_string() const;
1832
1833 static ClusterDimsAttr get(const Function &F);
1834
1835private:
1836 enum Encoding { EncoNoCluster = 0, EncoVariableDims = 1024 };
1837
1838 ClusterDimsAttr(Kind AttrKind) : AttrKind(AttrKind) {}
1839
1840 std::array<unsigned, 3> Dims = {0, 0, 0};
1841
1842 Kind AttrKind = Kind::Unknown;
1843};
1844
1845/// Evaluate the constant-folded result of v_rcp for \p Val, accounting for
1846/// the hardware's denormal flushing on f32/f64 and its approximate rounding.
1847/// Returns std::nullopt if the hardware result is not guaranteed to match the
1848/// exact reciprocal.
1849std::optional<APFloat> evaluateRcp(const APFloat &Val);
1850
1851} // namespace AMDGPU
1852
1853raw_ostream &operator<<(raw_ostream &OS, const AMDGPU::TargetIDSetting S);
1854
1855} // end namespace llvm
1856
1857#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
1858