1//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// SI DAG Lowering interface definition
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
15#define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16
17#include "AMDGPUArgumentUsageInfo.h"
18#include "AMDGPUISelLowering.h"
19#include "SIDefines.h"
20#include "llvm/CodeGen/MachineFunction.h"
21
22namespace llvm {
23
24class GCNSubtarget;
25class SIMachineFunctionInfo;
26class SIRegisterInfo;
27
28namespace AMDGPU {
29struct ImageDimIntrinsicInfo;
30}
31
32class SITargetLowering final : public AMDGPUTargetLowering {
33private:
34 const GCNSubtarget *Subtarget;
35
36public:
37 MVT getRegisterTypeForCallingConv(LLVMContext &Context,
38 CallingConv::ID CC,
39 EVT VT) const override;
40 unsigned getNumRegistersForCallingConv(LLVMContext &Context,
41 CallingConv::ID CC,
42 EVT VT) const override;
43
44 unsigned getVectorTypeBreakdownForCallingConv(
45 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
46 unsigned &NumIntermediates, MVT &RegisterVT) const override;
47
48 MachinePointerInfo getKernargSegmentPtrInfo(MachineFunction &MF) const;
49
50private:
51 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
52 SDValue Chain, uint64_t Offset) const;
53 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
54 SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const;
55 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
56 const SDLoc &SL, SDValue Chain,
57 uint64_t Offset, Align Alignment,
58 bool Signed,
59 const ISD::InputArg *Arg = nullptr) const;
60 SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL,
61 Align Alignment,
62 ImplicitParameter Param) const;
63
64 SDValue convertABITypeToValueType(SelectionDAG &DAG, SDValue Val,
65 CCValAssign &VA, const SDLoc &SL) const;
66
67 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
68 const SDLoc &SL, SDValue Chain,
69 const ISD::InputArg &Arg) const;
70 SDValue lowerWorkGroupId(
71 SelectionDAG &DAG, const SIMachineFunctionInfo &MFI, EVT VT,
72 AMDGPUFunctionArgInfo::PreloadedValue ClusterIdPV,
73 AMDGPUFunctionArgInfo::PreloadedValue ClusterMaxIdPV,
74 AMDGPUFunctionArgInfo::PreloadedValue ClusterWorkGroupIdPV) const;
75 SDValue getPreloadedValue(SelectionDAG &DAG,
76 const SIMachineFunctionInfo &MFI,
77 EVT VT,
78 AMDGPUFunctionArgInfo::PreloadedValue) const;
79
80 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
81 SelectionDAG &DAG) const override;
82 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
83
84 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
85 MVT VT, unsigned Offset) const;
86 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr,
87 SelectionDAG &DAG, bool WithChain) const;
88 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
89 SDValue CachePolicy, SelectionDAG &DAG) const;
90
91 SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
92 unsigned NewOpcode) const;
93 SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
94 unsigned NewOpcode) const;
95
96 SDValue lowerWaveID(SelectionDAG &DAG, SDValue Op) const;
97 SDValue lowerConstHwRegRead(SelectionDAG &DAG, SDValue Op,
98 AMDGPU::Hwreg::Id HwReg, unsigned LowBit,
99 unsigned Width) const;
100 SDValue lowerWorkitemID(SelectionDAG &DAG, SDValue Op, unsigned Dim,
101 const ArgDescriptor &ArgDesc) const;
102
103 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
104 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
105 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
106
107 // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
108 // (the offset that is included in bounds checking and swizzling, to be split
109 // between the instruction's voffset and immoffset fields) and soffset (the
110 // offset that is excluded from bounds checking and swizzling, to go in the
111 // instruction's soffset field). This function takes the first kind of
112 // offset and figures out how to split it between voffset and immoffset.
113 std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
114 SelectionDAG &DAG) const;
115
116 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
117 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
118 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
119 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
120 SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const;
121 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
122 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
125 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
126 SDValue LowerFFREXP(SDValue Op, SelectionDAG &DAG) const;
127 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
129 SDValue lowerFSQRTF16(SDValue Op, SelectionDAG &DAG) const;
130 SDValue lowerFSQRTF32(SDValue Op, SelectionDAG &DAG) const;
131 SDValue lowerFSQRTF64(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
136 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
137 SelectionDAG &DAG, ArrayRef<SDValue> Ops,
138 bool IsIntrinsic = false) const;
139
140 SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG,
141 ArrayRef<SDValue> Ops) const;
142
143 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
144 // dwordx4 if on SI.
145 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
146 ArrayRef<SDValue> Ops, EVT MemVT,
147 MachineMemOperand *MMO, SelectionDAG &DAG) const;
148
149 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG,
150 bool ImageStore = false) const;
151
152 /// Converts \p Op, which must be of floating point type, to the
153 /// floating point type \p VT, by either extending or truncating it.
154 SDValue getFPExtOrFPRound(SelectionDAG &DAG,
155 SDValue Op,
156 const SDLoc &DL,
157 EVT VT) const;
158
159 SDValue convertArgType(
160 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
161 bool Signed, const ISD::InputArg *Arg = nullptr) const;
162
163 /// Custom lowering for ISD::FP_ROUND for MVT::f16.
164 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
165 SDValue splitFP_ROUNDVectorOp(SDValue Op, SelectionDAG &DAG) const;
166 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
167 SDValue lowerFMINIMUMNUM_FMAXIMUMNUM(SDValue Op, SelectionDAG &DAG) const;
168 SDValue lowerFMINIMUM_FMAXIMUM(SDValue Op, SelectionDAG &DAG) const;
169 SDValue lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const;
170 SDValue promoteUniformOpToI32(SDValue Op, DAGCombinerInfo &DCI) const;
171 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
172 SDValue lowerMUL(SDValue Op, SelectionDAG &DAG) const;
173 SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const;
174 SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
175
176 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
177 SelectionDAG &DAG) const;
178
179 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
180 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
181 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
182 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
183 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
184 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
185 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
186
187 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
188 SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const;
189 SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const;
190 SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const;
191 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
192
193 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
194
195 SDValue performUCharToFloatCombine(SDNode *N,
196 DAGCombinerInfo &DCI) const;
197 SDValue performFCopySignCombine(SDNode *N, DAGCombinerInfo &DCI) const;
198
199 SDValue performSHLPtrCombine(SDNode *N,
200 unsigned AS,
201 EVT MemVT,
202 DAGCombinerInfo &DCI) const;
203
204 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
205
206 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
207 unsigned Opc, SDValue LHS,
208 const ConstantSDNode *CRHS) const;
209
210 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
211 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
212 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
213 SDValue performZeroOrAnyExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
214 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
215 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
216 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
217 const APFloat &C) const;
218 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
219
220 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
221 SDValue Op0, SDValue Op1,
222 bool IsKnownNoNaNs) const;
223 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
224 SDValue Src, SDValue MinVal, SDValue MaxVal,
225 bool Signed) const;
226 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
227 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
228 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
229 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
230 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
231 SDValue performFPRoundCombine(SDNode *N, DAGCombinerInfo &DCI) const;
232 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
233
234 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
235 unsigned getFusedOpcode(const SelectionDAG &DAG,
236 const SDNode *N0, const SDNode *N1) const;
237 SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const;
238 SDValue foldAddSub64WithZeroLowBitsTo32(SDNode *N,
239 DAGCombinerInfo &DCI) const;
240
241 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
242 SDValue performPtrAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
243 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
244 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
245 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
246 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
247 SDValue performFDivCombine(SDNode *N, DAGCombinerInfo &DCI) const;
248 SDValue performFMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
249 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
250 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
251 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
252 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
253 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
254
255 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
256
257 unsigned isCFIntrinsic(const SDNode *Intr) const;
258
259public:
260 /// \returns True if fixup needs to be emitted for given global value \p GV,
261 /// false otherwise.
262 bool shouldEmitFixup(const GlobalValue *GV) const;
263
264 /// \returns True if GOT relocation needs to be emitted for given global value
265 /// \p GV, false otherwise.
266 bool shouldEmitGOTReloc(const GlobalValue *GV) const;
267
268 /// \returns True if PC-relative relocation needs to be emitted for given
269 /// global value \p GV, false otherwise.
270 bool shouldEmitPCReloc(const GlobalValue *GV) const;
271
272 /// \returns true if this should use a literal constant for an LDS address,
273 /// and not emit a relocation for an LDS global.
274 bool shouldUseLDSConstAddress(const GlobalValue *GV) const;
275
276 /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be
277 /// expanded into a set of cmp/select instructions.
278 static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem,
279 bool IsDivergentIdx,
280 const GCNSubtarget *Subtarget);
281
282 bool shouldExpandVectorDynExt(SDNode *N) const;
283
284 bool shouldPreservePtrArith(const Function &F, EVT PtrVT) const override;
285
286 bool canTransformPtrArithOutOfBounds(const Function &F,
287 EVT PtrVT) const override;
288
289private:
290 /// Returns true if the first real instruction in MBB is 8 bytes and could
291 /// be split by a 32-byte fetch window boundary. Used on GFX950 to avoid
292 /// instruction fetch delays.
293 bool needsFetchWindowAlignment(const MachineBasicBlock &MBB) const;
294
295 // Analyze a combined offset from an amdgcn_s_buffer_load intrinsic and store
296 // the three offsets (voffset, soffset and instoffset) into the SDValue[3]
297 // array pointed to by Offsets.
298 void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
299 SDValue *Offsets, Align Alignment = Align(4)) const;
300
301 // Convert the i128 that an addrspace(8) pointer is natively represented as
302 // into the v4i32 that all the buffer intrinsics expect to receive. We can't
303 // add register classes for i128 on pain of the promotion logic going haywire,
304 // so this slightly ugly hack is what we've got. If passed a non-pointer
305 // argument (as would be seen in older buffer intrinsics), does nothing.
306 SDValue bufferRsrcPtrToVector(SDValue MaybePointer, SelectionDAG &DAG) const;
307
308 // Wrap a 64-bit pointer into a v4i32 (which is how all SelectionDAG code
309 // represents ptr addrspace(8)) using the flags specified in the intrinsic.
310 SDValue lowerPointerAsRsrcIntrin(SDNode *Op, SelectionDAG &DAG) const;
311
312 // Handle 8 bit and 16 bit buffer loads
313 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
314 ArrayRef<SDValue> Ops,
315 MachineMemOperand *MMO,
316 bool IsTFE = false) const;
317
318 // Handle 8 bit and 16 bit buffer stores
319 SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
320 SDLoc DL, SDValue Ops[],
321 MemSDNode *M) const;
322
323public:
324 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
325
326 const GCNSubtarget *getSubtarget() const;
327
328 ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
329
330 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
331 EVT SrcVT) const override;
332
333 bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy,
334 LLT SrcTy) const override;
335
336 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
337
338 // While address space 7 should never make it to codegen, it still needs to
339 // have a MVT to prevent some analyses that query this function from breaking.
340 // We use the custum MVT::amdgpuBufferFatPointer and
341 // amdgpu::amdgpuBufferStridedPointer for this, though we use v8i32 for the
342 // memory type (which is probably unused).
343 MVT getPointerTy(const DataLayout &DL, unsigned AS) const override;
344 MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override;
345
346 void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &, const CallBase &,
347 MachineFunction &MF,
348 unsigned IntrinsicID) const override;
349
350 void CollectTargetIntrinsicOperands(const CallInst &I,
351 SmallVectorImpl<SDValue> &Ops,
352 SelectionDAG &DAG) const override;
353
354 bool getAddrModeArguments(const IntrinsicInst *I,
355 SmallVectorImpl<Value *> &Ops,
356 Type *&AccessTy) const override;
357
358 bool isLegalFlatAddressingMode(const AddrMode &AM, unsigned AddrSpace) const;
359 bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
360 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
361 unsigned AS,
362 Instruction *I = nullptr) const override;
363
364 bool canMergeStoresTo(unsigned AS, EVT MemVT,
365 const MachineFunction &MF) const override;
366
367 bool allowsMisalignedMemoryAccessesImpl(
368 unsigned Size, unsigned AddrSpace, Align Alignment,
369 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
370 unsigned *IsFast = nullptr) const;
371
372 bool allowsMisalignedMemoryAccesses(
373 LLT Ty, unsigned AddrSpace, Align Alignment,
374 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
375 unsigned *IsFast = nullptr) const override {
376 if (IsFast)
377 *IsFast = 0;
378 return allowsMisalignedMemoryAccessesImpl(Size: Ty.getSizeInBits(), AddrSpace,
379 Alignment, Flags, IsFast);
380 }
381
382 bool allowsMisalignedMemoryAccesses(
383 EVT VT, unsigned AS, Align Alignment,
384 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
385 unsigned *IsFast = nullptr) const override;
386
387 EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,
388 const AttributeList &FuncAttributes) const override;
389
390 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
391
392 static bool isNonGlobalAddrSpace(unsigned AS);
393
394 bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
395
396 TargetLoweringBase::LegalizeTypeAction
397 getPreferredVectorAction(MVT VT) const override;
398
399 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
400 Type *Ty) const override;
401
402 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
403 unsigned Index) const override;
404 bool isExtractVecEltCheap(EVT VT, unsigned Index) const override;
405
406 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
407
408 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
409
410 unsigned combineRepeatedFPDivisors() const override {
411 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
412 // reciprocal.
413 return 2;
414 }
415
416 bool supportSplitCSR(MachineFunction *MF) const override;
417 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
418 void insertCopiesSplitCSR(
419 MachineBasicBlock *Entry,
420 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
421
422 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
423 bool isVarArg,
424 const SmallVectorImpl<ISD::InputArg> &Ins,
425 const SDLoc &DL, SelectionDAG &DAG,
426 SmallVectorImpl<SDValue> &InVals) const override;
427
428 bool CanLowerReturn(CallingConv::ID CallConv,
429 MachineFunction &MF, bool isVarArg,
430 const SmallVectorImpl<ISD::OutputArg> &Outs,
431 LLVMContext &Context, const Type *RetTy) const override;
432
433 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
434 const SmallVectorImpl<ISD::OutputArg> &Outs,
435 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
436 SelectionDAG &DAG) const override;
437
438 void passSpecialInputs(
439 CallLoweringInfo &CLI,
440 CCState &CCInfo,
441 const SIMachineFunctionInfo &Info,
442 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
443 SmallVectorImpl<SDValue> &MemOpChains,
444 SDValue Chain) const;
445
446 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
447 CallingConv::ID CallConv, bool isVarArg,
448 const SmallVectorImpl<ISD::InputArg> &Ins,
449 const SDLoc &DL, SelectionDAG &DAG,
450 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
451 SDValue ThisVal) const;
452
453 bool mayBeEmittedAsTailCall(const CallInst *) const override;
454
455 bool isEligibleForTailCallOptimization(
456 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
457 const SmallVectorImpl<ISD::OutputArg> &Outs,
458 const SmallVectorImpl<SDValue> &OutVals,
459 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
460
461 SDValue LowerCall(CallLoweringInfo &CLI,
462 SmallVectorImpl<SDValue> &InVals) const override;
463
464 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
465 SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
466 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
467 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
468
469 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
470 SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
471 SDValue lowerGET_FPENV(SDValue Op, SelectionDAG &DAG) const;
472 SDValue lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) const;
473 SDValue lowerROTR(SDValue Op, SelectionDAG &DAG) const;
474
475 Register getRegisterByName(const char* RegName, LLT VT,
476 const MachineFunction &MF) const override;
477
478 MachineBasicBlock *splitKillBlock(MachineInstr &MI,
479 MachineBasicBlock *BB) const;
480
481 void bundleInstWithWaitcnt(MachineInstr &MI) const;
482 MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI,
483 MachineBasicBlock *BB) const;
484
485 MachineBasicBlock *
486 EmitInstrWithCustomInserter(MachineInstr &MI,
487 MachineBasicBlock *BB) const override;
488
489 bool enableAggressiveFMAFusion(EVT VT) const override;
490 bool enableAggressiveFMAFusion(LLT Ty) const override;
491 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
492 EVT VT) const override;
493 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
494 LLT getPreferredShiftAmountTy(LLT Ty) const override;
495
496 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
497 EVT VT) const override;
498 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
499 const LLT Ty) const override;
500 bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override;
501 bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override;
502
503 SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
504 SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
505 SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
506 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
507 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
508 SelectionDAG &DAG) const override;
509
510 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
511 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
512 void AddMemOpInit(MachineInstr &MI) const;
513 void AdjustInstrPostInstrSelection(MachineInstr &MI,
514 SDNode *Node) const override;
515
516 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
517
518 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
519 SDValue Ptr) const;
520 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
521 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
522 std::pair<unsigned, const TargetRegisterClass *>
523 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
524 StringRef Constraint, MVT VT) const override;
525 ConstraintType getConstraintType(StringRef Constraint) const override;
526 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
527 std::vector<SDValue> &Ops,
528 SelectionDAG &DAG) const override;
529 bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
530 bool checkAsmConstraintVal(SDValue Op, StringRef Constraint,
531 uint64_t Val) const;
532 bool checkAsmConstraintValA(SDValue Op,
533 uint64_t Val,
534 unsigned MaxSize = 64) const;
535 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
536 SDValue V) const;
537
538 void finalizeLowering(MachineFunction &MF) const override;
539
540 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
541 const APInt &DemandedElts,
542 const SelectionDAG &DAG,
543 unsigned Depth = 0) const override;
544 void computeKnownBitsForFrameIndex(int FrameIdx,
545 KnownBits &Known,
546 const MachineFunction &MF) const override;
547 void computeKnownBitsForTargetInstr(GISelValueTracking &Analysis, Register R,
548 KnownBits &Known,
549 const APInt &DemandedElts,
550 const MachineRegisterInfo &MRI,
551 unsigned Depth = 0) const override;
552
553 Align computeKnownAlignForTargetInstr(GISelValueTracking &Analysis,
554 Register R,
555 const MachineRegisterInfo &MRI,
556 unsigned Depth = 0) const override;
557 bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI,
558 UniformityInfo *UA) const override;
559
560 bool hasMemSDNodeUser(SDNode *N) const;
561
562 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0,
563 SDValue N1) const override;
564
565 bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0,
566 Register N1) const override;
567
568 bool isCanonicalized(SelectionDAG &DAG, SDValue Op,
569 SDNodeFlags UserFlags = {}, unsigned MaxDepth = 5) const;
570 bool isCanonicalized(Register Reg, const MachineFunction &MF,
571 unsigned MaxDepth = 5) const;
572 bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const;
573 bool denormalsEnabledForType(LLT Ty, const MachineFunction &MF) const;
574
575 bool isKnownNeverNaNForTargetNode(SDValue Op, const APInt &DemandedElts,
576 const SelectionDAG &DAG, bool SNaN = false,
577 unsigned Depth = 0) const override;
578 AtomicExpansionKind
579 shouldExpandAtomicRMWInIR(const AtomicRMWInst *) const override;
580 AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
581 AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
582 AtomicExpansionKind
583 shouldExpandAtomicCmpXchgInIR(const AtomicCmpXchgInst *AI) const override;
584
585 void emitExpandAtomicAddrSpacePredicate(Instruction *AI) const;
586 void emitExpandAtomicRMW(AtomicRMWInst *AI) const override;
587 void emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const override;
588 void emitExpandAtomicLoad(LoadInst *LI) const override;
589 void emitExpandAtomicStore(StoreInst *SI) const override;
590
591 LoadInst *
592 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
593
594 const TargetRegisterClass *getRegClassFor(MVT VT,
595 bool isDivergent) const override;
596 bool requiresUniformRegister(MachineFunction &MF,
597 const Value *V) const override;
598 Align getPrefLoopAlignment(MachineLoop *ML) const override;
599 unsigned
600 getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const override;
601
602 void allocateHSAUserSGPRs(CCState &CCInfo,
603 MachineFunction &MF,
604 const SIRegisterInfo &TRI,
605 SIMachineFunctionInfo &Info) const;
606
607 void allocatePreloadKernArgSGPRs(CCState &CCInfo,
608 SmallVectorImpl<CCValAssign> &ArgLocs,
609 const SmallVectorImpl<ISD::InputArg> &Ins,
610 MachineFunction &MF,
611 const SIRegisterInfo &TRI,
612 SIMachineFunctionInfo &Info) const;
613
614 void allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF,
615 const SIRegisterInfo &TRI,
616 SIMachineFunctionInfo &Info) const;
617
618 void allocateSystemSGPRs(CCState &CCInfo,
619 MachineFunction &MF,
620 SIMachineFunctionInfo &Info,
621 CallingConv::ID CallConv,
622 bool IsShader) const;
623
624 void allocateSpecialEntryInputVGPRs(CCState &CCInfo,
625 MachineFunction &MF,
626 const SIRegisterInfo &TRI,
627 SIMachineFunctionInfo &Info) const;
628 void allocateSpecialInputSGPRs(
629 CCState &CCInfo,
630 MachineFunction &MF,
631 const SIRegisterInfo &TRI,
632 SIMachineFunctionInfo &Info) const;
633
634 void allocateSpecialInputVGPRs(CCState &CCInfo,
635 MachineFunction &MF,
636 const SIRegisterInfo &TRI,
637 SIMachineFunctionInfo &Info) const;
638 void allocateSpecialInputVGPRsFixed(CCState &CCInfo,
639 MachineFunction &MF,
640 const SIRegisterInfo &TRI,
641 SIMachineFunctionInfo &Info) const;
642
643 MachineMemOperand::Flags
644 getTargetMMOFlags(const Instruction &I) const override;
645};
646
647// Returns true if argument is a boolean value which is not serialized into
648// memory or argument and does not require v_cndmask_b32 to be deserialized.
649bool isBoolSGPR(SDValue V);
650
651} // End namespace llvm
652
653#endif
654