1//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// SI DAG Lowering interface definition
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
15#define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16
17#include "AMDGPUArgumentUsageInfo.h"
18#include "AMDGPUISelLowering.h"
19#include "SIDefines.h"
20#include "llvm/ADT/FloatingPointMode.h"
21#include "llvm/CodeGen/MachineFunction.h"
22
23namespace llvm {
24
25class GCNSubtarget;
26class SIMachineFunctionInfo;
27class SIRegisterInfo;
28
29namespace AMDGPU {
30struct ImageDimIntrinsicInfo;
31}
32
33class SITargetLowering final : public AMDGPUTargetLowering {
34private:
35 const GCNSubtarget *Subtarget;
36
37public:
38 MVT getRegisterTypeForCallingConv(LLVMContext &Context,
39 CallingConv::ID CC,
40 EVT VT) const override;
41 unsigned getNumRegistersForCallingConv(LLVMContext &Context,
42 CallingConv::ID CC,
43 EVT VT) const override;
44
45 unsigned getVectorTypeBreakdownForCallingConv(
46 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
47 unsigned &NumIntermediates, MVT &RegisterVT) const override;
48
49 MachinePointerInfo getKernargSegmentPtrInfo(MachineFunction &MF) const;
50
51private:
52 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
53 SDValue Chain, uint64_t Offset) const;
54 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
55 SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const;
56 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
57 const SDLoc &SL, SDValue Chain,
58 uint64_t Offset, Align Alignment,
59 bool Signed,
60 const ISD::InputArg *Arg = nullptr) const;
61 SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL,
62 Align Alignment,
63 ImplicitParameter Param) const;
64
65 SDValue convertABITypeToValueType(SelectionDAG &DAG, SDValue Val,
66 CCValAssign &VA, const SDLoc &SL) const;
67
68 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
69 const SDLoc &SL, SDValue Chain,
70 const ISD::InputArg &Arg) const;
71 SDValue lowerWorkGroupId(
72 SelectionDAG &DAG, const SIMachineFunctionInfo &MFI, EVT VT,
73 AMDGPUFunctionArgInfo::PreloadedValue ClusterIdPV,
74 AMDGPUFunctionArgInfo::PreloadedValue ClusterMaxIdPV,
75 AMDGPUFunctionArgInfo::PreloadedValue ClusterWorkGroupIdPV) const;
76 SDValue getPreloadedValue(SelectionDAG &DAG,
77 const SIMachineFunctionInfo &MFI,
78 EVT VT,
79 AMDGPUFunctionArgInfo::PreloadedValue) const;
80
81 SDValue LowerGlobalAddress(AMDGPUMachineFunctionInfo *MFI, SDValue Op,
82 SelectionDAG &DAG) const override;
83 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
84
85 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
86 MVT VT, unsigned Offset) const;
87 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr,
88 SelectionDAG &DAG, bool WithChain) const;
89 SDValue lowerSBuffer(EVT VT, EVT MemVT, SDLoc DL, SDValue Chain, SDValue Rsrc,
90 SDValue Offset, SDValue CachePolicy, SelectionDAG &DAG,
91 MachineMemOperand *MMO = nullptr) const;
92
93 SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
94 unsigned NewOpcode) const;
95 SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
96 unsigned NewOpcode) const;
97
98 SDValue lowerWaveID(SelectionDAG &DAG, SDValue Op) const;
99 SDValue lowerConstHwRegRead(SelectionDAG &DAG, SDValue Op,
100 AMDGPU::Hwreg::Id HwReg, unsigned LowBit,
101 unsigned Width) const;
102 SDValue lowerWorkitemID(SelectionDAG &DAG, SDValue Op, unsigned Dim,
103 const ArgDescriptor &ArgDesc) const;
104
105 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
106 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerCONVERT_FROM_ARBITRARY_FP(SDValue Op, SelectionDAG &DAG) const;
109 SDValue lowerFromFP8(SDValue Op, bool IsBF8, SelectionDAG &DAG) const;
110 SDValue LowerCONVERT_TO_ARBITRARY_FP(SDValue Op, SelectionDAG &DAG) const;
111 SDValue lowerToFP8(SDValue Op, bool IsBF8, bool IsE5M3,
112 SelectionDAG &DAG) const;
113
114 // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
115 // (the offset that is included in bounds checking and swizzling, to be split
116 // between the instruction's voffset and immoffset fields) and soffset (the
117 // offset that is excluded from bounds checking and swizzling, to go in the
118 // instruction's soffset field). This function takes the first kind of
119 // offset and figures out how to split it between voffset and immoffset.
120 std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
121 SelectionDAG &DAG) const;
122
123 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
124 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
125 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
126 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
127 SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const;
128 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerFFREXP(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
136 SDValue lowerFSQRTF16(SDValue Op, SelectionDAG &DAG) const;
137 SDValue lowerFSQRTF32(SDValue Op, SelectionDAG &DAG) const;
138 SDValue lowerFSQRTF64(SDValue Op, SelectionDAG &DAG) const;
139 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
142 SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
143 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
144 SelectionDAG &DAG, ArrayRef<SDValue> Ops,
145 bool IsIntrinsic = false) const;
146
147 SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG,
148 ArrayRef<SDValue> Ops) const;
149
150 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
151 // dwordx4 if on SI.
152 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
153 ArrayRef<SDValue> Ops, EVT MemVT,
154 MachineMemOperand *MMO, SelectionDAG &DAG) const;
155
156 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG,
157 bool ImageStore = false) const;
158
159 /// Converts \p Op, which must be of floating point type, to the
160 /// floating point type \p VT, by either extending or truncating it.
161 SDValue getFPExtOrFPRound(SelectionDAG &DAG,
162 SDValue Op,
163 const SDLoc &DL,
164 EVT VT) const;
165
166 SDValue convertArgType(
167 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
168 bool Signed, const ISD::InputArg *Arg = nullptr) const;
169
170 /// Custom lowering for ISD::FP_ROUND for MVT::f16.
171 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
172 SDValue splitFP_ROUNDVectorOp(SDValue Op, SelectionDAG &DAG) const;
173 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
174 SDValue lowerFMINIMUMNUM_FMAXIMUMNUM(SDValue Op, SelectionDAG &DAG) const;
175 SDValue lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const;
176 SDValue promoteUniformOpToI32(SDValue Op, DAGCombinerInfo &DCI) const;
177 SDValue promoteUniformUnaryOpToI32(SDValue Op, DAGCombinerInfo &DCI) const;
178 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
179 SDValue lowerMUL(SDValue Op, SelectionDAG &DAG) const;
180 SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const;
181 SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
182
183 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
184 SelectionDAG &DAG) const;
185
186 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
187 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
188 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
189 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
190 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
191 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
192 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
193
194 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
195 SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const;
196 SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const;
197 SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const;
198 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
199 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
200
201 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
202
203 SDValue performUCharToFloatCombine(SDNode *N,
204 DAGCombinerInfo &DCI) const;
205 SDValue performFCopySignCombine(SDNode *N, DAGCombinerInfo &DCI) const;
206
207 SDValue performSHLPtrCombine(SDNode *N,
208 unsigned AS,
209 EVT MemVT,
210 DAGCombinerInfo &DCI) const;
211
212 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
213
214 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
215 unsigned Opc, SDValue LHS,
216 const ConstantSDNode *CRHS) const;
217
218 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
219 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
220 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
221 SDValue performZeroOrAnyExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
222 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
223 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
224 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
225 const APFloat &C) const;
226 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
227
228 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
229 SDValue Op0, SDValue Op1,
230 bool IsKnownNoNaNs) const;
231 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
232 SDValue Src, SDValue MinVal, SDValue MaxVal,
233 bool Signed) const;
234 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
235 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
236 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
237 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
238 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
239 SDValue performFPRoundCombine(SDNode *N, DAGCombinerInfo &DCI) const;
240 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
241
242 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
243 unsigned getFusedOpcode(const SelectionDAG &DAG,
244 const SDNode *N0, const SDNode *N1) const;
245 SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const;
246 SDValue foldAddSub64WithZeroLowBitsTo32(SDNode *N,
247 DAGCombinerInfo &DCI) const;
248
249 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
250 SDValue performPtrAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
251 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
252 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
253 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
254 SDValue performFDivCombine(SDNode *N, DAGCombinerInfo &DCI) const;
255 SDValue performFMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
256 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
257 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
258 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
259 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
260 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
261
262 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
263
264 unsigned isCFIntrinsic(const SDNode *Intr) const;
265
266public:
267 /// \returns True if fixup needs to be emitted for given global value \p GV,
268 /// false otherwise.
269 bool shouldEmitFixup(const GlobalValue *GV) const;
270
271 /// \returns True if GOT relocation needs to be emitted for given global value
272 /// \p GV, false otherwise.
273 bool shouldEmitGOTReloc(const GlobalValue *GV) const;
274
275 /// \returns True if PC-relative relocation needs to be emitted for given
276 /// global value \p GV, false otherwise.
277 bool shouldEmitPCReloc(const GlobalValue *GV) const;
278
279 /// \returns true if this should use a literal constant for an LDS address,
280 /// and not emit a relocation for an LDS global.
281 bool shouldUseLDSConstAddress(const GlobalValue *GV) const;
282
283 /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be
284 /// expanded into a set of cmp/select instructions.
285 static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem,
286 bool IsDivergentIdx,
287 const GCNSubtarget *Subtarget);
288
289 bool shouldExpandVectorDynExt(SDNode *N) const;
290
291 bool shouldPreservePtrArith(const Function &F, EVT PtrVT) const override;
292
293 bool canTransformPtrArithOutOfBounds(const Function &F,
294 EVT PtrVT) const override;
295
296private:
297 /// Returns true if the first real instruction in MBB is 8 bytes and could
298 /// be split by a 32-byte fetch window boundary. Used on GFX950 to avoid
299 /// instruction fetch delays.
300 bool needsFetchWindowAlignment(const MachineBasicBlock &MBB) const;
301
302 // Analyze a combined offset from an amdgcn_s_buffer_load intrinsic and store
303 // the three offsets (voffset, soffset and instoffset) into the SDValue[3]
304 // array pointed to by Offsets.
305 void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
306 SDValue *Offsets, Align Alignment = Align(4)) const;
307
308 // Convert the i128 that an addrspace(8) pointer is natively represented as
309 // into the v4i32 that all the buffer intrinsics expect to receive. We can't
310 // add register classes for i128 on pain of the promotion logic going haywire,
311 // so this slightly ugly hack is what we've got. If passed a non-pointer
312 // argument (as would be seen in older buffer intrinsics), does nothing.
313 SDValue bufferRsrcPtrToVector(SDValue MaybePointer, SelectionDAG &DAG) const;
314
315 // Wrap a 64-bit pointer into a v4i32 (which is how all SelectionDAG code
316 // represents ptr addrspace(8)) using the flags specified in the intrinsic.
317 SDValue lowerPointerAsRsrcIntrin(SDNode *Op, SelectionDAG &DAG) const;
318
319 // Handle 8 bit and 16 bit buffer loads
320 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
321 ArrayRef<SDValue> Ops,
322 MachineMemOperand *MMO,
323 bool IsTFE = false) const;
324
325 // Handle 8 bit and 16 bit buffer stores
326 SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
327 SDLoc DL, SDValue Ops[],
328 MemSDNode *M) const;
329
330public:
331 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
332
333 const GCNSubtarget *getSubtarget() const;
334
335 ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
336
337 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
338 EVT SrcVT) const override;
339
340 bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy,
341 LLT SrcTy) const override;
342
343 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
344
345 // While address space 7 should never make it to codegen, it still needs to
346 // have a MVT to prevent some analyses that query this function from breaking.
347 // We use the custum MVT::amdgpuBufferFatPointer and
348 // amdgpu::amdgpuBufferStridedPointer for this, though we use v8i32 for the
349 // memory type (which is probably unused).
350 MVT getPointerTy(const DataLayout &DL, unsigned AS) const override;
351 MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override;
352
353 void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &, const CallBase &,
354 MachineFunction &MF,
355 unsigned IntrinsicID) const override;
356
357 void CollectTargetIntrinsicOperands(const CallInst &I,
358 SmallVectorImpl<SDValue> &Ops,
359 SelectionDAG &DAG) const override;
360
361 bool getAddrModeArguments(const IntrinsicInst *I,
362 SmallVectorImpl<Value *> &Ops,
363 Type *&AccessTy) const override;
364
365 bool isLegalFlatAddressingMode(const AddrMode &AM, unsigned AddrSpace) const;
366 bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
367 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
368 unsigned AS,
369 Instruction *I = nullptr) const override;
370
371 bool canMergeStoresTo(unsigned AS, EVT MemVT,
372 const MachineFunction &MF) const override;
373
374 bool allowsMisalignedMemoryAccessesImpl(
375 unsigned Size, unsigned AddrSpace, Align Alignment,
376 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
377 unsigned *IsFast = nullptr) const;
378
379 bool allowsMisalignedMemoryAccesses(
380 LLT Ty, unsigned AddrSpace, Align Alignment,
381 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
382 unsigned *IsFast = nullptr) const override {
383 if (IsFast)
384 *IsFast = 0;
385 return allowsMisalignedMemoryAccessesImpl(Size: Ty.getSizeInBits(), AddrSpace,
386 Alignment, Flags, IsFast);
387 }
388
389 bool allowsMisalignedMemoryAccesses(
390 EVT VT, unsigned AS, Align Alignment,
391 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
392 unsigned *IsFast = nullptr) const override;
393
394 EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,
395 const AttributeList &FuncAttributes) const override;
396
397 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
398
399 static bool isNonGlobalAddrSpace(unsigned AS);
400
401 bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
402
403 TargetLoweringBase::LegalizeTypeAction
404 getPreferredVectorAction(MVT VT) const override;
405
406 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
407 Type *Ty) const override;
408
409 ExtractSubvectorCost getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
410 unsigned Index) const override;
411 bool isExtractVecEltCheap(EVT VT, unsigned Index) const override;
412
413 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
414
415 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
416
417 unsigned combineRepeatedFPDivisors() const override {
418 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
419 // reciprocal.
420 return 2;
421 }
422
423 bool supportSplitCSR(MachineFunction *MF) const override;
424 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
425 void insertCopiesSplitCSR(
426 MachineBasicBlock *Entry,
427 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
428
429 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
430 bool isVarArg,
431 const SmallVectorImpl<ISD::InputArg> &Ins,
432 const SDLoc &DL, SelectionDAG &DAG,
433 SmallVectorImpl<SDValue> &InVals) const override;
434
435 bool CanLowerReturn(CallingConv::ID CallConv,
436 MachineFunction &MF, bool isVarArg,
437 const SmallVectorImpl<ISD::OutputArg> &Outs,
438 LLVMContext &Context, const Type *RetTy) const override;
439
440 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
441 const SmallVectorImpl<ISD::OutputArg> &Outs,
442 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
443 SelectionDAG &DAG) const override;
444
445 void passSpecialInputs(
446 CallLoweringInfo &CLI,
447 CCState &CCInfo,
448 const SIMachineFunctionInfo &Info,
449 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
450 SmallVectorImpl<SDValue> &MemOpChains,
451 SDValue Chain) const;
452
453 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
454 CallingConv::ID CallConv, bool isVarArg,
455 const SmallVectorImpl<ISD::InputArg> &Ins,
456 const SDLoc &DL, SelectionDAG &DAG,
457 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
458 SDValue ThisVal) const;
459
460 bool mayBeEmittedAsTailCall(const CallInst *) const override;
461
462 bool isEligibleForTailCallOptimization(
463 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
464 const SmallVectorImpl<ISD::OutputArg> &Outs,
465 const SmallVectorImpl<SDValue> &OutVals,
466 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
467
468 SDValue LowerCall(CallLoweringInfo &CLI,
469 SmallVectorImpl<SDValue> &InVals) const override;
470
471 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
472 SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
473 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
474 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
475
476 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
477 SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
478 SDValue lowerGET_FPENV(SDValue Op, SelectionDAG &DAG) const;
479 SDValue lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) const;
480 SDValue lowerROTR(SDValue Op, SelectionDAG &DAG) const;
481
482 Register getRegisterByName(const char* RegName, LLT VT,
483 const MachineFunction &MF) const override;
484
485 MachineBasicBlock *splitKillBlock(MachineInstr &MI,
486 MachineBasicBlock *BB) const;
487
488 void bundleInstWithWaitcnt(MachineInstr &MI) const;
489 MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI,
490 MachineBasicBlock *BB) const;
491
492 MachineBasicBlock *
493 EmitInstrWithCustomInserter(MachineInstr &MI,
494 MachineBasicBlock *BB) const override;
495
496 bool enableAggressiveFMAFusion(EVT VT) const override;
497 bool enableAggressiveFMAFusion(LLT Ty) const override;
498 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
499 EVT VT) const override;
500 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
501 LLT getPreferredShiftAmountTy(LLT Ty) const override;
502
503 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
504 EVT VT) const override;
505 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
506 const LLT Ty) const override;
507 bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override;
508 bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override;
509
510 /// Variants for IR level callers, which have no MachineFunction to read the
511 /// denormal mode from and must pass \p FPEnv explicitly.
512 bool isFMAFasterThanFMulAndFAdd(EVT VT, DenormalFPEnv FPEnv) const;
513
514 /// \p VT is used as written, so a vector type reports false.
515 bool isFMADLegal(EVT VT, DenormalFPEnv FPEnv) const;
516
517 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
518
519 SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
520 SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
521 SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
522 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
523 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
524 SelectionDAG &DAG) const override;
525
526 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
527 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
528 void AddMemOpInit(MachineInstr &MI) const;
529 void AdjustInstrPostInstrSelection(MachineInstr &MI,
530 SDNode *Node) const override;
531
532 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
533
534 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
535 SDValue Ptr) const;
536 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
537 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
538 std::pair<unsigned, const TargetRegisterClass *>
539 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
540 StringRef Constraint, MVT VT) const override;
541 ConstraintType getConstraintType(StringRef Constraint) const override;
542 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
543 std::vector<SDValue> &Ops,
544 SelectionDAG &DAG) const override;
545 bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
546 bool checkAsmConstraintVal(SDValue Op, StringRef Constraint,
547 uint64_t Val) const;
548 bool checkAsmConstraintValA(SDValue Op,
549 uint64_t Val,
550 unsigned MaxSize = 64) const;
551 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
552 SDValue V) const;
553
554 void finalizeLowering(MachineFunction &MF) const override;
555
556 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
557 const APInt &DemandedElts,
558 const SelectionDAG &DAG,
559 unsigned Depth = 0) const override;
560 void computeKnownBitsForStackObjectPointer(KnownBits &Known,
561 const MachineFunction &MF,
562 Align Alignment) const override;
563 void computeKnownBitsForTargetInstr(GISelValueTracking &Analysis, Register R,
564 KnownBits &Known,
565 const APInt &DemandedElts,
566 const MachineRegisterInfo &MRI,
567 unsigned Depth = 0) const override;
568
569 Align computeKnownAlignForTargetInstr(GISelValueTracking &Analysis,
570 Register R,
571 const MachineRegisterInfo &MRI,
572 unsigned Depth = 0) const override;
573 bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI,
574 UniformityInfo *UA) const override;
575
576 bool hasMemSDNodeUser(SDNode *N) const;
577
578 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0,
579 SDValue N1) const override;
580
581 bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0,
582 Register N1) const override;
583
584 bool isCanonicalized(SelectionDAG &DAG, SDValue Op,
585 SDNodeFlags UserFlags = {}, unsigned MaxDepth = 5) const;
586
587 /// Returns true if \p Op is provably canonical (no FCANONICALIZE needed).
588 /// \p QueryVT is the scalar FP type being checked, threaded unchanged
589 /// through recursion since canonicality is per vector element. FP operands
590 /// whose scalar type differs from \p QueryVT are treated as non-canonical,
591 /// since canonicality does not survive a change of FP format (e.g. bitcast
592 /// v2bf16 to v2f16); non-FP operands are not checked against \p QueryVT.
593 bool isCanonicalized(SelectionDAG &DAG, SDValue Op, EVT QueryVT,
594 SDNodeFlags UserFlags, unsigned MaxDepth) const;
595 bool isCanonicalized(Register Reg, const MachineFunction &MF,
596 unsigned MaxDepth = 5) const;
597 bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const;
598 bool denormalsEnabledForType(LLT Ty, const MachineFunction &MF) const;
599
600 bool isKnownNeverNaNForTargetNode(SDValue Op, const APInt &DemandedElts,
601 const SelectionDAG &DAG, bool SNaN = false,
602 unsigned Depth = 0) const override;
603 AtomicExpansionKind
604 shouldExpandAtomicRMWInIR(const AtomicRMWInst *) const override;
605 AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
606 AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
607 AtomicExpansionKind
608 shouldExpandAtomicCmpXchgInIR(const AtomicCmpXchgInst *AI) const override;
609
610 void emitExpandAtomicAddrSpacePredicate(Instruction *AI) const;
611 void emitExpandAtomicRMW(AtomicRMWInst *AI) const override;
612 void emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const override;
613 void emitExpandAtomicLoad(LoadInst *LI) const override;
614 void emitExpandAtomicStore(StoreInst *SI) const override;
615
616 LoadInst *
617 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
618
619 const TargetRegisterClass *getRegClassFor(MVT VT,
620 bool isDivergent) const override;
621 bool requiresUniformRegister(MachineFunction &MF,
622 const Value *V) const override;
623 Align getPrefLoopAlignment(MachineLoop *ML) const override;
624 unsigned
625 getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const override;
626
627 void allocateHSAUserSGPRs(CCState &CCInfo,
628 MachineFunction &MF,
629 const SIRegisterInfo &TRI,
630 SIMachineFunctionInfo &Info) const;
631
632 void allocatePreloadKernArgSGPRs(CCState &CCInfo,
633 SmallVectorImpl<CCValAssign> &ArgLocs,
634 const SmallVectorImpl<ISD::InputArg> &Ins,
635 MachineFunction &MF,
636 const SIRegisterInfo &TRI,
637 SIMachineFunctionInfo &Info) const;
638
639 void allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF,
640 const SIRegisterInfo &TRI,
641 SIMachineFunctionInfo &Info) const;
642
643 void allocateSystemSGPRs(CCState &CCInfo,
644 MachineFunction &MF,
645 SIMachineFunctionInfo &Info,
646 CallingConv::ID CallConv,
647 bool IsShader) const;
648
649 void allocateSpecialEntryInputVGPRs(CCState &CCInfo,
650 MachineFunction &MF,
651 const SIRegisterInfo &TRI,
652 SIMachineFunctionInfo &Info) const;
653 void allocateSpecialInputSGPRs(
654 CCState &CCInfo,
655 MachineFunction &MF,
656 const SIRegisterInfo &TRI,
657 SIMachineFunctionInfo &Info) const;
658
659 void allocateSpecialInputVGPRs(CCState &CCInfo,
660 MachineFunction &MF,
661 const SIRegisterInfo &TRI,
662 SIMachineFunctionInfo &Info) const;
663 void allocateSpecialInputVGPRsFixed(CCState &CCInfo,
664 MachineFunction &MF,
665 const SIRegisterInfo &TRI,
666 SIMachineFunctionInfo &Info) const;
667
668 MachineMemOperand::Flags
669 getTargetMMOFlags(const Instruction &I) const override;
670};
671
672// Returns true if argument is a boolean value which is not serialized into
673// memory or argument and does not require v_cndmask_b32 to be deserialized.
674bool isBoolSGPR(SDValue V);
675
676} // End namespace llvm
677
678#endif
679