1//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// SI DAG Lowering interface definition
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
15#define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16
17#include "AMDGPUArgumentUsageInfo.h"
18#include "AMDGPUISelLowering.h"
19#include "SIDefines.h"
20#include "llvm/ADT/FloatingPointMode.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include <bitset>
23
24namespace llvm {
25
26class GCNSubtarget;
27class SIMachineFunctionInfo;
28class SIRegisterInfo;
29
30namespace AMDGPU {
31struct ImageDimIntrinsicInfo;
32}
33
34class SITargetLowering final : public AMDGPUTargetLowering {
35private:
36 const GCNSubtarget *Subtarget;
37
38 /// Result types made Custom for ISD::INTRINSIC_W_CHAIN only so that
39 /// unsupported s_buffer_load result types can be diagnosed. Any other
40 /// intrinsic returning one of these must keep using generic legalization.
41 std::bitset<MVT::VALUETYPE_SIZE> SBufferLoadDiagnosticVTs;
42
43public:
44 MVT getRegisterTypeForCallingConv(LLVMContext &Context,
45 CallingConv::ID CC,
46 EVT VT) const override;
47 unsigned getNumRegistersForCallingConv(LLVMContext &Context,
48 CallingConv::ID CC,
49 EVT VT) const override;
50
51 unsigned getVectorTypeBreakdownForCallingConv(
52 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
53 unsigned &NumIntermediates, MVT &RegisterVT) const override;
54
55 MachinePointerInfo getKernargSegmentPtrInfo(MachineFunction &MF) const;
56
57private:
58 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
59 SDValue Chain, uint64_t Offset) const;
60 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
61 SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const;
62 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
63 const SDLoc &SL, SDValue Chain,
64 uint64_t Offset, Align Alignment,
65 bool Signed,
66 const ISD::InputArg *Arg = nullptr) const;
67 SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL,
68 Align Alignment,
69 ImplicitParameter Param) const;
70
71 SDValue convertABITypeToValueType(SelectionDAG &DAG, SDValue Val,
72 CCValAssign &VA, const SDLoc &SL) const;
73
74 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
75 const SDLoc &SL, SDValue Chain,
76 const ISD::InputArg &Arg) const;
77 SDValue lowerWorkGroupId(
78 SelectionDAG &DAG, const SIMachineFunctionInfo &MFI, EVT VT,
79 AMDGPUFunctionArgInfo::PreloadedValue ClusterIdPV,
80 AMDGPUFunctionArgInfo::PreloadedValue ClusterMaxIdPV,
81 AMDGPUFunctionArgInfo::PreloadedValue ClusterWorkGroupIdPV) const;
82 SDValue getPreloadedValue(SelectionDAG &DAG,
83 const SIMachineFunctionInfo &MFI,
84 EVT VT,
85 AMDGPUFunctionArgInfo::PreloadedValue) const;
86
87 SDValue LowerGlobalAddress(AMDGPUMachineFunctionInfo *MFI, SDValue Op,
88 SelectionDAG &DAG) const override;
89 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
90
91 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
92 MVT VT, unsigned Offset) const;
93 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr,
94 SelectionDAG &DAG, bool WithChain) const;
95 SDValue lowerSBuffer(EVT VT, EVT MemVT, SDLoc DL, SDValue Chain, SDValue Rsrc,
96 SDValue Offset, SDValue CachePolicy, SelectionDAG &DAG,
97 MachineMemOperand *MMO = nullptr) const;
98
99 SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
100 unsigned NewOpcode) const;
101 SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
102 unsigned NewOpcode) const;
103
104 SDValue lowerWaveID(SelectionDAG &DAG, SDValue Op) const;
105 SDValue lowerConstHwRegRead(SelectionDAG &DAG, SDValue Op,
106 AMDGPU::Hwreg::Id HwReg, unsigned LowBit,
107 unsigned Width) const;
108 SDValue lowerWorkitemID(SelectionDAG &DAG, SDValue Op, unsigned Dim,
109 const ArgDescriptor &ArgDesc) const;
110
111 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
112 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
113 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
114 SDValue LowerCONVERT_FROM_ARBITRARY_FP(SDValue Op, SelectionDAG &DAG) const;
115 SDValue lowerFromFP8(SDValue Op, bool IsBF8, SelectionDAG &DAG) const;
116 SDValue LowerCONVERT_TO_ARBITRARY_FP(SDValue Op, SelectionDAG &DAG) const;
117 SDValue lowerToFP8(SDValue Op, bool IsBF8, bool IsE5M3,
118 SelectionDAG &DAG) const;
119
120 // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
121 // (the offset that is included in bounds checking and swizzling, to be split
122 // between the instruction's voffset and immoffset fields) and soffset (the
123 // offset that is excluded from bounds checking and swizzling, to go in the
124 // instruction's soffset field). This function takes the first kind of
125 // offset and figures out how to split it between voffset and immoffset.
126 std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
127 SelectionDAG &DAG) const;
128
129 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
130 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
132 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
133 SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const;
134 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
136 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
137 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
139 SDValue LowerFFREXP(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
142 SDValue lowerFSQRTF16(SDValue Op, SelectionDAG &DAG) const;
143 SDValue lowerFSQRTF32(SDValue Op, SelectionDAG &DAG) const;
144 SDValue lowerFSQRTF64(SDValue Op, SelectionDAG &DAG) const;
145 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
146 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
147 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
148 SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
149 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, SelectionDAG &DAG,
150 ArrayRef<SDValue> Ops,
151 bool IsIntrinsic = false) const;
152
153 SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG,
154 ArrayRef<SDValue> Ops) const;
155
156 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
157 // dwordx4 if on SI.
158 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
159 ArrayRef<SDValue> Ops, EVT MemVT,
160 MachineMemOperand *MMO, SelectionDAG &DAG) const;
161
162 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG,
163 bool ImageStore = false) const;
164
165 /// Converts \p Op, which must be of floating point type, to the
166 /// floating point type \p VT, by either extending or truncating it.
167 SDValue getFPExtOrFPRound(SelectionDAG &DAG,
168 SDValue Op,
169 const SDLoc &DL,
170 EVT VT) const;
171
172 SDValue convertArgType(
173 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
174 bool Signed, const ISD::InputArg *Arg = nullptr) const;
175
176 /// Custom lowering for ISD::FP_ROUND for MVT::f16.
177 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
178 SDValue splitFP_ROUNDVectorOp(SDValue Op, SelectionDAG &DAG) const;
179 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
180 SDValue lowerFMINIMUMNUM_FMAXIMUMNUM(SDValue Op, SelectionDAG &DAG) const;
181 SDValue lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const;
182 SDValue promoteUniformOpToI32(SDValue Op, DAGCombinerInfo &DCI) const;
183 SDValue promoteUniformUnaryOpToI32(SDValue Op, DAGCombinerInfo &DCI) const;
184 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
185 SDValue lowerMUL(SDValue Op, SelectionDAG &DAG) const;
186 SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const;
187 SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
188
189 SDValue getBaseSegmentAperture(unsigned AS, const SDLoc &DL,
190 SelectionDAG &DAG) const;
191 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
192 SelectionDAG &DAG) const;
193
194 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
195 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
196 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
197 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
198 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
199 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
200 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
201
202 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
203 SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const;
204 SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const;
205 SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const;
206 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
207 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
208
209 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
210
211 SDValue performUCharToFloatCombine(SDNode *N,
212 DAGCombinerInfo &DCI) const;
213 SDValue performFCopySignCombine(SDNode *N, DAGCombinerInfo &DCI) const;
214
215 SDValue performSHLPtrCombine(SDNode *N,
216 unsigned AS,
217 EVT MemVT,
218 DAGCombinerInfo &DCI) const;
219
220 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
221
222 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
223 unsigned Opc, SDValue LHS,
224 const ConstantSDNode *CRHS) const;
225
226 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
227 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
228 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
229 SDValue performZeroOrAnyExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
230 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
231 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
232 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
233 const APFloat &C) const;
234 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
235
236 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
237 SDValue Op0, SDValue Op1,
238 bool IsKnownNoNaNs) const;
239 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
240 SDValue Src, SDValue MinVal, SDValue MaxVal,
241 bool Signed) const;
242 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
243 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
244 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
245 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
246 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
247 SDValue performFPRoundCombine(SDNode *N, DAGCombinerInfo &DCI) const;
248 SDValue performFrexpSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
249 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
250
251 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
252 unsigned getFusedOpcode(const SelectionDAG &DAG,
253 const SDNode *N0, const SDNode *N1) const;
254 SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const;
255 SDValue foldAddSub64WithZeroLowBitsTo32(SDNode *N,
256 DAGCombinerInfo &DCI) const;
257
258 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
259 SDValue performPtrAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
260 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
261 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
262 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
263 SDValue performFDivCombine(SDNode *N, DAGCombinerInfo &DCI) const;
264 SDValue performFMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
265 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
266 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
267 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
268 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
269 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
270
271 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
272
273 unsigned isCFIntrinsic(const SDNode *Intr) const;
274
275public:
276 /// \returns True if fixup needs to be emitted for given global value \p GV,
277 /// false otherwise.
278 bool shouldEmitFixup(const GlobalValue *GV) const;
279
280 /// \returns True if GOT relocation needs to be emitted for given global value
281 /// \p GV, false otherwise.
282 bool shouldEmitGOTReloc(const GlobalValue *GV) const;
283
284 /// \returns True if PC-relative relocation needs to be emitted for given
285 /// global value \p GV, false otherwise.
286 bool shouldEmitPCReloc(const GlobalValue *GV) const;
287
288 /// \returns true if this should use a literal constant for an LDS address,
289 /// and not emit a relocation for an LDS global.
290 bool shouldUseLDSConstAddress(const GlobalValue *GV) const;
291
292 /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be
293 /// expanded into a set of cmp/select instructions.
294 static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem,
295 bool IsDivergentIdx,
296 const GCNSubtarget *Subtarget);
297
298 bool shouldExpandVectorDynExt(SDNode *N) const;
299
300 bool shouldPreservePtrArith(const Function &F, EVT PtrVT) const override;
301
302 bool canTransformPtrArithOutOfBounds(const Function &F,
303 EVT PtrVT) const override;
304
305private:
306 /// Returns true if the first real instruction in MBB is 8 bytes and could
307 /// be split by a 32-byte fetch window boundary. Used on GFX950 to avoid
308 /// instruction fetch delays.
309 bool needsFetchWindowAlignment(const MachineBasicBlock &MBB) const;
310
311 // Analyze a combined offset from an amdgcn_s_buffer_load intrinsic and store
312 // the three offsets (voffset, soffset and instoffset) into the SDValue[3]
313 // array pointed to by Offsets.
314 void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
315 SDValue *Offsets, Align Alignment = Align(4)) const;
316
317 // Convert the i128 that an addrspace(8) pointer is natively represented as
318 // into the v4i32 that all the buffer intrinsics expect to receive. We can't
319 // add register classes for i128 on pain of the promotion logic going haywire,
320 // so this slightly ugly hack is what we've got. If passed a non-pointer
321 // argument (as would be seen in older buffer intrinsics), does nothing.
322 SDValue bufferRsrcPtrToVector(SDValue MaybePointer, SelectionDAG &DAG) const;
323
324 // Wrap a 64-bit pointer into a v4i32 (which is how all SelectionDAG code
325 // represents ptr addrspace(8)) using the flags specified in the intrinsic.
326 SDValue lowerPointerAsRsrcIntrin(SDNode *Op, SelectionDAG &DAG) const;
327
328 // Handle 8 bit and 16 bit buffer loads
329 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
330 ArrayRef<SDValue> Ops,
331 MachineMemOperand *MMO,
332 bool IsTFE = false) const;
333
334 // Handle 8 bit and 16 bit buffer stores
335 SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
336 SDLoc DL, SDValue Ops[],
337 MemSDNode *M) const;
338
339public:
340 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
341
342 const GCNSubtarget *getSubtarget() const;
343
344 ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
345
346 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
347 EVT SrcVT) const override;
348
349 bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy,
350 LLT SrcTy) const override;
351
352 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
353
354 // While address space 7 should never make it to codegen, it still needs to
355 // have a MVT to prevent some analyses that query this function from breaking.
356 // We use the custum MVT::amdgpuBufferFatPointer and
357 // amdgpu::amdgpuBufferStridedPointer for this, though we use v8i32 for the
358 // memory type (which is probably unused).
359 MVT getPointerTy(const DataLayout &DL, unsigned AS) const override;
360 MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override;
361
362 void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &, const CallBase &,
363 MachineFunction &MF,
364 unsigned IntrinsicID) const override;
365
366 bool getAddrModeArguments(const IntrinsicInst *I,
367 SmallVectorImpl<Value *> &Ops,
368 Type *&AccessTy) const override;
369
370 bool isLegalFlatAddressingMode(const AddrMode &AM, unsigned AddrSpace) const;
371 bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
372 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
373 unsigned AS,
374 Instruction *I = nullptr) const override;
375
376 bool canMergeStoresTo(unsigned AS, EVT MemVT,
377 const MachineFunction &MF) const override;
378
379 bool allowsMisalignedMemoryAccessesImpl(
380 unsigned Size, unsigned AddrSpace, Align Alignment,
381 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
382 unsigned *IsFast = nullptr) const;
383
384 bool allowsMisalignedMemoryAccesses(
385 LLT Ty, unsigned AddrSpace, Align Alignment,
386 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
387 unsigned *IsFast = nullptr) const override {
388 if (IsFast)
389 *IsFast = 0;
390 return allowsMisalignedMemoryAccessesImpl(Size: Ty.getSizeInBits(), AddrSpace,
391 Alignment, Flags, IsFast);
392 }
393
394 bool allowsMisalignedMemoryAccesses(
395 EVT VT, unsigned AS, Align Alignment,
396 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
397 unsigned *IsFast = nullptr) const override;
398
399 EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,
400 const AttributeList &FuncAttributes) const override;
401
402 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
403
404 static bool isNonGlobalAddrSpace(unsigned AS);
405
406 bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
407
408 TargetLoweringBase::LegalizeTypeAction
409 getPreferredVectorAction(MVT VT) const override;
410
411 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
412 Type *Ty) const override;
413
414 ExtractSubvectorCost getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
415 unsigned Index) const override;
416 bool isExtractVecEltCheap(EVT VT, unsigned Index) const override;
417
418 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
419
420 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
421
422 unsigned combineRepeatedFPDivisors() const override {
423 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
424 // reciprocal.
425 return 2;
426 }
427
428 bool supportSplitCSR(MachineFunction *MF) const override;
429 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
430 void insertCopiesSplitCSR(
431 MachineBasicBlock *Entry,
432 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
433
434 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
435 bool isVarArg,
436 const SmallVectorImpl<ISD::InputArg> &Ins,
437 const SDLoc &DL, SelectionDAG &DAG,
438 SmallVectorImpl<SDValue> &InVals) const override;
439
440 bool CanLowerReturn(CallingConv::ID CallConv,
441 MachineFunction &MF, bool isVarArg,
442 const SmallVectorImpl<ISD::OutputArg> &Outs,
443 LLVMContext &Context, const Type *RetTy) const override;
444
445 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
446 const SmallVectorImpl<ISD::OutputArg> &Outs,
447 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
448 SelectionDAG &DAG) const override;
449
450 void passSpecialInputs(
451 CallLoweringInfo &CLI,
452 CCState &CCInfo,
453 const SIMachineFunctionInfo &Info,
454 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
455 SmallVectorImpl<SDValue> &MemOpChains,
456 SDValue Chain) const;
457
458 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
459 CallingConv::ID CallConv, bool isVarArg,
460 const SmallVectorImpl<ISD::InputArg> &Ins,
461 const SDLoc &DL, SelectionDAG &DAG,
462 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
463 SDValue ThisVal) const;
464
465 bool mayBeEmittedAsTailCall(const CallInst *) const override;
466
467 bool isEligibleForTailCallOptimization(
468 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
469 const SmallVectorImpl<ISD::OutputArg> &Outs,
470 const SmallVectorImpl<SDValue> &OutVals,
471 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
472
473 SDValue LowerCall(CallLoweringInfo &CLI,
474 SmallVectorImpl<SDValue> &InVals) const override;
475
476 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
477 SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
478 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
479 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
480
481 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
482 SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
483 SDValue lowerGET_FPENV(SDValue Op, SelectionDAG &DAG) const;
484 SDValue lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) const;
485 SDValue lowerROTR(SDValue Op, SelectionDAG &DAG) const;
486
487 Register getRegisterByName(const char* RegName, LLT VT,
488 const MachineFunction &MF) const override;
489
490 MachineBasicBlock *splitKillBlock(MachineInstr &MI,
491 MachineBasicBlock *BB) const;
492
493 void bundleInstWithWaitcnt(MachineInstr &MI) const;
494 MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI,
495 MachineBasicBlock *BB) const;
496
497 MachineBasicBlock *
498 EmitInstrWithCustomInserter(MachineInstr &MI,
499 MachineBasicBlock *BB) const override;
500
501 bool enableAggressiveFMAFusion(EVT VT) const override;
502 bool enableAggressiveFMAFusion(LLT Ty) const override;
503 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
504 EVT VT) const override;
505 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
506 LLT getPreferredShiftAmountTy(LLT Ty) const override;
507
508 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
509 EVT VT) const override;
510 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
511 const LLT Ty) const override;
512 bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override;
513 bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override;
514
515 /// Variants for IR level callers, which have no MachineFunction to read the
516 /// denormal mode from and must pass \p FPEnv explicitly.
517 bool isFMAFasterThanFMulAndFAdd(EVT VT, DenormalFPEnv FPEnv) const;
518
519 /// \p VT is used as written, so a vector type reports false.
520 bool isFMADLegal(EVT VT, DenormalFPEnv FPEnv) const;
521
522 /// \p Ty is taken by its scalar type, so a vector type asks about a lane.
523 bool isFMADLegal(const Function &F, Type *Ty) const;
524
525 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
526
527 SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
528 SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
529 SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
530 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
531 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
532 SelectionDAG &DAG) const override;
533
534 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
535 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
536 void AddMemOpInit(MachineInstr &MI) const;
537 void AdjustInstrPostInstrSelection(MachineInstr &MI,
538 SDNode *Node) const override;
539
540 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
541
542 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
543 SDValue Ptr) const;
544 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
545 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
546 std::pair<unsigned, const TargetRegisterClass *>
547 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
548 StringRef Constraint, MVT VT) const override;
549 ConstraintType getConstraintType(StringRef Constraint) const override;
550 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
551 std::vector<SDValue> &Ops,
552 SelectionDAG &DAG) const override;
553 bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
554 bool checkAsmConstraintVal(SDValue Op, StringRef Constraint,
555 uint64_t Val) const;
556 bool checkAsmConstraintValA(SDValue Op,
557 uint64_t Val,
558 unsigned MaxSize = 64) const;
559 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
560 SDValue V) const;
561
562 void finalizeLowering(MachineFunction &MF) const override;
563
564 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
565 const APInt &DemandedElts,
566 const SelectionDAG &DAG,
567 unsigned Depth = 0) const override;
568 void computeKnownBitsForStackObjectPointer(KnownBits &Known,
569 const MachineFunction &MF,
570 Align Alignment) const override;
571 void computeKnownBitsForTargetInstr(GISelValueTracking &Analysis, Register R,
572 KnownBits &Known,
573 const APInt &DemandedElts,
574 const MachineRegisterInfo &MRI,
575 unsigned Depth = 0) const override;
576
577 Align computeKnownAlignForTargetInstr(GISelValueTracking &Analysis,
578 Register R,
579 const MachineRegisterInfo &MRI,
580 unsigned Depth = 0) const override;
581 bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI,
582 UniformityInfo *UA) const override;
583
584 bool hasMemSDNodeUser(SDNode *N) const;
585
586 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0,
587 SDValue N1) const override;
588
589 bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0,
590 Register N1) const override;
591
592 bool isCanonicalized(SelectionDAG &DAG, SDValue Op,
593 SDNodeFlags UserFlags = {}, unsigned MaxDepth = 5) const;
594
595 /// Returns true if \p Op is provably canonical (no FCANONICALIZE needed).
596 /// \p QueryVT is the scalar FP type being checked, threaded unchanged
597 /// through recursion since canonicality is per vector element. FP operands
598 /// whose scalar type differs from \p QueryVT are treated as non-canonical,
599 /// since canonicality does not survive a change of FP format (e.g. bitcast
600 /// v2bf16 to v2f16); non-FP operands are not checked against \p QueryVT.
601 bool isCanonicalized(SelectionDAG &DAG, SDValue Op, EVT QueryVT,
602 SDNodeFlags UserFlags, unsigned MaxDepth) const;
603 bool isCanonicalized(Register Reg, const MachineFunction &MF,
604 unsigned MaxDepth = 5) const;
605 bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const;
606 bool denormalsEnabledForType(LLT Ty, const MachineFunction &MF) const;
607
608 bool isKnownNeverNaNForTargetNode(SDValue Op, const APInt &DemandedElts,
609 const SelectionDAG &DAG, bool SNaN = false,
610 unsigned Depth = 0) const override;
611 AtomicExpansionKind
612 shouldExpandAtomicRMWInIR(const AtomicRMWInst *) const override;
613 AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
614 AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
615 AtomicExpansionKind
616 shouldExpandAtomicCmpXchgInIR(const AtomicCmpXchgInst *AI) const override;
617
618 void emitExpandAtomicAddrSpacePredicate(Instruction *AI) const;
619 void emitExpandAtomicRMW(AtomicRMWInst *AI) const override;
620 void emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const override;
621 void emitExpandAtomicLoad(LoadInst *LI) const override;
622 void emitExpandAtomicStore(StoreInst *SI) const override;
623
624 const TargetRegisterClass *getRegClassFor(MVT VT,
625 bool isDivergent) const override;
626 bool requiresUniformRegister(MachineFunction &MF,
627 const Value *V) const override;
628 Align getPrefLoopAlignment(MachineLoop *ML) const override;
629 unsigned
630 getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const override;
631
632 void allocateHSAUserSGPRs(CCState &CCInfo,
633 MachineFunction &MF,
634 const SIRegisterInfo &TRI,
635 SIMachineFunctionInfo &Info) const;
636
637 void allocatePreloadKernArgSGPRs(CCState &CCInfo,
638 SmallVectorImpl<CCValAssign> &ArgLocs,
639 const SmallVectorImpl<ISD::InputArg> &Ins,
640 MachineFunction &MF,
641 const SIRegisterInfo &TRI,
642 SIMachineFunctionInfo &Info) const;
643
644 void allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF,
645 const SIRegisterInfo &TRI,
646 SIMachineFunctionInfo &Info) const;
647
648 void allocateSystemSGPRs(CCState &CCInfo,
649 MachineFunction &MF,
650 SIMachineFunctionInfo &Info,
651 CallingConv::ID CallConv,
652 bool IsShader) const;
653
654 void allocateSpecialEntryInputVGPRs(CCState &CCInfo,
655 MachineFunction &MF,
656 const SIRegisterInfo &TRI,
657 SIMachineFunctionInfo &Info) const;
658 void allocateSpecialInputSGPRs(
659 CCState &CCInfo,
660 MachineFunction &MF,
661 const SIRegisterInfo &TRI,
662 SIMachineFunctionInfo &Info) const;
663
664 void allocateSpecialInputVGPRs(CCState &CCInfo,
665 MachineFunction &MF,
666 const SIRegisterInfo &TRI,
667 SIMachineFunctionInfo &Info) const;
668 void allocateSpecialInputVGPRsFixed(CCState &CCInfo,
669 MachineFunction &MF,
670 const SIRegisterInfo &TRI,
671 SIMachineFunctionInfo &Info) const;
672
673 MachineMemOperand::Flags
674 getTargetMMOFlags(const Instruction &I) const override;
675};
676
677// Returns true if argument is a boolean value which is not serialized into
678// memory or argument and does not require v_cndmask_b32 to be deserialized.
679bool isBoolSGPR(SDValue V);
680
681} // End namespace llvm
682
683#endif
684