1//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// SI DAG Lowering interface definition
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
15#define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16
17#include "AMDGPUArgumentUsageInfo.h"
18#include "AMDGPUISelLowering.h"
19#include "SIDefines.h"
20#include "llvm/ADT/FloatingPointMode.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include <bitset>
23
24namespace llvm {
25
26class GCNSubtarget;
27class SIMachineFunctionInfo;
28class SIRegisterInfo;
29
30namespace AMDGPU {
31struct ImageDimIntrinsicInfo;
32}
33
34class SITargetLowering final : public AMDGPUTargetLowering {
35private:
36 const GCNSubtarget *Subtarget;
37
38 /// Result types made Custom for ISD::INTRINSIC_W_CHAIN only so that
39 /// unsupported s_buffer_load result types can be diagnosed. Any other
40 /// intrinsic returning one of these must keep using generic legalization.
41 std::bitset<MVT::VALUETYPE_SIZE> SBufferLoadDiagnosticVTs;
42
43public:
44 MVT getRegisterTypeForCallingConv(LLVMContext &Context,
45 CallingConv::ID CC,
46 EVT VT) const override;
47 unsigned getNumRegistersForCallingConv(LLVMContext &Context,
48 CallingConv::ID CC,
49 EVT VT) const override;
50
51 unsigned getVectorTypeBreakdownForCallingConv(
52 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
53 unsigned &NumIntermediates, MVT &RegisterVT) const override;
54
55 MachinePointerInfo getKernargSegmentPtrInfo(MachineFunction &MF) const;
56
57 bool isUniformLoad(const LoadSDNode *Load) const;
58
59private:
60 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
61 SDValue Chain, uint64_t Offset) const;
62 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
63 SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const;
64 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
65 const SDLoc &SL, SDValue Chain,
66 uint64_t Offset, Align Alignment,
67 bool Signed,
68 const ISD::InputArg *Arg = nullptr) const;
69 SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL,
70 Align Alignment,
71 ImplicitParameter Param) const;
72
73 SDValue convertABITypeToValueType(SelectionDAG &DAG, SDValue Val,
74 CCValAssign &VA, const SDLoc &SL) const;
75
76 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
77 const SDLoc &SL, SDValue Chain,
78 const ISD::InputArg &Arg) const;
79 SDValue lowerWorkGroupId(
80 SelectionDAG &DAG, const SIMachineFunctionInfo &MFI, EVT VT,
81 AMDGPUFunctionArgInfo::PreloadedValue ClusterIdPV,
82 AMDGPUFunctionArgInfo::PreloadedValue ClusterMaxIdPV,
83 AMDGPUFunctionArgInfo::PreloadedValue ClusterWorkGroupIdPV) const;
84 SDValue getPreloadedValue(SelectionDAG &DAG,
85 const SIMachineFunctionInfo &MFI,
86 EVT VT,
87 AMDGPUFunctionArgInfo::PreloadedValue) const;
88
89 SDValue LowerGlobalAddress(AMDGPUMachineFunctionInfo *MFI, SDValue Op,
90 SelectionDAG &DAG) const override;
91 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
92
93 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
94 MVT VT, unsigned Offset) const;
95 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr,
96 SelectionDAG &DAG, bool WithChain) const;
97 SDValue lowerSBuffer(EVT VT, EVT MemVT, SDLoc DL, SDValue Chain, SDValue Rsrc,
98 SDValue Offset, SDValue CachePolicy, SelectionDAG &DAG,
99 MachineMemOperand *MMO = nullptr) const;
100
101 SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
102 unsigned NewOpcode) const;
103 SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
104 unsigned NewOpcode) const;
105
106 SDValue lowerWaveID(SelectionDAG &DAG, SDValue Op) const;
107 SDValue lowerConstHwRegRead(SelectionDAG &DAG, SDValue Op,
108 AMDGPU::Hwreg::Id HwReg, unsigned LowBit,
109 unsigned Width) const;
110 SDValue lowerWorkitemID(SelectionDAG &DAG, SDValue Op, unsigned Dim,
111 const ArgDescriptor &ArgDesc) const;
112
113 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
114 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
115 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
116 SDValue LowerCONVERT_FROM_ARBITRARY_FP(SDValue Op, SelectionDAG &DAG) const;
117 SDValue lowerFromFP8(SDValue Op, bool IsBF8, SelectionDAG &DAG) const;
118 SDValue LowerCONVERT_TO_ARBITRARY_FP(SDValue Op, SelectionDAG &DAG) const;
119 SDValue lowerToFP8(SDValue Op, bool IsBF8, bool IsE5M3,
120 SelectionDAG &DAG) const;
121
122 // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
123 // (the offset that is included in bounds checking and swizzling, to be split
124 // between the instruction's voffset and immoffset fields) and soffset (the
125 // offset that is excluded from bounds checking and swizzling, to go in the
126 // instruction's soffset field). This function takes the first kind of
127 // offset and figures out how to split it between voffset and immoffset.
128 std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
129 SelectionDAG &DAG) const;
130
131 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
132 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
134 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
135 SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const;
136 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
137 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
139 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerFFREXP(SDValue Op, SelectionDAG &DAG) const;
142 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
143 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
144 SDValue lowerFSQRTF16(SDValue Op, SelectionDAG &DAG) const;
145 SDValue lowerFSQRTF32(SDValue Op, SelectionDAG &DAG) const;
146 SDValue lowerFSQRTF64(SDValue Op, SelectionDAG &DAG) const;
147 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
148 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
149 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
150 SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
151 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, SelectionDAG &DAG,
152 ArrayRef<SDValue> Ops,
153 bool IsIntrinsic = false) const;
154
155 SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG,
156 ArrayRef<SDValue> Ops) const;
157
158 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
159 // dwordx4 if on SI.
160 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
161 ArrayRef<SDValue> Ops, EVT MemVT,
162 MachineMemOperand *MMO, SelectionDAG &DAG) const;
163
164 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG,
165 bool ImageStore = false) const;
166
167 /// Converts \p Op, which must be of floating point type, to the
168 /// floating point type \p VT, by either extending or truncating it.
169 SDValue getFPExtOrFPRound(SelectionDAG &DAG,
170 SDValue Op,
171 const SDLoc &DL,
172 EVT VT) const;
173
174 SDValue convertArgType(
175 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
176 bool Signed, const ISD::InputArg *Arg = nullptr) const;
177
178 /// Custom lowering for ISD::FP_ROUND for MVT::f16.
179 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
180 SDValue splitFP_ROUNDVectorOp(SDValue Op, SelectionDAG &DAG) const;
181 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
182 SDValue lowerFMINIMUMNUM_FMAXIMUMNUM(SDValue Op, SelectionDAG &DAG) const;
183 SDValue lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const;
184 SDValue promoteUniformOpToI32(SDValue Op, DAGCombinerInfo &DCI) const;
185 SDValue promoteUniformUnaryOpToI32(SDValue Op, DAGCombinerInfo &DCI) const;
186 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
187 SDValue lowerMUL(SDValue Op, SelectionDAG &DAG) const;
188 SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const;
189 SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
190
191 SDValue getBaseSegmentAperture(unsigned AS, const SDLoc &DL,
192 SelectionDAG &DAG) const;
193 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
194 SelectionDAG &DAG) const;
195
196 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
197 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
198 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
199 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
200 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
201 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
202 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
203
204 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
205 SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const;
206 SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const;
207 SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const;
208 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
209 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
210
211 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
212
213 SDValue performUCharToFloatCombine(SDNode *N,
214 DAGCombinerInfo &DCI) const;
215 SDValue performFCopySignCombine(SDNode *N, DAGCombinerInfo &DCI) const;
216
217 SDValue performSHLPtrCombine(SDNode *N,
218 unsigned AS,
219 EVT MemVT,
220 DAGCombinerInfo &DCI) const;
221
222 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
223
224 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
225 unsigned Opc, SDValue LHS,
226 const ConstantSDNode *CRHS) const;
227
228 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
229 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
230 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
231 SDValue performZeroOrAnyExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
232 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
233 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
234 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
235 const APFloat &C) const;
236 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
237
238 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
239 SDValue Op0, SDValue Op1,
240 bool IsKnownNoNaNs) const;
241 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
242 SDValue Src, SDValue MinVal, SDValue MaxVal,
243 bool Signed) const;
244 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
245 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
246 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
247 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
248 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
249 SDValue performFPRoundCombine(SDNode *N, DAGCombinerInfo &DCI) const;
250 SDValue performFrexpSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
251 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
252
253 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
254 unsigned getFusedOpcode(const SelectionDAG &DAG,
255 const SDNode *N0, const SDNode *N1) const;
256 SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const;
257 SDValue foldAddSub64WithZeroLowBitsTo32(SDNode *N,
258 DAGCombinerInfo &DCI) const;
259
260 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
261 SDValue performPtrAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
262 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
263 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
264 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
265 SDValue performFDivCombine(SDNode *N, DAGCombinerInfo &DCI) const;
266 SDValue performFMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
267 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
268 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
269 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
270 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
271 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
272
273 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
274
275 unsigned isCFIntrinsic(const SDNode *Intr) const;
276
277public:
278 /// \returns True if fixup needs to be emitted for given global value \p GV,
279 /// false otherwise.
280 bool shouldEmitFixup(const GlobalValue *GV) const;
281
282 /// \returns True if GOT relocation needs to be emitted for given global value
283 /// \p GV, false otherwise.
284 bool shouldEmitGOTReloc(const GlobalValue *GV) const;
285
286 /// \returns True if PC-relative relocation needs to be emitted for given
287 /// global value \p GV, false otherwise.
288 bool shouldEmitPCReloc(const GlobalValue *GV) const;
289
290 /// \returns true if this should use a literal constant for an LDS address,
291 /// and not emit a relocation for an LDS global.
292 bool shouldUseLDSConstAddress(const GlobalValue *GV) const;
293
294 /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be
295 /// expanded into a set of cmp/select instructions.
296 static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem,
297 bool IsDivergentIdx,
298 const GCNSubtarget *Subtarget);
299
300 bool shouldExpandVectorDynExt(SDNode *N) const;
301
302 bool shouldPreservePtrArith(const Function &F, EVT PtrVT) const override;
303
304 bool canTransformPtrArithOutOfBounds(const Function &F,
305 EVT PtrVT) const override;
306
307private:
308 /// Returns true if the first real instruction in MBB is 8 bytes and could
309 /// be split by a 32-byte fetch window boundary. Used on GFX950 to avoid
310 /// instruction fetch delays.
311 bool needsFetchWindowAlignment(const MachineBasicBlock &MBB) const;
312
313 // Analyze a combined offset from an amdgcn_s_buffer_load intrinsic and store
314 // the three offsets (voffset, soffset and instoffset) into the SDValue[3]
315 // array pointed to by Offsets.
316 void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
317 SDValue *Offsets, Align Alignment = Align(4)) const;
318
319 // Convert the i128 that an addrspace(8) pointer is natively represented as
320 // into the v4i32 that all the buffer intrinsics expect to receive. We can't
321 // add register classes for i128 on pain of the promotion logic going haywire,
322 // so this slightly ugly hack is what we've got. If passed a non-pointer
323 // argument (as would be seen in older buffer intrinsics), does nothing.
324 SDValue bufferRsrcPtrToVector(SDValue MaybePointer, SelectionDAG &DAG) const;
325
326 // Wrap a 64-bit pointer into a v4i32 (which is how all SelectionDAG code
327 // represents ptr addrspace(8)) using the flags specified in the intrinsic.
328 SDValue lowerPointerAsRsrcIntrin(SDNode *Op, SelectionDAG &DAG) const;
329
330 // Handle 8 bit and 16 bit buffer loads
331 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
332 ArrayRef<SDValue> Ops,
333 MachineMemOperand *MMO,
334 bool IsTFE = false) const;
335
336 // Handle 8 bit and 16 bit buffer stores
337 SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
338 SDLoc DL, SDValue Ops[],
339 MemSDNode *M) const;
340
341public:
342 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
343
344 const GCNSubtarget *getSubtarget() const;
345
346 ArrayRef<MCPhysReg> getRoundingControlRegisters() const override;
347
348 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
349 EVT SrcVT) const override;
350
351 bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy,
352 LLT SrcTy) const override;
353
354 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
355
356 // While address space 7 should never make it to codegen, it still needs to
357 // have a MVT to prevent some analyses that query this function from breaking.
358 // We use the custum MVT::amdgpuBufferFatPointer and
359 // amdgpu::amdgpuBufferStridedPointer for this, though we use v8i32 for the
360 // memory type (which is probably unused).
361 MVT getPointerTy(const DataLayout &DL, unsigned AS) const override;
362 MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override;
363
364 void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &, const CallBase &,
365 MachineFunction &MF,
366 unsigned IntrinsicID) const override;
367
368 bool getAddrModeArguments(const IntrinsicInst *I,
369 SmallVectorImpl<Value *> &Ops,
370 Type *&AccessTy) const override;
371
372 bool isLegalFlatAddressingMode(const AddrMode &AM, unsigned AddrSpace) const;
373 bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
374 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
375 unsigned AS,
376 Instruction *I = nullptr) const override;
377
378 bool canMergeStoresTo(unsigned AS, EVT MemVT,
379 const MachineFunction &MF) const override;
380
381 bool allowsMisalignedMemoryAccessesImpl(
382 unsigned Size, unsigned AddrSpace, Align Alignment,
383 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
384 unsigned *IsFast = nullptr) const;
385
386 bool allowsMisalignedMemoryAccesses(
387 LLT Ty, unsigned AddrSpace, Align Alignment,
388 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
389 unsigned *IsFast = nullptr) const override {
390 if (IsFast)
391 *IsFast = 0;
392 return allowsMisalignedMemoryAccessesImpl(Size: Ty.getSizeInBits(), AddrSpace,
393 Alignment, Flags, IsFast);
394 }
395
396 bool allowsMisalignedMemoryAccesses(
397 EVT VT, unsigned AS, Align Alignment,
398 MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
399 unsigned *IsFast = nullptr) const override;
400
401 EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,
402 const AttributeList &FuncAttributes) const override;
403
404 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
405
406 static bool isNonGlobalAddrSpace(unsigned AS);
407
408 bool isFreeAddrSpaceCast(const DataLayout &DL, unsigned SrcAS,
409 unsigned DestAS) const override;
410
411 TargetLoweringBase::LegalizeTypeAction
412 getPreferredVectorAction(MVT VT) const override;
413
414 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
415 Type *Ty) const override;
416
417 ExtractSubvectorCost getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
418 unsigned Index) const override;
419 bool isExtractVecEltCheap(EVT VT, unsigned Index) const override;
420
421 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
422 bool isTypeDesirableForOp(SDNode *N, EVT VT) const override;
423
424 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
425
426 unsigned combineRepeatedFPDivisors() const override {
427 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
428 // reciprocal.
429 return 2;
430 }
431
432 bool supportSplitCSR(MachineFunction *MF) const override;
433 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
434 void insertCopiesSplitCSR(
435 MachineBasicBlock *Entry,
436 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
437
438 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
439 bool isVarArg,
440 const SmallVectorImpl<ISD::InputArg> &Ins,
441 const SDLoc &DL, SelectionDAG &DAG,
442 SmallVectorImpl<SDValue> &InVals) const override;
443
444 bool CanLowerReturn(CallingConv::ID CallConv,
445 MachineFunction &MF, bool isVarArg,
446 const SmallVectorImpl<ISD::OutputArg> &Outs,
447 LLVMContext &Context, const Type *RetTy) const override;
448
449 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
450 const SmallVectorImpl<ISD::OutputArg> &Outs,
451 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
452 SelectionDAG &DAG) const override;
453
454 void passSpecialInputs(
455 CallLoweringInfo &CLI,
456 CCState &CCInfo,
457 const SIMachineFunctionInfo &Info,
458 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
459 SmallVectorImpl<SDValue> &MemOpChains,
460 SDValue Chain) const;
461
462 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
463 CallingConv::ID CallConv, bool isVarArg,
464 const SmallVectorImpl<ISD::InputArg> &Ins,
465 const SDLoc &DL, SelectionDAG &DAG,
466 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
467 SDValue ThisVal) const;
468
469 bool mayBeEmittedAsTailCall(const CallInst *) const override;
470
471 bool isEligibleForTailCallOptimization(
472 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
473 const SmallVectorImpl<ISD::OutputArg> &Outs,
474 const SmallVectorImpl<SDValue> &OutVals,
475 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
476
477 SDValue LowerCall(CallLoweringInfo &CLI,
478 SmallVectorImpl<SDValue> &InVals) const override;
479
480 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
481 SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
482 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
483 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
484
485 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
486 SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
487 SDValue lowerGET_FPENV(SDValue Op, SelectionDAG &DAG) const;
488 SDValue lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) const;
489 SDValue lowerROTR(SDValue Op, SelectionDAG &DAG) const;
490
491 Register getRegisterByName(const char* RegName, LLT VT,
492 const MachineFunction &MF) const override;
493
494 MachineBasicBlock *splitKillBlock(MachineInstr &MI,
495 MachineBasicBlock *BB) const;
496
497 void bundleInstWithWaitcnt(MachineInstr &MI) const;
498 MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI,
499 MachineBasicBlock *BB) const;
500
501 MachineBasicBlock *
502 EmitInstrWithCustomInserter(MachineInstr &MI,
503 MachineBasicBlock *BB) const override;
504
505 bool enableAggressiveFMAFusion(EVT VT) const override;
506 bool enableAggressiveFMAFusion(LLT Ty) const override;
507 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
508 EVT VT) const override;
509 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
510 LLT getPreferredShiftAmountTy(LLT Ty) const override;
511
512 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
513 EVT VT) const override;
514 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
515 const LLT Ty) const override;
516 bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override;
517 bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override;
518
519 /// Variants for IR level callers, which have no MachineFunction to read the
520 /// denormal mode from and must pass \p FPEnv explicitly.
521 bool isFMAFasterThanFMulAndFAdd(EVT VT, DenormalFPEnv FPEnv) const;
522
523 /// \p VT is used as written, so a vector type reports false.
524 bool isFMADLegal(EVT VT, DenormalFPEnv FPEnv) const;
525
526 /// \p Ty is taken by its scalar type, so a vector type asks about a lane.
527 bool isFMADLegal(const Function &F, Type *Ty) const;
528
529 bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
530
531 SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
532 SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
533 SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const;
534 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
535 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
536 SelectionDAG &DAG) const override;
537
538 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
539 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
540 void AddMemOpInit(MachineInstr &MI) const;
541 void AdjustInstrPostInstrSelection(MachineInstr &MI,
542 SDNode *Node) const override;
543
544 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
545
546 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
547 SDValue Ptr) const;
548 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
549 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
550 std::pair<unsigned, const TargetRegisterClass *>
551 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
552 StringRef Constraint, MVT VT) const override;
553 ConstraintType getConstraintType(StringRef Constraint) const override;
554 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
555 std::vector<SDValue> &Ops,
556 SelectionDAG &DAG) const override;
557 bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
558 bool checkAsmConstraintVal(SDValue Op, StringRef Constraint,
559 uint64_t Val) const;
560 bool checkAsmConstraintValA(SDValue Op,
561 uint64_t Val,
562 unsigned MaxSize = 64) const;
563 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
564 SDValue V) const;
565
566 void finalizeLowering(MachineFunction &MF) const override;
567
568 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
569 const APInt &DemandedElts,
570 const SelectionDAG &DAG,
571 unsigned Depth = 0) const override;
572 void computeKnownBitsForStackObjectPointer(KnownBits &Known,
573 const MachineFunction &MF,
574 Align Alignment) const override;
575 void computeKnownBitsForTargetInstr(GISelValueTracking &Analysis, Register R,
576 KnownBits &Known,
577 const APInt &DemandedElts,
578 const MachineRegisterInfo &MRI,
579 unsigned Depth = 0) const override;
580
581 Align computeKnownAlignForTargetInstr(GISelValueTracking &Analysis,
582 Register R,
583 const MachineRegisterInfo &MRI,
584 unsigned Depth = 0) const override;
585 bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI,
586 UniformityInfo *UA) const override;
587
588 bool hasMemSDNodeUser(SDNode *N) const;
589
590 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0,
591 SDValue N1) const override;
592
593 bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0,
594 Register N1) const override;
595
596 bool isCanonicalized(SelectionDAG &DAG, SDValue Op,
597 SDNodeFlags UserFlags = {}, unsigned MaxDepth = 5) const;
598
599 /// Returns true if \p Op is provably canonical (no FCANONICALIZE needed).
600 /// \p QueryVT is the scalar FP type being checked, threaded unchanged
601 /// through recursion since canonicality is per vector element. FP operands
602 /// whose scalar type differs from \p QueryVT are treated as non-canonical,
603 /// since canonicality does not survive a change of FP format (e.g. bitcast
604 /// v2bf16 to v2f16); non-FP operands are not checked against \p QueryVT.
605 bool isCanonicalized(SelectionDAG &DAG, SDValue Op, EVT QueryVT,
606 SDNodeFlags UserFlags, unsigned MaxDepth) const;
607 bool isCanonicalized(Register Reg, const MachineFunction &MF,
608 unsigned MaxDepth = 5) const;
609 bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const;
610 bool denormalsEnabledForType(LLT Ty, const MachineFunction &MF) const;
611
612 bool isKnownNeverNaNForTargetNode(SDValue Op, const APInt &DemandedElts,
613 const SelectionDAG &DAG, bool SNaN = false,
614 unsigned Depth = 0) const override;
615 AtomicExpansionKind
616 shouldExpandAtomicRMWInIR(const AtomicRMWInst *) const override;
617 AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
618 AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
619 AtomicExpansionKind
620 shouldExpandAtomicCmpXchgInIR(const AtomicCmpXchgInst *AI) const override;
621
622 void emitExpandAtomicAddrSpacePredicate(Instruction *AI) const;
623 void emitExpandAtomicRMW(AtomicRMWInst *AI) const override;
624 void emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const override;
625 void emitExpandAtomicLoad(LoadInst *LI) const override;
626 void emitExpandAtomicStore(StoreInst *SI) const override;
627
628 const TargetRegisterClass *getRegClassFor(MVT VT,
629 bool isDivergent) const override;
630 bool requiresUniformRegister(MachineFunction &MF,
631 const Value *V) const override;
632 Align
633 getPrefLoopAlignment(MachineLoop *ML,
634 const MachineBasicBlock *BlockToAlign) const override;
635 unsigned
636 getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const override;
637
638 void allocateHSAUserSGPRs(CCState &CCInfo,
639 MachineFunction &MF,
640 const SIRegisterInfo &TRI,
641 SIMachineFunctionInfo &Info) const;
642
643 void allocatePreloadKernArgSGPRs(CCState &CCInfo,
644 SmallVectorImpl<CCValAssign> &ArgLocs,
645 const SmallVectorImpl<ISD::InputArg> &Ins,
646 MachineFunction &MF,
647 const SIRegisterInfo &TRI,
648 SIMachineFunctionInfo &Info) const;
649
650 void allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF,
651 const SIRegisterInfo &TRI,
652 SIMachineFunctionInfo &Info) const;
653
654 void allocateSystemSGPRs(CCState &CCInfo,
655 MachineFunction &MF,
656 SIMachineFunctionInfo &Info,
657 CallingConv::ID CallConv,
658 bool IsShader) const;
659
660 void allocateSpecialEntryInputVGPRs(CCState &CCInfo,
661 MachineFunction &MF,
662 const SIRegisterInfo &TRI,
663 SIMachineFunctionInfo &Info) const;
664 void allocateSpecialInputSGPRs(
665 CCState &CCInfo,
666 MachineFunction &MF,
667 const SIRegisterInfo &TRI,
668 SIMachineFunctionInfo &Info) const;
669
670 void allocateSpecialInputVGPRsFixed(CCState &CCInfo,
671 MachineFunction &MF,
672 const SIRegisterInfo &TRI,
673 SIMachineFunctionInfo &Info) const;
674
675 MachineMemOperand::Flags
676 getTargetMMOFlags(const Instruction &I) const override;
677};
678
679// Returns true if argument is a boolean value which is not serialized into
680// memory or argument and does not require v_cndmask_b32 to be deserialized.
681bool isBoolSGPR(SDValue V);
682
683} // End namespace llvm
684
685#endif
686