1//===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// The AMDGPU TargetMachine interface definition for hw codegen targets.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
15#define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
16
17#include "GCNSubtarget.h"
18#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
19#include "llvm/CodeGen/TargetPassConfig.h"
20#include "llvm/MC/MCStreamer.h"
21#include <optional>
22#include <utility>
23
24namespace llvm {
25
26//===----------------------------------------------------------------------===//
27// AMDGPU Target Machine (R600+)
28//===----------------------------------------------------------------------===//
29
30namespace AMDGPU {
31StringRef getSchedStrategy(const Function &F);
32}
33
34class AMDGPUTargetMachine : public CodeGenTargetMachineImpl {
35protected:
36 std::unique_ptr<TargetLoweringObjectFile> TLOF;
37
38 StringRef getGPUName(const Function &F) const;
39 StringRef getFeatureString(const Function &F) const;
40
41public:
42 static bool EnableFunctionCalls;
43 static bool EnableLowerModuleLDS;
44
45 AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
46 StringRef FS, const TargetOptions &Options,
47 std::optional<Reloc::Model> RM,
48 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL);
49 ~AMDGPUTargetMachine() override;
50
51 const TargetSubtargetInfo *getSubtargetImpl() const;
52 const TargetSubtargetInfo *
53 getSubtargetImpl(const Function &) const override = 0;
54
55 TargetLoweringObjectFile *getObjFileLowering() const override {
56 return TLOF.get();
57 }
58
59 void registerPassBuilderCallbacks(PassBuilder &PB) override;
60 void registerDefaultAliasAnalyses(AAManager &) override;
61
62 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
63
64 unsigned getAssumedAddrSpace(const Value *V) const override;
65
66 std::pair<const Value *, unsigned>
67 getPredicatedAddrSpace(const Value *V) const override;
68
69 unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override;
70
71 bool splitModule(Module &M, unsigned NumParts,
72 function_ref<void(std::unique_ptr<Module> MPart)>
73 ModuleCallback) override;
74 ScheduleDAGInstrs *
75 createMachineScheduler(MachineSchedContext *C) const override;
76};
77
78//===----------------------------------------------------------------------===//
79// GCN Target Machine (SI+)
80//===----------------------------------------------------------------------===//
81
82class GCNTargetMachine final : public AMDGPUTargetMachine {
83private:
84 mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap;
85
86public:
87 GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
88 StringRef FS, const TargetOptions &Options,
89 std::optional<Reloc::Model> RM,
90 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
91 bool JIT);
92
93 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
94
95 const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override;
96
97 TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
98
99 bool useIPRA() const override { return true; }
100
101 Error buildCodeGenPipeline(ModulePassManager &MPM, raw_pwrite_stream &Out,
102 raw_pwrite_stream *DwoOut,
103 CodeGenFileType FileType,
104 const CGPassBuilderOption &Opts, MCContext &Ctx,
105 PassInstrumentationCallbacks *PIC) override;
106
107 void registerMachineRegisterInfoCallback(MachineFunction &MF) const override;
108
109 MachineFunctionInfo *
110 createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
111 const TargetSubtargetInfo *STI) const override;
112
113 yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
114 yaml::MachineFunctionInfo *
115 convertFuncInfoToYAML(const MachineFunction &MF) const override;
116 bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
117 PerFunctionMIParsingState &PFS,
118 SMDiagnostic &Error,
119 SMRange &SourceRange) const override;
120 ScheduleDAGInstrs *
121 createMachineScheduler(MachineSchedContext *C) const override;
122 ScheduleDAGInstrs *
123 createPostMachineScheduler(MachineSchedContext *C) const override;
124};
125
126//===----------------------------------------------------------------------===//
127// AMDGPU Pass Setup - For Legacy Pass Manager.
128//===----------------------------------------------------------------------===//
129
130class AMDGPUPassConfig : public TargetPassConfig {
131public:
132 AMDGPUPassConfig(TargetMachine &TM, PassManagerBase &PM);
133
134 AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
135 return getTM<AMDGPUTargetMachine>();
136 }
137 void addEarlyCSEOrGVNPass();
138 void addStraightLineScalarOptimizationPasses();
139 void addIRPasses() override;
140 void addCodeGenPrepare() override;
141 bool addPreISel() override;
142 bool addInstSelector() override;
143 bool addGCPasses() override;
144
145 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
146
147 /// Check if a pass is enabled given \p Opt option. The option always
148 /// overrides defaults if explicitly used. Otherwise its default will
149 /// be used given that a pass shall work at an optimization \p Level
150 /// minimum.
151 bool isPassEnabled(const cl::opt<bool> &Opt,
152 CodeGenOptLevel Level = CodeGenOptLevel::Default) const {
153 if (Opt.getNumOccurrences())
154 return Opt;
155 if (TM->getOptLevel() < Level)
156 return false;
157 return Opt;
158 }
159};
160
161} // end namespace llvm
162
163#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
164