1//===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// The AMDGPU TargetMachine interface definition for hw codegen targets.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
15#define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
16
17#include "GCNSubtarget.h"
18#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
19#include "llvm/CodeGen/TargetPassConfig.h"
20#include "llvm/MC/MCStreamer.h"
21#include <optional>
22#include <utility>
23
24namespace llvm {
25
26//===----------------------------------------------------------------------===//
27// AMDGPU Target Machine (R600+)
28//===----------------------------------------------------------------------===//
29
30class AMDGPUTargetMachine : public CodeGenTargetMachineImpl {
31protected:
32 std::unique_ptr<TargetLoweringObjectFile> TLOF;
33
34 StringRef getGPUName(const Function &F) const;
35 StringRef getFeatureString(const Function &F) const;
36
37public:
38 static bool EnableFunctionCalls;
39 static bool EnableLowerModuleLDS;
40
41 AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
42 StringRef FS, const TargetOptions &Options,
43 std::optional<Reloc::Model> RM,
44 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL);
45 ~AMDGPUTargetMachine() override;
46
47 const TargetSubtargetInfo *getSubtargetImpl() const;
48 const TargetSubtargetInfo *
49 getSubtargetImpl(const Function &) const override = 0;
50
51 TargetLoweringObjectFile *getObjFileLowering() const override {
52 return TLOF.get();
53 }
54
55 void registerPassBuilderCallbacks(PassBuilder &PB) override;
56 void registerDefaultAliasAnalyses(AAManager &) override;
57
58 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
59
60 unsigned getAssumedAddrSpace(const Value *V) const override;
61
62 std::pair<const Value *, unsigned>
63 getPredicatedAddrSpace(const Value *V) const override;
64
65 unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override;
66
67 bool splitModule(Module &M, unsigned NumParts,
68 function_ref<void(std::unique_ptr<Module> MPart)>
69 ModuleCallback) override;
70 ScheduleDAGInstrs *
71 createMachineScheduler(MachineSchedContext *C) const override;
72};
73
74//===----------------------------------------------------------------------===//
75// GCN Target Machine (SI+)
76//===----------------------------------------------------------------------===//
77
78class GCNTargetMachine final : public AMDGPUTargetMachine {
79private:
80 mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap;
81
82public:
83 GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
84 StringRef FS, const TargetOptions &Options,
85 std::optional<Reloc::Model> RM,
86 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
87 bool JIT);
88
89 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
90
91 const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override;
92
93 TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
94
95 bool useIPRA() const override { return true; }
96
97 Error buildCodeGenPipeline(ModulePassManager &MPM, raw_pwrite_stream &Out,
98 raw_pwrite_stream *DwoOut,
99 CodeGenFileType FileType,
100 const CGPassBuilderOption &Opts, MCContext &Ctx,
101 PassInstrumentationCallbacks *PIC) override;
102
103 void registerMachineRegisterInfoCallback(MachineFunction &MF) const override;
104
105 MachineFunctionInfo *
106 createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
107 const TargetSubtargetInfo *STI) const override;
108
109 yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
110 yaml::MachineFunctionInfo *
111 convertFuncInfoToYAML(const MachineFunction &MF) const override;
112 bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
113 PerFunctionMIParsingState &PFS,
114 SMDiagnostic &Error,
115 SMRange &SourceRange) const override;
116 ScheduleDAGInstrs *
117 createMachineScheduler(MachineSchedContext *C) const override;
118 ScheduleDAGInstrs *
119 createPostMachineScheduler(MachineSchedContext *C) const override;
120};
121
122//===----------------------------------------------------------------------===//
123// AMDGPU Pass Setup - For Legacy Pass Manager.
124//===----------------------------------------------------------------------===//
125
126class AMDGPUPassConfig : public TargetPassConfig {
127public:
128 AMDGPUPassConfig(TargetMachine &TM, PassManagerBase &PM);
129
130 AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
131 return getTM<AMDGPUTargetMachine>();
132 }
133 void addEarlyCSEOrGVNPass();
134 void addStraightLineScalarOptimizationPasses();
135 void addIRPasses() override;
136 void addCodeGenPrepare() override;
137 bool addPreISel() override;
138 bool addInstSelector() override;
139 bool addGCPasses() override;
140
141 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
142
143 /// Check if a pass is enabled given \p Opt option. The option always
144 /// overrides defaults if explicitly used. Otherwise its default will
145 /// be used given that a pass shall work at an optimization \p Level
146 /// minimum.
147 bool isPassEnabled(const cl::opt<bool> &Opt,
148 CodeGenOptLevel Level = CodeGenOptLevel::Default) const {
149 if (Opt.getNumOccurrences())
150 return Opt;
151 if (TM->getOptLevel() < Level)
152 return false;
153 return Opt;
154 }
155};
156
157} // end namespace llvm
158
159#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
160