1//===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// The AMDGPU TargetMachine interface definition for hw codegen targets.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
15#define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
16
17#include "GCNSubtarget.h"
18#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
19#include "llvm/CodeGen/TargetPassConfig.h"
20#include "llvm/MC/MCStreamer.h"
21#include <optional>
22#include <utility>
23
24namespace llvm {
25
26//===----------------------------------------------------------------------===//
27// AMDGPU Target Machine (R600+)
28//===----------------------------------------------------------------------===//
29
30namespace AMDGPU {
31StringRef getSchedStrategy(const Function &F);
32}
33
34class AMDGPUTargetMachine : public CodeGenTargetMachineImpl {
35protected:
36 std::unique_ptr<TargetLoweringObjectFile> TLOF;
37
38 StringRef getGPUName(const Function &F) const;
39 StringRef getFeatureString(const Function &F) const;
40
41public:
42 static bool EnableFunctionCalls;
43 static bool EnableObjectLinking;
44 static bool EnableLowerModuleLDS;
45
46 AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
47 StringRef FS, const TargetOptions &Options,
48 std::optional<Reloc::Model> RM,
49 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL);
50 ~AMDGPUTargetMachine() override;
51
52 const TargetSubtargetInfo *getSubtargetImpl() const;
53 const TargetSubtargetInfo *
54 getSubtargetImpl(const Function &) const override = 0;
55
56 TargetLoweringObjectFile *getObjFileLowering() const override {
57 return TLOF.get();
58 }
59
60 void registerPassBuilderCallbacks(PassBuilder &PB) override;
61 void registerDefaultAliasAnalyses(AAManager &) override;
62
63 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
64
65 unsigned getAssumedAddrSpace(const Value *V) const override;
66
67 std::pair<const Value *, unsigned>
68 getPredicatedAddrSpace(const Value *V) const override;
69
70 unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override;
71
72 bool splitModule(Module &M, unsigned NumParts,
73 function_ref<void(std::unique_ptr<Module> MPart)>
74 ModuleCallback) override;
75 ScheduleDAGInstrs *
76 createMachineScheduler(MachineSchedContext *C) const override;
77};
78
79//===----------------------------------------------------------------------===//
80// GCN Target Machine (SI+)
81//===----------------------------------------------------------------------===//
82
83class GCNTargetMachine final : public AMDGPUTargetMachine {
84private:
85 mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap;
86
87public:
88 GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
89 StringRef FS, const TargetOptions &Options,
90 std::optional<Reloc::Model> RM,
91 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
92 bool JIT);
93
94 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
95
96 const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override;
97
98 TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
99
100 bool useIPRA() const override { return true; }
101
102 Error buildCodeGenPipeline(ModulePassManager &MPM, ModuleAnalysisManager &MAM,
103 raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
104 CodeGenFileType FileType,
105 const CGPassBuilderOption &Opts, MCContext &Ctx,
106 PassInstrumentationCallbacks *PIC) override;
107
108 void registerMachineRegisterInfoCallback(MachineFunction &MF) const override;
109
110 MachineFunctionInfo *
111 createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
112 const TargetSubtargetInfo *STI) const override;
113
114 yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
115 yaml::MachineFunctionInfo *
116 convertFuncInfoToYAML(const MachineFunction &MF) const override;
117 bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
118 PerFunctionMIParsingState &PFS,
119 SMDiagnostic &Error,
120 SMRange &SourceRange) const override;
121 ScheduleDAGInstrs *
122 createMachineScheduler(MachineSchedContext *C) const override;
123 ScheduleDAGInstrs *
124 createPostMachineScheduler(MachineSchedContext *C) const override;
125};
126
127//===----------------------------------------------------------------------===//
128// AMDGPU Pass Setup - For Legacy Pass Manager.
129//===----------------------------------------------------------------------===//
130
131class AMDGPUPassConfig : public TargetPassConfig {
132public:
133 AMDGPUPassConfig(TargetMachine &TM, PassManagerBase &PM);
134
135 AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
136 return getTM<AMDGPUTargetMachine>();
137 }
138 void addEarlyCSEOrGVNPass();
139 void addStraightLineScalarOptimizationPasses();
140 void addIRPasses() override;
141 void addCodeGenPrepare() override;
142 bool addPreISel() override;
143 bool addInstSelector() override;
144 bool addGCPasses() override;
145
146 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
147
148 /// Check if a pass is enabled given \p Opt option. The option always
149 /// overrides defaults if explicitly used. Otherwise its default will
150 /// be used given that a pass shall work at an optimization \p Level
151 /// minimum.
152 bool isPassEnabled(const cl::opt<bool> &Opt,
153 CodeGenOptLevel Level = CodeGenOptLevel::Default) const {
154 if (Opt.getNumOccurrences())
155 return Opt;
156 if (TM->getOptLevel() < Level)
157 return false;
158 return Opt;
159 }
160};
161
162} // end namespace llvm
163
164#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
165