1//===- AMDGPULaneMaskUtils.h - Exec/lane mask helper functions -*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPULANEMASKUTILS_H
10#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPULANEMASKUTILS_H
11
12#include "GCNSubtarget.h"
13#include "llvm/CodeGen/Register.h"
14
15namespace llvm {
16
17class GCNSubtarget;
18
19namespace AMDGPU {
20
21class LaneMaskConstants {
22public:
23 const Register ExecReg;
24 const Register VccReg;
25 const unsigned AndOpc;
26 const unsigned AndTermOpc;
27 const unsigned AndN2Opc;
28 const unsigned AndN2SaveExecOpc;
29 const unsigned AndN2TermOpc;
30 const unsigned AndSaveExecOpc;
31 const unsigned AndSaveExecTermOpc;
32 const unsigned BfmOpc;
33 const unsigned CMovOpc;
34 const unsigned CSelectOpc;
35 const unsigned MovOpc;
36 const unsigned MovTermOpc;
37 const unsigned OrOpc;
38 const unsigned OrTermOpc;
39 const unsigned OrSaveExecOpc;
40 const unsigned XorOpc;
41 const unsigned XorTermOpc;
42 const unsigned WQMOpc;
43
44 constexpr LaneMaskConstants(bool IsWave32)
45 : ExecReg(IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC),
46 VccReg(IsWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC),
47 AndOpc(IsWave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64),
48 AndTermOpc(IsWave32 ? AMDGPU::S_AND_B32_term : AMDGPU::S_AND_B64_term),
49 AndN2Opc(IsWave32 ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_ANDN2_B64),
50 AndN2SaveExecOpc(IsWave32 ? AMDGPU::S_ANDN2_SAVEEXEC_B32
51 : AMDGPU::S_ANDN2_SAVEEXEC_B64),
52 AndN2TermOpc(IsWave32 ? AMDGPU::S_ANDN2_B32_term
53 : AMDGPU::S_ANDN2_B64_term),
54 AndSaveExecOpc(IsWave32 ? AMDGPU::S_AND_SAVEEXEC_B32
55 : AMDGPU::S_AND_SAVEEXEC_B64),
56 AndSaveExecTermOpc(IsWave32 ? AMDGPU::S_AND_SAVEEXEC_B32_term
57 : AMDGPU::S_AND_SAVEEXEC_B64_term),
58 BfmOpc(IsWave32 ? AMDGPU::S_BFM_B32 : AMDGPU::S_BFM_B64),
59 CMovOpc(IsWave32 ? AMDGPU::S_CMOV_B32 : AMDGPU::S_CMOV_B64),
60 CSelectOpc(IsWave32 ? AMDGPU::S_CSELECT_B32 : AMDGPU::S_CSELECT_B64),
61 MovOpc(IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64),
62 MovTermOpc(IsWave32 ? AMDGPU::S_MOV_B32_term : AMDGPU::S_MOV_B64_term),
63 OrOpc(IsWave32 ? AMDGPU::S_OR_B32 : AMDGPU::S_OR_B64),
64 OrTermOpc(IsWave32 ? AMDGPU::S_OR_B32_term : AMDGPU::S_OR_B64_term),
65 OrSaveExecOpc(IsWave32 ? AMDGPU::S_OR_SAVEEXEC_B32
66 : AMDGPU::S_OR_SAVEEXEC_B64),
67 XorOpc(IsWave32 ? AMDGPU::S_XOR_B32 : AMDGPU::S_XOR_B64),
68 XorTermOpc(IsWave32 ? AMDGPU::S_XOR_B32_term : AMDGPU::S_XOR_B64_term),
69 WQMOpc(IsWave32 ? AMDGPU::S_WQM_B32 : AMDGPU::S_WQM_B64) {}
70
71 static inline const LaneMaskConstants &get(const GCNSubtarget &ST);
72};
73
74static constexpr LaneMaskConstants LaneMaskConstants32 =
75 LaneMaskConstants(/*IsWave32=*/true);
76static constexpr LaneMaskConstants LaneMaskConstants64 =
77 LaneMaskConstants(/*IsWave32=*/false);
78
79inline const LaneMaskConstants &LaneMaskConstants::get(const GCNSubtarget &ST) {
80 unsigned WavefrontSize = ST.getWavefrontSize();
81 assert(WavefrontSize == 32 || WavefrontSize == 64);
82 return WavefrontSize == 32 ? LaneMaskConstants32 : LaneMaskConstants64;
83}
84
85} // end namespace AMDGPU
86
87} // end namespace llvm
88
89#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPULANEMASKUTILS_H
90