1//===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10///
11/// This file contains declaration for AMDGPU ISA disassembler
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
16#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17
18#include "SIDefines.h"
19#include "llvm/ADT/APInt.h"
20#include "llvm/ADT/SmallString.h"
21#include "llvm/MC/MCDisassembler/MCDisassembler.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/Support/DataExtractor.h"
25#include <memory>
26
27namespace llvm {
28
29class MCAsmInfo;
30class MCInst;
31class MCOperand;
32class MCSubtargetInfo;
33class Twine;
34
35//===----------------------------------------------------------------------===//
36// AMDGPUDisassembler
37//===----------------------------------------------------------------------===//
38
39class AMDGPUDisassembler : public MCDisassembler {
40private:
41 std::unique_ptr<MCInstrInfo const> const MCII;
42 const MCRegisterInfo &MRI;
43 const MCAsmInfo &MAI;
44 const unsigned HwModeRegClass;
45 const unsigned TargetMaxInstBytes;
46 mutable ArrayRef<uint8_t> Bytes;
47 mutable uint64_t Literal;
48 mutable bool HasLiteral;
49 mutable std::optional<bool> EnableWavefrontSize32;
50 unsigned CodeObjectVersion;
51 const MCExpr *UCVersionW64Expr;
52 const MCExpr *UCVersionW32Expr;
53 const MCExpr *UCVersionMDPExpr;
54
55 const MCExpr *createConstantSymbolExpr(StringRef Id, int64_t Val);
56
57 void decodeImmOperands(MCInst &MI, const MCInstrInfo &MCII) const;
58
59public:
60 AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
61 MCInstrInfo const *MCII);
62 ~AMDGPUDisassembler() override = default;
63
64 void setABIVersion(unsigned Version) override;
65
66 DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
67 ArrayRef<uint8_t> Bytes, uint64_t Address,
68 raw_ostream &CS) const override;
69
70 const char* getRegClassName(unsigned RegClassID) const;
71
72 MCOperand createRegOperand(MCRegister Reg) const;
73 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
74 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
75 MCOperand createVGPR16Operand(unsigned RegIdx, bool IsHi) const;
76
77 MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
78
79 template <typename InsnType>
80 DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst,
81 uint64_t Address, raw_ostream &Comments) const;
82 template <typename InsnType>
83 DecodeStatus tryDecodeInst(const uint8_t *Table1, const uint8_t *Table2,
84 MCInst &MI, InsnType Inst, uint64_t Address,
85 raw_ostream &Comments) const;
86
87 Expected<bool> onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size,
88 ArrayRef<uint8_t> Bytes,
89 uint64_t Address) const override;
90
91 Expected<bool> decodeKernelDescriptor(StringRef KdName,
92 ArrayRef<uint8_t> Bytes,
93 uint64_t KdAddress) const;
94
95 Expected<bool>
96 decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor,
97 ArrayRef<uint8_t> Bytes,
98 raw_string_ostream &KdStream) const;
99
100 /// Decode as directives that handle COMPUTE_PGM_RSRC1.
101 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC1.
102 /// \param KdStream - Stream to write the disassembled directives to.
103 // NOLINTNEXTLINE(readability-identifier-naming)
104 Expected<bool> decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer,
105 raw_string_ostream &KdStream) const;
106
107 /// Decode as directives that handle COMPUTE_PGM_RSRC2.
108 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC2.
109 /// \param KdStream - Stream to write the disassembled directives to.
110 // NOLINTNEXTLINE(readability-identifier-naming)
111 Expected<bool> decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer,
112 raw_string_ostream &KdStream) const;
113
114 /// Decode as directives that handle COMPUTE_PGM_RSRC3.
115 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC3.
116 /// \param KdStream - Stream to write the disassembled directives to.
117 // NOLINTNEXTLINE(readability-identifier-naming)
118 Expected<bool> decodeCOMPUTE_PGM_RSRC3(uint32_t FourByteBuffer,
119 raw_string_ostream &KdStream) const;
120
121 void convertEXPInst(MCInst &MI) const;
122 void convertVINTERPInst(MCInst &MI) const;
123 void convertFMAanyK(MCInst &MI) const;
124 void convertSDWAInst(MCInst &MI) const;
125 void convertMAIInst(MCInst &MI) const;
126 void convertWMMAInst(MCInst &MI) const;
127 void convertDPP8Inst(MCInst &MI) const;
128 void convertMIMGInst(MCInst &MI) const;
129 void convertVOP3DPPInst(MCInst &MI) const;
130 void convertVOP3PDPPInst(MCInst &MI) const;
131 void convertVOPCDPPInst(MCInst &MI) const;
132 void convertVOPC64DPPInst(MCInst &MI) const;
133 void convertMacDPPInst(MCInst &MI) const;
134 void convertTrue16OpSel(MCInst &MI) const;
135
136 unsigned getVgprClassId(unsigned Width) const;
137 unsigned getAgprClassId(unsigned Width) const;
138 unsigned getSgprClassId(unsigned Width) const;
139 unsigned getTtmpClassId(unsigned Width) const;
140
141 static MCOperand decodeIntImmed(unsigned Imm);
142
143 MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const;
144 MCOperand decodeMandatoryLiteral64Constant(uint64_t Imm) const;
145 MCOperand decodeLiteralConstant(const MCInstrDesc &Desc,
146 const MCOperandInfo &OpDesc) const;
147 MCOperand decodeLiteral64Constant() const;
148
149 MCOperand decodeSrcOp(const MCInst &Inst, unsigned Width, unsigned Val) const;
150
151 MCOperand decodeNonVGPRSrcOp(const MCInst &Inst, unsigned Width,
152 unsigned Val) const;
153
154 MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const;
155 MCOperand decodeSpecialReg32(unsigned Val) const;
156 MCOperand decodeSpecialReg64(unsigned Val) const;
157 MCOperand decodeSpecialReg96Plus(unsigned Val) const;
158
159 MCOperand decodeSDWASrc(unsigned Width, unsigned Val) const;
160 MCOperand decodeSDWASrc16(unsigned Val) const;
161 MCOperand decodeSDWASrc32(unsigned Val) const;
162 MCOperand decodeSDWAVopcDst(unsigned Val) const;
163
164 MCOperand decodeBoolReg(const MCInst &Inst, unsigned Val) const;
165 MCOperand decodeSplitBarrier(const MCInst &Inst, unsigned Val) const;
166 MCOperand decodeDpp8FI(unsigned Val) const;
167
168 MCOperand decodeVersionImm(unsigned Imm) const;
169
170 int getTTmpIdx(unsigned Val) const;
171
172 const MCInstrInfo *getMCII() const { return MCII.get(); }
173
174 bool isVI() const;
175 bool isGFX9() const;
176 bool isGFX90A() const;
177 bool isGFX9Plus() const;
178 bool isGFX10() const;
179 bool isGFX10Plus() const;
180 bool isGFX11() const;
181 bool isGFX11Plus() const;
182 bool isGFX12() const;
183 bool isGFX12Plus() const;
184 bool isGFX1250() const;
185 bool isGFX1250Plus() const;
186 bool isGFX13() const;
187 bool isGFX13Plus() const;
188
189 bool hasArchitectedFlatScratch() const;
190 bool hasKernargPreload() const;
191
192 bool isMacDPP(MCInst &MI) const;
193
194 /// Check if the instruction is a buffer operation (MUBUF, MTBUF, or S_BUFFER)
195 bool isBufferInstruction(const MCInst &MI) const;
196};
197
198//===----------------------------------------------------------------------===//
199// AMDGPUSymbolizer
200//===----------------------------------------------------------------------===//
201
202class AMDGPUSymbolizer : public MCSymbolizer {
203private:
204 void *DisInfo;
205 std::vector<uint64_t> ReferencedAddresses;
206
207public:
208 AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
209 void *disInfo)
210 : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
211
212 bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
213 int64_t Value, uint64_t Address, bool IsBranch,
214 uint64_t Offset, uint64_t OpSize,
215 uint64_t InstSize) override;
216
217 void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
218 int64_t Value,
219 uint64_t Address) override;
220
221 ArrayRef<uint64_t> getReferencedAddresses() const override {
222 return ReferencedAddresses;
223 }
224};
225
226} // end namespace llvm
227
228#endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
229