1//===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10///
11/// This file contains declaration for AMDGPU ISA disassembler
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
16#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17
18#include "SIDefines.h"
19#include "llvm/ADT/APInt.h"
20#include "llvm/ADT/SmallString.h"
21#include "llvm/MC/MCDisassembler/MCDisassembler.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/Support/DataExtractor.h"
25#include <memory>
26
27namespace llvm {
28
29class MCAsmInfo;
30class MCInst;
31class MCOperand;
32class MCSubtargetInfo;
33class Twine;
34
35//===----------------------------------------------------------------------===//
36// AMDGPUDisassembler
37//===----------------------------------------------------------------------===//
38
39class AMDGPUDisassembler : public MCDisassembler {
40private:
41 std::unique_ptr<MCInstrInfo const> const MCII;
42 const MCRegisterInfo &MRI;
43 const MCAsmInfo &MAI;
44 const unsigned HwModeRegClass;
45 const unsigned TargetMaxInstBytes;
46 mutable ArrayRef<uint8_t> Bytes;
47 mutable uint64_t Literal;
48 mutable bool HasLiteral;
49 mutable std::optional<bool> EnableWavefrontSize32;
50
51 // If the object's ELF e_flags enable xnack. TODO: Replace with TargetID
52 mutable bool XnackOnFromEFlags = false;
53 unsigned CodeObjectVersion;
54 const MCExpr *UCVersionW64Expr;
55 const MCExpr *UCVersionW32Expr;
56 const MCExpr *UCVersionMDPExpr;
57
58 const MCExpr *createConstantSymbolExpr(StringRef Id, int64_t Val);
59
60 bool decodeImmOperands(MCInst &MI, const MCInstrInfo &MCII) const;
61
62public:
63 AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
64 MCInstrInfo const *MCII);
65 ~AMDGPUDisassembler() override = default;
66
67 void setABIVersion(unsigned Version) override;
68
69 void emitTargetIDIfSupported(raw_ostream &OS, unsigned EFlags) const override;
70
71 DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
72 ArrayRef<uint8_t> Bytes, uint64_t Address,
73 raw_ostream &CS) const override;
74
75 const char* getRegClassName(unsigned RegClassID) const;
76
77 MCOperand createRegOperand(MCRegister Reg) const;
78 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
79 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
80 MCOperand createVGPR16Operand(unsigned RegIdx, bool IsHi) const;
81
82 MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
83
84 template <typename InsnType>
85 DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst,
86 uint64_t Address, raw_ostream &Comments) const;
87 template <typename InsnType>
88 DecodeStatus tryDecodeInst(const uint8_t *Table1, const uint8_t *Table2,
89 MCInst &MI, InsnType Inst, uint64_t Address,
90 raw_ostream &Comments) const;
91
92 Expected<bool> onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size,
93 ArrayRef<uint8_t> Bytes,
94 uint64_t Address) const override;
95
96 Expected<bool> decodeKernelDescriptor(StringRef KdName,
97 ArrayRef<uint8_t> Bytes,
98 uint64_t KdAddress) const;
99
100 Expected<bool>
101 decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor,
102 ArrayRef<uint8_t> Bytes,
103 raw_string_ostream &KdStream) const;
104
105 /// Decode as directives that handle COMPUTE_PGM_RSRC1.
106 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC1.
107 /// \param KdStream - Stream to write the disassembled directives to.
108 // NOLINTNEXTLINE(readability-identifier-naming)
109 Expected<bool> decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer,
110 raw_string_ostream &KdStream) const;
111
112 /// Decode as directives that handle COMPUTE_PGM_RSRC2.
113 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC2.
114 /// \param KdStream - Stream to write the disassembled directives to.
115 // NOLINTNEXTLINE(readability-identifier-naming)
116 Expected<bool> decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer,
117 raw_string_ostream &KdStream) const;
118
119 /// Decode as directives that handle COMPUTE_PGM_RSRC3.
120 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC3.
121 /// \param KdStream - Stream to write the disassembled directives to.
122 // NOLINTNEXTLINE(readability-identifier-naming)
123 Expected<bool> decodeCOMPUTE_PGM_RSRC3(uint32_t FourByteBuffer,
124 raw_string_ostream &KdStream) const;
125
126 void convertEXPInst(MCInst &MI) const;
127 void convertVINTERPInst(MCInst &MI) const;
128 void convertFMAanyK(MCInst &MI) const;
129 void convertSDWAInst(MCInst &MI) const;
130 bool convertMAIInst(MCInst &MI) const;
131 bool convertWMMAInst(MCInst &MI) const;
132 void convertDPP8Inst(MCInst &MI) const;
133 void convertMIMGInst(MCInst &MI) const;
134 void convertVOP3DPPInst(MCInst &MI) const;
135 void convertVOP3PDPPInst(MCInst &MI) const;
136 void convertVOPCDPPInst(MCInst &MI) const;
137 void convertVOPC64DPPInst(MCInst &MI) const;
138 void convertMacDPPInst(MCInst &MI) const;
139 void convertTrue16OpSel(MCInst &MI) const;
140
141 unsigned getVgprClassId(unsigned Width) const;
142 unsigned getAgprClassId(unsigned Width) const;
143
144 /// Return the SGPR/TTMP register class accepted by source decoding for
145 /// \p Width, or std::nullopt if that width has no supported encoding.
146 std::optional<unsigned> getSgprClassId(unsigned Width) const;
147 std::optional<unsigned> getTtmpClassId(unsigned Width) const;
148
149 static MCOperand decodeIntImmed(unsigned Imm);
150
151 MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const;
152 MCOperand decodeMandatoryLiteral64Constant(uint64_t Imm) const;
153 MCOperand decodeLiteralConstant(const MCInstrDesc &Desc,
154 const MCOperandInfo &OpDesc) const;
155 MCOperand decodeLiteral64Constant() const;
156
157 MCOperand decodeSrcOp(const MCInst &Inst, unsigned Width, unsigned Val) const;
158
159 MCOperand decodeNonVGPRSrcOp(const MCInst &Inst, unsigned Width,
160 unsigned Val) const;
161
162 MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const;
163 MCOperand decodeSpecialReg32(unsigned Val) const;
164 MCOperand decodeSpecialReg64(unsigned Val) const;
165 MCOperand decodeSpecialReg96Plus(unsigned Val) const;
166
167 MCOperand decodeSDWASrc(unsigned Width, unsigned Val) const;
168 MCOperand decodeSDWASrc16(unsigned Val) const;
169 MCOperand decodeSDWASrc32(unsigned Val) const;
170 MCOperand decodeSDWAVopcDst(unsigned Val) const;
171
172 MCOperand decodeBoolReg(const MCInst &Inst, unsigned Val) const;
173 MCOperand decodeSplitBarrier(const MCInst &Inst, unsigned Val) const;
174 MCOperand decodeDpp8FI(unsigned Val) const;
175
176 MCOperand decodeVersionImm(unsigned Imm) const;
177
178 int getTTmpIdx(unsigned Val) const;
179
180 const MCInstrInfo *getMCII() const { return MCII.get(); }
181
182 bool isVI() const;
183 bool isGFX9() const;
184 bool isGFX90A() const;
185 bool isGFX9Plus() const;
186 bool isGFX10() const;
187 bool isGFX10Plus() const;
188 bool isGFX11() const;
189 bool isGFX1170() const;
190 bool isGFX11Plus() const;
191 bool isGFX12() const;
192 bool isGFX12Plus() const;
193 bool isGFX1250() const;
194 bool isGFX1250Plus() const;
195 bool isGFX13() const;
196 bool isGFX13Plus() const;
197
198 bool hasArchitectedFlatScratch() const;
199 bool hasKernargPreload() const;
200
201 bool isMacDPP(MCInst &MI) const;
202
203 /// Check if the instruction is a buffer operation (MUBUF, MTBUF, or S_BUFFER)
204 bool isBufferInstruction(const MCInst &MI) const;
205};
206
207//===----------------------------------------------------------------------===//
208// AMDGPUSymbolizer
209//===----------------------------------------------------------------------===//
210
211class AMDGPUSymbolizer : public MCSymbolizer {
212private:
213 void *DisInfo;
214 std::vector<uint64_t> ReferencedAddresses;
215
216public:
217 AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
218 void *disInfo)
219 : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
220
221 bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
222 int64_t Value, uint64_t Address, bool IsBranch,
223 uint64_t Offset, uint64_t OpSize,
224 uint64_t InstSize) override;
225
226 void tryAddingPcLoadReferenceComment(raw_ostream &cStream,
227 int64_t Value,
228 uint64_t Address) override;
229
230 ArrayRef<uint64_t> getReferencedAddresses() const override {
231 return ReferencedAddresses;
232 }
233};
234
235} // end namespace llvm
236
237#endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
238