1//===-- MCTargetDesc/AMDGPUMCAsmInfo.cpp - Assembly Info ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#include "AMDGPUMCAsmInfo.h"
11#include "MCTargetDesc/AMDGPUMCExpr.h"
12#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13#include "llvm/MC/MCExpr.h"
14#include "llvm/MC/MCSubtargetInfo.h"
15#include "llvm/TargetParser/Triple.h"
16
17using namespace llvm;
18
19const MCAsmInfo::AtSpecifier atSpecifiers[] = {
20 {.Kind: AMDGPUMCExpr::S_GOTPCREL, .Name: "gotpcrel"},
21 {.Kind: AMDGPUMCExpr::S_GOTPCREL32_LO, .Name: "gotpcrel32@lo"},
22 {.Kind: AMDGPUMCExpr::S_GOTPCREL32_HI, .Name: "gotpcrel32@hi"},
23 {.Kind: AMDGPUMCExpr::S_REL32_LO, .Name: "rel32@lo"},
24 {.Kind: AMDGPUMCExpr::S_REL32_HI, .Name: "rel32@hi"},
25 {.Kind: AMDGPUMCExpr::S_REL64, .Name: "rel64"},
26 {.Kind: AMDGPUMCExpr::S_ABS32_LO, .Name: "abs32@lo"},
27 {.Kind: AMDGPUMCExpr::S_ABS32_HI, .Name: "abs32@hi"},
28 {.Kind: AMDGPUMCExpr::S_ABS64, .Name: "abs64"},
29};
30
31AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT,
32 const MCTargetOptions &Options)
33 : MCAsmInfoELF(Options) {
34 CodePointerSize = (TT.isAMDGCN()) ? 8 : 4;
35 StackGrowsUp = true;
36 HasSingleParameterDotFile = false;
37 //===------------------------------------------------------------------===//
38 MinInstAlignment = 4;
39
40 // This is the maximum instruction encoded size for gfx10. With a known
41 // subtarget, it can be reduced to 8 bytes.
42 MaxInstLength = (TT.isAMDGCN()) ? 20 : 16;
43 SeparatorString = "\n";
44 CommentString = ";";
45 InlineAsmStart = ";#ASMSTART";
46 InlineAsmEnd = ";#ASMEND";
47 UsesSetToEquateSymbol = true;
48
49 //===--- Data Emission Directives -------------------------------------===//
50 UsesELFSectionDirectiveForBSS = true;
51
52 //===--- Global Variable Emission Directives --------------------------===//
53 COMMDirectiveAlignmentIsInBytes = false;
54 HasNoDeadStrip = true;
55 //===--- Dwarf Emission Directives -----------------------------------===//
56 SupportsDebugInformation = true;
57 UsesCFIWithoutEH = true;
58 DwarfRegNumForCFI = true;
59
60 UseIntegratedAssembler = false;
61 initializeAtSpecifiers(atSpecifiers);
62}
63
64bool AMDGPUMCAsmInfo::shouldOmitSectionDirective(StringRef SectionName) const {
65 return SectionName == ".hsatext" || SectionName == ".hsadata_global_agent" ||
66 SectionName == ".hsadata_global_program" ||
67 SectionName == ".hsarodata_readonly_agent" ||
68 MCAsmInfo::shouldOmitSectionDirective(SectionName);
69}
70
71unsigned AMDGPUMCAsmInfo::getMaxInstLength(const MCSubtargetInfo *STI) const {
72 if (!STI || STI->getTargetTriple().getArch() == Triple::r600)
73 return MaxInstLength;
74
75 // Maximum for NSA encoded images
76 if (STI->hasFeature(Feature: AMDGPU::FeatureNSAEncoding))
77 return 20;
78
79 // VOP3PX/VOP3PX2 encoding.
80 if (STI->hasFeature(Feature: AMDGPU::FeatureGFX950Insts) ||
81 STI->hasFeature(Feature: AMDGPU::FeatureGFX1250Insts))
82 return 16;
83
84 // 64-bit instruction with 32-bit literal.
85 if (STI->hasFeature(Feature: AMDGPU::FeatureVOP3Literal))
86 return 12;
87
88 return 8;
89}
90