1//===-- MCTargetDesc/AMDGPUMCAsmInfo.cpp - Assembly Info ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#include "AMDGPUMCAsmInfo.h"
11#include "MCTargetDesc/AMDGPUMCExpr.h"
12#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13#include "llvm/MC/MCExpr.h"
14#include "llvm/MC/MCSubtargetInfo.h"
15#include "llvm/TargetParser/Triple.h"
16
17using namespace llvm;
18
19const MCAsmInfo::AtSpecifier atSpecifiers[] = {
20 {.Kind: AMDGPUMCExpr::S_GOTPCREL, .Name: "gotpcrel"},
21 {.Kind: AMDGPUMCExpr::S_GOTPCREL32_LO, .Name: "gotpcrel32@lo"},
22 {.Kind: AMDGPUMCExpr::S_GOTPCREL32_HI, .Name: "gotpcrel32@hi"},
23 {.Kind: AMDGPUMCExpr::S_REL32_LO, .Name: "rel32@lo"},
24 {.Kind: AMDGPUMCExpr::S_REL32_HI, .Name: "rel32@hi"},
25 {.Kind: AMDGPUMCExpr::S_REL64, .Name: "rel64"},
26 {.Kind: AMDGPUMCExpr::S_ABS32_LO, .Name: "abs32@lo"},
27 {.Kind: AMDGPUMCExpr::S_ABS32_HI, .Name: "abs32@hi"},
28 {.Kind: AMDGPUMCExpr::S_ABS64, .Name: "abs64"},
29};
30
31AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT,
32 const MCTargetOptions &Options) {
33 CodePointerSize = (TT.isAMDGCN()) ? 8 : 4;
34 StackGrowsUp = true;
35 HasSingleParameterDotFile = false;
36 //===------------------------------------------------------------------===//
37 MinInstAlignment = 4;
38
39 // This is the maximum instruction encoded size for gfx10. With a known
40 // subtarget, it can be reduced to 8 bytes.
41 MaxInstLength = (TT.isAMDGCN()) ? 20 : 16;
42 SeparatorString = "\n";
43 CommentString = ";";
44 InlineAsmStart = ";#ASMSTART";
45 InlineAsmEnd = ";#ASMEND";
46 UsesSetToEquateSymbol = true;
47
48 //===--- Data Emission Directives -------------------------------------===//
49 UsesELFSectionDirectiveForBSS = true;
50
51 //===--- Global Variable Emission Directives --------------------------===//
52 COMMDirectiveAlignmentIsInBytes = false;
53 HasNoDeadStrip = true;
54 //===--- Dwarf Emission Directives -----------------------------------===//
55 SupportsDebugInformation = true;
56 UsesCFIWithoutEH = true;
57 DwarfRegNumForCFI = true;
58
59 UseIntegratedAssembler = false;
60 initializeAtSpecifiers(atSpecifiers);
61}
62
63bool AMDGPUMCAsmInfo::shouldOmitSectionDirective(StringRef SectionName) const {
64 return SectionName == ".hsatext" || SectionName == ".hsadata_global_agent" ||
65 SectionName == ".hsadata_global_program" ||
66 SectionName == ".hsarodata_readonly_agent" ||
67 MCAsmInfo::shouldOmitSectionDirective(SectionName);
68}
69
70unsigned AMDGPUMCAsmInfo::getMaxInstLength(const MCSubtargetInfo *STI) const {
71 if (!STI || STI->getTargetTriple().getArch() == Triple::r600)
72 return MaxInstLength;
73
74 // Maximum for NSA encoded images
75 if (STI->hasFeature(Feature: AMDGPU::FeatureNSAEncoding))
76 return 20;
77
78 // VOP3PX/VOP3PX2 encoding.
79 if (STI->hasFeature(Feature: AMDGPU::FeatureGFX950Insts) ||
80 STI->hasFeature(Feature: AMDGPU::FeatureGFX1250Insts))
81 return 16;
82
83 // 64-bit instruction with 32-bit literal.
84 if (STI->hasFeature(Feature: AMDGPU::FeatureVOP3Literal))
85 return 12;
86
87 return 8;
88}
89