1//===-- AMDGPUPALMetadata.cpp - Accumulate and print AMDGPU PAL metadata -===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10///
11/// This class has methods called by AMDGPUAsmPrinter to accumulate and print
12/// the PAL metadata.
13//
14//===----------------------------------------------------------------------===//
15//
16
17#include "AMDGPUPALMetadata.h"
18#include "AMDGPUPTNote.h"
19#include "SIDefines.h"
20#include "llvm/ADT/Enum.h"
21#include "llvm/BinaryFormat/ELF.h"
22#include "llvm/IR/Constants.h"
23#include "llvm/IR/Module.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/Support/AMDGPUMetadata.h"
26#include "llvm/Support/EndianStream.h"
27#include "llvm/Support/VersionTuple.h"
28
29using namespace llvm;
30using namespace llvm::AMDGPU;
31
32// Return the PAL metadata hardware shader stage name.
33static const char *getStageName(CallingConv::ID CC) {
34 switch (CC) {
35 case CallingConv::AMDGPU_PS:
36 return ".ps";
37 case CallingConv::AMDGPU_VS:
38 return ".vs";
39 case CallingConv::AMDGPU_GS:
40 return ".gs";
41 case CallingConv::AMDGPU_ES:
42 return ".es";
43 case CallingConv::AMDGPU_HS:
44 return ".hs";
45 case CallingConv::AMDGPU_LS:
46 return ".ls";
47 case CallingConv::AMDGPU_Gfx:
48 case CallingConv::AMDGPU_Gfx_WholeWave:
49 llvm_unreachable("Callable shader has no hardware stage");
50 default:
51 return ".cs";
52 }
53}
54
55// Read the PAL metadata from IR metadata, where it was put by the frontend.
56void AMDGPUPALMetadata::readFromIR(Module &M) {
57 auto *NamedMD = M.getNamedMetadata(Name: "amdgpu.pal.metadata.msgpack");
58 if (NamedMD && NamedMD->getNumOperands()) {
59 // This is the new msgpack format for metadata. It is a NamedMD containing
60 // an MDTuple containing an MDString containing the msgpack data.
61 BlobType = ELF::NT_AMDGPU_METADATA;
62 auto *MDN = dyn_cast<MDTuple>(Val: NamedMD->getOperand(i: 0));
63 if (MDN && MDN->getNumOperands()) {
64 if (auto *MDS = dyn_cast<MDString>(Val: MDN->getOperand(I: 0)))
65 setFromMsgPackBlob(MDS->getString());
66 }
67 return;
68 }
69 BlobType = ELF::NT_AMD_PAL_METADATA;
70 NamedMD = M.getNamedMetadata(Name: "amdgpu.pal.metadata");
71 if (!NamedMD || !NamedMD->getNumOperands()) {
72 // Emit msgpack metadata by default
73 BlobType = ELF::NT_AMDGPU_METADATA;
74 return;
75 }
76 // This is the old reg=value pair format for metadata. It is a NamedMD
77 // containing an MDTuple containing a number of MDNodes each of which is an
78 // integer value, and each two integer values forms a key=value pair that we
79 // store as Registers[key]=value in the map.
80 auto *Tuple = dyn_cast<MDTuple>(Val: NamedMD->getOperand(i: 0));
81 if (!Tuple)
82 return;
83 for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
84 auto *Key = mdconst::dyn_extract<ConstantInt>(MD: Tuple->getOperand(I));
85 auto *Val = mdconst::dyn_extract<ConstantInt>(MD: Tuple->getOperand(I: I + 1));
86 if (!Key || !Val)
87 continue;
88 setRegister(Reg: Key->getZExtValue(), Val: Val->getZExtValue());
89 }
90}
91
92// Set PAL metadata from msgpack blob.
93bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) {
94 return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false);
95}
96
97// Given the calling convention, calculate the register number for rsrc1. In
98// principle the register number could change in future hardware, but we know
99// it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
100// we can use fixed values.
101static unsigned getRsrc1Reg(CallingConv::ID CC) {
102 switch (CC) {
103 default:
104 return PALMD::R_2E12_COMPUTE_PGM_RSRC1;
105 case CallingConv::AMDGPU_LS:
106 return PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS;
107 case CallingConv::AMDGPU_HS:
108 return PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS;
109 case CallingConv::AMDGPU_ES:
110 return PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES;
111 case CallingConv::AMDGPU_GS:
112 return PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS;
113 case CallingConv::AMDGPU_VS:
114 return PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS;
115 case CallingConv::AMDGPU_PS:
116 return PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS;
117 }
118}
119
120// Calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
121// with a constant offset to access any non-register shader-specific PAL
122// metadata key.
123static unsigned getScratchSizeKey(CallingConv::ID CC) {
124 switch (CC) {
125 case CallingConv::AMDGPU_PS:
126 return PALMD::Key::PS_SCRATCH_SIZE;
127 case CallingConv::AMDGPU_VS:
128 return PALMD::Key::VS_SCRATCH_SIZE;
129 case CallingConv::AMDGPU_GS:
130 return PALMD::Key::GS_SCRATCH_SIZE;
131 case CallingConv::AMDGPU_ES:
132 return PALMD::Key::ES_SCRATCH_SIZE;
133 case CallingConv::AMDGPU_HS:
134 return PALMD::Key::HS_SCRATCH_SIZE;
135 case CallingConv::AMDGPU_LS:
136 return PALMD::Key::LS_SCRATCH_SIZE;
137 default:
138 return PALMD::Key::CS_SCRATCH_SIZE;
139 }
140}
141
142// Set the rsrc1 register in the metadata for a particular shader stage.
143// In fact this ORs the value into any previous setting of the register.
144void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, unsigned Val) {
145 setRegister(Reg: getRsrc1Reg(CC), Val);
146}
147
148void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, const MCExpr *Val,
149 MCContext &Ctx) {
150 setRegister(Reg: getRsrc1Reg(CC), Val, Ctx);
151}
152
153// Set the rsrc2 register in the metadata for a particular shader stage.
154// In fact this ORs the value into any previous setting of the register.
155void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, unsigned Val) {
156 setRegister(Reg: getRsrc1Reg(CC) + 1, Val);
157}
158
159void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, const MCExpr *Val,
160 MCContext &Ctx) {
161 setRegister(Reg: getRsrc1Reg(CC) + 1, Val, Ctx);
162}
163
164// Set the SPI_PS_INPUT_ENA register in the metadata.
165// In fact this ORs the value into any previous setting of the register.
166void AMDGPUPALMetadata::setSpiPsInputEna(unsigned Val) {
167 setRegister(Reg: PALMD::R_A1B3_SPI_PS_INPUT_ENA, Val);
168}
169
170// Set the SPI_PS_INPUT_ADDR register in the metadata.
171// In fact this ORs the value into any previous setting of the register.
172void AMDGPUPALMetadata::setSpiPsInputAddr(unsigned Val) {
173 setRegister(Reg: PALMD::R_A1B4_SPI_PS_INPUT_ADDR, Val);
174}
175
176// Get a register from the metadata, or 0 if not currently set.
177unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) {
178 auto Regs = getRegisters();
179 auto It = Regs.find(Key: MsgPackDoc.getNode(V: Reg));
180 if (It == Regs.end())
181 return 0;
182 auto N = It->second;
183 if (N.getKind() != msgpack::Type::UInt)
184 return 0;
185 return N.getUInt();
186}
187
188// Set a register in the metadata.
189// In fact this ORs the value into any previous setting of the register.
190void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) {
191 if (!isLegacy()) {
192 // In the new MsgPack format, ignore register numbered >= 0x10000000. It
193 // is a PAL ABI pseudo-register in the old non-MsgPack format.
194 if (Reg >= 0x10000000)
195 return;
196 }
197 auto &N = getRegisters()[MsgPackDoc.getNode(V: Reg)];
198 if (N.getKind() == msgpack::Type::UInt)
199 Val |= N.getUInt();
200 N = N.getDocument()->getNode(V: Val);
201}
202
203// Set a register in the metadata.
204// In fact this ORs the value into any previous setting of the register.
205void AMDGPUPALMetadata::setRegister(unsigned Reg, const MCExpr *Val,
206 MCContext &Ctx) {
207 if (!isLegacy()) {
208 // In the new MsgPack format, ignore register numbered >= 0x10000000. It
209 // is a PAL ABI pseudo-register in the old non-MsgPack format.
210 if (Reg >= 0x10000000)
211 return;
212 }
213 auto &N = getRegisters()[MsgPackDoc.getNode(V: Reg)];
214 auto [ExprIt, Inserted] = REM.try_emplace(Key: Reg);
215
216 if (!Inserted) {
217 Val = MCBinaryExpr::createOr(LHS: Val, RHS: ExprIt->getSecond(), Ctx);
218 // This conditional may be redundant most of the time, but the alternate
219 // setRegister(unsigned, unsigned) could've been called while the
220 // conditional returns true (i.e., Reg exists in REM).
221 if (N.getKind() == msgpack::Type::UInt) {
222 const MCExpr *NExpr = MCConstantExpr::create(Value: N.getUInt(), Ctx);
223 Val = MCBinaryExpr::createOr(LHS: Val, RHS: NExpr, Ctx);
224 }
225 } else if (N.getKind() == msgpack::Type::UInt) {
226 const MCExpr *NExpr = MCConstantExpr::create(Value: N.getUInt(), Ctx);
227 Val = MCBinaryExpr::createOr(LHS: Val, RHS: NExpr, Ctx);
228 } else {
229 // Default to uint64_t 0 so additional calls to setRegister will allow
230 // propagate ORs.
231 N = (uint64_t)0;
232 }
233 ExprIt->second = Val;
234 DelayedExprs.assignDocNode(DN&: N, Type: msgpack::Type::UInt, ExprValue: Val);
235}
236
237// Set the entry point name for one shader.
238void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) {
239 if (isLegacy())
240 return;
241 // Msgpack format.
242 // Entry point is updated to .entry_point_symbol and is set to the function
243 // name
244 getHwStage(CC)[".entry_point_symbol"] =
245 MsgPackDoc.getNode(V: Name, /*Copy=*/true);
246
247 // For PAL version 3.6 and above, entry_point is no longer required.
248 if (getPALVersion() < VersionTuple(3, 6)) {
249 // Set .entry_point which is defined to be _amdgpu_<stage>_main and
250 // _amdgpu_cs_main for non-shader functions.
251 SmallString<16> EPName("_amdgpu_");
252 raw_svector_ostream EPNameOS(EPName);
253 EPNameOS << getStageName(CC) + 1 << "_main";
254 getHwStage(CC)[".entry_point"] =
255 MsgPackDoc.getNode(V: EPNameOS.str(), /*Copy=*/true);
256 }
257}
258
259// Set the number of used vgprs in the metadata. This is an optional
260// advisory record for logging etc; wave dispatch actually uses the rsrc1
261// register for the shader stage to determine the number of vgprs to
262// allocate.
263void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, unsigned Val) {
264 if (isLegacy()) {
265 // Old non-msgpack format.
266 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) +
267 PALMD::Key::VS_NUM_USED_VGPRS -
268 PALMD::Key::VS_SCRATCH_SIZE;
269 setRegister(Reg: NumUsedVgprsKey, Val);
270 return;
271 }
272 // Msgpack format.
273 getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(V: Val);
274}
275
276void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, const MCExpr *Val,
277 MCContext &Ctx) {
278 if (isLegacy()) {
279 // Old non-msgpack format.
280 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) +
281 PALMD::Key::VS_NUM_USED_VGPRS -
282 PALMD::Key::VS_SCRATCH_SIZE;
283 setRegister(Reg: NumUsedVgprsKey, Val, Ctx);
284 return;
285 }
286 // Msgpack format.
287 setHwStage(CC, field: ".vgpr_count", Type: msgpack::Type::UInt, Val);
288}
289
290// Set the number of used agprs in the metadata.
291void AMDGPUPALMetadata::setNumUsedAgprs(CallingConv::ID CC, unsigned Val) {
292 getHwStage(CC)[".agpr_count"] = Val;
293}
294
295void AMDGPUPALMetadata::setNumUsedAgprs(unsigned CC, const MCExpr *Val) {
296 setHwStage(CC, field: ".agpr_count", Type: msgpack::Type::UInt, Val);
297}
298
299// Set the number of used sgprs in the metadata. This is an optional advisory
300// record for logging etc; wave dispatch actually uses the rsrc1 register for
301// the shader stage to determine the number of sgprs to allocate.
302void AMDGPUPALMetadata::setNumUsedSgprs(CallingConv::ID CC, unsigned Val) {
303 if (isLegacy()) {
304 // Old non-msgpack format.
305 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) +
306 PALMD::Key::VS_NUM_USED_SGPRS -
307 PALMD::Key::VS_SCRATCH_SIZE;
308 setRegister(Reg: NumUsedSgprsKey, Val);
309 return;
310 }
311 // Msgpack format.
312 getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(V: Val);
313}
314
315void AMDGPUPALMetadata::setNumUsedSgprs(unsigned CC, const MCExpr *Val,
316 MCContext &Ctx) {
317 if (isLegacy()) {
318 // Old non-msgpack format.
319 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) +
320 PALMD::Key::VS_NUM_USED_SGPRS -
321 PALMD::Key::VS_SCRATCH_SIZE;
322 setRegister(Reg: NumUsedSgprsKey, Val, Ctx);
323 return;
324 }
325 // Msgpack format.
326 setHwStage(CC, field: ".sgpr_count", Type: msgpack::Type::UInt, Val);
327}
328
329// Set the scratch size in the metadata.
330void AMDGPUPALMetadata::setScratchSize(CallingConv::ID CC, unsigned Val) {
331 if (isLegacy()) {
332 // Old non-msgpack format.
333 setRegister(Reg: getScratchSizeKey(CC), Val);
334 return;
335 }
336 // Msgpack format.
337 getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(V: Val);
338}
339
340void AMDGPUPALMetadata::setScratchSize(unsigned CC, const MCExpr *Val,
341 MCContext &Ctx) {
342 if (isLegacy()) {
343 // Old non-msgpack format.
344 setRegister(Reg: getScratchSizeKey(CC), Val, Ctx);
345 return;
346 }
347 // Msgpack format.
348 setHwStage(CC, field: ".scratch_memory_size", Type: msgpack::Type::UInt, Val);
349}
350
351// Set the stack frame size of a function in the metadata.
352void AMDGPUPALMetadata::setFunctionScratchSize(StringRef FnName, unsigned Val) {
353 auto Node = getShaderFunction(Name: FnName);
354 Node[".stack_frame_size_in_bytes"] = MsgPackDoc.getNode(V: Val);
355 Node[".backend_stack_size"] = MsgPackDoc.getNode(V: Val);
356}
357
358// Set the amount of LDS used in bytes in the metadata.
359void AMDGPUPALMetadata::setFunctionLdsSize(StringRef FnName, unsigned Val) {
360 auto Node = getShaderFunction(Name: FnName);
361 Node[".lds_size"] = MsgPackDoc.getNode(V: Val);
362}
363
364// Set the number of used vgprs in the metadata.
365void AMDGPUPALMetadata::setFunctionNumUsedVgprs(StringRef FnName,
366 unsigned Val) {
367 auto Node = getShaderFunction(Name: FnName);
368 Node[".vgpr_count"] = MsgPackDoc.getNode(V: Val);
369}
370
371void AMDGPUPALMetadata::setFunctionNumUsedVgprs(StringRef FnName,
372 const MCExpr *Val) {
373 auto Node = getShaderFunction(Name: FnName);
374 DelayedExprs.assignDocNode(DN&: Node[".vgpr_count"], Type: msgpack::Type::UInt, ExprValue: Val);
375}
376
377// Set the number of used vgprs in the metadata.
378void AMDGPUPALMetadata::setFunctionNumUsedSgprs(StringRef FnName,
379 unsigned Val) {
380 auto Node = getShaderFunction(Name: FnName);
381 Node[".sgpr_count"] = MsgPackDoc.getNode(V: Val);
382}
383
384void AMDGPUPALMetadata::setFunctionNumUsedSgprs(StringRef FnName,
385 const MCExpr *Val) {
386 auto Node = getShaderFunction(Name: FnName);
387 DelayedExprs.assignDocNode(DN&: Node[".sgpr_count"], Type: msgpack::Type::UInt, ExprValue: Val);
388}
389
390// Set the hardware register bit in PAL metadata to enable wave32 on the
391// shader of the given calling convention.
392void AMDGPUPALMetadata::setWave32(unsigned CC) {
393 switch (CC) {
394 case CallingConv::AMDGPU_HS:
395 setRegister(Reg: PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_HS_W32_EN(1));
396 break;
397 case CallingConv::AMDGPU_GS:
398 setRegister(Reg: PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_GS_W32_EN(1));
399 break;
400 case CallingConv::AMDGPU_VS:
401 setRegister(Reg: PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_VS_W32_EN(1));
402 break;
403 case CallingConv::AMDGPU_PS:
404 setRegister(Reg: PALMD::R_A1B6_SPI_PS_IN_CONTROL, S_0286D8_PS_W32_EN(1));
405 break;
406 case CallingConv::AMDGPU_CS:
407 setRegister(Reg: PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR,
408 S_00B800_CS_W32_EN(1));
409 break;
410 }
411}
412
413// Convert a register number to name, for display by toString().
414// Returns nullptr if none.
415static StringRef getRegisterName(unsigned RegNum) {
416 // Table of registers.
417 constexpr EnumStringDef<uint16_t> RegInfoTableDefs[] = {
418 // Registers that code generation sets/modifies metadata for.
419 {.Names: {"SPI_SHADER_PGM_RSRC1_VS"}, .Value: PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS},
420 {.Names: {"SPI_SHADER_PGM_RSRC2_VS"}, .Value: PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1},
421 {.Names: {"SPI_SHADER_PGM_RSRC1_LS"}, .Value: PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS},
422 {.Names: {"SPI_SHADER_PGM_RSRC2_LS"}, .Value: PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1},
423 {.Names: {"SPI_SHADER_PGM_RSRC1_HS"}, .Value: PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS},
424 {.Names: {"SPI_SHADER_PGM_RSRC2_HS"}, .Value: PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1},
425 {.Names: {"SPI_SHADER_PGM_RSRC1_ES"}, .Value: PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES},
426 {.Names: {"SPI_SHADER_PGM_RSRC2_ES"}, .Value: PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1},
427 {.Names: {"SPI_SHADER_PGM_RSRC1_GS"}, .Value: PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS},
428 {.Names: {"SPI_SHADER_PGM_RSRC2_GS"}, .Value: PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1},
429 {.Names: {"COMPUTE_DISPATCH_INITIATOR"},
430 .Value: PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR},
431 {.Names: {"COMPUTE_PGM_RSRC1"}, .Value: PALMD::R_2E12_COMPUTE_PGM_RSRC1},
432 {.Names: {"COMPUTE_PGM_RSRC2"}, .Value: PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1},
433 {.Names: {"SPI_SHADER_PGM_RSRC1_PS"}, .Value: PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS},
434 {.Names: {"SPI_SHADER_PGM_RSRC2_PS"}, .Value: PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1},
435 {.Names: {"SPI_PS_INPUT_ENA"}, .Value: PALMD::R_A1B3_SPI_PS_INPUT_ENA},
436 {.Names: {"SPI_PS_INPUT_ADDR"}, .Value: PALMD::R_A1B4_SPI_PS_INPUT_ADDR},
437 {.Names: {"SPI_PS_IN_CONTROL"}, .Value: PALMD::R_A1B6_SPI_PS_IN_CONTROL},
438 {.Names: {"VGT_SHADER_STAGES_EN"}, .Value: PALMD::R_A2D5_VGT_SHADER_STAGES_EN},
439
440 // Registers not known to code generation.
441 {.Names: {"SPI_SHADER_PGM_RSRC3_PS"}, .Value: 0x2c07},
442 {.Names: {"SPI_SHADER_PGM_RSRC3_VS"}, .Value: 0x2c46},
443 {.Names: {"SPI_SHADER_PGM_RSRC3_GS"}, .Value: 0x2c87},
444 {.Names: {"SPI_SHADER_PGM_RSRC3_ES"}, .Value: 0x2cc7},
445 {.Names: {"SPI_SHADER_PGM_RSRC3_HS"}, .Value: 0x2d07},
446 {.Names: {"SPI_SHADER_PGM_RSRC3_LS"}, .Value: 0x2d47},
447
448 {.Names: {"SPI_SHADER_POS_FORMAT"}, .Value: 0xa1c3},
449 {.Names: {"SPI_VS_OUT_CONFIG"}, .Value: 0xa1b1},
450 {.Names: {"PA_CL_VS_OUT_CNTL"}, .Value: 0xa207},
451 {.Names: {"PA_CL_CLIP_CNTL"}, .Value: 0xa204},
452 {.Names: {"PA_CL_VTE_CNTL"}, .Value: 0xa206},
453 {.Names: {"PA_SU_VTX_CNTL"}, .Value: 0xa2f9},
454 {.Names: {"PA_SC_MODE_CNTL_1"}, .Value: 0xa293},
455 {.Names: {"VGT_PRIMITIVEID_EN"}, .Value: 0xa2a1},
456 {.Names: {"SPI_SHADER_PGM_RSRC4_GS"}, .Value: 0x2c81},
457 {.Names: {"COMPUTE_TMPRING_SIZE"}, .Value: 0x2e18},
458 {.Names: {"SPI_INTERP_CONTROL_0"}, .Value: 0xa1b5},
459 {.Names: {"SPI_TMPRING_SIZE"}, .Value: 0xa1ba},
460 {.Names: {"SPI_SHADER_Z_FORMAT"}, .Value: 0xa1c4},
461 {.Names: {"SPI_SHADER_COL_FORMAT"}, .Value: 0xa1c5},
462 {.Names: {"DB_SHADER_CONTROL"}, .Value: 0xa203},
463 {.Names: {"CB_SHADER_MASK"}, .Value: 0xa08f},
464 {.Names: {"SPI_PS_INPUT_CNTL_0"}, .Value: 0xa191},
465 {.Names: {"SPI_PS_INPUT_CNTL_1"}, .Value: 0xa192},
466 {.Names: {"SPI_PS_INPUT_CNTL_2"}, .Value: 0xa193},
467 {.Names: {"SPI_PS_INPUT_CNTL_3"}, .Value: 0xa194},
468 {.Names: {"SPI_PS_INPUT_CNTL_4"}, .Value: 0xa195},
469 {.Names: {"SPI_PS_INPUT_CNTL_5"}, .Value: 0xa196},
470 {.Names: {"SPI_PS_INPUT_CNTL_6"}, .Value: 0xa197},
471 {.Names: {"SPI_PS_INPUT_CNTL_7"}, .Value: 0xa198},
472 {.Names: {"SPI_PS_INPUT_CNTL_8"}, .Value: 0xa199},
473 {.Names: {"SPI_PS_INPUT_CNTL_9"}, .Value: 0xa19a},
474 {.Names: {"SPI_PS_INPUT_CNTL_10"}, .Value: 0xa19b},
475 {.Names: {"SPI_PS_INPUT_CNTL_11"}, .Value: 0xa19c},
476 {.Names: {"SPI_PS_INPUT_CNTL_12"}, .Value: 0xa19d},
477 {.Names: {"SPI_PS_INPUT_CNTL_13"}, .Value: 0xa19e},
478 {.Names: {"SPI_PS_INPUT_CNTL_14"}, .Value: 0xa19f},
479 {.Names: {"SPI_PS_INPUT_CNTL_15"}, .Value: 0xa1a0},
480 {.Names: {"SPI_PS_INPUT_CNTL_16"}, .Value: 0xa1a1},
481 {.Names: {"SPI_PS_INPUT_CNTL_17"}, .Value: 0xa1a2},
482 {.Names: {"SPI_PS_INPUT_CNTL_18"}, .Value: 0xa1a3},
483 {.Names: {"SPI_PS_INPUT_CNTL_19"}, .Value: 0xa1a4},
484 {.Names: {"SPI_PS_INPUT_CNTL_20"}, .Value: 0xa1a5},
485 {.Names: {"SPI_PS_INPUT_CNTL_21"}, .Value: 0xa1a6},
486 {.Names: {"SPI_PS_INPUT_CNTL_22"}, .Value: 0xa1a7},
487 {.Names: {"SPI_PS_INPUT_CNTL_23"}, .Value: 0xa1a8},
488 {.Names: {"SPI_PS_INPUT_CNTL_24"}, .Value: 0xa1a9},
489 {.Names: {"SPI_PS_INPUT_CNTL_25"}, .Value: 0xa1aa},
490 {.Names: {"SPI_PS_INPUT_CNTL_26"}, .Value: 0xa1ab},
491 {.Names: {"SPI_PS_INPUT_CNTL_27"}, .Value: 0xa1ac},
492 {.Names: {"SPI_PS_INPUT_CNTL_28"}, .Value: 0xa1ad},
493 {.Names: {"SPI_PS_INPUT_CNTL_29"}, .Value: 0xa1ae},
494 {.Names: {"SPI_PS_INPUT_CNTL_30"}, .Value: 0xa1af},
495 {.Names: {"SPI_PS_INPUT_CNTL_31"}, .Value: 0xa1b0},
496
497 {.Names: {"VGT_GS_MAX_VERT_OUT"}, .Value: 0xa2ce},
498 {.Names: {"VGT_ESGS_RING_ITEMSIZE"}, .Value: 0xa2ab},
499 {.Names: {"VGT_GS_MODE"}, .Value: 0xa290},
500 {.Names: {"VGT_GS_ONCHIP_CNTL"}, .Value: 0xa291},
501 {.Names: {"VGT_GS_VERT_ITEMSIZE"}, .Value: 0xa2d7},
502 {.Names: {"VGT_GS_VERT_ITEMSIZE_1"}, .Value: 0xa2d8},
503 {.Names: {"VGT_GS_VERT_ITEMSIZE_2"}, .Value: 0xa2d9},
504 {.Names: {"VGT_GS_VERT_ITEMSIZE_3"}, .Value: 0xa2da},
505 {.Names: {"VGT_GSVS_RING_OFFSET_1"}, .Value: 0xa298},
506 {.Names: {"VGT_GSVS_RING_OFFSET_2"}, .Value: 0xa299},
507 {.Names: {"VGT_GSVS_RING_OFFSET_3"}, .Value: 0xa29a},
508
509 {.Names: {"VGT_GS_INSTANCE_CNT"}, .Value: 0xa2e4},
510 {.Names: {"VGT_GS_PER_VS"}, .Value: 0xa297},
511 {.Names: {"VGT_GS_OUT_PRIM_TYPE"}, .Value: 0xa29b},
512 {.Names: {"VGT_GSVS_RING_ITEMSIZE"}, .Value: 0xa2ac},
513
514 {.Names: {"VGT_REUSE_OFF"}, .Value: 0xa2ad},
515 {.Names: {"SPI_BARYC_CNTL"}, .Value: 0xa1b8},
516
517 {.Names: {"SPI_SHADER_USER_DATA_VS_0"}, .Value: 0x2c4c},
518 {.Names: {"SPI_SHADER_USER_DATA_VS_1"}, .Value: 0x2c4d},
519 {.Names: {"SPI_SHADER_USER_DATA_VS_2"}, .Value: 0x2c4e},
520 {.Names: {"SPI_SHADER_USER_DATA_VS_3"}, .Value: 0x2c4f},
521 {.Names: {"SPI_SHADER_USER_DATA_VS_4"}, .Value: 0x2c50},
522 {.Names: {"SPI_SHADER_USER_DATA_VS_5"}, .Value: 0x2c51},
523 {.Names: {"SPI_SHADER_USER_DATA_VS_6"}, .Value: 0x2c52},
524 {.Names: {"SPI_SHADER_USER_DATA_VS_7"}, .Value: 0x2c53},
525 {.Names: {"SPI_SHADER_USER_DATA_VS_8"}, .Value: 0x2c54},
526 {.Names: {"SPI_SHADER_USER_DATA_VS_9"}, .Value: 0x2c55},
527 {.Names: {"SPI_SHADER_USER_DATA_VS_10"}, .Value: 0x2c56},
528 {.Names: {"SPI_SHADER_USER_DATA_VS_11"}, .Value: 0x2c57},
529 {.Names: {"SPI_SHADER_USER_DATA_VS_12"}, .Value: 0x2c58},
530 {.Names: {"SPI_SHADER_USER_DATA_VS_13"}, .Value: 0x2c59},
531 {.Names: {"SPI_SHADER_USER_DATA_VS_14"}, .Value: 0x2c5a},
532 {.Names: {"SPI_SHADER_USER_DATA_VS_15"}, .Value: 0x2c5b},
533 {.Names: {"SPI_SHADER_USER_DATA_VS_16"}, .Value: 0x2c5c},
534 {.Names: {"SPI_SHADER_USER_DATA_VS_17"}, .Value: 0x2c5d},
535 {.Names: {"SPI_SHADER_USER_DATA_VS_18"}, .Value: 0x2c5e},
536 {.Names: {"SPI_SHADER_USER_DATA_VS_19"}, .Value: 0x2c5f},
537 {.Names: {"SPI_SHADER_USER_DATA_VS_20"}, .Value: 0x2c60},
538 {.Names: {"SPI_SHADER_USER_DATA_VS_21"}, .Value: 0x2c61},
539 {.Names: {"SPI_SHADER_USER_DATA_VS_22"}, .Value: 0x2c62},
540 {.Names: {"SPI_SHADER_USER_DATA_VS_23"}, .Value: 0x2c63},
541 {.Names: {"SPI_SHADER_USER_DATA_VS_24"}, .Value: 0x2c64},
542 {.Names: {"SPI_SHADER_USER_DATA_VS_25"}, .Value: 0x2c65},
543 {.Names: {"SPI_SHADER_USER_DATA_VS_26"}, .Value: 0x2c66},
544 {.Names: {"SPI_SHADER_USER_DATA_VS_27"}, .Value: 0x2c67},
545 {.Names: {"SPI_SHADER_USER_DATA_VS_28"}, .Value: 0x2c68},
546 {.Names: {"SPI_SHADER_USER_DATA_VS_29"}, .Value: 0x2c69},
547 {.Names: {"SPI_SHADER_USER_DATA_VS_30"}, .Value: 0x2c6a},
548 {.Names: {"SPI_SHADER_USER_DATA_VS_31"}, .Value: 0x2c6b},
549
550 {.Names: {"SPI_SHADER_USER_DATA_GS_0"}, .Value: 0x2c8c},
551 {.Names: {"SPI_SHADER_USER_DATA_GS_1"}, .Value: 0x2c8d},
552 {.Names: {"SPI_SHADER_USER_DATA_GS_2"}, .Value: 0x2c8e},
553 {.Names: {"SPI_SHADER_USER_DATA_GS_3"}, .Value: 0x2c8f},
554 {.Names: {"SPI_SHADER_USER_DATA_GS_4"}, .Value: 0x2c90},
555 {.Names: {"SPI_SHADER_USER_DATA_GS_5"}, .Value: 0x2c91},
556 {.Names: {"SPI_SHADER_USER_DATA_GS_6"}, .Value: 0x2c92},
557 {.Names: {"SPI_SHADER_USER_DATA_GS_7"}, .Value: 0x2c93},
558 {.Names: {"SPI_SHADER_USER_DATA_GS_8"}, .Value: 0x2c94},
559 {.Names: {"SPI_SHADER_USER_DATA_GS_9"}, .Value: 0x2c95},
560 {.Names: {"SPI_SHADER_USER_DATA_GS_10"}, .Value: 0x2c96},
561 {.Names: {"SPI_SHADER_USER_DATA_GS_11"}, .Value: 0x2c97},
562 {.Names: {"SPI_SHADER_USER_DATA_GS_12"}, .Value: 0x2c98},
563 {.Names: {"SPI_SHADER_USER_DATA_GS_13"}, .Value: 0x2c99},
564 {.Names: {"SPI_SHADER_USER_DATA_GS_14"}, .Value: 0x2c9a},
565 {.Names: {"SPI_SHADER_USER_DATA_GS_15"}, .Value: 0x2c9b},
566 {.Names: {"SPI_SHADER_USER_DATA_GS_16"}, .Value: 0x2c9c},
567 {.Names: {"SPI_SHADER_USER_DATA_GS_17"}, .Value: 0x2c9d},
568 {.Names: {"SPI_SHADER_USER_DATA_GS_18"}, .Value: 0x2c9e},
569 {.Names: {"SPI_SHADER_USER_DATA_GS_19"}, .Value: 0x2c9f},
570 {.Names: {"SPI_SHADER_USER_DATA_GS_20"}, .Value: 0x2ca0},
571 {.Names: {"SPI_SHADER_USER_DATA_GS_21"}, .Value: 0x2ca1},
572 {.Names: {"SPI_SHADER_USER_DATA_GS_22"}, .Value: 0x2ca2},
573 {.Names: {"SPI_SHADER_USER_DATA_GS_23"}, .Value: 0x2ca3},
574 {.Names: {"SPI_SHADER_USER_DATA_GS_24"}, .Value: 0x2ca4},
575 {.Names: {"SPI_SHADER_USER_DATA_GS_25"}, .Value: 0x2ca5},
576 {.Names: {"SPI_SHADER_USER_DATA_GS_26"}, .Value: 0x2ca6},
577 {.Names: {"SPI_SHADER_USER_DATA_GS_27"}, .Value: 0x2ca7},
578 {.Names: {"SPI_SHADER_USER_DATA_GS_28"}, .Value: 0x2ca8},
579 {.Names: {"SPI_SHADER_USER_DATA_GS_29"}, .Value: 0x2ca9},
580 {.Names: {"SPI_SHADER_USER_DATA_GS_30"}, .Value: 0x2caa},
581 {.Names: {"SPI_SHADER_USER_DATA_GS_31"}, .Value: 0x2cab},
582
583 {.Names: {"SPI_SHADER_USER_DATA_ES_0"}, .Value: 0x2ccc},
584 {.Names: {"SPI_SHADER_USER_DATA_ES_1"}, .Value: 0x2ccd},
585 {.Names: {"SPI_SHADER_USER_DATA_ES_2"}, .Value: 0x2cce},
586 {.Names: {"SPI_SHADER_USER_DATA_ES_3"}, .Value: 0x2ccf},
587 {.Names: {"SPI_SHADER_USER_DATA_ES_4"}, .Value: 0x2cd0},
588 {.Names: {"SPI_SHADER_USER_DATA_ES_5"}, .Value: 0x2cd1},
589 {.Names: {"SPI_SHADER_USER_DATA_ES_6"}, .Value: 0x2cd2},
590 {.Names: {"SPI_SHADER_USER_DATA_ES_7"}, .Value: 0x2cd3},
591 {.Names: {"SPI_SHADER_USER_DATA_ES_8"}, .Value: 0x2cd4},
592 {.Names: {"SPI_SHADER_USER_DATA_ES_9"}, .Value: 0x2cd5},
593 {.Names: {"SPI_SHADER_USER_DATA_ES_10"}, .Value: 0x2cd6},
594 {.Names: {"SPI_SHADER_USER_DATA_ES_11"}, .Value: 0x2cd7},
595 {.Names: {"SPI_SHADER_USER_DATA_ES_12"}, .Value: 0x2cd8},
596 {.Names: {"SPI_SHADER_USER_DATA_ES_13"}, .Value: 0x2cd9},
597 {.Names: {"SPI_SHADER_USER_DATA_ES_14"}, .Value: 0x2cda},
598 {.Names: {"SPI_SHADER_USER_DATA_ES_15"}, .Value: 0x2cdb},
599 {.Names: {"SPI_SHADER_USER_DATA_ES_16"}, .Value: 0x2cdc},
600 {.Names: {"SPI_SHADER_USER_DATA_ES_17"}, .Value: 0x2cdd},
601 {.Names: {"SPI_SHADER_USER_DATA_ES_18"}, .Value: 0x2cde},
602 {.Names: {"SPI_SHADER_USER_DATA_ES_19"}, .Value: 0x2cdf},
603 {.Names: {"SPI_SHADER_USER_DATA_ES_20"}, .Value: 0x2ce0},
604 {.Names: {"SPI_SHADER_USER_DATA_ES_21"}, .Value: 0x2ce1},
605 {.Names: {"SPI_SHADER_USER_DATA_ES_22"}, .Value: 0x2ce2},
606 {.Names: {"SPI_SHADER_USER_DATA_ES_23"}, .Value: 0x2ce3},
607 {.Names: {"SPI_SHADER_USER_DATA_ES_24"}, .Value: 0x2ce4},
608 {.Names: {"SPI_SHADER_USER_DATA_ES_25"}, .Value: 0x2ce5},
609 {.Names: {"SPI_SHADER_USER_DATA_ES_26"}, .Value: 0x2ce6},
610 {.Names: {"SPI_SHADER_USER_DATA_ES_27"}, .Value: 0x2ce7},
611 {.Names: {"SPI_SHADER_USER_DATA_ES_28"}, .Value: 0x2ce8},
612 {.Names: {"SPI_SHADER_USER_DATA_ES_29"}, .Value: 0x2ce9},
613 {.Names: {"SPI_SHADER_USER_DATA_ES_30"}, .Value: 0x2cea},
614 {.Names: {"SPI_SHADER_USER_DATA_ES_31"}, .Value: 0x2ceb},
615
616 {.Names: {"SPI_SHADER_USER_DATA_PS_0"}, .Value: 0x2c0c},
617 {.Names: {"SPI_SHADER_USER_DATA_PS_1"}, .Value: 0x2c0d},
618 {.Names: {"SPI_SHADER_USER_DATA_PS_2"}, .Value: 0x2c0e},
619 {.Names: {"SPI_SHADER_USER_DATA_PS_3"}, .Value: 0x2c0f},
620 {.Names: {"SPI_SHADER_USER_DATA_PS_4"}, .Value: 0x2c10},
621 {.Names: {"SPI_SHADER_USER_DATA_PS_5"}, .Value: 0x2c11},
622 {.Names: {"SPI_SHADER_USER_DATA_PS_6"}, .Value: 0x2c12},
623 {.Names: {"SPI_SHADER_USER_DATA_PS_7"}, .Value: 0x2c13},
624 {.Names: {"SPI_SHADER_USER_DATA_PS_8"}, .Value: 0x2c14},
625 {.Names: {"SPI_SHADER_USER_DATA_PS_9"}, .Value: 0x2c15},
626 {.Names: {"SPI_SHADER_USER_DATA_PS_10"}, .Value: 0x2c16},
627 {.Names: {"SPI_SHADER_USER_DATA_PS_11"}, .Value: 0x2c17},
628 {.Names: {"SPI_SHADER_USER_DATA_PS_12"}, .Value: 0x2c18},
629 {.Names: {"SPI_SHADER_USER_DATA_PS_13"}, .Value: 0x2c19},
630 {.Names: {"SPI_SHADER_USER_DATA_PS_14"}, .Value: 0x2c1a},
631 {.Names: {"SPI_SHADER_USER_DATA_PS_15"}, .Value: 0x2c1b},
632 {.Names: {"SPI_SHADER_USER_DATA_PS_16"}, .Value: 0x2c1c},
633 {.Names: {"SPI_SHADER_USER_DATA_PS_17"}, .Value: 0x2c1d},
634 {.Names: {"SPI_SHADER_USER_DATA_PS_18"}, .Value: 0x2c1e},
635 {.Names: {"SPI_SHADER_USER_DATA_PS_19"}, .Value: 0x2c1f},
636 {.Names: {"SPI_SHADER_USER_DATA_PS_20"}, .Value: 0x2c20},
637 {.Names: {"SPI_SHADER_USER_DATA_PS_21"}, .Value: 0x2c21},
638 {.Names: {"SPI_SHADER_USER_DATA_PS_22"}, .Value: 0x2c22},
639 {.Names: {"SPI_SHADER_USER_DATA_PS_23"}, .Value: 0x2c23},
640 {.Names: {"SPI_SHADER_USER_DATA_PS_24"}, .Value: 0x2c24},
641 {.Names: {"SPI_SHADER_USER_DATA_PS_25"}, .Value: 0x2c25},
642 {.Names: {"SPI_SHADER_USER_DATA_PS_26"}, .Value: 0x2c26},
643 {.Names: {"SPI_SHADER_USER_DATA_PS_27"}, .Value: 0x2c27},
644 {.Names: {"SPI_SHADER_USER_DATA_PS_28"}, .Value: 0x2c28},
645 {.Names: {"SPI_SHADER_USER_DATA_PS_29"}, .Value: 0x2c29},
646 {.Names: {"SPI_SHADER_USER_DATA_PS_30"}, .Value: 0x2c2a},
647 {.Names: {"SPI_SHADER_USER_DATA_PS_31"}, .Value: 0x2c2b},
648
649 {.Names: {"COMPUTE_USER_DATA_0"}, .Value: 0x2e40},
650 {.Names: {"COMPUTE_USER_DATA_1"}, .Value: 0x2e41},
651 {.Names: {"COMPUTE_USER_DATA_2"}, .Value: 0x2e42},
652 {.Names: {"COMPUTE_USER_DATA_3"}, .Value: 0x2e43},
653 {.Names: {"COMPUTE_USER_DATA_4"}, .Value: 0x2e44},
654 {.Names: {"COMPUTE_USER_DATA_5"}, .Value: 0x2e45},
655 {.Names: {"COMPUTE_USER_DATA_6"}, .Value: 0x2e46},
656 {.Names: {"COMPUTE_USER_DATA_7"}, .Value: 0x2e47},
657 {.Names: {"COMPUTE_USER_DATA_8"}, .Value: 0x2e48},
658 {.Names: {"COMPUTE_USER_DATA_9"}, .Value: 0x2e49},
659 {.Names: {"COMPUTE_USER_DATA_10"}, .Value: 0x2e4a},
660 {.Names: {"COMPUTE_USER_DATA_11"}, .Value: 0x2e4b},
661 {.Names: {"COMPUTE_USER_DATA_12"}, .Value: 0x2e4c},
662 {.Names: {"COMPUTE_USER_DATA_13"}, .Value: 0x2e4d},
663 {.Names: {"COMPUTE_USER_DATA_14"}, .Value: 0x2e4e},
664 {.Names: {"COMPUTE_USER_DATA_15"}, .Value: 0x2e4f},
665 {.Names: {"COMPUTE_USER_DATA_16"}, .Value: 0x2e50},
666 {.Names: {"COMPUTE_USER_DATA_17"}, .Value: 0x2e51},
667 {.Names: {"COMPUTE_USER_DATA_18"}, .Value: 0x2e52},
668 {.Names: {"COMPUTE_USER_DATA_19"}, .Value: 0x2e53},
669 {.Names: {"COMPUTE_USER_DATA_20"}, .Value: 0x2e54},
670 {.Names: {"COMPUTE_USER_DATA_21"}, .Value: 0x2e55},
671 {.Names: {"COMPUTE_USER_DATA_22"}, .Value: 0x2e56},
672 {.Names: {"COMPUTE_USER_DATA_23"}, .Value: 0x2e57},
673 {.Names: {"COMPUTE_USER_DATA_24"}, .Value: 0x2e58},
674 {.Names: {"COMPUTE_USER_DATA_25"}, .Value: 0x2e59},
675 {.Names: {"COMPUTE_USER_DATA_26"}, .Value: 0x2e5a},
676 {.Names: {"COMPUTE_USER_DATA_27"}, .Value: 0x2e5b},
677 {.Names: {"COMPUTE_USER_DATA_28"}, .Value: 0x2e5c},
678 {.Names: {"COMPUTE_USER_DATA_29"}, .Value: 0x2e5d},
679 {.Names: {"COMPUTE_USER_DATA_30"}, .Value: 0x2e5e},
680 {.Names: {"COMPUTE_USER_DATA_31"}, .Value: 0x2e5f},
681
682 {.Names: {"COMPUTE_NUM_THREAD_X"}, .Value: 0x2e07},
683 {.Names: {"COMPUTE_NUM_THREAD_Y"}, .Value: 0x2e08},
684 {.Names: {"COMPUTE_NUM_THREAD_Z"}, .Value: 0x2e09},
685 {.Names: {"VGT_TF_PARAM"}, .Value: 0xa2db},
686 {.Names: {"VGT_LS_HS_CONFIG"}, .Value: 0xa2d6},
687 {.Names: {"VGT_HOS_MIN_TESS_LEVEL"}, .Value: 0xa287},
688 {.Names: {"VGT_HOS_MAX_TESS_LEVEL"}, .Value: 0xa286},
689 {.Names: {"PA_SC_AA_CONFIG"}, .Value: 0xa2f8},
690 {.Names: {"PA_SC_SHADER_CONTROL"}, .Value: 0xa310},
691 {.Names: {"PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"}, .Value: 0xa313},
692
693 {.Names: {"SPI_SHADER_USER_DATA_HS_0"}, .Value: 0x2d0c},
694 {.Names: {"SPI_SHADER_USER_DATA_HS_1"}, .Value: 0x2d0d},
695 {.Names: {"SPI_SHADER_USER_DATA_HS_2"}, .Value: 0x2d0e},
696 {.Names: {"SPI_SHADER_USER_DATA_HS_3"}, .Value: 0x2d0f},
697 {.Names: {"SPI_SHADER_USER_DATA_HS_4"}, .Value: 0x2d10},
698 {.Names: {"SPI_SHADER_USER_DATA_HS_5"}, .Value: 0x2d11},
699 {.Names: {"SPI_SHADER_USER_DATA_HS_6"}, .Value: 0x2d12},
700 {.Names: {"SPI_SHADER_USER_DATA_HS_7"}, .Value: 0x2d13},
701 {.Names: {"SPI_SHADER_USER_DATA_HS_8"}, .Value: 0x2d14},
702 {.Names: {"SPI_SHADER_USER_DATA_HS_9"}, .Value: 0x2d15},
703 {.Names: {"SPI_SHADER_USER_DATA_HS_10"}, .Value: 0x2d16},
704 {.Names: {"SPI_SHADER_USER_DATA_HS_11"}, .Value: 0x2d17},
705 {.Names: {"SPI_SHADER_USER_DATA_HS_12"}, .Value: 0x2d18},
706 {.Names: {"SPI_SHADER_USER_DATA_HS_13"}, .Value: 0x2d19},
707 {.Names: {"SPI_SHADER_USER_DATA_HS_14"}, .Value: 0x2d1a},
708 {.Names: {"SPI_SHADER_USER_DATA_HS_15"}, .Value: 0x2d1b},
709 {.Names: {"SPI_SHADER_USER_DATA_HS_16"}, .Value: 0x2d1c},
710 {.Names: {"SPI_SHADER_USER_DATA_HS_17"}, .Value: 0x2d1d},
711 {.Names: {"SPI_SHADER_USER_DATA_HS_18"}, .Value: 0x2d1e},
712 {.Names: {"SPI_SHADER_USER_DATA_HS_19"}, .Value: 0x2d1f},
713 {.Names: {"SPI_SHADER_USER_DATA_HS_20"}, .Value: 0x2d20},
714 {.Names: {"SPI_SHADER_USER_DATA_HS_21"}, .Value: 0x2d21},
715 {.Names: {"SPI_SHADER_USER_DATA_HS_22"}, .Value: 0x2d22},
716 {.Names: {"SPI_SHADER_USER_DATA_HS_23"}, .Value: 0x2d23},
717 {.Names: {"SPI_SHADER_USER_DATA_HS_24"}, .Value: 0x2d24},
718 {.Names: {"SPI_SHADER_USER_DATA_HS_25"}, .Value: 0x2d25},
719 {.Names: {"SPI_SHADER_USER_DATA_HS_26"}, .Value: 0x2d26},
720 {.Names: {"SPI_SHADER_USER_DATA_HS_27"}, .Value: 0x2d27},
721 {.Names: {"SPI_SHADER_USER_DATA_HS_28"}, .Value: 0x2d28},
722 {.Names: {"SPI_SHADER_USER_DATA_HS_29"}, .Value: 0x2d29},
723 {.Names: {"SPI_SHADER_USER_DATA_HS_30"}, .Value: 0x2d2a},
724 {.Names: {"SPI_SHADER_USER_DATA_HS_31"}, .Value: 0x2d2b},
725
726 {.Names: {"SPI_SHADER_USER_DATA_LS_0"}, .Value: 0x2d4c},
727 {.Names: {"SPI_SHADER_USER_DATA_LS_1"}, .Value: 0x2d4d},
728 {.Names: {"SPI_SHADER_USER_DATA_LS_2"}, .Value: 0x2d4e},
729 {.Names: {"SPI_SHADER_USER_DATA_LS_3"}, .Value: 0x2d4f},
730 {.Names: {"SPI_SHADER_USER_DATA_LS_4"}, .Value: 0x2d50},
731 {.Names: {"SPI_SHADER_USER_DATA_LS_5"}, .Value: 0x2d51},
732 {.Names: {"SPI_SHADER_USER_DATA_LS_6"}, .Value: 0x2d52},
733 {.Names: {"SPI_SHADER_USER_DATA_LS_7"}, .Value: 0x2d53},
734 {.Names: {"SPI_SHADER_USER_DATA_LS_8"}, .Value: 0x2d54},
735 {.Names: {"SPI_SHADER_USER_DATA_LS_9"}, .Value: 0x2d55},
736 {.Names: {"SPI_SHADER_USER_DATA_LS_10"}, .Value: 0x2d56},
737 {.Names: {"SPI_SHADER_USER_DATA_LS_11"}, .Value: 0x2d57},
738 {.Names: {"SPI_SHADER_USER_DATA_LS_12"}, .Value: 0x2d58},
739 {.Names: {"SPI_SHADER_USER_DATA_LS_13"}, .Value: 0x2d59},
740 {.Names: {"SPI_SHADER_USER_DATA_LS_14"}, .Value: 0x2d5a},
741 {.Names: {"SPI_SHADER_USER_DATA_LS_15"}, .Value: 0x2d5b},
742
743 {.Names: {"IA_MULTI_VGT_PARAM"}, .Value: 0xa2aa},
744 {.Names: {"VGT_GS_MAX_PRIMS_PER_SUBGROUP"}, .Value: 0xa2a5},
745 {.Names: {"VGT_STRMOUT_BUFFER_CONFIG"}, .Value: 0xa2e6},
746 {.Names: {"VGT_STRMOUT_CONFIG"}, .Value: 0xa2e5},
747 {.Names: {"VGT_STRMOUT_VTX_STRIDE_0"}, .Value: 0xa2b5},
748 {.Names: {"VGT_STRMOUT_VTX_STRIDE_1"}, .Value: 0xa2b9},
749 {.Names: {"VGT_STRMOUT_VTX_STRIDE_2"}, .Value: 0xa2bd},
750 {.Names: {"VGT_STRMOUT_VTX_STRIDE_3"}, .Value: 0xa2c1},
751 {.Names: {"VGT_VERTEX_REUSE_BLOCK_CNTL"}, .Value: 0xa316},
752
753 {.Names: {"COMPUTE_PGM_RSRC3"}, .Value: 0x2e28},
754 {.Names: {"COMPUTE_SHADER_CHKSUM"}, .Value: 0x2e2a},
755 {.Names: {"COMPUTE_USER_ACCUM_0"}, .Value: 0x2e24},
756 {.Names: {"COMPUTE_USER_ACCUM_1"}, .Value: 0x2e25},
757 {.Names: {"COMPUTE_USER_ACCUM_2"}, .Value: 0x2e26},
758 {.Names: {"COMPUTE_USER_ACCUM_3"}, .Value: 0x2e27},
759 {.Names: {"GE_MAX_OUTPUT_PER_SUBGROUP"}, .Value: 0xa1ff},
760 {.Names: {"GE_NGG_SUBGRP_CNTL"}, .Value: 0xa2d3},
761 {.Names: {"GE_STEREO_CNTL"}, .Value: 0xc25f},
762 {.Names: {"GE_USER_VGPR_EN"}, .Value: 0xc262},
763 {.Names: {"IA_MULTI_VGT_PARAM_PIPED"}, .Value: 0xc258},
764 {.Names: {"PA_STEREO_CNTL"}, .Value: 0xa210},
765 {.Names: {"SPI_SHADER_IDX_FORMAT"}, .Value: 0xa1c2},
766 {.Names: {"SPI_SHADER_PGM_CHKSUM_GS"}, .Value: 0x2c80},
767 {.Names: {"SPI_SHADER_PGM_CHKSUM_HS"}, .Value: 0x2d00},
768 {.Names: {"SPI_SHADER_PGM_CHKSUM_PS"}, .Value: 0x2c06},
769 {.Names: {"SPI_SHADER_PGM_CHKSUM_VS"}, .Value: 0x2c45},
770 {.Names: {"SPI_SHADER_PGM_LO_GS"}, .Value: 0x2c88},
771 {.Names: {"SPI_SHADER_USER_ACCUM_ESGS_0"}, .Value: 0x2cb2},
772 {.Names: {"SPI_SHADER_USER_ACCUM_ESGS_1"}, .Value: 0x2cb3},
773 {.Names: {"SPI_SHADER_USER_ACCUM_ESGS_2"}, .Value: 0x2cb4},
774 {.Names: {"SPI_SHADER_USER_ACCUM_ESGS_3"}, .Value: 0x2cb5},
775 {.Names: {"SPI_SHADER_USER_ACCUM_LSHS_0"}, .Value: 0x2d32},
776 {.Names: {"SPI_SHADER_USER_ACCUM_LSHS_1"}, .Value: 0x2d33},
777 {.Names: {"SPI_SHADER_USER_ACCUM_LSHS_2"}, .Value: 0x2d34},
778 {.Names: {"SPI_SHADER_USER_ACCUM_LSHS_3"}, .Value: 0x2d35},
779 {.Names: {"SPI_SHADER_USER_ACCUM_PS_0"}, .Value: 0x2c32},
780 {.Names: {"SPI_SHADER_USER_ACCUM_PS_1"}, .Value: 0x2c33},
781 {.Names: {"SPI_SHADER_USER_ACCUM_PS_2"}, .Value: 0x2c34},
782 {.Names: {"SPI_SHADER_USER_ACCUM_PS_3"}, .Value: 0x2c35},
783 {.Names: {"SPI_SHADER_USER_ACCUM_VS_0"}, .Value: 0x2c72},
784 {.Names: {"SPI_SHADER_USER_ACCUM_VS_1"}, .Value: 0x2c73},
785 {.Names: {"SPI_SHADER_USER_ACCUM_VS_2"}, .Value: 0x2c74},
786 {.Names: {"SPI_SHADER_USER_ACCUM_VS_3"}, .Value: 0x2c75},
787 };
788 static constexpr auto RegInfoTable = BUILD_ENUM_STRINGS(RegInfoTableDefs);
789 return EnumStrings(RegInfoTable).toString(Value: RegNum);
790}
791
792// Convert the accumulated PAL metadata into an asm directive.
793void AMDGPUPALMetadata::toString(std::string &String) {
794 String.clear();
795 if (!BlobType)
796 return;
797 ResolvedAll = DelayedExprs.resolveDelayedExpressions();
798 raw_string_ostream Stream(String);
799 if (isLegacy()) {
800 if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil)
801 return;
802 // Old linear reg=val format.
803 Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' ';
804 auto Regs = getRegisters();
805 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
806 if (I != Regs.begin())
807 Stream << ',';
808 unsigned Reg = I->first.getUInt();
809 unsigned Val = I->second.getUInt();
810 Stream << "0x" << Twine::utohexstr(Val: Reg) << ",0x" << Twine::utohexstr(Val);
811 }
812 Stream << '\n';
813 return;
814 }
815
816 // New msgpack-based format -- output as YAML (with unsigned numbers in hex),
817 // but first change the registers map to use names.
818 MsgPackDoc.setHexMode();
819 auto &RegsObj = refRegisters();
820 auto OrigRegs = RegsObj.getMap();
821 RegsObj = MsgPackDoc.getMapNode();
822 for (auto I : OrigRegs) {
823 auto Key = I.first;
824 if (StringRef RegName = getRegisterName(RegNum: Key.getUInt()); !RegName.empty()) {
825 std::string KeyName = Key.toString();
826 KeyName += " (";
827 KeyName += RegName;
828 KeyName += ')';
829 Key = MsgPackDoc.getNode(V: KeyName, /*Copy=*/true);
830 }
831 RegsObj.getMap()[Key] = I.second;
832 }
833
834 // Output as YAML.
835 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n';
836 MsgPackDoc.toYAML(OS&: Stream);
837 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n';
838
839 // Restore original registers map.
840 RegsObj = OrigRegs;
841}
842
843// Convert the accumulated PAL metadata into a binary blob for writing as
844// a .note record of the specified AMD type. Returns an empty blob if
845// there is no PAL metadata,
846void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) {
847 ResolvedAll = DelayedExprs.resolveDelayedExpressions();
848 if (Type == ELF::NT_AMD_PAL_METADATA)
849 toLegacyBlob(Blob);
850 else if (Type)
851 toMsgPackBlob(Blob);
852}
853
854void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) {
855 Blob.clear();
856 auto Registers = getRegisters();
857 if (Registers.getMap().empty())
858 return;
859 raw_string_ostream OS(Blob);
860 support::endian::Writer EW(OS, llvm::endianness::little);
861 for (auto I : Registers.getMap()) {
862 EW.write(Val: uint32_t(I.first.getUInt()));
863 EW.write(Val: uint32_t(I.second.getUInt()));
864 }
865}
866
867void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) {
868 Blob.clear();
869 MsgPackDoc.writeToBlob(Blob);
870}
871
872// Set PAL metadata from YAML text. Returns false if failed.
873bool AMDGPUPALMetadata::setFromString(StringRef S) {
874 BlobType = ELF::NT_AMDGPU_METADATA;
875 if (!MsgPackDoc.fromYAML(S))
876 return false;
877
878 // In the registers map, some keys may be of the form "0xa191
879 // (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a
880 // string. We need to turn it into a number.
881 auto &RegsObj = refRegisters();
882 auto OrigRegs = RegsObj;
883 RegsObj = MsgPackDoc.getMapNode();
884 Registers = RegsObj.getMap();
885 bool Ok = true;
886 for (auto I : OrigRegs.getMap()) {
887 auto Key = I.first;
888 if (Key.getKind() == msgpack::Type::String) {
889 StringRef S = Key.getString();
890 uint64_t Val;
891 if (S.consumeInteger(Radix: 0, Result&: Val)) {
892 Ok = false;
893 errs() << "Unrecognized PAL metadata register key '" << S << "'\n";
894 continue;
895 }
896 Key = MsgPackDoc.getNode(V: Val);
897 }
898 Registers.getMap()[Key] = I.second;
899 }
900 return Ok;
901}
902
903// Reference (create if necessary) the node for the registers map.
904msgpack::DocNode &AMDGPUPALMetadata::refRegisters() {
905 auto &N =
906 MsgPackDoc.getRoot()
907 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines")]
908 .getArray(/*Convert=*/true)[0]
909 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".registers")];
910 N.getMap(/*Convert=*/true);
911 return N;
912}
913
914// Get (create if necessary) the registers map.
915msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() {
916 if (Registers.isEmpty())
917 Registers = refRegisters();
918 return Registers.getMap();
919}
920
921// Reference (create if necessary) the node for the shader functions map.
922msgpack::DocNode &AMDGPUPALMetadata::refShaderFunctions() {
923 auto &N =
924 MsgPackDoc.getRoot()
925 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines")]
926 .getArray(/*Convert=*/true)[0]
927 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".shader_functions")];
928 N.getMap(/*Convert=*/true);
929 return N;
930}
931
932// Get (create if necessary) the shader functions map.
933msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunctions() {
934 if (ShaderFunctions.isEmpty())
935 ShaderFunctions = refShaderFunctions();
936 return ShaderFunctions.getMap();
937}
938
939// Get (create if necessary) a function in the shader functions map.
940msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunction(StringRef Name) {
941 auto Functions = getShaderFunctions();
942 return Functions[Name].getMap(/*Convert=*/true);
943}
944
945msgpack::DocNode &AMDGPUPALMetadata::refComputeRegisters() {
946 auto &N =
947 MsgPackDoc.getRoot()
948 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines")]
949 .getArray(/*Convert=*/true)[0]
950 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".compute_registers")];
951 N.getMap(/*Convert=*/true);
952 return N;
953}
954
955msgpack::MapDocNode AMDGPUPALMetadata::getComputeRegisters() {
956 if (ComputeRegisters.isEmpty())
957 ComputeRegisters = refComputeRegisters();
958 return ComputeRegisters.getMap();
959}
960
961msgpack::DocNode &AMDGPUPALMetadata::refGraphicsRegisters() {
962 auto &N =
963 MsgPackDoc.getRoot()
964 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines")]
965 .getArray(/*Convert=*/true)[0]
966 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".graphics_registers")];
967 N.getMap(/*Convert=*/true);
968 return N;
969}
970
971msgpack::MapDocNode AMDGPUPALMetadata::getGraphicsRegisters() {
972 if (GraphicsRegisters.isEmpty())
973 GraphicsRegisters = refGraphicsRegisters();
974 return GraphicsRegisters.getMap();
975}
976
977msgpack::DocNode &AMDGPUPALMetadata::refHwStage() {
978 auto &N =
979 MsgPackDoc.getRoot()
980 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines")]
981 .getArray(/*Convert=*/true)[0]
982 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".hardware_stages")];
983 N.getMap(/*Convert=*/true);
984 return N;
985}
986
987// Get (create if necessary) the .hardware_stages entry for the given calling
988// convention.
989msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) {
990 if (HwStages.isEmpty())
991 HwStages = refHwStage();
992 return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true);
993}
994
995// Get .note record vendor name of metadata blob to be emitted.
996const char *AMDGPUPALMetadata::getVendor() const {
997 return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3;
998}
999
1000// Get .note record type of metadata blob to be emitted:
1001// ELF::NT_AMD_PAL_METADATA (legacy key=val format), or
1002// ELF::NT_AMDGPU_METADATA (MsgPack format), or
1003// 0 (no PAL metadata).
1004unsigned AMDGPUPALMetadata::getType() const {
1005 return BlobType;
1006}
1007
1008// Return whether the blob type is legacy PAL metadata.
1009bool AMDGPUPALMetadata::isLegacy() const {
1010 return BlobType == ELF::NT_AMD_PAL_METADATA;
1011}
1012
1013// Set legacy PAL metadata format.
1014void AMDGPUPALMetadata::setLegacy() {
1015 BlobType = ELF::NT_AMD_PAL_METADATA;
1016}
1017
1018// Erase all PAL metadata.
1019void AMDGPUPALMetadata::reset() {
1020 MsgPackDoc.clear();
1021 REM.clear();
1022 DelayedExprs.clear();
1023 Registers = MsgPackDoc.getEmptyNode();
1024 HwStages = MsgPackDoc.getEmptyNode();
1025 ShaderFunctions = MsgPackDoc.getEmptyNode();
1026}
1027
1028bool AMDGPUPALMetadata::resolvedAllMCExpr() {
1029 return ResolvedAll && DelayedExprs.empty();
1030}
1031
1032unsigned AMDGPUPALMetadata::getPALVersion(unsigned idx) {
1033 assert(idx < 2 &&
1034 "illegal index to PAL version - should be 0 (major) or 1 (minor)");
1035 if (!VersionChecked) {
1036 if (Version.isEmpty()) {
1037 auto &M = MsgPackDoc.getRoot().getMap(/*Convert=*/true);
1038 auto I = M.find(Key: MsgPackDoc.getNode(V: "amdpal.version"));
1039 if (I != M.end())
1040 Version = I->second;
1041 }
1042 VersionChecked = true;
1043 }
1044 if (Version.isEmpty())
1045 // Default to 2.6 if there's no version info
1046 return idx ? 6 : 2;
1047 return Version.getArray()[idx].getUInt();
1048}
1049
1050unsigned AMDGPUPALMetadata::getPALMajorVersion() { return getPALVersion(idx: 0); }
1051
1052VersionTuple AMDGPUPALMetadata::getPALVersion() {
1053 return VersionTuple(getPALVersion(idx: 0), getPALVersion(idx: 1));
1054}
1055
1056// Set the field in a given .hardware_stages entry to a maximum value
1057void AMDGPUPALMetadata::updateHwStageMaximum(unsigned CC, StringRef field,
1058 unsigned Val) {
1059 msgpack::MapDocNode HwStageFieldMapNode = getHwStage(CC);
1060 auto &Node = HwStageFieldMapNode[field];
1061 if (Node.isEmpty())
1062 Node = Val;
1063 else
1064 Node = std::max<unsigned>(a: Node.getUInt(), b: Val);
1065}
1066
1067// Set the field in a given .hardware_stages entry
1068void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, unsigned Val) {
1069 getHwStage(CC)[field] = Val;
1070}
1071
1072void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, bool Val) {
1073 getHwStage(CC)[field] = Val;
1074}
1075
1076void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field,
1077 msgpack::Type Type, const MCExpr *Val) {
1078 DelayedExprs.assignDocNode(DN&: getHwStage(CC)[field], Type, ExprValue: Val);
1079}
1080
1081void AMDGPUPALMetadata::setComputeRegisters(StringRef field, unsigned Val) {
1082 getComputeRegisters()[field] = Val;
1083}
1084
1085void AMDGPUPALMetadata::setComputeRegisters(StringRef field, bool Val) {
1086 getComputeRegisters()[field] = Val;
1087}
1088
1089msgpack::DocNode *AMDGPUPALMetadata::refComputeRegister(StringRef field) {
1090 auto M = getComputeRegisters();
1091 auto I = M.find(Key: field);
1092 return I == M.end() ? nullptr : &I->second;
1093}
1094
1095bool AMDGPUPALMetadata::checkComputeRegisters(StringRef field, unsigned Val) {
1096 if (auto *N = refComputeRegister(field))
1097 return N->getUInt() == Val;
1098 return false;
1099}
1100
1101bool AMDGPUPALMetadata::checkComputeRegisters(StringRef field, bool Val) {
1102 if (auto *N = refComputeRegister(field))
1103 return N->getBool() == Val;
1104 return false;
1105}
1106
1107void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field, unsigned Val) {
1108 getGraphicsRegisters()[field] = Val;
1109}
1110
1111void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field, bool Val) {
1112 getGraphicsRegisters()[field] = Val;
1113}
1114
1115void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field1, StringRef field2,
1116 unsigned Val) {
1117 getGraphicsRegisters()[field1].getMap(Convert: true)[field2] = Val;
1118}
1119
1120void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field1, StringRef field2,
1121 bool Val) {
1122 getGraphicsRegisters()[field1].getMap(Convert: true)[field2] = Val;
1123}
1124