1//===-- AMDGPUPALMetadata.cpp - Accumulate and print AMDGPU PAL metadata -===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10///
11/// This class has methods called by AMDGPUAsmPrinter to accumulate and print
12/// the PAL metadata.
13//
14//===----------------------------------------------------------------------===//
15//
16
17#include "AMDGPUPALMetadata.h"
18#include "AMDGPUPTNote.h"
19#include "SIDefines.h"
20#include "llvm/ADT/Enum.h"
21#include "llvm/BinaryFormat/ELF.h"
22#include "llvm/IR/Constants.h"
23#include "llvm/IR/Module.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/Support/AMDGPUMetadata.h"
26#include "llvm/Support/EndianStream.h"
27#include "llvm/Support/VersionTuple.h"
28
29using namespace llvm;
30using namespace llvm::AMDGPU;
31
32// Return the PAL metadata hardware shader stage name.
33static const char *getStageName(CallingConv::ID CC) {
34 switch (CC) {
35 case CallingConv::AMDGPU_PS:
36 return ".ps";
37 case CallingConv::AMDGPU_VS:
38 return ".vs";
39 case CallingConv::AMDGPU_GS:
40 return ".gs";
41 case CallingConv::AMDGPU_ES:
42 return ".es";
43 case CallingConv::AMDGPU_HS:
44 return ".hs";
45 case CallingConv::AMDGPU_LS:
46 return ".ls";
47 case CallingConv::AMDGPU_Gfx:
48 case CallingConv::AMDGPU_Gfx_WholeWave:
49 llvm_unreachable("Callable shader has no hardware stage");
50 default:
51 return ".cs";
52 }
53}
54
55// Read the PAL metadata from IR metadata, where it was put by the frontend.
56void AMDGPUPALMetadata::readFromIR(Module &M) {
57 auto *NamedMD = M.getNamedMetadata(Name: "amdgpu.pal.metadata.msgpack");
58 if (NamedMD && NamedMD->getNumOperands()) {
59 // This is the new msgpack format for metadata. It is a NamedMD containing
60 // an MDTuple containing an MDString containing the msgpack data.
61 BlobType = ELF::NT_AMDGPU_METADATA;
62 auto *MDN = dyn_cast<MDTuple>(Val: NamedMD->getOperand(i: 0));
63 if (MDN && MDN->getNumOperands()) {
64 if (auto *MDS = dyn_cast<MDString>(Val: MDN->getOperand(I: 0)))
65 setFromMsgPackBlob(MDS->getString());
66 }
67 return;
68 }
69 BlobType = ELF::NT_AMD_PAL_METADATA;
70 NamedMD = M.getNamedMetadata(Name: "amdgpu.pal.metadata");
71 if (!NamedMD || !NamedMD->getNumOperands()) {
72 // Emit msgpack metadata by default
73 BlobType = ELF::NT_AMDGPU_METADATA;
74 return;
75 }
76 // This is the old reg=value pair format for metadata. It is a NamedMD
77 // containing an MDTuple containing a number of MDNodes each of which is an
78 // integer value, and each two integer values forms a key=value pair that we
79 // store as Registers[key]=value in the map.
80 auto *Tuple = dyn_cast<MDTuple>(Val: NamedMD->getOperand(i: 0));
81 if (!Tuple)
82 return;
83 for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) {
84 auto *Key = mdconst::dyn_extract<ConstantInt>(MD: Tuple->getOperand(I));
85 auto *Val = mdconst::dyn_extract<ConstantInt>(MD: Tuple->getOperand(I: I + 1));
86 if (!Key || !Val)
87 continue;
88 setRegister(Reg: Key->getZExtValue(), Val: Val->getZExtValue());
89 }
90}
91
92// Set PAL metadata from a binary blob from the applicable .note record.
93// Returns false if bad format. Blob must remain valid for the lifetime of the
94// Metadata.
95bool AMDGPUPALMetadata::setFromBlob(unsigned Type, StringRef Blob) {
96 BlobType = Type;
97 if (Type == ELF::NT_AMD_PAL_METADATA)
98 return setFromLegacyBlob(Blob);
99 return setFromMsgPackBlob(Blob);
100}
101
102// Set PAL metadata from legacy (array of key=value pairs) blob.
103bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) {
104 const auto *Data = reinterpret_cast<const uint32_t *>(Blob.data());
105 for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I)
106 setRegister(Reg: Data[I * 2], Val: Data[I * 2 + 1]);
107 return true;
108}
109
110// Set PAL metadata from msgpack blob.
111bool AMDGPUPALMetadata::setFromMsgPackBlob(StringRef Blob) {
112 return MsgPackDoc.readFromBlob(Blob, /*Multi=*/false);
113}
114
115// Given the calling convention, calculate the register number for rsrc1. In
116// principle the register number could change in future hardware, but we know
117// it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so
118// we can use fixed values.
119static unsigned getRsrc1Reg(CallingConv::ID CC) {
120 switch (CC) {
121 default:
122 return PALMD::R_2E12_COMPUTE_PGM_RSRC1;
123 case CallingConv::AMDGPU_LS:
124 return PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS;
125 case CallingConv::AMDGPU_HS:
126 return PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS;
127 case CallingConv::AMDGPU_ES:
128 return PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES;
129 case CallingConv::AMDGPU_GS:
130 return PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS;
131 case CallingConv::AMDGPU_VS:
132 return PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS;
133 case CallingConv::AMDGPU_PS:
134 return PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS;
135 }
136}
137
138// Calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
139// with a constant offset to access any non-register shader-specific PAL
140// metadata key.
141static unsigned getScratchSizeKey(CallingConv::ID CC) {
142 switch (CC) {
143 case CallingConv::AMDGPU_PS:
144 return PALMD::Key::PS_SCRATCH_SIZE;
145 case CallingConv::AMDGPU_VS:
146 return PALMD::Key::VS_SCRATCH_SIZE;
147 case CallingConv::AMDGPU_GS:
148 return PALMD::Key::GS_SCRATCH_SIZE;
149 case CallingConv::AMDGPU_ES:
150 return PALMD::Key::ES_SCRATCH_SIZE;
151 case CallingConv::AMDGPU_HS:
152 return PALMD::Key::HS_SCRATCH_SIZE;
153 case CallingConv::AMDGPU_LS:
154 return PALMD::Key::LS_SCRATCH_SIZE;
155 default:
156 return PALMD::Key::CS_SCRATCH_SIZE;
157 }
158}
159
160// Set the rsrc1 register in the metadata for a particular shader stage.
161// In fact this ORs the value into any previous setting of the register.
162void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, unsigned Val) {
163 setRegister(Reg: getRsrc1Reg(CC), Val);
164}
165
166void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, const MCExpr *Val,
167 MCContext &Ctx) {
168 setRegister(Reg: getRsrc1Reg(CC), Val, Ctx);
169}
170
171// Set the rsrc2 register in the metadata for a particular shader stage.
172// In fact this ORs the value into any previous setting of the register.
173void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, unsigned Val) {
174 setRegister(Reg: getRsrc1Reg(CC) + 1, Val);
175}
176
177void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, const MCExpr *Val,
178 MCContext &Ctx) {
179 setRegister(Reg: getRsrc1Reg(CC) + 1, Val, Ctx);
180}
181
182// Set the SPI_PS_INPUT_ENA register in the metadata.
183// In fact this ORs the value into any previous setting of the register.
184void AMDGPUPALMetadata::setSpiPsInputEna(unsigned Val) {
185 setRegister(Reg: PALMD::R_A1B3_SPI_PS_INPUT_ENA, Val);
186}
187
188// Set the SPI_PS_INPUT_ADDR register in the metadata.
189// In fact this ORs the value into any previous setting of the register.
190void AMDGPUPALMetadata::setSpiPsInputAddr(unsigned Val) {
191 setRegister(Reg: PALMD::R_A1B4_SPI_PS_INPUT_ADDR, Val);
192}
193
194// Get a register from the metadata, or 0 if not currently set.
195unsigned AMDGPUPALMetadata::getRegister(unsigned Reg) {
196 auto Regs = getRegisters();
197 auto It = Regs.find(Key: MsgPackDoc.getNode(V: Reg));
198 if (It == Regs.end())
199 return 0;
200 auto N = It->second;
201 if (N.getKind() != msgpack::Type::UInt)
202 return 0;
203 return N.getUInt();
204}
205
206// Set a register in the metadata.
207// In fact this ORs the value into any previous setting of the register.
208void AMDGPUPALMetadata::setRegister(unsigned Reg, unsigned Val) {
209 if (!isLegacy()) {
210 // In the new MsgPack format, ignore register numbered >= 0x10000000. It
211 // is a PAL ABI pseudo-register in the old non-MsgPack format.
212 if (Reg >= 0x10000000)
213 return;
214 }
215 auto &N = getRegisters()[MsgPackDoc.getNode(V: Reg)];
216 if (N.getKind() == msgpack::Type::UInt)
217 Val |= N.getUInt();
218 N = N.getDocument()->getNode(V: Val);
219}
220
221// Set a register in the metadata.
222// In fact this ORs the value into any previous setting of the register.
223void AMDGPUPALMetadata::setRegister(unsigned Reg, const MCExpr *Val,
224 MCContext &Ctx) {
225 if (!isLegacy()) {
226 // In the new MsgPack format, ignore register numbered >= 0x10000000. It
227 // is a PAL ABI pseudo-register in the old non-MsgPack format.
228 if (Reg >= 0x10000000)
229 return;
230 }
231 auto &N = getRegisters()[MsgPackDoc.getNode(V: Reg)];
232 auto [ExprIt, Inserted] = REM.try_emplace(Key: Reg);
233
234 if (!Inserted) {
235 Val = MCBinaryExpr::createOr(LHS: Val, RHS: ExprIt->getSecond(), Ctx);
236 // This conditional may be redundant most of the time, but the alternate
237 // setRegister(unsigned, unsigned) could've been called while the
238 // conditional returns true (i.e., Reg exists in REM).
239 if (N.getKind() == msgpack::Type::UInt) {
240 const MCExpr *NExpr = MCConstantExpr::create(Value: N.getUInt(), Ctx);
241 Val = MCBinaryExpr::createOr(LHS: Val, RHS: NExpr, Ctx);
242 }
243 } else if (N.getKind() == msgpack::Type::UInt) {
244 const MCExpr *NExpr = MCConstantExpr::create(Value: N.getUInt(), Ctx);
245 Val = MCBinaryExpr::createOr(LHS: Val, RHS: NExpr, Ctx);
246 } else {
247 // Default to uint64_t 0 so additional calls to setRegister will allow
248 // propagate ORs.
249 N = (uint64_t)0;
250 }
251 ExprIt->second = Val;
252 DelayedExprs.assignDocNode(DN&: N, Type: msgpack::Type::UInt, ExprValue: Val);
253}
254
255// Set the entry point name for one shader.
256void AMDGPUPALMetadata::setEntryPoint(unsigned CC, StringRef Name) {
257 if (isLegacy())
258 return;
259 // Msgpack format.
260 // Entry point is updated to .entry_point_symbol and is set to the function
261 // name
262 getHwStage(CC)[".entry_point_symbol"] =
263 MsgPackDoc.getNode(V: Name, /*Copy=*/true);
264
265 // For PAL version 3.6 and above, entry_point is no longer required.
266 if (getPALVersion() < VersionTuple(3, 6)) {
267 // Set .entry_point which is defined to be _amdgpu_<stage>_main and
268 // _amdgpu_cs_main for non-shader functions.
269 SmallString<16> EPName("_amdgpu_");
270 raw_svector_ostream EPNameOS(EPName);
271 EPNameOS << getStageName(CC) + 1 << "_main";
272 getHwStage(CC)[".entry_point"] =
273 MsgPackDoc.getNode(V: EPNameOS.str(), /*Copy=*/true);
274 }
275}
276
277// Set the number of used vgprs in the metadata. This is an optional
278// advisory record for logging etc; wave dispatch actually uses the rsrc1
279// register for the shader stage to determine the number of vgprs to
280// allocate.
281void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, unsigned Val) {
282 if (isLegacy()) {
283 // Old non-msgpack format.
284 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) +
285 PALMD::Key::VS_NUM_USED_VGPRS -
286 PALMD::Key::VS_SCRATCH_SIZE;
287 setRegister(Reg: NumUsedVgprsKey, Val);
288 return;
289 }
290 // Msgpack format.
291 getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(V: Val);
292}
293
294void AMDGPUPALMetadata::setNumUsedVgprs(CallingConv::ID CC, const MCExpr *Val,
295 MCContext &Ctx) {
296 if (isLegacy()) {
297 // Old non-msgpack format.
298 unsigned NumUsedVgprsKey = getScratchSizeKey(CC) +
299 PALMD::Key::VS_NUM_USED_VGPRS -
300 PALMD::Key::VS_SCRATCH_SIZE;
301 setRegister(Reg: NumUsedVgprsKey, Val, Ctx);
302 return;
303 }
304 // Msgpack format.
305 setHwStage(CC, field: ".vgpr_count", Type: msgpack::Type::UInt, Val);
306}
307
308// Set the number of used agprs in the metadata.
309void AMDGPUPALMetadata::setNumUsedAgprs(CallingConv::ID CC, unsigned Val) {
310 getHwStage(CC)[".agpr_count"] = Val;
311}
312
313void AMDGPUPALMetadata::setNumUsedAgprs(unsigned CC, const MCExpr *Val) {
314 setHwStage(CC, field: ".agpr_count", Type: msgpack::Type::UInt, Val);
315}
316
317// Set the number of used sgprs in the metadata. This is an optional advisory
318// record for logging etc; wave dispatch actually uses the rsrc1 register for
319// the shader stage to determine the number of sgprs to allocate.
320void AMDGPUPALMetadata::setNumUsedSgprs(CallingConv::ID CC, unsigned Val) {
321 if (isLegacy()) {
322 // Old non-msgpack format.
323 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) +
324 PALMD::Key::VS_NUM_USED_SGPRS -
325 PALMD::Key::VS_SCRATCH_SIZE;
326 setRegister(Reg: NumUsedSgprsKey, Val);
327 return;
328 }
329 // Msgpack format.
330 getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(V: Val);
331}
332
333void AMDGPUPALMetadata::setNumUsedSgprs(unsigned CC, const MCExpr *Val,
334 MCContext &Ctx) {
335 if (isLegacy()) {
336 // Old non-msgpack format.
337 unsigned NumUsedSgprsKey = getScratchSizeKey(CC) +
338 PALMD::Key::VS_NUM_USED_SGPRS -
339 PALMD::Key::VS_SCRATCH_SIZE;
340 setRegister(Reg: NumUsedSgprsKey, Val, Ctx);
341 return;
342 }
343 // Msgpack format.
344 setHwStage(CC, field: ".sgpr_count", Type: msgpack::Type::UInt, Val);
345}
346
347// Set the scratch size in the metadata.
348void AMDGPUPALMetadata::setScratchSize(CallingConv::ID CC, unsigned Val) {
349 if (isLegacy()) {
350 // Old non-msgpack format.
351 setRegister(Reg: getScratchSizeKey(CC), Val);
352 return;
353 }
354 // Msgpack format.
355 getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(V: Val);
356}
357
358void AMDGPUPALMetadata::setScratchSize(unsigned CC, const MCExpr *Val,
359 MCContext &Ctx) {
360 if (isLegacy()) {
361 // Old non-msgpack format.
362 setRegister(Reg: getScratchSizeKey(CC), Val, Ctx);
363 return;
364 }
365 // Msgpack format.
366 setHwStage(CC, field: ".scratch_memory_size", Type: msgpack::Type::UInt, Val);
367}
368
369// Set the stack frame size of a function in the metadata.
370void AMDGPUPALMetadata::setFunctionScratchSize(StringRef FnName, unsigned Val) {
371 auto Node = getShaderFunction(Name: FnName);
372 Node[".stack_frame_size_in_bytes"] = MsgPackDoc.getNode(V: Val);
373 Node[".backend_stack_size"] = MsgPackDoc.getNode(V: Val);
374}
375
376// Set the amount of LDS used in bytes in the metadata.
377void AMDGPUPALMetadata::setFunctionLdsSize(StringRef FnName, unsigned Val) {
378 auto Node = getShaderFunction(Name: FnName);
379 Node[".lds_size"] = MsgPackDoc.getNode(V: Val);
380}
381
382// Set the number of used vgprs in the metadata.
383void AMDGPUPALMetadata::setFunctionNumUsedVgprs(StringRef FnName,
384 unsigned Val) {
385 auto Node = getShaderFunction(Name: FnName);
386 Node[".vgpr_count"] = MsgPackDoc.getNode(V: Val);
387}
388
389void AMDGPUPALMetadata::setFunctionNumUsedVgprs(StringRef FnName,
390 const MCExpr *Val) {
391 auto Node = getShaderFunction(Name: FnName);
392 DelayedExprs.assignDocNode(DN&: Node[".vgpr_count"], Type: msgpack::Type::UInt, ExprValue: Val);
393}
394
395// Set the number of used vgprs in the metadata.
396void AMDGPUPALMetadata::setFunctionNumUsedSgprs(StringRef FnName,
397 unsigned Val) {
398 auto Node = getShaderFunction(Name: FnName);
399 Node[".sgpr_count"] = MsgPackDoc.getNode(V: Val);
400}
401
402void AMDGPUPALMetadata::setFunctionNumUsedSgprs(StringRef FnName,
403 const MCExpr *Val) {
404 auto Node = getShaderFunction(Name: FnName);
405 DelayedExprs.assignDocNode(DN&: Node[".sgpr_count"], Type: msgpack::Type::UInt, ExprValue: Val);
406}
407
408// Set the hardware register bit in PAL metadata to enable wave32 on the
409// shader of the given calling convention.
410void AMDGPUPALMetadata::setWave32(unsigned CC) {
411 switch (CC) {
412 case CallingConv::AMDGPU_HS:
413 setRegister(Reg: PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_HS_W32_EN(1));
414 break;
415 case CallingConv::AMDGPU_GS:
416 setRegister(Reg: PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_GS_W32_EN(1));
417 break;
418 case CallingConv::AMDGPU_VS:
419 setRegister(Reg: PALMD::R_A2D5_VGT_SHADER_STAGES_EN, S_028B54_VS_W32_EN(1));
420 break;
421 case CallingConv::AMDGPU_PS:
422 setRegister(Reg: PALMD::R_A1B6_SPI_PS_IN_CONTROL, S_0286D8_PS_W32_EN(1));
423 break;
424 case CallingConv::AMDGPU_CS:
425 setRegister(Reg: PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR,
426 S_00B800_CS_W32_EN(1));
427 break;
428 }
429}
430
431// Convert a register number to name, for display by toString().
432// Returns nullptr if none.
433static StringRef getRegisterName(unsigned RegNum) {
434 // Table of registers.
435 constexpr EnumStringDef<uint16_t> RegInfoTableDefs[] = {
436 // Registers that code generation sets/modifies metadata for.
437 {.Names: {"SPI_SHADER_PGM_RSRC1_VS"}, .Value: PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS},
438 {.Names: {"SPI_SHADER_PGM_RSRC2_VS"}, .Value: PALMD::R_2C4A_SPI_SHADER_PGM_RSRC1_VS + 1},
439 {.Names: {"SPI_SHADER_PGM_RSRC1_LS"}, .Value: PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS},
440 {.Names: {"SPI_SHADER_PGM_RSRC2_LS"}, .Value: PALMD::R_2D4A_SPI_SHADER_PGM_RSRC1_LS + 1},
441 {.Names: {"SPI_SHADER_PGM_RSRC1_HS"}, .Value: PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS},
442 {.Names: {"SPI_SHADER_PGM_RSRC2_HS"}, .Value: PALMD::R_2D0A_SPI_SHADER_PGM_RSRC1_HS + 1},
443 {.Names: {"SPI_SHADER_PGM_RSRC1_ES"}, .Value: PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES},
444 {.Names: {"SPI_SHADER_PGM_RSRC2_ES"}, .Value: PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1},
445 {.Names: {"SPI_SHADER_PGM_RSRC1_GS"}, .Value: PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS},
446 {.Names: {"SPI_SHADER_PGM_RSRC2_GS"}, .Value: PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1},
447 {.Names: {"COMPUTE_DISPATCH_INITIATOR"},
448 .Value: PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR},
449 {.Names: {"COMPUTE_PGM_RSRC1"}, .Value: PALMD::R_2E12_COMPUTE_PGM_RSRC1},
450 {.Names: {"COMPUTE_PGM_RSRC2"}, .Value: PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1},
451 {.Names: {"SPI_SHADER_PGM_RSRC1_PS"}, .Value: PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS},
452 {.Names: {"SPI_SHADER_PGM_RSRC2_PS"}, .Value: PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1},
453 {.Names: {"SPI_PS_INPUT_ENA"}, .Value: PALMD::R_A1B3_SPI_PS_INPUT_ENA},
454 {.Names: {"SPI_PS_INPUT_ADDR"}, .Value: PALMD::R_A1B4_SPI_PS_INPUT_ADDR},
455 {.Names: {"SPI_PS_IN_CONTROL"}, .Value: PALMD::R_A1B6_SPI_PS_IN_CONTROL},
456 {.Names: {"VGT_SHADER_STAGES_EN"}, .Value: PALMD::R_A2D5_VGT_SHADER_STAGES_EN},
457
458 // Registers not known to code generation.
459 {.Names: {"SPI_SHADER_PGM_RSRC3_PS"}, .Value: 0x2c07},
460 {.Names: {"SPI_SHADER_PGM_RSRC3_VS"}, .Value: 0x2c46},
461 {.Names: {"SPI_SHADER_PGM_RSRC3_GS"}, .Value: 0x2c87},
462 {.Names: {"SPI_SHADER_PGM_RSRC3_ES"}, .Value: 0x2cc7},
463 {.Names: {"SPI_SHADER_PGM_RSRC3_HS"}, .Value: 0x2d07},
464 {.Names: {"SPI_SHADER_PGM_RSRC3_LS"}, .Value: 0x2d47},
465
466 {.Names: {"SPI_SHADER_POS_FORMAT"}, .Value: 0xa1c3},
467 {.Names: {"SPI_VS_OUT_CONFIG"}, .Value: 0xa1b1},
468 {.Names: {"PA_CL_VS_OUT_CNTL"}, .Value: 0xa207},
469 {.Names: {"PA_CL_CLIP_CNTL"}, .Value: 0xa204},
470 {.Names: {"PA_CL_VTE_CNTL"}, .Value: 0xa206},
471 {.Names: {"PA_SU_VTX_CNTL"}, .Value: 0xa2f9},
472 {.Names: {"PA_SC_MODE_CNTL_1"}, .Value: 0xa293},
473 {.Names: {"VGT_PRIMITIVEID_EN"}, .Value: 0xa2a1},
474 {.Names: {"SPI_SHADER_PGM_RSRC4_GS"}, .Value: 0x2c81},
475 {.Names: {"COMPUTE_TMPRING_SIZE"}, .Value: 0x2e18},
476 {.Names: {"SPI_INTERP_CONTROL_0"}, .Value: 0xa1b5},
477 {.Names: {"SPI_TMPRING_SIZE"}, .Value: 0xa1ba},
478 {.Names: {"SPI_SHADER_Z_FORMAT"}, .Value: 0xa1c4},
479 {.Names: {"SPI_SHADER_COL_FORMAT"}, .Value: 0xa1c5},
480 {.Names: {"DB_SHADER_CONTROL"}, .Value: 0xa203},
481 {.Names: {"CB_SHADER_MASK"}, .Value: 0xa08f},
482 {.Names: {"SPI_PS_INPUT_CNTL_0"}, .Value: 0xa191},
483 {.Names: {"SPI_PS_INPUT_CNTL_1"}, .Value: 0xa192},
484 {.Names: {"SPI_PS_INPUT_CNTL_2"}, .Value: 0xa193},
485 {.Names: {"SPI_PS_INPUT_CNTL_3"}, .Value: 0xa194},
486 {.Names: {"SPI_PS_INPUT_CNTL_4"}, .Value: 0xa195},
487 {.Names: {"SPI_PS_INPUT_CNTL_5"}, .Value: 0xa196},
488 {.Names: {"SPI_PS_INPUT_CNTL_6"}, .Value: 0xa197},
489 {.Names: {"SPI_PS_INPUT_CNTL_7"}, .Value: 0xa198},
490 {.Names: {"SPI_PS_INPUT_CNTL_8"}, .Value: 0xa199},
491 {.Names: {"SPI_PS_INPUT_CNTL_9"}, .Value: 0xa19a},
492 {.Names: {"SPI_PS_INPUT_CNTL_10"}, .Value: 0xa19b},
493 {.Names: {"SPI_PS_INPUT_CNTL_11"}, .Value: 0xa19c},
494 {.Names: {"SPI_PS_INPUT_CNTL_12"}, .Value: 0xa19d},
495 {.Names: {"SPI_PS_INPUT_CNTL_13"}, .Value: 0xa19e},
496 {.Names: {"SPI_PS_INPUT_CNTL_14"}, .Value: 0xa19f},
497 {.Names: {"SPI_PS_INPUT_CNTL_15"}, .Value: 0xa1a0},
498 {.Names: {"SPI_PS_INPUT_CNTL_16"}, .Value: 0xa1a1},
499 {.Names: {"SPI_PS_INPUT_CNTL_17"}, .Value: 0xa1a2},
500 {.Names: {"SPI_PS_INPUT_CNTL_18"}, .Value: 0xa1a3},
501 {.Names: {"SPI_PS_INPUT_CNTL_19"}, .Value: 0xa1a4},
502 {.Names: {"SPI_PS_INPUT_CNTL_20"}, .Value: 0xa1a5},
503 {.Names: {"SPI_PS_INPUT_CNTL_21"}, .Value: 0xa1a6},
504 {.Names: {"SPI_PS_INPUT_CNTL_22"}, .Value: 0xa1a7},
505 {.Names: {"SPI_PS_INPUT_CNTL_23"}, .Value: 0xa1a8},
506 {.Names: {"SPI_PS_INPUT_CNTL_24"}, .Value: 0xa1a9},
507 {.Names: {"SPI_PS_INPUT_CNTL_25"}, .Value: 0xa1aa},
508 {.Names: {"SPI_PS_INPUT_CNTL_26"}, .Value: 0xa1ab},
509 {.Names: {"SPI_PS_INPUT_CNTL_27"}, .Value: 0xa1ac},
510 {.Names: {"SPI_PS_INPUT_CNTL_28"}, .Value: 0xa1ad},
511 {.Names: {"SPI_PS_INPUT_CNTL_29"}, .Value: 0xa1ae},
512 {.Names: {"SPI_PS_INPUT_CNTL_30"}, .Value: 0xa1af},
513 {.Names: {"SPI_PS_INPUT_CNTL_31"}, .Value: 0xa1b0},
514
515 {.Names: {"VGT_GS_MAX_VERT_OUT"}, .Value: 0xa2ce},
516 {.Names: {"VGT_ESGS_RING_ITEMSIZE"}, .Value: 0xa2ab},
517 {.Names: {"VGT_GS_MODE"}, .Value: 0xa290},
518 {.Names: {"VGT_GS_ONCHIP_CNTL"}, .Value: 0xa291},
519 {.Names: {"VGT_GS_VERT_ITEMSIZE"}, .Value: 0xa2d7},
520 {.Names: {"VGT_GS_VERT_ITEMSIZE_1"}, .Value: 0xa2d8},
521 {.Names: {"VGT_GS_VERT_ITEMSIZE_2"}, .Value: 0xa2d9},
522 {.Names: {"VGT_GS_VERT_ITEMSIZE_3"}, .Value: 0xa2da},
523 {.Names: {"VGT_GSVS_RING_OFFSET_1"}, .Value: 0xa298},
524 {.Names: {"VGT_GSVS_RING_OFFSET_2"}, .Value: 0xa299},
525 {.Names: {"VGT_GSVS_RING_OFFSET_3"}, .Value: 0xa29a},
526
527 {.Names: {"VGT_GS_INSTANCE_CNT"}, .Value: 0xa2e4},
528 {.Names: {"VGT_GS_PER_VS"}, .Value: 0xa297},
529 {.Names: {"VGT_GS_OUT_PRIM_TYPE"}, .Value: 0xa29b},
530 {.Names: {"VGT_GSVS_RING_ITEMSIZE"}, .Value: 0xa2ac},
531
532 {.Names: {"VGT_REUSE_OFF"}, .Value: 0xa2ad},
533 {.Names: {"SPI_BARYC_CNTL"}, .Value: 0xa1b8},
534
535 {.Names: {"SPI_SHADER_USER_DATA_VS_0"}, .Value: 0x2c4c},
536 {.Names: {"SPI_SHADER_USER_DATA_VS_1"}, .Value: 0x2c4d},
537 {.Names: {"SPI_SHADER_USER_DATA_VS_2"}, .Value: 0x2c4e},
538 {.Names: {"SPI_SHADER_USER_DATA_VS_3"}, .Value: 0x2c4f},
539 {.Names: {"SPI_SHADER_USER_DATA_VS_4"}, .Value: 0x2c50},
540 {.Names: {"SPI_SHADER_USER_DATA_VS_5"}, .Value: 0x2c51},
541 {.Names: {"SPI_SHADER_USER_DATA_VS_6"}, .Value: 0x2c52},
542 {.Names: {"SPI_SHADER_USER_DATA_VS_7"}, .Value: 0x2c53},
543 {.Names: {"SPI_SHADER_USER_DATA_VS_8"}, .Value: 0x2c54},
544 {.Names: {"SPI_SHADER_USER_DATA_VS_9"}, .Value: 0x2c55},
545 {.Names: {"SPI_SHADER_USER_DATA_VS_10"}, .Value: 0x2c56},
546 {.Names: {"SPI_SHADER_USER_DATA_VS_11"}, .Value: 0x2c57},
547 {.Names: {"SPI_SHADER_USER_DATA_VS_12"}, .Value: 0x2c58},
548 {.Names: {"SPI_SHADER_USER_DATA_VS_13"}, .Value: 0x2c59},
549 {.Names: {"SPI_SHADER_USER_DATA_VS_14"}, .Value: 0x2c5a},
550 {.Names: {"SPI_SHADER_USER_DATA_VS_15"}, .Value: 0x2c5b},
551 {.Names: {"SPI_SHADER_USER_DATA_VS_16"}, .Value: 0x2c5c},
552 {.Names: {"SPI_SHADER_USER_DATA_VS_17"}, .Value: 0x2c5d},
553 {.Names: {"SPI_SHADER_USER_DATA_VS_18"}, .Value: 0x2c5e},
554 {.Names: {"SPI_SHADER_USER_DATA_VS_19"}, .Value: 0x2c5f},
555 {.Names: {"SPI_SHADER_USER_DATA_VS_20"}, .Value: 0x2c60},
556 {.Names: {"SPI_SHADER_USER_DATA_VS_21"}, .Value: 0x2c61},
557 {.Names: {"SPI_SHADER_USER_DATA_VS_22"}, .Value: 0x2c62},
558 {.Names: {"SPI_SHADER_USER_DATA_VS_23"}, .Value: 0x2c63},
559 {.Names: {"SPI_SHADER_USER_DATA_VS_24"}, .Value: 0x2c64},
560 {.Names: {"SPI_SHADER_USER_DATA_VS_25"}, .Value: 0x2c65},
561 {.Names: {"SPI_SHADER_USER_DATA_VS_26"}, .Value: 0x2c66},
562 {.Names: {"SPI_SHADER_USER_DATA_VS_27"}, .Value: 0x2c67},
563 {.Names: {"SPI_SHADER_USER_DATA_VS_28"}, .Value: 0x2c68},
564 {.Names: {"SPI_SHADER_USER_DATA_VS_29"}, .Value: 0x2c69},
565 {.Names: {"SPI_SHADER_USER_DATA_VS_30"}, .Value: 0x2c6a},
566 {.Names: {"SPI_SHADER_USER_DATA_VS_31"}, .Value: 0x2c6b},
567
568 {.Names: {"SPI_SHADER_USER_DATA_GS_0"}, .Value: 0x2c8c},
569 {.Names: {"SPI_SHADER_USER_DATA_GS_1"}, .Value: 0x2c8d},
570 {.Names: {"SPI_SHADER_USER_DATA_GS_2"}, .Value: 0x2c8e},
571 {.Names: {"SPI_SHADER_USER_DATA_GS_3"}, .Value: 0x2c8f},
572 {.Names: {"SPI_SHADER_USER_DATA_GS_4"}, .Value: 0x2c90},
573 {.Names: {"SPI_SHADER_USER_DATA_GS_5"}, .Value: 0x2c91},
574 {.Names: {"SPI_SHADER_USER_DATA_GS_6"}, .Value: 0x2c92},
575 {.Names: {"SPI_SHADER_USER_DATA_GS_7"}, .Value: 0x2c93},
576 {.Names: {"SPI_SHADER_USER_DATA_GS_8"}, .Value: 0x2c94},
577 {.Names: {"SPI_SHADER_USER_DATA_GS_9"}, .Value: 0x2c95},
578 {.Names: {"SPI_SHADER_USER_DATA_GS_10"}, .Value: 0x2c96},
579 {.Names: {"SPI_SHADER_USER_DATA_GS_11"}, .Value: 0x2c97},
580 {.Names: {"SPI_SHADER_USER_DATA_GS_12"}, .Value: 0x2c98},
581 {.Names: {"SPI_SHADER_USER_DATA_GS_13"}, .Value: 0x2c99},
582 {.Names: {"SPI_SHADER_USER_DATA_GS_14"}, .Value: 0x2c9a},
583 {.Names: {"SPI_SHADER_USER_DATA_GS_15"}, .Value: 0x2c9b},
584 {.Names: {"SPI_SHADER_USER_DATA_GS_16"}, .Value: 0x2c9c},
585 {.Names: {"SPI_SHADER_USER_DATA_GS_17"}, .Value: 0x2c9d},
586 {.Names: {"SPI_SHADER_USER_DATA_GS_18"}, .Value: 0x2c9e},
587 {.Names: {"SPI_SHADER_USER_DATA_GS_19"}, .Value: 0x2c9f},
588 {.Names: {"SPI_SHADER_USER_DATA_GS_20"}, .Value: 0x2ca0},
589 {.Names: {"SPI_SHADER_USER_DATA_GS_21"}, .Value: 0x2ca1},
590 {.Names: {"SPI_SHADER_USER_DATA_GS_22"}, .Value: 0x2ca2},
591 {.Names: {"SPI_SHADER_USER_DATA_GS_23"}, .Value: 0x2ca3},
592 {.Names: {"SPI_SHADER_USER_DATA_GS_24"}, .Value: 0x2ca4},
593 {.Names: {"SPI_SHADER_USER_DATA_GS_25"}, .Value: 0x2ca5},
594 {.Names: {"SPI_SHADER_USER_DATA_GS_26"}, .Value: 0x2ca6},
595 {.Names: {"SPI_SHADER_USER_DATA_GS_27"}, .Value: 0x2ca7},
596 {.Names: {"SPI_SHADER_USER_DATA_GS_28"}, .Value: 0x2ca8},
597 {.Names: {"SPI_SHADER_USER_DATA_GS_29"}, .Value: 0x2ca9},
598 {.Names: {"SPI_SHADER_USER_DATA_GS_30"}, .Value: 0x2caa},
599 {.Names: {"SPI_SHADER_USER_DATA_GS_31"}, .Value: 0x2cab},
600
601 {.Names: {"SPI_SHADER_USER_DATA_ES_0"}, .Value: 0x2ccc},
602 {.Names: {"SPI_SHADER_USER_DATA_ES_1"}, .Value: 0x2ccd},
603 {.Names: {"SPI_SHADER_USER_DATA_ES_2"}, .Value: 0x2cce},
604 {.Names: {"SPI_SHADER_USER_DATA_ES_3"}, .Value: 0x2ccf},
605 {.Names: {"SPI_SHADER_USER_DATA_ES_4"}, .Value: 0x2cd0},
606 {.Names: {"SPI_SHADER_USER_DATA_ES_5"}, .Value: 0x2cd1},
607 {.Names: {"SPI_SHADER_USER_DATA_ES_6"}, .Value: 0x2cd2},
608 {.Names: {"SPI_SHADER_USER_DATA_ES_7"}, .Value: 0x2cd3},
609 {.Names: {"SPI_SHADER_USER_DATA_ES_8"}, .Value: 0x2cd4},
610 {.Names: {"SPI_SHADER_USER_DATA_ES_9"}, .Value: 0x2cd5},
611 {.Names: {"SPI_SHADER_USER_DATA_ES_10"}, .Value: 0x2cd6},
612 {.Names: {"SPI_SHADER_USER_DATA_ES_11"}, .Value: 0x2cd7},
613 {.Names: {"SPI_SHADER_USER_DATA_ES_12"}, .Value: 0x2cd8},
614 {.Names: {"SPI_SHADER_USER_DATA_ES_13"}, .Value: 0x2cd9},
615 {.Names: {"SPI_SHADER_USER_DATA_ES_14"}, .Value: 0x2cda},
616 {.Names: {"SPI_SHADER_USER_DATA_ES_15"}, .Value: 0x2cdb},
617 {.Names: {"SPI_SHADER_USER_DATA_ES_16"}, .Value: 0x2cdc},
618 {.Names: {"SPI_SHADER_USER_DATA_ES_17"}, .Value: 0x2cdd},
619 {.Names: {"SPI_SHADER_USER_DATA_ES_18"}, .Value: 0x2cde},
620 {.Names: {"SPI_SHADER_USER_DATA_ES_19"}, .Value: 0x2cdf},
621 {.Names: {"SPI_SHADER_USER_DATA_ES_20"}, .Value: 0x2ce0},
622 {.Names: {"SPI_SHADER_USER_DATA_ES_21"}, .Value: 0x2ce1},
623 {.Names: {"SPI_SHADER_USER_DATA_ES_22"}, .Value: 0x2ce2},
624 {.Names: {"SPI_SHADER_USER_DATA_ES_23"}, .Value: 0x2ce3},
625 {.Names: {"SPI_SHADER_USER_DATA_ES_24"}, .Value: 0x2ce4},
626 {.Names: {"SPI_SHADER_USER_DATA_ES_25"}, .Value: 0x2ce5},
627 {.Names: {"SPI_SHADER_USER_DATA_ES_26"}, .Value: 0x2ce6},
628 {.Names: {"SPI_SHADER_USER_DATA_ES_27"}, .Value: 0x2ce7},
629 {.Names: {"SPI_SHADER_USER_DATA_ES_28"}, .Value: 0x2ce8},
630 {.Names: {"SPI_SHADER_USER_DATA_ES_29"}, .Value: 0x2ce9},
631 {.Names: {"SPI_SHADER_USER_DATA_ES_30"}, .Value: 0x2cea},
632 {.Names: {"SPI_SHADER_USER_DATA_ES_31"}, .Value: 0x2ceb},
633
634 {.Names: {"SPI_SHADER_USER_DATA_PS_0"}, .Value: 0x2c0c},
635 {.Names: {"SPI_SHADER_USER_DATA_PS_1"}, .Value: 0x2c0d},
636 {.Names: {"SPI_SHADER_USER_DATA_PS_2"}, .Value: 0x2c0e},
637 {.Names: {"SPI_SHADER_USER_DATA_PS_3"}, .Value: 0x2c0f},
638 {.Names: {"SPI_SHADER_USER_DATA_PS_4"}, .Value: 0x2c10},
639 {.Names: {"SPI_SHADER_USER_DATA_PS_5"}, .Value: 0x2c11},
640 {.Names: {"SPI_SHADER_USER_DATA_PS_6"}, .Value: 0x2c12},
641 {.Names: {"SPI_SHADER_USER_DATA_PS_7"}, .Value: 0x2c13},
642 {.Names: {"SPI_SHADER_USER_DATA_PS_8"}, .Value: 0x2c14},
643 {.Names: {"SPI_SHADER_USER_DATA_PS_9"}, .Value: 0x2c15},
644 {.Names: {"SPI_SHADER_USER_DATA_PS_10"}, .Value: 0x2c16},
645 {.Names: {"SPI_SHADER_USER_DATA_PS_11"}, .Value: 0x2c17},
646 {.Names: {"SPI_SHADER_USER_DATA_PS_12"}, .Value: 0x2c18},
647 {.Names: {"SPI_SHADER_USER_DATA_PS_13"}, .Value: 0x2c19},
648 {.Names: {"SPI_SHADER_USER_DATA_PS_14"}, .Value: 0x2c1a},
649 {.Names: {"SPI_SHADER_USER_DATA_PS_15"}, .Value: 0x2c1b},
650 {.Names: {"SPI_SHADER_USER_DATA_PS_16"}, .Value: 0x2c1c},
651 {.Names: {"SPI_SHADER_USER_DATA_PS_17"}, .Value: 0x2c1d},
652 {.Names: {"SPI_SHADER_USER_DATA_PS_18"}, .Value: 0x2c1e},
653 {.Names: {"SPI_SHADER_USER_DATA_PS_19"}, .Value: 0x2c1f},
654 {.Names: {"SPI_SHADER_USER_DATA_PS_20"}, .Value: 0x2c20},
655 {.Names: {"SPI_SHADER_USER_DATA_PS_21"}, .Value: 0x2c21},
656 {.Names: {"SPI_SHADER_USER_DATA_PS_22"}, .Value: 0x2c22},
657 {.Names: {"SPI_SHADER_USER_DATA_PS_23"}, .Value: 0x2c23},
658 {.Names: {"SPI_SHADER_USER_DATA_PS_24"}, .Value: 0x2c24},
659 {.Names: {"SPI_SHADER_USER_DATA_PS_25"}, .Value: 0x2c25},
660 {.Names: {"SPI_SHADER_USER_DATA_PS_26"}, .Value: 0x2c26},
661 {.Names: {"SPI_SHADER_USER_DATA_PS_27"}, .Value: 0x2c27},
662 {.Names: {"SPI_SHADER_USER_DATA_PS_28"}, .Value: 0x2c28},
663 {.Names: {"SPI_SHADER_USER_DATA_PS_29"}, .Value: 0x2c29},
664 {.Names: {"SPI_SHADER_USER_DATA_PS_30"}, .Value: 0x2c2a},
665 {.Names: {"SPI_SHADER_USER_DATA_PS_31"}, .Value: 0x2c2b},
666
667 {.Names: {"COMPUTE_USER_DATA_0"}, .Value: 0x2e40},
668 {.Names: {"COMPUTE_USER_DATA_1"}, .Value: 0x2e41},
669 {.Names: {"COMPUTE_USER_DATA_2"}, .Value: 0x2e42},
670 {.Names: {"COMPUTE_USER_DATA_3"}, .Value: 0x2e43},
671 {.Names: {"COMPUTE_USER_DATA_4"}, .Value: 0x2e44},
672 {.Names: {"COMPUTE_USER_DATA_5"}, .Value: 0x2e45},
673 {.Names: {"COMPUTE_USER_DATA_6"}, .Value: 0x2e46},
674 {.Names: {"COMPUTE_USER_DATA_7"}, .Value: 0x2e47},
675 {.Names: {"COMPUTE_USER_DATA_8"}, .Value: 0x2e48},
676 {.Names: {"COMPUTE_USER_DATA_9"}, .Value: 0x2e49},
677 {.Names: {"COMPUTE_USER_DATA_10"}, .Value: 0x2e4a},
678 {.Names: {"COMPUTE_USER_DATA_11"}, .Value: 0x2e4b},
679 {.Names: {"COMPUTE_USER_DATA_12"}, .Value: 0x2e4c},
680 {.Names: {"COMPUTE_USER_DATA_13"}, .Value: 0x2e4d},
681 {.Names: {"COMPUTE_USER_DATA_14"}, .Value: 0x2e4e},
682 {.Names: {"COMPUTE_USER_DATA_15"}, .Value: 0x2e4f},
683 {.Names: {"COMPUTE_USER_DATA_16"}, .Value: 0x2e50},
684 {.Names: {"COMPUTE_USER_DATA_17"}, .Value: 0x2e51},
685 {.Names: {"COMPUTE_USER_DATA_18"}, .Value: 0x2e52},
686 {.Names: {"COMPUTE_USER_DATA_19"}, .Value: 0x2e53},
687 {.Names: {"COMPUTE_USER_DATA_20"}, .Value: 0x2e54},
688 {.Names: {"COMPUTE_USER_DATA_21"}, .Value: 0x2e55},
689 {.Names: {"COMPUTE_USER_DATA_22"}, .Value: 0x2e56},
690 {.Names: {"COMPUTE_USER_DATA_23"}, .Value: 0x2e57},
691 {.Names: {"COMPUTE_USER_DATA_24"}, .Value: 0x2e58},
692 {.Names: {"COMPUTE_USER_DATA_25"}, .Value: 0x2e59},
693 {.Names: {"COMPUTE_USER_DATA_26"}, .Value: 0x2e5a},
694 {.Names: {"COMPUTE_USER_DATA_27"}, .Value: 0x2e5b},
695 {.Names: {"COMPUTE_USER_DATA_28"}, .Value: 0x2e5c},
696 {.Names: {"COMPUTE_USER_DATA_29"}, .Value: 0x2e5d},
697 {.Names: {"COMPUTE_USER_DATA_30"}, .Value: 0x2e5e},
698 {.Names: {"COMPUTE_USER_DATA_31"}, .Value: 0x2e5f},
699
700 {.Names: {"COMPUTE_NUM_THREAD_X"}, .Value: 0x2e07},
701 {.Names: {"COMPUTE_NUM_THREAD_Y"}, .Value: 0x2e08},
702 {.Names: {"COMPUTE_NUM_THREAD_Z"}, .Value: 0x2e09},
703 {.Names: {"VGT_TF_PARAM"}, .Value: 0xa2db},
704 {.Names: {"VGT_LS_HS_CONFIG"}, .Value: 0xa2d6},
705 {.Names: {"VGT_HOS_MIN_TESS_LEVEL"}, .Value: 0xa287},
706 {.Names: {"VGT_HOS_MAX_TESS_LEVEL"}, .Value: 0xa286},
707 {.Names: {"PA_SC_AA_CONFIG"}, .Value: 0xa2f8},
708 {.Names: {"PA_SC_SHADER_CONTROL"}, .Value: 0xa310},
709 {.Names: {"PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"}, .Value: 0xa313},
710
711 {.Names: {"SPI_SHADER_USER_DATA_HS_0"}, .Value: 0x2d0c},
712 {.Names: {"SPI_SHADER_USER_DATA_HS_1"}, .Value: 0x2d0d},
713 {.Names: {"SPI_SHADER_USER_DATA_HS_2"}, .Value: 0x2d0e},
714 {.Names: {"SPI_SHADER_USER_DATA_HS_3"}, .Value: 0x2d0f},
715 {.Names: {"SPI_SHADER_USER_DATA_HS_4"}, .Value: 0x2d10},
716 {.Names: {"SPI_SHADER_USER_DATA_HS_5"}, .Value: 0x2d11},
717 {.Names: {"SPI_SHADER_USER_DATA_HS_6"}, .Value: 0x2d12},
718 {.Names: {"SPI_SHADER_USER_DATA_HS_7"}, .Value: 0x2d13},
719 {.Names: {"SPI_SHADER_USER_DATA_HS_8"}, .Value: 0x2d14},
720 {.Names: {"SPI_SHADER_USER_DATA_HS_9"}, .Value: 0x2d15},
721 {.Names: {"SPI_SHADER_USER_DATA_HS_10"}, .Value: 0x2d16},
722 {.Names: {"SPI_SHADER_USER_DATA_HS_11"}, .Value: 0x2d17},
723 {.Names: {"SPI_SHADER_USER_DATA_HS_12"}, .Value: 0x2d18},
724 {.Names: {"SPI_SHADER_USER_DATA_HS_13"}, .Value: 0x2d19},
725 {.Names: {"SPI_SHADER_USER_DATA_HS_14"}, .Value: 0x2d1a},
726 {.Names: {"SPI_SHADER_USER_DATA_HS_15"}, .Value: 0x2d1b},
727 {.Names: {"SPI_SHADER_USER_DATA_HS_16"}, .Value: 0x2d1c},
728 {.Names: {"SPI_SHADER_USER_DATA_HS_17"}, .Value: 0x2d1d},
729 {.Names: {"SPI_SHADER_USER_DATA_HS_18"}, .Value: 0x2d1e},
730 {.Names: {"SPI_SHADER_USER_DATA_HS_19"}, .Value: 0x2d1f},
731 {.Names: {"SPI_SHADER_USER_DATA_HS_20"}, .Value: 0x2d20},
732 {.Names: {"SPI_SHADER_USER_DATA_HS_21"}, .Value: 0x2d21},
733 {.Names: {"SPI_SHADER_USER_DATA_HS_22"}, .Value: 0x2d22},
734 {.Names: {"SPI_SHADER_USER_DATA_HS_23"}, .Value: 0x2d23},
735 {.Names: {"SPI_SHADER_USER_DATA_HS_24"}, .Value: 0x2d24},
736 {.Names: {"SPI_SHADER_USER_DATA_HS_25"}, .Value: 0x2d25},
737 {.Names: {"SPI_SHADER_USER_DATA_HS_26"}, .Value: 0x2d26},
738 {.Names: {"SPI_SHADER_USER_DATA_HS_27"}, .Value: 0x2d27},
739 {.Names: {"SPI_SHADER_USER_DATA_HS_28"}, .Value: 0x2d28},
740 {.Names: {"SPI_SHADER_USER_DATA_HS_29"}, .Value: 0x2d29},
741 {.Names: {"SPI_SHADER_USER_DATA_HS_30"}, .Value: 0x2d2a},
742 {.Names: {"SPI_SHADER_USER_DATA_HS_31"}, .Value: 0x2d2b},
743
744 {.Names: {"SPI_SHADER_USER_DATA_LS_0"}, .Value: 0x2d4c},
745 {.Names: {"SPI_SHADER_USER_DATA_LS_1"}, .Value: 0x2d4d},
746 {.Names: {"SPI_SHADER_USER_DATA_LS_2"}, .Value: 0x2d4e},
747 {.Names: {"SPI_SHADER_USER_DATA_LS_3"}, .Value: 0x2d4f},
748 {.Names: {"SPI_SHADER_USER_DATA_LS_4"}, .Value: 0x2d50},
749 {.Names: {"SPI_SHADER_USER_DATA_LS_5"}, .Value: 0x2d51},
750 {.Names: {"SPI_SHADER_USER_DATA_LS_6"}, .Value: 0x2d52},
751 {.Names: {"SPI_SHADER_USER_DATA_LS_7"}, .Value: 0x2d53},
752 {.Names: {"SPI_SHADER_USER_DATA_LS_8"}, .Value: 0x2d54},
753 {.Names: {"SPI_SHADER_USER_DATA_LS_9"}, .Value: 0x2d55},
754 {.Names: {"SPI_SHADER_USER_DATA_LS_10"}, .Value: 0x2d56},
755 {.Names: {"SPI_SHADER_USER_DATA_LS_11"}, .Value: 0x2d57},
756 {.Names: {"SPI_SHADER_USER_DATA_LS_12"}, .Value: 0x2d58},
757 {.Names: {"SPI_SHADER_USER_DATA_LS_13"}, .Value: 0x2d59},
758 {.Names: {"SPI_SHADER_USER_DATA_LS_14"}, .Value: 0x2d5a},
759 {.Names: {"SPI_SHADER_USER_DATA_LS_15"}, .Value: 0x2d5b},
760
761 {.Names: {"IA_MULTI_VGT_PARAM"}, .Value: 0xa2aa},
762 {.Names: {"VGT_GS_MAX_PRIMS_PER_SUBGROUP"}, .Value: 0xa2a5},
763 {.Names: {"VGT_STRMOUT_BUFFER_CONFIG"}, .Value: 0xa2e6},
764 {.Names: {"VGT_STRMOUT_CONFIG"}, .Value: 0xa2e5},
765 {.Names: {"VGT_STRMOUT_VTX_STRIDE_0"}, .Value: 0xa2b5},
766 {.Names: {"VGT_STRMOUT_VTX_STRIDE_1"}, .Value: 0xa2b9},
767 {.Names: {"VGT_STRMOUT_VTX_STRIDE_2"}, .Value: 0xa2bd},
768 {.Names: {"VGT_STRMOUT_VTX_STRIDE_3"}, .Value: 0xa2c1},
769 {.Names: {"VGT_VERTEX_REUSE_BLOCK_CNTL"}, .Value: 0xa316},
770
771 {.Names: {"COMPUTE_PGM_RSRC3"}, .Value: 0x2e28},
772 {.Names: {"COMPUTE_SHADER_CHKSUM"}, .Value: 0x2e2a},
773 {.Names: {"COMPUTE_USER_ACCUM_0"}, .Value: 0x2e24},
774 {.Names: {"COMPUTE_USER_ACCUM_1"}, .Value: 0x2e25},
775 {.Names: {"COMPUTE_USER_ACCUM_2"}, .Value: 0x2e26},
776 {.Names: {"COMPUTE_USER_ACCUM_3"}, .Value: 0x2e27},
777 {.Names: {"GE_MAX_OUTPUT_PER_SUBGROUP"}, .Value: 0xa1ff},
778 {.Names: {"GE_NGG_SUBGRP_CNTL"}, .Value: 0xa2d3},
779 {.Names: {"GE_STEREO_CNTL"}, .Value: 0xc25f},
780 {.Names: {"GE_USER_VGPR_EN"}, .Value: 0xc262},
781 {.Names: {"IA_MULTI_VGT_PARAM_PIPED"}, .Value: 0xc258},
782 {.Names: {"PA_STEREO_CNTL"}, .Value: 0xa210},
783 {.Names: {"SPI_SHADER_IDX_FORMAT"}, .Value: 0xa1c2},
784 {.Names: {"SPI_SHADER_PGM_CHKSUM_GS"}, .Value: 0x2c80},
785 {.Names: {"SPI_SHADER_PGM_CHKSUM_HS"}, .Value: 0x2d00},
786 {.Names: {"SPI_SHADER_PGM_CHKSUM_PS"}, .Value: 0x2c06},
787 {.Names: {"SPI_SHADER_PGM_CHKSUM_VS"}, .Value: 0x2c45},
788 {.Names: {"SPI_SHADER_PGM_LO_GS"}, .Value: 0x2c88},
789 {.Names: {"SPI_SHADER_USER_ACCUM_ESGS_0"}, .Value: 0x2cb2},
790 {.Names: {"SPI_SHADER_USER_ACCUM_ESGS_1"}, .Value: 0x2cb3},
791 {.Names: {"SPI_SHADER_USER_ACCUM_ESGS_2"}, .Value: 0x2cb4},
792 {.Names: {"SPI_SHADER_USER_ACCUM_ESGS_3"}, .Value: 0x2cb5},
793 {.Names: {"SPI_SHADER_USER_ACCUM_LSHS_0"}, .Value: 0x2d32},
794 {.Names: {"SPI_SHADER_USER_ACCUM_LSHS_1"}, .Value: 0x2d33},
795 {.Names: {"SPI_SHADER_USER_ACCUM_LSHS_2"}, .Value: 0x2d34},
796 {.Names: {"SPI_SHADER_USER_ACCUM_LSHS_3"}, .Value: 0x2d35},
797 {.Names: {"SPI_SHADER_USER_ACCUM_PS_0"}, .Value: 0x2c32},
798 {.Names: {"SPI_SHADER_USER_ACCUM_PS_1"}, .Value: 0x2c33},
799 {.Names: {"SPI_SHADER_USER_ACCUM_PS_2"}, .Value: 0x2c34},
800 {.Names: {"SPI_SHADER_USER_ACCUM_PS_3"}, .Value: 0x2c35},
801 {.Names: {"SPI_SHADER_USER_ACCUM_VS_0"}, .Value: 0x2c72},
802 {.Names: {"SPI_SHADER_USER_ACCUM_VS_1"}, .Value: 0x2c73},
803 {.Names: {"SPI_SHADER_USER_ACCUM_VS_2"}, .Value: 0x2c74},
804 {.Names: {"SPI_SHADER_USER_ACCUM_VS_3"}, .Value: 0x2c75},
805 };
806 static constexpr auto RegInfoTable = BUILD_ENUM_STRINGS(RegInfoTableDefs);
807 return EnumStrings(RegInfoTable).toString(Value: RegNum);
808}
809
810// Convert the accumulated PAL metadata into an asm directive.
811void AMDGPUPALMetadata::toString(std::string &String) {
812 String.clear();
813 if (!BlobType)
814 return;
815 ResolvedAll = DelayedExprs.resolveDelayedExpressions();
816 raw_string_ostream Stream(String);
817 if (isLegacy()) {
818 if (MsgPackDoc.getRoot().getKind() == msgpack::Type::Nil)
819 return;
820 // Old linear reg=val format.
821 Stream << '\t' << AMDGPU::PALMD::AssemblerDirective << ' ';
822 auto Regs = getRegisters();
823 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
824 if (I != Regs.begin())
825 Stream << ',';
826 unsigned Reg = I->first.getUInt();
827 unsigned Val = I->second.getUInt();
828 Stream << "0x" << Twine::utohexstr(Val: Reg) << ",0x" << Twine::utohexstr(Val);
829 }
830 Stream << '\n';
831 return;
832 }
833
834 // New msgpack-based format -- output as YAML (with unsigned numbers in hex),
835 // but first change the registers map to use names.
836 MsgPackDoc.setHexMode();
837 auto &RegsObj = refRegisters();
838 auto OrigRegs = RegsObj.getMap();
839 RegsObj = MsgPackDoc.getMapNode();
840 for (auto I : OrigRegs) {
841 auto Key = I.first;
842 if (StringRef RegName = getRegisterName(RegNum: Key.getUInt()); !RegName.empty()) {
843 std::string KeyName = Key.toString();
844 KeyName += " (";
845 KeyName += RegName;
846 KeyName += ')';
847 Key = MsgPackDoc.getNode(V: KeyName, /*Copy=*/true);
848 }
849 RegsObj.getMap()[Key] = I.second;
850 }
851
852 // Output as YAML.
853 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveBegin << '\n';
854 MsgPackDoc.toYAML(OS&: Stream);
855 Stream << '\t' << AMDGPU::PALMD::AssemblerDirectiveEnd << '\n';
856
857 // Restore original registers map.
858 RegsObj = OrigRegs;
859}
860
861// Convert the accumulated PAL metadata into a binary blob for writing as
862// a .note record of the specified AMD type. Returns an empty blob if
863// there is no PAL metadata,
864void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) {
865 ResolvedAll = DelayedExprs.resolveDelayedExpressions();
866 if (Type == ELF::NT_AMD_PAL_METADATA)
867 toLegacyBlob(Blob);
868 else if (Type)
869 toMsgPackBlob(Blob);
870}
871
872void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) {
873 Blob.clear();
874 auto Registers = getRegisters();
875 if (Registers.getMap().empty())
876 return;
877 raw_string_ostream OS(Blob);
878 support::endian::Writer EW(OS, llvm::endianness::little);
879 for (auto I : Registers.getMap()) {
880 EW.write(Val: uint32_t(I.first.getUInt()));
881 EW.write(Val: uint32_t(I.second.getUInt()));
882 }
883}
884
885void AMDGPUPALMetadata::toMsgPackBlob(std::string &Blob) {
886 Blob.clear();
887 MsgPackDoc.writeToBlob(Blob);
888}
889
890// Set PAL metadata from YAML text. Returns false if failed.
891bool AMDGPUPALMetadata::setFromString(StringRef S) {
892 BlobType = ELF::NT_AMDGPU_METADATA;
893 if (!MsgPackDoc.fromYAML(S))
894 return false;
895
896 // In the registers map, some keys may be of the form "0xa191
897 // (SPI_PS_INPUT_CNTL_0)", in which case the YAML input code made it a
898 // string. We need to turn it into a number.
899 auto &RegsObj = refRegisters();
900 auto OrigRegs = RegsObj;
901 RegsObj = MsgPackDoc.getMapNode();
902 Registers = RegsObj.getMap();
903 bool Ok = true;
904 for (auto I : OrigRegs.getMap()) {
905 auto Key = I.first;
906 if (Key.getKind() == msgpack::Type::String) {
907 StringRef S = Key.getString();
908 uint64_t Val;
909 if (S.consumeInteger(Radix: 0, Result&: Val)) {
910 Ok = false;
911 errs() << "Unrecognized PAL metadata register key '" << S << "'\n";
912 continue;
913 }
914 Key = MsgPackDoc.getNode(V: Val);
915 }
916 Registers.getMap()[Key] = I.second;
917 }
918 return Ok;
919}
920
921// Reference (create if necessary) the node for the registers map.
922msgpack::DocNode &AMDGPUPALMetadata::refRegisters() {
923 auto &N =
924 MsgPackDoc.getRoot()
925 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines")]
926 .getArray(/*Convert=*/true)[0]
927 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".registers")];
928 N.getMap(/*Convert=*/true);
929 return N;
930}
931
932// Get (create if necessary) the registers map.
933msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() {
934 if (Registers.isEmpty())
935 Registers = refRegisters();
936 return Registers.getMap();
937}
938
939// Reference (create if necessary) the node for the shader functions map.
940msgpack::DocNode &AMDGPUPALMetadata::refShaderFunctions() {
941 auto &N =
942 MsgPackDoc.getRoot()
943 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines")]
944 .getArray(/*Convert=*/true)[0]
945 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".shader_functions")];
946 N.getMap(/*Convert=*/true);
947 return N;
948}
949
950// Get (create if necessary) the shader functions map.
951msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunctions() {
952 if (ShaderFunctions.isEmpty())
953 ShaderFunctions = refShaderFunctions();
954 return ShaderFunctions.getMap();
955}
956
957// Get (create if necessary) a function in the shader functions map.
958msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunction(StringRef Name) {
959 auto Functions = getShaderFunctions();
960 return Functions[Name].getMap(/*Convert=*/true);
961}
962
963msgpack::DocNode &AMDGPUPALMetadata::refComputeRegisters() {
964 auto &N =
965 MsgPackDoc.getRoot()
966 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines")]
967 .getArray(/*Convert=*/true)[0]
968 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".compute_registers")];
969 N.getMap(/*Convert=*/true);
970 return N;
971}
972
973msgpack::MapDocNode AMDGPUPALMetadata::getComputeRegisters() {
974 if (ComputeRegisters.isEmpty())
975 ComputeRegisters = refComputeRegisters();
976 return ComputeRegisters.getMap();
977}
978
979msgpack::DocNode &AMDGPUPALMetadata::refGraphicsRegisters() {
980 auto &N =
981 MsgPackDoc.getRoot()
982 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines")]
983 .getArray(/*Convert=*/true)[0]
984 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".graphics_registers")];
985 N.getMap(/*Convert=*/true);
986 return N;
987}
988
989msgpack::MapDocNode AMDGPUPALMetadata::getGraphicsRegisters() {
990 if (GraphicsRegisters.isEmpty())
991 GraphicsRegisters = refGraphicsRegisters();
992 return GraphicsRegisters.getMap();
993}
994
995msgpack::DocNode &AMDGPUPALMetadata::refHwStage() {
996 auto &N =
997 MsgPackDoc.getRoot()
998 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: "amdpal.pipelines")]
999 .getArray(/*Convert=*/true)[0]
1000 .getMap(/*Convert=*/true)[MsgPackDoc.getNode(V: ".hardware_stages")];
1001 N.getMap(/*Convert=*/true);
1002 return N;
1003}
1004
1005// Get (create if necessary) the .hardware_stages entry for the given calling
1006// convention.
1007msgpack::MapDocNode AMDGPUPALMetadata::getHwStage(unsigned CC) {
1008 if (HwStages.isEmpty())
1009 HwStages = refHwStage();
1010 return HwStages.getMap()[getStageName(CC)].getMap(/*Convert=*/true);
1011}
1012
1013// Get .note record vendor name of metadata blob to be emitted.
1014const char *AMDGPUPALMetadata::getVendor() const {
1015 return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3;
1016}
1017
1018// Get .note record type of metadata blob to be emitted:
1019// ELF::NT_AMD_PAL_METADATA (legacy key=val format), or
1020// ELF::NT_AMDGPU_METADATA (MsgPack format), or
1021// 0 (no PAL metadata).
1022unsigned AMDGPUPALMetadata::getType() const {
1023 return BlobType;
1024}
1025
1026// Return whether the blob type is legacy PAL metadata.
1027bool AMDGPUPALMetadata::isLegacy() const {
1028 return BlobType == ELF::NT_AMD_PAL_METADATA;
1029}
1030
1031// Set legacy PAL metadata format.
1032void AMDGPUPALMetadata::setLegacy() {
1033 BlobType = ELF::NT_AMD_PAL_METADATA;
1034}
1035
1036// Erase all PAL metadata.
1037void AMDGPUPALMetadata::reset() {
1038 MsgPackDoc.clear();
1039 REM.clear();
1040 DelayedExprs.clear();
1041 Registers = MsgPackDoc.getEmptyNode();
1042 HwStages = MsgPackDoc.getEmptyNode();
1043 ShaderFunctions = MsgPackDoc.getEmptyNode();
1044}
1045
1046bool AMDGPUPALMetadata::resolvedAllMCExpr() {
1047 return ResolvedAll && DelayedExprs.empty();
1048}
1049
1050unsigned AMDGPUPALMetadata::getPALVersion(unsigned idx) {
1051 assert(idx < 2 &&
1052 "illegal index to PAL version - should be 0 (major) or 1 (minor)");
1053 if (!VersionChecked) {
1054 if (Version.isEmpty()) {
1055 auto &M = MsgPackDoc.getRoot().getMap(/*Convert=*/true);
1056 auto I = M.find(Key: MsgPackDoc.getNode(V: "amdpal.version"));
1057 if (I != M.end())
1058 Version = I->second;
1059 }
1060 VersionChecked = true;
1061 }
1062 if (Version.isEmpty())
1063 // Default to 2.6 if there's no version info
1064 return idx ? 6 : 2;
1065 return Version.getArray()[idx].getUInt();
1066}
1067
1068unsigned AMDGPUPALMetadata::getPALMajorVersion() { return getPALVersion(idx: 0); }
1069
1070unsigned AMDGPUPALMetadata::getPALMinorVersion() { return getPALVersion(idx: 1); }
1071
1072VersionTuple AMDGPUPALMetadata::getPALVersion() {
1073 return VersionTuple(getPALVersion(idx: 0), getPALVersion(idx: 1));
1074}
1075
1076// Set the field in a given .hardware_stages entry to a maximum value
1077void AMDGPUPALMetadata::updateHwStageMaximum(unsigned CC, StringRef field,
1078 unsigned Val) {
1079 msgpack::MapDocNode HwStageFieldMapNode = getHwStage(CC);
1080 auto &Node = HwStageFieldMapNode[field];
1081 if (Node.isEmpty())
1082 Node = Val;
1083 else
1084 Node = std::max<unsigned>(a: Node.getUInt(), b: Val);
1085}
1086
1087// Set the field in a given .hardware_stages entry
1088void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, unsigned Val) {
1089 getHwStage(CC)[field] = Val;
1090}
1091
1092void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field, bool Val) {
1093 getHwStage(CC)[field] = Val;
1094}
1095
1096void AMDGPUPALMetadata::setHwStage(unsigned CC, StringRef field,
1097 msgpack::Type Type, const MCExpr *Val) {
1098 DelayedExprs.assignDocNode(DN&: getHwStage(CC)[field], Type, ExprValue: Val);
1099}
1100
1101void AMDGPUPALMetadata::setComputeRegisters(StringRef field, unsigned Val) {
1102 getComputeRegisters()[field] = Val;
1103}
1104
1105void AMDGPUPALMetadata::setComputeRegisters(StringRef field, bool Val) {
1106 getComputeRegisters()[field] = Val;
1107}
1108
1109msgpack::DocNode *AMDGPUPALMetadata::refComputeRegister(StringRef field) {
1110 auto M = getComputeRegisters();
1111 auto I = M.find(Key: field);
1112 return I == M.end() ? nullptr : &I->second;
1113}
1114
1115bool AMDGPUPALMetadata::checkComputeRegisters(StringRef field, unsigned Val) {
1116 if (auto *N = refComputeRegister(field))
1117 return N->getUInt() == Val;
1118 return false;
1119}
1120
1121bool AMDGPUPALMetadata::checkComputeRegisters(StringRef field, bool Val) {
1122 if (auto *N = refComputeRegister(field))
1123 return N->getBool() == Val;
1124 return false;
1125}
1126
1127void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field, unsigned Val) {
1128 getGraphicsRegisters()[field] = Val;
1129}
1130
1131void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field, bool Val) {
1132 getGraphicsRegisters()[field] = Val;
1133}
1134
1135void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field1, StringRef field2,
1136 unsigned Val) {
1137 getGraphicsRegisters()[field1].getMap(Convert: true)[field2] = Val;
1138}
1139
1140void AMDGPUPALMetadata::setGraphicsRegisters(StringRef field1, StringRef field2,
1141 bool Val) {
1142 getGraphicsRegisters()[field1].getMap(Convert: true)[field2] = Val;
1143}
1144