1//=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
10#define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
11
12#include "llvm/CodeGen/MIRYamlMapping.h"
13#include "llvm/CodeGen/MachineFunction.h"
14#include <map>
15
16namespace llvm {
17
18namespace yaml {
19struct HexagonFunctionInfo;
20} // end namespace yaml
21
22namespace Hexagon {
23
24 const unsigned int StartPacket = 0x1;
25 const unsigned int EndPacket = 0x2;
26
27} // end namespace Hexagon
28
29/// Hexagon target-specific information for each MachineFunction.
30class HexagonMachineFunctionInfo : public MachineFunctionInfo {
31 // SRetReturnReg - Some subtargets require that sret lowering includes
32 // returning the value of the returned struct in a register. This field
33 // holds the virtual register into which the sret argument is passed.
34 unsigned SRetReturnReg = 0;
35 Register StackAlignBaseReg = 0; // Aligned-stack base register
36 int VarArgsFrameIndex;
37 int RegSavedAreaStartFrameIndex;
38 int FirstNamedArgFrameIndex;
39 int LastNamedArgFrameIndex;
40 bool HasClobberLR = false;
41 bool HasEHReturn = false;
42 std::map<const MachineInstr*, unsigned> PacketInfo;
43 virtual void anchor();
44
45public:
46 HexagonMachineFunctionInfo() = default;
47
48 HexagonMachineFunctionInfo(const Function &F,
49 const TargetSubtargetInfo *STI) {}
50
51 MachineFunctionInfo *
52 clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
53 const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
54 const override;
55
56 void initializeBaseYamlFields(const yaml::HexagonFunctionInfo &YamlMFI);
57
58 unsigned getSRetReturnReg() const { return SRetReturnReg; }
59 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
60
61 void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; }
62 int getVarArgsFrameIndex() { return VarArgsFrameIndex; }
63
64 void setRegSavedAreaStartFrameIndex(int v) { RegSavedAreaStartFrameIndex = v;}
65 int getRegSavedAreaStartFrameIndex() { return RegSavedAreaStartFrameIndex; }
66
67 void setFirstNamedArgFrameIndex(int v) { FirstNamedArgFrameIndex = v; }
68 int getFirstNamedArgFrameIndex() { return FirstNamedArgFrameIndex; }
69
70 void setLastNamedArgFrameIndex(int v) { LastNamedArgFrameIndex = v; }
71 int getLastNamedArgFrameIndex() { return LastNamedArgFrameIndex; }
72
73 void setStartPacket(MachineInstr* MI) {
74 PacketInfo[MI] |= Hexagon::StartPacket;
75 }
76 void setEndPacket(MachineInstr* MI) {
77 PacketInfo[MI] |= Hexagon::EndPacket;
78 }
79 bool isStartPacket(const MachineInstr* MI) const {
80 auto It = PacketInfo.find(x: MI);
81 return It != PacketInfo.end() && (It->second & Hexagon::StartPacket);
82 }
83 bool isEndPacket(const MachineInstr* MI) const {
84 auto It = PacketInfo.find(x: MI);
85 return It != PacketInfo.end() && (It->second & Hexagon::EndPacket);
86 }
87 void setHasClobberLR(bool v) { HasClobberLR = v; }
88 bool hasClobberLR() const { return HasClobberLR; }
89
90 bool hasEHReturn() const { return HasEHReturn; };
91 void setHasEHReturn(bool H = true) { HasEHReturn = H; };
92
93 void setStackAlignBaseReg(Register R) { StackAlignBaseReg = R; }
94 Register getStackAlignBaseReg() const { return StackAlignBaseReg; }
95};
96
97namespace yaml {
98
99/// Hexagon-specific MachineFunction properties for YAML serialization.
100struct HexagonFunctionInfo final : public yaml::MachineFunctionInfo {
101 StringValue StackAlignBaseReg;
102
103 HexagonFunctionInfo() = default;
104 HexagonFunctionInfo(const llvm::HexagonMachineFunctionInfo &MFI,
105 const TargetRegisterInfo &TRI);
106
107 void mappingImpl(yaml::IO &YamlIO) override;
108 ~HexagonFunctionInfo() override = default;
109};
110
111template <> struct MappingTraits<HexagonFunctionInfo> {
112 static void mapping(IO &YamlIO, HexagonFunctionInfo &MFI) {
113 YamlIO.mapOptional(Key: "stackAlignBaseReg", Val&: MFI.StackAlignBaseReg);
114 }
115};
116
117} // end namespace yaml
118
119} // end namespace llvm
120
121#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H
122