1//==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Hexagon implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
15#define LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
16
17#include "llvm/CodeGen/TargetRegisterInfo.h"
18
19#define GET_REGINFO_HEADER
20#include "HexagonGenRegisterInfo.inc"
21
22namespace llvm {
23
24namespace Hexagon {
25 // Generic (pseudo) subreg indices for use with getHexagonSubRegIndex.
26 enum { ps_sub_lo = 0, ps_sub_hi = 1 };
27}
28
29class HexagonRegisterInfo : public HexagonGenRegisterInfo {
30public:
31 HexagonRegisterInfo(unsigned HwMode);
32
33 /// Code Generation virtual methods...
34 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
35 const override;
36 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
37 CallingConv::ID) const override;
38
39 BitVector getReservedRegs(const MachineFunction &MF) const override;
40
41 /// Compute the first available callee-saved register to use as the
42 /// aligned-stack base register when this function needs dynamic stack
43 /// realignment. This does not update the machine function info.
44 Register computeStackAlignBaseRegister(const MachineFunction &MF) const;
45
46 bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
47 unsigned FIOperandNum, RegScavenger *RS = nullptr) const override;
48
49 /// Returns true since we may need scavenging for a temporary register
50 /// when generating hardware loop instructions.
51 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
52 return true;
53 }
54
55 /// Returns true. Spill code for predicate registers might need an extra
56 /// register.
57 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
58 return true;
59 }
60
61 /// Returns true if the frame pointer is valid.
62 bool useFPForScavengingIndex(const MachineFunction &MF) const override;
63
64 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
65 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
66 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
67
68 // Debug information queries.
69 Register getFrameRegister(const MachineFunction &MF) const override;
70 Register getFrameRegister() const;
71 Register getStackRegister() const;
72
73 unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
74 unsigned GenIdx) const;
75
76 const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF,
77 const TargetRegisterClass *RC) const;
78
79 const TargetRegisterClass *
80 getPointerRegClass(unsigned Kind = 0) const override;
81
82 /// Returns true if the given reserved physical register is live across
83 /// function calls/returns.
84 bool isGlobalReg(MCPhysReg Reg) const;
85
86 /// Returns true if the given reserved physical register Reg is live
87 /// across function calls/returns. This function should not be used for
88 /// non-reserved registers, instead register liveness information should be
89 /// checked
90 bool isFakeReg(MCPhysReg Reg) const;
91
92 bool isEHReturnCalleeSaveReg(Register Reg) const;
93
94private:
95 BitVector getBaseReservedRegs(const MachineFunction &MF) const;
96 Register
97 computeStackAlignBaseRegister(const MachineFunction &MF,
98 const BitVector &BaseReservedRegs) const;
99};
100
101} // end namespace llvm
102
103#endif
104