1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Information Header Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#include "llvm/CodeGen/TargetRegisterInfo.h"
10
11namespace llvm {
12
13class HexagonFrameLowering;
14
15extern const MCRegisterClassStorage<29, 428, 311, 54, 13, 19> HexagonMCRegisterClassStorage;
16
17struct HexagonGenRegisterInfo : public TargetRegisterInfo {
18 explicit HexagonGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
19 unsigned PC = 0, unsigned HwMode = 0);
20 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
21 unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
22 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
23 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
24 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
25 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
26 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
27 unsigned getRegUnitWeight(MCRegUnit RegUnit) const override;
28 unsigned getNumRegPressureSets() const override;
29 const char *getRegPressureSetName(unsigned Idx) const override;
30 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
31 const TargetRegisterClass *getLargestRegClassForRegPressureSet(unsigned Idx) const override;
32 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
33 const int *getRegUnitPressureSets(MCRegUnit RegUnit) const override;
34 ArrayRef<const char *> getRegMaskNames() const override;
35 ArrayRef<const uint32_t *> getRegMasks() const override;
36 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
37 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
38 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
39 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
40 bool isConstantPhysReg(MCRegister PhysReg) const override final;
41 /// Devirtualized TargetFrameLowering.
42 static const HexagonFrameLowering *getFrameLowering(
43 const MachineFunction &MF);
44 const TargetRegisterClass *getMinimalPhysRegClass(MCRegister Reg) const override;
45};
46
47namespace Hexagon {
48
49// Register classes
50static constexpr const TargetRegisterClass &UsrBitsRegClass = HexagonMCRegisterClassStorage.Classes[0];
51static constexpr const TargetRegisterClass &SysRegsRegClass = HexagonMCRegisterClassStorage.Classes[1];
52static constexpr const TargetRegisterClass &GuestRegsRegClass = HexagonMCRegisterClassStorage.Classes[2];
53static constexpr const TargetRegisterClass &IntRegsRegClass = HexagonMCRegisterClassStorage.Classes[3];
54static constexpr const TargetRegisterClass &CtrRegsRegClass = HexagonMCRegisterClassStorage.Classes[4];
55static constexpr const TargetRegisterClass &GeneralSubRegsRegClass = HexagonMCRegisterClassStorage.Classes[5];
56static constexpr const TargetRegisterClass &V62RegsRegClass = HexagonMCRegisterClassStorage.Classes[6];
57static constexpr const TargetRegisterClass &IntRegsLow8RegClass = HexagonMCRegisterClassStorage.Classes[7];
58static constexpr const TargetRegisterClass &CtrRegs_and_V62RegsRegClass = HexagonMCRegisterClassStorage.Classes[8];
59static constexpr const TargetRegisterClass &PredRegsRegClass = HexagonMCRegisterClassStorage.Classes[9];
60static constexpr const TargetRegisterClass &V62Regs_with_isub_hiRegClass = HexagonMCRegisterClassStorage.Classes[10];
61static constexpr const TargetRegisterClass &ModRegsRegClass = HexagonMCRegisterClassStorage.Classes[11];
62static constexpr const TargetRegisterClass &CtrRegs_with_subreg_overflowRegClass = HexagonMCRegisterClassStorage.Classes[12];
63static constexpr const TargetRegisterClass &V65RegsRegClass = HexagonMCRegisterClassStorage.Classes[13];
64static constexpr const TargetRegisterClass &SysRegs64RegClass = HexagonMCRegisterClassStorage.Classes[14];
65static constexpr const TargetRegisterClass &DoubleRegsRegClass = HexagonMCRegisterClassStorage.Classes[15];
66static constexpr const TargetRegisterClass &GuestRegs64RegClass = HexagonMCRegisterClassStorage.Classes[16];
67static constexpr const TargetRegisterClass &VectRegRevRegClass = HexagonMCRegisterClassStorage.Classes[17];
68static constexpr const TargetRegisterClass &CtrRegs64RegClass = HexagonMCRegisterClassStorage.Classes[18];
69static constexpr const TargetRegisterClass &GeneralDoubleLow8RegsRegClass = HexagonMCRegisterClassStorage.Classes[19];
70static constexpr const TargetRegisterClass &DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass = HexagonMCRegisterClassStorage.Classes[20];
71static constexpr const TargetRegisterClass &CtrRegs64_and_V62RegsRegClass = HexagonMCRegisterClassStorage.Classes[21];
72static constexpr const TargetRegisterClass &CtrRegs64_with_isub_hi_in_ModRegsRegClass = HexagonMCRegisterClassStorage.Classes[22];
73static constexpr const TargetRegisterClass &HvxQRRegClass = HexagonMCRegisterClassStorage.Classes[23];
74static constexpr const TargetRegisterClass &HvxVRRegClass = HexagonMCRegisterClassStorage.Classes[24];
75static constexpr const TargetRegisterClass &HvxVR_and_V65RegsRegClass = HexagonMCRegisterClassStorage.Classes[25];
76static constexpr const TargetRegisterClass &HvxWRRegClass = HexagonMCRegisterClassStorage.Classes[26];
77static constexpr const TargetRegisterClass &HvxWR_with_wsub_loRegClass = HexagonMCRegisterClassStorage.Classes[27];
78static constexpr const TargetRegisterClass &HvxVQRRegClass = HexagonMCRegisterClassStorage.Classes[28];
79
80} // namespace Hexagon
81
82} // namespace llvm
83