1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Information Header Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#include "llvm/CodeGen/TargetRegisterInfo.h"
10
11namespace llvm {
12
13class HexagonFrameLowering;
14
15struct HexagonGenRegisterInfo : public TargetRegisterInfo {
16 explicit HexagonGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
17 unsigned PC = 0, unsigned HwMode = 0);
18 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
19 unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override;
20 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
21 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
22 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
23 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
24 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
25 unsigned getRegUnitWeight(MCRegUnit RegUnit) const override;
26 unsigned getNumRegPressureSets() const override;
27 const char *getRegPressureSetName(unsigned Idx) const override;
28 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
29 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
30 const int *getRegUnitPressureSets(MCRegUnit RegUnit) const override;
31 ArrayRef<const char *> getRegMaskNames() const override;
32 ArrayRef<const uint32_t *> getRegMasks() const override;
33 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
34 bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override;
35 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
36 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
37 bool isConstantPhysReg(MCRegister PhysReg) const override final;
38 /// Devirtualized TargetFrameLowering.
39 static const HexagonFrameLowering *getFrameLowering(
40 const MachineFunction &MF);
41};
42
43namespace Hexagon { // Register classes
44 extern const TargetRegisterClass UsrBitsRegClass;
45 extern const TargetRegisterClass SysRegsRegClass;
46 extern const TargetRegisterClass GuestRegsRegClass;
47 extern const TargetRegisterClass IntRegsRegClass;
48 extern const TargetRegisterClass CtrRegsRegClass;
49 extern const TargetRegisterClass GeneralSubRegsRegClass;
50 extern const TargetRegisterClass V62RegsRegClass;
51 extern const TargetRegisterClass IntRegsLow8RegClass;
52 extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass;
53 extern const TargetRegisterClass PredRegsRegClass;
54 extern const TargetRegisterClass V62Regs_with_isub_hiRegClass;
55 extern const TargetRegisterClass ModRegsRegClass;
56 extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass;
57 extern const TargetRegisterClass V65RegsRegClass;
58 extern const TargetRegisterClass SysRegs64RegClass;
59 extern const TargetRegisterClass DoubleRegsRegClass;
60 extern const TargetRegisterClass GuestRegs64RegClass;
61 extern const TargetRegisterClass VectRegRevRegClass;
62 extern const TargetRegisterClass CtrRegs64RegClass;
63 extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass;
64 extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass;
65 extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass;
66 extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass;
67 extern const TargetRegisterClass HvxQRRegClass;
68 extern const TargetRegisterClass HvxVRRegClass;
69 extern const TargetRegisterClass HvxVR_and_V65RegsRegClass;
70 extern const TargetRegisterClass HvxWRRegClass;
71 extern const TargetRegisterClass HvxWR_and_VectRegRevRegClass;
72 extern const TargetRegisterClass HvxVQRRegClass;
73} // end namespace Hexagon
74
75} // end namespace llvm
76
77