1//==- HexagonFrameLowering.h - Define frame lowering for Hexagon -*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
10#define LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
11
12#include "Hexagon.h"
13#include "HexagonBlockRanges.h"
14#include "MCTargetDesc/HexagonMCTargetDesc.h"
15#include "llvm/ADT/STLExtras.h"
16#include "llvm/CodeGen/MachineBasicBlock.h"
17#include "llvm/CodeGen/MachineFrameInfo.h"
18#include "llvm/CodeGen/TargetFrameLowering.h"
19#include <vector>
20
21namespace llvm {
22
23class BitVector;
24class HexagonInstrInfo;
25class HexagonRegisterInfo;
26class MachineFunction;
27class MachineInstr;
28class MachineRegisterInfo;
29class MCRegisterClass;
30using TargetRegisterClass = MCRegisterClass;
31
32class HexagonFrameLowering : public TargetFrameLowering {
33public:
34 // First register which could possibly hold a variable argument.
35 int FirstVarArgSavedReg;
36 explicit HexagonFrameLowering()
37 : TargetFrameLowering(StackGrowsDown, Align(8), 0, Align(1), true) {}
38
39 void
40 orderFrameObjects(const MachineFunction &MF,
41 SmallVectorImpl<int> &ObjectsToAllocate) const override;
42
43 // All of the prolog/epilog functionality, including saving and restoring
44 // callee-saved registers is handled in emitPrologue. This is to have the
45 // logic for shrink-wrapping in one place.
46 void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const
47 override;
48 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
49 override {}
50
51 bool enableCalleeSaveSkip(const MachineFunction &MF) const override;
52
53 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator MI,
55 ArrayRef<CalleeSavedInfo> CSI,
56 const TargetRegisterInfo *TRI) const override {
57 return true;
58 }
59
60 bool
61 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator MI,
63 MutableArrayRef<CalleeSavedInfo> CSI,
64 const TargetRegisterInfo *TRI) const override {
65 return true;
66 }
67
68 bool hasReservedCallFrame(const MachineFunction &MF) const override {
69 // We always reserve call frame as a part of the initial stack allocation.
70 return true;
71 }
72
73 bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override {
74 // Override this function to avoid calling hasFP before CSI is set
75 // (the default implementation calls hasFP).
76 return true;
77 }
78
79 MachineBasicBlock::iterator
80 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator I) const override;
82 void processFunctionBeforeFrameFinalized(MachineFunction &MF,
83 RegScavenger *RS = nullptr) const override;
84 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
85 RegScavenger *RS) const override;
86
87 bool targetHandlesStackFrameRounding() const override {
88 return true;
89 }
90
91 StackOffset getFrameIndexReference(const MachineFunction &MF, int FI,
92 Register &FrameReg) const override;
93
94 const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries)
95 const override {
96 static const SpillSlot Offsets[] = {
97 { .Reg: Hexagon::R17, .Offset: -4 }, { .Reg: Hexagon::R16, .Offset: -8 }, { .Reg: Hexagon::D8, .Offset: -8 },
98 { .Reg: Hexagon::R19, .Offset: -12 }, { .Reg: Hexagon::R18, .Offset: -16 }, { .Reg: Hexagon::D9, .Offset: -16 },
99 { .Reg: Hexagon::R21, .Offset: -20 }, { .Reg: Hexagon::R20, .Offset: -24 }, { .Reg: Hexagon::D10, .Offset: -24 },
100 { .Reg: Hexagon::R23, .Offset: -28 }, { .Reg: Hexagon::R22, .Offset: -32 }, { .Reg: Hexagon::D11, .Offset: -32 },
101 { .Reg: Hexagon::R25, .Offset: -36 }, { .Reg: Hexagon::R24, .Offset: -40 }, { .Reg: Hexagon::D12, .Offset: -40 },
102 { .Reg: Hexagon::R27, .Offset: -44 }, { .Reg: Hexagon::R26, .Offset: -48 }, { .Reg: Hexagon::D13, .Offset: -48 }
103 };
104 NumEntries = std::size(Offsets);
105 return Offsets;
106 }
107
108 bool assignCalleeSavedSpillSlots(MachineFunction &MF,
109 const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI)
110 const override;
111
112 bool needsAligna(const MachineFunction &MF) const;
113 const MachineInstr *getAlignaInstr(const MachineFunction &MF) const;
114
115 void insertCFIInstructions(MachineFunction &MF) const;
116
117 void inlineStackProbe(MachineFunction &MF,
118 MachineBasicBlock &PrologueMBB) const override;
119
120protected:
121 bool hasFPImpl(const MachineFunction &MF) const override;
122
123private:
124 using CSIVect = std::vector<CalleeSavedInfo>;
125
126 void expandAlloca(MachineInstr *AI, MachineFunction &MF,
127 const HexagonInstrInfo &TII, Register SP,
128 unsigned CF) const;
129 void insertPrologueInBlock(MachineBasicBlock &MBB, bool PrologueStubs) const;
130 void insertEpilogueInBlock(MachineBasicBlock &MBB) const;
131 void insertAllocframe(MachineBasicBlock &MBB,
132 MachineBasicBlock::iterator InsertPt, unsigned NumBytes) const;
133 bool insertCSRSpillsInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
134 const HexagonRegisterInfo &HRI, bool &PrologueStubs) const;
135 bool insertCSRRestoresInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
136 const HexagonRegisterInfo &HRI) const;
137 void updateEntryPaths(MachineFunction &MF, MachineBasicBlock &SaveB) const;
138 bool updateExitPaths(MachineBasicBlock &MBB, MachineBasicBlock &RestoreB,
139 BitVector &DoneT, BitVector &DoneF, BitVector &Path) const;
140 void insertCFIInstructionsAt(MachineBasicBlock &MBB,
141 MachineBasicBlock::iterator At) const;
142
143 bool expandCopy(MachineBasicBlock &B, MachineBasicBlock::iterator It,
144 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
145 SmallVectorImpl<Register> &NewRegs) const;
146 bool expandStoreInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
147 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
148 SmallVectorImpl<Register> &NewRegs) const;
149 bool expandLoadInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
150 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
151 SmallVectorImpl<Register> &NewRegs) const;
152 bool expandStoreVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
153 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
154 SmallVectorImpl<Register> &NewRegs) const;
155 bool expandLoadVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
156 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
157 SmallVectorImpl<Register> &NewRegs) const;
158 bool expandStoreVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
159 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
160 SmallVectorImpl<Register> &NewRegs) const;
161 bool expandLoadVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
162 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
163 SmallVectorImpl<Register> &NewRegs) const;
164 bool expandStoreVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
165 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
166 SmallVectorImpl<Register> &NewRegs) const;
167 bool expandLoadVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
168 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
169 SmallVectorImpl<Register> &NewRegs) const;
170 bool expandSpillMacros(MachineFunction &MF,
171 SmallVectorImpl<Register> &NewRegs) const;
172
173 Register findPhysReg(MachineFunction &MF, HexagonBlockRanges::IndexRange &FIR,
174 HexagonBlockRanges::InstrIndexMap &IndexMap,
175 HexagonBlockRanges::RegToRangeMap &DeadMap,
176 const TargetRegisterClass *RC) const;
177 void optimizeSpillSlots(MachineFunction &MF,
178 SmallVectorImpl<Register> &VRegs) const;
179
180 void findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB,
181 MachineBasicBlock *&EpilogB) const;
182
183 void addCalleeSaveRegistersAsImpOperand(MachineInstr *MI, const CSIVect &CSI,
184 bool IsDef, bool IsKill) const;
185 bool shouldInlineCSR(const MachineFunction &MF, const CSIVect &CSI) const;
186 bool useSpillFunction(const MachineFunction &MF, const CSIVect &CSI) const;
187 bool useRestoreFunction(const MachineFunction &MF, const CSIVect &CSI) const;
188 bool mayOverflowFrameOffset(MachineFunction &MF) const;
189};
190
191} // end namespace llvm
192
193#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
194