1//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Hexagon implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
14#define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
15
16#include "MCTargetDesc/HexagonBaseInfo.h"
17#include "llvm/ADT/ArrayRef.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/CodeGen/MachineBasicBlock.h"
20#include "llvm/CodeGen/TargetInstrInfo.h"
21#include "llvm/CodeGen/ValueTypes.h"
22#include "llvm/CodeGenTypes/MachineValueType.h"
23#include <cstdint>
24#include <vector>
25
26#include "HexagonRegisterInfo.h"
27
28#define GET_INSTRINFO_HEADER
29#include "HexagonGenInstrInfo.inc"
30
31namespace llvm {
32
33class HexagonSubtarget;
34class MachineBranchProbabilityInfo;
35class MachineFunction;
36class MachineInstr;
37class MachineOperand;
38class TargetRegisterInfo;
39
40class HexagonInstrInfo : public HexagonGenInstrInfo {
41 const HexagonRegisterInfo RegInfo;
42 const HexagonSubtarget &Subtarget;
43
44 enum BundleAttribute {
45 memShufDisabledMask = 0x4
46 };
47
48 virtual void anchor();
49
50public:
51 explicit HexagonInstrInfo(const HexagonSubtarget &ST);
52
53 const HexagonRegisterInfo &getRegisterInfo() const { return RegInfo; }
54
55 bool isMIBefore(const MachineInstr *A, const MachineInstr *B) const;
56 bool hasQFPInstrs(const MachineFunction &MF) const;
57
58 /// TargetInstrInfo overrides.
59
60 /// If the specified machine instruction is a direct
61 /// load from a stack slot, return the virtual or physical register number of
62 /// the destination along with the FrameIndex of the loaded stack slot. If
63 /// not, return 0. This predicate must return 0 if the instruction has
64 /// any side effects other than loading from the stack slot.
65 Register isLoadFromStackSlot(const MachineInstr &MI,
66 int &FrameIndex) const override;
67
68 /// If the specified machine instruction is a direct
69 /// store to a stack slot, return the virtual or physical register number of
70 /// the source reg along with the FrameIndex of the loaded stack slot. If
71 /// not, return 0. This predicate must return 0 if the instruction has
72 /// any side effects other than storing to the stack slot.
73 Register isStoreToStackSlot(const MachineInstr &MI,
74 int &FrameIndex) const override;
75
76 /// Check if the instruction or the bundle of instructions has
77 /// load from stack slots. Return the frameindex and machine memory operand
78 /// if true.
79 bool hasLoadFromStackSlot(
80 const MachineInstr &MI,
81 SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
82
83 /// Check if the instruction or the bundle of instructions has
84 /// store to stack slots. Return the frameindex and machine memory operand
85 /// if true.
86 bool hasStoreToStackSlot(
87 const MachineInstr &MI,
88 SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
89
90 /// Analyze the branching code at the end of MBB, returning
91 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
92 /// implemented for a target). Upon success, this returns false and returns
93 /// with the following information in various cases:
94 ///
95 /// 1. If this block ends with no branches (it just falls through to its succ)
96 /// just return false, leaving TBB/FBB null.
97 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
98 /// the destination block.
99 /// 3. If this block ends with a conditional branch and it falls through to a
100 /// successor block, it sets TBB to be the branch destination block and a
101 /// list of operands that evaluate the condition. These operands can be
102 /// passed to other TargetInstrInfo methods to create new branches.
103 /// 4. If this block ends with a conditional branch followed by an
104 /// unconditional branch, it returns the 'true' destination in TBB, the
105 /// 'false' destination in FBB, and a list of operands that evaluate the
106 /// condition. These operands can be passed to other TargetInstrInfo
107 /// methods to create new branches.
108 ///
109 /// Note that removeBranch and insertBranch must be implemented to support
110 /// cases where this method returns success.
111 ///
112 /// If AllowModify is true, then this routine is allowed to modify the basic
113 /// block (e.g. delete instructions after the unconditional branch).
114 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
115 MachineBasicBlock *&FBB,
116 SmallVectorImpl<MachineOperand> &Cond,
117 bool AllowModify) const override;
118
119 /// Remove the branching code at the end of the specific MBB.
120 /// This is only invoked in cases where analyzeBranch returns success. It
121 /// returns the number of instructions that were removed.
122 unsigned removeBranch(MachineBasicBlock &MBB,
123 int *BytesRemoved = nullptr) const override;
124
125 /// Insert branch code into the end of the specified MachineBasicBlock.
126 /// The operands to this method are the same as those
127 /// returned by analyzeBranch. This is only invoked in cases where
128 /// analyzeBranch returns success. It returns the number of instructions
129 /// inserted.
130 ///
131 /// It is also invoked by tail merging to add unconditional branches in
132 /// cases where analyzeBranch doesn't apply because there was no original
133 /// branch to analyze. At least this much must be implemented, else tail
134 /// merging needs to be disabled.
135 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
136 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
137 const DebugLoc &DL,
138 int *BytesAdded = nullptr) const override;
139
140 /// Analyze loop L, which must be a single-basic-block loop, and if the
141 /// conditions can be understood enough produce a PipelinerLoopInfo object.
142 std::unique_ptr<PipelinerLoopInfo>
143 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
144
145 /// Return true if it's profitable to predicate
146 /// instructions with accumulated instruction latency of "NumCycles"
147 /// of the specified basic block, where the probability of the instructions
148 /// being executed is given by Probability, and Confidence is a measure
149 /// of our confidence that it will be properly predicted.
150 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
151 unsigned ExtraPredCycles,
152 BranchProbability Probability) const override;
153
154 /// Second variant of isProfitableToIfCvt. This one
155 /// checks for the case where two basic blocks from true and false path
156 /// of a if-then-else (diamond) are predicated on mutually exclusive
157 /// predicates, where the probability of the true path being taken is given
158 /// by Probability, and Confidence is a measure of our confidence that it
159 /// will be properly predicted.
160 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
161 unsigned NumTCycles, unsigned ExtraTCycles,
162 MachineBasicBlock &FMBB,
163 unsigned NumFCycles, unsigned ExtraFCycles,
164 BranchProbability Probability) const override;
165
166 /// Return true if it's profitable for if-converter to duplicate instructions
167 /// of specified accumulated instruction latencies in the specified MBB to
168 /// enable if-conversion.
169 /// The probability of the instructions being executed is given by
170 /// Probability, and Confidence is a measure of our confidence that it
171 /// will be properly predicted.
172 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
173 BranchProbability Probability) const override;
174
175 /// Emit instructions to copy a pair of physical registers.
176 ///
177 /// This function should support copies within any legal register class as
178 /// well as any cross-class copies created during instruction selection.
179 ///
180 /// The source and destination registers may overlap, which may require a
181 /// careful implementation when multiple copy instructions are required for
182 /// large registers. See for example the ARM target.
183 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
184 const DebugLoc &DL, Register DestReg, Register SrcReg,
185 bool KillSrc, bool RenamableDest = false,
186 bool RenamableSrc = false) const override;
187
188 /// Store the specified register of the given register class to the specified
189 /// stack frame index. The store instruction is to be added to the given
190 /// machine basic block before the specified machine instruction. If isKill
191 /// is true, the register operand is the last use and must be marked kill.
192 void storeRegToStackSlot(
193 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
194 bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
195 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
196
197 /// Load the specified register of the given register class from the specified
198 /// stack frame index. The load instruction is to be added to the given
199 /// machine basic block before the specified machine instruction.
200 void loadRegFromStackSlot(
201 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
202 Register DestReg, int FrameIndex, const TargetRegisterClass *RC,
203 Register VReg, unsigned SubReg = 0,
204 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
205
206 /// This function is called for all pseudo instructions
207 /// that remain after register allocation. Many pseudo instructions are
208 /// created to help register allocation. This is the place to convert them
209 /// into real instructions. The target can edit MI in place, or it can insert
210 /// new instructions and erase MI. The function should return true if
211 /// anything was changed.
212 bool expandPostRAPseudo(MachineInstr &MI) const override;
213
214 /// Get the base register and byte offset of a load/store instr.
215 bool getMemOperandsWithOffsetWidth(
216 const MachineInstr &LdSt,
217 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
218 bool &OffsetIsScalable, LocationSize &Width,
219 const TargetRegisterInfo *TRI) const override;
220
221 /// Reverses the branch condition of the specified condition list,
222 /// returning false on success and true if it cannot be reversed.
223 bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
224 const override;
225
226 /// Insert a noop into the instruction stream at the specified point.
227 void insertNoop(MachineBasicBlock &MBB,
228 MachineBasicBlock::iterator MI) const override;
229
230 /// Returns true if the instruction is already predicated.
231 bool isPredicated(const MachineInstr &MI) const override;
232
233 /// Return true for post-incremented instructions.
234 bool isPostIncrement(const MachineInstr &MI) const override;
235
236 /// Convert the instruction into a predicated instruction.
237 /// It returns true if the operation was successful.
238 bool PredicateInstruction(MachineInstr &MI,
239 ArrayRef<MachineOperand> Cond) const override;
240
241 /// Returns true if the first specified predicate
242 /// subsumes the second, e.g. GE subsumes GT.
243 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
244 ArrayRef<MachineOperand> Pred2) const override;
245
246 /// If the specified instruction defines any predicate
247 /// or condition code register(s) used for predication, returns true as well
248 /// as the definition predicate(s) by reference.
249 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
250 bool SkipDead) const override;
251
252 /// Return true if the specified instruction can be predicated.
253 /// By default, this returns true for every instruction with a
254 /// PredicateOperand.
255 bool isPredicable(const MachineInstr &MI) const override;
256
257 /// Test if the given instruction should be considered a scheduling boundary.
258 /// This primarily includes labels and terminators.
259 bool isSchedulingBoundary(const MachineInstr &MI,
260 const MachineBasicBlock *MBB,
261 const MachineFunction &MF) const override;
262
263 /// Measure the specified inline asm to determine an approximation of its
264 /// length.
265 unsigned getInlineAsmLength(
266 const char *Str,
267 const MCAsmInfo &MAI,
268 const TargetSubtargetInfo *STI = nullptr) const override;
269
270 /// Allocate and return a hazard recognizer to use for this target when
271 /// scheduling the machine instructions after register allocation.
272 ScheduleHazardRecognizer*
273 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
274 const ScheduleDAG *DAG) const override;
275
276 /// For a comparison instruction, return the source registers
277 /// in SrcReg and SrcReg2 if having two register operands, and the value it
278 /// compares against in CmpValue. Return true if the comparison instruction
279 /// can be analyzed.
280 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
281 Register &SrcReg2, int64_t &Mask,
282 int64_t &Value) const override;
283
284 /// Compute the instruction latency of a given instruction.
285 /// If the instruction has higher cost when predicated, it's returned via
286 /// PredCost.
287 unsigned getInstrLatency(const InstrItineraryData *ItinData,
288 const MachineInstr &MI,
289 unsigned *PredCost = nullptr) const override;
290
291 /// Create machine specific model for scheduling.
292 DFAPacketizer *
293 CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
294
295 // Sometimes, it is possible for the target
296 // to tell, even without aliasing information, that two MIs access different
297 // memory addresses. This function returns true if two MIs access different
298 // memory addresses and false otherwise.
299 bool
300 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
301 const MachineInstr &MIb) const override;
302
303 /// For instructions with a base and offset, return the position of the
304 /// base register and offset operands.
305 bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos,
306 unsigned &OffsetPos) const override;
307
308 /// If the instruction is an increment of a constant value, return the amount.
309 bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
310
311 /// getOperandLatency - Compute and return the use operand latency of a given
312 /// pair of def and use.
313 /// In most cases, the static scheduling itinerary was enough to determine the
314 /// operand latency. But it may not be possible for instructions with variable
315 /// number of defs / uses.
316 ///
317 /// This is a raw interface to the itinerary that may be directly overridden
318 /// by a target. Use computeOperandLatency to get the best estimate of
319 /// latency.
320 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
321 const MachineInstr &DefMI,
322 unsigned DefIdx,
323 const MachineInstr &UseMI,
324 unsigned UseIdx) const override;
325
326 /// Decompose the machine operand's target flags into two values - the direct
327 /// target flag value and any of bit flags that are applied.
328 std::pair<unsigned, unsigned>
329 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
330
331 /// Return an array that contains the direct target flag values and their
332 /// names.
333 ///
334 /// MIR Serialization is able to serialize only the target flags that are
335 /// defined by this method.
336 ArrayRef<std::pair<unsigned, const char *>>
337 getSerializableDirectMachineOperandTargetFlags() const override;
338
339 /// Return an array that contains the bitmask target flag values and their
340 /// names.
341 ///
342 /// MIR Serialization is able to serialize only the target flags that are
343 /// defined by this method.
344 ArrayRef<std::pair<unsigned, const char *>>
345 getSerializableBitmaskMachineOperandTargetFlags() const override;
346
347 bool isTailCall(const MachineInstr &MI) const override;
348 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
349
350 // Return true if the instruction should be sunk by MachineSink.
351 // MachineSink determines on its own whether the instruction is safe to sink;
352 // this gives the target a hook to override the default behavior with regards
353 // to which instructions should be sunk.
354 bool shouldSink(const MachineInstr &MI) const override;
355
356 /// HexagonInstrInfo specifics.
357
358 Register createVR(MachineFunction *MF, MVT VT) const;
359 MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp,
360 MachineBasicBlock *TargetBB,
361 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
362
363 bool isAbsoluteSet(const MachineInstr &MI) const;
364 bool isAccumulator(const MachineInstr &MI) const;
365 bool isAddrModeWithOffset(const MachineInstr &MI) const;
366 bool isBaseImmOffset(const MachineInstr &MI) const;
367 bool isComplex(const MachineInstr &MI) const;
368 bool isCompoundBranchInstr(const MachineInstr &MI) const;
369 bool isConstExtended(const MachineInstr &MI) const;
370 bool isDeallocRet(const MachineInstr &MI) const;
371 bool isDependent(const MachineInstr &ProdMI,
372 const MachineInstr &ConsMI) const;
373 bool isDotCurInst(const MachineInstr &MI) const;
374 bool isDotNewInst(const MachineInstr &MI) const;
375 bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
376 bool isEndLoopN(unsigned Opcode) const;
377 bool isExpr(unsigned OpType) const;
378 bool isExtendable(const MachineInstr &MI) const;
379 bool isExtended(const MachineInstr &MI) const;
380 bool isFloat(const MachineInstr &MI) const;
381 bool isHVXMemWithAIndirect(const MachineInstr &I,
382 const MachineInstr &J) const;
383 bool isIndirectCall(const MachineInstr &MI) const;
384 bool isIndirectL4Return(const MachineInstr &MI) const;
385 bool isJumpR(const MachineInstr &MI) const;
386 bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const;
387 bool isLateSourceInstr(const MachineInstr &MI) const;
388 bool isLoopN(const MachineInstr &MI) const;
389 bool isMemOp(const MachineInstr &MI) const;
390 bool isNewValue(const MachineInstr &MI) const;
391 bool isNewValue(unsigned Opcode) const;
392 bool isNewValueInst(const MachineInstr &MI) const;
393 bool isNewValueJump(const MachineInstr &MI) const;
394 bool isNewValueJump(unsigned Opcode) const;
395 bool isNewValueStore(const MachineInstr &MI) const;
396 bool isNewValueStore(unsigned Opcode) const;
397 bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const;
398 bool isPredicatedNew(const MachineInstr &MI) const;
399 bool isPredicatedNew(unsigned Opcode) const;
400 bool isPredicatedTrue(const MachineInstr &MI) const;
401 bool isPredicatedTrue(unsigned Opcode) const;
402 bool isPredicated(unsigned Opcode) const;
403 bool isPredicateLate(unsigned Opcode) const;
404 bool isPredictedTaken(unsigned Opcode) const;
405 bool isPureSlot0(const MachineInstr &MI) const;
406 bool isRestrictNoSlot1Store(const MachineInstr &MI) const;
407 bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const;
408 bool isSignExtendingLoad(const MachineInstr &MI) const;
409 bool isSolo(const MachineInstr &MI) const;
410 bool isSpillPredRegOp(const MachineInstr &MI) const;
411 bool isTC1(const MachineInstr &MI) const;
412 bool isTC2(const MachineInstr &MI) const;
413 bool isTC2Early(const MachineInstr &MI) const;
414 bool isTC4x(const MachineInstr &MI) const;
415 bool isToBeScheduledASAP(const MachineInstr &MI1,
416 const MachineInstr &MI2) const;
417 bool isHVXVec(const MachineInstr &MI) const;
418 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
419 bool isValidOffset(unsigned Opcode, int Offset,
420 const TargetRegisterInfo *TRI, bool Extend = true) const;
421 bool isVecAcc(const MachineInstr &MI) const;
422 bool isVecALU(const MachineInstr &MI) const;
423 bool isVecUsableNextPacket(const MachineInstr &ProdMI,
424 const MachineInstr &ConsMI) const;
425 bool isZeroExtendingLoad(const MachineInstr &MI) const;
426
427 bool addLatencyToSchedule(const MachineInstr &MI1,
428 const MachineInstr &MI2) const;
429 bool canExecuteInBundle(const MachineInstr &First,
430 const MachineInstr &Second) const;
431 bool doesNotReturn(const MachineInstr &CallMI) const;
432 bool hasEHLabel(const MachineBasicBlock *B) const;
433 bool hasNonExtEquivalent(const MachineInstr &MI) const;
434 bool hasPseudoInstrPair(const MachineInstr &MI) const;
435 bool hasUncondBranch(const MachineBasicBlock *B) const;
436 bool mayBeCurLoad(const MachineInstr &MI) const;
437 bool mayBeNewStore(const MachineInstr &MI) const;
438 bool producesStall(const MachineInstr &ProdMI,
439 const MachineInstr &ConsMI) const;
440 bool producesStall(const MachineInstr &MI,
441 MachineBasicBlock::const_instr_iterator MII) const;
442 bool predCanBeUsedAsDotNew(const MachineInstr &MI, Register PredReg) const;
443 bool PredOpcodeHasJMP_c(unsigned Opcode) const;
444 bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
445
446 unsigned getAddrMode(const MachineInstr &MI) const;
447 MachineOperand *getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
448 LocationSize &AccessSize) const;
449 SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
450 unsigned getCExtOpNum(const MachineInstr &MI) const;
451 HexagonII::CompoundGroup
452 getCompoundCandidateGroup(const MachineInstr &MI) const;
453 unsigned getCompoundOpcode(const MachineInstr &GA,
454 const MachineInstr &GB) const;
455 int getDuplexOpcode(const MachineInstr &MI, bool ForBigCore = true) const;
456 int getCondOpcode(int Opc, bool sense) const;
457 int getDotCurOp(const MachineInstr &MI) const;
458 int getNonDotCurOp(const MachineInstr &MI) const;
459 int getDotNewOp(const MachineInstr &MI) const;
460 int getDotNewPredJumpOp(const MachineInstr &MI,
461 const MachineBranchProbabilityInfo *MBPI) const;
462 int getDotNewPredOp(const MachineInstr &MI,
463 const MachineBranchProbabilityInfo *MBPI) const;
464 int getDotOldOp(const MachineInstr &MI) const;
465 HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI)
466 const;
467 short getEquivalentHWInstr(const MachineInstr &MI) const;
468 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
469 const MachineInstr &MI) const;
470 bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
471 unsigned getInvertedPredicatedOpcode(const int Opc) const;
472 int getMaxValue(const MachineInstr &MI) const;
473 unsigned getMemAccessSize(const MachineInstr &MI) const;
474 int getMinValue(const MachineInstr &MI) const;
475 short getNonExtOpcode(const MachineInstr &MI) const;
476 bool getPredReg(ArrayRef<MachineOperand> Cond, Register &PredReg,
477 unsigned &PredRegPos, RegState &PredRegFlags) const;
478 short getPseudoInstrPair(const MachineInstr &MI) const;
479 short getRegForm(const MachineInstr &MI) const;
480 unsigned getSize(const MachineInstr &MI) const;
481 uint64_t getType(const MachineInstr &MI) const;
482 InstrStage::FuncUnits getUnits(const MachineInstr &MI) const;
483
484 MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const;
485
486 /// getInstrTimingClassLatency - Compute the instruction latency of a given
487 /// instruction using Timing Class information, if available.
488 unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
489 unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
490
491 void immediateExtend(MachineInstr &MI) const;
492 bool invertAndChangeJumpTarget(MachineInstr &MI,
493 MachineBasicBlock *NewTarget) const;
494 void genAllInsnTimingClasses(MachineFunction &MF) const;
495 bool reversePredSense(MachineInstr &MI) const;
496 unsigned reversePrediction(unsigned Opcode) const;
497 bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
498
499 void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const;
500 bool getBundleNoShuf(const MachineInstr &MIB) const;
501
502 // When TinyCore with Duplexes is enabled, this function is used to translate
503 // tiny-instructions to big-instructions and vice versa to get the slot
504 // consumption.
505 void changeDuplexOpcode(MachineBasicBlock::instr_iterator MII,
506 bool ToBigInstrs) const;
507 void translateInstrsForDup(MachineFunction &MF,
508 bool ToBigInstrs = true) const;
509 void translateInstrsForDup(MachineBasicBlock::instr_iterator MII,
510 bool ToBigInstrs) const;
511 bool useMachineCombiner() const override { return true; }
512 bool isAssociativeAndCommutative(const MachineInstr &Inst,
513 bool Invert) const override;
514
515 // Addressing mode relations.
516 short changeAddrMode_abs_io(short Opc) const;
517 short changeAddrMode_io_abs(short Opc) const;
518 short changeAddrMode_io_pi(short Opc) const;
519 short changeAddrMode_io_rr(short Opc) const;
520 short changeAddrMode_pi_io(short Opc) const;
521 short changeAddrMode_rr_io(short Opc) const;
522 short changeAddrMode_rr_ur(short Opc) const;
523 short changeAddrMode_ur_rr(short Opc) const;
524
525 short changeAddrMode_abs_io(const MachineInstr &MI) const {
526 return changeAddrMode_abs_io(Opc: MI.getOpcode());
527 }
528 short changeAddrMode_io_abs(const MachineInstr &MI) const {
529 return changeAddrMode_io_abs(Opc: MI.getOpcode());
530 }
531 short changeAddrMode_io_rr(const MachineInstr &MI) const {
532 return changeAddrMode_io_rr(Opc: MI.getOpcode());
533 }
534 short changeAddrMode_rr_io(const MachineInstr &MI) const {
535 return changeAddrMode_rr_io(Opc: MI.getOpcode());
536 }
537 short changeAddrMode_rr_ur(const MachineInstr &MI) const {
538 return changeAddrMode_rr_ur(Opc: MI.getOpcode());
539 }
540 short changeAddrMode_ur_rr(const MachineInstr &MI) const {
541 return changeAddrMode_ur_rr(Opc: MI.getOpcode());
542 }
543
544 MCInst getNop() const override;
545 bool isQFPMul(const MachineInstr *MF) const;
546
547 // Check if the instruction uses a qf32/qf16 operand.
548 // 'Index' specifies the input operand number (1..3). If 0, check any.
549 bool usesQF32Operand(MachineInstr *MI, unsigned Index = 0) const;
550 bool usesQF16Operand(MachineInstr *MI, unsigned Index = 0) const;
551 bool usesQFOperand(MachineInstr *MI, unsigned Index = 0) const;
552
553 // Check if the instruction has a qf32/qf16 output.
554 bool isQFP32Instr(MachineInstr *MI) const;
555 bool isQFP16Instr(MachineInstr *MI) const;
556 bool isQFPInstr(MachineInstr *MI) const;
557};
558
559/// \brief Create RegSubRegPair from a register MachineOperand
560inline TargetInstrInfo::RegSubRegPair
561getRegSubRegPair(const MachineOperand &O) {
562 assert(O.isReg());
563 return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
564}
565
566} // end namespace llvm
567
568#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
569