1//===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the Hexagon specific subclass of TargetSubtarget.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
14#define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
15
16#include "HexagonDepArch.h"
17#include "HexagonFrameLowering.h"
18#include "HexagonISelLowering.h"
19#include "HexagonInstrInfo.h"
20#include "HexagonRegisterInfo.h"
21#include "HexagonSelectionDAGInfo.h"
22#include "llvm/ADT/SmallSet.h"
23#include "llvm/ADT/StringRef.h"
24#include "llvm/CodeGen/ScheduleDAGMutation.h"
25#include "llvm/CodeGen/TargetSubtargetInfo.h"
26#include "llvm/MC/MCInstrItineraries.h"
27#include "llvm/Support/Alignment.h"
28#include <bitset>
29#include <memory>
30#include <string>
31#include <vector>
32
33#define GET_SUBTARGETINFO_HEADER
34#include "HexagonGenSubtargetInfo.inc"
35
36namespace llvm {
37
38class LibcallLoweringInfo;
39class MachineInstr;
40class SDep;
41class SUnit;
42class TargetMachine;
43class Triple;
44
45class HexagonSubtarget : public HexagonGenSubtargetInfo {
46 virtual void anchor();
47
48 bool UseHVX64BOps = false;
49 bool UseHVX128BOps = false;
50
51 bool UseAudioOps = false;
52 bool UseCompound = false;
53 bool UseLongCalls = false;
54 bool UseMemops = false;
55 bool UsePackets = false;
56 bool UseNewValueJumps = false;
57 bool UseNewValueStores = false;
58 bool UseSmallData = false;
59 bool UseZRegOps = false;
60 bool UseHVXIEEEFPOps = false;
61 bool UseHVXQFloatOps = false;
62 bool UseHVXFloatingPoint = false;
63 bool UseCabac = false;
64
65 bool HasPreV65 = false;
66 bool HasMemNoShuf = false;
67 bool EnableDuplex = false;
68 std::bitset<Hexagon::NUM_TARGET_REGS> UserReservedRegister;
69 std::bitset<Hexagon::NUM_TARGET_REGS> SCSPointerRegister;
70 bool NoreturnStackElim = false;
71
72 /// Register holding the shadow call stack pointer, resolved from
73 /// SCSPointerRegister in initializeSubtargetDependencies().
74 Register SCSPReg;
75
76public:
77 Hexagon::ArchEnum HexagonArchVersion;
78 Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::NoArch;
79 CodeGenOptLevel OptLevel;
80 /// True if the target should use Back-Skip-Back scheduling. This is the
81 /// default for V60.
82 bool UseBSBScheduling;
83
84 struct UsrOverflowMutation : public ScheduleDAGMutation {
85 void apply(ScheduleDAGInstrs *DAG) override;
86 };
87 struct HVXMemLatencyMutation : public ScheduleDAGMutation {
88 void apply(ScheduleDAGInstrs *DAG) override;
89 };
90 struct CallMutation : public ScheduleDAGMutation {
91 void apply(ScheduleDAGInstrs *DAG) override;
92 private:
93 bool shouldTFRICallBind(const HexagonInstrInfo &HII,
94 const SUnit &Inst1, const SUnit &Inst2) const;
95 };
96 struct BankConflictMutation : public ScheduleDAGMutation {
97 void apply(ScheduleDAGInstrs *DAG) override;
98 };
99
100private:
101 enum HexagonProcFamilyEnum { Others, TinyCore };
102
103 std::string CPUString;
104 HexagonProcFamilyEnum HexagonProcFamily = Others;
105 Triple TargetTriple;
106
107 // The following objects can use the TargetTriple, so they must be
108 // declared after it.
109 HexagonInstrInfo InstrInfo;
110 HexagonTargetLowering TLInfo;
111 HexagonSelectionDAGInfo TSInfo;
112 HexagonFrameLowering FrameLowering;
113 InstrItineraryData InstrItins;
114
115public:
116 HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
117 const TargetMachine &TM);
118
119 const Triple &getTargetTriple() const { return TargetTriple; }
120 bool isEnvironmentMusl() const {
121 return TargetTriple.getEnvironment() == Triple::Musl;
122 }
123
124 /// getInstrItins - Return the instruction itineraries based on subtarget
125 /// selection.
126 const InstrItineraryData *getInstrItineraryData() const override {
127 return &InstrItins;
128 }
129 const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
130 const HexagonRegisterInfo *getRegisterInfo() const override {
131 return &InstrInfo.getRegisterInfo();
132 }
133 const HexagonTargetLowering *getTargetLowering() const override {
134 return &TLInfo;
135 }
136 const HexagonFrameLowering *getFrameLowering() const override {
137 return &FrameLowering;
138 }
139 const HexagonSelectionDAGInfo *getSelectionDAGInfo() const override {
140 return &TSInfo;
141 }
142
143 HexagonSubtarget &initializeSubtargetDependencies(StringRef CPU,
144 StringRef FS);
145
146 void initLibcallLoweringInfo(LibcallLoweringInfo &Info) const override;
147
148 /// ParseSubtargetFeatures - Parses features string setting specified
149 /// subtarget options. Definition of function is auto generated by tblgen.
150 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
151
152 bool isXRaySupported() const override { return true; }
153
154 bool hasV5Ops() const {
155 return getHexagonArchVersion() >= Hexagon::ArchEnum::V5;
156 }
157 bool hasV5OpsOnly() const {
158 return getHexagonArchVersion() == Hexagon::ArchEnum::V5;
159 }
160 bool hasV55Ops() const {
161 return getHexagonArchVersion() >= Hexagon::ArchEnum::V55;
162 }
163 bool hasV55OpsOnly() const {
164 return getHexagonArchVersion() == Hexagon::ArchEnum::V55;
165 }
166 bool hasV60Ops() const {
167 return getHexagonArchVersion() >= Hexagon::ArchEnum::V60;
168 }
169 bool hasV60OpsOnly() const {
170 return getHexagonArchVersion() == Hexagon::ArchEnum::V60;
171 }
172 bool hasV62Ops() const {
173 return getHexagonArchVersion() >= Hexagon::ArchEnum::V62;
174 }
175 bool hasV62OpsOnly() const {
176 return getHexagonArchVersion() == Hexagon::ArchEnum::V62;
177 }
178 bool hasV65Ops() const {
179 return getHexagonArchVersion() >= Hexagon::ArchEnum::V65;
180 }
181 bool hasV65OpsOnly() const {
182 return getHexagonArchVersion() == Hexagon::ArchEnum::V65;
183 }
184 bool hasV66Ops() const {
185 return getHexagonArchVersion() >= Hexagon::ArchEnum::V66;
186 }
187 bool hasV66OpsOnly() const {
188 return getHexagonArchVersion() == Hexagon::ArchEnum::V66;
189 }
190 bool hasV67Ops() const {
191 return getHexagonArchVersion() >= Hexagon::ArchEnum::V67;
192 }
193 bool hasV67OpsOnly() const {
194 return getHexagonArchVersion() == Hexagon::ArchEnum::V67;
195 }
196 bool hasV68Ops() const {
197 return getHexagonArchVersion() >= Hexagon::ArchEnum::V68;
198 }
199 bool hasV68OpsOnly() const {
200 return getHexagonArchVersion() == Hexagon::ArchEnum::V68;
201 }
202 bool hasV69Ops() const {
203 return getHexagonArchVersion() >= Hexagon::ArchEnum::V69;
204 }
205 bool hasV69OpsOnly() const {
206 return getHexagonArchVersion() == Hexagon::ArchEnum::V69;
207 }
208 bool hasV71Ops() const {
209 return getHexagonArchVersion() >= Hexagon::ArchEnum::V71;
210 }
211 bool hasV71OpsOnly() const {
212 return getHexagonArchVersion() == Hexagon::ArchEnum::V71;
213 }
214 bool hasV73Ops() const {
215 return getHexagonArchVersion() >= Hexagon::ArchEnum::V73;
216 }
217 bool hasV73OpsOnly() const {
218 return getHexagonArchVersion() == Hexagon::ArchEnum::V73;
219 }
220 bool hasV75Ops() const {
221 return getHexagonArchVersion() >= Hexagon::ArchEnum::V75;
222 }
223 bool hasV75OpsOnly() const {
224 return getHexagonArchVersion() == Hexagon::ArchEnum::V75;
225 }
226 bool hasV79Ops() const {
227 return getHexagonArchVersion() >= Hexagon::ArchEnum::V79;
228 }
229 bool hasV79OpsOnly() const {
230 return getHexagonArchVersion() == Hexagon::ArchEnum::V79;
231 }
232 bool useHVXV79Ops() const {
233 return HexagonHVXVersion >= Hexagon::ArchEnum::V79;
234 }
235 bool hasV81Ops() const {
236 return getHexagonArchVersion() >= Hexagon::ArchEnum::V81;
237 }
238 bool hasV81OpsOnly() const {
239 return getHexagonArchVersion() == Hexagon::ArchEnum::V81;
240 }
241 bool useHVXV81Ops() const {
242 return HexagonHVXVersion >= Hexagon::ArchEnum::V81;
243 }
244
245 bool useAudioOps() const { return UseAudioOps; }
246 bool useCompound() const { return UseCompound; }
247 bool useLongCalls() const { return UseLongCalls; }
248 bool useMemops() const { return UseMemops; }
249 bool usePackets() const { return UsePackets; }
250 bool useNewValueJumps() const { return UseNewValueJumps; }
251 bool useNewValueStores() const { return UseNewValueStores; }
252 bool useSmallData() const { return UseSmallData; }
253 bool useZRegOps() const { return UseZRegOps; }
254 bool useCabac() const { return UseCabac; }
255
256 bool isTinyCore() const { return HexagonProcFamily == TinyCore; }
257 bool isTinyCoreWithDuplex() const { return isTinyCore() && EnableDuplex; }
258
259 bool useHVXIEEEFPOps() const { return UseHVXIEEEFPOps && useHVXOps(); }
260 bool useHVXQFloatOps() const {
261 return UseHVXQFloatOps && HexagonHVXVersion >= Hexagon::ArchEnum::V68;
262 }
263 bool useHVXFloatingPoint() const { return UseHVXFloatingPoint; }
264 bool useHVXOps() const {
265 return HexagonHVXVersion > Hexagon::ArchEnum::NoArch;
266 }
267 bool useHVXV60Ops() const {
268 return HexagonHVXVersion >= Hexagon::ArchEnum::V60;
269 }
270 bool useHVXV62Ops() const {
271 return HexagonHVXVersion >= Hexagon::ArchEnum::V62;
272 }
273 bool useHVXV65Ops() const {
274 return HexagonHVXVersion >= Hexagon::ArchEnum::V65;
275 }
276 bool useHVXV66Ops() const {
277 return HexagonHVXVersion >= Hexagon::ArchEnum::V66;
278 }
279 bool useHVXV67Ops() const {
280 return HexagonHVXVersion >= Hexagon::ArchEnum::V67;
281 }
282 bool useHVXV68Ops() const {
283 return HexagonHVXVersion >= Hexagon::ArchEnum::V68;
284 }
285 bool useHVXV69Ops() const {
286 return HexagonHVXVersion >= Hexagon::ArchEnum::V69;
287 }
288 bool useHVXV71Ops() const {
289 return HexagonHVXVersion >= Hexagon::ArchEnum::V71;
290 }
291 bool useHVXV73Ops() const {
292 return HexagonHVXVersion >= Hexagon::ArchEnum::V73;
293 }
294 bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
295 bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
296
297 bool hasMemNoShuf() const { return HasMemNoShuf; }
298 bool isRegisterReservedByUser(Register i) const override {
299 assert(i.id() < Hexagon::NUM_TARGET_REGS && "Register out of range");
300 return UserReservedRegister[i.id()];
301 }
302
303 /// Returns the register that holds the shadow call stack pointer. Defaults
304 /// to R18, overridable with the "scs-reg-rN" subtarget features.
305 Register getSCSPReg() const { return SCSPReg; }
306
307 bool usePredicatedCalls() const;
308
309 bool noreturnStackElim() const { return NoreturnStackElim; }
310
311 bool useBSBScheduling() const { return UseBSBScheduling; }
312 bool enableMachineScheduler() const override;
313
314 // Always use the TargetLowering default scheduler.
315 // FIXME: This will use the vliw scheduler which is probably just hurting
316 // compiler time and will be removed eventually anyway.
317 bool enableMachineSchedDefaultSched() const override { return false; }
318
319 // For use with PostRAScheduling: get the anti-dependence breaking that should
320 // be performed before post-RA scheduling.
321 AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
322 /// True if the subtarget should run a scheduler after register
323 /// allocation.
324 bool enablePostRAScheduler() const override { return true; }
325
326 bool enableSubRegLiveness() const override;
327
328 const std::string &getCPUString () const { return CPUString; }
329
330 const Hexagon::ArchEnum &getHexagonArchVersion() const {
331 return HexagonArchVersion;
332 }
333
334 void getPostRAMutations(
335 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
336 const override;
337
338 void getSMSMutations(
339 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
340 const override;
341
342 /// Enable use of alias analysis during code generation (during MI
343 /// scheduling, DAGCombine, etc.).
344 bool useAA() const override;
345
346 /// Perform target specific adjustments to the latency of a schedule
347 /// dependency.
348 void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
349 SDep &Dep,
350 const TargetSchedModel *SchedModel) const override;
351
352 unsigned getVectorLength() const {
353 assert(useHVXOps());
354 if (useHVX64BOps())
355 return 64;
356 if (useHVX128BOps())
357 return 128;
358 llvm_unreachable("Invalid HVX vector length settings");
359 }
360
361 ArrayRef<MVT> getHVXElementTypes() const {
362 static MVT Types[] = {MVT::i8, MVT::i16, MVT::i32};
363 static MVT TypesV68[] = {MVT::i8, MVT::i16, MVT::i32, MVT::f16, MVT::f32};
364 static MVT TypesV81[] = {MVT::i8, MVT::i16, MVT::i32,
365 MVT::f16, MVT::bf16, MVT::f32};
366
367 if (useHVXV81Ops() && useHVXFloatingPoint())
368 return ArrayRef(TypesV81);
369 if (useHVXV68Ops() && useHVXFloatingPoint())
370 return ArrayRef(TypesV68);
371 return ArrayRef(Types);
372 }
373
374 bool isHVXElementType(MVT Ty, bool IncludeBool = false) const;
375 bool isHVXVectorType(EVT VecTy, bool IncludeBool = false) const;
376 bool isTypeForHVX(Type *VecTy, bool IncludeBool = false) const;
377
378 Align getTypeAlignment(MVT Ty) const {
379 if (isHVXVectorType(VecTy: Ty, IncludeBool: true))
380 return Align(getVectorLength());
381 return Align(std::max<unsigned>(a: 1, b: Ty.getSizeInBits() / 8));
382 }
383
384 unsigned getL1CacheLineSize() const;
385 unsigned getL1PrefetchDistance() const;
386
387 Intrinsic::ID getIntrinsicId(unsigned Opc) const;
388
389private:
390 // Helper function responsible for increasing the latency only.
391 int updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst,
392 bool IsArtificial, int Latency) const;
393 void restoreLatency(SUnit *Src, SUnit *Dst) const;
394 void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
395 bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
396 SmallPtrSet<SUnit *, 4> &ExclSrc,
397 SmallPtrSet<SUnit *, 4> &ExclDst) const;
398};
399
400} // end namespace llvm
401
402#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
403