1//===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the Hexagon specific subclass of TargetSubtarget.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
14#define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
15
16#include "HexagonDepArch.h"
17#include "HexagonFrameLowering.h"
18#include "HexagonISelLowering.h"
19#include "HexagonInstrInfo.h"
20#include "HexagonRegisterInfo.h"
21#include "HexagonSelectionDAGInfo.h"
22#include "llvm/ADT/SmallSet.h"
23#include "llvm/ADT/StringRef.h"
24#include "llvm/CodeGen/ScheduleDAGMutation.h"
25#include "llvm/CodeGen/TargetSubtargetInfo.h"
26#include "llvm/MC/MCInstrItineraries.h"
27#include "llvm/Support/Alignment.h"
28#include <bitset>
29#include <memory>
30#include <string>
31#include <vector>
32
33#define GET_SUBTARGETINFO_HEADER
34#include "HexagonGenSubtargetInfo.inc"
35
36namespace llvm {
37
38class MachineInstr;
39class SDep;
40class SUnit;
41class TargetMachine;
42class Triple;
43
44class HexagonSubtarget : public HexagonGenSubtargetInfo {
45 virtual void anchor();
46
47 bool UseHVX64BOps = false;
48 bool UseHVX128BOps = false;
49
50 bool UseAudioOps = false;
51 bool UseCompound = false;
52 bool UseLongCalls = false;
53 bool UseMemops = false;
54 bool UsePackets = false;
55 bool UseNewValueJumps = false;
56 bool UseNewValueStores = false;
57 bool UseSmallData = false;
58 bool UseZRegOps = false;
59 bool UseHVXIEEEFPOps = false;
60 bool UseHVXQFloatOps = false;
61 bool UseHVXFloatingPoint = false;
62 bool UseCabac = false;
63
64 bool HasPreV65 = false;
65 bool HasMemNoShuf = false;
66 bool EnableDuplex = false;
67 std::bitset<Hexagon::NUM_TARGET_REGS> UserReservedRegister;
68 bool NoreturnStackElim = false;
69
70public:
71 Hexagon::ArchEnum HexagonArchVersion;
72 Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::NoArch;
73 CodeGenOptLevel OptLevel;
74 /// True if the target should use Back-Skip-Back scheduling. This is the
75 /// default for V60.
76 bool UseBSBScheduling;
77
78 struct UsrOverflowMutation : public ScheduleDAGMutation {
79 void apply(ScheduleDAGInstrs *DAG) override;
80 };
81 struct HVXMemLatencyMutation : public ScheduleDAGMutation {
82 void apply(ScheduleDAGInstrs *DAG) override;
83 };
84 struct CallMutation : public ScheduleDAGMutation {
85 void apply(ScheduleDAGInstrs *DAG) override;
86 private:
87 bool shouldTFRICallBind(const HexagonInstrInfo &HII,
88 const SUnit &Inst1, const SUnit &Inst2) const;
89 };
90 struct BankConflictMutation : public ScheduleDAGMutation {
91 void apply(ScheduleDAGInstrs *DAG) override;
92 };
93
94private:
95 enum HexagonProcFamilyEnum { Others, TinyCore };
96
97 std::string CPUString;
98 HexagonProcFamilyEnum HexagonProcFamily = Others;
99 Triple TargetTriple;
100
101 // The following objects can use the TargetTriple, so they must be
102 // declared after it.
103 HexagonInstrInfo InstrInfo;
104 HexagonTargetLowering TLInfo;
105 HexagonSelectionDAGInfo TSInfo;
106 HexagonFrameLowering FrameLowering;
107 InstrItineraryData InstrItins;
108
109public:
110 HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
111 const TargetMachine &TM);
112
113 const Triple &getTargetTriple() const { return TargetTriple; }
114 bool isEnvironmentMusl() const {
115 return TargetTriple.getEnvironment() == Triple::Musl;
116 }
117
118 /// getInstrItins - Return the instruction itineraries based on subtarget
119 /// selection.
120 const InstrItineraryData *getInstrItineraryData() const override {
121 return &InstrItins;
122 }
123 const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
124 const HexagonRegisterInfo *getRegisterInfo() const override {
125 return &InstrInfo.getRegisterInfo();
126 }
127 const HexagonTargetLowering *getTargetLowering() const override {
128 return &TLInfo;
129 }
130 const HexagonFrameLowering *getFrameLowering() const override {
131 return &FrameLowering;
132 }
133 const HexagonSelectionDAGInfo *getSelectionDAGInfo() const override {
134 return &TSInfo;
135 }
136
137 HexagonSubtarget &initializeSubtargetDependencies(StringRef CPU,
138 StringRef FS);
139
140 /// ParseSubtargetFeatures - Parses features string setting specified
141 /// subtarget options. Definition of function is auto generated by tblgen.
142 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
143
144 bool isXRaySupported() const override { return true; }
145
146 bool hasV5Ops() const {
147 return getHexagonArchVersion() >= Hexagon::ArchEnum::V5;
148 }
149 bool hasV5OpsOnly() const {
150 return getHexagonArchVersion() == Hexagon::ArchEnum::V5;
151 }
152 bool hasV55Ops() const {
153 return getHexagonArchVersion() >= Hexagon::ArchEnum::V55;
154 }
155 bool hasV55OpsOnly() const {
156 return getHexagonArchVersion() == Hexagon::ArchEnum::V55;
157 }
158 bool hasV60Ops() const {
159 return getHexagonArchVersion() >= Hexagon::ArchEnum::V60;
160 }
161 bool hasV60OpsOnly() const {
162 return getHexagonArchVersion() == Hexagon::ArchEnum::V60;
163 }
164 bool hasV62Ops() const {
165 return getHexagonArchVersion() >= Hexagon::ArchEnum::V62;
166 }
167 bool hasV62OpsOnly() const {
168 return getHexagonArchVersion() == Hexagon::ArchEnum::V62;
169 }
170 bool hasV65Ops() const {
171 return getHexagonArchVersion() >= Hexagon::ArchEnum::V65;
172 }
173 bool hasV65OpsOnly() const {
174 return getHexagonArchVersion() == Hexagon::ArchEnum::V65;
175 }
176 bool hasV66Ops() const {
177 return getHexagonArchVersion() >= Hexagon::ArchEnum::V66;
178 }
179 bool hasV66OpsOnly() const {
180 return getHexagonArchVersion() == Hexagon::ArchEnum::V66;
181 }
182 bool hasV67Ops() const {
183 return getHexagonArchVersion() >= Hexagon::ArchEnum::V67;
184 }
185 bool hasV67OpsOnly() const {
186 return getHexagonArchVersion() == Hexagon::ArchEnum::V67;
187 }
188 bool hasV68Ops() const {
189 return getHexagonArchVersion() >= Hexagon::ArchEnum::V68;
190 }
191 bool hasV68OpsOnly() const {
192 return getHexagonArchVersion() == Hexagon::ArchEnum::V68;
193 }
194 bool hasV69Ops() const {
195 return getHexagonArchVersion() >= Hexagon::ArchEnum::V69;
196 }
197 bool hasV69OpsOnly() const {
198 return getHexagonArchVersion() == Hexagon::ArchEnum::V69;
199 }
200 bool hasV71Ops() const {
201 return getHexagonArchVersion() >= Hexagon::ArchEnum::V71;
202 }
203 bool hasV71OpsOnly() const {
204 return getHexagonArchVersion() == Hexagon::ArchEnum::V71;
205 }
206 bool hasV73Ops() const {
207 return getHexagonArchVersion() >= Hexagon::ArchEnum::V73;
208 }
209 bool hasV73OpsOnly() const {
210 return getHexagonArchVersion() == Hexagon::ArchEnum::V73;
211 }
212 bool hasV75Ops() const {
213 return getHexagonArchVersion() >= Hexagon::ArchEnum::V75;
214 }
215 bool hasV75OpsOnly() const {
216 return getHexagonArchVersion() == Hexagon::ArchEnum::V75;
217 }
218 bool hasV79Ops() const {
219 return getHexagonArchVersion() >= Hexagon::ArchEnum::V79;
220 }
221 bool hasV79OpsOnly() const {
222 return getHexagonArchVersion() == Hexagon::ArchEnum::V79;
223 }
224 bool useHVXV79Ops() const {
225 return HexagonHVXVersion >= Hexagon::ArchEnum::V79;
226 }
227 bool hasV81Ops() const {
228 return getHexagonArchVersion() >= Hexagon::ArchEnum::V81;
229 }
230 bool hasV81OpsOnly() const {
231 return getHexagonArchVersion() == Hexagon::ArchEnum::V81;
232 }
233 bool useHVXV81Ops() const {
234 return HexagonHVXVersion >= Hexagon::ArchEnum::V81;
235 }
236
237 bool useAudioOps() const { return UseAudioOps; }
238 bool useCompound() const { return UseCompound; }
239 bool useLongCalls() const { return UseLongCalls; }
240 bool useMemops() const { return UseMemops; }
241 bool usePackets() const { return UsePackets; }
242 bool useNewValueJumps() const { return UseNewValueJumps; }
243 bool useNewValueStores() const { return UseNewValueStores; }
244 bool useSmallData() const { return UseSmallData; }
245 bool useZRegOps() const { return UseZRegOps; }
246 bool useCabac() const { return UseCabac; }
247
248 bool isTinyCore() const { return HexagonProcFamily == TinyCore; }
249 bool isTinyCoreWithDuplex() const { return isTinyCore() && EnableDuplex; }
250
251 bool useHVXIEEEFPOps() const { return UseHVXIEEEFPOps && useHVXOps(); }
252 bool useHVXQFloatOps() const {
253 return UseHVXQFloatOps && HexagonHVXVersion >= Hexagon::ArchEnum::V68;
254 }
255 bool useHVXFloatingPoint() const { return UseHVXFloatingPoint; }
256 bool useHVXOps() const {
257 return HexagonHVXVersion > Hexagon::ArchEnum::NoArch;
258 }
259 bool useHVXV60Ops() const {
260 return HexagonHVXVersion >= Hexagon::ArchEnum::V60;
261 }
262 bool useHVXV62Ops() const {
263 return HexagonHVXVersion >= Hexagon::ArchEnum::V62;
264 }
265 bool useHVXV65Ops() const {
266 return HexagonHVXVersion >= Hexagon::ArchEnum::V65;
267 }
268 bool useHVXV66Ops() const {
269 return HexagonHVXVersion >= Hexagon::ArchEnum::V66;
270 }
271 bool useHVXV67Ops() const {
272 return HexagonHVXVersion >= Hexagon::ArchEnum::V67;
273 }
274 bool useHVXV68Ops() const {
275 return HexagonHVXVersion >= Hexagon::ArchEnum::V68;
276 }
277 bool useHVXV69Ops() const {
278 return HexagonHVXVersion >= Hexagon::ArchEnum::V69;
279 }
280 bool useHVXV71Ops() const {
281 return HexagonHVXVersion >= Hexagon::ArchEnum::V71;
282 }
283 bool useHVXV73Ops() const {
284 return HexagonHVXVersion >= Hexagon::ArchEnum::V73;
285 }
286 bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
287 bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
288
289 bool hasMemNoShuf() const { return HasMemNoShuf; }
290 bool isRegisterReservedByUser(Register i) const override {
291 assert(i.id() < Hexagon::NUM_TARGET_REGS && "Register out of range");
292 return UserReservedRegister[i.id()];
293 }
294 bool usePredicatedCalls() const;
295
296 bool noreturnStackElim() const { return NoreturnStackElim; }
297
298 bool useBSBScheduling() const { return UseBSBScheduling; }
299 bool enableMachineScheduler() const override;
300
301 // Always use the TargetLowering default scheduler.
302 // FIXME: This will use the vliw scheduler which is probably just hurting
303 // compiler time and will be removed eventually anyway.
304 bool enableMachineSchedDefaultSched() const override { return false; }
305
306 // For use with PostRAScheduling: get the anti-dependence breaking that should
307 // be performed before post-RA scheduling.
308 AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
309 /// True if the subtarget should run a scheduler after register
310 /// allocation.
311 bool enablePostRAScheduler() const override { return true; }
312
313 bool enableSubRegLiveness() const override;
314
315 const std::string &getCPUString () const { return CPUString; }
316
317 const Hexagon::ArchEnum &getHexagonArchVersion() const {
318 return HexagonArchVersion;
319 }
320
321 void getPostRAMutations(
322 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
323 const override;
324
325 void getSMSMutations(
326 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
327 const override;
328
329 /// Enable use of alias analysis during code generation (during MI
330 /// scheduling, DAGCombine, etc.).
331 bool useAA() const override;
332
333 /// Perform target specific adjustments to the latency of a schedule
334 /// dependency.
335 void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
336 SDep &Dep,
337 const TargetSchedModel *SchedModel) const override;
338
339 unsigned getVectorLength() const {
340 assert(useHVXOps());
341 if (useHVX64BOps())
342 return 64;
343 if (useHVX128BOps())
344 return 128;
345 llvm_unreachable("Invalid HVX vector length settings");
346 }
347
348 ArrayRef<MVT> getHVXElementTypes() const {
349 static MVT Types[] = {MVT::i8, MVT::i16, MVT::i32};
350 static MVT TypesV68[] = {MVT::i8, MVT::i16, MVT::i32, MVT::f16, MVT::f32};
351 static MVT TypesV81[] = {MVT::i8, MVT::i16, MVT::i32,
352 MVT::f16, MVT::bf16, MVT::f32};
353
354 if (useHVXV81Ops() && useHVXFloatingPoint())
355 return ArrayRef(TypesV81);
356 if (useHVXV68Ops() && useHVXFloatingPoint())
357 return ArrayRef(TypesV68);
358 return ArrayRef(Types);
359 }
360
361 bool isHVXElementType(MVT Ty, bool IncludeBool = false) const;
362 bool isHVXVectorType(EVT VecTy, bool IncludeBool = false) const;
363 bool isTypeForHVX(Type *VecTy, bool IncludeBool = false) const;
364
365 Align getTypeAlignment(MVT Ty) const {
366 if (isHVXVectorType(VecTy: Ty, IncludeBool: true))
367 return Align(getVectorLength());
368 return Align(std::max<unsigned>(a: 1, b: Ty.getSizeInBits() / 8));
369 }
370
371 unsigned getL1CacheLineSize() const;
372 unsigned getL1PrefetchDistance() const;
373
374 Intrinsic::ID getIntrinsicId(unsigned Opc) const;
375
376private:
377 // Helper function responsible for increasing the latency only.
378 int updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst,
379 bool IsArtificial, int Latency) const;
380 void restoreLatency(SUnit *Src, SUnit *Dst) const;
381 void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
382 bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
383 SmallPtrSet<SUnit *, 4> &ExclSrc,
384 SmallPtrSet<SUnit *, 4> &ExclDst) const;
385};
386
387} // end namespace llvm
388
389#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
390