| 1 | //===-- HexagonSelectionDAGInfo.h - Hexagon SelectionDAG Info ---*- C++ -*-===// |
| 2 | // |
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | // |
| 9 | // This file defines the Hexagon subclass for SelectionDAGTargetInfo. |
| 10 | // |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | |
| 13 | #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSELECTIONDAGINFO_H |
| 14 | #define LLVM_LIB_TARGET_HEXAGON_HEXAGONSELECTIONDAGINFO_H |
| 15 | |
| 16 | #include "llvm/CodeGen/SelectionDAGTargetInfo.h" |
| 17 | |
| 18 | #define GET_SDNODE_ENUM |
| 19 | #include "HexagonGenSDNodeInfo.inc" |
| 20 | |
| 21 | namespace llvm { |
| 22 | namespace HexagonISD { |
| 23 | |
| 24 | enum NodeType : unsigned { |
| 25 | CALLR = GENERATED_OPCODE_END, |
| 26 | |
| 27 | VROR, |
| 28 | D2P, // Convert 8-byte value to 8-bit predicate register. [*] |
| 29 | P2D, // Convert 8-bit predicate register to 8-byte value. [*] |
| 30 | V2Q, // Convert HVX vector to a vector predicate reg. [*] |
| 31 | Q2V, // Convert vector predicate to an HVX vector. [*] |
| 32 | // [*] The equivalence is defined as "Q <=> (V != 0)", |
| 33 | // where the != operation compares bytes. |
| 34 | // Note: V != 0 is implemented as V >u 0. |
| 35 | |
| 36 | TL_EXTEND, // Wrappers for ISD::*_EXTEND and ISD::TRUNCATE to prevent DAG |
| 37 | TL_TRUNCATE, // from auto-folding operations, e.g. |
| 38 | // (i32 ext (i16 ext i8)) would be folded to (i32 ext i8). |
| 39 | // To simplify the type legalization, we want to keep these |
| 40 | // single steps separate during type legalization. |
| 41 | // TL_[EXTEND|TRUNCATE] Inp, i128 _, i32 Opc |
| 42 | // * Inp is the original input to extend/truncate, |
| 43 | // * _ is a dummy operand with an illegal type (can be undef), |
| 44 | // * Opc is the original opcode. |
| 45 | // The legalization process (in Hexagon lowering code) will |
| 46 | // first deal with the "real" types (i.e. Inp and the result), |
| 47 | // and once all of them are processed, the wrapper node will |
| 48 | // be replaced with the original ISD node. The dummy illegal |
| 49 | // operand is there to make sure that the legalization hooks |
| 50 | // are called again after everything else is legal, giving |
| 51 | // us the opportunity to undo the wrapping. |
| 52 | |
| 53 | TYPECAST, // No-op that's used to convert between different legal |
| 54 | // types in a register. |
| 55 | ISEL, // Marker for nodes that were created during ISel, and |
| 56 | // which need explicit selection (would have been left |
| 57 | // unselected otherwise). |
| 58 | }; |
| 59 | |
| 60 | } // namespace HexagonISD |
| 61 | |
| 62 | class HexagonSelectionDAGInfo : public SelectionDAGGenTargetInfo { |
| 63 | public: |
| 64 | HexagonSelectionDAGInfo(); |
| 65 | |
| 66 | const char *getTargetNodeName(unsigned Opcode) const override; |
| 67 | |
| 68 | void verifyTargetNode(const SelectionDAG &DAG, |
| 69 | const SDNode *N) const override; |
| 70 | |
| 71 | SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, |
| 72 | SDValue Chain, SDValue Dst, SDValue Src, |
| 73 | SDValue Size, Align Alignment, |
| 74 | bool isVolatile, bool AlwaysInline, |
| 75 | MachinePointerInfo DstPtrInfo, |
| 76 | MachinePointerInfo SrcPtrInfo) const override; |
| 77 | }; |
| 78 | |
| 79 | } // namespace llvm |
| 80 | |
| 81 | #endif |
| 82 | |