1//===- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ---===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to Hexagon assembly language. This printer is
11// the output mechanism used by `llc'.
12//
13//===----------------------------------------------------------------------===//
14
15#include "HexagonAsmPrinter.h"
16#include "HexagonInstrInfo.h"
17#include "HexagonRegisterInfo.h"
18#include "HexagonSubtarget.h"
19#include "MCTargetDesc/HexagonInstPrinter.h"
20#include "MCTargetDesc/HexagonMCChecker.h"
21#include "MCTargetDesc/HexagonMCExpr.h"
22#include "MCTargetDesc/HexagonMCInstrInfo.h"
23#include "MCTargetDesc/HexagonMCTargetDesc.h"
24#include "MCTargetDesc/HexagonTargetStreamer.h"
25#include "TargetInfo/HexagonTargetInfo.h"
26#include "llvm/ADT/StringExtras.h"
27#include "llvm/ADT/StringRef.h"
28#include "llvm/ADT/Twine.h"
29#include "llvm/BinaryFormat/ELF.h"
30#include "llvm/CodeGen/AsmPrinter.h"
31#include "llvm/CodeGen/MachineBasicBlock.h"
32#include "llvm/CodeGen/MachineFunction.h"
33#include "llvm/CodeGen/MachineInstr.h"
34#include "llvm/CodeGen/MachineOperand.h"
35#include "llvm/CodeGen/TargetRegisterInfo.h"
36#include "llvm/CodeGen/TargetSubtargetInfo.h"
37#include "llvm/IR/Module.h"
38#include "llvm/MC/MCContext.h"
39#include "llvm/MC/MCDirectives.h"
40#include "llvm/MC/MCExpr.h"
41#include "llvm/MC/MCInst.h"
42#include "llvm/MC/MCRegisterInfo.h"
43#include "llvm/MC/MCSectionELF.h"
44#include "llvm/MC/MCStreamer.h"
45#include "llvm/MC/MCSymbol.h"
46#include "llvm/MC/TargetRegistry.h"
47#include "llvm/Support/Casting.h"
48#include "llvm/Support/Compiler.h"
49#include "llvm/Support/ErrorHandling.h"
50#include "llvm/Support/raw_ostream.h"
51#include "llvm/Target/TargetMachine.h"
52#include <cassert>
53#include <cstdint>
54#include <string>
55
56using namespace llvm;
57
58namespace llvm {
59
60void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
61 MCInst &MCB, HexagonAsmPrinter &AP);
62
63} // end namespace llvm
64
65#define DEBUG_TYPE "asm-printer"
66
67// Given a scalar register return its pair.
68inline static unsigned getHexagonRegisterPair(unsigned Reg,
69 const MCRegisterInfo *RI) {
70 assert(Hexagon::IntRegsRegClass.contains(Reg));
71 unsigned Pair = *RI->superregs(Reg).begin();
72 assert(Hexagon::DoubleRegsRegClass.contains(Pair));
73 return Pair;
74}
75
76void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
77 raw_ostream &O) {
78 const MachineOperand &MO = MI->getOperand(i: OpNo);
79
80 switch (MO.getType()) {
81 default:
82 llvm_unreachable ("<unknown operand type>");
83 case MachineOperand::MO_Register:
84 O << HexagonInstPrinter::getRegisterName(Reg: MO.getReg());
85 return;
86 case MachineOperand::MO_Immediate:
87 O << MO.getImm();
88 return;
89 case MachineOperand::MO_MachineBasicBlock:
90 MO.getMBB()->getSymbol()->print(OS&: O, MAI);
91 return;
92 case MachineOperand::MO_ConstantPoolIndex:
93 GetCPISymbol(CPID: MO.getIndex())->print(OS&: O, MAI);
94 return;
95 case MachineOperand::MO_GlobalAddress:
96 PrintSymbolOperand(MO, OS&: O);
97 return;
98 }
99}
100
101// isBlockOnlyReachableByFallthrough - We need to override this since the
102// default AsmPrinter does not print labels for any basic block that
103// is only reachable by a fall through. That works for all cases except
104// for the case in which the basic block is reachable by a fall through but
105// through an indirect from a jump table. In this case, the jump table
106// will contain a label not defined by AsmPrinter.
107bool HexagonAsmPrinter::isBlockOnlyReachableByFallthrough(
108 const MachineBasicBlock *MBB) const {
109 if (MBB->hasAddressTaken())
110 return false;
111 return AsmPrinter::isBlockOnlyReachableByFallthrough(MBB);
112}
113
114/// PrintAsmOperand - Print out an operand for an inline asm expression.
115bool HexagonAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
116 const char *ExtraCode,
117 raw_ostream &OS) {
118 // Does this asm operand have a single letter operand modifier?
119 if (ExtraCode && ExtraCode[0]) {
120 if (ExtraCode[1] != 0)
121 return true; // Unknown modifier.
122
123 switch (ExtraCode[0]) {
124 default:
125 // See if this is a generic print operand
126 return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
127 case 'L':
128 case 'H': { // The highest-numbered register of a pair.
129 const MachineOperand &MO = MI->getOperand(i: OpNo);
130 const MachineFunction &MF = *MI->getParent()->getParent();
131 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
132 if (!MO.isReg())
133 return true;
134 Register RegNumber = MO.getReg();
135 // This should be an assert in the frontend.
136 if (Hexagon::DoubleRegsRegClass.contains(Reg: RegNumber))
137 RegNumber = TRI->getSubReg(Reg: RegNumber, Idx: ExtraCode[0] == 'L' ?
138 Hexagon::isub_lo :
139 Hexagon::isub_hi);
140 OS << HexagonInstPrinter::getRegisterName(Reg: RegNumber);
141 return false;
142 }
143 case 'I':
144 // Write 'i' if an integer constant, otherwise nothing. Used to print
145 // addi vs add, etc.
146 if (MI->getOperand(i: OpNo).isImm())
147 OS << "i";
148 return false;
149 }
150 }
151
152 printOperand(MI, OpNo, O&: OS);
153 return false;
154}
155
156bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
157 unsigned OpNo,
158 const char *ExtraCode,
159 raw_ostream &O) {
160 if (ExtraCode && ExtraCode[0])
161 return true; // Unknown modifier.
162
163 const MachineOperand &Base = MI->getOperand(i: OpNo);
164 const MachineOperand &Offset = MI->getOperand(i: OpNo+1);
165
166 if (Base.isReg())
167 printOperand(MI, OpNo, O);
168 else
169 llvm_unreachable("Unimplemented");
170
171 if (Offset.isImm()) {
172 if (Offset.getImm())
173 O << "+#" << Offset.getImm();
174 } else {
175 llvm_unreachable("Unimplemented");
176 }
177
178 return false;
179}
180
181static MCSymbol *smallData(AsmPrinter &AP, const MachineInstr &MI,
182 MCStreamer &OutStreamer, const MCOperand &Imm,
183 int AlignSize, const MCSubtargetInfo& STI) {
184 MCSymbol *Sym;
185 int64_t Value;
186 if (Imm.getExpr()->evaluateAsAbsolute(Res&: Value)) {
187 StringRef sectionPrefix;
188 std::string ImmString;
189 StringRef Name;
190 if (AlignSize == 8) {
191 Name = ".CONST_0000000000000000";
192 sectionPrefix = ".gnu.linkonce.l8";
193 ImmString = utohexstr(X: Value);
194 } else {
195 Name = ".CONST_00000000";
196 sectionPrefix = ".gnu.linkonce.l4";
197 ImmString = utohexstr(X: static_cast<uint32_t>(Value));
198 }
199
200 std::string symbolName = // Yes, leading zeros are kept.
201 Name.drop_back(N: ImmString.size()).str() + ImmString;
202 std::string sectionName = sectionPrefix.str() + symbolName;
203
204 MCSectionELF *Section = OutStreamer.getContext().getELFSection(
205 Section: sectionName, Type: ELF::SHT_PROGBITS, Flags: ELF::SHF_WRITE | ELF::SHF_ALLOC);
206 OutStreamer.switchSection(Section);
207
208 Sym = AP.OutContext.getOrCreateSymbol(Name: Twine(symbolName));
209 if (Sym->isUndefined()) {
210 OutStreamer.emitLabel(Symbol: Sym);
211 OutStreamer.emitSymbolAttribute(Symbol: Sym, Attribute: MCSA_Global);
212 OutStreamer.emitIntValue(Value, Size: AlignSize);
213 OutStreamer.emitCodeAlignment(Alignment: Align(AlignSize), STI);
214 }
215 } else {
216 assert(Imm.isExpr() && "Expected expression and found none");
217 const MachineOperand &MO = MI.getOperand(i: 1);
218 assert(MO.isGlobal() || MO.isCPI() || MO.isJTI());
219 MCSymbol *MOSymbol = nullptr;
220 if (MO.isGlobal())
221 MOSymbol = AP.getSymbol(GV: MO.getGlobal());
222 else if (MO.isCPI())
223 MOSymbol = AP.GetCPISymbol(CPID: MO.getIndex());
224 else if (MO.isJTI())
225 MOSymbol = AP.GetJTISymbol(JTID: MO.getIndex());
226 else
227 llvm_unreachable("Unknown operand type!");
228
229 StringRef SymbolName = MOSymbol->getName();
230 std::string LitaName = ".CONST_" + SymbolName.str();
231
232 MCSectionELF *Section = OutStreamer.getContext().getELFSection(
233 Section: ".lita", Type: ELF::SHT_PROGBITS, Flags: ELF::SHF_WRITE | ELF::SHF_ALLOC);
234
235 OutStreamer.switchSection(Section);
236 Sym = AP.OutContext.getOrCreateSymbol(Name: Twine(LitaName));
237 if (Sym->isUndefined()) {
238 OutStreamer.emitLabel(Symbol: Sym);
239 OutStreamer.emitSymbolAttribute(Symbol: Sym, Attribute: MCSA_Local);
240 OutStreamer.emitValue(Value: Imm.getExpr(), Size: AlignSize);
241 OutStreamer.emitCodeAlignment(Alignment: Align(AlignSize), STI);
242 }
243 }
244 return Sym;
245}
246
247static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo,
248 unsigned VectorSize, MCContext &Ctx) {
249 MCInst T;
250 T.setOpcode(Inst.getOpcode());
251 for (unsigned i = 0, n = Inst.getNumOperands(); i != n; ++i) {
252 if (i != OpNo) {
253 T.addOperand(Op: Inst.getOperand(i));
254 continue;
255 }
256 MCOperand &ImmOp = Inst.getOperand(i);
257 const auto *HE = static_cast<const HexagonMCExpr*>(ImmOp.getExpr());
258 int32_t V = cast<MCConstantExpr>(Val: HE->getExpr())->getValue();
259 auto *NewCE = MCConstantExpr::create(Value: V / int32_t(VectorSize), Ctx);
260 auto *NewHE = HexagonMCExpr::create(Expr: NewCE, Ctx);
261 T.addOperand(Op: MCOperand::createExpr(Val: NewHE));
262 }
263 return T;
264}
265
266void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
267 const MachineInstr &MI) {
268 MCInst &MappedInst = static_cast <MCInst &>(Inst);
269 const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo();
270 const MachineFunction &MF = *MI.getParent()->getParent();
271 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
272 unsigned VectorSize = HRI.getRegSizeInBits(RC: Hexagon::HvxVRRegClass) / 8;
273
274 switch (Inst.getOpcode()) {
275 default:
276 return;
277
278 case Hexagon::A2_iconst: {
279 Inst.setOpcode(Hexagon::A2_addi);
280 MCOperand Reg = Inst.getOperand(i: 0);
281 MCOperand S16 = Inst.getOperand(i: 1);
282 HexagonMCInstrInfo::setMustNotExtend(Expr: *S16.getExpr());
283 HexagonMCInstrInfo::setS27_2_reloc(Expr: *S16.getExpr());
284 Inst.clear();
285 Inst.addOperand(Op: Reg);
286 Inst.addOperand(Op: MCOperand::createReg(Reg: Hexagon::R0));
287 Inst.addOperand(Op: S16);
288 break;
289 }
290
291 case Hexagon::A2_tfrf: {
292 const MCConstantExpr *Zero = MCConstantExpr::create(Value: 0, Ctx&: OutContext);
293 Inst.setOpcode(Hexagon::A2_paddif);
294 Inst.addOperand(Op: MCOperand::createExpr(Val: Zero));
295 break;
296 }
297
298 case Hexagon::A2_tfrt: {
299 const MCConstantExpr *Zero = MCConstantExpr::create(Value: 0, Ctx&: OutContext);
300 Inst.setOpcode(Hexagon::A2_paddit);
301 Inst.addOperand(Op: MCOperand::createExpr(Val: Zero));
302 break;
303 }
304
305 case Hexagon::A2_tfrfnew: {
306 const MCConstantExpr *Zero = MCConstantExpr::create(Value: 0, Ctx&: OutContext);
307 Inst.setOpcode(Hexagon::A2_paddifnew);
308 Inst.addOperand(Op: MCOperand::createExpr(Val: Zero));
309 break;
310 }
311
312 case Hexagon::A2_tfrtnew: {
313 const MCConstantExpr *Zero = MCConstantExpr::create(Value: 0, Ctx&: OutContext);
314 Inst.setOpcode(Hexagon::A2_padditnew);
315 Inst.addOperand(Op: MCOperand::createExpr(Val: Zero));
316 break;
317 }
318
319 case Hexagon::A2_zxtb: {
320 const MCConstantExpr *C255 = MCConstantExpr::create(Value: 255, Ctx&: OutContext);
321 Inst.setOpcode(Hexagon::A2_andir);
322 Inst.addOperand(Op: MCOperand::createExpr(Val: C255));
323 break;
324 }
325
326 // "$dst = CONST64(#$src1)",
327 case Hexagon::CONST64:
328 if (!OutStreamer->hasRawTextSupport()) {
329 const MCOperand &Imm = MappedInst.getOperand(i: 1);
330 MCSectionSubPair Current = OutStreamer->getCurrentSection();
331
332 MCSymbol *Sym =
333 smallData(AP&: *this, MI, OutStreamer&: *OutStreamer, Imm, AlignSize: 8, STI: getSubtargetInfo());
334
335 OutStreamer->switchSection(Section: Current.first, Subsec: Current.second);
336 MCInst TmpInst;
337 MCOperand &Reg = MappedInst.getOperand(i: 0);
338 TmpInst.setOpcode(Hexagon::L2_loadrdgp);
339 TmpInst.addOperand(Op: Reg);
340 TmpInst.addOperand(Op: MCOperand::createExpr(
341 Val: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext)));
342 MappedInst = TmpInst;
343
344 }
345 break;
346 case Hexagon::CONST32:
347 if (!OutStreamer->hasRawTextSupport()) {
348 MCOperand &Imm = MappedInst.getOperand(i: 1);
349 MCSectionSubPair Current = OutStreamer->getCurrentSection();
350 MCSymbol *Sym =
351 smallData(AP&: *this, MI, OutStreamer&: *OutStreamer, Imm, AlignSize: 4, STI: getSubtargetInfo());
352 OutStreamer->switchSection(Section: Current.first, Subsec: Current.second);
353 MCInst TmpInst;
354 MCOperand &Reg = MappedInst.getOperand(i: 0);
355 TmpInst.setOpcode(Hexagon::L2_loadrigp);
356 TmpInst.addOperand(Op: Reg);
357 TmpInst.addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
358 Expr: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext), Ctx&: OutContext)));
359 MappedInst = TmpInst;
360 }
361 break;
362
363 // C2_pxfer_map maps to C2_or instruction. Though, it's possible to use
364 // C2_or during instruction selection itself but it results
365 // into suboptimal code.
366 case Hexagon::C2_pxfer_map: {
367 MCOperand &Ps = Inst.getOperand(i: 1);
368 MappedInst.setOpcode(Hexagon::C2_or);
369 MappedInst.addOperand(Op: Ps);
370 return;
371 }
372
373 // Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo
374 // The insn is mapped from the 4 operand to the 3 operand raw form taking
375 // 3 register pairs.
376 case Hexagon::M2_vrcmpys_acc_s1: {
377 MCOperand &Rt = Inst.getOperand(i: 3);
378 assert(Rt.isReg() && "Expected register and none was found");
379 unsigned Reg = RI->getEncodingValue(Reg: Rt.getReg());
380 if (Reg & 1)
381 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
382 else
383 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
384 Rt.setReg(getHexagonRegisterPair(Reg: Rt.getReg(), RI));
385 return;
386 }
387 case Hexagon::M2_vrcmpys_s1: {
388 MCOperand &Rt = Inst.getOperand(i: 2);
389 assert(Rt.isReg() && "Expected register and none was found");
390 unsigned Reg = RI->getEncodingValue(Reg: Rt.getReg());
391 if (Reg & 1)
392 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
393 else
394 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
395 Rt.setReg(getHexagonRegisterPair(Reg: Rt.getReg(), RI));
396 return;
397 }
398
399 case Hexagon::M2_vrcmpys_s1rp: {
400 MCOperand &Rt = Inst.getOperand(i: 2);
401 assert(Rt.isReg() && "Expected register and none was found");
402 unsigned Reg = RI->getEncodingValue(Reg: Rt.getReg());
403 if (Reg & 1)
404 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
405 else
406 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
407 Rt.setReg(getHexagonRegisterPair(Reg: Rt.getReg(), RI));
408 return;
409 }
410
411 case Hexagon::A4_boundscheck: {
412 MCOperand &Rs = Inst.getOperand(i: 1);
413 assert(Rs.isReg() && "Expected register and none was found");
414 unsigned Reg = RI->getEncodingValue(Reg: Rs.getReg());
415 if (Reg & 1) // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
416 MappedInst.setOpcode(Hexagon::A4_boundscheck_hi);
417 else // raw:lo
418 MappedInst.setOpcode(Hexagon::A4_boundscheck_lo);
419 Rs.setReg(getHexagonRegisterPair(Reg: Rs.getReg(), RI));
420 return;
421 }
422
423 case Hexagon::PS_call_nr:
424 Inst.setOpcode(Hexagon::J2_call);
425 break;
426
427 case Hexagon::PS_readcr:
428 Inst.setOpcode(Hexagon::A2_tfrcrr);
429 break;
430
431 case Hexagon::PS_readcr64:
432 Inst.setOpcode(Hexagon::A4_tfrcpp);
433 break;
434
435 case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
436 MCOperand &MO = MappedInst.getOperand(i: 2);
437 int64_t Imm;
438 MCExpr const *Expr = MO.getExpr();
439 bool Success = Expr->evaluateAsAbsolute(Res&: Imm);
440 assert(Success && "Expected immediate and none was found");
441 (void)Success;
442 MCInst TmpInst;
443 if (Imm == 0) {
444 TmpInst.setOpcode(Hexagon::S2_vsathub);
445 TmpInst.addOperand(Op: MappedInst.getOperand(i: 0));
446 TmpInst.addOperand(Op: MappedInst.getOperand(i: 1));
447 MappedInst = TmpInst;
448 return;
449 }
450 TmpInst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
451 TmpInst.addOperand(Op: MappedInst.getOperand(i: 0));
452 TmpInst.addOperand(Op: MappedInst.getOperand(i: 1));
453 const MCExpr *One = MCConstantExpr::create(Value: 1, Ctx&: OutContext);
454 const MCExpr *Sub = MCBinaryExpr::createSub(LHS: Expr, RHS: One, Ctx&: OutContext);
455 TmpInst.addOperand(
456 Op: MCOperand::createExpr(Val: HexagonMCExpr::create(Expr: Sub, Ctx&: OutContext)));
457 MappedInst = TmpInst;
458 return;
459 }
460
461 case Hexagon::S5_vasrhrnd_goodsyntax:
462 case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
463 MCOperand &MO2 = MappedInst.getOperand(i: 2);
464 MCExpr const *Expr = MO2.getExpr();
465 int64_t Imm;
466 bool Success = Expr->evaluateAsAbsolute(Res&: Imm);
467 assert(Success && "Expected immediate and none was found");
468 (void)Success;
469 MCInst TmpInst;
470 if (Imm == 0) {
471 TmpInst.setOpcode(Hexagon::A2_combinew);
472 TmpInst.addOperand(Op: MappedInst.getOperand(i: 0));
473 MCOperand &MO1 = MappedInst.getOperand(i: 1);
474 MCRegister High = RI->getSubReg(Reg: MO1.getReg(), Idx: Hexagon::isub_hi);
475 MCRegister Low = RI->getSubReg(Reg: MO1.getReg(), Idx: Hexagon::isub_lo);
476 // Add a new operand for the second register in the pair.
477 TmpInst.addOperand(Op: MCOperand::createReg(Reg: High));
478 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Low));
479 MappedInst = TmpInst;
480 return;
481 }
482
483 if (Inst.getOpcode() == Hexagon::S2_asr_i_p_rnd_goodsyntax)
484 TmpInst.setOpcode(Hexagon::S2_asr_i_p_rnd);
485 else
486 TmpInst.setOpcode(Hexagon::S5_vasrhrnd);
487 TmpInst.addOperand(Op: MappedInst.getOperand(i: 0));
488 TmpInst.addOperand(Op: MappedInst.getOperand(i: 1));
489 const MCExpr *One = MCConstantExpr::create(Value: 1, Ctx&: OutContext);
490 const MCExpr *Sub = MCBinaryExpr::createSub(LHS: Expr, RHS: One, Ctx&: OutContext);
491 TmpInst.addOperand(
492 Op: MCOperand::createExpr(Val: HexagonMCExpr::create(Expr: Sub, Ctx&: OutContext)));
493 MappedInst = TmpInst;
494 return;
495 }
496
497 // if ("#u5==0") Assembler mapped to: "Rd=Rs"; else Rd=asr(Rs,#u5-1):rnd
498 case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
499 MCOperand &MO = Inst.getOperand(i: 2);
500 MCExpr const *Expr = MO.getExpr();
501 int64_t Imm;
502 bool Success = Expr->evaluateAsAbsolute(Res&: Imm);
503 assert(Success && "Expected immediate and none was found");
504 (void)Success;
505 MCInst TmpInst;
506 if (Imm == 0) {
507 TmpInst.setOpcode(Hexagon::A2_tfr);
508 TmpInst.addOperand(Op: MappedInst.getOperand(i: 0));
509 TmpInst.addOperand(Op: MappedInst.getOperand(i: 1));
510 MappedInst = TmpInst;
511 return;
512 }
513 TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
514 TmpInst.addOperand(Op: MappedInst.getOperand(i: 0));
515 TmpInst.addOperand(Op: MappedInst.getOperand(i: 1));
516 const MCExpr *One = MCConstantExpr::create(Value: 1, Ctx&: OutContext);
517 const MCExpr *Sub = MCBinaryExpr::createSub(LHS: Expr, RHS: One, Ctx&: OutContext);
518 TmpInst.addOperand(
519 Op: MCOperand::createExpr(Val: HexagonMCExpr::create(Expr: Sub, Ctx&: OutContext)));
520 MappedInst = TmpInst;
521 return;
522 }
523
524 // Translate a "$Rdd = #imm" to "$Rdd = combine(#[-1,0], #imm)"
525 case Hexagon::A2_tfrpi: {
526 MCInst TmpInst;
527 MCOperand &Rdd = MappedInst.getOperand(i: 0);
528 MCOperand &MO = MappedInst.getOperand(i: 1);
529
530 TmpInst.setOpcode(Hexagon::A2_combineii);
531 TmpInst.addOperand(Op: Rdd);
532 int64_t Imm;
533 bool Success = MO.getExpr()->evaluateAsAbsolute(Res&: Imm);
534 if (Success && Imm < 0) {
535 const MCExpr *MOne = MCConstantExpr::create(Value: -1, Ctx&: OutContext);
536 const HexagonMCExpr *E = HexagonMCExpr::create(Expr: MOne, Ctx&: OutContext);
537 TmpInst.addOperand(Op: MCOperand::createExpr(Val: E));
538 } else {
539 const MCExpr *Zero = MCConstantExpr::create(Value: 0, Ctx&: OutContext);
540 const HexagonMCExpr *E = HexagonMCExpr::create(Expr: Zero, Ctx&: OutContext);
541 TmpInst.addOperand(Op: MCOperand::createExpr(Val: E));
542 }
543 TmpInst.addOperand(Op: MO);
544 MappedInst = TmpInst;
545 return;
546 }
547
548 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
549 case Hexagon::A2_tfrp: {
550 MCOperand &MO = MappedInst.getOperand(i: 1);
551 MCRegister High = RI->getSubReg(Reg: MO.getReg(), Idx: Hexagon::isub_hi);
552 MCRegister Low = RI->getSubReg(Reg: MO.getReg(), Idx: Hexagon::isub_lo);
553 MO.setReg(High);
554 // Add a new operand for the second register in the pair.
555 MappedInst.addOperand(Op: MCOperand::createReg(Reg: Low));
556 MappedInst.setOpcode(Hexagon::A2_combinew);
557 return;
558 }
559
560 case Hexagon::A2_tfrpt:
561 case Hexagon::A2_tfrpf: {
562 MCOperand &MO = MappedInst.getOperand(i: 2);
563 MCRegister High = RI->getSubReg(Reg: MO.getReg(), Idx: Hexagon::isub_hi);
564 MCRegister Low = RI->getSubReg(Reg: MO.getReg(), Idx: Hexagon::isub_lo);
565 MO.setReg(High);
566 // Add a new operand for the second register in the pair.
567 MappedInst.addOperand(Op: MCOperand::createReg(Reg: Low));
568 MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
569 ? Hexagon::C2_ccombinewt
570 : Hexagon::C2_ccombinewf);
571 return;
572 }
573
574 case Hexagon::A2_tfrptnew:
575 case Hexagon::A2_tfrpfnew: {
576 MCOperand &MO = MappedInst.getOperand(i: 2);
577 MCRegister High = RI->getSubReg(Reg: MO.getReg(), Idx: Hexagon::isub_hi);
578 MCRegister Low = RI->getSubReg(Reg: MO.getReg(), Idx: Hexagon::isub_lo);
579 MO.setReg(High);
580 // Add a new operand for the second register in the pair.
581 MappedInst.addOperand(Op: MCOperand::createReg(Reg: Low));
582 MappedInst.setOpcode(Inst.getOpcode() == Hexagon::A2_tfrptnew
583 ? Hexagon::C2_ccombinewnewt
584 : Hexagon::C2_ccombinewnewf);
585 return;
586 }
587
588 case Hexagon::M2_mpysmi: {
589 MCOperand &Imm = MappedInst.getOperand(i: 2);
590 MCExpr const *Expr = Imm.getExpr();
591 int64_t Value;
592 bool Success = Expr->evaluateAsAbsolute(Res&: Value);
593 assert(Success);
594 (void)Success;
595 if (Value < 0 && Value > -256) {
596 MappedInst.setOpcode(Hexagon::M2_mpysin);
597 Imm.setExpr(HexagonMCExpr::create(
598 Expr: MCUnaryExpr::createMinus(Expr, Ctx&: OutContext), Ctx&: OutContext));
599 } else
600 MappedInst.setOpcode(Hexagon::M2_mpysip);
601 return;
602 }
603
604 case Hexagon::A2_addsp: {
605 MCOperand &Rt = Inst.getOperand(i: 1);
606 assert(Rt.isReg() && "Expected register and none was found");
607 unsigned Reg = RI->getEncodingValue(Reg: Rt.getReg());
608 if (Reg & 1)
609 MappedInst.setOpcode(Hexagon::A2_addsph);
610 else
611 MappedInst.setOpcode(Hexagon::A2_addspl);
612 Rt.setReg(getHexagonRegisterPair(Reg: Rt.getReg(), RI));
613 return;
614 }
615
616 case Hexagon::V6_vd0: {
617 MCInst TmpInst;
618 assert(Inst.getOperand(0).isReg() &&
619 "Expected register and none was found");
620
621 TmpInst.setOpcode(Hexagon::V6_vxor);
622 TmpInst.addOperand(Op: Inst.getOperand(i: 0));
623 TmpInst.addOperand(Op: Inst.getOperand(i: 0));
624 TmpInst.addOperand(Op: Inst.getOperand(i: 0));
625 MappedInst = TmpInst;
626 return;
627 }
628
629 case Hexagon::V6_vdd0: {
630 MCInst TmpInst;
631 assert (Inst.getOperand(0).isReg() &&
632 "Expected register and none was found");
633
634 TmpInst.setOpcode(Hexagon::V6_vsubw_dv);
635 TmpInst.addOperand(Op: Inst.getOperand(i: 0));
636 TmpInst.addOperand(Op: Inst.getOperand(i: 0));
637 TmpInst.addOperand(Op: Inst.getOperand(i: 0));
638 MappedInst = TmpInst;
639 return;
640 }
641
642 case Hexagon::V6_vL32Ub_pi:
643 case Hexagon::V6_vL32b_cur_pi:
644 case Hexagon::V6_vL32b_nt_cur_pi:
645 case Hexagon::V6_vL32b_pi:
646 case Hexagon::V6_vL32b_nt_pi:
647 case Hexagon::V6_vL32b_nt_tmp_pi:
648 case Hexagon::V6_vL32b_tmp_pi:
649 MappedInst = ScaleVectorOffset(Inst, OpNo: 3, VectorSize, Ctx&: OutContext);
650 return;
651
652 case Hexagon::V6_vL32Ub_ai:
653 case Hexagon::V6_vL32b_ai:
654 case Hexagon::V6_vL32b_cur_ai:
655 case Hexagon::V6_vL32b_nt_ai:
656 case Hexagon::V6_vL32b_nt_cur_ai:
657 case Hexagon::V6_vL32b_nt_tmp_ai:
658 case Hexagon::V6_vL32b_tmp_ai:
659 MappedInst = ScaleVectorOffset(Inst, OpNo: 2, VectorSize, Ctx&: OutContext);
660 return;
661
662 case Hexagon::V6_vS32Ub_pi:
663 case Hexagon::V6_vS32b_new_pi:
664 case Hexagon::V6_vS32b_nt_new_pi:
665 case Hexagon::V6_vS32b_nt_pi:
666 case Hexagon::V6_vS32b_pi:
667 MappedInst = ScaleVectorOffset(Inst, OpNo: 2, VectorSize, Ctx&: OutContext);
668 return;
669
670 case Hexagon::V6_vS32Ub_ai:
671 case Hexagon::V6_vS32b_ai:
672 case Hexagon::V6_vS32b_new_ai:
673 case Hexagon::V6_vS32b_nt_ai:
674 case Hexagon::V6_vS32b_nt_new_ai:
675 MappedInst = ScaleVectorOffset(Inst, OpNo: 1, VectorSize, Ctx&: OutContext);
676 return;
677
678 case Hexagon::V6_vL32b_cur_npred_pi:
679 case Hexagon::V6_vL32b_cur_pred_pi:
680 case Hexagon::V6_vL32b_npred_pi:
681 case Hexagon::V6_vL32b_nt_cur_npred_pi:
682 case Hexagon::V6_vL32b_nt_cur_pred_pi:
683 case Hexagon::V6_vL32b_nt_npred_pi:
684 case Hexagon::V6_vL32b_nt_pred_pi:
685 case Hexagon::V6_vL32b_nt_tmp_npred_pi:
686 case Hexagon::V6_vL32b_nt_tmp_pred_pi:
687 case Hexagon::V6_vL32b_pred_pi:
688 case Hexagon::V6_vL32b_tmp_npred_pi:
689 case Hexagon::V6_vL32b_tmp_pred_pi:
690 MappedInst = ScaleVectorOffset(Inst, OpNo: 4, VectorSize, Ctx&: OutContext);
691 return;
692
693 case Hexagon::V6_vL32b_cur_npred_ai:
694 case Hexagon::V6_vL32b_cur_pred_ai:
695 case Hexagon::V6_vL32b_npred_ai:
696 case Hexagon::V6_vL32b_nt_cur_npred_ai:
697 case Hexagon::V6_vL32b_nt_cur_pred_ai:
698 case Hexagon::V6_vL32b_nt_npred_ai:
699 case Hexagon::V6_vL32b_nt_pred_ai:
700 case Hexagon::V6_vL32b_nt_tmp_npred_ai:
701 case Hexagon::V6_vL32b_nt_tmp_pred_ai:
702 case Hexagon::V6_vL32b_pred_ai:
703 case Hexagon::V6_vL32b_tmp_npred_ai:
704 case Hexagon::V6_vL32b_tmp_pred_ai:
705 MappedInst = ScaleVectorOffset(Inst, OpNo: 3, VectorSize, Ctx&: OutContext);
706 return;
707
708 case Hexagon::V6_vS32Ub_npred_pi:
709 case Hexagon::V6_vS32Ub_pred_pi:
710 case Hexagon::V6_vS32b_new_npred_pi:
711 case Hexagon::V6_vS32b_new_pred_pi:
712 case Hexagon::V6_vS32b_npred_pi:
713 case Hexagon::V6_vS32b_nqpred_pi:
714 case Hexagon::V6_vS32b_nt_new_npred_pi:
715 case Hexagon::V6_vS32b_nt_new_pred_pi:
716 case Hexagon::V6_vS32b_nt_npred_pi:
717 case Hexagon::V6_vS32b_nt_nqpred_pi:
718 case Hexagon::V6_vS32b_nt_pred_pi:
719 case Hexagon::V6_vS32b_nt_qpred_pi:
720 case Hexagon::V6_vS32b_pred_pi:
721 case Hexagon::V6_vS32b_qpred_pi:
722 MappedInst = ScaleVectorOffset(Inst, OpNo: 3, VectorSize, Ctx&: OutContext);
723 return;
724
725 case Hexagon::V6_vS32Ub_npred_ai:
726 case Hexagon::V6_vS32Ub_pred_ai:
727 case Hexagon::V6_vS32b_new_npred_ai:
728 case Hexagon::V6_vS32b_new_pred_ai:
729 case Hexagon::V6_vS32b_npred_ai:
730 case Hexagon::V6_vS32b_nqpred_ai:
731 case Hexagon::V6_vS32b_nt_new_npred_ai:
732 case Hexagon::V6_vS32b_nt_new_pred_ai:
733 case Hexagon::V6_vS32b_nt_npred_ai:
734 case Hexagon::V6_vS32b_nt_nqpred_ai:
735 case Hexagon::V6_vS32b_nt_pred_ai:
736 case Hexagon::V6_vS32b_nt_qpred_ai:
737 case Hexagon::V6_vS32b_pred_ai:
738 case Hexagon::V6_vS32b_qpred_ai:
739 MappedInst = ScaleVectorOffset(Inst, OpNo: 2, VectorSize, Ctx&: OutContext);
740 return;
741
742 // V65+
743 case Hexagon::V6_vS32b_srls_ai:
744 MappedInst = ScaleVectorOffset(Inst, OpNo: 1, VectorSize, Ctx&: OutContext);
745 return;
746
747 case Hexagon::V6_vS32b_srls_pi:
748 MappedInst = ScaleVectorOffset(Inst, OpNo: 2, VectorSize, Ctx&: OutContext);
749 return;
750 }
751}
752
753/// Print out a single Hexagon MI to the current output stream.
754void HexagonAsmPrinter::emitInstruction(const MachineInstr *MI) {
755 Hexagon_MC::verifyInstructionPredicates(Opcode: MI->getOpcode(),
756 Features: getSubtargetInfo().getFeatureBits());
757
758 MCInst MCB;
759 MCB.setOpcode(Hexagon::BUNDLE);
760 MCB.addOperand(Op: MCOperand::createImm(Val: 0));
761 const MCInstrInfo &MCII = *Subtarget->getInstrInfo();
762
763 if (MI->isBundle()) {
764 const MachineBasicBlock* MBB = MI->getParent();
765 MachineBasicBlock::const_instr_iterator MII = MI->getIterator();
766
767 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
768 if (!MII->isDebugInstr() && !MII->isImplicitDef())
769 HexagonLowerToMC(MCII, MI: &*MII, MCB, AP&: *this);
770 } else {
771 HexagonLowerToMC(MCII, MI, MCB, AP&: *this);
772 }
773
774 const MachineFunction &MF = *MI->getParent()->getParent();
775 const auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
776 if (MI->isBundle() && HII.getBundleNoShuf(MIB: *MI))
777 HexagonMCInstrInfo::setMemReorderDisabled(MCB);
778
779 MCContext &Ctx = OutStreamer->getContext();
780 bool Ok = HexagonMCInstrInfo::canonicalizePacket(MCII, STI: *Subtarget, Context&: Ctx,
781 MCB, Checker: nullptr);
782 assert(Ok); (void)Ok;
783 if (HexagonMCInstrInfo::bundleSize(MCI: MCB) == 0)
784 return;
785 OutStreamer->emitInstruction(Inst: MCB, STI: getSubtargetInfo());
786}
787
788void HexagonAsmPrinter::emitStartOfAsmFile(Module &M) {
789 if (M.getTargetTriple().isOSBinFormatELF())
790 emitAttributes();
791}
792
793void HexagonAsmPrinter::emitEndOfAsmFile(Module &M) {
794 HexagonTargetStreamer &HTS =
795 static_cast<HexagonTargetStreamer &>(*OutStreamer->getTargetStreamer());
796 if (M.getTargetTriple().isOSBinFormatELF())
797 HTS.finishAttributeSection();
798}
799
800void HexagonAsmPrinter::emitAttributes() {
801 HexagonTargetStreamer &HTS =
802 static_cast<HexagonTargetStreamer &>(*OutStreamer->getTargetStreamer());
803 HTS.emitTargetAttributes(STI: TM.getMCSubtargetInfo());
804}
805
806void HexagonAsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI,
807 bool Typed) {
808 auto &O = *OutStreamer;
809 MCSymbol *CurSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
810 O.emitLabel(Symbol: CurSled);
811
812 auto *Sym = MCSymbolRefExpr::create(
813 Symbol: OutContext.getOrCreateSymbol(Name: Typed ? "__xray_TypedEvent"
814 : "__xray_CustomEvent"),
815 Ctx&: OutContext);
816
817 // The sled structure:
818 // .Lxray_sled_N:
819 // { jump .Lend } -- disabled (patched to nop when enabled)
820 // <save args, move operands, call handler, restore args>
821 // .Lend:
822
823 MCSymbol *EndSled = OutContext.createTempSymbol();
824
825 // Packet 1: jump over the sled (disabled state).
826 MCInst *JumpInst = OutContext.createMCInst();
827 JumpInst->setOpcode(Hexagon::J2_jump);
828 JumpInst->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
829 Expr: MCSymbolRefExpr::create(Symbol: EndSled, Ctx&: OutContext), Ctx&: OutContext)));
830
831 MCInst JumpPacket;
832 JumpPacket.setOpcode(Hexagon::BUNDLE);
833 JumpPacket.addOperand(Op: MCOperand::createImm(Val: 0));
834 JumpPacket.addOperand(Op: MCOperand::createInst(Val: JumpInst));
835 EmitToStreamer(S&: O, Inst: JumpPacket);
836
837 // Packet 2: allocframe to save LR:FP.
838 MCInst *AllocInst = OutContext.createMCInst();
839 AllocInst->setOpcode(Hexagon::S2_allocframe);
840 AllocInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R29));
841 AllocInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R30));
842 AllocInst->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
843 Expr: MCConstantExpr::create(Value: 0, Ctx&: OutContext), Ctx&: OutContext)));
844
845 MCInst AllocPacket;
846 AllocPacket.setOpcode(Hexagon::BUNDLE);
847 AllocPacket.addOperand(Op: MCOperand::createImm(Val: 0));
848 AllocPacket.addOperand(Op: MCOperand::createInst(Val: AllocInst));
849 EmitToStreamer(S&: O, Inst: AllocPacket);
850
851 // Save argument registers and set up call arguments.
852 // Custom event: 2 operands (ptr, size) in MI operands 0,1 -> r0, r1
853 // Typed event: 3 operands (type, ptr, size) in MI operands 0,1,2 ->
854 // r0,r1,r2
855 unsigned NumArgs = Typed ? 3 : 2;
856
857 // Save the original argument registers onto the stack.
858 // Packet 3: Allocate space and save r0.
859 MCInst *SubSpInst = OutContext.createMCInst();
860 SubSpInst->setOpcode(Hexagon::A2_addi);
861 SubSpInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R29));
862 SubSpInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R29));
863 SubSpInst->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
864 Expr: MCConstantExpr::create(Value: -(int64_t)(NumArgs * 4), Ctx&: OutContext),
865 Ctx&: OutContext)));
866
867 MCInst SubSpPacket;
868 SubSpPacket.setOpcode(Hexagon::BUNDLE);
869 SubSpPacket.addOperand(Op: MCOperand::createImm(Val: 0));
870 SubSpPacket.addOperand(Op: MCOperand::createInst(Val: SubSpInst));
871 EmitToStreamer(S&: O, Inst: SubSpPacket);
872
873 // Save each argument register.
874 for (unsigned I = 0; I < NumArgs; ++I) {
875 MCInst *StoreInst = OutContext.createMCInst();
876 StoreInst->setOpcode(Hexagon::S2_storeri_io);
877 StoreInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R29));
878 StoreInst->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
879 Expr: MCConstantExpr::create(Value: I * 4, Ctx&: OutContext), Ctx&: OutContext)));
880 StoreInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R0 + I));
881
882 MCInst StorePacket;
883 StorePacket.setOpcode(Hexagon::BUNDLE);
884 StorePacket.addOperand(Op: MCOperand::createImm(Val: 0));
885 StorePacket.addOperand(Op: MCOperand::createInst(Val: StoreInst));
886 EmitToStreamer(S&: O, Inst: StorePacket);
887 }
888
889 // Move operands into argument registers (r0, r1, [r2]).
890 // The XRay intrinsic uses i64 for size (and type) parameters. On 32-bit
891 // Hexagon these are in DoubleRegs (register pairs). The runtime handler
892 // expects 32-bit arguments, so extract the low sub-register.
893 //
894 // NOTE: Moves are always emitted (even identity moves like r0 = r0) so that
895 // the sled has a fixed size. The runtime patching code relies on the sled
896 // being a known number of words to encode the correct jump offset for the
897 // disabled state.
898 //
899 // NOTE: When source registers alias destination registers in a conflicting
900 // order (e.g., src0 in r1 and src1 in r0), the sequential moves can produce
901 // incorrect results. This is the same limitation as AArch64's implementation
902 // and is unlikely in practice since the register allocator rarely produces
903 // such assignments for XRay event intrinsics.
904 const auto &HRI = *MF->getSubtarget<HexagonSubtarget>().getRegisterInfo();
905 for (unsigned I = 0; I < NumArgs; ++I) {
906 Register SrcReg = MI.getOperand(i: I).getReg();
907 if (Hexagon::DoubleRegsRegClass.contains(Reg: SrcReg))
908 SrcReg = HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::isub_lo);
909
910 MCInst *MovInst = OutContext.createMCInst();
911 MovInst->setOpcode(Hexagon::A2_tfr);
912 MovInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R0 + I));
913 MovInst->addOperand(Op: MCOperand::createReg(Reg: SrcReg));
914
915 MCInst MovPacket;
916 MovPacket.setOpcode(Hexagon::BUNDLE);
917 MovPacket.addOperand(Op: MCOperand::createImm(Val: 0));
918 MovPacket.addOperand(Op: MCOperand::createInst(Val: MovInst));
919 EmitToStreamer(S&: O, Inst: MovPacket);
920 }
921
922 // Call the handler.
923 MCInst *CallInst = OutContext.createMCInst();
924 CallInst->setOpcode(Hexagon::J2_call);
925 CallInst->addOperand(
926 Op: MCOperand::createExpr(Val: HexagonMCExpr::create(Expr: Sym, Ctx&: OutContext)));
927
928 MCInst CallPacket;
929 CallPacket.setOpcode(Hexagon::BUNDLE);
930 CallPacket.addOperand(Op: MCOperand::createImm(Val: 0));
931 CallPacket.addOperand(Op: MCOperand::createInst(Val: CallInst));
932 EmitToStreamer(S&: O, Inst: CallPacket);
933
934 // Restore argument registers.
935 for (unsigned I = 0; I < NumArgs; ++I) {
936 MCInst *LoadInst = OutContext.createMCInst();
937 LoadInst->setOpcode(Hexagon::L2_loadri_io);
938 LoadInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R0 + I));
939 LoadInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R29));
940 LoadInst->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
941 Expr: MCConstantExpr::create(Value: I * 4, Ctx&: OutContext), Ctx&: OutContext)));
942
943 MCInst LoadPacket;
944 LoadPacket.setOpcode(Hexagon::BUNDLE);
945 LoadPacket.addOperand(Op: MCOperand::createImm(Val: 0));
946 LoadPacket.addOperand(Op: MCOperand::createInst(Val: LoadInst));
947 EmitToStreamer(S&: O, Inst: LoadPacket);
948 }
949
950 // Deallocate saved argument space.
951 MCInst *AddSpInst = OutContext.createMCInst();
952 AddSpInst->setOpcode(Hexagon::A2_addi);
953 AddSpInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R29));
954 AddSpInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R29));
955 AddSpInst->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
956 Expr: MCConstantExpr::create(Value: NumArgs * 4, Ctx&: OutContext), Ctx&: OutContext)));
957
958 MCInst AddSpPacket;
959 AddSpPacket.setOpcode(Hexagon::BUNDLE);
960 AddSpPacket.addOperand(Op: MCOperand::createImm(Val: 0));
961 AddSpPacket.addOperand(Op: MCOperand::createInst(Val: AddSpInst));
962 EmitToStreamer(S&: O, Inst: AddSpPacket);
963
964 // Deallocframe to restore LR:FP.
965 MCInst *DeallocInst = OutContext.createMCInst();
966 DeallocInst->setOpcode(Hexagon::L2_deallocframe);
967 DeallocInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::D15));
968 DeallocInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R30));
969
970 MCInst DeallocPacket;
971 DeallocPacket.setOpcode(Hexagon::BUNDLE);
972 DeallocPacket.addOperand(Op: MCOperand::createImm(Val: 0));
973 DeallocPacket.addOperand(Op: MCOperand::createInst(Val: DeallocInst));
974 EmitToStreamer(S&: O, Inst: DeallocPacket);
975
976 OutStreamer->emitLabel(Symbol: EndSled);
977 recordSled(Sled: CurSled, MI,
978 Kind: Typed ? SledKind::TYPED_EVENT : SledKind::CUSTOM_EVENT, Version: 2);
979}
980
981void HexagonAsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) {
982 Register AddrReg = MI.getOperand(i: 0).getReg();
983 const int64_t Type = MI.getOperand(i: 1).getImm();
984 [[maybe_unused]] MachineBasicBlock::const_instr_iterator NextI =
985 std::next(x: MI.getIterator());
986 assert(NextI != MI.getParent()->instr_end() && NextI->isCall() &&
987 "KCFI_CHECK not followed by a call instruction");
988 assert(NextI->getOperand(0).getReg() == AddrReg &&
989 "KCFI_CHECK call target doesn't match call operand");
990
991 // Scratch registers for the compare. Default to R6/R7 (caller-saved,
992 // in GeneralSubRegs for potential compounding). If AddrReg conflicts,
993 // fall back through other caller-saved registers.
994 unsigned ScratchRegs[] = {Hexagon::R6, Hexagon::R7};
995 unsigned NextReg = Hexagon::R8;
996 for (auto &Reg : ScratchRegs) {
997 if (Reg != AddrReg)
998 continue;
999 if (NextReg == AddrReg)
1000 ++NextReg;
1001 Reg = NextReg++;
1002 }
1003 unsigned LoadReg = ScratchRegs[0];
1004 unsigned TypeReg = ScratchRegs[1];
1005 unsigned PredReg = Hexagon::P0;
1006
1007 // Adjust for patchable-function-prefix (nop padding before the function).
1008 int64_t PrefixNops = MI.getMF()->getFunction().getFnAttributeAsParsedInteger(
1009 Kind: "patchable-function-prefix");
1010 int64_t Offset = -(PrefixNops * 4 + 4);
1011
1012 // Emit the KCFI check sequence.
1013 //
1014 // Packet 1: load the type hash and materialize the expected hash together.
1015 // The load offset only leaves its field for an implausible
1016 // patchable-function-prefix, but extend it rather than truncate.
1017 // { r_load = memw(r_addr + #offset); r_type = ##expected_hash }
1018 MCInst *LoadInst = OutContext.createMCInst();
1019 LoadInst->setOpcode(Hexagon::L2_loadri_io);
1020 LoadInst->addOperand(Op: MCOperand::createReg(Reg: LoadReg));
1021 LoadInst->addOperand(Op: MCOperand::createReg(Reg: AddrReg));
1022 LoadInst->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
1023 Expr: MCConstantExpr::create(Value: Offset, Ctx&: OutContext), Ctx&: OutContext)));
1024
1025 MCInst *TypeInst = OutContext.createMCInst();
1026 TypeInst->setOpcode(Hexagon::A2_tfrsi);
1027 TypeInst->addOperand(Op: MCOperand::createReg(Reg: TypeReg));
1028 auto *TypeExpr = HexagonMCExpr::create(
1029 Expr: MCConstantExpr::create(Value: Type, Ctx&: OutContext), Ctx&: OutContext);
1030 HexagonMCInstrInfo::setMustExtend(Expr: *TypeExpr, Val: true);
1031 TypeInst->addOperand(Op: MCOperand::createExpr(Val: TypeExpr));
1032
1033 // setMustExtend() only records that an operand needs an extender; the
1034 // extender still has to be inserted, and slot assignment has to place it
1035 // ahead of what it extends. HexagonLowerToMC()/emitInstruction() do both
1036 // for the MachineInstr stream; packets built here get neither.
1037 const MCInstrInfo &MCII = *Subtarget->getInstrInfo();
1038
1039 // Slot assignment is required for correctness, not just density: an extender
1040 // encoded after its instruction is not a legal packet. Passing a checker
1041 // (rather than nullptr) is what makes the assert meaningful.
1042 auto EmitPacket = [&](MCInst &MCB) {
1043 HexagonMCChecker Checker(OutContext, MCII, *Subtarget, MCB,
1044 *OutContext.getRegisterInfo(),
1045 /*ReportErrors=*/false);
1046 [[maybe_unused]] bool Ok = HexagonMCInstrInfo::canonicalizePacket(
1047 MCII, STI: *Subtarget, Context&: OutContext, MCB, Checker: &Checker);
1048 assert(Ok && "KCFI packet failed MC canonicalization");
1049 EmitToStreamer(S&: *OutStreamer, Inst: MCB);
1050 };
1051
1052 MCInst LoadTypePacket;
1053 LoadTypePacket.setOpcode(Hexagon::BUNDLE);
1054 LoadTypePacket.addOperand(Op: MCOperand::createImm(Val: 0));
1055 HexagonMCInstrInfo::extendIfNeeded(Context&: OutContext, MCII, MCB&: LoadTypePacket,
1056 MCI: *LoadInst);
1057 LoadTypePacket.addOperand(Op: MCOperand::createInst(Val: LoadInst));
1058 HexagonMCInstrInfo::extendIfNeeded(Context&: OutContext, MCII, MCB&: LoadTypePacket,
1059 MCI: *TypeInst);
1060 LoadTypePacket.addOperand(Op: MCOperand::createInst(Val: TypeInst));
1061 EmitPacket(LoadTypePacket);
1062
1063 // Packet 3: Compare and branch if equal.
1064 // { p0 = cmp.eq(r_load, r_type); if (p0.new) jump:t .Lpass }
1065 MCSymbol *Pass = OutContext.createTempSymbol();
1066
1067 MCInst *CmpInst = OutContext.createMCInst();
1068 CmpInst->setOpcode(Hexagon::C2_cmpeq);
1069 CmpInst->addOperand(Op: MCOperand::createReg(Reg: PredReg));
1070 CmpInst->addOperand(Op: MCOperand::createReg(Reg: LoadReg));
1071 CmpInst->addOperand(Op: MCOperand::createReg(Reg: TypeReg));
1072
1073 MCInst *JumpInst = OutContext.createMCInst();
1074 JumpInst->setOpcode(Hexagon::J2_jumptnewpt);
1075 JumpInst->addOperand(Op: MCOperand::createReg(Reg: PredReg));
1076 JumpInst->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
1077 Expr: MCSymbolRefExpr::create(Symbol: Pass, Ctx&: OutContext), Ctx&: OutContext)));
1078
1079 MCInst CmpJmpPacket;
1080 CmpJmpPacket.setOpcode(Hexagon::BUNDLE);
1081 CmpJmpPacket.addOperand(Op: MCOperand::createImm(Val: 0));
1082 CmpJmpPacket.addOperand(Op: MCOperand::createInst(Val: CmpInst));
1083 CmpJmpPacket.addOperand(Op: MCOperand::createInst(Val: JumpInst));
1084 EmitPacket(CmpJmpPacket);
1085
1086 // Packet 4: Crash on mismatch via misaligned load.
1087 // Use the same mechanism as llvm.trap (PS_crash): a doubleword load from
1088 // a misaligned address is guaranteed to fault in all execution modes,
1089 // including kernel/monitor mode where trap0 may not generate a useful
1090 // exception.
1091 MCSymbol *TrapLabel = OutContext.createTempSymbol();
1092 OutStreamer->emitLabel(Symbol: TrapLabel);
1093
1094 MCInst *CrashInst = OutContext.createMCInst();
1095 CrashInst->setOpcode(Hexagon::PS_loadrdabs);
1096 CrashInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::D13));
1097 auto *CrashExpr = HexagonMCExpr::create(
1098 Expr: MCConstantExpr::create(Value: 0xBADC0FEE, Ctx&: OutContext), Ctx&: OutContext);
1099 HexagonMCInstrInfo::setMustExtend(Expr: *CrashExpr, Val: true);
1100 CrashInst->addOperand(Op: MCOperand::createExpr(Val: CrashExpr));
1101
1102 MCInst CrashPacket;
1103 CrashPacket.setOpcode(Hexagon::BUNDLE);
1104 CrashPacket.addOperand(Op: MCOperand::createImm(Val: 0));
1105 HexagonMCInstrInfo::extendIfNeeded(Context&: OutContext, MCII, MCB&: CrashPacket, MCI: *CrashInst);
1106 CrashPacket.addOperand(Op: MCOperand::createInst(Val: CrashInst));
1107 EmitPacket(CrashPacket);
1108
1109 emitKCFITrapEntry(MF: *MI.getMF(), Symbol: TrapLabel);
1110 OutStreamer->emitLabel(Symbol: Pass);
1111}
1112
1113void HexagonAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) {
1114 static const int8_t NoopsInSledCount = 6;
1115 // We want to emit the following pattern:
1116 //
1117 // .L_xray_sled_N:
1118 // <xray_sled_base>:
1119 // { jump .Ltmp0 }
1120 // { nop }
1121 // { nop }
1122 // { nop }
1123 // { nop }
1124 // { nop }
1125 // { nop }
1126 // .Ltmp0:
1127 //
1128 // We need the 6 nop words because at runtime, we'd be patching over the
1129 // full 7 words with the following pattern:
1130 //
1131 // <xray_sled_n>:
1132 // { allocframe(#0) }
1133 // { immext(#...) // upper 26-bits of func id
1134 // r7 = ##... // lower 6-bits of func id
1135 // immext(#...) // upper 26-bits of trampoline
1136 // r6 = ##... } // lower 6-bits of trampoline
1137 // { callr r6 }
1138 // { deallocframe }
1139 //
1140 // allocframe saves r31:30 (LR:FP) before the call, and deallocframe
1141 // restores them after the trampoline returns, ensuring the caller's
1142 // return address in r31 is preserved across the sled.
1143 //
1144 auto CurSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
1145 OutStreamer->emitLabel(Symbol: CurSled);
1146
1147 MCInst *SledJump = new (OutContext) MCInst();
1148 SledJump->setOpcode(Hexagon::J2_jump);
1149 auto PostSled = OutContext.createTempSymbol();
1150 SledJump->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
1151 Expr: MCSymbolRefExpr::create(Symbol: PostSled, Ctx&: OutContext), Ctx&: OutContext)));
1152
1153 // Emit "jump PostSled" instruction, which jumps over the nop series.
1154 MCInst SledJumpPacket;
1155 SledJumpPacket.setOpcode(Hexagon::BUNDLE);
1156 SledJumpPacket.addOperand(Op: MCOperand::createImm(Val: 0));
1157 SledJumpPacket.addOperand(Op: MCOperand::createInst(Val: SledJump));
1158
1159 EmitToStreamer(S&: *OutStreamer, Inst: SledJumpPacket);
1160
1161 // FIXME: this will emit individual packets, we should
1162 // special-case this and combine them into a single packet.
1163 emitNops(N: NoopsInSledCount);
1164
1165 OutStreamer->emitLabel(Symbol: PostSled);
1166 recordSled(Sled: CurSled, MI, Kind, Version: 2);
1167}
1168
1169void HexagonAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI) {
1170 EmitSled(MI, Kind: SledKind::FUNCTION_ENTER);
1171}
1172
1173void HexagonAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI) {
1174 EmitSled(MI, Kind: SledKind::FUNCTION_EXIT);
1175}
1176
1177void HexagonAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI) {
1178 EmitSled(MI, Kind: SledKind::TAIL_CALL);
1179}
1180
1181char HexagonAsmPrinter::ID = 0;
1182
1183INITIALIZE_PASS(HexagonAsmPrinter, "hexagon-asm-printer",
1184 "Hexagon Assembly Printer", false, false)
1185
1186extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
1187LLVMInitializeHexagonAsmPrinter() {
1188 RegisterAsmPrinter<HexagonAsmPrinter> X(getTheHexagonTarget());
1189}
1190