1//===- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ---===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to Hexagon assembly language. This printer is
11// the output mechanism used by `llc'.
12//
13//===----------------------------------------------------------------------===//
14
15#include "HexagonAsmPrinter.h"
16#include "HexagonInstrInfo.h"
17#include "HexagonRegisterInfo.h"
18#include "HexagonSubtarget.h"
19#include "MCTargetDesc/HexagonInstPrinter.h"
20#include "MCTargetDesc/HexagonMCChecker.h"
21#include "MCTargetDesc/HexagonMCExpr.h"
22#include "MCTargetDesc/HexagonMCInstrInfo.h"
23#include "MCTargetDesc/HexagonMCTargetDesc.h"
24#include "MCTargetDesc/HexagonTargetStreamer.h"
25#include "TargetInfo/HexagonTargetInfo.h"
26#include "llvm/ADT/StringExtras.h"
27#include "llvm/ADT/StringRef.h"
28#include "llvm/ADT/Twine.h"
29#include "llvm/BinaryFormat/ELF.h"
30#include "llvm/CodeGen/AsmPrinter.h"
31#include "llvm/CodeGen/MachineBasicBlock.h"
32#include "llvm/CodeGen/MachineFunction.h"
33#include "llvm/CodeGen/MachineInstr.h"
34#include "llvm/CodeGen/MachineOperand.h"
35#include "llvm/CodeGen/TargetRegisterInfo.h"
36#include "llvm/CodeGen/TargetSubtargetInfo.h"
37#include "llvm/MC/MCContext.h"
38#include "llvm/MC/MCDirectives.h"
39#include "llvm/MC/MCExpr.h"
40#include "llvm/MC/MCInst.h"
41#include "llvm/MC/MCRegisterInfo.h"
42#include "llvm/MC/MCSectionELF.h"
43#include "llvm/MC/MCStreamer.h"
44#include "llvm/MC/MCSymbol.h"
45#include "llvm/MC/TargetRegistry.h"
46#include "llvm/Support/Casting.h"
47#include "llvm/Support/Compiler.h"
48#include "llvm/Support/ErrorHandling.h"
49#include "llvm/Support/raw_ostream.h"
50#include "llvm/Target/TargetMachine.h"
51#include <cassert>
52#include <cstdint>
53#include <string>
54
55using namespace llvm;
56
57namespace llvm {
58
59void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
60 MCInst &MCB, HexagonAsmPrinter &AP);
61
62} // end namespace llvm
63
64#define DEBUG_TYPE "asm-printer"
65
66// Given a scalar register return its pair.
67inline static unsigned getHexagonRegisterPair(unsigned Reg,
68 const MCRegisterInfo *RI) {
69 assert(Hexagon::IntRegsRegClass.contains(Reg));
70 unsigned Pair = *RI->superregs(Reg).begin();
71 assert(Hexagon::DoubleRegsRegClass.contains(Pair));
72 return Pair;
73}
74
75void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
76 raw_ostream &O) {
77 const MachineOperand &MO = MI->getOperand(i: OpNo);
78
79 switch (MO.getType()) {
80 default:
81 llvm_unreachable ("<unknown operand type>");
82 case MachineOperand::MO_Register:
83 O << HexagonInstPrinter::getRegisterName(Reg: MO.getReg());
84 return;
85 case MachineOperand::MO_Immediate:
86 O << MO.getImm();
87 return;
88 case MachineOperand::MO_MachineBasicBlock:
89 MO.getMBB()->getSymbol()->print(OS&: O, MAI);
90 return;
91 case MachineOperand::MO_ConstantPoolIndex:
92 GetCPISymbol(CPID: MO.getIndex())->print(OS&: O, MAI);
93 return;
94 case MachineOperand::MO_GlobalAddress:
95 PrintSymbolOperand(MO, OS&: O);
96 return;
97 }
98}
99
100// isBlockOnlyReachableByFallthrough - We need to override this since the
101// default AsmPrinter does not print labels for any basic block that
102// is only reachable by a fall through. That works for all cases except
103// for the case in which the basic block is reachable by a fall through but
104// through an indirect from a jump table. In this case, the jump table
105// will contain a label not defined by AsmPrinter.
106bool HexagonAsmPrinter::isBlockOnlyReachableByFallthrough(
107 const MachineBasicBlock *MBB) const {
108 if (MBB->hasAddressTaken())
109 return false;
110 return AsmPrinter::isBlockOnlyReachableByFallthrough(MBB);
111}
112
113/// PrintAsmOperand - Print out an operand for an inline asm expression.
114bool HexagonAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
115 const char *ExtraCode,
116 raw_ostream &OS) {
117 // Does this asm operand have a single letter operand modifier?
118 if (ExtraCode && ExtraCode[0]) {
119 if (ExtraCode[1] != 0)
120 return true; // Unknown modifier.
121
122 switch (ExtraCode[0]) {
123 default:
124 // See if this is a generic print operand
125 return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
126 case 'L':
127 case 'H': { // The highest-numbered register of a pair.
128 const MachineOperand &MO = MI->getOperand(i: OpNo);
129 const MachineFunction &MF = *MI->getParent()->getParent();
130 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
131 if (!MO.isReg())
132 return true;
133 Register RegNumber = MO.getReg();
134 // This should be an assert in the frontend.
135 if (Hexagon::DoubleRegsRegClass.contains(Reg: RegNumber))
136 RegNumber = TRI->getSubReg(Reg: RegNumber, Idx: ExtraCode[0] == 'L' ?
137 Hexagon::isub_lo :
138 Hexagon::isub_hi);
139 OS << HexagonInstPrinter::getRegisterName(Reg: RegNumber);
140 return false;
141 }
142 case 'I':
143 // Write 'i' if an integer constant, otherwise nothing. Used to print
144 // addi vs add, etc.
145 if (MI->getOperand(i: OpNo).isImm())
146 OS << "i";
147 return false;
148 }
149 }
150
151 printOperand(MI, OpNo, O&: OS);
152 return false;
153}
154
155bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
156 unsigned OpNo,
157 const char *ExtraCode,
158 raw_ostream &O) {
159 if (ExtraCode && ExtraCode[0])
160 return true; // Unknown modifier.
161
162 const MachineOperand &Base = MI->getOperand(i: OpNo);
163 const MachineOperand &Offset = MI->getOperand(i: OpNo+1);
164
165 if (Base.isReg())
166 printOperand(MI, OpNo, O);
167 else
168 llvm_unreachable("Unimplemented");
169
170 if (Offset.isImm()) {
171 if (Offset.getImm())
172 O << "+#" << Offset.getImm();
173 } else {
174 llvm_unreachable("Unimplemented");
175 }
176
177 return false;
178}
179
180static MCSymbol *smallData(AsmPrinter &AP, const MachineInstr &MI,
181 MCStreamer &OutStreamer, const MCOperand &Imm,
182 int AlignSize, const MCSubtargetInfo& STI) {
183 MCSymbol *Sym;
184 int64_t Value;
185 if (Imm.getExpr()->evaluateAsAbsolute(Res&: Value)) {
186 StringRef sectionPrefix;
187 std::string ImmString;
188 StringRef Name;
189 if (AlignSize == 8) {
190 Name = ".CONST_0000000000000000";
191 sectionPrefix = ".gnu.linkonce.l8";
192 ImmString = utohexstr(X: Value);
193 } else {
194 Name = ".CONST_00000000";
195 sectionPrefix = ".gnu.linkonce.l4";
196 ImmString = utohexstr(X: static_cast<uint32_t>(Value));
197 }
198
199 std::string symbolName = // Yes, leading zeros are kept.
200 Name.drop_back(N: ImmString.size()).str() + ImmString;
201 std::string sectionName = sectionPrefix.str() + symbolName;
202
203 MCSectionELF *Section = OutStreamer.getContext().getELFSection(
204 Section: sectionName, Type: ELF::SHT_PROGBITS, Flags: ELF::SHF_WRITE | ELF::SHF_ALLOC);
205 OutStreamer.switchSection(Section);
206
207 Sym = AP.OutContext.getOrCreateSymbol(Name: Twine(symbolName));
208 if (Sym->isUndefined()) {
209 OutStreamer.emitLabel(Symbol: Sym);
210 OutStreamer.emitSymbolAttribute(Symbol: Sym, Attribute: MCSA_Global);
211 OutStreamer.emitIntValue(Value, Size: AlignSize);
212 OutStreamer.emitCodeAlignment(Alignment: Align(AlignSize), STI);
213 }
214 } else {
215 assert(Imm.isExpr() && "Expected expression and found none");
216 const MachineOperand &MO = MI.getOperand(i: 1);
217 assert(MO.isGlobal() || MO.isCPI() || MO.isJTI());
218 MCSymbol *MOSymbol = nullptr;
219 if (MO.isGlobal())
220 MOSymbol = AP.getSymbol(GV: MO.getGlobal());
221 else if (MO.isCPI())
222 MOSymbol = AP.GetCPISymbol(CPID: MO.getIndex());
223 else if (MO.isJTI())
224 MOSymbol = AP.GetJTISymbol(JTID: MO.getIndex());
225 else
226 llvm_unreachable("Unknown operand type!");
227
228 StringRef SymbolName = MOSymbol->getName();
229 std::string LitaName = ".CONST_" + SymbolName.str();
230
231 MCSectionELF *Section = OutStreamer.getContext().getELFSection(
232 Section: ".lita", Type: ELF::SHT_PROGBITS, Flags: ELF::SHF_WRITE | ELF::SHF_ALLOC);
233
234 OutStreamer.switchSection(Section);
235 Sym = AP.OutContext.getOrCreateSymbol(Name: Twine(LitaName));
236 if (Sym->isUndefined()) {
237 OutStreamer.emitLabel(Symbol: Sym);
238 OutStreamer.emitSymbolAttribute(Symbol: Sym, Attribute: MCSA_Local);
239 OutStreamer.emitValue(Value: Imm.getExpr(), Size: AlignSize);
240 OutStreamer.emitCodeAlignment(Alignment: Align(AlignSize), STI);
241 }
242 }
243 return Sym;
244}
245
246static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo,
247 unsigned VectorSize, MCContext &Ctx) {
248 MCInst T;
249 T.setOpcode(Inst.getOpcode());
250 for (unsigned i = 0, n = Inst.getNumOperands(); i != n; ++i) {
251 if (i != OpNo) {
252 T.addOperand(Op: Inst.getOperand(i));
253 continue;
254 }
255 MCOperand &ImmOp = Inst.getOperand(i);
256 const auto *HE = static_cast<const HexagonMCExpr*>(ImmOp.getExpr());
257 int32_t V = cast<MCConstantExpr>(Val: HE->getExpr())->getValue();
258 auto *NewCE = MCConstantExpr::create(Value: V / int32_t(VectorSize), Ctx);
259 auto *NewHE = HexagonMCExpr::create(Expr: NewCE, Ctx);
260 T.addOperand(Op: MCOperand::createExpr(Val: NewHE));
261 }
262 return T;
263}
264
265void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
266 const MachineInstr &MI) {
267 MCInst &MappedInst = static_cast <MCInst &>(Inst);
268 const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo();
269 const MachineFunction &MF = *MI.getParent()->getParent();
270 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
271 unsigned VectorSize = HRI.getRegSizeInBits(RC: Hexagon::HvxVRRegClass) / 8;
272
273 switch (Inst.getOpcode()) {
274 default:
275 return;
276
277 case Hexagon::A2_iconst: {
278 Inst.setOpcode(Hexagon::A2_addi);
279 MCOperand Reg = Inst.getOperand(i: 0);
280 MCOperand S16 = Inst.getOperand(i: 1);
281 HexagonMCInstrInfo::setMustNotExtend(Expr: *S16.getExpr());
282 HexagonMCInstrInfo::setS27_2_reloc(Expr: *S16.getExpr());
283 Inst.clear();
284 Inst.addOperand(Op: Reg);
285 Inst.addOperand(Op: MCOperand::createReg(Reg: Hexagon::R0));
286 Inst.addOperand(Op: S16);
287 break;
288 }
289
290 case Hexagon::A2_tfrf: {
291 const MCConstantExpr *Zero = MCConstantExpr::create(Value: 0, Ctx&: OutContext);
292 Inst.setOpcode(Hexagon::A2_paddif);
293 Inst.addOperand(Op: MCOperand::createExpr(Val: Zero));
294 break;
295 }
296
297 case Hexagon::A2_tfrt: {
298 const MCConstantExpr *Zero = MCConstantExpr::create(Value: 0, Ctx&: OutContext);
299 Inst.setOpcode(Hexagon::A2_paddit);
300 Inst.addOperand(Op: MCOperand::createExpr(Val: Zero));
301 break;
302 }
303
304 case Hexagon::A2_tfrfnew: {
305 const MCConstantExpr *Zero = MCConstantExpr::create(Value: 0, Ctx&: OutContext);
306 Inst.setOpcode(Hexagon::A2_paddifnew);
307 Inst.addOperand(Op: MCOperand::createExpr(Val: Zero));
308 break;
309 }
310
311 case Hexagon::A2_tfrtnew: {
312 const MCConstantExpr *Zero = MCConstantExpr::create(Value: 0, Ctx&: OutContext);
313 Inst.setOpcode(Hexagon::A2_padditnew);
314 Inst.addOperand(Op: MCOperand::createExpr(Val: Zero));
315 break;
316 }
317
318 case Hexagon::A2_zxtb: {
319 const MCConstantExpr *C255 = MCConstantExpr::create(Value: 255, Ctx&: OutContext);
320 Inst.setOpcode(Hexagon::A2_andir);
321 Inst.addOperand(Op: MCOperand::createExpr(Val: C255));
322 break;
323 }
324
325 // "$dst = CONST64(#$src1)",
326 case Hexagon::CONST64:
327 if (!OutStreamer->hasRawTextSupport()) {
328 const MCOperand &Imm = MappedInst.getOperand(i: 1);
329 MCSectionSubPair Current = OutStreamer->getCurrentSection();
330
331 MCSymbol *Sym =
332 smallData(AP&: *this, MI, OutStreamer&: *OutStreamer, Imm, AlignSize: 8, STI: getSubtargetInfo());
333
334 OutStreamer->switchSection(Section: Current.first, Subsec: Current.second);
335 MCInst TmpInst;
336 MCOperand &Reg = MappedInst.getOperand(i: 0);
337 TmpInst.setOpcode(Hexagon::L2_loadrdgp);
338 TmpInst.addOperand(Op: Reg);
339 TmpInst.addOperand(Op: MCOperand::createExpr(
340 Val: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext)));
341 MappedInst = TmpInst;
342
343 }
344 break;
345 case Hexagon::CONST32:
346 if (!OutStreamer->hasRawTextSupport()) {
347 MCOperand &Imm = MappedInst.getOperand(i: 1);
348 MCSectionSubPair Current = OutStreamer->getCurrentSection();
349 MCSymbol *Sym =
350 smallData(AP&: *this, MI, OutStreamer&: *OutStreamer, Imm, AlignSize: 4, STI: getSubtargetInfo());
351 OutStreamer->switchSection(Section: Current.first, Subsec: Current.second);
352 MCInst TmpInst;
353 MCOperand &Reg = MappedInst.getOperand(i: 0);
354 TmpInst.setOpcode(Hexagon::L2_loadrigp);
355 TmpInst.addOperand(Op: Reg);
356 TmpInst.addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
357 Expr: MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext), Ctx&: OutContext)));
358 MappedInst = TmpInst;
359 }
360 break;
361
362 // C2_pxfer_map maps to C2_or instruction. Though, it's possible to use
363 // C2_or during instruction selection itself but it results
364 // into suboptimal code.
365 case Hexagon::C2_pxfer_map: {
366 MCOperand &Ps = Inst.getOperand(i: 1);
367 MappedInst.setOpcode(Hexagon::C2_or);
368 MappedInst.addOperand(Op: Ps);
369 return;
370 }
371
372 // Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo
373 // The insn is mapped from the 4 operand to the 3 operand raw form taking
374 // 3 register pairs.
375 case Hexagon::M2_vrcmpys_acc_s1: {
376 MCOperand &Rt = Inst.getOperand(i: 3);
377 assert(Rt.isReg() && "Expected register and none was found");
378 unsigned Reg = RI->getEncodingValue(Reg: Rt.getReg());
379 if (Reg & 1)
380 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
381 else
382 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
383 Rt.setReg(getHexagonRegisterPair(Reg: Rt.getReg(), RI));
384 return;
385 }
386 case Hexagon::M2_vrcmpys_s1: {
387 MCOperand &Rt = Inst.getOperand(i: 2);
388 assert(Rt.isReg() && "Expected register and none was found");
389 unsigned Reg = RI->getEncodingValue(Reg: Rt.getReg());
390 if (Reg & 1)
391 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
392 else
393 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
394 Rt.setReg(getHexagonRegisterPair(Reg: Rt.getReg(), RI));
395 return;
396 }
397
398 case Hexagon::M2_vrcmpys_s1rp: {
399 MCOperand &Rt = Inst.getOperand(i: 2);
400 assert(Rt.isReg() && "Expected register and none was found");
401 unsigned Reg = RI->getEncodingValue(Reg: Rt.getReg());
402 if (Reg & 1)
403 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
404 else
405 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
406 Rt.setReg(getHexagonRegisterPair(Reg: Rt.getReg(), RI));
407 return;
408 }
409
410 case Hexagon::A4_boundscheck: {
411 MCOperand &Rs = Inst.getOperand(i: 1);
412 assert(Rs.isReg() && "Expected register and none was found");
413 unsigned Reg = RI->getEncodingValue(Reg: Rs.getReg());
414 if (Reg & 1) // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
415 MappedInst.setOpcode(Hexagon::A4_boundscheck_hi);
416 else // raw:lo
417 MappedInst.setOpcode(Hexagon::A4_boundscheck_lo);
418 Rs.setReg(getHexagonRegisterPair(Reg: Rs.getReg(), RI));
419 return;
420 }
421
422 case Hexagon::PS_call_nr:
423 Inst.setOpcode(Hexagon::J2_call);
424 break;
425
426 case Hexagon::PS_readcr:
427 Inst.setOpcode(Hexagon::A2_tfrcrr);
428 break;
429
430 case Hexagon::PS_readcr64:
431 Inst.setOpcode(Hexagon::A4_tfrcpp);
432 break;
433
434 case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
435 MCOperand &MO = MappedInst.getOperand(i: 2);
436 int64_t Imm;
437 MCExpr const *Expr = MO.getExpr();
438 bool Success = Expr->evaluateAsAbsolute(Res&: Imm);
439 assert(Success && "Expected immediate and none was found");
440 (void)Success;
441 MCInst TmpInst;
442 if (Imm == 0) {
443 TmpInst.setOpcode(Hexagon::S2_vsathub);
444 TmpInst.addOperand(Op: MappedInst.getOperand(i: 0));
445 TmpInst.addOperand(Op: MappedInst.getOperand(i: 1));
446 MappedInst = TmpInst;
447 return;
448 }
449 TmpInst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
450 TmpInst.addOperand(Op: MappedInst.getOperand(i: 0));
451 TmpInst.addOperand(Op: MappedInst.getOperand(i: 1));
452 const MCExpr *One = MCConstantExpr::create(Value: 1, Ctx&: OutContext);
453 const MCExpr *Sub = MCBinaryExpr::createSub(LHS: Expr, RHS: One, Ctx&: OutContext);
454 TmpInst.addOperand(
455 Op: MCOperand::createExpr(Val: HexagonMCExpr::create(Expr: Sub, Ctx&: OutContext)));
456 MappedInst = TmpInst;
457 return;
458 }
459
460 case Hexagon::S5_vasrhrnd_goodsyntax:
461 case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
462 MCOperand &MO2 = MappedInst.getOperand(i: 2);
463 MCExpr const *Expr = MO2.getExpr();
464 int64_t Imm;
465 bool Success = Expr->evaluateAsAbsolute(Res&: Imm);
466 assert(Success && "Expected immediate and none was found");
467 (void)Success;
468 MCInst TmpInst;
469 if (Imm == 0) {
470 TmpInst.setOpcode(Hexagon::A2_combinew);
471 TmpInst.addOperand(Op: MappedInst.getOperand(i: 0));
472 MCOperand &MO1 = MappedInst.getOperand(i: 1);
473 MCRegister High = RI->getSubReg(Reg: MO1.getReg(), Idx: Hexagon::isub_hi);
474 MCRegister Low = RI->getSubReg(Reg: MO1.getReg(), Idx: Hexagon::isub_lo);
475 // Add a new operand for the second register in the pair.
476 TmpInst.addOperand(Op: MCOperand::createReg(Reg: High));
477 TmpInst.addOperand(Op: MCOperand::createReg(Reg: Low));
478 MappedInst = TmpInst;
479 return;
480 }
481
482 if (Inst.getOpcode() == Hexagon::S2_asr_i_p_rnd_goodsyntax)
483 TmpInst.setOpcode(Hexagon::S2_asr_i_p_rnd);
484 else
485 TmpInst.setOpcode(Hexagon::S5_vasrhrnd);
486 TmpInst.addOperand(Op: MappedInst.getOperand(i: 0));
487 TmpInst.addOperand(Op: MappedInst.getOperand(i: 1));
488 const MCExpr *One = MCConstantExpr::create(Value: 1, Ctx&: OutContext);
489 const MCExpr *Sub = MCBinaryExpr::createSub(LHS: Expr, RHS: One, Ctx&: OutContext);
490 TmpInst.addOperand(
491 Op: MCOperand::createExpr(Val: HexagonMCExpr::create(Expr: Sub, Ctx&: OutContext)));
492 MappedInst = TmpInst;
493 return;
494 }
495
496 // if ("#u5==0") Assembler mapped to: "Rd=Rs"; else Rd=asr(Rs,#u5-1):rnd
497 case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
498 MCOperand &MO = Inst.getOperand(i: 2);
499 MCExpr const *Expr = MO.getExpr();
500 int64_t Imm;
501 bool Success = Expr->evaluateAsAbsolute(Res&: Imm);
502 assert(Success && "Expected immediate and none was found");
503 (void)Success;
504 MCInst TmpInst;
505 if (Imm == 0) {
506 TmpInst.setOpcode(Hexagon::A2_tfr);
507 TmpInst.addOperand(Op: MappedInst.getOperand(i: 0));
508 TmpInst.addOperand(Op: MappedInst.getOperand(i: 1));
509 MappedInst = TmpInst;
510 return;
511 }
512 TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
513 TmpInst.addOperand(Op: MappedInst.getOperand(i: 0));
514 TmpInst.addOperand(Op: MappedInst.getOperand(i: 1));
515 const MCExpr *One = MCConstantExpr::create(Value: 1, Ctx&: OutContext);
516 const MCExpr *Sub = MCBinaryExpr::createSub(LHS: Expr, RHS: One, Ctx&: OutContext);
517 TmpInst.addOperand(
518 Op: MCOperand::createExpr(Val: HexagonMCExpr::create(Expr: Sub, Ctx&: OutContext)));
519 MappedInst = TmpInst;
520 return;
521 }
522
523 // Translate a "$Rdd = #imm" to "$Rdd = combine(#[-1,0], #imm)"
524 case Hexagon::A2_tfrpi: {
525 MCInst TmpInst;
526 MCOperand &Rdd = MappedInst.getOperand(i: 0);
527 MCOperand &MO = MappedInst.getOperand(i: 1);
528
529 TmpInst.setOpcode(Hexagon::A2_combineii);
530 TmpInst.addOperand(Op: Rdd);
531 int64_t Imm;
532 bool Success = MO.getExpr()->evaluateAsAbsolute(Res&: Imm);
533 if (Success && Imm < 0) {
534 const MCExpr *MOne = MCConstantExpr::create(Value: -1, Ctx&: OutContext);
535 const HexagonMCExpr *E = HexagonMCExpr::create(Expr: MOne, Ctx&: OutContext);
536 TmpInst.addOperand(Op: MCOperand::createExpr(Val: E));
537 } else {
538 const MCExpr *Zero = MCConstantExpr::create(Value: 0, Ctx&: OutContext);
539 const HexagonMCExpr *E = HexagonMCExpr::create(Expr: Zero, Ctx&: OutContext);
540 TmpInst.addOperand(Op: MCOperand::createExpr(Val: E));
541 }
542 TmpInst.addOperand(Op: MO);
543 MappedInst = TmpInst;
544 return;
545 }
546
547 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
548 case Hexagon::A2_tfrp: {
549 MCOperand &MO = MappedInst.getOperand(i: 1);
550 MCRegister High = RI->getSubReg(Reg: MO.getReg(), Idx: Hexagon::isub_hi);
551 MCRegister Low = RI->getSubReg(Reg: MO.getReg(), Idx: Hexagon::isub_lo);
552 MO.setReg(High);
553 // Add a new operand for the second register in the pair.
554 MappedInst.addOperand(Op: MCOperand::createReg(Reg: Low));
555 MappedInst.setOpcode(Hexagon::A2_combinew);
556 return;
557 }
558
559 case Hexagon::A2_tfrpt:
560 case Hexagon::A2_tfrpf: {
561 MCOperand &MO = MappedInst.getOperand(i: 2);
562 MCRegister High = RI->getSubReg(Reg: MO.getReg(), Idx: Hexagon::isub_hi);
563 MCRegister Low = RI->getSubReg(Reg: MO.getReg(), Idx: Hexagon::isub_lo);
564 MO.setReg(High);
565 // Add a new operand for the second register in the pair.
566 MappedInst.addOperand(Op: MCOperand::createReg(Reg: Low));
567 MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
568 ? Hexagon::C2_ccombinewt
569 : Hexagon::C2_ccombinewf);
570 return;
571 }
572
573 case Hexagon::A2_tfrptnew:
574 case Hexagon::A2_tfrpfnew: {
575 MCOperand &MO = MappedInst.getOperand(i: 2);
576 MCRegister High = RI->getSubReg(Reg: MO.getReg(), Idx: Hexagon::isub_hi);
577 MCRegister Low = RI->getSubReg(Reg: MO.getReg(), Idx: Hexagon::isub_lo);
578 MO.setReg(High);
579 // Add a new operand for the second register in the pair.
580 MappedInst.addOperand(Op: MCOperand::createReg(Reg: Low));
581 MappedInst.setOpcode(Inst.getOpcode() == Hexagon::A2_tfrptnew
582 ? Hexagon::C2_ccombinewnewt
583 : Hexagon::C2_ccombinewnewf);
584 return;
585 }
586
587 case Hexagon::M2_mpysmi: {
588 MCOperand &Imm = MappedInst.getOperand(i: 2);
589 MCExpr const *Expr = Imm.getExpr();
590 int64_t Value;
591 bool Success = Expr->evaluateAsAbsolute(Res&: Value);
592 assert(Success);
593 (void)Success;
594 if (Value < 0 && Value > -256) {
595 MappedInst.setOpcode(Hexagon::M2_mpysin);
596 Imm.setExpr(HexagonMCExpr::create(
597 Expr: MCUnaryExpr::createMinus(Expr, Ctx&: OutContext), Ctx&: OutContext));
598 } else
599 MappedInst.setOpcode(Hexagon::M2_mpysip);
600 return;
601 }
602
603 case Hexagon::A2_addsp: {
604 MCOperand &Rt = Inst.getOperand(i: 1);
605 assert(Rt.isReg() && "Expected register and none was found");
606 unsigned Reg = RI->getEncodingValue(Reg: Rt.getReg());
607 if (Reg & 1)
608 MappedInst.setOpcode(Hexagon::A2_addsph);
609 else
610 MappedInst.setOpcode(Hexagon::A2_addspl);
611 Rt.setReg(getHexagonRegisterPair(Reg: Rt.getReg(), RI));
612 return;
613 }
614
615 case Hexagon::V6_vd0: {
616 MCInst TmpInst;
617 assert(Inst.getOperand(0).isReg() &&
618 "Expected register and none was found");
619
620 TmpInst.setOpcode(Hexagon::V6_vxor);
621 TmpInst.addOperand(Op: Inst.getOperand(i: 0));
622 TmpInst.addOperand(Op: Inst.getOperand(i: 0));
623 TmpInst.addOperand(Op: Inst.getOperand(i: 0));
624 MappedInst = TmpInst;
625 return;
626 }
627
628 case Hexagon::V6_vdd0: {
629 MCInst TmpInst;
630 assert (Inst.getOperand(0).isReg() &&
631 "Expected register and none was found");
632
633 TmpInst.setOpcode(Hexagon::V6_vsubw_dv);
634 TmpInst.addOperand(Op: Inst.getOperand(i: 0));
635 TmpInst.addOperand(Op: Inst.getOperand(i: 0));
636 TmpInst.addOperand(Op: Inst.getOperand(i: 0));
637 MappedInst = TmpInst;
638 return;
639 }
640
641 case Hexagon::V6_vL32Ub_pi:
642 case Hexagon::V6_vL32b_cur_pi:
643 case Hexagon::V6_vL32b_nt_cur_pi:
644 case Hexagon::V6_vL32b_pi:
645 case Hexagon::V6_vL32b_nt_pi:
646 case Hexagon::V6_vL32b_nt_tmp_pi:
647 case Hexagon::V6_vL32b_tmp_pi:
648 MappedInst = ScaleVectorOffset(Inst, OpNo: 3, VectorSize, Ctx&: OutContext);
649 return;
650
651 case Hexagon::V6_vL32Ub_ai:
652 case Hexagon::V6_vL32b_ai:
653 case Hexagon::V6_vL32b_cur_ai:
654 case Hexagon::V6_vL32b_nt_ai:
655 case Hexagon::V6_vL32b_nt_cur_ai:
656 case Hexagon::V6_vL32b_nt_tmp_ai:
657 case Hexagon::V6_vL32b_tmp_ai:
658 MappedInst = ScaleVectorOffset(Inst, OpNo: 2, VectorSize, Ctx&: OutContext);
659 return;
660
661 case Hexagon::V6_vS32Ub_pi:
662 case Hexagon::V6_vS32b_new_pi:
663 case Hexagon::V6_vS32b_nt_new_pi:
664 case Hexagon::V6_vS32b_nt_pi:
665 case Hexagon::V6_vS32b_pi:
666 MappedInst = ScaleVectorOffset(Inst, OpNo: 2, VectorSize, Ctx&: OutContext);
667 return;
668
669 case Hexagon::V6_vS32Ub_ai:
670 case Hexagon::V6_vS32b_ai:
671 case Hexagon::V6_vS32b_new_ai:
672 case Hexagon::V6_vS32b_nt_ai:
673 case Hexagon::V6_vS32b_nt_new_ai:
674 MappedInst = ScaleVectorOffset(Inst, OpNo: 1, VectorSize, Ctx&: OutContext);
675 return;
676
677 case Hexagon::V6_vL32b_cur_npred_pi:
678 case Hexagon::V6_vL32b_cur_pred_pi:
679 case Hexagon::V6_vL32b_npred_pi:
680 case Hexagon::V6_vL32b_nt_cur_npred_pi:
681 case Hexagon::V6_vL32b_nt_cur_pred_pi:
682 case Hexagon::V6_vL32b_nt_npred_pi:
683 case Hexagon::V6_vL32b_nt_pred_pi:
684 case Hexagon::V6_vL32b_nt_tmp_npred_pi:
685 case Hexagon::V6_vL32b_nt_tmp_pred_pi:
686 case Hexagon::V6_vL32b_pred_pi:
687 case Hexagon::V6_vL32b_tmp_npred_pi:
688 case Hexagon::V6_vL32b_tmp_pred_pi:
689 MappedInst = ScaleVectorOffset(Inst, OpNo: 4, VectorSize, Ctx&: OutContext);
690 return;
691
692 case Hexagon::V6_vL32b_cur_npred_ai:
693 case Hexagon::V6_vL32b_cur_pred_ai:
694 case Hexagon::V6_vL32b_npred_ai:
695 case Hexagon::V6_vL32b_nt_cur_npred_ai:
696 case Hexagon::V6_vL32b_nt_cur_pred_ai:
697 case Hexagon::V6_vL32b_nt_npred_ai:
698 case Hexagon::V6_vL32b_nt_pred_ai:
699 case Hexagon::V6_vL32b_nt_tmp_npred_ai:
700 case Hexagon::V6_vL32b_nt_tmp_pred_ai:
701 case Hexagon::V6_vL32b_pred_ai:
702 case Hexagon::V6_vL32b_tmp_npred_ai:
703 case Hexagon::V6_vL32b_tmp_pred_ai:
704 MappedInst = ScaleVectorOffset(Inst, OpNo: 3, VectorSize, Ctx&: OutContext);
705 return;
706
707 case Hexagon::V6_vS32Ub_npred_pi:
708 case Hexagon::V6_vS32Ub_pred_pi:
709 case Hexagon::V6_vS32b_new_npred_pi:
710 case Hexagon::V6_vS32b_new_pred_pi:
711 case Hexagon::V6_vS32b_npred_pi:
712 case Hexagon::V6_vS32b_nqpred_pi:
713 case Hexagon::V6_vS32b_nt_new_npred_pi:
714 case Hexagon::V6_vS32b_nt_new_pred_pi:
715 case Hexagon::V6_vS32b_nt_npred_pi:
716 case Hexagon::V6_vS32b_nt_nqpred_pi:
717 case Hexagon::V6_vS32b_nt_pred_pi:
718 case Hexagon::V6_vS32b_nt_qpred_pi:
719 case Hexagon::V6_vS32b_pred_pi:
720 case Hexagon::V6_vS32b_qpred_pi:
721 MappedInst = ScaleVectorOffset(Inst, OpNo: 3, VectorSize, Ctx&: OutContext);
722 return;
723
724 case Hexagon::V6_vS32Ub_npred_ai:
725 case Hexagon::V6_vS32Ub_pred_ai:
726 case Hexagon::V6_vS32b_new_npred_ai:
727 case Hexagon::V6_vS32b_new_pred_ai:
728 case Hexagon::V6_vS32b_npred_ai:
729 case Hexagon::V6_vS32b_nqpred_ai:
730 case Hexagon::V6_vS32b_nt_new_npred_ai:
731 case Hexagon::V6_vS32b_nt_new_pred_ai:
732 case Hexagon::V6_vS32b_nt_npred_ai:
733 case Hexagon::V6_vS32b_nt_nqpred_ai:
734 case Hexagon::V6_vS32b_nt_pred_ai:
735 case Hexagon::V6_vS32b_nt_qpred_ai:
736 case Hexagon::V6_vS32b_pred_ai:
737 case Hexagon::V6_vS32b_qpred_ai:
738 MappedInst = ScaleVectorOffset(Inst, OpNo: 2, VectorSize, Ctx&: OutContext);
739 return;
740
741 // V65+
742 case Hexagon::V6_vS32b_srls_ai:
743 MappedInst = ScaleVectorOffset(Inst, OpNo: 1, VectorSize, Ctx&: OutContext);
744 return;
745
746 case Hexagon::V6_vS32b_srls_pi:
747 MappedInst = ScaleVectorOffset(Inst, OpNo: 2, VectorSize, Ctx&: OutContext);
748 return;
749 }
750}
751
752/// Print out a single Hexagon MI to the current output stream.
753void HexagonAsmPrinter::emitInstruction(const MachineInstr *MI) {
754 Hexagon_MC::verifyInstructionPredicates(Opcode: MI->getOpcode(),
755 Features: getSubtargetInfo().getFeatureBits());
756
757 MCInst MCB;
758 MCB.setOpcode(Hexagon::BUNDLE);
759 MCB.addOperand(Op: MCOperand::createImm(Val: 0));
760 const MCInstrInfo &MCII = *Subtarget->getInstrInfo();
761
762 if (MI->isBundle()) {
763 const MachineBasicBlock* MBB = MI->getParent();
764 MachineBasicBlock::const_instr_iterator MII = MI->getIterator();
765
766 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
767 if (!MII->isDebugInstr() && !MII->isImplicitDef())
768 HexagonLowerToMC(MCII, MI: &*MII, MCB, AP&: *this);
769 } else {
770 HexagonLowerToMC(MCII, MI, MCB, AP&: *this);
771 }
772
773 const MachineFunction &MF = *MI->getParent()->getParent();
774 const auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
775 if (MI->isBundle() && HII.getBundleNoShuf(MIB: *MI))
776 HexagonMCInstrInfo::setMemReorderDisabled(MCB);
777
778 MCContext &Ctx = OutStreamer->getContext();
779 bool Ok = HexagonMCInstrInfo::canonicalizePacket(MCII, STI: *Subtarget, Context&: Ctx,
780 MCB, Checker: nullptr);
781 assert(Ok); (void)Ok;
782 if (HexagonMCInstrInfo::bundleSize(MCI: MCB) == 0)
783 return;
784 OutStreamer->emitInstruction(Inst: MCB, STI: getSubtargetInfo());
785}
786
787void HexagonAsmPrinter::emitStartOfAsmFile(Module &M) {
788 if (TM.getTargetTriple().isOSBinFormatELF())
789 emitAttributes();
790}
791
792void HexagonAsmPrinter::emitEndOfAsmFile(Module &M) {
793 HexagonTargetStreamer &HTS =
794 static_cast<HexagonTargetStreamer &>(*OutStreamer->getTargetStreamer());
795 if (TM.getTargetTriple().isOSBinFormatELF())
796 HTS.finishAttributeSection();
797}
798
799void HexagonAsmPrinter::emitAttributes() {
800 HexagonTargetStreamer &HTS =
801 static_cast<HexagonTargetStreamer &>(*OutStreamer->getTargetStreamer());
802 HTS.emitTargetAttributes(STI: TM.getMCSubtargetInfo());
803}
804
805void HexagonAsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI,
806 bool Typed) {
807 auto &O = *OutStreamer;
808 MCSymbol *CurSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
809 O.emitLabel(Symbol: CurSled);
810
811 auto *Sym = MCSymbolRefExpr::create(
812 Symbol: OutContext.getOrCreateSymbol(Name: Typed ? "__xray_TypedEvent"
813 : "__xray_CustomEvent"),
814 Ctx&: OutContext);
815
816 // The sled structure:
817 // .Lxray_sled_N:
818 // { jump .Lend } -- disabled (patched to nop when enabled)
819 // <save args, move operands, call handler, restore args>
820 // .Lend:
821
822 MCSymbol *EndSled = OutContext.createTempSymbol();
823
824 // Packet 1: jump over the sled (disabled state).
825 MCInst *JumpInst = OutContext.createMCInst();
826 JumpInst->setOpcode(Hexagon::J2_jump);
827 JumpInst->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
828 Expr: MCSymbolRefExpr::create(Symbol: EndSled, Ctx&: OutContext), Ctx&: OutContext)));
829
830 MCInst JumpPacket;
831 JumpPacket.setOpcode(Hexagon::BUNDLE);
832 JumpPacket.addOperand(Op: MCOperand::createImm(Val: 0));
833 JumpPacket.addOperand(Op: MCOperand::createInst(Val: JumpInst));
834 EmitToStreamer(S&: O, Inst: JumpPacket);
835
836 // Packet 2: allocframe to save LR:FP.
837 MCInst *AllocInst = OutContext.createMCInst();
838 AllocInst->setOpcode(Hexagon::S2_allocframe);
839 AllocInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R29));
840 AllocInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R30));
841 AllocInst->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
842 Expr: MCConstantExpr::create(Value: 0, Ctx&: OutContext), Ctx&: OutContext)));
843
844 MCInst AllocPacket;
845 AllocPacket.setOpcode(Hexagon::BUNDLE);
846 AllocPacket.addOperand(Op: MCOperand::createImm(Val: 0));
847 AllocPacket.addOperand(Op: MCOperand::createInst(Val: AllocInst));
848 EmitToStreamer(S&: O, Inst: AllocPacket);
849
850 // Save argument registers and set up call arguments.
851 // Custom event: 2 operands (ptr, size) in MI operands 0,1 -> r0, r1
852 // Typed event: 3 operands (type, ptr, size) in MI operands 0,1,2 ->
853 // r0,r1,r2
854 unsigned NumArgs = Typed ? 3 : 2;
855
856 // Save the original argument registers onto the stack.
857 // Packet 3: Allocate space and save r0.
858 MCInst *SubSpInst = OutContext.createMCInst();
859 SubSpInst->setOpcode(Hexagon::A2_addi);
860 SubSpInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R29));
861 SubSpInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R29));
862 SubSpInst->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
863 Expr: MCConstantExpr::create(Value: -(int64_t)(NumArgs * 4), Ctx&: OutContext),
864 Ctx&: OutContext)));
865
866 MCInst SubSpPacket;
867 SubSpPacket.setOpcode(Hexagon::BUNDLE);
868 SubSpPacket.addOperand(Op: MCOperand::createImm(Val: 0));
869 SubSpPacket.addOperand(Op: MCOperand::createInst(Val: SubSpInst));
870 EmitToStreamer(S&: O, Inst: SubSpPacket);
871
872 // Save each argument register.
873 for (unsigned I = 0; I < NumArgs; ++I) {
874 MCInst *StoreInst = OutContext.createMCInst();
875 StoreInst->setOpcode(Hexagon::S2_storeri_io);
876 StoreInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R29));
877 StoreInst->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
878 Expr: MCConstantExpr::create(Value: I * 4, Ctx&: OutContext), Ctx&: OutContext)));
879 StoreInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R0 + I));
880
881 MCInst StorePacket;
882 StorePacket.setOpcode(Hexagon::BUNDLE);
883 StorePacket.addOperand(Op: MCOperand::createImm(Val: 0));
884 StorePacket.addOperand(Op: MCOperand::createInst(Val: StoreInst));
885 EmitToStreamer(S&: O, Inst: StorePacket);
886 }
887
888 // Move operands into argument registers (r0, r1, [r2]).
889 // The XRay intrinsic uses i64 for size (and type) parameters. On 32-bit
890 // Hexagon these are in DoubleRegs (register pairs). The runtime handler
891 // expects 32-bit arguments, so extract the low sub-register.
892 //
893 // NOTE: Moves are always emitted (even identity moves like r0 = r0) so that
894 // the sled has a fixed size. The runtime patching code relies on the sled
895 // being a known number of words to encode the correct jump offset for the
896 // disabled state.
897 //
898 // NOTE: When source registers alias destination registers in a conflicting
899 // order (e.g., src0 in r1 and src1 in r0), the sequential moves can produce
900 // incorrect results. This is the same limitation as AArch64's implementation
901 // and is unlikely in practice since the register allocator rarely produces
902 // such assignments for XRay event intrinsics.
903 const auto &HRI = *MF->getSubtarget<HexagonSubtarget>().getRegisterInfo();
904 for (unsigned I = 0; I < NumArgs; ++I) {
905 Register SrcReg = MI.getOperand(i: I).getReg();
906 if (Hexagon::DoubleRegsRegClass.contains(Reg: SrcReg))
907 SrcReg = HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::isub_lo);
908
909 MCInst *MovInst = OutContext.createMCInst();
910 MovInst->setOpcode(Hexagon::A2_tfr);
911 MovInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R0 + I));
912 MovInst->addOperand(Op: MCOperand::createReg(Reg: SrcReg));
913
914 MCInst MovPacket;
915 MovPacket.setOpcode(Hexagon::BUNDLE);
916 MovPacket.addOperand(Op: MCOperand::createImm(Val: 0));
917 MovPacket.addOperand(Op: MCOperand::createInst(Val: MovInst));
918 EmitToStreamer(S&: O, Inst: MovPacket);
919 }
920
921 // Call the handler.
922 MCInst *CallInst = OutContext.createMCInst();
923 CallInst->setOpcode(Hexagon::J2_call);
924 CallInst->addOperand(
925 Op: MCOperand::createExpr(Val: HexagonMCExpr::create(Expr: Sym, Ctx&: OutContext)));
926
927 MCInst CallPacket;
928 CallPacket.setOpcode(Hexagon::BUNDLE);
929 CallPacket.addOperand(Op: MCOperand::createImm(Val: 0));
930 CallPacket.addOperand(Op: MCOperand::createInst(Val: CallInst));
931 EmitToStreamer(S&: O, Inst: CallPacket);
932
933 // Restore argument registers.
934 for (unsigned I = 0; I < NumArgs; ++I) {
935 MCInst *LoadInst = OutContext.createMCInst();
936 LoadInst->setOpcode(Hexagon::L2_loadri_io);
937 LoadInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R0 + I));
938 LoadInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R29));
939 LoadInst->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
940 Expr: MCConstantExpr::create(Value: I * 4, Ctx&: OutContext), Ctx&: OutContext)));
941
942 MCInst LoadPacket;
943 LoadPacket.setOpcode(Hexagon::BUNDLE);
944 LoadPacket.addOperand(Op: MCOperand::createImm(Val: 0));
945 LoadPacket.addOperand(Op: MCOperand::createInst(Val: LoadInst));
946 EmitToStreamer(S&: O, Inst: LoadPacket);
947 }
948
949 // Deallocate saved argument space.
950 MCInst *AddSpInst = OutContext.createMCInst();
951 AddSpInst->setOpcode(Hexagon::A2_addi);
952 AddSpInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R29));
953 AddSpInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R29));
954 AddSpInst->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
955 Expr: MCConstantExpr::create(Value: NumArgs * 4, Ctx&: OutContext), Ctx&: OutContext)));
956
957 MCInst AddSpPacket;
958 AddSpPacket.setOpcode(Hexagon::BUNDLE);
959 AddSpPacket.addOperand(Op: MCOperand::createImm(Val: 0));
960 AddSpPacket.addOperand(Op: MCOperand::createInst(Val: AddSpInst));
961 EmitToStreamer(S&: O, Inst: AddSpPacket);
962
963 // Deallocframe to restore LR:FP.
964 MCInst *DeallocInst = OutContext.createMCInst();
965 DeallocInst->setOpcode(Hexagon::L2_deallocframe);
966 DeallocInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::D15));
967 DeallocInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::R30));
968
969 MCInst DeallocPacket;
970 DeallocPacket.setOpcode(Hexagon::BUNDLE);
971 DeallocPacket.addOperand(Op: MCOperand::createImm(Val: 0));
972 DeallocPacket.addOperand(Op: MCOperand::createInst(Val: DeallocInst));
973 EmitToStreamer(S&: O, Inst: DeallocPacket);
974
975 OutStreamer->emitLabel(Symbol: EndSled);
976 recordSled(Sled: CurSled, MI,
977 Kind: Typed ? SledKind::TYPED_EVENT : SledKind::CUSTOM_EVENT, Version: 2);
978}
979
980void HexagonAsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) {
981 Register AddrReg = MI.getOperand(i: 0).getReg();
982 const int64_t Type = MI.getOperand(i: 1).getImm();
983 [[maybe_unused]] MachineBasicBlock::const_instr_iterator NextI =
984 std::next(x: MI.getIterator());
985 assert(NextI != MI.getParent()->instr_end() && NextI->isCall() &&
986 "KCFI_CHECK not followed by a call instruction");
987 assert(NextI->getOperand(0).getReg() == AddrReg &&
988 "KCFI_CHECK call target doesn't match call operand");
989
990 // Scratch registers for the compare. Default to R6/R7 (caller-saved,
991 // in GeneralSubRegs for potential compounding). If AddrReg conflicts,
992 // fall back through other caller-saved registers.
993 unsigned ScratchRegs[] = {Hexagon::R6, Hexagon::R7};
994 unsigned NextReg = Hexagon::R8;
995 for (auto &Reg : ScratchRegs) {
996 if (Reg != AddrReg)
997 continue;
998 if (NextReg == AddrReg)
999 ++NextReg;
1000 Reg = NextReg++;
1001 }
1002 unsigned LoadReg = ScratchRegs[0];
1003 unsigned TypeReg = ScratchRegs[1];
1004 unsigned PredReg = Hexagon::P0;
1005
1006 // Adjust for patchable-function-prefix (nop padding before the function).
1007 int64_t PrefixNops = MI.getMF()->getFunction().getFnAttributeAsParsedInteger(
1008 Kind: "patchable-function-prefix");
1009 int64_t Offset = -(PrefixNops * 4 + 4);
1010
1011 // Emit the KCFI check sequence.
1012 //
1013 // Packet 1: load the type hash and materialize the expected hash together.
1014 // The load offset only leaves its field for an implausible
1015 // patchable-function-prefix, but extend it rather than truncate.
1016 // { r_load = memw(r_addr + #offset); r_type = ##expected_hash }
1017 MCInst *LoadInst = OutContext.createMCInst();
1018 LoadInst->setOpcode(Hexagon::L2_loadri_io);
1019 LoadInst->addOperand(Op: MCOperand::createReg(Reg: LoadReg));
1020 LoadInst->addOperand(Op: MCOperand::createReg(Reg: AddrReg));
1021 LoadInst->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
1022 Expr: MCConstantExpr::create(Value: Offset, Ctx&: OutContext), Ctx&: OutContext)));
1023
1024 MCInst *TypeInst = OutContext.createMCInst();
1025 TypeInst->setOpcode(Hexagon::A2_tfrsi);
1026 TypeInst->addOperand(Op: MCOperand::createReg(Reg: TypeReg));
1027 auto *TypeExpr = HexagonMCExpr::create(
1028 Expr: MCConstantExpr::create(Value: Type, Ctx&: OutContext), Ctx&: OutContext);
1029 HexagonMCInstrInfo::setMustExtend(Expr: *TypeExpr, Val: true);
1030 TypeInst->addOperand(Op: MCOperand::createExpr(Val: TypeExpr));
1031
1032 // setMustExtend() only records that an operand needs an extender; the
1033 // extender still has to be inserted, and slot assignment has to place it
1034 // ahead of what it extends. HexagonLowerToMC()/emitInstruction() do both
1035 // for the MachineInstr stream; packets built here get neither.
1036 const MCInstrInfo &MCII = *Subtarget->getInstrInfo();
1037
1038 // Slot assignment is required for correctness, not just density: an extender
1039 // encoded after its instruction is not a legal packet. Passing a checker
1040 // (rather than nullptr) is what makes the assert meaningful.
1041 auto EmitPacket = [&](MCInst &MCB) {
1042 HexagonMCChecker Checker(OutContext, MCII, *Subtarget, MCB,
1043 *OutContext.getRegisterInfo(),
1044 /*ReportErrors=*/false);
1045 [[maybe_unused]] bool Ok = HexagonMCInstrInfo::canonicalizePacket(
1046 MCII, STI: *Subtarget, Context&: OutContext, MCB, Checker: &Checker);
1047 assert(Ok && "KCFI packet failed MC canonicalization");
1048 EmitToStreamer(S&: *OutStreamer, Inst: MCB);
1049 };
1050
1051 MCInst LoadTypePacket;
1052 LoadTypePacket.setOpcode(Hexagon::BUNDLE);
1053 LoadTypePacket.addOperand(Op: MCOperand::createImm(Val: 0));
1054 HexagonMCInstrInfo::extendIfNeeded(Context&: OutContext, MCII, MCB&: LoadTypePacket,
1055 MCI: *LoadInst);
1056 LoadTypePacket.addOperand(Op: MCOperand::createInst(Val: LoadInst));
1057 HexagonMCInstrInfo::extendIfNeeded(Context&: OutContext, MCII, MCB&: LoadTypePacket,
1058 MCI: *TypeInst);
1059 LoadTypePacket.addOperand(Op: MCOperand::createInst(Val: TypeInst));
1060 EmitPacket(LoadTypePacket);
1061
1062 // Packet 3: Compare and branch if equal.
1063 // { p0 = cmp.eq(r_load, r_type); if (p0.new) jump:t .Lpass }
1064 MCSymbol *Pass = OutContext.createTempSymbol();
1065
1066 MCInst *CmpInst = OutContext.createMCInst();
1067 CmpInst->setOpcode(Hexagon::C2_cmpeq);
1068 CmpInst->addOperand(Op: MCOperand::createReg(Reg: PredReg));
1069 CmpInst->addOperand(Op: MCOperand::createReg(Reg: LoadReg));
1070 CmpInst->addOperand(Op: MCOperand::createReg(Reg: TypeReg));
1071
1072 MCInst *JumpInst = OutContext.createMCInst();
1073 JumpInst->setOpcode(Hexagon::J2_jumptnewpt);
1074 JumpInst->addOperand(Op: MCOperand::createReg(Reg: PredReg));
1075 JumpInst->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
1076 Expr: MCSymbolRefExpr::create(Symbol: Pass, Ctx&: OutContext), Ctx&: OutContext)));
1077
1078 MCInst CmpJmpPacket;
1079 CmpJmpPacket.setOpcode(Hexagon::BUNDLE);
1080 CmpJmpPacket.addOperand(Op: MCOperand::createImm(Val: 0));
1081 CmpJmpPacket.addOperand(Op: MCOperand::createInst(Val: CmpInst));
1082 CmpJmpPacket.addOperand(Op: MCOperand::createInst(Val: JumpInst));
1083 EmitPacket(CmpJmpPacket);
1084
1085 // Packet 4: Crash on mismatch via misaligned load.
1086 // Use the same mechanism as llvm.trap (PS_crash): a doubleword load from
1087 // a misaligned address is guaranteed to fault in all execution modes,
1088 // including kernel/monitor mode where trap0 may not generate a useful
1089 // exception.
1090 MCSymbol *TrapLabel = OutContext.createTempSymbol();
1091 OutStreamer->emitLabel(Symbol: TrapLabel);
1092
1093 MCInst *CrashInst = OutContext.createMCInst();
1094 CrashInst->setOpcode(Hexagon::PS_loadrdabs);
1095 CrashInst->addOperand(Op: MCOperand::createReg(Reg: Hexagon::D13));
1096 auto *CrashExpr = HexagonMCExpr::create(
1097 Expr: MCConstantExpr::create(Value: 0xBADC0FEE, Ctx&: OutContext), Ctx&: OutContext);
1098 HexagonMCInstrInfo::setMustExtend(Expr: *CrashExpr, Val: true);
1099 CrashInst->addOperand(Op: MCOperand::createExpr(Val: CrashExpr));
1100
1101 MCInst CrashPacket;
1102 CrashPacket.setOpcode(Hexagon::BUNDLE);
1103 CrashPacket.addOperand(Op: MCOperand::createImm(Val: 0));
1104 HexagonMCInstrInfo::extendIfNeeded(Context&: OutContext, MCII, MCB&: CrashPacket, MCI: *CrashInst);
1105 CrashPacket.addOperand(Op: MCOperand::createInst(Val: CrashInst));
1106 EmitPacket(CrashPacket);
1107
1108 emitKCFITrapEntry(MF: *MI.getMF(), Symbol: TrapLabel);
1109 OutStreamer->emitLabel(Symbol: Pass);
1110}
1111
1112void HexagonAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) {
1113 static const int8_t NoopsInSledCount = 6;
1114 // We want to emit the following pattern:
1115 //
1116 // .L_xray_sled_N:
1117 // <xray_sled_base>:
1118 // { jump .Ltmp0 }
1119 // { nop }
1120 // { nop }
1121 // { nop }
1122 // { nop }
1123 // { nop }
1124 // { nop }
1125 // .Ltmp0:
1126 //
1127 // We need the 6 nop words because at runtime, we'd be patching over the
1128 // full 7 words with the following pattern:
1129 //
1130 // <xray_sled_n>:
1131 // { allocframe(#0) }
1132 // { immext(#...) // upper 26-bits of func id
1133 // r7 = ##... // lower 6-bits of func id
1134 // immext(#...) // upper 26-bits of trampoline
1135 // r6 = ##... } // lower 6-bits of trampoline
1136 // { callr r6 }
1137 // { deallocframe }
1138 //
1139 // allocframe saves r31:30 (LR:FP) before the call, and deallocframe
1140 // restores them after the trampoline returns, ensuring the caller's
1141 // return address in r31 is preserved across the sled.
1142 //
1143 auto CurSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
1144 OutStreamer->emitLabel(Symbol: CurSled);
1145
1146 MCInst *SledJump = new (OutContext) MCInst();
1147 SledJump->setOpcode(Hexagon::J2_jump);
1148 auto PostSled = OutContext.createTempSymbol();
1149 SledJump->addOperand(Op: MCOperand::createExpr(Val: HexagonMCExpr::create(
1150 Expr: MCSymbolRefExpr::create(Symbol: PostSled, Ctx&: OutContext), Ctx&: OutContext)));
1151
1152 // Emit "jump PostSled" instruction, which jumps over the nop series.
1153 MCInst SledJumpPacket;
1154 SledJumpPacket.setOpcode(Hexagon::BUNDLE);
1155 SledJumpPacket.addOperand(Op: MCOperand::createImm(Val: 0));
1156 SledJumpPacket.addOperand(Op: MCOperand::createInst(Val: SledJump));
1157
1158 EmitToStreamer(S&: *OutStreamer, Inst: SledJumpPacket);
1159
1160 // FIXME: this will emit individual packets, we should
1161 // special-case this and combine them into a single packet.
1162 emitNops(N: NoopsInSledCount);
1163
1164 OutStreamer->emitLabel(Symbol: PostSled);
1165 recordSled(Sled: CurSled, MI, Kind, Version: 2);
1166}
1167
1168void HexagonAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI) {
1169 EmitSled(MI, Kind: SledKind::FUNCTION_ENTER);
1170}
1171
1172void HexagonAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI) {
1173 EmitSled(MI, Kind: SledKind::FUNCTION_EXIT);
1174}
1175
1176void HexagonAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI) {
1177 EmitSled(MI, Kind: SledKind::TAIL_CALL);
1178}
1179
1180char HexagonAsmPrinter::ID = 0;
1181
1182INITIALIZE_PASS(HexagonAsmPrinter, "hexagon-asm-printer",
1183 "Hexagon Assembly Printer", false, false)
1184
1185extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
1186LLVMInitializeHexagonAsmPrinter() {
1187 RegisterAsmPrinter<HexagonAsmPrinter> X(getTheHexagonTarget());
1188}
1189