1//===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that Hexagon uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
15#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16
17#include "Hexagon.h"
18#include "MCTargetDesc/HexagonMCTargetDesc.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/CodeGen/ISDOpcodes.h"
21#include "llvm/CodeGen/SelectionDAGNodes.h"
22#include "llvm/CodeGen/TargetLowering.h"
23#include "llvm/CodeGen/ValueTypes.h"
24#include "llvm/CodeGenTypes/MachineValueType.h"
25#include "llvm/IR/CallingConv.h"
26#include "llvm/IR/InlineAsm.h"
27#include <cstdint>
28#include <utility>
29
30namespace llvm {
31
32class HexagonSubtarget;
33
34class HexagonTargetLowering : public TargetLowering {
35 int VarArgsFrameOffset; // Frame offset to start of varargs area.
36 const HexagonTargetMachine &HTM;
37 const HexagonSubtarget &Subtarget;
38
39public:
40 explicit HexagonTargetLowering(const TargetMachine &TM,
41 const HexagonSubtarget &ST);
42
43 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
44 /// for tail call optimization. Targets which want to do tail call
45 /// optimization should implement this function.
46 bool IsEligibleForTailCallOptimization(SDValue Callee,
47 CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
48 bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
49 const SmallVectorImpl<SDValue> &OutVals,
50 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
51
52 void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos,
53 const CallBase &I, MachineFunction &MF,
54 unsigned Intrinsic) const override;
55
56 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
57 bool isTruncateFree(EVT VT1, EVT VT2) const override;
58
59 bool isCheapToSpeculateCttz(Type *) const override { return true; }
60 bool isCheapToSpeculateCtlz(Type *) const override { return true; }
61 bool isCtlzFast() const override { return true; }
62
63 bool hasBitTest(SDValue X, SDValue Y) const override;
64
65 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
66
67 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
68
69 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
70
71 /// Return true if an FMA operation is faster than a pair of mul and add
72 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
73 /// method returns true (and FMAs are legal), otherwise fmuladd is
74 /// expanded to mul + add.
75 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &,
76 EVT) const override;
77
78 // Should we expand the build vector with shuffles?
79 bool shouldExpandBuildVectorWithShuffles(EVT VT,
80 unsigned DefinedValues) const override;
81 ExtractSubvectorCost getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
82 unsigned Index) const override;
83
84 bool isTargetCanonicalConstantNode(SDValue Op) const override;
85
86 bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
87 LegalizeTypeAction getPreferredVectorAction(MVT VT) const override;
88 LegalizeAction getCustomOperationAction(SDNode &Op) const override;
89
90 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
91 void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
92 SelectionDAG &DAG) const override;
93 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
94 SelectionDAG &DAG) const override;
95
96 std::pair<MVT, unsigned>
97 handleMaskRegisterForCallingConv(const HexagonSubtarget &Subtarget,
98 EVT VT) const;
99
100 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
101 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
102 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
103 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
104 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
105 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
106 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
110 SDValue LowerANY_EXTEND(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
112 SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
113 SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const;
114 SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const;
115 SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const;
116 SDValue LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const;
117 SDValue LowerUAddSubOCarry(SDValue Op, SelectionDAG &DAG) const;
118
119 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
120 SDValue LowerFMINFMAX(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
122 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
125 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
126 SDValue
127 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
128 const SmallVectorImpl<ISD::InputArg> &Ins,
129 const SDLoc &dl, SelectionDAG &DAG,
130 SmallVectorImpl<SDValue> &InVals) const override;
131 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
135 SelectionDAG &DAG) const;
136 SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
137 SelectionDAG &DAG) const;
138 SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
139 SelectionDAG &DAG) const;
140 SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
141 GlobalAddressSDNode *GA, SDValue InGlue, EVT PtrVT,
142 unsigned ReturnReg, unsigned char OperandGlues) const;
143 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
144
145 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
146 SmallVectorImpl<SDValue> &InVals) const override;
147 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
148 CallingConv::ID CallConv, bool isVarArg,
149 const SmallVectorImpl<ISD::InputArg> &Ins,
150 const SDLoc &dl, SelectionDAG &DAG,
151 SmallVectorImpl<SDValue> &InVals,
152 const SmallVectorImpl<SDValue> &OutVals,
153 SDValue Callee) const;
154
155 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
158 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
159 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
160
161 bool CanLowerReturn(CallingConv::ID CallConv,
162 MachineFunction &MF, bool isVarArg,
163 const SmallVectorImpl<ISD::OutputArg> &Outs,
164 LLVMContext &Context, const Type *RetTy) const override;
165
166 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
167 const SmallVectorImpl<ISD::OutputArg> &Outs,
168 const SmallVectorImpl<SDValue> &OutVals,
169 const SDLoc &dl, SelectionDAG &DAG) const override;
170
171 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
172
173 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
174
175 Register getRegisterByName(const char* RegName, LLT VT,
176 const MachineFunction &MF) const override;
177
178 unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context,
179 CallingConv::ID CC, EVT VT,
180 EVT &IntermediateVT,
181 unsigned &NumIntermediates,
182 MVT &RegisterVT) const override;
183
184 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
185 EVT VT) const override;
186 /// If a physical register, this returns the register that receives the
187 /// exception address on entry to an EH pad.
188 Register
189 getExceptionPointerRegister(ExceptionHandling EH,
190 const Constant *PersonalityFn) const override {
191 return Hexagon::R0;
192 }
193
194 /// If a physical register, this returns the register that receives the
195 /// exception typeid on entry to a landing pad.
196 Register
197 getExceptionSelectorRegister(ExceptionHandling EH,
198 const Constant *PersonalityFn) const override {
199 return Hexagon::R1;
200 }
201
202 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
203 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
204 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
205 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
206
207 EVT getSetCCResultType(const DataLayout &, LLVMContext &C,
208 EVT VT) const override {
209 if (!VT.isVector())
210 return MVT::i1;
211 else
212 return EVT::getVectorVT(Context&: C, VT: MVT::i1, NumElements: VT.getVectorNumElements());
213 }
214
215 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
216 SDValue &Base, SDValue &Offset,
217 ISD::MemIndexedMode &AM,
218 SelectionDAG &DAG) const override;
219
220 ConstraintType getConstraintType(StringRef Constraint) const override;
221
222 std::pair<unsigned, const TargetRegisterClass *>
223 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
224 StringRef Constraint, MVT VT) const override;
225
226 // Intrinsics
227 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
228 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
229 /// isLegalAddressingMode - Return true if the addressing mode represented
230 /// by AM is legal for this target, for a load/store of the specified type.
231 /// The type may be VoidTy, in which case only return true if the addressing
232 /// mode is legal for a load/store of any legal type.
233 /// TODO: Handle pre/postinc as well.
234 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
235 Type *Ty, unsigned AS,
236 Instruction *I = nullptr) const override;
237 /// Return true if folding a constant offset with the given GlobalAddress
238 /// is legal. It is frequently not legal in PIC relocation models.
239 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
240
241 bool isFPImmLegal(const APFloat &Imm, EVT VT,
242 bool ForCodeSize) const override;
243
244 /// isLegalICmpImmediate - Return true if the specified immediate is legal
245 /// icmp immediate, that is the target has icmp instructions which can
246 /// compare a register against the immediate without having to materialize
247 /// the immediate into a register.
248 bool isLegalICmpImmediate(int64_t Imm) const override;
249
250 EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,
251 const AttributeList &FuncAttributes) const override;
252
253 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
254 unsigned AddrSpace, Align Alignment,
255 MachineMemOperand::Flags Flags,
256 unsigned *Fast) const override;
257
258 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
259 Align Alignment,
260 MachineMemOperand::Flags Flags,
261 unsigned *Fast) const override;
262
263 /// Returns relocation base for the given PIC jumptable.
264 SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG)
265 const override;
266
267 /// Returns true if it is beneficial to convert a load of a constant
268 /// to just the constant itself.
269 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
270 Type *Ty) const override;
271
272 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
273 std::optional<unsigned> ByteOffset) const override;
274
275 void AdjustInstrPostInstrSelection(MachineInstr &MI,
276 SDNode *Node) const override;
277
278 // Handling of atomic RMW instructions.
279 Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr,
280 AtomicOrdering Ord) const override;
281 Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr,
282 AtomicOrdering Ord) const override;
283 AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
284 AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
285 AtomicExpansionKind
286 shouldExpandAtomicCmpXchgInIR(const AtomicCmpXchgInst *AI) const override;
287
288 AtomicExpansionKind
289 shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const override {
290 return AtomicExpansionKind::LLSC;
291 }
292
293 MachineBasicBlock *
294 EmitInstrWithCustomInserter(MachineInstr &MI,
295 MachineBasicBlock *BB) const override;
296
297 bool supportKCFIBundles() const override { return true; }
298
299 MachineInstr *EmitKCFICheck(MachineBasicBlock &MBB,
300 MachineBasicBlock::instr_iterator &MBBI,
301 const TargetInstrInfo *TII) const override;
302
303 bool hasInlineStackProbe(const MachineFunction &MF) const override;
304 unsigned getStackProbeSize(const MachineFunction &MF, Align StackAlign) const;
305
306private:
307 void initializeHVXLowering();
308 unsigned getPreferredHvxVectorAction(MVT VecTy) const;
309 unsigned getCustomHvxOperationAction(SDNode &Op) const;
310
311 bool validateConstPtrAlignment(SDValue Ptr, Align NeedAlign, const SDLoc &dl,
312 SelectionDAG &DAG) const;
313 SDValue replaceMemWithUndef(SDValue Op, SelectionDAG &DAG) const;
314
315 std::pair<SDValue,int> getBaseAndOffset(SDValue Addr) const;
316
317 bool getBuildVectorConstInts(ArrayRef<SDValue> Values, MVT VecTy,
318 SelectionDAG &DAG,
319 MutableArrayRef<ConstantInt*> Consts) const;
320 SDValue buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
321 SelectionDAG &DAG) const;
322 SDValue buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
323 SelectionDAG &DAG) const;
324 SDValue extractVector(SDValue VecV, SDValue IdxV, const SDLoc &dl,
325 MVT ValTy, MVT ResTy, SelectionDAG &DAG) const;
326 SDValue extractVectorPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
327 MVT ValTy, MVT ResTy, SelectionDAG &DAG) const;
328 SDValue insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
329 const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const;
330 SDValue insertVectorPred(SDValue VecV, SDValue ValV, SDValue IdxV,
331 const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const;
332 SDValue expandPredicate(SDValue Vec32, const SDLoc &dl,
333 SelectionDAG &DAG) const;
334 SDValue contractPredicate(SDValue Vec64, const SDLoc &dl,
335 SelectionDAG &DAG) const;
336 SDValue getSplatValue(SDValue Op, SelectionDAG &DAG) const;
337 SDValue getVectorShiftByInt(SDValue Op, SelectionDAG &DAG) const;
338 SDValue appendUndef(SDValue Val, MVT ResTy, SelectionDAG &DAG) const;
339 SDValue getCombine(SDValue Hi, SDValue Lo, const SDLoc &dl, MVT ResTy,
340 SelectionDAG &DAG) const;
341
342 bool isUndef(SDValue Op) const {
343 if (Op.isMachineOpcode())
344 return Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
345 return Op.getOpcode() == ISD::UNDEF;
346 }
347 SDValue getInstr(unsigned MachineOpc, const SDLoc &dl, MVT Ty,
348 ArrayRef<SDValue> Ops, SelectionDAG &DAG) const {
349 SDNode *N = DAG.getMachineNode(Opcode: MachineOpc, dl, VT: Ty, Ops);
350 return SDValue(N, 0);
351 }
352 SDValue getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG) const;
353
354 using VectorPair = std::pair<SDValue, SDValue>;
355 using TypePair = std::pair<MVT, MVT>;
356
357 SDValue getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
358 const SDLoc &dl, SelectionDAG &DAG) const;
359
360 MVT ty(SDValue Op) const {
361 return Op.getValueType().getSimpleVT();
362 }
363 TypePair ty(const VectorPair &Ops) const {
364 return { Ops.first.getValueType().getSimpleVT(),
365 Ops.second.getValueType().getSimpleVT() };
366 }
367 MVT tyScalar(MVT Ty) const {
368 if (!Ty.isVector())
369 return Ty;
370 return MVT::getIntegerVT(BitWidth: Ty.getSizeInBits());
371 }
372 MVT tyVector(MVT Ty, MVT ElemTy) const {
373 if (Ty.isVectorOf(EltVT: ElemTy))
374 return Ty;
375 unsigned TyWidth = Ty.getSizeInBits();
376 unsigned ElemWidth = ElemTy.getSizeInBits();
377 assert((TyWidth % ElemWidth) == 0);
378 return MVT::getVectorVT(VT: ElemTy, NumElements: TyWidth/ElemWidth);
379 }
380
381 MVT typeJoin(const TypePair &Tys) const;
382 TypePair typeSplit(MVT Ty) const;
383 MVT typeExtElem(MVT VecTy, unsigned Factor) const;
384 MVT typeTruncElem(MVT VecTy, unsigned Factor) const;
385 TypePair typeExtendToWider(MVT Ty0, MVT Ty1) const;
386 TypePair typeWidenToWider(MVT Ty0, MVT Ty1) const;
387 MVT typeLegalize(MVT Ty, SelectionDAG &DAG) const;
388 MVT typeWidenToHvx(MVT Ty) const;
389
390 SDValue opJoin(const VectorPair &Ops, const SDLoc &dl,
391 SelectionDAG &DAG) const;
392 VectorPair opSplit(SDValue Vec, const SDLoc &dl, SelectionDAG &DAG) const;
393 SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG) const;
394
395 SDValue LoHalf(SDValue V, SelectionDAG &DAG) const {
396 MVT Ty = ty(Op: V);
397 const SDLoc &dl(V);
398 if (!Ty.isVector()) {
399 assert(Ty.getSizeInBits() == 64);
400 return DAG.getTargetExtractSubreg(SRIdx: Hexagon::isub_lo, DL: dl, VT: MVT::i32, Operand: V);
401 }
402 MVT HalfTy = typeSplit(Ty).first;
403 SDValue Idx = getZero(dl, Ty: MVT::i32, DAG);
404 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: HalfTy, N1: V, N2: Idx);
405 }
406 SDValue HiHalf(SDValue V, SelectionDAG &DAG) const {
407 MVT Ty = ty(Op: V);
408 const SDLoc &dl(V);
409 if (!Ty.isVector()) {
410 assert(Ty.getSizeInBits() == 64);
411 return DAG.getTargetExtractSubreg(SRIdx: Hexagon::isub_hi, DL: dl, VT: MVT::i32, Operand: V);
412 }
413 MVT HalfTy = typeSplit(Ty).first;
414 SDValue Idx = DAG.getConstant(Val: HalfTy.getVectorNumElements(), DL: dl, VT: MVT::i32);
415 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: HalfTy, N1: V, N2: Idx);
416 }
417
418 bool allowsHvxMemoryAccess(MVT VecTy, MachineMemOperand::Flags Flags,
419 unsigned *Fast) const;
420 bool allowsHvxMisalignedMemoryAccesses(MVT VecTy,
421 MachineMemOperand::Flags Flags,
422 unsigned *Fast) const;
423 void AdjustHvxInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const;
424
425 bool isHvxSingleTy(MVT Ty) const;
426 bool isHvxPairTy(MVT Ty) const;
427 bool isHvxBoolTy(MVT Ty) const;
428 SDValue convertToByteIndex(SDValue ElemIdx, MVT ElemTy,
429 SelectionDAG &DAG) const;
430 SDValue getIndexInWord32(SDValue Idx, MVT ElemTy, SelectionDAG &DAG) const;
431 SDValue getByteShuffle(const SDLoc &dl, SDValue Op0, SDValue Op1,
432 ArrayRef<int> Mask, SelectionDAG &DAG) const;
433
434 SDValue buildHvxVectorReg(ArrayRef<SDValue> Values, const SDLoc &dl,
435 MVT VecTy, SelectionDAG &DAG) const;
436 SDValue buildHvxVectorPred(ArrayRef<SDValue> Values, const SDLoc &dl,
437 MVT VecTy, SelectionDAG &DAG) const;
438 SDValue createHvxPrefixPred(SDValue PredV, const SDLoc &dl,
439 unsigned BitBytes, bool ZeroFill,
440 SelectionDAG &DAG) const;
441 SDValue extractHvxElementReg(SDValue VecV, SDValue IdxV, const SDLoc &dl,
442 MVT ResTy, SelectionDAG &DAG) const;
443 SDValue extractHvxElementPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
444 MVT ResTy, SelectionDAG &DAG) const;
445 SDValue insertHvxElementReg(SDValue VecV, SDValue IdxV, SDValue ValV,
446 const SDLoc &dl, SelectionDAG &DAG) const;
447 SDValue insertHvxElementPred(SDValue VecV, SDValue IdxV, SDValue ValV,
448 const SDLoc &dl, SelectionDAG &DAG) const;
449 SDValue extractHvxSubvectorReg(SDValue OrigOp, SDValue VecV, SDValue IdxV,
450 const SDLoc &dl, MVT ResTy, SelectionDAG &DAG)
451 const;
452 SDValue extractHvxSubvectorPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
453 MVT ResTy, SelectionDAG &DAG) const;
454 SDValue insertHvxSubvectorReg(SDValue VecV, SDValue SubV, SDValue IdxV,
455 const SDLoc &dl, SelectionDAG &DAG) const;
456 SDValue insertHvxSubvectorPred(SDValue VecV, SDValue SubV, SDValue IdxV,
457 const SDLoc &dl, SelectionDAG &DAG) const;
458 SDValue extendHvxVectorPred(SDValue VecV, const SDLoc &dl, MVT ResTy,
459 bool ZeroExt, SelectionDAG &DAG) const;
460 SDValue compressHvxPred(SDValue VecQ, const SDLoc &dl, MVT ResTy,
461 SelectionDAG &DAG) const;
462 SDValue resizeToWidth(SDValue VecV, MVT ResTy, bool Signed, const SDLoc &dl,
463 SelectionDAG &DAG) const;
464 SDValue extractSubvector(SDValue Vec, MVT SubTy, unsigned SubIdx,
465 SelectionDAG &DAG) const;
466 VectorPair emitHvxAddWithOverflow(SDValue A, SDValue B, const SDLoc &dl,
467 bool Signed, SelectionDAG &DAG) const;
468 VectorPair emitHvxShiftRightRnd(SDValue Val, unsigned Amt, bool Signed,
469 SelectionDAG &DAG) const;
470 SDValue emitHvxMulHsV60(SDValue A, SDValue B, const SDLoc &dl,
471 SelectionDAG &DAG) const;
472 SDValue emitHvxMulLoHiV60(SDValue A, bool SignedA, SDValue B, bool SignedB,
473 const SDLoc &dl, SelectionDAG &DAG) const;
474 SDValue emitHvxMulLoHiV62(SDValue A, bool SignedA, SDValue B, bool SignedB,
475 const SDLoc &dl, SelectionDAG &DAG) const;
476
477 SDValue LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) const;
478 SDValue LowerHvxSplatVector(SDValue Op, SelectionDAG &DAG) const;
479 SDValue LowerHvxConcatVectors(SDValue Op, SelectionDAG &DAG) const;
480 SDValue LowerHvxExtractElement(SDValue Op, SelectionDAG &DAG) const;
481 SDValue LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) const;
482 SDValue LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG) const;
483 SDValue LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG) const;
484 SDValue LowerHvxBitcast(SDValue Op, SelectionDAG &DAG) const;
485 SDValue LowerHvxAnyExt(SDValue Op, SelectionDAG &DAG) const;
486 SDValue LowerHvxSignExt(SDValue Op, SelectionDAG &DAG) const;
487 SDValue LowerHvxZeroExt(SDValue Op, SelectionDAG &DAG) const;
488 SDValue LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const;
489 SDValue LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const;
490 SDValue LowerHvxMulLoHi(SDValue Op, SelectionDAG &DAG) const;
491 SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const;
492 SDValue LowerHvxSelect(SDValue Op, SelectionDAG &DAG) const;
493 SDValue LowerHvxShift(SDValue Op, SelectionDAG &DAG) const;
494 SDValue LowerHvxFunnelShift(SDValue Op, SelectionDAG &DAG) const;
495 SDValue LowerHvxIntrinsic(SDValue Op, SelectionDAG &DAG) const;
496 SDValue LowerHvxMaskedOp(SDValue Op, SelectionDAG &DAG) const;
497 SDValue LowerHvxFpExtend(SDValue Op, SelectionDAG &DAG) const;
498 SDValue LowerHvxFpToInt(SDValue Op, SelectionDAG &DAG) const;
499 SDValue LowerHvxIntToFp(SDValue Op, SelectionDAG &DAG) const;
500 SDValue LowerHvxPred32ToFp(SDValue Op, SelectionDAG &DAG) const;
501 SDValue LowerHvxPred64ToFp(SDValue Op, SelectionDAG &DAG) const;
502 SDValue LowerHvxPartialReduceMLA(SDValue Op, SelectionDAG &DAG) const;
503 SDValue LowerHvxFpSetoeq(SDValue Op, SelectionDAG &DAG) const;
504 SDValue ExpandHvxFpToInt(SDValue Op, SelectionDAG &DAG) const;
505 SDValue ExpandHvxIntToFp(SDValue Op, SelectionDAG &DAG) const;
506 SDValue LowerHvxStore(SDValue Op, SelectionDAG &DAG) const;
507 SDValue LowerHvxLoad(SDValue Op, SelectionDAG &DAG) const;
508
509 VectorPair SplitVectorOp(SDValue Op, SelectionDAG &DAG) const;
510
511 SDValue SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const;
512 SDValue WidenHvxLoad(SDValue Op, SelectionDAG &DAG) const;
513 SDValue WidenHvxStore(SDValue Op, SelectionDAG &DAG) const;
514 SDValue WidenHvxSetCC(SDValue Op, SelectionDAG &DAG) const;
515 SDValue LegalizeHvxResize(SDValue Op, SelectionDAG &DAG) const;
516 SDValue ExpandHvxResizeIntoSteps(SDValue Op, SelectionDAG &DAG) const;
517 SDValue EqualizeFpIntConversion(SDValue Op, SelectionDAG &DAG) const;
518
519 SDValue CreateTLWrapper(SDValue Op, SelectionDAG &DAG) const;
520 SDValue RemoveTLWrapper(SDValue Op, SelectionDAG &DAG) const;
521 SDValue WidenHvxTruncateToBool(SDValue Op, SelectionDAG &DAG) const;
522
523 std::pair<const TargetRegisterClass*, uint8_t>
524 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
525 const override;
526
527 bool shouldSplitToHvx(MVT Ty, SelectionDAG &DAG) const;
528 bool shouldWidenToHvx(MVT Ty, SelectionDAG &DAG) const;
529 bool isHvxOperation(SDNode *N, SelectionDAG &DAG) const;
530 SDValue LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const;
531 void LowerHvxOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
532 SelectionDAG &DAG) const;
533 void ReplaceHvxNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
534 SelectionDAG &DAG) const;
535
536 SDValue combineTruncateBeforeLegal(SDValue Op, DAGCombinerInfo &DCI) const;
537
538 SDValue combineConcatOfShuffles(SDValue Op, SelectionDAG &DAG) const;
539 SDValue combineConcatOfScalarPreds(SDValue Op, unsigned BitBytes,
540 SelectionDAG &DAG) const;
541 SDValue combineConcatVectorsBeforeLegal(SDValue Op, DAGCombinerInfo & DCI)
542 const;
543 SDValue expandVecReduceAdd(SDNode *N, SelectionDAG &DAG) const;
544 SDValue createExtendingPartialReduceMLA(
545 unsigned Opcode, EVT AccEltType, unsigned AccNumElements, EVT InputType,
546 const SDValue &A, const SDValue &B, unsigned &RemainingReductionRatio,
547 const SDLoc &DL, SelectionDAG &DAG) const;
548 SDValue splitVecReduceAdd(SDNode *N, SelectionDAG &DAG) const;
549 SDValue splitExtendingPartialReduceMLA(SDNode *N, SelectionDAG &DAG) const;
550 SDValue PerformHvxDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
551};
552
553} // end namespace llvm
554
555#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
556