1//===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that Hexagon uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
15#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16
17#include "Hexagon.h"
18#include "MCTargetDesc/HexagonMCTargetDesc.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/CodeGen/ISDOpcodes.h"
21#include "llvm/CodeGen/SelectionDAGNodes.h"
22#include "llvm/CodeGen/TargetLowering.h"
23#include "llvm/CodeGen/ValueTypes.h"
24#include "llvm/CodeGenTypes/MachineValueType.h"
25#include "llvm/IR/CallingConv.h"
26#include "llvm/IR/InlineAsm.h"
27#include <cstdint>
28#include <utility>
29
30namespace llvm {
31
32class HexagonSubtarget;
33
34class HexagonTargetLowering : public TargetLowering {
35 int VarArgsFrameOffset; // Frame offset to start of varargs area.
36 const HexagonTargetMachine &HTM;
37 const HexagonSubtarget &Subtarget;
38
39public:
40 explicit HexagonTargetLowering(const TargetMachine &TM,
41 const HexagonSubtarget &ST);
42
43 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
44 /// for tail call optimization. Targets which want to do tail call
45 /// optimization should implement this function.
46 bool IsEligibleForTailCallOptimization(SDValue Callee,
47 CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
48 bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
49 const SmallVectorImpl<SDValue> &OutVals,
50 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
51
52 void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos,
53 const CallBase &I, MachineFunction &MF,
54 unsigned Intrinsic) const override;
55
56 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
57 bool isTruncateFree(EVT VT1, EVT VT2) const override;
58
59 bool isCheapToSpeculateCttz(Type *) const override { return true; }
60 bool isCheapToSpeculateCtlz(Type *) const override { return true; }
61 bool isCtlzFast() const override { return true; }
62
63 bool hasBitTest(SDValue X, SDValue Y) const override;
64
65 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
66
67 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
68
69 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
70
71 /// Return true if an FMA operation is faster than a pair of mul and add
72 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
73 /// method returns true (and FMAs are legal), otherwise fmuladd is
74 /// expanded to mul + add.
75 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &,
76 EVT) const override;
77
78 // Should we expand the build vector with shuffles?
79 bool shouldExpandBuildVectorWithShuffles(EVT VT,
80 unsigned DefinedValues) const override;
81 ExtractSubvectorCost getExtractSubvectorCost(EVT ResVT, EVT SrcVT,
82 unsigned Index) const override;
83
84 bool isTargetCanonicalConstantNode(SDValue Op) const override;
85
86 bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
87 LegalizeTypeAction getPreferredVectorAction(MVT VT) const override;
88 LegalizeAction getCustomOperationAction(SDNode &Op) const override;
89
90 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
91 void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
92 SelectionDAG &DAG) const override;
93 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
94 SelectionDAG &DAG) const override;
95
96 std::pair<MVT, unsigned>
97 handleMaskRegisterForCallingConv(const HexagonSubtarget &Subtarget,
98 EVT VT) const;
99
100 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
101 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
102 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
103 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
104 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
105 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
106 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
110 SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const;
112 SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const;
113 SDValue LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const;
114 SDValue LowerUAddSubOCarry(SDValue Op, SelectionDAG &DAG) const;
115
116 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
117 SDValue LowerFMINFMAX(SDValue Op, SelectionDAG &DAG) const;
118 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
119 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
120 SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
122 SDValue
123 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
124 const SmallVectorImpl<ISD::InputArg> &Ins,
125 const SDLoc &dl, SelectionDAG &DAG,
126 SmallVectorImpl<SDValue> &InVals) const override;
127 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
131 SelectionDAG &DAG) const;
132 SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
133 SelectionDAG &DAG) const;
134 SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
135 SelectionDAG &DAG) const;
136 SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
137 GlobalAddressSDNode *GA, SDValue InGlue, EVT PtrVT,
138 unsigned ReturnReg, unsigned char OperandGlues) const;
139 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
140
141 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
142 SmallVectorImpl<SDValue> &InVals) const override;
143 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
144 CallingConv::ID CallConv, bool isVarArg,
145 const SmallVectorImpl<ISD::InputArg> &Ins,
146 const SDLoc &dl, SelectionDAG &DAG,
147 SmallVectorImpl<SDValue> &InVals,
148 const SmallVectorImpl<SDValue> &OutVals,
149 SDValue Callee) const;
150
151 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
152 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
153 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
154 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
155 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
156
157 bool CanLowerReturn(CallingConv::ID CallConv,
158 MachineFunction &MF, bool isVarArg,
159 const SmallVectorImpl<ISD::OutputArg> &Outs,
160 LLVMContext &Context, const Type *RetTy) const override;
161
162 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
163 const SmallVectorImpl<ISD::OutputArg> &Outs,
164 const SmallVectorImpl<SDValue> &OutVals,
165 const SDLoc &dl, SelectionDAG &DAG) const override;
166
167 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
168
169 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
170
171 Register getRegisterByName(const char* RegName, LLT VT,
172 const MachineFunction &MF) const override;
173
174 unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context,
175 CallingConv::ID CC, EVT VT,
176 EVT &IntermediateVT,
177 unsigned &NumIntermediates,
178 MVT &RegisterVT) const override;
179
180 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
181 EVT VT) const override;
182 /// If a physical register, this returns the register that receives the
183 /// exception address on entry to an EH pad.
184 Register
185 getExceptionPointerRegister(ExceptionHandling EH,
186 const Constant *PersonalityFn) const override {
187 return Hexagon::R0;
188 }
189
190 /// If a physical register, this returns the register that receives the
191 /// exception typeid on entry to a landing pad.
192 Register
193 getExceptionSelectorRegister(ExceptionHandling EH,
194 const Constant *PersonalityFn) const override {
195 return Hexagon::R1;
196 }
197
198 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
199 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
200 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
201 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
202
203 EVT getSetCCResultType(const DataLayout &, LLVMContext &C,
204 EVT VT) const override {
205 if (!VT.isVector())
206 return MVT::i1;
207 else
208 return EVT::getVectorVT(Context&: C, VT: MVT::i1, NumElements: VT.getVectorNumElements());
209 }
210
211 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
212 SDValue &Base, SDValue &Offset,
213 ISD::MemIndexedMode &AM,
214 SelectionDAG &DAG) const override;
215
216 ConstraintType getConstraintType(StringRef Constraint) const override;
217
218 std::pair<unsigned, const TargetRegisterClass *>
219 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
220 StringRef Constraint, MVT VT) const override;
221
222 // Intrinsics
223 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
224 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
225 /// isLegalAddressingMode - Return true if the addressing mode represented
226 /// by AM is legal for this target, for a load/store of the specified type.
227 /// The type may be VoidTy, in which case only return true if the addressing
228 /// mode is legal for a load/store of any legal type.
229 /// TODO: Handle pre/postinc as well.
230 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
231 Type *Ty, unsigned AS,
232 Instruction *I = nullptr) const override;
233 /// Return true if folding a constant offset with the given GlobalAddress
234 /// is legal. It is frequently not legal in PIC relocation models.
235 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
236
237 bool isFPImmLegal(const APFloat &Imm, EVT VT,
238 bool ForCodeSize) const override;
239
240 /// isLegalICmpImmediate - Return true if the specified immediate is legal
241 /// icmp immediate, that is the target has icmp instructions which can
242 /// compare a register against the immediate without having to materialize
243 /// the immediate into a register.
244 bool isLegalICmpImmediate(int64_t Imm) const override;
245
246 EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,
247 const AttributeList &FuncAttributes) const override;
248
249 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
250 unsigned AddrSpace, Align Alignment,
251 MachineMemOperand::Flags Flags,
252 unsigned *Fast) const override;
253
254 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
255 Align Alignment,
256 MachineMemOperand::Flags Flags,
257 unsigned *Fast) const override;
258
259 /// Returns relocation base for the given PIC jumptable.
260 SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG)
261 const override;
262
263 /// Returns true if it is beneficial to convert a load of a constant
264 /// to just the constant itself.
265 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
266 Type *Ty) const override;
267
268 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
269 std::optional<unsigned> ByteOffset) const override;
270
271 void AdjustInstrPostInstrSelection(MachineInstr &MI,
272 SDNode *Node) const override;
273
274 // Handling of atomic RMW instructions.
275 Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr,
276 AtomicOrdering Ord) const override;
277 Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr,
278 AtomicOrdering Ord) const override;
279 AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
280 AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
281 AtomicExpansionKind
282 shouldExpandAtomicCmpXchgInIR(const AtomicCmpXchgInst *AI) const override;
283
284 AtomicExpansionKind
285 shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const override {
286 return AtomicExpansionKind::LLSC;
287 }
288
289 MachineBasicBlock *
290 EmitInstrWithCustomInserter(MachineInstr &MI,
291 MachineBasicBlock *BB) const override;
292
293 bool supportKCFIBundles() const override { return true; }
294
295 MachineInstr *EmitKCFICheck(MachineBasicBlock &MBB,
296 MachineBasicBlock::instr_iterator &MBBI,
297 const TargetInstrInfo *TII) const override;
298
299 bool hasInlineStackProbe(const MachineFunction &MF) const override;
300 unsigned getStackProbeSize(const MachineFunction &MF, Align StackAlign) const;
301
302private:
303 void initializeHVXLowering();
304 unsigned getPreferredHvxVectorAction(MVT VecTy) const;
305 unsigned getCustomHvxOperationAction(SDNode &Op) const;
306
307 bool validateConstPtrAlignment(SDValue Ptr, Align NeedAlign, const SDLoc &dl,
308 SelectionDAG &DAG) const;
309 SDValue replaceMemWithUndef(SDValue Op, SelectionDAG &DAG) const;
310
311 std::pair<SDValue,int> getBaseAndOffset(SDValue Addr) const;
312
313 bool getBuildVectorConstInts(ArrayRef<SDValue> Values, MVT VecTy,
314 SelectionDAG &DAG,
315 MutableArrayRef<ConstantInt*> Consts) const;
316 SDValue buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
317 SelectionDAG &DAG) const;
318 SDValue buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
319 SelectionDAG &DAG) const;
320 SDValue extractVector(SDValue VecV, SDValue IdxV, const SDLoc &dl,
321 MVT ValTy, MVT ResTy, SelectionDAG &DAG) const;
322 SDValue extractVectorPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
323 MVT ValTy, MVT ResTy, SelectionDAG &DAG) const;
324 SDValue insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
325 const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const;
326 SDValue insertVectorPred(SDValue VecV, SDValue ValV, SDValue IdxV,
327 const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const;
328 SDValue expandPredicate(SDValue Vec32, const SDLoc &dl,
329 SelectionDAG &DAG) const;
330 SDValue contractPredicate(SDValue Vec64, const SDLoc &dl,
331 SelectionDAG &DAG) const;
332 SDValue getSplatValue(SDValue Op, SelectionDAG &DAG) const;
333 SDValue getVectorShiftByInt(SDValue Op, SelectionDAG &DAG) const;
334 SDValue appendUndef(SDValue Val, MVT ResTy, SelectionDAG &DAG) const;
335 SDValue getCombine(SDValue Hi, SDValue Lo, const SDLoc &dl, MVT ResTy,
336 SelectionDAG &DAG) const;
337
338 bool isUndef(SDValue Op) const {
339 if (Op.isMachineOpcode())
340 return Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
341 return Op.getOpcode() == ISD::UNDEF;
342 }
343 SDValue getInstr(unsigned MachineOpc, const SDLoc &dl, MVT Ty,
344 ArrayRef<SDValue> Ops, SelectionDAG &DAG) const {
345 SDNode *N = DAG.getMachineNode(Opcode: MachineOpc, dl, VT: Ty, Ops);
346 return SDValue(N, 0);
347 }
348 SDValue getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG) const;
349
350 using VectorPair = std::pair<SDValue, SDValue>;
351 using TypePair = std::pair<MVT, MVT>;
352
353 SDValue getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
354 const SDLoc &dl, SelectionDAG &DAG) const;
355
356 MVT ty(SDValue Op) const {
357 return Op.getValueType().getSimpleVT();
358 }
359 TypePair ty(const VectorPair &Ops) const {
360 return { Ops.first.getValueType().getSimpleVT(),
361 Ops.second.getValueType().getSimpleVT() };
362 }
363 MVT tyScalar(MVT Ty) const {
364 if (!Ty.isVector())
365 return Ty;
366 return MVT::getIntegerVT(BitWidth: Ty.getSizeInBits());
367 }
368 MVT tyVector(MVT Ty, MVT ElemTy) const {
369 if (Ty.isVectorOf(EltVT: ElemTy))
370 return Ty;
371 unsigned TyWidth = Ty.getSizeInBits();
372 unsigned ElemWidth = ElemTy.getSizeInBits();
373 assert((TyWidth % ElemWidth) == 0);
374 return MVT::getVectorVT(VT: ElemTy, NumElements: TyWidth/ElemWidth);
375 }
376
377 MVT typeJoin(const TypePair &Tys) const;
378 TypePair typeSplit(MVT Ty) const;
379 MVT typeExtElem(MVT VecTy, unsigned Factor) const;
380 MVT typeTruncElem(MVT VecTy, unsigned Factor) const;
381 TypePair typeExtendToWider(MVT Ty0, MVT Ty1) const;
382 TypePair typeWidenToWider(MVT Ty0, MVT Ty1) const;
383 MVT typeLegalize(MVT Ty, SelectionDAG &DAG) const;
384 MVT typeWidenToHvx(MVT Ty) const;
385
386 SDValue opJoin(const VectorPair &Ops, const SDLoc &dl,
387 SelectionDAG &DAG) const;
388 VectorPair opSplit(SDValue Vec, const SDLoc &dl, SelectionDAG &DAG) const;
389 SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG) const;
390
391 SDValue LoHalf(SDValue V, SelectionDAG &DAG) const {
392 MVT Ty = ty(Op: V);
393 const SDLoc &dl(V);
394 if (!Ty.isVector()) {
395 assert(Ty.getSizeInBits() == 64);
396 return DAG.getTargetExtractSubreg(SRIdx: Hexagon::isub_lo, DL: dl, VT: MVT::i32, Operand: V);
397 }
398 MVT HalfTy = typeSplit(Ty).first;
399 SDValue Idx = getZero(dl, Ty: MVT::i32, DAG);
400 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: HalfTy, N1: V, N2: Idx);
401 }
402 SDValue HiHalf(SDValue V, SelectionDAG &DAG) const {
403 MVT Ty = ty(Op: V);
404 const SDLoc &dl(V);
405 if (!Ty.isVector()) {
406 assert(Ty.getSizeInBits() == 64);
407 return DAG.getTargetExtractSubreg(SRIdx: Hexagon::isub_hi, DL: dl, VT: MVT::i32, Operand: V);
408 }
409 MVT HalfTy = typeSplit(Ty).first;
410 SDValue Idx = DAG.getConstant(Val: HalfTy.getVectorNumElements(), DL: dl, VT: MVT::i32);
411 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: HalfTy, N1: V, N2: Idx);
412 }
413
414 bool allowsHvxMemoryAccess(MVT VecTy, MachineMemOperand::Flags Flags,
415 unsigned *Fast) const;
416 bool allowsHvxMisalignedMemoryAccesses(MVT VecTy,
417 MachineMemOperand::Flags Flags,
418 unsigned *Fast) const;
419 void AdjustHvxInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const;
420
421 bool isHvxSingleTy(MVT Ty) const;
422 bool isHvxPairTy(MVT Ty) const;
423 bool isHvxBoolTy(MVT Ty) const;
424 SDValue convertToByteIndex(SDValue ElemIdx, MVT ElemTy,
425 SelectionDAG &DAG) const;
426 SDValue getIndexInWord32(SDValue Idx, MVT ElemTy, SelectionDAG &DAG) const;
427 SDValue getByteShuffle(const SDLoc &dl, SDValue Op0, SDValue Op1,
428 ArrayRef<int> Mask, SelectionDAG &DAG) const;
429
430 SDValue buildHvxVectorReg(ArrayRef<SDValue> Values, const SDLoc &dl,
431 MVT VecTy, SelectionDAG &DAG) const;
432 SDValue buildHvxVectorPred(ArrayRef<SDValue> Values, const SDLoc &dl,
433 MVT VecTy, SelectionDAG &DAG) const;
434 SDValue createHvxPrefixPred(SDValue PredV, const SDLoc &dl,
435 unsigned BitBytes, bool ZeroFill,
436 SelectionDAG &DAG) const;
437 SDValue extractHvxElementReg(SDValue VecV, SDValue IdxV, const SDLoc &dl,
438 MVT ResTy, SelectionDAG &DAG) const;
439 SDValue extractHvxElementPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
440 MVT ResTy, SelectionDAG &DAG) const;
441 SDValue insertHvxElementReg(SDValue VecV, SDValue IdxV, SDValue ValV,
442 const SDLoc &dl, SelectionDAG &DAG) const;
443 SDValue insertHvxElementPred(SDValue VecV, SDValue IdxV, SDValue ValV,
444 const SDLoc &dl, SelectionDAG &DAG) const;
445 SDValue extractHvxSubvectorReg(SDValue OrigOp, SDValue VecV, SDValue IdxV,
446 const SDLoc &dl, MVT ResTy, SelectionDAG &DAG)
447 const;
448 SDValue extractHvxSubvectorPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
449 MVT ResTy, SelectionDAG &DAG) const;
450 SDValue insertHvxSubvectorReg(SDValue VecV, SDValue SubV, SDValue IdxV,
451 const SDLoc &dl, SelectionDAG &DAG) const;
452 SDValue insertHvxSubvectorPred(SDValue VecV, SDValue SubV, SDValue IdxV,
453 const SDLoc &dl, SelectionDAG &DAG) const;
454 SDValue extendHvxVectorPred(SDValue VecV, const SDLoc &dl, MVT ResTy,
455 bool ZeroExt, SelectionDAG &DAG) const;
456 SDValue compressHvxPred(SDValue VecQ, const SDLoc &dl, MVT ResTy,
457 SelectionDAG &DAG) const;
458 SDValue resizeToWidth(SDValue VecV, MVT ResTy, bool Signed, const SDLoc &dl,
459 SelectionDAG &DAG) const;
460 SDValue extractSubvector(SDValue Vec, MVT SubTy, unsigned SubIdx,
461 SelectionDAG &DAG) const;
462 VectorPair emitHvxAddWithOverflow(SDValue A, SDValue B, const SDLoc &dl,
463 bool Signed, SelectionDAG &DAG) const;
464 VectorPair emitHvxShiftRightRnd(SDValue Val, unsigned Amt, bool Signed,
465 SelectionDAG &DAG) const;
466 SDValue emitHvxMulHsV60(SDValue A, SDValue B, const SDLoc &dl,
467 SelectionDAG &DAG) const;
468 SDValue emitHvxMulLoHiV60(SDValue A, bool SignedA, SDValue B, bool SignedB,
469 const SDLoc &dl, SelectionDAG &DAG) const;
470 SDValue emitHvxMulLoHiV62(SDValue A, bool SignedA, SDValue B, bool SignedB,
471 const SDLoc &dl, SelectionDAG &DAG) const;
472
473 SDValue LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) const;
474 SDValue LowerHvxSplatVector(SDValue Op, SelectionDAG &DAG) const;
475 SDValue LowerHvxConcatVectors(SDValue Op, SelectionDAG &DAG) const;
476 SDValue LowerHvxExtractElement(SDValue Op, SelectionDAG &DAG) const;
477 SDValue LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) const;
478 SDValue LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG) const;
479 SDValue LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG) const;
480 SDValue LowerHvxBitcast(SDValue Op, SelectionDAG &DAG) const;
481 SDValue LowerHvxAnyExt(SDValue Op, SelectionDAG &DAG) const;
482 SDValue LowerHvxSignExt(SDValue Op, SelectionDAG &DAG) const;
483 SDValue LowerHvxZeroExt(SDValue Op, SelectionDAG &DAG) const;
484 SDValue LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const;
485 SDValue LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const;
486 SDValue LowerHvxMulLoHi(SDValue Op, SelectionDAG &DAG) const;
487 SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const;
488 SDValue LowerHvxSelect(SDValue Op, SelectionDAG &DAG) const;
489 SDValue LowerHvxShift(SDValue Op, SelectionDAG &DAG) const;
490 SDValue LowerHvxFunnelShift(SDValue Op, SelectionDAG &DAG) const;
491 SDValue LowerHvxIntrinsic(SDValue Op, SelectionDAG &DAG) const;
492 SDValue LowerHvxMaskedOp(SDValue Op, SelectionDAG &DAG) const;
493 SDValue LowerHvxFpExtend(SDValue Op, SelectionDAG &DAG) const;
494 SDValue LowerHvxFpToInt(SDValue Op, SelectionDAG &DAG) const;
495 SDValue LowerHvxIntToFp(SDValue Op, SelectionDAG &DAG) const;
496 SDValue LowerHvxPred32ToFp(SDValue Op, SelectionDAG &DAG) const;
497 SDValue LowerHvxPred64ToFp(SDValue Op, SelectionDAG &DAG) const;
498 SDValue LowerHvxPartialReduceMLA(SDValue Op, SelectionDAG &DAG) const;
499 SDValue LowerHvxFpSetoeq(SDValue Op, SelectionDAG &DAG) const;
500 SDValue LowerHvxVecReduceFMinMax(SDValue Op, unsigned PairwiseOpc,
501 bool IgnoreNaN, SelectionDAG &DAG) const;
502 SDValue LowerHvxVecReduceFMin(SDValue Op, SelectionDAG &DAG) const;
503 SDValue LowerHvxVecReduceFMax(SDValue Op, SelectionDAG &DAG) const;
504 SDValue LowerHvxVecReduceFMinimum(SDValue Op, SelectionDAG &DAG) const;
505 SDValue LowerHvxVecReduceFMaximum(SDValue Op, SelectionDAG &DAG) const;
506 SDValue LowerHvxFMinNum(SDValue Op, SelectionDAG &DAG) const;
507 SDValue LowerHvxFMaxNum(SDValue Op, SelectionDAG &DAG) const;
508 SDValue ExpandHvxFpToInt(SDValue Op, SelectionDAG &DAG) const;
509 SDValue ExpandHvxIntToFp(SDValue Op, SelectionDAG &DAG) const;
510 SDValue LowerHvxStore(SDValue Op, SelectionDAG &DAG) const;
511 SDValue LowerHvxLoad(SDValue Op, SelectionDAG &DAG) const;
512
513 VectorPair SplitVectorOp(SDValue Op, SelectionDAG &DAG) const;
514
515 SDValue SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const;
516 SDValue WidenHvxLoad(SDValue Op, SelectionDAG &DAG) const;
517 SDValue WidenHvxStore(SDValue Op, SelectionDAG &DAG) const;
518 SDValue WidenHvxSetCC(SDValue Op, SelectionDAG &DAG) const;
519 SDValue LegalizeHvxResize(SDValue Op, SelectionDAG &DAG) const;
520 SDValue ExpandHvxResizeIntoSteps(SDValue Op, SelectionDAG &DAG) const;
521 SDValue EqualizeFpIntConversion(SDValue Op, SelectionDAG &DAG) const;
522
523 SDValue CreateTLWrapper(SDValue Op, SelectionDAG &DAG) const;
524 SDValue RemoveTLWrapper(SDValue Op, SelectionDAG &DAG) const;
525 SDValue WidenHvxTruncateToBool(SDValue Op, SelectionDAG &DAG) const;
526
527 std::pair<const TargetRegisterClass*, uint8_t>
528 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
529 const override;
530
531 bool shouldSplitToHvx(MVT Ty, SelectionDAG &DAG) const;
532 bool shouldWidenToHvx(MVT Ty, SelectionDAG &DAG) const;
533 bool isHvxOperation(SDNode *N, SelectionDAG &DAG) const;
534 SDValue LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const;
535 void LowerHvxOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
536 SelectionDAG &DAG) const;
537 void ReplaceHvxNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
538 SelectionDAG &DAG) const;
539
540 SDValue combineTruncateBeforeLegal(SDValue Op, DAGCombinerInfo &DCI) const;
541
542 SDValue combineConcatOfShuffles(SDValue Op, SelectionDAG &DAG) const;
543 SDValue combineConcatOfScalarPreds(SDValue Op, unsigned BitBytes,
544 SelectionDAG &DAG) const;
545 SDValue combineConcatVectorsBeforeLegal(SDValue Op, DAGCombinerInfo & DCI)
546 const;
547 SDValue expandVecReduceAdd(SDNode *N, SelectionDAG &DAG) const;
548 SDValue createExtendingPartialReduceMLA(
549 unsigned Opcode, EVT AccEltType, unsigned AccNumElements, EVT InputType,
550 const SDValue &A, const SDValue &B, unsigned &RemainingReductionRatio,
551 const SDLoc &DL, SelectionDAG &DAG) const;
552 SDValue splitVecReduceAdd(SDNode *N, SelectionDAG &DAG) const;
553 SDValue splitExtendingPartialReduceMLA(SDNode *N, SelectionDAG &DAG) const;
554 SDValue PerformHvxDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
555};
556
557} // end namespace llvm
558
559#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
560