1//===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that Hexagon uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
15#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16
17#include "Hexagon.h"
18#include "MCTargetDesc/HexagonMCTargetDesc.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/CodeGen/ISDOpcodes.h"
21#include "llvm/CodeGen/SelectionDAGNodes.h"
22#include "llvm/CodeGen/TargetLowering.h"
23#include "llvm/CodeGen/ValueTypes.h"
24#include "llvm/CodeGenTypes/MachineValueType.h"
25#include "llvm/IR/CallingConv.h"
26#include "llvm/IR/InlineAsm.h"
27#include <cstdint>
28#include <utility>
29
30namespace llvm {
31
32class HexagonSubtarget;
33
34class HexagonTargetLowering : public TargetLowering {
35 int VarArgsFrameOffset; // Frame offset to start of varargs area.
36 const HexagonTargetMachine &HTM;
37 const HexagonSubtarget &Subtarget;
38
39public:
40 explicit HexagonTargetLowering(const TargetMachine &TM,
41 const HexagonSubtarget &ST);
42
43 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
44 /// for tail call optimization. Targets which want to do tail call
45 /// optimization should implement this function.
46 bool IsEligibleForTailCallOptimization(SDValue Callee,
47 CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
48 bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
49 const SmallVectorImpl<SDValue> &OutVals,
50 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
51
52 void getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos,
53 const CallBase &I, MachineFunction &MF,
54 unsigned Intrinsic) const override;
55
56 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
57 bool isTruncateFree(EVT VT1, EVT VT2) const override;
58
59 bool isCheapToSpeculateCttz(Type *) const override { return true; }
60 bool isCheapToSpeculateCtlz(Type *) const override { return true; }
61 bool isCtlzFast() const override { return true; }
62
63 bool hasBitTest(SDValue X, SDValue Y) const override;
64
65 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
66
67 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
68
69 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
70
71 /// Return true if an FMA operation is faster than a pair of mul and add
72 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
73 /// method returns true (and FMAs are legal), otherwise fmuladd is
74 /// expanded to mul + add.
75 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &,
76 EVT) const override;
77
78 // Should we expand the build vector with shuffles?
79 bool shouldExpandBuildVectorWithShuffles(EVT VT,
80 unsigned DefinedValues) const override;
81 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
82 unsigned Index) const override;
83
84 bool isTargetCanonicalConstantNode(SDValue Op) const override;
85
86 bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
87 LegalizeTypeAction getPreferredVectorAction(MVT VT) const override;
88 LegalizeAction getCustomOperationAction(SDNode &Op) const override;
89
90 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
91 void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
92 SelectionDAG &DAG) const override;
93 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
94 SelectionDAG &DAG) const override;
95
96 std::pair<MVT, unsigned>
97 handleMaskRegisterForCallingConv(const HexagonSubtarget &Subtarget,
98 EVT VT) const;
99
100 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
101 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
102 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
103 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
104 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
105 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
106 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
110 SDValue LowerANY_EXTEND(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
112 SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
113 SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const;
114 SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const;
115 SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const;
116 SDValue LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const;
117 SDValue LowerUAddSubOCarry(SDValue Op, SelectionDAG &DAG) const;
118
119 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
120 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
121 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
122 SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
125 SDValue
126 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
127 const SmallVectorImpl<ISD::InputArg> &Ins,
128 const SDLoc &dl, SelectionDAG &DAG,
129 SmallVectorImpl<SDValue> &InVals) const override;
130 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
134 SelectionDAG &DAG) const;
135 SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
136 SelectionDAG &DAG) const;
137 SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
138 SelectionDAG &DAG) const;
139 SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
140 GlobalAddressSDNode *GA, SDValue InGlue, EVT PtrVT,
141 unsigned ReturnReg, unsigned char OperandGlues) const;
142 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
143
144 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
145 SmallVectorImpl<SDValue> &InVals) const override;
146 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
147 CallingConv::ID CallConv, bool isVarArg,
148 const SmallVectorImpl<ISD::InputArg> &Ins,
149 const SDLoc &dl, SelectionDAG &DAG,
150 SmallVectorImpl<SDValue> &InVals,
151 const SmallVectorImpl<SDValue> &OutVals,
152 SDValue Callee) const;
153
154 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
155 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
158 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
159
160 bool CanLowerReturn(CallingConv::ID CallConv,
161 MachineFunction &MF, bool isVarArg,
162 const SmallVectorImpl<ISD::OutputArg> &Outs,
163 LLVMContext &Context, const Type *RetTy) const override;
164
165 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
166 const SmallVectorImpl<ISD::OutputArg> &Outs,
167 const SmallVectorImpl<SDValue> &OutVals,
168 const SDLoc &dl, SelectionDAG &DAG) const override;
169
170 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
171
172 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
173
174 Register getRegisterByName(const char* RegName, LLT VT,
175 const MachineFunction &MF) const override;
176
177 unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context,
178 CallingConv::ID CC, EVT VT,
179 EVT &IntermediateVT,
180 unsigned &NumIntermediates,
181 MVT &RegisterVT) const override;
182
183 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
184 EVT VT) const override;
185 /// If a physical register, this returns the register that receives the
186 /// exception address on entry to an EH pad.
187 Register
188 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
189 return Hexagon::R0;
190 }
191
192 /// If a physical register, this returns the register that receives the
193 /// exception typeid on entry to a landing pad.
194 Register
195 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
196 return Hexagon::R1;
197 }
198
199 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
200 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
201 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
202 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
203
204 EVT getSetCCResultType(const DataLayout &, LLVMContext &C,
205 EVT VT) const override {
206 if (!VT.isVector())
207 return MVT::i1;
208 else
209 return EVT::getVectorVT(Context&: C, VT: MVT::i1, NumElements: VT.getVectorNumElements());
210 }
211
212 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
213 SDValue &Base, SDValue &Offset,
214 ISD::MemIndexedMode &AM,
215 SelectionDAG &DAG) const override;
216
217 ConstraintType getConstraintType(StringRef Constraint) const override;
218
219 std::pair<unsigned, const TargetRegisterClass *>
220 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
221 StringRef Constraint, MVT VT) const override;
222
223 // Intrinsics
224 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
225 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
226 /// isLegalAddressingMode - Return true if the addressing mode represented
227 /// by AM is legal for this target, for a load/store of the specified type.
228 /// The type may be VoidTy, in which case only return true if the addressing
229 /// mode is legal for a load/store of any legal type.
230 /// TODO: Handle pre/postinc as well.
231 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
232 Type *Ty, unsigned AS,
233 Instruction *I = nullptr) const override;
234 /// Return true if folding a constant offset with the given GlobalAddress
235 /// is legal. It is frequently not legal in PIC relocation models.
236 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
237
238 bool isFPImmLegal(const APFloat &Imm, EVT VT,
239 bool ForCodeSize) const override;
240
241 /// isLegalICmpImmediate - Return true if the specified immediate is legal
242 /// icmp immediate, that is the target has icmp instructions which can
243 /// compare a register against the immediate without having to materialize
244 /// the immediate into a register.
245 bool isLegalICmpImmediate(int64_t Imm) const override;
246
247 EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,
248 const AttributeList &FuncAttributes) const override;
249
250 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
251 unsigned AddrSpace, Align Alignment,
252 MachineMemOperand::Flags Flags,
253 unsigned *Fast) const override;
254
255 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
256 Align Alignment,
257 MachineMemOperand::Flags Flags,
258 unsigned *Fast) const override;
259
260 /// Returns relocation base for the given PIC jumptable.
261 SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG)
262 const override;
263
264 /// Returns true if it is beneficial to convert a load of a constant
265 /// to just the constant itself.
266 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
267 Type *Ty) const override;
268
269 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
270 std::optional<unsigned> ByteOffset) const override;
271
272 void AdjustInstrPostInstrSelection(MachineInstr &MI,
273 SDNode *Node) const override;
274
275 // Handling of atomic RMW instructions.
276 Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr,
277 AtomicOrdering Ord) const override;
278 Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr,
279 AtomicOrdering Ord) const override;
280 AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
281 AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
282 AtomicExpansionKind
283 shouldExpandAtomicCmpXchgInIR(const AtomicCmpXchgInst *AI) const override;
284
285 AtomicExpansionKind
286 shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const override {
287 return AtomicExpansionKind::LLSC;
288 }
289
290private:
291 void initializeHVXLowering();
292 unsigned getPreferredHvxVectorAction(MVT VecTy) const;
293 unsigned getCustomHvxOperationAction(SDNode &Op) const;
294
295 bool validateConstPtrAlignment(SDValue Ptr, Align NeedAlign, const SDLoc &dl,
296 SelectionDAG &DAG) const;
297 SDValue replaceMemWithUndef(SDValue Op, SelectionDAG &DAG) const;
298
299 std::pair<SDValue,int> getBaseAndOffset(SDValue Addr) const;
300
301 bool getBuildVectorConstInts(ArrayRef<SDValue> Values, MVT VecTy,
302 SelectionDAG &DAG,
303 MutableArrayRef<ConstantInt*> Consts) const;
304 SDValue buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
305 SelectionDAG &DAG) const;
306 SDValue buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
307 SelectionDAG &DAG) const;
308 SDValue extractVector(SDValue VecV, SDValue IdxV, const SDLoc &dl,
309 MVT ValTy, MVT ResTy, SelectionDAG &DAG) const;
310 SDValue extractVectorPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
311 MVT ValTy, MVT ResTy, SelectionDAG &DAG) const;
312 SDValue insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
313 const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const;
314 SDValue insertVectorPred(SDValue VecV, SDValue ValV, SDValue IdxV,
315 const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const;
316 SDValue expandPredicate(SDValue Vec32, const SDLoc &dl,
317 SelectionDAG &DAG) const;
318 SDValue contractPredicate(SDValue Vec64, const SDLoc &dl,
319 SelectionDAG &DAG) const;
320 SDValue getSplatValue(SDValue Op, SelectionDAG &DAG) const;
321 SDValue getVectorShiftByInt(SDValue Op, SelectionDAG &DAG) const;
322 SDValue appendUndef(SDValue Val, MVT ResTy, SelectionDAG &DAG) const;
323 SDValue getCombine(SDValue Hi, SDValue Lo, const SDLoc &dl, MVT ResTy,
324 SelectionDAG &DAG) const;
325
326 bool isUndef(SDValue Op) const {
327 if (Op.isMachineOpcode())
328 return Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
329 return Op.getOpcode() == ISD::UNDEF;
330 }
331 SDValue getInstr(unsigned MachineOpc, const SDLoc &dl, MVT Ty,
332 ArrayRef<SDValue> Ops, SelectionDAG &DAG) const {
333 SDNode *N = DAG.getMachineNode(Opcode: MachineOpc, dl, VT: Ty, Ops);
334 return SDValue(N, 0);
335 }
336 SDValue getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG) const;
337
338 using VectorPair = std::pair<SDValue, SDValue>;
339 using TypePair = std::pair<MVT, MVT>;
340
341 SDValue getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
342 const SDLoc &dl, SelectionDAG &DAG) const;
343
344 MVT ty(SDValue Op) const {
345 return Op.getValueType().getSimpleVT();
346 }
347 TypePair ty(const VectorPair &Ops) const {
348 return { Ops.first.getValueType().getSimpleVT(),
349 Ops.second.getValueType().getSimpleVT() };
350 }
351 MVT tyScalar(MVT Ty) const {
352 if (!Ty.isVector())
353 return Ty;
354 return MVT::getIntegerVT(BitWidth: Ty.getSizeInBits());
355 }
356 MVT tyVector(MVT Ty, MVT ElemTy) const {
357 if (Ty.isVector() && Ty.getVectorElementType() == ElemTy)
358 return Ty;
359 unsigned TyWidth = Ty.getSizeInBits();
360 unsigned ElemWidth = ElemTy.getSizeInBits();
361 assert((TyWidth % ElemWidth) == 0);
362 return MVT::getVectorVT(VT: ElemTy, NumElements: TyWidth/ElemWidth);
363 }
364
365 MVT typeJoin(const TypePair &Tys) const;
366 TypePair typeSplit(MVT Ty) const;
367 MVT typeExtElem(MVT VecTy, unsigned Factor) const;
368 MVT typeTruncElem(MVT VecTy, unsigned Factor) const;
369 TypePair typeExtendToWider(MVT Ty0, MVT Ty1) const;
370 TypePair typeWidenToWider(MVT Ty0, MVT Ty1) const;
371 MVT typeLegalize(MVT Ty, SelectionDAG &DAG) const;
372 MVT typeWidenToHvx(MVT Ty) const;
373
374 SDValue opJoin(const VectorPair &Ops, const SDLoc &dl,
375 SelectionDAG &DAG) const;
376 VectorPair opSplit(SDValue Vec, const SDLoc &dl, SelectionDAG &DAG) const;
377 SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG) const;
378
379 SDValue LoHalf(SDValue V, SelectionDAG &DAG) const {
380 MVT Ty = ty(Op: V);
381 const SDLoc &dl(V);
382 if (!Ty.isVector()) {
383 assert(Ty.getSizeInBits() == 64);
384 return DAG.getTargetExtractSubreg(SRIdx: Hexagon::isub_lo, DL: dl, VT: MVT::i32, Operand: V);
385 }
386 MVT HalfTy = typeSplit(Ty).first;
387 SDValue Idx = getZero(dl, Ty: MVT::i32, DAG);
388 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: HalfTy, N1: V, N2: Idx);
389 }
390 SDValue HiHalf(SDValue V, SelectionDAG &DAG) const {
391 MVT Ty = ty(Op: V);
392 const SDLoc &dl(V);
393 if (!Ty.isVector()) {
394 assert(Ty.getSizeInBits() == 64);
395 return DAG.getTargetExtractSubreg(SRIdx: Hexagon::isub_hi, DL: dl, VT: MVT::i32, Operand: V);
396 }
397 MVT HalfTy = typeSplit(Ty).first;
398 SDValue Idx = DAG.getConstant(Val: HalfTy.getVectorNumElements(), DL: dl, VT: MVT::i32);
399 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL: dl, VT: HalfTy, N1: V, N2: Idx);
400 }
401
402 bool allowsHvxMemoryAccess(MVT VecTy, MachineMemOperand::Flags Flags,
403 unsigned *Fast) const;
404 bool allowsHvxMisalignedMemoryAccesses(MVT VecTy,
405 MachineMemOperand::Flags Flags,
406 unsigned *Fast) const;
407 void AdjustHvxInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const;
408
409 bool isHvxSingleTy(MVT Ty) const;
410 bool isHvxPairTy(MVT Ty) const;
411 bool isHvxBoolTy(MVT Ty) const;
412 SDValue convertToByteIndex(SDValue ElemIdx, MVT ElemTy,
413 SelectionDAG &DAG) const;
414 SDValue getIndexInWord32(SDValue Idx, MVT ElemTy, SelectionDAG &DAG) const;
415 SDValue getByteShuffle(const SDLoc &dl, SDValue Op0, SDValue Op1,
416 ArrayRef<int> Mask, SelectionDAG &DAG) const;
417
418 SDValue buildHvxVectorReg(ArrayRef<SDValue> Values, const SDLoc &dl,
419 MVT VecTy, SelectionDAG &DAG) const;
420 SDValue buildHvxVectorPred(ArrayRef<SDValue> Values, const SDLoc &dl,
421 MVT VecTy, SelectionDAG &DAG) const;
422 SDValue createHvxPrefixPred(SDValue PredV, const SDLoc &dl,
423 unsigned BitBytes, bool ZeroFill,
424 SelectionDAG &DAG) const;
425 SDValue extractHvxElementReg(SDValue VecV, SDValue IdxV, const SDLoc &dl,
426 MVT ResTy, SelectionDAG &DAG) const;
427 SDValue extractHvxElementPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
428 MVT ResTy, SelectionDAG &DAG) const;
429 SDValue insertHvxElementReg(SDValue VecV, SDValue IdxV, SDValue ValV,
430 const SDLoc &dl, SelectionDAG &DAG) const;
431 SDValue insertHvxElementPred(SDValue VecV, SDValue IdxV, SDValue ValV,
432 const SDLoc &dl, SelectionDAG &DAG) const;
433 SDValue extractHvxSubvectorReg(SDValue OrigOp, SDValue VecV, SDValue IdxV,
434 const SDLoc &dl, MVT ResTy, SelectionDAG &DAG)
435 const;
436 SDValue extractHvxSubvectorPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
437 MVT ResTy, SelectionDAG &DAG) const;
438 SDValue insertHvxSubvectorReg(SDValue VecV, SDValue SubV, SDValue IdxV,
439 const SDLoc &dl, SelectionDAG &DAG) const;
440 SDValue insertHvxSubvectorPred(SDValue VecV, SDValue SubV, SDValue IdxV,
441 const SDLoc &dl, SelectionDAG &DAG) const;
442 SDValue extendHvxVectorPred(SDValue VecV, const SDLoc &dl, MVT ResTy,
443 bool ZeroExt, SelectionDAG &DAG) const;
444 SDValue compressHvxPred(SDValue VecQ, const SDLoc &dl, MVT ResTy,
445 SelectionDAG &DAG) const;
446 SDValue resizeToWidth(SDValue VecV, MVT ResTy, bool Signed, const SDLoc &dl,
447 SelectionDAG &DAG) const;
448 SDValue extractSubvector(SDValue Vec, MVT SubTy, unsigned SubIdx,
449 SelectionDAG &DAG) const;
450 VectorPair emitHvxAddWithOverflow(SDValue A, SDValue B, const SDLoc &dl,
451 bool Signed, SelectionDAG &DAG) const;
452 VectorPair emitHvxShiftRightRnd(SDValue Val, unsigned Amt, bool Signed,
453 SelectionDAG &DAG) const;
454 SDValue emitHvxMulHsV60(SDValue A, SDValue B, const SDLoc &dl,
455 SelectionDAG &DAG) const;
456 SDValue emitHvxMulLoHiV60(SDValue A, bool SignedA, SDValue B, bool SignedB,
457 const SDLoc &dl, SelectionDAG &DAG) const;
458 SDValue emitHvxMulLoHiV62(SDValue A, bool SignedA, SDValue B, bool SignedB,
459 const SDLoc &dl, SelectionDAG &DAG) const;
460
461 SDValue LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) const;
462 SDValue LowerHvxSplatVector(SDValue Op, SelectionDAG &DAG) const;
463 SDValue LowerHvxConcatVectors(SDValue Op, SelectionDAG &DAG) const;
464 SDValue LowerHvxExtractElement(SDValue Op, SelectionDAG &DAG) const;
465 SDValue LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) const;
466 SDValue LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG) const;
467 SDValue LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG) const;
468 SDValue LowerHvxBitcast(SDValue Op, SelectionDAG &DAG) const;
469 SDValue LowerHvxAnyExt(SDValue Op, SelectionDAG &DAG) const;
470 SDValue LowerHvxSignExt(SDValue Op, SelectionDAG &DAG) const;
471 SDValue LowerHvxZeroExt(SDValue Op, SelectionDAG &DAG) const;
472 SDValue LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const;
473 SDValue LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const;
474 SDValue LowerHvxMulLoHi(SDValue Op, SelectionDAG &DAG) const;
475 SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const;
476 SDValue LowerHvxSelect(SDValue Op, SelectionDAG &DAG) const;
477 SDValue LowerHvxShift(SDValue Op, SelectionDAG &DAG) const;
478 SDValue LowerHvxFunnelShift(SDValue Op, SelectionDAG &DAG) const;
479 SDValue LowerHvxIntrinsic(SDValue Op, SelectionDAG &DAG) const;
480 SDValue LowerHvxMaskedOp(SDValue Op, SelectionDAG &DAG) const;
481 SDValue LowerHvxFpExtend(SDValue Op, SelectionDAG &DAG) const;
482 SDValue LowerHvxFpToInt(SDValue Op, SelectionDAG &DAG) const;
483 SDValue LowerHvxIntToFp(SDValue Op, SelectionDAG &DAG) const;
484 SDValue LowerHvxPred32ToFp(SDValue Op, SelectionDAG &DAG) const;
485 SDValue LowerHvxPred64ToFp(SDValue Op, SelectionDAG &DAG) const;
486 SDValue LowerHvxPartialReduceMLA(SDValue Op, SelectionDAG &DAG) const;
487 SDValue ExpandHvxFpToInt(SDValue Op, SelectionDAG &DAG) const;
488 SDValue ExpandHvxIntToFp(SDValue Op, SelectionDAG &DAG) const;
489 SDValue LowerHvxStore(SDValue Op, SelectionDAG &DAG) const;
490 SDValue LowerHvxLoad(SDValue Op, SelectionDAG &DAG) const;
491
492 VectorPair SplitVectorOp(SDValue Op, SelectionDAG &DAG) const;
493
494 SDValue SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const;
495 SDValue WidenHvxLoad(SDValue Op, SelectionDAG &DAG) const;
496 SDValue WidenHvxStore(SDValue Op, SelectionDAG &DAG) const;
497 SDValue WidenHvxSetCC(SDValue Op, SelectionDAG &DAG) const;
498 SDValue LegalizeHvxResize(SDValue Op, SelectionDAG &DAG) const;
499 SDValue ExpandHvxResizeIntoSteps(SDValue Op, SelectionDAG &DAG) const;
500 SDValue EqualizeFpIntConversion(SDValue Op, SelectionDAG &DAG) const;
501
502 SDValue CreateTLWrapper(SDValue Op, SelectionDAG &DAG) const;
503 SDValue RemoveTLWrapper(SDValue Op, SelectionDAG &DAG) const;
504
505 std::pair<const TargetRegisterClass*, uint8_t>
506 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
507 const override;
508
509 bool shouldSplitToHvx(MVT Ty, SelectionDAG &DAG) const;
510 bool shouldWidenToHvx(MVT Ty, SelectionDAG &DAG) const;
511 bool isHvxOperation(SDNode *N, SelectionDAG &DAG) const;
512 SDValue LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const;
513 void LowerHvxOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
514 SelectionDAG &DAG) const;
515 void ReplaceHvxNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
516 SelectionDAG &DAG) const;
517
518 SDValue combineTruncateBeforeLegal(SDValue Op, DAGCombinerInfo &DCI) const;
519
520 SDValue combineConcatOfShuffles(SDValue Op, SelectionDAG &DAG) const;
521 SDValue combineConcatOfScalarPreds(SDValue Op, unsigned BitBytes,
522 SelectionDAG &DAG) const;
523 SDValue combineConcatVectorsBeforeLegal(SDValue Op, DAGCombinerInfo & DCI)
524 const;
525 SDValue expandVecReduceAdd(SDNode *N, SelectionDAG &DAG) const;
526 SDValue createExtendingPartialReduceMLA(
527 unsigned Opcode, EVT AccEltType, unsigned AccNumElements, EVT InputType,
528 const SDValue &A, const SDValue &B, unsigned &RemainingReductionRatio,
529 const SDLoc &DL, SelectionDAG &DAG) const;
530 SDValue splitVecReduceAdd(SDNode *N, SelectionDAG &DAG) const;
531 SDValue splitExtendingPartialReduceMLA(SDNode *N, SelectionDAG &DAG) const;
532 SDValue PerformHvxDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
533};
534
535} // end namespace llvm
536
537#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
538